157 files changed, 507964 insertions, 0 deletions

diff --git a/meta-amdfalconx86/.gitignore b/meta-amdfalconx86/.gitignore
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amdfalconx86/.gitignore
diff --git a/meta-amdfalconx86/COPYING.MIT b/meta-amdfalconx86/COPYING.MIT
new file mode 100644
index 00000000..89de3547
--- /dev/null
+++ b/meta-amdfalconx86/COPYING.MIT
@@ -0,0 +1,17 @@
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
diff --git a/meta-amdfalconx86/binary/.gitignore b/meta-amdfalconx86/binary/.gitignore
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amdfalconx86/binary/.gitignore
diff --git a/meta-amdfalconx86/conf/layer.conf b/meta-amdfalconx86/conf/layer.conf
new file mode 100644
index 00000000..01b7067d
--- /dev/null
+++ b/meta-amdfalconx86/conf/layer.conf
@@ -0,0 +1,12 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have a recipes-* directories, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
+	${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "amdfalconx86"
+BBFILE_PATTERN_amdfalconx86 = "^${LAYERDIR}/"
+BBFILE_PRIORITY_amdfalconx86 = "6"
+
+LAYERDEPENDS_amdfalconx86 = "amd openembedded-layer"
diff --git a/meta-amdfalconx86/conf/machine/amdfalconx86.conf b/meta-amdfalconx86/conf/machine/amdfalconx86.conf
new file mode 100644
index 00000000..58f52c91
--- /dev/null
+++ b/meta-amdfalconx86/conf/machine/amdfalconx86.conf
@@ -0,0 +1,61 @@
+#@TYPE: Machine
+#@NAME: amdfalconx86
+
+#@DESCRIPTION: Machine configuration for amdfalconx86 systems
+
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
+PREFERRED_PROVIDER_jpeg ?= "jpeg"
+PREFERRED_PROVIDER_jpeg-native ?= "jpeg-native"
+PREFERRED_PROVIDER_llvm ?= "llvm3.7.0"
+PREFERRED_VERSION_linux-yocto ?= "3.14%"
+PREFERRED_VERSION_mesa = "10.6.0+git%"
+PREFERRED_VERSION_gstreamer1.0-omx = "git+git%"
+PREFERRED_VERSION_libav = "9.16"
+PREFERRED_VERSION_libdrm = "2.4.60+git%"
+PREFERRED_VERSION_glamor-egl = "0.6.0+git%"
+PREFERRED_VERSION_xf86-video-amdgpu = "0.0.01+git%"
+
+require conf/machine/include/tune-amdfalconx86.inc
+
+MACHINE_FEATURES += "wifi efi pcbios"
+
+XSERVER_X86_AMDGPU = "xf86-video-amdgpu \
+           ${@base_contains('DISTRO_FEATURES', 'opengl', 'mesa-driver-radeonsi', '', d)} \
+           "
+XSERVER ?= "${XSERVER_X86_BASE} \
+           ${XSERVER_X86_EXT} \
+           ${XSERVER_X86_FBDEV} \
+           ${XSERVER_X86_MODESETTING} \
+           ${XSERVER_X86_AMDGPU} \
+           "
+
+MACHINE_EXTRA_RRECOMMENDS += "kernel-modules amdgpu-firmware alsa-utils"
+MACHINE_EXTRA_RRECOMMENDS += "vdpauinfo gstreamer1.0-omx"
+MACHINE_EXTRA_RRECOMMENDS += "grub parted util-linux-blkid"
+MACHINE_EXTRA_RRECOMMENDS += "spi-test gpio-test rtc-test watchdog-test smbus-test"
+MACHINE_EXTRA_RRECOMMENDS += "kernel-module-amd-gpio kernel-module-amd-spi kernel-module-amd-wdt"
+MACHINE_EXTRA_RRECOMMENDS += "amd-gpio-load amd-wdt-load"
+
+MACHINE_EXTRA_RDEPENDS += "r8168"
+
+EXTRA_OECONF_append_pn-matchbox-panel-2 = " --with-battery=acpi"
+
+# Setup a gettys on all serial ports
+SERIAL_CONSOLES = "115200;ttyS4 115200;ttyS5 115200;ttyUSB0"
+
+# Enable the kernel console on ttyS4/COM0
+APPEND += "console=ttyS4,115200n8"
+
+# Make sure the kernel messages go to the VGA console
+APPEND += "console=tty0"
+
+RELEASE_IMAGE ?= "core-image-sato"
+
+APPEND += "amdgpu.dpm=1"
+
+# Make sure the VESA VGA driver goes up on boot, we provide a generic mode here
+# The AMD GPU driver will take over once it is up
+APPEND += "vga=802"
+
+MACHINEOVERRIDES =. "amd:"
diff --git a/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc b/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc
new file mode 100644
index 00000000..b78f0f7c
--- /dev/null
+++ b/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc
@@ -0,0 +1,18 @@
+DEFAULTTUNE ?= "dbfp4"
+
+require conf/machine/include/x86/arch-x86.inc
+require conf/machine/include/x86-base.inc
+
+
+# AMD DB-FP4 64bit (MerlinFalcon)
+TUNEVALID[dbfp4] = "Enable AMD DB-FP4 (64 bit) specific processor optimizations"
+TUNECONFLICTS[dbfp4] = "m32 mx32"
+TUNE_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "dbfp4", "${X86ARCH64}", "" ,d)}"
+TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "dbfp4", " -march=bdver4", "", d)}"
+
+# Extra tune selections
+AVAILTUNES += "dbfp4"
+TUNE_FEATURES_tune-dbfp4 = "dbfp4"
+BASE_LIB_tune-dbfp4 = "lib64"
+TUNE_PKGARCH_tune-dbfp4 = "dbfp4"
+PACKAGE_EXTRA_ARCHS_tune-dbfp4 = "${TUNE_PKGARCH_tune-dbfp4}"
diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c
new file mode 100644
index 00000000..6cd073bd
--- /dev/null
+++ b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c
@@ -0,0 +1,529 @@
+/*****************************************************************************
+*
+* Copyright (c) 2014, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+***************************************************************************/
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <errno.h>
+#include <string.h>
+
+#include <readline/readline.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <sys/ioctl.h>
+
+#include "gpio-test.h"
+
+#define GPIO_APP_VERSION	"0.2"
+#define AMD_GPIO_NUM_PINS	184
+static int gpio_in_use[AMD_GPIO_NUM_PINS];
+
+char *show_prompt(void)
+{
+	return "$ ";
+}
+
+void sighandler(int sig)
+{
+	printf("\n%s", show_prompt());
+}
+
+void show_license(void)
+{
+	printf("/*****************************************************************************\n"
+	       "*\n"
+	       "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
+	       "* All rights reserved.\n"
+	       "*\n"
+	       "* Redistribution and use in source and binary forms, with or without\n" 
+	       "* modification, are permitted provided that the following conditions are met:\n"
+	       "*     * Redistributions of source code must retain the above copyright\n"
+	       "*       notice, this list of conditions and the following disclaimer.\n"
+	       "*     * Redistributions in binary form must reproduce the above copyright\n"
+	       "*       notice, this list of conditions and the following disclaimer in the\n"
+	       "*       documentation and/or other materials provided with the distribution.\n"
+	       "*     * Neither the name of Advanced Micro Devices, Inc. nor the names of\n"
+	       "*       its contributors may be used to endorse or promote products derived\n"
+	       "*       from this software without specific prior written permission.\n"
+	       "*\n"
+	       "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n"
+	       "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n"
+	       "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n"
+	       "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n"
+	       "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n"
+	       "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n"
+	       "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n"
+	       "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n"
+	       "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n"
+	       "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
+	       "*\n"
+	       "*\n"
+	       "***************************************************************************/\n");
+}
+
+void print_usage()
+{
+	printf("\nCommands Supported ->\n");
+	printf(" getgpiomode <gpio>			: Gets the mode of GPIO pin\n");
+	printf(" setgpiomode <gpio> <in/out/high/low>	: Sets the mode of GPIO pin to input or output(high/low)\n");
+	printf(" getgpiovalue <gpio>			: Gets the value of GPIO pin\n");
+	printf(" setgpiovalue <gpio> <high/low>		: Sets the value of GPO pin to high or low\n");
+	printf(" getnumgpio				: Gets the number of GPIO pins supported\n");
+	printf(" getgpiobase				: Gets the number of first GPIO pin\n");
+	printf(" getgpioname				: Gets the name of GPIO driver currently in use\n");
+	printf(" dmesg					: Displays the kernel log messages related to GPIO\n");
+	printf(" license				: Displays the terms of LICENSE for this application\n");
+	printf(" help					: Displays help text\n");
+	printf(" exit					: Exits the application\n\n");
+}
+
+void parse_cmd(const char *cmdline)
+{
+	int fd;
+
+	if (strncmp(cmdline, "help", 4) == 0)
+		print_usage();
+	else if (strncmp(cmdline, "getnumgpio", 10) == 0) {
+		int fd;
+		char ngpio[3 + 1];
+
+		memset(ngpio, '\0', (3 + 1));
+		fd = open("/sys/class/gpio/gpiochip0/ngpio", O_RDONLY);
+		if (fd < 0) {
+			printf("\nPlease make sure AMD GPIO driver is loaded\n");
+			exit(EXIT_FAILURE);
+		}
+
+		/* Value read from the file is ASCII text */
+		if(read(fd, ngpio, 3) < 0)
+			perror("Cannot read number of GPIO pins");
+
+		printf("\nThe maximum number of GPIO pins supported is %d\n", atoi(ngpio));
+		close(fd);
+	} else if (strncmp(cmdline, "getgpiobase", 11) == 0) {
+		int fd;
+		char gpiobase[3 + 1];
+
+		memset(gpiobase, '\0', (3 + 1));
+		fd = open("/sys/class/gpio/gpiochip0/base", O_RDONLY);
+		if (fd < 0) {
+			printf("\nPlease make sure AMD GPIO driver is loaded\n");
+			exit(EXIT_FAILURE);
+		}
+
+		if(read(fd, gpiobase, 3) < 0)
+			perror("Cannot read GPIO base");
+
+		printf("\nGPIO pin numbering starts from %d\n", atoi(gpiobase));
+		close(fd);
+	} else if (strncmp(cmdline, "getgpioname", 11) == 0) {
+		int fd;
+		char gpioname[10 + 1]; /* Max 10 characters + NULL character */
+
+		/* Zero initialize gpioname array */
+		memset(gpioname, '\0', sizeof(gpioname));
+
+		fd = open("/sys/class/gpio/gpiochip0/label", O_RDONLY);
+		if (fd < 0) {
+			printf("\nPlease make sure AMD GPIO driver is loaded\n");
+			exit(EXIT_FAILURE);
+		}
+
+		if(read(fd, gpioname, 10) < 0)
+			perror("Cannot read GPIO driver name");
+
+		printf("\nGPIO driver loaded is %s\n", gpioname);
+		close(fd);
+	} else if (strncmp(cmdline, "getgpiovalue", 12) == 0) {
+		int fd;
+		int gpio_num;
+		char gpio[4 + 1];
+		char pathname[80];
+		int ret = 0;
+
+		/* Lets point to the end of first token */
+		if (sscanf(cmdline, "getgpiovalue %d", &gpio_num) < 1) {
+			printf("Invalid inputs, please try again\n\n");
+			return;
+		}
+
+		fd = open("/sys/class/gpio/export", O_WRONLY);
+		if (fd < 0) {
+			if (errno == EACCES)
+				printf("\nYou do not have correct permission, please run as root\n");
+			else
+				perror("Error opening /sys/class/gpio/export");
+
+			exit(EXIT_FAILURE);
+		}
+
+		memset(gpio, '\0', (3 + 1));
+		if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
+			printf("Invalid inputs, please try again\n");
+			close(fd);
+			return;
+		}
+
+		ret = write(fd, gpio, strlen(gpio));
+		/*
+		 * There can be two situations ->
+		 *      1) The GPIO is being exported for the first time.
+		 *      2) The GPIO is being exported again.
+		 * In the first case, the write to file descriptor should
+		 * succeed, and we should still fall into the if clause.
+		 *
+		 * In the second case, write will fail and errno will be
+		 * set to EBUSY, since the GPIO pin is already exported.
+		 * Rest all is error.
+		 */
+		if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
+			/* Close the last file descriptor */
+			close(fd);
+
+			memset(pathname, '\0', sizeof(pathname));
+			sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num);
+
+			fd = open(pathname, O_RDONLY);
+			if (fd < 0)
+				perror("GPIO read error");
+			else {
+				char value[1 + 1];
+
+				memset(value, '\0', 2);
+				ret = read(fd, value, 1);
+				if (ret < 0)
+					perror("Cannot read GPIO pin");
+
+				printf("\nGPIO pin %d is at \"%s\"\n", gpio_num,
+				(strncmp(value, "1", 1) == 0) ? "high" : "low");
+
+				close(fd);
+
+				/*
+				 * Mark the GPIO as already exported, so that we can use
+				 * unexport them during exit.
+				 */
+				gpio_in_use[gpio_num] = 1;
+			}
+		} else {
+			if (errno == EINVAL)
+				printf("\nInvalid GPIO number\n");
+			else
+				perror("Error exporting GPIO number");
+
+			close(fd);
+		}
+	} else if (strncmp(cmdline, "getgpiomode", 11) == 0) {
+		int fd;
+		int gpio_num;
+		char gpio[4 + 1];
+		char pathname[80];
+		int ret = 0;
+
+		/* Lets point to the end of first token */
+		if (sscanf(cmdline, "getgpiomode %d", &gpio_num) < 1) {
+			printf("Invalid inputs, please try again\n\n");
+			return;
+		}
+
+		fd = open("/sys/class/gpio/export", O_WRONLY);
+		if (fd < 0) {
+			if (errno == EACCES)
+				printf("\nYou do not have correct permission, please run as root\n");
+			else
+				perror("Error opening /sys/class/gpio/export");
+
+			exit(EXIT_FAILURE);
+		}
+
+		memset(gpio, '\0', (3 + 1));
+		if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
+			printf("Invalid inputs, please try again\n");
+			close(fd);
+			return;
+		}
+
+		ret = write(fd, gpio, strlen(gpio));
+		/*
+		 * There can be two situations ->
+		 *      1) The GPIO is being exported for the first time.
+		 *      2) The GPIO is being exported again.
+		 * In the first case, the write to file descriptor should
+		 * succeed, and we should still fall into the if clause.
+		 *
+		 * In the second case, write will fail and errno will be
+		 * set to EBUSY, since the GPIO pin is already exported.
+		 * Rest all is error.
+		 */
+		if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
+			/* Close the last file descriptor */
+			close(fd);
+
+			memset(pathname, '\0', sizeof(pathname));
+			sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num);
+
+			fd = open(pathname, O_RDONLY);
+			if (fd < 0)
+				perror("GPIO read error");
+			else {
+				char mode[3 + 1];
+				int c, i = 0;
+
+				memset(mode, '\0', (3 + 1));
+				ret = read(fd, mode, 3);
+				if (ret < 0)
+					perror("Cannot read GPIO pin");
+
+				printf("\nGPIO pin %d is in \"%s\" mode\n", gpio_num,
+				(strncmp(mode, "in", 2) == 0) ? "input" : "output");
+
+				close(fd);
+
+				/*
+				 * Mark the GPIO as already exported, so that we can use
+				 * unexport them during exit.
+				 */
+				gpio_in_use[gpio_num] = 1;
+			}
+		} else {
+			if (errno == EINVAL)
+				printf("\nInvalid GPIO number\n");
+			else
+				perror("Error exporting GPIO number");
+
+			close(fd);
+		}
+	} else if (strncmp(cmdline, "setgpiomode", 11) == 0) {
+		int fd;
+		int gpio_num;
+		char mode[4 + 1];
+		char gpio[3 + 1];
+		int ret;
+
+		memset(mode, (4 + 1), 0);
+		if (sscanf(cmdline, "setgpiomode %d %s", &gpio_num, mode) < 2) {
+			printf("Invalid inputs, please try again\n\n");
+			return;
+		}
+
+		memset(gpio, '\0', (3 + 1));
+		if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
+			printf("Invalid inputs, please try again\n");
+			return;
+		}
+
+		fd = open("/sys/class/gpio/export", O_WRONLY);
+		if (fd < 0) {
+			if (errno == EACCES)
+				printf("\nYou do not have correct permission, please run as root\n");
+			else
+				perror("Error opening /sys/class/gpio/export");
+
+			exit(EXIT_FAILURE);
+		}
+
+		ret = write(fd, gpio, strlen(gpio));
+		if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
+			char pathname[80];
+
+			/* Close the last file descriptor */
+			close(fd);
+
+			memset(pathname, '\0', sizeof(pathname));
+			sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num);
+
+			fd = open(pathname, O_WRONLY);
+			if (fd < 0)
+				perror("GPIO read error");
+			else {
+				/* Sanity check */
+				if ((strncmp(mode, "in", 2) == 0) ||
+				    (strncmp(mode, "out", 3) == 0) ||
+				    (strncmp(mode, "high", 4) == 0) ||
+				    (strncmp(mode, "low", 3) == 0)) {
+					/* Write mode into /sys/.../direction file */
+					ret = write(fd, mode, strlen(mode));
+					if (ret < 0)
+						perror("Error writing GPIO mode");
+				} else
+					printf("\nInvalid GPIO mode, please try again\n");
+
+				close(fd);
+
+				/*
+				 * Mark the GPIO as exported, so that we can use
+				 * unexport them during exit.
+				 */
+				gpio_in_use[gpio_num] = 1;
+			}
+		} else {
+			if (errno == EINVAL)
+				printf("\nInvalid GPIO number\n");
+			else
+				perror("Error exporting GPIO number");
+
+			close(fd);
+		}
+	} else if (strncmp(cmdline, "setgpiovalue", 12) == 0) {
+		int fd;
+		int gpio_num;
+		char gpio[3 + 1];
+		char value[4 + 1];
+		int ret;
+
+		memset(value, (4 + 1), 0);
+		if (sscanf(cmdline, "setgpiovalue %d %s", &gpio_num, value) < 2) {
+			printf("Invalid inputs, please try again\n\n");
+			return;
+		}
+
+		memset(gpio, '\0', (3 + 1));
+		if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
+			printf("Invalid inputs, please try again\n");
+			return;
+		}
+
+		fd = open("/sys/class/gpio/export", O_WRONLY);
+		if (fd < 0) {
+			if (errno == EACCES)
+				printf("\nYou do not have correct permission, please run as root\n");
+			else
+				perror("Error opening /sys/class/gpio/export");
+
+			exit(EXIT_FAILURE);
+		}
+
+		ret = write(fd, gpio, strlen(gpio));
+		if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
+			char pathname[80];
+
+			/* Close the last file descriptor */
+			close(fd);
+
+			memset(pathname, '\0', sizeof(pathname));
+			sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num);
+
+			fd = open(pathname, O_WRONLY);
+			if (fd < 0)
+				perror("GPIO read error");
+			else {
+				if (strncmp(value, "high", 4) == 0)
+					value[0] = '1';
+				else if (strncmp(value, "low", 3) == 0)
+					value[0] = '0';
+				else {
+					printf("\nInvalid input, please try again...\n");
+					return;
+				}
+
+				/* Write mode into /sys/.../direction file */
+				ret = write(fd, value, 1);
+				if (ret < 0)
+					perror("Error writing GPIO mode");
+
+				close(fd);
+
+				/*
+				 * Mark the GPIO as exported, so that we can use
+				 * unexport them during exit.
+				 */
+				gpio_in_use[gpio_num] = 1;
+			}
+		} else {
+			if (errno == EINVAL)
+				printf("\nInvalid GPIO number\n");
+			else
+				perror("Error exporting GPIO number");
+
+			close(fd);
+		}
+	} else if (strncmp(cmdline, "dmesg", 5) == 0) {
+		if (system("dmesg | grep GPIO") < 0)
+			perror("Error executing \'dmesg | grep GPIO\'");
+	} else if (strncmp(cmdline, "license", 7) == 0) {
+		show_license();
+	} else if (strncmp(cmdline, "exit", 4) == 0) {
+		int i;
+		int ret;
+		char gpio[3 + 1];
+
+		printf("\nExiting...\n");
+
+		/* We need to unexport all the GPIO pins exported earlier */
+		for (i = 0; i < AMD_GPIO_NUM_PINS; i++) {
+			if (gpio_in_use[i]) {
+				int fd;
+
+				fd = open("/sys/class/gpio/unexport", O_WRONLY);
+				if (fd < 0) {
+					printf("\nPlease make sure AMD GPIO driver is loaded\n");
+					exit(EXIT_FAILURE);
+				}
+				memset(gpio, '\0', (3 + 1));
+				snprintf(gpio, 4, "%d", i);
+
+				ret = write(fd, gpio, strlen(gpio));
+				if (ret < 0)
+					perror("Error writing to /sys/class/gpio/unexport");
+			}
+		}
+
+		exit(EXIT_SUCCESS);
+	} else {
+		printf("\nUnknown command\n");
+		print_usage();
+	}
+}
+
+int main(void)
+{
+	char *cmdline= NULL;
+
+	printf("GPIO sample application version: %s\n", GPIO_APP_VERSION);
+	printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
+	       "This sample application comes with ABSOLUTELY NO WARRANTY;\n"
+	       "This is free software, and you are welcome to redistribute it\n"
+	       "under certain conditions; type `license' for details.\n\n");
+
+	/* Handler for Ctrl+C */
+	signal(SIGINT, sighandler);
+
+	while (1) {
+		cmdline = readline(show_prompt());
+		parse_cmd(cmdline);
+		/* Free the memory malloc'ed by readline */
+		free(cmdline);
+		cmdline = NULL;
+	}
+
+	/* Should never reach here */
+	return 0;
+}
diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h
new file mode 100644
index 00000000..af9c3b68
--- /dev/null
+++ b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h
@@ -0,0 +1,17 @@
+#ifndef _GPIO_TEST_H_
+#define _GPIO_TEST_H_
+
+
+
+/* IOCTL numbers */
+
+typedef struct {
+	int offset;
+	int value;
+}debug_data;
+
+#define GPIO_TEST_IOC_MAGIC			'k'
+#define GPIO_IOC_SWCTRLIN  _IOW(GPIO_TEST_IOC_MAGIC, 1, debug_data)
+#define GPIO_IOC_SWCTRLEN  _IOW(GPIO_TEST_IOC_MAGIC, 2, debug_data)
+
+#endif /* _GPIO_TEST_H_ */
diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb b/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb
new file mode 100644
index 00000000..f3f3e2e3
--- /dev/null
+++ b/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb
@@ -0,0 +1,29 @@
+DESCRIPTION = "Sample application for AMD GPIO driver"
+SECTION = "applications"
+LICENSE = "BSD"
+DEPENDS = "readline"
+LIC_FILES_CHKSUM = "\
+		    file://gpio-test.c;md5=e6e905de01cc60d7d588d095010cc904 \
+		    file://gpio-test.h;md5=c7aaa743b172cf584032f9bfc5e85044 \
+		   "
+
+PR = "r1"
+PV = "1.0"
+
+SRC_URI = "\
+	   file://gpio-test.c \
+	   file://gpio-test.h \
+	  "
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+
+S = "${WORKDIR}"
+
+do_compile() {
+	${CC} gpio-test.c -o gpio-test -lreadline
+}
+
+do_install() {
+	install -d ${D}${bindir}
+	install -m 0755 gpio-test ${D}${bindir}
+}
diff --git a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c
new file mode 100644
index 00000000..22c90036
--- /dev/null
+++ b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c
@@ -0,0 +1,798 @@
+/*****************************************************************************
+*
+* Copyright (c) 2014, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+***************************************************************************/
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <string.h>
+#include <dirent.h>
+#include <signal.h>
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+
+#include <readline/readline.h>
+
+#include "spirom.h"
+
+#define SPI_APP_VERSION "1.0"
+
+static int device_opened = 0;
+static char filename[20];
+static int fd = -1;
+
+char *show_prompt(void)
+{
+	return "$ ";
+}
+
+void sighandler(int sig)
+{
+	/* Do nothing. That is the idea. */
+}
+
+void show_license(void)
+{
+	printf("/*****************************************************************************\n"
+	       "*\n"
+	       "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
+	       "* All rights reserved.\n"
+	       "*\n"
+	       "* Redistribution and use in source and binary forms, with or without\n"
+	       "* modification, are permitted provided that the following conditions are met:\n"
+	       "*     * Redistributions of source code must retain the above copyright\n"
+	       "*       notice, this list of conditions and the following disclaimer.\n"
+	       "*     * Redistributions in binary form must reproduce the above copyright\n"
+	       "*       notice, this list of conditions and the following disclaimer in the\n"
+	       "*       documentation and/or other materials provided with the distribution.\n"
+	       "*     * Neither the name of Advanced Micro Devices, Inc. nor the names of\n"
+	       "*       its contributors may be used to endorse or promote products derived\n"
+	       "*       from this software without specific prior written permission.\n"
+	       "*\n"
+	       "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n"
+	       "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n"
+	       "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n"
+	       "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n"
+	       "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n"
+	       "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n"
+	       "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n"
+	       "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n"
+	       "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n"
+	       "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
+	       "*\n"
+	       "*\n"
+	       "***************************************************************************/\n");
+}
+
+void print_usage(void)
+{
+	printf("\nCommands Supported ->\n");
+	printf(" enumerate				: List all SPI device nodes available\n");
+	printf(" setdevice <dev_id>			: Set the SPI device number to access\n");
+	printf(" wren					: Enable Write operation on SPI device\n");
+	printf(" wrdi					: Disable Write operation on SPI device\n");
+	printf(" chiperase				: Erase entire ROM chip\n");
+	printf(" rdsr					: Read status register of ROM device\n");
+	printf(" rdid					: Read device identification string\n");
+	printf(" sectorerase <addr> <num_sectors>	: Erase a fixed number of sectors starting at the address\n"
+	       "                                          specified\n");
+	printf(" blockerase <addr> <num_blocks>		: Erase a fixed number of blocks starting at the address\n"
+	       "                                          specified\n");
+	printf(" read <addr> <num_bytes> <filename>	: Read a fixed number of bytes starting at address\n"
+	       "                                          specified, and output the contents into file\n");
+	printf(" write <addr> <num_bytes> <filename>	: Read a fixed number of bytes from file and output\n"
+	       "                                          the contents to the device starting at the address\n"
+	       "                                          specified\n");
+	printf(" license				: Displays the terms of LICENSE for this application\n");
+	printf(" help					: Displays help text\n");
+	printf(" exit					: Exits the application\n\n");
+}
+
+void parse_cmd(const char *cmdline)
+{
+	struct spi_ioc_transfer tr;
+	unsigned int bytes_chunks;
+	unsigned int remaining_bytes;
+	int addr;
+	int ret;
+
+	if (strncmp(cmdline, "enumerate", 9) == 0) {
+		DIR *dir;
+		struct dirent *dir_entry;
+		int device_found = 0;
+
+		/* Get the directory handle */
+		if ((dir = opendir("/dev")) == NULL) {
+			printf("\n\nFailed to open directory /dev. Probably you "
+			       "do not have right privilege!\n\n");
+			exit(EXIT_FAILURE);
+		}
+
+		/* Iterate over all the directory entries */
+		while ((dir_entry = readdir(dir)) != NULL) {
+			/*
+			 * If the file is a character device, and its signature
+			 * matches spirom, then we print the corresponding file.
+			 */
+			if ((dir_entry->d_type == DT_CHR) &&
+			    (strncmp(dir_entry->d_name, "spirom", 6) == 0)) {
+				printf("/dev/%s\n", dir_entry->d_name);
+				device_found = 1;
+			}
+		}
+
+		printf("\n");
+
+		/*
+		 * In case we did not find even a single entry, we print a
+		 * message and exit.
+		 */
+		if (!device_found) {
+			printf("\n\nNo spirom device nodes found, load spirom "
+			       "kernel module and try again\n\n");
+			exit(EXIT_FAILURE);
+		}
+	} else if (strncmp(cmdline, "setdevice", 9) == 0) {
+		char input[2 + 1];
+		int file_desc;
+
+		cmdline += 10;
+		memset(input, 0, 3);
+		if (sscanf(cmdline, "%s", input) < 1) {
+			printf("\nInvalid inputs, please try again\n\n");
+			return;
+		}
+
+		memset(filename, 0, 20);
+		snprintf(filename, 19, "/dev/spirom%s", input);
+		file_desc = open(filename, O_RDWR);
+		if (file_desc < 0) {
+			printf("\nError opening file %s\n\n", filename);
+			return;
+		}
+
+		/* Once we have validated inputs, we store them into the global
+		 * variables used at other places in the program.
+		 */
+		fd = file_desc;
+		device_opened = 1;
+		printf("\nSPI device set to /dev/spirom%s\n\n", input);
+	} else if (strncmp(cmdline, "wren", 4) == 0) {
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		/* command without data */
+		tr.buf[0] = ROM_WREN;
+		tr.direction = 0;
+		tr.len = 0;
+		tr.addr_present = 0;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1)
+			printf("\nError executing WREN command\n\n");
+		else
+			printf("\n...WREN completed successfully\n\n");
+	} else if (strncmp(cmdline, "wrdi", 4) == 0) {
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		/* command without data */
+		tr.buf[0] = ROM_WRDI;
+		tr.direction = 0;
+		tr.len = 0;
+		tr.addr_present = 0;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1)
+			printf("\nError executing WRDI command\n\n");
+		else
+			printf("\n...WRDI completed successfully\n\n");
+	} else if (strncmp(cmdline, "chiperase", 9) == 0) {
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		tr.buf[0] = ROM_RDSR;
+		tr.direction = RECEIVE;
+		tr.addr_present = 0;
+		tr.len = 1;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing RDSR command\n\n");;
+			return;
+		} else if ((tr.buf[1] & 0x02) == 0x00) {
+			printf("\nCannot execute CHIPERASE command, write is disabled\n\n");
+			return;
+		}
+
+		/* Command without data */
+		tr.buf[0] = ROM_CHIP_ERASE;
+		tr.direction = 0;
+		tr.len = 0;
+		tr.addr_present = 0;
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing CHIPERASE command\n\n");
+			return;
+		}
+
+		printf("\n\nCHIPERASE operation in progress, please do not "
+		       " stop in between.\n\n");
+
+		/* Make sure WIP has been reset */
+		while (1) {
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_RDSR;
+			tr.direction = RECEIVE;
+			tr.addr_present = 0;
+			tr.len = 1;
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing RDSR command\n\n");
+				return;
+			}
+
+			if ((tr.buf[1] & 0x01) == 0x00)
+				break;
+		}
+
+		printf("\n\n...CHIPERASE completed successfully\n\n");
+		/* Restore signal handler to default */
+	} else if (strncmp(cmdline, "rdsr", 4) == 0) {
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		/* Command with response */
+		tr.buf[0] = ROM_RDSR;
+		tr.direction = RECEIVE;
+		tr.addr_present = 0;
+		tr.len = 1;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing RDSR command\n\n");
+			return;
+		}
+
+		/*
+		 * The 1-byte response will be stored in tr.buf,
+		 * so print it out
+		 */
+		printf("\nRDSR command returned: 0x%.2x\n\n", tr.buf[1]);
+	} else if (strncmp(cmdline, "rdid", 4) == 0) {
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		/* Command with response */
+		tr.buf[0] = ROM_RDID;
+		tr.direction = RECEIVE;
+		tr.addr_present = 0;
+		tr.len = 3;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing RDID command\n\n");
+			return;
+		}
+
+		/*
+		 * The 3-bytes response will be stored in tr.buf,
+		 * so print it out
+		 */
+		printf("\nRDID command returned: 0x%.2x%.2x%.2x\n", tr.buf[1],
+			tr.buf[2], tr.buf[3]);
+	} else if (strncmp(cmdline, "sectorerase", 11) == 0) {
+		int nsectors;
+		int i;
+
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		cmdline += 12;
+		if (sscanf(cmdline, "0x%x 0x%x", &addr, &nsectors) < 2) {
+			printf("\nInvalid inputs, please try again\n\n");
+			return;
+		}
+
+		tr.buf[0] = ROM_RDSR;
+		tr.direction = RECEIVE;
+		tr.addr_present = 0;
+		tr.len = 1;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing RDSR command\n\n");
+			return;
+		} else if ((tr.buf[1] & 0x02) == 0x00) {
+			printf("\nCannot execute SECTORERASE command, write is disabled\n\n");
+			return;
+		}
+
+		printf("\n\nSECTORERASE operation in progress, please do not "
+		       " stop in between.\n\n");
+
+		for (i = 0; i < nsectors; i++) {
+			/* Write Enable before Sector Erase */
+			tr.buf[0] = ROM_WREN;
+			tr.direction = 0;
+			tr.len = 0;
+			tr.addr_present = 0;
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing WREN command\n\n");
+				return;
+			}
+
+			/* Command with address but no data */
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_SECTOR_ERASE;
+			tr.buf[3] = addr & 0xff;
+			tr.buf[2] = (addr >> 8) & 0xff;
+			tr.buf[1] = (addr >> 16) & 0xff;
+			tr.addr_present = 1;
+			tr.direction = 0;
+			tr.len = 0;
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing SECTORERASE command\n\n");
+				return;
+			}
+
+			/* point to the next 4k sector */
+			addr += 4 * 1024;
+
+			/*
+			 * Before the next loop, we need to make sure that WIP
+			 * bit in the output of RDSR has been reset.
+			 */
+			while (1) {
+				memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+				tr.buf[0] = ROM_RDSR;
+				tr.direction = RECEIVE;
+				tr.addr_present = 0;
+				tr.len = 1;
+
+				ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+				if (ret < 1) {
+					printf("\nError executing RDSR command\n\n");
+					return;
+				}
+
+				if ((tr.buf[1] & 0x01) == 0x00)
+					break;
+			}
+		}
+
+		printf("\n\n...SECTORERASE completed successfully\n\n");
+	} else if (strncmp(cmdline, "blockerase", 10) == 0) {
+		int nblocks;
+		int i;
+
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		cmdline += 11;
+		if (sscanf(cmdline, "0x%x 0x%x", &addr, &nblocks) < 2) {
+			printf("\nInvalid inputs, please try again\n\n");
+			return;
+		}
+
+		tr.buf[0] = ROM_RDSR;
+		tr.direction = RECEIVE;
+		tr.addr_present = 0;
+		tr.len = 1;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing RDSR command\n\n");
+			return;
+		} else if ((tr.buf[1] & 0x02) == 0x00) {
+			printf("\nError executing BLOCKERASE command, write is disabled\n\n");
+			return;
+		}
+
+		printf("\n\nBLOCKERASE operation in progress, please do not "
+		       " stop in between.\n\n");
+
+		for (i = 0; i < nblocks; i++) {
+			/* Write Enable before Block Erase */
+			tr.buf[0] = ROM_WREN;
+			tr.direction = 0;
+			tr.len = 0;
+			tr.addr_present = 0;
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing WREN command\n\n");
+				return;
+			}
+
+			/* Command with address but no data */
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_BLOCK_ERASE;
+			tr.buf[3] = addr & 0xff;
+			tr.buf[2] = (addr >> 8) & 0xff;
+			tr.buf[1] = (addr >> 16) & 0xff;
+			tr.addr_present = 1;
+			tr.direction = 0;
+			tr.len = 0;
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing BLOCKERASE command\n\n");
+				return;
+			}
+
+			/* point to the next 64k block */
+			addr += 64 * 1024;
+
+			/*
+			 * Before the next loop, we need to make sure that WIP
+			 * bit in the output of RDSR has been reset.
+			 */
+			while (1) {
+				memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+				tr.buf[0] = ROM_RDSR;
+				tr.direction = RECEIVE;
+				tr.addr_present = 0;
+				tr.len = 1;
+
+				ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+				if (ret < 1) {
+					printf("\nError executing RDSR command\n\n");
+					return;
+				}
+
+				if ((tr.buf[1] & 0x01) == 0x00)
+					break;
+			}
+		}
+
+		printf("\n\n...BLOCKERASE completed successfully\n\n");
+	} else if (strncmp(cmdline, "read", 4) == 0) {
+		int nbytes;
+		int outfile_fd;
+		int i;
+
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		cmdline += 5;
+		memset(filename, 0, 20);
+		if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) {
+			printf("\nInvalid inputs, please try again\n\n");
+			return;
+		}
+
+		/*
+		 * Open the output file for writing. Create a new file if not
+		 * there, and empty the file before writing if file already
+		 * exists.
+		 */
+		outfile_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+		if (outfile_fd < 0) {
+			printf("\nError opening file %s for writing\n\n", filename);
+			return;
+		}
+
+		/*
+		 * We will break down the bytes to be received in chunks of
+		 * of 64-bytes. Data might not be a even multiple of 64. So
+		 * in that case, we will have some remaining bytes <4. We
+		 * handle that separately.
+		 */
+		bytes_chunks = nbytes / 64;
+		remaining_bytes = nbytes % 64;
+
+		printf("\n\nREAD operation in progress.\n\n");
+
+		for (i = 0; i < bytes_chunks; i++) {
+			/* Command with address and data */
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_READ;
+			tr.direction = RECEIVE;
+			/*
+			 * We will store the address into the buffer in little
+			 * endian order.
+			 */
+			tr.buf[3] = addr & 0xff;
+			tr.buf[2] = (addr >> 8) & 0xff;
+			tr.buf[1] = (addr >> 16) & 0xff;
+			tr.len = 64;
+			tr.addr_present = 1;
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing READ command\n\n");
+				return;
+			}
+
+			/* Write the data read to output file */
+			if (write(outfile_fd, &tr.buf[4], tr.len) < 0) {
+				printf("\nError writing to file %s\n\n", filename);
+				return;
+			}
+			addr += 64;
+		}
+
+		if (remaining_bytes) {
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_READ;
+			tr.direction = RECEIVE;
+			tr.buf[3] = addr & 0xff;
+			tr.buf[2] = (addr >> 8) & 0xff;
+			tr.buf[1] = (addr >> 16) & 0xff;
+			tr.len = remaining_bytes;
+			tr.addr_present = 1;
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing READ command\n\n");
+				return;
+			}
+
+			if (write(outfile_fd, &tr.buf[4], tr.len) < 0) {
+				printf("\nError writing to file %s\n\n", filename);
+				return;
+			}
+		}
+
+		printf("\n\n...READ completed successfully\n\n");
+		close(outfile_fd);
+	} else if (strncmp(cmdline, "write", 5) == 0) {
+		int nbytes;
+		int infile_fd;
+		int i;
+
+		if (!device_opened) {
+			printf("\nSPI device needs to be set before you can "
+			       "perform this operation\n\n");
+			return;
+		}
+
+		cmdline += 6;
+		memset(filename, 0, 20);
+		if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) {
+			printf("\nInvalid inputs, please try again\n\n");
+			return;
+		}
+
+		/* Open the input file for reading*/
+		infile_fd = open(filename, O_RDONLY);
+		if (infile_fd < 0) {
+			printf("\nError opening file %s for reading\n\n", filename);
+			return;
+		}
+
+		/*
+		 * We will break down the bytes to be transmitted in chunks of
+		 * of 64-bytes. Like for read, we might not have data in an
+		 * even multiple of 64 bytes. So we will handle the remaining
+		 * bytes in the end.
+		 */
+		tr.buf[0] = ROM_RDSR;
+		tr.direction = RECEIVE;
+		tr.addr_present = 0;
+		tr.len = 1;
+
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret < 1) {
+			printf("\nError executing RDSR command\n\n");
+			return;
+		} else if ((tr.buf[1] & 0x02) == 0x00) {
+			printf("\nCannot execute WRITE command, write is disabled\n\n");
+			return;
+		}
+
+		bytes_chunks = nbytes / 64;
+		remaining_bytes = nbytes % 64;
+
+		printf("\n\nWRITE operation in progress, please do not "
+		       " stop in between.\n\n");
+
+		for (i = 0; i < bytes_chunks; i++) {
+			tr.buf[0] = ROM_WREN;
+			tr.direction = 0;
+			tr.len = 0;
+			tr.addr_present = 0;
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing WREN command\n\n");
+				return;
+			}
+
+			/* Command with data and address */
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_WRITE;
+			tr.direction = TRANSMIT;
+			/*
+			 * We will store the address into the buffer in little
+			 * endian order.
+			 */
+			tr.buf[3] = addr & 0xff;
+			tr.buf[2] = (addr >> 8) & 0xff;
+			tr.buf[1] = (addr >> 16) & 0xff;
+			tr.len = 64;
+			tr.addr_present = 1;
+
+			/* Read 64 bytes from input file to buffer */
+			if (read(infile_fd, &tr.buf[4], tr.len) < 0) {
+				printf("\nError reading from file %s\n\n", filename);
+				return;
+			}
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing WRITE command\n\n");
+				return;
+			}
+
+			addr += 64;
+
+			/*
+			 * Before the next loop, we need to make sure that WIP
+			 * bit in the output of RDSR has been reset.
+			 */
+			while (1) {
+				memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+				tr.buf[0] = ROM_RDSR;
+				tr.direction = RECEIVE;
+				tr.addr_present = 0;
+				tr.len = 1;
+
+				ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+				if (ret < 1) {
+					printf("\nError executing RDSR command\n\n");
+					return;
+				}
+
+				if ((tr.buf[1] & 0x01) == 0x00)
+					break;
+			}
+		}
+
+		if (remaining_bytes) {
+			tr.buf[0] = ROM_WREN;
+			tr.direction = 0;
+			tr.len = 0;
+			tr.addr_present = 0;
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing WREN command\n\n");
+				return;
+			}
+
+			memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+			tr.buf[0] = ROM_WRITE;
+			tr.direction = TRANSMIT;
+			tr.buf[3] = addr & 0xff;
+			tr.buf[2] = (addr >> 8) & 0xff;
+			tr.buf[1] = (addr >> 16) & 0xff;
+			tr.len = remaining_bytes;
+			tr.addr_present = 1;
+
+			if (read(infile_fd, &tr.buf[4], tr.len) < 0) {
+				printf("\nError reading from file %s\n\n", filename);
+				return;
+			}
+
+			ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+			if (ret < 1) {
+				printf("\nError executing WRITE command\n\n");
+				return;
+			}
+
+			while (1) {
+				memset(&tr, 0, sizeof(struct spi_ioc_transfer));
+				tr.buf[0] = ROM_RDSR;
+				tr.direction = RECEIVE;
+				tr.addr_present = 0;
+				tr.len = 1;
+
+				ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+				if (ret < 1) {
+					printf("\nError executing RDSR command\n\n");
+					return;
+				}
+
+				if ((tr.buf[1] & 0x01) == 0x00)
+					break;
+			}
+		}
+
+		printf("\n\n...WRITE completed successfully\n\n");
+		close(infile_fd);
+	} else if (strncmp(cmdline, "license", 7) == 0) {
+		show_license();
+	} else if (strncmp(cmdline, "exit", 4) == 0) {
+		printf("\nExiting...\n");
+		close(fd);
+		exit(EXIT_SUCCESS);
+	} else if (strncmp(cmdline, "help", 4) == 0) {
+		print_usage();
+	} else {
+		printf("\nUnknown command\n");
+		print_usage();
+	}
+}
+
+int main(void)
+{
+	char *cmdline= NULL;
+
+	printf("SPI sample application version: %s\n", SPI_APP_VERSION);
+	printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
+	       "This sample application comes with ABSOLUTELY NO WARRANTY;\n"
+	       "This is free software, and you are welcome to redistribute it\n"
+	       "under certain conditions; type `license` for details.\n\n");
+
+	/* Set the signal handler */
+	signal(SIGINT, sighandler);
+
+	while (1) {
+		cmdline = readline(show_prompt());
+		parse_cmd(cmdline);
+		/* Free the memory malloc'ed by readline */
+		free(cmdline);
+	}
+
+	/* Restore the default signal handler */
+	signal(SIGINT, SIG_DFL);
+
+	/* Should never reach here */
+	return 0;
+}
diff --git a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h
new file mode 100644
index 00000000..f599925f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h
@@ -0,0 +1,53 @@
+#ifndef SPIROM_H
+#define SPIROM_H
+
+#include <linux/types.h>
+
+/*---------------------------------------------------------------------------*/
+
+/* IOCTL commands */
+
+#define SPI_IOC_MAGIC			'k'
+
+#define TRANSMIT	1
+#define RECEIVE		2
+
+/*
+ * struct spi_ioc_transfer - interface structure between application and ioctl
+ *
+ * @buf: Buffer to hold 1-byte command, 3-bytes address, and 4-byte data for
+ *       transmit or receive. The internal FIFO of our controller can hold a
+ *       maximum of 8 bytes, including the address. But here we assume the
+ *       maximum data excluding address to be 4-bytes long.
+ *
+ * @direction: Direction of data transfer, either TRANSMIT or RECEIVE.
+ *
+ * @len: Length of data excluding command and address.
+ *
+ * @addr_present: Flag to indicate whether 'buf' above contains an address.
+ */
+struct spi_ioc_transfer {
+	__u8		buf[64 + 1 + 3];
+	__u8		direction;
+	__u8		len;
+	__u8		addr_present;
+};
+
+/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
+#define SPI_MSGSIZE(N) \
+	((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
+		? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
+#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
+
+/* SPI ROM command codes */
+#define ROM_WREN		0x06
+#define ROM_WRDI		0x04
+#define ROM_RDSR		0x05
+#define ROM_RDID		0x9F
+#define ROM_CHIP_ERASE		0x60
+#define ROM_SECTOR_ERASE	0x20
+#define ROM_BLOCK_ERASE		0xD8
+#define ROM_READ		0x03
+#define ROM_WRITE		0x02
+
+#endif /* SPIROM_H */
diff --git a/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb b/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb
new file mode 100644
index 00000000..8824d55f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb
@@ -0,0 +1,27 @@
+DESCRIPTION = "Sample application for AMD SPI driver"
+SECTION = "applications"
+LICENSE = "BSD"
+DEPENDS = "readline"
+LIC_FILES_CHKSUM = "file://spirom-test.c;md5=73fa56dd9cc632c765154aa1c2f5b228 \
+                    file://spirom.h;md5=1990f1f1e7a82115c354152bed83df52 \
+                   "
+
+PR = "r1"
+PV = "1.0"
+
+SRC_URI = "file://spirom-test.c \
+           file://spirom.h \
+          "
+
+S = "${WORKDIR}"
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+
+do_compile() {
+	${CC} spirom-test.c -o spirom-test -lreadline
+}
+
+do_install() {
+	install -d ${D}${bindir}
+	install -m 0755 spirom-test ${D}${bindir}
+}
diff --git a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig
new file mode 100644
index 00000000..28ca080e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig
@@ -0,0 +1,3 @@
+# Assume a USB mouse and keyboard are connected
+HAVE_TOUCHSCREEN=n
+HAVE_KEYBOARD=y
diff --git a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend
new file mode 100644
index 00000000..6d4804d1
--- /dev/null
+++ b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend
@@ -0,0 +1,2 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
diff --git a/meta-amdfalconx86/recipes-core/llvm/files/0001-force-link-pass.o.patch b/meta-amdfalconx86/recipes-core/llvm/files/0001-force-link-pass.o.patch
new file mode 100644
index 00000000..e4b5f471
--- /dev/null
+++ b/meta-amdfalconx86/recipes-core/llvm/files/0001-force-link-pass.o.patch
@@ -0,0 +1,42 @@
+From 2f1e7f43ee516e56f9042c94abf6f90b8f61b7a9 Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Thu, 16 Apr 2015 16:11:24 +0530
+Subject: [PATCH 1/1] force link pass.o
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ tools/bugpoint/Makefile | 3 +++
+ tools/opt/Makefile      | 3 +++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/tools/bugpoint/Makefile b/tools/bugpoint/Makefile
+index 174f8d2..dfde77c 100644
+--- a/tools/bugpoint/Makefile
++++ b/tools/bugpoint/Makefile
+@@ -12,6 +12,9 @@ TOOLNAME := bugpoint
+ LINK_COMPONENTS := asmparser instrumentation scalaropts ipo linker bitreader \
+                    bitwriter irreader vectorize objcarcopts codegen
+ 
++# Crappy workaround to make sure it links correctly.
++LLVMLibsOptions := ../../lib/IR/Release*/Pass.o
++
+ # Support plugins.
+ NO_DEAD_STRIP := 1
+ 
+diff --git a/tools/opt/Makefile b/tools/opt/Makefile
+index 2422eb4..79ab3f7 100644
+--- a/tools/opt/Makefile
++++ b/tools/opt/Makefile
+@@ -11,6 +11,9 @@ LEVEL := ../..
+ TOOLNAME := opt
+ LINK_COMPONENTS := bitreader bitwriter asmparser irreader instrumentation scalaropts objcarcopts ipo vectorize all-targets codegen passes
+ 
++# Crappy workaround to make sure it links correctly.
++LLVMLibsOptions := ../../lib/IR/Release*/Pass.o
++
+ # Support plugins.
+ NO_DEAD_STRIP := 1
+ 
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-core/llvm/llvm3.7.0.inc b/meta-amdfalconx86/recipes-core/llvm/llvm3.7.0.inc
new file mode 100644
index 00000000..bb6c5ca3
--- /dev/null
+++ b/meta-amdfalconx86/recipes-core/llvm/llvm3.7.0.inc
@@ -0,0 +1,49 @@
+#
+# Since we need LLVM 3.7.0 but meta-oe currently only supports
+# 3.3, override the minimum bits needed to get it to work.
+# Eventually this will need to be reconciled with upstream
+#
+
+# Ideally this would be done as a patch but since llvm3.inc already 
+# manipulates this file with sed we have to do similar.  We also need
+# to do this as an append to ensure proper sequencing.
+do_configure_append_x86-64() {
+    # Fix paths in llvm-config
+    sed -ri "s#lib/${LLVM_DIR}#${baselib}/${LLVM_DIR}#g" ${S}/tools/llvm-config/llvm-config.cpp
+}
+
+#
+# Override the do_install() provided by llvm3.inc to use the lib64
+# directory naming.
+#
+# This should probably be cleaned up at some point in the stock LLVM
+# sources but at the moment they do not appear to handle lib64 very well.
+#
+do_install() {
+    cd ${LLVM_BUILD_DIR}
+    oe_runmake DESTDIR=${LLVM_INSTALL_DIR} install
+
+    mv ${LLVM_INSTALL_DIR}${bindir}/${HOST_SYS}-llvm-config-host ${LLVM_INSTALL_DIR}/llvm-config-host
+
+    install -d ${D}${bindir}/${LLVM_DIR}
+    mv ${LLVM_INSTALL_DIR}${bindir}/* ${D}${bindir}/${LLVM_DIR}/
+
+    install -d ${D}${includedir}/${LLVM_DIR}
+    mv ${LLVM_INSTALL_DIR}${includedir}/* ${D}${includedir}/${LLVM_DIR}/
+
+    install -d ${D}${libdir}/${LLVM_DIR}
+
+    # The LLVM sources have "/lib" embedded and so we cannot completely rely on the ${libdir} variable
+    if [ -d ${LLVM_INSTALL_DIR}${libdir}/ ]; then
+        mv ${LLVM_INSTALL_DIR}${libdir}/* ${D}${libdir}/${LLVM_DIR}/
+    elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib ]; then
+        mv ${LLVM_INSTALL_DIR}${prefix}/lib/* ${D}${libdir}/${LLVM_DIR}/
+    elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib64 ]; then
+        mv ${LLVM_INSTALL_DIR}${prefix}/lib64/* ${D}${libdir}/${LLVM_DIR}/
+    fi
+
+    ln -s ${LLVM_DIR}/libLLVM-${PV}${SOLIBSDEV} ${D}${libdir}/libLLVM-${PV}${SOLIBSDEV}
+
+    install -d ${D}${docdir}/${LLVM_DIR}
+    mv ${LLVM_INSTALL_DIR}${prefix}/docs/llvm/* ${D}${docdir}/${LLVM_DIR}
+}
diff --git a/meta-amdfalconx86/recipes-core/llvm/llvm3.7.0_3.7.0.bb b/meta-amdfalconx86/recipes-core/llvm/llvm3.7.0_3.7.0.bb
new file mode 100644
index 00000000..00bd0b1a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-core/llvm/llvm3.7.0_3.7.0.bb
@@ -0,0 +1,29 @@
+require recipes-core/llvm/llvm.inc
+require llvm3.7.0.inc
+
+LIC_FILES_CHKSUM = "file://LICENSE.TXT;md5=4c0bc17c954e99fd547528d938832bfa"
+
+DEPENDS += "zlib"
+RDEPENDS_${PN} += "ncurses-terminfo"
+PROVIDES += "llvm"
+
+EXTRA_OECONF += "--enable-zlib"
+PACKAGECONFIG_append_amd = "r600"
+
+SRC_URI = "\
+	   git://llvm.org/git/llvm.git;branch=master;protocol=http \
+	   file://0001-force-link-pass.o.patch \
+	  "
+
+S = "${WORKDIR}/git"
+
+SRCREV = "ffc045ab802ea542aabf1f1f22f97cb8a0ad6cde"
+PV = "3.7.0"
+
+PACKAGECONFIG ??= ""
+PACKAGECONFIG[r600] = "--enable-experimental-targets=R600,,,"
+
+do_configure_prepend() {
+	# Drop "svn" suffix from version string
+	sed -i 's/${PV}svn/${PV}/g' ${S}/configure
+}
diff --git a/meta-amdfalconx86/recipes-graphics/drm/libdrm/0001-drm-add-libdrm_amdgpu.patch b/meta-amdfalconx86/recipes-graphics/drm/libdrm/0001-drm-add-libdrm_amdgpu.patch
new file mode 100644
index 00000000..1609db27
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/drm/libdrm/0001-drm-add-libdrm_amdgpu.patch
@@ -0,0 +1,5665 @@
+From 7a6c09a5a0b17e9e981424fe35ea3492369d4eab Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 12:04:22 -0400
+Subject: [PATCH 1/3] drm: add libdrm_amdgpu
+
+This is the new ioctl wrapper used by the new admgpu driver.
+It's primarily used by xf86-video-amdgpu and mesa.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ Makefile.am                |    5 +
+ amdgpu/Makefile.am         |   55 ++
+ amdgpu/amdgpu.h            | 1278 ++++++++++++++++++++++++++++++++++++++++++++
+ amdgpu/amdgpu_bo.c         |  622 +++++++++++++++++++++
+ amdgpu/amdgpu_cs.c         |  981 ++++++++++++++++++++++++++++++++++
+ amdgpu/amdgpu_device.c     |  242 +++++++++
+ amdgpu/amdgpu_gpu_info.c   |  275 ++++++++++
+ amdgpu/amdgpu_internal.h   |  210 ++++++++
+ amdgpu/amdgpu_vamgr.c      |  169 ++++++
+ amdgpu/libdrm_amdgpu.pc.in |   10 +
+ amdgpu/util_double_list.h  |  146 +++++
+ amdgpu/util_hash.c         |  382 +++++++++++++
+ amdgpu/util_hash.h         |   99 ++++
+ amdgpu/util_hash_table.c   |  257 +++++++++
+ amdgpu/util_hash_table.h   |   65 +++
+ amdgpu/util_math.h         |   32 ++
+ configure.ac               |   20 +
+ include/drm/amdgpu_drm.h   |  600 +++++++++++++++++++++
+ 18 files changed, 5448 insertions(+)
+ create mode 100644 amdgpu/Makefile.am
+ create mode 100644 amdgpu/amdgpu.h
+ create mode 100644 amdgpu/amdgpu_bo.c
+ create mode 100644 amdgpu/amdgpu_cs.c
+ create mode 100644 amdgpu/amdgpu_device.c
+ create mode 100644 amdgpu/amdgpu_gpu_info.c
+ create mode 100644 amdgpu/amdgpu_internal.h
+ create mode 100644 amdgpu/amdgpu_vamgr.c
+ create mode 100644 amdgpu/libdrm_amdgpu.pc.in
+ create mode 100644 amdgpu/util_double_list.h
+ create mode 100644 amdgpu/util_hash.c
+ create mode 100644 amdgpu/util_hash.h
+ create mode 100644 amdgpu/util_hash_table.c
+ create mode 100644 amdgpu/util_hash_table.h
+ create mode 100644 amdgpu/util_math.h
+ create mode 100644 include/drm/amdgpu_drm.h
+
+diff --git a/Makefile.am b/Makefile.am
+index 42d3d7f..5defeb2 100644
+--- a/Makefile.am
++++ b/Makefile.am
+@@ -57,6 +57,10 @@ if HAVE_RADEON
+ RADEON_SUBDIR = radeon
+ endif
+ 
++if HAVE_AMDGPU
++AMDGPU_SUBDIR = amdgpu
++endif
++
+ if HAVE_OMAP
+ OMAP_SUBDIR = omap
+ endif
+@@ -79,6 +83,7 @@ SUBDIRS = \
+ 	$(INTEL_SUBDIR) \
+ 	$(NOUVEAU_SUBDIR) \
+ 	$(RADEON_SUBDIR) \
++	$(AMDGPU_SUBDIR) \
+ 	$(OMAP_SUBDIR) \
+ 	$(EXYNOS_SUBDIR) \
+ 	$(FREEDRENO_SUBDIR) \
+diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
+new file mode 100644
+index 0000000..9baf194
+--- /dev/null
++++ b/amdgpu/Makefile.am
+@@ -0,0 +1,55 @@
++# Copyright © 2008 Jérôme Glisse
++#
++# Permission is hereby granted, free of charge, to any person obtaining a
++# copy of this software and associated documentation files (the "Software"),
++# to deal in the Software without restriction, including without limitation
++# the rights to use, copy, modify, merge, publish, distribute, sublicense,
++# and/or sell copies of the Software, and to permit persons to whom the
++# Software is furnished to do so, subject to the following conditions:
++#
++# The above copyright notice and this permission notice (including the next
++# paragraph) shall be included in all copies or substantial portions of the
++# Software.
++#
++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
++# IN THE SOFTWARE.
++#
++# Authors:
++#    Jérôme Glisse <glisse@freedesktop.org>
++
++AM_CFLAGS = \
++	$(WARN_CFLAGS) -Wno-switch-enum \
++	-I$(top_srcdir) \
++	-I$(top_srcdir)/amdgpu \
++	$(PTHREADSTUBS_CFLAGS) \
++	-I$(top_srcdir)/include/drm
++
++libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
++libdrm_amdgpu_ladir = $(libdir)
++libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:1 -no-undefined
++libdrm_amdgpu_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@
++
++libdrm_amdgpu_la_SOURCES = \
++	amdgpu_gpu_info.c \
++	amdgpu_device.c \
++	amdgpu_bo.c \
++	util_hash.c \
++	util_hash_table.c \
++	amdgpu_vamgr.c \
++	amdgpu_cs.c
++
++nodist_EXTRA_libdrm_amdgpu_la_SOURCES = dummy.cxx
++
++libdrm_amdgpuincludedir = ${includedir}/libdrm
++libdrm_amdgpuinclude_HEADERS = \
++	amdgpu.h
++
++pkgconfigdir = @pkgconfigdir@
++pkgconfig_DATA = libdrm_amdgpu.pc
++
++EXTRA_DIST = libdrm_amdgpu.pc.in
+diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
+new file mode 100644
+index 0000000..90dc33c
+--- /dev/null
++++ b/amdgpu/amdgpu.h
+@@ -0,0 +1,1278 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++
++/**
++ * \file amdgpu.h
++ *
++ * Declare public libdrm_amdgpu API
++ *
++ * This file define API exposed by libdrm_amdgpu library.
++ * User wanted to use libdrm_amdgpu functionality must include
++ * this file.
++ *
++ */
++#ifndef _amdgpu_h_
++#define _amdgpu_h_
++
++#include <stdint.h>
++#include <stdbool.h>
++
++struct drm_amdgpu_info_hw_ip;
++
++/*--------------------------------------------------------------------------*/
++/* --------------------------- Defines ------------------------------------ */
++/*--------------------------------------------------------------------------*/
++
++/**
++ * Define max. number of Command Buffers (IB) which could be sent to the single
++ * hardware IP to accommodate CE/DE requirements
++ *
++ * \sa amdgpu_cs_ib_info
++*/
++#define AMDGPU_CS_MAX_IBS_PER_SUBMIT		4
++
++/**
++ *
++ */
++#define AMDGPU_TIMEOUT_INFINITE			0xffffffffffffffffull
++
++/**
++ * The special flag for GFX submission to identify that this is CE IB
++ * \sa amdgpu_cs_ib_info
++*/
++#define AMDGPU_CS_GFX_IB_CE			0x1
++
++/**
++ * The special flag to mark that this IB will re-used
++ * by client and should not be automatically return back
++ * to free pool by libdrm_amdgpu when submission is completed.
++ *
++ * \sa amdgpu_cs_ib_info
++*/
++#define AMDGPU_CS_REUSE_IB			0x2
++
++/**
++ * The special resource flag for IB submission.
++ * When VRAM is full, some resources may be moved to GTT to make place
++ * for other resources which want to be in VRAM. This flag affects the order
++ * in which resources are moved back to VRAM until there is no space there.
++ * The resources with the highest priority will be moved first.
++ * The value can be between 0 and 15, inclusive.
++ */
++#define AMDGPU_IB_RESOURCE_PRIORITY(x)		((x) & 0xf)
++
++
++/*--------------------------------------------------------------------------*/
++/* ----------------------------- Enums ------------------------------------ */
++/*--------------------------------------------------------------------------*/
++
++/**
++ * Enum describing possible handle types
++ *
++ * \sa amdgpu_bo_import, amdgpu_bo_export
++ *
++*/
++enum amdgpu_bo_handle_type {
++	/** GEM flink name (needs DRM authentication, used by DRI2) */
++	amdgpu_bo_handle_type_gem_flink_name = 0,
++
++	/** KMS handle which is used by all driver ioctls */
++	amdgpu_bo_handle_type_kms = 1,
++
++	/** DMA-buf fd handle */
++	amdgpu_bo_handle_type_dma_buf_fd = 2
++};
++
++/**
++ * Enum describing possible context reset states
++ *
++ * \sa amdgpu_cs_query_reset_state()
++ *
++*/
++enum amdgpu_cs_ctx_reset_state {
++	/** No reset was detected */
++	amdgpu_cs_reset_no_error = 0,
++
++	/** Reset/TDR was detected and context caused */
++	amdgpu_cs_reset_guilty   = 1,
++
++	/** Reset/TDR was detected caused by other context */
++	amdgpu_cs_reset_innocent = 2,
++
++	/** Reset TDR was detected by cause of it unknown */
++	amdgpu_cs_reset_unknown  = 3
++};
++
++/**
++ * For performance reasons and to simplify logic libdrm_amdgpu will handle
++ * IBs only some pre-defined sizes.
++ *
++ * \sa amdgpu_cs_alloc_ib()
++ */
++enum amdgpu_cs_ib_size {
++	amdgpu_cs_ib_size_4K	= 1,
++	amdgpu_cs_ib_size_16K	= 2,
++	amdgpu_cs_ib_size_32K	= 3,
++	amdgpu_cs_ib_size_64K	= 4,
++	amdgpu_cs_ib_size_128K	= 5
++};
++
++/** The number of different IB sizes */
++#define AMDGPU_CS_IB_SIZE_NUM 6
++
++
++/*--------------------------------------------------------------------------*/
++/* -------------------------- Datatypes ----------------------------------- */
++/*--------------------------------------------------------------------------*/
++
++/**
++ * Define opaque pointer to context associated with fd.
++ * This context will be returned as the result of
++ * "initialize" function and should be pass as the first
++ * parameter to any API call
++ */
++typedef struct amdgpu_device *amdgpu_device_handle;
++
++/**
++ * Define GPU Context type as pointer to opaque structure
++ * Example of GPU Context is the "rendering" context associated
++ * with OpenGL context (glCreateContext)
++ */
++typedef struct amdgpu_context *amdgpu_context_handle;
++
++/**
++ * Define handle for amdgpu resources: buffer, GDS, etc.
++ */
++typedef struct amdgpu_bo *amdgpu_bo_handle;
++
++/**
++ * Define handle to be used when dealing with command
++ * buffers (a.k.a. ibs)
++ *
++ */
++typedef struct amdgpu_ib *amdgpu_ib_handle;
++
++
++/*--------------------------------------------------------------------------*/
++/* -------------------------- Structures ---------------------------------- */
++/*--------------------------------------------------------------------------*/
++
++/**
++ * Structure describing memory allocation request
++ *
++ * \sa amdgpu_bo_alloc()
++ *
++*/
++struct amdgpu_bo_alloc_request {
++	/** Allocation request. It must be aligned correctly. */
++	uint64_t alloc_size;
++
++	/**
++	 * It may be required to have some specific alignment requirements
++	 * for physical back-up storage (e.g. for displayable surface).
++	 * If 0 there is no special alignment requirement
++	 */
++	uint64_t phys_alignment;
++
++	/**
++	 * UMD should specify where to allocate memory and how it
++	 * will be accessed by the CPU.
++	 */
++	uint32_t preferred_heap;
++
++	/** Additional flags passed on allocation */
++	uint64_t flags;
++};
++
++/**
++ * Structure describing memory allocation request
++ *
++ * \sa amdgpu_bo_alloc()
++*/
++struct amdgpu_bo_alloc_result {
++	/** Assigned virtual MC Base Address */
++	uint64_t virtual_mc_base_address;
++
++	/** Handle of allocated memory to be used by the given process only. */
++	amdgpu_bo_handle buf_handle;
++};
++
++/**
++ * Special UMD specific information associated with buffer.
++ *
++ * It may be need to pass some buffer charactersitic as part
++ * of buffer sharing. Such information are defined UMD and
++ * opaque for libdrm_amdgpu as well for kernel driver.
++ *
++ * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,
++ *     amdgpu_bo_import(), amdgpu_bo_export
++ *
++*/
++struct amdgpu_bo_metadata {
++	/** Special flag associated with surface */
++	uint64_t flags;
++
++	/**
++	 * ASIC-specific tiling information (also used by DCE).
++	 * The encoding is defined by the AMDGPU_TILING_* definitions.
++	 */
++	uint64_t tiling_info;
++
++	/** Size of metadata associated with the buffer, in bytes. */
++	uint32_t size_metadata;
++
++	/** UMD specific metadata. Opaque for kernel */
++	uint32_t umd_metadata[64];
++};
++
++/**
++ * Structure describing allocated buffer. Client may need
++ * to query such information as part of 'sharing' buffers mechanism
++ *
++ * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),
++ *     amdgpu_bo_import(), amdgpu_bo_export()
++*/
++struct amdgpu_bo_info {
++	/** Allocated memory size */
++	uint64_t alloc_size;
++
++	/**
++	 * It may be required to have some specific alignment requirements
++	 * for physical back-up storage.
++	 */
++	uint64_t phys_alignment;
++
++	/**
++	 * Assigned virtual MC Base Address.
++	 * \note  This information will be returned only if this buffer was
++	 * allocated in the same process otherwise 0 will be returned.
++	*/
++	uint64_t virtual_mc_base_address;
++
++	/** Heap where to allocate memory. */
++	uint32_t preferred_heap;
++
++	/** Additional allocation flags. */
++	uint64_t alloc_flags;
++
++	/** Metadata associated with buffer if any. */
++	struct amdgpu_bo_metadata metadata;
++};
++
++/**
++ * Structure with information about "imported" buffer
++ *
++ * \sa amdgpu_bo_import()
++ *
++ */
++struct amdgpu_bo_import_result {
++	/** Handle of memory/buffer to use */
++	amdgpu_bo_handle  buf_handle;
++
++	 /** Buffer size */
++	uint64_t alloc_size;
++
++	 /** Assigned virtual MC Base Address */
++	uint64_t virtual_mc_base_address;
++};
++
++
++/**
++ *
++ * Structure to describe GDS partitioning information.
++ * \note OA and GWS resources are asscoiated with GDS partition
++ *
++ * \sa amdgpu_gpu_resource_query_gds_info
++ *
++*/
++struct amdgpu_gds_resource_info {
++	uint32_t   gds_gfx_partition_size;
++	uint32_t   compute_partition_size;
++	uint32_t   gds_total_size;
++	uint32_t   gws_per_gfx_partition;
++	uint32_t   gws_per_compute_partition;
++	uint32_t   oa_per_gfx_partition;
++	uint32_t   oa_per_compute_partition;
++};
++
++
++
++/**
++ *  Structure describing result of request to allocate GDS
++ *
++ *  \sa amdgpu_gpu_resource_gds_alloc
++ *
++*/
++struct amdgpu_gds_alloc_info {
++	/** Handle assigned to gds allocation */
++	amdgpu_bo_handle resource_handle;
++
++	/** How much was really allocated */
++	uint32_t   gds_memory_size;
++
++	/** Number of GWS resources allocated */
++	uint32_t   gws;
++
++	/** Number of OA resources allocated */
++	uint32_t   oa;
++};
++
++/**
++ * Structure to described allocated command buffer (a.k.a. IB)
++ *
++ * \sa amdgpu_cs_alloc_ib()
++ *
++*/
++struct amdgpu_cs_ib_alloc_result {
++	/** IB allocation handle */
++	amdgpu_ib_handle handle;
++
++	/** Assigned GPU VM MC Address of command buffer */
++	uint64_t	mc_address;
++
++	/** Address to be used for CPU access */
++	void		*cpu;
++};
++
++/**
++ * Structure describing IB
++ *
++ * \sa amdgpu_cs_request, amdgpu_cs_submit()
++ *
++*/
++struct amdgpu_cs_ib_info {
++	/** Special flags */
++	uint64_t      flags;
++
++	/** Handle of command buffer */
++	amdgpu_ib_handle ib_handle;
++
++	/**
++	 * Size of Command Buffer to be submitted.
++	 *   - The size is in units of dwords (4 bytes).
++	 *   - Must be less or equal to the size of allocated IB
++	 *   - Could be 0
++	 */
++	uint32_t       size;
++};
++
++/**
++ * Structure describing submission request
++ *
++ * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx
++ *
++ * \sa amdgpu_cs_submit()
++*/
++struct amdgpu_cs_request {
++	/** Specify flags with additional information */
++	uint64_t	flags;
++
++	/** Specify HW IP block type to which to send the IB. */
++	unsigned	ip_type;
++
++	/** IP instance index if there are several IPs of the same type. */
++	unsigned	ip_instance;
++
++	/**
++	 * Specify ring index of the IP. We could have several rings
++	 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
++	 */
++	uint32_t           ring;
++
++	/**
++	 * Specify number of resource handles passed.
++	 * Size of 'handles' array
++	 *
++	 */
++	uint32_t number_of_resources;
++
++	/** Array of resources used by submission. */
++	amdgpu_bo_handle   *resources;
++
++	/** Array of resources flags. This is optional and can be NULL. */
++	uint8_t *resource_flags;
++
++	/** Number of IBs to submit in the field ibs. */
++	uint32_t number_of_ibs;
++
++	/**
++	 * IBs to submit. Those IBs will be submit together as single entity
++	 */
++	struct amdgpu_cs_ib_info *ibs;
++};
++
++/**
++ * Structure describing request to check submission state using fence
++ *
++ * \sa amdgpu_cs_query_fence_status()
++ *
++*/
++struct amdgpu_cs_query_fence {
++
++	/** In which context IB was sent to execution */
++	amdgpu_context_handle  context;
++
++	/** Timeout in nanoseconds. */
++	uint64_t  timeout_ns;
++
++	/** To which HW IP type the fence belongs */
++	unsigned  ip_type;
++
++	/** IP instance index if there are several IPs of the same type. */
++	unsigned ip_instance;
++
++	/** Ring index of the HW IP */
++	uint32_t      ring;
++
++	/** Flags */
++	uint64_t  flags;
++
++	/** Specify fence for which we need to check
++	 * submission status.*/
++	uint64_t	fence;
++};
++
++/**
++ * Structure which provide information about GPU VM MC Address space
++ * alignments requirements
++ *
++ * \sa amdgpu_query_buffer_size_alignment
++ */
++struct amdgpu_buffer_size_alignments {
++	/** Size alignment requirement for allocation in
++	 * local memory */
++	uint64_t size_local;
++
++	/**
++	 * Size alignment requirement for allocation in remote memory
++	 */
++	uint64_t size_remote;
++};
++
++
++/**
++ * Structure which provide information about heap
++ *
++ * \sa amdgpu_query_heap_info()
++ *
++ */
++struct amdgpu_heap_info {
++	/** Theoretical max. available memory in the given heap */
++	uint64_t  heap_size;
++
++	/**
++	 * Number of bytes allocated in the heap. This includes all processes
++	 * and private allocations in the kernel. It changes when new buffers
++	 * are allocated, freed, and moved. It cannot be larger than
++	 * heap_size.
++	 */
++	uint64_t  heap_usage;
++
++	/**
++	 * Theoretical possible max. size of buffer which
++	 * could be allocated in the given heap
++	 */
++	uint64_t  max_allocation;
++};
++
++
++
++/**
++ * Describe GPU h/w info needed for UMD correct initialization
++ *
++ * \sa amdgpu_query_gpu_info()
++*/
++struct amdgpu_gpu_info {
++	/** Asic id */
++	uint32_t asic_id;
++	/**< Chip revision */
++	uint32_t chip_rev;
++	/** Chip external revision */
++	uint32_t chip_external_rev;
++	/** Family ID */
++	uint32_t family_id;
++	/** Special flags */
++	uint64_t ids_flags;
++	/** max engine clock*/
++	uint64_t max_engine_clk;
++	/** number of shader engines */
++	uint32_t num_shader_engines;
++	/** number of shader arrays per engine */
++	uint32_t num_shader_arrays_per_engine;
++	/**  Number of available good shader pipes */
++	uint32_t avail_quad_shader_pipes;
++	/**  Max. number of shader pipes.(including good and bad pipes  */
++	uint32_t max_quad_shader_pipes;
++	/** Number of parameter cache entries per shader quad pipe */
++	uint32_t cache_entries_per_quad_pipe;
++	/**  Number of available graphics context */
++	uint32_t num_hw_gfx_contexts;
++	/** Number of render backend pipes */
++	uint32_t rb_pipes;
++	/** Active render backend pipe number */
++	uint32_t active_rb_pipes;
++	/**  Enabled render backend pipe mask */
++	uint32_t enabled_rb_pipes_mask;
++	/** Frequency of GPU Counter */
++	uint32_t gpu_counter_freq;
++	/** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */
++	uint32_t backend_disable[4];
++	/** Value of MC_ARB_RAMCFG register*/
++	uint32_t mc_arb_ramcfg;
++	/** Value of GB_ADDR_CONFIG */
++	uint32_t gb_addr_cfg;
++	/** Values of the GB_TILE_MODE0..31 registers */
++	uint32_t gb_tile_mode[32];
++	/** Values of GB_MACROTILE_MODE0..15 registers */
++	uint32_t gb_macro_tile_mode[16];
++	/** Value of PA_SC_RASTER_CONFIG register per SE */
++	uint32_t pa_sc_raster_cfg[4];
++	/** Value of PA_SC_RASTER_CONFIG_1 register per SE */
++	uint32_t pa_sc_raster_cfg1[4];
++	/* CU info */
++	uint32_t cu_active_number;
++	uint32_t cu_ao_mask;
++	uint32_t cu_bitmap[4][4];
++};
++
++
++/*--------------------------------------------------------------------------*/
++/*------------------------- Functions --------------------------------------*/
++/*--------------------------------------------------------------------------*/
++
++/*
++ * Initialization / Cleanup
++ *
++*/
++
++
++/**
++ *
++ * \param   fd            - \c [in]  File descriptor for AMD GPU device
++ *                                   received previously as the result of
++ *                                   e.g. drmOpen() call.
++ *                                   For legacy fd type, the DRI2/DRI3 authentication
++ *                                   should be done before calling this function.
++ * \param   major_version - \c [out] Major version of library. It is assumed
++ *                                   that adding new functionality will cause
++ *                                   increase in major version
++ * \param   minor_version - \c [out] Minor version of library
++ * \param   device_handle - \c [out] Pointer to opaque context which should
++ *                                   be passed as the first parameter on each
++ *                                   API call
++ *
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ *
++ * \sa amdgpu_device_deinitialize()
++*/
++int amdgpu_device_initialize(int fd,
++			     uint32_t *major_version,
++			     uint32_t *minor_version,
++			     amdgpu_device_handle *device_handle);
++
++
++
++/**
++ *
++ * When access to such library does not needed any more the special
++ * function must be call giving opportunity to clean up any
++ * resources if needed.
++ *
++ * \param   device_handle - \c [in]  Context associated with file
++ *                                   descriptor for AMD GPU device
++ *                                   received previously as the
++ *                                   result e.g. of drmOpen() call.
++ *
++ * \return  0 on success\n
++ *         >0 - AMD specific error code\n
++ *         <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_device_initialize()
++ *
++*/
++int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
++
++
++/*
++ * Memory Management
++ *
++*/
++
++/**
++ * Allocate memory to be used by UMD for GPU related operations
++ *
++ * \param   dev		 - \c [in] Device handle.
++ *				   See #amdgpu_device_initialize()
++ * \param   alloc_buffer - \c [in] Pointer to the structure describing an
++ *				   allocation request
++ * \param   info	 - \c [out] Pointer to structure which return
++ *				    information about allocated memory
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_bo_free()
++*/
++int amdgpu_bo_alloc(amdgpu_device_handle dev,
++		    struct amdgpu_bo_alloc_request *alloc_buffer,
++		    struct amdgpu_bo_alloc_result *info);
++
++/**
++ * Associate opaque data with buffer to be queried by another UMD
++ *
++ * \param   dev	       - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   buf_handle - \c [in] Buffer handle
++ * \param   info       - \c [in] Metadata to associated with buffer
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++*/
++int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
++			   struct amdgpu_bo_metadata *info);
++
++/**
++ * Query buffer information including metadata previusly associated with
++ * buffer.
++ *
++ * \param   dev	       - \c [in] Device handle.
++ *				 See #amdgpu_device_initialize()
++ * \param   buf_handle - \c [in]   Buffer handle
++ * \param   info       - \c [out]  Structure describing buffer
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
++*/
++int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle,
++			 struct amdgpu_bo_info *info);
++
++/**
++ * Allow others to get access to buffer
++ *
++ * \param   dev		  - \c [in] Device handle.
++ *				    See #amdgpu_device_initialize()
++ * \param   buf_handle    - \c [in] Buffer handle
++ * \param   type          - \c [in] Type of handle requested
++ * \param   shared_handle - \c [out] Special "shared" handle
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_bo_import()
++ *
++*/
++int amdgpu_bo_export(amdgpu_bo_handle buf_handle,
++		     enum amdgpu_bo_handle_type type,
++		     uint32_t *shared_handle);
++
++/**
++ * Request access to "shared" buffer
++ *
++ * \param   dev		  - \c [in] Device handle.
++ *				    See #amdgpu_device_initialize()
++ * \param   type	  - \c [in] Type of handle requested
++ * \param   shared_handle - \c [in] Shared handle received as result "import"
++ *				     operation
++ * \param   output        - \c [out] Pointer to structure with information
++ *				     about imported buffer
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \note  Buffer must be "imported" only using new "fd" (different from
++ *	  one used by "exporter").
++ *
++ * \sa amdgpu_bo_export()
++ *
++*/
++int amdgpu_bo_import(amdgpu_device_handle dev,
++		     enum amdgpu_bo_handle_type type,
++		     uint32_t shared_handle,
++		     struct amdgpu_bo_import_result *output);
++
++/**
++ * Free previosuly allocated memory
++ *
++ * \param   dev	       - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   buf_handle - \c [in]  Buffer handle to free
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \note In the case of memory shared between different applications all
++ *	 resources will be “physically” freed only all such applications
++ *	 will be terminated
++ * \note If is UMD responsibility to ‘free’ buffer only when there is no
++ *	 more GPU access
++ *
++ * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
++ *
++*/
++int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
++
++/**
++ * Request CPU access to GPU accessable memory
++ *
++ * \param   buf_handle - \c [in] Buffer handle
++ * \param   cpu        - \c [out] CPU address to be used for access
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_bo_cpu_unmap()
++ *
++*/
++int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
++
++/**
++ * Release CPU access to GPU memory
++ *
++ * \param   buf_handle  - \c [in] Buffer handle
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_bo_cpu_map()
++ *
++*/
++int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
++
++
++/**
++ * Wait until a buffer is not used by the device.
++ *
++ * \param   dev           - \c [in] Device handle. See #amdgpu_lib_initialize()
++ * \param   buf_handle    - \c [in] Buffer handle.
++ * \param   timeout_ns    - Timeout in nanoseconds.
++ * \param   buffer_busy   - 0 if buffer is idle, all GPU access was completed
++ *                            and no GPU access is scheduled.
++ *                          1 GPU access is in fly or scheduled
++ *
++ * \return   0 - on success
++ *          <0 - AMD specific error code
++ */
++int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
++			    uint64_t timeout_ns,
++			    bool *buffer_busy);
++
++
++/*
++ * Special GPU Resources
++ *
++*/
++
++
++
++/**
++ * Query information about GDS
++ *
++ * \param   dev	     - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   gds_info - \c [out] Pointer to structure to get GDS information
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_gpu_resource_query_gds_info(amdgpu_device_handle dev,
++					struct amdgpu_gds_resource_info *
++								gds_info);
++
++
++/**
++ * Allocate GDS partitions
++ *
++ * \param   dev	       - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   gds_size   - \c [in] Size of gds allocation. Must be aligned
++ *				accordingly.
++ * \param   alloc_info - \c [out] Pointer to structure to receive information
++ *				  about allocation
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ *
++*/
++int amdgpu_gpu_resource_gds_alloc(amdgpu_device_handle dev,
++				   uint32_t gds_size,
++				   struct amdgpu_gds_alloc_info *alloc_info);
++
++
++
++
++/**
++ * Release GDS resource. When GDS and associated resources not needed any
++ * more UMD should free them
++ *
++ * \param   dev	   - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   handle - \c [in] Handle assigned to GDS allocation
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_gpu_resource_gds_free(amdgpu_bo_handle handle);
++
++
++
++/*
++ * GPU Execution context
++ *
++*/
++
++/**
++ * Create GPU execution Context
++ *
++ * For the purpose of GPU Scheduler and GPU Robustness extensions it is
++ * necessary to have information/identify rendering/compute contexts.
++ * It also may be needed to associate some specific requirements with such
++ * contexts.  Kernel driver will guarantee that submission from the same
++ * context will always be executed in order (first come, first serve).
++ *
++ *
++ * \param   dev	    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   context - \c [out] GPU Context handle
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_cs_ctx_free()
++ *
++*/
++int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
++			 amdgpu_context_handle *context);
++
++/**
++ *
++ * Destroy GPU execution context when not needed any more
++ *
++ * \param   dev	    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   context - \c [in] GPU Context handle
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_cs_ctx_create()
++ *
++*/
++int amdgpu_cs_ctx_free(amdgpu_device_handle dev,
++		       amdgpu_context_handle context);
++
++/**
++ * Query reset state for the specific GPU Context
++ *
++ * \param   dev	    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   context - \c [in]  GPU Context handle
++ * \param   state   - \c [out] Reset state status
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_cs_ctx_create()
++ *
++*/
++int amdgpu_cs_query_reset_state(amdgpu_device_handle dev,
++				amdgpu_context_handle context,
++				enum amdgpu_cs_ctx_reset_state *state);
++
++
++/*
++ * Command Buffers Management
++ *
++*/
++
++
++/**
++ * Allocate memory to be filled with PM4 packets and be served as the first
++ * entry point of execution (a.k.a. Indirect Buffer)
++ *
++ * \param   dev	    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   context - \c [in]  GPU Context which will use IB
++ * \param   ib_size - \c [in]  Size of allocation
++ * \param   output  - \c [out] Pointer to structure to get information about
++ *				   allocated IB
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \sa amdgpu_cs_free_ib()
++ *
++*/
++int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
++		       amdgpu_context_handle context,
++		       enum amdgpu_cs_ib_size ib_size,
++		       struct amdgpu_cs_ib_alloc_result *output);
++
++/**
++ * If UMD has allocates IBs which doesn’t need any more than those IBs must
++ * be explicitly freed
++ *
++ * \param   dev	    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   context - \c [in] GPU Context containing IB
++ * \param   handle  - \c [in] IB handle
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \note Libdrm_amdgpu will guarantee that it will correctly detect when it
++ *	is safe to return IB to free pool
++ *
++ * \sa amdgpu_cs_alloc_ib()
++ *
++*/
++int amdgpu_cs_free_ib(amdgpu_device_handle dev,
++		      amdgpu_context_handle context,
++		      amdgpu_ib_handle handle);
++
++/**
++ * Send request to submit command buffers to hardware.
++ *
++ * Kernel driver could use GPU Scheduler to make decision when physically
++ * sent this request to the hardware. Accordingly this request could be put
++ * in queue and sent for execution later. The only guarantee is that request
++ * from the same GPU context to the same ip:ip_instance:ring will be executed in
++ * order.
++ *
++ *
++ * \param   dev		       - \c [in]  Device handle.
++ *					  See #amdgpu_device_initialize()
++ * \param   context            - \c [in]  GPU Context
++ * \param   flags              - \c [in]  Global submission flags
++ * \param   ibs_request        - \c [in]  Pointer to submission requests.
++ *					  We could submit to the several
++ *					  engines/rings simulteniously as
++ *					  'atomic' operation
++ * \param   number_of_requests - \c [in]  Number of submission requests
++ * \param   fences             - \c [out] Pointer to array of data to get
++ *					  fences to identify submission
++ *					  requests. Timestamps are valid
++ *					  in this GPU context and could be used
++ *					  to identify/detect completion of
++ *					  submission request
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \note It is assumed that by default IB will be returned to free pool
++ *	 automatically by libdrm_amdgpu when submission will completed.
++ *	 It is possible for UMD to make decision to re-use the same IB in
++ *	 this case it should be explicitly freed.\n
++ *	 Accordingly, by default, after submission UMD should not touch passed
++ *	 IBs. If UMD needs to re-use IB then the special flag AMDGPU_CS_REUSE_IB
++ *	 must be passed.
++ *
++ * \note It is required to pass correct resource list with buffer handles
++ *	 which will be accessible by command buffers from submission
++ *	 This will allow kernel driver to correctly implement "paging".
++ *	 Failure to do so will have unpredictable results.
++ *
++ * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),
++ *     amdgpu_cs_query_fence_status()
++ *
++*/
++int amdgpu_cs_submit(amdgpu_device_handle  dev,
++		     amdgpu_context_handle context,
++		     uint64_t flags,
++		     struct amdgpu_cs_request *ibs_request,
++		     uint32_t number_of_requests,
++		     uint64_t *fences);
++
++/**
++ *  Query status of Command Buffer Submission
++ *
++ * \param   dev	    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   fence   - \c [in] Structure describing fence to query
++ * \param   expired - \c [out] If fence expired or not.\n
++ *				0  – if fence is not expired\n
++ *				!0 - otherwise
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++ * \note If UMD wants only to check operation status and returned immediately
++ *	 then timeout value as 0 must be passed. In this case success will be
++ *	 returned in the case if submission was completed or timeout error
++ *	 code.
++ *
++ * \sa amdgpu_cs_submit()
++*/
++int amdgpu_cs_query_fence_status(amdgpu_device_handle dev,
++				 struct amdgpu_cs_query_fence *fence,
++				 uint32_t *expired);
++
++
++/*
++ * Query / Info API
++ *
++*/
++
++
++/**
++ * Query allocation size alignments
++ *
++ * UMD should query information about GPU VM MC size alignments requirements
++ * to be able correctly choose required allocation size and implement
++ * internal optimization if needed.
++ *
++ * \param   dev  - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   info - \c [out] Pointer to structure to get size alignment
++ *			  requirements
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
++					struct amdgpu_buffer_size_alignments
++									*info);
++
++
++
++/**
++ * Query firmware versions
++ *
++ * \param   dev	        - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   fw_type     - \c [in] AMDGPU_INFO_FW_*
++ * \param   ip_instance - \c [in] Index of the IP block of the same type.
++ * \param   index       - \c [in] Index of the engine. (for SDMA and MEC)
++ * \param   version     - \c [out] Pointer to to the "version" return value
++ * \param   feature     - \c [out] Pointer to to the "feature" return value
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
++				  unsigned ip_instance, unsigned index,
++				  uint32_t *version, uint32_t *feature);
++
++
++
++/**
++ * Query the number of HW IP instances of a certain type.
++ *
++ * \param   dev      - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   type     - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
++ * \param   count    - \c [out] Pointer to structure to get information
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++*/
++int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
++			     uint32_t *count);
++
++
++
++/**
++ * Query engine information
++ *
++ * This query allows UMD to query information different engines and their
++ * capabilities.
++ *
++ * \param   dev         - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   type        - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
++ * \param   ip_instance - \c [in] Index of the IP block of the same type.
++ * \param   info        - \c [out] Pointer to structure to get information
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++*/
++int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
++			    unsigned ip_instance,
++			    struct drm_amdgpu_info_hw_ip *info);
++
++
++
++
++/**
++ * Query heap information
++ *
++ * This query allows UMD to query potentially available memory resources and
++ * adjust their logic if necessary.
++ *
++ * \param   dev  - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   heap - \c [in] Heap type
++ * \param   info - \c [in] Pointer to structure to get needed information
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_query_heap_info(amdgpu_device_handle dev,
++			    uint32_t heap,
++				uint32_t flags,
++			    struct amdgpu_heap_info *info);
++
++
++
++/**
++ * Get the CRTC ID from the mode object ID
++ *
++ * \param   dev    - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   id     - \c [in] Mode object ID
++ * \param   result - \c [in] Pointer to the CRTC ID
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
++			      int32_t *result);
++
++
++
++/**
++ * Query GPU H/w Info
++ *
++ * Query hardware specific information
++ *
++ * \param   dev  - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   heap - \c [in] Heap type
++ * \param   info - \c [in] Pointer to structure to get needed information
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX Error code
++ *
++*/
++int amdgpu_query_gpu_info(amdgpu_device_handle dev,
++			   struct amdgpu_gpu_info *info);
++
++
++
++/**
++ * Query hardware or driver information.
++ *
++ * The return size is query-specific and depends on the "info_id" parameter.
++ * No more than "size" bytes is returned.
++ *
++ * \param   dev     - \c [in] Device handle. See #amdgpu_device_initialize()
++ * \param   info_id - \c [in] AMDGPU_INFO_*
++ * \param   size    - \c [in] Size of the returned value.
++ * \param   value   - \c [out] Pointer to the return value.
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX error code
++ *
++*/
++int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
++		      unsigned size, void *value);
++
++
++
++/**
++ * Read a set of consecutive memory-mapped registers.
++ * Not all registers are allowed to be read by userspace.
++ *
++ * \param   dev          - \c [in] Device handle. See #amdgpu_device_initialize(
++ * \param   dword_offset - \c [in] Register offset in dwords
++ * \param   count        - \c [in] The number of registers to read starting
++ *                                 from the offset
++ * \param   instance     - \c [in] GRBM_GFX_INDEX selector. It may have other
++ *                                 uses. Set it to 0xffffffff if unsure.
++ * \param   flags        - \c [in] Flags with additional information.
++ * \param   values       - \c [out] The pointer to return values.
++ *
++ * \return   0 on success\n
++ *          >0 - AMD specific error code\n
++ *          <0 - Negative POSIX error code
++ *
++*/
++int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
++			     unsigned count, uint32_t instance, uint32_t flags,
++			     uint32_t *values);
++
++
++
++/**
++ * Request GPU access to user allocated memory e.g. via "malloc"
++ *
++ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
++ * \param cpu - [in] CPU address of user allocated memory which we
++ * want to map to GPU address space (make GPU accessible)
++ * (This address must be correctly aligned).
++ * \param size - [in] Size of allocation (must be correctly aligned)
++ * \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as resource
++ * on submission and be used in other operations.(e.g. for VA submission)
++ * ( Temporally defined amdgpu_bo_alloc_result as parameter for return mc address. )
++ *
++ *
++ * \return 0 on success
++ * >0 - AMD specific error code
++ * <0 - Negative POSIX Error code
++ *
++ *
++ * \note
++ * This call doesn't guarantee that such memory will be persistently
++ * "locked" / make non-pageable. The purpose of this call is to provide
++ * opportunity for GPU get access to this resource during submission.
++ *
++ * The maximum amount of memory which could be mapped in this call depends
++ * if overcommit is disabled or not. If overcommit is disabled than the max.
++ * amount of memory to be pinned will be limited by left "free" size in total
++ * amount of memory which could be locked simultaneously ("GART" size).
++ *
++ * Supported (theoretical) max. size of mapping is restricted only by
++ * "GART" size.
++ *
++ * It is responsibility of caller to correctly specify access rights
++ * on VA assignment.
++*/
++int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
++				    void *cpu,
++				    uint64_t size,
++				    struct amdgpu_bo_alloc_result *info);
++
++
++#endif /* #ifdef _amdgpu_h_ */
++
++
+diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
+new file mode 100644
+index 0000000..ce7e9d1
+--- /dev/null
++++ b/amdgpu/amdgpu_bo.c
+@@ -0,0 +1,622 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#define _FILE_OFFSET_BITS 64
++#include <stdlib.h>
++#include <stdio.h>
++#include <string.h>
++#include <errno.h>
++#include <fcntl.h>
++#include <unistd.h>
++#include <sys/ioctl.h>
++#include <sys/mman.h>
++#include <sys/time.h>
++
++#include "xf86drm.h"
++#include "amdgpu_drm.h"
++#include "amdgpu_internal.h"
++#include "util_hash_table.h"
++
++static void amdgpu_close_kms_handle(amdgpu_device_handle dev,
++				     uint32_t handle)
++{
++	struct drm_gem_close args = {};
++
++	args.handle = handle;
++	drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args);
++}
++
++void amdgpu_bo_free_internal(amdgpu_bo_handle bo)
++{
++	/* Remove the buffer from the hash tables. */
++	pthread_mutex_lock(&bo->dev->bo_table_mutex);
++	util_hash_table_remove(bo->dev->bo_handles,
++			       (void*)(uintptr_t)bo->handle);
++	if (bo->flink_name) {
++		util_hash_table_remove(bo->dev->bo_flink_names,
++				       (void*)(uintptr_t)bo->flink_name);
++	}
++	pthread_mutex_unlock(&bo->dev->bo_table_mutex);
++
++	/* Release CPU access. */
++	if (bo->cpu_map_count > 0) {
++		bo->cpu_map_count = 1;
++		amdgpu_bo_cpu_unmap(bo);
++	}
++
++	amdgpu_close_kms_handle(bo->dev, bo->handle);
++	pthread_mutex_destroy(&bo->cpu_access_mutex);
++	amdgpu_vamgr_free_va(&bo->dev->vamgr, bo->virtual_mc_base_address, bo->alloc_size);
++	free(bo);
++}
++
++int amdgpu_bo_alloc(amdgpu_device_handle dev,
++		    struct amdgpu_bo_alloc_request *alloc_buffer,
++		    struct amdgpu_bo_alloc_result *info)
++{
++	struct amdgpu_bo *bo;
++	union drm_amdgpu_gem_create args;
++	unsigned heap = alloc_buffer->preferred_heap;
++	int r = 0;
++
++	/* It's an error if the heap is not specified */
++	if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
++		return -EINVAL;
++
++	bo = calloc(1, sizeof(struct amdgpu_bo));
++	if (!bo)
++		return -ENOMEM;
++
++	atomic_set(&bo->refcount, 1);
++	bo->dev = dev;
++	bo->alloc_size = alloc_buffer->alloc_size;
++
++	memset(&args, 0, sizeof(args));
++	args.in.bo_size = alloc_buffer->alloc_size;
++	args.in.alignment = alloc_buffer->phys_alignment;
++
++	/* Set the placement. */
++	args.in.domains = heap & AMDGPU_GEM_DOMAIN_MASK;
++	args.in.domain_flags = alloc_buffer->flags & AMDGPU_GEM_CREATE_CPU_GTT_MASK;
++
++	/* Allocate the buffer with the preferred heap. */
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
++				&args, sizeof(args));
++	if (r) {
++		free(bo);
++		return r;
++	}
++
++	bo->handle = args.out.handle;
++
++	pthread_mutex_init(&bo->cpu_access_mutex, NULL);
++
++	/* map the buffer to the GPU virtual address space */
++	{
++		union drm_amdgpu_gem_va va;
++
++		memset(&va, 0, sizeof(va));
++
++		bo->virtual_mc_base_address = amdgpu_vamgr_find_va(&dev->vamgr, alloc_buffer->alloc_size, alloc_buffer->phys_alignment);
++
++		va.in.handle = bo->handle;
++		va.in.operation = AMDGPU_VA_OP_MAP;
++		va.in.flags = 	AMDGPU_VM_PAGE_READABLE |
++				AMDGPU_VM_PAGE_WRITEABLE |
++				AMDGPU_VM_PAGE_EXECUTABLE;
++		va.in.va_address = bo->virtual_mc_base_address;
++
++		r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
++		if (r || va.out.result == AMDGPU_VA_RESULT_ERROR) {
++			amdgpu_bo_free_internal(bo);
++			return r;
++		}
++		pthread_mutex_lock(&dev->bo_table_mutex);
++
++		util_hash_table_set(dev->bo_vas,
++				    (void*)(uintptr_t)bo->virtual_mc_base_address, bo);
++		pthread_mutex_unlock(&dev->bo_table_mutex);
++	}
++
++	info->buf_handle = bo;
++	info->virtual_mc_base_address = bo->virtual_mc_base_address;
++	return 0;
++}
++
++int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
++			   struct amdgpu_bo_metadata *info)
++{
++	struct drm_amdgpu_gem_metadata args = {};
++
++	args.handle = bo->handle;
++	args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
++	args.data.flags = info->flags;
++	args.data.tiling_info = info->tiling_info;
++
++	if (info->size_metadata > sizeof(args.data.data))
++		return -EINVAL;
++
++	if (info->size_metadata) {
++		args.data.data_size_bytes = info->size_metadata;
++		memcpy(args.data.data, info->umd_metadata, info->size_metadata);
++	}
++
++	return drmCommandWriteRead(bo->dev->fd,
++				   DRM_AMDGPU_GEM_METADATA,
++				   &args, sizeof(args));
++}
++
++int amdgpu_bo_query_info(amdgpu_bo_handle bo,
++			 struct amdgpu_bo_info *info)
++{
++	struct drm_amdgpu_gem_metadata metadata = {};
++	struct drm_amdgpu_gem_create_in bo_info = {};
++	struct drm_amdgpu_gem_op gem_op = {};
++	int r;
++
++	/* Query metadata. */
++	metadata.handle = bo->handle;
++	metadata.op = AMDGPU_GEM_METADATA_OP_GET_METADATA;
++
++	r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_METADATA,
++				&metadata, sizeof(metadata));
++	if (r)
++		return r;
++
++	if (metadata.data.data_size_bytes >
++	    sizeof(info->metadata.umd_metadata))
++		return -EINVAL;
++
++	/* Query buffer info. */
++	gem_op.handle = bo->handle;
++	gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO;
++	gem_op.value = (intptr_t)&bo_info;
++
++	r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_OP,
++				&gem_op, sizeof(gem_op));
++	if (r)
++		return r;
++
++	memset(info, 0, sizeof(*info));
++	info->alloc_size = bo_info.bo_size;
++	info->phys_alignment = bo_info.alignment;
++	info->virtual_mc_base_address = bo->virtual_mc_base_address;
++	info->preferred_heap = bo_info.domains;
++	info->alloc_flags = bo_info.domain_flags;
++	info->metadata.flags = metadata.data.flags;
++	info->metadata.tiling_info = metadata.data.tiling_info;
++
++	info->metadata.size_metadata = metadata.data.data_size_bytes;
++	if (metadata.data.data_size_bytes > 0)
++		memcpy(info->metadata.umd_metadata, metadata.data.data,
++		       metadata.data.data_size_bytes);
++
++	return 0;
++}
++
++static void amdgpu_add_handle_to_table(amdgpu_bo_handle bo)
++{
++	pthread_mutex_lock(&bo->dev->bo_table_mutex);
++	util_hash_table_set(bo->dev->bo_handles,
++			    (void*)(uintptr_t)bo->handle, bo);
++	pthread_mutex_unlock(&bo->dev->bo_table_mutex);
++}
++
++static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
++{
++	struct drm_gem_flink flink;
++	int fd, dma_fd;
++	uint32_t handle;
++	int r;
++
++	fd = bo->dev->fd;
++	handle = bo->handle;
++	if (bo->flink_name)
++		return 0;
++
++
++	if (bo->dev->flink_fd != bo->dev->fd) {
++		r = drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC,
++				       &dma_fd);
++		if (!r) {
++			r = drmPrimeFDToHandle(bo->dev->flink_fd, dma_fd, &handle);
++			close(dma_fd);
++		}
++		if (r)
++			return r;
++		fd = bo->dev->flink_fd;
++	}
++	memset(&flink, 0, sizeof(flink));
++	flink.handle = handle;
++
++	r = drmIoctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
++	if (r)
++		return r;
++
++	bo->flink_name = flink.name;
++
++	if (bo->dev->flink_fd != bo->dev->fd) {
++		struct drm_gem_close args = {};
++		args.handle = handle;
++		drmIoctl(bo->dev->flink_fd, DRM_IOCTL_GEM_CLOSE, &args);
++	}
++
++	pthread_mutex_lock(&bo->dev->bo_table_mutex);
++	util_hash_table_set(bo->dev->bo_flink_names,
++			    (void*)(uintptr_t)bo->flink_name,
++			    bo);
++	pthread_mutex_unlock(&bo->dev->bo_table_mutex);
++
++	return 0;
++}
++
++int amdgpu_bo_export(amdgpu_bo_handle bo,
++		     enum amdgpu_bo_handle_type type,
++		     uint32_t *shared_handle)
++{
++	int r;
++
++	switch (type) {
++	case amdgpu_bo_handle_type_gem_flink_name:
++		r = amdgpu_bo_export_flink(bo);
++		if (r)
++			return r;
++
++		*shared_handle = bo->flink_name;
++		return 0;
++
++	case amdgpu_bo_handle_type_kms:
++		r = amdgpu_bo_export_flink(bo);
++		if (r)
++			return r;
++
++		amdgpu_add_handle_to_table(bo);
++		*shared_handle = bo->handle;
++		return 0;
++
++	case amdgpu_bo_handle_type_dma_buf_fd:
++		amdgpu_add_handle_to_table(bo);
++		return drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC,
++				       (int*)shared_handle);
++	}
++	return -EINVAL;
++}
++
++int amdgpu_bo_import(amdgpu_device_handle dev,
++		     enum amdgpu_bo_handle_type type,
++		     uint32_t shared_handle,
++		     struct amdgpu_bo_import_result *output)
++{
++	struct drm_gem_open open_arg = {};
++	union drm_amdgpu_gem_va va;
++	struct amdgpu_bo *bo = NULL;
++	int r;
++	int dma_fd;
++	uint64_t dma_buf_size = 0;
++
++	/* Convert a DMA buf handle to a KMS handle now. */
++	if (type == amdgpu_bo_handle_type_dma_buf_fd) {
++		uint32_t handle;
++		off_t size;
++
++		/* Get a KMS handle. */
++		r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle);
++		if (r) {
++			return r;
++		}
++
++		/* Query the buffer size. */
++		size = lseek(shared_handle, 0, SEEK_END);
++		if (size == (off_t)-1) {
++			amdgpu_close_kms_handle(dev, handle);
++			return -errno;
++		}
++		lseek(shared_handle, 0, SEEK_SET);
++
++		dma_buf_size = size;
++		shared_handle = handle;
++	}
++
++	/* We must maintain a list of pairs <handle, bo>, so that we always
++	 * return the same amdgpu_bo instance for the same handle. */
++	pthread_mutex_lock(&dev->bo_table_mutex);
++
++	/* If we have already created a buffer with this handle, find it. */
++	switch (type) {
++	case amdgpu_bo_handle_type_gem_flink_name:
++		bo = util_hash_table_get(dev->bo_flink_names,
++					 (void*)(uintptr_t)shared_handle);
++		break;
++
++	case amdgpu_bo_handle_type_dma_buf_fd:
++		bo = util_hash_table_get(dev->bo_handles,
++					 (void*)(uintptr_t)shared_handle);
++		break;
++
++	case amdgpu_bo_handle_type_kms:
++		/* Importing a KMS handle in not allowed. */
++		pthread_mutex_unlock(&dev->bo_table_mutex);
++		return -EPERM;
++
++	default:
++		pthread_mutex_unlock(&dev->bo_table_mutex);
++		return -EINVAL;
++	}
++
++	if (bo) {
++		pthread_mutex_unlock(&dev->bo_table_mutex);
++
++		/* The buffer already exists, just bump the refcount. */
++		atomic_inc(&bo->refcount);
++
++		output->buf_handle = bo;
++		output->alloc_size = bo->alloc_size;
++		output->virtual_mc_base_address =
++			bo->virtual_mc_base_address;
++		return 0;
++	}
++
++	bo = calloc(1, sizeof(struct amdgpu_bo));
++	if (!bo) {
++		pthread_mutex_unlock(&dev->bo_table_mutex);
++		if (type == amdgpu_bo_handle_type_dma_buf_fd) {
++			amdgpu_close_kms_handle(dev, shared_handle);
++		}
++		return -ENOMEM;
++	}
++
++	/* Open the handle. */
++	switch (type) {
++	case amdgpu_bo_handle_type_gem_flink_name:
++		open_arg.name = shared_handle;
++		r = drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_OPEN, &open_arg);
++		if (r) {
++			free(bo);
++			pthread_mutex_unlock(&dev->bo_table_mutex);
++			return r;
++		}
++
++		bo->handle = open_arg.handle;
++		if (dev->flink_fd != dev->fd) {
++			r = drmPrimeHandleToFD(dev->flink_fd, bo->handle, DRM_CLOEXEC, &dma_fd);
++			if (r) {
++				free(bo);
++				pthread_mutex_unlock(&dev->bo_table_mutex);
++				return r;
++			}
++			r = drmPrimeFDToHandle(dev->fd, dma_fd, &bo->handle );
++
++			close(dma_fd);
++
++			if (r) {
++				free(bo);
++				pthread_mutex_unlock(&dev->bo_table_mutex);
++				return r;
++			}
++		}
++		bo->flink_name = shared_handle;
++		bo->alloc_size = open_arg.size;
++		util_hash_table_set(dev->bo_flink_names,
++				    (void*)(uintptr_t)bo->flink_name, bo);
++		break;
++
++	case amdgpu_bo_handle_type_dma_buf_fd:
++		bo->handle = shared_handle;
++		bo->alloc_size = dma_buf_size;
++		break;
++
++	case amdgpu_bo_handle_type_kms:
++		assert(0); /* unreachable */
++	}
++
++	/* Initialize it. */
++	atomic_set(&bo->refcount, 1);
++	bo->dev = dev;
++	pthread_mutex_init(&bo->cpu_access_mutex, NULL);
++
++	bo->virtual_mc_base_address = amdgpu_vamgr_find_va(&dev->vamgr, bo->alloc_size, 1 << 20);
++
++	memset(&va, 0, sizeof(va));
++	va.in.handle = bo->handle;
++	va.in.operation = AMDGPU_VA_OP_MAP;
++	va.in.va_address = bo->virtual_mc_base_address;
++	va.in.flags =	AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
++			AMDGPU_VM_PAGE_EXECUTABLE;
++
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
++	if (r || va.out.result == AMDGPU_VA_RESULT_ERROR) {
++		pthread_mutex_unlock(&dev->bo_table_mutex);
++		amdgpu_vamgr_free_va(&dev->vamgr, bo->virtual_mc_base_address, bo->alloc_size);
++		amdgpu_bo_reference(&bo, NULL);
++		return r;
++	}
++
++	util_hash_table_set(dev->bo_vas,
++			    (void*)(uintptr_t)bo->virtual_mc_base_address, bo);
++	util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo);
++	pthread_mutex_unlock(&dev->bo_table_mutex);
++
++	output->buf_handle = bo;
++	output->alloc_size = bo->alloc_size;
++	output->virtual_mc_base_address = bo->virtual_mc_base_address;
++	return 0;
++}
++
++int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
++{
++	/* Just drop the reference. */
++	amdgpu_bo_reference(&buf_handle, NULL);
++	return 0;
++}
++
++int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
++{
++	union drm_amdgpu_gem_mmap args;
++	void *ptr;
++	int r;
++
++	pthread_mutex_lock(&bo->cpu_access_mutex);
++
++	if (bo->cpu_ptr) {
++		/* already mapped */
++		assert(bo->cpu_map_count > 0);
++		bo->cpu_map_count++;
++		*cpu = bo->cpu_ptr;
++		pthread_mutex_unlock(&bo->cpu_access_mutex);
++		return 0;
++	}
++
++	assert(bo->cpu_map_count == 0);
++
++	memset(&args, 0, sizeof(args));
++
++	/* Query the buffer address (args.addr_ptr).
++	 * The kernel driver ignores the offset and size parameters. */
++	args.in.handle = bo->handle;
++
++	r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_MMAP, &args,
++				sizeof(args));
++	if (r) {
++		pthread_mutex_unlock(&bo->cpu_access_mutex);
++		return r;
++	}
++
++	/* Map the buffer. */
++	ptr = mmap(NULL, bo->alloc_size, PROT_READ | PROT_WRITE, MAP_SHARED,
++		   bo->dev->fd, args.out.addr_ptr);
++	if (ptr == MAP_FAILED) {
++		pthread_mutex_unlock(&bo->cpu_access_mutex);
++		return -errno;
++	}
++
++	bo->cpu_ptr = ptr;
++	bo->cpu_map_count = 1;
++	pthread_mutex_unlock(&bo->cpu_access_mutex);
++
++	*cpu = ptr;
++	return 0;
++}
++
++int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
++{
++	int r;
++
++	pthread_mutex_lock(&bo->cpu_access_mutex);
++	assert(bo->cpu_map_count >= 0);
++
++	if (bo->cpu_map_count == 0) {
++		/* not mapped */
++		pthread_mutex_unlock(&bo->cpu_access_mutex);
++		return -EBADMSG;
++	}
++
++	bo->cpu_map_count--;
++	if (bo->cpu_map_count > 0) {
++		/* mapped multiple times */
++		pthread_mutex_unlock(&bo->cpu_access_mutex);
++		return 0;
++	}
++
++	r = munmap(bo->cpu_ptr, bo->alloc_size) == 0 ? 0 : -errno;
++	bo->cpu_ptr = NULL;
++	pthread_mutex_unlock(&bo->cpu_access_mutex);
++	return r;
++}
++
++int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
++				struct amdgpu_buffer_size_alignments *info)
++{
++	info->size_local = dev->dev_info.pte_fragment_size;
++	info->size_remote = dev->dev_info.gart_page_size;
++	return 0;
++}
++
++int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
++			    uint64_t timeout_ns,
++			    bool *busy)
++{
++	union drm_amdgpu_gem_wait_idle args;
++	int r;
++
++	memset(&args, 0, sizeof(args));
++	args.in.handle = bo->handle;
++	args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
++
++	r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_WAIT_IDLE,
++				&args, sizeof(args));
++
++	if (r == 0) {
++		*busy = args.out.status;
++		return 0;
++	} else {
++		fprintf(stderr, "amdgpu: GEM_WAIT_IDLE failed with %i\n", r);
++		return r;
++	}
++}
++
++int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
++				    void *cpu,
++				    uint64_t size,
++				    struct amdgpu_bo_alloc_result *info)
++{
++	int r;
++	struct amdgpu_bo *bo;
++	struct drm_amdgpu_gem_userptr args;
++	union drm_amdgpu_gem_va va;
++
++	memset(&args, 0, sizeof(args));
++	args.addr = (uint64_t)cpu;
++	args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER;
++	args.size = size;
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR,
++				&args, sizeof(args));
++	if (r)
++		return r;
++
++	bo = calloc(1, sizeof(struct amdgpu_bo));
++	if (!bo)
++		return -ENOMEM;
++
++	atomic_set(&bo->refcount, 1);
++	bo->dev = dev;
++	bo->alloc_size = size;
++	bo->handle = args.handle;
++	bo->virtual_mc_base_address = amdgpu_vamgr_find_va(&dev->vamgr, size, 4 * 1024);
++
++	memset(&va, 0, sizeof(va));
++	va.in.handle = bo->handle;
++	va.in.operation = AMDGPU_VA_OP_MAP;
++	va.in.flags =	AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
++			AMDGPU_VM_PAGE_EXECUTABLE;
++	va.in.va_address = bo->virtual_mc_base_address;
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
++	if (r || va.out.result == AMDGPU_VA_RESULT_ERROR) {
++		amdgpu_bo_free_internal(bo);
++		return r;
++	}
++	util_hash_table_set(dev->bo_vas,
++			    (void*)(uintptr_t)bo->virtual_mc_base_address, bo);
++	info->buf_handle = bo;
++	info->virtual_mc_base_address = bo->virtual_mc_base_address;
++	return r;
++}
+diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
+new file mode 100644
+index 0000000..614904d
+--- /dev/null
++++ b/amdgpu/amdgpu_cs.c
+@@ -0,0 +1,981 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++#include <stdlib.h>
++#include <stdio.h>
++#include <string.h>
++#include <errno.h>
++#include <pthread.h>
++#include <sched.h>
++#include <sys/ioctl.h>
++
++#include "xf86drm.h"
++#include "amdgpu_drm.h"
++#include "amdgpu_internal.h"
++
++/**
++ * Create an IB buffer.
++ *
++ * \param   dev - \c [in] Device handle
++ * \param   context - \c [in] GPU Context
++ * \param   ib_size - \c [in] Size of allocation
++ * \param   ib - \c [out] return the pointer to the created IB buffer
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_create_ib(amdgpu_device_handle dev,
++			       amdgpu_context_handle context,
++			       enum amdgpu_cs_ib_size ib_size,
++			       amdgpu_ib_handle *ib)
++{
++	struct amdgpu_bo_alloc_request alloc_buffer;
++	struct amdgpu_bo_alloc_result info;
++	int r;
++	void *cpu;
++	struct amdgpu_ib *new_ib;
++
++	memset(&alloc_buffer, 0, sizeof(alloc_buffer));
++
++	switch (ib_size) {
++	case amdgpu_cs_ib_size_4K:
++		alloc_buffer.alloc_size = 4 * 1024;
++		break;
++	case amdgpu_cs_ib_size_16K:
++		alloc_buffer.alloc_size = 16 * 1024;
++		break;
++	case amdgpu_cs_ib_size_32K:
++		alloc_buffer.alloc_size = 32 * 1024;
++		break;
++	case amdgpu_cs_ib_size_64K:
++		alloc_buffer.alloc_size = 64 * 1024;
++		break;
++	case amdgpu_cs_ib_size_128K:
++		alloc_buffer.alloc_size = 128 * 1024;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	alloc_buffer.phys_alignment = 4 * 1024;
++
++	alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
++
++	r = amdgpu_bo_alloc(dev,
++			    &alloc_buffer,
++			    &info);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_cpu_map(info.buf_handle, &cpu);
++	if (r) {
++		amdgpu_bo_free(info.buf_handle);
++		return r;
++	}
++
++	new_ib = malloc(sizeof(struct amdgpu_ib));
++	if (NULL == new_ib) {
++		amdgpu_bo_cpu_unmap(info.buf_handle);
++		amdgpu_bo_free(info.buf_handle);
++		return -ENOMEM;
++	}
++
++	new_ib->buf_handle = info.buf_handle;
++	new_ib->cpu = cpu;
++	new_ib->virtual_mc_base_address = info.virtual_mc_base_address;
++	new_ib->ib_size = ib_size;
++	*ib = new_ib;
++	return 0;
++}
++
++/**
++ * Destroy an IB buffer.
++ *
++ * \param   dev - \c [in]  Device handle
++ * \param   ib - \c [in] the IB buffer
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_destroy_ib(amdgpu_device_handle dev,
++				amdgpu_ib_handle ib)
++{
++	int r;
++	r = amdgpu_bo_cpu_unmap(ib->buf_handle);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_free(ib->buf_handle);
++	if (r)
++		return r;
++
++	free(ib);
++	return 0;
++}
++
++/**
++ * Initialize IB pools to empty.
++ *
++ * \param   context - \c [in]  GPU Context
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_init_ib_pool(amdgpu_context_handle context)
++{
++	int i;
++	int r;
++
++	r = pthread_mutex_init(&context->pool_mutex, NULL);
++	if (r)
++		return r;
++
++	for (i = 0; i < AMDGPU_CS_IB_SIZE_NUM; i++)
++		LIST_INITHEAD(&context->ib_pools[i]);
++
++	return 0;
++}
++
++/**
++ * Allocate an IB buffer from IB pools.
++ *
++ * \param   dev - \c [in]  Device handle
++ * \param   context - \c [in] GPU Context
++ * \param   ib_size - \c [in]  Size of allocation
++ * \param   ib - \c [out] return the pointer to the allocated IB buffer
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_alloc_from_ib_pool(amdgpu_device_handle dev,
++					amdgpu_context_handle context,
++					enum amdgpu_cs_ib_size ib_size,
++					amdgpu_ib_handle *ib)
++{
++	int r;
++	struct list_head *head;
++	head = &context->ib_pools[ib_size];
++
++	r = -ENOMEM;
++	pthread_mutex_lock(&context->pool_mutex);
++	if (!LIST_IS_EMPTY(head)) {
++		*ib = LIST_ENTRY(struct amdgpu_ib, head->next, list_node);
++		LIST_DEL(&(*ib)->list_node);
++		r = 0;
++	}
++	pthread_mutex_unlock(&context->pool_mutex);
++
++	return r;
++}
++
++/**
++ * Free an IB buffer to IB pools.
++ *
++ * \param   context - \c [in]  GPU Context
++ * \param   ib - \c [in] the IB buffer
++ *
++ * \return  N/A
++*/
++static void amdgpu_cs_free_to_ib_pool(amdgpu_context_handle context,
++				      amdgpu_ib_handle ib)
++{
++	struct list_head *head;
++	head = &context->ib_pools[ib->ib_size];
++	pthread_mutex_lock(&context->pool_mutex);
++	LIST_ADD(&ib->list_node, head);
++	pthread_mutex_unlock(&context->pool_mutex);
++	return;
++}
++
++/**
++ * Destroy all IB buffers in pools
++ *
++ * \param   dev - \c [in]  Device handle
++ * \param   context - \c [in]  GPU Context
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_destroy_ib_pool(amdgpu_device_handle dev,
++				     amdgpu_context_handle context)
++{
++	int i;
++	int r;
++	struct list_head *head;
++	struct amdgpu_ib *next;
++	struct amdgpu_ib *storage;
++
++	r = 0;
++	pthread_mutex_lock(&context->pool_mutex);
++	for (i = 0; i < AMDGPU_CS_IB_SIZE_NUM; i++) {
++		head = &context->ib_pools[i];
++		LIST_FOR_EACH_ENTRY_SAFE(next, storage, head, list_node) {
++			r = amdgpu_cs_destroy_ib(dev, next);
++			if (r)
++				break;
++		}
++	}
++	pthread_mutex_unlock(&context->pool_mutex);
++	pthread_mutex_destroy(&context->pool_mutex);
++	return r;
++}
++
++/**
++ * Initialize pending IB lists
++ *
++ * \param   context - \c [in]  GPU Context
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_init_pendings(amdgpu_context_handle context)
++{
++	unsigned ip, inst;
++	uint32_t ring;
++	int r;
++
++	r = pthread_mutex_init(&context->pendings_mutex, NULL);
++	if (r)
++		return r;
++
++	for (ip = 0; ip < AMDGPU_HW_IP_NUM; ip++)
++		for (inst = 0; inst < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; inst++)
++			for (ring = 0; ring < AMDGPU_CS_MAX_RINGS; ring++)
++				LIST_INITHEAD(&context->pendings[ip][inst][ring]);
++
++	LIST_INITHEAD(&context->freed);
++	return 0;
++}
++
++/**
++ * Free pending IBs
++ *
++ * \param   dev - \c [in]  Device handle
++ * \param   context - \c [in]  GPU Context
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_destroy_pendings(amdgpu_device_handle dev,
++				      amdgpu_context_handle context)
++{
++	int ip, inst;
++	uint32_t ring;
++	int r;
++	struct amdgpu_ib *next;
++	struct amdgpu_ib *s;
++	struct list_head *head;
++
++	r = 0;
++	pthread_mutex_lock(&context->pendings_mutex);
++	for (ip = 0; ip < AMDGPU_HW_IP_NUM; ip++)
++		for (inst = 0; inst < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; inst++)
++			for (ring = 0; ring < AMDGPU_CS_MAX_RINGS; ring++) {
++				head = &context->pendings[ip][inst][ring];
++				LIST_FOR_EACH_ENTRY_SAFE(next, s, head, list_node) {
++					r = amdgpu_cs_destroy_ib(dev, next);
++					if (r)
++						break;
++				}
++			}
++
++	head = &context->freed;
++	LIST_FOR_EACH_ENTRY_SAFE(next, s, head, list_node) {
++		r = amdgpu_cs_destroy_ib(dev, next);
++		if (r)
++			break;
++	}
++
++	pthread_mutex_unlock(&context->pendings_mutex);
++	pthread_mutex_destroy(&context->pendings_mutex);
++	return r;
++}
++
++/**
++ * Add IB to pending IB lists without holding sequence_mutex.
++ *
++ * \param   context - \c [in]  GPU Context
++ * \param   ib - \c [in]  ib to added to pending lists
++ * \param   ip - \c [in]  hw ip block
++ * \param   ip_instance - \c [in]  instance of the hw ip block
++ * \param   ring - \c [in]  Ring of hw ip
++ *
++ * \return  N/A
++*/
++static void amdgpu_cs_add_pending(amdgpu_context_handle context,
++				  amdgpu_ib_handle ib,
++				  unsigned ip, unsigned ip_instance,
++				  uint32_t ring)
++{
++	struct list_head *head;
++	pthread_mutex_lock(&context->pendings_mutex);
++	head = &context->pendings[ip][ip_instance][ring];
++	LIST_ADDTAIL(&ib->list_node, head);
++	pthread_mutex_unlock(&context->pendings_mutex);
++	return;
++}
++
++/**
++ * Garbage collector on a pending IB list without holding pendings_mutex.
++ * This function by itself is not multithread safe.
++ *
++ * \param   context - \c [in]  GPU Context
++ * \param   ip - \c [in]  hw ip block
++ * \param   ip_instance - \c [in]  instance of the hw ip block
++ * \param   ring - \c [in]  Ring of hw ip
++ * \param   expired_fence - \c [in]  fence expired
++ *
++ * \return  N/A
++ * \note Hold pendings_mutex before calling this function.
++*/
++static void amdgpu_cs_pending_gc_not_safe(amdgpu_context_handle context,
++					  unsigned ip, unsigned ip_instance,
++					  uint32_t ring,
++					  uint64_t expired_fence)
++{
++	struct list_head *head;
++	struct amdgpu_ib *next;
++	struct amdgpu_ib *s;
++	int r;
++
++	head = &context->pendings[ip][ip_instance][ring];
++	LIST_FOR_EACH_ENTRY_SAFE(next, s, head, list_node)
++		if (next->cs_handle <= expired_fence) {
++			LIST_DEL(&next->list_node);
++			amdgpu_cs_free_to_ib_pool(context, next);
++		} else {
++			/* The pending list is a sorted list.
++			   There is no need to continue. */
++			break;
++		}
++
++	/* walk the freed list as well */
++	head = &context->freed;
++	LIST_FOR_EACH_ENTRY_SAFE(next, s, head, list_node) {
++		bool busy;
++
++		r = amdgpu_bo_wait_for_idle(next->buf_handle, 0, &busy);
++		if (r || busy)
++			break;
++
++		LIST_DEL(&next->list_node);
++		amdgpu_cs_free_to_ib_pool(context, next);
++	}
++
++	return;
++}
++
++/**
++ * Garbage collector on a pending IB list
++ *
++ * \param   context - \c [in]  GPU Context
++ * \param   ip - \c [in]  hw ip block
++ * \param   ip_instance - \c [in]  instance of the hw ip block
++ * \param   ring - \c [in]  Ring of hw ip
++ * \param   expired_fence - \c [in]  fence expired
++ *
++ * \return  N/A
++*/
++static void amdgpu_cs_pending_gc(amdgpu_context_handle context,
++				 unsigned ip, unsigned ip_instance,
++				 uint32_t ring,
++				 uint64_t expired_fence)
++{
++	pthread_mutex_lock(&context->pendings_mutex);
++	amdgpu_cs_pending_gc_not_safe(context, ip, ip_instance, ring,
++				      expired_fence);
++	pthread_mutex_unlock(&context->pendings_mutex);
++	return;
++}
++
++/**
++ * Garbage collector on all pending IB lists
++ *
++ * \param   context - \c [in]  GPU Context
++ *
++ * \return  N/A
++*/
++static void amdgpu_cs_all_pending_gc(amdgpu_context_handle context)
++{
++	unsigned ip, inst;
++	uint32_t ring;
++	uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
++
++	pthread_mutex_lock(&context->sequence_mutex);
++	for (ip = 0; ip < AMDGPU_HW_IP_NUM; ip++)
++		for (inst = 0; inst < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; inst++)
++			for (ring = 0; ring < AMDGPU_CS_MAX_RINGS; ring++)
++				expired_fences[ip][inst][ring] =
++					context->expired_fences[ip][inst][ring];
++	pthread_mutex_unlock(&context->sequence_mutex);
++
++	pthread_mutex_lock(&context->pendings_mutex);
++	for (ip = 0; ip < AMDGPU_HW_IP_NUM; ip++)
++		for (inst = 0; inst < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; inst++)
++			for (ring = 0; ring < AMDGPU_CS_MAX_RINGS; ring++)
++				amdgpu_cs_pending_gc_not_safe(context, ip, inst, ring,
++					expired_fences[ip][inst][ring]);
++	pthread_mutex_unlock(&context->pendings_mutex);
++}
++
++/**
++ * Allocate an IB buffer
++ * If there is no free IB buffer in pools, create one.
++ *
++ * \param   dev - \c [in] Device handle
++ * \param   context - \c [in] GPU Context
++ * \param   ib_size - \c [in] Size of allocation
++ * \param   ib - \c [out] return the pointer to the allocated IB buffer
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++static int amdgpu_cs_alloc_ib_local(amdgpu_device_handle dev,
++				    amdgpu_context_handle context,
++				    enum amdgpu_cs_ib_size ib_size,
++				    amdgpu_ib_handle *ib)
++{
++	int r;
++
++	r = amdgpu_cs_alloc_from_ib_pool(dev, context, ib_size, ib);
++	if (!r)
++		return r;
++
++	amdgpu_cs_all_pending_gc(context);
++
++	/* Retry to allocate from free IB pools after garbage collector. */
++	r = amdgpu_cs_alloc_from_ib_pool(dev, context, ib_size, ib);
++	if (!r)
++		return r;
++
++	/* There is no suitable IB in free pools. Create one. */
++	r = amdgpu_cs_create_ib(dev, context, ib_size, ib);
++	return r;
++}
++
++int amdgpu_cs_alloc_ib(amdgpu_device_handle dev,
++		       amdgpu_context_handle context,
++		       enum amdgpu_cs_ib_size ib_size,
++		       struct amdgpu_cs_ib_alloc_result *output)
++{
++	int r;
++	amdgpu_ib_handle ib;
++
++	if (NULL == dev)
++		return -EINVAL;
++	if (NULL == context)
++		return -EINVAL;
++	if (NULL == output)
++		return -EINVAL;
++	if (ib_size >= AMDGPU_CS_IB_SIZE_NUM)
++		return -EINVAL;
++
++	r = amdgpu_cs_alloc_ib_local(dev, context, ib_size, &ib);
++	if (!r) {
++		output->handle = ib;
++		output->cpu = ib->cpu;
++		output->mc_address = ib->virtual_mc_base_address;
++	}
++
++	return r;
++}
++
++int amdgpu_cs_free_ib(amdgpu_device_handle dev,
++		      amdgpu_context_handle context,
++		      amdgpu_ib_handle handle)
++{
++	if (NULL == dev)
++		return -EINVAL;
++	if (NULL == context)
++		return -EINVAL;
++	if (NULL == handle)
++		return -EINVAL;
++
++	pthread_mutex_lock(&context->pendings_mutex);
++	LIST_ADD(&handle->list_node, &context->freed);
++	pthread_mutex_unlock(&context->pendings_mutex);
++	return 0;
++}
++
++/**
++ * Create command submission context
++ *
++ * \param   dev - \c [in] amdgpu device handle
++ * \param   context - \c [out] amdgpu context handle
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
++			 amdgpu_context_handle *context)
++{
++	struct amdgpu_context *gpu_context;
++	union drm_amdgpu_ctx args;
++	int r;
++
++	if (NULL == dev)
++		return -EINVAL;
++	if (NULL == context)
++		return -EINVAL;
++
++	gpu_context = calloc(1, sizeof(struct amdgpu_context));
++	if (NULL == gpu_context)
++		return -ENOMEM;
++
++	r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
++	if (r)
++		goto error_mutex;
++
++	r = amdgpu_cs_init_ib_pool(gpu_context);
++	if (r)
++		goto error_pool;
++
++	r = amdgpu_cs_init_pendings(gpu_context);
++	if (r)
++		goto error_pendings;
++
++	r = amdgpu_cs_alloc_ib_local(dev, gpu_context, amdgpu_cs_ib_size_4K,
++				     &gpu_context->fence_ib);
++	if (r)
++		goto error_fence_ib;
++
++
++	memset(&args, 0, sizeof(args));
++	args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
++	if (r)
++		goto error_kernel;
++
++	gpu_context->id = args.out.alloc.ctx_id;
++	*context = (amdgpu_context_handle)gpu_context;
++
++	return 0;
++
++error_kernel:
++	amdgpu_cs_free_ib(dev, gpu_context, gpu_context->fence_ib);
++
++error_fence_ib:
++	amdgpu_cs_destroy_pendings(dev, gpu_context);
++
++error_pendings:
++	amdgpu_cs_destroy_ib_pool(dev, gpu_context);
++
++error_pool:
++	pthread_mutex_destroy(&gpu_context->sequence_mutex);
++
++error_mutex:
++	free(gpu_context);
++	return r;
++}
++
++/**
++ * Release command submission context
++ *
++ * \param   dev - \c [in] amdgpu device handle
++ * \param   context - \c [in] amdgpu context handle
++ *
++ * \return  0 on success otherwise POSIX Error code
++*/
++int amdgpu_cs_ctx_free(amdgpu_device_handle dev,
++		       amdgpu_context_handle context)
++{
++	int r;
++	union drm_amdgpu_ctx args;
++
++	if (NULL == dev)
++		return -EINVAL;
++	if (NULL == context)
++		return -EINVAL;
++
++	r = amdgpu_cs_free_ib(dev, context, context->fence_ib);
++	if (r)
++		return r;
++
++	r = amdgpu_cs_destroy_pendings(dev, context);
++	if (r)
++		return r;
++
++	r = amdgpu_cs_destroy_ib_pool(dev, context);
++	if (r)
++		return r;
++
++	pthread_mutex_destroy(&context->sequence_mutex);
++
++	/* now deal with kernel side */
++	memset(&args, 0, sizeof(args));
++	args.in.op = AMDGPU_CTX_OP_FREE_CTX;
++	args.in.ctx_id = context->id;
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
++
++	free(context);
++
++	return r;
++}
++
++static int amdgpu_cs_create_bo_list(amdgpu_device_handle dev,
++				    amdgpu_context_handle context,
++				    struct amdgpu_cs_request *request,
++				    amdgpu_ib_handle fence_ib,
++				    uint32_t *handle)
++{
++	struct drm_amdgpu_bo_list_entry *list;
++	union drm_amdgpu_bo_list args;
++	unsigned num_resources;
++	unsigned i;
++	int r;
++
++	num_resources = request->number_of_resources;
++	if (fence_ib)
++		++num_resources;
++
++	list = alloca(sizeof(struct drm_amdgpu_bo_list_entry) * num_resources);
++
++	memset(&args, 0, sizeof(args));
++	args.in.operation = AMDGPU_BO_LIST_OP_CREATE;
++	args.in.bo_number = num_resources;
++	args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
++	args.in.bo_info_ptr = (uint64_t)(uintptr_t)list;
++
++	for (i = 0; i < request->number_of_resources; i++) {
++		list[i].bo_handle = request->resources[i]->handle;
++		if (request->resource_flags)
++			list[i].bo_priority = request->resource_flags[i];
++		else
++			list[i].bo_priority = 0;
++	}
++
++	if (fence_ib)
++		list[i].bo_handle = fence_ib->buf_handle->handle;
++
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
++				&args, sizeof(args));
++	if (r)
++		return r;
++
++	*handle = args.out.list_handle;
++	return 0;
++}
++
++static int amdgpu_cs_free_bo_list(amdgpu_device_handle dev, uint32_t handle)
++{
++	union drm_amdgpu_bo_list args;
++	int r;
++
++	memset(&args, 0, sizeof(args));
++	args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
++	args.in.list_handle = handle;
++
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
++				&args, sizeof(args));
++
++	return r;
++}
++
++static uint32_t amdgpu_cs_fence_index(unsigned ip, unsigned ring)
++{
++	return ip * AMDGPU_CS_MAX_RINGS + ring;
++}
++
++/**
++ * Submit command to kernel DRM
++ * \param   dev - \c [in]  Device handle
++ * \param   context - \c [in]  GPU Context
++ * \param   ibs_request - \c [in]  Pointer to submission requests
++ * \param   fence - \c [out] return fence for this submission
++ *
++ * \return  0 on success otherwise POSIX Error code
++ * \sa amdgpu_cs_submit()
++*/
++static int amdgpu_cs_submit_one(amdgpu_device_handle dev,
++				amdgpu_context_handle context,
++				struct amdgpu_cs_request *ibs_request,
++				uint64_t *fence)
++{
++	int r;
++	uint32_t i, size;
++	union drm_amdgpu_cs cs;
++	uint64_t *chunk_array;
++	struct drm_amdgpu_cs_chunk *chunks;
++	struct drm_amdgpu_cs_chunk_data *chunk_data;
++
++	if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
++		return -EINVAL;
++	if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS)
++		return -EINVAL;
++	if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT)
++		return -EINVAL;
++
++	size = (ibs_request->number_of_ibs + 1) * ((sizeof(uint64_t) +
++		sizeof(struct drm_amdgpu_cs_chunk) +
++		sizeof(struct drm_amdgpu_cs_chunk_data)) +
++	       ibs_request->number_of_resources + 1) *
++	       sizeof(struct drm_amdgpu_bo_list_entry);
++	chunk_array = malloc(size);
++	if (NULL == chunk_array)
++		return -ENOMEM;
++	memset(chunk_array, 0, size);
++
++	chunks = (struct drm_amdgpu_cs_chunk *)(chunk_array + ibs_request->number_of_ibs + 1);
++	chunk_data = (struct drm_amdgpu_cs_chunk_data *)(chunks + ibs_request->number_of_ibs + 1);
++
++	memset(&cs, 0, sizeof(cs));
++	cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
++	cs.in.ctx_id = context->id;
++	cs.in.num_chunks = ibs_request->number_of_ibs;
++	/* IB chunks */
++	for (i = 0; i < ibs_request->number_of_ibs; i++) {
++		struct amdgpu_cs_ib_info *ib;
++		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
++		chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
++		chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
++		chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
++
++		ib = &ibs_request->ibs[i];
++
++		chunk_data[i].ib_data.handle = ib->ib_handle->buf_handle->handle;
++		chunk_data[i].ib_data.va_start = ib->ib_handle->virtual_mc_base_address;
++		chunk_data[i].ib_data.ib_bytes = ib->size * 4;
++		chunk_data[i].ib_data.ip_type = ibs_request->ip_type;
++		chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance;
++		chunk_data[i].ib_data.ring = ibs_request->ring;
++
++		if (ib->flags & AMDGPU_CS_GFX_IB_CE)
++			chunk_data[i].ib_data.flags = AMDGPU_IB_FLAG_CE;
++	}
++
++	r = amdgpu_cs_create_bo_list(dev, context, ibs_request, NULL,
++				     &cs.in.bo_list_handle);
++	if (r)
++		goto error_unlock;
++
++	pthread_mutex_lock(&context->sequence_mutex);
++
++	if (ibs_request->ip_type != AMDGPU_HW_IP_UVD &&
++	    ibs_request->ip_type != AMDGPU_HW_IP_VCE) {
++		i = cs.in.num_chunks++;
++
++		/* fence chunk */
++		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
++		chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
++		chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
++		chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
++
++		/* fence bo handle */
++		chunk_data[i].fence_data.handle = context->fence_ib->buf_handle->handle;
++		/* offset */
++		chunk_data[i].fence_data.offset = amdgpu_cs_fence_index(
++			ibs_request->ip_type, ibs_request->ring);
++		chunk_data[i].fence_data.offset *= sizeof(uint64_t);
++	}
++
++	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
++				&cs, sizeof(cs));
++	if (r)
++		goto error_unlock;
++
++
++	/* Hold sequence_mutex while adding record to the pending list.
++	   So the pending list is a sorted list according to fence value. */
++
++	for (i = 0; i < ibs_request->number_of_ibs; i++) {
++		struct amdgpu_cs_ib_info *ib;
++
++		ib = &ibs_request->ibs[i];
++		if (ib->flags & AMDGPU_CS_REUSE_IB)
++			continue;
++
++		ib->ib_handle->cs_handle = cs.out.handle;
++
++		amdgpu_cs_add_pending(context, ib->ib_handle, ibs_request->ip_type,
++				      ibs_request->ip_instance,
++				      ibs_request->ring);
++	}
++
++	*fence = cs.out.handle;
++
++	pthread_mutex_unlock(&context->sequence_mutex);
++
++	r = amdgpu_cs_free_bo_list(dev, cs.in.bo_list_handle);
++	if (r)
++		goto error_free;
++
++	free(chunk_array);
++	return 0;
++
++error_unlock:
++	pthread_mutex_unlock(&context->sequence_mutex);
++
++error_free:
++	free(chunk_array);
++	return r;
++}
++
++int amdgpu_cs_submit(amdgpu_device_handle  dev,
++		     amdgpu_context_handle context,
++		     uint64_t flags,
++		     struct amdgpu_cs_request *ibs_request,
++		     uint32_t number_of_requests,
++		     uint64_t *fences)
++{
++	int r;
++	uint32_t i;
++
++	if (NULL == dev)
++		return -EINVAL;
++	if (NULL == context)
++		return -EINVAL;
++	if (NULL == ibs_request)
++		return -EINVAL;
++	if (NULL == fences)
++		return -EINVAL;
++
++	r = 0;
++	for (i = 0; i < number_of_requests; i++) {
++		r = amdgpu_cs_submit_one(dev, context, ibs_request, fences);
++		if (r)
++			break;
++		fences++;
++		ibs_request++;
++	}
++
++	return r;
++}
++
++/**
++ * Calculate absolute timeout.
++ *
++ * \param   timeout - \c [in] timeout in nanoseconds.
++ *
++ * \return  absolute timeout in nanoseconds
++*/
++uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
++{
++	int r;
++
++	if (timeout != AMDGPU_TIMEOUT_INFINITE) {
++		struct timespec current;
++		r = clock_gettime(CLOCK_MONOTONIC, &current);
++		if (r)
++			return r;
++
++		timeout += ((uint64_t)current.tv_sec) * 1000000000ull;
++		timeout += current.tv_nsec;
++	}
++	return timeout;
++}
++
++static int amdgpu_ioctl_wait_cs(amdgpu_device_handle dev,
++				unsigned ip,
++				unsigned ip_instance,
++				uint32_t ring,
++				uint64_t handle,
++				uint64_t timeout_ns,
++				bool *busy)
++{
++	union drm_amdgpu_wait_cs args;
++	int r;
++
++	memset(&args, 0, sizeof(args));
++	args.in.handle = handle;
++	args.in.ip_type = ip;
++	args.in.ip_instance = ip_instance;
++	args.in.ring = ring;
++	args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
++
++	/* Handle errors manually here because of timeout */
++	r = ioctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
++	if (r == -1 && (errno == EINTR || errno == EAGAIN)) {
++		*busy = true;
++		return 0;
++	} else if (r)
++		return -errno;
++
++	*busy = args.out.status;
++	return 0;
++}
++
++int amdgpu_cs_query_fence_status(amdgpu_device_handle dev,
++				 struct amdgpu_cs_query_fence *fence,
++				 uint32_t *expired)
++{
++	amdgpu_context_handle context;
++	uint64_t *signaled_fence;
++	uint64_t *expired_fence;
++	unsigned ip_type, ip_instance;
++	uint32_t ring;
++	bool busy = true;
++	int r;
++
++	if (NULL == dev)
++		return -EINVAL;
++	if (NULL == fence)
++		return -EINVAL;
++	if (NULL == expired)
++		return -EINVAL;
++	if (NULL == fence->context)
++		return -EINVAL;
++	if (fence->ip_type >= AMDGPU_HW_IP_NUM)
++		return -EINVAL;
++	if (fence->ring >= AMDGPU_CS_MAX_RINGS)
++		return -EINVAL;
++
++	context = fence->context;
++	ip_type = fence->ip_type;
++	ip_instance = fence->ip_instance;
++	ring = fence->ring;
++	signaled_fence = context->fence_ib->cpu;
++	signaled_fence += amdgpu_cs_fence_index(ip_type, ring);
++	expired_fence = &context->expired_fences[ip_type][ip_instance][ring];
++	*expired = false;
++
++	pthread_mutex_lock(&context->sequence_mutex);
++	if (fence->fence <= *expired_fence) {
++		/* This fence value is expired already. */
++		pthread_mutex_unlock(&context->sequence_mutex);
++		*expired = true;
++		return 0;
++	}
++
++	if (fence->fence <= *signaled_fence) {
++		/* This fence value is signaled already. */
++		*expired_fence = *signaled_fence;
++		pthread_mutex_unlock(&context->sequence_mutex);
++		amdgpu_cs_pending_gc(context, ip_type, ip_instance, ring,
++				     fence->fence);
++		*expired = true;
++		return 0;
++	}
++
++	pthread_mutex_unlock(&context->sequence_mutex);
++
++	r = amdgpu_ioctl_wait_cs(dev, ip_type, ip_instance, ring,
++				 fence->fence, fence->timeout_ns, &busy);
++	if (!r && !busy) {
++		*expired = true;
++		pthread_mutex_lock(&context->sequence_mutex);
++		/* The thread doesn't hold sequence_mutex. Other thread could
++		   update *expired_fence already. Check whether there is a
++		   newerly expired fence. */
++		if (fence->fence > *expired_fence) {
++			*expired_fence = fence->fence;
++			pthread_mutex_unlock(&context->sequence_mutex);
++			amdgpu_cs_pending_gc(context, ip_type, ip_instance,
++					     ring, fence->fence);
++		} else {
++			pthread_mutex_unlock(&context->sequence_mutex);
++		}
++	}
++
++	return r;
++}
++
+diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
+new file mode 100644
+index 0000000..66fa187
+--- /dev/null
++++ b/amdgpu/amdgpu_device.c
+@@ -0,0 +1,242 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++
++/**
++ * \file amdgpu_device.c
++ *
++ *  Implementation of functions for AMD GPU device
++ *
++ *
++ */
++
++#include <sys/stat.h>
++#include <errno.h>
++#include <string.h>
++#include <stdio.h>
++#include <stdlib.h>
++
++#include "xf86drm.h"
++#include "amdgpu_drm.h"
++#include "amdgpu_internal.h"
++#include "util_hash_table.h"
++
++#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
++#define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
++#define RENDERNODE_MINOR_MASK 0xff7f
++
++pthread_mutex_t fd_mutex = PTHREAD_MUTEX_INITIALIZER;
++static struct util_hash_table *fd_tab;
++
++static unsigned handle_hash(void *key)
++{
++	return PTR_TO_UINT(key);
++}
++
++static int handle_compare(void *key1, void *key2)
++{
++	return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
++}
++
++static unsigned fd_hash(void *key)
++{
++	int fd = PTR_TO_UINT(key);
++	struct stat stat;
++	fstat(fd, &stat);
++
++	if (!S_ISCHR(stat.st_mode))
++		return stat.st_dev ^ stat.st_ino;
++	else
++		return stat.st_dev ^ (stat.st_rdev & RENDERNODE_MINOR_MASK);
++}
++
++static int fd_compare(void *key1, void *key2)
++{
++	int fd1 = PTR_TO_UINT(key1);
++	int fd2 = PTR_TO_UINT(key2);
++	struct stat stat1, stat2;
++	fstat(fd1, &stat1);
++	fstat(fd2, &stat2);
++
++	if (!S_ISCHR(stat1.st_mode) || !S_ISCHR(stat2.st_mode))
++		return stat1.st_dev != stat2.st_dev ||
++			stat1.st_ino != stat2.st_ino;
++        else
++		return major(stat1.st_rdev) != major(stat2.st_rdev) ||
++			(minor(stat1.st_rdev) & RENDERNODE_MINOR_MASK) !=
++			(minor(stat2.st_rdev) & RENDERNODE_MINOR_MASK);
++}
++
++/**
++* Get the authenticated form fd,
++*
++* \param   fd   - \c [in]  File descriptor for AMD GPU device
++* \param   auth - \c [out] Pointer to output the fd is authenticated or not
++*                          A render node fd, output auth = 0
++*                          A legacy fd, get the authenticated for compatibility root
++*
++* \return   0 on success\n
++*          >0 - AMD specific error code\n
++*          <0 - Negative POSIX Error code
++*/
++static int amdgpu_get_auth(int fd, int *auth)
++{
++	int r = 0;
++	drm_client_t client;
++	struct stat stat1;
++	fstat(fd,&stat1);
++	if (minor(stat1.st_rdev) & ~RENDERNODE_MINOR_MASK)/* find a render node fd */
++		*auth = 0;
++	else {
++		client.idx=0;
++		r= drmIoctl(fd, DRM_IOCTL_GET_CLIENT, &client);
++		if (!r)
++			*auth = client.auth;
++	}
++	return r;
++}
++
++int amdgpu_device_initialize(int fd,
++			     uint32_t *major_version,
++			     uint32_t *minor_version,
++			     amdgpu_device_handle *device_handle)
++{
++	struct amdgpu_device *dev;
++	drmVersionPtr version;
++	int r;
++	int flag_auth = 0;
++	int flag_authexist=0;
++	uint32_t accel_working;
++
++	*device_handle = NULL;
++
++	pthread_mutex_lock(&fd_mutex);
++	if (!fd_tab)
++		fd_tab = util_hash_table_create(fd_hash, fd_compare);
++	r = amdgpu_get_auth(fd, &flag_auth);
++	if (r) {
++		pthread_mutex_unlock(&fd_mutex);
++		return r;
++	}
++	dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
++	if (dev) {
++		r = amdgpu_get_auth(dev->fd, &flag_authexist);
++		if (r) {
++			pthread_mutex_unlock(&fd_mutex);
++			return r;
++		}
++		if ((flag_auth) && (!flag_authexist)) {
++			dev->flink_fd = fd;
++		}
++		*major_version = dev->major_version;
++		*minor_version = dev->minor_version;
++		amdgpu_device_reference(device_handle, dev);
++		pthread_mutex_unlock(&fd_mutex);
++		return 0;
++	}
++
++	dev = calloc(1, sizeof(struct amdgpu_device));
++	if (!dev) {
++		pthread_mutex_unlock(&fd_mutex);
++		return -ENOMEM;
++	}
++
++	atomic_set(&dev->refcount, 1);
++
++	version = drmGetVersion(fd);
++	if (version->version_major != 3) {
++		fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
++			"only compatible with 3.x.x.\n",
++			__func__,
++			version->version_major,
++			version->version_minor,
++			version->version_patchlevel);
++		drmFreeVersion(version);
++		r = -EBADF;
++		goto cleanup;
++	}
++
++	dev->fd = fd;
++	dev->flink_fd = fd;
++	dev->major_version = version->version_major;
++	dev->minor_version = version->version_minor;
++	drmFreeVersion(version);
++
++	dev->bo_flink_names = util_hash_table_create(handle_hash,
++						     handle_compare);
++	dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
++	dev->bo_vas = util_hash_table_create(handle_hash, handle_compare);
++	pthread_mutex_init(&dev->bo_table_mutex, NULL);
++
++	/* Check if acceleration is working. */
++	r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4, &accel_working);
++	if (r)
++		goto cleanup;
++	if (!accel_working) {
++		r = -EBADF;
++		goto cleanup;
++	}
++
++	r = amdgpu_query_gpu_info_init(dev);
++	if (r)
++		goto cleanup;
++
++	amdgpu_vamgr_init(dev);
++
++	*major_version = dev->major_version;
++	*minor_version = dev->minor_version;
++	*device_handle = dev;
++	util_hash_table_set(fd_tab, UINT_TO_PTR(fd), dev);
++	pthread_mutex_unlock(&fd_mutex);
++
++	return 0;
++
++cleanup:
++	free(dev);
++	pthread_mutex_unlock(&fd_mutex);
++	return r;
++}
++
++void amdgpu_device_free_internal(amdgpu_device_handle dev)
++{
++	util_hash_table_destroy(dev->bo_flink_names);
++	util_hash_table_destroy(dev->bo_handles);
++	util_hash_table_destroy(dev->bo_vas);
++	pthread_mutex_destroy(&dev->bo_table_mutex);
++	pthread_mutex_destroy(&(dev->vamgr.bo_va_mutex));
++	util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd));
++	free(dev);
++}
++
++int amdgpu_device_deinitialize(amdgpu_device_handle dev)
++{
++	amdgpu_device_reference(&dev, NULL);
++	return 0;
++}
++
++void amdgpu_device_reference(struct amdgpu_device **dst,
++			     struct amdgpu_device *src)
++{
++	if (update_references(&(*dst)->refcount, &src->refcount))
++		amdgpu_device_free_internal(*dst);
++	*dst = src;
++}
+diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
+new file mode 100644
+index 0000000..0b77731
+--- /dev/null
++++ b/amdgpu/amdgpu_gpu_info.c
+@@ -0,0 +1,275 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <errno.h>
++#include <string.h>
++
++#include "amdgpu.h"
++#include "amdgpu_drm.h"
++#include "amdgpu_internal.h"
++#include "xf86drm.h"
++
++int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
++		      unsigned size, void *value)
++{
++	struct drm_amdgpu_info request;
++
++	memset(&request, 0, sizeof(request));
++	request.return_pointer = (uintptr_t)value;
++	request.return_size = size;
++	request.query = info_id;
++
++	return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
++			       sizeof(struct drm_amdgpu_info));
++}
++
++int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
++			      int32_t *result)
++{
++	struct drm_amdgpu_info request;
++
++	memset(&request, 0, sizeof(request));
++	request.return_pointer = (uintptr_t)result;
++	request.return_size = sizeof(*result);
++	request.query = AMDGPU_INFO_CRTC_FROM_ID;
++	request.mode_crtc.id = id;
++
++	return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
++			       sizeof(struct drm_amdgpu_info));
++}
++
++int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
++			     unsigned count, uint32_t instance, uint32_t flags,
++			     uint32_t *values)
++{
++	struct drm_amdgpu_info request;
++
++	memset(&request, 0, sizeof(request));
++	request.return_pointer = (uintptr_t)values;
++	request.return_size = count * sizeof(uint32_t);
++	request.query = AMDGPU_INFO_READ_MMR_REG;
++	request.read_mmr_reg.dword_offset = dword_offset;
++	request.read_mmr_reg.count = count;
++	request.read_mmr_reg.instance = instance;
++	request.read_mmr_reg.flags = flags;
++
++	return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
++			       sizeof(struct drm_amdgpu_info));
++}
++
++int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
++			     uint32_t *count)
++{
++	struct drm_amdgpu_info request;
++
++	memset(&request, 0, sizeof(request));
++	request.return_pointer = (uintptr_t)count;
++	request.return_size = sizeof(*count);
++	request.query = AMDGPU_INFO_HW_IP_COUNT;
++	request.query_hw_ip.type = type;
++
++	return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
++			       sizeof(struct drm_amdgpu_info));
++}
++
++int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
++			    unsigned ip_instance,
++			    struct drm_amdgpu_info_hw_ip *info)
++{
++	struct drm_amdgpu_info request;
++
++	memset(&request, 0, sizeof(request));
++	request.return_pointer = (uintptr_t)info;
++	request.return_size = sizeof(*info);
++	request.query = AMDGPU_INFO_HW_IP_INFO;
++	request.query_hw_ip.type = type;
++	request.query_hw_ip.ip_instance = ip_instance;
++
++	return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
++			       sizeof(struct drm_amdgpu_info));
++}
++
++int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
++				  unsigned ip_instance, unsigned index,
++				  uint32_t *version, uint32_t *feature)
++{
++	struct drm_amdgpu_info request;
++	struct drm_amdgpu_info_firmware firmware;
++	int r;
++
++	memset(&request, 0, sizeof(request));
++	request.return_pointer = (uintptr_t)&firmware;
++	request.return_size = sizeof(firmware);
++	request.query = AMDGPU_INFO_FW_VERSION;
++	request.query_fw.fw_type = fw_type;
++	request.query_fw.ip_instance = ip_instance;
++	request.query_fw.index = index;
++
++	r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
++			    sizeof(struct drm_amdgpu_info));
++	if (r)
++		return r;
++
++	*version = firmware.ver;
++	*feature = firmware.feature;
++	return 0;
++}
++
++int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
++{
++	int r, i;
++
++	r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(dev->dev_info),
++			      &dev->dev_info);
++	if (r)
++		return r;
++
++	dev->info.asic_id = dev->dev_info.device_id;
++	dev->info.chip_rev = dev->dev_info.chip_rev;
++	dev->info.chip_external_rev = dev->dev_info.external_rev;
++	dev->info.family_id = dev->dev_info.family;
++	dev->info.max_engine_clk = dev->dev_info.max_engine_clock;
++	dev->info.gpu_counter_freq = dev->dev_info.gpu_counter_freq;
++	dev->info.enabled_rb_pipes_mask = dev->dev_info.enabled_rb_pipes_mask;
++	dev->info.rb_pipes = dev->dev_info.num_rb_pipes;
++	dev->info.ids_flags = dev->dev_info.ids_flags;
++	dev->info.num_hw_gfx_contexts = dev->dev_info.num_hw_gfx_contexts;
++	dev->info.num_shader_engines = dev->dev_info.num_shader_engines;
++	dev->info.num_shader_arrays_per_engine =
++		dev->dev_info.num_shader_arrays_per_engine;
++
++	for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
++		unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
++				    (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
++				     AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
++
++		r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
++					     &dev->info.backend_disable[i]);
++		if (r)
++			return r;
++		/* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
++		dev->info.backend_disable[i] =
++			(dev->info.backend_disable[i] >> 16) & 0xff;
++
++		r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
++					     &dev->info.pa_sc_raster_cfg[i]);
++		if (r)
++			return r;
++
++		r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
++					     &dev->info.pa_sc_raster_cfg1[i]);
++		if (r)
++			return r;
++	}
++
++	r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
++				     dev->info.gb_tile_mode);
++	if (r)
++		return r;
++
++	r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
++				     dev->info.gb_macro_tile_mode);
++	if (r)
++		return r;
++
++	r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
++				     &dev->info.gb_addr_cfg);
++	if (r)
++		return r;
++
++	r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
++				     &dev->info.mc_arb_ramcfg);
++	if (r)
++		return r;
++
++	dev->info.cu_active_number = dev->dev_info.cu_active_number;
++	dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
++	memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
++
++	/* TODO: info->max_quad_shader_pipes is not set */
++	/* TODO: info->avail_quad_shader_pipes is not set */
++	/* TODO: info->cache_entries_per_quad_pipe is not set */
++	/* TODO: info->active_rb_pipes is not set */
++	return 0;
++}
++
++int amdgpu_query_gpu_info(amdgpu_device_handle dev,
++			struct amdgpu_gpu_info *info)
++{
++	/* Get ASIC info*/
++	*info = dev->info;
++
++	return 0;
++}
++
++int amdgpu_query_heap_info(amdgpu_device_handle dev,
++			uint32_t heap,
++			uint32_t flags,
++			struct amdgpu_heap_info *info)
++{
++	struct drm_amdgpu_info_vram_gtt vram_gtt_info;
++	int r;
++
++	r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT,
++			      sizeof(vram_gtt_info), &vram_gtt_info);
++	if (r)
++		return r;
++
++	/* Get heap information */
++	switch (heap) {
++	case AMDGPU_GEM_DOMAIN_VRAM:
++		/* query visible only vram heap */
++		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
++			info->heap_size = vram_gtt_info.vram_cpu_accessible_size;
++		else /* query total vram heap */
++			info->heap_size = vram_gtt_info.vram_size;
++
++		info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
++
++		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
++			r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE,
++					      sizeof(info->heap_usage),
++					      &info->heap_usage);
++		else
++			r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE,
++					      sizeof(info->heap_usage),
++					      &info->heap_usage);
++		if (r)
++			return r;
++		break;
++	case AMDGPU_GEM_DOMAIN_GTT:
++		info->heap_size = vram_gtt_info.gtt_size;
++		info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
++
++		r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE,
++				      sizeof(info->heap_usage),
++				      &info->heap_usage);
++		if (r)
++			return r;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
+diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
+new file mode 100644
+index 0000000..b27756d
+--- /dev/null
++++ b/amdgpu/amdgpu_internal.h
+@@ -0,0 +1,210 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef _amdgpu_internal_h_
++#define _amdgpu_internal_h_
++
++#ifdef HAVE_CONFIG_H
++#include "config.h"
++#endif
++
++#include <assert.h>
++#include <pthread.h>
++#include "xf86atomic.h"
++#include "amdgpu.h"
++#include "util_double_list.h"
++
++#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
++
++#define AMDGPU_CS_MAX_RINGS 8
++
++struct amdgpu_bo_va_hole {
++	struct list_head list;
++	uint64_t offset;
++	uint64_t size;
++};
++
++struct amdgpu_bo_va_mgr {
++	/* the start virtual address */
++	uint64_t va_offset;
++	struct list_head va_holes;
++	pthread_mutex_t bo_va_mutex;
++	uint32_t va_alignment;
++};
++
++struct amdgpu_device {
++	atomic_t refcount;
++	int fd;
++	int flink_fd;
++	unsigned major_version;
++	unsigned minor_version;
++
++	/** List of buffer handles. Protected by bo_table_mutex. */
++	struct util_hash_table *bo_handles;
++	/** List of buffer GEM flink names. Protected by bo_table_mutex. */
++	struct util_hash_table *bo_flink_names;
++	/** List of buffer virtual memory ranges. Protected by bo_table_mutex. */
++	struct util_hash_table *bo_vas;
++	/** This protects all hash tables. */
++	pthread_mutex_t bo_table_mutex;
++	struct amdgpu_bo_va_mgr vamgr;
++	struct drm_amdgpu_info_device dev_info;
++	struct amdgpu_gpu_info info;
++};
++
++struct amdgpu_bo {
++	atomic_t refcount;
++	struct amdgpu_device *dev;
++
++	uint64_t alloc_size;
++	uint64_t virtual_mc_base_address;
++
++	uint32_t handle;
++	uint32_t flink_name;
++
++	pthread_mutex_t cpu_access_mutex;
++	void *cpu_ptr;
++	int cpu_map_count;
++};
++
++/*
++ * There are three mutexes.
++ * To avoid deadlock, only hold the mutexes in this order:
++ * sequence_mutex -> pendings_mutex -> pool_mutex.
++*/
++struct amdgpu_context {
++	/** Mutex for accessing fences and to maintain command submissions
++	    and pending lists in good sequence. */
++	pthread_mutex_t sequence_mutex;
++	/** Buffer for user fences */
++	struct amdgpu_ib *fence_ib;
++	/** The newest expired fence for the ring of the ip blocks. */
++	uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
++	/** Mutex for accessing pendings list. */
++	pthread_mutex_t pendings_mutex;
++	/** Pending IBs. */
++	struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
++	/** Freed IBs not yet in pool */
++	struct list_head freed;
++	/** Mutex for accessing free ib pool. */
++	pthread_mutex_t pool_mutex;
++	/** Internal free IB pools. */
++	struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM];
++	/* context id*/
++	uint32_t id;
++};
++
++struct amdgpu_ib {
++	struct list_head list_node;
++	amdgpu_bo_handle buf_handle;
++	void *cpu;
++	uint64_t virtual_mc_base_address;
++	enum amdgpu_cs_ib_size ib_size;
++	uint64_t cs_handle;
++};
++
++/**
++ * Functions.
++ */
++
++void amdgpu_device_free_internal(amdgpu_device_handle dev);
++
++void amdgpu_bo_free_internal(amdgpu_bo_handle bo);
++
++void amdgpu_vamgr_init(struct amdgpu_device *dev);
++
++uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr,
++                               uint64_t size, uint64_t alignment);
++
++void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va,
++                           uint64_t size);
++
++int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
++
++uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
++
++/**
++ * Inline functions.
++ */
++
++/**
++ * Increment src and decrement dst as if we were updating references
++ * for an assignment between 2 pointers of some objects.
++ *
++ * \return  true if dst is 0
++ */
++static inline bool update_references(atomic_t *dst, atomic_t *src)
++{
++	if (dst != src) {
++		/* bump src first */
++		if (src) {
++			assert(atomic_read(src) > 0);
++			atomic_inc(src);
++		}
++		if (dst) {
++			assert(atomic_read(dst) > 0);
++			return atomic_dec_and_test(dst);
++		}
++	}
++	return false;
++}
++
++/**
++ * Assignment between two amdgpu_bo pointers with reference counting.
++ *
++ * Usage:
++ *    struct amdgpu_bo *dst = ... , *src = ...;
++ *
++ *    dst = src;
++ *    // No reference counting. Only use this when you need to move
++ *    // a reference from one pointer to another.
++ *
++ *    amdgpu_bo_reference(&dst, src);
++ *    // Reference counters are updated. dst is decremented and src is
++ *    // incremented. dst is freed if its reference counter is 0.
++ */
++static inline void amdgpu_bo_reference(struct amdgpu_bo **dst,
++					struct amdgpu_bo *src)
++{
++	if (update_references(&(*dst)->refcount, &src->refcount))
++		amdgpu_bo_free_internal(*dst);
++	*dst = src;
++}
++
++/**
++ * Assignment between two amdgpu_device pointers with reference counting.
++ *
++ * Usage:
++ *    struct amdgpu_device *dst = ... , *src = ...;
++ *
++ *    dst = src;
++ *    // No reference counting. Only use this when you need to move
++ *    // a reference from one pointer to another.
++ *
++ *    amdgpu_device_reference(&dst, src);
++ *    // Reference counters are updated. dst is decremented and src is
++ *    // incremented. dst is freed if its reference counter is 0.
++ */
++void amdgpu_device_reference(struct amdgpu_device **dst,
++			     struct amdgpu_device *src);
++#endif
+diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
+new file mode 100644
+index 0000000..2335912
+--- /dev/null
++++ b/amdgpu/amdgpu_vamgr.c
+@@ -0,0 +1,169 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++
++#include <stdlib.h>
++#include <string.h>
++#include "amdgpu.h"
++#include "amdgpu_drm.h"
++#include "amdgpu_internal.h"
++#include "util_math.h"
++
++void amdgpu_vamgr_init(struct amdgpu_device *dev)
++{
++	struct amdgpu_bo_va_mgr *vamgr = &dev->vamgr;
++
++	vamgr->va_offset = dev->dev_info.virtual_address_offset;
++	vamgr->va_alignment = dev->dev_info.virtual_address_alignment;
++
++	list_inithead(&vamgr->va_holes);
++	pthread_mutex_init(&vamgr->bo_va_mutex, NULL);
++}
++
++uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr,
++                               uint64_t size, uint64_t alignment)
++{
++        struct amdgpu_bo_va_hole *hole, *n;
++        uint64_t offset = 0, waste = 0;
++
++        alignment = MAX2(alignment, mgr->va_alignment);
++        size = ALIGN(size, mgr->va_alignment);
++
++        pthread_mutex_lock(&mgr->bo_va_mutex);
++        /* TODO: using more appropriate way to track the holes */
++        /* first look for a hole */
++        LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
++                offset = hole->offset;
++                waste = offset % alignment;
++                waste = waste ? alignment - waste : 0;
++                offset += waste;
++                if (offset >= (hole->offset + hole->size)) {
++                        continue;
++                }
++                if (!waste && hole->size == size) {
++                        offset = hole->offset;
++                        list_del(&hole->list);
++                        free(hole);
++                        pthread_mutex_unlock(&mgr->bo_va_mutex);
++                        return offset;
++                }
++                if ((hole->size - waste) > size) {
++                        if (waste) {
++                                n = calloc(1,
++                                           sizeof(struct amdgpu_bo_va_hole));
++                                n->size = waste;
++                                n->offset = hole->offset;
++                                list_add(&n->list, &hole->list);
++                        }
++                        hole->size -= (size + waste);
++                        hole->offset += size + waste;
++                        pthread_mutex_unlock(&mgr->bo_va_mutex);
++                        return offset;
++                }
++                if ((hole->size - waste) == size) {
++                        hole->size = waste;
++                        pthread_mutex_unlock(&mgr->bo_va_mutex);
++                        return offset;
++                }
++        }
++
++        offset = mgr->va_offset;
++        waste = offset % alignment;
++        waste = waste ? alignment - waste : 0;
++        if (waste) {
++                n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
++                n->size = waste;
++                n->offset = offset;
++                list_add(&n->list, &mgr->va_holes);
++        }
++        offset += waste;
++        mgr->va_offset += size + waste;
++        pthread_mutex_unlock(&mgr->bo_va_mutex);
++        return offset;
++}
++
++void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va,
++                           uint64_t size)
++{
++        struct amdgpu_bo_va_hole *hole;
++
++        size = ALIGN(size, mgr->va_alignment);
++
++        pthread_mutex_lock(&mgr->bo_va_mutex);
++        if ((va + size) == mgr->va_offset) {
++                mgr->va_offset = va;
++                /* Delete uppermost hole if it reaches the new top */
++                if (!LIST_IS_EMPTY(&mgr->va_holes)) {
++                        hole = container_of(mgr->va_holes.next, hole, list);
++                        if ((hole->offset + hole->size) == va) {
++                                mgr->va_offset = hole->offset;
++                                list_del(&hole->list);
++                                free(hole);
++                        }
++                }
++        } else {
++                struct amdgpu_bo_va_hole *next;
++
++                hole = container_of(&mgr->va_holes, hole, list);
++                LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
++                        if (next->offset < va)
++                                break;
++                        hole = next;
++                }
++
++                if (&hole->list != &mgr->va_holes) {
++                        /* Grow upper hole if it's adjacent */
++                        if (hole->offset == (va + size)) {
++                                hole->offset = va;
++                                hole->size += size;
++                                /* Merge lower hole if it's adjacent */
++                                if (next != hole
++                                    && &next->list != &mgr->va_holes
++                                    && (next->offset + next->size) == va) {
++                                        next->size += hole->size;
++                                        list_del(&hole->list);
++                                        free(hole);
++                                }
++                                goto out;
++                        }
++                }
++
++                /* Grow lower hole if it's adjacent */
++                if (next != hole && &next->list != &mgr->va_holes &&
++                    (next->offset + next->size) == va) {
++                        next->size += size;
++                        goto out;
++                }
++
++                /* FIXME on allocation failure we just lose virtual address space
++                 * maybe print a warning
++                 */
++                next = calloc(1, sizeof(struct amdgpu_bo_va_hole));
++                if (next) {
++                        next->size = size;
++                        next->offset = va;
++                        list_add(&next->list, &hole->list);
++                }
++        }
++out:
++        pthread_mutex_unlock(&mgr->bo_va_mutex);
++}
+diff --git a/amdgpu/libdrm_amdgpu.pc.in b/amdgpu/libdrm_amdgpu.pc.in
+new file mode 100644
+index 0000000..417865e
+--- /dev/null
++++ b/amdgpu/libdrm_amdgpu.pc.in
+@@ -0,0 +1,10 @@
++prefix=@prefix@
++exec_prefix=@exec_prefix@
++libdir=@libdir@
++includedir=@includedir@
++
++Name: libdrm_amdgpu
++Description: Userspace interface to kernel DRM services for amdgpu
++Version: @PACKAGE_VERSION@
++Libs: -L${libdir} -ldrm_amdgpu
++Cflags: -I${includedir} -I${includedir}/libdrm
+diff --git a/amdgpu/util_double_list.h b/amdgpu/util_double_list.h
+new file mode 100644
+index 0000000..3f48ae2
+--- /dev/null
++++ b/amdgpu/util_double_list.h
+@@ -0,0 +1,146 @@
++/**************************************************************************
++ *
++ * Copyright 2006 VMware, Inc., Bismarck, ND. USA.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ **************************************************************************/
++
++/**
++ * \file
++ * List macros heavily inspired by the Linux kernel
++ * list handling. No list looping yet.
++ *
++ * Is not threadsafe, so common operations need to
++ * be protected using an external mutex.
++ */
++
++#ifndef _U_DOUBLE_LIST_H_
++#define _U_DOUBLE_LIST_H_
++
++
++#include <stddef.h>
++
++
++struct list_head
++{
++    struct list_head *prev;
++    struct list_head *next;
++};
++
++static inline void list_inithead(struct list_head *item)
++{
++    item->prev = item;
++    item->next = item;
++}
++
++static inline void list_add(struct list_head *item, struct list_head *list)
++{
++    item->prev = list;
++    item->next = list->next;
++    list->next->prev = item;
++    list->next = item;
++}
++
++static inline void list_addtail(struct list_head *item, struct list_head *list)
++{
++    item->next = list;
++    item->prev = list->prev;
++    list->prev->next = item;
++    list->prev = item;
++}
++
++static inline void list_replace(struct list_head *from, struct list_head *to)
++{
++    to->prev = from->prev;
++    to->next = from->next;
++    from->next->prev = to;
++    from->prev->next = to;
++}
++
++static inline void list_del(struct list_head *item)
++{
++    item->prev->next = item->next;
++    item->next->prev = item->prev;
++    item->prev = item->next = NULL;
++}
++
++static inline void list_delinit(struct list_head *item)
++{
++    item->prev->next = item->next;
++    item->next->prev = item->prev;
++    item->next = item;
++    item->prev = item;
++}
++
++#define LIST_INITHEAD(__item) list_inithead(__item)
++#define LIST_ADD(__item, __list) list_add(__item, __list)
++#define LIST_ADDTAIL(__item, __list) list_addtail(__item, __list)
++#define LIST_REPLACE(__from, __to) list_replace(__from, __to)
++#define LIST_DEL(__item) list_del(__item)
++#define LIST_DELINIT(__item) list_delinit(__item)
++
++#define LIST_ENTRY(__type, __item, __field)   \
++    ((__type *)(((char *)(__item)) - offsetof(__type, __field)))
++
++#define LIST_IS_EMPTY(__list)                   \
++    ((__list)->next == (__list))
++
++/**
++ * Cast from a pointer to a member of a struct back to the containing struct.
++ *
++ * 'sample' MUST be initialized, or else the result is undefined!
++ */
++#ifndef container_of
++#define container_of(ptr, sample, member)				\
++    (void *)((char *)(ptr)						\
++	     - ((char *)&(sample)->member - (char *)(sample)))
++#endif
++
++#define LIST_FOR_EACH_ENTRY(pos, head, member)				\
++   for (pos = NULL, pos = container_of((head)->next, pos, member);	\
++	&pos->member != (head);						\
++	pos = container_of(pos->member.next, pos, member))
++
++#define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head, member)	\
++   for (pos = NULL, pos = container_of((head)->next, pos, member),	\
++	storage = container_of(pos->member.next, pos, member);	\
++	&pos->member != (head);						\
++	pos = storage, storage = container_of(storage->member.next, storage, member))
++
++#define LIST_FOR_EACH_ENTRY_SAFE_REV(pos, storage, head, member)	\
++   for (pos = NULL, pos = container_of((head)->prev, pos, member),	\
++	storage = container_of(pos->member.prev, pos, member);		\
++	&pos->member != (head);						\
++	pos = storage, storage = container_of(storage->member.prev, storage, member))
++
++#define LIST_FOR_EACH_ENTRY_FROM(pos, start, head, member)		\
++   for (pos = NULL, pos = container_of((start), pos, member);		\
++	&pos->member != (head);						\
++	pos = container_of(pos->member.next, pos, member))
++
++#define LIST_FOR_EACH_ENTRY_FROM_REV(pos, start, head, member)		\
++   for (pos = NULL, pos = container_of((start), pos, member);		\
++	&pos->member != (head);						\
++	pos = container_of(pos->member.prev, pos, member))
++
++#endif /*_U_DOUBLE_LIST_H_*/
+diff --git a/amdgpu/util_hash.c b/amdgpu/util_hash.c
+new file mode 100644
+index 0000000..b1e12c4
+--- /dev/null
++++ b/amdgpu/util_hash.c
+@@ -0,0 +1,382 @@
++/**************************************************************************
++ *
++ * Copyright 2007 VMware, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
++ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
++
++ /*
++  * Authors:
++  *   Zack Rusin <zackr@vmware.com>
++  */
++
++#include "util_hash.h"
++
++#include <stdlib.h>
++#include <assert.h>
++
++#define MAX(a, b) ((a > b) ? (a) : (b))
++
++static const int MinNumBits = 4;
++
++static const unsigned char prime_deltas[] = {
++	0,  0,  1,  3,  1,  5,  3,  3,  1,  9,  7,  5,  3,  9, 25,  3,
++	1, 21,  3, 21,  7, 15,  9,  5,  3, 29, 15,  0,  0,  0,  0,  0
++};
++
++static int primeForNumBits(int numBits)
++{
++	return (1 << numBits) + prime_deltas[numBits];
++}
++
++/* Returns the smallest integer n such that
++   primeForNumBits(n) >= hint.
++*/
++static int countBits(int hint)
++{
++	int numBits = 0;
++	int bits = hint;
++
++	while (bits > 1) {
++		bits >>= 1;
++		numBits++;
++	}
++
++	if (numBits >= (int)sizeof(prime_deltas)) {
++		numBits = sizeof(prime_deltas) - 1;
++	} else if (primeForNumBits(numBits) < hint) {
++		++numBits;
++	}
++	return numBits;
++}
++
++struct util_node {
++   struct util_node *next;
++   unsigned key;
++   void *value;
++};
++
++struct util_hash_data {
++   struct util_node *fakeNext;
++   struct util_node **buckets;
++   int size;
++   int nodeSize;
++   short userNumBits;
++   short numBits;
++   int numBuckets;
++};
++
++struct util_hash {
++   union {
++      struct util_hash_data *d;
++      struct util_node      *e;
++   } data;
++};
++
++static void *util_data_allocate_node(struct util_hash_data *hash)
++{
++   return malloc(hash->nodeSize);
++}
++
++static void util_free_node(struct util_node *node)
++{
++   free(node);
++}
++
++static struct util_node *
++util_hash_create_node(struct util_hash *hash,
++                      unsigned akey, void *avalue,
++                      struct util_node **anextNode)
++{
++   struct util_node *node = util_data_allocate_node(hash->data.d);
++
++   if (!node)
++      return NULL;
++
++   node->key = akey;
++   node->value = avalue;
++
++   node->next = (struct util_node*)(*anextNode);
++   *anextNode = node;
++   ++hash->data.d->size;
++   return node;
++}
++
++static void util_data_rehash(struct util_hash_data *hash, int hint)
++{
++   if (hint < 0) {
++      hint = countBits(-hint);
++      if (hint < MinNumBits)
++         hint = MinNumBits;
++      hash->userNumBits = (short)hint;
++      while (primeForNumBits(hint) < (hash->size >> 1))
++         ++hint;
++   } else if (hint < MinNumBits) {
++      hint = MinNumBits;
++   }
++
++   if (hash->numBits != hint) {
++      struct util_node *e = (struct util_node *)(hash);
++      struct util_node **oldBuckets = hash->buckets;
++      int oldNumBuckets = hash->numBuckets;
++      int  i = 0;
++
++      hash->numBits = (short)hint;
++      hash->numBuckets = primeForNumBits(hint);
++      hash->buckets = malloc(sizeof(struct util_node*) * hash->numBuckets);
++      for (i = 0; i < hash->numBuckets; ++i)
++         hash->buckets[i] = e;
++
++      for (i = 0; i < oldNumBuckets; ++i) {
++         struct util_node *firstNode = oldBuckets[i];
++         while (firstNode != e) {
++            unsigned h = firstNode->key;
++            struct util_node *lastNode = firstNode;
++            struct util_node *afterLastNode;
++            struct util_node **beforeFirstNode;
++            
++            while (lastNode->next != e && lastNode->next->key == h)
++               lastNode = lastNode->next;
++
++            afterLastNode = lastNode->next;
++            beforeFirstNode = &hash->buckets[h % hash->numBuckets];
++            while (*beforeFirstNode != e)
++               beforeFirstNode = &(*beforeFirstNode)->next;
++            lastNode->next = *beforeFirstNode;
++            *beforeFirstNode = firstNode;
++            firstNode = afterLastNode;
++         }
++      }
++      free(oldBuckets);
++   }
++}
++
++static void util_data_might_grow(struct util_hash_data *hash)
++{
++   if (hash->size >= hash->numBuckets)
++      util_data_rehash(hash, hash->numBits + 1);
++}
++
++static void util_data_has_shrunk(struct util_hash_data *hash)
++{
++   if (hash->size <= (hash->numBuckets >> 3) &&
++       hash->numBits > hash->userNumBits) {
++      int max = MAX(hash->numBits-2, hash->userNumBits);
++      util_data_rehash(hash,  max);
++   }
++}
++
++static struct util_node *util_data_first_node(struct util_hash_data *hash)
++{
++   struct util_node *e = (struct util_node *)(hash);
++   struct util_node **bucket = hash->buckets;
++   int n = hash->numBuckets;
++   while (n--) {
++      if (*bucket != e)
++         return *bucket;
++      ++bucket;
++   }
++   return e;
++}
++
++static struct util_node **util_hash_find_node(struct util_hash *hash, unsigned akey)
++{
++   struct util_node **node;
++
++   if (hash->data.d->numBuckets) {
++      node = (struct util_node **)(&hash->data.d->buckets[akey % hash->data.d->numBuckets]);
++      assert(*node == hash->data.e || (*node)->next);
++      while (*node != hash->data.e && (*node)->key != akey)
++         node = &(*node)->next;
++   } else {
++      node = (struct util_node **)((const struct util_node * const *)(&hash->data.e));
++   }
++   return node;
++}
++
++struct util_hash_iter util_hash_insert(struct util_hash *hash,
++                                       unsigned key, void *data)
++{
++   util_data_might_grow(hash->data.d);
++
++   {
++      struct util_node **nextNode = util_hash_find_node(hash, key);
++      struct util_node *node = util_hash_create_node(hash, key, data, nextNode);
++      if (!node) {
++         struct util_hash_iter null_iter = {hash, 0};
++         return null_iter;
++      }
++
++      {
++         struct util_hash_iter iter = {hash, node};
++         return iter;
++      }
++   }
++}
++
++struct util_hash * util_hash_create(void)
++{
++   struct util_hash *hash = malloc(sizeof(struct util_hash));
++   if (!hash)
++      return NULL;
++
++   hash->data.d = malloc(sizeof(struct util_hash_data));
++   if (!hash->data.d) {
++      free(hash);
++      return NULL;
++   }
++
++   hash->data.d->fakeNext = 0;
++   hash->data.d->buckets = 0;
++   hash->data.d->size = 0;
++   hash->data.d->nodeSize = sizeof(struct util_node);
++   hash->data.d->userNumBits = (short)MinNumBits;
++   hash->data.d->numBits = 0;
++   hash->data.d->numBuckets = 0;
++
++   return hash;
++}
++
++void util_hash_delete(struct util_hash *hash)
++{
++   struct util_node *e_for_x = (struct util_node *)(hash->data.d);
++   struct util_node **bucket = (struct util_node **)(hash->data.d->buckets);
++   int n = hash->data.d->numBuckets;
++   while (n--) {
++      struct util_node *cur = *bucket++;
++      while (cur != e_for_x) {
++         struct util_node *next = cur->next;
++         util_free_node(cur);
++         cur = next;
++      }
++   }
++   free(hash->data.d->buckets);
++   free(hash->data.d);
++   free(hash);
++}
++
++struct util_hash_iter util_hash_find(struct util_hash *hash,
++                                     unsigned key)
++{
++   struct util_node **nextNode = util_hash_find_node(hash, key);
++   struct util_hash_iter iter = {hash, *nextNode};
++   return iter;
++}
++
++unsigned util_hash_iter_key(struct util_hash_iter iter)
++{
++   if (!iter.node || iter.hash->data.e == iter.node)
++      return 0;
++   return iter.node->key;
++}
++
++void * util_hash_iter_data(struct util_hash_iter iter)
++{
++   if (!iter.node || iter.hash->data.e == iter.node)
++      return 0;
++   return iter.node->value;
++}
++
++static struct util_node *util_hash_data_next(struct util_node *node)
++{
++   union {
++      struct util_node *next;
++      struct util_node *e;
++      struct util_hash_data *d;
++   } a;
++   int start;
++   struct util_node **bucket;
++   int n;
++
++   a.next = node->next;
++   if (!a.next) {
++      /* iterating beyond the last element */
++      return 0;
++   }
++   if (a.next->next)
++      return a.next;
++
++   start = (node->key % a.d->numBuckets) + 1;
++   bucket = a.d->buckets + start;
++   n = a.d->numBuckets - start;
++   while (n--) {
++      if (*bucket != a.e)
++         return *bucket;
++      ++bucket;
++   }
++   return a.e;
++}
++
++struct util_hash_iter util_hash_iter_next(struct util_hash_iter iter)
++{
++   struct util_hash_iter next = {iter.hash, util_hash_data_next(iter.node)};
++   return next;
++}
++
++int util_hash_iter_is_null(struct util_hash_iter iter)
++{
++   if (!iter.node || iter.node == iter.hash->data.e)
++      return 1;
++   return 0;
++}
++
++void * util_hash_take(struct util_hash *hash,
++                      unsigned akey)
++{
++   struct util_node **node = util_hash_find_node(hash, akey);
++   if (*node != hash->data.e) {
++      void *t = (*node)->value;
++      struct util_node *next = (*node)->next;
++      util_free_node(*node);
++      *node = next;
++      --hash->data.d->size;
++      util_data_has_shrunk(hash->data.d);
++      return t;
++   }
++   return 0;
++}
++
++struct util_hash_iter util_hash_first_node(struct util_hash *hash)
++{
++   struct util_hash_iter iter = {hash, util_data_first_node(hash->data.d)};
++   return iter;
++}
++
++struct util_hash_iter util_hash_erase(struct util_hash *hash, struct util_hash_iter iter)
++{
++   struct util_hash_iter ret = iter;
++   struct util_node *node = iter.node;
++   struct util_node **node_ptr;
++
++   if (node == hash->data.e)
++      return iter;
++
++   ret = util_hash_iter_next(ret);
++   node_ptr = (struct util_node**)(&hash->data.d->buckets[node->key % hash->data.d->numBuckets]);
++   while (*node_ptr != node)
++      node_ptr = &(*node_ptr)->next;
++   *node_ptr = node->next;
++   util_free_node(node);
++   --hash->data.d->size;
++   return ret;
++}
+diff --git a/amdgpu/util_hash.h b/amdgpu/util_hash.h
+new file mode 100644
+index 0000000..8e0f9a2
+--- /dev/null
++++ b/amdgpu/util_hash.h
+@@ -0,0 +1,99 @@
++/**************************************************************************
++ *
++ * Copyright 2007 VMware, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
++ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
++
++/**
++ * @file
++ * Hash implementation.
++ * 
++ * This file provides a hash implementation that is capable of dealing
++ * with collisions. It stores colliding entries in linked list. All
++ * functions operating on the hash return an iterator. The iterator
++ * itself points to the collision list. If there wasn't any collision
++ * the list will have just one entry, otherwise client code should
++ * iterate over the entries to find the exact entry among ones that
++ * had the same key (e.g. memcmp could be used on the data to check
++ * that)
++ * 
++ * @author Zack Rusin <zackr@vmware.com>
++ */
++
++#ifndef UTIL_HASH_H
++#define UTIL_HASH_H
++
++#include <stdbool.h>
++
++struct util_hash;
++struct util_node;
++
++struct util_hash_iter {
++	struct util_hash *hash;
++	struct util_node *node;
++};
++
++
++struct util_hash *util_hash_create(void);
++void util_hash_delete(struct util_hash *hash);
++
++
++/**
++ * Adds a data with the given key to the hash. If entry with the given
++ * key is already in the hash, this current entry is instered before it
++ * in the collision list.
++ * Function returns iterator pointing to the inserted item in the hash.
++ */
++struct util_hash_iter util_hash_insert(struct util_hash *hash, unsigned key,
++				       void *data);
++
++/**
++ * Removes the item pointed to by the current iterator from the hash.
++ * Note that the data itself is not erased and if it was a malloc'ed pointer
++ * it will have to be freed after calling this function by the callee.
++ * Function returns iterator pointing to the item after the removed one in
++ * the hash.
++ */
++struct util_hash_iter util_hash_erase(struct util_hash *hash,
++				      struct util_hash_iter iter);
++
++void *util_hash_take(struct util_hash *hash, unsigned key);
++
++
++struct util_hash_iter util_hash_first_node(struct util_hash *hash);
++
++/**
++ * Return an iterator pointing to the first entry in the collision list.
++ */
++struct util_hash_iter util_hash_find(struct util_hash *hash, unsigned key);
++
++
++int util_hash_iter_is_null(struct util_hash_iter iter);
++unsigned util_hash_iter_key(struct util_hash_iter iter);
++void *util_hash_iter_data(struct util_hash_iter iter);
++
++
++struct util_hash_iter util_hash_iter_next(struct util_hash_iter iter);
++
++#endif
+diff --git a/amdgpu/util_hash_table.c b/amdgpu/util_hash_table.c
+new file mode 100644
+index 0000000..cb7213c
+--- /dev/null
++++ b/amdgpu/util_hash_table.c
+@@ -0,0 +1,257 @@
++/**************************************************************************
++ *
++ * Copyright 2008 VMware, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
++ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
++
++/**
++ * @file
++ * General purpose hash table implementation.
++ * 
++ * Just uses the util_hash for now, but it might be better switch to a linear
++ * probing hash table implementation at some point -- as it is said they have 
++ * better lookup and cache performance and it appears to be possible to write 
++ * a lock-free implementation of such hash tables . 
++ * 
++ * @author José Fonseca <jfonseca@vmware.com>
++ */
++
++
++
++#include "util_hash_table.h"
++#include "util_hash.h"
++
++#include <stdlib.h>
++#include <assert.h>
++
++struct util_hash_table
++{
++	struct util_hash *head;
++
++	/** Hash function */
++	unsigned (*make_hash)(void *key);
++
++	/** Compare two keys */
++	int (*compare)(void *key1, void *key2);
++};
++
++struct util_hash_table_item
++{
++	void *key;
++	void *value;
++};
++
++
++static struct util_hash_table_item *
++util_hash_table_item(struct util_hash_iter iter)
++{
++	return (struct util_hash_table_item *)util_hash_iter_data(iter);
++}
++
++struct util_hash_table *util_hash_table_create(unsigned (*hash)(void *key),
++				int (*compare)(void *key1, void *key2))
++{
++	struct util_hash_table *ht;
++
++	ht = malloc(sizeof(struct util_hash_table));
++	if(!ht)
++		return NULL;
++
++	ht->head = util_hash_create();
++	if(!ht->head) {
++		free(ht);
++		return NULL;
++	}
++
++	ht->make_hash = hash;
++	ht->compare = compare;
++
++	return ht;
++}
++
++static struct util_hash_iter
++util_hash_table_find_iter(struct util_hash_table *ht,
++			  void *key, unsigned key_hash)
++{
++	struct util_hash_iter iter;
++	struct util_hash_table_item *item;
++
++	iter = util_hash_find(ht->head, key_hash);
++	while (!util_hash_iter_is_null(iter)) {
++		item = (struct util_hash_table_item *)util_hash_iter_data(iter);
++		if (!ht->compare(item->key, key))
++			break;
++		iter = util_hash_iter_next(iter);
++	}
++
++	return iter;
++}
++
++static struct util_hash_table_item *
++util_hash_table_find_item(struct util_hash_table *ht,
++                          void *key, unsigned key_hash)
++{
++	struct util_hash_iter iter;
++	struct util_hash_table_item *item;
++
++	iter = util_hash_find(ht->head, key_hash);
++	while (!util_hash_iter_is_null(iter)) {
++		item = (struct util_hash_table_item *)util_hash_iter_data(iter);
++		if (!ht->compare(item->key, key))
++			return item;
++		iter = util_hash_iter_next(iter);
++	}
++
++	return NULL;
++}
++
++void util_hash_table_set(struct util_hash_table *ht, void *key, void *value)
++{
++	unsigned key_hash;
++	struct util_hash_table_item *item;
++	struct util_hash_iter iter;
++
++	assert(ht);
++	if (!ht)
++		return;
++
++	key_hash = ht->make_hash(key);
++
++	item = util_hash_table_find_item(ht, key, key_hash);
++	if(item) {
++		/* TODO: key/value destruction? */
++		item->value = value;
++		return;
++	}
++
++	item = malloc(sizeof(struct util_hash_table_item));
++	if(!item)
++		return;
++
++	item->key = key;
++	item->value = value;
++
++	iter = util_hash_insert(ht->head, key_hash, item);
++	if(util_hash_iter_is_null(iter)) {
++		free(item);
++		return;
++	}
++}
++
++void *util_hash_table_get(struct util_hash_table *ht, void *key)
++{
++	unsigned key_hash;
++	struct util_hash_table_item *item;
++
++	assert(ht);
++	if (!ht)
++		return NULL;
++
++	key_hash = ht->make_hash(key);
++
++	item = util_hash_table_find_item(ht, key, key_hash);
++	if(!item)
++		return NULL;
++
++	return item->value;
++}
++
++void util_hash_table_remove(struct util_hash_table *ht, void *key)
++{
++	unsigned key_hash;
++	struct util_hash_iter iter;
++	struct util_hash_table_item *item;
++
++	assert(ht);
++	if (!ht)
++		return;
++
++	key_hash = ht->make_hash(key);
++
++	iter = util_hash_table_find_iter(ht, key, key_hash);
++	if(util_hash_iter_is_null(iter))
++		return;
++
++	item = util_hash_table_item(iter);
++	assert(item);
++	free(item);
++
++	util_hash_erase(ht->head, iter);
++}
++
++void util_hash_table_clear(struct util_hash_table *ht)
++{
++	struct util_hash_iter iter;
++	struct util_hash_table_item *item;
++
++	assert(ht);
++	if (!ht)
++		return;
++
++	iter = util_hash_first_node(ht->head);
++	while (!util_hash_iter_is_null(iter)) {
++		item = (struct util_hash_table_item *)util_hash_take(ht->head, util_hash_iter_key(iter));
++		free(item);
++		iter = util_hash_first_node(ht->head);
++	}
++}
++
++void util_hash_table_foreach(struct util_hash_table *ht,
++			void (*callback)(void *key, void *value, void *data),
++			void *data)
++{
++	struct util_hash_iter iter;
++	struct util_hash_table_item *item;
++
++	assert(ht);
++	if (!ht)
++		return;
++
++	iter = util_hash_first_node(ht->head);
++	while (!util_hash_iter_is_null(iter)) {
++		item = (struct util_hash_table_item *)util_hash_iter_data(iter);
++		callback(item->key, item->value, data);
++		iter = util_hash_iter_next(iter);
++	}
++}
++
++void util_hash_table_destroy(struct util_hash_table *ht)
++{
++	struct util_hash_iter iter;
++	struct util_hash_table_item *item;
++
++	assert(ht);
++	if (!ht)
++		return;
++
++	iter = util_hash_first_node(ht->head);
++	while (!util_hash_iter_is_null(iter)) {
++		item = (struct util_hash_table_item *)util_hash_iter_data(iter);
++		free(item);
++		iter = util_hash_iter_next(iter);
++	}
++
++	util_hash_delete(ht->head);
++	free(ht);
++}
+diff --git a/amdgpu/util_hash_table.h b/amdgpu/util_hash_table.h
+new file mode 100644
+index 0000000..04fe704
+--- /dev/null
++++ b/amdgpu/util_hash_table.h
+@@ -0,0 +1,65 @@
++/**************************************************************************
++ *
++ * Copyright 2008 VMware, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
++ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ **************************************************************************/
++
++/**
++ * General purpose hash table.
++ *  
++ * @author José Fonseca <jfonseca@vmware.com>
++ */
++
++#ifndef U_HASH_TABLE_H_
++#define U_HASH_TABLE_H_
++
++/**
++ * Generic purpose hash table.
++ */
++struct util_hash_table;
++
++/**
++ * Create an hash table.
++ * 
++ * @param hash hash function
++ * @param compare should return 0 for two equal keys.
++ */
++struct util_hash_table *util_hash_table_create(unsigned (*hash)(void *key),
++				int (*compare)(void *key1, void *key2));
++
++void util_hash_table_set(struct util_hash_table *ht, void *key, void *value);
++
++void *util_hash_table_get(struct util_hash_table *ht, void *key);
++
++void util_hash_table_remove(struct util_hash_table *ht, void *key);
++
++void util_hash_table_clear(struct util_hash_table *ht);
++
++void util_hash_table_foreach(struct util_hash_table *ht,
++			void (*callback)(void *key, void *value, void *data),
++			void *data);
++
++void util_hash_table_destroy(struct util_hash_table *ht);
++
++#endif /* U_HASH_TABLE_H_ */
+diff --git a/amdgpu/util_math.h b/amdgpu/util_math.h
+new file mode 100644
+index 0000000..b8de0f8
+--- /dev/null
++++ b/amdgpu/util_math.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++
++#ifndef _UTIL_MATH_H_
++#define _UTIL_MATH_H_
++
++#define MIN2( A, B )   ( (A)<(B) ? (A) : (B) )
++#define MAX2( A, B )   ( (A)>(B) ? (A) : (B) )
++
++#define ALIGN( value, alignment )   ( ((value) + (alignment) - 1) & ~((alignment) - 1) )
++
++#endif /*_UTIL_MATH_H_*/
+diff --git a/configure.ac b/configure.ac
+index 155d577..509f2d4 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -36,6 +36,7 @@ m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
+ 
+ # Check for programs
+ AC_PROG_CC
++AC_PROG_CXX
+ 
+ AC_USE_SYSTEM_EXTENSIONS
+ AC_SYS_LARGEFILE
+@@ -74,6 +75,11 @@ AC_ARG_ENABLE(radeon,
+ 	      [Enable support for radeon's KMS API (default: auto)]),
+ 	      [RADEON=$enableval], [RADEON=auto])
+ 
++AC_ARG_ENABLE(amdgpu,
++	      AS_HELP_STRING([--disable-amdgpu],
++	      [Enable support for amdgpu's KMS API (default: auto)]),
++	      [AMDGPU=$enableval], [AMDGPU=auto])
++
+ AC_ARG_ENABLE(nouveau,
+ 	      AS_HELP_STRING([--disable-nouveau],
+ 	      [Enable support for nouveau's KMS API (default: auto)]),
+@@ -236,6 +242,9 @@ if test "x$drm_cv_atomic_primitives" = "xnone"; then
+ 	LIBDRM_ATOMICS_NOT_FOUND_MSG($RADEON, radeon, Radeon, radeon)
+ 	RADEON=no
+ 
++	LIBDRM_ATOMICS_NOT_FOUND_MSG($AMDGPU, amdgpu, AMD, amdgpu)
++	AMDGPU=no
++
+ 	LIBDRM_ATOMICS_NOT_FOUND_MSG($NOUVEAU, nouveau, NVIDIA, nouveau)
+ 	NOUVEAU=no
+ 
+@@ -257,6 +266,9 @@ else
+ 	if test "x$RADEON" = xauto; then
+ 		RADEON=yes
+ 	fi
++	if test "x$AMDGPU" = xauto; then
++		AMDGPU=yes
++	fi
+ 	if test "x$NOUVEAU" = xauto; then
+ 		NOUVEAU=yes
+ 	fi
+@@ -336,6 +348,11 @@ if test "x$RADEON" = xyes; then
+ 	AC_DEFINE(HAVE_RADEON, 1, [Have radeon support])
+ fi
+ 
++AM_CONDITIONAL(HAVE_AMDGPU, [test "x$AMDGPU" = xyes])
++if test "x$AMDGPU" = xyes; then
++	AC_DEFINE(HAVE_AMDGPU, 1, [Have amdgpu support])
++fi
++
+ AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes])
+ if test "x$TEGRA" = xyes; then
+ 	AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support])
+@@ -432,6 +449,8 @@ AC_CONFIG_FILES([
+ 	intel/libdrm_intel.pc
+ 	radeon/Makefile
+ 	radeon/libdrm_radeon.pc
++	amdgpu/Makefile
++	amdgpu/libdrm_amdgpu.pc
+ 	nouveau/Makefile
+ 	nouveau/libdrm_nouveau.pc
+ 	omap/Makefile
+@@ -463,6 +482,7 @@ echo "  libkms         $LIBKMS"
+ echo "  Intel API      $INTEL"
+ echo "  vmwgfx API     $VMWGFX"
+ echo "  Radeon API     $RADEON"
++echo "  AMDGPU API     $AMDGPU"
+ echo "  Nouveau API    $NOUVEAU"
+ echo "  OMAP API       $OMAP"
+ echo "  EXYNOS API     $EXYNOS"
+diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
+new file mode 100644
+index 0000000..d248d77
+--- /dev/null
++++ b/include/drm/amdgpu_drm.h
+@@ -0,0 +1,600 @@
++/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
++ *
++ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
++ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
++ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ *    Kevin E. Martin <martin@valinux.com>
++ *    Gareth Hughes <gareth@valinux.com>
++ *    Keith Whitwell <keith@tungstengraphics.com>
++ */
++
++#ifndef __AMDGPU_DRM_H__
++#define __AMDGPU_DRM_H__
++
++#include <drm.h>
++
++#define DRM_AMDGPU_GEM_CREATE		0x00
++#define DRM_AMDGPU_GEM_MMAP		0x01
++#define DRM_AMDGPU_CTX			0x02
++#define DRM_AMDGPU_BO_LIST		0x03
++#define DRM_AMDGPU_CS			0x04
++#define DRM_AMDGPU_INFO			0x05
++#define DRM_AMDGPU_GEM_METADATA		0x06
++#define DRM_AMDGPU_GEM_WAIT_IDLE	0x07
++#define DRM_AMDGPU_GEM_VA		0x08
++#define DRM_AMDGPU_WAIT_CS		0x09
++#define DRM_AMDGPU_GEM_OP		0x10
++#define DRM_AMDGPU_GEM_USERPTR		0x11
++
++#define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
++#define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
++#define DRM_IOCTL_AMDGPU_CTX		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
++#define DRM_IOCTL_AMDGPU_BO_LIST	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
++#define DRM_IOCTL_AMDGPU_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
++#define DRM_IOCTL_AMDGPU_INFO		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
++#define DRM_IOCTL_AMDGPU_GEM_METADATA	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
++#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
++#define DRM_IOCTL_AMDGPU_GEM_VA		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
++#define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
++#define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
++#define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
++
++#define AMDGPU_GEM_DOMAIN_CPU		0x1
++#define AMDGPU_GEM_DOMAIN_GTT		0x2
++#define AMDGPU_GEM_DOMAIN_VRAM		0x4
++#define AMDGPU_GEM_DOMAIN_GDS		0x8
++#define AMDGPU_GEM_DOMAIN_GWS		0x10
++#define AMDGPU_GEM_DOMAIN_OA		0x20
++
++#define AMDGPU_GEM_DOMAIN_MASK		0x3F
++
++/* Flag that CPU access will be required for the case of VRAM domain */
++#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
++/* Flag that CPU access will not work, this VRAM domain is invisible */
++#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS		(1 << 1)
++/* Flag that un-cached attributes should be used for GTT */
++#define AMDGPU_GEM_CREATE_CPU_GTT_UC		(1 << 2)
++/* Flag that USWC attributes should be used for GTT */
++#define AMDGPU_GEM_CREATE_CPU_GTT_WC		(1 << 3)
++
++/* Flag mask for GTT domain_flags */
++#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
++	(AMDGPU_GEM_CREATE_CPU_GTT_WC | \
++	 AMDGPU_GEM_CREATE_CPU_GTT_UC | \
++	 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
++	 AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
++
++struct drm_amdgpu_gem_create_in  {
++	/** the requested memory size */
++	uint64_t bo_size;
++	/** physical start_addr alignment in bytes for some HW requirements */
++	uint64_t alignment;
++	/** the requested memory domains */
++	uint64_t domains;
++	/** allocation flags */
++	uint64_t domain_flags;
++};
++
++struct drm_amdgpu_gem_create_out  {
++	/** returned GEM object handle */
++	uint32_t handle;
++};
++
++union drm_amdgpu_gem_create {
++	struct drm_amdgpu_gem_create_in		in;
++	struct drm_amdgpu_gem_create_out	out;
++};
++
++/** Opcode to create new residency list.  */
++#define AMDGPU_BO_LIST_OP_CREATE	0
++/** Opcode to destroy previously created residency list */
++#define AMDGPU_BO_LIST_OP_DESTROY	1
++/** Opcode to update resource information in the list */
++#define AMDGPU_BO_LIST_OP_UPDATE	2
++
++struct drm_amdgpu_bo_list_in {
++	/** Type of operation */
++	uint32_t operation;
++	/** Handle of list or 0 if we want to create one */
++	uint32_t list_handle;
++	/** Number of BOs in list  */
++	uint32_t bo_number;
++	/** Size of each element describing BO */
++	uint32_t bo_info_size;
++	/** Pointer to array describing BOs */
++	uint64_t bo_info_ptr;
++};
++
++struct drm_amdgpu_bo_list_entry {
++	/** Handle of BO */
++	uint32_t bo_handle;
++	/** New (if specified) BO priority to be used during migration */
++	uint32_t bo_priority;
++};
++
++struct drm_amdgpu_bo_list_out {
++	/** Handle of resource list  */
++	uint32_t list_handle;
++};
++
++union drm_amdgpu_bo_list {
++	struct drm_amdgpu_bo_list_in in;
++	struct drm_amdgpu_bo_list_out out;
++};
++
++/* context related */
++#define AMDGPU_CTX_OP_ALLOC_CTX	1
++#define AMDGPU_CTX_OP_FREE_CTX	2
++#define AMDGPU_CTX_OP_QUERY_STATE	3
++
++#define AMDGPU_CTX_OP_STATE_RUNNING	1
++
++struct drm_amdgpu_ctx_in {
++	uint32_t	op;
++	uint32_t	flags;
++	uint32_t	ctx_id;
++	uint32_t	pad;
++};
++
++union drm_amdgpu_ctx_out {
++		struct {
++			uint32_t	ctx_id;
++		} alloc;
++
++		struct {
++			uint64_t	flags;
++			uint64_t	hangs;
++		} state;
++};
++
++union drm_amdgpu_ctx {
++	struct drm_amdgpu_ctx_in in;
++	union drm_amdgpu_ctx_out out;
++};
++
++/*
++ * This is not a reliable API and you should expect it to fail for any
++ * number of reasons and have fallback path that do not use userptr to
++ * perform any operation.
++ */
++#define AMDGPU_GEM_USERPTR_READONLY	(1 << 0)
++#define AMDGPU_GEM_USERPTR_ANONONLY	(1 << 1)
++#define AMDGPU_GEM_USERPTR_VALIDATE	(1 << 2)
++#define AMDGPU_GEM_USERPTR_REGISTER	(1 << 3)
++
++struct drm_amdgpu_gem_userptr {
++	uint64_t		addr;
++	uint64_t		size;
++	uint32_t		flags;
++	uint32_t		handle;
++};
++
++#define AMDGPU_TILING_MACRO				0x1
++#define AMDGPU_TILING_MICRO				0x2
++#define AMDGPU_TILING_SWAP_16BIT			0x4
++#define AMDGPU_TILING_R600_NO_SCANOUT			AMDGPU_TILING_SWAP_16BIT
++#define AMDGPU_TILING_SWAP_32BIT			0x8
++/* this object requires a surface when mapped - i.e. front buffer */
++#define AMDGPU_TILING_SURFACE				0x10
++#define AMDGPU_TILING_MICRO_SQUARE			0x20
++#define AMDGPU_TILING_EG_BANKW_SHIFT			8
++#define AMDGPU_TILING_EG_BANKW_MASK			0xf
++#define AMDGPU_TILING_EG_BANKH_SHIFT			12
++#define AMDGPU_TILING_EG_BANKH_MASK			0xf
++#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT	16
++#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK	0xf
++#define AMDGPU_TILING_EG_TILE_SPLIT_SHIFT		24
++#define AMDGPU_TILING_EG_TILE_SPLIT_MASK		0xf
++#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT	28
++#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf
++
++#define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
++#define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
++
++/** The same structure is shared for input/output */
++struct drm_amdgpu_gem_metadata {
++	uint32_t	handle;		/* GEM Object handle */
++	uint32_t	op;		/** Do we want get or set metadata */
++	struct {
++		uint64_t	flags;
++		uint64_t	tiling_info; /* family specific tiling info */
++		uint32_t	data_size_bytes;
++		uint32_t	data[64];
++	} data;
++};
++
++struct drm_amdgpu_gem_mmap_in {
++	uint32_t handle;		/** the GEM object handle */
++};
++
++struct drm_amdgpu_gem_mmap_out {
++	uint64_t addr_ptr;	/** mmap offset from the vma offset manager */
++};
++
++union drm_amdgpu_gem_mmap {
++	struct drm_amdgpu_gem_mmap_in   in;
++	struct drm_amdgpu_gem_mmap_out out;
++};
++
++struct drm_amdgpu_gem_wait_idle_in {
++	uint32_t handle;   	/* GEM object handle */
++	uint32_t flags;
++	uint64_t timeout; 	/* Timeout to wait. If 0 then returned immediately with the status */
++};
++
++struct drm_amdgpu_gem_wait_idle_out {
++	uint32_t status;	/*   BO status:  0 - BO is idle, 1 - BO is busy */
++	uint32_t domain; /*  Returned current memory domain */
++};
++
++union drm_amdgpu_gem_wait_idle {
++	struct drm_amdgpu_gem_wait_idle_in  in;
++	struct drm_amdgpu_gem_wait_idle_out out;
++};
++
++struct drm_amdgpu_wait_cs_in {
++	uint64_t handle;
++	uint64_t timeout;
++	uint32_t ip_type;
++	uint32_t ip_instance;
++	uint32_t ring;
++};
++
++struct drm_amdgpu_wait_cs_out {
++	uint64_t status;
++};
++
++union drm_amdgpu_wait_cs {
++	struct drm_amdgpu_wait_cs_in in;
++	struct drm_amdgpu_wait_cs_out out;
++};
++
++/* Sets or returns a value associated with a buffer. */
++struct drm_amdgpu_gem_op {
++	uint32_t	handle; /* buffer */
++	uint32_t	op;     /* AMDGPU_GEM_OP_* */
++	uint64_t	value;  /* input or return value */
++};
++
++#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO		0
++#define AMDGPU_GEM_OP_SET_INITIAL_DOMAIN	1
++
++#define AMDGPU_VA_OP_MAP			1
++#define AMDGPU_VA_OP_UNMAP			2
++
++#define AMDGPU_VA_RESULT_OK			0
++#define AMDGPU_VA_RESULT_ERROR			1
++#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT	2
++
++/* Mapping flags */
++/* readable mapping */
++#define AMDGPU_VM_PAGE_READABLE		(1 << 1)
++/* writable mapping */
++#define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
++/* executable mapping, new for VI */
++#define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
++
++struct drm_amdgpu_gem_va_in {
++	/* GEM object handle */
++	uint32_t handle;
++	uint32_t pad;
++	/* map or unmap*/
++	uint32_t operation;
++	/* specify mapping flags */
++	uint32_t flags;
++	/* va address to assign . Must be correctly aligned.*/
++	uint64_t va_address;
++	/* Specify offset inside of BO to assign. Must be correctly aligned.*/
++	uint64_t offset_in_bo;
++	/* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
++	/* Must be correctly aligned. */
++	uint64_t map_size;
++};
++
++struct drm_amdgpu_gem_va_out {
++	uint32_t result;
++};
++
++union drm_amdgpu_gem_va {
++	struct drm_amdgpu_gem_va_in  in;
++	struct drm_amdgpu_gem_va_out out;
++};
++
++#define AMDGPU_HW_IP_GFX          0
++#define AMDGPU_HW_IP_COMPUTE      1
++#define AMDGPU_HW_IP_DMA          2
++#define AMDGPU_HW_IP_UVD          3
++#define AMDGPU_HW_IP_VCE          4
++#define AMDGPU_HW_IP_NUM          5
++
++#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
++
++#define AMDGPU_CHUNK_ID_IB		0x01
++#define AMDGPU_CHUNK_ID_FENCE		0x02
++struct drm_amdgpu_cs_chunk {
++	uint32_t		chunk_id;
++	uint32_t		length_dw;
++	uint64_t		chunk_data;
++};
++
++struct drm_amdgpu_cs_in {
++	/** Rendering context id */
++	uint32_t		ctx_id;
++	/**  Handle of resource list associated with CS */
++	uint32_t		bo_list_handle;
++	uint32_t		num_chunks;
++	uint32_t		pad;
++	/* this points to uint64_t * which point to cs chunks */
++	uint64_t		chunks;
++};
++
++struct drm_amdgpu_cs_out {
++	uint64_t handle;
++};
++
++union drm_amdgpu_cs {
++       struct drm_amdgpu_cs_in in;
++       struct drm_amdgpu_cs_out out;
++};
++
++/* Specify flags to be used for IB */
++
++/* This IB should be submitted to CE */
++#define AMDGPU_IB_FLAG_CE	(1<<0)
++
++/* GDS is used by this IB */
++#define AMDGPU_IB_FLAG_GDS	(1<<1)
++
++struct drm_amdgpu_cs_chunk_ib {
++	/**
++	 * Handle of GEM object to be used as IB or 0 if it is already in
++	 * residency list.
++	 */
++	uint32_t handle;
++	uint32_t flags;		/* IB Flags */
++	uint64_t va_start;	/* Virtual address to begin IB execution */
++	uint32_t ib_bytes;	/* Size of submission */
++	uint32_t ip_type;	/* HW IP to submit to */
++	uint32_t ip_instance;	/* HW IP index of the same type to submit to  */
++	uint32_t ring;		/* Ring index to submit to */
++};
++
++struct drm_amdgpu_cs_chunk_fence {
++	uint32_t handle;
++	uint32_t offset;
++};
++
++struct drm_amdgpu_cs_chunk_data {
++	union {
++		struct drm_amdgpu_cs_chunk_ib		ib_data;
++		struct drm_amdgpu_cs_chunk_fence	fence_data;
++	};
++};
++
++/**
++ *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
++ *
++ */
++#define AMDGPU_IDS_FLAGS_FUSION         0x1
++
++/* indicate if acceleration can be working */
++#define AMDGPU_INFO_ACCEL_WORKING		0x00
++/* get the crtc_id from the mode object id? */
++#define AMDGPU_INFO_CRTC_FROM_ID		0x01
++/* query hw IP info */
++#define AMDGPU_INFO_HW_IP_INFO			0x02
++/* query hw IP instance count for the specified type */
++#define AMDGPU_INFO_HW_IP_COUNT			0x03
++/* timestamp for GL_ARB_timer_query */
++#define AMDGPU_INFO_TIMESTAMP			0x05
++/* Query the firmware version */
++#define AMDGPU_INFO_FW_VERSION			0x0e
++	/* Subquery id: Query VCE firmware version */
++	#define AMDGPU_INFO_FW_VCE		0x1
++	/* Subquery id: Query UVD firmware version */
++	#define AMDGPU_INFO_FW_UVD		0x2
++	/* Subquery id: Query GMC firmware version */
++	#define AMDGPU_INFO_FW_GMC		0x03
++	/* Subquery id: Query GFX ME firmware version */
++	#define AMDGPU_INFO_FW_GFX_ME		0x04
++	/* Subquery id: Query GFX PFP firmware version */
++	#define AMDGPU_INFO_FW_GFX_PFP		0x05
++	/* Subquery id: Query GFX CE firmware version */
++	#define AMDGPU_INFO_FW_GFX_CE		0x06
++	/* Subquery id: Query GFX RLC firmware version */
++	#define AMDGPU_INFO_FW_GFX_RLC		0x07
++	/* Subquery id: Query GFX MEC firmware version */
++	#define AMDGPU_INFO_FW_GFX_MEC		0x08
++	/* Subquery id: Query SMC firmware version */
++	#define AMDGPU_INFO_FW_SMC		0x0a
++	/* Subquery id: Query SDMA firmware version */
++	#define AMDGPU_INFO_FW_SDMA		0x0b
++/* number of bytes moved for TTM migration */
++#define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
++/* the used VRAM size */
++#define AMDGPU_INFO_VRAM_USAGE			0x10
++/* the used GTT size */
++#define AMDGPU_INFO_GTT_USAGE			0x11
++/* Information about GDS, etc. resource configuration */
++#define AMDGPU_INFO_GDS_CONFIG			0x13
++/* Query information about VRAM and GTT domains */
++#define AMDGPU_INFO_VRAM_GTT			0x14
++/* Query information about register in MMR address space*/
++#define AMDGPU_INFO_READ_MMR_REG		0x15
++/* Query information about device: rev id, family, etc. */
++#define AMDGPU_INFO_DEV_INFO			0x16
++/* visible vram usage */
++#define AMDGPU_INFO_VIS_VRAM_USAGE		0x17
++
++#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
++#define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
++#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
++#define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
++
++/* Input structure for the INFO ioctl */
++struct drm_amdgpu_info {
++	/* Where the return value will be stored */
++	uint64_t return_pointer;
++	/* The size of the return value. Just like "size" in "snprintf",
++	 * it limits how many bytes the kernel can write. */
++	uint32_t return_size;
++	/* The query request id. */
++	uint32_t query;
++
++	union {
++		struct {
++			uint32_t id;
++		} mode_crtc;
++
++		struct {
++			/** AMDGPU_HW_IP_* */
++			uint32_t type;
++			/**
++			 * Index of the IP if there are more IPs of the same type.
++			 * Ignored by AMDGPU_INFO_HW_IP_COUNT.
++			 */
++			uint32_t ip_instance;
++		} query_hw_ip;
++
++		struct {
++			uint32_t dword_offset;
++			uint32_t count; /* number of registers to read */
++			uint32_t instance;
++			uint32_t flags;
++		} read_mmr_reg;
++
++		struct {
++			/** AMDGPU_INFO_FW_* */
++			uint32_t fw_type;
++			/** Index of the IP if there are more IPs of the same type. */
++			uint32_t ip_instance;
++			/**
++			 * Index of the engine. Whether this is used depends
++			 * on the firmware type. (e.g. MEC, SDMA)
++			 */
++			uint32_t index;
++		} query_fw;
++	};
++};
++
++struct drm_amdgpu_info_gds {
++	/** GDS GFX partition size */
++	uint32_t gds_gfx_partition_size;
++	/** GDS compute partition size */
++	uint32_t compute_partition_size;
++	/** total GDS memory size */
++	uint32_t gds_total_size;
++	/** GWS size per GFX partition */
++	uint32_t gws_per_gfx_partition;
++	/** GSW size per compute partition */
++	uint32_t gws_per_compute_partition;
++	/** OA size per GFX partition */
++	uint32_t oa_per_gfx_partition;
++	/** OA size per compute partition */
++	uint32_t oa_per_compute_partition;
++};
++
++struct drm_amdgpu_info_vram_gtt {
++	uint64_t vram_size;
++	uint64_t vram_cpu_accessible_size;
++	uint64_t gtt_size;
++};
++
++struct drm_amdgpu_info_firmware {
++	uint32_t ver;
++	uint32_t feature;
++};
++
++struct drm_amdgpu_info_device {
++	/** PCI Device ID */
++	uint32_t device_id;
++	/** Internal chip revision: A0, A1, etc.) */
++	uint32_t chip_rev;
++	uint32_t external_rev;
++	/** Revision id in PCI Config space */
++	uint32_t pci_rev;
++	uint32_t family;
++	uint32_t num_shader_engines;
++	uint32_t num_shader_arrays_per_engine;
++	uint32_t gpu_counter_freq; /* in KHz */
++	uint64_t max_engine_clock; /* in KHz */
++	/* cu information */
++	uint32_t cu_active_number;
++	uint32_t cu_ao_mask;
++	uint32_t cu_bitmap[4][4];
++	/** Render backend pipe mask. One render backend is CB+DB. */
++	uint32_t enabled_rb_pipes_mask;
++	uint32_t num_rb_pipes;
++	uint32_t num_hw_gfx_contexts;
++	uint32_t _pad;
++	uint64_t ids_flags;
++	/** Starting virtual address for UMDs. */
++	uint64_t virtual_address_offset;
++	/** Required alignment of virtual addresses. */
++	uint32_t virtual_address_alignment;
++	/** Page table entry - fragment size */
++	uint32_t pte_fragment_size;
++	uint32_t gart_page_size;
++};
++
++struct drm_amdgpu_info_hw_ip {
++	/** Version of h/w IP */
++	uint32_t  hw_ip_version_major;
++	uint32_t  hw_ip_version_minor;
++	/** Capabilities */
++	uint64_t  capabilities_flags;
++	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
++	uint32_t  available_rings;
++};
++
++/* Those correspond to the tile index to use, this is to explicitly state
++ * the API that is implicitly defined by the tile mode array.
++ */
++#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED	8
++#define SI_TILE_MODE_COLOR_1D			13
++#define SI_TILE_MODE_COLOR_1D_SCANOUT		9
++#define SI_TILE_MODE_COLOR_2D_8BPP		14
++#define SI_TILE_MODE_COLOR_2D_16BPP		15
++#define SI_TILE_MODE_COLOR_2D_32BPP		16
++#define SI_TILE_MODE_COLOR_2D_64BPP		17
++#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP	11
++#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP	12
++#define SI_TILE_MODE_DEPTH_STENCIL_1D		4
++#define SI_TILE_MODE_DEPTH_STENCIL_2D		0
++#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA	3
++#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3
++#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2
++
++#define CIK_TILE_MODE_DEPTH_STENCIL_1D		5
++
++/*
++ * Supported GPU families
++ */
++#define AMDGPU_FAMILY_UNKNOWN			0
++#define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
++#define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
++#define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
++#define AMDGPU_FAMILY_CZ			135 /* Carrizo */
++
++#endif
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/drm/libdrm/0002-drm-add-tests-amdgpu.patch b/meta-amdfalconx86/recipes-graphics/drm/libdrm/0002-drm-add-tests-amdgpu.patch
new file mode 100644
index 00000000..85675beb
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/drm/libdrm/0002-drm-add-tests-amdgpu.patch
@@ -0,0 +1,2487 @@
+From f946a76cb79c3d49e209ff5b48c7aa73af7af0dc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 12:15:23 -0400
+Subject: [PATCH 2/3] drm: add tests/amdgpu
+
+This adds some basic unit tests for the new amdgpu driver.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ configure.ac                |  23 ++
+ tests/Makefile.am           |   6 +
+ tests/amdgpu/Makefile.am    |  24 ++
+ tests/amdgpu/amdgpu_test.c  | 241 +++++++++++++
+ tests/amdgpu/amdgpu_test.h  | 119 +++++++
+ tests/amdgpu/basic_tests.c  | 676 ++++++++++++++++++++++++++++++++++++
+ tests/amdgpu/bo_tests.c     | 151 ++++++++
+ tests/amdgpu/cs_tests.c     | 319 +++++++++++++++++
+ tests/amdgpu/uvd_messages.h | 813 ++++++++++++++++++++++++++++++++++++++++++++
+ tests/kmstest/main.c        |   1 +
+ 10 files changed, 2373 insertions(+)
+ create mode 100644 tests/amdgpu/Makefile.am
+ create mode 100644 tests/amdgpu/amdgpu_test.c
+ create mode 100644 tests/amdgpu/amdgpu_test.h
+ create mode 100644 tests/amdgpu/basic_tests.c
+ create mode 100644 tests/amdgpu/bo_tests.c
+ create mode 100644 tests/amdgpu/cs_tests.c
+ create mode 100644 tests/amdgpu/uvd_messages.h
+
+diff --git a/configure.ac b/configure.ac
+index 509f2d4..0019f73 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -351,6 +351,28 @@ fi
+ AM_CONDITIONAL(HAVE_AMDGPU, [test "x$AMDGPU" = xyes])
+ if test "x$AMDGPU" = xyes; then
+ 	AC_DEFINE(HAVE_AMDGPU, 1, [Have amdgpu support])
++
++	# Detect cunit library
++	PKG_CHECK_MODULES([CUNIT], [cunit >= 2.1], [have_cunit=yes], [have_cunit=no])
++
++	# If pkg-config does not find cunit, check it using AC_CHECK_LIB.  We
++	# do this because Debian (Ubuntu) lacks pkg-config file for cunit.
++	if test "x${have_cunit}" = "xno"; then
++		AC_CHECK_LIB([cunit], [CU_initialize_registry], [have_cunit=yes], [have_cunit=no])
++		if test "x${have_cunit}" = "xyes"; then
++			CUNIT_LIBS="-lcunit"
++			CUNIT_CFLAGS=""
++			AC_SUBST([CUNIT_LIBS])
++			AC_SUBST([CUNIT_CFLAGS])
++		fi
++	fi
++
++	AM_CONDITIONAL(HAVE_CUNIT, [test "x$have_cunit" != "xno"])
++	AC_DEFINE(HAVE_CUNIT, [test "x$have_cunit" != "xno"], [Enable CUNIT Have amdgpu support])
++
++	if test "x$have_cunit" = "xno"; then
++		AC_MSG_WARN([Could not find cunit library. Disabling amdgpu tests])
++	fi
+ fi
+ 
+ AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes])
+@@ -467,6 +489,7 @@ AC_CONFIG_FILES([
+ 	tests/kmstest/Makefile
+ 	tests/proptest/Makefile
+ 	tests/radeon/Makefile
++	tests/amdgpu/Makefile
+ 	tests/vbltest/Makefile
+ 	tests/exynos/Makefile
+ 	tests/tegra/Makefile
+diff --git a/tests/Makefile.am b/tests/Makefile.am
+index 069285f..a980b3d 100644
+--- a/tests/Makefile.am
++++ b/tests/Makefile.am
+@@ -8,6 +8,12 @@ if HAVE_RADEON
+ SUBDIRS += radeon
+ endif
+ 
++if HAVE_AMDGPU
++if HAVE_CUNIT
++SUBDIRS += amdgpu
++endif
++endif
++
+ if HAVE_EXYNOS
+ SUBDIRS += exynos
+ endif
+diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
+new file mode 100644
+index 0000000..ba7339d
+--- /dev/null
++++ b/tests/amdgpu/Makefile.am
+@@ -0,0 +1,24 @@
++AM_CFLAGS = \
++	-I $(top_srcdir)/include/drm \
++	-I $(top_srcdir)/amdgpu \
++	-I $(top_srcdir)
++
++LDADD = $(top_builddir)/libdrm.la \
++	$(top_builddir)/amdgpu/libdrm_amdgpu.la
++
++if HAVE_INSTALL_TESTS
++bin_PROGRAMS = \
++	amdgpu_test
++else
++noinst_PROGRAMS = \
++	amdgpu_test
++endif
++
++amdgpu_test_CPPFLAGS = $(CUNIT_CFLAGS)
++amdgpu_test_LDFLAGS  = $(CUNIT_LIBS)
++
++amdgpu_test_SOURCES = \
++	amdgpu_test.c \
++	basic_tests.c \
++	bo_tests.c \
++	cs_tests.c
+diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
+new file mode 100644
+index 0000000..fc14b70
+--- /dev/null
++++ b/tests/amdgpu/amdgpu_test.c
+@@ -0,0 +1,241 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++#include <string.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <unistd.h>
++#include <string.h>
++#include <ctype.h>
++#include <fcntl.h>
++#include <errno.h>
++#include <signal.h>
++#include <time.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <sys/ioctl.h>
++#include <sys/time.h>
++#include <stdarg.h>
++#include <stdint.h>
++
++#include "drm.h"
++#include "xf86drmMode.h"
++#include "xf86drm.h"
++
++#include "CUnit/Basic.h"
++
++#include "amdgpu_test.h"
++
++/**
++ *  Open handles for amdgpu devices
++ *
++ */
++int drm_amdgpu[MAX_CARDS_SUPPORTED];
++
++/** The table of all known test suites to run */
++CU_SuiteInfo suites[] = {
++	{ "Basic Tests", suite_basic_tests_init,
++	  suite_basic_tests_clean, basic_tests },
++	{ "BO Tests", suite_bo_tests_init,
++	  suite_bo_tests_clean, bo_tests },
++	{ "CS Tests", suite_cs_tests_init,
++	  suite_cs_tests_clean, cs_tests },
++	CU_SUITE_INFO_NULL,
++};
++
++
++/** Display information about all  suites and their tests */
++static void display_test_suites(void)
++{
++	int iSuite;
++	int iTest;
++
++	printf("Suites\n");
++
++	for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) {
++		printf("Suite id = %d: Name '%s'\n",
++				iSuite + 1, suites[iSuite].pName);
++
++		for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL;
++			iTest++) {
++			printf("	Test id %d: Name: '%s'\n", iTest + 1,
++					suites[iSuite].pTests[iTest].pName);
++		}
++	}
++}
++
++
++/** Help string for command line parameters */
++static const char usage[] = "Usage: %s [-hl] [<-s <suite id>> [-t <test id>]]\n"
++				"where:\n"
++				"       l - Display all suites and their tests\n"
++				"       h - Display this help\n";
++/** Specified options strings for getopt */
++static const char options[]   = "hls:t:";
++
++/* The main() function for setting up and running the tests.
++ * Returns a CUE_SUCCESS on successful running, another
++ * CUnit error code on failure.
++ */
++int main(int argc, char **argv)
++{
++	int c;			/* Character received from getopt */
++	int i = 0;
++	int suite_id = -1;	/* By default run everything */
++	int test_id  = -1;	/* By default run all tests in the suite */
++	CU_pSuite pSuite = NULL;
++	CU_pTest  pTest  = NULL;
++
++	int aval = drmAvailable();
++
++	if (aval == 0) {
++		fprintf(stderr, "DRM driver is not available\n");
++		exit(EXIT_FAILURE);
++	}
++
++
++	for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
++		drm_amdgpu[i] = 0;
++
++
++	/* Parse command line string */
++	opterr = 0;		/* Do not print error messages from getopt */
++	while ((c = getopt(argc, argv, options)) != -1) {
++		switch (c) {
++		case 'l':
++			display_test_suites();
++			exit(EXIT_SUCCESS);
++		case 's':
++			suite_id = atoi(optarg);
++			break;
++		case 't':
++			test_id = atoi(optarg);
++			break;
++		case '?':
++		case 'h':
++			fprintf(stderr, usage, argv[0]);
++			exit(EXIT_SUCCESS);
++		default:
++			fprintf(stderr, usage, argv[0]);
++			exit(EXIT_FAILURE);
++		}
++	}
++
++	/* Try to open all possible radeon connections
++	 * Right now: Open only the 0.
++	 */
++	printf("Try to open the card 0..\n");
++	drm_amdgpu[0] = open("/dev/dri/card0", O_RDWR | O_CLOEXEC);
++
++	if (drm_amdgpu[0] == 1) {
++		perror("Cannot open /dev/dri/card0\n");
++		exit(EXIT_FAILURE);
++	}
++
++	/** Display version of DRM driver */
++	drmVersionPtr retval;
++	drm_version_t *version = drmMalloc(sizeof(*version));
++
++	version->name_len    = 0;
++	version->name        = NULL;
++	version->date_len    = 0;
++	version->date        = NULL;
++	version->desc_len    = 0;
++	version->desc        = NULL;
++
++	if (drmIoctl(drm_amdgpu[0], DRM_IOCTL_VERSION, version)) {
++		perror("Could not get DRM driver version\n");
++		drmFree(version);
++		exit(EXIT_FAILURE);
++	}
++
++	if (version->name_len)
++		version->name    = drmMalloc(version->name_len + 1);
++	if (version->date_len)
++		version->date    = drmMalloc(version->date_len + 1);
++	if (version->desc_len)
++		version->desc    = drmMalloc(version->desc_len + 1);
++
++	if (drmIoctl(drm_amdgpu[0], DRM_IOCTL_VERSION, version)) {
++		perror("Could not get information about DRM driver");
++		drmFree(version);
++		exit(EXIT_FAILURE);
++	}
++
++	/* The results might not be null-terminated strings. Add zero */
++	if (version->name_len)
++		version->name[version->name_len] = '\0';
++	if (version->date_len)
++		version->date[version->date_len] = '\0';
++	if (version->desc_len)
++		version->desc[version->desc_len] = '\0';
++
++	printf("DRM Driver: Name: [%s] : Date [%s] : Description [%s]\n",
++			version->name, version->date, version->desc);
++
++	drmFree(version);
++
++	/* Initialize test suites to run */
++
++	/* initialize the CUnit test registry */
++	if (CUE_SUCCESS != CU_initialize_registry())
++		return CU_get_error();
++
++	/* Register suites. */
++	if (CU_register_suites(suites) != CUE_SUCCESS) {
++		fprintf(stderr, "suite registration failed - %s\n",
++				CU_get_error_msg());
++		exit(EXIT_FAILURE);
++	}
++
++	/* Run tests using the CUnit Basic interface */
++	CU_basic_set_mode(CU_BRM_VERBOSE);
++
++	if (suite_id != -1) {	/* If user specify particular suite? */
++		pSuite = CU_get_suite_by_index((unsigned int) suite_id,
++						CU_get_registry());
++
++		if (pSuite) {
++			if (test_id != -1) {   /* If user specify test id */
++				pTest = CU_get_test_by_index(
++						(unsigned int) test_id,
++						pSuite);
++				if (pTest)
++					CU_basic_run_test(pSuite, pTest);
++				else {
++					fprintf(stderr, "Invalid test id: %d\n",
++								test_id);
++					exit(EXIT_FAILURE);
++				}
++			} else
++				CU_basic_run_suite(pSuite);
++		} else {
++			fprintf(stderr, "Invalid suite id : %d\n",
++					suite_id);
++			exit(EXIT_FAILURE);
++		}
++	} else
++		CU_basic_run_tests();
++
++	CU_cleanup_registry();
++	return CU_get_error();
++}
+diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
+new file mode 100644
+index 0000000..508e561
+--- /dev/null
++++ b/tests/amdgpu/amdgpu_test.h
+@@ -0,0 +1,119 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++
++#ifndef _amdgpu_test_h_
++#define _amdgpu_test_h_
++
++#include "amdgpu.h"
++
++/**
++ * Define max. number of card in system which we are able to handle
++ */
++#define MAX_CARDS_SUPPORTED     4
++
++/* Forward reference for array to keep "drm" handles */
++extern int drm_amdgpu[MAX_CARDS_SUPPORTED];
++
++/*************************  Basic test suite ********************************/
++
++/*
++ * Define basic test suite to serve as the starting point for future testing
++*/
++
++/**
++ * Initialize basic test suite
++ */
++int suite_basic_tests_init();
++
++/**
++ * Deinitialize basic test suite
++ */
++int suite_basic_tests_clean();
++
++/**
++ * Tests in basic test suite
++ */
++extern CU_TestInfo basic_tests[];
++
++/**
++ * Initialize bo test suite
++ */
++int suite_bo_tests_init();
++
++/**
++ * Deinitialize bo test suite
++ */
++int suite_bo_tests_clean();
++
++/**
++ * Tests in bo test suite
++ */
++extern CU_TestInfo bo_tests[];
++
++/**
++ * Initialize cs test suite
++ */
++int suite_cs_tests_init();
++
++/**
++ * Deinitialize cs test suite
++ */
++int suite_cs_tests_clean();
++
++/**
++ * Tests in cs test suite
++ */
++extern CU_TestInfo cs_tests[];
++
++/**
++ * Helper functions
++ */
++static inline amdgpu_bo_handle gpu_mem_alloc(
++					amdgpu_device_handle device_handle,
++					uint64_t size,
++					uint64_t alignment,
++					uint32_t type,
++					uint64_t flags,
++					uint64_t *vmc_addr)
++{
++	struct amdgpu_bo_alloc_request req = {0};
++	struct amdgpu_bo_alloc_result res = {0};
++	int r;
++
++	CU_ASSERT_NOT_EQUAL(vmc_addr, NULL);
++
++	req.alloc_size = size;
++	req.phys_alignment = alignment;
++	req.preferred_heap = type;
++	req.flags = flags;
++
++	r = amdgpu_bo_alloc(device_handle, &req, &res);
++	CU_ASSERT_EQUAL(r, 0);
++
++	CU_ASSERT_NOT_EQUAL(res.virtual_mc_base_address, 0);
++	CU_ASSERT_NOT_EQUAL(res.buf_handle, NULL);
++	*vmc_addr = res.virtual_mc_base_address;
++	return res.buf_handle;
++}
++
++#endif  /* #ifdef _amdgpu_test_h_ */
+diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
+new file mode 100644
+index 0000000..c53f6a0
+--- /dev/null
++++ b/tests/amdgpu/basic_tests.c
+@@ -0,0 +1,676 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++#include <stdio.h>
++#include <stdlib.h>
++#include <unistd.h>
++
++#include "CUnit/Basic.h"
++
++#include "amdgpu_test.h"
++#include "amdgpu_drm.h"
++
++static  amdgpu_device_handle device_handle;
++static  uint32_t  major_version;
++static  uint32_t  minor_version;
++
++static void amdgpu_query_info_test(void);
++static void amdgpu_memory_alloc(void);
++static void amdgpu_command_submission_gfx(void);
++static void amdgpu_command_submission_compute(void);
++static void amdgpu_command_submission_sdma(void);
++static void amdgpu_userptr_test(void);
++
++CU_TestInfo basic_tests[] = {
++	{ "Query Info Test",  amdgpu_query_info_test },
++	{ "Memory alloc Test",  amdgpu_memory_alloc },
++	{ "Userptr Test",  amdgpu_userptr_test },
++	{ "Command submission Test (GFX)",  amdgpu_command_submission_gfx },
++	{ "Command submission Test (Compute)", amdgpu_command_submission_compute },
++	{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
++	CU_TEST_INFO_NULL,
++};
++#define BUFFER_SIZE (8 * 1024)
++#define SDMA_PKT_HEADER_op_offset 0
++#define SDMA_PKT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_HEADER_op_shift  0
++#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift)
++#define SDMA_OPCODE_CONSTANT_FILL  11
++#       define SDMA_CONSTANT_FILL_EXTRA_SIZE(x)           ((x) << 14)
++	/* 0 = byte fill
++	 * 2 = DW fill
++	 */
++#define SDMA_PACKET(op, sub_op, e)	((((e) & 0xFFFF) << 16) |	\
++					(((sub_op) & 0xFF) << 8) |	\
++					(((op) & 0xFF) << 0))
++#define	SDMA_OPCODE_WRITE				  2
++#       define SDMA_WRITE_SUB_OPCODE_LINEAR               0
++#       define SDMA_WRTIE_SUB_OPCODE_TILED                1
++
++#define	SDMA_OPCODE_COPY				  1
++#       define SDMA_COPY_SUB_OPCODE_LINEAR                0
++
++int suite_basic_tests_init(void)
++{
++	int r;
++
++	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
++				   &minor_version, &device_handle);
++
++	if (r == 0)
++		return CUE_SUCCESS;
++	else
++		return CUE_SINIT_FAILED;
++}
++
++int suite_basic_tests_clean(void)
++{
++	int r = amdgpu_device_deinitialize(device_handle);
++
++	if (r == 0)
++		return CUE_SUCCESS;
++	else
++		return CUE_SCLEAN_FAILED;
++}
++
++static void amdgpu_query_info_test(void)
++{
++	struct amdgpu_gpu_info gpu_info = {0};
++	uint32_t version, feature;
++	int r;
++
++	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0,
++					  0, &version, &feature);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_memory_alloc(void)
++{
++	amdgpu_bo_handle bo;
++	uint64_t bo_mc;
++	int r;
++
++	/* Test visible VRAM */
++	bo = gpu_mem_alloc(device_handle,
++			4096, 4096,
++			AMDGPU_GEM_DOMAIN_VRAM,
++			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
++			&bo_mc);
++
++	r = amdgpu_bo_free(bo);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* Test invisible VRAM */
++	bo = gpu_mem_alloc(device_handle,
++			4096, 4096,
++			AMDGPU_GEM_DOMAIN_VRAM,
++			AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
++			&bo_mc);
++
++	r = amdgpu_bo_free(bo);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* Test GART Cacheable */
++	bo = gpu_mem_alloc(device_handle,
++			4096, 4096,
++			AMDGPU_GEM_DOMAIN_GTT,
++			0,
++			&bo_mc);
++
++	r = amdgpu_bo_free(bo);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* Test GART USWC */
++	bo = gpu_mem_alloc(device_handle,
++			4096, 4096,
++			AMDGPU_GEM_DOMAIN_GTT,
++			AMDGPU_GEM_CREATE_CPU_GTT_WC,
++			&bo_mc);
++
++	r = amdgpu_bo_free(bo);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_command_submission_gfx(void)
++{
++	amdgpu_context_handle context_handle;
++	struct amdgpu_cs_ib_alloc_result ib_result = {0};
++	struct amdgpu_cs_ib_alloc_result ib_result_ce = {0};
++	struct amdgpu_cs_request ibs_request = {0};
++	struct amdgpu_cs_ib_info ib_info[2];
++	struct amdgpu_cs_query_fence fence_status = {0};
++	uint32_t *ptr;
++	uint32_t expired;
++	int r;
++
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_cs_alloc_ib(device_handle, context_handle,
++			       amdgpu_cs_ib_size_4K, &ib_result);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_cs_alloc_ib(device_handle, context_handle,
++			       amdgpu_cs_ib_size_4K, &ib_result_ce);
++	CU_ASSERT_EQUAL(r, 0);
++
++	memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info));
++
++	/* IT_SET_CE_DE_COUNTERS */
++	ptr = ib_result_ce.cpu;
++	ptr[0] = 0xc0008900;
++	ptr[1] = 0;
++	ptr[2] = 0xc0008400;
++	ptr[3] = 1;
++	ib_info[0].ib_handle = ib_result_ce.handle;
++	ib_info[0].size = 4;
++	ib_info[0].flags = AMDGPU_CS_GFX_IB_CE;
++
++	/* IT_WAIT_ON_CE_COUNTER */
++	ptr = ib_result.cpu;
++	ptr[0] = 0xc0008600;
++	ptr[1] = 0x00000001;
++	ib_info[1].ib_handle = ib_result.handle;
++	ib_info[1].size = 2;
++
++	ibs_request.ip_type = AMDGPU_HW_IP_GFX;
++	ibs_request.number_of_ibs = 2;
++	ibs_request.ibs = ib_info;
++
++	r = amdgpu_cs_submit(device_handle, context_handle, 0,
++			     &ibs_request, 1, &fence_status.fence);
++	CU_ASSERT_EQUAL(r, 0);
++
++	fence_status.context = context_handle;
++	fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
++	fence_status.ip_type = AMDGPU_HW_IP_GFX;
++
++	r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_command_submission_compute(void)
++{
++	amdgpu_context_handle context_handle;
++	struct amdgpu_cs_ib_alloc_result ib_result;
++	struct amdgpu_cs_request ibs_request;
++	struct amdgpu_cs_ib_info ib_info;
++	struct amdgpu_cs_query_fence fence_status;
++	uint32_t *ptr;
++	uint32_t expired;
++	int i, r, instance;
++
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	for (instance = 0; instance < 8; instance++) {
++		memset(&ib_result, 0, sizeof(struct amdgpu_cs_ib_alloc_result));
++		r = amdgpu_cs_alloc_ib(device_handle, context_handle,
++				       amdgpu_cs_ib_size_4K, &ib_result);
++		CU_ASSERT_EQUAL(r, 0);
++
++		ptr = ib_result.cpu;
++		for (i = 0; i < 16; ++i)
++			ptr[i] = 0xffff1000;
++
++		memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
++		ib_info.ib_handle = ib_result.handle;
++		ib_info.size = 16;
++
++		memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
++		ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE;
++		ibs_request.ring = instance;
++		ibs_request.number_of_ibs = 1;
++		ibs_request.ibs = &ib_info;
++
++		memset(&fence_status, 0, sizeof(struct amdgpu_cs_query_fence));
++		r = amdgpu_cs_submit(device_handle, context_handle, 0,
++				     &ibs_request, 1, &fence_status.fence);
++		CU_ASSERT_EQUAL(r, 0);
++
++		fence_status.context = context_handle;
++		fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
++		fence_status.ip_type = AMDGPU_HW_IP_COMPUTE;
++		fence_status.ring = instance;
++
++		r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired);
++		CU_ASSERT_EQUAL(r, 0);
++	}
++
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++/*
++ * caller need create/release:
++ * pm4_src, resources, ib_info, and ibs_request
++ * submit command stream described in ibs_request and wait for this IB accomplished
++ */
++static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle,
++				 int instance, int pm4_dw, uint32_t *pm4_src,
++				 int res_cnt, amdgpu_bo_handle *resources,
++				 struct amdgpu_cs_ib_info *ib_info,
++				 struct amdgpu_cs_request *ibs_request)
++{
++	int r, i, j;
++	uint32_t expired;
++	uint32_t *ring_ptr;
++	struct amdgpu_cs_ib_alloc_result ib_result = {0};
++	struct amdgpu_cs_query_fence fence_status = {0};
++
++	/* prepare CS */
++	CU_ASSERT_NOT_EQUAL(pm4_src, NULL);
++	CU_ASSERT_NOT_EQUAL(resources, NULL);
++	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
++	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
++	CU_ASSERT_TRUE(pm4_dw <= 1024);
++
++	/* allocate IB */
++	r = amdgpu_cs_alloc_ib(device_handle, context_handle,
++			   amdgpu_cs_ib_size_4K, &ib_result);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* copy PM4 packet to ring from caller */
++	ring_ptr = ib_result.cpu;
++	memcpy(ring_ptr, pm4_src, pm4_dw * sizeof(*pm4_src));
++
++	ib_info->ib_handle = ib_result.handle;
++	ib_info->size = pm4_dw;
++
++	ibs_request->ip_type = AMDGPU_HW_IP_DMA;
++	ibs_request->ring = instance;
++	ibs_request->number_of_ibs = 1;
++	ibs_request->ibs = ib_info;
++	ibs_request->number_of_resources = res_cnt;
++	ibs_request->resources = resources;
++
++
++	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
++
++	/* submit CS */
++	r = amdgpu_cs_submit(device_handle, context_handle, 0,
++			 ibs_request, 1, &fence_status.fence);
++	CU_ASSERT_EQUAL(r, 0);
++
++	fence_status.ip_type = AMDGPU_HW_IP_DMA;
++	fence_status.ring = ibs_request->ring;
++	fence_status.context = context_handle;
++	fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
++
++	/* wait for IB accomplished */
++	r = amdgpu_cs_query_fence_status(device_handle, &fence_status,
++					&expired);
++	CU_ASSERT_EQUAL(r, 0);
++	CU_ASSERT_EQUAL(expired, true);
++}
++
++static void amdgpu_command_submission_sdma_write_linear(void)
++{
++	const int sdma_write_length = 128;
++	const int pm4_dw = 256;
++	amdgpu_context_handle context_handle;
++	amdgpu_bo_handle bo;
++	amdgpu_bo_handle *resources;
++	uint32_t *pm4;
++	struct amdgpu_cs_ib_info *ib_info;
++	struct amdgpu_cs_request *ibs_request;
++	uint64_t bo_mc;
++	volatile uint32_t *bo_cpu;
++	int i, j, r, loop;
++	uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC,
++				AMDGPU_GEM_CREATE_CPU_GTT_WC};
++
++	pm4 = malloc(pm4_dw * 4);
++	CU_ASSERT_NOT_EQUAL(pm4, NULL);
++
++	ib_info = malloc(sizeof(*ib_info));
++	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
++	memset(ib_info, 0, sizeof(*ib_info));
++
++	ibs_request = malloc(sizeof(*ibs_request));
++	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
++	memset(ibs_request, 0, sizeof(*ibs_request));
++
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* prepare resource */
++	resources = malloc(sizeof(amdgpu_bo_handle));
++	CU_ASSERT_NOT_EQUAL(resources, NULL);
++
++	loop = 0;
++	while(loop < 3) {
++		/* allocate UC bo for sDMA use */
++		bo = gpu_mem_alloc(device_handle,
++				sdma_write_length * sizeof(uint32_t),
++				4096, AMDGPU_GEM_DOMAIN_GTT,
++				gtt_flags[loop], &bo_mc);
++
++		CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo, (void **)&bo_cpu), 0);
++		CU_ASSERT_NOT_EQUAL(bo_cpu, NULL);
++
++		/* clear bo */
++		memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t));
++
++
++		resources[0] = bo;
++
++		/* fullfill PM4: test DMA write-linear */
++		i = j = 0;
++		pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
++				SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
++		pm4[i++] = 0xffffffff & bo_mc;
++		pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
++		pm4[i++] = sdma_write_length;
++		while(j++ < sdma_write_length)
++			pm4[i++] = 0xdeadbeaf;
++
++		amdgpu_sdma_test_exec_cs(context_handle, 0,
++					i, pm4,
++					1, resources,
++					ib_info, ibs_request);
++
++		/* verify if SDMA test result meets with expected */
++		i = 0;
++		while(i < sdma_write_length) {
++			CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
++		}
++		amdgpu_bo_free(bo);
++		loop++;
++	}
++	/* clean resources */
++	free(resources);
++	free(ibs_request);
++	free(ib_info);
++	free(pm4);
++
++	/* end of test */
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_command_submission_sdma_const_fill(void)
++{
++	const int sdma_write_length = 1024 * 1024;
++	const int pm4_dw = 256;
++	amdgpu_context_handle context_handle;
++	amdgpu_bo_handle bo;
++	amdgpu_bo_handle *resources;
++	uint32_t *pm4;
++	struct amdgpu_cs_ib_info *ib_info;
++	struct amdgpu_cs_request *ibs_request;
++	uint64_t bo_mc;
++	volatile uint32_t *bo_cpu;
++	int i, j, r, loop;
++	uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC,
++				AMDGPU_GEM_CREATE_CPU_GTT_WC};
++
++	pm4 = malloc(pm4_dw * 4);
++	CU_ASSERT_NOT_EQUAL(pm4, NULL);
++
++	ib_info = malloc(sizeof(*ib_info));
++	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
++	memset(ib_info, 0, sizeof(*ib_info));
++
++	ibs_request = malloc(sizeof(*ibs_request));
++	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
++	memset(ibs_request, 0, sizeof(*ibs_request));
++
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* prepare resource */
++	resources = malloc(sizeof(amdgpu_bo_handle));
++	CU_ASSERT_NOT_EQUAL(resources, NULL);
++
++	loop = 0;
++	while(loop < 3) {
++		/* allocate UC bo for sDMA use */
++		bo = gpu_mem_alloc(device_handle,
++				sdma_write_length, 4096,
++				AMDGPU_GEM_DOMAIN_GTT,
++				gtt_flags[loop], &bo_mc);
++
++		CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo, (void **)&bo_cpu), 0);
++		CU_ASSERT_NOT_EQUAL(bo_cpu, NULL);
++
++		/* clear bo */
++		memset((void*)bo_cpu, 0, sdma_write_length);
++
++		resources[0] = bo;
++
++		/* fullfill PM4: test DMA const fill */
++		i = j = 0;
++		pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
++				   SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
++		pm4[i++] = 0xffffffff & bo_mc;
++		pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
++		pm4[i++] = 0xdeadbeaf;
++		pm4[i++] = sdma_write_length;
++
++		amdgpu_sdma_test_exec_cs(context_handle, 0,
++					i, pm4,
++					1, resources,
++					ib_info, ibs_request);
++
++		/* verify if SDMA test result meets with expected */
++		i = 0;
++		while(i < (sdma_write_length / 4)) {
++			CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
++		}
++		amdgpu_bo_free(bo);
++		loop++;
++	}
++	/* clean resources */
++	free(resources);
++	free(ibs_request);
++	free(ib_info);
++	free(pm4);
++
++	/* end of test */
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_command_submission_sdma_copy_linear(void)
++{
++	const int sdma_write_length = 1024;
++	const int pm4_dw = 256;
++	amdgpu_context_handle context_handle;
++	amdgpu_bo_handle bo1, bo2;
++	amdgpu_bo_handle *resources;
++	uint32_t *pm4;
++	struct amdgpu_cs_ib_info *ib_info;
++	struct amdgpu_cs_request *ibs_request;
++	uint64_t bo1_mc, bo2_mc;
++	volatile unsigned char *bo1_cpu, *bo2_cpu;
++	int i, j, r, loop1, loop2;
++	uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC,
++				AMDGPU_GEM_CREATE_CPU_GTT_WC};
++
++	pm4 = malloc(pm4_dw * 4);
++	CU_ASSERT_NOT_EQUAL(pm4, NULL);
++
++	ib_info = malloc(sizeof(*ib_info));
++	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
++	memset(ib_info, 0, sizeof(*ib_info));
++
++	ibs_request = malloc(sizeof(*ibs_request));
++	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
++	memset(ibs_request, 0, sizeof(*ibs_request));
++
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* prepare resource */
++	resources = malloc(2 * sizeof(amdgpu_bo_handle));
++	CU_ASSERT_NOT_EQUAL(resources, NULL);
++
++	loop1 = loop2 = 0;
++	/* run 9 circle to test all mapping combination */
++	while(loop1 < 3) {
++		while(loop2 < 3) {
++			/* allocate UC bo1for sDMA use */
++			bo1 = gpu_mem_alloc(device_handle,
++					sdma_write_length, 4096,
++					AMDGPU_GEM_DOMAIN_GTT,
++					gtt_flags[loop1], &bo1_mc);
++
++			CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo1, (void **)&bo1_cpu), 0);
++			CU_ASSERT_NOT_EQUAL(bo1_cpu, NULL);
++
++			/* set bo1 */
++			memset((void*)bo1_cpu, 0xaa, sdma_write_length);
++
++			/* allocate UC bo2 for sDMA use */
++			bo2 = gpu_mem_alloc(device_handle,
++					sdma_write_length, 4096,
++					AMDGPU_GEM_DOMAIN_GTT,
++					gtt_flags[loop2], &bo2_mc);
++
++			CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo2, (void **)&bo2_cpu), 0);
++			CU_ASSERT_NOT_EQUAL(bo2_cpu, NULL);
++
++			/* clear bo2 */
++			memset((void*)bo2_cpu, 0, sdma_write_length);
++
++			resources[0] = bo1;
++			resources[1] = bo2;
++
++			/* fullfill PM4: test DMA copy linear */
++			i = j = 0;
++			pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
++			pm4[i++] = sdma_write_length;
++			pm4[i++] = 0;
++			pm4[i++] = 0xffffffff & bo1_mc;
++			pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
++			pm4[i++] = 0xffffffff & bo2_mc;
++			pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
++
++
++			amdgpu_sdma_test_exec_cs(context_handle, 0,
++						i, pm4,
++						2, resources,
++						ib_info, ibs_request);
++
++			/* verify if SDMA test result meets with expected */
++			i = 0;
++			while(i < sdma_write_length) {
++				CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa);
++			}
++			amdgpu_bo_free(bo1);
++			amdgpu_bo_free(bo2);
++			loop2++;
++		}
++		loop1++;
++	}
++	/* clean resources */
++	free(resources);
++	free(ibs_request);
++	free(ib_info);
++	free(pm4);
++
++	/* end of test */
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_command_submission_sdma(void)
++{
++	amdgpu_command_submission_sdma_write_linear();
++	amdgpu_command_submission_sdma_const_fill();
++	amdgpu_command_submission_sdma_copy_linear();
++}
++
++static void amdgpu_userptr_test(void)
++{
++	int i, r, j;
++	uint32_t *pm4 = NULL;
++	uint64_t bo_mc;
++	void *ptr = NULL;
++	int pm4_dw = 256;
++	int sdma_write_length = 4;
++	amdgpu_bo_handle handle;
++	amdgpu_context_handle context_handle;
++	struct amdgpu_cs_ib_info *ib_info;
++	struct amdgpu_cs_request *ibs_request;
++	struct amdgpu_bo_alloc_result res;
++
++	memset(&res, 0, sizeof(res));
++
++	pm4 = malloc(pm4_dw * sizeof(*pm4));
++	CU_ASSERT_NOT_EQUAL(pm4, NULL);
++
++	ib_info = malloc(sizeof(*ib_info));
++	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
++
++	memset(ib_info, 0, sizeof(*ib_info));
++	ibs_request = malloc(sizeof(*ibs_request));
++	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
++
++	memset(ibs_request, 0, sizeof(*ibs_request));
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	ptr = memalign(BUFFER_SIZE);
++	CU_ASSERT_NOT_EQUAL(ptr, NULL);
++
++	r = amdgpu_create_bo_from_user_mem(device_handle,
++					   ptr, BUFFER_SIZE, &res);
++	CU_ASSERT_EQUAL(r, 0);
++	bo_mc = res.virtual_mc_base_address;
++	handle = res.buf_handle;
++
++	j = i = 0;
++	pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
++			       SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
++	pm4[i++] = 0xffffffff & bo_mc;
++	pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
++	pm4[i++] = sdma_write_length;
++
++	while (j++ < sdma_write_length)
++		pm4[i++] = 0xdeadbeaf;
++
++	amdgpu_sdma_test_exec_cs(context_handle, 0,
++				 i, pm4,
++				 1, &handle,
++				 ib_info, ibs_request);
++	i = 0;
++	while (i < sdma_write_length) {
++		CU_ASSERT_EQUAL(((int*)ptr)[i++], 0xdeadbeaf);
++	}
++	free(ibs_request);
++	free(ib_info);
++	free(pm4);
++	r = amdgpu_bo_free(res.buf_handle);
++	CU_ASSERT_EQUAL(r, 0);
++	free(ptr);
++
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
+diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
+new file mode 100644
+index 0000000..73701b7
+--- /dev/null
++++ b/tests/amdgpu/bo_tests.c
+@@ -0,0 +1,151 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++#include <stdio.h>
++
++#include "CUnit/Basic.h"
++
++#include "amdgpu_test.h"
++#include "amdgpu_drm.h"
++
++#define BUFFER_SIZE (4*1024)
++#define BUFFER_ALIGN (4*1024)
++
++static amdgpu_device_handle device_handle;
++static uint32_t major_version;
++static uint32_t minor_version;
++
++static amdgpu_bo_handle buffer_handle;
++static uint64_t virtual_mc_base_address;
++
++static void amdgpu_bo_export_import(void);
++static void amdgpu_bo_metadata(void);
++static void amdgpu_bo_map_unmap(void);
++
++CU_TestInfo bo_tests[] = {
++	{ "Export/Import",  amdgpu_bo_export_import },
++#if 0
++	{ "Metadata",  amdgpu_bo_metadata },
++#endif
++	{ "CPU map/unmap",  amdgpu_bo_map_unmap },
++	CU_TEST_INFO_NULL,
++};
++
++int suite_bo_tests_init(void)
++{
++	struct amdgpu_bo_alloc_request req = {0};
++	struct amdgpu_bo_alloc_result res = {0};
++	int r;
++
++	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
++				  &minor_version, &device_handle);
++	if (r)
++		return CUE_SINIT_FAILED;
++
++	req.alloc_size = BUFFER_SIZE;
++	req.phys_alignment = BUFFER_ALIGN;
++	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
++
++	r = amdgpu_bo_alloc(device_handle, &req, &res);
++	if (r)
++		return CUE_SINIT_FAILED;
++
++	buffer_handle = res.buf_handle;
++	virtual_mc_base_address = res.virtual_mc_base_address;
++
++	return CUE_SUCCESS;
++}
++
++int suite_bo_tests_clean(void)
++{
++	int r;
++
++	r = amdgpu_bo_free(buffer_handle);
++	if (r)
++		return CUE_SCLEAN_FAILED;
++
++	r = amdgpu_device_deinitialize(device_handle);
++	if (r)
++		return CUE_SCLEAN_FAILED;
++
++	return CUE_SUCCESS;
++}
++
++static void amdgpu_bo_export_import_do_type(enum amdgpu_bo_handle_type type)
++{
++	struct amdgpu_bo_import_result res = {0};
++	uint32_t shared_handle;
++	int r;
++
++	r = amdgpu_bo_export(buffer_handle, type, &shared_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_import(device_handle, type, shared_handle, &res);
++	CU_ASSERT_EQUAL(r, 0);
++
++	CU_ASSERT_EQUAL(res.buf_handle, buffer_handle);
++	CU_ASSERT_EQUAL(res.alloc_size, BUFFER_SIZE);
++
++	r = amdgpu_bo_free(res.buf_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_bo_export_import(void)
++{
++	amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_gem_flink_name);
++	amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_dma_buf_fd);
++}
++
++static void amdgpu_bo_metadata(void)
++{
++	struct amdgpu_bo_metadata meta = {0};
++	struct amdgpu_bo_info info = {0};
++	int r;
++
++	meta.size_metadata = 1;
++	meta.umd_metadata[0] = 0xdeadbeef;
++
++	r = amdgpu_bo_set_metadata(buffer_handle, &meta);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_query_info(buffer_handle, &info);
++	CU_ASSERT_EQUAL(r, 0);
++
++	CU_ASSERT_EQUAL(info.metadata.size_metadata, 1);
++	CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef);
++}
++
++static void amdgpu_bo_map_unmap(void)
++{
++	uint32_t *ptr;
++	int i, r;
++
++	r = amdgpu_bo_cpu_map(buffer_handle, (void **)&ptr);
++	CU_ASSERT_EQUAL(r, 0);
++	CU_ASSERT_NOT_EQUAL(ptr, NULL);
++
++	for (i = 0; i < (BUFFER_SIZE / 4); ++i)
++		ptr[i] = 0xdeadbeef;
++
++	r = amdgpu_bo_cpu_unmap(buffer_handle);
++	CU_ASSERT_EQUAL(r, 0);
++}
+diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
+new file mode 100644
+index 0000000..f30d923
+--- /dev/null
++++ b/tests/amdgpu/cs_tests.c
+@@ -0,0 +1,319 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++*/
++#include <stdio.h>
++
++#include "CUnit/Basic.h"
++
++#include "amdgpu/util_math.h"
++
++#include "amdgpu_test.h"
++#include "uvd_messages.h"
++#include "amdgpu_drm.h"
++#include "amdgpu_internal.h"
++
++#define IB_SIZE		amdgpu_cs_ib_size_4K
++#define MAX_RESOURCES	16
++
++static amdgpu_device_handle device_handle;
++static uint32_t major_version;
++static uint32_t minor_version;
++static uint32_t family_id;
++
++static amdgpu_context_handle context_handle;
++static amdgpu_ib_handle ib_handle;
++uint32_t *ib_cpu;
++
++static amdgpu_bo_handle resources[MAX_RESOURCES];
++static unsigned num_resources;
++
++static void amdgpu_cs_uvd_create(void);
++static void amdgpu_cs_uvd_decode(void);
++static void amdgpu_cs_uvd_destroy(void);
++
++CU_TestInfo cs_tests[] = {
++	{ "UVD create",  amdgpu_cs_uvd_create },
++	{ "UVD decode",  amdgpu_cs_uvd_decode },
++	{ "UVD destroy",  amdgpu_cs_uvd_destroy },
++	CU_TEST_INFO_NULL,
++};
++
++int suite_cs_tests_init(void)
++{
++	struct amdgpu_cs_ib_alloc_result ib_result = {0};
++	int r;
++
++	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
++				     &minor_version, &device_handle);
++	if (r)
++		return CUE_SINIT_FAILED;
++
++	family_id = device_handle->info.family_id;
++
++	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
++	if (r)
++		return CUE_SINIT_FAILED;
++
++        r = amdgpu_cs_alloc_ib(device_handle, context_handle,
++                               IB_SIZE, &ib_result);
++	if (r)
++		return CUE_SINIT_FAILED;
++
++	ib_handle = ib_result.handle;
++	ib_cpu = ib_result.cpu;
++
++	return CUE_SUCCESS;
++}
++
++int suite_cs_tests_clean(void)
++{
++	int r;
++
++	r = amdgpu_cs_free_ib(device_handle, context_handle, ib_handle);
++	if (r)
++		return CUE_SCLEAN_FAILED;
++
++	r = amdgpu_cs_ctx_free(device_handle, context_handle);
++	if (r)
++		return CUE_SCLEAN_FAILED;
++
++	r = amdgpu_device_deinitialize(device_handle);
++	if (r)
++		return CUE_SCLEAN_FAILED;
++
++	return CUE_SUCCESS;
++}
++
++static int submit(unsigned ndw, unsigned ip)
++{
++	struct amdgpu_cs_ib_alloc_result ib_result = {0};
++	struct amdgpu_cs_request ibs_request = {0};
++	struct amdgpu_cs_ib_info ib_info = {0};
++	struct amdgpu_cs_query_fence fence_status = {0};
++	uint32_t expired;
++	int r;
++
++	ib_info.ib_handle = ib_handle;
++	ib_info.size = ndw;
++
++	ibs_request.ip_type = ip;
++	ibs_request.number_of_resources = num_resources;
++	ibs_request.resources = resources;
++	ibs_request.number_of_ibs = 1;
++	ibs_request.ibs = &ib_info;
++
++	r = amdgpu_cs_submit(device_handle, context_handle, 0,
++			     &ibs_request, 1, &fence_status.fence);
++	if (r)
++		return r;
++
++	r = amdgpu_cs_alloc_ib(device_handle, context_handle,
++			       IB_SIZE, &ib_result);
++	if (r)
++		return r;
++
++	ib_handle = ib_result.handle;
++	ib_cpu = ib_result.cpu;
++
++	fence_status.context = context_handle;
++	fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
++	fence_status.ip_type = ip;
++
++	r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
++{
++	ib_cpu[(*idx)++] = 0x3BC4;
++	ib_cpu[(*idx)++] = addr;
++	ib_cpu[(*idx)++] = 0x3BC5;
++	ib_cpu[(*idx)++] = addr >> 32;
++	ib_cpu[(*idx)++] = 0x3BC3;
++	ib_cpu[(*idx)++] = cmd << 1;
++}
++
++static void amdgpu_cs_uvd_create(void)
++{
++	struct amdgpu_bo_alloc_request req = {0};
++	struct amdgpu_bo_alloc_result res = {0};
++	void *msg;
++	int i, r;
++
++	req.alloc_size = 4*1024;
++	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
++
++	r = amdgpu_bo_alloc(device_handle, &req, &res);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_cpu_map(res.buf_handle, &msg);
++	CU_ASSERT_EQUAL(r, 0);
++
++	memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
++	if (family_id >= AMDGPU_FAMILY_VI)
++		((uint8_t*)msg)[0x10] = 7;
++
++	r = amdgpu_bo_cpu_unmap(res.buf_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	num_resources = 0;
++	resources[num_resources++] = res.buf_handle;
++
++	i = 0;
++	uvd_cmd(res.virtual_mc_base_address, 0x0, &i);
++	for (; i % 16; ++i)
++		ib_cpu[i] = 0x80000000;
++
++	r = submit(i, AMDGPU_HW_IP_UVD);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_free(resources[0]);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_cs_uvd_decode(void)
++{
++	const unsigned dpb_size = 15923584, dt_size = 737280;
++	uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr;
++	struct amdgpu_bo_alloc_request req = {0};
++	struct amdgpu_bo_alloc_result res = {0};
++	uint64_t sum;
++	uint8_t *ptr;
++	int i, r;
++
++	req.alloc_size = 4*1024; /* msg */
++	req.alloc_size += 4*1024; /* fb */
++	if (family_id >= AMDGPU_FAMILY_VI)
++		req.alloc_size += 4096; /*it_scaling_table*/
++	req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
++	req.alloc_size += ALIGN(dpb_size, 4*1024);
++	req.alloc_size += ALIGN(dt_size, 4*1024);
++
++	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
++
++	r = amdgpu_bo_alloc(device_handle, &req, &res);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_cpu_map(res.buf_handle, (void **)&ptr);
++	CU_ASSERT_EQUAL(r, 0);
++
++	memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
++	if (family_id >= AMDGPU_FAMILY_VI)
++		ptr[0x10] = 7;
++
++	ptr += 4*1024;
++	memset(ptr, 0, 4*1024);
++	if (family_id >= AMDGPU_FAMILY_VI) {
++		ptr += 4*1024;
++		memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
++	}
++
++	ptr += 4*1024;
++	memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
++
++	ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
++	memset(ptr, 0, dpb_size);
++
++	ptr += ALIGN(dpb_size, 4*1024);
++	memset(ptr, 0, dt_size);
++
++	num_resources = 0;
++	resources[num_resources++] = res.buf_handle;
++
++	msg_addr = res.virtual_mc_base_address;
++	fb_addr = msg_addr + 4*1024;
++	if (family_id >= AMDGPU_FAMILY_VI) {
++		it_addr = fb_addr + 4*1024;
++		bs_addr = it_addr + 4*1024;
++	} else
++		bs_addr = fb_addr + 4*1024;
++	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
++	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
++
++	i = 0;
++	uvd_cmd(msg_addr, 0x0, &i);
++	uvd_cmd(dpb_addr, 0x1, &i);
++	uvd_cmd(dt_addr, 0x2, &i);
++	uvd_cmd(fb_addr, 0x3, &i);
++	uvd_cmd(bs_addr, 0x100, &i);
++	if (family_id >= AMDGPU_FAMILY_VI)
++		uvd_cmd(it_addr, 0x204, &i);
++	ib_cpu[i++] = 0x3BC6;
++	ib_cpu[i++] = 0x1;
++	for (; i % 16; ++i)
++		ib_cpu[i] = 0x80000000;
++
++	r = submit(i, AMDGPU_HW_IP_UVD);
++	CU_ASSERT_EQUAL(r, 0);
++
++	/* TODO: use a real CRC32 */
++	for (i = 0, sum = 0; i < dt_size; ++i)
++		sum += ptr[i];
++	CU_ASSERT_EQUAL(sum, 0x20345d8);
++
++	r = amdgpu_bo_cpu_unmap(res.buf_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_free(resources[0]);
++	CU_ASSERT_EQUAL(r, 0);
++}
++
++static void amdgpu_cs_uvd_destroy(void)
++{
++	struct amdgpu_bo_alloc_request req = {0};
++	struct amdgpu_bo_alloc_result res = {0};
++	void *msg;
++	int i, r;
++
++	req.alloc_size = 4*1024;
++	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
++
++	r = amdgpu_bo_alloc(device_handle, &req, &res);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_cpu_map(res.buf_handle, &msg);
++	CU_ASSERT_EQUAL(r, 0);
++
++	memcpy(msg, uvd_destroy_msg, sizeof(uvd_create_msg));
++	if (family_id >= AMDGPU_FAMILY_VI)
++		((uint8_t*)msg)[0x10] = 7;
++
++	r = amdgpu_bo_cpu_unmap(res.buf_handle);
++	CU_ASSERT_EQUAL(r, 0);
++
++	num_resources = 0;
++	resources[num_resources++] = res.buf_handle;
++
++	i = 0;
++	uvd_cmd(res.virtual_mc_base_address, 0x0, &i);
++	for (; i % 16; ++i)
++		ib_cpu[i] = 0x80000000;
++
++	r = submit(i, AMDGPU_HW_IP_UVD);
++	CU_ASSERT_EQUAL(r, 0);
++
++	r = amdgpu_bo_free(resources[0]);
++	CU_ASSERT_EQUAL(r, 0);
++}
+diff --git a/tests/amdgpu/uvd_messages.h b/tests/amdgpu/uvd_messages.h
+new file mode 100644
+index 0000000..d4069c9
+--- /dev/null
++++ b/tests/amdgpu/uvd_messages.h
+@@ -0,0 +1,813 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef _uvd_messages_h_
++#define _uvd_messages_h_
++
++static uint8_t uvd_create_msg[] = {
++	0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00,
++	0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++};
++
++static uint8_t uvd_bitstream[] ={
++	0x00,0x00,0x01,0x25,0xb8,0x20,0x20,0x21,0x44,0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe,
++	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
++	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
++	0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,0x0e,0x00,0x02,0x02,0xa0,0x00,0x20,
++	0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,0x73,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xaf,0x00,0x00,0x01,0x25,0x00,0xa2,0xb8,0x20,0x20,0x21,0x44,
++	0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
++	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
++	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,
++	0x0e,0x00,0x02,0x02,0xa0,0x00,0x20,0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,
++	0x73,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xaf,0x00,0x00,0x01,0x25,
++	0x00,0x51,0x2e,0x08,0x08,0x08,0x51,0x31,0x40,0x00,0x55,0xe6,0xfb,0xef,0xbe,0xfb,
++	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
++	0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
++	0xfb,0xef,0xbf,0xe1,0xff,0xf0,0x96,0x03,0x80,0x00,0x80,0xa8,0x00,0x08,0x0e,0x80,
++	0x03,0x40,0x00,0x40,0x69,0x32,0xe5,0x1c,0xfa,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xc0,0x00,0x00,0x01,0x25,0x00,0x79,0xae,0x08,0x08,0x08,0x51,0x31,
++	0x40,0x00,0x55,0xe6,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
++	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
++	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbf,0xe1,0xff,0xf0,0x96,0x03,
++	0x80,0x00,0x80,0xa8,0x00,0x08,0x0e,0x80,0x03,0x40,0x00,0x40,0x69,0x32,0xe5,0x1c,
++	0xfa,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xc0,0x00,0x00,0x01,0x25,
++	0x00,0x28,0x8b,0x82,0x02,0x02,0x14,0x4c,0x50,0x00,0x15,0x79,0xbe,0xfb,0xef,0xbe,
++	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
++	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
++	0xbe,0xfb,0xef,0xf8,0x7f,0xfc,0x25,0x80,0xe0,0x00,0x20,0x2a,0x00,0x02,0x03,0xa0,
++	0x00,0xd0,0x00,0x10,0x1a,0x4c,0xb9,0x47,0x3e,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
++	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
++	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
++	0xeb,0xae,0xba,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++};
++
++static uint8_t uvd_decode_msg[] = {
++	0xe4,0x0d,0x00,0x00,0x01,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
++	0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++};
++
++static uint8_t uvd_destroy_msg[] = {
++	0xe4,0x0d,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
++};
++
++static uint8_t uvd_it_scaling_table[] = {
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
++};
++
++#endif /* _uvd_messages_h_ */
+diff --git a/tests/kmstest/main.c b/tests/kmstest/main.c
+index 7d50f5b..f39364f 100644
+--- a/tests/kmstest/main.c
++++ b/tests/kmstest/main.c
+@@ -62,6 +62,7 @@ static const char *drivers[] = {
+ 	"nouveau",
+ 	"vmwgfx",
+ 	"exynos",
++	"amdgpu",
+ 	"imx-drm",
+ 	"rockchip",
+ 	NULL
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/drm/libdrm/0003-tests-also-install-tests-app.patch b/meta-amdfalconx86/recipes-graphics/drm/libdrm/0003-tests-also-install-tests-app.patch
new file mode 100644
index 00000000..2adfbe74
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/drm/libdrm/0003-tests-also-install-tests-app.patch
@@ -0,0 +1,34 @@
+From b0c643612ff1477ab0faf49592556525d85fdb22 Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Tue, 21 Apr 2015 04:50:04 +0530
+Subject: [PATCH 3/3] tests: also install tests app
+
+Upstream-Status: Inappropriate [configuration]
+
+Signed-off-by: Yu Ke <ke.yu@intel.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ tests/Makefile.am | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/tests/Makefile.am b/tests/Makefile.am
+index a980b3d..fff6294 100644
+--- a/tests/Makefile.am
++++ b/tests/Makefile.am
+@@ -1,3 +1,4 @@
++check_PROGRAMS =
+ SUBDIRS = modeprint proptest modetest
+ 
+ if HAVE_LIBKMS
+@@ -33,7 +34,7 @@ AM_CFLAGS = \
+ 
+ LDADD = $(top_builddir)/libdrm.la
+ 
+-check_PROGRAMS = \
++bin_PROGRAMS = \
+ 	dristat \
+ 	drmstat
+ 
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/drm/libdrm_git.bbappend b/meta-amdfalconx86/recipes-graphics/drm/libdrm_git.bbappend
new file mode 100644
index 00000000..1ca35fd4
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/drm/libdrm_git.bbappend
@@ -0,0 +1,19 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI_append_amdfalconx86 = " file://0001-drm-add-libdrm_amdgpu.patch \
+				file://0002-drm-add-tests-amdgpu.patch \
+				file://0003-tests-also-install-tests-app.patch \
+"
+
+SRCREV_amdfalconx86 = "0d78b37b1cac304ce5e84d1207f0a43abd29c000"
+PV_amdfalconx86 = "2.4.60+git${SRCPV}"
+
+EXTRA_OECONF_append_amdfalconx86 = " --enable-amdgpu \
+				     --enable-radeon \
+"
+
+FILES_${PN}-amdgpu = "${libdir}/libdrm_amdgpu.so.*"
+
+do_install_append_amdfalconx86() {
+	cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm
+}
diff --git a/meta-amdfalconx86/recipes-graphics/libepoxy/libepoxy_1.2.bb b/meta-amdfalconx86/recipes-graphics/libepoxy/libepoxy_1.2.bb
new file mode 100644
index 00000000..02c8cad4
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/libepoxy/libepoxy_1.2.bb
@@ -0,0 +1,23 @@
+SUMMARY = "Library for handling OpenGL function pointer management"
+
+DESCRIPTION = "Epoxy is a library for handling OpenGL function pointer \
+management for you. It hides the complexity of dlopen(), dlsym(), \
+glXGetProcAddress(), eglGetProcAddress(), etc. from the app developer, \
+with very little knowledge needed on their part. They get to read GL specs \
+and write code using undecorated function names like glCompileShader()."
+
+HOMEPAGE = "https://github.com/anholt/libepoxy"
+SECTION = "x11/libs"
+LICENSE = "MIT"
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=58ef4c80d401e07bd9ee8b6b58cf464b"
+
+SRC_URI = "http://crux.nu/files/libepoxy-${PV}.tar.gz"
+SRC_URI[md5sum] = "12d6b7621f086c0c928887c27d90bc30"
+SRC_URI[sha256sum] = "42c328440f60a5795835c5ec4bdfc1329e75bba16b6e22b3a87ed17e9679e8f6"
+
+S = "${WORKDIR}/libepoxy-${PV}"
+
+DEPENDS += "util-macros virtual/libx11 virtual/egl"
+
+inherit autotools pkgconfig gettext
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0001-winsys-radeon-make-radeon_bo_vtbl-static.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0001-winsys-radeon-make-radeon_bo_vtbl-static.patch
new file mode 100644
index 00000000..a6abee97
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0001-winsys-radeon-make-radeon_bo_vtbl-static.patch
@@ -0,0 +1,35 @@
+From 65a1b608e285322358732911e41fce4fe89a5e07 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 19:09:57 +0200
+Subject: [PATCH 01/29] winsys/radeon: make radeon_bo_vtbl static
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+index e609d68..061c814 100644
+--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+@@ -42,7 +42,7 @@
+ #include <fcntl.h>
+ #include <stdio.h>
+ 
+-extern const struct pb_vtbl radeon_bo_vtbl;
++static const struct pb_vtbl radeon_bo_vtbl;
+ 
+ static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
+ {
+@@ -471,7 +471,7 @@ static void radeon_bo_fence(struct pb_buffer *buf,
+ {
+ }
+ 
+-const struct pb_vtbl radeon_bo_vtbl = {
++static const struct pb_vtbl radeon_bo_vtbl = {
+     radeon_bo_destroy,
+     NULL, /* never called */
+     NULL, /* never called */
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0002-gallium-radeon-print-winsys-info-with-R600_DEBUG-inf.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0002-gallium-radeon-print-winsys-info-with-R600_DEBUG-inf.patch
new file mode 100644
index 00000000..989b7a0d
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0002-gallium-radeon-print-winsys-info-with-R600_DEBUG-inf.patch
@@ -0,0 +1,71 @@
+From f3caa583548e36334891974a337d7e932d4260b3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:15:16 +0200
+Subject: [PATCH 02/29] gallium/radeon: print winsys info with R600_DEBUG=info
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/r600_pipe_common.c | 27 +++++++++++++++++++++++++++
+ src/gallium/drivers/radeon/r600_pipe_common.h |  1 +
+ 2 files changed, 28 insertions(+)
+
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
+index 2b27e0a..c6d7918 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.c
++++ b/src/gallium/drivers/radeon/r600_pipe_common.c
+@@ -306,6 +306,7 @@ static const struct debug_named_value common_debug_options[] = {
+ 	{ "compute", DBG_COMPUTE, "Print compute info" },
+ 	{ "vm", DBG_VM, "Print virtual addresses when creating resources" },
+ 	{ "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
++	{ "info", DBG_INFO, "Print driver information" },
+ 
+ 	/* shaders */
+ 	{ "fs", DBG_FS, "Print fetch shaders" },
+@@ -874,6 +875,32 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
+ 		}
+ 	}
+ 
++	if (rscreen->debug_flags & DBG_INFO) {
++		printf("pci_id = 0x%x\n", rscreen->info.pci_id);
++		printf("family = %i\n", rscreen->info.family);
++		printf("chip_class = %i\n", rscreen->info.chip_class);
++		printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
++		printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
++		printf("max_sclk = %i\n", rscreen->info.max_sclk);
++		printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
++		printf("max_se = %i\n", rscreen->info.max_se);
++		printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
++		printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
++		       rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
++		printf("has_uvd = %i\n", rscreen->info.has_uvd);
++		printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
++		printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
++		printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
++		printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
++		printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
++		printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
++		printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
++		printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
++		printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
++		printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
++		printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
++		printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
++	}
+ 	return true;
+ }
+ 
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
+index febd2a1..384a9a6 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.h
++++ b/src/gallium/drivers/radeon/r600_pipe_common.h
+@@ -84,6 +84,7 @@
+ #define DBG_SWITCH_ON_EOP	(1 << 15)
+ #define DBG_FORCE_DMA		(1 << 16)
+ #define DBG_PRECOMPILE		(1 << 17)
++#define DBG_INFO		(1 << 18)
+ /* The maximum allowed bit is 20. */
+ 
+ #define R600_MAP_BUFFER_ALIGNMENT 64
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0003-radeonsi-remove-useless-includes.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0003-radeonsi-remove-useless-includes.patch
new file mode 100644
index 00000000..28736b8d
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0003-radeonsi-remove-useless-includes.patch
@@ -0,0 +1,27 @@
+From 2eb1c8e83edfa6ebb0603e20813136bd696bea01 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:16:35 +0200
+Subject: [PATCH 03/29] radeonsi: remove useless includes
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeonsi/si_pipe.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
+index 5dc657c..e68c30e 100644
+--- a/src/gallium/drivers/radeonsi/si_pipe.c
++++ b/src/gallium/drivers/radeonsi/si_pipe.c
+@@ -30,9 +30,6 @@
+ #include "util/u_memory.h"
+ #include "vl/vl_decoder.h"
+ 
+-#include <llvm-c/Target.h>
+-#include <llvm-c/TargetMachine.h>
+-
+ /*
+  * pipe_context
+  */
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0004-radeonsi-remove-deprecated-and-useless-registers.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0004-radeonsi-remove-deprecated-and-useless-registers.patch
new file mode 100644
index 00000000..0bc7a57d
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0004-radeonsi-remove-deprecated-and-useless-registers.patch
@@ -0,0 +1,36 @@
+From 3c24679d5732c8b90e793537cd43c69a3a4d0618 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:37:45 +0200
+Subject: [PATCH 04/29] radeonsi: remove deprecated and useless registers
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeonsi/si_state.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index 4bb6f2b..f24cbbd 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -3035,18 +3035,8 @@ void si_init_config(struct si_context *sctx)
+ 
+ 	si_cmd_context_control(pm4);
+ 
+-	si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
+-	si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
+ 	si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
+ 	si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
+-	si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
+-	si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
+-	si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
+-	si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
+-	si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
+-	si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
+-	si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
+-	si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
+ 
+ 	/* FIXME calculate these values somehow ??? */
+ 	si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0005-radeonsi-set-an-optimal-value-for-DB_Z_INFO_ZRANGE_P.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0005-radeonsi-set-an-optimal-value-for-DB_Z_INFO_ZRANGE_P.patch
new file mode 100644
index 00000000..7148d2ee
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0005-radeonsi-set-an-optimal-value-for-DB_Z_INFO_ZRANGE_P.patch
@@ -0,0 +1,43 @@
+From a20e66cd94137e196ae5ef627b8d71d5bc6a52ed Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:40:31 +0200
+Subject: [PATCH 05/29] radeonsi: set an optimal value for
+ DB_Z_INFO_ZRANGE_PRECISION
+
+Required because of a VI hw bug.
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeonsi/si_state.c | 9 ++-------
+ 1 file changed, 2 insertions(+), 7 deletions(-)
+
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index f24cbbd..dc19d29 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -1948,12 +1948,6 @@ static void si_init_depth_surface(struct si_context *sctx,
+ 		z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
+ 			  S_028040_ALLOW_EXPCLEAR(1);
+ 
+-		/* This is optimal for the clear value of 1.0 and using
+-		 * the LESS and LEQUAL test functions. Set this to 0
+-		 * for the opposite case. This can only be changed when
+-		 * clearing. */
+-		z_info |= S_028040_ZRANGE_PRECISION(1);
+-
+ 		/* Use all of the htile_buffer for depth, because we don't
+ 		 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
+ 		s_info |= S_028044_TILE_STENCIL_DISABLE(1);
+@@ -2183,7 +2177,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
+ 
+ 		r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
+ 		radeon_emit(cs, zb->db_depth_info);	/* R_02803C_DB_DEPTH_INFO */
+-		radeon_emit(cs, zb->db_z_info);		/* R_028040_DB_Z_INFO */
++		radeon_emit(cs, zb->db_z_info |		/* R_028040_DB_Z_INFO */
++			    S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
+ 		radeon_emit(cs, zb->db_stencil_info);	/* R_028044_DB_STENCIL_INFO */
+ 		radeon_emit(cs, zb->db_depth_base);	/* R_028048_DB_Z_READ_BASE */
+ 		radeon_emit(cs, zb->db_stencil_base);	/* R_02804C_DB_STENCIL_READ_BASE */
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0006-winsys-radeon-move-radeon_winsys.h-up-one-directory.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0006-winsys-radeon-move-radeon_winsys.h-up-one-directory.patch
new file mode 100644
index 00000000..90c1f976
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0006-winsys-radeon-move-radeon_winsys.h-up-one-directory.patch
@@ -0,0 +1,1483 @@
+From f31b21f2e2ec8f5ab61740ced586eb04dd4dcb37 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 22:50:33 +0200
+Subject: [PATCH 06/29] winsys/radeon: move radeon_winsys.h up one directory
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ .../auxiliary/target-helpers/inline_drm_helper.h   |   6 +-
+ src/gallium/drivers/r300/r300_chipset.c            |   2 +-
+ src/gallium/drivers/r300/r300_context.h            |   1 -
+ src/gallium/drivers/r300/r300_screen.h             |   2 +-
+ src/gallium/drivers/radeon/r600_pipe_common.h      |   2 +-
+ src/gallium/drivers/radeon/radeon_uvd.c            |   1 -
+ src/gallium/drivers/radeon/radeon_uvd.h            |   2 +-
+ src/gallium/drivers/radeon/radeon_vce.c            |   1 -
+ src/gallium/drivers/radeon/radeon_vce_40_2_2.c     |   1 -
+ src/gallium/drivers/radeon/radeon_video.c          |   1 -
+ src/gallium/drivers/radeon/radeon_video.h          |   2 +-
+ src/gallium/drivers/radeonsi/si_pm4.h              |   2 +-
+ src/gallium/targets/pipe-loader/pipe_r300.c        |   2 +-
+ src/gallium/targets/pipe-loader/pipe_r600.c        |   2 +-
+ src/gallium/targets/pipe-loader/pipe_radeonsi.c    |   2 +-
+ src/gallium/winsys/radeon/drm/Makefile.sources     |   2 +-
+ src/gallium/winsys/radeon/drm/radeon_drm_winsys.h  |   2 +-
+ src/gallium/winsys/radeon/drm/radeon_winsys.h      | 604 ---------------------
+ src/gallium/winsys/radeon/radeon_winsys.h          | 604 +++++++++++++++++++++
+ 19 files changed, 618 insertions(+), 623 deletions(-)
+ delete mode 100644 src/gallium/winsys/radeon/drm/radeon_winsys.h
+ create mode 100644 src/gallium/winsys/radeon/radeon_winsys.h
+
+diff --git a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
+index 542ad43..d3c331d 100644
+--- a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
++++ b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
+@@ -28,19 +28,19 @@
+ #endif
+ 
+ #if GALLIUM_R300
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "radeon/drm/radeon_drm_public.h"
+ #include "r300/r300_public.h"
+ #endif
+ 
+ #if GALLIUM_R600
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "radeon/drm/radeon_drm_public.h"
+ #include "r600/r600_public.h"
+ #endif
+ 
+ #if GALLIUM_RADEONSI
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "radeon/drm/radeon_drm_public.h"
+ #include "radeonsi/si_public.h"
+ #endif
+diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c
+index 7a83611..c1c7ce3 100644
+--- a/src/gallium/drivers/r300/r300_chipset.c
++++ b/src/gallium/drivers/r300/r300_chipset.c
+@@ -22,7 +22,7 @@
+  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+ 
+ #include "r300_chipset.h"
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ 
+ #include "util/u_debug.h"
+ #include "util/u_memory.h"
+diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
+index 4d2b153..3873c9a 100644
+--- a/src/gallium/drivers/r300/r300_context.h
++++ b/src/gallium/drivers/r300/r300_context.h
+@@ -36,7 +36,6 @@
+ #include "r300_defines.h"
+ #include "r300_screen.h"
+ #include "compiler/radeon_regalloc.h"
+-#include "radeon/drm/radeon_winsys.h"
+ 
+ struct u_upload_mgr;
+ struct r300_context;
+diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h
+index f0dd3c6..7bba39b 100644
+--- a/src/gallium/drivers/r300/r300_screen.h
++++ b/src/gallium/drivers/r300/r300_screen.h
+@@ -25,7 +25,7 @@
+ #define R300_SCREEN_H
+ 
+ #include "r300_chipset.h"
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "pipe/p_screen.h"
+ #include "util/u_slab.h"
+ #include "os/os_thread.h"
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
+index 384a9a6..b7df001 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.h
++++ b/src/gallium/drivers/radeon/r600_pipe_common.h
+@@ -34,7 +34,7 @@
+ 
+ #include <stdio.h>
+ 
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ 
+ #include "util/u_blitter.h"
+ #include "util/u_double_list.h"
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
+index 9668d7d..4d4b54b 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.c
++++ b/src/gallium/drivers/radeon/radeon_uvd.c
+@@ -45,7 +45,6 @@
+ #include "vl/vl_defines.h"
+ #include "vl/vl_mpeg12_decoder.h"
+ 
+-#include "radeon/drm/radeon_winsys.h"
+ #include "r600_pipe_common.h"
+ #include "radeon_video.h"
+ #include "radeon_uvd.h"
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
+index 462b101..41a6fb4 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.h
++++ b/src/gallium/drivers/radeon/radeon_uvd.h
+@@ -34,7 +34,7 @@
+ #ifndef RADEON_UVD_H
+ #define RADEON_UVD_H
+ 
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "vl/vl_video_buffer.h"
+ 
+ /* UVD uses PM4 packet type 0 and 2 */
+diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
+index 6d34bd3..5f710e6 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.c
++++ b/src/gallium/drivers/radeon/radeon_vce.c
+@@ -40,7 +40,6 @@
+ 
+ #include "vl/vl_video_buffer.h"
+ 
+-#include "radeon/drm/radeon_winsys.h"
+ #include "r600_pipe_common.h"
+ #include "radeon_video.h"
+ #include "radeon_vce.h"
+diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+index b176aa7..0902957 100644
+--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
++++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+@@ -40,7 +40,6 @@
+ 
+ #include "vl/vl_video_buffer.h"
+ 
+-#include "radeon/drm/radeon_winsys.h"
+ #include "r600_pipe_common.h"
+ #include "radeon_video.h"
+ #include "radeon_vce.h"
+diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
+index 1420798..6ec10c1 100644
+--- a/src/gallium/drivers/radeon/radeon_video.c
++++ b/src/gallium/drivers/radeon/radeon_video.c
+@@ -39,7 +39,6 @@
+ #include "vl/vl_defines.h"
+ #include "vl/vl_video_buffer.h"
+ 
+-#include "radeon/drm/radeon_winsys.h"
+ #include "r600_pipe_common.h"
+ #include "radeon_video.h"
+ #include "radeon_vce.h"
+diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h
+index 974ea4f..6d0ff28 100644
+--- a/src/gallium/drivers/radeon/radeon_video.h
++++ b/src/gallium/drivers/radeon/radeon_video.h
+@@ -34,7 +34,7 @@
+ #ifndef RADEON_VIDEO_H
+ #define RADEON_VIDEO_H
+ 
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "vl/vl_video_buffer.h"
+ 
+ #define RVID_ERR(fmt, args...) \
+diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h
+index bfb5562..d215882 100644
+--- a/src/gallium/drivers/radeonsi/si_pm4.h
++++ b/src/gallium/drivers/radeonsi/si_pm4.h
+@@ -27,7 +27,7 @@
+ #ifndef SI_PM4_H
+ #define SI_PM4_H
+ 
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ 
+ #define SI_PM4_MAX_DW		256
+ #define SI_PM4_MAX_BO		32
+diff --git a/src/gallium/targets/pipe-loader/pipe_r300.c b/src/gallium/targets/pipe-loader/pipe_r300.c
+index abcade4..368b8c2 100644
+--- a/src/gallium/targets/pipe-loader/pipe_r300.c
++++ b/src/gallium/targets/pipe-loader/pipe_r300.c
+@@ -1,7 +1,7 @@
+ #include "target-helpers/inline_debug_helper.h"
+ #include "state_tracker/drm_driver.h"
+ #include "radeon/drm/radeon_drm_public.h"
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "r300/r300_public.h"
+ 
+ static struct pipe_screen *
+diff --git a/src/gallium/targets/pipe-loader/pipe_r600.c b/src/gallium/targets/pipe-loader/pipe_r600.c
+index eb53637..65b11c8 100644
+--- a/src/gallium/targets/pipe-loader/pipe_r600.c
++++ b/src/gallium/targets/pipe-loader/pipe_r600.c
+@@ -1,7 +1,7 @@
+ #include "state_tracker/drm_driver.h"
+ #include "target-helpers/inline_debug_helper.h"
+ #include "radeon/drm/radeon_drm_public.h"
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "r600/r600_public.h"
+ 
+ static struct pipe_screen *
+diff --git a/src/gallium/targets/pipe-loader/pipe_radeonsi.c b/src/gallium/targets/pipe-loader/pipe_radeonsi.c
+index 1dcd781..5457b5b 100644
+--- a/src/gallium/targets/pipe-loader/pipe_radeonsi.c
++++ b/src/gallium/targets/pipe-loader/pipe_radeonsi.c
+@@ -1,7 +1,7 @@
+ #include "state_tracker/drm_driver.h"
+ #include "target-helpers/inline_debug_helper.h"
+ #include "radeon/drm/radeon_drm_public.h"
+-#include "radeon/drm/radeon_winsys.h"
++#include "radeon/radeon_winsys.h"
+ #include "radeonsi/si_public.h"
+ 
+ static struct pipe_screen *
+diff --git a/src/gallium/winsys/radeon/drm/Makefile.sources b/src/gallium/winsys/radeon/drm/Makefile.sources
+index d30969e..ced788b 100644
+--- a/src/gallium/winsys/radeon/drm/Makefile.sources
++++ b/src/gallium/winsys/radeon/drm/Makefile.sources
+@@ -7,7 +7,7 @@ C_SOURCES := \
+ 	radeon_drm_public.h \
+ 	radeon_drm_winsys.c \
+ 	radeon_drm_winsys.h \
+-	radeon_winsys.h
++	../radeon_winsys.h
+ 
+ TOOLS_HDR := \
+ 	radeon_ctx.h
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+index 5711ffa..70657be 100644
+--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+@@ -30,7 +30,7 @@
+ #ifndef RADEON_DRM_WINSYS_H
+ #define RADEON_DRM_WINSYS_H
+ 
+-#include "radeon_winsys.h"
++#include "../radeon_winsys.h"
+ #include "os/os_thread.h"
+ #include <radeon_drm.h>
+ 
+diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
+deleted file mode 100644
+index a8cc60a..0000000
+--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
++++ /dev/null
+@@ -1,604 +0,0 @@
+-/*
+- * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
+- * Copyright 2010 Marek Olšák <maraeo@gmail.com>
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * on the rights to use, copy, modify, merge, publish, distribute, sub
+- * license, and/or sell copies of the Software, and to permit persons to whom
+- * the Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice (including the next
+- * paragraph) shall be included in all copies or substantial portions of the
+- * Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+- * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+-
+-#ifndef RADEON_WINSYS_H
+-#define RADEON_WINSYS_H
+-
+-/* The public winsys interface header for the radeon driver. */
+-
+-/* R300 features in DRM.
+- *
+- * 2.6.0:
+- * - Hyper-Z
+- * - GB_Z_PEQ_CONFIG on rv350->r4xx
+- * - R500 FG_ALPHA_VALUE
+- *
+- * 2.8.0:
+- * - R500 US_FORMAT regs
+- * - R500 ARGB2101010 colorbuffer
+- * - CMask and AA regs
+- * - R16F/RG16F
+- */
+-
+-#include "pipebuffer/pb_buffer.h"
+-#include "radeon_surface.h"
+-
+-#define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
+-
+-#define RADEON_FLUSH_ASYNC		(1 << 0)
+-#define RADEON_FLUSH_KEEP_TILING_FLAGS	(1 << 1) /* needs DRM 2.12.0 */
+-#define RADEON_FLUSH_COMPUTE		(1 << 2)
+-#define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
+-
+-/* Tiling flags. */
+-enum radeon_bo_layout {
+-    RADEON_LAYOUT_LINEAR = 0,
+-    RADEON_LAYOUT_TILED,
+-    RADEON_LAYOUT_SQUARETILED,
+-
+-    RADEON_LAYOUT_UNKNOWN
+-};
+-
+-enum radeon_bo_domain { /* bitfield */
+-    RADEON_DOMAIN_GTT  = 2,
+-    RADEON_DOMAIN_VRAM = 4,
+-    RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
+-};
+-
+-enum radeon_bo_flag { /* bitfield */
+-    RADEON_FLAG_GTT_WC =        (1 << 0),
+-    RADEON_FLAG_CPU_ACCESS =    (1 << 1),
+-    RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
+-};
+-
+-enum radeon_bo_usage { /* bitfield */
+-    RADEON_USAGE_READ = 2,
+-    RADEON_USAGE_WRITE = 4,
+-    RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
+-};
+-
+-enum radeon_family {
+-    CHIP_UNKNOWN = 0,
+-    CHIP_R300, /* R3xx-based cores. */
+-    CHIP_R350,
+-    CHIP_RV350,
+-    CHIP_RV370,
+-    CHIP_RV380,
+-    CHIP_RS400,
+-    CHIP_RC410,
+-    CHIP_RS480,
+-    CHIP_R420,     /* R4xx-based cores. */
+-    CHIP_R423,
+-    CHIP_R430,
+-    CHIP_R480,
+-    CHIP_R481,
+-    CHIP_RV410,
+-    CHIP_RS600,
+-    CHIP_RS690,
+-    CHIP_RS740,
+-    CHIP_RV515,    /* R5xx-based cores. */
+-    CHIP_R520,
+-    CHIP_RV530,
+-    CHIP_R580,
+-    CHIP_RV560,
+-    CHIP_RV570,
+-    CHIP_R600,
+-    CHIP_RV610,
+-    CHIP_RV630,
+-    CHIP_RV670,
+-    CHIP_RV620,
+-    CHIP_RV635,
+-    CHIP_RS780,
+-    CHIP_RS880,
+-    CHIP_RV770,
+-    CHIP_RV730,
+-    CHIP_RV710,
+-    CHIP_RV740,
+-    CHIP_CEDAR,
+-    CHIP_REDWOOD,
+-    CHIP_JUNIPER,
+-    CHIP_CYPRESS,
+-    CHIP_HEMLOCK,
+-    CHIP_PALM,
+-    CHIP_SUMO,
+-    CHIP_SUMO2,
+-    CHIP_BARTS,
+-    CHIP_TURKS,
+-    CHIP_CAICOS,
+-    CHIP_CAYMAN,
+-    CHIP_ARUBA,
+-    CHIP_TAHITI,
+-    CHIP_PITCAIRN,
+-    CHIP_VERDE,
+-    CHIP_OLAND,
+-    CHIP_HAINAN,
+-    CHIP_BONAIRE,
+-    CHIP_KAVERI,
+-    CHIP_KABINI,
+-    CHIP_HAWAII,
+-    CHIP_MULLINS,
+-    CHIP_LAST,
+-};
+-
+-enum chip_class {
+-    CLASS_UNKNOWN = 0,
+-    R300,
+-    R400,
+-    R500,
+-    R600,
+-    R700,
+-    EVERGREEN,
+-    CAYMAN,
+-    SI,
+-    CIK,
+-};
+-
+-enum ring_type {
+-    RING_GFX = 0,
+-    RING_DMA,
+-    RING_UVD,
+-    RING_VCE,
+-    RING_LAST,
+-};
+-
+-enum radeon_value_id {
+-    RADEON_REQUESTED_VRAM_MEMORY,
+-    RADEON_REQUESTED_GTT_MEMORY,
+-    RADEON_BUFFER_WAIT_TIME_NS,
+-    RADEON_TIMESTAMP,
+-    RADEON_NUM_CS_FLUSHES,
+-    RADEON_NUM_BYTES_MOVED,
+-    RADEON_VRAM_USAGE,
+-    RADEON_GTT_USAGE
+-};
+-
+-enum radeon_bo_priority {
+-    RADEON_PRIO_MIN,
+-    RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
+-    RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
+-    RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
+-    RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
+-    RADEON_PRIO_COLOR_BUFFER,
+-    RADEON_PRIO_DEPTH_BUFFER,
+-    RADEON_PRIO_SHADER_TEXTURE_MSAA,
+-    RADEON_PRIO_COLOR_BUFFER_MSAA,
+-    RADEON_PRIO_DEPTH_BUFFER_MSAA,
+-    RADEON_PRIO_COLOR_META,
+-    RADEON_PRIO_DEPTH_META,
+-    RADEON_PRIO_MAX /* must be <= 15 */
+-};
+-
+-struct winsys_handle;
+-struct radeon_winsys_cs_handle;
+-
+-struct radeon_winsys_cs {
+-    unsigned                    cdw;  /* Number of used dwords. */
+-    uint32_t                    *buf; /* The command buffer. */
+-    enum ring_type              ring_type;
+-};
+-
+-struct radeon_info {
+-    uint32_t                    pci_id;
+-    enum radeon_family          family;
+-    enum chip_class             chip_class;
+-    uint64_t                    gart_size;
+-    uint64_t                    vram_size;
+-    uint32_t                    max_sclk;
+-    uint32_t                    max_compute_units;
+-    uint32_t                    max_se;
+-    uint32_t                    max_sh_per_se;
+-
+-    uint32_t                    drm_major; /* version */
+-    uint32_t                    drm_minor;
+-    uint32_t                    drm_patchlevel;
+-
+-    boolean                     has_uvd;
+-    uint32_t                    vce_fw_version;
+-    boolean                     has_userptr;
+-
+-    uint32_t                    r300_num_gb_pipes;
+-    uint32_t                    r300_num_z_pipes;
+-
+-    uint32_t                    r600_num_backends;
+-    uint32_t                    r600_clock_crystal_freq;
+-    uint32_t                    r600_tiling_config;
+-    uint32_t                    r600_num_tile_pipes;
+-    uint32_t                    r600_max_pipes;
+-    boolean                     r600_virtual_address;
+-    boolean                     r600_has_dma;
+-
+-    uint32_t                    r600_backend_map;
+-    boolean                     r600_backend_map_valid;
+-
+-    boolean                     si_tile_mode_array_valid;
+-    uint32_t                    si_tile_mode_array[32];
+-    uint32_t                    si_backend_enabled_mask;
+-
+-    boolean                     cik_macrotile_mode_array_valid;
+-    uint32_t                    cik_macrotile_mode_array[16];
+-};
+-
+-enum radeon_feature_id {
+-    RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
+-    RADEON_FID_R300_CMASK_ACCESS,
+-};
+-
+-struct radeon_winsys {
+-    /**
+-     * The screen object this winsys was created for
+-     */
+-    struct pipe_screen *screen;
+-
+-    /**
+-     * Decrement the winsys reference count.
+-     *
+-     * \param ws  The winsys this function is called for.
+-     * \return    True if the winsys and screen should be destroyed.
+-     */
+-    bool (*unref)(struct radeon_winsys *ws);
+-
+-    /**
+-     * Destroy this winsys.
+-     *
+-     * \param ws        The winsys this function is called from.
+-     */
+-    void (*destroy)(struct radeon_winsys *ws);
+-
+-    /**
+-     * Query an info structure from winsys.
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param info      Return structure
+-     */
+-    void (*query_info)(struct radeon_winsys *ws,
+-                       struct radeon_info *info);
+-
+-    /**************************************************************************
+-     * Buffer management. Buffer attributes are mostly fixed over its lifetime.
+-     *
+-     * Remember that gallium gets to choose the interface it needs, and the
+-     * window systems must then implement that interface (rather than the
+-     * other way around...).
+-     *************************************************************************/
+-
+-    /**
+-     * Create a buffer object.
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param size      The size to allocate.
+-     * \param alignment An alignment of the buffer in memory.
+-     * \param use_reusable_pool Whether the cache buffer manager should be used.
+-     * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
+-     * \return          The created buffer object.
+-     */
+-    struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
+-                                       unsigned size,
+-                                       unsigned alignment,
+-                                       boolean use_reusable_pool,
+-                                       enum radeon_bo_domain domain,
+-                                       enum radeon_bo_flag flags);
+-
+-    struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
+-            struct pb_buffer *buf);
+-
+-    /**
+-     * Map the entire data store of a buffer object into the client's address
+-     * space.
+-     *
+-     * \param buf       A winsys buffer object to map.
+-     * \param cs        A command stream to flush if the buffer is referenced by it.
+-     * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
+-     * \return          The pointer at the beginning of the buffer.
+-     */
+-    void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
+-                        struct radeon_winsys_cs *cs,
+-                        enum pipe_transfer_usage usage);
+-
+-    /**
+-     * Unmap a buffer object from the client's address space.
+-     *
+-     * \param buf       A winsys buffer object to unmap.
+-     */
+-    void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
+-
+-    /**
+-     * Return TRUE if a buffer object is being used by the GPU.
+-     *
+-     * \param buf       A winsys buffer object.
+-     * \param usage     Only check whether the buffer is busy for the given usage.
+-     */
+-    boolean (*buffer_is_busy)(struct pb_buffer *buf,
+-                              enum radeon_bo_usage usage);
+-
+-    /**
+-     * Wait for a buffer object until it is not used by a GPU. This is
+-     * equivalent to a fence placed after the last command using the buffer,
+-     * and synchronizing to the fence.
+-     *
+-     * \param buf       A winsys buffer object to wait for.
+-     * \param usage     Only wait until the buffer is idle for the given usage,
+-     *                  but may still be busy for some other usage.
+-     */
+-    void (*buffer_wait)(struct pb_buffer *buf, enum radeon_bo_usage usage);
+-
+-    /**
+-     * Return tiling flags describing a memory layout of a buffer object.
+-     *
+-     * \param buf       A winsys buffer object to get the flags from.
+-     * \param macrotile A pointer to the return value of the microtile flag.
+-     * \param microtile A pointer to the return value of the macrotile flag.
+-     *
+-     * \note microtile and macrotile are not bitmasks!
+-     */
+-    void (*buffer_get_tiling)(struct pb_buffer *buf,
+-                              enum radeon_bo_layout *microtile,
+-                              enum radeon_bo_layout *macrotile,
+-                              unsigned *bankw, unsigned *bankh,
+-                              unsigned *tile_split,
+-                              unsigned *stencil_tile_split,
+-                              unsigned *mtilea,
+-                              bool *scanout);
+-
+-    /**
+-     * Set tiling flags describing a memory layout of a buffer object.
+-     *
+-     * \param buf       A winsys buffer object to set the flags for.
+-     * \param cs        A command stream to flush if the buffer is referenced by it.
+-     * \param macrotile A macrotile flag.
+-     * \param microtile A microtile flag.
+-     * \param stride    A stride of the buffer in bytes, for texturing.
+-     *
+-     * \note microtile and macrotile are not bitmasks!
+-     */
+-    void (*buffer_set_tiling)(struct pb_buffer *buf,
+-                              struct radeon_winsys_cs *rcs,
+-                              enum radeon_bo_layout microtile,
+-                              enum radeon_bo_layout macrotile,
+-                              unsigned bankw, unsigned bankh,
+-                              unsigned tile_split,
+-                              unsigned stencil_tile_split,
+-                              unsigned mtilea,
+-                              unsigned stride,
+-                              bool scanout);
+-
+-    /**
+-     * Get a winsys buffer from a winsys handle. The internal structure
+-     * of the handle is platform-specific and only a winsys should access it.
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param whandle   A winsys handle pointer as was received from a state
+-     *                  tracker.
+-     * \param stride    The returned buffer stride in bytes.
+-     */
+-    struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
+-                                            struct winsys_handle *whandle,
+-                                            unsigned *stride);
+-
+-    /**
+-     * Get a winsys buffer from a user pointer. The resulting buffer can't
+-     * be exported. Both pointer and size must be page aligned.
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param pointer   User pointer to turn into a buffer object.
+-     * \param Size      Size in bytes for the new buffer.
+-     */
+-    struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
+-                                         void *pointer, unsigned size);
+-
+-    /**
+-     * Get a winsys handle from a winsys buffer. The internal structure
+-     * of the handle is platform-specific and only a winsys should access it.
+-     *
+-     * \param buf       A winsys buffer object to get the handle from.
+-     * \param whandle   A winsys handle pointer.
+-     * \param stride    A stride of the buffer in bytes, for texturing.
+-     * \return          TRUE on success.
+-     */
+-    boolean (*buffer_get_handle)(struct pb_buffer *buf,
+-                                 unsigned stride,
+-                                 struct winsys_handle *whandle);
+-
+-    /**
+-     * Return the virtual address of a buffer.
+-     *
+-     * \param buf       A winsys buffer object
+-     * \return          virtual address
+-     */
+-    uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
+-
+-    /**
+-     * Query the initial placement of the buffer from the kernel driver.
+-     */
+-    enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
+-
+-    /**************************************************************************
+-     * Command submission.
+-     *
+-     * Each pipe context should create its own command stream and submit
+-     * commands independently of other contexts.
+-     *************************************************************************/
+-
+-    /**
+-     * Create a command stream.
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param ring_type The ring type (GFX, DMA, UVD)
+-     * \param flush     Flush callback function associated with the command stream.
+-     * \param user      User pointer that will be passed to the flush callback.
+-     * \param trace_buf Trace buffer when tracing is enabled
+-     */
+-    struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
+-                                          enum ring_type ring_type,
+-                                          void (*flush)(void *ctx, unsigned flags,
+-							struct pipe_fence_handle **fence),
+-                                          void *flush_ctx,
+-                                          struct radeon_winsys_cs_handle *trace_buf);
+-
+-    /**
+-     * Destroy a command stream.
+-     *
+-     * \param cs        A command stream to destroy.
+-     */
+-    void (*cs_destroy)(struct radeon_winsys_cs *cs);
+-
+-    /**
+-     * Add a new buffer relocation. Every relocation must first be added
+-     * before it can be written.
+-     *
+-     * \param cs  A command stream to add buffer for validation against.
+-     * \param buf A winsys buffer to validate.
+-     * \param usage   Whether the buffer is used for read and/or write.
+-     * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
+-     * \param priority  A higher number means a greater chance of being
+-     *                  placed in the requested domain. 15 is the maximum.
+-     * \return Relocation index.
+-     */
+-    unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
+-                             struct radeon_winsys_cs_handle *buf,
+-                             enum radeon_bo_usage usage,
+-                             enum radeon_bo_domain domain,
+-                             enum radeon_bo_priority priority);
+-
+-    /**
+-     * Return the index of an already-added buffer.
+-     *
+-     * \param cs        Command stream
+-     * \param buf       Buffer
+-     * \return          The buffer index, or -1 if the buffer has not been added.
+-     */
+-    int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
+-                        struct radeon_winsys_cs_handle *buf);
+-
+-    /**
+-     * Return TRUE if there is enough memory in VRAM and GTT for the relocs
+-     * added so far. If the validation fails, all the relocations which have
+-     * been added since the last call of cs_validate will be removed and
+-     * the CS will be flushed (provided there are still any relocations).
+-     *
+-     * \param cs        A command stream to validate.
+-     */
+-    boolean (*cs_validate)(struct radeon_winsys_cs *cs);
+-
+-    /**
+-     * Return TRUE if there is enough memory in VRAM and GTT for the relocs
+-     * added so far.
+-     *
+-     * \param cs        A command stream to validate.
+-     * \param vram      VRAM memory size pending to be use
+-     * \param gtt       GTT memory size pending to be use
+-     */
+-    boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
+-
+-    /**
+-     * Flush a command stream.
+-     *
+-     * \param cs          A command stream to flush.
+-     * \param flags,      RADEON_FLUSH_ASYNC or 0.
+-     * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
+-     *                    after the CS and is returned through this parameter.
+-     * \param cs_trace_id A unique identifier of the cs, used for tracing.
+-     */
+-    void (*cs_flush)(struct radeon_winsys_cs *cs,
+-                     unsigned flags,
+-                     struct pipe_fence_handle **fence,
+-                     uint32_t cs_trace_id);
+-
+-    /**
+-     * Return TRUE if a buffer is referenced by a command stream.
+-     *
+-     * \param cs        A command stream.
+-     * \param buf       A winsys buffer.
+-     */
+-    boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
+-                                       struct radeon_winsys_cs_handle *buf,
+-                                       enum radeon_bo_usage usage);
+-
+-    /**
+-     * Request access to a feature for a command stream.
+-     *
+-     * \param cs        A command stream.
+-     * \param fid       Feature ID, one of RADEON_FID_*
+-     * \param enable    Whether to enable or disable the feature.
+-     */
+-    boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
+-                                  enum radeon_feature_id fid,
+-                                  boolean enable);
+-     /**
+-      * Make sure all asynchronous flush of the cs have completed
+-      *
+-      * \param cs        A command stream.
+-      */
+-    void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
+-
+-    /**
+-     * Wait for the fence and return true if the fence has been signalled.
+-     * The timeout of 0 will only return the status.
+-     * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
+-     * is signalled.
+-     */
+-    bool (*fence_wait)(struct radeon_winsys *ws,
+-                       struct pipe_fence_handle *fence,
+-                       uint64_t timeout);
+-
+-    /**
+-     * Reference counting for fences.
+-     */
+-    void (*fence_reference)(struct pipe_fence_handle **dst,
+-                            struct pipe_fence_handle *src);
+-
+-    /**
+-     * Initialize surface
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param surf      Surface structure ptr
+-     */
+-    int (*surface_init)(struct radeon_winsys *ws,
+-                        struct radeon_surface *surf);
+-
+-    /**
+-     * Find best values for a surface
+-     *
+-     * \param ws        The winsys this function is called from.
+-     * \param surf      Surface structure ptr
+-     */
+-    int (*surface_best)(struct radeon_winsys *ws,
+-                        struct radeon_surface *surf);
+-
+-    uint64_t (*query_value)(struct radeon_winsys *ws,
+-                            enum radeon_value_id value);
+-};
+-
+-
+-static INLINE void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
+-{
+-    cs->buf[cs->cdw++] = value;
+-}
+-
+-static INLINE void radeon_emit_array(struct radeon_winsys_cs *cs,
+-				     const uint32_t *values, unsigned count)
+-{
+-    memcpy(cs->buf+cs->cdw, values, count * 4);
+-    cs->cdw += count;
+-}
+-
+-#endif
+diff --git a/src/gallium/winsys/radeon/radeon_winsys.h b/src/gallium/winsys/radeon/radeon_winsys.h
+new file mode 100644
+index 0000000..a8cc60a
+--- /dev/null
++++ b/src/gallium/winsys/radeon/radeon_winsys.h
+@@ -0,0 +1,604 @@
++/*
++ * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
++ * Copyright 2010 Marek Olšák <maraeo@gmail.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * on the rights to use, copy, modify, merge, publish, distribute, sub
++ * license, and/or sell copies of the Software, and to permit persons to whom
++ * the Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#ifndef RADEON_WINSYS_H
++#define RADEON_WINSYS_H
++
++/* The public winsys interface header for the radeon driver. */
++
++/* R300 features in DRM.
++ *
++ * 2.6.0:
++ * - Hyper-Z
++ * - GB_Z_PEQ_CONFIG on rv350->r4xx
++ * - R500 FG_ALPHA_VALUE
++ *
++ * 2.8.0:
++ * - R500 US_FORMAT regs
++ * - R500 ARGB2101010 colorbuffer
++ * - CMask and AA regs
++ * - R16F/RG16F
++ */
++
++#include "pipebuffer/pb_buffer.h"
++#include "radeon_surface.h"
++
++#define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
++
++#define RADEON_FLUSH_ASYNC		(1 << 0)
++#define RADEON_FLUSH_KEEP_TILING_FLAGS	(1 << 1) /* needs DRM 2.12.0 */
++#define RADEON_FLUSH_COMPUTE		(1 << 2)
++#define RADEON_FLUSH_END_OF_FRAME       (1 << 3)
++
++/* Tiling flags. */
++enum radeon_bo_layout {
++    RADEON_LAYOUT_LINEAR = 0,
++    RADEON_LAYOUT_TILED,
++    RADEON_LAYOUT_SQUARETILED,
++
++    RADEON_LAYOUT_UNKNOWN
++};
++
++enum radeon_bo_domain { /* bitfield */
++    RADEON_DOMAIN_GTT  = 2,
++    RADEON_DOMAIN_VRAM = 4,
++    RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
++};
++
++enum radeon_bo_flag { /* bitfield */
++    RADEON_FLAG_GTT_WC =        (1 << 0),
++    RADEON_FLAG_CPU_ACCESS =    (1 << 1),
++    RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
++};
++
++enum radeon_bo_usage { /* bitfield */
++    RADEON_USAGE_READ = 2,
++    RADEON_USAGE_WRITE = 4,
++    RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
++};
++
++enum radeon_family {
++    CHIP_UNKNOWN = 0,
++    CHIP_R300, /* R3xx-based cores. */
++    CHIP_R350,
++    CHIP_RV350,
++    CHIP_RV370,
++    CHIP_RV380,
++    CHIP_RS400,
++    CHIP_RC410,
++    CHIP_RS480,
++    CHIP_R420,     /* R4xx-based cores. */
++    CHIP_R423,
++    CHIP_R430,
++    CHIP_R480,
++    CHIP_R481,
++    CHIP_RV410,
++    CHIP_RS600,
++    CHIP_RS690,
++    CHIP_RS740,
++    CHIP_RV515,    /* R5xx-based cores. */
++    CHIP_R520,
++    CHIP_RV530,
++    CHIP_R580,
++    CHIP_RV560,
++    CHIP_RV570,
++    CHIP_R600,
++    CHIP_RV610,
++    CHIP_RV630,
++    CHIP_RV670,
++    CHIP_RV620,
++    CHIP_RV635,
++    CHIP_RS780,
++    CHIP_RS880,
++    CHIP_RV770,
++    CHIP_RV730,
++    CHIP_RV710,
++    CHIP_RV740,
++    CHIP_CEDAR,
++    CHIP_REDWOOD,
++    CHIP_JUNIPER,
++    CHIP_CYPRESS,
++    CHIP_HEMLOCK,
++    CHIP_PALM,
++    CHIP_SUMO,
++    CHIP_SUMO2,
++    CHIP_BARTS,
++    CHIP_TURKS,
++    CHIP_CAICOS,
++    CHIP_CAYMAN,
++    CHIP_ARUBA,
++    CHIP_TAHITI,
++    CHIP_PITCAIRN,
++    CHIP_VERDE,
++    CHIP_OLAND,
++    CHIP_HAINAN,
++    CHIP_BONAIRE,
++    CHIP_KAVERI,
++    CHIP_KABINI,
++    CHIP_HAWAII,
++    CHIP_MULLINS,
++    CHIP_LAST,
++};
++
++enum chip_class {
++    CLASS_UNKNOWN = 0,
++    R300,
++    R400,
++    R500,
++    R600,
++    R700,
++    EVERGREEN,
++    CAYMAN,
++    SI,
++    CIK,
++};
++
++enum ring_type {
++    RING_GFX = 0,
++    RING_DMA,
++    RING_UVD,
++    RING_VCE,
++    RING_LAST,
++};
++
++enum radeon_value_id {
++    RADEON_REQUESTED_VRAM_MEMORY,
++    RADEON_REQUESTED_GTT_MEMORY,
++    RADEON_BUFFER_WAIT_TIME_NS,
++    RADEON_TIMESTAMP,
++    RADEON_NUM_CS_FLUSHES,
++    RADEON_NUM_BYTES_MOVED,
++    RADEON_VRAM_USAGE,
++    RADEON_GTT_USAGE
++};
++
++enum radeon_bo_priority {
++    RADEON_PRIO_MIN,
++    RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
++    RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
++    RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
++    RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
++    RADEON_PRIO_COLOR_BUFFER,
++    RADEON_PRIO_DEPTH_BUFFER,
++    RADEON_PRIO_SHADER_TEXTURE_MSAA,
++    RADEON_PRIO_COLOR_BUFFER_MSAA,
++    RADEON_PRIO_DEPTH_BUFFER_MSAA,
++    RADEON_PRIO_COLOR_META,
++    RADEON_PRIO_DEPTH_META,
++    RADEON_PRIO_MAX /* must be <= 15 */
++};
++
++struct winsys_handle;
++struct radeon_winsys_cs_handle;
++
++struct radeon_winsys_cs {
++    unsigned                    cdw;  /* Number of used dwords. */
++    uint32_t                    *buf; /* The command buffer. */
++    enum ring_type              ring_type;
++};
++
++struct radeon_info {
++    uint32_t                    pci_id;
++    enum radeon_family          family;
++    enum chip_class             chip_class;
++    uint64_t                    gart_size;
++    uint64_t                    vram_size;
++    uint32_t                    max_sclk;
++    uint32_t                    max_compute_units;
++    uint32_t                    max_se;
++    uint32_t                    max_sh_per_se;
++
++    uint32_t                    drm_major; /* version */
++    uint32_t                    drm_minor;
++    uint32_t                    drm_patchlevel;
++
++    boolean                     has_uvd;
++    uint32_t                    vce_fw_version;
++    boolean                     has_userptr;
++
++    uint32_t                    r300_num_gb_pipes;
++    uint32_t                    r300_num_z_pipes;
++
++    uint32_t                    r600_num_backends;
++    uint32_t                    r600_clock_crystal_freq;
++    uint32_t                    r600_tiling_config;
++    uint32_t                    r600_num_tile_pipes;
++    uint32_t                    r600_max_pipes;
++    boolean                     r600_virtual_address;
++    boolean                     r600_has_dma;
++
++    uint32_t                    r600_backend_map;
++    boolean                     r600_backend_map_valid;
++
++    boolean                     si_tile_mode_array_valid;
++    uint32_t                    si_tile_mode_array[32];
++    uint32_t                    si_backend_enabled_mask;
++
++    boolean                     cik_macrotile_mode_array_valid;
++    uint32_t                    cik_macrotile_mode_array[16];
++};
++
++enum radeon_feature_id {
++    RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
++    RADEON_FID_R300_CMASK_ACCESS,
++};
++
++struct radeon_winsys {
++    /**
++     * The screen object this winsys was created for
++     */
++    struct pipe_screen *screen;
++
++    /**
++     * Decrement the winsys reference count.
++     *
++     * \param ws  The winsys this function is called for.
++     * \return    True if the winsys and screen should be destroyed.
++     */
++    bool (*unref)(struct radeon_winsys *ws);
++
++    /**
++     * Destroy this winsys.
++     *
++     * \param ws        The winsys this function is called from.
++     */
++    void (*destroy)(struct radeon_winsys *ws);
++
++    /**
++     * Query an info structure from winsys.
++     *
++     * \param ws        The winsys this function is called from.
++     * \param info      Return structure
++     */
++    void (*query_info)(struct radeon_winsys *ws,
++                       struct radeon_info *info);
++
++    /**************************************************************************
++     * Buffer management. Buffer attributes are mostly fixed over its lifetime.
++     *
++     * Remember that gallium gets to choose the interface it needs, and the
++     * window systems must then implement that interface (rather than the
++     * other way around...).
++     *************************************************************************/
++
++    /**
++     * Create a buffer object.
++     *
++     * \param ws        The winsys this function is called from.
++     * \param size      The size to allocate.
++     * \param alignment An alignment of the buffer in memory.
++     * \param use_reusable_pool Whether the cache buffer manager should be used.
++     * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
++     * \return          The created buffer object.
++     */
++    struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
++                                       unsigned size,
++                                       unsigned alignment,
++                                       boolean use_reusable_pool,
++                                       enum radeon_bo_domain domain,
++                                       enum radeon_bo_flag flags);
++
++    struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
++            struct pb_buffer *buf);
++
++    /**
++     * Map the entire data store of a buffer object into the client's address
++     * space.
++     *
++     * \param buf       A winsys buffer object to map.
++     * \param cs        A command stream to flush if the buffer is referenced by it.
++     * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
++     * \return          The pointer at the beginning of the buffer.
++     */
++    void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
++                        struct radeon_winsys_cs *cs,
++                        enum pipe_transfer_usage usage);
++
++    /**
++     * Unmap a buffer object from the client's address space.
++     *
++     * \param buf       A winsys buffer object to unmap.
++     */
++    void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
++
++    /**
++     * Return TRUE if a buffer object is being used by the GPU.
++     *
++     * \param buf       A winsys buffer object.
++     * \param usage     Only check whether the buffer is busy for the given usage.
++     */
++    boolean (*buffer_is_busy)(struct pb_buffer *buf,
++                              enum radeon_bo_usage usage);
++
++    /**
++     * Wait for a buffer object until it is not used by a GPU. This is
++     * equivalent to a fence placed after the last command using the buffer,
++     * and synchronizing to the fence.
++     *
++     * \param buf       A winsys buffer object to wait for.
++     * \param usage     Only wait until the buffer is idle for the given usage,
++     *                  but may still be busy for some other usage.
++     */
++    void (*buffer_wait)(struct pb_buffer *buf, enum radeon_bo_usage usage);
++
++    /**
++     * Return tiling flags describing a memory layout of a buffer object.
++     *
++     * \param buf       A winsys buffer object to get the flags from.
++     * \param macrotile A pointer to the return value of the microtile flag.
++     * \param microtile A pointer to the return value of the macrotile flag.
++     *
++     * \note microtile and macrotile are not bitmasks!
++     */
++    void (*buffer_get_tiling)(struct pb_buffer *buf,
++                              enum radeon_bo_layout *microtile,
++                              enum radeon_bo_layout *macrotile,
++                              unsigned *bankw, unsigned *bankh,
++                              unsigned *tile_split,
++                              unsigned *stencil_tile_split,
++                              unsigned *mtilea,
++                              bool *scanout);
++
++    /**
++     * Set tiling flags describing a memory layout of a buffer object.
++     *
++     * \param buf       A winsys buffer object to set the flags for.
++     * \param cs        A command stream to flush if the buffer is referenced by it.
++     * \param macrotile A macrotile flag.
++     * \param microtile A microtile flag.
++     * \param stride    A stride of the buffer in bytes, for texturing.
++     *
++     * \note microtile and macrotile are not bitmasks!
++     */
++    void (*buffer_set_tiling)(struct pb_buffer *buf,
++                              struct radeon_winsys_cs *rcs,
++                              enum radeon_bo_layout microtile,
++                              enum radeon_bo_layout macrotile,
++                              unsigned bankw, unsigned bankh,
++                              unsigned tile_split,
++                              unsigned stencil_tile_split,
++                              unsigned mtilea,
++                              unsigned stride,
++                              bool scanout);
++
++    /**
++     * Get a winsys buffer from a winsys handle. The internal structure
++     * of the handle is platform-specific and only a winsys should access it.
++     *
++     * \param ws        The winsys this function is called from.
++     * \param whandle   A winsys handle pointer as was received from a state
++     *                  tracker.
++     * \param stride    The returned buffer stride in bytes.
++     */
++    struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
++                                            struct winsys_handle *whandle,
++                                            unsigned *stride);
++
++    /**
++     * Get a winsys buffer from a user pointer. The resulting buffer can't
++     * be exported. Both pointer and size must be page aligned.
++     *
++     * \param ws        The winsys this function is called from.
++     * \param pointer   User pointer to turn into a buffer object.
++     * \param Size      Size in bytes for the new buffer.
++     */
++    struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
++                                         void *pointer, unsigned size);
++
++    /**
++     * Get a winsys handle from a winsys buffer. The internal structure
++     * of the handle is platform-specific and only a winsys should access it.
++     *
++     * \param buf       A winsys buffer object to get the handle from.
++     * \param whandle   A winsys handle pointer.
++     * \param stride    A stride of the buffer in bytes, for texturing.
++     * \return          TRUE on success.
++     */
++    boolean (*buffer_get_handle)(struct pb_buffer *buf,
++                                 unsigned stride,
++                                 struct winsys_handle *whandle);
++
++    /**
++     * Return the virtual address of a buffer.
++     *
++     * \param buf       A winsys buffer object
++     * \return          virtual address
++     */
++    uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
++
++    /**
++     * Query the initial placement of the buffer from the kernel driver.
++     */
++    enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
++
++    /**************************************************************************
++     * Command submission.
++     *
++     * Each pipe context should create its own command stream and submit
++     * commands independently of other contexts.
++     *************************************************************************/
++
++    /**
++     * Create a command stream.
++     *
++     * \param ws        The winsys this function is called from.
++     * \param ring_type The ring type (GFX, DMA, UVD)
++     * \param flush     Flush callback function associated with the command stream.
++     * \param user      User pointer that will be passed to the flush callback.
++     * \param trace_buf Trace buffer when tracing is enabled
++     */
++    struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
++                                          enum ring_type ring_type,
++                                          void (*flush)(void *ctx, unsigned flags,
++							struct pipe_fence_handle **fence),
++                                          void *flush_ctx,
++                                          struct radeon_winsys_cs_handle *trace_buf);
++
++    /**
++     * Destroy a command stream.
++     *
++     * \param cs        A command stream to destroy.
++     */
++    void (*cs_destroy)(struct radeon_winsys_cs *cs);
++
++    /**
++     * Add a new buffer relocation. Every relocation must first be added
++     * before it can be written.
++     *
++     * \param cs  A command stream to add buffer for validation against.
++     * \param buf A winsys buffer to validate.
++     * \param usage   Whether the buffer is used for read and/or write.
++     * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
++     * \param priority  A higher number means a greater chance of being
++     *                  placed in the requested domain. 15 is the maximum.
++     * \return Relocation index.
++     */
++    unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
++                             struct radeon_winsys_cs_handle *buf,
++                             enum radeon_bo_usage usage,
++                             enum radeon_bo_domain domain,
++                             enum radeon_bo_priority priority);
++
++    /**
++     * Return the index of an already-added buffer.
++     *
++     * \param cs        Command stream
++     * \param buf       Buffer
++     * \return          The buffer index, or -1 if the buffer has not been added.
++     */
++    int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
++                        struct radeon_winsys_cs_handle *buf);
++
++    /**
++     * Return TRUE if there is enough memory in VRAM and GTT for the relocs
++     * added so far. If the validation fails, all the relocations which have
++     * been added since the last call of cs_validate will be removed and
++     * the CS will be flushed (provided there are still any relocations).
++     *
++     * \param cs        A command stream to validate.
++     */
++    boolean (*cs_validate)(struct radeon_winsys_cs *cs);
++
++    /**
++     * Return TRUE if there is enough memory in VRAM and GTT for the relocs
++     * added so far.
++     *
++     * \param cs        A command stream to validate.
++     * \param vram      VRAM memory size pending to be use
++     * \param gtt       GTT memory size pending to be use
++     */
++    boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
++
++    /**
++     * Flush a command stream.
++     *
++     * \param cs          A command stream to flush.
++     * \param flags,      RADEON_FLUSH_ASYNC or 0.
++     * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
++     *                    after the CS and is returned through this parameter.
++     * \param cs_trace_id A unique identifier of the cs, used for tracing.
++     */
++    void (*cs_flush)(struct radeon_winsys_cs *cs,
++                     unsigned flags,
++                     struct pipe_fence_handle **fence,
++                     uint32_t cs_trace_id);
++
++    /**
++     * Return TRUE if a buffer is referenced by a command stream.
++     *
++     * \param cs        A command stream.
++     * \param buf       A winsys buffer.
++     */
++    boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
++                                       struct radeon_winsys_cs_handle *buf,
++                                       enum radeon_bo_usage usage);
++
++    /**
++     * Request access to a feature for a command stream.
++     *
++     * \param cs        A command stream.
++     * \param fid       Feature ID, one of RADEON_FID_*
++     * \param enable    Whether to enable or disable the feature.
++     */
++    boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
++                                  enum radeon_feature_id fid,
++                                  boolean enable);
++     /**
++      * Make sure all asynchronous flush of the cs have completed
++      *
++      * \param cs        A command stream.
++      */
++    void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
++
++    /**
++     * Wait for the fence and return true if the fence has been signalled.
++     * The timeout of 0 will only return the status.
++     * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
++     * is signalled.
++     */
++    bool (*fence_wait)(struct radeon_winsys *ws,
++                       struct pipe_fence_handle *fence,
++                       uint64_t timeout);
++
++    /**
++     * Reference counting for fences.
++     */
++    void (*fence_reference)(struct pipe_fence_handle **dst,
++                            struct pipe_fence_handle *src);
++
++    /**
++     * Initialize surface
++     *
++     * \param ws        The winsys this function is called from.
++     * \param surf      Surface structure ptr
++     */
++    int (*surface_init)(struct radeon_winsys *ws,
++                        struct radeon_surface *surf);
++
++    /**
++     * Find best values for a surface
++     *
++     * \param ws        The winsys this function is called from.
++     * \param surf      Surface structure ptr
++     */
++    int (*surface_best)(struct radeon_winsys *ws,
++                        struct radeon_surface *surf);
++
++    uint64_t (*query_value)(struct radeon_winsys *ws,
++                            enum radeon_value_id value);
++};
++
++
++static INLINE void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
++{
++    cs->buf[cs->cdw++] = value;
++}
++
++static INLINE void radeon_emit_array(struct radeon_winsys_cs *cs,
++				     const uint32_t *values, unsigned count)
++{
++    memcpy(cs->buf+cs->cdw, values, count * 4);
++    cs->cdw += count;
++}
++
++#endif
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0007-winsys-radeon-add-a-private-interface-for-radeon_sur.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0007-winsys-radeon-add-a-private-interface-for-radeon_sur.patch
new file mode 100644
index 00000000..094c76c0
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0007-winsys-radeon-add-a-private-interface-for-radeon_sur.patch
@@ -0,0 +1,659 @@
+From 96bcd3e235a5d326f455944e8393e254925b58bc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 22:53:04 +0200
+Subject: [PATCH 07/29] winsys/radeon: add a private interface for
+ radeon_surface
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/r600/evergreen_state.c         |   6 +-
+ src/gallium/drivers/r600/r600_uvd.c                |   2 +-
+ src/gallium/drivers/radeon/r600_pipe_common.h      |   2 +-
+ src/gallium/drivers/radeon/r600_texture.c          |  12 +-
+ src/gallium/drivers/radeon/radeon_uvd.c            |   6 +-
+ src/gallium/drivers/radeon/radeon_uvd.h            |   4 +-
+ src/gallium/drivers/radeon/radeon_vce.c            |   2 +-
+ src/gallium/drivers/radeon/radeon_vce.h            |   6 +-
+ src/gallium/drivers/radeon/radeon_video.c          |   2 +-
+ src/gallium/drivers/radeon/radeon_video.h          |   2 +-
+ src/gallium/drivers/radeonsi/si_state.c            |   4 +-
+ src/gallium/drivers/radeonsi/si_uvd.c              |   4 +-
+ src/gallium/winsys/radeon/drm/Makefile.sources     |   1 +
+ src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 180 +++++++++++++++++++++
+ src/gallium/winsys/radeon/drm/radeon_drm_winsys.c  |  20 +--
+ src/gallium/winsys/radeon/drm/radeon_drm_winsys.h  |   1 +
+ src/gallium/winsys/radeon/radeon_winsys.h          |  79 ++++++++-
+ 17 files changed, 286 insertions(+), 47 deletions(-)
+ create mode 100644 src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+
+diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
+index edd886b..8951ab0 100644
+--- a/src/gallium/drivers/r600/evergreen_state.c
++++ b/src/gallium/drivers/r600/evergreen_state.c
+@@ -664,7 +664,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
+ 	unsigned height, depth, width;
+ 	unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
+ 	enum pipe_format pipe_format = state->format;
+-	struct radeon_surface_level *surflevel;
++	struct radeon_surf_level *surflevel;
+ 	unsigned base_level, first_level, last_level;
+ 	uint64_t va;
+ 
+@@ -918,7 +918,7 @@ static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_
+ /**
+  * This function intializes the CB* register values for RATs.  It is meant
+  * to be used for 1D aligned buffers that do not have an associated
+- * radeon_surface.
++ * radeon_surf.
+  */
+ void evergreen_init_color_surface_rat(struct r600_context *rctx,
+ 					struct r600_surface *surf)
+@@ -1163,7 +1163,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
+ 	struct r600_screen *rscreen = rctx->screen;
+ 	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
+ 	unsigned level = surf->base.u.tex.level;
+-	struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
++	struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
+ 	uint64_t offset;
+ 	unsigned format, array_mode;
+ 	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
+diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c
+index ee5288f..357e901 100644
+--- a/src/gallium/drivers/r600/r600_uvd.c
++++ b/src/gallium/drivers/r600/r600_uvd.c
+@@ -57,7 +57,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
+ {
+ 	struct r600_context *ctx = (struct r600_context *)pipe;
+ 	struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
+-	struct radeon_surface* surfaces[VL_NUM_COMPONENTS] = {};
++	struct radeon_surf* surfaces[VL_NUM_COMPONENTS] = {};
+ 	struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
+ 	const enum pipe_format *resource_formats;
+ 	struct pipe_video_buffer template;
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
+index b7df001..bdb4541 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.h
++++ b/src/gallium/drivers/radeon/r600_pipe_common.h
+@@ -195,7 +195,7 @@ struct r600_texture {
+ 	unsigned			dirty_level_mask; /* each bit says if that mipmap is compressed */
+ 	struct r600_texture		*flushed_depth_texture;
+ 	boolean				is_flushing_texture;
+-	struct radeon_surface		surface;
++	struct radeon_surf		surface;
+ 
+ 	/* Colorbuffer compression and fast clear. */
+ 	struct r600_fmask_info		fmask;
+diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
+index ab8ce7b..dc510c9 100644
+--- a/src/gallium/drivers/radeon/r600_texture.c
++++ b/src/gallium/drivers/radeon/r600_texture.c
+@@ -119,7 +119,7 @@ static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned leve
+ }
+ 
+ static int r600_init_surface(struct r600_common_screen *rscreen,
+-			     struct radeon_surface *surface,
++			     struct radeon_surf *surface,
+ 			     const struct pipe_resource *ptex,
+ 			     unsigned array_mode,
+ 			     bool is_flushed_depth)
+@@ -234,7 +234,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
+ {
+ 	struct r600_texture *rtex = (struct r600_texture*)ptex;
+ 	struct r600_resource *resource = &rtex->resource;
+-	struct radeon_surface *surface = &rtex->surface;
++	struct radeon_surf *surface = &rtex->surface;
+ 	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ 
+ 	rscreen->ws->buffer_set_tiling(resource->buf,
+@@ -280,7 +280,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
+ 				 struct r600_fmask_info *out)
+ {
+ 	/* FMASK is allocated like an ordinary texture. */
+-	struct radeon_surface fmask = rtex->surface;
++	struct radeon_surf fmask = rtex->surface;
+ 
+ 	memset(out, 0, sizeof(*out));
+ 
+@@ -570,7 +570,7 @@ r600_texture_create_object(struct pipe_screen *screen,
+ 			   const struct pipe_resource *base,
+ 			   unsigned pitch_in_bytes_override,
+ 			   struct pb_buffer *buf,
+-			   struct radeon_surface *surface)
++			   struct radeon_surf *surface)
+ {
+ 	struct r600_texture *rtex;
+ 	struct r600_resource *resource;
+@@ -764,7 +764,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
+ 					  const struct pipe_resource *templ)
+ {
+ 	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+-	struct radeon_surface surface = {0};
++	struct radeon_surf surface = {0};
+ 	int r;
+ 
+ 	r = r600_init_surface(rscreen, &surface, templ,
+@@ -790,7 +790,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
+ 	unsigned stride = 0;
+ 	unsigned array_mode;
+ 	enum radeon_bo_layout micro, macro;
+-	struct radeon_surface surface;
++	struct radeon_surf surface;
+ 	bool scanout;
+ 	int r;
+ 
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
+index 4d4b54b..be58d0b 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.c
++++ b/src/gallium/drivers/radeon/radeon_uvd.c
+@@ -870,7 +870,7 @@ error:
+ }
+ 
+ /* calculate top/bottom offset */
+-static unsigned texture_offset(struct radeon_surface *surface, unsigned layer)
++static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
+ {
+ 	return surface->level[0].offset +
+ 		layer * surface->level[0].slice_size;
+@@ -905,8 +905,8 @@ static unsigned bank_wh(unsigned bankwh)
+ /**
+  * fill decoding target field from the luma and chroma surfaces
+  */
+-void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
+-			  struct radeon_surface *chroma)
++void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
++			  struct radeon_surf *chroma)
+ {
+ 	msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
+ 	switch (luma->level[0].mode) {
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
+index 41a6fb4..7442865 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.h
++++ b/src/gallium/drivers/radeon/radeon_uvd.h
+@@ -353,6 +353,6 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 					     ruvd_set_dtb set_dtb);
+ 
+ /* fill decoding target field from the luma and chroma surfaces */
+-void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
+-			  struct radeon_surface *chroma);
++void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
++			  struct radeon_surf *chroma);
+ #endif
+diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
+index 5f710e6..e220f40 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.c
++++ b/src/gallium/drivers/radeon/radeon_vce.c
+@@ -337,7 +337,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+ 	struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
+ 	struct rvce_encoder *enc;
+ 	struct pipe_video_buffer *tmp_buf, templat = {};
+-	struct radeon_surface *tmp_surf;
++	struct radeon_surf *tmp_surf;
+ 	unsigned cpb_size;
+ 
+ 	if (!rscreen->info.vce_fw_version) {
+diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
+index 7f0cd1f..5c6317a 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.h
++++ b/src/gallium/drivers/radeon/radeon_vce.h
+@@ -50,7 +50,7 @@ struct r600_common_screen;
+ /* driver dependent callback */
+ typedef void (*rvce_get_buffer)(struct pipe_resource *resource,
+ 				struct radeon_winsys_cs_handle **handle,
+-				struct radeon_surface **surface);
++				struct radeon_surf **surface);
+ 
+ /* Coded picture buffer slot */
+ struct rvce_cpb_slot {
+@@ -88,8 +88,8 @@ struct rvce_encoder {
+ 	rvce_get_buffer			get_buffer;
+ 
+ 	struct radeon_winsys_cs_handle*	handle;
+-	struct radeon_surface*		luma;
+-	struct radeon_surface*		chroma;
++	struct radeon_surf*		luma;
++	struct radeon_surf*		chroma;
+ 
+ 	struct radeon_winsys_cs_handle*	bs_handle;
+ 	unsigned			bs_size;
+diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
+index 6ec10c1..826e076 100644
+--- a/src/gallium/drivers/radeon/radeon_video.c
++++ b/src/gallium/drivers/radeon/radeon_video.c
+@@ -132,7 +132,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
+  */
+ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+ 			struct pb_buffer** buffers[VL_NUM_COMPONENTS],
+-			struct radeon_surface *surfaces[VL_NUM_COMPONENTS])
++			struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
+ {
+ 	unsigned best_tiling, best_wh, off;
+ 	unsigned size, alignment;
+diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h
+index 6d0ff28..c9ee67f 100644
+--- a/src/gallium/drivers/radeon/radeon_video.h
++++ b/src/gallium/drivers/radeon/radeon_video.h
+@@ -68,7 +68,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
+    sumup their sizes and replace the backend buffers with a single bo */
+ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+                         struct pb_buffer** buffers[VL_NUM_COMPONENTS],
+-                        struct radeon_surface *surfaces[VL_NUM_COMPONENTS]);
++                        struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);
+ 
+ /* returns supported codecs and other parameters */
+ int rvid_get_video_param(struct pipe_screen *screen,
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index dc19d29..7f0fdd5 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -1852,7 +1852,7 @@ static void si_init_depth_surface(struct si_context *sctx,
+ 	struct si_screen *sscreen = sctx->screen;
+ 	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
+ 	unsigned level = surf->base.u.tex.level;
+-	struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
++	struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
+ 	unsigned format, tile_mode_index, array_mode;
+ 	unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
+ 	uint32_t z_info, s_info, db_depth_info;
+@@ -2258,7 +2258,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
+ 	unsigned char state_swizzle[4], swizzle[4];
+ 	unsigned height, depth, width;
+ 	enum pipe_format pipe_format = state->format;
+-	struct radeon_surface_level *surflevel;
++	struct radeon_surf_level *surflevel;
+ 	int first_non_void;
+ 	uint64_t va;
+ 
+diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c
+index 0ba3b12..2f10f9b 100644
+--- a/src/gallium/drivers/radeonsi/si_uvd.c
++++ b/src/gallium/drivers/radeonsi/si_uvd.c
+@@ -44,7 +44,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
+ {
+ 	struct si_context *ctx = (struct si_context *)pipe;
+ 	struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
+-	struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {};
++	struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
+ 	struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
+ 	const enum pipe_format *resource_formats;
+ 	struct pipe_video_buffer template;
+@@ -136,7 +136,7 @@ static struct radeon_winsys_cs_handle* si_uvd_set_dtb(struct ruvd_msg *msg, stru
+ /* get the radeon resources for VCE */
+ static void si_vce_get_buffer(struct pipe_resource *resource,
+ 			      struct radeon_winsys_cs_handle **handle,
+-			      struct radeon_surface **surface)
++			      struct radeon_surf **surface)
+ {
+ 	struct r600_texture *res = (struct r600_texture *)resource;
+ 
+diff --git a/src/gallium/winsys/radeon/drm/Makefile.sources b/src/gallium/winsys/radeon/drm/Makefile.sources
+index ced788b..13a71c4 100644
+--- a/src/gallium/winsys/radeon/drm/Makefile.sources
++++ b/src/gallium/winsys/radeon/drm/Makefile.sources
+@@ -5,6 +5,7 @@ C_SOURCES := \
+ 	radeon_drm_cs_dump.c \
+ 	radeon_drm_cs.h \
+ 	radeon_drm_public.h \
++	radeon_drm_surface.c \
+ 	radeon_drm_winsys.c \
+ 	radeon_drm_winsys.h \
+ 	../radeon_winsys.h
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+new file mode 100644
+index 0000000..29d3467
+--- /dev/null
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+@@ -0,0 +1,180 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * Authors:
++ *   Marek Olšák <maraeo@gmail.com>
++ */
++
++#include "radeon_drm_winsys.h"
++
++#include <radeon_surface.h>
++
++static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
++                                     const struct radeon_surf_level *level_ws)
++{
++    level_drm->offset = level_ws->offset;
++    level_drm->slice_size = level_ws->slice_size;
++    level_drm->npix_x = level_ws->npix_x;
++    level_drm->npix_y = level_ws->npix_y;
++    level_drm->npix_z = level_ws->npix_z;
++    level_drm->nblk_x = level_ws->nblk_x;
++    level_drm->nblk_y = level_ws->nblk_y;
++    level_drm->nblk_z = level_ws->nblk_z;
++    level_drm->pitch_bytes = level_ws->pitch_bytes;
++    level_drm->mode = level_ws->mode;
++}
++
++static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
++                                     const struct radeon_surface_level *level_drm)
++{
++    level_ws->offset = level_drm->offset;
++    level_ws->slice_size = level_drm->slice_size;
++    level_ws->npix_x = level_drm->npix_x;
++    level_ws->npix_y = level_drm->npix_y;
++    level_ws->npix_z = level_drm->npix_z;
++    level_ws->nblk_x = level_drm->nblk_x;
++    level_ws->nblk_y = level_drm->nblk_y;
++    level_ws->nblk_z = level_drm->nblk_z;
++    level_ws->pitch_bytes = level_drm->pitch_bytes;
++    level_ws->mode = level_drm->mode;
++}
++
++static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
++                               const struct radeon_surf *surf_ws)
++{
++    int i;
++
++    memset(surf_drm, 0, sizeof(*surf_drm));
++
++    surf_drm->npix_x = surf_ws->npix_x;
++    surf_drm->npix_y = surf_ws->npix_y;
++    surf_drm->npix_z = surf_ws->npix_z;
++    surf_drm->blk_w = surf_ws->blk_w;
++    surf_drm->blk_h = surf_ws->blk_h;
++    surf_drm->blk_d = surf_ws->blk_d;
++    surf_drm->array_size = surf_ws->array_size;
++    surf_drm->last_level = surf_ws->last_level;
++    surf_drm->bpe = surf_ws->bpe;
++    surf_drm->nsamples = surf_ws->nsamples;
++    surf_drm->flags = surf_ws->flags;
++
++    surf_drm->bo_size = surf_ws->bo_size;
++    surf_drm->bo_alignment = surf_ws->bo_alignment;
++
++    surf_drm->bankw = surf_ws->bankw;
++    surf_drm->bankh = surf_ws->bankh;
++    surf_drm->mtilea = surf_ws->mtilea;
++    surf_drm->tile_split = surf_ws->tile_split;
++    surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
++    surf_drm->stencil_offset = surf_ws->stencil_offset;
++
++    for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
++        surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
++        surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
++                                 &surf_ws->stencil_level[i]);
++
++        surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
++        surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
++    }
++}
++
++static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
++                               const struct radeon_surface *surf_drm)
++{
++    int i;
++
++    memset(surf_ws, 0, sizeof(*surf_ws));
++
++    surf_ws->npix_x = surf_drm->npix_x;
++    surf_ws->npix_y = surf_drm->npix_y;
++    surf_ws->npix_z = surf_drm->npix_z;
++    surf_ws->blk_w = surf_drm->blk_w;
++    surf_ws->blk_h = surf_drm->blk_h;
++    surf_ws->blk_d = surf_drm->blk_d;
++    surf_ws->array_size = surf_drm->array_size;
++    surf_ws->last_level = surf_drm->last_level;
++    surf_ws->bpe = surf_drm->bpe;
++    surf_ws->nsamples = surf_drm->nsamples;
++    surf_ws->flags = surf_drm->flags;
++
++    surf_ws->bo_size = surf_drm->bo_size;
++    surf_ws->bo_alignment = surf_drm->bo_alignment;
++
++    surf_ws->bankw = surf_drm->bankw;
++    surf_ws->bankh = surf_drm->bankh;
++    surf_ws->mtilea = surf_drm->mtilea;
++    surf_ws->tile_split = surf_drm->tile_split;
++    surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
++    surf_ws->stencil_offset = surf_drm->stencil_offset;
++
++    for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
++        surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
++        surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
++                                 &surf_drm->stencil_level[i]);
++
++        surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
++        surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
++    }
++}
++
++static int radeon_winsys_surface_init(struct radeon_winsys *rws,
++                                      struct radeon_surf *surf_ws)
++{
++    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
++    struct radeon_surface surf_drm;
++    int r;
++
++    surf_winsys_to_drm(&surf_drm, surf_ws);
++
++    r = radeon_surface_init(ws->surf_man, &surf_drm);
++    if (r)
++        return r;
++
++    surf_drm_to_winsys(surf_ws, &surf_drm);
++    return 0;
++}
++
++static int radeon_winsys_surface_best(struct radeon_winsys *rws,
++                                      struct radeon_surf *surf_ws)
++{
++    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
++    struct radeon_surface surf_drm;
++    int r;
++
++    surf_winsys_to_drm(&surf_drm, surf_ws);
++
++    r = radeon_surface_best(ws->surf_man, &surf_drm);
++    if (r)
++        return r;
++
++    surf_drm_to_winsys(surf_ws, &surf_drm);
++    return 0;
++}
++
++void radeon_surface_init_functions(struct radeon_drm_winsys *ws)
++{
++    ws->base.surface_init = radeon_winsys_surface_init;
++    ws->base.surface_best = radeon_winsys_surface_best;
++}
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+index 2b12f4d..12767bf 100644
+--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+@@ -44,6 +44,7 @@
+ #include <sys/types.h>
+ #include <sys/stat.h>
+ #include <unistd.h>
++#include <radeon_surface.h>
+ 
+ #ifndef RADEON_INFO_ACTIVE_CU_COUNT
+ #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
+@@ -507,22 +508,6 @@ static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
+     return FALSE;
+ }
+ 
+-static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
+-                                          struct radeon_surface *surf)
+-{
+-    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
+-
+-    return radeon_surface_init(ws->surf_man, surf);
+-}
+-
+-static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
+-                                          struct radeon_surface *surf)
+-{
+-    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
+-
+-    return radeon_surface_best(ws->surf_man, surf);
+-}
+-
+ static uint64_t radeon_query_value(struct radeon_winsys *rws,
+                                    enum radeon_value_id value)
+ {
+@@ -706,12 +691,11 @@ radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
+     ws->base.destroy = radeon_winsys_destroy;
+     ws->base.query_info = radeon_query_info;
+     ws->base.cs_request_feature = radeon_cs_request_feature;
+-    ws->base.surface_init = radeon_drm_winsys_surface_init;
+-    ws->base.surface_best = radeon_drm_winsys_surface_best;
+     ws->base.query_value = radeon_query_value;
+ 
+     radeon_bomgr_init_functions(ws);
+     radeon_drm_cs_init_functions(ws);
++    radeon_surface_init_functions(ws);
+ 
+     pipe_mutex_init(ws->hyperz_owner_mutex);
+     pipe_mutex_init(ws->cmask_owner_mutex);
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+index 70657be..3200f0d 100644
+--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+@@ -103,5 +103,6 @@ radeon_drm_winsys(struct radeon_winsys *base)
+ }
+ 
+ void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs);
++void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
+ 
+ #endif
+diff --git a/src/gallium/winsys/radeon/radeon_winsys.h b/src/gallium/winsys/radeon/radeon_winsys.h
+index a8cc60a..7fb7ac9 100644
+--- a/src/gallium/winsys/radeon/radeon_winsys.h
++++ b/src/gallium/winsys/radeon/radeon_winsys.h
+@@ -41,7 +41,6 @@
+  */
+ 
+ #include "pipebuffer/pb_buffer.h"
+-#include "radeon_surface.h"
+ 
+ #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
+ 
+@@ -243,6 +242,80 @@ enum radeon_feature_id {
+     RADEON_FID_R300_CMASK_ACCESS,
+ };
+ 
++#define RADEON_SURF_MAX_LEVEL                   32
++
++#define RADEON_SURF_TYPE_MASK                   0xFF
++#define RADEON_SURF_TYPE_SHIFT                  0
++#define     RADEON_SURF_TYPE_1D                     0
++#define     RADEON_SURF_TYPE_2D                     1
++#define     RADEON_SURF_TYPE_3D                     2
++#define     RADEON_SURF_TYPE_CUBEMAP                3
++#define     RADEON_SURF_TYPE_1D_ARRAY               4
++#define     RADEON_SURF_TYPE_2D_ARRAY               5
++#define RADEON_SURF_MODE_MASK                   0xFF
++#define RADEON_SURF_MODE_SHIFT                  8
++#define     RADEON_SURF_MODE_LINEAR                 0
++#define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
++#define     RADEON_SURF_MODE_1D                     2
++#define     RADEON_SURF_MODE_2D                     3
++#define RADEON_SURF_SCANOUT                     (1 << 16)
++#define RADEON_SURF_ZBUFFER                     (1 << 17)
++#define RADEON_SURF_SBUFFER                     (1 << 18)
++#define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
++#define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
++#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
++#define RADEON_SURF_FMASK                       (1 << 21)
++
++#define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
++#define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
++#define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
++
++struct radeon_surf_level {
++    uint64_t                    offset;
++    uint64_t                    slice_size;
++    uint32_t                    npix_x;
++    uint32_t                    npix_y;
++    uint32_t                    npix_z;
++    uint32_t                    nblk_x;
++    uint32_t                    nblk_y;
++    uint32_t                    nblk_z;
++    uint32_t                    pitch_bytes;
++    uint32_t                    mode;
++};
++
++struct radeon_surf {
++    /* These are inputs to the calculator. */
++    uint32_t                    npix_x;
++    uint32_t                    npix_y;
++    uint32_t                    npix_z;
++    uint32_t                    blk_w;
++    uint32_t                    blk_h;
++    uint32_t                    blk_d;
++    uint32_t                    array_size;
++    uint32_t                    last_level;
++    uint32_t                    bpe;
++    uint32_t                    nsamples;
++    uint32_t                    flags;
++
++    /* These are return values. Some of them can be set by the caller, but
++     * they will be treated as hints (e.g. bankw, bankh) and might be
++     * changed by the calculator.
++     */
++    uint64_t                    bo_size;
++    uint64_t                    bo_alignment;
++    /* This applies to EG and later. */
++    uint32_t                    bankw;
++    uint32_t                    bankh;
++    uint32_t                    mtilea;
++    uint32_t                    tile_split;
++    uint32_t                    stencil_tile_split;
++    uint64_t                    stencil_offset;
++    struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
++    struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
++    uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
++    uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
++};
++
+ struct radeon_winsys {
+     /**
+      * The screen object this winsys was created for
+@@ -573,7 +646,7 @@ struct radeon_winsys {
+      * \param surf      Surface structure ptr
+      */
+     int (*surface_init)(struct radeon_winsys *ws,
+-                        struct radeon_surface *surf);
++                        struct radeon_surf *surf);
+ 
+     /**
+      * Find best values for a surface
+@@ -582,7 +655,7 @@ struct radeon_winsys {
+      * \param surf      Surface structure ptr
+      */
+     int (*surface_best)(struct radeon_winsys *ws,
+-                        struct radeon_surface *surf);
++                        struct radeon_surf *surf);
+ 
+     uint64_t (*query_value)(struct radeon_winsys *ws,
+                             enum radeon_value_id value);
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0008-winsys-amdgpu-add-a-new-winsys-for-the-new-kernel-dr.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0008-winsys-amdgpu-add-a-new-winsys-for-the-new-kernel-dr.patch
new file mode 100644
index 00000000..88914a74
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0008-winsys-amdgpu-add-a-new-winsys-for-the-new-kernel-dr.patch
@@ -0,0 +1,2396 @@
+From c0e94dfc8abc3ec25c0a6342f9872a9e71aa7864 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 22:43:23 +0200
+Subject: [PATCH 08/29] winsys/amdgpu: add a new winsys for the new kernel
+ driver
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ configure.ac                                      |   5 +
+ src/gallium/Makefile.am                           |   1 +
+ src/gallium/drivers/r300/Automake.inc             |   6 +-
+ src/gallium/drivers/r600/Automake.inc             |   6 +-
+ src/gallium/drivers/radeonsi/Automake.inc         |   6 +-
+ src/gallium/targets/pipe-loader/Makefile.am       |  12 +-
+ src/gallium/winsys/radeon/amdgpu/Android.mk       |  40 ++
+ src/gallium/winsys/radeon/amdgpu/Makefile.am      |  12 +
+ src/gallium/winsys/radeon/amdgpu/Makefile.sources |   8 +
+ src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c      | 643 ++++++++++++++++++++++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h      |  75 +++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c      | 578 +++++++++++++++++++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h      | 149 +++++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_public.h  |  14 +
+ src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c  | 491 +++++++++++++++++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h  |  80 +++
+ src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |   8 +
+ src/gallium/winsys/radeon/radeon_winsys.h         |   4 +
+ 18 files changed, 2129 insertions(+), 9 deletions(-)
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/Android.mk
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/Makefile.am
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/Makefile.sources
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_public.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h
+
+diff --git a/configure.ac b/configure.ac
+index 095e23e..f22975f 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -68,6 +68,7 @@ AC_SUBST([OSMESA_VERSION])
+ dnl Versions for external dependencies
+ LIBDRM_REQUIRED=2.4.38
+ LIBDRM_RADEON_REQUIRED=2.4.56
++LIBDRM_AMDGPU_REQUIRED=2.4.60
+ LIBDRM_INTEL_REQUIRED=2.4.60
+ LIBDRM_NVVIEUX_REQUIRED=2.4.33
+ LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41"
+@@ -2091,6 +2092,7 @@ if test -n "$with_gallium_drivers"; then
+         xr300)
+             HAVE_GALLIUM_R300=yes
+             PKG_CHECK_MODULES([RADEON], [libdrm_radeon >= $LIBDRM_RADEON_REQUIRED])
++            PKG_CHECK_MODULES([AMDGPU], [libdrm_amdgpu >= $LIBDRM_AMDGPU_REQUIRED])
+             gallium_require_drm "Gallium R300"
+             gallium_require_drm_loader
+             gallium_require_llvm "Gallium R300"
+@@ -2098,6 +2100,7 @@ if test -n "$with_gallium_drivers"; then
+         xr600)
+             HAVE_GALLIUM_R600=yes
+             PKG_CHECK_MODULES([RADEON], [libdrm_radeon >= $LIBDRM_RADEON_REQUIRED])
++            PKG_CHECK_MODULES([AMDGPU], [libdrm_amdgpu >= $LIBDRM_AMDGPU_REQUIRED])
+             gallium_require_drm "Gallium R600"
+             gallium_require_drm_loader
+             if test "x$enable_r600_llvm" = xyes -o "x$enable_opencl" = xyes; then
+@@ -2114,6 +2117,7 @@ if test -n "$with_gallium_drivers"; then
+         xradeonsi)
+             HAVE_GALLIUM_RADEONSI=yes
+             PKG_CHECK_MODULES([RADEON], [libdrm_radeon >= $LIBDRM_RADEON_REQUIRED])
++            PKG_CHECK_MODULES([AMDGPU], [libdrm_amdgpu >= $LIBDRM_AMDGPU_REQUIRED])
+             gallium_require_drm "radeonsi"
+             gallium_require_drm_loader
+             radeon_llvm_check "radeonsi"
+@@ -2384,6 +2388,7 @@ AC_CONFIG_FILES([Makefile
+ 		src/gallium/winsys/intel/drm/Makefile
+ 		src/gallium/winsys/nouveau/drm/Makefile
+ 		src/gallium/winsys/radeon/drm/Makefile
++		src/gallium/winsys/radeon/amdgpu/Makefile
+ 		src/gallium/winsys/svga/drm/Makefile
+ 		src/gallium/winsys/sw/dri/Makefile
+ 		src/gallium/winsys/sw/kms-dri/Makefile
+diff --git a/src/gallium/Makefile.am b/src/gallium/Makefile.am
+index ede6e21..fa526d4 100644
+--- a/src/gallium/Makefile.am
++++ b/src/gallium/Makefile.am
+@@ -63,6 +63,7 @@ endif
+ ## the radeon winsys - linked in by r300, r600 and radeonsi
+ if NEED_RADEON_DRM_WINSYS
+ SUBDIRS += winsys/radeon/drm
++SUBDIRS += winsys/radeon/amdgpu
+ endif
+ 
+ ## swrast/softpipe
+diff --git a/src/gallium/drivers/r300/Automake.inc b/src/gallium/drivers/r300/Automake.inc
+index 9334973..cfcd61c 100644
+--- a/src/gallium/drivers/r300/Automake.inc
++++ b/src/gallium/drivers/r300/Automake.inc
+@@ -5,9 +5,11 @@ TARGET_CPPFLAGS += -DGALLIUM_R300
+ TARGET_LIB_DEPS += \
+ 	$(top_builddir)/src/gallium/drivers/r300/libr300.la \
+ 	$(RADEON_LIBS) \
+-	$(INTEL_LIBS)
++	$(LIBDRM_LIBS) \
++	$(AMDGPU_LIBS)
+ 
+ TARGET_RADEON_WINSYS = \
+-	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la
++	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \
++	$(top_builddir)/src/gallium/winsys/radeon/amdgpu/libamdgpuwinsys.la
+ 
+ endif
+diff --git a/src/gallium/drivers/r600/Automake.inc b/src/gallium/drivers/r600/Automake.inc
+index 914eea3..2bb34b0 100644
+--- a/src/gallium/drivers/r600/Automake.inc
++++ b/src/gallium/drivers/r600/Automake.inc
+@@ -5,10 +5,12 @@ TARGET_CPPFLAGS += -DGALLIUM_R600
+ TARGET_LIB_DEPS += \
+ 	$(top_builddir)/src/gallium/drivers/r600/libr600.la \
+ 	$(RADEON_LIBS) \
+-	$(LIBDRM_LIBS)
++	$(LIBDRM_LIBS) \
++	$(AMDGPU_LIBS)
+ 
+ TARGET_RADEON_WINSYS = \
+-	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la
++	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \
++	$(top_builddir)/src/gallium/winsys/radeon/amdgpu/libamdgpuwinsys.la
+ 
+ TARGET_RADEON_COMMON = \
+ 	$(top_builddir)/src/gallium/drivers/radeon/libradeon.la
+diff --git a/src/gallium/drivers/radeonsi/Automake.inc b/src/gallium/drivers/radeonsi/Automake.inc
+index 8686fff..200a254 100644
+--- a/src/gallium/drivers/radeonsi/Automake.inc
++++ b/src/gallium/drivers/radeonsi/Automake.inc
+@@ -5,10 +5,12 @@ TARGET_CPPFLAGS += -DGALLIUM_RADEONSI
+ TARGET_LIB_DEPS += \
+ 	$(top_builddir)/src/gallium/drivers/radeonsi/libradeonsi.la \
+ 	$(RADEON_LIBS) \
+-	$(LIBDRM_LIBS)
++	$(LIBDRM_LIBS) \
++	$(AMDGPU_LIBS)
+ 
+ TARGET_RADEON_WINSYS = \
+-	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la
++	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \
++	$(top_builddir)/src/gallium/winsys/radeon/amdgpu/libamdgpuwinsys.la
+ 
+ TARGET_RADEON_COMMON = \
+ 	$(top_builddir)/src/gallium/drivers/radeon/libradeon.la
+diff --git a/src/gallium/targets/pipe-loader/Makefile.am b/src/gallium/targets/pipe-loader/Makefile.am
+index 967cdb7..3527090 100644
+--- a/src/gallium/targets/pipe-loader/Makefile.am
++++ b/src/gallium/targets/pipe-loader/Makefile.am
+@@ -124,9 +124,11 @@ nodist_EXTRA_pipe_r300_la_SOURCES = dummy.cpp
+ pipe_r300_la_LIBADD = \
+ 	$(PIPE_LIBS) \
+ 	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \
++	$(top_builddir)/src/gallium/winsys/radeon/amdgpu/libamdgpuwinsys.la \
+ 	$(top_builddir)/src/gallium/drivers/r300/libr300.la \
+ 	$(LIBDRM_LIBS) \
+-	$(RADEON_LIBS)
++	$(RADEON_LIBS) \
++	$(AMDGPU_LIBS)
+ 
+ endif
+ 
+@@ -138,10 +140,12 @@ nodist_EXTRA_pipe_r600_la_SOURCES = dummy.cpp
+ pipe_r600_la_LIBADD = \
+ 	$(PIPE_LIBS) \
+ 	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \
++	$(top_builddir)/src/gallium/winsys/radeon/amdgpu/libamdgpuwinsys.la \
+ 	$(top_builddir)/src/gallium/drivers/radeon/libradeon.la \
+ 	$(top_builddir)/src/gallium/drivers/r600/libr600.la \
+ 	$(LIBDRM_LIBS) \
+-	$(RADEON_LIBS)
++	$(RADEON_LIBS) \
++	$(AMDGPU_LIBS)
+ 
+ endif
+ 
+@@ -153,10 +157,12 @@ nodist_EXTRA_pipe_radeonsi_la_SOURCES = dummy.cpp
+ pipe_radeonsi_la_LIBADD = \
+ 	$(PIPE_LIBS) \
+ 	$(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \
++	$(top_builddir)/src/gallium/winsys/radeon/amdgpu/libamdgpuwinsys.la \
+ 	$(top_builddir)/src/gallium/drivers/radeon/libradeon.la \
+ 	$(top_builddir)/src/gallium/drivers/radeonsi/libradeonsi.la \
+ 	$(LIBDRM_LIBS) \
+-	$(RADEON_LIBS)
++	$(RADEON_LIBS) \
++	$(AMDGPU_LIBS)
+ 
+ endif
+ 
+diff --git a/src/gallium/winsys/radeon/amdgpu/Android.mk b/src/gallium/winsys/radeon/amdgpu/Android.mk
+new file mode 100644
+index 0000000..a10312f
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/Android.mk
+@@ -0,0 +1,40 @@
++# Mesa 3-D graphics library
++#
++# Copyright (C) 2011 Chia-I Wu <olvaffe@gmail.com>
++# Copyright (C) 2011 LunarG Inc.
++#
++# Permission is hereby granted, free of charge, to any person obtaining a
++# copy of this software and associated documentation files (the "Software"),
++# to deal in the Software without restriction, including without limitation
++# the rights to use, copy, modify, merge, publish, distribute, sublicense,
++# and/or sell copies of the Software, and to permit persons to whom the
++# Software is furnished to do so, subject to the following conditions:
++#
++# The above copyright notice and this permission notice shall be included
++# in all copies or substantial portions of the Software.
++#
++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++# DEALINGS IN THE SOFTWARE.
++
++LOCAL_PATH := $(call my-dir)
++
++# get C_SOURCES
++include $(LOCAL_PATH)/Makefile.sources
++
++include $(CLEAR_VARS)
++
++LOCAL_SRC_FILES := $(C_SOURCES)
++
++LOCAL_C_INCLUDES := \
++	$(DRM_TOP) \
++	$(DRM_TOP)/include/drm
++
++LOCAL_MODULE := libmesa_winsys_amdgpu
++
++include $(GALLIUM_COMMON_MK)
++include $(BUILD_STATIC_LIBRARY)
+diff --git a/src/gallium/winsys/radeon/amdgpu/Makefile.am b/src/gallium/winsys/radeon/amdgpu/Makefile.am
+new file mode 100644
+index 0000000..80ecb75
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/Makefile.am
+@@ -0,0 +1,12 @@
++include Makefile.sources
++include $(top_srcdir)/src/gallium/Automake.inc
++
++AM_CFLAGS = \
++	$(GALLIUM_WINSYS_CFLAGS) \
++	$(AMDGPU_CFLAGS)
++
++AM_CXXFLAGS = $(AM_CFLAGS)
++
++noinst_LTLIBRARIES = libamdgpuwinsys.la
++
++libamdgpuwinsys_la_SOURCES = $(C_SOURCES)
+diff --git a/src/gallium/winsys/radeon/amdgpu/Makefile.sources b/src/gallium/winsys/radeon/amdgpu/Makefile.sources
+new file mode 100644
+index 0000000..0f55010
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/Makefile.sources
+@@ -0,0 +1,8 @@
++C_SOURCES := \
++	amdgpu_bo.c \
++	amdgpu_bo.h \
++	amdgpu_cs.c \
++	amdgpu_cs.h \
++	amdgpu_public.h \
++	amdgpu_winsys.c \
++	amdgpu_winsys.h
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c b/src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c
+new file mode 100644
+index 0000000..de9548e
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c
+@@ -0,0 +1,643 @@
++/*
++ * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++#include "amdgpu_cs.h"
++
++#include "os/os_time.h"
++#include "state_tracker/drm_driver.h"
++#include <amdgpu_drm.h>
++#include <xf86drm.h>
++#include <stdio.h>
++
++static const struct pb_vtbl amdgpu_winsys_bo_vtbl;
++
++static INLINE struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer *bo)
++{
++   assert(bo->vtbl == &amdgpu_winsys_bo_vtbl);
++   return (struct amdgpu_winsys_bo *)bo;
++}
++
++struct amdgpu_bomgr {
++   struct pb_manager base;
++   struct amdgpu_winsys *rws;
++};
++
++static struct amdgpu_winsys *get_winsys(struct pb_manager *mgr)
++{
++   return ((struct amdgpu_bomgr*)mgr)->rws;
++}
++
++static struct amdgpu_winsys_bo *get_amdgpu_winsys_bo(struct pb_buffer *_buf)
++{
++   struct amdgpu_winsys_bo *bo = NULL;
++
++   if (_buf->vtbl == &amdgpu_winsys_bo_vtbl) {
++      bo = amdgpu_winsys_bo(_buf);
++   } else {
++      struct pb_buffer *base_buf;
++      pb_size offset;
++      pb_get_base_buffer(_buf, &base_buf, &offset);
++
++      if (base_buf->vtbl == &amdgpu_winsys_bo_vtbl)
++         bo = amdgpu_winsys_bo(base_buf);
++   }
++
++   return bo;
++}
++
++static void amdgpu_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
++{
++   struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
++   struct radeon_winsys *ws = &bo->rws->base;
++
++   while (p_atomic_read(&bo->num_active_ioctls)) {
++      sched_yield();
++   }
++
++   if (bo->fence) {
++      ws->fence_wait(ws, bo->fence, PIPE_TIMEOUT_INFINITE);
++   }
++}
++
++static boolean amdgpu_bo_is_busy(struct pb_buffer *_buf,
++                                 enum radeon_bo_usage usage)
++{
++   struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
++   struct radeon_winsys *ws = &bo->rws->base;
++
++   if (p_atomic_read(&bo->num_active_ioctls)) {
++      return TRUE;
++   }
++
++   return bo->fence && !ws->fence_wait(ws, bo->fence, 0);
++}
++
++static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
++      struct radeon_winsys_cs_handle *buf)
++{
++   return ((struct amdgpu_winsys_bo*)buf)->initial_domain;
++}
++
++static void amdgpu_bo_destroy(struct pb_buffer *_buf)
++{
++   struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
++
++   amdgpu_bo_free(bo->bo);
++   amdgpu_fence_reference(&bo->fence, NULL);
++
++   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
++      bo->rws->allocated_vram -= align(bo->base.size, 4096);
++   else if (bo->initial_domain & RADEON_DOMAIN_GTT)
++      bo->rws->allocated_gtt -= align(bo->base.size, 4096);
++   FREE(bo);
++}
++
++static void *amdgpu_bo_map(struct radeon_winsys_cs_handle *buf,
++                           struct radeon_winsys_cs *rcs,
++                           enum pipe_transfer_usage usage)
++{
++   struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
++   struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
++   int r;
++   void *cpu = NULL;
++
++   /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
++   if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
++      /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
++      if (usage & PIPE_TRANSFER_DONTBLOCK) {
++         if (!(usage & PIPE_TRANSFER_WRITE)) {
++            /* Mapping for read.
++             *
++             * Since we are mapping for read, we don't need to wait
++             * if the GPU is using the buffer for read too
++             * (neither one is changing it).
++             *
++             * Only check whether the buffer is being used for write. */
++            if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,
++                                                               RADEON_USAGE_WRITE)) {
++               cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC, NULL);
++               return NULL;
++            }
++
++            if (amdgpu_bo_is_busy((struct pb_buffer*)bo,
++                                  RADEON_USAGE_WRITE)) {
++               return NULL;
++            }
++         } else {
++            if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo)) {
++               cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC, NULL);
++               return NULL;
++            }
++
++            if (amdgpu_bo_is_busy((struct pb_buffer*)bo,
++                                  RADEON_USAGE_READWRITE)) {
++               return NULL;
++            }
++         }
++      } else {
++         uint64_t time = os_time_get_nano();
++
++         if (!(usage & PIPE_TRANSFER_WRITE)) {
++            /* Mapping for read.
++             *
++             * Since we are mapping for read, we don't need to wait
++             * if the GPU is using the buffer for read too
++             * (neither one is changing it).
++             *
++             * Only check whether the buffer is being used for write. */
++            if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,
++                                                               RADEON_USAGE_WRITE)) {
++               cs->flush_cs(cs->flush_data, 0, NULL);
++            }
++            amdgpu_bo_wait((struct pb_buffer*)bo,
++                           RADEON_USAGE_WRITE);
++         } else {
++            /* Mapping for write. */
++            if (cs) {
++               if (amdgpu_bo_is_referenced_by_cs(cs, bo)) {
++                  cs->flush_cs(cs->flush_data, 0, NULL);
++               } else {
++                  /* Try to avoid busy-waiting in radeon_bo_wait. */
++                  if (p_atomic_read(&bo->num_active_ioctls))
++                     amdgpu_cs_sync_flush(rcs);
++               }
++            }
++
++            amdgpu_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
++         }
++
++         bo->rws->buffer_wait_time += os_time_get_nano() - time;
++      }
++   }
++
++   r = amdgpu_bo_cpu_map(bo->bo, &cpu);
++   return r ? NULL : cpu;
++}
++
++static void amdgpu_bo_unmap(struct radeon_winsys_cs_handle *buf)
++{
++   struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
++
++   amdgpu_bo_cpu_unmap(bo->bo);
++}
++
++static void amdgpu_bo_get_base_buffer(struct pb_buffer *buf,
++                                      struct pb_buffer **base_buf,
++                                      unsigned *offset)
++{
++   *base_buf = buf;
++   *offset = 0;
++}
++
++static enum pipe_error amdgpu_bo_validate(struct pb_buffer *_buf,
++                                          struct pb_validate *vl,
++                                          unsigned flags)
++{
++   /* Always pinned */
++   return PIPE_OK;
++}
++
++static void amdgpu_bo_fence(struct pb_buffer *buf,
++                            struct pipe_fence_handle *fence)
++{
++}
++
++static const struct pb_vtbl amdgpu_winsys_bo_vtbl = {
++   amdgpu_bo_destroy,
++   NULL, /* never called */
++   NULL, /* never called */
++   amdgpu_bo_validate,
++   amdgpu_bo_fence,
++   amdgpu_bo_get_base_buffer,
++};
++
++static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
++                                                pb_size size,
++                                                const struct pb_desc *desc)
++{
++   struct amdgpu_winsys *rws = get_winsys(_mgr);
++   struct amdgpu_bo_desc *rdesc = (struct amdgpu_bo_desc*)desc;
++   struct amdgpu_bo_alloc_request request = {0};
++   struct amdgpu_bo_alloc_result result = {0};
++   struct amdgpu_winsys_bo *bo;
++   int r;
++
++   assert(rdesc->initial_domain & RADEON_DOMAIN_VRAM_GTT);
++
++   request.alloc_size = size;
++   request.phys_alignment = desc->alignment;
++
++   if (rdesc->initial_domain & RADEON_DOMAIN_VRAM) {
++      request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
++      if (rdesc->flags & RADEON_FLAG_CPU_ACCESS)
++         request.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
++   }
++   if (rdesc->initial_domain & RADEON_DOMAIN_GTT) {
++      request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
++      if (rdesc->flags & RADEON_FLAG_GTT_WC)
++         request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_WC;
++   }
++
++   r = amdgpu_bo_alloc(rws->dev, &request, &result);
++   if (r) {
++      fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
++      fprintf(stderr, "amdgpu:    size      : %d bytes\n", size);
++      fprintf(stderr, "amdgpu:    alignment : %d bytes\n", desc->alignment);
++      fprintf(stderr, "amdgpu:    domains   : %d\n", rdesc->initial_domain);
++      return NULL;
++   }
++
++   bo = CALLOC_STRUCT(amdgpu_winsys_bo);
++   if (!bo)
++      return NULL;
++
++   pipe_reference_init(&bo->base.reference, 1);
++   bo->base.alignment = desc->alignment;
++   bo->base.usage = desc->usage;
++   bo->base.size = size;
++   bo->base.vtbl = &amdgpu_winsys_bo_vtbl;
++   bo->rws = rws;
++   bo->bo = result.buf_handle;
++   bo->va = result.virtual_mc_base_address;
++   bo->initial_domain = rdesc->initial_domain;
++
++   if (amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->handle)) {
++      amdgpu_bo_free(bo->bo);
++      FREE(bo);
++      return NULL;
++   }
++
++   if (rdesc->initial_domain & RADEON_DOMAIN_VRAM)
++      rws->allocated_vram += align(size, 4096);
++   else if (rdesc->initial_domain & RADEON_DOMAIN_GTT)
++      rws->allocated_gtt += align(size, 4096);
++
++   return &bo->base;
++}
++
++static void amdgpu_bomgr_flush(struct pb_manager *mgr)
++{
++   /* NOP */
++}
++
++/* This is for the cache bufmgr. */
++static boolean amdgpu_bomgr_is_buffer_busy(struct pb_manager *_mgr,
++                                           struct pb_buffer *_buf)
++{
++   struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
++
++   if (amdgpu_bo_is_referenced_by_any_cs(bo)) {
++      return TRUE;
++   }
++
++   if (amdgpu_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
++      return TRUE;
++   }
++
++   return FALSE;
++}
++
++static void amdgpu_bomgr_destroy(struct pb_manager *mgr)
++{
++   FREE(mgr);
++}
++
++struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws)
++{
++   struct amdgpu_bomgr *mgr;
++
++   mgr = CALLOC_STRUCT(amdgpu_bomgr);
++   if (!mgr)
++      return NULL;
++
++   mgr->base.destroy = amdgpu_bomgr_destroy;
++   mgr->base.create_buffer = amdgpu_bomgr_create_bo;
++   mgr->base.flush = amdgpu_bomgr_flush;
++   mgr->base.is_buffer_busy = amdgpu_bomgr_is_buffer_busy;
++
++   mgr->rws = rws;
++   return &mgr->base;
++}
++
++static unsigned eg_tile_split(unsigned tile_split)
++{
++   switch (tile_split) {
++   case 0:     tile_split = 64;    break;
++   case 1:     tile_split = 128;   break;
++   case 2:     tile_split = 256;   break;
++   case 3:     tile_split = 512;   break;
++   default:
++   case 4:     tile_split = 1024;  break;
++   case 5:     tile_split = 2048;  break;
++   case 6:     tile_split = 4096;  break;
++   }
++   return tile_split;
++}
++
++static unsigned eg_tile_split_rev(unsigned eg_tile_split)
++{
++   switch (eg_tile_split) {
++   case 64:    return 0;
++   case 128:   return 1;
++   case 256:   return 2;
++   case 512:   return 3;
++   default:
++   case 1024:  return 4;
++   case 2048:  return 5;
++   case 4096:  return 6;
++   }
++}
++
++static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
++                                 enum radeon_bo_layout *microtiled,
++                                 enum radeon_bo_layout *macrotiled,
++                                 unsigned *bankw, unsigned *bankh,
++                                 unsigned *tile_split,
++                                 unsigned *stencil_tile_split,
++                                 unsigned *mtilea,
++                                 bool *scanout)
++{
++   struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
++   struct amdgpu_bo_info info = {0};
++   uint32_t tiling_flags;
++   int r;
++
++   r = amdgpu_bo_query_info(bo->bo, &info);
++   if (r)
++      return;
++
++   tiling_flags = info.metadata.tiling_info;
++
++   *microtiled = RADEON_LAYOUT_LINEAR;
++   *macrotiled = RADEON_LAYOUT_LINEAR;
++   if (tiling_flags & AMDGPU_TILING_MICRO)
++      *microtiled = RADEON_LAYOUT_TILED;
++   else if (tiling_flags & AMDGPU_TILING_MICRO_SQUARE)
++      *microtiled = RADEON_LAYOUT_SQUARETILED;
++
++   if (tiling_flags & AMDGPU_TILING_MACRO)
++      *macrotiled = RADEON_LAYOUT_TILED;
++   if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
++      *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK;
++      *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK;
++      *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK;
++      *stencil_tile_split = (tiling_flags >> AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK;
++      *mtilea = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
++      *tile_split = eg_tile_split(*tile_split);
++   }
++   if (scanout)
++      *scanout = !(tiling_flags & AMDGPU_TILING_R600_NO_SCANOUT);
++}
++
++static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
++                                 struct radeon_winsys_cs *rcs,
++                                 enum radeon_bo_layout microtiled,
++                                 enum radeon_bo_layout macrotiled,
++                                 unsigned bankw, unsigned bankh,
++                                 unsigned tile_split,
++                                 unsigned stencil_tile_split,
++                                 unsigned mtilea,
++                                 uint32_t pitch,
++                                 bool scanout)
++{
++   struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++   struct amdgpu_bo_metadata metadata = {0};
++   uint32_t tiling_flags = 0;
++
++
++   /* Tiling determines how DRM treats the buffer data.
++     * We must flush CS when changing it if the buffer is referenced. */
++   if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo)) {
++      cs->flush_cs(cs->flush_data, 0, NULL);
++   }
++
++   while (p_atomic_read(&bo->num_active_ioctls)) {
++      sched_yield();
++   }
++
++   if (microtiled == RADEON_LAYOUT_TILED)
++      tiling_flags |= AMDGPU_TILING_MICRO;
++   else if (microtiled == RADEON_LAYOUT_SQUARETILED)
++      tiling_flags |= AMDGPU_TILING_MICRO_SQUARE;
++
++   if (macrotiled == RADEON_LAYOUT_TILED)
++      tiling_flags |= AMDGPU_TILING_MACRO;
++
++   tiling_flags |= (bankw & AMDGPU_TILING_EG_BANKW_MASK) <<
++                   AMDGPU_TILING_EG_BANKW_SHIFT;
++   tiling_flags |= (bankh & AMDGPU_TILING_EG_BANKH_MASK) <<
++                   AMDGPU_TILING_EG_BANKH_SHIFT;
++   if (tile_split) {
++      tiling_flags |= (eg_tile_split_rev(tile_split) &
++                       AMDGPU_TILING_EG_TILE_SPLIT_MASK) <<
++                      AMDGPU_TILING_EG_TILE_SPLIT_SHIFT;
++   }
++   tiling_flags |= (stencil_tile_split &
++                    AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
++                   AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
++   tiling_flags |= (mtilea & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
++                   AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
++
++   if (!scanout)
++      tiling_flags |= AMDGPU_TILING_R600_NO_SCANOUT;
++
++   metadata.tiling_info = tiling_flags;
++
++   amdgpu_bo_set_metadata(bo->bo, &metadata);
++}
++
++static struct radeon_winsys_cs_handle *amdgpu_get_cs_handle(struct pb_buffer *_buf)
++{
++   /* return a direct pointer to amdgpu_winsys_bo. */
++   return (struct radeon_winsys_cs_handle*)get_amdgpu_winsys_bo(_buf);
++}
++
++static struct pb_buffer *
++amdgpu_bo_create(struct radeon_winsys *rws,
++                 unsigned size,
++                 unsigned alignment,
++                 boolean use_reusable_pool,
++                 enum radeon_bo_domain domain,
++                 enum radeon_bo_flag flags)
++{
++   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
++   struct amdgpu_bo_desc desc;
++   struct pb_manager *provider;
++   struct pb_buffer *buffer;
++
++   memset(&desc, 0, sizeof(desc));
++   desc.base.alignment = alignment;
++
++   /* Only set one usage bit each for domains and flags, or the cache manager
++    * might consider different sets of domains / flags compatible
++    */
++   if (domain == RADEON_DOMAIN_VRAM_GTT)
++      desc.base.usage = 1 << 2;
++   else
++      desc.base.usage = domain >> 1;
++   assert(flags < sizeof(desc.base.usage) * 8 - 3);
++   desc.base.usage |= 1 << (flags + 3);
++
++   desc.initial_domain = domain;
++   desc.flags = flags;
++
++   /* Assign a buffer manager. */
++   if (use_reusable_pool)
++      provider = ws->cman;
++   else
++      provider = ws->kman;
++
++   buffer = provider->create_buffer(provider, size, &desc.base);
++   if (!buffer)
++      return NULL;
++
++   return (struct pb_buffer*)buffer;
++}
++
++static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
++                                               struct winsys_handle *whandle,
++                                               unsigned *stride)
++{
++   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
++   struct amdgpu_winsys_bo *bo;
++   enum amdgpu_bo_handle_type type;
++   struct amdgpu_bo_import_result result = {0};
++   struct amdgpu_bo_info info = {0};
++   enum radeon_bo_domain initial = 0;
++   int r;
++
++   switch (whandle->type) {
++   case DRM_API_HANDLE_TYPE_SHARED:
++      type = amdgpu_bo_handle_type_gem_flink_name;
++      break;
++   case DRM_API_HANDLE_TYPE_FD:
++      type = amdgpu_bo_handle_type_dma_buf_fd;
++      break;
++   default:
++      return NULL;
++   }
++
++   r = amdgpu_bo_import(ws->dev, type, whandle->handle, &result);
++   if (r)
++      return NULL;
++
++   /* Get initial domains. */
++   r = amdgpu_bo_query_info(result.buf_handle, &info);
++   if (r) {
++      amdgpu_bo_free(result.buf_handle);
++      return NULL;
++   }
++
++   if (info.preferred_heap & AMDGPU_GEM_DOMAIN_VRAM)
++      initial |= RADEON_DOMAIN_VRAM;
++   if (info.preferred_heap & AMDGPU_GEM_DOMAIN_GTT)
++      initial |= RADEON_DOMAIN_GTT;
++
++   /* Initialize the structure. */
++   bo = CALLOC_STRUCT(amdgpu_winsys_bo);
++   if (!bo) {
++      amdgpu_bo_free(result.buf_handle);
++      return NULL;
++   }
++
++   pipe_reference_init(&bo->base.reference, 1);
++   bo->base.alignment = info.phys_alignment;
++   bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
++   bo->bo = result.buf_handle;
++   bo->base.size = result.alloc_size;
++   bo->base.vtbl = &amdgpu_winsys_bo_vtbl;
++   bo->rws = ws;
++   bo->va = result.virtual_mc_base_address;
++   bo->initial_domain = initial;
++
++   if (amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->handle)) {
++      amdgpu_bo_free(bo->bo);
++      FREE(bo);
++      return NULL;
++   }
++
++   if (stride)
++      *stride = whandle->stride;
++
++   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
++      ws->allocated_vram += align(bo->base.size, 4096);
++   else if (bo->initial_domain & RADEON_DOMAIN_GTT)
++      ws->allocated_gtt += align(bo->base.size, 4096);
++
++   return &bo->base;
++}
++
++static boolean amdgpu_bo_get_handle(struct pb_buffer *buffer,
++                                    unsigned stride,
++                                    struct winsys_handle *whandle)
++{
++   struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(buffer);
++   enum amdgpu_bo_handle_type type;
++   int r;
++
++   switch (whandle->type) {
++   case DRM_API_HANDLE_TYPE_SHARED:
++      type = amdgpu_bo_handle_type_gem_flink_name;
++      break;
++   case DRM_API_HANDLE_TYPE_FD:
++      type = amdgpu_bo_handle_type_dma_buf_fd;
++      break;
++   case DRM_API_HANDLE_TYPE_KMS:
++      type = amdgpu_bo_handle_type_kms;
++      break;
++   default:
++      return FALSE;
++   }
++
++   r = amdgpu_bo_export(bo->bo, type, &whandle->handle);
++   if (r)
++      return FALSE;
++
++   whandle->stride = stride;
++   return TRUE;
++}
++
++static uint64_t amdgpu_bo_get_va(struct radeon_winsys_cs_handle *buf)
++{
++   return ((struct amdgpu_winsys_bo*)buf)->va;
++}
++
++void amdgpu_bomgr_init_functions(struct amdgpu_winsys *ws)
++{
++   ws->base.buffer_get_cs_handle = amdgpu_get_cs_handle;
++   ws->base.buffer_set_tiling = amdgpu_bo_set_tiling;
++   ws->base.buffer_get_tiling = amdgpu_bo_get_tiling;
++   ws->base.buffer_map = amdgpu_bo_map;
++   ws->base.buffer_unmap = amdgpu_bo_unmap;
++   ws->base.buffer_wait = amdgpu_bo_wait;
++   ws->base.buffer_is_busy = amdgpu_bo_is_busy;
++   ws->base.buffer_create = amdgpu_bo_create;
++   ws->base.buffer_from_handle = amdgpu_bo_from_handle;
++   ws->base.buffer_get_handle = amdgpu_bo_get_handle;
++   ws->base.buffer_get_virtual_address = amdgpu_bo_get_va;
++   ws->base.buffer_get_initial_domain = amdgpu_bo_get_initial_domain;
++}
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h b/src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h
+new file mode 100644
+index 0000000..ccf98b5
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h
+@@ -0,0 +1,75 @@
++/*
++ * Copyright © 2008 Jérôme Glisse
++ * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++/*
++ * Authors:
++ *      Jérôme Glisse <glisse@freedesktop.org>
++ *      Marek Olšák <maraeo@gmail.com>
++ */
++#ifndef AMDGPU_DRM_BO_H
++#define AMDGPU_DRM_BO_H
++
++#include "amdgpu_winsys.h"
++#include "pipebuffer/pb_bufmgr.h"
++
++struct amdgpu_bo_desc {
++   struct pb_desc base;
++
++   enum radeon_bo_domain initial_domain;
++   unsigned flags;
++};
++
++struct amdgpu_winsys_bo {
++   struct pb_buffer base;
++
++   struct amdgpu_winsys *rws;
++
++   amdgpu_bo_handle bo;
++   uint32_t handle;
++   uint64_t va;
++   enum radeon_bo_domain initial_domain;
++
++   /* how many command streams is this bo referenced in? */
++   int num_cs_references;
++
++   /* how many command streams, which are being emitted in a separate
++    * thread, is this bo referenced in? */
++   int num_active_ioctls;
++
++   struct pipe_fence_handle *fence; /* for buffer_wait & buffer_is_busy */
++};
++
++struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws);
++void amdgpu_bomgr_init_functions(struct amdgpu_winsys *ws);
++
++static INLINE
++void amdgpu_winsys_bo_reference(struct amdgpu_winsys_bo **dst,
++                                struct amdgpu_winsys_bo *src)
++{
++   pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src);
++}
++
++#endif
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c b/src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c
+new file mode 100644
+index 0000000..aee7ff3
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c
+@@ -0,0 +1,578 @@
++/*
++ * Copyright © 2008 Jérôme Glisse
++ * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++/*
++ * Authors:
++ *      Marek Olšák <maraeo@gmail.com>
++ */
++
++#include "amdgpu_cs.h"
++#include "os/os_time.h"
++#include <stdio.h>
++#include <amdgpu_drm.h>
++
++
++/* FENCES */
++
++static struct pipe_fence_handle *
++amdgpu_fence_create(unsigned ip, uint32_t instance)
++{
++   struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
++
++   fence->reference.count = 1;
++   fence->ip_type = ip;
++   fence->ring = instance;
++   fence->submission_in_progress = true;
++   return (struct pipe_fence_handle *)fence;
++}
++
++static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
++                                   uint64_t fence_id)
++{
++   struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
++
++   rfence->fence = fence_id;
++   rfence->submission_in_progress = false;
++}
++
++static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
++{
++   struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
++
++   rfence->signalled = true;
++}
++
++static bool amdgpu_fence_wait(struct radeon_winsys *rws,
++                              struct pipe_fence_handle *fence,
++                              uint64_t timeout)
++{
++   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
++   struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
++   struct amdgpu_cs_query_fence query = {0};
++   uint32_t expired;
++   int r;
++
++   /* XXX Access to rfence->signalled is racy here. */
++   if (rfence->signalled)
++      return true;
++
++   /* The fence may not have a number assigned if its IB is being
++    * submitted in the other thread right now. Wait until the submission
++    * is done. */
++   if (rfence->submission_in_progress) {
++      if (!timeout) {
++         return FALSE;
++      } else if (timeout == PIPE_TIMEOUT_INFINITE) {
++         while (rfence->submission_in_progress)
++            sched_yield();
++      } else {
++         int64_t start_time = os_time_get_nano();
++         int64_t elapsed_time = 0;
++
++         while (rfence->submission_in_progress) {
++            elapsed_time = os_time_get_nano() - start_time;
++            if (elapsed_time >= timeout) {
++               return FALSE;
++            }
++            sched_yield();
++         }
++         timeout -= elapsed_time;
++      }
++   }
++
++   /* Now use the libdrm query. */
++   query.timeout_ns = timeout;
++   query.fence = rfence->fence;
++   query.context = ws->ctx;
++   query.ip_type = rfence->ip_type;
++   query.ip_instance = 0;
++   query.ring = rfence->ring;
++
++   r = amdgpu_cs_query_fence_status(ws->dev, &query, &expired);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
++      return FALSE;
++   }
++
++   rfence->signalled = expired != 0;
++   return rfence->signalled;
++}
++
++/* COMMAND SUBMISSION */
++
++static bool amdgpu_get_new_ib(struct amdgpu_cs *cs)
++{
++   struct amdgpu_cs_context *cur_cs = cs->csc;
++   struct amdgpu_winsys *ws = cs->ws;
++   struct amdgpu_cs_ib_alloc_result ib;
++   int r;
++
++   r = amdgpu_cs_alloc_ib(ws->dev, ws->ctx, amdgpu_cs_ib_size_64K, &ib);
++   if (r)
++      return false;
++
++   cs->base.buf = ib.cpu;
++   cs->base.cdw = 0;
++
++   cur_cs->ib.ib_handle = ib.handle;
++   return true;
++}
++
++static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *csc)
++{
++   int i;
++
++   csc->request.number_of_ibs = 1;
++   csc->request.ibs = &csc->ib;
++
++   csc->max_num_buffers = 512;
++   csc->buffers = (struct amdgpu_cs_buffer*)
++                  CALLOC(1, csc->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
++   if (!csc->buffers) {
++      return FALSE;
++   }
++
++   csc->handles = CALLOC(1, csc->max_num_buffers * sizeof(amdgpu_bo_handle));
++   if (!csc->handles) {
++      FREE(csc->buffers);
++      return FALSE;
++   }
++
++   csc->flags = CALLOC(1, csc->max_num_buffers);
++   if (!csc->flags) {
++      FREE(csc->handles);
++      FREE(csc->buffers);
++      return FALSE;
++   }
++
++   for (i = 0; i < Elements(csc->buffer_indices_hashlist); i++) {
++      csc->buffer_indices_hashlist[i] = -1;
++   }
++   return TRUE;
++}
++
++static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *csc)
++{
++   unsigned i;
++
++   for (i = 0; i < csc->num_buffers; i++) {
++      p_atomic_dec(&csc->buffers[i].bo->num_cs_references);
++      amdgpu_winsys_bo_reference(&csc->buffers[i].bo, NULL);
++      csc->handles[i] = NULL;
++      csc->flags[i] = 0;
++   }
++
++   csc->num_buffers = 0;
++   csc->used_gart = 0;
++   csc->used_vram = 0;
++   amdgpu_fence_reference(&csc->fence, NULL);
++
++   for (i = 0; i < Elements(csc->buffer_indices_hashlist); i++) {
++      csc->buffer_indices_hashlist[i] = -1;
++   }
++}
++
++static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *csc)
++{
++   amdgpu_cs_context_cleanup(csc);
++   FREE(csc->flags);
++   FREE(csc->buffers);
++   FREE(csc->handles);
++}
++
++
++static struct radeon_winsys_cs *
++amdgpu_cs_create(struct radeon_winsys *rws,
++                 enum ring_type ring_type,
++                 void (*flush)(void *ctx, unsigned flags,
++                               struct pipe_fence_handle **fence),
++                 void *flush_ctx,
++                 struct radeon_winsys_cs_handle *trace_buf)
++{
++   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
++   struct amdgpu_cs *cs;
++
++   cs = CALLOC_STRUCT(amdgpu_cs);
++   if (!cs) {
++      return NULL;
++   }
++
++   pipe_semaphore_init(&cs->flush_completed, 1);
++
++   cs->ws = ws;
++   cs->flush_cs = flush;
++   cs->flush_data = flush_ctx;
++
++   if (!amdgpu_init_cs_context(&cs->csc1)) {
++      FREE(cs);
++      return NULL;
++   }
++   if (!amdgpu_init_cs_context(&cs->csc2)) {
++      amdgpu_destroy_cs_context(&cs->csc1);
++      FREE(cs);
++      return NULL;
++   }
++
++   /* Set the first command buffer as current. */
++   cs->csc = &cs->csc1;
++   cs->cst = &cs->csc2;
++   cs->base.ring_type = ring_type;
++
++   if (!amdgpu_get_new_ib(cs)) {
++      amdgpu_destroy_cs_context(&cs->csc2);
++      amdgpu_destroy_cs_context(&cs->csc1);
++      FREE(cs);
++      return NULL;
++   }
++
++   p_atomic_inc(&ws->num_cs);
++   return &cs->base;
++}
++
++#define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
++
++int amdgpu_get_reloc(struct amdgpu_cs_context *csc, struct amdgpu_winsys_bo *bo)
++{
++   unsigned hash = bo->handle & (Elements(csc->buffer_indices_hashlist)-1);
++   int i = csc->buffer_indices_hashlist[hash];
++
++   /* not found or found */
++   if (i == -1 || csc->buffers[i].bo == bo)
++      return i;
++
++   /* Hash collision, look for the BO in the list of relocs linearly. */
++   for (i = csc->num_buffers - 1; i >= 0; i--) {
++      if (csc->buffers[i].bo == bo) {
++         /* Put this reloc in the hash list.
++          * This will prevent additional hash collisions if there are
++          * several consecutive get_reloc calls for the same buffer.
++          *
++          * Example: Assuming buffers A,B,C collide in the hash list,
++          * the following sequence of relocs:
++          *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
++          * will collide here: ^ and here:   ^,
++          * meaning that we should get very few collisions in the end. */
++         csc->buffer_indices_hashlist[hash] = i;
++         return i;
++      }
++   }
++   return -1;
++}
++
++static unsigned amdgpu_add_reloc(struct amdgpu_cs *cs,
++                                 struct amdgpu_winsys_bo *bo,
++                                 enum radeon_bo_usage usage,
++                                 enum radeon_bo_domain domains,
++                                 unsigned priority,
++                                 enum radeon_bo_domain *added_domains)
++{
++   struct amdgpu_cs_context *csc = cs->csc;
++   struct amdgpu_cs_buffer *reloc;
++   unsigned hash = bo->handle & (Elements(csc->buffer_indices_hashlist)-1);
++   int i = -1;
++
++   priority = MIN2(priority, 15);
++   *added_domains = 0;
++
++   i = amdgpu_get_reloc(csc, bo);
++
++   if (i >= 0) {
++      reloc = &csc->buffers[i];
++      reloc->usage |= usage;
++      *added_domains = domains & ~reloc->domains;
++      reloc->domains |= domains;
++      csc->flags[i] = MAX2(csc->flags[i], priority);
++      return i;
++   }
++
++   /* New relocation, check if the backing array is large enough. */
++   if (csc->num_buffers >= csc->max_num_buffers) {
++      uint32_t size;
++      csc->max_num_buffers += 10;
++
++      size = csc->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
++      csc->buffers = realloc(csc->buffers, size);
++
++      size = csc->max_num_buffers * sizeof(amdgpu_bo_handle);
++      csc->handles = realloc(csc->handles, size);
++
++      csc->flags = realloc(csc->flags, csc->max_num_buffers);
++   }
++
++   /* Initialize the new relocation. */
++   csc->buffers[csc->num_buffers].bo = NULL;
++   amdgpu_winsys_bo_reference(&csc->buffers[csc->num_buffers].bo, bo);
++   csc->handles[csc->num_buffers] = bo->bo;
++   csc->flags[csc->num_buffers] = priority;
++   p_atomic_inc(&bo->num_cs_references);
++   reloc = &csc->buffers[csc->num_buffers];
++   reloc->bo = bo;
++   reloc->usage = usage;
++   reloc->domains = domains;
++
++   csc->buffer_indices_hashlist[hash] = csc->num_buffers;
++
++   *added_domains = domains;
++   return csc->num_buffers++;
++}
++
++static unsigned amdgpu_cs_add_reloc(struct radeon_winsys_cs *rcs,
++                                    struct radeon_winsys_cs_handle *buf,
++                                    enum radeon_bo_usage usage,
++                                    enum radeon_bo_domain domains,
++                                    enum radeon_bo_priority priority)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++   struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
++   enum radeon_bo_domain added_domains;
++   unsigned index = amdgpu_add_reloc(cs, bo, usage, domains, priority, &added_domains);
++
++   if (added_domains & RADEON_DOMAIN_GTT)
++      cs->csc->used_gart += bo->base.size;
++   if (added_domains & RADEON_DOMAIN_VRAM)
++      cs->csc->used_vram += bo->base.size;
++
++   return index;
++}
++
++static int amdgpu_cs_get_reloc(struct radeon_winsys_cs *rcs,
++                               struct radeon_winsys_cs_handle *buf)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++
++   return amdgpu_get_reloc(cs->csc, (struct amdgpu_winsys_bo*)buf);
++}
++
++static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
++{
++   return TRUE;
++}
++
++static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++   boolean status =
++         (cs->csc->used_gart + gtt) < cs->ws->info.gart_size * 0.7 &&
++         (cs->csc->used_vram + vram) < cs->ws->info.vram_size * 0.7;
++
++   return status;
++}
++
++void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs, struct amdgpu_cs_context *csc)
++{
++   struct amdgpu_winsys *ws = cs->ws;
++   int i, r;
++   uint64_t fence;
++
++   r = amdgpu_cs_submit(ws->dev, ws->ctx, 0, &csc->request, 1, &fence);
++   if (r) {
++      fprintf(stderr, "amdgpu: The CS has been rejected, "
++              "see dmesg for more information.\n");
++
++      amdgpu_fence_signalled(csc->fence);
++   } else {
++      /* Success. */
++      amdgpu_fence_submitted(csc->fence, fence);
++
++      for (i = 0; i < csc->num_buffers; i++) {
++         amdgpu_fence_reference(&csc->buffers[i].bo->fence, csc->fence);
++      }
++   }
++
++   /* Cleanup. */
++   for (i = 0; i < csc->num_buffers; i++) {
++      p_atomic_dec(&csc->buffers[i].bo->num_active_ioctls);
++   }
++   amdgpu_cs_context_cleanup(csc);
++}
++
++/*
++ * Make sure previous submission of this cs are completed
++ */
++void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++
++   /* Wait for any pending ioctl to complete. */
++   if (cs->ws->thread) {
++      pipe_semaphore_wait(&cs->flush_completed);
++      pipe_semaphore_signal(&cs->flush_completed);
++   }
++}
++
++DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
++
++static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
++                            unsigned flags,
++                            struct pipe_fence_handle **fence,
++                            uint32_t cs_trace_id)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++   struct amdgpu_cs_context *tmp;
++
++   switch (cs->base.ring_type) {
++   case RING_DMA:
++      /* pad DMA ring to 8 DWs */
++      if (cs->ws->info.chip_class <= SI) {
++         while (rcs->cdw & 7)
++            OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
++      } else {
++         while (rcs->cdw & 7)
++            OUT_CS(&cs->base, 0x00000000); /* NOP packet */
++      }
++      break;
++   case RING_GFX:
++      /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
++             * r6xx, requires at least 4 dw alignment to avoid a hw bug.
++             */
++      if (cs->ws->info.chip_class <= SI) {
++         while (rcs->cdw & 7)
++            OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
++      } else {
++         while (rcs->cdw & 7)
++            OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
++      }
++      break;
++   case RING_UVD:
++      while (rcs->cdw & 15)
++         OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
++      break;
++   default:
++      break;
++   }
++
++   if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {
++      fprintf(stderr, "amdgpu: command stream overflowed\n");
++   }
++
++   amdgpu_cs_sync_flush(rcs);
++
++   /* Swap command streams. */
++   tmp = cs->csc;
++   cs->csc = cs->cst;
++   cs->cst = tmp;
++
++   /* If the CS is not empty or overflowed, emit it in a separate thread. */
++   if (cs->base.cdw && cs->base.cdw <= RADEON_MAX_CMDBUF_DWORDS && !debug_get_option_noop()) {
++      unsigned i, num_buffers = cs->cst->num_buffers;
++
++      cs->cst->ib.size = cs->base.cdw;
++      cs->cst->request.number_of_resources = cs->cst->num_buffers;
++      cs->cst->request.resources = cs->cst->handles;
++      cs->cst->request.resource_flags = cs->cst->flags;
++
++      for (i = 0; i < num_buffers; i++) {
++         /* Update the number of active asynchronous CS ioctls for the buffer. */
++         p_atomic_inc(&cs->cst->buffers[i].bo->num_active_ioctls);
++      }
++
++      switch (cs->base.ring_type) {
++      case RING_DMA:
++         cs->cst->request.ip_type = AMDGPU_HW_IP_DMA;
++         break;
++
++      case RING_UVD:
++         cs->cst->request.ip_type = AMDGPU_HW_IP_UVD;
++         break;
++
++      case RING_VCE:
++         cs->cst->request.ip_type = AMDGPU_HW_IP_VCE;
++         break;
++
++      default:
++      case RING_GFX:
++         if (flags & RADEON_FLUSH_COMPUTE) {
++            cs->cst->request.ip_type = AMDGPU_HW_IP_COMPUTE;
++         } else {
++            cs->cst->request.ip_type = AMDGPU_HW_IP_GFX;
++         }
++         break;
++      }
++
++      amdgpu_fence_reference(&cs->cst->fence, NULL);
++      cs->cst->fence = amdgpu_fence_create(cs->cst->request.ip_type,
++                                           cs->cst->request.ring);
++
++      if (fence)
++         amdgpu_fence_reference(fence, cs->cst->fence);
++
++      if (cs->ws->thread) {
++         pipe_semaphore_wait(&cs->flush_completed);
++         amdgpu_ws_queue_cs(cs->ws, cs);
++         if (!(flags & RADEON_FLUSH_ASYNC))
++            amdgpu_cs_sync_flush(rcs);
++      } else {
++         amdgpu_cs_emit_ioctl_oneshot(cs, cs->cst);
++      }
++   } else {
++      amdgpu_cs_context_cleanup(cs->cst);
++   }
++
++   amdgpu_get_new_ib(cs);
++
++   cs->ws->num_cs_flushes++;
++}
++
++static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++
++   amdgpu_cs_sync_flush(rcs);
++   pipe_semaphore_destroy(&cs->flush_completed);
++   amdgpu_cs_context_cleanup(&cs->csc1);
++   amdgpu_cs_context_cleanup(&cs->csc2);
++   p_atomic_dec(&cs->ws->num_cs);
++   amdgpu_cs_free_ib(cs->ws->dev, cs->ws->ctx,
++                     cs->csc->ib.ib_handle);
++   amdgpu_destroy_cs_context(&cs->csc1);
++   amdgpu_destroy_cs_context(&cs->csc2);
++   FREE(cs);
++}
++
++static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
++                                       struct radeon_winsys_cs_handle *_buf,
++                                       enum radeon_bo_usage usage)
++{
++   struct amdgpu_cs *cs = amdgpu_cs(rcs);
++   struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
++
++   return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
++}
++
++void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
++{
++   ws->base.cs_create = amdgpu_cs_create;
++   ws->base.cs_destroy = amdgpu_cs_destroy;
++   ws->base.cs_add_reloc = amdgpu_cs_add_reloc;
++   ws->base.cs_get_reloc = amdgpu_cs_get_reloc;
++   ws->base.cs_validate = amdgpu_cs_validate;
++   ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
++   ws->base.cs_flush = amdgpu_cs_flush;
++   ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
++   ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
++   ws->base.fence_wait = amdgpu_fence_wait;
++   ws->base.fence_reference = amdgpu_fence_reference;
++}
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h b/src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h
+new file mode 100644
+index 0000000..36a9aad
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h
+@@ -0,0 +1,149 @@
++/*
++ * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++#ifndef AMDGPU_DRM_CS_H
++#define AMDGPU_DRM_CS_H
++
++#include "amdgpu_bo.h"
++#include "util/u_memory.h"
++
++struct amdgpu_cs_buffer {
++   struct amdgpu_winsys_bo *bo;
++   enum radeon_bo_usage usage;
++   enum radeon_bo_domain domains;
++};
++
++struct amdgpu_cs_context {
++   struct amdgpu_cs_request    request;
++   struct amdgpu_cs_ib_info    ib;
++
++   /* Relocs. */
++   unsigned                    max_num_buffers;
++   unsigned                    num_buffers;
++   amdgpu_bo_handle            *handles;
++   uint8_t                     *flags;
++   struct amdgpu_cs_buffer     *buffers;
++
++   int                         buffer_indices_hashlist[512];
++
++   unsigned                    used_vram;
++   unsigned                    used_gart;
++
++   struct pipe_fence_handle    *fence;
++};
++
++struct amdgpu_cs {
++   struct radeon_winsys_cs base;
++
++   /* We flip between these two CS. While one is being consumed
++    * by the kernel in another thread, the other one is being filled
++    * by the pipe driver. */
++   struct amdgpu_cs_context csc1;
++   struct amdgpu_cs_context csc2;
++   /* The currently-used CS. */
++   struct amdgpu_cs_context *csc;
++   /* The CS being currently-owned by the other thread. */
++   struct amdgpu_cs_context *cst;
++
++   /* The winsys. */
++   struct amdgpu_winsys *ws;
++
++   /* Flush CS. */
++   void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
++   void *flush_data;
++
++   pipe_semaphore flush_completed;
++};
++
++struct amdgpu_fence {
++   struct pipe_reference reference;
++
++   uint64_t fence;          /* fence ID */
++   unsigned ip_type;        /* which hw ip block the fence belongs to */
++   uint32_t ring;           /* ring index of the hw ip block */
++
++   /* If the fence is unknown due to an IB still being submitted
++     * in the other thread. */
++   bool submission_in_progress;
++   bool signalled;
++};
++
++static INLINE void amdgpu_fence_reference(struct pipe_fence_handle **dst,
++                                          struct pipe_fence_handle *src)
++{
++   struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
++   struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
++
++   if (pipe_reference(&(*rdst)->reference, &rsrc->reference))
++      FREE(*rdst);
++   *rdst = rsrc;
++}
++
++int amdgpu_get_reloc(struct amdgpu_cs_context *csc, struct amdgpu_winsys_bo *bo);
++
++static INLINE struct amdgpu_cs *
++amdgpu_cs(struct radeon_winsys_cs *base)
++{
++   return (struct amdgpu_cs*)base;
++}
++
++static INLINE boolean
++amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
++                              struct amdgpu_winsys_bo *bo)
++{
++   int num_refs = bo->num_cs_references;
++   return num_refs == bo->rws->num_cs ||
++         (num_refs && amdgpu_get_reloc(cs->csc, bo) != -1);
++}
++
++static INLINE boolean
++amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
++                                         struct amdgpu_winsys_bo *bo,
++                                         enum radeon_bo_usage usage)
++{
++   int index;
++
++   if (!bo->num_cs_references)
++      return FALSE;
++
++   index = amdgpu_get_reloc(cs->csc, bo);
++   if (index == -1)
++      return FALSE;
++
++   return (cs->csc->buffers[index].usage & usage) != 0;
++}
++
++static INLINE boolean
++amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
++{
++   return bo->num_cs_references != 0;
++}
++
++void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs);
++void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
++void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs, struct amdgpu_cs_context *csc);
++
++#endif
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_public.h b/src/gallium/winsys/radeon/amdgpu/amdgpu_public.h
+new file mode 100644
+index 0000000..4a7aa8e
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_public.h
+@@ -0,0 +1,14 @@
++#ifndef AMDGPU_DRM_PUBLIC_H
++#define AMDGPU_DRM_PUBLIC_H
++
++#include "pipe/p_defines.h"
++
++struct radeon_winsys;
++struct pipe_screen;
++
++typedef struct pipe_screen *(*radeon_screen_create_t)(struct radeon_winsys *);
++
++struct radeon_winsys *
++amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create);
++
++#endif
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c
+new file mode 100644
+index 0000000..0f3367a
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c
+@@ -0,0 +1,491 @@
++/*
++ * Copyright © 2009 Corbin Simpson
++ * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++/*
++ * Authors:
++ *      Corbin Simpson <MostAwesomeDude@gmail.com>
++ *      Joakim Sindholt <opensource@zhasha.com>
++ *      Marek Olšák <maraeo@gmail.com>
++ */
++
++#include "amdgpu_cs.h"
++#include "amdgpu_public.h"
++
++#include "util/u_hash_table.h"
++#include <amdgpu_drm.h>
++#include <xf86drm.h>
++#include <stdio.h>
++#include <sys/stat.h>
++
++#define CIK_TILE_MODE_COLOR_2D			14
++
++#define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
++#define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
++
++static struct util_hash_table *fd_tab = NULL;
++pipe_static_mutex(fd_tab_mutex);
++
++static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
++{
++   unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
++
++   switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
++   case CIK__PIPE_CONFIG__ADDR_SURF_P2:
++   default:
++       return 2;
++   case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
++       return 4;
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
++       return 8;
++   case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
++   case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
++       return 16;
++   }
++}
++
++/* Convert Sea Islands register values GB_ADDR_CFG and MC_ADDR_CFG
++ * into GB_TILING_CONFIG register which is only present on R600-R700. */
++static unsigned r600_get_gb_tiling_config(struct amdgpu_gpu_info *info)
++{
++   unsigned num_pipes = info->gb_addr_cfg & 0x7;
++   unsigned num_banks = info->mc_arb_ramcfg & 0x3;
++   unsigned pipe_interleave_bytes = (info->gb_addr_cfg >> 4) & 0x7;
++   unsigned row_size = (info->gb_addr_cfg >> 28) & 0x3;
++
++   return num_pipes | (num_banks << 4) |
++         (pipe_interleave_bytes << 8) |
++         (row_size << 12);
++}
++
++/* Helper function to do the ioctls needed for setup and init. */
++static boolean do_winsys_init(struct amdgpu_winsys *ws)
++{
++   struct amdgpu_heap_info vram, gtt;
++   struct drm_amdgpu_info_hw_ip dma, uvd, vce;
++   uint32_t vce_version, vce_feature;
++   int r;
++
++   ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
++
++   r = amdgpu_device_initialize(ws->fd, &ws->info.drm_major,
++                                &ws->info.drm_minor, &ws->dev);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
++      return FALSE;
++   }
++
++   /* Query hardware and driver information. */
++   r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
++				     &vce_version, &vce_feature);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
++      goto fail;
++   }
++
++   r = amdgpu_cs_ctx_create(ws->dev, &ws->ctx);
++   if (r) {
++      fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed.\n");
++      goto fail;
++   }
++
++   /* Set chip identification. */
++   ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
++
++   switch (ws->info.pci_id) {
++#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
++#include "pci_ids/radeonsi_pci_ids.h"
++#undef CHIPSET
++
++   default:
++      fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
++      goto fail;
++   }
++
++   if (ws->info.family >= CHIP_TONGA)
++      ws->info.chip_class = VI;
++   else if (ws->info.family >= CHIP_BONAIRE)
++      ws->info.chip_class = CIK;
++   else {
++      fprintf(stderr, "amdgpu: Unknown family.\n");
++      goto fail;
++   }
++
++   /* LLVM 3.6 is required for VI. */
++   if (ws->info.chip_class >= VI && HAVE_LLVM < 0x0306) {
++      fprintf(stderr, "amdgpu: LLVM 3.6 is required, got LLVM %i.%i.\n",
++              HAVE_LLVM >> 8, HAVE_LLVM & 255);
++      goto fail;
++   }
++
++   /* Set hardware information. */
++   ws->info.gart_size = gtt.heap_size;
++   ws->info.vram_size = vram.heap_size;
++   /* convert the shader clock from KHz to MHz */
++   ws->info.max_sclk = ws->amdinfo.max_engine_clk / 1000;
++   ws->info.max_compute_units = 1; /* TODO */
++   ws->info.max_se = ws->amdinfo.num_shader_engines;
++   ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
++   ws->info.has_uvd = uvd.available_rings != 0;
++   ws->info.vce_fw_version =
++         vce.available_rings ? vce_version : 0;
++   ws->info.r600_num_backends = ws->amdinfo.rb_pipes;
++   ws->info.r600_clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
++   ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
++   ws->info.r600_num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
++   ws->info.r600_max_pipes = ws->amdinfo.max_quad_shader_pipes; /* TODO: is this correct? */
++   ws->info.r600_virtual_address = TRUE;
++   ws->info.r600_has_dma = dma.available_rings != 0;
++
++   memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
++          sizeof(ws->amdinfo.gb_tile_mode));
++   ws->info.si_tile_mode_array_valid = TRUE;
++   ws->info.si_backend_enabled_mask = ws->amdinfo.enabled_rb_pipes_mask;
++
++   memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
++          sizeof(ws->amdinfo.gb_macro_tile_mode));
++   ws->info.cik_macrotile_mode_array_valid = TRUE;
++
++   return TRUE;
++
++fail:
++   if (ws->ctx) {
++      amdgpu_cs_ctx_free(ws->dev, ws->ctx);
++   }
++   amdgpu_device_deinitialize(ws->dev);
++   ws->dev = NULL;
++   return FALSE;
++}
++
++static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
++{
++   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
++
++   if (ws->thread) {
++      ws->kill_thread = 1;
++      pipe_semaphore_signal(&ws->cs_queued);
++      pipe_thread_wait(ws->thread);
++   }
++   pipe_semaphore_destroy(&ws->cs_queued);
++   pipe_mutex_destroy(ws->cs_stack_lock);
++
++   ws->cman->destroy(ws->cman);
++   ws->kman->destroy(ws->kman);
++
++   amdgpu_cs_ctx_free(ws->dev, ws->ctx);
++   amdgpu_device_deinitialize(ws->dev);
++   FREE(rws);
++}
++
++static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
++                                     struct radeon_info *info)
++{
++   *info = ((struct amdgpu_winsys *)rws)->info;
++}
++
++static boolean amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
++                                         enum radeon_feature_id fid,
++                                         boolean enable)
++{
++   return FALSE;
++}
++
++static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
++                                   enum radeon_value_id value)
++{
++   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
++   struct amdgpu_heap_info heap;
++   uint64_t retval = 0;
++
++   switch (value) {
++   case RADEON_REQUESTED_VRAM_MEMORY:
++      return ws->allocated_vram;
++   case RADEON_REQUESTED_GTT_MEMORY:
++      return ws->allocated_gtt;
++   case RADEON_BUFFER_WAIT_TIME_NS:
++      return ws->buffer_wait_time;
++   case RADEON_TIMESTAMP:
++      amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
++      return retval;
++   case RADEON_NUM_CS_FLUSHES:
++      return ws->num_cs_flushes;
++   case RADEON_NUM_BYTES_MOVED:
++      amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
++      return retval;
++   case RADEON_VRAM_USAGE:
++      amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
++      return heap.heap_usage;
++   case RADEON_GTT_USAGE:
++      amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
++      return heap.heap_usage;
++   }
++   return 0;
++}
++
++static unsigned hash_fd(void *key)
++{
++   int fd = pointer_to_intptr(key);
++   struct stat stat;
++   fstat(fd, &stat);
++
++   return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
++}
++
++static int compare_fd(void *key1, void *key2)
++{
++   int fd1 = pointer_to_intptr(key1);
++   int fd2 = pointer_to_intptr(key2);
++   struct stat stat1, stat2;
++   fstat(fd1, &stat1);
++   fstat(fd2, &stat2);
++
++   return stat1.st_dev != stat2.st_dev ||
++          stat1.st_ino != stat2.st_ino ||
++          stat1.st_rdev != stat2.st_rdev;
++}
++
++void amdgpu_ws_queue_cs(struct amdgpu_winsys *ws, struct amdgpu_cs *cs)
++{
++retry:
++   pipe_mutex_lock(ws->cs_stack_lock);
++   if (ws->num_enqueued_cs >= RING_LAST) {
++      /* no room left for a flush */
++      pipe_mutex_unlock(ws->cs_stack_lock);
++      goto retry;
++   }
++   ws->cs_stack[ws->num_enqueued_cs++] = cs;
++   pipe_mutex_unlock(ws->cs_stack_lock);
++   pipe_semaphore_signal(&ws->cs_queued);
++}
++
++static PIPE_THREAD_ROUTINE(amdgpu_cs_emit_ioctl, param)
++{
++   struct amdgpu_winsys *ws = (struct amdgpu_winsys *)param;
++   struct amdgpu_cs *cs;
++   unsigned i;
++
++   while (1) {
++      pipe_semaphore_wait(&ws->cs_queued);
++      if (ws->kill_thread)
++         break;
++
++      pipe_mutex_lock(ws->cs_stack_lock);
++      cs = ws->cs_stack[0];
++      for (i = 1; i < ws->num_enqueued_cs; i++)
++         ws->cs_stack[i - 1] = ws->cs_stack[i];
++      ws->cs_stack[--ws->num_enqueued_cs] = NULL;
++      pipe_mutex_unlock(ws->cs_stack_lock);
++
++      if (cs) {
++         amdgpu_cs_emit_ioctl_oneshot(cs, cs->cst);
++         pipe_semaphore_signal(&cs->flush_completed);
++      }
++   }
++   pipe_mutex_lock(ws->cs_stack_lock);
++   for (i = 0; i < ws->num_enqueued_cs; i++) {
++      pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
++      ws->cs_stack[i] = NULL;
++   }
++   ws->num_enqueued_cs = 0;
++   pipe_mutex_unlock(ws->cs_stack_lock);
++   return 0;
++}
++
++DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
++static PIPE_THREAD_ROUTINE(amdgpu_cs_emit_ioctl, param);
++
++static bool amdgpu_winsys_unref(struct radeon_winsys *ws)
++{
++   struct amdgpu_winsys *rws = (struct amdgpu_winsys*)ws;
++   bool destroy;
++
++   /* When the reference counter drops to zero, remove the fd from the table.
++    * This must happen while the mutex is locked, so that
++    * amdgpu_winsys_create in another thread doesn't get the winsys
++    * from the table when the counter drops to 0. */
++   pipe_mutex_lock(fd_tab_mutex);
++
++   destroy = pipe_reference(&rws->reference, NULL);
++   if (destroy && fd_tab)
++      util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
++
++   pipe_mutex_unlock(fd_tab_mutex);
++   return destroy;
++}
++
++struct radeon_winsys *
++      amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
++{
++   struct amdgpu_winsys *ws;
++   drmVersionPtr version = drmGetVersion(fd);
++
++   /* The DRM driver version of amdgpu is 3.x.x. */
++   if (version->version_major != 3) {
++      drmFreeVersion(version);
++      return NULL;
++   }
++   drmFreeVersion(version);
++
++   /* Look up the winsys from the fd table. */
++   pipe_mutex_lock(fd_tab_mutex);
++   if (!fd_tab) {
++      fd_tab = util_hash_table_create(hash_fd, compare_fd);
++   }
++
++   ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
++   if (ws) {
++      pipe_reference(NULL, &ws->reference);
++      pipe_mutex_unlock(fd_tab_mutex);
++      return &ws->base;
++   }
++
++   ws = CALLOC_STRUCT(amdgpu_winsys);
++   if (!ws) {
++      pipe_mutex_unlock(fd_tab_mutex);
++      return NULL;
++   }
++
++   ws->fd = fd;
++
++   if (!do_winsys_init(ws))
++      goto fail;
++
++   /* Create managers. */
++   ws->kman = amdgpu_bomgr_create(ws);
++   if (!ws->kman)
++      goto fail;
++   ws->cman = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
++			(ws->info.vram_size + ws->info.gart_size) / 8);
++   if (!ws->cman)
++      goto fail;
++
++   /* init reference */
++   pipe_reference_init(&ws->reference, 1);
++
++   /* Set functions. */
++   ws->base.unref = amdgpu_winsys_unref;
++   ws->base.destroy = amdgpu_winsys_destroy;
++   ws->base.query_info = amdgpu_winsys_query_info;
++   ws->base.cs_request_feature = amdgpu_cs_request_feature;
++   ws->base.query_value = amdgpu_query_value;
++
++   amdgpu_bomgr_init_functions(ws);
++   amdgpu_cs_init_functions(ws);
++
++   pipe_mutex_init(ws->cs_stack_lock);
++
++   ws->num_enqueued_cs = 0;
++   pipe_semaphore_init(&ws->cs_queued, 0);
++   if (ws->num_cpus > 1 && debug_get_option_thread())
++      ws->thread = pipe_thread_create(amdgpu_cs_emit_ioctl, ws);
++
++   /* Create the screen at the end. The winsys must be initialized
++    * completely.
++    *
++    * Alternatively, we could create the screen based on "ws->gen"
++    * and link all drivers into one binary blob. */
++   ws->base.screen = screen_create(&ws->base);
++   if (!ws->base.screen) {
++      amdgpu_winsys_destroy(&ws->base);
++      pipe_mutex_unlock(fd_tab_mutex);
++      return NULL;
++   }
++
++   util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
++
++   /* We must unlock the mutex once the winsys is fully initialized, so that
++    * other threads attempting to create the winsys from the same fd will
++    * get a fully initialized winsys and not just half-way initialized. */
++   pipe_mutex_unlock(fd_tab_mutex);
++
++   return &ws->base;
++
++fail:
++   pipe_mutex_unlock(fd_tab_mutex);
++   if (ws->cman)
++      ws->cman->destroy(ws->cman);
++   if (ws->kman)
++      ws->kman->destroy(ws->kman);
++   FREE(ws);
++   return NULL;
++}
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h
+new file mode 100644
+index 0000000..fc27f1c
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h
+@@ -0,0 +1,80 @@
++/*
++ * Copyright © 2009 Corbin Simpson
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++/*
++ * Authors:
++ *      Corbin Simpson <MostAwesomeDude@gmail.com>
++ */
++#ifndef AMDGPU_DRM_WINSYS_H
++#define AMDGPU_DRM_WINSYS_H
++
++#include "../radeon_winsys.h"
++#include "os/os_thread.h"
++#include <amdgpu.h>
++
++struct amdgpu_cs;
++
++struct amdgpu_winsys {
++   struct radeon_winsys base;
++   struct pipe_reference reference;
++
++   int fd; /* DRM file descriptor */
++   amdgpu_device_handle dev;
++   /* This only affects the order in which IBs are executed. */
++   amdgpu_context_handle ctx;
++
++   int num_cs; /* The number of command streams created. */
++   uint64_t allocated_vram;
++   uint64_t allocated_gtt;
++   uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
++   uint64_t num_cs_flushes;
++
++   struct radeon_info info;
++
++   struct pb_manager *kman;
++   struct pb_manager *cman;
++
++   uint32_t num_cpus;      /* Number of CPUs. */
++
++   /* rings submission thread */
++   pipe_mutex cs_stack_lock;
++   pipe_semaphore cs_queued;
++   pipe_thread thread;
++   int kill_thread;
++   int num_enqueued_cs;
++   struct amdgpu_cs *cs_stack[RING_LAST];
++
++   struct amdgpu_gpu_info amdinfo;
++};
++
++static INLINE struct amdgpu_winsys *
++amdgpu_winsys(struct radeon_winsys *base)
++{
++   return (struct amdgpu_winsys*)base;
++}
++
++void amdgpu_ws_queue_cs(struct amdgpu_winsys *ws, struct amdgpu_cs *cs);
++
++#endif
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+index 12767bf..a312f03 100644
+--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+@@ -34,6 +34,7 @@
+ #include "radeon_drm_bo.h"
+ #include "radeon_drm_cs.h"
+ #include "radeon_drm_public.h"
++#include "../amdgpu/amdgpu_public.h"
+ 
+ #include "pipebuffer/pb_bufmgr.h"
+ #include "util/u_memory.h"
+@@ -643,6 +644,13 @@ PUBLIC struct radeon_winsys *
+ radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
+ {
+     struct radeon_drm_winsys *ws;
++    struct radeon_winsys *amdgpu;
++
++    /* First, try amdgpu. */
++    amdgpu = amdgpu_winsys_create(fd, screen_create);
++    if (amdgpu) {
++        return amdgpu;
++    }
+ 
+     pipe_mutex_lock(fd_tab_mutex);
+     if (!fd_tab) {
+diff --git a/src/gallium/winsys/radeon/radeon_winsys.h b/src/gallium/winsys/radeon/radeon_winsys.h
+index 7fb7ac9..a3cb273 100644
+--- a/src/gallium/winsys/radeon/radeon_winsys.h
++++ b/src/gallium/winsys/radeon/radeon_winsys.h
+@@ -136,6 +136,9 @@ enum radeon_family {
+     CHIP_KABINI,
+     CHIP_HAWAII,
+     CHIP_MULLINS,
++    CHIP_TONGA,
++    CHIP_ICELAND,
++    CHIP_CARRIZO,
+     CHIP_LAST,
+ };
+ 
+@@ -150,6 +153,7 @@ enum chip_class {
+     CAYMAN,
+     SI,
+     CIK,
++    VI,
+ };
+ 
+ enum ring_type {
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0009-winsys-amdgpu-add-addrlib-texture-addressing-and-ali.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0009-winsys-amdgpu-add-addrlib-texture-addressing-and-ali.patch
new file mode 100644
index 00000000..0ca8a819
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0009-winsys-amdgpu-add-addrlib-texture-addressing-and-ali.patch
@@ -0,0 +1,22649 @@
+From dbeaed6cf049a0be97631ab74afa1f4ab9a800bf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 19:41:33 +0200
+Subject: [PATCH 09/29] winsys/amdgpu: add addrlib - texture addressing and
+ alignment calculator
+
+This is an internal project that Catalyst uses and now open source will do
+too.
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/winsys/radeon/amdgpu/Makefile.am       |    7 +-
+ src/gallium/winsys/radeon/amdgpu/Makefile.sources  |   23 +
+ .../winsys/radeon/amdgpu/addrlib/addrinterface.cpp | 1008 +++++
+ .../winsys/radeon/amdgpu/addrlib/addrinterface.h   | 2166 +++++++++
+ .../winsys/radeon/amdgpu/addrlib/addrtypes.h       |  590 +++
+ .../winsys/radeon/amdgpu/addrlib/core/addrcommon.h |  558 +++
+ .../radeon/amdgpu/addrlib/core/addrelemlib.cpp     | 1678 +++++++
+ .../radeon/amdgpu/addrlib/core/addrelemlib.h       |  270 ++
+ .../winsys/radeon/amdgpu/addrlib/core/addrlib.cpp  | 4028 +++++++++++++++++
+ .../winsys/radeon/amdgpu/addrlib/core/addrlib.h    |  695 +++
+ .../radeon/amdgpu/addrlib/core/addrobject.cpp      |  246 ++
+ .../winsys/radeon/amdgpu/addrlib/core/addrobject.h |   89 +
+ .../amdgpu/addrlib/inc/chip/r800/si_gb_reg.h       |  155 +
+ .../radeon/amdgpu/addrlib/inc/lnx_common_defs.h    |  129 +
+ .../addrlib/r800/chip/si_ci_vi_merged_enum.h       |   40 +
+ .../radeon/amdgpu/addrlib/r800/ciaddrlib.cpp       | 1777 ++++++++
+ .../winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.h  |  197 +
+ .../radeon/amdgpu/addrlib/r800/egbaddrlib.cpp      | 4578 ++++++++++++++++++++
+ .../winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.h |  411 ++
+ .../radeon/amdgpu/addrlib/r800/siaddrlib.cpp       | 2818 ++++++++++++
+ .../winsys/radeon/amdgpu/addrlib/r800/siaddrlib.h  |  262 ++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_id.h       |  157 +
+ src/gallium/winsys/radeon/amdgpu/amdgpu_surface.c  |  436 ++
+ src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c   |   50 +
+ src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h   |    6 +
+ 25 files changed, 22373 insertions(+), 1 deletion(-)
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/addrtypes.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrcommon.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/inc/chip/r800/si_gb_reg.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/inc/lnx_common_defs.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/chip/si_ci_vi_merged_enum.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.cpp
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_id.h
+ create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_surface.c
+
+diff --git a/src/gallium/winsys/radeon/amdgpu/Makefile.am b/src/gallium/winsys/radeon/amdgpu/Makefile.am
+index 80ecb75..a719913 100644
+--- a/src/gallium/winsys/radeon/amdgpu/Makefile.am
++++ b/src/gallium/winsys/radeon/amdgpu/Makefile.am
+@@ -3,7 +3,12 @@ include $(top_srcdir)/src/gallium/Automake.inc
+ 
+ AM_CFLAGS = \
+ 	$(GALLIUM_WINSYS_CFLAGS) \
+-	$(AMDGPU_CFLAGS)
++	$(AMDGPU_CFLAGS) \
++	-I$(srcdir)/addrlib \
++	-I$(srcdir)/addrlib/core \
++	-I$(srcdir)/addrlib/inc/chip/r800 \
++	-I$(srcdir)/addrlib/r800/chip \
++	-DBRAHMA_BUILD=1
+ 
+ AM_CXXFLAGS = $(AM_CFLAGS)
+ 
+diff --git a/src/gallium/winsys/radeon/amdgpu/Makefile.sources b/src/gallium/winsys/radeon/amdgpu/Makefile.sources
+index 0f55010..6b33841 100644
+--- a/src/gallium/winsys/radeon/amdgpu/Makefile.sources
++++ b/src/gallium/winsys/radeon/amdgpu/Makefile.sources
+@@ -1,8 +1,31 @@
+ C_SOURCES := \
++	addrlib/addrinterface.cpp \
++	addrlib/addrinterface.h \
++	addrlib/addrtypes.h \
++	addrlib/core/addrcommon.h \
++	addrlib/core/addrelemlib.cpp \
++	addrlib/core/addrelemlib.h \
++	addrlib/core/addrlib.cpp \
++	addrlib/core/addrlib.h \
++	addrlib/core/addrobject.cpp \
++	addrlib/core/addrobject.h \
++	addrlib/inc/chip/r800/si_gb_reg.h \
++	addrlib/inc/lnx_common_defs.h \
++	addrlib/r800/chip/si_ci_merged_enum.h \
++	addrlib/r800/chip/si_ci_vi_merged_enum.h \
++	addrlib/r800/chip/si_enum.h \
++	addrlib/r800/ciaddrlib.cpp \
++	addrlib/r800/ciaddrlib.h \
++	addrlib/r800/egbaddrlib.cpp \
++	addrlib/r800/egbaddrlib.h \
++	addrlib/r800/siaddrlib.cpp \
++	addrlib/r800/siaddrlib.h \
+ 	amdgpu_bo.c \
+ 	amdgpu_bo.h \
+ 	amdgpu_cs.c \
+ 	amdgpu_cs.h \
++	amdgpu_id.h \
+ 	amdgpu_public.h \
++	amdgpu_surface.c \
+ 	amdgpu_winsys.c \
+ 	amdgpu_winsys.h
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.cpp
+new file mode 100644
+index 0000000..6556927
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.cpp
+@@ -0,0 +1,1008 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrinterface.cpp
++* @brief Contains the addrlib interface functions
++***************************************************************************************************
++*/
++#include "addrinterface.h"
++#include "addrlib.h"
++
++#include "addrcommon.h"
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Create/Destroy/Config functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrCreate
++*
++*   @brief
++*       Create address lib object
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrCreate(
++    const ADDR_CREATE_INPUT*    pAddrCreateIn,  ///< [in] infomation for creating address lib object
++    ADDR_CREATE_OUTPUT*         pAddrCreateOut) ///< [out] address lib handle
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    returnCode = AddrLib::Create(pAddrCreateIn, pAddrCreateOut);
++
++    return returnCode;
++}
++
++
++
++/**
++***************************************************************************************************
++*   AddrDestroy
++*
++*   @brief
++*       Destroy address lib object
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrDestroy(
++    ADDR_HANDLE hLib) ///< [in] address lib handle
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (hLib)
++    {
++        AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++        pLib->Destroy();
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                    Surface functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrComputeSurfaceInfo
++*
++*   @brief
++*       Calculate surface width/height/depth/alignments and suitable tiling mode
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
++    ADDR_HANDLE                             hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,  ///< [in] surface information
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut) ///< [out] surface parameters and alignments
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeSurfaceInfo(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++/**
++***************************************************************************************************
++*   AddrComputeSurfaceAddrFromCoord
++*
++*   @brief
++*       Compute surface address according to coordinates
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,  ///< [in] surface info and coordinates
++    ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) ///< [out] surface address
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeSurfaceAddrFromCoord(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeSurfaceCoordFromAddr
++*
++*   @brief
++*       Compute coordinates according to surface address
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,  ///< [in] surface info and address
++    ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut) ///< [out] coordinates
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeSurfaceCoordFromAddr(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                   HTile functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrComputeHtileInfo
++*
++*   @brief
++*       Compute Htile pitch, height, base alignment and size in bytes
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
++    ADDR_HANDLE                             hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_HTILE_INFO_INPUT*    pIn,  ///< [in] Htile information
++    ADDR_COMPUTE_HTILE_INFO_OUTPUT*         pOut) ///< [out] Htile pitch, height and size in bytes
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeHtileInfo(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeHtileAddrFromCoord
++*
++*   @brief
++*       Compute Htile address according to coordinates (of depth buffer)
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*   pIn,  ///< [in] Htile info and coordinates
++    ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut) ///< [out] Htile address
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeHtileAddrFromCoord(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeHtileCoordFromAddr
++*
++*   @brief
++*       Compute coordinates within depth buffer (1st pixel of a micro tile) according to
++*       Htile address
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*   pIn,  ///< [in] Htile info and address
++    ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut) ///< [out] Htile coordinates
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeHtileCoordFromAddr(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                     C-mask functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrComputeCmaskInfo
++*
++*   @brief
++*       Compute Cmask pitch, height, base alignment and size in bytes from color buffer
++*       info
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
++    ADDR_HANDLE                             hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_CMASK_INFO_INPUT*    pIn,  ///< [in] Cmask pitch and height
++    ADDR_COMPUTE_CMASK_INFO_OUTPUT*         pOut) ///< [out] Cmask pitch, height and size in bytes
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeCmaskInfo(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeCmaskAddrFromCoord
++*
++*   @brief
++*       Compute Cmask address according to coordinates (of MSAA color buffer)
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,  ///< [in] Cmask info and coordinates
++    ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut) ///< [out] Cmask address
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeCmaskAddrFromCoord(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeCmaskCoordFromAddr
++*
++*   @brief
++*       Compute coordinates within color buffer (1st pixel of a micro tile) according to
++*       Cmask address
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*   pIn,  ///< [in] Cmask info and address
++    ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*        pOut) ///< [out] Cmask coordinates
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeCmaskCoordFromAddr(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                     F-mask functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrComputeFmaskInfo
++*
++*   @brief
++*       Compute Fmask pitch/height/depth/alignments and size in bytes
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
++    ADDR_HANDLE                             hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,  ///< [in] Fmask information
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut) ///< [out] Fmask pitch and height
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeFmaskInfo(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeFmaskAddrFromCoord
++*
++*   @brief
++*       Compute Fmask address according to coordinates (x,y,slice,sample,plane)
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,  ///< [in] Fmask info and coordinates
++    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut) ///< [out] Fmask address
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeFmaskAddrFromCoord(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeFmaskCoordFromAddr
++*
++*   @brief
++*       Compute coordinates (x,y,slice,sample,plane) according to Fmask address
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
++    ADDR_HANDLE                                     hLib, ///< [in] address lib handle
++    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,  ///< [in] Fmask info and address
++    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut) ///< [out] Fmask coordinates
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeFmaskCoordFromAddr(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                     DCC key functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrComputeDccInfo
++*
++*   @brief
++*       Compute DCC key size, base alignment based on color surface size, tile info or tile index
++*
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
++    ADDR_HANDLE                             hLib,   ///< [in] handle of addrlib
++    const ADDR_COMPUTE_DCCINFO_INPUT*       pIn,    ///< [in] input
++    ADDR_COMPUTE_DCCINFO_OUTPUT*            pOut)   ///< [out] output
++{
++    ADDR_E_RETURNCODE returnCode;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++       returnCode = pLib->ComputeDccInfo(pIn, pOut);
++    }
++    else
++    {
++       returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////
++// Below functions are element related or helper functions
++///////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrGetVersion
++*
++*   @brief
++*       Get AddrLib version number. Client may check this return value against ADDRLIB_VERSION
++*       defined in addrinterface.h to see if there is a mismatch.
++***************************************************************************************************
++*/
++UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib)
++{
++    UINT_32 version = 0;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_ASSERT(pLib != NULL);
++
++    if (pLib)
++    {
++        version = pLib->GetVersion();
++    }
++
++    return version;
++}
++
++/**
++***************************************************************************************************
++*   AddrUseTileIndex
++*
++*   @brief
++*       Return TRUE if tileIndex is enabled in this address library
++***************************************************************************************************
++*/
++BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib)
++{
++    BOOL_32 useTileIndex = FALSE;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_ASSERT(pLib != NULL);
++
++    if (pLib)
++    {
++        useTileIndex = pLib->UseTileIndex(0);
++    }
++
++    return useTileIndex;
++}
++
++/**
++***************************************************************************************************
++*   AddrUseCombinedSwizzle
++*
++*   @brief
++*       Return TRUE if combined swizzle is enabled in this address library
++***************************************************************************************************
++*/
++BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib)
++{
++    BOOL_32 useCombinedSwizzle = FALSE;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_ASSERT(pLib != NULL);
++
++    if (pLib)
++    {
++        useCombinedSwizzle = pLib->UseCombinedSwizzle();
++    }
++
++    return useCombinedSwizzle;
++}
++
++/**
++***************************************************************************************************
++*   AddrExtractBankPipeSwizzle
++*
++*   @brief
++*       Extract Bank and Pipe swizzle from base256b
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
++    ADDR_HANDLE                                 hLib,     ///< [in] addrlib handle
++    const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT*  pIn,      ///< [in] input structure
++    ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*       pOut)     ///< [out] output structure
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ExtractBankPipeSwizzle(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrCombineBankPipeSwizzle
++*
++*   @brief
++*       Combine Bank and Pipe swizzle
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
++    ADDR_HANDLE                                 hLib,
++    const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,
++    ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT*       pOut)
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->CombineBankPipeSwizzle(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeSliceSwizzle
++*
++*   @brief
++*       Compute a swizzle for slice from a base swizzle
++*   @return
++*       ADDR_OK if no error
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
++    ADDR_HANDLE                                 hLib,
++    const ADDR_COMPUTE_SLICESWIZZLE_INPUT*      pIn,
++    ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*           pOut)
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeSliceTileSwizzle(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputeBaseSwizzle
++*
++*   @brief
++*       Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
++*   @return
++*       ADDR_OK if no error
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
++    ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*       pOut)
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputeBaseSwizzle(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   ElemFlt32ToDepthPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a depth/stencil pixel value
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++*
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
++    ADDR_HANDLE                         hLib,    ///< [in] addrlib handle
++    const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,     ///< [in] per-component value
++    ELEM_FLT32TODEPTHPIXEL_OUTPUT*      pOut)    ///< [out] final pixel value
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        pLib->Flt32ToDepthPixel(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   ElemFlt32ToColorPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a red/green/blue/alpha pixel value
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++*
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
++    ADDR_HANDLE                         hLib,    ///< [in] addrlib handle
++    const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,     ///< [in] format, surface number and swap value
++    ELEM_FLT32TOCOLORPIXEL_OUTPUT*      pOut)    ///< [out] final pixel value
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        pLib->Flt32ToColorPixel(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   ElemGetExportNorm
++*
++*   @brief
++*       Helper function to check one format can be EXPORT_NUM,
++*       which is a register CB_COLOR_INFO.SURFACE_FORMAT.
++*       FP16 can be reported as EXPORT_NORM for rv770 in r600
++*       family
++*
++***************************************************************************************************
++*/
++BOOL_32 ADDR_API ElemGetExportNorm(
++    ADDR_HANDLE                     hLib, ///< [in] addrlib handle
++    const ELEM_GETEXPORTNORM_INPUT* pIn)  ///< [in] input structure
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++    BOOL_32 enabled = FALSE;
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        enabled = pLib->GetExportNorm(pIn);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    ADDR_ASSERT(returnCode == ADDR_OK);
++
++    return enabled;
++}
++
++/**
++***************************************************************************************************
++*   AddrConvertTileInfoToHW
++*
++*   @brief
++*       Convert tile info from real value to hardware register value
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
++    ADDR_HANDLE                             hLib, ///< [in] address lib handle
++    const ADDR_CONVERT_TILEINFOTOHW_INPUT*  pIn,  ///< [in] tile info with real value
++    ADDR_CONVERT_TILEINFOTOHW_OUTPUT*       pOut) ///< [out] tile info with HW register value
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ConvertTileInfoToHW(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrConvertTileIndex
++*
++*   @brief
++*       Convert tile index to tile mode/type/info
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
++    ADDR_HANDLE                          hLib, ///< [in] address lib handle
++    const ADDR_CONVERT_TILEINDEX_INPUT*  pIn,  ///< [in] input - tile index
++    ADDR_CONVERT_TILEINDEX_OUTPUT*       pOut) ///< [out] tile mode/type/info
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ConvertTileIndex(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrConvertTileIndex1
++*
++*   @brief
++*       Convert tile index to tile mode/type/info
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
++    ADDR_HANDLE                          hLib, ///< [in] address lib handle
++    const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,  ///< [in] input - tile index
++    ADDR_CONVERT_TILEINDEX_OUTPUT*       pOut) ///< [out] tile mode/type/info
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ConvertTileIndex1(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrGetTileIndex
++*
++*   @brief
++*       Get tile index from tile mode/type/info
++*
++*   @return
++*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
++*
++*   @note
++*       Only meaningful for SI (and above)
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
++    ADDR_HANDLE                     hLib,
++    const ADDR_GET_TILEINDEX_INPUT* pIn,
++    ADDR_GET_TILEINDEX_OUTPUT*      pOut)
++{
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->GetTileIndex(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrComputePrtInfo
++*
++*   @brief
++*       Interface function for ComputePrtInfo
++*
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
++    ADDR_HANDLE                 hLib,
++    const ADDR_PRT_INFO_INPUT*  pIn,
++    ADDR_PRT_INFO_OUTPUT*       pOut)
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    AddrLib* pLib = AddrLib::GetAddrLib(hLib);
++
++    if (pLib != NULL)
++    {
++        returnCode = pLib->ComputePrtInfo(pIn, pOut);
++    }
++    else
++    {
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.h b/src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.h
+new file mode 100644
+index 0000000..03fbf2b
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/addrinterface.h
+@@ -0,0 +1,2166 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrinterface.h
++* @brief Contains the addrlib interfaces declaration and parameter defines
++***************************************************************************************************
++*/
++#ifndef __ADDR_INTERFACE_H__
++#define __ADDR_INTERFACE_H__
++
++#if defined(__cplusplus)
++extern "C"
++{
++#endif
++
++#include "addrtypes.h"
++
++#define ADDRLIB_VERSION_MAJOR 5
++#define ADDRLIB_VERSION_MINOR 25
++#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
++
++/// Virtually all interface functions need ADDR_HANDLE as first parameter
++typedef VOID*   ADDR_HANDLE;
++
++/// Client handle used in callbacks
++typedef VOID*   ADDR_CLIENT_HANDLE;
++
++/**
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                                  Callback functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*    typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
++*         const ADDR_ALLOCSYSMEM_INPUT* pInput);
++*    typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
++*         VOID* pVirtAddr);
++*    typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
++*         const ADDR_DEBUGPRINT_INPUT* pInput);
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                               Create/Destroy/Config functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     AddrCreate()
++*     AddrDestroy()
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                                  Surface functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     AddrComputeSurfaceInfo()
++*     AddrComputeSurfaceAddrFromCoord()
++*     AddrComputeSurfaceCoordFromAddr()
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                                   HTile functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     AddrComputeHtileInfo()
++*     AddrComputeHtileAddrFromCoord()
++*     AddrComputeHtileCoordFromAddr()
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                                   C-mask functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     AddrComputeCmaskInfo()
++*     AddrComputeCmaskAddrFromCoord()
++*     AddrComputeCmaskCoordFromAddr()
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                                   F-mask functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     AddrComputeFmaskInfo()
++*     AddrComputeFmaskAddrFromCoord()
++*     AddrComputeFmaskCoordFromAddr()
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                               Element/Utility functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     ElemFlt32ToDepthPixel()
++*     ElemFlt32ToColorPixel()
++*     AddrExtractBankPipeSwizzle()
++*     AddrCombineBankPipeSwizzle()
++*     AddrComputeSliceSwizzle()
++*     AddrConvertTileInfoToHW()
++*     AddrConvertTileIndex()
++*     AddrConvertTileIndex1()
++*     AddrGetTileIndex()
++*     AddrComputeBaseSwizzle()
++*     AddrUseTileIndex()
++*     AddrUseCombinedSwizzle()
++*
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++* //                                    Dump functions
++* /////////////////////////////////////////////////////////////////////////////////////////////////
++*     AddrDumpSurfaceInfo()
++*     AddrDumpFmaskInfo()
++*     AddrDumpCmaskInfo()
++*     AddrDumpHtileInfo()
++*
++**/
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                      Callback functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++* @brief Alloc system memory flags.
++* @note These flags are reserved for future use and if flags are added will minimize the impact
++*       of the client.
++***************************************************************************************************
++*/
++typedef union _ADDR_ALLOCSYSMEM_FLAGS
++{
++    struct
++    {
++        UINT_32 reserved    : 32;  ///< Reserved for future use.
++    } fields;
++    UINT_32 value;
++
++} ADDR_ALLOCSYSMEM_FLAGS;
++
++/**
++***************************************************************************************************
++* @brief Alloc system memory input structure
++***************************************************************************************************
++*/
++typedef struct _ADDR_ALLOCSYSMEM_INPUT
++{
++    UINT_32                 size;           ///< Size of this structure in bytes
++
++    ADDR_ALLOCSYSMEM_FLAGS  flags;          ///< System memory flags.
++    UINT_32                 sizeInBytes;    ///< System memory allocation size in bytes.
++    ADDR_CLIENT_HANDLE      hClient;        ///< Client handle
++} ADDR_ALLOCSYSMEM_INPUT;
++
++/**
++***************************************************************************************************
++* ADDR_ALLOCSYSMEM
++*   @brief
++*       Allocate system memory callback function. Returns valid pointer on success.
++***************************************************************************************************
++*/
++typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
++    const ADDR_ALLOCSYSMEM_INPUT* pInput);
++
++/**
++***************************************************************************************************
++* @brief Free system memory input structure
++***************************************************************************************************
++*/
++typedef struct _ADDR_FREESYSMEM_INPUT
++{
++    UINT_32                 size;           ///< Size of this structure in bytes
++
++    VOID*                   pVirtAddr;      ///< Virtual address
++    ADDR_CLIENT_HANDLE      hClient;        ///< Client handle
++} ADDR_FREESYSMEM_INPUT;
++
++/**
++***************************************************************************************************
++* ADDR_FREESYSMEM
++*   @brief
++*       Free system memory callback function.
++*       Returns ADDR_OK on success.
++***************************************************************************************************
++*/
++typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
++    const ADDR_FREESYSMEM_INPUT* pInput);
++
++/**
++***************************************************************************************************
++* @brief Print debug message input structure
++***************************************************************************************************
++*/
++typedef struct _ADDR_DEBUGPRINT_INPUT
++{
++    UINT_32             size;           ///< Size of this structure in bytes
++
++    CHAR*               pDebugString;   ///< Debug print string
++    va_list             ap;             ///< Variable argument list
++    ADDR_CLIENT_HANDLE  hClient;        ///< Client handle
++} ADDR_DEBUGPRINT_INPUT;
++
++/**
++***************************************************************************************************
++* ADDR_DEBUGPRINT
++*   @brief
++*       Print debug message callback function.
++*       Returns ADDR_OK on success.
++***************************************************************************************************
++*/
++typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
++    const ADDR_DEBUGPRINT_INPUT* pInput);
++
++/**
++***************************************************************************************************
++* ADDR_CALLBACKS
++*
++*   @brief
++*       Address Library needs client to provide system memory alloc/free routines.
++***************************************************************************************************
++*/
++typedef struct _ADDR_CALLBACKS
++{
++    ADDR_ALLOCSYSMEM allocSysMem;   ///< Routine to allocate system memory
++    ADDR_FREESYSMEM  freeSysMem;    ///< Routine to free system memory
++    ADDR_DEBUGPRINT  debugPrint;    ///< Routine to print debug message
++} ADDR_CALLBACKS;
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Create/Destroy functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++* ADDR_CREATE_FLAGS
++*
++*   @brief
++*       This structure is used to pass some setup in creation of AddrLib
++*   @note
++***************************************************************************************************
++*/
++typedef union _ADDR_CREATE_FLAGS
++{
++    struct
++    {
++        UINT_32 noCubeMipSlicesPad     : 1;    ///< Turn cubemap faces padding off
++        UINT_32 fillSizeFields         : 1;    ///< If clients fill size fields in all input and
++                                               ///  output structure
++        UINT_32 useTileIndex           : 1;    ///< Make tileIndex field in input valid
++        UINT_32 useCombinedSwizzle     : 1;    ///< Use combined tile swizzle
++        UINT_32 checkLast2DLevel       : 1;    ///< Check the last 2D mip sub level
++        UINT_32 useHtileSliceAlign     : 1;    ///< Do htile single slice alignment
++        UINT_32 degradeBaseLevel       : 1;    ///< Degrade to 1D modes automatically for base level
++        UINT_32 allowLargeThickTile    : 1;    ///< Allow 64*thickness*bytesPerPixel > rowSize
++        UINT_32 reserved               : 24;   ///< Reserved bits for future use
++    };
++
++    UINT_32 value;
++} ADDR_CREATE_FLAGS;
++
++/**
++***************************************************************************************************
++*   ADDR_REGISTER_VALUE
++*
++*   @brief
++*       Data from registers to setup AddrLib global data, used in AddrCreate
++***************************************************************************************************
++*/
++typedef struct _ADDR_REGISTER_VALUE
++{
++    UINT_32  gbAddrConfig;       ///< For R8xx, use GB_ADDR_CONFIG register value.
++                                 ///  For R6xx/R7xx, use GB_TILING_CONFIG.
++                                 ///  But they can be treated as the same.
++                                 ///  if this value is 0, use chip to set default value
++    UINT_32  backendDisables;    ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.
++                                 ///  Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE
++
++                                 ///  R800 registers-----------------------------------------------
++    UINT_32  noOfBanks;          ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
++                                 ///  No enums for this value in h/w header files
++                                 ///  0: 4
++                                 ///  1: 8
++                                 ///  2: 16
++    UINT_32  noOfRanks;          ///  MC_ARB_RAMCFG.NOOFRANK
++                                 ///  0: 1
++                                 ///  1: 2
++                                 ///  SI (R1000) registers-----------------------------------------
++    const UINT_32* pTileConfig;  ///< Global tile setting tables
++    UINT_32  noOfEntries;        ///< Number of entries in pTileConfig
++
++                                 ///< CI registers-------------------------------------------------
++    const UINT_32* pMacroTileConfig;    ///< Global macro tile mode table
++    UINT_32  noOfMacroEntries;   ///< Number of entries in pMacroTileConfig
++
++} ADDR_REGISTER_VALUE;
++
++/**
++***************************************************************************************************
++* ADDR_CREATE_INPUT
++*
++*   @brief
++*       Parameters use to create an AddrLib Object. Caller must provide all fields.
++*
++***************************************************************************************************
++*/
++typedef struct _ADDR_CREATE_INPUT
++{
++    UINT_32             size;                ///< Size of this structure in bytes
++
++    UINT_32             chipEngine;          ///< Chip Engine
++    UINT_32             chipFamily;          ///< Chip Family
++    UINT_32             chipRevision;        ///< Chip Revision
++    ADDR_CALLBACKS      callbacks;           ///< Callbacks for sysmem alloc/free/print
++    ADDR_CREATE_FLAGS   createFlags;         ///< Flags to setup AddrLib
++    ADDR_REGISTER_VALUE regValue;            ///< Data from registers to setup AddrLib global data
++    ADDR_CLIENT_HANDLE  hClient;             ///< Client handle
++    UINT_32             minPitchAlignPixels; ///< Minimum pitch alignment in pixels
++} ADDR_CREATE_INPUT;
++
++/**
++***************************************************************************************************
++* ADDR_CREATEINFO_OUTPUT
++*
++*   @brief
++*       Return AddrLib handle to client driver
++*
++***************************************************************************************************
++*/
++typedef struct _ADDR_CREATE_OUTPUT
++{
++    UINT_32     size;    ///< Size of this structure in bytes
++
++    ADDR_HANDLE hLib;    ///< Address lib handle
++} ADDR_CREATE_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrCreate
++*
++*   @brief
++*       Create AddrLib object, must be called before any interface calls
++*
++*   @return
++*       ADDR_OK if successful
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrCreate(
++    const ADDR_CREATE_INPUT*    pAddrCreateIn,
++    ADDR_CREATE_OUTPUT*         pAddrCreateOut);
++
++
++
++/**
++***************************************************************************************************
++*   AddrDestroy
++*
++*   @brief
++*       Destroy AddrLib object, must be called to free internally allocated resources.
++*
++*   @return
++*      ADDR_OK if successful
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrDestroy(
++    ADDR_HANDLE hLib);
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                    Surface functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++* @brief
++*       Bank/tiling parameters. On function input, these can be set as desired or
++*       left 0 for AddrLib to calculate/default. On function output, these are the actual
++*       parameters used.
++* @note
++*       Valid bankWidth/bankHeight value:
++*       1,2,4,8. They are factors instead of pixels or bytes.
++*
++*       The bank number remains constant across each row of the
++*       macro tile as each pipe is selected, so the number of
++*       tiles in the x direction with the same bank number will
++*       be bank_width * num_pipes.
++***************************************************************************************************
++*/
++typedef struct _ADDR_TILEINFO
++{
++    ///  Any of these parameters can be set to 0 to use the HW default.
++    UINT_32     banks;              ///< Number of banks, numerical value
++    UINT_32     bankWidth;          ///< Number of tiles in the X direction in the same bank
++    UINT_32     bankHeight;         ///< Number of tiles in the Y direction in the same bank
++    UINT_32     macroAspectRatio;   ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1
++    UINT_32     tileSplitBytes;     ///< Tile split size, in bytes
++    AddrPipeCfg pipeConfig;         ///< Pipe Config = HW enum + 1
++} ADDR_TILEINFO;
++
++// Create a define to avoid client change. The removal of R800 is because we plan to implement SI
++// within 800 HWL - An AddrPipeCfg is added in above data structure
++typedef ADDR_TILEINFO ADDR_R800_TILEINFO;
++
++/**
++***************************************************************************************************
++* @brief
++*       Information needed by quad buffer stereo support
++***************************************************************************************************
++*/
++typedef struct _ADDR_QBSTEREOINFO
++{
++    UINT_32         eyeHeight;          ///< Height (in pixel rows) to right eye
++    UINT_32         rightOffset;        ///< Offset (in bytes) to right eye
++    UINT_32         rightSwizzle;       ///< TileSwizzle for right eyes
++} ADDR_QBSTEREOINFO;
++
++/**
++***************************************************************************************************
++*   ADDR_SURFACE_FLAGS
++*
++*   @brief
++*       Surface flags
++***************************************************************************************************
++*/
++typedef union _ADDR_SURFACE_FLAGS
++{
++    struct
++    {
++        UINT_32 color         : 1; ///< Flag indicates this is a color buffer
++        UINT_32 depth         : 1; ///< Flag indicates this is a depth/stencil buffer
++        UINT_32 stencil       : 1; ///< Flag indicates this is a stencil buffer
++        UINT_32 texture       : 1; ///< Flag indicates this is a texture
++        UINT_32 cube          : 1; ///< Flag indicates this is a cubemap
++
++        UINT_32 volume        : 1; ///< Flag indicates this is a volume texture
++        UINT_32 fmask         : 1; ///< Flag indicates this is an fmask
++        UINT_32 cubeAsArray   : 1; ///< Flag indicates if treat cubemap as arrays
++        UINT_32 compressZ     : 1; ///< Flag indicates z buffer is compressed
++        UINT_32 overlay       : 1; ///< Flag indicates this is an overlay surface
++        UINT_32 noStencil     : 1; ///< Flag indicates this depth has no separate stencil
++        UINT_32 display       : 1; ///< Flag indicates this should match display controller req.
++        UINT_32 opt4Space     : 1; ///< Flag indicates this surface should be optimized for space
++                                   ///  i.e. save some memory but may lose performance
++        UINT_32 prt           : 1; ///< Flag for partially resident texture
++        UINT_32 qbStereo      : 1; ///< Quad buffer stereo surface
++        UINT_32 pow2Pad       : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
++        UINT_32 interleaved   : 1; ///< Special flag for interleaved YUV surface padding
++        UINT_32 degrade4Space : 1; ///< Degrade base level's tile mode to save memory
++        UINT_32 tcCompatible  : 1; ///< Flag indicates surface needs to be shader readable
++        UINT_32 dispTileType  : 1; ///< NI: force display Tiling for 128 bit shared resoruce
++        UINT_32 dccCompatible : 1; ///< VI: whether to support dcc fast clear
++        UINT_32 czDispCompatible: 1; ///< SI+: CZ family (Carrizo) has a HW bug needs special alignment.
++                                     ///<      This flag indicates we need to follow the alignment with
++                                     ///<      CZ families or other ASICs under PX configuration + CZ.
++        UINT_32 reserved      :10; ///< Reserved bits
++    };
++
++    UINT_32 value;
++} ADDR_SURFACE_FLAGS;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SURFACE_INFO_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeSurfaceInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
++{
++    UINT_32             size;               ///< Size of this structure in bytes
++
++    AddrTileMode        tileMode;           ///< Tile mode
++    AddrFormat          format;             ///< If format is set to valid one, bpp/width/height
++                                            ///  might be overwritten
++    UINT_32             bpp;                ///< Bits per pixel
++    UINT_32             numSamples;         ///< Number of samples
++    UINT_32             width;              ///< Width, in pixels
++    UINT_32             height;             ///< Height, in pixels
++    UINT_32             numSlices;          ///< Number surface slice/depth,
++                                            ///  Note:
++                                            ///  For cubemap, driver clients usually set numSlices
++                                            ///  to 1 in per-face calc.
++                                            ///  For 7xx and above, we need pad faces as slices.
++                                            ///  In this case, clients should set numSlices to 6 and
++                                            ///  this is also can be turned off by createFlags when
++                                            ///  calling AddrCreate
++    UINT_32             slice;              ///< Slice index
++    UINT_32             mipLevel;           ///< Current mipmap level.
++                                            ///  Padding/tiling have different rules for level0 and
++                                            ///  sublevels
++    ADDR_SURFACE_FLAGS  flags;              ///< Surface type flags
++    UINT_32             numFrags;           ///< Number of fragments, leave it zero or the same as
++                                            ///  number of samples for normal AA; Set it to the
++                                            ///  number of fragments for EQAA
++    /// r800 and later HWL parameters
++    // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's
++    ADDR_TILEINFO*      pTileInfo;          ///< 2D tile parameters. Set to 0 to default/calculate
++    AddrTileType        tileType;           ///< Micro tiling type, not needed when tileIndex != -1
++    INT_32              tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
++                                            ///  while the global useTileIndex is set to 1
++    UINT_32             basePitch;          ///< Base level pitch in pixels, 0 means ignored, is a
++                                            ///  must for mip levels from SI+.
++                                            ///  Don't use pitch in blocks for compressed formats!
++} ADDR_COMPUTE_SURFACE_INFO_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SURFACE_INFO_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeSurfInfo
++*   @note
++        Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
++        Pixel: Original pixel
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    UINT_32         pitch;          ///< Pitch in elements (in blocks for compressed formats)
++    UINT_32         height;         ///< Height in elements (in blocks for compressed formats)
++    UINT_32         depth;          ///< Number of slice/depth
++    UINT_64         surfSize;       ///< Surface size in bytes
++    AddrTileMode    tileMode;       ///< Actual tile mode. May differ from that in input
++    UINT_32         baseAlign;      ///< Base address alignment
++    UINT_32         pitchAlign;     ///< Pitch alignment, in elements
++    UINT_32         heightAlign;    ///< Height alignment, in elements
++    UINT_32         depthAlign;     ///< Depth alignment, aligned to thickness, for 3d texture
++    UINT_32         bpp;            ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)
++    UINT_32         pixelPitch;     ///< Pitch in original pixels
++    UINT_32         pixelHeight;    ///< Height in original pixels
++    UINT_32         pixelBits;      ///< Original bits per pixel, passed from input
++    UINT_64         sliceSize;      ///< Size of slice specified by input's slice
++                                    ///  The result is controlled by surface flags & createFlags
++                                    ///  By default this value equals to surfSize for volume
++    UINT_32         pitchTileMax;   ///< PITCH_TILE_MAX value for h/w register
++    UINT_32         heightTileMax;  ///< HEIGHT_TILE_MAX value for h/w register
++    UINT_32         sliceTileMax;   ///< SLICE_TILE_MAX value for h/w register
++
++    UINT_32         numSamples;     ///< Pass the effective numSamples processed in this call
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*  pTileInfo;      ///< Tile parameters used. Filled in if 0 on input
++    AddrTileType    tileType;       ///< Micro tiling type, only valid when tileIndex != -1
++    INT_32          tileIndex;      ///< Tile index, MAY be "downgraded"
++
++    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
++    /// Special information to work around SI mipmap swizzle bug UBTS #317508
++    BOOL_32         last2DLevel;    ///< TRUE if this is the last 2D(3D) tiled
++                                    ///< Only meaningful when create flag checkLast2DLevel is set
++    /// Stereo info
++    ADDR_QBSTEREOINFO*  pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
++} ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeSurfaceInfo
++*
++*   @brief
++*       Compute surface width/height/depth/alignments and suitable tiling mode
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeSurfaceAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    UINT_32         x;                  ///< X coordinate
++    UINT_32         y;                  ///< Y coordinate
++    UINT_32         slice;              ///< Slice index
++    UINT_32         sample;             ///< Sample index, use fragment index for EQAA
++
++    UINT_32         bpp;                ///< Bits per pixel
++    UINT_32         pitch;              ///< Surface pitch, in pixels
++    UINT_32         height;             ///< Surface height, in pixels
++    UINT_32         numSlices;          ///< Surface depth
++    UINT_32         numSamples;         ///< Number of samples
++
++    AddrTileMode    tileMode;           ///< Tile mode
++    BOOL_32         isDepth;            ///< TRUE if the surface uses depth sample ordering within
++                                        ///  micro tile. Textures can also choose depth sample order
++    UINT_32         tileBase;           ///< Base offset (in bits) inside micro tile which handles
++                                        ///  the case that components are stored separately
++    UINT_32         compBits;           ///< The component bits actually needed(for planar surface)
++
++    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
++                                        ///  number of samples for normal AA; Set it to the
++                                        ///  number of fragments for EQAA
++    /// r800 and later HWL parameters
++    // Used for 1D tiling above
++    AddrTileType    tileType;           ///< See defintion of AddrTileType
++    struct
++    {
++        UINT_32     ignoreSE : 1;       ///< TRUE if shader engines are ignored. This is texture
++                                        ///  only flag. Only non-RT texture can set this to TRUE
++        UINT_32     reserved :31;       ///< Reserved for future use.
++    };
++    // 2D tiling needs following structure
++    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Client must provide all data
++    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    union
++    {
++        struct
++        {
++            UINT_32  bankSwizzle;       ///< Bank swizzle
++            UINT_32  pipeSwizzle;       ///< Pipe swizzle
++        };
++        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
++    };
++
++#if ADDR_AM_BUILD // These two fields are not valid in SW blt since no HTILE access
++    UINT_32         addr5Swizzle;       ///< ADDR5_SWIZZLE_MASK of DB_DEPTH_INFO
++    BOOL_32         is32ByteTile;       ///< Caller must have access to HTILE buffer and know if
++                                        ///  this tile is compressed to 32B
++#endif
++} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeSurfaceAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_64 addr;           ///< Byte address
++    UINT_32 bitPosition;    ///< Bit position within surfaceAddr, 0-7.
++                            ///  For surface bpp < 8, e.g. FMT_1.
++    UINT_32 prtBlockIndex;  ///< Index of a PRT tile (64K block)
++} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeSurfaceAddrFromCoord
++*
++*   @brief
++*       Compute surface address from a given coordinate.
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
++    ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeSurfaceCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    UINT_64         addr;               ///< Address in bytes
++    UINT_32         bitPosition;        ///< Bit position in addr. 0-7. for surface bpp < 8,
++                                        ///  e.g. FMT_1;
++    UINT_32         bpp;                ///< Bits per pixel
++    UINT_32         pitch;              ///< Pitch, in pixels
++    UINT_32         height;             ///< Height in pixels
++    UINT_32         numSlices;          ///< Surface depth
++    UINT_32         numSamples;         ///< Number of samples
++
++    AddrTileMode    tileMode;           ///< Tile mode
++    BOOL_32         isDepth;            ///< Surface uses depth sample ordering within micro tile.
++                                        ///  Note: Textures can choose depth sample order as well.
++    UINT_32         tileBase;           ///< Base offset (in bits) inside micro tile which handles
++                                        ///  the case that components are stored separately
++    UINT_32         compBits;           ///< The component bits actually needed(for planar surface)
++
++    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
++                                        ///  number of samples for normal AA; Set it to the
++                                        ///  number of fragments for EQAA
++    /// r800 and later HWL parameters
++    // Used for 1D tiling above
++    AddrTileType    tileType;           ///< See defintion of AddrTileType
++    struct
++    {
++        UINT_32     ignoreSE : 1;       ///< TRUE if shader engines are ignored. This is texture
++                                        ///  only flag. Only non-RT texture can set this to TRUE
++        UINT_32     reserved :31;       ///< Reserved for future use.
++    };
++    // 2D tiling needs following structure
++    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Client must provide all data
++    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    union
++    {
++        struct
++        {
++            UINT_32  bankSwizzle;       ///< Bank swizzle
++            UINT_32  pipeSwizzle;       ///< Pipe swizzle
++        };
++        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
++    };
++} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeSurfaceCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
++{
++    UINT_32 size;   ///< Size of this structure in bytes
++
++    UINT_32 x;      ///< X coordinate
++    UINT_32 y;      ///< Y coordinate
++    UINT_32 slice;  ///< Index of slices
++    UINT_32 sample; ///< Index of samples, means fragment index for EQAA
++} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeSurfaceCoordFromAddr
++*
++*   @brief
++*       Compute coordinate from a given surface address
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
++    ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut);
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                   HTile functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   ADDR_HTILE_FLAGS
++*
++*   @brief
++*       HTILE flags
++***************************************************************************************************
++*/
++typedef union _ADDR_HTILE_FLAGS
++{
++    struct
++    {
++        UINT_32 tcCompatible  : 1; ///< Flag indicates surface needs to be shader readable
++        UINT_32 reserved      :31; ///< Reserved bits
++    };
++
++    UINT_32 value;
++} ADDR_HTILE_FLAGS;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_HTILE_INFO_INPUT
++*
++*   @brief
++*       Input structure of AddrComputeHtileInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT
++{
++    UINT_32            size;            ///< Size of this structure in bytes
++
++    ADDR_HTILE_FLAGS   flags;           ///< HTILE flags
++    UINT_32            pitch;           ///< Surface pitch, in pixels
++    UINT_32            height;          ///< Surface height, in pixels
++    UINT_32            numSlices;       ///< Number of slices
++    BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
++    AddrHtileBlockSize blockWidth;      ///< 4 or 8. EG above only support 8
++    AddrHtileBlockSize blockHeight;     ///< 4 or 8. EG above only support 8
++    ADDR_TILEINFO*     pTileInfo;       ///< Tile info
++
++    INT_32             tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    INT_32             macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
++                                        ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_HTILE_INFO_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_HTILE_INFO_OUTPUT
++*
++*   @brief
++*       Output structure of AddrComputeHtileInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_32 pitch;          ///< Pitch in pixels of depth buffer represented in this
++                            ///  HTile buffer. This might be larger than original depth
++                            ///  buffer pitch when called with an unaligned pitch.
++    UINT_32 height;         ///< Height in pixels, as above
++    UINT_64 htileBytes;     ///< Size of HTILE buffer, in bytes
++    UINT_32 baseAlign;      ///< Base alignment
++    UINT_32 bpp;            ///< Bits per pixel for HTILE is how many bits for an 8x8 block!
++    UINT_32 macroWidth;     ///< Macro width in pixels, actually squared cache shape
++    UINT_32 macroHeight;    ///< Macro height in pixels
++    UINT_64 sliceSize;      ///< Slice size, in bytes.
++} ADDR_COMPUTE_HTILE_INFO_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeHtileInfo
++*
++*   @brief
++*       Compute Htile pitch, height, base alignment and size in bytes
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_HTILE_INFO_INPUT*    pIn,
++    ADDR_COMPUTE_HTILE_INFO_OUTPUT*         pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeHtileAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
++{
++    UINT_32            size;            ///< Size of this structure in bytes
++
++    UINT_32            pitch;           ///< Pitch, in pixels
++    UINT_32            height;          ///< Height in pixels
++    UINT_32            x;               ///< X coordinate
++    UINT_32            y;               ///< Y coordinate
++    UINT_32            slice;           ///< Index of slice
++    UINT_32            numSlices;       ///< Number of slices
++    BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
++    AddrHtileBlockSize blockWidth;      ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
++    AddrHtileBlockSize blockHeight;     ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
++    ADDR_TILEINFO*     pTileInfo;       ///< Tile info
++
++    INT_32             tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    INT_32             macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
++                                        ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeHtileAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_64 addr;           ///< Address in bytes
++    UINT_32 bitPosition;    ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.
++                            ///  So we keep bitPosition for HTILE as well
++} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeHtileAddrFromCoord
++*
++*   @brief
++*       Compute Htile address according to coordinates (of depth buffer)
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*   pIn,
++    ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeHtileCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
++{
++    UINT_32            size;            ///< Size of this structure in bytes
++
++    UINT_64            addr;            ///< Address
++    UINT_32            bitPosition;     ///< Bit position 0 or 4. CMASK and HTILE share some methods
++                                        ///  so we keep bitPosition for HTILE as well
++    UINT_32            pitch;           ///< Pitch, in pixels
++    UINT_32            height;          ///< Height, in pixels
++    UINT_32            numSlices;       ///< Number of slices
++    BOOL_32            isLinear;        ///< Linear or tiled HTILE layout
++    AddrHtileBlockSize blockWidth;      ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
++    AddrHtileBlockSize blockHeight;     ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
++    ADDR_TILEINFO*     pTileInfo;       ///< Tile info
++
++    INT_32             tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    INT_32             macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
++                                        ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeHtileCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
++{
++    UINT_32 size;   ///< Size of this structure in bytes
++
++    UINT_32 x;      ///< X coordinate
++    UINT_32 y;      ///< Y coordinate
++    UINT_32 slice;  ///< Slice index
++} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeHtileCoordFromAddr
++*
++*   @brief
++*       Compute coordinates within depth buffer (1st pixel of a micro tile) according to
++*       Htile address
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*   pIn,
++    ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut);
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                     C-mask functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   ADDR_CMASK_FLAGS
++*
++*   @brief
++*       CMASK flags
++***************************************************************************************************
++*/
++typedef union _ADDR_CMASK_FLAGS
++{
++    struct
++    {
++        UINT_32 tcCompatible  : 1; ///< Flag indicates surface needs to be shader readable
++        UINT_32 reserved      :31; ///< Reserved bits
++    };
++
++    UINT_32 value;
++} ADDR_CMASK_FLAGS;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_CMASK_INFO_INPUT
++*
++*   @brief
++*       Input structure of AddrComputeCmaskInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT
++{
++    UINT_32             size;            ///< Size of this structure in bytes
++
++    ADDR_CMASK_FLAGS    flags;           ///< CMASK flags
++    UINT_32             pitch;           ///< Pitch, in pixels, of color buffer
++    UINT_32             height;          ///< Height, in pixels, of color buffer
++    UINT_32             numSlices;       ///< Number of slices, of color buffer
++    BOOL_32             isLinear;        ///< Linear or tiled layout, Only SI can be linear
++    ADDR_TILEINFO*      pTileInfo;       ///< Tile info
++
++    INT_32              tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
++                                         ///  while the global useTileIndex is set to 1
++    INT_32              macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
++                                         ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_CMASK_INFO_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_CMASK_INFO_OUTPUT
++*
++*   @brief
++*       Output structure of AddrComputeCmaskInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_32 pitch;          ///< Pitch in pixels of color buffer which
++                            ///  this Cmask matches. The size might be larger than
++                            ///  original color buffer pitch when called with
++                            ///  an unaligned pitch.
++    UINT_32 height;         ///< Height in pixels, as above
++    UINT_64 cmaskBytes;     ///< Size in bytes of CMask buffer
++    UINT_32 baseAlign;      ///< Base alignment
++    UINT_32 blockMax;       ///< Cmask block size. Need this to set CB_COLORn_MASK register
++    UINT_32 macroWidth;     ///< Macro width in pixels, actually squared cache shape
++    UINT_32 macroHeight;    ///< Macro height in pixels
++    UINT_64 sliceSize;      ///< Slice size, in bytes.
++} ADDR_COMPUTE_CMASK_INFO_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeCmaskInfo
++*
++*   @brief
++*       Compute Cmask pitch, height, base alignment and size in bytes from color buffer
++*       info
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_CMASK_INFO_INPUT*    pIn,
++    ADDR_COMPUTE_CMASK_INFO_OUTPUT*         pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeCmaskAddrFromCoord
++*
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
++{
++    UINT_32          size;           ///< Size of this structure in bytes
++    UINT_32          x;              ///< X coordinate
++    UINT_32          y;              ///< Y coordinate
++    UINT_64          fmaskAddr;      ///< Fmask addr for tc compatible Cmask
++    UINT_32          slice;          ///< Slice index
++    UINT_32          pitch;          ///< Pitch in pixels, of color buffer
++    UINT_32          height;         ///< Height in pixels, of color buffer
++    UINT_32          numSlices;      ///< Number of slices
++    UINT_32          bpp;
++    BOOL_32          isLinear;       ///< Linear or tiled layout, Only SI can be linear
++    ADDR_CMASK_FLAGS flags;          ///< CMASK flags
++    ADDR_TILEINFO*   pTileInfo;      ///< Tile info
++
++    INT_32           tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
++                                     ///< while the global useTileIndex is set to 1
++    INT_32           macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
++                                     ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeCmaskAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_64 addr;           ///< CMASK address in bytes
++    UINT_32 bitPosition;    ///< Bit position within addr, 0-7. CMASK is 4 bpp,
++                            ///  so the address may be located in bit 0 (0) or 4 (4)
++} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeCmaskAddrFromCoord
++*
++*   @brief
++*       Compute Cmask address according to coordinates (of MSAA color buffer)
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,
++    ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeCmaskCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
++{
++    UINT_32        size;            ///< Size of this structure in bytes
++
++    UINT_64        addr;            ///< CMASK address in bytes
++    UINT_32        bitPosition;     ///< Bit position within addr, 0-7. CMASK is 4 bpp,
++                                    ///  so the address may be located in bit 0 (0) or 4 (4)
++    UINT_32        pitch;           ///< Pitch, in pixels
++    UINT_32        height;          ///< Height in pixels
++    UINT_32        numSlices;       ///< Number of slices
++    BOOL_32        isLinear;        ///< Linear or tiled layout, Only SI can be linear
++    ADDR_TILEINFO* pTileInfo;       ///< Tile info
++
++    INT_32         tileIndex;       ///< Tile index, MUST be -1 if you don't want to use it
++                                    ///  while the global useTileIndex is set to 1
++    INT_32         macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
++                                    ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeCmaskCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
++{
++    UINT_32 size;   ///< Size of this structure in bytes
++
++    UINT_32 x;      ///< X coordinate
++    UINT_32 y;      ///< Y coordinate
++    UINT_32 slice;  ///< Slice index
++} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeCmaskCoordFromAddr
++*
++*   @brief
++*       Compute coordinates within color buffer (1st pixel of a micro tile) according to
++*       Cmask address
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*   pIn,
++    ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*        pOut);
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                     F-mask functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_FMASK_INFO_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeFmaskInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    AddrTileMode    tileMode;           ///< Tile mode
++    UINT_32         pitch;              ///< Surface pitch, in pixels
++    UINT_32         height;             ///< Surface height, in pixels
++    UINT_32         numSlices;          ///< Number of slice/depth
++    UINT_32         numSamples;         ///< Number of samples
++    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
++                                        ///  number of samples for normal AA; Set it to the
++                                        ///  number of fragments for EQAA
++    /// r800 and later HWL parameters
++    struct
++    {
++        UINT_32 resolved:   1;          ///< TRUE if the surface is for resolved fmask, only used
++                                        ///  by H/W clients. S/W should always set it to FALSE.
++        UINT_32 reserved:  31;          ///< Reserved for future use.
++    };
++    ADDR_TILEINFO*  pTileInfo;          ///< 2D tiling parameters. Clients must give valid data
++    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++} ADDR_COMPUTE_FMASK_INFO_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_FMASK_INFO_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeFmaskInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    UINT_32         pitch;          ///< Pitch of fmask in pixels
++    UINT_32         height;         ///< Height of fmask in pixels
++    UINT_32         numSlices;      ///< Slices of fmask
++    UINT_64         fmaskBytes;     ///< Size of fmask in bytes
++    UINT_32         baseAlign;      ///< Base address alignment
++    UINT_32         pitchAlign;     ///< Pitch alignment
++    UINT_32         heightAlign;    ///< Height alignment
++    UINT_32         bpp;            ///< Bits per pixel of FMASK is: number of bit planes
++    UINT_32         numSamples;     ///< Number of samples, used for dump, export this since input
++                                    ///  may be changed in 9xx and above
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*  pTileInfo;      ///< Tile parameters used. Fmask can have different
++                                    ///  bank_height from color buffer
++    INT_32          tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
++                                    ///  while the global useTileIndex is set to 1
++    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
++    UINT_64         sliceSize;      ///< Size of slice in bytes
++} ADDR_COMPUTE_FMASK_INFO_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeFmaskInfo
++*
++*   @brief
++*       Compute Fmask pitch/height/depth/alignments and size in bytes
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeFmaskAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    UINT_32         x;                  ///< X coordinate
++    UINT_32         y;                  ///< Y coordinate
++    UINT_32         slice;              ///< Slice index
++    UINT_32         plane;              ///< Plane number
++    UINT_32         sample;             ///< Sample index (fragment index for EQAA)
++
++    UINT_32         pitch;              ///< Surface pitch, in pixels
++    UINT_32         height;             ///< Surface height, in pixels
++    UINT_32         numSamples;         ///< Number of samples
++    UINT_32         numFrags;           ///< Number of fragments, leave it zero or the same as
++                                        ///  number of samples for normal AA; Set it to the
++                                        ///  number of fragments for EQAA
++
++    AddrTileMode    tileMode;           ///< Tile mode
++    union
++    {
++        struct
++        {
++            UINT_32  bankSwizzle;       ///< Bank swizzle
++            UINT_32  pipeSwizzle;       ///< Pipe swizzle
++        };
++        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
++    };
++
++    /// r800 and later HWL parameters
++    struct
++    {
++        UINT_32 resolved:   1;          ///< TRUE if this is a resolved fmask, used by H/W clients
++        UINT_32 ignoreSE:   1;          ///< TRUE if shader engines are ignored.
++        UINT_32 reserved:  30;          ///< Reserved for future use.
++    };
++    ADDR_TILEINFO*  pTileInfo;          ///< 2D tiling parameters. Client must provide all data
++
++} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeFmaskAddrFromCoord
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_64 addr;           ///< Fmask address
++    UINT_32 bitPosition;    ///< Bit position within fmaskAddr, 0-7.
++} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeFmaskAddrFromCoord
++*
++*   @brief
++*       Compute Fmask address according to coordinates (x,y,slice,sample,plane)
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,
++    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
++*
++*   @brief
++*       Input structure for AddrComputeFmaskCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    UINT_64         addr;               ///< Address
++    UINT_32         bitPosition;        ///< Bit position within addr, 0-7.
++
++    UINT_32         pitch;              ///< Pitch, in pixels
++    UINT_32         height;             ///< Height in pixels
++    UINT_32         numSamples;         ///< Number of samples
++    UINT_32         numFrags;           ///< Number of fragments
++    AddrTileMode    tileMode;           ///< Tile mode
++    union
++    {
++        struct
++        {
++            UINT_32  bankSwizzle;       ///< Bank swizzle
++            UINT_32  pipeSwizzle;       ///< Pipe swizzle
++        };
++        UINT_32     tileSwizzle;        ///< Combined swizzle, if useCombinedSwizzle is TRUE
++    };
++
++    /// r800 and later HWL parameters
++    struct
++    {
++        UINT_32 resolved:   1;          ///< TRUE if this is a resolved fmask, used by HW components
++        UINT_32 ignoreSE:   1;          ///< TRUE if shader engines are ignored.
++        UINT_32 reserved:  30;          ///< Reserved for future use.
++    };
++    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Client must provide all data
++
++} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
++*
++*   @brief
++*       Output structure for AddrComputeFmaskCoordFromAddr
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
++{
++    UINT_32 size;       ///< Size of this structure in bytes
++
++    UINT_32 x;          ///< X coordinate
++    UINT_32 y;          ///< Y coordinate
++    UINT_32 slice;      ///< Slice index
++    UINT_32 plane;      ///< Plane number
++    UINT_32 sample;     ///< Sample index (fragment index for EQAA)
++} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeFmaskCoordFromAddr
++*
++*   @brief
++*       Compute FMASK coordinate from an given address
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
++    ADDR_HANDLE                                     hLib,
++    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,
++    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut);
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                          Element/utility functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrGetVersion
++*
++*   @brief
++*       Get AddrLib version number
++***************************************************************************************************
++*/
++UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);
++
++/**
++***************************************************************************************************
++*   AddrUseTileIndex
++*
++*   @brief
++*       Return TRUE if tileIndex is enabled in this address library
++***************************************************************************************************
++*/
++BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
++
++/**
++***************************************************************************************************
++*   AddrUseCombinedSwizzle
++*
++*   @brief
++*       Return TRUE if combined swizzle is enabled in this address library
++***************************************************************************************************
++*/
++BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
++
++/**
++***************************************************************************************************
++*   ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
++*
++*   @brief
++*       Input structure of AddrExtractBankPipeSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    UINT_32         base256b;       ///< Base256b value
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*  pTileInfo;      ///< 2D tile parameters. Client must provide all data
++
++    INT_32          tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
++                                    ///  while the global useTileIndex is set to 1
++    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
++                                    ///< README: When tileIndex is not -1, this must be valid
++} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
++*
++*   @brief
++*       Output structure of AddrExtractBankPipeSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_32 bankSwizzle;    ///< Bank swizzle
++    UINT_32 pipeSwizzle;    ///< Pipe swizzle
++} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrExtractBankPipeSwizzle
++*
++*   @brief
++*       Extract Bank and Pipe swizzle from base256b
++*   @return
++*       ADDR_OK if no error
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
++    ADDR_HANDLE                                 hLib,
++    const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT*  pIn,
++    ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*       pOut);
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
++*
++*   @brief
++*       Input structure of AddrCombineBankPipeSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    UINT_32         bankSwizzle;    ///< Bank swizzle
++    UINT_32         pipeSwizzle;    ///< Pipe swizzle
++    UINT_64         baseAddr;       ///< Base address (leave it zero for driver clients)
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*  pTileInfo;      ///< 2D tile parameters. Client must provide all data
++
++    INT_32          tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
++                                    ///  while the global useTileIndex is set to 1
++    INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
++                                    ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
++*
++*   @brief
++*       Output structure of AddrCombineBankPipeSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_32 tileSwizzle;    ///< Combined swizzle
++} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrCombineBankPipeSwizzle
++*
++*   @brief
++*       Combine Bank and Pipe swizzle
++*   @return
++*       ADDR_OK if no error
++*   @note
++*       baseAddr here is full MCAddress instead of base256b
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
++    ADDR_HANDLE                                 hLib,
++    const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,
++    ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT*       pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SLICESWIZZLE_INPUT
++*
++*   @brief
++*       Input structure of AddrComputeSliceSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    AddrTileMode    tileMode;           ///< Tile Mode
++    UINT_32         baseSwizzle;        ///< Base tile swizzle
++    UINT_32         slice;              ///< Slice index
++    UINT_64         baseAddr;           ///< Base address, driver should leave it 0 in most cases
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*  pTileInfo;          ///< 2D tile parameters. Actually banks needed here!
++
++    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    INT_32          macroModeIndex;     ///< Index in macro tile mode table if there is one (CI)
++                                        ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_SLICESWIZZLE_INPUT;
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
++*
++*   @brief
++*       Output structure of AddrComputeSliceSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
++{
++    UINT_32  size;           ///< Size of this structure in bytes
++
++    UINT_32  tileSwizzle;    ///< Recalculated tileSwizzle value
++} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeSliceSwizzle
++*
++*   @brief
++*       Extract Bank and Pipe swizzle from base256b
++*   @return
++*       ADDR_OK if no error
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,
++    ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*       pOut);
++
++
++/**
++***************************************************************************************************
++*   AddrSwizzleGenOption
++*
++*   @brief
++*       Which swizzle generating options: legacy or linear
++***************************************************************************************************
++*/
++typedef enum _AddrSwizzleGenOption
++{
++    ADDR_SWIZZLE_GEN_DEFAULT    = 0,    ///< As is in client driver implemention for swizzle
++    ADDR_SWIZZLE_GEN_LINEAR     = 1,    ///< Using a linear increment of swizzle
++} AddrSwizzleGenOption;
++
++/**
++***************************************************************************************************
++*   AddrSwizzleOption
++*
++*   @brief
++*       Controls how swizzle is generated
++***************************************************************************************************
++*/
++typedef union _ADDR_SWIZZLE_OPTION
++{
++    struct
++    {
++        UINT_32 genOption       : 1;    ///< The way swizzle is generated, see AddrSwizzleGenOption
++        UINT_32 reduceBankBit   : 1;    ///< TRUE if we need reduce swizzle bits
++        UINT_32 reserved        :30;    ///< Reserved bits
++    };
++
++    UINT_32 value;
++
++} ADDR_SWIZZLE_OPTION;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_BASE_SWIZZLE_INPUT
++*
++*   @brief
++*       Input structure of AddrComputeBaseSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT
++{
++    UINT_32             size;           ///< Size of this structure in bytes
++
++    ADDR_SWIZZLE_OPTION option;         ///< Swizzle option
++    UINT_32             surfIndex;      ///< Index of this surface type
++    AddrTileMode        tileMode;       ///< Tile Mode
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*      pTileInfo;      ///< 2D tile parameters. Actually banks needed here!
++
++    INT_32              tileIndex;      ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    INT_32              macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
++                                        ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_BASE_SWIZZLE_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
++*
++*   @brief
++*       Output structure of AddrComputeBaseSwizzle
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_32 tileSwizzle;    ///< Combined swizzle
++} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeBaseSwizzle
++*
++*   @brief
++*       Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
++*   @return
++*       ADDR_OK if no error
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
++    ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*       pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ELEM_GETEXPORTNORM_INPUT
++*
++*   @brief
++*       Input structure for ElemGetExportNorm
++*
++***************************************************************************************************
++*/
++typedef struct _ELEM_GETEXPORTNORM_INPUT
++{
++    UINT_32             size;       ///< Size of this structure in bytes
++
++    AddrColorFormat     format;     ///< Color buffer format; Client should use ColorFormat
++    AddrSurfaceNumber   num;        ///< Surface number type; Client should use NumberType
++    AddrSurfaceSwap     swap;       ///< Surface swap byte swap; Client should use SurfaceSwap
++    UINT_32             numSamples; ///< Number of samples
++} ELEM_GETEXPORTNORM_INPUT;
++
++/**
++***************************************************************************************************
++*  ElemGetExportNorm
++*
++*   @brief
++*       Helper function to check one format can be EXPORT_NUM, which is a register
++*       CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600
++*       family
++*   @note
++*       The implementation is only for r600.
++*       00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two
++*       clocks per export)
++*       01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one
++*       clock per export)
++*
++***************************************************************************************************
++*/
++BOOL_32 ADDR_API ElemGetExportNorm(
++    ADDR_HANDLE                     hLib,
++    const ELEM_GETEXPORTNORM_INPUT* pIn);
++
++
++
++/**
++***************************************************************************************************
++*   ELEM_FLT32TODEPTHPIXEL_INPUT
++*
++*   @brief
++*       Input structure for addrFlt32ToDepthPixel
++*
++***************************************************************************************************
++*/
++typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    AddrDepthFormat format;         ///< Depth buffer format
++    ADDR_FLT_32     comps[2];       ///< Component values (Z/stencil)
++} ELEM_FLT32TODEPTHPIXEL_INPUT;
++
++/**
++***************************************************************************************************
++*   ELEM_FLT32TODEPTHPIXEL_INPUT
++*
++*   @brief
++*       Output structure for ElemFlt32ToDepthPixel
++*
++***************************************************************************************************
++*/
++typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT
++{
++    UINT_32 size;           ///< Size of this structure in bytes
++
++    UINT_8* pPixel;         ///< Real depth value. Same data type as depth buffer.
++                            ///  Client must provide enough storage for this type.
++    UINT_32 depthBase;      ///< Tile base in bits for depth bits
++    UINT_32 stencilBase;    ///< Tile base in bits for stencil bits
++    UINT_32 depthBits;      ///< Bits for depth
++    UINT_32 stencilBits;    ///< Bits for stencil
++} ELEM_FLT32TODEPTHPIXEL_OUTPUT;
++
++/**
++***************************************************************************************************
++*   ElemFlt32ToDepthPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a depth/stencil pixel value
++*
++*   @return
++*       Return code
++*
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
++    ADDR_HANDLE                         hLib,
++    const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
++    ELEM_FLT32TODEPTHPIXEL_OUTPUT*      pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ELEM_FLT32TOCOLORPIXEL_INPUT
++*
++*   @brief
++*       Input structure for addrFlt32ToColorPixel
++*
++***************************************************************************************************
++*/
++typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT
++{
++    UINT_32            size;           ///< Size of this structure in bytes
++
++    AddrColorFormat    format;         ///< Color buffer format
++    AddrSurfaceNumber  surfNum;        ///< Surface number
++    AddrSurfaceSwap    surfSwap;       ///< Surface swap
++    ADDR_FLT_32        comps[4];       ///< Component values (r/g/b/a)
++} ELEM_FLT32TOCOLORPIXEL_INPUT;
++
++/**
++***************************************************************************************************
++*   ELEM_FLT32TOCOLORPIXEL_INPUT
++*
++*   @brief
++*       Output structure for ElemFlt32ToColorPixel
++*
++***************************************************************************************************
++*/
++typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT
++{
++    UINT_32 size;       ///< Size of this structure in bytes
++
++    UINT_8* pPixel;     ///< Real color value. Same data type as color buffer.
++                        ///  Client must provide enough storage for this type.
++} ELEM_FLT32TOCOLORPIXEL_OUTPUT;
++
++/**
++***************************************************************************************************
++*   ElemFlt32ToColorPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a red/green/blue/alpha pixel value
++*
++*   @return
++*       Return code
++*
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
++    ADDR_HANDLE                         hLib,
++    const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
++    ELEM_FLT32TOCOLORPIXEL_OUTPUT*      pOut);
++
++
++/**
++***************************************************************************************************
++*   ADDR_CONVERT_TILEINFOTOHW_INPUT
++*
++*   @brief
++*       Input structure for AddrConvertTileInfoToHW
++*   @note
++*       When reverse is TRUE, indices are igonred
++***************************************************************************************************
++*/
++typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++    BOOL_32         reverse;            ///< Convert control flag.
++                                        ///  FALSE: convert from real value to HW value;
++                                        ///  TRUE: convert from HW value to real value.
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*  pTileInfo;          ///< Tile parameters with real value
++
++    INT_32          tileIndex;          ///< Tile index, MUST be -1 if you don't want to use it
++                                        ///  while the global useTileIndex is set to 1
++    INT_32          macroModeIndex;     ///< Index in macro tile mode table if there is one (CI)
++                                        ///< README: When tileIndex is not -1, this must be valid
++} ADDR_CONVERT_TILEINFOTOHW_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_CONVERT_TILEINFOTOHW_OUTPUT
++*
++*   @brief
++*       Output structure for AddrConvertTileInfoToHW
++***************************************************************************************************
++*/
++typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT
++{
++    UINT_32             size;               ///< Size of this structure in bytes
++
++    /// r800 and later HWL parameters
++    ADDR_TILEINFO*      pTileInfo;          ///< Tile parameters with hardware register value
++
++} ADDR_CONVERT_TILEINFOTOHW_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrConvertTileInfoToHW
++*
++*   @brief
++*       Convert tile info from real value to hardware register value
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
++    ADDR_HANDLE                             hLib,
++    const ADDR_CONVERT_TILEINFOTOHW_INPUT*  pIn,
++    ADDR_CONVERT_TILEINFOTOHW_OUTPUT*       pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_CONVERT_TILEINDEX_INPUT
++*
++*   @brief
++*       Input structure for AddrConvertTileIndex
++***************************************************************************************************
++*/
++typedef struct _ADDR_CONVERT_TILEINDEX_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    INT_32          tileIndex;          ///< Tile index
++    INT_32          macroModeIndex;     ///< Index in macro tile mode table if there is one (CI)
++    BOOL_32         tileInfoHw;         ///< Set to TRUE if client wants HW enum, otherwise actual
++} ADDR_CONVERT_TILEINDEX_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_CONVERT_TILEINDEX_OUTPUT
++*
++*   @brief
++*       Output structure for AddrConvertTileIndex
++***************************************************************************************************
++*/
++typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT
++{
++    UINT_32             size;           ///< Size of this structure in bytes
++
++    AddrTileMode        tileMode;       ///< Tile mode
++    AddrTileType        tileType;       ///< Tile type
++    ADDR_TILEINFO*      pTileInfo;      ///< Tile info
++
++} ADDR_CONVERT_TILEINDEX_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrConvertTileIndex
++*
++*   @brief
++*       Convert tile index to tile mode/type/info
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
++    ADDR_HANDLE                         hLib,
++    const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
++    ADDR_CONVERT_TILEINDEX_OUTPUT*      pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_CONVERT_TILEINDEX1_INPUT
++*
++*   @brief
++*       Input structure for AddrConvertTileIndex1 (without macro mode index)
++***************************************************************************************************
++*/
++typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT
++{
++    UINT_32         size;               ///< Size of this structure in bytes
++
++    INT_32          tileIndex;          ///< Tile index
++    UINT_32         bpp;                ///< Bits per pixel
++    UINT_32         numSamples;         ///< Number of samples
++    BOOL_32         tileInfoHw;         ///< Set to TRUE if client wants HW enum, otherwise actual
++} ADDR_CONVERT_TILEINDEX1_INPUT;
++
++/**
++***************************************************************************************************
++*   AddrConvertTileIndex1
++*
++*   @brief
++*       Convert tile index to tile mode/type/info
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
++    ADDR_HANDLE                             hLib,
++    const ADDR_CONVERT_TILEINDEX1_INPUT*    pIn,
++    ADDR_CONVERT_TILEINDEX_OUTPUT*          pOut);
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_GET_TILEINDEX_INPUT
++*
++*   @brief
++*       Input structure for AddrGetTileIndex
++***************************************************************************************************
++*/
++typedef struct _ADDR_GET_TILEINDEX_INPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    AddrTileMode    tileMode;       ///< Tile mode
++    AddrTileType    tileType;       ///< Tile-type: disp/non-disp/...
++    ADDR_TILEINFO*  pTileInfo;      ///< Pointer to tile-info structure, can be NULL for linear/1D
++} ADDR_GET_TILEINDEX_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_GET_TILEINDEX_OUTPUT
++*
++*   @brief
++*       Output structure for AddrGetTileIndex
++***************************************************************************************************
++*/
++typedef struct _ADDR_GET_TILEINDEX_OUTPUT
++{
++    UINT_32         size;           ///< Size of this structure in bytes
++
++    INT_32          index;          ///< index in table
++} ADDR_GET_TILEINDEX_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrGetTileIndex
++*
++*   @brief
++*       Get the tiling mode index in table
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
++    ADDR_HANDLE                     hLib,
++    const ADDR_GET_TILEINDEX_INPUT* pIn,
++    ADDR_GET_TILEINDEX_OUTPUT*      pOut);
++
++
++
++
++/**
++***************************************************************************************************
++*   ADDR_PRT_INFO_INPUT
++*
++*   @brief
++*       Input structure for AddrComputePrtInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_PRT_INFO_INPUT
++{
++    AddrFormat          format;        ///< Surface format
++    UINT_32             baseMipWidth;  ///< Base mipmap width
++    UINT_32             baseMipHeight; ///< Base mipmap height
++    UINT_32             baseMipDepth;  ///< Base mipmap depth
++    UINT_32             numFrags;      ///< Number of fragments,
++} ADDR_PRT_INFO_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_PRT_INFO_OUTPUT
++*
++*   @brief
++*       Input structure for AddrComputePrtInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_PRT_INFO_OUTPUT
++{
++    UINT_32             prtTileWidth;
++    UINT_32             prtTileHeight;
++} ADDR_PRT_INFO_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputePrtInfo
++*
++*   @brief
++*       Compute prt surface related information
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
++    ADDR_HANDLE                 hLib,
++    const ADDR_PRT_INFO_INPUT*  pIn,
++    ADDR_PRT_INFO_OUTPUT*       pOut);
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                                     DCC key functions
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   _ADDR_COMPUTE_DCCINFO_INPUT
++*
++*   @brief
++*       Input structure of AddrComputeDccInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
++{
++    UINT_32             size;            ///< Size of this structure in bytes
++    UINT_32             bpp;             ///< BitPP of color surface
++    UINT_32             numSamples;      ///< Sample number of color surface
++    UINT_64             colorSurfSize;   ///< Size of color surface to which dcc key is bound
++    AddrTileMode        tileMode;        ///< Tile mode of color surface
++    ADDR_TILEINFO       tileInfo;        ///< Tile info of color surface
++    UINT_32             tileSwizzle;     ///< Tile swizzle
++    INT_32              tileIndex;       ///< Tile index of color surface,
++                                         ///< MUST be -1 if you don't want to use it
++                                         ///< while the global useTileIndex is set to 1
++    INT_32              macroModeIndex;  ///< Index in macro tile mode table if there is one (CI)
++                                         ///< README: When tileIndex is not -1, this must be valid
++} ADDR_COMPUTE_DCCINFO_INPUT;
++
++/**
++***************************************************************************************************
++*   ADDR_COMPUTE_DCCINFO_OUTPUT
++*
++*   @brief
++*       Output structure of AddrComputeDccInfo
++***************************************************************************************************
++*/
++typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
++{
++    UINT_32 size;                 ///< Size of this structure in bytes
++    UINT_64 dccRamBaseAlign;      ///< Base alignment of dcc key
++    UINT_64 dccRamSize;           ///< Size of dcc key
++    UINT_64 dccFastClearSize;     ///< Size of dcc key portion that can be fast cleared
++    BOOL_32 subLvlCompressible;   ///< whether sub resource is compressiable
++} ADDR_COMPUTE_DCCINFO_OUTPUT;
++
++/**
++***************************************************************************************************
++*   AddrComputeDccInfo
++*
++*   @brief
++*       Compute DCC key size, base alignment
++*       info
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
++    ADDR_HANDLE                             hLib,
++    const ADDR_COMPUTE_DCCINFO_INPUT*       pIn,
++    ADDR_COMPUTE_DCCINFO_OUTPUT*            pOut);
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif // __ADDR_INTERFACE_H__
++
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/addrtypes.h b/src/gallium/winsys/radeon/amdgpu/addrlib/addrtypes.h
+new file mode 100644
+index 0000000..4c68ac5
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/addrtypes.h
+@@ -0,0 +1,590 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrtypes.h
++* @brief Contains the helper function and constants
++***************************************************************************************************
++*/
++#ifndef __ADDR_TYPES_H__
++#define __ADDR_TYPES_H__
++
++#if defined(__APPLE__) || defined(TCORE_BUILD)
++// External definitions header maintained by Mac driver team (and TCORE team)
++// Helps address compilation issues & reduces code covered by NDA
++#include "addrExtDef.h"
++
++#else
++
++// Windows and/or Linux
++#if !defined(VOID)
++typedef void           VOID;
++#endif
++
++#if !defined(FLOAT)
++typedef float          FLOAT;
++#endif
++
++#if !defined(CHAR)
++typedef char           CHAR;
++#endif
++
++#if !defined(INT)
++typedef int            INT;
++#endif
++
++#include <stdarg.h> // va_list...etc need this header
++
++#endif // defined (__APPLE__)
++
++/**
++***************************************************************************************************
++*   Calling conventions
++***************************************************************************************************
++*/
++#ifndef ADDR_CDECL
++    #if defined(__GNUC__)
++        #define ADDR_CDECL __attribute__((cdecl))
++    #else
++        #define ADDR_CDECL __cdecl
++    #endif
++#endif
++
++#ifndef ADDR_STDCALL
++    #if defined(__GNUC__)
++        #if defined(__AMD64__)
++            #define ADDR_STDCALL
++        #else
++            #define ADDR_STDCALL __attribute__((stdcall))
++        #endif
++    #else
++        #define ADDR_STDCALL __stdcall
++    #endif
++#endif
++
++#ifndef ADDR_FASTCALL
++    #if defined(__GNUC__)
++        #define ADDR_FASTCALL __attribute__((regparm(0)))
++    #else
++        #define ADDR_FASTCALL __fastcall
++    #endif
++#endif
++
++#ifndef GC_CDECL
++    #define GC_CDECL  ADDR_CDECL
++#endif
++
++#ifndef GC_STDCALL
++    #define GC_STDCALL  ADDR_STDCALL
++#endif
++
++#ifndef GC_FASTCALL
++    #define GC_FASTCALL  ADDR_FASTCALL
++#endif
++
++
++#if defined(__GNUC__)
++    #define ADDR_INLINE static inline   // inline needs to be static to link
++#else
++    // win32, win64, other platforms
++    #define ADDR_INLINE   __inline
++#endif // #if defined(__GNUC__)
++
++#define ADDR_API ADDR_FASTCALL //default call convention is fast call
++
++/**
++***************************************************************************************************
++* Global defines used by other modules
++***************************************************************************************************
++*/
++#if !defined(TILEINDEX_INVALID)
++#define TILEINDEX_INVALID                -1
++#endif
++
++#if !defined(TILEINDEX_LINEAR_GENERAL)
++#define TILEINDEX_LINEAR_GENERAL         -2
++#endif
++
++#if !defined(TILEINDEX_LINEAR_ALIGNED)
++#define TILEINDEX_LINEAR_ALIGNED          8
++#endif
++
++/**
++***************************************************************************************************
++* Return codes
++***************************************************************************************************
++*/
++typedef enum _ADDR_E_RETURNCODE
++{
++    // General Return
++    ADDR_OK    = 0,
++    ADDR_ERROR = 1,
++
++    // Specific Errors
++    ADDR_OUTOFMEMORY,
++    ADDR_INVALIDPARAMS,
++    ADDR_NOTSUPPORTED,
++    ADDR_NOTIMPLEMENTED,
++    ADDR_PARAMSIZEMISMATCH,
++    ADDR_INVALIDGBREGVALUES,
++
++} ADDR_E_RETURNCODE;
++
++/**
++***************************************************************************************************
++* @brief
++*   Neutral enums that define tile modes for all H/W
++* @note
++*   R600/R800 tiling mode can be cast to hw enums directly but never cast into HW enum from
++*   ADDR_TM_2D_TILED_XTHICK
++*
++***************************************************************************************************
++*/
++typedef enum _AddrTileMode
++{
++    ADDR_TM_LINEAR_GENERAL      = 0,    ///< Least restrictions, pitch: multiple of 8 if not buffer
++    ADDR_TM_LINEAR_ALIGNED      = 1,    ///< Requests pitch or slice to be multiple of 64 pixels
++    ADDR_TM_1D_TILED_THIN1      = 2,    ///< Linear array of 8x8 tiles
++    ADDR_TM_1D_TILED_THICK      = 3,    ///< Linear array of 8x8x4 tiles
++    ADDR_TM_2D_TILED_THIN1      = 4,    ///< A set of macro tiles consist of 8x8 tiles
++    ADDR_TM_2D_TILED_THIN2      = 5,    ///< 600 HWL only, macro tile ratio is 1:4
++    ADDR_TM_2D_TILED_THIN4      = 6,    ///< 600 HWL only, macro tile ratio is 1:16
++    ADDR_TM_2D_TILED_THICK      = 7,    ///< A set of macro tiles consist of 8x8x4 tiles
++    ADDR_TM_2B_TILED_THIN1      = 8,    ///< 600 HWL only, with bank swap
++    ADDR_TM_2B_TILED_THIN2      = 9,    ///< 600 HWL only, with bank swap and ratio is 1:4
++    ADDR_TM_2B_TILED_THIN4      = 10,   ///< 600 HWL only, with bank swap and ratio is 1:16
++    ADDR_TM_2B_TILED_THICK      = 11,   ///< 600 HWL only, with bank swap, consists of 8x8x4 tiles
++    ADDR_TM_3D_TILED_THIN1      = 12,   ///< Macro tiling w/ pipe rotation between slices
++    ADDR_TM_3D_TILED_THICK      = 13,   ///< Macro tiling w/ pipe rotation bwtween slices, thick
++    ADDR_TM_3B_TILED_THIN1      = 14,   ///< 600 HWL only, with bank swap
++    ADDR_TM_3B_TILED_THICK      = 15,   ///< 600 HWL only, with bank swap, thick
++    ADDR_TM_2D_TILED_XTHICK     = 16,   ///< Tile is 8x8x8, valid from NI
++    ADDR_TM_3D_TILED_XTHICK     = 17,   ///< Tile is 8x8x8, valid from NI
++    ADDR_TM_POWER_SAVE          = 18,   ///< Power save mode, only used by KMD on NI
++    ADDR_TM_PRT_TILED_THIN1     = 19,   ///< No bank/pipe rotation or hashing beyond macrotile size
++    ADDR_TM_PRT_2D_TILED_THIN1  = 20,   ///< Same as 2D_TILED_THIN1, PRT only
++    ADDR_TM_PRT_3D_TILED_THIN1  = 21,   ///< Same as 3D_TILED_THIN1, PRT only
++    ADDR_TM_PRT_TILED_THICK     = 22,   ///< No bank/pipe rotation or hashing beyond macrotile size
++    ADDR_TM_PRT_2D_TILED_THICK  = 23,   ///< Same as 2D_TILED_THICK, PRT only
++    ADDR_TM_PRT_3D_TILED_THICK  = 24,   ///< Same as 3D_TILED_THICK, PRT only
++    ADDR_TM_COUNT               = 25,   ///< Must be the value of the last tile mode
++} AddrTileMode;
++
++/**
++***************************************************************************************************
++*   AddrFormat
++*
++*   @brief
++*       Neutral enum for SurfaceFormat
++*
++***************************************************************************************************
++*/
++typedef enum _AddrFormat {
++    ADDR_FMT_INVALID                              = 0x00000000,
++    ADDR_FMT_8                                    = 0x00000001,
++    ADDR_FMT_4_4                                  = 0x00000002,
++    ADDR_FMT_3_3_2                                = 0x00000003,
++    ADDR_FMT_RESERVED_4                           = 0x00000004,
++    ADDR_FMT_16                                   = 0x00000005,
++    ADDR_FMT_16_FLOAT                             = 0x00000006,
++    ADDR_FMT_8_8                                  = 0x00000007,
++    ADDR_FMT_5_6_5                                = 0x00000008,
++    ADDR_FMT_6_5_5                                = 0x00000009,
++    ADDR_FMT_1_5_5_5                              = 0x0000000a,
++    ADDR_FMT_4_4_4_4                              = 0x0000000b,
++    ADDR_FMT_5_5_5_1                              = 0x0000000c,
++    ADDR_FMT_32                                   = 0x0000000d,
++    ADDR_FMT_32_FLOAT                             = 0x0000000e,
++    ADDR_FMT_16_16                                = 0x0000000f,
++    ADDR_FMT_16_16_FLOAT                          = 0x00000010,
++    ADDR_FMT_8_24                                 = 0x00000011,
++    ADDR_FMT_8_24_FLOAT                           = 0x00000012,
++    ADDR_FMT_24_8                                 = 0x00000013,
++    ADDR_FMT_24_8_FLOAT                           = 0x00000014,
++    ADDR_FMT_10_11_11                             = 0x00000015,
++    ADDR_FMT_10_11_11_FLOAT                       = 0x00000016,
++    ADDR_FMT_11_11_10                             = 0x00000017,
++    ADDR_FMT_11_11_10_FLOAT                       = 0x00000018,
++    ADDR_FMT_2_10_10_10                           = 0x00000019,
++    ADDR_FMT_8_8_8_8                              = 0x0000001a,
++    ADDR_FMT_10_10_10_2                           = 0x0000001b,
++    ADDR_FMT_X24_8_32_FLOAT                       = 0x0000001c,
++    ADDR_FMT_32_32                                = 0x0000001d,
++    ADDR_FMT_32_32_FLOAT                          = 0x0000001e,
++    ADDR_FMT_16_16_16_16                          = 0x0000001f,
++    ADDR_FMT_16_16_16_16_FLOAT                    = 0x00000020,
++    ADDR_FMT_RESERVED_33                          = 0x00000021,
++    ADDR_FMT_32_32_32_32                          = 0x00000022,
++    ADDR_FMT_32_32_32_32_FLOAT                    = 0x00000023,
++    ADDR_FMT_RESERVED_36                          = 0x00000024,
++    ADDR_FMT_1                                    = 0x00000025,
++    ADDR_FMT_1_REVERSED                           = 0x00000026,
++    ADDR_FMT_GB_GR                                = 0x00000027,
++    ADDR_FMT_BG_RG                                = 0x00000028,
++    ADDR_FMT_32_AS_8                              = 0x00000029,
++    ADDR_FMT_32_AS_8_8                            = 0x0000002a,
++    ADDR_FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
++    ADDR_FMT_8_8_8                                = 0x0000002c,
++    ADDR_FMT_16_16_16                             = 0x0000002d,
++    ADDR_FMT_16_16_16_FLOAT                       = 0x0000002e,
++    ADDR_FMT_32_32_32                             = 0x0000002f,
++    ADDR_FMT_32_32_32_FLOAT                       = 0x00000030,
++    ADDR_FMT_BC1                                  = 0x00000031,
++    ADDR_FMT_BC2                                  = 0x00000032,
++    ADDR_FMT_BC3                                  = 0x00000033,
++    ADDR_FMT_BC4                                  = 0x00000034,
++    ADDR_FMT_BC5                                  = 0x00000035,
++    ADDR_FMT_BC6                                  = 0x00000036,
++    ADDR_FMT_BC7                                  = 0x00000037,
++    ADDR_FMT_32_AS_32_32_32_32                    = 0x00000038,
++    ADDR_FMT_APC3                                 = 0x00000039,
++    ADDR_FMT_APC4                                 = 0x0000003a,
++    ADDR_FMT_APC5                                 = 0x0000003b,
++    ADDR_FMT_APC6                                 = 0x0000003c,
++    ADDR_FMT_APC7                                 = 0x0000003d,
++    ADDR_FMT_CTX1                                 = 0x0000003e,
++    ADDR_FMT_RESERVED_63                          = 0x0000003f,
++} AddrFormat;
++
++/**
++***************************************************************************************************
++*   AddrDepthFormat
++*
++*   @brief
++*       Neutral enum for addrFlt32ToDepthPixel
++*
++***************************************************************************************************
++*/
++typedef enum _AddrDepthFormat
++{
++    ADDR_DEPTH_INVALID                            = 0x00000000,
++    ADDR_DEPTH_16                                 = 0x00000001,
++    ADDR_DEPTH_X8_24                              = 0x00000002,
++    ADDR_DEPTH_8_24                               = 0x00000003,
++    ADDR_DEPTH_X8_24_FLOAT                        = 0x00000004,
++    ADDR_DEPTH_8_24_FLOAT                         = 0x00000005,
++    ADDR_DEPTH_32_FLOAT                           = 0x00000006,
++    ADDR_DEPTH_X24_8_32_FLOAT                     = 0x00000007,
++
++} AddrDepthFormat;
++
++/**
++***************************************************************************************************
++*   AddrColorFormat
++*
++*   @brief
++*       Neutral enum for ColorFormat
++*
++***************************************************************************************************
++*/
++typedef enum _AddrColorFormat
++{
++    ADDR_COLOR_INVALID                            = 0x00000000,
++    ADDR_COLOR_8                                  = 0x00000001,
++    ADDR_COLOR_4_4                                = 0x00000002,
++    ADDR_COLOR_3_3_2                              = 0x00000003,
++    ADDR_COLOR_RESERVED_4                         = 0x00000004,
++    ADDR_COLOR_16                                 = 0x00000005,
++    ADDR_COLOR_16_FLOAT                           = 0x00000006,
++    ADDR_COLOR_8_8                                = 0x00000007,
++    ADDR_COLOR_5_6_5                              = 0x00000008,
++    ADDR_COLOR_6_5_5                              = 0x00000009,
++    ADDR_COLOR_1_5_5_5                            = 0x0000000a,
++    ADDR_COLOR_4_4_4_4                            = 0x0000000b,
++    ADDR_COLOR_5_5_5_1                            = 0x0000000c,
++    ADDR_COLOR_32                                 = 0x0000000d,
++    ADDR_COLOR_32_FLOAT                           = 0x0000000e,
++    ADDR_COLOR_16_16                              = 0x0000000f,
++    ADDR_COLOR_16_16_FLOAT                        = 0x00000010,
++    ADDR_COLOR_8_24                               = 0x00000011,
++    ADDR_COLOR_8_24_FLOAT                         = 0x00000012,
++    ADDR_COLOR_24_8                               = 0x00000013,
++    ADDR_COLOR_24_8_FLOAT                         = 0x00000014,
++    ADDR_COLOR_10_11_11                           = 0x00000015,
++    ADDR_COLOR_10_11_11_FLOAT                     = 0x00000016,
++    ADDR_COLOR_11_11_10                           = 0x00000017,
++    ADDR_COLOR_11_11_10_FLOAT                     = 0x00000018,
++    ADDR_COLOR_2_10_10_10                         = 0x00000019,
++    ADDR_COLOR_8_8_8_8                            = 0x0000001a,
++    ADDR_COLOR_10_10_10_2                         = 0x0000001b,
++    ADDR_COLOR_X24_8_32_FLOAT                     = 0x0000001c,
++    ADDR_COLOR_32_32                              = 0x0000001d,
++    ADDR_COLOR_32_32_FLOAT                        = 0x0000001e,
++    ADDR_COLOR_16_16_16_16                        = 0x0000001f,
++    ADDR_COLOR_16_16_16_16_FLOAT                  = 0x00000020,
++    ADDR_COLOR_RESERVED_33                        = 0x00000021,
++    ADDR_COLOR_32_32_32_32                        = 0x00000022,
++    ADDR_COLOR_32_32_32_32_FLOAT                  = 0x00000023,
++} AddrColorFormat;
++
++/**
++***************************************************************************************************
++*   AddrSurfaceNumber
++*
++*   @brief
++*       Neutral enum for SurfaceNumber
++*
++***************************************************************************************************
++*/
++typedef enum _AddrSurfaceNumber {
++    ADDR_NUMBER_UNORM                             = 0x00000000,
++    ADDR_NUMBER_SNORM                             = 0x00000001,
++    ADDR_NUMBER_USCALED                           = 0x00000002,
++    ADDR_NUMBER_SSCALED                           = 0x00000003,
++    ADDR_NUMBER_UINT                              = 0x00000004,
++    ADDR_NUMBER_SINT                              = 0x00000005,
++    ADDR_NUMBER_SRGB                              = 0x00000006,
++    ADDR_NUMBER_FLOAT                             = 0x00000007,
++} AddrSurfaceNumber;
++
++/**
++***************************************************************************************************
++*   AddrSurfaceSwap
++*
++*   @brief
++*       Neutral enum for SurfaceSwap
++*
++***************************************************************************************************
++*/
++typedef enum _AddrSurfaceSwap {
++    ADDR_SWAP_STD                                 = 0x00000000,
++    ADDR_SWAP_ALT                                 = 0x00000001,
++    ADDR_SWAP_STD_REV                             = 0x00000002,
++    ADDR_SWAP_ALT_REV                             = 0x00000003,
++} AddrSurfaceSwap;
++
++/**
++***************************************************************************************************
++*   AddrHtileBlockSize
++*
++*   @brief
++*       Size of HTILE blocks, valid values are 4 or 8 for now
++***************************************************************************************************
++*/
++typedef enum _AddrHtileBlockSize
++{
++    ADDR_HTILE_BLOCKSIZE_4 = 4,
++    ADDR_HTILE_BLOCKSIZE_8 = 8,
++} AddrHtileBlockSize;
++
++
++/**
++***************************************************************************************************
++*   AddrPipeCfg
++*
++*   @brief
++*       The pipe configuration field specifies both the number of pipes and
++*       how pipes are interleaved on the surface.
++*       The expression of number of pipes, the shader engine tile size, and packer tile size
++*       is encoded in a PIPE_CONFIG register field.
++*       In general the number of pipes usually matches the number of memory channels of the
++*       hardware configuration.
++*       For hw configurations w/ non-pow2 memory number of memory channels, it usually matches
++*       the number of ROP units(? TODO: which registers??)
++*       The enum value = hw enum + 1 which is to reserve 0 for requesting default.
++***************************************************************************************************
++*/
++typedef enum _AddrPipeCfg
++{
++    ADDR_PIPECFG_INVALID         = 0,
++    ADDR_PIPECFG_P2              = 1, /// 2 pipes,
++    ADDR_PIPECFG_P4_8x16         = 5, /// 4 pipes,
++    ADDR_PIPECFG_P4_16x16        = 6,
++    ADDR_PIPECFG_P4_16x32        = 7,
++    ADDR_PIPECFG_P4_32x32        = 8,
++    ADDR_PIPECFG_P8_16x16_8x16   = 9, /// 8 pipes
++    ADDR_PIPECFG_P8_16x32_8x16   = 10,
++    ADDR_PIPECFG_P8_32x32_8x16   = 11,
++    ADDR_PIPECFG_P8_16x32_16x16  = 12,
++    ADDR_PIPECFG_P8_32x32_16x16  = 13,
++    ADDR_PIPECFG_P8_32x32_16x32  = 14,
++    ADDR_PIPECFG_P8_32x64_32x32  = 15,
++    ADDR_PIPECFG_P16_32x32_8x16  = 17, /// 16 pipes
++    ADDR_PIPECFG_P16_32x32_16x16 = 18,
++    ADDR_PIPECFG_MAX             = 19,
++} AddrPipeCfg;
++
++/**
++***************************************************************************************************
++* AddrTileType
++*
++*   @brief
++*       Neutral enums that specifies micro tile type (MICRO_TILE_MODE)
++***************************************************************************************************
++*/
++typedef enum _AddrTileType
++{
++    ADDR_DISPLAYABLE        = 0,    ///< Displayable tiling
++    ADDR_NON_DISPLAYABLE    = 1,    ///< Non-displayable tiling, a.k.a thin micro tiling
++    ADDR_DEPTH_SAMPLE_ORDER = 2,    ///< Same as non-displayable plus depth-sample-order
++    ADDR_ROTATED            = 3,    ///< Rotated displayable tiling
++    ADDR_THICK              = 4,    ///< Thick micro-tiling, only valid for THICK and XTHICK
++} AddrTileType;
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//
++//  Type definitions: short system-independent names for address library types
++//
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++#if !defined(__APPLE__)
++
++#ifndef BOOL_32        // no bool type in C
++/// @brief Boolean type, since none is defined in C
++/// @ingroup type
++#define BOOL_32 int
++#endif
++
++#ifndef INT_32
++#define INT_32  int
++#endif
++
++#ifndef UINT_32
++#define UINT_32 unsigned int
++#endif
++
++#ifndef INT_16
++#define INT_16  short
++#endif
++
++#ifndef UINT_16
++#define UINT_16 unsigned short
++#endif
++
++#ifndef INT_8
++#define INT_8   char
++#endif
++
++#ifndef UINT_8
++#define UINT_8  unsigned char
++#endif
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++//
++//  64-bit integer types depend on the compiler
++//
++#if defined( __GNUC__ ) || defined( __WATCOMC__ )
++#define INT_64   long long
++#define UINT_64  unsigned long long
++
++#elif defined( _WIN32 )
++#define INT_64   __int64
++#define UINT_64  unsigned __int64
++
++#else
++#error Unsupported compiler and/or operating system for 64-bit integers
++
++/// @brief 64-bit signed integer type (compiler dependent)
++/// @ingroup type
++///
++/// The addrlib defines a 64-bit signed integer type for either
++/// Gnu/Watcom compilers (which use the first syntax) or for
++/// the Windows VCC compiler (which uses the second syntax).
++#define INT_64  long long OR __int64
++
++/// @brief 64-bit unsigned integer type (compiler dependent)
++/// @ingroup type
++///
++/// The addrlib defines a 64-bit unsigned integer type for either
++/// Gnu/Watcom compilers (which use the first syntax) or for
++/// the Windows VCC compiler (which uses the second syntax).
++///
++#define UINT_64  unsigned long long OR unsigned __int64
++#endif
++
++#endif // #if !defined(__APPLE__)
++
++//  ADDR64X is used to print addresses in hex form on both Windows and Linux
++//
++#if defined( __GNUC__ ) || defined( __WATCOMC__ )
++#define ADDR64X "llx"
++#define ADDR64D "lld"
++
++#elif defined( _WIN32 )
++#define ADDR64X "I64x"
++#define ADDR64D "I64d"
++
++#else
++#error Unsupported compiler and/or operating system for 64-bit integers
++
++/// @brief Addrlib device address 64-bit printf tag  (compiler dependent)
++/// @ingroup type
++///
++/// This allows printf to display an ADDR_64 for either the Windows VCC compiler
++/// (which used this value) or the Gnu/Watcom compilers (which use "llx".
++/// An example of use is printf("addr 0x%"ADDR64X"\n", address);
++///
++#define ADDR64X "llx" OR "I64x"
++#define ADDR64D "lld" OR "I64d"
++#endif
++
++
++/// @brief Union for storing a 32-bit float or 32-bit integer
++/// @ingroup type
++///
++/// This union provides a simple way to convert between a 32-bit float
++/// and a 32-bit integer. It also prevents the compiler from producing
++/// code that alters NaN values when assiging or coying floats.
++/// Therefore, all address library routines that pass or return 32-bit
++/// floating point data do so by passing or returning a FLT_32.
++///
++typedef union {
++    INT_32   i;
++    UINT_32  u;
++    float    f;
++} ADDR_FLT_32;
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//
++//  Macros for controlling linking and building on multiple systems
++//
++///////////////////////////////////////////////////////////////////////////////////////////////////
++#if defined(_MSC_VER)
++#if defined(va_copy)
++#undef va_copy  //redefine va_copy to support VC2013
++#endif
++#endif
++
++#if !defined(va_copy)
++#define va_copy(dst, src) \
++    ((void) memcpy(&(dst), &(src), sizeof(va_list)))
++#endif
++
++#endif // __ADDR_TYPES_H__
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrcommon.h b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrcommon.h
+new file mode 100644
+index 0000000..f996c9a
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrcommon.h
+@@ -0,0 +1,558 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrcommon.h
++* @brief Contains the helper function and constants
++***************************************************************************************************
++*/
++
++#ifndef __ADDR_COMMON_H__
++#define __ADDR_COMMON_H__
++
++#include "addrinterface.h"
++
++
++// ADDR_LNX_KERNEL_BUILD is for internal build
++// Moved from addrinterface.h so __KERNEL__ is not needed any more
++#if ADDR_LNX_KERNEL_BUILD // || (defined(__GNUC__) && defined(__KERNEL__))
++    #include "lnx_common_defs.h" // ported from cmmqs
++#elif !defined(__APPLE__)
++    #include <stdlib.h>
++    #include <string.h>
++#endif
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++// Common constants
++///////////////////////////////////////////////////////////////////////////////////////////////////
++static const UINT_32 MicroTileWidth      = 8;       ///< Micro tile width, for 1D and 2D tiling
++static const UINT_32 MicroTileHeight     = 8;       ///< Micro tile height, for 1D and 2D tiling
++static const UINT_32 ThickTileThickness  = 4;       ///< Micro tile thickness, for THICK modes
++static const UINT_32 XThickTileThickness = 8;       ///< Extra thick tiling thickness
++static const UINT_32 PowerSaveTileBytes  = 64;      ///< Nuber of bytes per tile for power save 64
++static const UINT_32 CmaskCacheBits      = 1024;    ///< Number of bits for CMASK cache
++static const UINT_32 CmaskElemBits       = 4;       ///< Number of bits for CMASK element
++static const UINT_32 HtileCacheBits      = 16384;   ///< Number of bits for HTILE cache 512*32
++
++static const UINT_32 MicroTilePixels     = MicroTileWidth * MicroTileHeight;
++
++static const INT_32 TileIndexInvalid        = TILEINDEX_INVALID;
++static const INT_32 TileIndexLinearGeneral  = TILEINDEX_LINEAR_GENERAL;
++static const INT_32 TileIndexNoMacroIndex   = -3;
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++// Common macros
++///////////////////////////////////////////////////////////////////////////////////////////////////
++#define BITS_PER_BYTE 8
++#define BITS_TO_BYTES(x) ( ((x) + (BITS_PER_BYTE-1)) / BITS_PER_BYTE )
++#define BYTES_TO_BITS(x) ( (x) * BITS_PER_BYTE )
++
++/// Helper macros to select a single bit from an int (undefined later in section)
++#define _BIT(v,b)      (((v) >> (b) ) & 1)
++
++/**
++***************************************************************************************************
++* @brief Enums to identify AddrLib type
++***************************************************************************************************
++*/
++enum AddrLibClass
++{
++    BASE_ADDRLIB = 0x0,
++    R600_ADDRLIB = 0x6,
++    R800_ADDRLIB = 0x8,
++    SI_ADDRLIB   = 0xa,
++    CI_ADDRLIB   = 0xb,
++};
++
++/**
++***************************************************************************************************
++* AddrChipFamily
++*
++*   @brief
++*       Neutral enums that specifies chip family.
++*
++***************************************************************************************************
++*/
++enum AddrChipFamily
++{
++    ADDR_CHIP_FAMILY_IVLD,    ///< Invalid family
++    ADDR_CHIP_FAMILY_R6XX,
++    ADDR_CHIP_FAMILY_R7XX,
++    ADDR_CHIP_FAMILY_R8XX,
++    ADDR_CHIP_FAMILY_NI,
++    ADDR_CHIP_FAMILY_SI,
++    ADDR_CHIP_FAMILY_CI,
++    ADDR_CHIP_FAMILY_VI,
++};
++
++/**
++***************************************************************************************************
++* ADDR_CONFIG_FLAGS
++*
++*   @brief
++*       This structure is used to set addr configuration flags.
++***************************************************************************************************
++*/
++union ADDR_CONFIG_FLAGS
++{
++    struct
++    {
++        /// Clients do not need to set these flags except forceLinearAligned.
++        /// There flags are set up by AddrLib inside thru AddrInitGlobalParamsFromRegister
++        UINT_32 optimalBankSwap        : 1;    ///< New bank tiling for RV770 only
++        UINT_32 noCubeMipSlicesPad     : 1;    ///< Disables faces padding for cubemap mipmaps
++        UINT_32 fillSizeFields         : 1;    ///< If clients fill size fields in all input and
++                                               ///  output structure
++        UINT_32 ignoreTileInfo         : 1;    ///< Don't use tile info structure
++        UINT_32 useTileIndex           : 1;    ///< Make tileIndex field in input valid
++        UINT_32 useCombinedSwizzle     : 1;    ///< Use combined swizzle
++        UINT_32 checkLast2DLevel       : 1;    ///< Check the last 2D mip sub level
++        UINT_32 useHtileSliceAlign     : 1;    ///< Do htile single slice alignment
++        UINT_32 degradeBaseLevel       : 1;    ///< Degrade to 1D modes automatically for base level
++        UINT_32 allowLargeThickTile    : 1;    ///< Allow 64*thickness*bytesPerPixel > rowSize
++        UINT_32 reserved               : 22;   ///< Reserved bits for future use
++    };
++
++    UINT_32 value;
++};
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++// Platform specific debug break defines
++///////////////////////////////////////////////////////////////////////////////////////////////////
++#if DEBUG
++    #if defined(__GNUC__)
++        #define ADDR_DBG_BREAK()
++    #elif defined(__APPLE__)
++        #define ADDR_DBG_BREAK()    { IOPanic("");}
++    #else
++        #define ADDR_DBG_BREAK()    { __debugbreak(); }
++    #endif
++#else
++    #define ADDR_DBG_BREAK()
++#endif
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++// Debug assertions used in AddrLib
++///////////////////////////////////////////////////////////////////////////////////////////////////
++#if DEBUG
++#define ADDR_ASSERT(__e) if ( !((__e) ? TRUE : FALSE)) { ADDR_DBG_BREAK(); }
++#define ADDR_ASSERT_ALWAYS() ADDR_DBG_BREAK()
++#define ADDR_UNHANDLED_CASE() ADDR_ASSERT(!"Unhandled case")
++#define ADDR_NOT_IMPLEMENTED() ADDR_ASSERT(!"Not implemented");
++#else //DEBUG
++#define ADDR_ASSERT(__e)
++#define ADDR_ASSERT_ALWAYS()
++#define ADDR_UNHANDLED_CASE()
++#define ADDR_NOT_IMPLEMENTED()
++#endif //DEBUG
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++// Debug print macro from legacy address library
++///////////////////////////////////////////////////////////////////////////////////////////////////
++#if DEBUG
++
++#define ADDR_PRNT(a)    AddrObject::DebugPrint a
++
++/// @brief Macro for reporting informational messages
++/// @ingroup util
++///
++/// This macro optionally prints an informational message to stdout.
++/// The first parameter is a condition -- if it is true, nothing is done.
++/// The second pararmeter MUST be a parenthesis-enclosed list of arguments,
++/// starting with a string. This is passed to printf() or an equivalent
++/// in order to format the informational message. For example,
++/// ADDR_INFO(0, ("test %d",3) ); prints out "test 3".
++///
++#define ADDR_INFO(cond, a)         \
++{ if (!(cond)) { ADDR_PRNT(a); } }
++
++
++/// @brief Macro for reporting error warning messages
++/// @ingroup util
++///
++/// This macro optionally prints an error warning message to stdout,
++/// followed by the file name and line number where the macro was called.
++/// The first parameter is a condition -- if it is true, nothing is done.
++/// The second pararmeter MUST be a parenthesis-enclosed list of arguments,
++/// starting with a string. This is passed to printf() or an equivalent
++/// in order to format the informational message. For example,
++/// ADDR_WARN(0, ("test %d",3) ); prints out "test 3" followed by
++/// a second line with the file name and line number.
++///
++#define ADDR_WARN(cond, a)         \
++{ if (!(cond))                     \
++  { ADDR_PRNT(a);                  \
++    ADDR_PRNT(("  WARNING in file %s, line %d\n", __FILE__, __LINE__)); \
++} }
++
++
++/// @brief Macro for reporting fatal error conditions
++/// @ingroup util
++///
++/// This macro optionally stops execution of the current routine
++/// after printing an error warning message to stdout,
++/// followed by the file name and line number where the macro was called.
++/// The first parameter is a condition -- if it is true, nothing is done.
++/// The second pararmeter MUST be a parenthesis-enclosed list of arguments,
++/// starting with a string. This is passed to printf() or an equivalent
++/// in order to format the informational message. For example,
++/// ADDR_EXIT(0, ("test %d",3) ); prints out "test 3" followed by
++/// a second line with the file name and line number, then stops execution.
++///
++#define ADDR_EXIT(cond, a)         \
++{ if (!(cond))                     \
++  { ADDR_PRNT(a); ADDR_DBG_BREAK();\
++} }
++
++#else // DEBUG
++
++#define ADDRDPF 1 ? (void)0 : (void)
++
++#define ADDR_PRNT(a)
++
++#define ADDR_DBG_BREAK()
++
++#define ADDR_INFO(cond, a)
++
++#define ADDR_WARN(cond, a)
++
++#define ADDR_EXIT(cond, a)
++
++#endif // DEBUG
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++// Misc helper functions
++////////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrXorReduce
++*
++*   @brief
++*       Xor the right-side numberOfBits bits of x.
++***************************************************************************************************
++*/
++static inline UINT_32 XorReduce(
++    UINT_32 x,
++    UINT_32 numberOfBits)
++{
++    UINT_32 i;
++    UINT_32 result = x & 1;
++
++    for (i=1; i<numberOfBits; i++)
++    {
++        result ^= ((x>>i) & 1);
++    }
++
++    return result;
++}
++
++/**
++***************************************************************************************************
++*   IsPow2
++*
++*   @brief
++*       Check if the size (UINT_32) is pow 2
++***************************************************************************************************
++*/
++static inline UINT_32 IsPow2(
++    UINT_32 dim)        ///< [in] dimension of miplevel
++{
++    ADDR_ASSERT(dim > 0);
++    return !(dim & (dim - 1));
++}
++
++/**
++***************************************************************************************************
++*   IsPow2
++*
++*   @brief
++*       Check if the size (UINT_64) is pow 2
++***************************************************************************************************
++*/
++static inline UINT_64 IsPow2(
++    UINT_64 dim)        ///< [in] dimension of miplevel
++{
++    ADDR_ASSERT(dim > 0);
++    return !(dim & (dim - 1));
++}
++
++/**
++***************************************************************************************************
++*   ByteAlign
++*
++*   @brief
++*       Align UINT_32 "x" to "align" alignment, "align" should be power of 2
++***************************************************************************************************
++*/
++static inline UINT_32 PowTwoAlign(
++    UINT_32 x,
++    UINT_32 align)
++{
++    //
++    // Assert that x is a power of two.
++    //
++    ADDR_ASSERT(IsPow2(align));
++    return (x + (align - 1)) & (~(align - 1));
++}
++
++/**
++***************************************************************************************************
++*   ByteAlign
++*
++*   @brief
++*       Align UINT_64 "x" to "align" alignment, "align" should be power of 2
++***************************************************************************************************
++*/
++static inline UINT_64 PowTwoAlign(
++    UINT_64 x,
++    UINT_64 align)
++{
++    //
++    // Assert that x is a power of two.
++    //
++    ADDR_ASSERT(IsPow2(align));
++    return (x + (align - 1)) & (~(align - 1));
++}
++
++/**
++***************************************************************************************************
++*   Min
++*
++*   @brief
++*       Get the min value between two unsigned values
++***************************************************************************************************
++*/
++static inline UINT_32 Min(
++    UINT_32 value1,
++    UINT_32 value2)
++{
++    return ((value1 < (value2)) ? (value1) : value2);
++}
++
++/**
++***************************************************************************************************
++*   Min
++*
++*   @brief
++*       Get the min value between two signed values
++***************************************************************************************************
++*/
++static inline INT_32 Min(
++    INT_32 value1,
++    INT_32 value2)
++{
++    return ((value1 < (value2)) ? (value1) : value2);
++}
++
++/**
++***************************************************************************************************
++*   Max
++*
++*   @brief
++*       Get the max value between two unsigned values
++***************************************************************************************************
++*/
++static inline UINT_32 Max(
++    UINT_32 value1,
++    UINT_32 value2)
++{
++    return ((value1 > (value2)) ? (value1) : value2);
++}
++
++/**
++***************************************************************************************************
++*   Max
++*
++*   @brief
++*       Get the max value between two signed values
++***************************************************************************************************
++*/
++static inline INT_32 Max(
++    INT_32 value1,
++    INT_32 value2)
++{
++    return ((value1 > (value2)) ? (value1) : value2);
++}
++
++/**
++***************************************************************************************************
++*   NextPow2
++*
++*   @brief
++*       Compute the mipmap's next level dim size
++***************************************************************************************************
++*/
++static inline UINT_32 NextPow2(
++    UINT_32 dim)        ///< [in] dimension of miplevel
++{
++    UINT_32 newDim;
++
++    newDim = 1;
++
++    if (dim > 0x7fffffff)
++    {
++        ADDR_ASSERT_ALWAYS();
++        newDim = 0x80000000;
++    }
++    else
++    {
++        while (newDim < dim)
++        {
++            newDim <<= 1;
++        }
++    }
++
++    return newDim;
++}
++
++/**
++***************************************************************************************************
++*   Log2
++*
++*   @brief
++*       Compute log of base 2
++***************************************************************************************************
++*/
++static inline UINT_32 Log2(
++    UINT_32 x)      ///< [in] the value should calculate log based 2
++{
++    UINT_32 y;
++
++    //
++    // Assert that x is a power of two.
++    //
++    ADDR_ASSERT(IsPow2(x));
++
++    y = 0;
++    while (x > 1)
++    {
++        x >>= 1;
++        y++;
++    }
++
++    return y;
++}
++
++/**
++***************************************************************************************************
++*   QLog2
++*
++*   @brief
++*       Compute log of base 2 quickly (<= 16)
++***************************************************************************************************
++*/
++static inline UINT_32 QLog2(
++    UINT_32 x)      ///< [in] the value should calculate log based 2
++{
++    ADDR_ASSERT(x <= 16);
++
++    UINT_32 y = 0;
++
++    switch (x)
++    {
++        case 1:
++            y = 0;
++            break;
++        case 2:
++            y = 1;
++            break;
++        case 4:
++            y = 2;
++            break;
++        case 8:
++            y = 3;
++            break;
++        case 16:
++            y = 4;
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++    }
++
++    return y;
++}
++
++/**
++***************************************************************************************************
++*   SafeAssign
++*
++*   @brief
++*       NULL pointer safe assignment
++***************************************************************************************************
++*/
++static inline VOID SafeAssign(
++    UINT_32*    pLVal,  ///< [in] Pointer to left val
++    UINT_32     rVal)   ///< [in] Right value
++{
++    if (pLVal)
++    {
++        *pLVal = rVal;
++    }
++}
++
++/**
++***************************************************************************************************
++*   SafeAssign
++*
++*   @brief
++*       NULL pointer safe assignment for 64bit values
++***************************************************************************************************
++*/
++static inline VOID SafeAssign(
++    UINT_64*    pLVal,  ///< [in] Pointer to left val
++    UINT_64     rVal)   ///< [in] Right value
++{
++    if (pLVal)
++    {
++        *pLVal = rVal;
++    }
++}
++
++/**
++***************************************************************************************************
++*   SafeAssign
++*
++*   @brief
++*       NULL pointer safe assignment for AddrTileMode
++***************************************************************************************************
++*/
++static inline VOID SafeAssign(
++    AddrTileMode*    pLVal, ///< [in] Pointer to left val
++    AddrTileMode     rVal)  ///< [in] Right value
++{
++    if (pLVal)
++    {
++        *pLVal = rVal;
++    }
++}
++
++#endif // __ADDR_COMMON_H__
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.cpp
+new file mode 100644
+index 0000000..eb1b7de
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.cpp
+@@ -0,0 +1,1678 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrelemlib.cpp
++* @brief Contains the class implementation for element/pixel related functions
++***************************************************************************************************
++*/
++
++#include "addrelemlib.h"
++#include "addrlib.h"
++
++
++/**
++***************************************************************************************************
++*   AddrElemLib::AddrElemLib
++*
++*   @brief
++*       constructor
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++AddrElemLib::AddrElemLib(
++    AddrLib* const pAddrLib) :  ///< [in] Parent addrlib instance pointer
++    AddrObject(pAddrLib->GetClient()),
++    m_pAddrLib(pAddrLib)
++{
++    switch (m_pAddrLib->GetAddrChipFamily())
++    {
++        case ADDR_CHIP_FAMILY_R6XX:
++            m_depthPlanarType = ADDR_DEPTH_PLANAR_R600;
++            m_fp16ExportNorm = 0;
++            break;
++        case ADDR_CHIP_FAMILY_R7XX:
++            m_depthPlanarType = ADDR_DEPTH_PLANAR_R600;
++            m_fp16ExportNorm = 1;
++            break;
++        case ADDR_CHIP_FAMILY_R8XX:
++        case ADDR_CHIP_FAMILY_NI: // Same as 8xx
++            m_depthPlanarType = ADDR_DEPTH_PLANAR_R800;
++            m_fp16ExportNorm = 1;
++            break;
++        default:
++            m_fp16ExportNorm = 1;
++            m_depthPlanarType = ADDR_DEPTH_PLANAR_R800;
++    }
++
++    m_configFlags.value = 0;
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::~AddrElemLib
++*
++*   @brief
++*       destructor
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++AddrElemLib::~AddrElemLib()
++{
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::Create
++*
++*   @brief
++*       Creates and initializes AddrLib object.
++*
++*   @return
++*       Returns point to ADDR_CREATEINFO if successful.
++***************************************************************************************************
++*/
++AddrElemLib* AddrElemLib::Create(
++    const AddrLib* const        pAddrLib)   ///< [in] Pointer of parent AddrLib instance
++{
++    AddrElemLib* pElemLib = NULL;
++
++    if (pAddrLib)
++    {
++        pElemLib = new(pAddrLib->GetClient()) AddrElemLib(const_cast<AddrLib* const>(pAddrLib));
++    }
++
++    return pElemLib;
++}
++
++/**************************************************************************************************
++*   AddrElemLib::Flt32sToInt32s
++*
++*   @brief
++*       Convert a ADDR_FLT_32 value to Int32 value
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::Flt32sToInt32s(
++    ADDR_FLT_32     value,      ///< [in] ADDR_FLT_32 value
++    UINT_32         bits,       ///< [in] nubmer of bits in value
++    AddrNumberType  numberType, ///< [in] the type of number
++    UINT_32*        pResult)    ///< [out] Int32 value
++{
++    UINT_8 round = 128;    //ADDR_ROUND_BY_HALF
++    UINT_32 uscale;
++    UINT_32 sign;
++
++    //convert each component to an INT_32
++    switch ( numberType )
++    {
++        case ADDR_NO_NUMBER:    //fall through
++        case ADDR_ZERO:         //fall through
++        case ADDR_ONE:          //fall through
++        case ADDR_EPSILON:      //fall through
++            return;        // these are zero-bit components, so don't set result
++
++        case ADDR_UINT_BITS:            // unsigned integer bit field, clamped to range
++            uscale = (1<<bits) - 1;
++            if (bits == 32)               // special case unsigned 32-bit int
++            {
++                *pResult = value.i;
++            }
++            else
++            {
++                if ((value.i < 0) || (value.u > uscale))
++                {
++                    *pResult = uscale;
++                }
++                else
++                {
++                    *pResult = value.i;
++                }
++                return;
++            }
++
++        // The algorithm used in the DB and TX differs at one value for 24-bit unorms
++        case ADDR_UNORM_R6XXDB:        // unsigned repeating fraction
++            if ((bits==24) && (value.i == 0x33000000))
++            {
++                *pResult = 1;
++                return;
++            }              // Else treat like ADDR_UNORM_R6XX
++
++        case ADDR_UNORM_R6XX:            // unsigned repeating fraction
++            if (value.f <= 0)
++            {
++                *pResult = 0;            // first clamp to [0..1]
++            }
++            else
++            {
++                if (value.f >= 1)
++                {
++                     *pResult = (1<<bits) - 1;
++                }
++                else
++                {
++                    if ((value.i | 0x87FFFFFF) == 0xFFFFFFFF)
++                    {
++                        *pResult = 0;                        // NaN, so force to 0
++                    }
++
++                    #if 0 // floating point version for documentation
++                    else
++                    {
++                        FLOAT f = value.f * ((1<<bits) - 1);
++                        *pResult = static_cast<INT_32>(f + (round/256.0f));
++                    }
++                    #endif
++                    else
++                    {
++                        ADDR_FLT_32 scaled;
++                        ADDR_FLT_32 shifted;
++                        UINT_64 truncated, rounded;
++                        UINT_32 altShift;
++                        UINT_32 mask = (1 << bits) - 1;
++                        UINT_32 half = 1 << (bits - 1);
++                        UINT_32 mant24 = (value.i & 0x7FFFFF) + 0x800000;
++                        UINT_64 temp = mant24 - (mant24>>bits) -
++                            static_cast<INT_32>((mant24 & mask) > half);
++                        UINT_32 exp8 = value.i >> 23;
++                        UINT_32 shift = 126 - exp8 + 24 - bits;
++                        UINT_64 final;
++
++                        if (shift >= 32) // This is zero, even with maximum dither add
++                        {
++                            final = 0;
++                        }
++                        else
++                        {
++                            final = ((temp<<8) + (static_cast<UINT_64>(round)<<shift)) >> (shift+8);
++                        }
++                        //ADDR_EXIT( *pResult == final,
++                        //    ("Float %x converted to %d-bit Unorm %x != bitwise %x",
++                        //     value.u, bits, (UINT_32)*pResult, (UINT_32)final) );
++                        if (final > mask)
++                        {
++                            final = mask;
++                        }
++
++                        scaled.f  = value.f * ((1<<bits) - 1);
++                        shifted.f = (scaled.f * 256);
++                        truncated = ((shifted.i&0x7FFFFF) + (INT_64)0x800000) << 8;
++                        altShift  = 126 + 24 + 8 - ((shifted.i>>23)&0xFF);
++                        truncated = (altShift > 60) ? 0 : truncated >> altShift;
++                        rounded   = static_cast<INT_32>((round + truncated) >> 8);
++                        //if (rounded > ((1<<bits) - 1))
++                        //    rounded = ((1<<bits) - 1);
++                        *pResult = static_cast<INT_32>(rounded); //(INT_32)final;
++                    }
++                }
++            }
++
++            return;
++
++        case ADDR_S8FLOAT32:    // 32-bit IEEE float, passes through NaN values
++            *pResult = value.i;
++            return;
++
++        // @@ FIX ROUNDING in this code, fix the denorm case
++        case ADDR_U4FLOATC:         // Unsigned float, 4-bit exponent. bias 15, clamped [0..1]
++            sign = (value.i >> 31) & 1;
++            if ((value.i&0x7F800000) == 0x7F800000)    // If NaN or INF:
++            {
++                if ((value.i&0x007FFFFF) != 0)             // then if NaN
++                {
++                    *pResult = 0;                       // return 0
++                }
++                else
++                {
++                    *pResult = (sign)?0:0xF00000;           // else +INF->+1, -INF->0
++                }
++                return;
++            }
++            if (value.f <= 0)
++            {
++                *pResult = 0;
++            }
++            else
++            {
++                if (value.f>=1)
++                {
++                    *pResult = 0xF << (bits-4);
++                }
++                else
++                {
++                    if ((value.i>>23) > 112 )
++                    {
++                        // 24-bit float: normalized
++                        // value.i += 1 << (22-bits+4);
++                        // round the IEEE mantissa to mantissa size
++                        // @@ NOTE: add code to support rounding
++                        value.u &= 0x7FFFFFF;             // mask off high 4 exponent bits
++                        *pResult = value.i >> (23-bits+4);// shift off unused mantissa bits
++                    }
++                    else
++                    {
++                        // 24-bit float: denormalized
++                        value.f = value.f / (1<<28) / (1<<28);
++                        value.f = value.f / (1<<28) / (1<<28);    // convert to IEEE denorm
++                        // value.i += 1 << (22-bits+4);
++                        // round the IEEE mantissa to mantissa size
++                        // @@ NOTE: add code to support rounding
++                        *pResult = value.i >> (23-bits+4);    // shift off unused mantissa bits
++                    }
++                }
++            }
++
++            return;
++
++        default:                    // invalid number mode
++            //ADDR_EXIT(0, ("Invalid AddrNumber %d", numberType) );
++            break;
++
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::Int32sToPixel
++*
++*   @brief
++*       Pack 32-bit integer values into an uncompressed pixel,
++*       in the proper order
++*
++*   @return
++*       N/A
++*
++*   @note
++*       This entry point packes four 32-bit integer values into
++*       an uncompressed pixel. The pixel values are specifies in
++*       standard order, e.g. depth/stencil. This routine asserts
++*       if called on compressed pixel.
++***************************************************************************************************
++*/
++VOID AddrElemLib::Int32sToPixel(
++    UINT_32              numComps,      ///< [in] number of components
++    UINT_32*             pComps,        ///< [in] compnents
++    UINT_32*             pCompBits,     ///< [in] total bits in each component
++    UINT_32*             pCompStart,    ///< [in] the first bit position of each component
++    ADDR_COMPONENT_FLAGS properties,    ///< [in] properties about byteAligned, exportNorm
++    UINT_32              resultBits,    ///< [in] result bits: total bpp after decompression
++    UINT_8*              pPixel)        ///< [out] a depth/stencil pixel value
++{
++    UINT_32 i;
++    UINT_32 j;
++    UINT_32 start;
++    UINT_32 size;
++    UINT_32 byte;
++    UINT_32 value = 0;
++    UINT_32 compMask;
++    UINT_32 elemMask=0;
++    UINT_32 elementXor = 0;  // address xor when reading bytes from elements
++
++
++    // @@ NOTE: assert if called on a compressed format!
++
++    if (properties.byteAligned)    // Components are all byte-sized
++    {
++        for (i = 0; i < numComps; i++)        // Then for each component
++        {
++            // Copy the bytes of the component into the element
++            start = pCompStart[i] / 8;
++            size  = pCompBits[i]  / 8;
++            for (j = 0; j < size; j++)
++            {
++                pPixel[(j+start)^elementXor] = static_cast<UINT_8>(pComps[i] >> (8*j));
++            }
++        }
++    }
++    else                        // Element is 32-bits or less, components are bit fields
++    {
++        // First, extract each component in turn and combine it into a 32-bit value
++        for (i = 0; i < numComps; i++)
++        {
++            compMask = (1 << pCompBits[i]) - 1;
++            elemMask |= compMask << pCompStart[i];
++            value |= (pComps[i] & compMask) << pCompStart[i];
++        }
++
++        // Mext, copy the masked value into the element
++        size = (resultBits + 7) / 8;
++        for (i = 0; i < size; i++)
++        {
++            byte = pPixel[i^elementXor] & ~(elemMask >> (8*i));
++            pPixel[i^elementXor] = static_cast<UINT_8>(byte | ((elemMask & value) >> (8*i)));
++        }
++    }
++}
++
++/**
++***************************************************************************************************
++*   Flt32ToDepthPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a depth/stencil pixel value
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::Flt32ToDepthPixel(
++    AddrDepthFormat     format,     ///< [in] Depth format
++    const ADDR_FLT_32   comps[2],   ///< [in] two components of depth
++    UINT_8*             pPixel      ///< [out] depth pixel value
++    ) const
++{
++    UINT_32 i;
++    UINT_32 values[2];
++    ADDR_COMPONENT_FLAGS properties;    // byteAligned, exportNorm
++    UINT_32 resultBits = 0;             // result bits: total bits per pixel after decompression
++
++    ADDR_PIXEL_FORMATINFO fmt;
++
++    // get type for each component
++    PixGetDepthCompInfo(format, &fmt);
++
++    //initialize properties
++    properties.byteAligned = TRUE;
++    properties.exportNorm  = TRUE;
++    properties.floatComp   = FALSE;
++
++    //set properties and result bits
++    for (i = 0; i < 2; i++)
++    {
++        if ((fmt.compBit[i] & 7) || (fmt.compStart[i] & 7))
++        {
++            properties.byteAligned = FALSE;
++        }
++
++        if (resultBits < fmt.compStart[i] + fmt.compBit[i])
++        {
++            resultBits = fmt.compStart[i] + fmt.compBit[i];
++        }
++
++        // Clear ADDR_EXPORT_NORM if can't be represented as 11-bit or smaller [-1..+1] format
++        if (fmt.compBit[i] > 11 || fmt.numType[i] >= ADDR_USCALED)
++        {
++            properties.exportNorm = FALSE;
++        }
++
++        // Mark if there are any floating point components
++        if ((fmt.numType[i] == ADDR_U4FLOATC) || (fmt.numType[i] >= ADDR_S8FLOAT) )
++        {
++            properties.floatComp = TRUE;
++        }
++    }
++
++    // Convert the two input floats to integer values
++    for (i = 0; i < 2; i++)
++    {
++        Flt32sToInt32s(comps[i], fmt.compBit[i], fmt.numType[i], &values[i]);
++    }
++
++    // Then pack the two integer components, in the proper order
++    Int32sToPixel(2, values, fmt.compBit, fmt.compStart, properties, resultBits, pPixel );
++
++}
++
++/**
++***************************************************************************************************
++*   Flt32ToColorPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a red/green/blue/alpha pixel value
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::Flt32ToColorPixel(
++    AddrColorFormat     format,     ///< [in] Color format
++    AddrSurfaceNumber   surfNum,    ///< [in] Surface number
++    AddrSurfaceSwap     surfSwap,   ///< [in] Surface swap
++    const ADDR_FLT_32   comps[4],   ///< [in] four components of color
++    UINT_8*             pPixel      ///< [out] a red/green/blue/alpha pixel value
++    ) const
++{
++    ADDR_PIXEL_FORMATINFO pixelInfo;
++
++    UINT_32 i;
++    UINT_32 values[4];
++    ADDR_COMPONENT_FLAGS properties;    // byteAligned, exportNorm
++    UINT_32 resultBits = 0;             // result bits: total bits per pixel after decompression
++
++    memset(&pixelInfo, 0, sizeof(ADDR_PIXEL_FORMATINFO));
++
++    PixGetColorCompInfo(format, surfNum, surfSwap, &pixelInfo);
++
++    //initialize properties
++    properties.byteAligned = TRUE;
++    properties.exportNorm  = TRUE;
++    properties.floatComp   = FALSE;
++
++    //set properties and result bits
++    for (i = 0; i < 4; i++)
++    {
++        if ( (pixelInfo.compBit[i] & 7) || (pixelInfo.compStart[i] & 7) )
++        {
++            properties.byteAligned = FALSE;
++        }
++
++        if (resultBits < pixelInfo.compStart[i] + pixelInfo.compBit[i])
++        {
++            resultBits = pixelInfo.compStart[i] + pixelInfo.compBit[i];
++        }
++
++        if (m_fp16ExportNorm)
++        {
++            // Clear ADDR_EXPORT_NORM if can't be represented as 11-bit or smaller [-1..+1] format
++            // or if it's not FP and <=16 bits
++            if (((pixelInfo.compBit[i] > 11) || (pixelInfo.numType[i] >= ADDR_USCALED))
++                && (pixelInfo.numType[i] !=ADDR_U4FLOATC))
++            {
++                properties.exportNorm = FALSE;
++            }
++        }
++        else
++        {
++            // Clear ADDR_EXPORT_NORM if can't be represented as 11-bit or smaller [-1..+1] format
++            if (pixelInfo.compBit[i] > 11 || pixelInfo.numType[i] >= ADDR_USCALED)
++            {
++                properties.exportNorm = FALSE;
++            }
++        }
++
++        // Mark if there are any floating point components
++        if ( (pixelInfo.numType[i] == ADDR_U4FLOATC) ||
++             (pixelInfo.numType[i] >= ADDR_S8FLOAT) )
++        {
++            properties.floatComp = TRUE;
++        }
++    }
++
++    // Convert the four input floats to integer values
++    for (i = 0; i < 4; i++)
++    {
++        Flt32sToInt32s(comps[i], pixelInfo.compBit[i], pixelInfo.numType[i], &values[i]);
++    }
++
++    // Then pack the four integer components, in the proper order
++    Int32sToPixel(4, values, &pixelInfo.compBit[0], &pixelInfo.compStart[0],
++                  properties, resultBits, pPixel);
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::GetCompType
++*
++*   @brief
++*       Fill per component info
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrElemLib::GetCompType(
++    AddrColorFormat         format,     ///< [in] surface format
++    AddrSurfaceNumber       numType,  ///< [in] number type
++    ADDR_PIXEL_FORMATINFO*  pInfo)       ///< [in][out] per component info out
++{
++    BOOL_32 handled = FALSE;
++
++    // Floating point formats override the number format
++    switch (format)
++    {
++        case ADDR_COLOR_16_FLOAT:            // fall through for all pure floating point format
++        case ADDR_COLOR_16_16_FLOAT:
++        case ADDR_COLOR_16_16_16_16_FLOAT:
++        case ADDR_COLOR_32_FLOAT:
++        case ADDR_COLOR_32_32_FLOAT:
++        case ADDR_COLOR_32_32_32_32_FLOAT:
++        case ADDR_COLOR_10_11_11_FLOAT:
++        case ADDR_COLOR_11_11_10_FLOAT:
++            numType = ADDR_NUMBER_FLOAT;
++            break;
++            // Special handling for the depth formats
++        case ADDR_COLOR_8_24:                // fall through for these 2 similar format
++        case ADDR_COLOR_24_8:
++            for (UINT_32 c = 0; c < 4; c++)
++            {
++                if (pInfo->compBit[c] == 8)
++                {
++                    pInfo->numType[c] = ADDR_UINT_BITS;
++                }
++                else if (pInfo->compBit[c]  == 24)
++                {
++                    pInfo->numType[c] = ADDR_UNORM_R6XX;
++                }
++                else
++                {
++                    pInfo->numType[c] = ADDR_NO_NUMBER;
++                }
++            }
++            handled = TRUE;
++            break;
++        case ADDR_COLOR_8_24_FLOAT:          // fall through for these 3 similar format
++        case ADDR_COLOR_24_8_FLOAT:
++        case ADDR_COLOR_X24_8_32_FLOAT:
++            for (UINT_32 c = 0; c < 4; c++)
++            {
++                if (pInfo->compBit[c] == 8)
++                {
++                    pInfo->numType[c] = ADDR_UINT_BITS;
++                }
++                else if (pInfo->compBit[c] == 24)
++                {
++                    pInfo->numType[c] = ADDR_U4FLOATC;
++                }
++                else if (pInfo->compBit[c] == 32)
++                {
++                    pInfo->numType[c] = ADDR_S8FLOAT32;
++                }
++                else
++                {
++                    pInfo->numType[c] = ADDR_NO_NUMBER;
++                }
++            }
++            handled = TRUE;
++            break;
++        default:
++            break;
++    }
++
++    if (!handled)
++    {
++        for (UINT_32 c = 0; c < 4; c++)
++        {
++            // Assign a number type for each component
++            AddrSurfaceNumber cnum;
++
++            // First handle default component values
++            if (pInfo->compBit[c] == 0)
++            {
++                if (c < 3)
++                {
++                    pInfo->numType[c] = ADDR_ZERO;      // Default is zero for RGB
++                }
++                else if (numType == ADDR_NUMBER_UINT || numType == ADDR_NUMBER_SINT)
++                {
++                    pInfo->numType[c] = ADDR_EPSILON;   // Alpha INT_32 bits default is 0x01
++                }
++                else
++                {
++                    pInfo->numType[c] = ADDR_ONE;       // Alpha normal default is float 1.0
++                }
++                continue;
++            }
++            // Now handle small components
++            else if (pInfo->compBit[c] == 1)
++            {
++                if (numType == ADDR_NUMBER_UINT || numType == ADDR_NUMBER_SINT)
++                {
++                    cnum = ADDR_NUMBER_UINT;
++                }
++                else
++                {
++                    cnum = ADDR_NUMBER_UNORM;
++                }
++            }
++            else
++            {
++                cnum = numType;
++            }
++
++            // If no default, set the number type fom num, compbits, and architecture
++            switch (cnum)
++            {
++                case ADDR_NUMBER_SRGB:
++                    pInfo->numType[c] = (c < 3) ? ADDR_GAMMA8_R6XX : ADDR_UNORM_R6XX;
++                    break;
++                case ADDR_NUMBER_UNORM:
++                    pInfo->numType[c] = ADDR_UNORM_R6XX;
++                    break;
++                case ADDR_NUMBER_SNORM:
++                    pInfo->numType[c] = ADDR_SNORM_R6XX;
++                    break;
++                case ADDR_NUMBER_USCALED:
++                    pInfo->numType[c] = ADDR_USCALED;  // @@ Do we need separate Pele routine?
++                    break;
++                case ADDR_NUMBER_SSCALED:
++                    pInfo->numType[c] = ADDR_SSCALED;  // @@ Do we need separate Pele routine?
++                    break;
++                case ADDR_NUMBER_FLOAT:
++                    if (pInfo->compBit[c] == 32)
++                    {
++                        pInfo->numType[c] = ADDR_S8FLOAT32;
++                    }
++                    else if (pInfo->compBit[c] == 16)
++                    {
++                        pInfo->numType[c] = ADDR_S5FLOAT;
++                    }
++                    else if (pInfo->compBit[c] >= 10)
++                    {
++                        pInfo->numType[c] = ADDR_U5FLOAT;
++                    }
++                    else
++                    {
++                        ADDR_ASSERT_ALWAYS();
++                    }
++                    break;
++                case ADDR_NUMBER_SINT:
++                    pInfo->numType[c] = ADDR_SINT_BITS;
++                    break;
++                case ADDR_NUMBER_UINT:
++                    pInfo->numType[c] = ADDR_UINT_BITS;
++                    break;
++
++                default:
++                    ADDR_ASSERT(!"Invalid number type");
++                    pInfo->numType[c] = ADDR_NO_NUMBER;
++                    break;
++             }
++        }
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::GetCompSwap
++*
++*   @brief
++*       Get components swapped for color surface
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrElemLib::GetCompSwap(
++    AddrSurfaceSwap         swap,   ///< [in] swap mode
++    ADDR_PIXEL_FORMATINFO*  pInfo)  ///< [in/out] output per component info
++{
++    switch (pInfo->comps)
++    {
++        case 4:
++            switch (swap)
++            {
++                case ADDR_SWAP_ALT:
++                    SwapComps( 0, 2, pInfo );
++                    break;    // BGRA
++                case ADDR_SWAP_STD_REV:
++                    SwapComps( 0, 3, pInfo );
++                    SwapComps( 1, 2, pInfo );
++                    break;    // ABGR
++                case ADDR_SWAP_ALT_REV:
++                    SwapComps( 0, 3, pInfo );
++                    SwapComps( 0, 2, pInfo );
++                    SwapComps( 0, 1, pInfo );
++                    break;    // ARGB
++                default:
++                    break;
++            }
++            break;
++        case 3:
++            switch (swap)
++            {
++                case ADDR_SWAP_ALT_REV:
++                    SwapComps( 0, 3, pInfo );
++                    SwapComps( 0, 2, pInfo );
++                    break;    // AGR
++                case ADDR_SWAP_STD_REV:
++                    SwapComps( 0, 2, pInfo );
++                    break;    // BGR
++                case ADDR_SWAP_ALT:
++                    SwapComps( 2, 3, pInfo );
++                    break;    // RGA
++                default:
++                    break;    // RGB
++            }
++            break;
++        case 2:
++            switch (swap)
++            {
++                case ADDR_SWAP_ALT_REV:
++                    SwapComps( 0, 1, pInfo );
++                    SwapComps( 1, 3, pInfo );
++                    break;    // AR
++                case ADDR_SWAP_STD_REV:
++                    SwapComps( 0, 1, pInfo );
++                    break;    // GR
++                case ADDR_SWAP_ALT:
++                    SwapComps( 1, 3, pInfo );
++                    break;    // RA
++                default:
++                    break;    // RG
++            }
++            break;
++        case 1:
++            switch (swap)
++            {
++                case ADDR_SWAP_ALT_REV:
++                    SwapComps( 0, 3, pInfo );
++                    break;    // A
++                case ADDR_SWAP_STD_REV:
++                    SwapComps( 0, 2, pInfo );
++                    break;    // B
++                case ADDR_SWAP_ALT:
++                    SwapComps( 0, 1, pInfo );
++                    break;    // G
++                default:
++                    break;    // R
++            }
++            break;
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::GetCompSwap
++*
++*   @brief
++*       Get components swapped for color surface
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrElemLib::SwapComps(
++    UINT_32                 c0,     ///< [in] component index 0
++    UINT_32                 c1,     ///< [in] component index 1
++    ADDR_PIXEL_FORMATINFO*  pInfo)  ///< [in/out] output per component info
++{
++    UINT_32 start;
++    UINT_32 bits;
++
++    start = pInfo->compStart[c0];
++    pInfo->compStart[c0] = pInfo->compStart[c1];
++    pInfo->compStart[c1] = start;
++
++    bits  = pInfo->compBit[c0];
++    pInfo->compBit[c0] = pInfo->compBit[c1];
++    pInfo->compBit[c1] = bits;
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::PixGetColorCompInfo
++*
++*   @brief
++*       Get per component info for color surface
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrElemLib::PixGetColorCompInfo(
++    AddrColorFormat         format, ///< [in] surface format, read from register
++    AddrSurfaceNumber       number, ///< [in] pixel number type
++    AddrSurfaceSwap         swap,   ///< [in] component swap mode
++    ADDR_PIXEL_FORMATINFO*  pInfo   ///< [out] output per component info
++    ) const
++{
++    // 1. Get componet bits
++    switch (format)
++    {
++        case ADDR_COLOR_8:
++            GetCompBits(8, 0, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_1_5_5_5:
++            GetCompBits(5, 5, 5, 1, pInfo);
++            break;
++        case ADDR_COLOR_5_6_5:
++            GetCompBits(8, 6, 5, 0, pInfo);
++            break;
++        case ADDR_COLOR_6_5_5:
++            GetCompBits(5, 5, 6, 0, pInfo);
++            break;
++        case ADDR_COLOR_8_8:
++            GetCompBits(8, 8, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_4_4_4_4:
++            GetCompBits(4, 4, 4, 4, pInfo);
++            break;
++        case ADDR_COLOR_16:
++            GetCompBits(16, 0, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_8_8_8_8:
++            GetCompBits(8, 8, 8, 8, pInfo);
++            break;
++        case ADDR_COLOR_2_10_10_10:
++            GetCompBits(10, 10, 10, 2, pInfo);
++            break;
++        case ADDR_COLOR_10_11_11:
++            GetCompBits(11, 11, 10, 0, pInfo);
++            break;
++        case ADDR_COLOR_11_11_10:
++            GetCompBits(10, 11, 11, 0, pInfo);
++            break;
++        case ADDR_COLOR_16_16:
++            GetCompBits(16, 16, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_16_16_16_16:
++            GetCompBits(16, 16, 16, 16, pInfo);
++            break;
++        case ADDR_COLOR_16_FLOAT:
++            GetCompBits(16, 0, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_16_16_FLOAT:
++            GetCompBits(16, 16, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_32_FLOAT:
++            GetCompBits(32, 0, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_32_32_FLOAT:
++            GetCompBits(32, 32, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_16_16_16_16_FLOAT:
++            GetCompBits(16, 16, 16, 16, pInfo);
++            break;
++        case ADDR_COLOR_32_32_32_32_FLOAT:
++            GetCompBits(32, 32, 32, 32, pInfo);
++            break;
++
++        case ADDR_COLOR_32:
++            GetCompBits(32, 0, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_32_32:
++            GetCompBits(32, 32, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_32_32_32_32:
++            GetCompBits(32, 32, 32, 32, pInfo);
++            break;
++        case ADDR_COLOR_10_10_10_2:
++            GetCompBits(2, 10, 10, 10, pInfo);
++            break;
++        case ADDR_COLOR_10_11_11_FLOAT:
++            GetCompBits(11, 11, 10, 0, pInfo);
++            break;
++        case ADDR_COLOR_11_11_10_FLOAT:
++            GetCompBits(10, 11, 11, 0, pInfo);
++            break;
++        case ADDR_COLOR_5_5_5_1:
++            GetCompBits(1, 5, 5, 5, pInfo);
++            break;
++        case ADDR_COLOR_3_3_2:
++            GetCompBits(2, 3, 3, 0, pInfo);
++            break;
++        case ADDR_COLOR_4_4:
++            GetCompBits(4, 4, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_8_24:
++        case ADDR_COLOR_8_24_FLOAT:  // same bit count, fall through
++            GetCompBits(24, 8, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_24_8:
++        case ADDR_COLOR_24_8_FLOAT:  // same bit count, fall through
++            GetCompBits(8, 24, 0, 0, pInfo);
++            break;
++        case ADDR_COLOR_X24_8_32_FLOAT:
++            GetCompBits(32, 8, 0, 0, pInfo);
++            break;
++
++        case ADDR_COLOR_INVALID:
++            GetCompBits(0, 0, 0, 0, pInfo);
++            break;
++        default:
++            ADDR_ASSERT(0);
++            GetCompBits(0, 0, 0, 0, pInfo);
++            break;
++    }
++
++    // 2. Get component number type
++
++    GetCompType(format, number, pInfo);
++
++    // 3. Swap components if needed
++
++    GetCompSwap(swap, pInfo);
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::PixGetDepthCompInfo
++*
++*   @brief
++*       Get per component info for depth surface
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrElemLib::PixGetDepthCompInfo(
++    AddrDepthFormat         format,     ///< [in] surface format, read from register
++    ADDR_PIXEL_FORMATINFO*  pInfo       ///< [out] output per component bits and type
++    ) const
++{
++    if (m_depthPlanarType == ADDR_DEPTH_PLANAR_R800)
++    {
++        if (format == ADDR_DEPTH_8_24_FLOAT)
++        {
++            format = ADDR_DEPTH_X24_8_32_FLOAT; // Use this format to represent R800's D24FS8
++        }
++
++        if (format == ADDR_DEPTH_X8_24_FLOAT)
++        {
++            format = ADDR_DEPTH_32_FLOAT;
++        }
++    }
++
++    switch (format)
++    {
++        case ADDR_DEPTH_16:
++            GetCompBits(16, 0, 0, 0, pInfo);
++            break;
++        case ADDR_DEPTH_8_24:
++        case ADDR_DEPTH_8_24_FLOAT:      // similar format, fall through
++            GetCompBits(24, 8, 0, 0, pInfo);
++            break;
++        case ADDR_DEPTH_X8_24:
++        case ADDR_DEPTH_X8_24_FLOAT:     // similar format, fall through
++            GetCompBits(24, 0, 0, 0, pInfo);
++            break;
++        case ADDR_DEPTH_32_FLOAT:
++            GetCompBits(32, 0, 0, 0, pInfo);
++            break;
++        case ADDR_DEPTH_X24_8_32_FLOAT:
++            GetCompBits(32, 8, 0, 0, pInfo);
++            break;
++        case ADDR_DEPTH_INVALID:
++            GetCompBits(0, 0, 0, 0, pInfo);
++            break;
++        default:
++            ADDR_ASSERT(0);
++            GetCompBits(0, 0, 0, 0, pInfo);
++            break;
++    }
++
++    switch (format)
++    {
++        case ADDR_DEPTH_16:
++            pInfo->numType [0] = ADDR_UNORM_R6XX;
++            pInfo->numType [1] = ADDR_ZERO;
++            break;
++        case ADDR_DEPTH_8_24:
++            pInfo->numType [0] = ADDR_UNORM_R6XXDB;
++            pInfo->numType [1] = ADDR_UINT_BITS;
++            break;
++        case ADDR_DEPTH_8_24_FLOAT:
++            pInfo->numType [0] = ADDR_U4FLOATC;
++            pInfo->numType [1] = ADDR_UINT_BITS;
++            break;
++        case ADDR_DEPTH_X8_24:
++            pInfo->numType [0] = ADDR_UNORM_R6XXDB;
++            pInfo->numType [1] = ADDR_ZERO;
++            break;
++        case ADDR_DEPTH_X8_24_FLOAT:
++            pInfo->numType [0] = ADDR_U4FLOATC;
++            pInfo->numType [1] = ADDR_ZERO;
++            break;
++        case ADDR_DEPTH_32_FLOAT:
++            pInfo->numType [0] = ADDR_S8FLOAT32;
++            pInfo->numType [1] = ADDR_ZERO;
++            break;
++        case ADDR_DEPTH_X24_8_32_FLOAT:
++            pInfo->numType [0] = ADDR_S8FLOAT32;
++            pInfo->numType [1] = ADDR_UINT_BITS;
++            break;
++        default:
++            pInfo->numType [0] = ADDR_NO_NUMBER;
++            pInfo->numType [1] = ADDR_NO_NUMBER;
++            break;
++    }
++
++    pInfo->numType [2] = ADDR_NO_NUMBER;
++    pInfo->numType [3] = ADDR_NO_NUMBER;
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::PixGetExportNorm
++*
++*   @brief
++*       Check if fp16 export norm can be enabled.
++*
++*   @return
++*       TRUE if this can be enabled.
++*
++***************************************************************************************************
++*/
++BOOL_32 AddrElemLib::PixGetExportNorm(
++    AddrColorFormat     colorFmt,       ///< [in] surface format, read from register
++    AddrSurfaceNumber   numberFmt,      ///< [in] pixel number type
++    AddrSurfaceSwap     swap            ///< [in] components swap type
++    ) const
++{
++    BOOL_32 enabled = TRUE;
++
++    ADDR_PIXEL_FORMATINFO formatInfo;
++
++    PixGetColorCompInfo(colorFmt, numberFmt, swap, &formatInfo);
++
++    for (UINT_32 c = 0; c < 4; c++)
++    {
++        if (m_fp16ExportNorm)
++        {
++            if (((formatInfo.compBit[c] > 11) || (formatInfo.numType[c] > ADDR_USCALED)) &&
++                (formatInfo.numType[c] != ADDR_U4FLOATC)    &&
++                (formatInfo.numType[c] != ADDR_S5FLOAT)     &&
++                (formatInfo.numType[c] != ADDR_S5FLOATM)    &&
++                (formatInfo.numType[c] != ADDR_U5FLOAT)     &&
++                (formatInfo.numType[c] != ADDR_U3FLOATM))
++            {
++                enabled = FALSE;
++                break;
++            }
++        }
++        else
++        {
++            if ((formatInfo.compBit[c] > 11) || (formatInfo.numType[c] > ADDR_USCALED))
++            {
++                enabled = FALSE;
++                break;
++            }
++        }
++    }
++
++    return enabled;
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::AdjustSurfaceInfo
++*
++*   @brief
++*       Adjust bpp/base pitch/width/height according to elemMode and expandX/Y
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::AdjustSurfaceInfo(
++    AddrElemMode    elemMode,       ///< [in] element mode
++    UINT_32         expandX,        ///< [in] decompression expansion factor in X
++    UINT_32         expandY,        ///< [in] decompression expansion factor in Y
++    UINT_32*        pBpp,           ///< [in/out] bpp
++    UINT_32*        pBasePitch,     ///< [in/out] base pitch
++    UINT_32*        pWidth,         ///< [in/out] width
++    UINT_32*        pHeight)        ///< [in/out] height
++{
++    UINT_32 packedBits;
++    UINT_32 basePitch;
++    UINT_32 width;
++    UINT_32 height;
++    UINT_32 bpp;
++    BOOL_32 bBCnFormat = FALSE;
++
++    ADDR_ASSERT(pBpp != NULL);
++    ADDR_ASSERT(pWidth != NULL && pHeight != NULL && pBasePitch != NULL);
++
++    if (pBpp)
++    {
++        bpp = *pBpp;
++
++        switch (elemMode)
++        {
++            case ADDR_EXPANDED:
++                packedBits = bpp / expandX / expandY;
++                break;
++            case ADDR_PACKED_STD: // Different bit order
++            case ADDR_PACKED_REV:
++                packedBits = bpp * expandX * expandY;
++                break;
++            case ADDR_PACKED_GBGR:
++            case ADDR_PACKED_BGRG:
++                packedBits = bpp; // 32-bit packed ==> 2 32-bit result
++                break;
++            case ADDR_PACKED_BC1: // Fall through
++            case ADDR_PACKED_BC4:
++                packedBits = 64;
++                bBCnFormat = TRUE;
++                break;
++            case ADDR_PACKED_BC2: // Fall through
++            case ADDR_PACKED_BC3: // Fall through
++            case ADDR_PACKED_BC5: // Fall through
++                bBCnFormat = TRUE;
++                packedBits = 128;
++                break;
++            case ADDR_ROUND_BY_HALF:  // Fall through
++            case ADDR_ROUND_TRUNCATE: // Fall through
++            case ADDR_ROUND_DITHER:   // Fall through
++            case ADDR_UNCOMPRESSED:
++                packedBits = bpp;
++                break;
++            default:
++                packedBits = bpp;
++                ADDR_ASSERT_ALWAYS();
++                break;
++        }
++
++        *pBpp = packedBits;
++    }
++
++    if (pWidth && pHeight && pBasePitch)
++    {
++        basePitch = *pBasePitch;
++        width     = *pWidth;
++        height    = *pHeight;
++
++        if ((expandX > 1) || (expandY > 1))
++        {
++            if (elemMode == ADDR_EXPANDED)
++            {
++                basePitch *= expandX;
++                width     *= expandX;
++                height    *= expandY;
++            }
++            else
++            {
++                // Evergreen family workaround
++                if (bBCnFormat && (m_pAddrLib->GetAddrChipFamily() == ADDR_CHIP_FAMILY_R8XX))
++                {
++                    // For BCn we now pad it to POW2 at the beginning so it is safe to
++                    // divide by 4 directly
++                    basePitch = basePitch / expandX;
++                    width     = width  / expandX;
++                    height    = height / expandY;
++#if DEBUG
++                    width     = (width == 0) ? 1 : width;
++                    height    = (height == 0) ? 1 : height;
++
++                    if ((*pWidth > PowTwoAlign(width, 8) * expandX) ||
++                        (*pHeight > PowTwoAlign(height, 8) * expandY)) // 8 is 1D tiling alignment
++                    {
++                        // if this assertion is hit we may have issues if app samples
++                        // rightmost/bottommost pixels
++                        ADDR_ASSERT_ALWAYS();
++                    }
++#endif
++                }
++                else // Not BCn format we still keep old way (FMT_1? No real test yet)
++                {
++                    basePitch = (basePitch + expandX - 1) / expandX;
++                    width     = (width + expandX - 1) / expandX;
++                    height    = (height + expandY - 1) / expandY;
++                }
++            }
++
++            *pBasePitch = basePitch; // 0 is legal value for base pitch.
++            *pWidth     = (width == 0) ? 1 : width;
++            *pHeight    = (height == 0) ? 1 : height;
++        } //if (pWidth && pHeight && pBasePitch)
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::RestoreSurfaceInfo
++*
++*   @brief
++*       Reverse operation of AdjustSurfaceInfo
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::RestoreSurfaceInfo(
++    AddrElemMode    elemMode,       ///< [in] element mode
++    UINT_32         expandX,        ///< [in] decompression expansion factor in X
++    UINT_32         expandY,        ///< [out] decompression expansion factor in Y
++    UINT_32*        pBpp,           ///< [in/out] bpp
++    UINT_32*        pWidth,         ///< [in/out] width
++    UINT_32*        pHeight)        ///< [in/out] height
++{
++    UINT_32 originalBits;
++    UINT_32 width;
++    UINT_32 height;
++    UINT_32 bpp;
++
++    BOOL_32 bBCnFormat = FALSE;
++
++    ADDR_ASSERT(pBpp != NULL);
++    ADDR_ASSERT(pWidth != NULL && pHeight != NULL);
++
++    if (pBpp)
++    {
++        bpp = *pBpp;
++
++        switch (elemMode)
++        {
++        case ADDR_EXPANDED:
++            originalBits = bpp * expandX * expandY;
++            break;
++        case ADDR_PACKED_STD: // Different bit order
++        case ADDR_PACKED_REV:
++            originalBits = bpp / expandX / expandY;
++            break;
++        case ADDR_PACKED_GBGR:
++        case ADDR_PACKED_BGRG:
++            originalBits = bpp; // 32-bit packed ==> 2 32-bit result
++            break;
++        case ADDR_PACKED_BC1: // Fall through
++        case ADDR_PACKED_BC4:
++            originalBits = 64;
++            bBCnFormat = TRUE;
++            break;
++        case ADDR_PACKED_BC2: // Fall through
++        case ADDR_PACKED_BC3: // Fall through
++            case ADDR_PACKED_BC5:
++            bBCnFormat = TRUE;
++            originalBits = 128;
++            break;
++        case ADDR_ROUND_BY_HALF:  // Fall through
++        case ADDR_ROUND_TRUNCATE: // Fall through
++        case ADDR_ROUND_DITHER:   // Fall through
++        case ADDR_UNCOMPRESSED:
++            originalBits = bpp;
++            break;
++        default:
++            originalBits = bpp;
++            ADDR_ASSERT_ALWAYS();
++            break;
++        }
++
++        *pBpp = originalBits;
++    }
++
++    if (pWidth && pHeight)
++    {
++        width    = *pWidth;
++        height   = *pHeight;
++
++        if ((expandX > 1) || (expandY > 1))
++        {
++            if (elemMode == ADDR_EXPANDED)
++            {
++                width /= expandX;
++                height /= expandY;
++            }
++            else
++            {
++                width *= expandX;
++                height *= expandY;
++            }
++        }
++
++        *pWidth  = (width == 0) ? 1 : width;
++        *pHeight = (height == 0) ? 1 : height;
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::GetBitsPerPixel
++*
++*   @brief
++*       Compute the total bits per element according to a format
++*       code. For compressed formats, this is not the same as
++*       the number of bits per decompressed element.
++*
++*   @return
++*       Bits per pixel
++***************************************************************************************************
++*/
++UINT_32 AddrElemLib::GetBitsPerPixel(
++    AddrFormat          format,         ///< [in] surface format code
++    AddrElemMode*       pElemMode,      ///< [out] element mode
++    UINT_32*            pExpandX,       ///< [out] decompression expansion factor in X
++    UINT_32*            pExpandY,       ///< [out] decompression expansion factor in Y
++    UINT_32*            pUnusedBits)    ///< [out] bits unused
++{
++    UINT_32 bpp;
++    UINT_32 expandX = 1;
++    UINT_32 expandY = 1;
++    UINT_32 bitUnused = 0;
++    AddrElemMode elemMode = ADDR_UNCOMPRESSED; // default value
++
++    switch (format)
++    {
++        case ADDR_FMT_8:
++            bpp = 8;
++            break;
++        case ADDR_FMT_1_5_5_5:
++        case ADDR_FMT_5_6_5:
++        case ADDR_FMT_6_5_5:
++        case ADDR_FMT_8_8:
++        case ADDR_FMT_4_4_4_4:
++        case ADDR_FMT_16:
++        case ADDR_FMT_16_FLOAT:
++            bpp = 16;
++            break;
++        case ADDR_FMT_GB_GR: // treat as FMT_8_8
++            elemMode = ADDR_PACKED_GBGR;
++            bpp = 16;
++            break;
++        case ADDR_FMT_BG_RG: // treat as FMT_8_8
++            elemMode = ADDR_PACKED_BGRG;
++            bpp = 16;
++            break;
++        case ADDR_FMT_8_8_8_8:
++        case ADDR_FMT_2_10_10_10:
++        case ADDR_FMT_10_11_11:
++        case ADDR_FMT_11_11_10:
++        case ADDR_FMT_16_16:
++        case ADDR_FMT_16_16_FLOAT:
++        case ADDR_FMT_32:
++        case ADDR_FMT_32_FLOAT:
++        case ADDR_FMT_24_8:
++        case ADDR_FMT_24_8_FLOAT:
++            bpp = 32;
++            break;
++        case ADDR_FMT_16_16_16_16:
++        case ADDR_FMT_16_16_16_16_FLOAT:
++        case ADDR_FMT_32_32:
++        case ADDR_FMT_32_32_FLOAT:
++        case ADDR_FMT_CTX1:
++            bpp = 64;
++            break;
++        case ADDR_FMT_32_32_32_32:
++        case ADDR_FMT_32_32_32_32_FLOAT:
++            bpp = 128;
++            break;
++        case ADDR_FMT_INVALID:
++            bpp = 0;
++            break;
++        case ADDR_FMT_1_REVERSED:
++            elemMode = ADDR_PACKED_REV;
++            expandX = 8;
++            bpp = 1;
++            break;
++        case ADDR_FMT_1:
++            elemMode = ADDR_PACKED_STD;
++            expandX = 8;
++            bpp = 1;
++            break;
++        case ADDR_FMT_4_4:
++        case ADDR_FMT_3_3_2:
++            bpp = 8;
++            break;
++        case ADDR_FMT_5_5_5_1:
++            bpp = 16;
++            break;
++        case ADDR_FMT_32_AS_8:
++        case ADDR_FMT_32_AS_8_8:
++        case ADDR_FMT_8_24:
++        case ADDR_FMT_8_24_FLOAT:
++        case ADDR_FMT_10_10_10_2:
++        case ADDR_FMT_10_11_11_FLOAT:
++        case ADDR_FMT_11_11_10_FLOAT:
++        case ADDR_FMT_5_9_9_9_SHAREDEXP:
++            bpp = 32;
++            break;
++        case ADDR_FMT_X24_8_32_FLOAT:
++            bpp = 64;
++            bitUnused = 24;
++            break;
++        case ADDR_FMT_8_8_8:
++            elemMode = ADDR_EXPANDED;
++            bpp = 24;//@@ 8;      // read 3 elements per pixel
++            expandX = 3;
++            break;
++        case ADDR_FMT_16_16_16:
++        case ADDR_FMT_16_16_16_FLOAT:
++            elemMode = ADDR_EXPANDED;
++            bpp = 48;//@@ 16;      // read 3 elements per pixel
++            expandX = 3;
++            break;
++        case ADDR_FMT_32_32_32_FLOAT:
++        case ADDR_FMT_32_32_32:
++            elemMode = ADDR_EXPANDED;
++            expandX = 3;
++            bpp = 96;//@@ 32;      // read 3 elements per pixel
++            break;
++        case ADDR_FMT_BC1:
++            elemMode = ADDR_PACKED_BC1;
++            expandX = 4;
++            expandY = 4;
++            bpp = 64;
++            break;
++        case ADDR_FMT_BC4:
++            elemMode = ADDR_PACKED_BC4;
++            expandX = 4;
++            expandY = 4;
++            bpp = 64;
++            break;
++        case ADDR_FMT_BC2:
++            elemMode = ADDR_PACKED_BC2;
++            expandX = 4;
++            expandY = 4;
++            bpp = 128;
++            break;
++        case ADDR_FMT_BC3:
++            elemMode = ADDR_PACKED_BC3;
++            expandX = 4;
++            expandY = 4;
++            bpp = 128;
++            break;
++        case ADDR_FMT_BC5:
++        case ADDR_FMT_BC6: // reuse ADDR_PACKED_BC5
++        case ADDR_FMT_BC7: // reuse ADDR_PACKED_BC5
++            elemMode = ADDR_PACKED_BC5;
++            expandX = 4;
++            expandY = 4;
++            bpp = 128;
++            break;
++        default:
++            bpp = 0;
++            ADDR_ASSERT_ALWAYS();
++            break;
++            // @@ or should this be an error?
++    }
++
++    SafeAssign(pExpandX, expandX);
++    SafeAssign(pExpandY, expandY);
++    SafeAssign(pUnusedBits, bitUnused);
++    SafeAssign(reinterpret_cast<UINT_32*>(pElemMode), elemMode);
++
++    return bpp;
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::GetCompBits
++*
++*   @brief
++*       Set each component's bit size and bit start. And set element mode and number type
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::GetCompBits(
++    UINT_32 c0,                     ///< [in] bits of component 0
++    UINT_32 c1,                     ///< [in] bits of component 1
++    UINT_32 c2,                     ///< [in] bits of component 2
++    UINT_32 c3,                     ///< [in] bits of component 3
++    ADDR_PIXEL_FORMATINFO* pInfo,   ///< [out] per component info out
++    AddrElemMode elemMode)          ///< [in] element mode
++{
++    pInfo->comps = 0;
++
++    pInfo->compBit[0] = c0;
++    pInfo->compBit[1] = c1;
++    pInfo->compBit[2] = c2;
++    pInfo->compBit[3] = c3;
++
++    pInfo->compStart[0] = 0;
++    pInfo->compStart[1] = c0;
++    pInfo->compStart[2] = c0+c1;
++    pInfo->compStart[3] = c0+c1+c2;
++
++    pInfo->elemMode = elemMode;
++    // still needed since component swap may depend on number of components
++    for (INT i=0; i<4; i++)
++    {
++        if (pInfo->compBit[i] == 0)
++        {
++            pInfo->compStart[i]  = 0;       // all null components start at bit 0
++            pInfo->numType[i] = ADDR_NO_NUMBER; // and have no number type
++        }
++        else
++        {
++            pInfo->comps++;
++        }
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::GetCompBits
++*
++*   @brief
++*       Set the clear color (or clear depth/stencil) for a surface
++*
++*   @note
++*       If clearColor is zero, a default clear value is used in place of comps[4].
++*       If float32 is set, full precision is used, else the mantissa is reduced to 12-bits
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrElemLib::SetClearComps(
++    ADDR_FLT_32 comps[4],   ///< [in/out] components
++    BOOL_32 clearColor,     ///< [in] TRUE if clear color is set (CLEAR_COLOR)
++    BOOL_32 float32)        ///< [in] TRUE if float32 component (BLEND_FLOAT32)
++{
++    INT_32 i;
++
++    // Use default clearvalues if clearColor is disabled
++    if (clearColor == FALSE)
++    {
++        for (i=0; i<3; i++)
++        {
++            comps[i].f = 0.0;
++        }
++        comps[3].f = 1.0;
++    }
++
++    // Otherwise use the (modified) clear value
++    else
++    {
++        for (i=0; i<4; i++)
++        {   // If full precision, use clear value unchanged
++            if (float32)
++            {
++                // Do nothing
++                //comps[i] = comps[i];
++            }
++            // Else if it is a NaN, use the standard NaN value
++            else if ((comps[i].u & 0x7FFFFFFF) > 0x7F800000)
++            {
++                comps[i].u = 0xFFC00000;
++            }
++            // Else reduce the mantissa precision
++            else
++            {
++                comps[i].u = comps[i].u & 0xFFFFF000;
++            }
++        }
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::IsBlockCompressed
++*
++*   @brief
++*       TRUE if this is block compressed format
++*
++*   @note
++*
++*   @return
++*       BOOL_32
++***************************************************************************************************
++*/
++BOOL_32 AddrElemLib::IsBlockCompressed(
++    AddrFormat format)  ///< [in] Format
++{
++    return format >= ADDR_FMT_BC1 && format <= ADDR_FMT_BC7;
++}
++
++
++/**
++***************************************************************************************************
++*   AddrElemLib::IsCompressed
++*
++*   @brief
++*       TRUE if this is block compressed format or 1 bit format
++*
++*   @note
++*
++*   @return
++*       BOOL_32
++***************************************************************************************************
++*/
++BOOL_32 AddrElemLib::IsCompressed(
++    AddrFormat format)  ///< [in] Format
++{
++    return IsBlockCompressed(format) || format == ADDR_FMT_BC1 || format == ADDR_FMT_BC7;
++}
++
++/**
++***************************************************************************************************
++*   AddrElemLib::IsExpand3x
++*
++*   @brief
++*       TRUE if this is 3x expand format
++*
++*   @note
++*
++*   @return
++*       BOOL_32
++***************************************************************************************************
++*/
++BOOL_32 AddrElemLib::IsExpand3x(
++    AddrFormat format)  ///< [in] Format
++{
++    BOOL_32 is3x = FALSE;
++
++    switch (format)
++    {
++        case ADDR_FMT_8_8_8:
++        case ADDR_FMT_16_16_16:
++        case ADDR_FMT_16_16_16_FLOAT:
++        case ADDR_FMT_32_32_32:
++        case ADDR_FMT_32_32_32_FLOAT:
++            is3x = TRUE;
++            break;
++        default:
++            break;
++    }
++
++    return is3x;
++}
++
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.h b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.h
+new file mode 100644
+index 0000000..c302b3b
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrelemlib.h
+@@ -0,0 +1,270 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrelemlib.h
++* @brief Contains the class for element/pixel related functions
++***************************************************************************************************
++*/
++
++#ifndef __ELEM_LIB_H__
++#define __ELEM_LIB_H__
++
++#include "addrinterface.h"
++#include "addrobject.h"
++#include "addrcommon.h"
++
++class AddrLib;
++
++// The masks for property bits within the Properties INT_32
++union ADDR_COMPONENT_FLAGS
++{
++    struct
++    {
++        UINT_32 byteAligned    : 1;    ///< all components are byte aligned
++        UINT_32 exportNorm     : 1;    ///< components support R6xx NORM compression
++        UINT_32 floatComp      : 1;    ///< there is at least one floating point component
++    };
++
++    UINT_32 value;
++};
++
++// Copy from legacy lib's AddrNumberType
++enum AddrNumberType
++{
++    // The following number types have the range [-1..1]
++    ADDR_NO_NUMBER,         // This component doesn't exist and has no default value
++    ADDR_EPSILON,           // Force component value to integer 0x00000001
++    ADDR_ZERO,              // Force component value to integer 0x00000000
++    ADDR_ONE,               // Force component value to floating point 1.0
++    // Above values don't have any bits per component (keep ADDR_ONE the last of these)
++
++    ADDR_UNORM,             // Unsigned normalized (repeating fraction) full precision
++    ADDR_SNORM,             // Signed normalized (repeating fraction) full precision
++    ADDR_GAMMA,             // Gamma-corrected, full precision
++
++    ADDR_UNORM_R5XXRB,      // Unsigned normalized (repeating fraction) for r5xx RB
++    ADDR_SNORM_R5XXRB,      // Signed normalized (repeating fraction) for r5xx RB
++    ADDR_GAMMA_R5XXRB,      // Gamma-corrected for r5xx RB (note: unnormalized value)
++    ADDR_UNORM_R5XXBC,      // Unsigned normalized (repeating fraction) for r5xx BC
++    ADDR_SNORM_R5XXBC,      // Signed normalized (repeating fraction) for r5xx BC
++    ADDR_GAMMA_R5XXBC,      // Gamma-corrected for r5xx BC (note: unnormalized value)
++
++    ADDR_UNORM_R6XX,        // Unsigned normalized (repeating fraction) for R6xx
++    ADDR_UNORM_R6XXDB,      // Unorms for 24-bit depth: one value differs from ADDR_UNORM_R6XX
++    ADDR_SNORM_R6XX,        // Signed normalized (repeating fraction) for R6xx
++    ADDR_GAMMA8_R6XX,       // Gamma-corrected for r6xx
++    ADDR_GAMMA8_R7XX_TP,    // Gamma-corrected for r7xx TP 12bit unorm 8.4.
++
++    ADDR_U4FLOATC,          // Unsigned float: 4-bit exponent, bias=15, no NaN, clamp [0..1]
++    ADDR_GAMMA_4SEG,        // Gamma-corrected, four segment approximation
++    ADDR_U0FIXED,           // Unsigned 0.N-bit fixed point
++
++    // The following number types have large ranges (LEAVE ADDR_USCALED first or fix Finish routine)
++    ADDR_USCALED,           // Unsigned integer converted to/from floating point
++    ADDR_SSCALED,           // Signed integer converted to/from floating point
++    ADDR_USCALED_R5XXRB,    // Unsigned integer to/from floating point for r5xx RB
++    ADDR_SSCALED_R5XXRB,    // Signed integer to/from floating point for r5xx RB
++    ADDR_UINT_BITS,         // Keep in unsigned integer form, clamped to specified range
++    ADDR_SINT_BITS,         // Keep in signed integer form, clamped to specified range
++    ADDR_UINTBITS,          // @@ remove Keep in unsigned integer form, use modulus to reduce bits
++    ADDR_SINTBITS,          // @@ remove Keep in signed integer form, use modulus to reduce bits
++
++    // The following number types and ADDR_U4FLOATC have exponents
++    // (LEAVE ADDR_S8FLOAT first or fix Finish routine)
++    ADDR_S8FLOAT,           // Signed floating point with 8-bit exponent, bias=127
++    ADDR_S8FLOAT32,         // 32-bit IEEE float, passes through NaN values
++    ADDR_S5FLOAT,           // Signed floating point with 5-bit exponent, bias=15
++    ADDR_S5FLOATM,          // Signed floating point with 5-bit exponent, bias=15, no NaN/Inf
++    ADDR_U5FLOAT,           // Signed floating point with 5-bit exponent, bias=15
++    ADDR_U3FLOATM,          // Unsigned floating point with 3-bit exponent, bias=3
++
++    ADDR_S5FIXED,           // Signed 5.N-bit fixed point, with rounding
++
++    ADDR_END_NUMBER         // Used for range comparisons
++};
++
++// Copy from legacy lib's AddrElement
++enum AddrElemMode
++{
++    // These formats allow both packing an unpacking
++    ADDR_ROUND_BY_HALF,     // add 1/2 and truncate when packing this element
++    ADDR_ROUND_TRUNCATE,    // truncate toward 0 for sign/mag, else toward neg
++    ADDR_ROUND_DITHER,      // Pack by dithering -- requires (x,y) position
++
++    // These formats only allow unpacking, no packing
++    ADDR_UNCOMPRESSED,      // Elements are not compressed: one data element per pixel/texel
++    ADDR_EXPANDED,          // Elements are split up and stored in multiple data elements
++    ADDR_PACKED_STD,        // Elements are compressed into ExpandX by ExpandY data elements
++    ADDR_PACKED_REV,        // Like ADDR_PACKED, but X order of pixels is reverved
++    ADDR_PACKED_GBGR,       // Elements are compressed 4:2:2 in G1B_G0R order (high to low)
++    ADDR_PACKED_BGRG,       // Elements are compressed 4:2:2 in BG1_RG0 order (high to low)
++    ADDR_PACKED_BC1,        // Each data element is uncompressed to a 4x4 pixel/texel array
++    ADDR_PACKED_BC2,        // Each data element is uncompressed to a 4x4 pixel/texel array
++    ADDR_PACKED_BC3,        // Each data element is uncompressed to a 4x4 pixel/texel array
++    ADDR_PACKED_BC4,        // Each data element is uncompressed to a 4x4 pixel/texel array
++    ADDR_PACKED_BC5,        // Each data element is uncompressed to a 4x4 pixel/texel array
++
++    // These formats provide various kinds of compression
++    ADDR_ZPLANE_R5XX,       // Compressed Zplane using r5xx architecture format
++    ADDR_ZPLANE_R6XX,       // Compressed Zplane using r6xx architecture format
++    //@@ Fill in the compression modes
++
++    ADDR_END_ELEMENT        // Used for range comparisons
++};
++
++enum AddrDepthPlanarType
++{
++    ADDR_DEPTH_PLANAR_NONE = 0, // No plane z/stencl
++    ADDR_DEPTH_PLANAR_R600 = 1, // R600 z and stencil planes are store within a tile
++    ADDR_DEPTH_PLANAR_R800 = 2, // R800 has separate z and stencil planes
++};
++
++/**
++***************************************************************************************************
++*   ADDR_PIXEL_FORMATINFO
++*
++*   @brief
++*       Per component info
++*
++***************************************************************************************************
++*/
++struct ADDR_PIXEL_FORMATINFO
++{
++    UINT_32             compBit[4];
++    AddrNumberType      numType[4];
++    UINT_32             compStart[4];
++    AddrElemMode        elemMode;
++    UINT_32             comps;          ///< Number of components
++};
++
++/**
++***************************************************************************************************
++* @brief This class contains asic indepentent element related attributes and operations
++***************************************************************************************************
++*/
++class AddrElemLib : public AddrObject
++{
++protected:
++    AddrElemLib(AddrLib* const pAddrLib);
++
++public:
++
++    /// Makes this class virtual
++    virtual ~AddrElemLib();
++
++    static AddrElemLib *Create(
++        const AddrLib* const pAddrLib);
++
++    /// The implementation is only for R6xx/R7xx, so make it virtual in case we need for R8xx
++    BOOL_32 PixGetExportNorm(
++        AddrColorFormat colorFmt,
++        AddrSurfaceNumber numberFmt, AddrSurfaceSwap swap) const;
++
++    /// Below method are asic independent, so make them just static.
++    /// Remove static if we need different operation in hwl.
++
++    VOID    Flt32ToDepthPixel(
++        AddrDepthFormat format, const ADDR_FLT_32 comps[2], UINT_8 *pPixel) const;
++
++    VOID    Flt32ToColorPixel(
++        AddrColorFormat format, AddrSurfaceNumber surfNum, AddrSurfaceSwap surfSwap,
++        const ADDR_FLT_32 comps[4], UINT_8 *pPixel) const;
++
++    static VOID    Flt32sToInt32s(
++        ADDR_FLT_32 value, UINT_32 bits, AddrNumberType numberType, UINT_32* pResult);
++
++    static VOID    Int32sToPixel(
++        UINT_32 numComps, UINT_32* pComps, UINT_32* pCompBits, UINT_32* pCompStart,
++        ADDR_COMPONENT_FLAGS properties, UINT_32 resultBits, UINT_8* pPixel);
++
++    VOID    PixGetColorCompInfo(
++        AddrColorFormat format, AddrSurfaceNumber number, AddrSurfaceSwap swap,
++        ADDR_PIXEL_FORMATINFO* pInfo) const;
++
++    VOID    PixGetDepthCompInfo(
++        AddrDepthFormat format, ADDR_PIXEL_FORMATINFO* pInfo) const;
++
++    UINT_32 GetBitsPerPixel(
++        AddrFormat format, AddrElemMode* pElemMode,
++        UINT_32* pExpandX = NULL, UINT_32* pExpandY = NULL, UINT_32* pBitsUnused = NULL);
++
++    static VOID    SetClearComps(
++        ADDR_FLT_32 comps[4], BOOL_32 clearColor, BOOL_32 float32);
++
++    VOID    AdjustSurfaceInfo(
++        AddrElemMode elemMode, UINT_32 expandX, UINT_32 expandY,
++        UINT_32* pBpp, UINT_32* pBasePitch, UINT_32* pWidth, UINT_32* pHeight);
++
++    VOID    RestoreSurfaceInfo(
++        AddrElemMode elemMode, UINT_32 expandX, UINT_32 expandY,
++        UINT_32* pBpp, UINT_32* pWidth, UINT_32* pHeight);
++
++    /// Checks if depth and stencil are planar inside a tile
++    BOOL_32 IsDepthStencilTilePlanar()
++    {
++        return (m_depthPlanarType == ADDR_DEPTH_PLANAR_R600) ? TRUE : FALSE;
++    }
++
++    /// Sets m_configFlags, copied from AddrLib
++    VOID    SetConfigFlags(ADDR_CONFIG_FLAGS flags)
++    {
++        m_configFlags = flags;
++    }
++
++    static BOOL_32 IsCompressed(AddrFormat format);
++    static BOOL_32 IsBlockCompressed(AddrFormat format);
++    static BOOL_32 IsExpand3x(AddrFormat format);
++
++protected:
++
++    static VOID    GetCompBits(
++        UINT_32 c0, UINT_32 c1, UINT_32 c2, UINT_32 c3,
++        ADDR_PIXEL_FORMATINFO* pInfo,
++        AddrElemMode elemMode = ADDR_ROUND_BY_HALF);
++
++    static VOID    GetCompType(
++        AddrColorFormat format, AddrSurfaceNumber numType,
++        ADDR_PIXEL_FORMATINFO* pInfo);
++
++    static VOID    GetCompSwap(
++        AddrSurfaceSwap swap, ADDR_PIXEL_FORMATINFO* pInfo);
++
++    static VOID    SwapComps(
++        UINT_32 c0, UINT_32 c1, ADDR_PIXEL_FORMATINFO* pInfo);
++
++private:
++
++    UINT_32             m_fp16ExportNorm;   ///< If allow FP16 to be reported as EXPORT_NORM
++    AddrDepthPlanarType m_depthPlanarType;
++
++    ADDR_CONFIG_FLAGS   m_configFlags;      ///< Copy of AddrLib's configFlags
++    AddrLib* const      m_pAddrLib;         ///< Pointer to parent addrlib instance
++};
++
++#endif
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.cpp
+new file mode 100644
+index 0000000..51b1eab
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.cpp
+@@ -0,0 +1,4028 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrlib.cpp
++* @brief Contains the implementation for the AddrLib base class..
++***************************************************************************************************
++*/
++
++#include "addrinterface.h"
++#include "addrlib.h"
++#include "addrcommon.h"
++
++#if defined(__APPLE__)
++
++UINT_32 div64_32(UINT_64 n, UINT_32 base)
++{
++    UINT_64 rem = n;
++    UINT_64 b = base;
++    UINT_64 res, d = 1;
++    UINT_32 high = rem >> 32;
++
++    res = 0;
++    if (high >= base)
++    {
++        high /= base;
++        res = (UINT_64) high << 32;
++        rem -= (UINT_64) (high*base) << 32;
++    }
++
++    while ((INT_64)b > 0 && b < rem)
++    {
++        b = b+b;
++        d = d+d;
++    }
++
++    do
++    {
++        if (rem >= b)
++        {
++            rem -= b;
++            res += d;
++        }
++        b >>= 1;
++        d >>= 1;
++    } while (d);
++
++    n = res;
++    return rem;
++}
++
++extern "C"
++UINT_32 __umoddi3(UINT_64 n, UINT_32 base)
++{
++    return div64_32(n, base);
++}
++
++#endif // __APPLE__
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Static Const Member
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++const AddrTileModeFlags AddrLib::m_modeFlags[ADDR_TM_COUNT] =
++{// T   L  1  2  3  P  Pr B
++    {1, 1, 0, 0, 0, 0, 0, 0}, // ADDR_TM_LINEAR_GENERAL
++    {1, 1, 0, 0, 0, 0, 0, 0}, // ADDR_TM_LINEAR_ALIGNED
++    {1, 0, 1, 0, 0, 0, 0, 0}, // ADDR_TM_1D_TILED_THIN1
++    {4, 0, 1, 0, 0, 0, 0, 0}, // ADDR_TM_1D_TILED_THICK
++    {1, 0, 0, 1, 0, 0, 0, 0}, // ADDR_TM_2D_TILED_THIN1
++    {1, 0, 0, 1, 0, 0, 0, 0}, // ADDR_TM_2D_TILED_THIN2
++    {1, 0, 0, 1, 0, 0, 0, 0}, // ADDR_TM_2D_TILED_THIN4
++    {4, 0, 0, 1, 0, 0, 0, 0}, // ADDR_TM_2D_TILED_THICK
++    {1, 0, 0, 1, 0, 0, 0, 1}, // ADDR_TM_2B_TILED_THIN1
++    {1, 0, 0, 1, 0, 0, 0, 1}, // ADDR_TM_2B_TILED_THIN2
++    {1, 0, 0, 1, 0, 0, 0, 1}, // ADDR_TM_2B_TILED_THIN4
++    {4, 0, 0, 1, 0, 0, 0, 1}, // ADDR_TM_2B_TILED_THICK
++    {1, 0, 0, 1, 1, 0, 0, 0}, // ADDR_TM_3D_TILED_THIN1
++    {4, 0, 0, 1, 1, 0, 0, 0}, // ADDR_TM_3D_TILED_THICK
++    {1, 0, 0, 1, 1, 0, 0, 1}, // ADDR_TM_3B_TILED_THIN1
++    {4, 0, 0, 1, 1, 0, 0, 1}, // ADDR_TM_3B_TILED_THICK
++    {8, 0, 0, 1, 0, 0, 0, 0}, // ADDR_TM_2D_TILED_XTHICK
++    {8, 0, 0, 1, 1, 0, 0, 0}, // ADDR_TM_3D_TILED_XTHICK
++    {1, 0, 0, 0, 0, 0, 0, 0}, // ADDR_TM_POWER_SAVE
++    {1, 0, 0, 1, 0, 1, 1, 0}, // ADDR_TM_PRT_TILED_THIN1
++    {1, 0, 0, 1, 0, 1, 0, 0}, // ADDR_TM_PRT_2D_TILED_THIN1
++    {1, 0, 0, 1, 1, 1, 0, 0}, // ADDR_TM_PRT_3D_TILED_THIN1
++    {4, 0, 0, 1, 0, 1, 1, 0}, // ADDR_TM_PRT_TILED_THICK
++    {4, 0, 0, 1, 0, 1, 0, 0}, // ADDR_TM_PRT_2D_TILED_THICK
++    {4, 0, 0, 1, 1, 1, 0, 0}, // ADDR_TM_PRT_3D_TILED_THICK
++};
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Constructor/Destructor
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrLib::AddrLib
++*
++*   @brief
++*       Constructor for the AddrLib class
++*
++***************************************************************************************************
++*/
++AddrLib::AddrLib() :
++    m_class(BASE_ADDRLIB),
++    m_chipFamily(ADDR_CHIP_FAMILY_IVLD),
++    m_chipRevision(0),
++    m_version(ADDRLIB_VERSION),
++    m_pipes(0),
++    m_banks(0),
++    m_pipeInterleaveBytes(0),
++    m_rowSize(0),
++    m_minPitchAlignPixels(1),
++    m_maxSamples(8),
++    m_pElemLib(NULL)
++{
++    m_configFlags.value = 0;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::AddrLib
++*
++*   @brief
++*       Constructor for the AddrLib class with hClient as parameter
++*
++***************************************************************************************************
++*/
++AddrLib::AddrLib(const AddrClient* pClient) :
++    AddrObject(pClient),
++    m_class(BASE_ADDRLIB),
++    m_chipFamily(ADDR_CHIP_FAMILY_IVLD),
++    m_chipRevision(0),
++    m_version(ADDRLIB_VERSION),
++    m_pipes(0),
++    m_banks(0),
++    m_pipeInterleaveBytes(0),
++    m_rowSize(0),
++    m_minPitchAlignPixels(1),
++    m_maxSamples(8),
++    m_pElemLib(NULL)
++{
++    m_configFlags.value = 0;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::~AddrLib
++*
++*   @brief
++*       Destructor for the AddrLib class
++*
++***************************************************************************************************
++*/
++AddrLib::~AddrLib()
++{
++    if (m_pElemLib)
++    {
++        delete m_pElemLib;
++    }
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Initialization/Helper
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrLib::Create
++*
++*   @brief
++*       Creates and initializes AddrLib object.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::Create(
++    const ADDR_CREATE_INPUT* pCreateIn,     ///< [in] pointer to ADDR_CREATE_INPUT
++    ADDR_CREATE_OUTPUT*      pCreateOut)    ///< [out] pointer to ADDR_CREATE_OUTPUT
++{
++    AddrLib* pLib = NULL;
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (pCreateIn->createFlags.fillSizeFields == TRUE)
++    {
++        if ((pCreateIn->size != sizeof(ADDR_CREATE_INPUT)) ||
++            (pCreateOut->size != sizeof(ADDR_CREATE_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if ((returnCode == ADDR_OK)                    &&
++        (pCreateIn->callbacks.allocSysMem != NULL) &&
++        (pCreateIn->callbacks.freeSysMem != NULL))
++    {
++        AddrClient client = {
++            pCreateIn->hClient,
++            pCreateIn->callbacks
++        };
++
++        switch (pCreateIn->chipEngine)
++        {
++            case CIASICIDGFXENGINE_SOUTHERNISLAND:
++                switch (pCreateIn->chipFamily)
++                {
++                    case FAMILY_SI:
++                        pLib = AddrSIHwlInit(&client);
++                        break;
++                    case FAMILY_VI:
++                    case FAMILY_CZ: // VI based fusion(carrizo)
++                    case FAMILY_CI:
++                    case FAMILY_KV: // CI based fusion
++                        pLib = AddrCIHwlInit(&client);
++                        break;
++                    default:
++                        ADDR_ASSERT_ALWAYS();
++                        break;
++                }
++                break;
++            default:
++                ADDR_ASSERT_ALWAYS();
++                break;
++        }
++    }
++
++    if ((pLib != NULL))
++    {
++        BOOL_32 initValid;
++
++        // Pass createFlags to configFlags first since these flags may be overwritten
++        pLib->m_configFlags.noCubeMipSlicesPad  = pCreateIn->createFlags.noCubeMipSlicesPad;
++        pLib->m_configFlags.fillSizeFields      = pCreateIn->createFlags.fillSizeFields;
++        pLib->m_configFlags.useTileIndex        = pCreateIn->createFlags.useTileIndex;
++        pLib->m_configFlags.useCombinedSwizzle  = pCreateIn->createFlags.useCombinedSwizzle;
++        pLib->m_configFlags.checkLast2DLevel    = pCreateIn->createFlags.checkLast2DLevel;
++        pLib->m_configFlags.useHtileSliceAlign  = pCreateIn->createFlags.useHtileSliceAlign;
++        pLib->m_configFlags.degradeBaseLevel    = pCreateIn->createFlags.degradeBaseLevel;
++        pLib->m_configFlags.allowLargeThickTile = pCreateIn->createFlags.allowLargeThickTile;
++
++        pLib->SetAddrChipFamily(pCreateIn->chipFamily, pCreateIn->chipRevision);
++
++        pLib->SetMinPitchAlignPixels(pCreateIn->minPitchAlignPixels);
++
++        // Global parameters initialized and remaining configFlags bits are set as well
++        initValid = pLib->HwlInitGlobalParams(pCreateIn);
++
++        if (initValid)
++        {
++            pLib->m_pElemLib = AddrElemLib::Create(pLib);
++        }
++        else
++        {
++            pLib->m_pElemLib = NULL; // Don't go on allocating element lib
++            returnCode = ADDR_INVALIDGBREGVALUES;
++        }
++
++        if (pLib->m_pElemLib == NULL)
++        {
++            delete pLib;
++            pLib = NULL;
++            ADDR_ASSERT_ALWAYS();
++        }
++        else
++        {
++            pLib->m_pElemLib->SetConfigFlags(pLib->m_configFlags);
++        }
++    }
++
++    pCreateOut->hLib = pLib;
++
++    if ((pLib == NULL) &&
++        (returnCode == ADDR_OK))
++    {
++        // Unknown failures, we return the general error code
++        returnCode = ADDR_ERROR;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::SetAddrChipFamily
++*
++*   @brief
++*       Convert familyID defined in atiid.h to AddrChipFamily and set m_chipFamily/m_chipRevision
++*   @return
++*      N/A
++***************************************************************************************************
++*/
++VOID AddrLib::SetAddrChipFamily(
++    UINT_32 uChipFamily,        ///< [in] chip family defined in atiih.h
++    UINT_32 uChipRevision)      ///< [in] chip revision defined in "asic_family"_id.h
++{
++    AddrChipFamily family = ADDR_CHIP_FAMILY_IVLD;
++
++    family = HwlConvertChipFamily(uChipFamily, uChipRevision);
++
++    ADDR_ASSERT(family != ADDR_CHIP_FAMILY_IVLD);
++
++    m_chipFamily    = family;
++    m_chipRevision  = uChipRevision;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::SetMinPitchAlignPixels
++*
++*   @brief
++*       Set m_minPitchAlignPixels with input param
++*
++*   @return
++*      N/A
++***************************************************************************************************
++*/
++VOID AddrLib::SetMinPitchAlignPixels(
++    UINT_32 minPitchAlignPixels)    ///< [in] minmum pitch alignment in pixels
++{
++    m_minPitchAlignPixels = (minPitchAlignPixels == 0)? 1 : minPitchAlignPixels;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::GetAddrLib
++*
++*   @brief
++*       Get AddrLib pointer
++*
++*   @return
++*      An AddrLib class pointer
++***************************************************************************************************
++*/
++AddrLib * AddrLib::GetAddrLib(
++    ADDR_HANDLE hLib)   ///< [in] handle of ADDR_HANDLE
++{
++    return static_cast<AddrLib *>(hLib);
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Surface Methods
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceInfo
++*
++*   @brief
++*       Interface function stub of AddrComputeSurfaceInfo.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeSurfaceInfo(
++     const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,    ///< [in] input structure
++     ADDR_COMPUTE_SURFACE_INFO_OUTPUT*      pOut    ///< [out] output structure
++     ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    // We suggest client do sanity check but a check here is also good
++    if (pIn->bpp > 128)
++    {
++        returnCode = ADDR_INVALIDPARAMS;
++    }
++
++    // Thick modes don't support multisample
++    if (ComputeSurfaceThickness(pIn->tileMode) > 1 && pIn->numSamples > 1)
++    {
++        returnCode = ADDR_INVALIDPARAMS;
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        // Get a local copy of input structure and only reference pIn for unadjusted values
++        ADDR_COMPUTE_SURFACE_INFO_INPUT localIn = *pIn;
++        ADDR_TILEINFO tileInfoNull = {0};
++
++        if (UseTileInfo())
++        {
++            // If the original input has a valid ADDR_TILEINFO pointer then copy its contents.
++            // Otherwise the default 0's in tileInfoNull are used.
++            if (pIn->pTileInfo)
++            {
++                tileInfoNull = *pIn->pTileInfo;
++            }
++            localIn.pTileInfo  = &tileInfoNull;
++        }
++
++        localIn.numSamples = pIn->numSamples == 0 ? 1 : pIn->numSamples;
++
++        // Do mipmap check first
++        // If format is BCn, pre-pad dimension to power-of-two according to HWL
++        ComputeMipLevel(&localIn);
++
++        if (m_configFlags.checkLast2DLevel)
++        {
++            // Save this level's original height in pixels
++            pOut->height = pIn->height;
++        }
++
++        UINT_32 expandX = 1;
++        UINT_32 expandY = 1;
++        AddrElemMode elemMode;
++
++        // Save outputs that may not go through HWL
++        pOut->pixelBits = localIn.bpp;
++        pOut->numSamples = localIn.numSamples;
++        pOut->last2DLevel = FALSE;
++
++#if !ALT_TEST
++        if (localIn.numSamples > 1)
++        {
++            ADDR_ASSERT(localIn.mipLevel == 0);
++        }
++#endif
++
++        if (localIn.format != ADDR_FMT_INVALID) // Set format to INVALID will skip this conversion
++        {
++            // Get compression/expansion factors and element mode
++            // (which indicates compression/expansion
++            localIn.bpp = GetElemLib()->GetBitsPerPixel(localIn.format,
++                                                        &elemMode,
++                                                        &expandX,
++                                                        &expandY);
++
++            // Special flag for 96 bit surface. 96 (or 48 if we support) bit surface's width is
++            // pre-multiplied by 3 and bpp is divided by 3. So pitch alignment for linear-
++            // aligned does not meet 64-pixel in real. We keep special handling in hwl since hw
++            // restrictions are different.
++            // Also Mip 1+ needs an element pitch of 32 bits so we do not need this workaround
++            // but we use this flag to skip RestoreSurfaceInfo below
++
++            if ((elemMode == ADDR_EXPANDED) &&
++                (expandX > 1))
++            {
++                ADDR_ASSERT(localIn.tileMode == ADDR_TM_LINEAR_ALIGNED || localIn.height == 1);
++            }
++
++            GetElemLib()->AdjustSurfaceInfo(elemMode,
++                                            expandX,
++                                            expandY,
++                                            &localIn.bpp,
++                                            &localIn.basePitch,
++                                            &localIn.width,
++                                            &localIn.height);
++
++            // Overwrite these parameters if we have a valid format
++        }
++        else if (localIn.bpp != 0)
++        {
++            localIn.width  = (localIn.width != 0) ? localIn.width : 1;
++            localIn.height = (localIn.height != 0) ? localIn.height : 1;
++        }
++        else // Rule out some invalid parameters
++        {
++            ADDR_ASSERT_ALWAYS();
++
++            returnCode = ADDR_INVALIDPARAMS;
++        }
++
++        // Check mipmap after surface expansion
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = PostComputeMipLevel(&localIn, pOut);
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            if (UseTileIndex(localIn.tileIndex))
++            {
++                // Make sure pTileInfo is not NULL
++                ADDR_ASSERT(localIn.pTileInfo);
++
++                UINT_32 numSamples = GetNumFragments(localIn.numSamples, localIn.numFrags);
++
++                INT_32 macroModeIndex = TileIndexNoMacroIndex;
++
++                if (localIn.tileIndex != TileIndexLinearGeneral)
++                {
++                    // Try finding a macroModeIndex
++                    macroModeIndex = HwlComputeMacroModeIndex(localIn.tileIndex,
++                                                              localIn.flags,
++                                                              localIn.bpp,
++                                                              numSamples,
++                                                              localIn.pTileInfo,
++                                                              &localIn.tileMode,
++                                                              &localIn.tileType);
++                }
++
++                // If macroModeIndex is not needed, then call HwlSetupTileCfg to get tile info
++                if (macroModeIndex == TileIndexNoMacroIndex)
++                {
++                    returnCode = HwlSetupTileCfg(localIn.tileIndex, macroModeIndex,
++                                                 localIn.pTileInfo,
++                                                 &localIn.tileMode, &localIn.tileType);
++                }
++                // If macroModeIndex is invalid, then assert this is not macro tiled
++                else if (macroModeIndex == TileIndexInvalid)
++                {
++                    ADDR_ASSERT(!IsMacroTiled(localIn.tileMode));
++                }
++            }
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            AddrTileMode tileMode = localIn.tileMode;
++            AddrTileType tileType = localIn.tileType;
++
++            // HWL layer may override tile mode if necessary
++            if (HwlOverrideTileMode(&localIn, &tileMode, &tileType))
++            {
++                localIn.tileMode = tileMode;
++                localIn.tileType = tileType;
++            }
++            // Degrade base level if applicable
++            if (DegradeBaseLevel(&localIn, &tileMode))
++            {
++                localIn.tileMode = tileMode;
++            }
++        }
++
++        // Call main function to compute surface info
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlComputeSurfaceInfo(&localIn, pOut);
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            // Since bpp might be changed we just pass it through
++            pOut->bpp  = localIn.bpp;
++
++            // Also original width/height/bpp
++            pOut->pixelPitch    = pOut->pitch;
++            pOut->pixelHeight   = pOut->height;
++
++#if DEBUG
++            if (localIn.flags.display)
++            {
++                ADDR_ASSERT((pOut->pitchAlign % 32) == 0);
++            }
++#endif //DEBUG
++
++            if (localIn.format != ADDR_FMT_INVALID)
++            {
++                //
++                // 96 bits surface of level 1+ requires element pitch of 32 bits instead
++                // In hwl function we skip multiplication of 3 then we should skip division of 3
++                // We keep pitch that represents 32 bit element instead of 96 bits since we
++                // will get an odd number if divided by 3.
++                //
++                if (!((expandX == 3) && (localIn.mipLevel > 0)))
++                {
++
++                    GetElemLib()->RestoreSurfaceInfo(elemMode,
++                                                     expandX,
++                                                     expandY,
++                                                     &localIn.bpp,
++                                                     &pOut->pixelPitch,
++                                                     &pOut->pixelHeight);
++                }
++            }
++
++            if (localIn.flags.qbStereo)
++            {
++                if (pOut->pStereoInfo)
++                {
++                    ComputeQbStereoInfo(pOut);
++                }
++            }
++
++            if (localIn.flags.volume) // For volume sliceSize equals to all z-slices
++            {
++                pOut->sliceSize = pOut->surfSize;
++            }
++            else // For array: sliceSize is likely to have slice-padding (the last one)
++            {
++                pOut->sliceSize = pOut->surfSize / pOut->depth;
++
++                // array or cubemap
++                if (pIn->numSlices > 1)
++                {
++                    // If this is the last slice then add the padding size to this slice
++                    if (pIn->slice == (pIn->numSlices - 1))
++                    {
++                        pOut->sliceSize += pOut->sliceSize * (pOut->depth - pIn->numSlices);
++                    }
++                    else if (m_configFlags.checkLast2DLevel)
++                    {
++                        // Reset last2DLevel flag if this is not the last array slice
++                        pOut->last2DLevel = FALSE;
++                    }
++                }
++            }
++
++            pOut->pitchTileMax = pOut->pitch / 8 - 1;
++            pOut->heightTileMax = pOut->height / 8 - 1;
++            pOut->sliceTileMax = pOut->pitch * pOut->height / 64 - 1;
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceInfo
++*
++*   @brief
++*       Interface function stub of AddrComputeSurfaceInfo.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeSurfaceAddrFromCoord(
++    const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            const ADDR_SURFACE_FLAGS flags = {{0}};
++            UINT_32 numSamples = GetNumFragments(pIn->numSamples, pIn->numFrags);
++
++            // Try finding a macroModeIndex
++            INT_32 macroModeIndex = HwlComputeMacroModeIndex(input.tileIndex,
++                                                             flags,
++                                                             input.bpp,
++                                                             numSamples,
++                                                             input.pTileInfo,
++                                                             &input.tileMode,
++                                                             &input.tileType);
++
++            // If macroModeIndex is not needed, then call HwlSetupTileCfg to get tile info
++            if (macroModeIndex == TileIndexNoMacroIndex)
++            {
++                returnCode = HwlSetupTileCfg(input.tileIndex, macroModeIndex,
++                                             input.pTileInfo, &input.tileMode, &input.tileType);
++            }
++            // If macroModeIndex is invalid, then assert this is not macro tiled
++            else if (macroModeIndex == TileIndexInvalid)
++            {
++                ADDR_ASSERT(!IsMacroTiled(input.tileMode));
++            }
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlComputeSurfaceAddrFromCoord(pIn, pOut);
++
++            if (returnCode == ADDR_OK)
++            {
++                pOut->prtBlockIndex = static_cast<UINT_32>(pOut->addr / (64 * 1024));
++            }
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceCoordFromAddr
++*
++*   @brief
++*       Interface function stub of ComputeSurfaceCoordFromAddr.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeSurfaceCoordFromAddr(
++    const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            const ADDR_SURFACE_FLAGS flags = {{0}};
++            UINT_32 numSamples = GetNumFragments(pIn->numSamples, pIn->numFrags);
++
++            // Try finding a macroModeIndex
++            INT_32 macroModeIndex = HwlComputeMacroModeIndex(input.tileIndex,
++                                                             flags,
++                                                             input.bpp,
++                                                             numSamples,
++                                                             input.pTileInfo,
++                                                             &input.tileMode,
++                                                             &input.tileType);
++
++            // If macroModeIndex is not needed, then call HwlSetupTileCfg to get tile info
++            if (macroModeIndex == TileIndexNoMacroIndex)
++            {
++                returnCode = HwlSetupTileCfg(input.tileIndex, macroModeIndex,
++                                             input.pTileInfo, &input.tileMode, &input.tileType);
++            }
++            // If macroModeIndex is invalid, then assert this is not macro tiled
++            else if (macroModeIndex == TileIndexInvalid)
++            {
++                ADDR_ASSERT(!IsMacroTiled(input.tileMode));
++            }
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlComputeSurfaceCoordFromAddr(pIn, pOut);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSliceTileSwizzle
++*
++*   @brief
++*       Interface function stub of ComputeSliceTileSwizzle.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeSliceTileSwizzle(
++    const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_SLICESWIZZLE_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_SLICESWIZZLE_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_SLICESWIZZLE_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex,
++                                         input.pTileInfo, &input.tileMode);
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlComputeSliceTileSwizzle(pIn, pOut);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ExtractBankPipeSwizzle
++*
++*   @brief
++*       Interface function stub of AddrExtractBankPipeSwizzle.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ExtractBankPipeSwizzle(
++    const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT*  pIn,    ///< [in] input structure
++    ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT)) ||
++            (pOut->size != sizeof(ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlExtractBankPipeSwizzle(pIn, pOut);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::CombineBankPipeSwizzle
++*
++*   @brief
++*       Interface function stub of AddrCombineBankPipeSwizzle.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::CombineBankPipeSwizzle(
++    const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_FMASK_INFO_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_FMASK_INFO_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlCombineBankPipeSwizzle(pIn->bankSwizzle,
++                                                   pIn->pipeSwizzle,
++                                                   pIn->pTileInfo,
++                                                   pIn->baseAddr,
++                                                   &pOut->tileSwizzle);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeBaseSwizzle
++*
++*   @brief
++*       Interface function stub of AddrCompueBaseSwizzle.
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeBaseSwizzle(
++    const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
++    ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_BASE_SWIZZLE_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            if (IsMacroTiled(pIn->tileMode))
++            {
++                returnCode = HwlComputeBaseSwizzle(pIn, pOut);
++            }
++            else
++            {
++                pOut->tileSwizzle = 0;
++            }
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeFmaskInfo
++*
++*   @brief
++*       Interface function stub of ComputeFmaskInfo.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeFmaskInfo(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,    ///< [in] input structure
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut    ///< [out] output structure
++    )
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_FMASK_INFO_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_FMASK_INFO_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    // No thick MSAA
++    if (ComputeSurfaceThickness(pIn->tileMode) > 1)
++    {
++        returnCode = ADDR_INVALIDPARAMS;
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_FMASK_INFO_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++
++            if (pOut->pTileInfo)
++            {
++                // Use temp tile info for calcalation
++                input.pTileInfo = pOut->pTileInfo;
++            }
++            else
++            {
++                input.pTileInfo = &tileInfoNull;
++            }
++
++            ADDR_SURFACE_FLAGS flags = {{0}};
++            flags.fmask = 1;
++
++            // Try finding a macroModeIndex
++            INT_32 macroModeIndex = HwlComputeMacroModeIndex(pIn->tileIndex,
++                                                             flags,
++                                                             HwlComputeFmaskBits(pIn, NULL),
++                                                             pIn->numSamples,
++                                                             input.pTileInfo,
++                                                             &input.tileMode);
++
++            // If macroModeIndex is not needed, then call HwlSetupTileCfg to get tile info
++            if (macroModeIndex == TileIndexNoMacroIndex)
++            {
++                returnCode = HwlSetupTileCfg(input.tileIndex, macroModeIndex,
++                                             input.pTileInfo, &input.tileMode);
++            }
++
++            ADDR_ASSERT(macroModeIndex != TileIndexInvalid);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            if (pIn->numSamples > 1)
++            {
++                returnCode = HwlComputeFmaskInfo(pIn, pOut);
++            }
++            else
++            {
++                memset(pOut, 0, sizeof(ADDR_COMPUTE_FMASK_INFO_OUTPUT));
++
++                returnCode = ADDR_INVALIDPARAMS;
++            }
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeFmaskAddrFromCoord
++*
++*   @brief
++*       Interface function stub of ComputeFmaskAddrFromCoord.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeFmaskAddrFromCoord(
++    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_ASSERT(pIn->numSamples > 1);
++
++        if (pIn->numSamples > 1)
++        {
++            returnCode = HwlComputeFmaskAddrFromCoord(pIn, pOut);
++        }
++        else
++        {
++            returnCode = ADDR_INVALIDPARAMS;
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeFmaskCoordFromAddr
++*
++*   @brief
++*       Interface function stub of ComputeFmaskAddrFromCoord.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeFmaskCoordFromAddr(
++    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*  pIn,     ///< [in] input structure
++    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut           ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_ASSERT(pIn->numSamples > 1);
++
++        if (pIn->numSamples > 1)
++        {
++            returnCode = HwlComputeFmaskCoordFromAddr(pIn, pOut);
++        }
++        else
++        {
++            returnCode = ADDR_INVALIDPARAMS;
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ConvertTileInfoToHW
++*
++*   @brief
++*       Convert tile info from real value to HW register value in HW layer
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ConvertTileInfoToHW(
++    const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, ///< [in] input structure
++    ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut      ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT)) ||
++            (pOut->size != sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_CONVERT_TILEINFOTOHW_INPUT input;
++        // if pIn->reverse is TRUE, indices are ignored
++        if (pIn->reverse == FALSE && UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = HwlConvertTileInfoToHW(pIn, pOut);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ConvertTileIndex
++*
++*   @brief
++*       Convert tile index to tile mode/type/info
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ConvertTileIndex(
++    const ADDR_CONVERT_TILEINDEX_INPUT* pIn, ///< [in] input structure
++    ADDR_CONVERT_TILEINDEX_OUTPUT* pOut      ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_CONVERT_TILEINDEX_INPUT)) ||
++            (pOut->size != sizeof(ADDR_CONVERT_TILEINDEX_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++
++        returnCode = HwlSetupTileCfg(pIn->tileIndex, pIn->macroModeIndex,
++                                     pOut->pTileInfo, &pOut->tileMode, &pOut->tileType);
++
++        if (returnCode == ADDR_OK && pIn->tileInfoHw)
++        {
++            ADDR_CONVERT_TILEINFOTOHW_INPUT hwInput = {0};
++            ADDR_CONVERT_TILEINFOTOHW_OUTPUT hwOutput = {0};
++
++            hwInput.pTileInfo = pOut->pTileInfo;
++            hwInput.tileIndex = -1;
++            hwOutput.pTileInfo = pOut->pTileInfo;
++
++            returnCode = HwlConvertTileInfoToHW(&hwInput, &hwOutput);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ConvertTileIndex1
++*
++*   @brief
++*       Convert tile index to tile mode/type/info
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ConvertTileIndex1(
++    const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,   ///< [in] input structure
++    ADDR_CONVERT_TILEINDEX_OUTPUT* pOut         ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_CONVERT_TILEINDEX1_INPUT)) ||
++            (pOut->size != sizeof(ADDR_CONVERT_TILEINDEX_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_SURFACE_FLAGS flags = {{0}};
++
++        HwlComputeMacroModeIndex(pIn->tileIndex, flags, pIn->bpp, pIn->numSamples,
++                                 pOut->pTileInfo, &pOut->tileMode, &pOut->tileType);
++
++        if (pIn->tileInfoHw)
++        {
++            ADDR_CONVERT_TILEINFOTOHW_INPUT hwInput = {0};
++            ADDR_CONVERT_TILEINFOTOHW_OUTPUT hwOutput = {0};
++
++            hwInput.pTileInfo = pOut->pTileInfo;
++            hwInput.tileIndex = -1;
++            hwOutput.pTileInfo = pOut->pTileInfo;
++
++            returnCode = HwlConvertTileInfoToHW(&hwInput, &hwOutput);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::GetTileIndex
++*
++*   @brief
++*       Get tile index from tile mode/type/info
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::GetTileIndex(
++    const ADDR_GET_TILEINDEX_INPUT* pIn, ///< [in] input structure
++    ADDR_GET_TILEINDEX_OUTPUT* pOut      ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_GET_TILEINDEX_INPUT)) ||
++            (pOut->size != sizeof(ADDR_GET_TILEINDEX_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        returnCode = HwlGetTileIndex(pIn, pOut);
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceThickness
++*
++*   @brief
++*       Compute surface thickness
++*
++*   @return
++*       Surface thickness
++***************************************************************************************************
++*/
++UINT_32 AddrLib::ComputeSurfaceThickness(
++    AddrTileMode tileMode)    ///< [in] tile mode
++{
++    return m_modeFlags[tileMode].thickness;
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               CMASK/HTILE
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeHtileInfo
++*
++*   @brief
++*       Interface function stub of AddrComputeHtilenfo
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeHtileInfo(
++    const ADDR_COMPUTE_HTILE_INFO_INPUT*    pIn,    ///< [in] input structure
++    ADDR_COMPUTE_HTILE_INFO_OUTPUT*         pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    BOOL_32 isWidth8  = (pIn->blockWidth == 8) ? TRUE : FALSE;
++    BOOL_32 isHeight8 = (pIn->blockHeight == 8) ? TRUE : FALSE;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_HTILE_INFO_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            pOut->bpp = ComputeHtileInfo(pIn->flags,
++                                         pIn->pitch,
++                                         pIn->height,
++                                         pIn->numSlices,
++                                         pIn->isLinear,
++                                         isWidth8,
++                                         isHeight8,
++                                         pIn->pTileInfo,
++                                         &pOut->pitch,
++                                         &pOut->height,
++                                         &pOut->htileBytes,
++                                         &pOut->macroWidth,
++                                         &pOut->macroHeight,
++                                         &pOut->sliceSize,
++                                         &pOut->baseAlign);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeCmaskInfo
++*
++*   @brief
++*       Interface function stub of AddrComputeCmaskInfo
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeCmaskInfo(
++    const ADDR_COMPUTE_CMASK_INFO_INPUT*    pIn,    ///< [in] input structure
++    ADDR_COMPUTE_CMASK_INFO_OUTPUT*         pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_CMASK_INFO_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_CMASK_INFO_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_CMASK_INFO_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            returnCode = ComputeCmaskInfo(pIn->flags,
++                                          pIn->pitch,
++                                          pIn->height,
++                                          pIn->numSlices,
++                                          pIn->isLinear,
++                                          pIn->pTileInfo,
++                                          &pOut->pitch,
++                                          &pOut->height,
++                                          &pOut->cmaskBytes,
++                                          &pOut->macroWidth,
++                                          &pOut->macroHeight,
++                                          &pOut->sliceSize,
++                                          &pOut->baseAlign,
++                                          &pOut->blockMax);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeDccInfo
++*
++*   @brief
++*       Interface function to compute DCC key info
++*
++*   @return
++*       return code of HwlComputeDccInfo
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeDccInfo(
++    const ADDR_COMPUTE_DCCINFO_INPUT*    pIn,    ///< [in] input structure
++    ADDR_COMPUTE_DCCINFO_OUTPUT*         pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE ret = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_DCCINFO_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT)))
++        {
++            ret = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (ret == ADDR_OK)
++    {
++        ADDR_COMPUTE_DCCINFO_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++
++            ret = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex,
++                                  &input.tileInfo, &input.tileMode);
++
++            pIn = &input;
++        }
++
++        if (ADDR_OK == ret)
++        {
++            ret = HwlComputeDccInfo(pIn, pOut);
++        }
++    }
++
++    return ret;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeHtileAddrFromCoord
++*
++*   @brief
++*       Interface function stub of AddrComputeHtileAddrFromCoord
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeHtileAddrFromCoord(
++    const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    BOOL_32 isWidth8  = (pIn->blockWidth == 8) ? TRUE : FALSE;
++    BOOL_32 isHeight8 = (pIn->blockHeight == 8) ? TRUE : FALSE;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch,
++                                                      pIn->height,
++                                                      pIn->x,
++                                                      pIn->y,
++                                                      pIn->slice,
++                                                      pIn->numSlices,
++                                                      1,
++                                                      pIn->isLinear,
++                                                      isWidth8,
++                                                      isHeight8,
++                                                      pIn->pTileInfo,
++                                                      &pOut->bitPosition);
++        }
++    }
++
++    return returnCode;
++
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeHtileCoordFromAddr
++*
++*   @brief
++*       Interface function stub of AddrComputeHtileCoordFromAddr
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeHtileCoordFromAddr(
++    const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    BOOL_32 isWidth8  = (pIn->blockWidth == 8) ? TRUE : FALSE;
++    BOOL_32 isHeight8 = (pIn->blockHeight == 8) ? TRUE : FALSE;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            HwlComputeXmaskCoordFromAddr(pIn->addr,
++                                         pIn->bitPosition,
++                                         pIn->pitch,
++                                         pIn->height,
++                                         pIn->numSlices,
++                                         1,
++                                         pIn->isLinear,
++                                         isWidth8,
++                                         isHeight8,
++                                         pIn->pTileInfo,
++                                         &pOut->x,
++                                         &pOut->y,
++                                         &pOut->slice);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeCmaskAddrFromCoord
++*
++*   @brief
++*       Interface function stub of AddrComputeCmaskAddrFromCoord
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeCmaskAddrFromCoord(
++    const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            if (pIn->flags.tcCompatible == TRUE)
++            {
++                returnCode = HwlComputeCmaskAddrFromCoord(pIn, pOut);
++            }
++            else
++            {
++                pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch,
++                                                          pIn->height,
++                                                          pIn->x,
++                                                          pIn->y,
++                                                          pIn->slice,
++                                                          pIn->numSlices,
++                                                          2,
++                                                          pIn->isLinear,
++                                                          FALSE, //this is cmask, isWidth8 is not needed
++                                                          FALSE, //this is cmask, isHeight8 is not needed
++                                                          pIn->pTileInfo,
++                                                          &pOut->bitPosition);
++            }
++
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeCmaskCoordFromAddr
++*
++*   @brief
++*       Interface function stub of AddrComputeCmaskCoordFromAddr
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeCmaskCoordFromAddr(
++    const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT)) ||
++            (pOut->size != sizeof(ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        ADDR_TILEINFO tileInfoNull;
++        ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT input;
++
++        if (UseTileIndex(pIn->tileIndex))
++        {
++            input = *pIn;
++            // Use temp tile info for calcalation
++            input.pTileInfo = &tileInfoNull;
++
++            returnCode = HwlSetupTileCfg(input.tileIndex, input.macroModeIndex, input.pTileInfo);
++
++            // Change the input structure
++            pIn = &input;
++        }
++
++        if (returnCode == ADDR_OK)
++        {
++            HwlComputeXmaskCoordFromAddr(pIn->addr,
++                                         pIn->bitPosition,
++                                         pIn->pitch,
++                                         pIn->height,
++                                         pIn->numSlices,
++                                         2,
++                                         pIn->isLinear,
++                                         FALSE,
++                                         FALSE,
++                                         pIn->pTileInfo,
++                                         &pOut->x,
++                                         &pOut->y,
++                                         &pOut->slice);
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeTileDataWidthAndHeight
++*
++*   @brief
++*       Compute the squared cache shape for per-tile data (CMASK and HTILE)
++*
++*   @return
++*       N/A
++*
++*   @note
++*       MacroWidth and macroHeight are measured in pixels
++***************************************************************************************************
++*/
++VOID AddrLib::ComputeTileDataWidthAndHeight(
++    UINT_32         bpp,             ///< [in] bits per pixel
++    UINT_32         cacheBits,       ///< [in] bits of cache
++    ADDR_TILEINFO*  pTileInfo,       ///< [in] Tile info
++    UINT_32*        pMacroWidth,     ///< [out] macro tile width
++    UINT_32*        pMacroHeight     ///< [out] macro tile height
++    ) const
++{
++    UINT_32 height = 1;
++    UINT_32 width  = cacheBits / bpp;
++    UINT_32 pipes  = HwlGetPipes(pTileInfo);
++
++    // Double height until the macro-tile is close to square
++    // Height can only be doubled if width is even
++
++    while ((width > height * 2 * pipes) && !(width & 1))
++    {
++        width  /= 2;
++        height *= 2;
++    }
++
++    *pMacroWidth  = 8 * width;
++    *pMacroHeight = 8 * height * pipes;
++
++    // Note: The above iterative comptuation is equivalent to the following
++    //
++    //int log2_height = ((log2(cacheBits)-log2(bpp)-log2(pipes))/2);
++    //int macroHeight = pow2( 3+log2(pipes)+log2_height );
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlComputeTileDataWidthAndHeightLinear
++*
++*   @brief
++*       Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
++*
++*   @return
++*       N/A
++*
++*   @note
++*       MacroWidth and macroHeight are measured in pixels
++***************************************************************************************************
++*/
++VOID AddrLib::HwlComputeTileDataWidthAndHeightLinear(
++    UINT_32*        pMacroWidth,     ///< [out] macro tile width
++    UINT_32*        pMacroHeight,    ///< [out] macro tile height
++    UINT_32         bpp,             ///< [in] bits per pixel
++    ADDR_TILEINFO*  pTileInfo        ///< [in] tile info
++    ) const
++{
++    ADDR_ASSERT(bpp != 4);              // Cmask does not support linear layout prior to SI
++    *pMacroWidth  = 8 * 512 / bpp;      // Align width to 512-bit memory accesses
++    *pMacroHeight = 8 * m_pipes;        // Align height to number of pipes
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeHtileInfo
++*
++*   @brief
++*       Compute htile pitch,width, bytes per 2D slice
++*
++*   @return
++*       Htile bpp i.e. How many bits for an 8x8 tile
++*       Also returns by output parameters:
++*       *Htile pitch, height, total size in bytes, macro-tile dimensions and slice size*
++***************************************************************************************************
++*/
++UINT_32 AddrLib::ComputeHtileInfo(
++    ADDR_HTILE_FLAGS flags,             ///< [in] htile flags
++    UINT_32          pitchIn,           ///< [in] pitch input
++    UINT_32          heightIn,          ///< [in] height input
++    UINT_32          numSlices,         ///< [in] number of slices
++    BOOL_32          isLinear,          ///< [in] if it is linear mode
++    BOOL_32          isWidth8,          ///< [in] if htile block width is 8
++    BOOL_32          isHeight8,         ///< [in] if htile block height is 8
++    ADDR_TILEINFO*   pTileInfo,         ///< [in] Tile info
++    UINT_32*         pPitchOut,         ///< [out] pitch output
++    UINT_32*         pHeightOut,        ///< [out] height output
++    UINT_64*         pHtileBytes,       ///< [out] bytes per 2D slice
++    UINT_32*         pMacroWidth,       ///< [out] macro-tile width in pixels
++    UINT_32*         pMacroHeight,      ///< [out] macro-tile width in pixels
++    UINT_64*         pSliceSize,        ///< [out] slice size in bytes
++    UINT_32*         pBaseAlign         ///< [out] base alignment
++    ) const
++{
++
++    UINT_32 macroWidth;
++    UINT_32 macroHeight;
++    UINT_32 baseAlign;
++    UINT_64 surfBytes;
++    UINT_64 sliceBytes;
++
++    numSlices = Max(1u, numSlices);
++
++    const UINT_32 bpp = HwlComputeHtileBpp(isWidth8, isHeight8);
++    const UINT_32 cacheBits = HtileCacheBits;
++
++    if (isLinear)
++    {
++        HwlComputeTileDataWidthAndHeightLinear(&macroWidth,
++                                               &macroHeight,
++                                               bpp,
++                                               pTileInfo);
++    }
++    else
++    {
++        ComputeTileDataWidthAndHeight(bpp,
++                                      cacheBits,
++                                      pTileInfo,
++                                      &macroWidth,
++                                      &macroHeight);
++    }
++
++    *pPitchOut = PowTwoAlign(pitchIn,  macroWidth);
++    *pHeightOut = PowTwoAlign(heightIn,  macroHeight);
++
++    baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo);
++
++    surfBytes = HwlComputeHtileBytes(*pPitchOut,
++                                     *pHeightOut,
++                                     bpp,
++                                     isLinear,
++                                     numSlices,
++                                     &sliceBytes,
++                                     baseAlign);
++
++    *pHtileBytes = surfBytes;
++
++    //
++    // Use SafeAssign since they are optional
++    //
++    SafeAssign(pMacroWidth, macroWidth);
++
++    SafeAssign(pMacroHeight, macroHeight);
++
++    SafeAssign(pSliceSize,  sliceBytes);
++
++    SafeAssign(pBaseAlign, baseAlign);
++
++    return bpp;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeCmaskBaseAlign
++*
++*   @brief
++*       Compute cmask base alignment
++*
++*   @return
++*       Cmask base alignment
++***************************************************************************************************
++*/
++UINT_32 AddrLib::ComputeCmaskBaseAlign(
++    ADDR_CMASK_FLAGS flags,           ///< [in] Cmask flags
++    ADDR_TILEINFO*   pTileInfo        ///< [in] Tile info
++    ) const
++{
++    UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo);
++
++    if (flags.tcCompatible)
++    {
++        ADDR_ASSERT(pTileInfo != NULL);
++        if (pTileInfo)
++        {
++            baseAlign *= pTileInfo->banks;
++        }
++    }
++
++    return baseAlign;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeCmaskBytes
++*
++*   @brief
++*       Compute cmask size in bytes
++*
++*   @return
++*       Cmask size in bytes
++***************************************************************************************************
++*/
++UINT_64 AddrLib::ComputeCmaskBytes(
++    UINT_32 pitch,        ///< [in] pitch
++    UINT_32 height,       ///< [in] height
++    UINT_32 numSlices     ///< [in] number of slices
++    ) const
++{
++    return BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * numSlices * CmaskElemBits) /
++        MicroTilePixels;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeCmaskInfo
++*
++*   @brief
++*       Compute cmask pitch,width, bytes per 2D slice
++*
++*   @return
++*       BlockMax. Also by output parameters: Cmask pitch,height, total size in bytes,
++*       macro-tile dimensions
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputeCmaskInfo(
++    ADDR_CMASK_FLAGS flags,            ///< [in] cmask flags
++    UINT_32          pitchIn,           ///< [in] pitch input
++    UINT_32          heightIn,          ///< [in] height input
++    UINT_32          numSlices,         ///< [in] number of slices
++    BOOL_32          isLinear,          ///< [in] is linear mode
++    ADDR_TILEINFO*   pTileInfo,         ///< [in] Tile info
++    UINT_32*         pPitchOut,         ///< [out] pitch output
++    UINT_32*         pHeightOut,        ///< [out] height output
++    UINT_64*         pCmaskBytes,       ///< [out] bytes per 2D slice
++    UINT_32*         pMacroWidth,       ///< [out] macro-tile width in pixels
++    UINT_32*         pMacroHeight,      ///< [out] macro-tile width in pixels
++    UINT_64*         pSliceSize,        ///< [out] slice size in bytes
++    UINT_32*         pBaseAlign,        ///< [out] base alignment
++    UINT_32*         pBlockMax          ///< [out] block max == slice / 128 / 128 - 1
++    ) const
++{
++    UINT_32 macroWidth;
++    UINT_32 macroHeight;
++    UINT_32 baseAlign;
++    UINT_64 surfBytes;
++    UINT_64 sliceBytes;
++
++    numSlices = Max(1u, numSlices);
++
++    const UINT_32 bpp = CmaskElemBits;
++    const UINT_32 cacheBits = CmaskCacheBits;
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (isLinear)
++    {
++        HwlComputeTileDataWidthAndHeightLinear(&macroWidth,
++                                               &macroHeight,
++                                               bpp,
++                                               pTileInfo);
++    }
++    else
++    {
++        ComputeTileDataWidthAndHeight(bpp,
++                                      cacheBits,
++                                      pTileInfo,
++                                      &macroWidth,
++                                      &macroHeight);
++    }
++
++    *pPitchOut = (pitchIn + macroWidth - 1) & ~(macroWidth - 1);
++    *pHeightOut = (heightIn + macroHeight - 1) & ~(macroHeight - 1);
++
++
++    sliceBytes = ComputeCmaskBytes(*pPitchOut,
++                                   *pHeightOut,
++                                   1);
++
++    baseAlign = ComputeCmaskBaseAlign(flags, pTileInfo);
++
++    while (sliceBytes % baseAlign)
++    {
++        *pHeightOut += macroHeight;
++
++        sliceBytes = ComputeCmaskBytes(*pPitchOut,
++                                       *pHeightOut,
++                                       1);
++    }
++
++    surfBytes = sliceBytes * numSlices;
++
++    *pCmaskBytes = surfBytes;
++
++    //
++    // Use SafeAssign since they are optional
++    //
++    SafeAssign(pMacroWidth, macroWidth);
++
++    SafeAssign(pMacroHeight, macroHeight);
++
++    SafeAssign(pBaseAlign, baseAlign);
++
++    SafeAssign(pSliceSize, sliceBytes);
++
++    UINT_32 slice = (*pPitchOut) * (*pHeightOut);
++    UINT_32 blockMax = slice / 128 / 128 - 1;
++
++#if DEBUG
++    if (slice % (64*256) != 0)
++    {
++        ADDR_ASSERT_ALWAYS();
++    }
++#endif //DEBUG
++
++    UINT_32 maxBlockMax = HwlGetMaxCmaskBlockMax();
++
++    if (blockMax > maxBlockMax)
++    {
++        blockMax = maxBlockMax;
++        returnCode = ADDR_INVALIDPARAMS;
++    }
++
++    SafeAssign(pBlockMax, blockMax);
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeXmaskCoordYFromPipe
++*
++*   @brief
++*       Compute the Y coord from pipe number for cmask/htile
++*
++*   @return
++*       Y coordinate
++*
++***************************************************************************************************
++*/
++UINT_32 AddrLib::ComputeXmaskCoordYFromPipe(
++    UINT_32         pipe,       ///< [in] pipe number
++    UINT_32         x           ///< [in] x coordinate
++    ) const
++{
++    UINT_32 pipeBit0;
++    UINT_32 pipeBit1;
++    UINT_32 xBit0;
++    UINT_32 xBit1;
++    UINT_32 yBit0;
++    UINT_32 yBit1;
++
++    UINT_32 y = 0;
++
++    UINT_32 numPipes = m_pipes; // SI has its implementation
++    //
++    // Convert pipe + x to y coordinate.
++    //
++    switch (numPipes)
++    {
++        case 1:
++            //
++            // 1 pipe
++            //
++            // p0 = 0
++            //
++            y = 0;
++            break;
++        case 2:
++            //
++            // 2 pipes
++            //
++            // p0 = x0 ^ y0
++            //
++            // y0 = p0 ^ x0
++            //
++            pipeBit0 = pipe & 0x1;
++
++            xBit0 = x & 0x1;
++
++            yBit0 = pipeBit0 ^ xBit0;
++
++            y = yBit0;
++            break;
++        case 4:
++            //
++            // 4 pipes
++            //
++            // p0 = x1 ^ y0
++            // p1 = x0 ^ y1
++            //
++            // y0 = p0 ^ x1
++            // y1 = p1 ^ x0
++            //
++            pipeBit0 =  pipe & 0x1;
++            pipeBit1 = (pipe & 0x2) >> 1;
++
++            xBit0 =  x & 0x1;
++            xBit1 = (x & 0x2) >> 1;
++
++            yBit0 = pipeBit0 ^ xBit1;
++            yBit1 = pipeBit1 ^ xBit0;
++
++            y = (yBit0 |
++                 (yBit1 << 1));
++            break;
++        case 8:
++            //
++            // 8 pipes
++            //
++            // r600 and r800 have different method
++            //
++            y = HwlComputeXmaskCoordYFrom8Pipe(pipe, x);
++            break;
++        default:
++            break;
++    }
++    return y;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlComputeXmaskCoordFromAddr
++*
++*   @brief
++*       Compute the coord from an address of a cmask/htile
++*
++*   @return
++*       N/A
++*
++*   @note
++*       This method is reused by htile, so rename to Xmask
++***************************************************************************************************
++*/
++VOID AddrLib::HwlComputeXmaskCoordFromAddr(
++    UINT_64         addr,           ///< [in] address
++    UINT_32         bitPosition,    ///< [in] bitPosition in a byte
++    UINT_32         pitch,          ///< [in] pitch
++    UINT_32         height,         ///< [in] height
++    UINT_32         numSlices,      ///< [in] number of slices
++    UINT_32         factor,         ///< [in] factor that indicates cmask or htile
++    BOOL_32         isLinear,       ///< [in] linear or tiled HTILE layout
++    BOOL_32         isWidth8,       ///< [in] TRUE if width is 8, FALSE means 4. It's register value
++    BOOL_32         isHeight8,      ///< [in] TRUE if width is 8, FALSE means 4. It's register value
++    ADDR_TILEINFO*  pTileInfo,      ///< [in] Tile info
++    UINT_32*        pX,             ///< [out] x coord
++    UINT_32*        pY,             ///< [out] y coord
++    UINT_32*        pSlice          ///< [out] slice index
++    ) const
++{
++    UINT_32 pipe;
++    UINT_32 numPipes;
++    UINT_32 numGroupBits;
++    UINT_32 numPipeBits;
++    UINT_32 macroTilePitch;
++    UINT_32 macroTileHeight;
++
++    UINT_64 bitAddr;
++
++    UINT_32 microTileCoordY;
++
++    UINT_32 elemBits;
++
++    UINT_32 pitchAligned = pitch;
++    UINT_32 heightAligned = height;
++    UINT_64 totalBytes;
++
++    UINT_64 elemOffset;
++
++    UINT_64 macroIndex;
++    UINT_32 microIndex;
++
++    UINT_64 macroNumber;
++    UINT_32 microNumber;
++
++    UINT_32 macroX;
++    UINT_32 macroY;
++    UINT_32 macroZ;
++
++    UINT_32 microX;
++    UINT_32 microY;
++
++    UINT_32 tilesPerMacro;
++    UINT_32 macrosPerPitch;
++    UINT_32 macrosPerSlice;
++
++    //
++    // Extract pipe.
++    //
++    numPipes = HwlGetPipes(pTileInfo);
++    pipe = ComputePipeFromAddr(addr, numPipes);
++
++    //
++    // Compute the number of group and pipe bits.
++    //
++    numGroupBits = Log2(m_pipeInterleaveBytes);
++    numPipeBits  = Log2(numPipes);
++
++    UINT_32 groupBits = 8 * m_pipeInterleaveBytes;
++    UINT_32 pipes = numPipes;
++
++
++    //
++    // Compute the micro tile size, in bits. And macro tile pitch and height.
++    //
++    if (factor == 2) //CMASK
++    {
++        ADDR_CMASK_FLAGS flags = {{0}};
++
++        elemBits = CmaskElemBits;
++
++        ComputeCmaskInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         pTileInfo,
++                         &pitchAligned,
++                         &heightAligned,
++                         &totalBytes,
++                         &macroTilePitch,
++                         &macroTileHeight);
++    }
++    else  //HTILE
++    {
++        ADDR_HTILE_FLAGS flags = {{0}};
++
++        if (factor != 1)
++        {
++            factor = 1;
++        }
++
++        elemBits = HwlComputeHtileBpp(isWidth8, isHeight8);
++
++        ComputeHtileInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         isWidth8,
++                         isHeight8,
++                         pTileInfo,
++                         &pitchAligned,
++                         &heightAligned,
++                         &totalBytes,
++                         &macroTilePitch,
++                         &macroTileHeight);
++    }
++
++    // Should use aligned dims
++    //
++    pitch = pitchAligned;
++    height = heightAligned;
++
++
++    //
++    // Convert byte address to bit address.
++    //
++    bitAddr = BYTES_TO_BITS(addr) + bitPosition;
++
++
++    //
++    // Remove pipe bits from address.
++    //
++
++    bitAddr = (bitAddr % groupBits) + ((bitAddr/groupBits/pipes)*groupBits);
++
++
++    elemOffset = bitAddr / elemBits;
++
++    tilesPerMacro = (macroTilePitch/factor) * macroTileHeight / MicroTilePixels >> numPipeBits;
++
++    macrosPerPitch = pitch / (macroTilePitch/factor);
++    macrosPerSlice = macrosPerPitch * height / macroTileHeight;
++
++    macroIndex = elemOffset / factor / tilesPerMacro;
++    microIndex = static_cast<UINT_32>(elemOffset % (tilesPerMacro * factor));
++
++    macroNumber = macroIndex * factor + microIndex % factor;
++    microNumber = microIndex / factor;
++
++    macroX = static_cast<UINT_32>((macroNumber % macrosPerPitch));
++    macroY = static_cast<UINT_32>((macroNumber % macrosPerSlice) / macrosPerPitch);
++    macroZ = static_cast<UINT_32>((macroNumber / macrosPerSlice));
++
++
++    microX = microNumber % (macroTilePitch / factor / MicroTileWidth);
++    microY = (microNumber / (macroTilePitch / factor / MicroTileHeight));
++
++    *pX = macroX * (macroTilePitch/factor) + microX * MicroTileWidth;
++    *pY = macroY * macroTileHeight + (microY * MicroTileHeight << numPipeBits);
++    *pSlice = macroZ;
++
++    microTileCoordY = ComputeXmaskCoordYFromPipe(pipe,
++                                                 *pX/MicroTileWidth);
++
++
++    //
++    // Assemble final coordinates.
++    //
++    *pY += microTileCoordY * MicroTileHeight;
++
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlComputeXmaskAddrFromCoord
++*
++*   @brief
++*       Compute the address from an address of cmask (prior to si)
++*
++*   @return
++*       Address in bytes
++*
++***************************************************************************************************
++*/
++UINT_64 AddrLib::HwlComputeXmaskAddrFromCoord(
++    UINT_32        pitch,          ///< [in] pitch
++    UINT_32        height,         ///< [in] height
++    UINT_32        x,              ///< [in] x coord
++    UINT_32        y,              ///< [in] y coord
++    UINT_32        slice,          ///< [in] slice/depth index
++    UINT_32        numSlices,      ///< [in] number of slices
++    UINT_32        factor,         ///< [in] factor that indicates cmask(2) or htile(1)
++    BOOL_32        isLinear,       ///< [in] linear or tiled HTILE layout
++    BOOL_32        isWidth8,       ///< [in] TRUE if width is 8, FALSE means 4. It's register value
++    BOOL_32        isHeight8,      ///< [in] TRUE if width is 8, FALSE means 4. It's register value
++    ADDR_TILEINFO* pTileInfo,      ///< [in] Tile info
++    UINT_32*       pBitPosition    ///< [out] bit position inside a byte
++    ) const
++{
++    UINT_64 addr;
++    UINT_32 numGroupBits;
++    UINT_32 numPipeBits;
++    UINT_32 newPitch = 0;
++    UINT_32 newHeight = 0;
++    UINT_64 sliceBytes = 0;
++    UINT_64 totalBytes = 0;
++    UINT_64 sliceOffset;
++    UINT_32 pipe;
++    UINT_32 macroTileWidth;
++    UINT_32 macroTileHeight;
++    UINT_32 macroTilesPerRow;
++    UINT_32 macroTileBytes;
++    UINT_32 macroTileIndexX;
++    UINT_32 macroTileIndexY;
++    UINT_64 macroTileOffset;
++    UINT_32 pixelBytesPerRow;
++    UINT_32 pixelOffsetX;
++    UINT_32 pixelOffsetY;
++    UINT_32 pixelOffset;
++    UINT_64 totalOffset;
++    UINT_64 offsetLo;
++    UINT_64 offsetHi;
++    UINT_64 groupMask;
++
++
++    UINT_32 elemBits = 0;
++
++    UINT_32 numPipes = m_pipes; // This function is accessed prior to si only
++
++    if (factor == 2) //CMASK
++    {
++        elemBits = CmaskElemBits;
++
++        // For asics before SI, cmask is always tiled
++        isLinear = FALSE;
++    }
++    else //HTILE
++    {
++        if (factor != 1) // Fix compile warning
++        {
++            factor = 1;
++        }
++
++        elemBits = HwlComputeHtileBpp(isWidth8, isHeight8);
++    }
++
++    //
++    // Compute the number of group bits and pipe bits.
++    //
++    numGroupBits = Log2(m_pipeInterleaveBytes);
++    numPipeBits  = Log2(numPipes);
++
++    //
++    // Compute macro tile dimensions.
++    //
++    if (factor == 2) // CMASK
++    {
++        ADDR_CMASK_FLAGS flags = {{0}};
++
++        ComputeCmaskInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         pTileInfo,
++                         &newPitch,
++                         &newHeight,
++                         &totalBytes,
++                         &macroTileWidth,
++                         &macroTileHeight);
++
++        sliceBytes = totalBytes / numSlices;
++    }
++    else // HTILE
++    {
++        ADDR_HTILE_FLAGS flags = {{0}};
++
++        ComputeHtileInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         isWidth8,
++                         isHeight8,
++                         pTileInfo,
++                         &newPitch,
++                         &newHeight,
++                         &totalBytes,
++                         &macroTileWidth,
++                         &macroTileHeight,
++                         &sliceBytes);
++    }
++
++    sliceOffset = slice * sliceBytes;
++
++    //
++    // Get the pipe.  Note that neither slice rotation nor pipe swizzling apply for CMASK.
++    //
++    pipe = ComputePipeFromCoord(x,
++                                y,
++                                0,
++                                ADDR_TM_2D_TILED_THIN1,
++                                0,
++                                FALSE,
++                                pTileInfo);
++
++    //
++    // Compute the number of macro tiles per row.
++    //
++    macroTilesPerRow = newPitch / macroTileWidth;
++
++    //
++    // Compute the number of bytes per macro tile.
++    //
++    macroTileBytes = BITS_TO_BYTES((macroTileWidth * macroTileHeight * elemBits) / MicroTilePixels);
++
++    //
++    // Compute the offset to the macro tile containing the specified coordinate.
++    //
++    macroTileIndexX = x / macroTileWidth;
++    macroTileIndexY = y / macroTileHeight;
++    macroTileOffset = ((macroTileIndexY * macroTilesPerRow) + macroTileIndexX) * macroTileBytes;
++
++    //
++    // Compute the pixel offset within the macro tile.
++    //
++    pixelBytesPerRow = BITS_TO_BYTES(macroTileWidth * elemBits) / MicroTileWidth;
++
++    //
++    // The nibbles are interleaved (see below), so the part of the offset relative to the x
++    // coordinate repeats halfway across the row. (Not for HTILE)
++    //
++    if (factor == 2)
++    {
++        pixelOffsetX = (x % (macroTileWidth / 2)) / MicroTileWidth;
++    }
++    else
++    {
++        pixelOffsetX = (x % (macroTileWidth)) / MicroTileWidth * BITS_TO_BYTES(elemBits);
++    }
++
++    //
++    // Compute the y offset within the macro tile.
++    //
++    pixelOffsetY = (((y % macroTileHeight) / MicroTileHeight) / numPipes) * pixelBytesPerRow;
++
++    pixelOffset = pixelOffsetX + pixelOffsetY;
++
++    //
++    // Combine the slice offset and macro tile offset with the pixel offset, accounting for the
++    // pipe bits in the middle of the address.
++    //
++    totalOffset = ((sliceOffset + macroTileOffset) >> numPipeBits) + pixelOffset;
++
++    //
++    // Split the offset to put some bits below the pipe bits and some above.
++    //
++    groupMask = (1 << numGroupBits) - 1;
++    offsetLo  = totalOffset &  groupMask;
++    offsetHi  = (totalOffset & ~groupMask) << numPipeBits;
++
++    //
++    // Assemble the address from its components.
++    //
++    addr  = offsetLo;
++    addr |= offsetHi;
++    // This is to remove warning with /analyze option
++    UINT_32 pipeBits = pipe << numGroupBits;
++    addr |= pipeBits;
++
++    //
++    // Compute the bit position.  The lower nibble is used when the x coordinate within the macro
++    // tile is less than half of the macro tile width, and the upper nibble is used when the x
++    // coordinate within the macro tile is greater than or equal to half the macro tile width.
++    //
++    *pBitPosition = ((x % macroTileWidth) < (macroTileWidth / factor)) ? 0 : 4;
++
++    return addr;
++}
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Surface Addressing Shared
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceAddrFromCoordLinear
++*
++*   @brief
++*       Compute address from coord for linear surface
++*
++*   @return
++*       Address in bytes
++*
++***************************************************************************************************
++*/
++UINT_64 AddrLib::ComputeSurfaceAddrFromCoordLinear(
++    UINT_32  x,              ///< [in] x coord
++    UINT_32  y,              ///< [in] y coord
++    UINT_32  slice,          ///< [in] slice/depth index
++    UINT_32  sample,         ///< [in] sample index
++    UINT_32  bpp,            ///< [in] bits per pixel
++    UINT_32  pitch,          ///< [in] pitch
++    UINT_32  height,         ///< [in] height
++    UINT_32  numSlices,      ///< [in] number of slices
++    UINT_32* pBitPosition    ///< [out] bit position inside a byte
++    ) const
++{
++    const UINT_64 sliceSize = static_cast<UINT_64>(pitch) * height;
++
++    UINT_64 sliceOffset = (slice + sample * numSlices)* sliceSize;
++    UINT_64 rowOffset   = static_cast<UINT_64>(y) * pitch;
++    UINT_64 pixOffset   = x;
++
++    UINT_64 addr = (sliceOffset + rowOffset + pixOffset) * bpp;
++
++    *pBitPosition = static_cast<UINT_32>(addr % 8);
++    addr /= 8;
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceCoordFromAddrLinear
++*
++*   @brief
++*       Compute the coord from an address of a linear surface
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrLib::ComputeSurfaceCoordFromAddrLinear(
++    UINT_64  addr,           ///< [in] address
++    UINT_32  bitPosition,    ///< [in] bitPosition in a byte
++    UINT_32  bpp,            ///< [in] bits per pixel
++    UINT_32  pitch,          ///< [in] pitch
++    UINT_32  height,         ///< [in] height
++    UINT_32  numSlices,      ///< [in] number of slices
++    UINT_32* pX,             ///< [out] x coord
++    UINT_32* pY,             ///< [out] y coord
++    UINT_32* pSlice,         ///< [out] slice/depth index
++    UINT_32* pSample         ///< [out] sample index
++    ) const
++{
++    const UINT_64 sliceSize = static_cast<UINT_64>(pitch) * height;
++    const UINT_64 linearOffset = (BYTES_TO_BITS(addr) + bitPosition) / bpp;
++
++    *pX = static_cast<UINT_32>((linearOffset % sliceSize) % pitch);
++    *pY = static_cast<UINT_32>((linearOffset % sliceSize) / pitch % height);
++    *pSlice  = static_cast<UINT_32>((linearOffset / sliceSize) % numSlices);
++    *pSample = static_cast<UINT_32>((linearOffset / sliceSize) / numSlices);
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeSurfaceCoordFromAddrMicroTiled
++*
++*   @brief
++*       Compute the coord from an address of a micro tiled surface
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrLib::ComputeSurfaceCoordFromAddrMicroTiled(
++    UINT_64         addr,               ///< [in] address
++    UINT_32         bitPosition,        ///< [in] bitPosition in a byte
++    UINT_32         bpp,                ///< [in] bits per pixel
++    UINT_32         pitch,              ///< [in] pitch
++    UINT_32         height,             ///< [in] height
++    UINT_32         numSamples,         ///< [in] number of samples
++    AddrTileMode    tileMode,           ///< [in] tile mode
++    UINT_32         tileBase,           ///< [in] base offset within a tile
++    UINT_32         compBits,           ///< [in] component bits actually needed(for planar surface)
++    UINT_32*        pX,                 ///< [out] x coord
++    UINT_32*        pY,                 ///< [out] y coord
++    UINT_32*        pSlice,             ///< [out] slice/depth index
++    UINT_32*        pSample,            ///< [out] sample index,
++    AddrTileType    microTileType,      ///< [in] micro tiling order
++    BOOL_32         isDepthSampleOrder  ///< [in] TRUE if in depth sample order
++    ) const
++{
++    UINT_64 bitAddr;
++    UINT_32 microTileThickness;
++    UINT_32 microTileBits;
++    UINT_64 sliceBits;
++    UINT_64 rowBits;
++    UINT_32 sliceIndex;
++    UINT_32 microTileCoordX;
++    UINT_32 microTileCoordY;
++    UINT_32 pixelOffset;
++    UINT_32 pixelCoordX = 0;
++    UINT_32 pixelCoordY = 0;
++    UINT_32 pixelCoordZ = 0;
++    UINT_32 pixelCoordS = 0;
++
++    //
++    // Convert byte address to bit address.
++    //
++    bitAddr = BYTES_TO_BITS(addr) + bitPosition;
++
++    //
++    // Compute the micro tile size, in bits.
++    //
++    switch (tileMode)
++    {
++        case ADDR_TM_1D_TILED_THICK:
++            microTileThickness = ThickTileThickness;
++            break;
++        default:
++            microTileThickness = 1;
++            break;
++    }
++
++    microTileBits = MicroTilePixels * microTileThickness * bpp * numSamples;
++
++    //
++    // Compute number of bits per slice and number of bits per row of micro tiles.
++    //
++    sliceBits = static_cast<UINT_64>(pitch) * height * microTileThickness * bpp * numSamples;
++
++    rowBits   = (pitch / MicroTileWidth) * microTileBits;
++
++    //
++    // Extract the slice index.
++    //
++    sliceIndex = static_cast<UINT_32>(bitAddr / sliceBits);
++    bitAddr -= sliceIndex * sliceBits;
++
++    //
++    // Extract the y coordinate of the micro tile.
++    //
++    microTileCoordY = static_cast<UINT_32>(bitAddr / rowBits) * MicroTileHeight;
++    bitAddr -= (microTileCoordY / MicroTileHeight) * rowBits;
++
++    //
++    // Extract the x coordinate of the micro tile.
++    //
++    microTileCoordX = static_cast<UINT_32>(bitAddr / microTileBits) * MicroTileWidth;
++
++    //
++    // Compute the pixel offset within the micro tile.
++    //
++    pixelOffset = static_cast<UINT_32>(bitAddr % microTileBits);
++
++    //
++    // Extract pixel coordinates from the offset.
++    //
++    HwlComputePixelCoordFromOffset(pixelOffset,
++                                   bpp,
++                                   numSamples,
++                                   tileMode,
++                                   tileBase,
++                                   compBits,
++                                   &pixelCoordX,
++                                   &pixelCoordY,
++                                   &pixelCoordZ,
++                                   &pixelCoordS,
++                                   microTileType,
++                                   isDepthSampleOrder);
++
++    //
++    // Assemble final coordinates.
++    //
++    *pX     = microTileCoordX + pixelCoordX;
++    *pY     = microTileCoordY + pixelCoordY;
++    *pSlice = (sliceIndex * microTileThickness) + pixelCoordZ;
++    *pSample = pixelCoordS;
++
++    if (microTileThickness > 1)
++    {
++        *pSample = 0;
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputePipeFromAddr
++*
++*   @brief
++*       Compute the pipe number from an address
++*
++*   @return
++*       Pipe number
++*
++***************************************************************************************************
++*/
++UINT_32 AddrLib::ComputePipeFromAddr(
++    UINT_64 addr,        ///< [in] address
++    UINT_32 numPipes     ///< [in] number of banks
++    ) const
++{
++    UINT_32 pipe;
++
++    UINT_32 groupBytes = m_pipeInterleaveBytes; //just different terms
++
++    // R600
++    // The LSBs of the address are arranged as follows:
++    //   bank | pipe | group
++    //
++    // To get the pipe number, shift off the group bits and mask the pipe bits.
++    //
++
++    // R800
++    // The LSBs of the address are arranged as follows:
++    //   bank | bankInterleave | pipe | pipeInterleave
++    //
++    // To get the pipe number, shift off the pipe interleave bits and mask the pipe bits.
++    //
++
++    pipe = static_cast<UINT_32>(addr >> Log2(groupBytes)) & (numPipes - 1);
++
++    return pipe;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputePixelIndexWithinMicroTile
++*
++*   @brief
++*       Compute the pixel index inside a micro tile of surface
++*
++*   @return
++*       Pixel index
++*
++***************************************************************************************************
++*/
++UINT_32 AddrLib::ComputePixelIndexWithinMicroTile(
++    UINT_32         x,              ///< [in] x coord
++    UINT_32         y,              ///< [in] y coord
++    UINT_32         z,              ///< [in] slice/depth index
++    UINT_32         bpp,            ///< [in] bits per pixel
++    AddrTileMode    tileMode,       ///< [in] tile mode
++    AddrTileType    microTileType   ///< [in] pixel order in display/non-display mode
++    ) const
++{
++    UINT_32 pixelBit0 = 0;
++    UINT_32 pixelBit1 = 0;
++    UINT_32 pixelBit2 = 0;
++    UINT_32 pixelBit3 = 0;
++    UINT_32 pixelBit4 = 0;
++    UINT_32 pixelBit5 = 0;
++    UINT_32 pixelBit6 = 0;
++    UINT_32 pixelBit7 = 0;
++    UINT_32 pixelBit8 = 0;
++    UINT_32 pixelNumber;
++
++    UINT_32 x0 = _BIT(x, 0);
++    UINT_32 x1 = _BIT(x, 1);
++    UINT_32 x2 = _BIT(x, 2);
++    UINT_32 y0 = _BIT(y, 0);
++    UINT_32 y1 = _BIT(y, 1);
++    UINT_32 y2 = _BIT(y, 2);
++    UINT_32 z0 = _BIT(z, 0);
++    UINT_32 z1 = _BIT(z, 1);
++    UINT_32 z2 = _BIT(z, 2);
++
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++    // Compute the pixel number within the micro tile.
++
++    if (microTileType != ADDR_THICK)
++    {
++        if (microTileType == ADDR_DISPLAYABLE)
++        {
++            switch (bpp)
++            {
++                case 8:
++                    pixelBit0 = x0;
++                    pixelBit1 = x1;
++                    pixelBit2 = x2;
++                    pixelBit3 = y1;
++                    pixelBit4 = y0;
++                    pixelBit5 = y2;
++                    break;
++                case 16:
++                    pixelBit0 = x0;
++                    pixelBit1 = x1;
++                    pixelBit2 = x2;
++                    pixelBit3 = y0;
++                    pixelBit4 = y1;
++                    pixelBit5 = y2;
++                    break;
++                case 32:
++                    pixelBit0 = x0;
++                    pixelBit1 = x1;
++                    pixelBit2 = y0;
++                    pixelBit3 = x2;
++                    pixelBit4 = y1;
++                    pixelBit5 = y2;
++                    break;
++                case 64:
++                    pixelBit0 = x0;
++                    pixelBit1 = y0;
++                    pixelBit2 = x1;
++                    pixelBit3 = x2;
++                    pixelBit4 = y1;
++                    pixelBit5 = y2;
++                    break;
++                case 128:
++                    pixelBit0 = y0;
++                    pixelBit1 = x0;
++                    pixelBit2 = x1;
++                    pixelBit3 = x2;
++                    pixelBit4 = y1;
++                    pixelBit5 = y2;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    break;
++            }
++        }
++        else if (microTileType == ADDR_NON_DISPLAYABLE || microTileType == ADDR_DEPTH_SAMPLE_ORDER)
++        {
++            pixelBit0 = x0;
++            pixelBit1 = y0;
++            pixelBit2 = x1;
++            pixelBit3 = y1;
++            pixelBit4 = x2;
++            pixelBit5 = y2;
++        }
++        else if (microTileType == ADDR_ROTATED)
++        {
++            ADDR_ASSERT(thickness == 1);
++
++            switch (bpp)
++            {
++                case 8:
++                    pixelBit0 = y0;
++                    pixelBit1 = y1;
++                    pixelBit2 = y2;
++                    pixelBit3 = x1;
++                    pixelBit4 = x0;
++                    pixelBit5 = x2;
++                    break;
++                case 16:
++                    pixelBit0 = y0;
++                    pixelBit1 = y1;
++                    pixelBit2 = y2;
++                    pixelBit3 = x0;
++                    pixelBit4 = x1;
++                    pixelBit5 = x2;
++                    break;
++                case 32:
++                    pixelBit0 = y0;
++                    pixelBit1 = y1;
++                    pixelBit2 = x0;
++                    pixelBit3 = y2;
++                    pixelBit4 = x1;
++                    pixelBit5 = x2;
++                    break;
++                case 64:
++                    pixelBit0 = y0;
++                    pixelBit1 = x0;
++                    pixelBit2 = y1;
++                    pixelBit3 = x1;
++                    pixelBit4 = x2;
++                    pixelBit5 = y2;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    break;
++            }
++        }
++
++        if (thickness > 1)
++        {
++            pixelBit6 = z0;
++            pixelBit7 = z1;
++        }
++    }
++    else // ADDR_THICK
++    {
++        ADDR_ASSERT(thickness > 1);
++
++        switch (bpp)
++        {
++            case 8:
++            case 16:
++                pixelBit0 = x0;
++                pixelBit1 = y0;
++                pixelBit2 = x1;
++                pixelBit3 = y1;
++                pixelBit4 = z0;
++                pixelBit5 = z1;
++                break;
++            case 32:
++                pixelBit0 = x0;
++                pixelBit1 = y0;
++                pixelBit2 = x1;
++                pixelBit3 = z0;
++                pixelBit4 = y1;
++                pixelBit5 = z1;
++                break;
++            case 64:
++            case 128:
++                pixelBit0 = y0;
++                pixelBit1 = x0;
++                pixelBit2 = z0;
++                pixelBit3 = x1;
++                pixelBit4 = y1;
++                pixelBit5 = z1;
++                break;
++            default:
++                ADDR_ASSERT_ALWAYS();
++                break;
++        }
++
++        pixelBit6 = x2;
++        pixelBit7 = y2;
++    }
++
++    if (thickness == 8)
++    {
++        pixelBit8 = z2;
++    }
++
++    pixelNumber = ((pixelBit0     ) |
++                   (pixelBit1 << 1) |
++                   (pixelBit2 << 2) |
++                   (pixelBit3 << 3) |
++                   (pixelBit4 << 4) |
++                   (pixelBit5 << 5) |
++                   (pixelBit6 << 6) |
++                   (pixelBit7 << 7) |
++                   (pixelBit8 << 8));
++
++    return pixelNumber;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::AdjustPitchAlignment
++*
++*   @brief
++*       Adjusts pitch alignment for flipping surface
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrLib::AdjustPitchAlignment(
++    ADDR_SURFACE_FLAGS  flags,      ///< [in] Surface flags
++    UINT_32*            pPitchAlign ///< [out] Pointer to pitch alignment
++    ) const
++{
++    // Display engine hardwires lower 5 bit of GRPH_PITCH to ZERO which means 32 pixel alignment
++    // Maybe it will be fixed in future but let's make it general for now.
++    if (flags.display || flags.overlay)
++    {
++        *pPitchAlign = PowTwoAlign(*pPitchAlign, 32);
++
++        if(flags.display)
++        {
++            *pPitchAlign = Max(m_minPitchAlignPixels, *pPitchAlign);
++        }
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::PadDimensions
++*
++*   @brief
++*       Helper function to pad dimensions
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID AddrLib::PadDimensions(
++    AddrTileMode        tileMode,    ///< [in] tile mode
++    UINT_32             bpp,         ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,       ///< [in] surface flags
++    UINT_32             numSamples,  ///< [in] number of samples
++    ADDR_TILEINFO*      pTileInfo,   ///< [in/out] bank structure.
++    UINT_32             padDims,     ///< [in] Dimensions to pad valid value 1,2,3
++    UINT_32             mipLevel,    ///< [in] MipLevel
++    UINT_32*            pPitch,      ///< [in/out] pitch in pixels
++    UINT_32             pitchAlign,  ///< [in] pitch alignment
++    UINT_32*            pHeight,     ///< [in/out] height in pixels
++    UINT_32             heightAlign, ///< [in] height alignment
++    UINT_32*            pSlices,     ///< [in/out] number of slices
++    UINT_32             sliceAlign   ///< [in] number of slice alignment
++    ) const
++{
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++    ADDR_ASSERT(padDims <= 3);
++
++    //
++    // Override padding for mip levels
++    //
++    if (mipLevel > 0)
++    {
++        if (flags.cube)
++        {
++            // for cubemap, we only pad when client call with 6 faces as an identity
++            if (*pSlices > 1)
++            {
++                padDims = 3; // we should pad cubemap sub levels when we treat it as 3d texture
++            }
++            else
++            {
++                padDims = 2;
++            }
++        }
++    }
++
++    // Any possibilities that padDims is 0?
++    if (padDims == 0)
++    {
++        padDims = 3;
++    }
++
++    if (IsPow2(pitchAlign))
++    {
++        *pPitch = PowTwoAlign((*pPitch), pitchAlign);
++    }
++    else // add this code to pass unit test, r600 linear mode is not align bpp to pow2 for linear
++    {
++        *pPitch += pitchAlign - 1;
++        *pPitch /= pitchAlign;
++        *pPitch *= pitchAlign;
++    }
++
++    if (padDims > 1)
++    {
++        *pHeight = PowTwoAlign((*pHeight), heightAlign);
++    }
++
++    if (padDims > 2 || thickness > 1)
++    {
++        // for cubemap single face, we do not pad slices.
++        // if we pad it, the slice number should be set to 6 and current mip level > 1
++        if (flags.cube && (!m_configFlags.noCubeMipSlicesPad || flags.cubeAsArray))
++        {
++            *pSlices = NextPow2(*pSlices);
++        }
++
++        // normal 3D texture or arrays or cubemap has a thick mode? (Just pass unit test)
++        if (thickness > 1)
++        {
++            *pSlices = PowTwoAlign((*pSlices), sliceAlign);
++        }
++
++    }
++
++    HwlPadDimensions(tileMode,
++                     bpp,
++                     flags,
++                     numSamples,
++                     pTileInfo,
++                     padDims,
++                     mipLevel,
++                     pPitch,
++                     pitchAlign,
++                     pHeight,
++                     heightAlign,
++                     pSlices,
++                     sliceAlign);
++}
++
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlPreHandleBaseLvl3xPitch
++*
++*   @brief
++*       Pre-handler of 3x pitch (96 bit) adjustment
++*
++*   @return
++*       Expected pitch
++***************************************************************************************************
++*/
++UINT_32 AddrLib::HwlPreHandleBaseLvl3xPitch(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] input
++    UINT_32                                 expPitch    ///< [in] pitch
++    ) const
++{
++    ADDR_ASSERT(pIn->width == expPitch);
++    //
++    // If pitch is pre-multiplied by 3, we retrieve original one here to get correct miplevel size
++    //
++    if (AddrElemLib::IsExpand3x(pIn->format) &&
++        pIn->mipLevel == 0 &&
++        pIn->tileMode == ADDR_TM_LINEAR_ALIGNED)
++    {
++        expPitch /= 3;
++        expPitch = NextPow2(expPitch);
++    }
++
++    return expPitch;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlPostHandleBaseLvl3xPitch
++*
++*   @brief
++*       Post-handler of 3x pitch adjustment
++*
++*   @return
++*       Expected pitch
++***************************************************************************************************
++*/
++UINT_32 AddrLib::HwlPostHandleBaseLvl3xPitch(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] input
++    UINT_32                                 expPitch    ///< [in] pitch
++    ) const
++{
++    //
++    // 96 bits surface of sub levels require element pitch of 32 bits instead
++    // So we just return pitch in 32 bit pixels without timing 3
++    //
++    if (AddrElemLib::IsExpand3x(pIn->format) &&
++        pIn->mipLevel == 0 &&
++        pIn->tileMode == ADDR_TM_LINEAR_ALIGNED)
++    {
++        expPitch *= 3;
++    }
++
++    return expPitch;
++}
++
++
++/**
++***************************************************************************************************
++*   AddrLib::IsMacroTiled
++*
++*   @brief
++*       Check if the tile mode is macro tiled
++*
++*   @return
++*       TRUE if it is macro tiled (2D/2B/3D/3B)
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::IsMacroTiled(
++    AddrTileMode tileMode)  ///< [in] tile mode
++{
++   return m_modeFlags[tileMode].isMacro;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::IsMacro3dTiled
++*
++*   @brief
++*       Check if the tile mode is 3D macro tiled
++*
++*   @return
++*       TRUE if it is 3D macro tiled
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::IsMacro3dTiled(
++    AddrTileMode tileMode)  ///< [in] tile mode
++{
++    return m_modeFlags[tileMode].isMacro3d;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::IsMicroTiled
++*
++*   @brief
++*       Check if the tile mode is micro tiled
++*
++*   @return
++*       TRUE if micro tiled
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::IsMicroTiled(
++    AddrTileMode tileMode)  ///< [in] tile mode
++{
++    return m_modeFlags[tileMode].isMicro;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::IsLinear
++*
++*   @brief
++*       Check if the tile mode is linear
++*
++*   @return
++*       TRUE if linear
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::IsLinear(
++    AddrTileMode tileMode)  ///< [in] tile mode
++{
++    return m_modeFlags[tileMode].isLinear;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::IsPrtNoRotationTileMode
++*
++*   @brief
++*       Return TRUE if it is prt tile without rotation
++*   @note
++*       This function just used by CI
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::IsPrtNoRotationTileMode(
++    AddrTileMode tileMode)
++{
++    return m_modeFlags[tileMode].isPrtNoRotation;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::IsPrtTileMode
++*
++*   @brief
++*       Return TRUE if it is prt tile
++*   @note
++*       This function just used by CI
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::IsPrtTileMode(
++    AddrTileMode tileMode)
++{
++    return m_modeFlags[tileMode].isPrt;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::Bits2Number
++*
++*   @brief
++*       Cat a array of binary bit to a number
++*
++*   @return
++*       The number combined with the array of bits
++***************************************************************************************************
++*/
++UINT_32 AddrLib::Bits2Number(
++    UINT_32 bitNum,     ///< [in] how many bits
++    ...)                ///< [in] varaible bits value starting from MSB
++{
++    UINT_32 number = 0;
++    UINT_32 i;
++    va_list bits_ptr;
++
++    va_start(bits_ptr, bitNum);
++
++    for(i = 0; i < bitNum; i++)
++    {
++        number |= va_arg(bits_ptr, UINT_32);
++        number <<= 1;
++    }
++
++    number>>=1;
++
++    va_end(bits_ptr);
++
++    return number;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeMipLevel
++*
++*   @brief
++*       Compute mipmap level width/height/slices
++*   @return
++*      N/A
++***************************************************************************************************
++*/
++VOID AddrLib::ComputeMipLevel(
++    ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
++    ) const
++{
++    // Check if HWL has handled
++    BOOL_32 hwlHandled = FALSE;
++
++    if (AddrElemLib::IsBlockCompressed(pIn->format))
++    {
++        if (pIn->mipLevel == 0)
++        {
++            // DXTn's level 0 must be multiple of 4
++            // But there are exceptions:
++            // 1. Internal surface creation in hostblt/vsblt/etc...
++            // 2. Runtime doesn't reject ATI1/ATI2 whose width/height are not multiple of 4
++            pIn->width = PowTwoAlign(pIn->width, 4);
++            pIn->height = PowTwoAlign(pIn->height, 4);
++        }
++    }
++
++    hwlHandled = HwlComputeMipLevel(pIn);
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::DegradeBaseLevel
++*
++*   @brief
++*       Check if base level's tile mode can be degraded
++*   @return
++*       TRUE if degraded, also returns degraded tile mode (unchanged if not degraded)
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::DegradeBaseLevel(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] Input structure for surface info
++    AddrTileMode*                           pTileMode   ///< [out] Degraded tile mode
++    ) const
++{
++    BOOL_32 degraded = FALSE;
++    AddrTileMode tileMode = pIn->tileMode;
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++    if (m_configFlags.degradeBaseLevel) // This is a global setting
++    {
++        if (pIn->flags.degrade4Space        && // Degradation per surface
++            pIn->mipLevel == 0              &&
++            pIn->numSamples == 1            &&
++            IsMacroTiled(tileMode))
++        {
++            if (HwlDegradeBaseLevel(pIn))
++            {
++                *pTileMode = thickness == 1 ? ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
++                degraded = TRUE;
++            }
++            else if (thickness > 1)
++            {
++                // As in the following HwlComputeSurfaceInfo, thick modes may be degraded to
++                // thinner modes, we should re-evaluate whether the corresponding thinner modes
++                // need to be degraded. If so, we choose 1D thick mode instead.
++                tileMode = DegradeLargeThickTile(pIn->tileMode, pIn->bpp);
++                if (tileMode != pIn->tileMode)
++                {
++                    ADDR_COMPUTE_SURFACE_INFO_INPUT input = *pIn;
++                    input.tileMode = tileMode;
++                    if (HwlDegradeBaseLevel(&input))
++                    {
++                        *pTileMode = ADDR_TM_1D_TILED_THICK;
++                        degraded = TRUE;
++                    }
++                }
++            }
++        }
++    }
++
++    return degraded;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::DegradeLargeThickTile
++*
++*   @brief
++*       Check if the thickness needs to be reduced if a tile is too large
++*   @return
++*       The degraded tile mode (unchanged if not degraded)
++***************************************************************************************************
++*/
++AddrTileMode AddrLib::DegradeLargeThickTile(
++    AddrTileMode tileMode,
++    UINT_32 bpp) const
++{
++    // Override tilemode
++    // When tile_width (8) * tile_height (8) * thickness * element_bytes is > row_size,
++    // it is better to just use THIN mode in this case
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++    if (thickness > 1 && m_configFlags.allowLargeThickTile == 0)
++    {
++        UINT_32 tileSize = MicroTilePixels * thickness * (bpp >> 3);
++
++        if (tileSize > m_rowSize)
++        {
++            switch (tileMode)
++            {
++                case ADDR_TM_2D_TILED_XTHICK:
++                    if ((tileSize >> 1) <= m_rowSize)
++                    {
++                        tileMode = ADDR_TM_2D_TILED_THICK;
++                        break;
++                    }
++                    // else fall through
++                case ADDR_TM_2D_TILED_THICK:
++                    tileMode    = ADDR_TM_2D_TILED_THIN1;
++                    break;
++
++                case ADDR_TM_3D_TILED_XTHICK:
++                    if ((tileSize >> 1) <= m_rowSize)
++                    {
++                        tileMode = ADDR_TM_3D_TILED_THICK;
++                        break;
++                    }
++                    // else fall through
++                case ADDR_TM_3D_TILED_THICK:
++                    tileMode    = ADDR_TM_3D_TILED_THIN1;
++                    break;
++
++                case ADDR_TM_PRT_TILED_THICK:
++                    tileMode    = ADDR_TM_PRT_TILED_THIN1;
++                    break;
++
++                case ADDR_TM_PRT_2D_TILED_THICK:
++                    tileMode    = ADDR_TM_PRT_2D_TILED_THIN1;
++                    break;
++
++                case ADDR_TM_PRT_3D_TILED_THICK:
++                    tileMode    = ADDR_TM_PRT_3D_TILED_THIN1;
++                    break;
++
++                default:
++                    break;
++            }
++        }
++    }
++
++    return tileMode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::PostComputeMipLevel
++*   @brief
++*       Compute MipLevel info (including level 0) after surface adjustment
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::PostComputeMipLevel(
++    ADDR_COMPUTE_SURFACE_INFO_INPUT*    pIn,   ///< [in/out] Input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*   pOut   ///< [out] Output structure
++    ) const
++{
++    // Mipmap including level 0 must be pow2 padded since either SI hw expects so or it is
++    // required by CFX  for Hw Compatibility between NI and SI. Otherwise it is only needed for
++    // mipLevel > 0. Any h/w has different requirement should implement its own virtual function
++
++    if (pIn->flags.pow2Pad)
++    {
++        pIn->width      = NextPow2(pIn->width);
++        pIn->height     = NextPow2(pIn->height);
++        pIn->numSlices  = NextPow2(pIn->numSlices);
++    }
++    else if (pIn->mipLevel > 0)
++    {
++        pIn->width      = NextPow2(pIn->width);
++        pIn->height     = NextPow2(pIn->height);
++
++        if (!pIn->flags.cube)
++        {
++            pIn->numSlices = NextPow2(pIn->numSlices);
++        }
++
++        // for cubemap, we keep its value at first
++    }
++
++    return ADDR_OK;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlSetupTileCfg
++*
++*   @brief
++*       Map tile index to tile setting.
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::HwlSetupTileCfg(
++    INT_32          index,            ///< [in] Tile index
++    INT_32          macroModeIndex,   ///< [in] Index in macro tile mode table(CI)
++    ADDR_TILEINFO*  pInfo,            ///< [out] Tile Info
++    AddrTileMode*   pMode,            ///< [out] Tile mode
++    AddrTileType*   pType             ///< [out] Tile type
++    ) const
++{
++    return ADDR_NOTSUPPORTED;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::HwlGetPipes
++*
++*   @brief
++*       Get number pipes
++*   @return
++*       num pipes
++***************************************************************************************************
++*/
++UINT_32 AddrLib::HwlGetPipes(
++    const ADDR_TILEINFO* pTileInfo    ///< [in] Tile info
++    ) const
++{
++    //pTileInfo can be NULL when asic is 6xx and 8xx.
++    return m_pipes;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputeQbStereoInfo
++*
++*   @brief
++*       Get quad buffer stereo information
++*   @return
++*       TRUE if no error
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::ComputeQbStereoInfo(
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut    ///< [in/out] updated pOut+pStereoInfo
++    ) const
++{
++    BOOL_32 success = FALSE;
++
++    if (pOut->pStereoInfo)
++    {
++        ADDR_ASSERT(pOut->bpp >= 8);
++        ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
++
++        // Save original height
++        pOut->pStereoInfo->eyeHeight = pOut->height;
++
++        // Right offset
++        pOut->pStereoInfo->rightOffset = static_cast<UINT_32>(pOut->surfSize);
++
++        pOut->pStereoInfo->rightSwizzle = HwlComputeQbStereoRightSwizzle(pOut);
++        // Double height
++        pOut->height <<= 1;
++        pOut->pixelHeight <<= 1;
++
++        // Double size
++        pOut->surfSize <<= 1;
++
++        // Right start address meets the base align since it is guaranteed by AddrLib
++
++        // 1D surface on SI may break this rule, but we can force it to meet by checking .qbStereo.
++        success = TRUE;
++    }
++
++    return success;
++}
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++//                               Element lib
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++
++/**
++***************************************************************************************************
++*   AddrLib::Flt32ToColorPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a depth/stencil pixel value
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::Flt32ToDepthPixel(
++    const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
++    ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ELEM_FLT32TODEPTHPIXEL_INPUT)) ||
++            (pOut->size != sizeof(ELEM_FLT32TODEPTHPIXEL_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        GetElemLib()->Flt32ToDepthPixel(pIn->format,
++                                        pIn->comps,
++                                        pOut->pPixel);
++        UINT_32 depthBase = 0;
++        UINT_32 stencilBase = 0;
++        UINT_32 depthBits = 0;
++        UINT_32 stencilBits = 0;
++
++        switch (pIn->format)
++        {
++            case ADDR_DEPTH_16:
++                depthBits = 16;
++                break;
++            case ADDR_DEPTH_X8_24:
++            case ADDR_DEPTH_8_24:
++            case ADDR_DEPTH_X8_24_FLOAT:
++            case ADDR_DEPTH_8_24_FLOAT:
++                depthBase = 8;
++                depthBits = 24;
++                stencilBits = 8;
++                break;
++            case ADDR_DEPTH_32_FLOAT:
++                depthBits = 32;
++                break;
++            case ADDR_DEPTH_X24_8_32_FLOAT:
++                depthBase = 8;
++                depthBits = 32;
++                stencilBits = 8;
++                break;
++            default:
++                break;
++        }
++
++        // Overwrite base since R800 has no "tileBase"
++        if (GetElemLib()->IsDepthStencilTilePlanar() == FALSE)
++        {
++            depthBase = 0;
++            stencilBase = 0;
++        }
++
++        depthBase *= 64;
++        stencilBase *= 64;
++
++        pOut->stencilBase = stencilBase;
++        pOut->depthBase = depthBase;
++        pOut->depthBits = depthBits;
++        pOut->stencilBits = stencilBits;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::Flt32ToColorPixel
++*
++*   @brief
++*       Convert a FLT_32 value to a red/green/blue/alpha pixel value
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::Flt32ToColorPixel(
++    const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
++    ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if ((pIn->size != sizeof(ELEM_FLT32TOCOLORPIXEL_INPUT)) ||
++            (pOut->size != sizeof(ELEM_FLT32TOCOLORPIXEL_OUTPUT)))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        GetElemLib()->Flt32ToColorPixel(pIn->format,
++                                        pIn->surfNum,
++                                        pIn->surfSwap,
++                                        pIn->comps,
++                                        pOut->pPixel);
++    }
++
++    return returnCode;
++}
++
++
++/**
++***************************************************************************************************
++*   AddrLib::GetExportNorm
++*
++*   @brief
++*       Check one format can be EXPORT_NUM
++*   @return
++*       TRUE if EXPORT_NORM can be used
++***************************************************************************************************
++*/
++BOOL_32 AddrLib::GetExportNorm(
++    const ELEM_GETEXPORTNORM_INPUT* pIn) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    BOOL_32 enabled = FALSE;
++
++    if (GetFillSizeFieldsFlags() == TRUE)
++    {
++        if (pIn->size != sizeof(ELEM_GETEXPORTNORM_INPUT))
++        {
++            returnCode = ADDR_PARAMSIZEMISMATCH;
++        }
++    }
++
++    if (returnCode == ADDR_OK)
++    {
++        enabled = GetElemLib()->PixGetExportNorm(pIn->format,
++                                                 pIn->num,
++                                                 pIn->swap);
++    }
++
++    return enabled;
++}
++
++/**
++***************************************************************************************************
++*   AddrLib::ComputePrtInfo
++*
++*   @brief
++*       Compute prt surface related info
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE AddrLib::ComputePrtInfo(
++    const ADDR_PRT_INFO_INPUT*  pIn,
++    ADDR_PRT_INFO_OUTPUT*       pOut) const
++{
++    ADDR_ASSERT(pOut != NULL);
++
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    UINT_32     expandX = 1;
++    UINT_32     expandY = 1;
++    AddrElemMode elemMode;
++
++    UINT_32     bpp = GetElemLib()->GetBitsPerPixel(pIn->format,
++                                                &elemMode,
++                                                &expandX,
++                                                &expandY);
++
++    if (bpp <8 || bpp == 24 || bpp == 48 || bpp == 96 )
++    {
++        returnCode = ADDR_INVALIDPARAMS;
++    }
++
++    UINT_32     numFrags = pIn->numFrags;
++    ADDR_ASSERT(numFrags <= 8);
++
++    UINT_32     tileWidth = 0;
++    UINT_32     tileHeight = 0;
++    if (returnCode == ADDR_OK)
++    {
++        // 3D texture without depth or 2d texture
++        if (pIn->baseMipDepth > 1 || pIn->baseMipHeight > 1)
++        {
++            if (bpp == 8)
++            {
++                tileWidth = 256;
++                tileHeight = 256;
++            }
++            else if (bpp == 16)
++            {
++                tileWidth = 256;
++                tileHeight = 128;
++            }
++            else if (bpp == 32)
++            {
++                tileWidth = 128;
++                tileHeight = 128;
++            }
++            else if (bpp == 64)
++            {
++                // assume it is BC1/4
++                tileWidth = 512;
++                tileHeight = 256;
++
++                if (elemMode == ADDR_UNCOMPRESSED)
++                {
++                    tileWidth = 128;
++                    tileHeight = 64;
++                }
++            }
++            else if (bpp == 128)
++            {
++                // assume it is BC2/3/5/6H/7
++                tileWidth = 256;
++                tileHeight = 256;
++
++                if (elemMode == ADDR_UNCOMPRESSED)
++                {
++                    tileWidth = 64;
++                    tileHeight = 64;
++                }
++            }
++
++            if (numFrags == 2)
++            {
++                tileWidth = tileWidth / 2;
++            }
++            else if (numFrags == 4)
++            {
++                tileWidth = tileWidth / 2;
++                tileHeight = tileHeight / 2;
++            }
++            else if (numFrags == 8)
++            {
++                tileWidth = tileWidth / 4;
++                tileHeight = tileHeight / 2;
++            }
++        }
++        else    // 1d
++        {
++            tileHeight = 1;
++            if (bpp == 8)
++            {
++                tileWidth = 65536;
++            }
++            else if (bpp == 16)
++            {
++                tileWidth = 32768;
++            }
++            else if (bpp == 32)
++            {
++                tileWidth = 16384;
++            }
++            else if (bpp == 64)
++            {
++                tileWidth = 8192;
++            }
++            else if (bpp == 128)
++            {
++                tileWidth = 4096;
++            }
++        }
++    }
++
++    pOut->prtTileWidth = tileWidth;
++    pOut->prtTileHeight = tileHeight;
++
++    return returnCode;
++}
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.h b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.h
+new file mode 100644
+index 0000000..43c55ff
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrlib.h
+@@ -0,0 +1,695 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrlib.h
++* @brief Contains the AddrLib base class definition.
++***************************************************************************************************
++*/
++
++#ifndef __ADDR_LIB_H__
++#define __ADDR_LIB_H__
++
++
++#include "addrinterface.h"
++#include "addrobject.h"
++#include "addrelemlib.h"
++
++#if BRAHMA_BUILD
++#include "amdgpu_id.h"
++#else
++#include "atiid.h"
++#endif
++
++#ifndef CIASICIDGFXENGINE_R600
++#define CIASICIDGFXENGINE_R600 0x00000006
++#endif
++
++#ifndef CIASICIDGFXENGINE_R800
++#define CIASICIDGFXENGINE_R800 0x00000008
++#endif
++
++#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
++#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
++#endif
++
++#ifndef CIASICIDGFXENGINE_SEAISLAND
++#define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
++#endif
++/**
++***************************************************************************************************
++* @brief Neutral enums that define pipeinterleave
++***************************************************************************************************
++*/
++enum AddrPipeInterleave
++{
++    ADDR_PIPEINTERLEAVE_256B = 256,
++    ADDR_PIPEINTERLEAVE_512B = 512,
++};
++
++/**
++***************************************************************************************************
++* @brief Neutral enums that define DRAM row size
++***************************************************************************************************
++*/
++enum AddrRowSize
++{
++    ADDR_ROWSIZE_1KB = 1024,
++    ADDR_ROWSIZE_2KB = 2048,
++    ADDR_ROWSIZE_4KB = 4096,
++    ADDR_ROWSIZE_8KB = 8192,
++};
++
++/**
++***************************************************************************************************
++* @brief Neutral enums that define bank interleave
++***************************************************************************************************
++*/
++enum AddrBankInterleave
++{
++    ADDR_BANKINTERLEAVE_1 = 1,
++    ADDR_BANKINTERLEAVE_2 = 2,
++    ADDR_BANKINTERLEAVE_4 = 4,
++    ADDR_BANKINTERLEAVE_8 = 8,
++};
++
++/**
++***************************************************************************************************
++* @brief Neutral enums that define MGPU chip tile size
++***************************************************************************************************
++*/
++enum AddrChipTileSize
++{
++    ADDR_CHIPTILESIZE_16 = 16,
++    ADDR_CHIPTILESIZE_32 = 32,
++    ADDR_CHIPTILESIZE_64 = 64,
++    ADDR_CHIPTILESIZE_128 = 128,
++};
++
++/**
++***************************************************************************************************
++* @brief Neutral enums that define shader engine tile size
++***************************************************************************************************
++*/
++enum AddrEngTileSize
++{
++    ADDR_SE_TILESIZE_16 = 16,
++    ADDR_SE_TILESIZE_32 = 32,
++};
++
++/**
++***************************************************************************************************
++* @brief Neutral enums that define bank swap size
++***************************************************************************************************
++*/
++enum AddrBankSwapSize
++{
++    ADDR_BANKSWAP_128B = 128,
++    ADDR_BANKSWAP_256B = 256,
++    ADDR_BANKSWAP_512B = 512,
++    ADDR_BANKSWAP_1KB = 1024,
++};
++
++/**
++***************************************************************************************************
++* @brief Neutral enums that define bank swap size
++***************************************************************************************************
++*/
++enum AddrSampleSplitSize
++{
++    ADDR_SAMPLESPLIT_1KB = 1024,
++    ADDR_SAMPLESPLIT_2KB = 2048,
++    ADDR_SAMPLESPLIT_4KB = 4096,
++    ADDR_SAMPLESPLIT_8KB = 8192,
++};
++
++/**
++***************************************************************************************************
++* @brief Flags for AddrTileMode
++***************************************************************************************************
++*/
++struct AddrTileModeFlags
++{
++    UINT_32 thickness       : 4;
++    UINT_32 isLinear        : 1;
++    UINT_32 isMicro         : 1;
++    UINT_32 isMacro         : 1;
++    UINT_32 isMacro3d       : 1;
++    UINT_32 isPrt           : 1;
++    UINT_32 isPrtNoRotation : 1;
++    UINT_32 isBankSwapped   : 1;
++};
++
++/**
++***************************************************************************************************
++* @brief This class contains asic independent address lib functionalities
++***************************************************************************************************
++*/
++class AddrLib : public AddrObject
++{
++public:
++    virtual ~AddrLib();
++
++    static ADDR_E_RETURNCODE Create(
++        const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
++
++    /// Pair of Create
++    VOID Destroy()
++    {
++        delete this;
++    }
++
++    static AddrLib* GetAddrLib(
++        ADDR_HANDLE hLib);
++
++    /// Returns AddrLib version (from compiled binary instead include file)
++    UINT_32 GetVersion()
++    {
++        return m_version;
++    }
++
++    /// Returns asic chip family name defined by AddrLib
++    AddrChipFamily GetAddrChipFamily()
++    {
++        return m_chipFamily;
++    }
++
++    /// Returns tileIndex support
++    BOOL_32 UseTileIndex(INT_32 index) const
++    {
++        return m_configFlags.useTileIndex && (index != TileIndexInvalid);
++    }
++
++    /// Returns combined swizzle support
++    BOOL_32 UseCombinedSwizzle() const
++    {
++        return m_configFlags.useCombinedSwizzle;
++    }
++
++    //
++    // Interface stubs
++    //
++    ADDR_E_RETURNCODE ComputeSurfaceInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
++        const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
++        const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT*  pIn,
++        ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeSliceTileSwizzle(
++        const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,
++        ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ExtractBankPipeSwizzle(
++        const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
++        ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE CombineBankPipeSwizzle(
++        const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,
++        ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeBaseSwizzle(
++        const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
++        ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeFmaskInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT*  pIn,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
++
++    ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
++        const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*  pIn,
++        ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
++        const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*  pIn,
++        ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ConvertTileInfoToHW(
++        const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
++        ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ConvertTileIndex(
++        const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
++        ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ConvertTileIndex1(
++        const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
++        ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE GetTileIndex(
++        const ADDR_GET_TILEINDEX_INPUT* pIn,
++        ADDR_GET_TILEINDEX_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeHtileInfo(
++        const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeCmaskInfo(
++        const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
++        ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeDccInfo(
++        const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
++        ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
++        const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*  pIn,
++        ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
++        const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*  pIn,
++        ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
++        const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*  pIn,
++        ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
++        const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*  pIn,
++        ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE ComputePrtInfo(
++        const ADDR_PRT_INFO_INPUT*  pIn,
++        ADDR_PRT_INFO_OUTPUT*       pOut) const;
++
++    ADDR_E_RETURNCODE Flt32ToDepthPixel(
++        const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
++        ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE Flt32ToColorPixel(
++        const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
++        ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
++
++    BOOL_32 GetExportNorm(
++        const ELEM_GETEXPORTNORM_INPUT* pIn) const;
++
++protected:
++    AddrLib();  // Constructor is protected
++    AddrLib(const AddrClient* pClient);
++
++    /// Pure Virtual function for Hwl computing surface info
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl computing surface address from coord
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
++        const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl computing surface coord from address
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
++        const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl computing surface tile swizzle
++    virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
++        const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
++        ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl extracting bank/pipe swizzle from base256b
++    virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
++        const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
++        ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl combining bank/pipe swizzle
++    virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
++        UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO*  pTileInfo,
++        UINT_64 baseAddr, UINT_32* pTileSwizzle) const = 0;
++
++    /// Pure Virtual function for Hwl computing base swizzle
++    virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
++        const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
++        ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl computing HTILE base align
++    virtual UINT_32 HwlComputeHtileBaseAlign(
++        BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0;
++
++    /// Pure Virtual function for Hwl computing HTILE bpp
++    virtual UINT_32 HwlComputeHtileBpp(
++        BOOL_32 isWidth8, BOOL_32 isHeight8) const = 0;
++
++    /// Pure Virtual function for Hwl computing HTILE bytes
++    virtual UINT_64 HwlComputeHtileBytes(
++        UINT_32 pitch, UINT_32 height, UINT_32 bpp,
++        BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
++
++    /// Pure Virtual function for Hwl computing FMASK info
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut) = 0;
++
++    /// Pure Virtual function for Hwl FMASK address from coord
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
++        const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl FMASK coord from address
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
++        const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl convert tile info from real value to HW value
++    virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
++        const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
++        ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const = 0;
++
++    /// Pure Virtual function for Hwl compute mipmap info
++    virtual BOOL_32 HwlComputeMipLevel(
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
++
++    /// Pure Virtual function for Hwl compute max cmask blockMax value
++    virtual BOOL_32 HwlGetMaxCmaskBlockMax() const = 0;
++
++    /// Pure Virtual function for Hwl compute fmask bits
++    virtual UINT_32 HwlComputeFmaskBits(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++        UINT_32* pNumSamples) const = 0;
++
++    /// Virtual function to get index (not pure then no need to implement this in all hwls
++    virtual ADDR_E_RETURNCODE HwlGetTileIndex(
++        const ADDR_GET_TILEINDEX_INPUT* pIn,
++        ADDR_GET_TILEINDEX_OUTPUT*      pOut) const
++    {
++        return ADDR_NOTSUPPORTED;
++    }
++
++    /// Virtual function for Hwl to compute Dcc info
++    virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
++        const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
++        ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const
++    {
++        return ADDR_NOTSUPPORTED;
++    }
++
++    /// Virtual function to get cmask address for tc compatible cmask
++    virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
++        const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
++    {
++        return ADDR_NOTSUPPORTED;
++    }
++    // Compute attributes
++
++    // HTILE
++    UINT_32    ComputeHtileInfo(
++        ADDR_HTILE_FLAGS flags,
++        UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices,
++        BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
++        ADDR_TILEINFO*  pTileInfo,
++        UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pHtileBytes,
++        UINT_32* pMacroWidth = NULL, UINT_32* pMacroHeight = NULL,
++        UINT_64* pSliceSize = NULL, UINT_32* pBaseAlign = NULL) const;
++
++    // CMASK
++    ADDR_E_RETURNCODE ComputeCmaskInfo(
++        ADDR_CMASK_FLAGS flags,
++        UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices, BOOL_32 isLinear,
++        ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes,
++        UINT_32* pMacroWidth, UINT_32* pMacroHeight, UINT_64* pSliceSize = NULL,
++        UINT_32* pBaseAlign = NULL, UINT_32* pBlockMax = NULL) const;
++
++    virtual VOID HwlComputeTileDataWidthAndHeightLinear(
++        UINT_32* pMacroWidth, UINT_32* pMacroHeight,
++        UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
++
++    // CMASK & HTILE addressing
++    virtual UINT_64 HwlComputeXmaskAddrFromCoord(
++        UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice,
++        UINT_32 numSlices, UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8,
++        BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo,
++        UINT_32* bitPosition) const;
++
++    virtual VOID HwlComputeXmaskCoordFromAddr(
++        UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
++        UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
++        ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
++
++    // Surface mipmap
++    VOID    ComputeMipLevel(
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
++
++    /// Pure Virtual function for Hwl checking degrade for base level
++    virtual BOOL_32 HwlDegradeBaseLevel(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
++
++    virtual BOOL_32 HwlOverrideTileMode(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        AddrTileMode* pTileMode,
++        AddrTileType* pTileType) const
++    {
++        // not supported in hwl layer, FALSE for not-overrided
++        return FALSE;
++    }
++
++    AddrTileMode DegradeLargeThickTile(AddrTileMode tileMode, UINT_32 bpp) const;
++
++    VOID PadDimensions(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
++        UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
++        UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
++        UINT_32* pSlices, UINT_32 sliceAlign) const;
++
++    virtual VOID HwlPadDimensions(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
++        UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
++        UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
++        UINT_32* pSlices, UINT_32 sliceAlign) const
++    {
++    }
++
++    //
++    // Addressing shared for linear/1D tiling
++    //
++    UINT_64 ComputeSurfaceAddrFromCoordLinear(
++        UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
++        UINT_32* pBitPosition) const;
++
++    VOID    ComputeSurfaceCoordFromAddrLinear(
++        UINT_64 addr, UINT_32 bitPosition, UINT_32 bpp,
++        UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
++
++    VOID    ComputeSurfaceCoordFromAddrMicroTiled(
++        UINT_64 addr, UINT_32 bitPosition,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
++        AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
++
++    UINT_32 ComputePixelIndexWithinMicroTile(
++        UINT_32 x, UINT_32 y, UINT_32 z,
++        UINT_32 bpp, AddrTileMode tileMode, AddrTileType microTileType) const;
++
++    /// Pure Virtual function for Hwl computing coord from offset inside micro tile
++    virtual VOID HwlComputePixelCoordFromOffset(
++        UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
++        AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
++        AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const = 0;
++
++    //
++    // Addressing shared by all
++    //
++    virtual UINT_32 HwlGetPipes(
++        const ADDR_TILEINFO* pTileInfo) const;
++
++    UINT_32 ComputePipeFromAddr(
++        UINT_64 addr, UINT_32 numPipes) const;
++
++    /// Pure Virtual function for Hwl computing pipe from coord
++    virtual UINT_32 ComputePipeFromCoord(
++        UINT_32 x, UINT_32 y, UINT_32 slice, AddrTileMode tileMode,
++        UINT_32 pipeSwizzle, BOOL_32 flags, ADDR_TILEINFO* pTileInfo) const = 0;
++
++    /// Pure Virtual function for Hwl computing coord Y for 8 pipe cmask/htile
++    virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
++        UINT_32 pipe, UINT_32 x) const = 0;
++
++    //
++    // Initialization
++    //
++    /// Pure Virtual function for Hwl computing internal global parameters from h/w registers
++    virtual BOOL_32 HwlInitGlobalParams(
++        const ADDR_CREATE_INPUT* pCreateIn) = 0;
++
++    /// Pure Virtual function for Hwl converting chip family
++    virtual AddrChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
++
++    //
++    // Misc helper
++    //
++    static const AddrTileModeFlags m_modeFlags[ADDR_TM_COUNT];
++
++    static UINT_32 ComputeSurfaceThickness(
++        AddrTileMode tileMode);
++
++    // Checking tile mode
++    static BOOL_32 IsMacroTiled(AddrTileMode tileMode);
++    static BOOL_32 IsMacro3dTiled(AddrTileMode tileMode);
++    static BOOL_32 IsLinear(AddrTileMode tileMode);
++    static BOOL_32 IsMicroTiled(AddrTileMode tileMode);
++    static BOOL_32 IsPrtTileMode(AddrTileMode tileMode);
++    static BOOL_32 IsPrtNoRotationTileMode(AddrTileMode tileMode);
++
++    static UINT_32 Bits2Number(UINT_32 bitNum,...);
++
++    static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
++    {
++        return numFrags != 0 ? numFrags : Max(1u, numSamples);
++    }
++
++    /// Returns pointer of AddrElemLib
++    AddrElemLib* GetElemLib() const
++    {
++        return m_pElemLib;
++    }
++
++    /// Return TRUE if tile info is needed
++    BOOL_32 UseTileInfo() const
++    {
++        return !m_configFlags.ignoreTileInfo;
++    }
++
++    /// Returns fillSizeFields flag
++    UINT_32 GetFillSizeFieldsFlags() const
++    {
++        return m_configFlags.fillSizeFields;
++    }
++
++    /// Adjusts pitch alignment for flipping surface
++    VOID    AdjustPitchAlignment(
++        ADDR_SURFACE_FLAGS flags, UINT_32* pPitchAlign) const;
++
++    /// Overwrite tile config according to tile index
++    virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
++        INT_32 index, INT_32 macroModeIndex,
++        ADDR_TILEINFO* pInfo, AddrTileMode* mode = NULL, AddrTileType* type = NULL) const;
++
++    /// Overwrite macro tile config according to tile index
++    virtual INT_32 HwlComputeMacroModeIndex(
++        INT_32 index, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
++        ADDR_TILEINFO* pTileInfo, AddrTileMode *pTileMode = NULL, AddrTileType *pTileType = NULL
++        ) const
++    {
++        return TileIndexNoMacroIndex;
++    }
++
++    /// Pre-handler of 3x pitch (96 bit) adjustment
++    virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
++    /// Post-handler of 3x pitch adjustment
++    virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
++    /// Check miplevel after surface adjustment
++    ADDR_E_RETURNCODE PostComputeMipLevel(
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    /// Quad buffer stereo support, has its implementation in ind. layer
++    virtual BOOL_32 ComputeQbStereoInfo(
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    /// Pure virutual function to compute stereo bank swizzle for right eye
++    virtual UINT_32 HwlComputeQbStereoRightSwizzle(
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
++
++private:
++    // Disallow the copy constructor
++    AddrLib(const AddrLib& a);
++
++    // Disallow the assignment operator
++    AddrLib& operator=(const AddrLib& a);
++
++    VOID SetAddrChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
++
++    UINT_32 ComputeCmaskBaseAlign(
++        ADDR_CMASK_FLAGS flags, ADDR_TILEINFO*  pTileInfo) const;
++
++    UINT_64 ComputeCmaskBytes(
++        UINT_32 pitch, UINT_32 height, UINT_32 numSlices) const;
++
++    //
++    // CMASK/HTILE shared methods
++    //
++    VOID    ComputeTileDataWidthAndHeight(
++        UINT_32 bpp, UINT_32 cacheBits, ADDR_TILEINFO* pTileInfo,
++        UINT_32* pMacroWidth, UINT_32* pMacroHeight) const;
++
++    UINT_32 ComputeXmaskCoordYFromPipe(
++        UINT_32 pipe, UINT_32 x) const;
++
++    VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
++
++    BOOL_32 DegradeBaseLevel(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, AddrTileMode* pTileMode) const;
++
++protected:
++    AddrLibClass        m_class;        ///< Store class type (HWL type)
++
++    AddrChipFamily      m_chipFamily;   ///< Chip family translated from the one in atiid.h
++
++    UINT_32             m_chipRevision; ///< Revision id from xxx_id.h
++
++    UINT_32             m_version;      ///< Current version
++
++    //
++    // Global parameters
++    //
++    ADDR_CONFIG_FLAGS   m_configFlags;  ///< Global configuration flags. Note this is setup by
++                                        ///  AddrLib instead of Client except forceLinearAligned
++
++    UINT_32             m_pipes;        ///< Number of pipes
++    UINT_32             m_banks;        ///< Number of banks
++                                        ///  For r800 this is MC_ARB_RAMCFG.NOOFBANK
++                                        ///  Keep it here to do default parameter calculation
++
++    UINT_32             m_pipeInterleaveBytes;
++                                        ///< Specifies the size of contiguous address space
++                                        ///  within each tiling pipe when making linear
++                                        ///  accesses. (Formerly Group Size)
++
++    UINT_32             m_rowSize;      ///< DRAM row size, in bytes
++
++    UINT_32             m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
++    UINT_32             m_maxSamples;   ///< Max numSamples
++private:
++    AddrElemLib*        m_pElemLib;     ///< Element Lib pointer
++};
++
++AddrLib* AddrSIHwlInit  (const AddrClient* pClient);
++AddrLib* AddrCIHwlInit  (const AddrClient* pClient);
++
++#endif
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.cpp
+new file mode 100644
+index 0000000..863a252
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.cpp
+@@ -0,0 +1,246 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrobject.cpp
++* @brief Contains the AddrObject base class implementation.
++***************************************************************************************************
++*/
++
++#include "addrinterface.h"
++#include "addrobject.h"
++
++/**
++***************************************************************************************************
++*   AddrObject::AddrObject
++*
++*   @brief
++*       Constructor for the AddrObject class.
++***************************************************************************************************
++*/
++AddrObject::AddrObject()
++{
++    m_client.handle = NULL;
++    m_client.callbacks.allocSysMem = NULL;
++    m_client.callbacks.freeSysMem = NULL;
++    m_client.callbacks.debugPrint = NULL;
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::AddrObject
++*
++*   @brief
++*       Constructor for the AddrObject class.
++***************************************************************************************************
++*/
++AddrObject::AddrObject(const AddrClient* pClient)
++{
++    m_client = *pClient;
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::~AddrObject
++*
++*   @brief
++*       Destructor for the AddrObject class.
++***************************************************************************************************
++*/
++AddrObject::~AddrObject()
++{
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::ClientAlloc
++*
++*   @brief
++*       Calls instanced allocSysMem inside AddrClient
++***************************************************************************************************
++*/
++VOID* AddrObject::ClientAlloc(
++    size_t             objSize,    ///< [in] Size to allocate
++    const AddrClient*  pClient)    ///< [in] Client pointer
++{
++    VOID* pObjMem = NULL;
++
++    if (pClient->callbacks.allocSysMem != NULL)
++    {
++        ADDR_ALLOCSYSMEM_INPUT allocInput = {0};
++
++        allocInput.size        = sizeof(ADDR_ALLOCSYSMEM_INPUT);
++        allocInput.flags.value = 0;
++        allocInput.sizeInBytes = static_cast<UINT_32>(objSize);
++        allocInput.hClient     = pClient->handle;
++
++        pObjMem = pClient->callbacks.allocSysMem(&allocInput);
++    }
++
++    return pObjMem;
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::AddrMalloc
++*
++*   @brief
++*       A wrapper of ClientAlloc
++***************************************************************************************************
++*/
++VOID* AddrObject::AddrMalloc(
++    size_t objSize) const   ///< [in] Size to allocate
++{
++    return ClientAlloc(objSize, &m_client);;
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::ClientFree
++*
++*   @brief
++*       Calls freeSysMem inside AddrClient
++***************************************************************************************************
++*/
++VOID AddrObject::ClientFree(
++    VOID*              pObjMem,    ///< [in] User virtual address to free.
++    const AddrClient*  pClient)    ///< [in] Client pointer
++{
++    if (pClient->callbacks.freeSysMem != NULL)
++    {
++        if (pObjMem != NULL)
++        {
++            ADDR_FREESYSMEM_INPUT freeInput = {0};
++
++            freeInput.size      = sizeof(ADDR_FREESYSMEM_INPUT);
++            freeInput.hClient   = pClient->handle;
++            freeInput.pVirtAddr = pObjMem;
++
++            pClient->callbacks.freeSysMem(&freeInput);
++        }
++    }
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::AddrFree
++*
++*   @brief
++*       A wrapper of ClientFree
++***************************************************************************************************
++*/
++VOID AddrObject::AddrFree(
++    VOID* pObjMem) const                 ///< [in] User virtual address to free.
++{
++    ClientFree(pObjMem, &m_client);
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::operator new
++*
++*   @brief
++*       Allocates memory needed for AddrObject object. (with ADDR_CLIENT_HANDLE)
++*
++*   @return
++*       Returns NULL if unsuccessful.
++***************************************************************************************************
++*/
++VOID* AddrObject::operator new(
++    size_t             objSize,    ///< [in] Size to allocate
++    const AddrClient*  pClient)    ///< [in] Client pointer
++{
++    return ClientAlloc(objSize, pClient);
++}
++
++
++/**
++***************************************************************************************************
++*   AddrObject::operator delete
++*
++*   @brief
++*       Frees AddrObject object memory.
++***************************************************************************************************
++*/
++VOID AddrObject::operator delete(
++    VOID* pObjMem,              ///< [in] User virtual address to free.
++    const AddrClient* pClient)  ///< [in] Client handle
++{
++    ClientFree(pObjMem, pClient);
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::operator delete
++*
++*   @brief
++*       Frees AddrObject object memory.
++***************************************************************************************************
++*/
++VOID AddrObject::operator delete(
++    VOID* pObjMem)                  ///< [in] User virtual address to free.
++{
++    AddrObject* pObj = static_cast<AddrObject*>(pObjMem);
++    ClientFree(pObjMem, &pObj->m_client);
++}
++
++/**
++***************************************************************************************************
++*   AddrObject::DebugPrint
++*
++*   @brief
++*       Print debug message
++*
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID AddrObject::DebugPrint(
++    const CHAR* pDebugString,     ///< [in] Debug string
++    ...) const
++{
++#if DEBUG
++    if (m_client.callbacks.debugPrint != NULL)
++    {
++        va_list ap;
++
++        va_start(ap, pDebugString);
++
++        ADDR_DEBUGPRINT_INPUT debugPrintInput = {0};
++
++        debugPrintInput.size         = sizeof(ADDR_DEBUGPRINT_INPUT);
++        debugPrintInput.pDebugString = const_cast<CHAR*>(pDebugString);
++        debugPrintInput.hClient      = m_client.handle;
++        va_copy(debugPrintInput.ap, ap);
++
++        m_client.callbacks.debugPrint(&debugPrintInput);
++
++        va_end(ap);
++    }
++#endif
++}
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.h b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.h
+new file mode 100644
+index 0000000..3540088
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/core/addrobject.h
+@@ -0,0 +1,89 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  addrobject.h
++* @brief Contains the AddrObject base class definition.
++***************************************************************************************************
++*/
++
++#ifndef __ADDR_OBJECT_H__
++#define __ADDR_OBJECT_H__
++
++#include "addrtypes.h"
++#include "addrcommon.h"
++
++/**
++***************************************************************************************************
++* @brief This structure contains client specific data
++***************************************************************************************************
++*/
++struct AddrClient
++{
++    ADDR_CLIENT_HANDLE  handle;
++    ADDR_CALLBACKS      callbacks;
++};
++/**
++***************************************************************************************************
++* @brief This class is the base class for all ADDR class objects.
++***************************************************************************************************
++*/
++class AddrObject
++{
++public:
++    AddrObject();
++    AddrObject(const AddrClient* pClient);
++    virtual ~AddrObject();
++
++    VOID* operator new(size_t size, const AddrClient* pClient);
++    VOID  operator delete(VOID* pObj, const AddrClient* pClient);
++    VOID  operator delete(VOID* pObj);
++    VOID* AddrMalloc(size_t size) const;
++    VOID  AddrFree(VOID* pObj) const;
++
++    VOID DebugPrint(
++        const CHAR* pDebugString,
++        ...) const;
++
++    const AddrClient* GetClient() const {return &m_client;}
++
++protected:
++    AddrClient m_client;
++
++private:
++    static VOID* ClientAlloc(size_t size, const AddrClient* pClient);
++    static VOID  ClientFree(VOID* pObj, const AddrClient* pClient);
++
++    // disallow the copy constructor
++    AddrObject(const AddrObject& a);
++
++    // disallow the assignment operator
++    AddrObject& operator=(const AddrObject& a);
++};
++
++#endif
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/inc/chip/r800/si_gb_reg.h b/src/gallium/winsys/radeon/amdgpu/addrlib/inc/chip/r800/si_gb_reg.h
+new file mode 100644
+index 0000000..cf67f60
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/inc/chip/r800/si_gb_reg.h
+@@ -0,0 +1,155 @@
++#if !defined (__SI_GB_REG_H__)
++#define __SI_GB_REG_H__
++
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++//
++// Make sure the necessary endian defines are there.
++//
++#if defined(LITTLEENDIAN_CPU)
++#elif defined(BIGENDIAN_CPU)
++#else
++#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
++#endif
++
++/*
++ * GB_ADDR_CONFIG struct
++ */
++
++#if     defined(LITTLEENDIAN_CPU)
++
++     typedef struct _GB_ADDR_CONFIG_T {
++          unsigned int num_pipes                      : 3;
++          unsigned int                                : 1;
++          unsigned int pipe_interleave_size           : 3;
++          unsigned int                                : 1;
++          unsigned int bank_interleave_size           : 3;
++          unsigned int                                : 1;
++          unsigned int num_shader_engines             : 2;
++          unsigned int                                : 2;
++          unsigned int shader_engine_tile_size        : 3;
++          unsigned int                                : 1;
++          unsigned int num_gpus                       : 3;
++          unsigned int                                : 1;
++          unsigned int multi_gpu_tile_size            : 2;
++          unsigned int                                : 2;
++          unsigned int row_size                       : 2;
++          unsigned int num_lower_pipes                : 1;
++          unsigned int                                : 1;
++     } GB_ADDR_CONFIG_T;
++
++#elif       defined(BIGENDIAN_CPU)
++
++     typedef struct _GB_ADDR_CONFIG_T {
++          unsigned int                                : 1;
++          unsigned int num_lower_pipes                : 1;
++          unsigned int row_size                       : 2;
++          unsigned int                                : 2;
++          unsigned int multi_gpu_tile_size            : 2;
++          unsigned int                                : 1;
++          unsigned int num_gpus                       : 3;
++          unsigned int                                : 1;
++          unsigned int shader_engine_tile_size        : 3;
++          unsigned int                                : 2;
++          unsigned int num_shader_engines             : 2;
++          unsigned int                                : 1;
++          unsigned int bank_interleave_size           : 3;
++          unsigned int                                : 1;
++          unsigned int pipe_interleave_size           : 3;
++          unsigned int                                : 1;
++          unsigned int num_pipes                      : 3;
++     } GB_ADDR_CONFIG_T;
++
++#endif
++
++typedef union {
++     unsigned int val : 32;
++     GB_ADDR_CONFIG_T f;
++} GB_ADDR_CONFIG;
++
++#if       defined(LITTLEENDIAN_CPU)
++
++     typedef struct _GB_TILE_MODE_T {
++          unsigned int micro_tile_mode                : 2;
++          unsigned int array_mode                     : 4;
++          unsigned int pipe_config                    : 5;
++          unsigned int tile_split                     : 3;
++          unsigned int bank_width                     : 2;
++          unsigned int bank_height                    : 2;
++          unsigned int macro_tile_aspect              : 2;
++          unsigned int num_banks                      : 2;
++          unsigned int micro_tile_mode_new            : 3;
++          unsigned int sample_split                   : 2;
++          unsigned int                                : 5;
++     } GB_TILE_MODE_T;
++
++     typedef struct _GB_MACROTILE_MODE_T {
++          unsigned int bank_width                     : 2;
++          unsigned int bank_height                    : 2;
++          unsigned int macro_tile_aspect              : 2;
++          unsigned int num_banks                      : 2;
++          unsigned int                                : 24;
++     } GB_MACROTILE_MODE_T;
++
++#elif          defined(BIGENDIAN_CPU)
++
++     typedef struct _GB_TILE_MODE_T {
++          unsigned int                                : 5;
++          unsigned int sample_split                   : 2;
++          unsigned int micro_tile_mode_new            : 3;
++          unsigned int num_banks                      : 2;
++          unsigned int macro_tile_aspect              : 2;
++          unsigned int bank_height                    : 2;
++          unsigned int bank_width                     : 2;
++          unsigned int tile_split                     : 3;
++          unsigned int pipe_config                    : 5;
++          unsigned int array_mode                     : 4;
++          unsigned int micro_tile_mode                : 2;
++     } GB_TILE_MODE_T;
++
++     typedef struct _GB_MACROTILE_MODE_T {
++          unsigned int                                : 24;
++          unsigned int num_banks                      : 2;
++          unsigned int macro_tile_aspect              : 2;
++          unsigned int bank_height                    : 2;
++          unsigned int bank_width                     : 2;
++     } GB_MACROTILE_MODE_T;
++
++#endif
++
++typedef union {
++     unsigned int val : 32;
++     GB_TILE_MODE_T f;
++} GB_TILE_MODE;
++
++typedef union {
++     unsigned int val : 32;
++     GB_MACROTILE_MODE_T f;
++} GB_MACROTILE_MODE;
++
++#endif
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/inc/lnx_common_defs.h b/src/gallium/winsys/radeon/amdgpu/addrlib/inc/lnx_common_defs.h
+new file mode 100644
+index 0000000..61540f4
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/inc/lnx_common_defs.h
+@@ -0,0 +1,129 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++#ifndef _lnx_common_defs_h_
++#define _lnx_common_defs_h_
++
++#if DBG
++#include <stdarg.h>                         // We do not have any choice: need variable
++                                            // number of parameters support for debug
++                                            // build.
++#endif                                      // #if DBG
++
++//
++// --------------  External functions from Linux kernel driver ----------------
++//
++// Note: The definitions/declararions below must match the original ones.
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++typedef unsigned long __ke_size_t;              // as it is defined in firegl_public.h
++typedef int           __kernel_ptrdiff_t;       // as it is defined in posix_types.h
++
++
++#if !defined(ATI_API_CALL)
++#define ATI_API_CALL __attribute__((regparm(0)))
++#endif
++
++extern void * ATI_API_CALL __ke_memset(void* s, int c, __ke_size_t count);
++extern void * ATI_API_CALL __ke_memcpy(void* d, const void* s, __ke_size_t count);
++extern ATI_API_CALL __ke_size_t __ke_strlen(const char *s);
++extern char* ATI_API_CALL __ke_strcpy(char* d, const char* s);
++extern char* ATI_API_CALL __ke_strncpy(char* d, const char* s, __ke_size_t count);
++extern void __ke_printk(const char* fmt, ...);
++
++extern int ATI_API_CALL __ke_snprintf(char* buf, __ke_size_t size, const char* fmt, ...);
++extern int ATI_API_CALL KCL_CopyFromUserSpace(void* to, const void* from, __ke_size_t size);
++extern int ATI_API_CALL KCL_CopyToUserSpace(void* to, const void* from, __ke_size_t size);
++#define __ke_copy_from_user  KCL_CopyFromUserSpace
++#define __ke_copy_to_user    KCL_CopyToUserSpace
++extern int ATI_API_CALL __ke_verify_area(int type, const void * addr, unsigned long size);
++
++extern unsigned long ATI_API_CALL KAS_GetTickCounter(void);
++extern unsigned long ATI_API_CALL KAS_GetTicksPerSecond(void);
++
++
++#if DBG
++extern int ATI_API_CALL __ke_vsnprintf(char *buf, __ke_size_t size, const char *fmt, va_list ap);
++#define vsnprintf(_dst, _size, _fmt, varg)  __ke_snprintf(_dst, _size, _fmt, varg)
++#endif                                      // #if DBG
++
++
++// Note: This function is not defined in firegl_public.h.
++void    firegl_hardwareHangRecovery(void);
++
++#ifdef __cplusplus
++}
++#endif
++
++//
++// --------------------------  C/C++ standard typedefs ----------------------------
++//
++#ifdef __SIZE_TYPE__
++typedef __SIZE_TYPE__       size_t;
++#else                                       // #ifdef __SIZE_TYPE__
++typedef unsigned int        size_t;
++#endif                                      // #ifdef __SIZE_TYPE__
++
++#ifdef __PTRDIFF_TYPE__
++typedef __PTRDIFF_TYPE__    ptrdiff_t;
++#else                                       // #ifdef __PTRDIFF_TYPE__
++typedef int                 ptrdiff_t;
++#endif                                      // #ifdef __PTRDIFF_TYPE__
++
++#ifndef NULL
++#ifdef __cplusplus
++#define NULL    __null
++#else
++#define NULL    ((void *)0)
++#endif
++#endif
++
++
++//
++// -------------------------  C/C++ standard macros ---------------------------
++//
++
++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)  // as it is defined in stddef.h
++#define CHAR_BIT            8                                   // as it is defined in limits.h
++
++//
++// ---------------------------------  C RTL -----------------------------------
++//
++
++#define memset(_p, _v, _n)                  __ke_memset(_p, _v, _n)
++#define memcpy(_d, _s, _n)                  __ke_memcpy(_d, _s, _n)
++#define strlen(_s)                          __ke_strlen(_s)
++#define strcpy(_d, _s)                      __ke_strcpy(_d, _s)
++#define strncpy(_d, _s, _n)                 __ke_strncpy(_d, _s, _n)
++// Note: C99 supports macros with variable number of arguments. GCC also supports this C99 feature as
++//       C++ extension.
++#define snprintf(_dst, _size, _fmt, arg...) __ke_snprintf(_dst, _size, _fmt, ##arg)
++
++
++#endif                                      // #ifdef _lnx_common_defs_h_
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/chip/si_ci_vi_merged_enum.h b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/chip/si_ci_vi_merged_enum.h
+new file mode 100644
+index 0000000..5ed81ad
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/chip/si_ci_vi_merged_enum.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++#if !defined (SI_CI_VI_MERGED_ENUM_HEADER)
++#define SI_CI_VI_MERGED_ENUM_HEADER
++
++typedef enum PipeInterleaveSize {
++ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
++ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
++} PipeInterleaveSize;
++
++typedef enum RowSize {
++ADDR_CONFIG_1KB_ROW                      = 0x00000000,
++ADDR_CONFIG_2KB_ROW                      = 0x00000001,
++ADDR_CONFIG_4KB_ROW                      = 0x00000002,
++} RowSize;
++
++#endif
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.cpp
+new file mode 100644
+index 0000000..264e2ef
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.cpp
+@@ -0,0 +1,1777 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  ciaddrlib.cpp
++* @brief Contains the implementation for the CIAddrLib class.
++***************************************************************************************************
++*/
++
++#include "ciaddrlib.h"
++
++#include "si_gb_reg.h"
++
++#include "si_ci_vi_merged_enum.h"
++
++#if BRAHMA_BUILD
++#include "amdgpu_id.h"
++#else
++#include "ci_id.h"
++#include "kv_id.h"
++#include "vi_id.h"
++#endif
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrMask
++*
++*   @brief
++*       Gets a mask of "width"
++*   @return
++*       Bit mask
++***************************************************************************************************
++*/
++static UINT_64 AddrMask(
++    UINT_32 width)  ///< Width of bits
++{
++    UINT_64 ret;
++
++    if (width >= sizeof(UINT_64)*8)
++    {
++        ret = ~((UINT_64) 0);
++    }
++    else
++    {
++        return (((UINT_64) 1) << width) - 1;
++    }
++    return ret;
++}
++
++/**
++***************************************************************************************************
++*   AddrGetBits
++*
++*   @brief
++*       Gets bits within a range of [msb, lsb]
++*   @return
++*       Bits of this range
++***************************************************************************************************
++*/
++static UINT_64 AddrGetBits(
++    UINT_64 bits,   ///< Source bits
++    UINT_32 msb,    ///< Most signicant bit
++    UINT_32 lsb)    ///< Least signicant bit
++{
++    UINT_64 ret = 0;
++
++    if (msb >= lsb)
++    {
++        ret = (bits >> lsb) & (AddrMask(1 + msb - lsb));
++    }
++    return ret;
++}
++
++/**
++***************************************************************************************************
++*   AddrRemoveBits
++*
++*   @brief
++*       Removes bits within the range of [msb, lsb]
++*   @return
++*       Modified bits
++***************************************************************************************************
++*/
++static UINT_64 AddrRemoveBits(
++    UINT_64 bits,   ///< Source bits
++    UINT_32 msb,    ///< Most signicant bit
++    UINT_32 lsb)    ///< Least signicant bit
++{
++    UINT_64 ret = bits;
++
++    if (msb >= lsb)
++    {
++        ret = AddrGetBits(bits, lsb - 1, 0) // low bits
++            | (AddrGetBits(bits, 8 * sizeof(bits) - 1, msb + 1) << lsb); //high bits
++    }
++    return ret;
++}
++
++/**
++***************************************************************************************************
++*   AddrInsertBits
++*
++*   @brief
++*       Inserts new bits into the range of [msb, lsb]
++*   @return
++*       Modified bits
++***************************************************************************************************
++*/
++static UINT_64 AddrInsertBits(
++    UINT_64 bits,       ///< Source bits
++    UINT_64 newBits,    ///< New bits to be inserted
++    UINT_32 msb,        ///< Most signicant bit
++    UINT_32 lsb)        ///< Least signicant bit
++{
++    UINT_64 ret = bits;
++
++    if (msb >= lsb)
++    {
++        ret = AddrGetBits(bits, lsb - 1, 0) // old low bitss
++             | (AddrGetBits(newBits, msb - lsb, 0) << lsb) //new bits
++             | (AddrGetBits(bits, 8 * sizeof(bits) - 1, lsb) << (msb + 1)); //old high bits
++    }
++    return ret;
++}
++
++
++/**
++***************************************************************************************************
++*   AddrCIHwlInit
++*
++*   @brief
++*       Creates an CIAddrLib object.
++*
++*   @return
++*       Returns an CIAddrLib object pointer.
++***************************************************************************************************
++*/
++AddrLib* AddrCIHwlInit(const AddrClient* pClient)
++{
++    return CIAddrLib::CreateObj(pClient);
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::CIAddrLib
++*
++*   @brief
++*       Constructor
++*
++***************************************************************************************************
++*/
++CIAddrLib::CIAddrLib(const AddrClient* pClient) :
++    SIAddrLib(pClient),
++    m_noOfMacroEntries(0),
++    m_allowNonDispThickModes(FALSE)
++{
++    m_class = CI_ADDRLIB;
++    memset(&m_settings, 0, sizeof(m_settings));
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::~CIAddrLib
++*
++*   @brief
++*       Destructor
++***************************************************************************************************
++*/
++CIAddrLib::~CIAddrLib()
++{
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlComputeDccInfo
++*
++*   @brief
++*       Compute DCC key size, base alignment
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE CIAddrLib::HwlComputeDccInfo(
++    const ADDR_COMPUTE_DCCINFO_INPUT*  pIn,
++    ADDR_COMPUTE_DCCINFO_OUTPUT*       pOut) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    if (m_settings.isVolcanicIslands && IsMacroTiled(pIn->tileMode))
++    {
++        UINT_64 dccFastClearSize = pIn->colorSurfSize >> 8;
++
++        ADDR_ASSERT(0 == (pIn->colorSurfSize & 0xff));
++
++        if (pIn->numSamples > 1)
++        {
++            UINT_32 tileSizePerSample = BITS_TO_BYTES(pIn->bpp * MicroTileWidth * MicroTileHeight);
++            UINT_32 samplesPerSplit  = pIn->tileInfo.tileSplitBytes / tileSizePerSample;
++
++            if (samplesPerSplit < pIn->numSamples)
++            {
++                UINT_32 numSplits = pIn->numSamples / samplesPerSplit;
++                UINT_32 fastClearBaseAlign = HwlGetPipes(&pIn->tileInfo) * m_pipeInterleaveBytes;
++
++                ADDR_ASSERT(IsPow2(fastClearBaseAlign));
++
++                dccFastClearSize /= numSplits;
++
++                if (0 != (dccFastClearSize & (fastClearBaseAlign - 1)))
++                {
++                    // Disable dcc fast clear
++                    // if key size of fisrt sample split is not pipe*interleave aligned
++                    dccFastClearSize = 0;
++                }
++            }
++        }
++
++        pOut->dccRamSize          = pIn->colorSurfSize >> 8;
++        pOut->dccRamBaseAlign     = pIn->tileInfo.banks *
++                                    HwlGetPipes(&pIn->tileInfo) *
++                                    m_pipeInterleaveBytes;
++        pOut->dccFastClearSize    = dccFastClearSize;
++
++        ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
++
++        if (0 == (pOut->dccRamSize & (pOut->dccRamBaseAlign - 1)))
++        {
++            pOut->subLvlCompressible = TRUE;
++        }
++        else
++        {
++            UINT_64 dccRamSizeAlign = HwlGetPipes(&pIn->tileInfo) * m_pipeInterleaveBytes;
++
++            if (pOut->dccRamSize == pOut->dccFastClearSize)
++            {
++                pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
++            }
++            pOut->dccRamSize          = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
++            pOut->subLvlCompressible  = FALSE;
++        }
++    }
++    else
++    {
++        returnCode = ADDR_NOTSUPPORTED;
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlComputeCmaskAddrFromCoord
++*
++*   @brief
++*       Compute tc compatible Cmask address from fmask ram address
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE CIAddrLib::HwlComputeCmaskAddrFromCoord(
++    const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*  pIn,  ///< [in] fmask addr/bpp/tile input
++    ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*       pOut  ///< [out] cmask address
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED;
++
++    if ((m_settings.isVolcanicIslands == TRUE) &&
++        (pIn->flags.tcCompatible == TRUE))
++    {
++        UINT_32 numOfPipes   = HwlGetPipes(pIn->pTileInfo);
++        UINT_32 numOfBanks   = pIn->pTileInfo->banks;
++        UINT_64 fmaskAddress = pIn->fmaskAddr;
++        UINT_32 elemBits     = pIn->bpp;
++        UINT_32 blockByte    = 64 * elemBits / 8;
++        UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(fmaskAddress,
++                                                                    0,
++                                                                    0,
++                                                                    4,
++                                                                    elemBits,
++                                                                    blockByte,
++                                                                    m_pipeInterleaveBytes,
++                                                                    numOfPipes,
++                                                                    numOfBanks,
++                                                                    1);
++        pOut->addr = (metaNibbleAddress >> 1);
++        pOut->bitPosition = (metaNibbleAddress % 2) ? 4 : 0;
++        returnCode = ADDR_OK;
++    }
++
++    return returnCode;
++}
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlConvertChipFamily
++*
++*   @brief
++*       Convert familyID defined in atiid.h to AddrChipFamily and set m_chipFamily/m_chipRevision
++*   @return
++*       AddrChipFamily
++***************************************************************************************************
++*/
++AddrChipFamily CIAddrLib::HwlConvertChipFamily(
++    UINT_32 uChipFamily,        ///< [in] chip family defined in atiih.h
++    UINT_32 uChipRevision)      ///< [in] chip revision defined in "asic_family"_id.h
++{
++    AddrChipFamily family = ADDR_CHIP_FAMILY_CI;
++
++    switch (uChipFamily)
++    {
++        case FAMILY_CI:
++            m_settings.isSeaIsland  = 1;
++            m_settings.isBonaire    = ASICREV_IS_BONAIRE_M(uChipRevision);
++            m_settings.isHawaii     = ASICREV_IS_HAWAII_P(uChipRevision);
++            break;
++        case FAMILY_KV:
++            m_settings.isKaveri     = 1;
++            m_settings.isSpectre    = ASICREV_IS_SPECTRE(uChipRevision);
++            m_settings.isSpooky     = ASICREV_IS_SPOOKY(uChipRevision);
++            m_settings.isKalindi    = ASICREV_IS_KALINDI(uChipRevision);
++            break;
++        case FAMILY_VI:
++            m_settings.isVolcanicIslands = 1;
++            m_settings.isIceland         = ASICREV_IS_ICELAND_M(uChipRevision);
++            m_settings.isTonga           = ASICREV_IS_TONGA_P(uChipRevision);
++            break;
++        case FAMILY_CZ:
++            m_settings.isCarrizo         = 1;
++            m_settings.isVolcanicIslands = 1;
++            break;
++        default:
++            ADDR_ASSERT(!"This should be a unexpected Fusion");
++            break;
++    }
++
++    return family;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlInitGlobalParams
++*
++*   @brief
++*       Initializes global parameters
++*
++*   @return
++*       TRUE if all settings are valid
++*
++***************************************************************************************************
++*/
++BOOL_32 CIAddrLib::HwlInitGlobalParams(
++    const ADDR_CREATE_INPUT* pCreateIn) ///< [in] create input
++{
++    BOOL_32  valid = TRUE;
++
++    const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue;
++
++    valid = DecodeGbRegs(pRegValue);
++
++    // The following assignments for m_pipes is only for fail-safe, InitTileSettingTable should
++    // read the correct pipes from tile mode table
++    if (m_settings.isHawaii)
++    {
++        // Hawaii has 16-pipe, see GFXIP_Config_Summary.xls
++        m_pipes = 16;
++    }
++    else if (m_settings.isBonaire || m_settings.isSpectre)
++    {
++        m_pipes = 4;
++    }
++    else // Treat other KV asics to be 2-pipe
++    {
++        m_pipes = 2;
++    }
++
++    // @todo: VI
++    // Move this to VI code path once created
++    if (m_settings.isTonga)
++    {
++        m_pipes = 8;
++    }
++    else if (m_settings.isIceland)
++    {
++        m_pipes = 2;
++    }
++
++    if (valid)
++    {
++        valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries);
++    }
++    if (valid)
++    {
++        valid = InitMacroTileCfgTable(pRegValue->pMacroTileConfig, pRegValue->noOfMacroEntries);
++    }
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlPostCheckTileIndex
++*
++*   @brief
++*       Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
++*       tile mode/type/info and change the index if needed
++*   @return
++*       Tile index.
++***************************************************************************************************
++*/
++INT_32 CIAddrLib::HwlPostCheckTileIndex(
++    const ADDR_TILEINFO* pInfo,     ///< [in] Tile Info
++    AddrTileMode         mode,      ///< [in] Tile mode
++    AddrTileType         type,      ///< [in] Tile type
++    INT                  curIndex   ///< [in] Current index assigned in HwlSetupTileInfo
++    ) const
++{
++    INT_32 index = curIndex;
++
++    if (mode == ADDR_TM_LINEAR_GENERAL)
++    {
++        index = TileIndexLinearGeneral;
++    }
++    else
++    {
++        BOOL_32 macroTiled = IsMacroTiled(mode);
++
++        // We need to find a new index if either of them is true
++        // 1. curIndex is invalid
++        // 2. tile mode is changed
++        // 3. tile info does not match for macro tiled
++        if ((index == TileIndexInvalid)         ||
++            (mode != m_tileTable[index].mode)   ||
++            (macroTiled && pInfo->pipeConfig != m_tileTable[index].info.pipeConfig))
++        {
++            for (index = 0; index < static_cast<INT_32>(m_noOfEntries); index++)
++            {
++                if (macroTiled)
++                {
++                    // macro tile modes need all to match
++                    if ((pInfo->pipeConfig == m_tileTable[index].info.pipeConfig) &&
++                        (mode == m_tileTable[index].mode) &&
++                        (type == m_tileTable[index].type))
++                    {
++                        // tileSplitBytes stored in m_tileTable is only valid for depth entries
++                        if (type == ADDR_DEPTH_SAMPLE_ORDER)
++                        {
++                            if (pInfo->tileSplitBytes == m_tileTable[index].info.tileSplitBytes)
++                            {
++                                break;
++                            }
++                        }
++                        else // other entries are determined by other 3 fields
++                        {
++                            break;
++                        }
++                    }
++                }
++                else if (mode == ADDR_TM_LINEAR_ALIGNED)
++                {
++                    // linear mode only needs tile mode to match
++                    if (mode == m_tileTable[index].mode)
++                    {
++                        break;
++                    }
++                }
++                else
++                {
++                    // micro tile modes only need tile mode and tile type to match
++                    if (mode == m_tileTable[index].mode &&
++                        type == m_tileTable[index].type)
++                    {
++                        break;
++                    }
++                }
++            }
++        }
++    }
++
++    ADDR_ASSERT(index < static_cast<INT_32>(m_noOfEntries));
++
++    if (index >= static_cast<INT_32>(m_noOfEntries))
++    {
++        index = TileIndexInvalid;
++    }
++
++    return index;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlSetupTileCfg
++*
++*   @brief
++*       Map tile index to tile setting.
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE CIAddrLib::HwlSetupTileCfg(
++    INT_32          index,          ///< [in] Tile index
++    INT_32          macroModeIndex, ///< [in] Index in macro tile mode table(CI)
++    ADDR_TILEINFO*  pInfo,          ///< [out] Tile Info
++    AddrTileMode*   pMode,          ///< [out] Tile mode
++    AddrTileType*   pType           ///< [out] Tile type
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    // Global flag to control usage of tileIndex
++    if (UseTileIndex(index))
++    {
++        if (static_cast<UINT_32>(index) >= m_noOfEntries)
++        {
++            returnCode = ADDR_INVALIDPARAMS;
++        }
++        else
++        {
++            const ADDR_TILECONFIG* pCfgTable = GetTileSetting(index);
++
++            if (pInfo != NULL)
++            {
++                if (IsMacroTiled(pCfgTable->mode))
++                {
++                    ADDR_ASSERT(((macroModeIndex != TileIndexInvalid)
++                        && (macroModeIndex != TileIndexNoMacroIndex)));
++                    // Here we used tile_bytes to replace of tile_split
++                    // According info as below:
++                    // "tile_split_c = MIN(ROW_SIZE, tile_split)
++                    // "tile_bytes = MIN(tile_split_c, num_samples * tile_bytes_1x)
++                    // when using tile_bytes replacing of tile_split, the result of
++                    // alignment and others(such as slicesPerTile) are unaffected -
++                    // since if tile_split_c is larger, split won't happen, otherwise
++                    // (num_samples * tile_bytes_1x is larger), a correct tile_split is
++                    // returned.
++                    *pInfo = m_macroTileTable[macroModeIndex];
++
++                    if (pCfgTable->type == ADDR_DEPTH_SAMPLE_ORDER)
++                    {
++                        pInfo->tileSplitBytes = pCfgTable->info.tileSplitBytes;
++                    }
++                    pInfo->pipeConfig = pCfgTable->info.pipeConfig;
++                }
++                else // 1D and linear modes, we return default value stored in table
++                {
++                    *pInfo = pCfgTable->info;
++                }
++            }
++
++            if (pMode != NULL)
++            {
++                *pMode = pCfgTable->mode;
++            }
++
++            if (pType != NULL)
++            {
++                *pType = pCfgTable->type;
++            }
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlComputeSurfaceInfo
++*
++*   @brief
++*       Entry of ci's ComputeSurfaceInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE CIAddrLib::HwlComputeSurfaceInfo(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    // If tileIndex is invalid, force macroModeIndex to be invalid, too
++    if (pIn->tileIndex == TileIndexInvalid)
++    {
++        pOut->macroModeIndex = TileIndexInvalid;
++    }
++
++    ADDR_E_RETURNCODE retCode = SIAddrLib::HwlComputeSurfaceInfo(pIn,pOut);
++
++    if (pOut->macroModeIndex == TileIndexNoMacroIndex)
++    {
++        pOut->macroModeIndex = TileIndexInvalid;
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlFmaskSurfaceInfo
++*   @brief
++*       Entry of r800's ComputeFmaskInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE CIAddrLib::HwlComputeFmaskInfo(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,   ///< [in] input structure
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut   ///< [out] output structure
++    )
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    ADDR_TILEINFO tileInfo = {0};
++    ADDR_COMPUTE_FMASK_INFO_INPUT fmaskIn;
++    fmaskIn = *pIn;
++
++    AddrTileMode tileMode = pIn->tileMode;
++
++    // Use internal tile info if pOut does not have a valid pTileInfo
++    if (pOut->pTileInfo == NULL)
++    {
++        pOut->pTileInfo = &tileInfo;
++    }
++
++    ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1     ||
++                tileMode == ADDR_TM_3D_TILED_THIN1     ||
++                tileMode == ADDR_TM_PRT_TILED_THIN1    ||
++                tileMode == ADDR_TM_PRT_2D_TILED_THIN1 ||
++                tileMode == ADDR_TM_PRT_3D_TILED_THIN1);
++
++    ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1);
++    ADDR_ASSERT(m_tileTable[15].mode == ADDR_TM_3D_TILED_THIN1);
++
++    // The only valid tile modes for fmask are 2D_THIN1 and 3D_THIN1 plus non-displayable
++    INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15;
++    ADDR_SURFACE_FLAGS flags = {{0}};
++    flags.fmask = 1;
++
++    INT_32 macroModeIndex = TileIndexInvalid;
++
++    UINT_32 numSamples = pIn->numSamples;
++    UINT_32 numFrags = pIn->numFrags == 0 ? numSamples : pIn->numFrags;
++
++    UINT_32 bpp = QLog2(numFrags);
++
++    // EQAA needs one more bit
++    if (numSamples > numFrags)
++    {
++        bpp++;
++    }
++
++    if (bpp == 3)
++    {
++        bpp = 4;
++    }
++
++    bpp = Max(8u, bpp * numSamples);
++
++    macroModeIndex = HwlComputeMacroModeIndex(tileIndex, flags, bpp, numSamples, pOut->pTileInfo);
++
++    fmaskIn.tileIndex = tileIndex;
++    fmaskIn.pTileInfo = pOut->pTileInfo;
++    pOut->macroModeIndex = macroModeIndex;
++    pOut->tileIndex = tileIndex;
++
++    retCode = DispatchComputeFmaskInfo(&fmaskIn, pOut);
++
++    if (retCode == ADDR_OK)
++    {
++        pOut->tileIndex =
++            HwlPostCheckTileIndex(pOut->pTileInfo, pIn->tileMode, ADDR_NON_DISPLAYABLE,
++                                  pOut->tileIndex);
++    }
++
++    // Resets pTileInfo to NULL if the internal tile info is used
++    if (pOut->pTileInfo == &tileInfo)
++    {
++        pOut->pTileInfo = NULL;
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlFmaskPreThunkSurfInfo
++*
++*   @brief
++*       Some preparation before thunking a ComputeSurfaceInfo call for Fmask
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++VOID CIAddrLib::HwlFmaskPreThunkSurfInfo(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pFmaskIn,   ///< [in] Input of fmask info
++    const ADDR_COMPUTE_FMASK_INFO_OUTPUT*   pFmaskOut,  ///< [in] Output of fmask info
++    ADDR_COMPUTE_SURFACE_INFO_INPUT*        pSurfIn,    ///< [out] Input of thunked surface info
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pSurfOut    ///< [out] Output of thunked surface info
++    ) const
++{
++    pSurfIn->tileIndex = pFmaskIn->tileIndex;
++    pSurfOut->macroModeIndex  = pFmaskOut->macroModeIndex;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlFmaskPostThunkSurfInfo
++*
++*   @brief
++*       Copy hwl extra field after calling thunked ComputeSurfaceInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++VOID CIAddrLib::HwlFmaskPostThunkSurfInfo(
++    const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,   ///< [in] Output of surface info
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut           ///< [out] Output of fmask info
++    ) const
++{
++    pFmaskOut->tileIndex = pSurfOut->tileIndex;
++    pFmaskOut->macroModeIndex = pSurfOut->macroModeIndex;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlDegradeThickTileMode
++*
++*   @brief
++*       Degrades valid tile mode for thick modes if needed
++*
++*   @return
++*       Suitable tile mode
++***************************************************************************************************
++*/
++AddrTileMode CIAddrLib::HwlDegradeThickTileMode(
++    AddrTileMode        baseTileMode,   ///< [in] base tile mode
++    UINT_32             numSlices,      ///< [in] current number of slices
++    UINT_32*            pBytesPerTile   ///< [in/out] pointer to bytes per slice
++    ) const
++{
++    return baseTileMode;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlOverrideTileMode
++*
++*   @brief
++*       Override THICK to THIN, for specific formats on CI
++*
++*   @return
++*       Suitable tile mode
++*
++***************************************************************************************************
++*/
++BOOL_32 CIAddrLib::HwlOverrideTileMode(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,       ///< [in] input structure
++    AddrTileMode*                           pTileMode, ///< [in/out] pointer to the tile mode
++    AddrTileType*                           pTileType  ///< [in/out] pointer to the tile type
++    ) const
++{
++    BOOL_32 bOverrided = FALSE;
++    AddrTileMode tileMode = *pTileMode;
++
++    // currently, all CI/VI family do not
++    // support ADDR_TM_PRT_2D_TILED_THICK,ADDR_TM_PRT_3D_TILED_THICK and
++    // ADDR_TM_PRT_2D_TILED_THIN1, ADDR_TM_PRT_3D_TILED_THIN1
++    switch (tileMode)
++    {
++        case ADDR_TM_PRT_2D_TILED_THICK:
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            tileMode = ADDR_TM_PRT_TILED_THICK;
++            break;
++        case ADDR_TM_PRT_2D_TILED_THIN1:
++        case ADDR_TM_PRT_3D_TILED_THIN1:
++            tileMode = ADDR_TM_PRT_TILED_THIN1;
++            break;
++        default:
++            break;
++    }
++
++    // UBTS#404321, we do not need such overriding, as THICK+THICK entries removed from the tile-mode table
++    if (!m_settings.isBonaire)
++    {
++        UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++        // tile_thickness = (array_mode == XTHICK) ? 8 : ((array_mode == THICK) ? 4 : 1)
++        if (thickness > 1)
++        {
++            switch (pIn->format)
++            {
++                // see //gfxip/gcB/devel/cds/src/verif/tc/models/csim/tcp.cpp
++                // tcpError("Thick micro tiling is not supported for format...
++                case ADDR_FMT_X24_8_32_FLOAT:
++                case ADDR_FMT_32_AS_8:
++                case ADDR_FMT_32_AS_8_8:
++                case ADDR_FMT_32_AS_32_32_32_32:
++
++                // packed formats
++                case ADDR_FMT_GB_GR:
++                case ADDR_FMT_BG_RG:
++                case ADDR_FMT_1_REVERSED:
++                case ADDR_FMT_1:
++                case ADDR_FMT_BC1:
++                case ADDR_FMT_BC2:
++                case ADDR_FMT_BC3:
++                case ADDR_FMT_BC4:
++                case ADDR_FMT_BC5:
++                case ADDR_FMT_BC6:
++                case ADDR_FMT_BC7:
++                    switch (tileMode)
++                    {
++                        case ADDR_TM_1D_TILED_THICK:
++                            tileMode    = ADDR_TM_1D_TILED_THIN1;
++                            break;
++
++                        case ADDR_TM_2D_TILED_XTHICK:
++                        case ADDR_TM_2D_TILED_THICK:
++                            tileMode    = ADDR_TM_2D_TILED_THIN1;
++                            break;
++
++                        case ADDR_TM_3D_TILED_XTHICK:
++                        case ADDR_TM_3D_TILED_THICK:
++                            tileMode    = ADDR_TM_3D_TILED_THIN1;
++                            break;
++
++                        case ADDR_TM_PRT_TILED_THICK:
++                            tileMode    = ADDR_TM_PRT_TILED_THIN1;
++                            break;
++
++                        case ADDR_TM_PRT_2D_TILED_THICK:
++                            tileMode    = ADDR_TM_PRT_2D_TILED_THIN1;
++                            break;
++
++                        case ADDR_TM_PRT_3D_TILED_THICK:
++                            tileMode    = ADDR_TM_PRT_3D_TILED_THIN1;
++                            break;
++
++                        default:
++                            break;
++
++                    }
++
++                    // Switch tile type from thick to thin
++                    if (tileMode != *pTileMode)
++                    {
++                        // see tileIndex: 13-18
++                        *pTileType = ADDR_NON_DISPLAYABLE;
++                    }
++
++                    break;
++                default:
++                    break;
++            }
++        }
++    }
++
++    if (tileMode != *pTileMode)
++    {
++        *pTileMode = tileMode;
++        bOverrided = TRUE;
++    }
++
++    return bOverrided;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlSetupTileInfo
++*
++*   @brief
++*       Setup default value of tile info for SI
++***************************************************************************************************
++*/
++VOID CIAddrLib::HwlSetupTileInfo(
++    AddrTileMode                        tileMode,       ///< [in] Tile mode
++    ADDR_SURFACE_FLAGS                  flags,          ///< [in] Surface type flags
++    UINT_32                             bpp,            ///< [in] Bits per pixel
++    UINT_32                             pitch,          ///< [in] Pitch in pixels
++    UINT_32                             height,         ///< [in] Height in pixels
++    UINT_32                             numSamples,     ///< [in] Number of samples
++    ADDR_TILEINFO*                      pTileInfoIn,    ///< [in] Tile info input: NULL for default
++    ADDR_TILEINFO*                      pTileInfoOut,   ///< [out] Tile info output
++    AddrTileType                        inTileType,     ///< [in] Tile type
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*   pOut            ///< [out] Output
++    ) const
++{
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++    ADDR_TILEINFO* pTileInfo = pTileInfoOut;
++    INT index = TileIndexInvalid;
++    INT macroModeIndex = TileIndexInvalid;
++
++    // Fail-safe code
++    if (!IsLinear(tileMode))
++    {
++        // Thick tile modes must use thick micro tile mode but Bonaire does not support due to
++        // old derived netlists (UBTS 404321)
++        if (thickness > 1)
++        {
++            if (m_settings.isBonaire)
++            {
++                inTileType = ADDR_NON_DISPLAYABLE;
++            }
++            else if ((m_allowNonDispThickModes == FALSE) || (inTileType != ADDR_NON_DISPLAYABLE))
++            {
++                inTileType = ADDR_THICK;
++            }
++        }
++        // 128 bpp tiling must be non-displayable.
++        // Fmask reuse color buffer's entry but bank-height field can be from another entry
++        // To simplify the logic, fmask entry should be picked from non-displayable ones
++        else if (bpp == 128 || flags.fmask)
++        {
++            inTileType = ADDR_NON_DISPLAYABLE;
++        }
++        // These two modes only have non-disp entries though they can be other micro tile modes
++        else if (tileMode == ADDR_TM_3D_TILED_THIN1 || tileMode == ADDR_TM_PRT_3D_TILED_THIN1)
++        {
++            inTileType = ADDR_NON_DISPLAYABLE;
++        }
++
++        if (flags.depth || flags.stencil)
++        {
++            inTileType = ADDR_DEPTH_SAMPLE_ORDER;
++        }
++    }
++
++    if (IsTileInfoAllZero(pTileInfo))
++    {
++        // See table entries 0-4
++        if (flags.depth || flags.stencil)
++        {
++            if (flags.depth && flags.tcCompatible)
++            {
++                // tileSize = bpp * numSamples * 8 * 8 / 8
++                UINT_32 tileSize = bpp * numSamples * 8;
++
++                // Texure readable depth surface should not be split
++                switch (tileSize)
++                {
++                    case 128:
++                        index = 1;
++                        break;
++                    case 256:
++                        index = 2;
++                        break;
++                    case 512:
++                        index = 3;
++                        break;
++                    default:
++                        index = 4;
++                        break;
++                }
++            }
++            else
++            {
++                // Depth and stencil need to use the same index, thus the pre-defined tile_split
++                // can meet the requirement to choose the same macro mode index
++                // uncompressed depth/stencil are not supported for now
++                switch (numSamples)
++                {
++                    case 1:
++                        index = 0;
++                        break;
++                    case 2:
++                    case 4:
++                        index = 1;
++                        break;
++                    case 8:
++                        index = 2;
++                        break;
++                    default:
++                        break;
++                }
++            }
++        }
++
++        // See table entries 5-6
++        if (inTileType == ADDR_DEPTH_SAMPLE_ORDER)
++        {
++            switch (tileMode)
++            {
++                case ADDR_TM_1D_TILED_THIN1:
++                    index = 5;
++                    break;
++                case ADDR_TM_PRT_TILED_THIN1:
++                    index = 6;
++                    break;
++                default:
++                    break;
++            }
++        }
++
++        // See table entries 8-12
++        if (inTileType == ADDR_DISPLAYABLE)
++        {
++            switch (tileMode)
++            {
++                case ADDR_TM_1D_TILED_THIN1:
++                    index = 9;
++                    break;
++                case ADDR_TM_2D_TILED_THIN1:
++                    index = 10;
++                    break;
++                case ADDR_TM_PRT_TILED_THIN1:
++                    index = 11;
++                    break;
++                default:
++                    break;
++            }
++        }
++
++        // See table entries 13-18
++        if (inTileType == ADDR_NON_DISPLAYABLE)
++        {
++            switch (tileMode)
++            {
++                case ADDR_TM_1D_TILED_THIN1:
++                    index = 13;
++                    break;
++                case ADDR_TM_2D_TILED_THIN1:
++                    index = 14;
++                    break;
++                case ADDR_TM_3D_TILED_THIN1:
++                    index = 15;
++                    break;
++                case ADDR_TM_PRT_TILED_THIN1:
++                    index = 16;
++                    break;
++                default:
++                    break;
++            }
++        }
++
++        // See table entries 19-26
++        if (thickness > 1)
++        {
++            switch (tileMode)
++            {
++            case ADDR_TM_1D_TILED_THICK:
++                    //special check for bonaire, for the compatablity between old KMD and new UMD for bonaire
++                    index = ((inTileType == ADDR_THICK) || m_settings.isBonaire) ? 19 : 18;
++                    break;
++            case ADDR_TM_2D_TILED_THICK:
++                    // special check for bonaire, for the compatablity between old KMD and new UMD for bonaire
++                    index = ((inTileType == ADDR_THICK) || m_settings.isBonaire) ? 20 : 24;
++                    break;
++                case ADDR_TM_3D_TILED_THICK:
++                    index = 21;
++                    break;
++                case ADDR_TM_PRT_TILED_THICK:
++                    index = 22;
++                    break;
++                case ADDR_TM_2D_TILED_XTHICK:
++                    index = 25;
++                    break;
++                case ADDR_TM_3D_TILED_XTHICK:
++                    index = 26;
++                    break;
++                default:
++                    break;
++            }
++        }
++
++        // See table entries 27-30
++        if (inTileType == ADDR_ROTATED)
++        {
++            switch (tileMode)
++            {
++                case ADDR_TM_1D_TILED_THIN1:
++                    index = 27;
++                    break;
++                case ADDR_TM_2D_TILED_THIN1:
++                    index = 28;
++                    break;
++                case ADDR_TM_PRT_TILED_THIN1:
++                    index = 29;
++                    break;
++                case ADDR_TM_PRT_2D_TILED_THIN1:
++                    index = 30;
++                    break;
++                default:
++                    break;
++            }
++        }
++
++        if (m_pipes >= 8)
++        {
++            ADDR_ASSERT((index + 1) < static_cast<INT_32>(m_noOfEntries));
++            // Only do this when tile mode table is updated.
++            if (((tileMode == ADDR_TM_PRT_TILED_THIN1) || (tileMode == ADDR_TM_PRT_TILED_THICK)) &&
++                (m_tileTable[index+1].mode == tileMode))
++            {
++                UINT_32 bytesXSamples = bpp * numSamples / 8;
++                UINT_32 bytesXThickness = bpp * thickness / 8;
++                UINT_32 switchP4Threshold = (m_pipes == 16) ? 8 : 32;
++
++                if ((bytesXSamples > switchP4Threshold) || (bytesXThickness > switchP4Threshold))
++                {
++                    // Pick next 4 pipe entry
++                    index += 1;
++                }
++            }
++        }
++    }
++    else
++    {
++        // A pre-filled tile info is ready
++        index = pOut->tileIndex;
++        macroModeIndex = pOut->macroModeIndex;
++
++        // pass tile type back for post tile index compute
++        pOut->tileType = inTileType;
++    }
++
++    // We only need to set up tile info if there is a valid index but macroModeIndex is invalid
++    if (index != TileIndexInvalid && macroModeIndex == TileIndexInvalid)
++    {
++        macroModeIndex = HwlComputeMacroModeIndex(index, flags, bpp, numSamples, pTileInfo);
++
++        /// Copy to pOut->tileType/tileIndex/macroModeIndex
++        pOut->tileIndex = index;
++        pOut->tileType = m_tileTable[index].type; // Or inTileType, the samea
++        pOut->macroModeIndex = macroModeIndex;
++    }
++    else if (tileMode == ADDR_TM_LINEAR_GENERAL)
++    {
++        pOut->tileIndex = TileIndexLinearGeneral;
++
++        // Copy linear-aligned entry??
++        *pTileInfo = m_tileTable[8].info;
++    }
++    else if (tileMode == ADDR_TM_LINEAR_ALIGNED)
++    {
++        pOut->tileIndex = 8;
++        *pTileInfo = m_tileTable[8].info;
++    }
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::ReadGbTileMode
++*
++*   @brief
++*       Convert GB_TILE_MODE HW value to ADDR_TILE_CONFIG.
++*   @return
++*       NA.
++***************************************************************************************************
++*/
++VOID CIAddrLib::ReadGbTileMode(
++    UINT_32             regValue,   ///< [in] GB_TILE_MODE register
++    ADDR_TILECONFIG*    pCfg        ///< [out] output structure
++    ) const
++{
++    GB_TILE_MODE gbTileMode;
++    gbTileMode.val = regValue;
++
++    pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode_new);
++    pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
++
++    if (pCfg->type == ADDR_DEPTH_SAMPLE_ORDER)
++    {
++        pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
++    }
++    else
++    {
++        pCfg->info.tileSplitBytes = 1 << gbTileMode.f.sample_split;
++    }
++
++    UINT_32 regArrayMode = gbTileMode.f.array_mode;
++
++    pCfg->mode = static_cast<AddrTileMode>(regArrayMode);
++
++    switch (regArrayMode)
++    {
++        case 5:
++            pCfg->mode = ADDR_TM_PRT_TILED_THIN1;
++            break;
++        case 6:
++            pCfg->mode = ADDR_TM_PRT_2D_TILED_THIN1;
++            break;
++        case 8:
++            pCfg->mode = ADDR_TM_2D_TILED_XTHICK;
++            break;
++        case 9:
++            pCfg->mode = ADDR_TM_PRT_TILED_THICK;
++            break;
++        case 0xa:
++            pCfg->mode = ADDR_TM_PRT_2D_TILED_THICK;
++            break;
++        case 0xb:
++            pCfg->mode = ADDR_TM_PRT_3D_TILED_THIN1;
++            break;
++        case 0xe:
++            pCfg->mode = ADDR_TM_3D_TILED_XTHICK;
++            break;
++        case 0xf:
++            pCfg->mode = ADDR_TM_PRT_3D_TILED_THICK;
++            break;
++        default:
++            break;
++    }
++
++    // Fail-safe code for these always convert tile info, as the non-macro modes
++    // return the entry of tile mode table directly without looking up macro mode table
++    if (!IsMacroTiled(pCfg->mode))
++    {
++        pCfg->info.banks = 2;
++        pCfg->info.bankWidth = 1;
++        pCfg->info.bankHeight = 1;
++        pCfg->info.macroAspectRatio = 1;
++        pCfg->info.tileSplitBytes = 64;
++    }
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::InitTileSettingTable
++*
++*   @brief
++*       Initialize the ADDR_TILE_CONFIG table.
++*   @return
++*       TRUE if tile table is correctly initialized
++***************************************************************************************************
++*/
++BOOL_32 CIAddrLib::InitTileSettingTable(
++    const UINT_32*  pCfg,           ///< [in] Pointer to table of tile configs
++    UINT_32         noOfEntries     ///< [in] Numbe of entries in the table above
++    )
++{
++    BOOL_32 initOk = TRUE;
++
++    ADDR_ASSERT(noOfEntries <= TileTableSize);
++
++    memset(m_tileTable, 0, sizeof(m_tileTable));
++
++    if (noOfEntries != 0)
++    {
++        m_noOfEntries = noOfEntries;
++    }
++    else
++    {
++        m_noOfEntries = TileTableSize;
++    }
++
++    if (pCfg) // From Client
++    {
++        for (UINT_32 i = 0; i < m_noOfEntries; i++)
++        {
++            ReadGbTileMode(*(pCfg + i), &m_tileTable[i]);
++        }
++    }
++    else
++    {
++        ADDR_ASSERT_ALWAYS();
++        initOk = FALSE;
++    }
++
++    if (initOk)
++    {
++        ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED);
++
++        if (m_settings.isBonaire == FALSE)
++        {
++            // Check if entry 18 is "thick+thin" combination
++            if ((m_tileTable[18].mode == ADDR_TM_1D_TILED_THICK) &&
++                (m_tileTable[18].type == ADDR_NON_DISPLAYABLE))
++            {
++                m_allowNonDispThickModes = TRUE;
++                ADDR_ASSERT(m_tileTable[24].mode == ADDR_TM_2D_TILED_THICK);
++            }
++        }
++        else
++        {
++            m_allowNonDispThickModes = TRUE;
++        }
++
++        // Assume the first entry is always programmed with full pipes
++        m_pipes = HwlGetPipes(&m_tileTable[0].info);
++    }
++
++    return initOk;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::ReadGbMacroTileCfg
++*
++*   @brief
++*       Convert GB_MACRO_TILE_CFG HW value to ADDR_TILE_CONFIG.
++*   @return
++*       NA.
++***************************************************************************************************
++*/
++VOID CIAddrLib::ReadGbMacroTileCfg(
++    UINT_32             regValue,   ///< [in] GB_MACRO_TILE_MODE register
++    ADDR_TILEINFO*      pCfg        ///< [out] output structure
++    ) const
++{
++    GB_MACROTILE_MODE gbTileMode;
++    gbTileMode.val = regValue;
++
++    pCfg->bankHeight = 1 << gbTileMode.f.bank_height;
++    pCfg->bankWidth = 1 << gbTileMode.f.bank_width;
++    pCfg->banks = 1 << (gbTileMode.f.num_banks + 1);
++    pCfg->macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::InitMacroTileCfgTable
++*
++*   @brief
++*       Initialize the ADDR_MACRO_TILE_CONFIG table.
++*   @return
++*       TRUE if macro tile table is correctly initialized
++***************************************************************************************************
++*/
++BOOL_32 CIAddrLib::InitMacroTileCfgTable(
++    const UINT_32*  pCfg,           ///< [in] Pointer to table of tile configs
++    UINT_32         noOfMacroEntries     ///< [in] Numbe of entries in the table above
++    )
++{
++    BOOL_32 initOk = TRUE;
++
++    ADDR_ASSERT(noOfMacroEntries <= MacroTileTableSize);
++
++    memset(m_macroTileTable, 0, sizeof(m_macroTileTable));
++
++    if (noOfMacroEntries != 0)
++    {
++        m_noOfMacroEntries = noOfMacroEntries;
++    }
++    else
++    {
++        m_noOfMacroEntries = MacroTileTableSize;
++    }
++
++    if (pCfg) // From Client
++    {
++        for (UINT_32 i = 0; i < m_noOfMacroEntries; i++)
++        {
++            ReadGbMacroTileCfg(*(pCfg + i), &m_macroTileTable[i]);
++
++            m_macroTileTable[i].tileSplitBytes = 64 << (i % 8);
++        }
++    }
++    else
++    {
++        ADDR_ASSERT_ALWAYS();
++        initOk = FALSE;
++    }
++    return initOk;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlComputeMacroModeIndex
++*
++*   @brief
++*       Computes macro tile mode index
++*   @return
++*       TRUE if macro tile table is correctly initialized
++***************************************************************************************************
++*/
++INT_32 CIAddrLib::HwlComputeMacroModeIndex(
++    INT_32              tileIndex,      ///< [in] Tile mode index
++    ADDR_SURFACE_FLAGS  flags,          ///< [in] Surface flags
++    UINT_32             bpp,            ///< [in] Bit per pixel
++    UINT_32             numSamples,     ///< [in] Number of samples
++    ADDR_TILEINFO*      pTileInfo,      ///< [out] Pointer to ADDR_TILEINFO
++    AddrTileMode*       pTileMode,      ///< [out] Pointer to AddrTileMode
++    AddrTileType*       pTileType       ///< [out] Pointer to AddrTileType
++    ) const
++{
++    INT_32 macroModeIndex = TileIndexInvalid;
++
++    if (flags.tcCompatible && flags.stencil)
++    {
++        // Don't compute macroModeIndex for tc compatible stencil surface
++        macroModeIndex = TileIndexNoMacroIndex;
++    }
++    else
++    {
++        AddrTileMode tileMode = m_tileTable[tileIndex].mode;
++        AddrTileType tileType = m_tileTable[tileIndex].type;
++        UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++        if (!IsMacroTiled(tileMode))
++        {
++            *pTileInfo = m_tileTable[tileIndex].info;
++            macroModeIndex = TileIndexNoMacroIndex;
++        }
++        else
++        {
++            UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
++            UINT_32 tileSplit;
++
++            if (m_tileTable[tileIndex].type == ADDR_DEPTH_SAMPLE_ORDER)
++            {
++                // Depth entries store real tileSplitBytes
++                tileSplit = m_tileTable[tileIndex].info.tileSplitBytes;
++            }
++            else
++            {
++                // Non-depth entries store a split factor
++                UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
++                UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
++
++                tileSplit = colorTileSplit;
++            }
++
++            UINT_32 tileSplitC = Min(m_rowSize, tileSplit);
++            UINT_32 tileBytes;
++
++            if (flags.fmask)
++            {
++                tileBytes = Min(tileSplitC, tileBytes1x);
++            }
++            else
++            {
++                tileBytes = Min(tileSplitC, numSamples * tileBytes1x);
++            }
++
++            if (tileBytes < 64)
++            {
++                tileBytes = 64;
++            }
++
++            macroModeIndex = Log2(tileBytes / 64);
++
++            if (flags.prt || IsPrtTileMode(tileMode))
++            {
++                // Unknown - assume it is 1/2 of table size
++                const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
++
++                macroModeIndex += PrtMacroModeOffset;
++                *pTileInfo = m_macroTileTable[macroModeIndex];
++            }
++            else
++            {
++                *pTileInfo = m_macroTileTable[macroModeIndex];
++            }
++
++            pTileInfo->pipeConfig = m_tileTable[tileIndex].info.pipeConfig;
++
++            if (m_tileTable[tileIndex].type != ADDR_DEPTH_SAMPLE_ORDER)
++            {
++                pTileInfo->tileSplitBytes = tileSplitC;
++            }
++            else
++            {
++                pTileInfo->tileSplitBytes = m_tileTable[tileIndex].info.tileSplitBytes;
++            }
++        }
++
++        if (NULL != pTileMode)
++        {
++            *pTileMode = tileMode;
++        }
++
++        if (NULL != pTileType)
++        {
++            *pTileType = tileType;
++        }
++    }
++
++    return macroModeIndex;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlComputeTileDataWidthAndHeightLinear
++*
++*   @brief
++*       Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
++*
++*   @return
++*       N/A
++*
++*   @note
++*       MacroWidth and macroHeight are measured in pixels
++***************************************************************************************************
++*/
++VOID CIAddrLib::HwlComputeTileDataWidthAndHeightLinear(
++    UINT_32*        pMacroWidth,     ///< [out] macro tile width
++    UINT_32*        pMacroHeight,    ///< [out] macro tile height
++    UINT_32         bpp,             ///< [in] bits per pixel
++    ADDR_TILEINFO*  pTileInfo        ///< [in] tile info
++    ) const
++{
++    ADDR_ASSERT(pTileInfo != NULL);
++
++    UINT_32 numTiles;
++
++    switch (pTileInfo->pipeConfig)
++    {
++        case ADDR_PIPECFG_P16_32x32_8x16:
++        case ADDR_PIPECFG_P16_32x32_16x16:
++        case ADDR_PIPECFG_P8_32x64_32x32:
++        case ADDR_PIPECFG_P8_32x32_16x32:
++        case ADDR_PIPECFG_P8_32x32_16x16:
++        case ADDR_PIPECFG_P8_32x32_8x16:
++        case ADDR_PIPECFG_P4_32x32:
++            numTiles = 8;
++            break;
++        default:
++            numTiles = 4;
++            break;
++    }
++
++    *pMacroWidth    = numTiles * MicroTileWidth;
++    *pMacroHeight   = numTiles * MicroTileHeight;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlStereoCheckRightOffsetPadding
++*
++*   @brief
++*       check if the height needs extra padding for stereo right eye offset, to avoid swizzling
++*
++*   @return
++*       TRUE is the extra padding is needed
++*
++*   @note
++*       Kalindi (Kabini) is the only one that needs this padding as there is a uncertain
++*       possible HW issue where the right eye displays incorrectly with some type of swizzles, if
++*       the right eye offset is not 64KB aligned - EPR#366461
++*       Other Kaveri APUs also need the padding according to DXX team's report otherwise
++*       corruption observed. - EPR#374788
++***************************************************************************************************
++*/
++BOOL_32 CIAddrLib::HwlStereoCheckRightOffsetPadding() const
++{
++    BOOL_32 bNeedPadding = FALSE;
++
++    if (m_settings.isKaveri)
++    {
++        bNeedPadding = TRUE;
++    }
++
++    return bNeedPadding;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlComputeMetadataNibbleAddress
++*
++*   @brief
++*        calculate meta data address based on input information
++*
++*   &parameter
++*        uncompressedDataByteAddress - address of a pixel in color surface
++*        dataBaseByteAddress         - base address of color surface
++*        metadataBaseByteAddress     - base address of meta ram
++*        metadataBitSize             - meta key size, 8 for DCC, 4 for cmask
++*        elementBitSize              - element size of color surface
++*        blockByteSize               - compression block size, 256 for DCC
++*        pipeInterleaveBytes         - pipe interleave size
++*        numOfPipes                  - number of pipes
++*        numOfBanks                  - number of banks
++*        numOfSamplesPerSplit        - number of samples per tile split
++*   @return
++*        meta data nibble address (nibble address is used to support DCC compatible cmask)
++*
++***************************************************************************************************
++*/
++UINT_64 CIAddrLib::HwlComputeMetadataNibbleAddress(
++    UINT_64 uncompressedDataByteAddress,
++    UINT_64 dataBaseByteAddress,
++    UINT_64 metadataBaseByteAddress,
++    UINT_32 metadataBitSize,
++    UINT_32 elementBitSize,
++    UINT_32 blockByteSize,
++    UINT_32 pipeInterleaveBytes,
++    UINT_32 numOfPipes,
++    UINT_32 numOfBanks,
++    UINT_32 numOfSamplesPerSplit) const
++{
++    ///--------------------------------------------------------------------------------------------
++    /// Get pipe interleave, bank and pipe bits
++    ///--------------------------------------------------------------------------------------------
++    UINT_32 pipeInterleaveBits  = Log2(pipeInterleaveBytes);
++    UINT_32 pipeBits            = Log2(numOfPipes);
++    UINT_32 bankBits            = Log2(numOfBanks);
++
++    ///--------------------------------------------------------------------------------------------
++    /// Clear pipe and bank swizzles
++    ///--------------------------------------------------------------------------------------------
++    UINT_32 dataMacrotileBits        = pipeInterleaveBits + pipeBits + bankBits;
++    UINT_32 metadataMacrotileBits    = pipeInterleaveBits + pipeBits + bankBits;
++
++    UINT_64 dataMacrotileClearMask     = ~((1L << dataMacrotileBits) - 1);
++    UINT_64 metadataMacrotileClearMask = ~((1L << metadataMacrotileBits) - 1);
++
++    UINT_64 dataBaseByteAddressNoSwizzle = dataBaseByteAddress & dataMacrotileClearMask;
++    UINT_64 metadataBaseByteAddressNoSwizzle = metadataBaseByteAddress & metadataMacrotileClearMask;
++
++    ///--------------------------------------------------------------------------------------------
++    /// Modify metadata base before adding in so that when final address is divided by data ratio,
++    /// the base address returns to where it should be
++    ///--------------------------------------------------------------------------------------------
++    ADDR_ASSERT((0 != metadataBitSize));
++    UINT_64 metadataBaseShifted = metadataBaseByteAddressNoSwizzle * blockByteSize * 8 /
++                                  metadataBitSize;
++    UINT_64 offset = uncompressedDataByteAddress -
++                     dataBaseByteAddressNoSwizzle +
++                     metadataBaseShifted;
++
++    ///--------------------------------------------------------------------------------------------
++    /// Save bank data bits
++    ///--------------------------------------------------------------------------------------------
++    UINT_32 lsb = pipeBits + pipeInterleaveBits;
++    UINT_32 msb = bankBits - 1 + lsb;
++
++    UINT_64 bankDataBits = AddrGetBits(offset, msb, lsb);
++
++    ///--------------------------------------------------------------------------------------------
++    /// Save pipe data bits
++    ///--------------------------------------------------------------------------------------------
++    lsb = pipeInterleaveBits;
++    msb = pipeBits - 1 + lsb;
++
++    UINT_64 pipeDataBits = AddrGetBits(offset, msb, lsb);
++
++    ///--------------------------------------------------------------------------------------------
++    /// Remove pipe and bank bits
++    ///--------------------------------------------------------------------------------------------
++    lsb = pipeInterleaveBits;
++    msb = dataMacrotileBits - 1;
++
++    UINT_64 offsetWithoutPipeBankBits = AddrRemoveBits(offset, msb, lsb);
++
++    ADDR_ASSERT((0 != blockByteSize));
++    UINT_64 blockInBankpipe = offsetWithoutPipeBankBits / blockByteSize;
++
++    UINT_32 tileSize = 8 * 8 * elementBitSize/8 * numOfSamplesPerSplit;
++    UINT_32 blocksInTile = tileSize / blockByteSize;
++
++    if (0 == blocksInTile)
++    {
++        lsb = 0;
++    }
++    else
++    {
++        lsb = Log2(blocksInTile);
++    }
++    msb = bankBits - 1 + lsb;
++
++    UINT_64 blockInBankpipeWithBankBits = AddrInsertBits(blockInBankpipe, bankDataBits, msb, lsb);
++
++    /// NOTE *2 because we are converting to Nibble address in this step
++    UINT_64 metaAddressInPipe = blockInBankpipeWithBankBits * 2 * metadataBitSize / 8;
++
++
++    ///--------------------------------------------------------------------------------------------
++    /// Reinsert pipe bits back into the final address
++    ///--------------------------------------------------------------------------------------------
++    lsb = pipeInterleaveBits + 1; ///<+1 due to Nibble address now gives interleave bits extra lsb.
++    msb = pipeBits - 1 + lsb;
++    UINT_64 metadataAddress = AddrInsertBits(metaAddressInPipe, pipeDataBits, msb, lsb);
++
++    return metadataAddress;
++}
++
++/**
++***************************************************************************************************
++*   CIAddrLib::HwlPadDimensions
++*
++*   @brief
++*       Helper function to pad dimensions
++*
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID CIAddrLib::HwlPadDimensions(
++    AddrTileMode        tileMode,    ///< [in] tile mode
++    UINT_32             bpp,         ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,       ///< [in] surface flags
++    UINT_32             numSamples,  ///< [in] number of samples
++    ADDR_TILEINFO*      pTileInfo,   ///< [in/out] bank structure.
++    UINT_32             padDims,     ///< [in] Dimensions to pad valid value 1,2,3
++    UINT_32             mipLevel,    ///< [in] MipLevel
++    UINT_32*            pPitch,      ///< [in/out] pitch in pixels
++    UINT_32             pitchAlign,  ///< [in] pitch alignment
++    UINT_32*            pHeight,     ///< [in/out] height in pixels
++    UINT_32             heightAlign, ///< [in] height alignment
++    UINT_32*            pSlices,     ///< [in/out] number of slices
++    UINT_32             sliceAlign   ///< [in] number of slice alignment
++    ) const
++{
++    if (m_settings.isVolcanicIslands &&
++        flags.dccCompatible &&
++        (numSamples > 1) &&
++        (mipLevel == 0) &&
++        IsMacroTiled(tileMode))
++    {
++        UINT_32 tileSizePerSample = BITS_TO_BYTES(bpp * MicroTileWidth * MicroTileHeight);
++        UINT_32 samplesPerSplit  = pTileInfo->tileSplitBytes / tileSizePerSample;
++
++        if (samplesPerSplit < numSamples)
++        {
++            UINT_32 dccFastClearByteAlign = HwlGetPipes(pTileInfo) * m_pipeInterleaveBytes * 256;
++            UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * (*pHeight) * bpp * samplesPerSplit);
++
++            ADDR_ASSERT(IsPow2(dccFastClearByteAlign));
++
++            if (0 != (bytesPerSplit & (dccFastClearByteAlign - 1)))
++            {
++                UINT_32 dccFastClearPixelAlign = dccFastClearByteAlign /
++                                                BITS_TO_BYTES(bpp) /
++                                                samplesPerSplit;
++                UINT_32 macroTilePixelAlign = pitchAlign * heightAlign;
++
++                if ((dccFastClearPixelAlign >= macroTilePixelAlign) &&
++                    ((dccFastClearPixelAlign % macroTilePixelAlign) == 0))
++                {
++                    UINT_32 dccFastClearPitchAlignInMacroTile =
++                        dccFastClearPixelAlign / macroTilePixelAlign;
++                    UINT_32 heightInMacroTile = *pHeight / heightAlign;
++                    UINT_32 dccFastClearPitchAlignInPixels;
++
++                    while ((heightInMacroTile > 1) &&
++                           ((heightInMacroTile % 2) == 0) &&
++                           (dccFastClearPitchAlignInMacroTile > 1) &&
++                           ((dccFastClearPitchAlignInMacroTile % 2) == 0))
++                    {
++                        heightInMacroTile >>= 1;
++                        dccFastClearPitchAlignInMacroTile >>= 1;
++                    }
++
++                    dccFastClearPitchAlignInPixels = pitchAlign * dccFastClearPitchAlignInMacroTile;
++
++                    if (IsPow2(dccFastClearPitchAlignInPixels))
++                    {
++                        *pPitch = PowTwoAlign((*pPitch), dccFastClearPitchAlignInPixels);
++                    }
++                    else
++                    {
++                        *pPitch += (dccFastClearPitchAlignInPixels - 1);
++                        *pPitch /= dccFastClearPitchAlignInPixels;
++                        *pPitch *= dccFastClearPitchAlignInPixels;
++                    }
++                }
++            }
++        }
++    }
++}
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.h b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.h
+new file mode 100644
+index 0000000..0220736
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/ciaddrlib.h
+@@ -0,0 +1,197 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  ciaddrlib.h
++* @brief Contains the CIAddrLib class definition.
++***************************************************************************************************
++*/
++
++#ifndef __CI_ADDR_LIB_H__
++#define __CI_ADDR_LIB_H__
++
++#include "addrlib.h"
++#include "siaddrlib.h"
++
++/**
++***************************************************************************************************
++* @brief CI specific settings structure.
++***************************************************************************************************
++*/
++struct CIChipSettings
++{
++    struct
++    {
++        UINT_32 isSeaIsland : 1;
++        UINT_32 isBonaire   : 1;
++        UINT_32 isKaveri    : 1;
++        UINT_32 isSpectre   : 1;
++        UINT_32 isSpooky    : 1;
++        UINT_32 isKalindi   : 1;
++        // Hawaii is GFXIP 7.2, similar with CI (Bonaire)
++        UINT_32 isHawaii    : 1;
++
++        // VI
++        UINT_32 isVolcanicIslands : 1;
++        UINT_32 isIceland         : 1;
++        UINT_32 isTonga           : 1;
++        // VI fusion (Carrizo)
++        UINT_32 isCarrizo         : 1;
++    };
++};
++
++/**
++***************************************************************************************************
++* @brief This class is the CI specific address library
++*        function set.
++***************************************************************************************************
++*/
++class CIAddrLib : public SIAddrLib
++{
++public:
++    /// Creates CIAddrLib object
++    static AddrLib* CreateObj(const AddrClient* pClient)
++    {
++        return new(pClient) CIAddrLib(pClient);
++    }
++
++private:
++    CIAddrLib(const AddrClient* pClient);
++    virtual ~CIAddrLib();
++
++protected:
++
++    // Hwl interface - defined in AddrLib
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
++
++    virtual AddrChipFamily HwlConvertChipFamily(
++        UINT_32 uChipFamily, UINT_32 uChipRevision);
++
++    virtual BOOL_32 HwlInitGlobalParams(
++        const ADDR_CREATE_INPUT* pCreateIn);
++
++    virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
++        INT_32 index, INT_32 macroModeIndex, ADDR_TILEINFO* pInfo,
++        AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
++
++    virtual VOID HwlComputeTileDataWidthAndHeightLinear(
++        UINT_32* pMacroWidth, UINT_32* pMacroHeight,
++        UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
++
++    virtual INT_32 HwlComputeMacroModeIndex(
++        INT_32 tileIndex, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
++        ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL
++        ) const;
++
++    // Sub-hwl interface - defined in EgBasedAddrLib
++    virtual VOID HwlSetupTileInfo(
++        AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
++        AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    virtual INT_32 HwlPostCheckTileIndex(
++        const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
++        INT curIndex = TileIndexInvalid) const;
++
++    virtual VOID   HwlFmaskPreThunkSurfInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
++        const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
++
++    virtual VOID   HwlFmaskPostThunkSurfInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
++
++    virtual AddrTileMode HwlDegradeThickTileMode(
++        AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
++
++    virtual BOOL_32 HwlOverrideTileMode(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        AddrTileMode* pTileMode,
++        AddrTileType* pTileType) const;
++
++    virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
++        const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
++        ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
++        const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++protected:
++    virtual VOID HwlPadDimensions(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
++        UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
++        UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
++        UINT_32* pSlices, UINT_32 sliceAlign) const;
++
++private:
++    VOID ReadGbTileMode(
++        UINT_32 regValue, ADDR_TILECONFIG* pCfg) const;
++
++    VOID ReadGbMacroTileCfg(
++        UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
++
++    BOOL_32 InitTileSettingTable(
++        const UINT_32 *pSetting, UINT_32 noOfEntries);
++
++    BOOL_32 InitMacroTileCfgTable(
++        const UINT_32 *pSetting, UINT_32 noOfEntries);
++
++    UINT_64 HwlComputeMetadataNibbleAddress(
++        UINT_64 uncompressedDataByteAddress,
++        UINT_64 dataBaseByteAddress,
++        UINT_64 metadataBaseByteAddress,
++        UINT_32 metadataBitSize,
++        UINT_32 elementBitSize,
++        UINT_32 blockByteSize,
++        UINT_32 pipeInterleaveBytes,
++        UINT_32 numOfPipes,
++        UINT_32 numOfBanks,
++        UINT_32 numOfSamplesPerSplit) const;
++
++    static const UINT_32    MacroTileTableSize = 16;
++    ADDR_TILEINFO           m_macroTileTable[MacroTileTableSize];
++    UINT_32                 m_noOfMacroEntries;
++    BOOL_32                 m_allowNonDispThickModes;
++
++    CIChipSettings          m_settings;
++};
++
++#endif
++
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.cpp
+new file mode 100644
+index 0000000..2e16cb3
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.cpp
+@@ -0,0 +1,4578 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  egbaddrlib.cpp
++* @brief Contains the EgBasedAddrLib class implementation
++***************************************************************************************************
++*/
++
++#include "egbaddrlib.h"
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::EgBasedAddrLib
++*
++*   @brief
++*       Constructor
++*
++*   @note
++*
++***************************************************************************************************
++*/
++EgBasedAddrLib::EgBasedAddrLib(const AddrClient* pClient) :
++    AddrLib(pClient),
++    m_ranks(0),
++    m_logicalBanks(0),
++    m_bankInterleave(1)
++{
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::~EgBasedAddrLib
++*
++*   @brief
++*       Destructor
++***************************************************************************************************
++*/
++EgBasedAddrLib::~EgBasedAddrLib()
++{
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::DispatchComputeSurfaceInfo
++*
++*   @brief
++*       Compute surface sizes include padded pitch,height,slices,total size in bytes,
++*       meanwhile output suitable tile mode and base alignment might be changed in this
++*       call as well. Results are returned through output parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::DispatchComputeSurfaceInfo(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    AddrTileMode        tileMode      = pIn->tileMode;
++    UINT_32             bpp           = pIn->bpp;
++    UINT_32             numSamples    = pIn->numSamples;
++    UINT_32             numFrags      = ((pIn->numFrags == 0) ? numSamples : pIn->numFrags);
++    UINT_32             pitch         = pIn->width;
++    UINT_32             height        = pIn->height;
++    UINT_32             numSlices     = pIn->numSlices;
++    UINT_32             mipLevel      = pIn->mipLevel;
++    ADDR_SURFACE_FLAGS  flags         = pIn->flags;
++
++    ADDR_TILEINFO       tileInfoDef   = {0};
++    ADDR_TILEINFO*      pTileInfo     = &tileInfoDef;
++
++    UINT_32             padDims = 0;
++    BOOL_32             valid;
++
++    tileMode = DegradeLargeThickTile(tileMode, bpp);
++
++    // Only override numSamples for NI above
++    if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)
++    {
++        if (numFrags != numSamples) // This means EQAA
++        {
++            // The real surface size needed is determined by number of fragments
++            numSamples = numFrags;
++        }
++
++        // Save altered numSamples in pOut
++        pOut->numSamples = numSamples;
++    }
++
++    // Caller makes sure pOut->pTileInfo is not NULL, see HwlComputeSurfaceInfo
++    ADDR_ASSERT(pOut->pTileInfo);
++
++    if (pOut->pTileInfo != NULL)
++    {
++        pTileInfo = pOut->pTileInfo;
++    }
++
++    // Set default values
++    if (pIn->pTileInfo != NULL)
++    {
++        if (pTileInfo != pIn->pTileInfo)
++        {
++            *pTileInfo = *pIn->pTileInfo;
++        }
++    }
++    else
++    {
++        memset(pTileInfo, 0, sizeof(ADDR_TILEINFO));
++    }
++
++    // For macro tile mode, we should calculate default tiling parameters
++    HwlSetupTileInfo(tileMode,
++                     flags,
++                     bpp,
++                     pitch,
++                     height,
++                     numSamples,
++                     pIn->pTileInfo,
++                     pTileInfo,
++                     pIn->tileType,
++                     pOut);
++
++    if (flags.cube)
++    {
++        if (mipLevel == 0)
++        {
++            padDims = 2;
++        }
++
++        if (numSlices == 1)
++        {
++            // This is calculating one face, remove cube flag
++            flags.cube = 0;
++        }
++    }
++
++    switch (tileMode)
++    {
++        case ADDR_TM_LINEAR_GENERAL://fall through
++        case ADDR_TM_LINEAR_ALIGNED:
++            valid = ComputeSurfaceInfoLinear(pIn, pOut, padDims);
++            break;
++
++        case ADDR_TM_1D_TILED_THIN1://fall through
++        case ADDR_TM_1D_TILED_THICK:
++            valid = ComputeSurfaceInfoMicroTiled(pIn, pOut, padDims, tileMode);
++            break;
++
++        case ADDR_TM_2D_TILED_THIN1:    //fall through
++        case ADDR_TM_2D_TILED_THICK:    //fall through
++        case ADDR_TM_3D_TILED_THIN1:    //fall through
++        case ADDR_TM_3D_TILED_THICK:    //fall through
++        case ADDR_TM_2D_TILED_XTHICK:   //fall through
++        case ADDR_TM_3D_TILED_XTHICK:   //fall through
++        case ADDR_TM_PRT_TILED_THIN1:   //fall through
++        case ADDR_TM_PRT_2D_TILED_THIN1://fall through
++        case ADDR_TM_PRT_3D_TILED_THIN1://fall through
++        case ADDR_TM_PRT_TILED_THICK:   //fall through
++        case ADDR_TM_PRT_2D_TILED_THICK://fall through
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            valid = ComputeSurfaceInfoMacroTiled(pIn, pOut, padDims, tileMode);
++            break;
++
++        default:
++            valid = FALSE;
++            ADDR_ASSERT_ALWAYS();
++            break;
++    }
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceInfoLinear
++*
++*   @brief
++*       Compute linear surface sizes include padded pitch, height, slices, total size in
++*       bytes, meanwhile alignments as well. Since it is linear mode, so output tile mode
++*       will not be changed here. Results are returned through output parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoLinear(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,    ///< [in] Input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut,   ///< [out] Output structure
++    UINT_32                                 padDims ///< [in] Dimensions to padd
++    ) const
++{
++    UINT_32 expPitch = pIn->width;
++    UINT_32 expHeight = pIn->height;
++    UINT_32 expNumSlices = pIn->numSlices;
++
++    // No linear MSAA on real H/W, keep this for TGL
++    UINT_32 numSamples = pOut->numSamples;
++
++    const UINT_32 microTileThickness = 1;
++
++    //
++    // Compute the surface alignments.
++    //
++    ComputeSurfaceAlignmentsLinear(pIn->tileMode,
++                                   pIn->bpp,
++                                   pIn->flags,
++                                   &pOut->baseAlign,
++                                   &pOut->pitchAlign,
++                                   &pOut->heightAlign);
++
++    if ((pIn->tileMode == ADDR_TM_LINEAR_GENERAL) && pIn->flags.color && (pIn->height > 1))
++    {
++#if !ALT_TEST
++        // When linear_general surface is accessed in multiple lines, it requires 8 pixels in pitch
++        // alignment since PITCH_TILE_MAX is in unit of 8 pixels.
++        // It is OK if it is accessed per line.
++        ADDR_ASSERT((pIn->width % 8) == 0);
++#endif
++    }
++
++    pOut->depthAlign = microTileThickness;
++
++    expPitch = HwlPreHandleBaseLvl3xPitch(pIn, expPitch);
++
++    //
++    // Pad pitch and height to the required granularities.
++    //
++    PadDimensions(pIn->tileMode,
++                  pIn->bpp,
++                  pIn->flags,
++                  numSamples,
++                  pOut->pTileInfo,
++                  padDims,
++                  pIn->mipLevel,
++                  &expPitch, pOut->pitchAlign,
++                  &expHeight, pOut->heightAlign,
++                  &expNumSlices, microTileThickness);
++
++    expPitch = HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
++
++    //
++    // Adjust per HWL
++    //
++
++    UINT_64 logicalSliceSize;
++
++    logicalSliceSize = HwlGetSizeAdjustmentLinear(pIn->tileMode,
++                                                  pIn->bpp,
++                                                  numSamples,
++                                                  pOut->baseAlign,
++                                                  pOut->pitchAlign,
++                                                  &expPitch,
++                                                  &expHeight,
++                                                  &pOut->heightAlign);
++
++
++    pOut->pitch = expPitch;
++    pOut->height = expHeight;
++    pOut->depth = expNumSlices;
++
++    pOut->surfSize = logicalSliceSize * expNumSlices;
++
++    pOut->tileMode = pIn->tileMode;
++
++    return TRUE;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceInfoMicroTiled
++*
++*   @brief
++*       Compute 1D/Micro Tiled surface sizes include padded pitch, height, slices, total
++*       size in bytes, meanwhile alignments as well. Results are returned through output
++*       parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] Input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut,       ///< [out] Output structure
++    UINT_32                                 padDims,    ///< [in] Dimensions to padd
++    AddrTileMode                            expTileMode ///< [in] Expected tile mode
++    ) const
++{
++    BOOL_32 valid = TRUE;
++
++    UINT_32 microTileThickness;
++    UINT_32 expPitch = pIn->width;
++    UINT_32 expHeight = pIn->height;
++    UINT_32 expNumSlices = pIn->numSlices;
++
++    // No 1D MSAA on real H/W, keep this for TGL
++    UINT_32 numSamples = pOut->numSamples;
++
++    //
++    // Compute the micro tile thickness.
++    //
++    microTileThickness = ComputeSurfaceThickness(expTileMode);
++
++    //
++    // Extra override for mip levels
++    //
++    if (pIn->mipLevel > 0)
++    {
++        //
++        // Reduce tiling mode from thick to thin if the number of slices is less than the
++        // micro tile thickness.
++        //
++        if ((expTileMode == ADDR_TM_1D_TILED_THICK) &&
++            (expNumSlices < ThickTileThickness))
++        {
++            expTileMode = HwlDegradeThickTileMode(ADDR_TM_1D_TILED_THICK, expNumSlices, NULL);
++            if (expTileMode != ADDR_TM_1D_TILED_THICK)
++            {
++                microTileThickness = 1;
++            }
++        }
++    }
++
++    //
++    // Compute the surface restrictions.
++    //
++    ComputeSurfaceAlignmentsMicroTiled(expTileMode,
++                                       pIn->bpp,
++                                       pIn->flags,
++                                       numSamples,
++                                       &pOut->baseAlign,
++                                       &pOut->pitchAlign,
++                                       &pOut->heightAlign);
++
++    pOut->depthAlign = microTileThickness;
++
++    //
++    // Pad pitch and height to the required granularities.
++    // Compute surface size.
++    // Return parameters.
++    //
++    PadDimensions(expTileMode,
++                  pIn->bpp,
++                  pIn->flags,
++                  numSamples,
++                  pOut->pTileInfo,
++                  padDims,
++                  pIn->mipLevel,
++                  &expPitch, pOut->pitchAlign,
++                  &expHeight, pOut->heightAlign,
++                  &expNumSlices, microTileThickness);
++
++    //
++    // Get HWL specific pitch adjustment
++    //
++    UINT_64 logicalSliceSize = HwlGetSizeAdjustmentMicroTiled(microTileThickness,
++                                                              pIn->bpp,
++                                                              pIn->flags,
++                                                              numSamples,
++                                                              pOut->baseAlign,
++                                                              pOut->pitchAlign,
++                                                              &expPitch,
++                                                              &expHeight);
++
++
++    pOut->pitch = expPitch;
++    pOut->height = expHeight;
++    pOut->depth = expNumSlices;
++
++    pOut->surfSize = logicalSliceSize * expNumSlices;
++
++    pOut->tileMode = expTileMode;
++
++    return valid;
++}
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceInfoMacroTiled
++*
++*   @brief
++*       Compute 2D/macro tiled surface sizes include padded pitch, height, slices, total
++*       size in bytes, meanwhile output suitable tile mode and alignments might be changed
++*       in this call as well. Results are returned through output parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] Input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut,       ///< [out] Output structure
++    UINT_32                                 padDims,    ///< [in] Dimensions to padd
++    AddrTileMode                            expTileMode ///< [in] Expected tile mode
++    ) const
++{
++    BOOL_32 valid = TRUE;
++
++    AddrTileMode origTileMode = expTileMode;
++    UINT_32 microTileThickness;
++
++    UINT_32 paddedPitch;
++    UINT_32 paddedHeight;
++    UINT_64 bytesPerSlice;
++
++    UINT_32 expPitch     = pIn->width;
++    UINT_32 expHeight    = pIn->height;
++    UINT_32 expNumSlices = pIn->numSlices;
++
++    UINT_32 numSamples = pOut->numSamples;
++
++    //
++    // Compute the surface restrictions as base
++    // SanityCheckMacroTiled is called in ComputeSurfaceAlignmentsMacroTiled
++    //
++    valid = ComputeSurfaceAlignmentsMacroTiled(expTileMode,
++                                               pIn->bpp,
++                                               pIn->flags,
++                                               pIn->mipLevel,
++                                               numSamples,
++                                               pOut->pTileInfo,
++                                               &pOut->baseAlign,
++                                               &pOut->pitchAlign,
++                                               &pOut->heightAlign);
++
++    if (valid)
++    {
++        //
++        // Compute the micro tile thickness.
++        //
++        microTileThickness = ComputeSurfaceThickness(expTileMode);
++
++        //
++        // Find the correct tiling mode for mip levels
++        //
++        if (pIn->mipLevel > 0)
++        {
++            //
++            // Try valid tile mode
++            //
++            expTileMode = ComputeSurfaceMipLevelTileMode(expTileMode,
++                                                         pIn->bpp,
++                                                         expPitch,
++                                                         expHeight,
++                                                         expNumSlices,
++                                                         numSamples,
++                                                         pOut->pitchAlign,
++                                                         pOut->heightAlign,
++                                                         pOut->pTileInfo);
++
++            if (!IsMacroTiled(expTileMode)) // Downgraded to micro-tiled
++            {
++                return ComputeSurfaceInfoMicroTiled(pIn, pOut, padDims, expTileMode);
++            }
++            else
++            {
++                if (microTileThickness != ComputeSurfaceThickness(expTileMode))
++                {
++                    //
++                    // Re-compute if thickness changed since bank-height may be changed!
++                    //
++                    return ComputeSurfaceInfoMacroTiled(pIn, pOut, padDims, expTileMode);
++                }
++            }
++        }
++
++        paddedPitch     = expPitch;
++        paddedHeight    = expHeight;
++
++        //
++        // Re-cal alignment
++        //
++        if (expTileMode != origTileMode) // Tile mode is changed but still macro-tiled
++        {
++            valid = ComputeSurfaceAlignmentsMacroTiled(expTileMode,
++                                                       pIn->bpp,
++                                                       pIn->flags,
++                                                       pIn->mipLevel,
++                                                       numSamples,
++                                                       pOut->pTileInfo,
++                                                       &pOut->baseAlign,
++                                                       &pOut->pitchAlign,
++                                                       &pOut->heightAlign);
++        }
++
++        //
++        // Do padding
++        //
++        PadDimensions(expTileMode,
++                      pIn->bpp,
++                      pIn->flags,
++                      numSamples,
++                      pOut->pTileInfo,
++                      padDims,
++                      pIn->mipLevel,
++                      &paddedPitch, pOut->pitchAlign,
++                      &paddedHeight, pOut->heightAlign,
++                      &expNumSlices, microTileThickness);
++
++        if (pIn->flags.qbStereo &&
++            (pOut->pStereoInfo != NULL) &&
++            HwlStereoCheckRightOffsetPadding())
++        {
++            // Eye height's bank bits are different from y == 0?
++            // Since 3D rendering treats right eye buffer starting from y == "eye height" while
++            // display engine treats it to be 0, so the bank bits may be different, we pad
++            // more in height to make sure y == "eye height" has the same bank bits as y == 0.
++            UINT_32 checkMask = pOut->pTileInfo->banks - 1;
++            UINT_32 bankBits = 0;
++            do
++            {
++                bankBits = (paddedHeight / 8 / pOut->pTileInfo->bankHeight) & checkMask;
++
++                if (bankBits)
++                {
++                   paddedHeight += pOut->heightAlign;
++                }
++            } while (bankBits);
++        }
++
++        //
++        // Compute the size of a slice.
++        //
++        bytesPerSlice = BITS_TO_BYTES(static_cast<UINT_64>(paddedPitch) *
++                                      paddedHeight * NextPow2(pIn->bpp) * numSamples);
++
++        pOut->pitch = paddedPitch;
++        // Put this check right here to workaround special mipmap cases which the original height
++        // is needed.
++        // The original height is pre-stored in pOut->height in PostComputeMipLevel and
++        // pOut->pitch is needed in HwlCheckLastMacroTiledLvl, too.
++        if (m_configFlags.checkLast2DLevel && numSamples == 1) // Don't check MSAA
++        {
++            // Set a TRUE in pOut if next Level is the first 1D sub level
++            HwlCheckLastMacroTiledLvl(pIn, pOut);
++        }
++        pOut->height = paddedHeight;
++
++        pOut->depth = expNumSlices;
++
++        pOut->surfSize = bytesPerSlice * expNumSlices;
++
++        pOut->tileMode = expTileMode;
++
++        pOut->depthAlign = microTileThickness;
++
++    } // if (valid)
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceAlignmentsLinear
++*
++*   @brief
++*       Compute linear surface alignment, calculation results are returned through
++*       output parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsLinear(
++    AddrTileMode        tileMode,          ///< [in] tile mode
++    UINT_32             bpp,               ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,             ///< [in] surface flags
++    UINT_32*            pBaseAlign,        ///< [out] base address alignment in bytes
++    UINT_32*            pPitchAlign,       ///< [out] pitch alignment in pixels
++    UINT_32*            pHeightAlign       ///< [out] height alignment in pixels
++    ) const
++{
++    BOOL_32 valid = TRUE;
++
++    switch (tileMode)
++    {
++        case ADDR_TM_LINEAR_GENERAL:
++            //
++            // The required base alignment and pitch and height granularities is to 1 element.
++            //
++            *pBaseAlign   = (bpp > 8) ? bpp / 8 : 1;
++            *pPitchAlign  = 1;
++            *pHeightAlign = 1;
++            break;
++        case ADDR_TM_LINEAR_ALIGNED:
++            //
++            // The required alignment for base is the pipe interleave size.
++            // The required granularity for pitch is hwl dependent.
++            // The required granularity for height is one row.
++            //
++            *pBaseAlign     = m_pipeInterleaveBytes;
++            *pPitchAlign    = HwlGetPitchAlignmentLinear(bpp, flags);
++            *pHeightAlign   = 1;
++            break;
++        default:
++            *pBaseAlign     = 1;
++            *pPitchAlign    = 1;
++            *pHeightAlign   = 1;
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++
++    AdjustPitchAlignment(flags, pPitchAlign);
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled
++*
++*   @brief
++*       Compute 1D tiled surface alignment, calculation results are returned through
++*       output parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
++    AddrTileMode        tileMode,          ///< [in] tile mode
++    UINT_32             bpp,               ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,             ///< [in] surface flags
++    UINT_32             numSamples,        ///< [in] number of samples
++    UINT_32*            pBaseAlign,        ///< [out] base address alignment in bytes
++    UINT_32*            pPitchAlign,       ///< [out] pitch alignment in pixels
++    UINT_32*            pHeightAlign       ///< [out] height alignment in pixels
++    ) const
++{
++    BOOL_32 valid = TRUE;
++
++    //
++    // The required alignment for base is the pipe interleave size.
++    //
++    *pBaseAlign   = m_pipeInterleaveBytes;
++
++    *pPitchAlign  = HwlGetPitchAlignmentMicroTiled(tileMode, bpp, flags, numSamples);
++
++    *pHeightAlign = MicroTileHeight;
++
++    AdjustPitchAlignment(flags, pPitchAlign);
++
++    // ECR#393489
++    // Workaround 2 for 1D tiling -  There is HW bug for Carrizo
++    // where it requires the following alignments for 1D tiling.
++    if (flags.czDispCompatible)
++    {
++        *pBaseAlign  = PowTwoAlign(*pBaseAlign, 4096);                         //Base address MOD 4096 = 0
++        *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 >> (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
++    }
++    // end Carrizo workaround for 1D tilling
++
++    return valid;
++}
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlReduceBankWidthHeight
++*
++*   @brief
++*       Additional checks, reduce bankHeight/bankWidth if needed and possible
++*       tileSize*BANK_WIDTH*BANK_HEIGHT <= ROW_SIZE
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::HwlReduceBankWidthHeight(
++    UINT_32             tileSize,           ///< [in] tile size
++    UINT_32             bpp,                ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,              ///< [in] surface flags
++    UINT_32             numSamples,         ///< [in] number of samples
++    UINT_32             bankHeightAlign,    ///< [in] bank height alignment
++    UINT_32             pipes,              ///< [in] pipes
++    ADDR_TILEINFO*      pTileInfo           ///< [in/out] bank structure.
++    ) const
++{
++    UINT_32 macroAspectAlign;
++    BOOL_32 valid = TRUE;
++
++    if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize)
++    {
++        BOOL_32 stillGreater = TRUE;
++
++        // Try reducing bankWidth first
++        if (stillGreater && pTileInfo->bankWidth > 1)
++        {
++            while (stillGreater && pTileInfo->bankWidth > 0)
++            {
++                pTileInfo->bankWidth >>= 1;
++
++                if (pTileInfo->bankWidth == 0)
++                {
++                    pTileInfo->bankWidth = 1;
++                    break;
++                }
++
++                stillGreater =
++                    tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize;
++            }
++
++            // bankWidth is reduced above, so we need to recalculate bankHeight and ratio
++            bankHeightAlign = Max(1u,
++                                  m_pipeInterleaveBytes * m_bankInterleave /
++                                  (tileSize * pTileInfo->bankWidth)
++                                  );
++
++            // We cannot increase bankHeight so just assert this case.
++            ADDR_ASSERT((pTileInfo->bankHeight % bankHeightAlign) == 0);
++
++            if (numSamples == 1)
++            {
++                macroAspectAlign = Max(1u,
++                                   m_pipeInterleaveBytes * m_bankInterleave /
++                                   (tileSize * pipes * pTileInfo->bankWidth)
++                                   );
++                pTileInfo->macroAspectRatio = PowTwoAlign(pTileInfo->macroAspectRatio,
++                                                          macroAspectAlign);
++            }
++        }
++
++        // Early quit bank_height degradation for "64" bit z buffer
++        if (flags.depth && bpp >= 64)
++        {
++            stillGreater = FALSE;
++        }
++
++        // Then try reducing bankHeight
++        if (stillGreater && pTileInfo->bankHeight > bankHeightAlign)
++        {
++            while (stillGreater && pTileInfo->bankHeight > bankHeightAlign)
++            {
++                pTileInfo->bankHeight >>= 1;
++
++                if (pTileInfo->bankHeight < bankHeightAlign)
++                {
++                    pTileInfo->bankHeight = bankHeightAlign;
++                    break;
++                }
++
++                stillGreater =
++                    tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize;
++            }
++        }
++
++        valid = !stillGreater;
++
++        // Generate a warning if we still fail to meet this constraint
++        if (!valid)
++        {
++            ADDR_WARN(
++                0, ("TILE_SIZE(%d)*BANK_WIDTH(%d)*BANK_HEIGHT(%d) <= ROW_SIZE(%d)",
++                tileSize, pTileInfo->bankWidth, pTileInfo->bankHeight, m_rowSize));
++        }
++    }
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceAlignmentsMacroTiled
++*
++*   @brief
++*       Compute 2D tiled surface alignment, calculation results are returned through
++*       output parameters.
++*
++*   @return
++*       TRUE if no error occurs
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMacroTiled(
++    AddrTileMode        tileMode,           ///< [in] tile mode
++    UINT_32             bpp,                ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,              ///< [in] surface flags
++    UINT_32             mipLevel,           ///< [in] mip level
++    UINT_32             numSamples,         ///< [in] number of samples
++    ADDR_TILEINFO*      pTileInfo,          ///< [in/out] bank structure.
++    UINT_32*            pBaseAlign,         ///< [out] base address alignment in bytes
++    UINT_32*            pPitchAlign,        ///< [out] pitch alignment in pixels
++    UINT_32*            pHeightAlign        ///< [out] height alignment in pixels
++    ) const
++{
++    BOOL_32 valid = SanityCheckMacroTiled(pTileInfo);
++
++    if (valid)
++    {
++        UINT_32 macroTileWidth;
++        UINT_32 macroTileHeight;
++
++        UINT_32 tileSize;
++        UINT_32 bankHeightAlign;
++        UINT_32 macroAspectAlign;
++
++        UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++        UINT_32 pipes = HwlGetPipes(pTileInfo);
++
++        //
++        // Align bank height first according to latest h/w spec
++        //
++
++        // tile_size = MIN(tile_split, 64 * tile_thickness * element_bytes * num_samples)
++        tileSize = Min(pTileInfo->tileSplitBytes,
++                       BITS_TO_BYTES(64 * thickness * bpp * numSamples));
++
++        // bank_height_align =
++        // MAX(1, (pipe_interleave_bytes * bank_interleave)/(tile_size*bank_width))
++        bankHeightAlign = Max(1u,
++                              m_pipeInterleaveBytes * m_bankInterleave /
++                              (tileSize * pTileInfo->bankWidth)
++                              );
++
++        pTileInfo->bankHeight = PowTwoAlign(pTileInfo->bankHeight, bankHeightAlign);
++
++        // num_pipes * bank_width * macro_tile_aspect >=
++        // (pipe_interleave_size * bank_interleave) / tile_size
++        if (numSamples == 1)
++        {
++            // this restriction is only for mipmap (mipmap's numSamples must be 1)
++            macroAspectAlign = Max(1u,
++                               m_pipeInterleaveBytes * m_bankInterleave /
++                               (tileSize * pipes * pTileInfo->bankWidth)
++                               );
++            pTileInfo->macroAspectRatio = PowTwoAlign(pTileInfo->macroAspectRatio, macroAspectAlign);
++        }
++
++        valid = HwlReduceBankWidthHeight(tileSize,
++                                      bpp,
++                                      flags,
++                                      numSamples,
++                                      bankHeightAlign,
++                                      pipes,
++                                      pTileInfo);
++
++        //
++        // The required granularity for pitch is the macro tile width.
++        //
++        macroTileWidth = MicroTileWidth * pTileInfo->bankWidth * pipes *
++            pTileInfo->macroAspectRatio;
++
++        *pPitchAlign = macroTileWidth;
++
++        AdjustPitchAlignment(flags, pPitchAlign);
++
++        //
++        // The required granularity for height is the macro tile height.
++        //
++        macroTileHeight = MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
++            pTileInfo->macroAspectRatio;
++
++        *pHeightAlign = macroTileHeight;
++
++        //
++        // Compute base alignment
++        //
++        *pBaseAlign = pipes *
++            pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize;
++
++        if ((mipLevel == 0) && (flags.prt) && (m_chipFamily == ADDR_CHIP_FAMILY_SI))
++        {
++            static const UINT_32 PrtTileSize = 0x10000;
++
++            UINT_32 macroTileSize = macroTileWidth * macroTileHeight * numSamples * bpp / 8;
++
++            if (macroTileSize < PrtTileSize)
++            {
++                UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
++
++                ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
++
++                *pPitchAlign *= numMacroTiles;
++                *pBaseAlign  *= numMacroTiles;
++            }
++        }
++    }
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::SanityCheckMacroTiled
++*
++*   @brief
++*       Check if macro-tiled parameters are valid
++*   @return
++*       TRUE if valid
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::SanityCheckMacroTiled(
++    ADDR_TILEINFO* pTileInfo   ///< [in] macro-tiled parameters
++    ) const
++{
++    BOOL_32 valid       = TRUE;
++    UINT_32 numPipes    = HwlGetPipes(pTileInfo);
++
++    switch (pTileInfo->banks)
++    {
++        case 2: //fall through
++        case 4: //fall through
++        case 8: //fall through
++        case 16:
++            break;
++        default:
++            valid = FALSE;
++            break;
++
++    }
++
++    if (valid)
++    {
++        switch (pTileInfo->bankWidth)
++        {
++            case 1: //fall through
++            case 2: //fall through
++            case 4: //fall through
++            case 8:
++                break;
++            default:
++                valid = FALSE;
++                break;
++        }
++    }
++
++    if (valid)
++    {
++        switch (pTileInfo->bankHeight)
++        {
++            case 1: //fall through
++            case 2: //fall through
++            case 4: //fall through
++            case 8:
++                break;
++            default:
++                valid = FALSE;
++                break;
++        }
++    }
++
++    if (valid)
++    {
++        switch (pTileInfo->macroAspectRatio)
++        {
++            case 1: //fall through
++            case 2: //fall through
++            case 4: //fall through
++            case 8:
++                break;
++            default:
++                valid = FALSE;
++                break;
++        }
++    }
++
++    if (valid)
++    {
++        if (pTileInfo->banks < pTileInfo->macroAspectRatio)
++        {
++            // This will generate macro tile height <= 1
++            valid = FALSE;
++        }
++    }
++
++    if (valid)
++    {
++        if (pTileInfo->tileSplitBytes > m_rowSize)
++        {
++            valid = FALSE;
++        }
++    }
++
++    if (valid)
++    {
++        valid = HwlSanityCheckMacroTiled(pTileInfo);
++    }
++
++    ADDR_ASSERT(valid == TRUE);
++
++    // Add this assert for guidance
++    ADDR_ASSERT(numPipes * pTileInfo->banks >= 4);
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceMipLevelTileMode
++*
++*   @brief
++*       Compute valid tile mode for surface mipmap sub-levels
++*
++*   @return
++*       Suitable tile mode
++***************************************************************************************************
++*/
++AddrTileMode EgBasedAddrLib::ComputeSurfaceMipLevelTileMode(
++    AddrTileMode        baseTileMode,   ///< [in] base tile mode
++    UINT_32             bpp,            ///< [in] bits per pixels
++    UINT_32             pitch,          ///< [in] current level pitch
++    UINT_32             height,         ///< [in] current level height
++    UINT_32             numSlices,      ///< [in] current number of slices
++    UINT_32             numSamples,     ///< [in] number of samples
++    UINT_32             pitchAlign,     ///< [in] pitch alignment
++    UINT_32             heightAlign,    ///< [in] height alignment
++    ADDR_TILEINFO*      pTileInfo       ///< [in] ptr to bank structure
++    ) const
++{
++    UINT_64 bytesPerSlice;
++    UINT_32 bytesPerTile;
++
++    AddrTileMode expTileMode = baseTileMode;
++    UINT_32 microTileThickness = ComputeSurfaceThickness(expTileMode);
++    UINT_32 interleaveSize = m_pipeInterleaveBytes * m_bankInterleave;
++
++    //
++    // Compute the size of a slice.
++    //
++    bytesPerSlice = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
++    bytesPerTile = BITS_TO_BYTES(MicroTilePixels * microTileThickness * NextPow2(bpp) * numSamples);
++
++    //
++    // Reduce tiling mode from thick to thin if the number of slices is less than the
++    // micro tile thickness.
++    //
++    if (numSlices < microTileThickness)
++    {
++        expTileMode = HwlDegradeThickTileMode(expTileMode, numSlices, &bytesPerTile);
++    }
++
++    if (bytesPerTile > pTileInfo->tileSplitBytes)
++    {
++        bytesPerTile = pTileInfo->tileSplitBytes;
++    }
++
++    UINT_32 threshold1 =
++        bytesPerTile * HwlGetPipes(pTileInfo) * pTileInfo->bankWidth * pTileInfo->macroAspectRatio;
++
++    UINT_32 threshold2 =
++        bytesPerTile * pTileInfo->bankWidth * pTileInfo->bankHeight;
++
++    //
++    // Reduce the tile mode from 2D/3D to 1D in following conditions
++    //
++    switch (expTileMode)
++    {
++        case ADDR_TM_2D_TILED_THIN1: //fall through
++        case ADDR_TM_3D_TILED_THIN1:
++        case ADDR_TM_PRT_TILED_THIN1:
++        case ADDR_TM_PRT_2D_TILED_THIN1:
++        case ADDR_TM_PRT_3D_TILED_THIN1:
++            if ((pitch < pitchAlign) ||
++                (height < heightAlign) ||
++                (interleaveSize > threshold1) ||
++                (interleaveSize > threshold2))
++            {
++                expTileMode = ADDR_TM_1D_TILED_THIN1;
++            }
++            break;
++        case ADDR_TM_2D_TILED_THICK: //fall through
++        case ADDR_TM_3D_TILED_THICK:
++        case ADDR_TM_2D_TILED_XTHICK:
++        case ADDR_TM_3D_TILED_XTHICK:
++        case ADDR_TM_PRT_TILED_THICK:
++        case ADDR_TM_PRT_2D_TILED_THICK:
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            if ((pitch < pitchAlign) ||
++                (height < heightAlign))
++            {
++                expTileMode = ADDR_TM_1D_TILED_THICK;
++            }
++            break;
++        default:
++            break;
++    }
++
++    return expTileMode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlDegradeBaseLevel
++*   @brief
++*       Check if degrade is needed for base level
++*   @return
++*       TRUE if degrade is suggested
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::HwlDegradeBaseLevel(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const
++{
++    BOOL_32 degrade = FALSE;
++    BOOL_32 valid = TRUE;
++
++    ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
++
++    UINT_32 baseAlign;
++    UINT_32 pitchAlign;
++    UINT_32 heightAlign;
++
++    ADDR_ASSERT(pIn->pTileInfo);
++    ADDR_TILEINFO tileInfo = *pIn->pTileInfo;
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
++
++    if (UseTileIndex(pIn->tileIndex))
++    {
++        out.tileIndex = pIn->tileIndex;
++        out.macroModeIndex = TileIndexInvalid;
++    }
++
++    HwlSetupTileInfo(pIn->tileMode,
++                     pIn->flags,
++                     pIn->bpp,
++                     pIn->width,
++                     pIn->height,
++                     pIn->numSamples,
++                     &tileInfo,
++                     &tileInfo,
++                     pIn->tileType,
++                     &out);
++
++    valid = ComputeSurfaceAlignmentsMacroTiled(pIn->tileMode,
++                                               pIn->bpp,
++                                               pIn->flags,
++                                               pIn->mipLevel,
++                                               pIn->numSamples,
++                                               &tileInfo,
++                                               &baseAlign,
++                                               &pitchAlign,
++                                               &heightAlign);
++
++    if (valid)
++    {
++        degrade = (pIn->width < pitchAlign || pIn->height < heightAlign);
++    }
++    else
++    {
++        degrade = TRUE;
++    }
++
++    return degrade;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlDegradeThickTileMode
++*
++*   @brief
++*       Degrades valid tile mode for thick modes if needed
++*
++*   @return
++*       Suitable tile mode
++***************************************************************************************************
++*/
++AddrTileMode EgBasedAddrLib::HwlDegradeThickTileMode(
++    AddrTileMode        baseTileMode,   ///< [in] base tile mode
++    UINT_32             numSlices,      ///< [in] current number of slices
++    UINT_32*            pBytesPerTile   ///< [in/out] pointer to bytes per slice
++    ) const
++{
++    ADDR_ASSERT(numSlices < ComputeSurfaceThickness(baseTileMode));
++    // if pBytesPerTile is NULL, this is a don't-care....
++    UINT_32 bytesPerTile = pBytesPerTile != NULL ? *pBytesPerTile : 64;
++
++    AddrTileMode expTileMode = baseTileMode;
++    switch (baseTileMode)
++    {
++        case ADDR_TM_1D_TILED_THICK:
++            expTileMode = ADDR_TM_1D_TILED_THIN1;
++            bytesPerTile >>= 2;
++            break;
++        case ADDR_TM_2D_TILED_THICK:
++            expTileMode = ADDR_TM_2D_TILED_THIN1;
++            bytesPerTile >>= 2;
++            break;
++        case ADDR_TM_3D_TILED_THICK:
++            expTileMode = ADDR_TM_3D_TILED_THIN1;
++            bytesPerTile >>= 2;
++            break;
++        case ADDR_TM_2D_TILED_XTHICK:
++            if (numSlices < ThickTileThickness)
++            {
++                expTileMode = ADDR_TM_2D_TILED_THIN1;
++                bytesPerTile >>= 3;
++            }
++            else
++            {
++                expTileMode = ADDR_TM_2D_TILED_THICK;
++                bytesPerTile >>= 1;
++            }
++            break;
++        case ADDR_TM_3D_TILED_XTHICK:
++            if (numSlices < ThickTileThickness)
++            {
++                expTileMode = ADDR_TM_3D_TILED_THIN1;
++                bytesPerTile >>= 3;
++            }
++            else
++            {
++                expTileMode = ADDR_TM_3D_TILED_THICK;
++                bytesPerTile >>= 1;
++            }
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++            break;
++    }
++
++    if (pBytesPerTile != NULL)
++    {
++        *pBytesPerTile = bytesPerTile;
++    }
++
++    return expTileMode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::DispatchComputeSurfaceAddrFromCoord
++*
++*   @brief
++*       Compute surface address from given coord (x, y, slice,sample)
++*
++*   @return
++*       Address in bytes
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::DispatchComputeSurfaceAddrFromCoord(
++    const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut    ///< [out] output structure
++    ) const
++{
++    UINT_32             x                  = pIn->x;
++    UINT_32             y                  = pIn->y;
++    UINT_32             slice              = pIn->slice;
++    UINT_32             sample             = pIn->sample;
++    UINT_32             bpp                = pIn->bpp;
++    UINT_32             pitch              = pIn->pitch;
++    UINT_32             height             = pIn->height;
++    UINT_32             numSlices          = pIn->numSlices;
++    UINT_32             numSamples         = ((pIn->numSamples == 0) ? 1 : pIn->numSamples);
++    UINT_32             numFrags           = ((pIn->numFrags == 0) ? numSamples : pIn->numFrags);
++    AddrTileMode        tileMode           = pIn->tileMode;
++    AddrTileType        microTileType      = pIn->tileType;
++    BOOL_32             ignoreSE           = pIn->ignoreSE;
++    BOOL_32             isDepthSampleOrder = pIn->isDepth;
++    ADDR_TILEINFO*      pTileInfo          = pIn->pTileInfo;
++
++    UINT_32*            pBitPosition       = &pOut->bitPosition;
++    UINT_64             addr;
++
++#if ADDR_AM_BUILD
++    UINT_32             addr5Bit           = 0;
++    UINT_32             addr5Swizzle       = pIn->addr5Swizzle;
++    BOOL_32             is32ByteTile       = pIn->is32ByteTile;
++#endif
++
++    // ADDR_DEPTH_SAMPLE_ORDER = non-disp + depth-sample-order
++    if (microTileType == ADDR_DEPTH_SAMPLE_ORDER)
++    {
++        isDepthSampleOrder = TRUE;
++    }
++
++    if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)
++    {
++        if (numFrags != numSamples)
++        {
++            numSamples = numFrags;
++            ADDR_ASSERT(sample < numSamples);
++        }
++
++        /// @note
++        /// 128 bit/thick tiled surface doesn't support display tiling and
++        /// mipmap chain must have the same tileType, so please fill tileType correctly
++        if (!IsLinear(pIn->tileMode))
++        {
++            if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
++            {
++                ADDR_ASSERT(microTileType != ADDR_DISPLAYABLE);
++            }
++        }
++    }
++
++    switch (tileMode)
++    {
++        case ADDR_TM_LINEAR_GENERAL://fall through
++        case ADDR_TM_LINEAR_ALIGNED:
++            addr = ComputeSurfaceAddrFromCoordLinear(x,
++                                                     y,
++                                                     slice,
++                                                     sample,
++                                                     bpp,
++                                                     pitch,
++                                                     height,
++                                                     numSlices,
++                                                     pBitPosition);
++            break;
++        case ADDR_TM_1D_TILED_THIN1://fall through
++        case ADDR_TM_1D_TILED_THICK:
++            addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
++                                                         y,
++                                                         slice,
++                                                         sample,
++                                                         bpp,
++                                                         pitch,
++                                                         height,
++                                                         numSamples,
++                                                         tileMode,
++                                                         microTileType,
++                                                         isDepthSampleOrder,
++                                                         pBitPosition);
++            break;
++        case ADDR_TM_2D_TILED_THIN1:    //fall through
++        case ADDR_TM_2D_TILED_THICK:    //fall through
++        case ADDR_TM_3D_TILED_THIN1:    //fall through
++        case ADDR_TM_3D_TILED_THICK:    //fall through
++        case ADDR_TM_2D_TILED_XTHICK:   //fall through
++        case ADDR_TM_3D_TILED_XTHICK:   //fall through
++        case ADDR_TM_PRT_TILED_THIN1:   //fall through
++        case ADDR_TM_PRT_2D_TILED_THIN1://fall through
++        case ADDR_TM_PRT_3D_TILED_THIN1://fall through
++        case ADDR_TM_PRT_TILED_THICK:   //fall through
++        case ADDR_TM_PRT_2D_TILED_THICK://fall through
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            UINT_32 pipeSwizzle;
++            UINT_32 bankSwizzle;
++
++            if (m_configFlags.useCombinedSwizzle)
++            {
++                ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
++                                       &bankSwizzle, &pipeSwizzle);
++            }
++            else
++            {
++                pipeSwizzle = pIn->pipeSwizzle;
++                bankSwizzle = pIn->bankSwizzle;
++            }
++
++            addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
++                                                         y,
++                                                         slice,
++                                                         sample,
++                                                         bpp,
++                                                         pitch,
++                                                         height,
++                                                         numSamples,
++                                                         tileMode,
++                                                         microTileType,
++                                                         ignoreSE,
++                                                         isDepthSampleOrder,
++                                                         pipeSwizzle,
++                                                         bankSwizzle,
++                                                         pTileInfo,
++                                                         pBitPosition);
++            break;
++        default:
++            addr = 0;
++            ADDR_ASSERT_ALWAYS();
++            break;
++    }
++
++#if ADDR_AM_BUILD
++    if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)
++    {
++        if (addr5Swizzle && isDepthSampleOrder && is32ByteTile)
++        {
++            UINT_32 tx = x >> 3;
++            UINT_32 ty = y >> 3;
++            UINT_32 tileBits = ((ty&0x3) << 2) | (tx&0x3);
++
++            tileBits = tileBits & addr5Swizzle;
++            addr5Bit = XorReduce(tileBits, 4);
++
++            addr = addr | static_cast<UINT_64>(addr5Bit << 5);
++        }
++    }
++#endif
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceAddrFromCoordMicroTiled
++*
++*   @brief
++*       Computes the surface address and bit position from a
++*       coordinate for 2D tilied (macro tiled)
++*   @return
++*       The byte address
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::ComputeSurfaceAddrFromCoordMacroTiled(
++    UINT_32             x,                      ///< [in] x coordinate
++    UINT_32             y,                      ///< [in] y coordinate
++    UINT_32             slice,                  ///< [in] slice index
++    UINT_32             sample,                 ///< [in] sample index
++    UINT_32             bpp,                    ///< [in] bits per pixel
++    UINT_32             pitch,                  ///< [in] surface pitch, in pixels
++    UINT_32             height,                 ///< [in] surface height, in pixels
++    UINT_32             numSamples,             ///< [in] number of samples
++    AddrTileMode        tileMode,               ///< [in] tile mode
++    AddrTileType        microTileType,          ///< [in] micro tiling type
++    BOOL_32             ignoreSE,               ///< [in] TRUE if shader enginers can be ignored
++    BOOL_32             isDepthSampleOrder,     ///< [in] TRUE if it depth sample ordering is used
++    UINT_32             pipeSwizzle,            ///< [in] pipe swizzle
++    UINT_32             bankSwizzle,            ///< [in] bank swizzle
++    ADDR_TILEINFO*      pTileInfo,              ///< [in] bank structure
++                                                ///  **All fields to be valid on entry**
++    UINT_32*            pBitPosition            ///< [out] bit position, e.g. FMT_1 will use this
++    ) const
++{
++    UINT_64 addr;
++
++    UINT_32 microTileBytes;
++    UINT_32 microTileBits;
++    UINT_32 sampleOffset;
++    UINT_32 pixelIndex;
++    UINT_32 pixelOffset;
++    UINT_32 elementOffset;
++    UINT_32 tileSplitSlice;
++    UINT_32 pipe;
++    UINT_32 bank;
++    UINT_64 sliceBytes;
++    UINT_64 sliceOffset;
++    UINT_32 macroTilePitch;
++    UINT_32 macroTileHeight;
++    UINT_32 macroTilesPerRow;
++    UINT_32 macroTilesPerSlice;
++    UINT_64 macroTileBytes;
++    UINT_32 macroTileIndexX;
++    UINT_32 macroTileIndexY;
++    UINT_64 macroTileOffset;
++    UINT_64 totalOffset;
++    UINT_64 pipeInterleaveMask;
++    UINT_64 bankInterleaveMask;
++    UINT_64 pipeInterleaveOffset;
++    UINT_32 bankInterleaveOffset;
++    UINT_64 offset;
++    UINT_32 tileRowIndex;
++    UINT_32 tileColumnIndex;
++    UINT_32 tileIndex;
++    UINT_32 tileOffset;
++
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    //
++    // Compute the number of group, pipe, and bank bits.
++    //
++    UINT_32 numPipes              = HwlGetPipes(pTileInfo);
++    UINT_32 numPipeInterleaveBits = Log2(m_pipeInterleaveBytes);
++    UINT_32 numPipeBits           = Log2(numPipes);
++    UINT_32 numBankInterleaveBits = Log2(m_bankInterleave);
++    UINT_32 numBankBits           = Log2(pTileInfo->banks);
++
++    //
++    // Compute the micro tile size.
++    //
++    microTileBits = MicroTilePixels * microTileThickness * bpp * numSamples;
++
++    microTileBytes = microTileBits / 8;
++    //
++    // Compute the pixel index within the micro tile.
++    //
++    pixelIndex = ComputePixelIndexWithinMicroTile(x,
++                                                  y,
++                                                  slice,
++                                                  bpp,
++                                                  tileMode,
++                                                  microTileType);
++
++    //
++    // Compute the sample offset and pixel offset.
++    //
++    if (isDepthSampleOrder)
++    {
++        //
++        // For depth surfaces, samples are stored contiguously for each element, so the sample
++        // offset is the sample number times the element size.
++        //
++        sampleOffset = sample * bpp;
++        pixelOffset  = pixelIndex * bpp * numSamples;
++    }
++    else
++    {
++        //
++        // For color surfaces, all elements for a particular sample are stored contiguously, so
++        // the sample offset is the sample number times the micro tile size divided yBit the number
++        // of samples.
++        //
++        sampleOffset = sample * (microTileBits / numSamples);
++        pixelOffset  = pixelIndex * bpp;
++    }
++
++    //
++    // Compute the element offset.
++    //
++    elementOffset = pixelOffset + sampleOffset;
++
++    *pBitPosition = static_cast<UINT_32>(elementOffset % 8);
++
++    elementOffset /= 8; //bit-to-byte
++
++    //
++    // Determine if tiles need to be split across slices.
++    //
++    // If the size of the micro tile is larger than the tile split size, then the tile will be
++    // split across multiple slices.
++    //
++    UINT_32 slicesPerTile = 1;
++
++    if ((microTileBytes > pTileInfo->tileSplitBytes) && (microTileThickness == 1))
++    {   //don't support for thick mode
++
++        //
++        // Compute the number of slices per tile.
++        //
++        slicesPerTile = microTileBytes / pTileInfo->tileSplitBytes;
++
++        //
++        // Compute the tile split slice number for use in rotating the bank.
++        //
++        tileSplitSlice = elementOffset / pTileInfo->tileSplitBytes;
++
++        //
++        // Adjust the element offset to account for the portion of the tile that is being moved to
++        // a new slice..
++        //
++        elementOffset %= pTileInfo->tileSplitBytes;
++
++        //
++        // Adjust the microTileBytes size to tileSplitBytes size since
++        // a new slice..
++        //
++        microTileBytes = pTileInfo->tileSplitBytes;
++    }
++    else
++    {
++        tileSplitSlice = 0;
++    }
++
++    //
++    // Compute macro tile pitch and height.
++    //
++    macroTilePitch  =
++        (MicroTileWidth  * pTileInfo->bankWidth  * numPipes) * pTileInfo->macroAspectRatio;
++    macroTileHeight =
++        (MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks) / pTileInfo->macroAspectRatio;
++
++    //
++    // Compute the number of bytes per macro tile. Note: bytes of the same bank/pipe actually
++    //
++    macroTileBytes =
++        static_cast<UINT_64>(microTileBytes) *
++        (macroTilePitch / MicroTileWidth) * (macroTileHeight / MicroTileHeight) /
++        (numPipes * pTileInfo->banks);
++
++    //
++    // Compute the number of macro tiles per row.
++    //
++    macroTilesPerRow = pitch / macroTilePitch;
++
++    //
++    // Compute the offset to the macro tile containing the specified coordinate.
++    //
++    macroTileIndexX = x / macroTilePitch;
++    macroTileIndexY = y / macroTileHeight;
++    macroTileOffset = ((macroTileIndexY * macroTilesPerRow) + macroTileIndexX) * macroTileBytes;
++
++    //
++    // Compute the number of macro tiles per slice.
++    //
++    macroTilesPerSlice = macroTilesPerRow  * (height / macroTileHeight);
++
++    //
++    // Compute the slice size.
++    //
++    sliceBytes = macroTilesPerSlice * macroTileBytes;
++
++    //
++    // Compute the slice offset.
++    //
++    sliceOffset = sliceBytes * (tileSplitSlice + slicesPerTile * (slice / microTileThickness));
++
++    //
++    // Compute tile offest
++    //
++    tileRowIndex    = (y / MicroTileHeight) % pTileInfo->bankHeight;
++    tileColumnIndex = ((x / MicroTileWidth) / numPipes) % pTileInfo->bankWidth;
++    tileIndex        = (tileRowIndex * pTileInfo->bankWidth) + tileColumnIndex;
++    tileOffset       = tileIndex * microTileBytes;
++
++    //
++    // Combine the slice offset and macro tile offset with the pixel and sample offsets, accounting
++    // for the pipe and bank bits in the middle of the address.
++    //
++    totalOffset = sliceOffset + macroTileOffset + elementOffset + tileOffset;
++
++    //
++    // Get the pipe and bank.
++    //
++
++    // when the tileMode is PRT type, then adjust x and y coordinates
++    if (IsPrtNoRotationTileMode(tileMode))
++    {
++        x = x % macroTilePitch;
++        y = y % macroTileHeight;
++    }
++
++    pipe = ComputePipeFromCoord(x,
++                                y,
++                                slice,
++                                tileMode,
++                                pipeSwizzle,
++                                ignoreSE,
++                                pTileInfo);
++
++    bank = ComputeBankFromCoord(x,
++                                y,
++                                slice,
++                                tileMode,
++                                bankSwizzle,
++                                tileSplitSlice,
++                                pTileInfo);
++
++
++    //
++    // Split the offset to put some bits below the pipe+bank bits and some above.
++    //
++    pipeInterleaveMask = (1 << numPipeInterleaveBits) - 1;
++    bankInterleaveMask = (1 << numBankInterleaveBits) - 1;
++    pipeInterleaveOffset = totalOffset & pipeInterleaveMask;
++    bankInterleaveOffset = static_cast<UINT_32>((totalOffset >> numPipeInterleaveBits) &
++                                                bankInterleaveMask);
++    offset               =  totalOffset >> (numPipeInterleaveBits + numBankInterleaveBits);
++
++    //
++    // Assemble the address from its components.
++    //
++    addr  = pipeInterleaveOffset;
++    // This is to remove /analyze warnings
++    UINT_32 pipeBits            = pipe                 <<  numPipeInterleaveBits;
++    UINT_32 bankInterleaveBits  = bankInterleaveOffset << (numPipeInterleaveBits + numPipeBits);
++    UINT_32 bankBits            = bank                 << (numPipeInterleaveBits + numPipeBits +
++                                                           numBankInterleaveBits);
++    UINT_64 offsetBits          = offset               << (numPipeInterleaveBits + numPipeBits +
++                                                           numBankInterleaveBits + numBankBits);
++
++    addr |= pipeBits;
++    addr |= bankInterleaveBits;
++    addr |= bankBits;
++    addr |= offsetBits;
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceAddrFromCoordMicroTiled
++*
++*   @brief
++*       Computes the surface address and bit position from a coordinate for 1D tilied
++*       (micro tiled)
++*   @return
++*       The byte address
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::ComputeSurfaceAddrFromCoordMicroTiled(
++    UINT_32             x,                      ///< [in] x coordinate
++    UINT_32             y,                      ///< [in] y coordinate
++    UINT_32             slice,                  ///< [in] slice index
++    UINT_32             sample,                 ///< [in] sample index
++    UINT_32             bpp,                    ///< [in] bits per pixel
++    UINT_32             pitch,                  ///< [in] pitch, in pixels
++    UINT_32             height,                 ///< [in] height, in pixels
++    UINT_32             numSamples,             ///< [in] number of samples
++    AddrTileMode        tileMode,               ///< [in] tile mode
++    AddrTileType        microTileType,          ///< [in] micro tiling type
++    BOOL_32             isDepthSampleOrder,     ///< [in] TRUE if depth sample ordering is used
++    UINT_32*            pBitPosition            ///< [out] bit position, e.g. FMT_1 will use this
++    ) const
++{
++    UINT_64 addr = 0;
++
++    UINT_32 microTileBytes;
++    UINT_64 sliceBytes;
++    UINT_32 microTilesPerRow;
++    UINT_32 microTileIndexX;
++    UINT_32 microTileIndexY;
++    UINT_32 microTileIndexZ;
++    UINT_64 sliceOffset;
++    UINT_64 microTileOffset;
++    UINT_32 sampleOffset;
++    UINT_32 pixelIndex;
++    UINT_32 pixelOffset;
++
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    //
++    // Compute the micro tile size.
++    //
++    microTileBytes = BITS_TO_BYTES(MicroTilePixels * microTileThickness * bpp * numSamples);
++
++    //
++    // Compute the slice size.
++    //
++    sliceBytes =
++        BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * microTileThickness * bpp * numSamples);
++
++    //
++    // Compute the number of micro tiles per row.
++    //
++    microTilesPerRow = pitch / MicroTileWidth;
++
++    //
++    // Compute the micro tile index.
++    //
++    microTileIndexX = x     / MicroTileWidth;
++    microTileIndexY = y     / MicroTileHeight;
++    microTileIndexZ = slice / microTileThickness;
++
++    //
++    // Compute the slice offset.
++    //
++    sliceOffset = static_cast<UINT_64>(microTileIndexZ) * sliceBytes;
++
++    //
++    // Compute the offset to the micro tile containing the specified coordinate.
++    //
++    microTileOffset = (static_cast<UINT_64>(microTileIndexY) * microTilesPerRow + microTileIndexX) *
++        microTileBytes;
++
++    //
++    // Compute the pixel index within the micro tile.
++    //
++    pixelIndex = ComputePixelIndexWithinMicroTile(x,
++                                                  y,
++                                                  slice,
++                                                  bpp,
++                                                  tileMode,
++                                                  microTileType);
++
++    // Compute the sample offset.
++    //
++    if (isDepthSampleOrder)
++    {
++        //
++        // For depth surfaces, samples are stored contiguously for each element, so the sample
++        // offset is the sample number times the element size.
++        //
++        sampleOffset = sample * bpp;
++        pixelOffset = pixelIndex * bpp * numSamples;
++    }
++    else
++    {
++        //
++        // For color surfaces, all elements for a particular sample are stored contiguously, so
++        // the sample offset is the sample number times the micro tile size divided yBit the number
++        // of samples.
++        //
++        sampleOffset = sample * (microTileBytes*8 / numSamples);
++        pixelOffset = pixelIndex * bpp;
++    }
++
++    //
++    // Compute the bit position of the pixel.  Each element is stored with one bit per sample.
++    //
++
++    UINT_32 elemOffset = sampleOffset + pixelOffset;
++
++    *pBitPosition = elemOffset % 8;
++    elemOffset /= 8;
++
++    //
++    // Combine the slice offset, micro tile offset, sample offset, and pixel offsets.
++    //
++    addr = sliceOffset + microTileOffset + elemOffset;
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputePixelCoordFromOffset
++*
++*   @brief
++*       Compute pixel coordinate from offset inside a micro tile
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::HwlComputePixelCoordFromOffset(
++    UINT_32         offset,             ///< [in] offset inside micro tile in bits
++    UINT_32         bpp,                ///< [in] bits per pixel
++    UINT_32         numSamples,         ///< [in] number of samples
++    AddrTileMode    tileMode,           ///< [in] tile mode
++    UINT_32         tileBase,           ///< [in] base offset within a tile
++    UINT_32         compBits,           ///< [in] component bits actually needed(for planar surface)
++    UINT_32*        pX,                 ///< [out] x coordinate
++    UINT_32*        pY,                 ///< [out] y coordinate
++    UINT_32*        pSlice,             ///< [out] slice index
++    UINT_32*        pSample,            ///< [out] sample index
++    AddrTileType    microTileType,      ///< [in] micro tiling type
++    BOOL_32         isDepthSampleOrder  ///< [in] TRUE if depth sample order in microtile is used
++    ) const
++{
++    UINT_32 x = 0;
++    UINT_32 y = 0;
++    UINT_32 z = 0;
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++
++    // For planar surface, we adjust offset acoording to tile base
++    if ((bpp != compBits) && (compBits != 0) && isDepthSampleOrder)
++    {
++        offset -= tileBase;
++
++        ADDR_ASSERT(microTileType == ADDR_NON_DISPLAYABLE ||
++                    microTileType == ADDR_DEPTH_SAMPLE_ORDER);
++
++        bpp = compBits;
++    }
++
++    UINT_32 sampleTileBits;
++    UINT_32 samplePixelBits;
++    UINT_32 pixelIndex;
++
++    if (isDepthSampleOrder)
++    {
++        samplePixelBits = bpp * numSamples;
++        pixelIndex = offset / samplePixelBits;
++        *pSample = (offset % samplePixelBits) / bpp;
++    }
++    else
++    {
++        sampleTileBits = MicroTilePixels * bpp * thickness;
++        *pSample = offset / sampleTileBits;
++        pixelIndex = (offset % sampleTileBits) / bpp;
++    }
++
++    if (microTileType != ADDR_THICK)
++    {
++        if (microTileType == ADDR_DISPLAYABLE) // displayable
++        {
++            switch (bpp)
++            {
++                case 8:
++                    x = pixelIndex & 0x7;
++                    y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,3),_BIT(pixelIndex,4));
++                    break;
++                case 16:
++                    x = pixelIndex & 0x7;
++                    y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,4),_BIT(pixelIndex,3));
++                    break;
++                case 32:
++                    x = Bits2Number(3, _BIT(pixelIndex,3),_BIT(pixelIndex,1),_BIT(pixelIndex,0));
++                    y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,4),_BIT(pixelIndex,2));
++                    break;
++                case 64:
++                    x = Bits2Number(3, _BIT(pixelIndex,3),_BIT(pixelIndex,2),_BIT(pixelIndex,0));
++                    y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,4),_BIT(pixelIndex,1));
++                    break;
++                case 128:
++                    x = Bits2Number(3, _BIT(pixelIndex,3),_BIT(pixelIndex,2),_BIT(pixelIndex,1));
++                    y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,4),_BIT(pixelIndex,0));
++                    break;
++                default:
++                    break;
++            }
++        }
++        else if (microTileType == ADDR_NON_DISPLAYABLE || microTileType == ADDR_DEPTH_SAMPLE_ORDER)
++        {
++            x = Bits2Number(3, _BIT(pixelIndex,4),_BIT(pixelIndex,2),_BIT(pixelIndex,0));
++            y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,3),_BIT(pixelIndex,1));
++        }
++        else if (microTileType == ADDR_ROTATED)
++        {
++            /*
++                8-Bit Elements
++                element_index[5:0] = { x[2], x[0], x[1], y[2], y[1], y[0] }
++
++                16-Bit Elements
++                element_index[5:0] = { x[2], x[1], x[0], y[2], y[1], y[0] }
++
++                32-Bit Elements
++                element_index[5:0] = { x[2], x[1], y[2], x[0], y[1], y[0] }
++
++                64-Bit Elements
++                element_index[5:0] = { y[2], x[2], x[1], y[1], x[0], y[0] }
++            */
++            switch(bpp)
++            {
++                case 8:
++                    x = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,3),_BIT(pixelIndex,4));
++                    y = pixelIndex & 0x7;
++                    break;
++                case 16:
++                    x = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,4),_BIT(pixelIndex,3));
++                    y = pixelIndex & 0x7;
++                    break;
++                case 32:
++                    x = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,4),_BIT(pixelIndex,2));
++                    y = Bits2Number(3, _BIT(pixelIndex,3),_BIT(pixelIndex,1),_BIT(pixelIndex,0));
++                    break;
++                case 64:
++                    x = Bits2Number(3, _BIT(pixelIndex,4),_BIT(pixelIndex,3),_BIT(pixelIndex,1));
++                    y = Bits2Number(3, _BIT(pixelIndex,5),_BIT(pixelIndex,2),_BIT(pixelIndex,0));
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    break;
++            }
++        }
++
++        if (thickness > 1) // thick
++        {
++            z = Bits2Number(3, _BIT(pixelIndex,8),_BIT(pixelIndex,7),_BIT(pixelIndex,6));
++        }
++    }
++    else
++    {
++        ADDR_ASSERT((m_chipFamily >= ADDR_CHIP_FAMILY_CI) && (thickness > 1));
++        /*
++            8-Bit Elements and 16-Bit Elements
++            element_index[7:0] = { y[2], x[2], z[1], z[0], y[1], x[1], y[0], x[0] }
++
++            32-Bit Elements
++            element_index[7:0] = { y[2], x[2], z[1], y[1], z[0], x[1], y[0], x[0] }
++
++            64-Bit Elements and 128-Bit Elements
++            element_index[7:0] = { y[2], x[2], z[1], y[1], x[1], z[0], y[0], x[0] }
++
++            The equation to compute the element index for the extra thick tile:
++            element_index[8] = z[2]
++        */
++        switch (bpp)
++        {
++            case 8:
++            case 16: // fall-through
++                x = Bits2Number(3, _BIT(pixelIndex,6),_BIT(pixelIndex,2),_BIT(pixelIndex,0));
++                y = Bits2Number(3, _BIT(pixelIndex,7),_BIT(pixelIndex,3),_BIT(pixelIndex,1));
++                z = Bits2Number(2, _BIT(pixelIndex,5),_BIT(pixelIndex,4));
++                break;
++            case 32:
++                x = Bits2Number(3, _BIT(pixelIndex,6),_BIT(pixelIndex,2),_BIT(pixelIndex,0));
++                y = Bits2Number(3, _BIT(pixelIndex,7),_BIT(pixelIndex,4),_BIT(pixelIndex,1));
++                z = Bits2Number(2, _BIT(pixelIndex,5),_BIT(pixelIndex,3));
++                break;
++            case 64:
++            case 128: // fall-through
++                x = Bits2Number(3, _BIT(pixelIndex,6),_BIT(pixelIndex,3),_BIT(pixelIndex,0));
++                y = Bits2Number(3, _BIT(pixelIndex,7),_BIT(pixelIndex,4),_BIT(pixelIndex,1));
++                z = Bits2Number(2, _BIT(pixelIndex,5),_BIT(pixelIndex,2));
++                break;
++            default:
++                ADDR_ASSERT_ALWAYS();
++                break;
++        }
++
++        if (thickness == 8)
++        {
++            z += Bits2Number(3,_BIT(pixelIndex,8),0,0);
++        }
++    }
++
++    *pX = x;
++    *pY = y;
++    *pSlice += z;
++}
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::DispatchComputeSurfaceCoordFromAddrDispatch
++*
++*   @brief
++*       Compute (x,y,slice,sample) coordinates from surface address
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::DispatchComputeSurfaceCoordFromAddr(
++    const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut    ///< [out] output structure
++    ) const
++{
++    UINT_64             addr               = pIn->addr;
++    UINT_32             bitPosition        = pIn->bitPosition;
++    UINT_32             bpp                = pIn->bpp;
++    UINT_32             pitch              = pIn->pitch;
++    UINT_32             height             = pIn->height;
++    UINT_32             numSlices          = pIn->numSlices;
++    UINT_32             numSamples         = ((pIn->numSamples == 0) ? 1 : pIn->numSamples);
++    UINT_32             numFrags           = ((pIn->numFrags == 0) ? numSamples : pIn->numFrags);
++    AddrTileMode        tileMode           = pIn->tileMode;
++    UINT_32             tileBase           = pIn->tileBase;
++    UINT_32             compBits           = pIn->compBits;
++    AddrTileType        microTileType      = pIn->tileType;
++    BOOL_32             ignoreSE           = pIn->ignoreSE;
++    BOOL_32             isDepthSampleOrder = pIn->isDepth;
++    ADDR_TILEINFO*      pTileInfo          = pIn->pTileInfo;
++
++    UINT_32*            pX                 = &pOut->x;
++    UINT_32*            pY                 = &pOut->y;
++    UINT_32*            pSlice             = &pOut->slice;
++    UINT_32*            pSample            = &pOut->sample;
++
++    if (microTileType == ADDR_DEPTH_SAMPLE_ORDER)
++    {
++        isDepthSampleOrder = TRUE;
++    }
++
++    if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)
++    {
++        if (numFrags != numSamples)
++        {
++            numSamples = numFrags;
++        }
++
++        /// @note
++        /// 128 bit/thick tiled surface doesn't support display tiling and
++        /// mipmap chain must have the same tileType, so please fill tileType correctly
++        if (!IsLinear(pIn->tileMode))
++        {
++            if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
++            {
++                ADDR_ASSERT(microTileType != ADDR_DISPLAYABLE);
++            }
++        }
++    }
++
++    switch (tileMode)
++    {
++        case ADDR_TM_LINEAR_GENERAL://fall through
++        case ADDR_TM_LINEAR_ALIGNED:
++            ComputeSurfaceCoordFromAddrLinear(addr,
++                                              bitPosition,
++                                              bpp,
++                                              pitch,
++                                              height,
++                                              numSlices,
++                                              pX,
++                                              pY,
++                                              pSlice,
++                                              pSample);
++            break;
++        case ADDR_TM_1D_TILED_THIN1://fall through
++        case ADDR_TM_1D_TILED_THICK:
++            ComputeSurfaceCoordFromAddrMicroTiled(addr,
++                                                  bitPosition,
++                                                  bpp,
++                                                  pitch,
++                                                  height,
++                                                  numSamples,
++                                                  tileMode,
++                                                  tileBase,
++                                                  compBits,
++                                                  pX,
++                                                  pY,
++                                                  pSlice,
++                                                  pSample,
++                                                  microTileType,
++                                                  isDepthSampleOrder);
++            break;
++        case ADDR_TM_2D_TILED_THIN1:    //fall through
++        case ADDR_TM_2D_TILED_THICK:    //fall through
++        case ADDR_TM_3D_TILED_THIN1:    //fall through
++        case ADDR_TM_3D_TILED_THICK:    //fall through
++        case ADDR_TM_2D_TILED_XTHICK:   //fall through
++        case ADDR_TM_3D_TILED_XTHICK:   //fall through
++        case ADDR_TM_PRT_TILED_THIN1:   //fall through
++        case ADDR_TM_PRT_2D_TILED_THIN1://fall through
++        case ADDR_TM_PRT_3D_TILED_THIN1://fall through
++        case ADDR_TM_PRT_TILED_THICK:   //fall through
++        case ADDR_TM_PRT_2D_TILED_THICK://fall through
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            UINT_32 pipeSwizzle;
++            UINT_32 bankSwizzle;
++
++            if (m_configFlags.useCombinedSwizzle)
++            {
++                ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
++                                       &bankSwizzle, &pipeSwizzle);
++            }
++            else
++            {
++                pipeSwizzle = pIn->pipeSwizzle;
++                bankSwizzle = pIn->bankSwizzle;
++            }
++
++            ComputeSurfaceCoordFromAddrMacroTiled(addr,
++                                                  bitPosition,
++                                                  bpp,
++                                                  pitch,
++                                                  height,
++                                                  numSamples,
++                                                  tileMode,
++                                                  tileBase,
++                                                  compBits,
++                                                  microTileType,
++                                                  ignoreSE,
++                                                  isDepthSampleOrder,
++                                                  pipeSwizzle,
++                                                  bankSwizzle,
++                                                  pTileInfo,
++                                                  pX,
++                                                  pY,
++                                                  pSlice,
++                                                  pSample);
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++    }
++}
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceCoordFromAddrMacroTiled
++*
++*   @brief
++*       Compute surface coordinates from address for macro tiled surface
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::ComputeSurfaceCoordFromAddrMacroTiled(
++    UINT_64             addr,               ///< [in] byte address
++    UINT_32             bitPosition,        ///< [in] bit position
++    UINT_32             bpp,                ///< [in] bits per pixel
++    UINT_32             pitch,              ///< [in] pitch in pixels
++    UINT_32             height,             ///< [in] height in pixels
++    UINT_32             numSamples,         ///< [in] number of samples
++    AddrTileMode        tileMode,           ///< [in] tile mode
++    UINT_32             tileBase,           ///< [in] tile base offset
++    UINT_32             compBits,           ///< [in] component bits (for planar surface)
++    AddrTileType        microTileType,      ///< [in] micro tiling type
++    BOOL_32             ignoreSE,           ///< [in] TRUE if shader engines can be ignored
++    BOOL_32             isDepthSampleOrder, ///< [in] TRUE if depth sample order is used
++    UINT_32             pipeSwizzle,        ///< [in] pipe swizzle
++    UINT_32             bankSwizzle,        ///< [in] bank swizzle
++    ADDR_TILEINFO*      pTileInfo,          ///< [in] bank structure.
++                                            ///  **All fields to be valid on entry**
++    UINT_32*            pX,                 ///< [out] X coord
++    UINT_32*            pY,                 ///< [out] Y coord
++    UINT_32*            pSlice,             ///< [out] slice index
++    UINT_32*            pSample             ///< [out] sample index
++    ) const
++{
++    UINT_32 mx;
++    UINT_32 my;
++    UINT_64 tileBits;
++    UINT_64 macroTileBits;
++    UINT_32 slices;
++    UINT_32 tileSlices;
++    UINT_64 elementOffset;
++    UINT_64 macroTileIndex;
++    UINT_32 tileIndex;
++    UINT_64 totalOffset;
++
++
++    UINT_32 bank;
++    UINT_32 pipe;
++    UINT_32 groupBits = m_pipeInterleaveBytes << 3;
++    UINT_32 pipes = HwlGetPipes(pTileInfo);
++    UINT_32 banks = pTileInfo->banks;
++
++    UINT_32 bankInterleave = m_bankInterleave;
++
++    UINT_64 addrBits = BYTES_TO_BITS(addr) + bitPosition;
++
++    //
++    // remove bits for bank and pipe
++    //
++    totalOffset = (addrBits % groupBits) +
++        (((addrBits / groupBits / pipes) % bankInterleave) * groupBits) +
++        (((addrBits / groupBits / pipes) / bankInterleave) / banks) * groupBits * bankInterleave;
++
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    UINT_32 microTileBits = bpp * microTileThickness * MicroTilePixels * numSamples;
++
++    UINT_32 microTileBytes = BITS_TO_BYTES(microTileBits);
++    //
++    // Determine if tiles need to be split across slices.
++    //
++    // If the size of the micro tile is larger than the tile split size, then the tile will be
++    // split across multiple slices.
++    //
++    UINT_32 slicesPerTile = 1; //_State->TileSlices
++
++    if ((microTileBytes > pTileInfo->tileSplitBytes) && (microTileThickness == 1))
++    {   //don't support for thick mode
++
++        //
++        // Compute the number of slices per tile.
++        //
++        slicesPerTile = microTileBytes / pTileInfo->tileSplitBytes;
++    }
++
++    tileBits = microTileBits / slicesPerTile; // micro tile bits
++
++    // in micro tiles because not MicroTileWidth timed.
++    UINT_32 macroWidth  = pTileInfo->bankWidth * pipes * pTileInfo->macroAspectRatio;
++    // in micro tiles as well
++    UINT_32 macroHeight = pTileInfo->bankHeight * banks / pTileInfo->macroAspectRatio;
++
++    UINT_32 pitchInMacroTiles = pitch / MicroTileWidth / macroWidth;
++
++    macroTileBits = (macroWidth * macroHeight) * tileBits / (banks * pipes);
++
++    macroTileIndex = totalOffset / macroTileBits;
++
++    // pitchMacros * height / heightMacros;  macroTilesPerSlice == _State->SliceMacros
++    UINT_32 macroTilesPerSlice = (pitch / (macroWidth * MicroTileWidth)) * height /
++        (macroHeight * MicroTileWidth);
++
++    slices = static_cast<UINT_32>(macroTileIndex / macroTilesPerSlice);
++
++    *pSlice = static_cast<UINT_32>(slices / slicesPerTile * microTileThickness);
++
++    //
++    // calculate element offset and x[2:0], y[2:0], z[1:0] for thick
++    //
++    tileSlices = slices % slicesPerTile;
++
++    elementOffset  = tileSlices * tileBits;
++    elementOffset += totalOffset % tileBits;
++
++    UINT_32 coordZ = 0;
++
++    HwlComputePixelCoordFromOffset(static_cast<UINT_32>(elementOffset),
++                                   bpp,
++                                   numSamples,
++                                   tileMode,
++                                   tileBase,
++                                   compBits,
++                                   pX,
++                                   pY,
++                                   &coordZ,
++                                   pSample,
++                                   microTileType,
++                                   isDepthSampleOrder);
++
++    macroTileIndex = macroTileIndex % macroTilesPerSlice;
++    *pY += static_cast<UINT_32>(macroTileIndex / pitchInMacroTiles * macroHeight * MicroTileHeight);
++    *pX += static_cast<UINT_32>(macroTileIndex % pitchInMacroTiles * macroWidth * MicroTileWidth);
++
++    *pSlice += coordZ;
++
++    tileIndex = static_cast<UINT_32>((totalOffset % macroTileBits) / tileBits);
++
++    my = (tileIndex / pTileInfo->bankWidth) % pTileInfo->bankHeight * MicroTileHeight;
++    mx = (tileIndex % pTileInfo->bankWidth) * pipes * MicroTileWidth;
++
++    *pY += my;
++    *pX += mx;
++
++    bank = ComputeBankFromAddr(addr, banks, pipes);
++    pipe = ComputePipeFromAddr(addr, pipes);
++
++    HwlComputeSurfaceCoord2DFromBankPipe(tileMode,
++                                         pX,
++                                         pY,
++                                         *pSlice,
++                                         bank,
++                                         pipe,
++                                         bankSwizzle,
++                                         pipeSwizzle,
++                                         tileSlices,
++                                         ignoreSE,
++                                         pTileInfo);
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSurfaceCoord2DFromBankPipe
++*
++*   @brief
++*       Compute surface x,y coordinates from bank/pipe info
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::ComputeSurfaceCoord2DFromBankPipe(
++    AddrTileMode        tileMode,   ///< [in] tile mode
++    UINT_32             x,          ///< [in] x coordinate
++    UINT_32             y,          ///< [in] y coordinate
++    UINT_32             slice,      ///< [in] slice index
++    UINT_32             bank,       ///< [in] bank number
++    UINT_32             pipe,       ///< [in] pipe number
++    UINT_32             bankSwizzle,///< [in] bank swizzle
++    UINT_32             pipeSwizzle,///< [in] pipe swizzle
++    UINT_32             tileSlices, ///< [in] slices in a micro tile
++    ADDR_TILEINFO*      pTileInfo,  ///< [in] bank structure. **All fields to be valid on entry**
++    CoordFromBankPipe*  pOutput     ///< [out] pointer to extracted x/y bits
++    ) const
++{
++    UINT_32 yBit3 = 0;
++    UINT_32 yBit4 = 0;
++    UINT_32 yBit5 = 0;
++    UINT_32 yBit6 = 0;
++
++    UINT_32 xBit3 = 0;
++    UINT_32 xBit4 = 0;
++    UINT_32 xBit5 = 0;
++
++    UINT_32 tileSplitRotation;
++
++    UINT_32 numPipes = HwlGetPipes(pTileInfo);
++
++    UINT_32 bankRotation = ComputeBankRotation(tileMode,
++                                               pTileInfo->banks, numPipes);
++
++    UINT_32 pipeRotation = ComputePipeRotation(tileMode, numPipes);
++
++    UINT_32 xBit = x / (MicroTileWidth * pTileInfo->bankWidth * numPipes);
++    UINT_32 yBit = y / (MicroTileHeight * pTileInfo->bankHeight);
++
++    //calculate the bank and pipe before rotation and swizzle
++
++    switch (tileMode)
++    {
++        case ADDR_TM_2D_TILED_THIN1:  //fall through
++        case ADDR_TM_2D_TILED_THICK:  //fall through
++        case ADDR_TM_2D_TILED_XTHICK: //fall through
++        case ADDR_TM_3D_TILED_THIN1:  //fall through
++        case ADDR_TM_3D_TILED_THICK:  //fall through
++        case ADDR_TM_3D_TILED_XTHICK:
++            tileSplitRotation = ((pTileInfo->banks / 2) + 1);
++            break;
++        default:
++            tileSplitRotation =  0;
++            break;
++    }
++
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    bank ^= tileSplitRotation * tileSlices;
++    if (pipeRotation == 0)
++    {
++        bank ^= bankRotation * (slice / microTileThickness) + bankSwizzle;
++        bank %= pTileInfo->banks;
++        pipe ^= pipeSwizzle;
++    }
++    else
++    {
++        bank ^= bankRotation * (slice / microTileThickness) / numPipes + bankSwizzle;
++        bank %= pTileInfo->banks;
++        pipe ^= pipeRotation * (slice / microTileThickness) + pipeSwizzle;
++    }
++
++    if (pTileInfo->macroAspectRatio == 1)
++    {
++        switch (pTileInfo->banks)
++        {
++            case 2:
++                yBit3 = _BIT(bank, 0) ^ _BIT(xBit,0);
++                break;
++            case 4:
++                yBit4 = _BIT(bank, 0) ^ _BIT(xBit,0);
++                yBit3 = _BIT(bank, 1) ^ _BIT(xBit,1);
++                break;
++            case 8:
++                yBit3 = _BIT(bank, 2) ^ _BIT(xBit,2);
++                yBit5 = _BIT(bank, 0) ^ _BIT(xBit,0);
++                yBit4 = _BIT(bank, 1) ^ _BIT(xBit,1) ^ yBit5;
++                break;
++            case 16:
++                yBit3 = _BIT(bank, 3) ^ _BIT(xBit, 3);
++                yBit4 = _BIT(bank, 2) ^ _BIT(xBit, 2);
++                yBit6 = _BIT(bank, 0) ^ _BIT(xBit, 0);
++                yBit5 = _BIT(bank, 1) ^ _BIT(xBit, 1) ^ yBit6;
++                break;
++            default:
++                break;
++        }
++
++    }
++    else if (pTileInfo->macroAspectRatio == 2)
++    {
++        switch (pTileInfo->banks)
++        {
++            case 2: //xBit3 = yBit3^b0
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit,0);
++                break;
++            case 4: //xBit3=yBit4^b0; yBit3=xBit4^b1
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit,1);
++                yBit3 = _BIT(bank, 1) ^ _BIT(xBit,1);
++                break;
++            case 8: //xBit4, xBit5, yBit5 are known
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit,2);
++                yBit3 = _BIT(bank, 2) ^ _BIT(xBit,2);
++                yBit4 = _BIT(bank, 1) ^ _BIT(xBit,1) ^ _BIT(yBit, 2);
++                break;
++            case 16://x4,x5,x6,y6 are known
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit, 3); //x3 = y6 ^ b0
++                yBit3 = _BIT(bank, 3) ^ _BIT(xBit, 3); //y3 = x6 ^ b3
++                yBit4 = _BIT(bank, 2) ^ _BIT(xBit, 2); //y4 = x5 ^ b2
++                yBit5 = _BIT(bank, 1) ^ _BIT(xBit, 1) ^ _BIT(yBit, 3); //y5=x4^y6^b1
++                break;
++            default:
++                break;
++        }
++    }
++    else if (pTileInfo->macroAspectRatio == 4)
++    {
++        switch (pTileInfo->banks)
++        {
++            case 4: //yBit3, yBit4
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit,1);
++                xBit4 = _BIT(bank, 1) ^ _BIT(yBit,0);
++                break;
++            case 8: //xBit5, yBit4, yBit5
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit,2);
++                yBit3 = _BIT(bank, 2) ^ _BIT(xBit,2);
++                xBit4 = _BIT(bank, 1) ^ _BIT(yBit,1) ^  _BIT(yBit,2);
++                break;
++            case 16: //xBit5, xBit6, yBit5, yBit6
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit, 3);//x3 = b0 ^ y6
++                xBit4 = _BIT(bank, 1) ^ _BIT(yBit, 2) ^ _BIT(yBit, 3);//x4 = b1 ^ y5 ^ y6;
++                yBit3 = _BIT(bank, 3) ^ _BIT(xBit, 3); //y3 = b3 ^ x6;
++                yBit4 = _BIT(bank, 2) ^ _BIT(xBit, 2); //y4 = b2 ^ x5;
++                break;
++            default:
++                break;
++        }
++    }
++    else if (pTileInfo->macroAspectRatio == 8)
++    {
++        switch (pTileInfo->banks)
++        {
++            case 8: //yBit3, yBit4, yBit5
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit,2); //x3 = b0 ^ y5;
++                xBit4 = _BIT(bank, 1) ^ _BIT(yBit,1) ^ _BIT(yBit, 2);//x4 = b1 ^ y4 ^ y5;
++                xBit5 = _BIT(bank, 2) ^ _BIT(yBit,0);
++                break;
++            case 16: //xBit6, yBit4, yBit5, yBit6
++                xBit3 = _BIT(bank, 0) ^ _BIT(yBit, 3);//x3 = y6 ^ b0
++                xBit4 = _BIT(bank, 1) ^ _BIT(yBit, 2) ^ _BIT(yBit, 3);//x4 = y5 ^ y6 ^ b1
++                xBit5 = _BIT(bank, 2) ^ _BIT(yBit, 1);//x5 = y4 ^ b2
++                yBit3 = _BIT(bank, 3) ^ _BIT(xBit, 3); //y3 = x6 ^ b3
++                break;
++            default:
++                break;
++        }
++    }
++
++    pOutput->xBits = xBit;
++    pOutput->yBits = yBit;
++
++    pOutput->xBit3 = xBit3;
++    pOutput->xBit4 = xBit4;
++    pOutput->xBit5 = xBit5;
++    pOutput->yBit3 = yBit3;
++    pOutput->yBit4 = yBit4;
++    pOutput->yBit5 = yBit5;
++    pOutput->yBit6 = yBit6;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlExtractBankPipeSwizzle
++*   @brief
++*       Entry of EgBasedAddrLib ExtractBankPipeSwizzle
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlExtractBankPipeSwizzle(
++    const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT*  pIn,   ///< [in] input structure
++    ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*       pOut   ///< [out] output structure
++    ) const
++{
++    ExtractBankPipeSwizzle(pIn->base256b,
++                           pIn->pTileInfo,
++                           &pOut->bankSwizzle,
++                           &pOut->pipeSwizzle);
++
++    return ADDR_OK;
++}
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlCombineBankPipeSwizzle
++*   @brief
++*       Combine bank/pipe swizzle
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlCombineBankPipeSwizzle(
++    UINT_32         bankSwizzle,    ///< [in] bank swizzle
++    UINT_32         pipeSwizzle,    ///< [in] pipe swizzle
++    ADDR_TILEINFO*  pTileInfo,      ///< [in] tile info
++    UINT_64         baseAddr,       ///< [in] base address
++    UINT_32*        pTileSwizzle    ///< [out] combined swizzle
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    if (pTileSwizzle)
++    {
++        *pTileSwizzle = GetBankPipeSwizzle(bankSwizzle, pipeSwizzle, baseAddr, pTileInfo);
++    }
++    else
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeBaseSwizzle
++*   @brief
++*       Compute base swizzle
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeBaseSwizzle(
++    const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
++    ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut
++    ) const
++{
++    UINT_32 bankSwizzle = 0;
++    UINT_32 pipeSwizzle = 0;
++    ADDR_TILEINFO* pTileInfo = pIn->pTileInfo;
++
++    ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
++    ADDR_ASSERT(pIn->pTileInfo);
++
++    /// This is a legacy misreading of h/w doc, use it as it doesn't hurt.
++    static const UINT_8 bankRotationArray[4][16] = {
++        { 0, 0,  0, 0,  0, 0,  0, 0, 0,  0, 0,  0, 0,  0, 0, 0 }, // ADDR_SURF_2_BANK
++        { 0, 1,  2, 3,  0, 0,  0, 0, 0,  0, 0,  0, 0,  0, 0, 0 }, // ADDR_SURF_4_BANK
++        { 0, 3,  6, 1,  4, 7,  2, 5, 0,  0, 0,  0, 0,  0, 0, 0 }, // ADDR_SURF_8_BANK
++        { 0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9 }, // ADDR_SURF_16_BANK
++    };
++
++    UINT_32 pipes = HwlGetPipes(pTileInfo);
++    UINT_32 banks = pTileInfo ? pTileInfo->banks : 2;
++    UINT_32 hwNumBanks;
++
++    // Uses less bank swizzle bits
++    if (pIn->option.reduceBankBit && banks > 2)
++    {
++        banks >>= 1;
++    }
++
++    switch (banks)
++    {
++        case 2:
++            hwNumBanks = 0;
++            break;
++        case 4:
++            hwNumBanks = 1;
++            break;
++        case 8:
++            hwNumBanks = 2;
++            break;
++        case 16:
++            hwNumBanks = 3;
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++            hwNumBanks = 0;
++            break;
++    }
++
++    if (pIn->option.genOption == ADDR_SWIZZLE_GEN_LINEAR)
++    {
++        bankSwizzle = pIn->surfIndex & (banks - 1);
++    }
++    else // (pIn->option.genOption == ADDR_SWIZZLE_GEN_DEFAULT)
++    {
++        bankSwizzle = bankRotationArray[hwNumBanks][pIn->surfIndex & (banks - 1)];
++    }
++
++    if (IsMacro3dTiled(pIn->tileMode))
++    {
++        pipeSwizzle = pIn->surfIndex & (HwlGetPipes(pTileInfo) - 1);
++    }
++
++    return HwlCombineBankPipeSwizzle(bankSwizzle, pipeSwizzle, pTileInfo, 0, &pOut->tileSwizzle);
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ExtractBankPipeSwizzle
++*   @brief
++*       Extract bank/pipe swizzle from base256b
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::ExtractBankPipeSwizzle(
++    UINT_32         base256b,       ///< [in] input base256b register value
++    ADDR_TILEINFO*  pTileInfo,      ///< [in] 2D tile parameters. Client must provide all data
++    UINT_32*        pBankSwizzle,   ///< [out] bank swizzle
++    UINT_32*        pPipeSwizzle    ///< [out] pipe swizzle
++    ) const
++{
++    UINT_32 bankSwizzle = 0;
++    UINT_32 pipeSwizzle = 0;
++
++    if (base256b != 0)
++    {
++        UINT_32 numPipes        = HwlGetPipes(pTileInfo);
++        UINT_32 bankBits        = QLog2(pTileInfo->banks);
++        UINT_32 pipeBits        = QLog2(numPipes);
++        UINT_32 groupBytes      = m_pipeInterleaveBytes;
++        UINT_32 bankInterleave  = m_bankInterleave;
++
++        pipeSwizzle =
++            (base256b / (groupBytes >> 8)) & ((1<<pipeBits)-1);
++
++        bankSwizzle =
++            (base256b / (groupBytes >> 8) / numPipes / bankInterleave) & ((1 << bankBits) - 1);
++    }
++
++    *pPipeSwizzle = pipeSwizzle;
++    *pBankSwizzle = bankSwizzle;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::GetBankPipeSwizzle
++*   @brief
++*       Combine bank/pipe swizzle
++*   @return
++*       Base256b bits (only filled bank/pipe bits)
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::GetBankPipeSwizzle(
++    UINT_32         bankSwizzle,    ///< [in] bank swizzle
++    UINT_32         pipeSwizzle,    ///< [in] pipe swizzle
++    UINT_64         baseAddr,       ///< [in] base address
++    ADDR_TILEINFO*  pTileInfo       ///< [in] tile info
++    ) const
++{
++    UINT_32 pipeBits = QLog2(HwlGetPipes(pTileInfo));
++    UINT_32 bankInterleaveBits = QLog2(m_bankInterleave);
++    UINT_32 tileSwizzle = pipeSwizzle + ((bankSwizzle << bankInterleaveBits) << pipeBits);
++
++    baseAddr ^= tileSwizzle * m_pipeInterleaveBytes;
++    baseAddr >>= 8;
++
++    return static_cast<UINT_32>(baseAddr);
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeSliceTileSwizzle
++*   @brief
++*       Compute cubemap/3d texture faces/slices tile swizzle
++*   @return
++*       Tile swizzle
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputeSliceTileSwizzle(
++    AddrTileMode        tileMode,       ///< [in] Tile mode
++    UINT_32             baseSwizzle,    ///< [in] Base swizzle
++    UINT_32             slice,          ///< [in] Slice index, Cubemap face index, 0 means +X
++    UINT_64             baseAddr,       ///< [in] Base address
++    ADDR_TILEINFO* pTileInfo       ///< [in] Bank structure
++    ) const
++{
++    UINT_32 tileSwizzle = 0;
++
++    if (IsMacroTiled(tileMode)) // Swizzle only for macro tile mode
++    {
++        UINT_32 firstSlice = slice / ComputeSurfaceThickness(tileMode);
++
++        UINT_32 numPipes = HwlGetPipes(pTileInfo);
++        UINT_32 numBanks = pTileInfo->banks;
++
++        UINT_32 pipeRotation;
++        UINT_32 bankRotation;
++
++        UINT_32 bankSwizzle = 0;
++        UINT_32 pipeSwizzle = 0;
++
++        pipeRotation = ComputePipeRotation(tileMode, numPipes);
++        bankRotation = ComputeBankRotation(tileMode, numBanks, numPipes);
++
++        if (baseSwizzle != 0)
++        {
++            ExtractBankPipeSwizzle(baseSwizzle,
++                                   pTileInfo,
++                                   &bankSwizzle,
++                                   &pipeSwizzle);
++        }
++
++        if (pipeRotation == 0) //2D mode
++        {
++            bankSwizzle += firstSlice * bankRotation;
++            bankSwizzle %= numBanks;
++        }
++        else //3D mode
++        {
++            pipeSwizzle += firstSlice * pipeRotation;
++            pipeSwizzle %= numPipes;
++            bankSwizzle += firstSlice * bankRotation / numPipes;
++            bankSwizzle %= numBanks;
++        }
++
++        tileSwizzle = GetBankPipeSwizzle(bankSwizzle,
++                                         pipeSwizzle,
++                                         baseAddr,
++                                         pTileInfo);
++    }
++
++    return tileSwizzle;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeQbStereoRightSwizzle
++*
++*   @brief
++*       Compute right eye swizzle
++*   @return
++*       swizzle
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::HwlComputeQbStereoRightSwizzle(
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pInfo  ///< [in] Surface info, must be valid
++    ) const
++{
++    UINT_32 bankBits    = 0;
++    UINT_32 swizzle     = 0;
++
++    // The assumption is default swizzle for left eye is 0
++    if (IsMacroTiled(pInfo->tileMode) && pInfo->pStereoInfo && pInfo->pTileInfo)
++    {
++        bankBits = ComputeBankFromCoord(0, pInfo->height, 0,
++                                        pInfo->tileMode, 0, 0, pInfo->pTileInfo);
++
++        if (bankBits)
++        {
++            HwlCombineBankPipeSwizzle(bankBits, 0, pInfo->pTileInfo, 0, &swizzle);
++        }
++    }
++
++    return swizzle;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeBankFromCoord
++*
++*   @brief
++*       Compute bank number from coordinates
++*   @return
++*       Bank number
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputeBankFromCoord(
++    UINT_32         x,              ///< [in] x coordinate
++    UINT_32         y,              ///< [in] y coordinate
++    UINT_32         slice,          ///< [in] slice index
++    AddrTileMode    tileMode,       ///< [in] tile mode
++    UINT_32         bankSwizzle,    ///< [in] bank swizzle
++    UINT_32         tileSplitSlice, ///< [in] If the size of the pixel offset is larger than the
++                                    ///  tile split size, then the pixel will be moved to a separate
++                                    ///  slice. This value equals pixelOffset / tileSplitBytes
++                                    ///  in this case. Otherwise this is 0.
++    ADDR_TILEINFO*  pTileInfo       ///< [in] tile info
++    ) const
++{
++    UINT_32 pipes = HwlGetPipes(pTileInfo);
++    UINT_32 bankBit0 = 0;
++    UINT_32 bankBit1 = 0;
++    UINT_32 bankBit2 = 0;
++    UINT_32 bankBit3 = 0;
++    UINT_32 sliceRotation;
++    UINT_32 tileSplitRotation;
++    UINT_32 bank;
++    UINT_32 numBanks    = pTileInfo->banks;
++    UINT_32 bankWidth   = pTileInfo->bankWidth;
++    UINT_32 bankHeight  = pTileInfo->bankHeight;
++
++    UINT_32 tx = x / MicroTileWidth / (bankWidth * pipes);
++    UINT_32 ty = y / MicroTileHeight / bankHeight;
++
++    UINT_32 x3 = _BIT(tx,0);
++    UINT_32 x4 = _BIT(tx,1);
++    UINT_32 x5 = _BIT(tx,2);
++    UINT_32 x6 = _BIT(tx,3);
++    UINT_32 y3 = _BIT(ty,0);
++    UINT_32 y4 = _BIT(ty,1);
++    UINT_32 y5 = _BIT(ty,2);
++    UINT_32 y6 = _BIT(ty,3);
++
++    switch (numBanks)
++    {
++        case 16:
++            bankBit0 = x3 ^ y6;
++            bankBit1 = x4 ^ y5 ^ y6;
++            bankBit2 = x5 ^ y4;
++            bankBit3 = x6 ^ y3;
++            break;
++        case 8:
++            bankBit0 = x3 ^ y5;
++            bankBit1 = x4 ^ y4 ^ y5;
++            bankBit2 = x5 ^ y3;
++            break;
++        case 4:
++            bankBit0 = x3 ^ y4;
++            bankBit1 = x4 ^ y3;
++            break;
++        case 2:
++            bankBit0 = x3 ^ y3;
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++            break;
++    }
++
++    bank = bankBit0 | (bankBit1 << 1) | (bankBit2 << 2) | (bankBit3 << 3);
++
++    //Bits2Number(4, bankBit3, bankBit2, bankBit1, bankBit0);
++
++    bank = HwlPreAdjustBank((x / MicroTileWidth), bank, pTileInfo);
++    //
++    // Compute bank rotation for the slice.
++    //
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    switch (tileMode)
++    {
++        case ADDR_TM_2D_TILED_THIN1:  // fall through
++        case ADDR_TM_2D_TILED_THICK:  // fall through
++        case ADDR_TM_2D_TILED_XTHICK:
++            sliceRotation = ((numBanks / 2) - 1) * (slice / microTileThickness);
++            break;
++        case ADDR_TM_3D_TILED_THIN1:  // fall through
++        case ADDR_TM_3D_TILED_THICK:  // fall through
++        case ADDR_TM_3D_TILED_XTHICK:
++            sliceRotation =
++                Max(1u, (pipes / 2) - 1) * (slice / microTileThickness) / pipes;
++            break;
++        default:
++            sliceRotation =  0;
++            break;
++    }
++
++
++    //
++    // Compute bank rotation for the tile split slice.
++    //
++    // The sample slice will be non-zero if samples must be split across multiple slices.
++    // This situation arises when the micro tile size multiplied yBit the number of samples exceeds
++    // the split size (set in GB_ADDR_CONFIG).
++    //
++    switch (tileMode)
++    {
++        case ADDR_TM_2D_TILED_THIN1: //fall through
++        case ADDR_TM_3D_TILED_THIN1: //fall through
++        case ADDR_TM_PRT_2D_TILED_THIN1: //fall through
++        case ADDR_TM_PRT_3D_TILED_THIN1: //fall through
++            tileSplitRotation = ((numBanks / 2) + 1) * tileSplitSlice;
++            break;
++        default:
++            tileSplitRotation =  0;
++            break;
++    }
++
++    //
++    // Apply bank rotation for the slice and tile split slice.
++    //
++    bank ^= bankSwizzle + sliceRotation;
++    bank ^= tileSplitRotation;
++
++    bank &= (numBanks - 1);
++
++    return bank;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeBankFromAddr
++*
++*   @brief
++*       Compute the bank number from an address
++*   @return
++*       Bank number
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputeBankFromAddr(
++    UINT_64 addr,       ///< [in] address
++    UINT_32 numBanks,   ///< [in] number of banks
++    UINT_32 numPipes    ///< [in] number of pipes
++    ) const
++{
++    UINT_32 bank;
++
++    //
++    // The LSBs of the address are arranged as follows:
++    //   bank | bankInterleave | pipe | pipeInterleave
++    //
++    // To get the bank number, shift off the pipe interleave, pipe, and bank interlave bits and
++    // mask the bank bits.
++    //
++    bank = static_cast<UINT_32>(
++        (addr >> Log2(m_pipeInterleaveBytes * numPipes * m_bankInterleave)) &
++        (numBanks - 1)
++        );
++
++    return bank;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputePipeRotation
++*
++*   @brief
++*       Compute pipe rotation value
++*   @return
++*       Pipe rotation
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputePipeRotation(
++    AddrTileMode tileMode,  ///< [in] tile mode
++    UINT_32      numPipes   ///< [in] number of pipes
++    ) const
++{
++   UINT_32 rotation;
++
++    switch (tileMode)
++    {
++        case ADDR_TM_3D_TILED_THIN1:        //fall through
++        case ADDR_TM_3D_TILED_THICK:        //fall through
++        case ADDR_TM_3D_TILED_XTHICK:       //fall through
++        case ADDR_TM_PRT_3D_TILED_THIN1:    //fall through
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            rotation = (numPipes < 4) ? 1 : (numPipes / 2 - 1);
++            break;
++        default:
++            rotation = 0;
++    }
++
++    return rotation;
++}
++
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeBankRotation
++*
++*   @brief
++*       Compute bank rotation value
++*   @return
++*       Bank rotation
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputeBankRotation(
++    AddrTileMode tileMode,  ///< [in] tile mode
++    UINT_32      numBanks,  ///< [in] number of banks
++    UINT_32      numPipes   ///< [in] number of pipes
++    ) const
++{
++    UINT_32 rotation;
++
++    switch (tileMode)
++    {
++        case ADDR_TM_2D_TILED_THIN1: // fall through
++        case ADDR_TM_2D_TILED_THICK: // fall through
++        case ADDR_TM_2D_TILED_XTHICK:
++        case ADDR_TM_PRT_2D_TILED_THIN1:
++        case ADDR_TM_PRT_2D_TILED_THICK:
++            // Rotate banks per Z-slice yBit 1 for 4-bank or 3 for 8-bank
++            rotation =  numBanks / 2 - 1;
++            break;
++        case ADDR_TM_3D_TILED_THIN1: // fall through
++        case ADDR_TM_3D_TILED_THICK: // fall through
++        case ADDR_TM_3D_TILED_XTHICK:
++        case ADDR_TM_PRT_3D_TILED_THIN1:
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            rotation = (numPipes < 4) ? 1 : (numPipes / 2 - 1);    // rotate pipes & banks
++            break;
++        default:
++            rotation = 0;
++    }
++
++    return rotation;
++}
++
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeHtileBytes
++*
++*   @brief
++*       Compute htile size in bytes
++*
++*   @return
++*       Htile size in bytes
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::ComputeHtileBytes(
++    UINT_32 pitch,        ///< [in] pitch
++    UINT_32 height,       ///< [in] height
++    UINT_32 bpp,          ///< [in] bits per pixel
++    BOOL_32 isLinear,     ///< [in] if it is linear mode
++    UINT_32 numSlices,    ///< [in] number of slices
++    UINT_64* sliceBytes,  ///< [out] bytes per slice
++    UINT_32 baseAlign     ///< [in] base alignments
++    ) const
++{
++    UINT_64 surfBytes;
++
++    const UINT_64 HtileCacheLineSize = BITS_TO_BYTES(HtileCacheBits);
++
++    *sliceBytes = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp / 64);
++
++    if (m_configFlags.useHtileSliceAlign)
++    {
++        // Align the sliceSize to htilecachelinesize * pipes at first
++        *sliceBytes = PowTwoAlign(*sliceBytes, HtileCacheLineSize * m_pipes);
++        surfBytes  = *sliceBytes * numSlices;
++    }
++    else
++    {
++        // Align the surfSize to htilecachelinesize * pipes at last
++        surfBytes  = *sliceBytes * numSlices;
++        surfBytes  = PowTwoAlign(surfBytes, HtileCacheLineSize * m_pipes);
++    }
++
++    return surfBytes;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::DispatchComputeFmaskInfo
++*
++*   @brief
++*       Compute fmask sizes include padded pitch, height, slices, total size in bytes,
++*       meanwhile output suitable tile mode and alignments as well. Results are returned
++*       through output parameters.
++*
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::DispatchComputeFmaskInfo(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,   ///< [in] input structure
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut)  ///< [out] output structure
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    ADDR_COMPUTE_SURFACE_INFO_INPUT  surfIn     = {0};
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT surfOut    = {0};
++
++    // Setup input structure
++    surfIn.tileMode          = pIn->tileMode;
++    surfIn.width             = pIn->pitch;
++    surfIn.height            = pIn->height;
++    surfIn.numSlices         = pIn->numSlices;
++    surfIn.pTileInfo         = pIn->pTileInfo;
++    surfIn.tileType          = ADDR_NON_DISPLAYABLE;
++    surfIn.flags.fmask       = 1;
++
++    // Setup output structure
++    surfOut.pTileInfo       = pOut->pTileInfo;
++
++    // Setup hwl specific fields
++    HwlFmaskPreThunkSurfInfo(pIn, pOut, &surfIn, &surfOut);
++
++    surfIn.bpp = HwlComputeFmaskBits(pIn, &surfIn.numSamples);
++
++    // ComputeSurfaceInfo needs numSamples in surfOut as surface routines need adjusted numSamples
++    surfOut.numSamples = surfIn.numSamples;
++
++    retCode = HwlComputeSurfaceInfo(&surfIn, &surfOut);
++
++    // Save bpp field for surface dump support
++    surfOut.bpp = surfIn.bpp;
++
++    if (retCode == ADDR_OK)
++    {
++        pOut->bpp               = surfOut.bpp;
++        pOut->pitch             = surfOut.pitch;
++        pOut->height            = surfOut.height;
++        pOut->numSlices         = surfOut.depth;
++        pOut->fmaskBytes        = surfOut.surfSize;
++        pOut->baseAlign         = surfOut.baseAlign;
++        pOut->pitchAlign        = surfOut.pitchAlign;
++        pOut->heightAlign       = surfOut.heightAlign;
++
++        if (surfOut.depth > 1)
++        {
++            // For fmask, expNumSlices is stored in depth.
++            pOut->sliceSize = surfOut.surfSize / surfOut.depth;
++        }
++        else
++        {
++            pOut->sliceSize = surfOut.surfSize;
++        }
++
++        // Save numSamples field for surface dump support
++        pOut->numSamples        = surfOut.numSamples;
++
++        HwlFmaskPostThunkSurfInfo(&surfOut, pOut);
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlFmaskSurfaceInfo
++*   @brief
++*       Entry of EgBasedAddrLib ComputeFmaskInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeFmaskInfo(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,   ///< [in] input structure
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut   ///< [out] output structure
++    )
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    ADDR_TILEINFO tileInfo = {0};
++
++    // Use internal tile info if pOut does not have a valid pTileInfo
++    if (pOut->pTileInfo == NULL)
++    {
++        pOut->pTileInfo = &tileInfo;
++    }
++
++    retCode = DispatchComputeFmaskInfo(pIn, pOut);
++
++    if (retCode == ADDR_OK)
++    {
++        pOut->tileIndex =
++            HwlPostCheckTileIndex(pOut->pTileInfo, pIn->tileMode, ADDR_NON_DISPLAYABLE,
++                                  pOut->tileIndex);
++    }
++
++    // Resets pTileInfo to NULL if the internal tile info is used
++    if (pOut->pTileInfo == &tileInfo)
++    {
++        pOut->pTileInfo = NULL;
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeFmaskAddrFromCoord
++*   @brief
++*       Entry of EgBasedAddrLib ComputeFmaskAddrFromCoord
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeFmaskAddrFromCoord(
++    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++#if ADDR_AM_BUILD
++    if ((pIn->x > pIn->pitch)               ||
++        (pIn->y > pIn->height)              ||
++        (pIn->numSamples > m_maxSamples)    ||
++        (pIn->sample >= m_maxSamples))
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++    else
++    {
++        pOut->addr = DispatchComputeFmaskAddrFromCoord(pIn, pOut);
++    }
++#endif
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeFmaskCoordFromAddr
++*   @brief
++*       Entry of EgBasedAddrLib ComputeFmaskCoordFromAddr
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeFmaskCoordFromAddr(
++    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++#if ADDR_AM_BUILD
++    if ((pIn->bitPosition >= 8) ||
++        (pIn->numSamples > m_maxSamples))
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++    else
++    {
++        DispatchComputeFmaskCoordFromAddr(pIn, pOut);
++    }
++#endif
++
++    return retCode;
++}
++
++#if ADDR_AM_BUILD
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::DispatchComputeFmaskAddrFromCoord
++*
++*   @brief
++*       Computes the FMASK address and bit position from a coordinate.
++*   @return
++*       The byte address
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::DispatchComputeFmaskAddrFromCoord(
++    const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    UINT_32             x                 = pIn->x;
++    UINT_32             y                 = pIn->y;
++    UINT_32             slice             = pIn->slice;
++    UINT_32             sample            = pIn->sample;
++    UINT_32             plane             = pIn->plane;
++    UINT_32             pitch             = pIn->pitch;
++    UINT_32             height            = pIn->height;
++    UINT_32             numSamples        = pIn->numSamples;
++    AddrTileMode        tileMode          = pIn->tileMode;
++    BOOL_32             ignoreSE          = pIn->ignoreSE;
++    ADDR_TILEINFO*      pTileInfo         = pIn->pTileInfo;
++    BOOL_32             resolved          = pIn->resolved;
++
++    UINT_32* pBitPosition = &pOut->bitPosition;
++    UINT_64 addr          = 0;
++
++    ADDR_ASSERT(numSamples > 1);
++    ADDR_ASSERT(ComputeSurfaceThickness(tileMode) == 1);
++
++    switch (tileMode)
++    {
++        case ADDR_TM_1D_TILED_THIN1:
++            addr = ComputeFmaskAddrFromCoordMicroTiled(x,
++                                                       y,
++                                                       slice,
++                                                       sample,
++                                                       plane,
++                                                       pitch,
++                                                       height,
++                                                       numSamples,
++                                                       tileMode,
++                                                       resolved,
++                                                       pBitPosition);
++            break;
++        case ADDR_TM_2D_TILED_THIN1: //fall through
++        case ADDR_TM_3D_TILED_THIN1:
++            UINT_32 pipeSwizzle;
++            UINT_32 bankSwizzle;
++
++            if (m_configFlags.useCombinedSwizzle)
++            {
++                ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
++                                       &bankSwizzle, &pipeSwizzle);
++            }
++            else
++            {
++                pipeSwizzle = pIn->pipeSwizzle;
++                bankSwizzle = pIn->bankSwizzle;
++            }
++
++            addr = ComputeFmaskAddrFromCoordMacroTiled(x,
++                                                       y,
++                                                       slice,
++                                                       sample,
++                                                       plane,
++                                                       pitch,
++                                                       height,
++                                                       numSamples,
++                                                       tileMode,
++                                                       pipeSwizzle,
++                                                       bankSwizzle,
++                                                       ignoreSE,
++                                                       pTileInfo,
++                                                       resolved,
++                                                       pBitPosition);
++            break;
++        default:
++            *pBitPosition = 0;
++            break;
++    }
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeFmaskAddrFromCoordMicroTiled
++*
++*   @brief
++*       Computes the FMASK address and bit position from a coordinate for 1D tilied (micro
++*       tiled)
++*   @return
++*       The byte address
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::ComputeFmaskAddrFromCoordMicroTiled(
++    UINT_32             x,              ///< [in] x coordinate
++    UINT_32             y,              ///< [in] y coordinate
++    UINT_32             slice,          ///< [in] slice index
++    UINT_32             sample,         ///< [in] sample number
++    UINT_32             plane,          ///< [in] plane number
++    UINT_32             pitch,          ///< [in] surface pitch in pixels
++    UINT_32             height,         ///< [in] surface height in pixels
++    UINT_32             numSamples,     ///< [in] number of samples
++    AddrTileMode        tileMode,       ///< [in] tile mode
++    BOOL_32             resolved,       ///< [in] TRUE if this is for resolved fmask
++    UINT_32*            pBitPosition    ///< [out] pointer to returned bit position
++    ) const
++{
++    UINT_64 addr = 0;
++    UINT_32 effectiveBpp;
++    UINT_32 effectiveSamples;
++
++    //
++    // 2xAA use the same layout as 4xAA
++    //
++    if (numSamples == 2)
++    {
++        numSamples = 4;
++    }
++
++    //
++    // Compute the number of planes.
++    //
++    if (!resolved)
++    {
++        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);;
++        effectiveBpp = numSamples;
++
++        //
++        // Compute the address just like a color surface with numSamples bits per element and
++        // numPlanes samples.
++        //
++        addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
++                                                     y,
++                                                     slice,
++                                                     plane, // sample
++                                                     effectiveBpp,
++                                                     pitch,
++                                                     height,
++                                                     effectiveSamples,
++                                                     tileMode,
++                                                     ADDR_NON_DISPLAYABLE,
++                                                     FALSE,
++                                                     pBitPosition);
++
++        //
++        // Compute the real bit position. Each (sample, plane) is stored with one bit per sample.
++        //
++
++        //
++        // Compute the pixel index with in the micro tile
++        //
++        UINT_32 pixelIndex = ComputePixelIndexWithinMicroTile(x % 8,
++                                                              y % 8,
++                                                              slice,
++                                                              1,
++                                                              tileMode,
++                                                              ADDR_NON_DISPLAYABLE);
++
++        *pBitPosition = ((pixelIndex * numSamples) + sample) & (BITS_PER_BYTE-1);
++
++        UINT_64 bitAddr = BYTES_TO_BITS(addr) + *pBitPosition;
++
++        addr = bitAddr / 8;
++    }
++    else
++    {
++        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
++        effectiveSamples = 1;
++
++        //
++        // Compute the address just like a color surface with numSamples bits per element and
++        // numPlanes samples.
++        //
++        addr = ComputeSurfaceAddrFromCoordMicroTiled(x,
++                                                     y,
++                                                     slice,
++                                                     sample,
++                                                     effectiveBpp,
++                                                     pitch,
++                                                     height,
++                                                     effectiveSamples,
++                                                     tileMode,
++                                                     ADDR_NON_DISPLAYABLE,
++                                                     TRUE,
++                                                     pBitPosition);
++    }
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeFmaskAddrFromCoordMacroTiled
++*
++*   @brief
++*       Computes the FMASK address and bit position from a coordinate for 2D tilied (macro
++*       tiled)
++*   @return
++*       The byte address
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::ComputeFmaskAddrFromCoordMacroTiled(
++    UINT_32             x,              ///< [in] x coordinate
++    UINT_32             y,              ///< [in] y coordinate
++    UINT_32             slice,          ///< [in] slice index
++    UINT_32             sample,         ///< [in] sample number
++    UINT_32             plane,          ///< [in] plane number
++    UINT_32             pitch,          ///< [in] surface pitch in pixels
++    UINT_32             height,         ///< [in] surface height in pixels
++    UINT_32             numSamples,     ///< [in] number of samples
++    AddrTileMode        tileMode,       ///< [in] tile mode
++    UINT_32             pipeSwizzle,    ///< [in] pipe swizzle
++    UINT_32             bankSwizzle,    ///< [in] bank swizzle
++    BOOL_32             ignoreSE,       ///< [in] TRUE if ignore shader engine
++    ADDR_TILEINFO*      pTileInfo,      ///< [in] bank structure.**All fields to be valid on entry**
++    BOOL_32             resolved,       ///< [in] TRUE if this is for resolved fmask
++    UINT_32*            pBitPosition    ///< [out] pointer to returned bit position
++    ) const
++{
++    UINT_64 addr = 0;
++    UINT_32 effectiveBpp;
++    UINT_32 effectiveSamples;
++
++    //
++    // 2xAA use the same layout as 4xAA
++    //
++    if (numSamples == 2)
++    {
++        numSamples = 4;
++    }
++
++    //
++    // Compute the number of planes.
++    //
++    if (!resolved)
++    {
++        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
++        effectiveBpp = numSamples;
++
++        //
++        // Compute the address just like a color surface with numSamples bits per element and
++        // numPlanes samples.
++        //
++        addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
++                                                     y,
++                                                     slice,
++                                                     plane, // sample
++                                                     effectiveBpp,
++                                                     pitch,
++                                                     height,
++                                                     effectiveSamples,
++                                                     tileMode,
++                                                     ADDR_NON_DISPLAYABLE,// isdisp
++                                                     ignoreSE,// ignore_shader
++                                                     FALSE,// depth_sample_order
++                                                     pipeSwizzle,
++                                                     bankSwizzle,
++                                                     pTileInfo,
++                                                     pBitPosition);
++
++        //
++        // Compute the real bit position. Each (sample, plane) is stored with one bit per sample.
++        //
++
++
++        //
++        // Compute the pixel index with in the micro tile
++        //
++        UINT_32 pixelIndex = ComputePixelIndexWithinMicroTile(x ,
++                                                              y ,
++                                                              slice,
++                                                              effectiveBpp,
++                                                              tileMode,
++                                                              ADDR_NON_DISPLAYABLE);
++
++        *pBitPosition = ((pixelIndex * numSamples) + sample) & (BITS_PER_BYTE-1);
++
++        UINT_64 bitAddr = BYTES_TO_BITS(addr) + *pBitPosition;
++
++        addr = bitAddr / 8;
++
++    }
++    else
++    {
++        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
++        effectiveSamples = 1;
++
++        //
++        // Compute the address just like a color surface with numSamples bits per element and
++        // numPlanes samples.
++        //
++        addr = ComputeSurfaceAddrFromCoordMacroTiled(x,
++                                                     y,
++                                                     slice,
++                                                     sample,
++                                                     effectiveBpp,
++                                                     pitch,
++                                                     height,
++                                                     effectiveSamples,
++                                                     tileMode,
++                                                     ADDR_NON_DISPLAYABLE,
++                                                     ignoreSE,
++                                                     TRUE,
++                                                     pipeSwizzle,
++                                                     bankSwizzle,
++                                                     pTileInfo,
++                                                     pBitPosition);
++    }
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeFmaskCoordFromAddrMicroTiled
++*
++*   @brief
++*       Compute (x,y,slice,sample,plane) coordinates from fmask address
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::ComputeFmaskCoordFromAddrMicroTiled(
++    UINT_64             addr,       ///< [in] byte address
++    UINT_32             bitPosition,///< [in] bit position
++    UINT_32             pitch,      ///< [in] pitch in pixels
++    UINT_32             height,     ///< [in] height in pixels
++    UINT_32             numSamples, ///< [in] number of samples (of color buffer)
++    AddrTileMode        tileMode,   ///< [in] tile mode
++    BOOL_32             resolved,   ///< [in] TRUE if it is resolved fmask
++    UINT_32*            pX,         ///< [out] X coord
++    UINT_32*            pY,         ///< [out] Y coord
++    UINT_32*            pSlice,     ///< [out] slice index
++    UINT_32*            pSample,    ///< [out] sample index
++    UINT_32*            pPlane      ///< [out] plane index
++    ) const
++{
++    UINT_32 effectiveBpp;
++    UINT_32 effectiveSamples;
++
++    // 2xAA use the same layout as 4xAA
++    if (numSamples == 2)
++    {
++        numSamples = 4;
++    }
++
++    if (!resolved)
++    {
++        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
++        effectiveBpp  = numSamples;
++
++        ComputeSurfaceCoordFromAddrMicroTiled(addr,
++                                              bitPosition,
++                                              effectiveBpp,
++                                              pitch,
++                                              height,
++                                              effectiveSamples,
++                                              tileMode,
++                                              0, // tileBase
++                                              0, // compBits
++                                              pX,
++                                              pY,
++                                              pSlice,
++                                              pPlane,
++                                              ADDR_NON_DISPLAYABLE, // microTileType
++                                              FALSE  // isDepthSampleOrder
++                                              );
++
++
++        if ( pSample )
++        {
++            *pSample = bitPosition % numSamples;
++        }
++    }
++    else
++    {
++        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
++        effectiveSamples = 1;
++
++        ComputeSurfaceCoordFromAddrMicroTiled(addr,
++                                              bitPosition,
++                                              effectiveBpp,
++                                              pitch,
++                                              height,
++                                              effectiveSamples,
++                                              tileMode,
++                                              0,     // tileBase
++                                              0,     // compBits
++                                              pX,
++                                              pY,
++                                              pSlice,
++                                              pSample,
++                                              ADDR_NON_DISPLAYABLE, // microTileType
++                                              TRUE   // isDepthSampleOrder
++                                              );
++    }
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeFmaskCoordFromAddrMacroTiled
++*
++*   @brief
++*       Compute (x,y,slice,sample,plane) coordinates from
++*       fmask address
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::ComputeFmaskCoordFromAddrMacroTiled(
++    UINT_64             addr,       ///< [in] byte address
++    UINT_32             bitPosition,///< [in] bit position
++    UINT_32             pitch,      ///< [in] pitch in pixels
++    UINT_32             height,     ///< [in] height in pixels
++    UINT_32             numSamples, ///< [in] number of samples (of color buffer)
++    AddrTileMode        tileMode,   ///< [in] tile mode
++    UINT_32             pipeSwizzle,///< [in] pipe swizzle
++    UINT_32             bankSwizzle,///< [in] bank swizzle
++    BOOL_32             ignoreSE,   ///< [in] TRUE if ignore shader engine
++    ADDR_TILEINFO*      pTileInfo,  ///< [in] bank structure. **All fields to be valid on entry**
++    BOOL_32             resolved,   ///< [in] TRUE if it is resolved fmask
++    UINT_32*            pX,         ///< [out] X coord
++    UINT_32*            pY,         ///< [out] Y coord
++    UINT_32*            pSlice,     ///< [out] slice index
++    UINT_32*            pSample,    ///< [out] sample index
++    UINT_32*            pPlane      ///< [out] plane index
++    ) const
++{
++    UINT_32 effectiveBpp;
++    UINT_32 effectiveSamples;
++
++    // 2xAA use the same layout as 4xAA
++    if (numSamples == 2)
++    {
++        numSamples = 4;
++    }
++
++    //
++    // Compute the number of planes.
++    //
++    if (!resolved)
++    {
++        effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
++        effectiveBpp  = numSamples;
++
++        ComputeSurfaceCoordFromAddrMacroTiled(addr,
++                                              bitPosition,
++                                              effectiveBpp,
++                                              pitch,
++                                              height,
++                                              effectiveSamples,
++                                              tileMode,
++                                              0, // No tileBase
++                                              0, // No compBits
++                                              ADDR_NON_DISPLAYABLE,
++                                              ignoreSE,
++                                              FALSE,
++                                              pipeSwizzle,
++                                              bankSwizzle,
++                                              pTileInfo,
++                                              pX,
++                                              pY,
++                                              pSlice,
++                                              pPlane);
++
++        if (pSample)
++        {
++            *pSample = bitPosition % numSamples;
++        }
++    }
++    else
++    {
++        effectiveBpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
++        effectiveSamples = 1;
++
++        ComputeSurfaceCoordFromAddrMacroTiled(addr,
++                                              bitPosition,
++                                              effectiveBpp,
++                                              pitch,
++                                              height,
++                                              effectiveSamples,
++                                              tileMode,
++                                              0, // No tileBase
++                                              0, // No compBits
++                                              ADDR_NON_DISPLAYABLE,
++                                              ignoreSE,
++                                              TRUE,
++                                              pipeSwizzle,
++                                              bankSwizzle,
++                                              pTileInfo,
++                                              pX,
++                                              pY,
++                                              pSlice,
++                                              pSample);
++    }
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::DispatchComputeFmaskCoordFromAddr
++*
++*   @brief
++*       Compute (x,y,slice,sample,plane) coordinates from
++*       fmask address
++*   @return
++*       N/A
++*
++***************************************************************************************************
++*/
++VOID EgBasedAddrLib::DispatchComputeFmaskCoordFromAddr(
++    const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,    ///< [in] input structure
++    ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut    ///< [out] output structure
++    ) const
++{
++    UINT_64             addr              = pIn->addr;
++    UINT_32             bitPosition       = pIn->bitPosition;
++    UINT_32             pitch             = pIn->pitch;
++    UINT_32             height            = pIn->height;
++    UINT_32             numSamples        = pIn->numSamples;
++    AddrTileMode        tileMode          = pIn->tileMode;
++    BOOL_32             ignoreSE          = pIn->ignoreSE;
++    ADDR_TILEINFO*      pTileInfo         = pIn->pTileInfo;
++    BOOL_32             resolved          = pIn->resolved;
++
++    UINT_32*            pX      = &pOut->x;
++    UINT_32*            pY      = &pOut->y;
++    UINT_32*            pSlice  = &pOut->slice;
++    UINT_32*            pSample = &pOut->sample;
++    UINT_32*            pPlane  = &pOut->plane;
++
++    switch (tileMode)
++    {
++        case ADDR_TM_1D_TILED_THIN1:
++            ComputeFmaskCoordFromAddrMicroTiled(addr,
++                                                bitPosition,
++                                                pitch,
++                                                height,
++                                                numSamples,
++                                                tileMode,
++                                                resolved,
++                                                pX,
++                                                pY,
++                                                pSlice,
++                                                pSample,
++                                                pPlane);
++            break;
++        case ADDR_TM_2D_TILED_THIN1://fall through
++        case ADDR_TM_3D_TILED_THIN1:
++            UINT_32 pipeSwizzle;
++            UINT_32 bankSwizzle;
++
++            if (m_configFlags.useCombinedSwizzle)
++            {
++                ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
++                                       &bankSwizzle, &pipeSwizzle);
++            }
++            else
++            {
++                pipeSwizzle = pIn->pipeSwizzle;
++                bankSwizzle = pIn->bankSwizzle;
++            }
++
++            ComputeFmaskCoordFromAddrMacroTiled(addr,
++                                                bitPosition,
++                                                pitch,
++                                                height,
++                                                numSamples,
++                                                tileMode,
++                                                pipeSwizzle,
++                                                bankSwizzle,
++                                                ignoreSE,
++                                                pTileInfo,
++                                                resolved,
++                                                pX,
++                                                pY,
++                                                pSlice,
++                                                pSample,
++                                                pPlane);
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++            break;
++
++    }
++}
++#endif
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeFmaskNumPlanesFromNumSamples
++*
++*   @brief
++*       Compute fmask number of planes from number of samples
++*
++*   @return
++*       Number of planes
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputeFmaskNumPlanesFromNumSamples(
++    UINT_32 numSamples)     ///< [in] number of samples
++{
++    UINT_32 numPlanes;
++
++    //
++    // FMASK is stored such that each micro tile is composed of elements containing N bits, where
++    // N is the number of samples.  There is a micro tile for each bit in the FMASK address, and
++    // micro tiles for each address bit, sometimes referred to as a plane, are stored sequentially.
++    // The FMASK for a 2-sample surface looks like a general surface with 2 bits per element.
++    // The FMASK for a 4-sample surface looks like a general surface with 4 bits per element and
++    // 2 samples.  The FMASK for an 8-sample surface looks like a general surface with 8 bits per
++    // element and 4 samples.  R6xx and R7xx only stored 3 planes for 8-sample FMASK surfaces.
++    // This was changed for R8xx to simplify the logic in the CB.
++    //
++    switch (numSamples)
++    {
++        case 2:
++            numPlanes = 1;
++            break;
++        case 4:
++            numPlanes = 2;
++            break;
++        case 8:
++            numPlanes = 4;
++            break;
++        default:
++            ADDR_UNHANDLED_CASE();
++            numPlanes = 0;
++            break;
++    }
++    return numPlanes;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::ComputeFmaskResolvedBppFromNumSamples
++*
++*   @brief
++*       Compute resolved fmask effective bpp based on number of samples
++*
++*   @return
++*       bpp
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::ComputeFmaskResolvedBppFromNumSamples(
++    UINT_32 numSamples)     ///< number of samples
++{
++    UINT_32 bpp;
++
++    //
++    // Resolved FMASK surfaces are generated yBit the CB and read yBit the texture unit
++    // so that the texture unit can read compressed multi-sample color data.
++    // These surfaces store each index value packed per element.
++    // Each element contains at least num_samples * log2(num_samples) bits.
++    // Resolved FMASK surfaces are addressed as follows:
++    // 2-sample Addressed similarly to a color surface with 8 bits per element and 1 sample.
++    // 4-sample Addressed similarly to a color surface with 8 bits per element and 1 sample.
++    // 8-sample Addressed similarly to a color surface with 32 bits per element and 1 sample.
++
++    switch (numSamples)
++    {
++        case 2:
++            bpp = 8;
++            break;
++        case 4:
++            bpp = 8;
++            break;
++        case 8:
++            bpp = 32;
++            break;
++        default:
++            ADDR_UNHANDLED_CASE();
++            bpp = 0;
++            break;
++    }
++    return bpp;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::IsTileInfoAllZero
++*
++*   @brief
++*       Return TRUE if all field are zero
++*   @note
++*       Since NULL input is consider to be all zero
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::IsTileInfoAllZero(
++    ADDR_TILEINFO* pTileInfo)
++{
++    BOOL_32 allZero = TRUE;
++
++    if (pTileInfo)
++    {
++        if ((pTileInfo->banks            != 0)  ||
++            (pTileInfo->bankWidth        != 0)  ||
++            (pTileInfo->bankHeight       != 0)  ||
++            (pTileInfo->macroAspectRatio != 0)  ||
++            (pTileInfo->tileSplitBytes   != 0)  ||
++            (pTileInfo->pipeConfig       != 0)
++            )
++        {
++            allZero = FALSE;
++        }
++    }
++
++    return allZero;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlTileInfoEqual
++*
++*   @brief
++*       Return TRUE if all field are equal
++*   @note
++*       Only takes care of current HWL's data
++***************************************************************************************************
++*/
++BOOL_32 EgBasedAddrLib::HwlTileInfoEqual(
++    const ADDR_TILEINFO* pLeft, ///<[in] Left compare operand
++    const ADDR_TILEINFO* pRight ///<[in] Right compare operand
++    ) const
++{
++    BOOL_32 equal = FALSE;
++
++    if (pLeft->banks == pRight->banks           &&
++        pLeft->bankWidth == pRight->bankWidth   &&
++        pLeft->bankHeight == pRight->bankHeight &&
++        pLeft->macroAspectRatio == pRight->macroAspectRatio &&
++        pLeft->tileSplitBytes == pRight->tileSplitBytes)
++    {
++        equal = TRUE;
++    }
++
++    return equal;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlConvertTileInfoToHW
++*   @brief
++*       Entry of EgBasedAddrLib ConvertTileInfoToHW
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlConvertTileInfoToHW(
++    const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, ///< [in] input structure
++    ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut      ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode   = ADDR_OK;
++
++    ADDR_TILEINFO *pTileInfoIn  = pIn->pTileInfo;
++    ADDR_TILEINFO *pTileInfoOut = pOut->pTileInfo;
++
++    if ((pTileInfoIn != NULL) && (pTileInfoOut != NULL))
++    {
++        if (pIn->reverse == FALSE)
++        {
++            switch (pTileInfoIn->banks)
++            {
++                case 2:
++                    pTileInfoOut->banks = 0;
++                    break;
++                case 4:
++                    pTileInfoOut->banks = 1;
++                    break;
++                case 8:
++                    pTileInfoOut->banks = 2;
++                    break;
++                case 16:
++                    pTileInfoOut->banks = 3;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->banks = 0;
++                    break;
++            }
++
++            switch (pTileInfoIn->bankWidth)
++            {
++                case 1:
++                    pTileInfoOut->bankWidth = 0;
++                    break;
++                case 2:
++                    pTileInfoOut->bankWidth = 1;
++                    break;
++                case 4:
++                    pTileInfoOut->bankWidth = 2;
++                    break;
++                case 8:
++                    pTileInfoOut->bankWidth = 3;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->bankWidth = 0;
++                    break;
++            }
++
++            switch (pTileInfoIn->bankHeight)
++            {
++                case 1:
++                    pTileInfoOut->bankHeight = 0;
++                    break;
++                case 2:
++                    pTileInfoOut->bankHeight = 1;
++                    break;
++                case 4:
++                    pTileInfoOut->bankHeight = 2;
++                    break;
++                case 8:
++                    pTileInfoOut->bankHeight = 3;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->bankHeight = 0;
++                    break;
++            }
++
++            switch (pTileInfoIn->macroAspectRatio)
++            {
++                case 1:
++                    pTileInfoOut->macroAspectRatio = 0;
++                    break;
++                case 2:
++                    pTileInfoOut->macroAspectRatio = 1;
++                    break;
++                case 4:
++                    pTileInfoOut->macroAspectRatio = 2;
++                    break;
++                case 8:
++                    pTileInfoOut->macroAspectRatio = 3;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->macroAspectRatio = 0;
++                    break;
++            }
++
++            switch (pTileInfoIn->tileSplitBytes)
++            {
++                case 64:
++                    pTileInfoOut->tileSplitBytes = 0;
++                    break;
++                case 128:
++                    pTileInfoOut->tileSplitBytes = 1;
++                    break;
++                case 256:
++                    pTileInfoOut->tileSplitBytes = 2;
++                    break;
++                case 512:
++                    pTileInfoOut->tileSplitBytes = 3;
++                    break;
++                case 1024:
++                    pTileInfoOut->tileSplitBytes = 4;
++                    break;
++                case 2048:
++                    pTileInfoOut->tileSplitBytes = 5;
++                    break;
++                case 4096:
++                    pTileInfoOut->tileSplitBytes = 6;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->tileSplitBytes = 0;
++                    break;
++            }
++        }
++        else
++        {
++            switch (pTileInfoIn->banks)
++            {
++                case 0:
++                    pTileInfoOut->banks = 2;
++                    break;
++                case 1:
++                    pTileInfoOut->banks = 4;
++                    break;
++                case 2:
++                    pTileInfoOut->banks = 8;
++                    break;
++                case 3:
++                    pTileInfoOut->banks = 16;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->banks = 2;
++                    break;
++            }
++
++            switch (pTileInfoIn->bankWidth)
++            {
++                case 0:
++                    pTileInfoOut->bankWidth = 1;
++                    break;
++                case 1:
++                    pTileInfoOut->bankWidth = 2;
++                    break;
++                case 2:
++                    pTileInfoOut->bankWidth = 4;
++                    break;
++                case 3:
++                    pTileInfoOut->bankWidth = 8;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->bankWidth = 1;
++                    break;
++            }
++
++            switch (pTileInfoIn->bankHeight)
++            {
++                case 0:
++                    pTileInfoOut->bankHeight = 1;
++                    break;
++                case 1:
++                    pTileInfoOut->bankHeight = 2;
++                    break;
++                case 2:
++                    pTileInfoOut->bankHeight = 4;
++                    break;
++                case 3:
++                    pTileInfoOut->bankHeight = 8;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->bankHeight = 1;
++                    break;
++            }
++
++            switch (pTileInfoIn->macroAspectRatio)
++            {
++                case 0:
++                    pTileInfoOut->macroAspectRatio = 1;
++                    break;
++                case 1:
++                    pTileInfoOut->macroAspectRatio = 2;
++                    break;
++                case 2:
++                    pTileInfoOut->macroAspectRatio = 4;
++                    break;
++                case 3:
++                    pTileInfoOut->macroAspectRatio = 8;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->macroAspectRatio = 1;
++                    break;
++            }
++
++            switch (pTileInfoIn->tileSplitBytes)
++            {
++                case 0:
++                    pTileInfoOut->tileSplitBytes = 64;
++                    break;
++                case 1:
++                    pTileInfoOut->tileSplitBytes = 128;
++                    break;
++                case 2:
++                    pTileInfoOut->tileSplitBytes = 256;
++                    break;
++                case 3:
++                    pTileInfoOut->tileSplitBytes = 512;
++                    break;
++                case 4:
++                    pTileInfoOut->tileSplitBytes = 1024;
++                    break;
++                case 5:
++                    pTileInfoOut->tileSplitBytes = 2048;
++                    break;
++                case 6:
++                    pTileInfoOut->tileSplitBytes = 4096;
++                    break;
++                default:
++                    ADDR_ASSERT_ALWAYS();
++                    retCode = ADDR_INVALIDPARAMS;
++                    pTileInfoOut->tileSplitBytes = 64;
++                    break;
++            }
++        }
++
++        if (pTileInfoIn != pTileInfoOut)
++        {
++            pTileInfoOut->pipeConfig = pTileInfoIn->pipeConfig;
++        }
++    }
++    else
++    {
++        ADDR_ASSERT_ALWAYS();
++        retCode = ADDR_INVALIDPARAMS;
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeSurfaceInfo
++*   @brief
++*       Entry of EgBasedAddrLib ComputeSurfaceInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeSurfaceInfo(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    if (pIn->numSamples < pIn->numFrags)
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++
++    ADDR_TILEINFO tileInfo = {0};
++
++    if (retCode == ADDR_OK)
++    {
++        // Uses internal tile info if pOut does not have a valid pTileInfo
++        if (pOut->pTileInfo == NULL)
++        {
++            pOut->pTileInfo = &tileInfo;
++        }
++
++        if (!DispatchComputeSurfaceInfo(pIn, pOut))
++        {
++            retCode = ADDR_INVALIDPARAMS;
++        }
++
++        // Returns an index
++        pOut->tileIndex = HwlPostCheckTileIndex(pOut->pTileInfo,
++                                                pOut->tileMode,
++                                                pOut->tileType,
++                                                pOut->tileIndex);
++
++        if (IsMacroTiled(pOut->tileMode) && (pOut->macroModeIndex == TileIndexInvalid))
++        {
++            pOut->macroModeIndex = HwlComputeMacroModeIndex(pOut->tileIndex,
++                                                            pIn->flags,
++                                                            pIn->bpp,
++                                                            pIn->numSamples,
++                                                            pOut->pTileInfo);
++        }
++
++        // Resets pTileInfo to NULL if the internal tile info is used
++        if (pOut->pTileInfo == &tileInfo)
++        {
++#if DEBUG
++            // Client does not pass in a valid pTileInfo
++            if (IsMacroTiled(pOut->tileMode))
++            {
++                // If a valid index is returned, then no pTileInfo is okay
++                ADDR_ASSERT(!m_configFlags.useTileIndex || pOut->tileIndex != TileIndexInvalid);
++
++                if (!IsTileInfoAllZero(pIn->pTileInfo))
++                {
++                    // The initial value of pIn->pTileInfo is copied to tileInfo
++                    // We do not expect any of these value to be changed nor any 0 of inputs
++                    ADDR_ASSERT(tileInfo.banks == pIn->pTileInfo->banks);
++                    ADDR_ASSERT(tileInfo.bankWidth == pIn->pTileInfo->bankWidth);
++                    ADDR_ASSERT(tileInfo.bankHeight == pIn->pTileInfo->bankHeight);
++                    ADDR_ASSERT(tileInfo.macroAspectRatio == pIn->pTileInfo->macroAspectRatio);
++                    ADDR_ASSERT(tileInfo.tileSplitBytes == pIn->pTileInfo->tileSplitBytes);
++                }
++            }
++#endif
++            pOut->pTileInfo = NULL;
++        }
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeSurfaceAddrFromCoord
++*   @brief
++*       Entry of EgBasedAddrLib ComputeSurfaceAddrFromCoord
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeSurfaceAddrFromCoord(
++    const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    if (
++#if !ALT_TEST // Overflow test needs this out-of-boundary coord
++        (pIn->x > pIn->pitch)   ||
++        (pIn->y > pIn->height)  ||
++#endif
++        (pIn->numSamples > m_maxSamples))
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++    else
++    {
++        pOut->addr = DispatchComputeSurfaceAddrFromCoord(pIn, pOut);
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeSurfaceCoordFromAddr
++*   @brief
++*       Entry of EgBasedAddrLib ComputeSurfaceCoordFromAddr
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeSurfaceCoordFromAddr(
++    const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    if ((pIn->bitPosition >= 8) ||
++        (pIn->numSamples > m_maxSamples))
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++    else
++    {
++        DispatchComputeSurfaceCoordFromAddr(pIn, pOut);
++    }
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeSliceTileSwizzle
++*   @brief
++*       Entry of EgBasedAddrLib ComputeSurfaceCoordFromAddr
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeSliceTileSwizzle(
++    const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode = ADDR_OK;
++
++    if (pIn->pTileInfo && (pIn->pTileInfo->banks > 0))
++    {
++
++        pOut->tileSwizzle = ComputeSliceTileSwizzle(pIn->tileMode,
++                                                    pIn->baseSwizzle,
++                                                    pIn->slice,
++                                                    pIn->baseAddr,
++                                                    pIn->pTileInfo);
++    }
++    else
++    {
++        retCode = ADDR_INVALIDPARAMS;
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeHtileBpp
++*
++*   @brief
++*       Compute htile bpp
++*
++*   @return
++*       Htile bpp
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::HwlComputeHtileBpp(
++    BOOL_32 isWidth8,   ///< [in] TRUE if block width is 8
++    BOOL_32 isHeight8   ///< [in] TRUE if block height is 8
++    ) const
++{
++    // only support 8x8 mode
++    ADDR_ASSERT(isWidth8 && isHeight8);
++    return 32;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlComputeHtileBaseAlign
++*
++*   @brief
++*       Compute htile base alignment
++*
++*   @return
++*       Htile base alignment
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::HwlComputeHtileBaseAlign(
++    BOOL_32         isTcCompatible, ///< [in] if TC compatible
++    BOOL_32         isLinear,       ///< [in] if it is linear mode
++    ADDR_TILEINFO*  pTileInfo       ///< [in] Tile info
++    ) const
++{
++    UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo);
++
++    if (isTcCompatible)
++    {
++        ADDR_ASSERT(pTileInfo != NULL);
++        if (pTileInfo)
++        {
++            baseAlign *= pTileInfo->banks;
++        }
++    }
++
++    return baseAlign;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled
++*
++*   @brief
++*       Compute 1D tiled surface pitch alignment, calculation results are returned through
++*       output parameters.
++*
++*   @return
++*       pitch alignment
++***************************************************************************************************
++*/
++UINT_32 EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled(
++    AddrTileMode        tileMode,          ///< [in] tile mode
++    UINT_32             bpp,               ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,             ///< [in] surface flags
++    UINT_32             numSamples         ///< [in] number of samples
++    ) const
++{
++    UINT_32 pitchAlign;
++
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    UINT_32 pixelsPerMicroTile;
++    UINT_32 pixelsPerPipeInterleave;
++    UINT_32 microTilesPerPipeInterleave;
++
++    //
++    // Special workaround for depth/stencil buffer, use 8 bpp to meet larger requirement for
++    // stencil buffer since pitch alignment is related to bpp.
++    // For a depth only buffer do not set this.
++    //
++    // Note: this actually does not work for mipmap but mipmap depth texture is not really
++    // sampled with mipmap.
++    //
++    if (flags.depth && !flags.noStencil)
++    {
++        bpp = 8;
++    }
++
++    pixelsPerMicroTile = MicroTilePixels * microTileThickness;
++    pixelsPerPipeInterleave = BYTES_TO_BITS(m_pipeInterleaveBytes) / (bpp * numSamples);
++    microTilesPerPipeInterleave = pixelsPerPipeInterleave / pixelsPerMicroTile;
++
++    pitchAlign = Max(MicroTileWidth, microTilesPerPipeInterleave * MicroTileWidth);
++
++    return pitchAlign;
++}
++
++/**
++***************************************************************************************************
++*   EgBasedAddrLib::HwlGetSizeAdjustmentMicroTiled
++*
++*   @brief
++*       Adjust 1D tiled surface pitch and slice size
++*
++*   @return
++*       Logical slice size in bytes
++***************************************************************************************************
++*/
++UINT_64 EgBasedAddrLib::HwlGetSizeAdjustmentMicroTiled(
++    UINT_32             thickness,      ///< [in] thickness
++    UINT_32             bpp,            ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,          ///< [in] surface flags
++    UINT_32             numSamples,     ///< [in] number of samples
++    UINT_32             baseAlign,      ///< [in] base alignment
++    UINT_32             pitchAlign,     ///< [in] pitch alignment
++    UINT_32*            pPitch,         ///< [in/out] pointer to pitch
++    UINT_32*            pHeight         ///< [in/out] pointer to height
++    ) const
++{
++    UINT_64 logicalSliceSize;
++    UINT_64 physicalSliceSize;
++
++    UINT_32 pitch   = *pPitch;
++    UINT_32 height  = *pHeight;
++
++    // Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so actually numSamples == 1)
++    logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
++
++    // Physical slice: multiplied by thickness
++    physicalSliceSize =  logicalSliceSize * thickness;
++
++    //
++    // R800 will always pad physical slice size to baseAlign which is pipe_interleave_bytes
++    //
++    ADDR_ASSERT((physicalSliceSize % baseAlign) == 0)
++
++    return logicalSliceSize;
++}
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.h b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.h
+new file mode 100644
+index 0000000..84adb66
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/egbaddrlib.h
+@@ -0,0 +1,411 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  egbaddrlib.h
++* @brief Contains the EgBasedAddrLib class definition.
++***************************************************************************************************
++*/
++
++#ifndef __EG_BASED_ADDR_LIB_H__
++#define __EG_BASED_ADDR_LIB_H__
++
++#include "addrlib.h"
++
++
++/// Structures for functions
++struct CoordFromBankPipe
++{
++    UINT_32 xBits : 3;
++    UINT_32 yBits : 4;
++
++    UINT_32 xBit3 : 1;
++    UINT_32 xBit4 : 1;
++    UINT_32 xBit5 : 1;
++    UINT_32 yBit3 : 1;
++    UINT_32 yBit4 : 1;
++    UINT_32 yBit5 : 1;
++    UINT_32 yBit6 : 1;
++};
++
++/**
++***************************************************************************************************
++* @brief This class is the Evergreen based address library
++* @note  Abstract class
++***************************************************************************************************
++*/
++class EgBasedAddrLib : public AddrLib
++{
++protected:
++    EgBasedAddrLib(const AddrClient* pClient);
++    virtual ~EgBasedAddrLib();
++
++public:
++
++    /// Surface info functions
++
++    // NOTE: DispatchComputeSurfaceInfo using TileInfo takes both an input and an output.
++    //       On input:
++    //       One or more fields may be 0 to be calculated/defaulted - pre-SI h/w.
++    //       H/W using tile mode index only accepts none or all 0's - SI and newer h/w.
++    //       It then returns the actual tiling configuration used.
++    //       Other methods' TileInfo must be valid on entry
++    BOOL_32 DispatchComputeSurfaceInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    ADDR_E_RETURNCODE DispatchComputeFmaskInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
++
++protected:
++    // Hwl interface
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
++        const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
++        const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
++        const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
++        ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
++        const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
++        ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
++        UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO*  pTileInfo,
++        UINT_64 baseAddr, UINT_32* pTileSwizzle) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
++        const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
++        ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
++        const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
++        ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
++
++    virtual UINT_32 HwlComputeHtileBpp(
++        BOOL_32 isWidth8, BOOL_32 isHeight8) const;
++
++    virtual UINT_32 HwlComputeHtileBaseAlign(
++        BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
++
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
++        const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
++        const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
++
++    virtual BOOL_32 HwlDegradeBaseLevel(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
++
++    virtual UINT_32 HwlComputeQbStereoRightSwizzle(
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pInfo) const;
++
++    virtual VOID HwlComputePixelCoordFromOffset(
++        UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
++        AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
++        AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
++
++    /// Return Cmask block max
++    virtual BOOL_32 HwlGetMaxCmaskBlockMax() const
++    {
++        return 16383; // 14 bits
++    }
++
++    // Sub-hwl interface
++    /// Pure virtual function to setup tile info (indices) if client requests to do so
++    virtual VOID HwlSetupTileInfo(
++        AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
++        AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
++
++    /// Pure virtual function to get pitch alignment for linear modes
++    virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const = 0;
++
++    /// Pure virtual function to get size adjustment for linear modes
++    virtual UINT_64 HwlGetSizeAdjustmentLinear(
++        AddrTileMode tileMode,
++        UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
++        UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const = 0;
++
++    virtual UINT_32 HwlGetPitchAlignmentMicroTiled(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const;
++
++    virtual UINT_64 HwlGetSizeAdjustmentMicroTiled(
++        UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
++        UINT_32 baseAlign, UINT_32 pitchAlign,
++        UINT_32 *pPitch, UINT_32 *pHeight) const;
++
++        /// Pure virtual function to do extra sanity check
++    virtual BOOL_32 HwlSanityCheckMacroTiled(
++        ADDR_TILEINFO* pTileInfo) const = 0;
++
++    /// Pure virtual function to check current level to be the last macro tiled one
++    virtual VOID HwlCheckLastMacroTiledLvl(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
++
++    /// Adjusts bank before bank is modified by rotation
++    virtual UINT_32 HwlPreAdjustBank(
++        UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO*  pTileInfo) const = 0;
++
++    virtual VOID HwlComputeSurfaceCoord2DFromBankPipe(
++        AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice,
++        UINT_32 bank, UINT_32 pipe,
++        UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
++        BOOL_32 ignoreSE,
++        ADDR_TILEINFO* pTileInfo) const = 0;
++
++    virtual BOOL_32 HwlTileInfoEqual(
++        const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
++
++    virtual AddrTileMode HwlDegradeThickTileMode(
++        AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
++
++    virtual INT_32 HwlPostCheckTileIndex(
++        const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
++        INT curIndex = TileIndexInvalid) const
++    {
++        return TileIndexInvalid;
++    }
++
++    virtual VOID HwlFmaskPreThunkSurfInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
++        const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const
++    {
++    }
++
++    virtual VOID HwlFmaskPostThunkSurfInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const
++    {
++    }
++
++    /// Virtual function to check if the height needs extra padding
++    /// for stereo right eye offset, to avoid bank pipe swizzle
++    virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const
++    {
++        return FALSE;
++    }
++
++    virtual BOOL_32 HwlReduceBankWidthHeight(
++        UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
++        UINT_32 bankHeightAlign, UINT_32 pipes,
++        ADDR_TILEINFO* pTileInfo) const;
++
++    // Protected non-virtual functions
++
++    /// Mip level functions
++    AddrTileMode ComputeSurfaceMipLevelTileMode(
++        AddrTileMode baseTileMode, UINT_32 bpp,
++        UINT_32 pitch, UINT_32 height, UINT_32 numSlices, UINT_32 numSamples,
++        UINT_32 pitchAlign, UINT_32 heightAlign,
++        ADDR_TILEINFO* pTileInfo) const;
++
++    /// Swizzle functions
++    VOID ExtractBankPipeSwizzle(
++        UINT_32 base256b, ADDR_TILEINFO* pTileInfo,
++        UINT_32* pBankSwizzle, UINT_32* pPipeSwizzle) const;
++
++    UINT_32 GetBankPipeSwizzle(
++        UINT_32 bankSwizzle, UINT_32 pipeSwizzle,
++        UINT_64 baseAddr, ADDR_TILEINFO*  pTileInfo) const;
++
++    UINT_32 ComputeSliceTileSwizzle(
++        AddrTileMode tileMode, UINT_32 baseSwizzle, UINT_32 slice, UINT_64 baseAddr,
++        ADDR_TILEINFO* pTileInfo) const;
++
++    /// Addressing functions
++    UINT_32 ComputeBankFromCoord(
++        UINT_32 x, UINT_32 y, UINT_32 slice,
++        AddrTileMode tileMode, UINT_32 bankSwizzle, UINT_32 tileSpitSlice,
++        ADDR_TILEINFO* pTileInfo) const;
++
++    UINT_32 ComputeBankFromAddr(
++        UINT_64 addr, UINT_32 numBanks, UINT_32 numPipes) const;
++
++    UINT_32 ComputePipeRotation(
++        AddrTileMode tileMode, UINT_32 numPipes) const;
++
++    UINT_32 ComputeBankRotation(
++        AddrTileMode tileMode, UINT_32 numBanks,
++        UINT_32 numPipes) const;
++
++    VOID ComputeSurfaceCoord2DFromBankPipe(
++        AddrTileMode tileMode, UINT_32 x, UINT_32 y, UINT_32 slice,
++        UINT_32 bank, UINT_32 pipe,
++        UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
++        ADDR_TILEINFO* pTileInfo,
++        CoordFromBankPipe *pOutput) const;
++
++    /// Htile/Cmask functions
++    UINT_64 ComputeHtileBytes(
++        UINT_32 pitch, UINT_32 height, UINT_32 bpp,
++        BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
++
++    // Static functions
++    static BOOL_32 IsTileInfoAllZero(ADDR_TILEINFO* pTileInfo);
++    static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
++    static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
++
++private:
++
++    BOOL_32 ComputeSurfaceInfoLinear(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
++        UINT_32 padDims) const;
++
++    BOOL_32 ComputeSurfaceInfoMicroTiled(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
++        UINT_32 padDims,
++        AddrTileMode expTileMode) const;
++
++    BOOL_32 ComputeSurfaceInfoMacroTiled(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
++        UINT_32 padDims,
++        AddrTileMode expTileMode) const;
++
++    BOOL_32 ComputeSurfaceAlignmentsLinear(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
++        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
++
++    BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
++        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
++
++    BOOL_32 ComputeSurfaceAlignmentsMacroTiled(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
++        UINT_32 mipLevel, UINT_32 numSamples,
++        ADDR_TILEINFO* pTileInfo,
++        UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
++
++    /// Surface addressing functions
++    UINT_64 DispatchComputeSurfaceAddrFromCoord(
++        const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    VOID    DispatchComputeSurfaceCoordFromAddr(
++        const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
++
++    UINT_64 ComputeSurfaceAddrFromCoordMicroTiled(
++        UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        AddrTileMode tileMode,
++        AddrTileType microTileType, BOOL_32 isDepthSampleOrder,
++        UINT_32* pBitPosition) const;
++
++    UINT_64 ComputeSurfaceAddrFromCoordMacroTiled(
++        UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        AddrTileMode tileMode,
++        AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder,
++        UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
++        ADDR_TILEINFO* pTileInfo,
++        UINT_32* pBitPosition) const;
++
++    VOID    ComputeSurfaceCoordFromAddrMacroTiled(
++        UINT_64 addr, UINT_32 bitPosition,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
++        AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder,
++        UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
++        ADDR_TILEINFO* pTileInfo,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
++
++    /// Fmask functions
++    UINT_64 DispatchComputeFmaskAddrFromCoord(
++        const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
++
++    VOID    DispatchComputeFmaskCoordFromAddr(
++        const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
++        ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
++
++    // FMASK related methods - private
++    UINT_64 ComputeFmaskAddrFromCoordMicroTiled(
++        UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane,
++        UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
++        BOOL_32 resolved, UINT_32* pBitPosition) const;
++
++    VOID    ComputeFmaskCoordFromAddrMicroTiled(
++        UINT_64 addr, UINT_32 bitPosition,
++        UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        AddrTileMode tileMode, BOOL_32 resolved,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
++
++    VOID    ComputeFmaskCoordFromAddrMacroTiled(
++        UINT_64 addr, UINT_32 bitPosition,
++        UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
++        UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
++        BOOL_32 ignoreSE,
++        ADDR_TILEINFO* pTileInfo,
++        BOOL_32 resolved,
++        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
++
++    UINT_64 ComputeFmaskAddrFromCoordMacroTiled(
++        UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane,
++        UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        AddrTileMode tileMode, UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
++        BOOL_32 ignoreSE,
++        ADDR_TILEINFO* pTileInfo,
++        BOOL_32 resolved,
++        UINT_32* pBitPosition) const;
++
++    /// Sanity check functions
++    BOOL_32 SanityCheckMacroTiled(
++        ADDR_TILEINFO* pTileInfo) const;
++
++protected:
++    UINT_32 m_ranks;                ///< Number of ranks - MC_ARB_RAMCFG.NOOFRANK
++    UINT_32 m_logicalBanks;         ///< Logical banks = m_banks * m_ranks if m_banks != 16
++    UINT_32 m_bankInterleave;       ///< Bank interleave, as a multiple of pipe interleave size
++};
++
++#endif
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.cpp b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.cpp
+new file mode 100644
+index 0000000..a858b55
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.cpp
+@@ -0,0 +1,2818 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  siaddrlib.cpp
++* @brief Contains the implementation for the SIAddrLib class.
++***************************************************************************************************
++*/
++
++#include "siaddrlib.h"
++
++#include "si_gb_reg.h"
++
++#include "si_ci_vi_merged_enum.h"
++
++#if BRAHMA_BUILD
++#include "amdgpu_id.h"
++#else
++#include "si_id.h"
++#endif
++
++///////////////////////////////////////////////////////////////////////////////////////////////////
++///////////////////////////////////////////////////////////////////////////////////////////////////
++
++/**
++***************************************************************************************************
++*   AddrSIHwlInit
++*
++*   @brief
++*       Creates an SIAddrLib object.
++*
++*   @return
++*       Returns an SIAddrLib object pointer.
++***************************************************************************************************
++*/
++AddrLib* AddrSIHwlInit(const AddrClient* pClient)
++{
++    return SIAddrLib::CreateObj(pClient);
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::SIAddrLib
++*
++*   @brief
++*       Constructor
++*
++***************************************************************************************************
++*/
++SIAddrLib::SIAddrLib(const AddrClient* pClient) :
++    EgBasedAddrLib(pClient),
++    m_noOfEntries(0)
++{
++    m_class = SI_ADDRLIB;
++    memset(&m_settings, 0, sizeof(m_settings));
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::~SIAddrLib
++*
++*   @brief
++*       Destructor
++***************************************************************************************************
++*/
++SIAddrLib::~SIAddrLib()
++{
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlGetPipes
++*
++*   @brief
++*       Get number pipes
++*   @return
++*       num pipes
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlGetPipes(
++    const ADDR_TILEINFO* pTileInfo    ///< [in] Tile info
++    ) const
++{
++    UINT_32 numPipes;
++
++    if (pTileInfo)
++    {
++        numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
++    }
++    else
++    {
++        ADDR_ASSERT_ALWAYS();
++        numPipes = m_pipes; // Suppose we should still have a global pipes
++    }
++
++    return numPipes;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::GetPipePerSurf
++*   @brief
++*       get pipe num base on inputing tileinfo->pipeconfig
++*   @return
++*       pipe number
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::GetPipePerSurf(
++    AddrPipeCfg pipeConfig   ///< [in] pipe config
++    ) const
++{
++    UINT_32 numPipes = 0;
++
++    switch (pipeConfig)
++    {
++        case ADDR_PIPECFG_P2:
++            numPipes = 2;
++            break;
++        case ADDR_PIPECFG_P4_8x16:
++        case ADDR_PIPECFG_P4_16x16:
++        case ADDR_PIPECFG_P4_16x32:
++        case ADDR_PIPECFG_P4_32x32:
++            numPipes = 4;
++            break;
++        case ADDR_PIPECFG_P8_16x16_8x16:
++        case ADDR_PIPECFG_P8_16x32_8x16:
++        case ADDR_PIPECFG_P8_32x32_8x16:
++        case ADDR_PIPECFG_P8_16x32_16x16:
++        case ADDR_PIPECFG_P8_32x32_16x16:
++        case ADDR_PIPECFG_P8_32x32_16x32:
++        case ADDR_PIPECFG_P8_32x64_32x32:
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P16_32x32_8x16:
++        case ADDR_PIPECFG_P16_32x32_16x16:
++            numPipes = 16;
++            break;
++        default:
++            ADDR_ASSERT(!"Invalid pipe config");
++            numPipes = m_pipes;
++    }
++    return numPipes;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::ComputePipeFromCoord
++*
++*   @brief
++*       Compute pipe number from coordinates
++*   @return
++*       Pipe number
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::ComputePipeFromCoord(
++    UINT_32         x,              ///< [in] x coordinate
++    UINT_32         y,              ///< [in] y coordinate
++    UINT_32         slice,          ///< [in] slice index
++    AddrTileMode    tileMode,       ///< [in] tile mode
++    UINT_32         pipeSwizzle,    ///< [in] pipe swizzle
++    BOOL_32         ignoreSE,       ///< [in] TRUE if shader engines are ignored
++    ADDR_TILEINFO*  pTileInfo       ///< [in] Tile info
++    ) const
++{
++    UINT_32 pipe;
++    UINT_32 pipeBit0 = 0;
++    UINT_32 pipeBit1 = 0;
++    UINT_32 pipeBit2 = 0;
++    UINT_32 pipeBit3 = 0;
++    UINT_32 sliceRotation;
++    UINT_32 numPipes = 0;
++
++    UINT_32 tx = x / MicroTileWidth;
++    UINT_32 ty = y / MicroTileHeight;
++    UINT_32 x3 = _BIT(tx,0);
++    UINT_32 x4 = _BIT(tx,1);
++    UINT_32 x5 = _BIT(tx,2);
++    UINT_32 x6 = _BIT(tx,3);
++    UINT_32 y3 = _BIT(ty,0);
++    UINT_32 y4 = _BIT(ty,1);
++    UINT_32 y5 = _BIT(ty,2);
++    UINT_32 y6 = _BIT(ty,3);
++
++    switch (pTileInfo->pipeConfig)
++    {
++        case ADDR_PIPECFG_P2:
++            pipeBit0 = x3 ^ y3;
++            numPipes = 2;
++            break;
++        case ADDR_PIPECFG_P4_8x16:
++            pipeBit0 = x4 ^ y3;
++            pipeBit1 = x3 ^ y4;
++            numPipes = 4;
++            break;
++        case ADDR_PIPECFG_P4_16x16:
++            pipeBit0 = x3 ^ y3 ^ x4;
++            pipeBit1 = x4 ^ y4;
++            numPipes = 4;
++            break;
++        case ADDR_PIPECFG_P4_16x32:
++            pipeBit0 = x3 ^ y3 ^ x4;
++            pipeBit1 = x4 ^ y5;
++            numPipes = 4;
++            break;
++        case ADDR_PIPECFG_P4_32x32:
++            pipeBit0 = x3 ^ y3 ^ x5;
++            pipeBit1 = x5 ^ y5;
++            numPipes = 4;
++            break;
++        case ADDR_PIPECFG_P8_16x16_8x16:
++            pipeBit0 = x4 ^ y3 ^ x5;
++            pipeBit1 = x3 ^ y5;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P8_16x32_8x16:
++            pipeBit0 = x4 ^ y3 ^ x5;
++            pipeBit1 = x3 ^ y4;
++            pipeBit2 = x4 ^ y5;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P8_16x32_16x16:
++            pipeBit0 = x3 ^ y3 ^ x4;
++            pipeBit1 = x5 ^ y4;
++            pipeBit2 = x4 ^ y5;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P8_32x32_8x16:
++            pipeBit0 = x4 ^ y3 ^ x5;
++            pipeBit1 = x3 ^ y4;
++            pipeBit2 = x5 ^ y5;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x16:
++            pipeBit0 = x3 ^ y3 ^ x4;
++            pipeBit1 = x4 ^ y4;
++            pipeBit2 = x5 ^ y5;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x32:
++            pipeBit0 = x3 ^ y3 ^ x4;
++            pipeBit1 = x4 ^ y6;
++            pipeBit2 = x5 ^ y5;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P8_32x64_32x32:
++            pipeBit0 = x3 ^ y3 ^ x5;
++            pipeBit1 = x6 ^ y5;
++            pipeBit2 = x5 ^ y6;
++            numPipes = 8;
++            break;
++        case ADDR_PIPECFG_P16_32x32_8x16:
++            pipeBit0 = x4 ^ y3;
++            pipeBit1 = x3 ^ y4;
++            pipeBit2 = x5 ^ y6;
++            pipeBit3 = x6 ^ y5;
++            numPipes = 16;
++            break;
++        case ADDR_PIPECFG_P16_32x32_16x16:
++            pipeBit0 = x3 ^ y3 ^ x4;
++            pipeBit1 = x4 ^ y4;
++            pipeBit2 = x5 ^ y6;
++            pipeBit3 = x6 ^ y5;
++            numPipes = 16;
++            break;
++        default:
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++    pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
++
++    UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
++
++    //
++    // Apply pipe rotation for the slice.
++    //
++    switch (tileMode)
++    {
++        case ADDR_TM_3D_TILED_THIN1:    //fall through thin
++        case ADDR_TM_3D_TILED_THICK:    //fall through thick
++        case ADDR_TM_3D_TILED_XTHICK:
++            sliceRotation =
++                Max(1, static_cast<INT_32>(numPipes / 2) - 1) * (slice / microTileThickness);
++            break;
++        default:
++            sliceRotation = 0;
++            break;
++    }
++    pipeSwizzle += sliceRotation;
++    pipeSwizzle &= (numPipes - 1);
++
++    pipe = pipe ^ pipeSwizzle;
++
++    return pipe;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::ComputeTileCoordFromPipeAndElemIdx
++*
++*   @brief
++*       Compute (x,y) of a tile within a macro tile from address
++*   @return
++*       Pipe number
++***************************************************************************************************
++*/
++VOID SIAddrLib::ComputeTileCoordFromPipeAndElemIdx(
++    UINT_32         elemIdx,          ///< [in] per pipe element index within a macro tile
++    UINT_32         pipe,             ///< [in] pipe index
++    AddrPipeCfg     pipeCfg,          ///< [in] pipe config
++    UINT_32         pitchInMacroTile, ///< [in] surface pitch in macro tile
++    UINT_32         x,                ///< [in] x coordinate of the (0,0) tile in a macro tile
++    UINT_32         y,                ///< [in] y coordinate of the (0,0) tile in a macro tile
++    UINT_32*        pX,               ///< [out] x coordinate
++    UINT_32*        pY                ///< [out] y coordinate
++    ) const
++{
++    UINT_32 pipebit0 = _BIT(pipe,0);
++    UINT_32 pipebit1 = _BIT(pipe,1);
++    UINT_32 pipebit2 = _BIT(pipe,2);
++    UINT_32 pipebit3 = _BIT(pipe,3);
++    UINT_32 elemIdx0 = _BIT(elemIdx,0);
++    UINT_32 elemIdx1 = _BIT(elemIdx,1);
++    UINT_32 elemIdx2 = _BIT(elemIdx,2);
++    UINT_32 x3 = 0;
++    UINT_32 x4 = 0;
++    UINT_32 x5 = 0;
++    UINT_32 x6 = 0;
++    UINT_32 y3 = 0;
++    UINT_32 y4 = 0;
++    UINT_32 y5 = 0;
++    UINT_32 y6 = 0;
++
++    switch(pipeCfg)
++    {
++        case ADDR_PIPECFG_P2:
++            x4 = elemIdx2;
++            y4 = elemIdx1 ^ x4;
++            y3 = elemIdx0 ^ x4;
++            x3 = pipebit0 ^ y3;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P4_8x16:
++            x4 = elemIdx1;
++            y4 = elemIdx0 ^ x4;
++            x3 = pipebit1 ^ y4;
++            y3 = pipebit0 ^ x4;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P4_16x16:
++            x4 = elemIdx1;
++            y3 = elemIdx0 ^ x4;
++            y4 = pipebit1 ^ x4;
++            x3 = pipebit0 ^ y3 ^ x4;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P4_16x32:
++            x3 = elemIdx0 ^ pipebit0;
++            y5 = _BIT(y,5);
++            x4 = pipebit1 ^ y5;
++            y3 = pipebit0 ^ x3 ^ x4;
++            y4 = elemIdx1 ^ x4;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P4_32x32:
++            x4 = elemIdx2;
++            y3 = elemIdx0 ^ x4;
++            y4 = elemIdx1 ^ x4;
++            if((pitchInMacroTile % 2) == 0)
++            {   //even
++                y5 = _BIT(y,5);
++                x5 = pipebit1 ^ y5;
++                x3 = pipebit0 ^ y3 ^ x5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            else
++            {   //odd
++                x5 = _BIT(x,5);
++                x3 = pipebit0 ^ y3 ^ x5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(2, x4, x3);
++            }
++            break;
++        case ADDR_PIPECFG_P8_16x16_8x16:
++            x4 = elemIdx0;
++            y5 = _BIT(y,5);
++            x5 = _BIT(x,5);
++            x3 = pipebit1 ^ y5;
++            y4 = pipebit2 ^ x4;
++            y3 = pipebit0 ^ x5 ^ x4;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P8_16x32_8x16:
++            x3 = elemIdx0;
++            y4 = pipebit1 ^ x3;
++            y5 = _BIT(y,5);
++            x5 = _BIT(x,5);
++            x4 = pipebit2 ^ y5;
++            y3 = pipebit0 ^ x4 ^ x5;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P8_32x32_8x16:
++            x4 = elemIdx1;
++            y4 = elemIdx0 ^ x4;
++            x3 = pipebit1 ^ y4;
++            if((pitchInMacroTile % 2) == 0)
++            {  //even
++                y5 = _BIT(y,5);
++                x5 = _BIT(x,5);
++                x5 = pipebit2 ^ y5;
++                y3 = pipebit0 ^ x4 ^ x5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            else
++            {  //odd
++                x5 = _BIT(x,5);
++                y3 = pipebit0 ^ x4 ^ x5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(2, x4, x3);
++            }
++            break;
++        case ADDR_PIPECFG_P8_16x32_16x16:
++            x3 = elemIdx0;
++            x5 = _BIT(x,5);
++            y5 = _BIT(y,5);
++            x4 = pipebit2 ^ y5;
++            y4 = pipebit1 ^ x5;
++            y3 = pipebit0 ^ x3 ^ x4;
++            *pY = Bits2Number(2, y4, y3);
++            *pX = Bits2Number(2, x4, x3);
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x16:
++            x4 = elemIdx1;
++            y3 = elemIdx0 ^ x4;
++            x3 = y3^x4^pipebit0;
++            y4 = pipebit1 ^ x4;
++            if((pitchInMacroTile % 2) == 0)
++            {   //even
++                y5 = _BIT(y,5);
++                x5 = pipebit2 ^ y5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            else
++            {   //odd
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(2, x4, x3);
++            }
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x32:
++            if((pitchInMacroTile % 2) == 0)
++            {   //even
++                y5 = _BIT(y,5);
++                y6 = _BIT(y,6);
++                x4 = pipebit1 ^ y6;
++                y3 = elemIdx0 ^ x4;
++                y4 = elemIdx1 ^ x4;
++                x3 = pipebit0 ^ y3 ^ x4;
++                x5 = pipebit2 ^ y5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            else
++            {   //odd
++                y6 = _BIT(y,6);
++                x4 = pipebit1 ^ y6;
++                y3 = elemIdx0 ^ x4;
++                y4 = elemIdx1 ^ x4;
++                x3 = pipebit0 ^ y3 ^ x4;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(2, x4, x3);
++            }
++            break;
++        case ADDR_PIPECFG_P8_32x64_32x32:
++            x4 = elemIdx2;
++            y3 = elemIdx0 ^ x4;
++            y4 = elemIdx1 ^ x4;
++            if((pitchInMacroTile % 4) == 0)
++            {   //multiple of 4
++                y5 = _BIT(y,5);
++                y6 = _BIT(y,6);
++                x5 = pipebit2 ^ y6;
++                x6 = pipebit1 ^ y5;
++                x3 = pipebit0 ^ y3 ^ x5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(4, x6, x5, x4, x3);
++            }
++            else
++            {
++                y6 = _BIT(y,6);
++                x5 = pipebit2 ^ y6;
++                x3 = pipebit0 ^ y3 ^ x5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            break;
++        case ADDR_PIPECFG_P16_32x32_8x16:
++            x4 = elemIdx1;
++            y4 = elemIdx0 ^ x4;
++            y3 = pipebit0 ^ x4;
++            x3 = pipebit1 ^ y4;
++            if((pitchInMacroTile % 4) == 0)
++            {   //multiple of 4
++                y5 = _BIT(y,5);
++                y6 = _BIT(y,6);
++                x5 = pipebit2 ^ y6;
++                x6 = pipebit3 ^ y5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(4, x6, x5,x4, x3);
++            }
++            else
++            {
++                y6 = _BIT(y,6);
++                x5 = pipebit2 ^ y6;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            break;
++        case ADDR_PIPECFG_P16_32x32_16x16:
++            x4 = elemIdx1;
++            y3 = elemIdx0 ^ x4;
++            y4 = pipebit1 ^ x4;
++            x3 = pipebit0 ^ y3 ^ x4;
++            if((pitchInMacroTile % 4) == 0)
++            {   //multiple of 4
++                y5 = _BIT(y,5);
++                y6 = _BIT(y,6);
++                x5 = pipebit2 ^ y6;
++                x6 = pipebit3 ^ y5;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(4, x6, x5, x4, x3);
++            }
++            else
++            {
++                y6 = _BIT(y,6);
++                x5 = pipebit2 ^ y6;
++                *pY = Bits2Number(2, y4, y3);
++                *pX = Bits2Number(3, x5, x4, x3);
++            }
++            break;
++        default:
++            ADDR_UNHANDLED_CASE();
++    }
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::TileCoordToMaskElementIndex
++*
++*   @brief
++*       Compute element index from coordinates in tiles
++*   @return
++*       Element index
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::TileCoordToMaskElementIndex(
++    UINT_32         tx,                 ///< [in] x coord, in Tiles
++    UINT_32         ty,                 ///< [in] y coord, in Tiles
++    AddrPipeCfg     pipeConfig,         ///< [in] pipe config
++    UINT_32*        macroShift,         ///< [out] macro shift
++    UINT_32*        elemIdxBits         ///< [out] tile offset bits
++    ) const
++{
++    UINT_32 elemIdx = 0;
++    UINT_32 elemIdx0, elemIdx1, elemIdx2;
++    UINT_32 tx0, tx1;
++    UINT_32 ty0, ty1;
++
++    tx0 = _BIT(tx,0);
++    tx1 = _BIT(tx,1);
++    ty0 = _BIT(ty,0);
++    ty1 = _BIT(ty,1);
++
++    switch(pipeConfig)
++    {
++        case ADDR_PIPECFG_P2:
++            *macroShift = 3;
++            *elemIdxBits =3;
++            elemIdx2 = tx1;
++            elemIdx1 = tx1 ^ ty1;
++            elemIdx0 = tx1 ^ ty0;
++            elemIdx = Bits2Number(3,elemIdx2,elemIdx1,elemIdx0);
++            break;
++        case ADDR_PIPECFG_P4_8x16:
++            *macroShift = 2;
++            *elemIdxBits =2;
++            elemIdx1 = tx1;
++            elemIdx0 = tx1 ^ ty1;
++            elemIdx = Bits2Number(2,elemIdx1,elemIdx0);
++            break;
++        case ADDR_PIPECFG_P4_16x16:
++            *macroShift = 2;
++            *elemIdxBits =2;
++            elemIdx0 = tx1^ty0;
++            elemIdx1 = tx1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P4_16x32:
++            *macroShift = 2;
++            *elemIdxBits =2;
++            elemIdx0 = tx1^ty0;
++            elemIdx1 = tx1^ty1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P4_32x32:
++            *macroShift = 2;
++            *elemIdxBits =3;
++            elemIdx0 = tx1^ty0;
++            elemIdx1 = tx1^ty1;
++            elemIdx2 = tx1;
++            elemIdx = Bits2Number(3, elemIdx2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P8_16x16_8x16:
++            *macroShift = 1;
++            *elemIdxBits =1;
++            elemIdx0 = tx1;
++            elemIdx = elemIdx0;
++            break;
++        case ADDR_PIPECFG_P8_16x32_8x16:
++            *macroShift = 1;
++            *elemIdxBits =1;
++            elemIdx0 = tx0;
++            elemIdx = elemIdx0;
++            break;
++        case ADDR_PIPECFG_P8_32x32_8x16:
++            *macroShift = 1;
++            *elemIdxBits =2;
++            elemIdx1 = tx1;
++            elemIdx0 = tx1^ty1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P8_16x32_16x16:
++            *macroShift = 1;
++            *elemIdxBits =1;
++            elemIdx0 = tx0;
++            elemIdx = elemIdx0;
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x16:
++            *macroShift = 1;
++            *elemIdxBits =2;
++            elemIdx0 = tx1^ty0;
++            elemIdx1 = tx1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x32:
++            *macroShift = 1;
++            *elemIdxBits =2;
++            elemIdx0 =  tx1^ty0;
++            elemIdx1 = tx1^ty1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P8_32x64_32x32:
++            *macroShift = 1;
++            *elemIdxBits =3;
++            elemIdx0 = tx1^ty0;
++            elemIdx1 = tx1^ty1;
++            elemIdx2 = tx1;
++            elemIdx = Bits2Number(3, elemIdx2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P16_32x32_8x16:
++            *macroShift = 0;
++            *elemIdxBits =2;
++            elemIdx0 = tx1^ty1;
++            elemIdx1 = tx1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        case ADDR_PIPECFG_P16_32x32_16x16:
++            *macroShift = 0;
++            *elemIdxBits =2;
++            elemIdx0 = tx1^ty0;
++            elemIdx1 = tx1;
++            elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
++            break;
++        default:
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++
++    return elemIdx;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeTileDataWidthAndHeightLinear
++*
++*   @brief
++*       Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
++*
++*   @return
++*       N/A
++*
++*   @note
++*       MacroWidth and macroHeight are measured in pixels
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlComputeTileDataWidthAndHeightLinear(
++    UINT_32*        pMacroWidth,     ///< [out] macro tile width
++    UINT_32*        pMacroHeight,    ///< [out] macro tile height
++    UINT_32         bpp,             ///< [in] bits per pixel
++    ADDR_TILEINFO*  pTileInfo        ///< [in] tile info
++    ) const
++{
++    ADDR_ASSERT(pTileInfo != NULL);
++    UINT_32 macroWidth;
++    UINT_32 macroHeight;
++
++    /// In linear mode, the htile or cmask buffer must be padded out to 4 tiles
++    /// but for P8_32x64_32x32, it must be padded out to 8 tiles
++    /// Actually there are more pipe configs which need 8-tile padding but SI family
++    /// has a bug which is fixed in CI family
++    if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32) ||
++        (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
++        (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x32_16x16))
++    {
++        macroWidth  = 8*MicroTileWidth;
++        macroHeight = 8*MicroTileHeight;
++    }
++    else
++    {
++        macroWidth  = 4*MicroTileWidth;
++        macroHeight = 4*MicroTileHeight;
++    }
++
++    *pMacroWidth    = macroWidth;
++    *pMacroHeight   = macroHeight;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeHtileBytes
++*
++*   @brief
++*       Compute htile size in bytes
++*
++*   @return
++*       Htile size in bytes
++***************************************************************************************************
++*/
++UINT_64 SIAddrLib::HwlComputeHtileBytes(
++    UINT_32     pitch,          ///< [in] pitch
++    UINT_32     height,         ///< [in] height
++    UINT_32     bpp,            ///< [in] bits per pixel
++    BOOL_32     isLinear,       ///< [in] if it is linear mode
++    UINT_32     numSlices,      ///< [in] number of slices
++    UINT_64*    pSliceBytes,    ///< [out] bytes per slice
++    UINT_32     baseAlign       ///< [in] base alignments
++    ) const
++{
++    return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeXmaskAddrFromCoord
++*
++*   @brief
++*       Compute address from coordinates for htile/cmask
++*   @return
++*       Byte address
++***************************************************************************************************
++*/
++UINT_64 SIAddrLib::HwlComputeXmaskAddrFromCoord(
++    UINT_32        pitch,          ///< [in] pitch
++    UINT_32        height,         ///< [in] height
++    UINT_32        x,              ///< [in] x coord
++    UINT_32        y,              ///< [in] y coord
++    UINT_32        slice,          ///< [in] slice/depth index
++    UINT_32        numSlices,      ///< [in] number of slices
++    UINT_32        factor,         ///< [in] factor that indicates cmask(2) or htile(1)
++    BOOL_32        isLinear,       ///< [in] linear or tiled HTILE layout
++    BOOL_32        isWidth8,       ///< [in] TRUE if width is 8, FALSE means 4. It's register value
++    BOOL_32        isHeight8,      ///< [in] TRUE if width is 8, FALSE means 4. It's register value
++    ADDR_TILEINFO* pTileInfo,      ///< [in] Tile info
++    UINT_32*       pBitPosition    ///< [out] bit position inside a byte
++    ) const
++{
++    UINT_32 tx = x / MicroTileWidth;
++    UINT_32 ty = y / MicroTileHeight;
++    UINT_32 newPitch;
++    UINT_32 newHeight;
++    UINT_64 totalBytes;
++    UINT_32 macroWidth;
++    UINT_32 macroHeight;
++    UINT_64 pSliceBytes;
++    UINT_32 pBaseAlign;
++    UINT_32 tileNumPerPipe;
++    UINT_32 elemBits;
++
++    if (factor == 2) //CMASK
++    {
++        ADDR_CMASK_FLAGS flags = {{0}};
++
++        tileNumPerPipe = 256;
++
++        ComputeCmaskInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         pTileInfo,
++                         &newPitch,
++                         &newHeight,
++                         &totalBytes,
++                         &macroWidth,
++                         &macroHeight);
++        elemBits = CmaskElemBits;
++    }
++    else //HTile
++    {
++        ADDR_HTILE_FLAGS flags = {{0}};
++
++        tileNumPerPipe = 512;
++
++        ComputeHtileInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         TRUE,
++                         TRUE,
++                         pTileInfo,
++                         &newPitch,
++                         &newHeight,
++                         &totalBytes,
++                         &macroWidth,
++                         &macroHeight,
++                         &pSliceBytes,
++                         &pBaseAlign);
++        elemBits = 32;
++    }
++
++    const UINT_32 pitchInTile = newPitch / MicroTileWidth;
++    const UINT_32 heightInTile = newHeight / MicroTileWidth;
++    UINT_64 macroOffset; // Per pipe starting offset of the macro tile in which this tile lies.
++    UINT_64 microNumber; // Per pipe starting offset of the macro tile in which this tile lies.
++    UINT_32 microX;
++    UINT_32 microY;
++    UINT_64 microOffset;
++    UINT_32 microShift;
++    UINT_64 totalOffset;
++    UINT_32 elemIdxBits;
++    UINT_32 elemIdx =
++        TileCoordToMaskElementIndex(tx, ty, pTileInfo->pipeConfig, &microShift, &elemIdxBits);
++
++    UINT_32 numPipes = HwlGetPipes(pTileInfo);
++
++    if (isLinear)
++    {   //linear addressing
++        // Linear addressing is extremelly wasting memory if slice > 1, since each pipe has the full
++        // slice memory foot print instead of divided by numPipes.
++        microX = tx / 4; // Macro Tile is 4x4
++        microY = ty / 4 ;
++        microNumber = static_cast<UINT_64>(microX + microY * (pitchInTile / 4)) << microShift;
++
++        UINT_32 sliceBits = pitchInTile * heightInTile;
++
++        // do htile single slice alignment if the flag is true
++        if (m_configFlags.useHtileSliceAlign && (factor == 1))  //Htile
++        {
++            sliceBits = PowTwoAlign(sliceBits, BITS_TO_BYTES(HtileCacheBits) * numPipes / elemBits);
++        }
++        macroOffset = slice * (sliceBits / numPipes) * elemBits ;
++    }
++    else
++    {   //tiled addressing
++        const UINT_32 macroWidthInTile = macroWidth / MicroTileWidth; // Now in unit of Tiles
++        const UINT_32 macroHeightInTile = macroHeight / MicroTileHeight;
++        const UINT_32 pitchInCL = pitchInTile / macroWidthInTile;
++        const UINT_32 heightInCL = heightInTile / macroHeightInTile;
++
++        const UINT_32 macroX = x / macroWidth;
++        const UINT_32 macroY = y / macroHeight;
++        const UINT_32 macroNumber = macroX + macroY * pitchInCL + slice * pitchInCL * heightInCL;
++
++        // Per pipe starting offset of the cache line in which this tile lies.
++        microX = (x % macroWidth) / MicroTileWidth / 4; // Macro Tile is 4x4
++        microY = (y % macroHeight) / MicroTileHeight / 4 ;
++        microNumber = static_cast<UINT_64>(microX + microY * (macroWidth / MicroTileWidth / 4)) << microShift;
++
++        macroOffset = macroNumber * tileNumPerPipe * elemBits;
++    }
++
++    if(elemIdxBits == microShift)
++    {
++        microNumber += elemIdx;
++    }
++    else
++    {
++        microNumber >>= elemIdxBits;
++        microNumber <<= elemIdxBits;
++        microNumber += elemIdx;
++    }
++
++    microOffset = elemBits * microNumber;
++    totalOffset = microOffset + macroOffset;
++
++    UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo);
++    UINT_64 addrInBits = totalOffset % (m_pipeInterleaveBytes * 8) +
++                   pipe * (m_pipeInterleaveBytes * 8) +
++                   totalOffset / (m_pipeInterleaveBytes * 8) * (m_pipeInterleaveBytes * 8) * numPipes;
++    *pBitPosition = static_cast<UINT_32>(addrInBits) % 8;
++    UINT_64 addr = addrInBits / 8;
++
++    return addr;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeXmaskCoordFromAddr
++*
++*   @brief
++*       Compute the coord from an address of a cmask/htile
++*
++*   @return
++*       N/A
++*
++*   @note
++*       This method is reused by htile, so rename to Xmask
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlComputeXmaskCoordFromAddr(
++    UINT_64         addr,           ///< [in] address
++    UINT_32         bitPosition,    ///< [in] bitPosition in a byte
++    UINT_32         pitch,          ///< [in] pitch
++    UINT_32         height,         ///< [in] height
++    UINT_32         numSlices,      ///< [in] number of slices
++    UINT_32         factor,         ///< [in] factor that indicates cmask or htile
++    BOOL_32         isLinear,       ///< [in] linear or tiled HTILE layout
++    BOOL_32         isWidth8,       ///< [in] Not used by SI
++    BOOL_32         isHeight8,      ///< [in] Not used by SI
++    ADDR_TILEINFO*  pTileInfo,      ///< [in] Tile info
++    UINT_32*        pX,             ///< [out] x coord
++    UINT_32*        pY,             ///< [out] y coord
++    UINT_32*        pSlice          ///< [out] slice index
++    ) const
++{
++    UINT_32 newPitch;
++    UINT_32 newHeight;
++    UINT_64 totalBytes;
++    UINT_32 clWidth;
++    UINT_32 clHeight;
++    UINT_32 tileNumPerPipe;
++    UINT_64 sliceBytes;
++
++    *pX = 0;
++    *pY = 0;
++    *pSlice = 0;
++
++    if (factor == 2) //CMASK
++    {
++        ADDR_CMASK_FLAGS flags = {{0}};
++
++        tileNumPerPipe = 256;
++
++        ComputeCmaskInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         pTileInfo,
++                         &newPitch,
++                         &newHeight,
++                         &totalBytes,
++                         &clWidth,
++                         &clHeight);
++    }
++    else //HTile
++    {
++        ADDR_HTILE_FLAGS flags = {{0}};
++
++        tileNumPerPipe = 512;
++
++        ComputeHtileInfo(flags,
++                         pitch,
++                         height,
++                         numSlices,
++                         isLinear,
++                         TRUE,
++                         TRUE,
++                         pTileInfo,
++                         &newPitch,
++                         &newHeight,
++                         &totalBytes,
++                         &clWidth,
++                         &clHeight,
++                         &sliceBytes);
++    }
++
++    const UINT_32 pitchInTile = newPitch / MicroTileWidth;
++    const UINT_32 heightInTile = newHeight / MicroTileWidth;
++    const UINT_32 pitchInMacroTile = pitchInTile / 4;
++    UINT_32 macroShift;
++    UINT_32 elemIdxBits;
++    // get macroShift and elemIdxBits
++    TileCoordToMaskElementIndex(0, 0, pTileInfo->pipeConfig, &macroShift, &elemIdxBits);
++
++    const UINT_32 numPipes = HwlGetPipes(pTileInfo);
++    const UINT_32 pipe = (UINT_32)((addr / m_pipeInterleaveBytes) % numPipes);
++    // per pipe
++    UINT_64 localOffset = (addr % m_pipeInterleaveBytes) +
++        (addr / m_pipeInterleaveBytes / numPipes)* m_pipeInterleaveBytes;
++
++    UINT_32 tileIndex;
++    if (factor == 2) //CMASK
++    {
++        tileIndex = (UINT_32)(localOffset * 2 + (bitPosition != 0));
++    }
++    else
++    {
++        tileIndex = (UINT_32)(localOffset / 4);
++    }
++
++    UINT_32 macroOffset;
++    if (isLinear)
++    {
++        UINT_32 sliceSizeInTile = pitchInTile * heightInTile;
++
++        // do htile single slice alignment if the flag is true
++        if (m_configFlags.useHtileSliceAlign && (factor == 1))  //Htile
++        {
++            sliceSizeInTile = PowTwoAlign(sliceSizeInTile, static_cast<UINT_32>(sliceBytes) / 64);
++        }
++        *pSlice = tileIndex / (sliceSizeInTile / numPipes);
++        macroOffset = tileIndex % (sliceSizeInTile / numPipes);
++    }
++    else
++    {
++        const UINT_32 clWidthInTile = clWidth / MicroTileWidth; // Now in unit of Tiles
++        const UINT_32 clHeightInTile = clHeight / MicroTileHeight;
++        const UINT_32 pitchInCL = pitchInTile / clWidthInTile;
++        const UINT_32 heightInCL = heightInTile / clHeightInTile;
++        const UINT_32 clIndex = tileIndex / tileNumPerPipe;
++
++        UINT_32 clX = clIndex % pitchInCL;
++        UINT_32 clY = (clIndex % (heightInCL * pitchInCL)) / pitchInCL;
++
++        *pX = clX * clWidthInTile * MicroTileWidth;
++        *pY = clY * clHeightInTile * MicroTileHeight;
++        *pSlice = clIndex / (heightInCL * pitchInCL);
++
++        macroOffset = tileIndex % tileNumPerPipe;
++    }
++
++    UINT_32 elemIdx = macroOffset & 7;
++    macroOffset >>= elemIdxBits;
++
++    if (elemIdxBits != macroShift)
++    {
++        macroOffset <<= (elemIdxBits - macroShift);
++
++        UINT_32 pipebit1 = _BIT(pipe,1);
++        UINT_32 pipebit2 = _BIT(pipe,2);
++        UINT_32 pipebit3 = _BIT(pipe,3);
++        if (pitchInMacroTile % 2)
++        {   //odd
++            switch (pTileInfo->pipeConfig)
++            {
++                case ADDR_PIPECFG_P4_32x32:
++                    macroOffset |= pipebit1;
++                    break;
++                case ADDR_PIPECFG_P8_32x32_8x16:
++                case ADDR_PIPECFG_P8_32x32_16x16:
++                case ADDR_PIPECFG_P8_32x32_16x32:
++                    macroOffset |= pipebit2;
++                    break;
++                default:
++                    break;
++            }
++
++        }
++
++        if (pitchInMacroTile % 4)
++        {
++            if (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)
++            {
++                macroOffset |= (pipebit1<<1);
++            }
++            if((pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
++               (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_16x16))
++            {
++                macroOffset |= (pipebit3<<1);
++            }
++        }
++    }
++
++    UINT_32 macroX;
++    UINT_32 macroY;
++
++    if (isLinear)
++    {
++        macroX = macroOffset % pitchInMacroTile;
++        macroY = macroOffset / pitchInMacroTile;
++    }
++    else
++    {
++        const UINT_32 clWidthInMacroTile = clWidth / (MicroTileWidth * 4);
++        macroX = macroOffset % clWidthInMacroTile;
++        macroY = macroOffset / clWidthInMacroTile;
++    }
++
++    *pX += macroX * 4 * MicroTileWidth;
++    *pY += macroY * 4 * MicroTileHeight;
++
++    UINT_32 microX;
++    UINT_32 microY;
++    ComputeTileCoordFromPipeAndElemIdx(elemIdx, pipe, pTileInfo->pipeConfig, pitchInMacroTile,
++                                       *pX, *pY, &microX, &microY);
++
++    *pX += microX * MicroTileWidth;
++    *pY += microY * MicroTileWidth;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlGetPitchAlignmentLinear
++*   @brief
++*       Get pitch alignment
++*   @return
++*       pitch alignment
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlGetPitchAlignmentLinear(
++    UINT_32             bpp,    ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags   ///< [in] surface flags
++    ) const
++{
++    UINT_32 pitchAlign;
++
++    // Interleaved access requires a 256B aligned pitch, so fall back to pre-SI alignment
++    if (flags.interleaved)
++    {
++        pitchAlign = Max(64u, m_pipeInterleaveBytes / BITS_TO_BYTES(bpp));
++
++    }
++    else
++    {
++        pitchAlign = Max(8u, 64 / BITS_TO_BYTES(bpp));
++    }
++
++    return pitchAlign;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlGetSizeAdjustmentLinear
++*
++*   @brief
++*       Adjust linear surface pitch and slice size
++*
++*   @return
++*       Logical slice size in bytes
++***************************************************************************************************
++*/
++UINT_64 SIAddrLib::HwlGetSizeAdjustmentLinear(
++    AddrTileMode        tileMode,       ///< [in] tile mode
++    UINT_32             bpp,            ///< [in] bits per pixel
++    UINT_32             numSamples,     ///< [in] number of samples
++    UINT_32             baseAlign,      ///< [in] base alignment
++    UINT_32             pitchAlign,     ///< [in] pitch alignment
++    UINT_32*            pPitch,         ///< [in/out] pointer to pitch
++    UINT_32*            pHeight,        ///< [in/out] pointer to height
++    UINT_32*            pHeightAlign    ///< [in/out] pointer to height align
++    ) const
++{
++    UINT_64 sliceSize;
++    if (tileMode == ADDR_TM_LINEAR_GENERAL)
++    {
++        sliceSize = BITS_TO_BYTES(static_cast<UINT_64>(*pPitch) * (*pHeight) * bpp * numSamples);
++    }
++    else
++    {
++        UINT_32 pitch   = *pPitch;
++        UINT_32 height  = *pHeight;
++
++        UINT_32 pixelsPerPipeInterleave = m_pipeInterleaveBytes / BITS_TO_BYTES(bpp);
++        UINT_32 sliceAlignInPixel = pixelsPerPipeInterleave < 64 ? 64 : pixelsPerPipeInterleave;
++
++        // numSamples should be 1 in real cases (no MSAA for linear but TGL may pass non 1 value)
++        UINT_64 pixelPerSlice = static_cast<UINT_64>(pitch) * height * numSamples;
++
++        while (pixelPerSlice % sliceAlignInPixel)
++        {
++            pitch += pitchAlign;
++            pixelPerSlice = static_cast<UINT_64>(pitch) * height * numSamples;
++        }
++
++        *pPitch = pitch;
++
++        UINT_32 heightAlign = 1;
++
++        while ((pitch * heightAlign) % sliceAlignInPixel)
++        {
++            heightAlign++;
++        }
++
++        *pHeightAlign = heightAlign;
++
++        sliceSize = BITS_TO_BYTES(pixelPerSlice * bpp);
++    }
++
++    return sliceSize;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlPreHandleBaseLvl3xPitch
++*
++*   @brief
++*       Pre-handler of 3x pitch (96 bit) adjustment
++*
++*   @return
++*       Expected pitch
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlPreHandleBaseLvl3xPitch(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] input
++    UINT_32                                 expPitch    ///< [in] pitch
++    ) const
++{
++    ADDR_ASSERT(pIn->width == expPitch);
++
++    // From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
++    // do here
++    if (!pIn->flags.pow2Pad)
++    {
++        AddrLib::HwlPreHandleBaseLvl3xPitch(pIn, expPitch);
++    }
++    else
++    {
++        ADDR_ASSERT(IsPow2(expPitch));
++    }
++
++    return expPitch;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlPostHandleBaseLvl3xPitch
++*
++*   @brief
++*       Post-handler of 3x pitch adjustment
++*
++*   @return
++*       Expected pitch
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlPostHandleBaseLvl3xPitch(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,        ///< [in] input
++    UINT_32                                 expPitch    ///< [in] pitch
++    ) const
++{
++    /**
++     * @note The pitch will be divided by 3 in the end so the value will look odd but h/w should
++     *  be able to compute a correct pitch from it as h/w address library is doing the job.
++     */
++    // From SI, the pitch is expanded 3x first, then padded to pow2, so no special handler here
++    if (!pIn->flags.pow2Pad)
++    {
++        AddrLib::HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
++    }
++
++    return expPitch;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlGetPitchAlignmentMicroTiled
++*
++*   @brief
++*       Compute 1D tiled surface pitch alignment
++*
++*   @return
++*       pitch alignment
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlGetPitchAlignmentMicroTiled(
++    AddrTileMode        tileMode,          ///< [in] tile mode
++    UINT_32             bpp,               ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,             ///< [in] surface flags
++    UINT_32             numSamples         ///< [in] number of samples
++    ) const
++{
++    UINT_32 pitchAlign;
++
++    if (flags.qbStereo)
++    {
++        pitchAlign = EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled(tileMode,bpp,flags,numSamples);
++    }
++    else
++    {
++        pitchAlign = 8;
++    }
++
++    return pitchAlign;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlGetSizeAdjustmentMicroTiled
++*
++*   @brief
++*       Adjust 1D tiled surface pitch and slice size
++*
++*   @return
++*       Logical slice size in bytes
++***************************************************************************************************
++*/
++UINT_64 SIAddrLib::HwlGetSizeAdjustmentMicroTiled(
++    UINT_32             thickness,      ///< [in] thickness
++    UINT_32             bpp,            ///< [in] bits per pixel
++    ADDR_SURFACE_FLAGS  flags,          ///< [in] surface flags
++    UINT_32             numSamples,     ///< [in] number of samples
++    UINT_32             baseAlign,      ///< [in] base alignment
++    UINT_32             pitchAlign,     ///< [in] pitch alignment
++    UINT_32*            pPitch,         ///< [in/out] pointer to pitch
++    UINT_32*            pHeight         ///< [in/out] pointer to height
++    ) const
++{
++    UINT_64 logicalSliceSize;
++    UINT_64 physicalSliceSize;
++
++    UINT_32 pitch   = *pPitch;
++    UINT_32 height  = *pHeight;
++
++    // Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so actually numSamples == 1)
++    logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
++
++    // Physical slice: multiplied by thickness
++    physicalSliceSize =  logicalSliceSize * thickness;
++
++    // Pitch alignment is always 8, so if slice size is not padded to base alignment
++    // (pipe_interleave_size), we need to increase pitch
++    while ((physicalSliceSize % baseAlign) != 0)
++    {
++        pitch += pitchAlign;
++
++        logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
++
++        physicalSliceSize =  logicalSliceSize * thickness;
++    }
++
++#if !ALT_TEST
++    //
++    // Special workaround for depth/stencil buffer, use 8 bpp to align depth buffer again since
++    // the stencil plane may have larger pitch if the slice size is smaller than base alignment.
++    //
++    // Note: this actually does not work for mipmap but mipmap depth texture is not really
++    // sampled with mipmap.
++    //
++    if (flags.depth && !flags.noStencil)
++    {
++        ADDR_ASSERT(numSamples == 1);
++
++        UINT_64 logicalSiceSizeStencil = static_cast<UINT_64>(pitch) * height; // 1 byte stencil
++
++        while ((logicalSiceSizeStencil % baseAlign) != 0)
++        {
++            pitch += pitchAlign; // Stencil plane's pitch alignment is the same as depth plane's
++
++            logicalSiceSizeStencil = static_cast<UINT_64>(pitch) * height;
++        }
++
++        if (pitch != *pPitch)
++        {
++            // If this is a mipmap, this padded one cannot be sampled as a whole mipmap!
++            logicalSliceSize = logicalSiceSizeStencil * BITS_TO_BYTES(bpp);
++        }
++    }
++#endif
++    *pPitch = pitch;
++
++    // No adjust for pHeight
++
++    return logicalSliceSize;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlConvertChipFamily
++*
++*   @brief
++*       Convert familyID defined in atiid.h to AddrChipFamily and set m_chipFamily/m_chipRevision
++*   @return
++*       AddrChipFamily
++***************************************************************************************************
++*/
++AddrChipFamily SIAddrLib::HwlConvertChipFamily(
++    UINT_32 uChipFamily,        ///< [in] chip family defined in atiih.h
++    UINT_32 uChipRevision)      ///< [in] chip revision defined in "asic_family"_id.h
++{
++    AddrChipFamily family = ADDR_CHIP_FAMILY_SI;
++
++    switch (uChipFamily)
++    {
++        case FAMILY_SI:
++            m_settings.isSouthernIsland = 1;
++            m_settings.isTahiti     = ASICREV_IS_TAHITI_P(uChipRevision);
++            m_settings.isPitCairn   = ASICREV_IS_PITCAIRN_PM(uChipRevision);
++            m_settings.isCapeVerde  = ASICREV_IS_CAPEVERDE_M(uChipRevision);
++            m_settings.isOland      = ASICREV_IS_OLAND_M(uChipRevision);
++            m_settings.isHainan     = ASICREV_IS_HAINAN_V(uChipRevision);
++            break;
++        default:
++            ADDR_ASSERT(!"This should be a Fusion");
++            break;
++    }
++
++    return family;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlSetupTileInfo
++*
++*   @brief
++*       Setup default value of tile info for SI
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlSetupTileInfo(
++    AddrTileMode                        tileMode,       ///< [in] Tile mode
++    ADDR_SURFACE_FLAGS                  flags,          ///< [in] Surface type flags
++    UINT_32                             bpp,            ///< [in] Bits per pixel
++    UINT_32                             pitch,          ///< [in] Pitch in pixels
++    UINT_32                             height,         ///< [in] Height in pixels
++    UINT_32                             numSamples,     ///< [in] Number of samples
++    ADDR_TILEINFO*                      pTileInfoIn,    ///< [in] Tile info input: NULL for default
++    ADDR_TILEINFO*                      pTileInfoOut,   ///< [out] Tile info output
++    AddrTileType                        inTileType,     ///< [in] Tile type
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*   pOut            ///< [out] Output
++    ) const
++{
++    UINT_32 thickness = ComputeSurfaceThickness(tileMode);
++    ADDR_TILEINFO* pTileInfo = pTileInfoOut;
++    INT index = TileIndexInvalid;
++
++    // Fail-safe code
++    if (!IsLinear(tileMode))
++    {
++        // 128 bpp/thick tiling must be non-displayable.
++        // Fmask reuse color buffer's entry but bank-height field can be from another entry
++        // To simplify the logic, fmask entry should be picked from non-displayable ones
++        if (bpp == 128 || thickness > 1 || flags.fmask || flags.prt)
++        {
++            inTileType = ADDR_NON_DISPLAYABLE;
++        }
++
++        if (flags.depth || flags.stencil)
++        {
++            inTileType = ADDR_DEPTH_SAMPLE_ORDER;
++        }
++    }
++
++    // Partial valid fields are not allowed for SI.
++    if (IsTileInfoAllZero(pTileInfo))
++    {
++        if (IsMacroTiled(tileMode))
++        {
++            if (flags.prt)
++            {
++                if (numSamples == 1)
++                {
++                    if (flags.depth)
++                    {
++                        switch (bpp)
++                        {
++                            case 16:
++                                index = 3;
++                                break;
++                            case 32:
++                                index = 6;
++                                break;
++                            default:
++                                ADDR_ASSERT_ALWAYS();
++                                break;
++                        }
++                    }
++                    else
++                    {
++                        switch (bpp)
++                        {
++                            case 8:
++                                index = 21;
++                                break;
++                            case 16:
++                                index = 22;
++                                break;
++                            case 32:
++                                index = 23;
++                                break;
++                            case 64:
++                                index = 24;
++                                break;
++                            case 128:
++                                index = 25;
++                                break;
++                            default:
++                                break;
++                        }
++
++                        if (thickness > 1)
++                        {
++                            ADDR_ASSERT(bpp != 128);
++                            index += 5;
++                        }
++                    }
++                }
++                else
++                {
++                    ADDR_ASSERT(numSamples == 4);
++
++                    if (flags.depth)
++                    {
++                        switch (bpp)
++                        {
++                            case 16:
++                                index = 5;
++                                break;
++                            case 32:
++                                index = 7;
++                                break;
++                            default:
++                                ADDR_ASSERT_ALWAYS();
++                                break;
++                        }
++                    }
++                    else
++                    {
++                        switch (bpp)
++                        {
++                            case 8:
++                                index = 23;
++                                break;
++                            case 16:
++                                index = 24;
++                                break;
++                            case 32:
++                                index = 25;
++                                break;
++                            case 64:
++                                index = 30;
++                                break;
++                            default:
++                                ADDR_ASSERT_ALWAYS();
++                                break;
++                        }
++                    }
++                }
++            }//end of PRT part
++            // See table entries 0-7
++            else if (flags.depth || flags.stencil)
++            {
++                if (flags.compressZ)
++                {
++                    if (flags.stencil)
++                    {
++                        index = 0;
++                    }
++                    else
++                    {
++                        // optimal tile index for compressed depth/stencil.
++                        switch (numSamples)
++                        {
++                            case 1:
++                                index = 0;
++                                break;
++                            case 2:
++                            case 4:
++                                index = 1;
++                                break;
++                            case 8:
++                                index = 2;
++                                break;
++                            default:
++                                break;
++                        }
++                    }
++                }
++                else // unCompressZ
++                {
++                    index = 3;
++                }
++            }
++            else //non PRT & non Depth & non Stencil
++            {
++                // See table entries 9-12
++                if (inTileType == ADDR_DISPLAYABLE)
++                {
++                    switch (bpp)
++                    {
++                        case 8:
++                            index = 10;
++                            break;
++                        case 16:
++                            index = 11;
++                            break;
++                        case 32:
++                            index = 12;
++                            break;
++                        case 64:
++                            index = 12;
++                            break;
++                        default:
++                            break;
++                    }
++                }
++                else
++                {
++                    // See table entries 13-17
++                    if (thickness == 1)
++                    {
++                        if (flags.fmask)
++                        {
++                            UINT_32 fmaskPixelSize = bpp * numSamples;
++
++                            switch (fmaskPixelSize)
++                            {
++                                case 8:
++                                    index = 14;
++                                    break;
++                                case 16:
++                                    index = 15;
++                                    break;
++                                case 32:
++                                    index = 16;
++                                    break;
++                                case 64:
++                                    index = 17;
++                                    break;
++                                default:
++                                    ADDR_ASSERT_ALWAYS();
++                            }
++                        }
++                        else
++                        {
++                            switch (bpp)
++                            {
++                                case 8:
++                                    index = 14;
++                                    break;
++                                case 16:
++                                    index = 15;
++                                    break;
++                                case 32:
++                                    index = 16;
++                                    break;
++                                case 64:
++                                    index = 17;
++                                    break;
++                                case 128:
++                                    index = 17;
++                                    break;
++                                default:
++                                    break;
++                            }
++                        }
++                    }
++                    else // thick tiling - entries 18-20
++                    {
++                        switch (thickness)
++                        {
++                            case 4:
++                                index = 20;
++                                break;
++                            case 8:
++                                index = 19;
++                                break;
++                            default:
++                                break;
++                        }
++                    }
++                }
++            }
++        }
++        else
++        {
++            if (tileMode == ADDR_TM_LINEAR_ALIGNED)
++            {
++                index = 8;
++            }
++            else if (tileMode == ADDR_TM_LINEAR_GENERAL)
++            {
++                index = TileIndexLinearGeneral;
++            }
++            else
++            {
++                if (flags.depth || flags.stencil)
++                {
++                    index = 4;
++                }
++                else if (inTileType == ADDR_DISPLAYABLE)
++                {
++                    index = 9;
++                }
++                else if (thickness == 1)
++                {
++                    index = 13;
++                }
++                else
++                {
++                    index = 18;
++                }
++            }
++        }
++
++        if (index >= 0 && index <= 31)
++        {
++            *pTileInfo      = m_tileTable[index].info;
++            pOut->tileType  = m_tileTable[index].type;
++        }
++
++        if (index == TileIndexLinearGeneral)
++        {
++            *pTileInfo      = m_tileTable[8].info;
++            pOut->tileType  = m_tileTable[8].type;
++        }
++    }
++    else
++    {
++        if (pTileInfoIn)
++        {
++            if (flags.stencil && pTileInfoIn->tileSplitBytes == 0)
++            {
++                // Stencil always uses index 0
++                *pTileInfo = m_tileTable[0].info;
++            }
++        }
++        // Pass through tile type
++        pOut->tileType = inTileType;
++    }
++
++    pOut->tileIndex = index;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::DecodeGbRegs
++*
++*   @brief
++*       Decodes GB_ADDR_CONFIG and noOfBanks/noOfRanks
++*
++*   @return
++*       TRUE if all settings are valid
++*
++***************************************************************************************************
++*/
++BOOL_32 SIAddrLib::DecodeGbRegs(
++    const ADDR_REGISTER_VALUE* pRegValue) ///< [in] create input
++{
++    GB_ADDR_CONFIG  reg;
++    BOOL_32         valid = TRUE;
++
++    reg.val = pRegValue->gbAddrConfig;
++
++    switch (reg.f.pipe_interleave_size)
++    {
++        case ADDR_CONFIG_PIPE_INTERLEAVE_256B:
++            m_pipeInterleaveBytes = ADDR_PIPEINTERLEAVE_256B;
++            break;
++        case ADDR_CONFIG_PIPE_INTERLEAVE_512B:
++            m_pipeInterleaveBytes = ADDR_PIPEINTERLEAVE_512B;
++            break;
++        default:
++            valid = FALSE;
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++
++    switch (reg.f.row_size)
++    {
++        case ADDR_CONFIG_1KB_ROW:
++            m_rowSize = ADDR_ROWSIZE_1KB;
++            break;
++        case ADDR_CONFIG_2KB_ROW:
++            m_rowSize = ADDR_ROWSIZE_2KB;
++            break;
++        case ADDR_CONFIG_4KB_ROW:
++            m_rowSize = ADDR_ROWSIZE_4KB;
++            break;
++        default:
++            valid = FALSE;
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++
++    switch (pRegValue->noOfBanks)
++    {
++        case 0:
++            m_banks = 4;
++            break;
++        case 1:
++            m_banks = 8;
++            break;
++        case 2:
++            m_banks = 16;
++            break;
++        default:
++            valid = FALSE;
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++
++    switch (pRegValue->noOfRanks)
++    {
++        case 0:
++            m_ranks = 1;
++            break;
++        case 1:
++            m_ranks = 2;
++            break;
++        default:
++            valid = FALSE;
++            ADDR_UNHANDLED_CASE();
++            break;
++    }
++
++    m_logicalBanks = m_banks * m_ranks;
++
++    ADDR_ASSERT(m_logicalBanks <= 16);
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlInitGlobalParams
++*
++*   @brief
++*       Initializes global parameters
++*
++*   @return
++*       TRUE if all settings are valid
++*
++***************************************************************************************************
++*/
++BOOL_32 SIAddrLib::HwlInitGlobalParams(
++    const ADDR_CREATE_INPUT* pCreateIn) ///< [in] create input
++{
++    BOOL_32 valid = TRUE;
++    const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue;
++
++    valid = DecodeGbRegs(pRegValue);
++
++    if (valid)
++    {
++        if (m_settings.isTahiti || m_settings.isPitCairn)
++        {
++            m_pipes = 8;
++        }
++        else if (m_settings.isCapeVerde || m_settings.isOland)
++        {
++            m_pipes = 4;
++        }
++        else
++        {
++            // Hainan is 2-pipe (m_settings.isHainan == 1)
++            m_pipes = 2;
++        }
++
++        valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries);
++
++        m_maxSamples = 16;
++    }
++
++    return valid;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlConvertTileInfoToHW
++*   @brief
++*       Entry of si's ConvertTileInfoToHW
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE SIAddrLib::HwlConvertTileInfoToHW(
++    const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, ///< [in] input structure
++    ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut      ///< [out] output structure
++    ) const
++{
++    ADDR_E_RETURNCODE retCode   = ADDR_OK;
++
++    retCode = EgBasedAddrLib::HwlConvertTileInfoToHW(pIn, pOut);
++
++    if (retCode == ADDR_OK)
++    {
++        if (pIn->reverse == FALSE)
++        {
++            if (pIn->pTileInfo->pipeConfig == ADDR_PIPECFG_INVALID)
++            {
++                retCode = ADDR_INVALIDPARAMS;
++            }
++            else
++            {
++                pOut->pTileInfo->pipeConfig =
++                    static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig - 1);
++            }
++        }
++        else
++        {
++            pOut->pTileInfo->pipeConfig =
++                static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig + 1);
++        }
++    }
++
++    return retCode;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeXmaskCoordYFrom8Pipe
++*
++*   @brief
++*       Compute the Y coord which will be added to Xmask Y
++*       coord.
++*   @return
++*       Y coord
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlComputeXmaskCoordYFrom8Pipe(
++    UINT_32         pipe,       ///< [in] pipe id
++    UINT_32         x           ///< [in] tile coord x, which is original x coord / 8
++    ) const
++{
++    // This function should never be called since it is 6xx/8xx specfic.
++    // Keep this empty implementation to avoid any mis-use.
++    ADDR_ASSERT_ALWAYS();
++
++    return 0;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeSurfaceCoord2DFromBankPipe
++*
++*   @brief
++*       Compute surface x,y coordinates from bank/pipe info
++*   @return
++*       N/A
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlComputeSurfaceCoord2DFromBankPipe(
++    AddrTileMode        tileMode,   ///< [in] tile mode
++    UINT_32*            pX,         ///< [in/out] x coordinate
++    UINT_32*            pY,         ///< [in/out] y coordinate
++    UINT_32             slice,      ///< [in] slice index
++    UINT_32             bank,       ///< [in] bank number
++    UINT_32             pipe,       ///< [in] pipe number
++    UINT_32             bankSwizzle,///< [in] bank swizzle
++    UINT_32             pipeSwizzle,///< [in] pipe swizzle
++    UINT_32             tileSlices, ///< [in] slices in a micro tile
++    BOOL_32             ignoreSE,   ///< [in] TRUE if shader engines are ignored
++    ADDR_TILEINFO*      pTileInfo   ///< [in] bank structure. **All fields to be valid on entry**
++    ) const
++{
++    UINT_32 xBit;
++    UINT_32 yBit;
++    UINT_32 yBit3 = 0;
++    UINT_32 yBit4 = 0;
++    UINT_32 yBit5 = 0;
++    UINT_32 yBit6 = 0;
++
++    UINT_32 xBit3 = 0;
++    UINT_32 xBit4 = 0;
++    UINT_32 xBit5 = 0;
++
++    UINT_32 numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
++
++    CoordFromBankPipe xyBits = {0};
++    ComputeSurfaceCoord2DFromBankPipe(tileMode, *pX, *pY, slice, bank, pipe,
++                                      bankSwizzle, pipeSwizzle, tileSlices, pTileInfo,
++                                      &xyBits);
++    yBit3 = xyBits.yBit3;
++    yBit4 = xyBits.yBit4;
++    yBit5 = xyBits.yBit5;
++    yBit6 = xyBits.yBit6;
++
++    xBit3 = xyBits.xBit3;
++    xBit4 = xyBits.xBit4;
++    xBit5 = xyBits.xBit5;
++
++    yBit = xyBits.yBits;
++
++    UINT_32 yBitTemp = 0;
++
++    if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
++        (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32))
++    {
++        ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1);
++        UINT_32 yBitToCheck = QLog2(pTileInfo->banks) - 1;
++
++        ADDR_ASSERT(yBitToCheck <= 3);
++
++        yBitTemp = _BIT(yBit, yBitToCheck);
++
++        xBit3 = 0;
++    }
++
++    yBit = Bits2Number(4, yBit6, yBit5, yBit4, yBit3);
++    xBit = Bits2Number(3, xBit5, xBit4, xBit3);
++
++    *pY += yBit * pTileInfo->bankHeight * MicroTileHeight;
++    *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth;
++
++    //calculate the bank and pipe bits in x, y
++    UINT_32 xTile; //x in micro tile
++    UINT_32 x3 = 0;
++    UINT_32 x4 = 0;
++    UINT_32 x5 = 0;
++    UINT_32 x6 = 0;
++    UINT_32 y = *pY;
++
++    UINT_32 pipeBit0 = _BIT(pipe,0);
++    UINT_32 pipeBit1 = _BIT(pipe,1);
++    UINT_32 pipeBit2 = _BIT(pipe,2);
++
++    UINT_32 y3 = _BIT(y, 3);
++    UINT_32 y4 = _BIT(y, 4);
++    UINT_32 y5 = _BIT(y, 5);
++    UINT_32 y6 = _BIT(y, 6);
++
++    // bankbit0 after ^x4^x5
++    UINT_32 bankBit00 = _BIT(bank,0);
++    UINT_32 bankBit0 = 0;
++
++    switch (pTileInfo->pipeConfig)
++    {
++        case ADDR_PIPECFG_P2:
++            x3 = pipeBit0 ^ y3;
++            break;
++        case ADDR_PIPECFG_P4_8x16:
++            x4 = pipeBit0 ^ y3;
++            x3 = pipeBit0 ^ y4;
++            break;
++        case ADDR_PIPECFG_P4_16x16:
++            x4 = pipeBit1 ^ y4;
++            x3 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P4_16x32:
++            x4 = pipeBit1 ^ y4;
++            x3 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P4_32x32:
++            x5 = pipeBit1 ^ y5;
++            x3 = pipeBit0 ^ y3 ^ x5;
++            bankBit0 = yBitTemp ^ x5;
++            x4 = bankBit00 ^ x5 ^ bankBit0;
++            *pX += x5 * 4 * 1 * 8; // x5 * num_pipes * bank_width * 8;
++            break;
++        case ADDR_PIPECFG_P8_16x16_8x16:
++            x3 = pipeBit1 ^ y5;
++            x4 = pipeBit2 ^ y4;
++            x5 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P8_16x32_8x16:
++            x3 = pipeBit1 ^ y4;
++            x4 = pipeBit2 ^ y5;
++            x5 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P8_32x32_8x16:
++            x3 = pipeBit1 ^ y4;
++            x5 = pipeBit2 ^ y5;
++            x4 = pipeBit0 ^ y3 ^ x5;
++            break;
++        case ADDR_PIPECFG_P8_16x32_16x16:
++            x4 = pipeBit2 ^ y5;
++            x5 = pipeBit1 ^ y4;
++            x3 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x16:
++            x5 = pipeBit2 ^ y5;
++            x4 = pipeBit1 ^ y4;
++            x3 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P8_32x32_16x32:
++            x5 = pipeBit2 ^ y5;
++            x4 = pipeBit1 ^ y6;
++            x3 = pipeBit0 ^ y3 ^ x4;
++            break;
++        case ADDR_PIPECFG_P8_32x64_32x32:
++            x6 = pipeBit1 ^ y5;
++            x5 = pipeBit2 ^ y6;
++            x3 = pipeBit0 ^ y3 ^ x5;
++            bankBit0 = yBitTemp ^ x6;
++            x4 = bankBit00 ^ x5 ^ bankBit0;
++            *pX += x6 * 8 * 1 * 8; // x6 * num_pipes * bank_width * 8;
++            break;
++        default:
++            ADDR_ASSERT_ALWAYS();
++    }
++
++    xTile = Bits2Number(3, x5, x4, x3);
++
++    *pX += xTile << 3;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlPreAdjustBank
++*
++*   @brief
++*       Adjust bank before calculating address acoording to bank/pipe
++*   @return
++*       Adjusted bank
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlPreAdjustBank(
++    UINT_32         tileX,      ///< [in] x coordinate in unit of tile
++    UINT_32         bank,       ///< [in] bank
++    ADDR_TILEINFO*  pTileInfo   ///< [in] tile info
++    ) const
++{
++    if (((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
++        (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1))
++    {
++        UINT_32 bankBit0 = _BIT(bank, 0);
++        UINT_32 x4 = _BIT(tileX, 1);
++        UINT_32 x5 = _BIT(tileX, 2);
++
++        bankBit0 = bankBit0 ^ x4 ^ x5;
++        bank |= bankBit0;
++
++        ADDR_ASSERT(pTileInfo->macroAspectRatio > 1)
++    }
++
++    return bank;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeSurfaceInfo
++*
++*   @brief
++*       Entry of si's ComputeSurfaceInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE SIAddrLib::HwlComputeSurfaceInfo(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,    ///< [in] input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut    ///< [out] output structure
++    ) const
++{
++    pOut->tileIndex = pIn->tileIndex;
++
++    return EgBasedAddrLib::HwlComputeSurfaceInfo(pIn,pOut);
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeMipLevel
++*   @brief
++*       Compute MipLevel info (including level 0)
++*   @return
++*       TRUE if HWL's handled
++***************************************************************************************************
++*/
++BOOL_32 SIAddrLib::HwlComputeMipLevel(
++    ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
++    ) const
++{
++    // basePitch is calculated from level 0 so we only check this for mipLevel > 0
++    if (pIn->mipLevel > 0)
++    {
++        // Note: Don't check expand 3x formats(96 bit) as the basePitch is not pow2 even if
++        // we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being
++        // divided by expandX factor (3) - to program texture pitch, the basePitch is never pow2.
++        if (!AddrElemLib::IsExpand3x(pIn->format))
++        {
++            // Sublevel pitches are generated from base level pitch instead of width on SI
++            // If pow2Pad is 0, we don't assert - as this is not really used for a mip chain
++            ADDR_ASSERT(!pIn->flags.pow2Pad || ((pIn->basePitch != 0) && IsPow2(pIn->basePitch)));
++        }
++
++        if (pIn->basePitch != 0)
++        {
++            pIn->width = Max(1u, pIn->basePitch >> pIn->mipLevel);
++        }
++    }
++
++    // pow2Pad is done in PostComputeMipLevel
++
++    return TRUE;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlCheckLastMacroTiledLvl
++*
++*   @brief
++*       Sets pOut->last2DLevel to TRUE if it is
++*   @note
++*
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlCheckLastMacroTiledLvl(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut      ///< [in/out] Output structure (used as input, too)
++    ) const
++{
++    // pow2Pad covers all mipmap cases
++    if (pIn->flags.pow2Pad)
++    {
++        ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
++
++        UINT_32 nextPitch;
++        UINT_32 nextHeight;
++        UINT_32 nextSlices;
++
++        AddrTileMode nextTileMode;
++
++        if (pIn->mipLevel == 0 || pIn->basePitch == 0)
++        {
++            // Base level or fail-safe case (basePitch == 0)
++            nextPitch = pOut->pitch >> 1;
++        }
++        else
++        {
++            // Sub levels
++            nextPitch = pIn->basePitch >> (pIn->mipLevel + 1);
++        }
++
++        // nextHeight must be shifted from this level's original height rather than a pow2 padded
++        // one but this requires original height stored somewhere (pOut->height)
++        ADDR_ASSERT(pOut->height != 0);
++
++        // next level's height is just current level's >> 1 in pixels
++        nextHeight = pOut->height >> 1;
++        // Special format such as FMT_1 and FMT_32_32_32 can be linear only so we consider block
++        // compressed foramts
++        if (AddrElemLib::IsBlockCompressed(pIn->format))
++        {
++            nextHeight = (nextHeight + 3) / 4;
++        }
++        nextHeight = NextPow2(nextHeight);
++
++        // nextSlices may be 0 if this level's is 1
++        if (pIn->flags.volume)
++        {
++            nextSlices = Max(1u, pIn->numSlices >> 1);
++        }
++        else
++        {
++            nextSlices = pIn->numSlices;
++        }
++
++        nextTileMode = ComputeSurfaceMipLevelTileMode(pIn->tileMode,
++                                                      pIn->bpp,
++                                                      nextPitch,
++                                                      nextHeight,
++                                                      nextSlices,
++                                                      pIn->numSamples,
++                                                      pOut->pitchAlign,
++                                                      pOut->heightAlign,
++                                                      pOut->pTileInfo);
++
++        pOut->last2DLevel = IsMicroTiled(nextTileMode);
++    }
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlDegradeThickTileMode
++*
++*   @brief
++*       Degrades valid tile mode for thick modes if needed
++*
++*   @return
++*       Suitable tile mode
++***************************************************************************************************
++*/
++AddrTileMode SIAddrLib::HwlDegradeThickTileMode(
++    AddrTileMode        baseTileMode,   ///< [in] base tile mode
++    UINT_32             numSlices,      ///< [in] current number of slices
++    UINT_32*            pBytesPerTile   ///< [in/out] pointer to bytes per slice
++    ) const
++{
++    return EgBasedAddrLib::HwlDegradeThickTileMode(baseTileMode, numSlices, pBytesPerTile);
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlTileInfoEqual
++*
++*   @brief
++*       Return TRUE if all field are equal
++*   @note
++*       Only takes care of current HWL's data
++***************************************************************************************************
++*/
++BOOL_32 SIAddrLib::HwlTileInfoEqual(
++    const ADDR_TILEINFO* pLeft, ///<[in] Left compare operand
++    const ADDR_TILEINFO* pRight ///<[in] Right compare operand
++    ) const
++{
++    BOOL_32 equal = FALSE;
++
++    if (pLeft->pipeConfig == pRight->pipeConfig)
++    {
++        equal =  EgBasedAddrLib::HwlTileInfoEqual(pLeft, pRight);
++    }
++
++    return equal;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::GetTileSettings
++*
++*   @brief
++*       Get tile setting infos by index.
++*   @return
++*       Tile setting info.
++***************************************************************************************************
++*/
++const ADDR_TILECONFIG* SIAddrLib::GetTileSetting(
++    UINT_32 index          ///< [in] Tile index
++    ) const
++{
++    ADDR_ASSERT(index < m_noOfEntries);
++    return &m_tileTable[index];
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlPostCheckTileIndex
++*
++*   @brief
++*       Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
++*       tile mode/type/info and change the index if needed
++*   @return
++*       Tile index.
++***************************************************************************************************
++*/
++INT_32 SIAddrLib::HwlPostCheckTileIndex(
++    const ADDR_TILEINFO* pInfo,     ///< [in] Tile Info
++    AddrTileMode         mode,      ///< [in] Tile mode
++    AddrTileType         type,      ///< [in] Tile type
++    INT                  curIndex   ///< [in] Current index assigned in HwlSetupTileInfo
++    ) const
++{
++    INT_32 index = curIndex;
++
++    if (mode == ADDR_TM_LINEAR_GENERAL)
++    {
++        index = TileIndexLinearGeneral;
++    }
++    else
++    {
++        BOOL_32 macroTiled = IsMacroTiled(mode);
++
++        // We need to find a new index if either of them is true
++        // 1. curIndex is invalid
++        // 2. tile mode is changed
++        // 3. tile info does not match for macro tiled
++        if ((index == TileIndexInvalid         ||
++            (mode != m_tileTable[index].mode)  ||
++            (macroTiled && !HwlTileInfoEqual(pInfo, &m_tileTable[index].info))))
++        {
++            for (index = 0; index < static_cast<INT_32>(m_noOfEntries); index++)
++            {
++                if (macroTiled)
++                {
++                    // macro tile modes need all to match
++                    if (HwlTileInfoEqual(pInfo, &m_tileTable[index].info) &&
++                        (mode == m_tileTable[index].mode)                 &&
++                        (type == m_tileTable[index].type))
++                    {
++                        break;
++                    }
++                }
++                else if (mode == ADDR_TM_LINEAR_ALIGNED)
++                {
++                    // linear mode only needs tile mode to match
++                    if (mode == m_tileTable[index].mode)
++                    {
++                        break;
++                    }
++                }
++                else
++                {
++                    // micro tile modes only need tile mode and tile type to match
++                    if (mode == m_tileTable[index].mode &&
++                        type == m_tileTable[index].type)
++                    {
++                        break;
++                    }
++                }
++            }
++        }
++    }
++
++    ADDR_ASSERT(index < static_cast<INT_32>(m_noOfEntries));
++
++    if (index >= static_cast<INT_32>(m_noOfEntries))
++    {
++        index = TileIndexInvalid;
++    }
++
++    return index;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlSetupTileCfg
++*
++*   @brief
++*       Map tile index to tile setting.
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE SIAddrLib::HwlSetupTileCfg(
++    INT_32          index,          ///< [in] Tile index
++    INT_32          macroModeIndex, ///< [in] Index in macro tile mode table(CI)
++    ADDR_TILEINFO*  pInfo,          ///< [out] Tile Info
++    AddrTileMode*   pMode,          ///< [out] Tile mode
++    AddrTileType*   pType          ///< [out] Tile type
++    ) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    // Global flag to control usage of tileIndex
++    if (UseTileIndex(index))
++    {
++        if (index == TileIndexLinearGeneral)
++        {
++            if (pMode)
++            {
++                *pMode = ADDR_TM_LINEAR_GENERAL;
++            }
++
++            if (pType)
++            {
++                *pType = ADDR_DISPLAYABLE;
++            }
++
++            if (pInfo)
++            {
++                pInfo->banks = 2;
++                pInfo->bankWidth = 1;
++                pInfo->bankHeight = 1;
++                pInfo->macroAspectRatio = 1;
++                pInfo->tileSplitBytes = 64;
++                pInfo->pipeConfig = ADDR_PIPECFG_P2;
++            }
++        }
++        else if (static_cast<UINT_32>(index) >= m_noOfEntries)
++        {
++            returnCode = ADDR_INVALIDPARAMS;
++        }
++        else
++        {
++            const ADDR_TILECONFIG* pCfgTable = GetTileSetting(index);
++
++            if (pInfo)
++            {
++                *pInfo = pCfgTable->info;
++            }
++            else
++            {
++                if (IsMacroTiled(pCfgTable->mode))
++                {
++                    returnCode = ADDR_INVALIDPARAMS;
++                }
++            }
++
++            if (pMode)
++            {
++                *pMode = pCfgTable->mode;
++            }
++
++            if (pType)
++            {
++                *pType = pCfgTable->type;
++            }
++        }
++    }
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::ReadGbTileMode
++*
++*   @brief
++*       Convert GB_TILE_MODE HW value to ADDR_TILE_CONFIG.
++*   @return
++*       NA.
++***************************************************************************************************
++*/
++VOID SIAddrLib::ReadGbTileMode(
++    UINT_32             regValue,   ///< [in] GB_TILE_MODE register
++    ADDR_TILECONFIG*    pCfg        ///< [out] output structure
++    ) const
++{
++    GB_TILE_MODE gbTileMode;
++    gbTileMode.val = regValue;
++
++    pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode);
++    pCfg->info.bankHeight = 1 << gbTileMode.f.bank_height;
++    pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
++    pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1);
++    pCfg->info.macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
++    pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
++    pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
++
++    UINT_32 regArrayMode = gbTileMode.f.array_mode;
++
++    pCfg->mode = static_cast<AddrTileMode>(regArrayMode);
++
++    if (regArrayMode == 8) //ARRAY_2D_TILED_XTHICK
++    {
++        pCfg->mode = ADDR_TM_2D_TILED_XTHICK;
++    }
++    else if (regArrayMode >= 14) //ARRAY_3D_TILED_XTHICK
++    {
++        pCfg->mode = static_cast<AddrTileMode>(pCfg->mode + 3);
++    }
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::InitTileSettingTable
++*
++*   @brief
++*       Initialize the ADDR_TILE_CONFIG table.
++*   @return
++*       TRUE if tile table is correctly initialized
++***************************************************************************************************
++*/
++BOOL_32 SIAddrLib::InitTileSettingTable(
++    const UINT_32*  pCfg,           ///< [in] Pointer to table of tile configs
++    UINT_32         noOfEntries     ///< [in] Numbe of entries in the table above
++    )
++{
++    BOOL_32 initOk = TRUE;
++
++    ADDR_ASSERT(noOfEntries <= TileTableSize);
++
++    memset(m_tileTable, 0, sizeof(m_tileTable));
++
++    if (noOfEntries != 0)
++    {
++        m_noOfEntries = noOfEntries;
++    }
++    else
++    {
++        m_noOfEntries = TileTableSize;
++    }
++
++    if (pCfg) // From Client
++    {
++        for (UINT_32 i = 0; i < m_noOfEntries; i++)
++        {
++            ReadGbTileMode(*(pCfg + i), &m_tileTable[i]);
++        }
++    }
++    else
++    {
++        ADDR_ASSERT_ALWAYS();
++        initOk = FALSE;
++    }
++
++    if (initOk)
++    {
++        ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED);
++    }
++
++    return initOk;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlGetTileIndex
++*
++*   @brief
++*       Return the virtual/real index for given mode/type/info
++*   @return
++*       ADDR_OK if successful.
++***************************************************************************************************
++*/
++ADDR_E_RETURNCODE SIAddrLib::HwlGetTileIndex(
++    const ADDR_GET_TILEINDEX_INPUT* pIn,
++    ADDR_GET_TILEINDEX_OUTPUT*      pOut) const
++{
++    ADDR_E_RETURNCODE returnCode = ADDR_OK;
++
++    pOut->index = HwlPostCheckTileIndex(pIn->pTileInfo, pIn->tileMode, pIn->tileType);
++
++    return returnCode;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlFmaskPreThunkSurfInfo
++*
++*   @brief
++*       Some preparation before thunking a ComputeSurfaceInfo call for Fmask
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlFmaskPreThunkSurfInfo(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT*    pFmaskIn,   ///< [in] Input of fmask info
++    const ADDR_COMPUTE_FMASK_INFO_OUTPUT*   pFmaskOut,  ///< [in] Output of fmask info
++    ADDR_COMPUTE_SURFACE_INFO_INPUT*        pSurfIn,    ///< [out] Input of thunked surface info
++    ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pSurfOut    ///< [out] Output of thunked surface info
++    ) const
++{
++    pSurfIn->tileIndex = pFmaskIn->tileIndex;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlFmaskPostThunkSurfInfo
++*
++*   @brief
++*       Copy hwl extra field after calling thunked ComputeSurfaceInfo
++*   @return
++*       ADDR_E_RETURNCODE
++***************************************************************************************************
++*/
++VOID SIAddrLib::HwlFmaskPostThunkSurfInfo(
++    const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,   ///< [in] Output of surface info
++    ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut           ///< [out] Output of fmask info
++    ) const
++{
++    pFmaskOut->macroModeIndex = TileIndexInvalid;
++    pFmaskOut->tileIndex = pSurfOut->tileIndex;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlComputeFmaskBits
++*   @brief
++*       Computes fmask bits
++*   @return
++*       Fmask bits
++***************************************************************************************************
++*/
++UINT_32 SIAddrLib::HwlComputeFmaskBits(
++    const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++    UINT_32* pNumSamples
++    ) const
++{
++    UINT_32 numSamples = pIn->numSamples;
++    UINT_32 numFrags = GetNumFragments(numSamples, pIn->numFrags);
++    UINT_32 bpp;
++
++    if (numFrags != numSamples) // EQAA
++    {
++        ADDR_ASSERT(numFrags <= 8);
++
++        if (!pIn->resolved)
++        {
++            if (numFrags == 1)
++            {
++                bpp          = 1;
++                numSamples   = numSamples == 16 ? 16 : 8;
++            }
++            else if (numFrags == 2)
++            {
++                ADDR_ASSERT(numSamples >= 4);
++
++                bpp          = 2;
++                numSamples   = numSamples;
++            }
++            else if (numFrags == 4)
++            {
++                ADDR_ASSERT(numSamples >= 4);
++
++                bpp          = 4;
++                numSamples   = numSamples;
++            }
++            else // numFrags == 8
++            {
++                ADDR_ASSERT(numSamples == 16);
++
++                bpp          = 4;
++                numSamples   = numSamples;
++            }
++        }
++        else
++        {
++            if (numFrags == 1)
++            {
++                bpp          = (numSamples == 16) ? 16 : 8;
++                numSamples   = 1;
++            }
++            else if (numFrags == 2)
++            {
++                ADDR_ASSERT(numSamples >= 4);
++
++                bpp          = numSamples*2;
++                numSamples   = 1;
++            }
++            else if (numFrags == 4)
++            {
++                ADDR_ASSERT(numSamples >= 4);
++
++                bpp          = numSamples*4;
++                numSamples   = 1;
++            }
++            else // numFrags == 8
++            {
++                ADDR_ASSERT(numSamples >= 16);
++
++                bpp          = 16*4;
++                numSamples   = 1;
++            }
++        }
++    }
++    else // Normal AA
++    {
++        if (!pIn->resolved)
++        {
++            bpp          = ComputeFmaskNumPlanesFromNumSamples(numSamples);
++            numSamples   = numSamples == 2 ? 8 : numSamples;
++        }
++        else
++        {
++            // The same as 8XX
++            bpp          = ComputeFmaskResolvedBppFromNumSamples(numSamples);
++            numSamples   = 1; // 1x sample
++        }
++    }
++
++    SafeAssign(pNumSamples, numSamples);
++
++    return bpp;
++}
++
++/**
++***************************************************************************************************
++*   SIAddrLib::HwlOverrideTileMode
++*
++*   @brief
++*       Override tile modes (for PRT only, avoid client passes in an invalid PRT mode for SI.
++*
++*   @return
++*       Suitable tile mode
++*
++***************************************************************************************************
++*/
++BOOL_32 SIAddrLib::HwlOverrideTileMode(
++    const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,       ///< [in] input structure
++    AddrTileMode*                           pTileMode, ///< [in/out] pointer to the tile mode
++    AddrTileType*                           pTileType  ///< [in/out] pointer to the tile type
++    ) const
++{
++    BOOL_32 bOverrided = FALSE;
++    AddrTileMode tileMode = *pTileMode;
++
++    switch (tileMode)
++    {
++        case ADDR_TM_PRT_TILED_THIN1:
++            tileMode    = ADDR_TM_2D_TILED_THIN1;
++            break;
++
++        case ADDR_TM_PRT_TILED_THICK:
++            tileMode    = ADDR_TM_2D_TILED_THICK;
++            break;
++
++        case ADDR_TM_PRT_2D_TILED_THICK:
++            tileMode    = ADDR_TM_2D_TILED_THICK;
++            break;
++
++        case ADDR_TM_PRT_3D_TILED_THICK:
++            tileMode    = ADDR_TM_3D_TILED_THICK;
++            break;
++
++        default:
++            break;
++    }
++
++    if (tileMode != *pTileMode)
++    {
++        *pTileMode = tileMode;
++        bOverrided = TRUE;
++        ADDR_ASSERT(pIn->flags.prt == TRUE);
++    }
++
++    return bOverrided;
++}
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.h b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.h
+new file mode 100644
+index 0000000..897beb1
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/addrlib/r800/siaddrlib.h
+@@ -0,0 +1,262 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++***************************************************************************************************
++* @file  siaddrlib.h
++* @brief Contains the R800AddrLib class definition.
++***************************************************************************************************
++*/
++
++#ifndef __SI_ADDR_LIB_H__
++#define __SI_ADDR_LIB_H__
++
++#include "addrlib.h"
++#include "egbaddrlib.h"
++
++/**
++***************************************************************************************************
++* @brief Describes the information in tile mode table
++***************************************************************************************************
++*/
++struct ADDR_TILECONFIG
++{
++    AddrTileMode  mode;
++    AddrTileType  type;
++    ADDR_TILEINFO info;
++};
++
++/**
++***************************************************************************************************
++* @brief SI specific settings structure.
++***************************************************************************************************
++*/
++struct SIChipSettings
++{
++    struct
++    {
++        UINT_32 isSouthernIsland    : 1;
++        UINT_32 isTahiti            : 1;
++        UINT_32 isPitCairn          : 1;
++        UINT_32 isCapeVerde         : 1;
++        /// Oland/Hainan are of GFXIP 6.0, similar with SI
++        UINT_32 isOland             : 1;
++        UINT_32 isHainan            : 1;
++    };
++};
++
++/**
++***************************************************************************************************
++* @brief This class is the SI specific address library
++*        function set.
++***************************************************************************************************
++*/
++class SIAddrLib : public EgBasedAddrLib
++{
++public:
++    /// Creates SIAddrLib object
++    static AddrLib* CreateObj(const AddrClient* pClient)
++    {
++        return new(pClient) SIAddrLib(pClient);
++    }
++
++protected:
++    SIAddrLib(const AddrClient* pClient);
++    virtual ~SIAddrLib();
++
++    // Hwl interface - defined in AddrLib
++    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
++        const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
++        ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
++
++    virtual UINT_64 HwlComputeXmaskAddrFromCoord(
++        UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 numSlices,
++        UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
++        ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const;
++
++    virtual VOID HwlComputeXmaskCoordFromAddr(
++        UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
++        UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
++        ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
++
++    virtual ADDR_E_RETURNCODE HwlGetTileIndex(
++        const ADDR_GET_TILEINDEX_INPUT* pIn,
++        ADDR_GET_TILEINDEX_OUTPUT*      pOut) const;
++
++    virtual BOOL_32 HwlComputeMipLevel(
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
++
++    virtual AddrChipFamily HwlConvertChipFamily(
++        UINT_32 uChipFamily, UINT_32 uChipRevision);
++
++    virtual BOOL_32 HwlInitGlobalParams(
++        const ADDR_CREATE_INPUT* pCreateIn);
++
++    virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
++        INT_32 index, INT_32 macroModeIndex,
++        ADDR_TILEINFO* pInfo, AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
++
++    virtual VOID HwlComputeTileDataWidthAndHeightLinear(
++        UINT_32* pMacroWidth, UINT_32* pMacroHeight,
++        UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
++
++    virtual UINT_64 HwlComputeHtileBytes(
++        UINT_32 pitch, UINT_32 height, UINT_32 bpp,
++        BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
++
++    virtual UINT_32 ComputePipeFromCoord(
++        UINT_32 x, UINT_32 y, UINT_32 slice,
++        AddrTileMode tileMode, UINT_32 pipeSwizzle, BOOL_32 ignoreSE,
++        ADDR_TILEINFO* pTileInfo) const;
++
++    virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const;
++
++    /// Pre-handler of 3x pitch (96 bit) adjustment
++    virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
++    /// Post-handler of 3x pitch adjustment
++    virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
++
++    /// Dummy function to finalize the inheritance
++    virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
++        UINT_32 pipe, UINT_32 x) const;
++
++    // Sub-hwl interface - defined in EgBasedAddrLib
++    virtual VOID HwlSetupTileInfo(
++        AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
++        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
++        ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
++        AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    virtual UINT_32 HwlGetPitchAlignmentMicroTiled(
++        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const;
++
++    virtual UINT_64 HwlGetSizeAdjustmentMicroTiled(
++        UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
++        UINT_32 baseAlign, UINT_32 pitchAlign,
++        UINT_32 *pPitch, UINT_32 *pHeight) const;
++
++    virtual VOID HwlCheckLastMacroTiledLvl(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
++
++    virtual BOOL_32 HwlTileInfoEqual(
++        const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
++
++    virtual AddrTileMode HwlDegradeThickTileMode(
++        AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
++
++    virtual BOOL_32 HwlOverrideTileMode(
++        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
++        AddrTileMode* pTileMode,
++        AddrTileType* pTileType) const;
++
++    virtual BOOL_32 HwlSanityCheckMacroTiled(
++        ADDR_TILEINFO* pTileInfo) const
++    {
++        return TRUE;
++    }
++
++    virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const;
++
++    virtual UINT_64 HwlGetSizeAdjustmentLinear(
++        AddrTileMode tileMode,
++        UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
++        UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const;
++
++    virtual VOID HwlComputeSurfaceCoord2DFromBankPipe(
++        AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice,
++        UINT_32 bank, UINT_32 pipe,
++        UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
++        BOOL_32 ignoreSE,
++        ADDR_TILEINFO* pTileInfo) const;
++
++    virtual UINT_32 HwlPreAdjustBank(
++        UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const;
++
++    virtual INT_32 HwlPostCheckTileIndex(
++        const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
++        INT curIndex = TileIndexInvalid) const;
++
++    virtual VOID   HwlFmaskPreThunkSurfInfo(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
++        const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
++        ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
++        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
++
++    virtual VOID   HwlFmaskPostThunkSurfInfo(
++        const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
++        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
++
++    virtual UINT_32 HwlComputeFmaskBits(
++        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
++        UINT_32* pNumSamples) const;
++
++    virtual BOOL_32 HwlReduceBankWidthHeight(
++        UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
++        UINT_32 bankHeightAlign, UINT_32 pipes,
++        ADDR_TILEINFO* pTileInfo) const
++    {
++        return TRUE;
++    }
++
++    // Protected non-virtual functions
++    VOID ComputeTileCoordFromPipeAndElemIdx(
++        UINT_32 elemIdx, UINT_32 pipe, AddrPipeCfg pipeCfg, UINT_32 pitchInMacroTile,
++        UINT_32 x, UINT_32 y, UINT_32* pX, UINT_32* pY) const;
++
++    UINT_32 TileCoordToMaskElementIndex(
++        UINT_32 tx, UINT_32 ty, AddrPipeCfg  pipeConfig,
++        UINT_32 *macroShift, UINT_32 *elemIdxBits) const;
++
++    BOOL_32 DecodeGbRegs(
++        const ADDR_REGISTER_VALUE* pRegValue);
++
++    const ADDR_TILECONFIG* GetTileSetting(
++        UINT_32 index) const;
++
++    static const UINT_32    TileTableSize = 32;
++    ADDR_TILECONFIG         m_tileTable[TileTableSize];
++    UINT_32                 m_noOfEntries;
++
++private:
++
++    UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
++
++    VOID ReadGbTileMode(
++        UINT_32 regValue, ADDR_TILECONFIG* pCfg) const;
++    BOOL_32 InitTileSettingTable(
++        const UINT_32 *pSetting, UINT_32 noOfEntries);
++
++    SIChipSettings          m_settings;
++};
++
++#endif
++
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_id.h b/src/gallium/winsys/radeon/amdgpu/amdgpu_id.h
+new file mode 100644
+index 0000000..08a1591
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_id.h
+@@ -0,0 +1,157 @@
++/*
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/**
++ * This file is included by addrlib. It adds GPU family definitions and
++ * macros compatible with addrlib.
++ */
++
++#ifndef AMDGPU_ID_H
++#define AMDGPU_ID_H
++
++#include "pipe/p_config.h"
++
++#if defined(PIPE_ARCH_LITTLE_ENDIAN)
++#define LITTLEENDIAN_CPU
++#elif defined(PIPE_ARCH_BIG_ENDIAN)
++#define BIGENDIAN_CPU
++#endif
++
++enum {
++	FAMILY_UNKNOWN,
++	FAMILY_SI,
++	FAMILY_CI,
++	FAMILY_KV,
++	FAMILY_VI,
++	FAMILY_CZ,
++	FAMILY_PI,
++	FAMILY_LAST,
++};
++
++/* SI specific rev IDs */
++enum {
++	SI_TAHITI_P_A11      = 1,
++	SI_TAHITI_P_A0       = SI_TAHITI_P_A11,      /*A0 is alias of A11*/
++	SI_TAHITI_P_A21      = 5,
++	SI_TAHITI_P_B0       = SI_TAHITI_P_A21,      /*B0 is alias of A21*/
++	SI_TAHITI_P_A22      = 6,
++	SI_TAHITI_P_B1       = SI_TAHITI_P_A22,      /*B1 is alias of A22*/
++
++	SI_PITCAIRN_PM_A11   = 20,
++	SI_PITCAIRN_PM_A0    = SI_PITCAIRN_PM_A11,   /*A0 is alias of A11*/
++	SI_PITCAIRN_PM_A12   = 21,
++	SI_PITCAIRN_PM_A1    = SI_PITCAIRN_PM_A12,   /*A1 is alias of A12*/
++
++	SI_CAPEVERDE_M_A11   = 40,
++	SI_CAPEVERDE_M_A0    = SI_CAPEVERDE_M_A11,   /*A0 is alias of A11*/
++	SI_CAPEVERDE_M_A12   = 41,
++	SI_CAPEVERDE_M_A1    = SI_CAPEVERDE_M_A12,   /*A1 is alias of A12*/
++
++	SI_OLAND_M_A0        = 60,
++
++	SI_HAINAN_V_A0       = 70,
++
++	SI_UNKNOWN           = 0xFF
++};
++
++
++#define ASICREV_IS_TAHITI_P(eChipRev)	\
++	(eChipRev < SI_PITCAIRN_PM_A11)
++#define ASICREV_IS_PITCAIRN_PM(eChipRev)	\
++	((eChipRev >= SI_PITCAIRN_PM_A11) && (eChipRev < SI_CAPEVERDE_M_A11))
++#define ASICREV_IS_CAPEVERDE_M(eChipRev)	\
++	((eChipRev >= SI_CAPEVERDE_M_A11) && (eChipRev < SI_OLAND_M_A0))
++#define ASICREV_IS_OLAND_M(eChipRev)	\
++	((eChipRev >= SI_OLAND_M_A0) && (eChipRev < SI_HAINAN_V_A0))
++#define ASICREV_IS_HAINAN_V(eChipRev)	\
++(eChipRev >= SI_HAINAN_V_A0)
++
++/* CI specific revIDs */
++enum {
++	CI_BONAIRE_M_A0 = 20,
++	CI_BONAIRE_M_A1 = 21,
++
++	CI_HAWAII_P_A0  = 40,
++
++	CI_UNKNOWN      = 0xFF
++};
++
++#define ASICREV_IS_BONAIRE_M(eChipRev)	\
++	((eChipRev >= CI_BONAIRE_M_A0) && (eChipRev < CI_HAWAII_P_A0))
++#define ASICREV_IS_HAWAII_P(eChipRev)	\
++	(eChipRev >= CI_HAWAII_P_A0)
++
++/* KV specific rev IDs */
++enum {
++	KV_SPECTRE_A0      = 0x01,       /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
++	KV_SPOOKY_A0       = 0x41,       /* KV2 with Spooky GFX core, including downgraded from Spectre core, 3-4-1-1 (CU-Pix-Primitive-RB) */
++	KB_KALINDI_A0      = 0x81,       /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
++	KB_KALINDI_A1      = 0x82,       /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
++	BV_KALINDI_A2      = 0x85,       /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
++	ML_GODAVARI_A0     = 0xa1,      /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
++	ML_GODAVARI_A1     = 0xa2,      /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
++	KV_UNKNOWN = 0xFF
++};
++
++#define ASICREV_IS_SPECTRE(eChipRev)	\
++	((eChipRev >= KV_SPECTRE_A0) && (eChipRev < KV_SPOOKY_A0))         /* identify all versions of SPRECTRE and supported features set */
++#define ASICREV_IS_SPOOKY(eChipRev)	\
++	((eChipRev >= KV_SPOOKY_A0) && (eChipRev < KB_KALINDI_A0))          /* identify all versions of SPOOKY and supported features set */
++#define ASICREV_IS_KALINDI(eChipRev)	\
++	((eChipRev >= KB_KALINDI_A0) && (eChipRev < KV_UNKNOWN))           /* identify all versions of KALINDI and supported features set */
++
++/* Following macros are subset of ASICREV_IS_KALINDI macro */
++#define ASICREV_IS_KALINDI_BHAVANI(eChipRev)	\
++	((eChipRev >= BV_KALINDI_A2) && (eChipRev < ML_GODAVARI_A0))   /* identify all versions of BHAVANI and supported features set */
++#define ASICREV_IS_KALINDI_GODAVARI(eChipRev)	\
++	((eChipRev >= ML_GODAVARI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of GODAVARI and supported features set */
++
++/* VI specific rev IDs */
++enum {
++	VI_ICELAND_M_A0   = 1,
++
++	VI_TONGA_P_A0     = 20,
++	VI_TONGA_P_A1     = 21,
++
++	VI_UNKNOWN        = 0xFF
++};
++
++
++#define ASICREV_IS_ICELAND_M(eChipRev)	\
++	(eChipRev < VI_TONGA_P_A0)
++#define ASICREV_IS_TONGA_P(eChipRev)	\
++	(eChipRev >= VI_TONGA_P_A0)
++
++/* CZ specific rev IDs */
++enum {
++	CZ_CARRIZO_A0      = 0x01,
++	CZ_UNKNOWN      = 0xFF
++};
++
++#define ASICREV_IS_CARRIZO(eChipRev) \
++	(eChipRev >= CARRIZO_A0)
++
++#endif /* AMDGPU_ID_H */
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_surface.c b/src/gallium/winsys/radeon/amdgpu/amdgpu_surface.c
+new file mode 100644
+index 0000000..aa32413
+--- /dev/null
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_surface.c
+@@ -0,0 +1,436 @@
++/*
++ * Copyright © 2011 Red Hat All Rights Reserved.
++ * Copyright © 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
++ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ */
++
++/* Contact:
++ *     Marek Olšák <maraeo@gmail.com>
++ */
++
++#include "amdgpu_winsys.h"
++
++#ifndef NO_ENTRIES
++#define NO_ENTRIES 32
++#endif
++
++#ifndef NO_MACRO_ENTRIES
++#define NO_MACRO_ENTRIES 16
++#endif
++
++#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
++#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
++#endif
++
++
++static int amdgpu_surface_sanity(const struct radeon_surf *surf)
++{
++   unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
++
++   if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
++      return -EINVAL;
++
++   /* all dimension must be at least 1 ! */
++   if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
++       !surf->array_size)
++      return -EINVAL;
++
++   if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
++      return -EINVAL;
++
++   switch (surf->nsamples) {
++   case 1:
++   case 2:
++   case 4:
++   case 8:
++      break;
++   default:
++      return -EINVAL;
++   }
++
++   switch (type) {
++   case RADEON_SURF_TYPE_1D:
++      if (surf->npix_y > 1)
++         return -EINVAL;
++      /* fall through */
++   case RADEON_SURF_TYPE_2D:
++   case RADEON_SURF_TYPE_CUBEMAP:
++      if (surf->npix_z > 1 || surf->array_size > 1)
++         return -EINVAL;
++      break;
++   case RADEON_SURF_TYPE_3D:
++      if (surf->array_size > 1)
++         return -EINVAL;
++      break;
++   case RADEON_SURF_TYPE_1D_ARRAY:
++      if (surf->npix_y > 1)
++         return -EINVAL;
++      /* fall through */
++   case RADEON_SURF_TYPE_2D_ARRAY:
++      if (surf->npix_z > 1)
++         return -EINVAL;
++      break;
++   default:
++      return -EINVAL;
++   }
++   return 0;
++}
++
++static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
++{
++   return malloc(pInput->sizeInBytes);
++}
++
++static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
++{
++   free(pInput->pVirtAddr);
++   return ADDR_OK;
++}
++
++/**
++ * This returns the number of banks for the surface.
++ * Possible values: 2, 4, 8, 16.
++ */
++static uint32_t cik_num_banks(struct amdgpu_winsys *ws,
++                              struct radeon_surf *surf)
++{
++   unsigned index, tileb;
++
++   tileb = 8 * 8 * surf->bpe;
++   tileb = MIN2(surf->tile_split, tileb);
++
++   for (index = 0; tileb > 64; index++) {
++      tileb >>= 1;
++   }
++   assert(index < 16);
++
++   return 2 << ((ws->amdinfo.gb_macro_tile_mode[index] >> 6) & 0x3);
++}
++
++ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
++{
++   ADDR_CREATE_INPUT addrCreateInput = {0};
++   ADDR_CREATE_OUTPUT addrCreateOutput = {0};
++   ADDR_REGISTER_VALUE regValue = {0};
++   ADDR_CREATE_FLAGS createFlags = {{0}};
++   ADDR_E_RETURNCODE addrRet;
++
++   addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
++   addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
++
++   regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
++   regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
++   regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
++
++   regValue.backendDisables = ws->amdinfo.backend_disable[0];
++   regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
++   regValue.noOfEntries = sizeof(ws->amdinfo.gb_tile_mode) /
++                          sizeof(ws->amdinfo.gb_tile_mode[0]);
++   regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
++   regValue.noOfMacroEntries = sizeof(ws->amdinfo.gb_macro_tile_mode) /
++                               sizeof(ws->amdinfo.gb_macro_tile_mode[0]);
++
++   createFlags.value = 0;
++   createFlags.useTileIndex = 1;
++   createFlags.degradeBaseLevel = 1;
++
++   addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
++   addrCreateInput.chipFamily = ws->family;
++   addrCreateInput.chipRevision = ws->rev_id;
++   addrCreateInput.createFlags = createFlags;
++   addrCreateInput.callbacks.allocSysMem = allocSysMem;
++   addrCreateInput.callbacks.freeSysMem = freeSysMem;
++   addrCreateInput.callbacks.debugPrint = 0;
++   addrCreateInput.regValue = regValue;
++
++   addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
++   if (addrRet != ADDR_OK)
++      return NULL;
++
++   return addrCreateOutput.hLib;
++}
++
++static int compute_level(struct amdgpu_winsys *ws,
++                         struct radeon_surf *surf, bool is_stencil,
++                         unsigned level, unsigned type, bool compressed,
++                         ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
++                         ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut)
++{
++   struct radeon_surf_level *surf_level;
++   ADDR_E_RETURNCODE ret;
++
++   AddrSurfInfoIn->mipLevel = level;
++   AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
++   AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
++
++   if (type == RADEON_SURF_TYPE_3D)
++      AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
++   else if (type == RADEON_SURF_TYPE_CUBEMAP)
++      AddrSurfInfoIn->numSlices = 6;
++   else
++      AddrSurfInfoIn->numSlices = surf->array_size;
++
++   if (level > 0) {
++      /* Set the base level pitch. This is needed for calculation
++       * of non-zero levels. */
++      if (is_stencil)
++         AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
++      else
++         AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
++
++      /* Convert blocks to pixels for compressed formats. */
++      if (compressed)
++         AddrSurfInfoIn->basePitch *= surf->blk_w;
++   }
++
++   ret = AddrComputeSurfaceInfo(ws->addrlib,
++                                AddrSurfInfoIn,
++                                AddrSurfInfoOut);
++   if (ret != ADDR_OK) {
++      return ret;
++   }
++
++   surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
++   surf_level->offset = align(surf->bo_size, AddrSurfInfoOut->baseAlign);
++   surf_level->slice_size = AddrSurfInfoOut->sliceSize;
++   surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
++   surf_level->npix_x = u_minify(surf->npix_x, level);
++   surf_level->npix_y = u_minify(surf->npix_y, level);
++   surf_level->npix_z = u_minify(surf->npix_z, level);
++   surf_level->nblk_x = AddrSurfInfoOut->pitch;
++   surf_level->nblk_y = AddrSurfInfoOut->height;
++   if (type == RADEON_SURF_TYPE_3D)
++      surf_level->nblk_z = AddrSurfInfoOut->depth;
++   else
++      surf_level->nblk_z = 1;
++
++   switch (AddrSurfInfoOut->tileMode) {
++   case ADDR_TM_LINEAR_GENERAL:
++      surf_level->mode = RADEON_SURF_MODE_LINEAR;
++      break;
++   case ADDR_TM_LINEAR_ALIGNED:
++      surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
++      break;
++   case ADDR_TM_1D_TILED_THIN1:
++      surf_level->mode = RADEON_SURF_MODE_1D;
++      break;
++   case ADDR_TM_2D_TILED_THIN1:
++      surf_level->mode = RADEON_SURF_MODE_2D;
++      break;
++   default:
++      assert(0);
++   }
++
++   if (is_stencil)
++      surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
++   else
++      surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
++
++   surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
++   return 0;
++}
++
++static int amdgpu_surface_init(struct radeon_winsys *rws,
++                               struct radeon_surf *surf)
++{
++   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
++   unsigned level, mode, type;
++   bool compressed;
++   ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
++   ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
++   ADDR_TILEINFO AddrTileInfoIn = {0};
++   ADDR_TILEINFO AddrTileInfoOut = {0};
++   int r;
++
++   r = amdgpu_surface_sanity(surf);
++   if (r)
++      return r;
++
++   AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
++   AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
++   AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
++
++   type = RADEON_SURF_GET(surf->flags, TYPE);
++   mode = RADEON_SURF_GET(surf->flags, MODE);
++   compressed = surf->blk_w == 4 && surf->blk_h == 4;
++
++   /* MSAA and FMASK require 2D tiling. */
++   if (surf->nsamples > 1 ||
++       (surf->flags & RADEON_SURF_FMASK))
++      mode = RADEON_SURF_MODE_2D;
++
++   /* DB doesn't support linear layouts. */
++   if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
++       mode < RADEON_SURF_MODE_1D)
++      mode = RADEON_SURF_MODE_1D;
++
++   /* Set the requested tiling mode. */
++   switch (mode) {
++   case RADEON_SURF_MODE_LINEAR:
++      AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_GENERAL;
++      break;
++   case RADEON_SURF_MODE_LINEAR_ALIGNED:
++      AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
++      break;
++   case RADEON_SURF_MODE_1D:
++      AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
++      break;
++   case RADEON_SURF_MODE_2D:
++      AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
++      break;
++   default:
++      assert(0);
++   }
++
++   /* The format must be set correctly for the allocation of compressed
++    * textures to work. In other cases, setting the bpp is sufficient. */
++   if (compressed) {
++      switch (surf->bpe) {
++      case 8:
++         AddrSurfInfoIn.format = ADDR_FMT_BC1;
++         break;
++      case 16:
++         AddrSurfInfoIn.format = ADDR_FMT_BC3;
++         break;
++      default:
++         assert(0);
++      }
++   }
++   else {
++      AddrSurfInfoIn.bpp = surf->bpe * 8;
++   }
++
++   AddrSurfInfoIn.numSamples = surf->nsamples;
++   AddrSurfInfoIn.tileIndex = -1;
++
++   /* Set the micro tile type. */
++   if (surf->flags & RADEON_SURF_SCANOUT)
++      AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
++   else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
++      AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
++   else
++      AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
++
++   AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
++   AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
++   AddrSurfInfoIn.flags.stencil = (surf->flags & RADEON_SURF_SBUFFER) != 0;
++   AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
++   AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
++   AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
++   AddrSurfInfoIn.flags.degrade4Space = 1;
++
++   /* This disables incorrect calculations (hacks) in addrlib. */
++   AddrSurfInfoIn.flags.noStencil = 1;
++
++   /* Set preferred macrotile parameters. This is usually required
++    * for shared resources. This is for 2D tiling only. */
++   if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
++       surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
++      /* If any of these parameters are incorrect, the calculation
++       * will fail. */
++      AddrTileInfoIn.banks = cik_num_banks(ws, surf);
++      AddrTileInfoIn.bankWidth = surf->bankw;
++      AddrTileInfoIn.bankHeight = surf->bankh;
++      AddrTileInfoIn.macroAspectRatio = surf->mtilea;
++      AddrTileInfoIn.tileSplitBytes = surf->tile_split;
++      AddrSurfInfoIn.flags.degrade4Space = 0;
++      AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
++
++      /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
++       * the tile index, because we are expected to know it if
++       * we know the other parameters.
++       *
++       * This is something that can easily be fixed in Addrlib.
++       * For now, just figure it out here.
++       * Note that only 2D_TILE_THIN1 is handled here.
++       */
++      assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
++      assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
++
++      if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
++         AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
++      else
++         AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
++   }
++
++   surf->bo_size = 0;
++
++   /* Calculate texture layout information. */
++   for (level = 0; level <= surf->last_level; level++) {
++      r = compute_level(ws, surf, false, level, type, compressed,
++                        &AddrSurfInfoIn, &AddrSurfInfoOut);
++      if (r)
++         return r;
++
++      if (level == 0) {
++         surf->bo_alignment = AddrSurfInfoOut.baseAlign;
++
++         /* For 2D modes only. */
++         if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
++            surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
++            surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
++            surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
++            surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
++         }
++      }
++   }
++
++   /* Calculate texture layout information for stencil. */
++   if (surf->flags & RADEON_SURF_SBUFFER) {
++      AddrSurfInfoIn.bpp = 8;
++      /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
++      AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
++
++      for (level = 0; level <= surf->last_level; level++) {
++         r = compute_level(ws, surf, true, level, type, compressed,
++                           &AddrSurfInfoIn, &AddrSurfInfoOut);
++         if (r)
++            return r;
++
++         if (level == 0) {
++            surf->stencil_offset = surf->stencil_level[0].offset;
++
++            /* For 2D modes only. */
++            if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
++               surf->stencil_tile_split =
++                     AddrSurfInfoOut.pTileInfo->tileSplitBytes;
++            }
++         }
++      }
++   }
++
++   return 0;
++}
++
++static int amdgpu_surface_best(struct radeon_winsys *rws,
++                               struct radeon_surf *surf)
++{
++   return 0;
++}
++
++void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
++{
++   ws->base.surface_init = amdgpu_surface_init;
++   ws->base.surface_best = amdgpu_surface_best;
++}
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c
+index 0f3367a..d3992e9 100644
+--- a/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c
+@@ -39,6 +39,7 @@
+ #include <xf86drm.h>
+ #include <stdio.h>
+ #include <sys/stat.h>
++#include "amdgpu_id.h"
+ 
+ #define CIK_TILE_MODE_COLOR_2D			14
+ 
+@@ -198,6 +199,51 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
+       goto fail;
+    }
+ 
++   /* family and rev_id are for addrlib */
++   switch (ws->info.family) {
++   case CHIP_BONAIRE:
++      ws->family = FAMILY_CI;
++      ws->rev_id = CI_BONAIRE_M_A0;
++      break;
++   case CHIP_KAVERI:
++      ws->family = FAMILY_KV;
++      ws->rev_id = KV_SPECTRE_A0;
++      break;
++   case CHIP_KABINI:
++      ws->family = FAMILY_KV;
++      ws->rev_id = KB_KALINDI_A0;
++      break;
++   case CHIP_HAWAII:
++      ws->family = FAMILY_CI;
++      ws->rev_id = CI_HAWAII_P_A0;
++      break;
++   case CHIP_MULLINS:
++      ws->family = FAMILY_KV;
++      ws->rev_id = ML_GODAVARI_A0;
++      break;
++   case CHIP_TONGA:
++      ws->family = FAMILY_VI;
++      ws->rev_id = VI_TONGA_P_A0;
++      break;
++   case CHIP_ICELAND:
++      ws->family = FAMILY_VI;
++      ws->rev_id = VI_ICELAND_M_A0;
++      break;
++   case CHIP_CARRIZO:
++      ws->family = FAMILY_CZ;
++      ws->rev_id = CZ_CARRIZO_A0;
++      break;
++   default:
++      fprintf(stderr, "amdgpu: Unknown family.\n");
++      goto fail;
++   }
++
++   ws->addrlib = amdgpu_addr_create(ws);
++   if (!ws->addrlib) {
++      fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
++      goto fail;
++   }
++
+    /* Set hardware information. */
+    ws->info.gart_size = gtt.heap_size;
+    ws->info.vram_size = vram.heap_size;
+@@ -232,6 +278,8 @@ fail:
+    if (ws->ctx) {
+       amdgpu_cs_ctx_free(ws->dev, ws->ctx);
+    }
++   if (ws->addrlib)
++      AddrDestroy(ws->addrlib);
+    amdgpu_device_deinitialize(ws->dev);
+    ws->dev = NULL;
+    return FALSE;
+@@ -251,6 +299,7 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
+ 
+    ws->cman->destroy(ws->cman);
+    ws->kman->destroy(ws->kman);
++   AddrDestroy(ws->addrlib);
+ 
+    amdgpu_cs_ctx_free(ws->dev, ws->ctx);
+    amdgpu_device_deinitialize(ws->dev);
+@@ -451,6 +500,7 @@ struct radeon_winsys *
+ 
+    amdgpu_bomgr_init_functions(ws);
+    amdgpu_cs_init_functions(ws);
++   amdgpu_surface_init_functions(ws);
+ 
+    pipe_mutex_init(ws->cs_stack_lock);
+ 
+diff --git a/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h
+index fc27f1c..8755108 100644
+--- a/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h
++++ b/src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h
+@@ -31,6 +31,7 @@
+ #define AMDGPU_DRM_WINSYS_H
+ 
+ #include "../radeon_winsys.h"
++#include "addrlib/addrinterface.h"
+ #include "os/os_thread.h"
+ #include <amdgpu.h>
+ 
+@@ -67,6 +68,9 @@ struct amdgpu_winsys {
+    struct amdgpu_cs *cs_stack[RING_LAST];
+ 
+    struct amdgpu_gpu_info amdinfo;
++   ADDR_HANDLE addrlib;
++   uint32_t rev_id;
++   unsigned family;
+ };
+ 
+ static INLINE struct amdgpu_winsys *
+@@ -76,5 +80,7 @@ amdgpu_winsys(struct radeon_winsys *base)
+ }
+ 
+ void amdgpu_ws_queue_cs(struct amdgpu_winsys *ws, struct amdgpu_cs *cs);
++void amdgpu_surface_init_functions(struct amdgpu_winsys *ws);
++ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws);
+ 
+ #endif
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0010-radeonsi-fix-DRM-version-checks-for-amdgpu-DRM-3.0.0.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0010-radeonsi-fix-DRM-version-checks-for-amdgpu-DRM-3.0.0.patch
new file mode 100644
index 00000000..16cd660b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0010-radeonsi-fix-DRM-version-checks-for-amdgpu-DRM-3.0.0.patch
@@ -0,0 +1,137 @@
+From 05c1faed5211f58309d24729667f1af5ad72f954 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:35:27 +0200
+Subject: [PATCH 10/29] radeonsi: fix DRM version checks for amdgpu DRM 3.0.0
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/r600_buffer_common.c | 6 ++++--
+ src/gallium/drivers/radeon/r600_pipe_common.c   | 4 +++-
+ src/gallium/drivers/radeon/r600_texture.c       | 8 +++++---
+ src/gallium/drivers/radeonsi/si_pipe.c          | 4 +++-
+ src/gallium/drivers/radeonsi/si_state.c         | 8 ++++----
+ 5 files changed, 19 insertions(+), 11 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
+index fc5f6c2..ac395fa 100644
+--- a/src/gallium/drivers/radeon/r600_buffer_common.c
++++ b/src/gallium/drivers/radeon/r600_buffer_common.c
+@@ -121,7 +121,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
+ 		/* Older kernels didn't always flush the HDP cache before
+ 		 * CS execution
+ 		 */
+-		if (rscreen->info.drm_minor < 40) {
++		if (rscreen->info.drm_major == 2 &&
++		    rscreen->info.drm_minor < 40) {
+ 			res->domains = RADEON_DOMAIN_GTT;
+ 			flags |= RADEON_FLAG_GTT_WC;
+ 			break;
+@@ -147,7 +148,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
+ 		 * Write-combined CPU mappings are fine, the kernel ensures all CPU
+ 		 * writes finish before the GPU executes a command stream.
+ 		 */
+-		if (rscreen->info.drm_minor < 40)
++		if (rscreen->info.drm_major == 2 &&
++		    rscreen->info.drm_minor < 40)
+ 			res->domains = RADEON_DOMAIN_GTT;
+ 		else if (res->domains & RADEON_DOMAIN_VRAM)
+ 			flags |= RADEON_FLAG_CPU_ACCESS;
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
+index c6d7918..3b26dea 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.c
++++ b/src/gallium/drivers/radeon/r600_pipe_common.c
+@@ -864,7 +864,9 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
+ 	util_format_s3tc_init();
+ 	pipe_mutex_init(rscreen->aux_context_lock);
+ 
+-	if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
++	if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
++	     rscreen->info.drm_major == 3) &&
++	    (rscreen->debug_flags & DBG_TRACE_CS)) {
+ 		rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
+ 										PIPE_BIND_CUSTOM,
+ 										PIPE_USAGE_STAGING,
+diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
+index dc510c9..1b64507 100644
+--- a/src/gallium/drivers/radeon/r600_texture.c
++++ b/src/gallium/drivers/radeon/r600_texture.c
+@@ -489,7 +489,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+ 	unsigned num_pipes = rscreen->tiling_info.num_channels;
+ 
+ 	if (rscreen->chip_class <= EVERGREEN &&
+-	    rscreen->info.drm_minor < 26)
++	    rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
+ 		return 0;
+ 
+ 	/* HW bug on R6xx. */
+@@ -501,7 +501,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+ 	/* HTILE is broken with 1D tiling on old kernels and CIK. */
+ 	if (rscreen->chip_class >= CIK &&
+ 	    rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
+-	    rscreen->info.drm_minor < 38)
++	    rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
+ 		return 0;
+ 
+ 	switch (num_pipes) {
+@@ -1262,7 +1262,9 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
+ 
+ 		/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
+ 		if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
+-		    rctx->chip_class >= CIK && rctx->screen->info.drm_minor < 38) {
++		    rctx->chip_class >= CIK &&
++		    rctx->screen->info.drm_major == 2 &&
++		    rctx->screen->info.drm_minor < 38) {
+ 			continue;
+ 		}
+ 
+diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
+index e68c30e..91b4d6f 100644
+--- a/src/gallium/drivers/radeonsi/si_pipe.c
++++ b/src/gallium/drivers/radeonsi/si_pipe.c
+@@ -259,7 +259,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
+ 	case PIPE_CAP_TEXTURE_MULTISAMPLE:
+ 		/* 2D tiling on CIK is supported since DRM 2.35.0 */
+ 		return sscreen->b.chip_class < CIK ||
+-		       sscreen->b.info.drm_minor >= 35;
++		       (sscreen->b.info.drm_major == 2 &&
++			sscreen->b.info.drm_minor >= 35) ||
++		       sscreen->b.info.drm_major == 3;
+ 
+         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+                 return R600_MAP_BUFFER_ALIGNMENT;
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index 7f0fdd5..eae5e6f 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -1146,7 +1146,9 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
+ 				       int first_non_void)
+ {
+ 	struct si_screen *sscreen = (struct si_screen*)screen;
+-	bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
++	bool enable_s3tc = (sscreen->b.info.drm_major == 2 &&
++			    sscreen->b.info.drm_minor >= 31) ||
++			   sscreen->b.info.drm_major == 3;
+ 	boolean uniform = TRUE;
+ 	int i;
+ 
+@@ -1595,7 +1597,6 @@ boolean si_is_format_supported(struct pipe_screen *screen,
+                                unsigned sample_count,
+                                unsigned usage)
+ {
+-	struct si_screen *sscreen = (struct si_screen *)screen;
+ 	unsigned retval = 0;
+ 
+ 	if (target >= PIPE_MAX_TEXTURE_TYPES) {
+@@ -1607,8 +1608,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
+ 		return FALSE;
+ 
+ 	if (sample_count > 1) {
+-		/* 2D tiling on CIK is supported since DRM 2.35.0 */
+-		if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
++		if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
+ 			return FALSE;
+ 
+ 		switch (sample_count) {
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0011-radeonsi-add-VI-register-definitions.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0011-radeonsi-add-VI-register-definitions.patch
new file mode 100644
index 00000000..6154ba3b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0011-radeonsi-add-VI-register-definitions.patch
@@ -0,0 +1,1753 @@
+From c87e3033117dbead0f02c12117a72b6726134a5c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:12:24 +0200
+Subject: [PATCH 11/29] radeonsi: add VI register definitions
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/r600d_common.h |    2 +-
+ src/gallium/drivers/radeonsi/si_state.c   |   12 +-
+ src/gallium/drivers/radeonsi/sid.h        | 1089 +++++++++++++++++++++++++++--
+ 3 files changed, 1043 insertions(+), 60 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/r600d_common.h b/src/gallium/drivers/radeon/r600d_common.h
+index 74c8d87..bef5586 100644
+--- a/src/gallium/drivers/radeon/r600d_common.h
++++ b/src/gallium/drivers/radeon/r600d_common.h
+@@ -177,7 +177,7 @@
+ #define   S_028804_INTERPOLATE_SRC_Z(x)			(((x) & 0x1) << 19)
+ #define   S_028804_STATIC_ANCHOR_ASSOCIATIONS(x)	(((x) & 0x1) << 20)
+ #define   S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)	(((x) & 0x1) << 21)
+-#define   S_028804_OVERRASTERIZATION_AMOUNT(x)		(((x) & 0x7) << 24)
++#define   S_028804_OVERRASTERIZATION_AMOUNT(x)		(((x) & 0x07) << 24)
+ #define   S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x)	(((x) & 0x1) << 27)
+ #define CM_R_028BDC_PA_SC_LINE_CNTL                  0x28bdc
+ #define   S_028BDC_EXPAND_LINE_WIDTH(x)                (((x) & 0x1) << 9)
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index eae5e6f..6a0b093 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -523,12 +523,12 @@ static void si_set_viewport_states(struct pipe_context *ctx,
+ 		return;
+ 
+ 	viewport->viewport = *state;
+-	si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
+-	si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
+-	si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
+-	si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
+-	si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
+-	si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
++	si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE, fui(state->scale[0]));
++	si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET, fui(state->translate[0]));
++	si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE, fui(state->scale[1]));
++	si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET, fui(state->translate[1]));
++	si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE, fui(state->scale[2]));
++	si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET, fui(state->translate[2]));
+ 
+ 	si_pm4_set_state(sctx, viewport, viewport);
+ }
+diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h
+index afe011b..d7348a7 100644
+--- a/src/gallium/drivers/radeonsi/sid.h
++++ b/src/gallium/drivers/radeonsi/sid.h
+@@ -206,6 +206,80 @@
+  * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
+  */
+ 
++
++#define R_008010_GRBM_STATUS                                            0x008010
++#define   S_008010_ME0PIPE0_CMDFIFO_AVAIL(x)                          (((x) & 0x0F) << 0)
++#define   G_008010_ME0PIPE0_CMDFIFO_AVAIL(x)                          (((x) >> 0) & 0x0F)
++#define   C_008010_ME0PIPE0_CMDFIFO_AVAIL                             0xFFFFFFF0
++#define   S_008010_SRBM_RQ_PENDING(x)                                 (((x) & 0x1) << 5)
++#define   G_008010_SRBM_RQ_PENDING(x)                                 (((x) >> 5) & 0x1)
++#define   C_008010_SRBM_RQ_PENDING                                    0xFFFFFFDF
++#define   S_008010_ME0PIPE0_CF_RQ_PENDING(x)                          (((x) & 0x1) << 7)
++#define   G_008010_ME0PIPE0_CF_RQ_PENDING(x)                          (((x) >> 7) & 0x1)
++#define   C_008010_ME0PIPE0_CF_RQ_PENDING                             0xFFFFFF7F
++#define   S_008010_ME0PIPE0_PF_RQ_PENDING(x)                          (((x) & 0x1) << 8)
++#define   G_008010_ME0PIPE0_PF_RQ_PENDING(x)                          (((x) >> 8) & 0x1)
++#define   C_008010_ME0PIPE0_PF_RQ_PENDING                             0xFFFFFEFF
++#define   S_008010_GDS_DMA_RQ_PENDING(x)                              (((x) & 0x1) << 9)
++#define   G_008010_GDS_DMA_RQ_PENDING(x)                              (((x) >> 9) & 0x1)
++#define   C_008010_GDS_DMA_RQ_PENDING                                 0xFFFFFDFF
++#define   S_008010_DB_CLEAN(x)                                        (((x) & 0x1) << 12)
++#define   G_008010_DB_CLEAN(x)                                        (((x) >> 12) & 0x1)
++#define   C_008010_DB_CLEAN                                           0xFFFFEFFF
++#define   S_008010_CB_CLEAN(x)                                        (((x) & 0x1) << 13)
++#define   G_008010_CB_CLEAN(x)                                        (((x) >> 13) & 0x1)
++#define   C_008010_CB_CLEAN                                           0xFFFFDFFF
++#define   S_008010_TA_BUSY(x)                                         (((x) & 0x1) << 14)
++#define   G_008010_TA_BUSY(x)                                         (((x) >> 14) & 0x1)
++#define   C_008010_TA_BUSY                                            0xFFFFBFFF
++#define   S_008010_GDS_BUSY(x)                                        (((x) & 0x1) << 15)
++#define   G_008010_GDS_BUSY(x)                                        (((x) >> 15) & 0x1)
++#define   C_008010_GDS_BUSY                                           0xFFFF7FFF
++#define   S_008010_WD_BUSY_NO_DMA(x)                                  (((x) & 0x1) << 16)
++#define   G_008010_WD_BUSY_NO_DMA(x)                                  (((x) >> 16) & 0x1)
++#define   C_008010_WD_BUSY_NO_DMA                                     0xFFFEFFFF
++#define   S_008010_VGT_BUSY(x)                                        (((x) & 0x1) << 17)
++#define   G_008010_VGT_BUSY(x)                                        (((x) >> 17) & 0x1)
++#define   C_008010_VGT_BUSY                                           0xFFFDFFFF
++#define   S_008010_IA_BUSY_NO_DMA(x)                                  (((x) & 0x1) << 18)
++#define   G_008010_IA_BUSY_NO_DMA(x)                                  (((x) >> 18) & 0x1)
++#define   C_008010_IA_BUSY_NO_DMA                                     0xFFFBFFFF
++#define   S_008010_IA_BUSY(x)                                         (((x) & 0x1) << 19)
++#define   G_008010_IA_BUSY(x)                                         (((x) >> 19) & 0x1)
++#define   C_008010_IA_BUSY                                            0xFFF7FFFF
++#define   S_008010_SX_BUSY(x)                                         (((x) & 0x1) << 20)
++#define   G_008010_SX_BUSY(x)                                         (((x) >> 20) & 0x1)
++#define   C_008010_SX_BUSY                                            0xFFEFFFFF
++#define   S_008010_WD_BUSY(x)                                         (((x) & 0x1) << 21)
++#define   G_008010_WD_BUSY(x)                                         (((x) >> 21) & 0x1)
++#define   C_008010_WD_BUSY                                            0xFFDFFFFF
++#define   S_008010_SPI_BUSY(x)                                        (((x) & 0x1) << 22)
++#define   G_008010_SPI_BUSY(x)                                        (((x) >> 22) & 0x1)
++#define   C_008010_SPI_BUSY                                           0xFFBFFFFF
++#define   S_008010_BCI_BUSY(x)                                        (((x) & 0x1) << 23)
++#define   G_008010_BCI_BUSY(x)                                        (((x) >> 23) & 0x1)
++#define   C_008010_BCI_BUSY                                           0xFF7FFFFF
++#define   S_008010_SC_BUSY(x)                                         (((x) & 0x1) << 24)
++#define   G_008010_SC_BUSY(x)                                         (((x) >> 24) & 0x1)
++#define   C_008010_SC_BUSY                                            0xFEFFFFFF
++#define   S_008010_PA_BUSY(x)                                         (((x) & 0x1) << 25)
++#define   G_008010_PA_BUSY(x)                                         (((x) >> 25) & 0x1)
++#define   C_008010_PA_BUSY                                            0xFDFFFFFF
++#define   S_008010_DB_BUSY(x)                                         (((x) & 0x1) << 26)
++#define   G_008010_DB_BUSY(x)                                         (((x) >> 26) & 0x1)
++#define   C_008010_DB_BUSY                                            0xFBFFFFFF
++#define   S_008010_CP_COHERENCY_BUSY(x)                               (((x) & 0x1) << 28)
++#define   G_008010_CP_COHERENCY_BUSY(x)                               (((x) >> 28) & 0x1)
++#define   C_008010_CP_COHERENCY_BUSY                                  0xEFFFFFFF
++#define   S_008010_CP_BUSY(x)                                         (((x) & 0x1) << 29)
++#define   G_008010_CP_BUSY(x)                                         (((x) >> 29) & 0x1)
++#define   C_008010_CP_BUSY                                            0xDFFFFFFF
++#define   S_008010_CB_BUSY(x)                                         (((x) & 0x1) << 30)
++#define   G_008010_CB_BUSY(x)                                         (((x) >> 30) & 0x1)
++#define   C_008010_CB_BUSY                                            0xBFFFFFFF
++#define   S_008010_GUI_ACTIVE(x)                                      (((x) & 0x1) << 31)
++#define   G_008010_GUI_ACTIVE(x)                                      (((x) >> 31) & 0x1)
++#define   C_008010_GUI_ACTIVE                                         0x7FFFFFFF
+ #define GRBM_GFX_INDEX                                                  0x802C
+ #define         INSTANCE_INDEX(x)                                     ((x) << 0)
+ #define         SH_INDEX(x)                                           ((x) << 8)
+@@ -278,10 +352,18 @@
+ #define R_0085F8_CP_COHER_BASE                                          0x0085F8
+ 
+ /* CIK */
++#define R_0300FC_CP_STRMOUT_CNTL                                        0x0300FC
++#define   S_0300FC_OFFSET_UPDATE_DONE(x)                              (((x) & 0x1) << 0)
++#define   G_0300FC_OFFSET_UPDATE_DONE(x)                              (((x) >> 0) & 0x1)
++#define   C_0300FC_OFFSET_UPDATE_DONE                                 0xFFFFFFFE
+ #define R_0301E4_CP_COHER_BASE_HI                                       0x0301E4
+ #define   S_0301E4_COHER_BASE_HI_256B(x)                              (((x) & 0xFF) << 0)
+ #define   G_0301E4_COHER_BASE_HI_256B(x)                              (((x) >> 0) & 0xFF)
+ #define   C_0301E4_COHER_BASE_HI_256B                                 0xFFFFFF00
++#define R_0301EC_CP_COHER_START_DELAY                                   0x0301EC
++#define   S_0301EC_START_DELAY_COUNT(x)                               (((x) & 0x3F) << 0)
++#define   G_0301EC_START_DELAY_COUNT(x)                               (((x) >> 0) & 0x3F)
++#define   C_0301EC_START_DELAY_COUNT                                  0xFFFFFFC0
+ #define R_0301F0_CP_COHER_CNTL                                          0x0301F0
+ #define   S_0301F0_DEST_BASE_0_ENA(x)                                 (((x) & 0x1) << 0)
+ #define   G_0301F0_DEST_BASE_0_ENA(x)                                 (((x) >> 0) & 0x1)
+@@ -289,6 +371,14 @@
+ #define   S_0301F0_DEST_BASE_1_ENA(x)                                 (((x) & 0x1) << 1)
+ #define   G_0301F0_DEST_BASE_1_ENA(x)                                 (((x) >> 1) & 0x1)
+ #define   C_0301F0_DEST_BASE_1_ENA                                    0xFFFFFFFD
++/* VI */
++#define   S_0301F0_TC_SD_ACTION_ENA(x)                                (((x) & 0x1) << 2)
++#define   G_0301F0_TC_SD_ACTION_ENA(x)                                (((x) >> 2) & 0x1)
++#define   C_0301F0_TC_SD_ACTION_ENA                                   0xFFFFFFFB
++#define   S_0301F0_TC_NC_ACTION_ENA(x)                                (((x) & 0x1) << 3)
++#define   G_0301F0_TC_NC_ACTION_ENA(x)                                (((x) >> 3) & 0x1)
++#define   C_0301F0_TC_NC_ACTION_ENA                                   0xFFFFFFF7
++/*    */
+ #define   S_0301F0_CB0_DEST_BASE_ENA(x)                               (((x) & 0x1) << 6)
+ #define   G_0301F0_CB0_DEST_BASE_ENA(x)                               (((x) >> 6) & 0x1)
+ #define   C_0301F0_CB0_DEST_BASE_ENA                                  0xFFFFFFBF
+@@ -319,7 +409,7 @@
+ #define   S_0301F0_TCL1_VOL_ACTION_ENA(x)                             (((x) & 0x1) << 15)
+ #define   G_0301F0_TCL1_VOL_ACTION_ENA(x)                             (((x) >> 15) & 0x1)
+ #define   C_0301F0_TCL1_VOL_ACTION_ENA                                0xFFFF7FFF
+-#define   S_0301F0_TC_VOL_ACTION_ENA(x)                               (((x) & 0x1) << 16)
++#define   S_0301F0_TC_VOL_ACTION_ENA(x)                               (((x) & 0x1) << 16) /* not on VI */
+ #define   G_0301F0_TC_VOL_ACTION_ENA(x)                               (((x) >> 16) & 0x1)
+ #define   C_0301F0_TC_VOL_ACTION_ENA                                  0xFFFEFFFF
+ #define   S_0301F0_TC_WB_ACTION_ENA(x)                                (((x) & 0x1) << 18)
+@@ -352,8 +442,29 @@
+ #define   S_0301F0_SH_ICACHE_ACTION_ENA(x)                            (((x) & 0x1) << 29)
+ #define   G_0301F0_SH_ICACHE_ACTION_ENA(x)                            (((x) >> 29) & 0x1)
+ #define   C_0301F0_SH_ICACHE_ACTION_ENA                               0xDFFFFFFF
++/* VI */
++#define   S_0301F0_SH_KCACHE_WB_ACTION_ENA(x)                         (((x) & 0x1) << 30)
++#define   G_0301F0_SH_KCACHE_WB_ACTION_ENA(x)                         (((x) >> 30) & 0x1)
++#define   C_0301F0_SH_KCACHE_WB_ACTION_ENA                            0xBFFFFFFF
++#define   S_0301F0_SH_SD_ACTION_ENA(x)                                (((x) & 0x1) << 31)
++#define   G_0301F0_SH_SD_ACTION_ENA(x)                                (((x) >> 31) & 0x1)
++#define   C_0301F0_SH_SD_ACTION_ENA                                   0x7FFFFFFF
++/*    */
+ #define R_0301F4_CP_COHER_SIZE                                          0x0301F4
+ #define R_0301F8_CP_COHER_BASE                                          0x0301F8
++#define R_0301FC_CP_COHER_STATUS                                        0x0301FC
++#define   S_0301FC_MATCHING_GFX_CNTX(x)                               (((x) & 0xFF) << 0)
++#define   G_0301FC_MATCHING_GFX_CNTX(x)                               (((x) >> 0) & 0xFF)
++#define   C_0301FC_MATCHING_GFX_CNTX                                  0xFFFFFF00
++#define   S_0301FC_MEID(x)                                            (((x) & 0x03) << 24)
++#define   G_0301FC_MEID(x)                                            (((x) >> 24) & 0x03)
++#define   C_0301FC_MEID                                               0xFCFFFFFF
++#define   S_0301FC_PHASE1_STATUS(x)                                   (((x) & 0x1) << 30)
++#define   G_0301FC_PHASE1_STATUS(x)                                   (((x) >> 30) & 0x1)
++#define   C_0301FC_PHASE1_STATUS                                      0xBFFFFFFF
++#define   S_0301FC_STATUS(x)                                          (((x) & 0x1) << 31)
++#define   G_0301FC_STATUS(x)                                          (((x) >> 31) & 0x1)
++#define   C_0301FC_STATUS                                             0x7FFFFFFF
+ #define R_030230_CP_COHER_SIZE_HI                                       0x030230
+ #define   S_030230_COHER_SIZE_HI_256B(x)                              (((x) & 0xFF) << 0)
+ #define   G_030230_COHER_SIZE_HI_256B(x)                              (((x) >> 0) & 0xFF)
+@@ -375,10 +486,6 @@
+ #define   C_0088C4_ES_LIMIT                                           0xFFE0FFFF
+ #define R_0088C8_VGT_ESGS_RING_SIZE                                     0x0088C8
+ #define R_0088CC_VGT_GSVS_RING_SIZE                                     0x0088CC
+-/* CIK */
+-#define R_030900_VGT_ESGS_RING_SIZE                                     0x030900
+-#define R_030904_VGT_GSVS_RING_SIZE                                     0x030904
+-/*     */
+ #define R_0088D4_VGT_GS_VERTEX_REUSE                                    0x0088D4
+ #define   S_0088D4_VERT_REUSE(x)                                      (((x) & 0x1F) << 0)
+ #define   G_0088D4_VERT_REUSE(x)                                      (((x) >> 0) & 0x1F)
+@@ -462,6 +569,27 @@
+ #define   G_008B10_CURRENT_COUNT(x)                                   (((x) >> 8) & 0xFF)
+ #define   C_008B10_CURRENT_COUNT                                      0xFFFF00FF
+ /* CIK */
++#define R_030800_GRBM_GFX_INDEX                                         0x030800
++#define   S_030800_INSTANCE_INDEX(x)                                  (((x) & 0xFF) << 0)
++#define   G_030800_INSTANCE_INDEX(x)                                  (((x) >> 0) & 0xFF)
++#define   C_030800_INSTANCE_INDEX                                     0xFFFFFF00
++#define   S_030800_SH_INDEX(x)                                        (((x) & 0xFF) << 8)
++#define   G_030800_SH_INDEX(x)                                        (((x) >> 8) & 0xFF)
++#define   C_030800_SH_INDEX                                           0xFFFF00FF
++#define   S_030800_SE_INDEX(x)                                        (((x) & 0xFF) << 16)
++#define   G_030800_SE_INDEX(x)                                        (((x) >> 16) & 0xFF)
++#define   C_030800_SE_INDEX                                           0xFF00FFFF
++#define   S_030800_SH_BROADCAST_WRITES(x)                             (((x) & 0x1) << 29)
++#define   G_030800_SH_BROADCAST_WRITES(x)                             (((x) >> 29) & 0x1)
++#define   C_030800_SH_BROADCAST_WRITES                                0xDFFFFFFF
++#define   S_030800_INSTANCE_BROADCAST_WRITES(x)                       (((x) & 0x1) << 30)
++#define   G_030800_INSTANCE_BROADCAST_WRITES(x)                       (((x) >> 30) & 0x1)
++#define   C_030800_INSTANCE_BROADCAST_WRITES                          0xBFFFFFFF
++#define   S_030800_SE_BROADCAST_WRITES(x)                             (((x) & 0x1) << 31)
++#define   G_030800_SE_BROADCAST_WRITES(x)                             (((x) >> 31) & 0x1)
++#define   C_030800_SE_BROADCAST_WRITES                                0x7FFFFFFF
++#define R_030900_VGT_ESGS_RING_SIZE                                     0x030900
++#define R_030904_VGT_GSVS_RING_SIZE                                     0x030904
+ #define R_030908_VGT_PRIMITIVE_TYPE                                     0x030908
+ #define   S_030908_PRIM_TYPE(x)                                       (((x) & 0x3F) << 0)
+ #define   G_030908_PRIM_TYPE(x)                                       (((x) >> 0) & 0x3F)
+@@ -530,6 +658,34 @@
+ #define   S_030A04_CURRENT_COUNT(x)                                   (((x) & 0xFF) << 8)
+ #define   G_030A04_CURRENT_COUNT(x)                                   (((x) >> 8) & 0xFF)
+ #define   C_030A04_CURRENT_COUNT                                      0xFFFF00FF
++#define R_030A10_PA_SC_SCREEN_EXTENT_MIN_0                              0x030A10
++#define   S_030A10_X(x)                                               (((x) & 0xFFFF) << 0)
++#define   G_030A10_X(x)                                               (((x) >> 0) & 0xFFFF)
++#define   C_030A10_X                                                  0xFFFF0000
++#define   S_030A10_Y(x)                                               (((x) & 0xFFFF) << 16)
++#define   G_030A10_Y(x)                                               (((x) >> 16) & 0xFFFF)
++#define   C_030A10_Y                                                  0x0000FFFF
++#define R_030A14_PA_SC_SCREEN_EXTENT_MAX_0                              0x030A14
++#define   S_030A14_X(x)                                               (((x) & 0xFFFF) << 0)
++#define   G_030A14_X(x)                                               (((x) >> 0) & 0xFFFF)
++#define   C_030A14_X                                                  0xFFFF0000
++#define   S_030A14_Y(x)                                               (((x) & 0xFFFF) << 16)
++#define   G_030A14_Y(x)                                               (((x) >> 16) & 0xFFFF)
++#define   C_030A14_Y                                                  0x0000FFFF
++#define R_030A18_PA_SC_SCREEN_EXTENT_MIN_1                              0x030A18
++#define   S_030A18_X(x)                                               (((x) & 0xFFFF) << 0)
++#define   G_030A18_X(x)                                               (((x) >> 0) & 0xFFFF)
++#define   C_030A18_X                                                  0xFFFF0000
++#define   S_030A18_Y(x)                                               (((x) & 0xFFFF) << 16)
++#define   G_030A18_Y(x)                                               (((x) >> 16) & 0xFFFF)
++#define   C_030A18_Y                                                  0x0000FFFF
++#define R_030A2C_PA_SC_SCREEN_EXTENT_MAX_1                              0x030A2C
++#define   S_030A2C_X(x)                                               (((x) & 0xFFFF) << 0)
++#define   G_030A2C_X(x)                                               (((x) >> 0) & 0xFFFF)
++#define   C_030A2C_X                                                  0xFFFF0000
++#define   S_030A2C_Y(x)                                               (((x) & 0xFFFF) << 16)
++#define   G_030A2C_Y(x)                                               (((x) >> 16) & 0xFFFF)
++#define   C_030A2C_Y                                                  0x0000FFFF
+ /*     */
+ #define R_008BF0_PA_SC_ENHANCE                                          0x008BF0
+ #define   S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x)                       (((x) & 0x1) << 0)
+@@ -608,6 +764,32 @@
+ #define     V_008DFC_SQ_VGPR                                        0x00
+ /*     */
+ #define R_008DFC_SQ_INST                                                0x008DFC
++#define R_030D20_SQC_CACHES                                             0x030D20
++#define   S_030D20_TARGET_INST(x)                                     (((x) & 0x1) << 0)
++#define   G_030D20_TARGET_INST(x)                                     (((x) >> 0) & 0x1)
++#define   C_030D20_TARGET_INST                                        0xFFFFFFFE
++#define   S_030D20_TARGET_DATA(x)                                     (((x) & 0x1) << 1)
++#define   G_030D20_TARGET_DATA(x)                                     (((x) >> 1) & 0x1)
++#define   C_030D20_TARGET_DATA                                        0xFFFFFFFD
++#define   S_030D20_INVALIDATE(x)                                      (((x) & 0x1) << 2)
++#define   G_030D20_INVALIDATE(x)                                      (((x) >> 2) & 0x1)
++#define   C_030D20_INVALIDATE                                         0xFFFFFFFB
++#define   S_030D20_WRITEBACK(x)                                       (((x) & 0x1) << 3)
++#define   G_030D20_WRITEBACK(x)                                       (((x) >> 3) & 0x1)
++#define   C_030D20_WRITEBACK                                          0xFFFFFFF7
++#define   S_030D20_VOL(x)                                             (((x) & 0x1) << 4)
++#define   G_030D20_VOL(x)                                             (((x) >> 4) & 0x1)
++#define   C_030D20_VOL                                                0xFFFFFFEF
++#define   S_030D20_COMPLETE(x)                                        (((x) & 0x1) << 16)
++#define   G_030D20_COMPLETE(x)                                        (((x) >> 16) & 0x1)
++#define   C_030D20_COMPLETE                                           0xFFFEFFFF
++#define R_030D24_SQC_WRITEBACK                                          0x030D24
++#define   S_030D24_DWB(x)                                             (((x) & 0x1) << 0)
++#define   G_030D24_DWB(x)                                             (((x) >> 0) & 0x1)
++#define   C_030D24_DWB                                                0xFFFFFFFE
++#define   S_030D24_DIRTY(x)                                           (((x) & 0x1) << 1)
++#define   G_030D24_DIRTY(x)                                           (((x) >> 1) & 0x1)
++#define   C_030D24_DIRTY                                              0xFFFFFFFD
+ #define R_008DFC_SQ_VOP1                                                0x008DFC
+ #define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
+ #define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
+@@ -3740,7 +3922,17 @@
+ #define   C_008DFC_ENCODING                                           0x03FFFFFF
+ #define     V_008DFC_SQ_ENC_MUBUF_FIELD                             0x38
+ #endif
++#define R_030E00_TA_CS_BC_BASE_ADDR                                     0x030E00
++#define R_030E04_TA_CS_BC_BASE_ADDR_HI                                  0x030E04
++#define   S_030E04_ADDRESS(x)                                         (((x) & 0xFF) << 0)
++#define   G_030E04_ADDRESS(x)                                         (((x) >> 0) & 0xFF)
++#define   C_030E04_ADDRESS                                            0xFFFFFF00
++#define R_030F00_DB_OCCLUSION_COUNT0_LOW                                0x030F00
+ #define R_008F00_SQ_BUF_RSRC_WORD0                                      0x008F00
++#define R_030F04_DB_OCCLUSION_COUNT0_HI                                 0x030F04
++#define   S_030F04_COUNT_HI(x)                                        (((x) & 0x7FFFFFFF) << 0)
++#define   G_030F04_COUNT_HI(x)                                        (((x) >> 0) & 0x7FFFFFFF)
++#define   C_030F04_COUNT_HI                                           0x80000000
+ #define R_008F04_SQ_BUF_RSRC_WORD1                                      0x008F04
+ #define   S_008F04_BASE_ADDRESS_HI(x)                                 (((x) & 0xFFFF) << 0)
+ #define   G_008F04_BASE_ADDRESS_HI(x)                                 (((x) >> 0) & 0xFFFF)
+@@ -3754,7 +3946,12 @@
+ #define   S_008F04_SWIZZLE_ENABLE(x)                                  (((x) & 0x1) << 31)
+ #define   G_008F04_SWIZZLE_ENABLE(x)                                  (((x) >> 31) & 0x1)
+ #define   C_008F04_SWIZZLE_ENABLE                                     0x7FFFFFFF
++#define R_030F08_DB_OCCLUSION_COUNT1_LOW                                0x030F08
+ #define R_008F08_SQ_BUF_RSRC_WORD2                                      0x008F08
++#define R_030F0C_DB_OCCLUSION_COUNT1_HI                                 0x030F0C
++#define   S_030F0C_COUNT_HI(x)                                        (((x) & 0x7FFFFFFF) << 0)
++#define   G_030F0C_COUNT_HI(x)                                        (((x) >> 0) & 0x7FFFFFFF)
++#define   C_030F0C_COUNT_HI                                           0x80000000
+ #define R_008F0C_SQ_BUF_RSRC_WORD3                                      0x008F0C
+ #define   S_008F0C_DST_SEL_X(x)                                       (((x) & 0x07) << 0)
+ #define   G_008F0C_DST_SEL_X(x)                                       (((x) >> 0) & 0x07)
+@@ -3862,7 +4059,12 @@
+ #define     V_008F0C_SQ_RSRC_BUF_RSVD_1                             0x01
+ #define     V_008F0C_SQ_RSRC_BUF_RSVD_2                             0x02
+ #define     V_008F0C_SQ_RSRC_BUF_RSVD_3                             0x03
++#define R_030F10_DB_OCCLUSION_COUNT2_LOW                                0x030F10
+ #define R_008F10_SQ_IMG_RSRC_WORD0                                      0x008F10
++#define R_030F14_DB_OCCLUSION_COUNT2_HI                                 0x030F14
++#define   S_030F14_COUNT_HI(x)                                        (((x) & 0x7FFFFFFF) << 0)
++#define   G_030F14_COUNT_HI(x)                                        (((x) >> 0) & 0x7FFFFFFF)
++#define   C_030F14_COUNT_HI                                           0x80000000
+ #define R_008F14_SQ_IMG_RSRC_WORD1                                      0x008F14
+ #define   S_008F14_BASE_ADDRESS_HI(x)                                 (((x) & 0xFF) << 0)
+ #define   G_008F14_BASE_ADDRESS_HI(x)                                 (((x) >> 0) & 0xFF)
+@@ -3961,6 +4163,7 @@
+ #define   G_008F14_MTYPE(x)                                           (((x) >> 30) & 0x03)
+ #define   C_008F14_MTYPE                                              0x3FFFFFFF
+ /*     */
++#define R_030F18_DB_OCCLUSION_COUNT3_LOW                                0x030F18
+ #define R_008F18_SQ_IMG_RSRC_WORD2                                      0x008F18
+ #define   S_008F18_WIDTH(x)                                           (((x) & 0x3FFF) << 0)
+ #define   G_008F18_WIDTH(x)                                           (((x) >> 0) & 0x3FFF)
+@@ -3974,6 +4177,10 @@
+ #define   S_008F18_INTERLACED(x)                                      (((x) & 0x1) << 31)
+ #define   G_008F18_INTERLACED(x)                                      (((x) >> 31) & 0x1)
+ #define   C_008F18_INTERLACED                                         0x7FFFFFFF
++#define R_030F1C_DB_OCCLUSION_COUNT3_HI                                 0x030F1C
++#define   S_030F1C_COUNT_HI(x)                                        (((x) & 0x7FFFFFFF) << 0)
++#define   G_030F1C_COUNT_HI(x)                                        (((x) >> 0) & 0x7FFFFFFF)
++#define   C_030F1C_COUNT_HI                                           0x80000000
+ #define R_008F1C_SQ_IMG_RSRC_WORD3                                      0x008F1C
+ #define   S_008F1C_DST_SEL_X(x)                                       (((x) & 0x07) << 0)
+ #define   G_008F1C_DST_SEL_X(x)                                       (((x) >> 0) & 0x07)
+@@ -4084,6 +4291,23 @@
+ #define   G_008F28_LOD_HDW_CNT_EN(x)                                  (((x) >> 20) & 0x1)
+ #define   C_008F28_LOD_HDW_CNT_EN                                     0xFFEFFFFF
+ /*     */
++/* VI */
++#define   S_008F28_COMPRESSION_EN(x)                                  (((x) & 0x1) << 21)
++#define   G_008F28_COMPRESSION_EN(x)                                  (((x) >> 21) & 0x1)
++#define   C_008F28_COMPRESSION_EN                                     0xFFDFFFFF
++#define   S_008F28_ALPHA_IS_ON_MSB(x)                                 (((x) & 0x1) << 22)
++#define   G_008F28_ALPHA_IS_ON_MSB(x)                                 (((x) >> 22) & 0x1)
++#define   C_008F28_ALPHA_IS_ON_MSB                                    0xFFBFFFFF
++#define   S_008F28_COLOR_TRANSFORM(x)                                 (((x) & 0x1) << 23)
++#define   G_008F28_COLOR_TRANSFORM(x)                                 (((x) >> 23) & 0x1)
++#define   C_008F28_COLOR_TRANSFORM                                    0xFF7FFFFF
++#define   S_008F28_LOST_ALPHA_BITS(x)                                 (((x) & 0x0F) << 24)
++#define   G_008F28_LOST_ALPHA_BITS(x)                                 (((x) >> 24) & 0x0F)
++#define   C_008F28_LOST_ALPHA_BITS                                    0xF0FFFFFF
++#define   S_008F28_LOST_COLOR_BITS(x)                                 (((x) & 0x0F) << 28)
++#define   G_008F28_LOST_COLOR_BITS(x)                                 (((x) >> 28) & 0x0F)
++#define   C_008F28_LOST_COLOR_BITS                                    0x0FFFFFFF
++/*    */
+ #define R_008F2C_SQ_IMG_RSRC_WORD7                                      0x008F2C
+ #define R_008F30_SQ_IMG_SAMP_WORD0                                      0x008F30
+ #define   S_008F30_CLAMP_X(x)                                         (((x) & 0x07) << 0)
+@@ -4148,6 +4372,11 @@
+ #define   S_008F30_FILTER_MODE(x)                                     (((x) & 0x03) << 29)
+ #define   G_008F30_FILTER_MODE(x)                                     (((x) >> 29) & 0x03)
+ #define   C_008F30_FILTER_MODE                                        0x9FFFFFFF
++/* VI */
++#define   S_008F30_COMPAT_MODE(x)                                     (((x) & 0x1) << 31)
++#define   G_008F30_COMPAT_MODE(x)                                     (((x) >> 31) & 0x1)
++#define   C_008F30_COMPAT_MODE                                        0x7FFFFFFF
++/*    */
+ #define R_008F34_SQ_IMG_SAMP_WORD1                                      0x008F34
+ #define   S_008F34_MIN_LOD(x)                                         (((x) & 0xFFF) << 0)
+ #define   G_008F34_MIN_LOD(x)                                         (((x) >> 0) & 0xFFF)
+@@ -4313,6 +4542,11 @@
+ #define   G_008F44_OFFSET(x)                                          (((x) >> 0) & 0xFFFFFF)
+ #define   C_008F44_OFFSET                                             0xFF000000
+ /*     */
++#define R_030FF8_DB_ZPASS_COUNT_LOW                                     0x030FF8
++#define R_030FFC_DB_ZPASS_COUNT_HI                                      0x030FFC
++#define   S_030FFC_COUNT_HI(x)                                        (((x) & 0x7FFFFFFF) << 0)
++#define   G_030FFC_COUNT_HI(x)                                        (((x) >> 0) & 0x7FFFFFFF)
++#define   C_030FFC_COUNT_HI                                           0x80000000
+ #define R_009100_SPI_CONFIG_CNTL                                        0x009100
+ #define   S_009100_GPR_WRITE_PRIORITY(x)                              (((x) & 0x1FFFFF) << 0)
+ #define   G_009100_GPR_WRITE_PRIORITY(x)                              (((x) >> 0) & 0x1FFFFF)
+@@ -4437,6 +4671,34 @@
+ #define   S_009858_MSAA16_Y(x)                                        (((x) & 0x03) << 18)
+ #define   G_009858_MSAA16_Y(x)                                        (((x) >> 18) & 0x03)
+ #define   C_009858_MSAA16_Y                                           0xFFF3FFFF
++#define R_0098F8_GB_ADDR_CONFIG                                         0x0098F8
++#define   S_0098F8_NUM_PIPES(x)                                       (((x) & 0x07) << 0)
++#define   G_0098F8_NUM_PIPES(x)                                       (((x) >> 0) & 0x07)
++#define   C_0098F8_NUM_PIPES                                          0xFFFFFFF8
++#define   S_0098F8_PIPE_INTERLEAVE_SIZE(x)                            (((x) & 0x07) << 4)
++#define   G_0098F8_PIPE_INTERLEAVE_SIZE(x)                            (((x) >> 4) & 0x07)
++#define   C_0098F8_PIPE_INTERLEAVE_SIZE                               0xFFFFFF8F
++#define   S_0098F8_BANK_INTERLEAVE_SIZE(x)                            (((x) & 0x07) << 8)
++#define   G_0098F8_BANK_INTERLEAVE_SIZE(x)                            (((x) >> 8) & 0x07)
++#define   C_0098F8_BANK_INTERLEAVE_SIZE                               0xFFFFF8FF
++#define   S_0098F8_NUM_SHADER_ENGINES(x)                              (((x) & 0x03) << 12)
++#define   G_0098F8_NUM_SHADER_ENGINES(x)                              (((x) >> 12) & 0x03)
++#define   C_0098F8_NUM_SHADER_ENGINES                                 0xFFFFCFFF
++#define   S_0098F8_SHADER_ENGINE_TILE_SIZE(x)                         (((x) & 0x07) << 16)
++#define   G_0098F8_SHADER_ENGINE_TILE_SIZE(x)                         (((x) >> 16) & 0x07)
++#define   C_0098F8_SHADER_ENGINE_TILE_SIZE                            0xFFF8FFFF
++#define   S_0098F8_NUM_GPUS(x)                                        (((x) & 0x07) << 20)
++#define   G_0098F8_NUM_GPUS(x)                                        (((x) >> 20) & 0x07)
++#define   C_0098F8_NUM_GPUS                                           0xFF8FFFFF
++#define   S_0098F8_MULTI_GPU_TILE_SIZE(x)                             (((x) & 0x03) << 24)
++#define   G_0098F8_MULTI_GPU_TILE_SIZE(x)                             (((x) >> 24) & 0x03)
++#define   C_0098F8_MULTI_GPU_TILE_SIZE                                0xFCFFFFFF
++#define   S_0098F8_ROW_SIZE(x)                                        (((x) & 0x03) << 28)
++#define   G_0098F8_ROW_SIZE(x)                                        (((x) >> 28) & 0x03)
++#define   C_0098F8_ROW_SIZE                                           0xCFFFFFFF
++#define   S_0098F8_NUM_LOWER_PIPES(x)                                 (((x) & 0x1) << 30)
++#define   G_0098F8_NUM_LOWER_PIPES(x)                                 (((x) >> 30) & 0x1)
++#define   C_0098F8_NUM_LOWER_PIPES                                    0xBFFFFFFF
+ #define R_009910_GB_TILE_MODE0                                          0x009910
+ #define   S_009910_MICRO_TILE_MODE(x)                                 (((x) & 0x03) << 0)
+ #define   G_009910_MICRO_TILE_MODE(x)                                 (((x) >> 0) & 0x03)
+@@ -4515,6 +4777,83 @@
+ #define     V_009910_ADDR_SURF_4_BANK                               0x01
+ #define     V_009910_ADDR_SURF_8_BANK                               0x02
+ #define     V_009910_ADDR_SURF_16_BANK                              0x03
++#define   S_009910_MICRO_TILE_MODE_NEW(x)                             (((x) & 0x07) << 22)
++#define   G_009910_MICRO_TILE_MODE_NEW(x)                             (((x) >> 22) & 0x07)
++#define   C_009910_MICRO_TILE_MODE_NEW                                0xFE3FFFFF
++#define   S_009910_SAMPLE_SPLIT(x)                                    (((x) & 0x03) << 25)
++#define   G_009910_SAMPLE_SPLIT(x)                                    (((x) >> 25) & 0x03)
++#define   C_009910_SAMPLE_SPLIT                                       0xF9FFFFFF
++#define R_009914_GB_TILE_MODE1                                          0x009914
++#define R_009918_GB_TILE_MODE2                                          0x009918
++#define R_00991C_GB_TILE_MODE3                                          0x00991C
++#define R_009920_GB_TILE_MODE4                                          0x009920
++#define R_009924_GB_TILE_MODE5                                          0x009924
++#define R_009928_GB_TILE_MODE6                                          0x009928
++#define R_00992C_GB_TILE_MODE7                                          0x00992C
++#define R_009930_GB_TILE_MODE8                                          0x009930
++#define R_009934_GB_TILE_MODE9                                          0x009934
++#define R_009938_GB_TILE_MODE10                                         0x009938
++#define R_00993C_GB_TILE_MODE11                                         0x00993C
++#define R_009940_GB_TILE_MODE12                                         0x009940
++#define R_009944_GB_TILE_MODE13                                         0x009944
++#define R_009948_GB_TILE_MODE14                                         0x009948
++#define R_00994C_GB_TILE_MODE15                                         0x00994C
++#define R_009950_GB_TILE_MODE16                                         0x009950
++#define R_009954_GB_TILE_MODE17                                         0x009954
++#define R_009958_GB_TILE_MODE18                                         0x009958
++#define R_00995C_GB_TILE_MODE19                                         0x00995C
++#define R_009960_GB_TILE_MODE20                                         0x009960
++#define R_009964_GB_TILE_MODE21                                         0x009964
++#define R_009968_GB_TILE_MODE22                                         0x009968
++#define R_00996C_GB_TILE_MODE23                                         0x00996C
++#define R_009970_GB_TILE_MODE24                                         0x009970
++#define R_009974_GB_TILE_MODE25                                         0x009974
++#define R_009978_GB_TILE_MODE26                                         0x009978
++#define R_00997C_GB_TILE_MODE27                                         0x00997C
++#define R_009980_GB_TILE_MODE28                                         0x009980
++#define R_009984_GB_TILE_MODE29                                         0x009984
++#define R_009988_GB_TILE_MODE30                                         0x009988
++#define R_00998C_GB_TILE_MODE31                                         0x00998C
++/* CIK */
++#define R_009990_GB_MACROTILE_MODE0                                     0x009990
++#define   S_009990_BANK_WIDTH(x)                                      (((x) & 0x03) << 0)
++#define   G_009990_BANK_WIDTH(x)                                      (((x) >> 0) & 0x03)
++#define   C_009990_BANK_WIDTH                                         0xFFFFFFFC
++#define   S_009990_BANK_HEIGHT(x)                                     (((x) & 0x03) << 2)
++#define   G_009990_BANK_HEIGHT(x)                                     (((x) >> 2) & 0x03)
++#define   C_009990_BANK_HEIGHT                                        0xFFFFFFF3
++#define   S_009990_MACRO_TILE_ASPECT(x)                               (((x) & 0x03) << 4)
++#define   G_009990_MACRO_TILE_ASPECT(x)                               (((x) >> 4) & 0x03)
++#define   C_009990_MACRO_TILE_ASPECT                                  0xFFFFFFCF
++#define   S_009990_NUM_BANKS(x)                                       (((x) & 0x03) << 6)
++#define   G_009990_NUM_BANKS(x)                                       (((x) >> 6) & 0x03)
++#define   C_009990_NUM_BANKS                                          0xFFFFFF3F
++#define R_009994_GB_MACROTILE_MODE1                                     0x009994
++#define R_009998_GB_MACROTILE_MODE2                                     0x009998
++#define R_00999C_GB_MACROTILE_MODE3                                     0x00999C
++#define R_0099A0_GB_MACROTILE_MODE4                                     0x0099A0
++#define R_0099A4_GB_MACROTILE_MODE5                                     0x0099A4
++#define R_0099A8_GB_MACROTILE_MODE6                                     0x0099A8
++#define R_0099AC_GB_MACROTILE_MODE7                                     0x0099AC
++#define R_0099B0_GB_MACROTILE_MODE8                                     0x0099B0
++#define R_0099B4_GB_MACROTILE_MODE9                                     0x0099B4
++#define R_0099B8_GB_MACROTILE_MODE10                                    0x0099B8
++#define R_0099BC_GB_MACROTILE_MODE11                                    0x0099BC
++#define R_0099C0_GB_MACROTILE_MODE12                                    0x0099C0
++#define R_0099C4_GB_MACROTILE_MODE13                                    0x0099C4
++#define R_0099C8_GB_MACROTILE_MODE14                                    0x0099C8
++#define R_0099CC_GB_MACROTILE_MODE15                                    0x0099CC
++/*     */
++#define R_00B000_SPI_SHADER_TBA_LO_PS                                   0x00B000
++#define R_00B004_SPI_SHADER_TBA_HI_PS                                   0x00B004
++#define   S_00B004_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B004_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B004_MEM_BASE                                           0xFFFFFF00
++#define R_00B008_SPI_SHADER_TMA_LO_PS                                   0x00B008
++#define R_00B00C_SPI_SHADER_TMA_HI_PS                                   0x00B00C
++#define   S_00B00C_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B00C_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B00C_MEM_BASE                                           0xFFFFFF00
+ /* CIK */
+ #define R_00B01C_SPI_SHADER_PGM_RSRC3_PS                                0x00B01C
+ #define   S_00B01C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+@@ -4575,6 +4914,9 @@
+ #define   S_00B02C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B02C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B02C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B02C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B02C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B02C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B02C_WAVE_CNT_EN(x)                                     (((x) & 0x1) << 7)
+ #define   G_00B02C_WAVE_CNT_EN(x)                                     (((x) >> 7) & 0x1)
+ #define   C_00B02C_WAVE_CNT_EN                                        0xFFFFFF7F
+@@ -4584,6 +4926,9 @@
+ #define   S_00B02C_EXCP_EN(x)                                         (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
+ #define   G_00B02C_EXCP_EN(x)                                         (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
+ #define   C_00B02C_EXCP_EN                                            0xFF80FFFF /* mask is 0x1FF on CIK */
++#define   S_00B02C_EXCP_EN_CIK(x)                                     (((x) & 0x1FF) << 16)
++#define   G_00B02C_EXCP_EN_CIK(x)                                     (((x) >> 16) & 0x1FF)
++#define   C_00B02C_EXCP_EN_CIK                                        0xFE00FFFF
+ #define R_00B030_SPI_SHADER_USER_DATA_PS_0                              0x00B030
+ #define R_00B034_SPI_SHADER_USER_DATA_PS_1                              0x00B034
+ #define R_00B038_SPI_SHADER_USER_DATA_PS_2                              0x00B038
+@@ -4600,6 +4945,16 @@
+ #define R_00B064_SPI_SHADER_USER_DATA_PS_13                             0x00B064
+ #define R_00B068_SPI_SHADER_USER_DATA_PS_14                             0x00B068
+ #define R_00B06C_SPI_SHADER_USER_DATA_PS_15                             0x00B06C
++#define R_00B100_SPI_SHADER_TBA_LO_VS                                   0x00B100
++#define R_00B104_SPI_SHADER_TBA_HI_VS                                   0x00B104
++#define   S_00B104_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B104_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B104_MEM_BASE                                           0xFFFFFF00
++#define R_00B108_SPI_SHADER_TMA_LO_VS                                   0x00B108
++#define R_00B10C_SPI_SHADER_TMA_HI_VS                                   0x00B10C
++#define   S_00B10C_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B10C_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B10C_MEM_BASE                                           0xFFFFFF00
+ /* CIK */
+ #define R_00B118_SPI_SHADER_PGM_RSRC3_VS                                0x00B118
+ #define   S_00B118_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+@@ -4667,6 +5022,9 @@
+ #define   S_00B12C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B12C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B12C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B12C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B12C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B12C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B12C_OC_LDS_EN(x)                                       (((x) & 0x1) << 7)
+ #define   G_00B12C_OC_LDS_EN(x)                                       (((x) >> 7) & 0x1)
+ #define   C_00B12C_OC_LDS_EN                                          0xFFFFFF7F
+@@ -4688,6 +5046,14 @@
+ #define   S_00B12C_EXCP_EN(x)                                         (((x) & 0x7F) << 13) /* mask is 0x1FF on CIK */
+ #define   G_00B12C_EXCP_EN(x)                                         (((x) >> 13) & 0x7F) /* mask is 0x1FF on CIK */
+ #define   C_00B12C_EXCP_EN                                            0xFFF01FFF /* mask is 0x1FF on CIK */
++#define   S_00B12C_EXCP_EN_CIK(x)                                     (((x) & 0x1FF) << 13)
++#define   G_00B12C_EXCP_EN_CIK(x)                                     (((x) >> 13) & 0x1FF)
++#define   C_00B12C_EXCP_EN_CIK                                        0xFFC01FFF
++/* VI */
++#define   S_00B12C_DISPATCH_DRAW_EN(x)                                (((x) & 0x1) << 24)
++#define   G_00B12C_DISPATCH_DRAW_EN(x)                                (((x) >> 24) & 0x1)
++#define   C_00B12C_DISPATCH_DRAW_EN                                   0xFEFFFFFF
++/*    */
+ #define R_00B130_SPI_SHADER_USER_DATA_VS_0                              0x00B130
+ #define R_00B134_SPI_SHADER_USER_DATA_VS_1                              0x00B134
+ #define R_00B138_SPI_SHADER_USER_DATA_VS_2                              0x00B138
+@@ -4704,6 +5070,16 @@
+ #define R_00B164_SPI_SHADER_USER_DATA_VS_13                             0x00B164
+ #define R_00B168_SPI_SHADER_USER_DATA_VS_14                             0x00B168
+ #define R_00B16C_SPI_SHADER_USER_DATA_VS_15                             0x00B16C
++#define R_00B200_SPI_SHADER_TBA_LO_GS                                   0x00B200
++#define R_00B204_SPI_SHADER_TBA_HI_GS                                   0x00B204
++#define   S_00B204_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B204_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B204_MEM_BASE                                           0xFFFFFF00
++#define R_00B208_SPI_SHADER_TMA_LO_GS                                   0x00B208
++#define R_00B20C_SPI_SHADER_TMA_HI_GS                                   0x00B20C
++#define   S_00B20C_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B20C_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B20C_MEM_BASE                                           0xFFFFFF00
+ /* CIK */
+ #define R_00B21C_SPI_SHADER_PGM_RSRC3_GS                                0x00B21C
+ #define   S_00B21C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+@@ -4716,6 +5092,11 @@
+ #define   G_00B21C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+ #define   C_00B21C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+ /*     */
++/* VI */
++#define   S_00B21C_GROUP_FIFO_DEPTH(x)                                (((x) & 0x3F) << 26)
++#define   G_00B21C_GROUP_FIFO_DEPTH(x)                                (((x) >> 26) & 0x3F)
++#define   C_00B21C_GROUP_FIFO_DEPTH                                   0x03FFFFFF
++/*    */
+ #define R_00B220_SPI_SHADER_PGM_LO_GS                                   0x00B220
+ #define R_00B224_SPI_SHADER_PGM_HI_GS                                   0x00B224
+ #define   S_00B224_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+@@ -4764,10 +5145,41 @@
+ #define   S_00B22C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B22C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B22C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B22C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B22C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B22C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B22C_EXCP_EN(x)                                         (((x) & 0x7F) << 7) /* mask is 0x1FF on CIK */
+ #define   G_00B22C_EXCP_EN(x)                                         (((x) >> 7) & 0x7F) /* mask is 0x1FF on CIK */
+ #define   C_00B22C_EXCP_EN                                            0xFFFFC07F /* mask is 0x1FF on CIK */
++#define   S_00B22C_EXCP_EN_CIK(x)                                     (((x) & 0x1FF) << 7)
++#define   G_00B22C_EXCP_EN_CIK(x)                                     (((x) >> 7) & 0x1FF)
++#define   C_00B22C_EXCP_EN_CIK                                        0xFFFF007F
+ #define R_00B230_SPI_SHADER_USER_DATA_GS_0                              0x00B230
++#define R_00B234_SPI_SHADER_USER_DATA_GS_1                              0x00B234
++#define R_00B238_SPI_SHADER_USER_DATA_GS_2                              0x00B238
++#define R_00B23C_SPI_SHADER_USER_DATA_GS_3                              0x00B23C
++#define R_00B240_SPI_SHADER_USER_DATA_GS_4                              0x00B240
++#define R_00B244_SPI_SHADER_USER_DATA_GS_5                              0x00B244
++#define R_00B248_SPI_SHADER_USER_DATA_GS_6                              0x00B248
++#define R_00B24C_SPI_SHADER_USER_DATA_GS_7                              0x00B24C
++#define R_00B250_SPI_SHADER_USER_DATA_GS_8                              0x00B250
++#define R_00B254_SPI_SHADER_USER_DATA_GS_9                              0x00B254
++#define R_00B258_SPI_SHADER_USER_DATA_GS_10                             0x00B258
++#define R_00B25C_SPI_SHADER_USER_DATA_GS_11                             0x00B25C
++#define R_00B260_SPI_SHADER_USER_DATA_GS_12                             0x00B260
++#define R_00B264_SPI_SHADER_USER_DATA_GS_13                             0x00B264
++#define R_00B268_SPI_SHADER_USER_DATA_GS_14                             0x00B268
++#define R_00B26C_SPI_SHADER_USER_DATA_GS_15                             0x00B26C
++#define R_00B300_SPI_SHADER_TBA_LO_ES                                   0x00B300
++#define R_00B304_SPI_SHADER_TBA_HI_ES                                   0x00B304
++#define   S_00B304_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B304_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B304_MEM_BASE                                           0xFFFFFF00
++#define R_00B308_SPI_SHADER_TMA_LO_ES                                   0x00B308
++#define R_00B30C_SPI_SHADER_TMA_HI_ES                                   0x00B30C
++#define   S_00B30C_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B30C_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B30C_MEM_BASE                                           0xFFFFFF00
+ /* CIK */
+ #define R_00B31C_SPI_SHADER_PGM_RSRC3_ES                                0x00B31C
+ #define   S_00B31C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+@@ -4780,6 +5192,11 @@
+ #define   G_00B31C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+ #define   C_00B31C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+ /*     */
++/* VI */
++#define   S_00B31C_GROUP_FIFO_DEPTH(x)                                (((x) & 0x3F) << 26)
++#define   G_00B31C_GROUP_FIFO_DEPTH(x)                                (((x) >> 26) & 0x3F)
++#define   C_00B31C_GROUP_FIFO_DEPTH                                   0x03FFFFFF
++/*    */
+ #define R_00B320_SPI_SHADER_PGM_LO_ES                                   0x00B320
+ #define R_00B324_SPI_SHADER_PGM_HI_ES                                   0x00B324
+ #define   S_00B324_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+@@ -4831,6 +5248,9 @@
+ #define   S_00B32C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B32C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B32C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B32C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B32C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B32C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B32C_OC_LDS_EN(x)                                       (((x) & 0x1) << 7)
+ #define   G_00B32C_OC_LDS_EN(x)                                       (((x) >> 7) & 0x1)
+ #define   C_00B32C_OC_LDS_EN                                          0xFFFFFF7F
+@@ -4841,6 +5261,31 @@
+ #define   G_00B32C_LDS_SIZE(x)                                        (((x) >> 20) & 0x1FF) /* CIK, for on-chip GS */
+ #define   C_00B32C_LDS_SIZE                                           0xE00FFFFF /* CIK, for on-chip GS */
+ #define R_00B330_SPI_SHADER_USER_DATA_ES_0                              0x00B330
++#define R_00B334_SPI_SHADER_USER_DATA_ES_1                              0x00B334
++#define R_00B338_SPI_SHADER_USER_DATA_ES_2                              0x00B338
++#define R_00B33C_SPI_SHADER_USER_DATA_ES_3                              0x00B33C
++#define R_00B340_SPI_SHADER_USER_DATA_ES_4                              0x00B340
++#define R_00B344_SPI_SHADER_USER_DATA_ES_5                              0x00B344
++#define R_00B348_SPI_SHADER_USER_DATA_ES_6                              0x00B348
++#define R_00B34C_SPI_SHADER_USER_DATA_ES_7                              0x00B34C
++#define R_00B350_SPI_SHADER_USER_DATA_ES_8                              0x00B350
++#define R_00B354_SPI_SHADER_USER_DATA_ES_9                              0x00B354
++#define R_00B358_SPI_SHADER_USER_DATA_ES_10                             0x00B358
++#define R_00B35C_SPI_SHADER_USER_DATA_ES_11                             0x00B35C
++#define R_00B360_SPI_SHADER_USER_DATA_ES_12                             0x00B360
++#define R_00B364_SPI_SHADER_USER_DATA_ES_13                             0x00B364
++#define R_00B368_SPI_SHADER_USER_DATA_ES_14                             0x00B368
++#define R_00B36C_SPI_SHADER_USER_DATA_ES_15                             0x00B36C
++#define R_00B400_SPI_SHADER_TBA_LO_HS                                   0x00B400
++#define R_00B404_SPI_SHADER_TBA_HI_HS                                   0x00B404
++#define   S_00B404_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B404_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B404_MEM_BASE                                           0xFFFFFF00
++#define R_00B408_SPI_SHADER_TMA_LO_HS                                   0x00B408
++#define R_00B40C_SPI_SHADER_TMA_HI_HS                                   0x00B40C
++#define   S_00B40C_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B40C_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B40C_MEM_BASE                                           0xFFFFFF00
+ /* CIK */
+ #define R_00B41C_SPI_SHADER_PGM_RSRC3_HS                                0x00B41C
+ #define   S_00B41C_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 0)
+@@ -4850,6 +5295,11 @@
+ #define   G_00B41C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 6) & 0x0F)
+ #define   C_00B41C_LOCK_LOW_THRESHOLD                                 0xFFFFFC3F
+ /*     */
++/* VI */
++#define   S_00B41C_GROUP_FIFO_DEPTH(x)                                (((x) & 0x3F) << 10)
++#define   G_00B41C_GROUP_FIFO_DEPTH(x)                                (((x) >> 10) & 0x3F)
++#define   C_00B41C_GROUP_FIFO_DEPTH                                   0xFFFF03FF
++/*    */
+ #define R_00B420_SPI_SHADER_PGM_LO_HS                                   0x00B420
+ #define R_00B424_SPI_SHADER_PGM_HI_HS                                   0x00B424
+ #define   S_00B424_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+@@ -4895,6 +5345,9 @@
+ #define   S_00B42C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B42C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B42C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B42C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B42C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B42C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B42C_OC_LDS_EN(x)                                       (((x) & 0x1) << 7)
+ #define   G_00B42C_OC_LDS_EN(x)                                       (((x) >> 7) & 0x1)
+ #define   C_00B42C_OC_LDS_EN                                          0xFFFFFF7F
+@@ -4905,6 +5358,31 @@
+ #define   G_00B42C_EXCP_EN(x)                                         (((x) >> 9) & 0x7F) /* mask is 0x1FF on CIK */
+ #define   C_00B42C_EXCP_EN                                            0xFFFF01FF /* mask is 0x1FF on CIK */
+ #define R_00B430_SPI_SHADER_USER_DATA_HS_0                              0x00B430
++#define R_00B434_SPI_SHADER_USER_DATA_HS_1                              0x00B434
++#define R_00B438_SPI_SHADER_USER_DATA_HS_2                              0x00B438
++#define R_00B43C_SPI_SHADER_USER_DATA_HS_3                              0x00B43C
++#define R_00B440_SPI_SHADER_USER_DATA_HS_4                              0x00B440
++#define R_00B444_SPI_SHADER_USER_DATA_HS_5                              0x00B444
++#define R_00B448_SPI_SHADER_USER_DATA_HS_6                              0x00B448
++#define R_00B44C_SPI_SHADER_USER_DATA_HS_7                              0x00B44C
++#define R_00B450_SPI_SHADER_USER_DATA_HS_8                              0x00B450
++#define R_00B454_SPI_SHADER_USER_DATA_HS_9                              0x00B454
++#define R_00B458_SPI_SHADER_USER_DATA_HS_10                             0x00B458
++#define R_00B45C_SPI_SHADER_USER_DATA_HS_11                             0x00B45C
++#define R_00B460_SPI_SHADER_USER_DATA_HS_12                             0x00B460
++#define R_00B464_SPI_SHADER_USER_DATA_HS_13                             0x00B464
++#define R_00B468_SPI_SHADER_USER_DATA_HS_14                             0x00B468
++#define R_00B46C_SPI_SHADER_USER_DATA_HS_15                             0x00B46C
++#define R_00B500_SPI_SHADER_TBA_LO_LS                                   0x00B500
++#define R_00B504_SPI_SHADER_TBA_HI_LS                                   0x00B504
++#define   S_00B504_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B504_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B504_MEM_BASE                                           0xFFFFFF00
++#define R_00B508_SPI_SHADER_TMA_LO_LS                                   0x00B508
++#define R_00B50C_SPI_SHADER_TMA_HI_LS                                   0x00B50C
++#define   S_00B50C_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
++#define   G_00B50C_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
++#define   C_00B50C_MEM_BASE                                           0xFFFFFF00
+ /* CIK */
+ #define R_00B51C_SPI_SHADER_PGM_RSRC3_LS                                0x00B51C
+ #define   S_00B51C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+@@ -4917,6 +5395,11 @@
+ #define   G_00B51C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+ #define   C_00B51C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+ /*     */
++/* VI */
++#define   S_00B51C_GROUP_FIFO_DEPTH(x)                                (((x) & 0x3F) << 26)
++#define   G_00B51C_GROUP_FIFO_DEPTH(x)                                (((x) >> 26) & 0x3F)
++#define   C_00B51C_GROUP_FIFO_DEPTH                                   0x03FFFFFF
++/*    */
+ #define R_00B520_SPI_SHADER_PGM_LO_LS                                   0x00B520
+ #define R_00B524_SPI_SHADER_PGM_HI_LS                                   0x00B524
+ #define   S_00B524_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+@@ -4965,6 +5448,9 @@
+ #define   S_00B52C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B52C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B52C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B52C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B52C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B52C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B52C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 7)
+ #define   G_00B52C_LDS_SIZE(x)                                        (((x) >> 7) & 0x1FF)
+ #define   C_00B52C_LDS_SIZE                                           0xFFFF007F
+@@ -4972,6 +5458,21 @@
+ #define   G_00B52C_EXCP_EN(x)                                         (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
+ #define   C_00B52C_EXCP_EN                                            0xFF80FFFF /* mask is 0x1FF on CIK */
+ #define R_00B530_SPI_SHADER_USER_DATA_LS_0                              0x00B530
++#define R_00B534_SPI_SHADER_USER_DATA_LS_1                              0x00B534
++#define R_00B538_SPI_SHADER_USER_DATA_LS_2                              0x00B538
++#define R_00B53C_SPI_SHADER_USER_DATA_LS_3                              0x00B53C
++#define R_00B540_SPI_SHADER_USER_DATA_LS_4                              0x00B540
++#define R_00B544_SPI_SHADER_USER_DATA_LS_5                              0x00B544
++#define R_00B548_SPI_SHADER_USER_DATA_LS_6                              0x00B548
++#define R_00B54C_SPI_SHADER_USER_DATA_LS_7                              0x00B54C
++#define R_00B550_SPI_SHADER_USER_DATA_LS_8                              0x00B550
++#define R_00B554_SPI_SHADER_USER_DATA_LS_9                              0x00B554
++#define R_00B558_SPI_SHADER_USER_DATA_LS_10                             0x00B558
++#define R_00B55C_SPI_SHADER_USER_DATA_LS_11                             0x00B55C
++#define R_00B560_SPI_SHADER_USER_DATA_LS_12                             0x00B560
++#define R_00B564_SPI_SHADER_USER_DATA_LS_13                             0x00B564
++#define R_00B568_SPI_SHADER_USER_DATA_LS_14                             0x00B568
++#define R_00B56C_SPI_SHADER_USER_DATA_LS_15                             0x00B56C
+ #define R_00B800_COMPUTE_DISPATCH_INITIATOR                             0x00B800
+ #define   S_00B800_COMPUTE_SHADER_EN(x)                               (((x) & 0x1) << 0)
+ #define   G_00B800_COMPUTE_SHADER_EN(x)                               (((x) >> 0) & 0x1)
+@@ -5042,6 +5543,16 @@
+ #define   S_00B82C_MAX_WAVE_ID(x)                                     (((x) & 0xFFF) << 0)
+ #define   G_00B82C_MAX_WAVE_ID(x)                                     (((x) >> 0) & 0xFFF)
+ #define   C_00B82C_MAX_WAVE_ID                                        0xFFFFF000
++/* CIK */
++#define R_00B828_COMPUTE_PIPELINESTAT_ENABLE                            0x00B828
++#define   S_00B828_PIPELINESTAT_ENABLE(x)                             (((x) & 0x1) << 0)
++#define   G_00B828_PIPELINESTAT_ENABLE(x)                             (((x) >> 0) & 0x1)
++#define   C_00B828_PIPELINESTAT_ENABLE                                0xFFFFFFFE
++#define R_00B82C_COMPUTE_PERFCOUNT_ENABLE                               0x00B82C
++#define   S_00B82C_PERFCOUNT_ENABLE(x)                                (((x) & 0x1) << 0)
++#define   G_00B82C_PERFCOUNT_ENABLE(x)                                (((x) >> 0) & 0x1)
++#define   C_00B82C_PERFCOUNT_ENABLE                                   0xFFFFFFFE
++/*     */
+ #define R_00B830_COMPUTE_PGM_LO                                         0x00B830
+ #define R_00B834_COMPUTE_PGM_HI                                         0x00B834
+ #define   S_00B834_DATA(x)                                            (((x) & 0xFF) << 0)
+@@ -5052,6 +5563,16 @@
+ #define   G_00B834_INST_ATC(x)                                        (((x) >> 8) & 0x1)
+ #define   C_00B834_INST_ATC                                           0xFFFFFEFF
+ /*     */
++#define R_00B838_COMPUTE_TBA_LO                                         0x00B838
++#define R_00B83C_COMPUTE_TBA_HI                                         0x00B83C
++#define   S_00B83C_DATA(x)                                            (((x) & 0xFF) << 0)
++#define   G_00B83C_DATA(x)                                            (((x) >> 0) & 0xFF)
++#define   C_00B83C_DATA                                               0xFFFFFF00
++#define R_00B840_COMPUTE_TMA_LO                                         0x00B840
++#define R_00B844_COMPUTE_TMA_HI                                         0x00B844
++#define   S_00B844_DATA(x)                                            (((x) & 0xFF) << 0)
++#define   G_00B844_DATA(x)                                            (((x) >> 0) & 0xFF)
++#define   C_00B844_DATA                                               0xFFFFFF00
+ #define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
+ #define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
+ #define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+@@ -5092,6 +5613,9 @@
+ #define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+ #define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+ #define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
++#define   S_00B84C_TRAP_PRESENT(x)                                    (((x) & 0x1) << 6)
++#define   G_00B84C_TRAP_PRESENT(x)                                    (((x) >> 6) & 0x1)
++#define   C_00B84C_TRAP_PRESENT                                       0xFFFFFFBF
+ #define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
+ #define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
+ #define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
+@@ -5118,6 +5642,10 @@
+ #define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
+ #define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
+ #define   C_00B84C_EXCP_EN                                            0x80FFFFFF
++#define R_00B850_COMPUTE_VMID                                           0x00B850
++#define   S_00B850_DATA(x)                                            (((x) & 0x0F) << 0)
++#define   G_00B850_DATA(x)                                            (((x) >> 0) & 0x0F)
++#define   C_00B850_DATA                                               0xFFFFFFF0
+ #define R_00B854_COMPUTE_RESOURCE_LIMITS                                0x00B854
+ #define   S_00B854_WAVES_PER_SH(x)                                    (((x) & 0x3F) << 0) /* mask is 0x3FF on CIK */
+ #define   G_00B854_WAVES_PER_SH(x)                                    (((x) >> 0) & 0x3F) /* mask is 0x3FF on CIK */
+@@ -5160,7 +5688,84 @@
+ #define   S_00B860_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
+ #define   G_00B860_WAVESIZE(x)                                        (((x) >> 12) & 0x1FFF)
+ #define   C_00B860_WAVESIZE                                           0xFE000FFF
++/* CIK */
++#define R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2                         0x00B864
++#define   S_00B864_SH0_CU_EN(x)                                       (((x) & 0xFFFF) << 0)
++#define   G_00B864_SH0_CU_EN(x)                                       (((x) >> 0) & 0xFFFF)
++#define   C_00B864_SH0_CU_EN                                          0xFFFF0000
++#define   S_00B864_SH1_CU_EN(x)                                       (((x) & 0xFFFF) << 16)
++#define   G_00B864_SH1_CU_EN(x)                                       (((x) >> 16) & 0xFFFF)
++#define   C_00B864_SH1_CU_EN                                          0x0000FFFF
++#define R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3                         0x00B868
++#define   S_00B868_SH0_CU_EN(x)                                       (((x) & 0xFFFF) << 0)
++#define   G_00B868_SH0_CU_EN(x)                                       (((x) >> 0) & 0xFFFF)
++#define   C_00B868_SH0_CU_EN                                          0xFFFF0000
++#define   S_00B868_SH1_CU_EN(x)                                       (((x) & 0xFFFF) << 16)
++#define   G_00B868_SH1_CU_EN(x)                                       (((x) >> 16) & 0xFFFF)
++#define   C_00B868_SH1_CU_EN                                          0x0000FFFF
++#define R_00B86C_COMPUTE_RESTART_X                                      0x00B86C
++#define R_00B870_COMPUTE_RESTART_Y                                      0x00B870
++#define R_00B874_COMPUTE_RESTART_Z                                      0x00B874
++#define R_00B87C_COMPUTE_MISC_RESERVED                                  0x00B87C
++#define   S_00B87C_SEND_SEID(x)                                       (((x) & 0x03) << 0)
++#define   G_00B87C_SEND_SEID(x)                                       (((x) >> 0) & 0x03)
++#define   C_00B87C_SEND_SEID                                          0xFFFFFFFC
++#define   S_00B87C_RESERVED2(x)                                       (((x) & 0x1) << 2)
++#define   G_00B87C_RESERVED2(x)                                       (((x) >> 2) & 0x1)
++#define   C_00B87C_RESERVED2                                          0xFFFFFFFB
++#define   S_00B87C_RESERVED3(x)                                       (((x) & 0x1) << 3)
++#define   G_00B87C_RESERVED3(x)                                       (((x) >> 3) & 0x1)
++#define   C_00B87C_RESERVED3                                          0xFFFFFFF7
++#define   S_00B87C_RESERVED4(x)                                       (((x) & 0x1) << 4)
++#define   G_00B87C_RESERVED4(x)                                       (((x) >> 4) & 0x1)
++#define   C_00B87C_RESERVED4                                          0xFFFFFFEF
++/* VI */
++#define   S_00B87C_WAVE_ID_BASE(x)                                    (((x) & 0xFFF) << 5)
++#define   G_00B87C_WAVE_ID_BASE(x)                                    (((x) >> 5) & 0xFFF)
++#define   C_00B87C_WAVE_ID_BASE                                       0xFFFE001F
++#define R_00B880_COMPUTE_DISPATCH_ID                                    0x00B880
++#define R_00B884_COMPUTE_THREADGROUP_ID                                 0x00B884
++#define R_00B888_COMPUTE_RELAUNCH                                       0x00B888
++#define   S_00B888_PAYLOAD(x)                                         (((x) & 0x3FFFFFFF) << 0)
++#define   G_00B888_PAYLOAD(x)                                         (((x) >> 0) & 0x3FFFFFFF)
++#define   C_00B888_PAYLOAD                                            0xC0000000
++#define   S_00B888_IS_EVENT(x)                                        (((x) & 0x1) << 30)
++#define   G_00B888_IS_EVENT(x)                                        (((x) >> 30) & 0x1)
++#define   C_00B888_IS_EVENT                                           0xBFFFFFFF
++#define   S_00B888_IS_STATE(x)                                        (((x) & 0x1) << 31)
++#define   G_00B888_IS_STATE(x)                                        (((x) >> 31) & 0x1)
++#define   C_00B888_IS_STATE                                           0x7FFFFFFF
++#define R_00B88C_COMPUTE_WAVE_RESTORE_ADDR_LO                           0x00B88C
++#define R_00B890_COMPUTE_WAVE_RESTORE_ADDR_HI                           0x00B890
++#define   S_00B890_ADDR(x)                                            (((x) & 0xFFFF) << 0)
++#define   G_00B890_ADDR(x)                                            (((x) >> 0) & 0xFFFF)
++#define   C_00B890_ADDR                                               0xFFFF0000
++#define R_00B894_COMPUTE_WAVE_RESTORE_CONTROL                           0x00B894
++#define   S_00B894_ATC(x)                                             (((x) & 0x1) << 0)
++#define   G_00B894_ATC(x)                                             (((x) >> 0) & 0x1)
++#define   C_00B894_ATC                                                0xFFFFFFFE
++#define   S_00B894_MTYPE(x)                                           (((x) & 0x03) << 1)
++#define   G_00B894_MTYPE(x)                                           (((x) >> 1) & 0x03)
++#define   C_00B894_MTYPE                                              0xFFFFFFF9
++/*    */
++/*     */
+ #define R_00B900_COMPUTE_USER_DATA_0                                    0x00B900
++#define R_00B904_COMPUTE_USER_DATA_1                                    0x00B904
++#define R_00B908_COMPUTE_USER_DATA_2                                    0x00B908
++#define R_00B90C_COMPUTE_USER_DATA_3                                    0x00B90C
++#define R_00B910_COMPUTE_USER_DATA_4                                    0x00B910
++#define R_00B914_COMPUTE_USER_DATA_5                                    0x00B914
++#define R_00B918_COMPUTE_USER_DATA_6                                    0x00B918
++#define R_00B91C_COMPUTE_USER_DATA_7                                    0x00B91C
++#define R_00B920_COMPUTE_USER_DATA_8                                    0x00B920
++#define R_00B924_COMPUTE_USER_DATA_9                                    0x00B924
++#define R_00B928_COMPUTE_USER_DATA_10                                   0x00B928
++#define R_00B92C_COMPUTE_USER_DATA_11                                   0x00B92C
++#define R_00B930_COMPUTE_USER_DATA_12                                   0x00B930
++#define R_00B934_COMPUTE_USER_DATA_13                                   0x00B934
++#define R_00B938_COMPUTE_USER_DATA_14                                   0x00B938
++#define R_00B93C_COMPUTE_USER_DATA_15                                   0x00B93C
++#define R_00B9FC_COMPUTE_NOWHERE                                        0x00B9FC
+ #define R_028000_DB_RENDER_CONTROL                                      0x028000
+ #define   S_028000_DEPTH_CLEAR_ENABLE(x)                              (((x) & 0x1) << 0)
+ #define   G_028000_DEPTH_CLEAR_ENABLE(x)                              (((x) >> 0) & 0x1)
+@@ -5189,6 +5794,11 @@
+ #define   S_028000_COPY_SAMPLE(x)                                     (((x) & 0x0F) << 8)
+ #define   G_028000_COPY_SAMPLE(x)                                     (((x) >> 8) & 0x0F)
+ #define   C_028000_COPY_SAMPLE                                        0xFFFFF0FF
++/* VI */
++#define   S_028000_DECOMPRESS_ENABLE(x)                               (((x) & 0x1) << 12)
++#define   G_028000_DECOMPRESS_ENABLE(x)                               (((x) >> 12) & 0x1)
++#define   C_028000_DECOMPRESS_ENABLE                                  0xFFFFEFFF
++/*    */
+ #define R_028004_DB_COUNT_CONTROL                                       0x028004
+ #define   S_028004_ZPASS_INCREMENT_DISABLE(x)                         (((x) & 0x1) << 0)
+ #define   G_028004_ZPASS_INCREMENT_DISABLE(x)                         (((x) >> 0) & 0x1)
+@@ -5467,9 +6077,6 @@
+ #define   S_028040_NUM_SAMPLES(x)                                     (((x) & 0x03) << 2)
+ #define   G_028040_NUM_SAMPLES(x)                                     (((x) >> 2) & 0x03)
+ #define   C_028040_NUM_SAMPLES                                        0xFFFFFFF3
+-#define   S_028040_TILE_MODE_INDEX(x)                                 (((x) & 0x07) << 20) /* not on CIK */
+-#define   G_028040_TILE_MODE_INDEX(x)                                 (((x) >> 20) & 0x07) /* not on CIK */
+-#define   C_028040_TILE_MODE_INDEX                                    0xFF8FFFFF /* not on CIK */
+ /* CIK */
+ #define   S_028040_TILE_SPLIT(x)                                      (((x) & 0x07) << 13)
+ #define   G_028040_TILE_SPLIT(x)                                      (((x) >> 13) & 0x07)
+@@ -5482,6 +6089,14 @@
+ #define     V_028040_ADDR_SURF_TILE_SPLIT_2KB                       0x05
+ #define     V_028040_ADDR_SURF_TILE_SPLIT_4KB                       0x06
+ /*     */
++#define   S_028040_TILE_MODE_INDEX(x)                                 (((x) & 0x07) << 20) /* not on CIK */
++#define   G_028040_TILE_MODE_INDEX(x)                                 (((x) >> 20) & 0x07) /* not on CIK */
++#define   C_028040_TILE_MODE_INDEX                                    0xFF8FFFFF /* not on CIK */
++/* VI */
++#define   S_028040_DECOMPRESS_ON_N_ZPLANES(x)                         (((x) & 0x0F) << 23)
++#define   G_028040_DECOMPRESS_ON_N_ZPLANES(x)                         (((x) >> 23) & 0x0F)
++#define   C_028040_DECOMPRESS_ON_N_ZPLANES                            0xF87FFFFF
++/*    */
+ #define   S_028040_ALLOW_EXPCLEAR(x)                                  (((x) & 0x1) << 27)
+ #define   G_028040_ALLOW_EXPCLEAR(x)                                  (((x) >> 27) & 0x1)
+ #define   C_028040_ALLOW_EXPCLEAR                                     0xF7FFFFFF
+@@ -5491,6 +6106,11 @@
+ #define   S_028040_TILE_SURFACE_ENABLE(x)                             (((x) & 0x1) << 29)
+ #define   G_028040_TILE_SURFACE_ENABLE(x)                             (((x) >> 29) & 0x1)
+ #define   C_028040_TILE_SURFACE_ENABLE                                0xDFFFFFFF
++/* VI */
++#define   S_028040_CLEAR_DISALLOWED(x)                                (((x) & 0x1) << 30)
++#define   G_028040_CLEAR_DISALLOWED(x)                                (((x) >> 30) & 0x1)
++#define   C_028040_CLEAR_DISALLOWED                                   0xBFFFFFFF
++/*    */
+ #define   S_028040_ZRANGE_PRECISION(x)                                (((x) & 0x1) << 31)
+ #define   G_028040_ZRANGE_PRECISION(x)                                (((x) >> 31) & 0x1)
+ #define   C_028040_ZRANGE_PRECISION                                   0x7FFFFFFF
+@@ -5500,9 +6120,6 @@
+ #define   C_028044_FORMAT                                             0xFFFFFFFE
+ #define     V_028044_STENCIL_INVALID                                0x00
+ #define     V_028044_STENCIL_8                                      0x01
+-#define   S_028044_TILE_MODE_INDEX(x)                                 (((x) & 0x07) << 20) /* not on CIK */
+-#define   G_028044_TILE_MODE_INDEX(x)                                 (((x) >> 20) & 0x07) /* not on CIK */
+-#define   C_028044_TILE_MODE_INDEX                                    0xFF8FFFFF /* not on CIK */
+ /* CIK */
+ #define   S_028044_TILE_SPLIT(x)                                      (((x) & 0x07) << 13)
+ #define   G_028044_TILE_SPLIT(x)                                      (((x) >> 13) & 0x07)
+@@ -5515,12 +6132,20 @@
+ #define     V_028044_ADDR_SURF_TILE_SPLIT_2KB                       0x05
+ #define     V_028044_ADDR_SURF_TILE_SPLIT_4KB                       0x06
+ /*     */
++#define   S_028044_TILE_MODE_INDEX(x)                                 (((x) & 0x07) << 20) /* not on CIK */
++#define   G_028044_TILE_MODE_INDEX(x)                                 (((x) >> 20) & 0x07) /* not on CIK */
++#define   C_028044_TILE_MODE_INDEX                                    0xFF8FFFFF /* not on CIK */
+ #define   S_028044_ALLOW_EXPCLEAR(x)                                  (((x) & 0x1) << 27)
+ #define   G_028044_ALLOW_EXPCLEAR(x)                                  (((x) >> 27) & 0x1)
+ #define   C_028044_ALLOW_EXPCLEAR                                     0xF7FFFFFF
+ #define   S_028044_TILE_STENCIL_DISABLE(x)                            (((x) & 0x1) << 29)
+ #define   G_028044_TILE_STENCIL_DISABLE(x)                            (((x) >> 29) & 0x1)
+ #define   C_028044_TILE_STENCIL_DISABLE                               0xDFFFFFFF
++/* VI */
++#define   S_028044_CLEAR_DISALLOWED(x)                                (((x) & 0x1) << 30)
++#define   G_028044_CLEAR_DISALLOWED(x)                                (((x) >> 30) & 0x1)
++#define   C_028044_CLEAR_DISALLOWED                                   0xBFFFFFFF
++/*    */
+ #define R_028048_DB_Z_READ_BASE                                         0x028048
+ #define R_02804C_DB_STENCIL_READ_BASE                                   0x02804C
+ #define R_028050_DB_Z_WRITE_BASE                                        0x028050
+@@ -5542,7 +6167,13 @@
+ #define   S_028084_ADDRESS(x)                                         (((x) & 0xFF) << 0)
+ #define   G_028084_ADDRESS(x)                                         (((x) >> 0) & 0xFF)
+ #define   C_028084_ADDRESS                                            0xFFFFFF00
+-/* */
++#define R_0281E8_COHER_DEST_BASE_HI_0                                   0x0281E8
++#define R_0281EC_COHER_DEST_BASE_HI_1                                   0x0281EC
++#define R_0281F0_COHER_DEST_BASE_HI_2                                   0x0281F0
++#define R_0281F4_COHER_DEST_BASE_HI_3                                   0x0281F4
++/*     */
++#define R_0281F8_COHER_DEST_BASE_2                                      0x0281F8
++#define R_0281FC_COHER_DEST_BASE_3                                      0x0281FC
+ #define R_028200_PA_SC_WINDOW_OFFSET                                    0x028200
+ #define   S_028200_WINDOW_X_OFFSET(x)                                 (((x) & 0xFFFF) << 0)
+ #define   G_028200_WINDOW_X_OFFSET(x)                                 (((x) >> 0) & 0xFFFF)
+@@ -5687,6 +6318,8 @@
+ #define   S_028244_BR_Y(x)                                            (((x) & 0x7FFF) << 16)
+ #define   G_028244_BR_Y(x)                                            (((x) >> 16) & 0x7FFF)
+ #define   C_028244_BR_Y                                               0x8000FFFF
++#define R_028248_COHER_DEST_BASE_0                                      0x028248
++#define R_02824C_COHER_DEST_BASE_1                                      0x02824C
+ #define R_028250_PA_SC_VPORT_SCISSOR_0_TL                               0x028250
+ #define   S_028250_TL_X(x)                                            (((x) & 0x7FFF) << 0)
+ #define   G_028250_TL_X(x)                                            (((x) >> 0) & 0x7FFF)
+@@ -5704,8 +6337,68 @@
+ #define   S_028254_BR_Y(x)                                            (((x) & 0x7FFF) << 16)
+ #define   G_028254_BR_Y(x)                                            (((x) >> 16) & 0x7FFF)
+ #define   C_028254_BR_Y                                               0x8000FFFF
++#define R_028258_PA_SC_VPORT_SCISSOR_1_TL                               0x028258
++#define R_02825C_PA_SC_VPORT_SCISSOR_1_BR                               0x02825C
++#define R_028260_PA_SC_VPORT_SCISSOR_2_TL                               0x028260
++#define R_028264_PA_SC_VPORT_SCISSOR_2_BR                               0x028264
++#define R_028268_PA_SC_VPORT_SCISSOR_3_TL                               0x028268
++#define R_02826C_PA_SC_VPORT_SCISSOR_3_BR                               0x02826C
++#define R_028270_PA_SC_VPORT_SCISSOR_4_TL                               0x028270
++#define R_028274_PA_SC_VPORT_SCISSOR_4_BR                               0x028274
++#define R_028278_PA_SC_VPORT_SCISSOR_5_TL                               0x028278
++#define R_02827C_PA_SC_VPORT_SCISSOR_5_BR                               0x02827C
++#define R_028280_PA_SC_VPORT_SCISSOR_6_TL                               0x028280
++#define R_028284_PA_SC_VPORT_SCISSOR_6_BR                               0x028284
++#define R_028288_PA_SC_VPORT_SCISSOR_7_TL                               0x028288
++#define R_02828C_PA_SC_VPORT_SCISSOR_7_BR                               0x02828C
++#define R_028290_PA_SC_VPORT_SCISSOR_8_TL                               0x028290
++#define R_028294_PA_SC_VPORT_SCISSOR_8_BR                               0x028294
++#define R_028298_PA_SC_VPORT_SCISSOR_9_TL                               0x028298
++#define R_02829C_PA_SC_VPORT_SCISSOR_9_BR                               0x02829C
++#define R_0282A0_PA_SC_VPORT_SCISSOR_10_TL                              0x0282A0
++#define R_0282A4_PA_SC_VPORT_SCISSOR_10_BR                              0x0282A4
++#define R_0282A8_PA_SC_VPORT_SCISSOR_11_TL                              0x0282A8
++#define R_0282AC_PA_SC_VPORT_SCISSOR_11_BR                              0x0282AC
++#define R_0282B0_PA_SC_VPORT_SCISSOR_12_TL                              0x0282B0
++#define R_0282B4_PA_SC_VPORT_SCISSOR_12_BR                              0x0282B4
++#define R_0282B8_PA_SC_VPORT_SCISSOR_13_TL                              0x0282B8
++#define R_0282BC_PA_SC_VPORT_SCISSOR_13_BR                              0x0282BC
++#define R_0282C0_PA_SC_VPORT_SCISSOR_14_TL                              0x0282C0
++#define R_0282C4_PA_SC_VPORT_SCISSOR_14_BR                              0x0282C4
++#define R_0282C8_PA_SC_VPORT_SCISSOR_15_TL                              0x0282C8
++#define R_0282CC_PA_SC_VPORT_SCISSOR_15_BR                              0x0282CC
+ #define R_0282D0_PA_SC_VPORT_ZMIN_0                                     0x0282D0
+ #define R_0282D4_PA_SC_VPORT_ZMAX_0                                     0x0282D4
++#define R_0282D8_PA_SC_VPORT_ZMIN_1                                     0x0282D8
++#define R_0282DC_PA_SC_VPORT_ZMAX_1                                     0x0282DC
++#define R_0282E0_PA_SC_VPORT_ZMIN_2                                     0x0282E0
++#define R_0282E4_PA_SC_VPORT_ZMAX_2                                     0x0282E4
++#define R_0282E8_PA_SC_VPORT_ZMIN_3                                     0x0282E8
++#define R_0282EC_PA_SC_VPORT_ZMAX_3                                     0x0282EC
++#define R_0282F0_PA_SC_VPORT_ZMIN_4                                     0x0282F0
++#define R_0282F4_PA_SC_VPORT_ZMAX_4                                     0x0282F4
++#define R_0282F8_PA_SC_VPORT_ZMIN_5                                     0x0282F8
++#define R_0282FC_PA_SC_VPORT_ZMAX_5                                     0x0282FC
++#define R_028300_PA_SC_VPORT_ZMIN_6                                     0x028300
++#define R_028304_PA_SC_VPORT_ZMAX_6                                     0x028304
++#define R_028308_PA_SC_VPORT_ZMIN_7                                     0x028308
++#define R_02830C_PA_SC_VPORT_ZMAX_7                                     0x02830C
++#define R_028310_PA_SC_VPORT_ZMIN_8                                     0x028310
++#define R_028314_PA_SC_VPORT_ZMAX_8                                     0x028314
++#define R_028318_PA_SC_VPORT_ZMIN_9                                     0x028318
++#define R_02831C_PA_SC_VPORT_ZMAX_9                                     0x02831C
++#define R_028320_PA_SC_VPORT_ZMIN_10                                    0x028320
++#define R_028324_PA_SC_VPORT_ZMAX_10                                    0x028324
++#define R_028328_PA_SC_VPORT_ZMIN_11                                    0x028328
++#define R_02832C_PA_SC_VPORT_ZMAX_11                                    0x02832C
++#define R_028330_PA_SC_VPORT_ZMIN_12                                    0x028330
++#define R_028334_PA_SC_VPORT_ZMAX_12                                    0x028334
++#define R_028338_PA_SC_VPORT_ZMIN_13                                    0x028338
++#define R_02833C_PA_SC_VPORT_ZMAX_13                                    0x02833C
++#define R_028340_PA_SC_VPORT_ZMIN_14                                    0x028340
++#define R_028344_PA_SC_VPORT_ZMAX_14                                    0x028344
++#define R_028348_PA_SC_VPORT_ZMIN_15                                    0x028348
++#define R_02834C_PA_SC_VPORT_ZMAX_15                                    0x02834C
+ #define R_028350_PA_SC_RASTER_CONFIG                                    0x028350
+ #define   S_028350_RB_MAP_PKR0(x)                                     (((x) & 0x03) << 0)
+ #define   G_028350_RB_MAP_PKR0(x)                                     (((x) >> 0) & 0x03)
+@@ -5827,6 +6520,13 @@
+ #define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE        0x01
+ #define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE        0x02
+ #define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE        0x03
++#define R_028358_PA_SC_SCREEN_EXTENT_CONTROL                            0x028358
++#define   S_028358_SLICE_EVEN_ENABLE(x)                               (((x) & 0x03) << 0)
++#define   G_028358_SLICE_EVEN_ENABLE(x)                               (((x) >> 0) & 0x03)
++#define   C_028358_SLICE_EVEN_ENABLE                                  0xFFFFFFFC
++#define   S_028358_SLICE_ODD_ENABLE(x)                                (((x) & 0x03) << 2)
++#define   G_028358_SLICE_ODD_ENABLE(x)                                (((x) >> 2) & 0x03)
++#define   C_028358_SLICE_ODD_ENABLE                                   0xFFFFFFF3
+ /*     */
+ #define R_028400_VGT_MAX_VTX_INDX                                       0x028400
+ #define R_028404_VGT_MIN_VTX_INDX                                       0x028404
+@@ -5836,6 +6536,18 @@
+ #define R_028418_CB_BLEND_GREEN                                         0x028418
+ #define R_02841C_CB_BLEND_BLUE                                          0x02841C
+ #define R_028420_CB_BLEND_ALPHA                                         0x028420
++/* VI */
++#define R_028424_CB_DCC_CONTROL                                         0x028424
++#define   S_028424_OVERWRITE_COMBINER_DISABLE(x)                      (((x) & 0x1) << 0)
++#define   G_028424_OVERWRITE_COMBINER_DISABLE(x)                      (((x) >> 0) & 0x1)
++#define   C_028424_OVERWRITE_COMBINER_DISABLE                         0xFFFFFFFE
++#define   S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(x)          (((x) & 0x1) << 1)
++#define   G_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(x)          (((x) >> 1) & 0x1)
++#define   C_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE             0xFFFFFFFD
++#define   S_028424_OVERWRITE_COMBINER_WATERMARK(x)                    (((x) & 0x1F) << 2)
++#define   G_028424_OVERWRITE_COMBINER_WATERMARK(x)                    (((x) >> 2) & 0x1F)
++#define   C_028424_OVERWRITE_COMBINER_WATERMARK                       0xFFFFFF83
++/*    */
+ #define R_02842C_DB_STENCIL_CONTROL                                     0x02842C
+ #define   S_02842C_STENCILFAIL(x)                                     (((x) & 0x0F) << 0)
+ #define   G_02842C_STENCILFAIL(x)                                     (((x) >> 0) & 0x0F)
+@@ -5977,12 +6689,102 @@
+ #define   S_028434_STENCILOPVAL_BF(x)                                 (((x) & 0xFF) << 24)
+ #define   G_028434_STENCILOPVAL_BF(x)                                 (((x) >> 24) & 0xFF)
+ #define   C_028434_STENCILOPVAL_BF                                    0x00FFFFFF
+-#define R_02843C_PA_CL_VPORT_XSCALE_0                                   0x02843C
+-#define R_028440_PA_CL_VPORT_XOFFSET_0                                  0x028440
+-#define R_028444_PA_CL_VPORT_YSCALE_0                                   0x028444
+-#define R_028448_PA_CL_VPORT_YOFFSET_0                                  0x028448
+-#define R_02844C_PA_CL_VPORT_ZSCALE_0                                   0x02844C
+-#define R_028450_PA_CL_VPORT_ZOFFSET_0                                  0x028450
++#define R_02843C_PA_CL_VPORT_XSCALE                                     0x02843C
++#define R_028440_PA_CL_VPORT_XOFFSET                                    0x028440
++#define R_028444_PA_CL_VPORT_YSCALE                                     0x028444
++#define R_028448_PA_CL_VPORT_YOFFSET                                    0x028448
++#define R_02844C_PA_CL_VPORT_ZSCALE                                     0x02844C
++#define R_028450_PA_CL_VPORT_ZOFFSET                                    0x028450
++#define R_028454_PA_CL_VPORT_XSCALE_1                                   0x028454
++#define R_028458_PA_CL_VPORT_XOFFSET_1                                  0x028458
++#define R_02845C_PA_CL_VPORT_YSCALE_1                                   0x02845C
++#define R_028460_PA_CL_VPORT_YOFFSET_1                                  0x028460
++#define R_028464_PA_CL_VPORT_ZSCALE_1                                   0x028464
++#define R_028468_PA_CL_VPORT_ZOFFSET_1                                  0x028468
++#define R_02846C_PA_CL_VPORT_XSCALE_2                                   0x02846C
++#define R_028470_PA_CL_VPORT_XOFFSET_2                                  0x028470
++#define R_028474_PA_CL_VPORT_YSCALE_2                                   0x028474
++#define R_028478_PA_CL_VPORT_YOFFSET_2                                  0x028478
++#define R_02847C_PA_CL_VPORT_ZSCALE_2                                   0x02847C
++#define R_028480_PA_CL_VPORT_ZOFFSET_2                                  0x028480
++#define R_028484_PA_CL_VPORT_XSCALE_3                                   0x028484
++#define R_028488_PA_CL_VPORT_XOFFSET_3                                  0x028488
++#define R_02848C_PA_CL_VPORT_YSCALE_3                                   0x02848C
++#define R_028490_PA_CL_VPORT_YOFFSET_3                                  0x028490
++#define R_028494_PA_CL_VPORT_ZSCALE_3                                   0x028494
++#define R_028498_PA_CL_VPORT_ZOFFSET_3                                  0x028498
++#define R_02849C_PA_CL_VPORT_XSCALE_4                                   0x02849C
++#define R_0284A0_PA_CL_VPORT_XOFFSET_4                                  0x0284A0
++#define R_0284A4_PA_CL_VPORT_YSCALE_4                                   0x0284A4
++#define R_0284A8_PA_CL_VPORT_YOFFSET_4                                  0x0284A8
++#define R_0284AC_PA_CL_VPORT_ZSCALE_4                                   0x0284AC
++#define R_0284B0_PA_CL_VPORT_ZOFFSET_4                                  0x0284B0
++#define R_0284B4_PA_CL_VPORT_XSCALE_5                                   0x0284B4
++#define R_0284B8_PA_CL_VPORT_XOFFSET_5                                  0x0284B8
++#define R_0284BC_PA_CL_VPORT_YSCALE_5                                   0x0284BC
++#define R_0284C0_PA_CL_VPORT_YOFFSET_5                                  0x0284C0
++#define R_0284C4_PA_CL_VPORT_ZSCALE_5                                   0x0284C4
++#define R_0284C8_PA_CL_VPORT_ZOFFSET_5                                  0x0284C8
++#define R_0284CC_PA_CL_VPORT_XSCALE_6                                   0x0284CC
++#define R_0284D0_PA_CL_VPORT_XOFFSET_6                                  0x0284D0
++#define R_0284D4_PA_CL_VPORT_YSCALE_6                                   0x0284D4
++#define R_0284D8_PA_CL_VPORT_YOFFSET_6                                  0x0284D8
++#define R_0284DC_PA_CL_VPORT_ZSCALE_6                                   0x0284DC
++#define R_0284E0_PA_CL_VPORT_ZOFFSET_6                                  0x0284E0
++#define R_0284E4_PA_CL_VPORT_XSCALE_7                                   0x0284E4
++#define R_0284E8_PA_CL_VPORT_XOFFSET_7                                  0x0284E8
++#define R_0284EC_PA_CL_VPORT_YSCALE_7                                   0x0284EC
++#define R_0284F0_PA_CL_VPORT_YOFFSET_7                                  0x0284F0
++#define R_0284F4_PA_CL_VPORT_ZSCALE_7                                   0x0284F4
++#define R_0284F8_PA_CL_VPORT_ZOFFSET_7                                  0x0284F8
++#define R_0284FC_PA_CL_VPORT_XSCALE_8                                   0x0284FC
++#define R_028500_PA_CL_VPORT_XOFFSET_8                                  0x028500
++#define R_028504_PA_CL_VPORT_YSCALE_8                                   0x028504
++#define R_028508_PA_CL_VPORT_YOFFSET_8                                  0x028508
++#define R_02850C_PA_CL_VPORT_ZSCALE_8                                   0x02850C
++#define R_028510_PA_CL_VPORT_ZOFFSET_8                                  0x028510
++#define R_028514_PA_CL_VPORT_XSCALE_9                                   0x028514
++#define R_028518_PA_CL_VPORT_XOFFSET_9                                  0x028518
++#define R_02851C_PA_CL_VPORT_YSCALE_9                                   0x02851C
++#define R_028520_PA_CL_VPORT_YOFFSET_9                                  0x028520
++#define R_028524_PA_CL_VPORT_ZSCALE_9                                   0x028524
++#define R_028528_PA_CL_VPORT_ZOFFSET_9                                  0x028528
++#define R_02852C_PA_CL_VPORT_XSCALE_10                                  0x02852C
++#define R_028530_PA_CL_VPORT_XOFFSET_10                                 0x028530
++#define R_028534_PA_CL_VPORT_YSCALE_10                                  0x028534
++#define R_028538_PA_CL_VPORT_YOFFSET_10                                 0x028538
++#define R_02853C_PA_CL_VPORT_ZSCALE_10                                  0x02853C
++#define R_028540_PA_CL_VPORT_ZOFFSET_10                                 0x028540
++#define R_028544_PA_CL_VPORT_XSCALE_11                                  0x028544
++#define R_028548_PA_CL_VPORT_XOFFSET_11                                 0x028548
++#define R_02854C_PA_CL_VPORT_YSCALE_11                                  0x02854C
++#define R_028550_PA_CL_VPORT_YOFFSET_11                                 0x028550
++#define R_028554_PA_CL_VPORT_ZSCALE_11                                  0x028554
++#define R_028558_PA_CL_VPORT_ZOFFSET_11                                 0x028558
++#define R_02855C_PA_CL_VPORT_XSCALE_12                                  0x02855C
++#define R_028560_PA_CL_VPORT_XOFFSET_12                                 0x028560
++#define R_028564_PA_CL_VPORT_YSCALE_12                                  0x028564
++#define R_028568_PA_CL_VPORT_YOFFSET_12                                 0x028568
++#define R_02856C_PA_CL_VPORT_ZSCALE_12                                  0x02856C
++#define R_028570_PA_CL_VPORT_ZOFFSET_12                                 0x028570
++#define R_028574_PA_CL_VPORT_XSCALE_13                                  0x028574
++#define R_028578_PA_CL_VPORT_XOFFSET_13                                 0x028578
++#define R_02857C_PA_CL_VPORT_YSCALE_13                                  0x02857C
++#define R_028580_PA_CL_VPORT_YOFFSET_13                                 0x028580
++#define R_028584_PA_CL_VPORT_ZSCALE_13                                  0x028584
++#define R_028588_PA_CL_VPORT_ZOFFSET_13                                 0x028588
++#define R_02858C_PA_CL_VPORT_XSCALE_14                                  0x02858C
++#define R_028590_PA_CL_VPORT_XOFFSET_14                                 0x028590
++#define R_028594_PA_CL_VPORT_YSCALE_14                                  0x028594
++#define R_028598_PA_CL_VPORT_YOFFSET_14                                 0x028598
++#define R_02859C_PA_CL_VPORT_ZSCALE_14                                  0x02859C
++#define R_0285A0_PA_CL_VPORT_ZOFFSET_14                                 0x0285A0
++#define R_0285A4_PA_CL_VPORT_XSCALE_15                                  0x0285A4
++#define R_0285A8_PA_CL_VPORT_XOFFSET_15                                 0x0285A8
++#define R_0285AC_PA_CL_VPORT_YSCALE_15                                  0x0285AC
++#define R_0285B0_PA_CL_VPORT_YOFFSET_15                                 0x0285B0
++#define R_0285B4_PA_CL_VPORT_ZSCALE_15                                  0x0285B4
++#define R_0285B8_PA_CL_VPORT_ZOFFSET_15                                 0x0285B8
+ #define R_0285BC_PA_CL_UCP_0_X                                          0x0285BC
+ #define R_0285C0_PA_CL_UCP_0_Y                                          0x0285C0
+ #define R_0285C4_PA_CL_UCP_0_Z                                          0x0285C4
+@@ -6029,6 +6831,26 @@
+ #define   G_028644_DUP(x)                                             (((x) >> 18) & 0x1)
+ #define   C_028644_DUP                                                0xFFFBFFFF
+ /*     */
++/* VI */
++#define   S_028644_FP16_INTERP_MODE(x)                                (((x) & 0x1) << 19)
++#define   G_028644_FP16_INTERP_MODE(x)                                (((x) >> 19) & 0x1)
++#define   C_028644_FP16_INTERP_MODE                                   0xFFF7FFFF
++#define   S_028644_USE_DEFAULT_ATTR1(x)                               (((x) & 0x1) << 20)
++#define   G_028644_USE_DEFAULT_ATTR1(x)                               (((x) >> 20) & 0x1)
++#define   C_028644_USE_DEFAULT_ATTR1                                  0xFFEFFFFF
++#define   S_028644_DEFAULT_VAL_ATTR1(x)                               (((x) & 0x03) << 21)
++#define   G_028644_DEFAULT_VAL_ATTR1(x)                               (((x) >> 21) & 0x03)
++#define   C_028644_DEFAULT_VAL_ATTR1                                  0xFF9FFFFF
++#define   S_028644_PT_SPRITE_TEX_ATTR1(x)                             (((x) & 0x1) << 23)
++#define   G_028644_PT_SPRITE_TEX_ATTR1(x)                             (((x) >> 23) & 0x1)
++#define   C_028644_PT_SPRITE_TEX_ATTR1                                0xFF7FFFFF
++#define   S_028644_ATTR0_VALID(x)                                     (((x) & 0x1) << 24)
++#define   G_028644_ATTR0_VALID(x)                                     (((x) >> 24) & 0x1)
++#define   C_028644_ATTR0_VALID                                        0xFEFFFFFF
++#define   S_028644_ATTR1_VALID(x)                                     (((x) & 0x1) << 25)
++#define   G_028644_ATTR1_VALID(x)                                     (((x) >> 25) & 0x1)
++#define   C_028644_ATTR1_VALID                                        0xFDFFFFFF
++/*    */
+ #define R_028648_SPI_PS_INPUT_CNTL_1                                    0x028648
+ #define R_02864C_SPI_PS_INPUT_CNTL_2                                    0x02864C
+ #define R_028650_SPI_PS_INPUT_CNTL_3                                    0x028650
+@@ -6552,6 +7374,10 @@
+ #define R_028794_CB_BLEND5_CONTROL                                      0x028794
+ #define R_028798_CB_BLEND6_CONTROL                                      0x028798
+ #define R_02879C_CB_BLEND7_CONTROL                                      0x02879C
++#define R_0287CC_CS_COPY_STATE                                          0x0287CC
++#define   S_0287CC_SRC_STATE_ID(x)                                    (((x) & 0x07) << 0)
++#define   G_0287CC_SRC_STATE_ID(x)                                    (((x) >> 0) & 0x07)
++#define   C_0287CC_SRC_STATE_ID                                       0xFFFFFFF8
+ #define R_0287D4_PA_CL_POINT_X_RAD                                      0x0287D4
+ #define R_0287D8_PA_CL_POINT_Y_RAD                                      0x0287D8
+ #define R_0287DC_PA_CL_POINT_SIZE                                       0x0287DC
+@@ -6581,6 +7407,10 @@
+ #define   G_0287F0_USE_OPAQUE(x)                                      (((x) >> 6) & 0x1)
+ #define   C_0287F0_USE_OPAQUE                                         0xFFFFFFBF
+ #define R_0287F4_VGT_IMMED_DATA                                         0x0287F4 /* not on CIK */
++#define R_0287F8_VGT_EVENT_ADDRESS_REG                                  0x0287F8
++#define   S_0287F8_ADDRESS_LOW(x)                                     (((x) & 0xFFFFFFF) << 0)
++#define   G_0287F8_ADDRESS_LOW(x)                                     (((x) >> 0) & 0xFFFFFFF)
++#define   C_0287F8_ADDRESS_LOW                                        0xF0000000
+ #define R_028800_DB_DEPTH_CONTROL                                       0x028800
+ #define   S_028800_STENCIL_ENABLE(x)                                  (((x) & 0x1) << 0)
+ #define   G_028800_STENCIL_ENABLE(x)                                  (((x) >> 0) & 0x1)
+@@ -6637,36 +7467,42 @@
+ #define   G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x)              (((x) >> 31) & 0x1)
+ #define   C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS                 0x7FFFFFFF
+ #define R_028804_DB_EQAA                                                0x028804
+-#define   S_028804_MAX_ANCHOR_SAMPLES(x)		(((x) & 0x7) << 0)
+-#define   G_028804_MAX_ANCHOR_SAMPLES(x)		(((x) >> 0) & 0x7)
+-#define   C_028804_MAX_ANCHOR_SAMPLES			(~(((~0) & 0x7) << 0))
+-#define   S_028804_PS_ITER_SAMPLES(x)			(((x) & 0x7) << 4)
+-#define   G_028804_PS_ITER_SAMPLES(x)			(((x) >> 4) & 0x7)
+-#define   C_028804_PS_ITER_SAMPLES			(~(((~0) & 0x7) << 4))
+-#define   S_028804_MASK_EXPORT_NUM_SAMPLES(x)		(((x) & 0x7) << 8)
+-#define   G_028804_MASK_EXPORT_NUM_SAMPLES(x)		(((x) >> 8) & 0x7)
+-#define   C_028804_MASK_EXPORT_NUM_SAMPLES		(~(((~0) & 0x7) << 8))
+-#define   S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x)		(((x) & 0x7) << 12)
+-#define   G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x)		(((x) >> 12) & 0x7)
+-#define   C_028804_ALPHA_TO_MASK_NUM_SAMPLES		(~(((~0) & 0x7) << 12))
+-#define   S_028804_HIGH_QUALITY_INTERSECTIONS(x)	(((x) & 0x1) << 16)
+-#define   G_028804_HIGH_QUALITY_INTERSECTIONS(x)	(((x) >> 16) & 0x1)
+-#define   C_028804_HIGH_QUALITY_INTERSECTIONS		(~(((~0) & 0x1) << 16))
+-#define   S_028804_INCOHERENT_EQAA_READS(x)		(((x) & 0x1) << 17)
+-#define   G_028804_INCOHERENT_EQAA_READS(x)		(((x) >> 17) & 0x1)
+-#define   C_028804_INCOHERENT_EQAA_READS		(~(((~0) & 0x1) << 17))
+-#define   S_028804_INTERPOLATE_COMP_Z(x)		(((x) & 0x1) << 18)
+-#define   G_028804_INTERPOLATE_COMP_Z(x)		(((x) >> 18) & 0x1)
+-#define   C_028804_INTERPOLATE_COMP_Z			(~(((~0) >> 18) & 0x1))
+-#define   S_028804_INTERPOLATE_SRC_Z(x)			(((x) & 0x1) << 19)
+-#define   G_028804_INTERPOLATE_SRC_Z(x)			(((x) >> 19) & 0x1)
+-#define   C_028804_INTERPOLATE_SRC_Z			(~(((~0) & 0x1) << 19))
+-#define   S_028804_STATIC_ANCHOR_ASSOCIATIONS(x)	(((x) & 0x1) << 20)
+-#define   G_028804_STATIC_ANCHOR_ASSOCIATIONS(x)	(((x) >> 20) & 0x1)
+-#define   C_028804_STATIC_ANCHOR_ASSOCIATIONS		(~(((~0) & 0x1) << 20))
+-#define   S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)	(((x) & 0x1) << 21)
+-#define   G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)	(((x) >> 21) & 0x1)
+-#define   C_028804_ALPHA_TO_MASK_EQAA_DISABLE		(~(((~0) & 0x1) << 21))
++#define   S_028804_MAX_ANCHOR_SAMPLES(x)                              (((x) & 0x7) << 0)
++#define   G_028804_MAX_ANCHOR_SAMPLES(x)                              (((x) >> 0) & 0x07)
++#define   C_028804_MAX_ANCHOR_SAMPLES                                 0xFFFFFFF8
++#define   S_028804_PS_ITER_SAMPLES(x)                                 (((x) & 0x7) << 4)
++#define   G_028804_PS_ITER_SAMPLES(x)                                 (((x) >> 4) & 0x07)
++#define   C_028804_PS_ITER_SAMPLES                                    0xFFFFFF8F
++#define   S_028804_MASK_EXPORT_NUM_SAMPLES(x)                         (((x) & 0x7) << 8)
++#define   G_028804_MASK_EXPORT_NUM_SAMPLES(x)                         (((x) >> 8) & 0x07)
++#define   C_028804_MASK_EXPORT_NUM_SAMPLES                            0xFFFFF8FF
++#define   S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x)                       (((x) & 0x7) << 12)
++#define   G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x)                       (((x) >> 12) & 0x07)
++#define   C_028804_ALPHA_TO_MASK_NUM_SAMPLES                          0xFFFF8FFF
++#define   S_028804_HIGH_QUALITY_INTERSECTIONS(x)                      (((x) & 0x1) << 16)
++#define   G_028804_HIGH_QUALITY_INTERSECTIONS(x)                      (((x) >> 16) & 0x1)
++#define   C_028804_HIGH_QUALITY_INTERSECTIONS                         0xFFFEFFFF
++#define   S_028804_INCOHERENT_EQAA_READS(x)                           (((x) & 0x1) << 17)
++#define   G_028804_INCOHERENT_EQAA_READS(x)                           (((x) >> 17) & 0x1)
++#define   C_028804_INCOHERENT_EQAA_READS                              0xFFFDFFFF
++#define   S_028804_INTERPOLATE_COMP_Z(x)                              (((x) & 0x1) << 18)
++#define   G_028804_INTERPOLATE_COMP_Z(x)                              (((x) >> 18) & 0x1)
++#define   C_028804_INTERPOLATE_COMP_Z                                 0xFFFBFFFF
++#define   S_028804_INTERPOLATE_SRC_Z(x)                               (((x) & 0x1) << 19)
++#define   G_028804_INTERPOLATE_SRC_Z(x)                               (((x) >> 19) & 0x1)
++#define   C_028804_INTERPOLATE_SRC_Z                                  0xFFF7FFFF
++#define   S_028804_STATIC_ANCHOR_ASSOCIATIONS(x)                      (((x) & 0x1) << 20)
++#define   G_028804_STATIC_ANCHOR_ASSOCIATIONS(x)                      (((x) >> 20) & 0x1)
++#define   C_028804_STATIC_ANCHOR_ASSOCIATIONS                         0xFFEFFFFF
++#define   S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)                      (((x) & 0x1) << 21)
++#define   G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)                      (((x) >> 21) & 0x1)
++#define   C_028804_ALPHA_TO_MASK_EQAA_DISABLE                         0xFFDFFFFF
++#define   S_028804_OVERRASTERIZATION_AMOUNT(x)                        (((x) & 0x07) << 24)
++#define   G_028804_OVERRASTERIZATION_AMOUNT(x)                        (((x) >> 24) & 0x07)
++#define   C_028804_OVERRASTERIZATION_AMOUNT                           0xF8FFFFFF
++#define   S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x)                  (((x) & 0x1) << 27)
++#define   G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x)                  (((x) >> 27) & 0x1)
++#define   C_028804_ENABLE_POSTZ_OVERRASTERIZATION                     0xF7FFFFFF
+ #define R_028808_CB_COLOR_CONTROL                                       0x028808
+ #define   S_028808_DEGAMMA_ENABLE(x)                                  (((x) & 0x1) << 3)
+ #define   G_028808_DEGAMMA_ENABLE(x)                                  (((x) >> 3) & 0x1)
+@@ -6970,6 +7806,11 @@
+ #define   S_02881C_USE_VTX_GS_CUT_FLAG(x)                             (((x) & 0x1) << 25)
+ #define   G_02881C_USE_VTX_GS_CUT_FLAG(x)                             (((x) >> 25) & 0x1)
+ #define   C_02881C_USE_VTX_GS_CUT_FLAG                                0xFDFFFFFF
++/* VI */
++#define   S_02881C_USE_VTX_LINE_WIDTH(x)                              (((x) & 0x1) << 26)
++#define   G_02881C_USE_VTX_LINE_WIDTH(x)                              (((x) >> 26) & 0x1)
++#define   C_02881C_USE_VTX_LINE_WIDTH                                 0xFBFFFFFF
++/*    */
+ #define R_028820_PA_CL_NANINF_CNTL                                      0x028820
+ #define   S_028820_VTE_XY_INF_DISCARD(x)                              (((x) & 0x1) << 0)
+ #define   G_028820_VTE_XY_INF_DISCARD(x)                              (((x) >> 0) & 0x1)
+@@ -7440,9 +8281,21 @@
+ #define   S_028A4C_PS_ITER_SAMPLE(x)                                  (((x) & 0x1) << 16)
+ #define   G_028A4C_PS_ITER_SAMPLE(x)                                  (((x) >> 16) & 0x1)
+ #define   C_028A4C_PS_ITER_SAMPLE                                     0xFFFEFFFF
+-#define   S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x)                   (((x) & 0x1) << 17)
+-#define   G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x)                   (((x) >> 17) & 0x1)
+-#define   C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC                      0xFFFDFFFF
++#define   S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(x)         (((x) & 0x1) << 17)
++#define   G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(x)         (((x) >> 17) & 0x1)
++#define   C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE            0xFFFDFFFF
++#define   S_028A4C_MULTI_GPU_SUPERTILE_ENABLE(x)                      (((x) & 0x1) << 18)
++#define   G_028A4C_MULTI_GPU_SUPERTILE_ENABLE(x)                      (((x) >> 18) & 0x1)
++#define   C_028A4C_MULTI_GPU_SUPERTILE_ENABLE                         0xFFFBFFFF
++#define   S_028A4C_GPU_ID_OVERRIDE_ENABLE(x)                          (((x) & 0x1) << 19)
++#define   G_028A4C_GPU_ID_OVERRIDE_ENABLE(x)                          (((x) >> 19) & 0x1)
++#define   C_028A4C_GPU_ID_OVERRIDE_ENABLE                             0xFFF7FFFF
++#define   S_028A4C_GPU_ID_OVERRIDE(x)                                 (((x) & 0x0F) << 20)
++#define   G_028A4C_GPU_ID_OVERRIDE(x)                                 (((x) >> 20) & 0x0F)
++#define   C_028A4C_GPU_ID_OVERRIDE                                    0xFF0FFFFF
++#define   S_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE(x)                   (((x) & 0x1) << 24)
++#define   G_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE(x)                   (((x) >> 24) & 0x1)
++#define   C_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE                      0xFEFFFFFF
+ #define   S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)                         (((x) & 0x1) << 25)
+ #define   G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)                         (((x) >> 25) & 0x1)
+ #define   C_028A4C_FORCE_EOV_CNTDWN_ENABLE                            0xFDFFFFFF
+@@ -7508,6 +8361,7 @@
+ #define   C_028A7C_INDEX_TYPE                                         0xFFFFFFFC
+ #define     V_028A7C_VGT_INDEX_16                                   0x00
+ #define     V_028A7C_VGT_INDEX_32                                   0x01
++#define     V_028A7C_VGT_INDEX_8                                    0x02 /* VI */
+ #define   S_028A7C_SWAP_MODE(x)                                       (((x) & 0x03) << 2)
+ #define   G_028A7C_SWAP_MODE(x)                                       (((x) >> 2) & 0x03)
+ #define   C_028A7C_SWAP_MODE                                          0xFFFFFFF3
+@@ -7537,6 +8391,12 @@
+ #define   G_028A7C_REQ_PATH(x)                                        (((x) >> 10) & 0x1)
+ #define   C_028A7C_REQ_PATH                                           0xFFFFFBFF
+ /*     */
++/* VI */
++#define   S_028A7C_MTYPE(x)                                           (((x) & 0x03) << 11)
++#define   G_028A7C_MTYPE(x)                                           (((x) >> 11) & 0x03)
++#define   C_028A7C_MTYPE                                              0xFFFFE7FF
++/*    */
++#define R_028A80_WD_ENHANCE                                             0x028A80
+ #define R_028A84_VGT_PRIMITIVEID_EN                                     0x028A84
+ #define   S_028A84_PRIMITIVEID_EN(x)                                  (((x) & 0x1) << 0)
+ #define   G_028A84_PRIMITIVEID_EN(x)                                  (((x) >> 0) & 0x1)
+@@ -7635,6 +8495,10 @@
+ #define   S_028AA8_WD_SWITCH_ON_EOP(x)                                (((x) & 0x1) << 20)
+ #define   G_028AA8_WD_SWITCH_ON_EOP(x)                                (((x) >> 20) & 0x1)
+ #define   C_028AA8_WD_SWITCH_ON_EOP                                   0xFFEFFFFF
++/* VI */
++#define   S_028AA8_MAX_PRIMGRP_IN_WAVE(x)                             (((x) & 0x0F) << 28)
++#define   G_028AA8_MAX_PRIMGRP_IN_WAVE(x)                             (((x) >> 28) & 0x0F)
++#define   C_028AA8_MAX_PRIMGRP_IN_WAVE                                0x0FFFFFFF
+ /*     */
+ #define R_028AAC_VGT_ESGS_RING_ITEMSIZE                                 0x028AAC
+ #define   S_028AAC_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+@@ -7674,6 +8538,11 @@
+ #define   S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x)                         (((x) & 0x1) << 16)
+ #define   G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x)                         (((x) >> 16) & 0x1)
+ #define   C_028ABC_DST_OUTSIDE_ZERO_TO_ONE                            0xFFFEFFFF
++/* VI */
++#define   S_028ABC_TC_COMPATIBLE(x)                                   (((x) & 0x1) << 17)
++#define   G_028ABC_TC_COMPATIBLE(x)                                   (((x) >> 17) & 0x1)
++#define   C_028ABC_TC_COMPATIBLE                                      0xFFFDFFFF
++/*    */
+ #define R_028AC0_DB_SRESULTS_COMPARE_STATE0                             0x028AC0
+ #define   S_028AC0_COMPAREFUNC0(x)                                    (((x) & 0x07) << 0)
+ #define   G_028AC0_COMPAREFUNC0(x)                                    (((x) >> 0) & 0x07)
+@@ -7763,6 +8632,21 @@
+ #define   S_028B38_MAX_VERT_OUT(x)                                    (((x) & 0x7FF) << 0)
+ #define   G_028B38_MAX_VERT_OUT(x)                                    (((x) >> 0) & 0x7FF)
+ #define   C_028B38_MAX_VERT_OUT                                       0xFFFFF800
++/* VI */
++#define R_028B50_VGT_TESS_DISTRIBUTION                                  0x028B50
++#define   S_028B50_ACCUM_ISOLINE(x)                                   (((x) & 0xFF) << 0)
++#define   G_028B50_ACCUM_ISOLINE(x)                                   (((x) >> 0) & 0xFF)
++#define   C_028B50_ACCUM_ISOLINE                                      0xFFFFFF00
++#define   S_028B50_ACCUM_TRI(x)                                       (((x) & 0xFF) << 8)
++#define   G_028B50_ACCUM_TRI(x)                                       (((x) >> 8) & 0xFF)
++#define   C_028B50_ACCUM_TRI                                          0xFFFF00FF
++#define   S_028B50_ACCUM_QUAD(x)                                      (((x) & 0xFF) << 16)
++#define   G_028B50_ACCUM_QUAD(x)                                      (((x) >> 16) & 0xFF)
++#define   C_028B50_ACCUM_QUAD                                         0xFF00FFFF
++#define   S_028B50_DONUT_SPLIT(x)                                     (((x) & 0xFF) << 24)
++#define   G_028B50_DONUT_SPLIT(x)                                     (((x) >> 24) & 0xFF)
++#define   C_028B50_DONUT_SPLIT                                        0x00FFFFFF
++/*    */
+ #define R_028B54_VGT_SHADER_STAGES_EN                                   0x028B54
+ #define   S_028B54_LS_EN(x)                                           (((x) & 0x03) << 0)
+ #define   G_028B54_LS_EN(x)                                           (((x) >> 0) & 0x03)
+@@ -7791,6 +8675,20 @@
+ #define   S_028B54_DYNAMIC_HS(x)                                      (((x) & 0x1) << 8)
+ #define   G_028B54_DYNAMIC_HS(x)                                      (((x) >> 8) & 0x1)
+ #define   C_028B54_DYNAMIC_HS                                         0xFFFFFEFF
++/* VI */
++#define   S_028B54_DISPATCH_DRAW_EN(x)                                (((x) & 0x1) << 9)
++#define   G_028B54_DISPATCH_DRAW_EN(x)                                (((x) >> 9) & 0x1)
++#define   C_028B54_DISPATCH_DRAW_EN                                   0xFFFFFDFF
++#define   S_028B54_DIS_DEALLOC_ACCUM_0(x)                             (((x) & 0x1) << 10)
++#define   G_028B54_DIS_DEALLOC_ACCUM_0(x)                             (((x) >> 10) & 0x1)
++#define   C_028B54_DIS_DEALLOC_ACCUM_0                                0xFFFFFBFF
++#define   S_028B54_DIS_DEALLOC_ACCUM_1(x)                             (((x) & 0x1) << 11)
++#define   G_028B54_DIS_DEALLOC_ACCUM_1(x)                             (((x) >> 11) & 0x1)
++#define   C_028B54_DIS_DEALLOC_ACCUM_1                                0xFFFFF7FF
++#define   S_028B54_VS_WAVE_ID_EN(x)                                   (((x) & 0x1) << 12)
++#define   G_028B54_VS_WAVE_ID_EN(x)                                   (((x) >> 12) & 0x1)
++#define   C_028B54_VS_WAVE_ID_EN                                      0xFFFFEFFF
++/*    */
+ #define R_028B58_VGT_LS_HS_CONFIG                                       0x028B58
+ #define   S_028B58_NUM_PATCHES(x)                                     (((x) & 0xFF) << 0)
+ #define   G_028B58_NUM_PATCHES(x)                                     (((x) >> 0) & 0xFF)
+@@ -7841,6 +8739,9 @@
+ #define   S_028B6C_RESERVED_REDUC_AXIS(x)                             (((x) & 0x1) << 8) /* not on CIK */
+ #define   G_028B6C_RESERVED_REDUC_AXIS(x)                             (((x) >> 8) & 0x1) /* not on CIK */
+ #define   C_028B6C_RESERVED_REDUC_AXIS                                0xFFFFFEFF /* not on CIK */
++#define   S_028B6C_DEPRECATED(x)                                      (((x) & 0x1) << 9)
++#define   G_028B6C_DEPRECATED(x)                                      (((x) >> 9) & 0x1)
++#define   C_028B6C_DEPRECATED                                         0xFFFFFDFF
+ #define   S_028B6C_NUM_DS_WAVES_PER_SIMD(x)                           (((x) & 0x0F) << 10)
+ #define   G_028B6C_NUM_DS_WAVES_PER_SIMD(x)                           (((x) >> 10) & 0x0F)
+ #define   C_028B6C_NUM_DS_WAVES_PER_SIMD                              0xFFFFC3FF
+@@ -7855,6 +8756,14 @@
+ #define     V_028B6C_VGT_POLICY_STREAM                              0x01
+ #define     V_028B6C_VGT_POLICY_BYPASS                              0x02
+ /*     */
++/* VI */
++#define   S_028B6C_DISTRIBUTION_MODE(x)                               (((x) & 0x03) << 17)
++#define   G_028B6C_DISTRIBUTION_MODE(x)                               (((x) >> 17) & 0x03)
++#define   C_028B6C_DISTRIBUTION_MODE                                  0xFFF9FFFF
++#define   S_028B6C_MTYPE(x)                                           (((x) & 0x03) << 19)
++#define   G_028B6C_MTYPE(x)                                           (((x) >> 19) & 0x03)
++#define   C_028B6C_MTYPE                                              0xFFE7FFFF
++/*    */
+ #define R_028B70_DB_ALPHA_TO_MASK                                       0x028B70
+ #define   S_028B70_ALPHA_TO_MASK_ENABLE(x)                            (((x) & 0x1) << 0)
+ #define   G_028B70_ALPHA_TO_MASK_ENABLE(x)                            (((x) >> 0) & 0x1)
+@@ -7994,6 +8903,22 @@
+ #define   S_028BDC_DX10_DIAMOND_TEST_ENA(x)                           (((x) & 0x1) << 12)
+ #define   G_028BDC_DX10_DIAMOND_TEST_ENA(x)                           (((x) >> 12) & 0x1)
+ #define   C_028BDC_DX10_DIAMOND_TEST_ENA                              0xFFFFEFFF
++#define R_028BE0_PA_SC_AA_CONFIG                                        0x028BE0
++#define   S_028BE0_MSAA_NUM_SAMPLES(x)                                (((x) & 0x7) << 0)
++#define   G_028BE0_MSAA_NUM_SAMPLES(x)                                (((x) >> 0) & 0x07)
++#define   C_028BE0_MSAA_NUM_SAMPLES                                   0xFFFFFFF8
++#define   S_028BE0_AA_MASK_CENTROID_DTMN(x)                           (((x) & 0x1) << 4)
++#define   G_028BE0_AA_MASK_CENTROID_DTMN(x)                           (((x) >> 4) & 0x1)
++#define   C_028BE0_AA_MASK_CENTROID_DTMN                              0xFFFFFFEF
++#define   S_028BE0_MAX_SAMPLE_DIST(x)                                 (((x) & 0xf) << 13)
++#define   G_028BE0_MAX_SAMPLE_DIST(x)                                 (((x) >> 13) & 0x0F)
++#define   C_028BE0_MAX_SAMPLE_DIST                                    0xFFFE1FFF
++#define   S_028BE0_MSAA_EXPOSED_SAMPLES(x)                            (((x) & 0x7) << 20)
++#define   G_028BE0_MSAA_EXPOSED_SAMPLES(x)                            (((x) >> 20) & 0x07)
++#define   C_028BE0_MSAA_EXPOSED_SAMPLES                               0xFF8FFFFF
++#define   S_028BE0_DETAIL_TO_EXPOSED_MODE(x)                          (((x) & 0x3) << 24)
++#define   G_028BE0_DETAIL_TO_EXPOSED_MODE(x)                          (((x) >> 24) & 0x03)
++#define   C_028BE0_DETAIL_TO_EXPOSED_MODE                             0xFCFFFFFF
+ #define R_028BE4_PA_SU_VTX_CNTL                                         0x028BE4
+ #define   S_028BE4_PIX_CENTER(x)                                      (((x) & 0x1) << 0)
+ #define   G_028BE4_PIX_CENTER(x)                                      (((x) >> 0) & 0x1)
+@@ -8562,6 +9487,17 @@
+ #define   G_028C70_FMASK_COMPRESSION_DISABLE(x)                       (((x) >> 26) & 0x1)
+ #define   C_028C70_FMASK_COMPRESSION_DISABLE                          0xFBFFFFFF
+ /*     */
++/* VI */
++#define   S_028C70_FMASK_COMPRESS_1FRAG_ONLY(x)                       (((x) & 0x1) << 27)
++#define   G_028C70_FMASK_COMPRESS_1FRAG_ONLY(x)                       (((x) >> 27) & 0x1)
++#define   C_028C70_FMASK_COMPRESS_1FRAG_ONLY                          0xF7FFFFFF
++#define   S_028C70_DCC_ENABLE(x)                                      (((x) & 0x1) << 28)
++#define   G_028C70_DCC_ENABLE(x)                                      (((x) >> 28) & 0x1)
++#define   C_028C70_DCC_ENABLE                                         0xEFFFFFFF
++#define   S_028C70_CMASK_ADDR_TYPE(x)                                 (((x) & 0x03) << 29)
++#define   G_028C70_CMASK_ADDR_TYPE(x)                                 (((x) >> 29) & 0x03)
++#define   C_028C70_CMASK_ADDR_TYPE                                    0x9FFFFFFF
++/*    */
+ #define R_028C74_CB_COLOR0_ATTRIB                                       0x028C74
+ #define   S_028C74_TILE_MODE_INDEX(x)                                 (((x) & 0x1F) << 0)
+ #define   G_028C74_TILE_MODE_INDEX(x)                                 (((x) >> 0) & 0x1F)
+@@ -8569,7 +9505,9 @@
+ #define   S_028C74_FMASK_TILE_MODE_INDEX(x)                           (((x) & 0x1F) << 5)
+ #define   G_028C74_FMASK_TILE_MODE_INDEX(x)                           (((x) >> 5) & 0x1F)
+ #define   C_028C74_FMASK_TILE_MODE_INDEX                              0xFFFFFC1F
+-#define   S_028C74_FMASK_BANK_HEIGHT(x)				      (((x) & 0x3) << 10) /* SI errata */
++#define   S_028C74_FMASK_BANK_HEIGHT(x)                               (((x) & 0x03) << 10)
++#define   G_028C74_FMASK_BANK_HEIGHT(x)                               (((x) >> 10) & 0x03)
++#define   C_028C74_FMASK_BANK_HEIGHT                                  0xFFFFF3FF
+ #define   S_028C74_NUM_SAMPLES(x)                                     (((x) & 0x07) << 12)
+ #define   G_028C74_NUM_SAMPLES(x)                                     (((x) >> 12) & 0x07)
+ #define   C_028C74_NUM_SAMPLES                                        0xFFFF8FFF
+@@ -8579,6 +9517,36 @@
+ #define   S_028C74_FORCE_DST_ALPHA_1(x)                               (((x) & 0x1) << 17)
+ #define   G_028C74_FORCE_DST_ALPHA_1(x)                               (((x) >> 17) & 0x1)
+ #define   C_028C74_FORCE_DST_ALPHA_1                                  0xFFFDFFFF
++/* VI */
++#define R_028C78_CB_COLOR0_DCC_CONTROL                                  0x028C78
++#define   S_028C78_OVERWRITE_COMBINER_DISABLE(x)                      (((x) & 0x1) << 0)
++#define   G_028C78_OVERWRITE_COMBINER_DISABLE(x)                      (((x) >> 0) & 0x1)
++#define   C_028C78_OVERWRITE_COMBINER_DISABLE                         0xFFFFFFFE
++#define   S_028C78_KEY_CLEAR_ENABLE(x)                                (((x) & 0x1) << 1)
++#define   G_028C78_KEY_CLEAR_ENABLE(x)                                (((x) >> 1) & 0x1)
++#define   C_028C78_KEY_CLEAR_ENABLE                                   0xFFFFFFFD
++#define   S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(x)                     (((x) & 0x03) << 2)
++#define   G_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(x)                     (((x) >> 2) & 0x03)
++#define   C_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE                        0xFFFFFFF3
++#define   S_028C78_MIN_COMPRESSED_BLOCK_SIZE(x)                       (((x) & 0x1) << 4)
++#define   G_028C78_MIN_COMPRESSED_BLOCK_SIZE(x)                       (((x) >> 4) & 0x1)
++#define   C_028C78_MIN_COMPRESSED_BLOCK_SIZE                          0xFFFFFFEF
++#define   S_028C78_MAX_COMPRESSED_BLOCK_SIZE(x)                       (((x) & 0x03) << 5)
++#define   G_028C78_MAX_COMPRESSED_BLOCK_SIZE(x)                       (((x) >> 5) & 0x03)
++#define   C_028C78_MAX_COMPRESSED_BLOCK_SIZE                          0xFFFFFF9F
++#define   S_028C78_COLOR_TRANSFORM(x)                                 (((x) & 0x03) << 7)
++#define   G_028C78_COLOR_TRANSFORM(x)                                 (((x) >> 7) & 0x03)
++#define   C_028C78_COLOR_TRANSFORM                                    0xFFFFFE7F
++#define   S_028C78_INDEPENDENT_64B_BLOCKS(x)                          (((x) & 0x1) << 9)
++#define   G_028C78_INDEPENDENT_64B_BLOCKS(x)                          (((x) >> 9) & 0x1)
++#define   C_028C78_INDEPENDENT_64B_BLOCKS                             0xFFFFFDFF
++#define   S_028C78_LOSSY_RGB_PRECISION(x)                             (((x) & 0x0F) << 10)
++#define   G_028C78_LOSSY_RGB_PRECISION(x)                             (((x) >> 10) & 0x0F)
++#define   C_028C78_LOSSY_RGB_PRECISION                                0xFFFFC3FF
++#define   S_028C78_LOSSY_ALPHA_PRECISION(x)                           (((x) & 0x0F) << 14)
++#define   G_028C78_LOSSY_ALPHA_PRECISION(x)                           (((x) >> 14) & 0x0F)
++#define   C_028C78_LOSSY_ALPHA_PRECISION                              0xFFFC3FFF
++/*    */
+ #define R_028C7C_CB_COLOR0_CMASK                                        0x028C7C
+ #define R_028C80_CB_COLOR0_CMASK_SLICE                                  0x028C80
+ #define   S_028C80_TILE_MAX(x)                                        (((x) & 0x3FFF) << 0)
+@@ -8591,90 +9559,105 @@
+ #define   C_028C88_TILE_MAX                                           0xFFC00000
+ #define R_028C8C_CB_COLOR0_CLEAR_WORD0                                  0x028C8C
+ #define R_028C90_CB_COLOR0_CLEAR_WORD1                                  0x028C90
++#define R_028C94_CB_COLOR0_DCC_BASE                                     0x028C94 /* VI */
+ #define R_028C9C_CB_COLOR1_BASE                                         0x028C9C
+ #define R_028CA0_CB_COLOR1_PITCH                                        0x028CA0
+ #define R_028CA4_CB_COLOR1_SLICE                                        0x028CA4
+ #define R_028CA8_CB_COLOR1_VIEW                                         0x028CA8
+ #define R_028CAC_CB_COLOR1_INFO                                         0x028CAC
+ #define R_028CB0_CB_COLOR1_ATTRIB                                       0x028CB0
+-#define R_028CD4_CB_COLOR1_CMASK                                        0x028CB8
++#define R_028CB4_CB_COLOR1_DCC_CONTROL                                  0x028CB4 /* VI */
++#define R_028CB8_CB_COLOR1_CMASK                                        0x028CB8
+ #define R_028CBC_CB_COLOR1_CMASK_SLICE                                  0x028CBC
+ #define R_028CC0_CB_COLOR1_FMASK                                        0x028CC0
+ #define R_028CC4_CB_COLOR1_FMASK_SLICE                                  0x028CC4
+ #define R_028CC8_CB_COLOR1_CLEAR_WORD0                                  0x028CC8
+ #define R_028CCC_CB_COLOR1_CLEAR_WORD1                                  0x028CCC
++#define R_028CD0_CB_COLOR1_DCC_BASE                                     0x028CD0 /* VI */
+ #define R_028CD8_CB_COLOR2_BASE                                         0x028CD8
+ #define R_028CDC_CB_COLOR2_PITCH                                        0x028CDC
+ #define R_028CE0_CB_COLOR2_SLICE                                        0x028CE0
+ #define R_028CE4_CB_COLOR2_VIEW                                         0x028CE4
+ #define R_028CE8_CB_COLOR2_INFO                                         0x028CE8
+ #define R_028CEC_CB_COLOR2_ATTRIB                                       0x028CEC
++#define R_028CF0_CB_COLOR2_DCC_CONTROL                                  0x028CF0 /* VI */
+ #define R_028CF4_CB_COLOR2_CMASK                                        0x028CF4
+ #define R_028CF8_CB_COLOR2_CMASK_SLICE                                  0x028CF8
+ #define R_028CFC_CB_COLOR2_FMASK                                        0x028CFC
+ #define R_028D00_CB_COLOR2_FMASK_SLICE                                  0x028D00
+ #define R_028D04_CB_COLOR2_CLEAR_WORD0                                  0x028D04
+ #define R_028D08_CB_COLOR2_CLEAR_WORD1                                  0x028D08
++#define R_028D0C_CB_COLOR2_DCC_BASE                                     0x028D0C /* VI */
+ #define R_028D14_CB_COLOR3_BASE                                         0x028D14
+ #define R_028D18_CB_COLOR3_PITCH                                        0x028D18
+ #define R_028D1C_CB_COLOR3_SLICE                                        0x028D1C
+ #define R_028D20_CB_COLOR3_VIEW                                         0x028D20
+ #define R_028D24_CB_COLOR3_INFO                                         0x028D24
+ #define R_028D28_CB_COLOR3_ATTRIB                                       0x028D28
++#define R_028D2C_CB_COLOR3_DCC_CONTROL                                  0x028D2C /* VI */
+ #define R_028D30_CB_COLOR3_CMASK                                        0x028D30
+ #define R_028D34_CB_COLOR3_CMASK_SLICE                                  0x028D34
+ #define R_028D38_CB_COLOR3_FMASK                                        0x028D38
+ #define R_028D3C_CB_COLOR3_FMASK_SLICE                                  0x028D3C
+ #define R_028D40_CB_COLOR3_CLEAR_WORD0                                  0x028D40
+ #define R_028D44_CB_COLOR3_CLEAR_WORD1                                  0x028D44
++#define R_028D48_CB_COLOR3_DCC_BASE                                     0x028D48 /* VI */
+ #define R_028D50_CB_COLOR4_BASE                                         0x028D50
+ #define R_028D54_CB_COLOR4_PITCH                                        0x028D54
+ #define R_028D58_CB_COLOR4_SLICE                                        0x028D58
+ #define R_028D5C_CB_COLOR4_VIEW                                         0x028D5C
+ #define R_028D60_CB_COLOR4_INFO                                         0x028D60
+ #define R_028D64_CB_COLOR4_ATTRIB                                       0x028D64
++#define R_028D68_CB_COLOR4_DCC_CONTROL                                  0x028D68 /* VI */
+ #define R_028D6C_CB_COLOR4_CMASK                                        0x028D6C
+ #define R_028D70_CB_COLOR4_CMASK_SLICE                                  0x028D70
+ #define R_028D74_CB_COLOR4_FMASK                                        0x028D74
+ #define R_028D78_CB_COLOR4_FMASK_SLICE                                  0x028D78
+ #define R_028D7C_CB_COLOR4_CLEAR_WORD0                                  0x028D7C
+ #define R_028D80_CB_COLOR4_CLEAR_WORD1                                  0x028D80
++#define R_028D84_CB_COLOR4_DCC_BASE                                     0x028D84 /* VI */
+ #define R_028D8C_CB_COLOR5_BASE                                         0x028D8C
+ #define R_028D90_CB_COLOR5_PITCH                                        0x028D90
+ #define R_028D94_CB_COLOR5_SLICE                                        0x028D94
+ #define R_028D98_CB_COLOR5_VIEW                                         0x028D98
+ #define R_028D9C_CB_COLOR5_INFO                                         0x028D9C
+ #define R_028DA0_CB_COLOR5_ATTRIB                                       0x028DA0
++#define R_028DA4_CB_COLOR5_DCC_CONTROL                                  0x028DA4 /* VI */
+ #define R_028DA8_CB_COLOR5_CMASK                                        0x028DA8
+ #define R_028DAC_CB_COLOR5_CMASK_SLICE                                  0x028DAC
+ #define R_028DB0_CB_COLOR5_FMASK                                        0x028DB0
+ #define R_028DB4_CB_COLOR5_FMASK_SLICE                                  0x028DB4
+ #define R_028DB8_CB_COLOR5_CLEAR_WORD0                                  0x028DB8
+ #define R_028DBC_CB_COLOR5_CLEAR_WORD1                                  0x028DBC
++#define R_028DC0_CB_COLOR5_DCC_BASE                                     0x028DC0 /* VI */
+ #define R_028DC8_CB_COLOR6_BASE                                         0x028DC8
+ #define R_028DCC_CB_COLOR6_PITCH                                        0x028DCC
+ #define R_028DD0_CB_COLOR6_SLICE                                        0x028DD0
+ #define R_028DD4_CB_COLOR6_VIEW                                         0x028DD4
+ #define R_028DD8_CB_COLOR6_INFO                                         0x028DD8
+ #define R_028DDC_CB_COLOR6_ATTRIB                                       0x028DDC
++#define R_028DE0_CB_COLOR6_DCC_CONTROL                                  0x028DE0 /* VI */
+ #define R_028DE4_CB_COLOR6_CMASK                                        0x028DE4
+ #define R_028DE8_CB_COLOR6_CMASK_SLICE                                  0x028DE8
+ #define R_028DEC_CB_COLOR6_FMASK                                        0x028DEC
+ #define R_028DF0_CB_COLOR6_FMASK_SLICE                                  0x028DF0
+ #define R_028DF4_CB_COLOR6_CLEAR_WORD0                                  0x028DF4
+ #define R_028DF8_CB_COLOR6_CLEAR_WORD1                                  0x028DF8
++#define R_028DFC_CB_COLOR6_DCC_BASE                                     0x028DFC /* VI */
+ #define R_028E04_CB_COLOR7_BASE                                         0x028E04
+ #define R_028E08_CB_COLOR7_PITCH                                        0x028E08
+ #define R_028E0C_CB_COLOR7_SLICE                                        0x028E0C
+ #define R_028E10_CB_COLOR7_VIEW                                         0x028E10
+ #define R_028E14_CB_COLOR7_INFO                                         0x028E14
+ #define R_028E18_CB_COLOR7_ATTRIB                                       0x028E18
++#define R_028E1C_CB_COLOR7_DCC_CONTROL                                  0x028E1C /* VI */
+ #define R_028E20_CB_COLOR7_CMASK                                        0x028E20
+ #define R_028E24_CB_COLOR7_CMASK_SLICE                                  0x028E24
+ #define R_028E28_CB_COLOR7_FMASK                                        0x028E28
+ #define R_028E2C_CB_COLOR7_FMASK_SLICE                                  0x028E2C
+ #define R_028E30_CB_COLOR7_CLEAR_WORD0                                  0x028E30
+ #define R_028E34_CB_COLOR7_CLEAR_WORD1                                  0x028E34
++#define R_028E38_CB_COLOR7_DCC_BASE                                     0x028E38 /* VI */
+ 
+ /* SI async DMA packets */
+ #define SI_DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) |    \
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0012-radeonsi-add-VI-hardware-support.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0012-radeonsi-add-VI-hardware-support.patch
new file mode 100644
index 00000000..60b858b2
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0012-radeonsi-add-VI-hardware-support.patch
@@ -0,0 +1,410 @@
+From 5de6f83f9ce743f5a2ae600bb5cb2eba48a54d3f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 20:44:54 +0200
+Subject: [PATCH 12/29] radeonsi: add VI hardware support
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/r600_pipe_common.c   |  6 ++++
+ src/gallium/drivers/radeon/r600_pipe_common.h   |  1 +
+ src/gallium/drivers/radeonsi/si_descriptors.c   | 15 +++++++--
+ src/gallium/drivers/radeonsi/si_pipe.c          |  5 ++-
+ src/gallium/drivers/radeonsi/si_shader.c        | 24 +++++++++++--
+ src/gallium/drivers/radeonsi/si_state.c         | 45 +++++++++++++++++++++----
+ src/gallium/drivers/radeonsi/si_state_draw.c    | 41 ++++++++++++++++------
+ src/gallium/drivers/radeonsi/si_state_shaders.c |  8 ++++-
+ 8 files changed, 121 insertions(+), 24 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
+index 3b26dea..80a32ca 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.c
++++ b/src/gallium/drivers/radeon/r600_pipe_common.c
+@@ -379,6 +379,9 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
+ 	case CHIP_KABINI: return "AMD KABINI";
+ 	case CHIP_HAWAII: return "AMD HAWAII";
+ 	case CHIP_MULLINS: return "AMD MULLINS";
++	case CHIP_TONGA: return "AMD TONGA";
++	case CHIP_ICELAND: return "AMD ICELAND";
++	case CHIP_CARRIZO: return "AMD CARRIZO";
+ 	default: return "AMD unknown";
+ 	}
+ }
+@@ -496,6 +499,9 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
+ #else
+ 		return "kabini";
+ #endif
++	case CHIP_TONGA: return "tonga";
++	case CHIP_ICELAND: return "iceland";
++	case CHIP_CARRIZO: return "carrizo";
+ 	default: return "";
+ 	}
+ }
+diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
+index bdb4541..8944059 100644
+--- a/src/gallium/drivers/radeon/r600_pipe_common.h
++++ b/src/gallium/drivers/radeon/r600_pipe_common.h
+@@ -232,6 +232,7 @@ struct r600_surface {
+ 	unsigned cb_color_pitch;	/* EG and later */
+ 	unsigned cb_color_slice;	/* EG and later */
+ 	unsigned cb_color_attrib;	/* EG and later */
++	unsigned cb_dcc_control;	/* VI and later */
+ 	unsigned cb_color_fmask;	/* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
+ 	unsigned cb_color_fmask_slice;	/* EG and later */
+ 	unsigned cb_color_cmask;	/* CB_COLORn_TILE (r600 only) */
+diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
+index bbfd36d..88a507d 100644
+--- a/src/gallium/drivers/radeonsi/si_descriptors.c
++++ b/src/gallium/drivers/radeonsi/si_descriptors.c
+@@ -675,7 +675,8 @@ void si_update_vertex_buffers(struct si_context *sctx)
+ 		desc[0] = va & 0xFFFFFFFF;
+ 		desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ 			  S_008F04_STRIDE(vb->stride);
+-		if (vb->stride)
++
++		if (sctx->b.chip_class <= CIK && vb->stride)
+ 			/* Round up by rounding down and adding 1 */
+ 			desc[2] = (vb->buffer->width0 - offset -
+ 				   sctx->vertex_elements->format_size[i]) /
+@@ -839,6 +840,9 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+ 			break;
+ 		}
+ 
++		if (sctx->b.chip_class >= VI && stride)
++			num_records *= stride;
++
+ 		/* Set the descriptor. */
+ 		uint32_t *desc = buffers->desc_data[slot];
+ 		desc[0] = va;
+@@ -929,7 +933,11 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
+ 			struct pipe_resource *buffer = targets[i]->buffer;
+ 			uint64_t va = r600_resource(buffer)->gpu_address;
+ 
+-			/* Set the descriptor. */
++			/* Set the descriptor.
++			 *
++			 * On VI, the format must be non-INVALID, otherwise
++			 * the buffer will be considered not bound and store
++			 * instructions will be no-ops. */
+ 			uint32_t *desc = buffers->desc_data[bufidx];
+ 			desc[0] = va;
+ 			desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
+@@ -937,7 +945,8 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
+ 			desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ 				  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ 				  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+-				  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
++				  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
++				  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ 
+ 			/* Set the resource. */
+ 			pipe_resource_reference(&buffers->buffers[bufidx],
+diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
+index 91b4d6f..0bb7a35 100644
+--- a/src/gallium/drivers/radeonsi/si_pipe.c
++++ b/src/gallium/drivers/radeonsi/si_pipe.c
+@@ -130,6 +130,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
+ 	switch (sctx->b.chip_class) {
+ 	case SI:
+ 	case CIK:
++	case VI:
+ 		si_init_state_functions(sctx);
+ 		si_init_shader_functions(sctx);
+ 		si_init_config(sctx);
+@@ -181,7 +182,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
+ 	r600_target = radeon_llvm_get_r600_target(triple);
+ 	sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
+ 					   r600_get_llvm_processor_name(sscreen->b.family),
+-					   "+DumpCode,+vgpr-spilling",
++					   sctx->b.chip_class >= VI ?
++						   "+DumpCode" :
++						   "+DumpCode,+vgpr-spilling",
+ 					   LLVMCodeGenLevelDefault,
+ 					   LLVMRelocDefault,
+ 					   LLVMCodeModelDefault);
+diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
+index 89f02ab..9b9a9aa 100644
+--- a/src/gallium/drivers/radeonsi/si_shader.c
++++ b/src/gallium/drivers/radeonsi/si_shader.c
+@@ -2060,6 +2060,7 @@ static void txq_fetch_args(
+ 	struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+ 	const struct tgsi_full_instruction *inst = emit_data->inst;
+ 	struct gallivm_state *gallivm = bld_base->base.gallivm;
++	LLVMBuilderRef builder = gallivm->builder;
+ 	unsigned target = inst->Texture.Texture;
+ 
+ 	if (target == TGSI_TEXTURE_BUFFER) {
+@@ -2067,10 +2068,27 @@ static void txq_fetch_args(
+ 		LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
+ 
+ 		/* Read the size from the buffer descriptor directly. */
+-		LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
+-		size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
+-		size = LLVMBuildExtractElement(gallivm->builder, size,
++		LLVMValueRef res = si_shader_ctx->resources[inst->Src[1].Register.Index];
++		res = LLVMBuildBitCast(builder, res, v8i32, "");
++		LLVMValueRef size = LLVMBuildExtractElement(builder, res,
+ 					      lp_build_const_int32(gallivm, 6), "");
++
++		if (si_shader_ctx->screen->b.chip_class >= VI) {
++			/* On VI, the descriptor contains the size in bytes,
++			 * but TXQ must return the size in elements.
++			 * The stride is always non-zero for resources using TXQ.
++			 */
++			LLVMValueRef stride =
++				LLVMBuildExtractElement(builder, res,
++							lp_build_const_int32(gallivm, 5), "");
++			stride = LLVMBuildLShr(builder, stride,
++					       lp_build_const_int32(gallivm, 16), "");
++			stride = LLVMBuildAnd(builder, stride,
++					      lp_build_const_int32(gallivm, 0x3FFF), "");
++
++			size = LLVMBuildUDiv(builder, size, stride, "");
++		}
++
+ 		emit_data->args[0] = size;
+ 		return;
+ 	}
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index 6a0b093..b35fbd5 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -46,7 +46,7 @@ static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
+ 
+ uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
+ {
+-	if (sscreen->b.chip_class == CIK &&
++	if (sscreen->b.chip_class >= CIK &&
+ 	    sscreen->b.info.cik_macrotile_mode_array_valid) {
+ 		unsigned index, tileb;
+ 
+@@ -1815,6 +1815,9 @@ static void si_initialize_color_surface(struct si_context *sctx,
+ 	surf->cb_color_info = color_info;
+ 	surf->cb_color_attrib = color_attrib;
+ 
++	if (sctx->b.chip_class >= VI)
++		surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
++
+ 	if (rtex->fmask.size) {
+ 		surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
+ 		surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
+@@ -1960,6 +1963,10 @@ static void si_init_depth_surface(struct si_context *sctx,
+ 		db_htile_surface = 0;
+ 	}
+ 
++	/* Bug workaround. */
++	if (sctx->b.chip_class >= VI)
++		s_info |= S_028044_TILE_STENCIL_DISABLE(1);
++
+ 	assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
+ 
+ 	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
+@@ -2051,7 +2058,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
+ 	si_update_fb_rs_state(sctx);
+ 	si_update_fb_blend_state(sctx);
+ 
+-	sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
++	sctx->framebuffer.atom.num_dw = state->nr_cbufs*16 + (8 - state->nr_cbufs)*3;
+ 	sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
+ 	sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
+ 	sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
+@@ -2130,20 +2137,24 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
+ 				RADEON_PRIO_COLOR_META);
+ 		}
+ 
+-		r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
++		r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
++					   sctx->b.chip_class >= VI ? 14 : 13);
+ 		radeon_emit(cs, cb->cb_color_base);	/* R_028C60_CB_COLOR0_BASE */
+ 		radeon_emit(cs, cb->cb_color_pitch);	/* R_028C64_CB_COLOR0_PITCH */
+ 		radeon_emit(cs, cb->cb_color_slice);	/* R_028C68_CB_COLOR0_SLICE */
+ 		radeon_emit(cs, cb->cb_color_view);	/* R_028C6C_CB_COLOR0_VIEW */
+ 		radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
+ 		radeon_emit(cs, cb->cb_color_attrib);	/* R_028C74_CB_COLOR0_ATTRIB */
+-		radeon_emit(cs, 0);			/* R_028C78 unused */
++		radeon_emit(cs, cb->cb_dcc_control);	/* R_028C78_CB_COLOR0_DCC_CONTROL */
+ 		radeon_emit(cs, tex->cmask.base_address_reg);	/* R_028C7C_CB_COLOR0_CMASK */
+ 		radeon_emit(cs, tex->cmask.slice_tile_max);	/* R_028C80_CB_COLOR0_CMASK_SLICE */
+ 		radeon_emit(cs, cb->cb_color_fmask);		/* R_028C84_CB_COLOR0_FMASK */
+ 		radeon_emit(cs, cb->cb_color_fmask_slice);	/* R_028C88_CB_COLOR0_FMASK_SLICE */
+ 		radeon_emit(cs, tex->color_clear_value[0]);	/* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
+ 		radeon_emit(cs, tex->color_clear_value[1]);	/* R_028C90_CB_COLOR0_CLEAR_WORD1 */
++
++		if (sctx->b.chip_class >= VI)
++			radeon_emit(cs, 0);	/* R_028C94_CB_COLOR0_DCC_BASE */
+ 	}
+ 	/* set CB_COLOR1_INFO for possible dual-src blending */
+ 	if (i == 1 && state->cbufs[0]) {
+@@ -2286,7 +2297,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
+ 
+ 	/* Buffer resource. */
+ 	if (texture->target == PIPE_BUFFER) {
+-		unsigned stride;
++		unsigned stride, num_records;
+ 
+ 		desc = util_format_description(state->format);
+ 		first_non_void = util_format_get_first_non_void_channel(state->format);
+@@ -2295,10 +2306,16 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
+ 		format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
+ 		num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
+ 
++		num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
++		num_records = MIN2(num_records, texture->width0 / stride);
++
++		if (sctx->b.chip_class >= VI)
++			num_records *= stride;
++
+ 		view->state[4] = va;
+ 		view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ 				 S_008F04_STRIDE(stride);
+-		view->state[6] = state->u.buf.last_element + 1 - state->u.buf.first_element;
++		view->state[6] = num_records;
+ 		view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
+ 				 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
+ 				 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
+@@ -3070,6 +3087,15 @@ void si_init_config(struct si_context *sctx)
+ 			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
+ 			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
+ 			break;
++		case CHIP_TONGA:
++			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
++			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002a);
++			break;
++		case CHIP_ICELAND:
++		case CHIP_CARRIZO:
++			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002);
++			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
++			break;
+ 		case CHIP_KAVERI:
+ 			/* XXX todo */
+ 		case CHIP_KABINI:
+@@ -3162,5 +3188,12 @@ void si_init_config(struct si_context *sctx)
+ 		si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
+ 	}
+ 
++	if (sctx->b.chip_class >= VI) {
++		si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
++			       S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
++		si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
++		si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
++	}
++
+ 	sctx->init_config = pm4;
+ }
+diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
+index 2e77d85..2d38b20 100644
+--- a/src/gallium/drivers/radeonsi/si_state_draw.c
++++ b/src/gallium/drivers/radeonsi/si_state_draw.c
+@@ -146,7 +146,8 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
+ 	return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
+ 		S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
+ 		S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
+-		S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
++		S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
++		S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ? 2 : 0);
+ }
+ 
+ static void si_emit_scratch_reloc(struct si_context *sctx)
+@@ -275,12 +276,24 @@ static void si_emit_draw_packets(struct si_context *sctx,
+ 	if (info->indexed) {
+ 		radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
+ 
+-		if (ib->index_size == 4) {
+-			radeon_emit(cs, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
+-					V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
+-		} else {
+-			radeon_emit(cs, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
+-					V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
++		/* index type */
++		switch (ib->index_size) {
++		case 1:
++			radeon_emit(cs, V_028A7C_VGT_INDEX_8);
++			break;
++		case 2:
++			radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
++				    (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
++					     V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
++			break;
++		case 4:
++			radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
++				    (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
++					     V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
++			break;
++		default:
++			assert(!"unreachable");
++			return;
+ 		}
+ 	}
+ 
+@@ -406,9 +419,14 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
+ 
+ 	if (sctx->flags & SI_CONTEXT_INV_TC_L1)
+ 		cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
+-	if (sctx->flags & SI_CONTEXT_INV_TC_L2)
++	if (sctx->flags & SI_CONTEXT_INV_TC_L2) {
+ 		cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
+ 
++		/* TODO: this might not be needed. */
++		if (sctx->chip_class >= VI)
++			cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
++	}
++
+ 	if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
+ 		cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
+ 				 S_0085F0_CB0_DEST_BASE_ENA(1) |
+@@ -550,7 +568,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+ 		ib.offset = sctx->index_buffer.offset;
+ 
+ 		/* Translate or upload, if needed. */
+-		if (ib.index_size == 1) {
++		/* 8-bit indices are supported on VI. */
++		if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
+ 			struct pipe_resource *out_buffer = NULL;
+ 			unsigned out_offset, start, count, start_offset;
+ 			void *ptr;
+@@ -585,6 +604,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+ 		}
+ 	}
+ 
++	/* TODO: VI should read index buffers through TC, so this shouldn't be
++	 * needed on VI. */
+ 	if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) {
+ 		sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
+ 		r600_resource(ib.buffer)->TC_L2_dirty = false;
+@@ -618,7 +639,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+ 
+ 	/* Workaround for a VGT hang when streamout is enabled.
+ 	 * It must be done after drawing. */
+-	if (sctx->b.family == CHIP_HAWAII &&
++	if ((sctx->b.family == CHIP_HAWAII || sctx->b.family == CHIP_TONGA) &&
+ 	    (sctx->b.streamout.streamout_enabled ||
+ 	     sctx->b.streamout.prims_gen_query_enabled)) {
+ 		sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
+diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
+index 1bbc6b3..09ca792 100644
+--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
++++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
+@@ -700,7 +700,7 @@ bcolor:
+ static void si_init_gs_rings(struct si_context *sctx)
+ {
+ 	unsigned esgs_ring_size = 128 * 1024;
+-	unsigned gsvs_ring_size = 64 * 1024 * 1024;
++	unsigned gsvs_ring_size = 60 * 1024 * 1024;
+ 
+ 	assert(!sctx->gs_rings);
+ 	sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
+@@ -712,6 +712,12 @@ static void si_init_gs_rings(struct si_context *sctx)
+ 					     PIPE_USAGE_DEFAULT, gsvs_ring_size);
+ 
+ 	if (sctx->b.chip_class >= CIK) {
++		if (sctx->b.chip_class >= VI) {
++			/* The maximum sizes are 63.999 MB on VI, because
++			 * the register fields only have 18 bits. */
++			assert(esgs_ring_size / 256 < (1 << 18));
++			assert(gsvs_ring_size / 256 < (1 << 18));
++		}
+ 		si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
+ 			       esgs_ring_size / 256);
+ 		si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0013-radeonsi-add-a-temporary-workaround-for-a-shader-bug.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0013-radeonsi-add-a-temporary-workaround-for-a-shader-bug.patch
new file mode 100644
index 00000000..7180ff45
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0013-radeonsi-add-a-temporary-workaround-for-a-shader-bug.patch
@@ -0,0 +1,163 @@
+From 5c6a9bdcff5a32d31433896f34078e7a81ca3604 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 22:33:04 +0200
+Subject: [PATCH 13/29] radeonsi: add a temporary workaround for a shader bug
+
+This will be reverted after the corresponding LLVM fix is cherry-picked and
+released as part of LLVM 3.6.
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeonsi/si_state_shaders.c | 47 ++++++++++++++++---------
+ 1 file changed, 31 insertions(+), 16 deletions(-)
+
+diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
+index 09ca792..5833ee1 100644
+--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
++++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
+@@ -33,7 +33,19 @@
+ #include "util/u_memory.h"
+ #include "util/u_simple_shaders.h"
+ 
+-static void si_shader_es(struct si_shader *shader)
++/* TODO: the compiler has a better workaround, remove this */
++static unsigned si_adjust_num_sgprs(struct si_screen *sscreen, unsigned num_sgprs)
++{
++	assert(num_sgprs <= 104);
++
++	if (sscreen->b.family == CHIP_TONGA ||
++	    sscreen->b.family == CHIP_ICELAND)
++		num_sgprs = 104;
++
++	return num_sgprs;
++}
++
++static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
+ {
+ 	struct si_pm4_state *pm4;
+ 	unsigned num_sgprs, num_user_sgprs;
+@@ -57,7 +69,7 @@ static void si_shader_es(struct si_shader *shader)
+ 		/* Last 2 reserved SGPRs are used for VCC */
+ 		num_sgprs = num_user_sgprs + 1 + 2;
+ 	}
+-	assert(num_sgprs <= 104);
++	num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
+ 
+ 	si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
+ 	si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
+@@ -71,7 +83,7 @@ static void si_shader_es(struct si_shader *shader)
+ 		       S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
+ }
+ 
+-static void si_shader_gs(struct si_shader *shader)
++static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
+ {
+ 	unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
+ 	unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
+@@ -130,7 +142,7 @@ static void si_shader_gs(struct si_shader *shader)
+ 		/* Last 2 reserved SGPRs are used for VCC */
+ 		num_sgprs = num_user_sgprs + 2 + 2;
+ 	}
+-	assert(num_sgprs <= 104);
++	num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
+ 
+ 	si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
+ 		       S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
+@@ -141,7 +153,7 @@ static void si_shader_gs(struct si_shader *shader)
+ 		       S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
+ }
+ 
+-static void si_shader_vs(struct si_shader *shader)
++static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader)
+ {
+ 	struct tgsi_shader_info *info = &shader->selector->info;
+ 	struct si_pm4_state *pm4;
+@@ -173,7 +185,7 @@ static void si_shader_vs(struct si_shader *shader)
+ 		/* Last 2 reserved SGPRs are used for VCC */
+ 		num_sgprs = num_user_sgprs + 2;
+ 	}
+-	assert(num_sgprs <= 104);
++	num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
+ 
+ 	/* Certain attributes (position, psize, etc.) don't count as params.
+ 	 * VS is required to export at least one param and r600_shader_from_tgsi()
+@@ -233,7 +245,7 @@ static void si_shader_vs(struct si_shader *shader)
+ 			       S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
+ }
+ 
+-static void si_shader_ps(struct si_shader *shader)
++static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
+ {
+ 	struct tgsi_shader_info *info = &shader->selector->info;
+ 	struct si_pm4_state *pm4;
+@@ -308,7 +320,7 @@ static void si_shader_ps(struct si_shader *shader)
+ 		/* Last 2 reserved SGPRs are used for VCC */
+ 		num_sgprs = num_user_sgprs + 1 + 2;
+ 	}
+-	assert(num_sgprs <= 104);
++	num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
+ 
+ 	si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
+ 		       S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
+@@ -320,7 +332,8 @@ static void si_shader_ps(struct si_shader *shader)
+ 		       S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
+ }
+ 
+-static void si_shader_init_pm4_state(struct si_shader *shader)
++static void si_shader_init_pm4_state(struct si_screen *sscreen,
++				     struct si_shader *shader)
+ {
+ 
+ 	if (shader->pm4)
+@@ -329,16 +342,16 @@ static void si_shader_init_pm4_state(struct si_shader *shader)
+ 	switch (shader->selector->type) {
+ 	case PIPE_SHADER_VERTEX:
+ 		if (shader->key.vs.as_es)
+-			si_shader_es(shader);
++			si_shader_es(sscreen, shader);
+ 		else
+-			si_shader_vs(shader);
++			si_shader_vs(sscreen, shader);
+ 		break;
+ 	case PIPE_SHADER_GEOMETRY:
+-		si_shader_gs(shader);
+-		si_shader_vs(shader->gs_copy_shader);
++		si_shader_gs(sscreen, shader);
++		si_shader_vs(sscreen, shader->gs_copy_shader);
+ 		break;
+ 	case PIPE_SHADER_FRAGMENT:
+-		si_shader_ps(shader);
++		si_shader_ps(sscreen, shader);
+ 		break;
+ 	default:
+ 		assert(0);
+@@ -439,6 +452,8 @@ static int si_shader_select(struct pipe_context *ctx,
+ 		shader->next_variant = sel->current;
+ 		sel->current = shader;
+ 	} else {
++		struct si_screen *sscreen = (struct si_screen*)ctx->screen;
++
+ 		shader = CALLOC(1, sizeof(struct si_shader));
+ 		shader->selector = sel;
+ 		shader->key = key;
+@@ -454,7 +469,7 @@ static int si_shader_select(struct pipe_context *ctx,
+ 			FREE(shader);
+ 			return r;
+ 		}
+-		si_shader_init_pm4_state(shader);
++		si_shader_init_pm4_state(sscreen, shader);
+ 		sel->num_shaders++;
+ 	}
+ 
+@@ -778,7 +793,7 @@ static unsigned si_update_scratch_buffer(struct si_context *sctx,
+ 	sctx->screen->b.ws->buffer_unmap(shader->bo->cs_buf);
+ 
+ 	/* Update the shader state to use the new shader bo. */
+-	si_shader_init_pm4_state(shader);
++	si_shader_init_pm4_state(sctx->screen, shader);
+ 
+ 	r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
+ 
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0014-gallium-radeon-use-VM-for-UVD.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0014-gallium-radeon-use-VM-for-UVD.patch
new file mode 100644
index 00000000..889eb023
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0014-gallium-radeon-use-VM-for-UVD.patch
@@ -0,0 +1,64 @@
+From cbd8c552976aeebe913749c511c6656d84cd23a4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 9 Apr 2014 19:41:06 +0200
+Subject: [PATCH 14/29] gallium/radeon: use VM for UVD
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: (leo) add checking for driver backend
+v3: (leo) change variable name from use_amdgpu to use_vm
+v4: rebase by Marek
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_uvd.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
+index be58d0b..ac850a2 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.c
++++ b/src/gallium/drivers/radeon/radeon_uvd.c
+@@ -82,6 +82,7 @@ struct ruvd_decoder {
+ 	unsigned			bs_size;
+ 
+ 	struct rvid_buffer		dpb;
++	bool				use_legacy;
+ };
+ 
+ /* flush IB to the hardware */
+@@ -107,8 +108,16 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
+ 
+ 	reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain,
+ 					  RADEON_PRIO_MIN);
+-	set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
+-	set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
++	if (!dec->use_legacy) {
++		uint64_t addr;
++		addr = dec->ws->buffer_get_virtual_address(cs_buf);
++		addr = addr + off;
++		set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
++		set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
++	} else {
++		set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
++		set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
++	}
+ 	set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
+ }
+ 
+@@ -791,6 +800,9 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 	if (!dec)
+ 		return NULL;
+ 
++	if (info.drm_major < 3)
++		dec->use_legacy = TRUE;
++
+ 	dec->base = *templ;
+ 	dec->base.context = context;
+ 	dec->base.width = width;
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0015-gallium-radeon-use-VM-for-VCE.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0015-gallium-radeon-use-VM-for-VCE.patch
new file mode 100644
index 00000000..6524c25a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0015-gallium-radeon-use-VM-for-VCE.patch
@@ -0,0 +1,151 @@
+From 36b6118dfeae432644cb6fbba249319976c35dfa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 10 Apr 2014 17:18:32 +0200
+Subject: [PATCH 15/29] gallium/radeon: use VM for VCE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: (leo) add checking for driver backend
+v3: (leo) change variable name from use_amdgpu to use_vm
+v4: rebase by Marek
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_vce.c        | 24 ++++++++++++++++++++++++
+ src/gallium/drivers/radeon/radeon_vce.h        | 15 +++++++++------
+ src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 17 +++++++----------
+ 3 files changed, 40 insertions(+), 16 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
+index e220f40..d1495a2 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.c
++++ b/src/gallium/drivers/radeon/radeon_vce.c
+@@ -353,6 +353,8 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+ 	if (!enc)
+ 		return NULL;
+ 
++	if (rscreen->info.drm_major == 3)
++		enc->use_vm = true;
+ 	if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
+ 		enc->use_vui = true;
+ 
+@@ -428,3 +430,25 @@ bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
+ {
+ 	return rscreen->info.vce_fw_version == ((40 << 24) | (2 << 16) | (2 << 8));
+ }
++
++/**
++ * Add the buffer as relocation to the current command submission
++ */
++void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle *buf,
++                     enum radeon_bo_usage usage, enum radeon_bo_domain domain,
++                     uint32_t offset)
++{
++	int reloc_idx;
++
++	reloc_idx = enc->ws->cs_add_reloc(enc->cs, buf, usage, domain, RADEON_PRIO_MIN);
++	if (enc->use_vm) {
++		uint64_t addr;
++		addr = enc->ws->buffer_get_virtual_address(buf);
++		addr = addr + offset;
++		RVCE_CS(addr >> 32);
++		RVCE_CS(addr);
++	} else {
++		RVCE_CS(reloc_idx * 4);
++		RVCE_CS(offset);
++	}
++}
+diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
+index 5c6317a..67ba333 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.h
++++ b/src/gallium/drivers/radeon/radeon_vce.h
+@@ -36,13 +36,11 @@
+ 
+ #include "util/u_double_list.h"
+ 
+-#define RVCE_RELOC(buf, usage, domain) (enc->ws->cs_add_reloc(enc->cs, (buf), (usage), domain, RADEON_PRIO_MIN))
+-
+ #define RVCE_CS(value) (enc->cs->buf[enc->cs->cdw++] = (value))
+ #define RVCE_BEGIN(cmd) { uint32_t *begin = &enc->cs->buf[enc->cs->cdw++]; RVCE_CS(cmd)
+-#define RVCE_READ(buf, domain) RVCE_CS(RVCE_RELOC(buf, RADEON_USAGE_READ, domain) * 4)
+-#define RVCE_WRITE(buf, domain) RVCE_CS(RVCE_RELOC(buf, RADEON_USAGE_WRITE, domain) * 4)
+-#define RVCE_READWRITE(buf, domain) RVCE_CS(RVCE_RELOC(buf, RADEON_USAGE_READWRITE, domain) * 4)
++#define RVCE_READ(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
++#define RVCE_WRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
++#define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
+ #define RVCE_END() *begin = (&enc->cs->buf[enc->cs->cdw] - begin) * 4; }
+ 
+ struct r600_common_screen;
+@@ -101,7 +99,8 @@ struct rvce_encoder {
+ 	struct rvid_buffer		*fb;
+ 	struct rvid_buffer		cpb;
+ 	struct pipe_h264_enc_picture_desc pic;
+-	bool use_vui;
++	bool				use_vm;
++	bool				use_vui;
+ };
+ 
+ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+@@ -111,6 +110,10 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+ 
+ bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
+ 
++void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle *buf,
++		     enum radeon_bo_usage usage, enum radeon_bo_domain domain,
++		     uint32_t offset);
++
+ /* init vce fw 40.2.2 specific callbacks */
+ void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
+ 
+diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+index 0902957..1e7f278 100644
+--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
++++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+@@ -94,8 +94,7 @@ static void task_info(struct rvce_encoder *enc, uint32_t taskOperation)
+ static void feedback(struct rvce_encoder *enc)
+ {
+ 	RVCE_BEGIN(0x05000005); // feedback buffer
+-	RVCE_WRITE(enc->fb->res->cs_buf, enc->fb->res->domains); // feedbackRingAddressHi
+-	RVCE_CS(0x00000000); // feedbackRingAddressLo
++	RVCE_WRITE(enc->fb->res->cs_buf, enc->fb->res->domains, 0x0); // feedbackRingAddressHi/Lo
+ 	RVCE_CS(0x00000001); // feedbackRingSize
+ 	RVCE_END();
+ }
+@@ -306,13 +305,11 @@ static void encode(struct rvce_encoder *enc)
+ 	task_info(enc, 0x00000003);
+ 
+ 	RVCE_BEGIN(0x05000001); // context buffer
+-	RVCE_READWRITE(enc->cpb.res->cs_buf, enc->cpb.res->domains); // encodeContextAddressHi
+-	RVCE_CS(0x00000000); // encodeContextAddressLo
++	RVCE_READWRITE(enc->cpb.res->cs_buf, enc->cpb.res->domains, 0x0); // encodeContextAddressHi/Lo
+ 	RVCE_END();
+ 
+ 	RVCE_BEGIN(0x05000004); // video bitstream buffer
+-	RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT); // videoBitstreamRingAddressHi
+-	RVCE_CS(0x00000000); // videoBitstreamRingAddressLo
++	RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0x0); // videoBitstreamRingAddressHi/Lo
+ 	RVCE_CS(enc->bs_size); // videoBitstreamRingSize
+ 	RVCE_END();
+ 
+@@ -324,10 +321,10 @@ static void encode(struct rvce_encoder *enc)
+ 	RVCE_CS(0x00000000); // insertAUD
+ 	RVCE_CS(0x00000000); // endOfSequence
+ 	RVCE_CS(0x00000000); // endOfStream
+-	RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM); // inputPictureLumaAddressHi
+-	RVCE_CS(enc->luma->level[0].offset); // inputPictureLumaAddressLo
+-	RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM); // inputPictureChromaAddressHi
+-	RVCE_CS(enc->chroma->level[0].offset); // inputPictureChromaAddressLo
++	RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
++		  enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
++	RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
++		  enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
+ 	RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
+ 	RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
+ 	RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0016-gallium-radeon-add-h264-performance-HW-decoder-suppo.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0016-gallium-radeon-add-h264-performance-HW-decoder-suppo.patch
new file mode 100644
index 00000000..09468be9
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0016-gallium-radeon-add-h264-performance-HW-decoder-suppo.patch
@@ -0,0 +1,267 @@
+From 97d04773e92c30cef789463e939c722e5f19438c Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 15 Dec 2014 12:51:50 -0500
+Subject: [PATCH 16/29] gallium/radeon: add h264 performance HW decoder support
+
+v2: -make tonga use new h264 performance HW decoder;
+    -integrate it scaling buffer to msg_fb buffer
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_uvd.c | 63 +++++++++++++++++++++------------
+ src/gallium/drivers/radeon/radeon_uvd.h |  2 ++
+ 2 files changed, 43 insertions(+), 22 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
+index ac850a2..b0bfb3b 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.c
++++ b/src/gallium/drivers/radeon/radeon_uvd.c
+@@ -57,6 +57,7 @@
+ 
+ #define FB_BUFFER_OFFSET 0x1000
+ #define FB_BUFFER_SIZE 2048
++#define IT_SCALING_TABLE_SIZE 224
+ 
+ /* UVD decoder representation */
+ struct ruvd_decoder {
+@@ -65,6 +66,7 @@ struct ruvd_decoder {
+ 	ruvd_set_dtb			set_dtb;
+ 
+ 	unsigned			stream_handle;
++	unsigned			stream_type;
+ 	unsigned			frame_number;
+ 
+ 	struct pipe_screen		*screen;
+@@ -73,9 +75,10 @@ struct ruvd_decoder {
+ 
+ 	unsigned			cur_buffer;
+ 
+-	struct rvid_buffer		msg_fb_buffers[NUM_BUFFERS];
++	struct rvid_buffer		msg_fb_it_buffers[NUM_BUFFERS];
+ 	struct ruvd_msg			*msg;
+ 	uint32_t			*fb;
++	uint8_t				*it;
+ 
+ 	struct rvid_buffer		bs_buffers[NUM_BUFFERS];
+ 	void*				bs_ptr;
+@@ -121,14 +124,14 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
+ 	set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
+ }
+ 
+-/* map the next available message/feedback buffer */
+-static void map_msg_fb_buf(struct ruvd_decoder *dec)
++/* map the next available message/feedback/itscaling buffer */
++static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
+ {
+ 	struct rvid_buffer* buf;
+ 	uint8_t *ptr;
+ 
+ 	/* grab the current message/feedback buffer */
+-	buf = &dec->msg_fb_buffers[dec->cur_buffer];
++	buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
+ 
+ 	/* and map it for CPU access */
+ 	ptr = dec->ws->buffer_map(buf->res->cs_buf, dec->cs, PIPE_TRANSFER_WRITE);
+@@ -136,6 +139,8 @@ static void map_msg_fb_buf(struct ruvd_decoder *dec)
+ 	/* calc buffer offsets */
+ 	dec->msg = (struct ruvd_msg *)ptr;
+ 	dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
++	if (dec->stream_type == RUVD_CODEC_H264_PERF)
++		dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
+ }
+ 
+ /* unmap and send a message command to the VCPU */
+@@ -148,12 +153,14 @@ static void send_msg_buf(struct ruvd_decoder *dec)
+ 		return;
+ 
+ 	/* grab the current message buffer */
+-	buf = &dec->msg_fb_buffers[dec->cur_buffer];
++	buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
+ 
+ 	/* unmap the buffer */
+ 	dec->ws->buffer_unmap(buf->res->cs_buf);
+ 	dec->msg = NULL;
+ 	dec->fb = NULL;
++	if (dec->stream_type == RUVD_CODEC_H264_PERF)
++		dec->it = NULL;
+ 
+ 	/* and send it to the hardware */
+ 	send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->cs_buf, 0,
+@@ -168,11 +175,12 @@ static void next_buffer(struct ruvd_decoder *dec)
+ }
+ 
+ /* convert the profile into something UVD understands */
+-static uint32_t profile2stream_type(enum pipe_video_profile profile)
++static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
+ {
+-	switch (u_reduce_video_profile(profile)) {
++	switch (u_reduce_video_profile(dec->base.profile)) {
+ 	case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+-		return RUVD_CODEC_H264;
++		return (family >= CHIP_TONGA) ?
++			RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
+ 
+ 	case PIPE_VIDEO_FORMAT_VC1:
+ 		return RUVD_CODEC_VC1;
+@@ -565,7 +573,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
+ 
+ 	assert(decoder);
+ 
+-	map_msg_fb_buf(dec);
++	map_msg_fb_it_buf(dec);
+ 	memset(dec->msg, 0, sizeof(*dec->msg));
+ 	dec->msg->size = sizeof(*dec->msg);
+ 	dec->msg->msg_type = RUVD_MSG_DESTROY;
+@@ -577,7 +585,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
+ 	dec->ws->cs_destroy(dec->cs);
+ 
+ 	for (i = 0; i < NUM_BUFFERS; ++i) {
+-		rvid_destroy_buffer(&dec->msg_fb_buffers[i]);
++		rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
+ 		rvid_destroy_buffer(&dec->bs_buffers[i]);
+ 	}
+ 
+@@ -679,7 +687,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
+ {
+ 	struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
+ 	struct radeon_winsys_cs_handle *dt;
+-	struct rvid_buffer *msg_fb_buf, *bs_buf;
++	struct rvid_buffer *msg_fb_it_buf, *bs_buf;
+ 	unsigned bs_size;
+ 
+ 	assert(decoder);
+@@ -687,32 +695,37 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
+ 	if (!dec->bs_ptr)
+ 		return;
+ 
+-	msg_fb_buf = &dec->msg_fb_buffers[dec->cur_buffer];
++	msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
+ 	bs_buf = &dec->bs_buffers[dec->cur_buffer];
+ 
+ 	bs_size = align(dec->bs_size, 128);
+ 	memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
+ 	dec->ws->buffer_unmap(bs_buf->res->cs_buf);
+ 
+-	map_msg_fb_buf(dec);
++	map_msg_fb_it_buf(dec);
+ 	dec->msg->size = sizeof(*dec->msg);
+ 	dec->msg->msg_type = RUVD_MSG_DECODE;
+ 	dec->msg->stream_handle = dec->stream_handle;
+ 	dec->msg->status_report_feedback_number = dec->frame_number;
+ 
+-	dec->msg->body.decode.stream_type = profile2stream_type(dec->base.profile);
++	dec->msg->body.decode.stream_type = dec->stream_type;
+ 	dec->msg->body.decode.decode_flags = 0x1;
+ 	dec->msg->body.decode.width_in_samples = dec->base.width;
+ 	dec->msg->body.decode.height_in_samples = dec->base.height;
+ 
+ 	dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
+ 	dec->msg->body.decode.bsd_size = bs_size;
++	dec->msg->body.decode.db_pitch = dec->base.width;
+ 
+ 	dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
+ 
+ 	switch (u_reduce_video_profile(picture->profile)) {
+ 	case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+ 		dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
++		if (dec->stream_type == RUVD_CODEC_H264_PERF) {
++			memcpy(dec->it, dec->msg->body.decode.codec.h264.scaling_list_4x4, 6*16);
++			memcpy((dec->it + 96), dec->msg->body.decode.codec.h264.scaling_list_8x8, 2*64);
++		}
+ 		break;
+ 
+ 	case PIPE_VIDEO_FORMAT_VC1:
+@@ -746,8 +759,11 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
+ 		 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
+ 	send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
+ 		 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
+-	send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_buf->res->cs_buf,
++	send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->cs_buf,
+ 		 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
++	if (dec->stream_type == RUVD_CODEC_H264_PERF)
++		send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->cs_buf,
++			 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
+ 	set_reg(dec, RUVD_ENGINE_CNTL, 1);
+ 
+ 	flush(dec);
+@@ -815,6 +831,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 	dec->base.end_frame = ruvd_end_frame;
+ 	dec->base.flush = ruvd_flush;
+ 
++	dec->stream_type = profile2stream_type(dec, info.family);
+ 	dec->set_dtb = set_dtb;
+ 	dec->stream_handle = rvid_alloc_stream_handle();
+ 	dec->screen = context->screen;
+@@ -827,10 +844,12 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 
+ 	bs_buf_size = width * height * 512 / (16 * 16);
+ 	for (i = 0; i < NUM_BUFFERS; ++i) {
+-		unsigned msg_fb_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
++		unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
+ 		STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
+-		if (!rvid_create_buffer(dec->screen, &dec->msg_fb_buffers[i],
+-					msg_fb_size, PIPE_USAGE_STAGING)) {
++		if (dec->stream_type == RUVD_CODEC_H264_PERF)
++			msg_fb_it_size += IT_SCALING_TABLE_SIZE;
++		if (!rvid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i],
++					msg_fb_it_size, PIPE_USAGE_STAGING)) {
+ 			RVID_ERR("Can't allocated message buffers.\n");
+ 			goto error;
+ 		}
+@@ -841,7 +860,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 			goto error;
+ 		}
+ 
+-		rvid_clear_buffer(context, &dec->msg_fb_buffers[i]);
++		rvid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
+ 		rvid_clear_buffer(context, &dec->bs_buffers[i]);
+ 	}
+ 
+@@ -852,11 +871,11 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 
+ 	rvid_clear_buffer(context, &dec->dpb);
+ 
+-	map_msg_fb_buf(dec);
++	map_msg_fb_it_buf(dec);
+ 	dec->msg->size = sizeof(*dec->msg);
+ 	dec->msg->msg_type = RUVD_MSG_CREATE;
+ 	dec->msg->stream_handle = dec->stream_handle;
+-	dec->msg->body.create.stream_type = profile2stream_type(dec->base.profile);
++	dec->msg->body.create.stream_type = dec->stream_type;
+ 	dec->msg->body.create.width_in_samples = dec->base.width;
+ 	dec->msg->body.create.height_in_samples = dec->base.height;
+ 	dec->msg->body.create.dpb_size = dec->dpb.res->buf->size;
+@@ -870,7 +889,7 @@ error:
+ 	if (dec->cs) dec->ws->cs_destroy(dec->cs);
+ 
+ 	for (i = 0; i < NUM_BUFFERS; ++i) {
+-		rvid_destroy_buffer(&dec->msg_fb_buffers[i]);
++		rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
+ 		rvid_destroy_buffer(&dec->bs_buffers[i]);
+ 	}
+ 
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
+index 7442865..5b6c65c 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.h
++++ b/src/gallium/drivers/radeon/radeon_uvd.h
+@@ -62,6 +62,7 @@
+ #define RUVD_CMD_DECODING_TARGET_BUFFER	0x00000002
+ #define RUVD_CMD_FEEDBACK_BUFFER	0x00000003
+ #define RUVD_CMD_BITSTREAM_BUFFER	0x00000100
++#define RUVD_CMD_ITSCALING_TABLE_BUFFER	0x00000204
+ 
+ /* UVD message types */
+ #define RUVD_MSG_CREATE		0
+@@ -73,6 +74,7 @@
+ #define RUVD_CODEC_VC1		0x00000001
+ #define RUVD_CODEC_MPEG2	0x00000003
+ #define RUVD_CODEC_MPEG4	0x00000004
++#define RUVD_CODEC_H264_PERF	0x00000007
+ 
+ /* UVD decode target buffer tiling mode */
+ #define RUVD_TILE_LINEAR	0x00000000
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0017-radeon-vce-make-firmware-check-compatible-with-new-f.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0017-radeon-vce-make-firmware-check-compatible-with-new-f.patch
new file mode 100644
index 00000000..956a722a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0017-radeon-vce-make-firmware-check-compatible-with-new-f.patch
@@ -0,0 +1,29 @@
+From d2bfa3f43f6a8f905cf3115371bb82aa347315b7 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 6 Feb 2015 12:58:23 -0500
+Subject: [PATCH 17/29] radeon/vce: make firmware check compatible with new
+ firmware
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_vce.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
+index d1495a2..b8b35b3 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.c
++++ b/src/gallium/drivers/radeon/radeon_vce.c
+@@ -428,7 +428,7 @@ error:
+  */
+ bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
+ {
+-	return rscreen->info.vce_fw_version == ((40 << 24) | (2 << 16) | (2 << 8));
++	return rscreen->info.vce_fw_version >= ((40 << 24) | (2 << 16) | (2 << 8));
+ }
+ 
+ /**
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0018-radeon-vce-adapt-new-firmware-interface-changes.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0018-radeon-vce-adapt-new-firmware-interface-changes.patch
new file mode 100644
index 00000000..915d6cab
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0018-radeon-vce-adapt-new-firmware-interface-changes.patch
@@ -0,0 +1,89 @@
+From b0624db0423f37e45038aa163f9699a4453b8945 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Wed, 11 Feb 2015 15:22:21 -0500
+Subject: [PATCH 18/29] radeon/vce: adapt new firmware interface changes
+
+v2: make this also compatible with original released firmware
+v3: rebase by Marek
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_vce.c        |  1 +
+ src/gallium/drivers/radeon/radeon_vce.h        |  1 +
+ src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 13 +++++++++++--
+ 3 files changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
+index b8b35b3..d5ae26d 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.c
++++ b/src/gallium/drivers/radeon/radeon_vce.c
+@@ -353,6 +353,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+ 	if (!enc)
+ 		return NULL;
+ 
++	enc->fw_ver = rscreen->info.vce_fw_version;
+ 	if (rscreen->info.drm_major == 3)
+ 		enc->use_vm = true;
+ 	if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
+diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
+index 67ba333..7d37320 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.h
++++ b/src/gallium/drivers/radeon/radeon_vce.h
+@@ -100,6 +100,7 @@ struct rvce_encoder {
+ 	struct rvid_buffer		cpb;
+ 	struct pipe_h264_enc_picture_desc pic;
+ 	bool				use_vm;
++	unsigned			fw_ver;
+ 	bool				use_vui;
+ };
+ 
+diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+index 1e7f278..f1f4cce 100644
+--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
++++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+@@ -44,6 +44,8 @@
+ #include "radeon_video.h"
+ #include "radeon_vce.h"
+ 
++#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
++
+ static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
+ 
+ static struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
+@@ -145,6 +147,10 @@ static void rate_control(struct rvce_encoder *enc)
+ 	RVCE_CS(0x00000000); // encBPicsDeltaQP
+ 	RVCE_CS(0x00000000); // encReferenceBPicsDeltaQP
+ 	RVCE_CS(0x00000000); // encRateControlReInitDisable
++	if (enc->fw_ver > FW_40_2_2) {
++		RVCE_CS(0x00000000); // encLCVBRInitQPFlag
++		RVCE_CS(0x00000000); // encLCVBRSATDBasedNonlinearBitBudgetFlag
++	}
+ 	RVCE_END();
+ }
+ 
+@@ -314,7 +320,10 @@ static void encode(struct rvce_encoder *enc)
+ 	RVCE_END();
+ 
+ 	RVCE_BEGIN(0x03000001); // encode
+-	RVCE_CS(0x00000000); // insertHeaders
++	if ((enc->fw_ver > FW_40_2_2) && (!enc->pic.frame_num))
++		RVCE_CS(0x00000011); // insertHeaders
++	else
++		RVCE_CS(0x00000000); // insertHeaders
+ 	RVCE_CS(0x00000000); // pictureStructure
+ 	RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
+ 	RVCE_CS(0x00000000); // forceRefreshMap
+@@ -328,7 +337,7 @@ static void encode(struct rvce_encoder *enc)
+ 	RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
+ 	RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
+ 	RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+-	RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode
++	RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
+ 	RVCE_CS(0x00000000); // encInputPicTileConfig
+ 	RVCE_CS(enc->pic.picture_type); // encPicType
+ 	RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0019-radeon-video-add-4K-support-for-decode-encode-parame.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0019-radeon-video-add-4K-support-for-decode-encode-parame.patch
new file mode 100644
index 00000000..66670644
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0019-radeon-video-add-4K-support-for-decode-encode-parame.patch
@@ -0,0 +1,48 @@
+From 94b8d8d7ec638b16d62a1bddb060925ced9f50b7 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 9 Mar 2015 16:24:48 -0400
+Subject: [PATCH 19/29] radeon/video: add 4K support for decode/encode
+ parameters
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_video.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
+index 826e076..65949fb 100644
+--- a/src/gallium/drivers/radeon/radeon_video.c
++++ b/src/gallium/drivers/radeon/radeon_video.c
+@@ -214,9 +214,9 @@ int rvid_get_video_param(struct pipe_screen *screen,
+ 	        case PIPE_VIDEO_CAP_NPOT_TEXTURES:
+         	        return 1;
+ 	        case PIPE_VIDEO_CAP_MAX_WIDTH:
+-        	        return 2048;
++			return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
+ 	        case PIPE_VIDEO_CAP_MAX_HEIGHT:
+-        	        return 1152;
++			return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
+ 	        case PIPE_VIDEO_CAP_PREFERED_FORMAT:
+         	        return PIPE_FORMAT_NV12;
+ 	        case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
+@@ -268,9 +268,9 @@ int rvid_get_video_param(struct pipe_screen *screen,
+ 	case PIPE_VIDEO_CAP_NPOT_TEXTURES:
+ 		return 1;
+ 	case PIPE_VIDEO_CAP_MAX_WIDTH:
+-		return 2048;
++		return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
+ 	case PIPE_VIDEO_CAP_MAX_HEIGHT:
+-		return 1152;
++		return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
+ 	case PIPE_VIDEO_CAP_PREFERED_FORMAT:
+ 		return PIPE_FORMAT_NV12;
+ 	case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0020-radeon-uvd-recalculate-dbp-buffer-size.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0020-radeon-uvd-recalculate-dbp-buffer-size.patch
new file mode 100644
index 00000000..4dfbfcc9
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0020-radeon-uvd-recalculate-dbp-buffer-size.patch
@@ -0,0 +1,145 @@
+From f42b0415fa5e9a4525d378c1c9c71a3934fd2a3a Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 12 Mar 2015 16:13:44 -0400
+Subject: [PATCH 20/29] radeon/uvd: recalculate dbp buffer size
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_uvd.c | 81 ++++++++++++++++++++++++---------
+ 1 file changed, 59 insertions(+), 22 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
+index b0bfb3b..38eb3d1 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.c
++++ b/src/gallium/drivers/radeon/radeon_uvd.c
+@@ -198,16 +198,16 @@ static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
+ }
+ 
+ /* calculate size of reference picture buffer */
+-static unsigned calc_dpb_size(const struct pipe_video_codec *templ)
++static unsigned calc_dpb_size(struct ruvd_decoder *dec)
+ {
+ 	unsigned width_in_mb, height_in_mb, image_size, dpb_size;
+ 
+ 	// always align them to MB size for dpb calculation
+-	unsigned width = align(templ->width, VL_MACROBLOCK_WIDTH);
+-	unsigned height = align(templ->height, VL_MACROBLOCK_HEIGHT);
++	unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
++	unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
+ 
+ 	// always one more for currently decoded picture
+-	unsigned max_references = templ->max_references + 1;
++	unsigned max_references = dec->base.max_references + 1;
+ 
+ 	// aligned size of a single frame
+ 	image_size = width * height;
+@@ -218,20 +218,57 @@ static unsigned calc_dpb_size(const struct pipe_video_codec *templ)
+ 	width_in_mb = width / VL_MACROBLOCK_WIDTH;
+ 	height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
+ 
+-	switch (u_reduce_video_profile(templ->profile)) {
+-	case PIPE_VIDEO_FORMAT_MPEG4_AVC:
+-		// the firmware seems to allways assume a minimum of ref frames
+-		max_references = MAX2(NUM_H264_REFS, max_references);
+-
+-		// reference picture buffer
+-		dpb_size = image_size * max_references;
+-
+-		// macroblock context buffer
+-		dpb_size += width_in_mb * height_in_mb * max_references * 192;
+-
+-		// IT surface buffer
+-		dpb_size += width_in_mb * height_in_mb * 32;
++	switch (u_reduce_video_profile(dec->base.profile)) {
++	case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
++		if (!dec->use_legacy) {
++			unsigned fs_in_mb = width_in_mb * height_in_mb;
++			unsigned alignment = 64, num_dpb_buffer;
++
++			if (dec->stream_type == RUVD_CODEC_H264_PERF)
++				alignment = 256;
++			switch(dec->base.level) {
++			case 30:
++				num_dpb_buffer = 8100 / fs_in_mb;
++				break;
++			case 31:
++				num_dpb_buffer = 18000 / fs_in_mb;
++				break;
++			case 32:
++				num_dpb_buffer = 20480 / fs_in_mb;
++				break;
++			case 41:
++				num_dpb_buffer = 32768 / fs_in_mb;
++				break;
++			case 42:
++				num_dpb_buffer = 34816 / fs_in_mb;
++				break;
++			case 50:
++				num_dpb_buffer = 110400 / fs_in_mb;
++				break;
++			case 51:
++				num_dpb_buffer = 184320 / fs_in_mb;
++				break;
++			default:
++				num_dpb_buffer = 184320 / fs_in_mb;
++				break;
++			}
++			num_dpb_buffer++;
++			max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
++			dpb_size = image_size * max_references;
++			dpb_size += max_references * align(width_in_mb * height_in_mb  * 192, alignment);
++			dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
++		} else {
++			// the firmware seems to allways assume a minimum of ref frames
++			max_references = MAX2(NUM_H264_REFS, max_references);
++			// reference picture buffer
++			dpb_size = image_size * max_references;
++			// macroblock context buffer
++			dpb_size += width_in_mb * height_in_mb * max_references * 192;
++			// IT surface buffer
++			dpb_size += width_in_mb * height_in_mb * 32;
++		}
+ 		break;
++	}
+ 
+ 	case PIPE_VIDEO_FORMAT_VC1:
+ 		// the firmware seems to allways assume a minimum of ref frames
+@@ -303,10 +340,8 @@ static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_
+ 		assert(0);
+ 		break;
+ 	}
+-	if (((dec->base.width * dec->base.height) >> 8) <= 1620)
+-		result.level = 30;
+-	else
+-		result.level = 41;
++
++	result.level = dec->base.level;
+ 
+ 	result.sps_info_flags = 0;
+ 	result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
+@@ -785,7 +820,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 					     ruvd_set_dtb set_dtb)
+ {
+ 	struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
+-	unsigned dpb_size = calc_dpb_size(templ);
++	unsigned dpb_size;
+ 	unsigned width = templ->width, height = templ->height;
+ 	unsigned bs_buf_size;
+ 	struct radeon_info info;
+@@ -864,6 +899,8 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+ 		rvid_clear_buffer(context, &dec->bs_buffers[i]);
+ 	}
+ 
++	dpb_size = calc_dpb_size(dec);
++
+ 	if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
+ 		RVID_ERR("Can't allocated dpb.\n");
+ 		goto error;
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0021-radeon-uvd-make-30M-as-minimum-for-MPEG4-dpb-buffer-.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0021-radeon-uvd-make-30M-as-minimum-for-MPEG4-dpb-buffer-.patch
new file mode 100644
index 00000000..3873845d
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0021-radeon-uvd-make-30M-as-minimum-for-MPEG4-dpb-buffer-.patch
@@ -0,0 +1,32 @@
+From 2ff165c0f33193fd9ae6ae6f373c0416b14d8584 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 12 Mar 2015 16:24:57 -0400
+Subject: [PATCH 21/29] radeon/uvd: make 30M as minimum for MPEG4 dpb buffer
+ size
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_uvd.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
+index 38eb3d1..a712907 100644
+--- a/src/gallium/drivers/radeon/radeon_uvd.c
++++ b/src/gallium/drivers/radeon/radeon_uvd.c
+@@ -304,6 +304,8 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
+ 
+ 		// IT surface buffer
+ 		dpb_size += align(width_in_mb * height_in_mb * 32, 64);
++
++		dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
+ 		break;
+ 
+ 	default:
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0022-radeon-vce-implement-VCE-two-pipe-support.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0022-radeon-vce-implement-VCE-two-pipe-support.patch
new file mode 100644
index 00000000..98feea2e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0022-radeon-vce-implement-VCE-two-pipe-support.patch
@@ -0,0 +1,96 @@
+From 411aabe76ae9621510d038b84e755fe583b54a7b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Wed, 15 Apr 2015 12:36:32 -0400
+Subject: [PATCH 22/29] radeon/vce: implement VCE two pipe support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: rebase by Marek
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeon/radeon_vce.c        |  5 +++++
+ src/gallium/drivers/radeon/radeon_vce.h        |  4 ++++
+ src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 17 +++++++++++++++++
+ 3 files changed, 26 insertions(+)
+
+diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
+index d5ae26d..79b0909 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.c
++++ b/src/gallium/drivers/radeon/radeon_vce.c
+@@ -358,6 +358,8 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+ 		enc->use_vm = true;
+ 	if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
+ 		enc->use_vui = true;
++	if (rscreen->info.family >= CHIP_TONGA)
++		enc->use_2p = true;
+ 
+ 	enc->base = *templ;
+ 	enc->base.context = context;
+@@ -397,6 +399,9 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+ 	cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
+ 	cpb_size = cpb_size * 3 / 2;
+ 	cpb_size = cpb_size * enc->cpb_num;
++	if (enc->use_2p)
++		cpb_size +=  RVCE_MAX_AUX_BUFFER_NUM *
++			RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
+ 	tmp_buf->destroy(tmp_buf);
+ 	if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
+ 		RVID_ERR("Can't create CPB buffer.\n");
+diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
+index 7d37320..4d07204 100644
+--- a/src/gallium/drivers/radeon/radeon_vce.h
++++ b/src/gallium/drivers/radeon/radeon_vce.h
+@@ -43,6 +43,9 @@
+ #define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
+ #define RVCE_END() *begin = (&enc->cs->buf[enc->cs->cdw] - begin) * 4; }
+ 
++#define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
++#define RVCE_MAX_AUX_BUFFER_NUM 4
++
+ struct r600_common_screen;
+ 
+ /* driver dependent callback */
+@@ -102,6 +105,7 @@ struct rvce_encoder {
+ 	bool				use_vm;
+ 	unsigned			fw_ver;
+ 	bool				use_vui;
++	bool				use_2p;
+ };
+ 
+ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
+diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+index f1f4cce..970d572 100644
+--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
++++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+@@ -319,6 +319,23 @@ static void encode(struct rvce_encoder *enc)
+ 	RVCE_CS(enc->bs_size); // videoBitstreamRingSize
+ 	RVCE_END();
+ 
++	if (enc->use_2p) {
++		unsigned aux_offset = enc->cpb.res->buf->size -
++			RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
++		RVCE_BEGIN(0x05000002); // auxiliary buffer
++		for (i = 0; i < 4; ++i) {
++			RVCE_CS(aux_offset);
++			aux_offset += RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
++		}
++		for (i = 0; i < 4; ++i)
++			RVCE_CS(0x00000000);
++		for (i = 0; i < 4; ++i)
++			RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE);
++		for (i = 0; i < 4; ++i)
++			RVCE_CS(0x00000000);
++		RVCE_END();
++	}
++
+ 	RVCE_BEGIN(0x03000001); // encode
+ 	if ((enc->fw_ver > FW_40_2_2) && (!enc->pic.frame_num))
+ 		RVCE_CS(0x00000011); // insertHeaders
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0023-radeonsi-add-new-VI-PCI-IDs.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0023-radeonsi-add-new-VI-PCI-IDs.patch
new file mode 100644
index 00000000..00762071
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0023-radeonsi-add-new-VI-PCI-IDs.patch
@@ -0,0 +1,41 @@
+From a8ff4160a2bd41c2d59681fb58e0422c60e26778 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 16 Apr 2015 22:59:41 +0200
+Subject: [PATCH 23/29] radeonsi: add new VI PCI IDs
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ include/pci_ids/radeonsi_pci_ids.h | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h
+index 571e863..ca81f76 100644
+--- a/include/pci_ids/radeonsi_pci_ids.h
++++ b/include/pci_ids/radeonsi_pci_ids.h
+@@ -155,3 +155,23 @@ CHIPSET(0x67B8, HAWAII_67B8, HAWAII)
+ CHIPSET(0x67B9, HAWAII_67B9, HAWAII)
+ CHIPSET(0x67BA, HAWAII_67BA, HAWAII)
+ CHIPSET(0x67BE, HAWAII_67BE, HAWAII)
++
++CHIPSET(0x6900, ICELAND_, ICELAND)
++CHIPSET(0x6901, ICELAND_, ICELAND)
++CHIPSET(0x6902, ICELAND_, ICELAND)
++CHIPSET(0x6903, ICELAND_, ICELAND)
++CHIPSET(0x6907, ICELAND_, ICELAND)
++
++CHIPSET(0x6920, TONGA_, TONGA)
++CHIPSET(0x6921, TONGA_, TONGA)
++CHIPSET(0x6928, TONGA_, TONGA)
++CHIPSET(0x692B, TONGA_, TONGA)
++CHIPSET(0x692F, TONGA_, TONGA)
++CHIPSET(0x6938, TONGA_, TONGA)
++CHIPSET(0x6939, TONGA_, TONGA)
++
++CHIPSET(0x9870, CARRIZO_, CARRIZO)
++CHIPSET(0x9874, CARRIZO_, CARRIZO)
++CHIPSET(0x9875, CARRIZO_, CARRIZO)
++CHIPSET(0x9876, CARRIZO_, CARRIZO)
++CHIPSET(0x9877, CARRIZO_, CARRIZO)
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0024-gallium-util-get-h264-level-based-on-number-of-max-r.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0024-gallium-util-get-h264-level-based-on-number-of-max-r.patch
new file mode 100644
index 00000000..3a4a63d8
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0024-gallium-util-get-h264-level-based-on-number-of-max-r.patch
@@ -0,0 +1,76 @@
+From 4e9dbaaafed23588945a09617796baa91194dc57 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 12 Mar 2015 14:01:52 -0400
+Subject: [PATCH 24/29] gallium/util: get h264 level based on number of max
+ references and resolution
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: add commments for limitation of max references numbers,
+and what the caculation is based
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/auxiliary/util/u_video.h | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/src/gallium/auxiliary/util/u_video.h b/src/gallium/auxiliary/util/u_video.h
+index 45b2d6e..b4743d1 100644
+--- a/src/gallium/auxiliary/util/u_video.h
++++ b/src/gallium/auxiliary/util/u_video.h
+@@ -38,6 +38,7 @@ extern "C" {
+ /* u_reduce_video_profile() needs these */
+ #include "pipe/p_compiler.h"
+ #include "util/u_debug.h"
++#include "util/u_math.h"
+ 
+ static INLINE enum pipe_video_format
+ u_reduce_video_profile(enum pipe_video_profile profile)
+@@ -146,6 +147,41 @@ u_copy_swap422_packed(void *const *destination_data,
+    }
+ }
+ 
++static INLINE uint32_t
++u_get_h264_level(uint32_t width, uint32_t height, uint32_t *max_reference)
++{
++   uint32_t max_dpb_mbs;
++
++   width = align(width, 16);
++   height = align(height, 16);
++
++   /* Max references will be used for caculation of number of DPB buffers
++      in the UVD driver, limitation of max references is 16. Some client
++      like mpv application for VA-API, it requires references more than that,
++      so we have to set max of references to 16 here. */
++   *max_reference = MIN2(*max_reference, 16);
++   max_dpb_mbs = (width / 16) * (height / 16) * *max_reference;
++
++   /* The calculation is based on "Decoded picture buffering" section
++      from http://en.wikipedia.org/wiki/H.264/MPEG-4_AVC */
++   if (max_dpb_mbs <= 8100)
++      return 30;
++   else if (max_dpb_mbs <= 18000)
++      return 31;
++   else if (max_dpb_mbs <= 20480)
++      return 32;
++   else if (max_dpb_mbs <= 32768)
++      return 41;
++   else if (max_dpb_mbs <= 34816)
++      return 42;
++   else if (max_dpb_mbs <= 110400)
++      return 50;
++   else if (max_dpb_mbs <= 184320)
++      return 51;
++   else
++      return 52;
++}
++
+ #ifdef __cplusplus
+ }
+ #endif
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0025-st-vdpau-add-h264-decoder-level-support.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0025-st-vdpau-add-h264-decoder-level-support.patch
new file mode 100644
index 00000000..729d11cc
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0025-st-vdpau-add-h264-decoder-level-support.patch
@@ -0,0 +1,34 @@
+From 2ccc95646ab8c004b0073cc6f01f9359ddc495a2 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 12 Mar 2015 14:09:49 -0400
+Subject: [PATCH 25/29] st/vdpau: add h264 decoder level support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/state_trackers/vdpau/decode.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/gallium/state_trackers/vdpau/decode.c b/src/gallium/state_trackers/vdpau/decode.c
+index 767d311..0634ba7 100644
+--- a/src/gallium/state_trackers/vdpau/decode.c
++++ b/src/gallium/state_trackers/vdpau/decode.c
+@@ -118,6 +118,11 @@ vlVdpDecoderCreate(VdpDevice device,
+    templat.height = height;
+    templat.max_references = max_references;
+ 
++   if (u_reduce_video_profile(templat.profile) ==
++       PIPE_VIDEO_FORMAT_MPEG4_AVC)
++      templat.level = u_get_h264_level(templat.width, templat.height,
++                            &templat.max_references);
++
+    vldecoder->decoder = pipe->create_video_codec(pipe, &templat);
+ 
+    if (!vldecoder->decoder) {
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0026-st-omx-dec-separate-create_video_codec-to-different-.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0026-st-omx-dec-separate-create_video_codec-to-different-.patch
new file mode 100644
index 00000000..6bd9c12e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0026-st-omx-dec-separate-create_video_codec-to-different-.patch
@@ -0,0 +1,123 @@
+From 2261e94a5b6a67ec9142cd3c71d824fec35b70c2 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 13 Mar 2015 12:25:42 -0400
+Subject: [PATCH 26/29] st/omx/dec: separate create_video_codec to different
+ codecs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: get frame size from port info
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/state_trackers/omx/vid_dec.c        | 18 ------------------
+ src/gallium/state_trackers/omx/vid_dec.h        |  1 +
+ src/gallium/state_trackers/omx/vid_dec_h264.c   | 15 +++++++++++++++
+ src/gallium/state_trackers/omx/vid_dec_mpeg12.c | 14 ++++++++++++++
+ 4 files changed, 30 insertions(+), 18 deletions(-)
+
+diff --git a/src/gallium/state_trackers/omx/vid_dec.c b/src/gallium/state_trackers/omx/vid_dec.c
+index 13f4f55..9e7e7ba 100644
+--- a/src/gallium/state_trackers/omx/vid_dec.c
++++ b/src/gallium/state_trackers/omx/vid_dec.c
+@@ -44,8 +44,6 @@
+ #include <bellagio/omxcore.h>
+ #endif
+ 
+-#include <bellagio/omx_base_video_port.h>
+-
+ #include "pipe/p_screen.h"
+ #include "pipe/p_video_codec.h"
+ #include "util/u_memory.h"
+@@ -364,22 +362,6 @@ static OMX_ERRORTYPE vid_dec_MessageHandler(OMX_COMPONENTTYPE* comp, internalReq
+ 
+    if (msg->messageType == OMX_CommandStateSet) {
+       if ((msg->messageParam == OMX_StateIdle ) && (priv->state == OMX_StateLoaded)) {
+-
+-         struct pipe_video_codec templat = {};
+-         omx_base_video_PortType *port;
+-
+-         port = (omx_base_video_PortType *)priv->ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
+-
+-         templat.profile = priv->profile;
+-         templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
+-         templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
+-         templat.width = port->sPortParam.format.video.nFrameWidth;
+-         templat.height = port->sPortParam.format.video.nFrameHeight;
+-         templat.max_references = 2;
+-         templat.expect_chunked_decode = true;
+-
+-         priv->codec = priv->pipe->create_video_codec(priv->pipe, &templat);
+-
+          if (priv->profile == PIPE_VIDEO_PROFILE_MPEG2_MAIN)
+             vid_dec_mpeg12_Init(priv);
+          else if (priv->profile == PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH)
+diff --git a/src/gallium/state_trackers/omx/vid_dec.h b/src/gallium/state_trackers/omx/vid_dec.h
+index 9acf872..1c51f9c 100644
+--- a/src/gallium/state_trackers/omx/vid_dec.h
++++ b/src/gallium/state_trackers/omx/vid_dec.h
+@@ -44,6 +44,7 @@
+ 
+ #include <bellagio/st_static_component_loader.h>
+ #include <bellagio/omx_base_filter.h>
++#include <bellagio/omx_base_video_port.h>
+ 
+ #include "pipe/p_video_state.h"
+ #include "state_tracker/drm_driver.h"
+diff --git a/src/gallium/state_trackers/omx/vid_dec_h264.c b/src/gallium/state_trackers/omx/vid_dec_h264.c
+index e01e873..7c90dee 100644
+--- a/src/gallium/state_trackers/omx/vid_dec_h264.c
++++ b/src/gallium/state_trackers/omx/vid_dec_h264.c
+@@ -105,6 +105,21 @@ static void vid_dec_h264_BeginFrame(vid_dec_PrivateType *priv)
+ 
+    priv->picture.h264.num_ref_frames = priv->picture.h264.pps->sps->max_num_ref_frames;
+ 
++   if (!priv->codec) {
++      struct pipe_video_codec templat = {};
++      omx_base_video_PortType *port;
++
++      port = (omx_base_video_PortType *)priv->ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
++      templat.profile = priv->profile;
++      templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
++      templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
++      templat.max_references = 2;
++      templat.expect_chunked_decode = true;
++      templat.width = port->sPortParam.format.video.nFrameWidth;
++      templat.height = port->sPortParam.format.video.nFrameHeight;
++
++      priv->codec = priv->pipe->create_video_codec(priv->pipe, &templat);
++   }
+    priv->codec->begin_frame(priv->codec, priv->target, &priv->picture.base);
+    priv->frame_started = true;
+ }
+diff --git a/src/gallium/state_trackers/omx/vid_dec_mpeg12.c b/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
+index de4c69a..bef83ec 100644
+--- a/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
++++ b/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
+@@ -65,6 +65,20 @@ static struct pipe_video_buffer *vid_dec_mpeg12_Flush(vid_dec_PrivateType *priv)
+ 
+ void vid_dec_mpeg12_Init(vid_dec_PrivateType *priv)
+ {
++   struct pipe_video_codec templat = {};
++   omx_base_video_PortType *port;
++
++   port = (omx_base_video_PortType *)priv->ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
++   templat.profile = priv->profile;
++   templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
++   templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
++   templat.max_references = 2;
++   templat.expect_chunked_decode = true;
++   templat.width = port->sPortParam.format.video.nFrameWidth;
++   templat.height = port->sPortParam.format.video.nFrameHeight;
++
++   priv->codec = priv->pipe->create_video_codec(priv->pipe, &templat);
++
+    priv->picture.base.profile = PIPE_VIDEO_PROFILE_MPEG2_MAIN;
+    priv->picture.mpeg12.intra_matrix = default_intra_matrix;
+    priv->picture.mpeg12.non_intra_matrix = default_non_intra_matrix;
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0027-vl-add-level-idc-in-sps.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0027-vl-add-level-idc-in-sps.patch
new file mode 100644
index 00000000..e084140c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0027-vl-add-level-idc-in-sps.patch
@@ -0,0 +1,30 @@
+From 6804e81546f265be09aa3d496ec6ac2fb4a1665e Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 16 Mar 2015 15:06:30 -0400
+Subject: [PATCH 27/29] vl: add level idc in sps
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/include/pipe/p_video_state.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/gallium/include/pipe/p_video_state.h b/src/gallium/include/pipe/p_video_state.h
+index 6621dbd..3713cd9 100644
+--- a/src/gallium/include/pipe/p_video_state.h
++++ b/src/gallium/include/pipe/p_video_state.h
+@@ -271,6 +271,7 @@ struct pipe_vc1_picture_desc
+ 
+ struct pipe_h264_sps
+ {
++   uint8_t  level_idc;
+    uint8_t  chroma_format_idc;
+    uint8_t  separate_colour_plane_flag;
+    uint8_t  bit_depth_luma_minus8;
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0028-st-omx-dec-add-h264-decoder-level-support.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0028-st-omx-dec-add-h264-decoder-level-support.patch
new file mode 100644
index 00000000..0b59004a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0028-st-omx-dec-add-h264-decoder-level-support.patch
@@ -0,0 +1,72 @@
+From fdf7e12f010fd7650b767f726cb27e62321e6573 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 13 Mar 2015 12:39:26 -0400
+Subject: [PATCH 28/29] st/omx/dec: add h264 decoder level support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: use sps level idc as level to driver
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/state_trackers/omx/vid_dec_h264.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/src/gallium/state_trackers/omx/vid_dec_h264.c b/src/gallium/state_trackers/omx/vid_dec_h264.c
+index 7c90dee..18d8803 100644
+--- a/src/gallium/state_trackers/omx/vid_dec_h264.c
++++ b/src/gallium/state_trackers/omx/vid_dec_h264.c
+@@ -33,6 +33,7 @@
+ 
+ #include "pipe/p_video_codec.h"
+ #include "util/u_memory.h"
++#include "util/u_video.h"
+ #include "vl/vl_rbsp.h"
+ 
+ #include "entrypoint.h"
+@@ -113,10 +114,11 @@ static void vid_dec_h264_BeginFrame(vid_dec_PrivateType *priv)
+       templat.profile = priv->profile;
+       templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
+       templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
+-      templat.max_references = 2;
++      templat.max_references = priv->picture.h264.num_ref_frames;
+       templat.expect_chunked_decode = true;
+       templat.width = port->sPortParam.format.video.nFrameWidth;
+       templat.height = port->sPortParam.format.video.nFrameHeight;
++      templat.level = priv->picture.h264.pps->sps->level_idc;
+ 
+       priv->codec = priv->pipe->create_video_codec(priv->pipe, &templat);
+    }
+@@ -239,7 +241,7 @@ static struct pipe_h264_sps *seq_parameter_set_id(vid_dec_PrivateType *priv, str
+ static void seq_parameter_set(vid_dec_PrivateType *priv, struct vl_rbsp *rbsp)
+ {
+    struct pipe_h264_sps *sps;
+-   unsigned profile_idc;
++   unsigned profile_idc, level_idc;
+    unsigned i;
+ 
+    /* Sequence parameter set */
+@@ -267,7 +269,7 @@ static void seq_parameter_set(vid_dec_PrivateType *priv, struct vl_rbsp *rbsp)
+    vl_rbsp_u(rbsp, 2);
+ 
+    /* level_idc */
+-   vl_rbsp_u(rbsp, 8);
++   level_idc = vl_rbsp_u(rbsp, 8);
+ 
+    sps = seq_parameter_set_id(priv, rbsp);
+    if (!sps)
+@@ -277,6 +279,8 @@ static void seq_parameter_set(vid_dec_PrivateType *priv, struct vl_rbsp *rbsp)
+    memset(sps->ScalingList4x4, 16, sizeof(sps->ScalingList4x4));
+    memset(sps->ScalingList8x8, 16, sizeof(sps->ScalingList8x8));
+ 
++   sps->level_idc = level_idc;
++
+    if (profile_idc == 100 || profile_idc == 110 || profile_idc == 122 || profile_idc == 244 ||
+        profile_idc == 44 || profile_idc == 83 || profile_idc == 86 || profile_idc == 118 ||
+        profile_idc == 128 || profile_idc == 138) {
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0029-st-va-add-h264-decoder-level-support.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0029-st-va-add-h264-decoder-level-support.patch
new file mode 100644
index 00000000..a06168a3
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0029-st-va-add-h264-decoder-level-support.patch
@@ -0,0 +1,34 @@
+From b1cb817f8f37d16aba15e610ca3a7df7aed23bcf Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 12 Mar 2015 14:29:21 -0400
+Subject: [PATCH 29/29] st/va: add h264 decoder level support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/state_trackers/va/context.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/gallium/state_trackers/va/context.c b/src/gallium/state_trackers/va/context.c
+index a7a55f9..0a733b3 100644
+--- a/src/gallium/state_trackers/va/context.c
++++ b/src/gallium/state_trackers/va/context.c
+@@ -167,6 +167,11 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID config_id, int picture_width,
+    templat.max_references = num_render_targets;
+    templat.expect_chunked_decode = true;
+ 
++   if (u_reduce_video_profile(templat.profile) ==
++       PIPE_VIDEO_FORMAT_MPEG4_AVC)
++      templat.level = u_get_h264_level(templat.width, templat.height,
++                            &templat.max_references);
++
+    context->decoder = drv->pipe->create_video_codec(drv->pipe, &templat);
+    if (!context->decoder) {
+       FREE(context);
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch
new file mode 100644
index 00000000..9ed40181
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch
@@ -0,0 +1,53 @@
+From 7f720fc229da2b75b60ddc9824f19ebd1acc42df Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Thu, 11 Jun 2015 14:07:38 +0530
+Subject: [PATCH 1/2] radeonsi: properly set the raster_config for KV
+
+This enables the second RB on asics that support it which
+should boost performance.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: mesa-stable@lists.freedesktop.org
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeonsi/si_state.c | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index b35fbd5..b3e77ec 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -3040,6 +3040,7 @@ si_write_harvested_raster_configs(struct si_context *sctx,
+ 
+ void si_init_config(struct si_context *sctx)
+ {
++	unsigned num_rb = sctx->screen->b.info.r600_num_backends;
+ 	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ 
+ 	if (pm4 == NULL)
+@@ -3097,14 +3098,17 @@ void si_init_config(struct si_context *sctx)
+ 			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ 			break;
+ 		case CHIP_KAVERI:
+-			/* XXX todo */
++			if (num_rb > 1)
++				si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002);
++			else
++				si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
++			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
++			break;
+ 		case CHIP_KABINI:
+-			/* XXX todo */
+ 		case CHIP_MULLINS:
+-			/* XXX todo */
+ 		default:
+-			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
+-			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
++			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
++			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ 			break;
+ 		}
+ 	} else {
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0031-radeonsi-properly-handler-raster_config-setup-on-CZ.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0031-radeonsi-properly-handler-raster_config-setup-on-CZ.patch
new file mode 100644
index 00000000..0b234494
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0031-radeonsi-properly-handler-raster_config-setup-on-CZ.patch
@@ -0,0 +1,32 @@
+From 111520d282ddabf9a26c640c67ac9e88341a3423 Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Thu, 11 Jun 2015 14:09:25 +0530
+Subject: [PATCH 2/2] radeonsi: properly handler raster_config setup on CZ
+
+Need to take into account the number of RBs.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ src/gallium/drivers/radeonsi/si_state.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
+index b3e77ec..f3c90e2 100644
+--- a/src/gallium/drivers/radeonsi/si_state.c
++++ b/src/gallium/drivers/radeonsi/si_state.c
+@@ -3093,10 +3093,10 @@ void si_init_config(struct si_context *sctx)
+ 			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002a);
+ 			break;
+ 		case CHIP_ICELAND:
+-		case CHIP_CARRIZO:
+ 			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002);
+ 			si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ 			break;
++		case CHIP_CARRIZO:
+ 		case CHIP_KAVERI:
+ 			if (num_rb > 1)
+ 				si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002);
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa_git.bbappend b/meta-amdfalconx86/recipes-graphics/mesa/mesa_git.bbappend
new file mode 100644
index 00000000..331d51eb
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa_git.bbappend
@@ -0,0 +1,54 @@
+FILESEXTRAPATHS_prepend_amdfalconx86 := "${THISDIR}/${PN}:"
+
+SRCREV_amdfalconx86 = "c1485f4b7d044724b3dbc1011f3c3a8a53132010"
+LIC_FILES_CHKSUM_amdfalconx86 = "file://docs/license.html;md5=6a23445982a7a972ac198e93cc1cb3de"
+PV_amdfalconx86 = "10.6.0+git${SRCPV}"
+DEPENDS_append_amdfalconx86 = " python-mako-native wayland libdrm nettle"
+GALLIUMDRIVERS_append_amdfalconx86 = ",r300,r600,radeonsi"
+GALLIUMDRIVERS_LLVM_amdfalconx86 = "r300,svga${@',${GALLIUMDRIVERS_LLVM33}' if ${GALLIUMDRIVERS_LLVM33_ENABLED} else ',nouveau'}"
+MESA_LLVM_RELEASE_amdfalconx86 = "3.7.0"
+
+SRC_URI_amdfalconx86 = "git://anongit.freedesktop.org/git/mesa/mesa;branch=master \
+			file://0001-winsys-radeon-make-radeon_bo_vtbl-static.patch \
+			file://0002-gallium-radeon-print-winsys-info-with-R600_DEBUG-inf.patch \
+			file://0003-radeonsi-remove-useless-includes.patch \
+			file://0004-radeonsi-remove-deprecated-and-useless-registers.patch \
+			file://0005-radeonsi-set-an-optimal-value-for-DB_Z_INFO_ZRANGE_P.patch \
+			file://0006-winsys-radeon-move-radeon_winsys.h-up-one-directory.patch \
+			file://0007-winsys-radeon-add-a-private-interface-for-radeon_sur.patch \
+			file://0008-winsys-amdgpu-add-a-new-winsys-for-the-new-kernel-dr.patch \
+			file://0009-winsys-amdgpu-add-addrlib-texture-addressing-and-ali.patch \
+			file://0010-radeonsi-fix-DRM-version-checks-for-amdgpu-DRM-3.0.0.patch \
+			file://0011-radeonsi-add-VI-register-definitions.patch \
+			file://0012-radeonsi-add-VI-hardware-support.patch \
+			file://0013-radeonsi-add-a-temporary-workaround-for-a-shader-bug.patch \
+			file://0014-gallium-radeon-use-VM-for-UVD.patch \
+			file://0015-gallium-radeon-use-VM-for-VCE.patch \
+			file://0016-gallium-radeon-add-h264-performance-HW-decoder-suppo.patch \
+			file://0017-radeon-vce-make-firmware-check-compatible-with-new-f.patch \
+			file://0018-radeon-vce-adapt-new-firmware-interface-changes.patch \
+			file://0019-radeon-video-add-4K-support-for-decode-encode-parame.patch \
+			file://0020-radeon-uvd-recalculate-dbp-buffer-size.patch \
+			file://0021-radeon-uvd-make-30M-as-minimum-for-MPEG4-dpb-buffer-.patch \
+			file://0022-radeon-vce-implement-VCE-two-pipe-support.patch \
+			file://0023-radeonsi-add-new-VI-PCI-IDs.patch \
+			file://0024-gallium-util-get-h264-level-based-on-number-of-max-r.patch \
+			file://0025-st-vdpau-add-h264-decoder-level-support.patch \
+			file://0026-st-omx-dec-separate-create_video_codec-to-different-.patch \
+			file://0027-vl-add-level-idc-in-sps.patch \
+			file://0028-st-omx-dec-add-h264-decoder-level-support.patch \
+			file://0029-st-va-add-h264-decoder-level-support.patch \
+			file://0030-radeonsi-properly-set-the-raster_config-for-KV.patch \
+			file://0031-radeonsi-properly-handler-raster_config-setup-on-CZ.patch \
+"
+
+# Install override from mesa.inc
+do_install_append_amdfalconx86() {
+	cp ${S}/include/EGL/eglplatform.h ${D}${includedir}/EGL/eglplatform.h
+}
+
+EXTRA_OECONF_append_amdfalconx86 = " \
+		 --enable-r600-llvm-compiler \
+		 --enable-llvm-shared-libs \
+		"
+
diff --git a/meta-amdfalconx86/recipes-graphics/xorg-driver/xf86-video-amdgpu.inc b/meta-amdfalconx86/recipes-graphics/xorg-driver/xf86-video-amdgpu.inc
new file mode 100644
index 00000000..c670e64f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/xorg-driver/xf86-video-amdgpu.inc
@@ -0,0 +1,33 @@
+SUMMARY = "X.Org X server -- AMDGPU graphics chipsets driver"
+
+DESCRIPTION = "xf86-video-amdgpu is an Xorg driver for AMD/ATI		\
+integrated graphics chipsets. The driver supports depths 8, 15,		\
+16 and 24. On some chipsets, the driver supports hardware accelerated	\
+3D via the Direct Rendering Infrastructure (DRI).			\
+"
+
+require recipes-graphics/xorg-driver/xorg-driver-video.inc
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=aabff1606551f9461ccf567739af63dc"
+
+DEPENDS += "virtual/libx11 drm dri2proto glproto \
+	    virtual/libgl xineramaproto libpciaccess \
+	    udev glamor-egl \
+"
+
+PR = "${INC_PR}.1"
+EXTRA_OECONF += "--enable-udev --enable-glamor"
+
+SRC_URI = " \
+	    git://people.freedesktop.org/~agd5f/xf86-video-amdgpu;branch=amdgpu \
+"
+
+S = "${WORKDIR}/git"
+
+RDEPENDS_${PN} += "glamor-egl \
+		   mesa-driver-radeon \
+		   mesa-driver-radeonsi \
+		   mesa-driver-swrast \
+"
+
+COMPATIBLE_HOST = '(i.86|x86_64).*-linux'
diff --git a/meta-amdfalconx86/recipes-graphics/xorg-driver/xf86-video-amdgpu_0.0.01.bb b/meta-amdfalconx86/recipes-graphics/xorg-driver/xf86-video-amdgpu_0.0.01.bb
new file mode 100644
index 00000000..069c0ddb
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/xorg-driver/xf86-video-amdgpu_0.0.01.bb
@@ -0,0 +1,4 @@
+require xf86-video-amdgpu.inc
+
+SRCREV = "ff62bf6e9dce55dbde92baf4fa30193c7344ee8a"
+PV = "0.0.01+git${SRCPV}"
diff --git a/meta-amdfalconx86/recipes-graphics/xorg-xserver/glamor-egl_0.6.0.bbappend b/meta-amdfalconx86/recipes-graphics/xorg-xserver/glamor-egl_0.6.0.bbappend
new file mode 100644
index 00000000..c51eec66
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/xorg-xserver/glamor-egl_0.6.0.bbappend
@@ -0,0 +1,12 @@
+FILESEXTRAPATHS_prepend_amdfalconx86 := "${THISDIR}/${PN}:"
+
+SRC_URI_amdfalconx86 = " \
+	    git://anongit.freedesktop.org/xorg/driver/glamor;branch=master \
+"
+
+SRCREV_amdfalconx86 = "347ef4f01edba49820eefaf4b25522fc260d118c"
+PV_amdfalconx86 = "0.6.0+git${SRCPV}"
+
+S_amdfalconx86 = "${WORKDIR}/git"
+
+DEPENDS_append_amdfalconx86 = " libepoxy "
diff --git a/meta-amdfalconx86/recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend b/meta-amdfalconx86/recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend
new file mode 100644
index 00000000..ff42a8eb
--- /dev/null
+++ b/meta-amdfalconx86/recipes-graphics/xorg-xserver/xserver-xf86-config_0.1.bbappend
@@ -0,0 +1,3 @@
+do_install_prepend_amdfalconx86 () {
+        sed -i -e 's/^\tDriver      "radeon"/	Driver      "amdgpu"/' ${WORKDIR}/xorg.conf
+}
diff --git a/meta-amdfalconx86/recipes-kernel/amd-gpio/amd-gpio_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-gpio/amd-gpio_1.0.bb
new file mode 100644
index 00000000..4e7a9bab
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-gpio/amd-gpio_1.0.bb
@@ -0,0 +1,28 @@
+DESCRIPTION = "This kernel module provides support for AMD GPIO driver"
+LICENSE = "BSD | GPLv2"
+LIC_FILES_CHKSUM = "file://gpio-amd.c;md5=2a772a9977520ddf9780e9760062b621 \
+		    file://gpio-amd.h;md5=7b49b68331706afd157c54bafe6426cb \
+		    file://Makefile;md5=1cf995f5213fae50197541e5992b0d4e \
+		   "
+
+inherit module
+
+PR = "r0"
+PV = "1.0"
+
+SRC_URI = "file://Makefile \
+           file://gpio-amd.c \
+           file://gpio-amd.h \
+          "
+
+S = "${WORKDIR}"
+
+# Kernel module packages MUST begin with 'kernel-module-', otherwise
+# multilib image generation can fail.
+#
+# The following line is only necessary if the recipe name does not begin
+# with kernel-module-.
+#
+PKG_${PN} = "kernel-module-${PN}"
+
+FILES_${PN} += "${sysconfdir}"
diff --git a/meta-amdfalconx86/recipes-kernel/amd-gpio/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-gpio/files/Makefile
new file mode 100644
index 00000000..147c8ad4
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-gpio/files/Makefile
@@ -0,0 +1,14 @@
+obj-m := gpio-amd.o
+
+SRC := $(shell pwd)
+
+all:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC)
+
+modules_install:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
+
+clean:
+	rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
+	rm -f Module.markers Module.symvers modules.order
+	rm -rf .tmp_versions Modules.symvers
diff --git a/meta-amdfalconx86/recipes-kernel/amd-gpio/files/gpio-amd.c b/meta-amdfalconx86/recipes-kernel/amd-gpio/files/gpio-amd.c
new file mode 100644
index 00000000..3c43817a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-gpio/files/gpio-amd.c
@@ -0,0 +1,701 @@
+/*****************************************************************************
+*
+* Copyright (c) 2014, Advanced Micro Devices, Inc.   
+* All rights reserved.   
+*
+* Redistribution and use in source and binary forms, with or without   
+* modification, are permitted provided that the following conditions are met:   
+*     * Redistributions of source code must retain the above copyright   
+*       notice, this list of conditions and the following disclaimer.   
+*     * Redistributions in binary form must reproduce the above copyright   
+*       notice, this list of conditions and the following disclaimer in the   
+*       documentation and/or other materials provided with the distribution.   
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of    
+*       its contributors may be used to endorse or promote products derived    
+*       from this software without specific prior written permission.   
+*    
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND   
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED   
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE   
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY   
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES   
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;   
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT   
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS   
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.   
+*    
+*   
+***************************************************************************/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/gpio.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#include <asm/io.h>
+
+#include <linux/cdev.h>
+#include <linux/fs.h>           /* everything... */
+#include <asm/io.h>
+#include <linux/ioctl.h>
+#include <linux/device.h>
+#include <linux/string.h>
+
+#include "gpio-amd.h"
+
+static u32 gpiobase_phys;
+static u32 iomuxbase_phys;
+static struct pci_dev *amd_gpio_pci;
+static struct platform_device *amd_gpio_platform_device;
+
+
+static int dev_major;
+static int dev_minor = 0;
+
+static struct gpio_test_dev{
+	struct cdev cdev;
+	struct class *gpio_class;
+}gpio_test_dev;
+
+
+/* The following GPIO pins are reserved as per the specification. 184 max */
+static u8 mask[] = {
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	/*  0 to 11   */
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	/* 12 to 23   */
+	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,	/* 24 to 35   */
+	0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 1,	/* 36 to 47   */
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	/* 48 to 59   */
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	/* 60 to 71   */
+	1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,	/* 72 to 83   */
+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1,	/* 84 to 95   */
+	1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,	/* 96 to 107  */
+	0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1,	/* 108 to 119 */
+	1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1,	/* 120 to 131 */
+	1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1,	/* 132 to 143 */
+	1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,	/* 144 to 155 */
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	/* 156 to 167 */
+	0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,	/* 168 to 179 */
+	1, 1, 1, 1,				/* 180 to 183 */
+};
+
+static unsigned char iomux_mode0[] = {3, 4, 5, 6, 7, 8, 9, 11, 40, 64, 65, 66,
+				      67, 68, 69, 70, 71, 72, 76, 89, 90, 95,
+				      96, 97, 98, 99, 100, '\0'};
+static unsigned char iomux_mode1[] = {1, 2, 10, 13, 14, 15, 21, 22, 24, 25, 26,
+				      39, 42, 74, 75, 84, 85, 86, 87, 88, 91,
+				      93, 101, 102, 115, 116, 117, 118, 120,
+				      121, 122, 126, 129, 130, 133, 135, 136,
+				      137, 138, 139, 140, 141, 142, 143, 144,
+				      145, 146, 147, 148, '\0'};
+static unsigned char iomux_mode2[] = {11, 12, 16, 17, 18, 19, 20, 23, 113, 114,
+				      119, 132, '\0'};
+static unsigned char iomux_mode3[] = {92, 131, '\0'};
+
+static int gpio_mask[AMD_GPIO_NUM_PINS];
+static unsigned int num_mask;
+module_param_array(gpio_mask, int, &num_mask, 0);
+MODULE_PARM_DESC(gpio_mask, "GPIO mask which marks them as reserved");
+
+static int gpio_mode[AMD_GPIO_NUM_PINS];
+static unsigned int num_modes;
+module_param_array(gpio_mode, int, &num_modes, 0);
+MODULE_PARM_DESC(gpio_mode, "Specifies whether the GPIO mentioned "
+			"in gpio_mask is 0-reserved, 1-available, 2-GPI only, "
+			"3-GPO only");
+
+static struct amd_gpio_chip {
+	struct gpio_chip gpio;
+
+	void __iomem *gpiobase;
+	void __iomem *iomuxbase;
+
+	struct platform_device *pdev;
+	spinlock_t lock;
+} amd_gpio_chip;
+
+static int amd_gpio_request(struct gpio_chip *c, unsigned offset)
+{
+	struct amd_gpio_chip *chip = container_of(c, struct amd_gpio_chip,
+						  gpio);
+	unsigned long flags;
+	u8 iomux_reg;
+	u32 gpio_reg = 0;
+
+	spin_lock_irqsave(&chip->lock, flags);
+
+	/* check if this pin is available */
+	if (mask[offset] == AMD_GPIO_MODE_RESV) {
+		spin_unlock_irqrestore(&chip->lock, flags);
+		pr_info("GPIO pin %u not available\n", offset);
+		return -EINVAL;
+	}
+
+	/* Program the GPIO Wake/Interrupt Switch offset is AMD_GPIO_MSWITCH */
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + AMD_GPIO_MSWITCH);
+	/* to disable all GPIO wake and interrupt*/
+	gpio_reg &= (~AMD_GPIO_WAKE_EN & ~AMD_GPIO_INTERRUPT_EN);
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + AMD_GPIO_MSWITCH));
+
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+	/* clear wake status and interrupt status */
+	gpio_reg |= (AMD_GPIO_INTERPT_STATUS | AMD_GPIO_WAKE_STATUS);
+
+	/* Set disable both Pull Up and Pull Down and disable output */
+	gpio_reg &= (~AMD_GPIO_PULLUP_ENABLE & ~AMD_GPIO_PULLDN_ENABLE
+			& ~AMD_GPIO_DEB_CTRL & ~AMD_GPIO_SWCTRL_IN
+			& ~AMD_GPIO_WAKECTRL & ~AMD_GPIO_INTERPT_ENABLE);
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + offset));
+
+	/* Enable GPIO by writing to the corresponding IOMUX register */
+	iomux_reg = ioread8((u8 *)amd_gpio_chip.iomuxbase + offset);
+	iomux_reg &= ~AMD_IOMUX_GPIO_MASK;
+
+	if(offset == 10 || offset == 72 || offset == 73 ||offset == 76)
+		iomux_reg |= AMD_IOMUX_ENABLE_FUNC0;
+	else if(offset == 35 || offset == 64 || offset == 65 ||offset == 66 ||
+		offset == 71 || offset == 93 ||offset == 115 ||offset == 116)
+		iomux_reg |= AMD_IOMUX_ENABLE_FUNC2;
+	else if(offset == 67 || offset == 70)
+		iomux_reg |= AMD_IOMUX_ENABLE_FUNC3;
+	else
+		iomux_reg |= AMD_IOMUX_ENABLE_FUNC1;
+
+	iowrite8(iomux_reg, ((u8 *)amd_gpio_chip.iomuxbase + offset));
+
+	spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+
+static int amd_gpio_get(struct gpio_chip *c, unsigned offset)
+{
+	struct amd_gpio_chip *chip = container_of(c, struct amd_gpio_chip,
+						  gpio);
+	unsigned long flags;
+	u32 gpio_reg;
+
+	spin_lock_irqsave(&chip->lock, flags);
+
+	/* Read the GPIO register */
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+
+	spin_unlock_irqrestore(&chip->lock, flags);
+
+	return (gpio_reg & AMD_GPIO_GET_INPUT) ? 1 : 0;
+}
+
+static void amd_gpio_set(struct gpio_chip *c, unsigned offset, int val)
+{
+	struct amd_gpio_chip *chip = container_of(c, struct amd_gpio_chip,
+						  gpio);
+	unsigned long flags;
+	u32 gpio_reg;
+
+	spin_lock_irqsave(&chip->lock, flags);
+
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+
+	/* Set GPIO Output depending on 'val' */
+	if (val)
+		gpio_reg |= AMD_GPIO_SET_OUTPUT;
+	else
+		gpio_reg &= ~AMD_GPIO_SET_OUTPUT;
+
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + offset));
+
+	spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static int amd_gpio_direction_input(struct gpio_chip *c, unsigned offset)
+{
+	struct amd_gpio_chip *chip = container_of(c, struct amd_gpio_chip,
+						  gpio);
+	unsigned long flags;
+	u32 gpio_reg;
+
+	spin_lock_irqsave(&chip->lock, flags);
+
+	/* If the mask says the pin should be GPO, we return from here */
+	if (mask[offset] == AMD_GPIO_MODE_OUTPUT) {
+		pr_info("GPIO %u can only be set in output mode\n", offset);
+		spin_unlock_irqrestore(&chip->lock, flags);
+		return -EINVAL;
+	}
+
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+	/* Disable output by set the bit to 0 */
+	gpio_reg &= ~AMD_GPIO_OUTPUT_ENABLE;
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + offset));
+
+	spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static int amd_gpio_direction_output(struct gpio_chip *c, unsigned offset,
+				     int val)
+{
+	struct amd_gpio_chip *chip = container_of(c, struct amd_gpio_chip,
+						  gpio);
+	unsigned long flags;
+	u32 gpio_reg;
+
+	spin_lock_irqsave(&chip->lock, flags);
+
+	/* If the mask says the pin should be GPI, we return from here */
+	if (mask[offset] == AMD_GPIO_MODE_INPUT) {
+		pr_info("GPIO %u can only be set in input mode\n", offset);
+		spin_unlock_irqrestore(&chip->lock, flags);
+		return -EINVAL;
+	}
+
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+
+
+	gpio_reg |= AMD_GPIO_DRV_STRENGTH(2);
+	/* Set disable both Pull Up and Pull Down */
+	gpio_reg &= (~AMD_GPIO_PULLUP_ENABLE & ~AMD_GPIO_PULLDN_ENABLE
+			& ~AMD_GPIO_DEB_CTRL & ~AMD_GPIO_SWCTRL_IN
+			& ~AMD_GPIO_WAKECTRL & ~AMD_GPIO_INTERPT_ENABLE);
+	/* Enable output */
+	gpio_reg |= AMD_GPIO_OUTPUT_ENABLE;
+
+	/* Set GPIO Output depending on 'val' */
+	if (val)
+		gpio_reg |= AMD_GPIO_SET_OUTPUT;
+	else
+		gpio_reg &= ~AMD_GPIO_SET_OUTPUT;
+
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + offset));
+
+	spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static struct amd_gpio_chip amd_gpio_chip = {
+	.gpio = {
+		.owner = THIS_MODULE,
+		.label = DRV_NAME,
+
+		.base = 0,
+		.ngpio = AMD_GPIO_NUM_PINS,
+		.names = NULL,
+		.request = amd_gpio_request,
+		.get = amd_gpio_get,
+		.set = amd_gpio_set,
+		.direction_input = amd_gpio_direction_input,
+		.direction_output = amd_gpio_direction_output,
+	},
+};
+
+/*
+* The PCI Device ID table below is used to identify the platform
+* the driver is supposed to work for. Since this is a platform
+* driver, we need a way for us to be able to find the correct
+* platform when the driver gets loaded, otherwise we should
+* bail out.
+*/
+static DEFINE_PCI_DEVICE_TABLE(amd_gpio_pci_tbl) = {
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CARRIZO_SMBUS, PCI_ANY_ID,
+	  PCI_ANY_ID, },
+	{ 0, },
+};
+
+MODULE_DEVICE_TABLE(pci, amd_gpio_pci_tbl);
+
+static void amd_update_gpio_mask(void)
+{
+	u8 iomux_reg;
+	int i, j;
+	unsigned char *iomux_modes[4] = {iomux_mode0, iomux_mode1,
+					 iomux_mode2, iomux_mode3};
+	/*
+	 * Some of the GPIO pins have an alternate function assigned to
+	 * them. That will be reflected in the corresponding IOMUX
+	 * registers. If so, we mark these GPIO pins as reserved.
+	 */
+
+	/* GPIO0 */
+	iomux_reg = ioread8((u8 *)amd_gpio_chip.iomuxbase + 0);
+	if (((iomux_reg & AMD_IOMUX_GPIO_MASK) != 0x1) )
+		mask[0] = AMD_GPIO_MODE_RESV;
+
+	/* GPIO1 to GPIO183 */
+	 for(j = 0; j < 4; j++) {
+		for(i = 0; i < strlen((char *)iomux_modes[j]); i++) {
+			iomux_reg = ioread8((u8 *)amd_gpio_chip.iomuxbase
+					    + iomux_modes[j][i]);
+
+			if (((iomux_reg & AMD_IOMUX_GPIO_MASK) != j))
+				mask[iomux_modes[j][i]] = AMD_GPIO_MODE_RESV;
+		}
+	}
+}
+
+static int amd_gpio_init(struct platform_device *pdev)
+{
+	struct pci_dev *dev = NULL;
+	int i;
+	int err;
+
+	/* Match the PCI device */
+	for_each_pci_dev(dev) {
+		if (pci_match_id(amd_gpio_pci_tbl, dev) != NULL) {
+			amd_gpio_pci = dev;
+			break;
+		}
+	}
+
+	if (!amd_gpio_pci)
+		return -ENODEV;
+
+	/* GPIO registers range from AMD_GPIO_ACPIMMIO_BASE+1500h to 
+						AMD_GPIO_ACPIMMIO_BASE+17FFh. */
+	if (!request_mem_region_exclusive(AMD_GPIO_ACPIMMIO_BASE
+		+ AMD_GPIO_BANK_OFFSET,	AMD_GPIO_MEM_MAP_SIZE, "AMD GPIO")) {
+		pr_err("mmio address 0x%04x already in use\n",
+			AMD_GPIO_ACPIMMIO_BASE + AMD_GPIO_BANK_OFFSET );
+		goto exit;
+	}
+	gpiobase_phys = AMD_GPIO_ACPIMMIO_BASE + AMD_GPIO_BANK_OFFSET;
+
+	amd_gpio_chip.gpiobase = ioremap(gpiobase_phys, AMD_GPIO_MEM_MAP_SIZE);
+	if (!amd_gpio_chip.gpiobase) {
+		pr_err("failed to get gpiobase address\n");
+		goto unreg_gpio_region;
+	}
+
+	/* IOMUX Base Address starts from ACPI MMIO Base Address + 0xD00 */
+	if (!request_mem_region_exclusive(AMD_GPIO_ACPIMMIO_BASE
+					+ AMD_IOMUX_MEM_MAP_OFFSET,
+					AMD_IOMUX_MEM_MAP_SIZE,	"AMD IOMUX")) {
+		pr_err("mmio address 0x%04x already in use\n",
+			AMD_GPIO_ACPIMMIO_BASE + AMD_IOMUX_MEM_MAP_OFFSET);
+		goto unmap_gpio_region;
+	}
+	iomuxbase_phys = AMD_GPIO_ACPIMMIO_BASE + AMD_IOMUX_MEM_MAP_OFFSET;
+
+	amd_gpio_chip.iomuxbase = ioremap(iomuxbase_phys,
+						AMD_IOMUX_MEM_MAP_SIZE);
+	if (!amd_gpio_chip.iomuxbase) {
+		pr_err("failed to get iomuxbase address\n");
+		goto unreg_iomux_region;
+	}
+
+	/* Set up driver specific struct */
+	amd_gpio_chip.pdev = pdev;
+	spin_lock_init(&amd_gpio_chip.lock);
+
+	/* Register ourself with the GPIO core */
+	err = gpiochip_add(&amd_gpio_chip.gpio);
+	if (err)
+		goto unmap_iomux_region;
+
+	/*
+	 * Lets take care of special GPIO pins, and mark them as reserved
+	 * as appropriate.
+	 */
+	amd_update_gpio_mask();
+
+	/*
+	 * If the number of GPIO pins provided during module loading does
+	 * not match the number of GPIO modes, we fall back to the default
+	 * mask.
+	 */
+	if (num_mask == num_modes) {
+		/*
+		 * If the number of masks or the number of modes specified
+		 * is more than the maximum number of GPIO pins supported
+		 * by the driver, we set the limit to the one supported
+		 * driver.
+		 */
+		if (num_mask > AMD_GPIO_NUM_PINS)
+			num_mask = num_modes = AMD_GPIO_NUM_PINS;
+
+		/*
+		 * The default mask is our de facto standard. The GPIO
+		 * pins marked reserved in the default mask stay reserved
+		 * no matter what the module load parameter says. Also, we
+		 * set the mode of the GPIO pins depending on the value
+		 * of gpio_mode provided.
+		 */
+		for (i = 0; i < num_mask; i++) {
+			if (mask[gpio_mask[i]] != AMD_GPIO_MODE_RESV) {
+				mask[gpio_mask[i]] = gpio_mode[i];
+
+				/*
+				 * gpio_request() can fail, in which case we
+				 * won't set the GPIO modes.
+				 */
+				if(!gpio_request(gpio_mask[i], DRV_NAME)) {
+					if (gpio_mode[i] ==
+						AMD_GPIO_MODE_INPUT)
+						gpio_direction_input(gpio_mask[i]);
+					else if (gpio_mode[i] ==
+						AMD_GPIO_MODE_OUTPUT)
+						gpio_direction_output(gpio_mask[i],
+									0);
+
+					gpio_free(gpio_mask[i]);
+				}
+			}
+		}
+	}
+
+	return 0;
+
+unmap_iomux_region:
+	iounmap(amd_gpio_chip.iomuxbase);
+unreg_iomux_region:
+	release_mem_region(iomuxbase_phys, AMD_IOMUX_MEM_MAP_SIZE);
+unmap_gpio_region:
+	iounmap(amd_gpio_chip.gpiobase);
+unreg_gpio_region:
+	release_mem_region(gpiobase_phys, AMD_GPIO_MEM_MAP_SIZE);
+exit:
+	return -ENODEV;
+}
+
+static int amd_gpio_remove(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpiochip_remove(&amd_gpio_chip.gpio);
+	if (err) {
+		dev_err(&pdev->dev, "Unable to remove gpio chip\n");
+		return err;
+	}
+
+	iounmap(amd_gpio_chip.iomuxbase);
+	release_mem_region(iomuxbase_phys, AMD_IOMUX_MEM_MAP_SIZE);
+	iounmap(amd_gpio_chip.gpiobase);
+	release_mem_region(gpiobase_phys, AMD_GPIO_MEM_MAP_SIZE);
+
+	return 0;
+}
+
+static struct platform_driver amd_gpio_driver = {
+	.probe		= amd_gpio_init,
+	.remove		= amd_gpio_remove,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= GPIO_MODULE_NAME,
+	},
+};
+
+/* interface to debug driver for gpio */
+
+static int amd_gpio_swctrlen(int offset, int value)
+{
+	struct amd_gpio_chip *chip = &amd_gpio_chip;
+	u32 gpio_reg;
+	unsigned long flags;
+
+	spin_lock_irqsave(&chip->lock, flags);
+
+		/* If the mask says the pin should be GPO, we return from here */
+	if (mask[offset] == AMD_GPIO_MODE_RESV) {
+		pr_info("GPIO %u is reserved\n", offset);
+		spin_unlock_irqrestore(&chip->lock, flags);
+		return -EINVAL;
+	}
+
+	if (mask[offset] == AMD_GPIO_MODE_OUTPUT) {
+		pr_info("GPIO %u can only be set in output mode\n", offset);
+		spin_unlock_irqrestore(&chip->lock, flags);
+		return -EINVAL;
+	}
+
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+	/* Disable output by set the bit to 0 */
+	gpio_reg &= ~AMD_GPIO_OUTPUT_ENABLE;
+	/* enable or disable sw input */
+	if(value)
+		gpio_reg |= AMD_GPIO_SWCTRL_EN;
+	else
+		gpio_reg &= ~AMD_GPIO_SWCTRL_EN;
+
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + offset));
+
+	spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static int amd_gpio_swctrlin(int offset, int value)
+{
+	struct amd_gpio_chip *chip = &amd_gpio_chip;
+	u32 gpio_reg;
+	unsigned long flags;
+
+	spin_lock_irqsave(&chip->lock, flags);
+		/* If the mask says the pin should be GPO, we return from here */
+	if (mask[offset] == AMD_GPIO_MODE_RESV) {
+		pr_info("GPIO %u is reserved\n", offset);
+		spin_unlock_irqrestore(&chip->lock, flags);
+		return -EINVAL;
+	}
+
+	if (mask[offset] == AMD_GPIO_MODE_OUTPUT) {
+		pr_info("GPIO %u can only be set in input mode\n", offset);
+		spin_unlock_irqrestore(&chip->lock, flags);
+		return -EINVAL;
+	}
+
+	gpio_reg = ioread32((u32 *)amd_gpio_chip.gpiobase + offset);
+	/* Disable output by set the bit to 0 */
+	gpio_reg &= ~AMD_GPIO_OUTPUT_ENABLE;
+	/* enable or disable sw input */
+	if(value)
+		gpio_reg |= AMD_GPIO_SWCTRL_IN;
+	else
+		gpio_reg &= ~AMD_GPIO_SWCTRL_IN;
+
+	iowrite32(gpio_reg, ((u32 *)amd_gpio_chip.gpiobase + offset));
+	spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+
+static int gpio_test_open(struct inode *inode, struct file *filp)
+{
+	struct gpio_test_dev *dev; /* device information */
+
+	dev = container_of(inode->i_cdev, struct gpio_test_dev, cdev);
+	filp->private_data = dev; /* for other methods */
+
+	return 0;          /* success */
+}
+
+static int gpio_test_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static long gpio_test_ioctl(struct file *filp,
+                 unsigned cmd, unsigned long arg)
+{
+
+	debug_data  tmp;
+	unsigned long retval = 0;
+
+	/* Check type and command number */
+	if (_IOC_TYPE(cmd) != GPIO_TEST_IOC_MAGIC)
+		return -ENOTTY;
+
+	retval = copy_from_user(&tmp, (void __user *)arg, sizeof(debug_data));
+	if(retval != 0)
+	return 0;
+
+	switch(cmd) {
+		case GPIO_IOC_SWCTRLIN:
+			retval = amd_gpio_swctrlin(tmp.offset,tmp.value);
+		break;
+		case GPIO_IOC_SWCTRLEN:
+			retval = amd_gpio_swctrlen(tmp.offset,tmp.value);
+		break;
+		default:
+			return -ENOTTY;
+	}
+
+	return retval;
+}
+
+struct file_operations gpio_test_fops = {
+	.owner = THIS_MODULE,
+	.unlocked_ioctl = gpio_test_ioctl,
+	.open = gpio_test_open,
+	.release = gpio_test_release,
+};
+
+
+static int __init amd_gpio_init_module(void)
+{
+	int err;
+	dev_t dev = 0;
+	struct device *gpio_device = 0;
+
+	pr_info("AMD GPIO Driver v%s\n", GPIO_VERSION);
+
+	err = platform_driver_register(&amd_gpio_driver);
+	if (err)
+		return err;
+
+	err = alloc_chrdev_region(&dev, dev_minor, 1,"gpio_test_driver");
+	if (err < 0) {
+		printk(KERN_WARNING " can't get major %d\n", dev_major);
+		goto unreg_platform_driver;
+	}
+
+	gpio_test_dev.gpio_class = class_create(THIS_MODULE, "gpio_test_driver");
+	if (IS_ERR(gpio_test_dev.gpio_class)) {
+		printk(" error in class create \n");
+		goto unregister_test_driver;
+	}
+
+	dev_major = MAJOR(dev);
+
+	gpio_device = device_create(gpio_test_dev.gpio_class, NULL, dev, NULL,
+				    "gpio_test_driver");
+	if (IS_ERR(gpio_device)) {
+		printk(" error in device create \n");
+		goto destroy_class;
+	}
+
+	cdev_init(&gpio_test_dev.cdev, &gpio_test_fops);
+	err = cdev_add (&gpio_test_dev.cdev, dev, 1);
+	if(err)
+		goto destroy_device;
+
+	amd_gpio_platform_device = platform_device_register_simple(
+					GPIO_MODULE_NAME, -1, NULL, 0);
+	if (IS_ERR(amd_gpio_platform_device)) {
+		err = PTR_ERR(amd_gpio_platform_device);
+		goto cdev_delete;
+	}
+
+	return 0;
+
+cdev_delete:
+	cdev_del(&gpio_test_dev.cdev);
+destroy_device:
+	device_destroy(gpio_test_dev.gpio_class, dev);
+destroy_class:
+	class_destroy(gpio_test_dev.gpio_class);
+unregister_test_driver:
+	unregister_chrdev_region(dev, 1);
+unreg_platform_driver:
+	platform_driver_unregister(&amd_gpio_driver);
+	return err;
+}
+
+static void __exit amd_gpio_cleanup_module(void)
+{
+	dev_t dev = MKDEV(dev_major, dev_minor);
+	
+	device_destroy(gpio_test_dev.gpio_class, dev);
+	class_destroy(gpio_test_dev.gpio_class);
+	cdev_del(&gpio_test_dev.cdev);
+	unregister_chrdev_region(dev, 1);
+	platform_device_unregister(amd_gpio_platform_device);
+	platform_driver_unregister(&amd_gpio_driver);
+	pr_info("AMD GPIO Module Unloaded\n");
+}
+
+module_init(amd_gpio_init_module);
+module_exit(amd_gpio_cleanup_module);
+
+
+
+MODULE_AUTHOR("Sudheesh Mavila <sudheesh.mavila@amd.com>");
+MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
+MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-gpio/files/gpio-amd.h b/meta-amdfalconx86/recipes-kernel/amd-gpio/files/gpio-amd.h
new file mode 100644
index 00000000..4cbceb57
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-gpio/files/gpio-amd.h
@@ -0,0 +1,86 @@
+#ifndef _AMD_GPIO_H_
+#define _AMD_GPIO_H_
+
+#include <linux/types.h>
+
+/* Module and version information */
+#define GPIO_VERSION "0.1"
+#define GPIO_MODULE_NAME "AMD GPIO"
+#define GPIO_DRIVER_NAME   GPIO_MODULE_NAME ", v" GPIO_VERSION
+
+#define DRV_NAME "amd-gpio"
+
+/* GPIO register definitions */
+#define PCI_DEVICE_ID_AMD_CARRIZO_SMBUS	0x790B
+#define AMD_GPIO_ACPIMMIO_BASE		0xFED80000
+#define AMD_GPIO_BANK_OFFSET		0x1500
+#define AMD_GPIO_MEM_MAP_SIZE		0x300
+#define AMD_GPIO_MSWITCH		63
+
+#define AMD_IOMUX_MEM_MAP_OFFSET	0x0D00
+#define AMD_IOMUX_MEM_MAP_SIZE		0x100
+
+#define AMD_PM_IOPORTS_SIZE		0x02
+
+/* IO port address for indirect access using the ACPI PM registers */
+#define AMD_IO_PM_INDEX_REG		0xCD6
+#define AMD_IO_PM_DATA_REG		0xCD7
+
+#define AMD_GPIO_NUM_PINS		184
+
+#define AMD_GPIO_DEB_TIMEOUT0		(0)	/* debouncing logic disabled */
+#define AMD_GPIO_DEB_TIMEOUT1		(1)
+#define AMD_GPIO_DEB_TIMEOUT_MASK	(7)
+#define AMD_GPIO_DEB_TIMEOUTUNIT	(1 << 4)
+#define AMD_GPIO_DEB_CTRL		(3 << 5)
+#define AMD_GPIO_LEVL_TRG		(1 << 8)	/* 0 - edge , 1 level */
+#define AMD_GPIO_ACTIVE_LEVEL		(3 << 9)
+#define AMD_GPIO_INTERPT_ENABLE		(3 << 11)
+#define AMD_GPIO_WAKECTRL		(7 << 13)
+#define AMD_GPIO_GET_INPUT		(1 << 16)
+#define AMD_GPIO_DRV_STRENGTH(x)	(((x) & 3) << 17)
+#define AMD_GPIO_PULLUP_SEL		(1 << 19)
+#define AMD_GPIO_PULLUP_ENABLE		(1 << 20)
+#define AMD_GPIO_PULLDN_ENABLE		(1 << 21)
+#define AMD_GPIO_SET_OUTPUT		(1 << 22)
+#define AMD_GPIO_OUTPUT_ENABLE		(1 << 23)
+#define AMD_GPIO_SWCTRL_IN		(1 << 24)
+#define AMD_GPIO_SWCTRL_EN		(1 << 25)
+#define AMD_GPIO_INTERPT_STATUS		(1 << 28)
+#define AMD_GPIO_WAKE_STATUS		(1 << 29)
+
+#define AMD_GPIO_WAKE_EN		(1 << 31)
+#define AMD_GPIO_INTERRUPT_EN		(1 << 30)
+
+#define AMD_IOMUX_ENABLE_FUNC0		0x0
+#define AMD_IOMUX_ENABLE_FUNC1		0x1
+#define AMD_IOMUX_ENABLE_FUNC2		0x2
+#define AMD_IOMUX_ENABLE_FUNC3		0x3
+#define AMD_IOMUX_GPIO_MASK		0x03
+
+#define AMD_PM_GPIO_BASE0		0x24
+#define AMD_PM_GPIO_BASE1		0x25
+#define AMD_PM_GPIO_BASE2		0x26
+#define AMD_PM_GPIO_BASE3		0x27
+
+
+
+
+/* GPIO pin mode definitions */
+#define AMD_GPIO_MODE_RESV		0	/* Reserved */
+#define AMD_GPIO_MODE_ANY		1	/* Either input or output */
+#define AMD_GPIO_MODE_INPUT		2	/* GPI */
+#define AMD_GPIO_MODE_OUTPUT		3	/* GPO */
+
+/* IOCTL numbers */
+
+typedef struct {
+	int offset;
+	int value;
+}debug_data;
+
+#define GPIO_TEST_IOC_MAGIC			'k'
+#define GPIO_IOC_SWCTRLIN  _IOW(GPIO_TEST_IOC_MAGIC, 1, debug_data)
+#define GPIO_IOC_SWCTRLEN  _IOW(GPIO_TEST_IOC_MAGIC, 2, debug_data)
+
+#endif /* _AMD_GPIO_H_ */
diff --git a/meta-amdfalconx86/recipes-kernel/amd-gpio/kernel-module-amd-gpio_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-gpio/kernel-module-amd-gpio_1.0.bb
new file mode 100644
index 00000000..ba1e854f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-gpio/kernel-module-amd-gpio_1.0.bb
@@ -0,0 +1,28 @@
+DESCRIPTION = "This kernel module provides support for AMD GPIO driver"
+LICENSE = "BSD | GPLv2"
+LIC_FILES_CHKSUM = "file://gpio-amd.c;md5=e4d507e6f1ccf2efcb9fc2d4d65f9cf7 \
+		    file://gpio-amd.h;md5=7b49b68331706afd157c54bafe6426cb \
+		    file://Makefile;md5=1cf995f5213fae50197541e5992b0d4e \
+		   "
+
+inherit module
+
+PR = "r0"
+PV = "1.0"
+
+SRC_URI = "file://Makefile \
+           file://gpio-amd.c \
+           file://gpio-amd.h \
+          "
+
+S = "${WORKDIR}"
+
+# Kernel module packages MUST begin with 'kernel-module-', otherwise
+# multilib image generation can fail.
+#
+# The following line is only necessary if the recipe name does not begin
+# with kernel-module-.
+#
+PKG_${PN} = "kernel-module-${PN}"
+
+FILES_${PN} += "${sysconfdir}"
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb
new file mode 100644
index 00000000..b0cdc4f0
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb
@@ -0,0 +1,33 @@
+DESCRIPTION = "This kernel module provides support for AMD SPI controller driver"
+LICENSE = "BSD | GPLv2"
+LIC_FILES_CHKSUM = "file://spi_amd.c;md5=80f01f3b969d0b1d633df6ba9edf4170 \
+                    file://spi_amd.h;md5=488f986ada9e64f6b5ee6d55c269ae1b \
+                    file://spirom.c;md5=ec2142faf7c64a85563fcaa129772fc0 \
+                    file://spirom.h;md5=8de0c535224dbd8ecd2f40ef29c15d0a \
+		    file://Makefile;md5=8ea80a6d4ae15bcf922d090df6cfdd4c \
+		   "
+
+inherit module
+
+PR = "r0"
+PV = "1.0"
+
+SRC_URI = "file://Makefile \
+           file://spi_amd.c \
+           file://spi_amd.h \
+           file://spirom.c \
+           file://spirom.h \
+          "
+
+S = "${WORKDIR}"
+
+
+# Kernel module packages MUST begin with 'kernel-module-', otherwise
+# multilib image generation can fail.
+#
+# The following line is only necessary if the recipe name does not begin
+# with kernel-module-.
+#
+PKG_${PN} = "kernel-module-${PN}"
+
+FILES_${PN} += "${sysconfdir}"
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile
new file mode 100644
index 00000000..f778a69a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile
@@ -0,0 +1,14 @@
+obj-m := spi_amd.o spirom.o
+
+SRC := $(shell pwd)
+
+all:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC)
+
+modules_install:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
+
+clean:
+	rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
+	rm -f Module.markers Module.symvers modules.order
+	rm -rf .tmp_versions Modules.symvers
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c
new file mode 100644
index 00000000..76c08cec
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c
@@ -0,0 +1,476 @@
+/*****************************************************************************
+*
+* Copyright (c) 2013, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+***************************************************************************/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/spi/spi.h>
+#include <linux/kthread.h>
+
+#include "spi_amd.h"
+
+struct amd_platform_data {
+	u8 chip_select;
+};
+
+struct amd_spi {
+	void __iomem *io_remap_addr;
+	unsigned long io_base_addr;
+	u32 rom_addr;
+	struct spi_master *master;
+	struct amd_platform_data controller_data;
+	struct task_struct *kthread_spi;
+	struct list_head msg_queue;
+	wait_queue_head_t wq;
+};
+
+static struct pci_device_id amd_spi_pci_device_id[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE) },
+	{}
+};
+MODULE_DEVICE_TABLE(pci, amd_spi_pci_device_id);
+
+static inline u8 amd_spi_readreg8(struct spi_master *master, int idx)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	return ioread8((u8 *)amd_spi->io_remap_addr + idx);
+}
+
+static inline void amd_spi_writereg8(struct spi_master *master, int idx,
+				     u8 val)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	iowrite8(val, ((u8 *)amd_spi->io_remap_addr + idx));
+}
+
+static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx,
+					 u8 set, u8 clear)
+{
+	u8 tmp = amd_spi_readreg8(master, idx);
+	tmp = (tmp & ~clear) | set;
+	amd_spi_writereg8(master, idx, tmp);
+}
+
+static inline u32 amd_spi_readreg32(struct spi_master *master, int idx)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	return ioread32((u8 *)amd_spi->io_remap_addr + idx);
+}
+
+static inline void amd_spi_writereg32(struct spi_master *master, int idx,
+					u32 val)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	iowrite32(val, ((u8 *)amd_spi->io_remap_addr + idx));
+}
+
+static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx,
+					  u32 set, u32 clear)
+{
+	u32 tmp = amd_spi_readreg32(master, idx);
+	tmp = (tmp & ~clear) | set;
+	amd_spi_writereg32(master, idx, tmp);
+}
+
+static void amd_spi_select_chip(struct spi_master *master)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+	u8 chip_select = amd_spi->controller_data.chip_select;
+
+	amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select,
+			      AMD_SPI_ALT_CS_MASK);
+}
+
+
+static void amd_spi_clear_fifo_ptr(struct spi_master *master)
+{
+	amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR,
+			       AMD_SPI_FIFO_CLEAR);
+}
+
+static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode)
+{
+	amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode,
+			       AMD_SPI_OPCODE_MASK);
+}
+
+static inline void amd_spi_set_rx_count(struct spi_master *master,
+					u8 rx_count)
+{
+	amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
+}
+
+static inline void amd_spi_set_tx_count(struct spi_master *master,
+					u8 tx_count)
+{
+	amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
+}
+
+static void amd_spi_execute_opcode(struct spi_master *master)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+	bool spi_busy;
+
+	/* Set ExecuteOpCode bit in the CTRL0 register */
+	amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
+			       AMD_SPI_EXEC_CMD);
+
+	/* poll for SPI bus to become idle */
+	spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr +
+		    AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
+	while (spi_busy) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule();
+		set_current_state(TASK_RUNNING);
+		spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr +
+			    AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
+	}
+}
+
+/* Helper function */
+#ifdef CONFIG_SPI_DEBUG
+static void amd_spi_dump_reg(struct spi_master *master)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	printk(KERN_DEBUG DRIVER_NAME ": SPI CTRL 0 registers: 0x%.8x\n",
+		ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_CTRL0_REG));
+	/*
+	 * We cannot read CTRL1 register, because reading it would
+	 * inadvertently increment the FIFO pointer.
+	 */
+	printk(KERN_DEBUG DRIVER_NAME ": SPI ALT CS registers: 0x%.2x\n",
+		ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_ALT_CS_REG));
+	printk(KERN_DEBUG DRIVER_NAME ": SPI Tx Byte Count: 0x%.2x\n",
+		ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_TX_COUNT_REG));
+	printk(KERN_DEBUG DRIVER_NAME ": SPI Rx Byte Count: 0x%.2x\n",
+		ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_RX_COUNT_REG));
+	printk(KERN_DEBUG DRIVER_NAME ": SPI Status registers: 0x%.8x\n",
+		ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_STATUS_REG));
+}
+#else
+static void amd_spi_dump_reg(struct spi_master *master) {}
+#endif
+
+
+static int amd_spi_master_setup(struct spi_device *spi)
+{
+	struct spi_master *master = spi->master;
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	amd_spi->controller_data.chip_select = spi->chip_select;
+
+	amd_spi_select_chip(master);
+
+	return 0;
+}
+
+static int amd_spi_master_transfer(struct spi_master *master,
+				   struct spi_message *msg)
+{
+	struct amd_spi *amd_spi = spi_master_get_devdata(master);
+
+	/*
+	 * Add new message to the queue and let the kernel thread know
+	 * about it.
+	 */
+	list_add_tail(&msg->queue, &amd_spi->msg_queue);
+	wake_up_interruptible(&amd_spi->wq);
+
+	return 0;
+}
+static int amd_spi_thread(void *t)
+{
+	struct amd_spi *amd_spi = t;
+	struct spi_master *master = amd_spi->master;
+	struct spi_transfer *transfer = NULL;
+	struct spi_message *message = NULL;
+	int direction = 0,i = 0,saved_index = 0;
+	int opcode_found = 0,recv_flag = 0,tx_len = 0,rx_len = 0;
+	u8 cmd_opcode = 0;
+	u8 *buffer = NULL;
+
+	/*
+	 * What we do here is actually pretty simple. We pick one message
+	 * at a time from the message queue set up by the controller, and
+	 * then process all the spi_transfers of that spi_message in one go.
+	 * We then remove the message from the queue, and complete the
+	 * transaction. This might not be the best approach, but this is how
+	 * we chose to implement this. Note that out SPI controller has FIFO
+	 * size of 70 bytes, but we consider it to contain a maximum of
+	 * 64-bytes of data and 3-bytes of address.
+	 */
+	while (1) {
+		/*
+		 * Let us wait on a wait queue till the message queue is empty.
+		 */
+		wait_event_interruptible(amd_spi->wq,
+					 !list_empty(&amd_spi->msg_queue));
+
+		/* stop condition */		
+		if (kthread_should_stop()) {
+			set_current_state(TASK_RUNNING);
+			break;
+		}
+
+		/*
+		 * Else, pull the very first message from the queue and process
+		 * all transfers within that message. And process the messages
+		 * in a pure linear fashion. We also remove the spi_message
+		 * from the queue.
+		 */
+		message = list_entry(amd_spi->msg_queue.next,
+				     struct spi_message, queue);
+		list_del_init(&message->queue);
+
+		/* We store the CS# line to be used for this spi_message */
+		amd_spi->controller_data.chip_select =
+						message->spi->chip_select;
+
+		/* Setting all variables to default value. */
+		direction = i = 0;
+		opcode_found = 0;
+		recv_flag = tx_len = rx_len = 0;
+		cmd_opcode = 0;
+		buffer = NULL;
+		saved_index = 0;
+
+		amd_spi_select_chip(master);
+
+		/*
+		 * This loop extracts spi_transfers from the spi message,
+		 * programs the command into command register. Pointer variable
+		 * *buffer* points to either tx_buf or rx_buf of spi_transfer
+		 * depending on direction of transfer. Also programs FIFO of
+		 * controller if data has to be transmitted.
+		 */
+		list_for_each_entry(transfer, &message->transfers,
+				    transfer_list)
+		{
+			if(transfer->rx_buf != NULL)
+				direction = RECEIVE;
+			else if(transfer->tx_buf != NULL)
+				direction = TRANSMIT;
+
+			switch (direction) {
+			case TRANSMIT:
+				buffer = (u8 *)transfer->tx_buf;
+
+				if(opcode_found != 1) {
+					/* Store no. of bytes to be sent into
+					 * FIFO  */
+					tx_len = transfer->len - 1;
+					/* Store opcode  */
+					cmd_opcode = *(u8 *)transfer->tx_buf;
+					/* Pointing to start of TX data  */
+					buffer++;
+					/* Program the command register*/
+					amd_spi_set_opcode(master, cmd_opcode);
+					opcode_found = 1;
+				} else {
+					/* Store no. of bytes to be sent into
+					 * FIFO  */
+					tx_len = transfer->len;
+				}
+
+				/* Write data into the FIFO. */
+				for (i = 0; i < tx_len; i++) {
+					iowrite8(buffer[i],
+						 ((u8 *)amd_spi->io_remap_addr +
+						 AMD_SPI_FIFO_BASE +
+						 i + saved_index));
+				}
+
+				/* Set no. of bytes to be transmitted */
+				amd_spi_set_tx_count(master,
+						     tx_len + saved_index);
+
+				/*
+				 * Saving the index, from where next
+				 * spi_transfer's data will be stored in FIFO.
+				 */
+				saved_index = i;
+				break;
+			case RECEIVE:
+				/* Store no. of bytes to be received from
+				 * FIFO */
+				rx_len = transfer->len;
+				buffer = (u8 *)transfer->rx_buf;
+				recv_flag=1;
+				break;
+			}
+		}
+
+		/* Set the RX count to the number of bytes to expect in
+		 * response */
+		amd_spi_set_rx_count(master, rx_len );
+		amd_spi_clear_fifo_ptr(master);
+		amd_spi_dump_reg(master);
+		/* Executing command */
+		amd_spi_execute_opcode(master);
+		amd_spi_dump_reg(master);
+
+		if(recv_flag == 1) {
+			/* Read data from FIFO to receive buffer  */
+			for (i = 0; i < rx_len; i++) {
+				buffer[i] = ioread8((u8 *)amd_spi->io_remap_addr
+						    + AMD_SPI_FIFO_BASE
+						    + tx_len + i);
+			}
+
+			recv_flag = 0;
+		}
+
+		/* Update statistics */
+		message->actual_length = tx_len + rx_len + 1 ;
+		/* complete the transaction */
+		message->status = 0;
+		spi_finalize_current_message(master);
+	}
+
+	return 0;
+}
+
+static int amd_spi_pci_probe(struct pci_dev *pdev,
+			     const struct pci_device_id *id)
+{
+	struct device *dev = &pdev->dev;
+	struct spi_master *master;
+	struct amd_spi *amd_spi;
+	u32 io_base_addr;
+	int err = 0;
+
+	/* Allocate storage for spi_master and driver private data */
+	master = spi_alloc_master(dev, sizeof(struct amd_spi));
+	if (master == NULL) {
+		dev_err(dev, "Error allocating SPI master\n");
+		return -ENOMEM;
+	}
+
+	amd_spi = spi_master_get_devdata(master);
+	amd_spi->master = master;
+
+	/*
+	 * Lets first get the base address of SPI registers. The SPI Base
+	 * Address is stored at offset 0xA0 into the LPC PCI configuration
+	 * space. As per the specification, it is stored at bits 6:31 of the
+	 * register. The address is aligned at 64-byte boundary,
+	 * so we should just mask the lower 6 bits and get the address.
+	 */
+	pci_read_config_dword(pdev, AMD_PCI_LPC_SPI_BASE_ADDR_REG,
+			      &io_base_addr);
+	amd_spi->io_base_addr = io_base_addr & AMD_SPI_BASE_ADDR_MASK;
+	amd_spi->io_remap_addr = ioremap_nocache(amd_spi->io_base_addr,
+						 AMD_SPI_MEM_SIZE);
+	if (amd_spi->io_remap_addr == NULL) {
+		dev_err(dev, "ioremap of SPI registers failed\n");
+		err = -ENOMEM;
+		goto err_free_master;
+	}
+	dev_dbg(dev, "io_base_addr: 0x%.8lx, io_remap_address: %p\n",
+		amd_spi->io_base_addr, amd_spi->io_remap_addr);
+	INIT_LIST_HEAD(&amd_spi->msg_queue);
+	init_waitqueue_head(&amd_spi->wq);
+	amd_spi->kthread_spi = kthread_run(amd_spi_thread, amd_spi,
+					   "amd_spi_thread");
+
+	/* Now lets initialize the fields of spi_master */
+	master->bus_num = 0;	/*
+				 * This should be the same as passed in
+				 * spi_board_info structure
+				 */
+	master->num_chipselect = 4; /* Can be overwritten later during setup */
+	master->mode_bits = 0;
+	master->flags = 0;
+	master->setup = amd_spi_master_setup;
+	master->transfer_one_message = amd_spi_master_transfer;
+	/* Register the controller with SPI framework */
+	err = spi_register_master(master);
+	if (err) {
+		dev_err(dev, "error registering SPI controller\n");
+		goto err_iounmap;
+	}
+	pci_set_drvdata(pdev, amd_spi);
+
+	return 0;
+
+err_iounmap:
+	iounmap(amd_spi->io_remap_addr);
+err_free_master:
+	spi_master_put(master);
+
+	return 0;
+}
+
+static void amd_spi_pci_remove(struct pci_dev *pdev)
+{
+	struct amd_spi *amd_spi = pci_get_drvdata(pdev);
+
+	kthread_stop(amd_spi->kthread_spi);
+	iounmap(amd_spi->io_remap_addr);
+	spi_unregister_master(amd_spi->master);
+	spi_master_put(amd_spi->master);
+	pci_set_drvdata(pdev, NULL);
+}
+
+static struct pci_driver amd_spi_pci_driver = {
+	.name = "amd_spi",
+	.id_table = amd_spi_pci_device_id,
+	.probe = amd_spi_pci_probe,
+	.remove = amd_spi_pci_remove,
+};
+
+static int __init amd_spi_init(void)
+{
+	int ret;
+
+	pr_info("AMD SPI Driver v%s\n", SPI_VERSION);
+
+	ret = pci_register_driver(&amd_spi_pci_driver);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+module_init(amd_spi_init);
+
+static void __exit amd_spi_exit(void)
+{
+	pci_unregister_driver(&amd_spi_pci_driver);
+}
+module_exit(amd_spi_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
+MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
+MODULE_DESCRIPTION("AMD SPI Master Controller Driver");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h
new file mode 100644
index 00000000..ec58b9a8
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h
@@ -0,0 +1,28 @@
+#ifndef SPI_AMD_H
+#define SPI_AMD_H
+
+#define DRIVER_NAME	"spi_amd"
+#define SPI_VERSION	"1.0"
+
+#define AMD_SPI_CTRL0_REG		0x00
+ #define AMD_SPI_EXEC_CMD		(0x1 << 16)
+ #define AMD_SPI_OPCODE_MASK		0xFF
+ #define AMD_SPI_FIFO_CLEAR		(0x1 << 20)
+ #define AMD_SPI_BUSY			(0x1 << 31)
+#define AMD_SPI_ALT_CS_REG		0x1D
+ #define AMD_SPI_ALT_CS_MASK		0x3
+#define AMD_SPI_FIFO_BASE		0x80
+#define AMD_SPI_TX_COUNT_REG		0x48
+#define AMD_SPI_RX_COUNT_REG		0x4B
+#define AMD_SPI_STATUS_REG		0x4C
+
+#define AMD_PCI_LPC_SPI_BASE_ADDR_REG	0xA0
+#define AMD_SPI_BASE_ADDR_MASK		~0x3F
+#define AMD_SPI_MEM_SIZE		200
+
+#define PCI_DEVICE_ID_AMD_LPC_BRIDGE	0x790E
+
+#define TRANSMIT	1
+#define RECEIVE		2
+
+#endif /* SPI_AMD_H  */
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c
new file mode 100644
index 00000000..dd3538be
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c
@@ -0,0 +1,519 @@
+/*****************************************************************************
+*
+* spirom.c - SPI ROM client driver
+*
+* Copyright (c) 2014, Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*   
+***************************************************************************/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ioctl.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+
+#include <asm/uaccess.h>
+
+#include "spirom.h"
+
+#define SPIROM_VERSION	"0.2"
+
+/*
+ * SPI has a character major number assigned.  We allocate minor numbers
+ * dynamically using a bitmask.  You must use hotplug tools, such as udev
+ * (or mdev with busybox) to create and destroy the /dev/spiromB.C device
+ * nodes, since there is no fixed association of minor numbers with any
+ * particular SPI bus or device.
+ */
+#define SPIROM_MAJOR			153	/* assigned */
+#define N_SPI_MINORS			32	/* ... up to 256 */
+
+#define SPI_BUS		0
+#define SPI_BUS_CS1	0
+
+static unsigned long	minors[N_SPI_MINORS / BITS_PER_LONG];
+
+
+struct spirom_data {
+	dev_t			devt;
+	spinlock_t		spi_lock;
+	struct spi_device	*spi;
+	struct list_head	device_entry;
+	struct completion	done;
+
+	struct mutex		buf_lock;
+	unsigned		users;
+};
+
+static LIST_HEAD(device_list);
+static DEFINE_MUTEX(device_list_lock);
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * We can't use the standard synchronous wrappers for file I/O; we
+ * need to protect against async removal of the underlying spi_device.
+ */
+static void spirom_complete(void *arg)
+{
+	complete(arg);
+}
+
+static ssize_t
+spirom_sync(struct spirom_data *spirom, struct spi_message *message)
+{
+	int status;
+
+	message->complete = spirom_complete;
+	message->context = &spirom->done;
+
+	spin_lock_irq(&spirom->spi_lock);
+	if (spirom->spi == NULL)
+		status = -ESHUTDOWN;
+	else
+		status = spi_async(spirom->spi, message);
+	spin_unlock_irq(&spirom->spi_lock);
+
+	if (status == 0) {
+		/*
+		 * There might be cases where the controller driver has been
+		 * unloaded in the middle of a transaction. So we might end up
+		 * in a situation where we will be waiting for an event which
+		 * will never happen. So we provide a timeout of 1 second for
+		 * situations like this.
+		 */
+		wait_for_completion_timeout(&spirom->done, HZ);
+		status = message->status;
+		if (status == 0)
+			status = message->actual_length;
+	}
+	return status;
+}
+
+static int spirom_message(struct spirom_data *spirom,
+		struct spi_ioc_transfer *u_trans, unsigned long arg)
+{
+	struct spi_message msg;
+	struct spi_transfer *transfer;
+	u8 *buffer;
+	int status = u_trans->len;
+
+	buffer = u_trans->buf;
+	spi_message_init(&msg);
+
+	/* The very first spi_transfer will contain the command only */
+	transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL);
+	if (!transfer)
+		return -ENOMEM;
+
+	transfer->tx_buf = buffer;
+	transfer->len = 1;
+	buffer += transfer->len;
+	spi_message_add_tail(transfer, &msg);
+
+	/*
+	 * If the command expects an address as its argument, we populate
+	 * it in the very next spi_transfer.
+	 */
+	if (u_trans->addr_present) {
+		transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL);
+		if (!transfer)
+			return -ENOMEM;
+
+		transfer->tx_buf = buffer;
+		transfer->len = 3; // 3-byte address
+		buffer += transfer->len;
+		spi_message_add_tail(transfer, &msg);
+	}
+
+	/*
+	 * Next is data, which can have a maximum of 64-bytes, the size limited
+	 * by the number of bytes that can stored in the controller FIFO.
+	 */
+	if (u_trans->len) {
+		transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL);
+		if (!transfer)
+			return -ENOMEM;
+
+		if (u_trans->direction == TRANSMIT)
+			transfer->tx_buf = buffer;
+		else if (u_trans->direction == RECEIVE)
+			transfer->rx_buf = buffer;
+
+		transfer->len = u_trans->len;
+		/* No need to increment buffer pointer */
+		spi_message_add_tail(transfer, &msg);
+	}
+
+	status = spirom_sync(spirom, &msg);
+
+	if (u_trans->direction == RECEIVE) {
+		/*
+		 * The received data should have been populated in
+		 * u_trans->buf, so we just need to copy it into the
+		 * user-space buffer.
+		 */
+		buffer = u_trans->buf;
+		if (u_trans->addr_present) {
+			buffer += 4; // 1-byte command and 3-byte address
+			if(__copy_to_user((u8 __user *)
+				(((struct spi_ioc_transfer *)arg)->buf) + 4,
+				buffer, u_trans->len)) {
+				status = -EFAULT;
+			}
+		} else {
+			buffer += 1; // 1-byte command only
+			if(__copy_to_user((u8 __user *)
+				(((struct spi_ioc_transfer *)arg)->buf) + 1,
+				buffer, u_trans->len)) {
+				status = -EFAULT;
+			}
+		}
+	}
+
+	/* Done with everything, free the memory taken by spi_transfer */
+	while (msg.transfers.next != &msg.transfers) {
+		transfer = list_entry(msg.transfers.next, struct spi_transfer,
+				      transfer_list);
+		msg.transfers.next = transfer->transfer_list.next;
+		transfer->transfer_list.next->prev = &msg.transfers;
+		kfree(transfer);
+	}
+
+	return status;
+}
+
+static long
+spirom_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	int			err = 0;
+	int			retval = 0;
+	struct spirom_data	*spirom;
+	struct spi_device	*spi;
+	u32			tmp;
+	struct spi_ioc_transfer	*ioc;
+
+	/* Check type and command number */
+	if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC)
+		return -ENOTTY;
+
+	/* Check access direction once here; don't repeat below.
+	 * IOC_DIR is from the user perspective, while access_ok is
+	 * from the kernel perspective; so they look reversed.
+	 */
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		err = !access_ok(VERIFY_WRITE,
+				(void __user *)arg, _IOC_SIZE(cmd));
+	if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE)
+		err = !access_ok(VERIFY_READ,
+				(void __user *)arg, _IOC_SIZE(cmd));
+	if (err)
+		return -EFAULT;
+
+	/* guard against device removal before, or while,
+	 * we issue this ioctl.
+	 */
+	spirom = filp->private_data;
+	spin_lock_irq(&spirom->spi_lock);
+	spi = spi_dev_get(spirom->spi);
+	spin_unlock_irq(&spirom->spi_lock);
+
+	if (spi == NULL)
+		return -ESHUTDOWN;
+
+	/* use the buffer lock here for triple duty:
+	 *  - prevent I/O (from us) so calling spi_setup() is safe;
+	 *  - prevent concurrent SPI_IOC_WR_* from morphing
+	 *    data fields while SPI_IOC_RD_* reads them;
+	 *  - SPI_IOC_MESSAGE needs the buffer locked "normally".
+	 */
+	mutex_lock(&spirom->buf_lock);
+
+	/* segmented and/or full-duplex I/O request */
+	if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) ||
+	    _IOC_DIR(cmd) !=_IOC_WRITE) {
+		retval = -ENOTTY;
+		goto out;
+	}
+
+	tmp = sizeof(struct spi_ioc_transfer);
+
+	/* copy into scratch area */
+	ioc = kzalloc(tmp, GFP_KERNEL);
+	if (!ioc) {
+		retval = -ENOMEM;
+		goto out;
+	}
+	if (__copy_from_user(ioc, (struct spi_ioc_transfer __user *)arg,
+	    tmp)) {
+		kfree(ioc);
+		retval = -EFAULT;
+		goto out;
+	}
+
+	/* translate to spi_message, execute */
+	retval = spirom_message(spirom, ioc, arg);
+	kfree(ioc);
+
+out:
+	mutex_unlock(&spirom->buf_lock);
+	spi_dev_put(spi);
+	return retval;
+}
+
+static int spirom_open(struct inode *inode, struct file *filp)
+{
+	struct spirom_data	*spirom;
+	int			status = -ENXIO;
+
+	mutex_lock(&device_list_lock);
+
+	list_for_each_entry(spirom, &device_list, device_entry) {
+		if (spirom->devt == inode->i_rdev) {
+			status = 0;
+			break;
+		}
+	}
+	if (status == 0) {
+		if (status == 0) {
+			spirom->users++;
+			filp->private_data = spirom;
+			nonseekable_open(inode, filp);
+		}
+	} else
+		pr_debug("spirom: nothing for minor %d\n", iminor(inode));
+
+	mutex_unlock(&device_list_lock);
+	return status;
+}
+
+static int spirom_release(struct inode *inode, struct file *filp)
+{
+	struct spirom_data	*spirom;
+	int			status = 0;
+
+	mutex_lock(&device_list_lock);
+	spirom = filp->private_data;
+	filp->private_data = NULL;
+
+	/* last close? */
+	spirom->users--;
+	if (!spirom->users) {
+		int		dofree;
+
+		/* ... after we unbound from the underlying device? */
+		spin_lock_irq(&spirom->spi_lock);
+		dofree = (spirom->spi == NULL);
+		spin_unlock_irq(&spirom->spi_lock);
+
+		if (dofree)
+			kfree(spirom);
+	}
+	mutex_unlock(&device_list_lock);
+
+	return status;
+}
+
+static const struct file_operations spirom_fops = {
+	.owner =	THIS_MODULE,
+	.unlocked_ioctl = spirom_ioctl,
+	.open =		spirom_open,
+	.release =	spirom_release,
+};
+
+static int __init add_spi_device_to_bus(void)
+{
+	struct spi_master *spi_master;
+	struct spi_device *spi_device;
+	struct spi_board_info spi_info;
+
+	spi_master = spi_busnum_to_master(SPI_BUS);
+	if (!spi_master) {
+		printk(KERN_ALERT "Please make sure to \'modprobe "
+			"spi_amd\' driver first\n");
+		return -1;
+	}
+	memset(&spi_info, 0, sizeof(struct spi_board_info));
+
+	strlcpy(spi_info.modalias, "spirom", SPI_NAME_SIZE);
+	spi_info.bus_num = SPI_BUS; //Bus number of SPI master
+	spi_info.chip_select = SPI_BUS_CS1; //CS on which SPI device is connected
+
+	spi_device = spi_new_device(spi_master, &spi_info);
+	if (!spi_device)
+		return -ENODEV;
+
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* The main reason to have this class is to make mdev/udev create the
+ * /dev/spiromB.C character device nodes exposing our userspace API.
+ * It also simplifies memory management.
+ */
+
+static struct class *spirom_class;
+
+/*-------------------------------------------------------------------------*/
+
+static int spirom_probe(struct spi_device *spi)
+{
+	struct spirom_data	*spirom;
+	int			status;
+	unsigned long		minor;
+
+	/* Allocate driver data */
+	spirom = kzalloc(sizeof(*spirom), GFP_KERNEL);
+	if (!spirom)
+		return -ENOMEM;
+
+	/* Initialize the driver data */
+	spirom->spi = spi;
+	spin_lock_init(&spirom->spi_lock);
+	mutex_init(&spirom->buf_lock);
+
+	INIT_LIST_HEAD(&spirom->device_entry);
+	init_completion(&spirom->done);
+
+	/* If we can allocate a minor number, hook up this device.
+	 * Reusing minors is fine so long as udev or mdev is working.
+	 */
+	mutex_lock(&device_list_lock);
+	minor = find_first_zero_bit(minors, N_SPI_MINORS);
+	if (minor < N_SPI_MINORS) {
+		struct device *dev;
+
+		spirom->devt = MKDEV(SPIROM_MAJOR, minor);
+		dev = device_create(spirom_class, &spi->dev, spirom->devt,
+				    spirom, "spirom%d.%d",
+				    spi->master->bus_num, spi->chip_select);
+		status = IS_ERR(dev) ? PTR_ERR(dev) : 0;
+	} else {
+		dev_dbg(&spi->dev, "no minor number available!\n");
+		status = -ENODEV;
+	}
+	if (status == 0) {
+		set_bit(minor, minors);
+		list_add(&spirom->device_entry, &device_list);
+	}
+	mutex_unlock(&device_list_lock);
+
+	if (status == 0)
+		spi_set_drvdata(spi, spirom);
+	else
+		kfree(spirom);
+
+	return status;
+}
+
+static int spirom_remove(struct spi_device *spi)
+{
+	struct spirom_data	*spirom = spi_get_drvdata(spi);
+
+	/* make sure ops on existing fds can abort cleanly */
+	spin_lock_irq(&spirom->spi_lock);
+	spirom->spi = NULL;
+	spi_set_drvdata(spi, NULL);
+	spin_unlock_irq(&spirom->spi_lock);
+
+	/* prevent new opens */
+	mutex_lock(&device_list_lock);
+	list_del(&spirom->device_entry);
+	clear_bit(MINOR(spirom->devt), minors);
+	device_destroy(spirom_class, spirom->devt);
+	if (spirom->users == 0)
+		kfree(spirom);
+	mutex_unlock(&device_list_lock);
+
+	return 0;
+}
+
+static struct spi_driver spirom_spi = {
+	.driver = {
+		.name =		"spirom",
+		.owner =	THIS_MODULE,
+	},
+	.probe =	spirom_probe,
+	.remove =	spirom_remove,
+
+	/* NOTE:  suspend/resume methods are not necessary here.
+	 * We don't do anything except pass the requests to/from
+	 * the underlying controller.  The refrigerator handles
+	 * most issues; the controller driver handles the rest.
+	 */
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int __init spirom_init(void)
+{
+	int status;
+
+	pr_info("AMD SPIROM Driver v%s\n", SPIROM_VERSION);
+
+	/* Claim our 256 reserved device numbers.  Then register a class
+	 * that will key udev/mdev to add/remove /dev nodes.  Last, register
+	 * the driver which manages those device numbers.
+	 */
+	BUILD_BUG_ON(N_SPI_MINORS > 256);
+	status = register_chrdev(SPIROM_MAJOR, "spi", &spirom_fops);
+	if (status < 0)
+		return status;
+
+	spirom_class = class_create(THIS_MODULE, "spirom");
+	if (IS_ERR(spirom_class)) {
+		unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
+		return PTR_ERR(spirom_class);
+	}
+
+	status = spi_register_driver(&spirom_spi);
+	if (status < 0) {
+		class_destroy(spirom_class);
+		unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
+	}
+
+	status = add_spi_device_to_bus();
+	if (status < 0) {
+		spi_unregister_driver(&spirom_spi);
+		class_destroy(spirom_class);
+		unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
+	}
+
+	return status;
+}
+module_init(spirom_init);
+
+static void __exit spirom_exit(void)
+{
+	spi_unregister_driver(&spirom_spi);
+	class_destroy(spirom_class);
+	unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
+}
+module_exit(spirom_exit);
+
+MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
+MODULE_DESCRIPTION("User mode SPI ROM interface");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("spi:spirom");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h
new file mode 100644
index 00000000..941b357a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h
@@ -0,0 +1,53 @@
+#ifndef SPIROM_H
+#define SPIROM_H
+
+#include <linux/types.h>
+
+/*---------------------------------------------------------------------------*/
+
+/* IOCTL commands */
+
+#define SPI_IOC_MAGIC			'k'
+
+#define TRANSMIT	1
+#define RECEIVE		2
+
+/*
+ * struct spi_ioc_transfer - interface structure between application and ioctl
+ *
+ * @buf: Buffer to hold 1-byte command, 3-bytes address, and 64-byte data for
+ *       transmit or receive. The internal FIFO of our controller can hold a
+ *       maximum of 70 bytes, including the address. But here we assume the
+ *       maximum data excluding address to be 64-bytes long.
+ *
+ * @direction: Direction of data transfer, either TRANSMIT or RECEIVE.
+ *
+ * @len: Length of data excluding command and address.
+ *
+ * @addr_present: Flag to indicate whether 'buf' above contains an address.
+ */
+struct spi_ioc_transfer {
+	__u8		buf[64 + 1 + 3];
+	__u8		direction;
+	__u8		len;
+	__u8		addr_present;
+};
+
+/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
+#define SPI_MSGSIZE(N) \
+	((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
+		? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
+#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
+
+/* SPI ROM command codes */
+#define ROM_WREN		0x06
+#define ROM_WRDI		0x04
+#define ROM_RDSR		0x05
+#define ROM_RDID		0x9F
+#define ROM_CHIP_ERASE		0x60
+#define ROM_SECTOR_ERASE	0x20
+#define ROM_BLOCK_ERASE		0xD8
+#define ROM_READ		0x03
+#define ROM_WRITE		0x02
+
+#endif /* SPIROM_H */
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/kernel-module-amd-spi_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-spi/kernel-module-amd-spi_1.0.bb
new file mode 100644
index 00000000..b0cdc4f0
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-spi/kernel-module-amd-spi_1.0.bb
@@ -0,0 +1,33 @@
+DESCRIPTION = "This kernel module provides support for AMD SPI controller driver"
+LICENSE = "BSD | GPLv2"
+LIC_FILES_CHKSUM = "file://spi_amd.c;md5=80f01f3b969d0b1d633df6ba9edf4170 \
+                    file://spi_amd.h;md5=488f986ada9e64f6b5ee6d55c269ae1b \
+                    file://spirom.c;md5=ec2142faf7c64a85563fcaa129772fc0 \
+                    file://spirom.h;md5=8de0c535224dbd8ecd2f40ef29c15d0a \
+		    file://Makefile;md5=8ea80a6d4ae15bcf922d090df6cfdd4c \
+		   "
+
+inherit module
+
+PR = "r0"
+PV = "1.0"
+
+SRC_URI = "file://Makefile \
+           file://spi_amd.c \
+           file://spi_amd.h \
+           file://spirom.c \
+           file://spirom.h \
+          "
+
+S = "${WORKDIR}"
+
+
+# Kernel module packages MUST begin with 'kernel-module-', otherwise
+# multilib image generation can fail.
+#
+# The following line is only necessary if the recipe name does not begin
+# with kernel-module-.
+#
+PKG_${PN} = "kernel-module-${PN}"
+
+FILES_${PN} += "${sysconfdir}"
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile
new file mode 100644
index 00000000..36b32f87
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile
@@ -0,0 +1,14 @@
+obj-m := amd_wdt.o
+
+SRC := $(shell pwd)
+
+all:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC)
+
+modules_install:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
+
+clean:
+	rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
+	rm -f Module.markers Module.symvers modules.order
+	rm -rf .tmp_versions Modules.symvers
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c
new file mode 100644
index 00000000..82329fe3
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c
@@ -0,0 +1,418 @@
+/*****************************************************************************
+*
+* Copyright (c) 2014, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+***************************************************************************/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
+#include <linux/watchdog.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include "amd_wdt.h"
+
+/* internal variables */
+static u32 wdtbase_phys;
+static void __iomem *wdtbase;
+static DEFINE_SPINLOCK(wdt_lock);
+static struct pci_dev *amd_wdt_pci;
+
+/* watchdog platform device */
+static struct platform_device *amd_wdt_platform_device;
+
+/* module parameters */
+static int heartbeat = AMD_WDT_DEFAULT_TIMEOUT;
+module_param(heartbeat, int, 0);
+MODULE_PARM_DESC(heartbeat, "Watchdog timeout in frequency units. "
+		 "(default="  __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
+
+static char frequency[MAX_LENGTH] = "1s";
+module_param_string(frequency, frequency, MAX_LENGTH, 0);
+MODULE_PARM_DESC(frequency, "Watchdog timer frequency units (32us, "
+		 "10ms, 100ms, 1s). (default=1s)");
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
+		" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+static char action[MAX_LENGTH] = "reboot";
+module_param_string(action, action, MAX_LENGTH, 0);
+MODULE_PARM_DESC(action, "Watchdog action (reboot/shutdown). (default=reboot) ");
+
+/*
+ * Watchdog specific functions
+ */
+static int amd_wdt_set_timeout(struct watchdog_device *wdt_dev, unsigned int t)
+{
+	unsigned long flags;
+
+	/*
+	 * In ideal cases the limits will be checked by Watchdog core itself,
+	 * but there might be cases when we call this function directly from
+	 * somewhere else. So check the limits here.
+	 */
+	if (t < AMD_WDT_MIN_TIMEOUT)
+		heartbeat = t = AMD_WDT_MIN_TIMEOUT;
+	else if (t > AMD_WDT_MAX_TIMEOUT)
+		heartbeat = t = AMD_WDT_MAX_TIMEOUT;
+
+	/* Write new timeout value to watchdog */
+	spin_lock_irqsave(&wdt_lock, flags);
+	writel(t, AMD_WDT_COUNT(wdtbase));
+	spin_unlock_irqrestore(&wdt_lock, flags);
+
+	wdt_dev->timeout = t;
+
+	return 0;
+}
+
+static int amd_wdt_ping(struct watchdog_device *wdt_dev)
+{
+	u32 val;
+	unsigned long flags;
+
+	/* Trigger watchdog */
+	spin_lock_irqsave(&wdt_lock, flags);
+
+	val = readl(AMD_WDT_CONTROL(wdtbase));
+	val |= AMD_WDT_TRIGGER_BIT;
+	writel(val, AMD_WDT_CONTROL(wdtbase));
+
+	spin_unlock_irqrestore(&wdt_lock, flags);
+
+	return 0;
+}
+
+static int amd_wdt_start(struct watchdog_device *wdt_dev)
+{
+	u32 val;
+	unsigned long flags;
+
+	/* Enable the watchdog timer */
+	spin_lock_irqsave(&wdt_lock, flags);
+
+	val = readl(AMD_WDT_CONTROL(wdtbase));
+	val |= AMD_WDT_START_STOP_BIT;
+	writel(val, AMD_WDT_CONTROL(wdtbase));
+
+	spin_unlock_irqrestore(&wdt_lock, flags);
+
+	/* Trigger the watchdog timer */
+	amd_wdt_ping(wdt_dev);
+
+	return 0;
+}
+
+static int amd_wdt_stop(struct watchdog_device *wdt_dev)
+{
+	u32 val;
+	unsigned long flags;
+
+	/* Disable the watchdog timer */
+	spin_lock_irqsave(&wdt_lock, flags);
+
+	val = readl(AMD_WDT_CONTROL(wdtbase));
+	val &= ~AMD_WDT_START_STOP_BIT; 
+	writel(val, AMD_WDT_CONTROL(wdtbase));
+
+	spin_unlock_irqrestore(&wdt_lock, flags);
+
+	return 0;
+}
+
+static unsigned int amd_wdt_get_timeleft(struct watchdog_device *wdt_dev)
+{
+	u32 val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&wdt_lock, flags);
+	val = readl(AMD_WDT_COUNT(wdtbase));
+	spin_unlock_irqrestore(&wdt_lock, flags);
+
+	/* Mask out the upper 16-bits and return */
+	return val & AMD_WDT_COUNT_MASK;
+}
+
+static unsigned int amd_wdt_status(struct watchdog_device *wdt_dev)
+{
+	return wdt_dev->status;
+}
+
+static struct watchdog_ops amd_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= amd_wdt_start,
+	.stop		= amd_wdt_stop,
+	.ping		= amd_wdt_ping,
+	.status		= amd_wdt_status,
+	.set_timeout	= amd_wdt_set_timeout,
+	.get_timeleft	= amd_wdt_get_timeleft,
+};
+static struct watchdog_info amd_wdt_info = {
+	.options		= WDIOF_SETTIMEOUT |
+				  WDIOF_MAGICCLOSE |
+				  WDIOF_KEEPALIVEPING,
+	.firmware_version	= 0,
+	.identity		= WDT_MODULE_NAME,
+};
+
+static struct watchdog_device amd_wdt_dev = {
+	.info		= &amd_wdt_info,
+	.ops		= &amd_wdt_ops,
+};
+
+/*
+ * The PCI Device ID table below is used to identify the platform
+ * the driver is supposed to work for. Since this is a platform
+ * device, we need a way for us to be able to find the correct
+ * platform when the driver gets loaded, otherwise we should
+ * bail out.
+ */
+static DEFINE_PCI_DEVICE_TABLE(amd_wdt_pci_tbl) = {
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CARRIZO_SMBUS, PCI_ANY_ID,
+	  PCI_ANY_ID, },
+	{ 0, },
+};
+MODULE_DEVICE_TABLE(pci, amd_wdt_pci_tbl);
+
+static unsigned char amd_wdt_setupdevice(void)
+{
+	struct pci_dev *dev = NULL;
+	u32 val;
+
+	/* Match the PCI device */
+	for_each_pci_dev(dev) {
+		if (pci_match_id(amd_wdt_pci_tbl, dev) != NULL) {
+			amd_wdt_pci = dev;
+			break;
+		}
+	}
+
+	if (!amd_wdt_pci)
+		return 0;
+
+	/* Watchdog Base Address starts from ACPI MMIO Base Address + 0xB00 */
+	wdtbase_phys = AMD_ACPI_MMIO_BASE + AMD_WDT_MEM_MAP_OFFSET;
+	if (!request_mem_region_exclusive(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE,
+					  "AMD Watchdog")) {
+		pr_err("mmio address 0x%04x already in use\n", wdtbase_phys);
+		goto exit;
+	}
+
+	wdtbase = ioremap(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
+	if (!wdtbase) {
+		pr_err("failed to get wdtbase address\n");
+		goto unreg_mem_region;
+	}
+
+	/* Enable watchdog timer and decode bit */
+	outb(AMD_PM_WATCHDOG_EN_REG, AMD_IO_PM_INDEX_REG);
+	val = inb(AMD_IO_PM_DATA_REG);
+	val |= AMD_PM_WATCHDOG_TIMER_EN;
+	outb(val, AMD_IO_PM_DATA_REG);
+
+	/* Set the watchdog timer resolution */
+	outb(AMD_PM_WATCHDOG_CONFIG_REG, AMD_IO_PM_INDEX_REG);
+	val = inb(AMD_IO_PM_DATA_REG);
+	/* Clear the previous frequency setting, if any */
+	val &= ~AMD_PM_WATCHDOG_CONFIG_MASK;
+
+	/*
+	 * Now set the frequency depending on the module load parameter.
+	 * In case the user passes an invalid argument, we consider the
+	 * frequency to be of 1 second resolution.
+	 */
+	if (strncmp(frequency, "32us", 4) == 0)
+		val |= AMD_PM_WATCHDOG_32USEC_RES;
+	else if (strncmp(frequency, "10ms", 4) == 0)
+		val |= AMD_PM_WATCHDOG_10MSEC_RES;
+	else if (strncmp(frequency, "100ms", 5) == 0)
+		val |= AMD_PM_WATCHDOG_100MSEC_RES;
+	else {
+		val |= AMD_PM_WATCHDOG_1SEC_RES;
+		if (strncmp(frequency, "1s", 2) != 0)
+			strncpy(frequency, "1s", 2);
+	}
+
+	outb(val, AMD_IO_PM_DATA_REG);
+
+	/* Check to see if last reboot was due to watchdog timeout */
+	val = readl(AMD_WDT_CONTROL(wdtbase));
+	if (val & AMD_WDT_FIRED_BIT)
+		amd_wdt_dev.bootstatus |= WDIOF_CARDRESET;
+	else
+		amd_wdt_dev.bootstatus &= ~WDIOF_CARDRESET;
+
+	pr_info("Watchdog reboot %sdetected\n",
+		(val & AMD_WDT_FIRED_BIT) ? "" : "not ");
+
+	/* Clear out the old status */
+	val |= AMD_WDT_FIRED_BIT;
+
+	/*
+	 * Set the watchdog action depending on module load parameter.
+	 *
+	 * If action is specified anything other than reboot or shutdown,
+	 * we default it to reboot.
+	 */
+	if (strncmp(action, "shutdown", 8) == 0)
+		val |= AMD_WDT_ACTION_RESET_BIT;
+	else {
+		val &= ~AMD_WDT_ACTION_RESET_BIT;
+		/* The statement below is required for when the action
+		 * is set anything other than reboot.
+		 */
+		if (strncmp(action, "reboot", 6) != 0)
+			strncpy(action, "reboot", 6);
+	}
+
+	writel(val, AMD_WDT_CONTROL(wdtbase));
+
+	return 1;
+
+unreg_mem_region:
+	release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
+exit:
+	return 0;
+}
+
+static int amd_wdt_init(struct platform_device *dev)
+{
+	int ret;
+	u32 val;
+
+	/* Identify our device and initialize watchdog hardware */
+	if (!amd_wdt_setupdevice())
+		return -ENODEV;
+
+	amd_wdt_dev.timeout = heartbeat;
+	amd_wdt_dev.min_timeout = AMD_WDT_MIN_TIMEOUT;
+	amd_wdt_dev.max_timeout = AMD_WDT_MAX_TIMEOUT;
+	watchdog_set_nowayout(&amd_wdt_dev, nowayout);
+
+	/* Make sure watchdog is not running */
+	amd_wdt_stop(&amd_wdt_dev);
+
+	/* Set Watchdog timeout */
+	amd_wdt_set_timeout(&amd_wdt_dev, heartbeat);
+
+	ret = watchdog_register_device(&amd_wdt_dev);
+	if (ret != 0) {
+		pr_err("Watchdog timer: cannot register watchdog device"
+		       " (err=%d)\n", ret);
+		goto exit;
+	}
+
+		pr_info("initialized (0x%p). (timeout=%d units) (frequency=%s) "
+		"(nowayout=%d) (action=%s)\n", wdtbase, heartbeat, frequency,
+		nowayout, action);
+
+	return 0;
+
+exit:
+	iounmap(wdtbase);
+	release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
+	return ret;
+}
+
+static void amd_wdt_cleanup(void)
+{
+	/* Stop the timer before we leave */
+	if (!nowayout)
+		amd_wdt_stop(NULL);
+
+	watchdog_unregister_device(&amd_wdt_dev);
+	iounmap(wdtbase);
+	release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
+}
+
+static int amd_wdt_remove(struct platform_device *dev)
+{
+	if (wdtbase)
+		amd_wdt_cleanup();
+
+	return 0;
+}
+
+static void amd_wdt_shutdown(struct platform_device *dev)
+{
+	amd_wdt_stop(NULL);
+}
+
+static struct platform_driver amd_wdt_driver = {
+	.probe		= amd_wdt_init,
+	.remove		= amd_wdt_remove,
+	.shutdown	= amd_wdt_shutdown,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= WDT_MODULE_NAME,
+	},
+};
+
+static int __init amd_wdt_init_module(void)
+{
+	int err;
+
+	pr_info("AMD WatchDog Timer Driver v%s\n", WDT_VERSION);
+
+	err = platform_driver_register(&amd_wdt_driver);
+	if (err)
+		return err;
+
+	amd_wdt_platform_device = platform_device_register_simple(
+					WDT_MODULE_NAME, -1, NULL, 0);
+	if (IS_ERR(amd_wdt_platform_device)) {
+		err = PTR_ERR(amd_wdt_platform_device);
+		goto unreg_platform_driver;
+	}
+
+	return 0;
+
+unreg_platform_driver:
+	platform_driver_unregister(&amd_wdt_driver);
+	return err;
+}
+
+static void __exit amd_wdt_cleanup_module(void)
+{
+	platform_device_unregister(amd_wdt_platform_device);
+	platform_driver_unregister(&amd_wdt_driver);
+	pr_info("AMD Watchdog Module Unloaded\n");
+}
+
+module_init(amd_wdt_init_module);
+module_exit(amd_wdt_cleanup_module);
+
+MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
+MODULE_DESCRIPTION("Watchdog timer driver for AMD chipsets");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h
new file mode 100644
index 00000000..855e6810
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h
@@ -0,0 +1,46 @@
+#ifndef _AMD_WDT_H_
+#define _AMD_WDT_H_
+
+/* Module and version information */
+#define WDT_VERSION "1.0"
+#define WDT_MODULE_NAME "AMD watchdog timer"
+#define WDT_DRIVER_NAME   WDT_MODULE_NAME ", v" WDT_VERSION
+
+#define AMD_WDT_DEFAULT_TIMEOUT		60	/* 60 units default heartbeat. */
+#define AMD_WDT_MIN_TIMEOUT	0x0001	/* minimum timeout value */
+#define AMD_WDT_MAX_TIMEOUT	0xFFFF	/* maximum timeout value */
+#define MAX_LENGTH		(8 + 1)	/* shutdown has 8 characters + NULL character */
+
+/* Watchdog register definitions */
+#define AMD_ACPI_MMIO_BASE		0xFED80000
+#define AMD_WDT_MEM_MAP_OFFSET		0xB00
+#define AMD_WDT_MEM_MAP_SIZE		0x100
+
+#define AMD_WDT_CONTROL(base)		((base) + 0x00) /* Watchdog Control */
+ #define AMD_WDT_START_STOP_BIT		(1 << 0)
+ #define AMD_WDT_FIRED_BIT		(1 << 1)
+ #define AMD_WDT_ACTION_RESET_BIT	(1 << 2)
+ #define AMD_WDT_DISABLE_BIT		(1 << 3)
+ /* 6:4 bits Reserved */
+ #define AMD_WDT_TRIGGER_BIT		(1 << 7)
+#define AMD_WDT_COUNT(base)		((base) + 0x04) /* Watchdog Count */
+ #define AMD_WDT_COUNT_MASK		0xFFFF
+
+#define AMD_PM_WATCHDOG_EN_REG		0x00
+ #define AMD_PM_WATCHDOG_TIMER_EN	(0x01 << 7)
+
+#define AMD_PM_WATCHDOG_CONFIG_REG	0x03
+ #define AMD_PM_WATCHDOG_32USEC_RES	0x0
+ #define AMD_PM_WATCHDOG_10MSEC_RES	0x1
+ #define AMD_PM_WATCHDOG_100MSEC_RES	0x2
+ #define AMD_PM_WATCHDOG_1SEC_RES	0x3
+#define AMD_PM_WATCHDOG_CONFIG_MASK	0x3
+
+/* IO port address for indirect access using ACPI PM registers */
+#define AMD_IO_PM_INDEX_REG		0xCD6
+#define AMD_IO_PM_DATA_REG		0xCD7
+
+#define AMD_ACPI_MMIO_ADDR_MASK		~0x1FFF
+#define PCI_DEVICE_ID_AMD_CARRIZO_SMBUS 0x790B
+
+#endif /* _AMD_WDT_H_ */
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/kernel-module-amd-wdt_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-wdt/kernel-module-amd-wdt_1.0.bb
new file mode 100644
index 00000000..433b70ab
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/amd-wdt/kernel-module-amd-wdt_1.0.bb
@@ -0,0 +1,28 @@
+DESCRIPTION = "This kernel module provides support for AMD Watchdog driver"
+LICENSE = "BSD | GPLv2"
+LIC_FILES_CHKSUM = "file://amd_wdt.c;md5=b29790cbc2f022e868ca443bdd03858a \
+                    file://amd_wdt.h;md5=a9f4cbcd9c7179dbe5e1444bbf764a53 \
+                    file://Makefile;md5=111ec65dfed99f6cd330ccb4957fb924 \
+                   "
+
+inherit module
+
+PR = "r0"
+PV = "1.0"
+
+SRC_URI = "file://Makefile \
+           file://amd_wdt.c \
+           file://amd_wdt.h \
+          "
+
+S = "${WORKDIR}"
+
+# Kernel module packages MUST begin with 'kernel-module-', otherwise
+# multilib image generation can fail.
+#
+# The following line is only necessary if the recipe name does not begin
+# with kernel-module-.
+#
+PKG_${PN} = "kernel-module-${PN}"
+
+FILES_${PN} += "${sysconfdir}"
diff --git a/meta-amdfalconx86/recipes-kernel/gpio-load/amd-gpio-load_1.0.bb b/meta-amdfalconx86/recipes-kernel/gpio-load/amd-gpio-load_1.0.bb
new file mode 100644
index 00000000..eba925e4
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/gpio-load/amd-gpio-load_1.0.bb
@@ -0,0 +1,17 @@
+DESCRIPTION = "Configuration file to pass module load parameters to AMD GPIO driver"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
+
+SRC_URI = "file://modprobe.d/gpio-amd.conf"
+
+PR = "r0"
+PV = "1.0"
+
+S = "${WORKDIR}"
+
+do_install() {
+    install -d ${D}/${sysconfdir}/modprobe.d/
+    install -m 0644 modprobe.d/gpio-amd.conf ${D}${sysconfdir}/modprobe.d/
+}
+
+FILES_${PN} = "${sysconfdir}/modprobe.d"
diff --git a/meta-amdfalconx86/recipes-kernel/gpio-load/files/modprobe.d/gpio-amd.conf b/meta-amdfalconx86/recipes-kernel/gpio-load/files/modprobe.d/gpio-amd.conf
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/gpio-load/files/modprobe.d/gpio-amd.conf
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb
new file mode 100644
index 00000000..4b76e058
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb
@@ -0,0 +1,35 @@
+DESCRIPTION = "These binaries provide kernel support for newer AMD GPUs"
+SECTION = "kernel"
+LICENSE = "Proprietary"
+
+SRC_URI = "file://carrizo_ce.bin \
+	   file://carrizo_me.bin \
+	   file://carrizo_mec2.bin \
+	   file://carrizo_mec.bin \
+	   file://carrizo_pfp.bin \
+	   file://carrizo_rlc.bin \
+	   file://carrizo_sdma1.bin \
+	   file://carrizo_sdma.bin \
+	   file://carrizo_uvd.bin \
+	   file://carrizo_vce.bin \
+	   file://LICENSE.radeon \
+	  "
+
+LIC_FILES_CHKSUM = "file://LICENSE.radeon;md5=07b0c31777bd686d8e1609c6940b5e74"
+
+S = "${WORKDIR}"
+
+# Since, no binaries are generated for a specific target, 
+# inherit allarch to simply populate prebuilt binaries
+inherit allarch
+
+do_compile() {
+	:
+}
+
+do_install() {
+	install -v -m 444 -D ${S}/LICENSE.radeon ${D}/lib/firmware/radeon/LICENSE.radeon
+	install -v -m 0644 ${S}/*.bin ${D}/lib/firmware/radeon/
+}
+
+FILES_${PN} = "/lib/firmware/*"
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE.radeon b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE.radeon
new file mode 100644
index 00000000..fe3780b3
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE.radeon
@@ -0,0 +1,51 @@
+Copyright (C) 2009-2014  Advanced Micro Devices, Inc. All rights reserved.
+
+REDISTRIBUTION: Permission is hereby granted, free of any license fees,
+to any person obtaining a copy of this microcode (the "Software"), to
+install, reproduce, copy and distribute copies, in binary form only, of
+the Software and to permit persons to whom the Software is provided to
+do the same, provided that the following conditions are met:
+
+No reverse engineering, decompilation, or disassembly of this Software
+is permitted.
+
+Redistributions must reproduce the above copyright notice, this
+permission notice, and the following disclaimers and notices in the
+Software documentation and/or other materials provided with the
+Software.
+
+DISCLAIMER: THE USE OF THE SOFTWARE IS AT YOUR SOLE RISK.  THE SOFTWARE
+IS PROVIDED "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND COPYRIGHT
+HOLDER AND ITS LICENSORS EXPRESSLY DISCLAIM ALL WARRANTIES, EXPRESS AND
+IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT THAT THE SOFTWARE WILL
+MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE SOFTWARE WILL BE
+UNINTERRUPTED OR ERROR-FREE.  THE ENTIRE RISK ASSOCIATED WITH THE USE OF
+THE SOFTWARE IS ASSUMED BY YOU.  FURTHERMORE, COPYRIGHT HOLDER AND ITS
+LICENSORS DO NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING THE USE
+OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
+ACCURACY, RELIABILITY, CURRENTNESS, OR OTHERWISE.
+
+DISCLAIMER: UNDER NO CIRCUMSTANCES INCLUDING NEGLIGENCE, SHALL COPYRIGHT
+HOLDER AND ITS LICENSORS OR ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS
+("AUTHORIZED REPRESENTATIVES") BE LIABLE FOR ANY INCIDENTAL, INDIRECT,
+SPECIAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF BUSINESS
+PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, AND THE
+LIKE) ARISING OUT OF THE USE, MISUSE OR INABILITY TO USE THE SOFTWARE,
+BREACH OR DEFAULT, INCLUDING THOSE ARISING FROM INFRINGEMENT OR ALLEGED
+INFRINGEMENT OF ANY PATENT, TRADEMARK, COPYRIGHT OR OTHER INTELLECTUAL
+PROPERTY RIGHT EVEN IF COPYRIGHT HOLDER AND ITS AUTHORIZED
+REPRESENTATIVES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.  IN
+NO EVENT SHALL COPYRIGHT HOLDER OR ITS AUTHORIZED REPRESENTATIVES TOTAL
+LIABILITY FOR ALL DAMAGES, LOSSES, AND CAUSES OF ACTION (WHETHER IN
+CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE) EXCEED THE AMOUNT OF
+US$10.
+
+Notice:  The Software is subject to United States export laws and
+regulations.  You agree to comply with all domestic and international
+export laws and regulations that apply to the Software, including but
+not limited to the Export Administration Regulations administered by the
+U.S. Department of Commerce and International Traffic in Arm Regulations
+administered by the U.S. Department of State.  These laws include
+restrictions on destinations, end users and end use.
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin
new file mode 100644
index 00000000..6153fcb7
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin
new file mode 100644
index 00000000..6056d83c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin
new file mode 100644
index 00000000..5f965b28
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec2.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec2.bin
new file mode 100644
index 00000000..c467fc91
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec2.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_pfp.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_pfp.bin
new file mode 100644
index 00000000..0e2ab856
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_pfp.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_rlc.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_rlc.bin
new file mode 100644
index 00000000..a701ef51
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_rlc.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma.bin
new file mode 100644
index 00000000..5c4be064
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma1.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma1.bin
new file mode 100644
index 00000000..5c4be064
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma1.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_uvd.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_uvd.bin
new file mode 100644
index 00000000..042f6813
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_uvd.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_vce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_vce.bin
new file mode 100644
index 00000000..e132ff69
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_vce.bin
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-yocto-amd-drm-amdgpu-add-VI-pci-idsamdgpu.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-yocto-amd-drm-amdgpu-add-VI-pci-idsamdgpu.patch
new file mode 100644
index 00000000..5df22924
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0001-yocto-amd-drm-amdgpu-add-VI-pci-idsamdgpu.patch
@@ -0,0 +1,11197 @@
+From a85a7fb221800dfd7853a9dae2c55219a532fa21 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:06:12 -0400
+Subject: drm/amdgpu: add BIF 4.1 register headers
+
+These are register headers for the BIF (Bus InterFace) block on
+the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
+new file mode 100644
+index 0000000..a761ba0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
+@@ -0,0 +1,921 @@
++/*
++ * BIF_4_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_4_1_D_H
++#define BIF_4_1_D_H
++
++#define mmMM_INDEX                                                              0x0
++#define mmMM_INDEX_HI                                                           0x6
++#define mmMM_DATA                                                               0x1
++#define mmBUS_CNTL                                                              0x1508
++#define mmCONFIG_CNTL                                                           0x1509
++#define mmCONFIG_MEMSIZE                                                        0x150a
++#define mmCONFIG_F0_BASE                                                        0x150b
++#define mmCONFIG_APER_SIZE                                                      0x150c
++#define mmCONFIG_REG_APER_SIZE                                                  0x150d
++#define mmBIF_SCRATCH0                                                          0x150e
++#define mmBIF_SCRATCH1                                                          0x150f
++#define mmBX_RESET_EN                                                           0x1514
++#define mmMM_CFGREGS_CNTL                                                       0x1513
++#define mmHW_DEBUG                                                              0x1515
++#define mmMASTER_CREDIT_CNTL                                                    0x1516
++#define mmSLAVE_REQ_CREDIT_CNTL                                                 0x1517
++#define mmBX_RESET_CNTL                                                         0x1518
++#define mmINTERRUPT_CNTL                                                        0x151a
++#define mmINTERRUPT_CNTL2                                                       0x151b
++#define mmBIF_DEBUG_CNTL                                                        0x151c
++#define mmBIF_DEBUG_MUX                                                         0x151d
++#define mmBIF_DEBUG_OUT                                                         0x151e
++#define mmHDP_REG_COHERENCY_FLUSH_CNTL                                          0x1528
++#define mmHDP_MEM_COHERENCY_FLUSH_CNTL                                          0x1520
++#define mmCLKREQB_PAD_CNTL                                                      0x1521
++#define mmSMBUS_SLV_CNTL                                                        0x14fd
++#define mmSMBUS_SLV_CNTL1                                                       0x14fe
++#define mmSMBDAT_PAD_CNTL                                                       0x1522
++#define mmSMBCLK_PAD_CNTL                                                       0x1523
++#define mmBIF_XDMA_LO                                                           0x14c0
++#define mmBIF_XDMA_HI                                                           0x14c1
++#define mmBIF_FEATURES_CONTROL_MISC                                             0x14c2
++#define mmBIF_DOORBELL_CNTL                                                     0x14c3
++#define mmBIF_SLVARB_MODE                                                       0x14c4
++#define mmBIF_FB_EN                                                             0x1524
++#define mmBIF_BUSNUM_CNTL1                                                      0x1525
++#define mmBIF_BUSNUM_LIST0                                                      0x1526
++#define mmBIF_BUSNUM_LIST1                                                      0x1527
++#define mmBIF_BUSNUM_CNTL2                                                      0x152b
++#define mmBIF_BUSY_DELAY_CNTR                                                   0x1529
++#define mmBIF_PERFMON_CNTL                                                      0x152c
++#define mmBIF_PERFCOUNTER0_RESULT                                               0x152d
++#define mmBIF_PERFCOUNTER1_RESULT                                               0x152e
++#define mmSLAVE_HANG_PROTECTION_CNTL                                            0x1536
++#define mmGPU_HDP_FLUSH_REQ                                                     0x1537
++#define mmGPU_HDP_FLUSH_DONE                                                    0x1538
++#define mmSLAVE_HANG_ERROR                                                      0x153b
++#define mmCAPTURE_HOST_BUSNUM                                                   0x153c
++#define mmHOST_BUSNUM                                                           0x153d
++#define mmPEER_REG_RANGE0                                                       0x153e
++#define mmPEER_REG_RANGE1                                                       0x153f
++#define mmPEER0_FB_OFFSET_HI                                                    0x14f3
++#define mmPEER0_FB_OFFSET_LO                                                    0x14f2
++#define mmPEER1_FB_OFFSET_HI                                                    0x14f1
++#define mmPEER1_FB_OFFSET_LO                                                    0x14f0
++#define mmPEER2_FB_OFFSET_HI                                                    0x14ef
++#define mmPEER2_FB_OFFSET_LO                                                    0x14ee
++#define mmPEER3_FB_OFFSET_HI                                                    0x14ed
++#define mmPEER3_FB_OFFSET_LO                                                    0x14ec
++#define mmDBG_BYPASS_SRBM_ACCESS                                                0x14eb
++#define mmSMBUS_BACO_DUMMY                                                      0x14c6
++#define mmBIF_DEVFUNCNUM_LIST0                                                  0x14e8
++#define mmBIF_DEVFUNCNUM_LIST1                                                  0x14e7
++#define mmBACO_CNTL                                                             0x14e5
++#define mmBF_ANA_ISO_CNTL                                                       0x14c7
++#define mmMEM_TYPE_CNTL                                                         0x14e4
++#define mmBIF_BACO_DEBUG                                                        0x14df
++#define mmBIF_BACO_DEBUG_LATCH                                                  0x14dc
++#define mmBACO_CNTL_MISC                                                        0x14db
++#define mmBIF_SSA_PWR_STATUS                                                    0x14c8
++#define mmBIF_SSA_GFX0_LOWER                                                    0x14ca
++#define mmBIF_SSA_GFX0_UPPER                                                    0x14cb
++#define mmBIF_SSA_GFX1_LOWER                                                    0x14cc
++#define mmBIF_SSA_GFX1_UPPER                                                    0x14cd
++#define mmBIF_SSA_GFX2_LOWER                                                    0x14ce
++#define mmBIF_SSA_GFX2_UPPER                                                    0x14cf
++#define mmBIF_SSA_GFX3_LOWER                                                    0x14d0
++#define mmBIF_SSA_GFX3_UPPER                                                    0x14d1
++#define mmBIF_SSA_DISP_LOWER                                                    0x14d2
++#define mmBIF_SSA_DISP_UPPER                                                    0x14d3
++#define mmBIF_SSA_MC_LOWER                                                      0x14d4
++#define mmBIF_SSA_MC_UPPER                                                      0x14d5
++#define mmIMPCTL_RESET                                                          0x14f5
++#define mmGARLIC_FLUSH_CNTL                                                     0x1401
++#define mmGARLIC_FLUSH_ADDR_START_0                                             0x1402
++#define mmGARLIC_FLUSH_ADDR_START_1                                             0x1404
++#define mmGARLIC_FLUSH_ADDR_START_2                                             0x1406
++#define mmGARLIC_FLUSH_ADDR_START_3                                             0x1408
++#define mmGARLIC_FLUSH_ADDR_START_4                                             0x140a
++#define mmGARLIC_FLUSH_ADDR_START_5                                             0x140c
++#define mmGARLIC_FLUSH_ADDR_START_6                                             0x140e
++#define mmGARLIC_FLUSH_ADDR_START_7                                             0x1410
++#define mmGARLIC_FLUSH_ADDR_END_0                                               0x1403
++#define mmGARLIC_FLUSH_ADDR_END_1                                               0x1405
++#define mmGARLIC_FLUSH_ADDR_END_2                                               0x1407
++#define mmGARLIC_FLUSH_ADDR_END_3                                               0x1409
++#define mmGARLIC_FLUSH_ADDR_END_4                                               0x140b
++#define mmGARLIC_FLUSH_ADDR_END_5                                               0x140d
++#define mmGARLIC_FLUSH_ADDR_END_6                                               0x140f
++#define mmGARLIC_FLUSH_ADDR_END_7                                               0x1411
++#define mmGARLIC_FLUSH_REQ                                                      0x1412
++#define mmGPU_GARLIC_FLUSH_REQ                                                  0x1413
++#define mmGPU_GARLIC_FLUSH_DONE                                                 0x1414
++#define mmGARLIC_COHE_CP_RB0_WPTR                                               0x1415
++#define mmGARLIC_COHE_CP_RB1_WPTR                                               0x1416
++#define mmGARLIC_COHE_CP_RB2_WPTR                                               0x1417
++#define mmGARLIC_COHE_UVD_RBC_RB_WPTR                                           0x1418
++#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR                                         0x1419
++#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR                                         0x141a
++#define mmGARLIC_COHE_CP_DMA_ME_COMMAND                                         0x141b
++#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND                                        0x141c
++#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR                                          0x141d
++#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR                                          0x141e
++#define mmGARLIC_COHE_VCE_OUT_RB_WPTR                                           0x141f
++#define mmGARLIC_COHE_VCE_RB_WPTR2                                              0x1420
++#define mmGARLIC_COHE_VCE_RB_WPTR                                               0x1421
++#define mmBIOS_SCRATCH_0                                                        0x5c9
++#define mmBIOS_SCRATCH_1                                                        0x5ca
++#define mmBIOS_SCRATCH_2                                                        0x5cb
++#define mmBIOS_SCRATCH_3                                                        0x5cc
++#define mmBIOS_SCRATCH_4                                                        0x5cd
++#define mmBIOS_SCRATCH_5                                                        0x5ce
++#define mmBIOS_SCRATCH_6                                                        0x5cf
++#define mmBIOS_SCRATCH_7                                                        0x5d0
++#define mmBIOS_SCRATCH_8                                                        0x5d1
++#define mmBIOS_SCRATCH_9                                                        0x5d2
++#define mmBIOS_SCRATCH_10                                                       0x5d3
++#define mmBIOS_SCRATCH_11                                                       0x5d4
++#define mmBIOS_SCRATCH_12                                                       0x5d5
++#define mmBIOS_SCRATCH_13                                                       0x5d6
++#define mmBIOS_SCRATCH_14                                                       0x5d7
++#define mmBIOS_SCRATCH_15                                                       0x5d8
++#define mmVENDOR_ID                                                             0x0
++#define mmDEVICE_ID                                                             0x0
++#define mmCOMMAND                                                               0x1
++#define mmSTATUS                                                                0x1
++#define mmREVISION_ID                                                           0x2
++#define mmPROG_INTERFACE                                                        0x2
++#define mmSUB_CLASS                                                             0x2
++#define mmBASE_CLASS                                                            0x2
++#define mmCACHE_LINE                                                            0x3
++#define mmLATENCY                                                               0x3
++#define mmHEADER                                                                0x3
++#define mmBIST                                                                  0x3
++#define mmBASE_ADDR_1                                                           0x4
++#define mmBASE_ADDR_2                                                           0x5
++#define mmBASE_ADDR_3                                                           0x6
++#define mmBASE_ADDR_4                                                           0x7
++#define mmBASE_ADDR_5                                                           0x8
++#define mmBASE_ADDR_6                                                           0x9
++#define mmROM_BASE_ADDR                                                         0xc
++#define mmCAP_PTR                                                               0xd
++#define mmINTERRUPT_LINE                                                        0xf
++#define mmINTERRUPT_PIN                                                         0xf
++#define mmADAPTER_ID                                                            0xb
++#define mmMIN_GRANT                                                             0xf
++#define mmMAX_LATENCY                                                           0xf
++#define mmVENDOR_CAP_LIST                                                       0x12
++#define mmADAPTER_ID_W                                                          0x13
++#define mmPMI_CAP_LIST                                                          0x14
++#define mmPMI_CAP                                                               0x14
++#define mmPMI_STATUS_CNTL                                                       0x15
++#define mmPCIE_CAP_LIST                                                         0x16
++#define mmPCIE_CAP                                                              0x16
++#define mmDEVICE_CAP                                                            0x17
++#define mmDEVICE_CNTL                                                           0x18
++#define mmDEVICE_STATUS                                                         0x18
++#define mmLINK_CAP                                                              0x19
++#define mmLINK_CNTL                                                             0x1a
++#define mmLINK_STATUS                                                           0x1a
++#define mmDEVICE_CAP2                                                           0x1f
++#define mmDEVICE_CNTL2                                                          0x20
++#define mmDEVICE_STATUS2                                                        0x20
++#define mmLINK_CAP2                                                             0x21
++#define mmLINK_CNTL2                                                            0x22
++#define mmLINK_STATUS2                                                          0x22
++#define mmMSI_CAP_LIST                                                          0x28
++#define mmMSI_MSG_CNTL                                                          0x28
++#define mmMSI_MSG_ADDR_LO                                                       0x29
++#define mmMSI_MSG_ADDR_HI                                                       0x2a
++#define mmMSI_MSG_DATA_64                                                       0x2b
++#define mmMSI_MSG_DATA                                                          0x2a
++#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                     0x40
++#define mmPCIE_VENDOR_SPECIFIC_HDR                                              0x41
++#define mmPCIE_VENDOR_SPECIFIC1                                                 0x42
++#define mmPCIE_VENDOR_SPECIFIC2                                                 0x43
++#define mmPCIE_VC_ENH_CAP_LIST                                                  0x44
++#define mmPCIE_PORT_VC_CAP_REG1                                                 0x45
++#define mmPCIE_PORT_VC_CAP_REG2                                                 0x46
++#define mmPCIE_PORT_VC_CNTL                                                     0x47
++#define mmPCIE_PORT_VC_STATUS                                                   0x47
++#define mmPCIE_VC0_RESOURCE_CAP                                                 0x48
++#define mmPCIE_VC0_RESOURCE_CNTL                                                0x49
++#define mmPCIE_VC0_RESOURCE_STATUS                                              0x4a
++#define mmPCIE_VC1_RESOURCE_CAP                                                 0x4b
++#define mmPCIE_VC1_RESOURCE_CNTL                                                0x4c
++#define mmPCIE_VC1_RESOURCE_STATUS                                              0x4d
++#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                      0x50
++#define mmPCIE_DEV_SERIAL_NUM_DW1                                               0x51
++#define mmPCIE_DEV_SERIAL_NUM_DW2                                               0x52
++#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST                                         0x54
++#define mmPCIE_UNCORR_ERR_STATUS                                                0x55
++#define mmPCIE_UNCORR_ERR_MASK                                                  0x56
++#define mmPCIE_UNCORR_ERR_SEVERITY                                              0x57
++#define mmPCIE_CORR_ERR_STATUS                                                  0x58
++#define mmPCIE_CORR_ERR_MASK                                                    0x59
++#define mmPCIE_ADV_ERR_CAP_CNTL                                                 0x5a
++#define mmPCIE_HDR_LOG0                                                         0x5b
++#define mmPCIE_HDR_LOG1                                                         0x5c
++#define mmPCIE_HDR_LOG2                                                         0x5d
++#define mmPCIE_HDR_LOG3                                                         0x5e
++#define mmPCIE_TLP_PREFIX_LOG0                                                  0x62
++#define mmPCIE_TLP_PREFIX_LOG1                                                  0x63
++#define mmPCIE_TLP_PREFIX_LOG2                                                  0x64
++#define mmPCIE_TLP_PREFIX_LOG3                                                  0x65
++#define mmPCIE_BAR_ENH_CAP_LIST                                                 0x80
++#define mmPCIE_BAR1_CAP                                                         0x81
++#define mmPCIE_BAR1_CNTL                                                        0x82
++#define mmPCIE_BAR2_CAP                                                         0x83
++#define mmPCIE_BAR2_CNTL                                                        0x84
++#define mmPCIE_BAR3_CAP                                                         0x85
++#define mmPCIE_BAR3_CNTL                                                        0x86
++#define mmPCIE_BAR4_CAP                                                         0x87
++#define mmPCIE_BAR4_CNTL                                                        0x88
++#define mmPCIE_BAR5_CAP                                                         0x89
++#define mmPCIE_BAR5_CNTL                                                        0x8a
++#define mmPCIE_BAR6_CAP                                                         0x8b
++#define mmPCIE_BAR6_CNTL                                                        0x8c
++#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST                                          0x90
++#define mmPCIE_PWR_BUDGET_DATA_SELECT                                           0x91
++#define mmPCIE_PWR_BUDGET_DATA                                                  0x92
++#define mmPCIE_PWR_BUDGET_CAP                                                   0x93
++#define mmPCIE_DPA_ENH_CAP_LIST                                                 0x94
++#define mmPCIE_DPA_CAP                                                          0x95
++#define mmPCIE_DPA_LATENCY_INDICATOR                                            0x96
++#define mmPCIE_DPA_STATUS                                                       0x97
++#define mmPCIE_DPA_CNTL                                                         0x97
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                         0x99
++#define mmPCIE_SECONDARY_ENH_CAP_LIST                                           0x9c
++#define mmPCIE_LINK_CNTL3                                                       0x9d
++#define mmPCIE_LANE_ERROR_STATUS                                                0x9e
++#define mmPCIE_LANE_0_EQUALIZATION_CNTL                                         0x9f
++#define mmPCIE_LANE_1_EQUALIZATION_CNTL                                         0x9f
++#define mmPCIE_LANE_2_EQUALIZATION_CNTL                                         0xa0
++#define mmPCIE_LANE_3_EQUALIZATION_CNTL                                         0xa0
++#define mmPCIE_LANE_4_EQUALIZATION_CNTL                                         0xa1
++#define mmPCIE_LANE_5_EQUALIZATION_CNTL                                         0xa1
++#define mmPCIE_LANE_6_EQUALIZATION_CNTL                                         0xa2
++#define mmPCIE_LANE_7_EQUALIZATION_CNTL                                         0xa2
++#define mmPCIE_LANE_8_EQUALIZATION_CNTL                                         0xa3
++#define mmPCIE_LANE_9_EQUALIZATION_CNTL                                         0xa3
++#define mmPCIE_LANE_10_EQUALIZATION_CNTL                                        0xa4
++#define mmPCIE_LANE_11_EQUALIZATION_CNTL                                        0xa4
++#define mmPCIE_LANE_12_EQUALIZATION_CNTL                                        0xa5
++#define mmPCIE_LANE_13_EQUALIZATION_CNTL                                        0xa5
++#define mmPCIE_LANE_14_EQUALIZATION_CNTL                                        0xa6
++#define mmPCIE_LANE_15_EQUALIZATION_CNTL                                        0xa6
++#define mmPCIE_ACS_ENH_CAP_LIST                                                 0xa8
++#define mmPCIE_ACS_CAP                                                          0xa9
++#define mmPCIE_ACS_CNTL                                                         0xa9
++#define mmPCIE_ATS_ENH_CAP_LIST                                                 0xac
++#define mmPCIE_ATS_CAP                                                          0xad
++#define mmPCIE_ATS_CNTL                                                         0xad
++#define mmPCIE_PAGE_REQ_ENH_CAP_LIST                                            0xb0
++#define mmPCIE_PAGE_REQ_CNTL                                                    0xb1
++#define mmPCIE_PAGE_REQ_STATUS                                                  0xb1
++#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                       0xb2
++#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC                                          0xb3
++#define mmPCIE_PASID_ENH_CAP_LIST                                               0xb4
++#define mmPCIE_PASID_CAP                                                        0xb5
++#define mmPCIE_PASID_CNTL                                                       0xb5
++#define mmPCIE_TPH_REQR_ENH_CAP_LIST                                            0xb8
++#define mmPCIE_TPH_REQR_CAP                                                     0xb9
++#define mmPCIE_TPH_REQR_CNTL                                                    0xba
++#define mmPCIE_MC_ENH_CAP_LIST                                                  0xbc
++#define mmPCIE_MC_CAP                                                           0xbd
++#define mmPCIE_MC_CNTL                                                          0xbd
++#define mmPCIE_MC_ADDR0                                                         0xbe
++#define mmPCIE_MC_ADDR1                                                         0xbf
++#define mmPCIE_MC_RCV0                                                          0xc0
++#define mmPCIE_MC_RCV1                                                          0xc1
++#define mmPCIE_MC_BLOCK_ALL0                                                    0xc2
++#define mmPCIE_MC_BLOCK_ALL1                                                    0xc3
++#define mmPCIE_MC_BLOCK_UNTRANSLATED_0                                          0xc4
++#define mmPCIE_MC_BLOCK_UNTRANSLATED_1                                          0xc5
++#define mmPCIE_LTR_ENH_CAP_LIST                                                 0xc8
++#define mmPCIE_LTR_CAP                                                          0xc9
++#define mmPCIE_INDEX                                                            0xe
++#define mmPCIE_DATA                                                             0xf
++#define mmPCIE_INDEX_2                                                          0xc
++#define mmPCIE_DATA_2                                                           0xd
++#define ixPCIE_RESERVED                                                         0x1400000
++#define ixPCIE_SCRATCH                                                          0x1400001
++#define ixPCIE_HW_DEBUG                                                         0x1400002
++#define ixPCIE_RX_NUM_NAK                                                       0x140000e
++#define ixPCIE_RX_NUM_NAK_GENERATED                                             0x140000f
++#define ixPCIE_CNTL                                                             0x1400010
++#define ixPCIE_CONFIG_CNTL                                                      0x1400011
++#define ixPCIE_DEBUG_CNTL                                                       0x1400012
++#define ixPCIE_INT_CNTL                                                         0x140001a
++#define ixPCIE_INT_STATUS                                                       0x140001b
++#define ixPCIE_CNTL2                                                            0x140001c
++#define ixPCIE_RX_CNTL2                                                         0x140001d
++#define ixPCIE_TX_F0_ATTR_CNTL                                                  0x140001e
++#define ixPCIE_TX_F1_F2_ATTR_CNTL                                               0x140001f
++#define ixPCIE_CI_CNTL                                                          0x1400020
++#define ixPCIE_BUS_CNTL                                                         0x1400021
++#define ixPCIE_LC_STATE6                                                        0x1400022
++#define ixPCIE_LC_STATE7                                                        0x1400023
++#define ixPCIE_LC_STATE8                                                        0x1400024
++#define ixPCIE_LC_STATE9                                                        0x1400025
++#define ixPCIE_LC_STATE10                                                       0x1400026
++#define ixPCIE_LC_STATE11                                                       0x1400027
++#define ixPCIE_LC_STATUS1                                                       0x1400028
++#define ixPCIE_LC_STATUS2                                                       0x1400029
++#define ixPCIE_WPR_CNTL                                                         0x1400030
++#define ixPCIE_RX_LAST_TLP0                                                     0x1400031
++#define ixPCIE_RX_LAST_TLP1                                                     0x1400032
++#define ixPCIE_RX_LAST_TLP2                                                     0x1400033
++#define ixPCIE_RX_LAST_TLP3                                                     0x1400034
++#define ixPCIE_TX_LAST_TLP0                                                     0x1400035
++#define ixPCIE_TX_LAST_TLP1                                                     0x1400036
++#define ixPCIE_TX_LAST_TLP2                                                     0x1400037
++#define ixPCIE_TX_LAST_TLP3                                                     0x1400038
++#define ixPCIE_I2C_REG_ADDR_EXPAND                                              0x140003a
++#define ixPCIE_I2C_REG_DATA                                                     0x140003b
++#define ixPCIE_CFG_CNTL                                                         0x140003c
++#define ixPCIE_P_CNTL                                                           0x1400040
++#define ixPCIE_P_BUF_STATUS                                                     0x1400041
++#define ixPCIE_P_DECODER_STATUS                                                 0x1400042
++#define ixPCIE_P_MISC_STATUS                                                    0x1400043
++#define ixPCIE_P_RCV_L0S_FTS_DET                                                0x1400050
++#define ixPCIE_OBFF_CNTL                                                        0x1400061
++#define ixPCIE_TX_LTR_CNTL                                                      0x1400060
++#define ixPCIE_PERF_COUNT_CNTL                                                  0x1400080
++#define ixPCIE_PERF_CNTL_TXCLK                                                  0x1400081
++#define ixPCIE_PERF_COUNT0_TXCLK                                                0x1400082
++#define ixPCIE_PERF_COUNT1_TXCLK                                                0x1400083
++#define ixPCIE_PERF_CNTL_MST_R_CLK                                              0x1400084
++#define ixPCIE_PERF_COUNT0_MST_R_CLK                                            0x1400085
++#define ixPCIE_PERF_COUNT1_MST_R_CLK                                            0x1400086
++#define ixPCIE_PERF_CNTL_MST_C_CLK                                              0x1400087
++#define ixPCIE_PERF_COUNT0_MST_C_CLK                                            0x1400088
++#define ixPCIE_PERF_COUNT1_MST_C_CLK                                            0x1400089
++#define ixPCIE_PERF_CNTL_SLV_R_CLK                                              0x140008a
++#define ixPCIE_PERF_COUNT0_SLV_R_CLK                                            0x140008b
++#define ixPCIE_PERF_COUNT1_SLV_R_CLK                                            0x140008c
++#define ixPCIE_PERF_CNTL_SLV_S_C_CLK                                            0x140008d
++#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK                                          0x140008e
++#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK                                          0x140008f
++#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK                                           0x1400090
++#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK                                         0x1400091
++#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK                                         0x1400092
++#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL                                        0x1400093
++#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL                                        0x1400094
++#define ixPCIE_PERF_CNTL_TXCLK2                                                 0x1400095
++#define ixPCIE_PERF_COUNT0_TXCLK2                                               0x1400096
++#define ixPCIE_PERF_COUNT1_TXCLK2                                               0x1400097
++#define ixPCIE_STRAP_F0                                                         0x14000b0
++#define ixPCIE_STRAP_F1                                                         0x14000b1
++#define ixPCIE_STRAP_F2                                                         0x14000b2
++#define ixPCIE_STRAP_F3                                                         0x14000b3
++#define ixPCIE_STRAP_F4                                                         0x14000b4
++#define ixPCIE_STRAP_F5                                                         0x14000b5
++#define ixPCIE_STRAP_F6                                                         0x14000b6
++#define ixPCIE_STRAP_F7                                                         0x14000b7
++#define ixPCIE_STRAP_MISC                                                       0x14000c0
++#define ixPCIE_STRAP_MISC2                                                      0x14000c1
++#define ixPCIE_STRAP_PI                                                         0x14000c2
++#define ixPCIE_STRAP_I2C_BD                                                     0x14000c4
++#define ixPCIE_PRBS_CLR                                                         0x14000c8
++#define ixPCIE_PRBS_STATUS1                                                     0x14000c9
++#define ixPCIE_PRBS_STATUS2                                                     0x14000ca
++#define ixPCIE_PRBS_FREERUN                                                     0x14000cb
++#define ixPCIE_PRBS_MISC                                                        0x14000cc
++#define ixPCIE_PRBS_USER_PATTERN                                                0x14000cd
++#define ixPCIE_PRBS_LO_BITCNT                                                   0x14000ce
++#define ixPCIE_PRBS_HI_BITCNT                                                   0x14000cf
++#define ixPCIE_PRBS_ERRCNT_0                                                    0x14000d0
++#define ixPCIE_PRBS_ERRCNT_1                                                    0x14000d1
++#define ixPCIE_PRBS_ERRCNT_2                                                    0x14000d2
++#define ixPCIE_PRBS_ERRCNT_3                                                    0x14000d3
++#define ixPCIE_PRBS_ERRCNT_4                                                    0x14000d4
++#define ixPCIE_PRBS_ERRCNT_5                                                    0x14000d5
++#define ixPCIE_PRBS_ERRCNT_6                                                    0x14000d6
++#define ixPCIE_PRBS_ERRCNT_7                                                    0x14000d7
++#define ixPCIE_PRBS_ERRCNT_8                                                    0x14000d8
++#define ixPCIE_PRBS_ERRCNT_9                                                    0x14000d9
++#define ixPCIE_PRBS_ERRCNT_10                                                   0x14000da
++#define ixPCIE_PRBS_ERRCNT_11                                                   0x14000db
++#define ixPCIE_PRBS_ERRCNT_12                                                   0x14000dc
++#define ixPCIE_PRBS_ERRCNT_13                                                   0x14000dd
++#define ixPCIE_PRBS_ERRCNT_14                                                   0x14000de
++#define ixPCIE_PRBS_ERRCNT_15                                                   0x14000df
++#define ixPCIE_F0_DPA_CAP                                                       0x14000e0
++#define ixPCIE_F0_DPA_LATENCY_INDICATOR                                         0x14000e4
++#define ixPCIE_F0_DPA_CNTL                                                      0x14000e5
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                      0x14000e7
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                      0x14000e8
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                      0x14000e9
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                      0x14000ea
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                      0x14000eb
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                      0x14000ec
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                      0x14000ed
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                      0x14000ee
++#define ixPCIEP_RESERVED                                                        0x10010000
++#define ixPCIEP_SCRATCH                                                         0x10010001
++#define ixPCIEP_HW_DEBUG                                                        0x10010002
++#define ixPCIEP_PORT_CNTL                                                       0x10010010
++#define ixPCIE_TX_CNTL                                                          0x10010020
++#define ixPCIE_TX_REQUESTER_ID                                                  0x10010021
++#define ixPCIE_TX_VENDOR_SPECIFIC                                               0x10010022
++#define ixPCIE_TX_REQUEST_NUM_CNTL                                              0x10010023
++#define ixPCIE_TX_SEQ                                                           0x10010024
++#define ixPCIE_TX_REPLAY                                                        0x10010025
++#define ixPCIE_TX_ACK_LATENCY_LIMIT                                             0x10010026
++#define ixPCIE_TX_CREDITS_ADVT_P                                                0x10010030
++#define ixPCIE_TX_CREDITS_ADVT_NP                                               0x10010031
++#define ixPCIE_TX_CREDITS_ADVT_CPL                                              0x10010032
++#define ixPCIE_TX_CREDITS_INIT_P                                                0x10010033
++#define ixPCIE_TX_CREDITS_INIT_NP                                               0x10010034
++#define ixPCIE_TX_CREDITS_INIT_CPL                                              0x10010035
++#define ixPCIE_TX_CREDITS_STATUS                                                0x10010036
++#define ixPCIE_TX_CREDITS_FCU_THRESHOLD                                         0x10010037
++#define ixPCIE_P_PORT_LANE_STATUS                                               0x10010050
++#define ixPCIE_FC_P                                                             0x10010060
++#define ixPCIE_FC_NP                                                            0x10010061
++#define ixPCIE_FC_CPL                                                           0x10010062
++#define ixPCIE_ERR_CNTL                                                         0x1001006a
++#define ixPCIE_RX_CNTL                                                          0x10010070
++#define ixPCIE_RX_EXPECTED_SEQNUM                                               0x10010071
++#define ixPCIE_RX_VENDOR_SPECIFIC                                               0x10010072
++#define ixPCIE_RX_CNTL3                                                         0x10010074
++#define ixPCIE_RX_CREDITS_ALLOCATED_P                                           0x10010080
++#define ixPCIE_RX_CREDITS_ALLOCATED_NP                                          0x10010081
++#define ixPCIE_RX_CREDITS_ALLOCATED_CPL                                         0x10010082
++#define ixPCIE_LC_CNTL                                                          0x100100a0
++#define ixPCIE_LC_CNTL2                                                         0x100100b1
++#define ixPCIE_LC_CNTL3                                                         0x100100b5
++#define ixPCIE_LC_CNTL4                                                         0x100100b6
++#define ixPCIE_LC_CNTL5                                                         0x100100b7
++#define ixPCIE_LC_BW_CHANGE_CNTL                                                0x100100b2
++#define ixPCIE_LC_TRAINING_CNTL                                                 0x100100a1
++#define ixPCIE_LC_LINK_WIDTH_CNTL                                               0x100100a2
++#define ixPCIE_LC_N_FTS_CNTL                                                    0x100100a3
++#define ixPCIE_LC_SPEED_CNTL                                                    0x100100a4
++#define ixPCIE_LC_CDR_CNTL                                                      0x100100b3
++#define ixPCIE_LC_LANE_CNTL                                                     0x100100b4
++#define ixPCIE_LC_FORCE_COEFF                                                   0x100100b8
++#define ixPCIE_LC_BEST_EQ_SETTINGS                                              0x100100b9
++#define ixPCIE_LC_FORCE_EQ_REQ_COEFF                                            0x100100ba
++#define ixPCIE_LC_STATE0                                                        0x100100a5
++#define ixPCIE_LC_STATE1                                                        0x100100a6
++#define ixPCIE_LC_STATE2                                                        0x100100a7
++#define ixPCIE_LC_STATE3                                                        0x100100a8
++#define ixPCIE_LC_STATE4                                                        0x100100a9
++#define ixPCIE_LC_STATE5                                                        0x100100aa
++#define ixPCIEP_STRAP_LC                                                        0x100100c0
++#define ixPCIEP_STRAP_MISC                                                      0x100100c1
++#define ixPCIEP_BCH_ECC_CNTL                                                    0x100100d0
++#define ixPB0_GLB_CTRL_REG0                                                     0x1200004
++#define ixPB0_GLB_CTRL_REG1                                                     0x1200008
++#define ixPB0_GLB_CTRL_REG2                                                     0x120000c
++#define ixPB0_GLB_CTRL_REG3                                                     0x1200010
++#define ixPB0_GLB_CTRL_REG4                                                     0x1200014
++#define ixPB0_GLB_CTRL_REG5                                                     0x1200018
++#define ixPB0_GLB_SCI_STAT_OVRD_REG0                                            0x120001c
++#define ixPB0_GLB_SCI_STAT_OVRD_REG1                                            0x1200020
++#define ixPB0_GLB_SCI_STAT_OVRD_REG2                                            0x1200024
++#define ixPB0_GLB_SCI_STAT_OVRD_REG3                                            0x1200028
++#define ixPB0_GLB_SCI_STAT_OVRD_REG4                                            0x120002c
++#define ixPB0_GLB_OVRD_REG0                                                     0x1200030
++#define ixPB0_GLB_OVRD_REG1                                                     0x1200034
++#define ixPB0_GLB_OVRD_REG2                                                     0x1200038
++#define ixPB0_HW_DEBUG                                                          0x1202004
++#define ixPB0_STRAP_GLB_REG0                                                    0x1202020
++#define ixPB0_STRAP_TX_REG0                                                     0x1202024
++#define ixPB0_STRAP_RX_REG0                                                     0x1202028
++#define ixPB0_STRAP_RX_REG1                                                     0x120202c
++#define ixPB0_STRAP_PLL_REG0                                                    0x1202030
++#define ixPB0_STRAP_PIN_REG0                                                    0x1202034
++#define ixPB0_DFT_JIT_INJ_REG0                                                  0x1203000
++#define ixPB0_DFT_JIT_INJ_REG1                                                  0x1203004
++#define ixPB0_DFT_JIT_INJ_REG2                                                  0x1203008
++#define ixPB0_DFT_DEBUG_CTRL_REG0                                               0x120300c
++#define ixPB0_DFT_JIT_INJ_STAT_REG0                                             0x1203010
++#define ixPB0_PLL_RO_GLB_CTRL_REG0                                              0x1204000
++#define ixPB0_PLL_RO_GLB_OVRD_REG0                                              0x1204010
++#define ixPB0_PLL_RO0_CTRL_REG0                                                 0x1204440
++#define ixPB0_PLL_RO0_OVRD_REG0                                                 0x1204450
++#define ixPB0_PLL_RO0_OVRD_REG1                                                 0x1204454
++#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0                                        0x1204460
++#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0                                        0x1204464
++#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0                                        0x1204468
++#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0                                        0x120446c
++#define ixPB0_PLL_LC0_CTRL_REG0                                                 0x1204480
++#define ixPB0_PLL_LC0_OVRD_REG0                                                 0x1204490
++#define ixPB0_PLL_LC0_OVRD_REG1                                                 0x1204494
++#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0                                        0x1204500
++#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0                                        0x1204504
++#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0                                        0x1204508
++#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0                                        0x120450c
++#define ixPB0_RX_GLB_CTRL_REG0                                                  0x1206000
++#define ixPB0_RX_GLB_CTRL_REG1                                                  0x1206004
++#define ixPB0_RX_GLB_CTRL_REG2                                                  0x1206008
++#define ixPB0_RX_GLB_CTRL_REG3                                                  0x120600c
++#define ixPB0_RX_GLB_CTRL_REG4                                                  0x1206010
++#define ixPB0_RX_GLB_CTRL_REG5                                                  0x1206014
++#define ixPB0_RX_GLB_CTRL_REG6                                                  0x1206018
++#define ixPB0_RX_GLB_CTRL_REG7                                                  0x120601c
++#define ixPB0_RX_GLB_CTRL_REG8                                                  0x1206020
++#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0                                         0x1206028
++#define ixPB0_RX_GLB_OVRD_REG0                                                  0x1206030
++#define ixPB0_RX_GLB_OVRD_REG1                                                  0x1206034
++#define ixPB0_RX_LANE0_CTRL_REG0                                                0x1206440
++#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0                                       0x1206448
++#define ixPB0_RX_LANE1_CTRL_REG0                                                0x1206480
++#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0                                       0x1206488
++#define ixPB0_RX_LANE2_CTRL_REG0                                                0x1206500
++#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0                                       0x1206508
++#define ixPB0_RX_LANE3_CTRL_REG0                                                0x1206600
++#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0                                       0x1206608
++#define ixPB0_RX_LANE4_CTRL_REG0                                                0x1206800
++#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0                                       0x1206848
++#define ixPB0_RX_LANE5_CTRL_REG0                                                0x1206880
++#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0                                       0x1206888
++#define ixPB0_RX_LANE6_CTRL_REG0                                                0x1206900
++#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0                                       0x1206908
++#define ixPB0_RX_LANE7_CTRL_REG0                                                0x1206a00
++#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0                                       0x1206a08
++#define ixPB0_RX_LANE8_CTRL_REG0                                                0x1207440
++#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0                                       0x1207448
++#define ixPB0_RX_LANE9_CTRL_REG0                                                0x1207480
++#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0                                       0x1207488
++#define ixPB0_RX_LANE10_CTRL_REG0                                               0x1207500
++#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0                                      0x1207508
++#define ixPB0_RX_LANE11_CTRL_REG0                                               0x1207600
++#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0                                      0x1207608
++#define ixPB0_RX_LANE12_CTRL_REG0                                               0x1207840
++#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0                                      0x1207848
++#define ixPB0_RX_LANE13_CTRL_REG0                                               0x1207880
++#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0                                      0x1207888
++#define ixPB0_RX_LANE14_CTRL_REG0                                               0x1207900
++#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0                                      0x1207908
++#define ixPB0_RX_LANE15_CTRL_REG0                                               0x1207a00
++#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0                                      0x1207a08
++#define ixPB0_TX_GLB_CTRL_REG0                                                  0x1208000
++#define ixPB0_TX_GLB_LANE_SKEW_CTRL                                             0x1208004
++#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0                                         0x1208010
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0                                    0x1208014
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1                                    0x1208018
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2                                    0x120801c
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3                                    0x1208020
++#define ixPB0_TX_GLB_OVRD_REG0                                                  0x1208030
++#define ixPB0_TX_GLB_OVRD_REG1                                                  0x1208034
++#define ixPB0_TX_GLB_OVRD_REG2                                                  0x1208038
++#define ixPB0_TX_GLB_OVRD_REG3                                                  0x120803c
++#define ixPB0_TX_GLB_OVRD_REG4                                                  0x1208040
++#define ixPB0_TX_LANE0_CTRL_REG0                                                0x1208440
++#define ixPB0_TX_LANE0_OVRD_REG0                                                0x1208444
++#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0                                       0x1208448
++#define ixPB0_TX_LANE1_CTRL_REG0                                                0x1208480
++#define ixPB0_TX_LANE1_OVRD_REG0                                                0x1208484
++#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0                                       0x1208488
++#define ixPB0_TX_LANE2_CTRL_REG0                                                0x1208500
++#define ixPB0_TX_LANE2_OVRD_REG0                                                0x1208504
++#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0                                       0x1208508
++#define ixPB0_TX_LANE3_CTRL_REG0                                                0x1208600
++#define ixPB0_TX_LANE3_OVRD_REG0                                                0x1208604
++#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0                                       0x1208608
++#define ixPB0_TX_LANE4_CTRL_REG0                                                0x1208840
++#define ixPB0_TX_LANE4_OVRD_REG0                                                0x1208844
++#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0                                       0x1208848
++#define ixPB0_TX_LANE5_CTRL_REG0                                                0x1208880
++#define ixPB0_TX_LANE5_OVRD_REG0                                                0x1208884
++#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0                                       0x1208888
++#define ixPB0_TX_LANE6_CTRL_REG0                                                0x1208900
++#define ixPB0_TX_LANE6_OVRD_REG0                                                0x1208904
++#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0                                       0x1208908
++#define ixPB0_TX_LANE7_CTRL_REG0                                                0x1208a00
++#define ixPB0_TX_LANE7_OVRD_REG0                                                0x1208a04
++#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0                                       0x1208a08
++#define ixPB0_TX_LANE8_CTRL_REG0                                                0x1209440
++#define ixPB0_TX_LANE8_OVRD_REG0                                                0x1209444
++#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0                                       0x1209448
++#define ixPB0_TX_LANE9_CTRL_REG0                                                0x1209480
++#define ixPB0_TX_LANE9_OVRD_REG0                                                0x1209484
++#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0                                       0x1209488
++#define ixPB0_TX_LANE10_CTRL_REG0                                               0x1209500
++#define ixPB0_TX_LANE10_OVRD_REG0                                               0x1209504
++#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0                                      0x1209508
++#define ixPB0_TX_LANE11_CTRL_REG0                                               0x1209600
++#define ixPB0_TX_LANE11_OVRD_REG0                                               0x1209604
++#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0                                      0x1209608
++#define ixPB0_TX_LANE12_CTRL_REG0                                               0x1209840
++#define ixPB0_TX_LANE12_OVRD_REG0                                               0x1209844
++#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0                                      0x1209848
++#define ixPB0_TX_LANE13_CTRL_REG0                                               0x1209880
++#define ixPB0_TX_LANE13_OVRD_REG0                                               0x1209884
++#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0                                      0x1209888
++#define ixPB0_TX_LANE14_CTRL_REG0                                               0x1209900
++#define ixPB0_TX_LANE14_OVRD_REG0                                               0x1209904
++#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0                                      0x1209908
++#define ixPB0_TX_LANE15_CTRL_REG0                                               0x1209a00
++#define ixPB0_TX_LANE15_OVRD_REG0                                               0x1209a04
++#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0                                      0x1209a08
++#define ixPB1_GLB_CTRL_REG0                                                     0x2200004
++#define ixPB1_GLB_CTRL_REG1                                                     0x2200008
++#define ixPB1_GLB_CTRL_REG2                                                     0x220000c
++#define ixPB1_GLB_CTRL_REG3                                                     0x2200010
++#define ixPB1_GLB_CTRL_REG4                                                     0x2200014
++#define ixPB1_GLB_CTRL_REG5                                                     0x2200018
++#define ixPB1_GLB_SCI_STAT_OVRD_REG0                                            0x220001c
++#define ixPB1_GLB_SCI_STAT_OVRD_REG1                                            0x2200020
++#define ixPB1_GLB_SCI_STAT_OVRD_REG2                                            0x2200024
++#define ixPB1_GLB_SCI_STAT_OVRD_REG3                                            0x2200028
++#define ixPB1_GLB_SCI_STAT_OVRD_REG4                                            0x220002c
++#define ixPB1_GLB_OVRD_REG0                                                     0x2200030
++#define ixPB1_GLB_OVRD_REG1                                                     0x2200034
++#define ixPB1_GLB_OVRD_REG2                                                     0x2200038
++#define ixPB1_HW_DEBUG                                                          0x2202004
++#define ixPB1_STRAP_GLB_REG0                                                    0x2202020
++#define ixPB1_STRAP_TX_REG0                                                     0x2202024
++#define ixPB1_STRAP_RX_REG0                                                     0x2202028
++#define ixPB1_STRAP_RX_REG1                                                     0x220202c
++#define ixPB1_STRAP_PLL_REG0                                                    0x2202030
++#define ixPB1_STRAP_PIN_REG0                                                    0x2202034
++#define ixPB1_DFT_JIT_INJ_REG0                                                  0x2203000
++#define ixPB1_DFT_JIT_INJ_REG1                                                  0x2203004
++#define ixPB1_DFT_JIT_INJ_REG2                                                  0x2203008
++#define ixPB1_DFT_DEBUG_CTRL_REG0                                               0x220300c
++#define ixPB1_DFT_JIT_INJ_STAT_REG0                                             0x2203010
++#define ixPB1_PLL_RO_GLB_CTRL_REG0                                              0x2204000
++#define ixPB1_PLL_RO_GLB_OVRD_REG0                                              0x2204010
++#define ixPB1_PLL_RO0_CTRL_REG0                                                 0x2204440
++#define ixPB1_PLL_RO0_OVRD_REG0                                                 0x2204450
++#define ixPB1_PLL_RO0_OVRD_REG1                                                 0x2204454
++#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0                                        0x2204460
++#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0                                        0x2204464
++#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0                                        0x2204468
++#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0                                        0x220446c
++#define ixPB1_PLL_LC0_CTRL_REG0                                                 0x2204480
++#define ixPB1_PLL_LC0_OVRD_REG0                                                 0x2204490
++#define ixPB1_PLL_LC0_OVRD_REG1                                                 0x2204494
++#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0                                        0x2204500
++#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0                                        0x2204504
++#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0                                        0x2204508
++#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0                                        0x220450c
++#define ixPB1_RX_GLB_CTRL_REG0                                                  0x2206000
++#define ixPB1_RX_GLB_CTRL_REG1                                                  0x2206004
++#define ixPB1_RX_GLB_CTRL_REG2                                                  0x2206008
++#define ixPB1_RX_GLB_CTRL_REG3                                                  0x220600c
++#define ixPB1_RX_GLB_CTRL_REG4                                                  0x2206010
++#define ixPB1_RX_GLB_CTRL_REG5                                                  0x2206014
++#define ixPB1_RX_GLB_CTRL_REG6                                                  0x2206018
++#define ixPB1_RX_GLB_CTRL_REG7                                                  0x220601c
++#define ixPB1_RX_GLB_CTRL_REG8                                                  0x2206020
++#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0                                         0x2206028
++#define ixPB1_RX_GLB_OVRD_REG0                                                  0x2206030
++#define ixPB1_RX_GLB_OVRD_REG1                                                  0x2206034
++#define ixPB1_RX_LANE0_CTRL_REG0                                                0x2206440
++#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0                                       0x2206448
++#define ixPB1_RX_LANE1_CTRL_REG0                                                0x2206480
++#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0                                       0x2206488
++#define ixPB1_RX_LANE2_CTRL_REG0                                                0x2206500
++#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0                                       0x2206508
++#define ixPB1_RX_LANE3_CTRL_REG0                                                0x2206600
++#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0                                       0x2206608
++#define ixPB1_RX_LANE4_CTRL_REG0                                                0x2206800
++#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0                                       0x2206848
++#define ixPB1_RX_LANE5_CTRL_REG0                                                0x2206880
++#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0                                       0x2206888
++#define ixPB1_RX_LANE6_CTRL_REG0                                                0x2206900
++#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0                                       0x2206908
++#define ixPB1_RX_LANE7_CTRL_REG0                                                0x2206a00
++#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0                                       0x2206a08
++#define ixPB1_RX_LANE8_CTRL_REG0                                                0x2207440
++#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0                                       0x2207448
++#define ixPB1_RX_LANE9_CTRL_REG0                                                0x2207480
++#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0                                       0x2207488
++#define ixPB1_RX_LANE10_CTRL_REG0                                               0x2207500
++#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0                                      0x2207508
++#define ixPB1_RX_LANE11_CTRL_REG0                                               0x2207600
++#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0                                      0x2207608
++#define ixPB1_RX_LANE12_CTRL_REG0                                               0x2207840
++#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0                                      0x2207848
++#define ixPB1_RX_LANE13_CTRL_REG0                                               0x2207880
++#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0                                      0x2207888
++#define ixPB1_RX_LANE14_CTRL_REG0                                               0x2207900
++#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0                                      0x2207908
++#define ixPB1_RX_LANE15_CTRL_REG0                                               0x2207a00
++#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0                                      0x2207a08
++#define ixPB1_TX_GLB_CTRL_REG0                                                  0x2208000
++#define ixPB1_TX_GLB_LANE_SKEW_CTRL                                             0x2208004
++#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0                                         0x2208010
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0                                    0x2208014
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1                                    0x2208018
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2                                    0x220801c
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3                                    0x2208020
++#define ixPB1_TX_GLB_OVRD_REG0                                                  0x2208030
++#define ixPB1_TX_GLB_OVRD_REG1                                                  0x2208034
++#define ixPB1_TX_GLB_OVRD_REG2                                                  0x2208038
++#define ixPB1_TX_GLB_OVRD_REG3                                                  0x220803c
++#define ixPB1_TX_GLB_OVRD_REG4                                                  0x2208040
++#define ixPB1_TX_LANE0_CTRL_REG0                                                0x2208440
++#define ixPB1_TX_LANE0_OVRD_REG0                                                0x2208444
++#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0                                       0x2208448
++#define ixPB1_TX_LANE1_CTRL_REG0                                                0x2208480
++#define ixPB1_TX_LANE1_OVRD_REG0                                                0x2208484
++#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0                                       0x2208488
++#define ixPB1_TX_LANE2_CTRL_REG0                                                0x2208500
++#define ixPB1_TX_LANE2_OVRD_REG0                                                0x2208504
++#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0                                       0x2208508
++#define ixPB1_TX_LANE3_CTRL_REG0                                                0x2208600
++#define ixPB1_TX_LANE3_OVRD_REG0                                                0x2208604
++#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0                                       0x2208608
++#define ixPB1_TX_LANE4_CTRL_REG0                                                0x2208840
++#define ixPB1_TX_LANE4_OVRD_REG0                                                0x2208844
++#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0                                       0x2208848
++#define ixPB1_TX_LANE5_CTRL_REG0                                                0x2208880
++#define ixPB1_TX_LANE5_OVRD_REG0                                                0x2208884
++#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0                                       0x2208888
++#define ixPB1_TX_LANE6_CTRL_REG0                                                0x2208900
++#define ixPB1_TX_LANE6_OVRD_REG0                                                0x2208904
++#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0                                       0x2208908
++#define ixPB1_TX_LANE7_CTRL_REG0                                                0x2208a00
++#define ixPB1_TX_LANE7_OVRD_REG0                                                0x2208a04
++#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0                                       0x2208a08
++#define ixPB1_TX_LANE8_CTRL_REG0                                                0x2209440
++#define ixPB1_TX_LANE8_OVRD_REG0                                                0x2209444
++#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0                                       0x2209448
++#define ixPB1_TX_LANE9_CTRL_REG0                                                0x2209480
++#define ixPB1_TX_LANE9_OVRD_REG0                                                0x2209484
++#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0                                       0x2209488
++#define ixPB1_TX_LANE10_CTRL_REG0                                               0x2209500
++#define ixPB1_TX_LANE10_OVRD_REG0                                               0x2209504
++#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0                                      0x2209508
++#define ixPB1_TX_LANE11_CTRL_REG0                                               0x2209600
++#define ixPB1_TX_LANE11_OVRD_REG0                                               0x2209604
++#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0                                      0x2209608
++#define ixPB1_TX_LANE12_CTRL_REG0                                               0x2209840
++#define ixPB1_TX_LANE12_OVRD_REG0                                               0x2209844
++#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0                                      0x2209848
++#define ixPB1_TX_LANE13_CTRL_REG0                                               0x2209880
++#define ixPB1_TX_LANE13_OVRD_REG0                                               0x2209884
++#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0                                      0x2209888
++#define ixPB1_TX_LANE14_CTRL_REG0                                               0x2209900
++#define ixPB1_TX_LANE14_OVRD_REG0                                               0x2209904
++#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0                                      0x2209908
++#define ixPB1_TX_LANE15_CTRL_REG0                                               0x2209a00
++#define ixPB1_TX_LANE15_OVRD_REG0                                               0x2209a04
++#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0                                      0x2209a08
++#define ixPB0_PIF_SCRATCH                                                       0x1100001
++#define ixPB0_PIF_HW_DEBUG                                                      0x1100002
++#define ixPB0_PIF_PRG6                                                          0x1100003
++#define ixPB0_PIF_PRG7                                                          0x1100004
++#define ixPB0_PIF_CNTL                                                          0x1100010
++#define ixPB0_PIF_PAIRING                                                       0x1100011
++#define ixPB0_PIF_PWRDOWN_0                                                     0x1100012
++#define ixPB0_PIF_PWRDOWN_1                                                     0x1100013
++#define ixPB0_PIF_CNTL2                                                         0x1100014
++#define ixPB0_PIF_TXPHYSTATUS                                                   0x1100015
++#define ixPB0_PIF_SC_CTL                                                        0x1100016
++#define ixPB0_PIF_PWRDOWN_2                                                     0x1100017
++#define ixPB0_PIF_PWRDOWN_3                                                     0x1100018
++#define ixPB0_PIF_SC_CTL2                                                       0x1100019
++#define ixPB0_PIF_PRG0                                                          0x110001a
++#define ixPB0_PIF_PRG1                                                          0x110001b
++#define ixPB0_PIF_PRG2                                                          0x110001c
++#define ixPB0_PIF_PRG3                                                          0x110001d
++#define ixPB0_PIF_PRG4                                                          0x110001e
++#define ixPB0_PIF_PRG5                                                          0x110001f
++#define ixPB0_PIF_PDNB_OVERRIDE_0                                               0x1100020
++#define ixPB0_PIF_PDNB_OVERRIDE_1                                               0x1100021
++#define ixPB0_PIF_PDNB_OVERRIDE_2                                               0x1100022
++#define ixPB0_PIF_PDNB_OVERRIDE_3                                               0x1100023
++#define ixPB0_PIF_PDNB_OVERRIDE_4                                               0x1100024
++#define ixPB0_PIF_PDNB_OVERRIDE_5                                               0x1100025
++#define ixPB0_PIF_PDNB_OVERRIDE_6                                               0x1100026
++#define ixPB0_PIF_PDNB_OVERRIDE_7                                               0x1100027
++#define ixPB0_PIF_SEQ_STATUS_0                                                  0x1100028
++#define ixPB0_PIF_SEQ_STATUS_1                                                  0x1100029
++#define ixPB0_PIF_SEQ_STATUS_2                                                  0x110002a
++#define ixPB0_PIF_SEQ_STATUS_3                                                  0x110002b
++#define ixPB0_PIF_SEQ_STATUS_4                                                  0x110002c
++#define ixPB0_PIF_SEQ_STATUS_5                                                  0x110002d
++#define ixPB0_PIF_SEQ_STATUS_6                                                  0x110002e
++#define ixPB0_PIF_SEQ_STATUS_7                                                  0x110002f
++#define ixPB0_PIF_PDNB_OVERRIDE_8                                               0x1100030
++#define ixPB0_PIF_PDNB_OVERRIDE_9                                               0x1100031
++#define ixPB0_PIF_PDNB_OVERRIDE_10                                              0x1100032
++#define ixPB0_PIF_PDNB_OVERRIDE_11                                              0x1100033
++#define ixPB0_PIF_PDNB_OVERRIDE_12                                              0x1100034
++#define ixPB0_PIF_PDNB_OVERRIDE_13                                              0x1100035
++#define ixPB0_PIF_PDNB_OVERRIDE_14                                              0x1100036
++#define ixPB0_PIF_PDNB_OVERRIDE_15                                              0x1100037
++#define ixPB0_PIF_SEQ_STATUS_8                                                  0x1100038
++#define ixPB0_PIF_SEQ_STATUS_9                                                  0x1100039
++#define ixPB0_PIF_SEQ_STATUS_10                                                 0x110003a
++#define ixPB0_PIF_SEQ_STATUS_11                                                 0x110003b
++#define ixPB0_PIF_SEQ_STATUS_12                                                 0x110003c
++#define ixPB0_PIF_SEQ_STATUS_13                                                 0x110003d
++#define ixPB0_PIF_SEQ_STATUS_14                                                 0x110003e
++#define ixPB0_PIF_SEQ_STATUS_15                                                 0x110003f
++#define ixPB1_PIF_SCRATCH                                                       0x2100001
++#define ixPB1_PIF_HW_DEBUG                                                      0x2100002
++#define ixPB1_PIF_PRG6                                                          0x2100003
++#define ixPB1_PIF_PRG7                                                          0x2100004
++#define ixPB1_PIF_CNTL                                                          0x2100010
++#define ixPB1_PIF_PAIRING                                                       0x2100011
++#define ixPB1_PIF_PWRDOWN_0                                                     0x2100012
++#define ixPB1_PIF_PWRDOWN_1                                                     0x2100013
++#define ixPB1_PIF_CNTL2                                                         0x2100014
++#define ixPB1_PIF_TXPHYSTATUS                                                   0x2100015
++#define ixPB1_PIF_SC_CTL                                                        0x2100016
++#define ixPB1_PIF_PWRDOWN_2                                                     0x2100017
++#define ixPB1_PIF_PWRDOWN_3                                                     0x2100018
++#define ixPB1_PIF_SC_CTL2                                                       0x2100019
++#define ixPB1_PIF_PRG0                                                          0x210001a
++#define ixPB1_PIF_PRG1                                                          0x210001b
++#define ixPB1_PIF_PRG2                                                          0x210001c
++#define ixPB1_PIF_PRG3                                                          0x210001d
++#define ixPB1_PIF_PRG4                                                          0x210001e
++#define ixPB1_PIF_PRG5                                                          0x210001f
++#define ixPB1_PIF_PDNB_OVERRIDE_0                                               0x2100020
++#define ixPB1_PIF_PDNB_OVERRIDE_1                                               0x2100021
++#define ixPB1_PIF_PDNB_OVERRIDE_2                                               0x2100022
++#define ixPB1_PIF_PDNB_OVERRIDE_3                                               0x2100023
++#define ixPB1_PIF_PDNB_OVERRIDE_4                                               0x2100024
++#define ixPB1_PIF_PDNB_OVERRIDE_5                                               0x2100025
++#define ixPB1_PIF_PDNB_OVERRIDE_6                                               0x2100026
++#define ixPB1_PIF_PDNB_OVERRIDE_7                                               0x2100027
++#define ixPB1_PIF_SEQ_STATUS_0                                                  0x2100028
++#define ixPB1_PIF_SEQ_STATUS_1                                                  0x2100029
++#define ixPB1_PIF_SEQ_STATUS_2                                                  0x210002a
++#define ixPB1_PIF_SEQ_STATUS_3                                                  0x210002b
++#define ixPB1_PIF_SEQ_STATUS_4                                                  0x210002c
++#define ixPB1_PIF_SEQ_STATUS_5                                                  0x210002d
++#define ixPB1_PIF_SEQ_STATUS_6                                                  0x210002e
++#define ixPB1_PIF_SEQ_STATUS_7                                                  0x210002f
++#define ixPB1_PIF_PDNB_OVERRIDE_8                                               0x2100030
++#define ixPB1_PIF_PDNB_OVERRIDE_9                                               0x2100031
++#define ixPB1_PIF_PDNB_OVERRIDE_10                                              0x2100032
++#define ixPB1_PIF_PDNB_OVERRIDE_11                                              0x2100033
++#define ixPB1_PIF_PDNB_OVERRIDE_12                                              0x2100034
++#define ixPB1_PIF_PDNB_OVERRIDE_13                                              0x2100035
++#define ixPB1_PIF_PDNB_OVERRIDE_14                                              0x2100036
++#define ixPB1_PIF_PDNB_OVERRIDE_15                                              0x2100037
++#define ixPB1_PIF_SEQ_STATUS_8                                                  0x2100038
++#define ixPB1_PIF_SEQ_STATUS_9                                                  0x2100039
++#define ixPB1_PIF_SEQ_STATUS_10                                                 0x210003a
++#define ixPB1_PIF_SEQ_STATUS_11                                                 0x210003b
++#define ixPB1_PIF_SEQ_STATUS_12                                                 0x210003c
++#define ixPB1_PIF_SEQ_STATUS_13                                                 0x210003d
++#define ixPB1_PIF_SEQ_STATUS_14                                                 0x210003e
++#define ixPB1_PIF_SEQ_STATUS_15                                                 0x210003f
++#define mmBIF_RFE_SNOOP_REG                                                     0x27
++#define mmBIF_RFE_WARMRST_CNTL                                                  0x1459
++#define mmBIF_RFE_SOFTRST_CNTL                                                  0x1441
++#define mmBIF_RFE_IMPRST_CNTL                                                   0x1458
++#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER                                        0x1442
++#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER                                        0x1443
++#define mmBIF_PWDN_COMMAND                                                      0x1444
++#define mmBIF_PWDN_STATUS                                                       0x1445
++#define mmBIF_RFE_MST_BU_CMDSTATUS                                              0x1446
++#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS                                  0x1447
++#define mmBIF_RFE_MST_BX_CMDSTATUS                                              0x1448
++#define mmBIF_RFE_MST_TMOUT_STATUS                                              0x144b
++#define mmBIF_RFE_MMCFG_CNTL                                                    0x144c
++#define mmBIF_CC_RFE_IMP_OVERRIDECNTL                                           0x1455
++#define mmBIF_IMPCTL_SMPLCNTL                                                   0x1450
++#define mmBIF_IMPCTL_RXCNTL                                                     0x1451
++#define mmBIF_IMPCTL_TXCNTL_pd                                                  0x1452
++#define mmBIF_IMPCTL_TXCNTL_pu                                                  0x1453
++#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD                              0x1454
++#define mmBIF_CLOCKS_BITS                                                       0x1489
++#define mmBIF_LNCNT_RESET                                                       0x1488
++#define mmLNCNT_CONTROL                                                         0x1487
++#define mmNEW_REFCLKB_TIMER                                                     0x1485
++#define mmNEW_REFCLKB_TIMER_1                                                   0x1484
++#define mmBIF_CLK_PDWN_DELAY_TIMER                                              0x1483
++#define mmBIF_RESET_EN                                                          0x1482
++#define mmBIF_PIF_TXCLK_SWITCH_TIMER                                            0x1481
++#define mmBIF_BACO_MSIC                                                         0x1480
++#define mmBIF_RESET_CNTL                                                        0x1486
++#define mmBIF_RFE_CNTL_MISC                                                     0x148c
++
++#endif /* BIF_4_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
+new file mode 100644
+index 0000000..8fbfd02
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
+@@ -0,0 +1,10250 @@
++/*
++ * BIF_4_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_4_1_SH_MASK_H
++#define BIF_4_1_SH_MASK_H
++
++#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
++#define MM_INDEX__MM_OFFSET__SHIFT 0x0
++#define MM_INDEX__MM_APER_MASK 0x80000000
++#define MM_INDEX__MM_APER__SHIFT 0x1f
++#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
++#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
++#define MM_DATA__MM_DATA_MASK 0xffffffff
++#define MM_DATA__MM_DATA__SHIFT 0x0
++#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
++#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
++#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
++#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
++#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
++#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
++#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
++#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
++#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
++#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
++#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
++#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
++#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
++#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
++#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
++#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
++#define BUS_CNTL__SET_MC_TC_MASK 0xe000
++#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
++#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
++#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
++#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
++#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
++#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
++#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
++#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
++#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
++#define CONFIG_CNTL__VGA_DIS_MASK 0x2
++#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
++#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
++#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
++#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
++#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
++#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
++#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
++#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
++#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
++#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
++#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
++#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
++#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
++#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
++#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
++#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
++#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
++#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
++#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
++#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
++#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
++#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
++#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
++#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
++#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
++#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
++#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
++#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
++#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
++#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
++#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
++#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
++#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
++#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
++#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
++#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
++#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
++#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
++#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
++#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
++#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
++#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
++#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
++#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
++#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
++#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
++#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
++#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
++#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
++#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
++#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
++#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
++#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
++#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
++#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
++#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
++#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
++#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
++#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
++#define SMBUS_SLV_CNTL__SMB_SOFT_RESET_MASK 0x1
++#define SMBUS_SLV_CNTL__SMB_SOFT_RESET__SHIFT 0x0
++#define SMBUS_SLV_CNTL__SMB_SLV_ADR_MASK 0xfe
++#define SMBUS_SLV_CNTL__SMB_SLV_ADR__SHIFT 0x1
++#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD_MASK 0x3fffff
++#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD__SHIFT 0x0
++#define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL_MASK 0x1000000
++#define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL__SHIFT 0x18
++#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS_MASK 0x2000000
++#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS__SHIFT 0x19
++#define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0xfc000000
++#define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x1a
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
++#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
++#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
++#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
++#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
++#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
++#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
++#define BIF_FB_EN__FB_READ_EN_MASK 0x1
++#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
++#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
++#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
++#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
++#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
++#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
++#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
++#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
++#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
++#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
++#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
++#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
++#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
++#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
++#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
++#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
++#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
++#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
++#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
++#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
++#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
++#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
++#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
++#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
++#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
++#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
++#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
++#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
++#define HOST_BUSNUM__HOST_ID_MASK 0xffff
++#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
++#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
++#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
++#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
++#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
++#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e
++#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1
++#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
++#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
++#define BACO_CNTL__BACO_EN_MASK 0x1
++#define BACO_CNTL__BACO_EN__SHIFT 0x0
++#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
++#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
++#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
++#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
++#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
++#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
++#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
++#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
++#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
++#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
++#define BACO_CNTL__BACO_MODE_MASK 0x40
++#define BACO_CNTL__BACO_MODE__SHIFT 0x6
++#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
++#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
++#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
++#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
++#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
++#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
++#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
++#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
++#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
++#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
++#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
++#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
++#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
++#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
++#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
++#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
++#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x1
++#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x0
++#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x2
++#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x1
++#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x4
++#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x2
++#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x3fffc
++#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x2
++#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000
++#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x1e
++#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000
++#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x1f
++#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x3fffc
++#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x2
++#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x3fffc
++#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x2
++#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000
++#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000
++#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x3fffc
++#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x2
++#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x3fffc
++#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x2
++#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000
++#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000
++#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x3fffc
++#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x2
++#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x3fffc
++#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x2
++#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000
++#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000
++#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x3fffc
++#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x2
++#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x3fffc
++#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x2
++#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000
++#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x1e
++#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000
++#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x1f
++#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x3fffc
++#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x2
++#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x3fffc
++#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x2
++#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000
++#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d
++#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000
++#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x1e
++#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000
++#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x1f
++#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x3fffc
++#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x2
++#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
++#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
++#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
++#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
++#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
++#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
++#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
++#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
++#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
++#define VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define DEVICE_ID__DEVICE_ID_MASK 0xffff
++#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
++#define COMMAND__IO_ACCESS_EN_MASK 0x1
++#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define COMMAND__BUS_MASTER_EN_MASK 0x4
++#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define COMMAND__AD_STEPPING_MASK 0x80
++#define COMMAND__AD_STEPPING__SHIFT 0x7
++#define COMMAND__SERR_EN_MASK 0x100
++#define COMMAND__SERR_EN__SHIFT 0x8
++#define COMMAND__FAST_B2B_EN_MASK 0x200
++#define COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define COMMAND__INT_DIS_MASK 0x400
++#define COMMAND__INT_DIS__SHIFT 0xa
++#define STATUS__INT_STATUS_MASK 0x8
++#define STATUS__INT_STATUS__SHIFT 0x3
++#define STATUS__CAP_LIST_MASK 0x10
++#define STATUS__CAP_LIST__SHIFT 0x4
++#define STATUS__PCI_66_EN_MASK 0x20
++#define STATUS__PCI_66_EN__SHIFT 0x5
++#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
++#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
++#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
++#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
++#define STATUS__DEVSEL_TIMING_MASK 0x600
++#define STATUS__DEVSEL_TIMING__SHIFT 0x9
++#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
++#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
++#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
++#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
++#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
++#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
++#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
++#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
++#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
++#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
++#define REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
++#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
++#define SUB_CLASS__SUB_CLASS_MASK 0xff
++#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
++#define BASE_CLASS__BASE_CLASS_MASK 0xff
++#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
++#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define LATENCY__LATENCY_TIMER_MASK 0xff
++#define LATENCY__LATENCY_TIMER__SHIFT 0x0
++#define HEADER__HEADER_TYPE_MASK 0x7f
++#define HEADER__HEADER_TYPE__SHIFT 0x0
++#define HEADER__DEVICE_TYPE_MASK 0x80
++#define HEADER__DEVICE_TYPE__SHIFT 0x7
++#define BIST__BIST_COMP_MASK 0xf
++#define BIST__BIST_COMP__SHIFT 0x0
++#define BIST__BIST_STRT_MASK 0x40
++#define BIST__BIST_STRT__SHIFT 0x6
++#define BIST__BIST_CAP_MASK 0x80
++#define BIST__BIST_CAP__SHIFT 0x7
++#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
++#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
++#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
++#define CAP_PTR__CAP_PTR_MASK 0xff
++#define CAP_PTR__CAP_PTR__SHIFT 0x0
++#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
++#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
++#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
++#define MIN_GRANT__MIN_GNT_MASK 0xff
++#define MIN_GRANT__MIN_GNT__SHIFT 0x0
++#define MAX_LATENCY__MAX_LAT_MASK 0xff
++#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
++#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
++#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
++#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
++#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
++#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
++#define PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define PMI_CAP__VERSION_MASK 0x7
++#define PMI_CAP__VERSION__SHIFT 0x0
++#define PMI_CAP__PME_CLOCK_MASK 0x8
++#define PMI_CAP__PME_CLOCK__SHIFT 0x3
++#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
++#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
++#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
++#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
++#define PMI_CAP__D1_SUPPORT_MASK 0x200
++#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
++#define PMI_CAP__D2_SUPPORT_MASK 0x400
++#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
++#define PMI_CAP__PME_SUPPORT_MASK 0xf800
++#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
++#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define PCIE_CAP__VERSION_MASK 0xf
++#define PCIE_CAP__VERSION__SHIFT 0x0
++#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
++#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
++#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
++#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
++#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
++#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
++#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
++#define DEVICE_STATUS__CORR_ERR_MASK 0x1
++#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
++#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
++#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
++#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
++#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
++#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
++#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
++#define DEVICE_STATUS__AUX_PWR_MASK 0x10
++#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
++#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
++#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
++#define LINK_CAP__LINK_SPEED_MASK 0xf
++#define LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define LINK_CNTL__PM_CONTROL_MASK 0x3
++#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define LINK_CNTL__LINK_DIS_MASK 0x10
++#define LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
++#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
++#define LINK_STATUS__LINK_TRAINING_MASK 0x800
++#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
++#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
++#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
++#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
++#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define DEVICE_STATUS2__RESERVED_MASK 0xffff
++#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
++#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define LINK_CAP2__RESERVED__SHIFT 0x9
++#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
++#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
++#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
++#define MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
++#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
++#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
++#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
++#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
++#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
++#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
++#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
++#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
++#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
++#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
++#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
++#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
++#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
++#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
++#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
++#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
++#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
++#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
++#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
++#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
++#define PCIE_ATS_CNTL__STU_MASK 0x1f
++#define PCIE_ATS_CNTL__STU__SHIFT 0x0
++#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
++#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
++#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
++#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
++#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
++#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
++#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
++#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
++#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
++#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
++#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
++#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
++#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
++#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
++#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
++#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
++#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
++#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
++#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
++#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
++#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
++#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
++#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
++#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
++#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
++#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
++#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
++#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
++#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
++#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
++#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
++#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
++#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
++#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
++#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
++#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000
++#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14
++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
++#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
++#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
++#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
++#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
++#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
++#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
++#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
++#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
++#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
++#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
++#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
++#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
++#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
++#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
++#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
++#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
++#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
++#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
++#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
++#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
++#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
++#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
++#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
++#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
++#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
++#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
++#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
++#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
++#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
++#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
++#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
++#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
++#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
++#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
++#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
++#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
++#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
++#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
++#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
++#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
++#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
++#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
++#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
++#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
++#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
++#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
++#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
++#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
++#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
++#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
++#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
++#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
++#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
++#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
++#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
++#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
++#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
++#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
++#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
++#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
++#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
++#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
++#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
++#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
++#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
++#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
++#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
++#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
++#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
++#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
++#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
++#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
++#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
++#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
++#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
++#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
++#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
++#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
++#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
++#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
++#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
++#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
++#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
++#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
++#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
++#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
++#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
++#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1
++#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0
++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
++#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
++#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1
++#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0
++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
++#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
++#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf
++#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0
++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
++#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
++#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
++#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
++#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
++#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
++#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
++#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
++#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
++#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
++#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
++#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6
++#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8
++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3
++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10
++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4
++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60
++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5
++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80
++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7
++#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
++#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
++#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
++#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
++#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
++#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
++#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff
++#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
++#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
++#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
++#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
++#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
++#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
++#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
++#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
++#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
++#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
++#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
++#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
++#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
++#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
++#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
++#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
++#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
++#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
++#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
++#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
++#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
++#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
++#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
++#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
++#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
++#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
++#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
++#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
++#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
++#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
++#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
++#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
++#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
++#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
++#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
++#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
++#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
++#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
++#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
++#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
++#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
++#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
++#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
++#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
++#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
++#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
++#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
++#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
++#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
++#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
++#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x1
++#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x0
++#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x2
++#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x1
++#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x4
++#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x2
++#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x8
++#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x3
++#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x10
++#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x4
++#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x20
++#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x5
++#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x40
++#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x6
++#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x80
++#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x7
++#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x100
++#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x8
++#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x200
++#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x9
++#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x400
++#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0xa
++#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x800
++#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0xb
++#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x1000
++#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0xc
++#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x2000
++#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0xd
++#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x4000
++#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0xe
++#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x8000
++#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0xf
++#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x10000
++#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x10
++#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x20000
++#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x11
++#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x40000
++#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x12
++#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x80000
++#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x13
++#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x100000
++#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x14
++#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x200000
++#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x15
++#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x400000
++#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x16
++#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x800000
++#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x17
++#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x1000000
++#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x18
++#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x2000000
++#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x19
++#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x4000000
++#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x1a
++#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x8000000
++#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x1b
++#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000
++#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x1c
++#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000
++#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d
++#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000
++#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x1e
++#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000
++#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x1f
++#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
++#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
++#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
++#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
++#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
++#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
++#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
++#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
++#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
++#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
++#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
++#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
++#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
++#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
++#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
++#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
++#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
++#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
++#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
++#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
++#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
++#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
++#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
++#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
++#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
++#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
++#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
++#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
++#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
++#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
++#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
++#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
++#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
++#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
++#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
++#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
++#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
++#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
++#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
++#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
++#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
++#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
++#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
++#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
++#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
++#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
++#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
++#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
++#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
++#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
++#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
++#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
++#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
++#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
++#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000
++#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e
++#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
++#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
++#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
++#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000
++#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
++#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000
++#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17
++#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000
++#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
++#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
++#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
++#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
++#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
++#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
++#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
++#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
++#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
++#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
++#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
++#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
++#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
++#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
++#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
++#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
++#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
++#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
++#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
++#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
++#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
++#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
++#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
++#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
++#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
++#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
++#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
++#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
++#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
++#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
++#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
++#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
++#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
++#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
++#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
++#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
++#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
++#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
++#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
++#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
++#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
++#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
++#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
++#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
++#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
++#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
++#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
++#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
++#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
++#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
++#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
++#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
++#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
++#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
++#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
++#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
++#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
++#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
++#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
++#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
++#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
++#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
++#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
++#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
++#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
++#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
++#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
++#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
++#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
++#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
++#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
++#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
++#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
++#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
++#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
++#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
++#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
++#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
++#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
++#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
++#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
++#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
++#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
++#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
++#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
++#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
++#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
++#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
++#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
++#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
++#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
++#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
++#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
++#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
++#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
++#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
++#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
++#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
++#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
++#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
++#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
++#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
++#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
++#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
++#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
++#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
++#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
++#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
++#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
++#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
++#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
++#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
++#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
++#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
++#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
++#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
++#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
++#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
++#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
++#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
++#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
++#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
++#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
++#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
++#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
++#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
++#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
++#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
++#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
++#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
++#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
++#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
++#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
++#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
++#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
++#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
++#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
++#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000
++#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
++#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
++#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
++#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
++#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
++#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
++#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
++#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
++#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
++#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
++#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
++#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
++#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
++#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
++#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
++#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
++#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
++#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
++#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
++#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
++#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
++#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
++#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
++#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
++#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
++#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
++#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
++#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
++#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
++#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
++#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
++#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
++#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
++#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff
++#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
++#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
++#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
++#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
++#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
++#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
++#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
++#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
++#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
++#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
++#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
++#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
++#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
++#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
++#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
++#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
++#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
++#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
++#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
++#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
++#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
++#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
++#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
++#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
++#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
++#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
++#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
++#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
++#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
++#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
++#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
++#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
++#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
++#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
++#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
++#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
++#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
++#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
++#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
++#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
++#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
++#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
++#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
++#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
++#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
++#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
++#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
++#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
++#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
++#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
++#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x1
++#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x0
++#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x2
++#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x1
++#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x4
++#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x2
++#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x8
++#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x3
++#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x10
++#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x4
++#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x20
++#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x5
++#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x40
++#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x6
++#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x80
++#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x7
++#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x100
++#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x8
++#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x200
++#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x9
++#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x400
++#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0xa
++#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x800
++#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0xb
++#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x1000
++#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0xc
++#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x2000
++#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0xd
++#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x4000
++#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0xe
++#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x8000
++#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0xf
++#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x10000
++#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x10
++#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x20000
++#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x11
++#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x40000
++#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x12
++#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x80000
++#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x13
++#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x100000
++#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x14
++#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x200000
++#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x15
++#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x400000
++#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x16
++#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x800000
++#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x17
++#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x1000000
++#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x18
++#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x2000000
++#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x19
++#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x4000000
++#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x1a
++#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x8000000
++#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x1b
++#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000
++#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x1c
++#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000
++#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x1d
++#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000
++#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x1e
++#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000
++#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x1f
++#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
++#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
++#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
++#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
++#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
++#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
++#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
++#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
++#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
++#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
++#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
++#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
++#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
++#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
++#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
++#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
++#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
++#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
++#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
++#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
++#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
++#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
++#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
++#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
++#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
++#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
++#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
++#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
++#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
++#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
++#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
++#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
++#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
++#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
++#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
++#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
++#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
++#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
++#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
++#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
++#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
++#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
++#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
++#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
++#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
++#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
++#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
++#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
++#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
++#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
++#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
++#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
++#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
++#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
++#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000
++#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e
++#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
++#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
++#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
++#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000
++#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
++#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000
++#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17
++#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000
++#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
++#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
++#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
++#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
++#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
++#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
++#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
++#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
++#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
++#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
++#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
++#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
++#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
++#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
++#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
++#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
++#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
++#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
++#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
++#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
++#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
++#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
++#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
++#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
++#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
++#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
++#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
++#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
++#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
++#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
++#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
++#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
++#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
++#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
++#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
++#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
++#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
++#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
++#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
++#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
++#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
++#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
++#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
++#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
++#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
++#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
++#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
++#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
++#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
++#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
++#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
++#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
++#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
++#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
++#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
++#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
++#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
++#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
++#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
++#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
++#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
++#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
++#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
++#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
++#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
++#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
++#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
++#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
++#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
++#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
++#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
++#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
++#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
++#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
++#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
++#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
++#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
++#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
++#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
++#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
++#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
++#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
++#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
++#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
++#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
++#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
++#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
++#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
++#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
++#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
++#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
++#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
++#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
++#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
++#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
++#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
++#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
++#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
++#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
++#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
++#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
++#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
++#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
++#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
++#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
++#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
++#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
++#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
++#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
++#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
++#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
++#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
++#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
++#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
++#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
++#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
++#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
++#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
++#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
++#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
++#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
++#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
++#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
++#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
++#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
++#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
++#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
++#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
++#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
++#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
++#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
++#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
++#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
++#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
++#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
++#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
++#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
++#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000
++#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
++#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
++#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
++#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
++#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
++#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
++#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
++#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
++#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
++#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
++#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
++#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
++#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
++#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
++#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
++#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
++#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
++#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
++#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
++#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
++#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
++#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
++#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
++#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
++#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
++#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
++#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
++#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
++#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
++#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
++#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
++#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
++#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
++#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
++#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x1
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x0
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x2
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x1
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x4
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x2
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x8
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x3
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x10
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x4
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x20
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x5
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x40
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x6
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x80
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x7
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x100
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x8
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x200
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x9
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x400
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0xa
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x800
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0xb
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x1000
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0xc
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x2000
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0xd
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x4000
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0xe
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x8000
++#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0xf
++#define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff
++#define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0
++#define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff
++#define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0
++#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1
++#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0
++#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2
++#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1
++#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4
++#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2
++#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8
++#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3
++#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10
++#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4
++#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20
++#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5
++#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40
++#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6
++#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80
++#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7
++#define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x100
++#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8
++#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200
++#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9
++#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400
++#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa
++#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800
++#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb
++#define PB0_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000
++#define PB0_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc
++#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000
++#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd
++#define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000
++#define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe
++#define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000
++#define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf
++#define PB0_PIF_CNTL__TXGND_TIME_MASK 0x10000
++#define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x10
++#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000
++#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11
++#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000
++#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14
++#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000
++#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17
++#define PB0_PIF_CNTL__RXEN_GATER_MASK 0xf000000
++#define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x18
++#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000
++#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c
++#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000
++#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d
++#define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000
++#define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e
++#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x1
++#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0
++#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x2
++#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1
++#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x4
++#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2
++#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x8
++#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3
++#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x10
++#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4
++#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x20
++#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5
++#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x40
++#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6
++#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x80
++#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7
++#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x100
++#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8
++#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x200
++#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9
++#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x400
++#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa
++#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x800
++#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb
++#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000
++#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10
++#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000
++#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11
++#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000
++#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14
++#define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x2000000
++#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x19
++#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7
++#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0
++#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8
++#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3
++#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70
++#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4
++#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380
++#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7
++#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00
++#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa
++#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000
++#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10
++#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000
++#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18
++#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000
++#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c
++#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000
++#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d
++#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7
++#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0
++#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8
++#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3
++#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70
++#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4
++#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380
++#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7
++#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00
++#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa
++#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000
++#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10
++#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000
++#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18
++#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000
++#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c
++#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000
++#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d
++#define PB0_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1
++#define PB0_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0
++#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6
++#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1
++#define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8
++#define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3
++#define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10
++#define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4
++#define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20
++#define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5
++#define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40
++#define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000
++#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17
++#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000
++#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18
++#define PB0_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000
++#define PB0_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b
++#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000
++#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c
++#define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000
++#define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d
++#define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000
++#define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e
++#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000
++#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000
++#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf
++#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1
++#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0
++#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x2
++#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1
++#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4
++#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2
++#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8
++#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3
++#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10
++#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4
++#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20
++#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5
++#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40
++#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6
++#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x100
++#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8
++#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x200
++#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9
++#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x400
++#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa
++#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x800
++#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb
++#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000
++#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc
++#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000
++#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd
++#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000
++#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe
++#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000
++#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf
++#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000
++#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10
++#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000
++#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11
++#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000
++#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12
++#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000
++#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13
++#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000
++#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14
++#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000
++#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15
++#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000
++#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16
++#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000
++#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17
++#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000
++#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18
++#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000
++#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19
++#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000
++#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a
++#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000
++#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b
++#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000
++#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c
++#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000
++#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d
++#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000
++#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e
++#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000
++#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f
++#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7
++#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0
++#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8
++#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3
++#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70
++#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4
++#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380
++#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7
++#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00
++#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa
++#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000
++#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10
++#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000
++#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18
++#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000
++#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c
++#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000
++#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d
++#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7
++#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0
++#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8
++#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3
++#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70
++#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4
++#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380
++#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7
++#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00
++#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa
++#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000
++#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10
++#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000
++#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18
++#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000
++#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c
++#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000
++#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000
++#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf
++#define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff
++#define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0
++#define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff
++#define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0
++#define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff
++#define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0
++#define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff
++#define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0
++#define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff
++#define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0
++#define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff
++#define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf
++#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf
++#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1
++#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0
++#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe
++#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1
++#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10
++#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4
++#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0
++#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5
++#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100
++#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8
++#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200
++#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9
++#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400
++#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa
++#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800
++#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb
++#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000
++#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe
++#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000
++#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf
++#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8
++#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1
++#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0
++#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2
++#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1
++#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4
++#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2
++#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8
++#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3
++#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10
++#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4
++#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20
++#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5
++#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40
++#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6
++#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700
++#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8
++#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
++#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x1
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x0
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x2
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x1
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x4
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x2
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x8
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x3
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x10
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x4
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x20
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x5
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x40
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x6
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x80
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x7
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x100
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x8
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x200
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x9
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x400
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0xa
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x800
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0xb
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x1000
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0xc
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x2000
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0xd
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x4000
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0xe
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x8000
++#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0xf
++#define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff
++#define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0
++#define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff
++#define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0
++#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1
++#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0
++#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2
++#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1
++#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4
++#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2
++#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8
++#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3
++#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10
++#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4
++#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20
++#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5
++#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40
++#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6
++#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80
++#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7
++#define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x100
++#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8
++#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200
++#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9
++#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400
++#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa
++#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800
++#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb
++#define PB1_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000
++#define PB1_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc
++#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000
++#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd
++#define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000
++#define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe
++#define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000
++#define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf
++#define PB1_PIF_CNTL__TXGND_TIME_MASK 0x10000
++#define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x10
++#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000
++#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11
++#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000
++#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14
++#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000
++#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17
++#define PB1_PIF_CNTL__RXEN_GATER_MASK 0xf000000
++#define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x18
++#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000
++#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c
++#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000
++#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d
++#define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000
++#define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e
++#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x1
++#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0
++#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x2
++#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1
++#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x4
++#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2
++#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x8
++#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3
++#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x10
++#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4
++#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x20
++#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5
++#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x40
++#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6
++#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x80
++#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7
++#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x100
++#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8
++#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x200
++#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9
++#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x400
++#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa
++#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x800
++#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb
++#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000
++#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10
++#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000
++#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11
++#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000
++#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14
++#define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x2000000
++#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x19
++#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7
++#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0
++#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8
++#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3
++#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70
++#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4
++#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380
++#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7
++#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00
++#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa
++#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000
++#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10
++#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000
++#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18
++#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000
++#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c
++#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000
++#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d
++#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7
++#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0
++#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8
++#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3
++#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70
++#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4
++#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380
++#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7
++#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00
++#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa
++#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000
++#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10
++#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000
++#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18
++#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000
++#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c
++#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000
++#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d
++#define PB1_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1
++#define PB1_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0
++#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6
++#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1
++#define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8
++#define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3
++#define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10
++#define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4
++#define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20
++#define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5
++#define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40
++#define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000
++#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17
++#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000
++#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18
++#define PB1_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000
++#define PB1_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b
++#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000
++#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c
++#define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000
++#define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d
++#define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000
++#define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e
++#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000
++#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000
++#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf
++#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1
++#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0
++#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x2
++#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1
++#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4
++#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2
++#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8
++#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3
++#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10
++#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4
++#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20
++#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5
++#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40
++#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6
++#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x100
++#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8
++#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x200
++#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9
++#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x400
++#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa
++#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x800
++#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb
++#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000
++#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc
++#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000
++#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd
++#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000
++#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe
++#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000
++#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf
++#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000
++#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10
++#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000
++#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11
++#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000
++#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12
++#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000
++#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13
++#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000
++#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14
++#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000
++#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15
++#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000
++#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16
++#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000
++#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17
++#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000
++#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18
++#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000
++#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19
++#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000
++#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a
++#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000
++#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b
++#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000
++#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c
++#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000
++#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d
++#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000
++#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e
++#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000
++#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f
++#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7
++#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0
++#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8
++#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3
++#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70
++#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4
++#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380
++#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7
++#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00
++#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa
++#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000
++#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10
++#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000
++#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18
++#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000
++#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c
++#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000
++#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d
++#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7
++#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0
++#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8
++#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3
++#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70
++#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4
++#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380
++#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7
++#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00
++#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa
++#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000
++#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10
++#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000
++#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18
++#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000
++#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c
++#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000
++#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000
++#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf
++#define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff
++#define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0
++#define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff
++#define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0
++#define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff
++#define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0
++#define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff
++#define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0
++#define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff
++#define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0
++#define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff
++#define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf
++#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf
++#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1
++#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0
++#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe
++#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1
++#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10
++#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4
++#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0
++#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5
++#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100
++#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8
++#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200
++#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9
++#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400
++#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa
++#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800
++#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb
++#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000
++#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe
++#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000
++#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf
++#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8
++#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1
++#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0
++#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2
++#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1
++#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4
++#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2
++#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8
++#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3
++#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10
++#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4
++#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20
++#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5
++#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40
++#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6
++#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700
++#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
++#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
++#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
++#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1
++#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0
++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2
++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1
++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4
++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
++#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1
++#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0
++#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2
++#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1
++#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4
++#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10
++#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1
++#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0
++#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2
++#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3
++#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00
++#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8
++#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000
++#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd
++#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000
++#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe
++#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000
++#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf
++#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000
++#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14
++#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000
++#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a
++#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7
++#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0
++#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8
++#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3
++#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10
++#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4
++#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40
++#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6
++#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80
++#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11
++#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000
++#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14
++#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000
++#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c
++#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000
++#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d
++#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7
++#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0
++#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8
++#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14
++#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000
++#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c
++#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7
++#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0
++#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8
++#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14
++#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000
++#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c
++#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff
++#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0
++#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1
++#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
++#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1
++#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0
++#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1
++#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0
++#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6
++#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1
++#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1
++#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0
++#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe
++#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1
++#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000
++#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15
++#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff
++#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0
++#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400
++#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa
++#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff
++#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0
++#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
++#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1
++#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4
++#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
++#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8
++#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3
++#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10
++#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4
++#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20
++#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5
++#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40
++#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6
++#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80
++#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7
++#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100
++#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8
++#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200
++#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9
++#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400
++#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa
++#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800
++#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb
++#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
++#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
++#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000
++#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12
++#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000
++#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14
++#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000
++#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
++#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000
++#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16
++#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000
++#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17
++#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000
++#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18
++#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000
++#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19
++#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
++#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
++#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
++#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
++#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
++#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6
++#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1
++#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0
++#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6
++#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1
++#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1
++#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0
++#define BIF_RESET_CNTL__RST_DONE_MASK 0x2
++#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1
++#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4
++#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
++#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8
++#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3
++#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100
++#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8
++#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
++#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
++#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
++#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
++#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
++#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
++#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
++#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
++#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
++#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
++
++#endif /* BIF_4_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-IMC-to-fetch-BIOS-code.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-IMC-to-fetch-BIOS-code.patch
new file mode 100644
index 00000000..3d806215
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-IMC-to-fetch-BIOS-code.patch
@@ -0,0 +1,415 @@
+The patch essentially adds support for two functions:
+amd_imc_enter_scratch_ram() and amd_imc_exit_scratch_ram(). These
+functions instruct IMC to stop and start fetching code from BIOS
+ROM respectively. These functions are needed where IMC is trying
+to fetch code on a shared bus when some other transaction is already
+occuring. To prevent IMC to fetch incorrect data from ROM while it
+is still being updated, we instruct IMC to temporarily stop fetching
+code from BIOS, and then start fetching again when it is safe to do
+so.
+
+upstream status: None
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com>
+diff -Naur a/drivers/staging/amd_imc/amd_imc.c b/drivers/staging/amd_imc/amd_imc.c
+--- a/drivers/staging/amd_imc/amd_imc.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/staging/amd_imc/amd_imc.c	2014-11-17 15:29:04.300072303 +0530
+@@ -0,0 +1,286 @@
++/*****************************************************************************
++*
++* Copyright (c) 2014, Advanced Micro Devices, Inc.
++* All rights reserved.
++*
++* Redistribution and use in source and binary forms, with or without
++* modification, are permitted provided that the following conditions are met:
++*     * Redistributions of source code must retain the above copyright
++*       notice, this list of conditions and the following disclaimer.
++*     * Redistributions in binary form must reproduce the above copyright
++*       notice, this list of conditions and the following disclaimer in the
++*       documentation and/or other materials provided with the distribution.
++*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
++*       its contributors may be used to endorse or promote products derived
++*       from this software without specific prior written permission.
++*
++* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
++* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++*
++*
++***************************************************************************/
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/amd_imc.h>
++
++static int imc_enabled;
++static u16 imc_port_addr;
++static u8 msg_reg_base_hi;
++static u8 msg_reg_base_lo;
++static u16 msg_reg_base;
++
++static struct pci_dev *amd_imc_pci;
++static struct platform_device *amd_imc_platform_device;
++
++static DEFINE_PCI_DEVICE_TABLE(amd_lpc_pci_tbl) = {
++	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE, PCI_ANY_ID,
++	 PCI_ANY_ID,},
++	{}
++};
++
++void amd_imc_enter_scratch_ram(void)
++{
++	u8 byte;
++
++	if (!imc_enabled)
++		return;
++
++	/* Instruct IMC to enter scratch RAM */
++	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	outb(0, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
++
++	outb(AMD_MSG_REG1, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	outb(AMD_IMC_ENTER_SCRATCH_RAM, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
++
++	outb(AMD_MSG_SYS_TO_IMC, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	outb(AMD_IMC_ROM_OWNERSHIP_SEM, msg_reg_base +
++	     AMD_MSG_DATA_REG_OFFSET);
++
++	/* As per the spec, the firmware may take up to 50ms */
++	msleep(50);
++
++	/* read message registger 0 to confirm function completion */
++	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	byte = inb(msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
++
++	if (byte == AMD_IMC_FUNC_NOT_SUPP)
++		pr_info("amd_imc: %s not supported\n", __func__);
++	else if (byte == AMD_IMC_FUNC_COMPLETED)
++		pr_info("amd_imc: %s completed\n", __func__);
++}
++EXPORT_SYMBOL_GPL(amd_imc_enter_scratch_ram);
++
++void amd_imc_exit_scratch_ram(void)
++{
++	u8 byte;
++
++	if (!imc_enabled)
++		return;
++
++	/* Instruct IMC to exit scratch RAM */
++	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	outb(0, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
++
++	outb(AMD_MSG_REG1, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	outb(AMD_IMC_ENTER_SCRATCH_RAM, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
++
++	outb(AMD_MSG_SYS_TO_IMC, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	outb(AMD_IMC_ROM_OWNERSHIP_SEM, msg_reg_base +
++	     AMD_MSG_DATA_REG_OFFSET);
++
++	/* As per the spec, the firmware may take up to 50ms */
++	msleep(50);
++
++	/* read message registger 0 to confirm function completion */
++	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
++	byte = inb(msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
++
++	if (byte == AMD_IMC_FUNC_NOT_SUPP)
++		pr_info("amd_imc: %s not supported\n", __func__);
++	else if (byte == AMD_IMC_FUNC_COMPLETED)
++		pr_info("amd_imc: %s completed\n", __func__);
++}
++EXPORT_SYMBOL_GPL(amd_imc_exit_scratch_ram);
++
++/*
++* The PCI Device ID table below is used to identify the platform
++* the driver is supposed to work for. Since this is a platform
++* driver, we need a way for us to be able to find the correct
++* platform when the driver gets loaded, otherwise we should
++* bail out.
++*/
++static DEFINE_PCI_DEVICE_TABLE(amd_imc_pci_tbl) = {
++	{ PCI_VENDOR_ID_AMD, 0x790B, PCI_ANY_ID,
++	  PCI_ANY_ID, },
++	{ 0, },
++};
++
++static int amd_imc_init(struct platform_device *pdev)
++{
++	struct pci_dev *dev = NULL;
++	static u32 imc_strap_status_phys;
++	void __iomem *imcstrapstatus;
++	u32 val;
++
++	/* Match the PCI device */
++	for_each_pci_dev(dev) {
++		if (pci_match_id(amd_imc_pci_tbl, dev) != NULL) {
++			amd_imc_pci = dev;
++			break;
++		}
++	}
++
++	if (!amd_imc_pci)
++		return -ENODEV;
++
++
++	/* ACPI MMIO Base Address */
++	val = AMD_GPIO_ACPIMMIO_BASE;
++
++	/* IMCStrapStatus is located at ACPI MMIO Base Address + 0xE80 */
++	if (!request_mem_region_exclusive(val + AMD_IMC_STRAP_STATUS_OFFSET,
++	    AMD_IMC_STRAP_STATUS_SIZE, "IMC Strap Status")) {
++		pr_err("amd_imc: MMIO address 0x%04x already in use\n",
++			val + AMD_IMC_STRAP_STATUS_OFFSET);
++		goto exit;
++	}
++
++	imc_strap_status_phys = val + AMD_IMC_STRAP_STATUS_OFFSET;
++
++	imcstrapstatus = ioremap(imc_strap_status_phys,
++				 AMD_IMC_STRAP_STATUS_SIZE);
++	if (!imcstrapstatus) {
++		pr_err("amd_imc: failed to get IMC Strap Status address\n");
++		goto unreg_imc_region;
++	}
++
++	/* Check if IMC is enabled */
++	val = ioread32(imcstrapstatus);
++	if ((val & AMD_IMC_ENABLED) == AMD_IMC_ENABLED) {
++		struct pci_dev *pdev = NULL;
++
++		pr_info("amd_imc: IMC is enabled\n");
++		imc_enabled = 1;
++
++		/*
++		 * In case IMC is enabled, we need to find the IMC port address
++		 * which will be used to send messages to the IMC. The IMC port
++		 * address is stored in bits 1:15 of PCI device 20, function 3,
++		 * offset 0xA4. PCI device 20, function 3 is actually the LPC
++		 * ISA bridge.
++		 */
++		for_each_pci_dev(pdev) {
++			if (pci_match_id(amd_lpc_pci_tbl, pdev) != NULL)
++				break;
++		}
++
++		/* Match found. Get the IMC port address */
++		if (pdev) {
++			pci_read_config_word(pdev, AMD_PCI_IMC_PORT_ADDR_REG,
++					     &imc_port_addr);
++
++			/* The actual IMC port address has bit 0 masked out */
++			imc_port_addr &= ~AMD_IMC_PORT_ACTIVE;
++		}
++
++		/* Put device into configuration state */
++		outb(AMD_DEVICE_ENTER_CONFIG_STATE, imc_port_addr +
++		     AMD_IMC_INDEX_REG_OFFSET);
++
++		/* Select logical device number 9 */
++		outb(AMD_SET_LOGICAL_DEVICE, imc_port_addr +
++		     AMD_IMC_INDEX_REG_OFFSET);
++		outb(AMD_SET_DEVICE_9, imc_port_addr +
++		     AMD_IMC_DATA_REG_OFFSET);
++
++		/* read high byte of message register base address */
++		outb(AMD_MSG_REG_HIGH, imc_port_addr +
++		     AMD_IMC_INDEX_REG_OFFSET);
++		msg_reg_base_hi = inb(imc_port_addr + AMD_IMC_DATA_REG_OFFSET);
++
++		/* read low byte of message register base address */
++		outb(AMD_MSG_REG_LOW, imc_port_addr +
++		     AMD_IMC_INDEX_REG_OFFSET);
++		msg_reg_base_lo = inb(imc_port_addr + AMD_IMC_DATA_REG_OFFSET);
++
++		msg_reg_base = msg_reg_base_lo | (msg_reg_base_hi << 8);
++
++		/* Get device out of configuration state */
++		outb(AMD_DEVICE_EXIT_CONFIG_STATE, imc_port_addr +
++		     AMD_IMC_INDEX_REG_OFFSET);
++	} else {
++		pr_info("amd_imc: IMC is disabled\n");
++		imc_enabled = 0;
++	}
++
++	/* Release the region occupied by IMC Strap Status register */
++	iounmap(imcstrapstatus);
++	release_mem_region(imc_strap_status_phys, AMD_IMC_STRAP_STATUS_SIZE);
++
++	return 0;
++
++unreg_imc_region:
++	release_mem_region(imc_strap_status_phys, AMD_IMC_STRAP_STATUS_SIZE);
++exit:
++	return -ENODEV;
++}
++
++static struct platform_driver amd_imc_driver = {
++	.probe		= amd_imc_init,
++	.driver		= {
++		.owner	= THIS_MODULE,
++		.name	= IMC_MODULE_NAME,
++	},
++};
++
++static int __init amd_imc_init_module(void)
++{
++	int err;
++
++	pr_info("AMD IMC Driver v%s\n", IMC_VERSION);
++
++	err = platform_driver_register(&amd_imc_driver);
++	if (err)
++		return err;
++
++	amd_imc_platform_device = platform_device_register_simple(
++					IMC_MODULE_NAME, -1, NULL, 0);
++	if (IS_ERR(amd_imc_platform_device)) {
++		err = PTR_ERR(amd_imc_platform_device);
++		goto unreg_platform_driver;
++	}
++
++	return 0;
++
++unreg_platform_driver:
++	platform_driver_unregister(&amd_imc_driver);
++	return err;
++}
++
++static void __exit amd_imc_cleanup_module(void)
++{
++	platform_device_unregister(amd_imc_platform_device);
++	platform_driver_unregister(&amd_imc_driver);
++	pr_info("AMD IMC Module Unloaded\n");
++}
++
++module_init(amd_imc_init_module);
++module_exit(amd_imc_cleanup_module);
++
++MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
++MODULE_DESCRIPTION("AMD IMC driver");
++MODULE_LICENSE("Dual BSD/GPL");
+diff -Naur a/drivers/staging/amd_imc/Kconfig b/drivers/staging/amd_imc/Kconfig
+--- a/drivers/staging/amd_imc/Kconfig	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/staging/amd_imc/Kconfig	2014-11-17 15:26:04.496065060 +0530
+@@ -0,0 +1,9 @@
++config AMD_IMC
++	bool "AMD Intergrated Micro Controller support"
++	depends on PCI && X86_64
++	default y
++	---help---
++	  This driver supports AMD Intergrated Micro Controller.
++
++	  To compile this driver as a module, choose M here. The module
++	  will be called amd_imc.
+diff -Naur a/drivers/staging/amd_imc/Makefile b/drivers/staging/amd_imc/Makefile
+--- a/drivers/staging/amd_imc/Makefile	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/staging/amd_imc/Makefile	2014-11-17 15:26:04.496065060 +0530
+@@ -0,0 +1 @@
++obj-$(CONFIG_AMD_IMC) += amd_imc.o
+diff -Naur a/drivers/staging/Kconfig b/drivers/staging/Kconfig
+--- a/drivers/staging/Kconfig	2014-03-31 09:10:15.000000000 +0530
++++ b/drivers/staging/Kconfig	2014-11-17 15:26:04.496065060 +0530
+@@ -146,4 +146,8 @@
+ 
+ source "drivers/staging/dgap/Kconfig"
+ 
++source "drivers/staging/amd_imc/Kconfig"
++
++source "drivers/staging/amd_imc/Kconfig"
++
+ endif # STAGING
+diff -Naur a/drivers/staging/Makefile b/drivers/staging/Makefile
+--- a/drivers/staging/Makefile	2014-03-31 09:10:15.000000000 +0530
++++ b/drivers/staging/Makefile	2014-11-17 15:26:04.496065060 +0530
+@@ -65,3 +65,4 @@
+ obj-$(CONFIG_DGNC)			+= dgnc/
+ obj-$(CONFIG_DGAP)			+= dgap/
+ obj-$(CONFIG_MTD_SPINAND_MT29F)	+= mt29f_spinand/
++obj-$(CONFIG_AMD_IMC)		+= amd_imc/
+diff -Naur a/include/linux/amd_imc.h b/include/linux/amd_imc.h
+--- a/include/linux/amd_imc.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/linux/amd_imc.h	2014-11-17 15:27:54.132069476 +0530
+@@ -0,0 +1,69 @@
++#ifndef _AMD_IMC_H_
++#define _AMD_IMC_H_
++
++/* Module and version information */
++#define IMC_VERSION "0.1"
++#define IMC_MODULE_NAME "AMD IMC"
++#define IMC_DRIVER_NAME   IMC_MODULE_NAME ", v" IMC_VERSION
++
++#define DRV_NAME "amd_imc"
++
++/* IO port address for indirect access using the ACPI PM registers */
++#define AMD_IO_PM_INDEX_REG		0xCD6
++#define AMD_IO_PM_DATA_REG		0xCD7
++
++#define AMD_GPIO_ACPIMMIO_BASE		0xFED80000
++#define AMD_PM_ACPI_MMIO_BASE0		0x24
++#define AMD_PM_ACPI_MMIO_BASE1		0x25
++#define AMD_PM_ACPI_MMIO_BASE2		0x26
++#define AMD_PM_ACPI_MMIO_BASE3		0x27
++
++#define AMD_ACPI_MMIO_ADDR_MASK		~0x1FFF
++
++/* Offset of IMC Strap Status register in the ACPI MMIO region */
++#define AMD_IMC_STRAP_STATUS_OFFSET	0xE80
++ #define AMD_IMC_ENABLED		0x4
++#define AMD_IMC_STRAP_STATUS_SIZE	4
++
++#define PCI_DEVICE_ID_AMD_LPC_BRIDGE	0x790E
++ #define AMD_PCI_IMC_PORT_ADDR_REG	0xA4
++  #define AMD_IMC_PORT_ACTIVE		0x0001
++
++/* Device configuration state fields */
++#define AMD_DEVICE_ENTER_CONFIG_STATE	0x5A
++#define AMD_DEVICE_EXIT_CONFIG_STATE	0xA5
++
++/* Global configuration registers */
++#define AMD_SET_LOGICAL_DEVICE		0x07
++ #define AMD_SET_DEVICE_9		0x09
++#define AMD_MSG_REG_HIGH		0x60
++#define AMD_MSG_REG_LOW			0x61
++
++/* IMC index and data port offsets for indirect access */
++#define AMD_IMC_INDEX_REG_OFFSET	0x00
++#define AMD_IMC_DATA_REG_OFFSET		0x01
++
++/* Message register index and data port offsets for indirect access */
++#define AMD_MSG_INDEX_REG_OFFSET	0x00
++#define AMD_MSG_DATA_REG_OFFSET		0x01
++
++/* IMC message registers */
++#define AMD_MSG_SYS_TO_IMC		0x80
++ #define AMD_IMC_ROM_OWNERSHIP_SEM	0x96
++#define AMD_MSG_REG0			0x82
++ #define AMD_IMC_FUNC_NOT_SUPP		0x00
++ #define AMD_IMC_FUNC_COMPLETED		0xFA
++#define AMD_MSG_REG1			0x83
++ #define AMD_IMC_ENTER_SCRATCH_RAM	0xB4
++ #define AMD_IMC_EXIT_SCRATCH_RAM	0xB5
++
++/* Extern functions */
++#ifdef CONFIG_AMD_IMC
++extern void amd_imc_enter_scratch_ram(void);
++extern void amd_imc_exit_scratch_ram(void);
++#else
++void amd_imc_enter_scratch_ram(void) {}
++void amd_imc_exit_scratch_ram(void) {}
++#endif
++
++#endif /* _AMD_IMC_H_ */
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0002-yocto-amd-drm-amdgpu-add-CIK-pci-ids.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0002-yocto-amd-drm-amdgpu-add-CIK-pci-ids.patch
new file mode 100644
index 00000000..bd5f0ae4
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0002-yocto-amd-drm-amdgpu-add-CIK-pci-ids.patch
@@ -0,0 +1,13792 @@
+From 09bf24d838d40ee3962f7d0f36997817f43af4ce Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:15:36 -0400
+Subject: drm/amdgpu: add BIF 5.0 register headers
+
+These are register headers for the BIF (Bus InterFace) block on
+the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
+new file mode 100644
+index 0000000..92b6ba0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
+@@ -0,0 +1,1068 @@
++/*
++ * BIF_5_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_5_0_D_H
++#define BIF_5_0_D_H
++
++#define mmMM_INDEX                                                              0x0
++#define mmMM_INDEX_HI                                                           0x6
++#define mmMM_DATA                                                               0x1
++#define mmBIF_MM_INDACCESS_CNTL                                                 0x1500
++#define mmBIF_DOORBELL_APER_EN                                                  0x1501
++#define mmBUS_CNTL                                                              0x1508
++#define mmCONFIG_CNTL                                                           0x1509
++#define mmCONFIG_MEMSIZE                                                        0x150a
++#define mmCONFIG_RESERVED                                                       0x1502
++#define mmBIF_IOV_FUNC_IDENTIFIER                                               0x1503
++#define mmCONFIG_F0_BASE                                                        0x150b
++#define mmCONFIG_APER_SIZE                                                      0x150c
++#define mmCONFIG_REG_APER_SIZE                                                  0x150d
++#define mmBIF_SCRATCH0                                                          0x150e
++#define mmBIF_SCRATCH1                                                          0x150f
++#define mmBIF_RLC_INTR_CNTL                                                     0x1510
++#define mmBIF_BME_STATUS                                                        0x1511
++#define mmBIF_ATOMIC_ERR_LOG                                                    0x1512
++#define mmBX_RESET_EN                                                           0x1514
++#define mmMM_CFGREGS_CNTL                                                       0x1513
++#define mmHW_DEBUG                                                              0x1515
++#define mmMASTER_CREDIT_CNTL                                                    0x1516
++#define mmSLAVE_REQ_CREDIT_CNTL                                                 0x1517
++#define mmBX_RESET_CNTL                                                         0x1518
++#define mmINTERRUPT_CNTL                                                        0x151a
++#define mmINTERRUPT_CNTL2                                                       0x151b
++#define mmBIF_DEBUG_CNTL                                                        0x151c
++#define mmBIF_DEBUG_MUX                                                         0x151d
++#define mmBIF_DEBUG_OUT                                                         0x151e
++#define mmHDP_REG_COHERENCY_FLUSH_CNTL                                          0x1528
++#define mmHDP_MEM_COHERENCY_FLUSH_CNTL                                          0x1520
++#define mmCLKREQB_PAD_CNTL                                                      0x1521
++#define mmCLKREQB_PERF_COUNTER                                                  0x1522
++#define mmBIF_XDMA_LO                                                           0x14c0
++#define mmBIF_XDMA_HI                                                           0x14c1
++#define mmBIF_FEATURES_CONTROL_MISC                                             0x14c2
++#define mmBIF_DOORBELL_CNTL                                                     0x14c3
++#define mmBIF_SLVARB_MODE                                                       0x14c4
++#define mmBIF_CLK_CTRL                                                          0x14c5
++#define mmBIF_FB_EN                                                             0x1524
++#define mmBIF_BUSNUM_CNTL1                                                      0x1525
++#define mmBIF_BUSNUM_LIST0                                                      0x1526
++#define mmBIF_BUSNUM_LIST1                                                      0x1527
++#define mmBIF_BUSNUM_CNTL2                                                      0x152b
++#define mmBIF_BUSY_DELAY_CNTR                                                   0x1529
++#define mmBIF_PERFMON_CNTL                                                      0x152c
++#define mmBIF_PERFCOUNTER0_RESULT                                               0x152d
++#define mmBIF_PERFCOUNTER1_RESULT                                               0x152e
++#define mmSLAVE_HANG_PROTECTION_CNTL                                            0x1536
++#define mmGPU_HDP_FLUSH_REQ                                                     0x1537
++#define mmGPU_HDP_FLUSH_DONE                                                    0x1538
++#define mmSLAVE_HANG_ERROR                                                      0x153b
++#define mmCAPTURE_HOST_BUSNUM                                                   0x153c
++#define mmHOST_BUSNUM                                                           0x153d
++#define mmPEER_REG_RANGE0                                                       0x153e
++#define mmPEER_REG_RANGE1                                                       0x153f
++#define mmPEER0_FB_OFFSET_HI                                                    0x14f3
++#define mmPEER0_FB_OFFSET_LO                                                    0x14f2
++#define mmPEER1_FB_OFFSET_HI                                                    0x14f1
++#define mmPEER1_FB_OFFSET_LO                                                    0x14f0
++#define mmPEER2_FB_OFFSET_HI                                                    0x14ef
++#define mmPEER2_FB_OFFSET_LO                                                    0x14ee
++#define mmPEER3_FB_OFFSET_HI                                                    0x14ed
++#define mmPEER3_FB_OFFSET_LO                                                    0x14ec
++#define mmDBG_SMB_BYPASS_SRBM_ACCESS                                            0x14eb
++#define mmBIF_MST_TRANS_PENDING                                                 0x14ea
++#define mmBIF_SLV_TRANS_PENDING                                                 0x14e9
++#define mmBIF_DEVFUNCNUM_LIST0                                                  0x14e8
++#define mmBIF_DEVFUNCNUM_LIST1                                                  0x14e7
++#define mmBACO_CNTL                                                             0x14e5
++#define mmBF_ANA_ISO_CNTL                                                       0x14c7
++#define mmMEM_TYPE_CNTL                                                         0x14e4
++#define mmBIF_BACO_DEBUG                                                        0x14df
++#define mmBIF_BACO_DEBUG_LATCH                                                  0x14dc
++#define mmBACO_CNTL_MISC                                                        0x14db
++#define mmSMU_BIF_VDDGFX_PWR_STATUS                                             0x14f8
++#define mmBIF_VDDGFX_GFX0_LOWER                                                 0x1428
++#define mmBIF_VDDGFX_GFX0_UPPER                                                 0x1429
++#define mmBIF_VDDGFX_GFX1_LOWER                                                 0x142a
++#define mmBIF_VDDGFX_GFX1_UPPER                                                 0x142b
++#define mmBIF_VDDGFX_GFX2_LOWER                                                 0x142c
++#define mmBIF_VDDGFX_GFX2_UPPER                                                 0x142d
++#define mmBIF_VDDGFX_GFX3_LOWER                                                 0x142e
++#define mmBIF_VDDGFX_GFX3_UPPER                                                 0x142f
++#define mmBIF_VDDGFX_GFX4_LOWER                                                 0x1430
++#define mmBIF_VDDGFX_GFX4_UPPER                                                 0x1431
++#define mmBIF_VDDGFX_GFX5_LOWER                                                 0x1432
++#define mmBIF_VDDGFX_GFX5_UPPER                                                 0x1433
++#define mmBIF_VDDGFX_RSV1_LOWER                                                 0x1434
++#define mmBIF_VDDGFX_RSV1_UPPER                                                 0x1435
++#define mmBIF_VDDGFX_RSV2_LOWER                                                 0x1436
++#define mmBIF_VDDGFX_RSV2_UPPER                                                 0x1437
++#define mmBIF_VDDGFX_RSV3_LOWER                                                 0x1438
++#define mmBIF_VDDGFX_RSV3_UPPER                                                 0x1439
++#define mmBIF_VDDGFX_RSV4_LOWER                                                 0x143a
++#define mmBIF_VDDGFX_RSV4_UPPER                                                 0x143b
++#define mmBIF_VDDGFX_FB_CMP                                                     0x143c
++#define mmBIF_SMU_INDEX                                                         0x143d
++#define mmBIF_SMU_DATA                                                          0x143e
++#define mmBIF_DOORBELL_GBLAPER1_LOWER                                           0x14fc
++#define mmBIF_DOORBELL_GBLAPER1_UPPER                                           0x14fd
++#define mmBIF_DOORBELL_GBLAPER2_LOWER                                           0x14fe
++#define mmBIF_DOORBELL_GBLAPER2_UPPER                                           0x14ff
++#define mmIMPCTL_RESET                                                          0x14f5
++#define mmGARLIC_FLUSH_CNTL                                                     0x1401
++#define mmGARLIC_FLUSH_ADDR_START_0                                             0x1402
++#define mmGARLIC_FLUSH_ADDR_START_1                                             0x1404
++#define mmGARLIC_FLUSH_ADDR_START_2                                             0x1406
++#define mmGARLIC_FLUSH_ADDR_START_3                                             0x1408
++#define mmGARLIC_FLUSH_ADDR_START_4                                             0x140a
++#define mmGARLIC_FLUSH_ADDR_START_5                                             0x140c
++#define mmGARLIC_FLUSH_ADDR_START_6                                             0x140e
++#define mmGARLIC_FLUSH_ADDR_START_7                                             0x1410
++#define mmGARLIC_FLUSH_ADDR_END_0                                               0x1403
++#define mmGARLIC_FLUSH_ADDR_END_1                                               0x1405
++#define mmGARLIC_FLUSH_ADDR_END_2                                               0x1407
++#define mmGARLIC_FLUSH_ADDR_END_3                                               0x1409
++#define mmGARLIC_FLUSH_ADDR_END_4                                               0x140b
++#define mmGARLIC_FLUSH_ADDR_END_5                                               0x140d
++#define mmGARLIC_FLUSH_ADDR_END_6                                               0x140f
++#define mmGARLIC_FLUSH_ADDR_END_7                                               0x1411
++#define mmGARLIC_FLUSH_REQ                                                      0x1412
++#define mmGPU_GARLIC_FLUSH_REQ                                                  0x1413
++#define mmGPU_GARLIC_FLUSH_DONE                                                 0x1414
++#define mmREMAP_HDP_MEM_FLUSH_CNTL                                              0x1426
++#define mmREMAP_HDP_REG_FLUSH_CNTL                                              0x1427
++#define mmBIOS_SCRATCH_0                                                        0x5c9
++#define mmBIOS_SCRATCH_1                                                        0x5ca
++#define mmBIOS_SCRATCH_2                                                        0x5cb
++#define mmBIOS_SCRATCH_3                                                        0x5cc
++#define mmBIOS_SCRATCH_4                                                        0x5cd
++#define mmBIOS_SCRATCH_5                                                        0x5ce
++#define mmBIOS_SCRATCH_6                                                        0x5cf
++#define mmBIOS_SCRATCH_7                                                        0x5d0
++#define mmBIOS_SCRATCH_8                                                        0x5d1
++#define mmBIOS_SCRATCH_9                                                        0x5d2
++#define mmBIOS_SCRATCH_10                                                       0x5d3
++#define mmBIOS_SCRATCH_11                                                       0x5d4
++#define mmBIOS_SCRATCH_12                                                       0x5d5
++#define mmBIOS_SCRATCH_13                                                       0x5d6
++#define mmBIOS_SCRATCH_14                                                       0x5d7
++#define mmBIOS_SCRATCH_15                                                       0x5d8
++#define mmBIF_RB_CNTL                                                           0x1530
++#define mmBIF_RB_BASE                                                           0x1531
++#define mmBIF_RB_RPTR                                                           0x1532
++#define mmBIF_RB_WPTR                                                           0x1533
++#define mmBIF_RB_WPTR_ADDR_HI                                                   0x1534
++#define mmBIF_RB_WPTR_ADDR_LO                                                   0x1535
++#define mmMAILBOX_INDEX                                                         0x14c6
++#define mmMAILBOX_MSGBUF_TRN_DW0                                                0x14c8
++#define mmMAILBOX_MSGBUF_TRN_DW1                                                0x14c9
++#define mmMAILBOX_MSGBUF_TRN_DW2                                                0x14ca
++#define mmMAILBOX_MSGBUF_TRN_DW3                                                0x14cb
++#define mmMAILBOX_MSGBUF_RCV_DW0                                                0x14cc
++#define mmMAILBOX_MSGBUF_RCV_DW1                                                0x14cd
++#define mmMAILBOX_MSGBUF_RCV_DW2                                                0x14ce
++#define mmMAILBOX_MSGBUF_RCV_DW3                                                0x14cf
++#define mmMAILBOX_CONTROL                                                       0x14d0
++#define mmMAILBOX_INT_CNTL                                                      0x14d1
++#define mmBIF_VIRT_RESET_REQ                                                    0x14d2
++#define mmVM_INIT_STATUS                                                        0x14d3
++#define mmBIF_GPUIOV_RESET_NOTIFICATION                                         0x14d5
++#define mmBIF_GPUIOV_VM_INIT_STATUS                                             0x14d6
++#define mmBIF_GPUIOV_FB_TOTAL_FB_INFO                                           0x14d8
++#define mmBIF_GPUIOV_GPU_IDLE_LATENCY                                           0x141c
++#define mmBIF_GPUIOV_MMIO_MAP_RANGE0                                            0x141d
++#define mmBIF_GPUIOV_MMIO_MAP_RANGE1                                            0x141e
++#define mmBIF_GPUIOV_MMIO_MAP_RANGE2                                            0x141f
++#define mmBIF_GPUIOV_MMIO_MAP_RANGE3                                            0x1420
++#define mmBIF_GPUIOV_MMIO_MAP_RANGE4                                            0x1421
++#define mmBIF_GPUIOV_MMIO_MAP_RANGE5                                            0x1422
++#define mmBIF_GPU_IDLE_LATENCY                                                  0x1415
++#define mmBIF_MMIO_MAP_RANGE0                                                   0x1416
++#define mmBIF_MMIO_MAP_RANGE1                                                   0x1417
++#define mmBIF_MMIO_MAP_RANGE2                                                   0x1418
++#define mmBIF_MMIO_MAP_RANGE3                                                   0x1419
++#define mmBIF_MMIO_MAP_RANGE4                                                   0x141a
++#define mmBIF_MMIO_MAP_RANGE5                                                   0x141b
++#define mmVENDOR_ID                                                             0x0
++#define mmDEVICE_ID                                                             0x0
++#define mmCOMMAND                                                               0x1
++#define mmSTATUS                                                                0x1
++#define mmREVISION_ID                                                           0x2
++#define mmPROG_INTERFACE                                                        0x2
++#define mmSUB_CLASS                                                             0x2
++#define mmBASE_CLASS                                                            0x2
++#define mmCACHE_LINE                                                            0x3
++#define mmLATENCY                                                               0x3
++#define mmHEADER                                                                0x3
++#define mmBIST                                                                  0x3
++#define mmBASE_ADDR_1                                                           0x4
++#define mmBASE_ADDR_2                                                           0x5
++#define mmBASE_ADDR_3                                                           0x6
++#define mmBASE_ADDR_4                                                           0x7
++#define mmBASE_ADDR_5                                                           0x8
++#define mmBASE_ADDR_6                                                           0x9
++#define mmROM_BASE_ADDR                                                         0xc
++#define mmCAP_PTR                                                               0xd
++#define mmINTERRUPT_LINE                                                        0xf
++#define mmINTERRUPT_PIN                                                         0xf
++#define mmADAPTER_ID                                                            0xb
++#define mmMIN_GRANT                                                             0xf
++#define mmMAX_LATENCY                                                           0xf
++#define mmVENDOR_CAP_LIST                                                       0x12
++#define mmADAPTER_ID_W                                                          0x13
++#define mmPMI_CAP_LIST                                                          0x14
++#define mmPMI_CAP                                                               0x14
++#define mmPMI_STATUS_CNTL                                                       0x15
++#define mmPCIE_CAP_LIST                                                         0x16
++#define mmPCIE_CAP                                                              0x16
++#define mmDEVICE_CAP                                                            0x17
++#define mmDEVICE_CNTL                                                           0x18
++#define mmDEVICE_STATUS                                                         0x18
++#define mmLINK_CAP                                                              0x19
++#define mmLINK_CNTL                                                             0x1a
++#define mmLINK_STATUS                                                           0x1a
++#define mmDEVICE_CAP2                                                           0x1f
++#define mmDEVICE_CNTL2                                                          0x20
++#define mmDEVICE_STATUS2                                                        0x20
++#define mmLINK_CAP2                                                             0x21
++#define mmLINK_CNTL2                                                            0x22
++#define mmLINK_STATUS2                                                          0x22
++#define mmMSI_CAP_LIST                                                          0x28
++#define mmMSI_MSG_CNTL                                                          0x28
++#define mmMSI_MSG_ADDR_LO                                                       0x29
++#define mmMSI_MSG_ADDR_HI                                                       0x2a
++#define mmMSI_MSG_DATA_64                                                       0x2b
++#define mmMSI_MSG_DATA                                                          0x2a
++#define mmMSI_MASK                                                              0x2b
++#define mmMSI_PENDING                                                           0x2c
++#define mmMSI_MASK_64                                                           0x2c
++#define mmMSI_PENDING_64                                                        0x2d
++#define mmMSIX_CAP_LIST                                                         0x30
++#define mmMSIX_MSG_CNTL                                                         0x30
++#define mmMSIX_TABLE                                                            0x31
++#define mmMSIX_PBA                                                              0x32
++#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                     0x40
++#define mmPCIE_VENDOR_SPECIFIC_HDR                                              0x41
++#define mmPCIE_VENDOR_SPECIFIC1                                                 0x42
++#define mmPCIE_VENDOR_SPECIFIC2                                                 0x43
++#define mmPCIE_VC_ENH_CAP_LIST                                                  0x44
++#define mmPCIE_PORT_VC_CAP_REG1                                                 0x45
++#define mmPCIE_PORT_VC_CAP_REG2                                                 0x46
++#define mmPCIE_PORT_VC_CNTL                                                     0x47
++#define mmPCIE_PORT_VC_STATUS                                                   0x47
++#define mmPCIE_VC0_RESOURCE_CAP                                                 0x48
++#define mmPCIE_VC0_RESOURCE_CNTL                                                0x49
++#define mmPCIE_VC0_RESOURCE_STATUS                                              0x4a
++#define mmPCIE_VC1_RESOURCE_CAP                                                 0x4b
++#define mmPCIE_VC1_RESOURCE_CNTL                                                0x4c
++#define mmPCIE_VC1_RESOURCE_STATUS                                              0x4d
++#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                      0x50
++#define mmPCIE_DEV_SERIAL_NUM_DW1                                               0x51
++#define mmPCIE_DEV_SERIAL_NUM_DW2                                               0x52
++#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST                                         0x54
++#define mmPCIE_UNCORR_ERR_STATUS                                                0x55
++#define mmPCIE_UNCORR_ERR_MASK                                                  0x56
++#define mmPCIE_UNCORR_ERR_SEVERITY                                              0x57
++#define mmPCIE_CORR_ERR_STATUS                                                  0x58
++#define mmPCIE_CORR_ERR_MASK                                                    0x59
++#define mmPCIE_ADV_ERR_CAP_CNTL                                                 0x5a
++#define mmPCIE_HDR_LOG0                                                         0x5b
++#define mmPCIE_HDR_LOG1                                                         0x5c
++#define mmPCIE_HDR_LOG2                                                         0x5d
++#define mmPCIE_HDR_LOG3                                                         0x5e
++#define mmPCIE_TLP_PREFIX_LOG0                                                  0x62
++#define mmPCIE_TLP_PREFIX_LOG1                                                  0x63
++#define mmPCIE_TLP_PREFIX_LOG2                                                  0x64
++#define mmPCIE_TLP_PREFIX_LOG3                                                  0x65
++#define mmPCIE_BAR_ENH_CAP_LIST                                                 0x80
++#define mmPCIE_BAR1_CAP                                                         0x81
++#define mmPCIE_BAR1_CNTL                                                        0x82
++#define mmPCIE_BAR2_CAP                                                         0x83
++#define mmPCIE_BAR2_CNTL                                                        0x84
++#define mmPCIE_BAR3_CAP                                                         0x85
++#define mmPCIE_BAR3_CNTL                                                        0x86
++#define mmPCIE_BAR4_CAP                                                         0x87
++#define mmPCIE_BAR4_CNTL                                                        0x88
++#define mmPCIE_BAR5_CAP                                                         0x89
++#define mmPCIE_BAR5_CNTL                                                        0x8a
++#define mmPCIE_BAR6_CAP                                                         0x8b
++#define mmPCIE_BAR6_CNTL                                                        0x8c
++#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST                                          0x90
++#define mmPCIE_PWR_BUDGET_DATA_SELECT                                           0x91
++#define mmPCIE_PWR_BUDGET_DATA                                                  0x92
++#define mmPCIE_PWR_BUDGET_CAP                                                   0x93
++#define mmPCIE_DPA_ENH_CAP_LIST                                                 0x94
++#define mmPCIE_DPA_CAP                                                          0x95
++#define mmPCIE_DPA_LATENCY_INDICATOR                                            0x96
++#define mmPCIE_DPA_STATUS                                                       0x97
++#define mmPCIE_DPA_CNTL                                                         0x97
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                         0x99
++#define mmPCIE_SECONDARY_ENH_CAP_LIST                                           0x9c
++#define mmPCIE_LINK_CNTL3                                                       0x9d
++#define mmPCIE_LANE_ERROR_STATUS                                                0x9e
++#define mmPCIE_LANE_0_EQUALIZATION_CNTL                                         0x9f
++#define mmPCIE_LANE_1_EQUALIZATION_CNTL                                         0x9f
++#define mmPCIE_LANE_2_EQUALIZATION_CNTL                                         0xa0
++#define mmPCIE_LANE_3_EQUALIZATION_CNTL                                         0xa0
++#define mmPCIE_LANE_4_EQUALIZATION_CNTL                                         0xa1
++#define mmPCIE_LANE_5_EQUALIZATION_CNTL                                         0xa1
++#define mmPCIE_LANE_6_EQUALIZATION_CNTL                                         0xa2
++#define mmPCIE_LANE_7_EQUALIZATION_CNTL                                         0xa2
++#define mmPCIE_LANE_8_EQUALIZATION_CNTL                                         0xa3
++#define mmPCIE_LANE_9_EQUALIZATION_CNTL                                         0xa3
++#define mmPCIE_LANE_10_EQUALIZATION_CNTL                                        0xa4
++#define mmPCIE_LANE_11_EQUALIZATION_CNTL                                        0xa4
++#define mmPCIE_LANE_12_EQUALIZATION_CNTL                                        0xa5
++#define mmPCIE_LANE_13_EQUALIZATION_CNTL                                        0xa5
++#define mmPCIE_LANE_14_EQUALIZATION_CNTL                                        0xa6
++#define mmPCIE_LANE_15_EQUALIZATION_CNTL                                        0xa6
++#define mmPCIE_ACS_ENH_CAP_LIST                                                 0xa8
++#define mmPCIE_ACS_CAP                                                          0xa9
++#define mmPCIE_ACS_CNTL                                                         0xa9
++#define mmPCIE_ATS_ENH_CAP_LIST                                                 0xac
++#define mmPCIE_ATS_CAP                                                          0xad
++#define mmPCIE_ATS_CNTL                                                         0xad
++#define mmPCIE_PAGE_REQ_ENH_CAP_LIST                                            0xb0
++#define mmPCIE_PAGE_REQ_CNTL                                                    0xb1
++#define mmPCIE_PAGE_REQ_STATUS                                                  0xb1
++#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                       0xb2
++#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC                                          0xb3
++#define mmPCIE_PASID_ENH_CAP_LIST                                               0xb4
++#define mmPCIE_PASID_CAP                                                        0xb5
++#define mmPCIE_PASID_CNTL                                                       0xb5
++#define mmPCIE_TPH_REQR_ENH_CAP_LIST                                            0xb8
++#define mmPCIE_TPH_REQR_CAP                                                     0xb9
++#define mmPCIE_TPH_REQR_CNTL                                                    0xba
++#define mmPCIE_MC_ENH_CAP_LIST                                                  0xbc
++#define mmPCIE_MC_CAP                                                           0xbd
++#define mmPCIE_MC_CNTL                                                          0xbd
++#define mmPCIE_MC_ADDR0                                                         0xbe
++#define mmPCIE_MC_ADDR1                                                         0xbf
++#define mmPCIE_MC_RCV0                                                          0xc0
++#define mmPCIE_MC_RCV1                                                          0xc1
++#define mmPCIE_MC_BLOCK_ALL0                                                    0xc2
++#define mmPCIE_MC_BLOCK_ALL1                                                    0xc3
++#define mmPCIE_MC_BLOCK_UNTRANSLATED_0                                          0xc4
++#define mmPCIE_MC_BLOCK_UNTRANSLATED_1                                          0xc5
++#define mmPCIE_LTR_ENH_CAP_LIST                                                 0xc8
++#define mmPCIE_LTR_CAP                                                          0xc9
++#define mmPCIE_ARI_ENH_CAP_LIST                                                 0xca
++#define mmPCIE_ARI_CAP                                                          0xcb
++#define mmPCIE_ARI_CNTL                                                         0xcb
++#define mmPCIE_SRIOV_ENH_CAP_LIST                                               0xcc
++#define mmPCIE_SRIOV_CAP                                                        0xcd
++#define mmPCIE_SRIOV_CONTROL                                                    0xce
++#define mmPCIE_SRIOV_STATUS                                                     0xce
++#define mmPCIE_SRIOV_INITIAL_VFS                                                0xcf
++#define mmPCIE_SRIOV_TOTAL_VFS                                                  0xcf
++#define mmPCIE_SRIOV_NUM_VFS                                                    0xd0
++#define mmPCIE_SRIOV_FUNC_DEP_LINK                                              0xd0
++#define mmPCIE_SRIOV_FIRST_VF_OFFSET                                            0xd1
++#define mmPCIE_SRIOV_VF_STRIDE                                                  0xd1
++#define mmPCIE_SRIOV_VF_DEVICE_ID                                               0xd2
++#define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE                                        0xd3
++#define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE                                           0xd4
++#define mmPCIE_SRIOV_VF_BASE_ADDR_0                                             0xd5
++#define mmPCIE_SRIOV_VF_BASE_ADDR_1                                             0xd6
++#define mmPCIE_SRIOV_VF_BASE_ADDR_2                                             0xd7
++#define mmPCIE_SRIOV_VF_BASE_ADDR_3                                             0xd8
++#define mmPCIE_SRIOV_VF_BASE_ADDR_4                                             0xd9
++#define mmPCIE_SRIOV_VF_BASE_ADDR_5                                             0xda
++#define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                            0xdb
++#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                              0x100
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                       0x101
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                          0x102
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC                       0x103
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS                            0x104
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                         0x105
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION                    0x106
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS                        0x107
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                               0x108
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                              0x109
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS                        0x10a
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                               0x10b
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                0x10c
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                0x10d
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                0x10e
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                0x10f
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                0x110
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                0x111
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                0x112
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                0x113
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                0x114
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                0x115
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                               0x116
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                               0x117
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                               0x118
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                               0x119
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                               0x11a
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                               0x11b
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT                          0x11c
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0                       0x11d
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1                       0x11e
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2                       0x11f
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3                       0x120
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4                       0x121
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5                       0x122
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0                                 0x124
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1                                 0x125
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2                                 0x126
++#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3                                 0x127
++#define mmPCIE_INDEX                                                            0xe
++#define mmPCIE_DATA                                                             0xf
++#define mmPCIE_INDEX_2                                                          0xc
++#define mmPCIE_DATA_2                                                           0xd
++#define ixPCIE_HOLD_TRAINING_A                                                  0x1500820
++#define ixLNCNT_CONTROL                                                         0x1508030
++#define ixCFG_LNC_WINDOW                                                        0x1508031
++#define ixLNCNT_QUAN_THRD                                                       0x1508032
++#define ixLNCNT_WEIGHT                                                          0x1508033
++#define ixLNC_TOTAL_WACC                                                        0x1508034
++#define ixLNC_BW_WACC                                                           0x1508035
++#define ixLNC_CMN_WACC                                                          0x1508036
++#define mmPCIE_EFUSE                                                            0xfc0
++#define mmPCIE_EFUSE2                                                           0xfc1
++#define mmPCIE_EFUSE3                                                           0xfc2
++#define mmPCIE_EFUSE4                                                           0xfc3
++#define mmPCIE_EFUSE5                                                           0xfc4
++#define mmPCIE_EFUSE6                                                           0xfc5
++#define mmPCIE_EFUSE7                                                           0xfc6
++#define ixPCIE_WRAP_SCRATCH1                                                    0x1308001
++#define ixPCIE_WRAP_SCRATCH2                                                    0x1308002
++#define ixPCIE_WRAP_REG_TARG_MISC                                               0x1308005
++#define ixPCIE_WRAP_DTM_MISC                                                    0x1308006
++#define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN                                       0x1308007
++#define ixPCIE_WRAP_MISC                                                        0x1308008
++#define ixPCIE_WRAP_PIF_MISC                                                    0x1308009
++#define ixPCIE_RXDET_OVERRIDE                                                   0x130800a
++#define ixREG_ADAPT_pciecore0_CONTROL                                           0x1308090
++#define ixREG_ADAPT_pwregt_CONTROL                                              0x1308096
++#define ixREG_ADAPT_pwregr_CONTROL                                              0x1308097
++#define ixREG_ADAPT_pif0_CONTROL                                                0x1308098
++#define ixPCIE_RESERVED                                                         0x1400000
++#define ixPCIE_SCRATCH                                                          0x1400001
++#define ixPCIE_HW_DEBUG                                                         0x1400002
++#define ixPCIE_RX_NUM_NAK                                                       0x140000e
++#define ixPCIE_RX_NUM_NAK_GENERATED                                             0x140000f
++#define ixPCIE_CNTL                                                             0x1400010
++#define ixPCIE_CONFIG_CNTL                                                      0x1400011
++#define ixPCIE_DEBUG_CNTL                                                       0x1400012
++#define ixPCIE_INT_CNTL                                                         0x140001a
++#define ixPCIE_INT_STATUS                                                       0x140001b
++#define ixPCIE_CNTL2                                                            0x140001c
++#define ixPCIE_RX_CNTL2                                                         0x140001d
++#define ixPCIE_TX_F0_ATTR_CNTL                                                  0x140001e
++#define ixPCIE_TX_F1_F2_ATTR_CNTL                                               0x140001f
++#define ixPCIE_CI_CNTL                                                          0x1400020
++#define ixPCIE_BUS_CNTL                                                         0x1400021
++#define ixPCIE_LC_STATE6                                                        0x1400022
++#define ixPCIE_LC_STATE7                                                        0x1400023
++#define ixPCIE_LC_STATE8                                                        0x1400024
++#define ixPCIE_LC_STATE9                                                        0x1400025
++#define ixPCIE_LC_STATE10                                                       0x1400026
++#define ixPCIE_LC_STATE11                                                       0x1400027
++#define ixPCIE_LC_STATUS1                                                       0x1400028
++#define ixPCIE_LC_STATUS2                                                       0x1400029
++#define ixPCIE_WPR_CNTL                                                         0x1400030
++#define ixPCIE_RX_LAST_TLP0                                                     0x1400031
++#define ixPCIE_RX_LAST_TLP1                                                     0x1400032
++#define ixPCIE_RX_LAST_TLP2                                                     0x1400033
++#define ixPCIE_RX_LAST_TLP3                                                     0x1400034
++#define ixPCIE_TX_LAST_TLP0                                                     0x1400035
++#define ixPCIE_TX_LAST_TLP1                                                     0x1400036
++#define ixPCIE_TX_LAST_TLP2                                                     0x1400037
++#define ixPCIE_TX_LAST_TLP3                                                     0x1400038
++#define ixPCIE_I2C_REG_ADDR_EXPAND                                              0x140003a
++#define ixPCIE_I2C_REG_DATA                                                     0x140003b
++#define ixPCIE_CFG_CNTL                                                         0x140003c
++#define ixPCIE_LC_PM_CNTL                                                       0x140003d
++#define ixPCIE_P_CNTL                                                           0x1400040
++#define ixPCIE_P_BUF_STATUS                                                     0x1400041
++#define ixPCIE_P_DECODER_STATUS                                                 0x1400042
++#define ixPCIE_P_MISC_STATUS                                                    0x1400043
++#define ixPCIE_P_RCV_L0S_FTS_DET                                                0x1400050
++#define ixPCIE_OBFF_CNTL                                                        0x1400061
++#define ixPCIE_TX_LTR_CNTL                                                      0x1400060
++#define ixPCIE_IDLE_STATUS                                                      0x1400062
++#define ixPCIE_PERF_COUNT_CNTL                                                  0x1400080
++#define ixPCIE_PERF_CNTL_TXCLK                                                  0x1400081
++#define ixPCIE_PERF_COUNT0_TXCLK                                                0x1400082
++#define ixPCIE_PERF_COUNT1_TXCLK                                                0x1400083
++#define ixPCIE_PERF_CNTL_MST_R_CLK                                              0x1400084
++#define ixPCIE_PERF_COUNT0_MST_R_CLK                                            0x1400085
++#define ixPCIE_PERF_COUNT1_MST_R_CLK                                            0x1400086
++#define ixPCIE_PERF_CNTL_MST_C_CLK                                              0x1400087
++#define ixPCIE_PERF_COUNT0_MST_C_CLK                                            0x1400088
++#define ixPCIE_PERF_COUNT1_MST_C_CLK                                            0x1400089
++#define ixPCIE_PERF_CNTL_SLV_R_CLK                                              0x140008a
++#define ixPCIE_PERF_COUNT0_SLV_R_CLK                                            0x140008b
++#define ixPCIE_PERF_COUNT1_SLV_R_CLK                                            0x140008c
++#define ixPCIE_PERF_CNTL_SLV_S_C_CLK                                            0x140008d
++#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK                                          0x140008e
++#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK                                          0x140008f
++#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK                                           0x1400090
++#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK                                         0x1400091
++#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK                                         0x1400092
++#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL                                        0x1400093
++#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL                                        0x1400094
++#define ixPCIE_PERF_CNTL_TXCLK2                                                 0x1400095
++#define ixPCIE_PERF_COUNT0_TXCLK2                                               0x1400096
++#define ixPCIE_PERF_COUNT1_TXCLK2                                               0x1400097
++#define ixPCIE_STRAP_F0                                                         0x14000b0
++#define ixPCIE_STRAP_F1                                                         0x14000b1
++#define ixPCIE_STRAP_F2                                                         0x14000b2
++#define ixPCIE_STRAP_F3                                                         0x14000b3
++#define ixPCIE_STRAP_F4                                                         0x14000b4
++#define ixPCIE_STRAP_F5                                                         0x14000b5
++#define ixPCIE_STRAP_F6                                                         0x14000b6
++#define ixPCIE_STRAP_MSIX                                                       0x14000b7
++#define ixPCIE_STRAP_MISC                                                       0x14000c0
++#define ixPCIE_STRAP_MISC2                                                      0x14000c1
++#define ixPCIE_STRAP_PI                                                         0x14000c2
++#define ixPCIE_STRAP_I2C_BD                                                     0x14000c4
++#define ixPCIE_PRBS_CLR                                                         0x14000c8
++#define ixPCIE_PRBS_STATUS1                                                     0x14000c9
++#define ixPCIE_PRBS_STATUS2                                                     0x14000ca
++#define ixPCIE_PRBS_FREERUN                                                     0x14000cb
++#define ixPCIE_PRBS_MISC                                                        0x14000cc
++#define ixPCIE_PRBS_USER_PATTERN                                                0x14000cd
++#define ixPCIE_PRBS_LO_BITCNT                                                   0x14000ce
++#define ixPCIE_PRBS_HI_BITCNT                                                   0x14000cf
++#define ixPCIE_PRBS_ERRCNT_0                                                    0x14000d0
++#define ixPCIE_PRBS_ERRCNT_1                                                    0x14000d1
++#define ixPCIE_PRBS_ERRCNT_2                                                    0x14000d2
++#define ixPCIE_PRBS_ERRCNT_3                                                    0x14000d3
++#define ixPCIE_PRBS_ERRCNT_4                                                    0x14000d4
++#define ixPCIE_PRBS_ERRCNT_5                                                    0x14000d5
++#define ixPCIE_PRBS_ERRCNT_6                                                    0x14000d6
++#define ixPCIE_PRBS_ERRCNT_7                                                    0x14000d7
++#define ixPCIE_PRBS_ERRCNT_8                                                    0x14000d8
++#define ixPCIE_PRBS_ERRCNT_9                                                    0x14000d9
++#define ixPCIE_PRBS_ERRCNT_10                                                   0x14000da
++#define ixPCIE_PRBS_ERRCNT_11                                                   0x14000db
++#define ixPCIE_PRBS_ERRCNT_12                                                   0x14000dc
++#define ixPCIE_PRBS_ERRCNT_13                                                   0x14000dd
++#define ixPCIE_PRBS_ERRCNT_14                                                   0x14000de
++#define ixPCIE_PRBS_ERRCNT_15                                                   0x14000df
++#define ixPCIE_F0_DPA_CAP                                                       0x14000e0
++#define ixPCIE_F0_DPA_LATENCY_INDICATOR                                         0x14000e4
++#define ixPCIE_F0_DPA_CNTL                                                      0x14000e5
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                      0x14000e7
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                      0x14000e8
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                      0x14000e9
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                      0x14000ea
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                      0x14000eb
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                      0x14000ec
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                      0x14000ed
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                      0x14000ee
++#define mmSWRST_COMMAND_STATUS                                                  0x14a0
++#define mmSWRST_GENERAL_CONTROL                                                 0x14a1
++#define mmSWRST_COMMAND_0                                                       0x14a2
++#define mmSWRST_COMMAND_1                                                       0x14a3
++#define mmSWRST_CONTROL_0                                                       0x14a4
++#define mmSWRST_CONTROL_1                                                       0x14a5
++#define mmSWRST_CONTROL_2                                                       0x14a6
++#define mmSWRST_CONTROL_3                                                       0x14a7
++#define mmSWRST_CONTROL_4                                                       0x14a8
++#define mmSWRST_CONTROL_5                                                       0x14a9
++#define mmSWRST_CONTROL_6                                                       0x14aa
++#define mmSWRST_EP_COMMAND_0                                                    0x14ab
++#define mmSWRST_EP_CONTROL_0                                                    0x14ac
++#define mmCPM_CONTROL                                                           0x14b8
++#define mmGSKT_CONTROL                                                          0x14bf
++#define ixLM_CONTROL                                                            0x1400120
++#define ixLM_PCIETXMUX0                                                         0x1400121
++#define ixLM_PCIETXMUX1                                                         0x1400122
++#define ixLM_PCIETXMUX2                                                         0x1400123
++#define ixLM_PCIETXMUX3                                                         0x1400124
++#define ixLM_PCIERXMUX0                                                         0x1400125
++#define ixLM_PCIERXMUX1                                                         0x1400126
++#define ixLM_PCIERXMUX2                                                         0x1400127
++#define ixLM_PCIERXMUX3                                                         0x1400128
++#define ixLM_LANEENABLE                                                         0x1400129
++#define ixLM_PRBSCONTROL                                                        0x140012a
++#define ixLM_POWERCONTROL                                                       0x140012b
++#define ixLM_POWERCONTROL1                                                      0x140012c
++#define ixLM_POWERCONTROL2                                                      0x140012d
++#define ixLM_POWERCONTROL3                                                      0x140012e
++#define ixLM_POWERCONTROL4                                                      0x140012f
++#define ixPB0_GLB_CTRL_REG0                                                     0x1200004
++#define ixPB0_GLB_CTRL_REG1                                                     0x1200008
++#define ixPB0_GLB_CTRL_REG2                                                     0x120000c
++#define ixPB0_GLB_CTRL_REG3                                                     0x1200010
++#define ixPB0_GLB_CTRL_REG4                                                     0x1200014
++#define ixPB0_GLB_CTRL_REG5                                                     0x1200018
++#define ixPB0_GLB_SCI_STAT_OVRD_REG0                                            0x120001c
++#define ixPB0_GLB_SCI_STAT_OVRD_REG1                                            0x1200020
++#define ixPB0_GLB_SCI_STAT_OVRD_REG2                                            0x1200024
++#define ixPB0_GLB_SCI_STAT_OVRD_REG3                                            0x1200028
++#define ixPB0_GLB_SCI_STAT_OVRD_REG4                                            0x120002c
++#define ixPB0_GLB_OVRD_REG0                                                     0x1200030
++#define ixPB0_GLB_OVRD_REG1                                                     0x1200034
++#define ixPB0_GLB_OVRD_REG2                                                     0x1200038
++#define ixPB0_HW_DEBUG                                                          0x1202004
++#define ixPB0_STRAP_GLB_REG0                                                    0x1202020
++#define ixPB0_STRAP_TX_REG0                                                     0x1202024
++#define ixPB0_STRAP_RX_REG0                                                     0x1202028
++#define ixPB0_STRAP_RX_REG1                                                     0x120202c
++#define ixPB0_STRAP_PLL_REG0                                                    0x1202030
++#define ixPB0_STRAP_PIN_REG0                                                    0x1202034
++#define ixPB0_STRAP_GLB_REG1                                                    0x1202038
++#define ixPB0_STRAP_GLB_REG2                                                    0x120203c
++#define ixPB0_DFT_JIT_INJ_REG0                                                  0x1203000
++#define ixPB0_DFT_JIT_INJ_REG1                                                  0x1203004
++#define ixPB0_DFT_JIT_INJ_REG2                                                  0x1203008
++#define ixPB0_DFT_DEBUG_CTRL_REG0                                               0x120300c
++#define ixPB0_DFT_JIT_INJ_STAT_REG0                                             0x1203010
++#define ixPB0_PLL_RO_GLB_CTRL_REG0                                              0x1204000
++#define ixPB0_PLL_RO_GLB_OVRD_REG0                                              0x1204010
++#define ixPB0_PLL_RO0_CTRL_REG0                                                 0x1204440
++#define ixPB0_PLL_RO0_OVRD_REG0                                                 0x1204450
++#define ixPB0_PLL_RO0_OVRD_REG1                                                 0x1204454
++#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0                                        0x1204460
++#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0                                        0x1204464
++#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0                                        0x1204468
++#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0                                        0x120446c
++#define ixPB0_PLL_LC0_CTRL_REG0                                                 0x1204480
++#define ixPB0_PLL_LC0_OVRD_REG0                                                 0x1204490
++#define ixPB0_PLL_LC0_OVRD_REG1                                                 0x1204494
++#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0                                        0x1204500
++#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0                                        0x1204504
++#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0                                        0x1204508
++#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0                                        0x120450c
++#define ixPB0_RX_GLB_CTRL_REG0                                                  0x1206000
++#define ixPB0_RX_GLB_CTRL_REG1                                                  0x1206004
++#define ixPB0_RX_GLB_CTRL_REG2                                                  0x1206008
++#define ixPB0_RX_GLB_CTRL_REG3                                                  0x120600c
++#define ixPB0_RX_GLB_CTRL_REG4                                                  0x1206010
++#define ixPB0_RX_GLB_CTRL_REG5                                                  0x1206014
++#define ixPB0_RX_GLB_CTRL_REG6                                                  0x1206018
++#define ixPB0_RX_GLB_CTRL_REG7                                                  0x120601c
++#define ixPB0_RX_GLB_CTRL_REG8                                                  0x1206020
++#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0                                         0x1206028
++#define ixPB0_RX_GLB_OVRD_REG0                                                  0x1206030
++#define ixPB0_RX_GLB_OVRD_REG1                                                  0x1206034
++#define ixPB0_RX_LANE0_CTRL_REG0                                                0x1206440
++#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0                                       0x1206448
++#define ixPB0_RX_LANE1_CTRL_REG0                                                0x1206480
++#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0                                       0x1206488
++#define ixPB0_RX_LANE2_CTRL_REG0                                                0x1206500
++#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0                                       0x1206508
++#define ixPB0_RX_LANE3_CTRL_REG0                                                0x1206600
++#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0                                       0x1206608
++#define ixPB0_RX_LANE4_CTRL_REG0                                                0x1206800
++#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0                                       0x1206848
++#define ixPB0_RX_LANE5_CTRL_REG0                                                0x1206880
++#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0                                       0x1206888
++#define ixPB0_RX_LANE6_CTRL_REG0                                                0x1206900
++#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0                                       0x1206908
++#define ixPB0_RX_LANE7_CTRL_REG0                                                0x1206a00
++#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0                                       0x1206a08
++#define ixPB0_RX_LANE8_CTRL_REG0                                                0x1207440
++#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0                                       0x1207448
++#define ixPB0_RX_LANE9_CTRL_REG0                                                0x1207480
++#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0                                       0x1207488
++#define ixPB0_RX_LANE10_CTRL_REG0                                               0x1207500
++#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0                                      0x1207508
++#define ixPB0_RX_LANE11_CTRL_REG0                                               0x1207600
++#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0                                      0x1207608
++#define ixPB0_RX_LANE12_CTRL_REG0                                               0x1207840
++#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0                                      0x1207848
++#define ixPB0_RX_LANE13_CTRL_REG0                                               0x1207880
++#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0                                      0x1207888
++#define ixPB0_RX_LANE14_CTRL_REG0                                               0x1207900
++#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0                                      0x1207908
++#define ixPB0_RX_LANE15_CTRL_REG0                                               0x1207a00
++#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0                                      0x1207a08
++#define ixPB0_TX_GLB_CTRL_REG0                                                  0x1208000
++#define ixPB0_TX_GLB_LANE_SKEW_CTRL                                             0x1208004
++#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0                                         0x1208010
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0                                    0x1208014
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1                                    0x1208018
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2                                    0x120801c
++#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3                                    0x1208020
++#define ixPB0_TX_GLB_OVRD_REG0                                                  0x1208030
++#define ixPB0_TX_GLB_OVRD_REG1                                                  0x1208034
++#define ixPB0_TX_GLB_OVRD_REG2                                                  0x1208038
++#define ixPB0_TX_GLB_OVRD_REG3                                                  0x120803c
++#define ixPB0_TX_GLB_OVRD_REG4                                                  0x1208040
++#define ixPB0_TX_LANE0_CTRL_REG0                                                0x1208440
++#define ixPB0_TX_LANE0_OVRD_REG0                                                0x1208444
++#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0                                       0x1208448
++#define ixPB0_TX_LANE1_CTRL_REG0                                                0x1208480
++#define ixPB0_TX_LANE1_OVRD_REG0                                                0x1208484
++#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0                                       0x1208488
++#define ixPB0_TX_LANE2_CTRL_REG0                                                0x1208500
++#define ixPB0_TX_LANE2_OVRD_REG0                                                0x1208504
++#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0                                       0x1208508
++#define ixPB0_TX_LANE3_CTRL_REG0                                                0x1208600
++#define ixPB0_TX_LANE3_OVRD_REG0                                                0x1208604
++#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0                                       0x1208608
++#define ixPB0_TX_LANE4_CTRL_REG0                                                0x1208840
++#define ixPB0_TX_LANE4_OVRD_REG0                                                0x1208844
++#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0                                       0x1208848
++#define ixPB0_TX_LANE5_CTRL_REG0                                                0x1208880
++#define ixPB0_TX_LANE5_OVRD_REG0                                                0x1208884
++#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0                                       0x1208888
++#define ixPB0_TX_LANE6_CTRL_REG0                                                0x1208900
++#define ixPB0_TX_LANE6_OVRD_REG0                                                0x1208904
++#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0                                       0x1208908
++#define ixPB0_TX_LANE7_CTRL_REG0                                                0x1208a00
++#define ixPB0_TX_LANE7_OVRD_REG0                                                0x1208a04
++#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0                                       0x1208a08
++#define ixPB0_TX_LANE8_CTRL_REG0                                                0x1209440
++#define ixPB0_TX_LANE8_OVRD_REG0                                                0x1209444
++#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0                                       0x1209448
++#define ixPB0_TX_LANE9_CTRL_REG0                                                0x1209480
++#define ixPB0_TX_LANE9_OVRD_REG0                                                0x1209484
++#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0                                       0x1209488
++#define ixPB0_TX_LANE10_CTRL_REG0                                               0x1209500
++#define ixPB0_TX_LANE10_OVRD_REG0                                               0x1209504
++#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0                                      0x1209508
++#define ixPB0_TX_LANE11_CTRL_REG0                                               0x1209600
++#define ixPB0_TX_LANE11_OVRD_REG0                                               0x1209604
++#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0                                      0x1209608
++#define ixPB0_TX_LANE12_CTRL_REG0                                               0x1209840
++#define ixPB0_TX_LANE12_OVRD_REG0                                               0x1209844
++#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0                                      0x1209848
++#define ixPB0_TX_LANE13_CTRL_REG0                                               0x1209880
++#define ixPB0_TX_LANE13_OVRD_REG0                                               0x1209884
++#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0                                      0x1209888
++#define ixPB0_TX_LANE14_CTRL_REG0                                               0x1209900
++#define ixPB0_TX_LANE14_OVRD_REG0                                               0x1209904
++#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0                                      0x1209908
++#define ixPB0_TX_LANE15_CTRL_REG0                                               0x1209a00
++#define ixPB0_TX_LANE15_OVRD_REG0                                               0x1209a04
++#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0                                      0x1209a08
++#define ixPB1_GLB_CTRL_REG0                                                     0x2200004
++#define ixPB1_GLB_CTRL_REG1                                                     0x2200008
++#define ixPB1_GLB_CTRL_REG2                                                     0x220000c
++#define ixPB1_GLB_CTRL_REG3                                                     0x2200010
++#define ixPB1_GLB_CTRL_REG4                                                     0x2200014
++#define ixPB1_GLB_CTRL_REG5                                                     0x2200018
++#define ixPB1_GLB_SCI_STAT_OVRD_REG0                                            0x220001c
++#define ixPB1_GLB_SCI_STAT_OVRD_REG1                                            0x2200020
++#define ixPB1_GLB_SCI_STAT_OVRD_REG2                                            0x2200024
++#define ixPB1_GLB_SCI_STAT_OVRD_REG3                                            0x2200028
++#define ixPB1_GLB_SCI_STAT_OVRD_REG4                                            0x220002c
++#define ixPB1_GLB_OVRD_REG0                                                     0x2200030
++#define ixPB1_GLB_OVRD_REG1                                                     0x2200034
++#define ixPB1_GLB_OVRD_REG2                                                     0x2200038
++#define ixPB1_HW_DEBUG                                                          0x2202004
++#define ixPB1_STRAP_GLB_REG0                                                    0x2202020
++#define ixPB1_STRAP_TX_REG0                                                     0x2202024
++#define ixPB1_STRAP_RX_REG0                                                     0x2202028
++#define ixPB1_STRAP_RX_REG1                                                     0x220202c
++#define ixPB1_STRAP_PLL_REG0                                                    0x2202030
++#define ixPB1_STRAP_PIN_REG0                                                    0x2202034
++#define ixPB1_STRAP_GLB_REG1                                                    0x2202038
++#define ixPB1_STRAP_GLB_REG2                                                    0x220203c
++#define ixPB1_DFT_JIT_INJ_REG0                                                  0x2203000
++#define ixPB1_DFT_JIT_INJ_REG1                                                  0x2203004
++#define ixPB1_DFT_JIT_INJ_REG2                                                  0x2203008
++#define ixPB1_DFT_DEBUG_CTRL_REG0                                               0x220300c
++#define ixPB1_DFT_JIT_INJ_STAT_REG0                                             0x2203010
++#define ixPB1_PLL_RO_GLB_CTRL_REG0                                              0x2204000
++#define ixPB1_PLL_RO_GLB_OVRD_REG0                                              0x2204010
++#define ixPB1_PLL_RO0_CTRL_REG0                                                 0x2204440
++#define ixPB1_PLL_RO0_OVRD_REG0                                                 0x2204450
++#define ixPB1_PLL_RO0_OVRD_REG1                                                 0x2204454
++#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0                                        0x2204460
++#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0                                        0x2204464
++#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0                                        0x2204468
++#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0                                        0x220446c
++#define ixPB1_PLL_LC0_CTRL_REG0                                                 0x2204480
++#define ixPB1_PLL_LC0_OVRD_REG0                                                 0x2204490
++#define ixPB1_PLL_LC0_OVRD_REG1                                                 0x2204494
++#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0                                        0x2204500
++#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0                                        0x2204504
++#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0                                        0x2204508
++#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0                                        0x220450c
++#define ixPB1_RX_GLB_CTRL_REG0                                                  0x2206000
++#define ixPB1_RX_GLB_CTRL_REG1                                                  0x2206004
++#define ixPB1_RX_GLB_CTRL_REG2                                                  0x2206008
++#define ixPB1_RX_GLB_CTRL_REG3                                                  0x220600c
++#define ixPB1_RX_GLB_CTRL_REG4                                                  0x2206010
++#define ixPB1_RX_GLB_CTRL_REG5                                                  0x2206014
++#define ixPB1_RX_GLB_CTRL_REG6                                                  0x2206018
++#define ixPB1_RX_GLB_CTRL_REG7                                                  0x220601c
++#define ixPB1_RX_GLB_CTRL_REG8                                                  0x2206020
++#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0                                         0x2206028
++#define ixPB1_RX_GLB_OVRD_REG0                                                  0x2206030
++#define ixPB1_RX_GLB_OVRD_REG1                                                  0x2206034
++#define ixPB1_RX_LANE0_CTRL_REG0                                                0x2206440
++#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0                                       0x2206448
++#define ixPB1_RX_LANE1_CTRL_REG0                                                0x2206480
++#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0                                       0x2206488
++#define ixPB1_RX_LANE2_CTRL_REG0                                                0x2206500
++#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0                                       0x2206508
++#define ixPB1_RX_LANE3_CTRL_REG0                                                0x2206600
++#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0                                       0x2206608
++#define ixPB1_RX_LANE4_CTRL_REG0                                                0x2206800
++#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0                                       0x2206848
++#define ixPB1_RX_LANE5_CTRL_REG0                                                0x2206880
++#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0                                       0x2206888
++#define ixPB1_RX_LANE6_CTRL_REG0                                                0x2206900
++#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0                                       0x2206908
++#define ixPB1_RX_LANE7_CTRL_REG0                                                0x2206a00
++#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0                                       0x2206a08
++#define ixPB1_RX_LANE8_CTRL_REG0                                                0x2207440
++#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0                                       0x2207448
++#define ixPB1_RX_LANE9_CTRL_REG0                                                0x2207480
++#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0                                       0x2207488
++#define ixPB1_RX_LANE10_CTRL_REG0                                               0x2207500
++#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0                                      0x2207508
++#define ixPB1_RX_LANE11_CTRL_REG0                                               0x2207600
++#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0                                      0x2207608
++#define ixPB1_RX_LANE12_CTRL_REG0                                               0x2207840
++#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0                                      0x2207848
++#define ixPB1_RX_LANE13_CTRL_REG0                                               0x2207880
++#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0                                      0x2207888
++#define ixPB1_RX_LANE14_CTRL_REG0                                               0x2207900
++#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0                                      0x2207908
++#define ixPB1_RX_LANE15_CTRL_REG0                                               0x2207a00
++#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0                                      0x2207a08
++#define ixPB1_TX_GLB_CTRL_REG0                                                  0x2208000
++#define ixPB1_TX_GLB_LANE_SKEW_CTRL                                             0x2208004
++#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0                                         0x2208010
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0                                    0x2208014
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1                                    0x2208018
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2                                    0x220801c
++#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3                                    0x2208020
++#define ixPB1_TX_GLB_OVRD_REG0                                                  0x2208030
++#define ixPB1_TX_GLB_OVRD_REG1                                                  0x2208034
++#define ixPB1_TX_GLB_OVRD_REG2                                                  0x2208038
++#define ixPB1_TX_GLB_OVRD_REG3                                                  0x220803c
++#define ixPB1_TX_GLB_OVRD_REG4                                                  0x2208040
++#define ixPB1_TX_LANE0_CTRL_REG0                                                0x2208440
++#define ixPB1_TX_LANE0_OVRD_REG0                                                0x2208444
++#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0                                       0x2208448
++#define ixPB1_TX_LANE1_CTRL_REG0                                                0x2208480
++#define ixPB1_TX_LANE1_OVRD_REG0                                                0x2208484
++#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0                                       0x2208488
++#define ixPB1_TX_LANE2_CTRL_REG0                                                0x2208500
++#define ixPB1_TX_LANE2_OVRD_REG0                                                0x2208504
++#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0                                       0x2208508
++#define ixPB1_TX_LANE3_CTRL_REG0                                                0x2208600
++#define ixPB1_TX_LANE3_OVRD_REG0                                                0x2208604
++#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0                                       0x2208608
++#define ixPB1_TX_LANE4_CTRL_REG0                                                0x2208840
++#define ixPB1_TX_LANE4_OVRD_REG0                                                0x2208844
++#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0                                       0x2208848
++#define ixPB1_TX_LANE5_CTRL_REG0                                                0x2208880
++#define ixPB1_TX_LANE5_OVRD_REG0                                                0x2208884
++#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0                                       0x2208888
++#define ixPB1_TX_LANE6_CTRL_REG0                                                0x2208900
++#define ixPB1_TX_LANE6_OVRD_REG0                                                0x2208904
++#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0                                       0x2208908
++#define ixPB1_TX_LANE7_CTRL_REG0                                                0x2208a00
++#define ixPB1_TX_LANE7_OVRD_REG0                                                0x2208a04
++#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0                                       0x2208a08
++#define ixPB1_TX_LANE8_CTRL_REG0                                                0x2209440
++#define ixPB1_TX_LANE8_OVRD_REG0                                                0x2209444
++#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0                                       0x2209448
++#define ixPB1_TX_LANE9_CTRL_REG0                                                0x2209480
++#define ixPB1_TX_LANE9_OVRD_REG0                                                0x2209484
++#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0                                       0x2209488
++#define ixPB1_TX_LANE10_CTRL_REG0                                               0x2209500
++#define ixPB1_TX_LANE10_OVRD_REG0                                               0x2209504
++#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0                                      0x2209508
++#define ixPB1_TX_LANE11_CTRL_REG0                                               0x2209600
++#define ixPB1_TX_LANE11_OVRD_REG0                                               0x2209604
++#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0                                      0x2209608
++#define ixPB1_TX_LANE12_CTRL_REG0                                               0x2209840
++#define ixPB1_TX_LANE12_OVRD_REG0                                               0x2209844
++#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0                                      0x2209848
++#define ixPB1_TX_LANE13_CTRL_REG0                                               0x2209880
++#define ixPB1_TX_LANE13_OVRD_REG0                                               0x2209884
++#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0                                      0x2209888
++#define ixPB1_TX_LANE14_CTRL_REG0                                               0x2209900
++#define ixPB1_TX_LANE14_OVRD_REG0                                               0x2209904
++#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0                                      0x2209908
++#define ixPB1_TX_LANE15_CTRL_REG0                                               0x2209a00
++#define ixPB1_TX_LANE15_OVRD_REG0                                               0x2209a04
++#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0                                      0x2209a08
++#define ixPB0_PIF_SCRATCH                                                       0x1100001
++#define ixPB0_PIF_HW_DEBUG                                                      0x1100002
++#define ixPB0_PIF_STRAP_0                                                       0x1100003
++#define ixPB0_PIF_CTRL                                                          0x1100004
++#define ixPB0_PIF_TX_CTRL                                                       0x1100008
++#define ixPB0_PIF_TX_CTRL2                                                      0x1100009
++#define ixPB0_PIF_RX_CTRL                                                       0x110000a
++#define ixPB0_PIF_RX_CTRL2                                                      0x110000b
++#define ixPB0_PIF_GLB_OVRD                                                      0x110000c
++#define ixPB0_PIF_GLB_OVRD2                                                     0x110000d
++#define ixPB0_PIF_BIF_CMD_STATUS                                                0x1100010
++#define ixPB0_PIF_CMD_BUS_CTRL                                                  0x1100011
++#define ixPB0_PIF_CMD_BUS_GLB_OVRD                                              0x1100013
++#define ixPB0_PIF_LANE0_OVRD                                                    0x1100014
++#define ixPB0_PIF_LANE0_OVRD2                                                   0x1100015
++#define ixPB0_PIF_LANE1_OVRD                                                    0x1100016
++#define ixPB0_PIF_LANE1_OVRD2                                                   0x1100017
++#define ixPB0_PIF_LANE2_OVRD                                                    0x1100018
++#define ixPB0_PIF_LANE2_OVRD2                                                   0x1100019
++#define ixPB0_PIF_LANE3_OVRD                                                    0x110001a
++#define ixPB0_PIF_LANE3_OVRD2                                                   0x110001b
++#define ixPB0_PIF_LANE4_OVRD                                                    0x110001c
++#define ixPB0_PIF_LANE4_OVRD2                                                   0x110001d
++#define ixPB0_PIF_LANE5_OVRD                                                    0x110001e
++#define ixPB0_PIF_LANE5_OVRD2                                                   0x110001f
++#define ixPB0_PIF_LANE6_OVRD                                                    0x1100020
++#define ixPB0_PIF_LANE6_OVRD2                                                   0x1100021
++#define ixPB0_PIF_LANE7_OVRD                                                    0x1100022
++#define ixPB0_PIF_LANE7_OVRD2                                                   0x1100023
++#define ixPB1_PIF_SCRATCH                                                       0x2100001
++#define ixPB1_PIF_HW_DEBUG                                                      0x2100002
++#define ixPB1_PIF_STRAP_0                                                       0x2100003
++#define ixPB1_PIF_CTRL                                                          0x2100004
++#define ixPB1_PIF_TX_CTRL                                                       0x2100008
++#define ixPB1_PIF_TX_CTRL2                                                      0x2100009
++#define ixPB1_PIF_RX_CTRL                                                       0x210000a
++#define ixPB1_PIF_RX_CTRL2                                                      0x210000b
++#define ixPB1_PIF_GLB_OVRD                                                      0x210000c
++#define ixPB1_PIF_GLB_OVRD2                                                     0x210000d
++#define ixPB1_PIF_BIF_CMD_STATUS                                                0x2100010
++#define ixPB1_PIF_CMD_BUS_CTRL                                                  0x2100011
++#define ixPB1_PIF_CMD_BUS_GLB_OVRD                                              0x2100013
++#define ixPB1_PIF_LANE0_OVRD                                                    0x2100014
++#define ixPB1_PIF_LANE0_OVRD2                                                   0x2100015
++#define ixPB1_PIF_LANE1_OVRD                                                    0x2100016
++#define ixPB1_PIF_LANE1_OVRD2                                                   0x2100017
++#define ixPB1_PIF_LANE2_OVRD                                                    0x2100018
++#define ixPB1_PIF_LANE2_OVRD2                                                   0x2100019
++#define ixPB1_PIF_LANE3_OVRD                                                    0x210001a
++#define ixPB1_PIF_LANE3_OVRD2                                                   0x210001b
++#define ixPB1_PIF_LANE4_OVRD                                                    0x210001c
++#define ixPB1_PIF_LANE4_OVRD2                                                   0x210001d
++#define ixPB1_PIF_LANE5_OVRD                                                    0x210001e
++#define ixPB1_PIF_LANE5_OVRD2                                                   0x210001f
++#define ixPB1_PIF_LANE6_OVRD                                                    0x2100020
++#define ixPB1_PIF_LANE6_OVRD2                                                   0x2100021
++#define ixPB1_PIF_LANE7_OVRD                                                    0x2100022
++#define ixPB1_PIF_LANE7_OVRD2                                                   0x2100023
++#define ixPCIEP_RESERVED                                                        0x10010000
++#define ixPCIEP_SCRATCH                                                         0x10010001
++#define ixPCIEP_HW_DEBUG                                                        0x10010002
++#define ixPCIEP_PORT_CNTL                                                       0x10010010
++#define ixPCIE_TX_CNTL                                                          0x10010020
++#define ixPCIE_TX_REQUESTER_ID                                                  0x10010021
++#define ixPCIE_TX_VENDOR_SPECIFIC                                               0x10010022
++#define ixPCIE_TX_REQUEST_NUM_CNTL                                              0x10010023
++#define ixPCIE_TX_SEQ                                                           0x10010024
++#define ixPCIE_TX_REPLAY                                                        0x10010025
++#define ixPCIE_TX_ACK_LATENCY_LIMIT                                             0x10010026
++#define ixPCIE_TX_CREDITS_ADVT_P                                                0x10010030
++#define ixPCIE_TX_CREDITS_ADVT_NP                                               0x10010031
++#define ixPCIE_TX_CREDITS_ADVT_CPL                                              0x10010032
++#define ixPCIE_TX_CREDITS_INIT_P                                                0x10010033
++#define ixPCIE_TX_CREDITS_INIT_NP                                               0x10010034
++#define ixPCIE_TX_CREDITS_INIT_CPL                                              0x10010035
++#define ixPCIE_TX_CREDITS_STATUS                                                0x10010036
++#define ixPCIE_TX_CREDITS_FCU_THRESHOLD                                         0x10010037
++#define ixPCIE_P_PORT_LANE_STATUS                                               0x10010050
++#define ixPCIE_FC_P                                                             0x10010060
++#define ixPCIE_FC_NP                                                            0x10010061
++#define ixPCIE_FC_CPL                                                           0x10010062
++#define ixPCIE_ERR_CNTL                                                         0x1001006a
++#define ixPCIE_RX_CNTL                                                          0x10010070
++#define ixPCIE_RX_EXPECTED_SEQNUM                                               0x10010071
++#define ixPCIE_RX_VENDOR_SPECIFIC                                               0x10010072
++#define ixPCIE_RX_CNTL3                                                         0x10010074
++#define ixPCIE_RX_CREDITS_ALLOCATED_P                                           0x10010080
++#define ixPCIE_RX_CREDITS_ALLOCATED_NP                                          0x10010081
++#define ixPCIE_RX_CREDITS_ALLOCATED_CPL                                         0x10010082
++#define ixPCIEP_ERROR_INJECT_PHYSICAL                                           0x10010083
++#define ixPCIEP_ERROR_INJECT_TRANSACTION                                        0x10010084
++#define ixPCIEP_SRIOV_PRIV_CTRL                                                 0x10010085
++#define ixPCIE_LC_CNTL                                                          0x100100a0
++#define ixPCIE_LC_CNTL2                                                         0x100100b1
++#define ixPCIE_LC_CNTL3                                                         0x100100b5
++#define ixPCIE_LC_CNTL4                                                         0x100100b6
++#define ixPCIE_LC_CNTL5                                                         0x100100b7
++#define ixPCIE_LC_CNTL6                                                         0x100100bb
++#define ixPCIE_LC_BW_CHANGE_CNTL                                                0x100100b2
++#define ixPCIE_LC_TRAINING_CNTL                                                 0x100100a1
++#define ixPCIE_LC_LINK_WIDTH_CNTL                                               0x100100a2
++#define ixPCIE_LC_N_FTS_CNTL                                                    0x100100a3
++#define ixPCIE_LC_SPEED_CNTL                                                    0x100100a4
++#define ixPCIE_LC_CDR_CNTL                                                      0x100100b3
++#define ixPCIE_LC_LANE_CNTL                                                     0x100100b4
++#define ixPCIE_LC_FORCE_COEFF                                                   0x100100b8
++#define ixPCIE_LC_BEST_EQ_SETTINGS                                              0x100100b9
++#define ixPCIE_LC_FORCE_EQ_REQ_COEFF                                            0x100100ba
++#define ixPCIE_LC_STATE0                                                        0x100100a5
++#define ixPCIE_LC_STATE1                                                        0x100100a6
++#define ixPCIE_LC_STATE2                                                        0x100100a7
++#define ixPCIE_LC_STATE3                                                        0x100100a8
++#define ixPCIE_LC_STATE4                                                        0x100100a9
++#define ixPCIE_LC_STATE5                                                        0x100100aa
++#define ixPCIEP_STRAP_LC                                                        0x100100c0
++#define ixPCIEP_STRAP_MISC                                                      0x100100c1
++#define ixPCIEP_BCH_ECC_CNTL                                                    0x100100d0
++#define ixPCIEP_HPGI_PRIVATE                                                    0x100100d2
++#define ixPCIEP_HPGI                                                            0x100100da
++#define mmPCIEMSIX_VECT0_ADDR_LO                                                0x6000
++#define mmPCIEMSIX_VECT0_ADDR_HI                                                0x6001
++#define mmPCIEMSIX_VECT0_MSG_DATA                                               0x6002
++#define mmPCIEMSIX_VECT0_CONTROL                                                0x6003
++#define mmPCIEMSIX_VECT1_ADDR_LO                                                0x6004
++#define mmPCIEMSIX_VECT1_ADDR_HI                                                0x6005
++#define mmPCIEMSIX_VECT1_MSG_DATA                                               0x6006
++#define mmPCIEMSIX_VECT1_CONTROL                                                0x6007
++#define mmPCIEMSIX_VECT2_ADDR_LO                                                0x6008
++#define mmPCIEMSIX_VECT2_ADDR_HI                                                0x6009
++#define mmPCIEMSIX_VECT2_MSG_DATA                                               0x600a
++#define mmPCIEMSIX_VECT2_CONTROL                                                0x600b
++#define mmPCIEMSIX_VECT3_ADDR_LO                                                0x600c
++#define mmPCIEMSIX_VECT3_ADDR_HI                                                0x600d
++#define mmPCIEMSIX_VECT3_MSG_DATA                                               0x600e
++#define mmPCIEMSIX_VECT3_CONTROL                                                0x600f
++#define mmPCIEMSIX_PBA                                                          0x6200
++#define mmBIF_RFE_SNOOP_REG                                                     0x27
++#define mmBIF_RFE_WARMRST_CNTL                                                  0x1459
++#define mmBIF_RFE_SOFTRST_CNTL                                                  0x1441
++#define mmBIF_RFE_IMPRST_CNTL                                                   0x1458
++#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER                                        0x1442
++#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER                                        0x1443
++#define mmBIF_PWDN_COMMAND                                                      0x1444
++#define mmBIF_PWDN_STATUS                                                       0x1445
++#define mmBIF_RFE_MST_BU_CMDSTATUS                                              0x1446
++#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS                                  0x1447
++#define mmBIF_RFE_MST_SMBUS_CMDSTATUS                                           0x1448
++#define mmBIF_RFE_MST_BX_CMDSTATUS                                              0x1449
++#define mmBIF_RFE_MST_TMOUT_STATUS                                              0x144b
++#define mmBIF_RFE_MMCFG_CNTL                                                    0x144c
++#define mmBIF_CC_RFE_IMP_OVERRIDECNTL                                           0x1455
++#define mmBIF_IMPCTL_SMPLCNTL                                                   0x1450
++#define mmBIF_IMPCTL_RXCNTL                                                     0x1451
++#define mmBIF_IMPCTL_TXCNTL_pd                                                  0x1452
++#define mmBIF_IMPCTL_TXCNTL_pu                                                  0x1453
++#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD                              0x1454
++
++#endif /* BIF_5_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
+new file mode 100644
+index 0000000..46b75f4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
+@@ -0,0 +1,1198 @@
++/*
++ * BIF_5_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_5_0_ENUM_H
++#define BIF_5_0_ENUM_H
++
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
++	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
++	DBG_CLIENT_BLKID_bci0                            = 0xe,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
++	DBG_CLIENT_BLKID_cb100                           = 0x10,
++	DBG_CLIENT_BLKID_cb001                           = 0x11,
++	DBG_CLIENT_BLKID_mcd4                            = 0x12,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
++	DBG_CLIENT_BLKID_cb101                           = 0x14,
++	DBG_CLIENT_BLKID_sx10                            = 0x15,
++	DBG_CLIENT_BLKID_cb301                           = 0x16,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
++	DBG_CLIENT_BLKID_scf1                            = 0x1c,
++	DBG_CLIENT_BLKID_sx20                            = 0x1d,
++	DBG_CLIENT_BLKID_spim1                           = 0x1e,
++	DBG_CLIENT_BLKID_pa10                            = 0x1f,
++	DBG_CLIENT_BLKID_pa00                            = 0x20,
++	DBG_CLIENT_BLKID_gmcon                           = 0x21,
++	DBG_CLIENT_BLKID_mcb                             = 0x22,
++	DBG_CLIENT_BLKID_vgt0                            = 0x23,
++	DBG_CLIENT_BLKID_pc0                             = 0x24,
++	DBG_CLIENT_BLKID_bci2                            = 0x25,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
++	DBG_CLIENT_BLKID_spim3                           = 0x27,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
++	DBG_CLIENT_BLKID_cb000                           = 0x2e,
++	DBG_CLIENT_BLKID_spim0                           = 0x2f,
++	DBG_CLIENT_BLKID_mcc2                            = 0x30,
++	DBG_CLIENT_BLKID_ds0                             = 0x31,
++	DBG_CLIENT_BLKID_srbm                            = 0x32,
++	DBG_CLIENT_BLKID_ih                              = 0x33,
++	DBG_CLIENT_BLKID_sem                             = 0x34,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
++	DBG_CLIENT_BLKID_hdp                             = 0x37,
++	DBG_CLIENT_BLKID_acp_0                           = 0x38,
++	DBG_CLIENT_BLKID_acp_1                           = 0x39,
++	DBG_CLIENT_BLKID_cb200                           = 0x3a,
++	DBG_CLIENT_BLKID_scf3                            = 0x3b,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
++	DBG_CLIENT_BLKID_bci3                            = 0x41,
++	DBG_CLIENT_BLKID_mcd0                            = 0x42,
++	DBG_CLIENT_BLKID_pa11                            = 0x43,
++	DBG_CLIENT_BLKID_pa01                            = 0x44,
++	DBG_CLIENT_BLKID_cb201                           = 0x45,
++	DBG_CLIENT_BLKID_spim2                           = 0x46,
++	DBG_CLIENT_BLKID_vgt2                            = 0x47,
++	DBG_CLIENT_BLKID_pc2                             = 0x48,
++	DBG_CLIENT_BLKID_smu_0                           = 0x49,
++	DBG_CLIENT_BLKID_smu_1                           = 0x4a,
++	DBG_CLIENT_BLKID_smu_2                           = 0x4b,
++	DBG_CLIENT_BLKID_cb1                             = 0x4c,
++	DBG_CLIENT_BLKID_ia0                             = 0x4d,
++	DBG_CLIENT_BLKID_wd                              = 0x4e,
++	DBG_CLIENT_BLKID_ia1                             = 0x4f,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
++	DBG_CLIENT_BLKID_scf0                            = 0x51,
++	DBG_CLIENT_BLKID_vgt1                            = 0x52,
++	DBG_CLIENT_BLKID_pc1                             = 0x53,
++	DBG_CLIENT_BLKID_cb0                             = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
++	DBG_CLIENT_BLKID_vgt3                            = 0x7a,
++	DBG_CLIENT_BLKID_pc3                             = 0x7b,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
++	DBG_CLIENT_BLKID_cb300                           = 0x84,
++	DBG_CLIENT_BLKID_mcd1                            = 0x85,
++	DBG_CLIENT_BLKID_sx00                            = 0x86,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
++	DBG_CLIENT_BLKID_mcc3                            = 0x89,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
++	DBG_CLIENT_BLKID_gck                             = 0x8c,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8d,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
++	DBG_CLIENT_BLKID_rlc                             = 0x90,
++	DBG_CLIENT_BLKID_grbm                            = 0x91,
++	DBG_CLIENT_BLKID_sammsp                          = 0x92,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x93,
++	DBG_CLIENT_BLKID_dci_0                           = 0x94,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* BIF_5_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
+new file mode 100644
+index 0000000..adc71b0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
+@@ -0,0 +1,11494 @@
++/*
++ * BIF_5_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_5_0_SH_MASK_H
++#define BIF_5_0_SH_MASK_H
++
++#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
++#define MM_INDEX__MM_OFFSET__SHIFT 0x0
++#define MM_INDEX__MM_APER_MASK 0x80000000
++#define MM_INDEX__MM_APER__SHIFT 0x1f
++#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
++#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
++#define MM_DATA__MM_DATA_MASK 0xffffffff
++#define MM_DATA__MM_DATA__SHIFT 0x0
++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
++#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1
++#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
++#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
++#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
++#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
++#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
++#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
++#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
++#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
++#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
++#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
++#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
++#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
++#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
++#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
++#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
++#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
++#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
++#define BUS_CNTL__SET_MC_TC_MASK 0xe000
++#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
++#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
++#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
++#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
++#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
++#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
++#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
++#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
++#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
++#define CONFIG_CNTL__VGA_DIS_MASK 0x2
++#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
++#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
++#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
++#define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff
++#define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
++#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1
++#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
++#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000
++#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
++#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
++#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
++#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
++#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
++#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
++#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
++#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
++#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
++#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1
++#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0
++#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100
++#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8
++#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1
++#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
++#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000
++#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1
++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2
++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000
++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000
++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
++#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
++#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
++#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
++#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
++#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
++#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
++#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x100
++#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
++#define BX_RESET_EN__FLR_TIMER_SEL_MASK 0x600
++#define BX_RESET_EN__FLR_TIMER_SEL__SHIFT 0x9
++#define BX_RESET_EN__DB_APER_RESET_EN_MASK 0x8000
++#define BX_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
++#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x10000
++#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
++#define BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK 0x20000
++#define BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT 0x11
++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
++#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
++#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
++#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
++#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
++#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
++#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
++#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
++#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
++#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
++#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
++#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
++#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
++#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
++#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
++#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
++#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
++#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
++#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
++#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
++#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
++#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
++#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
++#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
++#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
++#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
++#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
++#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
++#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
++#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
++#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
++#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
++#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
++#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
++#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
++#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
++#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
++#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
++#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
++#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
++#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
++#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
++#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x2000
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
++#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000
++#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18
++#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffff
++#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0
++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
++#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
++#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
++#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x2000
++#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
++#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x8000
++#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
++#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x10000
++#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x10
++#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x20000
++#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
++#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x40000
++#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
++#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK 0x80000
++#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT 0x13
++#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK 0x100000
++#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT 0x14
++#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK 0x200000
++#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT 0x15
++#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK 0x400000
++#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT 0x16
++#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK 0x800000
++#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT 0x17
++#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK 0x1000000
++#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT 0x18
++#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
++#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10
++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x1000000
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x2000000
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x4000000
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x8000000
++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
++#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
++#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
++#define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x1
++#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0
++#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2
++#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1
++#define BIF_FB_EN__FB_READ_EN_MASK 0x1
++#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
++#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
++#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
++#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
++#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
++#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
++#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
++#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
++#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
++#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
++#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
++#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
++#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
++#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
++#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
++#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
++#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
++#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
++#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
++#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
++#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
++#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
++#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
++#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
++#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
++#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
++#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
++#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
++#define HOST_BUSNUM__HOST_ID_MASK 0xffff
++#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
++#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
++#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
++#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK 0x1
++#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT 0x0
++#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0xffffffff
++#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
++#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0xffffffff
++#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
++#define BACO_CNTL__BACO_EN_MASK 0x1
++#define BACO_CNTL__BACO_EN__SHIFT 0x0
++#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
++#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
++#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
++#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
++#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
++#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
++#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
++#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
++#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
++#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
++#define BACO_CNTL__BACO_MODE_MASK 0x40
++#define BACO_CNTL__BACO_MODE__SHIFT 0x6
++#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
++#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
++#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
++#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
++#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
++#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
++#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
++#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
++#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
++#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
++#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
++#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
++#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
++#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
++#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
++#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
++#define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK 0x40000
++#define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT 0x12
++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
++#define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK 0x10
++#define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT 0x4
++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1
++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
++#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc
++#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
++#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc
++#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
++#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
++#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
++#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000
++#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf
++#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
++#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
++#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000
++#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11
++#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000
++#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12
++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
++#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
++#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
++#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
++#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000
++#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc
++#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000
++#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
++#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000
++#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc
++#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000
++#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
++#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1
++#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e
++#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
++#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000
++#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define BIF_RB_BASE__ADDR_MASK 0xffffffff
++#define BIF_RB_BASE__ADDR__SHIFT 0x0
++#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc
++#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
++#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1
++#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
++#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc
++#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
++#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
++#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0xf
++#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
++#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffff
++#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
++#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x1
++#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
++#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2
++#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
++#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x100
++#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
++#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x200
++#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
++#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x1
++#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
++#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2
++#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
++#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK 0xffff
++#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT 0x0
++#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK 0x80000000
++#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT 0x1f
++#define VM_INIT_STATUS__VM_INIT_STATUS_MASK 0x1
++#define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
++#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff
++#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
++#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff
++#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
++#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0xffff
++#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x0
++#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000
++#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x10
++#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff
++#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff
++#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000
++#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10
++#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff
++#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000
++#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10
++#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff
++#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000
++#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10
++#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff
++#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000
++#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10
++#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff
++#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000
++#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10
++#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff
++#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0
++#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000
++#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10
++#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff
++#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff
++#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000
++#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10
++#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff
++#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000
++#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10
++#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff
++#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000
++#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10
++#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff
++#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000
++#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10
++#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff
++#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000
++#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10
++#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff
++#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0
++#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000
++#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10
++#define VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define DEVICE_ID__DEVICE_ID_MASK 0xffff
++#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
++#define COMMAND__IO_ACCESS_EN_MASK 0x1
++#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define COMMAND__BUS_MASTER_EN_MASK 0x4
++#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define COMMAND__AD_STEPPING_MASK 0x80
++#define COMMAND__AD_STEPPING__SHIFT 0x7
++#define COMMAND__SERR_EN_MASK 0x100
++#define COMMAND__SERR_EN__SHIFT 0x8
++#define COMMAND__FAST_B2B_EN_MASK 0x200
++#define COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define COMMAND__INT_DIS_MASK 0x400
++#define COMMAND__INT_DIS__SHIFT 0xa
++#define STATUS__INT_STATUS_MASK 0x8
++#define STATUS__INT_STATUS__SHIFT 0x3
++#define STATUS__CAP_LIST_MASK 0x10
++#define STATUS__CAP_LIST__SHIFT 0x4
++#define STATUS__PCI_66_EN_MASK 0x20
++#define STATUS__PCI_66_EN__SHIFT 0x5
++#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
++#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
++#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
++#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
++#define STATUS__DEVSEL_TIMING_MASK 0x600
++#define STATUS__DEVSEL_TIMING__SHIFT 0x9
++#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
++#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
++#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
++#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
++#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
++#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
++#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
++#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
++#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
++#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
++#define REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
++#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
++#define SUB_CLASS__SUB_CLASS_MASK 0xff
++#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
++#define BASE_CLASS__BASE_CLASS_MASK 0xff
++#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
++#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define LATENCY__LATENCY_TIMER_MASK 0xff
++#define LATENCY__LATENCY_TIMER__SHIFT 0x0
++#define HEADER__HEADER_TYPE_MASK 0x7f
++#define HEADER__HEADER_TYPE__SHIFT 0x0
++#define HEADER__DEVICE_TYPE_MASK 0x80
++#define HEADER__DEVICE_TYPE__SHIFT 0x7
++#define BIST__BIST_COMP_MASK 0xf
++#define BIST__BIST_COMP__SHIFT 0x0
++#define BIST__BIST_STRT_MASK 0x40
++#define BIST__BIST_STRT__SHIFT 0x6
++#define BIST__BIST_CAP_MASK 0x80
++#define BIST__BIST_CAP__SHIFT 0x7
++#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
++#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
++#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
++#define CAP_PTR__CAP_PTR_MASK 0xff
++#define CAP_PTR__CAP_PTR__SHIFT 0x0
++#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
++#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
++#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
++#define MIN_GRANT__MIN_GNT_MASK 0xff
++#define MIN_GRANT__MIN_GNT__SHIFT 0x0
++#define MAX_LATENCY__MAX_LAT_MASK 0xff
++#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
++#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
++#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
++#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
++#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
++#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
++#define PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define PMI_CAP__VERSION_MASK 0x7
++#define PMI_CAP__VERSION__SHIFT 0x0
++#define PMI_CAP__PME_CLOCK_MASK 0x8
++#define PMI_CAP__PME_CLOCK__SHIFT 0x3
++#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
++#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
++#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
++#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
++#define PMI_CAP__D1_SUPPORT_MASK 0x200
++#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
++#define PMI_CAP__D2_SUPPORT_MASK 0x400
++#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
++#define PMI_CAP__PME_SUPPORT_MASK 0xf800
++#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
++#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define PCIE_CAP__VERSION_MASK 0xf
++#define PCIE_CAP__VERSION__SHIFT 0x0
++#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
++#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
++#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
++#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
++#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
++#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
++#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
++#define DEVICE_STATUS__CORR_ERR_MASK 0x1
++#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
++#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
++#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
++#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
++#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
++#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
++#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
++#define DEVICE_STATUS__AUX_PWR_MASK 0x10
++#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
++#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
++#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
++#define LINK_CAP__LINK_SPEED_MASK 0xf
++#define LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define LINK_CNTL__PM_CONTROL_MASK 0x3
++#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define LINK_CNTL__LINK_DIS_MASK 0x10
++#define LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
++#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
++#define LINK_STATUS__LINK_TRAINING_MASK 0x800
++#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
++#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
++#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
++#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
++#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define DEVICE_STATUS2__RESERVED_MASK 0xffff
++#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
++#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define LINK_CAP2__RESERVED__SHIFT 0x9
++#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
++#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
++#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
++#define MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
++#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
++#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
++#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
++#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
++#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
++#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
++#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
++#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x100
++#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define MSI_MASK__MSI_MASK_MASK 0xffffffff
++#define MSI_MASK__MSI_MASK__SHIFT 0x0
++#define MSI_PENDING__MSI_PENDING_MASK 0xffffffff
++#define MSI_PENDING__MSI_PENDING__SHIFT 0x0
++#define MSI_MASK_64__MSI_MASK_64_MASK 0xffffffff
++#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
++#define MSI_PENDING_64__MSI_PENDING_64_MASK 0xffffffff
++#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
++#define MSIX_CAP_LIST__CAP_ID_MASK 0xff
++#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
++#define MSIX_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x7ff
++#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
++#define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000
++#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
++#define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000
++#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
++#define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x7
++#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
++#define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xfffffff8
++#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
++#define MSIX_PBA__MSIX_PBA_BIR_MASK 0x7
++#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
++#define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xfffffff8
++#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
++#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
++#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
++#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
++#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
++#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
++#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
++#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
++#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
++#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
++#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
++#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
++#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
++#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
++#define PCIE_ATS_CNTL__STU_MASK 0x1f
++#define PCIE_ATS_CNTL__STU__SHIFT 0x0
++#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
++#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
++#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
++#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
++#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
++#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
++#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
++#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
++#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
++#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
++#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
++#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
++#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
++#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
++#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
++#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x1
++#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
++#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2
++#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
++#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xff00
++#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
++#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x1
++#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
++#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2
++#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
++#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x70
++#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x1
++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
++#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2
++#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000
++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x1
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x4
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x8
++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
++#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x10
++#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
++#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x1
++#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
++#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xffff
++#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
++#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xffff
++#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
++#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xffff
++#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
++#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xff
++#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
++#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xffff
++#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
++#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xffff
++#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
++#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xffff
++#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
++#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffff
++#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
++#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffff
++#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
++#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xffffffff
++#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
++#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xffffffff
++#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
++#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xffffffff
++#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
++#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xffffffff
++#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
++#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xffffffff
++#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
++#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xffffffff
++#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
++#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xffffffff
++#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x1
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK 0xff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK 0xff00
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT 0x8
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK 0xff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK 0xff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x1
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK 0x7f
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x80
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK 0xfffc0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT 0x12
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK 0xff00
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT 0x8
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK 0xff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK 0xff000000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT 0x18
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK 0xffff0000
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT 0x0
++#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
++#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
++#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
++#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
++#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
++#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
++#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
++#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
++#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK 0x1
++#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT 0x0
++#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
++#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
++#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
++#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
++#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
++#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
++#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
++#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
++#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
++#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
++#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
++#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
++#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
++#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
++#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
++#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
++#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
++#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
++#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
++#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
++#define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
++#define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
++#define LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
++#define LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
++#define LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
++#define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
++#define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2
++#define PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT 0x1
++#define PCIE_EFUSE__PPHY_EFUSE_VALID_MASK 0x4
++#define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2
++#define PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK 0x38
++#define PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT 0x3
++#define PCIE_EFUSE__ISTRAP_ARBEN0_MASK 0x40
++#define PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT 0x6
++#define PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK 0x7ffff80
++#define PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT 0x7
++#define PCIE_EFUSE__CHIP_BIF_MODE_MASK 0x8000000
++#define PCIE_EFUSE__CHIP_BIF_MODE__SHIFT 0x1b
++#define PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK 0xf0000000
++#define PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT 0x1c
++#define PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK 0xfffffffe
++#define PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT 0x1
++#define PCIE_EFUSE3__STRAP_CEC_ID_MASK 0x1fffe
++#define PCIE_EFUSE3__STRAP_CEC_ID__SHIFT 0x1
++#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK 0x20000
++#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT 0x11
++#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK 0xfffc0000
++#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT 0x12
++#define PCIE_EFUSE4__CC_WRITE_DISABLE_MASK 0x1
++#define PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT 0x0
++#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK 0xe
++#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT 0x1
++#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK 0xffff0
++#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT 0x4
++#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK 0xf00000
++#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT 0x14
++#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK 0xf000000
++#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT 0x18
++#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK 0xf0000000
++#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT 0x1c
++#define PCIE_EFUSE5__STRAP_AZALIA_DID_MASK 0x1fffe
++#define PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT 0x1
++#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK 0xfffe0000
++#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT 0x11
++#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK 0x1fffe
++#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT 0x1
++#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK 0xfffe0000
++#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT 0x11
++#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK 0x1fffe
++#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT 0x1
++#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK 0xfffe0000
++#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT 0x11
++#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
++#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
++#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
++#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
++#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
++#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
++#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
++#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
++#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
++#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
++#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
++#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
++#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2
++#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT 0x1
++#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
++#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
++#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
++#define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xffff
++#define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
++#define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
++#define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
++#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
++#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
++#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
++#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
++#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
++#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
++#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
++#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
++#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
++#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
++#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
++#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
++#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
++#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
++#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
++#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
++#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
++#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
++#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
++#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
++#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
++#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
++#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
++#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
++#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
++#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
++#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
++#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
++#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
++#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
++#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
++#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
++#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
++#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
++#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
++#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
++#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
++#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
++#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
++#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
++#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
++#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
++#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
++#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
++#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
++#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
++#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
++#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
++#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
++#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
++#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
++#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
++#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
++#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
++#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
++#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
++#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
++#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
++#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
++#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
++#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
++#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
++#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
++#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
++#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
++#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
++#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK 0x70000
++#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT 0x10
++#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
++#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
++#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
++#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
++#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
++#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
++#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
++#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
++#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
++#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
++#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
++#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
++#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
++#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
++#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
++#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
++#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
++#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
++#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
++#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
++#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
++#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
++#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
++#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
++#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
++#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
++#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
++#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
++#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
++#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
++#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
++#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
++#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
++#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
++#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
++#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
++#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
++#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
++#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
++#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
++#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
++#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
++#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
++#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
++#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
++#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
++#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
++#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
++#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
++#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
++#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
++#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
++#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
++#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
++#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
++#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
++#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
++#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
++#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
++#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
++#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x80000
++#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13
++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
++#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x10000
++#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
++#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK 0x1
++#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT 0x0
++#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2
++#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT 0x1
++#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK 0x4
++#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2
++#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK 0x8
++#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT 0x3
++#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK 0x10
++#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT 0x4
++#define PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK 0x20
++#define PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT 0x5
++#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK 0x40
++#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT 0x6
++#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK 0x80
++#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT 0x7
++#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK 0x100
++#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT 0x8
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
++#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
++#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
++#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
++#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
++#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
++#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
++#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
++#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
++#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
++#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
++#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
++#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
++#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
++#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
++#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
++#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
++#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
++#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
++#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
++#define PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
++#define PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
++#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
++#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
++#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
++#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK 0x40000
++#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT 0x12
++#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK 0x80000
++#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT 0x13
++#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK 0x100000
++#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT 0x14
++#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK 0xe00000
++#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT 0x15
++#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
++#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
++#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
++#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK 0x40000
++#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT 0x12
++#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK 0x80000
++#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT 0x13
++#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK 0x100000
++#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT 0x14
++#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK 0xe00000
++#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT 0x15
++#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
++#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
++#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK 0x1
++#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT 0x0
++#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK 0xe
++#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT 0x1
++#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK 0xfffff000
++#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT 0xc
++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
++#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
++#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
++#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
++#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
++#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
++#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
++#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
++#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
++#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
++#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
++#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
++#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
++#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
++#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
++#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
++#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
++#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x100
++#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
++#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
++#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
++#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
++#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
++#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
++#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
++#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
++#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
++#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
++#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
++#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
++#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
++#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
++#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
++#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
++#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
++#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
++#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
++#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
++#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
++#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
++#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
++#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
++#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
++#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
++#define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
++#define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
++#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
++#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
++#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK 0x10000000
++#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT 0x1c
++#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK 0x60000000
++#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT 0x1d
++#define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
++#define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
++#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
++#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
++#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
++#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
++#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
++#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
++#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
++#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
++#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
++#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
++#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
++#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
++#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
++#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
++#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
++#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
++#define SWRST_COMMAND_1__RESETPCFG_MASK 0x2
++#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
++#define SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
++#define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
++#define SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
++#define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
++#define SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
++#define SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
++#define SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
++#define SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
++#define SWRST_COMMAND_1__RESETLC_MASK 0x40
++#define SWRST_COMMAND_1__RESETLC__SHIFT 0x6
++#define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
++#define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
++#define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
++#define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
++#define SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
++#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
++#define SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
++#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
++#define SWRST_COMMAND_1__RESETCPM_MASK 0x8000
++#define SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
++#define SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
++#define SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
++#define SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
++#define SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
++#define SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
++#define SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
++#define SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
++#define SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
++#define SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
++#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
++#define SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
++#define SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
++#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
++#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
++#define SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
++#define SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
++#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
++#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
++#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
++#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
++#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
++#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
++#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
++#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
++#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
++#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
++#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
++#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
++#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
++#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
++#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
++#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
++#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
++#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
++#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
++#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
++#define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
++#define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
++#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
++#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
++#define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
++#define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
++#define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
++#define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
++#define SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
++#define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
++#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
++#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
++#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
++#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
++#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
++#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
++#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
++#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
++#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
++#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
++#define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
++#define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
++#define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
++#define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
++#define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
++#define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
++#define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
++#define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
++#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
++#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
++#define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
++#define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
++#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
++#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
++#define SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
++#define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
++#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
++#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
++#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
++#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
++#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
++#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
++#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
++#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
++#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
++#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
++#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
++#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
++#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
++#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
++#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
++#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
++#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
++#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
++#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
++#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
++#define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
++#define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
++#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
++#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
++#define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
++#define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
++#define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
++#define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
++#define SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
++#define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
++#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
++#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
++#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
++#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
++#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
++#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
++#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
++#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
++#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
++#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
++#define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
++#define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
++#define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
++#define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
++#define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
++#define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
++#define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
++#define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
++#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
++#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
++#define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
++#define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
++#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
++#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
++#define SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
++#define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
++#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
++#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
++#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
++#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
++#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
++#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
++#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
++#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
++#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
++#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
++#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
++#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
++#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
++#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
++#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
++#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
++#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
++#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
++#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
++#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
++#define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
++#define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
++#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
++#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
++#define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
++#define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
++#define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
++#define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
++#define SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
++#define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
++#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
++#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
++#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
++#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
++#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
++#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
++#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
++#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
++#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
++#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
++#define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
++#define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
++#define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
++#define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
++#define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
++#define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
++#define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
++#define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
++#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
++#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
++#define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
++#define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
++#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
++#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
++#define SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
++#define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
++#define SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
++#define SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
++#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
++#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
++#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x1
++#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
++#define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2
++#define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT 0x1
++#define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK 0x4
++#define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2
++#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x100
++#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
++#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x200
++#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
++#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x400
++#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
++#define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK 0x10000
++#define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT 0x10
++#define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK 0x20000
++#define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT 0x11
++#define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK 0x40000
++#define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT 0x12
++#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x1
++#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
++#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2
++#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT 0x1
++#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK 0x4
++#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2
++#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x100
++#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
++#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x200
++#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
++#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x400
++#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
++#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK 0x10000
++#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT 0x10
++#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK 0x20000
++#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT 0x11
++#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK 0x40000
++#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT 0x12
++#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK 0x80000
++#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT 0x13
++#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK 0xf00000
++#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT 0x14
++#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
++#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
++#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
++#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
++#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
++#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
++#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
++#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
++#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
++#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
++#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
++#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
++#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
++#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
++#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
++#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
++#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
++#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
++#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
++#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
++#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
++#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
++#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
++#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
++#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
++#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
++#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
++#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
++#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
++#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
++#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
++#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
++#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
++#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
++#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
++#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
++#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
++#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
++#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
++#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
++#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
++#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
++#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
++#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
++#define CPM_CONTROL__SPARE_REGS_MASK 0xff000000
++#define CPM_CONTROL__SPARE_REGS__SHIFT 0x18
++#define GSKT_CONTROL__GSKT_TxFifoBypass_MASK 0x1
++#define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT 0x0
++#define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2
++#define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT 0x1
++#define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK 0x4
++#define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2
++#define GSKT_CONTROL__GSKT_SpareRegs_MASK 0xf8
++#define GSKT_CONTROL__GSKT_SpareRegs__SHIFT 0x3
++#define LM_CONTROL__LoopbackSelect_MASK 0x1e
++#define LM_CONTROL__LoopbackSelect__SHIFT 0x1
++#define LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
++#define LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
++#define LM_CONTROL__LoopbackHalfRate_MASK 0xc0
++#define LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
++#define LM_CONTROL__LoopbackFifoPtr_MASK 0x700
++#define LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
++#define LM_PCIETXMUX0__TXLANE0_MASK 0xff
++#define LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
++#define LM_PCIETXMUX0__TXLANE1_MASK 0xff00
++#define LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
++#define LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
++#define LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
++#define LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
++#define LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
++#define LM_PCIETXMUX1__TXLANE4_MASK 0xff
++#define LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
++#define LM_PCIETXMUX1__TXLANE5_MASK 0xff00
++#define LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
++#define LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
++#define LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
++#define LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
++#define LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
++#define LM_PCIETXMUX2__TXLANE8_MASK 0xff
++#define LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
++#define LM_PCIETXMUX2__TXLANE9_MASK 0xff00
++#define LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
++#define LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
++#define LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
++#define LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
++#define LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
++#define LM_PCIETXMUX3__TXLANE12_MASK 0xff
++#define LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
++#define LM_PCIETXMUX3__TXLANE13_MASK 0xff00
++#define LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
++#define LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
++#define LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
++#define LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
++#define LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
++#define LM_PCIERXMUX0__RXLANE0_MASK 0xff
++#define LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
++#define LM_PCIERXMUX0__RXLANE1_MASK 0xff00
++#define LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
++#define LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
++#define LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
++#define LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
++#define LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
++#define LM_PCIERXMUX1__RXLANE4_MASK 0xff
++#define LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
++#define LM_PCIERXMUX1__RXLANE5_MASK 0xff00
++#define LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
++#define LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
++#define LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
++#define LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
++#define LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
++#define LM_PCIERXMUX2__RXLANE8_MASK 0xff
++#define LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
++#define LM_PCIERXMUX2__RXLANE9_MASK 0xff00
++#define LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
++#define LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
++#define LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
++#define LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
++#define LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
++#define LM_PCIERXMUX3__RXLANE12_MASK 0xff
++#define LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
++#define LM_PCIERXMUX3__RXLANE13_MASK 0xff00
++#define LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
++#define LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
++#define LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
++#define LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
++#define LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
++#define LM_LANEENABLE__LANE_enable_MASK 0xffff
++#define LM_LANEENABLE__LANE_enable__SHIFT 0x0
++#define LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
++#define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
++#define LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
++#define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
++#define LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
++#define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
++#define LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
++#define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
++#define LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
++#define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
++#define LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
++#define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
++#define LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
++#define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
++#define LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
++#define LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
++#define LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
++#define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
++#define LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
++#define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
++#define LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
++#define LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
++#define LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
++#define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
++#define LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
++#define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
++#define LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
++#define LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
++#define LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
++#define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
++#define LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
++#define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
++#define LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
++#define LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
++#define LM_POWERCONTROL1__LMTxEn0_MASK 0x1
++#define LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
++#define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
++#define LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
++#define LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
++#define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
++#define LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
++#define LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
++#define LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
++#define LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
++#define LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
++#define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
++#define LM_POWERCONTROL1__LMDeemph0_MASK 0x100
++#define LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
++#define LM_POWERCONTROL1__LMTxEn1_MASK 0x200
++#define LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
++#define LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
++#define LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
++#define LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
++#define LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
++#define LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
++#define LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
++#define LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
++#define LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
++#define LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
++#define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
++#define LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
++#define LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
++#define LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
++#define LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
++#define LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
++#define LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
++#define LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
++#define LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
++#define LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
++#define LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
++#define LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
++#define LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
++#define LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
++#define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
++#define LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
++#define LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
++#define LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
++#define LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
++#define LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
++#define LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
++#define LM_POWERCONTROL2__LMTxEn3_MASK 0x1
++#define LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
++#define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
++#define LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
++#define LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
++#define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
++#define LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
++#define LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
++#define LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
++#define LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
++#define LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
++#define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
++#define LM_POWERCONTROL2__LMDeemph3_MASK 0x100
++#define LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
++#define LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
++#define LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
++#define LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
++#define LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
++#define LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
++#define LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
++#define LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
++#define LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
++#define LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
++#define LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
++#define LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
++#define LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
++#define LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
++#define LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
++#define LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
++#define LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
++#define LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
++#define LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
++#define LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
++#define LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
++#define LM_POWERCONTROL4__LinkNum0_MASK 0x7
++#define LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
++#define LM_POWERCONTROL4__LinkNum1_MASK 0x38
++#define LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
++#define LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
++#define LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
++#define LM_POWERCONTROL4__LinkNum3_MASK 0xe00
++#define LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
++#define LM_POWERCONTROL4__LaneNum0_MASK 0xf000
++#define LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
++#define LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
++#define LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
++#define LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
++#define LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
++#define LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
++#define LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
++#define LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
++#define LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
++#define LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
++#define LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
++#define LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
++#define LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
++#define LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
++#define LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
++#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff
++#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
++#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
++#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
++#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
++#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
++#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
++#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
++#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
++#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
++#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
++#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
++#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
++#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
++#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
++#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
++#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
++#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
++#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
++#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
++#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
++#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
++#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
++#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
++#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
++#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
++#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
++#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
++#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
++#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
++#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
++#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
++#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
++#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
++#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
++#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
++#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
++#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
++#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
++#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
++#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
++#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
++#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
++#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
++#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
++#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
++#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
++#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
++#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
++#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
++#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
++#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
++#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
++#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
++#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
++#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
++#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
++#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
++#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4
++#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
++#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
++#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
++#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
++#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
++#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
++#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
++#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
++#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
++#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
++#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4
++#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
++#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8
++#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3
++#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10
++#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4
++#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20
++#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5
++#define PB0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PB0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PB0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PB0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PB0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PB0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PB0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PB0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PB0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PB0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PB0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PB0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PB0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PB0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PB0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PB0_HW_DEBUG__HW_16_DEBUG_MASK 0x10000
++#define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
++#define PB0_HW_DEBUG__HW_17_DEBUG_MASK 0x20000
++#define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
++#define PB0_HW_DEBUG__HW_18_DEBUG_MASK 0x40000
++#define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
++#define PB0_HW_DEBUG__HW_19_DEBUG_MASK 0x80000
++#define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
++#define PB0_HW_DEBUG__HW_20_DEBUG_MASK 0x100000
++#define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
++#define PB0_HW_DEBUG__HW_21_DEBUG_MASK 0x200000
++#define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
++#define PB0_HW_DEBUG__HW_22_DEBUG_MASK 0x400000
++#define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
++#define PB0_HW_DEBUG__HW_23_DEBUG_MASK 0x800000
++#define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
++#define PB0_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
++#define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
++#define PB0_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
++#define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
++#define PB0_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
++#define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
++#define PB0_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
++#define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
++#define PB0_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
++#define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
++#define PB0_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
++#define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
++#define PB0_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
++#define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
++#define PB0_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
++#define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
++#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
++#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
++#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
++#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10
++#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4
++#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
++#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
++#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
++#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
++#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
++#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
++#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
++#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
++#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
++#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
++#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
++#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
++#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
++#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
++#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
++#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
++#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
++#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
++#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
++#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
++#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
++#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
++#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
++#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
++#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
++#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
++#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
++#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
++#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
++#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
++#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
++#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6
++#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1
++#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18
++#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3
++#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60
++#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5
++#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80
++#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7
++#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300
++#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8
++#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400
++#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa
++#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800
++#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb
++#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c
++#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
++#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60
++#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5
++#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180
++#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7
++#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600
++#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9
++#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800
++#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb
++#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000
++#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c
++#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000
++#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d
++#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000
++#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e
++#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
++#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
++#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
++#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
++#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
++#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
++#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
++#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
++#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
++#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
++#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
++#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
++#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
++#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
++#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
++#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
++#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
++#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
++#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
++#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
++#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
++#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
++#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
++#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
++#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
++#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
++#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000
++#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
++#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
++#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
++#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
++#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
++#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300
++#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300
++#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300
++#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300
++#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
++#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
++#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
++#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
++#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
++#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
++#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
++#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
++#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
++#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
++#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
++#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
++#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
++#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00
++#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9
++#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000
++#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000
++#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe
++#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000
++#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
++#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
++#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
++#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
++#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
++#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
++#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000
++#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe
++#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000
++#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10
++#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000
++#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
++#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10
++#define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4
++#define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20
++#define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000
++#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
++#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
++#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
++#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
++#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
++#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
++#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
++#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
++#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
++#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
++#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
++#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
++#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
++#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
++#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
++#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
++#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
++#define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000
++#define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00
++#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa
++#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
++#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
++#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
++#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
++#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
++#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
++#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
++#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
++#define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000
++#define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00
++#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa
++#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
++#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
++#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
++#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
++#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
++#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
++#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
++#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
++#define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000
++#define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00
++#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa
++#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
++#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
++#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
++#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
++#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
++#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
++#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
++#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
++#define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000
++#define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00
++#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa
++#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
++#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
++#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
++#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
++#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
++#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
++#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
++#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
++#define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000
++#define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00
++#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa
++#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
++#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
++#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
++#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
++#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
++#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
++#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
++#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
++#define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000
++#define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00
++#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa
++#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
++#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
++#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
++#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
++#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
++#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
++#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
++#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
++#define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000
++#define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00
++#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa
++#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
++#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
++#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
++#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
++#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
++#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
++#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
++#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
++#define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000
++#define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00
++#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa
++#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
++#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
++#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
++#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
++#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
++#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
++#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
++#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
++#define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000
++#define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00
++#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa
++#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
++#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
++#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
++#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
++#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
++#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
++#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
++#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
++#define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000
++#define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00
++#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa
++#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
++#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
++#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
++#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
++#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
++#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
++#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
++#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
++#define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000
++#define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00
++#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa
++#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
++#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
++#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
++#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
++#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
++#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
++#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
++#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
++#define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000
++#define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00
++#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa
++#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
++#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
++#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
++#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
++#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
++#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
++#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
++#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
++#define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000
++#define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00
++#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa
++#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
++#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
++#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
++#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
++#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
++#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
++#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
++#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
++#define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000
++#define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00
++#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa
++#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
++#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
++#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
++#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
++#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
++#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
++#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
++#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
++#define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000
++#define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00
++#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa
++#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
++#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
++#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
++#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
++#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
++#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
++#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
++#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
++#define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000
++#define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00
++#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
++#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
++#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
++#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
++#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
++#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
++#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
++#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
++#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
++#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
++#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
++#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
++#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000
++#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
++#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000
++#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
++#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
++#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
++#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
++#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
++#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
++#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
++#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
++#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
++#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
++#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
++#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
++#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
++#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
++#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
++#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
++#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
++#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
++#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
++#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
++#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
++#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
++#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
++#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
++#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
++#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
++#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
++#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
++#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
++#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
++#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
++#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
++#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
++#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
++#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
++#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
++#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
++#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
++#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
++#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
++#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
++#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
++#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
++#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
++#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
++#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
++#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
++#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
++#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
++#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
++#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
++#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
++#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
++#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
++#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
++#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
++#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
++#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
++#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
++#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
++#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
++#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
++#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
++#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
++#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
++#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
++#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
++#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
++#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
++#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
++#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
++#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
++#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
++#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
++#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
++#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
++#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
++#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
++#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
++#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
++#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
++#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
++#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
++#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
++#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
++#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
++#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
++#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
++#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
++#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
++#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
++#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
++#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
++#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
++#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
++#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
++#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
++#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
++#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
++#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
++#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
++#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
++#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
++#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
++#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
++#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
++#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
++#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
++#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
++#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
++#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
++#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
++#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
++#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
++#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
++#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
++#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
++#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
++#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
++#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
++#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
++#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
++#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
++#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
++#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff
++#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
++#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
++#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
++#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
++#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
++#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
++#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
++#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
++#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
++#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
++#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
++#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
++#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
++#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
++#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
++#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
++#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
++#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
++#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
++#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
++#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
++#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
++#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
++#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
++#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
++#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
++#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
++#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
++#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
++#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
++#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
++#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
++#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
++#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
++#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
++#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
++#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
++#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
++#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
++#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
++#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
++#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
++#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
++#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
++#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
++#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
++#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
++#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
++#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
++#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
++#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
++#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
++#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
++#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
++#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
++#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
++#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
++#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4
++#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
++#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
++#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
++#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
++#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
++#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
++#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
++#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
++#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
++#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
++#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
++#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4
++#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
++#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8
++#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3
++#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10
++#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4
++#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20
++#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5
++#define PB1_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PB1_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PB1_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PB1_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PB1_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PB1_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PB1_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PB1_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PB1_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PB1_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PB1_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PB1_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PB1_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PB1_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PB1_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PB1_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PB1_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PB1_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PB1_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PB1_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PB1_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PB1_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PB1_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PB1_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PB1_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PB1_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PB1_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PB1_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PB1_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PB1_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PB1_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PB1_HW_DEBUG__HW_16_DEBUG_MASK 0x10000
++#define PB1_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
++#define PB1_HW_DEBUG__HW_17_DEBUG_MASK 0x20000
++#define PB1_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
++#define PB1_HW_DEBUG__HW_18_DEBUG_MASK 0x40000
++#define PB1_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
++#define PB1_HW_DEBUG__HW_19_DEBUG_MASK 0x80000
++#define PB1_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
++#define PB1_HW_DEBUG__HW_20_DEBUG_MASK 0x100000
++#define PB1_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
++#define PB1_HW_DEBUG__HW_21_DEBUG_MASK 0x200000
++#define PB1_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
++#define PB1_HW_DEBUG__HW_22_DEBUG_MASK 0x400000
++#define PB1_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
++#define PB1_HW_DEBUG__HW_23_DEBUG_MASK 0x800000
++#define PB1_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
++#define PB1_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
++#define PB1_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
++#define PB1_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
++#define PB1_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
++#define PB1_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
++#define PB1_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
++#define PB1_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
++#define PB1_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
++#define PB1_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
++#define PB1_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
++#define PB1_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
++#define PB1_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
++#define PB1_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
++#define PB1_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
++#define PB1_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
++#define PB1_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
++#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
++#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
++#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
++#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10
++#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4
++#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
++#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
++#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
++#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
++#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
++#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
++#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
++#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
++#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
++#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
++#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
++#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
++#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
++#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
++#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
++#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
++#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
++#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
++#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
++#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
++#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
++#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
++#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
++#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
++#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
++#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
++#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
++#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
++#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
++#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
++#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
++#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6
++#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1
++#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18
++#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3
++#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60
++#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5
++#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80
++#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7
++#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300
++#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8
++#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400
++#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa
++#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800
++#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb
++#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c
++#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
++#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60
++#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5
++#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180
++#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7
++#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600
++#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9
++#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800
++#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb
++#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000
++#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c
++#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000
++#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d
++#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000
++#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e
++#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
++#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
++#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
++#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
++#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
++#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
++#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
++#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
++#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
++#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
++#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
++#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
++#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
++#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
++#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
++#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
++#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
++#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
++#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
++#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
++#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
++#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
++#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
++#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
++#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
++#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
++#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000
++#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
++#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
++#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
++#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
++#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
++#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300
++#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300
++#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300
++#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300
++#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
++#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
++#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
++#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
++#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
++#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
++#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
++#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
++#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
++#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
++#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
++#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
++#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
++#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
++#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00
++#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9
++#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000
++#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000
++#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe
++#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000
++#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
++#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
++#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
++#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
++#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
++#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
++#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000
++#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe
++#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000
++#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10
++#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000
++#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
++#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10
++#define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4
++#define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20
++#define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000
++#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
++#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
++#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
++#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
++#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
++#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
++#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
++#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
++#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
++#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
++#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
++#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
++#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
++#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
++#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
++#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
++#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
++#define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000
++#define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00
++#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa
++#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
++#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
++#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
++#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
++#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
++#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
++#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
++#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
++#define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000
++#define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00
++#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa
++#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
++#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
++#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
++#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
++#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
++#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
++#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
++#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
++#define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000
++#define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00
++#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa
++#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
++#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
++#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
++#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
++#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
++#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
++#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
++#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
++#define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000
++#define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00
++#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa
++#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
++#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
++#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
++#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
++#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
++#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
++#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
++#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
++#define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000
++#define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00
++#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa
++#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
++#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
++#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
++#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
++#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
++#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
++#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
++#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
++#define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000
++#define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00
++#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa
++#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
++#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
++#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
++#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
++#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
++#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
++#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
++#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
++#define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000
++#define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00
++#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa
++#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
++#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
++#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
++#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
++#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
++#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
++#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
++#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
++#define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000
++#define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00
++#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa
++#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
++#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
++#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
++#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
++#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
++#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
++#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
++#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
++#define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000
++#define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00
++#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa
++#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
++#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
++#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
++#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
++#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
++#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
++#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
++#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
++#define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000
++#define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00
++#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa
++#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
++#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
++#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
++#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
++#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
++#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
++#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
++#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
++#define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000
++#define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00
++#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa
++#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
++#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
++#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
++#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
++#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
++#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
++#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
++#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
++#define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000
++#define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00
++#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa
++#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
++#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
++#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
++#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
++#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
++#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
++#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
++#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
++#define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000
++#define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00
++#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa
++#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
++#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
++#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
++#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
++#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
++#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
++#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
++#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
++#define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000
++#define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00
++#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa
++#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
++#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
++#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
++#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
++#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
++#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
++#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
++#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
++#define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000
++#define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00
++#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa
++#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
++#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
++#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
++#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
++#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
++#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
++#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
++#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
++#define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000
++#define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00
++#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
++#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
++#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
++#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
++#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
++#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
++#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
++#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
++#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
++#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
++#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
++#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
++#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000
++#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
++#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000
++#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
++#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
++#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
++#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
++#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
++#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
++#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
++#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
++#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
++#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
++#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
++#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
++#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
++#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
++#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
++#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
++#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
++#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
++#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
++#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
++#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
++#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
++#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
++#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
++#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
++#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
++#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
++#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
++#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
++#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
++#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
++#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
++#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
++#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
++#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
++#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
++#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
++#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
++#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
++#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
++#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
++#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
++#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
++#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
++#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
++#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
++#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
++#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
++#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
++#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
++#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
++#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
++#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
++#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
++#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
++#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
++#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
++#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
++#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
++#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
++#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
++#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
++#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
++#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
++#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
++#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
++#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
++#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
++#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
++#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
++#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
++#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
++#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
++#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
++#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
++#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
++#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
++#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
++#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
++#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
++#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
++#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
++#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
++#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
++#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
++#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
++#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
++#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
++#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
++#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
++#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
++#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
++#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
++#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
++#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
++#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
++#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
++#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
++#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
++#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
++#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
++#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
++#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
++#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
++#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
++#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
++#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
++#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
++#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
++#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
++#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
++#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
++#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
++#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
++#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
++#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
++#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
++#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
++#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
++#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
++#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
++#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
++#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
++#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
++#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
++#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
++#define PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
++#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
++#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
++#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
++#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
++#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
++#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
++#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
++#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
++#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
++#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
++#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
++#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
++#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
++#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
++#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
++#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
++#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
++#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
++#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
++#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
++#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
++#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
++#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
++#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
++#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
++#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
++#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
++#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
++#define PB0_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0
++#define PB0_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6
++#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
++#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
++#define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
++#define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
++#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
++#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
++#define PB0_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
++#define PB0_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
++#define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
++#define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
++#define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
++#define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
++#define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
++#define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
++#define PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7
++#define PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
++#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
++#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
++#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
++#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
++#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
++#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
++#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
++#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
++#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
++#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
++#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
++#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
++#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
++#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
++#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
++#define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
++#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
++#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
++#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
++#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
++#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
++#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
++#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
++#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
++#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
++#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
++#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
++#define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
++#define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
++#define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
++#define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
++#define PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7
++#define PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
++#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
++#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
++#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
++#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
++#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
++#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
++#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
++#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
++#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
++#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
++#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
++#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
++#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
++#define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
++#define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
++#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
++#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
++#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
++#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
++#define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
++#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
++#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
++#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
++#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
++#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
++#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
++#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
++#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
++#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
++#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
++#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
++#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
++#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
++#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
++#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
++#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
++#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
++#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
++#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
++#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
++#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
++#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
++#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
++#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
++#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
++#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
++#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
++#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
++#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
++#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
++#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
++#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
++#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
++#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
++#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
++#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
++#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
++#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
++#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
++#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
++#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
++#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
++#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
++#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
++#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
++#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
++#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
++#define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
++#define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
++#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
++#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
++#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
++#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
++#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
++#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
++#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
++#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
++#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
++#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
++#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
++#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
++#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
++#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
++#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
++#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
++#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
++#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
++#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
++#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
++#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
++#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
++#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
++#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
++#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
++#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
++#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
++#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
++#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
++#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
++#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
++#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
++#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
++#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
++#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
++#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
++#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
++#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
++#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
++#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
++#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
++#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
++#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
++#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
++#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
++#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
++#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
++#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
++#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
++#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
++#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
++#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
++#define PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7
++#define PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
++#define PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18
++#define PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
++#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
++#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
++#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
++#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
++#define PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700
++#define PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
++#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
++#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
++#define PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000
++#define PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
++#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
++#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
++#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
++#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
++#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
++#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
++#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
++#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
++#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
++#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
++#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
++#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
++#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
++#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
++#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
++#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
++#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
++#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
++#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
++#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
++#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
++#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
++#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
++#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
++#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
++#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
++#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
++#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
++#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
++#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
++#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
++#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
++#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
++#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
++#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
++#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
++#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
++#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
++#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
++#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
++#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
++#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
++#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
++#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
++#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
++#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
++#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
++#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
++#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
++#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
++#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
++#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
++#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
++#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
++#define PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7
++#define PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
++#define PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18
++#define PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
++#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
++#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
++#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
++#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
++#define PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700
++#define PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
++#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
++#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
++#define PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000
++#define PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
++#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
++#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
++#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
++#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
++#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
++#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
++#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
++#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
++#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
++#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
++#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
++#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
++#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
++#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
++#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
++#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
++#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
++#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
++#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
++#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
++#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
++#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
++#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
++#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
++#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
++#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
++#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
++#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
++#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
++#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
++#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
++#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
++#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
++#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
++#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
++#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
++#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
++#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
++#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
++#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
++#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
++#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
++#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
++#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
++#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
++#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
++#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
++#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
++#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
++#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
++#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
++#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
++#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
++#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
++#define PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7
++#define PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
++#define PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18
++#define PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
++#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
++#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
++#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
++#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
++#define PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700
++#define PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
++#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
++#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
++#define PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000
++#define PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
++#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
++#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
++#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
++#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
++#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
++#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
++#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
++#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
++#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
++#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
++#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
++#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
++#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
++#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
++#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
++#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
++#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
++#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
++#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
++#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
++#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
++#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
++#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
++#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
++#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
++#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
++#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
++#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
++#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
++#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
++#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
++#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
++#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
++#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
++#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
++#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
++#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
++#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
++#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
++#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
++#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
++#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
++#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
++#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
++#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
++#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
++#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
++#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
++#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
++#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
++#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
++#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
++#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
++#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
++#define PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7
++#define PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
++#define PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18
++#define PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
++#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
++#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
++#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
++#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
++#define PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700
++#define PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
++#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
++#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
++#define PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000
++#define PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
++#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
++#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
++#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
++#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
++#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
++#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
++#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
++#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
++#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
++#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
++#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
++#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
++#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
++#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
++#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
++#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
++#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
++#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
++#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
++#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
++#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
++#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
++#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
++#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
++#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
++#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
++#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
++#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
++#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
++#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
++#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
++#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
++#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
++#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
++#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
++#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
++#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
++#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
++#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
++#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
++#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
++#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
++#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
++#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
++#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
++#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
++#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
++#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
++#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
++#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
++#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
++#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
++#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
++#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
++#define PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7
++#define PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
++#define PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18
++#define PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
++#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
++#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
++#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
++#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
++#define PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700
++#define PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
++#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
++#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
++#define PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000
++#define PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
++#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
++#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
++#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
++#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
++#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
++#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
++#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
++#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
++#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
++#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
++#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
++#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
++#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
++#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
++#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
++#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
++#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
++#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
++#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
++#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
++#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
++#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
++#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
++#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
++#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
++#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
++#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
++#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
++#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
++#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
++#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
++#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
++#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
++#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
++#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
++#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
++#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
++#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
++#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
++#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
++#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
++#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
++#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
++#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
++#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
++#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
++#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
++#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
++#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
++#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
++#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
++#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
++#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
++#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
++#define PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7
++#define PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
++#define PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18
++#define PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
++#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
++#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
++#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
++#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
++#define PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700
++#define PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
++#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
++#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
++#define PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000
++#define PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
++#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
++#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
++#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
++#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
++#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
++#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
++#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
++#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
++#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
++#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
++#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
++#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
++#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
++#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
++#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
++#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
++#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
++#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
++#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
++#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
++#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
++#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
++#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
++#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
++#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
++#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
++#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
++#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
++#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
++#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
++#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
++#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
++#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
++#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
++#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
++#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
++#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
++#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
++#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
++#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
++#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
++#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
++#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
++#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
++#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
++#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
++#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
++#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
++#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
++#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
++#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
++#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
++#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
++#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
++#define PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7
++#define PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
++#define PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18
++#define PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
++#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
++#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
++#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
++#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
++#define PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700
++#define PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
++#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
++#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
++#define PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000
++#define PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
++#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
++#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
++#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
++#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
++#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
++#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
++#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
++#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
++#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
++#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
++#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
++#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
++#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
++#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
++#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
++#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
++#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
++#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
++#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
++#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
++#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
++#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
++#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
++#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
++#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
++#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
++#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
++#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
++#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
++#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
++#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
++#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
++#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
++#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
++#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
++#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
++#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
++#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
++#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
++#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
++#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
++#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
++#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
++#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
++#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
++#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
++#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
++#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
++#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
++#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
++#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
++#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
++#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
++#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
++#define PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7
++#define PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
++#define PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18
++#define PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
++#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
++#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
++#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
++#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
++#define PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700
++#define PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
++#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
++#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
++#define PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000
++#define PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
++#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
++#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
++#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
++#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
++#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
++#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
++#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
++#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
++#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
++#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
++#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
++#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
++#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
++#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
++#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
++#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
++#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
++#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
++#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
++#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
++#define PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
++#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
++#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
++#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
++#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
++#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
++#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
++#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
++#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
++#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
++#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
++#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
++#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
++#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
++#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
++#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
++#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
++#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
++#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
++#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
++#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
++#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
++#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
++#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
++#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
++#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
++#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
++#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
++#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
++#define PB1_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0
++#define PB1_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6
++#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
++#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
++#define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
++#define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
++#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
++#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
++#define PB1_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
++#define PB1_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
++#define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
++#define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
++#define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
++#define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
++#define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
++#define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
++#define PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7
++#define PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
++#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
++#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
++#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
++#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
++#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
++#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
++#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
++#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
++#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
++#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
++#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
++#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
++#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
++#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
++#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
++#define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
++#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
++#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
++#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
++#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
++#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
++#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
++#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
++#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
++#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
++#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
++#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
++#define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
++#define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
++#define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
++#define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
++#define PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7
++#define PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
++#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
++#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
++#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
++#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
++#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
++#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
++#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
++#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
++#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
++#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
++#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
++#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
++#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
++#define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
++#define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
++#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
++#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
++#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
++#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
++#define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
++#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
++#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
++#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
++#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
++#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
++#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
++#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
++#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
++#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
++#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
++#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
++#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
++#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
++#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
++#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
++#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
++#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
++#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
++#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
++#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
++#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
++#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
++#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
++#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
++#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
++#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
++#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
++#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
++#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
++#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
++#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
++#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
++#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
++#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
++#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
++#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
++#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
++#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
++#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
++#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
++#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
++#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
++#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
++#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
++#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
++#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
++#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
++#define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
++#define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
++#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
++#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
++#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
++#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
++#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
++#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
++#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
++#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
++#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
++#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
++#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
++#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
++#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
++#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
++#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
++#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
++#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
++#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
++#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
++#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
++#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
++#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
++#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
++#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
++#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
++#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
++#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
++#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
++#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
++#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
++#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
++#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
++#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
++#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
++#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
++#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
++#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
++#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
++#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
++#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
++#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
++#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
++#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
++#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
++#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
++#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
++#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
++#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
++#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
++#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
++#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
++#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
++#define PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7
++#define PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
++#define PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18
++#define PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
++#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
++#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
++#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
++#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
++#define PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700
++#define PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
++#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
++#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
++#define PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000
++#define PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
++#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
++#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
++#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
++#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
++#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
++#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
++#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
++#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
++#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
++#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
++#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
++#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
++#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
++#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
++#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
++#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
++#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
++#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
++#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
++#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
++#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
++#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
++#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
++#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
++#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
++#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
++#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
++#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
++#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
++#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
++#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
++#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
++#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
++#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
++#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
++#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
++#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
++#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
++#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
++#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
++#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
++#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
++#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
++#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
++#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
++#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
++#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
++#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
++#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
++#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
++#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
++#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
++#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
++#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
++#define PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7
++#define PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
++#define PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18
++#define PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
++#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
++#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
++#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
++#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
++#define PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700
++#define PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
++#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
++#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
++#define PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000
++#define PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
++#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
++#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
++#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
++#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
++#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
++#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
++#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
++#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
++#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
++#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
++#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
++#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
++#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
++#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
++#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
++#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
++#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
++#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
++#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
++#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
++#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
++#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
++#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
++#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
++#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
++#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
++#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
++#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
++#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
++#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
++#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
++#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
++#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
++#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
++#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
++#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
++#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
++#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
++#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
++#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
++#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
++#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
++#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
++#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
++#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
++#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
++#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
++#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
++#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
++#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
++#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
++#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
++#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
++#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
++#define PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7
++#define PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
++#define PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18
++#define PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
++#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
++#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
++#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
++#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
++#define PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700
++#define PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
++#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
++#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
++#define PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000
++#define PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
++#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
++#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
++#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
++#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
++#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
++#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
++#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
++#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
++#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
++#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
++#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
++#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
++#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
++#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
++#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
++#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
++#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
++#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
++#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
++#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
++#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
++#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
++#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
++#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
++#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
++#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
++#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
++#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
++#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
++#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
++#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
++#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
++#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
++#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
++#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
++#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
++#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
++#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
++#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
++#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
++#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
++#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
++#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
++#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
++#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
++#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
++#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
++#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
++#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
++#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
++#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
++#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
++#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
++#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
++#define PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7
++#define PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
++#define PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18
++#define PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
++#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
++#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
++#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
++#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
++#define PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700
++#define PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
++#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
++#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
++#define PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000
++#define PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
++#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
++#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
++#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
++#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
++#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
++#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
++#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
++#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
++#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
++#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
++#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
++#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
++#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
++#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
++#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
++#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
++#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
++#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
++#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
++#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
++#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
++#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
++#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
++#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
++#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
++#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
++#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
++#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
++#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
++#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
++#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
++#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
++#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
++#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
++#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
++#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
++#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
++#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
++#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
++#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
++#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
++#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
++#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
++#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
++#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
++#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
++#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
++#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
++#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
++#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
++#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
++#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
++#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
++#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
++#define PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7
++#define PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
++#define PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18
++#define PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
++#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
++#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
++#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
++#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
++#define PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700
++#define PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
++#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
++#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
++#define PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000
++#define PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
++#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
++#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
++#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
++#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
++#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
++#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
++#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
++#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
++#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
++#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
++#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
++#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
++#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
++#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
++#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
++#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
++#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
++#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
++#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
++#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
++#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
++#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
++#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
++#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
++#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
++#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
++#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
++#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
++#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
++#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
++#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
++#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
++#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
++#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
++#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
++#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
++#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
++#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
++#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
++#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
++#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
++#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
++#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
++#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
++#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
++#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
++#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
++#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
++#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
++#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
++#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
++#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
++#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
++#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
++#define PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7
++#define PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
++#define PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18
++#define PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
++#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
++#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
++#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
++#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
++#define PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700
++#define PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
++#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
++#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
++#define PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000
++#define PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
++#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
++#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
++#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
++#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
++#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
++#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
++#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
++#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
++#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
++#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
++#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
++#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
++#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
++#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
++#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
++#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
++#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
++#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
++#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
++#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
++#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
++#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
++#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
++#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
++#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
++#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
++#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
++#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
++#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
++#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
++#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
++#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
++#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
++#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
++#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
++#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
++#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
++#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
++#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
++#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
++#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
++#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
++#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
++#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
++#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
++#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
++#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
++#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
++#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
++#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
++#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
++#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
++#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
++#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
++#define PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7
++#define PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
++#define PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18
++#define PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
++#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
++#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
++#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
++#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
++#define PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700
++#define PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
++#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
++#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
++#define PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000
++#define PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
++#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
++#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
++#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
++#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
++#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
++#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
++#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
++#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
++#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
++#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
++#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
++#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
++#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
++#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
++#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
++#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
++#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
++#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
++#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
++#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
++#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
++#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
++#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
++#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
++#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
++#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
++#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
++#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
++#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
++#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
++#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
++#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
++#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
++#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
++#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
++#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
++#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
++#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
++#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
++#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
++#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
++#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
++#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
++#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
++#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
++#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
++#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
++#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
++#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
++#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
++#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
++#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
++#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
++#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
++#define PB1_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7
++#define PB1_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
++#define PB1_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18
++#define PB1_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
++#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
++#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
++#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
++#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
++#define PB1_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700
++#define PB1_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
++#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
++#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
++#define PB1_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000
++#define PB1_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
++#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
++#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
++#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
++#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
++#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
++#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
++#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
++#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
++#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
++#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
++#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
++#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
++#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
++#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
++#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
++#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
++#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
++#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
++#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
++#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
++#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
++#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
++#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
++#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x3
++#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0
++#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0xc
++#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2
++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
++#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
++#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
++#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
++#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xffffffff
++#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
++#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x1
++#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
++#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
++#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
++#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
++#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
++#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xffffffff
++#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
++#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x1
++#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
++#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
++#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
++#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
++#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
++#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xffffffff
++#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
++#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x1
++#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
++#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
++#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
++#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
++#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
++#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xffffffff
++#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
++#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x1
++#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
++#define PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xf
++#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
++#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
++#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst_MASK 0x4
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT 0x2
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x8
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x3
++#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1
++#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0
++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2
++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1
++#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd_MASK 0x4
++#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT 0x2
++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x8
++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x3
++#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1
++#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0
++#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2
++#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1
++#define BIF_PWDN_STATUS__SMBUS_REG_pw_status_MASK 0x4
++#define BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT 0x2
++#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x8
++#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x3
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe
++#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM_MASK 0x20000
++#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM__SHIFT 0x11
++#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1
++#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0
++#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2
++#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8
++#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3
++#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00
++#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8
++#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000
++#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd
++#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000
++#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe
++#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000
++#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf
++#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000
++#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14
++#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000
++#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a
++#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7
++#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0
++#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8
++#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3
++#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10
++#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4
++#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40
++#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6
++#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80
++#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000
++#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000
++#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11
++#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000
++#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000
++#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14
++#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000
++#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c
++#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000
++#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d
++#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7
++#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0
++#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8
++#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000
++#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000
++#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000
++#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14
++#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000
++#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c
++#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7
++#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0
++#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8
++#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000
++#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000
++#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000
++#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14
++#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000
++#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c
++#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff
++#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0
++
++#endif /* BIF_5_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IMC-from-fetching-BIOS-code.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IMC-from-fetching-BIOS-code.patch
new file mode 100644
index 00000000..3fd0e5a4
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IMC-from-fetching-BIOS-code.patch
@@ -0,0 +1,38 @@
+The patch adds support to disable IMC from fetching BIOS code when
+we first open the SMBus device. We can perform SMBus transaction
+safely once IMC is disabled. Then when we close the device after
+the operation, we enable IMC to start fetching from BIOS ROM again.
+
+upstream status: None
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com>
+diff -Naur a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
+--- a/drivers/i2c/i2c-dev.c	2014-03-31 09:10:15.000000000 +0530
++++ b/drivers/i2c/i2c-dev.c	2014-11-17 15:31:14.564077551 +0530
+@@ -39,6 +39,7 @@
+ #include <linux/i2c-dev.h>
+ #include <linux/jiffies.h>
+ #include <linux/uaccess.h>
++#include <linux/amd_imc.h>
+ 
+ /*
+  * An i2c_dev represents an i2c_adapter ... an I2C or SMBus master, not a
+@@ -518,6 +519,8 @@
+ 	client->adapter = adap;
+ 	file->private_data = client;
+ 
++	amd_imc_enter_scratch_ram();
++
+ 	return 0;
+ }
+ 
+@@ -529,6 +532,8 @@
+ 	kfree(client);
+ 	file->private_data = NULL;
+ 
++	amd_imc_exit_scratch_ram();
++
+ 	return 0;
+ }
+ 
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch
new file mode 100644
index 00000000..dc25affe
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch
@@ -0,0 +1,121 @@
+EDAC, MCE, AMD: Add MCE decoding for F15h M60h
+Add decoding logic for new Fam15h model 60h.
+
+Tested using mce_amd_inj module and works fine.
+
+Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com>
+diff -Naur a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
+--- a/drivers/edac/mce_amd.c	2015-03-25 14:39:54.692737985 +0530
++++ b/drivers/edac/mce_amd.c	2015-03-25 14:43:37.872742361 +0530
+@@ -79,7 +79,8 @@
+ 	"uop queue",
+ 	"insn buffer",
+ 	"predecode buffer",
+-	"fetch address FIFO"
++	"fetch address FIFO",
++	"dispatch uop queue"
+ };
+ 
+ static const char * const f15h_mc2_mce_desc[] = {
+@@ -268,6 +269,11 @@
+ 			pr_cont("System Read Data Error.\n");
+ 		else
+ 			pr_cont(" Internal error condition type %d.\n", xec);
++	} else if (INT_ERROR(ec)) {
++		if (xec <= 0x1f)
++			pr_cont("Hardware Assert.\n");
++		else
++			ret = false;
+ 	} else
+ 		ret = false;
+ 
+@@ -374,7 +380,7 @@
+ 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
+ 		break;
+ 
+-	case 0x11 ... 0x14:
++	case 0x11 ... 0x15:
+ 		pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
+ 		break;
+ 
+@@ -398,10 +404,21 @@
+ 		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
+ 
+ 		pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
++	} else if (INT_ERROR(ec)) {
++		if (xec <= 0x3f)
++			pr_cont("Hardware Assert.\n");
++		else
++			goto wrong_mc1_mce;
+ 	} else if (fam_ops->mc1_mce(ec, xec))
+ 		;
+ 	else
+-		pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
++		goto wrong_mc1_mce;
++
++	return;
++
++wrong_mc1_mce:
++	pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
++
+ }
+ 
+ static bool k8_mc2_mce(u16 ec, u8 xec)
+@@ -469,6 +486,12 @@
+ 		default:
+ 			ret = false;
+ 		}
++
++	} else if (INT_ERROR(ec)) {
++		if (xec <= 0x3f)
++			pr_cont("Hardware Assert.\n");
++		else
++			ret = false;
+ 	}
+ 
+ 	return ret;
+@@ -616,6 +639,7 @@
+ static void decode_mc5_mce(struct mce *m)
+ {
+ 	struct cpuinfo_x86 *c = &boot_cpu_data;
++	u16 ec = EC(m->status);
+ 	u8 xec = XEC(m->status, xec_mask);
+ 
+ 	if (c->x86 == 0xf || c->x86 == 0x11)
+@@ -623,6 +647,14 @@
+ 
+ 	pr_emerg(HW_ERR "MC5 Error: ");
+ 
++	if (INT_ERROR(ec)) {
++		if (xec <= 0x1f) {
++			pr_cont("Hardware Assert.\n");
++			return;
++		} else
++			goto wrong_mc5_mce;
++	}
++
+ 	if (xec == 0x0 || xec == 0xc)
+ 		pr_cont("%s.\n", mc5_mce_desc[xec]);
+ 	else if (xec <= 0xd)
+@@ -643,6 +675,10 @@
+ 	pr_emerg(HW_ERR "MC6 Error: ");
+ 
+ 	switch (xec) {
++	case 0x0:
++		pr_cont("Hardware Assertion");
++		break;
++
+ 	case 0x1:
+ 		pr_cont("Free List");
+ 		break;
+@@ -858,7 +894,7 @@
+ 		break;
+ 
+ 	case 0x15:
+-		xec_mask = 0x1f;
++		xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;
+ 		fam_ops->mc0_mce = f15h_mc0_mce;
+ 		fam_ops->mc1_mce = f15h_mc1_mce;
+ 		fam_ops->mc2_mce = f15h_mc2_mce;
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch
new file mode 100644
index 00000000..e066809d
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch
@@ -0,0 +1,37757 @@
+From 00f68a4d67bf0cb36586416022e251f300d6938e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:16:08 -0400
+Subject: drm/amdgpu: add BIF 5.1 register headers
+
+These are register headers for the BIF (Bus InterFace) block on
+the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h
+new file mode 100644
+index 0000000..b52c9aa
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h
+@@ -0,0 +1,3577 @@
++/*
++ * BIF_5_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_5_1_D_H
++#define BIF_5_1_D_H
++
++#define mmMM_INDEX                                                              0x0
++#define mmMM_INDEX_HI                                                           0x6
++#define mmMM_DATA                                                               0x1
++#define mmBIF_MM_INDACCESS_CNTL                                                 0x1500
++#define mmBUS_CNTL                                                              0x1508
++#define mmCONFIG_CNTL                                                           0x1509
++#define mmCONFIG_MEMSIZE                                                        0x150a
++#define mmCONFIG_F0_BASE                                                        0x150b
++#define mmCONFIG_APER_SIZE                                                      0x150c
++#define mmCONFIG_REG_APER_SIZE                                                  0x150d
++#define mmBIF_SCRATCH0                                                          0x150e
++#define mmBIF_SCRATCH1                                                          0x150f
++#define mmBX_RESET_EN                                                           0x1514
++#define mmMM_CFGREGS_CNTL                                                       0x1513
++#define mmHW_DEBUG                                                              0x1515
++#define mmMASTER_CREDIT_CNTL                                                    0x1516
++#define mmSLAVE_REQ_CREDIT_CNTL                                                 0x1517
++#define mmBX_RESET_CNTL                                                         0x1518
++#define mmINTERRUPT_CNTL                                                        0x151a
++#define mmINTERRUPT_CNTL2                                                       0x151b
++#define mmBIF_DEBUG_CNTL                                                        0x151c
++#define mmBIF_DEBUG_MUX                                                         0x151d
++#define mmBIF_DEBUG_OUT                                                         0x151e
++#define mmHDP_REG_COHERENCY_FLUSH_CNTL                                          0x1528
++#define mmHDP_MEM_COHERENCY_FLUSH_CNTL                                          0x1520
++#define mmCLKREQB_PAD_CNTL                                                      0x1521
++#define mmSMBDAT_PAD_CNTL                                                       0x1522
++#define mmSMBCLK_PAD_CNTL                                                       0x1523
++#define mmBIF_XDMA_LO                                                           0x14c0
++#define mmBIF_XDMA_HI                                                           0x14c1
++#define mmBIF_FEATURES_CONTROL_MISC                                             0x14c2
++#define mmBIF_DOORBELL_CNTL                                                     0x14c3
++#define mmBIF_SLVARB_MODE                                                       0x14c4
++#define mmBIF_FB_EN                                                             0x1524
++#define mmBIF_BUSNUM_CNTL1                                                      0x1525
++#define mmBIF_BUSNUM_LIST0                                                      0x1526
++#define mmBIF_BUSNUM_LIST1                                                      0x1527
++#define mmBIF_BUSNUM_CNTL2                                                      0x152b
++#define mmBIF_BUSY_DELAY_CNTR                                                   0x1529
++#define mmBIF_PERFMON_CNTL                                                      0x152c
++#define mmBIF_PERFCOUNTER0_RESULT                                               0x152d
++#define mmBIF_PERFCOUNTER1_RESULT                                               0x152e
++#define mmSLAVE_HANG_PROTECTION_CNTL                                            0x1536
++#define mmGPU_HDP_FLUSH_REQ                                                     0x1537
++#define mmGPU_HDP_FLUSH_DONE                                                    0x1538
++#define mmSLAVE_HANG_ERROR                                                      0x153b
++#define mmCAPTURE_HOST_BUSNUM                                                   0x153c
++#define mmHOST_BUSNUM                                                           0x153d
++#define mmPEER_REG_RANGE0                                                       0x153e
++#define mmPEER_REG_RANGE1                                                       0x153f
++#define mmPEER0_FB_OFFSET_HI                                                    0x14f3
++#define mmPEER0_FB_OFFSET_LO                                                    0x14f2
++#define mmPEER1_FB_OFFSET_HI                                                    0x14f1
++#define mmPEER1_FB_OFFSET_LO                                                    0x14f0
++#define mmPEER2_FB_OFFSET_HI                                                    0x14ef
++#define mmPEER2_FB_OFFSET_LO                                                    0x14ee
++#define mmPEER3_FB_OFFSET_HI                                                    0x14ed
++#define mmPEER3_FB_OFFSET_LO                                                    0x14ec
++#define mmDBG_BYPASS_SRBM_ACCESS                                                0x14eb
++#define mmSMBUS_BACO_DUMMY                                                      0x14c6
++#define mmBIF_DEVFUNCNUM_LIST0                                                  0x14e8
++#define mmBIF_DEVFUNCNUM_LIST1                                                  0x14e7
++#define mmBACO_CNTL                                                             0x14e5
++#define mmBF_ANA_ISO_CNTL                                                       0x14c7
++#define mmMEM_TYPE_CNTL                                                         0x14e4
++#define mmBIF_BACO_DEBUG                                                        0x14df
++#define mmBIF_BACO_DEBUG_LATCH                                                  0x14dc
++#define mmBACO_CNTL_MISC                                                        0x14db
++#define mmSMU_BIF_VDDGFX_PWR_STATUS                                             0x14f8
++#define mmBIF_VDDGFX_GFX0_LOWER                                                 0x1428
++#define mmBIF_VDDGFX_GFX0_UPPER                                                 0x1429
++#define mmBIF_VDDGFX_GFX1_LOWER                                                 0x142a
++#define mmBIF_VDDGFX_GFX1_UPPER                                                 0x142b
++#define mmBIF_VDDGFX_GFX2_LOWER                                                 0x142c
++#define mmBIF_VDDGFX_GFX2_UPPER                                                 0x142d
++#define mmBIF_VDDGFX_GFX3_LOWER                                                 0x142e
++#define mmBIF_VDDGFX_GFX3_UPPER                                                 0x142f
++#define mmBIF_VDDGFX_GFX4_LOWER                                                 0x1430
++#define mmBIF_VDDGFX_GFX4_UPPER                                                 0x1431
++#define mmBIF_VDDGFX_GFX5_LOWER                                                 0x1432
++#define mmBIF_VDDGFX_GFX5_UPPER                                                 0x1433
++#define mmBIF_VDDGFX_RSV1_LOWER                                                 0x1434
++#define mmBIF_VDDGFX_RSV1_UPPER                                                 0x1435
++#define mmBIF_VDDGFX_RSV2_LOWER                                                 0x1436
++#define mmBIF_VDDGFX_RSV2_UPPER                                                 0x1437
++#define mmBIF_VDDGFX_RSV3_LOWER                                                 0x1438
++#define mmBIF_VDDGFX_RSV3_UPPER                                                 0x1439
++#define mmBIF_VDDGFX_RSV4_LOWER                                                 0x143a
++#define mmBIF_VDDGFX_RSV4_UPPER                                                 0x143b
++#define mmBIF_VDDGFX_FB_CMP                                                     0x143c
++#define mmBIF_DOORBELL_GBLAPER1_LOWER                                           0x14fc
++#define mmBIF_DOORBELL_GBLAPER1_UPPER                                           0x14fd
++#define mmBIF_DOORBELL_GBLAPER2_LOWER                                           0x14fe
++#define mmBIF_DOORBELL_GBLAPER2_UPPER                                           0x14ff
++#define mmBIF_SMU_INDEX                                                         0x143d
++#define mmBIF_SMU_DATA                                                          0x143e
++#define mmIMPCTL_RESET                                                          0x14f5
++#define mmGARLIC_FLUSH_CNTL                                                     0x1401
++#define mmGARLIC_FLUSH_ADDR_START_0                                             0x1402
++#define mmGARLIC_FLUSH_ADDR_START_1                                             0x1404
++#define mmGARLIC_FLUSH_ADDR_START_2                                             0x1406
++#define mmGARLIC_FLUSH_ADDR_START_3                                             0x1408
++#define mmGARLIC_FLUSH_ADDR_START_4                                             0x140a
++#define mmGARLIC_FLUSH_ADDR_START_5                                             0x140c
++#define mmGARLIC_FLUSH_ADDR_START_6                                             0x140e
++#define mmGARLIC_FLUSH_ADDR_START_7                                             0x1410
++#define mmGARLIC_FLUSH_ADDR_END_0                                               0x1403
++#define mmGARLIC_FLUSH_ADDR_END_1                                               0x1405
++#define mmGARLIC_FLUSH_ADDR_END_2                                               0x1407
++#define mmGARLIC_FLUSH_ADDR_END_3                                               0x1409
++#define mmGARLIC_FLUSH_ADDR_END_4                                               0x140b
++#define mmGARLIC_FLUSH_ADDR_END_5                                               0x140d
++#define mmGARLIC_FLUSH_ADDR_END_6                                               0x140f
++#define mmGARLIC_FLUSH_ADDR_END_7                                               0x1411
++#define mmGARLIC_FLUSH_REQ                                                      0x1412
++#define mmGPU_GARLIC_FLUSH_REQ                                                  0x1413
++#define mmGPU_GARLIC_FLUSH_DONE                                                 0x1414
++#define mmGARLIC_COHE_CP_RB0_WPTR                                               0x1415
++#define mmGARLIC_COHE_CP_RB1_WPTR                                               0x1416
++#define mmGARLIC_COHE_CP_RB2_WPTR                                               0x1417
++#define mmGARLIC_COHE_UVD_RBC_RB_WPTR                                           0x1418
++#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR                                         0x1419
++#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR                                         0x141a
++#define mmGARLIC_COHE_CP_DMA_ME_COMMAND                                         0x141b
++#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND                                        0x141c
++#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR                                          0x141d
++#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR                                          0x141e
++#define mmGARLIC_COHE_VCE_OUT_RB_WPTR                                           0x141f
++#define mmGARLIC_COHE_VCE_RB_WPTR2                                              0x1420
++#define mmGARLIC_COHE_VCE_RB_WPTR                                               0x1421
++#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR                                         0x1422
++#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR                                         0x1423
++#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND                                        0x1424
++#define mmGARLIC_COHE_GARLIC_FLUSH_REQ                                          0x1425
++#define mmREMAP_HDP_MEM_FLUSH_CNTL                                              0x1426
++#define mmREMAP_HDP_REG_FLUSH_CNTL                                              0x1427
++#define mmBIOS_SCRATCH_0                                                        0x5c9
++#define mmBIOS_SCRATCH_1                                                        0x5ca
++#define mmBIOS_SCRATCH_2                                                        0x5cb
++#define mmBIOS_SCRATCH_3                                                        0x5cc
++#define mmBIOS_SCRATCH_4                                                        0x5cd
++#define mmBIOS_SCRATCH_5                                                        0x5ce
++#define mmBIOS_SCRATCH_6                                                        0x5cf
++#define mmBIOS_SCRATCH_7                                                        0x5d0
++#define mmBIOS_SCRATCH_8                                                        0x5d1
++#define mmBIOS_SCRATCH_9                                                        0x5d2
++#define mmBIOS_SCRATCH_10                                                       0x5d3
++#define mmBIOS_SCRATCH_11                                                       0x5d4
++#define mmBIOS_SCRATCH_12                                                       0x5d5
++#define mmBIOS_SCRATCH_13                                                       0x5d6
++#define mmBIOS_SCRATCH_14                                                       0x5d7
++#define mmBIOS_SCRATCH_15                                                       0x5d8
++#define mmBIF_RB_CNTL                                                           0x1530
++#define mmBIF_RB_BASE                                                           0x1531
++#define mmBIF_RB_RPTR                                                           0x1532
++#define mmBIF_RB_WPTR                                                           0x1533
++#define mmBIF_RB_WPTR_ADDR_HI                                                   0x1534
++#define mmBIF_RB_WPTR_ADDR_LO                                                   0x1535
++#define mmVENDOR_ID                                                             0x0
++#define mmDEVICE_ID                                                             0x0
++#define mmCOMMAND                                                               0x1
++#define mmSTATUS                                                                0x1
++#define mmREVISION_ID                                                           0x2
++#define mmPROG_INTERFACE                                                        0x2
++#define mmSUB_CLASS                                                             0x2
++#define mmBASE_CLASS                                                            0x2
++#define mmCACHE_LINE                                                            0x3
++#define mmLATENCY                                                               0x3
++#define mmHEADER                                                                0x3
++#define mmBIST                                                                  0x3
++#define mmBASE_ADDR_1                                                           0x4
++#define mmBASE_ADDR_2                                                           0x5
++#define mmBASE_ADDR_3                                                           0x6
++#define mmBASE_ADDR_4                                                           0x7
++#define mmBASE_ADDR_5                                                           0x8
++#define mmBASE_ADDR_6                                                           0x9
++#define mmROM_BASE_ADDR                                                         0xc
++#define mmCAP_PTR                                                               0xd
++#define mmINTERRUPT_LINE                                                        0xf
++#define mmINTERRUPT_PIN                                                         0xf
++#define mmADAPTER_ID                                                            0xb
++#define mmMIN_GRANT                                                             0xf
++#define mmMAX_LATENCY                                                           0xf
++#define mmVENDOR_CAP_LIST                                                       0x12
++#define mmADAPTER_ID_W                                                          0x13
++#define mmPMI_CAP_LIST                                                          0x14
++#define mmPMI_CAP                                                               0x14
++#define mmPMI_STATUS_CNTL                                                       0x15
++#define mmPCIE_CAP_LIST                                                         0x16
++#define mmPCIE_CAP                                                              0x16
++#define mmDEVICE_CAP                                                            0x17
++#define mmDEVICE_CNTL                                                           0x18
++#define mmDEVICE_STATUS                                                         0x18
++#define mmLINK_CAP                                                              0x19
++#define mmLINK_CNTL                                                             0x1a
++#define mmLINK_STATUS                                                           0x1a
++#define mmDEVICE_CAP2                                                           0x1f
++#define mmDEVICE_CNTL2                                                          0x20
++#define mmDEVICE_STATUS2                                                        0x20
++#define mmLINK_CAP2                                                             0x21
++#define mmLINK_CNTL2                                                            0x22
++#define mmLINK_STATUS2                                                          0x22
++#define mmMSI_CAP_LIST                                                          0x28
++#define mmMSI_MSG_CNTL                                                          0x28
++#define mmMSI_MSG_ADDR_LO                                                       0x29
++#define mmMSI_MSG_ADDR_HI                                                       0x2a
++#define mmMSI_MSG_DATA_64                                                       0x2b
++#define mmMSI_MSG_DATA                                                          0x2a
++#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                     0x40
++#define mmPCIE_VENDOR_SPECIFIC_HDR                                              0x41
++#define mmPCIE_VENDOR_SPECIFIC1                                                 0x42
++#define mmPCIE_VENDOR_SPECIFIC2                                                 0x43
++#define mmPCIE_VC_ENH_CAP_LIST                                                  0x44
++#define mmPCIE_PORT_VC_CAP_REG1                                                 0x45
++#define mmPCIE_PORT_VC_CAP_REG2                                                 0x46
++#define mmPCIE_PORT_VC_CNTL                                                     0x47
++#define mmPCIE_PORT_VC_STATUS                                                   0x47
++#define mmPCIE_VC0_RESOURCE_CAP                                                 0x48
++#define mmPCIE_VC0_RESOURCE_CNTL                                                0x49
++#define mmPCIE_VC0_RESOURCE_STATUS                                              0x4a
++#define mmPCIE_VC1_RESOURCE_CAP                                                 0x4b
++#define mmPCIE_VC1_RESOURCE_CNTL                                                0x4c
++#define mmPCIE_VC1_RESOURCE_STATUS                                              0x4d
++#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                      0x50
++#define mmPCIE_DEV_SERIAL_NUM_DW1                                               0x51
++#define mmPCIE_DEV_SERIAL_NUM_DW2                                               0x52
++#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST                                         0x54
++#define mmPCIE_UNCORR_ERR_STATUS                                                0x55
++#define mmPCIE_UNCORR_ERR_MASK                                                  0x56
++#define mmPCIE_UNCORR_ERR_SEVERITY                                              0x57
++#define mmPCIE_CORR_ERR_STATUS                                                  0x58
++#define mmPCIE_CORR_ERR_MASK                                                    0x59
++#define mmPCIE_ADV_ERR_CAP_CNTL                                                 0x5a
++#define mmPCIE_HDR_LOG0                                                         0x5b
++#define mmPCIE_HDR_LOG1                                                         0x5c
++#define mmPCIE_HDR_LOG2                                                         0x5d
++#define mmPCIE_HDR_LOG3                                                         0x5e
++#define mmPCIE_TLP_PREFIX_LOG0                                                  0x62
++#define mmPCIE_TLP_PREFIX_LOG1                                                  0x63
++#define mmPCIE_TLP_PREFIX_LOG2                                                  0x64
++#define mmPCIE_TLP_PREFIX_LOG3                                                  0x65
++#define mmPCIE_BAR_ENH_CAP_LIST                                                 0x80
++#define mmPCIE_BAR1_CAP                                                         0x81
++#define mmPCIE_BAR1_CNTL                                                        0x82
++#define mmPCIE_BAR2_CAP                                                         0x83
++#define mmPCIE_BAR2_CNTL                                                        0x84
++#define mmPCIE_BAR3_CAP                                                         0x85
++#define mmPCIE_BAR3_CNTL                                                        0x86
++#define mmPCIE_BAR4_CAP                                                         0x87
++#define mmPCIE_BAR4_CNTL                                                        0x88
++#define mmPCIE_BAR5_CAP                                                         0x89
++#define mmPCIE_BAR5_CNTL                                                        0x8a
++#define mmPCIE_BAR6_CAP                                                         0x8b
++#define mmPCIE_BAR6_CNTL                                                        0x8c
++#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST                                          0x90
++#define mmPCIE_PWR_BUDGET_DATA_SELECT                                           0x91
++#define mmPCIE_PWR_BUDGET_DATA                                                  0x92
++#define mmPCIE_PWR_BUDGET_CAP                                                   0x93
++#define mmPCIE_DPA_ENH_CAP_LIST                                                 0x94
++#define mmPCIE_DPA_CAP                                                          0x95
++#define mmPCIE_DPA_LATENCY_INDICATOR                                            0x96
++#define mmPCIE_DPA_STATUS                                                       0x97
++#define mmPCIE_DPA_CNTL                                                         0x97
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                         0x98
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                         0x99
++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                         0x99
++#define mmPCIE_SECONDARY_ENH_CAP_LIST                                           0x9c
++#define mmPCIE_LINK_CNTL3                                                       0x9d
++#define mmPCIE_LANE_ERROR_STATUS                                                0x9e
++#define mmPCIE_LANE_0_EQUALIZATION_CNTL                                         0x9f
++#define mmPCIE_LANE_1_EQUALIZATION_CNTL                                         0x9f
++#define mmPCIE_LANE_2_EQUALIZATION_CNTL                                         0xa0
++#define mmPCIE_LANE_3_EQUALIZATION_CNTL                                         0xa0
++#define mmPCIE_LANE_4_EQUALIZATION_CNTL                                         0xa1
++#define mmPCIE_LANE_5_EQUALIZATION_CNTL                                         0xa1
++#define mmPCIE_LANE_6_EQUALIZATION_CNTL                                         0xa2
++#define mmPCIE_LANE_7_EQUALIZATION_CNTL                                         0xa2
++#define mmPCIE_LANE_8_EQUALIZATION_CNTL                                         0xa3
++#define mmPCIE_LANE_9_EQUALIZATION_CNTL                                         0xa3
++#define mmPCIE_LANE_10_EQUALIZATION_CNTL                                        0xa4
++#define mmPCIE_LANE_11_EQUALIZATION_CNTL                                        0xa4
++#define mmPCIE_LANE_12_EQUALIZATION_CNTL                                        0xa5
++#define mmPCIE_LANE_13_EQUALIZATION_CNTL                                        0xa5
++#define mmPCIE_LANE_14_EQUALIZATION_CNTL                                        0xa6
++#define mmPCIE_LANE_15_EQUALIZATION_CNTL                                        0xa6
++#define mmPCIE_ACS_ENH_CAP_LIST                                                 0xa8
++#define mmPCIE_ACS_CAP                                                          0xa9
++#define mmPCIE_ACS_CNTL                                                         0xa9
++#define mmPCIE_ATS_ENH_CAP_LIST                                                 0xac
++#define mmPCIE_ATS_CAP                                                          0xad
++#define mmPCIE_ATS_CNTL                                                         0xad
++#define mmPCIE_PAGE_REQ_ENH_CAP_LIST                                            0xb0
++#define mmPCIE_PAGE_REQ_CNTL                                                    0xb1
++#define mmPCIE_PAGE_REQ_STATUS                                                  0xb1
++#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                       0xb2
++#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC                                          0xb3
++#define mmPCIE_PASID_ENH_CAP_LIST                                               0xb4
++#define mmPCIE_PASID_CAP                                                        0xb5
++#define mmPCIE_PASID_CNTL                                                       0xb5
++#define mmPCIE_TPH_REQR_ENH_CAP_LIST                                            0xb8
++#define mmPCIE_TPH_REQR_CAP                                                     0xb9
++#define mmPCIE_TPH_REQR_CNTL                                                    0xba
++#define mmPCIE_MC_ENH_CAP_LIST                                                  0xbc
++#define mmPCIE_MC_CAP                                                           0xbd
++#define mmPCIE_MC_CNTL                                                          0xbd
++#define mmPCIE_MC_ADDR0                                                         0xbe
++#define mmPCIE_MC_ADDR1                                                         0xbf
++#define mmPCIE_MC_RCV0                                                          0xc0
++#define mmPCIE_MC_RCV1                                                          0xc1
++#define mmPCIE_MC_BLOCK_ALL0                                                    0xc2
++#define mmPCIE_MC_BLOCK_ALL1                                                    0xc3
++#define mmPCIE_MC_BLOCK_UNTRANSLATED_0                                          0xc4
++#define mmPCIE_MC_BLOCK_UNTRANSLATED_1                                          0xc5
++#define mmPCIE_LTR_ENH_CAP_LIST                                                 0xc8
++#define mmPCIE_LTR_CAP                                                          0xc9
++#define ixMM_INDEX_IND                                                          0x1090000
++#define ixMM_INDEX_HI_IND                                                       0x1090006
++#define ixMM_DATA_IND                                                           0x1090001
++#define ixBIF_MM_INDACCESS_CNTL_IND                                             0x1091500
++#define ixBUS_CNTL_IND                                                          0x1091508
++#define ixCONFIG_CNTL_IND                                                       0x1091509
++#define ixCONFIG_MEMSIZE_IND                                                    0x109150a
++#define ixCONFIG_F0_BASE_IND                                                    0x109150b
++#define ixCONFIG_APER_SIZE_IND                                                  0x109150c
++#define ixCONFIG_REG_APER_SIZE_IND                                              0x109150d
++#define ixBIF_SCRATCH0_IND                                                      0x109150e
++#define ixBIF_SCRATCH1_IND                                                      0x109150f
++#define ixBX_RESET_EN_IND                                                       0x1091514
++#define ixMM_CFGREGS_CNTL_IND                                                   0x1091513
++#define ixHW_DEBUG_IND                                                          0x1091515
++#define ixMASTER_CREDIT_CNTL_IND                                                0x1091516
++#define ixSLAVE_REQ_CREDIT_CNTL_IND                                             0x1091517
++#define ixBX_RESET_CNTL_IND                                                     0x1091518
++#define ixINTERRUPT_CNTL_IND                                                    0x109151a
++#define ixINTERRUPT_CNTL2_IND                                                   0x109151b
++#define ixBIF_DEBUG_CNTL_IND                                                    0x109151c
++#define ixBIF_DEBUG_MUX_IND                                                     0x109151d
++#define ixBIF_DEBUG_OUT_IND                                                     0x109151e
++#define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND                                      0x1091528
++#define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND                                      0x1091520
++#define ixCLKREQB_PAD_CNTL_IND                                                  0x1091521
++#define ixSMBDAT_PAD_CNTL_IND                                                   0x1091522
++#define ixSMBCLK_PAD_CNTL_IND                                                   0x1091523
++#define ixBIF_XDMA_LO_IND                                                       0x10914c0
++#define ixBIF_XDMA_HI_IND                                                       0x10914c1
++#define ixBIF_FEATURES_CONTROL_MISC_IND                                         0x10914c2
++#define ixBIF_DOORBELL_CNTL_IND                                                 0x10914c3
++#define ixBIF_SLVARB_MODE_IND                                                   0x10914c4
++#define ixBIF_FB_EN_IND                                                         0x1091524
++#define ixBIF_BUSNUM_CNTL1_IND                                                  0x1091525
++#define ixBIF_BUSNUM_LIST0_IND                                                  0x1091526
++#define ixBIF_BUSNUM_LIST1_IND                                                  0x1091527
++#define ixBIF_BUSNUM_CNTL2_IND                                                  0x109152b
++#define ixBIF_BUSY_DELAY_CNTR_IND                                               0x1091529
++#define ixBIF_PERFMON_CNTL_IND                                                  0x109152c
++#define ixBIF_PERFCOUNTER0_RESULT_IND                                           0x109152d
++#define ixBIF_PERFCOUNTER1_RESULT_IND                                           0x109152e
++#define ixSLAVE_HANG_PROTECTION_CNTL_IND                                        0x1091536
++#define ixGPU_HDP_FLUSH_REQ_IND                                                 0x1091537
++#define ixGPU_HDP_FLUSH_DONE_IND                                                0x1091538
++#define ixSLAVE_HANG_ERROR_IND                                                  0x109153b
++#define ixCAPTURE_HOST_BUSNUM_IND                                               0x109153c
++#define ixHOST_BUSNUM_IND                                                       0x109153d
++#define ixPEER_REG_RANGE0_IND                                                   0x109153e
++#define ixPEER_REG_RANGE1_IND                                                   0x109153f
++#define ixPEER0_FB_OFFSET_HI_IND                                                0x10914f3
++#define ixPEER0_FB_OFFSET_LO_IND                                                0x10914f2
++#define ixPEER1_FB_OFFSET_HI_IND                                                0x10914f1
++#define ixPEER1_FB_OFFSET_LO_IND                                                0x10914f0
++#define ixPEER2_FB_OFFSET_HI_IND                                                0x10914ef
++#define ixPEER2_FB_OFFSET_LO_IND                                                0x10914ee
++#define ixPEER3_FB_OFFSET_HI_IND                                                0x10914ed
++#define ixPEER3_FB_OFFSET_LO_IND                                                0x10914ec
++#define ixDBG_BYPASS_SRBM_ACCESS_IND                                            0x10914eb
++#define ixSMBUS_BACO_DUMMY_IND                                                  0x10914c6
++#define ixBIF_DEVFUNCNUM_LIST0_IND                                              0x10914e8
++#define ixBIF_DEVFUNCNUM_LIST1_IND                                              0x10914e7
++#define ixBACO_CNTL_IND                                                         0x10914e5
++#define ixBF_ANA_ISO_CNTL_IND                                                   0x10914c7
++#define ixMEM_TYPE_CNTL_IND                                                     0x10914e4
++#define ixBIF_BACO_DEBUG_IND                                                    0x10914df
++#define ixBIF_BACO_DEBUG_LATCH_IND                                              0x10914dc
++#define ixBACO_CNTL_MISC_IND                                                    0x10914db
++#define ixSMU_BIF_VDDGFX_PWR_STATUS_IND                                         0x10914f8
++#define ixBIF_VDDGFX_GFX0_LOWER_IND                                             0x1091428
++#define ixBIF_VDDGFX_GFX0_UPPER_IND                                             0x1091429
++#define ixBIF_VDDGFX_GFX1_LOWER_IND                                             0x109142a
++#define ixBIF_VDDGFX_GFX1_UPPER_IND                                             0x109142b
++#define ixBIF_VDDGFX_GFX2_LOWER_IND                                             0x109142c
++#define ixBIF_VDDGFX_GFX2_UPPER_IND                                             0x109142d
++#define ixBIF_VDDGFX_GFX3_LOWER_IND                                             0x109142e
++#define ixBIF_VDDGFX_GFX3_UPPER_IND                                             0x109142f
++#define ixBIF_VDDGFX_GFX4_LOWER_IND                                             0x1091430
++#define ixBIF_VDDGFX_GFX4_UPPER_IND                                             0x1091431
++#define ixBIF_VDDGFX_GFX5_LOWER_IND                                             0x1091432
++#define ixBIF_VDDGFX_GFX5_UPPER_IND                                             0x1091433
++#define ixBIF_VDDGFX_RSV1_LOWER_IND                                             0x1091434
++#define ixBIF_VDDGFX_RSV1_UPPER_IND                                             0x1091435
++#define ixBIF_VDDGFX_RSV2_LOWER_IND                                             0x1091436
++#define ixBIF_VDDGFX_RSV2_UPPER_IND                                             0x1091437
++#define ixBIF_VDDGFX_RSV3_LOWER_IND                                             0x1091438
++#define ixBIF_VDDGFX_RSV3_UPPER_IND                                             0x1091439
++#define ixBIF_VDDGFX_RSV4_LOWER_IND                                             0x109143a
++#define ixBIF_VDDGFX_RSV4_UPPER_IND                                             0x109143b
++#define ixBIF_VDDGFX_FB_CMP_IND                                                 0x109143c
++#define ixBIF_DOORBELL_GBLAPER1_LOWER_IND                                       0x10914fc
++#define ixBIF_DOORBELL_GBLAPER1_UPPER_IND                                       0x10914fd
++#define ixBIF_DOORBELL_GBLAPER2_LOWER_IND                                       0x10914fe
++#define ixBIF_DOORBELL_GBLAPER2_UPPER_IND                                       0x10914ff
++#define ixBIF_SMU_INDEX_IND                                                     0x109143d
++#define ixBIF_SMU_DATA_IND                                                      0x109143e
++#define ixIMPCTL_RESET_IND                                                      0x10914f5
++#define ixGARLIC_FLUSH_CNTL_IND                                                 0x1091401
++#define ixGARLIC_FLUSH_REQ_IND                                                  0x1091412
++#define ixGPU_GARLIC_FLUSH_REQ_IND                                              0x1091413
++#define ixGPU_GARLIC_FLUSH_DONE_IND                                             0x1091414
++#define ixGARLIC_COHE_CP_RB0_WPTR_IND                                           0x1091415
++#define ixGARLIC_COHE_CP_RB1_WPTR_IND                                           0x1091416
++#define ixGARLIC_COHE_CP_RB2_WPTR_IND                                           0x1091417
++#define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND                                       0x1091418
++#define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND                                     0x1091419
++#define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND                                     0x109141a
++#define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND                                     0x109141b
++#define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND                                    0x109141c
++#define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND                                      0x109141d
++#define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND                                      0x109141e
++#define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND                                       0x109141f
++#define ixGARLIC_COHE_VCE_RB_WPTR2_IND                                          0x1091420
++#define ixGARLIC_COHE_VCE_RB_WPTR_IND                                           0x1091421
++#define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND                                     0x1091422
++#define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND                                     0x1091423
++#define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND                                    0x1091424
++#define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND                                      0x1091425
++#define ixREMAP_HDP_MEM_FLUSH_CNTL_IND                                          0x1091426
++#define ixREMAP_HDP_REG_FLUSH_CNTL_IND                                          0x1091427
++#define ixBIOS_SCRATCH_0_IND                                                    0x10905c9
++#define ixBIOS_SCRATCH_1_IND                                                    0x10905ca
++#define ixBIOS_SCRATCH_2_IND                                                    0x10905cb
++#define ixBIOS_SCRATCH_3_IND                                                    0x10905cc
++#define ixBIOS_SCRATCH_4_IND                                                    0x10905cd
++#define ixBIOS_SCRATCH_5_IND                                                    0x10905ce
++#define ixBIOS_SCRATCH_6_IND                                                    0x10905cf
++#define ixBIOS_SCRATCH_7_IND                                                    0x10905d0
++#define ixBIOS_SCRATCH_8_IND                                                    0x10905d1
++#define ixBIOS_SCRATCH_9_IND                                                    0x10905d2
++#define ixBIOS_SCRATCH_10_IND                                                   0x10905d3
++#define ixBIOS_SCRATCH_11_IND                                                   0x10905d4
++#define ixBIOS_SCRATCH_12_IND                                                   0x10905d5
++#define ixBIOS_SCRATCH_13_IND                                                   0x10905d6
++#define ixBIOS_SCRATCH_14_IND                                                   0x10905d7
++#define ixBIOS_SCRATCH_15_IND                                                   0x10905d8
++#define ixBIF_RB_CNTL_IND                                                       0x1091530
++#define ixBIF_RB_BASE_IND                                                       0x1091531
++#define ixBIF_RB_RPTR_IND                                                       0x1091532
++#define ixBIF_RB_WPTR_IND                                                       0x1091533
++#define ixBIF_RB_WPTR_ADDR_HI_IND                                               0x1091534
++#define ixBIF_RB_WPTR_ADDR_LO_IND                                               0x1091535
++#define mmNB_GBIF_INDEX                                                         0x34
++#define mmNB_GBIF_DATA                                                          0x35
++#define mmPCIE_INDEX                                                            0xe
++#define mmPCIE_DATA                                                             0xf
++#define mmPCIE_INDEX_2                                                          0xc
++#define mmPCIE_DATA_2                                                           0xd
++#define ixPCIE_RESERVED                                                         0x1400000
++#define ixPCIE_SCRATCH                                                          0x1400001
++#define ixPCIE_HW_DEBUG                                                         0x1400002
++#define ixPCIE_RX_NUM_NAK                                                       0x140000e
++#define ixPCIE_RX_NUM_NAK_GENERATED                                             0x140000f
++#define ixPCIE_CNTL                                                             0x1400010
++#define ixPCIE_CONFIG_CNTL                                                      0x1400011
++#define ixPCIE_DEBUG_CNTL                                                       0x1400012
++#define ixPCIE_INT_CNTL                                                         0x140001a
++#define ixPCIE_INT_STATUS                                                       0x140001b
++#define ixPCIE_CNTL2                                                            0x140001c
++#define ixPCIE_RX_CNTL2                                                         0x140001d
++#define ixPCIE_TX_F0_ATTR_CNTL                                                  0x140001e
++#define ixPCIE_TX_F1_F2_ATTR_CNTL                                               0x140001f
++#define ixPCIE_CI_CNTL                                                          0x1400020
++#define ixPCIE_BUS_CNTL                                                         0x1400021
++#define ixPCIE_LC_STATE6                                                        0x1400022
++#define ixPCIE_LC_STATE7                                                        0x1400023
++#define ixPCIE_LC_STATE8                                                        0x1400024
++#define ixPCIE_LC_STATE9                                                        0x1400025
++#define ixPCIE_LC_STATE10                                                       0x1400026
++#define ixPCIE_LC_STATE11                                                       0x1400027
++#define ixPCIE_LC_STATUS1                                                       0x1400028
++#define ixPCIE_LC_STATUS2                                                       0x1400029
++#define ixPCIE_WPR_CNTL                                                         0x1400030
++#define ixPCIE_RX_LAST_TLP0                                                     0x1400031
++#define ixPCIE_RX_LAST_TLP1                                                     0x1400032
++#define ixPCIE_RX_LAST_TLP2                                                     0x1400033
++#define ixPCIE_RX_LAST_TLP3                                                     0x1400034
++#define ixPCIE_TX_LAST_TLP0                                                     0x1400035
++#define ixPCIE_TX_LAST_TLP1                                                     0x1400036
++#define ixPCIE_TX_LAST_TLP2                                                     0x1400037
++#define ixPCIE_TX_LAST_TLP3                                                     0x1400038
++#define ixPCIE_I2C_REG_ADDR_EXPAND                                              0x140003a
++#define ixPCIE_I2C_REG_DATA                                                     0x140003b
++#define ixPCIE_CFG_CNTL                                                         0x140003c
++#define ixPCIE_P_CNTL                                                           0x1400040
++#define ixPCIE_P_BUF_STATUS                                                     0x1400041
++#define ixPCIE_P_DECODER_STATUS                                                 0x1400042
++#define ixPCIE_P_MISC_STATUS                                                    0x1400043
++#define ixPCIE_P_RCV_L0S_FTS_DET                                                0x1400050
++#define ixPCIE_OBFF_CNTL                                                        0x1400061
++#define ixPCIE_TX_LTR_CNTL                                                      0x1400060
++#define ixPCIE_PERF_COUNT_CNTL                                                  0x1400080
++#define ixPCIE_PERF_CNTL_TXCLK                                                  0x1400081
++#define ixPCIE_PERF_COUNT0_TXCLK                                                0x1400082
++#define ixPCIE_PERF_COUNT1_TXCLK                                                0x1400083
++#define ixPCIE_PERF_CNTL_MST_R_CLK                                              0x1400084
++#define ixPCIE_PERF_COUNT0_MST_R_CLK                                            0x1400085
++#define ixPCIE_PERF_COUNT1_MST_R_CLK                                            0x1400086
++#define ixPCIE_PERF_CNTL_MST_C_CLK                                              0x1400087
++#define ixPCIE_PERF_COUNT0_MST_C_CLK                                            0x1400088
++#define ixPCIE_PERF_COUNT1_MST_C_CLK                                            0x1400089
++#define ixPCIE_PERF_CNTL_SLV_R_CLK                                              0x140008a
++#define ixPCIE_PERF_COUNT0_SLV_R_CLK                                            0x140008b
++#define ixPCIE_PERF_COUNT1_SLV_R_CLK                                            0x140008c
++#define ixPCIE_PERF_CNTL_SLV_S_C_CLK                                            0x140008d
++#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK                                          0x140008e
++#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK                                          0x140008f
++#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK                                           0x1400090
++#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK                                         0x1400091
++#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK                                         0x1400092
++#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL                                        0x1400093
++#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL                                        0x1400094
++#define ixPCIE_PERF_CNTL_TXCLK2                                                 0x1400095
++#define ixPCIE_PERF_COUNT0_TXCLK2                                               0x1400096
++#define ixPCIE_PERF_COUNT1_TXCLK2                                               0x1400097
++#define ixPCIE_STRAP_F0                                                         0x14000b0
++#define ixPCIE_STRAP_F1                                                         0x14000b1
++#define ixPCIE_STRAP_F2                                                         0x14000b2
++#define ixPCIE_STRAP_F3                                                         0x14000b3
++#define ixPCIE_STRAP_F4                                                         0x14000b4
++#define ixPCIE_STRAP_F5                                                         0x14000b5
++#define ixPCIE_STRAP_F6                                                         0x14000b6
++#define ixPCIE_STRAP_F7                                                         0x14000b7
++#define ixPCIE_STRAP_MISC                                                       0x14000c0
++#define ixPCIE_STRAP_MISC2                                                      0x14000c1
++#define ixPCIE_STRAP_PI                                                         0x14000c2
++#define ixPCIE_STRAP_I2C_BD                                                     0x14000c4
++#define ixPCIE_PRBS_CLR                                                         0x14000c8
++#define ixPCIE_PRBS_STATUS1                                                     0x14000c9
++#define ixPCIE_PRBS_STATUS2                                                     0x14000ca
++#define ixPCIE_PRBS_FREERUN                                                     0x14000cb
++#define ixPCIE_PRBS_MISC                                                        0x14000cc
++#define ixPCIE_PRBS_USER_PATTERN                                                0x14000cd
++#define ixPCIE_PRBS_LO_BITCNT                                                   0x14000ce
++#define ixPCIE_PRBS_HI_BITCNT                                                   0x14000cf
++#define ixPCIE_PRBS_ERRCNT_0                                                    0x14000d0
++#define ixPCIE_PRBS_ERRCNT_1                                                    0x14000d1
++#define ixPCIE_PRBS_ERRCNT_2                                                    0x14000d2
++#define ixPCIE_PRBS_ERRCNT_3                                                    0x14000d3
++#define ixPCIE_PRBS_ERRCNT_4                                                    0x14000d4
++#define ixPCIE_PRBS_ERRCNT_5                                                    0x14000d5
++#define ixPCIE_PRBS_ERRCNT_6                                                    0x14000d6
++#define ixPCIE_PRBS_ERRCNT_7                                                    0x14000d7
++#define ixPCIE_PRBS_ERRCNT_8                                                    0x14000d8
++#define ixPCIE_PRBS_ERRCNT_9                                                    0x14000d9
++#define ixPCIE_PRBS_ERRCNT_10                                                   0x14000da
++#define ixPCIE_PRBS_ERRCNT_11                                                   0x14000db
++#define ixPCIE_PRBS_ERRCNT_12                                                   0x14000dc
++#define ixPCIE_PRBS_ERRCNT_13                                                   0x14000dd
++#define ixPCIE_PRBS_ERRCNT_14                                                   0x14000de
++#define ixPCIE_PRBS_ERRCNT_15                                                   0x14000df
++#define ixPCIE_F0_DPA_CAP                                                       0x14000e0
++#define ixPCIE_F0_DPA_LATENCY_INDICATOR                                         0x14000e4
++#define ixPCIE_F0_DPA_CNTL                                                      0x14000e5
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                      0x14000e7
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                      0x14000e8
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                      0x14000e9
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                      0x14000ea
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                      0x14000eb
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                      0x14000ec
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                      0x14000ed
++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                      0x14000ee
++#define ixPCIEP_RESERVED                                                        0x10010000
++#define ixPCIEP_SCRATCH                                                         0x10010001
++#define ixPCIEP_HW_DEBUG                                                        0x10010002
++#define ixPCIEP_PORT_CNTL                                                       0x10010010
++#define ixPCIE_TX_CNTL                                                          0x10010020
++#define ixPCIE_TX_REQUESTER_ID                                                  0x10010021
++#define ixPCIE_TX_VENDOR_SPECIFIC                                               0x10010022
++#define ixPCIE_TX_REQUEST_NUM_CNTL                                              0x10010023
++#define ixPCIE_TX_SEQ                                                           0x10010024
++#define ixPCIE_TX_REPLAY                                                        0x10010025
++#define ixPCIE_TX_ACK_LATENCY_LIMIT                                             0x10010026
++#define ixPCIE_TX_CREDITS_ADVT_P                                                0x10010030
++#define ixPCIE_TX_CREDITS_ADVT_NP                                               0x10010031
++#define ixPCIE_TX_CREDITS_ADVT_CPL                                              0x10010032
++#define ixPCIE_TX_CREDITS_INIT_P                                                0x10010033
++#define ixPCIE_TX_CREDITS_INIT_NP                                               0x10010034
++#define ixPCIE_TX_CREDITS_INIT_CPL                                              0x10010035
++#define ixPCIE_TX_CREDITS_STATUS                                                0x10010036
++#define ixPCIE_TX_CREDITS_FCU_THRESHOLD                                         0x10010037
++#define ixPCIE_P_PORT_LANE_STATUS                                               0x10010050
++#define ixPCIE_FC_P                                                             0x10010060
++#define ixPCIE_FC_NP                                                            0x10010061
++#define ixPCIE_FC_CPL                                                           0x10010062
++#define ixPCIE_ERR_CNTL                                                         0x1001006a
++#define ixPCIE_RX_CNTL                                                          0x10010070
++#define ixPCIE_RX_EXPECTED_SEQNUM                                               0x10010071
++#define ixPCIE_RX_VENDOR_SPECIFIC                                               0x10010072
++#define ixPCIE_RX_CNTL3                                                         0x10010074
++#define ixPCIE_RX_CREDITS_ALLOCATED_P                                           0x10010080
++#define ixPCIE_RX_CREDITS_ALLOCATED_NP                                          0x10010081
++#define ixPCIE_RX_CREDITS_ALLOCATED_CPL                                         0x10010082
++#define ixPCIE_LC_CNTL                                                          0x100100a0
++#define ixPCIE_LC_CNTL2                                                         0x100100b1
++#define ixPCIE_LC_CNTL3                                                         0x100100b5
++#define ixPCIE_LC_CNTL4                                                         0x100100b6
++#define ixPCIE_LC_CNTL5                                                         0x100100b7
++#define ixPCIE_LC_BW_CHANGE_CNTL                                                0x100100b2
++#define ixPCIE_LC_TRAINING_CNTL                                                 0x100100a1
++#define ixPCIE_LC_LINK_WIDTH_CNTL                                               0x100100a2
++#define ixPCIE_LC_N_FTS_CNTL                                                    0x100100a3
++#define ixPCIE_LC_SPEED_CNTL                                                    0x100100a4
++#define ixPCIE_LC_CDR_CNTL                                                      0x100100b3
++#define ixPCIE_LC_LANE_CNTL                                                     0x100100b4
++#define ixPCIE_LC_FORCE_COEFF                                                   0x100100b8
++#define ixPCIE_LC_BEST_EQ_SETTINGS                                              0x100100b9
++#define ixPCIE_LC_FORCE_EQ_REQ_COEFF                                            0x100100ba
++#define ixPCIE_LC_STATE0                                                        0x100100a5
++#define ixPCIE_LC_STATE1                                                        0x100100a6
++#define ixPCIE_LC_STATE2                                                        0x100100a7
++#define ixPCIE_LC_STATE3                                                        0x100100a8
++#define ixPCIE_LC_STATE4                                                        0x100100a9
++#define ixPCIE_LC_STATE5                                                        0x100100aa
++#define ixPCIEP_STRAP_LC                                                        0x100100c0
++#define ixPCIEP_STRAP_MISC                                                      0x100100c1
++#define ixPCIEP_BCH_ECC_CNTL                                                    0x100100d0
++#define mmBIF_RFE_SNOOP_REG                                                     0x27
++#define mmBIF_RFE_WARMRST_CNTL                                                  0x1459
++#define mmBIF_RFE_SOFTRST_CNTL                                                  0x1441
++#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER                                        0x1442
++#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER                                        0x1443
++#define mmBIF_PWDN_COMMAND                                                      0x1444
++#define mmBIF_PWDN_STATUS                                                       0x1445
++#define mmBIF_RFE_MST_FBU_CMDSTATUS                                             0x1446
++#define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS                                  0x1447
++#define mmBIF_RFE_MST_BX_CMDSTATUS                                              0x1448
++#define mmBIF_RFE_MST_TMOUT_STATUS                                              0x144b
++#define mmBIF_RFE_MMCFG_CNTL                                                    0x144c
++#define ixBIF_CLOCKS_BITS_IND                                                   0x1301489
++#define ixBIF_LNCNT_RESET_IND                                                   0x1301488
++#define ixLNCNT_CONTROL_IND                                                     0x1301487
++#define ixNEW_REFCLKB_TIMER_IND                                                 0x1301485
++#define ixNEW_REFCLKB_TIMER_1_IND                                               0x1301484
++#define ixBIF_CLK_PDWN_DELAY_TIMER_IND                                          0x1301483
++#define ixBIF_RESET_EN_IND                                                      0x1301482
++#define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND                                        0x1301481
++#define ixBIF_BACO_MSIC_IND                                                     0x1301480
++#define ixBIF_RESET_CNTL_IND                                                    0x1301486
++#define ixBIF_RFE_CNTL_MISC_IND                                                 0x130148c
++#define ixBIF_MEM_PG_CNTL_IND                                                   0x130148a
++#define mmNB_GBIF_INDEX                                                         0x34
++#define mmNB_GBIF_DATA                                                          0x35
++#define mmBIF_CLOCKS_BITS                                                       0x1489
++#define mmBIF_LNCNT_RESET                                                       0x1488
++#define mmLNCNT_CONTROL                                                         0x1487
++#define mmNEW_REFCLKB_TIMER                                                     0x1485
++#define mmNEW_REFCLKB_TIMER_1                                                   0x1484
++#define mmBIF_CLK_PDWN_DELAY_TIMER                                              0x1483
++#define mmBIF_RESET_EN                                                          0x1482
++#define mmBIF_PIF_TXCLK_SWITCH_TIMER                                            0x1481
++#define mmBIF_BACO_MSIC                                                         0x1480
++#define mmBIF_RESET_CNTL                                                        0x1486
++#define mmBIF_RFE_CNTL_MISC                                                     0x148c
++#define mmBIF_MEM_PG_CNTL                                                       0x148a
++#define mmC_PCIE_P_INDEX                                                        0x38
++#define mmC_PCIE_P_DATA                                                         0x39
++#define ixD2F1_PCIE_PORT_INDEX                                                  0x2000038
++#define ixD2F1_PCIE_PORT_DATA                                                   0x2000039
++#define ixD2F1_PCIEP_RESERVED                                                   0x0
++#define ixD2F1_PCIEP_SCRATCH                                                    0x1
++#define ixD2F1_PCIEP_HW_DEBUG                                                   0x2
++#define ixD2F1_PCIEP_PORT_CNTL                                                  0x10
++#define ixD2F1_PCIE_TX_CNTL                                                     0x20
++#define ixD2F1_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD2F1_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD2F1_PCIE_TX_SEQ                                                      0x24
++#define ixD2F1_PCIE_TX_REPLAY                                                   0x25
++#define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD2F1_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD2F1_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD2F1_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD2F1_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD2F1_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD2F1_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD2F1_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD2F1_PCIE_FC_P                                                        0x60
++#define ixD2F1_PCIE_FC_NP                                                       0x61
++#define ixD2F1_PCIE_FC_CPL                                                      0x62
++#define ixD2F1_PCIE_ERR_CNTL                                                    0x6a
++#define ixD2F1_PCIE_RX_CNTL                                                     0x70
++#define ixD2F1_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD2F1_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD2F1_PCIE_RX_CNTL3                                                    0x74
++#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD2F1_PCIE_LC_CNTL                                                     0xa0
++#define ixD2F1_PCIE_LC_CNTL2                                                    0xb1
++#define ixD2F1_PCIE_LC_CNTL3                                                    0xb5
++#define ixD2F1_PCIE_LC_CNTL4                                                    0xb6
++#define ixD2F1_PCIE_LC_CNTL5                                                    0xb7
++#define ixD2F1_PCIE_LC_CNTL6                                                    0xbb
++#define ixD2F1_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD2F1_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD2F1_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD2F1_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD2F1_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD2F1_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD2F1_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD2F1_PCIE_LC_STATE0                                                   0xa5
++#define ixD2F1_PCIE_LC_STATE1                                                   0xa6
++#define ixD2F1_PCIE_LC_STATE2                                                   0xa7
++#define ixD2F1_PCIE_LC_STATE3                                                   0xa8
++#define ixD2F1_PCIE_LC_STATE4                                                   0xa9
++#define ixD2F1_PCIE_LC_STATE5                                                   0xaa
++#define ixD2F1_PCIEP_STRAP_LC                                                   0xc0
++#define ixD2F1_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD2F1_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD2F1_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD2F1_PCIEP_HPGI                                                       0xda
++#define ixD2F1_VENDOR_ID                                                        0x2000000
++#define ixD2F1_DEVICE_ID                                                        0x2000000
++#define ixD2F1_COMMAND                                                          0x2000001
++#define ixD2F1_STATUS                                                           0x2000001
++#define ixD2F1_REVISION_ID                                                      0x2000002
++#define ixD2F1_PROG_INTERFACE                                                   0x2000002
++#define ixD2F1_SUB_CLASS                                                        0x2000002
++#define ixD2F1_BASE_CLASS                                                       0x2000002
++#define ixD2F1_CACHE_LINE                                                       0x2000003
++#define ixD2F1_LATENCY                                                          0x2000003
++#define ixD2F1_HEADER                                                           0x2000003
++#define ixD2F1_BIST                                                             0x2000003
++#define ixD2F1_SUB_BUS_NUMBER_LATENCY                                           0x2000006
++#define ixD2F1_IO_BASE_LIMIT                                                    0x2000007
++#define ixD2F1_SECONDARY_STATUS                                                 0x2000007
++#define ixD2F1_MEM_BASE_LIMIT                                                   0x2000008
++#define ixD2F1_PREF_BASE_LIMIT                                                  0x2000009
++#define ixD2F1_PREF_BASE_UPPER                                                  0x200000a
++#define ixD2F1_PREF_LIMIT_UPPER                                                 0x200000b
++#define ixD2F1_IO_BASE_LIMIT_HI                                                 0x200000c
++#define ixD2F1_IRQ_BRIDGE_CNTL                                                  0x200000f
++#define ixD2F1_CAP_PTR                                                          0x200000d
++#define ixD2F1_INTERRUPT_LINE                                                   0x200000f
++#define ixD2F1_INTERRUPT_PIN                                                    0x200000f
++#define ixD2F1_EXT_BRIDGE_CNTL                                                  0x2000010
++#define ixD2F1_PMI_CAP_LIST                                                     0x2000014
++#define ixD2F1_PMI_CAP                                                          0x2000014
++#define ixD2F1_PMI_STATUS_CNTL                                                  0x2000015
++#define ixD2F1_PCIE_CAP_LIST                                                    0x2000016
++#define ixD2F1_PCIE_CAP                                                         0x2000016
++#define ixD2F1_DEVICE_CAP                                                       0x2000017
++#define ixD2F1_DEVICE_CNTL                                                      0x2000018
++#define ixD2F1_DEVICE_STATUS                                                    0x2000018
++#define ixD2F1_LINK_CAP                                                         0x2000019
++#define ixD2F1_LINK_CNTL                                                        0x200001a
++#define ixD2F1_LINK_STATUS                                                      0x200001a
++#define ixD2F1_SLOT_CAP                                                         0x200001b
++#define ixD2F1_SLOT_CNTL                                                        0x200001c
++#define ixD2F1_SLOT_STATUS                                                      0x200001c
++#define ixD2F1_ROOT_CNTL                                                        0x200001d
++#define ixD2F1_ROOT_CAP                                                         0x200001d
++#define ixD2F1_ROOT_STATUS                                                      0x200001e
++#define ixD2F1_DEVICE_CAP2                                                      0x200001f
++#define ixD2F1_DEVICE_CNTL2                                                     0x2000020
++#define ixD2F1_DEVICE_STATUS2                                                   0x2000020
++#define ixD2F1_LINK_CAP2                                                        0x2000021
++#define ixD2F1_LINK_CNTL2                                                       0x2000022
++#define ixD2F1_LINK_STATUS2                                                     0x2000022
++#define ixD2F1_SLOT_CAP2                                                        0x2000023
++#define ixD2F1_SLOT_CNTL2                                                       0x2000024
++#define ixD2F1_SLOT_STATUS2                                                     0x2000024
++#define ixD2F1_MSI_CAP_LIST                                                     0x2000028
++#define ixD2F1_MSI_MSG_CNTL                                                     0x2000028
++#define ixD2F1_MSI_MSG_ADDR_LO                                                  0x2000029
++#define ixD2F1_MSI_MSG_ADDR_HI                                                  0x200002a
++#define ixD2F1_MSI_MSG_DATA_64                                                  0x200002b
++#define ixD2F1_MSI_MSG_DATA                                                     0x200002a
++#define ixD2F1_SSID_CAP_LIST                                                    0x2000030
++#define ixD2F1_SSID_CAP                                                         0x2000031
++#define ixD2F1_MSI_MAP_CAP_LIST                                                 0x2000032
++#define ixD2F1_MSI_MAP_CAP                                                      0x2000032
++#define ixD2F1_MSI_MAP_ADDR_LO                                                  0x2000033
++#define ixD2F1_MSI_MAP_ADDR_HI                                                  0x2000034
++#define ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x2000040
++#define ixD2F1_PCIE_VENDOR_SPECIFIC_HDR                                         0x2000041
++#define ixD2F1_PCIE_VENDOR_SPECIFIC1                                            0x2000042
++#define ixD2F1_PCIE_VENDOR_SPECIFIC2                                            0x2000043
++#define ixD2F1_PCIE_VC_ENH_CAP_LIST                                             0x2000044
++#define ixD2F1_PCIE_PORT_VC_CAP_REG1                                            0x2000045
++#define ixD2F1_PCIE_PORT_VC_CAP_REG2                                            0x2000046
++#define ixD2F1_PCIE_PORT_VC_CNTL                                                0x2000047
++#define ixD2F1_PCIE_PORT_VC_STATUS                                              0x2000047
++#define ixD2F1_PCIE_VC0_RESOURCE_CAP                                            0x2000048
++#define ixD2F1_PCIE_VC0_RESOURCE_CNTL                                           0x2000049
++#define ixD2F1_PCIE_VC0_RESOURCE_STATUS                                         0x200004a
++#define ixD2F1_PCIE_VC1_RESOURCE_CAP                                            0x200004b
++#define ixD2F1_PCIE_VC1_RESOURCE_CNTL                                           0x200004c
++#define ixD2F1_PCIE_VC1_RESOURCE_STATUS                                         0x200004d
++#define ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x2000050
++#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW1                                          0x2000051
++#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW2                                          0x2000052
++#define ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x2000054
++#define ixD2F1_PCIE_UNCORR_ERR_STATUS                                           0x2000055
++#define ixD2F1_PCIE_UNCORR_ERR_MASK                                             0x2000056
++#define ixD2F1_PCIE_UNCORR_ERR_SEVERITY                                         0x2000057
++#define ixD2F1_PCIE_CORR_ERR_STATUS                                             0x2000058
++#define ixD2F1_PCIE_CORR_ERR_MASK                                               0x2000059
++#define ixD2F1_PCIE_ADV_ERR_CAP_CNTL                                            0x200005a
++#define ixD2F1_PCIE_HDR_LOG0                                                    0x200005b
++#define ixD2F1_PCIE_HDR_LOG1                                                    0x200005c
++#define ixD2F1_PCIE_HDR_LOG2                                                    0x200005d
++#define ixD2F1_PCIE_HDR_LOG3                                                    0x200005e
++#define ixD2F1_PCIE_ROOT_ERR_CMD                                                0x200005f
++#define ixD2F1_PCIE_ROOT_ERR_STATUS                                             0x2000060
++#define ixD2F1_PCIE_ERR_SRC_ID                                                  0x2000061
++#define ixD2F1_PCIE_TLP_PREFIX_LOG0                                             0x2000062
++#define ixD2F1_PCIE_TLP_PREFIX_LOG1                                             0x2000063
++#define ixD2F1_PCIE_TLP_PREFIX_LOG2                                             0x2000064
++#define ixD2F1_PCIE_TLP_PREFIX_LOG3                                             0x2000065
++#define ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST                                      0x200009c
++#define ixD2F1_PCIE_LINK_CNTL3                                                  0x200009d
++#define ixD2F1_PCIE_LANE_ERROR_STATUS                                           0x200009e
++#define ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x200009f
++#define ixD2F1_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x200009f
++#define ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x20000a0
++#define ixD2F1_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x20000a0
++#define ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x20000a1
++#define ixD2F1_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x20000a1
++#define ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x20000a2
++#define ixD2F1_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x20000a2
++#define ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x20000a3
++#define ixD2F1_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x20000a3
++#define ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x20000a4
++#define ixD2F1_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x20000a4
++#define ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x20000a5
++#define ixD2F1_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x20000a5
++#define ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x20000a6
++#define ixD2F1_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x20000a6
++#define ixD2F1_PCIE_ACS_ENH_CAP_LIST                                            0x20000a8
++#define ixD2F1_PCIE_ACS_CAP                                                     0x20000a9
++#define ixD2F1_PCIE_ACS_CNTL                                                    0x20000a9
++#define ixD2F1_PCIE_MC_ENH_CAP_LIST                                             0x20000bc
++#define ixD2F1_PCIE_MC_CAP                                                      0x20000bd
++#define ixD2F1_PCIE_MC_CNTL                                                     0x20000bd
++#define ixD2F1_PCIE_MC_ADDR0                                                    0x20000be
++#define ixD2F1_PCIE_MC_ADDR1                                                    0x20000bf
++#define ixD2F1_PCIE_MC_RCV0                                                     0x20000c0
++#define ixD2F1_PCIE_MC_RCV1                                                     0x20000c1
++#define ixD2F1_PCIE_MC_BLOCK_ALL0                                               0x20000c2
++#define ixD2F1_PCIE_MC_BLOCK_ALL1                                               0x20000c3
++#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x20000c4
++#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x20000c5
++#define ixD2F1_PCIE_MC_OVERLAY_BAR0                                             0x20000c6
++#define ixD2F1_PCIE_MC_OVERLAY_BAR1                                             0x20000c7
++#define ixD2F2_PCIE_PORT_INDEX                                                  0x3000038
++#define ixD2F2_PCIE_PORT_DATA                                                   0x3000039
++#define ixD2F2_PCIEP_RESERVED                                                   0x0
++#define ixD2F2_PCIEP_SCRATCH                                                    0x1
++#define ixD2F2_PCIEP_HW_DEBUG                                                   0x2
++#define ixD2F2_PCIEP_PORT_CNTL                                                  0x10
++#define ixD2F2_PCIE_TX_CNTL                                                     0x20
++#define ixD2F2_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD2F2_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD2F2_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD2F2_PCIE_TX_SEQ                                                      0x24
++#define ixD2F2_PCIE_TX_REPLAY                                                   0x25
++#define ixD2F2_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD2F2_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD2F2_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD2F2_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD2F2_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD2F2_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD2F2_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD2F2_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD2F2_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD2F2_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD2F2_PCIE_FC_P                                                        0x60
++#define ixD2F2_PCIE_FC_NP                                                       0x61
++#define ixD2F2_PCIE_FC_CPL                                                      0x62
++#define ixD2F2_PCIE_ERR_CNTL                                                    0x6a
++#define ixD2F2_PCIE_RX_CNTL                                                     0x70
++#define ixD2F2_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD2F2_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD2F2_PCIE_RX_CNTL3                                                    0x74
++#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD2F2_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD2F2_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD2F2_PCIE_LC_CNTL                                                     0xa0
++#define ixD2F2_PCIE_LC_CNTL2                                                    0xb1
++#define ixD2F2_PCIE_LC_CNTL3                                                    0xb5
++#define ixD2F2_PCIE_LC_CNTL4                                                    0xb6
++#define ixD2F2_PCIE_LC_CNTL5                                                    0xb7
++#define ixD2F2_PCIE_LC_CNTL6                                                    0xbb
++#define ixD2F2_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD2F2_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD2F2_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD2F2_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD2F2_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD2F2_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD2F2_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD2F2_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD2F2_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD2F2_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD2F2_PCIE_LC_STATE0                                                   0xa5
++#define ixD2F2_PCIE_LC_STATE1                                                   0xa6
++#define ixD2F2_PCIE_LC_STATE2                                                   0xa7
++#define ixD2F2_PCIE_LC_STATE3                                                   0xa8
++#define ixD2F2_PCIE_LC_STATE4                                                   0xa9
++#define ixD2F2_PCIE_LC_STATE5                                                   0xaa
++#define ixD2F2_PCIEP_STRAP_LC                                                   0xc0
++#define ixD2F2_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD2F2_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD2F2_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD2F2_PCIEP_HPGI                                                       0xda
++#define ixD2F2_VENDOR_ID                                                        0x3000000
++#define ixD2F2_DEVICE_ID                                                        0x3000000
++#define ixD2F2_COMMAND                                                          0x3000001
++#define ixD2F2_STATUS                                                           0x3000001
++#define ixD2F2_REVISION_ID                                                      0x3000002
++#define ixD2F2_PROG_INTERFACE                                                   0x3000002
++#define ixD2F2_SUB_CLASS                                                        0x3000002
++#define ixD2F2_BASE_CLASS                                                       0x3000002
++#define ixD2F2_CACHE_LINE                                                       0x3000003
++#define ixD2F2_LATENCY                                                          0x3000003
++#define ixD2F2_HEADER                                                           0x3000003
++#define ixD2F2_BIST                                                             0x3000003
++#define ixD2F2_SUB_BUS_NUMBER_LATENCY                                           0x3000006
++#define ixD2F2_IO_BASE_LIMIT                                                    0x3000007
++#define ixD2F2_SECONDARY_STATUS                                                 0x3000007
++#define ixD2F2_MEM_BASE_LIMIT                                                   0x3000008
++#define ixD2F2_PREF_BASE_LIMIT                                                  0x3000009
++#define ixD2F2_PREF_BASE_UPPER                                                  0x300000a
++#define ixD2F2_PREF_LIMIT_UPPER                                                 0x300000b
++#define ixD2F2_IO_BASE_LIMIT_HI                                                 0x300000c
++#define ixD2F2_IRQ_BRIDGE_CNTL                                                  0x300000f
++#define ixD2F2_CAP_PTR                                                          0x300000d
++#define ixD2F2_INTERRUPT_LINE                                                   0x300000f
++#define ixD2F2_INTERRUPT_PIN                                                    0x300000f
++#define ixD2F2_EXT_BRIDGE_CNTL                                                  0x3000010
++#define ixD2F2_PMI_CAP_LIST                                                     0x3000014
++#define ixD2F2_PMI_CAP                                                          0x3000014
++#define ixD2F2_PMI_STATUS_CNTL                                                  0x3000015
++#define ixD2F2_PCIE_CAP_LIST                                                    0x3000016
++#define ixD2F2_PCIE_CAP                                                         0x3000016
++#define ixD2F2_DEVICE_CAP                                                       0x3000017
++#define ixD2F2_DEVICE_CNTL                                                      0x3000018
++#define ixD2F2_DEVICE_STATUS                                                    0x3000018
++#define ixD2F2_LINK_CAP                                                         0x3000019
++#define ixD2F2_LINK_CNTL                                                        0x300001a
++#define ixD2F2_LINK_STATUS                                                      0x300001a
++#define ixD2F2_SLOT_CAP                                                         0x300001b
++#define ixD2F2_SLOT_CNTL                                                        0x300001c
++#define ixD2F2_SLOT_STATUS                                                      0x300001c
++#define ixD2F2_ROOT_CNTL                                                        0x300001d
++#define ixD2F2_ROOT_CAP                                                         0x300001d
++#define ixD2F2_ROOT_STATUS                                                      0x300001e
++#define ixD2F2_DEVICE_CAP2                                                      0x300001f
++#define ixD2F2_DEVICE_CNTL2                                                     0x3000020
++#define ixD2F2_DEVICE_STATUS2                                                   0x3000020
++#define ixD2F2_LINK_CAP2                                                        0x3000021
++#define ixD2F2_LINK_CNTL2                                                       0x3000022
++#define ixD2F2_LINK_STATUS2                                                     0x3000022
++#define ixD2F2_SLOT_CAP2                                                        0x3000023
++#define ixD2F2_SLOT_CNTL2                                                       0x3000024
++#define ixD2F2_SLOT_STATUS2                                                     0x3000024
++#define ixD2F2_MSI_CAP_LIST                                                     0x3000028
++#define ixD2F2_MSI_MSG_CNTL                                                     0x3000028
++#define ixD2F2_MSI_MSG_ADDR_LO                                                  0x3000029
++#define ixD2F2_MSI_MSG_ADDR_HI                                                  0x300002a
++#define ixD2F2_MSI_MSG_DATA_64                                                  0x300002b
++#define ixD2F2_MSI_MSG_DATA                                                     0x300002a
++#define ixD2F2_SSID_CAP_LIST                                                    0x3000030
++#define ixD2F2_SSID_CAP                                                         0x3000031
++#define ixD2F2_MSI_MAP_CAP_LIST                                                 0x3000032
++#define ixD2F2_MSI_MAP_CAP                                                      0x3000032
++#define ixD2F2_MSI_MAP_ADDR_LO                                                  0x3000033
++#define ixD2F2_MSI_MAP_ADDR_HI                                                  0x3000034
++#define ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x3000040
++#define ixD2F2_PCIE_VENDOR_SPECIFIC_HDR                                         0x3000041
++#define ixD2F2_PCIE_VENDOR_SPECIFIC1                                            0x3000042
++#define ixD2F2_PCIE_VENDOR_SPECIFIC2                                            0x3000043
++#define ixD2F2_PCIE_VC_ENH_CAP_LIST                                             0x3000044
++#define ixD2F2_PCIE_PORT_VC_CAP_REG1                                            0x3000045
++#define ixD2F2_PCIE_PORT_VC_CAP_REG2                                            0x3000046
++#define ixD2F2_PCIE_PORT_VC_CNTL                                                0x3000047
++#define ixD2F2_PCIE_PORT_VC_STATUS                                              0x3000047
++#define ixD2F2_PCIE_VC0_RESOURCE_CAP                                            0x3000048
++#define ixD2F2_PCIE_VC0_RESOURCE_CNTL                                           0x3000049
++#define ixD2F2_PCIE_VC0_RESOURCE_STATUS                                         0x300004a
++#define ixD2F2_PCIE_VC1_RESOURCE_CAP                                            0x300004b
++#define ixD2F2_PCIE_VC1_RESOURCE_CNTL                                           0x300004c
++#define ixD2F2_PCIE_VC1_RESOURCE_STATUS                                         0x300004d
++#define ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x3000050
++#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW1                                          0x3000051
++#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW2                                          0x3000052
++#define ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x3000054
++#define ixD2F2_PCIE_UNCORR_ERR_STATUS                                           0x3000055
++#define ixD2F2_PCIE_UNCORR_ERR_MASK                                             0x3000056
++#define ixD2F2_PCIE_UNCORR_ERR_SEVERITY                                         0x3000057
++#define ixD2F2_PCIE_CORR_ERR_STATUS                                             0x3000058
++#define ixD2F2_PCIE_CORR_ERR_MASK                                               0x3000059
++#define ixD2F2_PCIE_ADV_ERR_CAP_CNTL                                            0x300005a
++#define ixD2F2_PCIE_HDR_LOG0                                                    0x300005b
++#define ixD2F2_PCIE_HDR_LOG1                                                    0x300005c
++#define ixD2F2_PCIE_HDR_LOG2                                                    0x300005d
++#define ixD2F2_PCIE_HDR_LOG3                                                    0x300005e
++#define ixD2F2_PCIE_ROOT_ERR_CMD                                                0x300005f
++#define ixD2F2_PCIE_ROOT_ERR_STATUS                                             0x3000060
++#define ixD2F2_PCIE_ERR_SRC_ID                                                  0x3000061
++#define ixD2F2_PCIE_TLP_PREFIX_LOG0                                             0x3000062
++#define ixD2F2_PCIE_TLP_PREFIX_LOG1                                             0x3000063
++#define ixD2F2_PCIE_TLP_PREFIX_LOG2                                             0x3000064
++#define ixD2F2_PCIE_TLP_PREFIX_LOG3                                             0x3000065
++#define ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST                                      0x300009c
++#define ixD2F2_PCIE_LINK_CNTL3                                                  0x300009d
++#define ixD2F2_PCIE_LANE_ERROR_STATUS                                           0x300009e
++#define ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x300009f
++#define ixD2F2_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x300009f
++#define ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x30000a0
++#define ixD2F2_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x30000a0
++#define ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x30000a1
++#define ixD2F2_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x30000a1
++#define ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x30000a2
++#define ixD2F2_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x30000a2
++#define ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x30000a3
++#define ixD2F2_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x30000a3
++#define ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x30000a4
++#define ixD2F2_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x30000a4
++#define ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x30000a5
++#define ixD2F2_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x30000a5
++#define ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x30000a6
++#define ixD2F2_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x30000a6
++#define ixD2F2_PCIE_ACS_ENH_CAP_LIST                                            0x30000a8
++#define ixD2F2_PCIE_ACS_CAP                                                     0x30000a9
++#define ixD2F2_PCIE_ACS_CNTL                                                    0x30000a9
++#define ixD2F2_PCIE_MC_ENH_CAP_LIST                                             0x30000bc
++#define ixD2F2_PCIE_MC_CAP                                                      0x30000bd
++#define ixD2F2_PCIE_MC_CNTL                                                     0x30000bd
++#define ixD2F2_PCIE_MC_ADDR0                                                    0x30000be
++#define ixD2F2_PCIE_MC_ADDR1                                                    0x30000bf
++#define ixD2F2_PCIE_MC_RCV0                                                     0x30000c0
++#define ixD2F2_PCIE_MC_RCV1                                                     0x30000c1
++#define ixD2F2_PCIE_MC_BLOCK_ALL0                                               0x30000c2
++#define ixD2F2_PCIE_MC_BLOCK_ALL1                                               0x30000c3
++#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x30000c4
++#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x30000c5
++#define ixD2F2_PCIE_MC_OVERLAY_BAR0                                             0x30000c6
++#define ixD2F2_PCIE_MC_OVERLAY_BAR1                                             0x30000c7
++#define ixD2F3_PCIE_PORT_INDEX                                                  0x4000038
++#define ixD2F3_PCIE_PORT_DATA                                                   0x4000039
++#define ixD2F3_PCIEP_RESERVED                                                   0x0
++#define ixD2F3_PCIEP_SCRATCH                                                    0x1
++#define ixD2F3_PCIEP_HW_DEBUG                                                   0x2
++#define ixD2F3_PCIEP_PORT_CNTL                                                  0x10
++#define ixD2F3_PCIE_TX_CNTL                                                     0x20
++#define ixD2F3_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD2F3_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD2F3_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD2F3_PCIE_TX_SEQ                                                      0x24
++#define ixD2F3_PCIE_TX_REPLAY                                                   0x25
++#define ixD2F3_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD2F3_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD2F3_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD2F3_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD2F3_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD2F3_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD2F3_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD2F3_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD2F3_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD2F3_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD2F3_PCIE_FC_P                                                        0x60
++#define ixD2F3_PCIE_FC_NP                                                       0x61
++#define ixD2F3_PCIE_FC_CPL                                                      0x62
++#define ixD2F3_PCIE_ERR_CNTL                                                    0x6a
++#define ixD2F3_PCIE_RX_CNTL                                                     0x70
++#define ixD2F3_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD2F3_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD2F3_PCIE_RX_CNTL3                                                    0x74
++#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD2F3_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD2F3_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD2F3_PCIE_LC_CNTL                                                     0xa0
++#define ixD2F3_PCIE_LC_CNTL2                                                    0xb1
++#define ixD2F3_PCIE_LC_CNTL3                                                    0xb5
++#define ixD2F3_PCIE_LC_CNTL4                                                    0xb6
++#define ixD2F3_PCIE_LC_CNTL5                                                    0xb7
++#define ixD2F3_PCIE_LC_CNTL6                                                    0xbb
++#define ixD2F3_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD2F3_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD2F3_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD2F3_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD2F3_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD2F3_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD2F3_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD2F3_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD2F3_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD2F3_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD2F3_PCIE_LC_STATE0                                                   0xa5
++#define ixD2F3_PCIE_LC_STATE1                                                   0xa6
++#define ixD2F3_PCIE_LC_STATE2                                                   0xa7
++#define ixD2F3_PCIE_LC_STATE3                                                   0xa8
++#define ixD2F3_PCIE_LC_STATE4                                                   0xa9
++#define ixD2F3_PCIE_LC_STATE5                                                   0xaa
++#define ixD2F3_PCIEP_STRAP_LC                                                   0xc0
++#define ixD2F3_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD2F3_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD2F3_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD2F3_PCIEP_HPGI                                                       0xda
++#define ixD2F3_VENDOR_ID                                                        0x4000000
++#define ixD2F3_DEVICE_ID                                                        0x4000000
++#define ixD2F3_COMMAND                                                          0x4000001
++#define ixD2F3_STATUS                                                           0x4000001
++#define ixD2F3_REVISION_ID                                                      0x4000002
++#define ixD2F3_PROG_INTERFACE                                                   0x4000002
++#define ixD2F3_SUB_CLASS                                                        0x4000002
++#define ixD2F3_BASE_CLASS                                                       0x4000002
++#define ixD2F3_CACHE_LINE                                                       0x4000003
++#define ixD2F3_LATENCY                                                          0x4000003
++#define ixD2F3_HEADER                                                           0x4000003
++#define ixD2F3_BIST                                                             0x4000003
++#define ixD2F3_SUB_BUS_NUMBER_LATENCY                                           0x4000006
++#define ixD2F3_IO_BASE_LIMIT                                                    0x4000007
++#define ixD2F3_SECONDARY_STATUS                                                 0x4000007
++#define ixD2F3_MEM_BASE_LIMIT                                                   0x4000008
++#define ixD2F3_PREF_BASE_LIMIT                                                  0x4000009
++#define ixD2F3_PREF_BASE_UPPER                                                  0x400000a
++#define ixD2F3_PREF_LIMIT_UPPER                                                 0x400000b
++#define ixD2F3_IO_BASE_LIMIT_HI                                                 0x400000c
++#define ixD2F3_IRQ_BRIDGE_CNTL                                                  0x400000f
++#define ixD2F3_CAP_PTR                                                          0x400000d
++#define ixD2F3_INTERRUPT_LINE                                                   0x400000f
++#define ixD2F3_INTERRUPT_PIN                                                    0x400000f
++#define ixD2F3_EXT_BRIDGE_CNTL                                                  0x4000010
++#define ixD2F3_PMI_CAP_LIST                                                     0x4000014
++#define ixD2F3_PMI_CAP                                                          0x4000014
++#define ixD2F3_PMI_STATUS_CNTL                                                  0x4000015
++#define ixD2F3_PCIE_CAP_LIST                                                    0x4000016
++#define ixD2F3_PCIE_CAP                                                         0x4000016
++#define ixD2F3_DEVICE_CAP                                                       0x4000017
++#define ixD2F3_DEVICE_CNTL                                                      0x4000018
++#define ixD2F3_DEVICE_STATUS                                                    0x4000018
++#define ixD2F3_LINK_CAP                                                         0x4000019
++#define ixD2F3_LINK_CNTL                                                        0x400001a
++#define ixD2F3_LINK_STATUS                                                      0x400001a
++#define ixD2F3_SLOT_CAP                                                         0x400001b
++#define ixD2F3_SLOT_CNTL                                                        0x400001c
++#define ixD2F3_SLOT_STATUS                                                      0x400001c
++#define ixD2F3_ROOT_CNTL                                                        0x400001d
++#define ixD2F3_ROOT_CAP                                                         0x400001d
++#define ixD2F3_ROOT_STATUS                                                      0x400001e
++#define ixD2F3_DEVICE_CAP2                                                      0x400001f
++#define ixD2F3_DEVICE_CNTL2                                                     0x4000020
++#define ixD2F3_DEVICE_STATUS2                                                   0x4000020
++#define ixD2F3_LINK_CAP2                                                        0x4000021
++#define ixD2F3_LINK_CNTL2                                                       0x4000022
++#define ixD2F3_LINK_STATUS2                                                     0x4000022
++#define ixD2F3_SLOT_CAP2                                                        0x4000023
++#define ixD2F3_SLOT_CNTL2                                                       0x4000024
++#define ixD2F3_SLOT_STATUS2                                                     0x4000024
++#define ixD2F3_MSI_CAP_LIST                                                     0x4000028
++#define ixD2F3_MSI_MSG_CNTL                                                     0x4000028
++#define ixD2F3_MSI_MSG_ADDR_LO                                                  0x4000029
++#define ixD2F3_MSI_MSG_ADDR_HI                                                  0x400002a
++#define ixD2F3_MSI_MSG_DATA_64                                                  0x400002b
++#define ixD2F3_MSI_MSG_DATA                                                     0x400002a
++#define ixD2F3_SSID_CAP_LIST                                                    0x4000030
++#define ixD2F3_SSID_CAP                                                         0x4000031
++#define ixD2F3_MSI_MAP_CAP_LIST                                                 0x4000032
++#define ixD2F3_MSI_MAP_CAP                                                      0x4000032
++#define ixD2F3_MSI_MAP_ADDR_LO                                                  0x4000033
++#define ixD2F3_MSI_MAP_ADDR_HI                                                  0x4000034
++#define ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x4000040
++#define ixD2F3_PCIE_VENDOR_SPECIFIC_HDR                                         0x4000041
++#define ixD2F3_PCIE_VENDOR_SPECIFIC1                                            0x4000042
++#define ixD2F3_PCIE_VENDOR_SPECIFIC2                                            0x4000043
++#define ixD2F3_PCIE_VC_ENH_CAP_LIST                                             0x4000044
++#define ixD2F3_PCIE_PORT_VC_CAP_REG1                                            0x4000045
++#define ixD2F3_PCIE_PORT_VC_CAP_REG2                                            0x4000046
++#define ixD2F3_PCIE_PORT_VC_CNTL                                                0x4000047
++#define ixD2F3_PCIE_PORT_VC_STATUS                                              0x4000047
++#define ixD2F3_PCIE_VC0_RESOURCE_CAP                                            0x4000048
++#define ixD2F3_PCIE_VC0_RESOURCE_CNTL                                           0x4000049
++#define ixD2F3_PCIE_VC0_RESOURCE_STATUS                                         0x400004a
++#define ixD2F3_PCIE_VC1_RESOURCE_CAP                                            0x400004b
++#define ixD2F3_PCIE_VC1_RESOURCE_CNTL                                           0x400004c
++#define ixD2F3_PCIE_VC1_RESOURCE_STATUS                                         0x400004d
++#define ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x4000050
++#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW1                                          0x4000051
++#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW2                                          0x4000052
++#define ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x4000054
++#define ixD2F3_PCIE_UNCORR_ERR_STATUS                                           0x4000055
++#define ixD2F3_PCIE_UNCORR_ERR_MASK                                             0x4000056
++#define ixD2F3_PCIE_UNCORR_ERR_SEVERITY                                         0x4000057
++#define ixD2F3_PCIE_CORR_ERR_STATUS                                             0x4000058
++#define ixD2F3_PCIE_CORR_ERR_MASK                                               0x4000059
++#define ixD2F3_PCIE_ADV_ERR_CAP_CNTL                                            0x400005a
++#define ixD2F3_PCIE_HDR_LOG0                                                    0x400005b
++#define ixD2F3_PCIE_HDR_LOG1                                                    0x400005c
++#define ixD2F3_PCIE_HDR_LOG2                                                    0x400005d
++#define ixD2F3_PCIE_HDR_LOG3                                                    0x400005e
++#define ixD2F3_PCIE_ROOT_ERR_CMD                                                0x400005f
++#define ixD2F3_PCIE_ROOT_ERR_STATUS                                             0x4000060
++#define ixD2F3_PCIE_ERR_SRC_ID                                                  0x4000061
++#define ixD2F3_PCIE_TLP_PREFIX_LOG0                                             0x4000062
++#define ixD2F3_PCIE_TLP_PREFIX_LOG1                                             0x4000063
++#define ixD2F3_PCIE_TLP_PREFIX_LOG2                                             0x4000064
++#define ixD2F3_PCIE_TLP_PREFIX_LOG3                                             0x4000065
++#define ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST                                      0x400009c
++#define ixD2F3_PCIE_LINK_CNTL3                                                  0x400009d
++#define ixD2F3_PCIE_LANE_ERROR_STATUS                                           0x400009e
++#define ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x400009f
++#define ixD2F3_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x400009f
++#define ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x40000a0
++#define ixD2F3_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x40000a0
++#define ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x40000a1
++#define ixD2F3_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x40000a1
++#define ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x40000a2
++#define ixD2F3_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x40000a2
++#define ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x40000a3
++#define ixD2F3_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x40000a3
++#define ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x40000a4
++#define ixD2F3_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x40000a4
++#define ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x40000a5
++#define ixD2F3_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x40000a5
++#define ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x40000a6
++#define ixD2F3_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x40000a6
++#define ixD2F3_PCIE_ACS_ENH_CAP_LIST                                            0x40000a8
++#define ixD2F3_PCIE_ACS_CAP                                                     0x40000a9
++#define ixD2F3_PCIE_ACS_CNTL                                                    0x40000a9
++#define ixD2F3_PCIE_MC_ENH_CAP_LIST                                             0x40000bc
++#define ixD2F3_PCIE_MC_CAP                                                      0x40000bd
++#define ixD2F3_PCIE_MC_CNTL                                                     0x40000bd
++#define ixD2F3_PCIE_MC_ADDR0                                                    0x40000be
++#define ixD2F3_PCIE_MC_ADDR1                                                    0x40000bf
++#define ixD2F3_PCIE_MC_RCV0                                                     0x40000c0
++#define ixD2F3_PCIE_MC_RCV1                                                     0x40000c1
++#define ixD2F3_PCIE_MC_BLOCK_ALL0                                               0x40000c2
++#define ixD2F3_PCIE_MC_BLOCK_ALL1                                               0x40000c3
++#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x40000c4
++#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x40000c5
++#define ixD2F3_PCIE_MC_OVERLAY_BAR0                                             0x40000c6
++#define ixD2F3_PCIE_MC_OVERLAY_BAR1                                             0x40000c7
++#define ixD2F4_PCIE_PORT_INDEX                                                  0x5000038
++#define ixD2F4_PCIE_PORT_DATA                                                   0x5000039
++#define ixD2F4_PCIEP_RESERVED                                                   0x0
++#define ixD2F4_PCIEP_SCRATCH                                                    0x1
++#define ixD2F4_PCIEP_HW_DEBUG                                                   0x2
++#define ixD2F4_PCIEP_PORT_CNTL                                                  0x10
++#define ixD2F4_PCIE_TX_CNTL                                                     0x20
++#define ixD2F4_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD2F4_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD2F4_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD2F4_PCIE_TX_SEQ                                                      0x24
++#define ixD2F4_PCIE_TX_REPLAY                                                   0x25
++#define ixD2F4_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD2F4_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD2F4_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD2F4_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD2F4_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD2F4_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD2F4_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD2F4_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD2F4_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD2F4_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD2F4_PCIE_FC_P                                                        0x60
++#define ixD2F4_PCIE_FC_NP                                                       0x61
++#define ixD2F4_PCIE_FC_CPL                                                      0x62
++#define ixD2F4_PCIE_ERR_CNTL                                                    0x6a
++#define ixD2F4_PCIE_RX_CNTL                                                     0x70
++#define ixD2F4_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD2F4_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD2F4_PCIE_RX_CNTL3                                                    0x74
++#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD2F4_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD2F4_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD2F4_PCIE_LC_CNTL                                                     0xa0
++#define ixD2F4_PCIE_LC_CNTL2                                                    0xb1
++#define ixD2F4_PCIE_LC_CNTL3                                                    0xb5
++#define ixD2F4_PCIE_LC_CNTL4                                                    0xb6
++#define ixD2F4_PCIE_LC_CNTL5                                                    0xb7
++#define ixD2F4_PCIE_LC_CNTL6                                                    0xbb
++#define ixD2F4_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD2F4_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD2F4_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD2F4_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD2F4_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD2F4_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD2F4_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD2F4_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD2F4_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD2F4_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD2F4_PCIE_LC_STATE0                                                   0xa5
++#define ixD2F4_PCIE_LC_STATE1                                                   0xa6
++#define ixD2F4_PCIE_LC_STATE2                                                   0xa7
++#define ixD2F4_PCIE_LC_STATE3                                                   0xa8
++#define ixD2F4_PCIE_LC_STATE4                                                   0xa9
++#define ixD2F4_PCIE_LC_STATE5                                                   0xaa
++#define ixD2F4_PCIEP_STRAP_LC                                                   0xc0
++#define ixD2F4_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD2F4_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD2F4_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD2F4_PCIEP_HPGI                                                       0xda
++#define ixD2F4_VENDOR_ID                                                        0x5000000
++#define ixD2F4_DEVICE_ID                                                        0x5000000
++#define ixD2F4_COMMAND                                                          0x5000001
++#define ixD2F4_STATUS                                                           0x5000001
++#define ixD2F4_REVISION_ID                                                      0x5000002
++#define ixD2F4_PROG_INTERFACE                                                   0x5000002
++#define ixD2F4_SUB_CLASS                                                        0x5000002
++#define ixD2F4_BASE_CLASS                                                       0x5000002
++#define ixD2F4_CACHE_LINE                                                       0x5000003
++#define ixD2F4_LATENCY                                                          0x5000003
++#define ixD2F4_HEADER                                                           0x5000003
++#define ixD2F4_BIST                                                             0x5000003
++#define ixD2F4_SUB_BUS_NUMBER_LATENCY                                           0x5000006
++#define ixD2F4_IO_BASE_LIMIT                                                    0x5000007
++#define ixD2F4_SECONDARY_STATUS                                                 0x5000007
++#define ixD2F4_MEM_BASE_LIMIT                                                   0x5000008
++#define ixD2F4_PREF_BASE_LIMIT                                                  0x5000009
++#define ixD2F4_PREF_BASE_UPPER                                                  0x500000a
++#define ixD2F4_PREF_LIMIT_UPPER                                                 0x500000b
++#define ixD2F4_IO_BASE_LIMIT_HI                                                 0x500000c
++#define ixD2F4_IRQ_BRIDGE_CNTL                                                  0x500000f
++#define ixD2F4_CAP_PTR                                                          0x500000d
++#define ixD2F4_INTERRUPT_LINE                                                   0x500000f
++#define ixD2F4_INTERRUPT_PIN                                                    0x500000f
++#define ixD2F4_EXT_BRIDGE_CNTL                                                  0x5000010
++#define ixD2F4_PMI_CAP_LIST                                                     0x5000014
++#define ixD2F4_PMI_CAP                                                          0x5000014
++#define ixD2F4_PMI_STATUS_CNTL                                                  0x5000015
++#define ixD2F4_PCIE_CAP_LIST                                                    0x5000016
++#define ixD2F4_PCIE_CAP                                                         0x5000016
++#define ixD2F4_DEVICE_CAP                                                       0x5000017
++#define ixD2F4_DEVICE_CNTL                                                      0x5000018
++#define ixD2F4_DEVICE_STATUS                                                    0x5000018
++#define ixD2F4_LINK_CAP                                                         0x5000019
++#define ixD2F4_LINK_CNTL                                                        0x500001a
++#define ixD2F4_LINK_STATUS                                                      0x500001a
++#define ixD2F4_SLOT_CAP                                                         0x500001b
++#define ixD2F4_SLOT_CNTL                                                        0x500001c
++#define ixD2F4_SLOT_STATUS                                                      0x500001c
++#define ixD2F4_ROOT_CNTL                                                        0x500001d
++#define ixD2F4_ROOT_CAP                                                         0x500001d
++#define ixD2F4_ROOT_STATUS                                                      0x500001e
++#define ixD2F4_DEVICE_CAP2                                                      0x500001f
++#define ixD2F4_DEVICE_CNTL2                                                     0x5000020
++#define ixD2F4_DEVICE_STATUS2                                                   0x5000020
++#define ixD2F4_LINK_CAP2                                                        0x5000021
++#define ixD2F4_LINK_CNTL2                                                       0x5000022
++#define ixD2F4_LINK_STATUS2                                                     0x5000022
++#define ixD2F4_SLOT_CAP2                                                        0x5000023
++#define ixD2F4_SLOT_CNTL2                                                       0x5000024
++#define ixD2F4_SLOT_STATUS2                                                     0x5000024
++#define ixD2F4_MSI_CAP_LIST                                                     0x5000028
++#define ixD2F4_MSI_MSG_CNTL                                                     0x5000028
++#define ixD2F4_MSI_MSG_ADDR_LO                                                  0x5000029
++#define ixD2F4_MSI_MSG_ADDR_HI                                                  0x500002a
++#define ixD2F4_MSI_MSG_DATA_64                                                  0x500002b
++#define ixD2F4_MSI_MSG_DATA                                                     0x500002a
++#define ixD2F4_SSID_CAP_LIST                                                    0x5000030
++#define ixD2F4_SSID_CAP                                                         0x5000031
++#define ixD2F4_MSI_MAP_CAP_LIST                                                 0x5000032
++#define ixD2F4_MSI_MAP_CAP                                                      0x5000032
++#define ixD2F4_MSI_MAP_ADDR_LO                                                  0x5000033
++#define ixD2F4_MSI_MAP_ADDR_HI                                                  0x5000034
++#define ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x5000040
++#define ixD2F4_PCIE_VENDOR_SPECIFIC_HDR                                         0x5000041
++#define ixD2F4_PCIE_VENDOR_SPECIFIC1                                            0x5000042
++#define ixD2F4_PCIE_VENDOR_SPECIFIC2                                            0x5000043
++#define ixD2F4_PCIE_VC_ENH_CAP_LIST                                             0x5000044
++#define ixD2F4_PCIE_PORT_VC_CAP_REG1                                            0x5000045
++#define ixD2F4_PCIE_PORT_VC_CAP_REG2                                            0x5000046
++#define ixD2F4_PCIE_PORT_VC_CNTL                                                0x5000047
++#define ixD2F4_PCIE_PORT_VC_STATUS                                              0x5000047
++#define ixD2F4_PCIE_VC0_RESOURCE_CAP                                            0x5000048
++#define ixD2F4_PCIE_VC0_RESOURCE_CNTL                                           0x5000049
++#define ixD2F4_PCIE_VC0_RESOURCE_STATUS                                         0x500004a
++#define ixD2F4_PCIE_VC1_RESOURCE_CAP                                            0x500004b
++#define ixD2F4_PCIE_VC1_RESOURCE_CNTL                                           0x500004c
++#define ixD2F4_PCIE_VC1_RESOURCE_STATUS                                         0x500004d
++#define ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x5000050
++#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW1                                          0x5000051
++#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW2                                          0x5000052
++#define ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x5000054
++#define ixD2F4_PCIE_UNCORR_ERR_STATUS                                           0x5000055
++#define ixD2F4_PCIE_UNCORR_ERR_MASK                                             0x5000056
++#define ixD2F4_PCIE_UNCORR_ERR_SEVERITY                                         0x5000057
++#define ixD2F4_PCIE_CORR_ERR_STATUS                                             0x5000058
++#define ixD2F4_PCIE_CORR_ERR_MASK                                               0x5000059
++#define ixD2F4_PCIE_ADV_ERR_CAP_CNTL                                            0x500005a
++#define ixD2F4_PCIE_HDR_LOG0                                                    0x500005b
++#define ixD2F4_PCIE_HDR_LOG1                                                    0x500005c
++#define ixD2F4_PCIE_HDR_LOG2                                                    0x500005d
++#define ixD2F4_PCIE_HDR_LOG3                                                    0x500005e
++#define ixD2F4_PCIE_ROOT_ERR_CMD                                                0x500005f
++#define ixD2F4_PCIE_ROOT_ERR_STATUS                                             0x5000060
++#define ixD2F4_PCIE_ERR_SRC_ID                                                  0x5000061
++#define ixD2F4_PCIE_TLP_PREFIX_LOG0                                             0x5000062
++#define ixD2F4_PCIE_TLP_PREFIX_LOG1                                             0x5000063
++#define ixD2F4_PCIE_TLP_PREFIX_LOG2                                             0x5000064
++#define ixD2F4_PCIE_TLP_PREFIX_LOG3                                             0x5000065
++#define ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST                                      0x500009c
++#define ixD2F4_PCIE_LINK_CNTL3                                                  0x500009d
++#define ixD2F4_PCIE_LANE_ERROR_STATUS                                           0x500009e
++#define ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x500009f
++#define ixD2F4_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x500009f
++#define ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x50000a0
++#define ixD2F4_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x50000a0
++#define ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x50000a1
++#define ixD2F4_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x50000a1
++#define ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x50000a2
++#define ixD2F4_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x50000a2
++#define ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x50000a3
++#define ixD2F4_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x50000a3
++#define ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x50000a4
++#define ixD2F4_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x50000a4
++#define ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x50000a5
++#define ixD2F4_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x50000a5
++#define ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x50000a6
++#define ixD2F4_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x50000a6
++#define ixD2F4_PCIE_ACS_ENH_CAP_LIST                                            0x50000a8
++#define ixD2F4_PCIE_ACS_CAP                                                     0x50000a9
++#define ixD2F4_PCIE_ACS_CNTL                                                    0x50000a9
++#define ixD2F4_PCIE_MC_ENH_CAP_LIST                                             0x50000bc
++#define ixD2F4_PCIE_MC_CAP                                                      0x50000bd
++#define ixD2F4_PCIE_MC_CNTL                                                     0x50000bd
++#define ixD2F4_PCIE_MC_ADDR0                                                    0x50000be
++#define ixD2F4_PCIE_MC_ADDR1                                                    0x50000bf
++#define ixD2F4_PCIE_MC_RCV0                                                     0x50000c0
++#define ixD2F4_PCIE_MC_RCV1                                                     0x50000c1
++#define ixD2F4_PCIE_MC_BLOCK_ALL0                                               0x50000c2
++#define ixD2F4_PCIE_MC_BLOCK_ALL1                                               0x50000c3
++#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x50000c4
++#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x50000c5
++#define ixD2F4_PCIE_MC_OVERLAY_BAR0                                             0x50000c6
++#define ixD2F4_PCIE_MC_OVERLAY_BAR1                                             0x50000c7
++#define ixD2F5_PCIE_PORT_INDEX                                                  0x6000038
++#define ixD2F5_PCIE_PORT_DATA                                                   0x6000039
++#define ixD2F5_PCIEP_RESERVED                                                   0x0
++#define ixD2F5_PCIEP_SCRATCH                                                    0x1
++#define ixD2F5_PCIEP_HW_DEBUG                                                   0x2
++#define ixD2F5_PCIEP_PORT_CNTL                                                  0x10
++#define ixD2F5_PCIE_TX_CNTL                                                     0x20
++#define ixD2F5_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD2F5_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD2F5_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD2F5_PCIE_TX_SEQ                                                      0x24
++#define ixD2F5_PCIE_TX_REPLAY                                                   0x25
++#define ixD2F5_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD2F5_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD2F5_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD2F5_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD2F5_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD2F5_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD2F5_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD2F5_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD2F5_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD2F5_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD2F5_PCIE_FC_P                                                        0x60
++#define ixD2F5_PCIE_FC_NP                                                       0x61
++#define ixD2F5_PCIE_FC_CPL                                                      0x62
++#define ixD2F5_PCIE_ERR_CNTL                                                    0x6a
++#define ixD2F5_PCIE_RX_CNTL                                                     0x70
++#define ixD2F5_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD2F5_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD2F5_PCIE_RX_CNTL3                                                    0x74
++#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD2F5_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD2F5_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD2F5_PCIE_LC_CNTL                                                     0xa0
++#define ixD2F5_PCIE_LC_CNTL2                                                    0xb1
++#define ixD2F5_PCIE_LC_CNTL3                                                    0xb5
++#define ixD2F5_PCIE_LC_CNTL4                                                    0xb6
++#define ixD2F5_PCIE_LC_CNTL5                                                    0xb7
++#define ixD2F5_PCIE_LC_CNTL6                                                    0xbb
++#define ixD2F5_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD2F5_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD2F5_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD2F5_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD2F5_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD2F5_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD2F5_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD2F5_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD2F5_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD2F5_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD2F5_PCIE_LC_STATE0                                                   0xa5
++#define ixD2F5_PCIE_LC_STATE1                                                   0xa6
++#define ixD2F5_PCIE_LC_STATE2                                                   0xa7
++#define ixD2F5_PCIE_LC_STATE3                                                   0xa8
++#define ixD2F5_PCIE_LC_STATE4                                                   0xa9
++#define ixD2F5_PCIE_LC_STATE5                                                   0xaa
++#define ixD2F5_PCIEP_STRAP_LC                                                   0xc0
++#define ixD2F5_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD2F5_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD2F5_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD2F5_PCIEP_HPGI                                                       0xda
++#define ixD2F5_VENDOR_ID                                                        0x6000000
++#define ixD2F5_DEVICE_ID                                                        0x6000000
++#define ixD2F5_COMMAND                                                          0x6000001
++#define ixD2F5_STATUS                                                           0x6000001
++#define ixD2F5_REVISION_ID                                                      0x6000002
++#define ixD2F5_PROG_INTERFACE                                                   0x6000002
++#define ixD2F5_SUB_CLASS                                                        0x6000002
++#define ixD2F5_BASE_CLASS                                                       0x6000002
++#define ixD2F5_CACHE_LINE                                                       0x6000003
++#define ixD2F5_LATENCY                                                          0x6000003
++#define ixD2F5_HEADER                                                           0x6000003
++#define ixD2F5_BIST                                                             0x6000003
++#define ixD2F5_SUB_BUS_NUMBER_LATENCY                                           0x6000006
++#define ixD2F5_IO_BASE_LIMIT                                                    0x6000007
++#define ixD2F5_SECONDARY_STATUS                                                 0x6000007
++#define ixD2F5_MEM_BASE_LIMIT                                                   0x6000008
++#define ixD2F5_PREF_BASE_LIMIT                                                  0x6000009
++#define ixD2F5_PREF_BASE_UPPER                                                  0x600000a
++#define ixD2F5_PREF_LIMIT_UPPER                                                 0x600000b
++#define ixD2F5_IO_BASE_LIMIT_HI                                                 0x600000c
++#define ixD2F5_IRQ_BRIDGE_CNTL                                                  0x600000f
++#define ixD2F5_CAP_PTR                                                          0x600000d
++#define ixD2F5_INTERRUPT_LINE                                                   0x600000f
++#define ixD2F5_INTERRUPT_PIN                                                    0x600000f
++#define ixD2F5_EXT_BRIDGE_CNTL                                                  0x6000010
++#define ixD2F5_PMI_CAP_LIST                                                     0x6000014
++#define ixD2F5_PMI_CAP                                                          0x6000014
++#define ixD2F5_PMI_STATUS_CNTL                                                  0x6000015
++#define ixD2F5_PCIE_CAP_LIST                                                    0x6000016
++#define ixD2F5_PCIE_CAP                                                         0x6000016
++#define ixD2F5_DEVICE_CAP                                                       0x6000017
++#define ixD2F5_DEVICE_CNTL                                                      0x6000018
++#define ixD2F5_DEVICE_STATUS                                                    0x6000018
++#define ixD2F5_LINK_CAP                                                         0x6000019
++#define ixD2F5_LINK_CNTL                                                        0x600001a
++#define ixD2F5_LINK_STATUS                                                      0x600001a
++#define ixD2F5_SLOT_CAP                                                         0x600001b
++#define ixD2F5_SLOT_CNTL                                                        0x600001c
++#define ixD2F5_SLOT_STATUS                                                      0x600001c
++#define ixD2F5_ROOT_CNTL                                                        0x600001d
++#define ixD2F5_ROOT_CAP                                                         0x600001d
++#define ixD2F5_ROOT_STATUS                                                      0x600001e
++#define ixD2F5_DEVICE_CAP2                                                      0x600001f
++#define ixD2F5_DEVICE_CNTL2                                                     0x6000020
++#define ixD2F5_DEVICE_STATUS2                                                   0x6000020
++#define ixD2F5_LINK_CAP2                                                        0x6000021
++#define ixD2F5_LINK_CNTL2                                                       0x6000022
++#define ixD2F5_LINK_STATUS2                                                     0x6000022
++#define ixD2F5_SLOT_CAP2                                                        0x6000023
++#define ixD2F5_SLOT_CNTL2                                                       0x6000024
++#define ixD2F5_SLOT_STATUS2                                                     0x6000024
++#define ixD2F5_MSI_CAP_LIST                                                     0x6000028
++#define ixD2F5_MSI_MSG_CNTL                                                     0x6000028
++#define ixD2F5_MSI_MSG_ADDR_LO                                                  0x6000029
++#define ixD2F5_MSI_MSG_ADDR_HI                                                  0x600002a
++#define ixD2F5_MSI_MSG_DATA_64                                                  0x600002b
++#define ixD2F5_MSI_MSG_DATA                                                     0x600002a
++#define ixD2F5_SSID_CAP_LIST                                                    0x6000030
++#define ixD2F5_SSID_CAP                                                         0x6000031
++#define ixD2F5_MSI_MAP_CAP_LIST                                                 0x6000032
++#define ixD2F5_MSI_MAP_CAP                                                      0x6000032
++#define ixD2F5_MSI_MAP_ADDR_LO                                                  0x6000033
++#define ixD2F5_MSI_MAP_ADDR_HI                                                  0x6000034
++#define ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x6000040
++#define ixD2F5_PCIE_VENDOR_SPECIFIC_HDR                                         0x6000041
++#define ixD2F5_PCIE_VENDOR_SPECIFIC1                                            0x6000042
++#define ixD2F5_PCIE_VENDOR_SPECIFIC2                                            0x6000043
++#define ixD2F5_PCIE_VC_ENH_CAP_LIST                                             0x6000044
++#define ixD2F5_PCIE_PORT_VC_CAP_REG1                                            0x6000045
++#define ixD2F5_PCIE_PORT_VC_CAP_REG2                                            0x6000046
++#define ixD2F5_PCIE_PORT_VC_CNTL                                                0x6000047
++#define ixD2F5_PCIE_PORT_VC_STATUS                                              0x6000047
++#define ixD2F5_PCIE_VC0_RESOURCE_CAP                                            0x6000048
++#define ixD2F5_PCIE_VC0_RESOURCE_CNTL                                           0x6000049
++#define ixD2F5_PCIE_VC0_RESOURCE_STATUS                                         0x600004a
++#define ixD2F5_PCIE_VC1_RESOURCE_CAP                                            0x600004b
++#define ixD2F5_PCIE_VC1_RESOURCE_CNTL                                           0x600004c
++#define ixD2F5_PCIE_VC1_RESOURCE_STATUS                                         0x600004d
++#define ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x6000050
++#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW1                                          0x6000051
++#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW2                                          0x6000052
++#define ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x6000054
++#define ixD2F5_PCIE_UNCORR_ERR_STATUS                                           0x6000055
++#define ixD2F5_PCIE_UNCORR_ERR_MASK                                             0x6000056
++#define ixD2F5_PCIE_UNCORR_ERR_SEVERITY                                         0x6000057
++#define ixD2F5_PCIE_CORR_ERR_STATUS                                             0x6000058
++#define ixD2F5_PCIE_CORR_ERR_MASK                                               0x6000059
++#define ixD2F5_PCIE_ADV_ERR_CAP_CNTL                                            0x600005a
++#define ixD2F5_PCIE_HDR_LOG0                                                    0x600005b
++#define ixD2F5_PCIE_HDR_LOG1                                                    0x600005c
++#define ixD2F5_PCIE_HDR_LOG2                                                    0x600005d
++#define ixD2F5_PCIE_HDR_LOG3                                                    0x600005e
++#define ixD2F5_PCIE_ROOT_ERR_CMD                                                0x600005f
++#define ixD2F5_PCIE_ROOT_ERR_STATUS                                             0x6000060
++#define ixD2F5_PCIE_ERR_SRC_ID                                                  0x6000061
++#define ixD2F5_PCIE_TLP_PREFIX_LOG0                                             0x6000062
++#define ixD2F5_PCIE_TLP_PREFIX_LOG1                                             0x6000063
++#define ixD2F5_PCIE_TLP_PREFIX_LOG2                                             0x6000064
++#define ixD2F5_PCIE_TLP_PREFIX_LOG3                                             0x6000065
++#define ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST                                      0x600009c
++#define ixD2F5_PCIE_LINK_CNTL3                                                  0x600009d
++#define ixD2F5_PCIE_LANE_ERROR_STATUS                                           0x600009e
++#define ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x600009f
++#define ixD2F5_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x600009f
++#define ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x60000a0
++#define ixD2F5_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x60000a0
++#define ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x60000a1
++#define ixD2F5_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x60000a1
++#define ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x60000a2
++#define ixD2F5_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x60000a2
++#define ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x60000a3
++#define ixD2F5_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x60000a3
++#define ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x60000a4
++#define ixD2F5_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x60000a4
++#define ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x60000a5
++#define ixD2F5_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x60000a5
++#define ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x60000a6
++#define ixD2F5_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x60000a6
++#define ixD2F5_PCIE_ACS_ENH_CAP_LIST                                            0x60000a8
++#define ixD2F5_PCIE_ACS_CAP                                                     0x60000a9
++#define ixD2F5_PCIE_ACS_CNTL                                                    0x60000a9
++#define ixD2F5_PCIE_MC_ENH_CAP_LIST                                             0x60000bc
++#define ixD2F5_PCIE_MC_CAP                                                      0x60000bd
++#define ixD2F5_PCIE_MC_CNTL                                                     0x60000bd
++#define ixD2F5_PCIE_MC_ADDR0                                                    0x60000be
++#define ixD2F5_PCIE_MC_ADDR1                                                    0x60000bf
++#define ixD2F5_PCIE_MC_RCV0                                                     0x60000c0
++#define ixD2F5_PCIE_MC_RCV1                                                     0x60000c1
++#define ixD2F5_PCIE_MC_BLOCK_ALL0                                               0x60000c2
++#define ixD2F5_PCIE_MC_BLOCK_ALL1                                               0x60000c3
++#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x60000c4
++#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x60000c5
++#define ixD2F5_PCIE_MC_OVERLAY_BAR0                                             0x60000c6
++#define ixD2F5_PCIE_MC_OVERLAY_BAR1                                             0x60000c7
++#define ixD3F1_PCIE_PORT_INDEX                                                  0x7000038
++#define ixD3F1_PCIE_PORT_DATA                                                   0x7000039
++#define ixD3F1_PCIEP_RESERVED                                                   0x0
++#define ixD3F1_PCIEP_SCRATCH                                                    0x1
++#define ixD3F1_PCIEP_HW_DEBUG                                                   0x2
++#define ixD3F1_PCIEP_PORT_CNTL                                                  0x10
++#define ixD3F1_PCIE_TX_CNTL                                                     0x20
++#define ixD3F1_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD3F1_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD3F1_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD3F1_PCIE_TX_SEQ                                                      0x24
++#define ixD3F1_PCIE_TX_REPLAY                                                   0x25
++#define ixD3F1_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD3F1_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD3F1_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD3F1_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD3F1_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD3F1_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD3F1_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD3F1_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD3F1_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD3F1_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD3F1_PCIE_FC_P                                                        0x60
++#define ixD3F1_PCIE_FC_NP                                                       0x61
++#define ixD3F1_PCIE_FC_CPL                                                      0x62
++#define ixD3F1_PCIE_ERR_CNTL                                                    0x6a
++#define ixD3F1_PCIE_RX_CNTL                                                     0x70
++#define ixD3F1_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD3F1_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD3F1_PCIE_RX_CNTL3                                                    0x74
++#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD3F1_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD3F1_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD3F1_PCIE_LC_CNTL                                                     0xa0
++#define ixD3F1_PCIE_LC_CNTL2                                                    0xb1
++#define ixD3F1_PCIE_LC_CNTL3                                                    0xb5
++#define ixD3F1_PCIE_LC_CNTL4                                                    0xb6
++#define ixD3F1_PCIE_LC_CNTL5                                                    0xb7
++#define ixD3F1_PCIE_LC_CNTL6                                                    0xbb
++#define ixD3F1_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD3F1_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD3F1_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD3F1_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD3F1_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD3F1_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD3F1_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD3F1_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD3F1_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD3F1_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD3F1_PCIE_LC_STATE0                                                   0xa5
++#define ixD3F1_PCIE_LC_STATE1                                                   0xa6
++#define ixD3F1_PCIE_LC_STATE2                                                   0xa7
++#define ixD3F1_PCIE_LC_STATE3                                                   0xa8
++#define ixD3F1_PCIE_LC_STATE4                                                   0xa9
++#define ixD3F1_PCIE_LC_STATE5                                                   0xaa
++#define ixD3F1_PCIEP_STRAP_LC                                                   0xc0
++#define ixD3F1_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD3F1_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD3F1_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD3F1_PCIEP_HPGI                                                       0xda
++#define ixD3F1_VENDOR_ID                                                        0x7000000
++#define ixD3F1_DEVICE_ID                                                        0x7000000
++#define ixD3F1_COMMAND                                                          0x7000001
++#define ixD3F1_STATUS                                                           0x7000001
++#define ixD3F1_REVISION_ID                                                      0x7000002
++#define ixD3F1_PROG_INTERFACE                                                   0x7000002
++#define ixD3F1_SUB_CLASS                                                        0x7000002
++#define ixD3F1_BASE_CLASS                                                       0x7000002
++#define ixD3F1_CACHE_LINE                                                       0x7000003
++#define ixD3F1_LATENCY                                                          0x7000003
++#define ixD3F1_HEADER                                                           0x7000003
++#define ixD3F1_BIST                                                             0x7000003
++#define ixD3F1_SUB_BUS_NUMBER_LATENCY                                           0x7000006
++#define ixD3F1_IO_BASE_LIMIT                                                    0x7000007
++#define ixD3F1_SECONDARY_STATUS                                                 0x7000007
++#define ixD3F1_MEM_BASE_LIMIT                                                   0x7000008
++#define ixD3F1_PREF_BASE_LIMIT                                                  0x7000009
++#define ixD3F1_PREF_BASE_UPPER                                                  0x700000a
++#define ixD3F1_PREF_LIMIT_UPPER                                                 0x700000b
++#define ixD3F1_IO_BASE_LIMIT_HI                                                 0x700000c
++#define ixD3F1_IRQ_BRIDGE_CNTL                                                  0x700000f
++#define ixD3F1_CAP_PTR                                                          0x700000d
++#define ixD3F1_INTERRUPT_LINE                                                   0x700000f
++#define ixD3F1_INTERRUPT_PIN                                                    0x700000f
++#define ixD3F1_EXT_BRIDGE_CNTL                                                  0x7000010
++#define ixD3F1_PMI_CAP_LIST                                                     0x7000014
++#define ixD3F1_PMI_CAP                                                          0x7000014
++#define ixD3F1_PMI_STATUS_CNTL                                                  0x7000015
++#define ixD3F1_PCIE_CAP_LIST                                                    0x7000016
++#define ixD3F1_PCIE_CAP                                                         0x7000016
++#define ixD3F1_DEVICE_CAP                                                       0x7000017
++#define ixD3F1_DEVICE_CNTL                                                      0x7000018
++#define ixD3F1_DEVICE_STATUS                                                    0x7000018
++#define ixD3F1_LINK_CAP                                                         0x7000019
++#define ixD3F1_LINK_CNTL                                                        0x700001a
++#define ixD3F1_LINK_STATUS                                                      0x700001a
++#define ixD3F1_SLOT_CAP                                                         0x700001b
++#define ixD3F1_SLOT_CNTL                                                        0x700001c
++#define ixD3F1_SLOT_STATUS                                                      0x700001c
++#define ixD3F1_ROOT_CNTL                                                        0x700001d
++#define ixD3F1_ROOT_CAP                                                         0x700001d
++#define ixD3F1_ROOT_STATUS                                                      0x700001e
++#define ixD3F1_DEVICE_CAP2                                                      0x700001f
++#define ixD3F1_DEVICE_CNTL2                                                     0x7000020
++#define ixD3F1_DEVICE_STATUS2                                                   0x7000020
++#define ixD3F1_LINK_CAP2                                                        0x7000021
++#define ixD3F1_LINK_CNTL2                                                       0x7000022
++#define ixD3F1_LINK_STATUS2                                                     0x7000022
++#define ixD3F1_SLOT_CAP2                                                        0x7000023
++#define ixD3F1_SLOT_CNTL2                                                       0x7000024
++#define ixD3F1_SLOT_STATUS2                                                     0x7000024
++#define ixD3F1_MSI_CAP_LIST                                                     0x7000028
++#define ixD3F1_MSI_MSG_CNTL                                                     0x7000028
++#define ixD3F1_MSI_MSG_ADDR_LO                                                  0x7000029
++#define ixD3F1_MSI_MSG_ADDR_HI                                                  0x700002a
++#define ixD3F1_MSI_MSG_DATA_64                                                  0x700002b
++#define ixD3F1_MSI_MSG_DATA                                                     0x700002a
++#define ixD3F1_SSID_CAP_LIST                                                    0x7000030
++#define ixD3F1_SSID_CAP                                                         0x7000031
++#define ixD3F1_MSI_MAP_CAP_LIST                                                 0x7000032
++#define ixD3F1_MSI_MAP_CAP                                                      0x7000032
++#define ixD3F1_MSI_MAP_ADDR_LO                                                  0x7000033
++#define ixD3F1_MSI_MAP_ADDR_HI                                                  0x7000034
++#define ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x7000040
++#define ixD3F1_PCIE_VENDOR_SPECIFIC_HDR                                         0x7000041
++#define ixD3F1_PCIE_VENDOR_SPECIFIC1                                            0x7000042
++#define ixD3F1_PCIE_VENDOR_SPECIFIC2                                            0x7000043
++#define ixD3F1_PCIE_VC_ENH_CAP_LIST                                             0x7000044
++#define ixD3F1_PCIE_PORT_VC_CAP_REG1                                            0x7000045
++#define ixD3F1_PCIE_PORT_VC_CAP_REG2                                            0x7000046
++#define ixD3F1_PCIE_PORT_VC_CNTL                                                0x7000047
++#define ixD3F1_PCIE_PORT_VC_STATUS                                              0x7000047
++#define ixD3F1_PCIE_VC0_RESOURCE_CAP                                            0x7000048
++#define ixD3F1_PCIE_VC0_RESOURCE_CNTL                                           0x7000049
++#define ixD3F1_PCIE_VC0_RESOURCE_STATUS                                         0x700004a
++#define ixD3F1_PCIE_VC1_RESOURCE_CAP                                            0x700004b
++#define ixD3F1_PCIE_VC1_RESOURCE_CNTL                                           0x700004c
++#define ixD3F1_PCIE_VC1_RESOURCE_STATUS                                         0x700004d
++#define ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x7000050
++#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW1                                          0x7000051
++#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW2                                          0x7000052
++#define ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x7000054
++#define ixD3F1_PCIE_UNCORR_ERR_STATUS                                           0x7000055
++#define ixD3F1_PCIE_UNCORR_ERR_MASK                                             0x7000056
++#define ixD3F1_PCIE_UNCORR_ERR_SEVERITY                                         0x7000057
++#define ixD3F1_PCIE_CORR_ERR_STATUS                                             0x7000058
++#define ixD3F1_PCIE_CORR_ERR_MASK                                               0x7000059
++#define ixD3F1_PCIE_ADV_ERR_CAP_CNTL                                            0x700005a
++#define ixD3F1_PCIE_HDR_LOG0                                                    0x700005b
++#define ixD3F1_PCIE_HDR_LOG1                                                    0x700005c
++#define ixD3F1_PCIE_HDR_LOG2                                                    0x700005d
++#define ixD3F1_PCIE_HDR_LOG3                                                    0x700005e
++#define ixD3F1_PCIE_ROOT_ERR_CMD                                                0x700005f
++#define ixD3F1_PCIE_ROOT_ERR_STATUS                                             0x7000060
++#define ixD3F1_PCIE_ERR_SRC_ID                                                  0x7000061
++#define ixD3F1_PCIE_TLP_PREFIX_LOG0                                             0x7000062
++#define ixD3F1_PCIE_TLP_PREFIX_LOG1                                             0x7000063
++#define ixD3F1_PCIE_TLP_PREFIX_LOG2                                             0x7000064
++#define ixD3F1_PCIE_TLP_PREFIX_LOG3                                             0x7000065
++#define ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST                                      0x700009c
++#define ixD3F1_PCIE_LINK_CNTL3                                                  0x700009d
++#define ixD3F1_PCIE_LANE_ERROR_STATUS                                           0x700009e
++#define ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x700009f
++#define ixD3F1_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x700009f
++#define ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x70000a0
++#define ixD3F1_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x70000a0
++#define ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x70000a1
++#define ixD3F1_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x70000a1
++#define ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x70000a2
++#define ixD3F1_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x70000a2
++#define ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x70000a3
++#define ixD3F1_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x70000a3
++#define ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x70000a4
++#define ixD3F1_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x70000a4
++#define ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x70000a5
++#define ixD3F1_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x70000a5
++#define ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x70000a6
++#define ixD3F1_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x70000a6
++#define ixD3F1_PCIE_ACS_ENH_CAP_LIST                                            0x70000a8
++#define ixD3F1_PCIE_ACS_CAP                                                     0x70000a9
++#define ixD3F1_PCIE_ACS_CNTL                                                    0x70000a9
++#define ixD3F1_PCIE_MC_ENH_CAP_LIST                                             0x70000bc
++#define ixD3F1_PCIE_MC_CAP                                                      0x70000bd
++#define ixD3F1_PCIE_MC_CNTL                                                     0x70000bd
++#define ixD3F1_PCIE_MC_ADDR0                                                    0x70000be
++#define ixD3F1_PCIE_MC_ADDR1                                                    0x70000bf
++#define ixD3F1_PCIE_MC_RCV0                                                     0x70000c0
++#define ixD3F1_PCIE_MC_RCV1                                                     0x70000c1
++#define ixD3F1_PCIE_MC_BLOCK_ALL0                                               0x70000c2
++#define ixD3F1_PCIE_MC_BLOCK_ALL1                                               0x70000c3
++#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x70000c4
++#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x70000c5
++#define ixD3F1_PCIE_MC_OVERLAY_BAR0                                             0x70000c6
++#define ixD3F1_PCIE_MC_OVERLAY_BAR1                                             0x70000c7
++#define ixD3F2_PCIE_PORT_INDEX                                                  0x8000038
++#define ixD3F2_PCIE_PORT_DATA                                                   0x8000039
++#define ixD3F2_PCIEP_RESERVED                                                   0x0
++#define ixD3F2_PCIEP_SCRATCH                                                    0x1
++#define ixD3F2_PCIEP_HW_DEBUG                                                   0x2
++#define ixD3F2_PCIEP_PORT_CNTL                                                  0x10
++#define ixD3F2_PCIE_TX_CNTL                                                     0x20
++#define ixD3F2_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD3F2_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD3F2_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD3F2_PCIE_TX_SEQ                                                      0x24
++#define ixD3F2_PCIE_TX_REPLAY                                                   0x25
++#define ixD3F2_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD3F2_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD3F2_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD3F2_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD3F2_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD3F2_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD3F2_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD3F2_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD3F2_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD3F2_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD3F2_PCIE_FC_P                                                        0x60
++#define ixD3F2_PCIE_FC_NP                                                       0x61
++#define ixD3F2_PCIE_FC_CPL                                                      0x62
++#define ixD3F2_PCIE_ERR_CNTL                                                    0x6a
++#define ixD3F2_PCIE_RX_CNTL                                                     0x70
++#define ixD3F2_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD3F2_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD3F2_PCIE_RX_CNTL3                                                    0x74
++#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD3F2_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD3F2_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD3F2_PCIE_LC_CNTL                                                     0xa0
++#define ixD3F2_PCIE_LC_CNTL2                                                    0xb1
++#define ixD3F2_PCIE_LC_CNTL3                                                    0xb5
++#define ixD3F2_PCIE_LC_CNTL4                                                    0xb6
++#define ixD3F2_PCIE_LC_CNTL5                                                    0xb7
++#define ixD3F2_PCIE_LC_CNTL6                                                    0xbb
++#define ixD3F2_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD3F2_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD3F2_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD3F2_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD3F2_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD3F2_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD3F2_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD3F2_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD3F2_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD3F2_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD3F2_PCIE_LC_STATE0                                                   0xa5
++#define ixD3F2_PCIE_LC_STATE1                                                   0xa6
++#define ixD3F2_PCIE_LC_STATE2                                                   0xa7
++#define ixD3F2_PCIE_LC_STATE3                                                   0xa8
++#define ixD3F2_PCIE_LC_STATE4                                                   0xa9
++#define ixD3F2_PCIE_LC_STATE5                                                   0xaa
++#define ixD3F2_PCIEP_STRAP_LC                                                   0xc0
++#define ixD3F2_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD3F2_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD3F2_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD3F2_PCIEP_HPGI                                                       0xda
++#define ixD3F2_VENDOR_ID                                                        0x8000000
++#define ixD3F2_DEVICE_ID                                                        0x8000000
++#define ixD3F2_COMMAND                                                          0x8000001
++#define ixD3F2_STATUS                                                           0x8000001
++#define ixD3F2_REVISION_ID                                                      0x8000002
++#define ixD3F2_PROG_INTERFACE                                                   0x8000002
++#define ixD3F2_SUB_CLASS                                                        0x8000002
++#define ixD3F2_BASE_CLASS                                                       0x8000002
++#define ixD3F2_CACHE_LINE                                                       0x8000003
++#define ixD3F2_LATENCY                                                          0x8000003
++#define ixD3F2_HEADER                                                           0x8000003
++#define ixD3F2_BIST                                                             0x8000003
++#define ixD3F2_SUB_BUS_NUMBER_LATENCY                                           0x8000006
++#define ixD3F2_IO_BASE_LIMIT                                                    0x8000007
++#define ixD3F2_SECONDARY_STATUS                                                 0x8000007
++#define ixD3F2_MEM_BASE_LIMIT                                                   0x8000008
++#define ixD3F2_PREF_BASE_LIMIT                                                  0x8000009
++#define ixD3F2_PREF_BASE_UPPER                                                  0x800000a
++#define ixD3F2_PREF_LIMIT_UPPER                                                 0x800000b
++#define ixD3F2_IO_BASE_LIMIT_HI                                                 0x800000c
++#define ixD3F2_IRQ_BRIDGE_CNTL                                                  0x800000f
++#define ixD3F2_CAP_PTR                                                          0x800000d
++#define ixD3F2_INTERRUPT_LINE                                                   0x800000f
++#define ixD3F2_INTERRUPT_PIN                                                    0x800000f
++#define ixD3F2_EXT_BRIDGE_CNTL                                                  0x8000010
++#define ixD3F2_PMI_CAP_LIST                                                     0x8000014
++#define ixD3F2_PMI_CAP                                                          0x8000014
++#define ixD3F2_PMI_STATUS_CNTL                                                  0x8000015
++#define ixD3F2_PCIE_CAP_LIST                                                    0x8000016
++#define ixD3F2_PCIE_CAP                                                         0x8000016
++#define ixD3F2_DEVICE_CAP                                                       0x8000017
++#define ixD3F2_DEVICE_CNTL                                                      0x8000018
++#define ixD3F2_DEVICE_STATUS                                                    0x8000018
++#define ixD3F2_LINK_CAP                                                         0x8000019
++#define ixD3F2_LINK_CNTL                                                        0x800001a
++#define ixD3F2_LINK_STATUS                                                      0x800001a
++#define ixD3F2_SLOT_CAP                                                         0x800001b
++#define ixD3F2_SLOT_CNTL                                                        0x800001c
++#define ixD3F2_SLOT_STATUS                                                      0x800001c
++#define ixD3F2_ROOT_CNTL                                                        0x800001d
++#define ixD3F2_ROOT_CAP                                                         0x800001d
++#define ixD3F2_ROOT_STATUS                                                      0x800001e
++#define ixD3F2_DEVICE_CAP2                                                      0x800001f
++#define ixD3F2_DEVICE_CNTL2                                                     0x8000020
++#define ixD3F2_DEVICE_STATUS2                                                   0x8000020
++#define ixD3F2_LINK_CAP2                                                        0x8000021
++#define ixD3F2_LINK_CNTL2                                                       0x8000022
++#define ixD3F2_LINK_STATUS2                                                     0x8000022
++#define ixD3F2_SLOT_CAP2                                                        0x8000023
++#define ixD3F2_SLOT_CNTL2                                                       0x8000024
++#define ixD3F2_SLOT_STATUS2                                                     0x8000024
++#define ixD3F2_MSI_CAP_LIST                                                     0x8000028
++#define ixD3F2_MSI_MSG_CNTL                                                     0x8000028
++#define ixD3F2_MSI_MSG_ADDR_LO                                                  0x8000029
++#define ixD3F2_MSI_MSG_ADDR_HI                                                  0x800002a
++#define ixD3F2_MSI_MSG_DATA_64                                                  0x800002b
++#define ixD3F2_MSI_MSG_DATA                                                     0x800002a
++#define ixD3F2_SSID_CAP_LIST                                                    0x8000030
++#define ixD3F2_SSID_CAP                                                         0x8000031
++#define ixD3F2_MSI_MAP_CAP_LIST                                                 0x8000032
++#define ixD3F2_MSI_MAP_CAP                                                      0x8000032
++#define ixD3F2_MSI_MAP_ADDR_LO                                                  0x8000033
++#define ixD3F2_MSI_MAP_ADDR_HI                                                  0x8000034
++#define ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x8000040
++#define ixD3F2_PCIE_VENDOR_SPECIFIC_HDR                                         0x8000041
++#define ixD3F2_PCIE_VENDOR_SPECIFIC1                                            0x8000042
++#define ixD3F2_PCIE_VENDOR_SPECIFIC2                                            0x8000043
++#define ixD3F2_PCIE_VC_ENH_CAP_LIST                                             0x8000044
++#define ixD3F2_PCIE_PORT_VC_CAP_REG1                                            0x8000045
++#define ixD3F2_PCIE_PORT_VC_CAP_REG2                                            0x8000046
++#define ixD3F2_PCIE_PORT_VC_CNTL                                                0x8000047
++#define ixD3F2_PCIE_PORT_VC_STATUS                                              0x8000047
++#define ixD3F2_PCIE_VC0_RESOURCE_CAP                                            0x8000048
++#define ixD3F2_PCIE_VC0_RESOURCE_CNTL                                           0x8000049
++#define ixD3F2_PCIE_VC0_RESOURCE_STATUS                                         0x800004a
++#define ixD3F2_PCIE_VC1_RESOURCE_CAP                                            0x800004b
++#define ixD3F2_PCIE_VC1_RESOURCE_CNTL                                           0x800004c
++#define ixD3F2_PCIE_VC1_RESOURCE_STATUS                                         0x800004d
++#define ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x8000050
++#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW1                                          0x8000051
++#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW2                                          0x8000052
++#define ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x8000054
++#define ixD3F2_PCIE_UNCORR_ERR_STATUS                                           0x8000055
++#define ixD3F2_PCIE_UNCORR_ERR_MASK                                             0x8000056
++#define ixD3F2_PCIE_UNCORR_ERR_SEVERITY                                         0x8000057
++#define ixD3F2_PCIE_CORR_ERR_STATUS                                             0x8000058
++#define ixD3F2_PCIE_CORR_ERR_MASK                                               0x8000059
++#define ixD3F2_PCIE_ADV_ERR_CAP_CNTL                                            0x800005a
++#define ixD3F2_PCIE_HDR_LOG0                                                    0x800005b
++#define ixD3F2_PCIE_HDR_LOG1                                                    0x800005c
++#define ixD3F2_PCIE_HDR_LOG2                                                    0x800005d
++#define ixD3F2_PCIE_HDR_LOG3                                                    0x800005e
++#define ixD3F2_PCIE_ROOT_ERR_CMD                                                0x800005f
++#define ixD3F2_PCIE_ROOT_ERR_STATUS                                             0x8000060
++#define ixD3F2_PCIE_ERR_SRC_ID                                                  0x8000061
++#define ixD3F2_PCIE_TLP_PREFIX_LOG0                                             0x8000062
++#define ixD3F2_PCIE_TLP_PREFIX_LOG1                                             0x8000063
++#define ixD3F2_PCIE_TLP_PREFIX_LOG2                                             0x8000064
++#define ixD3F2_PCIE_TLP_PREFIX_LOG3                                             0x8000065
++#define ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST                                      0x800009c
++#define ixD3F2_PCIE_LINK_CNTL3                                                  0x800009d
++#define ixD3F2_PCIE_LANE_ERROR_STATUS                                           0x800009e
++#define ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x800009f
++#define ixD3F2_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x800009f
++#define ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x80000a0
++#define ixD3F2_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x80000a0
++#define ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x80000a1
++#define ixD3F2_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x80000a1
++#define ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x80000a2
++#define ixD3F2_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x80000a2
++#define ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x80000a3
++#define ixD3F2_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x80000a3
++#define ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x80000a4
++#define ixD3F2_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x80000a4
++#define ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x80000a5
++#define ixD3F2_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x80000a5
++#define ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x80000a6
++#define ixD3F2_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x80000a6
++#define ixD3F2_PCIE_ACS_ENH_CAP_LIST                                            0x80000a8
++#define ixD3F2_PCIE_ACS_CAP                                                     0x80000a9
++#define ixD3F2_PCIE_ACS_CNTL                                                    0x80000a9
++#define ixD3F2_PCIE_MC_ENH_CAP_LIST                                             0x80000bc
++#define ixD3F2_PCIE_MC_CAP                                                      0x80000bd
++#define ixD3F2_PCIE_MC_CNTL                                                     0x80000bd
++#define ixD3F2_PCIE_MC_ADDR0                                                    0x80000be
++#define ixD3F2_PCIE_MC_ADDR1                                                    0x80000bf
++#define ixD3F2_PCIE_MC_RCV0                                                     0x80000c0
++#define ixD3F2_PCIE_MC_RCV1                                                     0x80000c1
++#define ixD3F2_PCIE_MC_BLOCK_ALL0                                               0x80000c2
++#define ixD3F2_PCIE_MC_BLOCK_ALL1                                               0x80000c3
++#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x80000c4
++#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x80000c5
++#define ixD3F2_PCIE_MC_OVERLAY_BAR0                                             0x80000c6
++#define ixD3F2_PCIE_MC_OVERLAY_BAR1                                             0x80000c7
++#define ixD3F3_PCIE_PORT_INDEX                                                  0x9000038
++#define ixD3F3_PCIE_PORT_DATA                                                   0x9000039
++#define ixD3F3_PCIEP_RESERVED                                                   0x0
++#define ixD3F3_PCIEP_SCRATCH                                                    0x1
++#define ixD3F3_PCIEP_HW_DEBUG                                                   0x2
++#define ixD3F3_PCIEP_PORT_CNTL                                                  0x10
++#define ixD3F3_PCIE_TX_CNTL                                                     0x20
++#define ixD3F3_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD3F3_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD3F3_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD3F3_PCIE_TX_SEQ                                                      0x24
++#define ixD3F3_PCIE_TX_REPLAY                                                   0x25
++#define ixD3F3_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD3F3_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD3F3_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD3F3_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD3F3_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD3F3_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD3F3_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD3F3_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD3F3_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD3F3_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD3F3_PCIE_FC_P                                                        0x60
++#define ixD3F3_PCIE_FC_NP                                                       0x61
++#define ixD3F3_PCIE_FC_CPL                                                      0x62
++#define ixD3F3_PCIE_ERR_CNTL                                                    0x6a
++#define ixD3F3_PCIE_RX_CNTL                                                     0x70
++#define ixD3F3_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD3F3_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD3F3_PCIE_RX_CNTL3                                                    0x74
++#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD3F3_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD3F3_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD3F3_PCIE_LC_CNTL                                                     0xa0
++#define ixD3F3_PCIE_LC_CNTL2                                                    0xb1
++#define ixD3F3_PCIE_LC_CNTL3                                                    0xb5
++#define ixD3F3_PCIE_LC_CNTL4                                                    0xb6
++#define ixD3F3_PCIE_LC_CNTL5                                                    0xb7
++#define ixD3F3_PCIE_LC_CNTL6                                                    0xbb
++#define ixD3F3_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD3F3_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD3F3_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD3F3_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD3F3_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD3F3_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD3F3_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD3F3_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD3F3_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD3F3_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD3F3_PCIE_LC_STATE0                                                   0xa5
++#define ixD3F3_PCIE_LC_STATE1                                                   0xa6
++#define ixD3F3_PCIE_LC_STATE2                                                   0xa7
++#define ixD3F3_PCIE_LC_STATE3                                                   0xa8
++#define ixD3F3_PCIE_LC_STATE4                                                   0xa9
++#define ixD3F3_PCIE_LC_STATE5                                                   0xaa
++#define ixD3F3_PCIEP_STRAP_LC                                                   0xc0
++#define ixD3F3_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD3F3_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD3F3_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD3F3_PCIEP_HPGI                                                       0xda
++#define ixD3F3_VENDOR_ID                                                        0x9000000
++#define ixD3F3_DEVICE_ID                                                        0x9000000
++#define ixD3F3_COMMAND                                                          0x9000001
++#define ixD3F3_STATUS                                                           0x9000001
++#define ixD3F3_REVISION_ID                                                      0x9000002
++#define ixD3F3_PROG_INTERFACE                                                   0x9000002
++#define ixD3F3_SUB_CLASS                                                        0x9000002
++#define ixD3F3_BASE_CLASS                                                       0x9000002
++#define ixD3F3_CACHE_LINE                                                       0x9000003
++#define ixD3F3_LATENCY                                                          0x9000003
++#define ixD3F3_HEADER                                                           0x9000003
++#define ixD3F3_BIST                                                             0x9000003
++#define ixD3F3_SUB_BUS_NUMBER_LATENCY                                           0x9000006
++#define ixD3F3_IO_BASE_LIMIT                                                    0x9000007
++#define ixD3F3_SECONDARY_STATUS                                                 0x9000007
++#define ixD3F3_MEM_BASE_LIMIT                                                   0x9000008
++#define ixD3F3_PREF_BASE_LIMIT                                                  0x9000009
++#define ixD3F3_PREF_BASE_UPPER                                                  0x900000a
++#define ixD3F3_PREF_LIMIT_UPPER                                                 0x900000b
++#define ixD3F3_IO_BASE_LIMIT_HI                                                 0x900000c
++#define ixD3F3_IRQ_BRIDGE_CNTL                                                  0x900000f
++#define ixD3F3_CAP_PTR                                                          0x900000d
++#define ixD3F3_INTERRUPT_LINE                                                   0x900000f
++#define ixD3F3_INTERRUPT_PIN                                                    0x900000f
++#define ixD3F3_EXT_BRIDGE_CNTL                                                  0x9000010
++#define ixD3F3_PMI_CAP_LIST                                                     0x9000014
++#define ixD3F3_PMI_CAP                                                          0x9000014
++#define ixD3F3_PMI_STATUS_CNTL                                                  0x9000015
++#define ixD3F3_PCIE_CAP_LIST                                                    0x9000016
++#define ixD3F3_PCIE_CAP                                                         0x9000016
++#define ixD3F3_DEVICE_CAP                                                       0x9000017
++#define ixD3F3_DEVICE_CNTL                                                      0x9000018
++#define ixD3F3_DEVICE_STATUS                                                    0x9000018
++#define ixD3F3_LINK_CAP                                                         0x9000019
++#define ixD3F3_LINK_CNTL                                                        0x900001a
++#define ixD3F3_LINK_STATUS                                                      0x900001a
++#define ixD3F3_SLOT_CAP                                                         0x900001b
++#define ixD3F3_SLOT_CNTL                                                        0x900001c
++#define ixD3F3_SLOT_STATUS                                                      0x900001c
++#define ixD3F3_ROOT_CNTL                                                        0x900001d
++#define ixD3F3_ROOT_CAP                                                         0x900001d
++#define ixD3F3_ROOT_STATUS                                                      0x900001e
++#define ixD3F3_DEVICE_CAP2                                                      0x900001f
++#define ixD3F3_DEVICE_CNTL2                                                     0x9000020
++#define ixD3F3_DEVICE_STATUS2                                                   0x9000020
++#define ixD3F3_LINK_CAP2                                                        0x9000021
++#define ixD3F3_LINK_CNTL2                                                       0x9000022
++#define ixD3F3_LINK_STATUS2                                                     0x9000022
++#define ixD3F3_SLOT_CAP2                                                        0x9000023
++#define ixD3F3_SLOT_CNTL2                                                       0x9000024
++#define ixD3F3_SLOT_STATUS2                                                     0x9000024
++#define ixD3F3_MSI_CAP_LIST                                                     0x9000028
++#define ixD3F3_MSI_MSG_CNTL                                                     0x9000028
++#define ixD3F3_MSI_MSG_ADDR_LO                                                  0x9000029
++#define ixD3F3_MSI_MSG_ADDR_HI                                                  0x900002a
++#define ixD3F3_MSI_MSG_DATA_64                                                  0x900002b
++#define ixD3F3_MSI_MSG_DATA                                                     0x900002a
++#define ixD3F3_SSID_CAP_LIST                                                    0x9000030
++#define ixD3F3_SSID_CAP                                                         0x9000031
++#define ixD3F3_MSI_MAP_CAP_LIST                                                 0x9000032
++#define ixD3F3_MSI_MAP_CAP                                                      0x9000032
++#define ixD3F3_MSI_MAP_ADDR_LO                                                  0x9000033
++#define ixD3F3_MSI_MAP_ADDR_HI                                                  0x9000034
++#define ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0x9000040
++#define ixD3F3_PCIE_VENDOR_SPECIFIC_HDR                                         0x9000041
++#define ixD3F3_PCIE_VENDOR_SPECIFIC1                                            0x9000042
++#define ixD3F3_PCIE_VENDOR_SPECIFIC2                                            0x9000043
++#define ixD3F3_PCIE_VC_ENH_CAP_LIST                                             0x9000044
++#define ixD3F3_PCIE_PORT_VC_CAP_REG1                                            0x9000045
++#define ixD3F3_PCIE_PORT_VC_CAP_REG2                                            0x9000046
++#define ixD3F3_PCIE_PORT_VC_CNTL                                                0x9000047
++#define ixD3F3_PCIE_PORT_VC_STATUS                                              0x9000047
++#define ixD3F3_PCIE_VC0_RESOURCE_CAP                                            0x9000048
++#define ixD3F3_PCIE_VC0_RESOURCE_CNTL                                           0x9000049
++#define ixD3F3_PCIE_VC0_RESOURCE_STATUS                                         0x900004a
++#define ixD3F3_PCIE_VC1_RESOURCE_CAP                                            0x900004b
++#define ixD3F3_PCIE_VC1_RESOURCE_CNTL                                           0x900004c
++#define ixD3F3_PCIE_VC1_RESOURCE_STATUS                                         0x900004d
++#define ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0x9000050
++#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW1                                          0x9000051
++#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW2                                          0x9000052
++#define ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0x9000054
++#define ixD3F3_PCIE_UNCORR_ERR_STATUS                                           0x9000055
++#define ixD3F3_PCIE_UNCORR_ERR_MASK                                             0x9000056
++#define ixD3F3_PCIE_UNCORR_ERR_SEVERITY                                         0x9000057
++#define ixD3F3_PCIE_CORR_ERR_STATUS                                             0x9000058
++#define ixD3F3_PCIE_CORR_ERR_MASK                                               0x9000059
++#define ixD3F3_PCIE_ADV_ERR_CAP_CNTL                                            0x900005a
++#define ixD3F3_PCIE_HDR_LOG0                                                    0x900005b
++#define ixD3F3_PCIE_HDR_LOG1                                                    0x900005c
++#define ixD3F3_PCIE_HDR_LOG2                                                    0x900005d
++#define ixD3F3_PCIE_HDR_LOG3                                                    0x900005e
++#define ixD3F3_PCIE_ROOT_ERR_CMD                                                0x900005f
++#define ixD3F3_PCIE_ROOT_ERR_STATUS                                             0x9000060
++#define ixD3F3_PCIE_ERR_SRC_ID                                                  0x9000061
++#define ixD3F3_PCIE_TLP_PREFIX_LOG0                                             0x9000062
++#define ixD3F3_PCIE_TLP_PREFIX_LOG1                                             0x9000063
++#define ixD3F3_PCIE_TLP_PREFIX_LOG2                                             0x9000064
++#define ixD3F3_PCIE_TLP_PREFIX_LOG3                                             0x9000065
++#define ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST                                      0x900009c
++#define ixD3F3_PCIE_LINK_CNTL3                                                  0x900009d
++#define ixD3F3_PCIE_LANE_ERROR_STATUS                                           0x900009e
++#define ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL                                    0x900009f
++#define ixD3F3_PCIE_LANE_1_EQUALIZATION_CNTL                                    0x900009f
++#define ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL                                    0x90000a0
++#define ixD3F3_PCIE_LANE_3_EQUALIZATION_CNTL                                    0x90000a0
++#define ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL                                    0x90000a1
++#define ixD3F3_PCIE_LANE_5_EQUALIZATION_CNTL                                    0x90000a1
++#define ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL                                    0x90000a2
++#define ixD3F3_PCIE_LANE_7_EQUALIZATION_CNTL                                    0x90000a2
++#define ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL                                    0x90000a3
++#define ixD3F3_PCIE_LANE_9_EQUALIZATION_CNTL                                    0x90000a3
++#define ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL                                   0x90000a4
++#define ixD3F3_PCIE_LANE_11_EQUALIZATION_CNTL                                   0x90000a4
++#define ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL                                   0x90000a5
++#define ixD3F3_PCIE_LANE_13_EQUALIZATION_CNTL                                   0x90000a5
++#define ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL                                   0x90000a6
++#define ixD3F3_PCIE_LANE_15_EQUALIZATION_CNTL                                   0x90000a6
++#define ixD3F3_PCIE_ACS_ENH_CAP_LIST                                            0x90000a8
++#define ixD3F3_PCIE_ACS_CAP                                                     0x90000a9
++#define ixD3F3_PCIE_ACS_CNTL                                                    0x90000a9
++#define ixD3F3_PCIE_MC_ENH_CAP_LIST                                             0x90000bc
++#define ixD3F3_PCIE_MC_CAP                                                      0x90000bd
++#define ixD3F3_PCIE_MC_CNTL                                                     0x90000bd
++#define ixD3F3_PCIE_MC_ADDR0                                                    0x90000be
++#define ixD3F3_PCIE_MC_ADDR1                                                    0x90000bf
++#define ixD3F3_PCIE_MC_RCV0                                                     0x90000c0
++#define ixD3F3_PCIE_MC_RCV1                                                     0x90000c1
++#define ixD3F3_PCIE_MC_BLOCK_ALL0                                               0x90000c2
++#define ixD3F3_PCIE_MC_BLOCK_ALL1                                               0x90000c3
++#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0x90000c4
++#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0x90000c5
++#define ixD3F3_PCIE_MC_OVERLAY_BAR0                                             0x90000c6
++#define ixD3F3_PCIE_MC_OVERLAY_BAR1                                             0x90000c7
++#define ixD3F4_PCIE_PORT_INDEX                                                  0xa000038
++#define ixD3F4_PCIE_PORT_DATA                                                   0xa000039
++#define ixD3F4_PCIEP_RESERVED                                                   0x0
++#define ixD3F4_PCIEP_SCRATCH                                                    0x1
++#define ixD3F4_PCIEP_HW_DEBUG                                                   0x2
++#define ixD3F4_PCIEP_PORT_CNTL                                                  0x10
++#define ixD3F4_PCIE_TX_CNTL                                                     0x20
++#define ixD3F4_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD3F4_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD3F4_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD3F4_PCIE_TX_SEQ                                                      0x24
++#define ixD3F4_PCIE_TX_REPLAY                                                   0x25
++#define ixD3F4_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD3F4_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD3F4_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD3F4_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD3F4_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD3F4_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD3F4_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD3F4_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD3F4_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD3F4_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD3F4_PCIE_FC_P                                                        0x60
++#define ixD3F4_PCIE_FC_NP                                                       0x61
++#define ixD3F4_PCIE_FC_CPL                                                      0x62
++#define ixD3F4_PCIE_ERR_CNTL                                                    0x6a
++#define ixD3F4_PCIE_RX_CNTL                                                     0x70
++#define ixD3F4_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD3F4_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD3F4_PCIE_RX_CNTL3                                                    0x74
++#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD3F4_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD3F4_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD3F4_PCIE_LC_CNTL                                                     0xa0
++#define ixD3F4_PCIE_LC_CNTL2                                                    0xb1
++#define ixD3F4_PCIE_LC_CNTL3                                                    0xb5
++#define ixD3F4_PCIE_LC_CNTL4                                                    0xb6
++#define ixD3F4_PCIE_LC_CNTL5                                                    0xb7
++#define ixD3F4_PCIE_LC_CNTL6                                                    0xbb
++#define ixD3F4_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD3F4_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD3F4_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD3F4_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD3F4_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD3F4_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD3F4_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD3F4_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD3F4_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD3F4_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD3F4_PCIE_LC_STATE0                                                   0xa5
++#define ixD3F4_PCIE_LC_STATE1                                                   0xa6
++#define ixD3F4_PCIE_LC_STATE2                                                   0xa7
++#define ixD3F4_PCIE_LC_STATE3                                                   0xa8
++#define ixD3F4_PCIE_LC_STATE4                                                   0xa9
++#define ixD3F4_PCIE_LC_STATE5                                                   0xaa
++#define ixD3F4_PCIEP_STRAP_LC                                                   0xc0
++#define ixD3F4_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD3F4_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD3F4_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD3F4_PCIEP_HPGI                                                       0xda
++#define ixD3F4_VENDOR_ID                                                        0xa000000
++#define ixD3F4_DEVICE_ID                                                        0xa000000
++#define ixD3F4_COMMAND                                                          0xa000001
++#define ixD3F4_STATUS                                                           0xa000001
++#define ixD3F4_REVISION_ID                                                      0xa000002
++#define ixD3F4_PROG_INTERFACE                                                   0xa000002
++#define ixD3F4_SUB_CLASS                                                        0xa000002
++#define ixD3F4_BASE_CLASS                                                       0xa000002
++#define ixD3F4_CACHE_LINE                                                       0xa000003
++#define ixD3F4_LATENCY                                                          0xa000003
++#define ixD3F4_HEADER                                                           0xa000003
++#define ixD3F4_BIST                                                             0xa000003
++#define ixD3F4_SUB_BUS_NUMBER_LATENCY                                           0xa000006
++#define ixD3F4_IO_BASE_LIMIT                                                    0xa000007
++#define ixD3F4_SECONDARY_STATUS                                                 0xa000007
++#define ixD3F4_MEM_BASE_LIMIT                                                   0xa000008
++#define ixD3F4_PREF_BASE_LIMIT                                                  0xa000009
++#define ixD3F4_PREF_BASE_UPPER                                                  0xa00000a
++#define ixD3F4_PREF_LIMIT_UPPER                                                 0xa00000b
++#define ixD3F4_IO_BASE_LIMIT_HI                                                 0xa00000c
++#define ixD3F4_IRQ_BRIDGE_CNTL                                                  0xa00000f
++#define ixD3F4_CAP_PTR                                                          0xa00000d
++#define ixD3F4_INTERRUPT_LINE                                                   0xa00000f
++#define ixD3F4_INTERRUPT_PIN                                                    0xa00000f
++#define ixD3F4_EXT_BRIDGE_CNTL                                                  0xa000010
++#define ixD3F4_PMI_CAP_LIST                                                     0xa000014
++#define ixD3F4_PMI_CAP                                                          0xa000014
++#define ixD3F4_PMI_STATUS_CNTL                                                  0xa000015
++#define ixD3F4_PCIE_CAP_LIST                                                    0xa000016
++#define ixD3F4_PCIE_CAP                                                         0xa000016
++#define ixD3F4_DEVICE_CAP                                                       0xa000017
++#define ixD3F4_DEVICE_CNTL                                                      0xa000018
++#define ixD3F4_DEVICE_STATUS                                                    0xa000018
++#define ixD3F4_LINK_CAP                                                         0xa000019
++#define ixD3F4_LINK_CNTL                                                        0xa00001a
++#define ixD3F4_LINK_STATUS                                                      0xa00001a
++#define ixD3F4_SLOT_CAP                                                         0xa00001b
++#define ixD3F4_SLOT_CNTL                                                        0xa00001c
++#define ixD3F4_SLOT_STATUS                                                      0xa00001c
++#define ixD3F4_ROOT_CNTL                                                        0xa00001d
++#define ixD3F4_ROOT_CAP                                                         0xa00001d
++#define ixD3F4_ROOT_STATUS                                                      0xa00001e
++#define ixD3F4_DEVICE_CAP2                                                      0xa00001f
++#define ixD3F4_DEVICE_CNTL2                                                     0xa000020
++#define ixD3F4_DEVICE_STATUS2                                                   0xa000020
++#define ixD3F4_LINK_CAP2                                                        0xa000021
++#define ixD3F4_LINK_CNTL2                                                       0xa000022
++#define ixD3F4_LINK_STATUS2                                                     0xa000022
++#define ixD3F4_SLOT_CAP2                                                        0xa000023
++#define ixD3F4_SLOT_CNTL2                                                       0xa000024
++#define ixD3F4_SLOT_STATUS2                                                     0xa000024
++#define ixD3F4_MSI_CAP_LIST                                                     0xa000028
++#define ixD3F4_MSI_MSG_CNTL                                                     0xa000028
++#define ixD3F4_MSI_MSG_ADDR_LO                                                  0xa000029
++#define ixD3F4_MSI_MSG_ADDR_HI                                                  0xa00002a
++#define ixD3F4_MSI_MSG_DATA_64                                                  0xa00002b
++#define ixD3F4_MSI_MSG_DATA                                                     0xa00002a
++#define ixD3F4_SSID_CAP_LIST                                                    0xa000030
++#define ixD3F4_SSID_CAP                                                         0xa000031
++#define ixD3F4_MSI_MAP_CAP_LIST                                                 0xa000032
++#define ixD3F4_MSI_MAP_CAP                                                      0xa000032
++#define ixD3F4_MSI_MAP_ADDR_LO                                                  0xa000033
++#define ixD3F4_MSI_MAP_ADDR_HI                                                  0xa000034
++#define ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0xa000040
++#define ixD3F4_PCIE_VENDOR_SPECIFIC_HDR                                         0xa000041
++#define ixD3F4_PCIE_VENDOR_SPECIFIC1                                            0xa000042
++#define ixD3F4_PCIE_VENDOR_SPECIFIC2                                            0xa000043
++#define ixD3F4_PCIE_VC_ENH_CAP_LIST                                             0xa000044
++#define ixD3F4_PCIE_PORT_VC_CAP_REG1                                            0xa000045
++#define ixD3F4_PCIE_PORT_VC_CAP_REG2                                            0xa000046
++#define ixD3F4_PCIE_PORT_VC_CNTL                                                0xa000047
++#define ixD3F4_PCIE_PORT_VC_STATUS                                              0xa000047
++#define ixD3F4_PCIE_VC0_RESOURCE_CAP                                            0xa000048
++#define ixD3F4_PCIE_VC0_RESOURCE_CNTL                                           0xa000049
++#define ixD3F4_PCIE_VC0_RESOURCE_STATUS                                         0xa00004a
++#define ixD3F4_PCIE_VC1_RESOURCE_CAP                                            0xa00004b
++#define ixD3F4_PCIE_VC1_RESOURCE_CNTL                                           0xa00004c
++#define ixD3F4_PCIE_VC1_RESOURCE_STATUS                                         0xa00004d
++#define ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0xa000050
++#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW1                                          0xa000051
++#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW2                                          0xa000052
++#define ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0xa000054
++#define ixD3F4_PCIE_UNCORR_ERR_STATUS                                           0xa000055
++#define ixD3F4_PCIE_UNCORR_ERR_MASK                                             0xa000056
++#define ixD3F4_PCIE_UNCORR_ERR_SEVERITY                                         0xa000057
++#define ixD3F4_PCIE_CORR_ERR_STATUS                                             0xa000058
++#define ixD3F4_PCIE_CORR_ERR_MASK                                               0xa000059
++#define ixD3F4_PCIE_ADV_ERR_CAP_CNTL                                            0xa00005a
++#define ixD3F4_PCIE_HDR_LOG0                                                    0xa00005b
++#define ixD3F4_PCIE_HDR_LOG1                                                    0xa00005c
++#define ixD3F4_PCIE_HDR_LOG2                                                    0xa00005d
++#define ixD3F4_PCIE_HDR_LOG3                                                    0xa00005e
++#define ixD3F4_PCIE_ROOT_ERR_CMD                                                0xa00005f
++#define ixD3F4_PCIE_ROOT_ERR_STATUS                                             0xa000060
++#define ixD3F4_PCIE_ERR_SRC_ID                                                  0xa000061
++#define ixD3F4_PCIE_TLP_PREFIX_LOG0                                             0xa000062
++#define ixD3F4_PCIE_TLP_PREFIX_LOG1                                             0xa000063
++#define ixD3F4_PCIE_TLP_PREFIX_LOG2                                             0xa000064
++#define ixD3F4_PCIE_TLP_PREFIX_LOG3                                             0xa000065
++#define ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST                                      0xa00009c
++#define ixD3F4_PCIE_LINK_CNTL3                                                  0xa00009d
++#define ixD3F4_PCIE_LANE_ERROR_STATUS                                           0xa00009e
++#define ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL                                    0xa00009f
++#define ixD3F4_PCIE_LANE_1_EQUALIZATION_CNTL                                    0xa00009f
++#define ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL                                    0xa0000a0
++#define ixD3F4_PCIE_LANE_3_EQUALIZATION_CNTL                                    0xa0000a0
++#define ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL                                    0xa0000a1
++#define ixD3F4_PCIE_LANE_5_EQUALIZATION_CNTL                                    0xa0000a1
++#define ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL                                    0xa0000a2
++#define ixD3F4_PCIE_LANE_7_EQUALIZATION_CNTL                                    0xa0000a2
++#define ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL                                    0xa0000a3
++#define ixD3F4_PCIE_LANE_9_EQUALIZATION_CNTL                                    0xa0000a3
++#define ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL                                   0xa0000a4
++#define ixD3F4_PCIE_LANE_11_EQUALIZATION_CNTL                                   0xa0000a4
++#define ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL                                   0xa0000a5
++#define ixD3F4_PCIE_LANE_13_EQUALIZATION_CNTL                                   0xa0000a5
++#define ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL                                   0xa0000a6
++#define ixD3F4_PCIE_LANE_15_EQUALIZATION_CNTL                                   0xa0000a6
++#define ixD3F4_PCIE_ACS_ENH_CAP_LIST                                            0xa0000a8
++#define ixD3F4_PCIE_ACS_CAP                                                     0xa0000a9
++#define ixD3F4_PCIE_ACS_CNTL                                                    0xa0000a9
++#define ixD3F4_PCIE_MC_ENH_CAP_LIST                                             0xa0000bc
++#define ixD3F4_PCIE_MC_CAP                                                      0xa0000bd
++#define ixD3F4_PCIE_MC_CNTL                                                     0xa0000bd
++#define ixD3F4_PCIE_MC_ADDR0                                                    0xa0000be
++#define ixD3F4_PCIE_MC_ADDR1                                                    0xa0000bf
++#define ixD3F4_PCIE_MC_RCV0                                                     0xa0000c0
++#define ixD3F4_PCIE_MC_RCV1                                                     0xa0000c1
++#define ixD3F4_PCIE_MC_BLOCK_ALL0                                               0xa0000c2
++#define ixD3F4_PCIE_MC_BLOCK_ALL1                                               0xa0000c3
++#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0xa0000c4
++#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0xa0000c5
++#define ixD3F4_PCIE_MC_OVERLAY_BAR0                                             0xa0000c6
++#define ixD3F4_PCIE_MC_OVERLAY_BAR1                                             0xa0000c7
++#define ixD3F5_PCIE_PORT_INDEX                                                  0xb000038
++#define ixD3F5_PCIE_PORT_DATA                                                   0xb000039
++#define ixD3F5_PCIEP_RESERVED                                                   0x0
++#define ixD3F5_PCIEP_SCRATCH                                                    0x1
++#define ixD3F5_PCIEP_HW_DEBUG                                                   0x2
++#define ixD3F5_PCIEP_PORT_CNTL                                                  0x10
++#define ixD3F5_PCIE_TX_CNTL                                                     0x20
++#define ixD3F5_PCIE_TX_REQUESTER_ID                                             0x21
++#define ixD3F5_PCIE_TX_VENDOR_SPECIFIC                                          0x22
++#define ixD3F5_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
++#define ixD3F5_PCIE_TX_SEQ                                                      0x24
++#define ixD3F5_PCIE_TX_REPLAY                                                   0x25
++#define ixD3F5_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
++#define ixD3F5_PCIE_TX_CREDITS_ADVT_P                                           0x30
++#define ixD3F5_PCIE_TX_CREDITS_ADVT_NP                                          0x31
++#define ixD3F5_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
++#define ixD3F5_PCIE_TX_CREDITS_INIT_P                                           0x33
++#define ixD3F5_PCIE_TX_CREDITS_INIT_NP                                          0x34
++#define ixD3F5_PCIE_TX_CREDITS_INIT_CPL                                         0x35
++#define ixD3F5_PCIE_TX_CREDITS_STATUS                                           0x36
++#define ixD3F5_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
++#define ixD3F5_PCIE_P_PORT_LANE_STATUS                                          0x50
++#define ixD3F5_PCIE_FC_P                                                        0x60
++#define ixD3F5_PCIE_FC_NP                                                       0x61
++#define ixD3F5_PCIE_FC_CPL                                                      0x62
++#define ixD3F5_PCIE_ERR_CNTL                                                    0x6a
++#define ixD3F5_PCIE_RX_CNTL                                                     0x70
++#define ixD3F5_PCIE_RX_EXPECTED_SEQNUM                                          0x71
++#define ixD3F5_PCIE_RX_VENDOR_SPECIFIC                                          0x72
++#define ixD3F5_PCIE_RX_CNTL3                                                    0x74
++#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
++#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
++#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
++#define ixD3F5_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
++#define ixD3F5_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
++#define ixD3F5_PCIE_LC_CNTL                                                     0xa0
++#define ixD3F5_PCIE_LC_CNTL2                                                    0xb1
++#define ixD3F5_PCIE_LC_CNTL3                                                    0xb5
++#define ixD3F5_PCIE_LC_CNTL4                                                    0xb6
++#define ixD3F5_PCIE_LC_CNTL5                                                    0xb7
++#define ixD3F5_PCIE_LC_CNTL6                                                    0xbb
++#define ixD3F5_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
++#define ixD3F5_PCIE_LC_TRAINING_CNTL                                            0xa1
++#define ixD3F5_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
++#define ixD3F5_PCIE_LC_N_FTS_CNTL                                               0xa3
++#define ixD3F5_PCIE_LC_SPEED_CNTL                                               0xa4
++#define ixD3F5_PCIE_LC_CDR_CNTL                                                 0xb3
++#define ixD3F5_PCIE_LC_LANE_CNTL                                                0xb4
++#define ixD3F5_PCIE_LC_FORCE_COEFF                                              0xb8
++#define ixD3F5_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
++#define ixD3F5_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
++#define ixD3F5_PCIE_LC_STATE0                                                   0xa5
++#define ixD3F5_PCIE_LC_STATE1                                                   0xa6
++#define ixD3F5_PCIE_LC_STATE2                                                   0xa7
++#define ixD3F5_PCIE_LC_STATE3                                                   0xa8
++#define ixD3F5_PCIE_LC_STATE4                                                   0xa9
++#define ixD3F5_PCIE_LC_STATE5                                                   0xaa
++#define ixD3F5_PCIEP_STRAP_LC                                                   0xc0
++#define ixD3F5_PCIEP_STRAP_MISC                                                 0xc1
++#define ixD3F5_PCIEP_BCH_ECC_CNTL                                               0xd0
++#define ixD3F5_PCIEP_HPGI_PRIVATE                                               0xd2
++#define ixD3F5_PCIEP_HPGI                                                       0xda
++#define ixD3F5_VENDOR_ID                                                        0xb000000
++#define ixD3F5_DEVICE_ID                                                        0xb000000
++#define ixD3F5_COMMAND                                                          0xb000001
++#define ixD3F5_STATUS                                                           0xb000001
++#define ixD3F5_REVISION_ID                                                      0xb000002
++#define ixD3F5_PROG_INTERFACE                                                   0xb000002
++#define ixD3F5_SUB_CLASS                                                        0xb000002
++#define ixD3F5_BASE_CLASS                                                       0xb000002
++#define ixD3F5_CACHE_LINE                                                       0xb000003
++#define ixD3F5_LATENCY                                                          0xb000003
++#define ixD3F5_HEADER                                                           0xb000003
++#define ixD3F5_BIST                                                             0xb000003
++#define ixD3F5_SUB_BUS_NUMBER_LATENCY                                           0xb000006
++#define ixD3F5_IO_BASE_LIMIT                                                    0xb000007
++#define ixD3F5_SECONDARY_STATUS                                                 0xb000007
++#define ixD3F5_MEM_BASE_LIMIT                                                   0xb000008
++#define ixD3F5_PREF_BASE_LIMIT                                                  0xb000009
++#define ixD3F5_PREF_BASE_UPPER                                                  0xb00000a
++#define ixD3F5_PREF_LIMIT_UPPER                                                 0xb00000b
++#define ixD3F5_IO_BASE_LIMIT_HI                                                 0xb00000c
++#define ixD3F5_IRQ_BRIDGE_CNTL                                                  0xb00000f
++#define ixD3F5_CAP_PTR                                                          0xb00000d
++#define ixD3F5_INTERRUPT_LINE                                                   0xb00000f
++#define ixD3F5_INTERRUPT_PIN                                                    0xb00000f
++#define ixD3F5_EXT_BRIDGE_CNTL                                                  0xb000010
++#define ixD3F5_PMI_CAP_LIST                                                     0xb000014
++#define ixD3F5_PMI_CAP                                                          0xb000014
++#define ixD3F5_PMI_STATUS_CNTL                                                  0xb000015
++#define ixD3F5_PCIE_CAP_LIST                                                    0xb000016
++#define ixD3F5_PCIE_CAP                                                         0xb000016
++#define ixD3F5_DEVICE_CAP                                                       0xb000017
++#define ixD3F5_DEVICE_CNTL                                                      0xb000018
++#define ixD3F5_DEVICE_STATUS                                                    0xb000018
++#define ixD3F5_LINK_CAP                                                         0xb000019
++#define ixD3F5_LINK_CNTL                                                        0xb00001a
++#define ixD3F5_LINK_STATUS                                                      0xb00001a
++#define ixD3F5_SLOT_CAP                                                         0xb00001b
++#define ixD3F5_SLOT_CNTL                                                        0xb00001c
++#define ixD3F5_SLOT_STATUS                                                      0xb00001c
++#define ixD3F5_ROOT_CNTL                                                        0xb00001d
++#define ixD3F5_ROOT_CAP                                                         0xb00001d
++#define ixD3F5_ROOT_STATUS                                                      0xb00001e
++#define ixD3F5_DEVICE_CAP2                                                      0xb00001f
++#define ixD3F5_DEVICE_CNTL2                                                     0xb000020
++#define ixD3F5_DEVICE_STATUS2                                                   0xb000020
++#define ixD3F5_LINK_CAP2                                                        0xb000021
++#define ixD3F5_LINK_CNTL2                                                       0xb000022
++#define ixD3F5_LINK_STATUS2                                                     0xb000022
++#define ixD3F5_SLOT_CAP2                                                        0xb000023
++#define ixD3F5_SLOT_CNTL2                                                       0xb000024
++#define ixD3F5_SLOT_STATUS2                                                     0xb000024
++#define ixD3F5_MSI_CAP_LIST                                                     0xb000028
++#define ixD3F5_MSI_MSG_CNTL                                                     0xb000028
++#define ixD3F5_MSI_MSG_ADDR_LO                                                  0xb000029
++#define ixD3F5_MSI_MSG_ADDR_HI                                                  0xb00002a
++#define ixD3F5_MSI_MSG_DATA_64                                                  0xb00002b
++#define ixD3F5_MSI_MSG_DATA                                                     0xb00002a
++#define ixD3F5_SSID_CAP_LIST                                                    0xb000030
++#define ixD3F5_SSID_CAP                                                         0xb000031
++#define ixD3F5_MSI_MAP_CAP_LIST                                                 0xb000032
++#define ixD3F5_MSI_MAP_CAP                                                      0xb000032
++#define ixD3F5_MSI_MAP_ADDR_LO                                                  0xb000033
++#define ixD3F5_MSI_MAP_ADDR_HI                                                  0xb000034
++#define ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                0xb000040
++#define ixD3F5_PCIE_VENDOR_SPECIFIC_HDR                                         0xb000041
++#define ixD3F5_PCIE_VENDOR_SPECIFIC1                                            0xb000042
++#define ixD3F5_PCIE_VENDOR_SPECIFIC2                                            0xb000043
++#define ixD3F5_PCIE_VC_ENH_CAP_LIST                                             0xb000044
++#define ixD3F5_PCIE_PORT_VC_CAP_REG1                                            0xb000045
++#define ixD3F5_PCIE_PORT_VC_CAP_REG2                                            0xb000046
++#define ixD3F5_PCIE_PORT_VC_CNTL                                                0xb000047
++#define ixD3F5_PCIE_PORT_VC_STATUS                                              0xb000047
++#define ixD3F5_PCIE_VC0_RESOURCE_CAP                                            0xb000048
++#define ixD3F5_PCIE_VC0_RESOURCE_CNTL                                           0xb000049
++#define ixD3F5_PCIE_VC0_RESOURCE_STATUS                                         0xb00004a
++#define ixD3F5_PCIE_VC1_RESOURCE_CAP                                            0xb00004b
++#define ixD3F5_PCIE_VC1_RESOURCE_CNTL                                           0xb00004c
++#define ixD3F5_PCIE_VC1_RESOURCE_STATUS                                         0xb00004d
++#define ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                 0xb000050
++#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW1                                          0xb000051
++#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW2                                          0xb000052
++#define ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                    0xb000054
++#define ixD3F5_PCIE_UNCORR_ERR_STATUS                                           0xb000055
++#define ixD3F5_PCIE_UNCORR_ERR_MASK                                             0xb000056
++#define ixD3F5_PCIE_UNCORR_ERR_SEVERITY                                         0xb000057
++#define ixD3F5_PCIE_CORR_ERR_STATUS                                             0xb000058
++#define ixD3F5_PCIE_CORR_ERR_MASK                                               0xb000059
++#define ixD3F5_PCIE_ADV_ERR_CAP_CNTL                                            0xb00005a
++#define ixD3F5_PCIE_HDR_LOG0                                                    0xb00005b
++#define ixD3F5_PCIE_HDR_LOG1                                                    0xb00005c
++#define ixD3F5_PCIE_HDR_LOG2                                                    0xb00005d
++#define ixD3F5_PCIE_HDR_LOG3                                                    0xb00005e
++#define ixD3F5_PCIE_ROOT_ERR_CMD                                                0xb00005f
++#define ixD3F5_PCIE_ROOT_ERR_STATUS                                             0xb000060
++#define ixD3F5_PCIE_ERR_SRC_ID                                                  0xb000061
++#define ixD3F5_PCIE_TLP_PREFIX_LOG0                                             0xb000062
++#define ixD3F5_PCIE_TLP_PREFIX_LOG1                                             0xb000063
++#define ixD3F5_PCIE_TLP_PREFIX_LOG2                                             0xb000064
++#define ixD3F5_PCIE_TLP_PREFIX_LOG3                                             0xb000065
++#define ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST                                      0xb00009c
++#define ixD3F5_PCIE_LINK_CNTL3                                                  0xb00009d
++#define ixD3F5_PCIE_LANE_ERROR_STATUS                                           0xb00009e
++#define ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL                                    0xb00009f
++#define ixD3F5_PCIE_LANE_1_EQUALIZATION_CNTL                                    0xb00009f
++#define ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL                                    0xb0000a0
++#define ixD3F5_PCIE_LANE_3_EQUALIZATION_CNTL                                    0xb0000a0
++#define ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL                                    0xb0000a1
++#define ixD3F5_PCIE_LANE_5_EQUALIZATION_CNTL                                    0xb0000a1
++#define ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL                                    0xb0000a2
++#define ixD3F5_PCIE_LANE_7_EQUALIZATION_CNTL                                    0xb0000a2
++#define ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL                                    0xb0000a3
++#define ixD3F5_PCIE_LANE_9_EQUALIZATION_CNTL                                    0xb0000a3
++#define ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL                                   0xb0000a4
++#define ixD3F5_PCIE_LANE_11_EQUALIZATION_CNTL                                   0xb0000a4
++#define ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL                                   0xb0000a5
++#define ixD3F5_PCIE_LANE_13_EQUALIZATION_CNTL                                   0xb0000a5
++#define ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL                                   0xb0000a6
++#define ixD3F5_PCIE_LANE_15_EQUALIZATION_CNTL                                   0xb0000a6
++#define ixD3F5_PCIE_ACS_ENH_CAP_LIST                                            0xb0000a8
++#define ixD3F5_PCIE_ACS_CAP                                                     0xb0000a9
++#define ixD3F5_PCIE_ACS_CNTL                                                    0xb0000a9
++#define ixD3F5_PCIE_MC_ENH_CAP_LIST                                             0xb0000bc
++#define ixD3F5_PCIE_MC_CAP                                                      0xb0000bd
++#define ixD3F5_PCIE_MC_CNTL                                                     0xb0000bd
++#define ixD3F5_PCIE_MC_ADDR0                                                    0xb0000be
++#define ixD3F5_PCIE_MC_ADDR1                                                    0xb0000bf
++#define ixD3F5_PCIE_MC_RCV0                                                     0xb0000c0
++#define ixD3F5_PCIE_MC_RCV1                                                     0xb0000c1
++#define ixD3F5_PCIE_MC_BLOCK_ALL0                                               0xb0000c2
++#define ixD3F5_PCIE_MC_BLOCK_ALL1                                               0xb0000c3
++#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0                                     0xb0000c4
++#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1                                     0xb0000c5
++#define ixD3F5_PCIE_MC_OVERLAY_BAR0                                             0xb0000c6
++#define ixD3F5_PCIE_MC_OVERLAY_BAR1                                             0xb0000c7
++#define mmC_PCIE_INDEX                                                          0x28
++#define mmPCIE_WRAPPER0_C_PCIE_INDEX                                            0x28
++#define mmPCIE_WRAPPER1_C_PCIE_INDEX                                            0x38
++#define mmC_PCIE_DATA                                                           0x29
++#define mmPCIE_WRAPPER0_C_PCIE_DATA                                             0x29
++#define mmPCIE_WRAPPER1_C_PCIE_DATA                                             0x39
++#define mmRFE_SNOOP_RST                                                         0x3c
++#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1                                      0x1500000
++#define ixPSX80_WRP_BIF_STRAP_PI_CNTL                                           0x1500001
++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE                                   0x1500002
++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE                                      0x1500003
++#define ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE                                      0x1500004
++#define ixPSX80_WRP_BIF_STRAP_TEST_DFT                                          0x1500005
++#define ixPSX80_WRP_BIF_STRAP_ID                                                0x1500006
++#define ixPSX80_WRP_BIF_STRAP_REV_ID                                            0x1500007
++#define ixPSX80_WRP_BIF_STRAP_I2C_CNTL                                          0x1500008
++#define ixPSX80_WRP_BIF_INT_CNTL                                                0x1500009
++#define ixPSX80_WRP_BIF_STRAP_ACS                                               0x150000a
++#define ixPSX80_WRP_BIF_STRAP_PM                                                0x150000b
++#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2                                      0x150000c
++#define ixPSX80_WRP_BIF_SERIAL_NUM                                              0x1500045
++#define ixPSX80_WRP_BIF_SSID                                                    0x1500046
++#define ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL                                  0x1500050
++#define ixPSX80_WRP_PCIE_LINK_CONFIG                                            0x1500080
++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_A                                        0x1500800
++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A                                 0x1500801
++#define ixPSX80_WRP_BIF_STRAP_ASPM_A                                            0x1500802
++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A                                    0x1500803
++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_A                                       0x1500804
++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A                                   0x1500805
++#define ixPSX80_WRP_PCIE_PORT_IS_SB_A                                           0x1500813
++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_B                                        0x1500900
++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B                                 0x1500901
++#define ixPSX80_WRP_BIF_STRAP_ASPM_B                                            0x1500902
++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B                                    0x1500903
++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_B                                       0x1500904
++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B                                   0x1500905
++#define ixPSX80_WRP_PCIE_PORT_IS_SB_B                                           0x1500913
++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_C                                        0x1500a00
++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C                                 0x1500a01
++#define ixPSX80_WRP_BIF_STRAP_ASPM_C                                            0x1500a02
++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C                                    0x1500a03
++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_C                                       0x1500a04
++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C                                   0x1500a05
++#define ixPSX80_WRP_PCIE_PORT_IS_SB_C                                           0x1500a13
++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_D                                        0x1500b00
++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D                                 0x1500b01
++#define ixPSX80_WRP_BIF_STRAP_ASPM_D                                            0x1500b02
++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D                                    0x1500b03
++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_D                                       0x1500b04
++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D                                   0x1500b05
++#define ixPSX80_WRP_PCIE_PORT_IS_SB_D                                           0x1500b13
++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_E                                        0x1500c00
++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E                                 0x1500c01
++#define ixPSX80_WRP_BIF_STRAP_ASPM_E                                            0x1500c02
++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E                                    0x1500c03
++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_E                                       0x1500c04
++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E                                   0x1500c05
++#define ixPSX80_WRP_PCIE_PORT_IS_SB_E                                           0x1500c13
++#define ixPSX80_WRP_LNCNT_CONTROL                                               0x1508030
++#define ixPSX80_WRP_CFG_LNC_WINDOW                                              0x1508031
++#define ixPSX80_WRP_LNCNT_QUAN_THRD                                             0x1508032
++#define ixPSX80_WRP_LNCNT_WEIGHT                                                0x1508033
++#define ixPSX80_WRP_LNC_TOTAL_WACC                                              0x1508034
++#define ixPSX80_WRP_LNC_BW_WACC                                                 0x1508035
++#define ixPSX80_WRP_LNC_CMN_WACC                                                0x1508036
++#define ixPSX80_WRP_PCIE_EFUSE                                                  0x150fff0
++#define ixPSX80_WRP_PCIE_EFUSE2                                                 0x150fff1
++#define ixPSX80_WRP_PCIE_EFUSE3                                                 0x150fff2
++#define ixPSX80_WRP_PCIE_EFUSE4                                                 0x150fff3
++#define ixPSX80_WRP_PCIE_EFUSE5                                                 0x150fff4
++#define ixPSX80_WRP_PCIE_EFUSE6                                                 0x150fff5
++#define ixPSX80_WRP_PCIE_EFUSE7                                                 0x150fff6
++#define ixPSX80_WRP_PCIE_WRAP_SCRATCH1                                          0x1308001
++#define ixPSX80_WRP_PCIE_WRAP_SCRATCH2                                          0x1308002
++#define ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC                                     0x1308005
++#define ixPSX80_WRP_PCIE_WRAP_DTM_MISC                                          0x1308006
++#define ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN                             0x1308007
++#define ixPSX80_WRP_PCIE_WRAP_MISC                                              0x1308008
++#define ixPSX80_WRP_PCIE_WRAP_PIF_MISC                                          0x1308009
++#define ixPSX80_WRP_PCIE_RXDET_OVERRIDE                                         0x130800a
++#define ixPSX80_WRP_IMPCTL_CNTL_PIF0                                            0x1308070
++#define ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL                                 0x1308090
++#define ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL                                    0x1308096
++#define ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL                                    0x1308097
++#define ixPSX80_WRP_REG_ADAPT_pif0_CONTROL                                      0x1308098
++#define ixPSX80_WRP_BIOSTIMER_CMD                                               0x13080f0
++#define ixPSX80_WRP_BIOSTIMER_CNTL                                              0x13080f1
++#define ixPSX80_WRP_BIOSTIMER_DEBUG                                             0x13080f2
++#define ixPSX80_WRP_DTM_RX_BP_CNTL                                              0x130ffe0
++#define ixPSX80_WRP_DTM_CNTL                                                    0x130ffe1
++#define ixPSX80_WRP_DTM_CNTL_LEGACY                                             0x130ffe2
++#define ixPSX80_WRP_DTM_STI_LCLK_CTRL                                           0x130ffe3
++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x                           0x130ffe4
++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt                          0x130ffe5
++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x                           0x130ffe6
++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt                          0x130ffe7
++#define ixPSX80_WRP_DELAYLINE_COMMAND                                           0x130ffd0
++#define ixPSX80_WRP_DELAYLINE_STATUS                                            0x130ffd1
++#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1                                      0x1510000
++#define ixPSX81_WRP_BIF_STRAP_PI_CNTL                                           0x1510001
++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE                                   0x1510002
++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE                                      0x1510003
++#define ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE                                      0x1510004
++#define ixPSX81_WRP_BIF_STRAP_TEST_DFT                                          0x1510005
++#define ixPSX81_WRP_BIF_STRAP_ID                                                0x1510006
++#define ixPSX81_WRP_BIF_STRAP_REV_ID                                            0x1510007
++#define ixPSX81_WRP_BIF_STRAP_I2C_CNTL                                          0x1510008
++#define ixPSX81_WRP_BIF_INT_CNTL                                                0x1510009
++#define ixPSX81_WRP_BIF_STRAP_ACS                                               0x151000a
++#define ixPSX81_WRP_BIF_STRAP_PM                                                0x151000b
++#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2                                      0x151000c
++#define ixPSX81_WRP_BIF_SERIAL_NUM                                              0x1510045
++#define ixPSX81_WRP_BIF_SSID                                                    0x1510046
++#define ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL                                  0x1510050
++#define ixPSX81_WRP_PCIE_LINK_CONFIG                                            0x1510080
++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_A                                        0x1510800
++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A                                 0x1510801
++#define ixPSX81_WRP_BIF_STRAP_ASPM_A                                            0x1510802
++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A                                    0x1510803
++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_A                                       0x1510804
++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A                                   0x1510805
++#define ixPSX81_WRP_PCIE_PORT_IS_SB_A                                           0x1510813
++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_B                                        0x1510900
++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B                                 0x1510901
++#define ixPSX81_WRP_BIF_STRAP_ASPM_B                                            0x1510902
++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B                                    0x1510903
++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_B                                       0x1510904
++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B                                   0x1510905
++#define ixPSX81_WRP_PCIE_PORT_IS_SB_B                                           0x1510913
++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_C                                        0x1510a00
++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C                                 0x1510a01
++#define ixPSX81_WRP_BIF_STRAP_ASPM_C                                            0x1510a02
++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C                                    0x1510a03
++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_C                                       0x1510a04
++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C                                   0x1510a05
++#define ixPSX81_WRP_PCIE_PORT_IS_SB_C                                           0x1510a13
++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_D                                        0x1510b00
++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D                                 0x1510b01
++#define ixPSX81_WRP_BIF_STRAP_ASPM_D                                            0x1510b02
++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D                                    0x1510b03
++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_D                                       0x1510b04
++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D                                   0x1510b05
++#define ixPSX81_WRP_PCIE_PORT_IS_SB_D                                           0x1510b13
++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_E                                        0x1510c00
++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E                                 0x1510c01
++#define ixPSX81_WRP_BIF_STRAP_ASPM_E                                            0x1510c02
++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E                                    0x1510c03
++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_E                                       0x1510c04
++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E                                   0x1510c05
++#define ixPSX81_WRP_PCIE_PORT_IS_SB_E                                           0x1510c13
++#define ixPSX81_WRP_LNCNT_CONTROL                                               0x1518030
++#define ixPSX81_WRP_CFG_LNC_WINDOW                                              0x1518031
++#define ixPSX81_WRP_LNCNT_QUAN_THRD                                             0x1518032
++#define ixPSX81_WRP_LNCNT_WEIGHT                                                0x1518033
++#define ixPSX81_WRP_LNC_TOTAL_WACC                                              0x1518034
++#define ixPSX81_WRP_LNC_BW_WACC                                                 0x1518035
++#define ixPSX81_WRP_LNC_CMN_WACC                                                0x1518036
++#define ixPSX81_WRP_PCIE_EFUSE                                                  0x151fff0
++#define ixPSX81_WRP_PCIE_EFUSE2                                                 0x151fff1
++#define ixPSX81_WRP_PCIE_EFUSE3                                                 0x151fff2
++#define ixPSX81_WRP_PCIE_EFUSE4                                                 0x151fff3
++#define ixPSX81_WRP_PCIE_EFUSE5                                                 0x151fff4
++#define ixPSX81_WRP_PCIE_EFUSE6                                                 0x151fff5
++#define ixPSX81_WRP_PCIE_EFUSE7                                                 0x151fff6
++#define ixPSX81_WRP_PCIE_WRAP_SCRATCH1                                          0x1318001
++#define ixPSX81_WRP_PCIE_WRAP_SCRATCH2                                          0x1318002
++#define ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC                                     0x1318005
++#define ixPSX81_WRP_PCIE_WRAP_DTM_MISC                                          0x1318006
++#define ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN                             0x1318007
++#define ixPSX81_WRP_PCIE_WRAP_MISC                                              0x1318008
++#define ixPSX81_WRP_PCIE_WRAP_PIF_MISC                                          0x1318009
++#define ixPSX81_WRP_PCIE_RXDET_OVERRIDE                                         0x131800a
++#define ixPSX81_WRP_IMPCTL_CNTL_PIF0                                            0x1318070
++#define ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL                                 0x1318090
++#define ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL                                    0x1318096
++#define ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL                                    0x1318097
++#define ixPSX81_WRP_REG_ADAPT_pif0_CONTROL                                      0x1318098
++#define ixPSX81_WRP_BIOSTIMER_CMD                                               0x13180f0
++#define ixPSX81_WRP_BIOSTIMER_CNTL                                              0x13180f1
++#define ixPSX81_WRP_BIOSTIMER_DEBUG                                             0x13180f2
++#define ixPSX81_WRP_DTM_RX_BP_CNTL                                              0x131ffe0
++#define ixPSX81_WRP_DTM_CNTL                                                    0x131ffe1
++#define ixPSX81_WRP_DTM_CNTL_LEGACY                                             0x131ffe2
++#define ixPSX81_WRP_DTM_STI_LCLK_CTRL                                           0x131ffe3
++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x                           0x131ffe4
++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt                          0x131ffe5
++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x                           0x131ffe6
++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt                          0x131ffe7
++#define ixPSX81_WRP_DELAYLINE_COMMAND                                           0x131ffd0
++#define ixPSX81_WRP_DELAYLINE_STATUS                                            0x131ffd1
++#define ixRFE_WARMRST_CNTL                                                      0x1085164
++#define ixRFE_SOFTRST_CNTL                                                      0x1080001
++#define ixRFE_IMPRST_CNTL                                                       0x1085160
++#define ixRFE_CLIENT_SOFTRST_TRIGGER                                            0x1080004
++#define ixRFE_MASTER_SOFTRST_TRIGGER                                            0x1080005
++#define ixRFE_PWDN_COMMAND                                                      0x1080010
++#define ixRFE_PWDN_STATUS                                                       0x1080011
++#define ixRFE_MST_PCIEW0_CMDSTATUS                                              0x1080020
++#define ixRFE_MST_PCIEW1_CMDSTATUS                                              0x1080021
++#define ixRFE_MST_RWREG_RFEWRC_CMDSTATUS                                        0x1080022
++#define ixRFE_MST_TMOUT_STATUS                                                  0x108003f
++#define ixRFE_IMPARBH_STATUS                                                    0x1085140
++#define ixRFE_IMPARBH_CONTROL                                                   0x1080083
++#define ixPSX80_BIF_PCIE_RESERVED                                               0x1400000
++#define ixPSX80_BIF_PCIE_SCRATCH                                                0x1400001
++#define ixPSX80_BIF_PCIE_HW_DEBUG                                               0x1400002
++#define ixPSX80_BIF_PCIE_RX_NUM_NAK                                             0x140000e
++#define ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED                                   0x140000f
++#define ixPSX80_BIF_PCIE_CNTL                                                   0x1400010
++#define ixPSX80_BIF_PCIE_CONFIG_CNTL                                            0x1400011
++#define ixPSX80_BIF_PCIE_DEBUG_CNTL                                             0x1400012
++#define ixPSX80_BIF_PCIE_CNTL2                                                  0x140001c
++#define ixPSX80_BIF_PCIE_RX_CNTL2                                               0x140001d
++#define ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL                                        0x140001e
++#define ixPSX80_BIF_PCIE_CI_CNTL                                                0x1400020
++#define ixPSX80_BIF_PCIE_BUS_CNTL                                               0x1400021
++#define ixPSX80_BIF_PCIE_LC_STATE6                                              0x1400022
++#define ixPSX80_BIF_PCIE_LC_STATE7                                              0x1400023
++#define ixPSX80_BIF_PCIE_LC_STATE8                                              0x1400024
++#define ixPSX80_BIF_PCIE_LC_STATE9                                              0x1400025
++#define ixPSX80_BIF_PCIE_LC_STATE10                                             0x1400026
++#define ixPSX80_BIF_PCIE_LC_STATE11                                             0x1400027
++#define ixPSX80_BIF_PCIE_LC_STATUS1                                             0x1400028
++#define ixPSX80_BIF_PCIE_LC_STATUS2                                             0x1400029
++#define ixPSX80_BIF_PCIE_WPR_CNTL                                               0x1400030
++#define ixPSX80_BIF_PCIE_RX_LAST_TLP0                                           0x1400031
++#define ixPSX80_BIF_PCIE_RX_LAST_TLP1                                           0x1400032
++#define ixPSX80_BIF_PCIE_RX_LAST_TLP2                                           0x1400033
++#define ixPSX80_BIF_PCIE_RX_LAST_TLP3                                           0x1400034
++#define ixPSX80_BIF_PCIE_TX_LAST_TLP0                                           0x1400035
++#define ixPSX80_BIF_PCIE_TX_LAST_TLP1                                           0x1400036
++#define ixPSX80_BIF_PCIE_TX_LAST_TLP2                                           0x1400037
++#define ixPSX80_BIF_PCIE_TX_LAST_TLP3                                           0x1400038
++#define ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND                                    0x140003a
++#define ixPSX80_BIF_PCIE_I2C_REG_DATA                                           0x140003b
++#define ixPSX80_BIF_PCIE_CFG_CNTL                                               0x140003c
++#define ixPSX80_BIF_PCIE_LC_PM_CNTL                                             0x140003d
++#define ixPSX80_BIF_PCIE_P_CNTL                                                 0x1400040
++#define ixPSX80_BIF_PCIE_P_BUF_STATUS                                           0x1400041
++#define ixPSX80_BIF_PCIE_P_DECODER_STATUS                                       0x1400042
++#define ixPSX80_BIF_PCIE_P_MISC_STATUS                                          0x1400043
++#define ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET                                      0x1400050
++#define ixPSX80_BIF_PCIE_PERF_COUNT_CNTL                                        0x1400080
++#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK                                        0x1400081
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK                                      0x1400082
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK                                      0x1400083
++#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK                                    0x1400084
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK                                  0x1400085
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK                                  0x1400086
++#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK                                    0x1400087
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK                                  0x1400088
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK                                  0x1400089
++#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK                                    0x140008a
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK                                  0x140008b
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK                                  0x140008c
++#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK                                  0x140008d
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK                                0x140008e
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK                                0x140008f
++#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK                                 0x1400090
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK                               0x1400091
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK                               0x1400092
++#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL                              0x1400093
++#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL                              0x1400094
++#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2                                       0x1400095
++#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2                                     0x1400096
++#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2                                     0x1400097
++#define ixPSX80_BIF_PCIE_STRAP_F0                                               0x14000b0
++#define ixPSX80_BIF_PCIE_STRAP_MISC                                             0x14000c0
++#define ixPSX80_BIF_PCIE_STRAP_MISC2                                            0x14000c1
++#define ixPSX80_BIF_PCIE_STRAP_PI                                               0x14000c2
++#define ixPSX80_BIF_PCIE_STRAP_I2C_BD                                           0x14000c4
++#define ixPSX80_BIF_PCIE_PRBS_CLR                                               0x14000c8
++#define ixPSX80_BIF_PCIE_PRBS_STATUS1                                           0x14000c9
++#define ixPSX80_BIF_PCIE_PRBS_STATUS2                                           0x14000ca
++#define ixPSX80_BIF_PCIE_PRBS_FREERUN                                           0x14000cb
++#define ixPSX80_BIF_PCIE_PRBS_MISC                                              0x14000cc
++#define ixPSX80_BIF_PCIE_PRBS_USER_PATTERN                                      0x14000cd
++#define ixPSX80_BIF_PCIE_PRBS_LO_BITCNT                                         0x14000ce
++#define ixPSX80_BIF_PCIE_PRBS_HI_BITCNT                                         0x14000cf
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_0                                          0x14000d0
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_1                                          0x14000d1
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_2                                          0x14000d2
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_3                                          0x14000d3
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_4                                          0x14000d4
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_5                                          0x14000d5
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_6                                          0x14000d6
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_7                                          0x14000d7
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_8                                          0x14000d8
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_9                                          0x14000d9
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_10                                         0x14000da
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_11                                         0x14000db
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_12                                         0x14000dc
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_13                                         0x14000dd
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_14                                         0x14000de
++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_15                                         0x14000df
++#define ixPSX80_BIF_SWRST_COMMAND_STATUS                                        0x1400100
++#define ixPSX80_BIF_SWRST_GENERAL_CONTROL                                       0x1400101
++#define ixPSX80_BIF_SWRST_COMMAND_0                                             0x1400102
++#define ixPSX80_BIF_SWRST_COMMAND_1                                             0x1400103
++#define ixPSX80_BIF_SWRST_CONTROL_0                                             0x1400104
++#define ixPSX80_BIF_SWRST_CONTROL_1                                             0x1400105
++#define ixPSX80_BIF_SWRST_CONTROL_2                                             0x1400106
++#define ixPSX80_BIF_SWRST_CONTROL_3                                             0x1400107
++#define ixPSX80_BIF_SWRST_CONTROL_4                                             0x1400108
++#define ixPSX80_BIF_SWRST_CONTROL_5                                             0x1400109
++#define ixPSX80_BIF_SWRST_CONTROL_6                                             0x140010a
++#define ixPSX80_BIF_CPM_CONTROL                                                 0x1400118
++#define ixPSX80_BIF_LM_CONTROL                                                  0x1400120
++#define ixPSX80_BIF_LM_PCIETXMUX0                                               0x1400121
++#define ixPSX80_BIF_LM_PCIETXMUX1                                               0x1400122
++#define ixPSX80_BIF_LM_PCIETXMUX2                                               0x1400123
++#define ixPSX80_BIF_LM_PCIETXMUX3                                               0x1400124
++#define ixPSX80_BIF_LM_PCIERXMUX0                                               0x1400125
++#define ixPSX80_BIF_LM_PCIERXMUX1                                               0x1400126
++#define ixPSX80_BIF_LM_PCIERXMUX2                                               0x1400127
++#define ixPSX80_BIF_LM_PCIERXMUX3                                               0x1400128
++#define ixPSX80_BIF_LM_LANEENABLE                                               0x1400129
++#define ixPSX80_BIF_LM_PRBSCONTROL                                              0x140012a
++#define ixPSX80_BIF_LM_POWERCONTROL                                             0x140012b
++#define ixPSX80_BIF_LM_POWERCONTROL1                                            0x140012c
++#define ixPSX80_BIF_LM_POWERCONTROL2                                            0x140012d
++#define ixPSX80_BIF_LM_POWERCONTROL3                                            0x140012e
++#define ixPSX80_BIF_LM_POWERCONTROL4                                            0x140012f
++#define ixPSX81_BIF_PCIE_RESERVED                                               0x1410000
++#define ixPSX81_BIF_PCIE_SCRATCH                                                0x1410001
++#define ixPSX81_BIF_PCIE_HW_DEBUG                                               0x1410002
++#define ixPSX81_BIF_PCIE_RX_NUM_NAK                                             0x141000e
++#define ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED                                   0x141000f
++#define ixPSX81_BIF_PCIE_CNTL                                                   0x1410010
++#define ixPSX81_BIF_PCIE_CONFIG_CNTL                                            0x1410011
++#define ixPSX81_BIF_PCIE_DEBUG_CNTL                                             0x1410012
++#define ixPSX81_BIF_PCIE_CNTL2                                                  0x141001c
++#define ixPSX81_BIF_PCIE_RX_CNTL2                                               0x141001d
++#define ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL                                        0x141001e
++#define ixPSX81_BIF_PCIE_CI_CNTL                                                0x1410020
++#define ixPSX81_BIF_PCIE_BUS_CNTL                                               0x1410021
++#define ixPSX81_BIF_PCIE_LC_STATE6                                              0x1410022
++#define ixPSX81_BIF_PCIE_LC_STATE7                                              0x1410023
++#define ixPSX81_BIF_PCIE_LC_STATE8                                              0x1410024
++#define ixPSX81_BIF_PCIE_LC_STATE9                                              0x1410025
++#define ixPSX81_BIF_PCIE_LC_STATE10                                             0x1410026
++#define ixPSX81_BIF_PCIE_LC_STATE11                                             0x1410027
++#define ixPSX81_BIF_PCIE_LC_STATUS1                                             0x1410028
++#define ixPSX81_BIF_PCIE_LC_STATUS2                                             0x1410029
++#define ixPSX81_BIF_PCIE_WPR_CNTL                                               0x1410030
++#define ixPSX81_BIF_PCIE_RX_LAST_TLP0                                           0x1410031
++#define ixPSX81_BIF_PCIE_RX_LAST_TLP1                                           0x1410032
++#define ixPSX81_BIF_PCIE_RX_LAST_TLP2                                           0x1410033
++#define ixPSX81_BIF_PCIE_RX_LAST_TLP3                                           0x1410034
++#define ixPSX81_BIF_PCIE_TX_LAST_TLP0                                           0x1410035
++#define ixPSX81_BIF_PCIE_TX_LAST_TLP1                                           0x1410036
++#define ixPSX81_BIF_PCIE_TX_LAST_TLP2                                           0x1410037
++#define ixPSX81_BIF_PCIE_TX_LAST_TLP3                                           0x1410038
++#define ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND                                    0x141003a
++#define ixPSX81_BIF_PCIE_I2C_REG_DATA                                           0x141003b
++#define ixPSX81_BIF_PCIE_CFG_CNTL                                               0x141003c
++#define ixPSX81_BIF_PCIE_LC_PM_CNTL                                             0x141003d
++#define ixPSX81_BIF_PCIE_P_CNTL                                                 0x1410040
++#define ixPSX81_BIF_PCIE_P_BUF_STATUS                                           0x1410041
++#define ixPSX81_BIF_PCIE_P_DECODER_STATUS                                       0x1410042
++#define ixPSX81_BIF_PCIE_P_MISC_STATUS                                          0x1410043
++#define ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET                                      0x1410050
++#define ixPSX81_BIF_PCIE_PERF_COUNT_CNTL                                        0x1410080
++#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK                                        0x1410081
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK                                      0x1410082
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK                                      0x1410083
++#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK                                    0x1410084
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK                                  0x1410085
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK                                  0x1410086
++#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK                                    0x1410087
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK                                  0x1410088
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK                                  0x1410089
++#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK                                    0x141008a
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK                                  0x141008b
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK                                  0x141008c
++#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK                                  0x141008d
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK                                0x141008e
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK                                0x141008f
++#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK                                 0x1410090
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK                               0x1410091
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK                               0x1410092
++#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL                              0x1410093
++#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL                              0x1410094
++#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2                                       0x1410095
++#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2                                     0x1410096
++#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2                                     0x1410097
++#define ixPSX81_BIF_PCIE_STRAP_F0                                               0x14100b0
++#define ixPSX81_BIF_PCIE_STRAP_MISC                                             0x14100c0
++#define ixPSX81_BIF_PCIE_STRAP_MISC2                                            0x14100c1
++#define ixPSX81_BIF_PCIE_STRAP_PI                                               0x14100c2
++#define ixPSX81_BIF_PCIE_STRAP_I2C_BD                                           0x14100c4
++#define ixPSX81_BIF_PCIE_PRBS_CLR                                               0x14100c8
++#define ixPSX81_BIF_PCIE_PRBS_STATUS1                                           0x14100c9
++#define ixPSX81_BIF_PCIE_PRBS_STATUS2                                           0x14100ca
++#define ixPSX81_BIF_PCIE_PRBS_FREERUN                                           0x14100cb
++#define ixPSX81_BIF_PCIE_PRBS_MISC                                              0x14100cc
++#define ixPSX81_BIF_PCIE_PRBS_USER_PATTERN                                      0x14100cd
++#define ixPSX81_BIF_PCIE_PRBS_LO_BITCNT                                         0x14100ce
++#define ixPSX81_BIF_PCIE_PRBS_HI_BITCNT                                         0x14100cf
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_0                                          0x14100d0
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_1                                          0x14100d1
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_2                                          0x14100d2
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_3                                          0x14100d3
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_4                                          0x14100d4
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_5                                          0x14100d5
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_6                                          0x14100d6
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_7                                          0x14100d7
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_8                                          0x14100d8
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_9                                          0x14100d9
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_10                                         0x14100da
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_11                                         0x14100db
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_12                                         0x14100dc
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_13                                         0x14100dd
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_14                                         0x14100de
++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_15                                         0x14100df
++#define ixPSX81_BIF_SWRST_COMMAND_STATUS                                        0x1410100
++#define ixPSX81_BIF_SWRST_GENERAL_CONTROL                                       0x1410101
++#define ixPSX81_BIF_SWRST_COMMAND_0                                             0x1410102
++#define ixPSX81_BIF_SWRST_COMMAND_1                                             0x1410103
++#define ixPSX81_BIF_SWRST_CONTROL_0                                             0x1410104
++#define ixPSX81_BIF_SWRST_CONTROL_1                                             0x1410105
++#define ixPSX81_BIF_SWRST_CONTROL_2                                             0x1410106
++#define ixPSX81_BIF_SWRST_CONTROL_3                                             0x1410107
++#define ixPSX81_BIF_SWRST_CONTROL_4                                             0x1410108
++#define ixPSX81_BIF_SWRST_CONTROL_5                                             0x1410109
++#define ixPSX81_BIF_SWRST_CONTROL_6                                             0x141010a
++#define ixPSX81_BIF_CPM_CONTROL                                                 0x1410118
++#define ixPSX81_BIF_LM_CONTROL                                                  0x1410120
++#define ixPSX81_BIF_LM_PCIETXMUX0                                               0x1410121
++#define ixPSX81_BIF_LM_PCIETXMUX1                                               0x1410122
++#define ixPSX81_BIF_LM_PCIETXMUX2                                               0x1410123
++#define ixPSX81_BIF_LM_PCIETXMUX3                                               0x1410124
++#define ixPSX81_BIF_LM_PCIERXMUX0                                               0x1410125
++#define ixPSX81_BIF_LM_PCIERXMUX1                                               0x1410126
++#define ixPSX81_BIF_LM_PCIERXMUX2                                               0x1410127
++#define ixPSX81_BIF_LM_PCIERXMUX3                                               0x1410128
++#define ixPSX81_BIF_LM_LANEENABLE                                               0x1410129
++#define ixPSX81_BIF_LM_PRBSCONTROL                                              0x141012a
++#define ixPSX81_BIF_LM_POWERCONTROL                                             0x141012b
++#define ixPSX81_BIF_LM_POWERCONTROL1                                            0x141012c
++#define ixPSX81_BIF_LM_POWERCONTROL2                                            0x141012d
++#define ixPSX81_BIF_LM_POWERCONTROL3                                            0x141012e
++#define ixPSX81_BIF_LM_POWERCONTROL4                                            0x141012f
++#define ixPSX80_PHY0_COM_COMMON_FUSE1                                           0x1206200
++#define ixPSX80_PHY0_COM_COMMON_FUSE2                                           0x1206201
++#define ixPSX80_PHY0_COM_COMMON_FUSE3                                           0x1206202
++#define ixPSX80_PHY0_COM_COMMON_ELECIDLE                                        0x1206204
++#define ixPSX80_PHY0_COM_COMMON_DFX                                             0x1206205
++#define ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM                                  0x1206206
++#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH35                                     0x1206207
++#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH60                                     0x1206208
++#define ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT                                    0x1206209
++#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL1                                       0x120620a
++#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL2                                       0x120620b
++#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL                               0x120620c
++#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1                              0x120620d
++#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL                               0x120620e
++#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1                              0x120620f
++#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1                                      0x1206210
++#define ixPSX80_PHY0_COM_COMMON_LNCNTRL                                         0x1206211
++#define ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG                                     0x1206212
++#define ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG                                     0x1206213
++#define ixPSX80_PHY0_COM_COMMON_CDR_PHCTL                                       0x1206214
++#define ixPSX80_PHY0_COM_COMMON_CDR_FRCTL                                       0x1206215
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST                            0x120fe00
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0                                0x1200000
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1                                0x1200100
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2                                0x1200200
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3                                0x1200300
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4                                0x1200400
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5                                0x1200500
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6                                0x1200600
++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7                                0x1200700
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST                         0x120fe01
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0                             0x1200001
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1                             0x1200101
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2                             0x1200201
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3                             0x1200301
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4                             0x1200401
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5                             0x1200501
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6                             0x1200601
++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7                             0x1200701
++#define ixPSX80_PHY0_RX_RX_CTL_BROADCAST                                        0x120fe02
++#define ixPSX80_PHY0_RX_RX_CTL_LANE0                                            0x1200002
++#define ixPSX80_PHY0_RX_RX_CTL_LANE1                                            0x1200102
++#define ixPSX80_PHY0_RX_RX_CTL_LANE2                                            0x1200202
++#define ixPSX80_PHY0_RX_RX_CTL_LANE3                                            0x1200302
++#define ixPSX80_PHY0_RX_RX_CTL_LANE4                                            0x1200402
++#define ixPSX80_PHY0_RX_RX_CTL_LANE5                                            0x1200502
++#define ixPSX80_PHY0_RX_RX_CTL_LANE6                                            0x1200602
++#define ixPSX80_PHY0_RX_RX_CTL_LANE7                                            0x1200702
++#define ixPSX80_PHY0_RX_DLL_CTL_BROADCAST                                       0x120fe03
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE0                                           0x1200003
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE1                                           0x1200103
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE2                                           0x1200203
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE3                                           0x1200303
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE4                                           0x1200403
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE5                                           0x1200503
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE6                                           0x1200603
++#define ixPSX80_PHY0_RX_DLL_CTL_LANE7                                           0x1200703
++#define ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST                                   0x120fe04
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE0                                       0x1200004
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE1                                       0x1200104
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE2                                       0x1200204
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE3                                       0x1200304
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE4                                       0x1200404
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE5                                       0x1200504
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE6                                       0x1200604
++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE7                                       0x1200704
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST                                0x120fe05
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0                                    0x1200005
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1                                    0x1200105
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2                                    0x1200205
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3                                    0x1200305
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4                                    0x1200405
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5                                    0x1200505
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6                                    0x1200605
++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7                                    0x1200705
++#define ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST                                      0x120fe0a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE0                                          0x120000a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE1                                          0x120010a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE2                                          0x120020a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE3                                          0x120030a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE4                                          0x120040a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE5                                          0x120050a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE6                                          0x120060a
++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE7                                          0x120070a
++#define ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST                                    0x120fe0b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE0                                        0x120000b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE1                                        0x120010b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE2                                        0x120020b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE3                                        0x120030b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE4                                        0x120040b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE5                                        0x120050b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE6                                        0x120060b
++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE7                                        0x120070b
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST                              0x120fe0c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0                                  0x120000c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1                                  0x120010c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2                                  0x120020c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3                                  0x120030c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4                                  0x120040c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5                                  0x120050c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6                                  0x120060c
++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7                                  0x120070c
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST                                    0x120fe0d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0                                        0x120000d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1                                        0x120010d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2                                        0x120020d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3                                        0x120030d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4                                        0x120040d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5                                        0x120050d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6                                        0x120060d
++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7                                        0x120070d
++#define ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST                                     0x120fe0e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE0                                         0x120000e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE1                                         0x120010e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE2                                         0x120020e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE3                                         0x120030e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE4                                         0x120040e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE5                                         0x120050e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE6                                         0x120060e
++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE7                                         0x120070e
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST                            0x120ff00
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0                                0x1202000
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1                                0x1202100
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2                                0x1202200
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3                                0x1202300
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4                                0x1202400
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5                                0x1202500
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6                                0x1202600
++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7                                0x1202700
++#define ixPSX80_PHY0_TX_DFX_BROADCAST                                           0x120ff01
++#define ixPSX80_PHY0_TX_DFX_LANE0                                               0x1202001
++#define ixPSX80_PHY0_TX_DFX_LANE1                                               0x1202101
++#define ixPSX80_PHY0_TX_DFX_LANE2                                               0x1202201
++#define ixPSX80_PHY0_TX_DFX_LANE3                                               0x1202301
++#define ixPSX80_PHY0_TX_DFX_LANE4                                               0x1202401
++#define ixPSX80_PHY0_TX_DFX_LANE5                                               0x1202501
++#define ixPSX80_PHY0_TX_DFX_LANE6                                               0x1202601
++#define ixPSX80_PHY0_TX_DFX_LANE7                                               0x1202701
++#define ixPSX80_PHY0_TX_DEEMPH_BROADCAST                                        0x120ff02
++#define ixPSX80_PHY0_TX_DEEMPH_LANE0                                            0x1202002
++#define ixPSX80_PHY0_TX_DEEMPH_LANE1                                            0x1202102
++#define ixPSX80_PHY0_TX_DEEMPH_LANE2                                            0x1202202
++#define ixPSX80_PHY0_TX_DEEMPH_LANE3                                            0x1202302
++#define ixPSX80_PHY0_TX_DEEMPH_LANE4                                            0x1202402
++#define ixPSX80_PHY0_TX_DEEMPH_LANE5                                            0x1202502
++#define ixPSX80_PHY0_TX_DEEMPH_LANE6                                            0x1202602
++#define ixPSX80_PHY0_TX_DEEMPH_LANE7                                            0x1202702
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST                                 0x120ff03
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0                                     0x1202003
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1                                     0x1202103
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2                                     0x1202203
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3                                     0x1202303
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4                                     0x1202403
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5                                     0x1202503
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6                                     0x1202603
++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7                                     0x1202703
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST                              0x120ff04
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0                                  0x1202004
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1                                  0x1202104
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2                                  0x1202204
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3                                  0x1202304
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4                                  0x1202404
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5                                  0x1202504
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6                                  0x1202604
++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7                                  0x1202704
++#define ixPSX80_PHY0_TX_TXCNTRL_BROADCAST                                       0x120ff06
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE0                                           0x1202006
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE1                                           0x1202106
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE2                                           0x1202206
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE3                                           0x1202306
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE4                                           0x1202406
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE5                                           0x1202506
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE6                                           0x1202606
++#define ixPSX80_PHY0_TX_TXCNTRL_LANE7                                           0x1202706
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST                         0x120ff07
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0                             0x1202007
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1                             0x1202107
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2                             0x1202207
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3                             0x1202307
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4                             0x1202407
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5                             0x1202507
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6                             0x1202607
++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7                             0x1202707
++#define ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn                                    0x1204180
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt                               0x1204101
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl                                  0x1204102
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1                               0x1204103
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2                               0x1204104
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode                                 0x1204105
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl                               0x1204108
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3                               0x1204109
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess                                 0x120410a
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4                               0x120410b
++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5                               0x120410c
++#define ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn                                    0x1204080
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt                               0x1204001
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl                                  0x1204002
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1                               0x1204003
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2                               0x1204004
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode                                 0x1204005
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl                                   0x1204007
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl                               0x1204008
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3                               0x1204009
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4                               0x120400b
++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5                               0x120400c
++#define ixPSX81_PHY0_COM_COMMON_FUSE1                                           0x1216200
++#define ixPSX81_PHY0_COM_COMMON_FUSE2                                           0x1216201
++#define ixPSX81_PHY0_COM_COMMON_FUSE3                                           0x1216202
++#define ixPSX81_PHY0_COM_COMMON_ELECIDLE                                        0x1216204
++#define ixPSX81_PHY0_COM_COMMON_DFX                                             0x1216205
++#define ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM                                  0x1216206
++#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH35                                     0x1216207
++#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH60                                     0x1216208
++#define ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT                                    0x1216209
++#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL1                                       0x121620a
++#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL2                                       0x121620b
++#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL                               0x121620c
++#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1                              0x121620d
++#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL                               0x121620e
++#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1                              0x121620f
++#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1                                      0x1216210
++#define ixPSX81_PHY0_COM_COMMON_LNCNTRL                                         0x1216211
++#define ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG                                     0x1216212
++#define ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG                                     0x1216213
++#define ixPSX81_PHY0_COM_COMMON_CDR_PHCTL                                       0x1216214
++#define ixPSX81_PHY0_COM_COMMON_CDR_FRCTL                                       0x1216215
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST                            0x121fe00
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0                                0x1210000
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1                                0x1210100
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2                                0x1210200
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3                                0x1210300
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4                                0x1210400
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5                                0x1210500
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6                                0x1210600
++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7                                0x1210700
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST                         0x121fe01
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0                             0x1210001
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1                             0x1210101
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2                             0x1210201
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3                             0x1210301
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4                             0x1210401
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5                             0x1210501
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6                             0x1210601
++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7                             0x1210701
++#define ixPSX81_PHY0_RX_RX_CTL_BROADCAST                                        0x121fe02
++#define ixPSX81_PHY0_RX_RX_CTL_LANE0                                            0x1210002
++#define ixPSX81_PHY0_RX_RX_CTL_LANE1                                            0x1210102
++#define ixPSX81_PHY0_RX_RX_CTL_LANE2                                            0x1210202
++#define ixPSX81_PHY0_RX_RX_CTL_LANE3                                            0x1210302
++#define ixPSX81_PHY0_RX_RX_CTL_LANE4                                            0x1210402
++#define ixPSX81_PHY0_RX_RX_CTL_LANE5                                            0x1210502
++#define ixPSX81_PHY0_RX_RX_CTL_LANE6                                            0x1210602
++#define ixPSX81_PHY0_RX_RX_CTL_LANE7                                            0x1210702
++#define ixPSX81_PHY0_RX_DLL_CTL_BROADCAST                                       0x121fe03
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE0                                           0x1210003
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE1                                           0x1210103
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE2                                           0x1210203
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE3                                           0x1210303
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE4                                           0x1210403
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE5                                           0x1210503
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE6                                           0x1210603
++#define ixPSX81_PHY0_RX_DLL_CTL_LANE7                                           0x1210703
++#define ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST                                   0x121fe04
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE0                                       0x1210004
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE1                                       0x1210104
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE2                                       0x1210204
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE3                                       0x1210304
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE4                                       0x1210404
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE5                                       0x1210504
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE6                                       0x1210604
++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE7                                       0x1210704
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST                                0x121fe05
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0                                    0x1210005
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1                                    0x1210105
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2                                    0x1210205
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3                                    0x1210305
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4                                    0x1210405
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5                                    0x1210505
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6                                    0x1210605
++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7                                    0x1210705
++#define ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST                                      0x121fe0a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE0                                          0x121000a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE1                                          0x121010a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE2                                          0x121020a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE3                                          0x121030a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE4                                          0x121040a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE5                                          0x121050a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE6                                          0x121060a
++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE7                                          0x121070a
++#define ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST                                    0x121fe0b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE0                                        0x121000b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE1                                        0x121010b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE2                                        0x121020b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE3                                        0x121030b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE4                                        0x121040b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE5                                        0x121050b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE6                                        0x121060b
++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE7                                        0x121070b
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST                              0x121fe0c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0                                  0x121000c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1                                  0x121010c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2                                  0x121020c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3                                  0x121030c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4                                  0x121040c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5                                  0x121050c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6                                  0x121060c
++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7                                  0x121070c
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST                                    0x121fe0d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0                                        0x121000d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1                                        0x121010d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2                                        0x121020d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3                                        0x121030d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4                                        0x121040d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5                                        0x121050d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6                                        0x121060d
++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7                                        0x121070d
++#define ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST                                     0x121fe0e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE0                                         0x121000e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE1                                         0x121010e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE2                                         0x121020e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE3                                         0x121030e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE4                                         0x121040e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE5                                         0x121050e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE6                                         0x121060e
++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE7                                         0x121070e
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST                            0x121ff00
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0                                0x1212000
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1                                0x1212100
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2                                0x1212200
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3                                0x1212300
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4                                0x1212400
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5                                0x1212500
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6                                0x1212600
++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7                                0x1212700
++#define ixPSX81_PHY0_TX_DFX_BROADCAST                                           0x121ff01
++#define ixPSX81_PHY0_TX_DFX_LANE0                                               0x1212001
++#define ixPSX81_PHY0_TX_DFX_LANE1                                               0x1212101
++#define ixPSX81_PHY0_TX_DFX_LANE2                                               0x1212201
++#define ixPSX81_PHY0_TX_DFX_LANE3                                               0x1212301
++#define ixPSX81_PHY0_TX_DFX_LANE4                                               0x1212401
++#define ixPSX81_PHY0_TX_DFX_LANE5                                               0x1212501
++#define ixPSX81_PHY0_TX_DFX_LANE6                                               0x1212601
++#define ixPSX81_PHY0_TX_DFX_LANE7                                               0x1212701
++#define ixPSX81_PHY0_TX_DEEMPH_BROADCAST                                        0x121ff02
++#define ixPSX81_PHY0_TX_DEEMPH_LANE0                                            0x1212002
++#define ixPSX81_PHY0_TX_DEEMPH_LANE1                                            0x1212102
++#define ixPSX81_PHY0_TX_DEEMPH_LANE2                                            0x1212202
++#define ixPSX81_PHY0_TX_DEEMPH_LANE3                                            0x1212302
++#define ixPSX81_PHY0_TX_DEEMPH_LANE4                                            0x1212402
++#define ixPSX81_PHY0_TX_DEEMPH_LANE5                                            0x1212502
++#define ixPSX81_PHY0_TX_DEEMPH_LANE6                                            0x1212602
++#define ixPSX81_PHY0_TX_DEEMPH_LANE7                                            0x1212702
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST                                 0x121ff03
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0                                     0x1212003
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1                                     0x1212103
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2                                     0x1212203
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3                                     0x1212303
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4                                     0x1212403
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5                                     0x1212503
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6                                     0x1212603
++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7                                     0x1212703
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST                              0x121ff04
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0                                  0x1212004
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1                                  0x1212104
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2                                  0x1212204
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3                                  0x1212304
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4                                  0x1212404
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5                                  0x1212504
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6                                  0x1212604
++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7                                  0x1212704
++#define ixPSX81_PHY0_TX_TXCNTRL_BROADCAST                                       0x121ff06
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE0                                           0x1212006
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE1                                           0x1212106
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE2                                           0x1212206
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE3                                           0x1212306
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE4                                           0x1212406
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE5                                           0x1212506
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE6                                           0x1212606
++#define ixPSX81_PHY0_TX_TXCNTRL_LANE7                                           0x1212706
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST                         0x121ff07
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0                             0x1212007
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1                             0x1212107
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2                             0x1212207
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3                             0x1212307
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4                             0x1212407
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5                             0x1212507
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6                             0x1212607
++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7                             0x1212707
++#define ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn                                    0x1214180
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt                               0x1214101
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl                                  0x1214102
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1                               0x1214103
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2                               0x1214104
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode                                 0x1214105
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl                               0x1214108
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3                               0x1214109
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess                                 0x121410a
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4                               0x121410b
++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5                               0x121410c
++#define ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn                                    0x1214080
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt                               0x1214001
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl                                  0x1214002
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1                               0x1214003
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2                               0x1214004
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode                                 0x1214005
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl                                   0x1214007
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl                               0x1214008
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3                               0x1214009
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4                               0x121400b
++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5                               0x121400c
++#define ixPSX80_PIF0_SCRATCH                                                    0x1100001
++#define ixPSX80_PIF0_HW_DEBUG                                                   0x1100002
++#define ixPSX80_PIF0_STRAP_0                                                    0x1100003
++#define ixPSX80_PIF0_CTRL                                                       0x1100004
++#define ixPSX80_PIF0_TX_CTRL                                                    0x1100008
++#define ixPSX80_PIF0_TX_CTRL2                                                   0x1100009
++#define ixPSX80_PIF0_RX_CTRL                                                    0x110000a
++#define ixPSX80_PIF0_RX_CTRL2                                                   0x110000b
++#define ixPSX80_PIF0_GLB_OVRD                                                   0x110000c
++#define ixPSX80_PIF0_GLB_OVRD2                                                  0x110000d
++#define ixPSX80_PIF0_BIF_CMD_STATUS                                             0x1100010
++#define ixPSX80_PIF0_CMD_BUS_CTRL                                               0x1100011
++#define ixPSX80_PIF0_CMD_BUS_GLB_OVRD                                           0x1100013
++#define ixPSX80_PIF0_LANE0_OVRD                                                 0x1100014
++#define ixPSX80_PIF0_LANE0_OVRD2                                                0x1100015
++#define ixPSX80_PIF0_LANE1_OVRD                                                 0x1100016
++#define ixPSX80_PIF0_LANE1_OVRD2                                                0x1100017
++#define ixPSX80_PIF0_LANE2_OVRD                                                 0x1100018
++#define ixPSX80_PIF0_LANE2_OVRD2                                                0x1100019
++#define ixPSX80_PIF0_LANE3_OVRD                                                 0x110001a
++#define ixPSX80_PIF0_LANE3_OVRD2                                                0x110001b
++#define ixPSX80_PIF0_LANE4_OVRD                                                 0x110001c
++#define ixPSX80_PIF0_LANE4_OVRD2                                                0x110001d
++#define ixPSX80_PIF0_LANE5_OVRD                                                 0x110001e
++#define ixPSX80_PIF0_LANE5_OVRD2                                                0x110001f
++#define ixPSX80_PIF0_LANE6_OVRD                                                 0x1100020
++#define ixPSX80_PIF0_LANE6_OVRD2                                                0x1100021
++#define ixPSX80_PIF0_LANE7_OVRD                                                 0x1100022
++#define ixPSX80_PIF0_LANE7_OVRD2                                                0x1100023
++#define ixPSX81_PIF0_SCRATCH                                                    0x1110001
++#define ixPSX81_PIF0_HW_DEBUG                                                   0x1110002
++#define ixPSX81_PIF0_STRAP_0                                                    0x1110003
++#define ixPSX81_PIF0_CTRL                                                       0x1110004
++#define ixPSX81_PIF0_TX_CTRL                                                    0x1110008
++#define ixPSX81_PIF0_TX_CTRL2                                                   0x1110009
++#define ixPSX81_PIF0_RX_CTRL                                                    0x111000a
++#define ixPSX81_PIF0_RX_CTRL2                                                   0x111000b
++#define ixPSX81_PIF0_GLB_OVRD                                                   0x111000c
++#define ixPSX81_PIF0_GLB_OVRD2                                                  0x111000d
++#define ixPSX81_PIF0_BIF_CMD_STATUS                                             0x1110010
++#define ixPSX81_PIF0_CMD_BUS_CTRL                                               0x1110011
++#define ixPSX81_PIF0_CMD_BUS_GLB_OVRD                                           0x1110013
++#define ixPSX81_PIF0_LANE0_OVRD                                                 0x1110014
++#define ixPSX81_PIF0_LANE0_OVRD2                                                0x1110015
++#define ixPSX81_PIF0_LANE1_OVRD                                                 0x1110016
++#define ixPSX81_PIF0_LANE1_OVRD2                                                0x1110017
++#define ixPSX81_PIF0_LANE2_OVRD                                                 0x1110018
++#define ixPSX81_PIF0_LANE2_OVRD2                                                0x1110019
++#define ixPSX81_PIF0_LANE3_OVRD                                                 0x111001a
++#define ixPSX81_PIF0_LANE3_OVRD2                                                0x111001b
++#define ixPSX81_PIF0_LANE4_OVRD                                                 0x111001c
++#define ixPSX81_PIF0_LANE4_OVRD2                                                0x111001d
++#define ixPSX81_PIF0_LANE5_OVRD                                                 0x111001e
++#define ixPSX81_PIF0_LANE5_OVRD2                                                0x111001f
++#define ixPSX81_PIF0_LANE6_OVRD                                                 0x1110020
++#define ixPSX81_PIF0_LANE6_OVRD2                                                0x1110021
++#define ixPSX81_PIF0_LANE7_OVRD                                                 0x1110022
++#define ixPSX81_PIF0_LANE7_OVRD2                                                0x1110023
++
++#endif /* BIF_5_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
+new file mode 100644
+index 0000000..d8d5ae0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
+@@ -0,0 +1,1068 @@
++/*
++ * BIF_5_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_5_1_ENUM_H
++#define BIF_5_1_ENUM_H
++
++typedef enum DebugBlockId {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_UVDU                                = 0xd,
++	DBG_BLOCK_ID_SQA                                 = 0xe,
++	DBG_BLOCK_ID_SDMA0                               = 0xf,
++	DBG_BLOCK_ID_SDMA1                               = 0x10,
++	DBG_BLOCK_ID_SPIM                                = 0x11,
++	DBG_BLOCK_ID_GDS                                 = 0x12,
++	DBG_BLOCK_ID_VC0                                 = 0x13,
++	DBG_BLOCK_ID_VC1                                 = 0x14,
++	DBG_BLOCK_ID_PA0                                 = 0x15,
++	DBG_BLOCK_ID_PA1                                 = 0x16,
++	DBG_BLOCK_ID_CP0                                 = 0x17,
++	DBG_BLOCK_ID_CP1                                 = 0x18,
++	DBG_BLOCK_ID_CP2                                 = 0x19,
++	DBG_BLOCK_ID_XBR                                 = 0x1a,
++	DBG_BLOCK_ID_UVDM                                = 0x1b,
++	DBG_BLOCK_ID_VGT0                                = 0x1c,
++	DBG_BLOCK_ID_VGT1                                = 0x1d,
++	DBG_BLOCK_ID_IA                                  = 0x1e,
++	DBG_BLOCK_ID_SXM0                                = 0x1f,
++	DBG_BLOCK_ID_SXM1                                = 0x20,
++	DBG_BLOCK_ID_SCT0                                = 0x21,
++	DBG_BLOCK_ID_SCT1                                = 0x22,
++	DBG_BLOCK_ID_SPM0                                = 0x23,
++	DBG_BLOCK_ID_SPM1                                = 0x24,
++	DBG_BLOCK_ID_UNUSED0                             = 0x25,
++	DBG_BLOCK_ID_UNUSED1                             = 0x26,
++	DBG_BLOCK_ID_TCAA                                = 0x27,
++	DBG_BLOCK_ID_TCAB                                = 0x28,
++	DBG_BLOCK_ID_TCCA                                = 0x29,
++	DBG_BLOCK_ID_TCCB                                = 0x2a,
++	DBG_BLOCK_ID_MCC0                                = 0x2b,
++	DBG_BLOCK_ID_MCC1                                = 0x2c,
++	DBG_BLOCK_ID_MCC2                                = 0x2d,
++	DBG_BLOCK_ID_MCC3                                = 0x2e,
++	DBG_BLOCK_ID_SXS0                                = 0x2f,
++	DBG_BLOCK_ID_SXS1                                = 0x30,
++	DBG_BLOCK_ID_SXS2                                = 0x31,
++	DBG_BLOCK_ID_SXS3                                = 0x32,
++	DBG_BLOCK_ID_SXS4                                = 0x33,
++	DBG_BLOCK_ID_SXS5                                = 0x34,
++	DBG_BLOCK_ID_SXS6                                = 0x35,
++	DBG_BLOCK_ID_SXS7                                = 0x36,
++	DBG_BLOCK_ID_SXS8                                = 0x37,
++	DBG_BLOCK_ID_SXS9                                = 0x38,
++	DBG_BLOCK_ID_BCI0                                = 0x39,
++	DBG_BLOCK_ID_BCI1                                = 0x3a,
++	DBG_BLOCK_ID_BCI2                                = 0x3b,
++	DBG_BLOCK_ID_BCI3                                = 0x3c,
++	DBG_BLOCK_ID_MCB                                 = 0x3d,
++	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
++	DBG_BLOCK_ID_SQA00                               = 0x3f,
++	DBG_BLOCK_ID_SQA01                               = 0x40,
++	DBG_BLOCK_ID_SQA02                               = 0x41,
++	DBG_BLOCK_ID_SQA10                               = 0x42,
++	DBG_BLOCK_ID_SQA11                               = 0x43,
++	DBG_BLOCK_ID_SQA12                               = 0x44,
++	DBG_BLOCK_ID_UNUSED7                             = 0x45,
++	DBG_BLOCK_ID_UNUSED8                             = 0x46,
++	DBG_BLOCK_ID_SQB00                               = 0x47,
++	DBG_BLOCK_ID_SQB01                               = 0x48,
++	DBG_BLOCK_ID_SQB10                               = 0x49,
++	DBG_BLOCK_ID_SQB11                               = 0x4a,
++	DBG_BLOCK_ID_SQ00                                = 0x4b,
++	DBG_BLOCK_ID_SQ01                                = 0x4c,
++	DBG_BLOCK_ID_SQ10                                = 0x4d,
++	DBG_BLOCK_ID_SQ11                                = 0x4e,
++	DBG_BLOCK_ID_CB00                                = 0x4f,
++	DBG_BLOCK_ID_CB01                                = 0x50,
++	DBG_BLOCK_ID_CB02                                = 0x51,
++	DBG_BLOCK_ID_CB03                                = 0x52,
++	DBG_BLOCK_ID_CB04                                = 0x53,
++	DBG_BLOCK_ID_UNUSED9                             = 0x54,
++	DBG_BLOCK_ID_UNUSED10                            = 0x55,
++	DBG_BLOCK_ID_UNUSED11                            = 0x56,
++	DBG_BLOCK_ID_CB10                                = 0x57,
++	DBG_BLOCK_ID_CB11                                = 0x58,
++	DBG_BLOCK_ID_CB12                                = 0x59,
++	DBG_BLOCK_ID_CB13                                = 0x5a,
++	DBG_BLOCK_ID_CB14                                = 0x5b,
++	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
++	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
++	DBG_BLOCK_ID_TCP0                                = 0x5f,
++	DBG_BLOCK_ID_TCP1                                = 0x60,
++	DBG_BLOCK_ID_TCP2                                = 0x61,
++	DBG_BLOCK_ID_TCP3                                = 0x62,
++	DBG_BLOCK_ID_TCP4                                = 0x63,
++	DBG_BLOCK_ID_TCP5                                = 0x64,
++	DBG_BLOCK_ID_TCP6                                = 0x65,
++	DBG_BLOCK_ID_TCP7                                = 0x66,
++	DBG_BLOCK_ID_TCP8                                = 0x67,
++	DBG_BLOCK_ID_TCP9                                = 0x68,
++	DBG_BLOCK_ID_TCP10                               = 0x69,
++	DBG_BLOCK_ID_TCP11                               = 0x6a,
++	DBG_BLOCK_ID_TCP12                               = 0x6b,
++	DBG_BLOCK_ID_TCP13                               = 0x6c,
++	DBG_BLOCK_ID_TCP14                               = 0x6d,
++	DBG_BLOCK_ID_TCP15                               = 0x6e,
++	DBG_BLOCK_ID_TCP16                               = 0x6f,
++	DBG_BLOCK_ID_TCP17                               = 0x70,
++	DBG_BLOCK_ID_TCP18                               = 0x71,
++	DBG_BLOCK_ID_TCP19                               = 0x72,
++	DBG_BLOCK_ID_TCP20                               = 0x73,
++	DBG_BLOCK_ID_TCP21                               = 0x74,
++	DBG_BLOCK_ID_TCP22                               = 0x75,
++	DBG_BLOCK_ID_TCP23                               = 0x76,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
++	DBG_BLOCK_ID_DB00                                = 0x7f,
++	DBG_BLOCK_ID_DB01                                = 0x80,
++	DBG_BLOCK_ID_DB02                                = 0x81,
++	DBG_BLOCK_ID_DB03                                = 0x82,
++	DBG_BLOCK_ID_DB04                                = 0x83,
++	DBG_BLOCK_ID_UNUSED15                            = 0x84,
++	DBG_BLOCK_ID_UNUSED16                            = 0x85,
++	DBG_BLOCK_ID_UNUSED17                            = 0x86,
++	DBG_BLOCK_ID_DB10                                = 0x87,
++	DBG_BLOCK_ID_DB11                                = 0x88,
++	DBG_BLOCK_ID_DB12                                = 0x89,
++	DBG_BLOCK_ID_DB13                                = 0x8a,
++	DBG_BLOCK_ID_DB14                                = 0x8b,
++	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
++	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
++	DBG_BLOCK_ID_TCC0                                = 0x8f,
++	DBG_BLOCK_ID_TCC1                                = 0x90,
++	DBG_BLOCK_ID_TCC2                                = 0x91,
++	DBG_BLOCK_ID_TCC3                                = 0x92,
++	DBG_BLOCK_ID_TCC4                                = 0x93,
++	DBG_BLOCK_ID_TCC5                                = 0x94,
++	DBG_BLOCK_ID_TCC6                                = 0x95,
++	DBG_BLOCK_ID_TCC7                                = 0x96,
++	DBG_BLOCK_ID_SPS00                               = 0x97,
++	DBG_BLOCK_ID_SPS01                               = 0x98,
++	DBG_BLOCK_ID_SPS02                               = 0x99,
++	DBG_BLOCK_ID_SPS10                               = 0x9a,
++	DBG_BLOCK_ID_SPS11                               = 0x9b,
++	DBG_BLOCK_ID_SPS12                               = 0x9c,
++	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
++	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
++	DBG_BLOCK_ID_TA00                                = 0x9f,
++	DBG_BLOCK_ID_TA01                                = 0xa0,
++	DBG_BLOCK_ID_TA02                                = 0xa1,
++	DBG_BLOCK_ID_TA03                                = 0xa2,
++	DBG_BLOCK_ID_TA04                                = 0xa3,
++	DBG_BLOCK_ID_TA05                                = 0xa4,
++	DBG_BLOCK_ID_TA06                                = 0xa5,
++	DBG_BLOCK_ID_TA07                                = 0xa6,
++	DBG_BLOCK_ID_TA08                                = 0xa7,
++	DBG_BLOCK_ID_TA09                                = 0xa8,
++	DBG_BLOCK_ID_TA0A                                = 0xa9,
++	DBG_BLOCK_ID_TA0B                                = 0xaa,
++	DBG_BLOCK_ID_UNUSED23                            = 0xab,
++	DBG_BLOCK_ID_UNUSED24                            = 0xac,
++	DBG_BLOCK_ID_UNUSED25                            = 0xad,
++	DBG_BLOCK_ID_UNUSED26                            = 0xae,
++	DBG_BLOCK_ID_TA10                                = 0xaf,
++	DBG_BLOCK_ID_TA11                                = 0xb0,
++	DBG_BLOCK_ID_TA12                                = 0xb1,
++	DBG_BLOCK_ID_TA13                                = 0xb2,
++	DBG_BLOCK_ID_TA14                                = 0xb3,
++	DBG_BLOCK_ID_TA15                                = 0xb4,
++	DBG_BLOCK_ID_TA16                                = 0xb5,
++	DBG_BLOCK_ID_TA17                                = 0xb6,
++	DBG_BLOCK_ID_TA18                                = 0xb7,
++	DBG_BLOCK_ID_TA19                                = 0xb8,
++	DBG_BLOCK_ID_TA1A                                = 0xb9,
++	DBG_BLOCK_ID_TA1B                                = 0xba,
++	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
++	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
++	DBG_BLOCK_ID_TD00                                = 0xbf,
++	DBG_BLOCK_ID_TD01                                = 0xc0,
++	DBG_BLOCK_ID_TD02                                = 0xc1,
++	DBG_BLOCK_ID_TD03                                = 0xc2,
++	DBG_BLOCK_ID_TD04                                = 0xc3,
++	DBG_BLOCK_ID_TD05                                = 0xc4,
++	DBG_BLOCK_ID_TD06                                = 0xc5,
++	DBG_BLOCK_ID_TD07                                = 0xc6,
++	DBG_BLOCK_ID_TD08                                = 0xc7,
++	DBG_BLOCK_ID_TD09                                = 0xc8,
++	DBG_BLOCK_ID_TD0A                                = 0xc9,
++	DBG_BLOCK_ID_TD0B                                = 0xca,
++	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
++	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED34                            = 0xce,
++	DBG_BLOCK_ID_TD10                                = 0xcf,
++	DBG_BLOCK_ID_TD11                                = 0xd0,
++	DBG_BLOCK_ID_TD12                                = 0xd1,
++	DBG_BLOCK_ID_TD13                                = 0xd2,
++	DBG_BLOCK_ID_TD14                                = 0xd3,
++	DBG_BLOCK_ID_TD15                                = 0xd4,
++	DBG_BLOCK_ID_TD16                                = 0xd5,
++	DBG_BLOCK_ID_TD17                                = 0xd6,
++	DBG_BLOCK_ID_TD18                                = 0xd7,
++	DBG_BLOCK_ID_TD19                                = 0xd8,
++	DBG_BLOCK_ID_TD1A                                = 0xd9,
++	DBG_BLOCK_ID_TD1B                                = 0xda,
++	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
++	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED38                            = 0xde,
++	DBG_BLOCK_ID_LDS00                               = 0xdf,
++	DBG_BLOCK_ID_LDS01                               = 0xe0,
++	DBG_BLOCK_ID_LDS02                               = 0xe1,
++	DBG_BLOCK_ID_LDS03                               = 0xe2,
++	DBG_BLOCK_ID_LDS04                               = 0xe3,
++	DBG_BLOCK_ID_LDS05                               = 0xe4,
++	DBG_BLOCK_ID_LDS06                               = 0xe5,
++	DBG_BLOCK_ID_LDS07                               = 0xe6,
++	DBG_BLOCK_ID_LDS08                               = 0xe7,
++	DBG_BLOCK_ID_LDS09                               = 0xe8,
++	DBG_BLOCK_ID_LDS0A                               = 0xe9,
++	DBG_BLOCK_ID_LDS0B                               = 0xea,
++	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
++	DBG_BLOCK_ID_UNUSED40                            = 0xec,
++	DBG_BLOCK_ID_UNUSED41                            = 0xed,
++	DBG_BLOCK_ID_UNUSED42                            = 0xee,
++	DBG_BLOCK_ID_LDS10                               = 0xef,
++	DBG_BLOCK_ID_LDS11                               = 0xf0,
++	DBG_BLOCK_ID_LDS12                               = 0xf1,
++	DBG_BLOCK_ID_LDS13                               = 0xf2,
++	DBG_BLOCK_ID_LDS14                               = 0xf3,
++	DBG_BLOCK_ID_LDS15                               = 0xf4,
++	DBG_BLOCK_ID_LDS16                               = 0xf5,
++	DBG_BLOCK_ID_LDS17                               = 0xf6,
++	DBG_BLOCK_ID_LDS18                               = 0xf7,
++	DBG_BLOCK_ID_LDS19                               = 0xf8,
++	DBG_BLOCK_ID_LDS1A                               = 0xf9,
++	DBG_BLOCK_ID_LDS1B                               = 0xfa,
++	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
++	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
++	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
++	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
++} DebugBlockId;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
++	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
++	DBG_BLOCK_ID_PA_BY2                              = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
++	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
++	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
++	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
++	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
++	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
++	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
++	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
++	DBG_BLOCK_ID_CB_BY2                              = 0x24,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
++	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
++	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
++	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
++	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
++	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
++	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
++	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
++	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
++	DBG_BLOCK_ID_TA_BY2                              = 0x48,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
++	DBG_BLOCK_ID_TD_BY2                              = 0x58,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
++	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
++	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
++	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
++	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
++	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
++	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
++	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
++	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
++	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
++	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
++	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
++	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
++	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
++	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
++	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
++	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
++	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
++	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
++	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
++	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
++	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
++	DBG_BLOCK_ID_CB_BY4                              = 0x12,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
++	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
++	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
++	DBG_BLOCK_ID_DB_BY4                              = 0x16,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
++	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
++	DBG_BLOCK_ID_TA_BY4                              = 0x24,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
++	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
++	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
++	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
++	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
++	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
++	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
++	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
++	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
++	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
++	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
++	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
++	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
++	DBG_BLOCK_ID_CB_BY8                              = 0x9,
++	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
++	DBG_BLOCK_ID_DB_BY8                              = 0xb,
++	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
++	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
++	DBG_BLOCK_ID_TA_BY8                              = 0x12,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
++	DBG_BLOCK_ID_TD_BY8                              = 0x16,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
++	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
++	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
++	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
++	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
++	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
++	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
++	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
++	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
++	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
++	DBG_BLOCK_ID_TA_BY16                             = 0x9,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
++	DBG_BLOCK_ID_TD_BY16                             = 0xb,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
++	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
++	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
++} DebugBlockId_BY16;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* BIF_5_1_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
+new file mode 100644
+index 0000000..ee1da0c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
+@@ -0,0 +1,33080 @@
++/*
++ * BIF_5_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef BIF_5_1_SH_MASK_H
++#define BIF_5_1_SH_MASK_H
++
++#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
++#define MM_INDEX__MM_OFFSET__SHIFT 0x0
++#define MM_INDEX__MM_APER_MASK 0x80000000
++#define MM_INDEX__MM_APER__SHIFT 0x1f
++#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
++#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
++#define MM_DATA__MM_DATA_MASK 0xffffffff
++#define MM_DATA__MM_DATA__SHIFT 0x0
++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
++#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
++#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
++#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
++#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
++#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
++#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
++#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
++#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
++#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
++#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
++#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
++#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
++#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
++#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
++#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
++#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
++#define BUS_CNTL__SET_MC_TC_MASK 0xe000
++#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
++#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
++#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
++#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
++#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
++#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
++#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
++#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
++#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
++#define CONFIG_CNTL__VGA_DIS_MASK 0x2
++#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
++#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
++#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
++#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
++#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
++#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
++#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
++#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
++#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
++#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
++#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
++#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
++#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
++#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
++#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
++#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
++#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
++#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
++#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
++#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
++#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
++#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
++#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
++#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
++#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
++#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
++#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
++#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
++#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
++#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
++#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
++#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
++#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
++#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
++#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
++#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
++#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
++#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
++#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
++#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
++#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
++#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
++#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
++#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
++#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
++#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
++#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
++#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
++#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
++#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
++#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
++#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
++#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
++#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
++#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
++#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
++#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
++#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
++#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000
++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000
++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
++#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
++#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
++#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
++#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10
++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
++#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
++#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
++#define BIF_FB_EN__FB_READ_EN_MASK 0x1
++#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
++#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
++#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
++#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
++#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
++#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
++#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
++#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
++#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
++#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
++#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
++#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
++#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
++#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
++#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
++#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
++#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
++#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
++#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
++#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
++#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
++#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
++#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
++#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
++#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
++#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
++#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
++#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
++#define HOST_BUSNUM__HOST_ID_MASK 0xffff
++#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
++#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
++#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
++#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
++#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
++#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e
++#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1
++#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
++#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
++#define BACO_CNTL__BACO_EN_MASK 0x1
++#define BACO_CNTL__BACO_EN__SHIFT 0x0
++#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
++#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
++#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
++#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
++#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
++#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
++#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
++#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
++#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
++#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
++#define BACO_CNTL__BACO_MODE_MASK 0x40
++#define BACO_CNTL__BACO_MODE__SHIFT 0x6
++#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
++#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
++#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
++#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
++#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
++#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
++#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
++#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
++#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
++#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
++#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
++#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
++#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
++#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
++#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
++#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1
++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000
++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000
++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
++#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc
++#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
++#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc
++#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
++#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
++#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
++#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000
++#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf
++#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
++#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
++#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000
++#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11
++#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000
++#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12
++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
++#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
++#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
++#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
++#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
++#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
++#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
++#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
++#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000
++#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc
++#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000
++#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
++#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000
++#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc
++#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000
++#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
++#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT 0x2
++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
++#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1
++#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e
++#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
++#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000
++#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define BIF_RB_BASE__ADDR_MASK 0xffffffff
++#define BIF_RB_BASE__ADDR__SHIFT 0x0
++#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc
++#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
++#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1
++#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
++#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc
++#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
++#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
++#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define DEVICE_ID__DEVICE_ID_MASK 0xffff
++#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
++#define COMMAND__IO_ACCESS_EN_MASK 0x1
++#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define COMMAND__BUS_MASTER_EN_MASK 0x4
++#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define COMMAND__AD_STEPPING_MASK 0x80
++#define COMMAND__AD_STEPPING__SHIFT 0x7
++#define COMMAND__SERR_EN_MASK 0x100
++#define COMMAND__SERR_EN__SHIFT 0x8
++#define COMMAND__FAST_B2B_EN_MASK 0x200
++#define COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define COMMAND__INT_DIS_MASK 0x400
++#define COMMAND__INT_DIS__SHIFT 0xa
++#define STATUS__INT_STATUS_MASK 0x8
++#define STATUS__INT_STATUS__SHIFT 0x3
++#define STATUS__CAP_LIST_MASK 0x10
++#define STATUS__CAP_LIST__SHIFT 0x4
++#define STATUS__PCI_66_EN_MASK 0x20
++#define STATUS__PCI_66_EN__SHIFT 0x5
++#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
++#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
++#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
++#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
++#define STATUS__DEVSEL_TIMING_MASK 0x600
++#define STATUS__DEVSEL_TIMING__SHIFT 0x9
++#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
++#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
++#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
++#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
++#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
++#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
++#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
++#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
++#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
++#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
++#define REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
++#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
++#define SUB_CLASS__SUB_CLASS_MASK 0xff
++#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
++#define BASE_CLASS__BASE_CLASS_MASK 0xff
++#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
++#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define LATENCY__LATENCY_TIMER_MASK 0xff
++#define LATENCY__LATENCY_TIMER__SHIFT 0x0
++#define HEADER__HEADER_TYPE_MASK 0x7f
++#define HEADER__HEADER_TYPE__SHIFT 0x0
++#define HEADER__DEVICE_TYPE_MASK 0x80
++#define HEADER__DEVICE_TYPE__SHIFT 0x7
++#define BIST__BIST_COMP_MASK 0xf
++#define BIST__BIST_COMP__SHIFT 0x0
++#define BIST__BIST_STRT_MASK 0x40
++#define BIST__BIST_STRT__SHIFT 0x6
++#define BIST__BIST_CAP_MASK 0x80
++#define BIST__BIST_CAP__SHIFT 0x7
++#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
++#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
++#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
++#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
++#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
++#define CAP_PTR__CAP_PTR_MASK 0xff
++#define CAP_PTR__CAP_PTR__SHIFT 0x0
++#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
++#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
++#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
++#define MIN_GRANT__MIN_GNT_MASK 0xff
++#define MIN_GRANT__MIN_GNT__SHIFT 0x0
++#define MAX_LATENCY__MAX_LAT_MASK 0xff
++#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
++#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
++#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
++#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
++#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
++#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
++#define PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define PMI_CAP__VERSION_MASK 0x7
++#define PMI_CAP__VERSION__SHIFT 0x0
++#define PMI_CAP__PME_CLOCK_MASK 0x8
++#define PMI_CAP__PME_CLOCK__SHIFT 0x3
++#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
++#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
++#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
++#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
++#define PMI_CAP__D1_SUPPORT_MASK 0x200
++#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
++#define PMI_CAP__D2_SUPPORT_MASK 0x400
++#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
++#define PMI_CAP__PME_SUPPORT_MASK 0xf800
++#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
++#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define PCIE_CAP__VERSION_MASK 0xf
++#define PCIE_CAP__VERSION__SHIFT 0x0
++#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
++#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
++#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
++#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
++#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
++#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
++#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
++#define DEVICE_STATUS__CORR_ERR_MASK 0x1
++#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
++#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
++#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
++#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
++#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
++#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
++#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
++#define DEVICE_STATUS__AUX_PWR_MASK 0x10
++#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
++#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
++#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
++#define LINK_CAP__LINK_SPEED_MASK 0xf
++#define LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define LINK_CNTL__PM_CONTROL_MASK 0x3
++#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define LINK_CNTL__LINK_DIS_MASK 0x10
++#define LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
++#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
++#define LINK_STATUS__LINK_TRAINING_MASK 0x800
++#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
++#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
++#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
++#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
++#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define DEVICE_STATUS2__RESERVED_MASK 0xffff
++#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
++#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define LINK_CAP2__RESERVED__SHIFT 0x9
++#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
++#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
++#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
++#define MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
++#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
++#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
++#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
++#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
++#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
++#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
++#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
++#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
++#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
++#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
++#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
++#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
++#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
++#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
++#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
++#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
++#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
++#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
++#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
++#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
++#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
++#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
++#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
++#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
++#define PCIE_ATS_CNTL__STU_MASK 0x1f
++#define PCIE_ATS_CNTL__STU__SHIFT 0x0
++#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
++#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
++#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
++#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
++#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
++#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
++#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
++#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
++#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
++#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
++#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
++#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
++#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
++#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
++#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
++#define MM_INDEX_IND__MM_OFFSET_MASK 0x7fffffff
++#define MM_INDEX_IND__MM_OFFSET__SHIFT 0x0
++#define MM_INDEX_IND__MM_APER_MASK 0x80000000
++#define MM_INDEX_IND__MM_APER__SHIFT 0x1f
++#define MM_INDEX_HI_IND__MM_OFFSET_HI_MASK 0xffffffff
++#define MM_INDEX_HI_IND__MM_OFFSET_HI__SHIFT 0x0
++#define MM_DATA_IND__MM_DATA_MASK 0xffffffff
++#define MM_DATA_IND__MM_DATA__SHIFT 0x0
++#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK 0x2
++#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS__SHIFT 0x1
++#define BUS_CNTL_IND__BIOS_ROM_WRT_EN_MASK 0x1
++#define BUS_CNTL_IND__BIOS_ROM_WRT_EN__SHIFT 0x0
++#define BUS_CNTL_IND__BIOS_ROM_DIS_MASK 0x2
++#define BUS_CNTL_IND__BIOS_ROM_DIS__SHIFT 0x1
++#define BUS_CNTL_IND__PMI_IO_DIS_MASK 0x4
++#define BUS_CNTL_IND__PMI_IO_DIS__SHIFT 0x2
++#define BUS_CNTL_IND__PMI_MEM_DIS_MASK 0x8
++#define BUS_CNTL_IND__PMI_MEM_DIS__SHIFT 0x3
++#define BUS_CNTL_IND__PMI_BM_DIS_MASK 0x10
++#define BUS_CNTL_IND__PMI_BM_DIS__SHIFT 0x4
++#define BUS_CNTL_IND__PMI_INT_DIS_MASK 0x20
++#define BUS_CNTL_IND__PMI_INT_DIS__SHIFT 0x5
++#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS_MASK 0x40
++#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS__SHIFT 0x6
++#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS_MASK 0x80
++#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
++#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
++#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
++#define BUS_CNTL_IND__SET_AZ_TC_MASK 0x1c00
++#define BUS_CNTL_IND__SET_AZ_TC__SHIFT 0xa
++#define BUS_CNTL_IND__SET_MC_TC_MASK 0xe000
++#define BUS_CNTL_IND__SET_MC_TC__SHIFT 0xd
++#define BUS_CNTL_IND__ZERO_BE_WR_EN_MASK 0x10000
++#define BUS_CNTL_IND__ZERO_BE_WR_EN__SHIFT 0x10
++#define BUS_CNTL_IND__ZERO_BE_RD_EN_MASK 0x20000
++#define BUS_CNTL_IND__ZERO_BE_RD_EN__SHIFT 0x11
++#define BUS_CNTL_IND__RD_STALL_IO_WR_MASK 0x40000
++#define BUS_CNTL_IND__RD_STALL_IO_WR__SHIFT 0x12
++#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN_MASK 0x1
++#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN__SHIFT 0x0
++#define CONFIG_CNTL_IND__VGA_DIS_MASK 0x2
++#define CONFIG_CNTL_IND__VGA_DIS__SHIFT 0x1
++#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B_MASK 0x4
++#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B__SHIFT 0x2
++#define CONFIG_CNTL_IND__GRPH_ADRSEL_MASK 0x18
++#define CONFIG_CNTL_IND__GRPH_ADRSEL__SHIFT 0x3
++#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE_MASK 0xffffffff
++#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE__SHIFT 0x0
++#define CONFIG_F0_BASE_IND__F0_BASE_MASK 0xffffffff
++#define CONFIG_F0_BASE_IND__F0_BASE__SHIFT 0x0
++#define CONFIG_APER_SIZE_IND__APER_SIZE_MASK 0xffffffff
++#define CONFIG_APER_SIZE_IND__APER_SIZE__SHIFT 0x0
++#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE_MASK 0xfffff
++#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE__SHIFT 0x0
++#define BIF_SCRATCH0_IND__BIF_SCRATCH0_MASK 0xffffffff
++#define BIF_SCRATCH0_IND__BIF_SCRATCH0__SHIFT 0x0
++#define BIF_SCRATCH1_IND__BIF_SCRATCH1_MASK 0xffffffff
++#define BIF_SCRATCH1_IND__BIF_SCRATCH1__SHIFT 0x0
++#define BX_RESET_EN_IND__COR_RESET_EN_MASK 0x1
++#define BX_RESET_EN_IND__COR_RESET_EN__SHIFT 0x0
++#define BX_RESET_EN_IND__REG_RESET_EN_MASK 0x2
++#define BX_RESET_EN_IND__REG_RESET_EN__SHIFT 0x1
++#define BX_RESET_EN_IND__STY_RESET_EN_MASK 0x4
++#define BX_RESET_EN_IND__STY_RESET_EN__SHIFT 0x2
++#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL_MASK 0x7
++#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL__SHIFT 0x0
++#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN_MASK 0x8
++#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN__SHIFT 0x3
++#define HW_DEBUG_IND__HW_00_DEBUG_MASK 0x1
++#define HW_DEBUG_IND__HW_00_DEBUG__SHIFT 0x0
++#define HW_DEBUG_IND__HW_01_DEBUG_MASK 0x2
++#define HW_DEBUG_IND__HW_01_DEBUG__SHIFT 0x1
++#define HW_DEBUG_IND__HW_02_DEBUG_MASK 0x4
++#define HW_DEBUG_IND__HW_02_DEBUG__SHIFT 0x2
++#define HW_DEBUG_IND__HW_03_DEBUG_MASK 0x8
++#define HW_DEBUG_IND__HW_03_DEBUG__SHIFT 0x3
++#define HW_DEBUG_IND__HW_04_DEBUG_MASK 0x10
++#define HW_DEBUG_IND__HW_04_DEBUG__SHIFT 0x4
++#define HW_DEBUG_IND__HW_05_DEBUG_MASK 0x20
++#define HW_DEBUG_IND__HW_05_DEBUG__SHIFT 0x5
++#define HW_DEBUG_IND__HW_06_DEBUG_MASK 0x40
++#define HW_DEBUG_IND__HW_06_DEBUG__SHIFT 0x6
++#define HW_DEBUG_IND__HW_07_DEBUG_MASK 0x80
++#define HW_DEBUG_IND__HW_07_DEBUG__SHIFT 0x7
++#define HW_DEBUG_IND__HW_08_DEBUG_MASK 0x100
++#define HW_DEBUG_IND__HW_08_DEBUG__SHIFT 0x8
++#define HW_DEBUG_IND__HW_09_DEBUG_MASK 0x200
++#define HW_DEBUG_IND__HW_09_DEBUG__SHIFT 0x9
++#define HW_DEBUG_IND__HW_10_DEBUG_MASK 0x400
++#define HW_DEBUG_IND__HW_10_DEBUG__SHIFT 0xa
++#define HW_DEBUG_IND__HW_11_DEBUG_MASK 0x800
++#define HW_DEBUG_IND__HW_11_DEBUG__SHIFT 0xb
++#define HW_DEBUG_IND__HW_12_DEBUG_MASK 0x1000
++#define HW_DEBUG_IND__HW_12_DEBUG__SHIFT 0xc
++#define HW_DEBUG_IND__HW_13_DEBUG_MASK 0x2000
++#define HW_DEBUG_IND__HW_13_DEBUG__SHIFT 0xd
++#define HW_DEBUG_IND__HW_14_DEBUG_MASK 0x4000
++#define HW_DEBUG_IND__HW_14_DEBUG__SHIFT 0xe
++#define HW_DEBUG_IND__HW_15_DEBUG_MASK 0x8000
++#define HW_DEBUG_IND__HW_15_DEBUG__SHIFT 0xf
++#define HW_DEBUG_IND__HW_16_DEBUG_MASK 0x10000
++#define HW_DEBUG_IND__HW_16_DEBUG__SHIFT 0x10
++#define HW_DEBUG_IND__HW_17_DEBUG_MASK 0x20000
++#define HW_DEBUG_IND__HW_17_DEBUG__SHIFT 0x11
++#define HW_DEBUG_IND__HW_18_DEBUG_MASK 0x40000
++#define HW_DEBUG_IND__HW_18_DEBUG__SHIFT 0x12
++#define HW_DEBUG_IND__HW_19_DEBUG_MASK 0x80000
++#define HW_DEBUG_IND__HW_19_DEBUG__SHIFT 0x13
++#define HW_DEBUG_IND__HW_20_DEBUG_MASK 0x100000
++#define HW_DEBUG_IND__HW_20_DEBUG__SHIFT 0x14
++#define HW_DEBUG_IND__HW_21_DEBUG_MASK 0x200000
++#define HW_DEBUG_IND__HW_21_DEBUG__SHIFT 0x15
++#define HW_DEBUG_IND__HW_22_DEBUG_MASK 0x400000
++#define HW_DEBUG_IND__HW_22_DEBUG__SHIFT 0x16
++#define HW_DEBUG_IND__HW_23_DEBUG_MASK 0x800000
++#define HW_DEBUG_IND__HW_23_DEBUG__SHIFT 0x17
++#define HW_DEBUG_IND__HW_24_DEBUG_MASK 0x1000000
++#define HW_DEBUG_IND__HW_24_DEBUG__SHIFT 0x18
++#define HW_DEBUG_IND__HW_25_DEBUG_MASK 0x2000000
++#define HW_DEBUG_IND__HW_25_DEBUG__SHIFT 0x19
++#define HW_DEBUG_IND__HW_26_DEBUG_MASK 0x4000000
++#define HW_DEBUG_IND__HW_26_DEBUG__SHIFT 0x1a
++#define HW_DEBUG_IND__HW_27_DEBUG_MASK 0x8000000
++#define HW_DEBUG_IND__HW_27_DEBUG__SHIFT 0x1b
++#define HW_DEBUG_IND__HW_28_DEBUG_MASK 0x10000000
++#define HW_DEBUG_IND__HW_28_DEBUG__SHIFT 0x1c
++#define HW_DEBUG_IND__HW_29_DEBUG_MASK 0x20000000
++#define HW_DEBUG_IND__HW_29_DEBUG__SHIFT 0x1d
++#define HW_DEBUG_IND__HW_30_DEBUG_MASK 0x40000000
++#define HW_DEBUG_IND__HW_30_DEBUG__SHIFT 0x1e
++#define HW_DEBUG_IND__HW_31_DEBUG_MASK 0x80000000
++#define HW_DEBUG_IND__HW_31_DEBUG__SHIFT 0x1f
++#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT_MASK 0x7f
++#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT__SHIFT 0x0
++#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
++#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT_MASK 0x1f
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT_MASK 0x1e0
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT__SHIFT 0x5
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT_MASK 0x7c00
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT__SHIFT 0xa
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT_MASK 0x8000
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT__SHIFT 0xf
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT_MASK 0x100000
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT__SHIFT 0x14
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
++#define BX_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x1
++#define BX_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x0
++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE_MASK 0x1
++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK 0x2
++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN__SHIFT 0x1
++#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN_MASK 0x8
++#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN__SHIFT 0x3
++#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR_MASK 0xf0
++#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR__SHIFT 0x4
++#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN_MASK 0x100
++#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN__SHIFT 0x8
++#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN_MASK 0x1e00
++#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN__SHIFT 0x9
++#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
++#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
++#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
++#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
++#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR_MASK 0xffffffff
++#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR__SHIFT 0x0
++#define BIF_DEBUG_CNTL_IND__DEBUG_EN_MASK 0x1
++#define BIF_DEBUG_CNTL_IND__DEBUG_EN__SHIFT 0x0
++#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK 0x2
++#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN__SHIFT 0x1
++#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN_MASK 0x4
++#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT 0x2
++#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL_MASK 0x8
++#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL__SHIFT 0x3
++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1_MASK 0x10
++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1__SHIFT 0x4
++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2_MASK 0x20
++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2__SHIFT 0x5
++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN_MASK 0x40
++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN__SHIFT 0x6
++#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP_MASK 0x80
++#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP__SHIFT 0x7
++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1_MASK 0x1f00
++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1__SHIFT 0x8
++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2_MASK 0x1f0000
++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2__SHIFT 0x10
++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP_MASK 0x1000000
++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP__SHIFT 0x18
++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1_MASK 0x3f
++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1__SHIFT 0x0
++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2_MASK 0x3f00
++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2__SHIFT 0x8
++#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT_MASK 0x1ffff
++#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT__SHIFT 0x0
++#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR_MASK 0x1
++#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR__SHIFT 0x0
++#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR_MASK 0x1
++#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A_MASK 0x1
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A__SHIFT 0x0
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL_MASK 0x2
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL__SHIFT 0x1
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE_MASK 0x4
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE__SHIFT 0x2
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE_MASK 0x18
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE__SHIFT 0x3
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0_MASK 0x20
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0__SHIFT 0x5
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1_MASK 0x40
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1__SHIFT 0x6
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2_MASK 0x80
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2__SHIFT 0x7
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3_MASK 0x100
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3__SHIFT 0x8
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN_MASK 0x200
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN__SHIFT 0x9
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE_MASK 0x400
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE__SHIFT 0xa
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN_MASK 0x800
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN__SHIFT 0xb
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN_MASK 0x1000
++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A_MASK 0x1
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A__SHIFT 0x0
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL_MASK 0x2
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL__SHIFT 0x1
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE_MASK 0x4
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE__SHIFT 0x2
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE_MASK 0x18
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE__SHIFT 0x3
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0_MASK 0x20
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0__SHIFT 0x5
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1_MASK 0x40
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1__SHIFT 0x6
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2_MASK 0x80
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2__SHIFT 0x7
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3_MASK 0x100
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3__SHIFT 0x8
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN_MASK 0x200
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN__SHIFT 0x9
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE_MASK 0x400
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE__SHIFT 0xa
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN_MASK 0x800
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN__SHIFT 0xb
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN_MASK 0x1000
++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A_MASK 0x1
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A__SHIFT 0x0
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL_MASK 0x2
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL__SHIFT 0x1
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE_MASK 0x4
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE__SHIFT 0x2
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE_MASK 0x18
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE__SHIFT 0x3
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0_MASK 0x20
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0__SHIFT 0x5
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1_MASK 0x40
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1__SHIFT 0x6
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2_MASK 0x80
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2__SHIFT 0x7
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3_MASK 0x100
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3__SHIFT 0x8
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN_MASK 0x200
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN__SHIFT 0x9
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE_MASK 0x400
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE__SHIFT 0xa
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN_MASK 0x800
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN__SHIFT 0xb
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN_MASK 0x1000
++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
++#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
++#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN_MASK 0x80000000
++#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN__SHIFT 0x1f
++#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
++#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS_MASK 0x1
++#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS__SHIFT 0x0
++#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK 0x2
++#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS_MASK 0x4
++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS_MASK 0x8
++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS__SHIFT 0x3
++#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
++#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
++#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
++#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
++#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
++#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
++#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
++#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
++#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
++#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
++#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
++#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
++#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS_MASK 0x1
++#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS__SHIFT 0x0
++#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK 0x2
++#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS__SHIFT 0x1
++#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN_MASK 0x4
++#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT 0x2
++#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
++#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
++#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN_MASK 0x10
++#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN__SHIFT 0x4
++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS_MASK 0x20
++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
++#define BIF_SLVARB_MODE_IND__SLVARB_MODE_MASK 0x3
++#define BIF_SLVARB_MODE_IND__SLVARB_MODE__SHIFT 0x0
++#define BIF_FB_EN_IND__FB_READ_EN_MASK 0x1
++#define BIF_FB_EN_IND__FB_READ_EN__SHIFT 0x0
++#define BIF_FB_EN_IND__FB_WRITE_EN_MASK 0x2
++#define BIF_FB_EN_IND__FB_WRITE_EN__SHIFT 0x1
++#define BIF_BUSNUM_CNTL1_IND__ID_MASK_MASK 0xff
++#define BIF_BUSNUM_CNTL1_IND__ID_MASK__SHIFT 0x0
++#define BIF_BUSNUM_LIST0_IND__ID0_MASK 0xff
++#define BIF_BUSNUM_LIST0_IND__ID0__SHIFT 0x0
++#define BIF_BUSNUM_LIST0_IND__ID1_MASK 0xff00
++#define BIF_BUSNUM_LIST0_IND__ID1__SHIFT 0x8
++#define BIF_BUSNUM_LIST0_IND__ID2_MASK 0xff0000
++#define BIF_BUSNUM_LIST0_IND__ID2__SHIFT 0x10
++#define BIF_BUSNUM_LIST0_IND__ID3_MASK 0xff000000
++#define BIF_BUSNUM_LIST0_IND__ID3__SHIFT 0x18
++#define BIF_BUSNUM_LIST1_IND__ID4_MASK 0xff
++#define BIF_BUSNUM_LIST1_IND__ID4__SHIFT 0x0
++#define BIF_BUSNUM_LIST1_IND__ID5_MASK 0xff00
++#define BIF_BUSNUM_LIST1_IND__ID5__SHIFT 0x8
++#define BIF_BUSNUM_LIST1_IND__ID6_MASK 0xff0000
++#define BIF_BUSNUM_LIST1_IND__ID6__SHIFT 0x10
++#define BIF_BUSNUM_LIST1_IND__ID7_MASK 0xff000000
++#define BIF_BUSNUM_LIST1_IND__ID7__SHIFT 0x18
++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL_MASK 0xff
++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL__SHIFT 0x0
++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN_MASK 0x100
++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN__SHIFT 0x8
++#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL_MASK 0x10000
++#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL__SHIFT 0x10
++#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
++#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
++#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT_MASK 0x3f
++#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT__SHIFT 0x0
++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN_MASK 0x1
++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN__SHIFT 0x0
++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK 0x2
++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0__SHIFT 0x1
++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1_MASK 0x4
++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT 0x2
++#define BIF_PERFMON_CNTL_IND__PERF_SEL0_MASK 0x1f00
++#define BIF_PERFMON_CNTL_IND__PERF_SEL0__SHIFT 0x8
++#define BIF_PERFMON_CNTL_IND__PERF_SEL1_MASK 0x3e000
++#define BIF_PERFMON_CNTL_IND__PERF_SEL1__SHIFT 0xd
++#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0
++#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff
++#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0
++#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL_MASK 0xe
++#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ_IND__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_REQ_IND__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_REQ_IND__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_REQ_IND__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_REQ_IND__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_REQ_IND__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_REQ_IND__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_REQ_IND__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_REQ_IND__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_REQ_IND__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_REQ_IND__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_REQ_IND__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_REQ_IND__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_REQ_IND__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_REQ_IND__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_REQ_IND__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_REQ_IND__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_REQ_IND__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_REQ_IND__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_REQ_IND__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_REQ_IND__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_REQ_IND__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_REQ_IND__SDMA1__SHIFT 0xb
++#define GPU_HDP_FLUSH_DONE_IND__CP0_MASK 0x1
++#define GPU_HDP_FLUSH_DONE_IND__CP0__SHIFT 0x0
++#define GPU_HDP_FLUSH_DONE_IND__CP1_MASK 0x2
++#define GPU_HDP_FLUSH_DONE_IND__CP1__SHIFT 0x1
++#define GPU_HDP_FLUSH_DONE_IND__CP2_MASK 0x4
++#define GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT 0x2
++#define GPU_HDP_FLUSH_DONE_IND__CP3_MASK 0x8
++#define GPU_HDP_FLUSH_DONE_IND__CP3__SHIFT 0x3
++#define GPU_HDP_FLUSH_DONE_IND__CP4_MASK 0x10
++#define GPU_HDP_FLUSH_DONE_IND__CP4__SHIFT 0x4
++#define GPU_HDP_FLUSH_DONE_IND__CP5_MASK 0x20
++#define GPU_HDP_FLUSH_DONE_IND__CP5__SHIFT 0x5
++#define GPU_HDP_FLUSH_DONE_IND__CP6_MASK 0x40
++#define GPU_HDP_FLUSH_DONE_IND__CP6__SHIFT 0x6
++#define GPU_HDP_FLUSH_DONE_IND__CP7_MASK 0x80
++#define GPU_HDP_FLUSH_DONE_IND__CP7__SHIFT 0x7
++#define GPU_HDP_FLUSH_DONE_IND__CP8_MASK 0x100
++#define GPU_HDP_FLUSH_DONE_IND__CP8__SHIFT 0x8
++#define GPU_HDP_FLUSH_DONE_IND__CP9_MASK 0x200
++#define GPU_HDP_FLUSH_DONE_IND__CP9__SHIFT 0x9
++#define GPU_HDP_FLUSH_DONE_IND__SDMA0_MASK 0x400
++#define GPU_HDP_FLUSH_DONE_IND__SDMA0__SHIFT 0xa
++#define GPU_HDP_FLUSH_DONE_IND__SDMA1_MASK 0x800
++#define GPU_HDP_FLUSH_DONE_IND__SDMA1__SHIFT 0xb
++#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR_MASK 0x1
++#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR__SHIFT 0x0
++#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR_MASK 0x2
++#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR__SHIFT 0x1
++#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR_MASK 0x4
++#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR__SHIFT 0x2
++#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR_MASK 0x8
++#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR__SHIFT 0x3
++#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR_MASK 0x10
++#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR__SHIFT 0x4
++#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR_MASK 0x20
++#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR__SHIFT 0x5
++#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR_MASK 0x80
++#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR__SHIFT 0x7
++#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR_MASK 0x100
++#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR__SHIFT 0x8
++#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR_MASK 0x200
++#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR__SHIFT 0x9
++#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN_MASK 0x1
++#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN__SHIFT 0x0
++#define HOST_BUSNUM_IND__HOST_ID_MASK 0xffff
++#define HOST_BUSNUM_IND__HOST_ID__SHIFT 0x0
++#define PEER_REG_RANGE0_IND__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE0_IND__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE0_IND__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE0_IND__END_ADDR__SHIFT 0x10
++#define PEER_REG_RANGE1_IND__START_ADDR_MASK 0xffff
++#define PEER_REG_RANGE1_IND__START_ADDR__SHIFT 0x0
++#define PEER_REG_RANGE1_IND__END_ADDR_MASK 0xffff0000
++#define PEER_REG_RANGE1_IND__END_ADDR__SHIFT 0x10
++#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI_MASK 0xfffff
++#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO_MASK 0xfffff
++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO__SHIFT 0x0
++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN_MASK 0x80000000
++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN__SHIFT 0x1f
++#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI_MASK 0xfffff
++#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO_MASK 0xfffff
++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO__SHIFT 0x0
++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN_MASK 0x80000000
++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN__SHIFT 0x1f
++#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI_MASK 0xfffff
++#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO_MASK 0xfffff
++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO__SHIFT 0x0
++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN_MASK 0x80000000
++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN__SHIFT 0x1f
++#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI_MASK 0xfffff
++#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO_MASK 0xfffff
++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO__SHIFT 0x0
++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN_MASK 0x80000000
++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN__SHIFT 0x1f
++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD_MASK 0x1e
++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD__SHIFT 0x1
++#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
++#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3__SHIFT 0x18
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4_MASK 0xff
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4__SHIFT 0x0
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5_MASK 0xff00
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5__SHIFT 0x8
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6_MASK 0xff0000
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6__SHIFT 0x10
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7_MASK 0xff000000
++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7__SHIFT 0x18
++#define BACO_CNTL_IND__BACO_EN_MASK 0x1
++#define BACO_CNTL_IND__BACO_EN__SHIFT 0x0
++#define BACO_CNTL_IND__BACO_BCLK_OFF_MASK 0x2
++#define BACO_CNTL_IND__BACO_BCLK_OFF__SHIFT 0x1
++#define BACO_CNTL_IND__BACO_ISO_DIS_MASK 0x4
++#define BACO_CNTL_IND__BACO_ISO_DIS__SHIFT 0x2
++#define BACO_CNTL_IND__BACO_POWER_OFF_MASK 0x8
++#define BACO_CNTL_IND__BACO_POWER_OFF__SHIFT 0x3
++#define BACO_CNTL_IND__BACO_RESET_EN_MASK 0x10
++#define BACO_CNTL_IND__BACO_RESET_EN__SHIFT 0x4
++#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN_MASK 0x20
++#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN__SHIFT 0x5
++#define BACO_CNTL_IND__BACO_MODE_MASK 0x40
++#define BACO_CNTL_IND__BACO_MODE__SHIFT 0x6
++#define BACO_CNTL_IND__BACO_ANA_ISO_DIS_MASK 0x80
++#define BACO_CNTL_IND__BACO_ANA_ISO_DIS__SHIFT 0x7
++#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE_MASK 0x100
++#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE__SHIFT 0x8
++#define BACO_CNTL_IND__PWRGOOD_BF_MASK 0x200
++#define BACO_CNTL_IND__PWRGOOD_BF__SHIFT 0x9
++#define BACO_CNTL_IND__PWRGOOD_GPIO_MASK 0x400
++#define BACO_CNTL_IND__PWRGOOD_GPIO__SHIFT 0xa
++#define BACO_CNTL_IND__PWRGOOD_MEM_MASK 0x800
++#define BACO_CNTL_IND__PWRGOOD_MEM__SHIFT 0xb
++#define BACO_CNTL_IND__PWRGOOD_DVO_MASK 0x1000
++#define BACO_CNTL_IND__PWRGOOD_DVO__SHIFT 0xc
++#define BACO_CNTL_IND__PWRGOOD_IDSC_MASK 0x2000
++#define BACO_CNTL_IND__PWRGOOD_IDSC__SHIFT 0xd
++#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM_MASK 0x10000
++#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM__SHIFT 0x10
++#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
++#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
++#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK_MASK 0x1
++#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
++#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK 0x2
++#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
++#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3_MASK 0x1
++#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3__SHIFT 0x0
++#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG_MASK 0x1
++#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
++#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG_MASK 0x1
++#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG__SHIFT 0x0
++#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS_MASK 0x1
++#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS__SHIFT 0x0
++#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK 0x2
++#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS__SHIFT 0x1
++#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
++#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
++#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF_MASK 0x1
++#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
++#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
++#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN_MASK 0x80000000
++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
++#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN_MASK 0x80000000
++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
++#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
++#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
++#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX_MASK 0x7fffc
++#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT 0x2
++#define BIF_SMU_DATA_IND__BIF_SMU_DATA_MASK 0x7fffc
++#define BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT 0x2
++#define IMPCTL_RESET_IND__IMP_SW_RESET_MASK 0x1
++#define IMPCTL_RESET_IND__IMP_SW_RESET__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR_MASK 0x1
++#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR__SHIFT 0x0
++#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK 0x2
++#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR__SHIFT 0x1
++#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR_MASK 0x4
++#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT 0x2
++#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR_MASK 0x8
++#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR__SHIFT 0x3
++#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR_MASK 0x10
++#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR__SHIFT 0x4
++#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR_MASK 0x20
++#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR__SHIFT 0x5
++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND_MASK 0x40
++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND__SHIFT 0x6
++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND_MASK 0x80
++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND__SHIFT 0x7
++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR_MASK 0x100
++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR__SHIFT 0x8
++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR_MASK 0x200
++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR__SHIFT 0x9
++#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR_MASK 0x400
++#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR__SHIFT 0xa
++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2_MASK 0x800
++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2__SHIFT 0xb
++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR_MASK 0x1000
++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR__SHIFT 0xc
++#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL_MASK 0x2000
++#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL__SHIFT 0xd
++#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL_MASK 0x4000
++#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL__SHIFT 0xe
++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND_MASK 0x8000
++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND__SHIFT 0xf
++#define GARLIC_FLUSH_CNTL_IND__DISPLAY_MASK 0x10000
++#define GARLIC_FLUSH_CNTL_IND__DISPLAY__SHIFT 0x10
++#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR_MASK 0x20000
++#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR__SHIFT 0x11
++#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR_MASK 0x40000
++#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR__SHIFT 0x12
++#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE_MASK 0x40000000
++#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE__SHIFT 0x1e
++#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL_MASK 0x80000000
++#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL__SHIFT 0x1f
++#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ_MASK 0x1
++#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ_IND__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_REQ_IND__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_REQ_IND__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_REQ_IND__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_REQ_IND__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_REQ_IND__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_REQ_IND__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_REQ_IND__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_REQ_IND__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_REQ_IND__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_REQ_IND__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_REQ_IND__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_REQ_IND__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_REQ_IND__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_REQ_IND__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_REQ_IND__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_REQ_IND__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_REQ_IND__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2_MASK 0x1000
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2__SHIFT 0xc
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3_MASK 0x2000
++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3__SHIFT 0xd
++#define GPU_GARLIC_FLUSH_DONE_IND__CP0_MASK 0x1
++#define GPU_GARLIC_FLUSH_DONE_IND__CP0__SHIFT 0x0
++#define GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK 0x2
++#define GPU_GARLIC_FLUSH_DONE_IND__CP1__SHIFT 0x1
++#define GPU_GARLIC_FLUSH_DONE_IND__CP2_MASK 0x4
++#define GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT 0x2
++#define GPU_GARLIC_FLUSH_DONE_IND__CP3_MASK 0x8
++#define GPU_GARLIC_FLUSH_DONE_IND__CP3__SHIFT 0x3
++#define GPU_GARLIC_FLUSH_DONE_IND__CP4_MASK 0x10
++#define GPU_GARLIC_FLUSH_DONE_IND__CP4__SHIFT 0x4
++#define GPU_GARLIC_FLUSH_DONE_IND__CP5_MASK 0x20
++#define GPU_GARLIC_FLUSH_DONE_IND__CP5__SHIFT 0x5
++#define GPU_GARLIC_FLUSH_DONE_IND__CP6_MASK 0x40
++#define GPU_GARLIC_FLUSH_DONE_IND__CP6__SHIFT 0x6
++#define GPU_GARLIC_FLUSH_DONE_IND__CP7_MASK 0x80
++#define GPU_GARLIC_FLUSH_DONE_IND__CP7__SHIFT 0x7
++#define GPU_GARLIC_FLUSH_DONE_IND__CP8_MASK 0x100
++#define GPU_GARLIC_FLUSH_DONE_IND__CP8__SHIFT 0x8
++#define GPU_GARLIC_FLUSH_DONE_IND__CP9_MASK 0x200
++#define GPU_GARLIC_FLUSH_DONE_IND__CP9__SHIFT 0x9
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0_MASK 0x400
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0__SHIFT 0xa
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1_MASK 0x800
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1__SHIFT 0xb
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2_MASK 0x1000
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2__SHIFT 0xc
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3_MASK 0x2000
++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3__SHIFT 0xd
++#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT 0x2
++#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS_MASK 0x7fffc
++#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT 0x2
++#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc
++#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
++#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc
++#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
++#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0_MASK 0xffffffff
++#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0__SHIFT 0x0
++#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1_MASK 0xffffffff
++#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1__SHIFT 0x0
++#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2_MASK 0xffffffff
++#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2__SHIFT 0x0
++#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3_MASK 0xffffffff
++#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3__SHIFT 0x0
++#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4_MASK 0xffffffff
++#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4__SHIFT 0x0
++#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5_MASK 0xffffffff
++#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5__SHIFT 0x0
++#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6_MASK 0xffffffff
++#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6__SHIFT 0x0
++#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7_MASK 0xffffffff
++#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7__SHIFT 0x0
++#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8_MASK 0xffffffff
++#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8__SHIFT 0x0
++#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9_MASK 0xffffffff
++#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9__SHIFT 0x0
++#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10_MASK 0xffffffff
++#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10__SHIFT 0x0
++#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11_MASK 0xffffffff
++#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11__SHIFT 0x0
++#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12_MASK 0xffffffff
++#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12__SHIFT 0x0
++#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13_MASK 0xffffffff
++#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13__SHIFT 0x0
++#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14_MASK 0xffffffff
++#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14__SHIFT 0x0
++#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15_MASK 0xffffffff
++#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15__SHIFT 0x0
++#define BIF_RB_CNTL_IND__RB_ENABLE_MASK 0x1
++#define BIF_RB_CNTL_IND__RB_ENABLE__SHIFT 0x0
++#define BIF_RB_CNTL_IND__RB_SIZE_MASK 0x3e
++#define BIF_RB_CNTL_IND__RB_SIZE__SHIFT 0x1
++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER_MASK 0x3e00
++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER__SHIFT 0x9
++#define BIF_RB_CNTL_IND__BIF_RB_TRAN_MASK 0x20000
++#define BIF_RB_CNTL_IND__BIF_RB_TRAN__SHIFT 0x11
++#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define BIF_RB_BASE_IND__ADDR_MASK 0xffffffff
++#define BIF_RB_BASE_IND__ADDR__SHIFT 0x0
++#define BIF_RB_RPTR_IND__OFFSET_MASK 0x3fffc
++#define BIF_RB_RPTR_IND__OFFSET__SHIFT 0x2
++#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW_MASK 0x1
++#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW__SHIFT 0x0
++#define BIF_RB_WPTR_IND__OFFSET_MASK 0x3fffc
++#define BIF_RB_WPTR_IND__OFFSET__SHIFT 0x2
++#define BIF_RB_WPTR_ADDR_HI_IND__ADDR_MASK 0xff
++#define BIF_RB_WPTR_ADDR_HI_IND__ADDR__SHIFT 0x0
++#define BIF_RB_WPTR_ADDR_LO_IND__ADDR_MASK 0xfffffffc
++#define BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT 0x2
++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff
++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0
++#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff
++#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0
++#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
++#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
++#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
++#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
++#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
++#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
++#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
++#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
++#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
++#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
++#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
++#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
++#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
++#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
++#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
++#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
++#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
++#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
++#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
++#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
++#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000
++#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14
++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
++#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
++#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
++#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
++#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
++#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
++#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
++#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
++#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
++#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
++#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
++#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
++#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
++#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
++#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
++#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
++#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
++#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
++#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
++#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
++#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
++#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
++#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
++#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
++#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
++#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
++#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
++#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
++#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
++#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
++#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
++#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
++#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
++#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
++#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
++#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
++#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
++#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
++#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
++#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
++#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
++#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
++#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
++#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
++#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
++#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
++#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
++#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
++#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
++#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
++#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
++#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
++#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
++#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
++#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
++#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
++#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
++#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
++#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
++#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
++#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
++#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
++#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
++#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
++#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
++#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
++#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
++#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
++#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
++#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
++#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
++#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
++#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
++#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
++#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
++#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
++#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
++#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
++#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
++#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
++#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
++#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
++#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
++#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
++#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
++#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
++#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
++#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
++#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1
++#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0
++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
++#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
++#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1
++#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0
++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
++#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
++#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
++#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
++#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff
++#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0
++#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf
++#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0
++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
++#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
++#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
++#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
++#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
++#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
++#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
++#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
++#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
++#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
++#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
++#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6
++#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8
++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3
++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10
++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4
++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60
++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5
++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80
++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7
++#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
++#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
++#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
++#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
++#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
++#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
++#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
++#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst_MASK 0x1
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst__SHIFT 0x0
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK 0x2
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst__SHIFT 0x1
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst_MASK 0x4
++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT 0x2
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst_MASK 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst__SHIFT 0x0
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK 0x2
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst__SHIFT 0x1
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4
++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
++#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd_MASK 0x1
++#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd__SHIFT 0x0
++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK 0x2
++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd__SHIFT 0x1
++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4
++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
++#define BIF_PWDN_STATUS__FBU_REG_pw_status_MASK 0x1
++#define BIF_PWDN_STATUS__FBU_REG_pw_status__SHIFT 0x0
++#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK 0x2
++#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status__SHIFT 0x1
++#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4
++#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x1
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe
++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x10
++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe0
++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
++#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK_MASK 0x1
++#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
++#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN_MASK 0x1
++#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN__SHIFT 0x0
++#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE_MASK 0x1
++#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE__SHIFT 0x0
++#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE_MASK 0x6
++#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE__SHIFT 0x1
++#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN_MASK 0x1
++#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN__SHIFT 0x0
++#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER_MASK 0x1ffffe
++#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER__SHIFT 0x1
++#define NEW_REFCLKB_TIMER_IND__REFCLK_ON_MASK 0x200000
++#define NEW_REFCLKB_TIMER_IND__REFCLK_ON__SHIFT 0x15
++#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER_MASK 0x3ff
++#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER__SHIFT 0x0
++#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN_MASK 0x400
++#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN__SHIFT 0xa
++#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER_MASK 0x3ff
++#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER__SHIFT 0x0
++#define BIF_RESET_EN_IND__SOFT_RST_MODE_MASK 0x2
++#define BIF_RESET_EN_IND__SOFT_RST_MODE__SHIFT 0x1
++#define BIF_RESET_EN_IND__PHY_RESET_EN_MASK 0x4
++#define BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT 0x2
++#define BIF_RESET_EN_IND__COR_RESET_EN_MASK 0x8
++#define BIF_RESET_EN_IND__COR_RESET_EN__SHIFT 0x3
++#define BIF_RESET_EN_IND__REG_RESET_EN_MASK 0x10
++#define BIF_RESET_EN_IND__REG_RESET_EN__SHIFT 0x4
++#define BIF_RESET_EN_IND__STY_RESET_EN_MASK 0x20
++#define BIF_RESET_EN_IND__STY_RESET_EN__SHIFT 0x5
++#define BIF_RESET_EN_IND__CFG_RESET_EN_MASK 0x40
++#define BIF_RESET_EN_IND__CFG_RESET_EN__SHIFT 0x6
++#define BIF_RESET_EN_IND__DRV_RESET_EN_MASK 0x80
++#define BIF_RESET_EN_IND__DRV_RESET_EN__SHIFT 0x7
++#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN_MASK 0x100
++#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN__SHIFT 0x8
++#define BIF_RESET_EN_IND__HOT_RESET_EN_MASK 0x200
++#define BIF_RESET_EN_IND__HOT_RESET_EN__SHIFT 0x9
++#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN_MASK 0x400
++#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN__SHIFT 0xa
++#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN_MASK 0x800
++#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN__SHIFT 0xb
++#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
++#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
++#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL_MASK 0xc0000
++#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL__SHIFT 0x12
++#define BIF_RESET_EN_IND__PIF_RSTB_EN_MASK 0x100000
++#define BIF_RESET_EN_IND__PIF_RSTB_EN__SHIFT 0x14
++#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN_MASK 0x200000
++#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
++#define BIF_RESET_EN_IND__BIF_COR_RESET_EN_MASK 0x400000
++#define BIF_RESET_EN_IND__BIF_COR_RESET_EN__SHIFT 0x16
++#define BIF_RESET_EN_IND__FUNC0_FLR_EN_MASK 0x800000
++#define BIF_RESET_EN_IND__FUNC0_FLR_EN__SHIFT 0x17
++#define BIF_RESET_EN_IND__FUNC1_FLR_EN_MASK 0x1000000
++#define BIF_RESET_EN_IND__FUNC1_FLR_EN__SHIFT 0x18
++#define BIF_RESET_EN_IND__FUNC2_FLR_EN_MASK 0x2000000
++#define BIF_RESET_EN_IND__FUNC2_FLR_EN__SHIFT 0x19
++#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
++#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
++#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
++#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
++#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
++#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER_MASK 0x7
++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER__SHIFT 0x0
++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER_MASK 0x38
++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER__SHIFT 0x3
++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER_MASK 0x3c0
++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER__SHIFT 0x6
++#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL_MASK 0x1
++#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL__SHIFT 0x0
++#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL_MASK 0x6
++#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL__SHIFT 0x1
++#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS_MASK 0x10
++#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS__SHIFT 0x4
++#define BIF_RESET_CNTL_IND__STRAP_EN_MASK 0x1
++#define BIF_RESET_CNTL_IND__STRAP_EN__SHIFT 0x0
++#define BIF_RESET_CNTL_IND__RST_DONE_MASK 0x2
++#define BIF_RESET_CNTL_IND__RST_DONE__SHIFT 0x1
++#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x4
++#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x2
++#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID_MASK 0x8
++#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID__SHIFT 0x3
++#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST_MASK 0x100
++#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST__SHIFT 0x8
++#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
++#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN_MASK 0x1
++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN__SHIFT 0x0
++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER_MASK 0xffff0000
++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER__SHIFT 0x10
++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff
++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0
++#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff
++#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0
++#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1
++#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
++#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1
++#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0
++#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1
++#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0
++#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6
++#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1
++#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1
++#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0
++#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe
++#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1
++#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000
++#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15
++#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff
++#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0
++#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400
++#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa
++#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff
++#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0
++#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
++#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1
++#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4
++#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
++#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8
++#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3
++#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10
++#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4
++#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20
++#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5
++#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40
++#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6
++#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80
++#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7
++#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100
++#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8
++#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200
++#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9
++#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400
++#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa
++#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800
++#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb
++#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
++#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
++#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000
++#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12
++#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000
++#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14
++#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000
++#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
++#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000
++#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16
++#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000
++#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17
++#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000
++#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18
++#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000
++#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19
++#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
++#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
++#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
++#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
++#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
++#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0
++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6
++#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1
++#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0
++#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6
++#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1
++#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS_MASK 0x10
++#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS__SHIFT 0x4
++#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1
++#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0
++#define BIF_RESET_CNTL__RST_DONE_MASK 0x2
++#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1
++#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4
++#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
++#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8
++#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3
++#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100
++#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8
++#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
++#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
++#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
++#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
++#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
++#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
++#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
++#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
++#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
++#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN_MASK 0x1
++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN__SHIFT 0x0
++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER_MASK 0xffff0000
++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER__SHIFT 0x10
++#define C_PCIE_P_INDEX__PCIE_INDEX_MASK 0xffffffff
++#define C_PCIE_P_INDEX__PCIE_INDEX__SHIFT 0x0
++#define C_PCIE_P_DATA__PCIE_DATA_MASK 0xffffffff
++#define C_PCIE_P_DATA__PCIE_DATA__SHIFT 0x0
++#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D2F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D2F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D2F1_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D2F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D2F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D2F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D2F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D2F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D2F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D2F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D2F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D2F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D2F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D2F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D2F1_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D2F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D2F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D2F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D2F1_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D2F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D2F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D2F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D2F1_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D2F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D2F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D2F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D2F1_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D2F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D2F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D2F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D2F1_COMMAND__AD_STEPPING_MASK 0x80
++#define D2F1_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D2F1_COMMAND__SERR_EN_MASK 0x100
++#define D2F1_COMMAND__SERR_EN__SHIFT 0x8
++#define D2F1_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D2F1_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D2F1_COMMAND__INT_DIS_MASK 0x400
++#define D2F1_COMMAND__INT_DIS__SHIFT 0xa
++#define D2F1_STATUS__INT_STATUS_MASK 0x80000
++#define D2F1_STATUS__INT_STATUS__SHIFT 0x13
++#define D2F1_STATUS__CAP_LIST_MASK 0x100000
++#define D2F1_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F1_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F1_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F1_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F1_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F1_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D2F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D2F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D2F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D2F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D2F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D2F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D2F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D2F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D2F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D2F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D2F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D2F1_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D2F1_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D2F1_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D2F1_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D2F1_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D2F1_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D2F1_BIST__BIST_COMP_MASK 0xf000000
++#define D2F1_BIST__BIST_COMP__SHIFT 0x18
++#define D2F1_BIST__BIST_STRT_MASK 0x40000000
++#define D2F1_BIST__BIST_STRT__SHIFT 0x1e
++#define D2F1_BIST__BIST_CAP_MASK 0x80000000
++#define D2F1_BIST__BIST_CAP__SHIFT 0x1f
++#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D2F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D2F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D2F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D2F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D2F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D2F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D2F1_CAP_PTR__CAP_PTR_MASK 0xff
++#define D2F1_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D2F1_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F1_PMI_CAP__VERSION_MASK 0x70000
++#define D2F1_PMI_CAP__VERSION__SHIFT 0x10
++#define D2F1_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D2F1_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D2F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D2F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D2F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D2F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D2F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D2F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D2F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D2F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D2F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D2F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D2F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D2F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D2F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D2F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D2F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D2F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D2F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D2F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D2F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D2F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D2F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F1_PCIE_CAP__VERSION_MASK 0xf0000
++#define D2F1_PCIE_CAP__VERSION__SHIFT 0x10
++#define D2F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D2F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D2F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D2F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D2F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D2F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D2F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D2F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D2F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D2F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D2F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D2F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D2F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D2F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D2F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D2F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D2F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D2F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D2F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D2F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D2F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D2F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D2F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D2F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D2F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D2F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D2F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D2F1_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D2F1_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D2F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D2F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D2F1_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D2F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D2F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D2F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D2F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D2F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D2F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D2F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D2F1_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D2F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D2F1_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D2F1_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D2F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D2F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D2F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D2F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D2F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D2F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D2F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D2F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D2F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D2F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D2F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D2F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D2F1_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D2F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D2F1_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D2F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D2F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D2F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D2F1_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D2F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D2F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D2F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D2F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D2F1_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D2F1_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D2F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D2F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D2F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D2F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D2F1_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D2F1_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D2F1_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D2F1_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D2F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F1_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D2F1_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D2F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D2F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D2F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D2F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D2F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D2F1_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D2F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D2F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D2F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F1_MSI_MAP_CAP__EN_MASK 0x10000
++#define D2F1_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D2F1_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D2F1_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D2F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D2F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D2F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D2F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D2F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D2F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D2F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D2F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D2F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D2F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D2F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D2F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D2F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D2F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D2F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D2F2_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D2F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D2F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D2F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D2F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D2F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D2F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D2F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D2F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D2F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D2F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D2F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D2F2_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D2F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D2F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D2F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D2F2_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D2F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D2F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D2F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D2F2_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D2F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D2F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D2F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D2F2_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D2F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D2F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D2F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D2F2_COMMAND__AD_STEPPING_MASK 0x80
++#define D2F2_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D2F2_COMMAND__SERR_EN_MASK 0x100
++#define D2F2_COMMAND__SERR_EN__SHIFT 0x8
++#define D2F2_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D2F2_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D2F2_COMMAND__INT_DIS_MASK 0x400
++#define D2F2_COMMAND__INT_DIS__SHIFT 0xa
++#define D2F2_STATUS__INT_STATUS_MASK 0x80000
++#define D2F2_STATUS__INT_STATUS__SHIFT 0x13
++#define D2F2_STATUS__CAP_LIST_MASK 0x100000
++#define D2F2_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F2_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F2_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F2_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F2_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F2_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D2F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D2F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D2F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D2F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D2F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D2F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D2F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D2F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D2F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D2F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D2F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D2F2_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D2F2_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D2F2_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D2F2_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D2F2_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D2F2_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D2F2_BIST__BIST_COMP_MASK 0xf000000
++#define D2F2_BIST__BIST_COMP__SHIFT 0x18
++#define D2F2_BIST__BIST_STRT_MASK 0x40000000
++#define D2F2_BIST__BIST_STRT__SHIFT 0x1e
++#define D2F2_BIST__BIST_CAP_MASK 0x80000000
++#define D2F2_BIST__BIST_CAP__SHIFT 0x1f
++#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D2F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D2F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D2F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D2F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D2F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D2F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D2F2_CAP_PTR__CAP_PTR_MASK 0xff
++#define D2F2_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D2F2_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F2_PMI_CAP__VERSION_MASK 0x70000
++#define D2F2_PMI_CAP__VERSION__SHIFT 0x10
++#define D2F2_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D2F2_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D2F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D2F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D2F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D2F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D2F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D2F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D2F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D2F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D2F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D2F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D2F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D2F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D2F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D2F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D2F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D2F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D2F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D2F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D2F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D2F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D2F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F2_PCIE_CAP__VERSION_MASK 0xf0000
++#define D2F2_PCIE_CAP__VERSION__SHIFT 0x10
++#define D2F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D2F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D2F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D2F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D2F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D2F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D2F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D2F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D2F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D2F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D2F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D2F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D2F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D2F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D2F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D2F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D2F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D2F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D2F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D2F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D2F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D2F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D2F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D2F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D2F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D2F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D2F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D2F2_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D2F2_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D2F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D2F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D2F2_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D2F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D2F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D2F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D2F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D2F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D2F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D2F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D2F2_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D2F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D2F2_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D2F2_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D2F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D2F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D2F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D2F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D2F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D2F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D2F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D2F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D2F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D2F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D2F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D2F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D2F2_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D2F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D2F2_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D2F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D2F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D2F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D2F2_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D2F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D2F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D2F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D2F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D2F2_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D2F2_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D2F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D2F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D2F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D2F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D2F2_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D2F2_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D2F2_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D2F2_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D2F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F2_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D2F2_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D2F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D2F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D2F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D2F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D2F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D2F2_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D2F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D2F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D2F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F2_MSI_MAP_CAP__EN_MASK 0x10000
++#define D2F2_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D2F2_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D2F2_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D2F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D2F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D2F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D2F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D2F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D2F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D2F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D2F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D2F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D2F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D2F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D2F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D2F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D2F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D2F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D2F3_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D2F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D2F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D2F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D2F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D2F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D2F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D2F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D2F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D2F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D2F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D2F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D2F3_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D2F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D2F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D2F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D2F3_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D2F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D2F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D2F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D2F3_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D2F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D2F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D2F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D2F3_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D2F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D2F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D2F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D2F3_COMMAND__AD_STEPPING_MASK 0x80
++#define D2F3_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D2F3_COMMAND__SERR_EN_MASK 0x100
++#define D2F3_COMMAND__SERR_EN__SHIFT 0x8
++#define D2F3_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D2F3_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D2F3_COMMAND__INT_DIS_MASK 0x400
++#define D2F3_COMMAND__INT_DIS__SHIFT 0xa
++#define D2F3_STATUS__INT_STATUS_MASK 0x80000
++#define D2F3_STATUS__INT_STATUS__SHIFT 0x13
++#define D2F3_STATUS__CAP_LIST_MASK 0x100000
++#define D2F3_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F3_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F3_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F3_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F3_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F3_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D2F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D2F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D2F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D2F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D2F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D2F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D2F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D2F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D2F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D2F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D2F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D2F3_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D2F3_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D2F3_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D2F3_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D2F3_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D2F3_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D2F3_BIST__BIST_COMP_MASK 0xf000000
++#define D2F3_BIST__BIST_COMP__SHIFT 0x18
++#define D2F3_BIST__BIST_STRT_MASK 0x40000000
++#define D2F3_BIST__BIST_STRT__SHIFT 0x1e
++#define D2F3_BIST__BIST_CAP_MASK 0x80000000
++#define D2F3_BIST__BIST_CAP__SHIFT 0x1f
++#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D2F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D2F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D2F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D2F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D2F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D2F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D2F3_CAP_PTR__CAP_PTR_MASK 0xff
++#define D2F3_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D2F3_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F3_PMI_CAP__VERSION_MASK 0x70000
++#define D2F3_PMI_CAP__VERSION__SHIFT 0x10
++#define D2F3_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D2F3_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D2F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D2F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D2F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D2F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D2F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D2F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D2F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D2F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D2F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D2F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D2F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D2F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D2F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D2F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D2F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D2F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D2F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D2F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D2F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D2F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D2F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F3_PCIE_CAP__VERSION_MASK 0xf0000
++#define D2F3_PCIE_CAP__VERSION__SHIFT 0x10
++#define D2F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D2F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D2F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D2F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D2F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D2F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D2F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D2F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D2F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D2F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D2F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D2F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D2F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D2F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D2F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D2F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D2F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D2F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D2F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D2F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D2F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D2F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D2F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D2F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D2F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D2F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D2F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D2F3_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D2F3_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D2F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D2F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D2F3_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D2F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D2F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D2F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D2F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D2F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D2F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D2F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D2F3_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D2F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D2F3_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D2F3_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D2F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D2F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D2F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D2F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D2F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D2F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D2F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D2F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D2F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D2F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D2F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D2F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D2F3_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D2F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D2F3_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D2F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D2F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D2F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D2F3_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D2F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D2F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D2F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D2F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D2F3_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D2F3_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D2F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D2F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D2F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D2F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D2F3_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D2F3_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D2F3_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D2F3_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D2F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F3_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D2F3_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D2F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D2F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D2F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D2F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D2F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D2F3_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D2F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D2F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D2F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F3_MSI_MAP_CAP__EN_MASK 0x10000
++#define D2F3_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D2F3_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D2F3_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D2F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D2F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D2F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D2F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D2F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D2F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D2F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D2F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D2F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D2F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D2F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D2F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D2F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D2F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D2F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D2F4_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D2F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D2F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D2F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D2F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D2F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D2F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D2F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D2F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D2F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D2F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D2F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D2F4_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D2F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D2F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D2F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D2F4_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D2F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D2F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D2F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D2F4_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D2F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D2F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D2F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D2F4_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D2F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D2F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D2F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D2F4_COMMAND__AD_STEPPING_MASK 0x80
++#define D2F4_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D2F4_COMMAND__SERR_EN_MASK 0x100
++#define D2F4_COMMAND__SERR_EN__SHIFT 0x8
++#define D2F4_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D2F4_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D2F4_COMMAND__INT_DIS_MASK 0x400
++#define D2F4_COMMAND__INT_DIS__SHIFT 0xa
++#define D2F4_STATUS__INT_STATUS_MASK 0x80000
++#define D2F4_STATUS__INT_STATUS__SHIFT 0x13
++#define D2F4_STATUS__CAP_LIST_MASK 0x100000
++#define D2F4_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F4_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F4_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F4_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F4_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F4_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D2F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D2F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D2F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D2F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D2F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D2F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D2F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D2F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D2F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D2F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D2F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D2F4_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D2F4_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D2F4_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D2F4_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D2F4_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D2F4_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D2F4_BIST__BIST_COMP_MASK 0xf000000
++#define D2F4_BIST__BIST_COMP__SHIFT 0x18
++#define D2F4_BIST__BIST_STRT_MASK 0x40000000
++#define D2F4_BIST__BIST_STRT__SHIFT 0x1e
++#define D2F4_BIST__BIST_CAP_MASK 0x80000000
++#define D2F4_BIST__BIST_CAP__SHIFT 0x1f
++#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D2F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D2F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D2F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D2F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D2F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D2F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D2F4_CAP_PTR__CAP_PTR_MASK 0xff
++#define D2F4_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D2F4_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F4_PMI_CAP__VERSION_MASK 0x70000
++#define D2F4_PMI_CAP__VERSION__SHIFT 0x10
++#define D2F4_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D2F4_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D2F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D2F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D2F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D2F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D2F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D2F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D2F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D2F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D2F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D2F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D2F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D2F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D2F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D2F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D2F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D2F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D2F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D2F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D2F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D2F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D2F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F4_PCIE_CAP__VERSION_MASK 0xf0000
++#define D2F4_PCIE_CAP__VERSION__SHIFT 0x10
++#define D2F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D2F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D2F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D2F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D2F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D2F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D2F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D2F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D2F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D2F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D2F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D2F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D2F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D2F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D2F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D2F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D2F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D2F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D2F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D2F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D2F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D2F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D2F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D2F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D2F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D2F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D2F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D2F4_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D2F4_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D2F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D2F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D2F4_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D2F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D2F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D2F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D2F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D2F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D2F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D2F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D2F4_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D2F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D2F4_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D2F4_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D2F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D2F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D2F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D2F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D2F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D2F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D2F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D2F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D2F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D2F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D2F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D2F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D2F4_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D2F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D2F4_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D2F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D2F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D2F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D2F4_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D2F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D2F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D2F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D2F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D2F4_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D2F4_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D2F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D2F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D2F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D2F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D2F4_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D2F4_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D2F4_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D2F4_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D2F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F4_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D2F4_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D2F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D2F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D2F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D2F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D2F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D2F4_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D2F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D2F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D2F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F4_MSI_MAP_CAP__EN_MASK 0x10000
++#define D2F4_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D2F4_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D2F4_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D2F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D2F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D2F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D2F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D2F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D2F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D2F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D2F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D2F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D2F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D2F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D2F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D2F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D2F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D2F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D2F5_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D2F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D2F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D2F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D2F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D2F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D2F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D2F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D2F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D2F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D2F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D2F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D2F5_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D2F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D2F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D2F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D2F5_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D2F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D2F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D2F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D2F5_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D2F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D2F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D2F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D2F5_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D2F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D2F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D2F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D2F5_COMMAND__AD_STEPPING_MASK 0x80
++#define D2F5_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D2F5_COMMAND__SERR_EN_MASK 0x100
++#define D2F5_COMMAND__SERR_EN__SHIFT 0x8
++#define D2F5_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D2F5_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D2F5_COMMAND__INT_DIS_MASK 0x400
++#define D2F5_COMMAND__INT_DIS__SHIFT 0xa
++#define D2F5_STATUS__INT_STATUS_MASK 0x80000
++#define D2F5_STATUS__INT_STATUS__SHIFT 0x13
++#define D2F5_STATUS__CAP_LIST_MASK 0x100000
++#define D2F5_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F5_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F5_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F5_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F5_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F5_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D2F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D2F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D2F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D2F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D2F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D2F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D2F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D2F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D2F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D2F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D2F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D2F5_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D2F5_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D2F5_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D2F5_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D2F5_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D2F5_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D2F5_BIST__BIST_COMP_MASK 0xf000000
++#define D2F5_BIST__BIST_COMP__SHIFT 0x18
++#define D2F5_BIST__BIST_STRT_MASK 0x40000000
++#define D2F5_BIST__BIST_STRT__SHIFT 0x1e
++#define D2F5_BIST__BIST_CAP_MASK 0x80000000
++#define D2F5_BIST__BIST_CAP__SHIFT 0x1f
++#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D2F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D2F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D2F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D2F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D2F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D2F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D2F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D2F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D2F5_CAP_PTR__CAP_PTR_MASK 0xff
++#define D2F5_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D2F5_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F5_PMI_CAP__VERSION_MASK 0x70000
++#define D2F5_PMI_CAP__VERSION__SHIFT 0x10
++#define D2F5_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D2F5_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D2F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D2F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D2F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D2F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D2F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D2F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D2F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D2F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D2F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D2F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D2F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D2F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D2F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D2F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D2F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D2F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D2F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D2F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D2F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D2F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D2F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F5_PCIE_CAP__VERSION_MASK 0xf0000
++#define D2F5_PCIE_CAP__VERSION__SHIFT 0x10
++#define D2F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D2F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D2F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D2F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D2F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D2F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D2F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D2F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D2F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D2F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D2F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D2F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D2F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D2F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D2F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D2F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D2F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D2F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D2F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D2F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D2F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D2F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D2F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D2F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D2F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D2F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D2F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D2F5_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D2F5_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D2F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D2F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D2F5_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D2F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D2F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D2F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D2F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D2F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D2F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D2F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D2F5_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D2F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D2F5_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D2F5_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D2F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D2F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D2F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D2F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D2F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D2F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D2F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D2F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D2F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D2F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D2F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D2F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D2F5_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D2F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D2F5_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D2F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D2F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D2F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D2F5_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D2F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D2F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D2F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D2F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D2F5_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D2F5_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D2F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D2F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D2F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D2F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D2F5_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D2F5_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D2F5_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D2F5_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D2F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D2F5_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D2F5_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D2F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D2F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D2F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D2F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D2F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D2F5_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D2F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D2F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D2F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D2F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D2F5_MSI_MAP_CAP__EN_MASK 0x10000
++#define D2F5_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D2F5_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D2F5_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D2F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D2F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D2F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D2F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D2F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D2F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D2F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D2F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D2F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D2F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D2F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D2F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D2F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D3F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D3F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D3F1_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D3F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D3F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D3F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D3F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D3F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D3F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D3F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D3F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D3F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D3F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D3F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D3F1_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D3F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D3F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D3F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D3F1_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D3F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D3F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D3F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D3F1_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D3F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D3F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D3F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D3F1_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D3F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D3F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D3F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D3F1_COMMAND__AD_STEPPING_MASK 0x80
++#define D3F1_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D3F1_COMMAND__SERR_EN_MASK 0x100
++#define D3F1_COMMAND__SERR_EN__SHIFT 0x8
++#define D3F1_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D3F1_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D3F1_COMMAND__INT_DIS_MASK 0x400
++#define D3F1_COMMAND__INT_DIS__SHIFT 0xa
++#define D3F1_STATUS__INT_STATUS_MASK 0x80000
++#define D3F1_STATUS__INT_STATUS__SHIFT 0x13
++#define D3F1_STATUS__CAP_LIST_MASK 0x100000
++#define D3F1_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F1_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F1_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F1_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F1_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F1_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D3F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D3F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D3F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D3F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D3F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D3F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D3F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D3F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D3F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D3F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D3F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D3F1_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D3F1_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D3F1_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D3F1_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D3F1_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D3F1_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D3F1_BIST__BIST_COMP_MASK 0xf000000
++#define D3F1_BIST__BIST_COMP__SHIFT 0x18
++#define D3F1_BIST__BIST_STRT_MASK 0x40000000
++#define D3F1_BIST__BIST_STRT__SHIFT 0x1e
++#define D3F1_BIST__BIST_CAP_MASK 0x80000000
++#define D3F1_BIST__BIST_CAP__SHIFT 0x1f
++#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D3F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D3F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D3F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D3F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D3F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D3F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D3F1_CAP_PTR__CAP_PTR_MASK 0xff
++#define D3F1_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D3F1_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F1_PMI_CAP__VERSION_MASK 0x70000
++#define D3F1_PMI_CAP__VERSION__SHIFT 0x10
++#define D3F1_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D3F1_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D3F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D3F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D3F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D3F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D3F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D3F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D3F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D3F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D3F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D3F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D3F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D3F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D3F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D3F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D3F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D3F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D3F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D3F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D3F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D3F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D3F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F1_PCIE_CAP__VERSION_MASK 0xf0000
++#define D3F1_PCIE_CAP__VERSION__SHIFT 0x10
++#define D3F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D3F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D3F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D3F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D3F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D3F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D3F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D3F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D3F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D3F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D3F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D3F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D3F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D3F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D3F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D3F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D3F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D3F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D3F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D3F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D3F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D3F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D3F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D3F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D3F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D3F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D3F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D3F1_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D3F1_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D3F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D3F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D3F1_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D3F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D3F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D3F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D3F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D3F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D3F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D3F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D3F1_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D3F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D3F1_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D3F1_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D3F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D3F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D3F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D3F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D3F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D3F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D3F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D3F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D3F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D3F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D3F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D3F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D3F1_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D3F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D3F1_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D3F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D3F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D3F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D3F1_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D3F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D3F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D3F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D3F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D3F1_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D3F1_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D3F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D3F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D3F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D3F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D3F1_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D3F1_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D3F1_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D3F1_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D3F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F1_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D3F1_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D3F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D3F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D3F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D3F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D3F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D3F1_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D3F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D3F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D3F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F1_MSI_MAP_CAP__EN_MASK 0x10000
++#define D3F1_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D3F1_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D3F1_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D3F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D3F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D3F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D3F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D3F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D3F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D3F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D3F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D3F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D3F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D3F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D3F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D3F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D3F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D3F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D3F2_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D3F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D3F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D3F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D3F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D3F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D3F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D3F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D3F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D3F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D3F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D3F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D3F2_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D3F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D3F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D3F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D3F2_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D3F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D3F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D3F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D3F2_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D3F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D3F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D3F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D3F2_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D3F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D3F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D3F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D3F2_COMMAND__AD_STEPPING_MASK 0x80
++#define D3F2_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D3F2_COMMAND__SERR_EN_MASK 0x100
++#define D3F2_COMMAND__SERR_EN__SHIFT 0x8
++#define D3F2_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D3F2_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D3F2_COMMAND__INT_DIS_MASK 0x400
++#define D3F2_COMMAND__INT_DIS__SHIFT 0xa
++#define D3F2_STATUS__INT_STATUS_MASK 0x80000
++#define D3F2_STATUS__INT_STATUS__SHIFT 0x13
++#define D3F2_STATUS__CAP_LIST_MASK 0x100000
++#define D3F2_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F2_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F2_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F2_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F2_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F2_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D3F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D3F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D3F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D3F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D3F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D3F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D3F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D3F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D3F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D3F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D3F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D3F2_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D3F2_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D3F2_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D3F2_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D3F2_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D3F2_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D3F2_BIST__BIST_COMP_MASK 0xf000000
++#define D3F2_BIST__BIST_COMP__SHIFT 0x18
++#define D3F2_BIST__BIST_STRT_MASK 0x40000000
++#define D3F2_BIST__BIST_STRT__SHIFT 0x1e
++#define D3F2_BIST__BIST_CAP_MASK 0x80000000
++#define D3F2_BIST__BIST_CAP__SHIFT 0x1f
++#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D3F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D3F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D3F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D3F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D3F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D3F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D3F2_CAP_PTR__CAP_PTR_MASK 0xff
++#define D3F2_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D3F2_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F2_PMI_CAP__VERSION_MASK 0x70000
++#define D3F2_PMI_CAP__VERSION__SHIFT 0x10
++#define D3F2_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D3F2_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D3F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D3F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D3F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D3F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D3F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D3F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D3F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D3F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D3F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D3F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D3F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D3F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D3F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D3F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D3F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D3F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D3F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D3F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D3F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D3F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D3F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F2_PCIE_CAP__VERSION_MASK 0xf0000
++#define D3F2_PCIE_CAP__VERSION__SHIFT 0x10
++#define D3F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D3F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D3F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D3F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D3F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D3F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D3F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D3F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D3F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D3F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D3F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D3F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D3F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D3F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D3F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D3F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D3F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D3F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D3F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D3F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D3F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D3F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D3F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D3F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D3F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D3F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D3F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D3F2_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D3F2_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D3F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D3F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D3F2_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D3F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D3F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D3F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D3F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D3F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D3F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D3F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D3F2_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D3F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D3F2_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D3F2_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D3F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D3F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D3F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D3F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D3F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D3F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D3F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D3F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D3F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D3F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D3F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D3F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D3F2_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D3F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D3F2_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D3F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D3F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D3F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D3F2_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D3F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D3F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D3F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D3F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D3F2_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D3F2_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D3F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D3F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D3F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D3F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D3F2_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D3F2_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D3F2_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D3F2_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D3F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F2_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D3F2_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D3F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D3F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D3F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D3F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D3F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D3F2_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D3F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D3F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D3F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F2_MSI_MAP_CAP__EN_MASK 0x10000
++#define D3F2_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D3F2_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D3F2_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D3F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D3F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D3F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D3F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D3F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D3F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D3F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D3F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D3F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D3F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D3F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D3F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D3F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D3F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D3F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D3F3_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D3F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D3F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D3F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D3F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D3F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D3F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D3F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D3F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D3F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D3F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D3F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D3F3_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D3F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D3F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D3F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D3F3_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D3F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D3F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D3F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D3F3_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D3F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D3F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D3F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D3F3_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D3F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D3F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D3F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D3F3_COMMAND__AD_STEPPING_MASK 0x80
++#define D3F3_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D3F3_COMMAND__SERR_EN_MASK 0x100
++#define D3F3_COMMAND__SERR_EN__SHIFT 0x8
++#define D3F3_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D3F3_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D3F3_COMMAND__INT_DIS_MASK 0x400
++#define D3F3_COMMAND__INT_DIS__SHIFT 0xa
++#define D3F3_STATUS__INT_STATUS_MASK 0x80000
++#define D3F3_STATUS__INT_STATUS__SHIFT 0x13
++#define D3F3_STATUS__CAP_LIST_MASK 0x100000
++#define D3F3_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F3_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F3_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F3_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F3_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F3_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D3F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D3F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D3F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D3F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D3F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D3F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D3F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D3F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D3F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D3F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D3F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D3F3_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D3F3_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D3F3_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D3F3_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D3F3_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D3F3_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D3F3_BIST__BIST_COMP_MASK 0xf000000
++#define D3F3_BIST__BIST_COMP__SHIFT 0x18
++#define D3F3_BIST__BIST_STRT_MASK 0x40000000
++#define D3F3_BIST__BIST_STRT__SHIFT 0x1e
++#define D3F3_BIST__BIST_CAP_MASK 0x80000000
++#define D3F3_BIST__BIST_CAP__SHIFT 0x1f
++#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D3F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D3F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D3F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D3F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D3F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D3F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D3F3_CAP_PTR__CAP_PTR_MASK 0xff
++#define D3F3_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D3F3_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F3_PMI_CAP__VERSION_MASK 0x70000
++#define D3F3_PMI_CAP__VERSION__SHIFT 0x10
++#define D3F3_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D3F3_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D3F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D3F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D3F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D3F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D3F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D3F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D3F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D3F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D3F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D3F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D3F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D3F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D3F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D3F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D3F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D3F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D3F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D3F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D3F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D3F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D3F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F3_PCIE_CAP__VERSION_MASK 0xf0000
++#define D3F3_PCIE_CAP__VERSION__SHIFT 0x10
++#define D3F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D3F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D3F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D3F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D3F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D3F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D3F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D3F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D3F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D3F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D3F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D3F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D3F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D3F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D3F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D3F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D3F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D3F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D3F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D3F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D3F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D3F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D3F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D3F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D3F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D3F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D3F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D3F3_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D3F3_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D3F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D3F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D3F3_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D3F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D3F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D3F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D3F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D3F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D3F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D3F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D3F3_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D3F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D3F3_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D3F3_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D3F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D3F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D3F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D3F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D3F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D3F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D3F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D3F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D3F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D3F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D3F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D3F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D3F3_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D3F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D3F3_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D3F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D3F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D3F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D3F3_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D3F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D3F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D3F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D3F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D3F3_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D3F3_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D3F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D3F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D3F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D3F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D3F3_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D3F3_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D3F3_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D3F3_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D3F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F3_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D3F3_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D3F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D3F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D3F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D3F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D3F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D3F3_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D3F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D3F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D3F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F3_MSI_MAP_CAP__EN_MASK 0x10000
++#define D3F3_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D3F3_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D3F3_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D3F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D3F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D3F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D3F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D3F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D3F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D3F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D3F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D3F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D3F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D3F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D3F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D3F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D3F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D3F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D3F4_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D3F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D3F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D3F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D3F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D3F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D3F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D3F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D3F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D3F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D3F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D3F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D3F4_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D3F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D3F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D3F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D3F4_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D3F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D3F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D3F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D3F4_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D3F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D3F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D3F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D3F4_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D3F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D3F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D3F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D3F4_COMMAND__AD_STEPPING_MASK 0x80
++#define D3F4_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D3F4_COMMAND__SERR_EN_MASK 0x100
++#define D3F4_COMMAND__SERR_EN__SHIFT 0x8
++#define D3F4_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D3F4_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D3F4_COMMAND__INT_DIS_MASK 0x400
++#define D3F4_COMMAND__INT_DIS__SHIFT 0xa
++#define D3F4_STATUS__INT_STATUS_MASK 0x80000
++#define D3F4_STATUS__INT_STATUS__SHIFT 0x13
++#define D3F4_STATUS__CAP_LIST_MASK 0x100000
++#define D3F4_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F4_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F4_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F4_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F4_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F4_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D3F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D3F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D3F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D3F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D3F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D3F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D3F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D3F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D3F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D3F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D3F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D3F4_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D3F4_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D3F4_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D3F4_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D3F4_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D3F4_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D3F4_BIST__BIST_COMP_MASK 0xf000000
++#define D3F4_BIST__BIST_COMP__SHIFT 0x18
++#define D3F4_BIST__BIST_STRT_MASK 0x40000000
++#define D3F4_BIST__BIST_STRT__SHIFT 0x1e
++#define D3F4_BIST__BIST_CAP_MASK 0x80000000
++#define D3F4_BIST__BIST_CAP__SHIFT 0x1f
++#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D3F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D3F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D3F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D3F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D3F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D3F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D3F4_CAP_PTR__CAP_PTR_MASK 0xff
++#define D3F4_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D3F4_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F4_PMI_CAP__VERSION_MASK 0x70000
++#define D3F4_PMI_CAP__VERSION__SHIFT 0x10
++#define D3F4_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D3F4_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D3F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D3F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D3F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D3F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D3F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D3F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D3F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D3F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D3F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D3F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D3F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D3F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D3F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D3F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D3F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D3F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D3F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D3F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D3F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D3F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D3F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F4_PCIE_CAP__VERSION_MASK 0xf0000
++#define D3F4_PCIE_CAP__VERSION__SHIFT 0x10
++#define D3F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D3F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D3F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D3F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D3F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D3F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D3F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D3F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D3F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D3F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D3F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D3F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D3F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D3F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D3F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D3F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D3F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D3F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D3F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D3F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D3F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D3F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D3F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D3F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D3F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D3F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D3F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D3F4_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D3F4_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D3F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D3F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D3F4_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D3F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D3F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D3F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D3F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D3F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D3F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D3F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D3F4_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D3F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D3F4_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D3F4_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D3F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D3F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D3F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D3F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D3F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D3F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D3F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D3F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D3F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D3F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D3F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D3F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D3F4_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D3F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D3F4_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D3F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D3F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D3F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D3F4_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D3F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D3F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D3F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D3F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D3F4_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D3F4_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D3F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D3F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D3F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D3F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D3F4_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D3F4_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D3F4_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D3F4_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D3F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F4_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D3F4_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D3F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D3F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D3F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D3F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D3F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D3F4_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D3F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D3F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D3F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F4_MSI_MAP_CAP__EN_MASK 0x10000
++#define D3F4_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D3F4_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D3F4_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D3F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D3F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D3F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D3F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D3F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D3F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D3F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D3F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D3F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D3F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D3F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D3F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D3F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
++#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
++#define D3F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
++#define D3F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
++#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
++#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
++#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
++#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
++#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
++#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
++#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
++#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
++#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
++#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
++#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
++#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
++#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
++#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
++#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
++#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
++#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
++#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
++#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
++#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
++#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
++#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
++#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
++#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
++#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
++#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
++#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
++#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
++#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
++#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
++#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
++#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
++#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
++#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
++#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
++#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
++#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
++#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
++#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
++#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
++#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
++#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
++#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
++#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
++#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
++#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
++#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
++#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
++#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
++#define D3F5_PCIE_FC_P__PD_CREDITS_MASK 0xff
++#define D3F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
++#define D3F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00
++#define D3F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
++#define D3F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
++#define D3F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
++#define D3F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
++#define D3F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
++#define D3F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
++#define D3F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
++#define D3F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
++#define D3F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
++#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
++#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
++#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
++#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
++#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
++#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
++#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
++#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
++#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
++#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
++#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
++#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
++#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
++#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
++#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
++#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
++#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
++#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
++#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
++#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
++#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
++#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
++#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
++#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
++#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
++#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
++#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
++#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
++#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
++#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
++#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
++#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
++#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
++#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
++#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
++#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
++#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
++#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
++#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
++#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
++#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
++#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
++#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
++#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
++#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
++#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
++#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
++#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
++#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
++#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
++#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
++#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
++#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
++#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
++#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
++#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
++#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
++#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
++#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
++#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
++#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
++#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
++#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
++#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
++#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
++#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
++#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
++#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
++#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
++#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
++#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
++#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
++#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
++#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
++#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
++#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
++#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
++#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
++#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
++#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
++#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
++#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
++#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
++#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
++#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
++#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
++#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
++#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
++#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
++#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
++#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
++#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
++#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
++#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
++#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
++#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
++#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
++#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
++#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
++#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
++#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
++#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
++#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
++#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
++#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
++#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
++#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
++#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
++#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
++#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
++#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
++#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
++#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
++#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
++#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
++#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
++#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
++#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
++#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
++#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
++#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
++#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
++#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
++#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
++#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
++#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
++#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
++#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
++#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
++#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
++#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
++#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
++#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
++#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
++#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
++#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
++#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
++#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
++#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
++#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
++#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
++#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
++#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
++#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
++#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
++#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
++#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
++#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
++#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
++#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
++#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
++#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
++#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
++#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
++#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
++#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
++#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
++#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
++#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
++#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
++#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
++#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
++#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
++#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
++#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
++#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
++#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
++#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
++#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
++#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
++#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
++#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
++#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
++#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
++#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
++#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
++#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
++#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
++#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
++#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
++#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
++#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
++#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
++#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
++#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
++#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
++#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
++#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
++#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
++#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
++#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
++#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
++#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
++#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
++#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
++#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
++#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
++#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
++#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
++#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
++#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
++#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
++#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
++#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
++#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
++#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
++#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
++#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
++#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
++#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
++#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
++#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
++#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
++#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
++#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
++#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
++#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
++#define D3F5_VENDOR_ID__VENDOR_ID_MASK 0xffff
++#define D3F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
++#define D3F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
++#define D3F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10
++#define D3F5_COMMAND__IO_ACCESS_EN_MASK 0x1
++#define D3F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
++#define D3F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
++#define D3F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
++#define D3F5_COMMAND__BUS_MASTER_EN_MASK 0x4
++#define D3F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
++#define D3F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
++#define D3F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
++#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
++#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
++#define D3F5_COMMAND__PAL_SNOOP_EN_MASK 0x20
++#define D3F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
++#define D3F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
++#define D3F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
++#define D3F5_COMMAND__AD_STEPPING_MASK 0x80
++#define D3F5_COMMAND__AD_STEPPING__SHIFT 0x7
++#define D3F5_COMMAND__SERR_EN_MASK 0x100
++#define D3F5_COMMAND__SERR_EN__SHIFT 0x8
++#define D3F5_COMMAND__FAST_B2B_EN_MASK 0x200
++#define D3F5_COMMAND__FAST_B2B_EN__SHIFT 0x9
++#define D3F5_COMMAND__INT_DIS_MASK 0x400
++#define D3F5_COMMAND__INT_DIS__SHIFT 0xa
++#define D3F5_STATUS__INT_STATUS_MASK 0x80000
++#define D3F5_STATUS__INT_STATUS__SHIFT 0x13
++#define D3F5_STATUS__CAP_LIST_MASK 0x100000
++#define D3F5_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F5_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F5_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F5_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F5_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F5_REVISION_ID__MINOR_REV_ID_MASK 0xf
++#define D3F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
++#define D3F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
++#define D3F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
++#define D3F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
++#define D3F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
++#define D3F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000
++#define D3F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10
++#define D3F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000
++#define D3F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18
++#define D3F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
++#define D3F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
++#define D3F5_LATENCY__LATENCY_TIMER_MASK 0xff00
++#define D3F5_LATENCY__LATENCY_TIMER__SHIFT 0x8
++#define D3F5_HEADER__HEADER_TYPE_MASK 0x7f0000
++#define D3F5_HEADER__HEADER_TYPE__SHIFT 0x10
++#define D3F5_HEADER__DEVICE_TYPE_MASK 0x800000
++#define D3F5_HEADER__DEVICE_TYPE__SHIFT 0x17
++#define D3F5_BIST__BIST_COMP_MASK 0xf000000
++#define D3F5_BIST__BIST_COMP__SHIFT 0x18
++#define D3F5_BIST__BIST_STRT_MASK 0x40000000
++#define D3F5_BIST__BIST_STRT__SHIFT 0x1e
++#define D3F5_BIST__BIST_CAP_MASK 0x80000000
++#define D3F5_BIST__BIST_CAP__SHIFT 0x1f
++#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
++#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
++#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
++#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
++#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
++#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
++#define D3F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
++#define D3F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
++#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
++#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
++#define D3F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
++#define D3F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
++#define D3F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
++#define D3F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
++#define D3F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
++#define D3F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
++#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
++#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
++#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
++#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
++#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
++#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
++#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
++#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
++#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
++#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
++#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
++#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
++#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
++#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
++#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
++#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
++#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
++#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
++#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
++#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
++#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
++#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
++#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
++#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
++#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
++#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
++#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
++#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
++#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
++#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
++#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
++#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
++#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
++#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
++#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
++#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
++#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
++#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
++#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
++#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
++#define D3F5_CAP_PTR__CAP_PTR_MASK 0xff
++#define D3F5_CAP_PTR__CAP_PTR__SHIFT 0x0
++#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
++#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
++#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
++#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
++#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
++#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
++#define D3F5_PMI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F5_PMI_CAP__VERSION_MASK 0x70000
++#define D3F5_PMI_CAP__VERSION__SHIFT 0x10
++#define D3F5_PMI_CAP__PME_CLOCK_MASK 0x80000
++#define D3F5_PMI_CAP__PME_CLOCK__SHIFT 0x13
++#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
++#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
++#define D3F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
++#define D3F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16
++#define D3F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000
++#define D3F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19
++#define D3F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000
++#define D3F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
++#define D3F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
++#define D3F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
++#define D3F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
++#define D3F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
++#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
++#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
++#define D3F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100
++#define D3F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
++#define D3F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
++#define D3F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
++#define D3F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
++#define D3F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
++#define D3F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
++#define D3F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
++#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
++#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
++#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
++#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
++#define D3F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
++#define D3F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
++#define D3F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F5_PCIE_CAP__VERSION_MASK 0xf0000
++#define D3F5_PCIE_CAP__VERSION__SHIFT 0x10
++#define D3F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
++#define D3F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
++#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
++#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
++#define D3F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
++#define D3F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
++#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
++#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
++#define D3F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
++#define D3F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
++#define D3F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
++#define D3F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
++#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
++#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
++#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
++#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
++#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
++#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
++#define D3F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
++#define D3F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
++#define D3F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
++#define D3F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
++#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
++#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
++#define D3F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
++#define D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
++#define D3F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
++#define D3F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
++#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
++#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
++#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
++#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
++#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
++#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
++#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
++#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
++#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
++#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
++#define D3F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
++#define D3F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
++#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
++#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
++#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
++#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
++#define D3F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000
++#define D3F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
++#define D3F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
++#define D3F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
++#define D3F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
++#define D3F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
++#define D3F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
++#define D3F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
++#define D3F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000
++#define D3F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
++#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
++#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
++#define D3F5_LINK_CAP__LINK_SPEED_MASK 0xf
++#define D3F5_LINK_CAP__LINK_SPEED__SHIFT 0x0
++#define D3F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0
++#define D3F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
++#define D3F5_LINK_CAP__PM_SUPPORT_MASK 0xc00
++#define D3F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
++#define D3F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
++#define D3F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
++#define D3F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
++#define D3F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
++#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
++#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
++#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
++#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
++#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
++#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
++#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
++#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
++#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
++#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
++#define D3F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000
++#define D3F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
++#define D3F5_LINK_CNTL__PM_CONTROL_MASK 0x3
++#define D3F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
++#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
++#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
++#define D3F5_LINK_CNTL__LINK_DIS_MASK 0x10
++#define D3F5_LINK_CNTL__LINK_DIS__SHIFT 0x4
++#define D3F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20
++#define D3F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
++#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
++#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
++#define D3F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
++#define D3F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
++#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
++#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
++#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
++#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
++#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
++#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
++#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
++#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
++#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
++#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
++#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
++#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
++#define D3F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
++#define D3F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
++#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
++#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
++#define D3F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
++#define D3F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
++#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
++#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
++#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
++#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
++#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
++#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
++#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
++#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
++#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
++#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
++#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
++#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
++#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
++#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
++#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
++#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
++#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
++#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
++#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
++#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
++#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
++#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
++#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
++#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
++#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
++#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
++#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
++#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
++#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
++#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
++#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
++#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
++#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
++#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
++#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
++#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
++#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
++#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
++#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
++#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
++#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
++#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
++#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
++#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
++#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
++#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
++#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
++#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
++#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
++#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
++#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
++#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
++#define D3F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
++#define D3F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
++#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
++#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
++#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
++#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
++#define D3F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
++#define D3F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
++#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
++#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
++#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
++#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
++#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
++#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
++#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
++#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
++#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
++#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
++#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
++#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
++#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
++#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
++#define D3F5_ROOT_STATUS__PME_STATUS_MASK 0x10000
++#define D3F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
++#define D3F5_ROOT_STATUS__PME_PENDING_MASK 0x20000
++#define D3F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
++#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
++#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
++#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
++#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
++#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
++#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
++#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
++#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
++#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
++#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
++#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
++#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
++#define D3F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
++#define D3F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
++#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
++#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
++#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
++#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
++#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
++#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
++#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
++#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
++#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
++#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
++#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
++#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
++#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
++#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
++#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
++#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
++#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
++#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
++#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
++#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
++#define D3F5_DEVICE_CNTL2__LTR_EN_MASK 0x400
++#define D3F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
++#define D3F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
++#define D3F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
++#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
++#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
++#define D3F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10
++#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
++#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
++#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
++#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
++#define D3F5_LINK_CAP2__RESERVED_MASK 0xfffffe00
++#define D3F5_LINK_CAP2__RESERVED__SHIFT 0x9
++#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
++#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
++#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
++#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
++#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
++#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
++#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
++#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
++#define D3F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
++#define D3F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
++#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
++#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
++#define D3F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
++#define D3F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
++#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
++#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
++#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
++#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
++#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
++#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
++#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
++#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
++#define D3F5_SLOT_CAP2__RESERVED_MASK 0xffffffff
++#define D3F5_SLOT_CAP2__RESERVED__SHIFT 0x0
++#define D3F5_SLOT_CNTL2__RESERVED_MASK 0xffff
++#define D3F5_SLOT_CNTL2__RESERVED__SHIFT 0x0
++#define D3F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000
++#define D3F5_SLOT_STATUS2__RESERVED__SHIFT 0x10
++#define D3F5_MSI_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
++#define D3F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
++#define D3F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
++#define D3F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
++#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
++#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
++#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
++#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
++#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
++#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
++#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
++#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
++#define D3F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
++#define D3F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
++#define D3F5_SSID_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
++#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
++#define D3F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
++#define D3F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
++#define D3F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
++#define D3F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
++#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
++#define D3F5_MSI_MAP_CAP__EN_MASK 0x10000
++#define D3F5_MSI_MAP_CAP__EN__SHIFT 0x10
++#define D3F5_MSI_MAP_CAP__FIXD_MASK 0x20000
++#define D3F5_MSI_MAP_CAP__FIXD__SHIFT 0x11
++#define D3F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
++#define D3F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
++#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
++#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
++#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
++#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
++#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
++#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
++#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
++#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
++#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
++#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
++#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
++#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
++#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
++#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
++#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
++#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
++#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
++#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
++#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
++#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
++#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
++#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
++#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
++#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
++#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
++#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
++#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
++#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
++#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
++#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
++#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
++#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
++#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
++#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
++#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
++#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
++#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
++#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
++#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
++#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
++#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
++#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
++#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
++#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
++#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
++#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
++#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
++#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
++#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
++#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
++#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
++#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
++#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
++#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
++#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
++#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
++#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
++#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
++#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
++#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
++#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
++#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
++#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
++#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
++#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
++#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
++#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
++#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
++#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
++#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
++#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
++#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
++#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
++#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
++#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
++#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
++#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
++#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
++#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
++#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
++#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
++#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
++#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
++#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
++#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
++#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
++#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
++#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
++#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
++#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
++#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
++#define D3F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
++#define D3F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
++#define D3F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
++#define D3F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
++#define D3F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
++#define D3F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
++#define D3F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
++#define D3F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
++#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
++#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
++#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
++#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
++#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
++#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
++#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
++#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
++#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
++#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
++#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
++#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
++#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
++#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
++#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
++#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
++#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
++#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
++#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
++#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
++#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
++#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
++#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
++#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
++#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
++#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
++#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
++#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
++#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
++#define D3F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
++#define D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
++#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
++#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
++#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
++#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
++#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
++#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
++#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
++#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
++#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
++#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
++#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
++#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
++#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
++#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
++#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
++#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
++#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
++#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
++#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
++#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
++#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
++#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
++#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
++#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
++#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
++#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
++#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
++#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
++#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
++#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
++#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
++#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
++#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
++#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
++#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
++#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
++#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
++#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
++#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
++#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
++#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
++#define D3F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
++#define D3F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
++#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
++#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
++#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
++#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
++#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
++#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
++#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
++#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
++#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
++#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
++#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
++#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
++#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
++#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
++#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
++#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
++#define C_PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
++#define C_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
++#define C_PCIE_DATA__PCIE_DATA_MASK 0xffffffff
++#define C_PCIE_DATA__PCIE_DATA__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000
++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000
++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12
++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000
++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a
++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000
++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e
++#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1
++#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8
++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff
++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0
++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000
++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00
++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa
++#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf
++#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0
++#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1
++#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1
++#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0
++#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1
++#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1
++#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0
++#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1
++#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1
++#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0
++#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1
++#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1
++#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0
++#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1
++#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1
++#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
++#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
++#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
++#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
++#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
++#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
++#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
++#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
++#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0
++#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff
++#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
++#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
++#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
++#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
++#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
++#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
++#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1
++#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
++#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff
++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
++#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1
++#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0
++#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800
++#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb
++#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
++#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
++#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
++#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
++#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
++#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
++#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
++#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
++#define PSX80_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff
++#define PSX80_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0
++#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff
++#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0
++#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff
++#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0
++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff
++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0
++#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000
++#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10
++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000
++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14
++#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000
++#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1
++#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4
++#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7
++#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300
++#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8
++#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00
++#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa
++#define PSX80_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000
++#define PSX80_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc
++#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000
++#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15
++#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000
++#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c
++#define PSX80_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000
++#define PSX80_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000
++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0
++#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
++#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000
++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14
++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff
++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0
++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00
++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9
++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000
++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000
++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000
++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000
++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000
++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000
++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12
++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000
++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a
++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000
++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e
++#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1
++#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8
++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff
++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0
++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000
++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00
++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa
++#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf
++#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0
++#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1
++#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1
++#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0
++#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1
++#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1
++#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0
++#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1
++#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1
++#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0
++#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1
++#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1
++#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0
++#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1
++#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
++#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1
++#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
++#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
++#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
++#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
++#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
++#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
++#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
++#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
++#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0
++#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff
++#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
++#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
++#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
++#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
++#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
++#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
++#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1
++#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
++#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff
++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
++#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1
++#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0
++#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800
++#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb
++#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
++#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
++#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
++#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
++#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
++#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
++#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
++#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
++#define PSX81_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff
++#define PSX81_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0
++#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff
++#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0
++#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff
++#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0
++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff
++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0
++#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000
++#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10
++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000
++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14
++#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000
++#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1
++#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4
++#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7
++#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300
++#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8
++#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00
++#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa
++#define PSX81_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000
++#define PSX81_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc
++#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000
++#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15
++#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000
++#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c
++#define PSX81_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000
++#define PSX81_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000
++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0
++#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
++#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000
++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14
++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff
++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0
++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00
++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9
++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000
++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000
++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000
++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000
++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18
++#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
++#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
++#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
++#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
++#define RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
++#define RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
++#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
++#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
++#define RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
++#define RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
++#define RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
++#define RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst_MASK 0x1
++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst__SHIFT 0x0
++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK 0x2
++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst__SHIFT 0x1
++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst_MASK 0x4
++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT 0x2
++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst_MASK 0x1
++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst__SHIFT 0x0
++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK 0x2
++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst__SHIFT 0x1
++#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst_MASK 0x4
++#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT 0x2
++#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd_MASK 0x1
++#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd__SHIFT 0x0
++#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK 0x2
++#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd__SHIFT 0x1
++#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd_MASK 0x4
++#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT 0x2
++#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status_MASK 0x1
++#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status__SHIFT 0x0
++#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK 0x2
++#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status__SHIFT 0x1
++#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status_MASK 0x4
++#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT 0x2
++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer_MASK 0xff
++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer__SHIFT 0x0
++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer_MASK 0xf00
++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer__SHIFT 0x8
++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer_MASK 0xff0000
++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer__SHIFT 0x10
++#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout_MASK 0x1000000
++#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout__SHIFT 0x18
++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer_MASK 0xff
++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer__SHIFT 0x0
++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer_MASK 0xf00
++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer__SHIFT 0x8
++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer_MASK 0xff0000
++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer__SHIFT 0x10
++#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout_MASK 0x1000000
++#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout__SHIFT 0x18
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer_MASK 0xff
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer__SHIFT 0x0
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer_MASK 0xf00
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer__SHIFT 0x8
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer_MASK 0xff0000
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer__SHIFT 0x10
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout_MASK 0x1000000
++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout__SHIFT 0x18
++#define RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
++#define RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
++#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone_MASK 0x1
++#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone__SHIFT 0x0
++#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer_MASK 0x3ff
++#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer__SHIFT 0x0
++#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
++#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
++#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
++#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
++#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
++#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
++#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
++#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
++#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
++#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
++#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
++#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
++#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
++#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
++#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
++#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
++#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
++#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
++#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
++#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
++#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
++#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
++#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
++#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
++#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
++#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
++#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
++#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
++#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
++#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
++#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
++#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
++#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
++#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
++#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
++#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
++#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
++#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
++#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
++#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
++#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
++#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
++#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
++#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
++#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
++#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
++#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
++#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
++#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
++#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
++#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
++#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
++#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
++#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
++#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
++#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
++#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
++#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
++#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
++#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
++#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
++#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
++#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
++#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
++#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
++#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
++#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
++#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
++#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
++#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
++#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
++#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
++#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
++#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
++#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
++#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
++#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
++#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
++#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
++#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
++#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
++#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
++#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
++#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
++#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
++#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
++#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
++#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
++#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
++#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
++#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
++#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
++#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
++#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
++#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
++#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
++#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
++#define PSX80_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40
++#define PSX80_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6
++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
++#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
++#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
++#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
++#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
++#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
++#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
++#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
++#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
++#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
++#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
++#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
++#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
++#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
++#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
++#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
++#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
++#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
++#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
++#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
++#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
++#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
++#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
++#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
++#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
++#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
++#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
++#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
++#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
++#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
++#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
++#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
++#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
++#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
++#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
++#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
++#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
++#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
++#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
++#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
++#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
++#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
++#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
++#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
++#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
++#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
++#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
++#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
++#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
++#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
++#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
++#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
++#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
++#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
++#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
++#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
++#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
++#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
++#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
++#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
++#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
++#define PSX80_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000
++#define PSX80_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18
++#define PSX80_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e
++#define PSX80_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1
++#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
++#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
++#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0
++#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
++#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700
++#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
++#define PSX80_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff
++#define PSX80_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0
++#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
++#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100
++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
++#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
++#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
++#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
++#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
++#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100
++#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
++#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
++#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00
++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
++#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
++#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
++#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
++#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
++#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
++#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
++#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
++#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
++#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
++#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
++#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
++#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
++#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
++#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
++#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
++#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
++#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
++#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
++#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
++#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
++#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
++#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
++#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
++#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
++#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
++#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
++#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
++#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
++#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
++#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
++#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
++#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
++#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
++#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
++#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
++#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
++#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
++#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
++#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
++#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
++#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
++#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
++#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
++#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
++#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
++#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
++#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
++#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
++#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
++#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
++#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
++#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
++#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
++#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
++#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
++#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
++#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
++#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
++#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
++#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
++#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
++#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
++#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
++#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
++#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
++#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
++#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
++#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
++#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
++#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
++#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
++#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
++#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
++#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
++#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
++#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
++#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
++#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
++#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
++#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
++#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
++#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
++#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
++#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
++#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
++#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
++#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
++#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
++#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
++#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
++#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
++#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
++#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
++#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
++#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
++#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
++#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
++#define PSX81_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40
++#define PSX81_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6
++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
++#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
++#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
++#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
++#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
++#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
++#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
++#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
++#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
++#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
++#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
++#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
++#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
++#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
++#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
++#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
++#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
++#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
++#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
++#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
++#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
++#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
++#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
++#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
++#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
++#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
++#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
++#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
++#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
++#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
++#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
++#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
++#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
++#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
++#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
++#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
++#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
++#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
++#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
++#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
++#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
++#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
++#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
++#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
++#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
++#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
++#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
++#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
++#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
++#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
++#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
++#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
++#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
++#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
++#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
++#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
++#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
++#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
++#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
++#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
++#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
++#define PSX81_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000
++#define PSX81_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18
++#define PSX81_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e
++#define PSX81_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1
++#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
++#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
++#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0
++#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
++#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700
++#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
++#define PSX81_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff
++#define PSX81_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0
++#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
++#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100
++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
++#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
++#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
++#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
++#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
++#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100
++#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
++#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
++#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00
++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000
++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14
++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe
++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000
++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0
++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4
++#define PSX80_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe
++#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1
++#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800
++#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb
++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000
++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd
++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000
++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf
++#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000
++#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11
++#define PSX80_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000
++#define PSX80_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18
++#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000
++#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000
++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18
++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000
++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000
++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00
++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa
++#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20
++#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5
++#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0
++#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6
++#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300
++#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8
++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f
++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40
++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6
++#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70
++#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4
++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780
++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7
++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000
++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000
++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20
++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8
++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000
++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80
++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400
++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400
++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000
++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80
++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000
++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18
++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3
++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1
++#define PSX80_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0
++#define PSX80_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4
++#define PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
++#define PSX80_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10
++#define PSX80_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4
++#define PSX80_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100
++#define PSX80_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff
++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0
++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00
++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8
++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000
++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8
++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000
++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10
++#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800
++#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0
++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5
++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a
++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1
++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e
++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1
++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00
++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
++#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff
++#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000
++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14
++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe
++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000
++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0
++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4
++#define PSX81_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe
++#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1
++#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800
++#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb
++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000
++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd
++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000
++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf
++#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000
++#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11
++#define PSX81_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000
++#define PSX81_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18
++#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000
++#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000
++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18
++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000
++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000
++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00
++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa
++#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20
++#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5
++#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0
++#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6
++#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300
++#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8
++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f
++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40
++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6
++#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70
++#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4
++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780
++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7
++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000
++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000
++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20
++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8
++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000
++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80
++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400
++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400
++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000
++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000
++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80
++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000
++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18
++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3
++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1
++#define PSX81_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0
++#define PSX81_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4
++#define PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
++#define PSX81_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10
++#define PSX81_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4
++#define PSX81_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100
++#define PSX81_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff
++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0
++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00
++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8
++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000
++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8
++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000
++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10
++#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800
++#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0
++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5
++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a
++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1
++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e
++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1
++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00
++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
++#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff
++#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
++#define PSX80_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
++#define PSX80_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0
++#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
++#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
++#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
++#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
++#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
++#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
++#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
++#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
++#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
++#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
++#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
++#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
++#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
++#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
++#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
++#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
++#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
++#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
++#define PSX80_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0
++#define PSX80_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6
++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
++#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
++#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
++#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
++#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
++#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
++#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
++#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
++#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
++#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
++#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
++#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
++#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
++#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
++#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
++#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
++#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
++#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
++#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
++#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
++#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
++#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
++#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
++#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
++#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
++#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
++#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
++#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
++#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
++#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
++#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
++#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
++#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
++#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
++#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
++#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
++#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
++#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
++#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
++#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
++#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
++#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
++#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
++#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
++#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
++#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
++#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
++#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
++#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
++#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
++#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
++#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
++#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
++#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
++#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
++#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
++#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
++#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
++#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
++#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
++#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
++#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
++#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
++#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
++#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
++#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
++#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
++#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
++#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
++#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
++#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
++#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
++#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7
++#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
++#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18
++#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
++#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
++#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
++#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
++#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
++#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700
++#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
++#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
++#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
++#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000
++#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
++#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
++#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
++#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
++#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
++#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
++#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
++#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
++#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
++#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
++#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
++#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
++#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
++#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
++#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
++#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
++#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
++#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
++#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
++#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
++#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
++#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
++#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
++#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
++#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
++#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
++#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
++#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
++#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
++#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
++#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
++#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
++#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
++#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
++#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
++#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7
++#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
++#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18
++#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
++#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
++#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
++#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
++#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
++#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700
++#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
++#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
++#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
++#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000
++#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
++#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
++#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
++#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
++#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
++#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
++#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
++#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
++#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
++#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
++#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
++#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
++#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
++#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
++#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
++#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
++#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
++#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
++#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
++#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
++#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
++#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
++#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
++#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
++#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
++#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
++#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
++#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
++#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
++#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
++#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
++#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
++#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
++#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
++#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
++#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7
++#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
++#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18
++#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
++#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
++#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
++#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
++#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
++#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700
++#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
++#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
++#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
++#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000
++#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
++#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
++#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
++#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
++#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
++#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
++#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
++#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
++#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
++#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
++#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
++#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
++#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
++#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
++#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
++#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
++#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
++#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
++#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
++#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
++#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
++#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
++#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
++#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
++#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
++#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
++#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
++#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
++#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
++#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
++#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
++#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
++#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
++#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
++#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
++#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7
++#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
++#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18
++#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
++#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
++#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
++#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
++#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
++#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700
++#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
++#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
++#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
++#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000
++#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
++#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
++#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
++#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
++#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
++#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
++#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
++#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
++#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
++#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
++#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
++#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
++#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
++#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
++#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
++#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
++#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
++#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
++#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
++#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
++#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
++#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
++#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
++#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
++#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
++#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
++#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
++#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
++#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
++#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
++#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
++#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
++#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
++#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
++#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
++#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7
++#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
++#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18
++#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
++#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
++#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
++#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
++#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
++#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700
++#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
++#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
++#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
++#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000
++#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
++#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
++#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
++#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
++#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
++#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
++#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
++#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
++#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
++#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
++#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
++#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
++#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
++#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
++#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
++#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
++#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
++#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
++#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
++#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
++#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
++#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
++#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
++#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
++#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
++#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
++#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
++#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
++#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
++#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
++#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
++#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
++#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
++#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
++#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
++#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7
++#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
++#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18
++#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
++#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
++#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
++#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
++#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
++#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700
++#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
++#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
++#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
++#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000
++#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
++#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
++#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
++#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
++#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
++#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
++#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
++#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
++#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
++#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
++#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
++#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
++#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
++#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
++#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
++#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
++#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
++#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
++#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
++#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
++#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
++#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
++#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
++#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
++#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
++#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
++#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
++#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
++#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
++#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
++#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
++#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
++#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
++#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
++#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
++#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7
++#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
++#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18
++#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
++#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
++#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
++#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
++#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
++#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700
++#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
++#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
++#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
++#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000
++#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
++#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
++#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
++#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
++#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
++#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
++#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
++#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
++#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
++#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
++#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
++#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
++#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
++#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
++#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
++#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
++#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
++#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
++#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
++#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
++#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
++#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
++#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
++#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
++#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
++#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
++#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
++#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
++#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
++#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
++#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
++#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
++#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
++#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
++#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
++#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7
++#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
++#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18
++#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
++#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
++#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
++#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
++#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
++#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700
++#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
++#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
++#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
++#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000
++#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
++#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
++#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
++#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
++#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
++#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
++#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
++#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
++#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
++#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
++#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
++#define PSX81_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
++#define PSX81_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0
++#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
++#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
++#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
++#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
++#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
++#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
++#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
++#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
++#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
++#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
++#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
++#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
++#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
++#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
++#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
++#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
++#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
++#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
++#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
++#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
++#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
++#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
++#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
++#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
++#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
++#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
++#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
++#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
++#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
++#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
++#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
++#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
++#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
++#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
++#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
++#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
++#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
++#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
++#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
++#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
++#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
++#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
++#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
++#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
++#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
++#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
++#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
++#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
++#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
++#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
++#define PSX81_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0
++#define PSX81_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6
++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
++#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
++#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
++#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
++#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
++#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
++#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
++#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
++#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
++#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
++#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
++#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
++#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
++#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
++#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
++#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
++#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
++#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
++#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
++#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
++#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
++#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
++#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
++#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
++#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
++#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
++#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
++#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
++#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
++#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
++#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
++#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
++#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
++#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
++#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
++#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
++#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
++#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
++#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
++#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
++#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
++#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
++#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
++#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
++#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
++#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
++#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
++#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
++#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
++#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
++#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
++#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
++#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
++#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
++#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
++#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
++#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
++#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
++#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
++#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
++#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
++#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
++#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
++#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
++#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
++#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
++#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
++#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
++#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
++#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
++#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
++#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
++#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
++#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
++#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
++#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
++#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
++#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
++#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
++#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7
++#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
++#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18
++#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
++#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
++#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
++#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
++#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
++#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700
++#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
++#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
++#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
++#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000
++#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
++#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
++#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
++#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
++#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
++#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
++#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
++#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
++#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
++#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
++#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
++#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
++#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
++#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
++#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
++#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
++#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
++#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
++#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
++#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
++#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
++#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
++#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
++#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
++#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
++#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
++#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
++#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
++#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
++#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
++#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
++#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
++#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
++#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
++#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
++#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7
++#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
++#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18
++#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
++#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
++#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
++#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
++#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
++#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700
++#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
++#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
++#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
++#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000
++#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
++#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
++#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
++#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
++#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
++#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
++#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
++#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
++#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
++#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
++#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
++#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
++#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
++#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
++#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
++#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
++#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
++#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
++#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
++#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
++#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
++#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
++#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
++#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
++#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
++#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
++#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
++#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
++#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
++#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
++#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
++#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
++#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
++#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
++#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
++#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7
++#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
++#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18
++#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
++#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
++#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
++#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
++#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
++#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700
++#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
++#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
++#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
++#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000
++#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
++#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
++#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
++#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
++#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
++#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
++#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
++#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
++#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
++#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
++#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
++#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
++#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
++#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
++#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
++#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
++#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
++#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
++#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
++#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
++#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
++#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
++#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
++#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
++#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
++#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
++#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
++#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
++#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
++#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
++#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
++#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
++#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
++#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
++#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
++#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7
++#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
++#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18
++#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
++#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
++#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
++#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
++#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
++#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700
++#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
++#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
++#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
++#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000
++#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
++#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
++#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
++#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
++#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
++#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
++#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
++#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
++#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
++#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
++#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
++#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
++#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
++#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
++#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
++#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
++#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
++#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
++#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
++#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
++#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
++#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
++#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
++#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
++#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
++#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
++#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
++#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
++#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
++#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
++#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
++#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
++#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
++#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
++#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
++#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7
++#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
++#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18
++#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
++#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
++#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
++#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
++#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
++#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700
++#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
++#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
++#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
++#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000
++#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
++#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
++#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
++#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
++#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
++#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
++#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
++#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
++#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
++#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
++#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
++#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
++#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
++#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
++#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
++#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
++#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
++#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
++#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
++#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
++#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
++#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
++#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
++#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
++#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
++#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
++#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
++#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
++#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
++#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
++#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
++#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
++#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
++#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
++#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
++#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7
++#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
++#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18
++#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
++#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
++#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
++#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
++#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
++#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700
++#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
++#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
++#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
++#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000
++#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
++#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
++#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
++#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
++#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
++#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
++#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
++#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
++#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
++#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
++#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
++#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
++#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
++#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
++#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
++#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
++#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
++#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
++#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
++#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
++#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
++#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
++#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
++#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
++#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
++#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
++#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
++#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
++#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
++#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
++#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
++#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
++#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
++#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
++#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
++#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7
++#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
++#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18
++#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
++#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
++#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
++#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
++#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
++#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700
++#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
++#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
++#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
++#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000
++#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
++#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
++#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
++#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
++#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
++#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
++#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
++#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
++#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
++#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
++#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
++#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
++#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
++#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
++#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
++#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
++#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
++#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
++#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
++#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
++#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
++#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
++#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
++#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
++#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
++#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
++#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
++#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
++#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
++#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
++#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
++#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
++#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
++#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
++#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
++#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7
++#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
++#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18
++#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
++#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
++#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
++#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
++#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
++#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700
++#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
++#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
++#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
++#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000
++#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
++#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
++#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
++#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
++#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
++#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
++#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
++#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
++#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
++#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
++#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
++
++#endif /* BIF_5_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0004-yocto-amd-drm-amdgpu-Add-support-for-CIK-parts.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0004-yocto-amd-drm-amdgpu-Add-support-for-CIK-parts.patch
new file mode 100644
index 00000000..d915eadc
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0004-yocto-amd-drm-amdgpu-Add-support-for-CIK-parts.patch
@@ -0,0 +1,18838 @@
+From f45db8cbb934702e6495a55495fdf6fe4822c658 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:17:19 -0400
+Subject: drm/amdgpu: add DCE 8.0 register headers
+
+These are register headers for the DCE (Display and Composition Engine)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
+new file mode 100644
+index 0000000..dc52ea0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
+@@ -0,0 +1,5703 @@
++/*
++ * DCE_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_8_0_D_H
++#define DCE_8_0_D_H
++
++#define mmPIPE0_PG_CONFIG                                                       0x1760
++#define mmPIPE0_PG_ENABLE                                                       0x1761
++#define mmPIPE0_PG_STATUS                                                       0x1762
++#define mmPIPE1_PG_CONFIG                                                       0x1764
++#define mmPIPE1_PG_ENABLE                                                       0x1765
++#define mmPIPE1_PG_STATUS                                                       0x1766
++#define mmPIPE2_PG_CONFIG                                                       0x1768
++#define mmPIPE2_PG_ENABLE                                                       0x1769
++#define mmPIPE2_PG_STATUS                                                       0x176a
++#define mmPIPE3_PG_CONFIG                                                       0x176c
++#define mmPIPE3_PG_ENABLE                                                       0x176d
++#define mmPIPE3_PG_STATUS                                                       0x176e
++#define mmPIPE4_PG_CONFIG                                                       0x1770
++#define mmPIPE4_PG_ENABLE                                                       0x1771
++#define mmPIPE4_PG_STATUS                                                       0x1772
++#define mmPIPE5_PG_CONFIG                                                       0x1774
++#define mmPIPE5_PG_ENABLE                                                       0x1775
++#define mmPIPE5_PG_STATUS                                                       0x1776
++#define mmDC_IP_REQUEST_CNTL                                                    0x1778
++#define mmDC_PGFSM_CONFIG_REG                                                   0x177c
++#define mmDC_PGFSM_WRITE_REG                                                    0x177d
++#define mmDC_PGCNTL_STATUS_REG                                                  0x177e
++#define mmDCPG_TEST_DEBUG_INDEX                                                 0x1779
++#define mmDCPG_TEST_DEBUG_DATA                                                  0x177b
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                           0x1628
++#define mmBL1_PWM_USER_LEVEL                                                    0x1629
++#define mmBL1_PWM_TARGET_ABM_LEVEL                                              0x162a
++#define mmBL1_PWM_CURRENT_ABM_LEVEL                                             0x162b
++#define mmBL1_PWM_FINAL_DUTY_CYCLE                                              0x162c
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                            0x162d
++#define mmBL1_PWM_ABM_CNTL                                                      0x162e
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
++#define mmBL1_PWM_GRP2_REG_LOCK                                                 0x1630
++#define mmDC_ABM1_CNTL                                                          0x1638
++#define mmDC_ABM1_IPCSC_COEFF_SEL                                               0x1639
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                            0x163a
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                            0x163b
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                            0x163c
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                            0x163d
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                            0x163e
++#define mmDC_ABM1_ACE_THRES_12                                                  0x163f
++#define mmDC_ABM1_ACE_THRES_34                                                  0x1640
++#define mmDC_ABM1_ACE_CNTL_MISC                                                 0x1641
++#define mmDC_ABM1_DEBUG_MISC                                                    0x1649
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                        0x164a
++#define mmDC_ABM1_HG_MISC_CTRL                                                  0x164b
++#define mmDC_ABM1_LS_SUM_OF_LUMA                                                0x164c
++#define mmDC_ABM1_LS_MIN_MAX_LUMA                                               0x164d
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                      0x164e
++#define mmDC_ABM1_LS_PIXEL_COUNT                                                0x164f
++#define mmDC_ABM1_LS_OVR_SCAN_BIN                                               0x1650
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                  0x1651
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                      0x1652
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                      0x1653
++#define mmDC_ABM1_HG_SAMPLE_RATE                                                0x1654
++#define mmDC_ABM1_LS_SAMPLE_RATE                                                0x1655
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                        0x1656
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                        0x1657
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                       0x1658
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                      0x1659
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                      0x165a
++#define mmDC_ABM1_HG_RESULT_1                                                   0x165b
++#define mmDC_ABM1_HG_RESULT_2                                                   0x165c
++#define mmDC_ABM1_HG_RESULT_3                                                   0x165d
++#define mmDC_ABM1_HG_RESULT_4                                                   0x165e
++#define mmDC_ABM1_HG_RESULT_5                                                   0x165f
++#define mmDC_ABM1_HG_RESULT_6                                                   0x1660
++#define mmDC_ABM1_HG_RESULT_7                                                   0x1661
++#define mmDC_ABM1_HG_RESULT_8                                                   0x1662
++#define mmDC_ABM1_HG_RESULT_9                                                   0x1663
++#define mmDC_ABM1_HG_RESULT_10                                                  0x1664
++#define mmDC_ABM1_HG_RESULT_11                                                  0x1665
++#define mmDC_ABM1_HG_RESULT_12                                                  0x1666
++#define mmDC_ABM1_HG_RESULT_13                                                  0x1667
++#define mmDC_ABM1_HG_RESULT_14                                                  0x1668
++#define mmDC_ABM1_HG_RESULT_15                                                  0x1669
++#define mmDC_ABM1_HG_RESULT_16                                                  0x166a
++#define mmDC_ABM1_HG_RESULT_17                                                  0x166b
++#define mmDC_ABM1_HG_RESULT_18                                                  0x166c
++#define mmDC_ABM1_HG_RESULT_19                                                  0x166d
++#define mmDC_ABM1_HG_RESULT_20                                                  0x166e
++#define mmDC_ABM1_HG_RESULT_21                                                  0x166f
++#define mmDC_ABM1_HG_RESULT_22                                                  0x1670
++#define mmDC_ABM1_HG_RESULT_23                                                  0x1671
++#define mmDC_ABM1_HG_RESULT_24                                                  0x1672
++#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                          0x169b
++#define mmDC_ABM1_BL_MASTER_LOCK                                                0x169c
++#define mmABM_TEST_DEBUG_INDEX                                                  0x169e
++#define mmABM_TEST_DEBUG_DATA                                                   0x169f
++#define mmCRTC_DCFE_CLOCK_CONTROL                                               0x1b7c
++#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL                                         0x1b7c
++#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL                                         0x1e7c
++#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL                                         0x417c
++#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL                                         0x447c
++#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL                                         0x477c
++#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL                                         0x4a7c
++#define mmCRTC_H_BLANK_EARLY_NUM                                                0x1b7d
++#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                          0x1b7d
++#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                          0x1e7d
++#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                          0x417d
++#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                          0x447d
++#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                          0x477d
++#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                          0x4a7d
++#define mmDCFE_DBG_SEL                                                          0x1b7e
++#define mmCRTC0_DCFE_DBG_SEL                                                    0x1b7e
++#define mmCRTC1_DCFE_DBG_SEL                                                    0x1e7e
++#define mmCRTC2_DCFE_DBG_SEL                                                    0x417e
++#define mmCRTC3_DCFE_DBG_SEL                                                    0x447e
++#define mmCRTC4_DCFE_DBG_SEL                                                    0x477e
++#define mmCRTC5_DCFE_DBG_SEL                                                    0x4a7e
++#define mmDCFE_MEM_LIGHT_SLEEP_CNTL                                             0x1b7f
++#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x1b7f
++#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x1e7f
++#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x417f
++#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x447f
++#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x477f
++#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL                                       0x4a7f
++#define mmCRTC_H_TOTAL                                                          0x1b80
++#define mmCRTC0_CRTC_H_TOTAL                                                    0x1b80
++#define mmCRTC1_CRTC_H_TOTAL                                                    0x1e80
++#define mmCRTC2_CRTC_H_TOTAL                                                    0x4180
++#define mmCRTC3_CRTC_H_TOTAL                                                    0x4480
++#define mmCRTC4_CRTC_H_TOTAL                                                    0x4780
++#define mmCRTC5_CRTC_H_TOTAL                                                    0x4a80
++#define mmCRTC_H_BLANK_START_END                                                0x1b81
++#define mmCRTC0_CRTC_H_BLANK_START_END                                          0x1b81
++#define mmCRTC1_CRTC_H_BLANK_START_END                                          0x1e81
++#define mmCRTC2_CRTC_H_BLANK_START_END                                          0x4181
++#define mmCRTC3_CRTC_H_BLANK_START_END                                          0x4481
++#define mmCRTC4_CRTC_H_BLANK_START_END                                          0x4781
++#define mmCRTC5_CRTC_H_BLANK_START_END                                          0x4a81
++#define mmCRTC_H_SYNC_A                                                         0x1b82
++#define mmCRTC0_CRTC_H_SYNC_A                                                   0x1b82
++#define mmCRTC1_CRTC_H_SYNC_A                                                   0x1e82
++#define mmCRTC2_CRTC_H_SYNC_A                                                   0x4182
++#define mmCRTC3_CRTC_H_SYNC_A                                                   0x4482
++#define mmCRTC4_CRTC_H_SYNC_A                                                   0x4782
++#define mmCRTC5_CRTC_H_SYNC_A                                                   0x4a82
++#define mmCRTC_H_SYNC_A_CNTL                                                    0x1b83
++#define mmCRTC0_CRTC_H_SYNC_A_CNTL                                              0x1b83
++#define mmCRTC1_CRTC_H_SYNC_A_CNTL                                              0x1e83
++#define mmCRTC2_CRTC_H_SYNC_A_CNTL                                              0x4183
++#define mmCRTC3_CRTC_H_SYNC_A_CNTL                                              0x4483
++#define mmCRTC4_CRTC_H_SYNC_A_CNTL                                              0x4783
++#define mmCRTC5_CRTC_H_SYNC_A_CNTL                                              0x4a83
++#define mmCRTC_H_SYNC_B                                                         0x1b84
++#define mmCRTC0_CRTC_H_SYNC_B                                                   0x1b84
++#define mmCRTC1_CRTC_H_SYNC_B                                                   0x1e84
++#define mmCRTC2_CRTC_H_SYNC_B                                                   0x4184
++#define mmCRTC3_CRTC_H_SYNC_B                                                   0x4484
++#define mmCRTC4_CRTC_H_SYNC_B                                                   0x4784
++#define mmCRTC5_CRTC_H_SYNC_B                                                   0x4a84
++#define mmCRTC_H_SYNC_B_CNTL                                                    0x1b85
++#define mmCRTC0_CRTC_H_SYNC_B_CNTL                                              0x1b85
++#define mmCRTC1_CRTC_H_SYNC_B_CNTL                                              0x1e85
++#define mmCRTC2_CRTC_H_SYNC_B_CNTL                                              0x4185
++#define mmCRTC3_CRTC_H_SYNC_B_CNTL                                              0x4485
++#define mmCRTC4_CRTC_H_SYNC_B_CNTL                                              0x4785
++#define mmCRTC5_CRTC_H_SYNC_B_CNTL                                              0x4a85
++#define mmCRTC_VBI_END                                                          0x1b86
++#define mmCRTC0_CRTC_VBI_END                                                    0x1b86
++#define mmCRTC1_CRTC_VBI_END                                                    0x1e86
++#define mmCRTC2_CRTC_VBI_END                                                    0x4186
++#define mmCRTC3_CRTC_VBI_END                                                    0x4486
++#define mmCRTC4_CRTC_VBI_END                                                    0x4786
++#define mmCRTC5_CRTC_VBI_END                                                    0x4a86
++#define mmCRTC_V_TOTAL                                                          0x1b87
++#define mmCRTC0_CRTC_V_TOTAL                                                    0x1b87
++#define mmCRTC1_CRTC_V_TOTAL                                                    0x1e87
++#define mmCRTC2_CRTC_V_TOTAL                                                    0x4187
++#define mmCRTC3_CRTC_V_TOTAL                                                    0x4487
++#define mmCRTC4_CRTC_V_TOTAL                                                    0x4787
++#define mmCRTC5_CRTC_V_TOTAL                                                    0x4a87
++#define mmCRTC_V_TOTAL_MIN                                                      0x1b88
++#define mmCRTC0_CRTC_V_TOTAL_MIN                                                0x1b88
++#define mmCRTC1_CRTC_V_TOTAL_MIN                                                0x1e88
++#define mmCRTC2_CRTC_V_TOTAL_MIN                                                0x4188
++#define mmCRTC3_CRTC_V_TOTAL_MIN                                                0x4488
++#define mmCRTC4_CRTC_V_TOTAL_MIN                                                0x4788
++#define mmCRTC5_CRTC_V_TOTAL_MIN                                                0x4a88
++#define mmCRTC_V_TOTAL_MAX                                                      0x1b89
++#define mmCRTC0_CRTC_V_TOTAL_MAX                                                0x1b89
++#define mmCRTC1_CRTC_V_TOTAL_MAX                                                0x1e89
++#define mmCRTC2_CRTC_V_TOTAL_MAX                                                0x4189
++#define mmCRTC3_CRTC_V_TOTAL_MAX                                                0x4489
++#define mmCRTC4_CRTC_V_TOTAL_MAX                                                0x4789
++#define mmCRTC5_CRTC_V_TOTAL_MAX                                                0x4a89
++#define mmCRTC_V_TOTAL_CONTROL                                                  0x1b8a
++#define mmCRTC0_CRTC_V_TOTAL_CONTROL                                            0x1b8a
++#define mmCRTC1_CRTC_V_TOTAL_CONTROL                                            0x1e8a
++#define mmCRTC2_CRTC_V_TOTAL_CONTROL                                            0x418a
++#define mmCRTC3_CRTC_V_TOTAL_CONTROL                                            0x448a
++#define mmCRTC4_CRTC_V_TOTAL_CONTROL                                            0x478a
++#define mmCRTC5_CRTC_V_TOTAL_CONTROL                                            0x4a8a
++#define mmCRTC_V_TOTAL_INT_STATUS                                               0x1b8b
++#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                         0x1b8b
++#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                         0x1e8b
++#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                         0x418b
++#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                         0x448b
++#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                         0x478b
++#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                         0x4a8b
++#define mmCRTC_VSYNC_NOM_INT_STATUS                                             0x1b8c
++#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                       0x1b8c
++#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                       0x1e8c
++#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                       0x418c
++#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                       0x448c
++#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                       0x478c
++#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                       0x4a8c
++#define mmCRTC_V_BLANK_START_END                                                0x1b8d
++#define mmCRTC0_CRTC_V_BLANK_START_END                                          0x1b8d
++#define mmCRTC1_CRTC_V_BLANK_START_END                                          0x1e8d
++#define mmCRTC2_CRTC_V_BLANK_START_END                                          0x418d
++#define mmCRTC3_CRTC_V_BLANK_START_END                                          0x448d
++#define mmCRTC4_CRTC_V_BLANK_START_END                                          0x478d
++#define mmCRTC5_CRTC_V_BLANK_START_END                                          0x4a8d
++#define mmCRTC_V_SYNC_A                                                         0x1b8e
++#define mmCRTC0_CRTC_V_SYNC_A                                                   0x1b8e
++#define mmCRTC1_CRTC_V_SYNC_A                                                   0x1e8e
++#define mmCRTC2_CRTC_V_SYNC_A                                                   0x418e
++#define mmCRTC3_CRTC_V_SYNC_A                                                   0x448e
++#define mmCRTC4_CRTC_V_SYNC_A                                                   0x478e
++#define mmCRTC5_CRTC_V_SYNC_A                                                   0x4a8e
++#define mmCRTC_V_SYNC_A_CNTL                                                    0x1b8f
++#define mmCRTC0_CRTC_V_SYNC_A_CNTL                                              0x1b8f
++#define mmCRTC1_CRTC_V_SYNC_A_CNTL                                              0x1e8f
++#define mmCRTC2_CRTC_V_SYNC_A_CNTL                                              0x418f
++#define mmCRTC3_CRTC_V_SYNC_A_CNTL                                              0x448f
++#define mmCRTC4_CRTC_V_SYNC_A_CNTL                                              0x478f
++#define mmCRTC5_CRTC_V_SYNC_A_CNTL                                              0x4a8f
++#define mmCRTC_V_SYNC_B                                                         0x1b90
++#define mmCRTC0_CRTC_V_SYNC_B                                                   0x1b90
++#define mmCRTC1_CRTC_V_SYNC_B                                                   0x1e90
++#define mmCRTC2_CRTC_V_SYNC_B                                                   0x4190
++#define mmCRTC3_CRTC_V_SYNC_B                                                   0x4490
++#define mmCRTC4_CRTC_V_SYNC_B                                                   0x4790
++#define mmCRTC5_CRTC_V_SYNC_B                                                   0x4a90
++#define mmCRTC_V_SYNC_B_CNTL                                                    0x1b91
++#define mmCRTC0_CRTC_V_SYNC_B_CNTL                                              0x1b91
++#define mmCRTC1_CRTC_V_SYNC_B_CNTL                                              0x1e91
++#define mmCRTC2_CRTC_V_SYNC_B_CNTL                                              0x4191
++#define mmCRTC3_CRTC_V_SYNC_B_CNTL                                              0x4491
++#define mmCRTC4_CRTC_V_SYNC_B_CNTL                                              0x4791
++#define mmCRTC5_CRTC_V_SYNC_B_CNTL                                              0x4a91
++#define mmCRTC_DTMTEST_CNTL                                                     0x1b92
++#define mmCRTC0_CRTC_DTMTEST_CNTL                                               0x1b92
++#define mmCRTC1_CRTC_DTMTEST_CNTL                                               0x1e92
++#define mmCRTC2_CRTC_DTMTEST_CNTL                                               0x4192
++#define mmCRTC3_CRTC_DTMTEST_CNTL                                               0x4492
++#define mmCRTC4_CRTC_DTMTEST_CNTL                                               0x4792
++#define mmCRTC5_CRTC_DTMTEST_CNTL                                               0x4a92
++#define mmCRTC_DTMTEST_STATUS_POSITION                                          0x1b93
++#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                    0x1b93
++#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                    0x1e93
++#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                    0x4193
++#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                    0x4493
++#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                    0x4793
++#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                    0x4a93
++#define mmCRTC_TRIGA_CNTL                                                       0x1b94
++#define mmCRTC0_CRTC_TRIGA_CNTL                                                 0x1b94
++#define mmCRTC1_CRTC_TRIGA_CNTL                                                 0x1e94
++#define mmCRTC2_CRTC_TRIGA_CNTL                                                 0x4194
++#define mmCRTC3_CRTC_TRIGA_CNTL                                                 0x4494
++#define mmCRTC4_CRTC_TRIGA_CNTL                                                 0x4794
++#define mmCRTC5_CRTC_TRIGA_CNTL                                                 0x4a94
++#define mmCRTC_TRIGA_MANUAL_TRIG                                                0x1b95
++#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                          0x1b95
++#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                          0x1e95
++#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                          0x4195
++#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                          0x4495
++#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                          0x4795
++#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                          0x4a95
++#define mmCRTC_TRIGB_CNTL                                                       0x1b96
++#define mmCRTC0_CRTC_TRIGB_CNTL                                                 0x1b96
++#define mmCRTC1_CRTC_TRIGB_CNTL                                                 0x1e96
++#define mmCRTC2_CRTC_TRIGB_CNTL                                                 0x4196
++#define mmCRTC3_CRTC_TRIGB_CNTL                                                 0x4496
++#define mmCRTC4_CRTC_TRIGB_CNTL                                                 0x4796
++#define mmCRTC5_CRTC_TRIGB_CNTL                                                 0x4a96
++#define mmCRTC_TRIGB_MANUAL_TRIG                                                0x1b97
++#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                          0x1b97
++#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                          0x1e97
++#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                          0x4197
++#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                          0x4497
++#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                          0x4797
++#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                          0x4a97
++#define mmCRTC_FORCE_COUNT_NOW_CNTL                                             0x1b98
++#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1b98
++#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1e98
++#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4198
++#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4498
++#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4798
++#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4a98
++#define mmCRTC_FLOW_CONTROL                                                     0x1b99
++#define mmCRTC0_CRTC_FLOW_CONTROL                                               0x1b99
++#define mmCRTC1_CRTC_FLOW_CONTROL                                               0x1e99
++#define mmCRTC2_CRTC_FLOW_CONTROL                                               0x4199
++#define mmCRTC3_CRTC_FLOW_CONTROL                                               0x4499
++#define mmCRTC4_CRTC_FLOW_CONTROL                                               0x4799
++#define mmCRTC5_CRTC_FLOW_CONTROL                                               0x4a99
++#define mmCRTC_STEREO_FORCE_NEXT_EYE                                            0x1b9b
++#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1b9b
++#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1e9b
++#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                      0x419b
++#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                      0x449b
++#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                      0x479b
++#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                      0x4a9b
++#define mmCRTC_CONTROL                                                          0x1b9c
++#define mmCRTC0_CRTC_CONTROL                                                    0x1b9c
++#define mmCRTC1_CRTC_CONTROL                                                    0x1e9c
++#define mmCRTC2_CRTC_CONTROL                                                    0x419c
++#define mmCRTC3_CRTC_CONTROL                                                    0x449c
++#define mmCRTC4_CRTC_CONTROL                                                    0x479c
++#define mmCRTC5_CRTC_CONTROL                                                    0x4a9c
++#define mmCRTC_BLANK_CONTROL                                                    0x1b9d
++#define mmCRTC0_CRTC_BLANK_CONTROL                                              0x1b9d
++#define mmCRTC1_CRTC_BLANK_CONTROL                                              0x1e9d
++#define mmCRTC2_CRTC_BLANK_CONTROL                                              0x419d
++#define mmCRTC3_CRTC_BLANK_CONTROL                                              0x449d
++#define mmCRTC4_CRTC_BLANK_CONTROL                                              0x479d
++#define mmCRTC5_CRTC_BLANK_CONTROL                                              0x4a9d
++#define mmCRTC_INTERLACE_CONTROL                                                0x1b9e
++#define mmCRTC0_CRTC_INTERLACE_CONTROL                                          0x1b9e
++#define mmCRTC1_CRTC_INTERLACE_CONTROL                                          0x1e9e
++#define mmCRTC2_CRTC_INTERLACE_CONTROL                                          0x419e
++#define mmCRTC3_CRTC_INTERLACE_CONTROL                                          0x449e
++#define mmCRTC4_CRTC_INTERLACE_CONTROL                                          0x479e
++#define mmCRTC5_CRTC_INTERLACE_CONTROL                                          0x4a9e
++#define mmCRTC_INTERLACE_STATUS                                                 0x1b9f
++#define mmCRTC0_CRTC_INTERLACE_STATUS                                           0x1b9f
++#define mmCRTC1_CRTC_INTERLACE_STATUS                                           0x1e9f
++#define mmCRTC2_CRTC_INTERLACE_STATUS                                           0x419f
++#define mmCRTC3_CRTC_INTERLACE_STATUS                                           0x449f
++#define mmCRTC4_CRTC_INTERLACE_STATUS                                           0x479f
++#define mmCRTC5_CRTC_INTERLACE_STATUS                                           0x4a9f
++#define mmCRTC_FIELD_INDICATION_CONTROL                                         0x1ba0
++#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                   0x1ba0
++#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                   0x1ea0
++#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                   0x41a0
++#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                   0x44a0
++#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                   0x47a0
++#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                   0x4aa0
++#define mmCRTC_PIXEL_DATA_READBACK0                                             0x1ba1
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                       0x1ba1
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                       0x1ea1
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                       0x41a1
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                       0x44a1
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                       0x47a1
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                       0x4aa1
++#define mmCRTC_PIXEL_DATA_READBACK1                                             0x1ba2
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                       0x1ba2
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                       0x1ea2
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                       0x41a2
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                       0x44a2
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                       0x47a2
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                       0x4aa2
++#define mmCRTC_STATUS                                                           0x1ba3
++#define mmCRTC0_CRTC_STATUS                                                     0x1ba3
++#define mmCRTC1_CRTC_STATUS                                                     0x1ea3
++#define mmCRTC2_CRTC_STATUS                                                     0x41a3
++#define mmCRTC3_CRTC_STATUS                                                     0x44a3
++#define mmCRTC4_CRTC_STATUS                                                     0x47a3
++#define mmCRTC5_CRTC_STATUS                                                     0x4aa3
++#define mmCRTC_STATUS_POSITION                                                  0x1ba4
++#define mmCRTC0_CRTC_STATUS_POSITION                                            0x1ba4
++#define mmCRTC1_CRTC_STATUS_POSITION                                            0x1ea4
++#define mmCRTC2_CRTC_STATUS_POSITION                                            0x41a4
++#define mmCRTC3_CRTC_STATUS_POSITION                                            0x44a4
++#define mmCRTC4_CRTC_STATUS_POSITION                                            0x47a4
++#define mmCRTC5_CRTC_STATUS_POSITION                                            0x4aa4
++#define mmCRTC_NOM_VERT_POSITION                                                0x1ba5
++#define mmCRTC0_CRTC_NOM_VERT_POSITION                                          0x1ba5
++#define mmCRTC1_CRTC_NOM_VERT_POSITION                                          0x1ea5
++#define mmCRTC2_CRTC_NOM_VERT_POSITION                                          0x41a5
++#define mmCRTC3_CRTC_NOM_VERT_POSITION                                          0x44a5
++#define mmCRTC4_CRTC_NOM_VERT_POSITION                                          0x47a5
++#define mmCRTC5_CRTC_NOM_VERT_POSITION                                          0x4aa5
++#define mmCRTC_STATUS_FRAME_COUNT                                               0x1ba6
++#define mmCRTC0_CRTC_STATUS_FRAME_COUNT                                         0x1ba6
++#define mmCRTC1_CRTC_STATUS_FRAME_COUNT                                         0x1ea6
++#define mmCRTC2_CRTC_STATUS_FRAME_COUNT                                         0x41a6
++#define mmCRTC3_CRTC_STATUS_FRAME_COUNT                                         0x44a6
++#define mmCRTC4_CRTC_STATUS_FRAME_COUNT                                         0x47a6
++#define mmCRTC5_CRTC_STATUS_FRAME_COUNT                                         0x4aa6
++#define mmCRTC_STATUS_VF_COUNT                                                  0x1ba7
++#define mmCRTC0_CRTC_STATUS_VF_COUNT                                            0x1ba7
++#define mmCRTC1_CRTC_STATUS_VF_COUNT                                            0x1ea7
++#define mmCRTC2_CRTC_STATUS_VF_COUNT                                            0x41a7
++#define mmCRTC3_CRTC_STATUS_VF_COUNT                                            0x44a7
++#define mmCRTC4_CRTC_STATUS_VF_COUNT                                            0x47a7
++#define mmCRTC5_CRTC_STATUS_VF_COUNT                                            0x4aa7
++#define mmCRTC_STATUS_HV_COUNT                                                  0x1ba8
++#define mmCRTC0_CRTC_STATUS_HV_COUNT                                            0x1ba8
++#define mmCRTC1_CRTC_STATUS_HV_COUNT                                            0x1ea8
++#define mmCRTC2_CRTC_STATUS_HV_COUNT                                            0x41a8
++#define mmCRTC3_CRTC_STATUS_HV_COUNT                                            0x44a8
++#define mmCRTC4_CRTC_STATUS_HV_COUNT                                            0x47a8
++#define mmCRTC5_CRTC_STATUS_HV_COUNT                                            0x4aa8
++#define mmCRTC_COUNT_CONTROL                                                    0x1ba9
++#define mmCRTC0_CRTC_COUNT_CONTROL                                              0x1ba9
++#define mmCRTC1_CRTC_COUNT_CONTROL                                              0x1ea9
++#define mmCRTC2_CRTC_COUNT_CONTROL                                              0x41a9
++#define mmCRTC3_CRTC_COUNT_CONTROL                                              0x44a9
++#define mmCRTC4_CRTC_COUNT_CONTROL                                              0x47a9
++#define mmCRTC5_CRTC_COUNT_CONTROL                                              0x4aa9
++#define mmCRTC_COUNT_RESET                                                      0x1baa
++#define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
++#define mmCRTC1_CRTC_COUNT_RESET                                                0x1eaa
++#define mmCRTC2_CRTC_COUNT_RESET                                                0x41aa
++#define mmCRTC3_CRTC_COUNT_RESET                                                0x44aa
++#define mmCRTC4_CRTC_COUNT_RESET                                                0x47aa
++#define mmCRTC5_CRTC_COUNT_RESET                                                0x4aaa
++#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                     0x1bab
++#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1bab
++#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1eab
++#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x41ab
++#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x44ab
++#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x47ab
++#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x4aab
++#define mmCRTC_VERT_SYNC_CONTROL                                                0x1bac
++#define mmCRTC0_CRTC_VERT_SYNC_CONTROL                                          0x1bac
++#define mmCRTC1_CRTC_VERT_SYNC_CONTROL                                          0x1eac
++#define mmCRTC2_CRTC_VERT_SYNC_CONTROL                                          0x41ac
++#define mmCRTC3_CRTC_VERT_SYNC_CONTROL                                          0x44ac
++#define mmCRTC4_CRTC_VERT_SYNC_CONTROL                                          0x47ac
++#define mmCRTC5_CRTC_VERT_SYNC_CONTROL                                          0x4aac
++#define mmCRTC_STEREO_STATUS                                                    0x1bad
++#define mmCRTC0_CRTC_STEREO_STATUS                                              0x1bad
++#define mmCRTC1_CRTC_STEREO_STATUS                                              0x1ead
++#define mmCRTC2_CRTC_STEREO_STATUS                                              0x41ad
++#define mmCRTC3_CRTC_STEREO_STATUS                                              0x44ad
++#define mmCRTC4_CRTC_STEREO_STATUS                                              0x47ad
++#define mmCRTC5_CRTC_STEREO_STATUS                                              0x4aad
++#define mmCRTC_STEREO_CONTROL                                                   0x1bae
++#define mmCRTC0_CRTC_STEREO_CONTROL                                             0x1bae
++#define mmCRTC1_CRTC_STEREO_CONTROL                                             0x1eae
++#define mmCRTC2_CRTC_STEREO_CONTROL                                             0x41ae
++#define mmCRTC3_CRTC_STEREO_CONTROL                                             0x44ae
++#define mmCRTC4_CRTC_STEREO_CONTROL                                             0x47ae
++#define mmCRTC5_CRTC_STEREO_CONTROL                                             0x4aae
++#define mmCRTC_SNAPSHOT_STATUS                                                  0x1baf
++#define mmCRTC0_CRTC_SNAPSHOT_STATUS                                            0x1baf
++#define mmCRTC1_CRTC_SNAPSHOT_STATUS                                            0x1eaf
++#define mmCRTC2_CRTC_SNAPSHOT_STATUS                                            0x41af
++#define mmCRTC3_CRTC_SNAPSHOT_STATUS                                            0x44af
++#define mmCRTC4_CRTC_SNAPSHOT_STATUS                                            0x47af
++#define mmCRTC5_CRTC_SNAPSHOT_STATUS                                            0x4aaf
++#define mmCRTC_SNAPSHOT_CONTROL                                                 0x1bb0
++#define mmCRTC0_CRTC_SNAPSHOT_CONTROL                                           0x1bb0
++#define mmCRTC1_CRTC_SNAPSHOT_CONTROL                                           0x1eb0
++#define mmCRTC2_CRTC_SNAPSHOT_CONTROL                                           0x41b0
++#define mmCRTC3_CRTC_SNAPSHOT_CONTROL                                           0x44b0
++#define mmCRTC4_CRTC_SNAPSHOT_CONTROL                                           0x47b0
++#define mmCRTC5_CRTC_SNAPSHOT_CONTROL                                           0x4ab0
++#define mmCRTC_SNAPSHOT_POSITION                                                0x1bb1
++#define mmCRTC0_CRTC_SNAPSHOT_POSITION                                          0x1bb1
++#define mmCRTC1_CRTC_SNAPSHOT_POSITION                                          0x1eb1
++#define mmCRTC2_CRTC_SNAPSHOT_POSITION                                          0x41b1
++#define mmCRTC3_CRTC_SNAPSHOT_POSITION                                          0x44b1
++#define mmCRTC4_CRTC_SNAPSHOT_POSITION                                          0x47b1
++#define mmCRTC5_CRTC_SNAPSHOT_POSITION                                          0x4ab1
++#define mmCRTC_SNAPSHOT_FRAME                                                   0x1bb2
++#define mmCRTC0_CRTC_SNAPSHOT_FRAME                                             0x1bb2
++#define mmCRTC1_CRTC_SNAPSHOT_FRAME                                             0x1eb2
++#define mmCRTC2_CRTC_SNAPSHOT_FRAME                                             0x41b2
++#define mmCRTC3_CRTC_SNAPSHOT_FRAME                                             0x44b2
++#define mmCRTC4_CRTC_SNAPSHOT_FRAME                                             0x47b2
++#define mmCRTC5_CRTC_SNAPSHOT_FRAME                                             0x4ab2
++#define mmCRTC_START_LINE_CONTROL                                               0x1bb3
++#define mmCRTC0_CRTC_START_LINE_CONTROL                                         0x1bb3
++#define mmCRTC1_CRTC_START_LINE_CONTROL                                         0x1eb3
++#define mmCRTC2_CRTC_START_LINE_CONTROL                                         0x41b3
++#define mmCRTC3_CRTC_START_LINE_CONTROL                                         0x44b3
++#define mmCRTC4_CRTC_START_LINE_CONTROL                                         0x47b3
++#define mmCRTC5_CRTC_START_LINE_CONTROL                                         0x4ab3
++#define mmCRTC_INTERRUPT_CONTROL                                                0x1bb4
++#define mmCRTC0_CRTC_INTERRUPT_CONTROL                                          0x1bb4
++#define mmCRTC1_CRTC_INTERRUPT_CONTROL                                          0x1eb4
++#define mmCRTC2_CRTC_INTERRUPT_CONTROL                                          0x41b4
++#define mmCRTC3_CRTC_INTERRUPT_CONTROL                                          0x44b4
++#define mmCRTC4_CRTC_INTERRUPT_CONTROL                                          0x47b4
++#define mmCRTC5_CRTC_INTERRUPT_CONTROL                                          0x4ab4
++#define mmCRTC_UPDATE_LOCK                                                      0x1bb5
++#define mmCRTC0_CRTC_UPDATE_LOCK                                                0x1bb5
++#define mmCRTC1_CRTC_UPDATE_LOCK                                                0x1eb5
++#define mmCRTC2_CRTC_UPDATE_LOCK                                                0x41b5
++#define mmCRTC3_CRTC_UPDATE_LOCK                                                0x44b5
++#define mmCRTC4_CRTC_UPDATE_LOCK                                                0x47b5
++#define mmCRTC5_CRTC_UPDATE_LOCK                                                0x4ab5
++#define mmCRTC_DOUBLE_BUFFER_CONTROL                                            0x1bb6
++#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1bb6
++#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1eb6
++#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                      0x41b6
++#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                      0x44b6
++#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                      0x47b6
++#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                      0x4ab6
++#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE                                       0x1bb7
++#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1bb7
++#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1eb7
++#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x41b7
++#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x44b7
++#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x47b7
++#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x4ab7
++#define mmCRTC_TEST_PATTERN_CONTROL                                             0x1bba
++#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                       0x1bba
++#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                       0x1eba
++#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                       0x41ba
++#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                       0x44ba
++#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                       0x47ba
++#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                       0x4aba
++#define mmCRTC_TEST_PATTERN_PARAMETERS                                          0x1bbb
++#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                    0x1bbb
++#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                    0x1ebb
++#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                    0x41bb
++#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                    0x44bb
++#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                    0x47bb
++#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                    0x4abb
++#define mmCRTC_TEST_PATTERN_COLOR                                               0x1bbc
++#define mmCRTC0_CRTC_TEST_PATTERN_COLOR                                         0x1bbc
++#define mmCRTC1_CRTC_TEST_PATTERN_COLOR                                         0x1ebc
++#define mmCRTC2_CRTC_TEST_PATTERN_COLOR                                         0x41bc
++#define mmCRTC3_CRTC_TEST_PATTERN_COLOR                                         0x44bc
++#define mmCRTC4_CRTC_TEST_PATTERN_COLOR                                         0x47bc
++#define mmCRTC5_CRTC_TEST_PATTERN_COLOR                                         0x4abc
++#define mmMASTER_UPDATE_LOCK                                                    0x1bbd
++#define mmCRTC0_MASTER_UPDATE_LOCK                                              0x1bbd
++#define mmCRTC1_MASTER_UPDATE_LOCK                                              0x1ebd
++#define mmCRTC2_MASTER_UPDATE_LOCK                                              0x41bd
++#define mmCRTC3_MASTER_UPDATE_LOCK                                              0x44bd
++#define mmCRTC4_MASTER_UPDATE_LOCK                                              0x47bd
++#define mmCRTC5_MASTER_UPDATE_LOCK                                              0x4abd
++#define mmMASTER_UPDATE_MODE                                                    0x1bbe
++#define mmCRTC0_MASTER_UPDATE_MODE                                              0x1bbe
++#define mmCRTC1_MASTER_UPDATE_MODE                                              0x1ebe
++#define mmCRTC2_MASTER_UPDATE_MODE                                              0x41be
++#define mmCRTC3_MASTER_UPDATE_MODE                                              0x44be
++#define mmCRTC4_MASTER_UPDATE_MODE                                              0x47be
++#define mmCRTC5_MASTER_UPDATE_MODE                                              0x4abe
++#define mmCRTC_MVP_INBAND_CNTL_INSERT                                           0x1bbf
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1bbf
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1ebf
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                     0x41bf
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                     0x44bf
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                     0x47bf
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                     0x4abf
++#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER                                     0x1bc0
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1bc0
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1ec0
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x41c0
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x44c0
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x47c0
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x4ac0
++#define mmCRTC_MVP_STATUS                                                       0x1bc1
++#define mmCRTC0_CRTC_MVP_STATUS                                                 0x1bc1
++#define mmCRTC1_CRTC_MVP_STATUS                                                 0x1ec1
++#define mmCRTC2_CRTC_MVP_STATUS                                                 0x41c1
++#define mmCRTC3_CRTC_MVP_STATUS                                                 0x44c1
++#define mmCRTC4_CRTC_MVP_STATUS                                                 0x47c1
++#define mmCRTC5_CRTC_MVP_STATUS                                                 0x4ac1
++#define mmCRTC_MASTER_EN                                                        0x1bc2
++#define mmCRTC0_CRTC_MASTER_EN                                                  0x1bc2
++#define mmCRTC1_CRTC_MASTER_EN                                                  0x1ec2
++#define mmCRTC2_CRTC_MASTER_EN                                                  0x41c2
++#define mmCRTC3_CRTC_MASTER_EN                                                  0x44c2
++#define mmCRTC4_CRTC_MASTER_EN                                                  0x47c2
++#define mmCRTC5_CRTC_MASTER_EN                                                  0x4ac2
++#define mmCRTC_ALLOW_STOP_OFF_V_CNT                                             0x1bc3
++#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1bc3
++#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1ec3
++#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x41c3
++#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x44c3
++#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x47c3
++#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x4ac3
++#define mmCRTC_V_UPDATE_INT_STATUS                                              0x1bc4
++#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                        0x1bc4
++#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                        0x1ec4
++#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                        0x41c4
++#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                        0x44c4
++#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                        0x47c4
++#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                        0x4ac4
++#define mmCRTC_OVERSCAN_COLOR                                                   0x1bc8
++#define mmCRTC0_CRTC_OVERSCAN_COLOR                                             0x1bc8
++#define mmCRTC1_CRTC_OVERSCAN_COLOR                                             0x1ec8
++#define mmCRTC2_CRTC_OVERSCAN_COLOR                                             0x41c8
++#define mmCRTC3_CRTC_OVERSCAN_COLOR                                             0x44c8
++#define mmCRTC4_CRTC_OVERSCAN_COLOR                                             0x47c8
++#define mmCRTC5_CRTC_OVERSCAN_COLOR                                             0x4ac8
++#define mmCRTC_OVERSCAN_COLOR_EXT                                               0x1bc9
++#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                         0x1bc9
++#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                         0x1ec9
++#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                         0x41c9
++#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                         0x44c9
++#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                         0x47c9
++#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                         0x4ac9
++#define mmCRTC_BLANK_DATA_COLOR                                                 0x1bca
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR                                           0x1bca
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR                                           0x1eca
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR                                           0x41ca
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR                                           0x44ca
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR                                           0x47ca
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR                                           0x4aca
++#define mmCRTC_BLANK_DATA_COLOR_EXT                                             0x1bcb
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                       0x1bcb
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                       0x1ecb
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                       0x41cb
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                       0x44cb
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                       0x47cb
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                       0x4acb
++#define mmCRTC_BLACK_COLOR                                                      0x1bcc
++#define mmCRTC0_CRTC_BLACK_COLOR                                                0x1bcc
++#define mmCRTC1_CRTC_BLACK_COLOR                                                0x1ecc
++#define mmCRTC2_CRTC_BLACK_COLOR                                                0x41cc
++#define mmCRTC3_CRTC_BLACK_COLOR                                                0x44cc
++#define mmCRTC4_CRTC_BLACK_COLOR                                                0x47cc
++#define mmCRTC5_CRTC_BLACK_COLOR                                                0x4acc
++#define mmCRTC_BLACK_COLOR_EXT                                                  0x1bcd
++#define mmCRTC0_CRTC_BLACK_COLOR_EXT                                            0x1bcd
++#define mmCRTC1_CRTC_BLACK_COLOR_EXT                                            0x1ecd
++#define mmCRTC2_CRTC_BLACK_COLOR_EXT                                            0x41cd
++#define mmCRTC3_CRTC_BLACK_COLOR_EXT                                            0x44cd
++#define mmCRTC4_CRTC_BLACK_COLOR_EXT                                            0x47cd
++#define mmCRTC5_CRTC_BLACK_COLOR_EXT                                            0x4acd
++#define mmCRTC_VERTICAL_INTERRUPT0_POSITION                                     0x1bce
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1bce
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1ece
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x41ce
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x44ce
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x47ce
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x4ace
++#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL                                      0x1bcf
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1bcf
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1ecf
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x41cf
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x44cf
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x47cf
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x4acf
++#define mmCRTC_VERTICAL_INTERRUPT1_POSITION                                     0x1bd0
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1bd0
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1ed0
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x41d0
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x44d0
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x47d0
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x4ad0
++#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL                                      0x1bd1
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1bd1
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1ed1
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x41d1
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x44d1
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x47d1
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x4ad1
++#define mmCRTC_VERTICAL_INTERRUPT2_POSITION                                     0x1bd2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1bd2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1ed2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x41d2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x44d2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x47d2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x4ad2
++#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL                                      0x1bd3
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1bd3
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1ed3
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x41d3
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x44d3
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x47d3
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x4ad3
++#define mmCRTC_CRC_CNTL                                                         0x1bd4
++#define mmCRTC0_CRTC_CRC_CNTL                                                   0x1bd4
++#define mmCRTC1_CRTC_CRC_CNTL                                                   0x1ed4
++#define mmCRTC2_CRTC_CRC_CNTL                                                   0x41d4
++#define mmCRTC3_CRTC_CRC_CNTL                                                   0x44d4
++#define mmCRTC4_CRTC_CRC_CNTL                                                   0x47d4
++#define mmCRTC5_CRTC_CRC_CNTL                                                   0x4ad4
++#define mmCRTC_CRC0_WINDOWA_X_CONTROL                                           0x1bd5
++#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1bd5
++#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1ed5
++#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x41d5
++#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x44d5
++#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x47d5
++#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x4ad5
++#define mmCRTC_CRC0_WINDOWA_Y_CONTROL                                           0x1bd6
++#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1bd6
++#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1ed6
++#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x41d6
++#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x44d6
++#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x47d6
++#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x4ad6
++#define mmCRTC_CRC0_WINDOWB_X_CONTROL                                           0x1bd7
++#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1bd7
++#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1ed7
++#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x41d7
++#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x44d7
++#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x47d7
++#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x4ad7
++#define mmCRTC_CRC0_WINDOWB_Y_CONTROL                                           0x1bd8
++#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1bd8
++#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1ed8
++#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x41d8
++#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x44d8
++#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x47d8
++#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x4ad8
++#define mmCRTC_CRC0_DATA_RG                                                     0x1bd9
++#define mmCRTC0_CRTC_CRC0_DATA_RG                                               0x1bd9
++#define mmCRTC1_CRTC_CRC0_DATA_RG                                               0x1ed9
++#define mmCRTC2_CRTC_CRC0_DATA_RG                                               0x41d9
++#define mmCRTC3_CRTC_CRC0_DATA_RG                                               0x44d9
++#define mmCRTC4_CRTC_CRC0_DATA_RG                                               0x47d9
++#define mmCRTC5_CRTC_CRC0_DATA_RG                                               0x4ad9
++#define mmCRTC_CRC0_DATA_B                                                      0x1bda
++#define mmCRTC0_CRTC_CRC0_DATA_B                                                0x1bda
++#define mmCRTC1_CRTC_CRC0_DATA_B                                                0x1eda
++#define mmCRTC2_CRTC_CRC0_DATA_B                                                0x41da
++#define mmCRTC3_CRTC_CRC0_DATA_B                                                0x44da
++#define mmCRTC4_CRTC_CRC0_DATA_B                                                0x47da
++#define mmCRTC5_CRTC_CRC0_DATA_B                                                0x4ada
++#define mmCRTC_CRC1_WINDOWA_X_CONTROL                                           0x1bdb
++#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1bdb
++#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1edb
++#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x41db
++#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x44db
++#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x47db
++#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x4adb
++#define mmCRTC_CRC1_WINDOWA_Y_CONTROL                                           0x1bdc
++#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1bdc
++#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1edc
++#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x41dc
++#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x44dc
++#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x47dc
++#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x4adc
++#define mmCRTC_CRC1_WINDOWB_X_CONTROL                                           0x1bdd
++#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1bdd
++#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1edd
++#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x41dd
++#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x44dd
++#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x47dd
++#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x4add
++#define mmCRTC_CRC1_WINDOWB_Y_CONTROL                                           0x1bde
++#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1bde
++#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1ede
++#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x41de
++#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x44de
++#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x47de
++#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x4ade
++#define mmCRTC_CRC1_DATA_RG                                                     0x1bdf
++#define mmCRTC0_CRTC_CRC1_DATA_RG                                               0x1bdf
++#define mmCRTC1_CRTC_CRC1_DATA_RG                                               0x1edf
++#define mmCRTC2_CRTC_CRC1_DATA_RG                                               0x41df
++#define mmCRTC3_CRTC_CRC1_DATA_RG                                               0x44df
++#define mmCRTC4_CRTC_CRC1_DATA_RG                                               0x47df
++#define mmCRTC5_CRTC_CRC1_DATA_RG                                               0x4adf
++#define mmCRTC_CRC1_DATA_B                                                      0x1be0
++#define mmCRTC0_CRTC_CRC1_DATA_B                                                0x1be0
++#define mmCRTC1_CRTC_CRC1_DATA_B                                                0x1ee0
++#define mmCRTC2_CRTC_CRC1_DATA_B                                                0x41e0
++#define mmCRTC3_CRTC_CRC1_DATA_B                                                0x44e0
++#define mmCRTC4_CRTC_CRC1_DATA_B                                                0x47e0
++#define mmCRTC5_CRTC_CRC1_DATA_B                                                0x4ae0
++#define mmCRTC_EXT_TIMING_SYNC_CONTROL                                          0x1be1
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1be1
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1ee1
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x41e1
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x44e1
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x47e1
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x4ae1
++#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START                                     0x1be2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1be2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1ee2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x41e2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x44e2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x47e2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x4ae2
++#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END                                       0x1be3
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1be3
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1ee3
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x41e3
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x44e3
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x47e3
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x4ae3
++#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                           0x1be4
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1be4
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1ee4
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x41e4
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x44e4
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x47e4
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x4ae4
++#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                0x1be5
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1be5
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1ee5
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x41e5
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x44e5
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x47e5
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x4ae5
++#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                         0x1be6
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1be6
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1ee6
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x41e6
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x44e6
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x47e6
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x4ae6
++#define mmCRTC_STATIC_SCREEN_CONTROL                                            0x1be7
++#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                      0x1be7
++#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                      0x1ee7
++#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                      0x41e7
++#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                      0x44e7
++#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                      0x47e7
++#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                      0x4ae7
++#define mmCRTC_3D_STRUCTURE_CONTROL                                             0x1b78
++#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                       0x1b78
++#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                       0x1e78
++#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                       0x4178
++#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                       0x4478
++#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                       0x4778
++#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                       0x4a78
++#define mmCRTC_GSL_VSYNC_GAP                                                    0x1b79
++#define mmCRTC0_CRTC_GSL_VSYNC_GAP                                              0x1b79
++#define mmCRTC1_CRTC_GSL_VSYNC_GAP                                              0x1e79
++#define mmCRTC2_CRTC_GSL_VSYNC_GAP                                              0x4179
++#define mmCRTC3_CRTC_GSL_VSYNC_GAP                                              0x4479
++#define mmCRTC4_CRTC_GSL_VSYNC_GAP                                              0x4779
++#define mmCRTC5_CRTC_GSL_VSYNC_GAP                                              0x4a79
++#define mmCRTC_GSL_WINDOW                                                       0x1b7a
++#define mmCRTC0_CRTC_GSL_WINDOW                                                 0x1b7a
++#define mmCRTC1_CRTC_GSL_WINDOW                                                 0x1e7a
++#define mmCRTC2_CRTC_GSL_WINDOW                                                 0x417a
++#define mmCRTC3_CRTC_GSL_WINDOW                                                 0x447a
++#define mmCRTC4_CRTC_GSL_WINDOW                                                 0x477a
++#define mmCRTC5_CRTC_GSL_WINDOW                                                 0x4a7a
++#define mmCRTC_GSL_CONTROL                                                      0x1b7b
++#define mmCRTC0_CRTC_GSL_CONTROL                                                0x1b7b
++#define mmCRTC1_CRTC_GSL_CONTROL                                                0x1e7b
++#define mmCRTC2_CRTC_GSL_CONTROL                                                0x417b
++#define mmCRTC3_CRTC_GSL_CONTROL                                                0x447b
++#define mmCRTC4_CRTC_GSL_CONTROL                                                0x477b
++#define mmCRTC5_CRTC_GSL_CONTROL                                                0x4a7b
++#define mmCRTC_TEST_DEBUG_INDEX                                                 0x1bc6
++#define mmCRTC0_CRTC_TEST_DEBUG_INDEX                                           0x1bc6
++#define mmCRTC1_CRTC_TEST_DEBUG_INDEX                                           0x1ec6
++#define mmCRTC2_CRTC_TEST_DEBUG_INDEX                                           0x41c6
++#define mmCRTC3_CRTC_TEST_DEBUG_INDEX                                           0x44c6
++#define mmCRTC4_CRTC_TEST_DEBUG_INDEX                                           0x47c6
++#define mmCRTC5_CRTC_TEST_DEBUG_INDEX                                           0x4ac6
++#define mmCRTC_TEST_DEBUG_DATA                                                  0x1bc7
++#define mmCRTC0_CRTC_TEST_DEBUG_DATA                                            0x1bc7
++#define mmCRTC1_CRTC_TEST_DEBUG_DATA                                            0x1ec7
++#define mmCRTC2_CRTC_TEST_DEBUG_DATA                                            0x41c7
++#define mmCRTC3_CRTC_TEST_DEBUG_DATA                                            0x44c7
++#define mmCRTC4_CRTC_TEST_DEBUG_DATA                                            0x47c7
++#define mmCRTC5_CRTC_TEST_DEBUG_DATA                                            0x4ac7
++#define mmDAC_ENABLE                                                            0x19e4
++#define mmDAC_SOURCE_SELECT                                                     0x19e5
++#define mmDAC_CRC_EN                                                            0x19e6
++#define mmDAC_CRC_CONTROL                                                       0x19e7
++#define mmDAC_CRC_SIG_RGB_MASK                                                  0x19e8
++#define mmDAC_CRC_SIG_CONTROL_MASK                                              0x19e9
++#define mmDAC_CRC_SIG_RGB                                                       0x19ea
++#define mmDAC_CRC_SIG_CONTROL                                                   0x19eb
++#define mmDAC_SYNC_TRISTATE_CONTROL                                             0x19ec
++#define mmDAC_STEREOSYNC_SELECT                                                 0x19ed
++#define mmDAC_AUTODETECT_CONTROL                                                0x19ee
++#define mmDAC_AUTODETECT_CONTROL2                                               0x19ef
++#define mmDAC_AUTODETECT_CONTROL3                                               0x19f0
++#define mmDAC_AUTODETECT_STATUS                                                 0x19f1
++#define mmDAC_AUTODETECT_INT_CONTROL                                            0x19f2
++#define mmDAC_FORCE_OUTPUT_CNTL                                                 0x19f3
++#define mmDAC_FORCE_DATA                                                        0x19f4
++#define mmDAC_POWERDOWN                                                         0x19f5
++#define mmDAC_CONTROL                                                           0x19f6
++#define mmDAC_COMPARATOR_ENABLE                                                 0x19f7
++#define mmDAC_COMPARATOR_OUTPUT                                                 0x19f8
++#define mmDAC_PWR_CNTL                                                          0x19f9
++#define mmDAC_DFT_CONFIG                                                        0x19fa
++#define mmDAC_FIFO_STATUS                                                       0x19fb
++#define mmPERFCOUNTER_CNTL                                                      0x170
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                          0x170
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                          0x1870
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                          0x1b24
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                          0x1e24
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                          0x4124
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                          0x4424
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                          0x4724
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                          0x4a24
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                          0x4c40
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                          0x4d14
++#define mmPERFCOUNTER_STATE                                                     0x171
++#define mmDC_PERFMON0_PERFCOUNTER_STATE                                         0x171
++#define mmDC_PERFMON1_PERFCOUNTER_STATE                                         0x1871
++#define mmDC_PERFMON2_PERFCOUNTER_STATE                                         0x1b25
++#define mmDC_PERFMON3_PERFCOUNTER_STATE                                         0x1e25
++#define mmDC_PERFMON4_PERFCOUNTER_STATE                                         0x4125
++#define mmDC_PERFMON5_PERFCOUNTER_STATE                                         0x4425
++#define mmDC_PERFMON6_PERFCOUNTER_STATE                                         0x4725
++#define mmDC_PERFMON7_PERFCOUNTER_STATE                                         0x4a25
++#define mmDC_PERFMON8_PERFCOUNTER_STATE                                         0x4c41
++#define mmDC_PERFMON9_PERFCOUNTER_STATE                                         0x4d15
++#define mmPERFMON_CNTL                                                          0x173
++#define mmDC_PERFMON0_PERFMON_CNTL                                              0x173
++#define mmDC_PERFMON1_PERFMON_CNTL                                              0x1873
++#define mmDC_PERFMON2_PERFMON_CNTL                                              0x1b27
++#define mmDC_PERFMON3_PERFMON_CNTL                                              0x1e27
++#define mmDC_PERFMON4_PERFMON_CNTL                                              0x4127
++#define mmDC_PERFMON5_PERFMON_CNTL                                              0x4427
++#define mmDC_PERFMON6_PERFMON_CNTL                                              0x4727
++#define mmDC_PERFMON7_PERFMON_CNTL                                              0x4a27
++#define mmDC_PERFMON8_PERFMON_CNTL                                              0x4c43
++#define mmDC_PERFMON9_PERFMON_CNTL                                              0x4d17
++#define mmPERFMON_CVALUE_INT_MISC                                               0x172
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                   0x172
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                   0x1872
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                   0x1b26
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                   0x1e26
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                   0x4126
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                   0x4426
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                   0x4726
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                   0x4a26
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                   0x4c42
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                   0x4d16
++#define mmPERFMON_CVALUE_LOW                                                    0x174
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                        0x174
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                        0x1874
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                        0x1b28
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                        0x1e28
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                        0x4128
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                        0x4428
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                        0x4728
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                        0x4a28
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                        0x4c44
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                        0x4d18
++#define mmPERFMON_HI                                                            0x175
++#define mmDC_PERFMON0_PERFMON_HI                                                0x175
++#define mmDC_PERFMON1_PERFMON_HI                                                0x1875
++#define mmDC_PERFMON2_PERFMON_HI                                                0x1b29
++#define mmDC_PERFMON3_PERFMON_HI                                                0x1e29
++#define mmDC_PERFMON4_PERFMON_HI                                                0x4129
++#define mmDC_PERFMON5_PERFMON_HI                                                0x4429
++#define mmDC_PERFMON6_PERFMON_HI                                                0x4729
++#define mmDC_PERFMON7_PERFMON_HI                                                0x4a29
++#define mmDC_PERFMON8_PERFMON_HI                                                0x4c45
++#define mmDC_PERFMON9_PERFMON_HI                                                0x4d19
++#define mmPERFMON_LOW                                                           0x176
++#define mmDC_PERFMON0_PERFMON_LOW                                               0x176
++#define mmDC_PERFMON1_PERFMON_LOW                                               0x1876
++#define mmDC_PERFMON2_PERFMON_LOW                                               0x1b2a
++#define mmDC_PERFMON3_PERFMON_LOW                                               0x1e2a
++#define mmDC_PERFMON4_PERFMON_LOW                                               0x412a
++#define mmDC_PERFMON5_PERFMON_LOW                                               0x442a
++#define mmDC_PERFMON6_PERFMON_LOW                                               0x472a
++#define mmDC_PERFMON7_PERFMON_LOW                                               0x4a2a
++#define mmDC_PERFMON8_PERFMON_LOW                                               0x4c46
++#define mmDC_PERFMON9_PERFMON_LOW                                               0x4d1a
++#define mmPERFMON_TEST_DEBUG_INDEX                                              0x177
++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX                                  0x177
++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX                                  0x1877
++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX                                  0x1b2b
++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX                                  0x1e2b
++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX                                  0x412b
++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX                                  0x442b
++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                                  0x472b
++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                                  0x4a2b
++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                                  0x4c47
++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                                  0x4d1b
++#define mmPERFMON_TEST_DEBUG_DATA                                               0x178
++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA                                   0x178
++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA                                   0x1878
++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA                                   0x1b2c
++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA                                   0x1e2c
++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA                                   0x412c
++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA                                   0x442c
++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                                   0x472c
++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                                   0x4a2c
++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                                   0x4c48
++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                                   0x4d1c
++#define mmVGA25_PPLL_REF_DIV                                                    0xd8
++#define mmVGA28_PPLL_REF_DIV                                                    0xd9
++#define mmVGA41_PPLL_REF_DIV                                                    0xda
++#define mmVGA25_PPLL_FB_DIV                                                     0xdc
++#define mmVGA28_PPLL_FB_DIV                                                     0xdd
++#define mmVGA41_PPLL_FB_DIV                                                     0xde
++#define mmVGA25_PPLL_POST_DIV                                                   0xe0
++#define mmVGA28_PPLL_POST_DIV                                                   0xe1
++#define mmVGA41_PPLL_POST_DIV                                                   0xe2
++#define mmVGA25_PPLL_ANALOG                                                     0xe4
++#define mmVGA28_PPLL_ANALOG                                                     0xe5
++#define mmVGA41_PPLL_ANALOG                                                     0xe6
++#define mmDPREFCLK_CNTL                                                         0x118
++#define mmSCANIN_SOFT_RESET                                                     0x11e
++#define mmDCCG_GTC_CNTL                                                         0x120
++#define mmDCCG_GTC_DTO_INCR                                                     0x121
++#define mmDCCG_GTC_DTO_MODULO                                                   0x122
++#define mmDCCG_GTC_CURRENT                                                      0x123
++#define mmDCCG_DS_DTO_INCR                                                      0x113
++#define mmDCCG_DS_DTO_MODULO                                                    0x114
++#define mmDCCG_DS_CNTL                                                          0x115
++#define mmDCCG_DS_HW_CAL_INTERVAL                                               0x116
++#define mmDCCG_DS_DEBUG_CNTL                                                    0x112
++#define mmDMCU_SMU_INTERRUPT_CNTL                                               0x12c
++#define mmSMU_CONTROL                                                           0x12d
++#define mmSMU_INTERRUPT_CONTROL                                                 0x12e
++#define mmDAC_CLK_ENABLE                                                        0x128
++#define mmDVO_CLK_ENABLE                                                        0x129
++#define mmDCCG_GATE_DISABLE_CNTL                                                0x134
++#define mmDISPCLK_CGTT_BLK_CTRL_REG                                             0x135
++#define mmSCLK_CGTT_BLK_CTRL_REG                                                0x136
++#define mmDCCG_CAC_STATUS                                                       0x137
++#define mmPIXCLK1_RESYNC_CNTL                                                   0x138
++#define mmPIXCLK2_RESYNC_CNTL                                                   0x139
++#define mmPIXCLK0_RESYNC_CNTL                                                   0x13a
++#define mmMICROSECOND_TIME_BASE_DIV                                             0x13b
++#define mmDCCG_DISP_CNTL_REG                                                    0x13f
++#define mmDISPPLL_BG_CNTL                                                       0x13c
++#define mmDIG_SOFT_RESET                                                        0x13d
++#define mmMILLISECOND_TIME_BASE_DIV                                             0x130
++#define mmDISPCLK_FREQ_CHANGE_CNTL                                              0x131
++#define mmLIGHT_SLEEP_CNTL                                                      0x132
++#define mmDCCG_PERFMON_CNTL                                                     0x133
++#define mmCRTC0_PIXEL_RATE_CNTL                                                 0x140
++#define mmDP_DTO0_PHASE                                                         0x141
++#define mmDP_DTO0_MODULO                                                        0x142
++#define mmCRTC1_PIXEL_RATE_CNTL                                                 0x144
++#define mmDP_DTO1_PHASE                                                         0x145
++#define mmDP_DTO1_MODULO                                                        0x146
++#define mmCRTC2_PIXEL_RATE_CNTL                                                 0x148
++#define mmDP_DTO2_PHASE                                                         0x149
++#define mmDP_DTO2_MODULO                                                        0x14a
++#define mmCRTC3_PIXEL_RATE_CNTL                                                 0x14c
++#define mmDP_DTO3_PHASE                                                         0x14d
++#define mmDP_DTO3_MODULO                                                        0x14e
++#define mmCRTC4_PIXEL_RATE_CNTL                                                 0x150
++#define mmDP_DTO4_PHASE                                                         0x151
++#define mmDP_DTO4_MODULO                                                        0x152
++#define mmCRTC5_PIXEL_RATE_CNTL                                                 0x154
++#define mmDP_DTO5_PHASE                                                         0x155
++#define mmDP_DTO5_MODULO                                                        0x156
++#define mmDCFE0_SOFT_RESET                                                      0x158
++#define mmDCFE1_SOFT_RESET                                                      0x159
++#define mmDCFE2_SOFT_RESET                                                      0x15a
++#define mmDCFE3_SOFT_RESET                                                      0x15b
++#define mmDCFE4_SOFT_RESET                                                      0x15c
++#define mmDCFE5_SOFT_RESET                                                      0x15d
++#define mmDCI_SOFT_RESET                                                        0x15e
++#define mmDCCG_SOFT_RESET                                                       0x15f
++#define mmSYMCLKA_CLOCK_ENABLE                                                  0x160
++#define mmSYMCLKB_CLOCK_ENABLE                                                  0x161
++#define mmSYMCLKC_CLOCK_ENABLE                                                  0x162
++#define mmSYMCLKD_CLOCK_ENABLE                                                  0x163
++#define mmSYMCLKE_CLOCK_ENABLE                                                  0x164
++#define mmSYMCLKF_CLOCK_ENABLE                                                  0x165
++#define mmSYMCLKG_CLOCK_ENABLE                                                  0x117
++#define mmUNIPHY_SOFT_RESET                                                     0x166
++#define mmDCO_SOFT_RESET                                                        0x167
++#define mmDVOACLKD_CNTL                                                         0x168
++#define mmDVOACLKC_MVP_CNTL                                                     0x169
++#define mmDVOACLKC_CNTL                                                         0x16a
++#define mmDCCG_AUDIO_DTO_SOURCE                                                 0x16b
++#define mmDCCG_AUDIO_DTO0_PHASE                                                 0x16c
++#define mmDCCG_AUDIO_DTO0_MODULE                                                0x16d
++#define mmDCCG_AUDIO_DTO1_PHASE                                                 0x16e
++#define mmDCCG_AUDIO_DTO1_MODULE                                                0x16f
++#define mmDCCG_TEST_DEBUG_INDEX                                                 0x17c
++#define mmDCCG_TEST_DEBUG_DATA                                                  0x17d
++#define mmDCCG_TEST_CLK_SEL                                                     0x17e
++#define mmPLL_REF_DIV                                                           0x1700
++#define mmDCCG_PLL0_PLL_REF_DIV                                                 0x1700
++#define mmDCCG_PLL1_PLL_REF_DIV                                                 0x1714
++#define mmDCCG_PLL2_PLL_REF_DIV                                                 0x1728
++#define mmDCCG_PLL3_PLL_REF_DIV                                                 0x173c
++#define mmPLL_FB_DIV                                                            0x1701
++#define mmDCCG_PLL0_PLL_FB_DIV                                                  0x1701
++#define mmDCCG_PLL1_PLL_FB_DIV                                                  0x1715
++#define mmDCCG_PLL2_PLL_FB_DIV                                                  0x1729
++#define mmDCCG_PLL3_PLL_FB_DIV                                                  0x173d
++#define mmPLL_POST_DIV                                                          0x1702
++#define mmDCCG_PLL0_PLL_POST_DIV                                                0x1702
++#define mmDCCG_PLL1_PLL_POST_DIV                                                0x1716
++#define mmDCCG_PLL2_PLL_POST_DIV                                                0x172a
++#define mmDCCG_PLL3_PLL_POST_DIV                                                0x173e
++#define mmPLL_SS_AMOUNT_DSFRAC                                                  0x1703
++#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC                                        0x1703
++#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC                                        0x1717
++#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC                                        0x172b
++#define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC                                        0x173f
++#define mmPLL_SS_CNTL                                                           0x1704
++#define mmDCCG_PLL0_PLL_SS_CNTL                                                 0x1704
++#define mmDCCG_PLL1_PLL_SS_CNTL                                                 0x1718
++#define mmDCCG_PLL2_PLL_SS_CNTL                                                 0x172c
++#define mmDCCG_PLL3_PLL_SS_CNTL                                                 0x1740
++#define mmPLL_DS_CNTL                                                           0x1705
++#define mmDCCG_PLL0_PLL_DS_CNTL                                                 0x1705
++#define mmDCCG_PLL1_PLL_DS_CNTL                                                 0x1719
++#define mmDCCG_PLL2_PLL_DS_CNTL                                                 0x172d
++#define mmDCCG_PLL3_PLL_DS_CNTL                                                 0x1741
++#define mmPLL_IDCLK_CNTL                                                        0x1706
++#define mmDCCG_PLL0_PLL_IDCLK_CNTL                                              0x1706
++#define mmDCCG_PLL1_PLL_IDCLK_CNTL                                              0x171a
++#define mmDCCG_PLL2_PLL_IDCLK_CNTL                                              0x172e
++#define mmDCCG_PLL3_PLL_IDCLK_CNTL                                              0x1742
++#define mmPLL_CNTL                                                              0x1707
++#define mmDCCG_PLL0_PLL_CNTL                                                    0x1707
++#define mmDCCG_PLL1_PLL_CNTL                                                    0x171b
++#define mmDCCG_PLL2_PLL_CNTL                                                    0x172f
++#define mmDCCG_PLL3_PLL_CNTL                                                    0x1743
++#define mmPLL_ANALOG                                                            0x1708
++#define mmDCCG_PLL0_PLL_ANALOG                                                  0x1708
++#define mmDCCG_PLL1_PLL_ANALOG                                                  0x171c
++#define mmDCCG_PLL2_PLL_ANALOG                                                  0x1730
++#define mmDCCG_PLL3_PLL_ANALOG                                                  0x1744
++#define mmPLL_ANALOG_CNTL                                                       0x1711
++#define mmDCCG_PLL0_PLL_ANALOG_CNTL                                             0x1711
++#define mmDCCG_PLL1_PLL_ANALOG_CNTL                                             0x1725
++#define mmDCCG_PLL2_PLL_ANALOG_CNTL                                             0x1739
++#define mmDCCG_PLL3_PLL_ANALOG_CNTL                                             0x174d
++#define mmPLL_VREG_CNTL                                                         0x1709
++#define mmDCCG_PLL0_PLL_VREG_CNTL                                               0x1709
++#define mmDCCG_PLL1_PLL_VREG_CNTL                                               0x171d
++#define mmDCCG_PLL2_PLL_VREG_CNTL                                               0x1731
++#define mmDCCG_PLL3_PLL_VREG_CNTL                                               0x1745
++#define mmPLL_XOR_LOCK                                                          0x1710
++#define mmDCCG_PLL0_PLL_XOR_LOCK                                                0x1710
++#define mmDCCG_PLL1_PLL_XOR_LOCK                                                0x1724
++#define mmDCCG_PLL2_PLL_XOR_LOCK                                                0x1738
++#define mmDCCG_PLL3_PLL_XOR_LOCK                                                0x174c
++#define mmPLL_UNLOCK_DETECT_CNTL                                                0x170a
++#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL                                      0x170a
++#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL                                      0x171e
++#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL                                      0x1732
++#define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL                                      0x1746
++#define mmPLL_DEBUG_CNTL                                                        0x170b
++#define mmDCCG_PLL0_PLL_DEBUG_CNTL                                              0x170b
++#define mmDCCG_PLL1_PLL_DEBUG_CNTL                                              0x171f
++#define mmDCCG_PLL2_PLL_DEBUG_CNTL                                              0x1733
++#define mmDCCG_PLL3_PLL_DEBUG_CNTL                                              0x1747
++#define mmPLL_UPDATE_LOCK                                                       0x170c
++#define mmDCCG_PLL0_PLL_UPDATE_LOCK                                             0x170c
++#define mmDCCG_PLL1_PLL_UPDATE_LOCK                                             0x1720
++#define mmDCCG_PLL2_PLL_UPDATE_LOCK                                             0x1734
++#define mmDCCG_PLL3_PLL_UPDATE_LOCK                                             0x1748
++#define mmPLL_UPDATE_CNTL                                                       0x170d
++#define mmDCCG_PLL0_PLL_UPDATE_CNTL                                             0x170d
++#define mmDCCG_PLL1_PLL_UPDATE_CNTL                                             0x1721
++#define mmDCCG_PLL2_PLL_UPDATE_CNTL                                             0x1735
++#define mmDCCG_PLL3_PLL_UPDATE_CNTL                                             0x1749
++#define mmPLL_DISPCLK_DTO_CNTL                                                  0x170e
++#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL                                        0x170e
++#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL                                        0x1722
++#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL                                        0x1736
++#define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL                                        0x174a
++#define mmPLL_DISPCLK_CURRENT_DTO_PHASE                                         0x170f
++#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x170f
++#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x1723
++#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x1737
++#define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE                               0x174b
++#define mmDENTIST_DISPCLK_CNTL                                                  0x124
++#define mmDCDEBUG_BUS_CLK1_SEL                                                  0x1860
++#define mmDCDEBUG_BUS_CLK2_SEL                                                  0x1861
++#define mmDCDEBUG_BUS_CLK3_SEL                                                  0x1862
++#define mmDCDEBUG_BUS_CLK4_SEL                                                  0x1863
++#define mmDCDEBUG_OUT_PIN_OVERRIDE                                              0x186a
++#define mmDCDEBUG_OUT_CNTL                                                      0x186b
++#define mmDCDEBUG_OUT_DATA                                                      0x186e
++#define mmDMIF_ADDR_CONFIG                                                      0x2f5
++#define mmDMIF_CONTROL                                                          0x2f6
++#define mmDMIF_STATUS                                                           0x2f7
++#define mmDMIF_HW_DEBUG                                                         0x2f8
++#define mmDMIF_ARBITRATION_CONTROL                                              0x2f9
++#define mmPIPE0_ARBITRATION_CONTROL3                                            0x2fa
++#define mmPIPE1_ARBITRATION_CONTROL3                                            0x2fb
++#define mmPIPE2_ARBITRATION_CONTROL3                                            0x2fc
++#define mmPIPE3_ARBITRATION_CONTROL3                                            0x2fd
++#define mmPIPE4_ARBITRATION_CONTROL3                                            0x2fe
++#define mmPIPE5_ARBITRATION_CONTROL3                                            0x2ff
++#define mmDMIF_TEST_DEBUG_INDEX                                                 0x312
++#define mmDMIF_TEST_DEBUG_DATA                                                  0x313
++#define ixDMIF_DEBUG02_CORE0                                                    0x2
++#define ixDMIF_DEBUG02_CORE1                                                    0xa
++#define mmDMIF_ADDR_CALC                                                        0x300
++#define mmDMIF_STATUS2                                                          0x301
++#define mmPIPE0_MAX_REQUESTS                                                    0x302
++#define mmPIPE1_MAX_REQUESTS                                                    0x303
++#define mmPIPE2_MAX_REQUESTS                                                    0x304
++#define mmPIPE3_MAX_REQUESTS                                                    0x305
++#define mmPIPE4_MAX_REQUESTS                                                    0x306
++#define mmPIPE5_MAX_REQUESTS                                                    0x307
++#define mmLOW_POWER_TILING_CONTROL                                              0x325
++#define mmMCIF_CONTROL                                                          0x314
++#define mmMCIF_WRITE_COMBINE_CONTROL                                            0x315
++#define mmMCIF_TEST_DEBUG_INDEX                                                 0x316
++#define mmMCIF_TEST_DEBUG_DATA                                                  0x317
++#define ixIDDCCIF02_DBG_DCCIF_C                                                 0x9
++#define ixIDDCCIF04_DBG_DCCIF_E                                                 0xb
++#define ixIDDCCIF05_DBG_DCCIF_F                                                 0xc
++#define mmMCIF_VMID                                                             0x318
++#define mmMCIF_MEM_CONTROL                                                      0x319
++#define mmCC_DC_PIPE_DIS                                                        0x177f
++#define mmMC_DC_INTERFACE_NACK_STATUS                                           0x31c
++#define mmDC_RBBMIF_RDWR_CNTL1                                                  0x31a
++#define mmDC_RBBMIF_RDWR_CNTL2                                                  0x31d
++#define mmDC_RBBMIF_RDWR_CNTL3                                                  0x311
++#define mmDCI_MEM_PWR_STATE                                                     0x31b
++#define mmDCI_MEM_PWR_STATE2                                                    0x322
++#define mmDCI_CLK_CNTL                                                          0x31e
++#define mmDCCG_VPCLK_CNTL                                                       0x31f
++#define mmDCI_MEM_PWR_CNTL                                                      0x326
++#define mmDC_XDMA_INTERFACE_CNTL                                                0x327
++#define mmDCI_TEST_DEBUG_INDEX                                                  0x320
++#define mmDCI_TEST_DEBUG_DATA                                                   0x321
++#define mmDCI_DEBUG_CONFIG                                                      0x323
++#define mmPIPE0_DMIF_BUFFER_CONTROL                                             0x328
++#define mmPIPE1_DMIF_BUFFER_CONTROL                                             0x330
++#define mmPIPE2_DMIF_BUFFER_CONTROL                                             0x338
++#define mmPIPE3_DMIF_BUFFER_CONTROL                                             0x340
++#define mmPIPE4_DMIF_BUFFER_CONTROL                                             0x348
++#define mmPIPE5_DMIF_BUFFER_CONTROL                                             0x350
++#define mmMCIF_BUFMGR_SW_CONTROL                                                0x358
++#define mmMCIF_BUFMGR_STATUS                                                    0x35a
++#define mmMCIF_BUF_PITCH                                                        0x35b
++#define mmMCIF_BUF_1_ADDR_Y_LOW                                                 0x35c
++#define mmMCIF_BUF_2_ADDR_Y_LOW                                                 0x360
++#define mmMCIF_BUF_3_ADDR_Y_LOW                                                 0x364
++#define mmMCIF_BUF_4_ADDR_Y_LOW                                                 0x368
++#define mmMCIF_BUF_1_ADDR_UP                                                    0x35d
++#define mmMCIF_BUF_2_ADDR_UP                                                    0x361
++#define mmMCIF_BUF_3_ADDR_UP                                                    0x365
++#define mmMCIF_BUF_4_ADDR_UP                                                    0x369
++#define mmMCIF_BUF_1_ADDR_C_LOW                                                 0x35e
++#define mmMCIF_BUF_2_ADDR_C_LOW                                                 0x362
++#define mmMCIF_BUF_3_ADDR_C_LOW                                                 0x366
++#define mmMCIF_BUF_4_ADDR_C_LOW                                                 0x36a
++#define mmMCIF_BUF_1_STATUS                                                     0x35f
++#define mmMCIF_BUF_2_STATUS                                                     0x363
++#define mmMCIF_BUF_3_STATUS                                                     0x367
++#define mmMCIF_BUF_4_STATUS                                                     0x36b
++#define mmMCIF_SI_ARBITRATION_CONTROL                                           0x36c
++#define mmMCIF_URGENCY_WATERMARK                                                0x36d
++#define mmDC_GENERICA                                                           0x1900
++#define mmDC_GENERICB                                                           0x1901
++#define mmDC_PAD_EXTERN_SIG                                                     0x1902
++#define mmDC_REF_CLK_CNTL                                                       0x1903
++#define mmDC_GPIO_DEBUG                                                         0x1904
++#define mmDCO_MEM_POWER_STATE                                                   0x1906
++#define mmDCO_MEM_POWER_STATE_2                                                 0x193a
++#define mmDCO_LIGHT_SLEEP_DIS                                                   0x1907
++#define mmUNIPHY_IMPCAL_LINKA                                                   0x1908
++#define mmUNIPHY_IMPCAL_LINKB                                                   0x1909
++#define mmUNIPHY_IMPCAL_PERIOD                                                  0x190a
++#define mmAUXP_IMPCAL                                                           0x190b
++#define mmAUXN_IMPCAL                                                           0x190c
++#define mmDCIO_IMPCAL_CNTL_AB                                                   0x190d
++#define mmUNIPHY_IMPCAL_PSW_AB                                                  0x190e
++#define mmUNIPHY_IMPCAL_LINKC                                                   0x190f
++#define mmUNIPHY_IMPCAL_LINKD                                                   0x1910
++#define mmDCIO_IMPCAL_CNTL_CD                                                   0x1911
++#define mmUNIPHY_IMPCAL_PSW_CD                                                  0x1912
++#define mmUNIPHY_IMPCAL_LINKE                                                   0x1913
++#define mmUNIPHY_IMPCAL_LINKF                                                   0x1914
++#define mmDCIO_IMPCAL_CNTL_EF                                                   0x1915
++#define mmUNIPHY_IMPCAL_PSW_EF                                                  0x1916
++#define mmDC_PINSTRAPS                                                          0x1917
++#define mmDC_DVODATA_CONFIG                                                     0x1905
++#define mmLVTMA_PWRSEQ_CNTL                                                     0x1919
++#define mmLVTMA_PWRSEQ_STATE                                                    0x191a
++#define mmLVTMA_PWRSEQ_REF_DIV                                                  0x191b
++#define mmLVTMA_PWRSEQ_DELAY1                                                   0x191c
++#define mmLVTMA_PWRSEQ_DELAY2                                                   0x191d
++#define mmBL_PWM_CNTL                                                           0x191e
++#define mmBL_PWM_CNTL2                                                          0x191f
++#define mmBL_PWM_PERIOD_CNTL                                                    0x1920
++#define mmBL_PWM_GRP1_REG_LOCK                                                  0x1921
++#define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x1922
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                            0x1923
++#define mmDCIO_GSL0_CNTL                                                        0x1924
++#define mmDCIO_GSL1_CNTL                                                        0x1925
++#define mmDCIO_GSL2_CNTL                                                        0x1926
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                  0x1927
++#define mmDC_GPU_TIMER_START_POSITION_P_FLIP                                    0x1928
++#define mmDC_GPU_TIMER_READ                                                     0x1929
++#define mmDC_GPU_TIMER_READ_CNTL                                                0x192a
++#define mmDCO_CLK_CNTL                                                          0x192b
++#define mmDCO_CLK_RAMP_CNTL                                                     0x192c
++#define mmDCIO_DEBUG                                                            0x192e
++#define mmDCO_DCFE_EXT_VSYNC_CNTL                                               0x1937
++#define mmDCIO_TEST_DEBUG_INDEX                                                 0x192f
++#define mmDCIO_TEST_DEBUG_DATA                                                  0x1930
++#define ixDCIO_DEBUG1                                                           0x1
++#define ixDCIO_DEBUG2                                                           0x2
++#define ixDCIO_DEBUG3                                                           0x3
++#define ixDCIO_DEBUG4                                                           0x4
++#define ixDCIO_DEBUG5                                                           0x5
++#define ixDCIO_DEBUG6                                                           0x6
++#define ixDCIO_DEBUG7                                                           0x7
++#define ixDCIO_DEBUG8                                                           0x8
++#define ixDCIO_DEBUG9                                                           0x9
++#define ixDCIO_DEBUGA                                                           0xa
++#define ixDCIO_DEBUGB                                                           0xb
++#define ixDCIO_DEBUGC                                                           0xc
++#define ixDCIO_DEBUGD                                                           0xd
++#define ixDCIO_DEBUGE                                                           0xe
++#define ixDCIO_DEBUGF                                                           0xf
++#define ixDCIO_DEBUG10                                                          0x10
++#define ixDCIO_DEBUG11                                                          0x11
++#define ixDCIO_DEBUG12                                                          0x12
++#define ixDCIO_DEBUG13                                                          0x13
++#define ixDCIO_DEBUG14                                                          0x14
++#define ixDCIO_DEBUG15                                                          0x15
++#define ixDCIO_DEBUG_ID                                                         0x0
++#define mmDC_GPIO_GENERIC_MASK                                                  0x1944
++#define mmDC_GPIO_GENERIC_A                                                     0x1945
++#define mmDC_GPIO_GENERIC_EN                                                    0x1946
++#define mmDC_GPIO_GENERIC_Y                                                     0x1947
++#define mmDC_GPIO_DVODATA_MASK                                                  0x1948
++#define mmDC_GPIO_DVODATA_A                                                     0x1949
++#define mmDC_GPIO_DVODATA_EN                                                    0x194a
++#define mmDC_GPIO_DVODATA_Y                                                     0x194b
++#define mmDC_GPIO_DDC1_MASK                                                     0x194c
++#define mmDC_GPIO_DDC1_A                                                        0x194d
++#define mmDC_GPIO_DDC1_EN                                                       0x194e
++#define mmDC_GPIO_DDC1_Y                                                        0x194f
++#define mmDC_GPIO_DDC2_MASK                                                     0x1950
++#define mmDC_GPIO_DDC2_A                                                        0x1951
++#define mmDC_GPIO_DDC2_EN                                                       0x1952
++#define mmDC_GPIO_DDC2_Y                                                        0x1953
++#define mmDC_GPIO_DDC3_MASK                                                     0x1954
++#define mmDC_GPIO_DDC3_A                                                        0x1955
++#define mmDC_GPIO_DDC3_EN                                                       0x1956
++#define mmDC_GPIO_DDC3_Y                                                        0x1957
++#define mmDC_GPIO_DDC4_MASK                                                     0x1958
++#define mmDC_GPIO_DDC4_A                                                        0x1959
++#define mmDC_GPIO_DDC4_EN                                                       0x195a
++#define mmDC_GPIO_DDC4_Y                                                        0x195b
++#define mmDC_GPIO_DDC5_MASK                                                     0x195c
++#define mmDC_GPIO_DDC5_A                                                        0x195d
++#define mmDC_GPIO_DDC5_EN                                                       0x195e
++#define mmDC_GPIO_DDC5_Y                                                        0x195f
++#define mmDC_GPIO_DDC6_MASK                                                     0x1960
++#define mmDC_GPIO_DDC6_A                                                        0x1961
++#define mmDC_GPIO_DDC6_EN                                                       0x1962
++#define mmDC_GPIO_DDC6_Y                                                        0x1963
++#define mmDC_GPIO_DDCVGA_MASK                                                   0x1970
++#define mmDC_GPIO_DDCVGA_A                                                      0x1971
++#define mmDC_GPIO_DDCVGA_EN                                                     0x1972
++#define mmDC_GPIO_DDCVGA_Y                                                      0x1973
++#define mmDC_GPIO_SYNCA_MASK                                                    0x1964
++#define mmDC_GPIO_SYNCA_A                                                       0x1965
++#define mmDC_GPIO_SYNCA_EN                                                      0x1966
++#define mmDC_GPIO_SYNCA_Y                                                       0x1967
++#define mmDC_GPIO_GENLK_MASK                                                    0x1968
++#define mmDC_GPIO_GENLK_A                                                       0x1969
++#define mmDC_GPIO_GENLK_EN                                                      0x196a
++#define mmDC_GPIO_GENLK_Y                                                       0x196b
++#define mmDC_GPIO_HPD_MASK                                                      0x196c
++#define mmDC_GPIO_HPD_A                                                         0x196d
++#define mmDC_GPIO_HPD_EN                                                        0x196e
++#define mmDC_GPIO_HPD_Y                                                         0x196f
++#define mmDC_GPIO_PWRSEQ_MASK                                                   0x1940
++#define mmDC_GPIO_PWRSEQ_A                                                      0x1941
++#define mmDC_GPIO_PWRSEQ_EN                                                     0x1942
++#define mmDC_GPIO_PWRSEQ_Y                                                      0x1943
++#define mmDC_GPIO_PAD_STRENGTH_1                                                0x1978
++#define mmDC_GPIO_PAD_STRENGTH_2                                                0x1979
++#define mmPHY_AUX_CNTL                                                          0x197f
++#define mmDC_GPIO_I2CPAD_A                                                      0x1975
++#define mmDC_GPIO_I2CPAD_EN                                                     0x1976
++#define mmDC_GPIO_I2CPAD_Y                                                      0x1977
++#define mmDC_GPIO_I2CPAD_STRENGTH                                               0x197a
++#define mmDVO_STRENGTH_CONTROL                                                  0x197b
++#define mmDVO_VREF_CONTROL                                                      0x197c
++#define mmDVO_SKEW_ADJUST                                                       0x197d
++#define mmUNIPHYAB_TPG_CONTROL                                                  0x1931
++#define mmUNIPHYAB_TPG_SEED                                                     0x1932
++#define mmUNIPHYCD_TPG_CONTROL                                                  0x1933
++#define mmUNIPHYCD_TPG_SEED                                                     0x1934
++#define mmUNIPHYEF_TPG_CONTROL                                                  0x1935
++#define mmUNIPHYEF_TPG_SEED                                                     0x1936
++#define mmUNIPHYGH_TPG_CONTROL                                                  0x1938
++#define mmUNIPHYGH_TPG_SEED                                                     0x1939
++#define mmDC_GPIO_I2S_SPDIF_MASK                                                0x193c
++#define mmDC_GPIO_I2S_SPDIF_A                                                   0x193d
++#define mmDC_GPIO_I2S_SPDIF_EN                                                  0x193e
++#define mmDC_GPIO_I2S_SPDIF_Y                                                   0x193f
++#define mmDC_GPIO_I2S_SPDIF_STRENGTH                                            0x193b
++#define mmDAC_MACRO_CNTL_RESERVED0                                              0x19fc
++#define mmDAC_MACRO_CNTL_RESERVED1                                              0x19fd
++#define mmDAC_MACRO_CNTL_RESERVED2                                              0x19fe
++#define mmDAC_MACRO_CNTL_RESERVED3                                              0x19ff
++#define mmUNIPHY_TX_CONTROL1                                                    0x1980
++#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1                                       0x1980
++#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1                                       0x1990
++#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1                                       0x19a0
++#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1                                       0x19b0
++#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1                                       0x19c0
++#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1                                       0x19d0
++#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1                                       0x4df0
++#define mmUNIPHY_TX_CONTROL2                                                    0x1981
++#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2                                       0x1981
++#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2                                       0x1991
++#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2                                       0x19a1
++#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2                                       0x19b1
++#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2                                       0x19c1
++#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2                                       0x19d1
++#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2                                       0x4df1
++#define mmUNIPHY_TX_CONTROL3                                                    0x1982
++#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3                                       0x1982
++#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3                                       0x1992
++#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3                                       0x19a2
++#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3                                       0x19b2
++#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3                                       0x19c2
++#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3                                       0x19d2
++#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3                                       0x4df2
++#define mmUNIPHY_TX_CONTROL4                                                    0x1983
++#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4                                       0x1983
++#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4                                       0x1993
++#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4                                       0x19a3
++#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4                                       0x19b3
++#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4                                       0x19c3
++#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4                                       0x19d3
++#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4                                       0x4df3
++#define mmUNIPHY_POWER_CONTROL                                                  0x1984
++#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL                                     0x1984
++#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL                                     0x1994
++#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL                                     0x19a4
++#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL                                     0x19b4
++#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL                                     0x19c4
++#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL                                     0x19d4
++#define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL                                     0x4df4
++#define mmUNIPHY_PLL_FBDIV                                                      0x1985
++#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV                                         0x1985
++#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV                                         0x1995
++#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV                                         0x19a5
++#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV                                         0x19b5
++#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV                                         0x19c5
++#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV                                         0x19d5
++#define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV                                         0x4df5
++#define mmUNIPHY_PLL_CONTROL1                                                   0x1986
++#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1                                      0x1986
++#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1                                      0x1996
++#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1                                      0x19a6
++#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1                                      0x19b6
++#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1                                      0x19c6
++#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1                                      0x19d6
++#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1                                      0x4df6
++#define mmUNIPHY_PLL_CONTROL2                                                   0x1987
++#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2                                      0x1987
++#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2                                      0x1997
++#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2                                      0x19a7
++#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2                                      0x19b7
++#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2                                      0x19c7
++#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2                                      0x19d7
++#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2                                      0x4df7
++#define mmUNIPHY_PLL_SS_STEP_SIZE                                               0x1988
++#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                                  0x1988
++#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                                  0x1998
++#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                                  0x19a8
++#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                                  0x19b8
++#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                                  0x19c8
++#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                                  0x19d8
++#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                                  0x4df8
++#define mmUNIPHY_PLL_SS_CNTL                                                    0x1989
++#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL                                       0x1989
++#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL                                       0x1999
++#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL                                       0x19a9
++#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL                                       0x19b9
++#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL                                       0x19c9
++#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL                                       0x19d9
++#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL                                       0x4df9
++#define mmUNIPHY_DATA_SYNCHRONIZATION                                           0x198a
++#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION                              0x198a
++#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION                              0x199a
++#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION                              0x19aa
++#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION                              0x19ba
++#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION                              0x19ca
++#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION                              0x19da
++#define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION                              0x4dfa
++#define mmUNIPHY_REG_TEST_OUTPUT                                                0x198b
++#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                                   0x198b
++#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                                   0x199b
++#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                                   0x19ab
++#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                                   0x19bb
++#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                                   0x19cb
++#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                                   0x19db
++#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                                   0x4dfb
++#define mmUNIPHY_ANG_BIST_CNTL                                                  0x198c
++#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL                                     0x198c
++#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL                                     0x199c
++#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL                                     0x19ac
++#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL                                     0x19bc
++#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL                                     0x19cc
++#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL                                     0x19dc
++#define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL                                     0x4dfc
++#define mmUNIPHY_LINK_CNTL                                                      0x198d
++#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL                                         0x198d
++#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL                                         0x199d
++#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL                                         0x19ad
++#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL                                         0x19bd
++#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL                                         0x19cd
++#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL                                         0x19dd
++#define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL                                         0x4dfd
++#define mmUNIPHY_CHANNEL_XBAR_CNTL                                              0x198e
++#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL                                 0x198e
++#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL                                 0x199e
++#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19ae
++#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19be
++#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19ce
++#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL                                 0x19de
++#define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL                                 0x4dfe
++#define mmUNIPHY_REG_TEST_OUTPUT2                                               0x198f
++#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                                  0x198f
++#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                                  0x199f
++#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                                  0x19af
++#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                                  0x19bf
++#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                                  0x19cf
++#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                                  0x19df
++#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                                  0x4dff
++#define mmGRPH_ENABLE                                                           0x1a00
++#define mmDCP0_GRPH_ENABLE                                                      0x1a00
++#define mmDCP1_GRPH_ENABLE                                                      0x1d00
++#define mmDCP2_GRPH_ENABLE                                                      0x4000
++#define mmDCP3_GRPH_ENABLE                                                      0x4300
++#define mmDCP4_GRPH_ENABLE                                                      0x4600
++#define mmDCP5_GRPH_ENABLE                                                      0x4900
++#define mmGRPH_CONTROL                                                          0x1a01
++#define mmDCP0_GRPH_CONTROL                                                     0x1a01
++#define mmDCP1_GRPH_CONTROL                                                     0x1d01
++#define mmDCP2_GRPH_CONTROL                                                     0x4001
++#define mmDCP3_GRPH_CONTROL                                                     0x4301
++#define mmDCP4_GRPH_CONTROL                                                     0x4601
++#define mmDCP5_GRPH_CONTROL                                                     0x4901
++#define mmGRPH_LUT_10BIT_BYPASS                                                 0x1a02
++#define mmDCP0_GRPH_LUT_10BIT_BYPASS                                            0x1a02
++#define mmDCP1_GRPH_LUT_10BIT_BYPASS                                            0x1d02
++#define mmDCP2_GRPH_LUT_10BIT_BYPASS                                            0x4002
++#define mmDCP3_GRPH_LUT_10BIT_BYPASS                                            0x4302
++#define mmDCP4_GRPH_LUT_10BIT_BYPASS                                            0x4602
++#define mmDCP5_GRPH_LUT_10BIT_BYPASS                                            0x4902
++#define mmGRPH_SWAP_CNTL                                                        0x1a03
++#define mmDCP0_GRPH_SWAP_CNTL                                                   0x1a03
++#define mmDCP1_GRPH_SWAP_CNTL                                                   0x1d03
++#define mmDCP2_GRPH_SWAP_CNTL                                                   0x4003
++#define mmDCP3_GRPH_SWAP_CNTL                                                   0x4303
++#define mmDCP4_GRPH_SWAP_CNTL                                                   0x4603
++#define mmDCP5_GRPH_SWAP_CNTL                                                   0x4903
++#define mmGRPH_PRIMARY_SURFACE_ADDRESS                                          0x1a04
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1a04
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1d04
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4004
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4304
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4604
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4904
++#define mmGRPH_SECONDARY_SURFACE_ADDRESS                                        0x1a05
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1a05
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1d05
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4005
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4305
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4605
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4905
++#define mmGRPH_PITCH                                                            0x1a06
++#define mmDCP0_GRPH_PITCH                                                       0x1a06
++#define mmDCP1_GRPH_PITCH                                                       0x1d06
++#define mmDCP2_GRPH_PITCH                                                       0x4006
++#define mmDCP3_GRPH_PITCH                                                       0x4306
++#define mmDCP4_GRPH_PITCH                                                       0x4606
++#define mmDCP5_GRPH_PITCH                                                       0x4906
++#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                     0x1a07
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1a07
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1d07
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4007
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4307
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4607
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4907
++#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                   0x1a08
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1a08
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1d08
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4008
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4308
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4608
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4908
++#define mmGRPH_SURFACE_OFFSET_X                                                 0x1a09
++#define mmDCP0_GRPH_SURFACE_OFFSET_X                                            0x1a09
++#define mmDCP1_GRPH_SURFACE_OFFSET_X                                            0x1d09
++#define mmDCP2_GRPH_SURFACE_OFFSET_X                                            0x4009
++#define mmDCP3_GRPH_SURFACE_OFFSET_X                                            0x4309
++#define mmDCP4_GRPH_SURFACE_OFFSET_X                                            0x4609
++#define mmDCP5_GRPH_SURFACE_OFFSET_X                                            0x4909
++#define mmGRPH_SURFACE_OFFSET_Y                                                 0x1a0a
++#define mmDCP0_GRPH_SURFACE_OFFSET_Y                                            0x1a0a
++#define mmDCP1_GRPH_SURFACE_OFFSET_Y                                            0x1d0a
++#define mmDCP2_GRPH_SURFACE_OFFSET_Y                                            0x400a
++#define mmDCP3_GRPH_SURFACE_OFFSET_Y                                            0x430a
++#define mmDCP4_GRPH_SURFACE_OFFSET_Y                                            0x460a
++#define mmDCP5_GRPH_SURFACE_OFFSET_Y                                            0x490a
++#define mmGRPH_X_START                                                          0x1a0b
++#define mmDCP0_GRPH_X_START                                                     0x1a0b
++#define mmDCP1_GRPH_X_START                                                     0x1d0b
++#define mmDCP2_GRPH_X_START                                                     0x400b
++#define mmDCP3_GRPH_X_START                                                     0x430b
++#define mmDCP4_GRPH_X_START                                                     0x460b
++#define mmDCP5_GRPH_X_START                                                     0x490b
++#define mmGRPH_Y_START                                                          0x1a0c
++#define mmDCP0_GRPH_Y_START                                                     0x1a0c
++#define mmDCP1_GRPH_Y_START                                                     0x1d0c
++#define mmDCP2_GRPH_Y_START                                                     0x400c
++#define mmDCP3_GRPH_Y_START                                                     0x430c
++#define mmDCP4_GRPH_Y_START                                                     0x460c
++#define mmDCP5_GRPH_Y_START                                                     0x490c
++#define mmGRPH_X_END                                                            0x1a0d
++#define mmDCP0_GRPH_X_END                                                       0x1a0d
++#define mmDCP1_GRPH_X_END                                                       0x1d0d
++#define mmDCP2_GRPH_X_END                                                       0x400d
++#define mmDCP3_GRPH_X_END                                                       0x430d
++#define mmDCP4_GRPH_X_END                                                       0x460d
++#define mmDCP5_GRPH_X_END                                                       0x490d
++#define mmGRPH_Y_END                                                            0x1a0e
++#define mmDCP0_GRPH_Y_END                                                       0x1a0e
++#define mmDCP1_GRPH_Y_END                                                       0x1d0e
++#define mmDCP2_GRPH_Y_END                                                       0x400e
++#define mmDCP3_GRPH_Y_END                                                       0x430e
++#define mmDCP4_GRPH_Y_END                                                       0x460e
++#define mmDCP5_GRPH_Y_END                                                       0x490e
++#define mmINPUT_GAMMA_CONTROL                                                   0x1a10
++#define mmDCP0_INPUT_GAMMA_CONTROL                                              0x1a10
++#define mmDCP1_INPUT_GAMMA_CONTROL                                              0x1d10
++#define mmDCP2_INPUT_GAMMA_CONTROL                                              0x4010
++#define mmDCP3_INPUT_GAMMA_CONTROL                                              0x4310
++#define mmDCP4_INPUT_GAMMA_CONTROL                                              0x4610
++#define mmDCP5_INPUT_GAMMA_CONTROL                                              0x4910
++#define mmGRPH_UPDATE                                                           0x1a11
++#define mmDCP0_GRPH_UPDATE                                                      0x1a11
++#define mmDCP1_GRPH_UPDATE                                                      0x1d11
++#define mmDCP2_GRPH_UPDATE                                                      0x4011
++#define mmDCP3_GRPH_UPDATE                                                      0x4311
++#define mmDCP4_GRPH_UPDATE                                                      0x4611
++#define mmDCP5_GRPH_UPDATE                                                      0x4911
++#define mmGRPH_FLIP_CONTROL                                                     0x1a12
++#define mmDCP0_GRPH_FLIP_CONTROL                                                0x1a12
++#define mmDCP1_GRPH_FLIP_CONTROL                                                0x1d12
++#define mmDCP2_GRPH_FLIP_CONTROL                                                0x4012
++#define mmDCP3_GRPH_FLIP_CONTROL                                                0x4312
++#define mmDCP4_GRPH_FLIP_CONTROL                                                0x4612
++#define mmDCP5_GRPH_FLIP_CONTROL                                                0x4912
++#define mmGRPH_SURFACE_ADDRESS_INUSE                                            0x1a13
++#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                       0x1a13
++#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                       0x1d13
++#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                       0x4013
++#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                       0x4313
++#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                       0x4613
++#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                       0x4913
++#define mmGRPH_DFQ_CONTROL                                                      0x1a14
++#define mmDCP0_GRPH_DFQ_CONTROL                                                 0x1a14
++#define mmDCP1_GRPH_DFQ_CONTROL                                                 0x1d14
++#define mmDCP2_GRPH_DFQ_CONTROL                                                 0x4014
++#define mmDCP3_GRPH_DFQ_CONTROL                                                 0x4314
++#define mmDCP4_GRPH_DFQ_CONTROL                                                 0x4614
++#define mmDCP5_GRPH_DFQ_CONTROL                                                 0x4914
++#define mmGRPH_DFQ_STATUS                                                       0x1a15
++#define mmDCP0_GRPH_DFQ_STATUS                                                  0x1a15
++#define mmDCP1_GRPH_DFQ_STATUS                                                  0x1d15
++#define mmDCP2_GRPH_DFQ_STATUS                                                  0x4015
++#define mmDCP3_GRPH_DFQ_STATUS                                                  0x4315
++#define mmDCP4_GRPH_DFQ_STATUS                                                  0x4615
++#define mmDCP5_GRPH_DFQ_STATUS                                                  0x4915
++#define mmGRPH_INTERRUPT_STATUS                                                 0x1a16
++#define mmDCP0_GRPH_INTERRUPT_STATUS                                            0x1a16
++#define mmDCP1_GRPH_INTERRUPT_STATUS                                            0x1d16
++#define mmDCP2_GRPH_INTERRUPT_STATUS                                            0x4016
++#define mmDCP3_GRPH_INTERRUPT_STATUS                                            0x4316
++#define mmDCP4_GRPH_INTERRUPT_STATUS                                            0x4616
++#define mmDCP5_GRPH_INTERRUPT_STATUS                                            0x4916
++#define mmGRPH_INTERRUPT_CONTROL                                                0x1a17
++#define mmDCP0_GRPH_INTERRUPT_CONTROL                                           0x1a17
++#define mmDCP1_GRPH_INTERRUPT_CONTROL                                           0x1d17
++#define mmDCP2_GRPH_INTERRUPT_CONTROL                                           0x4017
++#define mmDCP3_GRPH_INTERRUPT_CONTROL                                           0x4317
++#define mmDCP4_GRPH_INTERRUPT_CONTROL                                           0x4617
++#define mmDCP5_GRPH_INTERRUPT_CONTROL                                           0x4917
++#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE                                       0x1a18
++#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1a18
++#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1d18
++#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4018
++#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4318
++#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4618
++#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4918
++#define mmGRPH_COMPRESS_SURFACE_ADDRESS                                         0x1a19
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1a19
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1d19
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4019
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4319
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4619
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4919
++#define mmGRPH_COMPRESS_PITCH                                                   0x1a1a
++#define mmDCP0_GRPH_COMPRESS_PITCH                                              0x1a1a
++#define mmDCP1_GRPH_COMPRESS_PITCH                                              0x1d1a
++#define mmDCP2_GRPH_COMPRESS_PITCH                                              0x401a
++#define mmDCP3_GRPH_COMPRESS_PITCH                                              0x431a
++#define mmDCP4_GRPH_COMPRESS_PITCH                                              0x461a
++#define mmDCP5_GRPH_COMPRESS_PITCH                                              0x491a
++#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                    0x1a1b
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1a1b
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1d1b
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x401b
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x431b
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x461b
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x491b
++#define mmOVL_ENABLE                                                            0x1a1c
++#define mmDCP0_OVL_ENABLE                                                       0x1a1c
++#define mmDCP1_OVL_ENABLE                                                       0x1d1c
++#define mmDCP2_OVL_ENABLE                                                       0x401c
++#define mmDCP3_OVL_ENABLE                                                       0x431c
++#define mmDCP4_OVL_ENABLE                                                       0x461c
++#define mmDCP5_OVL_ENABLE                                                       0x491c
++#define mmOVL_CONTROL1                                                          0x1a1d
++#define mmDCP0_OVL_CONTROL1                                                     0x1a1d
++#define mmDCP1_OVL_CONTROL1                                                     0x1d1d
++#define mmDCP2_OVL_CONTROL1                                                     0x401d
++#define mmDCP3_OVL_CONTROL1                                                     0x431d
++#define mmDCP4_OVL_CONTROL1                                                     0x461d
++#define mmDCP5_OVL_CONTROL1                                                     0x491d
++#define mmOVL_CONTROL2                                                          0x1a1e
++#define mmDCP0_OVL_CONTROL2                                                     0x1a1e
++#define mmDCP1_OVL_CONTROL2                                                     0x1d1e
++#define mmDCP2_OVL_CONTROL2                                                     0x401e
++#define mmDCP3_OVL_CONTROL2                                                     0x431e
++#define mmDCP4_OVL_CONTROL2                                                     0x461e
++#define mmDCP5_OVL_CONTROL2                                                     0x491e
++#define mmOVL_SWAP_CNTL                                                         0x1a1f
++#define mmDCP0_OVL_SWAP_CNTL                                                    0x1a1f
++#define mmDCP1_OVL_SWAP_CNTL                                                    0x1d1f
++#define mmDCP2_OVL_SWAP_CNTL                                                    0x401f
++#define mmDCP3_OVL_SWAP_CNTL                                                    0x431f
++#define mmDCP4_OVL_SWAP_CNTL                                                    0x461f
++#define mmDCP5_OVL_SWAP_CNTL                                                    0x491f
++#define mmOVL_SURFACE_ADDRESS                                                   0x1a20
++#define mmDCP0_OVL_SURFACE_ADDRESS                                              0x1a20
++#define mmDCP1_OVL_SURFACE_ADDRESS                                              0x1d20
++#define mmDCP2_OVL_SURFACE_ADDRESS                                              0x4020
++#define mmDCP3_OVL_SURFACE_ADDRESS                                              0x4320
++#define mmDCP4_OVL_SURFACE_ADDRESS                                              0x4620
++#define mmDCP5_OVL_SURFACE_ADDRESS                                              0x4920
++#define mmOVL_PITCH                                                             0x1a21
++#define mmDCP0_OVL_PITCH                                                        0x1a21
++#define mmDCP1_OVL_PITCH                                                        0x1d21
++#define mmDCP2_OVL_PITCH                                                        0x4021
++#define mmDCP3_OVL_PITCH                                                        0x4321
++#define mmDCP4_OVL_PITCH                                                        0x4621
++#define mmDCP5_OVL_PITCH                                                        0x4921
++#define mmOVL_SURFACE_ADDRESS_HIGH                                              0x1a22
++#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH                                         0x1a22
++#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH                                         0x1d22
++#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH                                         0x4022
++#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH                                         0x4322
++#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH                                         0x4622
++#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH                                         0x4922
++#define mmOVL_SURFACE_OFFSET_X                                                  0x1a23
++#define mmDCP0_OVL_SURFACE_OFFSET_X                                             0x1a23
++#define mmDCP1_OVL_SURFACE_OFFSET_X                                             0x1d23
++#define mmDCP2_OVL_SURFACE_OFFSET_X                                             0x4023
++#define mmDCP3_OVL_SURFACE_OFFSET_X                                             0x4323
++#define mmDCP4_OVL_SURFACE_OFFSET_X                                             0x4623
++#define mmDCP5_OVL_SURFACE_OFFSET_X                                             0x4923
++#define mmOVL_SURFACE_OFFSET_Y                                                  0x1a24
++#define mmDCP0_OVL_SURFACE_OFFSET_Y                                             0x1a24
++#define mmDCP1_OVL_SURFACE_OFFSET_Y                                             0x1d24
++#define mmDCP2_OVL_SURFACE_OFFSET_Y                                             0x4024
++#define mmDCP3_OVL_SURFACE_OFFSET_Y                                             0x4324
++#define mmDCP4_OVL_SURFACE_OFFSET_Y                                             0x4624
++#define mmDCP5_OVL_SURFACE_OFFSET_Y                                             0x4924
++#define mmOVL_START                                                             0x1a25
++#define mmDCP0_OVL_START                                                        0x1a25
++#define mmDCP1_OVL_START                                                        0x1d25
++#define mmDCP2_OVL_START                                                        0x4025
++#define mmDCP3_OVL_START                                                        0x4325
++#define mmDCP4_OVL_START                                                        0x4625
++#define mmDCP5_OVL_START                                                        0x4925
++#define mmOVL_END                                                               0x1a26
++#define mmDCP0_OVL_END                                                          0x1a26
++#define mmDCP1_OVL_END                                                          0x1d26
++#define mmDCP2_OVL_END                                                          0x4026
++#define mmDCP3_OVL_END                                                          0x4326
++#define mmDCP4_OVL_END                                                          0x4626
++#define mmDCP5_OVL_END                                                          0x4926
++#define mmOVL_UPDATE                                                            0x1a27
++#define mmDCP0_OVL_UPDATE                                                       0x1a27
++#define mmDCP1_OVL_UPDATE                                                       0x1d27
++#define mmDCP2_OVL_UPDATE                                                       0x4027
++#define mmDCP3_OVL_UPDATE                                                       0x4327
++#define mmDCP4_OVL_UPDATE                                                       0x4627
++#define mmDCP5_OVL_UPDATE                                                       0x4927
++#define mmOVL_SURFACE_ADDRESS_INUSE                                             0x1a28
++#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE                                        0x1a28
++#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE                                        0x1d28
++#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE                                        0x4028
++#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE                                        0x4328
++#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE                                        0x4628
++#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE                                        0x4928
++#define mmOVL_DFQ_CONTROL                                                       0x1a29
++#define mmDCP0_OVL_DFQ_CONTROL                                                  0x1a29
++#define mmDCP1_OVL_DFQ_CONTROL                                                  0x1d29
++#define mmDCP2_OVL_DFQ_CONTROL                                                  0x4029
++#define mmDCP3_OVL_DFQ_CONTROL                                                  0x4329
++#define mmDCP4_OVL_DFQ_CONTROL                                                  0x4629
++#define mmDCP5_OVL_DFQ_CONTROL                                                  0x4929
++#define mmOVL_DFQ_STATUS                                                        0x1a2a
++#define mmDCP0_OVL_DFQ_STATUS                                                   0x1a2a
++#define mmDCP1_OVL_DFQ_STATUS                                                   0x1d2a
++#define mmDCP2_OVL_DFQ_STATUS                                                   0x402a
++#define mmDCP3_OVL_DFQ_STATUS                                                   0x432a
++#define mmDCP4_OVL_DFQ_STATUS                                                   0x462a
++#define mmDCP5_OVL_DFQ_STATUS                                                   0x492a
++#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE                                        0x1a2b
++#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1a2b
++#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1d2b
++#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x402b
++#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x432b
++#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x462b
++#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x492b
++#define mmOVLSCL_EDGE_PIXEL_CNTL                                                0x1a2c
++#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL                                           0x1a2c
++#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL                                           0x1d2c
++#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL                                           0x402c
++#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL                                           0x432c
++#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL                                           0x462c
++#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL                                           0x492c
++#define mmPRESCALE_GRPH_CONTROL                                                 0x1a2d
++#define mmDCP0_PRESCALE_GRPH_CONTROL                                            0x1a2d
++#define mmDCP1_PRESCALE_GRPH_CONTROL                                            0x1d2d
++#define mmDCP2_PRESCALE_GRPH_CONTROL                                            0x402d
++#define mmDCP3_PRESCALE_GRPH_CONTROL                                            0x432d
++#define mmDCP4_PRESCALE_GRPH_CONTROL                                            0x462d
++#define mmDCP5_PRESCALE_GRPH_CONTROL                                            0x492d
++#define mmPRESCALE_VALUES_GRPH_R                                                0x1a2e
++#define mmDCP0_PRESCALE_VALUES_GRPH_R                                           0x1a2e
++#define mmDCP1_PRESCALE_VALUES_GRPH_R                                           0x1d2e
++#define mmDCP2_PRESCALE_VALUES_GRPH_R                                           0x402e
++#define mmDCP3_PRESCALE_VALUES_GRPH_R                                           0x432e
++#define mmDCP4_PRESCALE_VALUES_GRPH_R                                           0x462e
++#define mmDCP5_PRESCALE_VALUES_GRPH_R                                           0x492e
++#define mmPRESCALE_VALUES_GRPH_G                                                0x1a2f
++#define mmDCP0_PRESCALE_VALUES_GRPH_G                                           0x1a2f
++#define mmDCP1_PRESCALE_VALUES_GRPH_G                                           0x1d2f
++#define mmDCP2_PRESCALE_VALUES_GRPH_G                                           0x402f
++#define mmDCP3_PRESCALE_VALUES_GRPH_G                                           0x432f
++#define mmDCP4_PRESCALE_VALUES_GRPH_G                                           0x462f
++#define mmDCP5_PRESCALE_VALUES_GRPH_G                                           0x492f
++#define mmPRESCALE_VALUES_GRPH_B                                                0x1a30
++#define mmDCP0_PRESCALE_VALUES_GRPH_B                                           0x1a30
++#define mmDCP1_PRESCALE_VALUES_GRPH_B                                           0x1d30
++#define mmDCP2_PRESCALE_VALUES_GRPH_B                                           0x4030
++#define mmDCP3_PRESCALE_VALUES_GRPH_B                                           0x4330
++#define mmDCP4_PRESCALE_VALUES_GRPH_B                                           0x4630
++#define mmDCP5_PRESCALE_VALUES_GRPH_B                                           0x4930
++#define mmPRESCALE_OVL_CONTROL                                                  0x1a31
++#define mmDCP0_PRESCALE_OVL_CONTROL                                             0x1a31
++#define mmDCP1_PRESCALE_OVL_CONTROL                                             0x1d31
++#define mmDCP2_PRESCALE_OVL_CONTROL                                             0x4031
++#define mmDCP3_PRESCALE_OVL_CONTROL                                             0x4331
++#define mmDCP4_PRESCALE_OVL_CONTROL                                             0x4631
++#define mmDCP5_PRESCALE_OVL_CONTROL                                             0x4931
++#define mmPRESCALE_VALUES_OVL_CB                                                0x1a32
++#define mmDCP0_PRESCALE_VALUES_OVL_CB                                           0x1a32
++#define mmDCP1_PRESCALE_VALUES_OVL_CB                                           0x1d32
++#define mmDCP2_PRESCALE_VALUES_OVL_CB                                           0x4032
++#define mmDCP3_PRESCALE_VALUES_OVL_CB                                           0x4332
++#define mmDCP4_PRESCALE_VALUES_OVL_CB                                           0x4632
++#define mmDCP5_PRESCALE_VALUES_OVL_CB                                           0x4932
++#define mmPRESCALE_VALUES_OVL_Y                                                 0x1a33
++#define mmDCP0_PRESCALE_VALUES_OVL_Y                                            0x1a33
++#define mmDCP1_PRESCALE_VALUES_OVL_Y                                            0x1d33
++#define mmDCP2_PRESCALE_VALUES_OVL_Y                                            0x4033
++#define mmDCP3_PRESCALE_VALUES_OVL_Y                                            0x4333
++#define mmDCP4_PRESCALE_VALUES_OVL_Y                                            0x4633
++#define mmDCP5_PRESCALE_VALUES_OVL_Y                                            0x4933
++#define mmPRESCALE_VALUES_OVL_CR                                                0x1a34
++#define mmDCP0_PRESCALE_VALUES_OVL_CR                                           0x1a34
++#define mmDCP1_PRESCALE_VALUES_OVL_CR                                           0x1d34
++#define mmDCP2_PRESCALE_VALUES_OVL_CR                                           0x4034
++#define mmDCP3_PRESCALE_VALUES_OVL_CR                                           0x4334
++#define mmDCP4_PRESCALE_VALUES_OVL_CR                                           0x4634
++#define mmDCP5_PRESCALE_VALUES_OVL_CR                                           0x4934
++#define mmINPUT_CSC_CONTROL                                                     0x1a35
++#define mmDCP0_INPUT_CSC_CONTROL                                                0x1a35
++#define mmDCP1_INPUT_CSC_CONTROL                                                0x1d35
++#define mmDCP2_INPUT_CSC_CONTROL                                                0x4035
++#define mmDCP3_INPUT_CSC_CONTROL                                                0x4335
++#define mmDCP4_INPUT_CSC_CONTROL                                                0x4635
++#define mmDCP5_INPUT_CSC_CONTROL                                                0x4935
++#define mmINPUT_CSC_C11_C12                                                     0x1a36
++#define mmDCP0_INPUT_CSC_C11_C12                                                0x1a36
++#define mmDCP1_INPUT_CSC_C11_C12                                                0x1d36
++#define mmDCP2_INPUT_CSC_C11_C12                                                0x4036
++#define mmDCP3_INPUT_CSC_C11_C12                                                0x4336
++#define mmDCP4_INPUT_CSC_C11_C12                                                0x4636
++#define mmDCP5_INPUT_CSC_C11_C12                                                0x4936
++#define mmINPUT_CSC_C13_C14                                                     0x1a37
++#define mmDCP0_INPUT_CSC_C13_C14                                                0x1a37
++#define mmDCP1_INPUT_CSC_C13_C14                                                0x1d37
++#define mmDCP2_INPUT_CSC_C13_C14                                                0x4037
++#define mmDCP3_INPUT_CSC_C13_C14                                                0x4337
++#define mmDCP4_INPUT_CSC_C13_C14                                                0x4637
++#define mmDCP5_INPUT_CSC_C13_C14                                                0x4937
++#define mmINPUT_CSC_C21_C22                                                     0x1a38
++#define mmDCP0_INPUT_CSC_C21_C22                                                0x1a38
++#define mmDCP1_INPUT_CSC_C21_C22                                                0x1d38
++#define mmDCP2_INPUT_CSC_C21_C22                                                0x4038
++#define mmDCP3_INPUT_CSC_C21_C22                                                0x4338
++#define mmDCP4_INPUT_CSC_C21_C22                                                0x4638
++#define mmDCP5_INPUT_CSC_C21_C22                                                0x4938
++#define mmINPUT_CSC_C23_C24                                                     0x1a39
++#define mmDCP0_INPUT_CSC_C23_C24                                                0x1a39
++#define mmDCP1_INPUT_CSC_C23_C24                                                0x1d39
++#define mmDCP2_INPUT_CSC_C23_C24                                                0x4039
++#define mmDCP3_INPUT_CSC_C23_C24                                                0x4339
++#define mmDCP4_INPUT_CSC_C23_C24                                                0x4639
++#define mmDCP5_INPUT_CSC_C23_C24                                                0x4939
++#define mmINPUT_CSC_C31_C32                                                     0x1a3a
++#define mmDCP0_INPUT_CSC_C31_C32                                                0x1a3a
++#define mmDCP1_INPUT_CSC_C31_C32                                                0x1d3a
++#define mmDCP2_INPUT_CSC_C31_C32                                                0x403a
++#define mmDCP3_INPUT_CSC_C31_C32                                                0x433a
++#define mmDCP4_INPUT_CSC_C31_C32                                                0x463a
++#define mmDCP5_INPUT_CSC_C31_C32                                                0x493a
++#define mmINPUT_CSC_C33_C34                                                     0x1a3b
++#define mmDCP0_INPUT_CSC_C33_C34                                                0x1a3b
++#define mmDCP1_INPUT_CSC_C33_C34                                                0x1d3b
++#define mmDCP2_INPUT_CSC_C33_C34                                                0x403b
++#define mmDCP3_INPUT_CSC_C33_C34                                                0x433b
++#define mmDCP4_INPUT_CSC_C33_C34                                                0x463b
++#define mmDCP5_INPUT_CSC_C33_C34                                                0x493b
++#define mmOUTPUT_CSC_CONTROL                                                    0x1a3c
++#define mmDCP0_OUTPUT_CSC_CONTROL                                               0x1a3c
++#define mmDCP1_OUTPUT_CSC_CONTROL                                               0x1d3c
++#define mmDCP2_OUTPUT_CSC_CONTROL                                               0x403c
++#define mmDCP3_OUTPUT_CSC_CONTROL                                               0x433c
++#define mmDCP4_OUTPUT_CSC_CONTROL                                               0x463c
++#define mmDCP5_OUTPUT_CSC_CONTROL                                               0x493c
++#define mmOUTPUT_CSC_C11_C12                                                    0x1a3d
++#define mmDCP0_OUTPUT_CSC_C11_C12                                               0x1a3d
++#define mmDCP1_OUTPUT_CSC_C11_C12                                               0x1d3d
++#define mmDCP2_OUTPUT_CSC_C11_C12                                               0x403d
++#define mmDCP3_OUTPUT_CSC_C11_C12                                               0x433d
++#define mmDCP4_OUTPUT_CSC_C11_C12                                               0x463d
++#define mmDCP5_OUTPUT_CSC_C11_C12                                               0x493d
++#define mmOUTPUT_CSC_C13_C14                                                    0x1a3e
++#define mmDCP0_OUTPUT_CSC_C13_C14                                               0x1a3e
++#define mmDCP1_OUTPUT_CSC_C13_C14                                               0x1d3e
++#define mmDCP2_OUTPUT_CSC_C13_C14                                               0x403e
++#define mmDCP3_OUTPUT_CSC_C13_C14                                               0x433e
++#define mmDCP4_OUTPUT_CSC_C13_C14                                               0x463e
++#define mmDCP5_OUTPUT_CSC_C13_C14                                               0x493e
++#define mmOUTPUT_CSC_C21_C22                                                    0x1a3f
++#define mmDCP0_OUTPUT_CSC_C21_C22                                               0x1a3f
++#define mmDCP1_OUTPUT_CSC_C21_C22                                               0x1d3f
++#define mmDCP2_OUTPUT_CSC_C21_C22                                               0x403f
++#define mmDCP3_OUTPUT_CSC_C21_C22                                               0x433f
++#define mmDCP4_OUTPUT_CSC_C21_C22                                               0x463f
++#define mmDCP5_OUTPUT_CSC_C21_C22                                               0x493f
++#define mmOUTPUT_CSC_C23_C24                                                    0x1a40
++#define mmDCP0_OUTPUT_CSC_C23_C24                                               0x1a40
++#define mmDCP1_OUTPUT_CSC_C23_C24                                               0x1d40
++#define mmDCP2_OUTPUT_CSC_C23_C24                                               0x4040
++#define mmDCP3_OUTPUT_CSC_C23_C24                                               0x4340
++#define mmDCP4_OUTPUT_CSC_C23_C24                                               0x4640
++#define mmDCP5_OUTPUT_CSC_C23_C24                                               0x4940
++#define mmOUTPUT_CSC_C31_C32                                                    0x1a41
++#define mmDCP0_OUTPUT_CSC_C31_C32                                               0x1a41
++#define mmDCP1_OUTPUT_CSC_C31_C32                                               0x1d41
++#define mmDCP2_OUTPUT_CSC_C31_C32                                               0x4041
++#define mmDCP3_OUTPUT_CSC_C31_C32                                               0x4341
++#define mmDCP4_OUTPUT_CSC_C31_C32                                               0x4641
++#define mmDCP5_OUTPUT_CSC_C31_C32                                               0x4941
++#define mmOUTPUT_CSC_C33_C34                                                    0x1a42
++#define mmDCP0_OUTPUT_CSC_C33_C34                                               0x1a42
++#define mmDCP1_OUTPUT_CSC_C33_C34                                               0x1d42
++#define mmDCP2_OUTPUT_CSC_C33_C34                                               0x4042
++#define mmDCP3_OUTPUT_CSC_C33_C34                                               0x4342
++#define mmDCP4_OUTPUT_CSC_C33_C34                                               0x4642
++#define mmDCP5_OUTPUT_CSC_C33_C34                                               0x4942
++#define mmCOMM_MATRIXA_TRANS_C11_C12                                            0x1a43
++#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                       0x1a43
++#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                       0x1d43
++#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                       0x4043
++#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                       0x4343
++#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                       0x4643
++#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                       0x4943
++#define mmCOMM_MATRIXA_TRANS_C13_C14                                            0x1a44
++#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                       0x1a44
++#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                       0x1d44
++#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                       0x4044
++#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                       0x4344
++#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                       0x4644
++#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                       0x4944
++#define mmCOMM_MATRIXA_TRANS_C21_C22                                            0x1a45
++#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                       0x1a45
++#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                       0x1d45
++#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                       0x4045
++#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                       0x4345
++#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                       0x4645
++#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                       0x4945
++#define mmCOMM_MATRIXA_TRANS_C23_C24                                            0x1a46
++#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                       0x1a46
++#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                       0x1d46
++#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                       0x4046
++#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                       0x4346
++#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                       0x4646
++#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                       0x4946
++#define mmCOMM_MATRIXA_TRANS_C31_C32                                            0x1a47
++#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                       0x1a47
++#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                       0x1d47
++#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                       0x4047
++#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                       0x4347
++#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                       0x4647
++#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                       0x4947
++#define mmCOMM_MATRIXA_TRANS_C33_C34                                            0x1a48
++#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                       0x1a48
++#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                       0x1d48
++#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                       0x4048
++#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                       0x4348
++#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                       0x4648
++#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                       0x4948
++#define mmCOMM_MATRIXB_TRANS_C11_C12                                            0x1a49
++#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                       0x1a49
++#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                       0x1d49
++#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                       0x4049
++#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                       0x4349
++#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                       0x4649
++#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                       0x4949
++#define mmCOMM_MATRIXB_TRANS_C13_C14                                            0x1a4a
++#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                       0x1a4a
++#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                       0x1d4a
++#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                       0x404a
++#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                       0x434a
++#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                       0x464a
++#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                       0x494a
++#define mmCOMM_MATRIXB_TRANS_C21_C22                                            0x1a4b
++#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                       0x1a4b
++#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                       0x1d4b
++#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                       0x404b
++#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                       0x434b
++#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                       0x464b
++#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                       0x494b
++#define mmCOMM_MATRIXB_TRANS_C23_C24                                            0x1a4c
++#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                       0x1a4c
++#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                       0x1d4c
++#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                       0x404c
++#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                       0x434c
++#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                       0x464c
++#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                       0x494c
++#define mmCOMM_MATRIXB_TRANS_C31_C32                                            0x1a4d
++#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                       0x1a4d
++#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                       0x1d4d
++#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                       0x404d
++#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                       0x434d
++#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                       0x464d
++#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                       0x494d
++#define mmCOMM_MATRIXB_TRANS_C33_C34                                            0x1a4e
++#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                       0x1a4e
++#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                       0x1d4e
++#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                       0x404e
++#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                       0x434e
++#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                       0x464e
++#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                       0x494e
++#define mmDENORM_CONTROL                                                        0x1a50
++#define mmDCP0_DENORM_CONTROL                                                   0x1a50
++#define mmDCP1_DENORM_CONTROL                                                   0x1d50
++#define mmDCP2_DENORM_CONTROL                                                   0x4050
++#define mmDCP3_DENORM_CONTROL                                                   0x4350
++#define mmDCP4_DENORM_CONTROL                                                   0x4650
++#define mmDCP5_DENORM_CONTROL                                                   0x4950
++#define mmOUT_ROUND_CONTROL                                                     0x1a51
++#define mmDCP0_OUT_ROUND_CONTROL                                                0x1a51
++#define mmDCP1_OUT_ROUND_CONTROL                                                0x1d51
++#define mmDCP2_OUT_ROUND_CONTROL                                                0x4051
++#define mmDCP3_OUT_ROUND_CONTROL                                                0x4351
++#define mmDCP4_OUT_ROUND_CONTROL                                                0x4651
++#define mmDCP5_OUT_ROUND_CONTROL                                                0x4951
++#define mmOUT_CLAMP_CONTROL_R_CR                                                0x1a52
++#define mmDCP0_OUT_CLAMP_CONTROL_R_CR                                           0x1a52
++#define mmDCP1_OUT_CLAMP_CONTROL_R_CR                                           0x1d52
++#define mmDCP2_OUT_CLAMP_CONTROL_R_CR                                           0x4052
++#define mmDCP3_OUT_CLAMP_CONTROL_R_CR                                           0x4352
++#define mmDCP4_OUT_CLAMP_CONTROL_R_CR                                           0x4652
++#define mmDCP5_OUT_CLAMP_CONTROL_R_CR                                           0x4952
++#define mmOUT_CLAMP_CONTROL_G_Y                                                 0x1a9c
++#define mmDCP0_OUT_CLAMP_CONTROL_G_Y                                            0x1a9c
++#define mmDCP1_OUT_CLAMP_CONTROL_G_Y                                            0x1d9c
++#define mmDCP2_OUT_CLAMP_CONTROL_G_Y                                            0x409c
++#define mmDCP3_OUT_CLAMP_CONTROL_G_Y                                            0x439c
++#define mmDCP4_OUT_CLAMP_CONTROL_G_Y                                            0x469c
++#define mmDCP5_OUT_CLAMP_CONTROL_G_Y                                            0x499c
++#define mmOUT_CLAMP_CONTROL_B_CB                                                0x1a9d
++#define mmDCP0_OUT_CLAMP_CONTROL_B_CB                                           0x1a9d
++#define mmDCP1_OUT_CLAMP_CONTROL_B_CB                                           0x1d9d
++#define mmDCP2_OUT_CLAMP_CONTROL_B_CB                                           0x409d
++#define mmDCP3_OUT_CLAMP_CONTROL_B_CB                                           0x439d
++#define mmDCP4_OUT_CLAMP_CONTROL_B_CB                                           0x469d
++#define mmDCP5_OUT_CLAMP_CONTROL_B_CB                                           0x499d
++#define mmKEY_CONTROL                                                           0x1a53
++#define mmDCP0_KEY_CONTROL                                                      0x1a53
++#define mmDCP1_KEY_CONTROL                                                      0x1d53
++#define mmDCP2_KEY_CONTROL                                                      0x4053
++#define mmDCP3_KEY_CONTROL                                                      0x4353
++#define mmDCP4_KEY_CONTROL                                                      0x4653
++#define mmDCP5_KEY_CONTROL                                                      0x4953
++#define mmKEY_RANGE_ALPHA                                                       0x1a54
++#define mmDCP0_KEY_RANGE_ALPHA                                                  0x1a54
++#define mmDCP1_KEY_RANGE_ALPHA                                                  0x1d54
++#define mmDCP2_KEY_RANGE_ALPHA                                                  0x4054
++#define mmDCP3_KEY_RANGE_ALPHA                                                  0x4354
++#define mmDCP4_KEY_RANGE_ALPHA                                                  0x4654
++#define mmDCP5_KEY_RANGE_ALPHA                                                  0x4954
++#define mmKEY_RANGE_RED                                                         0x1a55
++#define mmDCP0_KEY_RANGE_RED                                                    0x1a55
++#define mmDCP1_KEY_RANGE_RED                                                    0x1d55
++#define mmDCP2_KEY_RANGE_RED                                                    0x4055
++#define mmDCP3_KEY_RANGE_RED                                                    0x4355
++#define mmDCP4_KEY_RANGE_RED                                                    0x4655
++#define mmDCP5_KEY_RANGE_RED                                                    0x4955
++#define mmKEY_RANGE_GREEN                                                       0x1a56
++#define mmDCP0_KEY_RANGE_GREEN                                                  0x1a56
++#define mmDCP1_KEY_RANGE_GREEN                                                  0x1d56
++#define mmDCP2_KEY_RANGE_GREEN                                                  0x4056
++#define mmDCP3_KEY_RANGE_GREEN                                                  0x4356
++#define mmDCP4_KEY_RANGE_GREEN                                                  0x4656
++#define mmDCP5_KEY_RANGE_GREEN                                                  0x4956
++#define mmKEY_RANGE_BLUE                                                        0x1a57
++#define mmDCP0_KEY_RANGE_BLUE                                                   0x1a57
++#define mmDCP1_KEY_RANGE_BLUE                                                   0x1d57
++#define mmDCP2_KEY_RANGE_BLUE                                                   0x4057
++#define mmDCP3_KEY_RANGE_BLUE                                                   0x4357
++#define mmDCP4_KEY_RANGE_BLUE                                                   0x4657
++#define mmDCP5_KEY_RANGE_BLUE                                                   0x4957
++#define mmDEGAMMA_CONTROL                                                       0x1a58
++#define mmDCP0_DEGAMMA_CONTROL                                                  0x1a58
++#define mmDCP1_DEGAMMA_CONTROL                                                  0x1d58
++#define mmDCP2_DEGAMMA_CONTROL                                                  0x4058
++#define mmDCP3_DEGAMMA_CONTROL                                                  0x4358
++#define mmDCP4_DEGAMMA_CONTROL                                                  0x4658
++#define mmDCP5_DEGAMMA_CONTROL                                                  0x4958
++#define mmGAMUT_REMAP_CONTROL                                                   0x1a59
++#define mmDCP0_GAMUT_REMAP_CONTROL                                              0x1a59
++#define mmDCP1_GAMUT_REMAP_CONTROL                                              0x1d59
++#define mmDCP2_GAMUT_REMAP_CONTROL                                              0x4059
++#define mmDCP3_GAMUT_REMAP_CONTROL                                              0x4359
++#define mmDCP4_GAMUT_REMAP_CONTROL                                              0x4659
++#define mmDCP5_GAMUT_REMAP_CONTROL                                              0x4959
++#define mmGAMUT_REMAP_C11_C12                                                   0x1a5a
++#define mmDCP0_GAMUT_REMAP_C11_C12                                              0x1a5a
++#define mmDCP1_GAMUT_REMAP_C11_C12                                              0x1d5a
++#define mmDCP2_GAMUT_REMAP_C11_C12                                              0x405a
++#define mmDCP3_GAMUT_REMAP_C11_C12                                              0x435a
++#define mmDCP4_GAMUT_REMAP_C11_C12                                              0x465a
++#define mmDCP5_GAMUT_REMAP_C11_C12                                              0x495a
++#define mmGAMUT_REMAP_C13_C14                                                   0x1a5b
++#define mmDCP0_GAMUT_REMAP_C13_C14                                              0x1a5b
++#define mmDCP1_GAMUT_REMAP_C13_C14                                              0x1d5b
++#define mmDCP2_GAMUT_REMAP_C13_C14                                              0x405b
++#define mmDCP3_GAMUT_REMAP_C13_C14                                              0x435b
++#define mmDCP4_GAMUT_REMAP_C13_C14                                              0x465b
++#define mmDCP5_GAMUT_REMAP_C13_C14                                              0x495b
++#define mmGAMUT_REMAP_C21_C22                                                   0x1a5c
++#define mmDCP0_GAMUT_REMAP_C21_C22                                              0x1a5c
++#define mmDCP1_GAMUT_REMAP_C21_C22                                              0x1d5c
++#define mmDCP2_GAMUT_REMAP_C21_C22                                              0x405c
++#define mmDCP3_GAMUT_REMAP_C21_C22                                              0x435c
++#define mmDCP4_GAMUT_REMAP_C21_C22                                              0x465c
++#define mmDCP5_GAMUT_REMAP_C21_C22                                              0x495c
++#define mmGAMUT_REMAP_C23_C24                                                   0x1a5d
++#define mmDCP0_GAMUT_REMAP_C23_C24                                              0x1a5d
++#define mmDCP1_GAMUT_REMAP_C23_C24                                              0x1d5d
++#define mmDCP2_GAMUT_REMAP_C23_C24                                              0x405d
++#define mmDCP3_GAMUT_REMAP_C23_C24                                              0x435d
++#define mmDCP4_GAMUT_REMAP_C23_C24                                              0x465d
++#define mmDCP5_GAMUT_REMAP_C23_C24                                              0x495d
++#define mmGAMUT_REMAP_C31_C32                                                   0x1a5e
++#define mmDCP0_GAMUT_REMAP_C31_C32                                              0x1a5e
++#define mmDCP1_GAMUT_REMAP_C31_C32                                              0x1d5e
++#define mmDCP2_GAMUT_REMAP_C31_C32                                              0x405e
++#define mmDCP3_GAMUT_REMAP_C31_C32                                              0x435e
++#define mmDCP4_GAMUT_REMAP_C31_C32                                              0x465e
++#define mmDCP5_GAMUT_REMAP_C31_C32                                              0x495e
++#define mmGAMUT_REMAP_C33_C34                                                   0x1a5f
++#define mmDCP0_GAMUT_REMAP_C33_C34                                              0x1a5f
++#define mmDCP1_GAMUT_REMAP_C33_C34                                              0x1d5f
++#define mmDCP2_GAMUT_REMAP_C33_C34                                              0x405f
++#define mmDCP3_GAMUT_REMAP_C33_C34                                              0x435f
++#define mmDCP4_GAMUT_REMAP_C33_C34                                              0x465f
++#define mmDCP5_GAMUT_REMAP_C33_C34                                              0x495f
++#define mmDCP_SPATIAL_DITHER_CNTL                                               0x1a60
++#define mmDCP0_DCP_SPATIAL_DITHER_CNTL                                          0x1a60
++#define mmDCP1_DCP_SPATIAL_DITHER_CNTL                                          0x1d60
++#define mmDCP2_DCP_SPATIAL_DITHER_CNTL                                          0x4060
++#define mmDCP3_DCP_SPATIAL_DITHER_CNTL                                          0x4360
++#define mmDCP4_DCP_SPATIAL_DITHER_CNTL                                          0x4660
++#define mmDCP5_DCP_SPATIAL_DITHER_CNTL                                          0x4960
++#define mmDCP_RANDOM_SEEDS                                                      0x1a61
++#define mmDCP0_DCP_RANDOM_SEEDS                                                 0x1a61
++#define mmDCP1_DCP_RANDOM_SEEDS                                                 0x1d61
++#define mmDCP2_DCP_RANDOM_SEEDS                                                 0x4061
++#define mmDCP3_DCP_RANDOM_SEEDS                                                 0x4361
++#define mmDCP4_DCP_RANDOM_SEEDS                                                 0x4661
++#define mmDCP5_DCP_RANDOM_SEEDS                                                 0x4961
++#define mmDCP_FP_CONVERTED_FIELD                                                0x1a65
++#define mmDCP0_DCP_FP_CONVERTED_FIELD                                           0x1a65
++#define mmDCP1_DCP_FP_CONVERTED_FIELD                                           0x1d65
++#define mmDCP2_DCP_FP_CONVERTED_FIELD                                           0x4065
++#define mmDCP3_DCP_FP_CONVERTED_FIELD                                           0x4365
++#define mmDCP4_DCP_FP_CONVERTED_FIELD                                           0x4665
++#define mmDCP5_DCP_FP_CONVERTED_FIELD                                           0x4965
++#define mmCUR_CONTROL                                                           0x1a66
++#define mmDCP0_CUR_CONTROL                                                      0x1a66
++#define mmDCP1_CUR_CONTROL                                                      0x1d66
++#define mmDCP2_CUR_CONTROL                                                      0x4066
++#define mmDCP3_CUR_CONTROL                                                      0x4366
++#define mmDCP4_CUR_CONTROL                                                      0x4666
++#define mmDCP5_CUR_CONTROL                                                      0x4966
++#define mmCUR_SURFACE_ADDRESS                                                   0x1a67
++#define mmDCP0_CUR_SURFACE_ADDRESS                                              0x1a67
++#define mmDCP1_CUR_SURFACE_ADDRESS                                              0x1d67
++#define mmDCP2_CUR_SURFACE_ADDRESS                                              0x4067
++#define mmDCP3_CUR_SURFACE_ADDRESS                                              0x4367
++#define mmDCP4_CUR_SURFACE_ADDRESS                                              0x4667
++#define mmDCP5_CUR_SURFACE_ADDRESS                                              0x4967
++#define mmCUR_SIZE                                                              0x1a68
++#define mmDCP0_CUR_SIZE                                                         0x1a68
++#define mmDCP1_CUR_SIZE                                                         0x1d68
++#define mmDCP2_CUR_SIZE                                                         0x4068
++#define mmDCP3_CUR_SIZE                                                         0x4368
++#define mmDCP4_CUR_SIZE                                                         0x4668
++#define mmDCP5_CUR_SIZE                                                         0x4968
++#define mmCUR_SURFACE_ADDRESS_HIGH                                              0x1a69
++#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                         0x1a69
++#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                         0x1d69
++#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                         0x4069
++#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                         0x4369
++#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                         0x4669
++#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                         0x4969
++#define mmCUR_POSITION                                                          0x1a6a
++#define mmDCP0_CUR_POSITION                                                     0x1a6a
++#define mmDCP1_CUR_POSITION                                                     0x1d6a
++#define mmDCP2_CUR_POSITION                                                     0x406a
++#define mmDCP3_CUR_POSITION                                                     0x436a
++#define mmDCP4_CUR_POSITION                                                     0x466a
++#define mmDCP5_CUR_POSITION                                                     0x496a
++#define mmCUR_HOT_SPOT                                                          0x1a6b
++#define mmDCP0_CUR_HOT_SPOT                                                     0x1a6b
++#define mmDCP1_CUR_HOT_SPOT                                                     0x1d6b
++#define mmDCP2_CUR_HOT_SPOT                                                     0x406b
++#define mmDCP3_CUR_HOT_SPOT                                                     0x436b
++#define mmDCP4_CUR_HOT_SPOT                                                     0x466b
++#define mmDCP5_CUR_HOT_SPOT                                                     0x496b
++#define mmCUR_COLOR1                                                            0x1a6c
++#define mmDCP0_CUR_COLOR1                                                       0x1a6c
++#define mmDCP1_CUR_COLOR1                                                       0x1d6c
++#define mmDCP2_CUR_COLOR1                                                       0x406c
++#define mmDCP3_CUR_COLOR1                                                       0x436c
++#define mmDCP4_CUR_COLOR1                                                       0x466c
++#define mmDCP5_CUR_COLOR1                                                       0x496c
++#define mmCUR_COLOR2                                                            0x1a6d
++#define mmDCP0_CUR_COLOR2                                                       0x1a6d
++#define mmDCP1_CUR_COLOR2                                                       0x1d6d
++#define mmDCP2_CUR_COLOR2                                                       0x406d
++#define mmDCP3_CUR_COLOR2                                                       0x436d
++#define mmDCP4_CUR_COLOR2                                                       0x466d
++#define mmDCP5_CUR_COLOR2                                                       0x496d
++#define mmCUR_UPDATE                                                            0x1a6e
++#define mmDCP0_CUR_UPDATE                                                       0x1a6e
++#define mmDCP1_CUR_UPDATE                                                       0x1d6e
++#define mmDCP2_CUR_UPDATE                                                       0x406e
++#define mmDCP3_CUR_UPDATE                                                       0x436e
++#define mmDCP4_CUR_UPDATE                                                       0x466e
++#define mmDCP5_CUR_UPDATE                                                       0x496e
++#define mmCUR2_CONTROL                                                          0x1a6f
++#define mmDCP0_CUR2_CONTROL                                                     0x1a6f
++#define mmDCP1_CUR2_CONTROL                                                     0x1d6f
++#define mmDCP2_CUR2_CONTROL                                                     0x406f
++#define mmDCP3_CUR2_CONTROL                                                     0x436f
++#define mmDCP4_CUR2_CONTROL                                                     0x466f
++#define mmDCP5_CUR2_CONTROL                                                     0x496f
++#define mmCUR2_SURFACE_ADDRESS                                                  0x1a70
++#define mmDCP0_CUR2_SURFACE_ADDRESS                                             0x1a70
++#define mmDCP1_CUR2_SURFACE_ADDRESS                                             0x1d70
++#define mmDCP2_CUR2_SURFACE_ADDRESS                                             0x4070
++#define mmDCP3_CUR2_SURFACE_ADDRESS                                             0x4370
++#define mmDCP4_CUR2_SURFACE_ADDRESS                                             0x4670
++#define mmDCP5_CUR2_SURFACE_ADDRESS                                             0x4970
++#define mmCUR2_SIZE                                                             0x1a71
++#define mmDCP0_CUR2_SIZE                                                        0x1a71
++#define mmDCP1_CUR2_SIZE                                                        0x1d71
++#define mmDCP2_CUR2_SIZE                                                        0x4071
++#define mmDCP3_CUR2_SIZE                                                        0x4371
++#define mmDCP4_CUR2_SIZE                                                        0x4671
++#define mmDCP5_CUR2_SIZE                                                        0x4971
++#define mmCUR2_SURFACE_ADDRESS_HIGH                                             0x1a72
++#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH                                        0x1a72
++#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH                                        0x1d72
++#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH                                        0x4072
++#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH                                        0x4372
++#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH                                        0x4672
++#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH                                        0x4972
++#define mmCUR2_POSITION                                                         0x1a73
++#define mmDCP0_CUR2_POSITION                                                    0x1a73
++#define mmDCP1_CUR2_POSITION                                                    0x1d73
++#define mmDCP2_CUR2_POSITION                                                    0x4073
++#define mmDCP3_CUR2_POSITION                                                    0x4373
++#define mmDCP4_CUR2_POSITION                                                    0x4673
++#define mmDCP5_CUR2_POSITION                                                    0x4973
++#define mmCUR2_HOT_SPOT                                                         0x1a74
++#define mmDCP0_CUR2_HOT_SPOT                                                    0x1a74
++#define mmDCP1_CUR2_HOT_SPOT                                                    0x1d74
++#define mmDCP2_CUR2_HOT_SPOT                                                    0x4074
++#define mmDCP3_CUR2_HOT_SPOT                                                    0x4374
++#define mmDCP4_CUR2_HOT_SPOT                                                    0x4674
++#define mmDCP5_CUR2_HOT_SPOT                                                    0x4974
++#define mmCUR2_COLOR1                                                           0x1a75
++#define mmDCP0_CUR2_COLOR1                                                      0x1a75
++#define mmDCP1_CUR2_COLOR1                                                      0x1d75
++#define mmDCP2_CUR2_COLOR1                                                      0x4075
++#define mmDCP3_CUR2_COLOR1                                                      0x4375
++#define mmDCP4_CUR2_COLOR1                                                      0x4675
++#define mmDCP5_CUR2_COLOR1                                                      0x4975
++#define mmCUR2_COLOR2                                                           0x1a76
++#define mmDCP0_CUR2_COLOR2                                                      0x1a76
++#define mmDCP1_CUR2_COLOR2                                                      0x1d76
++#define mmDCP2_CUR2_COLOR2                                                      0x4076
++#define mmDCP3_CUR2_COLOR2                                                      0x4376
++#define mmDCP4_CUR2_COLOR2                                                      0x4676
++#define mmDCP5_CUR2_COLOR2                                                      0x4976
++#define mmCUR2_UPDATE                                                           0x1a77
++#define mmDCP0_CUR2_UPDATE                                                      0x1a77
++#define mmDCP1_CUR2_UPDATE                                                      0x1d77
++#define mmDCP2_CUR2_UPDATE                                                      0x4077
++#define mmDCP3_CUR2_UPDATE                                                      0x4377
++#define mmDCP4_CUR2_UPDATE                                                      0x4677
++#define mmDCP5_CUR2_UPDATE                                                      0x4977
++#define mmCUR_REQUEST_FILTER_CNTL                                               0x1a99
++#define mmDCP0_CUR_REQUEST_FILTER_CNTL                                          0x1a99
++#define mmDCP1_CUR_REQUEST_FILTER_CNTL                                          0x1d99
++#define mmDCP2_CUR_REQUEST_FILTER_CNTL                                          0x4099
++#define mmDCP3_CUR_REQUEST_FILTER_CNTL                                          0x4399
++#define mmDCP4_CUR_REQUEST_FILTER_CNTL                                          0x4699
++#define mmDCP5_CUR_REQUEST_FILTER_CNTL                                          0x4999
++#define mmCUR_STEREO_CONTROL                                                    0x1a9a
++#define mmDCP0_CUR_STEREO_CONTROL                                               0x1a9a
++#define mmDCP1_CUR_STEREO_CONTROL                                               0x1d9a
++#define mmDCP2_CUR_STEREO_CONTROL                                               0x409a
++#define mmDCP3_CUR_STEREO_CONTROL                                               0x439a
++#define mmDCP4_CUR_STEREO_CONTROL                                               0x469a
++#define mmDCP5_CUR_STEREO_CONTROL                                               0x499a
++#define mmCUR2_STEREO_CONTROL                                                   0x1a9b
++#define mmDCP0_CUR2_STEREO_CONTROL                                              0x1a9b
++#define mmDCP1_CUR2_STEREO_CONTROL                                              0x1d9b
++#define mmDCP2_CUR2_STEREO_CONTROL                                              0x409b
++#define mmDCP3_CUR2_STEREO_CONTROL                                              0x439b
++#define mmDCP4_CUR2_STEREO_CONTROL                                              0x469b
++#define mmDCP5_CUR2_STEREO_CONTROL                                              0x499b
++#define mmDC_LUT_RW_MODE                                                        0x1a78
++#define mmDCP0_DC_LUT_RW_MODE                                                   0x1a78
++#define mmDCP1_DC_LUT_RW_MODE                                                   0x1d78
++#define mmDCP2_DC_LUT_RW_MODE                                                   0x4078
++#define mmDCP3_DC_LUT_RW_MODE                                                   0x4378
++#define mmDCP4_DC_LUT_RW_MODE                                                   0x4678
++#define mmDCP5_DC_LUT_RW_MODE                                                   0x4978
++#define mmDC_LUT_RW_INDEX                                                       0x1a79
++#define mmDCP0_DC_LUT_RW_INDEX                                                  0x1a79
++#define mmDCP1_DC_LUT_RW_INDEX                                                  0x1d79
++#define mmDCP2_DC_LUT_RW_INDEX                                                  0x4079
++#define mmDCP3_DC_LUT_RW_INDEX                                                  0x4379
++#define mmDCP4_DC_LUT_RW_INDEX                                                  0x4679
++#define mmDCP5_DC_LUT_RW_INDEX                                                  0x4979
++#define mmDC_LUT_SEQ_COLOR                                                      0x1a7a
++#define mmDCP0_DC_LUT_SEQ_COLOR                                                 0x1a7a
++#define mmDCP1_DC_LUT_SEQ_COLOR                                                 0x1d7a
++#define mmDCP2_DC_LUT_SEQ_COLOR                                                 0x407a
++#define mmDCP3_DC_LUT_SEQ_COLOR                                                 0x437a
++#define mmDCP4_DC_LUT_SEQ_COLOR                                                 0x467a
++#define mmDCP5_DC_LUT_SEQ_COLOR                                                 0x497a
++#define mmDC_LUT_PWL_DATA                                                       0x1a7b
++#define mmDCP0_DC_LUT_PWL_DATA                                                  0x1a7b
++#define mmDCP1_DC_LUT_PWL_DATA                                                  0x1d7b
++#define mmDCP2_DC_LUT_PWL_DATA                                                  0x407b
++#define mmDCP3_DC_LUT_PWL_DATA                                                  0x437b
++#define mmDCP4_DC_LUT_PWL_DATA                                                  0x467b
++#define mmDCP5_DC_LUT_PWL_DATA                                                  0x497b
++#define mmDC_LUT_30_COLOR                                                       0x1a7c
++#define mmDCP0_DC_LUT_30_COLOR                                                  0x1a7c
++#define mmDCP1_DC_LUT_30_COLOR                                                  0x1d7c
++#define mmDCP2_DC_LUT_30_COLOR                                                  0x407c
++#define mmDCP3_DC_LUT_30_COLOR                                                  0x437c
++#define mmDCP4_DC_LUT_30_COLOR                                                  0x467c
++#define mmDCP5_DC_LUT_30_COLOR                                                  0x497c
++#define mmDC_LUT_VGA_ACCESS_ENABLE                                              0x1a7d
++#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                         0x1a7d
++#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                         0x1d7d
++#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                         0x407d
++#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                         0x437d
++#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                         0x467d
++#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                         0x497d
++#define mmDC_LUT_WRITE_EN_MASK                                                  0x1a7e
++#define mmDCP0_DC_LUT_WRITE_EN_MASK                                             0x1a7e
++#define mmDCP1_DC_LUT_WRITE_EN_MASK                                             0x1d7e
++#define mmDCP2_DC_LUT_WRITE_EN_MASK                                             0x407e
++#define mmDCP3_DC_LUT_WRITE_EN_MASK                                             0x437e
++#define mmDCP4_DC_LUT_WRITE_EN_MASK                                             0x467e
++#define mmDCP5_DC_LUT_WRITE_EN_MASK                                             0x497e
++#define mmDC_LUT_AUTOFILL                                                       0x1a7f
++#define mmDCP0_DC_LUT_AUTOFILL                                                  0x1a7f
++#define mmDCP1_DC_LUT_AUTOFILL                                                  0x1d7f
++#define mmDCP2_DC_LUT_AUTOFILL                                                  0x407f
++#define mmDCP3_DC_LUT_AUTOFILL                                                  0x437f
++#define mmDCP4_DC_LUT_AUTOFILL                                                  0x467f
++#define mmDCP5_DC_LUT_AUTOFILL                                                  0x497f
++#define mmDC_LUT_CONTROL                                                        0x1a80
++#define mmDCP0_DC_LUT_CONTROL                                                   0x1a80
++#define mmDCP1_DC_LUT_CONTROL                                                   0x1d80
++#define mmDCP2_DC_LUT_CONTROL                                                   0x4080
++#define mmDCP3_DC_LUT_CONTROL                                                   0x4380
++#define mmDCP4_DC_LUT_CONTROL                                                   0x4680
++#define mmDCP5_DC_LUT_CONTROL                                                   0x4980
++#define mmDC_LUT_BLACK_OFFSET_BLUE                                              0x1a81
++#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                         0x1a81
++#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                         0x1d81
++#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                         0x4081
++#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                         0x4381
++#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                         0x4681
++#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                         0x4981
++#define mmDC_LUT_BLACK_OFFSET_GREEN                                             0x1a82
++#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                        0x1a82
++#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                        0x1d82
++#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                        0x4082
++#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                        0x4382
++#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                        0x4682
++#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                        0x4982
++#define mmDC_LUT_BLACK_OFFSET_RED                                               0x1a83
++#define mmDCP0_DC_LUT_BLACK_OFFSET_RED                                          0x1a83
++#define mmDCP1_DC_LUT_BLACK_OFFSET_RED                                          0x1d83
++#define mmDCP2_DC_LUT_BLACK_OFFSET_RED                                          0x4083
++#define mmDCP3_DC_LUT_BLACK_OFFSET_RED                                          0x4383
++#define mmDCP4_DC_LUT_BLACK_OFFSET_RED                                          0x4683
++#define mmDCP5_DC_LUT_BLACK_OFFSET_RED                                          0x4983
++#define mmDC_LUT_WHITE_OFFSET_BLUE                                              0x1a84
++#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                         0x1a84
++#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                         0x1d84
++#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                         0x4084
++#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                         0x4384
++#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                         0x4684
++#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                         0x4984
++#define mmDC_LUT_WHITE_OFFSET_GREEN                                             0x1a85
++#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                        0x1a85
++#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                        0x1d85
++#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                        0x4085
++#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                        0x4385
++#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                        0x4685
++#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                        0x4985
++#define mmDC_LUT_WHITE_OFFSET_RED                                               0x1a86
++#define mmDCP0_DC_LUT_WHITE_OFFSET_RED                                          0x1a86
++#define mmDCP1_DC_LUT_WHITE_OFFSET_RED                                          0x1d86
++#define mmDCP2_DC_LUT_WHITE_OFFSET_RED                                          0x4086
++#define mmDCP3_DC_LUT_WHITE_OFFSET_RED                                          0x4386
++#define mmDCP4_DC_LUT_WHITE_OFFSET_RED                                          0x4686
++#define mmDCP5_DC_LUT_WHITE_OFFSET_RED                                          0x4986
++#define mmDCP_CRC_CONTROL                                                       0x1a87
++#define mmDCP0_DCP_CRC_CONTROL                                                  0x1a87
++#define mmDCP1_DCP_CRC_CONTROL                                                  0x1d87
++#define mmDCP2_DCP_CRC_CONTROL                                                  0x4087
++#define mmDCP3_DCP_CRC_CONTROL                                                  0x4387
++#define mmDCP4_DCP_CRC_CONTROL                                                  0x4687
++#define mmDCP5_DCP_CRC_CONTROL                                                  0x4987
++#define mmDCP_CRC_MASK                                                          0x1a88
++#define mmDCP0_DCP_CRC_MASK                                                     0x1a88
++#define mmDCP1_DCP_CRC_MASK                                                     0x1d88
++#define mmDCP2_DCP_CRC_MASK                                                     0x4088
++#define mmDCP3_DCP_CRC_MASK                                                     0x4388
++#define mmDCP4_DCP_CRC_MASK                                                     0x4688
++#define mmDCP5_DCP_CRC_MASK                                                     0x4988
++#define mmDCP_CRC_CURRENT                                                       0x1a89
++#define mmDCP0_DCP_CRC_CURRENT                                                  0x1a89
++#define mmDCP1_DCP_CRC_CURRENT                                                  0x1d89
++#define mmDCP2_DCP_CRC_CURRENT                                                  0x4089
++#define mmDCP3_DCP_CRC_CURRENT                                                  0x4389
++#define mmDCP4_DCP_CRC_CURRENT                                                  0x4689
++#define mmDCP5_DCP_CRC_CURRENT                                                  0x4989
++#define mmDCP_CRC_LAST                                                          0x1a8b
++#define mmDCP0_DCP_CRC_LAST                                                     0x1a8b
++#define mmDCP1_DCP_CRC_LAST                                                     0x1d8b
++#define mmDCP2_DCP_CRC_LAST                                                     0x408b
++#define mmDCP3_DCP_CRC_LAST                                                     0x438b
++#define mmDCP4_DCP_CRC_LAST                                                     0x468b
++#define mmDCP5_DCP_CRC_LAST                                                     0x498b
++#define mmDCP_DEBUG                                                             0x1a8d
++#define mmDCP0_DCP_DEBUG                                                        0x1a8d
++#define mmDCP1_DCP_DEBUG                                                        0x1d8d
++#define mmDCP2_DCP_DEBUG                                                        0x408d
++#define mmDCP3_DCP_DEBUG                                                        0x438d
++#define mmDCP4_DCP_DEBUG                                                        0x468d
++#define mmDCP5_DCP_DEBUG                                                        0x498d
++#define mmGRPH_FLIP_RATE_CNTL                                                   0x1a8e
++#define mmDCP0_GRPH_FLIP_RATE_CNTL                                              0x1a8e
++#define mmDCP1_GRPH_FLIP_RATE_CNTL                                              0x1d8e
++#define mmDCP2_GRPH_FLIP_RATE_CNTL                                              0x408e
++#define mmDCP3_GRPH_FLIP_RATE_CNTL                                              0x438e
++#define mmDCP4_GRPH_FLIP_RATE_CNTL                                              0x468e
++#define mmDCP5_GRPH_FLIP_RATE_CNTL                                              0x498e
++#define mmDCP_GSL_CONTROL                                                       0x1a90
++#define mmDCP0_DCP_GSL_CONTROL                                                  0x1a90
++#define mmDCP1_DCP_GSL_CONTROL                                                  0x1d90
++#define mmDCP2_DCP_GSL_CONTROL                                                  0x4090
++#define mmDCP3_DCP_GSL_CONTROL                                                  0x4390
++#define mmDCP4_DCP_GSL_CONTROL                                                  0x4690
++#define mmDCP5_DCP_GSL_CONTROL                                                  0x4990
++#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x1a91
++#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1a91
++#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1d91
++#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4091
++#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4391
++#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4691
++#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4991
++#define mmOVL_SECONDARY_SURFACE_ADDRESS                                         0x1a92
++#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1a92
++#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1d92
++#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4092
++#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4392
++#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4692
++#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4992
++#define mmOVL_STEREOSYNC_FLIP                                                   0x1a93
++#define mmDCP0_OVL_STEREOSYNC_FLIP                                              0x1a93
++#define mmDCP1_OVL_STEREOSYNC_FLIP                                              0x1d93
++#define mmDCP2_OVL_STEREOSYNC_FLIP                                              0x4093
++#define mmDCP3_OVL_STEREOSYNC_FLIP                                              0x4393
++#define mmDCP4_OVL_STEREOSYNC_FLIP                                              0x4693
++#define mmDCP5_OVL_STEREOSYNC_FLIP                                              0x4993
++#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH                                    0x1a94
++#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1a94
++#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1d94
++#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4094
++#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4394
++#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4694
++#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4994
++#define mmDCP_TEST_DEBUG_INDEX                                                  0x1a95
++#define mmDCP0_DCP_TEST_DEBUG_INDEX                                             0x1a95
++#define mmDCP1_DCP_TEST_DEBUG_INDEX                                             0x1d95
++#define mmDCP2_DCP_TEST_DEBUG_INDEX                                             0x4095
++#define mmDCP3_DCP_TEST_DEBUG_INDEX                                             0x4395
++#define mmDCP4_DCP_TEST_DEBUG_INDEX                                             0x4695
++#define mmDCP5_DCP_TEST_DEBUG_INDEX                                             0x4995
++#define mmDCP_TEST_DEBUG_DATA                                                   0x1a96
++#define mmDCP0_DCP_TEST_DEBUG_DATA                                              0x1a96
++#define mmDCP1_DCP_TEST_DEBUG_DATA                                              0x1d96
++#define mmDCP2_DCP_TEST_DEBUG_DATA                                              0x4096
++#define mmDCP3_DCP_TEST_DEBUG_DATA                                              0x4396
++#define mmDCP4_DCP_TEST_DEBUG_DATA                                              0x4696
++#define mmDCP5_DCP_TEST_DEBUG_DATA                                              0x4996
++#define mmGRPH_STEREOSYNC_FLIP                                                  0x1a97
++#define mmDCP0_GRPH_STEREOSYNC_FLIP                                             0x1a97
++#define mmDCP1_GRPH_STEREOSYNC_FLIP                                             0x1d97
++#define mmDCP2_GRPH_STEREOSYNC_FLIP                                             0x4097
++#define mmDCP3_GRPH_STEREOSYNC_FLIP                                             0x4397
++#define mmDCP4_GRPH_STEREOSYNC_FLIP                                             0x4697
++#define mmDCP5_GRPH_STEREOSYNC_FLIP                                             0x4997
++#define mmDCP_DEBUG2                                                            0x1a98
++#define mmDCP0_DCP_DEBUG2                                                       0x1a98
++#define mmDCP1_DCP_DEBUG2                                                       0x1d98
++#define mmDCP2_DCP_DEBUG2                                                       0x4098
++#define mmDCP3_DCP_DEBUG2                                                       0x4398
++#define mmDCP4_DCP_DEBUG2                                                       0x4698
++#define mmDCP5_DCP_DEBUG2                                                       0x4998
++#define mmHW_ROTATION                                                           0x1a9e
++#define mmDCP0_HW_ROTATION                                                      0x1a9e
++#define mmDCP1_HW_ROTATION                                                      0x1d9e
++#define mmDCP2_HW_ROTATION                                                      0x409e
++#define mmDCP3_HW_ROTATION                                                      0x439e
++#define mmDCP4_HW_ROTATION                                                      0x469e
++#define mmDCP5_HW_ROTATION                                                      0x499e
++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                    0x1a9f
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1a9f
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1d9f
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x409f
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x439f
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x469f
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x499f
++#define mmREGAMMA_CONTROL                                                       0x1aa0
++#define mmDCP0_REGAMMA_CONTROL                                                  0x1aa0
++#define mmDCP1_REGAMMA_CONTROL                                                  0x1da0
++#define mmDCP2_REGAMMA_CONTROL                                                  0x40a0
++#define mmDCP3_REGAMMA_CONTROL                                                  0x43a0
++#define mmDCP4_REGAMMA_CONTROL                                                  0x46a0
++#define mmDCP5_REGAMMA_CONTROL                                                  0x49a0
++#define mmREGAMMA_LUT_INDEX                                                     0x1aa1
++#define mmDCP0_REGAMMA_LUT_INDEX                                                0x1aa1
++#define mmDCP1_REGAMMA_LUT_INDEX                                                0x1da1
++#define mmDCP2_REGAMMA_LUT_INDEX                                                0x40a1
++#define mmDCP3_REGAMMA_LUT_INDEX                                                0x43a1
++#define mmDCP4_REGAMMA_LUT_INDEX                                                0x46a1
++#define mmDCP5_REGAMMA_LUT_INDEX                                                0x49a1
++#define mmREGAMMA_LUT_DATA                                                      0x1aa2
++#define mmDCP0_REGAMMA_LUT_DATA                                                 0x1aa2
++#define mmDCP1_REGAMMA_LUT_DATA                                                 0x1da2
++#define mmDCP2_REGAMMA_LUT_DATA                                                 0x40a2
++#define mmDCP3_REGAMMA_LUT_DATA                                                 0x43a2
++#define mmDCP4_REGAMMA_LUT_DATA                                                 0x46a2
++#define mmDCP5_REGAMMA_LUT_DATA                                                 0x49a2
++#define mmREGAMMA_LUT_WRITE_EN_MASK                                             0x1aa3
++#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                        0x1aa3
++#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                        0x1da3
++#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                        0x40a3
++#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                        0x43a3
++#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                        0x46a3
++#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                        0x49a3
++#define mmREGAMMA_CNTLA_START_CNTL                                              0x1aa4
++#define mmDCP0_REGAMMA_CNTLA_START_CNTL                                         0x1aa4
++#define mmDCP1_REGAMMA_CNTLA_START_CNTL                                         0x1da4
++#define mmDCP2_REGAMMA_CNTLA_START_CNTL                                         0x40a4
++#define mmDCP3_REGAMMA_CNTLA_START_CNTL                                         0x43a4
++#define mmDCP4_REGAMMA_CNTLA_START_CNTL                                         0x46a4
++#define mmDCP5_REGAMMA_CNTLA_START_CNTL                                         0x49a4
++#define mmREGAMMA_CNTLA_SLOPE_CNTL                                              0x1aa5
++#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1aa5
++#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1da5
++#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                         0x40a5
++#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                         0x43a5
++#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                         0x46a5
++#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                         0x49a5
++#define mmREGAMMA_CNTLA_END_CNTL1                                               0x1aa6
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL1                                          0x1aa6
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL1                                          0x1da6
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL1                                          0x40a6
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL1                                          0x43a6
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL1                                          0x46a6
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL1                                          0x49a6
++#define mmREGAMMA_CNTLA_END_CNTL2                                               0x1aa7
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL2                                          0x1aa7
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL2                                          0x1da7
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL2                                          0x40a7
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL2                                          0x43a7
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL2                                          0x46a7
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL2                                          0x49a7
++#define mmREGAMMA_CNTLA_REGION_0_1                                              0x1aa8
++#define mmDCP0_REGAMMA_CNTLA_REGION_0_1                                         0x1aa8
++#define mmDCP1_REGAMMA_CNTLA_REGION_0_1                                         0x1da8
++#define mmDCP2_REGAMMA_CNTLA_REGION_0_1                                         0x40a8
++#define mmDCP3_REGAMMA_CNTLA_REGION_0_1                                         0x43a8
++#define mmDCP4_REGAMMA_CNTLA_REGION_0_1                                         0x46a8
++#define mmDCP5_REGAMMA_CNTLA_REGION_0_1                                         0x49a8
++#define mmREGAMMA_CNTLA_REGION_2_3                                              0x1aa9
++#define mmDCP0_REGAMMA_CNTLA_REGION_2_3                                         0x1aa9
++#define mmDCP1_REGAMMA_CNTLA_REGION_2_3                                         0x1da9
++#define mmDCP2_REGAMMA_CNTLA_REGION_2_3                                         0x40a9
++#define mmDCP3_REGAMMA_CNTLA_REGION_2_3                                         0x43a9
++#define mmDCP4_REGAMMA_CNTLA_REGION_2_3                                         0x46a9
++#define mmDCP5_REGAMMA_CNTLA_REGION_2_3                                         0x49a9
++#define mmREGAMMA_CNTLA_REGION_4_5                                              0x1aaa
++#define mmDCP0_REGAMMA_CNTLA_REGION_4_5                                         0x1aaa
++#define mmDCP1_REGAMMA_CNTLA_REGION_4_5                                         0x1daa
++#define mmDCP2_REGAMMA_CNTLA_REGION_4_5                                         0x40aa
++#define mmDCP3_REGAMMA_CNTLA_REGION_4_5                                         0x43aa
++#define mmDCP4_REGAMMA_CNTLA_REGION_4_5                                         0x46aa
++#define mmDCP5_REGAMMA_CNTLA_REGION_4_5                                         0x49aa
++#define mmREGAMMA_CNTLA_REGION_6_7                                              0x1aab
++#define mmDCP0_REGAMMA_CNTLA_REGION_6_7                                         0x1aab
++#define mmDCP1_REGAMMA_CNTLA_REGION_6_7                                         0x1dab
++#define mmDCP2_REGAMMA_CNTLA_REGION_6_7                                         0x40ab
++#define mmDCP3_REGAMMA_CNTLA_REGION_6_7                                         0x43ab
++#define mmDCP4_REGAMMA_CNTLA_REGION_6_7                                         0x46ab
++#define mmDCP5_REGAMMA_CNTLA_REGION_6_7                                         0x49ab
++#define mmREGAMMA_CNTLA_REGION_8_9                                              0x1aac
++#define mmDCP0_REGAMMA_CNTLA_REGION_8_9                                         0x1aac
++#define mmDCP1_REGAMMA_CNTLA_REGION_8_9                                         0x1dac
++#define mmDCP2_REGAMMA_CNTLA_REGION_8_9                                         0x40ac
++#define mmDCP3_REGAMMA_CNTLA_REGION_8_9                                         0x43ac
++#define mmDCP4_REGAMMA_CNTLA_REGION_8_9                                         0x46ac
++#define mmDCP5_REGAMMA_CNTLA_REGION_8_9                                         0x49ac
++#define mmREGAMMA_CNTLA_REGION_10_11                                            0x1aad
++#define mmDCP0_REGAMMA_CNTLA_REGION_10_11                                       0x1aad
++#define mmDCP1_REGAMMA_CNTLA_REGION_10_11                                       0x1dad
++#define mmDCP2_REGAMMA_CNTLA_REGION_10_11                                       0x40ad
++#define mmDCP3_REGAMMA_CNTLA_REGION_10_11                                       0x43ad
++#define mmDCP4_REGAMMA_CNTLA_REGION_10_11                                       0x46ad
++#define mmDCP5_REGAMMA_CNTLA_REGION_10_11                                       0x49ad
++#define mmREGAMMA_CNTLA_REGION_12_13                                            0x1aae
++#define mmDCP0_REGAMMA_CNTLA_REGION_12_13                                       0x1aae
++#define mmDCP1_REGAMMA_CNTLA_REGION_12_13                                       0x1dae
++#define mmDCP2_REGAMMA_CNTLA_REGION_12_13                                       0x40ae
++#define mmDCP3_REGAMMA_CNTLA_REGION_12_13                                       0x43ae
++#define mmDCP4_REGAMMA_CNTLA_REGION_12_13                                       0x46ae
++#define mmDCP5_REGAMMA_CNTLA_REGION_12_13                                       0x49ae
++#define mmREGAMMA_CNTLA_REGION_14_15                                            0x1aaf
++#define mmDCP0_REGAMMA_CNTLA_REGION_14_15                                       0x1aaf
++#define mmDCP1_REGAMMA_CNTLA_REGION_14_15                                       0x1daf
++#define mmDCP2_REGAMMA_CNTLA_REGION_14_15                                       0x40af
++#define mmDCP3_REGAMMA_CNTLA_REGION_14_15                                       0x43af
++#define mmDCP4_REGAMMA_CNTLA_REGION_14_15                                       0x46af
++#define mmDCP5_REGAMMA_CNTLA_REGION_14_15                                       0x49af
++#define mmREGAMMA_CNTLB_START_CNTL                                              0x1ab0
++#define mmDCP0_REGAMMA_CNTLB_START_CNTL                                         0x1ab0
++#define mmDCP1_REGAMMA_CNTLB_START_CNTL                                         0x1db0
++#define mmDCP2_REGAMMA_CNTLB_START_CNTL                                         0x40b0
++#define mmDCP3_REGAMMA_CNTLB_START_CNTL                                         0x43b0
++#define mmDCP4_REGAMMA_CNTLB_START_CNTL                                         0x46b0
++#define mmDCP5_REGAMMA_CNTLB_START_CNTL                                         0x49b0
++#define mmREGAMMA_CNTLB_SLOPE_CNTL                                              0x1ab1
++#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1ab1
++#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1db1
++#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                         0x40b1
++#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                         0x43b1
++#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                         0x46b1
++#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                         0x49b1
++#define mmREGAMMA_CNTLB_END_CNTL1                                               0x1ab2
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL1                                          0x1ab2
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL1                                          0x1db2
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL1                                          0x40b2
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL1                                          0x43b2
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL1                                          0x46b2
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL1                                          0x49b2
++#define mmREGAMMA_CNTLB_END_CNTL2                                               0x1ab3
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL2                                          0x1ab3
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL2                                          0x1db3
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL2                                          0x40b3
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL2                                          0x43b3
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL2                                          0x46b3
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL2                                          0x49b3
++#define mmREGAMMA_CNTLB_REGION_0_1                                              0x1ab4
++#define mmDCP0_REGAMMA_CNTLB_REGION_0_1                                         0x1ab4
++#define mmDCP1_REGAMMA_CNTLB_REGION_0_1                                         0x1db4
++#define mmDCP2_REGAMMA_CNTLB_REGION_0_1                                         0x40b4
++#define mmDCP3_REGAMMA_CNTLB_REGION_0_1                                         0x43b4
++#define mmDCP4_REGAMMA_CNTLB_REGION_0_1                                         0x46b4
++#define mmDCP5_REGAMMA_CNTLB_REGION_0_1                                         0x49b4
++#define mmREGAMMA_CNTLB_REGION_2_3                                              0x1ab5
++#define mmDCP0_REGAMMA_CNTLB_REGION_2_3                                         0x1ab5
++#define mmDCP1_REGAMMA_CNTLB_REGION_2_3                                         0x1db5
++#define mmDCP2_REGAMMA_CNTLB_REGION_2_3                                         0x40b5
++#define mmDCP3_REGAMMA_CNTLB_REGION_2_3                                         0x43b5
++#define mmDCP4_REGAMMA_CNTLB_REGION_2_3                                         0x46b5
++#define mmDCP5_REGAMMA_CNTLB_REGION_2_3                                         0x49b5
++#define mmREGAMMA_CNTLB_REGION_4_5                                              0x1ab6
++#define mmDCP0_REGAMMA_CNTLB_REGION_4_5                                         0x1ab6
++#define mmDCP1_REGAMMA_CNTLB_REGION_4_5                                         0x1db6
++#define mmDCP2_REGAMMA_CNTLB_REGION_4_5                                         0x40b6
++#define mmDCP3_REGAMMA_CNTLB_REGION_4_5                                         0x43b6
++#define mmDCP4_REGAMMA_CNTLB_REGION_4_5                                         0x46b6
++#define mmDCP5_REGAMMA_CNTLB_REGION_4_5                                         0x49b6
++#define mmREGAMMA_CNTLB_REGION_6_7                                              0x1ab7
++#define mmDCP0_REGAMMA_CNTLB_REGION_6_7                                         0x1ab7
++#define mmDCP1_REGAMMA_CNTLB_REGION_6_7                                         0x1db7
++#define mmDCP2_REGAMMA_CNTLB_REGION_6_7                                         0x40b7
++#define mmDCP3_REGAMMA_CNTLB_REGION_6_7                                         0x43b7
++#define mmDCP4_REGAMMA_CNTLB_REGION_6_7                                         0x46b7
++#define mmDCP5_REGAMMA_CNTLB_REGION_6_7                                         0x49b7
++#define mmREGAMMA_CNTLB_REGION_8_9                                              0x1ab8
++#define mmDCP0_REGAMMA_CNTLB_REGION_8_9                                         0x1ab8
++#define mmDCP1_REGAMMA_CNTLB_REGION_8_9                                         0x1db8
++#define mmDCP2_REGAMMA_CNTLB_REGION_8_9                                         0x40b8
++#define mmDCP3_REGAMMA_CNTLB_REGION_8_9                                         0x43b8
++#define mmDCP4_REGAMMA_CNTLB_REGION_8_9                                         0x46b8
++#define mmDCP5_REGAMMA_CNTLB_REGION_8_9                                         0x49b8
++#define mmREGAMMA_CNTLB_REGION_10_11                                            0x1ab9
++#define mmDCP0_REGAMMA_CNTLB_REGION_10_11                                       0x1ab9
++#define mmDCP1_REGAMMA_CNTLB_REGION_10_11                                       0x1db9
++#define mmDCP2_REGAMMA_CNTLB_REGION_10_11                                       0x40b9
++#define mmDCP3_REGAMMA_CNTLB_REGION_10_11                                       0x43b9
++#define mmDCP4_REGAMMA_CNTLB_REGION_10_11                                       0x46b9
++#define mmDCP5_REGAMMA_CNTLB_REGION_10_11                                       0x49b9
++#define mmREGAMMA_CNTLB_REGION_12_13                                            0x1aba
++#define mmDCP0_REGAMMA_CNTLB_REGION_12_13                                       0x1aba
++#define mmDCP1_REGAMMA_CNTLB_REGION_12_13                                       0x1dba
++#define mmDCP2_REGAMMA_CNTLB_REGION_12_13                                       0x40ba
++#define mmDCP3_REGAMMA_CNTLB_REGION_12_13                                       0x43ba
++#define mmDCP4_REGAMMA_CNTLB_REGION_12_13                                       0x46ba
++#define mmDCP5_REGAMMA_CNTLB_REGION_12_13                                       0x49ba
++#define mmREGAMMA_CNTLB_REGION_14_15                                            0x1abb
++#define mmDCP0_REGAMMA_CNTLB_REGION_14_15                                       0x1abb
++#define mmDCP1_REGAMMA_CNTLB_REGION_14_15                                       0x1dbb
++#define mmDCP2_REGAMMA_CNTLB_REGION_14_15                                       0x40bb
++#define mmDCP3_REGAMMA_CNTLB_REGION_14_15                                       0x43bb
++#define mmDCP4_REGAMMA_CNTLB_REGION_14_15                                       0x46bb
++#define mmDCP5_REGAMMA_CNTLB_REGION_14_15                                       0x49bb
++#define mmALPHA_CONTROL                                                         0x1abc
++#define mmDCP0_ALPHA_CONTROL                                                    0x1abc
++#define mmDCP1_ALPHA_CONTROL                                                    0x1dbc
++#define mmDCP2_ALPHA_CONTROL                                                    0x40bc
++#define mmDCP3_ALPHA_CONTROL                                                    0x43bc
++#define mmDCP4_ALPHA_CONTROL                                                    0x46bc
++#define mmDCP5_ALPHA_CONTROL                                                    0x49bc
++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                    0x1abd
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1abd
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1dbd
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x40bd
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x43bd
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x46bd
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x49bd
++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                               0x1abe
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1abe
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1dbe
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x40be
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x43be
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x46be
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x49be
++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                  0x1abf
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1abf
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1dbf
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x40bf
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x43bf
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x46bf
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x49bf
++#define mmDIG_FE_CNTL                                                           0x1c00
++#define mmDIG0_DIG_FE_CNTL                                                      0x1c00
++#define mmDIG1_DIG_FE_CNTL                                                      0x1f00
++#define mmDIG2_DIG_FE_CNTL                                                      0x4200
++#define mmDIG3_DIG_FE_CNTL                                                      0x4500
++#define mmDIG4_DIG_FE_CNTL                                                      0x4800
++#define mmDIG5_DIG_FE_CNTL                                                      0x4b00
++#define mmDIG6_DIG_FE_CNTL                                                      0x4e00
++#define mmDIG_OUTPUT_CRC_CNTL                                                   0x1c01
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                              0x1c01
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                              0x1f01
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                              0x4201
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                              0x4501
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL                                              0x4801
++#define mmDIG5_DIG_OUTPUT_CRC_CNTL                                              0x4b01
++#define mmDIG6_DIG_OUTPUT_CRC_CNTL                                              0x4e01
++#define mmDIG_OUTPUT_CRC_RESULT                                                 0x1c02
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                            0x1c02
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                            0x1f02
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                            0x4202
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                            0x4502
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT                                            0x4802
++#define mmDIG5_DIG_OUTPUT_CRC_RESULT                                            0x4b02
++#define mmDIG6_DIG_OUTPUT_CRC_RESULT                                            0x4e02
++#define mmDIG_CLOCK_PATTERN                                                     0x1c03
++#define mmDIG0_DIG_CLOCK_PATTERN                                                0x1c03
++#define mmDIG1_DIG_CLOCK_PATTERN                                                0x1f03
++#define mmDIG2_DIG_CLOCK_PATTERN                                                0x4203
++#define mmDIG3_DIG_CLOCK_PATTERN                                                0x4503
++#define mmDIG4_DIG_CLOCK_PATTERN                                                0x4803
++#define mmDIG5_DIG_CLOCK_PATTERN                                                0x4b03
++#define mmDIG6_DIG_CLOCK_PATTERN                                                0x4e03
++#define mmDIG_TEST_PATTERN                                                      0x1c04
++#define mmDIG0_DIG_TEST_PATTERN                                                 0x1c04
++#define mmDIG1_DIG_TEST_PATTERN                                                 0x1f04
++#define mmDIG2_DIG_TEST_PATTERN                                                 0x4204
++#define mmDIG3_DIG_TEST_PATTERN                                                 0x4504
++#define mmDIG4_DIG_TEST_PATTERN                                                 0x4804
++#define mmDIG5_DIG_TEST_PATTERN                                                 0x4b04
++#define mmDIG6_DIG_TEST_PATTERN                                                 0x4e04
++#define mmDIG_RANDOM_PATTERN_SEED                                               0x1c05
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                          0x1c05
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                          0x1f05
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                          0x4205
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                          0x4505
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED                                          0x4805
++#define mmDIG5_DIG_RANDOM_PATTERN_SEED                                          0x4b05
++#define mmDIG6_DIG_RANDOM_PATTERN_SEED                                          0x4e05
++#define mmDIG_FIFO_STATUS                                                       0x1c0a
++#define mmDIG0_DIG_FIFO_STATUS                                                  0x1c0a
++#define mmDIG1_DIG_FIFO_STATUS                                                  0x1f0a
++#define mmDIG2_DIG_FIFO_STATUS                                                  0x420a
++#define mmDIG3_DIG_FIFO_STATUS                                                  0x450a
++#define mmDIG4_DIG_FIFO_STATUS                                                  0x480a
++#define mmDIG5_DIG_FIFO_STATUS                                                  0x4b0a
++#define mmDIG6_DIG_FIFO_STATUS                                                  0x4e0a
++#define mmDIG_DISPCLK_SWITCH_CNTL                                               0x1c08
++#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL                                          0x1c08
++#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL                                          0x1f08
++#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL                                          0x4208
++#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL                                          0x4508
++#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL                                          0x4808
++#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL                                          0x4b08
++#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL                                          0x4e08
++#define mmDIG_DISPCLK_SWITCH_STATUS                                             0x1c09
++#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS                                        0x1c09
++#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS                                        0x1f09
++#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS                                        0x4209
++#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS                                        0x4509
++#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS                                        0x4809
++#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS                                        0x4b09
++#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS                                        0x4e09
++#define mmHDMI_CONTROL                                                          0x1c0c
++#define mmDIG0_HDMI_CONTROL                                                     0x1c0c
++#define mmDIG1_HDMI_CONTROL                                                     0x1f0c
++#define mmDIG2_HDMI_CONTROL                                                     0x420c
++#define mmDIG3_HDMI_CONTROL                                                     0x450c
++#define mmDIG4_HDMI_CONTROL                                                     0x480c
++#define mmDIG5_HDMI_CONTROL                                                     0x4b0c
++#define mmDIG6_HDMI_CONTROL                                                     0x4e0c
++#define mmHDMI_STATUS                                                           0x1c0d
++#define mmDIG0_HDMI_STATUS                                                      0x1c0d
++#define mmDIG1_HDMI_STATUS                                                      0x1f0d
++#define mmDIG2_HDMI_STATUS                                                      0x420d
++#define mmDIG3_HDMI_STATUS                                                      0x450d
++#define mmDIG4_HDMI_STATUS                                                      0x480d
++#define mmDIG5_HDMI_STATUS                                                      0x4b0d
++#define mmDIG6_HDMI_STATUS                                                      0x4e0d
++#define mmHDMI_AUDIO_PACKET_CONTROL                                             0x1c0e
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                        0x1c0e
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                        0x1f0e
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                        0x420e
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                        0x450e
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                        0x480e
++#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                        0x4b0e
++#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                        0x4e0e
++#define mmHDMI_ACR_PACKET_CONTROL                                               0x1c0f
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                          0x1c0f
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                          0x1f0f
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                          0x420f
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                          0x450f
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL                                          0x480f
++#define mmDIG5_HDMI_ACR_PACKET_CONTROL                                          0x4b0f
++#define mmDIG6_HDMI_ACR_PACKET_CONTROL                                          0x4e0f
++#define mmHDMI_VBI_PACKET_CONTROL                                               0x1c10
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                          0x1c10
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                          0x1f10
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                          0x4210
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                          0x4510
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL                                          0x4810
++#define mmDIG5_HDMI_VBI_PACKET_CONTROL                                          0x4b10
++#define mmDIG6_HDMI_VBI_PACKET_CONTROL                                          0x4e10
++#define mmHDMI_INFOFRAME_CONTROL0                                               0x1c11
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                          0x1c11
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                          0x1f11
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                          0x4211
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                          0x4511
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0                                          0x4811
++#define mmDIG5_HDMI_INFOFRAME_CONTROL0                                          0x4b11
++#define mmDIG6_HDMI_INFOFRAME_CONTROL0                                          0x4e11
++#define mmHDMI_INFOFRAME_CONTROL1                                               0x1c12
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                          0x1c12
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                          0x1f12
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                          0x4212
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                          0x4512
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1                                          0x4812
++#define mmDIG5_HDMI_INFOFRAME_CONTROL1                                          0x4b12
++#define mmDIG6_HDMI_INFOFRAME_CONTROL1                                          0x4e12
++#define mmHDMI_GENERIC_PACKET_CONTROL0                                          0x1c13
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                     0x1c13
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                     0x1f13
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                     0x4213
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                     0x4513
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                     0x4813
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                     0x4b13
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                     0x4e13
++#define mmAFMT_INTERRUPT_STATUS                                                 0x1c14
++#define mmDIG0_AFMT_INTERRUPT_STATUS                                            0x1c14
++#define mmDIG1_AFMT_INTERRUPT_STATUS                                            0x1f14
++#define mmDIG2_AFMT_INTERRUPT_STATUS                                            0x4214
++#define mmDIG3_AFMT_INTERRUPT_STATUS                                            0x4514
++#define mmDIG4_AFMT_INTERRUPT_STATUS                                            0x4814
++#define mmDIG5_AFMT_INTERRUPT_STATUS                                            0x4b14
++#define mmDIG6_AFMT_INTERRUPT_STATUS                                            0x4e14
++#define mmHDMI_GC                                                               0x1c16
++#define mmDIG0_HDMI_GC                                                          0x1c16
++#define mmDIG1_HDMI_GC                                                          0x1f16
++#define mmDIG2_HDMI_GC                                                          0x4216
++#define mmDIG3_HDMI_GC                                                          0x4516
++#define mmDIG4_HDMI_GC                                                          0x4816
++#define mmDIG5_HDMI_GC                                                          0x4b16
++#define mmDIG6_HDMI_GC                                                          0x4e16
++#define mmAFMT_AUDIO_PACKET_CONTROL2                                            0x1c17
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                       0x1c17
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                       0x1f17
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                       0x4217
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                       0x4517
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                       0x4817
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                       0x4b17
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                       0x4e17
++#define mmAFMT_ISRC1_0                                                          0x1c18
++#define mmDIG0_AFMT_ISRC1_0                                                     0x1c18
++#define mmDIG1_AFMT_ISRC1_0                                                     0x1f18
++#define mmDIG2_AFMT_ISRC1_0                                                     0x4218
++#define mmDIG3_AFMT_ISRC1_0                                                     0x4518
++#define mmDIG4_AFMT_ISRC1_0                                                     0x4818
++#define mmDIG5_AFMT_ISRC1_0                                                     0x4b18
++#define mmDIG6_AFMT_ISRC1_0                                                     0x4e18
++#define mmAFMT_ISRC1_1                                                          0x1c19
++#define mmDIG0_AFMT_ISRC1_1                                                     0x1c19
++#define mmDIG1_AFMT_ISRC1_1                                                     0x1f19
++#define mmDIG2_AFMT_ISRC1_1                                                     0x4219
++#define mmDIG3_AFMT_ISRC1_1                                                     0x4519
++#define mmDIG4_AFMT_ISRC1_1                                                     0x4819
++#define mmDIG5_AFMT_ISRC1_1                                                     0x4b19
++#define mmDIG6_AFMT_ISRC1_1                                                     0x4e19
++#define mmAFMT_ISRC1_2                                                          0x1c1a
++#define mmDIG0_AFMT_ISRC1_2                                                     0x1c1a
++#define mmDIG1_AFMT_ISRC1_2                                                     0x1f1a
++#define mmDIG2_AFMT_ISRC1_2                                                     0x421a
++#define mmDIG3_AFMT_ISRC1_2                                                     0x451a
++#define mmDIG4_AFMT_ISRC1_2                                                     0x481a
++#define mmDIG5_AFMT_ISRC1_2                                                     0x4b1a
++#define mmDIG6_AFMT_ISRC1_2                                                     0x4e1a
++#define mmAFMT_ISRC1_3                                                          0x1c1b
++#define mmDIG0_AFMT_ISRC1_3                                                     0x1c1b
++#define mmDIG1_AFMT_ISRC1_3                                                     0x1f1b
++#define mmDIG2_AFMT_ISRC1_3                                                     0x421b
++#define mmDIG3_AFMT_ISRC1_3                                                     0x451b
++#define mmDIG4_AFMT_ISRC1_3                                                     0x481b
++#define mmDIG5_AFMT_ISRC1_3                                                     0x4b1b
++#define mmDIG6_AFMT_ISRC1_3                                                     0x4e1b
++#define mmAFMT_ISRC1_4                                                          0x1c1c
++#define mmDIG0_AFMT_ISRC1_4                                                     0x1c1c
++#define mmDIG1_AFMT_ISRC1_4                                                     0x1f1c
++#define mmDIG2_AFMT_ISRC1_4                                                     0x421c
++#define mmDIG3_AFMT_ISRC1_4                                                     0x451c
++#define mmDIG4_AFMT_ISRC1_4                                                     0x481c
++#define mmDIG5_AFMT_ISRC1_4                                                     0x4b1c
++#define mmDIG6_AFMT_ISRC1_4                                                     0x4e1c
++#define mmAFMT_ISRC2_0                                                          0x1c1d
++#define mmDIG0_AFMT_ISRC2_0                                                     0x1c1d
++#define mmDIG1_AFMT_ISRC2_0                                                     0x1f1d
++#define mmDIG2_AFMT_ISRC2_0                                                     0x421d
++#define mmDIG3_AFMT_ISRC2_0                                                     0x451d
++#define mmDIG4_AFMT_ISRC2_0                                                     0x481d
++#define mmDIG5_AFMT_ISRC2_0                                                     0x4b1d
++#define mmDIG6_AFMT_ISRC2_0                                                     0x4e1d
++#define mmAFMT_ISRC2_1                                                          0x1c1e
++#define mmDIG0_AFMT_ISRC2_1                                                     0x1c1e
++#define mmDIG1_AFMT_ISRC2_1                                                     0x1f1e
++#define mmDIG2_AFMT_ISRC2_1                                                     0x421e
++#define mmDIG3_AFMT_ISRC2_1                                                     0x451e
++#define mmDIG4_AFMT_ISRC2_1                                                     0x481e
++#define mmDIG5_AFMT_ISRC2_1                                                     0x4b1e
++#define mmDIG6_AFMT_ISRC2_1                                                     0x4e1e
++#define mmAFMT_ISRC2_2                                                          0x1c1f
++#define mmDIG0_AFMT_ISRC2_2                                                     0x1c1f
++#define mmDIG1_AFMT_ISRC2_2                                                     0x1f1f
++#define mmDIG2_AFMT_ISRC2_2                                                     0x421f
++#define mmDIG3_AFMT_ISRC2_2                                                     0x451f
++#define mmDIG4_AFMT_ISRC2_2                                                     0x481f
++#define mmDIG5_AFMT_ISRC2_2                                                     0x4b1f
++#define mmDIG6_AFMT_ISRC2_2                                                     0x4e1f
++#define mmAFMT_ISRC2_3                                                          0x1c20
++#define mmDIG0_AFMT_ISRC2_3                                                     0x1c20
++#define mmDIG1_AFMT_ISRC2_3                                                     0x1f20
++#define mmDIG2_AFMT_ISRC2_3                                                     0x4220
++#define mmDIG3_AFMT_ISRC2_3                                                     0x4520
++#define mmDIG4_AFMT_ISRC2_3                                                     0x4820
++#define mmDIG5_AFMT_ISRC2_3                                                     0x4b20
++#define mmDIG6_AFMT_ISRC2_3                                                     0x4e20
++#define mmAFMT_AVI_INFO0                                                        0x1c21
++#define mmDIG0_AFMT_AVI_INFO0                                                   0x1c21
++#define mmDIG1_AFMT_AVI_INFO0                                                   0x1f21
++#define mmDIG2_AFMT_AVI_INFO0                                                   0x4221
++#define mmDIG3_AFMT_AVI_INFO0                                                   0x4521
++#define mmDIG4_AFMT_AVI_INFO0                                                   0x4821
++#define mmDIG5_AFMT_AVI_INFO0                                                   0x4b21
++#define mmDIG6_AFMT_AVI_INFO0                                                   0x4e21
++#define mmAFMT_AVI_INFO1                                                        0x1c22
++#define mmDIG0_AFMT_AVI_INFO1                                                   0x1c22
++#define mmDIG1_AFMT_AVI_INFO1                                                   0x1f22
++#define mmDIG2_AFMT_AVI_INFO1                                                   0x4222
++#define mmDIG3_AFMT_AVI_INFO1                                                   0x4522
++#define mmDIG4_AFMT_AVI_INFO1                                                   0x4822
++#define mmDIG5_AFMT_AVI_INFO1                                                   0x4b22
++#define mmDIG6_AFMT_AVI_INFO1                                                   0x4e22
++#define mmAFMT_AVI_INFO2                                                        0x1c23
++#define mmDIG0_AFMT_AVI_INFO2                                                   0x1c23
++#define mmDIG1_AFMT_AVI_INFO2                                                   0x1f23
++#define mmDIG2_AFMT_AVI_INFO2                                                   0x4223
++#define mmDIG3_AFMT_AVI_INFO2                                                   0x4523
++#define mmDIG4_AFMT_AVI_INFO2                                                   0x4823
++#define mmDIG5_AFMT_AVI_INFO2                                                   0x4b23
++#define mmDIG6_AFMT_AVI_INFO2                                                   0x4e23
++#define mmAFMT_AVI_INFO3                                                        0x1c24
++#define mmDIG0_AFMT_AVI_INFO3                                                   0x1c24
++#define mmDIG1_AFMT_AVI_INFO3                                                   0x1f24
++#define mmDIG2_AFMT_AVI_INFO3                                                   0x4224
++#define mmDIG3_AFMT_AVI_INFO3                                                   0x4524
++#define mmDIG4_AFMT_AVI_INFO3                                                   0x4824
++#define mmDIG5_AFMT_AVI_INFO3                                                   0x4b24
++#define mmDIG6_AFMT_AVI_INFO3                                                   0x4e24
++#define mmAFMT_MPEG_INFO0                                                       0x1c25
++#define mmDIG0_AFMT_MPEG_INFO0                                                  0x1c25
++#define mmDIG1_AFMT_MPEG_INFO0                                                  0x1f25
++#define mmDIG2_AFMT_MPEG_INFO0                                                  0x4225
++#define mmDIG3_AFMT_MPEG_INFO0                                                  0x4525
++#define mmDIG4_AFMT_MPEG_INFO0                                                  0x4825
++#define mmDIG5_AFMT_MPEG_INFO0                                                  0x4b25
++#define mmDIG6_AFMT_MPEG_INFO0                                                  0x4e25
++#define mmAFMT_MPEG_INFO1                                                       0x1c26
++#define mmDIG0_AFMT_MPEG_INFO1                                                  0x1c26
++#define mmDIG1_AFMT_MPEG_INFO1                                                  0x1f26
++#define mmDIG2_AFMT_MPEG_INFO1                                                  0x4226
++#define mmDIG3_AFMT_MPEG_INFO1                                                  0x4526
++#define mmDIG4_AFMT_MPEG_INFO1                                                  0x4826
++#define mmDIG5_AFMT_MPEG_INFO1                                                  0x4b26
++#define mmDIG6_AFMT_MPEG_INFO1                                                  0x4e26
++#define mmAFMT_GENERIC_HDR                                                      0x1c27
++#define mmDIG0_AFMT_GENERIC_HDR                                                 0x1c27
++#define mmDIG1_AFMT_GENERIC_HDR                                                 0x1f27
++#define mmDIG2_AFMT_GENERIC_HDR                                                 0x4227
++#define mmDIG3_AFMT_GENERIC_HDR                                                 0x4527
++#define mmDIG4_AFMT_GENERIC_HDR                                                 0x4827
++#define mmDIG5_AFMT_GENERIC_HDR                                                 0x4b27
++#define mmDIG6_AFMT_GENERIC_HDR                                                 0x4e27
++#define mmAFMT_GENERIC_0                                                        0x1c28
++#define mmDIG0_AFMT_GENERIC_0                                                   0x1c28
++#define mmDIG1_AFMT_GENERIC_0                                                   0x1f28
++#define mmDIG2_AFMT_GENERIC_0                                                   0x4228
++#define mmDIG3_AFMT_GENERIC_0                                                   0x4528
++#define mmDIG4_AFMT_GENERIC_0                                                   0x4828
++#define mmDIG5_AFMT_GENERIC_0                                                   0x4b28
++#define mmDIG6_AFMT_GENERIC_0                                                   0x4e28
++#define mmAFMT_GENERIC_1                                                        0x1c29
++#define mmDIG0_AFMT_GENERIC_1                                                   0x1c29
++#define mmDIG1_AFMT_GENERIC_1                                                   0x1f29
++#define mmDIG2_AFMT_GENERIC_1                                                   0x4229
++#define mmDIG3_AFMT_GENERIC_1                                                   0x4529
++#define mmDIG4_AFMT_GENERIC_1                                                   0x4829
++#define mmDIG5_AFMT_GENERIC_1                                                   0x4b29
++#define mmDIG6_AFMT_GENERIC_1                                                   0x4e29
++#define mmAFMT_GENERIC_2                                                        0x1c2a
++#define mmDIG0_AFMT_GENERIC_2                                                   0x1c2a
++#define mmDIG1_AFMT_GENERIC_2                                                   0x1f2a
++#define mmDIG2_AFMT_GENERIC_2                                                   0x422a
++#define mmDIG3_AFMT_GENERIC_2                                                   0x452a
++#define mmDIG4_AFMT_GENERIC_2                                                   0x482a
++#define mmDIG5_AFMT_GENERIC_2                                                   0x4b2a
++#define mmDIG6_AFMT_GENERIC_2                                                   0x4e2a
++#define mmAFMT_GENERIC_3                                                        0x1c2b
++#define mmDIG0_AFMT_GENERIC_3                                                   0x1c2b
++#define mmDIG1_AFMT_GENERIC_3                                                   0x1f2b
++#define mmDIG2_AFMT_GENERIC_3                                                   0x422b
++#define mmDIG3_AFMT_GENERIC_3                                                   0x452b
++#define mmDIG4_AFMT_GENERIC_3                                                   0x482b
++#define mmDIG5_AFMT_GENERIC_3                                                   0x4b2b
++#define mmDIG6_AFMT_GENERIC_3                                                   0x4e2b
++#define mmAFMT_GENERIC_4                                                        0x1c2c
++#define mmDIG0_AFMT_GENERIC_4                                                   0x1c2c
++#define mmDIG1_AFMT_GENERIC_4                                                   0x1f2c
++#define mmDIG2_AFMT_GENERIC_4                                                   0x422c
++#define mmDIG3_AFMT_GENERIC_4                                                   0x452c
++#define mmDIG4_AFMT_GENERIC_4                                                   0x482c
++#define mmDIG5_AFMT_GENERIC_4                                                   0x4b2c
++#define mmDIG6_AFMT_GENERIC_4                                                   0x4e2c
++#define mmAFMT_GENERIC_5                                                        0x1c2d
++#define mmDIG0_AFMT_GENERIC_5                                                   0x1c2d
++#define mmDIG1_AFMT_GENERIC_5                                                   0x1f2d
++#define mmDIG2_AFMT_GENERIC_5                                                   0x422d
++#define mmDIG3_AFMT_GENERIC_5                                                   0x452d
++#define mmDIG4_AFMT_GENERIC_5                                                   0x482d
++#define mmDIG5_AFMT_GENERIC_5                                                   0x4b2d
++#define mmDIG6_AFMT_GENERIC_5                                                   0x4e2d
++#define mmAFMT_GENERIC_6                                                        0x1c2e
++#define mmDIG0_AFMT_GENERIC_6                                                   0x1c2e
++#define mmDIG1_AFMT_GENERIC_6                                                   0x1f2e
++#define mmDIG2_AFMT_GENERIC_6                                                   0x422e
++#define mmDIG3_AFMT_GENERIC_6                                                   0x452e
++#define mmDIG4_AFMT_GENERIC_6                                                   0x482e
++#define mmDIG5_AFMT_GENERIC_6                                                   0x4b2e
++#define mmDIG6_AFMT_GENERIC_6                                                   0x4e2e
++#define mmAFMT_GENERIC_7                                                        0x1c2f
++#define mmDIG0_AFMT_GENERIC_7                                                   0x1c2f
++#define mmDIG1_AFMT_GENERIC_7                                                   0x1f2f
++#define mmDIG2_AFMT_GENERIC_7                                                   0x422f
++#define mmDIG3_AFMT_GENERIC_7                                                   0x452f
++#define mmDIG4_AFMT_GENERIC_7                                                   0x482f
++#define mmDIG5_AFMT_GENERIC_7                                                   0x4b2f
++#define mmDIG6_AFMT_GENERIC_7                                                   0x4e2f
++#define mmHDMI_GENERIC_PACKET_CONTROL1                                          0x1c30
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                     0x1c30
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                     0x1f30
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                     0x4230
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                     0x4530
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                     0x4830
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                     0x4b30
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                     0x4e30
++#define mmHDMI_ACR_32_0                                                         0x1c37
++#define mmDIG0_HDMI_ACR_32_0                                                    0x1c37
++#define mmDIG1_HDMI_ACR_32_0                                                    0x1f37
++#define mmDIG2_HDMI_ACR_32_0                                                    0x4237
++#define mmDIG3_HDMI_ACR_32_0                                                    0x4537
++#define mmDIG4_HDMI_ACR_32_0                                                    0x4837
++#define mmDIG5_HDMI_ACR_32_0                                                    0x4b37
++#define mmDIG6_HDMI_ACR_32_0                                                    0x4e37
++#define mmHDMI_ACR_32_1                                                         0x1c38
++#define mmDIG0_HDMI_ACR_32_1                                                    0x1c38
++#define mmDIG1_HDMI_ACR_32_1                                                    0x1f38
++#define mmDIG2_HDMI_ACR_32_1                                                    0x4238
++#define mmDIG3_HDMI_ACR_32_1                                                    0x4538
++#define mmDIG4_HDMI_ACR_32_1                                                    0x4838
++#define mmDIG5_HDMI_ACR_32_1                                                    0x4b38
++#define mmDIG6_HDMI_ACR_32_1                                                    0x4e38
++#define mmHDMI_ACR_44_0                                                         0x1c39
++#define mmDIG0_HDMI_ACR_44_0                                                    0x1c39
++#define mmDIG1_HDMI_ACR_44_0                                                    0x1f39
++#define mmDIG2_HDMI_ACR_44_0                                                    0x4239
++#define mmDIG3_HDMI_ACR_44_0                                                    0x4539
++#define mmDIG4_HDMI_ACR_44_0                                                    0x4839
++#define mmDIG5_HDMI_ACR_44_0                                                    0x4b39
++#define mmDIG6_HDMI_ACR_44_0                                                    0x4e39
++#define mmHDMI_ACR_44_1                                                         0x1c3a
++#define mmDIG0_HDMI_ACR_44_1                                                    0x1c3a
++#define mmDIG1_HDMI_ACR_44_1                                                    0x1f3a
++#define mmDIG2_HDMI_ACR_44_1                                                    0x423a
++#define mmDIG3_HDMI_ACR_44_1                                                    0x453a
++#define mmDIG4_HDMI_ACR_44_1                                                    0x483a
++#define mmDIG5_HDMI_ACR_44_1                                                    0x4b3a
++#define mmDIG6_HDMI_ACR_44_1                                                    0x4e3a
++#define mmHDMI_ACR_48_0                                                         0x1c3b
++#define mmDIG0_HDMI_ACR_48_0                                                    0x1c3b
++#define mmDIG1_HDMI_ACR_48_0                                                    0x1f3b
++#define mmDIG2_HDMI_ACR_48_0                                                    0x423b
++#define mmDIG3_HDMI_ACR_48_0                                                    0x453b
++#define mmDIG4_HDMI_ACR_48_0                                                    0x483b
++#define mmDIG5_HDMI_ACR_48_0                                                    0x4b3b
++#define mmDIG6_HDMI_ACR_48_0                                                    0x4e3b
++#define mmHDMI_ACR_48_1                                                         0x1c3c
++#define mmDIG0_HDMI_ACR_48_1                                                    0x1c3c
++#define mmDIG1_HDMI_ACR_48_1                                                    0x1f3c
++#define mmDIG2_HDMI_ACR_48_1                                                    0x423c
++#define mmDIG3_HDMI_ACR_48_1                                                    0x453c
++#define mmDIG4_HDMI_ACR_48_1                                                    0x483c
++#define mmDIG5_HDMI_ACR_48_1                                                    0x4b3c
++#define mmDIG6_HDMI_ACR_48_1                                                    0x4e3c
++#define mmHDMI_ACR_STATUS_0                                                     0x1c3d
++#define mmDIG0_HDMI_ACR_STATUS_0                                                0x1c3d
++#define mmDIG1_HDMI_ACR_STATUS_0                                                0x1f3d
++#define mmDIG2_HDMI_ACR_STATUS_0                                                0x423d
++#define mmDIG3_HDMI_ACR_STATUS_0                                                0x453d
++#define mmDIG4_HDMI_ACR_STATUS_0                                                0x483d
++#define mmDIG5_HDMI_ACR_STATUS_0                                                0x4b3d
++#define mmDIG6_HDMI_ACR_STATUS_0                                                0x4e3d
++#define mmHDMI_ACR_STATUS_1                                                     0x1c3e
++#define mmDIG0_HDMI_ACR_STATUS_1                                                0x1c3e
++#define mmDIG1_HDMI_ACR_STATUS_1                                                0x1f3e
++#define mmDIG2_HDMI_ACR_STATUS_1                                                0x423e
++#define mmDIG3_HDMI_ACR_STATUS_1                                                0x453e
++#define mmDIG4_HDMI_ACR_STATUS_1                                                0x483e
++#define mmDIG5_HDMI_ACR_STATUS_1                                                0x4b3e
++#define mmDIG6_HDMI_ACR_STATUS_1                                                0x4e3e
++#define mmAFMT_AUDIO_INFO0                                                      0x1c3f
++#define mmDIG0_AFMT_AUDIO_INFO0                                                 0x1c3f
++#define mmDIG1_AFMT_AUDIO_INFO0                                                 0x1f3f
++#define mmDIG2_AFMT_AUDIO_INFO0                                                 0x423f
++#define mmDIG3_AFMT_AUDIO_INFO0                                                 0x453f
++#define mmDIG4_AFMT_AUDIO_INFO0                                                 0x483f
++#define mmDIG5_AFMT_AUDIO_INFO0                                                 0x4b3f
++#define mmDIG6_AFMT_AUDIO_INFO0                                                 0x4e3f
++#define mmAFMT_AUDIO_INFO1                                                      0x1c40
++#define mmDIG0_AFMT_AUDIO_INFO1                                                 0x1c40
++#define mmDIG1_AFMT_AUDIO_INFO1                                                 0x1f40
++#define mmDIG2_AFMT_AUDIO_INFO1                                                 0x4240
++#define mmDIG3_AFMT_AUDIO_INFO1                                                 0x4540
++#define mmDIG4_AFMT_AUDIO_INFO1                                                 0x4840
++#define mmDIG5_AFMT_AUDIO_INFO1                                                 0x4b40
++#define mmDIG6_AFMT_AUDIO_INFO1                                                 0x4e40
++#define mmAFMT_60958_0                                                          0x1c41
++#define mmDIG0_AFMT_60958_0                                                     0x1c41
++#define mmDIG1_AFMT_60958_0                                                     0x1f41
++#define mmDIG2_AFMT_60958_0                                                     0x4241
++#define mmDIG3_AFMT_60958_0                                                     0x4541
++#define mmDIG4_AFMT_60958_0                                                     0x4841
++#define mmDIG5_AFMT_60958_0                                                     0x4b41
++#define mmDIG6_AFMT_60958_0                                                     0x4e41
++#define mmAFMT_60958_1                                                          0x1c42
++#define mmDIG0_AFMT_60958_1                                                     0x1c42
++#define mmDIG1_AFMT_60958_1                                                     0x1f42
++#define mmDIG2_AFMT_60958_1                                                     0x4242
++#define mmDIG3_AFMT_60958_1                                                     0x4542
++#define mmDIG4_AFMT_60958_1                                                     0x4842
++#define mmDIG5_AFMT_60958_1                                                     0x4b42
++#define mmDIG6_AFMT_60958_1                                                     0x4e42
++#define mmAFMT_AUDIO_CRC_CONTROL                                                0x1c43
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                           0x1c43
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                           0x1f43
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                           0x4243
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                           0x4543
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                           0x4843
++#define mmDIG5_AFMT_AUDIO_CRC_CONTROL                                           0x4b43
++#define mmDIG6_AFMT_AUDIO_CRC_CONTROL                                           0x4e43
++#define mmAFMT_RAMP_CONTROL0                                                    0x1c44
++#define mmDIG0_AFMT_RAMP_CONTROL0                                               0x1c44
++#define mmDIG1_AFMT_RAMP_CONTROL0                                               0x1f44
++#define mmDIG2_AFMT_RAMP_CONTROL0                                               0x4244
++#define mmDIG3_AFMT_RAMP_CONTROL0                                               0x4544
++#define mmDIG4_AFMT_RAMP_CONTROL0                                               0x4844
++#define mmDIG5_AFMT_RAMP_CONTROL0                                               0x4b44
++#define mmDIG6_AFMT_RAMP_CONTROL0                                               0x4e44
++#define mmAFMT_RAMP_CONTROL1                                                    0x1c45
++#define mmDIG0_AFMT_RAMP_CONTROL1                                               0x1c45
++#define mmDIG1_AFMT_RAMP_CONTROL1                                               0x1f45
++#define mmDIG2_AFMT_RAMP_CONTROL1                                               0x4245
++#define mmDIG3_AFMT_RAMP_CONTROL1                                               0x4545
++#define mmDIG4_AFMT_RAMP_CONTROL1                                               0x4845
++#define mmDIG5_AFMT_RAMP_CONTROL1                                               0x4b45
++#define mmDIG6_AFMT_RAMP_CONTROL1                                               0x4e45
++#define mmAFMT_RAMP_CONTROL2                                                    0x1c46
++#define mmDIG0_AFMT_RAMP_CONTROL2                                               0x1c46
++#define mmDIG1_AFMT_RAMP_CONTROL2                                               0x1f46
++#define mmDIG2_AFMT_RAMP_CONTROL2                                               0x4246
++#define mmDIG3_AFMT_RAMP_CONTROL2                                               0x4546
++#define mmDIG4_AFMT_RAMP_CONTROL2                                               0x4846
++#define mmDIG5_AFMT_RAMP_CONTROL2                                               0x4b46
++#define mmDIG6_AFMT_RAMP_CONTROL2                                               0x4e46
++#define mmAFMT_RAMP_CONTROL3                                                    0x1c47
++#define mmDIG0_AFMT_RAMP_CONTROL3                                               0x1c47
++#define mmDIG1_AFMT_RAMP_CONTROL3                                               0x1f47
++#define mmDIG2_AFMT_RAMP_CONTROL3                                               0x4247
++#define mmDIG3_AFMT_RAMP_CONTROL3                                               0x4547
++#define mmDIG4_AFMT_RAMP_CONTROL3                                               0x4847
++#define mmDIG5_AFMT_RAMP_CONTROL3                                               0x4b47
++#define mmDIG6_AFMT_RAMP_CONTROL3                                               0x4e47
++#define mmAFMT_60958_2                                                          0x1c48
++#define mmDIG0_AFMT_60958_2                                                     0x1c48
++#define mmDIG1_AFMT_60958_2                                                     0x1f48
++#define mmDIG2_AFMT_60958_2                                                     0x4248
++#define mmDIG3_AFMT_60958_2                                                     0x4548
++#define mmDIG4_AFMT_60958_2                                                     0x4848
++#define mmDIG5_AFMT_60958_2                                                     0x4b48
++#define mmDIG6_AFMT_60958_2                                                     0x4e48
++#define mmAFMT_AUDIO_CRC_RESULT                                                 0x1c49
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT                                            0x1c49
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT                                            0x1f49
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT                                            0x4249
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT                                            0x4549
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT                                            0x4849
++#define mmDIG5_AFMT_AUDIO_CRC_RESULT                                            0x4b49
++#define mmDIG6_AFMT_AUDIO_CRC_RESULT                                            0x4e49
++#define mmAFMT_STATUS                                                           0x1c4a
++#define mmDIG0_AFMT_STATUS                                                      0x1c4a
++#define mmDIG1_AFMT_STATUS                                                      0x1f4a
++#define mmDIG2_AFMT_STATUS                                                      0x424a
++#define mmDIG3_AFMT_STATUS                                                      0x454a
++#define mmDIG4_AFMT_STATUS                                                      0x484a
++#define mmDIG5_AFMT_STATUS                                                      0x4b4a
++#define mmDIG6_AFMT_STATUS                                                      0x4e4a
++#define mmAFMT_AUDIO_PACKET_CONTROL                                             0x1c4b
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                        0x1c4b
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                        0x1f4b
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                        0x424b
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                        0x454b
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                        0x484b
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                        0x4b4b
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                        0x4e4b
++#define mmAFMT_VBI_PACKET_CONTROL                                               0x1c4c
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL                                          0x1c4c
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL                                          0x1f4c
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL                                          0x424c
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL                                          0x454c
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL                                          0x484c
++#define mmDIG5_AFMT_VBI_PACKET_CONTROL                                          0x4b4c
++#define mmDIG6_AFMT_VBI_PACKET_CONTROL                                          0x4e4c
++#define mmAFMT_INFOFRAME_CONTROL0                                               0x1c4d
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0                                          0x1c4d
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0                                          0x1f4d
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0                                          0x424d
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0                                          0x454d
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0                                          0x484d
++#define mmDIG5_AFMT_INFOFRAME_CONTROL0                                          0x4b4d
++#define mmDIG6_AFMT_INFOFRAME_CONTROL0                                          0x4e4d
++#define mmAFMT_AUDIO_SRC_CONTROL                                                0x1c4f
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                           0x1c4f
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                           0x1f4f
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                           0x424f
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                           0x454f
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                           0x484f
++#define mmDIG5_AFMT_AUDIO_SRC_CONTROL                                           0x4b4f
++#define mmDIG6_AFMT_AUDIO_SRC_CONTROL                                           0x4e4f
++#define mmAFMT_AUDIO_DBG_DTO_CNTL                                               0x1c52
++#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL                                          0x1c52
++#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                                          0x1f52
++#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4252
++#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4552
++#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4852
++#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4b52
++#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4e52
++#define mmDIG_BE_CNTL                                                           0x1c50
++#define mmDIG0_DIG_BE_CNTL                                                      0x1c50
++#define mmDIG1_DIG_BE_CNTL                                                      0x1f50
++#define mmDIG2_DIG_BE_CNTL                                                      0x4250
++#define mmDIG3_DIG_BE_CNTL                                                      0x4550
++#define mmDIG4_DIG_BE_CNTL                                                      0x4850
++#define mmDIG5_DIG_BE_CNTL                                                      0x4b50
++#define mmDIG6_DIG_BE_CNTL                                                      0x4e50
++#define mmDIG_BE_EN_CNTL                                                        0x1c51
++#define mmDIG0_DIG_BE_EN_CNTL                                                   0x1c51
++#define mmDIG1_DIG_BE_EN_CNTL                                                   0x1f51
++#define mmDIG2_DIG_BE_EN_CNTL                                                   0x4251
++#define mmDIG3_DIG_BE_EN_CNTL                                                   0x4551
++#define mmDIG4_DIG_BE_EN_CNTL                                                   0x4851
++#define mmDIG5_DIG_BE_EN_CNTL                                                   0x4b51
++#define mmDIG6_DIG_BE_EN_CNTL                                                   0x4e51
++#define mmTMDS_CNTL                                                             0x1c7c
++#define mmDIG0_TMDS_CNTL                                                        0x1c7c
++#define mmDIG1_TMDS_CNTL                                                        0x1f7c
++#define mmDIG2_TMDS_CNTL                                                        0x427c
++#define mmDIG3_TMDS_CNTL                                                        0x457c
++#define mmDIG4_TMDS_CNTL                                                        0x487c
++#define mmDIG5_TMDS_CNTL                                                        0x4b7c
++#define mmDIG6_TMDS_CNTL                                                        0x4e7c
++#define mmTMDS_CONTROL_CHAR                                                     0x1c7d
++#define mmDIG0_TMDS_CONTROL_CHAR                                                0x1c7d
++#define mmDIG1_TMDS_CONTROL_CHAR                                                0x1f7d
++#define mmDIG2_TMDS_CONTROL_CHAR                                                0x427d
++#define mmDIG3_TMDS_CONTROL_CHAR                                                0x457d
++#define mmDIG4_TMDS_CONTROL_CHAR                                                0x487d
++#define mmDIG5_TMDS_CONTROL_CHAR                                                0x4b7d
++#define mmDIG6_TMDS_CONTROL_CHAR                                                0x4e7d
++#define mmTMDS_CONTROL0_FEEDBACK                                                0x1c7e
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                           0x1c7e
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                           0x1f7e
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                           0x427e
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                           0x457e
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK                                           0x487e
++#define mmDIG5_TMDS_CONTROL0_FEEDBACK                                           0x4b7e
++#define mmDIG6_TMDS_CONTROL0_FEEDBACK                                           0x4e7e
++#define mmTMDS_STEREOSYNC_CTL_SEL                                               0x1c7f
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                          0x1c7f
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                          0x1f7f
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                          0x427f
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                          0x457f
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                          0x487f
++#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                          0x4b7f
++#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                          0x4e7f
++#define mmTMDS_SYNC_CHAR_PATTERN_0_1                                            0x1c80
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x1c80
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x1f80
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4280
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4580
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4880
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4b80
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4e80
++#define mmTMDS_SYNC_CHAR_PATTERN_2_3                                            0x1c81
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x1c81
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x1f81
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4281
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4581
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4881
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4b81
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4e81
++#define mmTMDS_DEBUG                                                            0x1c82
++#define mmDIG0_TMDS_DEBUG                                                       0x1c82
++#define mmDIG1_TMDS_DEBUG                                                       0x1f82
++#define mmDIG2_TMDS_DEBUG                                                       0x4282
++#define mmDIG3_TMDS_DEBUG                                                       0x4582
++#define mmDIG4_TMDS_DEBUG                                                       0x4882
++#define mmDIG5_TMDS_DEBUG                                                       0x4b82
++#define mmDIG6_TMDS_DEBUG                                                       0x4e82
++#define mmTMDS_CTL_BITS                                                         0x1c83
++#define mmDIG0_TMDS_CTL_BITS                                                    0x1c83
++#define mmDIG1_TMDS_CTL_BITS                                                    0x1f83
++#define mmDIG2_TMDS_CTL_BITS                                                    0x4283
++#define mmDIG3_TMDS_CTL_BITS                                                    0x4583
++#define mmDIG4_TMDS_CTL_BITS                                                    0x4883
++#define mmDIG5_TMDS_CTL_BITS                                                    0x4b83
++#define mmDIG6_TMDS_CTL_BITS                                                    0x4e83
++#define mmTMDS_DCBALANCER_CONTROL                                               0x1c84
++#define mmDIG0_TMDS_DCBALANCER_CONTROL                                          0x1c84
++#define mmDIG1_TMDS_DCBALANCER_CONTROL                                          0x1f84
++#define mmDIG2_TMDS_DCBALANCER_CONTROL                                          0x4284
++#define mmDIG3_TMDS_DCBALANCER_CONTROL                                          0x4584
++#define mmDIG4_TMDS_DCBALANCER_CONTROL                                          0x4884
++#define mmDIG5_TMDS_DCBALANCER_CONTROL                                          0x4b84
++#define mmDIG6_TMDS_DCBALANCER_CONTROL                                          0x4e84
++#define mmTMDS_CTL0_1_GEN_CNTL                                                  0x1c86
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                             0x1c86
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                             0x1f86
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                             0x4286
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                             0x4586
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                             0x4886
++#define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                             0x4b86
++#define mmDIG6_TMDS_CTL0_1_GEN_CNTL                                             0x4e86
++#define mmTMDS_CTL2_3_GEN_CNTL                                                  0x1c87
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                             0x1c87
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                             0x1f87
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                             0x4287
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                             0x4587
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                             0x4887
++#define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                             0x4b87
++#define mmDIG6_TMDS_CTL2_3_GEN_CNTL                                             0x4e87
++#define mmLVDS_DATA_CNTL                                                        0x1c8c
++#define mmDIG0_LVDS_DATA_CNTL                                                   0x1c8c
++#define mmDIG1_LVDS_DATA_CNTL                                                   0x1f8c
++#define mmDIG2_LVDS_DATA_CNTL                                                   0x428c
++#define mmDIG3_LVDS_DATA_CNTL                                                   0x458c
++#define mmDIG4_LVDS_DATA_CNTL                                                   0x488c
++#define mmDIG5_LVDS_DATA_CNTL                                                   0x4b8c
++#define mmDIG6_LVDS_DATA_CNTL                                                   0x4e8c
++#define mmDIG_LANE_ENABLE                                                       0x1c8d
++#define mmDIG0_DIG_LANE_ENABLE                                                  0x1c8d
++#define mmDIG1_DIG_LANE_ENABLE                                                  0x1f8d
++#define mmDIG2_DIG_LANE_ENABLE                                                  0x428d
++#define mmDIG3_DIG_LANE_ENABLE                                                  0x458d
++#define mmDIG4_DIG_LANE_ENABLE                                                  0x488d
++#define mmDIG5_DIG_LANE_ENABLE                                                  0x4b8d
++#define mmDIG6_DIG_LANE_ENABLE                                                  0x4e8d
++#define mmDOUT_SCRATCH0                                                         0x1844
++#define mmDOUT_SCRATCH1                                                         0x1845
++#define mmDOUT_SCRATCH2                                                         0x1846
++#define mmDOUT_SCRATCH3                                                         0x1847
++#define mmDOUT_SCRATCH4                                                         0x1848
++#define mmDOUT_SCRATCH5                                                         0x1849
++#define mmDOUT_SCRATCH6                                                         0x184a
++#define mmDOUT_SCRATCH7                                                         0x184b
++#define mmDOUT_DCE_VCE_CONTROL                                                  0x18ff
++#define mmDC_HPD1_INT_STATUS                                                    0x1807
++#define mmDC_HPD1_INT_CONTROL                                                   0x1808
++#define mmDC_HPD1_CONTROL                                                       0x1809
++#define mmDC_HPD2_INT_STATUS                                                    0x180a
++#define mmDC_HPD2_INT_CONTROL                                                   0x180b
++#define mmDC_HPD2_CONTROL                                                       0x180c
++#define mmDC_HPD3_INT_STATUS                                                    0x180d
++#define mmDC_HPD3_INT_CONTROL                                                   0x180e
++#define mmDC_HPD3_CONTROL                                                       0x180f
++#define mmDC_HPD4_INT_STATUS                                                    0x1810
++#define mmDC_HPD4_INT_CONTROL                                                   0x1811
++#define mmDC_HPD4_CONTROL                                                       0x1812
++#define mmDC_HPD5_INT_STATUS                                                    0x1813
++#define mmDC_HPD5_INT_CONTROL                                                   0x1814
++#define mmDC_HPD5_CONTROL                                                       0x1815
++#define mmDC_HPD6_INT_STATUS                                                    0x1816
++#define mmDC_HPD6_INT_CONTROL                                                   0x1817
++#define mmDC_HPD6_CONTROL                                                       0x1818
++#define mmDC_HPD1_FAST_TRAIN_CNTL                                               0x1864
++#define mmDC_HPD2_FAST_TRAIN_CNTL                                               0x1865
++#define mmDC_HPD3_FAST_TRAIN_CNTL                                               0x1866
++#define mmDC_HPD4_FAST_TRAIN_CNTL                                               0x1867
++#define mmDC_HPD5_FAST_TRAIN_CNTL                                               0x1868
++#define mmDC_HPD6_FAST_TRAIN_CNTL                                               0x1869
++#define mmDC_HPD1_TOGGLE_FILT_CNTL                                              0x18bc
++#define mmDC_HPD2_TOGGLE_FILT_CNTL                                              0x18bd
++#define mmDC_HPD3_TOGGLE_FILT_CNTL                                              0x18be
++#define mmDC_HPD4_TOGGLE_FILT_CNTL                                              0x18fc
++#define mmDC_HPD5_TOGGLE_FILT_CNTL                                              0x18fd
++#define mmDC_HPD6_TOGGLE_FILT_CNTL                                              0x18fe
++#define mmDC_I2C_CONTROL                                                        0x1819
++#define mmDC_I2C_ARBITRATION                                                    0x181a
++#define mmDC_I2C_INTERRUPT_CONTROL                                              0x181b
++#define mmDC_I2C_SW_STATUS                                                      0x181c
++#define mmDC_I2C_DDC1_HW_STATUS                                                 0x181d
++#define mmDC_I2C_DDC2_HW_STATUS                                                 0x181e
++#define mmDC_I2C_DDC3_HW_STATUS                                                 0x181f
++#define mmDC_I2C_DDC4_HW_STATUS                                                 0x1820
++#define mmDC_I2C_DDC5_HW_STATUS                                                 0x1821
++#define mmDC_I2C_DDC6_HW_STATUS                                                 0x1822
++#define mmDC_I2C_DDC1_SPEED                                                     0x1823
++#define mmDC_I2C_DDC1_SETUP                                                     0x1824
++#define mmDC_I2C_DDC2_SPEED                                                     0x1825
++#define mmDC_I2C_DDC2_SETUP                                                     0x1826
++#define mmDC_I2C_DDC3_SPEED                                                     0x1827
++#define mmDC_I2C_DDC3_SETUP                                                     0x1828
++#define mmDC_I2C_DDC4_SPEED                                                     0x1829
++#define mmDC_I2C_DDC4_SETUP                                                     0x182a
++#define mmDC_I2C_DDC5_SPEED                                                     0x182b
++#define mmDC_I2C_DDC5_SETUP                                                     0x182c
++#define mmDC_I2C_DDC6_SPEED                                                     0x182d
++#define mmDC_I2C_DDC6_SETUP                                                     0x182e
++#define mmDC_I2C_TRANSACTION0                                                   0x182f
++#define mmDC_I2C_TRANSACTION1                                                   0x1830
++#define mmDC_I2C_TRANSACTION2                                                   0x1831
++#define mmDC_I2C_TRANSACTION3                                                   0x1832
++#define mmDC_I2C_DATA                                                           0x1833
++#define mmGENERIC_I2C_CONTROL                                                   0x1834
++#define mmGENERIC_I2C_INTERRUPT_CONTROL                                         0x1835
++#define mmGENERIC_I2C_STATUS                                                    0x1836
++#define mmGENERIC_I2C_SPEED                                                     0x1837
++#define mmGENERIC_I2C_SETUP                                                     0x1838
++#define mmGENERIC_I2C_TRANSACTION                                               0x1839
++#define mmGENERIC_I2C_DATA                                                      0x183a
++#define mmGENERIC_I2C_PIN_SELECTION                                             0x183b
++#define mmGENERIC_I2C_PIN_DEBUG                                                 0x183c
++#define mmDISP_INTERRUPT_STATUS                                                 0x183d
++#define mmDISP_INTERRUPT_STATUS_CONTINUE                                        0x183e
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                       0x183f
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                       0x1840
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                       0x1853
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                       0x1854
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                       0x19e0
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                       0x19e1
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                       0x19e2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                       0x19e3
++#define mmDOUT_POWER_MANAGEMENT_CNTL                                            0x1841
++#define mmDISP_TIMER_CONTROL                                                    0x1842
++#define mmDC_I2C_DDCVGA_HW_STATUS                                               0x1855
++#define mmDC_I2C_DDCVGA_SPEED                                                   0x1856
++#define mmDC_I2C_DDCVGA_SETUP                                                   0x1857
++#define mmDC_I2C_EDID_DETECT_CTRL                                               0x186f
++#define mmDISPOUT_STEREOSYNC_SEL                                                0x18bf
++#define mmDOUT_TEST_DEBUG_INDEX                                                 0x184d
++#define mmDOUT_TEST_DEBUG_DATA                                                  0x184e
++#define ixDP_AUX1_DEBUG_A                                                       0x10
++#define ixDP_AUX1_DEBUG_B                                                       0x11
++#define ixDP_AUX1_DEBUG_C                                                       0x12
++#define ixDP_AUX1_DEBUG_D                                                       0x13
++#define ixDP_AUX1_DEBUG_E                                                       0x14
++#define ixDP_AUX1_DEBUG_F                                                       0x15
++#define ixDP_AUX1_DEBUG_G                                                       0x16
++#define ixDP_AUX1_DEBUG_H                                                       0x17
++#define ixDP_AUX1_DEBUG_I                                                       0x18
++#define ixDP_AUX1_DEBUG_J                                                       0x19
++#define ixDP_AUX1_DEBUG_K                                                       0x1a
++#define ixDP_AUX1_DEBUG_L                                                       0x1b
++#define ixDP_AUX1_DEBUG_M                                                       0x1c
++#define ixDP_AUX1_DEBUG_N                                                       0x1d
++#define ixDP_AUX1_DEBUG_O                                                       0x1e
++#define ixDP_AUX1_DEBUG_P                                                       0x1f
++#define ixDP_AUX1_DEBUG_Q                                                       0x90
++#define ixDP_AUX2_DEBUG_A                                                       0x20
++#define ixDP_AUX2_DEBUG_B                                                       0x21
++#define ixDP_AUX2_DEBUG_C                                                       0x22
++#define ixDP_AUX2_DEBUG_D                                                       0x23
++#define ixDP_AUX2_DEBUG_E                                                       0x24
++#define ixDP_AUX2_DEBUG_F                                                       0x25
++#define ixDP_AUX2_DEBUG_G                                                       0x26
++#define ixDP_AUX2_DEBUG_H                                                       0x27
++#define ixDP_AUX2_DEBUG_I                                                       0x28
++#define ixDP_AUX2_DEBUG_J                                                       0x29
++#define ixDP_AUX2_DEBUG_K                                                       0x2a
++#define ixDP_AUX2_DEBUG_L                                                       0x2b
++#define ixDP_AUX2_DEBUG_M                                                       0x2c
++#define ixDP_AUX2_DEBUG_N                                                       0x2d
++#define ixDP_AUX2_DEBUG_O                                                       0x2e
++#define ixDP_AUX2_DEBUG_P                                                       0x2f
++#define ixDP_AUX2_DEBUG_Q                                                       0x91
++#define ixDP_AUX3_DEBUG_A                                                       0x30
++#define ixDP_AUX3_DEBUG_B                                                       0x31
++#define ixDP_AUX3_DEBUG_C                                                       0x32
++#define ixDP_AUX3_DEBUG_D                                                       0x33
++#define ixDP_AUX3_DEBUG_E                                                       0x34
++#define ixDP_AUX3_DEBUG_F                                                       0x35
++#define ixDP_AUX3_DEBUG_G                                                       0x36
++#define ixDP_AUX3_DEBUG_H                                                       0x37
++#define ixDP_AUX3_DEBUG_I                                                       0x38
++#define ixDP_AUX3_DEBUG_J                                                       0x39
++#define ixDP_AUX3_DEBUG_K                                                       0x3a
++#define ixDP_AUX3_DEBUG_L                                                       0x3b
++#define ixDP_AUX3_DEBUG_M                                                       0x3c
++#define ixDP_AUX3_DEBUG_N                                                       0x3d
++#define ixDP_AUX3_DEBUG_O                                                       0x3e
++#define ixDP_AUX3_DEBUG_P                                                       0x3f
++#define ixDP_AUX3_DEBUG_Q                                                       0x92
++#define ixDP_AUX4_DEBUG_A                                                       0x40
++#define ixDP_AUX4_DEBUG_B                                                       0x41
++#define ixDP_AUX4_DEBUG_C                                                       0x42
++#define ixDP_AUX4_DEBUG_D                                                       0x43
++#define ixDP_AUX4_DEBUG_E                                                       0x44
++#define ixDP_AUX4_DEBUG_F                                                       0x45
++#define ixDP_AUX4_DEBUG_G                                                       0x46
++#define ixDP_AUX4_DEBUG_H                                                       0x47
++#define ixDP_AUX4_DEBUG_I                                                       0x48
++#define ixDP_AUX4_DEBUG_J                                                       0x49
++#define ixDP_AUX4_DEBUG_K                                                       0x4a
++#define ixDP_AUX4_DEBUG_L                                                       0x4b
++#define ixDP_AUX4_DEBUG_M                                                       0x4c
++#define ixDP_AUX4_DEBUG_N                                                       0x4d
++#define ixDP_AUX4_DEBUG_O                                                       0x4e
++#define ixDP_AUX4_DEBUG_P                                                       0x4f
++#define ixDP_AUX4_DEBUG_Q                                                       0x93
++#define ixDP_AUX5_DEBUG_A                                                       0x70
++#define ixDP_AUX5_DEBUG_B                                                       0x71
++#define ixDP_AUX5_DEBUG_C                                                       0x72
++#define ixDP_AUX5_DEBUG_D                                                       0x73
++#define ixDP_AUX5_DEBUG_E                                                       0x74
++#define ixDP_AUX5_DEBUG_F                                                       0x75
++#define ixDP_AUX5_DEBUG_G                                                       0x76
++#define ixDP_AUX5_DEBUG_H                                                       0x77
++#define ixDP_AUX5_DEBUG_I                                                       0x78
++#define ixDP_AUX5_DEBUG_J                                                       0x79
++#define ixDP_AUX5_DEBUG_K                                                       0x7a
++#define ixDP_AUX5_DEBUG_L                                                       0x7b
++#define ixDP_AUX5_DEBUG_M                                                       0x7c
++#define ixDP_AUX5_DEBUG_N                                                       0x7d
++#define ixDP_AUX5_DEBUG_O                                                       0x7f
++#define ixDP_AUX5_DEBUG_P                                                       0x94
++#define ixDP_AUX5_DEBUG_Q                                                       0x95
++#define ixDP_AUX6_DEBUG_A                                                       0x80
++#define ixDP_AUX6_DEBUG_B                                                       0x81
++#define ixDP_AUX6_DEBUG_C                                                       0x82
++#define ixDP_AUX6_DEBUG_D                                                       0x83
++#define ixDP_AUX6_DEBUG_E                                                       0x84
++#define ixDP_AUX6_DEBUG_F                                                       0x85
++#define ixDP_AUX6_DEBUG_G                                                       0x86
++#define ixDP_AUX6_DEBUG_H                                                       0x87
++#define ixDP_AUX6_DEBUG_I                                                       0x88
++#define ixDP_AUX6_DEBUG_J                                                       0x89
++#define ixDP_AUX6_DEBUG_K                                                       0x8a
++#define ixDP_AUX6_DEBUG_L                                                       0x8b
++#define ixDP_AUX6_DEBUG_M                                                       0x8c
++#define ixDP_AUX6_DEBUG_N                                                       0x8d
++#define ixDP_AUX6_DEBUG_O                                                       0x8f
++#define ixDP_AUX6_DEBUG_P                                                       0x96
++#define ixDP_AUX6_DEBUG_Q                                                       0x97
++#define mmDMCU_CTRL                                                             0x1600
++#define mmDMCU_STATUS                                                           0x1601
++#define mmDMCU_PC_START_ADDR                                                    0x1602
++#define mmDMCU_FW_START_ADDR                                                    0x1603
++#define mmDMCU_FW_END_ADDR                                                      0x1604
++#define mmDMCU_FW_ISR_START_ADDR                                                0x1605
++#define mmDMCU_FW_CS_HI                                                         0x1606
++#define mmDMCU_FW_CS_LO                                                         0x1607
++#define mmDMCU_RAM_ACCESS_CTRL                                                  0x1608
++#define mmDMCU_ERAM_WR_CTRL                                                     0x1609
++#define mmDMCU_ERAM_WR_DATA                                                     0x160a
++#define mmDMCU_ERAM_RD_CTRL                                                     0x160b
++#define mmDMCU_ERAM_RD_DATA                                                     0x160c
++#define mmDMCU_IRAM_WR_CTRL                                                     0x160d
++#define mmDMCU_IRAM_WR_DATA                                                     0x160e
++#define mmDMCU_IRAM_RD_CTRL                                                     0x160f
++#define mmDMCU_IRAM_RD_DATA                                                     0x1610
++#define mmDMCU_EVENT_TRIGGER                                                    0x1611
++#define mmDMCU_UC_INTERNAL_INT_STATUS                                           0x1612
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                         0x1613
++#define mmDMCU_INTERRUPT_STATUS                                                 0x1614
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                        0x1615
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                          0x1616
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                     0x1617
++#define mmDC_DMCU_SCRATCH                                                       0x1618
++#define mmDMCU_INT_CNT                                                          0x1619
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                        0x161a
++#define mmDMCU_UC_CLK_GATING_CNTL                                               0x161b
++#define mmMASTER_COMM_DATA_REG1                                                 0x161c
++#define mmMASTER_COMM_DATA_REG2                                                 0x161d
++#define mmMASTER_COMM_DATA_REG3                                                 0x161e
++#define mmMASTER_COMM_CMD_REG                                                   0x161f
++#define mmMASTER_COMM_CNTL_REG                                                  0x1620
++#define mmSLAVE_COMM_DATA_REG1                                                  0x1621
++#define mmSLAVE_COMM_DATA_REG2                                                  0x1622
++#define mmSLAVE_COMM_DATA_REG3                                                  0x1623
++#define mmSLAVE_COMM_CMD_REG                                                    0x1624
++#define mmSLAVE_COMM_CNTL_REG                                                   0x1625
++#define mmDMCU_TEST_DEBUG_INDEX                                                 0x1626
++#define mmDMCU_TEST_DEBUG_DATA                                                  0x1627
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                        0x1750
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                        0x1751
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                        0x1752
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                        0x1753
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                 0x1754
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                 0x1755
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                 0x1756
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                 0x1757
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                            0x1758
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                            0x1759
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                            0x175a
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                            0x175b
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1                               0x175c
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2                               0x175d
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3                               0x175e
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4                               0x175f
++#define mmDP_LINK_CNTL                                                          0x1cc0
++#define mmDP0_DP_LINK_CNTL                                                      0x1cc0
++#define mmDP1_DP_LINK_CNTL                                                      0x1fc0
++#define mmDP2_DP_LINK_CNTL                                                      0x42c0
++#define mmDP3_DP_LINK_CNTL                                                      0x45c0
++#define mmDP4_DP_LINK_CNTL                                                      0x48c0
++#define mmDP5_DP_LINK_CNTL                                                      0x4bc0
++#define mmDP6_DP_LINK_CNTL                                                      0x4ec0
++#define mmDP_PIXEL_FORMAT                                                       0x1cc1
++#define mmDP0_DP_PIXEL_FORMAT                                                   0x1cc1
++#define mmDP1_DP_PIXEL_FORMAT                                                   0x1fc1
++#define mmDP2_DP_PIXEL_FORMAT                                                   0x42c1
++#define mmDP3_DP_PIXEL_FORMAT                                                   0x45c1
++#define mmDP4_DP_PIXEL_FORMAT                                                   0x48c1
++#define mmDP5_DP_PIXEL_FORMAT                                                   0x4bc1
++#define mmDP6_DP_PIXEL_FORMAT                                                   0x4ec1
++#define mmDP_MSA_COLORIMETRY                                                    0x1cda
++#define mmDP0_DP_MSA_COLORIMETRY                                                0x1cda
++#define mmDP1_DP_MSA_COLORIMETRY                                                0x1fda
++#define mmDP2_DP_MSA_COLORIMETRY                                                0x42da
++#define mmDP3_DP_MSA_COLORIMETRY                                                0x45da
++#define mmDP4_DP_MSA_COLORIMETRY                                                0x48da
++#define mmDP5_DP_MSA_COLORIMETRY                                                0x4bda
++#define mmDP6_DP_MSA_COLORIMETRY                                                0x4eda
++#define mmDP_CONFIG                                                             0x1cc2
++#define mmDP0_DP_CONFIG                                                         0x1cc2
++#define mmDP1_DP_CONFIG                                                         0x1fc2
++#define mmDP2_DP_CONFIG                                                         0x42c2
++#define mmDP3_DP_CONFIG                                                         0x45c2
++#define mmDP4_DP_CONFIG                                                         0x48c2
++#define mmDP5_DP_CONFIG                                                         0x4bc2
++#define mmDP6_DP_CONFIG                                                         0x4ec2
++#define mmDP_VID_STREAM_CNTL                                                    0x1cc3
++#define mmDP0_DP_VID_STREAM_CNTL                                                0x1cc3
++#define mmDP1_DP_VID_STREAM_CNTL                                                0x1fc3
++#define mmDP2_DP_VID_STREAM_CNTL                                                0x42c3
++#define mmDP3_DP_VID_STREAM_CNTL                                                0x45c3
++#define mmDP4_DP_VID_STREAM_CNTL                                                0x48c3
++#define mmDP5_DP_VID_STREAM_CNTL                                                0x4bc3
++#define mmDP6_DP_VID_STREAM_CNTL                                                0x4ec3
++#define mmDP_STEER_FIFO                                                         0x1cc4
++#define mmDP0_DP_STEER_FIFO                                                     0x1cc4
++#define mmDP1_DP_STEER_FIFO                                                     0x1fc4
++#define mmDP2_DP_STEER_FIFO                                                     0x42c4
++#define mmDP3_DP_STEER_FIFO                                                     0x45c4
++#define mmDP4_DP_STEER_FIFO                                                     0x48c4
++#define mmDP5_DP_STEER_FIFO                                                     0x4bc4
++#define mmDP6_DP_STEER_FIFO                                                     0x4ec4
++#define mmDP_MSA_MISC                                                           0x1cc5
++#define mmDP0_DP_MSA_MISC                                                       0x1cc5
++#define mmDP1_DP_MSA_MISC                                                       0x1fc5
++#define mmDP2_DP_MSA_MISC                                                       0x42c5
++#define mmDP3_DP_MSA_MISC                                                       0x45c5
++#define mmDP4_DP_MSA_MISC                                                       0x48c5
++#define mmDP5_DP_MSA_MISC                                                       0x4bc5
++#define mmDP6_DP_MSA_MISC                                                       0x4ec5
++#define mmDP_VID_TIMING                                                         0x1cc9
++#define mmDP0_DP_VID_TIMING                                                     0x1cc9
++#define mmDP1_DP_VID_TIMING                                                     0x1fc9
++#define mmDP2_DP_VID_TIMING                                                     0x42c9
++#define mmDP3_DP_VID_TIMING                                                     0x45c9
++#define mmDP4_DP_VID_TIMING                                                     0x48c9
++#define mmDP5_DP_VID_TIMING                                                     0x4bc9
++#define mmDP6_DP_VID_TIMING                                                     0x4ec9
++#define mmDP_VID_N                                                              0x1cca
++#define mmDP0_DP_VID_N                                                          0x1cca
++#define mmDP1_DP_VID_N                                                          0x1fca
++#define mmDP2_DP_VID_N                                                          0x42ca
++#define mmDP3_DP_VID_N                                                          0x45ca
++#define mmDP4_DP_VID_N                                                          0x48ca
++#define mmDP5_DP_VID_N                                                          0x4bca
++#define mmDP6_DP_VID_N                                                          0x4eca
++#define mmDP_VID_M                                                              0x1ccb
++#define mmDP0_DP_VID_M                                                          0x1ccb
++#define mmDP1_DP_VID_M                                                          0x1fcb
++#define mmDP2_DP_VID_M                                                          0x42cb
++#define mmDP3_DP_VID_M                                                          0x45cb
++#define mmDP4_DP_VID_M                                                          0x48cb
++#define mmDP5_DP_VID_M                                                          0x4bcb
++#define mmDP6_DP_VID_M                                                          0x4ecb
++#define mmDP_LINK_FRAMING_CNTL                                                  0x1ccc
++#define mmDP0_DP_LINK_FRAMING_CNTL                                              0x1ccc
++#define mmDP1_DP_LINK_FRAMING_CNTL                                              0x1fcc
++#define mmDP2_DP_LINK_FRAMING_CNTL                                              0x42cc
++#define mmDP3_DP_LINK_FRAMING_CNTL                                              0x45cc
++#define mmDP4_DP_LINK_FRAMING_CNTL                                              0x48cc
++#define mmDP5_DP_LINK_FRAMING_CNTL                                              0x4bcc
++#define mmDP6_DP_LINK_FRAMING_CNTL                                              0x4ecc
++#define mmDP_HBR2_EYE_PATTERN                                                   0x1cc8
++#define mmDP0_DP_HBR2_EYE_PATTERN                                               0x1cc8
++#define mmDP1_DP_HBR2_EYE_PATTERN                                               0x1fc8
++#define mmDP2_DP_HBR2_EYE_PATTERN                                               0x42c8
++#define mmDP3_DP_HBR2_EYE_PATTERN                                               0x45c8
++#define mmDP4_DP_HBR2_EYE_PATTERN                                               0x48c8
++#define mmDP5_DP_HBR2_EYE_PATTERN                                               0x4bc8
++#define mmDP6_DP_HBR2_EYE_PATTERN                                               0x4ec8
++#define mmDP_VID_MSA_VBID                                                       0x1ccd
++#define mmDP0_DP_VID_MSA_VBID                                                   0x1ccd
++#define mmDP1_DP_VID_MSA_VBID                                                   0x1fcd
++#define mmDP2_DP_VID_MSA_VBID                                                   0x42cd
++#define mmDP3_DP_VID_MSA_VBID                                                   0x45cd
++#define mmDP4_DP_VID_MSA_VBID                                                   0x48cd
++#define mmDP5_DP_VID_MSA_VBID                                                   0x4bcd
++#define mmDP6_DP_VID_MSA_VBID                                                   0x4ecd
++#define mmDP_VID_INTERRUPT_CNTL                                                 0x1ccf
++#define mmDP0_DP_VID_INTERRUPT_CNTL                                             0x1ccf
++#define mmDP1_DP_VID_INTERRUPT_CNTL                                             0x1fcf
++#define mmDP2_DP_VID_INTERRUPT_CNTL                                             0x42cf
++#define mmDP3_DP_VID_INTERRUPT_CNTL                                             0x45cf
++#define mmDP4_DP_VID_INTERRUPT_CNTL                                             0x48cf
++#define mmDP5_DP_VID_INTERRUPT_CNTL                                             0x4bcf
++#define mmDP6_DP_VID_INTERRUPT_CNTL                                             0x4ecf
++#define mmDP_DPHY_CNTL                                                          0x1cd0
++#define mmDP0_DP_DPHY_CNTL                                                      0x1cd0
++#define mmDP1_DP_DPHY_CNTL                                                      0x1fd0
++#define mmDP2_DP_DPHY_CNTL                                                      0x42d0
++#define mmDP3_DP_DPHY_CNTL                                                      0x45d0
++#define mmDP4_DP_DPHY_CNTL                                                      0x48d0
++#define mmDP5_DP_DPHY_CNTL                                                      0x4bd0
++#define mmDP6_DP_DPHY_CNTL                                                      0x4ed0
++#define mmDP_DPHY_TRAINING_PATTERN_SEL                                          0x1cd1
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                      0x1cd1
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                      0x1fd1
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                      0x42d1
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                      0x45d1
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                      0x48d1
++#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4bd1
++#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4ed1
++#define mmDP_DPHY_SYM0                                                          0x1cd2
++#define mmDP0_DP_DPHY_SYM0                                                      0x1cd2
++#define mmDP1_DP_DPHY_SYM0                                                      0x1fd2
++#define mmDP2_DP_DPHY_SYM0                                                      0x42d2
++#define mmDP3_DP_DPHY_SYM0                                                      0x45d2
++#define mmDP4_DP_DPHY_SYM0                                                      0x48d2
++#define mmDP5_DP_DPHY_SYM0                                                      0x4bd2
++#define mmDP6_DP_DPHY_SYM0                                                      0x4ed2
++#define mmDP_DPHY_SYM1                                                          0x1ce0
++#define mmDP0_DP_DPHY_SYM1                                                      0x1ce0
++#define mmDP1_DP_DPHY_SYM1                                                      0x1fe0
++#define mmDP2_DP_DPHY_SYM1                                                      0x42e0
++#define mmDP3_DP_DPHY_SYM1                                                      0x45e0
++#define mmDP4_DP_DPHY_SYM1                                                      0x48e0
++#define mmDP5_DP_DPHY_SYM1                                                      0x4be0
++#define mmDP6_DP_DPHY_SYM1                                                      0x4ee0
++#define mmDP_DPHY_SYM2                                                          0x1cdf
++#define mmDP0_DP_DPHY_SYM2                                                      0x1cdf
++#define mmDP1_DP_DPHY_SYM2                                                      0x1fdf
++#define mmDP2_DP_DPHY_SYM2                                                      0x42df
++#define mmDP3_DP_DPHY_SYM2                                                      0x45df
++#define mmDP4_DP_DPHY_SYM2                                                      0x48df
++#define mmDP5_DP_DPHY_SYM2                                                      0x4bdf
++#define mmDP6_DP_DPHY_SYM2                                                      0x4edf
++#define mmDP_DPHY_8B10B_CNTL                                                    0x1cd3
++#define mmDP0_DP_DPHY_8B10B_CNTL                                                0x1cd3
++#define mmDP1_DP_DPHY_8B10B_CNTL                                                0x1fd3
++#define mmDP2_DP_DPHY_8B10B_CNTL                                                0x42d3
++#define mmDP3_DP_DPHY_8B10B_CNTL                                                0x45d3
++#define mmDP4_DP_DPHY_8B10B_CNTL                                                0x48d3
++#define mmDP5_DP_DPHY_8B10B_CNTL                                                0x4bd3
++#define mmDP6_DP_DPHY_8B10B_CNTL                                                0x4ed3
++#define mmDP_DPHY_PRBS_CNTL                                                     0x1cd4
++#define mmDP0_DP_DPHY_PRBS_CNTL                                                 0x1cd4
++#define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x1fd4
++#define mmDP2_DP_DPHY_PRBS_CNTL                                                 0x42d4
++#define mmDP3_DP_DPHY_PRBS_CNTL                                                 0x45d4
++#define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x48d4
++#define mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4bd4
++#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x4ed4
++#define mmDP_DPHY_CRC_EN                                                        0x1cd6
++#define mmDP0_DP_DPHY_CRC_EN                                                    0x1cd6
++#define mmDP1_DP_DPHY_CRC_EN                                                    0x1fd6
++#define mmDP2_DP_DPHY_CRC_EN                                                    0x42d6
++#define mmDP3_DP_DPHY_CRC_EN                                                    0x45d6
++#define mmDP4_DP_DPHY_CRC_EN                                                    0x48d6
++#define mmDP5_DP_DPHY_CRC_EN                                                    0x4bd6
++#define mmDP6_DP_DPHY_CRC_EN                                                    0x4ed6
++#define mmDP_DPHY_CRC_CNTL                                                      0x1cd7
++#define mmDP0_DP_DPHY_CRC_CNTL                                                  0x1cd7
++#define mmDP1_DP_DPHY_CRC_CNTL                                                  0x1fd7
++#define mmDP2_DP_DPHY_CRC_CNTL                                                  0x42d7
++#define mmDP3_DP_DPHY_CRC_CNTL                                                  0x45d7
++#define mmDP4_DP_DPHY_CRC_CNTL                                                  0x48d7
++#define mmDP5_DP_DPHY_CRC_CNTL                                                  0x4bd7
++#define mmDP6_DP_DPHY_CRC_CNTL                                                  0x4ed7
++#define mmDP_DPHY_CRC_RESULT                                                    0x1cd8
++#define mmDP0_DP_DPHY_CRC_RESULT                                                0x1cd8
++#define mmDP1_DP_DPHY_CRC_RESULT                                                0x1fd8
++#define mmDP2_DP_DPHY_CRC_RESULT                                                0x42d8
++#define mmDP3_DP_DPHY_CRC_RESULT                                                0x45d8
++#define mmDP4_DP_DPHY_CRC_RESULT                                                0x48d8
++#define mmDP5_DP_DPHY_CRC_RESULT                                                0x4bd8
++#define mmDP6_DP_DPHY_CRC_RESULT                                                0x4ed8
++#define mmDP_DPHY_CRC_MST_CNTL                                                  0x1cc6
++#define mmDP0_DP_DPHY_CRC_MST_CNTL                                              0x1cc6
++#define mmDP1_DP_DPHY_CRC_MST_CNTL                                              0x1fc6
++#define mmDP2_DP_DPHY_CRC_MST_CNTL                                              0x42c6
++#define mmDP3_DP_DPHY_CRC_MST_CNTL                                              0x45c6
++#define mmDP4_DP_DPHY_CRC_MST_CNTL                                              0x48c6
++#define mmDP5_DP_DPHY_CRC_MST_CNTL                                              0x4bc6
++#define mmDP6_DP_DPHY_CRC_MST_CNTL                                              0x4ec6
++#define mmDP_DPHY_CRC_MST_STATUS                                                0x1cc7
++#define mmDP0_DP_DPHY_CRC_MST_STATUS                                            0x1cc7
++#define mmDP1_DP_DPHY_CRC_MST_STATUS                                            0x1fc7
++#define mmDP2_DP_DPHY_CRC_MST_STATUS                                            0x42c7
++#define mmDP3_DP_DPHY_CRC_MST_STATUS                                            0x45c7
++#define mmDP4_DP_DPHY_CRC_MST_STATUS                                            0x48c7
++#define mmDP5_DP_DPHY_CRC_MST_STATUS                                            0x4bc7
++#define mmDP6_DP_DPHY_CRC_MST_STATUS                                            0x4ec7
++#define mmDP_DPHY_FAST_TRAINING                                                 0x1cce
++#define mmDP0_DP_DPHY_FAST_TRAINING                                             0x1cce
++#define mmDP1_DP_DPHY_FAST_TRAINING                                             0x1fce
++#define mmDP2_DP_DPHY_FAST_TRAINING                                             0x42ce
++#define mmDP3_DP_DPHY_FAST_TRAINING                                             0x45ce
++#define mmDP4_DP_DPHY_FAST_TRAINING                                             0x48ce
++#define mmDP5_DP_DPHY_FAST_TRAINING                                             0x4bce
++#define mmDP6_DP_DPHY_FAST_TRAINING                                             0x4ece
++#define mmDP_DPHY_FAST_TRAINING_STATUS                                          0x1ce9
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                      0x1ce9
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                      0x1fe9
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                      0x42e9
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                      0x45e9
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                      0x48e9
++#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                      0x4be9
++#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                      0x4ee9
++#define mmDP_MSA_V_TIMING_OVERRIDE1                                             0x1cea
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                         0x1cea
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                         0x1fea
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                         0x42ea
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                         0x45ea
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                         0x48ea
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                         0x4bea
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                         0x4eea
++#define mmDP_MSA_V_TIMING_OVERRIDE2                                             0x1ceb
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                         0x1ceb
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                         0x1feb
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                         0x42eb
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                         0x45eb
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                         0x48eb
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                         0x4beb
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                         0x4eeb
++#define mmDP_SEC_CNTL                                                           0x1ca0
++#define mmDP0_DP_SEC_CNTL                                                       0x1ca0
++#define mmDP1_DP_SEC_CNTL                                                       0x1fa0
++#define mmDP2_DP_SEC_CNTL                                                       0x42a0
++#define mmDP3_DP_SEC_CNTL                                                       0x45a0
++#define mmDP4_DP_SEC_CNTL                                                       0x48a0
++#define mmDP5_DP_SEC_CNTL                                                       0x4ba0
++#define mmDP6_DP_SEC_CNTL                                                       0x4ea0
++#define mmDP_SEC_CNTL1                                                          0x1cab
++#define mmDP0_DP_SEC_CNTL1                                                      0x1cab
++#define mmDP1_DP_SEC_CNTL1                                                      0x1fab
++#define mmDP2_DP_SEC_CNTL1                                                      0x42ab
++#define mmDP3_DP_SEC_CNTL1                                                      0x45ab
++#define mmDP4_DP_SEC_CNTL1                                                      0x48ab
++#define mmDP5_DP_SEC_CNTL1                                                      0x4bab
++#define mmDP6_DP_SEC_CNTL1                                                      0x4eab
++#define mmDP_SEC_FRAMING1                                                       0x1ca1
++#define mmDP0_DP_SEC_FRAMING1                                                   0x1ca1
++#define mmDP1_DP_SEC_FRAMING1                                                   0x1fa1
++#define mmDP2_DP_SEC_FRAMING1                                                   0x42a1
++#define mmDP3_DP_SEC_FRAMING1                                                   0x45a1
++#define mmDP4_DP_SEC_FRAMING1                                                   0x48a1
++#define mmDP5_DP_SEC_FRAMING1                                                   0x4ba1
++#define mmDP6_DP_SEC_FRAMING1                                                   0x4ea1
++#define mmDP_SEC_FRAMING2                                                       0x1ca2
++#define mmDP0_DP_SEC_FRAMING2                                                   0x1ca2
++#define mmDP1_DP_SEC_FRAMING2                                                   0x1fa2
++#define mmDP2_DP_SEC_FRAMING2                                                   0x42a2
++#define mmDP3_DP_SEC_FRAMING2                                                   0x45a2
++#define mmDP4_DP_SEC_FRAMING2                                                   0x48a2
++#define mmDP5_DP_SEC_FRAMING2                                                   0x4ba2
++#define mmDP6_DP_SEC_FRAMING2                                                   0x4ea2
++#define mmDP_SEC_FRAMING3                                                       0x1ca3
++#define mmDP0_DP_SEC_FRAMING3                                                   0x1ca3
++#define mmDP1_DP_SEC_FRAMING3                                                   0x1fa3
++#define mmDP2_DP_SEC_FRAMING3                                                   0x42a3
++#define mmDP3_DP_SEC_FRAMING3                                                   0x45a3
++#define mmDP4_DP_SEC_FRAMING3                                                   0x48a3
++#define mmDP5_DP_SEC_FRAMING3                                                   0x4ba3
++#define mmDP6_DP_SEC_FRAMING3                                                   0x4ea3
++#define mmDP_SEC_FRAMING4                                                       0x1ca4
++#define mmDP0_DP_SEC_FRAMING4                                                   0x1ca4
++#define mmDP1_DP_SEC_FRAMING4                                                   0x1fa4
++#define mmDP2_DP_SEC_FRAMING4                                                   0x42a4
++#define mmDP3_DP_SEC_FRAMING4                                                   0x45a4
++#define mmDP4_DP_SEC_FRAMING4                                                   0x48a4
++#define mmDP5_DP_SEC_FRAMING4                                                   0x4ba4
++#define mmDP6_DP_SEC_FRAMING4                                                   0x4ea4
++#define mmDP_SEC_AUD_N                                                          0x1ca5
++#define mmDP0_DP_SEC_AUD_N                                                      0x1ca5
++#define mmDP1_DP_SEC_AUD_N                                                      0x1fa5
++#define mmDP2_DP_SEC_AUD_N                                                      0x42a5
++#define mmDP3_DP_SEC_AUD_N                                                      0x45a5
++#define mmDP4_DP_SEC_AUD_N                                                      0x48a5
++#define mmDP5_DP_SEC_AUD_N                                                      0x4ba5
++#define mmDP6_DP_SEC_AUD_N                                                      0x4ea5
++#define mmDP_SEC_AUD_N_READBACK                                                 0x1ca6
++#define mmDP0_DP_SEC_AUD_N_READBACK                                             0x1ca6
++#define mmDP1_DP_SEC_AUD_N_READBACK                                             0x1fa6
++#define mmDP2_DP_SEC_AUD_N_READBACK                                             0x42a6
++#define mmDP3_DP_SEC_AUD_N_READBACK                                             0x45a6
++#define mmDP4_DP_SEC_AUD_N_READBACK                                             0x48a6
++#define mmDP5_DP_SEC_AUD_N_READBACK                                             0x4ba6
++#define mmDP6_DP_SEC_AUD_N_READBACK                                             0x4ea6
++#define mmDP_SEC_AUD_M                                                          0x1ca7
++#define mmDP0_DP_SEC_AUD_M                                                      0x1ca7
++#define mmDP1_DP_SEC_AUD_M                                                      0x1fa7
++#define mmDP2_DP_SEC_AUD_M                                                      0x42a7
++#define mmDP3_DP_SEC_AUD_M                                                      0x45a7
++#define mmDP4_DP_SEC_AUD_M                                                      0x48a7
++#define mmDP5_DP_SEC_AUD_M                                                      0x4ba7
++#define mmDP6_DP_SEC_AUD_M                                                      0x4ea7
++#define mmDP_SEC_AUD_M_READBACK                                                 0x1ca8
++#define mmDP0_DP_SEC_AUD_M_READBACK                                             0x1ca8
++#define mmDP1_DP_SEC_AUD_M_READBACK                                             0x1fa8
++#define mmDP2_DP_SEC_AUD_M_READBACK                                             0x42a8
++#define mmDP3_DP_SEC_AUD_M_READBACK                                             0x45a8
++#define mmDP4_DP_SEC_AUD_M_READBACK                                             0x48a8
++#define mmDP5_DP_SEC_AUD_M_READBACK                                             0x4ba8
++#define mmDP6_DP_SEC_AUD_M_READBACK                                             0x4ea8
++#define mmDP_SEC_TIMESTAMP                                                      0x1ca9
++#define mmDP0_DP_SEC_TIMESTAMP                                                  0x1ca9
++#define mmDP1_DP_SEC_TIMESTAMP                                                  0x1fa9
++#define mmDP2_DP_SEC_TIMESTAMP                                                  0x42a9
++#define mmDP3_DP_SEC_TIMESTAMP                                                  0x45a9
++#define mmDP4_DP_SEC_TIMESTAMP                                                  0x48a9
++#define mmDP5_DP_SEC_TIMESTAMP                                                  0x4ba9
++#define mmDP6_DP_SEC_TIMESTAMP                                                  0x4ea9
++#define mmDP_SEC_PACKET_CNTL                                                    0x1caa
++#define mmDP0_DP_SEC_PACKET_CNTL                                                0x1caa
++#define mmDP1_DP_SEC_PACKET_CNTL                                                0x1faa
++#define mmDP2_DP_SEC_PACKET_CNTL                                                0x42aa
++#define mmDP3_DP_SEC_PACKET_CNTL                                                0x45aa
++#define mmDP4_DP_SEC_PACKET_CNTL                                                0x48aa
++#define mmDP5_DP_SEC_PACKET_CNTL                                                0x4baa
++#define mmDP6_DP_SEC_PACKET_CNTL                                                0x4eaa
++#define mmDP_MSE_RATE_CNTL                                                      0x1ce1
++#define mmDP0_DP_MSE_RATE_CNTL                                                  0x1ce1
++#define mmDP1_DP_MSE_RATE_CNTL                                                  0x1fe1
++#define mmDP2_DP_MSE_RATE_CNTL                                                  0x42e1
++#define mmDP3_DP_MSE_RATE_CNTL                                                  0x45e1
++#define mmDP4_DP_MSE_RATE_CNTL                                                  0x48e1
++#define mmDP5_DP_MSE_RATE_CNTL                                                  0x4be1
++#define mmDP6_DP_MSE_RATE_CNTL                                                  0x4ee1
++#define mmDP_MSE_RATE_UPDATE                                                    0x1ce3
++#define mmDP0_DP_MSE_RATE_UPDATE                                                0x1ce3
++#define mmDP1_DP_MSE_RATE_UPDATE                                                0x1fe3
++#define mmDP2_DP_MSE_RATE_UPDATE                                                0x42e3
++#define mmDP3_DP_MSE_RATE_UPDATE                                                0x45e3
++#define mmDP4_DP_MSE_RATE_UPDATE                                                0x48e3
++#define mmDP5_DP_MSE_RATE_UPDATE                                                0x4be3
++#define mmDP6_DP_MSE_RATE_UPDATE                                                0x4ee3
++#define mmDP_MSE_SAT0                                                           0x1ce4
++#define mmDP0_DP_MSE_SAT0                                                       0x1ce4
++#define mmDP1_DP_MSE_SAT0                                                       0x1fe4
++#define mmDP2_DP_MSE_SAT0                                                       0x42e4
++#define mmDP3_DP_MSE_SAT0                                                       0x45e4
++#define mmDP4_DP_MSE_SAT0                                                       0x48e4
++#define mmDP5_DP_MSE_SAT0                                                       0x4be4
++#define mmDP6_DP_MSE_SAT0                                                       0x4ee4
++#define mmDP_MSE_SAT1                                                           0x1ce5
++#define mmDP0_DP_MSE_SAT1                                                       0x1ce5
++#define mmDP1_DP_MSE_SAT1                                                       0x1fe5
++#define mmDP2_DP_MSE_SAT1                                                       0x42e5
++#define mmDP3_DP_MSE_SAT1                                                       0x45e5
++#define mmDP4_DP_MSE_SAT1                                                       0x48e5
++#define mmDP5_DP_MSE_SAT1                                                       0x4be5
++#define mmDP6_DP_MSE_SAT1                                                       0x4ee5
++#define mmDP_MSE_SAT2                                                           0x1ce6
++#define mmDP0_DP_MSE_SAT2                                                       0x1ce6
++#define mmDP1_DP_MSE_SAT2                                                       0x1fe6
++#define mmDP2_DP_MSE_SAT2                                                       0x42e6
++#define mmDP3_DP_MSE_SAT2                                                       0x45e6
++#define mmDP4_DP_MSE_SAT2                                                       0x48e6
++#define mmDP5_DP_MSE_SAT2                                                       0x4be6
++#define mmDP6_DP_MSE_SAT2                                                       0x4ee6
++#define mmDP_MSE_SAT_UPDATE                                                     0x1ce7
++#define mmDP0_DP_MSE_SAT_UPDATE                                                 0x1ce7
++#define mmDP1_DP_MSE_SAT_UPDATE                                                 0x1fe7
++#define mmDP2_DP_MSE_SAT_UPDATE                                                 0x42e7
++#define mmDP3_DP_MSE_SAT_UPDATE                                                 0x45e7
++#define mmDP4_DP_MSE_SAT_UPDATE                                                 0x48e7
++#define mmDP5_DP_MSE_SAT_UPDATE                                                 0x4be7
++#define mmDP6_DP_MSE_SAT_UPDATE                                                 0x4ee7
++#define mmDP_MSE_LINK_TIMING                                                    0x1ce8
++#define mmDP0_DP_MSE_LINK_TIMING                                                0x1ce8
++#define mmDP1_DP_MSE_LINK_TIMING                                                0x1fe8
++#define mmDP2_DP_MSE_LINK_TIMING                                                0x42e8
++#define mmDP3_DP_MSE_LINK_TIMING                                                0x45e8
++#define mmDP4_DP_MSE_LINK_TIMING                                                0x48e8
++#define mmDP5_DP_MSE_LINK_TIMING                                                0x4be8
++#define mmDP6_DP_MSE_LINK_TIMING                                                0x4ee8
++#define mmDP_MSE_MISC_CNTL                                                      0x1cdb
++#define mmDP0_DP_MSE_MISC_CNTL                                                  0x1cdb
++#define mmDP1_DP_MSE_MISC_CNTL                                                  0x1fdb
++#define mmDP2_DP_MSE_MISC_CNTL                                                  0x42db
++#define mmDP3_DP_MSE_MISC_CNTL                                                  0x45db
++#define mmDP4_DP_MSE_MISC_CNTL                                                  0x48db
++#define mmDP5_DP_MSE_MISC_CNTL                                                  0x4bdb
++#define mmDP6_DP_MSE_MISC_CNTL                                                  0x4edb
++#define mmDP_TEST_DEBUG_INDEX                                                   0x1cfc
++#define mmDP0_DP_TEST_DEBUG_INDEX                                               0x1cfc
++#define mmDP1_DP_TEST_DEBUG_INDEX                                               0x1ffc
++#define mmDP2_DP_TEST_DEBUG_INDEX                                               0x42fc
++#define mmDP3_DP_TEST_DEBUG_INDEX                                               0x45fc
++#define mmDP4_DP_TEST_DEBUG_INDEX                                               0x48fc
++#define mmDP5_DP_TEST_DEBUG_INDEX                                               0x4bfc
++#define mmDP6_DP_TEST_DEBUG_INDEX                                               0x4efc
++#define mmDP_TEST_DEBUG_DATA                                                    0x1cfd
++#define mmDP0_DP_TEST_DEBUG_DATA                                                0x1cfd
++#define mmDP1_DP_TEST_DEBUG_DATA                                                0x1ffd
++#define mmDP2_DP_TEST_DEBUG_DATA                                                0x42fd
++#define mmDP3_DP_TEST_DEBUG_DATA                                                0x45fd
++#define mmDP4_DP_TEST_DEBUG_DATA                                                0x48fd
++#define mmDP5_DP_TEST_DEBUG_DATA                                                0x4bfd
++#define mmDP6_DP_TEST_DEBUG_DATA                                                0x4efd
++#define mmAUX_CONTROL                                                           0x1880
++#define mmDP_AUX0_AUX_CONTROL                                                   0x1880
++#define mmDP_AUX1_AUX_CONTROL                                                   0x1894
++#define mmDP_AUX2_AUX_CONTROL                                                   0x18a8
++#define mmDP_AUX3_AUX_CONTROL                                                   0x18c0
++#define mmDP_AUX4_AUX_CONTROL                                                   0x18d4
++#define mmDP_AUX5_AUX_CONTROL                                                   0x18e8
++#define mmAUX_SW_CONTROL                                                        0x1881
++#define mmDP_AUX0_AUX_SW_CONTROL                                                0x1881
++#define mmDP_AUX1_AUX_SW_CONTROL                                                0x1895
++#define mmDP_AUX2_AUX_SW_CONTROL                                                0x18a9
++#define mmDP_AUX3_AUX_SW_CONTROL                                                0x18c1
++#define mmDP_AUX4_AUX_SW_CONTROL                                                0x18d5
++#define mmDP_AUX5_AUX_SW_CONTROL                                                0x18e9
++#define mmAUX_ARB_CONTROL                                                       0x1882
++#define mmDP_AUX0_AUX_ARB_CONTROL                                               0x1882
++#define mmDP_AUX1_AUX_ARB_CONTROL                                               0x1896
++#define mmDP_AUX2_AUX_ARB_CONTROL                                               0x18aa
++#define mmDP_AUX3_AUX_ARB_CONTROL                                               0x18c2
++#define mmDP_AUX4_AUX_ARB_CONTROL                                               0x18d6
++#define mmDP_AUX5_AUX_ARB_CONTROL                                               0x18ea
++#define mmAUX_INTERRUPT_CONTROL                                                 0x1883
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                         0x1883
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                         0x1897
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                         0x18ab
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                         0x18c3
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                         0x18d7
++#define mmDP_AUX5_AUX_INTERRUPT_CONTROL                                         0x18eb
++#define mmAUX_SW_STATUS                                                         0x1884
++#define mmDP_AUX0_AUX_SW_STATUS                                                 0x1884
++#define mmDP_AUX1_AUX_SW_STATUS                                                 0x1898
++#define mmDP_AUX2_AUX_SW_STATUS                                                 0x18ac
++#define mmDP_AUX3_AUX_SW_STATUS                                                 0x18c4
++#define mmDP_AUX4_AUX_SW_STATUS                                                 0x18d8
++#define mmDP_AUX5_AUX_SW_STATUS                                                 0x18ec
++#define mmAUX_LS_STATUS                                                         0x1885
++#define mmDP_AUX0_AUX_LS_STATUS                                                 0x1885
++#define mmDP_AUX1_AUX_LS_STATUS                                                 0x1899
++#define mmDP_AUX2_AUX_LS_STATUS                                                 0x18ad
++#define mmDP_AUX3_AUX_LS_STATUS                                                 0x18c5
++#define mmDP_AUX4_AUX_LS_STATUS                                                 0x18d9
++#define mmDP_AUX5_AUX_LS_STATUS                                                 0x18ed
++#define mmAUX_SW_DATA                                                           0x1886
++#define mmDP_AUX0_AUX_SW_DATA                                                   0x1886
++#define mmDP_AUX1_AUX_SW_DATA                                                   0x189a
++#define mmDP_AUX2_AUX_SW_DATA                                                   0x18ae
++#define mmDP_AUX3_AUX_SW_DATA                                                   0x18c6
++#define mmDP_AUX4_AUX_SW_DATA                                                   0x18da
++#define mmDP_AUX5_AUX_SW_DATA                                                   0x18ee
++#define mmAUX_LS_DATA                                                           0x1887
++#define mmDP_AUX0_AUX_LS_DATA                                                   0x1887
++#define mmDP_AUX1_AUX_LS_DATA                                                   0x189b
++#define mmDP_AUX2_AUX_LS_DATA                                                   0x18af
++#define mmDP_AUX3_AUX_LS_DATA                                                   0x18c7
++#define mmDP_AUX4_AUX_LS_DATA                                                   0x18db
++#define mmDP_AUX5_AUX_LS_DATA                                                   0x18ef
++#define mmAUX_DPHY_TX_REF_CONTROL                                               0x1888
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                       0x1888
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                       0x189c
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                       0x18b0
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                       0x18c8
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                       0x18dc
++#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                       0x18f0
++#define mmAUX_DPHY_TX_CONTROL                                                   0x1889
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                           0x1889
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                           0x189d
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                           0x18b1
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                           0x18c9
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                           0x18dd
++#define mmDP_AUX5_AUX_DPHY_TX_CONTROL                                           0x18f1
++#define mmAUX_DPHY_RX_CONTROL0                                                  0x188a
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                          0x188a
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                          0x189e
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                          0x18b2
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                          0x18ca
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                          0x18de
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                          0x18f2
++#define mmAUX_DPHY_RX_CONTROL1                                                  0x188b
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                          0x188b
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                          0x189f
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                          0x18b3
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                          0x18cb
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                          0x18df
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                          0x18f3
++#define mmAUX_DPHY_TX_STATUS                                                    0x188c
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                            0x188c
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                            0x18a0
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                            0x18b4
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                            0x18cc
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS                                            0x18e0
++#define mmDP_AUX5_AUX_DPHY_TX_STATUS                                            0x18f4
++#define mmAUX_DPHY_RX_STATUS                                                    0x188d
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                            0x188d
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                            0x18a1
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                            0x18b5
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                            0x18cd
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS                                            0x18e1
++#define mmDP_AUX5_AUX_DPHY_RX_STATUS                                            0x18f5
++#define mmAUX_GTC_SYNC_CONTROL                                                  0x188e
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                          0x188e
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                          0x18a2
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                          0x18b6
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                          0x18ce
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                          0x18e2
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL                                          0x18f6
++#define mmAUX_GTC_SYNC_ERROR_CONTROL                                            0x188f
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                    0x188f
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18a3
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18b7
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18cf
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18e3
++#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                    0x18f7
++#define mmAUX_GTC_SYNC_CONTROLLER_STATUS                                        0x1890
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x1890
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18a4
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18b8
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18d0
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18e4
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x18f8
++#define mmAUX_GTC_SYNC_STATUS                                                   0x1891
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                           0x1891
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                           0x18a5
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                           0x18b9
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                           0x18d1
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                           0x18e5
++#define mmDP_AUX5_AUX_GTC_SYNC_STATUS                                           0x18f9
++#define mmAUX_GTC_SYNC_DATA                                                     0x1892
++#define mmDP_AUX0_AUX_GTC_SYNC_DATA                                             0x1892
++#define mmDP_AUX1_AUX_GTC_SYNC_DATA                                             0x18a6
++#define mmDP_AUX2_AUX_GTC_SYNC_DATA                                             0x18ba
++#define mmDP_AUX3_AUX_GTC_SYNC_DATA                                             0x18d2
++#define mmDP_AUX4_AUX_GTC_SYNC_DATA                                             0x18e6
++#define mmDP_AUX5_AUX_GTC_SYNC_DATA                                             0x18fa
++#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                                    0x1893
++#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x1893
++#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18a7
++#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18bb
++#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18d3
++#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18e7
++#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x18fb
++#define mmDVO_ENABLE                                                            0x1858
++#define mmDVO_SOURCE_SELECT                                                     0x1859
++#define mmDVO_OUTPUT                                                            0x185a
++#define mmDVO_CONTROL                                                           0x185b
++#define mmDVO_CRC_EN                                                            0x185c
++#define mmDVO_CRC2_SIG_MASK                                                     0x185d
++#define mmDVO_CRC2_SIG_RESULT                                                   0x185e
++#define mmDVO_FIFO_ERROR_STATUS                                                 0x185f
++#define mmFBC_CNTL                                                              0x16d0
++#define mmFBC_IDLE_MASK                                                         0x16d1
++#define mmFBC_IDLE_FORCE_CLEAR_MASK                                             0x16d2
++#define mmFBC_START_STOP_DELAY                                                  0x16d3
++#define mmFBC_COMP_CNTL                                                         0x16d4
++#define mmFBC_COMP_MODE                                                         0x16d5
++#define mmFBC_DEBUG0                                                            0x16d6
++#define mmFBC_DEBUG1                                                            0x16d7
++#define mmFBC_DEBUG2                                                            0x16d8
++#define mmFBC_IND_LUT0                                                          0x16d9
++#define mmFBC_IND_LUT1                                                          0x16da
++#define mmFBC_IND_LUT2                                                          0x16db
++#define mmFBC_IND_LUT3                                                          0x16dc
++#define mmFBC_IND_LUT4                                                          0x16dd
++#define mmFBC_IND_LUT5                                                          0x16de
++#define mmFBC_IND_LUT6                                                          0x16df
++#define mmFBC_IND_LUT7                                                          0x16e0
++#define mmFBC_IND_LUT8                                                          0x16e1
++#define mmFBC_IND_LUT9                                                          0x16e2
++#define mmFBC_IND_LUT10                                                         0x16e3
++#define mmFBC_IND_LUT11                                                         0x16e4
++#define mmFBC_IND_LUT12                                                         0x16e5
++#define mmFBC_IND_LUT13                                                         0x16e6
++#define mmFBC_IND_LUT14                                                         0x16e7
++#define mmFBC_IND_LUT15                                                         0x16e8
++#define mmFBC_CSM_REGION_OFFSET_01                                              0x16e9
++#define mmFBC_CSM_REGION_OFFSET_23                                              0x16ea
++#define mmFBC_CLIENT_REGION_MASK                                                0x16eb
++#define mmFBC_DEBUG_COMP                                                        0x16ec
++#define mmFBC_DEBUG_CSR                                                         0x16ed
++#define mmFBC_DEBUG_CSR_RDATA                                                   0x16ee
++#define mmFBC_DEBUG_CSR_WDATA                                                   0x16ef
++#define mmFBC_DEBUG_CSR_RDATA_HI                                                0x16f6
++#define mmFBC_DEBUG_CSR_WDATA_HI                                                0x16f7
++#define mmFBC_MISC                                                              0x16f0
++#define mmFBC_STATUS                                                            0x16f1
++#define mmFBC_TEST_DEBUG_INDEX                                                  0x16f4
++#define mmFBC_TEST_DEBUG_DATA                                                   0x16f5
++#define mmFMT_CLAMP_COMPONENT_R                                                 0x1be8
++#define mmFMT0_FMT_CLAMP_COMPONENT_R                                            0x1be8
++#define mmFMT1_FMT_CLAMP_COMPONENT_R                                            0x1ee8
++#define mmFMT2_FMT_CLAMP_COMPONENT_R                                            0x41e8
++#define mmFMT3_FMT_CLAMP_COMPONENT_R                                            0x44e8
++#define mmFMT4_FMT_CLAMP_COMPONENT_R                                            0x47e8
++#define mmFMT5_FMT_CLAMP_COMPONENT_R                                            0x4ae8
++#define mmFMT_CLAMP_COMPONENT_G                                                 0x1be9
++#define mmFMT0_FMT_CLAMP_COMPONENT_G                                            0x1be9
++#define mmFMT1_FMT_CLAMP_COMPONENT_G                                            0x1ee9
++#define mmFMT2_FMT_CLAMP_COMPONENT_G                                            0x41e9
++#define mmFMT3_FMT_CLAMP_COMPONENT_G                                            0x44e9
++#define mmFMT4_FMT_CLAMP_COMPONENT_G                                            0x47e9
++#define mmFMT5_FMT_CLAMP_COMPONENT_G                                            0x4ae9
++#define mmFMT_CLAMP_COMPONENT_B                                                 0x1bea
++#define mmFMT0_FMT_CLAMP_COMPONENT_B                                            0x1bea
++#define mmFMT1_FMT_CLAMP_COMPONENT_B                                            0x1eea
++#define mmFMT2_FMT_CLAMP_COMPONENT_B                                            0x41ea
++#define mmFMT3_FMT_CLAMP_COMPONENT_B                                            0x44ea
++#define mmFMT4_FMT_CLAMP_COMPONENT_B                                            0x47ea
++#define mmFMT5_FMT_CLAMP_COMPONENT_B                                            0x4aea
++#define mmFMT_DYNAMIC_EXP_CNTL                                                  0x1bed
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                             0x1bed
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                             0x1eed
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                             0x41ed
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                             0x44ed
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                             0x47ed
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                             0x4aed
++#define mmFMT_CONTROL                                                           0x1bee
++#define mmFMT0_FMT_CONTROL                                                      0x1bee
++#define mmFMT1_FMT_CONTROL                                                      0x1eee
++#define mmFMT2_FMT_CONTROL                                                      0x41ee
++#define mmFMT3_FMT_CONTROL                                                      0x44ee
++#define mmFMT4_FMT_CONTROL                                                      0x47ee
++#define mmFMT5_FMT_CONTROL                                                      0x4aee
++#define mmFMT_FORCE_OUTPUT_CNTL                                                 0x1bef
++#define mmFMT0_FMT_FORCE_OUTPUT_CNTL                                            0x1bef
++#define mmFMT1_FMT_FORCE_OUTPUT_CNTL                                            0x1eef
++#define mmFMT2_FMT_FORCE_OUTPUT_CNTL                                            0x41ef
++#define mmFMT3_FMT_FORCE_OUTPUT_CNTL                                            0x44ef
++#define mmFMT4_FMT_FORCE_OUTPUT_CNTL                                            0x47ef
++#define mmFMT5_FMT_FORCE_OUTPUT_CNTL                                            0x4aef
++#define mmFMT_FORCE_DATA_0_1                                                    0x1bf0
++#define mmFMT0_FMT_FORCE_DATA_0_1                                               0x1bf0
++#define mmFMT1_FMT_FORCE_DATA_0_1                                               0x1ef0
++#define mmFMT2_FMT_FORCE_DATA_0_1                                               0x41f0
++#define mmFMT3_FMT_FORCE_DATA_0_1                                               0x44f0
++#define mmFMT4_FMT_FORCE_DATA_0_1                                               0x47f0
++#define mmFMT5_FMT_FORCE_DATA_0_1                                               0x4af0
++#define mmFMT_FORCE_DATA_2_3                                                    0x1bf1
++#define mmFMT0_FMT_FORCE_DATA_2_3                                               0x1bf1
++#define mmFMT1_FMT_FORCE_DATA_2_3                                               0x1ef1
++#define mmFMT2_FMT_FORCE_DATA_2_3                                               0x41f1
++#define mmFMT3_FMT_FORCE_DATA_2_3                                               0x44f1
++#define mmFMT4_FMT_FORCE_DATA_2_3                                               0x47f1
++#define mmFMT5_FMT_FORCE_DATA_2_3                                               0x4af1
++#define mmFMT_BIT_DEPTH_CONTROL                                                 0x1bf2
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                            0x1bf2
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                            0x1ef2
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                            0x41f2
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                            0x44f2
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL                                            0x47f2
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL                                            0x4af2
++#define mmFMT_DITHER_RAND_R_SEED                                                0x1bf3
++#define mmFMT0_FMT_DITHER_RAND_R_SEED                                           0x1bf3
++#define mmFMT1_FMT_DITHER_RAND_R_SEED                                           0x1ef3
++#define mmFMT2_FMT_DITHER_RAND_R_SEED                                           0x41f3
++#define mmFMT3_FMT_DITHER_RAND_R_SEED                                           0x44f3
++#define mmFMT4_FMT_DITHER_RAND_R_SEED                                           0x47f3
++#define mmFMT5_FMT_DITHER_RAND_R_SEED                                           0x4af3
++#define mmFMT_DITHER_RAND_G_SEED                                                0x1bf4
++#define mmFMT0_FMT_DITHER_RAND_G_SEED                                           0x1bf4
++#define mmFMT1_FMT_DITHER_RAND_G_SEED                                           0x1ef4
++#define mmFMT2_FMT_DITHER_RAND_G_SEED                                           0x41f4
++#define mmFMT3_FMT_DITHER_RAND_G_SEED                                           0x44f4
++#define mmFMT4_FMT_DITHER_RAND_G_SEED                                           0x47f4
++#define mmFMT5_FMT_DITHER_RAND_G_SEED                                           0x4af4
++#define mmFMT_DITHER_RAND_B_SEED                                                0x1bf5
++#define mmFMT0_FMT_DITHER_RAND_B_SEED                                           0x1bf5
++#define mmFMT1_FMT_DITHER_RAND_B_SEED                                           0x1ef5
++#define mmFMT2_FMT_DITHER_RAND_B_SEED                                           0x41f5
++#define mmFMT3_FMT_DITHER_RAND_B_SEED                                           0x44f5
++#define mmFMT4_FMT_DITHER_RAND_B_SEED                                           0x47f5
++#define mmFMT5_FMT_DITHER_RAND_B_SEED                                           0x4af5
++#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL                                   0x1bf6
++#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1bf6
++#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1ef6
++#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x41f6
++#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x44f6
++#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x47f6
++#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x4af6
++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                     0x1bf7
++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1bf7
++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1ef7
++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x41f7
++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x44f7
++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x47f7
++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x4af7
++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                     0x1bf8
++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1bf8
++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1ef8
++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x41f8
++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x44f8
++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x47f8
++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x4af8
++#define mmFMT_CLAMP_CNTL                                                        0x1bf9
++#define mmFMT0_FMT_CLAMP_CNTL                                                   0x1bf9
++#define mmFMT1_FMT_CLAMP_CNTL                                                   0x1ef9
++#define mmFMT2_FMT_CLAMP_CNTL                                                   0x41f9
++#define mmFMT3_FMT_CLAMP_CNTL                                                   0x44f9
++#define mmFMT4_FMT_CLAMP_CNTL                                                   0x47f9
++#define mmFMT5_FMT_CLAMP_CNTL                                                   0x4af9
++#define mmFMT_CRC_CNTL                                                          0x1bfa
++#define mmFMT0_FMT_CRC_CNTL                                                     0x1bfa
++#define mmFMT1_FMT_CRC_CNTL                                                     0x1efa
++#define mmFMT2_FMT_CRC_CNTL                                                     0x41fa
++#define mmFMT3_FMT_CRC_CNTL                                                     0x44fa
++#define mmFMT4_FMT_CRC_CNTL                                                     0x47fa
++#define mmFMT5_FMT_CRC_CNTL                                                     0x4afa
++#define mmFMT_CRC_SIG_RED_GREEN_MASK                                            0x1bfb
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1bfb
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1efb
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK                                       0x41fb
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                                       0x44fb
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                                       0x47fb
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                                       0x4afb
++#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK                                         0x1bfc
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1bfc
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1efc
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x41fc
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x44fc
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x47fc
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x4afc
++#define mmFMT_CRC_SIG_RED_GREEN                                                 0x1bfd
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN                                            0x1bfd
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN                                            0x1efd
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN                                            0x41fd
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN                                            0x44fd
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN                                            0x47fd
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN                                            0x4afd
++#define mmFMT_CRC_SIG_BLUE_CONTROL                                              0x1bfe
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL                                         0x1bfe
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL                                         0x1efe
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL                                         0x41fe
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                                         0x44fe
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL                                         0x47fe
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                                         0x4afe
++#define mmFMT_DEBUG_CNTL                                                        0x1bff
++#define mmFMT0_FMT_DEBUG_CNTL                                                   0x1bff
++#define mmFMT1_FMT_DEBUG_CNTL                                                   0x1eff
++#define mmFMT2_FMT_DEBUG_CNTL                                                   0x41ff
++#define mmFMT3_FMT_DEBUG_CNTL                                                   0x44ff
++#define mmFMT4_FMT_DEBUG_CNTL                                                   0x47ff
++#define mmFMT5_FMT_DEBUG_CNTL                                                   0x4aff
++#define mmFMT_TEST_DEBUG_INDEX                                                  0x1beb
++#define mmFMT0_FMT_TEST_DEBUG_INDEX                                             0x1beb
++#define mmFMT1_FMT_TEST_DEBUG_INDEX                                             0x1eeb
++#define mmFMT2_FMT_TEST_DEBUG_INDEX                                             0x41eb
++#define mmFMT3_FMT_TEST_DEBUG_INDEX                                             0x44eb
++#define mmFMT4_FMT_TEST_DEBUG_INDEX                                             0x47eb
++#define mmFMT5_FMT_TEST_DEBUG_INDEX                                             0x4aeb
++#define mmFMT_TEST_DEBUG_DATA                                                   0x1bec
++#define mmFMT0_FMT_TEST_DEBUG_DATA                                              0x1bec
++#define mmFMT1_FMT_TEST_DEBUG_DATA                                              0x1eec
++#define mmFMT2_FMT_TEST_DEBUG_DATA                                              0x41ec
++#define mmFMT3_FMT_TEST_DEBUG_DATA                                              0x44ec
++#define mmFMT4_FMT_TEST_DEBUG_DATA                                              0x47ec
++#define mmFMT5_FMT_TEST_DEBUG_DATA                                              0x4aec
++#define ixFMT_DEBUG0                                                            0x1
++#define ixFMT_DEBUG1                                                            0x2
++#define ixFMT_DEBUG2                                                            0x3
++#define ixFMT_DEBUG_ID                                                          0x0
++#define mmLB_DATA_FORMAT                                                        0x1ac0
++#define mmLB0_LB_DATA_FORMAT                                                    0x1ac0
++#define mmLB1_LB_DATA_FORMAT                                                    0x1dc0
++#define mmLB2_LB_DATA_FORMAT                                                    0x40c0
++#define mmLB3_LB_DATA_FORMAT                                                    0x43c0
++#define mmLB4_LB_DATA_FORMAT                                                    0x46c0
++#define mmLB5_LB_DATA_FORMAT                                                    0x49c0
++#define mmLB_MEMORY_CTRL                                                        0x1ac1
++#define mmLB0_LB_MEMORY_CTRL                                                    0x1ac1
++#define mmLB1_LB_MEMORY_CTRL                                                    0x1dc1
++#define mmLB2_LB_MEMORY_CTRL                                                    0x40c1
++#define mmLB3_LB_MEMORY_CTRL                                                    0x43c1
++#define mmLB4_LB_MEMORY_CTRL                                                    0x46c1
++#define mmLB5_LB_MEMORY_CTRL                                                    0x49c1
++#define mmLB_MEMORY_SIZE_STATUS                                                 0x1ac2
++#define mmLB0_LB_MEMORY_SIZE_STATUS                                             0x1ac2
++#define mmLB1_LB_MEMORY_SIZE_STATUS                                             0x1dc2
++#define mmLB2_LB_MEMORY_SIZE_STATUS                                             0x40c2
++#define mmLB3_LB_MEMORY_SIZE_STATUS                                             0x43c2
++#define mmLB4_LB_MEMORY_SIZE_STATUS                                             0x46c2
++#define mmLB5_LB_MEMORY_SIZE_STATUS                                             0x49c2
++#define mmLB_DESKTOP_HEIGHT                                                     0x1ac3
++#define mmLB0_LB_DESKTOP_HEIGHT                                                 0x1ac3
++#define mmLB1_LB_DESKTOP_HEIGHT                                                 0x1dc3
++#define mmLB2_LB_DESKTOP_HEIGHT                                                 0x40c3
++#define mmLB3_LB_DESKTOP_HEIGHT                                                 0x43c3
++#define mmLB4_LB_DESKTOP_HEIGHT                                                 0x46c3
++#define mmLB5_LB_DESKTOP_HEIGHT                                                 0x49c3
++#define mmLB_VLINE_START_END                                                    0x1ac4
++#define mmLB0_LB_VLINE_START_END                                                0x1ac4
++#define mmLB1_LB_VLINE_START_END                                                0x1dc4
++#define mmLB2_LB_VLINE_START_END                                                0x40c4
++#define mmLB3_LB_VLINE_START_END                                                0x43c4
++#define mmLB4_LB_VLINE_START_END                                                0x46c4
++#define mmLB5_LB_VLINE_START_END                                                0x49c4
++#define mmLB_VLINE2_START_END                                                   0x1ac5
++#define mmLB0_LB_VLINE2_START_END                                               0x1ac5
++#define mmLB1_LB_VLINE2_START_END                                               0x1dc5
++#define mmLB2_LB_VLINE2_START_END                                               0x40c5
++#define mmLB3_LB_VLINE2_START_END                                               0x43c5
++#define mmLB4_LB_VLINE2_START_END                                               0x46c5
++#define mmLB5_LB_VLINE2_START_END                                               0x49c5
++#define mmLB_V_COUNTER                                                          0x1ac6
++#define mmLB0_LB_V_COUNTER                                                      0x1ac6
++#define mmLB1_LB_V_COUNTER                                                      0x1dc6
++#define mmLB2_LB_V_COUNTER                                                      0x40c6
++#define mmLB3_LB_V_COUNTER                                                      0x43c6
++#define mmLB4_LB_V_COUNTER                                                      0x46c6
++#define mmLB5_LB_V_COUNTER                                                      0x49c6
++#define mmLB_SNAPSHOT_V_COUNTER                                                 0x1ac7
++#define mmLB0_LB_SNAPSHOT_V_COUNTER                                             0x1ac7
++#define mmLB1_LB_SNAPSHOT_V_COUNTER                                             0x1dc7
++#define mmLB2_LB_SNAPSHOT_V_COUNTER                                             0x40c7
++#define mmLB3_LB_SNAPSHOT_V_COUNTER                                             0x43c7
++#define mmLB4_LB_SNAPSHOT_V_COUNTER                                             0x46c7
++#define mmLB5_LB_SNAPSHOT_V_COUNTER                                             0x49c7
++#define mmLB_INTERRUPT_MASK                                                     0x1ac8
++#define mmLB0_LB_INTERRUPT_MASK                                                 0x1ac8
++#define mmLB1_LB_INTERRUPT_MASK                                                 0x1dc8
++#define mmLB2_LB_INTERRUPT_MASK                                                 0x40c8
++#define mmLB3_LB_INTERRUPT_MASK                                                 0x43c8
++#define mmLB4_LB_INTERRUPT_MASK                                                 0x46c8
++#define mmLB5_LB_INTERRUPT_MASK                                                 0x49c8
++#define mmLB_VLINE_STATUS                                                       0x1ac9
++#define mmLB0_LB_VLINE_STATUS                                                   0x1ac9
++#define mmLB1_LB_VLINE_STATUS                                                   0x1dc9
++#define mmLB2_LB_VLINE_STATUS                                                   0x40c9
++#define mmLB3_LB_VLINE_STATUS                                                   0x43c9
++#define mmLB4_LB_VLINE_STATUS                                                   0x46c9
++#define mmLB5_LB_VLINE_STATUS                                                   0x49c9
++#define mmLB_VLINE2_STATUS                                                      0x1aca
++#define mmLB0_LB_VLINE2_STATUS                                                  0x1aca
++#define mmLB1_LB_VLINE2_STATUS                                                  0x1dca
++#define mmLB2_LB_VLINE2_STATUS                                                  0x40ca
++#define mmLB3_LB_VLINE2_STATUS                                                  0x43ca
++#define mmLB4_LB_VLINE2_STATUS                                                  0x46ca
++#define mmLB5_LB_VLINE2_STATUS                                                  0x49ca
++#define mmLB_VBLANK_STATUS                                                      0x1acb
++#define mmLB0_LB_VBLANK_STATUS                                                  0x1acb
++#define mmLB1_LB_VBLANK_STATUS                                                  0x1dcb
++#define mmLB2_LB_VBLANK_STATUS                                                  0x40cb
++#define mmLB3_LB_VBLANK_STATUS                                                  0x43cb
++#define mmLB4_LB_VBLANK_STATUS                                                  0x46cb
++#define mmLB5_LB_VBLANK_STATUS                                                  0x49cb
++#define mmLB_SYNC_RESET_SEL                                                     0x1acc
++#define mmLB0_LB_SYNC_RESET_SEL                                                 0x1acc
++#define mmLB1_LB_SYNC_RESET_SEL                                                 0x1dcc
++#define mmLB2_LB_SYNC_RESET_SEL                                                 0x40cc
++#define mmLB3_LB_SYNC_RESET_SEL                                                 0x43cc
++#define mmLB4_LB_SYNC_RESET_SEL                                                 0x46cc
++#define mmLB5_LB_SYNC_RESET_SEL                                                 0x49cc
++#define mmLB_BLACK_KEYER_R_CR                                                   0x1acd
++#define mmLB0_LB_BLACK_KEYER_R_CR                                               0x1acd
++#define mmLB1_LB_BLACK_KEYER_R_CR                                               0x1dcd
++#define mmLB2_LB_BLACK_KEYER_R_CR                                               0x40cd
++#define mmLB3_LB_BLACK_KEYER_R_CR                                               0x43cd
++#define mmLB4_LB_BLACK_KEYER_R_CR                                               0x46cd
++#define mmLB5_LB_BLACK_KEYER_R_CR                                               0x49cd
++#define mmLB_BLACK_KEYER_G_Y                                                    0x1ace
++#define mmLB0_LB_BLACK_KEYER_G_Y                                                0x1ace
++#define mmLB1_LB_BLACK_KEYER_G_Y                                                0x1dce
++#define mmLB2_LB_BLACK_KEYER_G_Y                                                0x40ce
++#define mmLB3_LB_BLACK_KEYER_G_Y                                                0x43ce
++#define mmLB4_LB_BLACK_KEYER_G_Y                                                0x46ce
++#define mmLB5_LB_BLACK_KEYER_G_Y                                                0x49ce
++#define mmLB_BLACK_KEYER_B_CB                                                   0x1acf
++#define mmLB0_LB_BLACK_KEYER_B_CB                                               0x1acf
++#define mmLB1_LB_BLACK_KEYER_B_CB                                               0x1dcf
++#define mmLB2_LB_BLACK_KEYER_B_CB                                               0x40cf
++#define mmLB3_LB_BLACK_KEYER_B_CB                                               0x43cf
++#define mmLB4_LB_BLACK_KEYER_B_CB                                               0x46cf
++#define mmLB5_LB_BLACK_KEYER_B_CB                                               0x49cf
++#define mmLB_KEYER_COLOR_CTRL                                                   0x1ad0
++#define mmLB0_LB_KEYER_COLOR_CTRL                                               0x1ad0
++#define mmLB1_LB_KEYER_COLOR_CTRL                                               0x1dd0
++#define mmLB2_LB_KEYER_COLOR_CTRL                                               0x40d0
++#define mmLB3_LB_KEYER_COLOR_CTRL                                               0x43d0
++#define mmLB4_LB_KEYER_COLOR_CTRL                                               0x46d0
++#define mmLB5_LB_KEYER_COLOR_CTRL                                               0x49d0
++#define mmLB_KEYER_COLOR_R_CR                                                   0x1ad1
++#define mmLB0_LB_KEYER_COLOR_R_CR                                               0x1ad1
++#define mmLB1_LB_KEYER_COLOR_R_CR                                               0x1dd1
++#define mmLB2_LB_KEYER_COLOR_R_CR                                               0x40d1
++#define mmLB3_LB_KEYER_COLOR_R_CR                                               0x43d1
++#define mmLB4_LB_KEYER_COLOR_R_CR                                               0x46d1
++#define mmLB5_LB_KEYER_COLOR_R_CR                                               0x49d1
++#define mmLB_KEYER_COLOR_G_Y                                                    0x1ad2
++#define mmLB0_LB_KEYER_COLOR_G_Y                                                0x1ad2
++#define mmLB1_LB_KEYER_COLOR_G_Y                                                0x1dd2
++#define mmLB2_LB_KEYER_COLOR_G_Y                                                0x40d2
++#define mmLB3_LB_KEYER_COLOR_G_Y                                                0x43d2
++#define mmLB4_LB_KEYER_COLOR_G_Y                                                0x46d2
++#define mmLB5_LB_KEYER_COLOR_G_Y                                                0x49d2
++#define mmLB_KEYER_COLOR_B_CB                                                   0x1ad3
++#define mmLB0_LB_KEYER_COLOR_B_CB                                               0x1ad3
++#define mmLB1_LB_KEYER_COLOR_B_CB                                               0x1dd3
++#define mmLB2_LB_KEYER_COLOR_B_CB                                               0x40d3
++#define mmLB3_LB_KEYER_COLOR_B_CB                                               0x43d3
++#define mmLB4_LB_KEYER_COLOR_B_CB                                               0x46d3
++#define mmLB5_LB_KEYER_COLOR_B_CB                                               0x49d3
++#define mmLB_KEYER_COLOR_REP_R_CR                                               0x1ad4
++#define mmLB0_LB_KEYER_COLOR_REP_R_CR                                           0x1ad4
++#define mmLB1_LB_KEYER_COLOR_REP_R_CR                                           0x1dd4
++#define mmLB2_LB_KEYER_COLOR_REP_R_CR                                           0x40d4
++#define mmLB3_LB_KEYER_COLOR_REP_R_CR                                           0x43d4
++#define mmLB4_LB_KEYER_COLOR_REP_R_CR                                           0x46d4
++#define mmLB5_LB_KEYER_COLOR_REP_R_CR                                           0x49d4
++#define mmLB_KEYER_COLOR_REP_G_Y                                                0x1ad5
++#define mmLB0_LB_KEYER_COLOR_REP_G_Y                                            0x1ad5
++#define mmLB1_LB_KEYER_COLOR_REP_G_Y                                            0x1dd5
++#define mmLB2_LB_KEYER_COLOR_REP_G_Y                                            0x40d5
++#define mmLB3_LB_KEYER_COLOR_REP_G_Y                                            0x43d5
++#define mmLB4_LB_KEYER_COLOR_REP_G_Y                                            0x46d5
++#define mmLB5_LB_KEYER_COLOR_REP_G_Y                                            0x49d5
++#define mmLB_KEYER_COLOR_REP_B_CB                                               0x1ad6
++#define mmLB0_LB_KEYER_COLOR_REP_B_CB                                           0x1ad6
++#define mmLB1_LB_KEYER_COLOR_REP_B_CB                                           0x1dd6
++#define mmLB2_LB_KEYER_COLOR_REP_B_CB                                           0x40d6
++#define mmLB3_LB_KEYER_COLOR_REP_B_CB                                           0x43d6
++#define mmLB4_LB_KEYER_COLOR_REP_B_CB                                           0x46d6
++#define mmLB5_LB_KEYER_COLOR_REP_B_CB                                           0x49d6
++#define mmLB_BUFFER_LEVEL_STATUS                                                0x1ad7
++#define mmLB0_LB_BUFFER_LEVEL_STATUS                                            0x1ad7
++#define mmLB1_LB_BUFFER_LEVEL_STATUS                                            0x1dd7
++#define mmLB2_LB_BUFFER_LEVEL_STATUS                                            0x40d7
++#define mmLB3_LB_BUFFER_LEVEL_STATUS                                            0x43d7
++#define mmLB4_LB_BUFFER_LEVEL_STATUS                                            0x46d7
++#define mmLB5_LB_BUFFER_LEVEL_STATUS                                            0x49d7
++#define mmLB_BUFFER_URGENCY_CTRL                                                0x1ad8
++#define mmLB0_LB_BUFFER_URGENCY_CTRL                                            0x1ad8
++#define mmLB1_LB_BUFFER_URGENCY_CTRL                                            0x1dd8
++#define mmLB2_LB_BUFFER_URGENCY_CTRL                                            0x40d8
++#define mmLB3_LB_BUFFER_URGENCY_CTRL                                            0x43d8
++#define mmLB4_LB_BUFFER_URGENCY_CTRL                                            0x46d8
++#define mmLB5_LB_BUFFER_URGENCY_CTRL                                            0x49d8
++#define mmLB_BUFFER_URGENCY_STATUS                                              0x1ad9
++#define mmLB0_LB_BUFFER_URGENCY_STATUS                                          0x1ad9
++#define mmLB1_LB_BUFFER_URGENCY_STATUS                                          0x1dd9
++#define mmLB2_LB_BUFFER_URGENCY_STATUS                                          0x40d9
++#define mmLB3_LB_BUFFER_URGENCY_STATUS                                          0x43d9
++#define mmLB4_LB_BUFFER_URGENCY_STATUS                                          0x46d9
++#define mmLB5_LB_BUFFER_URGENCY_STATUS                                          0x49d9
++#define mmLB_BUFFER_STATUS                                                      0x1ada
++#define mmLB0_LB_BUFFER_STATUS                                                  0x1ada
++#define mmLB1_LB_BUFFER_STATUS                                                  0x1dda
++#define mmLB2_LB_BUFFER_STATUS                                                  0x40da
++#define mmLB3_LB_BUFFER_STATUS                                                  0x43da
++#define mmLB4_LB_BUFFER_STATUS                                                  0x46da
++#define mmLB5_LB_BUFFER_STATUS                                                  0x49da
++#define mmLB_NO_OUTSTANDING_REQ_STATUS                                          0x1adc
++#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1adc
++#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1ddc
++#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS                                      0x40dc
++#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                                      0x43dc
++#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                                      0x46dc
++#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                                      0x49dc
++#define mmMVP_AFR_FLIP_MODE                                                     0x1ae0
++#define mmLB0_MVP_AFR_FLIP_MODE                                                 0x1ae0
++#define mmLB1_MVP_AFR_FLIP_MODE                                                 0x1de0
++#define mmLB2_MVP_AFR_FLIP_MODE                                                 0x40e0
++#define mmLB3_MVP_AFR_FLIP_MODE                                                 0x43e0
++#define mmLB4_MVP_AFR_FLIP_MODE                                                 0x46e0
++#define mmLB5_MVP_AFR_FLIP_MODE                                                 0x49e0
++#define mmMVP_AFR_FLIP_FIFO_CNTL                                                0x1ae1
++#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ae1
++#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL                                            0x1de1
++#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL                                            0x40e1
++#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL                                            0x43e1
++#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL                                            0x46e1
++#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL                                            0x49e1
++#define mmMVP_FLIP_LINE_NUM_INSERT                                              0x1ae2
++#define mmLB0_MVP_FLIP_LINE_NUM_INSERT                                          0x1ae2
++#define mmLB1_MVP_FLIP_LINE_NUM_INSERT                                          0x1de2
++#define mmLB2_MVP_FLIP_LINE_NUM_INSERT                                          0x40e2
++#define mmLB3_MVP_FLIP_LINE_NUM_INSERT                                          0x43e2
++#define mmLB4_MVP_FLIP_LINE_NUM_INSERT                                          0x46e2
++#define mmLB5_MVP_FLIP_LINE_NUM_INSERT                                          0x49e2
++#define mmDC_MVP_LB_CONTROL                                                     0x1ae3
++#define mmLB0_DC_MVP_LB_CONTROL                                                 0x1ae3
++#define mmLB1_DC_MVP_LB_CONTROL                                                 0x1de3
++#define mmLB2_DC_MVP_LB_CONTROL                                                 0x40e3
++#define mmLB3_DC_MVP_LB_CONTROL                                                 0x43e3
++#define mmLB4_DC_MVP_LB_CONTROL                                                 0x46e3
++#define mmLB5_DC_MVP_LB_CONTROL                                                 0x49e3
++#define mmLB_DEBUG                                                              0x1ae4
++#define mmLB0_LB_DEBUG                                                          0x1ae4
++#define mmLB1_LB_DEBUG                                                          0x1de4
++#define mmLB2_LB_DEBUG                                                          0x40e4
++#define mmLB3_LB_DEBUG                                                          0x43e4
++#define mmLB4_LB_DEBUG                                                          0x46e4
++#define mmLB5_LB_DEBUG                                                          0x49e4
++#define mmLB_DEBUG2                                                             0x1ae5
++#define mmLB0_LB_DEBUG2                                                         0x1ae5
++#define mmLB1_LB_DEBUG2                                                         0x1de5
++#define mmLB2_LB_DEBUG2                                                         0x40e5
++#define mmLB3_LB_DEBUG2                                                         0x43e5
++#define mmLB4_LB_DEBUG2                                                         0x46e5
++#define mmLB5_LB_DEBUG2                                                         0x49e5
++#define mmLB_DEBUG3                                                             0x1ae6
++#define mmLB0_LB_DEBUG3                                                         0x1ae6
++#define mmLB1_LB_DEBUG3                                                         0x1de6
++#define mmLB2_LB_DEBUG3                                                         0x40e6
++#define mmLB3_LB_DEBUG3                                                         0x43e6
++#define mmLB4_LB_DEBUG3                                                         0x46e6
++#define mmLB5_LB_DEBUG3                                                         0x49e6
++#define mmLB_TEST_DEBUG_INDEX                                                   0x1afe
++#define mmLB0_LB_TEST_DEBUG_INDEX                                               0x1afe
++#define mmLB1_LB_TEST_DEBUG_INDEX                                               0x1dfe
++#define mmLB2_LB_TEST_DEBUG_INDEX                                               0x40fe
++#define mmLB3_LB_TEST_DEBUG_INDEX                                               0x43fe
++#define mmLB4_LB_TEST_DEBUG_INDEX                                               0x46fe
++#define mmLB5_LB_TEST_DEBUG_INDEX                                               0x49fe
++#define mmLB_TEST_DEBUG_DATA                                                    0x1aff
++#define mmLB0_LB_TEST_DEBUG_DATA                                                0x1aff
++#define mmLB1_LB_TEST_DEBUG_DATA                                                0x1dff
++#define mmLB2_LB_TEST_DEBUG_DATA                                                0x40ff
++#define mmLB3_LB_TEST_DEBUG_DATA                                                0x43ff
++#define mmLB4_LB_TEST_DEBUG_DATA                                                0x46ff
++#define mmLB5_LB_TEST_DEBUG_DATA                                                0x49ff
++#define mmMVP_CONTROL1                                                          0x1680
++#define mmMVP_CONTROL2                                                          0x1681
++#define mmMVP_FIFO_CONTROL                                                      0x1682
++#define mmMVP_FIFO_STATUS                                                       0x1683
++#define mmMVP_SLAVE_STATUS                                                      0x1684
++#define mmMVP_INBAND_CNTL_CAP                                                   0x1685
++#define mmMVP_BLACK_KEYER                                                       0x1686
++#define mmMVP_CRC_CNTL                                                          0x1687
++#define mmMVP_CRC_RESULT_BLUE_GREEN                                             0x1688
++#define mmMVP_CRC_RESULT_RED                                                    0x1689
++#define mmMVP_CONTROL3                                                          0x168a
++#define mmMVP_RECEIVE_CNT_CNTL1                                                 0x168b
++#define mmMVP_RECEIVE_CNT_CNTL2                                                 0x168c
++#define mmMVP_DEBUG                                                             0x168f
++#define mmMVP_TEST_DEBUG_INDEX                                                  0x168d
++#define mmMVP_TEST_DEBUG_DATA                                                   0x168e
++#define ixMVP_DEBUG_12                                                          0xc
++#define ixMVP_DEBUG_13                                                          0xd
++#define ixMVP_DEBUG_14                                                          0xe
++#define ixMVP_DEBUG_15                                                          0xf
++#define ixMVP_DEBUG_16                                                          0x10
++#define ixMVP_DEBUG_17                                                          0x11
++#define mmSCL_COEF_RAM_SELECT                                                   0x1b40
++#define mmSCL0_SCL_COEF_RAM_SELECT                                              0x1b40
++#define mmSCL1_SCL_COEF_RAM_SELECT                                              0x1e40
++#define mmSCL2_SCL_COEF_RAM_SELECT                                              0x4140
++#define mmSCL3_SCL_COEF_RAM_SELECT                                              0x4440
++#define mmSCL4_SCL_COEF_RAM_SELECT                                              0x4740
++#define mmSCL5_SCL_COEF_RAM_SELECT                                              0x4a40
++#define mmSCL_COEF_RAM_TAP_DATA                                                 0x1b41
++#define mmSCL0_SCL_COEF_RAM_TAP_DATA                                            0x1b41
++#define mmSCL1_SCL_COEF_RAM_TAP_DATA                                            0x1e41
++#define mmSCL2_SCL_COEF_RAM_TAP_DATA                                            0x4141
++#define mmSCL3_SCL_COEF_RAM_TAP_DATA                                            0x4441
++#define mmSCL4_SCL_COEF_RAM_TAP_DATA                                            0x4741
++#define mmSCL5_SCL_COEF_RAM_TAP_DATA                                            0x4a41
++#define mmSCL_MODE                                                              0x1b42
++#define mmSCL0_SCL_MODE                                                         0x1b42
++#define mmSCL1_SCL_MODE                                                         0x1e42
++#define mmSCL2_SCL_MODE                                                         0x4142
++#define mmSCL3_SCL_MODE                                                         0x4442
++#define mmSCL4_SCL_MODE                                                         0x4742
++#define mmSCL5_SCL_MODE                                                         0x4a42
++#define mmSCL_TAP_CONTROL                                                       0x1b43
++#define mmSCL0_SCL_TAP_CONTROL                                                  0x1b43
++#define mmSCL1_SCL_TAP_CONTROL                                                  0x1e43
++#define mmSCL2_SCL_TAP_CONTROL                                                  0x4143
++#define mmSCL3_SCL_TAP_CONTROL                                                  0x4443
++#define mmSCL4_SCL_TAP_CONTROL                                                  0x4743
++#define mmSCL5_SCL_TAP_CONTROL                                                  0x4a43
++#define mmSCL_CONTROL                                                           0x1b44
++#define mmSCL0_SCL_CONTROL                                                      0x1b44
++#define mmSCL1_SCL_CONTROL                                                      0x1e44
++#define mmSCL2_SCL_CONTROL                                                      0x4144
++#define mmSCL3_SCL_CONTROL                                                      0x4444
++#define mmSCL4_SCL_CONTROL                                                      0x4744
++#define mmSCL5_SCL_CONTROL                                                      0x4a44
++#define mmSCL_BYPASS_CONTROL                                                    0x1b45
++#define mmSCL0_SCL_BYPASS_CONTROL                                               0x1b45
++#define mmSCL1_SCL_BYPASS_CONTROL                                               0x1e45
++#define mmSCL2_SCL_BYPASS_CONTROL                                               0x4145
++#define mmSCL3_SCL_BYPASS_CONTROL                                               0x4445
++#define mmSCL4_SCL_BYPASS_CONTROL                                               0x4745
++#define mmSCL5_SCL_BYPASS_CONTROL                                               0x4a45
++#define mmSCL_MANUAL_REPLICATE_CONTROL                                          0x1b46
++#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL                                     0x1b46
++#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL                                     0x1e46
++#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL                                     0x4146
++#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                                     0x4446
++#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                                     0x4746
++#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                                     0x4a46
++#define mmSCL_AUTOMATIC_MODE_CONTROL                                            0x1b47
++#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL                                       0x1b47
++#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL                                       0x1e47
++#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL                                       0x4147
++#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                                       0x4447
++#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                                       0x4747
++#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                                       0x4a47
++#define mmSCL_HORZ_FILTER_CONTROL                                               0x1b48
++#define mmSCL0_SCL_HORZ_FILTER_CONTROL                                          0x1b48
++#define mmSCL1_SCL_HORZ_FILTER_CONTROL                                          0x1e48
++#define mmSCL2_SCL_HORZ_FILTER_CONTROL                                          0x4148
++#define mmSCL3_SCL_HORZ_FILTER_CONTROL                                          0x4448
++#define mmSCL4_SCL_HORZ_FILTER_CONTROL                                          0x4748
++#define mmSCL5_SCL_HORZ_FILTER_CONTROL                                          0x4a48
++#define mmSCL_HORZ_FILTER_SCALE_RATIO                                           0x1b49
++#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1b49
++#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1e49
++#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4149
++#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4449
++#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4749
++#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4a49
++#define mmSCL_HORZ_FILTER_INIT                                                  0x1b4a
++#define mmSCL0_SCL_HORZ_FILTER_INIT                                             0x1b4a
++#define mmSCL1_SCL_HORZ_FILTER_INIT                                             0x1e4a
++#define mmSCL2_SCL_HORZ_FILTER_INIT                                             0x414a
++#define mmSCL3_SCL_HORZ_FILTER_INIT                                             0x444a
++#define mmSCL4_SCL_HORZ_FILTER_INIT                                             0x474a
++#define mmSCL5_SCL_HORZ_FILTER_INIT                                             0x4a4a
++#define mmSCL_VERT_FILTER_CONTROL                                               0x1b4b
++#define mmSCL0_SCL_VERT_FILTER_CONTROL                                          0x1b4b
++#define mmSCL1_SCL_VERT_FILTER_CONTROL                                          0x1e4b
++#define mmSCL2_SCL_VERT_FILTER_CONTROL                                          0x414b
++#define mmSCL3_SCL_VERT_FILTER_CONTROL                                          0x444b
++#define mmSCL4_SCL_VERT_FILTER_CONTROL                                          0x474b
++#define mmSCL5_SCL_VERT_FILTER_CONTROL                                          0x4a4b
++#define mmSCL_VERT_FILTER_SCALE_RATIO                                           0x1b4c
++#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO                                      0x1b4c
++#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO                                      0x1e4c
++#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO                                      0x414c
++#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                                      0x444c
++#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                                      0x474c
++#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                                      0x4a4c
++#define mmSCL_VERT_FILTER_INIT                                                  0x1b4d
++#define mmSCL0_SCL_VERT_FILTER_INIT                                             0x1b4d
++#define mmSCL1_SCL_VERT_FILTER_INIT                                             0x1e4d
++#define mmSCL2_SCL_VERT_FILTER_INIT                                             0x414d
++#define mmSCL3_SCL_VERT_FILTER_INIT                                             0x444d
++#define mmSCL4_SCL_VERT_FILTER_INIT                                             0x474d
++#define mmSCL5_SCL_VERT_FILTER_INIT                                             0x4a4d
++#define mmSCL_VERT_FILTER_INIT_BOT                                              0x1b4e
++#define mmSCL0_SCL_VERT_FILTER_INIT_BOT                                         0x1b4e
++#define mmSCL1_SCL_VERT_FILTER_INIT_BOT                                         0x1e4e
++#define mmSCL2_SCL_VERT_FILTER_INIT_BOT                                         0x414e
++#define mmSCL3_SCL_VERT_FILTER_INIT_BOT                                         0x444e
++#define mmSCL4_SCL_VERT_FILTER_INIT_BOT                                         0x474e
++#define mmSCL5_SCL_VERT_FILTER_INIT_BOT                                         0x4a4e
++#define mmSCL_ROUND_OFFSET                                                      0x1b4f
++#define mmSCL0_SCL_ROUND_OFFSET                                                 0x1b4f
++#define mmSCL1_SCL_ROUND_OFFSET                                                 0x1e4f
++#define mmSCL2_SCL_ROUND_OFFSET                                                 0x414f
++#define mmSCL3_SCL_ROUND_OFFSET                                                 0x444f
++#define mmSCL4_SCL_ROUND_OFFSET                                                 0x474f
++#define mmSCL5_SCL_ROUND_OFFSET                                                 0x4a4f
++#define mmSCL_UPDATE                                                            0x1b51
++#define mmSCL0_SCL_UPDATE                                                       0x1b51
++#define mmSCL1_SCL_UPDATE                                                       0x1e51
++#define mmSCL2_SCL_UPDATE                                                       0x4151
++#define mmSCL3_SCL_UPDATE                                                       0x4451
++#define mmSCL4_SCL_UPDATE                                                       0x4751
++#define mmSCL5_SCL_UPDATE                                                       0x4a51
++#define mmSCL_F_SHARP_CONTROL                                                   0x1b53
++#define mmSCL0_SCL_F_SHARP_CONTROL                                              0x1b53
++#define mmSCL1_SCL_F_SHARP_CONTROL                                              0x1e53
++#define mmSCL2_SCL_F_SHARP_CONTROL                                              0x4153
++#define mmSCL3_SCL_F_SHARP_CONTROL                                              0x4453
++#define mmSCL4_SCL_F_SHARP_CONTROL                                              0x4753
++#define mmSCL5_SCL_F_SHARP_CONTROL                                              0x4a53
++#define mmSCL_ALU_CONTROL                                                       0x1b54
++#define mmSCL0_SCL_ALU_CONTROL                                                  0x1b54
++#define mmSCL1_SCL_ALU_CONTROL                                                  0x1e54
++#define mmSCL2_SCL_ALU_CONTROL                                                  0x4154
++#define mmSCL3_SCL_ALU_CONTROL                                                  0x4454
++#define mmSCL4_SCL_ALU_CONTROL                                                  0x4754
++#define mmSCL5_SCL_ALU_CONTROL                                                  0x4a54
++#define mmSCL_COEF_RAM_CONFLICT_STATUS                                          0x1b55
++#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1b55
++#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1e55
++#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4155
++#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4455
++#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4755
++#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4a55
++#define mmVIEWPORT_START                                                        0x1b5c
++#define mmSCL0_VIEWPORT_START                                                   0x1b5c
++#define mmSCL1_VIEWPORT_START                                                   0x1e5c
++#define mmSCL2_VIEWPORT_START                                                   0x415c
++#define mmSCL3_VIEWPORT_START                                                   0x445c
++#define mmSCL4_VIEWPORT_START                                                   0x475c
++#define mmSCL5_VIEWPORT_START                                                   0x4a5c
++#define mmVIEWPORT_SIZE                                                         0x1b5d
++#define mmSCL0_VIEWPORT_SIZE                                                    0x1b5d
++#define mmSCL1_VIEWPORT_SIZE                                                    0x1e5d
++#define mmSCL2_VIEWPORT_SIZE                                                    0x415d
++#define mmSCL3_VIEWPORT_SIZE                                                    0x445d
++#define mmSCL4_VIEWPORT_SIZE                                                    0x475d
++#define mmSCL5_VIEWPORT_SIZE                                                    0x4a5d
++#define mmEXT_OVERSCAN_LEFT_RIGHT                                               0x1b5e
++#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT                                          0x1b5e
++#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT                                          0x1e5e
++#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT                                          0x415e
++#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                                          0x445e
++#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                                          0x475e
++#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                                          0x4a5e
++#define mmEXT_OVERSCAN_TOP_BOTTOM                                               0x1b5f
++#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM                                          0x1b5f
++#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM                                          0x1e5f
++#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM                                          0x415f
++#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                                          0x445f
++#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                                          0x475f
++#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                                          0x4a5f
++#define mmSCL_MODE_CHANGE_DET1                                                  0x1b60
++#define mmSCL0_SCL_MODE_CHANGE_DET1                                             0x1b60
++#define mmSCL1_SCL_MODE_CHANGE_DET1                                             0x1e60
++#define mmSCL2_SCL_MODE_CHANGE_DET1                                             0x4160
++#define mmSCL3_SCL_MODE_CHANGE_DET1                                             0x4460
++#define mmSCL4_SCL_MODE_CHANGE_DET1                                             0x4760
++#define mmSCL5_SCL_MODE_CHANGE_DET1                                             0x4a60
++#define mmSCL_MODE_CHANGE_DET2                                                  0x1b61
++#define mmSCL0_SCL_MODE_CHANGE_DET2                                             0x1b61
++#define mmSCL1_SCL_MODE_CHANGE_DET2                                             0x1e61
++#define mmSCL2_SCL_MODE_CHANGE_DET2                                             0x4161
++#define mmSCL3_SCL_MODE_CHANGE_DET2                                             0x4461
++#define mmSCL4_SCL_MODE_CHANGE_DET2                                             0x4761
++#define mmSCL5_SCL_MODE_CHANGE_DET2                                             0x4a61
++#define mmSCL_MODE_CHANGE_DET3                                                  0x1b62
++#define mmSCL0_SCL_MODE_CHANGE_DET3                                             0x1b62
++#define mmSCL1_SCL_MODE_CHANGE_DET3                                             0x1e62
++#define mmSCL2_SCL_MODE_CHANGE_DET3                                             0x4162
++#define mmSCL3_SCL_MODE_CHANGE_DET3                                             0x4462
++#define mmSCL4_SCL_MODE_CHANGE_DET3                                             0x4762
++#define mmSCL5_SCL_MODE_CHANGE_DET3                                             0x4a62
++#define mmSCL_MODE_CHANGE_MASK                                                  0x1b63
++#define mmSCL0_SCL_MODE_CHANGE_MASK                                             0x1b63
++#define mmSCL1_SCL_MODE_CHANGE_MASK                                             0x1e63
++#define mmSCL2_SCL_MODE_CHANGE_MASK                                             0x4163
++#define mmSCL3_SCL_MODE_CHANGE_MASK                                             0x4463
++#define mmSCL4_SCL_MODE_CHANGE_MASK                                             0x4763
++#define mmSCL5_SCL_MODE_CHANGE_MASK                                             0x4a63
++#define mmSCL_DEBUG2                                                            0x1b69
++#define mmSCL0_SCL_DEBUG2                                                       0x1b69
++#define mmSCL1_SCL_DEBUG2                                                       0x1e69
++#define mmSCL2_SCL_DEBUG2                                                       0x4169
++#define mmSCL3_SCL_DEBUG2                                                       0x4469
++#define mmSCL4_SCL_DEBUG2                                                       0x4769
++#define mmSCL5_SCL_DEBUG2                                                       0x4a69
++#define mmSCL_DEBUG                                                             0x1b6a
++#define mmSCL0_SCL_DEBUG                                                        0x1b6a
++#define mmSCL1_SCL_DEBUG                                                        0x1e6a
++#define mmSCL2_SCL_DEBUG                                                        0x416a
++#define mmSCL3_SCL_DEBUG                                                        0x446a
++#define mmSCL4_SCL_DEBUG                                                        0x476a
++#define mmSCL5_SCL_DEBUG                                                        0x4a6a
++#define mmSCL_TEST_DEBUG_INDEX                                                  0x1b6b
++#define mmSCL0_SCL_TEST_DEBUG_INDEX                                             0x1b6b
++#define mmSCL1_SCL_TEST_DEBUG_INDEX                                             0x1e6b
++#define mmSCL2_SCL_TEST_DEBUG_INDEX                                             0x416b
++#define mmSCL3_SCL_TEST_DEBUG_INDEX                                             0x446b
++#define mmSCL4_SCL_TEST_DEBUG_INDEX                                             0x476b
++#define mmSCL5_SCL_TEST_DEBUG_INDEX                                             0x4a6b
++#define mmSCL_TEST_DEBUG_DATA                                                   0x1b6c
++#define mmSCL0_SCL_TEST_DEBUG_DATA                                              0x1b6c
++#define mmSCL1_SCL_TEST_DEBUG_DATA                                              0x1e6c
++#define mmSCL2_SCL_TEST_DEBUG_DATA                                              0x416c
++#define mmSCL3_SCL_TEST_DEBUG_DATA                                              0x446c
++#define mmSCL4_SCL_TEST_DEBUG_DATA                                              0x476c
++#define mmSCL5_SCL_TEST_DEBUG_DATA                                              0x4a6c
++#define mmGENMO_WT                                                              0xf0
++#define mmGENMO_RD                                                              0xf3
++#define mmGENENB                                                                0xf0
++#define mmGENFC_WT                                                              0xee
++#define mmVGA0_GENFC_WT                                                         0xee
++#define mmVGA1_GENFC_WT                                                         0xf6
++#define mmGENFC_RD                                                              0xf2
++#define mmGENS0                                                                 0xf0
++#define mmGENS1                                                                 0xee
++#define mmVGA0_GENS1                                                            0xee
++#define mmVGA1_GENS1                                                            0xf6
++#define mmDAC_DATA                                                              0xf2
++#define mmDAC_MASK                                                              0xf1
++#define mmDAC_R_INDEX                                                           0xf1
++#define mmDAC_W_INDEX                                                           0xf2
++#define mmSEQ8_IDX                                                              0xf1
++#define mmSEQ8_DATA                                                             0xf1
++#define ixSEQ00                                                                 0x0
++#define ixSEQ01                                                                 0x1
++#define ixSEQ02                                                                 0x2
++#define ixSEQ03                                                                 0x3
++#define ixSEQ04                                                                 0x4
++#define mmCRTC8_IDX                                                             0xed
++#define mmVGA0_CRTC8_IDX                                                        0xed
++#define mmVGA1_CRTC8_IDX                                                        0xf5
++#define mmCRTC8_DATA                                                            0xed
++#define mmVGA0_CRTC8_DATA                                                       0xed
++#define mmVGA1_CRTC8_DATA                                                       0xf5
++#define ixCRT00                                                                 0x0
++#define ixCRT01                                                                 0x1
++#define ixCRT02                                                                 0x2
++#define ixCRT03                                                                 0x3
++#define ixCRT04                                                                 0x4
++#define ixCRT05                                                                 0x5
++#define ixCRT06                                                                 0x6
++#define ixCRT07                                                                 0x7
++#define ixCRT08                                                                 0x8
++#define ixCRT09                                                                 0x9
++#define ixCRT0A                                                                 0xa
++#define ixCRT0B                                                                 0xb
++#define ixCRT0C                                                                 0xc
++#define ixCRT0D                                                                 0xd
++#define ixCRT0E                                                                 0xe
++#define ixCRT0F                                                                 0xf
++#define ixCRT10                                                                 0x10
++#define ixCRT11                                                                 0x11
++#define ixCRT12                                                                 0x12
++#define ixCRT13                                                                 0x13
++#define ixCRT14                                                                 0x14
++#define ixCRT15                                                                 0x15
++#define ixCRT16                                                                 0x16
++#define ixCRT17                                                                 0x17
++#define ixCRT18                                                                 0x18
++#define ixCRT1E                                                                 0x1e
++#define ixCRT1F                                                                 0x1f
++#define ixCRT22                                                                 0x22
++#define mmGRPH8_IDX                                                             0xf3
++#define mmGRPH8_DATA                                                            0xf3
++#define ixGRA00                                                                 0x0
++#define ixGRA01                                                                 0x1
++#define ixGRA02                                                                 0x2
++#define ixGRA03                                                                 0x3
++#define ixGRA04                                                                 0x4
++#define ixGRA05                                                                 0x5
++#define ixGRA06                                                                 0x6
++#define ixGRA07                                                                 0x7
++#define ixGRA08                                                                 0x8
++#define mmATTRX                                                                 0xf0
++#define mmATTRDW                                                                0xf0
++#define mmATTRDR                                                                0xf0
++#define ixATTR00                                                                0x0
++#define ixATTR01                                                                0x1
++#define ixATTR02                                                                0x2
++#define ixATTR03                                                                0x3
++#define ixATTR04                                                                0x4
++#define ixATTR05                                                                0x5
++#define ixATTR06                                                                0x6
++#define ixATTR07                                                                0x7
++#define ixATTR08                                                                0x8
++#define ixATTR09                                                                0x9
++#define ixATTR0A                                                                0xa
++#define ixATTR0B                                                                0xb
++#define ixATTR0C                                                                0xc
++#define ixATTR0D                                                                0xd
++#define ixATTR0E                                                                0xe
++#define ixATTR0F                                                                0xf
++#define ixATTR10                                                                0x10
++#define ixATTR11                                                                0x11
++#define ixATTR12                                                                0x12
++#define ixATTR13                                                                0x13
++#define ixATTR14                                                                0x14
++#define mmVGA_RENDER_CONTROL                                                    0xc0
++#define mmVGA_SOURCE_SELECT                                                     0xfc
++#define mmVGA_SEQUENCER_RESET_CONTROL                                           0xc1
++#define mmVGA_MODE_CONTROL                                                      0xc2
++#define mmVGA_SURFACE_PITCH_SELECT                                              0xc3
++#define mmVGA_MEMORY_BASE_ADDRESS                                               0xc4
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                          0xc9
++#define mmVGA_DISPBUF1_SURFACE_ADDR                                             0xc6
++#define mmVGA_DISPBUF2_SURFACE_ADDR                                             0xc8
++#define mmVGA_HDP_CONTROL                                                       0xca
++#define mmVGA_CACHE_CONTROL                                                     0xcb
++#define mmD1VGA_CONTROL                                                         0xcc
++#define mmD2VGA_CONTROL                                                         0xce
++#define mmD3VGA_CONTROL                                                         0xf8
++#define mmD4VGA_CONTROL                                                         0xf9
++#define mmD5VGA_CONTROL                                                         0xfa
++#define mmD6VGA_CONTROL                                                         0xfb
++#define mmVGA_HW_DEBUG                                                          0xcf
++#define mmVGA_STATUS                                                            0xd0
++#define mmVGA_INTERRUPT_CONTROL                                                 0xd1
++#define mmVGA_STATUS_CLEAR                                                      0xd2
++#define mmVGA_INTERRUPT_STATUS                                                  0xd3
++#define mmVGA_MAIN_CONTROL                                                      0xd4
++#define mmVGA_TEST_CONTROL                                                      0xd5
++#define mmVGA_DEBUG_READBACK_INDEX                                              0xd6
++#define mmVGA_DEBUG_READBACK_DATA                                               0xd7
++#define mmVGA_MEM_WRITE_PAGE_ADDR                                               0x12
++#define mmVGA_MEM_READ_PAGE_ADDR                                                0x13
++#define mmVGA_TEST_DEBUG_INDEX                                                  0xc5
++#define mmVGA_TEST_DEBUG_DATA                                                   0xc7
++#define ixVGADCC_DBG_DCCIF_C                                                    0x7e
++#define mmBPHYC_DAC_MACRO_CNTL                                                  0x19fd
++#define mmBPHYC_DAC_AUTO_CALIB_CONTROL                                          0x19fe
++#define mmDPG_PIPE_ARBITRATION_CONTROL1                                         0x1b30
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1                                0x1b30
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1                                0x1e30
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1                                0x4130
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                                0x4430
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                                0x4730
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                                0x4a30
++#define mmDPG_PIPE_ARBITRATION_CONTROL2                                         0x1b31
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2                                0x1b31
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2                                0x1e31
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2                                0x4131
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                                0x4431
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                                0x4731
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                                0x4a31
++#define mmDPG_WATERMARK_MASK_CONTROL                                            0x1b32
++#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL                                   0x1b32
++#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL                                   0x1e32
++#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL                                   0x4132
++#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                                   0x4432
++#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                                   0x4732
++#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                                   0x4a32
++#define mmDPG_PIPE_URGENCY_CONTROL                                              0x1b33
++#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL                                     0x1b33
++#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL                                     0x1e33
++#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL                                     0x4133
++#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                                     0x4433
++#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                                     0x4733
++#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                                     0x4a33
++#define mmDPG_PIPE_DPM_CONTROL                                                  0x1b34
++#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL                                         0x1b34
++#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL                                         0x1e34
++#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL                                         0x4134
++#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                                         0x4434
++#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                                         0x4734
++#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                                         0x4a34
++#define mmDPG_PIPE_STUTTER_CONTROL                                              0x1b35
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL                                     0x1b35
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL                                     0x1e35
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL                                     0x4135
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                                     0x4435
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                                     0x4735
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                                     0x4a35
++#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL                                     0x1b36
++#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1b36
++#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1e36
++#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4136
++#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4436
++#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4736
++#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4a36
++#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH                                     0x1b37
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1b37
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1e37
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4137
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4437
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4737
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4a37
++#define mmDPG_REPEATER_PROGRAM                                                  0x1b3a
++#define mmDMIF_PG0_DPG_REPEATER_PROGRAM                                         0x1b3a
++#define mmDMIF_PG1_DPG_REPEATER_PROGRAM                                         0x1e3a
++#define mmDMIF_PG2_DPG_REPEATER_PROGRAM                                         0x413a
++#define mmDMIF_PG3_DPG_REPEATER_PROGRAM                                         0x443a
++#define mmDMIF_PG4_DPG_REPEATER_PROGRAM                                         0x473a
++#define mmDMIF_PG5_DPG_REPEATER_PROGRAM                                         0x4a3a
++#define mmDPG_HW_DEBUG_A                                                        0x1b3b
++#define mmDMIF_PG0_DPG_HW_DEBUG_A                                               0x1b3b
++#define mmDMIF_PG1_DPG_HW_DEBUG_A                                               0x1e3b
++#define mmDMIF_PG2_DPG_HW_DEBUG_A                                               0x413b
++#define mmDMIF_PG3_DPG_HW_DEBUG_A                                               0x443b
++#define mmDMIF_PG4_DPG_HW_DEBUG_A                                               0x473b
++#define mmDMIF_PG5_DPG_HW_DEBUG_A                                               0x4a3b
++#define mmDPG_HW_DEBUG_B                                                        0x1b3c
++#define mmDMIF_PG0_DPG_HW_DEBUG_B                                               0x1b3c
++#define mmDMIF_PG1_DPG_HW_DEBUG_B                                               0x1e3c
++#define mmDMIF_PG2_DPG_HW_DEBUG_B                                               0x413c
++#define mmDMIF_PG3_DPG_HW_DEBUG_B                                               0x443c
++#define mmDMIF_PG4_DPG_HW_DEBUG_B                                               0x473c
++#define mmDMIF_PG5_DPG_HW_DEBUG_B                                               0x4a3c
++#define mmDPG_TEST_DEBUG_INDEX                                                  0x1b38
++#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX                                         0x1b38
++#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX                                         0x1e38
++#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX                                         0x4138
++#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                                         0x4438
++#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                                         0x4738
++#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                                         0x4a38
++#define mmDPG_TEST_DEBUG_DATA                                                   0x1b39
++#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA                                          0x1b39
++#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA                                          0x1e39
++#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA                                          0x4139
++#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA                                          0x4439
++#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA                                          0x4739
++#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA                                          0x4a39
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                       0x18
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                        0x18
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0xf00
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                            0xf02
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                 0xf04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT             0x1f04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x1f05
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x1f0a
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x1f0b
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x1f0f
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1705
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                0x17ff
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1720
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2              0x1721
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3              0x1722
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4              0x1723
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1770
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0x17d2
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                            0x17d3
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x17d5
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                   0x17d6
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x17d7
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x17d8
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x17d9
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x17da
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x17db
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                0x17dc
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x17dd
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x17de
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                     0x17d4
++#define mmAZALIA_F0_CODEC_DEBUG                                                 0x17df
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                           0x17e1
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                           0x17e2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                           0x17e3
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                           0x17e4
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                           0x17e5
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                           0x17e6
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                           0x17e7
++#define mmGLOBAL_CAPABILITIES                                                   0x0
++#define mmMINOR_VERSION                                                         0x0
++#define mmMAJOR_VERSION                                                         0x0
++#define mmOUTPUT_PAYLOAD_CAPABILITY                                             0x1
++#define mmINPUT_PAYLOAD_CAPABILITY                                              0x1
++#define mmGLOBAL_CONTROL                                                        0x2
++#define mmWAKE_ENABLE                                                           0x3
++#define mmSTATE_CHANGE_STATUS                                                   0x3
++#define mmGLOBAL_STATUS                                                         0x4
++#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY                                      0x6
++#define mmINTERRUPT_CONTROL                                                     0x8
++#define mmINTERRUPT_STATUS                                                      0x9
++#define mmWALL_CLOCK_COUNTER                                                    0xc
++#define mmSTREAM_SYNCHRONIZATION                                                0xe
++#define mmCORB_LOWER_BASE_ADDRESS                                               0x10
++#define mmCORB_UPPER_BASE_ADDRESS                                               0x11
++#define mmCORB_WRITE_POINTER                                                    0x12
++#define mmCORB_READ_POINTER                                                     0x12
++#define mmCORB_CONTROL                                                          0x13
++#define mmCORB_STATUS                                                           0x13
++#define mmCORB_SIZE                                                             0x13
++#define mmRIRB_LOWER_BASE_ADDRESS                                               0x14
++#define mmRIRB_UPPER_BASE_ADDRESS                                               0x15
++#define mmRIRB_WRITE_POINTER                                                    0x16
++#define mmRESPONSE_INTERRUPT_COUNT                                              0x16
++#define mmRIRB_CONTROL                                                          0x17
++#define mmRIRB_STATUS                                                           0x17
++#define mmRIRB_SIZE                                                             0x17
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                    0x18
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x18
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x18
++#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                    0x19
++#define mmIMMEDIATE_COMMAND_STATUS                                              0x1a
++#define mmDMA_POSITION_LOWER_BASE_ADDRESS                                       0x1c
++#define mmDMA_POSITION_UPPER_BASE_ADDRESS                                       0x1d
++#define mmWALL_CLOCK_COUNTER_ALIAS                                              0x80c
++#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                           0x20
++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER              0x21
++#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                         0x22
++#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                             0x23
++#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                    0x24
++#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT                                       0x24
++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS               0x26
++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS               0x27
++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS        0x821
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                   0x18
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                    0x18
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x2f09
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x2f0a
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x2f0b
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2200
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x2706
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x270d
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                 0x270e
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                 0x273e
++#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                              0x2724
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x2770
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x2771
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x3f09
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                            0x3f0c
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                  0x3f0e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY            0x3702
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x3707
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x3708
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x3709
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x371c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2          0x371d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3          0x371e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4          0x371f
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION               0x3770
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                        0x3771
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                             0x3772
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                          0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                     0x3776
++#define ixAUDIO_DESCRIPTOR0                                                     0x1
++#define ixAUDIO_DESCRIPTOR1                                                     0x2
++#define ixAUDIO_DESCRIPTOR2                                                     0x3
++#define ixAUDIO_DESCRIPTOR3                                                     0x4
++#define ixAUDIO_DESCRIPTOR4                                                     0x5
++#define ixAUDIO_DESCRIPTOR5                                                     0x6
++#define ixAUDIO_DESCRIPTOR6                                                     0x7
++#define ixAUDIO_DESCRIPTOR7                                                     0x8
++#define ixAUDIO_DESCRIPTOR8                                                     0x9
++#define ixAUDIO_DESCRIPTOR9                                                     0xa
++#define ixAUDIO_DESCRIPTOR10                                                    0xb
++#define ixAUDIO_DESCRIPTOR11                                                    0xc
++#define ixAUDIO_DESCRIPTOR12                                                    0xd
++#define ixAUDIO_DESCRIPTOR13                                                    0xe
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                     0x3777
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                     0x3778
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                     0x3779
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                     0x377a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                   0x377b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                     0x3780
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                      0x3781
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                           0x0
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                0x1
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                      0x2
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                   0x3
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                   0x4
++#define ixSINK_DESCRIPTION0                                                     0x5
++#define ixSINK_DESCRIPTION1                                                     0x6
++#define ixSINK_DESCRIPTION2                                                     0x7
++#define ixSINK_DESCRIPTION3                                                     0x8
++#define ixSINK_DESCRIPTION4                                                     0x9
++#define ixSINK_DESCRIPTION5                                                     0xa
++#define ixSINK_DESCRIPTION6                                                     0xb
++#define ixSINK_DESCRIPTION7                                                     0xc
++#define ixSINK_DESCRIPTION8                                                     0xd
++#define ixSINK_DESCRIPTION9                                                     0xe
++#define ixSINK_DESCRIPTION10                                                    0xf
++#define ixSINK_DESCRIPTION11                                                    0x10
++#define ixSINK_DESCRIPTION12                                                    0x11
++#define ixSINK_DESCRIPTION13                                                    0x12
++#define ixSINK_DESCRIPTION14                                                    0x13
++#define ixSINK_DESCRIPTION15                                                    0x14
++#define ixSINK_DESCRIPTION16                                                    0x15
++#define ixSINK_DESCRIPTION17                                                    0x16
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                      0x3785
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                      0x3786
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                      0x3787
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                      0x3788
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x3789
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x378a
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x378b
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x378c
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x378d
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x378e
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x378f
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x3790
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x3791
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x3792
++#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                  0x3793
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x3797
++#define mmAZALIA_CONTROLLER_CLOCK_GATING                                        0x17b9
++#define mmAZALIA_AUDIO_DTO                                                      0x17ba
++#define mmAZALIA_AUDIO_DTO_CONTROL                                              0x17bb
++#define mmAZALIA_SCLK_CONTROL                                                   0x17bc
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                        0x17bd
++#define mmAZALIA_DATA_DMA_CONTROL                                               0x17be
++#define mmAZALIA_BDL_DMA_CONTROL                                                0x17bf
++#define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17c0
++#define mmAZALIA_CORB_DMA_CONTROL                                               0x17c1
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                          0x17c9
++#define mmAZALIA_CYCLIC_BUFFER_SYNC                                             0x17ca
++#define mmAZALIA_GLOBAL_CAPABILITIES                                            0x17cb
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                      0x17cc
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                  0x17cd
++#define mmAZALIA_CONTROLLER_DEBUG                                               0x17cf
++#define mmAZALIA_CRC0_CONTROL0                                                  0x17ae
++#define mmAZALIA_CRC0_CONTROL1                                                  0x17af
++#define mmAZALIA_CRC0_CONTROL2                                                  0x17b0
++#define mmAZALIA_CRC0_CONTROL3                                                  0x17b1
++#define mmAZALIA_CRC0_RESULT                                                    0x17b2
++#define ixAZALIA_CRC0_CHANNEL0                                                  0x0
++#define ixAZALIA_CRC0_CHANNEL1                                                  0x1
++#define ixAZALIA_CRC0_CHANNEL2                                                  0x2
++#define ixAZALIA_CRC0_CHANNEL3                                                  0x3
++#define ixAZALIA_CRC0_CHANNEL4                                                  0x4
++#define ixAZALIA_CRC0_CHANNEL5                                                  0x5
++#define ixAZALIA_CRC0_CHANNEL6                                                  0x6
++#define ixAZALIA_CRC0_CHANNEL7                                                  0x7
++#define mmAZALIA_CRC1_CONTROL0                                                  0x17b3
++#define mmAZALIA_CRC1_CONTROL1                                                  0x17b4
++#define mmAZALIA_CRC1_CONTROL2                                                  0x17b5
++#define mmAZALIA_CRC1_CONTROL3                                                  0x17b6
++#define mmAZALIA_CRC1_RESULT                                                    0x17b7
++#define ixAZALIA_CRC1_CHANNEL0                                                  0x0
++#define ixAZALIA_CRC1_CHANNEL1                                                  0x1
++#define ixAZALIA_CRC1_CHANNEL2                                                  0x2
++#define ixAZALIA_CRC1_CHANNEL3                                                  0x3
++#define ixAZALIA_CRC1_CHANNEL4                                                  0x4
++#define ixAZALIA_CRC1_CHANNEL5                                                  0x5
++#define ixAZALIA_CRC1_CHANNEL6                                                  0x6
++#define ixAZALIA_CRC1_CHANNEL7                                                  0x7
++#define mmAZ_TEST_DEBUG_INDEX                                                   0x17d0
++#define mmAZ_TEST_DEBUG_DATA                                                    0x17d1
++#define mmAZALIA_STREAM_INDEX                                                   0x17e8
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                       0x17e8
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                       0x17ec
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                       0x17f0
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                       0x17f4
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                       0x17f8
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                       0x17fc
++#define mmAZALIA_STREAM_DATA                                                    0x17e9
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                        0x17e9
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                        0x17ed
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                        0x17f1
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                        0x17f5
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                        0x17f9
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                        0x17fd
++#define ixAZALIA_FIFO_SIZE_CONTROL                                              0x0
++#define ixAZALIA_LATENCY_COUNTER_CONTROL                                        0x1
++#define ixAZALIA_WORSTCASE_LATENCY_COUNT                                        0x2
++#define ixAZALIA_CUMULATIVE_LATENCY_COUNT                                       0x3
++#define ixAZALIA_CUMULATIVE_REQUEST_COUNT                                       0x4
++#define ixAZALIA_STREAM_DEBUG                                                   0x5
++#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX                                        0x1780
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x1780
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x1786
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x178c
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x1792
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x1798
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x179e
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17a4
++#define mmAZALIA_F0_CODEC_ENDPOINT_DATA                                         0x1781
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x1781
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x1787
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x178d
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x1793
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x1799
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x179f
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17a5
++#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG                                   0x0
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x1
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x3
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x4
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x5
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x6
++#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                              0x7
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x8
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x9
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG                    0xa
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                           0xc
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                       0xd
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                       0xe
++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x20
++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                            0x21
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x22
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                         0x2b
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                         0x2c
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                         0x2d
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                         0x2e
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                         0x2f
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                         0x30
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                         0x31
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                        0x32
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                        0x33
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                        0x34
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                        0x35
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                       0x36
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                      0x57
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x58
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                          0x37
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                              0x38
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                0x3a
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                0x3b
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                0x3c
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                0x3d
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                0x3e
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                0x3f
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                0x40
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                0x41
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                0x42
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                          0x54
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                0x55
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x56
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x59
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x5a
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x5b
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x5c
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x5d
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x5e
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x5f
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x60
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x61
++#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                  0x62
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x63
++#define mmBLND_CONTROL                                                          0x1b6d
++#define mmBLND0_BLND_CONTROL                                                    0x1b6d
++#define mmBLND1_BLND_CONTROL                                                    0x1e6d
++#define mmBLND2_BLND_CONTROL                                                    0x416d
++#define mmBLND3_BLND_CONTROL                                                    0x446d
++#define mmBLND4_BLND_CONTROL                                                    0x476d
++#define mmBLND5_BLND_CONTROL                                                    0x4a6d
++#define mmSM_CONTROL2                                                           0x1b6e
++#define mmBLND0_SM_CONTROL2                                                     0x1b6e
++#define mmBLND1_SM_CONTROL2                                                     0x1e6e
++#define mmBLND2_SM_CONTROL2                                                     0x416e
++#define mmBLND3_SM_CONTROL2                                                     0x446e
++#define mmBLND4_SM_CONTROL2                                                     0x476e
++#define mmBLND5_SM_CONTROL2                                                     0x4a6e
++#define mmPTI_CONTROL                                                           0x1b6f
++#define mmBLND0_PTI_CONTROL                                                     0x1b6f
++#define mmBLND1_PTI_CONTROL                                                     0x1e6f
++#define mmBLND2_PTI_CONTROL                                                     0x416f
++#define mmBLND3_PTI_CONTROL                                                     0x446f
++#define mmBLND4_PTI_CONTROL                                                     0x476f
++#define mmBLND5_PTI_CONTROL                                                     0x4a6f
++#define mmBLND_UPDATE                                                           0x1b70
++#define mmBLND0_BLND_UPDATE                                                     0x1b70
++#define mmBLND1_BLND_UPDATE                                                     0x1e70
++#define mmBLND2_BLND_UPDATE                                                     0x4170
++#define mmBLND3_BLND_UPDATE                                                     0x4470
++#define mmBLND4_BLND_UPDATE                                                     0x4770
++#define mmBLND5_BLND_UPDATE                                                     0x4a70
++#define mmBLND_UNDERFLOW_INTERRUPT                                              0x1b71
++#define mmBLND0_BLND_UNDERFLOW_INTERRUPT                                        0x1b71
++#define mmBLND1_BLND_UNDERFLOW_INTERRUPT                                        0x1e71
++#define mmBLND2_BLND_UNDERFLOW_INTERRUPT                                        0x4171
++#define mmBLND3_BLND_UNDERFLOW_INTERRUPT                                        0x4471
++#define mmBLND4_BLND_UNDERFLOW_INTERRUPT                                        0x4771
++#define mmBLND5_BLND_UNDERFLOW_INTERRUPT                                        0x4a71
++#define mmBLND_V_UPDATE_LOCK                                                    0x1b73
++#define mmBLND0_BLND_V_UPDATE_LOCK                                              0x1b73
++#define mmBLND1_BLND_V_UPDATE_LOCK                                              0x1e73
++#define mmBLND2_BLND_V_UPDATE_LOCK                                              0x4173
++#define mmBLND3_BLND_V_UPDATE_LOCK                                              0x4473
++#define mmBLND4_BLND_V_UPDATE_LOCK                                              0x4773
++#define mmBLND5_BLND_V_UPDATE_LOCK                                              0x4a73
++#define mmBLND_REG_UPDATE_STATUS                                                0x1b77
++#define mmBLND0_BLND_REG_UPDATE_STATUS                                          0x1b77
++#define mmBLND1_BLND_REG_UPDATE_STATUS                                          0x1e77
++#define mmBLND2_BLND_REG_UPDATE_STATUS                                          0x4177
++#define mmBLND3_BLND_REG_UPDATE_STATUS                                          0x4477
++#define mmBLND4_BLND_REG_UPDATE_STATUS                                          0x4777
++#define mmBLND5_BLND_REG_UPDATE_STATUS                                          0x4a77
++#define mmBLND_DEBUG                                                            0x1b74
++#define mmBLND0_BLND_DEBUG                                                      0x1b74
++#define mmBLND1_BLND_DEBUG                                                      0x1e74
++#define mmBLND2_BLND_DEBUG                                                      0x4174
++#define mmBLND3_BLND_DEBUG                                                      0x4474
++#define mmBLND4_BLND_DEBUG                                                      0x4774
++#define mmBLND5_BLND_DEBUG                                                      0x4a74
++#define mmBLND_TEST_DEBUG_INDEX                                                 0x1b75
++#define mmBLND0_BLND_TEST_DEBUG_INDEX                                           0x1b75
++#define mmBLND1_BLND_TEST_DEBUG_INDEX                                           0x1e75
++#define mmBLND2_BLND_TEST_DEBUG_INDEX                                           0x4175
++#define mmBLND3_BLND_TEST_DEBUG_INDEX                                           0x4475
++#define mmBLND4_BLND_TEST_DEBUG_INDEX                                           0x4775
++#define mmBLND5_BLND_TEST_DEBUG_INDEX                                           0x4a75
++#define mmBLND_TEST_DEBUG_DATA                                                  0x1b76
++#define mmBLND0_BLND_TEST_DEBUG_DATA                                            0x1b76
++#define mmBLND1_BLND_TEST_DEBUG_DATA                                            0x1e76
++#define mmBLND2_BLND_TEST_DEBUG_DATA                                            0x4176
++#define mmBLND3_BLND_TEST_DEBUG_DATA                                            0x4476
++#define mmBLND4_BLND_TEST_DEBUG_DATA                                            0x4776
++#define mmBLND5_BLND_TEST_DEBUG_DATA                                            0x4a76
++#define mmSI_ENABLE                                                             0x4c00
++#define mmSI_EC_CONFIG                                                          0x4c01
++#define mmCNV_MODE                                                              0x4c02
++#define mmCNV_WINDOW_START                                                      0x4c03
++#define mmCNV_WINDOW_SIZE                                                       0x4c04
++#define mmCNV_UPDATE                                                            0x4c05
++#define mmCNV_SOURCE_SIZE                                                       0x4c06
++#define mmCNV_CSC_CONTROL                                                       0x4c07
++#define mmCNV_CSC_C11_C12                                                       0x4c08
++#define mmCNV_CSC_C13_C14                                                       0x4c09
++#define mmCNV_CSC_C21_C22                                                       0x4c0a
++#define mmCNV_CSC_C23_C24                                                       0x4c0b
++#define mmCNV_CSC_C31_C32                                                       0x4c0c
++#define mmCNV_CSC_C33_C34                                                       0x4c0d
++#define mmCNV_CSC_ROUND_OFFSET_R                                                0x4c0e
++#define mmCNV_CSC_ROUND_OFFSET_G                                                0x4c0f
++#define mmCNV_CSC_ROUND_OFFSET_B                                                0x4c10
++#define mmCNV_CSC_CLAMP_R                                                       0x4c11
++#define mmCNV_CSC_CLAMP_G                                                       0x4c12
++#define mmCNV_CSC_CLAMP_B                                                       0x4c13
++#define mmCNV_TEST_CNTL                                                         0x4c14
++#define mmCNV_TEST_CRC_RED                                                      0x4c15
++#define mmCNV_TEST_CRC_GREEN                                                    0x4c16
++#define mmCNV_TEST_CRC_BLUE                                                     0x4c17
++#define mmSI_DEBUG_CTRL                                                         0x4c18
++#define mmSI_DBG_MODE                                                           0x4c1b
++#define mmSI_HARD_DEBUG                                                         0x4c1c
++#define mmCNV_TEST_DEBUG_INDEX                                                  0x4c19
++#define mmCNV_TEST_DEBUG_DATA                                                   0x4c1a
++#define mmSISCL_COEF_RAM_SELECT                                                 0x4c20
++#define mmSISCL_COEF_RAM_TAP_DATA                                               0x4c21
++#define mmSISCL_MODE                                                            0x4c22
++#define mmSISCL_TAP_CONTROL                                                     0x4c23
++#define mmSISCL_DEST_SIZE                                                       0x4c24
++#define mmSISCL_HORZ_FILTER_SCALE_RATIO                                         0x4c25
++#define mmSISCL_HORZ_FILTER_INIT_Y_RGB                                          0x4c26
++#define mmSISCL_HORZ_FILTER_INIT_CBCR                                           0x4c27
++#define mmSISCL_VERT_FILTER_SCALE_RATIO                                         0x4c28
++#define mmSISCL_VERT_FILTER_INIT_Y_RGB                                          0x4c29
++#define mmSISCL_VERT_FILTER_INIT_CBCR                                           0x4c2a
++#define mmSISCL_ROUND_OFFSET                                                    0x4c2b
++#define mmSISCL_CLAMP                                                           0x4c2c
++#define mmSISCL_OVERFLOW_STATUS                                                 0x4c2d
++#define mmSISCL_COEF_RAM_CONFLICT_STATUS                                        0x4c2e
++#define mmSISCL_OUTSIDE_PIX_STRATEGY                                            0x4c2f
++#define mmSISCL_TEST_CNTL                                                       0x4c30
++#define mmSISCL_TEST_CRC_RED                                                    0x4c31
++#define mmSISCL_TEST_CRC_GREEN                                                  0x4c32
++#define mmSISCL_TEST_CRC_BLUE                                                   0x4c33
++#define mmSISCL_BACKPRESSURE_CNT_EN                                             0x4c36
++#define mmSISCL_MCIF_BACKPRESSURE_CNT                                           0x4c37
++#define mmSISCL_TEST_DEBUG_INDEX                                                0x4c34
++#define mmSISCL_TEST_DEBUG_DATA                                                 0x4c35
++#define mmXDMA_MC_PCIE_CLIENT_CONFIG                                            0x3e0
++#define mmXDMA_LOCAL_SURFACE_TILING1                                            0x3e1
++#define mmXDMA_LOCAL_SURFACE_TILING2                                            0x3e2
++#define mmXDMA_INTERRUPT                                                        0x3e3
++#define mmXDMA_CLOCK_GATING_CNTL                                                0x3e4
++#define mmXDMA_MEM_POWER_CNTL                                                   0x3e6
++#define mmXDMA_IF_BIF_STATUS                                                    0x3e7
++#define mmXDMA_PERF_MEAS_STATUS                                                 0x3e8
++#define mmXDMA_IF_STATUS                                                        0x3e9
++#define mmXDMA_TEST_DEBUG_INDEX                                                 0x3ea
++#define mmXDMA_TEST_DEBUG_DATA                                                  0x3eb
++#define mmXDMA_RBBMIF_RDWR_CNTL                                                 0x3f8
++#define mmXDMA_PG_CONTROL                                                       0x3f9
++#define mmXDMA_PG_WDATA                                                         0x3fa
++#define mmXDMA_PG_STATUS                                                        0x3fb
++#define mmXDMA_AON_TEST_DEBUG_INDEX                                             0x3fc
++#define mmXDMA_AON_TEST_DEBUG_DATA                                              0x3fd
++
++#endif /* DCE_8_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
+new file mode 100644
+index 0000000..8a29307
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
+@@ -0,0 +1,13109 @@
++/*
++ * DCE_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_8_0_SH_MASK_H
++#define DCE_8_0_SH_MASK_H
++
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
++#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
++#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
++#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
++#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
++#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
++#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1
++#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
++#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1
++#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
++#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf
++#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x1
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x0
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK 0x2
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS__SHIFT 0x1
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x4
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x10
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x4
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x20
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x5
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x40
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x6
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x300
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE_MASK 0xc00
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x3000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0xc000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x30000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x10
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0xc0000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x300000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0xc00000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x16
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x3000000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x18
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x1c
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x1d
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000
++#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x1e
++#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x1fff
++#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x1fff
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x1fff
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x1fff
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x1fff
++#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000
++#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x1fff
++#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x1fff
++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x1fff
++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x1fff
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x1fff
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x1fff
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x1fff
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
++#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
++#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
++#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
++#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
++#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
++#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
++#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
++#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
++#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
++#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x1fff
++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000
++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x1fff
++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffff
++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffff
++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x1fff
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x1fff
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100
++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8
++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xf0000
++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x10
++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
++#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
++#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
++#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x1fff
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x1fff0000
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x1fff
++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x1fff
++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
++#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x1fff
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x1fff0000
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x1fff
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x1fff0000
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x1fff
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x1fff0000
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x1fff
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x1fff0000
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
++#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
++#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
++#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x1fff
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x1fff0000
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x1fff
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x1fff0000
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x1fff
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x1fff0000
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x1fff
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x1fff0000
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
++#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
++#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
++#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x1fff
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x1fff0000
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x1fff
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x1fff0000
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x1fff
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x1fff
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
++#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
++#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
++#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
++#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
++#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
++#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x100
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x8
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x1000000
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x18
++#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
++#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
++#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
++#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
++#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
++#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
++#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
++#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
++#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
++#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
++#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
++#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xf0
++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x4
++#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
++#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define PERFMON_HI__PERFMON_HI_MASK 0xffff
++#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
++#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
++#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff
++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0
++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff
++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0
++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff
++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f
++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18
++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f
++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18
++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f
++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
++#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN_MASK 0x10
++#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN__SHIFT 0x4
++#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET_MASK 0x1
++#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET__SHIFT 0x0
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
++#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
++#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x100
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x8
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x200
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x9
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x400
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0xa
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0xb
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x1000
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0xc
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x2000
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0xd
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE_MASK 0x4000
++#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE__SHIFT 0xe
++#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000
++#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x7000000
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x18
++#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000
++#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x1c
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000
++#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1
++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0
++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0
++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
++#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x1
++#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x0
++#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x100
++#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
++#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
++#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
++#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
++#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
++#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
++#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
++#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
++#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
++#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
++#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
++#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
++#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
++#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
++#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
++#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
++#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
++#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
++#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
++#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x2
++#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x4
++#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x8
++#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x3
++#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x10
++#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x4
++#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x2
++#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x4
++#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x8
++#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x3
++#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x10
++#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x4
++#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x2
++#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x4
++#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x8
++#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x3
++#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x10
++#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x4
++#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x2
++#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x4
++#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x8
++#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x3
++#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x10
++#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x4
++#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x2
++#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x4
++#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x8
++#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x3
++#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x10
++#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x4
++#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x2
++#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x4
++#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x8
++#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x3
++#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x10
++#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x4
++#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
++#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
++#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
++#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
++#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
++#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
++#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET_MASK 0x4000
++#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET__SHIFT 0xe
++#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET_MASK 0x8000
++#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET__SHIFT 0xf
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
++#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x1
++#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x0
++#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x2
++#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x1
++#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x4
++#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x2
++#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x8
++#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x3
++#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x10
++#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x4
++#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x20
++#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x5
++#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x40
++#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0x6
++#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
++#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
++#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x2
++#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x1
++#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
++#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
++#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
++#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
++#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
++#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
++#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
++#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
++#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x4000000
++#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x1a
++#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
++#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
++#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000
++#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x1c
++#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000
++#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x1d
++#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7
++#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000
++#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000
++#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
++#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000
++#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
++#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000
++#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
++#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7
++#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000
++#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000
++#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x1000
++#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0xc
++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
++#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff
++#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0
++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000
++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000
++#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10
++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f
++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7
++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf
++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10
++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff
++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8
++#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000
++#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc
++#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000
++#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd
++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000
++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10
++#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff
++#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0
++#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000
++#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10
++#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000
++#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12
++#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000
++#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3
++#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x10
++#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x4
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10
++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000
++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14
++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000
++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16
++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000
++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18
++#define PLL_CNTL__PLL_RESET_MASK 0x1
++#define PLL_CNTL__PLL_RESET__SHIFT 0x0
++#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
++#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1
++#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4
++#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
++#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8
++#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3
++#define PLL_CNTL__PLL_VCOREF_MASK 0x30
++#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4
++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40
++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6
++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80
++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7
++#define PLL_CNTL__PLL_CALREF_MASK 0x300
++#define PLL_CNTL__PLL_CALREF__SHIFT 0x8
++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400
++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa
++#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800
++#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb
++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000
++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd
++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000
++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe
++#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000
++#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10
++#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000
++#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13
++#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000
++#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14
++#define PLL_CNTL__PLL_LOCKED_MASK 0x200000
++#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15
++#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000
++#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18
++#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000
++#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a
++#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f
++#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0
++#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60
++#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5
++#define PLL_ANALOG__PLL_CP_MASK 0xf00
++#define PLL_ANALOG__PLL_CP__SHIFT 0x8
++#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000
++#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc
++#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000
++#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15
++#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000
++#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18
++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1
++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0
++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e
++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1
++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0
++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5
++#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff
++#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0
++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000
++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14
++#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000
++#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a
++#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000
++#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1
++#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1
++#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00
++#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x8
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x3
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8
++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1
++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0
++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0
++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4
++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00
++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b
++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1
++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0
++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1
++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0
++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100
++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8
++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000
++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x1ff
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x0
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x10000
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x10
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x60000
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x11
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x100000
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x14
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x200000
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x15
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x400000
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x16
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000
++#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x18
++#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x1ff
++#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0xf
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x1f0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x4
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf0000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x10
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x20
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x5
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x40
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x6
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x80
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x7
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0xfff00
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x8
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x300000
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x14
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x400000
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x16
++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
++#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
++#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
++#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
++#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
++#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
++#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
++#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
++#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
++#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
++#define MCIF_CONTROL__MCIF_SCANIN_DISABLE_MASK 0x8
++#define MCIF_CONTROL__MCIF_SCANIN_DISABLE__SHIFT 0x3
++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
++#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
++#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
++#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
++#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
++#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
++#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0xf
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x0
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x20
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x5
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x3c0
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x6
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0xb
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0xf000
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0xc
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x20000
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x11
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x3c0000
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x12
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x800000
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x17
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0xf000000
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x18
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x20000000
++#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x1d
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY_MASK 0xf
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY__SHIFT 0x0
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS_MASK 0x20
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS__SHIFT 0x5
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY_MASK 0x3c0
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY__SHIFT 0x6
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS__SHIFT 0xb
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY_MASK 0xf000
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY__SHIFT 0xc
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS_MASK 0x20000
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS__SHIFT 0x11
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x3c0000
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x12
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x800000
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x17
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0xf000000
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x18
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x20000000
++#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x1d
++#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY_MASK 0xf
++#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY__SHIFT 0x0
++#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS_MASK 0x20
++#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS__SHIFT 0x5
++#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY_MASK 0x1ffff000
++#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY__SHIFT 0xc
++#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x3
++#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0xc
++#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x30
++#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0xc0
++#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x6
++#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x300
++#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x8
++#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0xc00
++#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0xa
++#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x3000
++#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0xc000
++#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x30000
++#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x10
++#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0xc0000
++#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x12
++#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x300000
++#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0xc00000
++#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x3000000
++#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0xc000000
++#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x1a
++#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000
++#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x1c
++#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE_MASK 0xc0000000
++#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE__SHIFT 0x1e
++#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x3
++#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0xc
++#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x30
++#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x4
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
++#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x400
++#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0xa
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
++#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x1000
++#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0xc
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
++#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x4000
++#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0xe
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
++#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x1
++#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x0
++#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x2
++#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1
++#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x4
++#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x10
++#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x4
++#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x20
++#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x5
++#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x100
++#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x8
++#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x200
++#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x9
++#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x400
++#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0xa
++#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800
++#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0xb
++#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x1000
++#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0xc
++#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x2000
++#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0xd
++#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x4000
++#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0xe
++#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x8000
++#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0xf
++#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x10000
++#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x10
++#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x20000
++#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x11
++#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x40000
++#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x12
++#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x80000
++#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x13
++#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x100000
++#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x14
++#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x200000
++#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x15
++#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x400000
++#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x16
++#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x800000
++#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x17
++#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x1000000
++#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x18
++#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x2000000
++#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x19
++#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x4000000
++#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x1a
++#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE_MASK 0x8000000
++#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1b
++#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE_MASK 0x10000000
++#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x1c
++#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x1
++#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x2
++#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x1
++#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x10
++#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x4
++#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x20
++#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x40
++#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x80
++#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x100
++#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x200
++#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x9
++#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x400
++#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800
++#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000
++#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0xc000
++#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x30000
++#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc0000
++#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x300000
++#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0xc00000
++#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x16
++#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x3f
++#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x0
++#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x700
++#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x8
++#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x10000
++#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x10
++#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x100000
++#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x14
++#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x200000
++#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x15
++#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x400000
++#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x16
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0xf
++#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x0
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE_MASK 0x1
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE__SHIFT 0x0
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN_MASK 0x10
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN__SHIFT 0x4
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK_MASK 0x20
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK__SHIFT 0x5
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK_MASK 0xf00
++#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK__SHIFT 0x8
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS_MASK 0x2
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS__SHIFT 0x1
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF_MASK 0x70
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF__SHIFT 0x4
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG_MASK 0xf00
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG__SHIFT 0x8
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE_MASK 0x1fff000
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE__SHIFT 0xc
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF_MASK 0x70000000
++#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF__SHIFT 0x1c
++#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH_MASK 0xffff
++#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH__SHIFT 0x0
++#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH_MASK 0xffff0000
++#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH__SHIFT 0x10
++#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
++#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
++#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
++#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
++#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
++#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
++#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
++#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
++#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
++#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
++#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
++#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
++#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
++#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
++#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
++#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
++#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
++#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
++#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
++#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
++#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
++#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
++#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
++#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
++#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
++#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
++#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
++#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
++#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
++#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
++#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
++#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
++#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
++#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
++#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
++#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
++#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
++#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
++#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE_MASK 0x10
++#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
++#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
++#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
++#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
++#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
++#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE_MASK 0x80
++#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE__SHIFT 0x7
++#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
++#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
++#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
++#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
++#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
++#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
++#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
++#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
++#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
++#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
++#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
++#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
++#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE_MASK 0x10
++#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
++#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
++#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
++#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
++#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
++#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE_MASK 0x80
++#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE__SHIFT 0x7
++#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
++#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
++#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
++#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
++#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
++#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
++#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
++#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
++#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
++#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
++#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
++#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
++#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE_MASK 0x10
++#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
++#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
++#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
++#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
++#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
++#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE_MASK 0x80
++#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE__SHIFT 0x7
++#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
++#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
++#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
++#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
++#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
++#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
++#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
++#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
++#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
++#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
++#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
++#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
++#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE_MASK 0x10
++#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
++#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
++#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
++#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
++#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
++#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE_MASK 0x80
++#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE__SHIFT 0x7
++#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
++#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
++#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
++#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
++#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
++#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
++#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE_MASK 0x3
++#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE__SHIFT 0x0
++#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE_MASK 0x30
++#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE__SHIFT 0x4
++#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
++#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
++#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
++#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
++#define DC_GENERICA__GENERICA_EN_MASK 0x1
++#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
++#define DC_GENERICA__GENERICA_SEL_MASK 0xf00
++#define DC_GENERICA__GENERICA_SEL__SHIFT 0x8
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_GENERICB__GENERICB_EN_MASK 0x1
++#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
++#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
++#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
++#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x3
++#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0xc
++#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x2
++#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x30
++#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x4
++#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0xc0
++#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x6
++#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x300
++#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x8
++#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0xc00
++#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0xa
++#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x3000
++#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0xc
++#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0xc000
++#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0xe
++#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x30000
++#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x10
++#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0xc0000
++#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x12
++#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x300000
++#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x14
++#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0xc00000
++#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x16
++#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x3000000
++#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x18
++#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0xc000000
++#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x1a
++#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000
++#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x1c
++#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE_MASK 0x3
++#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE_MASK 0xc
++#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT 0x2
++#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x1
++#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x0
++#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x2
++#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x1
++#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x4
++#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x10
++#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x4
++#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x20
++#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x5
++#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x40
++#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x6
++#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x80
++#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x7
++#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x100
++#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x8
++#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x200
++#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x9
++#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x400
++#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0xa
++#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x800
++#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0xb
++#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x1000
++#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0xc
++#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x2000
++#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0xd
++#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x4000
++#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0xe
++#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS_MASK 0x8000
++#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS__SHIFT 0xf
++#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x10000
++#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x10
++#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x20000
++#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x11
++#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x40000
++#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x12
++#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x80000
++#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x13
++#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x100000
++#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x14
++#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x200000
++#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x15
++#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x400000
++#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x16
++#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS_MASK 0x800000
++#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS__SHIFT 0x17
++#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS_MASK 0x1000000
++#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
++#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x800
++#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0xb
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
++#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
++#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
++#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
++#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
++#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f
++#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x1000
++#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0xc
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
++#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20
++#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9
++#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x1000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0xc
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e
++#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x1000
++#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0xc
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x8000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0xf
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x100000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x14
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x200000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x15
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x800000
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x17
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x2000000
++#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x19
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
++#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
++#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
++#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
++#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
++#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
++#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
++#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
++#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
++#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
++#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
++#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
++#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
++#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
++#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
++#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
++#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
++#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
++#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
++#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
++#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
++#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
++#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
++#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
++#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
++#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
++#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
++#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
++#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
++#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
++#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
++#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
++#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
++#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
++#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
++#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
++#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
++#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
++#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
++#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
++#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
++#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf
++#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
++#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0
++#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
++#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00
++#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
++#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000
++#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
++#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000
++#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
++#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000
++#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
++#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000
++#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
++#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000
++#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
++#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000
++#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
++#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
++#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
++#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
++#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
++#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
++#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
++#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x3ff
++#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x0
++#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x10000
++#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x10
++#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0xe0000
++#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x11
++#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x7fffff
++#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x0
++#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x3ff
++#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x0
++#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x10000
++#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x10
++#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0xe0000
++#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x11
++#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x7fffff
++#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x0
++#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x3ff
++#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x0
++#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x10000
++#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x10
++#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0xe0000
++#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x11
++#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x7fffff
++#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x0
++#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN_MASK 0x3ff
++#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN__SHIFT 0x0
++#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN_MASK 0x10000
++#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN__SHIFT 0x10
++#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL_MASK 0xe0000
++#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL__SHIFT 0x11
++#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED_MASK 0x7fffff
++#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000
++#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000
++#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000
++#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000
++#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_MASK 0x700
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH__SHIFT 0x8
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000
++#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_MASK 0x7000000
++#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH__SHIFT 0x18
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x7000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x70000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17
++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000
++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18
++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000
++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0
++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1
++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x4
++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a
++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0
++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc
++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc
++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d
++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff
++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x1000
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0xc
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x1c
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a
++#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x30000
++#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x10
++#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff
++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0
++#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
++#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
++#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
++#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define GRPH_CONTROL__GRPH_Z_MASK 0x30
++#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
++#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
++#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
++#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
++#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
++#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
++#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
++#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
++#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
++#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
++#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
++#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
++#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
++#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
++#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3
++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30
++#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
++#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
++#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define OVL_ENABLE__OVL_ENABLE_MASK 0x1
++#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0
++#define OVL_ENABLE__OVLSCL_EN_MASK 0x100
++#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8
++#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3
++#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0
++#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc
++#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2
++#define OVL_CONTROL1__OVL_Z_MASK 0x30
++#define OVL_CONTROL1__OVL_Z__SHIFT 0x4
++#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0
++#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6
++#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700
++#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8
++#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800
++#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb
++#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000
++#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd
++#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000
++#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12
++#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000
++#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14
++#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000
++#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18
++#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000
++#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19
++#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000
++#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e
++#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1
++#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0
++#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3
++#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0
++#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30
++#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4
++#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0
++#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6
++#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300
++#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8
++#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00
++#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa
++#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1
++#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0
++#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00
++#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8
++#define OVL_PITCH__OVL_PITCH_MASK 0x7fff
++#define OVL_PITCH__OVL_PITCH__SHIFT 0x0
++#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff
++#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0
++#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff
++#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0
++#define OVL_START__OVL_Y_START_MASK 0x3fff
++#define OVL_START__OVL_Y_START__SHIFT 0x0
++#define OVL_START__OVL_X_START_MASK 0x3fff0000
++#define OVL_START__OVL_X_START__SHIFT 0x10
++#define OVL_END__OVL_Y_END_MASK 0x7fff
++#define OVL_END__OVL_Y_END__SHIFT 0x0
++#define OVL_END__OVL_X_END_MASK 0x7fff0000
++#define OVL_END__OVL_X_END__SHIFT 0x10
++#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1
++#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0
++#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2
++#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1
++#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000
++#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10
++#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
++#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1
++#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0
++#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70
++#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4
++#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700
++#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf
++#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
++#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9
++#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
++#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10
++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30
++#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4
++#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
++#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
++#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
++#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
++#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
++#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
++#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
++#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
++#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
++#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
++#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
++#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
++#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
++#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
++#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define KEY_CONTROL__KEY_SELECT_MASK 0x1
++#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0
++#define KEY_CONTROL__KEY_MODE_MASK 0x6
++#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000
++#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c
++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
++#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
++#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
++#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
++#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30
++#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4
++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30
++#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff
++#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00
++#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000
++#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define CUR_CONTROL__CURSOR_EN_MASK 0x1
++#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
++#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
++#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
++#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
++#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
++#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
++#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
++#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
++#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
++#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
++#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
++#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
++#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
++#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
++#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
++#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
++#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define CUR2_CONTROL__CURSOR2_EN_MASK 0x1
++#define CUR2_CONTROL__CURSOR2_EN__SHIFT 0x0
++#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP_MASK 0x10
++#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP__SHIFT 0x4
++#define CUR2_CONTROL__CURSOR2_MODE_MASK 0x300
++#define CUR2_CONTROL__CURSOR2_MODE__SHIFT 0x8
++#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY_MASK 0x10000
++#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY__SHIFT 0x10
++#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON_MASK 0x100000
++#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON__SHIFT 0x14
++#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL_MASK 0x7000000
++#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL__SHIFT 0x18
++#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS_MASK 0xffffffff
++#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS__SHIFT 0x0
++#define CUR2_SIZE__CURSOR2_HEIGHT_MASK 0x7f
++#define CUR2_SIZE__CURSOR2_HEIGHT__SHIFT 0x0
++#define CUR2_SIZE__CURSOR2_WIDTH_MASK 0x7f0000
++#define CUR2_SIZE__CURSOR2_WIDTH__SHIFT 0x10
++#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define CUR2_POSITION__CURSOR2_Y_POSITION_MASK 0x3fff
++#define CUR2_POSITION__CURSOR2_Y_POSITION__SHIFT 0x0
++#define CUR2_POSITION__CURSOR2_X_POSITION_MASK 0x3fff0000
++#define CUR2_POSITION__CURSOR2_X_POSITION__SHIFT 0x10
++#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y_MASK 0x7f
++#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y__SHIFT 0x0
++#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X_MASK 0x7f0000
++#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X__SHIFT 0x10
++#define CUR2_COLOR1__CUR2_COLOR1_BLUE_MASK 0xff
++#define CUR2_COLOR1__CUR2_COLOR1_BLUE__SHIFT 0x0
++#define CUR2_COLOR1__CUR2_COLOR1_GREEN_MASK 0xff00
++#define CUR2_COLOR1__CUR2_COLOR1_GREEN__SHIFT 0x8
++#define CUR2_COLOR1__CUR2_COLOR1_RED_MASK 0xff0000
++#define CUR2_COLOR1__CUR2_COLOR1_RED__SHIFT 0x10
++#define CUR2_COLOR2__CUR2_COLOR2_BLUE_MASK 0xff
++#define CUR2_COLOR2__CUR2_COLOR2_BLUE__SHIFT 0x0
++#define CUR2_COLOR2__CUR2_COLOR2_GREEN_MASK 0xff00
++#define CUR2_COLOR2__CUR2_COLOR2_GREEN__SHIFT 0x8
++#define CUR2_COLOR2__CUR2_COLOR2_RED_MASK 0xff0000
++#define CUR2_COLOR2__CUR2_COLOR2_RED__SHIFT 0x10
++#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING_MASK 0x1
++#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING__SHIFT 0x0
++#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN_MASK 0x2
++#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN__SHIFT 0x1
++#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK_MASK 0x10000
++#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK__SHIFT 0x10
++#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE_MASK 0x6000000
++#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE__SHIFT 0x19
++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN_MASK 0x1
++#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN__SHIFT 0x0
++#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX_MASK 0x2
++#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX__SHIFT 0x1
++#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET_MASK 0x3ff0
++#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET__SHIFT 0x4
++#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET_MASK 0x3ff0000
++#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET__SHIFT 0x10
++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
++#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
++#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
++#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
++#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
++#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
++#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
++#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
++#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
++#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
++#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
++#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300
++#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0xf0
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
++#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
++#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
++#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70
++#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4
++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
++#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG_FE_CNTL__DIG_START_MASK 0x400
++#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x10000
++#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x10
++#define DIG_FE_CNTL__DIG_SWAP_MASK 0x40000
++#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x12
++#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x100000
++#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x14
++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4
++#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100
++#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8
++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
++#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
++#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
++#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
++#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
++#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
++#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
++#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
++#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
++#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
++#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
++#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
++#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
++#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
++#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
++#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
++#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
++#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
++#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
++#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
++#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
++#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
++#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
++#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
++#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10
++#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x4
++#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x300
++#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x8
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
++#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
++#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
++#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
++#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
++#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
++#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
++#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
++#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1
++#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0
++#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10
++#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa
++#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000
++#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc
++#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000
++#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10
++#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000
++#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11
++#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000
++#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12
++#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
++#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
++#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
++#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
++#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
++#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffff
++#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x0
++#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffff
++#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x0
++#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffff
++#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x0
++#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffff
++#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x0
++#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffff
++#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x0
++#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffff
++#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x0
++#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffff
++#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x0
++#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffff
++#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x0
++#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
++#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
++#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
++#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
++#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x1
++#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x0
++#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x2
++#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x1
++#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10
++#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x100
++#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1
++#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x0
++#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100
++#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8
++#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x10000
++#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x10
++#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x100000
++#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x1000000
++#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x18
++#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000
++#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x1c
++#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x1
++#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x0
++#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x2
++#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x1
++#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x10
++#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x100
++#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x1
++#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x0
++#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x100
++#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x8
++#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x10000
++#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x10
++#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x100000
++#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x1000000
++#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x18
++#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000
++#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x1c
++#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x1
++#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x0
++#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x2
++#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x1
++#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x10
++#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x100
++#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x1
++#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x0
++#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x100
++#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x8
++#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x10000
++#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x10
++#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x100000
++#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x1000000
++#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x18
++#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000
++#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x1c
++#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x1
++#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x0
++#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x2
++#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x1
++#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x10
++#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x100
++#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x1
++#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x0
++#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x100
++#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x8
++#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x10000
++#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x10
++#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x100000
++#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x1000000
++#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x18
++#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000
++#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x1c
++#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x1
++#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x0
++#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x2
++#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x1
++#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x10
++#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x100
++#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x1
++#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x0
++#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x100
++#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x8
++#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x10000
++#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x10
++#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x100000
++#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x1000000
++#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x18
++#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000
++#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x1c
++#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x1
++#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x0
++#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x2
++#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x1
++#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x10
++#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x100
++#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x1
++#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x0
++#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x100
++#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x8
++#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x10000
++#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x10
++#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x100000
++#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x1000000
++#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x18
++#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000
++#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x1c
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
++#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
++#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
++#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
++#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
++#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
++#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
++#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
++#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
++#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
++#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
++#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
++#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
++#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000
++#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
++#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
++#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
++#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
++#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x8000000
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x1b
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
++#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
++#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
++#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
++#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
++#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0xff
++#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x0
++#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffff
++#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x0
++#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffff
++#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x0
++#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffff
++#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x0
++#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffff
++#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x0
++#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffff
++#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x0
++#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffff
++#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x0
++#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffff
++#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x0
++#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffff
++#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x0
++#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffff
++#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x0
++#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J_MASK 0xffffffff
++#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J__SHIFT 0x0
++#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K_MASK 0xffffffff
++#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K__SHIFT 0x0
++#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L_MASK 0xffffffff
++#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L__SHIFT 0x0
++#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M_MASK 0xffffffff
++#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M__SHIFT 0x0
++#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N_MASK 0xffffffff
++#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N__SHIFT 0x0
++#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O_MASK 0xffffffff
++#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O__SHIFT 0x0
++#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P_MASK 0xffffffff
++#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P__SHIFT 0x0
++#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q__SHIFT 0x0
++#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffff
++#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x0
++#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffff
++#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x0
++#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffff
++#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x0
++#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffff
++#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x0
++#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffff
++#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x0
++#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffff
++#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x0
++#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffff
++#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x0
++#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffff
++#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x0
++#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffff
++#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x0
++#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J_MASK 0xffffffff
++#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J__SHIFT 0x0
++#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K_MASK 0xffffffff
++#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K__SHIFT 0x0
++#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L_MASK 0xffffffff
++#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L__SHIFT 0x0
++#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M_MASK 0xffffffff
++#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M__SHIFT 0x0
++#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N_MASK 0xffffffff
++#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N__SHIFT 0x0
++#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O_MASK 0xffffffff
++#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O__SHIFT 0x0
++#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P_MASK 0xffffffff
++#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P__SHIFT 0x0
++#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q__SHIFT 0x0
++#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffff
++#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x0
++#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffff
++#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x0
++#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffff
++#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x0
++#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffff
++#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x0
++#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffff
++#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x0
++#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffff
++#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x0
++#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffff
++#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x0
++#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffff
++#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x0
++#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffff
++#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x0
++#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J_MASK 0xffffffff
++#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J__SHIFT 0x0
++#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K_MASK 0xffffffff
++#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K__SHIFT 0x0
++#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L_MASK 0xffffffff
++#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L__SHIFT 0x0
++#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M_MASK 0xffffffff
++#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M__SHIFT 0x0
++#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N_MASK 0xffffffff
++#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N__SHIFT 0x0
++#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O_MASK 0xffffffff
++#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O__SHIFT 0x0
++#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P_MASK 0xffffffff
++#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P__SHIFT 0x0
++#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q__SHIFT 0x0
++#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffff
++#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x0
++#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffff
++#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x0
++#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffff
++#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x0
++#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffff
++#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x0
++#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffff
++#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x0
++#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffff
++#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x0
++#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffff
++#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x0
++#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffff
++#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x0
++#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffff
++#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x0
++#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J_MASK 0xffffffff
++#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J__SHIFT 0x0
++#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K_MASK 0xffffffff
++#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K__SHIFT 0x0
++#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L_MASK 0xffffffff
++#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L__SHIFT 0x0
++#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M_MASK 0xffffffff
++#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M__SHIFT 0x0
++#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N_MASK 0xffffffff
++#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N__SHIFT 0x0
++#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O_MASK 0xffffffff
++#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O__SHIFT 0x0
++#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P_MASK 0xffffffff
++#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P__SHIFT 0x0
++#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q__SHIFT 0x0
++#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffff
++#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x0
++#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffff
++#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x0
++#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffff
++#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x0
++#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffff
++#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x0
++#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffff
++#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x0
++#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffff
++#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x0
++#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffff
++#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x0
++#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffff
++#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x0
++#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffff
++#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x0
++#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J_MASK 0xffffffff
++#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J__SHIFT 0x0
++#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K_MASK 0xffffffff
++#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K__SHIFT 0x0
++#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L_MASK 0xffffffff
++#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L__SHIFT 0x0
++#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M_MASK 0xffffffff
++#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M__SHIFT 0x0
++#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N_MASK 0xffffffff
++#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N__SHIFT 0x0
++#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O_MASK 0xffffffff
++#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O__SHIFT 0x0
++#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P_MASK 0xffffffff
++#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P__SHIFT 0x0
++#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q__SHIFT 0x0
++#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffff
++#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x0
++#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffff
++#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x0
++#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffff
++#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x0
++#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffff
++#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x0
++#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffff
++#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x0
++#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffff
++#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x0
++#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffff
++#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x0
++#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffff
++#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x0
++#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffff
++#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x0
++#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J_MASK 0xffffffff
++#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J__SHIFT 0x0
++#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K_MASK 0xffffffff
++#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K__SHIFT 0x0
++#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L_MASK 0xffffffff
++#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L__SHIFT 0x0
++#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M_MASK 0xffffffff
++#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M__SHIFT 0x0
++#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N_MASK 0xffffffff
++#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N__SHIFT 0x0
++#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O_MASK 0xffffffff
++#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O__SHIFT 0x0
++#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P_MASK 0xffffffff
++#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P__SHIFT 0x0
++#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q__SHIFT 0x0
++#define DMCU_CTRL__RESET_UC_MASK 0x1
++#define DMCU_CTRL__RESET_UC__SHIFT 0x0
++#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
++#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
++#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
++#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x16
++#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
++#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
++#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
++#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
++#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
++#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
++#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00
++#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x1
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x2
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x4
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x8
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x20
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
++#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
++#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
++#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
++#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
++#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
++#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
++#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
++#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
++#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP_VID_N__DP_VID_N_MASK 0xffffff
++#define DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP_VID_M__DP_VID_M_MASK 0xffffff
++#define DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
++#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
++#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
++#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
++#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
++#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
++#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
++#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
++#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
++#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
++#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x1fff0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x1fff
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
++#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
++#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
++#define AUX_CONTROL__AUX_EN_MASK 0x1
++#define AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
++#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
++#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
++#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
++#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
++#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define AUX_CONTROL__SPARE_0_MASK 0x40000000
++#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define AUX_CONTROL__SPARE_1_MASK 0x80000000
++#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
++#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
++#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
++#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
++#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
++#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
++#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
++#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
++#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
++#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
++#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
++#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
++#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
++#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
++#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4
++#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
++#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
++#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
++#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
++#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
++#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
++#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
++#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
++#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
++#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
++#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
++#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
++#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
++#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
++#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
++#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
++#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
++#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
++#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
++#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
++#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
++#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
++#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
++#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
++#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
++#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
++#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
++#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
++#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
++#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
++#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
++#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
++#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
++#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
++#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
++#define FBC_CNTL__FBC_EN_MASK 0x80000000
++#define FBC_CNTL__FBC_EN__SHIFT 0x1f
++#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff
++#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
++#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
++#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
++#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
++#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
++#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
++#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
++#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
++#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
++#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
++#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
++#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
++#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
++#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
++#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
++#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
++#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
++#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff
++#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
++#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff
++#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
++#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff
++#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
++#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff
++#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
++#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff
++#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
++#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff
++#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
++#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff
++#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
++#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff
++#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
++#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff
++#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
++#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff
++#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
++#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff
++#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
++#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff
++#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
++#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff
++#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
++#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff
++#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
++#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff
++#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
++#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff
++#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
++#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
++#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
++#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
++#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
++#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
++#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
++#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
++#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
++#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
++#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
++#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
++#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
++#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
++#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
++#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x1c
++#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
++#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000
++#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000
++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11
++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000
++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12
++#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
++#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x10000
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x10
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0
++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
++#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x100
++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x8
++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
++#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
++#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
++#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
++#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
++#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
++#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
++#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
++#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
++#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
++#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
++#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
++#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
++#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
++#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
++#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
++#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
++#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
++#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
++#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
++#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
++#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
++#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
++#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
++#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
++#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
++#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
++#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
++#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
++#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
++#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
++#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
++#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
++#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
++#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
++#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
++#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
++#define MVP_CONTROL1__MVP_EN_MASK 0x1
++#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
++#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
++#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
++#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
++#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
++#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
++#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
++#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
++#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
++#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
++#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
++#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
++#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6
++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6
++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
++#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
++#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
++#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
++#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
++#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
++#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
++#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
++#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
++#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
++#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
++#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
++#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
++#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
++#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
++#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL_MODE__SCL_MODE_MASK 0x3
++#define SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
++#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
++#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
++#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
++#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
++#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
++#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
++#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
++#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
++#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
++#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
++#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
++#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
++#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_WT__VGA_RAM_EN_MASK 0x2
++#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_WT__VGA_CKSEL_MASK 0xc
++#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
++#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
++#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
++#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
++#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
++#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
++#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_RD__VGA_RAM_EN_MASK 0x2
++#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_RD__VGA_CKSEL_MASK 0xc
++#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
++#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
++#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
++#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
++#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
++#define GENENB__BLK_IO_BASE_MASK 0xff
++#define GENENB__BLK_IO_BASE__SHIFT 0x0
++#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
++#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
++#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
++#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
++#define GENS0__SENSE_SWITCH_MASK 0x10
++#define GENS0__SENSE_SWITCH__SHIFT 0x4
++#define GENS0__CRT_INTR_MASK 0x80
++#define GENS0__CRT_INTR__SHIFT 0x7
++#define GENS1__NO_DISPLAY_MASK 0x1
++#define GENS1__NO_DISPLAY__SHIFT 0x0
++#define GENS1__VGA_VSTATUS_MASK 0x8
++#define GENS1__VGA_VSTATUS__SHIFT 0x3
++#define GENS1__PIXEL_READ_BACK_MASK 0x30
++#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
++#define DAC_DATA__DAC_DATA_MASK 0x3f
++#define DAC_DATA__DAC_DATA__SHIFT 0x0
++#define DAC_MASK__DAC_MASK_MASK 0xff
++#define DAC_MASK__DAC_MASK__SHIFT 0x0
++#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
++#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
++#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
++#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
++#define SEQ8_IDX__SEQ_IDX_MASK 0x7
++#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
++#define SEQ8_DATA__SEQ_DATA_MASK 0xff
++#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
++#define SEQ00__SEQ_RST0B_MASK 0x1
++#define SEQ00__SEQ_RST0B__SHIFT 0x0
++#define SEQ00__SEQ_RST1B_MASK 0x2
++#define SEQ00__SEQ_RST1B__SHIFT 0x1
++#define SEQ01__SEQ_DOT8_MASK 0x1
++#define SEQ01__SEQ_DOT8__SHIFT 0x0
++#define SEQ01__SEQ_SHIFT2_MASK 0x4
++#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
++#define SEQ01__SEQ_PCLKBY2_MASK 0x8
++#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
++#define SEQ01__SEQ_SHIFT4_MASK 0x10
++#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
++#define SEQ01__SEQ_MAXBW_MASK 0x20
++#define SEQ01__SEQ_MAXBW__SHIFT 0x5
++#define SEQ02__SEQ_MAP0_EN_MASK 0x1
++#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
++#define SEQ02__SEQ_MAP1_EN_MASK 0x2
++#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
++#define SEQ02__SEQ_MAP2_EN_MASK 0x4
++#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
++#define SEQ02__SEQ_MAP3_EN_MASK 0x8
++#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B1_MASK 0x1
++#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
++#define SEQ03__SEQ_FONT_B2_MASK 0x2
++#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
++#define SEQ03__SEQ_FONT_A1_MASK 0x4
++#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
++#define SEQ03__SEQ_FONT_A2_MASK 0x8
++#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B0_MASK 0x10
++#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
++#define SEQ03__SEQ_FONT_A0_MASK 0x20
++#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
++#define SEQ04__SEQ_256K_MASK 0x2
++#define SEQ04__SEQ_256K__SHIFT 0x1
++#define SEQ04__SEQ_ODDEVEN_MASK 0x4
++#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
++#define SEQ04__SEQ_CHAIN_MASK 0x8
++#define SEQ04__SEQ_CHAIN__SHIFT 0x3
++#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
++#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
++#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
++#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
++#define CRT00__H_TOTAL_MASK 0xff
++#define CRT00__H_TOTAL__SHIFT 0x0
++#define CRT01__H_DISP_END_MASK 0xff
++#define CRT01__H_DISP_END__SHIFT 0x0
++#define CRT02__H_BLANK_START_MASK 0xff
++#define CRT02__H_BLANK_START__SHIFT 0x0
++#define CRT03__H_BLANK_END_MASK 0x1f
++#define CRT03__H_BLANK_END__SHIFT 0x0
++#define CRT03__H_DE_SKEW_MASK 0x60
++#define CRT03__H_DE_SKEW__SHIFT 0x5
++#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
++#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
++#define CRT04__H_SYNC_START_MASK 0xff
++#define CRT04__H_SYNC_START__SHIFT 0x0
++#define CRT05__H_SYNC_END_MASK 0x1f
++#define CRT05__H_SYNC_END__SHIFT 0x0
++#define CRT05__H_SYNC_SKEW_MASK 0x60
++#define CRT05__H_SYNC_SKEW__SHIFT 0x5
++#define CRT05__H_BLANK_END_B5_MASK 0x80
++#define CRT05__H_BLANK_END_B5__SHIFT 0x7
++#define CRT06__V_TOTAL_MASK 0xff
++#define CRT06__V_TOTAL__SHIFT 0x0
++#define CRT07__V_TOTAL_B8_MASK 0x1
++#define CRT07__V_TOTAL_B8__SHIFT 0x0
++#define CRT07__V_DISP_END_B8_MASK 0x2
++#define CRT07__V_DISP_END_B8__SHIFT 0x1
++#define CRT07__V_SYNC_START_B8_MASK 0x4
++#define CRT07__V_SYNC_START_B8__SHIFT 0x2
++#define CRT07__V_BLANK_START_B8_MASK 0x8
++#define CRT07__V_BLANK_START_B8__SHIFT 0x3
++#define CRT07__LINE_CMP_B8_MASK 0x10
++#define CRT07__LINE_CMP_B8__SHIFT 0x4
++#define CRT07__V_TOTAL_B9_MASK 0x20
++#define CRT07__V_TOTAL_B9__SHIFT 0x5
++#define CRT07__V_DISP_END_B9_MASK 0x40
++#define CRT07__V_DISP_END_B9__SHIFT 0x6
++#define CRT07__V_SYNC_START_B9_MASK 0x80
++#define CRT07__V_SYNC_START_B9__SHIFT 0x7
++#define CRT08__ROW_SCAN_START_MASK 0x1f
++#define CRT08__ROW_SCAN_START__SHIFT 0x0
++#define CRT08__BYTE_PAN_MASK 0x60
++#define CRT08__BYTE_PAN__SHIFT 0x5
++#define CRT09__MAX_ROW_SCAN_MASK 0x1f
++#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
++#define CRT09__V_BLANK_START_B9_MASK 0x20
++#define CRT09__V_BLANK_START_B9__SHIFT 0x5
++#define CRT09__LINE_CMP_B9_MASK 0x40
++#define CRT09__LINE_CMP_B9__SHIFT 0x6
++#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
++#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
++#define CRT0A__CURSOR_START_MASK 0x1f
++#define CRT0A__CURSOR_START__SHIFT 0x0
++#define CRT0A__CURSOR_DISABLE_MASK 0x20
++#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
++#define CRT0B__CURSOR_END_MASK 0x1f
++#define CRT0B__CURSOR_END__SHIFT 0x0
++#define CRT0B__CURSOR_SKEW_MASK 0x60
++#define CRT0B__CURSOR_SKEW__SHIFT 0x5
++#define CRT0C__DISP_START_MASK 0xff
++#define CRT0C__DISP_START__SHIFT 0x0
++#define CRT0D__DISP_START_MASK 0xff
++#define CRT0D__DISP_START__SHIFT 0x0
++#define CRT0E__CURSOR_LOC_HI_MASK 0xff
++#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
++#define CRT0F__CURSOR_LOC_LO_MASK 0xff
++#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
++#define CRT10__V_SYNC_START_MASK 0xff
++#define CRT10__V_SYNC_START__SHIFT 0x0
++#define CRT11__V_SYNC_END_MASK 0xf
++#define CRT11__V_SYNC_END__SHIFT 0x0
++#define CRT11__V_INTR_CLR_MASK 0x10
++#define CRT11__V_INTR_CLR__SHIFT 0x4
++#define CRT11__V_INTR_EN_MASK 0x20
++#define CRT11__V_INTR_EN__SHIFT 0x5
++#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
++#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
++#define CRT11__C0T7_WR_ONLY_MASK 0x80
++#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
++#define CRT12__V_DISP_END_MASK 0xff
++#define CRT12__V_DISP_END__SHIFT 0x0
++#define CRT13__DISP_PITCH_MASK 0xff
++#define CRT13__DISP_PITCH__SHIFT 0x0
++#define CRT14__UNDRLN_LOC_MASK 0x1f
++#define CRT14__UNDRLN_LOC__SHIFT 0x0
++#define CRT14__ADDR_CNT_BY4_MASK 0x20
++#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
++#define CRT14__DOUBLE_WORD_MASK 0x40
++#define CRT14__DOUBLE_WORD__SHIFT 0x6
++#define CRT15__V_BLANK_START_MASK 0xff
++#define CRT15__V_BLANK_START__SHIFT 0x0
++#define CRT16__V_BLANK_END_MASK 0xff
++#define CRT16__V_BLANK_END__SHIFT 0x0
++#define CRT17__RA0_AS_A13B_MASK 0x1
++#define CRT17__RA0_AS_A13B__SHIFT 0x0
++#define CRT17__RA1_AS_A14B_MASK 0x2
++#define CRT17__RA1_AS_A14B__SHIFT 0x1
++#define CRT17__VCOUNT_BY2_MASK 0x4
++#define CRT17__VCOUNT_BY2__SHIFT 0x2
++#define CRT17__ADDR_CNT_BY2_MASK 0x8
++#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
++#define CRT17__WRAP_A15TOA0_MASK 0x20
++#define CRT17__WRAP_A15TOA0__SHIFT 0x5
++#define CRT17__BYTE_MODE_MASK 0x40
++#define CRT17__BYTE_MODE__SHIFT 0x6
++#define CRT17__CRTC_SYNC_EN_MASK 0x80
++#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
++#define CRT18__LINE_CMP_MASK 0xff
++#define CRT18__LINE_CMP__SHIFT 0x0
++#define CRT1E__GRPH_DEC_RD1_MASK 0x2
++#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
++#define CRT1F__GRPH_DEC_RD0_MASK 0xff
++#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
++#define CRT22__GRPH_LATCH_DATA_MASK 0xff
++#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
++#define GRPH8_IDX__GRPH_IDX_MASK 0xf
++#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
++#define GRPH8_DATA__GRPH_DATA_MASK 0xff
++#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET0_MASK 0x1
++#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET1_MASK 0x2
++#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
++#define GRA00__GRPH_SET_RESET2_MASK 0x4
++#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
++#define GRA00__GRPH_SET_RESET3_MASK 0x8
++#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
++#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
++#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
++#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
++#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
++#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
++#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
++#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
++#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
++#define GRA02__GRPH_CCOMP_MASK 0xf
++#define GRA02__GRPH_CCOMP__SHIFT 0x0
++#define GRA03__GRPH_ROTATE_MASK 0x7
++#define GRA03__GRPH_ROTATE__SHIFT 0x0
++#define GRA03__GRPH_FN_SEL_MASK 0x18
++#define GRA03__GRPH_FN_SEL__SHIFT 0x3
++#define GRA04__GRPH_RMAP_MASK 0x3
++#define GRA04__GRPH_RMAP__SHIFT 0x0
++#define GRA05__GRPH_WRITE_MODE_MASK 0x3
++#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
++#define GRA05__GRPH_READ1_MASK 0x8
++#define GRA05__GRPH_READ1__SHIFT 0x3
++#define GRA05__CGA_ODDEVEN_MASK 0x10
++#define GRA05__CGA_ODDEVEN__SHIFT 0x4
++#define GRA05__GRPH_OES_MASK 0x20
++#define GRA05__GRPH_OES__SHIFT 0x5
++#define GRA05__GRPH_PACK_MASK 0x40
++#define GRA05__GRPH_PACK__SHIFT 0x6
++#define GRA06__GRPH_GRAPHICS_MASK 0x1
++#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
++#define GRA06__GRPH_ODDEVEN_MASK 0x2
++#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
++#define GRA06__GRPH_ADRSEL_MASK 0xc
++#define GRA06__GRPH_ADRSEL__SHIFT 0x2
++#define GRA07__GRPH_XCARE0_MASK 0x1
++#define GRA07__GRPH_XCARE0__SHIFT 0x0
++#define GRA07__GRPH_XCARE1_MASK 0x2
++#define GRA07__GRPH_XCARE1__SHIFT 0x1
++#define GRA07__GRPH_XCARE2_MASK 0x4
++#define GRA07__GRPH_XCARE2__SHIFT 0x2
++#define GRA07__GRPH_XCARE3_MASK 0x8
++#define GRA07__GRPH_XCARE3__SHIFT 0x3
++#define GRA08__GRPH_BMSK_MASK 0xff
++#define GRA08__GRPH_BMSK__SHIFT 0x0
++#define ATTRX__ATTR_IDX_MASK 0x1f
++#define ATTRX__ATTR_IDX__SHIFT 0x0
++#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
++#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
++#define ATTRDW__ATTR_DATA_MASK 0xff
++#define ATTRDW__ATTR_DATA__SHIFT 0x0
++#define ATTRDR__ATTR_DATA_MASK 0xff
++#define ATTRDR__ATTR_DATA__SHIFT 0x0
++#define ATTR00__ATTR_PAL_MASK 0x3f
++#define ATTR00__ATTR_PAL__SHIFT 0x0
++#define ATTR01__ATTR_PAL_MASK 0x3f
++#define ATTR01__ATTR_PAL__SHIFT 0x0
++#define ATTR02__ATTR_PAL_MASK 0x3f
++#define ATTR02__ATTR_PAL__SHIFT 0x0
++#define ATTR03__ATTR_PAL_MASK 0x3f
++#define ATTR03__ATTR_PAL__SHIFT 0x0
++#define ATTR04__ATTR_PAL_MASK 0x3f
++#define ATTR04__ATTR_PAL__SHIFT 0x0
++#define ATTR05__ATTR_PAL_MASK 0x3f
++#define ATTR05__ATTR_PAL__SHIFT 0x0
++#define ATTR06__ATTR_PAL_MASK 0x3f
++#define ATTR06__ATTR_PAL__SHIFT 0x0
++#define ATTR07__ATTR_PAL_MASK 0x3f
++#define ATTR07__ATTR_PAL__SHIFT 0x0
++#define ATTR08__ATTR_PAL_MASK 0x3f
++#define ATTR08__ATTR_PAL__SHIFT 0x0
++#define ATTR09__ATTR_PAL_MASK 0x3f
++#define ATTR09__ATTR_PAL__SHIFT 0x0
++#define ATTR0A__ATTR_PAL_MASK 0x3f
++#define ATTR0A__ATTR_PAL__SHIFT 0x0
++#define ATTR0B__ATTR_PAL_MASK 0x3f
++#define ATTR0B__ATTR_PAL__SHIFT 0x0
++#define ATTR0C__ATTR_PAL_MASK 0x3f
++#define ATTR0C__ATTR_PAL__SHIFT 0x0
++#define ATTR0D__ATTR_PAL_MASK 0x3f
++#define ATTR0D__ATTR_PAL__SHIFT 0x0
++#define ATTR0E__ATTR_PAL_MASK 0x3f
++#define ATTR0E__ATTR_PAL__SHIFT 0x0
++#define ATTR0F__ATTR_PAL_MASK 0x3f
++#define ATTR0F__ATTR_PAL__SHIFT 0x0
++#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
++#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
++#define ATTR10__ATTR_MONO_EN_MASK 0x2
++#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
++#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
++#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
++#define ATTR10__ATTR_BLINK_EN_MASK 0x8
++#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
++#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
++#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
++#define ATTR10__ATTR_PCLKBY2_MASK 0x40
++#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
++#define ATTR10__ATTR_CSEL_EN_MASK 0x80
++#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
++#define ATTR11__ATTR_OVSC_MASK 0xff
++#define ATTR11__ATTR_OVSC__SHIFT 0x0
++#define ATTR12__ATTR_MAP_EN_MASK 0xf
++#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
++#define ATTR12__ATTR_VSMUX_MASK 0x30
++#define ATTR12__ATTR_VSMUX__SHIFT 0x4
++#define ATTR13__ATTR_PPAN_MASK 0xf
++#define ATTR13__ATTR_PPAN__SHIFT 0x0
++#define ATTR14__ATTR_CSEL1_MASK 0x3
++#define ATTR14__ATTR_CSEL1__SHIFT 0x0
++#define ATTR14__ATTR_CSEL2_MASK 0xc
++#define ATTR14__ATTR_CSEL2__SHIFT 0x2
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
++#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
++#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
++#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
++#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
++#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
++#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
++#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
++#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffff
++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
++#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
++#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
++#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
++#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
++#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
++#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
++#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
++#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
++#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK 0x1
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK 0x2
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE_MASK 0x4
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE_MASK 0x8
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE_MASK 0x10
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE_MASK 0x20
++#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
++#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK 0x1
++#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
++#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK 0x2
++#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
++#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS_MASK 0x4
++#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
++#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS_MASK 0x8
++#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
++#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS_MASK 0x10
++#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
++#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS_MASK 0x20
++#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
++#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_MASK 0x3
++#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
++#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
++#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
++#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
++#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
++#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
++#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
++#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
++#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
++#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
++#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
++#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define BLND_CONTROL__BLND_MODE_MASK 0x300
++#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
++#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
++#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
++#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define SM_CONTROL2__SM_MODE_MASK 0x7
++#define SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
++#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
++#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
++#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
++#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
++#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define PTI_CONTROL__PTI_ENABLE_MASK 0x1
++#define PTI_CONTROL__PTI_ENABLE__SHIFT 0x0
++#define PTI_CONTROL__PTI_NEW_PIXEL_GAP_MASK 0x30
++#define PTI_CONTROL__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define PTI_CONTROL__BLND_NEW_PIXEL_MODE_MASK 0x40
++#define PTI_CONTROL__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
++#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
++#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
++#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100
++#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING_MASK 0x1
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK 0x2
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING_MASK 0x4
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING_MASK 0x8
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING_MASK 0x10
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING__SHIFT 0x4
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING_MASK 0x20
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING__SHIFT 0x5
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING_MASK 0x40
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING_MASK 0x80
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING_MASK 0x100
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING__SHIFT 0x8
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING_MASK 0x200
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING__SHIFT 0x9
++#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
++#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
++#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
++#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
++#define SI_ENABLE__SI_ENABLE_MASK 0x1
++#define SI_ENABLE__SI_ENABLE__SHIFT 0x0
++#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS_MASK 0x1
++#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS__SHIFT 0x0
++#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS_MASK 0x2
++#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS__SHIFT 0x1
++#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS_MASK 0x4
++#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS__SHIFT 0x2
++#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS_MASK 0x8
++#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS__SHIFT 0x3
++#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS_MASK 0x10
++#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS__SHIFT 0x4
++#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS_MASK 0x20
++#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS__SHIFT 0x5
++#define SI_EC_CONFIG__SI_LB_LS_DIS_MASK 0x40
++#define SI_EC_CONFIG__SI_LB_LS_DIS__SHIFT 0x6
++#define SI_EC_CONFIG__SI_LB_SD_DIS_MASK 0x80
++#define SI_EC_CONFIG__SI_LB_SD_DIS__SHIFT 0x7
++#define SI_EC_CONFIG__SI_LUT_LS_DIS_MASK 0x100
++#define SI_EC_CONFIG__SI_LUT_LS_DIS__SHIFT 0x8
++#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL_MASK 0xf000
++#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL__SHIFT 0xc
++#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE_MASK 0x800000
++#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE__SHIFT 0x17
++#define SI_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
++#define SI_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
++#define SI_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
++#define SI_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
++#define CNV_MODE__CNV_INPUT_SRC_SELECT_MASK 0x3
++#define CNV_MODE__CNV_INPUT_SRC_SELECT__SHIFT 0x0
++#define CNV_MODE__CNV_INPUT_PIPE_SELECT_MASK 0x1c
++#define CNV_MODE__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
++#define CNV_MODE__CNV_FRAME_COUNT_MASK 0x300
++#define CNV_MODE__CNV_FRAME_COUNT__SHIFT 0x8
++#define CNV_MODE__CNV_WINDOW_EN_MASK 0x1000
++#define CNV_MODE__CNV_WINDOW_EN__SHIFT 0xc
++#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
++#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
++#define CNV_MODE__CNV_STEREO_EYE_ORDER_MASK 0x40000
++#define CNV_MODE__CNV_STEREO_EYE_ORDER__SHIFT 0x12
++#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
++#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
++#define CNV_MODE__CNV_FRAME_EN_MASK 0x80000000
++#define CNV_MODE__CNV_FRAME_EN__SHIFT 0x1f
++#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
++#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
++#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
++#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
++#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
++#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
++#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
++#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
++#define CNV_CSC_CONTROL__CNV_CSC_bypass_MASK 0x1
++#define CNV_CSC_CONTROL__CNV_CSC_bypass__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
++#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
++#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
++#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
++#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
++#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
++#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
++#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
++#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
++#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
++#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
++#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
++#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
++#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
++#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
++#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
++#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
++#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
++#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
++#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
++#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
++#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
++#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xffff
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x0
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xffff
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x0
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xffff
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x0
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
++#define SI_DEBUG_CTRL__SI_DEBUG_SEL_MASK 0x3
++#define SI_DEBUG_CTRL__SI_DEBUG_SEL__SHIFT 0x0
++#define SI_DBG_MODE__SI_DBG_MODE_EN_MASK 0x1
++#define SI_DBG_MODE__SI_DBG_MODE_EN__SHIFT 0x0
++#define SI_DBG_MODE__SI_DBG_DIN_FMT_MASK 0x2
++#define SI_DBG_MODE__SI_DBG_DIN_FMT__SHIFT 0x1
++#define SI_DBG_MODE__SI_DBG_36MODE_MASK 0x4
++#define SI_DBG_MODE__SI_DBG_36MODE__SHIFT 0x2
++#define SI_DBG_MODE__SI_DBG_CMAP_MASK 0x8
++#define SI_DBG_MODE__SI_DBG_CMAP__SHIFT 0x3
++#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR_MASK 0x100
++#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR__SHIFT 0x8
++#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH_MASK 0x7fff0000
++#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH__SHIFT 0x10
++#define SI_HARD_DEBUG__SI_HARD_DEBUG_MASK 0xffffffff
++#define SI_HARD_DEBUG__SI_HARD_DEBUG__SHIFT 0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
++#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x7
++#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE_MASK 0xf00
++#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE__SHIFT 0x8
++#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE_MASK 0x30000
++#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x3fff
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
++#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SISCL_MODE__SISCL_MODE_MASK 0x3
++#define SISCL_MODE__SISCL_MODE__SHIFT 0x0
++#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB_MASK 0xf
++#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0
++#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR_MASK 0xf0
++#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4
++#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB_MASK 0xf00
++#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8
++#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR_MASK 0xf000
++#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc
++#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT_MASK 0x7fff
++#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT__SHIFT 0x0
++#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH_MASK 0x7fff0000
++#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH__SHIFT 0x10
++#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO_MASK 0x7ffffff
++#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO__SHIFT 0x0
++#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB_MASK 0xffffff
++#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0
++#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB_MASK 0x1f000000
++#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB__SHIFT 0x18
++#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR_MASK 0xffffff
++#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR__SHIFT 0x0
++#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR_MASK 0x1f000000
++#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR__SHIFT 0x18
++#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO_MASK 0x7ffffff
++#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO__SHIFT 0x0
++#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB_MASK 0xffffff
++#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0
++#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB_MASK 0x1f000000
++#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB__SHIFT 0x18
++#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR_MASK 0xffffff
++#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR__SHIFT 0x0
++#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR_MASK 0x1f000000
++#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR__SHIFT 0x18
++#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB_MASK 0xffff
++#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0
++#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
++#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB_MASK 0xff
++#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0
++#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB_MASK 0xff00
++#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8
++#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR_MASK 0xff0000
++#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR__SHIFT 0x10
++#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR_MASK 0xff000000
++#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR__SHIFT 0x18
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG_MASK 0x1
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG__SHIFT 0x0
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK_MASK 0x100
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK__SHIFT 0x8
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK_MASK 0x1000
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK__SHIFT 0xc
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS_MASK 0x10000
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE_MASK 0x100000
++#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG_MASK 0x1
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK_MASK 0x100
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK_MASK 0x1000
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE_MASK 0x100000
++#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY_MASK 0x1
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB_MASK 0xff00
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB__SHIFT 0x8
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y_MASK 0xff0000
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y__SHIFT 0x10
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR_MASK 0xff000000
++#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR__SHIFT 0x18
++#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN_MASK 0x10
++#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN__SHIFT 0x4
++#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN_MASK 0x100
++#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN__SHIFT 0x8
++#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY_MASK 0x10000
++#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY__SHIFT 0x10
++#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK_MASK 0xffff
++#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK__SHIFT 0x0
++#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED_MASK 0xffff0000
++#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED__SHIFT 0x10
++#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK_MASK 0xffff
++#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK__SHIFT 0x0
++#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN_MASK 0xffff0000
++#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN__SHIFT 0x10
++#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK_MASK 0xffff
++#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK__SHIFT 0x0
++#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE_MASK 0xffff0000
++#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE__SHIFT 0x10
++#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN_MASK 0x1
++#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN__SHIFT 0x0
++#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE_MASK 0xffff
++#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0
++#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE_MASK 0xffff0000
++#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10
++#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX_MASK 0xff
++#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX__SHIFT 0x0
++#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA_MASK 0xffffffff
++#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
++#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x1000
++#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0xc
++#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x2000
++#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0xd
++#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x4000
++#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0xe
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x1
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x100
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x8
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x10000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x10
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x1000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x18
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x1e
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
++#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
++#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
++
++#endif /* DCE_8_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0004-yocto-amd-temperature-monitoring-support-for-F15h-M60h-processor.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0004-yocto-amd-temperature-monitoring-support-for-F15h-M60h-processor.patch
new file mode 100644
index 00000000..4036d5b5
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0004-yocto-amd-temperature-monitoring-support-for-F15h-M60h-processor.patch
@@ -0,0 +1,94 @@
+This patch adds temperature monitoring support for F15h M60h processor.
+ - Add new pci device id for the relevant processor
+ - The functionality of REG_REPORTED_TEMPERATURE is moved to
+   D0F0xBC_xD820_0CA4 [Reported Temperature Control]
+   - So, use this to get CUR_TEMP value
+   - Since we need an indirect register access, protect this with
+     a mutex lock
+ - Add Kconfig, Doc entries to indicate support for this processor.
+
+Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
+Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com>
+diff -Naur a/Documentation/hwmon/k10temp b/Documentation/hwmon/k10temp
+--- a/Documentation/hwmon/k10temp	2014-11-20 06:57:23.314425285 +0530
++++ b/Documentation/hwmon/k10temp	2014-11-20 06:59:21.794427609 +0530
+@@ -11,7 +11,7 @@
+   Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
+ * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
+ * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
+-* AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity"
++* AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Carrizo"
+ * AMD Family 16h processors: "Kabini"
+ 
+   Prefix: 'k10temp'
+diff -Naur a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+--- a/drivers/hwmon/k10temp.c	2014-11-20 06:57:25.386425326 +0530
++++ b/drivers/hwmon/k10temp.c	2014-11-20 07:10:20.450440524 +0530
+@@ -33,6 +33,9 @@
+ module_param(force, bool, 0444);
+ MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
+ 
++/* Provide lock for writing to NB_SMU_IND_ADDR */
++DEFINE_MUTEX(nb_smu_ind_mutex);
++
+ /* CPUID function 0x80000001, ebx */
+ #define CPUID_PKGTYPE_MASK	0xf0000000
+ #define CPUID_PKGTYPE_F		0x00000000
+@@ -51,13 +54,41 @@
+ #define REG_NORTHBRIDGE_CAPABILITIES	0xe8
+ #define  NB_CAP_HTC			0x00000400
+ 
++/*
++* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
++* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
++* Control]
++*/
++#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4
++#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3	0x1573
++
++void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
++			   int offset, u32 *val)
++{
++	mutex_lock(&nb_smu_ind_mutex);
++	pci_bus_write_config_dword(pdev->bus, devfn,
++				   0xb8, offset);
++	pci_bus_read_config_dword(pdev->bus, devfn,
++				  0xbc, val);
++	mutex_unlock(&nb_smu_ind_mutex);
++}
++
++
++
+ static ssize_t show_temp(struct device *dev,
+ 			 struct device_attribute *attr, char *buf)
+ {
+ 	u32 regval;
+ 
+-	pci_read_config_dword(to_pci_dev(dev),
+-			      REG_REPORTED_TEMPERATURE, &regval);
++	struct pci_dev *pdev = to_pci_dev(dev);
++
++	if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
++		amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
++					F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
++					&regval);
++	} else {
++		pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
++	}
+ 	return sprintf(buf, "%u\n", (regval >> 21) * 125);
+ }
+ 
+diff -Naur a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
+--- a/drivers/hwmon/Kconfig	2014-11-20 06:57:25.382425326 +0530
++++ b/drivers/hwmon/Kconfig	2014-11-20 07:01:10.974429749 +0530
+@@ -296,8 +296,8 @@
+ 	  If you say yes here you get support for the temperature
+ 	  sensor(s) inside your CPU. Supported are later revisions of
+ 	  the AMD Family 10h and all revisions of the AMD Family 11h,
+-	  12h (Llano), 14h (Brazos), 15h (Bulldozer/Trinity) and
+-	  16h (Kabini) microarchitectures.
++	  12h (Llano), 14h (Brazos), 15h (Bulldozer/Trinity/Carrizo)
++	  and 16h (Kabini) microarchitectures.
+ 
+ 	  This driver can also be built as a module.  If so, the module
+ 	  will be called k10temp.
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0005-yocto-amd-drm-amdgpu-Do-not-directly-dereference-pointers-to-BIOS-area.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0005-yocto-amd-drm-amdgpu-Do-not-directly-dereference-pointers-to-BIOS-area.patch
new file mode 100644
index 00000000..ac394b94
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0005-yocto-amd-drm-amdgpu-Do-not-directly-dereference-pointers-to-BIOS-area.patch
@@ -0,0 +1,25802 @@
+From 2f1130657501a6053ed8c3af4c7cfc06c5ccd821 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:17:56 -0400
+Subject: drm/amdgpu: add DCE 10.0 register headers
+
+These are register headers for the DCE (Display and Composition Engine)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h
+new file mode 100644
+index 0000000..95570db
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h
+@@ -0,0 +1,7350 @@
++/*
++ * DCE_10_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_10_0_D_H
++#define DCE_10_0_D_H
++
++#define mmPIPE0_PG_CONFIG                                                       0x2c0
++#define mmPIPE0_PG_ENABLE                                                       0x2c1
++#define mmPIPE0_PG_STATUS                                                       0x2c2
++#define mmPIPE1_PG_CONFIG                                                       0x2c3
++#define mmPIPE1_PG_ENABLE                                                       0x2c4
++#define mmPIPE1_PG_STATUS                                                       0x2c5
++#define mmPIPE2_PG_CONFIG                                                       0x2c6
++#define mmPIPE2_PG_ENABLE                                                       0x2c7
++#define mmPIPE2_PG_STATUS                                                       0x2c8
++#define mmPIPE3_PG_CONFIG                                                       0x2c9
++#define mmPIPE3_PG_ENABLE                                                       0x2ca
++#define mmPIPE3_PG_STATUS                                                       0x2cb
++#define mmPIPE4_PG_CONFIG                                                       0x2cc
++#define mmPIPE4_PG_ENABLE                                                       0x2cd
++#define mmPIPE4_PG_STATUS                                                       0x2ce
++#define mmPIPE5_PG_CONFIG                                                       0x2cf
++#define mmPIPE5_PG_ENABLE                                                       0x2d0
++#define mmPIPE5_PG_STATUS                                                       0x2d1
++#define mmDC_IP_REQUEST_CNTL                                                    0x2d2
++#define mmDC_PGFSM_CONFIG_REG                                                   0x2d3
++#define mmDC_PGFSM_WRITE_REG                                                    0x2d4
++#define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
++#define mmDCPG_TEST_DEBUG_INDEX                                                 0x2d6
++#define mmDCPG_TEST_DEBUG_DATA                                                  0x2d7
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                           0x1628
++#define mmBL1_PWM_USER_LEVEL                                                    0x1629
++#define mmBL1_PWM_TARGET_ABM_LEVEL                                              0x162a
++#define mmBL1_PWM_CURRENT_ABM_LEVEL                                             0x162b
++#define mmBL1_PWM_FINAL_DUTY_CYCLE                                              0x162c
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                            0x162d
++#define mmBL1_PWM_ABM_CNTL                                                      0x162e
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
++#define mmBL1_PWM_GRP2_REG_LOCK                                                 0x1630
++#define mmDC_ABM1_CNTL                                                          0x1638
++#define mmDC_ABM1_IPCSC_COEFF_SEL                                               0x1639
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                            0x163a
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                            0x163b
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                            0x163c
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                            0x163d
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                            0x163e
++#define mmDC_ABM1_ACE_THRES_12                                                  0x163f
++#define mmDC_ABM1_ACE_THRES_34                                                  0x1640
++#define mmDC_ABM1_ACE_CNTL_MISC                                                 0x1641
++#define mmDC_ABM1_DEBUG_MISC                                                    0x1649
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                        0x164a
++#define mmDC_ABM1_HG_MISC_CTRL                                                  0x164b
++#define mmDC_ABM1_LS_SUM_OF_LUMA                                                0x164c
++#define mmDC_ABM1_LS_MIN_MAX_LUMA                                               0x164d
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                      0x164e
++#define mmDC_ABM1_LS_PIXEL_COUNT                                                0x164f
++#define mmDC_ABM1_LS_OVR_SCAN_BIN                                               0x1650
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                  0x1651
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                      0x1652
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                      0x1653
++#define mmDC_ABM1_HG_SAMPLE_RATE                                                0x1654
++#define mmDC_ABM1_LS_SAMPLE_RATE                                                0x1655
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                        0x1656
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                        0x1657
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                       0x1658
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                      0x1659
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                      0x165a
++#define mmDC_ABM1_HG_RESULT_1                                                   0x165b
++#define mmDC_ABM1_HG_RESULT_2                                                   0x165c
++#define mmDC_ABM1_HG_RESULT_3                                                   0x165d
++#define mmDC_ABM1_HG_RESULT_4                                                   0x165e
++#define mmDC_ABM1_HG_RESULT_5                                                   0x165f
++#define mmDC_ABM1_HG_RESULT_6                                                   0x1660
++#define mmDC_ABM1_HG_RESULT_7                                                   0x1661
++#define mmDC_ABM1_HG_RESULT_8                                                   0x1662
++#define mmDC_ABM1_HG_RESULT_9                                                   0x1663
++#define mmDC_ABM1_HG_RESULT_10                                                  0x1664
++#define mmDC_ABM1_HG_RESULT_11                                                  0x1665
++#define mmDC_ABM1_HG_RESULT_12                                                  0x1666
++#define mmDC_ABM1_HG_RESULT_13                                                  0x1667
++#define mmDC_ABM1_HG_RESULT_14                                                  0x1668
++#define mmDC_ABM1_HG_RESULT_15                                                  0x1669
++#define mmDC_ABM1_HG_RESULT_16                                                  0x166a
++#define mmDC_ABM1_HG_RESULT_17                                                  0x166b
++#define mmDC_ABM1_HG_RESULT_18                                                  0x166c
++#define mmDC_ABM1_HG_RESULT_19                                                  0x166d
++#define mmDC_ABM1_HG_RESULT_20                                                  0x166e
++#define mmDC_ABM1_HG_RESULT_21                                                  0x166f
++#define mmDC_ABM1_HG_RESULT_22                                                  0x1670
++#define mmDC_ABM1_HG_RESULT_23                                                  0x1671
++#define mmDC_ABM1_HG_RESULT_24                                                  0x1672
++#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                          0x169b
++#define mmDC_ABM1_BL_MASTER_LOCK                                                0x169c
++#define mmABM_TEST_DEBUG_INDEX                                                  0x169e
++#define mmABM_TEST_DEBUG_DATA                                                   0x169f
++#define mmCRTC_DCFE_CLOCK_CONTROL                                               0x1b7c
++#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL                                         0x1b7c
++#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL                                         0x1d7c
++#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL                                         0x1f7c
++#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL                                         0x417c
++#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL                                         0x437c
++#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL                                         0x457c
++#define mmCRTC6_CRTC_DCFE_CLOCK_CONTROL                                         0x477c
++#define mmCRTC_H_BLANK_EARLY_NUM                                                0x1b7d
++#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                          0x1b7d
++#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                          0x1d7d
++#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                          0x1f7d
++#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                          0x417d
++#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                          0x437d
++#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                          0x457d
++#define mmCRTC6_CRTC_H_BLANK_EARLY_NUM                                          0x477d
++#define mmDCFE_DBG_SEL                                                          0x1b7e
++#define mmCRTC0_DCFE_DBG_SEL                                                    0x1b7e
++#define mmCRTC1_DCFE_DBG_SEL                                                    0x1d7e
++#define mmCRTC2_DCFE_DBG_SEL                                                    0x1f7e
++#define mmCRTC3_DCFE_DBG_SEL                                                    0x417e
++#define mmCRTC4_DCFE_DBG_SEL                                                    0x437e
++#define mmCRTC5_DCFE_DBG_SEL                                                    0x457e
++#define mmCRTC6_DCFE_DBG_SEL                                                    0x477e
++#define mmDCFE_MEM_PWR_CTRL                                                     0x1b7f
++#define mmCRTC0_DCFE_MEM_PWR_CTRL                                               0x1b7f
++#define mmCRTC1_DCFE_MEM_PWR_CTRL                                               0x1d7f
++#define mmCRTC2_DCFE_MEM_PWR_CTRL                                               0x1f7f
++#define mmCRTC3_DCFE_MEM_PWR_CTRL                                               0x417f
++#define mmCRTC4_DCFE_MEM_PWR_CTRL                                               0x437f
++#define mmCRTC5_DCFE_MEM_PWR_CTRL                                               0x457f
++#define mmCRTC6_DCFE_MEM_PWR_CTRL                                               0x477f
++#define mmDCFE_MEM_PWR_CTRL2                                                    0x1bb8
++#define mmCRTC0_DCFE_MEM_PWR_CTRL2                                              0x1bb8
++#define mmCRTC1_DCFE_MEM_PWR_CTRL2                                              0x1db8
++#define mmCRTC2_DCFE_MEM_PWR_CTRL2                                              0x1fb8
++#define mmCRTC3_DCFE_MEM_PWR_CTRL2                                              0x41b8
++#define mmCRTC4_DCFE_MEM_PWR_CTRL2                                              0x43b8
++#define mmCRTC5_DCFE_MEM_PWR_CTRL2                                              0x45b8
++#define mmCRTC6_DCFE_MEM_PWR_CTRL2                                              0x47b8
++#define mmDCFE_MEM_PWR_STATUS                                                   0x1bb9
++#define mmCRTC0_DCFE_MEM_PWR_STATUS                                             0x1bb9
++#define mmCRTC1_DCFE_MEM_PWR_STATUS                                             0x1db9
++#define mmCRTC2_DCFE_MEM_PWR_STATUS                                             0x1fb9
++#define mmCRTC3_DCFE_MEM_PWR_STATUS                                             0x41b9
++#define mmCRTC4_DCFE_MEM_PWR_STATUS                                             0x43b9
++#define mmCRTC5_DCFE_MEM_PWR_STATUS                                             0x45b9
++#define mmCRTC6_DCFE_MEM_PWR_STATUS                                             0x47b9
++#define mmCRTC_H_TOTAL                                                          0x1b80
++#define mmCRTC0_CRTC_H_TOTAL                                                    0x1b80
++#define mmCRTC1_CRTC_H_TOTAL                                                    0x1d80
++#define mmCRTC2_CRTC_H_TOTAL                                                    0x1f80
++#define mmCRTC3_CRTC_H_TOTAL                                                    0x4180
++#define mmCRTC4_CRTC_H_TOTAL                                                    0x4380
++#define mmCRTC5_CRTC_H_TOTAL                                                    0x4580
++#define mmCRTC6_CRTC_H_TOTAL                                                    0x4780
++#define mmCRTC_H_BLANK_START_END                                                0x1b81
++#define mmCRTC0_CRTC_H_BLANK_START_END                                          0x1b81
++#define mmCRTC1_CRTC_H_BLANK_START_END                                          0x1d81
++#define mmCRTC2_CRTC_H_BLANK_START_END                                          0x1f81
++#define mmCRTC3_CRTC_H_BLANK_START_END                                          0x4181
++#define mmCRTC4_CRTC_H_BLANK_START_END                                          0x4381
++#define mmCRTC5_CRTC_H_BLANK_START_END                                          0x4581
++#define mmCRTC6_CRTC_H_BLANK_START_END                                          0x4781
++#define mmCRTC_H_SYNC_A                                                         0x1b82
++#define mmCRTC0_CRTC_H_SYNC_A                                                   0x1b82
++#define mmCRTC1_CRTC_H_SYNC_A                                                   0x1d82
++#define mmCRTC2_CRTC_H_SYNC_A                                                   0x1f82
++#define mmCRTC3_CRTC_H_SYNC_A                                                   0x4182
++#define mmCRTC4_CRTC_H_SYNC_A                                                   0x4382
++#define mmCRTC5_CRTC_H_SYNC_A                                                   0x4582
++#define mmCRTC6_CRTC_H_SYNC_A                                                   0x4782
++#define mmCRTC_H_SYNC_A_CNTL                                                    0x1b83
++#define mmCRTC0_CRTC_H_SYNC_A_CNTL                                              0x1b83
++#define mmCRTC1_CRTC_H_SYNC_A_CNTL                                              0x1d83
++#define mmCRTC2_CRTC_H_SYNC_A_CNTL                                              0x1f83
++#define mmCRTC3_CRTC_H_SYNC_A_CNTL                                              0x4183
++#define mmCRTC4_CRTC_H_SYNC_A_CNTL                                              0x4383
++#define mmCRTC5_CRTC_H_SYNC_A_CNTL                                              0x4583
++#define mmCRTC6_CRTC_H_SYNC_A_CNTL                                              0x4783
++#define mmCRTC_H_SYNC_B                                                         0x1b84
++#define mmCRTC0_CRTC_H_SYNC_B                                                   0x1b84
++#define mmCRTC1_CRTC_H_SYNC_B                                                   0x1d84
++#define mmCRTC2_CRTC_H_SYNC_B                                                   0x1f84
++#define mmCRTC3_CRTC_H_SYNC_B                                                   0x4184
++#define mmCRTC4_CRTC_H_SYNC_B                                                   0x4384
++#define mmCRTC5_CRTC_H_SYNC_B                                                   0x4584
++#define mmCRTC6_CRTC_H_SYNC_B                                                   0x4784
++#define mmCRTC_H_SYNC_B_CNTL                                                    0x1b85
++#define mmCRTC0_CRTC_H_SYNC_B_CNTL                                              0x1b85
++#define mmCRTC1_CRTC_H_SYNC_B_CNTL                                              0x1d85
++#define mmCRTC2_CRTC_H_SYNC_B_CNTL                                              0x1f85
++#define mmCRTC3_CRTC_H_SYNC_B_CNTL                                              0x4185
++#define mmCRTC4_CRTC_H_SYNC_B_CNTL                                              0x4385
++#define mmCRTC5_CRTC_H_SYNC_B_CNTL                                              0x4585
++#define mmCRTC6_CRTC_H_SYNC_B_CNTL                                              0x4785
++#define mmCRTC_VBI_END                                                          0x1b86
++#define mmCRTC0_CRTC_VBI_END                                                    0x1b86
++#define mmCRTC1_CRTC_VBI_END                                                    0x1d86
++#define mmCRTC2_CRTC_VBI_END                                                    0x1f86
++#define mmCRTC3_CRTC_VBI_END                                                    0x4186
++#define mmCRTC4_CRTC_VBI_END                                                    0x4386
++#define mmCRTC5_CRTC_VBI_END                                                    0x4586
++#define mmCRTC6_CRTC_VBI_END                                                    0x4786
++#define mmCRTC_V_TOTAL                                                          0x1b87
++#define mmCRTC0_CRTC_V_TOTAL                                                    0x1b87
++#define mmCRTC1_CRTC_V_TOTAL                                                    0x1d87
++#define mmCRTC2_CRTC_V_TOTAL                                                    0x1f87
++#define mmCRTC3_CRTC_V_TOTAL                                                    0x4187
++#define mmCRTC4_CRTC_V_TOTAL                                                    0x4387
++#define mmCRTC5_CRTC_V_TOTAL                                                    0x4587
++#define mmCRTC6_CRTC_V_TOTAL                                                    0x4787
++#define mmCRTC_V_TOTAL_MIN                                                      0x1b88
++#define mmCRTC0_CRTC_V_TOTAL_MIN                                                0x1b88
++#define mmCRTC1_CRTC_V_TOTAL_MIN                                                0x1d88
++#define mmCRTC2_CRTC_V_TOTAL_MIN                                                0x1f88
++#define mmCRTC3_CRTC_V_TOTAL_MIN                                                0x4188
++#define mmCRTC4_CRTC_V_TOTAL_MIN                                                0x4388
++#define mmCRTC5_CRTC_V_TOTAL_MIN                                                0x4588
++#define mmCRTC6_CRTC_V_TOTAL_MIN                                                0x4788
++#define mmCRTC_V_TOTAL_MAX                                                      0x1b89
++#define mmCRTC0_CRTC_V_TOTAL_MAX                                                0x1b89
++#define mmCRTC1_CRTC_V_TOTAL_MAX                                                0x1d89
++#define mmCRTC2_CRTC_V_TOTAL_MAX                                                0x1f89
++#define mmCRTC3_CRTC_V_TOTAL_MAX                                                0x4189
++#define mmCRTC4_CRTC_V_TOTAL_MAX                                                0x4389
++#define mmCRTC5_CRTC_V_TOTAL_MAX                                                0x4589
++#define mmCRTC6_CRTC_V_TOTAL_MAX                                                0x4789
++#define mmCRTC_V_TOTAL_CONTROL                                                  0x1b8a
++#define mmCRTC0_CRTC_V_TOTAL_CONTROL                                            0x1b8a
++#define mmCRTC1_CRTC_V_TOTAL_CONTROL                                            0x1d8a
++#define mmCRTC2_CRTC_V_TOTAL_CONTROL                                            0x1f8a
++#define mmCRTC3_CRTC_V_TOTAL_CONTROL                                            0x418a
++#define mmCRTC4_CRTC_V_TOTAL_CONTROL                                            0x438a
++#define mmCRTC5_CRTC_V_TOTAL_CONTROL                                            0x458a
++#define mmCRTC6_CRTC_V_TOTAL_CONTROL                                            0x478a
++#define mmCRTC_V_TOTAL_INT_STATUS                                               0x1b8b
++#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                         0x1b8b
++#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                         0x1d8b
++#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                         0x1f8b
++#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                         0x418b
++#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                         0x438b
++#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                         0x458b
++#define mmCRTC6_CRTC_V_TOTAL_INT_STATUS                                         0x478b
++#define mmCRTC_VSYNC_NOM_INT_STATUS                                             0x1b8c
++#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                       0x1b8c
++#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                       0x1d8c
++#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                       0x1f8c
++#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                       0x418c
++#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                       0x438c
++#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                       0x458c
++#define mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS                                       0x478c
++#define mmCRTC_V_BLANK_START_END                                                0x1b8d
++#define mmCRTC0_CRTC_V_BLANK_START_END                                          0x1b8d
++#define mmCRTC1_CRTC_V_BLANK_START_END                                          0x1d8d
++#define mmCRTC2_CRTC_V_BLANK_START_END                                          0x1f8d
++#define mmCRTC3_CRTC_V_BLANK_START_END                                          0x418d
++#define mmCRTC4_CRTC_V_BLANK_START_END                                          0x438d
++#define mmCRTC5_CRTC_V_BLANK_START_END                                          0x458d
++#define mmCRTC6_CRTC_V_BLANK_START_END                                          0x478d
++#define mmCRTC_V_SYNC_A                                                         0x1b8e
++#define mmCRTC0_CRTC_V_SYNC_A                                                   0x1b8e
++#define mmCRTC1_CRTC_V_SYNC_A                                                   0x1d8e
++#define mmCRTC2_CRTC_V_SYNC_A                                                   0x1f8e
++#define mmCRTC3_CRTC_V_SYNC_A                                                   0x418e
++#define mmCRTC4_CRTC_V_SYNC_A                                                   0x438e
++#define mmCRTC5_CRTC_V_SYNC_A                                                   0x458e
++#define mmCRTC6_CRTC_V_SYNC_A                                                   0x478e
++#define mmCRTC_V_SYNC_A_CNTL                                                    0x1b8f
++#define mmCRTC0_CRTC_V_SYNC_A_CNTL                                              0x1b8f
++#define mmCRTC1_CRTC_V_SYNC_A_CNTL                                              0x1d8f
++#define mmCRTC2_CRTC_V_SYNC_A_CNTL                                              0x1f8f
++#define mmCRTC3_CRTC_V_SYNC_A_CNTL                                              0x418f
++#define mmCRTC4_CRTC_V_SYNC_A_CNTL                                              0x438f
++#define mmCRTC5_CRTC_V_SYNC_A_CNTL                                              0x458f
++#define mmCRTC6_CRTC_V_SYNC_A_CNTL                                              0x478f
++#define mmCRTC_V_SYNC_B                                                         0x1b90
++#define mmCRTC0_CRTC_V_SYNC_B                                                   0x1b90
++#define mmCRTC1_CRTC_V_SYNC_B                                                   0x1d90
++#define mmCRTC2_CRTC_V_SYNC_B                                                   0x1f90
++#define mmCRTC3_CRTC_V_SYNC_B                                                   0x4190
++#define mmCRTC4_CRTC_V_SYNC_B                                                   0x4390
++#define mmCRTC5_CRTC_V_SYNC_B                                                   0x4590
++#define mmCRTC6_CRTC_V_SYNC_B                                                   0x4790
++#define mmCRTC_V_SYNC_B_CNTL                                                    0x1b91
++#define mmCRTC0_CRTC_V_SYNC_B_CNTL                                              0x1b91
++#define mmCRTC1_CRTC_V_SYNC_B_CNTL                                              0x1d91
++#define mmCRTC2_CRTC_V_SYNC_B_CNTL                                              0x1f91
++#define mmCRTC3_CRTC_V_SYNC_B_CNTL                                              0x4191
++#define mmCRTC4_CRTC_V_SYNC_B_CNTL                                              0x4391
++#define mmCRTC5_CRTC_V_SYNC_B_CNTL                                              0x4591
++#define mmCRTC6_CRTC_V_SYNC_B_CNTL                                              0x4791
++#define mmCRTC_DTMTEST_CNTL                                                     0x1b92
++#define mmCRTC0_CRTC_DTMTEST_CNTL                                               0x1b92
++#define mmCRTC1_CRTC_DTMTEST_CNTL                                               0x1d92
++#define mmCRTC2_CRTC_DTMTEST_CNTL                                               0x1f92
++#define mmCRTC3_CRTC_DTMTEST_CNTL                                               0x4192
++#define mmCRTC4_CRTC_DTMTEST_CNTL                                               0x4392
++#define mmCRTC5_CRTC_DTMTEST_CNTL                                               0x4592
++#define mmCRTC6_CRTC_DTMTEST_CNTL                                               0x4792
++#define mmCRTC_DTMTEST_STATUS_POSITION                                          0x1b93
++#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                    0x1b93
++#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                    0x1d93
++#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                    0x1f93
++#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                    0x4193
++#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                    0x4393
++#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                    0x4593
++#define mmCRTC6_CRTC_DTMTEST_STATUS_POSITION                                    0x4793
++#define mmCRTC_TRIGA_CNTL                                                       0x1b94
++#define mmCRTC0_CRTC_TRIGA_CNTL                                                 0x1b94
++#define mmCRTC1_CRTC_TRIGA_CNTL                                                 0x1d94
++#define mmCRTC2_CRTC_TRIGA_CNTL                                                 0x1f94
++#define mmCRTC3_CRTC_TRIGA_CNTL                                                 0x4194
++#define mmCRTC4_CRTC_TRIGA_CNTL                                                 0x4394
++#define mmCRTC5_CRTC_TRIGA_CNTL                                                 0x4594
++#define mmCRTC6_CRTC_TRIGA_CNTL                                                 0x4794
++#define mmCRTC_TRIGA_MANUAL_TRIG                                                0x1b95
++#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                          0x1b95
++#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                          0x1d95
++#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                          0x1f95
++#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                          0x4195
++#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                          0x4395
++#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                          0x4595
++#define mmCRTC6_CRTC_TRIGA_MANUAL_TRIG                                          0x4795
++#define mmCRTC_TRIGB_CNTL                                                       0x1b96
++#define mmCRTC0_CRTC_TRIGB_CNTL                                                 0x1b96
++#define mmCRTC1_CRTC_TRIGB_CNTL                                                 0x1d96
++#define mmCRTC2_CRTC_TRIGB_CNTL                                                 0x1f96
++#define mmCRTC3_CRTC_TRIGB_CNTL                                                 0x4196
++#define mmCRTC4_CRTC_TRIGB_CNTL                                                 0x4396
++#define mmCRTC5_CRTC_TRIGB_CNTL                                                 0x4596
++#define mmCRTC6_CRTC_TRIGB_CNTL                                                 0x4796
++#define mmCRTC_TRIGB_MANUAL_TRIG                                                0x1b97
++#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                          0x1b97
++#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                          0x1d97
++#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                          0x1f97
++#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                          0x4197
++#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                          0x4397
++#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                          0x4597
++#define mmCRTC6_CRTC_TRIGB_MANUAL_TRIG                                          0x4797
++#define mmCRTC_FORCE_COUNT_NOW_CNTL                                             0x1b98
++#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1b98
++#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1d98
++#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1f98
++#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4198
++#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4398
++#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4598
++#define mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4798
++#define mmCRTC_FLOW_CONTROL                                                     0x1b99
++#define mmCRTC0_CRTC_FLOW_CONTROL                                               0x1b99
++#define mmCRTC1_CRTC_FLOW_CONTROL                                               0x1d99
++#define mmCRTC2_CRTC_FLOW_CONTROL                                               0x1f99
++#define mmCRTC3_CRTC_FLOW_CONTROL                                               0x4199
++#define mmCRTC4_CRTC_FLOW_CONTROL                                               0x4399
++#define mmCRTC5_CRTC_FLOW_CONTROL                                               0x4599
++#define mmCRTC6_CRTC_FLOW_CONTROL                                               0x4799
++#define mmCRTC_STEREO_FORCE_NEXT_EYE                                            0x1b9a
++#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1b9a
++#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1d9a
++#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1f9a
++#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                      0x419a
++#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                      0x439a
++#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                      0x459a
++#define mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE                                      0x479a
++#define mmCRTC_AVSYNC_COUNTER                                                   0x1b9b
++#define mmCRTC0_CRTC_AVSYNC_COUNTER                                             0x1b9b
++#define mmCRTC1_CRTC_AVSYNC_COUNTER                                             0x1d9b
++#define mmCRTC2_CRTC_AVSYNC_COUNTER                                             0x1f9b
++#define mmCRTC3_CRTC_AVSYNC_COUNTER                                             0x419b
++#define mmCRTC4_CRTC_AVSYNC_COUNTER                                             0x439b
++#define mmCRTC5_CRTC_AVSYNC_COUNTER                                             0x459b
++#define mmCRTC6_CRTC_AVSYNC_COUNTER                                             0x479b
++#define mmCRTC_CONTROL                                                          0x1b9c
++#define mmCRTC0_CRTC_CONTROL                                                    0x1b9c
++#define mmCRTC1_CRTC_CONTROL                                                    0x1d9c
++#define mmCRTC2_CRTC_CONTROL                                                    0x1f9c
++#define mmCRTC3_CRTC_CONTROL                                                    0x419c
++#define mmCRTC4_CRTC_CONTROL                                                    0x439c
++#define mmCRTC5_CRTC_CONTROL                                                    0x459c
++#define mmCRTC6_CRTC_CONTROL                                                    0x479c
++#define mmCRTC_BLANK_CONTROL                                                    0x1b9d
++#define mmCRTC0_CRTC_BLANK_CONTROL                                              0x1b9d
++#define mmCRTC1_CRTC_BLANK_CONTROL                                              0x1d9d
++#define mmCRTC2_CRTC_BLANK_CONTROL                                              0x1f9d
++#define mmCRTC3_CRTC_BLANK_CONTROL                                              0x419d
++#define mmCRTC4_CRTC_BLANK_CONTROL                                              0x439d
++#define mmCRTC5_CRTC_BLANK_CONTROL                                              0x459d
++#define mmCRTC6_CRTC_BLANK_CONTROL                                              0x479d
++#define mmCRTC_INTERLACE_CONTROL                                                0x1b9e
++#define mmCRTC0_CRTC_INTERLACE_CONTROL                                          0x1b9e
++#define mmCRTC1_CRTC_INTERLACE_CONTROL                                          0x1d9e
++#define mmCRTC2_CRTC_INTERLACE_CONTROL                                          0x1f9e
++#define mmCRTC3_CRTC_INTERLACE_CONTROL                                          0x419e
++#define mmCRTC4_CRTC_INTERLACE_CONTROL                                          0x439e
++#define mmCRTC5_CRTC_INTERLACE_CONTROL                                          0x459e
++#define mmCRTC6_CRTC_INTERLACE_CONTROL                                          0x479e
++#define mmCRTC_INTERLACE_STATUS                                                 0x1b9f
++#define mmCRTC0_CRTC_INTERLACE_STATUS                                           0x1b9f
++#define mmCRTC1_CRTC_INTERLACE_STATUS                                           0x1d9f
++#define mmCRTC2_CRTC_INTERLACE_STATUS                                           0x1f9f
++#define mmCRTC3_CRTC_INTERLACE_STATUS                                           0x419f
++#define mmCRTC4_CRTC_INTERLACE_STATUS                                           0x439f
++#define mmCRTC5_CRTC_INTERLACE_STATUS                                           0x459f
++#define mmCRTC6_CRTC_INTERLACE_STATUS                                           0x479f
++#define mmCRTC_FIELD_INDICATION_CONTROL                                         0x1ba0
++#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                   0x1ba0
++#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                   0x1da0
++#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                   0x1fa0
++#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                   0x41a0
++#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                   0x43a0
++#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                   0x45a0
++#define mmCRTC6_CRTC_FIELD_INDICATION_CONTROL                                   0x47a0
++#define mmCRTC_PIXEL_DATA_READBACK0                                             0x1ba1
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                       0x1ba1
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                       0x1da1
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                       0x1fa1
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                       0x41a1
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                       0x43a1
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                       0x45a1
++#define mmCRTC6_CRTC_PIXEL_DATA_READBACK0                                       0x47a1
++#define mmCRTC_PIXEL_DATA_READBACK1                                             0x1ba2
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                       0x1ba2
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                       0x1da2
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                       0x1fa2
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                       0x41a2
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                       0x43a2
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                       0x45a2
++#define mmCRTC6_CRTC_PIXEL_DATA_READBACK1                                       0x47a2
++#define mmCRTC_STATUS                                                           0x1ba3
++#define mmCRTC0_CRTC_STATUS                                                     0x1ba3
++#define mmCRTC1_CRTC_STATUS                                                     0x1da3
++#define mmCRTC2_CRTC_STATUS                                                     0x1fa3
++#define mmCRTC3_CRTC_STATUS                                                     0x41a3
++#define mmCRTC4_CRTC_STATUS                                                     0x43a3
++#define mmCRTC5_CRTC_STATUS                                                     0x45a3
++#define mmCRTC6_CRTC_STATUS                                                     0x47a3
++#define mmCRTC_STATUS_POSITION                                                  0x1ba4
++#define mmCRTC0_CRTC_STATUS_POSITION                                            0x1ba4
++#define mmCRTC1_CRTC_STATUS_POSITION                                            0x1da4
++#define mmCRTC2_CRTC_STATUS_POSITION                                            0x1fa4
++#define mmCRTC3_CRTC_STATUS_POSITION                                            0x41a4
++#define mmCRTC4_CRTC_STATUS_POSITION                                            0x43a4
++#define mmCRTC5_CRTC_STATUS_POSITION                                            0x45a4
++#define mmCRTC6_CRTC_STATUS_POSITION                                            0x47a4
++#define mmCRTC_NOM_VERT_POSITION                                                0x1ba5
++#define mmCRTC0_CRTC_NOM_VERT_POSITION                                          0x1ba5
++#define mmCRTC1_CRTC_NOM_VERT_POSITION                                          0x1da5
++#define mmCRTC2_CRTC_NOM_VERT_POSITION                                          0x1fa5
++#define mmCRTC3_CRTC_NOM_VERT_POSITION                                          0x41a5
++#define mmCRTC4_CRTC_NOM_VERT_POSITION                                          0x43a5
++#define mmCRTC5_CRTC_NOM_VERT_POSITION                                          0x45a5
++#define mmCRTC6_CRTC_NOM_VERT_POSITION                                          0x47a5
++#define mmCRTC_STATUS_FRAME_COUNT                                               0x1ba6
++#define mmCRTC0_CRTC_STATUS_FRAME_COUNT                                         0x1ba6
++#define mmCRTC1_CRTC_STATUS_FRAME_COUNT                                         0x1da6
++#define mmCRTC2_CRTC_STATUS_FRAME_COUNT                                         0x1fa6
++#define mmCRTC3_CRTC_STATUS_FRAME_COUNT                                         0x41a6
++#define mmCRTC4_CRTC_STATUS_FRAME_COUNT                                         0x43a6
++#define mmCRTC5_CRTC_STATUS_FRAME_COUNT                                         0x45a6
++#define mmCRTC6_CRTC_STATUS_FRAME_COUNT                                         0x47a6
++#define mmCRTC_STATUS_VF_COUNT                                                  0x1ba7
++#define mmCRTC0_CRTC_STATUS_VF_COUNT                                            0x1ba7
++#define mmCRTC1_CRTC_STATUS_VF_COUNT                                            0x1da7
++#define mmCRTC2_CRTC_STATUS_VF_COUNT                                            0x1fa7
++#define mmCRTC3_CRTC_STATUS_VF_COUNT                                            0x41a7
++#define mmCRTC4_CRTC_STATUS_VF_COUNT                                            0x43a7
++#define mmCRTC5_CRTC_STATUS_VF_COUNT                                            0x45a7
++#define mmCRTC6_CRTC_STATUS_VF_COUNT                                            0x47a7
++#define mmCRTC_STATUS_HV_COUNT                                                  0x1ba8
++#define mmCRTC0_CRTC_STATUS_HV_COUNT                                            0x1ba8
++#define mmCRTC1_CRTC_STATUS_HV_COUNT                                            0x1da8
++#define mmCRTC2_CRTC_STATUS_HV_COUNT                                            0x1fa8
++#define mmCRTC3_CRTC_STATUS_HV_COUNT                                            0x41a8
++#define mmCRTC4_CRTC_STATUS_HV_COUNT                                            0x43a8
++#define mmCRTC5_CRTC_STATUS_HV_COUNT                                            0x45a8
++#define mmCRTC6_CRTC_STATUS_HV_COUNT                                            0x47a8
++#define mmCRTC_COUNT_CONTROL                                                    0x1ba9
++#define mmCRTC0_CRTC_COUNT_CONTROL                                              0x1ba9
++#define mmCRTC1_CRTC_COUNT_CONTROL                                              0x1da9
++#define mmCRTC2_CRTC_COUNT_CONTROL                                              0x1fa9
++#define mmCRTC3_CRTC_COUNT_CONTROL                                              0x41a9
++#define mmCRTC4_CRTC_COUNT_CONTROL                                              0x43a9
++#define mmCRTC5_CRTC_COUNT_CONTROL                                              0x45a9
++#define mmCRTC6_CRTC_COUNT_CONTROL                                              0x47a9
++#define mmCRTC_COUNT_RESET                                                      0x1baa
++#define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
++#define mmCRTC1_CRTC_COUNT_RESET                                                0x1daa
++#define mmCRTC2_CRTC_COUNT_RESET                                                0x1faa
++#define mmCRTC3_CRTC_COUNT_RESET                                                0x41aa
++#define mmCRTC4_CRTC_COUNT_RESET                                                0x43aa
++#define mmCRTC5_CRTC_COUNT_RESET                                                0x45aa
++#define mmCRTC6_CRTC_COUNT_RESET                                                0x47aa
++#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                     0x1bab
++#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1bab
++#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1dab
++#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1fab
++#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x41ab
++#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x43ab
++#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x45ab
++#define mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x47ab
++#define mmCRTC_VERT_SYNC_CONTROL                                                0x1bac
++#define mmCRTC0_CRTC_VERT_SYNC_CONTROL                                          0x1bac
++#define mmCRTC1_CRTC_VERT_SYNC_CONTROL                                          0x1dac
++#define mmCRTC2_CRTC_VERT_SYNC_CONTROL                                          0x1fac
++#define mmCRTC3_CRTC_VERT_SYNC_CONTROL                                          0x41ac
++#define mmCRTC4_CRTC_VERT_SYNC_CONTROL                                          0x43ac
++#define mmCRTC5_CRTC_VERT_SYNC_CONTROL                                          0x45ac
++#define mmCRTC6_CRTC_VERT_SYNC_CONTROL                                          0x47ac
++#define mmCRTC_STEREO_STATUS                                                    0x1bad
++#define mmCRTC0_CRTC_STEREO_STATUS                                              0x1bad
++#define mmCRTC1_CRTC_STEREO_STATUS                                              0x1dad
++#define mmCRTC2_CRTC_STEREO_STATUS                                              0x1fad
++#define mmCRTC3_CRTC_STEREO_STATUS                                              0x41ad
++#define mmCRTC4_CRTC_STEREO_STATUS                                              0x43ad
++#define mmCRTC5_CRTC_STEREO_STATUS                                              0x45ad
++#define mmCRTC6_CRTC_STEREO_STATUS                                              0x47ad
++#define mmCRTC_STEREO_CONTROL                                                   0x1bae
++#define mmCRTC0_CRTC_STEREO_CONTROL                                             0x1bae
++#define mmCRTC1_CRTC_STEREO_CONTROL                                             0x1dae
++#define mmCRTC2_CRTC_STEREO_CONTROL                                             0x1fae
++#define mmCRTC3_CRTC_STEREO_CONTROL                                             0x41ae
++#define mmCRTC4_CRTC_STEREO_CONTROL                                             0x43ae
++#define mmCRTC5_CRTC_STEREO_CONTROL                                             0x45ae
++#define mmCRTC6_CRTC_STEREO_CONTROL                                             0x47ae
++#define mmCRTC_SNAPSHOT_STATUS                                                  0x1baf
++#define mmCRTC0_CRTC_SNAPSHOT_STATUS                                            0x1baf
++#define mmCRTC1_CRTC_SNAPSHOT_STATUS                                            0x1daf
++#define mmCRTC2_CRTC_SNAPSHOT_STATUS                                            0x1faf
++#define mmCRTC3_CRTC_SNAPSHOT_STATUS                                            0x41af
++#define mmCRTC4_CRTC_SNAPSHOT_STATUS                                            0x43af
++#define mmCRTC5_CRTC_SNAPSHOT_STATUS                                            0x45af
++#define mmCRTC6_CRTC_SNAPSHOT_STATUS                                            0x47af
++#define mmCRTC_SNAPSHOT_CONTROL                                                 0x1bb0
++#define mmCRTC0_CRTC_SNAPSHOT_CONTROL                                           0x1bb0
++#define mmCRTC1_CRTC_SNAPSHOT_CONTROL                                           0x1db0
++#define mmCRTC2_CRTC_SNAPSHOT_CONTROL                                           0x1fb0
++#define mmCRTC3_CRTC_SNAPSHOT_CONTROL                                           0x41b0
++#define mmCRTC4_CRTC_SNAPSHOT_CONTROL                                           0x43b0
++#define mmCRTC5_CRTC_SNAPSHOT_CONTROL                                           0x45b0
++#define mmCRTC6_CRTC_SNAPSHOT_CONTROL                                           0x47b0
++#define mmCRTC_SNAPSHOT_POSITION                                                0x1bb1
++#define mmCRTC0_CRTC_SNAPSHOT_POSITION                                          0x1bb1
++#define mmCRTC1_CRTC_SNAPSHOT_POSITION                                          0x1db1
++#define mmCRTC2_CRTC_SNAPSHOT_POSITION                                          0x1fb1
++#define mmCRTC3_CRTC_SNAPSHOT_POSITION                                          0x41b1
++#define mmCRTC4_CRTC_SNAPSHOT_POSITION                                          0x43b1
++#define mmCRTC5_CRTC_SNAPSHOT_POSITION                                          0x45b1
++#define mmCRTC6_CRTC_SNAPSHOT_POSITION                                          0x47b1
++#define mmCRTC_SNAPSHOT_FRAME                                                   0x1bb2
++#define mmCRTC0_CRTC_SNAPSHOT_FRAME                                             0x1bb2
++#define mmCRTC1_CRTC_SNAPSHOT_FRAME                                             0x1db2
++#define mmCRTC2_CRTC_SNAPSHOT_FRAME                                             0x1fb2
++#define mmCRTC3_CRTC_SNAPSHOT_FRAME                                             0x41b2
++#define mmCRTC4_CRTC_SNAPSHOT_FRAME                                             0x43b2
++#define mmCRTC5_CRTC_SNAPSHOT_FRAME                                             0x45b2
++#define mmCRTC6_CRTC_SNAPSHOT_FRAME                                             0x47b2
++#define mmCRTC_START_LINE_CONTROL                                               0x1bb3
++#define mmCRTC0_CRTC_START_LINE_CONTROL                                         0x1bb3
++#define mmCRTC1_CRTC_START_LINE_CONTROL                                         0x1db3
++#define mmCRTC2_CRTC_START_LINE_CONTROL                                         0x1fb3
++#define mmCRTC3_CRTC_START_LINE_CONTROL                                         0x41b3
++#define mmCRTC4_CRTC_START_LINE_CONTROL                                         0x43b3
++#define mmCRTC5_CRTC_START_LINE_CONTROL                                         0x45b3
++#define mmCRTC6_CRTC_START_LINE_CONTROL                                         0x47b3
++#define mmCRTC_INTERRUPT_CONTROL                                                0x1bb4
++#define mmCRTC0_CRTC_INTERRUPT_CONTROL                                          0x1bb4
++#define mmCRTC1_CRTC_INTERRUPT_CONTROL                                          0x1db4
++#define mmCRTC2_CRTC_INTERRUPT_CONTROL                                          0x1fb4
++#define mmCRTC3_CRTC_INTERRUPT_CONTROL                                          0x41b4
++#define mmCRTC4_CRTC_INTERRUPT_CONTROL                                          0x43b4
++#define mmCRTC5_CRTC_INTERRUPT_CONTROL                                          0x45b4
++#define mmCRTC6_CRTC_INTERRUPT_CONTROL                                          0x47b4
++#define mmCRTC_UPDATE_LOCK                                                      0x1bb5
++#define mmCRTC0_CRTC_UPDATE_LOCK                                                0x1bb5
++#define mmCRTC1_CRTC_UPDATE_LOCK                                                0x1db5
++#define mmCRTC2_CRTC_UPDATE_LOCK                                                0x1fb5
++#define mmCRTC3_CRTC_UPDATE_LOCK                                                0x41b5
++#define mmCRTC4_CRTC_UPDATE_LOCK                                                0x43b5
++#define mmCRTC5_CRTC_UPDATE_LOCK                                                0x45b5
++#define mmCRTC6_CRTC_UPDATE_LOCK                                                0x47b5
++#define mmCRTC_DOUBLE_BUFFER_CONTROL                                            0x1bb6
++#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1bb6
++#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1db6
++#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1fb6
++#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                      0x41b6
++#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                      0x43b6
++#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                      0x45b6
++#define mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL                                      0x47b6
++#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE                                       0x1bb7
++#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1bb7
++#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1db7
++#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1fb7
++#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x41b7
++#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x43b7
++#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x45b7
++#define mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x47b7
++#define mmCRTC_TEST_PATTERN_CONTROL                                             0x1bba
++#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                       0x1bba
++#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                       0x1dba
++#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                       0x1fba
++#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                       0x41ba
++#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                       0x43ba
++#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                       0x45ba
++#define mmCRTC6_CRTC_TEST_PATTERN_CONTROL                                       0x47ba
++#define mmCRTC_TEST_PATTERN_PARAMETERS                                          0x1bbb
++#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                    0x1bbb
++#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                    0x1dbb
++#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                    0x1fbb
++#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                    0x41bb
++#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                    0x43bb
++#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                    0x45bb
++#define mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS                                    0x47bb
++#define mmCRTC_TEST_PATTERN_COLOR                                               0x1bbc
++#define mmCRTC0_CRTC_TEST_PATTERN_COLOR                                         0x1bbc
++#define mmCRTC1_CRTC_TEST_PATTERN_COLOR                                         0x1dbc
++#define mmCRTC2_CRTC_TEST_PATTERN_COLOR                                         0x1fbc
++#define mmCRTC3_CRTC_TEST_PATTERN_COLOR                                         0x41bc
++#define mmCRTC4_CRTC_TEST_PATTERN_COLOR                                         0x43bc
++#define mmCRTC5_CRTC_TEST_PATTERN_COLOR                                         0x45bc
++#define mmCRTC6_CRTC_TEST_PATTERN_COLOR                                         0x47bc
++#define mmMASTER_UPDATE_LOCK                                                    0x1bbd
++#define mmCRTC0_MASTER_UPDATE_LOCK                                              0x1bbd
++#define mmCRTC1_MASTER_UPDATE_LOCK                                              0x1dbd
++#define mmCRTC2_MASTER_UPDATE_LOCK                                              0x1fbd
++#define mmCRTC3_MASTER_UPDATE_LOCK                                              0x41bd
++#define mmCRTC4_MASTER_UPDATE_LOCK                                              0x43bd
++#define mmCRTC5_MASTER_UPDATE_LOCK                                              0x45bd
++#define mmCRTC6_MASTER_UPDATE_LOCK                                              0x47bd
++#define mmMASTER_UPDATE_MODE                                                    0x1bbe
++#define mmCRTC0_MASTER_UPDATE_MODE                                              0x1bbe
++#define mmCRTC1_MASTER_UPDATE_MODE                                              0x1dbe
++#define mmCRTC2_MASTER_UPDATE_MODE                                              0x1fbe
++#define mmCRTC3_MASTER_UPDATE_MODE                                              0x41be
++#define mmCRTC4_MASTER_UPDATE_MODE                                              0x43be
++#define mmCRTC5_MASTER_UPDATE_MODE                                              0x45be
++#define mmCRTC6_MASTER_UPDATE_MODE                                              0x47be
++#define mmCRTC_MVP_INBAND_CNTL_INSERT                                           0x1bbf
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1bbf
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1dbf
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1fbf
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                     0x41bf
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                     0x43bf
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                     0x45bf
++#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT                                     0x47bf
++#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER                                     0x1bc0
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1bc0
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1dc0
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1fc0
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x41c0
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x43c0
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x45c0
++#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x47c0
++#define mmCRTC_MVP_STATUS                                                       0x1bc1
++#define mmCRTC0_CRTC_MVP_STATUS                                                 0x1bc1
++#define mmCRTC1_CRTC_MVP_STATUS                                                 0x1dc1
++#define mmCRTC2_CRTC_MVP_STATUS                                                 0x1fc1
++#define mmCRTC3_CRTC_MVP_STATUS                                                 0x41c1
++#define mmCRTC4_CRTC_MVP_STATUS                                                 0x43c1
++#define mmCRTC5_CRTC_MVP_STATUS                                                 0x45c1
++#define mmCRTC6_CRTC_MVP_STATUS                                                 0x47c1
++#define mmCRTC_MASTER_EN                                                        0x1bc2
++#define mmCRTC0_CRTC_MASTER_EN                                                  0x1bc2
++#define mmCRTC1_CRTC_MASTER_EN                                                  0x1dc2
++#define mmCRTC2_CRTC_MASTER_EN                                                  0x1fc2
++#define mmCRTC3_CRTC_MASTER_EN                                                  0x41c2
++#define mmCRTC4_CRTC_MASTER_EN                                                  0x43c2
++#define mmCRTC5_CRTC_MASTER_EN                                                  0x45c2
++#define mmCRTC6_CRTC_MASTER_EN                                                  0x47c2
++#define mmCRTC_ALLOW_STOP_OFF_V_CNT                                             0x1bc3
++#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1bc3
++#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1dc3
++#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1fc3
++#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x41c3
++#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x43c3
++#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x45c3
++#define mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x47c3
++#define mmCRTC_V_UPDATE_INT_STATUS                                              0x1bc4
++#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                        0x1bc4
++#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                        0x1dc4
++#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                        0x1fc4
++#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                        0x41c4
++#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                        0x43c4
++#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                        0x45c4
++#define mmCRTC6_CRTC_V_UPDATE_INT_STATUS                                        0x47c4
++#define mmCRTC_OVERSCAN_COLOR                                                   0x1bc8
++#define mmCRTC0_CRTC_OVERSCAN_COLOR                                             0x1bc8
++#define mmCRTC1_CRTC_OVERSCAN_COLOR                                             0x1dc8
++#define mmCRTC2_CRTC_OVERSCAN_COLOR                                             0x1fc8
++#define mmCRTC3_CRTC_OVERSCAN_COLOR                                             0x41c8
++#define mmCRTC4_CRTC_OVERSCAN_COLOR                                             0x43c8
++#define mmCRTC5_CRTC_OVERSCAN_COLOR                                             0x45c8
++#define mmCRTC6_CRTC_OVERSCAN_COLOR                                             0x47c8
++#define mmCRTC_OVERSCAN_COLOR_EXT                                               0x1bc9
++#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                         0x1bc9
++#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                         0x1dc9
++#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                         0x1fc9
++#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                         0x41c9
++#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                         0x43c9
++#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                         0x45c9
++#define mmCRTC6_CRTC_OVERSCAN_COLOR_EXT                                         0x47c9
++#define mmCRTC_BLANK_DATA_COLOR                                                 0x1bca
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR                                           0x1bca
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR                                           0x1dca
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR                                           0x1fca
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR                                           0x41ca
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR                                           0x43ca
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR                                           0x45ca
++#define mmCRTC6_CRTC_BLANK_DATA_COLOR                                           0x47ca
++#define mmCRTC_BLANK_DATA_COLOR_EXT                                             0x1bcb
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                       0x1bcb
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                       0x1dcb
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                       0x1fcb
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                       0x41cb
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                       0x43cb
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                       0x45cb
++#define mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT                                       0x47cb
++#define mmCRTC_BLACK_COLOR                                                      0x1bcc
++#define mmCRTC0_CRTC_BLACK_COLOR                                                0x1bcc
++#define mmCRTC1_CRTC_BLACK_COLOR                                                0x1dcc
++#define mmCRTC2_CRTC_BLACK_COLOR                                                0x1fcc
++#define mmCRTC3_CRTC_BLACK_COLOR                                                0x41cc
++#define mmCRTC4_CRTC_BLACK_COLOR                                                0x43cc
++#define mmCRTC5_CRTC_BLACK_COLOR                                                0x45cc
++#define mmCRTC6_CRTC_BLACK_COLOR                                                0x47cc
++#define mmCRTC_BLACK_COLOR_EXT                                                  0x1bcd
++#define mmCRTC0_CRTC_BLACK_COLOR_EXT                                            0x1bcd
++#define mmCRTC1_CRTC_BLACK_COLOR_EXT                                            0x1dcd
++#define mmCRTC2_CRTC_BLACK_COLOR_EXT                                            0x1fcd
++#define mmCRTC3_CRTC_BLACK_COLOR_EXT                                            0x41cd
++#define mmCRTC4_CRTC_BLACK_COLOR_EXT                                            0x43cd
++#define mmCRTC5_CRTC_BLACK_COLOR_EXT                                            0x45cd
++#define mmCRTC6_CRTC_BLACK_COLOR_EXT                                            0x47cd
++#define mmCRTC_VERTICAL_INTERRUPT0_POSITION                                     0x1bce
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1bce
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1dce
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1fce
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x41ce
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x43ce
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x45ce
++#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x47ce
++#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL                                      0x1bcf
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1bcf
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1dcf
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1fcf
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x41cf
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x43cf
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x45cf
++#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x47cf
++#define mmCRTC_VERTICAL_INTERRUPT1_POSITION                                     0x1bd0
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1bd0
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1dd0
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1fd0
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x41d0
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x43d0
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x45d0
++#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x47d0
++#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL                                      0x1bd1
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1bd1
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1dd1
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1fd1
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x41d1
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x43d1
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x45d1
++#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x47d1
++#define mmCRTC_VERTICAL_INTERRUPT2_POSITION                                     0x1bd2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1bd2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1dd2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1fd2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x41d2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x43d2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x45d2
++#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x47d2
++#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL                                      0x1bd3
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1bd3
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1dd3
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1fd3
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x41d3
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x43d3
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x45d3
++#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x47d3
++#define mmCRTC_CRC_CNTL                                                         0x1bd4
++#define mmCRTC0_CRTC_CRC_CNTL                                                   0x1bd4
++#define mmCRTC1_CRTC_CRC_CNTL                                                   0x1dd4
++#define mmCRTC2_CRTC_CRC_CNTL                                                   0x1fd4
++#define mmCRTC3_CRTC_CRC_CNTL                                                   0x41d4
++#define mmCRTC4_CRTC_CRC_CNTL                                                   0x43d4
++#define mmCRTC5_CRTC_CRC_CNTL                                                   0x45d4
++#define mmCRTC6_CRTC_CRC_CNTL                                                   0x47d4
++#define mmCRTC_CRC0_WINDOWA_X_CONTROL                                           0x1bd5
++#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1bd5
++#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1dd5
++#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1fd5
++#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x41d5
++#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x43d5
++#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x45d5
++#define mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x47d5
++#define mmCRTC_CRC0_WINDOWA_Y_CONTROL                                           0x1bd6
++#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1bd6
++#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1dd6
++#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1fd6
++#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x41d6
++#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x43d6
++#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x45d6
++#define mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x47d6
++#define mmCRTC_CRC0_WINDOWB_X_CONTROL                                           0x1bd7
++#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1bd7
++#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1dd7
++#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1fd7
++#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x41d7
++#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x43d7
++#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x45d7
++#define mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x47d7
++#define mmCRTC_CRC0_WINDOWB_Y_CONTROL                                           0x1bd8
++#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1bd8
++#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1dd8
++#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1fd8
++#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x41d8
++#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x43d8
++#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x45d8
++#define mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x47d8
++#define mmCRTC_CRC0_DATA_RG                                                     0x1bd9
++#define mmCRTC0_CRTC_CRC0_DATA_RG                                               0x1bd9
++#define mmCRTC1_CRTC_CRC0_DATA_RG                                               0x1dd9
++#define mmCRTC2_CRTC_CRC0_DATA_RG                                               0x1fd9
++#define mmCRTC3_CRTC_CRC0_DATA_RG                                               0x41d9
++#define mmCRTC4_CRTC_CRC0_DATA_RG                                               0x43d9
++#define mmCRTC5_CRTC_CRC0_DATA_RG                                               0x45d9
++#define mmCRTC6_CRTC_CRC0_DATA_RG                                               0x47d9
++#define mmCRTC_CRC0_DATA_B                                                      0x1bda
++#define mmCRTC0_CRTC_CRC0_DATA_B                                                0x1bda
++#define mmCRTC1_CRTC_CRC0_DATA_B                                                0x1dda
++#define mmCRTC2_CRTC_CRC0_DATA_B                                                0x1fda
++#define mmCRTC3_CRTC_CRC0_DATA_B                                                0x41da
++#define mmCRTC4_CRTC_CRC0_DATA_B                                                0x43da
++#define mmCRTC5_CRTC_CRC0_DATA_B                                                0x45da
++#define mmCRTC6_CRTC_CRC0_DATA_B                                                0x47da
++#define mmCRTC_CRC1_WINDOWA_X_CONTROL                                           0x1bdb
++#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1bdb
++#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1ddb
++#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1fdb
++#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x41db
++#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x43db
++#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x45db
++#define mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x47db
++#define mmCRTC_CRC1_WINDOWA_Y_CONTROL                                           0x1bdc
++#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1bdc
++#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1ddc
++#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1fdc
++#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x41dc
++#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x43dc
++#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x45dc
++#define mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x47dc
++#define mmCRTC_CRC1_WINDOWB_X_CONTROL                                           0x1bdd
++#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1bdd
++#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1ddd
++#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1fdd
++#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x41dd
++#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x43dd
++#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x45dd
++#define mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x47dd
++#define mmCRTC_CRC1_WINDOWB_Y_CONTROL                                           0x1bde
++#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1bde
++#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1dde
++#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1fde
++#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x41de
++#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x43de
++#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x45de
++#define mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x47de
++#define mmCRTC_CRC1_DATA_RG                                                     0x1bdf
++#define mmCRTC0_CRTC_CRC1_DATA_RG                                               0x1bdf
++#define mmCRTC1_CRTC_CRC1_DATA_RG                                               0x1ddf
++#define mmCRTC2_CRTC_CRC1_DATA_RG                                               0x1fdf
++#define mmCRTC3_CRTC_CRC1_DATA_RG                                               0x41df
++#define mmCRTC4_CRTC_CRC1_DATA_RG                                               0x43df
++#define mmCRTC5_CRTC_CRC1_DATA_RG                                               0x45df
++#define mmCRTC6_CRTC_CRC1_DATA_RG                                               0x47df
++#define mmCRTC_CRC1_DATA_B                                                      0x1be0
++#define mmCRTC0_CRTC_CRC1_DATA_B                                                0x1be0
++#define mmCRTC1_CRTC_CRC1_DATA_B                                                0x1de0
++#define mmCRTC2_CRTC_CRC1_DATA_B                                                0x1fe0
++#define mmCRTC3_CRTC_CRC1_DATA_B                                                0x41e0
++#define mmCRTC4_CRTC_CRC1_DATA_B                                                0x43e0
++#define mmCRTC5_CRTC_CRC1_DATA_B                                                0x45e0
++#define mmCRTC6_CRTC_CRC1_DATA_B                                                0x47e0
++#define mmCRTC_EXT_TIMING_SYNC_CONTROL                                          0x1be1
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1be1
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1de1
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1fe1
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x41e1
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x43e1
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x45e1
++#define mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x47e1
++#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START                                     0x1be2
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1be2
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1de2
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1fe2
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x41e2
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x43e2
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x45e2
++#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x47e2
++#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END                                       0x1be3
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1be3
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1de3
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1fe3
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x41e3
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x43e3
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x45e3
++#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x47e3
++#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                           0x1be4
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1be4
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1de4
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1fe4
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x41e4
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x43e4
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x45e4
++#define mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x47e4
++#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                0x1be5
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1be5
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1de5
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1fe5
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x41e5
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x43e5
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x45e5
++#define mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x47e5
++#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                         0x1be6
++#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1be6
++#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1de6
++#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1fe6
++#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x41e6
++#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x43e6
++#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x45e6
++#define mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x47e6
++#define mmCRTC_STATIC_SCREEN_CONTROL                                            0x1be7
++#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                      0x1be7
++#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                      0x1de7
++#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                      0x1fe7
++#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                      0x41e7
++#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                      0x43e7
++#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                      0x45e7
++#define mmCRTC6_CRTC_STATIC_SCREEN_CONTROL                                      0x47e7
++#define mmCRTC_3D_STRUCTURE_CONTROL                                             0x1b78
++#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                       0x1b78
++#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                       0x1d78
++#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                       0x1f78
++#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                       0x4178
++#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                       0x4378
++#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                       0x4578
++#define mmCRTC6_CRTC_3D_STRUCTURE_CONTROL                                       0x4778
++#define mmCRTC_GSL_VSYNC_GAP                                                    0x1b79
++#define mmCRTC0_CRTC_GSL_VSYNC_GAP                                              0x1b79
++#define mmCRTC1_CRTC_GSL_VSYNC_GAP                                              0x1d79
++#define mmCRTC2_CRTC_GSL_VSYNC_GAP                                              0x1f79
++#define mmCRTC3_CRTC_GSL_VSYNC_GAP                                              0x4179
++#define mmCRTC4_CRTC_GSL_VSYNC_GAP                                              0x4379
++#define mmCRTC5_CRTC_GSL_VSYNC_GAP                                              0x4579
++#define mmCRTC6_CRTC_GSL_VSYNC_GAP                                              0x4779
++#define mmCRTC_GSL_WINDOW                                                       0x1b7a
++#define mmCRTC0_CRTC_GSL_WINDOW                                                 0x1b7a
++#define mmCRTC1_CRTC_GSL_WINDOW                                                 0x1d7a
++#define mmCRTC2_CRTC_GSL_WINDOW                                                 0x1f7a
++#define mmCRTC3_CRTC_GSL_WINDOW                                                 0x417a
++#define mmCRTC4_CRTC_GSL_WINDOW                                                 0x437a
++#define mmCRTC5_CRTC_GSL_WINDOW                                                 0x457a
++#define mmCRTC6_CRTC_GSL_WINDOW                                                 0x477a
++#define mmCRTC_GSL_CONTROL                                                      0x1b7b
++#define mmCRTC0_CRTC_GSL_CONTROL                                                0x1b7b
++#define mmCRTC1_CRTC_GSL_CONTROL                                                0x1d7b
++#define mmCRTC2_CRTC_GSL_CONTROL                                                0x1f7b
++#define mmCRTC3_CRTC_GSL_CONTROL                                                0x417b
++#define mmCRTC4_CRTC_GSL_CONTROL                                                0x437b
++#define mmCRTC5_CRTC_GSL_CONTROL                                                0x457b
++#define mmCRTC6_CRTC_GSL_CONTROL                                                0x477b
++#define mmCRTC_TEST_DEBUG_INDEX                                                 0x1bc6
++#define mmCRTC0_CRTC_TEST_DEBUG_INDEX                                           0x1bc6
++#define mmCRTC1_CRTC_TEST_DEBUG_INDEX                                           0x1dc6
++#define mmCRTC2_CRTC_TEST_DEBUG_INDEX                                           0x1fc6
++#define mmCRTC3_CRTC_TEST_DEBUG_INDEX                                           0x41c6
++#define mmCRTC4_CRTC_TEST_DEBUG_INDEX                                           0x43c6
++#define mmCRTC5_CRTC_TEST_DEBUG_INDEX                                           0x45c6
++#define mmCRTC6_CRTC_TEST_DEBUG_INDEX                                           0x47c6
++#define mmCRTC_TEST_DEBUG_DATA                                                  0x1bc7
++#define mmCRTC0_CRTC_TEST_DEBUG_DATA                                            0x1bc7
++#define mmCRTC1_CRTC_TEST_DEBUG_DATA                                            0x1dc7
++#define mmCRTC2_CRTC_TEST_DEBUG_DATA                                            0x1fc7
++#define mmCRTC3_CRTC_TEST_DEBUG_DATA                                            0x41c7
++#define mmCRTC4_CRTC_TEST_DEBUG_DATA                                            0x43c7
++#define mmCRTC5_CRTC_TEST_DEBUG_DATA                                            0x45c7
++#define mmCRTC6_CRTC_TEST_DEBUG_DATA                                            0x47c7
++#define mmDAC_ENABLE                                                            0x16aa
++#define mmDAC_SOURCE_SELECT                                                     0x16ab
++#define mmDAC_CRC_EN                                                            0x16ac
++#define mmDAC_CRC_CONTROL                                                       0x16ad
++#define mmDAC_CRC_SIG_RGB_MASK                                                  0x16ae
++#define mmDAC_CRC_SIG_CONTROL_MASK                                              0x16af
++#define mmDAC_CRC_SIG_RGB                                                       0x16b0
++#define mmDAC_CRC_SIG_CONTROL                                                   0x16b1
++#define mmDAC_SYNC_TRISTATE_CONTROL                                             0x16b2
++#define mmDAC_STEREOSYNC_SELECT                                                 0x16b3
++#define mmDAC_AUTODETECT_CONTROL                                                0x16b4
++#define mmDAC_AUTODETECT_CONTROL2                                               0x16b5
++#define mmDAC_AUTODETECT_CONTROL3                                               0x16b6
++#define mmDAC_AUTODETECT_STATUS                                                 0x16b7
++#define mmDAC_AUTODETECT_INT_CONTROL                                            0x16b8
++#define mmDAC_FORCE_OUTPUT_CNTL                                                 0x16b9
++#define mmDAC_FORCE_DATA                                                        0x16ba
++#define mmDAC_POWERDOWN                                                         0x16bb
++#define mmDAC_CONTROL                                                           0x16bc
++#define mmDAC_COMPARATOR_ENABLE                                                 0x16bd
++#define mmDAC_COMPARATOR_OUTPUT                                                 0x16be
++#define mmDAC_PWR_CNTL                                                          0x16bf
++#define mmDAC_DFT_CONFIG                                                        0x16c0
++#define mmDAC_FIFO_STATUS                                                       0x16c1
++#define mmDAC_TEST_DEBUG_INDEX                                                  0x16c2
++#define mmDAC_TEST_DEBUG_DATA                                                   0x16c3
++#define mmPERFCOUNTER_CNTL                                                      0x170
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                          0x170
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                          0x364
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                          0x18c8
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                          0x1b24
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                          0x1d24
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                          0x1f24
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                          0x4124
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                          0x4324
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                          0x4524
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                          0x4724
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                         0x59a0
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                         0x5f68
++#define mmPERFCOUNTER_STATE                                                     0x171
++#define mmDC_PERFMON0_PERFCOUNTER_STATE                                         0x171
++#define mmDC_PERFMON1_PERFCOUNTER_STATE                                         0x365
++#define mmDC_PERFMON2_PERFCOUNTER_STATE                                         0x18c9
++#define mmDC_PERFMON3_PERFCOUNTER_STATE                                         0x1b25
++#define mmDC_PERFMON4_PERFCOUNTER_STATE                                         0x1d25
++#define mmDC_PERFMON5_PERFCOUNTER_STATE                                         0x1f25
++#define mmDC_PERFMON6_PERFCOUNTER_STATE                                         0x4125
++#define mmDC_PERFMON7_PERFCOUNTER_STATE                                         0x4325
++#define mmDC_PERFMON8_PERFCOUNTER_STATE                                         0x4525
++#define mmDC_PERFMON9_PERFCOUNTER_STATE                                         0x4725
++#define mmDC_PERFMON10_PERFCOUNTER_STATE                                        0x59a1
++#define mmDC_PERFMON11_PERFCOUNTER_STATE                                        0x5f69
++#define mmPERFMON_CNTL                                                          0x173
++#define mmDC_PERFMON0_PERFMON_CNTL                                              0x173
++#define mmDC_PERFMON1_PERFMON_CNTL                                              0x367
++#define mmDC_PERFMON2_PERFMON_CNTL                                              0x18cb
++#define mmDC_PERFMON3_PERFMON_CNTL                                              0x1b27
++#define mmDC_PERFMON4_PERFMON_CNTL                                              0x1d27
++#define mmDC_PERFMON5_PERFMON_CNTL                                              0x1f27
++#define mmDC_PERFMON6_PERFMON_CNTL                                              0x4127
++#define mmDC_PERFMON7_PERFMON_CNTL                                              0x4327
++#define mmDC_PERFMON8_PERFMON_CNTL                                              0x4527
++#define mmDC_PERFMON9_PERFMON_CNTL                                              0x4727
++#define mmDC_PERFMON10_PERFMON_CNTL                                             0x59a3
++#define mmDC_PERFMON11_PERFMON_CNTL                                             0x5f6b
++#define mmPERFMON_CNTL2                                                         0x17a
++#define mmDC_PERFMON0_PERFMON_CNTL2                                             0x17a
++#define mmDC_PERFMON1_PERFMON_CNTL2                                             0x36e
++#define mmDC_PERFMON2_PERFMON_CNTL2                                             0x18d2
++#define mmDC_PERFMON3_PERFMON_CNTL2                                             0x1b2e
++#define mmDC_PERFMON4_PERFMON_CNTL2                                             0x1d2e
++#define mmDC_PERFMON5_PERFMON_CNTL2                                             0x1f2e
++#define mmDC_PERFMON6_PERFMON_CNTL2                                             0x412e
++#define mmDC_PERFMON7_PERFMON_CNTL2                                             0x432e
++#define mmDC_PERFMON8_PERFMON_CNTL2                                             0x452e
++#define mmDC_PERFMON9_PERFMON_CNTL2                                             0x472e
++#define mmDC_PERFMON10_PERFMON_CNTL2                                            0x59aa
++#define mmDC_PERFMON11_PERFMON_CNTL2                                            0x5f72
++#define mmPERFMON_CVALUE_INT_MISC                                               0x172
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                   0x172
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                   0x366
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                   0x18ca
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                   0x1b26
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                   0x1d26
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                   0x1f26
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                   0x4126
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                   0x4326
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                   0x4526
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                   0x4726
++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                  0x59a2
++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                  0x5f6a
++#define mmPERFMON_CVALUE_LOW                                                    0x174
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                        0x174
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                        0x368
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                        0x18cc
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                        0x1b28
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                        0x1d28
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                        0x1f28
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                        0x4128
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                        0x4328
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                        0x4528
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                        0x4728
++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                       0x59a4
++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                       0x5f6c
++#define mmPERFMON_HI                                                            0x175
++#define mmDC_PERFMON0_PERFMON_HI                                                0x175
++#define mmDC_PERFMON1_PERFMON_HI                                                0x369
++#define mmDC_PERFMON2_PERFMON_HI                                                0x18cd
++#define mmDC_PERFMON3_PERFMON_HI                                                0x1b29
++#define mmDC_PERFMON4_PERFMON_HI                                                0x1d29
++#define mmDC_PERFMON5_PERFMON_HI                                                0x1f29
++#define mmDC_PERFMON6_PERFMON_HI                                                0x4129
++#define mmDC_PERFMON7_PERFMON_HI                                                0x4329
++#define mmDC_PERFMON8_PERFMON_HI                                                0x4529
++#define mmDC_PERFMON9_PERFMON_HI                                                0x4729
++#define mmDC_PERFMON10_PERFMON_HI                                               0x59a5
++#define mmDC_PERFMON11_PERFMON_HI                                               0x5f6d
++#define mmPERFMON_LOW                                                           0x176
++#define mmDC_PERFMON0_PERFMON_LOW                                               0x176
++#define mmDC_PERFMON1_PERFMON_LOW                                               0x36a
++#define mmDC_PERFMON2_PERFMON_LOW                                               0x18ce
++#define mmDC_PERFMON3_PERFMON_LOW                                               0x1b2a
++#define mmDC_PERFMON4_PERFMON_LOW                                               0x1d2a
++#define mmDC_PERFMON5_PERFMON_LOW                                               0x1f2a
++#define mmDC_PERFMON6_PERFMON_LOW                                               0x412a
++#define mmDC_PERFMON7_PERFMON_LOW                                               0x432a
++#define mmDC_PERFMON8_PERFMON_LOW                                               0x452a
++#define mmDC_PERFMON9_PERFMON_LOW                                               0x472a
++#define mmDC_PERFMON10_PERFMON_LOW                                              0x59a6
++#define mmDC_PERFMON11_PERFMON_LOW                                              0x5f6e
++#define mmPERFMON_TEST_DEBUG_INDEX                                              0x177
++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX                                  0x177
++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX                                  0x36b
++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX                                  0x18cf
++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX                                  0x1b2b
++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX                                  0x1d2b
++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX                                  0x1f2b
++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                                  0x412b
++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                                  0x432b
++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                                  0x452b
++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                                  0x472b
++#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                                 0x59a7
++#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                                 0x5f6f
++#define mmPERFMON_TEST_DEBUG_DATA                                               0x178
++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA                                   0x178
++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA                                   0x36c
++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA                                   0x18d0
++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA                                   0x1b2c
++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA                                   0x1d2c
++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA                                   0x1f2c
++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                                   0x412c
++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                                   0x432c
++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                                   0x452c
++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                                   0x472c
++#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA                                  0x59a8
++#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA                                  0x5f70
++#define mmREFCLK_CNTL                                                           0x109
++#define mmDCCG_CBUS_WRCMD_DELAY                                                 0x110
++#define mmDPREFCLK_CNTL                                                         0x118
++#define mmAVSYNC_COUNTER_WRITE                                                  0x12a
++#define mmAVSYNC_COUNTER_CONTROL                                                0x12b
++#define mmAVSYNC_COUNTER_READ                                                   0x12f
++#define mmDCCG_GTC_CNTL                                                         0x120
++#define mmDCCG_GTC_DTO_INCR                                                     0x121
++#define mmDCCG_GTC_DTO_MODULO                                                   0x122
++#define mmDCCG_GTC_CURRENT                                                      0x123
++#define mmDCCG_DS_DTO_INCR                                                      0x113
++#define mmDCCG_DS_DTO_MODULO                                                    0x114
++#define mmDCCG_DS_CNTL                                                          0x115
++#define mmDCCG_DS_HW_CAL_INTERVAL                                               0x116
++#define mmDCCG_DS_DEBUG_CNTL                                                    0x112
++#define mmDMCU_SMU_INTERRUPT_CNTL                                               0x12c
++#define mmSMU_CONTROL                                                           0x12d
++#define mmSMU_INTERRUPT_CONTROL                                                 0x12e
++#define mmDAC_CLK_ENABLE                                                        0x128
++#define mmDVO_CLK_ENABLE                                                        0x129
++#define mmDCCG_GATE_DISABLE_CNTL                                                0x134
++#define mmDISPCLK_CGTT_BLK_CTRL_REG                                             0x135
++#define mmSCLK_CGTT_BLK_CTRL_REG                                                0x136
++#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                            0x108
++#define mmREFCLK_CGTT_BLK_CTRL_REG                                              0x10b
++#define mmDCCG_CAC_STATUS                                                       0x137
++#define mmPIXCLK1_RESYNC_CNTL                                                   0x138
++#define mmPIXCLK2_RESYNC_CNTL                                                   0x139
++#define mmPIXCLK0_RESYNC_CNTL                                                   0x13a
++#define mmMICROSECOND_TIME_BASE_DIV                                             0x13b
++#define mmDCCG_DISP_CNTL_REG                                                    0x13f
++#define mmMILLISECOND_TIME_BASE_DIV                                             0x130
++#define mmDISPCLK_FREQ_CHANGE_CNTL                                              0x131
++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                            0x132
++#define mmDCCG_PERFMON_CNTL                                                     0x133
++#define mmDCCG_PERFMON_CNTL2                                                    0x10e
++#define mmCRTC0_PIXEL_RATE_CNTL                                                 0x140
++#define mmDP_DTO0_PHASE                                                         0x141
++#define mmDP_DTO0_MODULO                                                        0x142
++#define mmCRTC1_PIXEL_RATE_CNTL                                                 0x144
++#define mmDP_DTO1_PHASE                                                         0x145
++#define mmDP_DTO1_MODULO                                                        0x146
++#define mmCRTC2_PIXEL_RATE_CNTL                                                 0x148
++#define mmDP_DTO2_PHASE                                                         0x149
++#define mmDP_DTO2_MODULO                                                        0x14a
++#define mmCRTC3_PIXEL_RATE_CNTL                                                 0x14c
++#define mmDP_DTO3_PHASE                                                         0x14d
++#define mmDP_DTO3_MODULO                                                        0x14e
++#define mmCRTC4_PIXEL_RATE_CNTL                                                 0x150
++#define mmDP_DTO4_PHASE                                                         0x151
++#define mmDP_DTO4_MODULO                                                        0x152
++#define mmCRTC5_PIXEL_RATE_CNTL                                                 0x154
++#define mmDP_DTO5_PHASE                                                         0x155
++#define mmDP_DTO5_MODULO                                                        0x156
++#define mmDCCG_SOFT_RESET                                                       0x15f
++#define mmSYMCLKA_CLOCK_ENABLE                                                  0x160
++#define mmSYMCLKB_CLOCK_ENABLE                                                  0x161
++#define mmSYMCLKC_CLOCK_ENABLE                                                  0x162
++#define mmSYMCLKD_CLOCK_ENABLE                                                  0x163
++#define mmSYMCLKE_CLOCK_ENABLE                                                  0x164
++#define mmSYMCLKF_CLOCK_ENABLE                                                  0x165
++#define mmDPDBG_CLK_FORCE_CONTROL                                               0x10d
++#define mmDVOACLKD_CNTL                                                         0x168
++#define mmDVOACLKC_MVP_CNTL                                                     0x169
++#define mmDVOACLKC_CNTL                                                         0x16a
++#define mmDCCG_AUDIO_DTO_SOURCE                                                 0x16b
++#define mmDCCG_AUDIO_DTO0_PHASE                                                 0x16c
++#define mmDCCG_AUDIO_DTO0_MODULE                                                0x16d
++#define mmDCCG_AUDIO_DTO1_PHASE                                                 0x16e
++#define mmDCCG_AUDIO_DTO1_MODULE                                                0x16f
++#define mmDCCG_TEST_DEBUG_INDEX                                                 0x17c
++#define mmDCCG_TEST_DEBUG_DATA                                                  0x17d
++#define mmDCCG_TEST_CLK_SEL                                                     0x17e
++#define mmCPLL_MACRO_CNTL_RESERVED0                                             0x5fd0
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0                                  0x5fd0
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                                  0x5fdc
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                                  0x5fe8
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                                  0x5ff4
++#define mmCPLL_MACRO_CNTL_RESERVED1                                             0x5fd1
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1                                  0x5fd1
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                                  0x5fdd
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                                  0x5fe9
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                                  0x5ff5
++#define mmCPLL_MACRO_CNTL_RESERVED2                                             0x5fd2
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2                                  0x5fd2
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                                  0x5fde
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                                  0x5fea
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                                  0x5ff6
++#define mmCPLL_MACRO_CNTL_RESERVED3                                             0x5fd3
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3                                  0x5fd3
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                                  0x5fdf
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                                  0x5feb
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                                  0x5ff7
++#define mmCPLL_MACRO_CNTL_RESERVED4                                             0x5fd4
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4                                  0x5fd4
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                                  0x5fe0
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                                  0x5fec
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                                  0x5ff8
++#define mmCPLL_MACRO_CNTL_RESERVED5                                             0x5fd5
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5                                  0x5fd5
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                                  0x5fe1
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                                  0x5fed
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                                  0x5ff9
++#define mmCPLL_MACRO_CNTL_RESERVED6                                             0x5fd6
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6                                  0x5fd6
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                                  0x5fe2
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                                  0x5fee
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                                  0x5ffa
++#define mmCPLL_MACRO_CNTL_RESERVED7                                             0x5fd7
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7                                  0x5fd7
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                                  0x5fe3
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                                  0x5fef
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                                  0x5ffb
++#define mmCPLL_MACRO_CNTL_RESERVED8                                             0x5fd8
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8                                  0x5fd8
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                                  0x5fe4
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                                  0x5ff0
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                                  0x5ffc
++#define mmCPLL_MACRO_CNTL_RESERVED9                                             0x5fd9
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9                                  0x5fd9
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                                  0x5fe5
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                                  0x5ff1
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                                  0x5ffd
++#define mmCPLL_MACRO_CNTL_RESERVED10                                            0x5fda
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10                                 0x5fda
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                                 0x5fe6
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                                 0x5ff2
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                                 0x5ffe
++#define mmCPLL_MACRO_CNTL_RESERVED11                                            0x5fdb
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11                                 0x5fdb
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                                 0x5fe7
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                                 0x5ff3
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                                 0x5fff
++#define mmPLL_MACRO_CNTL_RESERVED0                                              0x1700
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0                                    0x1700
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0                                    0x172a
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0                                    0x1754
++#define mmPLL_MACRO_CNTL_RESERVED1                                              0x1701
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1                                    0x1701
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1                                    0x172b
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1                                    0x1755
++#define mmPLL_MACRO_CNTL_RESERVED2                                              0x1702
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2                                    0x1702
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2                                    0x172c
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2                                    0x1756
++#define mmPLL_MACRO_CNTL_RESERVED3                                              0x1703
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3                                    0x1703
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3                                    0x172d
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3                                    0x1757
++#define mmPLL_MACRO_CNTL_RESERVED4                                              0x1704
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4                                    0x1704
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4                                    0x172e
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4                                    0x1758
++#define mmPLL_MACRO_CNTL_RESERVED5                                              0x1705
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5                                    0x1705
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5                                    0x172f
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5                                    0x1759
++#define mmPLL_MACRO_CNTL_RESERVED6                                              0x1706
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6                                    0x1706
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6                                    0x1730
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6                                    0x175a
++#define mmPLL_MACRO_CNTL_RESERVED7                                              0x1707
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7                                    0x1707
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7                                    0x1731
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7                                    0x175b
++#define mmPLL_MACRO_CNTL_RESERVED8                                              0x1708
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8                                    0x1708
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8                                    0x1732
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8                                    0x175c
++#define mmPLL_MACRO_CNTL_RESERVED9                                              0x1709
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9                                    0x1709
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9                                    0x1733
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9                                    0x175d
++#define mmPLL_MACRO_CNTL_RESERVED10                                             0x170a
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10                                   0x170a
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10                                   0x1734
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10                                   0x175e
++#define mmPLL_MACRO_CNTL_RESERVED11                                             0x170b
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11                                   0x170b
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11                                   0x1735
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11                                   0x175f
++#define mmPLL_MACRO_CNTL_RESERVED12                                             0x170c
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12                                   0x170c
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12                                   0x1736
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12                                   0x1760
++#define mmPLL_MACRO_CNTL_RESERVED13                                             0x170d
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13                                   0x170d
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13                                   0x1737
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13                                   0x1761
++#define mmPLL_MACRO_CNTL_RESERVED14                                             0x170e
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14                                   0x170e
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14                                   0x1738
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14                                   0x1762
++#define mmPLL_MACRO_CNTL_RESERVED15                                             0x170f
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15                                   0x170f
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15                                   0x1739
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15                                   0x1763
++#define mmPLL_MACRO_CNTL_RESERVED16                                             0x1710
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16                                   0x1710
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16                                   0x173a
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16                                   0x1764
++#define mmPLL_MACRO_CNTL_RESERVED17                                             0x1711
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17                                   0x1711
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17                                   0x173b
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17                                   0x1765
++#define mmPLL_MACRO_CNTL_RESERVED18                                             0x1712
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18                                   0x1712
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18                                   0x173c
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18                                   0x1766
++#define mmPLL_MACRO_CNTL_RESERVED19                                             0x1713
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19                                   0x1713
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19                                   0x173d
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19                                   0x1767
++#define mmPLL_MACRO_CNTL_RESERVED20                                             0x1714
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20                                   0x1714
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20                                   0x173e
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20                                   0x1768
++#define mmPLL_MACRO_CNTL_RESERVED21                                             0x1715
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21                                   0x1715
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21                                   0x173f
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21                                   0x1769
++#define mmPLL_MACRO_CNTL_RESERVED22                                             0x1716
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22                                   0x1716
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22                                   0x1740
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22                                   0x176a
++#define mmPLL_MACRO_CNTL_RESERVED23                                             0x1717
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23                                   0x1717
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23                                   0x1741
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23                                   0x176b
++#define mmPLL_MACRO_CNTL_RESERVED24                                             0x1718
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24                                   0x1718
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24                                   0x1742
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24                                   0x176c
++#define mmPLL_MACRO_CNTL_RESERVED25                                             0x1719
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25                                   0x1719
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25                                   0x1743
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25                                   0x176d
++#define mmPLL_MACRO_CNTL_RESERVED26                                             0x171a
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26                                   0x171a
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26                                   0x1744
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26                                   0x176e
++#define mmPLL_MACRO_CNTL_RESERVED27                                             0x171b
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27                                   0x171b
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27                                   0x1745
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27                                   0x176f
++#define mmPLL_MACRO_CNTL_RESERVED28                                             0x171c
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28                                   0x171c
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28                                   0x1746
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28                                   0x1770
++#define mmPLL_MACRO_CNTL_RESERVED29                                             0x171d
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29                                   0x171d
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29                                   0x1747
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29                                   0x1771
++#define mmPLL_MACRO_CNTL_RESERVED30                                             0x171e
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30                                   0x171e
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30                                   0x1748
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30                                   0x1772
++#define mmPLL_MACRO_CNTL_RESERVED31                                             0x171f
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31                                   0x171f
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31                                   0x1749
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31                                   0x1773
++#define mmPLL_MACRO_CNTL_RESERVED32                                             0x1720
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32                                   0x1720
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32                                   0x174a
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32                                   0x1774
++#define mmPLL_MACRO_CNTL_RESERVED33                                             0x1721
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33                                   0x1721
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33                                   0x174b
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33                                   0x1775
++#define mmPLL_MACRO_CNTL_RESERVED34                                             0x1722
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34                                   0x1722
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34                                   0x174c
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34                                   0x1776
++#define mmPLL_MACRO_CNTL_RESERVED35                                             0x1723
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35                                   0x1723
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35                                   0x174d
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35                                   0x1777
++#define mmPLL_MACRO_CNTL_RESERVED36                                             0x1724
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36                                   0x1724
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36                                   0x174e
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36                                   0x1778
++#define mmPLL_MACRO_CNTL_RESERVED37                                             0x1725
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37                                   0x1725
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37                                   0x174f
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37                                   0x1779
++#define mmPLL_MACRO_CNTL_RESERVED38                                             0x1726
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38                                   0x1726
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38                                   0x1750
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38                                   0x177a
++#define mmPLL_MACRO_CNTL_RESERVED39                                             0x1727
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39                                   0x1727
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39                                   0x1751
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39                                   0x177b
++#define mmPLL_MACRO_CNTL_RESERVED40                                             0x1728
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40                                   0x1728
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40                                   0x1752
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40                                   0x177c
++#define mmPLL_MACRO_CNTL_RESERVED41                                             0x1729
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41                                   0x1729
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41                                   0x1753
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41                                   0x177d
++#define mmDENTIST_DISPCLK_CNTL                                                  0x124
++#define mmDCDEBUG_BUS_CLK1_SEL                                                  0x16c4
++#define mmDCDEBUG_BUS_CLK2_SEL                                                  0x16c5
++#define mmDCDEBUG_BUS_CLK3_SEL                                                  0x16c6
++#define mmDCDEBUG_BUS_CLK4_SEL                                                  0x16c7
++#define mmDCDEBUG_BUS_CLK5_SEL                                                  0x16c8
++#define mmDCDEBUG_OUT_PIN_OVERRIDE                                              0x16c9
++#define mmDCDEBUG_OUT_CNTL                                                      0x16ca
++#define mmDCDEBUG_OUT_DATA                                                      0x16cb
++#define mmDMIF_ADDR_CONFIG                                                      0x2f5
++#define mmDMIF_CONTROL                                                          0x2f6
++#define mmDMIF_STATUS                                                           0x2f7
++#define mmDMIF_HW_DEBUG                                                         0x2f8
++#define mmDMIF_ARBITRATION_CONTROL                                              0x2f9
++#define mmPIPE0_ARBITRATION_CONTROL3                                            0x2fa
++#define mmPIPE1_ARBITRATION_CONTROL3                                            0x2fb
++#define mmPIPE2_ARBITRATION_CONTROL3                                            0x2fc
++#define mmPIPE3_ARBITRATION_CONTROL3                                            0x2fd
++#define mmPIPE4_ARBITRATION_CONTROL3                                            0x2fe
++#define mmPIPE5_ARBITRATION_CONTROL3                                            0x2ff
++#define mmPIPE6_ARBITRATION_CONTROL3                                            0x32a
++#define mmPIPE7_ARBITRATION_CONTROL3                                            0x32b
++#define mmDMIF_P_VMID                                                           0x300
++#define mmDMIF_URG_OVERRIDE                                                     0x329
++#define mmDMIF_TEST_DEBUG_INDEX                                                 0x301
++#define mmDMIF_TEST_DEBUG_DATA                                                  0x302
++#define ixDMIF_DEBUG02_CORE0                                                    0x2
++#define ixDMIF_DEBUG02_CORE1                                                    0xa
++#define mmDMIF_ADDR_CALC                                                        0x303
++#define mmDMIF_STATUS2                                                          0x304
++#define mmPIPE0_MAX_REQUESTS                                                    0x305
++#define mmPIPE1_MAX_REQUESTS                                                    0x306
++#define mmPIPE2_MAX_REQUESTS                                                    0x307
++#define mmPIPE3_MAX_REQUESTS                                                    0x308
++#define mmPIPE4_MAX_REQUESTS                                                    0x309
++#define mmPIPE5_MAX_REQUESTS                                                    0x30a
++#define mmPIPE6_MAX_REQUESTS                                                    0x32c
++#define mmPIPE7_MAX_REQUESTS                                                    0x32d
++#define mmLOW_POWER_TILING_CONTROL                                              0x30b
++#define mmMCIF_CONTROL                                                          0x30c
++#define mmMCIF_WRITE_COMBINE_CONTROL                                            0x30d
++#define mmMCIF_TEST_DEBUG_INDEX                                                 0x30e
++#define mmMCIF_TEST_DEBUG_DATA                                                  0x30f
++#define ixIDDCCIF02_DBG_DCCIF_C                                                 0x9
++#define ixIDDCCIF04_DBG_DCCIF_E                                                 0xb
++#define ixIDDCCIF05_DBG_DCCIF_F                                                 0xc
++#define mmMCIF_VMID                                                             0x310
++#define mmMCIF_MEM_CONTROL                                                      0x311
++#define mmCC_DC_PIPE_DIS                                                        0x312
++#define mmMC_DC_INTERFACE_NACK_STATUS                                           0x313
++#define mmRBBMIF_TIMEOUT                                                        0x314
++#define mmRBBMIF_STATUS                                                         0x315
++#define mmRBBMIF_TIMEOUT_DIS                                                    0x316
++#define mmRBBMIF_STATUS_FLAG                                                    0x327
++#define mmDCI_MEM_PWR_STATUS                                                    0x317
++#define mmDCI_MEM_PWR_STATUS2                                                   0x318
++#define mmDCI_CLK_CNTL                                                          0x319
++#define mmDCI_MEM_PWR_CNTL                                                      0x31b
++#define mmDCI_MEM_PWR_CNTL2                                                     0x31c
++#define mmDCI_MEM_PWR_CNTL3                                                     0x31d
++#define mmDCI_SOFT_RESET                                                        0x328
++#define mmDCI_TEST_DEBUG_INDEX                                                  0x31e
++#define mmDCI_TEST_DEBUG_DATA                                                   0x31f
++#define mmDCI_DEBUG_CONFIG                                                      0x320
++#define mmPIPE0_DMIF_BUFFER_CONTROL                                             0x321
++#define mmPIPE1_DMIF_BUFFER_CONTROL                                             0x322
++#define mmPIPE2_DMIF_BUFFER_CONTROL                                             0x323
++#define mmPIPE3_DMIF_BUFFER_CONTROL                                             0x324
++#define mmPIPE4_DMIF_BUFFER_CONTROL                                             0x325
++#define mmPIPE5_DMIF_BUFFER_CONTROL                                             0x326
++#define mmDC_GENERICA                                                           0x4800
++#define mmDC_GENERICB                                                           0x4801
++#define mmDC_PAD_EXTERN_SIG                                                     0x4802
++#define mmDC_REF_CLK_CNTL                                                       0x4803
++#define mmDC_GPIO_DEBUG                                                         0x4804
++#define mmUNIPHYA_LINK_CNTL                                                     0x4805
++#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                             0x4806
++#define mmUNIPHYB_LINK_CNTL                                                     0x4807
++#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                             0x4808
++#define mmUNIPHYC_LINK_CNTL                                                     0x4809
++#define mmUNIPHYC_CHANNEL_XBAR_CNTL                                             0x480a
++#define mmUNIPHYD_LINK_CNTL                                                     0x480b
++#define mmUNIPHYD_CHANNEL_XBAR_CNTL                                             0x480c
++#define mmUNIPHYE_LINK_CNTL                                                     0x480d
++#define mmUNIPHYE_CHANNEL_XBAR_CNTL                                             0x480e
++#define mmUNIPHYF_LINK_CNTL                                                     0x480f
++#define mmUNIPHYF_CHANNEL_XBAR_CNTL                                             0x4810
++#define mmUNIPHYG_LINK_CNTL                                                     0x4811
++#define mmUNIPHYG_CHANNEL_XBAR_CNTL                                             0x4812
++#define mmUNIPHY_IMPCAL_LINKA                                                   0x4838
++#define mmUNIPHY_IMPCAL_LINKB                                                   0x4839
++#define mmUNIPHY_IMPCAL_LINKC                                                   0x483f
++#define mmUNIPHY_IMPCAL_LINKD                                                   0x4840
++#define mmUNIPHY_IMPCAL_LINKE                                                   0x4843
++#define mmUNIPHY_IMPCAL_LINKF                                                   0x4844
++#define mmUNIPHY_IMPCAL_PERIOD                                                  0x483a
++#define mmAUXP_IMPCAL                                                           0x483b
++#define mmAUXN_IMPCAL                                                           0x483c
++#define mmDCIO_IMPCAL_CNTL                                                      0x483d
++#define mmUNIPHY_IMPCAL_PSW_AB                                                  0x483e
++#define mmDCIO_IMPCAL_CNTL_CD                                                   0x4841
++#define mmUNIPHY_IMPCAL_PSW_CD                                                  0x4842
++#define mmDCIO_IMPCAL_CNTL_EF                                                   0x4845
++#define mmUNIPHY_IMPCAL_PSW_EF                                                  0x4846
++#define mmDCIO_WRCMD_DELAY                                                      0x4816
++#define mmDC_PINSTRAPS                                                          0x4818
++#define mmDC_DVODATA_CONFIG                                                     0x481a
++#define mmLVTMA_PWRSEQ_CNTL                                                     0x481b
++#define mmLVTMA_PWRSEQ_STATE                                                    0x481c
++#define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
++#define mmLVTMA_PWRSEQ_DELAY1                                                   0x481e
++#define mmLVTMA_PWRSEQ_DELAY2                                                   0x481f
++#define mmBL_PWM_CNTL                                                           0x4820
++#define mmBL_PWM_CNTL2                                                          0x4821
++#define mmBL_PWM_PERIOD_CNTL                                                    0x4822
++#define mmBL_PWM_GRP1_REG_LOCK                                                  0x4823
++#define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                            0x4825
++#define mmDCIO_GSL0_CNTL                                                        0x4826
++#define mmDCIO_GSL1_CNTL                                                        0x4827
++#define mmDCIO_GSL2_CNTL                                                        0x4828
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                  0x4829
++#define mmDC_GPU_TIMER_START_POSITION_P_FLIP                                    0x482a
++#define mmDC_GPU_TIMER_READ                                                     0x482b
++#define mmDC_GPU_TIMER_READ_CNTL                                                0x482c
++#define mmDCIO_CLOCK_CNTL                                                       0x482d
++#define mmDCIO_DEBUG                                                            0x482f
++#define mmDCO_DCFE_EXT_VSYNC_CNTL                                               0x4830
++#define mmDBG_OUT_CNTL                                                          0x4834
++#define mmDCIO_DEBUG_CONFIG                                                     0x4835
++#define mmDCIO_SOFT_RESET                                                       0x4836
++#define mmDCIO_DPHY_SEL                                                         0x4837
++#define mmDCIO_TEST_DEBUG_INDEX                                                 0x4831
++#define mmDCIO_TEST_DEBUG_DATA                                                  0x4832
++#define ixDCIO_DEBUG1                                                           0x1
++#define ixDCIO_DEBUG2                                                           0x2
++#define ixDCIO_DEBUG3                                                           0x3
++#define ixDCIO_DEBUG4                                                           0x4
++#define ixDCIO_DEBUG5                                                           0x5
++#define ixDCIO_DEBUG6                                                           0x6
++#define ixDCIO_DEBUG7                                                           0x7
++#define ixDCIO_DEBUG8                                                           0x8
++#define ixDCIO_DEBUG9                                                           0x9
++#define ixDCIO_DEBUGA                                                           0xa
++#define ixDCIO_DEBUGB                                                           0xb
++#define ixDCIO_DEBUGC                                                           0xc
++#define ixDCIO_DEBUGD                                                           0xd
++#define ixDCIO_DEBUGE                                                           0xe
++#define ixDCIO_DEBUGF                                                           0xf
++#define ixDCIO_DEBUG10                                                          0x10
++#define ixDCIO_DEBUG11                                                          0x11
++#define ixDCIO_DEBUG12                                                          0x12
++#define ixDCIO_DEBUG13                                                          0x13
++#define ixDCIO_DEBUG14                                                          0x14
++#define ixDCIO_DEBUG15                                                          0x15
++#define ixDCIO_DEBUG16                                                          0x16
++#define ixDCIO_DEBUG_ID                                                         0x0
++#define mmDC_GPIO_GENERIC_MASK                                                  0x4860
++#define mmDC_GPIO_GENERIC_A                                                     0x4861
++#define mmDC_GPIO_GENERIC_EN                                                    0x4862
++#define mmDC_GPIO_GENERIC_Y                                                     0x4863
++#define mmDC_GPIO_DVODATA_MASK                                                  0x4864
++#define mmDC_GPIO_DVODATA_A                                                     0x4865
++#define mmDC_GPIO_DVODATA_EN                                                    0x4866
++#define mmDC_GPIO_DVODATA_Y                                                     0x4867
++#define mmDC_GPIO_DDC1_MASK                                                     0x4868
++#define mmDC_GPIO_DDC1_A                                                        0x4869
++#define mmDC_GPIO_DDC1_EN                                                       0x486a
++#define mmDC_GPIO_DDC1_Y                                                        0x486b
++#define mmDC_GPIO_DDC2_MASK                                                     0x486c
++#define mmDC_GPIO_DDC2_A                                                        0x486d
++#define mmDC_GPIO_DDC2_EN                                                       0x486e
++#define mmDC_GPIO_DDC2_Y                                                        0x486f
++#define mmDC_GPIO_DDC3_MASK                                                     0x4870
++#define mmDC_GPIO_DDC3_A                                                        0x4871
++#define mmDC_GPIO_DDC3_EN                                                       0x4872
++#define mmDC_GPIO_DDC3_Y                                                        0x4873
++#define mmDC_GPIO_DDC4_MASK                                                     0x4874
++#define mmDC_GPIO_DDC4_A                                                        0x4875
++#define mmDC_GPIO_DDC4_EN                                                       0x4876
++#define mmDC_GPIO_DDC4_Y                                                        0x4877
++#define mmDC_GPIO_DDC5_MASK                                                     0x4878
++#define mmDC_GPIO_DDC5_A                                                        0x4879
++#define mmDC_GPIO_DDC5_EN                                                       0x487a
++#define mmDC_GPIO_DDC5_Y                                                        0x487b
++#define mmDC_GPIO_DDC6_MASK                                                     0x487c
++#define mmDC_GPIO_DDC6_A                                                        0x487d
++#define mmDC_GPIO_DDC6_EN                                                       0x487e
++#define mmDC_GPIO_DDC6_Y                                                        0x487f
++#define mmDC_GPIO_DDCVGA_MASK                                                   0x4880
++#define mmDC_GPIO_DDCVGA_A                                                      0x4881
++#define mmDC_GPIO_DDCVGA_EN                                                     0x4882
++#define mmDC_GPIO_DDCVGA_Y                                                      0x4883
++#define mmDC_GPIO_SYNCA_MASK                                                    0x4884
++#define mmDC_GPIO_SYNCA_A                                                       0x4885
++#define mmDC_GPIO_SYNCA_EN                                                      0x4886
++#define mmDC_GPIO_SYNCA_Y                                                       0x4887
++#define mmDC_GPIO_GENLK_MASK                                                    0x4888
++#define mmDC_GPIO_GENLK_A                                                       0x4889
++#define mmDC_GPIO_GENLK_EN                                                      0x488a
++#define mmDC_GPIO_GENLK_Y                                                       0x488b
++#define mmDC_GPIO_HPD_MASK                                                      0x488c
++#define mmDC_GPIO_HPD_A                                                         0x488d
++#define mmDC_GPIO_HPD_EN                                                        0x488e
++#define mmDC_GPIO_HPD_Y                                                         0x488f
++#define mmDC_GPIO_PWRSEQ_MASK                                                   0x4890
++#define mmDC_GPIO_PWRSEQ_A                                                      0x4891
++#define mmDC_GPIO_PWRSEQ_EN                                                     0x4892
++#define mmDC_GPIO_PWRSEQ_Y                                                      0x4893
++#define mmDC_GPIO_PAD_STRENGTH_1                                                0x4894
++#define mmDC_GPIO_PAD_STRENGTH_2                                                0x4895
++#define mmPHY_AUX_CNTL                                                          0x4897
++#define mmDC_GPIO_I2CPAD_A                                                      0x4899
++#define mmDC_GPIO_I2CPAD_EN                                                     0x489a
++#define mmDC_GPIO_I2CPAD_Y                                                      0x489b
++#define mmDC_GPIO_I2CPAD_STRENGTH                                               0x489c
++#define mmDVO_STRENGTH_CONTROL                                                  0x489d
++#define mmDVO_VREF_CONTROL                                                      0x489e
++#define mmDVO_SKEW_ADJUST                                                       0x489f
++#define mmDAC_MACRO_CNTL_RESERVED0                                              0x48b8
++#define mmDAC_MACRO_CNTL_RESERVED1                                              0x48b9
++#define mmDAC_MACRO_CNTL_RESERVED2                                              0x48ba
++#define mmDAC_MACRO_CNTL_RESERVED3                                              0x48bb
++#define mmUNIPHY_MACRO_CNTL_RESERVED0                                           0x48c0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                              0x48c0
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                              0x48e0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                              0x4900
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                              0x4920
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                              0x4940
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0                              0x4960
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0                              0x4980
++#define mmUNIPHY_MACRO_CNTL_RESERVED1                                           0x48c1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                              0x48c1
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                              0x48e1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                              0x4901
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                              0x4921
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                              0x4941
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1                              0x4961
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1                              0x4981
++#define mmUNIPHY_MACRO_CNTL_RESERVED2                                           0x48c2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                              0x48c2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                              0x48e2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                              0x4902
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                              0x4922
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                              0x4942
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2                              0x4962
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2                              0x4982
++#define mmUNIPHY_MACRO_CNTL_RESERVED3                                           0x48c3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                              0x48c3
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                              0x48e3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                              0x4903
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                              0x4923
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                              0x4943
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3                              0x4963
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3                              0x4983
++#define mmUNIPHY_MACRO_CNTL_RESERVED4                                           0x48c4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                              0x48c4
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                              0x48e4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                              0x4904
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                              0x4924
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                              0x4944
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4                              0x4964
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4                              0x4984
++#define mmUNIPHY_MACRO_CNTL_RESERVED5                                           0x48c5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                              0x48c5
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                              0x48e5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                              0x4905
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                              0x4925
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                              0x4945
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5                              0x4965
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5                              0x4985
++#define mmUNIPHY_MACRO_CNTL_RESERVED6                                           0x48c6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                              0x48c6
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                              0x48e6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                              0x4906
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                              0x4926
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                              0x4946
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6                              0x4966
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6                              0x4986
++#define mmUNIPHY_MACRO_CNTL_RESERVED7                                           0x48c7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                              0x48c7
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                              0x48e7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                              0x4907
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                              0x4927
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                              0x4947
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7                              0x4967
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7                              0x4987
++#define mmUNIPHY_MACRO_CNTL_RESERVED8                                           0x48c8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                              0x48c8
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                              0x48e8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                              0x4908
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                              0x4928
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                              0x4948
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8                              0x4968
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8                              0x4988
++#define mmUNIPHY_MACRO_CNTL_RESERVED9                                           0x48c9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                              0x48c9
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                              0x48e9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                              0x4909
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                              0x4929
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                              0x4949
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9                              0x4969
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9                              0x4989
++#define mmUNIPHY_MACRO_CNTL_RESERVED10                                          0x48ca
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                             0x48ca
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                             0x48ea
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                             0x490a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                             0x492a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                             0x494a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10                             0x496a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10                             0x498a
++#define mmUNIPHY_MACRO_CNTL_RESERVED11                                          0x48cb
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                             0x48cb
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                             0x48eb
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                             0x490b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                             0x492b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                             0x494b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11                             0x496b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11                             0x498b
++#define mmUNIPHY_MACRO_CNTL_RESERVED12                                          0x48cc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                             0x48cc
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                             0x48ec
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                             0x490c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                             0x492c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                             0x494c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12                             0x496c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12                             0x498c
++#define mmUNIPHY_MACRO_CNTL_RESERVED13                                          0x48cd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                             0x48cd
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                             0x48ed
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                             0x490d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                             0x492d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                             0x494d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13                             0x496d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13                             0x498d
++#define mmUNIPHY_MACRO_CNTL_RESERVED14                                          0x48ce
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                             0x48ce
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                             0x48ee
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                             0x490e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                             0x492e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                             0x494e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14                             0x496e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14                             0x498e
++#define mmUNIPHY_MACRO_CNTL_RESERVED15                                          0x48cf
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                             0x48cf
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                             0x48ef
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                             0x490f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                             0x492f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                             0x494f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15                             0x496f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15                             0x498f
++#define mmUNIPHY_MACRO_CNTL_RESERVED16                                          0x48d0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                             0x48d0
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                             0x48f0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                             0x4910
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                             0x4930
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                             0x4950
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16                             0x4970
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16                             0x4990
++#define mmUNIPHY_MACRO_CNTL_RESERVED17                                          0x48d1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                             0x48d1
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                             0x48f1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                             0x4911
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                             0x4931
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                             0x4951
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17                             0x4971
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17                             0x4991
++#define mmUNIPHY_MACRO_CNTL_RESERVED18                                          0x48d2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                             0x48d2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                             0x48f2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                             0x4912
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                             0x4932
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                             0x4952
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18                             0x4972
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18                             0x4992
++#define mmUNIPHY_MACRO_CNTL_RESERVED19                                          0x48d3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                             0x48d3
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                             0x48f3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                             0x4913
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                             0x4933
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                             0x4953
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19                             0x4973
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19                             0x4993
++#define mmUNIPHY_MACRO_CNTL_RESERVED20                                          0x48d4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                             0x48d4
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                             0x48f4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                             0x4914
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                             0x4934
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                             0x4954
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20                             0x4974
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20                             0x4994
++#define mmUNIPHY_MACRO_CNTL_RESERVED21                                          0x48d5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                             0x48d5
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                             0x48f5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                             0x4915
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                             0x4935
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                             0x4955
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21                             0x4975
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21                             0x4995
++#define mmUNIPHY_MACRO_CNTL_RESERVED22                                          0x48d6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                             0x48d6
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                             0x48f6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                             0x4916
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                             0x4936
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                             0x4956
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22                             0x4976
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22                             0x4996
++#define mmUNIPHY_MACRO_CNTL_RESERVED23                                          0x48d7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                             0x48d7
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                             0x48f7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                             0x4917
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                             0x4937
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                             0x4957
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23                             0x4977
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23                             0x4997
++#define mmUNIPHY_MACRO_CNTL_RESERVED24                                          0x48d8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                             0x48d8
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                             0x48f8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                             0x4918
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                             0x4938
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                             0x4958
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24                             0x4978
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24                             0x4998
++#define mmUNIPHY_MACRO_CNTL_RESERVED25                                          0x48d9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                             0x48d9
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                             0x48f9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                             0x4919
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                             0x4939
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                             0x4959
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25                             0x4979
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25                             0x4999
++#define mmUNIPHY_MACRO_CNTL_RESERVED26                                          0x48da
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                             0x48da
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                             0x48fa
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                             0x491a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                             0x493a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                             0x495a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26                             0x497a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26                             0x499a
++#define mmUNIPHY_MACRO_CNTL_RESERVED27                                          0x48db
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                             0x48db
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                             0x48fb
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                             0x491b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                             0x493b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                             0x495b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27                             0x497b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27                             0x499b
++#define mmUNIPHY_MACRO_CNTL_RESERVED28                                          0x48dc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                             0x48dc
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                             0x48fc
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                             0x491c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                             0x493c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                             0x495c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28                             0x497c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28                             0x499c
++#define mmUNIPHY_MACRO_CNTL_RESERVED29                                          0x48dd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                             0x48dd
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                             0x48fd
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                             0x491d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                             0x493d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                             0x495d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29                             0x497d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29                             0x499d
++#define mmUNIPHY_MACRO_CNTL_RESERVED30                                          0x48de
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                             0x48de
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                             0x48fe
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                             0x491e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                             0x493e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                             0x495e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30                             0x497e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30                             0x499e
++#define mmUNIPHY_MACRO_CNTL_RESERVED31                                          0x48df
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                             0x48df
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                             0x48ff
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                             0x491f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                             0x493f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                             0x495f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31                             0x497f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31                             0x499f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED0                                         0x5a84
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED1                                         0x5a85
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED2                                         0x5a86
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED3                                         0x5a87
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED4                                         0x5a88
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED5                                         0x5a89
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED6                                         0x5a8a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED7                                         0x5a8b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED8                                         0x5a8c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED9                                         0x5a8d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED10                                        0x5a8e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED11                                        0x5a8f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED12                                        0x5a90
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED13                                        0x5a91
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED14                                        0x5a92
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED15                                        0x5a93
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED16                                        0x5a94
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED17                                        0x5a95
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED18                                        0x5a96
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED19                                        0x5a97
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED20                                        0x5a98
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED21                                        0x5a99
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED22                                        0x5a9a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED23                                        0x5a9b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED24                                        0x5a9c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED25                                        0x5a9d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED26                                        0x5a9e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED27                                        0x5a9f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED28                                        0x5aa0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED29                                        0x5aa1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED30                                        0x5aa2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED31                                        0x5aa3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED32                                        0x5aa4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED33                                        0x5aa5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED34                                        0x5aa6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED35                                        0x5aa7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED36                                        0x5aa8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED37                                        0x5aa9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED38                                        0x5aaa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED39                                        0x5aab
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED40                                        0x5aac
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED41                                        0x5aad
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED42                                        0x5aae
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED43                                        0x5aaf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED44                                        0x5ab0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED45                                        0x5ab1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED46                                        0x5ab2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED47                                        0x5ab3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED48                                        0x5ab4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED49                                        0x5ab5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED50                                        0x5ab6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED51                                        0x5ab7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED52                                        0x5ab8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED53                                        0x5ab9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED54                                        0x5aba
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED55                                        0x5abb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED56                                        0x5abc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED57                                        0x5abd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED58                                        0x5abe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED59                                        0x5abf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED60                                        0x5ac0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED61                                        0x5ac1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED62                                        0x5ac2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED63                                        0x5ac3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED64                                        0x5ac4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED65                                        0x5ac5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED66                                        0x5ac6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED67                                        0x5ac7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED68                                        0x5ac8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED69                                        0x5ac9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED70                                        0x5aca
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED71                                        0x5acb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED72                                        0x5acc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED73                                        0x5acd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED74                                        0x5ace
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED75                                        0x5acf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED76                                        0x5ad0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED77                                        0x5ad1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED78                                        0x5ad2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED79                                        0x5ad3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED80                                        0x5ad4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED81                                        0x5ad5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED82                                        0x5ad6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED83                                        0x5ad7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED84                                        0x5ad8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED85                                        0x5ad9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED86                                        0x5ada
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED87                                        0x5adb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED88                                        0x5adc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED89                                        0x5add
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED90                                        0x5ade
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED91                                        0x5adf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED92                                        0x5ae0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED93                                        0x5ae1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED94                                        0x5ae2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED95                                        0x5ae3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED96                                        0x5ae4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED97                                        0x5ae5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED98                                        0x5ae6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED99                                        0x5ae7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED100                                       0x5ae8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED101                                       0x5ae9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED102                                       0x5aea
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED103                                       0x5aeb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED104                                       0x5aec
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED105                                       0x5aed
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED106                                       0x5aee
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED107                                       0x5aef
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED108                                       0x5af0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED109                                       0x5af1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED110                                       0x5af2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED111                                       0x5af3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED112                                       0x5af4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED113                                       0x5af5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED114                                       0x5af6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED115                                       0x5af7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED116                                       0x5af8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED117                                       0x5af9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED118                                       0x5afa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED119                                       0x5afb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED120                                       0x5afc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED121                                       0x5afd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED122                                       0x5afe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED123                                       0x5aff
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED124                                       0x5b00
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED125                                       0x5b01
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED126                                       0x5b02
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED127                                       0x5b03
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED128                                       0x5b04
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED129                                       0x5b05
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED130                                       0x5b06
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED131                                       0x5b07
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED132                                       0x5b08
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED133                                       0x5b09
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED134                                       0x5b0a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED135                                       0x5b0b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED136                                       0x5b0c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED137                                       0x5b0d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED138                                       0x5b0e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED139                                       0x5b0f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED140                                       0x5b10
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED141                                       0x5b11
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED142                                       0x5b12
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED143                                       0x5b13
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED144                                       0x5b14
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED145                                       0x5b15
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED146                                       0x5b16
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED147                                       0x5b17
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED148                                       0x5b18
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED149                                       0x5b19
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED150                                       0x5b1a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED151                                       0x5b1b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED152                                       0x5b1c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED153                                       0x5b1d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED154                                       0x5b1e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED155                                       0x5b1f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED156                                       0x5b20
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED157                                       0x5b21
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED158                                       0x5b22
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED159                                       0x5b23
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED160                                       0x5b24
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED161                                       0x5b25
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED162                                       0x5b26
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED163                                       0x5b27
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED164                                       0x5b28
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED165                                       0x5b29
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED166                                       0x5b2a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED167                                       0x5b2b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED168                                       0x5b2c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED169                                       0x5b2d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED170                                       0x5b2e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED171                                       0x5b2f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED172                                       0x5b30
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED173                                       0x5b31
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED174                                       0x5b32
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED175                                       0x5b33
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED176                                       0x5b34
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED177                                       0x5b35
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED178                                       0x5b36
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED179                                       0x5b37
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED180                                       0x5b38
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED181                                       0x5b39
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED182                                       0x5b3a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED183                                       0x5b3b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED184                                       0x5b3c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED185                                       0x5b3d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED186                                       0x5b3e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED187                                       0x5b3f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED188                                       0x5b40
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED189                                       0x5b41
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED190                                       0x5b42
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED191                                       0x5b43
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED192                                       0x5b44
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED193                                       0x5b45
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED194                                       0x5b46
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED195                                       0x5b47
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED196                                       0x5b48
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED197                                       0x5b49
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED198                                       0x5b4a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED199                                       0x5b4b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED200                                       0x5b4c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED201                                       0x5b4d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED202                                       0x5b4e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED203                                       0x5b4f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED204                                       0x5b50
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED205                                       0x5b51
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED206                                       0x5b52
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED207                                       0x5b53
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED208                                       0x5b54
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED209                                       0x5b55
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED210                                       0x5b56
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED211                                       0x5b57
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED212                                       0x5b58
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED213                                       0x5b59
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED214                                       0x5b5a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED215                                       0x5b5b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED216                                       0x5b5c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED217                                       0x5b5d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED218                                       0x5b5e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED219                                       0x5b5f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED220                                       0x5b60
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED221                                       0x5b61
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED222                                       0x5b62
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED223                                       0x5b63
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED224                                       0x5b64
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED225                                       0x5b65
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED226                                       0x5b66
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED227                                       0x5b67
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED228                                       0x5b68
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED229                                       0x5b69
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED230                                       0x5b6a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED231                                       0x5b6b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED232                                       0x5b6c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED233                                       0x5b6d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED234                                       0x5b6e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED235                                       0x5b6f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED236                                       0x5b70
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED237                                       0x5b71
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED238                                       0x5b72
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED239                                       0x5b73
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED240                                       0x5b74
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED241                                       0x5b75
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED242                                       0x5b76
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED243                                       0x5b77
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED244                                       0x5b78
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED245                                       0x5b79
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED246                                       0x5b7a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED247                                       0x5b7b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED248                                       0x5b7c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED249                                       0x5b7d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED250                                       0x5b7e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED251                                       0x5b7f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED252                                       0x5b80
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED253                                       0x5b81
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED254                                       0x5b82
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED255                                       0x5b83
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED256                                       0x5b84
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED257                                       0x5b85
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED258                                       0x5b86
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED259                                       0x5b87
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED260                                       0x5b88
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED261                                       0x5b89
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED262                                       0x5b8a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED263                                       0x5b8b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED264                                       0x5b8c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED265                                       0x5b8d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED266                                       0x5b8e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED267                                       0x5b8f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED268                                       0x5b90
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED269                                       0x5b91
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED270                                       0x5b92
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED271                                       0x5b93
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED272                                       0x5b94
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED273                                       0x5b95
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED274                                       0x5b96
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED275                                       0x5b97
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED276                                       0x5b98
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED277                                       0x5b99
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED278                                       0x5b9a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED279                                       0x5b9b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED280                                       0x5b9c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED281                                       0x5b9d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED282                                       0x5b9e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED283                                       0x5b9f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED284                                       0x5ba0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED285                                       0x5ba1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED286                                       0x5ba2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED287                                       0x5ba3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED288                                       0x5ba4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED289                                       0x5ba5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED290                                       0x5ba6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED291                                       0x5ba7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED292                                       0x5ba8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED293                                       0x5ba9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED294                                       0x5baa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED295                                       0x5bab
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED296                                       0x5bac
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED297                                       0x5bad
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED298                                       0x5bae
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED299                                       0x5baf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED300                                       0x5bb0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED301                                       0x5bb1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED302                                       0x5bb2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED303                                       0x5bb3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED304                                       0x5bb4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED305                                       0x5bb5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED306                                       0x5bb6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED307                                       0x5bb7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED308                                       0x5bb8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED309                                       0x5bb9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED310                                       0x5bba
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED311                                       0x5bbb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED312                                       0x5bbc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED313                                       0x5bbd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED314                                       0x5bbe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED315                                       0x5bbf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED316                                       0x5bc0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED317                                       0x5bc1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED318                                       0x5bc2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED319                                       0x5bc3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED320                                       0x5bc4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED321                                       0x5bc5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED322                                       0x5bc6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED323                                       0x5bc7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED324                                       0x5bc8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED325                                       0x5bc9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED326                                       0x5bca
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED327                                       0x5bcb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED328                                       0x5bcc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED329                                       0x5bcd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED330                                       0x5bce
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED331                                       0x5bcf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED332                                       0x5bd0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED333                                       0x5bd1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED334                                       0x5bd2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED335                                       0x5bd3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED336                                       0x5bd4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED337                                       0x5bd5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED338                                       0x5bd6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED339                                       0x5bd7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED340                                       0x5bd8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED341                                       0x5bd9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED342                                       0x5bda
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED343                                       0x5bdb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED344                                       0x5bdc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED345                                       0x5bdd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED346                                       0x5bde
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED347                                       0x5bdf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED348                                       0x5be0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED349                                       0x5be1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED350                                       0x5be2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED351                                       0x5be3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED352                                       0x5be4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED353                                       0x5be5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED354                                       0x5be6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED355                                       0x5be7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED356                                       0x5be8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED357                                       0x5be9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED358                                       0x5bea
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED359                                       0x5beb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED360                                       0x5bec
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED361                                       0x5bed
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED362                                       0x5bee
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED363                                       0x5bef
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED364                                       0x5bf0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED365                                       0x5bf1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED366                                       0x5bf2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED367                                       0x5bf3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED368                                       0x5bf4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED369                                       0x5bf5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED370                                       0x5bf6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED371                                       0x5bf7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED372                                       0x5bf8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED373                                       0x5bf9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED374                                       0x5bfa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED375                                       0x5bfb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED376                                       0x5bfc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED377                                       0x5bfd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED378                                       0x5bfe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED379                                       0x5bff
++#define mmDPHY_MACRO_CNTL_RESERVED0                                             0x5d98
++#define mmDPHY_MACRO_CNTL_RESERVED1                                             0x5d99
++#define mmDPHY_MACRO_CNTL_RESERVED2                                             0x5d9a
++#define mmDPHY_MACRO_CNTL_RESERVED3                                             0x5d9b
++#define mmDPHY_MACRO_CNTL_RESERVED4                                             0x5d9c
++#define mmDPHY_MACRO_CNTL_RESERVED5                                             0x5d9d
++#define mmDPHY_MACRO_CNTL_RESERVED6                                             0x5d9e
++#define mmDPHY_MACRO_CNTL_RESERVED7                                             0x5d9f
++#define mmDPHY_MACRO_CNTL_RESERVED8                                             0x5da0
++#define mmDPHY_MACRO_CNTL_RESERVED9                                             0x5da1
++#define mmDPHY_MACRO_CNTL_RESERVED10                                            0x5da2
++#define mmDPHY_MACRO_CNTL_RESERVED11                                            0x5da3
++#define mmDPHY_MACRO_CNTL_RESERVED12                                            0x5da4
++#define mmDPHY_MACRO_CNTL_RESERVED13                                            0x5da5
++#define mmDPHY_MACRO_CNTL_RESERVED14                                            0x5da6
++#define mmDPHY_MACRO_CNTL_RESERVED15                                            0x5da7
++#define mmDPHY_MACRO_CNTL_RESERVED16                                            0x5da8
++#define mmDPHY_MACRO_CNTL_RESERVED17                                            0x5da9
++#define mmDPHY_MACRO_CNTL_RESERVED18                                            0x5daa
++#define mmDPHY_MACRO_CNTL_RESERVED19                                            0x5dab
++#define mmDPHY_MACRO_CNTL_RESERVED20                                            0x5dac
++#define mmDPHY_MACRO_CNTL_RESERVED21                                            0x5dad
++#define mmDPHY_MACRO_CNTL_RESERVED22                                            0x5dae
++#define mmDPHY_MACRO_CNTL_RESERVED23                                            0x5daf
++#define mmDPHY_MACRO_CNTL_RESERVED24                                            0x5db0
++#define mmDPHY_MACRO_CNTL_RESERVED25                                            0x5db1
++#define mmDPHY_MACRO_CNTL_RESERVED26                                            0x5db2
++#define mmDPHY_MACRO_CNTL_RESERVED27                                            0x5db3
++#define mmDPHY_MACRO_CNTL_RESERVED28                                            0x5db4
++#define mmDPHY_MACRO_CNTL_RESERVED29                                            0x5db5
++#define mmDPHY_MACRO_CNTL_RESERVED30                                            0x5db6
++#define mmDPHY_MACRO_CNTL_RESERVED31                                            0x5db7
++#define mmDPHY_MACRO_CNTL_RESERVED32                                            0x5db8
++#define mmDPHY_MACRO_CNTL_RESERVED33                                            0x5db9
++#define mmDPHY_MACRO_CNTL_RESERVED34                                            0x5dba
++#define mmDPHY_MACRO_CNTL_RESERVED35                                            0x5dbb
++#define mmDPHY_MACRO_CNTL_RESERVED36                                            0x5dbc
++#define mmDPHY_MACRO_CNTL_RESERVED37                                            0x5dbd
++#define mmDPHY_MACRO_CNTL_RESERVED38                                            0x5dbe
++#define mmDPHY_MACRO_CNTL_RESERVED39                                            0x5dbf
++#define mmDPHY_MACRO_CNTL_RESERVED40                                            0x5dc0
++#define mmDPHY_MACRO_CNTL_RESERVED41                                            0x5dc1
++#define mmDPHY_MACRO_CNTL_RESERVED42                                            0x5dc2
++#define mmDPHY_MACRO_CNTL_RESERVED43                                            0x5dc3
++#define mmDPHY_MACRO_CNTL_RESERVED44                                            0x5dc4
++#define mmDPHY_MACRO_CNTL_RESERVED45                                            0x5dc5
++#define mmDPHY_MACRO_CNTL_RESERVED46                                            0x5dc6
++#define mmDPHY_MACRO_CNTL_RESERVED47                                            0x5dc7
++#define mmDPHY_MACRO_CNTL_RESERVED48                                            0x5dc8
++#define mmDPHY_MACRO_CNTL_RESERVED49                                            0x5dc9
++#define mmDPHY_MACRO_CNTL_RESERVED50                                            0x5dca
++#define mmDPHY_MACRO_CNTL_RESERVED51                                            0x5dcb
++#define mmDPHY_MACRO_CNTL_RESERVED52                                            0x5dcc
++#define mmDPHY_MACRO_CNTL_RESERVED53                                            0x5dcd
++#define mmDPHY_MACRO_CNTL_RESERVED54                                            0x5dce
++#define mmDPHY_MACRO_CNTL_RESERVED55                                            0x5dcf
++#define mmDPHY_MACRO_CNTL_RESERVED56                                            0x5dd0
++#define mmDPHY_MACRO_CNTL_RESERVED57                                            0x5dd1
++#define mmDPHY_MACRO_CNTL_RESERVED58                                            0x5dd2
++#define mmDPHY_MACRO_CNTL_RESERVED59                                            0x5dd3
++#define mmDPHY_MACRO_CNTL_RESERVED60                                            0x5dd4
++#define mmDPHY_MACRO_CNTL_RESERVED61                                            0x5dd5
++#define mmDPHY_MACRO_CNTL_RESERVED62                                            0x5dd6
++#define mmDPHY_MACRO_CNTL_RESERVED63                                            0x5dd7
++#define mmGRPH_ENABLE                                                           0x1a00
++#define mmDCP0_GRPH_ENABLE                                                      0x1a00
++#define mmDCP1_GRPH_ENABLE                                                      0x1c00
++#define mmDCP2_GRPH_ENABLE                                                      0x1e00
++#define mmDCP3_GRPH_ENABLE                                                      0x4000
++#define mmDCP4_GRPH_ENABLE                                                      0x4200
++#define mmDCP5_GRPH_ENABLE                                                      0x4400
++#define mmGRPH_CONTROL                                                          0x1a01
++#define mmDCP0_GRPH_CONTROL                                                     0x1a01
++#define mmDCP1_GRPH_CONTROL                                                     0x1c01
++#define mmDCP2_GRPH_CONTROL                                                     0x1e01
++#define mmDCP3_GRPH_CONTROL                                                     0x4001
++#define mmDCP4_GRPH_CONTROL                                                     0x4201
++#define mmDCP5_GRPH_CONTROL                                                     0x4401
++#define mmGRPH_LUT_10BIT_BYPASS                                                 0x1a02
++#define mmDCP0_GRPH_LUT_10BIT_BYPASS                                            0x1a02
++#define mmDCP1_GRPH_LUT_10BIT_BYPASS                                            0x1c02
++#define mmDCP2_GRPH_LUT_10BIT_BYPASS                                            0x1e02
++#define mmDCP3_GRPH_LUT_10BIT_BYPASS                                            0x4002
++#define mmDCP4_GRPH_LUT_10BIT_BYPASS                                            0x4202
++#define mmDCP5_GRPH_LUT_10BIT_BYPASS                                            0x4402
++#define mmGRPH_SWAP_CNTL                                                        0x1a03
++#define mmDCP0_GRPH_SWAP_CNTL                                                   0x1a03
++#define mmDCP1_GRPH_SWAP_CNTL                                                   0x1c03
++#define mmDCP2_GRPH_SWAP_CNTL                                                   0x1e03
++#define mmDCP3_GRPH_SWAP_CNTL                                                   0x4003
++#define mmDCP4_GRPH_SWAP_CNTL                                                   0x4203
++#define mmDCP5_GRPH_SWAP_CNTL                                                   0x4403
++#define mmGRPH_PRIMARY_SURFACE_ADDRESS                                          0x1a04
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1a04
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1c04
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1e04
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4004
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4204
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4404
++#define mmGRPH_SECONDARY_SURFACE_ADDRESS                                        0x1a05
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1a05
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1c05
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1e05
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4005
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4205
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4405
++#define mmGRPH_PITCH                                                            0x1a06
++#define mmDCP0_GRPH_PITCH                                                       0x1a06
++#define mmDCP1_GRPH_PITCH                                                       0x1c06
++#define mmDCP2_GRPH_PITCH                                                       0x1e06
++#define mmDCP3_GRPH_PITCH                                                       0x4006
++#define mmDCP4_GRPH_PITCH                                                       0x4206
++#define mmDCP5_GRPH_PITCH                                                       0x4406
++#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                     0x1a07
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1a07
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1c07
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1e07
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4007
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4207
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4407
++#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                   0x1a08
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1a08
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1c08
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1e08
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4008
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4208
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4408
++#define mmGRPH_SURFACE_OFFSET_X                                                 0x1a09
++#define mmDCP0_GRPH_SURFACE_OFFSET_X                                            0x1a09
++#define mmDCP1_GRPH_SURFACE_OFFSET_X                                            0x1c09
++#define mmDCP2_GRPH_SURFACE_OFFSET_X                                            0x1e09
++#define mmDCP3_GRPH_SURFACE_OFFSET_X                                            0x4009
++#define mmDCP4_GRPH_SURFACE_OFFSET_X                                            0x4209
++#define mmDCP5_GRPH_SURFACE_OFFSET_X                                            0x4409
++#define mmGRPH_SURFACE_OFFSET_Y                                                 0x1a0a
++#define mmDCP0_GRPH_SURFACE_OFFSET_Y                                            0x1a0a
++#define mmDCP1_GRPH_SURFACE_OFFSET_Y                                            0x1c0a
++#define mmDCP2_GRPH_SURFACE_OFFSET_Y                                            0x1e0a
++#define mmDCP3_GRPH_SURFACE_OFFSET_Y                                            0x400a
++#define mmDCP4_GRPH_SURFACE_OFFSET_Y                                            0x420a
++#define mmDCP5_GRPH_SURFACE_OFFSET_Y                                            0x440a
++#define mmGRPH_X_START                                                          0x1a0b
++#define mmDCP0_GRPH_X_START                                                     0x1a0b
++#define mmDCP1_GRPH_X_START                                                     0x1c0b
++#define mmDCP2_GRPH_X_START                                                     0x1e0b
++#define mmDCP3_GRPH_X_START                                                     0x400b
++#define mmDCP4_GRPH_X_START                                                     0x420b
++#define mmDCP5_GRPH_X_START                                                     0x440b
++#define mmGRPH_Y_START                                                          0x1a0c
++#define mmDCP0_GRPH_Y_START                                                     0x1a0c
++#define mmDCP1_GRPH_Y_START                                                     0x1c0c
++#define mmDCP2_GRPH_Y_START                                                     0x1e0c
++#define mmDCP3_GRPH_Y_START                                                     0x400c
++#define mmDCP4_GRPH_Y_START                                                     0x420c
++#define mmDCP5_GRPH_Y_START                                                     0x440c
++#define mmGRPH_X_END                                                            0x1a0d
++#define mmDCP0_GRPH_X_END                                                       0x1a0d
++#define mmDCP1_GRPH_X_END                                                       0x1c0d
++#define mmDCP2_GRPH_X_END                                                       0x1e0d
++#define mmDCP3_GRPH_X_END                                                       0x400d
++#define mmDCP4_GRPH_X_END                                                       0x420d
++#define mmDCP5_GRPH_X_END                                                       0x440d
++#define mmGRPH_Y_END                                                            0x1a0e
++#define mmDCP0_GRPH_Y_END                                                       0x1a0e
++#define mmDCP1_GRPH_Y_END                                                       0x1c0e
++#define mmDCP2_GRPH_Y_END                                                       0x1e0e
++#define mmDCP3_GRPH_Y_END                                                       0x400e
++#define mmDCP4_GRPH_Y_END                                                       0x420e
++#define mmDCP5_GRPH_Y_END                                                       0x440e
++#define mmINPUT_GAMMA_CONTROL                                                   0x1a10
++#define mmDCP0_INPUT_GAMMA_CONTROL                                              0x1a10
++#define mmDCP1_INPUT_GAMMA_CONTROL                                              0x1c10
++#define mmDCP2_INPUT_GAMMA_CONTROL                                              0x1e10
++#define mmDCP3_INPUT_GAMMA_CONTROL                                              0x4010
++#define mmDCP4_INPUT_GAMMA_CONTROL                                              0x4210
++#define mmDCP5_INPUT_GAMMA_CONTROL                                              0x4410
++#define mmGRPH_UPDATE                                                           0x1a11
++#define mmDCP0_GRPH_UPDATE                                                      0x1a11
++#define mmDCP1_GRPH_UPDATE                                                      0x1c11
++#define mmDCP2_GRPH_UPDATE                                                      0x1e11
++#define mmDCP3_GRPH_UPDATE                                                      0x4011
++#define mmDCP4_GRPH_UPDATE                                                      0x4211
++#define mmDCP5_GRPH_UPDATE                                                      0x4411
++#define mmGRPH_FLIP_CONTROL                                                     0x1a12
++#define mmDCP0_GRPH_FLIP_CONTROL                                                0x1a12
++#define mmDCP1_GRPH_FLIP_CONTROL                                                0x1c12
++#define mmDCP2_GRPH_FLIP_CONTROL                                                0x1e12
++#define mmDCP3_GRPH_FLIP_CONTROL                                                0x4012
++#define mmDCP4_GRPH_FLIP_CONTROL                                                0x4212
++#define mmDCP5_GRPH_FLIP_CONTROL                                                0x4412
++#define mmGRPH_SURFACE_ADDRESS_INUSE                                            0x1a13
++#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                       0x1a13
++#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                       0x1c13
++#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                       0x1e13
++#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                       0x4013
++#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                       0x4213
++#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                       0x4413
++#define mmGRPH_DFQ_CONTROL                                                      0x1a14
++#define mmDCP0_GRPH_DFQ_CONTROL                                                 0x1a14
++#define mmDCP1_GRPH_DFQ_CONTROL                                                 0x1c14
++#define mmDCP2_GRPH_DFQ_CONTROL                                                 0x1e14
++#define mmDCP3_GRPH_DFQ_CONTROL                                                 0x4014
++#define mmDCP4_GRPH_DFQ_CONTROL                                                 0x4214
++#define mmDCP5_GRPH_DFQ_CONTROL                                                 0x4414
++#define mmGRPH_DFQ_STATUS                                                       0x1a15
++#define mmDCP0_GRPH_DFQ_STATUS                                                  0x1a15
++#define mmDCP1_GRPH_DFQ_STATUS                                                  0x1c15
++#define mmDCP2_GRPH_DFQ_STATUS                                                  0x1e15
++#define mmDCP3_GRPH_DFQ_STATUS                                                  0x4015
++#define mmDCP4_GRPH_DFQ_STATUS                                                  0x4215
++#define mmDCP5_GRPH_DFQ_STATUS                                                  0x4415
++#define mmGRPH_INTERRUPT_STATUS                                                 0x1a16
++#define mmDCP0_GRPH_INTERRUPT_STATUS                                            0x1a16
++#define mmDCP1_GRPH_INTERRUPT_STATUS                                            0x1c16
++#define mmDCP2_GRPH_INTERRUPT_STATUS                                            0x1e16
++#define mmDCP3_GRPH_INTERRUPT_STATUS                                            0x4016
++#define mmDCP4_GRPH_INTERRUPT_STATUS                                            0x4216
++#define mmDCP5_GRPH_INTERRUPT_STATUS                                            0x4416
++#define mmGRPH_INTERRUPT_CONTROL                                                0x1a17
++#define mmDCP0_GRPH_INTERRUPT_CONTROL                                           0x1a17
++#define mmDCP1_GRPH_INTERRUPT_CONTROL                                           0x1c17
++#define mmDCP2_GRPH_INTERRUPT_CONTROL                                           0x1e17
++#define mmDCP3_GRPH_INTERRUPT_CONTROL                                           0x4017
++#define mmDCP4_GRPH_INTERRUPT_CONTROL                                           0x4217
++#define mmDCP5_GRPH_INTERRUPT_CONTROL                                           0x4417
++#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE                                       0x1a18
++#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1a18
++#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1c18
++#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1e18
++#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4018
++#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4218
++#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4418
++#define mmGRPH_COMPRESS_SURFACE_ADDRESS                                         0x1a19
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1a19
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1c19
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1e19
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4019
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4219
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4419
++#define mmGRPH_COMPRESS_PITCH                                                   0x1a1a
++#define mmDCP0_GRPH_COMPRESS_PITCH                                              0x1a1a
++#define mmDCP1_GRPH_COMPRESS_PITCH                                              0x1c1a
++#define mmDCP2_GRPH_COMPRESS_PITCH                                              0x1e1a
++#define mmDCP3_GRPH_COMPRESS_PITCH                                              0x401a
++#define mmDCP4_GRPH_COMPRESS_PITCH                                              0x421a
++#define mmDCP5_GRPH_COMPRESS_PITCH                                              0x441a
++#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                    0x1a1b
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1a1b
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1c1b
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1e1b
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x401b
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x421b
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x441b
++#define mmOVL_ENABLE                                                            0x1a1c
++#define mmDCP0_OVL_ENABLE                                                       0x1a1c
++#define mmDCP1_OVL_ENABLE                                                       0x1c1c
++#define mmDCP2_OVL_ENABLE                                                       0x1e1c
++#define mmDCP3_OVL_ENABLE                                                       0x401c
++#define mmDCP4_OVL_ENABLE                                                       0x421c
++#define mmDCP5_OVL_ENABLE                                                       0x441c
++#define mmOVL_CONTROL1                                                          0x1a1d
++#define mmDCP0_OVL_CONTROL1                                                     0x1a1d
++#define mmDCP1_OVL_CONTROL1                                                     0x1c1d
++#define mmDCP2_OVL_CONTROL1                                                     0x1e1d
++#define mmDCP3_OVL_CONTROL1                                                     0x401d
++#define mmDCP4_OVL_CONTROL1                                                     0x421d
++#define mmDCP5_OVL_CONTROL1                                                     0x441d
++#define mmOVL_CONTROL2                                                          0x1a1e
++#define mmDCP0_OVL_CONTROL2                                                     0x1a1e
++#define mmDCP1_OVL_CONTROL2                                                     0x1c1e
++#define mmDCP2_OVL_CONTROL2                                                     0x1e1e
++#define mmDCP3_OVL_CONTROL2                                                     0x401e
++#define mmDCP4_OVL_CONTROL2                                                     0x421e
++#define mmDCP5_OVL_CONTROL2                                                     0x441e
++#define mmOVL_SWAP_CNTL                                                         0x1a1f
++#define mmDCP0_OVL_SWAP_CNTL                                                    0x1a1f
++#define mmDCP1_OVL_SWAP_CNTL                                                    0x1c1f
++#define mmDCP2_OVL_SWAP_CNTL                                                    0x1e1f
++#define mmDCP3_OVL_SWAP_CNTL                                                    0x401f
++#define mmDCP4_OVL_SWAP_CNTL                                                    0x421f
++#define mmDCP5_OVL_SWAP_CNTL                                                    0x441f
++#define mmOVL_SURFACE_ADDRESS                                                   0x1a20
++#define mmDCP0_OVL_SURFACE_ADDRESS                                              0x1a20
++#define mmDCP1_OVL_SURFACE_ADDRESS                                              0x1c20
++#define mmDCP2_OVL_SURFACE_ADDRESS                                              0x1e20
++#define mmDCP3_OVL_SURFACE_ADDRESS                                              0x4020
++#define mmDCP4_OVL_SURFACE_ADDRESS                                              0x4220
++#define mmDCP5_OVL_SURFACE_ADDRESS                                              0x4420
++#define mmOVL_PITCH                                                             0x1a21
++#define mmDCP0_OVL_PITCH                                                        0x1a21
++#define mmDCP1_OVL_PITCH                                                        0x1c21
++#define mmDCP2_OVL_PITCH                                                        0x1e21
++#define mmDCP3_OVL_PITCH                                                        0x4021
++#define mmDCP4_OVL_PITCH                                                        0x4221
++#define mmDCP5_OVL_PITCH                                                        0x4421
++#define mmOVL_SURFACE_ADDRESS_HIGH                                              0x1a22
++#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH                                         0x1a22
++#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH                                         0x1c22
++#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH                                         0x1e22
++#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH                                         0x4022
++#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH                                         0x4222
++#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH                                         0x4422
++#define mmOVL_SURFACE_OFFSET_X                                                  0x1a23
++#define mmDCP0_OVL_SURFACE_OFFSET_X                                             0x1a23
++#define mmDCP1_OVL_SURFACE_OFFSET_X                                             0x1c23
++#define mmDCP2_OVL_SURFACE_OFFSET_X                                             0x1e23
++#define mmDCP3_OVL_SURFACE_OFFSET_X                                             0x4023
++#define mmDCP4_OVL_SURFACE_OFFSET_X                                             0x4223
++#define mmDCP5_OVL_SURFACE_OFFSET_X                                             0x4423
++#define mmOVL_SURFACE_OFFSET_Y                                                  0x1a24
++#define mmDCP0_OVL_SURFACE_OFFSET_Y                                             0x1a24
++#define mmDCP1_OVL_SURFACE_OFFSET_Y                                             0x1c24
++#define mmDCP2_OVL_SURFACE_OFFSET_Y                                             0x1e24
++#define mmDCP3_OVL_SURFACE_OFFSET_Y                                             0x4024
++#define mmDCP4_OVL_SURFACE_OFFSET_Y                                             0x4224
++#define mmDCP5_OVL_SURFACE_OFFSET_Y                                             0x4424
++#define mmOVL_START                                                             0x1a25
++#define mmDCP0_OVL_START                                                        0x1a25
++#define mmDCP1_OVL_START                                                        0x1c25
++#define mmDCP2_OVL_START                                                        0x1e25
++#define mmDCP3_OVL_START                                                        0x4025
++#define mmDCP4_OVL_START                                                        0x4225
++#define mmDCP5_OVL_START                                                        0x4425
++#define mmOVL_END                                                               0x1a26
++#define mmDCP0_OVL_END                                                          0x1a26
++#define mmDCP1_OVL_END                                                          0x1c26
++#define mmDCP2_OVL_END                                                          0x1e26
++#define mmDCP3_OVL_END                                                          0x4026
++#define mmDCP4_OVL_END                                                          0x4226
++#define mmDCP5_OVL_END                                                          0x4426
++#define mmOVL_UPDATE                                                            0x1a27
++#define mmDCP0_OVL_UPDATE                                                       0x1a27
++#define mmDCP1_OVL_UPDATE                                                       0x1c27
++#define mmDCP2_OVL_UPDATE                                                       0x1e27
++#define mmDCP3_OVL_UPDATE                                                       0x4027
++#define mmDCP4_OVL_UPDATE                                                       0x4227
++#define mmDCP5_OVL_UPDATE                                                       0x4427
++#define mmOVL_SURFACE_ADDRESS_INUSE                                             0x1a28
++#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE                                        0x1a28
++#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE                                        0x1c28
++#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE                                        0x1e28
++#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE                                        0x4028
++#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE                                        0x4228
++#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE                                        0x4428
++#define mmOVL_DFQ_CONTROL                                                       0x1a29
++#define mmDCP0_OVL_DFQ_CONTROL                                                  0x1a29
++#define mmDCP1_OVL_DFQ_CONTROL                                                  0x1c29
++#define mmDCP2_OVL_DFQ_CONTROL                                                  0x1e29
++#define mmDCP3_OVL_DFQ_CONTROL                                                  0x4029
++#define mmDCP4_OVL_DFQ_CONTROL                                                  0x4229
++#define mmDCP5_OVL_DFQ_CONTROL                                                  0x4429
++#define mmOVL_DFQ_STATUS                                                        0x1a2a
++#define mmDCP0_OVL_DFQ_STATUS                                                   0x1a2a
++#define mmDCP1_OVL_DFQ_STATUS                                                   0x1c2a
++#define mmDCP2_OVL_DFQ_STATUS                                                   0x1e2a
++#define mmDCP3_OVL_DFQ_STATUS                                                   0x402a
++#define mmDCP4_OVL_DFQ_STATUS                                                   0x422a
++#define mmDCP5_OVL_DFQ_STATUS                                                   0x442a
++#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE                                        0x1a2b
++#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1a2b
++#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1c2b
++#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x1e2b
++#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x402b
++#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x422b
++#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE                                   0x442b
++#define mmOVLSCL_EDGE_PIXEL_CNTL                                                0x1a2c
++#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL                                           0x1a2c
++#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL                                           0x1c2c
++#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL                                           0x1e2c
++#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL                                           0x402c
++#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL                                           0x422c
++#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL                                           0x442c
++#define mmPRESCALE_GRPH_CONTROL                                                 0x1a2d
++#define mmDCP0_PRESCALE_GRPH_CONTROL                                            0x1a2d
++#define mmDCP1_PRESCALE_GRPH_CONTROL                                            0x1c2d
++#define mmDCP2_PRESCALE_GRPH_CONTROL                                            0x1e2d
++#define mmDCP3_PRESCALE_GRPH_CONTROL                                            0x402d
++#define mmDCP4_PRESCALE_GRPH_CONTROL                                            0x422d
++#define mmDCP5_PRESCALE_GRPH_CONTROL                                            0x442d
++#define mmPRESCALE_VALUES_GRPH_R                                                0x1a2e
++#define mmDCP0_PRESCALE_VALUES_GRPH_R                                           0x1a2e
++#define mmDCP1_PRESCALE_VALUES_GRPH_R                                           0x1c2e
++#define mmDCP2_PRESCALE_VALUES_GRPH_R                                           0x1e2e
++#define mmDCP3_PRESCALE_VALUES_GRPH_R                                           0x402e
++#define mmDCP4_PRESCALE_VALUES_GRPH_R                                           0x422e
++#define mmDCP5_PRESCALE_VALUES_GRPH_R                                           0x442e
++#define mmPRESCALE_VALUES_GRPH_G                                                0x1a2f
++#define mmDCP0_PRESCALE_VALUES_GRPH_G                                           0x1a2f
++#define mmDCP1_PRESCALE_VALUES_GRPH_G                                           0x1c2f
++#define mmDCP2_PRESCALE_VALUES_GRPH_G                                           0x1e2f
++#define mmDCP3_PRESCALE_VALUES_GRPH_G                                           0x402f
++#define mmDCP4_PRESCALE_VALUES_GRPH_G                                           0x422f
++#define mmDCP5_PRESCALE_VALUES_GRPH_G                                           0x442f
++#define mmPRESCALE_VALUES_GRPH_B                                                0x1a30
++#define mmDCP0_PRESCALE_VALUES_GRPH_B                                           0x1a30
++#define mmDCP1_PRESCALE_VALUES_GRPH_B                                           0x1c30
++#define mmDCP2_PRESCALE_VALUES_GRPH_B                                           0x1e30
++#define mmDCP3_PRESCALE_VALUES_GRPH_B                                           0x4030
++#define mmDCP4_PRESCALE_VALUES_GRPH_B                                           0x4230
++#define mmDCP5_PRESCALE_VALUES_GRPH_B                                           0x4430
++#define mmPRESCALE_OVL_CONTROL                                                  0x1a31
++#define mmDCP0_PRESCALE_OVL_CONTROL                                             0x1a31
++#define mmDCP1_PRESCALE_OVL_CONTROL                                             0x1c31
++#define mmDCP2_PRESCALE_OVL_CONTROL                                             0x1e31
++#define mmDCP3_PRESCALE_OVL_CONTROL                                             0x4031
++#define mmDCP4_PRESCALE_OVL_CONTROL                                             0x4231
++#define mmDCP5_PRESCALE_OVL_CONTROL                                             0x4431
++#define mmPRESCALE_VALUES_OVL_CB                                                0x1a32
++#define mmDCP0_PRESCALE_VALUES_OVL_CB                                           0x1a32
++#define mmDCP1_PRESCALE_VALUES_OVL_CB                                           0x1c32
++#define mmDCP2_PRESCALE_VALUES_OVL_CB                                           0x1e32
++#define mmDCP3_PRESCALE_VALUES_OVL_CB                                           0x4032
++#define mmDCP4_PRESCALE_VALUES_OVL_CB                                           0x4232
++#define mmDCP5_PRESCALE_VALUES_OVL_CB                                           0x4432
++#define mmPRESCALE_VALUES_OVL_Y                                                 0x1a33
++#define mmDCP0_PRESCALE_VALUES_OVL_Y                                            0x1a33
++#define mmDCP1_PRESCALE_VALUES_OVL_Y                                            0x1c33
++#define mmDCP2_PRESCALE_VALUES_OVL_Y                                            0x1e33
++#define mmDCP3_PRESCALE_VALUES_OVL_Y                                            0x4033
++#define mmDCP4_PRESCALE_VALUES_OVL_Y                                            0x4233
++#define mmDCP5_PRESCALE_VALUES_OVL_Y                                            0x4433
++#define mmPRESCALE_VALUES_OVL_CR                                                0x1a34
++#define mmDCP0_PRESCALE_VALUES_OVL_CR                                           0x1a34
++#define mmDCP1_PRESCALE_VALUES_OVL_CR                                           0x1c34
++#define mmDCP2_PRESCALE_VALUES_OVL_CR                                           0x1e34
++#define mmDCP3_PRESCALE_VALUES_OVL_CR                                           0x4034
++#define mmDCP4_PRESCALE_VALUES_OVL_CR                                           0x4234
++#define mmDCP5_PRESCALE_VALUES_OVL_CR                                           0x4434
++#define mmINPUT_CSC_CONTROL                                                     0x1a35
++#define mmDCP0_INPUT_CSC_CONTROL                                                0x1a35
++#define mmDCP1_INPUT_CSC_CONTROL                                                0x1c35
++#define mmDCP2_INPUT_CSC_CONTROL                                                0x1e35
++#define mmDCP3_INPUT_CSC_CONTROL                                                0x4035
++#define mmDCP4_INPUT_CSC_CONTROL                                                0x4235
++#define mmDCP5_INPUT_CSC_CONTROL                                                0x4435
++#define mmINPUT_CSC_C11_C12                                                     0x1a36
++#define mmDCP0_INPUT_CSC_C11_C12                                                0x1a36
++#define mmDCP1_INPUT_CSC_C11_C12                                                0x1c36
++#define mmDCP2_INPUT_CSC_C11_C12                                                0x1e36
++#define mmDCP3_INPUT_CSC_C11_C12                                                0x4036
++#define mmDCP4_INPUT_CSC_C11_C12                                                0x4236
++#define mmDCP5_INPUT_CSC_C11_C12                                                0x4436
++#define mmINPUT_CSC_C13_C14                                                     0x1a37
++#define mmDCP0_INPUT_CSC_C13_C14                                                0x1a37
++#define mmDCP1_INPUT_CSC_C13_C14                                                0x1c37
++#define mmDCP2_INPUT_CSC_C13_C14                                                0x1e37
++#define mmDCP3_INPUT_CSC_C13_C14                                                0x4037
++#define mmDCP4_INPUT_CSC_C13_C14                                                0x4237
++#define mmDCP5_INPUT_CSC_C13_C14                                                0x4437
++#define mmINPUT_CSC_C21_C22                                                     0x1a38
++#define mmDCP0_INPUT_CSC_C21_C22                                                0x1a38
++#define mmDCP1_INPUT_CSC_C21_C22                                                0x1c38
++#define mmDCP2_INPUT_CSC_C21_C22                                                0x1e38
++#define mmDCP3_INPUT_CSC_C21_C22                                                0x4038
++#define mmDCP4_INPUT_CSC_C21_C22                                                0x4238
++#define mmDCP5_INPUT_CSC_C21_C22                                                0x4438
++#define mmINPUT_CSC_C23_C24                                                     0x1a39
++#define mmDCP0_INPUT_CSC_C23_C24                                                0x1a39
++#define mmDCP1_INPUT_CSC_C23_C24                                                0x1c39
++#define mmDCP2_INPUT_CSC_C23_C24                                                0x1e39
++#define mmDCP3_INPUT_CSC_C23_C24                                                0x4039
++#define mmDCP4_INPUT_CSC_C23_C24                                                0x4239
++#define mmDCP5_INPUT_CSC_C23_C24                                                0x4439
++#define mmINPUT_CSC_C31_C32                                                     0x1a3a
++#define mmDCP0_INPUT_CSC_C31_C32                                                0x1a3a
++#define mmDCP1_INPUT_CSC_C31_C32                                                0x1c3a
++#define mmDCP2_INPUT_CSC_C31_C32                                                0x1e3a
++#define mmDCP3_INPUT_CSC_C31_C32                                                0x403a
++#define mmDCP4_INPUT_CSC_C31_C32                                                0x423a
++#define mmDCP5_INPUT_CSC_C31_C32                                                0x443a
++#define mmINPUT_CSC_C33_C34                                                     0x1a3b
++#define mmDCP0_INPUT_CSC_C33_C34                                                0x1a3b
++#define mmDCP1_INPUT_CSC_C33_C34                                                0x1c3b
++#define mmDCP2_INPUT_CSC_C33_C34                                                0x1e3b
++#define mmDCP3_INPUT_CSC_C33_C34                                                0x403b
++#define mmDCP4_INPUT_CSC_C33_C34                                                0x423b
++#define mmDCP5_INPUT_CSC_C33_C34                                                0x443b
++#define mmOUTPUT_CSC_CONTROL                                                    0x1a3c
++#define mmDCP0_OUTPUT_CSC_CONTROL                                               0x1a3c
++#define mmDCP1_OUTPUT_CSC_CONTROL                                               0x1c3c
++#define mmDCP2_OUTPUT_CSC_CONTROL                                               0x1e3c
++#define mmDCP3_OUTPUT_CSC_CONTROL                                               0x403c
++#define mmDCP4_OUTPUT_CSC_CONTROL                                               0x423c
++#define mmDCP5_OUTPUT_CSC_CONTROL                                               0x443c
++#define mmOUTPUT_CSC_C11_C12                                                    0x1a3d
++#define mmDCP0_OUTPUT_CSC_C11_C12                                               0x1a3d
++#define mmDCP1_OUTPUT_CSC_C11_C12                                               0x1c3d
++#define mmDCP2_OUTPUT_CSC_C11_C12                                               0x1e3d
++#define mmDCP3_OUTPUT_CSC_C11_C12                                               0x403d
++#define mmDCP4_OUTPUT_CSC_C11_C12                                               0x423d
++#define mmDCP5_OUTPUT_CSC_C11_C12                                               0x443d
++#define mmOUTPUT_CSC_C13_C14                                                    0x1a3e
++#define mmDCP0_OUTPUT_CSC_C13_C14                                               0x1a3e
++#define mmDCP1_OUTPUT_CSC_C13_C14                                               0x1c3e
++#define mmDCP2_OUTPUT_CSC_C13_C14                                               0x1e3e
++#define mmDCP3_OUTPUT_CSC_C13_C14                                               0x403e
++#define mmDCP4_OUTPUT_CSC_C13_C14                                               0x423e
++#define mmDCP5_OUTPUT_CSC_C13_C14                                               0x443e
++#define mmOUTPUT_CSC_C21_C22                                                    0x1a3f
++#define mmDCP0_OUTPUT_CSC_C21_C22                                               0x1a3f
++#define mmDCP1_OUTPUT_CSC_C21_C22                                               0x1c3f
++#define mmDCP2_OUTPUT_CSC_C21_C22                                               0x1e3f
++#define mmDCP3_OUTPUT_CSC_C21_C22                                               0x403f
++#define mmDCP4_OUTPUT_CSC_C21_C22                                               0x423f
++#define mmDCP5_OUTPUT_CSC_C21_C22                                               0x443f
++#define mmOUTPUT_CSC_C23_C24                                                    0x1a40
++#define mmDCP0_OUTPUT_CSC_C23_C24                                               0x1a40
++#define mmDCP1_OUTPUT_CSC_C23_C24                                               0x1c40
++#define mmDCP2_OUTPUT_CSC_C23_C24                                               0x1e40
++#define mmDCP3_OUTPUT_CSC_C23_C24                                               0x4040
++#define mmDCP4_OUTPUT_CSC_C23_C24                                               0x4240
++#define mmDCP5_OUTPUT_CSC_C23_C24                                               0x4440
++#define mmOUTPUT_CSC_C31_C32                                                    0x1a41
++#define mmDCP0_OUTPUT_CSC_C31_C32                                               0x1a41
++#define mmDCP1_OUTPUT_CSC_C31_C32                                               0x1c41
++#define mmDCP2_OUTPUT_CSC_C31_C32                                               0x1e41
++#define mmDCP3_OUTPUT_CSC_C31_C32                                               0x4041
++#define mmDCP4_OUTPUT_CSC_C31_C32                                               0x4241
++#define mmDCP5_OUTPUT_CSC_C31_C32                                               0x4441
++#define mmOUTPUT_CSC_C33_C34                                                    0x1a42
++#define mmDCP0_OUTPUT_CSC_C33_C34                                               0x1a42
++#define mmDCP1_OUTPUT_CSC_C33_C34                                               0x1c42
++#define mmDCP2_OUTPUT_CSC_C33_C34                                               0x1e42
++#define mmDCP3_OUTPUT_CSC_C33_C34                                               0x4042
++#define mmDCP4_OUTPUT_CSC_C33_C34                                               0x4242
++#define mmDCP5_OUTPUT_CSC_C33_C34                                               0x4442
++#define mmCOMM_MATRIXA_TRANS_C11_C12                                            0x1a43
++#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                       0x1a43
++#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                       0x1c43
++#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                       0x1e43
++#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                       0x4043
++#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                       0x4243
++#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                       0x4443
++#define mmCOMM_MATRIXA_TRANS_C13_C14                                            0x1a44
++#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                       0x1a44
++#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                       0x1c44
++#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                       0x1e44
++#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                       0x4044
++#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                       0x4244
++#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                       0x4444
++#define mmCOMM_MATRIXA_TRANS_C21_C22                                            0x1a45
++#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                       0x1a45
++#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                       0x1c45
++#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                       0x1e45
++#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                       0x4045
++#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                       0x4245
++#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                       0x4445
++#define mmCOMM_MATRIXA_TRANS_C23_C24                                            0x1a46
++#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                       0x1a46
++#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                       0x1c46
++#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                       0x1e46
++#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                       0x4046
++#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                       0x4246
++#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                       0x4446
++#define mmCOMM_MATRIXA_TRANS_C31_C32                                            0x1a47
++#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                       0x1a47
++#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                       0x1c47
++#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                       0x1e47
++#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                       0x4047
++#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                       0x4247
++#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                       0x4447
++#define mmCOMM_MATRIXA_TRANS_C33_C34                                            0x1a48
++#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                       0x1a48
++#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                       0x1c48
++#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                       0x1e48
++#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                       0x4048
++#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                       0x4248
++#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                       0x4448
++#define mmCOMM_MATRIXB_TRANS_C11_C12                                            0x1a49
++#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                       0x1a49
++#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                       0x1c49
++#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                       0x1e49
++#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                       0x4049
++#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                       0x4249
++#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                       0x4449
++#define mmCOMM_MATRIXB_TRANS_C13_C14                                            0x1a4a
++#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                       0x1a4a
++#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                       0x1c4a
++#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                       0x1e4a
++#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                       0x404a
++#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                       0x424a
++#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                       0x444a
++#define mmCOMM_MATRIXB_TRANS_C21_C22                                            0x1a4b
++#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                       0x1a4b
++#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                       0x1c4b
++#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                       0x1e4b
++#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                       0x404b
++#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                       0x424b
++#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                       0x444b
++#define mmCOMM_MATRIXB_TRANS_C23_C24                                            0x1a4c
++#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                       0x1a4c
++#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                       0x1c4c
++#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                       0x1e4c
++#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                       0x404c
++#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                       0x424c
++#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                       0x444c
++#define mmCOMM_MATRIXB_TRANS_C31_C32                                            0x1a4d
++#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                       0x1a4d
++#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                       0x1c4d
++#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                       0x1e4d
++#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                       0x404d
++#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                       0x424d
++#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                       0x444d
++#define mmCOMM_MATRIXB_TRANS_C33_C34                                            0x1a4e
++#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                       0x1a4e
++#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                       0x1c4e
++#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                       0x1e4e
++#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                       0x404e
++#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                       0x424e
++#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                       0x444e
++#define mmDENORM_CONTROL                                                        0x1a50
++#define mmDCP0_DENORM_CONTROL                                                   0x1a50
++#define mmDCP1_DENORM_CONTROL                                                   0x1c50
++#define mmDCP2_DENORM_CONTROL                                                   0x1e50
++#define mmDCP3_DENORM_CONTROL                                                   0x4050
++#define mmDCP4_DENORM_CONTROL                                                   0x4250
++#define mmDCP5_DENORM_CONTROL                                                   0x4450
++#define mmOUT_ROUND_CONTROL                                                     0x1a51
++#define mmDCP0_OUT_ROUND_CONTROL                                                0x1a51
++#define mmDCP1_OUT_ROUND_CONTROL                                                0x1c51
++#define mmDCP2_OUT_ROUND_CONTROL                                                0x1e51
++#define mmDCP3_OUT_ROUND_CONTROL                                                0x4051
++#define mmDCP4_OUT_ROUND_CONTROL                                                0x4251
++#define mmDCP5_OUT_ROUND_CONTROL                                                0x4451
++#define mmOUT_CLAMP_CONTROL_R_CR                                                0x1a52
++#define mmDCP0_OUT_CLAMP_CONTROL_R_CR                                           0x1a52
++#define mmDCP1_OUT_CLAMP_CONTROL_R_CR                                           0x1c52
++#define mmDCP2_OUT_CLAMP_CONTROL_R_CR                                           0x1e52
++#define mmDCP3_OUT_CLAMP_CONTROL_R_CR                                           0x4052
++#define mmDCP4_OUT_CLAMP_CONTROL_R_CR                                           0x4252
++#define mmDCP5_OUT_CLAMP_CONTROL_R_CR                                           0x4452
++#define mmOUT_CLAMP_CONTROL_G_Y                                                 0x1a9c
++#define mmDCP0_OUT_CLAMP_CONTROL_G_Y                                            0x1a9c
++#define mmDCP1_OUT_CLAMP_CONTROL_G_Y                                            0x1c9c
++#define mmDCP2_OUT_CLAMP_CONTROL_G_Y                                            0x1e9c
++#define mmDCP3_OUT_CLAMP_CONTROL_G_Y                                            0x409c
++#define mmDCP4_OUT_CLAMP_CONTROL_G_Y                                            0x429c
++#define mmDCP5_OUT_CLAMP_CONTROL_G_Y                                            0x449c
++#define mmOUT_CLAMP_CONTROL_B_CB                                                0x1a9d
++#define mmDCP0_OUT_CLAMP_CONTROL_B_CB                                           0x1a9d
++#define mmDCP1_OUT_CLAMP_CONTROL_B_CB                                           0x1c9d
++#define mmDCP2_OUT_CLAMP_CONTROL_B_CB                                           0x1e9d
++#define mmDCP3_OUT_CLAMP_CONTROL_B_CB                                           0x409d
++#define mmDCP4_OUT_CLAMP_CONTROL_B_CB                                           0x429d
++#define mmDCP5_OUT_CLAMP_CONTROL_B_CB                                           0x449d
++#define mmKEY_CONTROL                                                           0x1a53
++#define mmDCP0_KEY_CONTROL                                                      0x1a53
++#define mmDCP1_KEY_CONTROL                                                      0x1c53
++#define mmDCP2_KEY_CONTROL                                                      0x1e53
++#define mmDCP3_KEY_CONTROL                                                      0x4053
++#define mmDCP4_KEY_CONTROL                                                      0x4253
++#define mmDCP5_KEY_CONTROL                                                      0x4453
++#define mmKEY_RANGE_ALPHA                                                       0x1a54
++#define mmDCP0_KEY_RANGE_ALPHA                                                  0x1a54
++#define mmDCP1_KEY_RANGE_ALPHA                                                  0x1c54
++#define mmDCP2_KEY_RANGE_ALPHA                                                  0x1e54
++#define mmDCP3_KEY_RANGE_ALPHA                                                  0x4054
++#define mmDCP4_KEY_RANGE_ALPHA                                                  0x4254
++#define mmDCP5_KEY_RANGE_ALPHA                                                  0x4454
++#define mmKEY_RANGE_RED                                                         0x1a55
++#define mmDCP0_KEY_RANGE_RED                                                    0x1a55
++#define mmDCP1_KEY_RANGE_RED                                                    0x1c55
++#define mmDCP2_KEY_RANGE_RED                                                    0x1e55
++#define mmDCP3_KEY_RANGE_RED                                                    0x4055
++#define mmDCP4_KEY_RANGE_RED                                                    0x4255
++#define mmDCP5_KEY_RANGE_RED                                                    0x4455
++#define mmKEY_RANGE_GREEN                                                       0x1a56
++#define mmDCP0_KEY_RANGE_GREEN                                                  0x1a56
++#define mmDCP1_KEY_RANGE_GREEN                                                  0x1c56
++#define mmDCP2_KEY_RANGE_GREEN                                                  0x1e56
++#define mmDCP3_KEY_RANGE_GREEN                                                  0x4056
++#define mmDCP4_KEY_RANGE_GREEN                                                  0x4256
++#define mmDCP5_KEY_RANGE_GREEN                                                  0x4456
++#define mmKEY_RANGE_BLUE                                                        0x1a57
++#define mmDCP0_KEY_RANGE_BLUE                                                   0x1a57
++#define mmDCP1_KEY_RANGE_BLUE                                                   0x1c57
++#define mmDCP2_KEY_RANGE_BLUE                                                   0x1e57
++#define mmDCP3_KEY_RANGE_BLUE                                                   0x4057
++#define mmDCP4_KEY_RANGE_BLUE                                                   0x4257
++#define mmDCP5_KEY_RANGE_BLUE                                                   0x4457
++#define mmDEGAMMA_CONTROL                                                       0x1a58
++#define mmDCP0_DEGAMMA_CONTROL                                                  0x1a58
++#define mmDCP1_DEGAMMA_CONTROL                                                  0x1c58
++#define mmDCP2_DEGAMMA_CONTROL                                                  0x1e58
++#define mmDCP3_DEGAMMA_CONTROL                                                  0x4058
++#define mmDCP4_DEGAMMA_CONTROL                                                  0x4258
++#define mmDCP5_DEGAMMA_CONTROL                                                  0x4458
++#define mmGAMUT_REMAP_CONTROL                                                   0x1a59
++#define mmDCP0_GAMUT_REMAP_CONTROL                                              0x1a59
++#define mmDCP1_GAMUT_REMAP_CONTROL                                              0x1c59
++#define mmDCP2_GAMUT_REMAP_CONTROL                                              0x1e59
++#define mmDCP3_GAMUT_REMAP_CONTROL                                              0x4059
++#define mmDCP4_GAMUT_REMAP_CONTROL                                              0x4259
++#define mmDCP5_GAMUT_REMAP_CONTROL                                              0x4459
++#define mmGAMUT_REMAP_C11_C12                                                   0x1a5a
++#define mmDCP0_GAMUT_REMAP_C11_C12                                              0x1a5a
++#define mmDCP1_GAMUT_REMAP_C11_C12                                              0x1c5a
++#define mmDCP2_GAMUT_REMAP_C11_C12                                              0x1e5a
++#define mmDCP3_GAMUT_REMAP_C11_C12                                              0x405a
++#define mmDCP4_GAMUT_REMAP_C11_C12                                              0x425a
++#define mmDCP5_GAMUT_REMAP_C11_C12                                              0x445a
++#define mmGAMUT_REMAP_C13_C14                                                   0x1a5b
++#define mmDCP0_GAMUT_REMAP_C13_C14                                              0x1a5b
++#define mmDCP1_GAMUT_REMAP_C13_C14                                              0x1c5b
++#define mmDCP2_GAMUT_REMAP_C13_C14                                              0x1e5b
++#define mmDCP3_GAMUT_REMAP_C13_C14                                              0x405b
++#define mmDCP4_GAMUT_REMAP_C13_C14                                              0x425b
++#define mmDCP5_GAMUT_REMAP_C13_C14                                              0x445b
++#define mmGAMUT_REMAP_C21_C22                                                   0x1a5c
++#define mmDCP0_GAMUT_REMAP_C21_C22                                              0x1a5c
++#define mmDCP1_GAMUT_REMAP_C21_C22                                              0x1c5c
++#define mmDCP2_GAMUT_REMAP_C21_C22                                              0x1e5c
++#define mmDCP3_GAMUT_REMAP_C21_C22                                              0x405c
++#define mmDCP4_GAMUT_REMAP_C21_C22                                              0x425c
++#define mmDCP5_GAMUT_REMAP_C21_C22                                              0x445c
++#define mmGAMUT_REMAP_C23_C24                                                   0x1a5d
++#define mmDCP0_GAMUT_REMAP_C23_C24                                              0x1a5d
++#define mmDCP1_GAMUT_REMAP_C23_C24                                              0x1c5d
++#define mmDCP2_GAMUT_REMAP_C23_C24                                              0x1e5d
++#define mmDCP3_GAMUT_REMAP_C23_C24                                              0x405d
++#define mmDCP4_GAMUT_REMAP_C23_C24                                              0x425d
++#define mmDCP5_GAMUT_REMAP_C23_C24                                              0x445d
++#define mmGAMUT_REMAP_C31_C32                                                   0x1a5e
++#define mmDCP0_GAMUT_REMAP_C31_C32                                              0x1a5e
++#define mmDCP1_GAMUT_REMAP_C31_C32                                              0x1c5e
++#define mmDCP2_GAMUT_REMAP_C31_C32                                              0x1e5e
++#define mmDCP3_GAMUT_REMAP_C31_C32                                              0x405e
++#define mmDCP4_GAMUT_REMAP_C31_C32                                              0x425e
++#define mmDCP5_GAMUT_REMAP_C31_C32                                              0x445e
++#define mmGAMUT_REMAP_C33_C34                                                   0x1a5f
++#define mmDCP0_GAMUT_REMAP_C33_C34                                              0x1a5f
++#define mmDCP1_GAMUT_REMAP_C33_C34                                              0x1c5f
++#define mmDCP2_GAMUT_REMAP_C33_C34                                              0x1e5f
++#define mmDCP3_GAMUT_REMAP_C33_C34                                              0x405f
++#define mmDCP4_GAMUT_REMAP_C33_C34                                              0x425f
++#define mmDCP5_GAMUT_REMAP_C33_C34                                              0x445f
++#define mmDCP_SPATIAL_DITHER_CNTL                                               0x1a60
++#define mmDCP0_DCP_SPATIAL_DITHER_CNTL                                          0x1a60
++#define mmDCP1_DCP_SPATIAL_DITHER_CNTL                                          0x1c60
++#define mmDCP2_DCP_SPATIAL_DITHER_CNTL                                          0x1e60
++#define mmDCP3_DCP_SPATIAL_DITHER_CNTL                                          0x4060
++#define mmDCP4_DCP_SPATIAL_DITHER_CNTL                                          0x4260
++#define mmDCP5_DCP_SPATIAL_DITHER_CNTL                                          0x4460
++#define mmDCP_RANDOM_SEEDS                                                      0x1a61
++#define mmDCP0_DCP_RANDOM_SEEDS                                                 0x1a61
++#define mmDCP1_DCP_RANDOM_SEEDS                                                 0x1c61
++#define mmDCP2_DCP_RANDOM_SEEDS                                                 0x1e61
++#define mmDCP3_DCP_RANDOM_SEEDS                                                 0x4061
++#define mmDCP4_DCP_RANDOM_SEEDS                                                 0x4261
++#define mmDCP5_DCP_RANDOM_SEEDS                                                 0x4461
++#define mmDCP_FP_CONVERTED_FIELD                                                0x1a65
++#define mmDCP0_DCP_FP_CONVERTED_FIELD                                           0x1a65
++#define mmDCP1_DCP_FP_CONVERTED_FIELD                                           0x1c65
++#define mmDCP2_DCP_FP_CONVERTED_FIELD                                           0x1e65
++#define mmDCP3_DCP_FP_CONVERTED_FIELD                                           0x4065
++#define mmDCP4_DCP_FP_CONVERTED_FIELD                                           0x4265
++#define mmDCP5_DCP_FP_CONVERTED_FIELD                                           0x4465
++#define mmCUR_CONTROL                                                           0x1a66
++#define mmDCP0_CUR_CONTROL                                                      0x1a66
++#define mmDCP1_CUR_CONTROL                                                      0x1c66
++#define mmDCP2_CUR_CONTROL                                                      0x1e66
++#define mmDCP3_CUR_CONTROL                                                      0x4066
++#define mmDCP4_CUR_CONTROL                                                      0x4266
++#define mmDCP5_CUR_CONTROL                                                      0x4466
++#define mmCUR_SURFACE_ADDRESS                                                   0x1a67
++#define mmDCP0_CUR_SURFACE_ADDRESS                                              0x1a67
++#define mmDCP1_CUR_SURFACE_ADDRESS                                              0x1c67
++#define mmDCP2_CUR_SURFACE_ADDRESS                                              0x1e67
++#define mmDCP3_CUR_SURFACE_ADDRESS                                              0x4067
++#define mmDCP4_CUR_SURFACE_ADDRESS                                              0x4267
++#define mmDCP5_CUR_SURFACE_ADDRESS                                              0x4467
++#define mmCUR_SIZE                                                              0x1a68
++#define mmDCP0_CUR_SIZE                                                         0x1a68
++#define mmDCP1_CUR_SIZE                                                         0x1c68
++#define mmDCP2_CUR_SIZE                                                         0x1e68
++#define mmDCP3_CUR_SIZE                                                         0x4068
++#define mmDCP4_CUR_SIZE                                                         0x4268
++#define mmDCP5_CUR_SIZE                                                         0x4468
++#define mmCUR_SURFACE_ADDRESS_HIGH                                              0x1a69
++#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                         0x1a69
++#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                         0x1c69
++#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                         0x1e69
++#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                         0x4069
++#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                         0x4269
++#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                         0x4469
++#define mmCUR_POSITION                                                          0x1a6a
++#define mmDCP0_CUR_POSITION                                                     0x1a6a
++#define mmDCP1_CUR_POSITION                                                     0x1c6a
++#define mmDCP2_CUR_POSITION                                                     0x1e6a
++#define mmDCP3_CUR_POSITION                                                     0x406a
++#define mmDCP4_CUR_POSITION                                                     0x426a
++#define mmDCP5_CUR_POSITION                                                     0x446a
++#define mmCUR_HOT_SPOT                                                          0x1a6b
++#define mmDCP0_CUR_HOT_SPOT                                                     0x1a6b
++#define mmDCP1_CUR_HOT_SPOT                                                     0x1c6b
++#define mmDCP2_CUR_HOT_SPOT                                                     0x1e6b
++#define mmDCP3_CUR_HOT_SPOT                                                     0x406b
++#define mmDCP4_CUR_HOT_SPOT                                                     0x426b
++#define mmDCP5_CUR_HOT_SPOT                                                     0x446b
++#define mmCUR_COLOR1                                                            0x1a6c
++#define mmDCP0_CUR_COLOR1                                                       0x1a6c
++#define mmDCP1_CUR_COLOR1                                                       0x1c6c
++#define mmDCP2_CUR_COLOR1                                                       0x1e6c
++#define mmDCP3_CUR_COLOR1                                                       0x406c
++#define mmDCP4_CUR_COLOR1                                                       0x426c
++#define mmDCP5_CUR_COLOR1                                                       0x446c
++#define mmCUR_COLOR2                                                            0x1a6d
++#define mmDCP0_CUR_COLOR2                                                       0x1a6d
++#define mmDCP1_CUR_COLOR2                                                       0x1c6d
++#define mmDCP2_CUR_COLOR2                                                       0x1e6d
++#define mmDCP3_CUR_COLOR2                                                       0x406d
++#define mmDCP4_CUR_COLOR2                                                       0x426d
++#define mmDCP5_CUR_COLOR2                                                       0x446d
++#define mmCUR_UPDATE                                                            0x1a6e
++#define mmDCP0_CUR_UPDATE                                                       0x1a6e
++#define mmDCP1_CUR_UPDATE                                                       0x1c6e
++#define mmDCP2_CUR_UPDATE                                                       0x1e6e
++#define mmDCP3_CUR_UPDATE                                                       0x406e
++#define mmDCP4_CUR_UPDATE                                                       0x426e
++#define mmDCP5_CUR_UPDATE                                                       0x446e
++#define mmCUR_REQUEST_FILTER_CNTL                                               0x1a99
++#define mmDCP0_CUR_REQUEST_FILTER_CNTL                                          0x1a99
++#define mmDCP1_CUR_REQUEST_FILTER_CNTL                                          0x1c99
++#define mmDCP2_CUR_REQUEST_FILTER_CNTL                                          0x1e99
++#define mmDCP3_CUR_REQUEST_FILTER_CNTL                                          0x4099
++#define mmDCP4_CUR_REQUEST_FILTER_CNTL                                          0x4299
++#define mmDCP5_CUR_REQUEST_FILTER_CNTL                                          0x4499
++#define mmCUR_STEREO_CONTROL                                                    0x1a9a
++#define mmDCP0_CUR_STEREO_CONTROL                                               0x1a9a
++#define mmDCP1_CUR_STEREO_CONTROL                                               0x1c9a
++#define mmDCP2_CUR_STEREO_CONTROL                                               0x1e9a
++#define mmDCP3_CUR_STEREO_CONTROL                                               0x409a
++#define mmDCP4_CUR_STEREO_CONTROL                                               0x429a
++#define mmDCP5_CUR_STEREO_CONTROL                                               0x449a
++#define mmDC_LUT_RW_MODE                                                        0x1a78
++#define mmDCP0_DC_LUT_RW_MODE                                                   0x1a78
++#define mmDCP1_DC_LUT_RW_MODE                                                   0x1c78
++#define mmDCP2_DC_LUT_RW_MODE                                                   0x1e78
++#define mmDCP3_DC_LUT_RW_MODE                                                   0x4078
++#define mmDCP4_DC_LUT_RW_MODE                                                   0x4278
++#define mmDCP5_DC_LUT_RW_MODE                                                   0x4478
++#define mmDC_LUT_RW_INDEX                                                       0x1a79
++#define mmDCP0_DC_LUT_RW_INDEX                                                  0x1a79
++#define mmDCP1_DC_LUT_RW_INDEX                                                  0x1c79
++#define mmDCP2_DC_LUT_RW_INDEX                                                  0x1e79
++#define mmDCP3_DC_LUT_RW_INDEX                                                  0x4079
++#define mmDCP4_DC_LUT_RW_INDEX                                                  0x4279
++#define mmDCP5_DC_LUT_RW_INDEX                                                  0x4479
++#define mmDC_LUT_SEQ_COLOR                                                      0x1a7a
++#define mmDCP0_DC_LUT_SEQ_COLOR                                                 0x1a7a
++#define mmDCP1_DC_LUT_SEQ_COLOR                                                 0x1c7a
++#define mmDCP2_DC_LUT_SEQ_COLOR                                                 0x1e7a
++#define mmDCP3_DC_LUT_SEQ_COLOR                                                 0x407a
++#define mmDCP4_DC_LUT_SEQ_COLOR                                                 0x427a
++#define mmDCP5_DC_LUT_SEQ_COLOR                                                 0x447a
++#define mmDC_LUT_PWL_DATA                                                       0x1a7b
++#define mmDCP0_DC_LUT_PWL_DATA                                                  0x1a7b
++#define mmDCP1_DC_LUT_PWL_DATA                                                  0x1c7b
++#define mmDCP2_DC_LUT_PWL_DATA                                                  0x1e7b
++#define mmDCP3_DC_LUT_PWL_DATA                                                  0x407b
++#define mmDCP4_DC_LUT_PWL_DATA                                                  0x427b
++#define mmDCP5_DC_LUT_PWL_DATA                                                  0x447b
++#define mmDC_LUT_30_COLOR                                                       0x1a7c
++#define mmDCP0_DC_LUT_30_COLOR                                                  0x1a7c
++#define mmDCP1_DC_LUT_30_COLOR                                                  0x1c7c
++#define mmDCP2_DC_LUT_30_COLOR                                                  0x1e7c
++#define mmDCP3_DC_LUT_30_COLOR                                                  0x407c
++#define mmDCP4_DC_LUT_30_COLOR                                                  0x427c
++#define mmDCP5_DC_LUT_30_COLOR                                                  0x447c
++#define mmDC_LUT_VGA_ACCESS_ENABLE                                              0x1a7d
++#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                         0x1a7d
++#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                         0x1c7d
++#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                         0x1e7d
++#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                         0x407d
++#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                         0x427d
++#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                         0x447d
++#define mmDC_LUT_WRITE_EN_MASK                                                  0x1a7e
++#define mmDCP0_DC_LUT_WRITE_EN_MASK                                             0x1a7e
++#define mmDCP1_DC_LUT_WRITE_EN_MASK                                             0x1c7e
++#define mmDCP2_DC_LUT_WRITE_EN_MASK                                             0x1e7e
++#define mmDCP3_DC_LUT_WRITE_EN_MASK                                             0x407e
++#define mmDCP4_DC_LUT_WRITE_EN_MASK                                             0x427e
++#define mmDCP5_DC_LUT_WRITE_EN_MASK                                             0x447e
++#define mmDC_LUT_AUTOFILL                                                       0x1a7f
++#define mmDCP0_DC_LUT_AUTOFILL                                                  0x1a7f
++#define mmDCP1_DC_LUT_AUTOFILL                                                  0x1c7f
++#define mmDCP2_DC_LUT_AUTOFILL                                                  0x1e7f
++#define mmDCP3_DC_LUT_AUTOFILL                                                  0x407f
++#define mmDCP4_DC_LUT_AUTOFILL                                                  0x427f
++#define mmDCP5_DC_LUT_AUTOFILL                                                  0x447f
++#define mmDC_LUT_CONTROL                                                        0x1a80
++#define mmDCP0_DC_LUT_CONTROL                                                   0x1a80
++#define mmDCP1_DC_LUT_CONTROL                                                   0x1c80
++#define mmDCP2_DC_LUT_CONTROL                                                   0x1e80
++#define mmDCP3_DC_LUT_CONTROL                                                   0x4080
++#define mmDCP4_DC_LUT_CONTROL                                                   0x4280
++#define mmDCP5_DC_LUT_CONTROL                                                   0x4480
++#define mmDC_LUT_BLACK_OFFSET_BLUE                                              0x1a81
++#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                         0x1a81
++#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                         0x1c81
++#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                         0x1e81
++#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                         0x4081
++#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                         0x4281
++#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                         0x4481
++#define mmDC_LUT_BLACK_OFFSET_GREEN                                             0x1a82
++#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                        0x1a82
++#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                        0x1c82
++#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                        0x1e82
++#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                        0x4082
++#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                        0x4282
++#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                        0x4482
++#define mmDC_LUT_BLACK_OFFSET_RED                                               0x1a83
++#define mmDCP0_DC_LUT_BLACK_OFFSET_RED                                          0x1a83
++#define mmDCP1_DC_LUT_BLACK_OFFSET_RED                                          0x1c83
++#define mmDCP2_DC_LUT_BLACK_OFFSET_RED                                          0x1e83
++#define mmDCP3_DC_LUT_BLACK_OFFSET_RED                                          0x4083
++#define mmDCP4_DC_LUT_BLACK_OFFSET_RED                                          0x4283
++#define mmDCP5_DC_LUT_BLACK_OFFSET_RED                                          0x4483
++#define mmDC_LUT_WHITE_OFFSET_BLUE                                              0x1a84
++#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                         0x1a84
++#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                         0x1c84
++#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                         0x1e84
++#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                         0x4084
++#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                         0x4284
++#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                         0x4484
++#define mmDC_LUT_WHITE_OFFSET_GREEN                                             0x1a85
++#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                        0x1a85
++#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                        0x1c85
++#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                        0x1e85
++#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                        0x4085
++#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                        0x4285
++#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                        0x4485
++#define mmDC_LUT_WHITE_OFFSET_RED                                               0x1a86
++#define mmDCP0_DC_LUT_WHITE_OFFSET_RED                                          0x1a86
++#define mmDCP1_DC_LUT_WHITE_OFFSET_RED                                          0x1c86
++#define mmDCP2_DC_LUT_WHITE_OFFSET_RED                                          0x1e86
++#define mmDCP3_DC_LUT_WHITE_OFFSET_RED                                          0x4086
++#define mmDCP4_DC_LUT_WHITE_OFFSET_RED                                          0x4286
++#define mmDCP5_DC_LUT_WHITE_OFFSET_RED                                          0x4486
++#define mmDCP_CRC_CONTROL                                                       0x1a87
++#define mmDCP0_DCP_CRC_CONTROL                                                  0x1a87
++#define mmDCP1_DCP_CRC_CONTROL                                                  0x1c87
++#define mmDCP2_DCP_CRC_CONTROL                                                  0x1e87
++#define mmDCP3_DCP_CRC_CONTROL                                                  0x4087
++#define mmDCP4_DCP_CRC_CONTROL                                                  0x4287
++#define mmDCP5_DCP_CRC_CONTROL                                                  0x4487
++#define mmDCP_CRC_MASK                                                          0x1a88
++#define mmDCP0_DCP_CRC_MASK                                                     0x1a88
++#define mmDCP1_DCP_CRC_MASK                                                     0x1c88
++#define mmDCP2_DCP_CRC_MASK                                                     0x1e88
++#define mmDCP3_DCP_CRC_MASK                                                     0x4088
++#define mmDCP4_DCP_CRC_MASK                                                     0x4288
++#define mmDCP5_DCP_CRC_MASK                                                     0x4488
++#define mmDCP_CRC_CURRENT                                                       0x1a89
++#define mmDCP0_DCP_CRC_CURRENT                                                  0x1a89
++#define mmDCP1_DCP_CRC_CURRENT                                                  0x1c89
++#define mmDCP2_DCP_CRC_CURRENT                                                  0x1e89
++#define mmDCP3_DCP_CRC_CURRENT                                                  0x4089
++#define mmDCP4_DCP_CRC_CURRENT                                                  0x4289
++#define mmDCP5_DCP_CRC_CURRENT                                                  0x4489
++#define mmDCP_CRC_LAST                                                          0x1a8b
++#define mmDCP0_DCP_CRC_LAST                                                     0x1a8b
++#define mmDCP1_DCP_CRC_LAST                                                     0x1c8b
++#define mmDCP2_DCP_CRC_LAST                                                     0x1e8b
++#define mmDCP3_DCP_CRC_LAST                                                     0x408b
++#define mmDCP4_DCP_CRC_LAST                                                     0x428b
++#define mmDCP5_DCP_CRC_LAST                                                     0x448b
++#define mmDCP_DEBUG                                                             0x1a8d
++#define mmDCP0_DCP_DEBUG                                                        0x1a8d
++#define mmDCP1_DCP_DEBUG                                                        0x1c8d
++#define mmDCP2_DCP_DEBUG                                                        0x1e8d
++#define mmDCP3_DCP_DEBUG                                                        0x408d
++#define mmDCP4_DCP_DEBUG                                                        0x428d
++#define mmDCP5_DCP_DEBUG                                                        0x448d
++#define mmGRPH_FLIP_RATE_CNTL                                                   0x1a8e
++#define mmDCP0_GRPH_FLIP_RATE_CNTL                                              0x1a8e
++#define mmDCP1_GRPH_FLIP_RATE_CNTL                                              0x1c8e
++#define mmDCP2_GRPH_FLIP_RATE_CNTL                                              0x1e8e
++#define mmDCP3_GRPH_FLIP_RATE_CNTL                                              0x408e
++#define mmDCP4_GRPH_FLIP_RATE_CNTL                                              0x428e
++#define mmDCP5_GRPH_FLIP_RATE_CNTL                                              0x448e
++#define mmDCP_GSL_CONTROL                                                       0x1a90
++#define mmDCP0_DCP_GSL_CONTROL                                                  0x1a90
++#define mmDCP1_DCP_GSL_CONTROL                                                  0x1c90
++#define mmDCP2_DCP_GSL_CONTROL                                                  0x1e90
++#define mmDCP3_DCP_GSL_CONTROL                                                  0x4090
++#define mmDCP4_DCP_GSL_CONTROL                                                  0x4290
++#define mmDCP5_DCP_GSL_CONTROL                                                  0x4490
++#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x1a91
++#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1a91
++#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1c91
++#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1e91
++#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4091
++#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4291
++#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4491
++#define mmOVL_SECONDARY_SURFACE_ADDRESS                                         0x1a92
++#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1a92
++#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1c92
++#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS                                    0x1e92
++#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4092
++#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4292
++#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS                                    0x4492
++#define mmOVL_STEREOSYNC_FLIP                                                   0x1a93
++#define mmDCP0_OVL_STEREOSYNC_FLIP                                              0x1a93
++#define mmDCP1_OVL_STEREOSYNC_FLIP                                              0x1c93
++#define mmDCP2_OVL_STEREOSYNC_FLIP                                              0x1e93
++#define mmDCP3_OVL_STEREOSYNC_FLIP                                              0x4093
++#define mmDCP4_OVL_STEREOSYNC_FLIP                                              0x4293
++#define mmDCP5_OVL_STEREOSYNC_FLIP                                              0x4493
++#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH                                    0x1a94
++#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1a94
++#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1c94
++#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x1e94
++#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4094
++#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4294
++#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH                               0x4494
++#define mmDCP_TEST_DEBUG_INDEX                                                  0x1a95
++#define mmDCP0_DCP_TEST_DEBUG_INDEX                                             0x1a95
++#define mmDCP1_DCP_TEST_DEBUG_INDEX                                             0x1c95
++#define mmDCP2_DCP_TEST_DEBUG_INDEX                                             0x1e95
++#define mmDCP3_DCP_TEST_DEBUG_INDEX                                             0x4095
++#define mmDCP4_DCP_TEST_DEBUG_INDEX                                             0x4295
++#define mmDCP5_DCP_TEST_DEBUG_INDEX                                             0x4495
++#define mmDCP_TEST_DEBUG_DATA                                                   0x1a96
++#define mmDCP0_DCP_TEST_DEBUG_DATA                                              0x1a96
++#define mmDCP1_DCP_TEST_DEBUG_DATA                                              0x1c96
++#define mmDCP2_DCP_TEST_DEBUG_DATA                                              0x1e96
++#define mmDCP3_DCP_TEST_DEBUG_DATA                                              0x4096
++#define mmDCP4_DCP_TEST_DEBUG_DATA                                              0x4296
++#define mmDCP5_DCP_TEST_DEBUG_DATA                                              0x4496
++#define mmGRPH_STEREOSYNC_FLIP                                                  0x1a97
++#define mmDCP0_GRPH_STEREOSYNC_FLIP                                             0x1a97
++#define mmDCP1_GRPH_STEREOSYNC_FLIP                                             0x1c97
++#define mmDCP2_GRPH_STEREOSYNC_FLIP                                             0x1e97
++#define mmDCP3_GRPH_STEREOSYNC_FLIP                                             0x4097
++#define mmDCP4_GRPH_STEREOSYNC_FLIP                                             0x4297
++#define mmDCP5_GRPH_STEREOSYNC_FLIP                                             0x4497
++#define mmDCP_DEBUG2                                                            0x1a98
++#define mmDCP0_DCP_DEBUG2                                                       0x1a98
++#define mmDCP1_DCP_DEBUG2                                                       0x1c98
++#define mmDCP2_DCP_DEBUG2                                                       0x1e98
++#define mmDCP3_DCP_DEBUG2                                                       0x4098
++#define mmDCP4_DCP_DEBUG2                                                       0x4298
++#define mmDCP5_DCP_DEBUG2                                                       0x4498
++#define mmHW_ROTATION                                                           0x1a9e
++#define mmDCP0_HW_ROTATION                                                      0x1a9e
++#define mmDCP1_HW_ROTATION                                                      0x1c9e
++#define mmDCP2_HW_ROTATION                                                      0x1e9e
++#define mmDCP3_HW_ROTATION                                                      0x409e
++#define mmDCP4_HW_ROTATION                                                      0x429e
++#define mmDCP5_HW_ROTATION                                                      0x449e
++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                    0x1a9f
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1a9f
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1c9f
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1e9f
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x409f
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x429f
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x449f
++#define mmREGAMMA_CONTROL                                                       0x1aa0
++#define mmDCP0_REGAMMA_CONTROL                                                  0x1aa0
++#define mmDCP1_REGAMMA_CONTROL                                                  0x1ca0
++#define mmDCP2_REGAMMA_CONTROL                                                  0x1ea0
++#define mmDCP3_REGAMMA_CONTROL                                                  0x40a0
++#define mmDCP4_REGAMMA_CONTROL                                                  0x42a0
++#define mmDCP5_REGAMMA_CONTROL                                                  0x44a0
++#define mmREGAMMA_LUT_INDEX                                                     0x1aa1
++#define mmDCP0_REGAMMA_LUT_INDEX                                                0x1aa1
++#define mmDCP1_REGAMMA_LUT_INDEX                                                0x1ca1
++#define mmDCP2_REGAMMA_LUT_INDEX                                                0x1ea1
++#define mmDCP3_REGAMMA_LUT_INDEX                                                0x40a1
++#define mmDCP4_REGAMMA_LUT_INDEX                                                0x42a1
++#define mmDCP5_REGAMMA_LUT_INDEX                                                0x44a1
++#define mmREGAMMA_LUT_DATA                                                      0x1aa2
++#define mmDCP0_REGAMMA_LUT_DATA                                                 0x1aa2
++#define mmDCP1_REGAMMA_LUT_DATA                                                 0x1ca2
++#define mmDCP2_REGAMMA_LUT_DATA                                                 0x1ea2
++#define mmDCP3_REGAMMA_LUT_DATA                                                 0x40a2
++#define mmDCP4_REGAMMA_LUT_DATA                                                 0x42a2
++#define mmDCP5_REGAMMA_LUT_DATA                                                 0x44a2
++#define mmREGAMMA_LUT_WRITE_EN_MASK                                             0x1aa3
++#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                        0x1aa3
++#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ca3
++#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ea3
++#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                        0x40a3
++#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                        0x42a3
++#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                        0x44a3
++#define mmREGAMMA_CNTLA_START_CNTL                                              0x1aa4
++#define mmDCP0_REGAMMA_CNTLA_START_CNTL                                         0x1aa4
++#define mmDCP1_REGAMMA_CNTLA_START_CNTL                                         0x1ca4
++#define mmDCP2_REGAMMA_CNTLA_START_CNTL                                         0x1ea4
++#define mmDCP3_REGAMMA_CNTLA_START_CNTL                                         0x40a4
++#define mmDCP4_REGAMMA_CNTLA_START_CNTL                                         0x42a4
++#define mmDCP5_REGAMMA_CNTLA_START_CNTL                                         0x44a4
++#define mmREGAMMA_CNTLA_SLOPE_CNTL                                              0x1aa5
++#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1aa5
++#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ca5
++#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ea5
++#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                         0x40a5
++#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                         0x42a5
++#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                         0x44a5
++#define mmREGAMMA_CNTLA_END_CNTL1                                               0x1aa6
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL1                                          0x1aa6
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL1                                          0x1ca6
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL1                                          0x1ea6
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL1                                          0x40a6
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL1                                          0x42a6
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL1                                          0x44a6
++#define mmREGAMMA_CNTLA_END_CNTL2                                               0x1aa7
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL2                                          0x1aa7
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL2                                          0x1ca7
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL2                                          0x1ea7
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL2                                          0x40a7
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL2                                          0x42a7
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL2                                          0x44a7
++#define mmREGAMMA_CNTLA_REGION_0_1                                              0x1aa8
++#define mmDCP0_REGAMMA_CNTLA_REGION_0_1                                         0x1aa8
++#define mmDCP1_REGAMMA_CNTLA_REGION_0_1                                         0x1ca8
++#define mmDCP2_REGAMMA_CNTLA_REGION_0_1                                         0x1ea8
++#define mmDCP3_REGAMMA_CNTLA_REGION_0_1                                         0x40a8
++#define mmDCP4_REGAMMA_CNTLA_REGION_0_1                                         0x42a8
++#define mmDCP5_REGAMMA_CNTLA_REGION_0_1                                         0x44a8
++#define mmREGAMMA_CNTLA_REGION_2_3                                              0x1aa9
++#define mmDCP0_REGAMMA_CNTLA_REGION_2_3                                         0x1aa9
++#define mmDCP1_REGAMMA_CNTLA_REGION_2_3                                         0x1ca9
++#define mmDCP2_REGAMMA_CNTLA_REGION_2_3                                         0x1ea9
++#define mmDCP3_REGAMMA_CNTLA_REGION_2_3                                         0x40a9
++#define mmDCP4_REGAMMA_CNTLA_REGION_2_3                                         0x42a9
++#define mmDCP5_REGAMMA_CNTLA_REGION_2_3                                         0x44a9
++#define mmREGAMMA_CNTLA_REGION_4_5                                              0x1aaa
++#define mmDCP0_REGAMMA_CNTLA_REGION_4_5                                         0x1aaa
++#define mmDCP1_REGAMMA_CNTLA_REGION_4_5                                         0x1caa
++#define mmDCP2_REGAMMA_CNTLA_REGION_4_5                                         0x1eaa
++#define mmDCP3_REGAMMA_CNTLA_REGION_4_5                                         0x40aa
++#define mmDCP4_REGAMMA_CNTLA_REGION_4_5                                         0x42aa
++#define mmDCP5_REGAMMA_CNTLA_REGION_4_5                                         0x44aa
++#define mmREGAMMA_CNTLA_REGION_6_7                                              0x1aab
++#define mmDCP0_REGAMMA_CNTLA_REGION_6_7                                         0x1aab
++#define mmDCP1_REGAMMA_CNTLA_REGION_6_7                                         0x1cab
++#define mmDCP2_REGAMMA_CNTLA_REGION_6_7                                         0x1eab
++#define mmDCP3_REGAMMA_CNTLA_REGION_6_7                                         0x40ab
++#define mmDCP4_REGAMMA_CNTLA_REGION_6_7                                         0x42ab
++#define mmDCP5_REGAMMA_CNTLA_REGION_6_7                                         0x44ab
++#define mmREGAMMA_CNTLA_REGION_8_9                                              0x1aac
++#define mmDCP0_REGAMMA_CNTLA_REGION_8_9                                         0x1aac
++#define mmDCP1_REGAMMA_CNTLA_REGION_8_9                                         0x1cac
++#define mmDCP2_REGAMMA_CNTLA_REGION_8_9                                         0x1eac
++#define mmDCP3_REGAMMA_CNTLA_REGION_8_9                                         0x40ac
++#define mmDCP4_REGAMMA_CNTLA_REGION_8_9                                         0x42ac
++#define mmDCP5_REGAMMA_CNTLA_REGION_8_9                                         0x44ac
++#define mmREGAMMA_CNTLA_REGION_10_11                                            0x1aad
++#define mmDCP0_REGAMMA_CNTLA_REGION_10_11                                       0x1aad
++#define mmDCP1_REGAMMA_CNTLA_REGION_10_11                                       0x1cad
++#define mmDCP2_REGAMMA_CNTLA_REGION_10_11                                       0x1ead
++#define mmDCP3_REGAMMA_CNTLA_REGION_10_11                                       0x40ad
++#define mmDCP4_REGAMMA_CNTLA_REGION_10_11                                       0x42ad
++#define mmDCP5_REGAMMA_CNTLA_REGION_10_11                                       0x44ad
++#define mmREGAMMA_CNTLA_REGION_12_13                                            0x1aae
++#define mmDCP0_REGAMMA_CNTLA_REGION_12_13                                       0x1aae
++#define mmDCP1_REGAMMA_CNTLA_REGION_12_13                                       0x1cae
++#define mmDCP2_REGAMMA_CNTLA_REGION_12_13                                       0x1eae
++#define mmDCP3_REGAMMA_CNTLA_REGION_12_13                                       0x40ae
++#define mmDCP4_REGAMMA_CNTLA_REGION_12_13                                       0x42ae
++#define mmDCP5_REGAMMA_CNTLA_REGION_12_13                                       0x44ae
++#define mmREGAMMA_CNTLA_REGION_14_15                                            0x1aaf
++#define mmDCP0_REGAMMA_CNTLA_REGION_14_15                                       0x1aaf
++#define mmDCP1_REGAMMA_CNTLA_REGION_14_15                                       0x1caf
++#define mmDCP2_REGAMMA_CNTLA_REGION_14_15                                       0x1eaf
++#define mmDCP3_REGAMMA_CNTLA_REGION_14_15                                       0x40af
++#define mmDCP4_REGAMMA_CNTLA_REGION_14_15                                       0x42af
++#define mmDCP5_REGAMMA_CNTLA_REGION_14_15                                       0x44af
++#define mmREGAMMA_CNTLB_START_CNTL                                              0x1ab0
++#define mmDCP0_REGAMMA_CNTLB_START_CNTL                                         0x1ab0
++#define mmDCP1_REGAMMA_CNTLB_START_CNTL                                         0x1cb0
++#define mmDCP2_REGAMMA_CNTLB_START_CNTL                                         0x1eb0
++#define mmDCP3_REGAMMA_CNTLB_START_CNTL                                         0x40b0
++#define mmDCP4_REGAMMA_CNTLB_START_CNTL                                         0x42b0
++#define mmDCP5_REGAMMA_CNTLB_START_CNTL                                         0x44b0
++#define mmREGAMMA_CNTLB_SLOPE_CNTL                                              0x1ab1
++#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1ab1
++#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1cb1
++#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1eb1
++#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                         0x40b1
++#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                         0x42b1
++#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                         0x44b1
++#define mmREGAMMA_CNTLB_END_CNTL1                                               0x1ab2
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL1                                          0x1ab2
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL1                                          0x1cb2
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL1                                          0x1eb2
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL1                                          0x40b2
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL1                                          0x42b2
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL1                                          0x44b2
++#define mmREGAMMA_CNTLB_END_CNTL2                                               0x1ab3
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL2                                          0x1ab3
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL2                                          0x1cb3
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL2                                          0x1eb3
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL2                                          0x40b3
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL2                                          0x42b3
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL2                                          0x44b3
++#define mmREGAMMA_CNTLB_REGION_0_1                                              0x1ab4
++#define mmDCP0_REGAMMA_CNTLB_REGION_0_1                                         0x1ab4
++#define mmDCP1_REGAMMA_CNTLB_REGION_0_1                                         0x1cb4
++#define mmDCP2_REGAMMA_CNTLB_REGION_0_1                                         0x1eb4
++#define mmDCP3_REGAMMA_CNTLB_REGION_0_1                                         0x40b4
++#define mmDCP4_REGAMMA_CNTLB_REGION_0_1                                         0x42b4
++#define mmDCP5_REGAMMA_CNTLB_REGION_0_1                                         0x44b4
++#define mmREGAMMA_CNTLB_REGION_2_3                                              0x1ab5
++#define mmDCP0_REGAMMA_CNTLB_REGION_2_3                                         0x1ab5
++#define mmDCP1_REGAMMA_CNTLB_REGION_2_3                                         0x1cb5
++#define mmDCP2_REGAMMA_CNTLB_REGION_2_3                                         0x1eb5
++#define mmDCP3_REGAMMA_CNTLB_REGION_2_3                                         0x40b5
++#define mmDCP4_REGAMMA_CNTLB_REGION_2_3                                         0x42b5
++#define mmDCP5_REGAMMA_CNTLB_REGION_2_3                                         0x44b5
++#define mmREGAMMA_CNTLB_REGION_4_5                                              0x1ab6
++#define mmDCP0_REGAMMA_CNTLB_REGION_4_5                                         0x1ab6
++#define mmDCP1_REGAMMA_CNTLB_REGION_4_5                                         0x1cb6
++#define mmDCP2_REGAMMA_CNTLB_REGION_4_5                                         0x1eb6
++#define mmDCP3_REGAMMA_CNTLB_REGION_4_5                                         0x40b6
++#define mmDCP4_REGAMMA_CNTLB_REGION_4_5                                         0x42b6
++#define mmDCP5_REGAMMA_CNTLB_REGION_4_5                                         0x44b6
++#define mmREGAMMA_CNTLB_REGION_6_7                                              0x1ab7
++#define mmDCP0_REGAMMA_CNTLB_REGION_6_7                                         0x1ab7
++#define mmDCP1_REGAMMA_CNTLB_REGION_6_7                                         0x1cb7
++#define mmDCP2_REGAMMA_CNTLB_REGION_6_7                                         0x1eb7
++#define mmDCP3_REGAMMA_CNTLB_REGION_6_7                                         0x40b7
++#define mmDCP4_REGAMMA_CNTLB_REGION_6_7                                         0x42b7
++#define mmDCP5_REGAMMA_CNTLB_REGION_6_7                                         0x44b7
++#define mmREGAMMA_CNTLB_REGION_8_9                                              0x1ab8
++#define mmDCP0_REGAMMA_CNTLB_REGION_8_9                                         0x1ab8
++#define mmDCP1_REGAMMA_CNTLB_REGION_8_9                                         0x1cb8
++#define mmDCP2_REGAMMA_CNTLB_REGION_8_9                                         0x1eb8
++#define mmDCP3_REGAMMA_CNTLB_REGION_8_9                                         0x40b8
++#define mmDCP4_REGAMMA_CNTLB_REGION_8_9                                         0x42b8
++#define mmDCP5_REGAMMA_CNTLB_REGION_8_9                                         0x44b8
++#define mmREGAMMA_CNTLB_REGION_10_11                                            0x1ab9
++#define mmDCP0_REGAMMA_CNTLB_REGION_10_11                                       0x1ab9
++#define mmDCP1_REGAMMA_CNTLB_REGION_10_11                                       0x1cb9
++#define mmDCP2_REGAMMA_CNTLB_REGION_10_11                                       0x1eb9
++#define mmDCP3_REGAMMA_CNTLB_REGION_10_11                                       0x40b9
++#define mmDCP4_REGAMMA_CNTLB_REGION_10_11                                       0x42b9
++#define mmDCP5_REGAMMA_CNTLB_REGION_10_11                                       0x44b9
++#define mmREGAMMA_CNTLB_REGION_12_13                                            0x1aba
++#define mmDCP0_REGAMMA_CNTLB_REGION_12_13                                       0x1aba
++#define mmDCP1_REGAMMA_CNTLB_REGION_12_13                                       0x1cba
++#define mmDCP2_REGAMMA_CNTLB_REGION_12_13                                       0x1eba
++#define mmDCP3_REGAMMA_CNTLB_REGION_12_13                                       0x40ba
++#define mmDCP4_REGAMMA_CNTLB_REGION_12_13                                       0x42ba
++#define mmDCP5_REGAMMA_CNTLB_REGION_12_13                                       0x44ba
++#define mmREGAMMA_CNTLB_REGION_14_15                                            0x1abb
++#define mmDCP0_REGAMMA_CNTLB_REGION_14_15                                       0x1abb
++#define mmDCP1_REGAMMA_CNTLB_REGION_14_15                                       0x1cbb
++#define mmDCP2_REGAMMA_CNTLB_REGION_14_15                                       0x1ebb
++#define mmDCP3_REGAMMA_CNTLB_REGION_14_15                                       0x40bb
++#define mmDCP4_REGAMMA_CNTLB_REGION_14_15                                       0x42bb
++#define mmDCP5_REGAMMA_CNTLB_REGION_14_15                                       0x44bb
++#define mmALPHA_CONTROL                                                         0x1abc
++#define mmDCP0_ALPHA_CONTROL                                                    0x1abc
++#define mmDCP1_ALPHA_CONTROL                                                    0x1cbc
++#define mmDCP2_ALPHA_CONTROL                                                    0x1ebc
++#define mmDCP3_ALPHA_CONTROL                                                    0x40bc
++#define mmDCP4_ALPHA_CONTROL                                                    0x42bc
++#define mmDCP5_ALPHA_CONTROL                                                    0x44bc
++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                    0x1abd
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1abd
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1cbd
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1ebd
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x40bd
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x42bd
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x44bd
++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                               0x1abe
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1abe
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1cbe
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1ebe
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x40be
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x42be
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x44be
++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                  0x1abf
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1abf
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1cbf
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1ebf
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x40bf
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x42bf
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x44bf
++#define mmDIG_FE_CNTL                                                           0x4a00
++#define mmDIG0_DIG_FE_CNTL                                                      0x4a00
++#define mmDIG1_DIG_FE_CNTL                                                      0x4b00
++#define mmDIG2_DIG_FE_CNTL                                                      0x4c00
++#define mmDIG3_DIG_FE_CNTL                                                      0x4d00
++#define mmDIG4_DIG_FE_CNTL                                                      0x4e00
++#define mmDIG5_DIG_FE_CNTL                                                      0x4f00
++#define mmDIG6_DIG_FE_CNTL                                                      0x5400
++#define mmDIG_OUTPUT_CRC_CNTL                                                   0x4a01
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                              0x4a01
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                              0x4b01
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                              0x4c01
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                              0x4d01
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL                                              0x4e01
++#define mmDIG5_DIG_OUTPUT_CRC_CNTL                                              0x4f01
++#define mmDIG6_DIG_OUTPUT_CRC_CNTL                                              0x5401
++#define mmDIG_OUTPUT_CRC_RESULT                                                 0x4a02
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                            0x4a02
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                            0x4b02
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                            0x4c02
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                            0x4d02
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT                                            0x4e02
++#define mmDIG5_DIG_OUTPUT_CRC_RESULT                                            0x4f02
++#define mmDIG6_DIG_OUTPUT_CRC_RESULT                                            0x5402
++#define mmDIG_CLOCK_PATTERN                                                     0x4a03
++#define mmDIG0_DIG_CLOCK_PATTERN                                                0x4a03
++#define mmDIG1_DIG_CLOCK_PATTERN                                                0x4b03
++#define mmDIG2_DIG_CLOCK_PATTERN                                                0x4c03
++#define mmDIG3_DIG_CLOCK_PATTERN                                                0x4d03
++#define mmDIG4_DIG_CLOCK_PATTERN                                                0x4e03
++#define mmDIG5_DIG_CLOCK_PATTERN                                                0x4f03
++#define mmDIG6_DIG_CLOCK_PATTERN                                                0x5403
++#define mmDIG_TEST_PATTERN                                                      0x4a04
++#define mmDIG0_DIG_TEST_PATTERN                                                 0x4a04
++#define mmDIG1_DIG_TEST_PATTERN                                                 0x4b04
++#define mmDIG2_DIG_TEST_PATTERN                                                 0x4c04
++#define mmDIG3_DIG_TEST_PATTERN                                                 0x4d04
++#define mmDIG4_DIG_TEST_PATTERN                                                 0x4e04
++#define mmDIG5_DIG_TEST_PATTERN                                                 0x4f04
++#define mmDIG6_DIG_TEST_PATTERN                                                 0x5404
++#define mmDIG_RANDOM_PATTERN_SEED                                               0x4a05
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                          0x4a05
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                          0x4b05
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                          0x4c05
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                          0x4d05
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED                                          0x4e05
++#define mmDIG5_DIG_RANDOM_PATTERN_SEED                                          0x4f05
++#define mmDIG6_DIG_RANDOM_PATTERN_SEED                                          0x5405
++#define mmDIG_FIFO_STATUS                                                       0x4a06
++#define mmDIG0_DIG_FIFO_STATUS                                                  0x4a06
++#define mmDIG1_DIG_FIFO_STATUS                                                  0x4b06
++#define mmDIG2_DIG_FIFO_STATUS                                                  0x4c06
++#define mmDIG3_DIG_FIFO_STATUS                                                  0x4d06
++#define mmDIG4_DIG_FIFO_STATUS                                                  0x4e06
++#define mmDIG5_DIG_FIFO_STATUS                                                  0x4f06
++#define mmDIG6_DIG_FIFO_STATUS                                                  0x5406
++#define mmDIG_DISPCLK_SWITCH_CNTL                                               0x4a07
++#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL                                          0x4a07
++#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL                                          0x4b07
++#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL                                          0x4c07
++#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL                                          0x4d07
++#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL                                          0x4e07
++#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL                                          0x4f07
++#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL                                          0x5407
++#define mmDIG_DISPCLK_SWITCH_STATUS                                             0x4a08
++#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS                                        0x4a08
++#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS                                        0x4b08
++#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS                                        0x4c08
++#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS                                        0x4d08
++#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS                                        0x4e08
++#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS                                        0x4f08
++#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS                                        0x5408
++#define mmHDMI_CONTROL                                                          0x4a09
++#define mmDIG0_HDMI_CONTROL                                                     0x4a09
++#define mmDIG1_HDMI_CONTROL                                                     0x4b09
++#define mmDIG2_HDMI_CONTROL                                                     0x4c09
++#define mmDIG3_HDMI_CONTROL                                                     0x4d09
++#define mmDIG4_HDMI_CONTROL                                                     0x4e09
++#define mmDIG5_HDMI_CONTROL                                                     0x4f09
++#define mmDIG6_HDMI_CONTROL                                                     0x5409
++#define mmHDMI_STATUS                                                           0x4a0a
++#define mmDIG0_HDMI_STATUS                                                      0x4a0a
++#define mmDIG1_HDMI_STATUS                                                      0x4b0a
++#define mmDIG2_HDMI_STATUS                                                      0x4c0a
++#define mmDIG3_HDMI_STATUS                                                      0x4d0a
++#define mmDIG4_HDMI_STATUS                                                      0x4e0a
++#define mmDIG5_HDMI_STATUS                                                      0x4f0a
++#define mmDIG6_HDMI_STATUS                                                      0x540a
++#define mmHDMI_AUDIO_PACKET_CONTROL                                             0x4a0b
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                        0x4a0b
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                        0x4b0b
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                        0x4c0b
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                        0x4d0b
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                        0x4e0b
++#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                        0x4f0b
++#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                        0x540b
++#define mmHDMI_ACR_PACKET_CONTROL                                               0x4a0c
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                          0x4a0c
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                          0x4b0c
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                          0x4c0c
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                          0x4d0c
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL                                          0x4e0c
++#define mmDIG5_HDMI_ACR_PACKET_CONTROL                                          0x4f0c
++#define mmDIG6_HDMI_ACR_PACKET_CONTROL                                          0x540c
++#define mmHDMI_VBI_PACKET_CONTROL                                               0x4a0d
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                          0x4a0d
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                          0x4b0d
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                          0x4c0d
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                          0x4d0d
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL                                          0x4e0d
++#define mmDIG5_HDMI_VBI_PACKET_CONTROL                                          0x4f0d
++#define mmDIG6_HDMI_VBI_PACKET_CONTROL                                          0x540d
++#define mmHDMI_INFOFRAME_CONTROL0                                               0x4a0e
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                          0x4a0e
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                          0x4b0e
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                          0x4c0e
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                          0x4d0e
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0                                          0x4e0e
++#define mmDIG5_HDMI_INFOFRAME_CONTROL0                                          0x4f0e
++#define mmDIG6_HDMI_INFOFRAME_CONTROL0                                          0x540e
++#define mmHDMI_INFOFRAME_CONTROL1                                               0x4a0f
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                          0x4a0f
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                          0x4b0f
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                          0x4c0f
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                          0x4d0f
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1                                          0x4e0f
++#define mmDIG5_HDMI_INFOFRAME_CONTROL1                                          0x4f0f
++#define mmDIG6_HDMI_INFOFRAME_CONTROL1                                          0x540f
++#define mmHDMI_GENERIC_PACKET_CONTROL0                                          0x4a10
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                     0x4a10
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                     0x4b10
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                     0x4c10
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                     0x4d10
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                     0x4e10
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                     0x4f10
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                     0x5410
++#define mmAFMT_INTERRUPT_STATUS                                                 0x4a11
++#define mmDIG0_AFMT_INTERRUPT_STATUS                                            0x4a11
++#define mmDIG1_AFMT_INTERRUPT_STATUS                                            0x4b11
++#define mmDIG2_AFMT_INTERRUPT_STATUS                                            0x4c11
++#define mmDIG3_AFMT_INTERRUPT_STATUS                                            0x4d11
++#define mmDIG4_AFMT_INTERRUPT_STATUS                                            0x4e11
++#define mmDIG5_AFMT_INTERRUPT_STATUS                                            0x4f11
++#define mmDIG6_AFMT_INTERRUPT_STATUS                                            0x5411
++#define mmHDMI_GC                                                               0x4a13
++#define mmDIG0_HDMI_GC                                                          0x4a13
++#define mmDIG1_HDMI_GC                                                          0x4b13
++#define mmDIG2_HDMI_GC                                                          0x4c13
++#define mmDIG3_HDMI_GC                                                          0x4d13
++#define mmDIG4_HDMI_GC                                                          0x4e13
++#define mmDIG5_HDMI_GC                                                          0x4f13
++#define mmDIG6_HDMI_GC                                                          0x5413
++#define mmAFMT_AUDIO_PACKET_CONTROL2                                            0x4a14
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                       0x4a14
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                       0x4b14
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                       0x4c14
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                       0x4d14
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                       0x4e14
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                       0x4f14
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                       0x5414
++#define mmAFMT_ISRC1_0                                                          0x4a15
++#define mmDIG0_AFMT_ISRC1_0                                                     0x4a15
++#define mmDIG1_AFMT_ISRC1_0                                                     0x4b15
++#define mmDIG2_AFMT_ISRC1_0                                                     0x4c15
++#define mmDIG3_AFMT_ISRC1_0                                                     0x4d15
++#define mmDIG4_AFMT_ISRC1_0                                                     0x4e15
++#define mmDIG5_AFMT_ISRC1_0                                                     0x4f15
++#define mmDIG6_AFMT_ISRC1_0                                                     0x5415
++#define mmAFMT_ISRC1_1                                                          0x4a16
++#define mmDIG0_AFMT_ISRC1_1                                                     0x4a16
++#define mmDIG1_AFMT_ISRC1_1                                                     0x4b16
++#define mmDIG2_AFMT_ISRC1_1                                                     0x4c16
++#define mmDIG3_AFMT_ISRC1_1                                                     0x4d16
++#define mmDIG4_AFMT_ISRC1_1                                                     0x4e16
++#define mmDIG5_AFMT_ISRC1_1                                                     0x4f16
++#define mmDIG6_AFMT_ISRC1_1                                                     0x5416
++#define mmAFMT_ISRC1_2                                                          0x4a17
++#define mmDIG0_AFMT_ISRC1_2                                                     0x4a17
++#define mmDIG1_AFMT_ISRC1_2                                                     0x4b17
++#define mmDIG2_AFMT_ISRC1_2                                                     0x4c17
++#define mmDIG3_AFMT_ISRC1_2                                                     0x4d17
++#define mmDIG4_AFMT_ISRC1_2                                                     0x4e17
++#define mmDIG5_AFMT_ISRC1_2                                                     0x4f17
++#define mmDIG6_AFMT_ISRC1_2                                                     0x5417
++#define mmAFMT_ISRC1_3                                                          0x4a18
++#define mmDIG0_AFMT_ISRC1_3                                                     0x4a18
++#define mmDIG1_AFMT_ISRC1_3                                                     0x4b18
++#define mmDIG2_AFMT_ISRC1_3                                                     0x4c18
++#define mmDIG3_AFMT_ISRC1_3                                                     0x4d18
++#define mmDIG4_AFMT_ISRC1_3                                                     0x4e18
++#define mmDIG5_AFMT_ISRC1_3                                                     0x4f18
++#define mmDIG6_AFMT_ISRC1_3                                                     0x5418
++#define mmAFMT_ISRC1_4                                                          0x4a19
++#define mmDIG0_AFMT_ISRC1_4                                                     0x4a19
++#define mmDIG1_AFMT_ISRC1_4                                                     0x4b19
++#define mmDIG2_AFMT_ISRC1_4                                                     0x4c19
++#define mmDIG3_AFMT_ISRC1_4                                                     0x4d19
++#define mmDIG4_AFMT_ISRC1_4                                                     0x4e19
++#define mmDIG5_AFMT_ISRC1_4                                                     0x4f19
++#define mmDIG6_AFMT_ISRC1_4                                                     0x5419
++#define mmAFMT_ISRC2_0                                                          0x4a1a
++#define mmDIG0_AFMT_ISRC2_0                                                     0x4a1a
++#define mmDIG1_AFMT_ISRC2_0                                                     0x4b1a
++#define mmDIG2_AFMT_ISRC2_0                                                     0x4c1a
++#define mmDIG3_AFMT_ISRC2_0                                                     0x4d1a
++#define mmDIG4_AFMT_ISRC2_0                                                     0x4e1a
++#define mmDIG5_AFMT_ISRC2_0                                                     0x4f1a
++#define mmDIG6_AFMT_ISRC2_0                                                     0x541a
++#define mmAFMT_ISRC2_1                                                          0x4a1b
++#define mmDIG0_AFMT_ISRC2_1                                                     0x4a1b
++#define mmDIG1_AFMT_ISRC2_1                                                     0x4b1b
++#define mmDIG2_AFMT_ISRC2_1                                                     0x4c1b
++#define mmDIG3_AFMT_ISRC2_1                                                     0x4d1b
++#define mmDIG4_AFMT_ISRC2_1                                                     0x4e1b
++#define mmDIG5_AFMT_ISRC2_1                                                     0x4f1b
++#define mmDIG6_AFMT_ISRC2_1                                                     0x541b
++#define mmAFMT_ISRC2_2                                                          0x4a1c
++#define mmDIG0_AFMT_ISRC2_2                                                     0x4a1c
++#define mmDIG1_AFMT_ISRC2_2                                                     0x4b1c
++#define mmDIG2_AFMT_ISRC2_2                                                     0x4c1c
++#define mmDIG3_AFMT_ISRC2_2                                                     0x4d1c
++#define mmDIG4_AFMT_ISRC2_2                                                     0x4e1c
++#define mmDIG5_AFMT_ISRC2_2                                                     0x4f1c
++#define mmDIG6_AFMT_ISRC2_2                                                     0x541c
++#define mmAFMT_ISRC2_3                                                          0x4a1d
++#define mmDIG0_AFMT_ISRC2_3                                                     0x4a1d
++#define mmDIG1_AFMT_ISRC2_3                                                     0x4b1d
++#define mmDIG2_AFMT_ISRC2_3                                                     0x4c1d
++#define mmDIG3_AFMT_ISRC2_3                                                     0x4d1d
++#define mmDIG4_AFMT_ISRC2_3                                                     0x4e1d
++#define mmDIG5_AFMT_ISRC2_3                                                     0x4f1d
++#define mmDIG6_AFMT_ISRC2_3                                                     0x541d
++#define mmAFMT_AVI_INFO0                                                        0x4a1e
++#define mmDIG0_AFMT_AVI_INFO0                                                   0x4a1e
++#define mmDIG1_AFMT_AVI_INFO0                                                   0x4b1e
++#define mmDIG2_AFMT_AVI_INFO0                                                   0x4c1e
++#define mmDIG3_AFMT_AVI_INFO0                                                   0x4d1e
++#define mmDIG4_AFMT_AVI_INFO0                                                   0x4e1e
++#define mmDIG5_AFMT_AVI_INFO0                                                   0x4f1e
++#define mmDIG6_AFMT_AVI_INFO0                                                   0x541e
++#define mmAFMT_AVI_INFO1                                                        0x4a1f
++#define mmDIG0_AFMT_AVI_INFO1                                                   0x4a1f
++#define mmDIG1_AFMT_AVI_INFO1                                                   0x4b1f
++#define mmDIG2_AFMT_AVI_INFO1                                                   0x4c1f
++#define mmDIG3_AFMT_AVI_INFO1                                                   0x4d1f
++#define mmDIG4_AFMT_AVI_INFO1                                                   0x4e1f
++#define mmDIG5_AFMT_AVI_INFO1                                                   0x4f1f
++#define mmDIG6_AFMT_AVI_INFO1                                                   0x541f
++#define mmAFMT_AVI_INFO2                                                        0x4a20
++#define mmDIG0_AFMT_AVI_INFO2                                                   0x4a20
++#define mmDIG1_AFMT_AVI_INFO2                                                   0x4b20
++#define mmDIG2_AFMT_AVI_INFO2                                                   0x4c20
++#define mmDIG3_AFMT_AVI_INFO2                                                   0x4d20
++#define mmDIG4_AFMT_AVI_INFO2                                                   0x4e20
++#define mmDIG5_AFMT_AVI_INFO2                                                   0x4f20
++#define mmDIG6_AFMT_AVI_INFO2                                                   0x5420
++#define mmAFMT_AVI_INFO3                                                        0x4a21
++#define mmDIG0_AFMT_AVI_INFO3                                                   0x4a21
++#define mmDIG1_AFMT_AVI_INFO3                                                   0x4b21
++#define mmDIG2_AFMT_AVI_INFO3                                                   0x4c21
++#define mmDIG3_AFMT_AVI_INFO3                                                   0x4d21
++#define mmDIG4_AFMT_AVI_INFO3                                                   0x4e21
++#define mmDIG5_AFMT_AVI_INFO3                                                   0x4f21
++#define mmDIG6_AFMT_AVI_INFO3                                                   0x5421
++#define mmAFMT_MPEG_INFO0                                                       0x4a22
++#define mmDIG0_AFMT_MPEG_INFO0                                                  0x4a22
++#define mmDIG1_AFMT_MPEG_INFO0                                                  0x4b22
++#define mmDIG2_AFMT_MPEG_INFO0                                                  0x4c22
++#define mmDIG3_AFMT_MPEG_INFO0                                                  0x4d22
++#define mmDIG4_AFMT_MPEG_INFO0                                                  0x4e22
++#define mmDIG5_AFMT_MPEG_INFO0                                                  0x4f22
++#define mmDIG6_AFMT_MPEG_INFO0                                                  0x5422
++#define mmAFMT_MPEG_INFO1                                                       0x4a23
++#define mmDIG0_AFMT_MPEG_INFO1                                                  0x4a23
++#define mmDIG1_AFMT_MPEG_INFO1                                                  0x4b23
++#define mmDIG2_AFMT_MPEG_INFO1                                                  0x4c23
++#define mmDIG3_AFMT_MPEG_INFO1                                                  0x4d23
++#define mmDIG4_AFMT_MPEG_INFO1                                                  0x4e23
++#define mmDIG5_AFMT_MPEG_INFO1                                                  0x4f23
++#define mmDIG6_AFMT_MPEG_INFO1                                                  0x5423
++#define mmAFMT_GENERIC_HDR                                                      0x4a24
++#define mmDIG0_AFMT_GENERIC_HDR                                                 0x4a24
++#define mmDIG1_AFMT_GENERIC_HDR                                                 0x4b24
++#define mmDIG2_AFMT_GENERIC_HDR                                                 0x4c24
++#define mmDIG3_AFMT_GENERIC_HDR                                                 0x4d24
++#define mmDIG4_AFMT_GENERIC_HDR                                                 0x4e24
++#define mmDIG5_AFMT_GENERIC_HDR                                                 0x4f24
++#define mmDIG6_AFMT_GENERIC_HDR                                                 0x5424
++#define mmAFMT_GENERIC_0                                                        0x4a25
++#define mmDIG0_AFMT_GENERIC_0                                                   0x4a25
++#define mmDIG1_AFMT_GENERIC_0                                                   0x4b25
++#define mmDIG2_AFMT_GENERIC_0                                                   0x4c25
++#define mmDIG3_AFMT_GENERIC_0                                                   0x4d25
++#define mmDIG4_AFMT_GENERIC_0                                                   0x4e25
++#define mmDIG5_AFMT_GENERIC_0                                                   0x4f25
++#define mmDIG6_AFMT_GENERIC_0                                                   0x5425
++#define mmAFMT_GENERIC_1                                                        0x4a26
++#define mmDIG0_AFMT_GENERIC_1                                                   0x4a26
++#define mmDIG1_AFMT_GENERIC_1                                                   0x4b26
++#define mmDIG2_AFMT_GENERIC_1                                                   0x4c26
++#define mmDIG3_AFMT_GENERIC_1                                                   0x4d26
++#define mmDIG4_AFMT_GENERIC_1                                                   0x4e26
++#define mmDIG5_AFMT_GENERIC_1                                                   0x4f26
++#define mmDIG6_AFMT_GENERIC_1                                                   0x5426
++#define mmAFMT_GENERIC_2                                                        0x4a27
++#define mmDIG0_AFMT_GENERIC_2                                                   0x4a27
++#define mmDIG1_AFMT_GENERIC_2                                                   0x4b27
++#define mmDIG2_AFMT_GENERIC_2                                                   0x4c27
++#define mmDIG3_AFMT_GENERIC_2                                                   0x4d27
++#define mmDIG4_AFMT_GENERIC_2                                                   0x4e27
++#define mmDIG5_AFMT_GENERIC_2                                                   0x4f27
++#define mmDIG6_AFMT_GENERIC_2                                                   0x5427
++#define mmAFMT_GENERIC_3                                                        0x4a28
++#define mmDIG0_AFMT_GENERIC_3                                                   0x4a28
++#define mmDIG1_AFMT_GENERIC_3                                                   0x4b28
++#define mmDIG2_AFMT_GENERIC_3                                                   0x4c28
++#define mmDIG3_AFMT_GENERIC_3                                                   0x4d28
++#define mmDIG4_AFMT_GENERIC_3                                                   0x4e28
++#define mmDIG5_AFMT_GENERIC_3                                                   0x4f28
++#define mmDIG6_AFMT_GENERIC_3                                                   0x5428
++#define mmAFMT_GENERIC_4                                                        0x4a29
++#define mmDIG0_AFMT_GENERIC_4                                                   0x4a29
++#define mmDIG1_AFMT_GENERIC_4                                                   0x4b29
++#define mmDIG2_AFMT_GENERIC_4                                                   0x4c29
++#define mmDIG3_AFMT_GENERIC_4                                                   0x4d29
++#define mmDIG4_AFMT_GENERIC_4                                                   0x4e29
++#define mmDIG5_AFMT_GENERIC_4                                                   0x4f29
++#define mmDIG6_AFMT_GENERIC_4                                                   0x5429
++#define mmAFMT_GENERIC_5                                                        0x4a2a
++#define mmDIG0_AFMT_GENERIC_5                                                   0x4a2a
++#define mmDIG1_AFMT_GENERIC_5                                                   0x4b2a
++#define mmDIG2_AFMT_GENERIC_5                                                   0x4c2a
++#define mmDIG3_AFMT_GENERIC_5                                                   0x4d2a
++#define mmDIG4_AFMT_GENERIC_5                                                   0x4e2a
++#define mmDIG5_AFMT_GENERIC_5                                                   0x4f2a
++#define mmDIG6_AFMT_GENERIC_5                                                   0x542a
++#define mmAFMT_GENERIC_6                                                        0x4a2b
++#define mmDIG0_AFMT_GENERIC_6                                                   0x4a2b
++#define mmDIG1_AFMT_GENERIC_6                                                   0x4b2b
++#define mmDIG2_AFMT_GENERIC_6                                                   0x4c2b
++#define mmDIG3_AFMT_GENERIC_6                                                   0x4d2b
++#define mmDIG4_AFMT_GENERIC_6                                                   0x4e2b
++#define mmDIG5_AFMT_GENERIC_6                                                   0x4f2b
++#define mmDIG6_AFMT_GENERIC_6                                                   0x542b
++#define mmAFMT_GENERIC_7                                                        0x4a2c
++#define mmDIG0_AFMT_GENERIC_7                                                   0x4a2c
++#define mmDIG1_AFMT_GENERIC_7                                                   0x4b2c
++#define mmDIG2_AFMT_GENERIC_7                                                   0x4c2c
++#define mmDIG3_AFMT_GENERIC_7                                                   0x4d2c
++#define mmDIG4_AFMT_GENERIC_7                                                   0x4e2c
++#define mmDIG5_AFMT_GENERIC_7                                                   0x4f2c
++#define mmDIG6_AFMT_GENERIC_7                                                   0x542c
++#define mmHDMI_GENERIC_PACKET_CONTROL1                                          0x4a2d
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                     0x4a2d
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                     0x4b2d
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                     0x4c2d
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                     0x4d2d
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                     0x4e2d
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                     0x4f2d
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                     0x542d
++#define mmHDMI_ACR_32_0                                                         0x4a2e
++#define mmDIG0_HDMI_ACR_32_0                                                    0x4a2e
++#define mmDIG1_HDMI_ACR_32_0                                                    0x4b2e
++#define mmDIG2_HDMI_ACR_32_0                                                    0x4c2e
++#define mmDIG3_HDMI_ACR_32_0                                                    0x4d2e
++#define mmDIG4_HDMI_ACR_32_0                                                    0x4e2e
++#define mmDIG5_HDMI_ACR_32_0                                                    0x4f2e
++#define mmDIG6_HDMI_ACR_32_0                                                    0x542e
++#define mmHDMI_ACR_32_1                                                         0x4a2f
++#define mmDIG0_HDMI_ACR_32_1                                                    0x4a2f
++#define mmDIG1_HDMI_ACR_32_1                                                    0x4b2f
++#define mmDIG2_HDMI_ACR_32_1                                                    0x4c2f
++#define mmDIG3_HDMI_ACR_32_1                                                    0x4d2f
++#define mmDIG4_HDMI_ACR_32_1                                                    0x4e2f
++#define mmDIG5_HDMI_ACR_32_1                                                    0x4f2f
++#define mmDIG6_HDMI_ACR_32_1                                                    0x542f
++#define mmHDMI_ACR_44_0                                                         0x4a30
++#define mmDIG0_HDMI_ACR_44_0                                                    0x4a30
++#define mmDIG1_HDMI_ACR_44_0                                                    0x4b30
++#define mmDIG2_HDMI_ACR_44_0                                                    0x4c30
++#define mmDIG3_HDMI_ACR_44_0                                                    0x4d30
++#define mmDIG4_HDMI_ACR_44_0                                                    0x4e30
++#define mmDIG5_HDMI_ACR_44_0                                                    0x4f30
++#define mmDIG6_HDMI_ACR_44_0                                                    0x5430
++#define mmHDMI_ACR_44_1                                                         0x4a31
++#define mmDIG0_HDMI_ACR_44_1                                                    0x4a31
++#define mmDIG1_HDMI_ACR_44_1                                                    0x4b31
++#define mmDIG2_HDMI_ACR_44_1                                                    0x4c31
++#define mmDIG3_HDMI_ACR_44_1                                                    0x4d31
++#define mmDIG4_HDMI_ACR_44_1                                                    0x4e31
++#define mmDIG5_HDMI_ACR_44_1                                                    0x4f31
++#define mmDIG6_HDMI_ACR_44_1                                                    0x5431
++#define mmHDMI_ACR_48_0                                                         0x4a32
++#define mmDIG0_HDMI_ACR_48_0                                                    0x4a32
++#define mmDIG1_HDMI_ACR_48_0                                                    0x4b32
++#define mmDIG2_HDMI_ACR_48_0                                                    0x4c32
++#define mmDIG3_HDMI_ACR_48_0                                                    0x4d32
++#define mmDIG4_HDMI_ACR_48_0                                                    0x4e32
++#define mmDIG5_HDMI_ACR_48_0                                                    0x4f32
++#define mmDIG6_HDMI_ACR_48_0                                                    0x5432
++#define mmHDMI_ACR_48_1                                                         0x4a33
++#define mmDIG0_HDMI_ACR_48_1                                                    0x4a33
++#define mmDIG1_HDMI_ACR_48_1                                                    0x4b33
++#define mmDIG2_HDMI_ACR_48_1                                                    0x4c33
++#define mmDIG3_HDMI_ACR_48_1                                                    0x4d33
++#define mmDIG4_HDMI_ACR_48_1                                                    0x4e33
++#define mmDIG5_HDMI_ACR_48_1                                                    0x4f33
++#define mmDIG6_HDMI_ACR_48_1                                                    0x5433
++#define mmHDMI_ACR_STATUS_0                                                     0x4a34
++#define mmDIG0_HDMI_ACR_STATUS_0                                                0x4a34
++#define mmDIG1_HDMI_ACR_STATUS_0                                                0x4b34
++#define mmDIG2_HDMI_ACR_STATUS_0                                                0x4c34
++#define mmDIG3_HDMI_ACR_STATUS_0                                                0x4d34
++#define mmDIG4_HDMI_ACR_STATUS_0                                                0x4e34
++#define mmDIG5_HDMI_ACR_STATUS_0                                                0x4f34
++#define mmDIG6_HDMI_ACR_STATUS_0                                                0x5434
++#define mmHDMI_ACR_STATUS_1                                                     0x4a35
++#define mmDIG0_HDMI_ACR_STATUS_1                                                0x4a35
++#define mmDIG1_HDMI_ACR_STATUS_1                                                0x4b35
++#define mmDIG2_HDMI_ACR_STATUS_1                                                0x4c35
++#define mmDIG3_HDMI_ACR_STATUS_1                                                0x4d35
++#define mmDIG4_HDMI_ACR_STATUS_1                                                0x4e35
++#define mmDIG5_HDMI_ACR_STATUS_1                                                0x4f35
++#define mmDIG6_HDMI_ACR_STATUS_1                                                0x5435
++#define mmAFMT_AUDIO_INFO0                                                      0x4a36
++#define mmDIG0_AFMT_AUDIO_INFO0                                                 0x4a36
++#define mmDIG1_AFMT_AUDIO_INFO0                                                 0x4b36
++#define mmDIG2_AFMT_AUDIO_INFO0                                                 0x4c36
++#define mmDIG3_AFMT_AUDIO_INFO0                                                 0x4d36
++#define mmDIG4_AFMT_AUDIO_INFO0                                                 0x4e36
++#define mmDIG5_AFMT_AUDIO_INFO0                                                 0x4f36
++#define mmDIG6_AFMT_AUDIO_INFO0                                                 0x5436
++#define mmAFMT_AUDIO_INFO1                                                      0x4a37
++#define mmDIG0_AFMT_AUDIO_INFO1                                                 0x4a37
++#define mmDIG1_AFMT_AUDIO_INFO1                                                 0x4b37
++#define mmDIG2_AFMT_AUDIO_INFO1                                                 0x4c37
++#define mmDIG3_AFMT_AUDIO_INFO1                                                 0x4d37
++#define mmDIG4_AFMT_AUDIO_INFO1                                                 0x4e37
++#define mmDIG5_AFMT_AUDIO_INFO1                                                 0x4f37
++#define mmDIG6_AFMT_AUDIO_INFO1                                                 0x5437
++#define mmAFMT_60958_0                                                          0x4a38
++#define mmDIG0_AFMT_60958_0                                                     0x4a38
++#define mmDIG1_AFMT_60958_0                                                     0x4b38
++#define mmDIG2_AFMT_60958_0                                                     0x4c38
++#define mmDIG3_AFMT_60958_0                                                     0x4d38
++#define mmDIG4_AFMT_60958_0                                                     0x4e38
++#define mmDIG5_AFMT_60958_0                                                     0x4f38
++#define mmDIG6_AFMT_60958_0                                                     0x5438
++#define mmAFMT_60958_1                                                          0x4a39
++#define mmDIG0_AFMT_60958_1                                                     0x4a39
++#define mmDIG1_AFMT_60958_1                                                     0x4b39
++#define mmDIG2_AFMT_60958_1                                                     0x4c39
++#define mmDIG3_AFMT_60958_1                                                     0x4d39
++#define mmDIG4_AFMT_60958_1                                                     0x4e39
++#define mmDIG5_AFMT_60958_1                                                     0x4f39
++#define mmDIG6_AFMT_60958_1                                                     0x5439
++#define mmAFMT_AUDIO_CRC_CONTROL                                                0x4a3a
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                           0x4a3a
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                           0x4b3a
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                           0x4c3a
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                           0x4d3a
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                           0x4e3a
++#define mmDIG5_AFMT_AUDIO_CRC_CONTROL                                           0x4f3a
++#define mmDIG6_AFMT_AUDIO_CRC_CONTROL                                           0x543a
++#define mmAFMT_RAMP_CONTROL0                                                    0x4a3b
++#define mmDIG0_AFMT_RAMP_CONTROL0                                               0x4a3b
++#define mmDIG1_AFMT_RAMP_CONTROL0                                               0x4b3b
++#define mmDIG2_AFMT_RAMP_CONTROL0                                               0x4c3b
++#define mmDIG3_AFMT_RAMP_CONTROL0                                               0x4d3b
++#define mmDIG4_AFMT_RAMP_CONTROL0                                               0x4e3b
++#define mmDIG5_AFMT_RAMP_CONTROL0                                               0x4f3b
++#define mmDIG6_AFMT_RAMP_CONTROL0                                               0x543b
++#define mmAFMT_RAMP_CONTROL1                                                    0x4a3c
++#define mmDIG0_AFMT_RAMP_CONTROL1                                               0x4a3c
++#define mmDIG1_AFMT_RAMP_CONTROL1                                               0x4b3c
++#define mmDIG2_AFMT_RAMP_CONTROL1                                               0x4c3c
++#define mmDIG3_AFMT_RAMP_CONTROL1                                               0x4d3c
++#define mmDIG4_AFMT_RAMP_CONTROL1                                               0x4e3c
++#define mmDIG5_AFMT_RAMP_CONTROL1                                               0x4f3c
++#define mmDIG6_AFMT_RAMP_CONTROL1                                               0x543c
++#define mmAFMT_RAMP_CONTROL2                                                    0x4a3d
++#define mmDIG0_AFMT_RAMP_CONTROL2                                               0x4a3d
++#define mmDIG1_AFMT_RAMP_CONTROL2                                               0x4b3d
++#define mmDIG2_AFMT_RAMP_CONTROL2                                               0x4c3d
++#define mmDIG3_AFMT_RAMP_CONTROL2                                               0x4d3d
++#define mmDIG4_AFMT_RAMP_CONTROL2                                               0x4e3d
++#define mmDIG5_AFMT_RAMP_CONTROL2                                               0x4f3d
++#define mmDIG6_AFMT_RAMP_CONTROL2                                               0x543d
++#define mmAFMT_RAMP_CONTROL3                                                    0x4a3e
++#define mmDIG0_AFMT_RAMP_CONTROL3                                               0x4a3e
++#define mmDIG1_AFMT_RAMP_CONTROL3                                               0x4b3e
++#define mmDIG2_AFMT_RAMP_CONTROL3                                               0x4c3e
++#define mmDIG3_AFMT_RAMP_CONTROL3                                               0x4d3e
++#define mmDIG4_AFMT_RAMP_CONTROL3                                               0x4e3e
++#define mmDIG5_AFMT_RAMP_CONTROL3                                               0x4f3e
++#define mmDIG6_AFMT_RAMP_CONTROL3                                               0x543e
++#define mmAFMT_60958_2                                                          0x4a3f
++#define mmDIG0_AFMT_60958_2                                                     0x4a3f
++#define mmDIG1_AFMT_60958_2                                                     0x4b3f
++#define mmDIG2_AFMT_60958_2                                                     0x4c3f
++#define mmDIG3_AFMT_60958_2                                                     0x4d3f
++#define mmDIG4_AFMT_60958_2                                                     0x4e3f
++#define mmDIG5_AFMT_60958_2                                                     0x4f3f
++#define mmDIG6_AFMT_60958_2                                                     0x543f
++#define mmAFMT_AUDIO_CRC_RESULT                                                 0x4a40
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT                                            0x4a40
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT                                            0x4b40
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT                                            0x4c40
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT                                            0x4d40
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT                                            0x4e40
++#define mmDIG5_AFMT_AUDIO_CRC_RESULT                                            0x4f40
++#define mmDIG6_AFMT_AUDIO_CRC_RESULT                                            0x5440
++#define mmAFMT_STATUS                                                           0x4a41
++#define mmDIG0_AFMT_STATUS                                                      0x4a41
++#define mmDIG1_AFMT_STATUS                                                      0x4b41
++#define mmDIG2_AFMT_STATUS                                                      0x4c41
++#define mmDIG3_AFMT_STATUS                                                      0x4d41
++#define mmDIG4_AFMT_STATUS                                                      0x4e41
++#define mmDIG5_AFMT_STATUS                                                      0x4f41
++#define mmDIG6_AFMT_STATUS                                                      0x5441
++#define mmAFMT_AUDIO_PACKET_CONTROL                                             0x4a42
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                        0x4a42
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                        0x4b42
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                        0x4c42
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                        0x4d42
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                        0x4e42
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                        0x4f42
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                        0x5442
++#define mmAFMT_VBI_PACKET_CONTROL                                               0x4a43
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL                                          0x4a43
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL                                          0x4b43
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL                                          0x4c43
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL                                          0x4d43
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL                                          0x4e43
++#define mmDIG5_AFMT_VBI_PACKET_CONTROL                                          0x4f43
++#define mmDIG6_AFMT_VBI_PACKET_CONTROL                                          0x5443
++#define mmAFMT_INFOFRAME_CONTROL0                                               0x4a44
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0                                          0x4a44
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0                                          0x4b44
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0                                          0x4c44
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0                                          0x4d44
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0                                          0x4e44
++#define mmDIG5_AFMT_INFOFRAME_CONTROL0                                          0x4f44
++#define mmDIG6_AFMT_INFOFRAME_CONTROL0                                          0x5444
++#define mmAFMT_AUDIO_SRC_CONTROL                                                0x4a45
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                           0x4a45
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                           0x4b45
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                           0x4c45
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                           0x4d45
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                           0x4e45
++#define mmDIG5_AFMT_AUDIO_SRC_CONTROL                                           0x4f45
++#define mmDIG6_AFMT_AUDIO_SRC_CONTROL                                           0x5445
++#define mmAFMT_AUDIO_DBG_DTO_CNTL                                               0x4a46
++#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4a46
++#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4b46
++#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4c46
++#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4d46
++#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4e46
++#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4f46
++#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5446
++#define mmDIG_BE_CNTL                                                           0x4a47
++#define mmDIG0_DIG_BE_CNTL                                                      0x4a47
++#define mmDIG1_DIG_BE_CNTL                                                      0x4b47
++#define mmDIG2_DIG_BE_CNTL                                                      0x4c47
++#define mmDIG3_DIG_BE_CNTL                                                      0x4d47
++#define mmDIG4_DIG_BE_CNTL                                                      0x4e47
++#define mmDIG5_DIG_BE_CNTL                                                      0x4f47
++#define mmDIG6_DIG_BE_CNTL                                                      0x5447
++#define mmDIG_BE_EN_CNTL                                                        0x4a48
++#define mmDIG0_DIG_BE_EN_CNTL                                                   0x4a48
++#define mmDIG1_DIG_BE_EN_CNTL                                                   0x4b48
++#define mmDIG2_DIG_BE_EN_CNTL                                                   0x4c48
++#define mmDIG3_DIG_BE_EN_CNTL                                                   0x4d48
++#define mmDIG4_DIG_BE_EN_CNTL                                                   0x4e48
++#define mmDIG5_DIG_BE_EN_CNTL                                                   0x4f48
++#define mmDIG6_DIG_BE_EN_CNTL                                                   0x5448
++#define mmTMDS_CNTL                                                             0x4a6b
++#define mmDIG0_TMDS_CNTL                                                        0x4a6b
++#define mmDIG1_TMDS_CNTL                                                        0x4b6b
++#define mmDIG2_TMDS_CNTL                                                        0x4c6b
++#define mmDIG3_TMDS_CNTL                                                        0x4d6b
++#define mmDIG4_TMDS_CNTL                                                        0x4e6b
++#define mmDIG5_TMDS_CNTL                                                        0x4f6b
++#define mmDIG6_TMDS_CNTL                                                        0x546b
++#define mmTMDS_CONTROL_CHAR                                                     0x4a6c
++#define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
++#define mmDIG1_TMDS_CONTROL_CHAR                                                0x4b6c
++#define mmDIG2_TMDS_CONTROL_CHAR                                                0x4c6c
++#define mmDIG3_TMDS_CONTROL_CHAR                                                0x4d6c
++#define mmDIG4_TMDS_CONTROL_CHAR                                                0x4e6c
++#define mmDIG5_TMDS_CONTROL_CHAR                                                0x4f6c
++#define mmDIG6_TMDS_CONTROL_CHAR                                                0x546c
++#define mmTMDS_CONTROL0_FEEDBACK                                                0x4a6d
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                           0x4a6d
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                           0x4b6d
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                           0x4c6d
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                           0x4d6d
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK                                           0x4e6d
++#define mmDIG5_TMDS_CONTROL0_FEEDBACK                                           0x4f6d
++#define mmDIG6_TMDS_CONTROL0_FEEDBACK                                           0x546d
++#define mmTMDS_STEREOSYNC_CTL_SEL                                               0x4a6e
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                          0x4a6e
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                          0x4b6e
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                          0x4c6e
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                          0x4d6e
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                          0x4e6e
++#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                          0x4f6e
++#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                          0x546e
++#define mmTMDS_SYNC_CHAR_PATTERN_0_1                                            0x4a6f
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4a6f
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4b6f
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4c6f
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4d6f
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4e6f
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4f6f
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x546f
++#define mmTMDS_SYNC_CHAR_PATTERN_2_3                                            0x4a70
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4a70
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4b70
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4c70
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4d70
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4e70
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4f70
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5470
++#define mmTMDS_DEBUG                                                            0x4a71
++#define mmDIG0_TMDS_DEBUG                                                       0x4a71
++#define mmDIG1_TMDS_DEBUG                                                       0x4b71
++#define mmDIG2_TMDS_DEBUG                                                       0x4c71
++#define mmDIG3_TMDS_DEBUG                                                       0x4d71
++#define mmDIG4_TMDS_DEBUG                                                       0x4e71
++#define mmDIG5_TMDS_DEBUG                                                       0x4f71
++#define mmDIG6_TMDS_DEBUG                                                       0x5471
++#define mmTMDS_CTL_BITS                                                         0x4a72
++#define mmDIG0_TMDS_CTL_BITS                                                    0x4a72
++#define mmDIG1_TMDS_CTL_BITS                                                    0x4b72
++#define mmDIG2_TMDS_CTL_BITS                                                    0x4c72
++#define mmDIG3_TMDS_CTL_BITS                                                    0x4d72
++#define mmDIG4_TMDS_CTL_BITS                                                    0x4e72
++#define mmDIG5_TMDS_CTL_BITS                                                    0x4f72
++#define mmDIG6_TMDS_CTL_BITS                                                    0x5472
++#define mmTMDS_DCBALANCER_CONTROL                                               0x4a73
++#define mmDIG0_TMDS_DCBALANCER_CONTROL                                          0x4a73
++#define mmDIG1_TMDS_DCBALANCER_CONTROL                                          0x4b73
++#define mmDIG2_TMDS_DCBALANCER_CONTROL                                          0x4c73
++#define mmDIG3_TMDS_DCBALANCER_CONTROL                                          0x4d73
++#define mmDIG4_TMDS_DCBALANCER_CONTROL                                          0x4e73
++#define mmDIG5_TMDS_DCBALANCER_CONTROL                                          0x4f73
++#define mmDIG6_TMDS_DCBALANCER_CONTROL                                          0x5473
++#define mmTMDS_CTL0_1_GEN_CNTL                                                  0x4a75
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                             0x4a75
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                             0x4b75
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                             0x4c75
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                             0x4d75
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                             0x4e75
++#define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                             0x4f75
++#define mmDIG6_TMDS_CTL0_1_GEN_CNTL                                             0x5475
++#define mmTMDS_CTL2_3_GEN_CNTL                                                  0x4a76
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                             0x4a76
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                             0x4b76
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                             0x4c76
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                             0x4d76
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                             0x4e76
++#define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                             0x4f76
++#define mmDIG6_TMDS_CTL2_3_GEN_CNTL                                             0x5476
++#define ixTMDS_DEBUG1                                                           0x1
++#define ixTMDS_DEBUG2                                                           0x2
++#define ixTMDS_DEBUG3                                                           0x3
++#define ixTMDS_DEBUG7                                                           0x4
++#define ixTMDS_DEBUG8                                                           0x5
++#define ixTMDS_DEBUG9                                                           0x6
++#define ixTMDS_DEBUG10                                                          0x7
++#define ixTMDS_DEBUG11                                                          0x8
++#define ixTMDS_DEBUG12                                                          0x9
++#define ixTMDS_DEBUG13                                                          0xa
++#define mmLVDS_DATA_CNTL                                                        0x4a78
++#define mmDIG0_LVDS_DATA_CNTL                                                   0x4a78
++#define mmDIG1_LVDS_DATA_CNTL                                                   0x4b78
++#define mmDIG2_LVDS_DATA_CNTL                                                   0x4c78
++#define mmDIG3_LVDS_DATA_CNTL                                                   0x4d78
++#define mmDIG4_LVDS_DATA_CNTL                                                   0x4e78
++#define mmDIG5_LVDS_DATA_CNTL                                                   0x4f78
++#define mmDIG6_LVDS_DATA_CNTL                                                   0x5478
++#define mmDIG_LANE_ENABLE                                                       0x4a79
++#define mmDIG0_DIG_LANE_ENABLE                                                  0x4a79
++#define mmDIG1_DIG_LANE_ENABLE                                                  0x4b79
++#define mmDIG2_DIG_LANE_ENABLE                                                  0x4c79
++#define mmDIG3_DIG_LANE_ENABLE                                                  0x4d79
++#define mmDIG4_DIG_LANE_ENABLE                                                  0x4e79
++#define mmDIG5_DIG_LANE_ENABLE                                                  0x4f79
++#define mmDIG6_DIG_LANE_ENABLE                                                  0x5479
++#define mmDIG_TEST_DEBUG_INDEX                                                  0x4a7a
++#define mmDIG0_DIG_TEST_DEBUG_INDEX                                             0x4a7a
++#define mmDIG1_DIG_TEST_DEBUG_INDEX                                             0x4b7a
++#define mmDIG2_DIG_TEST_DEBUG_INDEX                                             0x4c7a
++#define mmDIG3_DIG_TEST_DEBUG_INDEX                                             0x4d7a
++#define mmDIG4_DIG_TEST_DEBUG_INDEX                                             0x4e7a
++#define mmDIG5_DIG_TEST_DEBUG_INDEX                                             0x4f7a
++#define mmDIG6_DIG_TEST_DEBUG_INDEX                                             0x547a
++#define mmDIG_TEST_DEBUG_DATA                                                   0x4a7b
++#define mmDIG0_DIG_TEST_DEBUG_DATA                                              0x4a7b
++#define mmDIG1_DIG_TEST_DEBUG_DATA                                              0x4b7b
++#define mmDIG2_DIG_TEST_DEBUG_DATA                                              0x4c7b
++#define mmDIG3_DIG_TEST_DEBUG_DATA                                              0x4d7b
++#define mmDIG4_DIG_TEST_DEBUG_DATA                                              0x4e7b
++#define mmDIG5_DIG_TEST_DEBUG_DATA                                              0x4f7b
++#define mmDIG6_DIG_TEST_DEBUG_DATA                                              0x547b
++#define mmDIG_FE_TEST_DEBUG_INDEX                                               0x4a7c
++#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX                                          0x4a7c
++#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX                                          0x4b7c
++#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX                                          0x4c7c
++#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX                                          0x4d7c
++#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX                                          0x4e7c
++#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX                                          0x4f7c
++#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX                                          0x547c
++#define mmDIG_FE_TEST_DEBUG_DATA                                                0x4a7d
++#define mmDIG0_DIG_FE_TEST_DEBUG_DATA                                           0x4a7d
++#define mmDIG1_DIG_FE_TEST_DEBUG_DATA                                           0x4b7d
++#define mmDIG2_DIG_FE_TEST_DEBUG_DATA                                           0x4c7d
++#define mmDIG3_DIG_FE_TEST_DEBUG_DATA                                           0x4d7d
++#define mmDIG4_DIG_FE_TEST_DEBUG_DATA                                           0x4e7d
++#define mmDIG5_DIG_FE_TEST_DEBUG_DATA                                           0x4f7d
++#define mmDIG6_DIG_FE_TEST_DEBUG_DATA                                           0x547d
++#define mmDMCU_CTRL                                                             0x1600
++#define mmDMCU_STATUS                                                           0x1601
++#define mmDMCU_PC_START_ADDR                                                    0x1602
++#define mmDMCU_FW_START_ADDR                                                    0x1603
++#define mmDMCU_FW_END_ADDR                                                      0x1604
++#define mmDMCU_FW_ISR_START_ADDR                                                0x1605
++#define mmDMCU_FW_CS_HI                                                         0x1606
++#define mmDMCU_FW_CS_LO                                                         0x1607
++#define mmDMCU_RAM_ACCESS_CTRL                                                  0x1608
++#define mmDMCU_ERAM_WR_CTRL                                                     0x1609
++#define mmDMCU_ERAM_WR_DATA                                                     0x160a
++#define mmDMCU_ERAM_RD_CTRL                                                     0x160b
++#define mmDMCU_ERAM_RD_DATA                                                     0x160c
++#define mmDMCU_IRAM_WR_CTRL                                                     0x160d
++#define mmDMCU_IRAM_WR_DATA                                                     0x160e
++#define mmDMCU_IRAM_RD_CTRL                                                     0x160f
++#define mmDMCU_IRAM_RD_DATA                                                     0x1610
++#define mmDMCU_EVENT_TRIGGER                                                    0x1611
++#define mmDMCU_UC_INTERNAL_INT_STATUS                                           0x1612
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                         0x1613
++#define mmDMCU_INTERRUPT_STATUS                                                 0x1614
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                        0x1615
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                          0x1616
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                     0x1617
++#define mmDC_DMCU_SCRATCH                                                       0x1618
++#define mmDMCU_INT_CNT                                                          0x1619
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                        0x161a
++#define mmDMCU_UC_CLK_GATING_CNTL                                               0x161b
++#define mmMASTER_COMM_DATA_REG1                                                 0x161c
++#define mmMASTER_COMM_DATA_REG2                                                 0x161d
++#define mmMASTER_COMM_DATA_REG3                                                 0x161e
++#define mmMASTER_COMM_CMD_REG                                                   0x161f
++#define mmMASTER_COMM_CNTL_REG                                                  0x1620
++#define mmSLAVE_COMM_DATA_REG1                                                  0x1621
++#define mmSLAVE_COMM_DATA_REG2                                                  0x1622
++#define mmSLAVE_COMM_DATA_REG3                                                  0x1623
++#define mmSLAVE_COMM_CMD_REG                                                    0x1624
++#define mmSLAVE_COMM_CNTL_REG                                                   0x1625
++#define mmDMCU_TEST_DEBUG_INDEX                                                 0x1626
++#define mmDMCU_TEST_DEBUG_DATA                                                  0x1627
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                        0x1644
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                        0x1645
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                        0x1646
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                        0x1647
++#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                        0x1642
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                 0x1674
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                 0x1675
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                 0x1676
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                 0x1677
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                 0x1643
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                            0x1678
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                            0x1679
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                            0x167a
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                            0x167b
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                            0x1673
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1                               0x167c
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2                               0x167d
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3                               0x167e
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4                               0x167f
++#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5                               0x1633
++#define mmDMCU_DPRX_INTERRUPT_STATUS1                                           0x1634
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                    0x1635
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                               0x1636
++#define mmDP_LINK_CNTL                                                          0x4aa0
++#define mmDP0_DP_LINK_CNTL                                                      0x4aa0
++#define mmDP1_DP_LINK_CNTL                                                      0x4ba0
++#define mmDP2_DP_LINK_CNTL                                                      0x4ca0
++#define mmDP3_DP_LINK_CNTL                                                      0x4da0
++#define mmDP4_DP_LINK_CNTL                                                      0x4ea0
++#define mmDP5_DP_LINK_CNTL                                                      0x4fa0
++#define mmDP6_DP_LINK_CNTL                                                      0x54a0
++#define mmDP_PIXEL_FORMAT                                                       0x4aa1
++#define mmDP0_DP_PIXEL_FORMAT                                                   0x4aa1
++#define mmDP1_DP_PIXEL_FORMAT                                                   0x4ba1
++#define mmDP2_DP_PIXEL_FORMAT                                                   0x4ca1
++#define mmDP3_DP_PIXEL_FORMAT                                                   0x4da1
++#define mmDP4_DP_PIXEL_FORMAT                                                   0x4ea1
++#define mmDP5_DP_PIXEL_FORMAT                                                   0x4fa1
++#define mmDP6_DP_PIXEL_FORMAT                                                   0x54a1
++#define mmDP_MSA_COLORIMETRY                                                    0x4aa2
++#define mmDP0_DP_MSA_COLORIMETRY                                                0x4aa2
++#define mmDP1_DP_MSA_COLORIMETRY                                                0x4ba2
++#define mmDP2_DP_MSA_COLORIMETRY                                                0x4ca2
++#define mmDP3_DP_MSA_COLORIMETRY                                                0x4da2
++#define mmDP4_DP_MSA_COLORIMETRY                                                0x4ea2
++#define mmDP5_DP_MSA_COLORIMETRY                                                0x4fa2
++#define mmDP6_DP_MSA_COLORIMETRY                                                0x54a2
++#define mmDP_CONFIG                                                             0x4aa3
++#define mmDP0_DP_CONFIG                                                         0x4aa3
++#define mmDP1_DP_CONFIG                                                         0x4ba3
++#define mmDP2_DP_CONFIG                                                         0x4ca3
++#define mmDP3_DP_CONFIG                                                         0x4da3
++#define mmDP4_DP_CONFIG                                                         0x4ea3
++#define mmDP5_DP_CONFIG                                                         0x4fa3
++#define mmDP6_DP_CONFIG                                                         0x54a3
++#define mmDP_VID_STREAM_CNTL                                                    0x4aa4
++#define mmDP0_DP_VID_STREAM_CNTL                                                0x4aa4
++#define mmDP1_DP_VID_STREAM_CNTL                                                0x4ba4
++#define mmDP2_DP_VID_STREAM_CNTL                                                0x4ca4
++#define mmDP3_DP_VID_STREAM_CNTL                                                0x4da4
++#define mmDP4_DP_VID_STREAM_CNTL                                                0x4ea4
++#define mmDP5_DP_VID_STREAM_CNTL                                                0x4fa4
++#define mmDP6_DP_VID_STREAM_CNTL                                                0x54a4
++#define mmDP_STEER_FIFO                                                         0x4aa5
++#define mmDP0_DP_STEER_FIFO                                                     0x4aa5
++#define mmDP1_DP_STEER_FIFO                                                     0x4ba5
++#define mmDP2_DP_STEER_FIFO                                                     0x4ca5
++#define mmDP3_DP_STEER_FIFO                                                     0x4da5
++#define mmDP4_DP_STEER_FIFO                                                     0x4ea5
++#define mmDP5_DP_STEER_FIFO                                                     0x4fa5
++#define mmDP6_DP_STEER_FIFO                                                     0x54a5
++#define mmDP_MSA_MISC                                                           0x4aa6
++#define mmDP0_DP_MSA_MISC                                                       0x4aa6
++#define mmDP1_DP_MSA_MISC                                                       0x4ba6
++#define mmDP2_DP_MSA_MISC                                                       0x4ca6
++#define mmDP3_DP_MSA_MISC                                                       0x4da6
++#define mmDP4_DP_MSA_MISC                                                       0x4ea6
++#define mmDP5_DP_MSA_MISC                                                       0x4fa6
++#define mmDP6_DP_MSA_MISC                                                       0x54a6
++#define mmDP_VID_TIMING                                                         0x4aa8
++#define mmDP0_DP_VID_TIMING                                                     0x4aa8
++#define mmDP1_DP_VID_TIMING                                                     0x4ba8
++#define mmDP2_DP_VID_TIMING                                                     0x4ca8
++#define mmDP3_DP_VID_TIMING                                                     0x4da8
++#define mmDP4_DP_VID_TIMING                                                     0x4ea8
++#define mmDP5_DP_VID_TIMING                                                     0x4fa8
++#define mmDP6_DP_VID_TIMING                                                     0x54a8
++#define mmDP_VID_N                                                              0x4aa9
++#define mmDP0_DP_VID_N                                                          0x4aa9
++#define mmDP1_DP_VID_N                                                          0x4ba9
++#define mmDP2_DP_VID_N                                                          0x4ca9
++#define mmDP3_DP_VID_N                                                          0x4da9
++#define mmDP4_DP_VID_N                                                          0x4ea9
++#define mmDP5_DP_VID_N                                                          0x4fa9
++#define mmDP6_DP_VID_N                                                          0x54a9
++#define mmDP_VID_M                                                              0x4aaa
++#define mmDP0_DP_VID_M                                                          0x4aaa
++#define mmDP1_DP_VID_M                                                          0x4baa
++#define mmDP2_DP_VID_M                                                          0x4caa
++#define mmDP3_DP_VID_M                                                          0x4daa
++#define mmDP4_DP_VID_M                                                          0x4eaa
++#define mmDP5_DP_VID_M                                                          0x4faa
++#define mmDP6_DP_VID_M                                                          0x54aa
++#define mmDP_LINK_FRAMING_CNTL                                                  0x4aab
++#define mmDP0_DP_LINK_FRAMING_CNTL                                              0x4aab
++#define mmDP1_DP_LINK_FRAMING_CNTL                                              0x4bab
++#define mmDP2_DP_LINK_FRAMING_CNTL                                              0x4cab
++#define mmDP3_DP_LINK_FRAMING_CNTL                                              0x4dab
++#define mmDP4_DP_LINK_FRAMING_CNTL                                              0x4eab
++#define mmDP5_DP_LINK_FRAMING_CNTL                                              0x4fab
++#define mmDP6_DP_LINK_FRAMING_CNTL                                              0x54ab
++#define mmDP_HBR2_EYE_PATTERN                                                   0x4aac
++#define mmDP0_DP_HBR2_EYE_PATTERN                                               0x4aac
++#define mmDP1_DP_HBR2_EYE_PATTERN                                               0x4bac
++#define mmDP2_DP_HBR2_EYE_PATTERN                                               0x4cac
++#define mmDP3_DP_HBR2_EYE_PATTERN                                               0x4dac
++#define mmDP4_DP_HBR2_EYE_PATTERN                                               0x4eac
++#define mmDP5_DP_HBR2_EYE_PATTERN                                               0x4fac
++#define mmDP6_DP_HBR2_EYE_PATTERN                                               0x54ac
++#define mmDP_VID_MSA_VBID                                                       0x4aad
++#define mmDP0_DP_VID_MSA_VBID                                                   0x4aad
++#define mmDP1_DP_VID_MSA_VBID                                                   0x4bad
++#define mmDP2_DP_VID_MSA_VBID                                                   0x4cad
++#define mmDP3_DP_VID_MSA_VBID                                                   0x4dad
++#define mmDP4_DP_VID_MSA_VBID                                                   0x4ead
++#define mmDP5_DP_VID_MSA_VBID                                                   0x4fad
++#define mmDP6_DP_VID_MSA_VBID                                                   0x54ad
++#define mmDP_VID_INTERRUPT_CNTL                                                 0x4aae
++#define mmDP0_DP_VID_INTERRUPT_CNTL                                             0x4aae
++#define mmDP1_DP_VID_INTERRUPT_CNTL                                             0x4bae
++#define mmDP2_DP_VID_INTERRUPT_CNTL                                             0x4cae
++#define mmDP3_DP_VID_INTERRUPT_CNTL                                             0x4dae
++#define mmDP4_DP_VID_INTERRUPT_CNTL                                             0x4eae
++#define mmDP5_DP_VID_INTERRUPT_CNTL                                             0x4fae
++#define mmDP6_DP_VID_INTERRUPT_CNTL                                             0x54ae
++#define mmDP_DPHY_CNTL                                                          0x4aaf
++#define mmDP0_DP_DPHY_CNTL                                                      0x4aaf
++#define mmDP1_DP_DPHY_CNTL                                                      0x4baf
++#define mmDP2_DP_DPHY_CNTL                                                      0x4caf
++#define mmDP3_DP_DPHY_CNTL                                                      0x4daf
++#define mmDP4_DP_DPHY_CNTL                                                      0x4eaf
++#define mmDP5_DP_DPHY_CNTL                                                      0x4faf
++#define mmDP6_DP_DPHY_CNTL                                                      0x54af
++#define mmDP_DPHY_TRAINING_PATTERN_SEL                                          0x4ab0
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4ab0
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4bb0
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4cb0
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4db0
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4eb0
++#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4fb0
++#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                      0x54b0
++#define mmDP_DPHY_SYM0                                                          0x4ab1
++#define mmDP0_DP_DPHY_SYM0                                                      0x4ab1
++#define mmDP1_DP_DPHY_SYM0                                                      0x4bb1
++#define mmDP2_DP_DPHY_SYM0                                                      0x4cb1
++#define mmDP3_DP_DPHY_SYM0                                                      0x4db1
++#define mmDP4_DP_DPHY_SYM0                                                      0x4eb1
++#define mmDP5_DP_DPHY_SYM0                                                      0x4fb1
++#define mmDP6_DP_DPHY_SYM0                                                      0x54b1
++#define mmDP_DPHY_SYM1                                                          0x4ab2
++#define mmDP0_DP_DPHY_SYM1                                                      0x4ab2
++#define mmDP1_DP_DPHY_SYM1                                                      0x4bb2
++#define mmDP2_DP_DPHY_SYM1                                                      0x4cb2
++#define mmDP3_DP_DPHY_SYM1                                                      0x4db2
++#define mmDP4_DP_DPHY_SYM1                                                      0x4eb2
++#define mmDP5_DP_DPHY_SYM1                                                      0x4fb2
++#define mmDP6_DP_DPHY_SYM1                                                      0x54b2
++#define mmDP_DPHY_SYM2                                                          0x4ab3
++#define mmDP0_DP_DPHY_SYM2                                                      0x4ab3
++#define mmDP1_DP_DPHY_SYM2                                                      0x4bb3
++#define mmDP2_DP_DPHY_SYM2                                                      0x4cb3
++#define mmDP3_DP_DPHY_SYM2                                                      0x4db3
++#define mmDP4_DP_DPHY_SYM2                                                      0x4eb3
++#define mmDP5_DP_DPHY_SYM2                                                      0x4fb3
++#define mmDP6_DP_DPHY_SYM2                                                      0x54b3
++#define mmDP_DPHY_8B10B_CNTL                                                    0x4ab4
++#define mmDP0_DP_DPHY_8B10B_CNTL                                                0x4ab4
++#define mmDP1_DP_DPHY_8B10B_CNTL                                                0x4bb4
++#define mmDP2_DP_DPHY_8B10B_CNTL                                                0x4cb4
++#define mmDP3_DP_DPHY_8B10B_CNTL                                                0x4db4
++#define mmDP4_DP_DPHY_8B10B_CNTL                                                0x4eb4
++#define mmDP5_DP_DPHY_8B10B_CNTL                                                0x4fb4
++#define mmDP6_DP_DPHY_8B10B_CNTL                                                0x54b4
++#define mmDP_DPHY_PRBS_CNTL                                                     0x4ab5
++#define mmDP0_DP_DPHY_PRBS_CNTL                                                 0x4ab5
++#define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
++#define mmDP2_DP_DPHY_PRBS_CNTL                                                 0x4cb5
++#define mmDP3_DP_DPHY_PRBS_CNTL                                                 0x4db5
++#define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
++#define mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4fb5
++#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5
++#define mmDP_DPHY_CRC_EN                                                        0x4ab7
++#define mmDP0_DP_DPHY_CRC_EN                                                    0x4ab7
++#define mmDP1_DP_DPHY_CRC_EN                                                    0x4bb7
++#define mmDP2_DP_DPHY_CRC_EN                                                    0x4cb7
++#define mmDP3_DP_DPHY_CRC_EN                                                    0x4db7
++#define mmDP4_DP_DPHY_CRC_EN                                                    0x4eb7
++#define mmDP5_DP_DPHY_CRC_EN                                                    0x4fb7
++#define mmDP6_DP_DPHY_CRC_EN                                                    0x54b7
++#define mmDP_DPHY_CRC_CNTL                                                      0x4ab8
++#define mmDP0_DP_DPHY_CRC_CNTL                                                  0x4ab8
++#define mmDP1_DP_DPHY_CRC_CNTL                                                  0x4bb8
++#define mmDP2_DP_DPHY_CRC_CNTL                                                  0x4cb8
++#define mmDP3_DP_DPHY_CRC_CNTL                                                  0x4db8
++#define mmDP4_DP_DPHY_CRC_CNTL                                                  0x4eb8
++#define mmDP5_DP_DPHY_CRC_CNTL                                                  0x4fb8
++#define mmDP6_DP_DPHY_CRC_CNTL                                                  0x54b8
++#define mmDP_DPHY_CRC_RESULT                                                    0x4ab9
++#define mmDP0_DP_DPHY_CRC_RESULT                                                0x4ab9
++#define mmDP1_DP_DPHY_CRC_RESULT                                                0x4bb9
++#define mmDP2_DP_DPHY_CRC_RESULT                                                0x4cb9
++#define mmDP3_DP_DPHY_CRC_RESULT                                                0x4db9
++#define mmDP4_DP_DPHY_CRC_RESULT                                                0x4eb9
++#define mmDP5_DP_DPHY_CRC_RESULT                                                0x4fb9
++#define mmDP6_DP_DPHY_CRC_RESULT                                                0x54b9
++#define mmDP_DPHY_CRC_MST_CNTL                                                  0x4aba
++#define mmDP0_DP_DPHY_CRC_MST_CNTL                                              0x4aba
++#define mmDP1_DP_DPHY_CRC_MST_CNTL                                              0x4bba
++#define mmDP2_DP_DPHY_CRC_MST_CNTL                                              0x4cba
++#define mmDP3_DP_DPHY_CRC_MST_CNTL                                              0x4dba
++#define mmDP4_DP_DPHY_CRC_MST_CNTL                                              0x4eba
++#define mmDP5_DP_DPHY_CRC_MST_CNTL                                              0x4fba
++#define mmDP6_DP_DPHY_CRC_MST_CNTL                                              0x54ba
++#define mmDP_DPHY_CRC_MST_STATUS                                                0x4abb
++#define mmDP0_DP_DPHY_CRC_MST_STATUS                                            0x4abb
++#define mmDP1_DP_DPHY_CRC_MST_STATUS                                            0x4bbb
++#define mmDP2_DP_DPHY_CRC_MST_STATUS                                            0x4cbb
++#define mmDP3_DP_DPHY_CRC_MST_STATUS                                            0x4dbb
++#define mmDP4_DP_DPHY_CRC_MST_STATUS                                            0x4ebb
++#define mmDP5_DP_DPHY_CRC_MST_STATUS                                            0x4fbb
++#define mmDP6_DP_DPHY_CRC_MST_STATUS                                            0x54bb
++#define mmDP_DPHY_FAST_TRAINING                                                 0x4abc
++#define mmDP0_DP_DPHY_FAST_TRAINING                                             0x4abc
++#define mmDP1_DP_DPHY_FAST_TRAINING                                             0x4bbc
++#define mmDP2_DP_DPHY_FAST_TRAINING                                             0x4cbc
++#define mmDP3_DP_DPHY_FAST_TRAINING                                             0x4dbc
++#define mmDP4_DP_DPHY_FAST_TRAINING                                             0x4ebc
++#define mmDP5_DP_DPHY_FAST_TRAINING                                             0x4fbc
++#define mmDP6_DP_DPHY_FAST_TRAINING                                             0x54bc
++#define mmDP_DPHY_FAST_TRAINING_STATUS                                          0x4abd
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                      0x4abd
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                      0x4bbd
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                      0x4cbd
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                      0x4dbd
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                      0x4ebd
++#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                      0x4fbd
++#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                      0x54bd
++#define mmDP_MSA_V_TIMING_OVERRIDE1                                             0x4abe
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                         0x4abe
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                         0x4bbe
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                         0x4cbe
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                         0x4dbe
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                         0x4ebe
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                         0x4fbe
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                         0x54be
++#define mmDP_MSA_V_TIMING_OVERRIDE2                                             0x4abf
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                         0x4abf
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                         0x4bbf
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                         0x4cbf
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                         0x4dbf
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                         0x4ebf
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                         0x4fbf
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                         0x54bf
++#define mmDP_SEC_CNTL                                                           0x4ac3
++#define mmDP0_DP_SEC_CNTL                                                       0x4ac3
++#define mmDP1_DP_SEC_CNTL                                                       0x4bc3
++#define mmDP2_DP_SEC_CNTL                                                       0x4cc3
++#define mmDP3_DP_SEC_CNTL                                                       0x4dc3
++#define mmDP4_DP_SEC_CNTL                                                       0x4ec3
++#define mmDP5_DP_SEC_CNTL                                                       0x4fc3
++#define mmDP6_DP_SEC_CNTL                                                       0x54c3
++#define mmDP_SEC_CNTL1                                                          0x4ac4
++#define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
++#define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
++#define mmDP2_DP_SEC_CNTL1                                                      0x4cc4
++#define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
++#define mmDP4_DP_SEC_CNTL1                                                      0x4ec4
++#define mmDP5_DP_SEC_CNTL1                                                      0x4fc4
++#define mmDP6_DP_SEC_CNTL1                                                      0x54c4
++#define mmDP_SEC_FRAMING1                                                       0x4ac5
++#define mmDP0_DP_SEC_FRAMING1                                                   0x4ac5
++#define mmDP1_DP_SEC_FRAMING1                                                   0x4bc5
++#define mmDP2_DP_SEC_FRAMING1                                                   0x4cc5
++#define mmDP3_DP_SEC_FRAMING1                                                   0x4dc5
++#define mmDP4_DP_SEC_FRAMING1                                                   0x4ec5
++#define mmDP5_DP_SEC_FRAMING1                                                   0x4fc5
++#define mmDP6_DP_SEC_FRAMING1                                                   0x54c5
++#define mmDP_SEC_FRAMING2                                                       0x4ac6
++#define mmDP0_DP_SEC_FRAMING2                                                   0x4ac6
++#define mmDP1_DP_SEC_FRAMING2                                                   0x4bc6
++#define mmDP2_DP_SEC_FRAMING2                                                   0x4cc6
++#define mmDP3_DP_SEC_FRAMING2                                                   0x4dc6
++#define mmDP4_DP_SEC_FRAMING2                                                   0x4ec6
++#define mmDP5_DP_SEC_FRAMING2                                                   0x4fc6
++#define mmDP6_DP_SEC_FRAMING2                                                   0x54c6
++#define mmDP_SEC_FRAMING3                                                       0x4ac7
++#define mmDP0_DP_SEC_FRAMING3                                                   0x4ac7
++#define mmDP1_DP_SEC_FRAMING3                                                   0x4bc7
++#define mmDP2_DP_SEC_FRAMING3                                                   0x4cc7
++#define mmDP3_DP_SEC_FRAMING3                                                   0x4dc7
++#define mmDP4_DP_SEC_FRAMING3                                                   0x4ec7
++#define mmDP5_DP_SEC_FRAMING3                                                   0x4fc7
++#define mmDP6_DP_SEC_FRAMING3                                                   0x54c7
++#define mmDP_SEC_FRAMING4                                                       0x4ac8
++#define mmDP0_DP_SEC_FRAMING4                                                   0x4ac8
++#define mmDP1_DP_SEC_FRAMING4                                                   0x4bc8
++#define mmDP2_DP_SEC_FRAMING4                                                   0x4cc8
++#define mmDP3_DP_SEC_FRAMING4                                                   0x4dc8
++#define mmDP4_DP_SEC_FRAMING4                                                   0x4ec8
++#define mmDP5_DP_SEC_FRAMING4                                                   0x4fc8
++#define mmDP6_DP_SEC_FRAMING4                                                   0x54c8
++#define mmDP_SEC_AUD_N                                                          0x4ac9
++#define mmDP0_DP_SEC_AUD_N                                                      0x4ac9
++#define mmDP1_DP_SEC_AUD_N                                                      0x4bc9
++#define mmDP2_DP_SEC_AUD_N                                                      0x4cc9
++#define mmDP3_DP_SEC_AUD_N                                                      0x4dc9
++#define mmDP4_DP_SEC_AUD_N                                                      0x4ec9
++#define mmDP5_DP_SEC_AUD_N                                                      0x4fc9
++#define mmDP6_DP_SEC_AUD_N                                                      0x54c9
++#define mmDP_SEC_AUD_N_READBACK                                                 0x4aca
++#define mmDP0_DP_SEC_AUD_N_READBACK                                             0x4aca
++#define mmDP1_DP_SEC_AUD_N_READBACK                                             0x4bca
++#define mmDP2_DP_SEC_AUD_N_READBACK                                             0x4cca
++#define mmDP3_DP_SEC_AUD_N_READBACK                                             0x4dca
++#define mmDP4_DP_SEC_AUD_N_READBACK                                             0x4eca
++#define mmDP5_DP_SEC_AUD_N_READBACK                                             0x4fca
++#define mmDP6_DP_SEC_AUD_N_READBACK                                             0x54ca
++#define mmDP_SEC_AUD_M                                                          0x4acb
++#define mmDP0_DP_SEC_AUD_M                                                      0x4acb
++#define mmDP1_DP_SEC_AUD_M                                                      0x4bcb
++#define mmDP2_DP_SEC_AUD_M                                                      0x4ccb
++#define mmDP3_DP_SEC_AUD_M                                                      0x4dcb
++#define mmDP4_DP_SEC_AUD_M                                                      0x4ecb
++#define mmDP5_DP_SEC_AUD_M                                                      0x4fcb
++#define mmDP6_DP_SEC_AUD_M                                                      0x54cb
++#define mmDP_SEC_AUD_M_READBACK                                                 0x4acc
++#define mmDP0_DP_SEC_AUD_M_READBACK                                             0x4acc
++#define mmDP1_DP_SEC_AUD_M_READBACK                                             0x4bcc
++#define mmDP2_DP_SEC_AUD_M_READBACK                                             0x4ccc
++#define mmDP3_DP_SEC_AUD_M_READBACK                                             0x4dcc
++#define mmDP4_DP_SEC_AUD_M_READBACK                                             0x4ecc
++#define mmDP5_DP_SEC_AUD_M_READBACK                                             0x4fcc
++#define mmDP6_DP_SEC_AUD_M_READBACK                                             0x54cc
++#define mmDP_SEC_TIMESTAMP                                                      0x4acd
++#define mmDP0_DP_SEC_TIMESTAMP                                                  0x4acd
++#define mmDP1_DP_SEC_TIMESTAMP                                                  0x4bcd
++#define mmDP2_DP_SEC_TIMESTAMP                                                  0x4ccd
++#define mmDP3_DP_SEC_TIMESTAMP                                                  0x4dcd
++#define mmDP4_DP_SEC_TIMESTAMP                                                  0x4ecd
++#define mmDP5_DP_SEC_TIMESTAMP                                                  0x4fcd
++#define mmDP6_DP_SEC_TIMESTAMP                                                  0x54cd
++#define mmDP_SEC_PACKET_CNTL                                                    0x4ace
++#define mmDP0_DP_SEC_PACKET_CNTL                                                0x4ace
++#define mmDP1_DP_SEC_PACKET_CNTL                                                0x4bce
++#define mmDP2_DP_SEC_PACKET_CNTL                                                0x4cce
++#define mmDP3_DP_SEC_PACKET_CNTL                                                0x4dce
++#define mmDP4_DP_SEC_PACKET_CNTL                                                0x4ece
++#define mmDP5_DP_SEC_PACKET_CNTL                                                0x4fce
++#define mmDP6_DP_SEC_PACKET_CNTL                                                0x54ce
++#define mmDP_MSE_RATE_CNTL                                                      0x4acf
++#define mmDP0_DP_MSE_RATE_CNTL                                                  0x4acf
++#define mmDP1_DP_MSE_RATE_CNTL                                                  0x4bcf
++#define mmDP2_DP_MSE_RATE_CNTL                                                  0x4ccf
++#define mmDP3_DP_MSE_RATE_CNTL                                                  0x4dcf
++#define mmDP4_DP_MSE_RATE_CNTL                                                  0x4ecf
++#define mmDP5_DP_MSE_RATE_CNTL                                                  0x4fcf
++#define mmDP6_DP_MSE_RATE_CNTL                                                  0x54cf
++#define mmDP_MSE_RATE_UPDATE                                                    0x4ad1
++#define mmDP0_DP_MSE_RATE_UPDATE                                                0x4ad1
++#define mmDP1_DP_MSE_RATE_UPDATE                                                0x4bd1
++#define mmDP2_DP_MSE_RATE_UPDATE                                                0x4cd1
++#define mmDP3_DP_MSE_RATE_UPDATE                                                0x4dd1
++#define mmDP4_DP_MSE_RATE_UPDATE                                                0x4ed1
++#define mmDP5_DP_MSE_RATE_UPDATE                                                0x4fd1
++#define mmDP6_DP_MSE_RATE_UPDATE                                                0x54d1
++#define mmDP_MSE_SAT0                                                           0x4ad2
++#define mmDP0_DP_MSE_SAT0                                                       0x4ad2
++#define mmDP1_DP_MSE_SAT0                                                       0x4bd2
++#define mmDP2_DP_MSE_SAT0                                                       0x4cd2
++#define mmDP3_DP_MSE_SAT0                                                       0x4dd2
++#define mmDP4_DP_MSE_SAT0                                                       0x4ed2
++#define mmDP5_DP_MSE_SAT0                                                       0x4fd2
++#define mmDP6_DP_MSE_SAT0                                                       0x54d2
++#define mmDP_MSE_SAT1                                                           0x4ad3
++#define mmDP0_DP_MSE_SAT1                                                       0x4ad3
++#define mmDP1_DP_MSE_SAT1                                                       0x4bd3
++#define mmDP2_DP_MSE_SAT1                                                       0x4cd3
++#define mmDP3_DP_MSE_SAT1                                                       0x4dd3
++#define mmDP4_DP_MSE_SAT1                                                       0x4ed3
++#define mmDP5_DP_MSE_SAT1                                                       0x4fd3
++#define mmDP6_DP_MSE_SAT1                                                       0x54d3
++#define mmDP_MSE_SAT2                                                           0x4ad4
++#define mmDP0_DP_MSE_SAT2                                                       0x4ad4
++#define mmDP1_DP_MSE_SAT2                                                       0x4bd4
++#define mmDP2_DP_MSE_SAT2                                                       0x4cd4
++#define mmDP3_DP_MSE_SAT2                                                       0x4dd4
++#define mmDP4_DP_MSE_SAT2                                                       0x4ed4
++#define mmDP5_DP_MSE_SAT2                                                       0x4fd4
++#define mmDP6_DP_MSE_SAT2                                                       0x54d4
++#define mmDP_MSE_SAT_UPDATE                                                     0x4ad5
++#define mmDP0_DP_MSE_SAT_UPDATE                                                 0x4ad5
++#define mmDP1_DP_MSE_SAT_UPDATE                                                 0x4bd5
++#define mmDP2_DP_MSE_SAT_UPDATE                                                 0x4cd5
++#define mmDP3_DP_MSE_SAT_UPDATE                                                 0x4dd5
++#define mmDP4_DP_MSE_SAT_UPDATE                                                 0x4ed5
++#define mmDP5_DP_MSE_SAT_UPDATE                                                 0x4fd5
++#define mmDP6_DP_MSE_SAT_UPDATE                                                 0x54d5
++#define mmDP_MSE_LINK_TIMING                                                    0x4ad6
++#define mmDP0_DP_MSE_LINK_TIMING                                                0x4ad6
++#define mmDP1_DP_MSE_LINK_TIMING                                                0x4bd6
++#define mmDP2_DP_MSE_LINK_TIMING                                                0x4cd6
++#define mmDP3_DP_MSE_LINK_TIMING                                                0x4dd6
++#define mmDP4_DP_MSE_LINK_TIMING                                                0x4ed6
++#define mmDP5_DP_MSE_LINK_TIMING                                                0x4fd6
++#define mmDP6_DP_MSE_LINK_TIMING                                                0x54d6
++#define mmDP_MSE_MISC_CNTL                                                      0x4ad7
++#define mmDP0_DP_MSE_MISC_CNTL                                                  0x4ad7
++#define mmDP1_DP_MSE_MISC_CNTL                                                  0x4bd7
++#define mmDP2_DP_MSE_MISC_CNTL                                                  0x4cd7
++#define mmDP3_DP_MSE_MISC_CNTL                                                  0x4dd7
++#define mmDP4_DP_MSE_MISC_CNTL                                                  0x4ed7
++#define mmDP5_DP_MSE_MISC_CNTL                                                  0x4fd7
++#define mmDP6_DP_MSE_MISC_CNTL                                                  0x54d7
++#define mmDP_TEST_DEBUG_INDEX                                                   0x4ad8
++#define mmDP0_DP_TEST_DEBUG_INDEX                                               0x4ad8
++#define mmDP1_DP_TEST_DEBUG_INDEX                                               0x4bd8
++#define mmDP2_DP_TEST_DEBUG_INDEX                                               0x4cd8
++#define mmDP3_DP_TEST_DEBUG_INDEX                                               0x4dd8
++#define mmDP4_DP_TEST_DEBUG_INDEX                                               0x4ed8
++#define mmDP5_DP_TEST_DEBUG_INDEX                                               0x4fd8
++#define mmDP6_DP_TEST_DEBUG_INDEX                                               0x54d8
++#define mmDP_TEST_DEBUG_DATA                                                    0x4ad9
++#define mmDP0_DP_TEST_DEBUG_DATA                                                0x4ad9
++#define mmDP1_DP_TEST_DEBUG_DATA                                                0x4bd9
++#define mmDP2_DP_TEST_DEBUG_DATA                                                0x4cd9
++#define mmDP3_DP_TEST_DEBUG_DATA                                                0x4dd9
++#define mmDP4_DP_TEST_DEBUG_DATA                                                0x4ed9
++#define mmDP5_DP_TEST_DEBUG_DATA                                                0x4fd9
++#define mmDP6_DP_TEST_DEBUG_DATA                                                0x54d9
++#define mmDP_FE_TEST_DEBUG_INDEX                                                0x4ada
++#define mmDP0_DP_FE_TEST_DEBUG_INDEX                                            0x4ada
++#define mmDP1_DP_FE_TEST_DEBUG_INDEX                                            0x4bda
++#define mmDP2_DP_FE_TEST_DEBUG_INDEX                                            0x4cda
++#define mmDP3_DP_FE_TEST_DEBUG_INDEX                                            0x4dda
++#define mmDP4_DP_FE_TEST_DEBUG_INDEX                                            0x4eda
++#define mmDP5_DP_FE_TEST_DEBUG_INDEX                                            0x4fda
++#define mmDP6_DP_FE_TEST_DEBUG_INDEX                                            0x54da
++#define mmDP_FE_TEST_DEBUG_DATA                                                 0x4adb
++#define mmDP0_DP_FE_TEST_DEBUG_DATA                                             0x4adb
++#define mmDP1_DP_FE_TEST_DEBUG_DATA                                             0x4bdb
++#define mmDP2_DP_FE_TEST_DEBUG_DATA                                             0x4cdb
++#define mmDP3_DP_FE_TEST_DEBUG_DATA                                             0x4ddb
++#define mmDP4_DP_FE_TEST_DEBUG_DATA                                             0x4edb
++#define mmDP5_DP_FE_TEST_DEBUG_DATA                                             0x4fdb
++#define mmDP6_DP_FE_TEST_DEBUG_DATA                                             0x54db
++#define mmAUX_CONTROL                                                           0x5c00
++#define mmDP_AUX0_AUX_CONTROL                                                   0x5c00
++#define mmDP_AUX1_AUX_CONTROL                                                   0x5c1c
++#define mmDP_AUX2_AUX_CONTROL                                                   0x5c38
++#define mmDP_AUX3_AUX_CONTROL                                                   0x5c54
++#define mmDP_AUX4_AUX_CONTROL                                                   0x5c70
++#define mmDP_AUX5_AUX_CONTROL                                                   0x5c8c
++#define mmAUX_SW_CONTROL                                                        0x5c01
++#define mmDP_AUX0_AUX_SW_CONTROL                                                0x5c01
++#define mmDP_AUX1_AUX_SW_CONTROL                                                0x5c1d
++#define mmDP_AUX2_AUX_SW_CONTROL                                                0x5c39
++#define mmDP_AUX3_AUX_SW_CONTROL                                                0x5c55
++#define mmDP_AUX4_AUX_SW_CONTROL                                                0x5c71
++#define mmDP_AUX5_AUX_SW_CONTROL                                                0x5c8d
++#define mmAUX_ARB_CONTROL                                                       0x5c02
++#define mmDP_AUX0_AUX_ARB_CONTROL                                               0x5c02
++#define mmDP_AUX1_AUX_ARB_CONTROL                                               0x5c1e
++#define mmDP_AUX2_AUX_ARB_CONTROL                                               0x5c3a
++#define mmDP_AUX3_AUX_ARB_CONTROL                                               0x5c56
++#define mmDP_AUX4_AUX_ARB_CONTROL                                               0x5c72
++#define mmDP_AUX5_AUX_ARB_CONTROL                                               0x5c8e
++#define mmAUX_INTERRUPT_CONTROL                                                 0x5c03
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                         0x5c03
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                         0x5c1f
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                         0x5c3b
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                         0x5c57
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                         0x5c73
++#define mmDP_AUX5_AUX_INTERRUPT_CONTROL                                         0x5c8f
++#define mmAUX_SW_STATUS                                                         0x5c04
++#define mmDP_AUX0_AUX_SW_STATUS                                                 0x5c04
++#define mmDP_AUX1_AUX_SW_STATUS                                                 0x5c20
++#define mmDP_AUX2_AUX_SW_STATUS                                                 0x5c3c
++#define mmDP_AUX3_AUX_SW_STATUS                                                 0x5c58
++#define mmDP_AUX4_AUX_SW_STATUS                                                 0x5c74
++#define mmDP_AUX5_AUX_SW_STATUS                                                 0x5c90
++#define mmAUX_LS_STATUS                                                         0x5c05
++#define mmDP_AUX0_AUX_LS_STATUS                                                 0x5c05
++#define mmDP_AUX1_AUX_LS_STATUS                                                 0x5c21
++#define mmDP_AUX2_AUX_LS_STATUS                                                 0x5c3d
++#define mmDP_AUX3_AUX_LS_STATUS                                                 0x5c59
++#define mmDP_AUX4_AUX_LS_STATUS                                                 0x5c75
++#define mmDP_AUX5_AUX_LS_STATUS                                                 0x5c91
++#define mmAUX_SW_DATA                                                           0x5c06
++#define mmDP_AUX0_AUX_SW_DATA                                                   0x5c06
++#define mmDP_AUX1_AUX_SW_DATA                                                   0x5c22
++#define mmDP_AUX2_AUX_SW_DATA                                                   0x5c3e
++#define mmDP_AUX3_AUX_SW_DATA                                                   0x5c5a
++#define mmDP_AUX4_AUX_SW_DATA                                                   0x5c76
++#define mmDP_AUX5_AUX_SW_DATA                                                   0x5c92
++#define mmAUX_LS_DATA                                                           0x5c07
++#define mmDP_AUX0_AUX_LS_DATA                                                   0x5c07
++#define mmDP_AUX1_AUX_LS_DATA                                                   0x5c23
++#define mmDP_AUX2_AUX_LS_DATA                                                   0x5c3f
++#define mmDP_AUX3_AUX_LS_DATA                                                   0x5c5b
++#define mmDP_AUX4_AUX_LS_DATA                                                   0x5c77
++#define mmDP_AUX5_AUX_LS_DATA                                                   0x5c93
++#define mmAUX_DPHY_TX_REF_CONTROL                                               0x5c08
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                       0x5c08
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                       0x5c24
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                       0x5c40
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                       0x5c5c
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                       0x5c78
++#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                       0x5c94
++#define mmAUX_DPHY_TX_CONTROL                                                   0x5c09
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                           0x5c09
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                           0x5c25
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                           0x5c41
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                           0x5c5d
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                           0x5c79
++#define mmDP_AUX5_AUX_DPHY_TX_CONTROL                                           0x5c95
++#define mmAUX_DPHY_RX_CONTROL0                                                  0x5c0a
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                          0x5c0a
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                          0x5c26
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                          0x5c42
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                          0x5c5e
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                          0x5c7a
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                          0x5c96
++#define mmAUX_DPHY_RX_CONTROL1                                                  0x5c0b
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                          0x5c0b
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                          0x5c27
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                          0x5c43
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                          0x5c5f
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                          0x5c7b
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                          0x5c97
++#define mmAUX_DPHY_TX_STATUS                                                    0x5c0c
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                            0x5c0c
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                            0x5c28
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                            0x5c44
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                            0x5c60
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS                                            0x5c7c
++#define mmDP_AUX5_AUX_DPHY_TX_STATUS                                            0x5c98
++#define mmAUX_DPHY_RX_STATUS                                                    0x5c0d
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                            0x5c0d
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                            0x5c29
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                            0x5c45
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                            0x5c61
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS                                            0x5c7d
++#define mmDP_AUX5_AUX_DPHY_RX_STATUS                                            0x5c99
++#define mmAUX_GTC_SYNC_CONTROL                                                  0x5c0e
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                          0x5c0e
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                          0x5c2a
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                          0x5c46
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                          0x5c62
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                          0x5c7e
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL                                          0x5c9a
++#define mmAUX_GTC_SYNC_ERROR_CONTROL                                            0x5c0f
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c0f
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c2b
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c47
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c63
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c7f
++#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c9b
++#define mmAUX_GTC_SYNC_CONTROLLER_STATUS                                        0x5c10
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c10
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c2c
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c48
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c64
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c80
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c9c
++#define mmAUX_GTC_SYNC_STATUS                                                   0x5c11
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                           0x5c11
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                           0x5c2d
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                           0x5c49
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                           0x5c65
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                           0x5c81
++#define mmDP_AUX5_AUX_GTC_SYNC_STATUS                                           0x5c9d
++#define mmAUX_GTC_SYNC_DATA                                                     0x5c12
++#define mmDP_AUX0_AUX_GTC_SYNC_DATA                                             0x5c12
++#define mmDP_AUX1_AUX_GTC_SYNC_DATA                                             0x5c2e
++#define mmDP_AUX2_AUX_GTC_SYNC_DATA                                             0x5c4a
++#define mmDP_AUX3_AUX_GTC_SYNC_DATA                                             0x5c66
++#define mmDP_AUX4_AUX_GTC_SYNC_DATA                                             0x5c82
++#define mmDP_AUX5_AUX_GTC_SYNC_DATA                                             0x5c9e
++#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                                    0x5c13
++#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c13
++#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c2f
++#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c4b
++#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c67
++#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c83
++#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c9f
++#define mmAUX_TEST_DEBUG_INDEX                                                  0x5c14
++#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX                                          0x5c14
++#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX                                          0x5c30
++#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX                                          0x5c4c
++#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX                                          0x5c68
++#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX                                          0x5c84
++#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX                                          0x5ca0
++#define mmAUX_TEST_DEBUG_DATA                                                   0x5c15
++#define mmDP_AUX0_AUX_TEST_DEBUG_DATA                                           0x5c15
++#define mmDP_AUX1_AUX_TEST_DEBUG_DATA                                           0x5c31
++#define mmDP_AUX2_AUX_TEST_DEBUG_DATA                                           0x5c4d
++#define mmDP_AUX3_AUX_TEST_DEBUG_DATA                                           0x5c69
++#define mmDP_AUX4_AUX_TEST_DEBUG_DATA                                           0x5c85
++#define mmDP_AUX5_AUX_TEST_DEBUG_DATA                                           0x5ca1
++#define ixDP_AUX_DEBUG_A                                                        0x10
++#define ixDP_AUX_DEBUG_B                                                        0x11
++#define ixDP_AUX_DEBUG_C                                                        0x12
++#define ixDP_AUX_DEBUG_D                                                        0x13
++#define ixDP_AUX_DEBUG_E                                                        0x14
++#define ixDP_AUX_DEBUG_F                                                        0x15
++#define ixDP_AUX_DEBUG_G                                                        0x16
++#define ixDP_AUX_DEBUG_H                                                        0x17
++#define ixDP_AUX_DEBUG_I                                                        0x18
++#define ixDP_AUX_DEBUG_J                                                        0x19
++#define ixDP_AUX_DEBUG_K                                                        0x1a
++#define ixDP_AUX_DEBUG_L                                                        0x1b
++#define ixDP_AUX_DEBUG_M                                                        0x1c
++#define ixDP_AUX_DEBUG_N                                                        0x1d
++#define ixDP_AUX_DEBUG_O                                                        0x1e
++#define ixDP_AUX_DEBUG_P                                                        0x1f
++#define ixDP_AUX_DEBUG_Q                                                        0x20
++#define mmDVO_ENABLE                                                            0x16a0
++#define mmDVO_SOURCE_SELECT                                                     0x16a1
++#define mmDVO_OUTPUT                                                            0x16a2
++#define mmDVO_CONTROL                                                           0x16a3
++#define mmDVO_CRC_EN                                                            0x16a4
++#define mmDVO_CRC2_SIG_MASK                                                     0x16a5
++#define mmDVO_CRC2_SIG_RESULT                                                   0x16a6
++#define mmDVO_FIFO_ERROR_STATUS                                                 0x16a7
++#define mmDVO_TEST_DEBUG_INDEX                                                  0x16a8
++#define mmDVO_TEST_DEBUG_DATA                                                   0x16a9
++#define mmFBC_CNTL                                                              0x280
++#define mmFBC_IDLE_MASK                                                         0x281
++#define mmFBC_IDLE_FORCE_CLEAR_MASK                                             0x282
++#define mmFBC_START_STOP_DELAY                                                  0x283
++#define mmFBC_COMP_CNTL                                                         0x284
++#define mmFBC_COMP_MODE                                                         0x285
++#define mmFBC_DEBUG0                                                            0x286
++#define mmFBC_DEBUG1                                                            0x287
++#define mmFBC_DEBUG2                                                            0x288
++#define mmFBC_IND_LUT0                                                          0x289
++#define mmFBC_IND_LUT1                                                          0x28a
++#define mmFBC_IND_LUT2                                                          0x28b
++#define mmFBC_IND_LUT3                                                          0x28c
++#define mmFBC_IND_LUT4                                                          0x28d
++#define mmFBC_IND_LUT5                                                          0x28e
++#define mmFBC_IND_LUT6                                                          0x28f
++#define mmFBC_IND_LUT7                                                          0x290
++#define mmFBC_IND_LUT8                                                          0x291
++#define mmFBC_IND_LUT9                                                          0x292
++#define mmFBC_IND_LUT10                                                         0x293
++#define mmFBC_IND_LUT11                                                         0x294
++#define mmFBC_IND_LUT12                                                         0x295
++#define mmFBC_IND_LUT13                                                         0x296
++#define mmFBC_IND_LUT14                                                         0x297
++#define mmFBC_IND_LUT15                                                         0x298
++#define mmFBC_CSM_REGION_OFFSET_01                                              0x299
++#define mmFBC_CSM_REGION_OFFSET_23                                              0x29a
++#define mmFBC_CLIENT_REGION_MASK                                                0x29b
++#define mmFBC_DEBUG_COMP                                                        0x29c
++#define mmFBC_DEBUG_CSR                                                         0x29d
++#define mmFBC_DEBUG_CSR_RDATA                                                   0x29e
++#define mmFBC_DEBUG_CSR_WDATA                                                   0x29f
++#define mmFBC_DEBUG_CSR_RDATA_HI                                                0x2a0
++#define mmFBC_DEBUG_CSR_WDATA_HI                                                0x2a1
++#define mmFBC_MISC                                                              0x2a2
++#define mmFBC_STATUS                                                            0x2a3
++#define mmFBC_TEST_DEBUG_INDEX                                                  0x2a4
++#define mmFBC_TEST_DEBUG_DATA                                                   0x2a5
++#define mmFMT_CLAMP_COMPONENT_R                                                 0x1be8
++#define mmFMT0_FMT_CLAMP_COMPONENT_R                                            0x1be8
++#define mmFMT1_FMT_CLAMP_COMPONENT_R                                            0x1de8
++#define mmFMT2_FMT_CLAMP_COMPONENT_R                                            0x1fe8
++#define mmFMT3_FMT_CLAMP_COMPONENT_R                                            0x41e8
++#define mmFMT4_FMT_CLAMP_COMPONENT_R                                            0x43e8
++#define mmFMT5_FMT_CLAMP_COMPONENT_R                                            0x45e8
++#define mmFMT_CLAMP_COMPONENT_G                                                 0x1be9
++#define mmFMT0_FMT_CLAMP_COMPONENT_G                                            0x1be9
++#define mmFMT1_FMT_CLAMP_COMPONENT_G                                            0x1de9
++#define mmFMT2_FMT_CLAMP_COMPONENT_G                                            0x1fe9
++#define mmFMT3_FMT_CLAMP_COMPONENT_G                                            0x41e9
++#define mmFMT4_FMT_CLAMP_COMPONENT_G                                            0x43e9
++#define mmFMT5_FMT_CLAMP_COMPONENT_G                                            0x45e9
++#define mmFMT_CLAMP_COMPONENT_B                                                 0x1bea
++#define mmFMT0_FMT_CLAMP_COMPONENT_B                                            0x1bea
++#define mmFMT1_FMT_CLAMP_COMPONENT_B                                            0x1dea
++#define mmFMT2_FMT_CLAMP_COMPONENT_B                                            0x1fea
++#define mmFMT3_FMT_CLAMP_COMPONENT_B                                            0x41ea
++#define mmFMT4_FMT_CLAMP_COMPONENT_B                                            0x43ea
++#define mmFMT5_FMT_CLAMP_COMPONENT_B                                            0x45ea
++#define mmFMT_DYNAMIC_EXP_CNTL                                                  0x1bed
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                             0x1bed
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                             0x1ded
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                             0x1fed
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                             0x41ed
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                             0x43ed
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                             0x45ed
++#define mmFMT_CONTROL                                                           0x1bee
++#define mmFMT0_FMT_CONTROL                                                      0x1bee
++#define mmFMT1_FMT_CONTROL                                                      0x1dee
++#define mmFMT2_FMT_CONTROL                                                      0x1fee
++#define mmFMT3_FMT_CONTROL                                                      0x41ee
++#define mmFMT4_FMT_CONTROL                                                      0x43ee
++#define mmFMT5_FMT_CONTROL                                                      0x45ee
++#define mmFMT_FORCE_OUTPUT_CNTL                                                 0x1bef
++#define mmFMT0_FMT_FORCE_OUTPUT_CNTL                                            0x1bef
++#define mmFMT1_FMT_FORCE_OUTPUT_CNTL                                            0x1def
++#define mmFMT2_FMT_FORCE_OUTPUT_CNTL                                            0x1fef
++#define mmFMT3_FMT_FORCE_OUTPUT_CNTL                                            0x41ef
++#define mmFMT4_FMT_FORCE_OUTPUT_CNTL                                            0x43ef
++#define mmFMT5_FMT_FORCE_OUTPUT_CNTL                                            0x45ef
++#define mmFMT_FORCE_DATA_0_1                                                    0x1bf0
++#define mmFMT0_FMT_FORCE_DATA_0_1                                               0x1bf0
++#define mmFMT1_FMT_FORCE_DATA_0_1                                               0x1df0
++#define mmFMT2_FMT_FORCE_DATA_0_1                                               0x1ff0
++#define mmFMT3_FMT_FORCE_DATA_0_1                                               0x41f0
++#define mmFMT4_FMT_FORCE_DATA_0_1                                               0x43f0
++#define mmFMT5_FMT_FORCE_DATA_0_1                                               0x45f0
++#define mmFMT_FORCE_DATA_2_3                                                    0x1bf1
++#define mmFMT0_FMT_FORCE_DATA_2_3                                               0x1bf1
++#define mmFMT1_FMT_FORCE_DATA_2_3                                               0x1df1
++#define mmFMT2_FMT_FORCE_DATA_2_3                                               0x1ff1
++#define mmFMT3_FMT_FORCE_DATA_2_3                                               0x41f1
++#define mmFMT4_FMT_FORCE_DATA_2_3                                               0x43f1
++#define mmFMT5_FMT_FORCE_DATA_2_3                                               0x45f1
++#define mmFMT_BIT_DEPTH_CONTROL                                                 0x1bf2
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                            0x1bf2
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                            0x1df2
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                            0x1ff2
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                            0x41f2
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL                                            0x43f2
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL                                            0x45f2
++#define mmFMT_DITHER_RAND_R_SEED                                                0x1bf3
++#define mmFMT0_FMT_DITHER_RAND_R_SEED                                           0x1bf3
++#define mmFMT1_FMT_DITHER_RAND_R_SEED                                           0x1df3
++#define mmFMT2_FMT_DITHER_RAND_R_SEED                                           0x1ff3
++#define mmFMT3_FMT_DITHER_RAND_R_SEED                                           0x41f3
++#define mmFMT4_FMT_DITHER_RAND_R_SEED                                           0x43f3
++#define mmFMT5_FMT_DITHER_RAND_R_SEED                                           0x45f3
++#define mmFMT_DITHER_RAND_G_SEED                                                0x1bf4
++#define mmFMT0_FMT_DITHER_RAND_G_SEED                                           0x1bf4
++#define mmFMT1_FMT_DITHER_RAND_G_SEED                                           0x1df4
++#define mmFMT2_FMT_DITHER_RAND_G_SEED                                           0x1ff4
++#define mmFMT3_FMT_DITHER_RAND_G_SEED                                           0x41f4
++#define mmFMT4_FMT_DITHER_RAND_G_SEED                                           0x43f4
++#define mmFMT5_FMT_DITHER_RAND_G_SEED                                           0x45f4
++#define mmFMT_DITHER_RAND_B_SEED                                                0x1bf5
++#define mmFMT0_FMT_DITHER_RAND_B_SEED                                           0x1bf5
++#define mmFMT1_FMT_DITHER_RAND_B_SEED                                           0x1df5
++#define mmFMT2_FMT_DITHER_RAND_B_SEED                                           0x1ff5
++#define mmFMT3_FMT_DITHER_RAND_B_SEED                                           0x41f5
++#define mmFMT4_FMT_DITHER_RAND_B_SEED                                           0x43f5
++#define mmFMT5_FMT_DITHER_RAND_B_SEED                                           0x45f5
++#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL                                   0x1bf6
++#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1bf6
++#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1df6
++#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1ff6
++#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x41f6
++#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x43f6
++#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x45f6
++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                     0x1bf7
++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1bf7
++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1df7
++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1ff7
++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x41f7
++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x43f7
++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x45f7
++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                     0x1bf8
++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1bf8
++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1df8
++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1ff8
++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x41f8
++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x43f8
++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x45f8
++#define mmFMT_CLAMP_CNTL                                                        0x1bf9
++#define mmFMT0_FMT_CLAMP_CNTL                                                   0x1bf9
++#define mmFMT1_FMT_CLAMP_CNTL                                                   0x1df9
++#define mmFMT2_FMT_CLAMP_CNTL                                                   0x1ff9
++#define mmFMT3_FMT_CLAMP_CNTL                                                   0x41f9
++#define mmFMT4_FMT_CLAMP_CNTL                                                   0x43f9
++#define mmFMT5_FMT_CLAMP_CNTL                                                   0x45f9
++#define mmFMT_CRC_CNTL                                                          0x1bfa
++#define mmFMT0_FMT_CRC_CNTL                                                     0x1bfa
++#define mmFMT1_FMT_CRC_CNTL                                                     0x1dfa
++#define mmFMT2_FMT_CRC_CNTL                                                     0x1ffa
++#define mmFMT3_FMT_CRC_CNTL                                                     0x41fa
++#define mmFMT4_FMT_CRC_CNTL                                                     0x43fa
++#define mmFMT5_FMT_CRC_CNTL                                                     0x45fa
++#define mmFMT_CRC_SIG_RED_GREEN_MASK                                            0x1bfb
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1bfb
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1dfb
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1ffb
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                                       0x41fb
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                                       0x43fb
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                                       0x45fb
++#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK                                         0x1bfc
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1bfc
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1dfc
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1ffc
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x41fc
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x43fc
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x45fc
++#define mmFMT_CRC_SIG_RED_GREEN                                                 0x1bfd
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN                                            0x1bfd
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN                                            0x1dfd
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN                                            0x1ffd
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN                                            0x41fd
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN                                            0x43fd
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN                                            0x45fd
++#define mmFMT_CRC_SIG_BLUE_CONTROL                                              0x1bfe
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL                                         0x1bfe
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL                                         0x1dfe
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL                                         0x1ffe
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                                         0x41fe
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL                                         0x43fe
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                                         0x45fe
++#define mmFMT_DEBUG_CNTL                                                        0x1bff
++#define mmFMT0_FMT_DEBUG_CNTL                                                   0x1bff
++#define mmFMT1_FMT_DEBUG_CNTL                                                   0x1dff
++#define mmFMT2_FMT_DEBUG_CNTL                                                   0x1fff
++#define mmFMT3_FMT_DEBUG_CNTL                                                   0x41ff
++#define mmFMT4_FMT_DEBUG_CNTL                                                   0x43ff
++#define mmFMT5_FMT_DEBUG_CNTL                                                   0x45ff
++#define mmFMT_TEST_DEBUG_INDEX                                                  0x1beb
++#define mmFMT0_FMT_TEST_DEBUG_INDEX                                             0x1beb
++#define mmFMT1_FMT_TEST_DEBUG_INDEX                                             0x1deb
++#define mmFMT2_FMT_TEST_DEBUG_INDEX                                             0x1feb
++#define mmFMT3_FMT_TEST_DEBUG_INDEX                                             0x41eb
++#define mmFMT4_FMT_TEST_DEBUG_INDEX                                             0x43eb
++#define mmFMT5_FMT_TEST_DEBUG_INDEX                                             0x45eb
++#define mmFMT_TEST_DEBUG_DATA                                                   0x1bec
++#define mmFMT0_FMT_TEST_DEBUG_DATA                                              0x1bec
++#define mmFMT1_FMT_TEST_DEBUG_DATA                                              0x1dec
++#define mmFMT2_FMT_TEST_DEBUG_DATA                                              0x1fec
++#define mmFMT3_FMT_TEST_DEBUG_DATA                                              0x41ec
++#define mmFMT4_FMT_TEST_DEBUG_DATA                                              0x43ec
++#define mmFMT5_FMT_TEST_DEBUG_DATA                                              0x45ec
++#define ixFMT_DEBUG0                                                            0x1
++#define ixFMT_DEBUG1                                                            0x2
++#define ixFMT_DEBUG2                                                            0x3
++#define ixFMT_DEBUG_ID                                                          0x0
++#define mmLB_DATA_FORMAT                                                        0x1ac0
++#define mmLB0_LB_DATA_FORMAT                                                    0x1ac0
++#define mmLB1_LB_DATA_FORMAT                                                    0x1cc0
++#define mmLB2_LB_DATA_FORMAT                                                    0x1ec0
++#define mmLB3_LB_DATA_FORMAT                                                    0x40c0
++#define mmLB4_LB_DATA_FORMAT                                                    0x42c0
++#define mmLB5_LB_DATA_FORMAT                                                    0x44c0
++#define mmLB_MEMORY_CTRL                                                        0x1ac1
++#define mmLB0_LB_MEMORY_CTRL                                                    0x1ac1
++#define mmLB1_LB_MEMORY_CTRL                                                    0x1cc1
++#define mmLB2_LB_MEMORY_CTRL                                                    0x1ec1
++#define mmLB3_LB_MEMORY_CTRL                                                    0x40c1
++#define mmLB4_LB_MEMORY_CTRL                                                    0x42c1
++#define mmLB5_LB_MEMORY_CTRL                                                    0x44c1
++#define mmLB_MEMORY_SIZE_STATUS                                                 0x1ac2
++#define mmLB0_LB_MEMORY_SIZE_STATUS                                             0x1ac2
++#define mmLB1_LB_MEMORY_SIZE_STATUS                                             0x1cc2
++#define mmLB2_LB_MEMORY_SIZE_STATUS                                             0x1ec2
++#define mmLB3_LB_MEMORY_SIZE_STATUS                                             0x40c2
++#define mmLB4_LB_MEMORY_SIZE_STATUS                                             0x42c2
++#define mmLB5_LB_MEMORY_SIZE_STATUS                                             0x44c2
++#define mmLB_DESKTOP_HEIGHT                                                     0x1ac3
++#define mmLB0_LB_DESKTOP_HEIGHT                                                 0x1ac3
++#define mmLB1_LB_DESKTOP_HEIGHT                                                 0x1cc3
++#define mmLB2_LB_DESKTOP_HEIGHT                                                 0x1ec3
++#define mmLB3_LB_DESKTOP_HEIGHT                                                 0x40c3
++#define mmLB4_LB_DESKTOP_HEIGHT                                                 0x42c3
++#define mmLB5_LB_DESKTOP_HEIGHT                                                 0x44c3
++#define mmLB_VLINE_START_END                                                    0x1ac4
++#define mmLB0_LB_VLINE_START_END                                                0x1ac4
++#define mmLB1_LB_VLINE_START_END                                                0x1cc4
++#define mmLB2_LB_VLINE_START_END                                                0x1ec4
++#define mmLB3_LB_VLINE_START_END                                                0x40c4
++#define mmLB4_LB_VLINE_START_END                                                0x42c4
++#define mmLB5_LB_VLINE_START_END                                                0x44c4
++#define mmLB_VLINE2_START_END                                                   0x1ac5
++#define mmLB0_LB_VLINE2_START_END                                               0x1ac5
++#define mmLB1_LB_VLINE2_START_END                                               0x1cc5
++#define mmLB2_LB_VLINE2_START_END                                               0x1ec5
++#define mmLB3_LB_VLINE2_START_END                                               0x40c5
++#define mmLB4_LB_VLINE2_START_END                                               0x42c5
++#define mmLB5_LB_VLINE2_START_END                                               0x44c5
++#define mmLB_V_COUNTER                                                          0x1ac6
++#define mmLB0_LB_V_COUNTER                                                      0x1ac6
++#define mmLB1_LB_V_COUNTER                                                      0x1cc6
++#define mmLB2_LB_V_COUNTER                                                      0x1ec6
++#define mmLB3_LB_V_COUNTER                                                      0x40c6
++#define mmLB4_LB_V_COUNTER                                                      0x42c6
++#define mmLB5_LB_V_COUNTER                                                      0x44c6
++#define mmLB_SNAPSHOT_V_COUNTER                                                 0x1ac7
++#define mmLB0_LB_SNAPSHOT_V_COUNTER                                             0x1ac7
++#define mmLB1_LB_SNAPSHOT_V_COUNTER                                             0x1cc7
++#define mmLB2_LB_SNAPSHOT_V_COUNTER                                             0x1ec7
++#define mmLB3_LB_SNAPSHOT_V_COUNTER                                             0x40c7
++#define mmLB4_LB_SNAPSHOT_V_COUNTER                                             0x42c7
++#define mmLB5_LB_SNAPSHOT_V_COUNTER                                             0x44c7
++#define mmLB_INTERRUPT_MASK                                                     0x1ac8
++#define mmLB0_LB_INTERRUPT_MASK                                                 0x1ac8
++#define mmLB1_LB_INTERRUPT_MASK                                                 0x1cc8
++#define mmLB2_LB_INTERRUPT_MASK                                                 0x1ec8
++#define mmLB3_LB_INTERRUPT_MASK                                                 0x40c8
++#define mmLB4_LB_INTERRUPT_MASK                                                 0x42c8
++#define mmLB5_LB_INTERRUPT_MASK                                                 0x44c8
++#define mmLB_VLINE_STATUS                                                       0x1ac9
++#define mmLB0_LB_VLINE_STATUS                                                   0x1ac9
++#define mmLB1_LB_VLINE_STATUS                                                   0x1cc9
++#define mmLB2_LB_VLINE_STATUS                                                   0x1ec9
++#define mmLB3_LB_VLINE_STATUS                                                   0x40c9
++#define mmLB4_LB_VLINE_STATUS                                                   0x42c9
++#define mmLB5_LB_VLINE_STATUS                                                   0x44c9
++#define mmLB_VLINE2_STATUS                                                      0x1aca
++#define mmLB0_LB_VLINE2_STATUS                                                  0x1aca
++#define mmLB1_LB_VLINE2_STATUS                                                  0x1cca
++#define mmLB2_LB_VLINE2_STATUS                                                  0x1eca
++#define mmLB3_LB_VLINE2_STATUS                                                  0x40ca
++#define mmLB4_LB_VLINE2_STATUS                                                  0x42ca
++#define mmLB5_LB_VLINE2_STATUS                                                  0x44ca
++#define mmLB_VBLANK_STATUS                                                      0x1acb
++#define mmLB0_LB_VBLANK_STATUS                                                  0x1acb
++#define mmLB1_LB_VBLANK_STATUS                                                  0x1ccb
++#define mmLB2_LB_VBLANK_STATUS                                                  0x1ecb
++#define mmLB3_LB_VBLANK_STATUS                                                  0x40cb
++#define mmLB4_LB_VBLANK_STATUS                                                  0x42cb
++#define mmLB5_LB_VBLANK_STATUS                                                  0x44cb
++#define mmLB_SYNC_RESET_SEL                                                     0x1acc
++#define mmLB0_LB_SYNC_RESET_SEL                                                 0x1acc
++#define mmLB1_LB_SYNC_RESET_SEL                                                 0x1ccc
++#define mmLB2_LB_SYNC_RESET_SEL                                                 0x1ecc
++#define mmLB3_LB_SYNC_RESET_SEL                                                 0x40cc
++#define mmLB4_LB_SYNC_RESET_SEL                                                 0x42cc
++#define mmLB5_LB_SYNC_RESET_SEL                                                 0x44cc
++#define mmLB_BLACK_KEYER_R_CR                                                   0x1acd
++#define mmLB0_LB_BLACK_KEYER_R_CR                                               0x1acd
++#define mmLB1_LB_BLACK_KEYER_R_CR                                               0x1ccd
++#define mmLB2_LB_BLACK_KEYER_R_CR                                               0x1ecd
++#define mmLB3_LB_BLACK_KEYER_R_CR                                               0x40cd
++#define mmLB4_LB_BLACK_KEYER_R_CR                                               0x42cd
++#define mmLB5_LB_BLACK_KEYER_R_CR                                               0x44cd
++#define mmLB_BLACK_KEYER_G_Y                                                    0x1ace
++#define mmLB0_LB_BLACK_KEYER_G_Y                                                0x1ace
++#define mmLB1_LB_BLACK_KEYER_G_Y                                                0x1cce
++#define mmLB2_LB_BLACK_KEYER_G_Y                                                0x1ece
++#define mmLB3_LB_BLACK_KEYER_G_Y                                                0x40ce
++#define mmLB4_LB_BLACK_KEYER_G_Y                                                0x42ce
++#define mmLB5_LB_BLACK_KEYER_G_Y                                                0x44ce
++#define mmLB_BLACK_KEYER_B_CB                                                   0x1acf
++#define mmLB0_LB_BLACK_KEYER_B_CB                                               0x1acf
++#define mmLB1_LB_BLACK_KEYER_B_CB                                               0x1ccf
++#define mmLB2_LB_BLACK_KEYER_B_CB                                               0x1ecf
++#define mmLB3_LB_BLACK_KEYER_B_CB                                               0x40cf
++#define mmLB4_LB_BLACK_KEYER_B_CB                                               0x42cf
++#define mmLB5_LB_BLACK_KEYER_B_CB                                               0x44cf
++#define mmLB_KEYER_COLOR_CTRL                                                   0x1ad0
++#define mmLB0_LB_KEYER_COLOR_CTRL                                               0x1ad0
++#define mmLB1_LB_KEYER_COLOR_CTRL                                               0x1cd0
++#define mmLB2_LB_KEYER_COLOR_CTRL                                               0x1ed0
++#define mmLB3_LB_KEYER_COLOR_CTRL                                               0x40d0
++#define mmLB4_LB_KEYER_COLOR_CTRL                                               0x42d0
++#define mmLB5_LB_KEYER_COLOR_CTRL                                               0x44d0
++#define mmLB_KEYER_COLOR_R_CR                                                   0x1ad1
++#define mmLB0_LB_KEYER_COLOR_R_CR                                               0x1ad1
++#define mmLB1_LB_KEYER_COLOR_R_CR                                               0x1cd1
++#define mmLB2_LB_KEYER_COLOR_R_CR                                               0x1ed1
++#define mmLB3_LB_KEYER_COLOR_R_CR                                               0x40d1
++#define mmLB4_LB_KEYER_COLOR_R_CR                                               0x42d1
++#define mmLB5_LB_KEYER_COLOR_R_CR                                               0x44d1
++#define mmLB_KEYER_COLOR_G_Y                                                    0x1ad2
++#define mmLB0_LB_KEYER_COLOR_G_Y                                                0x1ad2
++#define mmLB1_LB_KEYER_COLOR_G_Y                                                0x1cd2
++#define mmLB2_LB_KEYER_COLOR_G_Y                                                0x1ed2
++#define mmLB3_LB_KEYER_COLOR_G_Y                                                0x40d2
++#define mmLB4_LB_KEYER_COLOR_G_Y                                                0x42d2
++#define mmLB5_LB_KEYER_COLOR_G_Y                                                0x44d2
++#define mmLB_KEYER_COLOR_B_CB                                                   0x1ad3
++#define mmLB0_LB_KEYER_COLOR_B_CB                                               0x1ad3
++#define mmLB1_LB_KEYER_COLOR_B_CB                                               0x1cd3
++#define mmLB2_LB_KEYER_COLOR_B_CB                                               0x1ed3
++#define mmLB3_LB_KEYER_COLOR_B_CB                                               0x40d3
++#define mmLB4_LB_KEYER_COLOR_B_CB                                               0x42d3
++#define mmLB5_LB_KEYER_COLOR_B_CB                                               0x44d3
++#define mmLB_KEYER_COLOR_REP_R_CR                                               0x1ad4
++#define mmLB0_LB_KEYER_COLOR_REP_R_CR                                           0x1ad4
++#define mmLB1_LB_KEYER_COLOR_REP_R_CR                                           0x1cd4
++#define mmLB2_LB_KEYER_COLOR_REP_R_CR                                           0x1ed4
++#define mmLB3_LB_KEYER_COLOR_REP_R_CR                                           0x40d4
++#define mmLB4_LB_KEYER_COLOR_REP_R_CR                                           0x42d4
++#define mmLB5_LB_KEYER_COLOR_REP_R_CR                                           0x44d4
++#define mmLB_KEYER_COLOR_REP_G_Y                                                0x1ad5
++#define mmLB0_LB_KEYER_COLOR_REP_G_Y                                            0x1ad5
++#define mmLB1_LB_KEYER_COLOR_REP_G_Y                                            0x1cd5
++#define mmLB2_LB_KEYER_COLOR_REP_G_Y                                            0x1ed5
++#define mmLB3_LB_KEYER_COLOR_REP_G_Y                                            0x40d5
++#define mmLB4_LB_KEYER_COLOR_REP_G_Y                                            0x42d5
++#define mmLB5_LB_KEYER_COLOR_REP_G_Y                                            0x44d5
++#define mmLB_KEYER_COLOR_REP_B_CB                                               0x1ad6
++#define mmLB0_LB_KEYER_COLOR_REP_B_CB                                           0x1ad6
++#define mmLB1_LB_KEYER_COLOR_REP_B_CB                                           0x1cd6
++#define mmLB2_LB_KEYER_COLOR_REP_B_CB                                           0x1ed6
++#define mmLB3_LB_KEYER_COLOR_REP_B_CB                                           0x40d6
++#define mmLB4_LB_KEYER_COLOR_REP_B_CB                                           0x42d6
++#define mmLB5_LB_KEYER_COLOR_REP_B_CB                                           0x44d6
++#define mmLB_BUFFER_LEVEL_STATUS                                                0x1ad7
++#define mmLB0_LB_BUFFER_LEVEL_STATUS                                            0x1ad7
++#define mmLB1_LB_BUFFER_LEVEL_STATUS                                            0x1cd7
++#define mmLB2_LB_BUFFER_LEVEL_STATUS                                            0x1ed7
++#define mmLB3_LB_BUFFER_LEVEL_STATUS                                            0x40d7
++#define mmLB4_LB_BUFFER_LEVEL_STATUS                                            0x42d7
++#define mmLB5_LB_BUFFER_LEVEL_STATUS                                            0x44d7
++#define mmLB_BUFFER_URGENCY_CTRL                                                0x1ad8
++#define mmLB0_LB_BUFFER_URGENCY_CTRL                                            0x1ad8
++#define mmLB1_LB_BUFFER_URGENCY_CTRL                                            0x1cd8
++#define mmLB2_LB_BUFFER_URGENCY_CTRL                                            0x1ed8
++#define mmLB3_LB_BUFFER_URGENCY_CTRL                                            0x40d8
++#define mmLB4_LB_BUFFER_URGENCY_CTRL                                            0x42d8
++#define mmLB5_LB_BUFFER_URGENCY_CTRL                                            0x44d8
++#define mmLB_BUFFER_URGENCY_STATUS                                              0x1ad9
++#define mmLB0_LB_BUFFER_URGENCY_STATUS                                          0x1ad9
++#define mmLB1_LB_BUFFER_URGENCY_STATUS                                          0x1cd9
++#define mmLB2_LB_BUFFER_URGENCY_STATUS                                          0x1ed9
++#define mmLB3_LB_BUFFER_URGENCY_STATUS                                          0x40d9
++#define mmLB4_LB_BUFFER_URGENCY_STATUS                                          0x42d9
++#define mmLB5_LB_BUFFER_URGENCY_STATUS                                          0x44d9
++#define mmLB_BUFFER_STATUS                                                      0x1ada
++#define mmLB0_LB_BUFFER_STATUS                                                  0x1ada
++#define mmLB1_LB_BUFFER_STATUS                                                  0x1cda
++#define mmLB2_LB_BUFFER_STATUS                                                  0x1eda
++#define mmLB3_LB_BUFFER_STATUS                                                  0x40da
++#define mmLB4_LB_BUFFER_STATUS                                                  0x42da
++#define mmLB5_LB_BUFFER_STATUS                                                  0x44da
++#define mmLB_NO_OUTSTANDING_REQ_STATUS                                          0x1adc
++#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1adc
++#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1cdc
++#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1edc
++#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                                      0x40dc
++#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                                      0x42dc
++#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                                      0x44dc
++#define mmMVP_AFR_FLIP_MODE                                                     0x1ae0
++#define mmLB0_MVP_AFR_FLIP_MODE                                                 0x1ae0
++#define mmLB1_MVP_AFR_FLIP_MODE                                                 0x1ce0
++#define mmLB2_MVP_AFR_FLIP_MODE                                                 0x1ee0
++#define mmLB3_MVP_AFR_FLIP_MODE                                                 0x40e0
++#define mmLB4_MVP_AFR_FLIP_MODE                                                 0x42e0
++#define mmLB5_MVP_AFR_FLIP_MODE                                                 0x44e0
++#define mmMVP_AFR_FLIP_FIFO_CNTL                                                0x1ae1
++#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ae1
++#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ce1
++#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ee1
++#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL                                            0x40e1
++#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL                                            0x42e1
++#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL                                            0x44e1
++#define mmMVP_FLIP_LINE_NUM_INSERT                                              0x1ae2
++#define mmLB0_MVP_FLIP_LINE_NUM_INSERT                                          0x1ae2
++#define mmLB1_MVP_FLIP_LINE_NUM_INSERT                                          0x1ce2
++#define mmLB2_MVP_FLIP_LINE_NUM_INSERT                                          0x1ee2
++#define mmLB3_MVP_FLIP_LINE_NUM_INSERT                                          0x40e2
++#define mmLB4_MVP_FLIP_LINE_NUM_INSERT                                          0x42e2
++#define mmLB5_MVP_FLIP_LINE_NUM_INSERT                                          0x44e2
++#define mmDC_MVP_LB_CONTROL                                                     0x1ae3
++#define mmLB0_DC_MVP_LB_CONTROL                                                 0x1ae3
++#define mmLB1_DC_MVP_LB_CONTROL                                                 0x1ce3
++#define mmLB2_DC_MVP_LB_CONTROL                                                 0x1ee3
++#define mmLB3_DC_MVP_LB_CONTROL                                                 0x40e3
++#define mmLB4_DC_MVP_LB_CONTROL                                                 0x42e3
++#define mmLB5_DC_MVP_LB_CONTROL                                                 0x44e3
++#define mmLB_DEBUG                                                              0x1ae4
++#define mmLB0_LB_DEBUG                                                          0x1ae4
++#define mmLB1_LB_DEBUG                                                          0x1ce4
++#define mmLB2_LB_DEBUG                                                          0x1ee4
++#define mmLB3_LB_DEBUG                                                          0x40e4
++#define mmLB4_LB_DEBUG                                                          0x42e4
++#define mmLB5_LB_DEBUG                                                          0x44e4
++#define mmLB_DEBUG2                                                             0x1ae5
++#define mmLB0_LB_DEBUG2                                                         0x1ae5
++#define mmLB1_LB_DEBUG2                                                         0x1ce5
++#define mmLB2_LB_DEBUG2                                                         0x1ee5
++#define mmLB3_LB_DEBUG2                                                         0x40e5
++#define mmLB4_LB_DEBUG2                                                         0x42e5
++#define mmLB5_LB_DEBUG2                                                         0x44e5
++#define mmLB_DEBUG3                                                             0x1ae6
++#define mmLB0_LB_DEBUG3                                                         0x1ae6
++#define mmLB1_LB_DEBUG3                                                         0x1ce6
++#define mmLB2_LB_DEBUG3                                                         0x1ee6
++#define mmLB3_LB_DEBUG3                                                         0x40e6
++#define mmLB4_LB_DEBUG3                                                         0x42e6
++#define mmLB5_LB_DEBUG3                                                         0x44e6
++#define mmLB_TEST_DEBUG_INDEX                                                   0x1afe
++#define mmLB0_LB_TEST_DEBUG_INDEX                                               0x1afe
++#define mmLB1_LB_TEST_DEBUG_INDEX                                               0x1cfe
++#define mmLB2_LB_TEST_DEBUG_INDEX                                               0x1efe
++#define mmLB3_LB_TEST_DEBUG_INDEX                                               0x40fe
++#define mmLB4_LB_TEST_DEBUG_INDEX                                               0x42fe
++#define mmLB5_LB_TEST_DEBUG_INDEX                                               0x44fe
++#define mmLB_TEST_DEBUG_DATA                                                    0x1aff
++#define mmLB0_LB_TEST_DEBUG_DATA                                                0x1aff
++#define mmLB1_LB_TEST_DEBUG_DATA                                                0x1cff
++#define mmLB2_LB_TEST_DEBUG_DATA                                                0x1eff
++#define mmLB3_LB_TEST_DEBUG_DATA                                                0x40ff
++#define mmLB4_LB_TEST_DEBUG_DATA                                                0x42ff
++#define mmLB5_LB_TEST_DEBUG_DATA                                                0x44ff
++#define mmLBV_DATA_FORMAT                                                       0x463c
++#define mmLBV_MEMORY_CTRL                                                       0x463d
++#define mmLBV_MEMORY_SIZE_STATUS                                                0x463e
++#define mmLBV_DESKTOP_HEIGHT                                                    0x463f
++#define mmLBV_VLINE_START_END                                                   0x4640
++#define mmLBV_VLINE2_START_END                                                  0x4641
++#define mmLBV_V_COUNTER                                                         0x4642
++#define mmLBV_SNAPSHOT_V_COUNTER                                                0x4643
++#define mmLBV_V_COUNTER_CHROMA                                                  0x4644
++#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA                                         0x4645
++#define mmLBV_INTERRUPT_MASK                                                    0x4646
++#define mmLBV_VLINE_STATUS                                                      0x4647
++#define mmLBV_VLINE2_STATUS                                                     0x4648
++#define mmLBV_VBLANK_STATUS                                                     0x4649
++#define mmLBV_SYNC_RESET_SEL                                                    0x464a
++#define mmLBV_BLACK_KEYER_R_CR                                                  0x464b
++#define mmLBV_BLACK_KEYER_G_Y                                                   0x464c
++#define mmLBV_BLACK_KEYER_B_CB                                                  0x464d
++#define mmLBV_KEYER_COLOR_CTRL                                                  0x464e
++#define mmLBV_KEYER_COLOR_R_CR                                                  0x464f
++#define mmLBV_KEYER_COLOR_G_Y                                                   0x4650
++#define mmLBV_KEYER_COLOR_B_CB                                                  0x4651
++#define mmLBV_KEYER_COLOR_REP_R_CR                                              0x4652
++#define mmLBV_KEYER_COLOR_REP_G_Y                                               0x4653
++#define mmLBV_KEYER_COLOR_REP_B_CB                                              0x4654
++#define mmLBV_BUFFER_LEVEL_STATUS                                               0x4655
++#define mmLBV_BUFFER_URGENCY_CTRL                                               0x4656
++#define mmLBV_BUFFER_URGENCY_STATUS                                             0x4657
++#define mmLBV_BUFFER_STATUS                                                     0x4658
++#define mmLBV_NO_OUTSTANDING_REQ_STATUS                                         0x4659
++#define mmLBV_DEBUG                                                             0x465a
++#define mmLBV_DEBUG2                                                            0x465b
++#define mmLBV_DEBUG3                                                            0x465c
++#define mmLBV_TEST_DEBUG_INDEX                                                  0x4666
++#define mmLBV_TEST_DEBUG_DATA                                                   0x4667
++#define mmMVP_CONTROL1                                                          0x2ac
++#define mmMVP_CONTROL2                                                          0x2ad
++#define mmMVP_FIFO_CONTROL                                                      0x2ae
++#define mmMVP_FIFO_STATUS                                                       0x2af
++#define mmMVP_SLAVE_STATUS                                                      0x2b0
++#define mmMVP_INBAND_CNTL_CAP                                                   0x2b1
++#define mmMVP_BLACK_KEYER                                                       0x2b2
++#define mmMVP_CRC_CNTL                                                          0x2b3
++#define mmMVP_CRC_RESULT_BLUE_GREEN                                             0x2b4
++#define mmMVP_CRC_RESULT_RED                                                    0x2b5
++#define mmMVP_CONTROL3                                                          0x2b6
++#define mmMVP_RECEIVE_CNT_CNTL1                                                 0x2b7
++#define mmMVP_RECEIVE_CNT_CNTL2                                                 0x2b8
++#define mmMVP_DEBUG                                                             0x2bb
++#define mmMVP_TEST_DEBUG_INDEX                                                  0x2b9
++#define mmMVP_TEST_DEBUG_DATA                                                   0x2ba
++#define ixMVP_DEBUG_12                                                          0xc
++#define ixMVP_DEBUG_13                                                          0xd
++#define ixMVP_DEBUG_14                                                          0xe
++#define ixMVP_DEBUG_15                                                          0xf
++#define ixMVP_DEBUG_16                                                          0x10
++#define ixMVP_DEBUG_17                                                          0x11
++#define mmSCL_COEF_RAM_SELECT                                                   0x1b40
++#define mmSCL0_SCL_COEF_RAM_SELECT                                              0x1b40
++#define mmSCL1_SCL_COEF_RAM_SELECT                                              0x1d40
++#define mmSCL2_SCL_COEF_RAM_SELECT                                              0x1f40
++#define mmSCL3_SCL_COEF_RAM_SELECT                                              0x4140
++#define mmSCL4_SCL_COEF_RAM_SELECT                                              0x4340
++#define mmSCL5_SCL_COEF_RAM_SELECT                                              0x4540
++#define mmSCL_COEF_RAM_TAP_DATA                                                 0x1b41
++#define mmSCL0_SCL_COEF_RAM_TAP_DATA                                            0x1b41
++#define mmSCL1_SCL_COEF_RAM_TAP_DATA                                            0x1d41
++#define mmSCL2_SCL_COEF_RAM_TAP_DATA                                            0x1f41
++#define mmSCL3_SCL_COEF_RAM_TAP_DATA                                            0x4141
++#define mmSCL4_SCL_COEF_RAM_TAP_DATA                                            0x4341
++#define mmSCL5_SCL_COEF_RAM_TAP_DATA                                            0x4541
++#define mmSCL_MODE                                                              0x1b42
++#define mmSCL0_SCL_MODE                                                         0x1b42
++#define mmSCL1_SCL_MODE                                                         0x1d42
++#define mmSCL2_SCL_MODE                                                         0x1f42
++#define mmSCL3_SCL_MODE                                                         0x4142
++#define mmSCL4_SCL_MODE                                                         0x4342
++#define mmSCL5_SCL_MODE                                                         0x4542
++#define mmSCL_TAP_CONTROL                                                       0x1b43
++#define mmSCL0_SCL_TAP_CONTROL                                                  0x1b43
++#define mmSCL1_SCL_TAP_CONTROL                                                  0x1d43
++#define mmSCL2_SCL_TAP_CONTROL                                                  0x1f43
++#define mmSCL3_SCL_TAP_CONTROL                                                  0x4143
++#define mmSCL4_SCL_TAP_CONTROL                                                  0x4343
++#define mmSCL5_SCL_TAP_CONTROL                                                  0x4543
++#define mmSCL_CONTROL                                                           0x1b44
++#define mmSCL0_SCL_CONTROL                                                      0x1b44
++#define mmSCL1_SCL_CONTROL                                                      0x1d44
++#define mmSCL2_SCL_CONTROL                                                      0x1f44
++#define mmSCL3_SCL_CONTROL                                                      0x4144
++#define mmSCL4_SCL_CONTROL                                                      0x4344
++#define mmSCL5_SCL_CONTROL                                                      0x4544
++#define mmSCL_BYPASS_CONTROL                                                    0x1b45
++#define mmSCL0_SCL_BYPASS_CONTROL                                               0x1b45
++#define mmSCL1_SCL_BYPASS_CONTROL                                               0x1d45
++#define mmSCL2_SCL_BYPASS_CONTROL                                               0x1f45
++#define mmSCL3_SCL_BYPASS_CONTROL                                               0x4145
++#define mmSCL4_SCL_BYPASS_CONTROL                                               0x4345
++#define mmSCL5_SCL_BYPASS_CONTROL                                               0x4545
++#define mmSCL_MANUAL_REPLICATE_CONTROL                                          0x1b46
++#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL                                     0x1b46
++#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL                                     0x1d46
++#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL                                     0x1f46
++#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                                     0x4146
++#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                                     0x4346
++#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                                     0x4546
++#define mmSCL_AUTOMATIC_MODE_CONTROL                                            0x1b47
++#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL                                       0x1b47
++#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL                                       0x1d47
++#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL                                       0x1f47
++#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                                       0x4147
++#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                                       0x4347
++#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                                       0x4547
++#define mmSCL_HORZ_FILTER_CONTROL                                               0x1b48
++#define mmSCL0_SCL_HORZ_FILTER_CONTROL                                          0x1b48
++#define mmSCL1_SCL_HORZ_FILTER_CONTROL                                          0x1d48
++#define mmSCL2_SCL_HORZ_FILTER_CONTROL                                          0x1f48
++#define mmSCL3_SCL_HORZ_FILTER_CONTROL                                          0x4148
++#define mmSCL4_SCL_HORZ_FILTER_CONTROL                                          0x4348
++#define mmSCL5_SCL_HORZ_FILTER_CONTROL                                          0x4548
++#define mmSCL_HORZ_FILTER_SCALE_RATIO                                           0x1b49
++#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1b49
++#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1d49
++#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1f49
++#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4149
++#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4349
++#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4549
++#define mmSCL_HORZ_FILTER_INIT                                                  0x1b4a
++#define mmSCL0_SCL_HORZ_FILTER_INIT                                             0x1b4a
++#define mmSCL1_SCL_HORZ_FILTER_INIT                                             0x1d4a
++#define mmSCL2_SCL_HORZ_FILTER_INIT                                             0x1f4a
++#define mmSCL3_SCL_HORZ_FILTER_INIT                                             0x414a
++#define mmSCL4_SCL_HORZ_FILTER_INIT                                             0x434a
++#define mmSCL5_SCL_HORZ_FILTER_INIT                                             0x454a
++#define mmSCL_VERT_FILTER_CONTROL                                               0x1b4b
++#define mmSCL0_SCL_VERT_FILTER_CONTROL                                          0x1b4b
++#define mmSCL1_SCL_VERT_FILTER_CONTROL                                          0x1d4b
++#define mmSCL2_SCL_VERT_FILTER_CONTROL                                          0x1f4b
++#define mmSCL3_SCL_VERT_FILTER_CONTROL                                          0x414b
++#define mmSCL4_SCL_VERT_FILTER_CONTROL                                          0x434b
++#define mmSCL5_SCL_VERT_FILTER_CONTROL                                          0x454b
++#define mmSCL_VERT_FILTER_SCALE_RATIO                                           0x1b4c
++#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO                                      0x1b4c
++#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO                                      0x1d4c
++#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO                                      0x1f4c
++#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                                      0x414c
++#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                                      0x434c
++#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                                      0x454c
++#define mmSCL_VERT_FILTER_INIT                                                  0x1b4d
++#define mmSCL0_SCL_VERT_FILTER_INIT                                             0x1b4d
++#define mmSCL1_SCL_VERT_FILTER_INIT                                             0x1d4d
++#define mmSCL2_SCL_VERT_FILTER_INIT                                             0x1f4d
++#define mmSCL3_SCL_VERT_FILTER_INIT                                             0x414d
++#define mmSCL4_SCL_VERT_FILTER_INIT                                             0x434d
++#define mmSCL5_SCL_VERT_FILTER_INIT                                             0x454d
++#define mmSCL_VERT_FILTER_INIT_BOT                                              0x1b4e
++#define mmSCL0_SCL_VERT_FILTER_INIT_BOT                                         0x1b4e
++#define mmSCL1_SCL_VERT_FILTER_INIT_BOT                                         0x1d4e
++#define mmSCL2_SCL_VERT_FILTER_INIT_BOT                                         0x1f4e
++#define mmSCL3_SCL_VERT_FILTER_INIT_BOT                                         0x414e
++#define mmSCL4_SCL_VERT_FILTER_INIT_BOT                                         0x434e
++#define mmSCL5_SCL_VERT_FILTER_INIT_BOT                                         0x454e
++#define mmSCL_ROUND_OFFSET                                                      0x1b4f
++#define mmSCL0_SCL_ROUND_OFFSET                                                 0x1b4f
++#define mmSCL1_SCL_ROUND_OFFSET                                                 0x1d4f
++#define mmSCL2_SCL_ROUND_OFFSET                                                 0x1f4f
++#define mmSCL3_SCL_ROUND_OFFSET                                                 0x414f
++#define mmSCL4_SCL_ROUND_OFFSET                                                 0x434f
++#define mmSCL5_SCL_ROUND_OFFSET                                                 0x454f
++#define mmSCL_UPDATE                                                            0x1b51
++#define mmSCL0_SCL_UPDATE                                                       0x1b51
++#define mmSCL1_SCL_UPDATE                                                       0x1d51
++#define mmSCL2_SCL_UPDATE                                                       0x1f51
++#define mmSCL3_SCL_UPDATE                                                       0x4151
++#define mmSCL4_SCL_UPDATE                                                       0x4351
++#define mmSCL5_SCL_UPDATE                                                       0x4551
++#define mmSCL_F_SHARP_CONTROL                                                   0x1b53
++#define mmSCL0_SCL_F_SHARP_CONTROL                                              0x1b53
++#define mmSCL1_SCL_F_SHARP_CONTROL                                              0x1d53
++#define mmSCL2_SCL_F_SHARP_CONTROL                                              0x1f53
++#define mmSCL3_SCL_F_SHARP_CONTROL                                              0x4153
++#define mmSCL4_SCL_F_SHARP_CONTROL                                              0x4353
++#define mmSCL5_SCL_F_SHARP_CONTROL                                              0x4553
++#define mmSCL_ALU_CONTROL                                                       0x1b54
++#define mmSCL0_SCL_ALU_CONTROL                                                  0x1b54
++#define mmSCL1_SCL_ALU_CONTROL                                                  0x1d54
++#define mmSCL2_SCL_ALU_CONTROL                                                  0x1f54
++#define mmSCL3_SCL_ALU_CONTROL                                                  0x4154
++#define mmSCL4_SCL_ALU_CONTROL                                                  0x4354
++#define mmSCL5_SCL_ALU_CONTROL                                                  0x4554
++#define mmSCL_COEF_RAM_CONFLICT_STATUS                                          0x1b55
++#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1b55
++#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1d55
++#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1f55
++#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4155
++#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4355
++#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4555
++#define mmVIEWPORT_START_SECONDARY                                              0x1b5b
++#define mmSCL0_VIEWPORT_START_SECONDARY                                         0x1b5b
++#define mmSCL1_VIEWPORT_START_SECONDARY                                         0x1d5b
++#define mmSCL2_VIEWPORT_START_SECONDARY                                         0x1f5b
++#define mmSCL3_VIEWPORT_START_SECONDARY                                         0x415b
++#define mmSCL4_VIEWPORT_START_SECONDARY                                         0x435b
++#define mmSCL5_VIEWPORT_START_SECONDARY                                         0x455b
++#define mmVIEWPORT_START                                                        0x1b5c
++#define mmSCL0_VIEWPORT_START                                                   0x1b5c
++#define mmSCL1_VIEWPORT_START                                                   0x1d5c
++#define mmSCL2_VIEWPORT_START                                                   0x1f5c
++#define mmSCL3_VIEWPORT_START                                                   0x415c
++#define mmSCL4_VIEWPORT_START                                                   0x435c
++#define mmSCL5_VIEWPORT_START                                                   0x455c
++#define mmVIEWPORT_SIZE                                                         0x1b5d
++#define mmSCL0_VIEWPORT_SIZE                                                    0x1b5d
++#define mmSCL1_VIEWPORT_SIZE                                                    0x1d5d
++#define mmSCL2_VIEWPORT_SIZE                                                    0x1f5d
++#define mmSCL3_VIEWPORT_SIZE                                                    0x415d
++#define mmSCL4_VIEWPORT_SIZE                                                    0x435d
++#define mmSCL5_VIEWPORT_SIZE                                                    0x455d
++#define mmEXT_OVERSCAN_LEFT_RIGHT                                               0x1b5e
++#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT                                          0x1b5e
++#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT                                          0x1d5e
++#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT                                          0x1f5e
++#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                                          0x415e
++#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                                          0x435e
++#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                                          0x455e
++#define mmEXT_OVERSCAN_TOP_BOTTOM                                               0x1b5f
++#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM                                          0x1b5f
++#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM                                          0x1d5f
++#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM                                          0x1f5f
++#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                                          0x415f
++#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                                          0x435f
++#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                                          0x455f
++#define mmSCL_MODE_CHANGE_DET1                                                  0x1b60
++#define mmSCL0_SCL_MODE_CHANGE_DET1                                             0x1b60
++#define mmSCL1_SCL_MODE_CHANGE_DET1                                             0x1d60
++#define mmSCL2_SCL_MODE_CHANGE_DET1                                             0x1f60
++#define mmSCL3_SCL_MODE_CHANGE_DET1                                             0x4160
++#define mmSCL4_SCL_MODE_CHANGE_DET1                                             0x4360
++#define mmSCL5_SCL_MODE_CHANGE_DET1                                             0x4560
++#define mmSCL_MODE_CHANGE_DET2                                                  0x1b61
++#define mmSCL0_SCL_MODE_CHANGE_DET2                                             0x1b61
++#define mmSCL1_SCL_MODE_CHANGE_DET2                                             0x1d61
++#define mmSCL2_SCL_MODE_CHANGE_DET2                                             0x1f61
++#define mmSCL3_SCL_MODE_CHANGE_DET2                                             0x4161
++#define mmSCL4_SCL_MODE_CHANGE_DET2                                             0x4361
++#define mmSCL5_SCL_MODE_CHANGE_DET2                                             0x4561
++#define mmSCL_MODE_CHANGE_DET3                                                  0x1b62
++#define mmSCL0_SCL_MODE_CHANGE_DET3                                             0x1b62
++#define mmSCL1_SCL_MODE_CHANGE_DET3                                             0x1d62
++#define mmSCL2_SCL_MODE_CHANGE_DET3                                             0x1f62
++#define mmSCL3_SCL_MODE_CHANGE_DET3                                             0x4162
++#define mmSCL4_SCL_MODE_CHANGE_DET3                                             0x4362
++#define mmSCL5_SCL_MODE_CHANGE_DET3                                             0x4562
++#define mmSCL_MODE_CHANGE_MASK                                                  0x1b63
++#define mmSCL0_SCL_MODE_CHANGE_MASK                                             0x1b63
++#define mmSCL1_SCL_MODE_CHANGE_MASK                                             0x1d63
++#define mmSCL2_SCL_MODE_CHANGE_MASK                                             0x1f63
++#define mmSCL3_SCL_MODE_CHANGE_MASK                                             0x4163
++#define mmSCL4_SCL_MODE_CHANGE_MASK                                             0x4363
++#define mmSCL5_SCL_MODE_CHANGE_MASK                                             0x4563
++#define mmSCL_DEBUG2                                                            0x1b69
++#define mmSCL0_SCL_DEBUG2                                                       0x1b69
++#define mmSCL1_SCL_DEBUG2                                                       0x1d69
++#define mmSCL2_SCL_DEBUG2                                                       0x1f69
++#define mmSCL3_SCL_DEBUG2                                                       0x4169
++#define mmSCL4_SCL_DEBUG2                                                       0x4369
++#define mmSCL5_SCL_DEBUG2                                                       0x4569
++#define mmSCL_DEBUG                                                             0x1b6a
++#define mmSCL0_SCL_DEBUG                                                        0x1b6a
++#define mmSCL1_SCL_DEBUG                                                        0x1d6a
++#define mmSCL2_SCL_DEBUG                                                        0x1f6a
++#define mmSCL3_SCL_DEBUG                                                        0x416a
++#define mmSCL4_SCL_DEBUG                                                        0x436a
++#define mmSCL5_SCL_DEBUG                                                        0x456a
++#define mmSCL_TEST_DEBUG_INDEX                                                  0x1b6b
++#define mmSCL0_SCL_TEST_DEBUG_INDEX                                             0x1b6b
++#define mmSCL1_SCL_TEST_DEBUG_INDEX                                             0x1d6b
++#define mmSCL2_SCL_TEST_DEBUG_INDEX                                             0x1f6b
++#define mmSCL3_SCL_TEST_DEBUG_INDEX                                             0x416b
++#define mmSCL4_SCL_TEST_DEBUG_INDEX                                             0x436b
++#define mmSCL5_SCL_TEST_DEBUG_INDEX                                             0x456b
++#define mmSCL_TEST_DEBUG_DATA                                                   0x1b6c
++#define mmSCL0_SCL_TEST_DEBUG_DATA                                              0x1b6c
++#define mmSCL1_SCL_TEST_DEBUG_DATA                                              0x1d6c
++#define mmSCL2_SCL_TEST_DEBUG_DATA                                              0x1f6c
++#define mmSCL3_SCL_TEST_DEBUG_DATA                                              0x416c
++#define mmSCL4_SCL_TEST_DEBUG_DATA                                              0x436c
++#define mmSCL5_SCL_TEST_DEBUG_DATA                                              0x456c
++#define mmSCLV_COEF_RAM_SELECT                                                  0x4670
++#define mmSCLV_COEF_RAM_TAP_DATA                                                0x4671
++#define mmSCLV_MODE                                                             0x4672
++#define mmSCLV_TAP_CONTROL                                                      0x4673
++#define mmSCLV_CONTROL                                                          0x4674
++#define mmSCLV_MANUAL_REPLICATE_CONTROL                                         0x4675
++#define mmSCLV_AUTOMATIC_MODE_CONTROL                                           0x4676
++#define mmSCLV_HORZ_FILTER_CONTROL                                              0x4677
++#define mmSCLV_HORZ_FILTER_SCALE_RATIO                                          0x4678
++#define mmSCLV_HORZ_FILTER_INIT                                                 0x4679
++#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C                                        0x467a
++#define mmSCLV_HORZ_FILTER_INIT_C                                               0x467b
++#define mmSCLV_VERT_FILTER_CONTROL                                              0x467c
++#define mmSCLV_VERT_FILTER_SCALE_RATIO                                          0x467d
++#define mmSCLV_VERT_FILTER_INIT                                                 0x467e
++#define mmSCLV_VERT_FILTER_INIT_BOT                                             0x467f
++#define mmSCLV_VERT_FILTER_SCALE_RATIO_C                                        0x4680
++#define mmSCLV_VERT_FILTER_INIT_C                                               0x4681
++#define mmSCLV_VERT_FILTER_INIT_BOT_C                                           0x4682
++#define mmSCLV_ROUND_OFFSET                                                     0x4683
++#define mmSCLV_UPDATE                                                           0x4684
++#define mmSCLV_ALU_CONTROL                                                      0x4685
++#define mmSCLV_VIEWPORT_START                                                   0x4686
++#define mmSCLV_VIEWPORT_START_SECONDARY                                         0x4687
++#define mmSCLV_VIEWPORT_SIZE                                                    0x4688
++#define mmSCLV_VIEWPORT_START_C                                                 0x4689
++#define mmSCLV_VIEWPORT_START_SECONDARY_C                                       0x468a
++#define mmSCLV_VIEWPORT_SIZE_C                                                  0x468b
++#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT                                          0x468c
++#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM                                          0x468d
++#define mmSCLV_MODE_CHANGE_DET1                                                 0x468e
++#define mmSCLV_MODE_CHANGE_DET2                                                 0x468f
++#define mmSCLV_MODE_CHANGE_DET3                                                 0x4690
++#define mmSCLV_MODE_CHANGE_MASK                                                 0x4691
++#define mmSCLV_DEBUG2                                                           0x4692
++#define mmSCLV_DEBUG                                                            0x4693
++#define mmSCLV_TEST_DEBUG_INDEX                                                 0x4694
++#define mmSCLV_TEST_DEBUG_DATA                                                  0x4695
++#define mmCOL_MAN_UPDATE                                                        0x46a4
++#define mmCOL_MAN_INPUT_CSC_CONTROL                                             0x46a5
++#define mmINPUT_CSC_C11_C12_A                                                   0x46a6
++#define mmINPUT_CSC_C13_C14_A                                                   0x46a7
++#define mmINPUT_CSC_C21_C22_A                                                   0x46a8
++#define mmINPUT_CSC_C23_C24_A                                                   0x46a9
++#define mmINPUT_CSC_C31_C32_A                                                   0x46aa
++#define mmINPUT_CSC_C33_C34_A                                                   0x46ab
++#define mmINPUT_CSC_C11_C12_B                                                   0x46ac
++#define mmINPUT_CSC_C13_C14_B                                                   0x46ad
++#define mmINPUT_CSC_C21_C22_B                                                   0x46ae
++#define mmINPUT_CSC_C23_C24_B                                                   0x46af
++#define mmINPUT_CSC_C31_C32_B                                                   0x46b0
++#define mmINPUT_CSC_C33_C34_B                                                   0x46b1
++#define mmPRESCALE_CONTROL                                                      0x46b2
++#define mmPRESCALE_VALUES_R                                                     0x46b3
++#define mmPRESCALE_VALUES_G                                                     0x46b4
++#define mmPRESCALE_VALUES_B                                                     0x46b5
++#define mmCOL_MAN_OUTPUT_CSC_CONTROL                                            0x46b6
++#define mmOUTPUT_CSC_C11_C12_A                                                  0x46b7
++#define mmOUTPUT_CSC_C13_C14_A                                                  0x46b8
++#define mmOUTPUT_CSC_C21_C22_A                                                  0x46b9
++#define mmOUTPUT_CSC_C23_C24_A                                                  0x46ba
++#define mmOUTPUT_CSC_C31_C32_A                                                  0x46bb
++#define mmOUTPUT_CSC_C33_C34_A                                                  0x46bc
++#define mmOUTPUT_CSC_C11_C12_B                                                  0x46bd
++#define mmOUTPUT_CSC_C13_C14_B                                                  0x46be
++#define mmOUTPUT_CSC_C21_C22_B                                                  0x46bf
++#define mmOUTPUT_CSC_C23_C24_B                                                  0x46c0
++#define mmOUTPUT_CSC_C31_C32_B                                                  0x46c1
++#define mmOUTPUT_CSC_C33_C34_B                                                  0x46c2
++#define mmDENORM_CLAMP_CONTROL                                                  0x46c3
++#define mmDENORM_CLAMP_RANGE_R_CR                                               0x46c4
++#define mmDENORM_CLAMP_RANGE_G_Y                                                0x46c5
++#define mmDENORM_CLAMP_RANGE_B_CB                                               0x46c6
++#define mmCOL_MAN_FP_CONVERTED_FIELD                                            0x46c7
++#define mmGAMMA_CORR_CONTROL                                                    0x46c8
++#define mmGAMMA_CORR_LUT_INDEX                                                  0x46c9
++#define mmGAMMA_CORR_LUT_DATA                                                   0x46ca
++#define mmGAMMA_CORR_LUT_WRITE_EN_MASK                                          0x46cb
++#define mmGAMMA_CORR_CNTLA_START_CNTL                                           0x46cc
++#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL                                           0x46cd
++#define mmGAMMA_CORR_CNTLA_END_CNTL1                                            0x46ce
++#define mmGAMMA_CORR_CNTLA_END_CNTL2                                            0x46cf
++#define mmGAMMA_CORR_CNTLA_REGION_0_1                                           0x46d0
++#define mmGAMMA_CORR_CNTLA_REGION_2_3                                           0x46d1
++#define mmGAMMA_CORR_CNTLA_REGION_4_5                                           0x46d2
++#define mmGAMMA_CORR_CNTLA_REGION_6_7                                           0x46d3
++#define mmGAMMA_CORR_CNTLA_REGION_8_9                                           0x46d4
++#define mmGAMMA_CORR_CNTLA_REGION_10_11                                         0x46d5
++#define mmGAMMA_CORR_CNTLA_REGION_12_13                                         0x46d6
++#define mmGAMMA_CORR_CNTLA_REGION_14_15                                         0x46d7
++#define mmGAMMA_CORR_CNTLB_START_CNTL                                           0x46d8
++#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL                                           0x46d9
++#define mmGAMMA_CORR_CNTLB_END_CNTL1                                            0x46da
++#define mmGAMMA_CORR_CNTLB_END_CNTL2                                            0x46db
++#define mmGAMMA_CORR_CNTLB_REGION_0_1                                           0x46dc
++#define mmGAMMA_CORR_CNTLB_REGION_2_3                                           0x46dd
++#define mmGAMMA_CORR_CNTLB_REGION_4_5                                           0x46de
++#define mmGAMMA_CORR_CNTLB_REGION_6_7                                           0x46df
++#define mmGAMMA_CORR_CNTLB_REGION_8_9                                           0x46e0
++#define mmGAMMA_CORR_CNTLB_REGION_10_11                                         0x46e1
++#define mmGAMMA_CORR_CNTLB_REGION_12_13                                         0x46e2
++#define mmGAMMA_CORR_CNTLB_REGION_14_15                                         0x46e3
++#define mmCOL_MAN_TEST_DEBUG_INDEX                                              0x46e4
++#define mmCOL_MAN_TEST_DEBUG_DATA                                               0x46e5
++#define mmCOL_MAN_DEBUG_CONTROL                                                 0x46e6
++#define mmUNP_GRPH_ENABLE                                                       0x4600
++#define mmUNP_GRPH_CONTROL                                                      0x4601
++#define mmUNP_GRPH_CONTROL_EXP                                                  0x4603
++#define mmUNP_GRPH_SWAP_CNTL                                                    0x4605
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                                    0x4606
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                                    0x4607
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                               0x4608
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                               0x4609
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                             0x460a
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                             0x460b
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                        0x460c
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                        0x460d
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                                  0x460e
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                                  0x460f
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                             0x4610
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                             0x4611
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                           0x4612
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                           0x4613
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                      0x4614
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                      0x4615
++#define mmUNP_GRPH_PITCH_L                                                      0x4616
++#define mmUNP_GRPH_PITCH_C                                                      0x4617
++#define mmUNP_GRPH_SURFACE_OFFSET_X_L                                           0x4618
++#define mmUNP_GRPH_SURFACE_OFFSET_X_C                                           0x4619
++#define mmUNP_GRPH_SURFACE_OFFSET_Y_L                                           0x461a
++#define mmUNP_GRPH_SURFACE_OFFSET_Y_C                                           0x461b
++#define mmUNP_GRPH_X_START_L                                                    0x461c
++#define mmUNP_GRPH_X_START_C                                                    0x461d
++#define mmUNP_GRPH_Y_START_L                                                    0x461e
++#define mmUNP_GRPH_Y_START_C                                                    0x461f
++#define mmUNP_GRPH_X_END_L                                                      0x4620
++#define mmUNP_GRPH_X_END_C                                                      0x4621
++#define mmUNP_GRPH_Y_END_L                                                      0x4622
++#define mmUNP_GRPH_Y_END_C                                                      0x4623
++#define mmUNP_GRPH_UPDATE                                                       0x4624
++#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L                                      0x4625
++#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C                                      0x4626
++#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                                 0x4627
++#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                                 0x4628
++#define mmUNP_GRPH_DFQ_CONTROL                                                  0x4629
++#define mmUNP_GRPH_DFQ_STATUS                                                   0x462a
++#define mmUNP_GRPH_INTERRUPT_STATUS                                             0x462b
++#define mmUNP_GRPH_INTERRUPT_CONTROL                                            0x462c
++#define mmUNP_GRPH_STEREOSYNC_FLIP                                              0x462e
++#define mmUNP_GRPH_FLIP_RATE_CNTL                                               0x462f
++#define mmUNP_CRC_CONTROL                                                       0x4630
++#define mmUNP_CRC_MASK                                                          0x4631
++#define mmUNP_CRC_CURRENT                                                       0x4632
++#define mmUNP_CRC_LAST                                                          0x4633
++#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x4634
++#define mmUNP_HW_ROTATION                                                       0x4635
++#define mmUNP_DEBUG                                                             0x4636
++#define mmUNP_DEBUG2                                                            0x4637
++#define mmUNP_TEST_DEBUG_INDEX                                                  0x4638
++#define mmUNP_TEST_DEBUG_DATA                                                   0x4639
++#define mmGENMO_WT                                                              0xf0
++#define mmGENMO_RD                                                              0xf3
++#define mmGENENB                                                                0xf0
++#define mmGENFC_WT                                                              0xee
++#define mmVGA0_GENFC_WT                                                         0xee
++#define mmVGA1_GENFC_WT                                                         0xf6
++#define mmGENFC_RD                                                              0xf2
++#define mmGENS0                                                                 0xf0
++#define mmGENS1                                                                 0xee
++#define mmVGA0_GENS1                                                            0xee
++#define mmVGA1_GENS1                                                            0xf6
++#define mmDAC_DATA                                                              0xf2
++#define mmDAC_MASK                                                              0xf1
++#define mmDAC_R_INDEX                                                           0xf1
++#define mmDAC_W_INDEX                                                           0xf2
++#define mmSEQ8_IDX                                                              0xf1
++#define mmSEQ8_DATA                                                             0xf1
++#define ixSEQ00                                                                 0x0
++#define ixSEQ01                                                                 0x1
++#define ixSEQ02                                                                 0x2
++#define ixSEQ03                                                                 0x3
++#define ixSEQ04                                                                 0x4
++#define mmCRTC8_IDX                                                             0xed
++#define mmVGA0_CRTC8_IDX                                                        0xed
++#define mmVGA1_CRTC8_IDX                                                        0xf5
++#define mmCRTC8_DATA                                                            0xed
++#define mmVGA0_CRTC8_DATA                                                       0xed
++#define mmVGA1_CRTC8_DATA                                                       0xf5
++#define ixCRT00                                                                 0x0
++#define ixCRT01                                                                 0x1
++#define ixCRT02                                                                 0x2
++#define ixCRT03                                                                 0x3
++#define ixCRT04                                                                 0x4
++#define ixCRT05                                                                 0x5
++#define ixCRT06                                                                 0x6
++#define ixCRT07                                                                 0x7
++#define ixCRT08                                                                 0x8
++#define ixCRT09                                                                 0x9
++#define ixCRT0A                                                                 0xa
++#define ixCRT0B                                                                 0xb
++#define ixCRT0C                                                                 0xc
++#define ixCRT0D                                                                 0xd
++#define ixCRT0E                                                                 0xe
++#define ixCRT0F                                                                 0xf
++#define ixCRT10                                                                 0x10
++#define ixCRT11                                                                 0x11
++#define ixCRT12                                                                 0x12
++#define ixCRT13                                                                 0x13
++#define ixCRT14                                                                 0x14
++#define ixCRT15                                                                 0x15
++#define ixCRT16                                                                 0x16
++#define ixCRT17                                                                 0x17
++#define ixCRT18                                                                 0x18
++#define ixCRT1E                                                                 0x1e
++#define ixCRT1F                                                                 0x1f
++#define ixCRT22                                                                 0x22
++#define mmGRPH8_IDX                                                             0xf3
++#define mmGRPH8_DATA                                                            0xf3
++#define ixGRA00                                                                 0x0
++#define ixGRA01                                                                 0x1
++#define ixGRA02                                                                 0x2
++#define ixGRA03                                                                 0x3
++#define ixGRA04                                                                 0x4
++#define ixGRA05                                                                 0x5
++#define ixGRA06                                                                 0x6
++#define ixGRA07                                                                 0x7
++#define ixGRA08                                                                 0x8
++#define mmATTRX                                                                 0xf0
++#define mmATTRDW                                                                0xf0
++#define mmATTRDR                                                                0xf0
++#define ixATTR00                                                                0x0
++#define ixATTR01                                                                0x1
++#define ixATTR02                                                                0x2
++#define ixATTR03                                                                0x3
++#define ixATTR04                                                                0x4
++#define ixATTR05                                                                0x5
++#define ixATTR06                                                                0x6
++#define ixATTR07                                                                0x7
++#define ixATTR08                                                                0x8
++#define ixATTR09                                                                0x9
++#define ixATTR0A                                                                0xa
++#define ixATTR0B                                                                0xb
++#define ixATTR0C                                                                0xc
++#define ixATTR0D                                                                0xd
++#define ixATTR0E                                                                0xe
++#define ixATTR0F                                                                0xf
++#define ixATTR10                                                                0x10
++#define ixATTR11                                                                0x11
++#define ixATTR12                                                                0x12
++#define ixATTR13                                                                0x13
++#define ixATTR14                                                                0x14
++#define mmVGA_RENDER_CONTROL                                                    0xc0
++#define mmVGA_SOURCE_SELECT                                                     0xfc
++#define mmVGA_SEQUENCER_RESET_CONTROL                                           0xc1
++#define mmVGA_MODE_CONTROL                                                      0xc2
++#define mmVGA_SURFACE_PITCH_SELECT                                              0xc3
++#define mmVGA_MEMORY_BASE_ADDRESS                                               0xc4
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                          0xc9
++#define mmVGA_DISPBUF1_SURFACE_ADDR                                             0xc6
++#define mmVGA_DISPBUF2_SURFACE_ADDR                                             0xc8
++#define mmVGA_HDP_CONTROL                                                       0xca
++#define mmVGA_CACHE_CONTROL                                                     0xcb
++#define mmD1VGA_CONTROL                                                         0xcc
++#define mmD2VGA_CONTROL                                                         0xce
++#define mmD3VGA_CONTROL                                                         0xf8
++#define mmD4VGA_CONTROL                                                         0xf9
++#define mmD5VGA_CONTROL                                                         0xfa
++#define mmD6VGA_CONTROL                                                         0xfb
++#define mmVGA_HW_DEBUG                                                          0xcf
++#define mmVGA_STATUS                                                            0xd0
++#define mmVGA_INTERRUPT_CONTROL                                                 0xd1
++#define mmVGA_STATUS_CLEAR                                                      0xd2
++#define mmVGA_INTERRUPT_STATUS                                                  0xd3
++#define mmVGA_MAIN_CONTROL                                                      0xd4
++#define mmVGA_TEST_CONTROL                                                      0xd5
++#define mmVGA_DEBUG_READBACK_INDEX                                              0xd6
++#define mmVGA_DEBUG_READBACK_DATA                                               0xd7
++#define mmVGA_MEM_WRITE_PAGE_ADDR                                               0x12
++#define mmVGA_MEM_READ_PAGE_ADDR                                                0x13
++#define mmVGA_TEST_DEBUG_INDEX                                                  0xc5
++#define mmVGA_TEST_DEBUG_DATA                                                   0xc7
++#define ixVGADCC_DBG_DCCIF_C                                                    0x7e
++#define mmBPHYC_DAC_MACRO_CNTL                                                  0x48b9
++#define mmBPHYC_DAC_AUTO_CALIB_CONTROL                                          0x48ba
++#define mmPLL_REF_DIV                                                           0x1700
++#define mmBPHYC_PLL0_PLL_REF_DIV                                                0x1700
++#define mmBPHYC_PLL1_PLL_REF_DIV                                                0x172a
++#define mmBPHYC_PLL2_PLL_REF_DIV                                                0x1754
++#define mmPLL_FB_DIV                                                            0x1701
++#define mmBPHYC_PLL0_PLL_FB_DIV                                                 0x1701
++#define mmBPHYC_PLL1_PLL_FB_DIV                                                 0x172b
++#define mmBPHYC_PLL2_PLL_FB_DIV                                                 0x1755
++#define mmPLL_POST_DIV                                                          0x1702
++#define mmBPHYC_PLL0_PLL_POST_DIV                                               0x1702
++#define mmBPHYC_PLL1_PLL_POST_DIV                                               0x172c
++#define mmBPHYC_PLL2_PLL_POST_DIV                                               0x1756
++#define mmPLL_SS_AMOUNT_DSFRAC                                                  0x1703
++#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC                                       0x1703
++#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC                                       0x172d
++#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC                                       0x1757
++#define mmPLL_SS_CNTL                                                           0x1704
++#define mmBPHYC_PLL0_PLL_SS_CNTL                                                0x1704
++#define mmBPHYC_PLL1_PLL_SS_CNTL                                                0x172e
++#define mmBPHYC_PLL2_PLL_SS_CNTL                                                0x1758
++#define mmPLL_DS_CNTL                                                           0x1705
++#define mmBPHYC_PLL0_PLL_DS_CNTL                                                0x1705
++#define mmBPHYC_PLL1_PLL_DS_CNTL                                                0x172f
++#define mmBPHYC_PLL2_PLL_DS_CNTL                                                0x1759
++#define mmPLL_IDCLK_CNTL                                                        0x1706
++#define mmBPHYC_PLL0_PLL_IDCLK_CNTL                                             0x1706
++#define mmBPHYC_PLL1_PLL_IDCLK_CNTL                                             0x1730
++#define mmBPHYC_PLL2_PLL_IDCLK_CNTL                                             0x175a
++#define mmPLL_CNTL                                                              0x1707
++#define mmBPHYC_PLL0_PLL_CNTL                                                   0x1707
++#define mmBPHYC_PLL1_PLL_CNTL                                                   0x1731
++#define mmBPHYC_PLL2_PLL_CNTL                                                   0x175b
++#define mmPLL_ANALOG                                                            0x1708
++#define mmBPHYC_PLL0_PLL_ANALOG                                                 0x1708
++#define mmBPHYC_PLL1_PLL_ANALOG                                                 0x1732
++#define mmBPHYC_PLL2_PLL_ANALOG                                                 0x175c
++#define mmPLL_VREG_CNTL                                                         0x1709
++#define mmBPHYC_PLL0_PLL_VREG_CNTL                                              0x1709
++#define mmBPHYC_PLL1_PLL_VREG_CNTL                                              0x1733
++#define mmBPHYC_PLL2_PLL_VREG_CNTL                                              0x175d
++#define mmPLL_UNLOCK_DETECT_CNTL                                                0x170a
++#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL                                     0x170a
++#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL                                     0x1734
++#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL                                     0x175e
++#define mmPLL_DEBUG_CNTL                                                        0x170b
++#define mmBPHYC_PLL0_PLL_DEBUG_CNTL                                             0x170b
++#define mmBPHYC_PLL1_PLL_DEBUG_CNTL                                             0x1735
++#define mmBPHYC_PLL2_PLL_DEBUG_CNTL                                             0x175f
++#define mmPLL_UPDATE_LOCK                                                       0x170c
++#define mmBPHYC_PLL0_PLL_UPDATE_LOCK                                            0x170c
++#define mmBPHYC_PLL1_PLL_UPDATE_LOCK                                            0x1736
++#define mmBPHYC_PLL2_PLL_UPDATE_LOCK                                            0x1760
++#define mmPLL_UPDATE_CNTL                                                       0x170d
++#define mmBPHYC_PLL0_PLL_UPDATE_CNTL                                            0x170d
++#define mmBPHYC_PLL1_PLL_UPDATE_CNTL                                            0x1737
++#define mmBPHYC_PLL2_PLL_UPDATE_CNTL                                            0x1761
++#define mmPLL_XOR_LOCK                                                          0x1710
++#define mmBPHYC_PLL0_PLL_XOR_LOCK                                               0x1710
++#define mmBPHYC_PLL1_PLL_XOR_LOCK                                               0x173a
++#define mmBPHYC_PLL2_PLL_XOR_LOCK                                               0x1764
++#define mmPLL_ANALOG_CNTL                                                       0x1711
++#define mmBPHYC_PLL0_PLL_ANALOG_CNTL                                            0x1711
++#define mmBPHYC_PLL1_PLL_ANALOG_CNTL                                            0x173b
++#define mmBPHYC_PLL2_PLL_ANALOG_CNTL                                            0x1765
++#define mmVGA25_PPLL_REF_DIV                                                    0x1712
++#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV                                         0x1712
++#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV                                         0x173c
++#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV                                         0x1766
++#define mmVGA28_PPLL_REF_DIV                                                    0x1713
++#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV                                         0x1713
++#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV                                         0x173d
++#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV                                         0x1767
++#define mmVGA41_PPLL_REF_DIV                                                    0x1714
++#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV                                         0x1714
++#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV                                         0x173e
++#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV                                         0x1768
++#define mmVGA25_PPLL_FB_DIV                                                     0x1715
++#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV                                          0x1715
++#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV                                          0x173f
++#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV                                          0x1769
++#define mmVGA28_PPLL_FB_DIV                                                     0x1716
++#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV                                          0x1716
++#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV                                          0x1740
++#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV                                          0x176a
++#define mmVGA41_PPLL_FB_DIV                                                     0x1717
++#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV                                          0x1717
++#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV                                          0x1741
++#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV                                          0x176b
++#define mmVGA25_PPLL_POST_DIV                                                   0x1718
++#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV                                        0x1718
++#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV                                        0x1742
++#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV                                        0x176c
++#define mmVGA28_PPLL_POST_DIV                                                   0x1719
++#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV                                        0x1719
++#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV                                        0x1743
++#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV                                        0x176d
++#define mmVGA41_PPLL_POST_DIV                                                   0x171a
++#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV                                        0x171a
++#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV                                        0x1744
++#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV                                        0x176e
++#define mmVGA25_PPLL_ANALOG                                                     0x171b
++#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG                                          0x171b
++#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG                                          0x1745
++#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG                                          0x176f
++#define mmVGA28_PPLL_ANALOG                                                     0x171c
++#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG                                          0x171c
++#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG                                          0x1746
++#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG                                          0x1770
++#define mmVGA41_PPLL_ANALOG                                                     0x171d
++#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG                                          0x171d
++#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG                                          0x1747
++#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG                                          0x1771
++#define mmDISPPLL_BG_CNTL                                                       0x171e
++#define mmBPHYC_PLL0_DISPPLL_BG_CNTL                                            0x171e
++#define mmBPHYC_PLL1_DISPPLL_BG_CNTL                                            0x1748
++#define mmBPHYC_PLL2_DISPPLL_BG_CNTL                                            0x1772
++#define mmPPLL_DIV_UPDATE_DEBUG                                                 0x171f
++#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG                                      0x171f
++#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG                                      0x1749
++#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG                                      0x1773
++#define mmPPLL_STATUS_DEBUG                                                     0x1720
++#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG                                          0x1720
++#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG                                          0x174a
++#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG                                          0x1774
++#define mmPPLL_DEBUG_MUX_CNTL                                                   0x1721
++#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL                                        0x1721
++#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL                                        0x174b
++#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL                                        0x1775
++#define mmPPLL_SPARE0                                                           0x1722
++#define mmBPHYC_PLL0_PPLL_SPARE0                                                0x1722
++#define mmBPHYC_PLL1_PPLL_SPARE0                                                0x174c
++#define mmBPHYC_PLL2_PPLL_SPARE0                                                0x1776
++#define mmPPLL_SPARE1                                                           0x1723
++#define mmBPHYC_PLL0_PPLL_SPARE1                                                0x1723
++#define mmBPHYC_PLL1_PPLL_SPARE1                                                0x174d
++#define mmBPHYC_PLL2_PPLL_SPARE1                                                0x1777
++#define mmUNIPHY_TX_CONTROL1                                                    0x48c0
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1                                      0x48c0
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1                                      0x48e0
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1                                      0x4900
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1                                      0x4920
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1                                      0x4940
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1                                      0x4960
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1                                      0x4980
++#define mmUNIPHY_TX_CONTROL2                                                    0x48c1
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2                                      0x48c1
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2                                      0x48e1
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2                                      0x4901
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2                                      0x4921
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2                                      0x4941
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2                                      0x4961
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2                                      0x4981
++#define mmUNIPHY_TX_CONTROL3                                                    0x48c2
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3                                      0x48c2
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3                                      0x48e2
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3                                      0x4902
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3                                      0x4922
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3                                      0x4942
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3                                      0x4962
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3                                      0x4982
++#define mmUNIPHY_TX_CONTROL4                                                    0x48c3
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4                                      0x48c3
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4                                      0x48e3
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4                                      0x4903
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4                                      0x4923
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4                                      0x4943
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4                                      0x4963
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4                                      0x4983
++#define mmUNIPHY_POWER_CONTROL                                                  0x48c4
++#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL                                    0x48c4
++#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL                                    0x48e4
++#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL                                    0x4904
++#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL                                    0x4924
++#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL                                    0x4944
++#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL                                    0x4964
++#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL                                    0x4984
++#define mmUNIPHY_PLL_FBDIV                                                      0x48c5
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV                                        0x48c5
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV                                        0x48e5
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV                                        0x4905
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV                                        0x4925
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV                                        0x4945
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV                                        0x4965
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV                                        0x4985
++#define mmUNIPHY_PLL_CONTROL1                                                   0x48c6
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1                                     0x48c6
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1                                     0x48e6
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1                                     0x4906
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1                                     0x4926
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1                                     0x4946
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1                                     0x4966
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1                                     0x4986
++#define mmUNIPHY_PLL_CONTROL2                                                   0x48c7
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2                                     0x48c7
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2                                     0x48e7
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2                                     0x4907
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2                                     0x4927
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2                                     0x4947
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2                                     0x4967
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2                                     0x4987
++#define mmUNIPHY_PLL_SS_STEP_SIZE                                               0x48c8
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                                 0x48c8
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                                 0x48e8
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                                 0x4908
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                                 0x4928
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                                 0x4948
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                                 0x4968
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                                 0x4988
++#define mmUNIPHY_PLL_SS_CNTL                                                    0x48c9
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL                                      0x48c9
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL                                      0x48e9
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL                                      0x4909
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL                                      0x4929
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL                                      0x4949
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL                                      0x4969
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL                                      0x4989
++#define mmUNIPHY_DATA_SYNCHRONIZATION                                           0x48ca
++#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION                             0x48ca
++#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION                             0x48ea
++#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION                             0x490a
++#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION                             0x492a
++#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION                             0x494a
++#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION                             0x496a
++#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION                             0x498a
++#define mmUNIPHY_REG_TEST_OUTPUT                                                0x48cb
++#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                                  0x48cb
++#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                                  0x48eb
++#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                                  0x490b
++#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                                  0x492b
++#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                                  0x494b
++#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                                  0x496b
++#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                                  0x498b
++#define mmUNIPHY_ANG_BIST_CNTL                                                  0x48cc
++#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL                                    0x48cc
++#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL                                    0x48ec
++#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL                                    0x490c
++#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL                                    0x492c
++#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL                                    0x494c
++#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL                                    0x496c
++#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL                                    0x498c
++#define mmUNIPHY_REG_TEST_OUTPUT2                                               0x48cd
++#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                                 0x48cd
++#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                                 0x48ed
++#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                                 0x490d
++#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                                 0x492d
++#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                                 0x494d
++#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                                 0x496d
++#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                                 0x498d
++#define mmUNIPHY_TMDP_REG0                                                      0x48ce
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0                                        0x48ce
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0                                        0x48ee
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0                                        0x490e
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0                                        0x492e
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0                                        0x494e
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0                                        0x496e
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0                                        0x498e
++#define mmUNIPHY_TMDP_REG1                                                      0x48cf
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1                                        0x48cf
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1                                        0x48ef
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1                                        0x490f
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1                                        0x492f
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1                                        0x494f
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1                                        0x496f
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1                                        0x498f
++#define mmUNIPHY_TMDP_REG2                                                      0x48d0
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2                                        0x48d0
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2                                        0x48f0
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2                                        0x4910
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2                                        0x4930
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2                                        0x4950
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2                                        0x4970
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2                                        0x4990
++#define mmUNIPHY_TMDP_REG3                                                      0x48d1
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3                                        0x48d1
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3                                        0x48f1
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3                                        0x4911
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3                                        0x4931
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3                                        0x4951
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3                                        0x4971
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3                                        0x4991
++#define mmUNIPHY_TMDP_REG4                                                      0x48d2
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4                                        0x48d2
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4                                        0x48f2
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4                                        0x4912
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4                                        0x4932
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4                                        0x4952
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4                                        0x4972
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4                                        0x4992
++#define mmUNIPHY_TMDP_REG5                                                      0x48d3
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5                                        0x48d3
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5                                        0x48f3
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5                                        0x4913
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5                                        0x4933
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5                                        0x4953
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5                                        0x4973
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5                                        0x4993
++#define mmUNIPHY_TMDP_REG6                                                      0x48d4
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6                                        0x48d4
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6                                        0x48f4
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6                                        0x4914
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6                                        0x4934
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6                                        0x4954
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6                                        0x4974
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6                                        0x4994
++#define mmUNIPHY_TPG_CONTROL                                                    0x48d5
++#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL                                      0x48d5
++#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL                                      0x48f5
++#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL                                      0x4915
++#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL                                      0x4935
++#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL                                      0x4955
++#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL                                      0x4975
++#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL                                      0x4995
++#define mmUNIPHY_TPG_SEED                                                       0x48d6
++#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED                                         0x48d6
++#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED                                         0x48f6
++#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED                                         0x4916
++#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED                                         0x4936
++#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED                                         0x4956
++#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED                                         0x4976
++#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED                                         0x4996
++#define mmUNIPHY_DEBUG                                                          0x48d7
++#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG                                            0x48d7
++#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG                                            0x48f7
++#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG                                            0x4917
++#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG                                            0x4937
++#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG                                            0x4957
++#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG                                            0x4977
++#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG                                            0x4997
++#define mmDPG_PIPE_ARBITRATION_CONTROL1                                         0x1b30
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1                                0x1b30
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1                                0x1d30
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1                                0x1f30
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                                0x4130
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                                0x4330
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                                0x4530
++#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1                                0x4730
++#define mmDPG_PIPE_ARBITRATION_CONTROL2                                         0x1b31
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2                                0x1b31
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2                                0x1d31
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2                                0x1f31
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                                0x4131
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                                0x4331
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                                0x4531
++#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2                                0x4731
++#define mmDPG_WATERMARK_MASK_CONTROL                                            0x1b32
++#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL                                   0x1b32
++#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL                                   0x1d32
++#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL                                   0x1f32
++#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                                   0x4132
++#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                                   0x4332
++#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                                   0x4532
++#define mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL                                   0x4732
++#define mmDPG_PIPE_URGENCY_CONTROL                                              0x1b33
++#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL                                     0x1b33
++#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL                                     0x1d33
++#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL                                     0x1f33
++#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                                     0x4133
++#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                                     0x4333
++#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                                     0x4533
++#define mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL                                     0x4733
++#define mmDPG_PIPE_DPM_CONTROL                                                  0x1b34
++#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL                                         0x1b34
++#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL                                         0x1d34
++#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL                                         0x1f34
++#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                                         0x4134
++#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                                         0x4334
++#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                                         0x4534
++#define mmDMIF_PG6_DPG_PIPE_DPM_CONTROL                                         0x4734
++#define mmDPG_PIPE_STUTTER_CONTROL                                              0x1b35
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL                                     0x1b35
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL                                     0x1d35
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL                                     0x1f35
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                                     0x4135
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                                     0x4335
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                                     0x4535
++#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL                                     0x4735
++#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL                                     0x1b36
++#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1b36
++#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1d36
++#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1f36
++#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4136
++#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4336
++#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4536
++#define mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4736
++#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH                                     0x1b37
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1b37
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1d37
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1f37
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4137
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4337
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4537
++#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4737
++#define mmDPG_REPEATER_PROGRAM                                                  0x1b3a
++#define mmDMIF_PG0_DPG_REPEATER_PROGRAM                                         0x1b3a
++#define mmDMIF_PG1_DPG_REPEATER_PROGRAM                                         0x1d3a
++#define mmDMIF_PG2_DPG_REPEATER_PROGRAM                                         0x1f3a
++#define mmDMIF_PG3_DPG_REPEATER_PROGRAM                                         0x413a
++#define mmDMIF_PG4_DPG_REPEATER_PROGRAM                                         0x433a
++#define mmDMIF_PG5_DPG_REPEATER_PROGRAM                                         0x453a
++#define mmDMIF_PG6_DPG_REPEATER_PROGRAM                                         0x473a
++#define mmDPG_HW_DEBUG_A                                                        0x1b3b
++#define mmDMIF_PG0_DPG_HW_DEBUG_A                                               0x1b3b
++#define mmDMIF_PG1_DPG_HW_DEBUG_A                                               0x1d3b
++#define mmDMIF_PG2_DPG_HW_DEBUG_A                                               0x1f3b
++#define mmDMIF_PG3_DPG_HW_DEBUG_A                                               0x413b
++#define mmDMIF_PG4_DPG_HW_DEBUG_A                                               0x433b
++#define mmDMIF_PG5_DPG_HW_DEBUG_A                                               0x453b
++#define mmDMIF_PG6_DPG_HW_DEBUG_A                                               0x473b
++#define mmDPG_HW_DEBUG_B                                                        0x1b3c
++#define mmDMIF_PG0_DPG_HW_DEBUG_B                                               0x1b3c
++#define mmDMIF_PG1_DPG_HW_DEBUG_B                                               0x1d3c
++#define mmDMIF_PG2_DPG_HW_DEBUG_B                                               0x1f3c
++#define mmDMIF_PG3_DPG_HW_DEBUG_B                                               0x413c
++#define mmDMIF_PG4_DPG_HW_DEBUG_B                                               0x433c
++#define mmDMIF_PG5_DPG_HW_DEBUG_B                                               0x453c
++#define mmDMIF_PG6_DPG_HW_DEBUG_B                                               0x473c
++#define mmDPG_HW_DEBUG_11                                                       0x1b3d
++#define mmDMIF_PG0_DPG_HW_DEBUG_11                                              0x1b3d
++#define mmDMIF_PG1_DPG_HW_DEBUG_11                                              0x1d3d
++#define mmDMIF_PG2_DPG_HW_DEBUG_11                                              0x1f3d
++#define mmDMIF_PG3_DPG_HW_DEBUG_11                                              0x413d
++#define mmDMIF_PG4_DPG_HW_DEBUG_11                                              0x433d
++#define mmDMIF_PG5_DPG_HW_DEBUG_11                                              0x453d
++#define mmDMIF_PG6_DPG_HW_DEBUG_11                                              0x473d
++#define mmDPG_TEST_DEBUG_INDEX                                                  0x1b38
++#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX                                         0x1b38
++#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX                                         0x1d38
++#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX                                         0x1f38
++#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                                         0x4138
++#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                                         0x4338
++#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                                         0x4538
++#define mmDMIF_PG6_DPG_TEST_DEBUG_INDEX                                         0x4738
++#define mmDPG_TEST_DEBUG_DATA                                                   0x1b39
++#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA                                          0x1b39
++#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA                                          0x1d39
++#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA                                          0x1f39
++#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA                                          0x4139
++#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA                                          0x4339
++#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA                                          0x4539
++#define mmDMIF_PG6_DPG_TEST_DEBUG_DATA                                          0x4739
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                       0x18
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                        0x18
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0xf00
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                            0xf02
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                 0xf04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT             0x1f04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x1f05
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x1f0a
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x1f0b
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x1f0f
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1705
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                0x17ff
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1720
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2              0x1721
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3              0x1722
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4              0x1723
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1770
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0x1828
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                            0x1829
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                   0x182b
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x182c
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x182d
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x182e
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x182f
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1830
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                0x1831
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1832
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1833
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                     0x1834
++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                               0x1835
++#define mmAZALIA_F0_CODEC_DEBUG                                                 0x1836
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                           0x1837
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                           0x1838
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                           0x1839
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                           0x183a
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                           0x183b
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                           0x183c
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                           0x183d
++#define mmGLOBAL_CAPABILITIES                                                   0x0
++#define mmMINOR_VERSION                                                         0x0
++#define mmMAJOR_VERSION                                                         0x0
++#define mmOUTPUT_PAYLOAD_CAPABILITY                                             0x1
++#define mmINPUT_PAYLOAD_CAPABILITY                                              0x1
++#define mmGLOBAL_CONTROL                                                        0x2
++#define mmWAKE_ENABLE                                                           0x3
++#define mmSTATE_CHANGE_STATUS                                                   0x3
++#define mmGLOBAL_STATUS                                                         0x4
++#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY                                      0x6
++#define mmINPUT_STREAM_PAYLOAD_CAPABILITY                                       0x6
++#define mmINTERRUPT_CONTROL                                                     0x8
++#define mmINTERRUPT_STATUS                                                      0x9
++#define mmWALL_CLOCK_COUNTER                                                    0xc
++#define mmSTREAM_SYNCHRONIZATION                                                0xe
++#define mmCORB_LOWER_BASE_ADDRESS                                               0x10
++#define mmCORB_UPPER_BASE_ADDRESS                                               0x11
++#define mmCORB_WRITE_POINTER                                                    0x12
++#define mmCORB_READ_POINTER                                                     0x12
++#define mmCORB_CONTROL                                                          0x13
++#define mmCORB_STATUS                                                           0x13
++#define mmCORB_SIZE                                                             0x13
++#define mmRIRB_LOWER_BASE_ADDRESS                                               0x14
++#define mmRIRB_UPPER_BASE_ADDRESS                                               0x15
++#define mmRIRB_WRITE_POINTER                                                    0x16
++#define mmRESPONSE_INTERRUPT_COUNT                                              0x16
++#define mmRIRB_CONTROL                                                          0x17
++#define mmRIRB_STATUS                                                           0x17
++#define mmRIRB_SIZE                                                             0x17
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                    0x18
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x18
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x18
++#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                    0x19
++#define mmIMMEDIATE_COMMAND_STATUS                                              0x1a
++#define mmDMA_POSITION_LOWER_BASE_ADDRESS                                       0x1c
++#define mmDMA_POSITION_UPPER_BASE_ADDRESS                                       0x1d
++#define mmWALL_CLOCK_COUNTER_ALIAS                                              0x80c
++#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                           0x20
++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER              0x21
++#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                         0x22
++#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                             0x23
++#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                    0x24
++#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT                                       0x24
++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS               0x26
++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS               0x27
++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS        0x821
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                   0x18
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                    0x18
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x2f09
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x2f0a
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x2f0b
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2200
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x2706
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x270d
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                 0x270e
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                 0x273e
++#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                              0x2724
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x2770
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x2771
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x3f09
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                            0x3f0c
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                  0x3f0e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY            0x3702
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x3707
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x3708
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x3709
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x371c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2          0x371d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3          0x371e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4          0x371f
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION               0x3770
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                        0x3771
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                             0x3772
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                          0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                     0x3776
++#define ixAUDIO_DESCRIPTOR0                                                     0x1
++#define ixAUDIO_DESCRIPTOR1                                                     0x2
++#define ixAUDIO_DESCRIPTOR2                                                     0x3
++#define ixAUDIO_DESCRIPTOR3                                                     0x4
++#define ixAUDIO_DESCRIPTOR4                                                     0x5
++#define ixAUDIO_DESCRIPTOR5                                                     0x6
++#define ixAUDIO_DESCRIPTOR6                                                     0x7
++#define ixAUDIO_DESCRIPTOR7                                                     0x8
++#define ixAUDIO_DESCRIPTOR8                                                     0x9
++#define ixAUDIO_DESCRIPTOR9                                                     0xa
++#define ixAUDIO_DESCRIPTOR10                                                    0xb
++#define ixAUDIO_DESCRIPTOR11                                                    0xc
++#define ixAUDIO_DESCRIPTOR12                                                    0xd
++#define ixAUDIO_DESCRIPTOR13                                                    0xe
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                     0x3777
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                     0x3778
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                     0x3779
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                     0x377a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                   0x377b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                     0x3780
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                      0x3781
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                           0x0
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                0x1
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                      0x2
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                   0x3
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                   0x4
++#define ixSINK_DESCRIPTION0                                                     0x5
++#define ixSINK_DESCRIPTION1                                                     0x6
++#define ixSINK_DESCRIPTION2                                                     0x7
++#define ixSINK_DESCRIPTION3                                                     0x8
++#define ixSINK_DESCRIPTION4                                                     0x9
++#define ixSINK_DESCRIPTION5                                                     0xa
++#define ixSINK_DESCRIPTION6                                                     0xb
++#define ixSINK_DESCRIPTION7                                                     0xc
++#define ixSINK_DESCRIPTION8                                                     0xd
++#define ixSINK_DESCRIPTION9                                                     0xe
++#define ixSINK_DESCRIPTION10                                                    0xf
++#define ixSINK_DESCRIPTION11                                                    0x10
++#define ixSINK_DESCRIPTION12                                                    0x11
++#define ixSINK_DESCRIPTION13                                                    0x12
++#define ixSINK_DESCRIPTION14                                                    0x13
++#define ixSINK_DESCRIPTION15                                                    0x14
++#define ixSINK_DESCRIPTION16                                                    0x15
++#define ixSINK_DESCRIPTION17                                                    0x16
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                      0x3785
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                      0x3786
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                      0x3787
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                      0x3788
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x3789
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x378a
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x378b
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x378c
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x378d
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x378e
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x378f
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x3790
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x3791
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x3792
++#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                  0x3793
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x3797
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x3798
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                      0x3799
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x379a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                               0x379b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x379c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x379d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x379e
++#define mmAZALIA_CONTROLLER_CLOCK_GATING                                        0x17e4
++#define mmAZALIA_AUDIO_DTO                                                      0x17e5
++#define mmAZALIA_AUDIO_DTO_CONTROL                                              0x17e6
++#define mmAZALIA_SCLK_CONTROL                                                   0x17e7
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                        0x17e8
++#define mmAZALIA_DATA_DMA_CONTROL                                               0x17e9
++#define mmAZALIA_BDL_DMA_CONTROL                                                0x17ea
++#define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
++#define mmAZALIA_CORB_DMA_CONTROL                                               0x17ec
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                          0x17f3
++#define mmAZALIA_CYCLIC_BUFFER_SYNC                                             0x17f4
++#define mmAZALIA_GLOBAL_CAPABILITIES                                            0x17f5
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                      0x17f6
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                  0x17f7
++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                       0x17f8
++#define mmAZALIA_CONTROLLER_DEBUG                                               0x17f9
++#define mmAZALIA_MEM_PWR_CTRL                                                   0x1810
++#define mmAZALIA_MEM_PWR_STATUS                                                 0x1811
++#define mmDCI_PG_DEBUG_CONFIG                                                   0x1812
++#define mmAZALIA_INPUT_CRC0_CONTROL0                                            0x17fb
++#define mmAZALIA_INPUT_CRC0_CONTROL1                                            0x17fc
++#define mmAZALIA_INPUT_CRC0_CONTROL2                                            0x17fd
++#define mmAZALIA_INPUT_CRC0_CONTROL3                                            0x17fe
++#define mmAZALIA_INPUT_CRC0_RESULT                                              0x17ff
++#define ixAZALIA_INPUT_CRC0_CHANNEL0                                            0x0
++#define ixAZALIA_INPUT_CRC0_CHANNEL1                                            0x1
++#define ixAZALIA_INPUT_CRC0_CHANNEL2                                            0x2
++#define ixAZALIA_INPUT_CRC0_CHANNEL3                                            0x3
++#define ixAZALIA_INPUT_CRC0_CHANNEL4                                            0x4
++#define ixAZALIA_INPUT_CRC0_CHANNEL5                                            0x5
++#define ixAZALIA_INPUT_CRC0_CHANNEL6                                            0x6
++#define ixAZALIA_INPUT_CRC0_CHANNEL7                                            0x7
++#define mmAZALIA_INPUT_CRC1_CONTROL0                                            0x1800
++#define mmAZALIA_INPUT_CRC1_CONTROL1                                            0x1801
++#define mmAZALIA_INPUT_CRC1_CONTROL2                                            0x1802
++#define mmAZALIA_INPUT_CRC1_CONTROL3                                            0x1803
++#define mmAZALIA_INPUT_CRC1_RESULT                                              0x1804
++#define ixAZALIA_INPUT_CRC1_CHANNEL0                                            0x0
++#define ixAZALIA_INPUT_CRC1_CHANNEL1                                            0x1
++#define ixAZALIA_INPUT_CRC1_CHANNEL2                                            0x2
++#define ixAZALIA_INPUT_CRC1_CHANNEL3                                            0x3
++#define ixAZALIA_INPUT_CRC1_CHANNEL4                                            0x4
++#define ixAZALIA_INPUT_CRC1_CHANNEL5                                            0x5
++#define ixAZALIA_INPUT_CRC1_CHANNEL6                                            0x6
++#define ixAZALIA_INPUT_CRC1_CHANNEL7                                            0x7
++#define mmAZALIA_CRC0_CONTROL0                                                  0x1805
++#define mmAZALIA_CRC0_CONTROL1                                                  0x1806
++#define mmAZALIA_CRC0_CONTROL2                                                  0x1807
++#define mmAZALIA_CRC0_CONTROL3                                                  0x1808
++#define mmAZALIA_CRC0_RESULT                                                    0x1809
++#define ixAZALIA_CRC0_CHANNEL0                                                  0x0
++#define ixAZALIA_CRC0_CHANNEL1                                                  0x1
++#define ixAZALIA_CRC0_CHANNEL2                                                  0x2
++#define ixAZALIA_CRC0_CHANNEL3                                                  0x3
++#define ixAZALIA_CRC0_CHANNEL4                                                  0x4
++#define ixAZALIA_CRC0_CHANNEL5                                                  0x5
++#define ixAZALIA_CRC0_CHANNEL6                                                  0x6
++#define ixAZALIA_CRC0_CHANNEL7                                                  0x7
++#define mmAZALIA_CRC1_CONTROL0                                                  0x180a
++#define mmAZALIA_CRC1_CONTROL1                                                  0x180b
++#define mmAZALIA_CRC1_CONTROL2                                                  0x180c
++#define mmAZALIA_CRC1_CONTROL3                                                  0x180d
++#define mmAZALIA_CRC1_RESULT                                                    0x180e
++#define ixAZALIA_CRC1_CHANNEL0                                                  0x0
++#define ixAZALIA_CRC1_CHANNEL1                                                  0x1
++#define ixAZALIA_CRC1_CHANNEL2                                                  0x2
++#define ixAZALIA_CRC1_CHANNEL3                                                  0x3
++#define ixAZALIA_CRC1_CHANNEL4                                                  0x4
++#define ixAZALIA_CRC1_CHANNEL5                                                  0x5
++#define ixAZALIA_CRC1_CHANNEL6                                                  0x6
++#define ixAZALIA_CRC1_CHANNEL7                                                  0x7
++#define mmAZ_TEST_DEBUG_INDEX                                                   0x181f
++#define mmAZ_TEST_DEBUG_DATA                                                    0x1820
++#define mmAZALIA_STREAM_INDEX                                                   0x1780
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                       0x1780
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                       0x1782
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                       0x1784
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                       0x1786
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                       0x1788
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                       0x178a
++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                       0x178c
++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                       0x178e
++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                       0x59c0
++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                       0x59c2
++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                      0x59c4
++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                      0x59c6
++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                      0x59c8
++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                      0x59ca
++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                      0x59cc
++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                      0x59ce
++#define mmAZALIA_STREAM_DATA                                                    0x1781
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                        0x1781
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                        0x1783
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                        0x1785
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                        0x1787
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                        0x1789
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                        0x178b
++#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                        0x178d
++#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                        0x178f
++#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                        0x59c1
++#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                        0x59c3
++#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                       0x59c5
++#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                       0x59c7
++#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                       0x59c9
++#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                       0x59cb
++#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                       0x59cd
++#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                       0x59cf
++#define ixAZALIA_FIFO_SIZE_CONTROL                                              0x0
++#define ixAZALIA_LATENCY_COUNTER_CONTROL                                        0x1
++#define ixAZALIA_WORSTCASE_LATENCY_COUNT                                        0x2
++#define ixAZALIA_CUMULATIVE_LATENCY_COUNT                                       0x3
++#define ixAZALIA_CUMULATIVE_REQUEST_COUNT                                       0x4
++#define ixAZALIA_STREAM_DEBUG                                                   0x5
++#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX                                        0x17a8
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17a8
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17ac
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b0
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b4
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b8
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17bc
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c0
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c4
++#define mmAZALIA_F0_CODEC_ENDPOINT_DATA                                         0x17a9
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17a9
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17ad
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b1
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b5
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b9
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17bd
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c1
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c5
++#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG                                   0x0
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x1
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x3
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x4
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x5
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x6
++#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                              0x7
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x8
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x9
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG                    0xa
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                           0xc
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                       0xd
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                       0xe
++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x20
++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                            0x21
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x22
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                         0x2b
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                         0x2c
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                         0x2d
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                         0x2e
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                         0x2f
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                         0x30
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                         0x31
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                        0x32
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                        0x33
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                        0x34
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                        0x35
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                       0x36
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                      0x57
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x58
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                          0x37
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                              0x38
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                0x3a
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                0x3b
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                0x3c
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                0x3d
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                0x3e
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                0x3f
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                0x40
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                0x41
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                0x42
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                          0x54
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                0x55
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x56
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x59
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x5a
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x5b
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x5c
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x5d
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x5e
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x5f
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x60
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x61
++#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                  0x62
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x63
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x64
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB                                      0x65
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x66
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                               0x67
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x68
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x69
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x6a
++#define ixAZALIA_F0_AUDIO_ENABLE_STATUS                                         0x6b
++#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS                                    0x6c
++#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS                                   0x6d
++#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                             0x6e
++#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                  0x59d4
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d4
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d8
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59dc
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e0
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e4
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e8
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59ec
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59f0
++#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                   0x59d5
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d5
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d9
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59dd
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e1
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e5
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e9
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59ed
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59f1
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG                             0x0
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x1
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x2
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x3
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x4
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x5
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6
++#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x20
++#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x21
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x22
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE            0x23
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x24
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                 0x36
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                0x37
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                        0x38
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x53
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                    0x54
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE          0x55
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x56
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x67
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x68
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x64
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                0x65
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x66
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                    0x18
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                     0x18
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x6f09
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6f0a
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x6f0b
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x6200
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x6706
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x670d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x7f09
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x7f0c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x7707
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x7708
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                  0x7709
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x771c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2    0x771d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3    0x771e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4    0x771f
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                0x7777
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                0x7785
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                0x7778
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                0x7786
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                 0x777c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                0x7779
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                0x7787
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                0x777a
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                0x7788
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x7771
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x779b
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x779c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                    0x779d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                    0x779e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x7798
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                0x7799
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x779a
++#define mmBLND_CONTROL                                                          0x1b6d
++#define mmBLND0_BLND_CONTROL                                                    0x1b6d
++#define mmBLND1_BLND_CONTROL                                                    0x1d6d
++#define mmBLND2_BLND_CONTROL                                                    0x1f6d
++#define mmBLND3_BLND_CONTROL                                                    0x416d
++#define mmBLND4_BLND_CONTROL                                                    0x436d
++#define mmBLND5_BLND_CONTROL                                                    0x456d
++#define mmBLND6_BLND_CONTROL                                                    0x476d
++#define mmSM_CONTROL2                                                           0x1b6e
++#define mmBLND0_SM_CONTROL2                                                     0x1b6e
++#define mmBLND1_SM_CONTROL2                                                     0x1d6e
++#define mmBLND2_SM_CONTROL2                                                     0x1f6e
++#define mmBLND3_SM_CONTROL2                                                     0x416e
++#define mmBLND4_SM_CONTROL2                                                     0x436e
++#define mmBLND5_SM_CONTROL2                                                     0x456e
++#define mmBLND6_SM_CONTROL2                                                     0x476e
++#define mmBLND_CONTROL2                                                         0x1b6f
++#define mmBLND0_BLND_CONTROL2                                                   0x1b6f
++#define mmBLND1_BLND_CONTROL2                                                   0x1d6f
++#define mmBLND2_BLND_CONTROL2                                                   0x1f6f
++#define mmBLND3_BLND_CONTROL2                                                   0x416f
++#define mmBLND4_BLND_CONTROL2                                                   0x436f
++#define mmBLND5_BLND_CONTROL2                                                   0x456f
++#define mmBLND6_BLND_CONTROL2                                                   0x476f
++#define mmBLND_UPDATE                                                           0x1b70
++#define mmBLND0_BLND_UPDATE                                                     0x1b70
++#define mmBLND1_BLND_UPDATE                                                     0x1d70
++#define mmBLND2_BLND_UPDATE                                                     0x1f70
++#define mmBLND3_BLND_UPDATE                                                     0x4170
++#define mmBLND4_BLND_UPDATE                                                     0x4370
++#define mmBLND5_BLND_UPDATE                                                     0x4570
++#define mmBLND6_BLND_UPDATE                                                     0x4770
++#define mmBLND_UNDERFLOW_INTERRUPT                                              0x1b71
++#define mmBLND0_BLND_UNDERFLOW_INTERRUPT                                        0x1b71
++#define mmBLND1_BLND_UNDERFLOW_INTERRUPT                                        0x1d71
++#define mmBLND2_BLND_UNDERFLOW_INTERRUPT                                        0x1f71
++#define mmBLND3_BLND_UNDERFLOW_INTERRUPT                                        0x4171
++#define mmBLND4_BLND_UNDERFLOW_INTERRUPT                                        0x4371
++#define mmBLND5_BLND_UNDERFLOW_INTERRUPT                                        0x4571
++#define mmBLND6_BLND_UNDERFLOW_INTERRUPT                                        0x4771
++#define mmBLND_V_UPDATE_LOCK                                                    0x1b73
++#define mmBLND0_BLND_V_UPDATE_LOCK                                              0x1b73
++#define mmBLND1_BLND_V_UPDATE_LOCK                                              0x1d73
++#define mmBLND2_BLND_V_UPDATE_LOCK                                              0x1f73
++#define mmBLND3_BLND_V_UPDATE_LOCK                                              0x4173
++#define mmBLND4_BLND_V_UPDATE_LOCK                                              0x4373
++#define mmBLND5_BLND_V_UPDATE_LOCK                                              0x4573
++#define mmBLND6_BLND_V_UPDATE_LOCK                                              0x4773
++#define mmBLND_REG_UPDATE_STATUS                                                0x1b77
++#define mmBLND0_BLND_REG_UPDATE_STATUS                                          0x1b77
++#define mmBLND1_BLND_REG_UPDATE_STATUS                                          0x1d77
++#define mmBLND2_BLND_REG_UPDATE_STATUS                                          0x1f77
++#define mmBLND3_BLND_REG_UPDATE_STATUS                                          0x4177
++#define mmBLND4_BLND_REG_UPDATE_STATUS                                          0x4377
++#define mmBLND5_BLND_REG_UPDATE_STATUS                                          0x4577
++#define mmBLND6_BLND_REG_UPDATE_STATUS                                          0x4777
++#define mmBLND_DEBUG                                                            0x1b74
++#define mmBLND0_BLND_DEBUG                                                      0x1b74
++#define mmBLND1_BLND_DEBUG                                                      0x1d74
++#define mmBLND2_BLND_DEBUG                                                      0x1f74
++#define mmBLND3_BLND_DEBUG                                                      0x4174
++#define mmBLND4_BLND_DEBUG                                                      0x4374
++#define mmBLND5_BLND_DEBUG                                                      0x4574
++#define mmBLND6_BLND_DEBUG                                                      0x4774
++#define mmBLND_TEST_DEBUG_INDEX                                                 0x1b75
++#define mmBLND0_BLND_TEST_DEBUG_INDEX                                           0x1b75
++#define mmBLND1_BLND_TEST_DEBUG_INDEX                                           0x1d75
++#define mmBLND2_BLND_TEST_DEBUG_INDEX                                           0x1f75
++#define mmBLND3_BLND_TEST_DEBUG_INDEX                                           0x4175
++#define mmBLND4_BLND_TEST_DEBUG_INDEX                                           0x4375
++#define mmBLND5_BLND_TEST_DEBUG_INDEX                                           0x4575
++#define mmBLND6_BLND_TEST_DEBUG_INDEX                                           0x4775
++#define mmBLND_TEST_DEBUG_DATA                                                  0x1b76
++#define mmBLND0_BLND_TEST_DEBUG_DATA                                            0x1b76
++#define mmBLND1_BLND_TEST_DEBUG_DATA                                            0x1d76
++#define mmBLND2_BLND_TEST_DEBUG_DATA                                            0x1f76
++#define mmBLND3_BLND_TEST_DEBUG_DATA                                            0x4176
++#define mmBLND4_BLND_TEST_DEBUG_DATA                                            0x4376
++#define mmBLND5_BLND_TEST_DEBUG_DATA                                            0x4576
++#define mmBLND6_BLND_TEST_DEBUG_DATA                                            0x4776
++#define mmWB_ENABLE                                                             0x5e18
++#define mmWB_EC_CONFIG                                                          0x5e19
++#define mmCNV_MODE                                                              0x5e1a
++#define mmCNV_WINDOW_START                                                      0x5e1b
++#define mmCNV_WINDOW_SIZE                                                       0x5e1c
++#define mmCNV_UPDATE                                                            0x5e1d
++#define mmCNV_SOURCE_SIZE                                                       0x5e1e
++#define mmCNV_CSC_CONTROL                                                       0x5e1f
++#define mmCNV_CSC_C11_C12                                                       0x5e20
++#define mmCNV_CSC_C13_C14                                                       0x5e21
++#define mmCNV_CSC_C21_C22                                                       0x5e22
++#define mmCNV_CSC_C23_C24                                                       0x5e23
++#define mmCNV_CSC_C31_C32                                                       0x5e24
++#define mmCNV_CSC_C33_C34                                                       0x5e25
++#define mmCNV_CSC_ROUND_OFFSET_R                                                0x5e26
++#define mmCNV_CSC_ROUND_OFFSET_G                                                0x5e27
++#define mmCNV_CSC_ROUND_OFFSET_B                                                0x5e28
++#define mmCNV_CSC_CLAMP_R                                                       0x5e29
++#define mmCNV_CSC_CLAMP_G                                                       0x5e2a
++#define mmCNV_CSC_CLAMP_B                                                       0x5e2b
++#define mmCNV_TEST_CNTL                                                         0x5e2c
++#define mmCNV_TEST_CRC_RED                                                      0x5e2d
++#define mmCNV_TEST_CRC_GREEN                                                    0x5e2e
++#define mmCNV_TEST_CRC_BLUE                                                     0x5e2f
++#define mmWB_DEBUG_CTRL                                                         0x5e30
++#define mmWB_DBG_MODE                                                           0x5e31
++#define mmWB_HW_DEBUG                                                           0x5e32
++#define mmCNV_INPUT_SELECT                                                      0x5e33
++#define mmWB_SOFT_RESET                                                         0x5e36
++#define mmCNV_TEST_DEBUG_INDEX                                                  0x5e34
++#define mmCNV_TEST_DEBUG_DATA                                                   0x5e35
++#define mmDCFE_CLOCK_CONTROL                                                    0x1b00
++#define mmDCFE0_DCFE_CLOCK_CONTROL                                              0x1b00
++#define mmDCFE1_DCFE_CLOCK_CONTROL                                              0x1d00
++#define mmDCFE2_DCFE_CLOCK_CONTROL                                              0x1f00
++#define mmDCFE3_DCFE_CLOCK_CONTROL                                              0x4100
++#define mmDCFE4_DCFE_CLOCK_CONTROL                                              0x4300
++#define mmDCFE5_DCFE_CLOCK_CONTROL                                              0x4500
++#define mmDCFE_SOFT_RESET                                                       0x1b01
++#define mmDCFE0_DCFE_SOFT_RESET                                                 0x1b01
++#define mmDCFE1_DCFE_SOFT_RESET                                                 0x1d01
++#define mmDCFE2_DCFE_SOFT_RESET                                                 0x1f01
++#define mmDCFE3_DCFE_SOFT_RESET                                                 0x4101
++#define mmDCFE4_DCFE_SOFT_RESET                                                 0x4301
++#define mmDCFE5_DCFE_SOFT_RESET                                                 0x4501
++#define mmDCFE_DBG_CONFIG                                                       0x1b02
++#define mmDCFE0_DCFE_DBG_CONFIG                                                 0x1b02
++#define mmDCFE1_DCFE_DBG_CONFIG                                                 0x1d02
++#define mmDCFE2_DCFE_DBG_CONFIG                                                 0x1f02
++#define mmDCFE3_DCFE_DBG_CONFIG                                                 0x4102
++#define mmDCFE4_DCFE_DBG_CONFIG                                                 0x4302
++#define mmDCFE5_DCFE_DBG_CONFIG                                                 0x4502
++#define mmDCFEV_CLOCK_CONTROL                                                   0x46f4
++#define mmDCFEV_SOFT_RESET                                                      0x46f5
++#define mmDCFEV_DMIFV_CLOCK_CONTROL                                             0x46f6
++#define mmDCFEV_DBG_CONFIG                                                      0x46f7
++#define mmDCFEV_DMIFV_MEM_PWR_CTRL                                              0x46f8
++#define mmDCFEV_DMIFV_MEM_PWR_STATUS                                            0x46f9
++#define mmDC_HPD_INT_STATUS                                                     0x1898
++#define mmHPD0_DC_HPD_INT_STATUS                                                0x1898
++#define mmHPD1_DC_HPD_INT_STATUS                                                0x18a0
++#define mmHPD2_DC_HPD_INT_STATUS                                                0x18a8
++#define mmHPD3_DC_HPD_INT_STATUS                                                0x18b0
++#define mmHPD4_DC_HPD_INT_STATUS                                                0x18b8
++#define mmHPD5_DC_HPD_INT_STATUS                                                0x18c0
++#define mmDC_HPD_INT_CONTROL                                                    0x1899
++#define mmHPD0_DC_HPD_INT_CONTROL                                               0x1899
++#define mmHPD1_DC_HPD_INT_CONTROL                                               0x18a1
++#define mmHPD2_DC_HPD_INT_CONTROL                                               0x18a9
++#define mmHPD3_DC_HPD_INT_CONTROL                                               0x18b1
++#define mmHPD4_DC_HPD_INT_CONTROL                                               0x18b9
++#define mmHPD5_DC_HPD_INT_CONTROL                                               0x18c1
++#define mmDC_HPD_CONTROL                                                        0x189a
++#define mmHPD0_DC_HPD_CONTROL                                                   0x189a
++#define mmHPD1_DC_HPD_CONTROL                                                   0x18a2
++#define mmHPD2_DC_HPD_CONTROL                                                   0x18aa
++#define mmHPD3_DC_HPD_CONTROL                                                   0x18b2
++#define mmHPD4_DC_HPD_CONTROL                                                   0x18ba
++#define mmHPD5_DC_HPD_CONTROL                                                   0x18c2
++#define mmDC_HPD_FAST_TRAIN_CNTL                                                0x189b
++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                           0x189b
++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                           0x18a3
++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                           0x18ab
++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                           0x18b3
++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                           0x18bb
++#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL                                           0x18c3
++#define mmDC_HPD_TOGGLE_FILT_CNTL                                               0x189c
++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                          0x189c
++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                          0x18a4
++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                          0x18ac
++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                          0x18b4
++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                          0x18bc
++#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL                                          0x18c4
++#define mmDCO_SCRATCH0                                                          0x184e
++#define mmDCO_SCRATCH1                                                          0x184f
++#define mmDCO_SCRATCH2                                                          0x1850
++#define mmDCO_SCRATCH3                                                          0x1851
++#define mmDCO_SCRATCH4                                                          0x1852
++#define mmDCO_SCRATCH5                                                          0x1853
++#define mmDCO_SCRATCH6                                                          0x1854
++#define mmDCO_SCRATCH7                                                          0x1855
++#define mmDCE_VCE_CONTROL                                                       0x1856
++#define mmDISP_INTERRUPT_STATUS                                                 0x1857
++#define mmDISP_INTERRUPT_STATUS_CONTINUE                                        0x1858
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                       0x1859
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                       0x185a
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                       0x185b
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                       0x185c
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                       0x185d
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                       0x185e
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                       0x185f
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                       0x1860
++#define mmDCO_MEM_PWR_STATUS                                                    0x1861
++#define mmDCO_MEM_PWR_CTRL                                                      0x1862
++#define mmDCO_MEM_PWR_CTRL2                                                     0x1863
++#define mmDCO_CLK_CNTL                                                          0x1864
++#define mmDCO_CLK_RAMP_CNTL                                                     0x1865
++#define mmDPDBG_CNTL                                                            0x1866
++#define mmDPDBG_INTERRUPT                                                       0x1867
++#define mmDCO_POWER_MANAGEMENT_CNTL                                             0x1868
++#define mmDCO_SOFT_RESET                                                        0x1871
++#define mmDIG_SOFT_RESET                                                        0x1872
++#define mmDCO_STEREOSYNC_SEL                                                    0x186e
++#define mmDCO_TEST_DEBUG_INDEX                                                  0x186f
++#define mmDCO_TEST_DEBUG_DATA                                                   0x1870
++#define mmDC_I2C_CONTROL                                                        0x16d4
++#define mmDC_I2C_ARBITRATION                                                    0x16d5
++#define mmDC_I2C_INTERRUPT_CONTROL                                              0x16d6
++#define mmDC_I2C_SW_STATUS                                                      0x16d7
++#define mmDC_I2C_DDC1_HW_STATUS                                                 0x16d8
++#define mmDC_I2C_DDC2_HW_STATUS                                                 0x16d9
++#define mmDC_I2C_DDC3_HW_STATUS                                                 0x16da
++#define mmDC_I2C_DDC4_HW_STATUS                                                 0x16db
++#define mmDC_I2C_DDC5_HW_STATUS                                                 0x16dc
++#define mmDC_I2C_DDC6_HW_STATUS                                                 0x16dd
++#define mmDC_I2C_DDC1_SPEED                                                     0x16de
++#define mmDC_I2C_DDC1_SETUP                                                     0x16df
++#define mmDC_I2C_DDC2_SPEED                                                     0x16e0
++#define mmDC_I2C_DDC2_SETUP                                                     0x16e1
++#define mmDC_I2C_DDC3_SPEED                                                     0x16e2
++#define mmDC_I2C_DDC3_SETUP                                                     0x16e3
++#define mmDC_I2C_DDC4_SPEED                                                     0x16e4
++#define mmDC_I2C_DDC4_SETUP                                                     0x16e5
++#define mmDC_I2C_DDC5_SPEED                                                     0x16e6
++#define mmDC_I2C_DDC5_SETUP                                                     0x16e7
++#define mmDC_I2C_DDC6_SPEED                                                     0x16e8
++#define mmDC_I2C_DDC6_SETUP                                                     0x16e9
++#define mmDC_I2C_TRANSACTION0                                                   0x16ea
++#define mmDC_I2C_TRANSACTION1                                                   0x16eb
++#define mmDC_I2C_TRANSACTION2                                                   0x16ec
++#define mmDC_I2C_TRANSACTION3                                                   0x16ed
++#define mmDC_I2C_DATA                                                           0x16ee
++#define mmDC_I2C_DDCVGA_HW_STATUS                                               0x16ef
++#define mmDC_I2C_DDCVGA_SPEED                                                   0x16f0
++#define mmDC_I2C_DDCVGA_SETUP                                                   0x16f1
++#define mmDC_I2C_EDID_DETECT_CTRL                                               0x16f2
++#define mmDC_I2C_READ_REQUEST_INTERRUPT                                         0x16f3
++#define mmGENERIC_I2C_CONTROL                                                   0x16f4
++#define mmGENERIC_I2C_INTERRUPT_CONTROL                                         0x16f5
++#define mmGENERIC_I2C_STATUS                                                    0x16f6
++#define mmGENERIC_I2C_SPEED                                                     0x16f7
++#define mmGENERIC_I2C_SETUP                                                     0x16f8
++#define mmGENERIC_I2C_TRANSACTION                                               0x16f9
++#define mmGENERIC_I2C_DATA                                                      0x16fa
++#define mmGENERIC_I2C_PIN_SELECTION                                             0x16fb
++#define mmGENERIC_I2C_PIN_DEBUG                                                 0x16fc
++#define mmXDMA_MC_PCIE_CLIENT_CONFIG                                            0x3e0
++#define mmXDMA_LOCAL_SURFACE_TILING1                                            0x3e1
++#define mmXDMA_LOCAL_SURFACE_TILING2                                            0x3e2
++#define mmXDMA_INTERRUPT                                                        0x3e3
++#define mmXDMA_CLOCK_GATING_CNTL                                                0x3e4
++#define mmXDMA_MEM_POWER_CNTL                                                   0x3e6
++#define mmXDMA_IF_BIF_STATUS                                                    0x3e7
++#define mmXDMA_PERF_MEAS_STATUS                                                 0x3e8
++#define mmXDMA_IF_STATUS                                                        0x3e9
++#define mmXDMA_TEST_DEBUG_INDEX                                                 0x3ea
++#define mmXDMA_TEST_DEBUG_DATA                                                  0x3eb
++#define mmXDMA_RBBMIF_RDWR_CNTL                                                 0x3f8
++#define mmXDMA_PG_CONTROL                                                       0x3f9
++#define mmXDMA_PG_WDATA                                                         0x3fa
++#define mmXDMA_PG_STATUS                                                        0x3fb
++#define mmXDMA_AON_TEST_DEBUG_INDEX                                             0x3fc
++#define mmXDMA_AON_TEST_DEBUG_DATA                                              0x3fd
++#define mmXDMA_MSTR_CNTL                                                        0x3ec
++#define mmXDMA_MSTR_STATUS                                                      0x3ed
++#define mmXDMA_MSTR_MEM_CLIENT_CONFIG                                           0x3ee
++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR                                     0x3ef
++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH                                0x3f0
++#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH                                         0x3f1
++#define mmXDMA_MSTR_CMD_URGENT_CNTL                                             0x3f2
++#define mmXDMA_MSTR_MEM_URGENT_CNTL                                             0x3f3
++#define mmXDMA_MSTR_PCIE_NACK_STATUS                                            0x3f5
++#define mmXDMA_MSTR_MEM_NACK_STATUS                                             0x3f6
++#define mmXDMA_MSTR_VSYNC_GSL_CHECK                                             0x3f7
++#define mmXDMA_MSTR_PIPE_CNTL                                                   0x400
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL                                   0x400
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL                                   0x410
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL                                   0x420
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL                                   0x430
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL                                   0x440
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL                                   0x450
++#define mmXDMA_MSTR_READ_COMMAND                                                0x401
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND                                0x401
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND                                0x411
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND                                0x421
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND                                0x431
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND                                0x441
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND                                0x451
++#define mmXDMA_MSTR_CHANNEL_DIM                                                 0x402
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM                                 0x402
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM                                 0x412
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM                                 0x422
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM                                 0x432
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM                                 0x442
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM                                 0x452
++#define mmXDMA_MSTR_HEIGHT                                                      0x403
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT                                      0x403
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT                                      0x413
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT                                      0x423
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT                                      0x433
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT                                      0x443
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT                                      0x453
++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE                                         0x404
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x404
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x414
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x424
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x434
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x444
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x454
++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                                    0x405
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x405
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x415
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x425
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x435
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x445
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x455
++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS                                          0x406
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x406
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x416
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x426
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x436
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x446
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x456
++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                                     0x407
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x407
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x417
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x427
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x437
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x447
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x457
++#define mmXDMA_MSTR_CACHE_BASE_ADDR                                             0x408
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR                             0x408
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR                             0x418
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR                             0x428
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR                             0x438
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR                             0x448
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR                             0x458
++#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH                                        0x409
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x409
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x419
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x429
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x439
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x449
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x459
++#define mmXDMA_MSTR_CACHE                                                       0x40a
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE                                       0x40a
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE                                       0x41a
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE                                       0x42a
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE                                       0x43a
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE                                       0x44a
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE                                       0x45a
++#define mmXDMA_MSTR_CHANNEL_START                                               0x40b
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START                               0x40b
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START                               0x41b
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START                               0x42b
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START                               0x43b
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START                               0x44b
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START                               0x45b
++#define mmXDMA_MSTR_PERFMEAS_STATUS                                             0x40e
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS                             0x40e
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS                             0x41e
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS                             0x42e
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS                             0x43e
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS                             0x44e
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS                             0x45e
++#define mmXDMA_MSTR_PERFMEAS_CNTL                                               0x40f
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL                               0x40f
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL                               0x41f
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL                               0x42f
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL                               0x43f
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL                               0x44f
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL                               0x45f
++#define mmXDMA_SLV_CNTL                                                         0x460
++#define mmXDMA_SLV_MEM_CLIENT_CONFIG                                            0x461
++#define mmXDMA_SLV_SLS_PITCH                                                    0x462
++#define mmXDMA_SLV_READ_URGENT_CNTL                                             0x463
++#define mmXDMA_SLV_WRITE_URGENT_CNTL                                            0x464
++#define mmXDMA_SLV_WB_RATE_CNTL                                                 0x465
++#define mmXDMA_SLV_READ_LATENCY_MINMAX                                          0x466
++#define mmXDMA_SLV_READ_LATENCY_AVE                                             0x467
++#define mmXDMA_SLV_PCIE_NACK_STATUS                                             0x468
++#define mmXDMA_SLV_MEM_NACK_STATUS                                              0x469
++#define mmXDMA_SLV_RDRET_BUF_STATUS                                             0x46a
++#define mmXDMA_SLV_READ_LATENCY_TIMER                                           0x46b
++#define mmXDMA_SLV_FLIP_PENDING                                                 0x46c
++#define mmXDMA_SLV_CHANNEL_CNTL                                                 0x470
++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL                               0x470
++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL                               0x478
++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL                               0x480
++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL                               0x488
++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL                               0x490
++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL                               0x498
++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS                                           0x471
++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x471
++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x479
++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x481
++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x489
++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x491
++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x499
++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                                      0x472
++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x472
++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x47a
++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x482
++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x48a
++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x492
++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x49a
++
++#endif /* DCE_10_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
+new file mode 100644
+index 0000000..061560e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
+@@ -0,0 +1,1773 @@
++/*
++ * DCE_10_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_10_0_ENUM_H
++#define DCE_10_0_ENUM_H
++
++typedef enum DCIO_DC_GENERICA_SEL {
++	DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
++	DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
++	DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
++	DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
++	DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
++	DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
++	DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
++	DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
++	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
++	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
++	DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
++	DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
++	DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
++	DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
++	DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
++	DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
++	DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
++	DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
++} DCIO_DC_GENERICA_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
++	DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
++	DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
++	DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
++	DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
++	DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
++	DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
++} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
++	DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
++	DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
++	DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
++	DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
++	DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
++	DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
++} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
++	DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
++	DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
++	DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
++	DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
++	DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
++	DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
++} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
++	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
++	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
++	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
++	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
++	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
++	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
++} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
++typedef enum DCIO_DC_GENERICB_SEL {
++	DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
++	DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
++	DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
++	DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
++	DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
++	DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
++	DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
++	DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
++	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
++	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
++	DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
++	DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
++	DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
++	DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
++	DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
++	DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
++} DCIO_DC_GENERICB_SEL;
++typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
++	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,
++} DCIO_DC_PAD_EXTERN_SIG_SEL;
++typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
++	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA                 = 0x0,
++	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE       = 0x1,
++	DCIO_MVP_PIXEL_SRC_STATUS_CRTC                   = 0x2,
++	DCIO_MVP_PIXEL_SRC_STATUS_LB                     = 0x3,
++} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
++typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
++	DCIO_HSYNCA_OUTPUT_SEL_DISABLE                   = 0x0,
++	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
++	DCIO_HSYNCA_OUTPUT_SEL_PPLL2                     = 0x2,
++	DCIO_HSYNCA_OUTPUT_SEL_RESERVED                  = 0x3,
++} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
++typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
++	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE                = 0x0,
++	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1                  = 0x1,
++	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
++	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3        = 0x3,
++} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
++typedef enum DCIO_DC_GPIO_VIP_DEBUG {
++	DCIO_DC_GPIO_VIP_DEBUG_NORMAL                    = 0x0,
++	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG                    = 0x1,
++} DCIO_DC_GPIO_VIP_DEBUG;
++typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
++	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL                  = 0x0,
++	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF                = 0x1,
++	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2         = 0x2,
++	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3         = 0x3,
++} DCIO_DC_GPIO_MACRO_DEBUG;
++typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
++	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL       = 0x0,
++	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP         = 0x1,
++} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
++typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
++	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS            = 0x0,
++	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE            = 0x1,
++} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
++typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
++	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL                 = 0x0,
++	DCIO_DPRX_LOOPBACK_ENABLE_LOOP                   = 0x1,
++} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
++typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
++} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
++typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
++	DCIO_UNIPHY_CHANNEL_NO_INVERSION                 = 0x0,
++	DCIO_UNIPHY_CHANNEL_INVERTED                     = 0x1,
++} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
++typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW        = 0x0,
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW           = 0x1,
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
++} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
++typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0              = 0x0,
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1              = 0x1,
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2              = 0x2,
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3              = 0x3,
++} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
++typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
++	DCIO_VIP_MUX_EN_DVO                              = 0x0,
++	DCIO_VIP_MUX_EN_VIP                              = 0x1,
++} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
++typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
++	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT                = 0x0,
++	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
++} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
++typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
++	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT                = 0x0,
++	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
++} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
++	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
++	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
++	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF           = 0x0,
++	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON            = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
++	DCIO_LVTMA_SYNCEN_POL_NON_INVERT                 = 0x0,
++	DCIO_LVTMA_SYNCEN_POL_INVERT                     = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
++	DCIO_LVTMA_DIGON_OFF                             = 0x0,
++	DCIO_LVTMA_DIGON_ON                              = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
++	DCIO_LVTMA_DIGON_POL_NON_INVERT                  = 0x0,
++	DCIO_LVTMA_DIGON_POL_INVERT                      = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
++	DCIO_LVTMA_BLON_OFF                              = 0x0,
++	DCIO_LVTMA_BLON_ON                               = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
++	DCIO_LVTMA_BLON_POL_NON_INVERT                   = 0x0,
++	DCIO_LVTMA_BLON_POL_INVERT                       = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
++typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
++	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON              = 0x0,
++	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE          = 0x1,
++} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
++typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
++	DCIO_BL_PWM_FRACTIONAL_DISABLE                   = 0x0,
++	DCIO_BL_PWM_FRACTIONAL_ENABLE                    = 0x1,
++} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
++typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
++	DCIO_BL_PWM_DISABLE                              = 0x0,
++	DCIO_BL_PWM_ENABLE                               = 0x1,
++} DCIO_BL_PWM_CNTL_BL_PWM_EN;
++typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL       = 0x0,
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1       = 0x1,
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2       = 0x2,
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3       = 0x3,
++} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
++typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
++	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE              = 0x0,
++	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE               = 0x1,
++} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
++typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
++	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL      = 0x0,
++	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM         = 0x1,
++} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
++typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
++	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE                = 0x0,
++	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE                 = 0x1,
++} DCIO_BL_PWM_GRP1_REG_LOCK;
++typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
++	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE   = 0x0,
++	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE    = 0x1,
++} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
++typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
++} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
++typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
++	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
++	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
++} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
++typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
++	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE       = 0x0,
++	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE      = 0x1,
++} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
++typedef enum DCIO_GSL_SEL {
++	DCIO_GSL_SEL_GROUP_0                             = 0x0,
++	DCIO_GSL_SEL_GROUP_1                             = 0x1,
++	DCIO_GSL_SEL_GROUP_2                             = 0x2,
++} DCIO_GSL_SEL;
++typedef enum DCIO_GENLK_CLK_GSL_MASK {
++	DCIO_GENLK_CLK_GSL_MASK_NO                       = 0x0,
++	DCIO_GENLK_CLK_GSL_MASK_TIMING                   = 0x1,
++	DCIO_GENLK_CLK_GSL_MASK_STEREO                   = 0x2,
++} DCIO_GENLK_CLK_GSL_MASK;
++typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
++	DCIO_GENLK_VSYNC_GSL_MASK_NO                     = 0x0,
++	DCIO_GENLK_VSYNC_GSL_MASK_TIMING                 = 0x1,
++	DCIO_GENLK_VSYNC_GSL_MASK_STEREO                 = 0x2,
++} DCIO_GENLK_VSYNC_GSL_MASK;
++typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
++	DCIO_SWAPLOCK_A_GSL_MASK_NO                      = 0x0,
++	DCIO_SWAPLOCK_A_GSL_MASK_TIMING                  = 0x1,
++	DCIO_SWAPLOCK_A_GSL_MASK_STEREO                  = 0x2,
++} DCIO_SWAPLOCK_A_GSL_MASK;
++typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
++	DCIO_SWAPLOCK_B_GSL_MASK_NO                      = 0x0,
++	DCIO_SWAPLOCK_B_GSL_MASK_TIMING                  = 0x1,
++	DCIO_SWAPLOCK_B_GSL_MASK_STEREO                  = 0x2,
++} DCIO_SWAPLOCK_B_GSL_MASK;
++typedef enum DCIO_GSL_VSYNC_SEL {
++	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
++	DCIO_GSL_VSYNC_SEL_PIPE1                         = 0x1,
++	DCIO_GSL_VSYNC_SEL_PIPE2                         = 0x2,
++	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
++	DCIO_GSL_VSYNC_SEL_PIPE4                         = 0x4,
++	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
++} DCIO_GSL_VSYNC_SEL;
++typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
++	DCIO_GSL0_TIMING_SYNC_SEL_PIPE                   = 0x0,
++	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
++	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
++	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
++	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
++} DCIO_GSL0_TIMING_SYNC_SEL;
++typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
++} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
++typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
++	DCIO_GSL1_TIMING_SYNC_SEL_PIPE                   = 0x0,
++	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
++	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
++	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
++	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
++} DCIO_GSL1_TIMING_SYNC_SEL;
++typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
++} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
++typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
++	DCIO_GSL2_TIMING_SYNC_SEL_PIPE                   = 0x0,
++	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
++	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
++	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
++	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
++} DCIO_GSL2_TIMING_SYNC_SEL;
++typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
++} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
++typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
++	DCIO_GPU_TIMER_START_0_END_27                    = 0x0,
++	DCIO_GPU_TIMER_START_1_END_28                    = 0x1,
++	DCIO_GPU_TIMER_START_2_END_29                    = 0x2,
++	DCIO_GPU_TIMER_START_3_END_30                    = 0x3,
++	DCIO_GPU_TIMER_START_4_END_31                    = 0x4,
++	DCIO_GPU_TIMER_START_6_END_33                    = 0x5,
++	DCIO_GPU_TIMER_START_8_END_35                    = 0x6,
++	DCIO_GPU_TIMER_START_10_END_37                   = 0x7,
++} DCIO_DC_GPU_TIMER_START_POSITION;
++typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
++	DCIO_TEST_CLK_SEL_DISPCLK                        = 0x0,
++	DCIO_TEST_CLK_SEL_GATED_DISPCLK                  = 0x1,
++	DCIO_TEST_CLK_SEL_SCLK                           = 0x2,
++} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
++typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
++	DCIO_DISPCLK_R_DCIO_GATE_DISABLE                 = 0x0,
++	DCIO_DISPCLK_R_DCIO_GATE_ENABLE                  = 0x1,
++} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
++typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS {
++	DCIO_DISPCLK_R_DCIO_RAMP_DISABLE                 = 0x0,
++	DCIO_DISPCLK_R_DCIO_RAMP_ENABLE                  = 0x1,
++} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS;
++typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
++	DCIO_EXT_VSYNC_MUX_SWAPLOCKB                     = 0x0,
++	DCIO_EXT_VSYNC_MUX_CRTC0                         = 0x1,
++	DCIO_EXT_VSYNC_MUX_CRTC1                         = 0x2,
++	DCIO_EXT_VSYNC_MUX_CRTC2                         = 0x3,
++	DCIO_EXT_VSYNC_MUX_CRTC3                         = 0x4,
++	DCIO_EXT_VSYNC_MUX_CRTC4                         = 0x5,
++	DCIO_EXT_VSYNC_MUX_CRTC5                         = 0x6,
++	DCIO_EXT_VSYNC_MUX_GENERICB                      = 0x7,
++} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
++typedef enum DCIO_DCO_EXT_VSYNC_MASK {
++	DCIO_EXT_VSYNC_MASK_NONE                         = 0x0,
++	DCIO_EXT_VSYNC_MASK_PIPE0                        = 0x1,
++	DCIO_EXT_VSYNC_MASK_PIPE1                        = 0x2,
++	DCIO_EXT_VSYNC_MASK_PIPE2                        = 0x3,
++	DCIO_EXT_VSYNC_MASK_PIPE3                        = 0x4,
++	DCIO_EXT_VSYNC_MASK_PIPE4                        = 0x5,
++	DCIO_EXT_VSYNC_MASK_PIPE5                        = 0x6,
++	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE               = 0x7,
++} DCIO_DCO_EXT_VSYNC_MASK;
++typedef enum DCIO_DBG_OUT_PIN_SEL {
++	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT                   = 0x0,
++	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT                  = 0x1,
++} DCIO_DBG_OUT_PIN_SEL;
++typedef enum DCIO_DBG_OUT_12BIT_SEL {
++	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT                 = 0x0,
++	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT                 = 0x1,
++	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT                = 0x2,
++	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE                  = 0x3,
++} DCIO_DBG_OUT_12BIT_SEL;
++typedef enum DCIO_DSYNC_SOFT_RESET {
++	DCIO_DSYNC_SOFT_RESET_DEASSERT                   = 0x0,
++	DCIO_DSYNC_SOFT_RESET_ASSERT                     = 0x1,
++} DCIO_DSYNC_SOFT_RESET;
++typedef enum DCIO_DACA_SOFT_RESET {
++	DCIO_DACA_SOFT_RESET_DEASSERT                    = 0x0,
++	DCIO_DACA_SOFT_RESET_ASSERT                      = 0x1,
++} DCIO_DACA_SOFT_RESET;
++typedef enum DCIO_DCRXPHY_SOFT_RESET {
++	DCIO_DCRXPHY_SOFT_RESET_DEASSERT                 = 0x0,
++	DCIO_DCRXPHY_SOFT_RESET_ASSERT                   = 0x1,
++} DCIO_DCRXPHY_SOFT_RESET;
++typedef enum DCIO_DPHY_LANE_SEL {
++	DCIO_DPHY_LANE_SEL_LANE0                         = 0x0,
++	DCIO_DPHY_LANE_SEL_LANE1                         = 0x1,
++	DCIO_DPHY_LANE_SEL_LANE2                         = 0x2,
++	DCIO_DPHY_LANE_SEL_LANE3                         = 0x3,
++} DCIO_DPHY_LANE_SEL;
++typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE     = 0x0,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE     = 0x1,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE     = 0x2,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE     = 0x3,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE     = 0x4,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE     = 0x5,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE     = 0x6,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE     = 0x7,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE     = 0x8,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE     = 0x9,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE     = 0xa,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE     = 0xb,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP       = 0xc,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP       = 0xd,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP       = 0xe,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP       = 0xf,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP       = 0x10,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP       = 0x11,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP       = 0x12,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP       = 0x13,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP       = 0x14,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP       = 0x15,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP       = 0x16,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP       = 0x17,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM    = 0x18,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM    = 0x19,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM    = 0x1a,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM    = 0x1b,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM    = 0x1c,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM    = 0x1d,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM    = 0x1e,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM    = 0x1f,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM    = 0x20,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM    = 0x21,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM    = 0x22,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM    = 0x23,
++} DCIO_DC_GPU_TIMER_READ_SELECT;
++typedef enum DCIO_IMPCAL_STEP_DELAY {
++	DCIO_IMPCAL_STEP_DELAY_1us                       = 0x0,
++	DCIO_IMPCAL_STEP_DELAY_2us                       = 0x1,
++	DCIO_IMPCAL_STEP_DELAY_3us                       = 0x2,
++	DCIO_IMPCAL_STEP_DELAY_4us                       = 0x3,
++	DCIO_IMPCAL_STEP_DELAY_5us                       = 0x4,
++	DCIO_IMPCAL_STEP_DELAY_6us                       = 0x5,
++	DCIO_IMPCAL_STEP_DELAY_7us                       = 0x6,
++	DCIO_IMPCAL_STEP_DELAY_8us                       = 0x7,
++	DCIO_IMPCAL_STEP_DELAY_9us                       = 0x8,
++	DCIO_IMPCAL_STEP_DELAY_10us                      = 0x9,
++	DCIO_IMPCAL_STEP_DELAY_11us                      = 0xa,
++	DCIO_IMPCAL_STEP_DELAY_12us                      = 0xb,
++	DCIO_IMPCAL_STEP_DELAY_13us                      = 0xc,
++	DCIO_IMPCAL_STEP_DELAY_14us                      = 0xd,
++	DCIO_IMPCAL_STEP_DELAY_15us                      = 0xe,
++	DCIO_IMPCAL_STEP_DELAY_16us                      = 0xf,
++} DCIO_IMPCAL_STEP_DELAY;
++typedef enum DCIO_UNIPHY_IMPCAL_SEL {
++	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE               = 0x0,
++	DCIO_UNIPHY_IMPCAL_SEL_BINARY                    = 0x1,
++} DCIO_UNIPHY_IMPCAL_SEL;
++typedef enum DCIOCHIP_HPD_SEL {
++	DCIOCHIP_HPD_SEL_ASYNC                           = 0x0,
++	DCIOCHIP_HPD_SEL_CLOCKED                         = 0x1,
++} DCIOCHIP_HPD_SEL;
++typedef enum DCIOCHIP_PAD_MODE {
++	DCIOCHIP_PAD_MODE_DDC                            = 0x0,
++	DCIOCHIP_PAD_MODE_DP                             = 0x1,
++} DCIOCHIP_PAD_MODE;
++typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
++	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C                   = 0x0,
++	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX                   = 0x1,
++} DCIOCHIP_AUXSLAVE_PAD_MODE;
++typedef enum DCIOCHIP_INVERT {
++	DCIOCHIP_POL_NON_INVERT                          = 0x0,
++	DCIOCHIP_POL_INVERT                              = 0x1,
++} DCIOCHIP_INVERT;
++typedef enum DCIOCHIP_PD_EN {
++	DCIOCHIP_PD_EN_NOTALLOW                          = 0x0,
++	DCIOCHIP_PD_EN_ALLOW                             = 0x1,
++} DCIOCHIP_PD_EN;
++typedef enum DCIOCHIP_GPIO_MASK_EN {
++	DCIOCHIP_GPIO_MASK_EN_HARDWARE                   = 0x0,
++	DCIOCHIP_GPIO_MASK_EN_SOFTWARE                   = 0x1,
++} DCIOCHIP_GPIO_MASK_EN;
++typedef enum DCIOCHIP_MASK {
++	DCIOCHIP_MASK_DISABLE                            = 0x0,
++	DCIOCHIP_MASK_ENABLE                             = 0x1,
++} DCIOCHIP_MASK;
++typedef enum DCIOCHIP_GPIO_I2C_MASK {
++	DCIOCHIP_GPIO_I2C_MASK_DISABLE                   = 0x0,
++	DCIOCHIP_GPIO_I2C_MASK_ENABLE                    = 0x1,
++} DCIOCHIP_GPIO_I2C_MASK;
++typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
++	DCIOCHIP_GPIO_I2C_DRIVE_LOW                      = 0x0,
++	DCIOCHIP_GPIO_I2C_DRIVE_HIGH                     = 0x1,
++} DCIOCHIP_GPIO_I2C_DRIVE;
++typedef enum DCIOCHIP_GPIO_I2C_EN {
++	DCIOCHIP_GPIO_I2C_DISABLE                        = 0x0,
++	DCIOCHIP_GPIO_I2C_ENABLE                         = 0x1,
++} DCIOCHIP_GPIO_I2C_EN;
++typedef enum DCIOCHIP_MASK_4BIT {
++	DCIOCHIP_MASK_4BIT_DISABLE                       = 0x0,
++	DCIOCHIP_MASK_4BIT_ENABLE                        = 0xf,
++} DCIOCHIP_MASK_4BIT;
++typedef enum DCIOCHIP_ENABLE_4BIT {
++	DCIOCHIP_4BIT_DISABLE                            = 0x0,
++	DCIOCHIP_4BIT_ENABLE                             = 0xf,
++} DCIOCHIP_ENABLE_4BIT;
++typedef enum DCIOCHIP_MASK_5BIT {
++	DCIOCHIP_MASIK_5BIT_DISABLE                      = 0x0,
++	DCIOCHIP_MASIK_5BIT_ENABLE                       = 0x1f,
++} DCIOCHIP_MASK_5BIT;
++typedef enum DCIOCHIP_ENABLE_5BIT {
++	DCIOCHIP_5BIT_DISABLE                            = 0x0,
++	DCIOCHIP_5BIT_ENABLE                             = 0x1f,
++} DCIOCHIP_ENABLE_5BIT;
++typedef enum DCIOCHIP_MASK_2BIT {
++	DCIOCHIP_MASK_2BIT_DISABLE                       = 0x0,
++	DCIOCHIP_MASK_2BIT_ENABLE                        = 0x3,
++} DCIOCHIP_MASK_2BIT;
++typedef enum DCIOCHIP_ENABLE_2BIT {
++	DCIOCHIP_2BIT_DISABLE                            = 0x0,
++	DCIOCHIP_2BIT_ENABLE                             = 0x3,
++} DCIOCHIP_ENABLE_2BIT;
++typedef enum DCIOCHIP_REF_27_SRC_SEL {
++	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER             = 0x0,
++	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER      = 0x1,
++	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS              = 0x2,
++	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS       = 0x3,
++} DCIOCHIP_REF_27_SRC_SEL;
++typedef enum DCIOCHIP_DVO_VREFPON {
++	DCIOCHIP_DVO_VREFPON_DISABLE                     = 0x0,
++	DCIOCHIP_DVO_VREFPON_ENABLE                      = 0x1,
++} DCIOCHIP_DVO_VREFPON;
++typedef enum DCIOCHIP_DVO_VREFSEL {
++	DCIOCHIP_DVO_VREFSEL_ONCHIP                      = 0x0,
++	DCIOCHIP_DVO_VREFSEL_EXTERNAL                    = 0x1,
++} DCIOCHIP_DVO_VREFSEL;
++typedef enum COL_MAN_UPDATE_LOCK {
++	COL_MAN_UPDATE_UNLOCKED                          = 0x0,
++	COL_MAN_UPDATE_LOCKED                            = 0x1,
++} COL_MAN_UPDATE_LOCK;
++typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
++	COL_MAN_MULTIPLE_UPDATE                          = 0x0,
++	COL_MAN_MULTIPLE_UPDAT_EDISABLE                  = 0x1,
++} COL_MAN_DISABLE_MULTIPLE_UPDATE;
++typedef enum COL_MAN_INPUTCSC_MODE {
++	INPUTCSC_MODE_BYPASS                             = 0x0,
++	INPUTCSC_MODE_A                                  = 0x1,
++	INPUTCSC_MODE_B                                  = 0x2,
++	INPUTCSC_MODE_UNITY                              = 0x3,
++} COL_MAN_INPUTCSC_MODE;
++typedef enum COL_MAN_INPUTCSC_TYPE {
++	INPUTCSC_TYPE_12_0                               = 0x0,
++	INPUTCSC_TYPE_10_2                               = 0x1,
++	INPUTCSC_TYPE_8_4                                = 0x2,
++} COL_MAN_INPUTCSC_TYPE;
++typedef enum COL_MAN_INPUTCSC_CONVERT {
++	INPUTCSC_ROUND                                   = 0x0,
++	INPUTCSC_TRUNCATE                                = 0x1,
++} COL_MAN_INPUTCSC_CONVERT;
++typedef enum COL_MAN_PRESCALE_MODE {
++	PRESCALE_MODE_BYPASS                             = 0x0,
++	PRESCALE_MODE_PROGRAM                            = 0x1,
++	PRESCALE_MODE_UNITY                              = 0x2,
++} COL_MAN_PRESCALE_MODE;
++typedef enum COL_MAN_OUTPUT_CSC_MODE {
++	COL_MAN_OUTPUT_CSC_BYPASS                        = 0x0,
++	COL_MAN_OUTPUT_CSC_RGB                           = 0x1,
++	COL_MAN_OUTPUT_CSC_YCrCb601                      = 0x2,
++	COL_MAN_OUTPUT_CSC_YCrCb709                      = 0x3,
++	COL_MAN_OUTPUT_CSC_A                             = 0x4,
++	COL_MAN_OUTPUT_CSC_B                             = 0x5,
++} COL_MAN_OUTPUT_CSC_MODE;
++typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
++	DENORM_CLAMP_CONTROL_UNITY                       = 0x0,
++	DENORM_CLAMP_CONTROL_8                           = 0x1,
++	DENORM_CLAMP_CONTROL_10                          = 0x2,
++	DENORM_CLAMP_CONTROL_12                          = 0x3,
++} COL_MAN_DENORM_CLAMP_CONTROL;
++typedef enum COL_MAN_GAMMA_CORR_CONTROL {
++	GAMMA_CORR_CONTROL_BYPASS                        = 0x0,
++	GAMMA_CORR_CONTROL_A                             = 0x1,
++	GAMMA_CORR_CONTROL_B                             = 0x2,
++} COL_MAN_GAMMA_CORR_CONTROL;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
++	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
++	DBG_CLIENT_BLKID_bci0                            = 0xe,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
++	DBG_CLIENT_BLKID_cb100                           = 0x10,
++	DBG_CLIENT_BLKID_cb001                           = 0x11,
++	DBG_CLIENT_BLKID_mcd4                            = 0x12,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
++	DBG_CLIENT_BLKID_cb101                           = 0x14,
++	DBG_CLIENT_BLKID_sx10                            = 0x15,
++	DBG_CLIENT_BLKID_cb301                           = 0x16,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
++	DBG_CLIENT_BLKID_scf1                            = 0x1c,
++	DBG_CLIENT_BLKID_sx20                            = 0x1d,
++	DBG_CLIENT_BLKID_spim1                           = 0x1e,
++	DBG_CLIENT_BLKID_pa10                            = 0x1f,
++	DBG_CLIENT_BLKID_pa00                            = 0x20,
++	DBG_CLIENT_BLKID_gmcon                           = 0x21,
++	DBG_CLIENT_BLKID_mcb                             = 0x22,
++	DBG_CLIENT_BLKID_vgt0                            = 0x23,
++	DBG_CLIENT_BLKID_pc0                             = 0x24,
++	DBG_CLIENT_BLKID_bci2                            = 0x25,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
++	DBG_CLIENT_BLKID_spim3                           = 0x27,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
++	DBG_CLIENT_BLKID_cb000                           = 0x2e,
++	DBG_CLIENT_BLKID_spim0                           = 0x2f,
++	DBG_CLIENT_BLKID_mcc2                            = 0x30,
++	DBG_CLIENT_BLKID_ds0                             = 0x31,
++	DBG_CLIENT_BLKID_srbm                            = 0x32,
++	DBG_CLIENT_BLKID_ih                              = 0x33,
++	DBG_CLIENT_BLKID_sem                             = 0x34,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
++	DBG_CLIENT_BLKID_hdp                             = 0x37,
++	DBG_CLIENT_BLKID_acp_0                           = 0x38,
++	DBG_CLIENT_BLKID_acp_1                           = 0x39,
++	DBG_CLIENT_BLKID_cb200                           = 0x3a,
++	DBG_CLIENT_BLKID_scf3                            = 0x3b,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
++	DBG_CLIENT_BLKID_bci3                            = 0x41,
++	DBG_CLIENT_BLKID_mcd0                            = 0x42,
++	DBG_CLIENT_BLKID_pa11                            = 0x43,
++	DBG_CLIENT_BLKID_pa01                            = 0x44,
++	DBG_CLIENT_BLKID_cb201                           = 0x45,
++	DBG_CLIENT_BLKID_spim2                           = 0x46,
++	DBG_CLIENT_BLKID_vgt2                            = 0x47,
++	DBG_CLIENT_BLKID_pc2                             = 0x48,
++	DBG_CLIENT_BLKID_smu_0                           = 0x49,
++	DBG_CLIENT_BLKID_smu_1                           = 0x4a,
++	DBG_CLIENT_BLKID_smu_2                           = 0x4b,
++	DBG_CLIENT_BLKID_cb1                             = 0x4c,
++	DBG_CLIENT_BLKID_ia0                             = 0x4d,
++	DBG_CLIENT_BLKID_wd                              = 0x4e,
++	DBG_CLIENT_BLKID_ia1                             = 0x4f,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
++	DBG_CLIENT_BLKID_scf0                            = 0x51,
++	DBG_CLIENT_BLKID_vgt1                            = 0x52,
++	DBG_CLIENT_BLKID_pc1                             = 0x53,
++	DBG_CLIENT_BLKID_cb0                             = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
++	DBG_CLIENT_BLKID_vgt3                            = 0x7a,
++	DBG_CLIENT_BLKID_pc3                             = 0x7b,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
++	DBG_CLIENT_BLKID_cb300                           = 0x84,
++	DBG_CLIENT_BLKID_mcd1                            = 0x85,
++	DBG_CLIENT_BLKID_sx00                            = 0x86,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
++	DBG_CLIENT_BLKID_mcc3                            = 0x89,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
++	DBG_CLIENT_BLKID_gck                             = 0x8c,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8d,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
++	DBG_CLIENT_BLKID_rlc                             = 0x90,
++	DBG_CLIENT_BLKID_grbm                            = 0x91,
++	DBG_CLIENT_BLKID_sammsp                          = 0x92,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x93,
++	DBG_CLIENT_BLKID_dci_0                           = 0x94,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* DCE_10_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h
+new file mode 100644
+index 0000000..8a75eb9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h
+@@ -0,0 +1,16647 @@
++/*
++ * DCE_10_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_10_0_SH_MASK_H
++#define DCE_10_0_SH_MASK_H
++
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
++#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
++#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
++#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
++#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
++#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
++#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1
++#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
++#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1
++#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
++#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000
++#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf
++#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3
++#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc
++#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
++#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300
++#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00
++#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK 0x80000
++#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT 0x13
++#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK 0x100000
++#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
++#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc
++#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30
++#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00
++#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000
++#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000
++#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000
++#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
++#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000
++#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000
++#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK 0x1000000
++#define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT 0x18
++#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
++#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
++#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
++#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
++#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
++#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
++#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
++#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
++#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
++#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
++#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
++#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
++#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
++#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
++#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
++#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
++#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
++#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100
++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8
++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
++#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
++#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
++#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
++#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
++#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
++#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
++#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
++#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
++#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
++#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
++#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000
++#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000
++#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000
++#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000
++#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000
++#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000
++#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
++#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
++#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
++#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
++#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
++#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
++#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
++#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
++#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
++#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
++#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
++#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
++#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
++#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
++#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
++#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
++#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
++#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0
++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a
++#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
++#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc
++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2
++#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
++#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1
++#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define PERFMON_HI__PERFMON_HI_MASK 0xffff
++#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
++#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
++#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
++#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1
++#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
++#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2
++#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf
++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100
++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff
++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1
++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff
++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40
++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
++#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
++#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
++#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80
++#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
++#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000
++#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000
++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000
++#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
++#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
++#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
++#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
++#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
++#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
++#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
++#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
++#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
++#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
++#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
++#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
++#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
++#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
++#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
++#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
++#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
++#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
++#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8
++#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7
++#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000
++#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000
++#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000
++#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000
++#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
++#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000
++#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
++#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000
++#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
++#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7
++#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
++#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000
++#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000
++#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
++#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000
++#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
++#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17
++#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000
++#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18
++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
++#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
++#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
++#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
++#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf
++#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
++#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0
++#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
++#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00
++#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
++#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000
++#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
++#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000
++#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
++#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000
++#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
++#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000
++#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
++#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000
++#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
++#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
++#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
++#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
++#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
++#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
++#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
++#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
++#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
++#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
++#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
++#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
++#define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD_MASK 0x100
++#define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD__SHIFT 0x8
++#define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL_MASK 0x1e00
++#define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL__SHIFT 0x9
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
++#define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK 0xfff00000
++#define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT 0x14
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x7
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
++#define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK 0x8
++#define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT 0x3
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10
++#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40
++#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6
++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100
++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600
++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000
++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000
++#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000
++#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10
++#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000
++#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12
++#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000
++#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000
++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000
++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000
++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000
++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3
++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc
++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10
++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60
++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180
++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200
++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00
++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000
++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000
++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000
++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000
++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000
++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000
++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000
++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
++#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000
++#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000
++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000
++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000
++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000
++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000
++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000
++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
++#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
++#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
++#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
++#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
++#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
++#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400
++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800
++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc
++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000
++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000
++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000
++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1
++#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0
++#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0
++#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4
++#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00
++#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define DC_GENERICA__GENERICA_EN_MASK 0x1
++#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
++#define DC_GENERICA__GENERICA_SEL_MASK 0xf80
++#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_GENERICB__GENERICB_EN_MASK 0x1
++#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
++#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
++#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000
++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000
++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
++#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0
++#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
++#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00
++#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000
++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11
++#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
++#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
++#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
++#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK 0x100
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT 0x8
++#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
++#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1
++#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0
++#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10
++#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4
++#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300
++#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8
++#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000
++#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc
++#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1
++#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3
++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc
++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30
++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0
++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
++#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
++#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
++#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17
++#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
++#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
++#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
++#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
++#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
++#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
++#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
++#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
++#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
++#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
++#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
++#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
++#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
++#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
++#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
++#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
++#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
++#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
++#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
++#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
++#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
++#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
++#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
++#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
++#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
++#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
++#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
++#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff
++#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0
++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
++#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
++#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
++#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
++#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
++#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
++#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
++#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
++#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
++#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
++#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
++#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
++#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
++#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40
++#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
++#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
++#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
++#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf
++#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
++#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0
++#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
++#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00
++#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
++#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000
++#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
++#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000
++#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
++#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000
++#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
++#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000
++#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
++#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000
++#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
++#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000
++#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
++#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
++#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
++#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
++#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
++#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
++#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
++#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
++#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
++#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define GRPH_CONTROL__GRPH_Z_MASK 0x30
++#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
++#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
++#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
++#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
++#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
++#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
++#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
++#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
++#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
++#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
++#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
++#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
++#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
++#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
++#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3
++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30
++#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
++#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
++#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2
++#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define OVL_ENABLE__OVL_ENABLE_MASK 0x1
++#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0
++#define OVL_ENABLE__OVLSCL_EN_MASK 0x100
++#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8
++#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3
++#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0
++#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc
++#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2
++#define OVL_CONTROL1__OVL_Z_MASK 0x30
++#define OVL_CONTROL1__OVL_Z__SHIFT 0x4
++#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0
++#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6
++#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700
++#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8
++#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800
++#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb
++#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000
++#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd
++#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000
++#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12
++#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000
++#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14
++#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000
++#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18
++#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000
++#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19
++#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000
++#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e
++#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1
++#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0
++#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3
++#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0
++#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30
++#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4
++#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0
++#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6
++#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300
++#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8
++#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00
++#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa
++#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1
++#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0
++#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00
++#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8
++#define OVL_PITCH__OVL_PITCH_MASK 0x7fff
++#define OVL_PITCH__OVL_PITCH__SHIFT 0x0
++#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff
++#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0
++#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff
++#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0
++#define OVL_START__OVL_Y_START_MASK 0x3fff
++#define OVL_START__OVL_Y_START__SHIFT 0x0
++#define OVL_START__OVL_X_START_MASK 0x3fff0000
++#define OVL_START__OVL_X_START__SHIFT 0x10
++#define OVL_END__OVL_Y_END_MASK 0x7fff
++#define OVL_END__OVL_Y_END__SHIFT 0x0
++#define OVL_END__OVL_X_END_MASK 0x7fff0000
++#define OVL_END__OVL_X_END__SHIFT 0x10
++#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1
++#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0
++#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2
++#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1
++#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000
++#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10
++#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
++#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1
++#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0
++#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70
++#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4
++#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700
++#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf
++#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
++#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200
++#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9
++#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
++#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000
++#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10
++#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000
++#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000
++#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000
++#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10
++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30
++#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4
++#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
++#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
++#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
++#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
++#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
++#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
++#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
++#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
++#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
++#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
++#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
++#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
++#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
++#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
++#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define KEY_CONTROL__KEY_SELECT_MASK 0x1
++#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0
++#define KEY_CONTROL__KEY_MODE_MASK 0x6
++#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000
++#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c
++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
++#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
++#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
++#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
++#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30
++#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4
++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30
++#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff
++#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
++#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00
++#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
++#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000
++#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define CUR_CONTROL__CURSOR_EN_MASK 0x1
++#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
++#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
++#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
++#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
++#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
++#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
++#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
++#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
++#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
++#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
++#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
++#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
++#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
++#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
++#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
++#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
++#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000
++#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000
++#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
++#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
++#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
++#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
++#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
++#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
++#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
++#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
++#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
++#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
++#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
++#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300
++#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13
++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
++#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
++#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
++#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70
++#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4
++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
++#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG_FE_CNTL__DIG_START_MASK 0x400
++#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000
++#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000
++#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4
++#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100
++#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8
++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
++#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8
++#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
++#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
++#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
++#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
++#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
++#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
++#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
++#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
++#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
++#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
++#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
++#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
++#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
++#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
++#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
++#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
++#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
++#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
++#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
++#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
++#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
++#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1
++#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2
++#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4
++#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
++#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
++#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
++#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
++#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
++#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
++#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
++#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
++#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
++#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
++#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
++#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
++#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK_MASK 0x1
++#define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN_MASK 0x2
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN__SHIFT 0x1
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN_MASK 0x4
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN__SHIFT 0x2
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN_MASK 0x8
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN__SHIFT 0x3
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN_MASK 0xff0
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN__SHIFT 0x4
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN_MASK 0x1000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN__SHIFT 0xc
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN_MASK 0x2000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN__SHIFT 0xd
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT_MASK 0x3fc000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT__SHIFT 0xe
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE_MASK 0x400000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE__SHIFT 0x16
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT_MASK 0x800000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT__SHIFT 0x17
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT_MASK 0x1000000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT__SHIFT 0x18
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT_MASK 0x2000000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT__SHIFT 0x19
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT_MASK 0x4000000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT__SHIFT 0x1a
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT_MASK 0x8000000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT__SHIFT 0x1b
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT_MASK 0x10000000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT__SHIFT 0x1c
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT_MASK 0x20000000
++#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT__SHIFT 0x1d
++#define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK_MASK 0x1
++#define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN_MASK 0x2
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN__SHIFT 0x1
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN_MASK 0x4
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN__SHIFT 0x2
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN_MASK 0x8
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN__SHIFT 0x3
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN_MASK 0xff0
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN__SHIFT 0x4
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB_MASK 0x1ff000
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB__SHIFT 0xc
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX_MASK 0x200000
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX__SHIFT 0x15
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX_MASK 0xffc00000
++#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX__SHIFT 0x16
++#define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK_MASK 0x1
++#define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN_MASK 0x2
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN__SHIFT 0x1
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN_MASK 0xffc
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN__SHIFT 0x2
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN_MASK 0x1000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN__SHIFT 0xc
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN_MASK 0x2000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN__SHIFT 0xd
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN_MASK 0x4000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN__SHIFT 0xe
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN_MASK 0x8000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN__SHIFT 0xf
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN_MASK 0x100000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN__SHIFT 0x14
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN_MASK 0x200000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN__SHIFT 0x15
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT_MASK 0xffc00000
++#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT__SHIFT 0x16
++#define TMDS_DEBUG7__DBG_DIG_TMDS7_MASK 0xffffffff
++#define TMDS_DEBUG7__DBG_DIG_TMDS7__SHIFT 0x0
++#define TMDS_DEBUG8__DBG_DIG_TMDS8_MASK 0xffffffff
++#define TMDS_DEBUG8__DBG_DIG_TMDS8__SHIFT 0x0
++#define TMDS_DEBUG9__DBG_DIG_TMDS9_MASK 0xffffffff
++#define TMDS_DEBUG9__DBG_DIG_TMDS9__SHIFT 0x0
++#define TMDS_DEBUG10__DBG_DIG_TMDS10_MASK 0xffffffff
++#define TMDS_DEBUG10__DBG_DIG_TMDS10__SHIFT 0x0
++#define TMDS_DEBUG11__DBG_DIG_TMDS11_MASK 0xffffffff
++#define TMDS_DEBUG11__DBG_DIG_TMDS11__SHIFT 0x0
++#define TMDS_DEBUG12__DBG_LVDS_DEBUG1_MASK 0xffffffff
++#define TMDS_DEBUG12__DBG_LVDS_DEBUG1__SHIFT 0x0
++#define TMDS_DEBUG13__DBG_LVDS_DEBUG2_MASK 0xffffffff
++#define TMDS_DEBUG13__DBG_LVDS_DEBUG2__SHIFT 0x0
++#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1
++#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0
++#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10
++#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400
++#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa
++#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000
++#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc
++#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000
++#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10
++#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000
++#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11
++#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000
++#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12
++#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
++#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
++#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
++#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
++#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
++#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMCU_CTRL__RESET_UC_MASK 0x1
++#define DMCU_CTRL__RESET_UC__SHIFT 0x0
++#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
++#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
++#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
++#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
++#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
++#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
++#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
++#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
++#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
++#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
++#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00
++#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK_MASK 0x10
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK_MASK 0x20
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
++#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
++#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
++#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
++#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
++#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
++#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
++#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
++#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
++#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP_VID_N__DP_VID_N_MASK 0xffffff
++#define DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP_VID_M__DP_VID_M_MASK 0xffffff
++#define DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
++#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
++#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
++#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
++#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
++#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
++#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
++#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
++#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
++#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
++#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
++#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
++#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000
++#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0
++#define AUX_CONTROL__AUX_EN_MASK 0x1
++#define AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
++#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
++#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
++#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
++#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
++#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define AUX_CONTROL__SPARE_0_MASK 0x40000000
++#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define AUX_CONTROL__SPARE_1_MASK 0x80000000
++#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
++#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
++#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
++#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
++#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
++#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
++#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
++#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
++#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
++#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
++#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
++#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
++#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
++#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
++#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff
++#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0
++#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff
++#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0
++#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff
++#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0
++#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff
++#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0
++#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff
++#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0
++#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff
++#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0
++#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff
++#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0
++#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff
++#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0
++#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff
++#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0
++#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff
++#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0
++#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff
++#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0
++#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff
++#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0
++#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff
++#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0
++#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff
++#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0
++#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff
++#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0
++#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff
++#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0
++#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff
++#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0
++#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0
++#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
++#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
++#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
++#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
++#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
++#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
++#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
++#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
++#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
++#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
++#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
++#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
++#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
++#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
++#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
++#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
++#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
++#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
++#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
++#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
++#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
++#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
++#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
++#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
++#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
++#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
++#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
++#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
++#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
++#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0
++#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
++#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
++#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
++#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
++#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
++#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
++#define FBC_CNTL__FBC_EN_MASK 0x80000000
++#define FBC_CNTL__FBC_EN__SHIFT 0x1f
++#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff
++#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
++#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
++#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
++#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
++#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
++#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
++#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
++#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
++#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
++#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
++#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
++#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
++#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
++#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
++#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
++#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
++#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
++#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff
++#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
++#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff
++#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
++#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff
++#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
++#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff
++#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
++#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff
++#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
++#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff
++#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
++#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff
++#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
++#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff
++#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
++#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff
++#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
++#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff
++#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
++#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff
++#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
++#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff
++#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
++#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff
++#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
++#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff
++#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
++#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff
++#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
++#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff
++#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
++#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
++#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
++#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
++#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
++#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
++#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
++#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
++#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
++#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
++#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
++#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
++#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
++#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
++#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
++#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
++#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
++#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000
++#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000
++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11
++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000
++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12
++#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
++#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x10000
++#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x10
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000
++#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000
++#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0
++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
++#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100
++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
++#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
++#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
++#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
++#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
++#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
++#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
++#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
++#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
++#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
++#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
++#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
++#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
++#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
++#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
++#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
++#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
++#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
++#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
++#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
++#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
++#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
++#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
++#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
++#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
++#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
++#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
++#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
++#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
++#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
++#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
++#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
++#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
++#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
++#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
++#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
++#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
++#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
++#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
++#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
++#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
++#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
++#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
++#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
++#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40
++#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
++#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80
++#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
++#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000
++#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
++#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
++#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
++#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
++#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
++#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
++#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
++#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff
++#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000
++#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000
++#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff
++#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
++#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
++#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff
++#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
++#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff
++#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff
++#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
++#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
++#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
++#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
++#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10
++#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000
++#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
++#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
++#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
++#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
++#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
++#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
++#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
++#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
++#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
++#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
++#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
++#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
++#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
++#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
++#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
++#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
++#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
++#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
++#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
++#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff
++#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0
++#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff
++#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0
++#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff
++#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
++#define MVP_CONTROL1__MVP_EN_MASK 0x1
++#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
++#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
++#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
++#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
++#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
++#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
++#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
++#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
++#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
++#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
++#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
++#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
++#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6
++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6
++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
++#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
++#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
++#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
++#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
++#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
++#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
++#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
++#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
++#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
++#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
++#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
++#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
++#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
++#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
++#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL_MODE__SCL_MODE_MASK 0x3
++#define SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL_MODE__SCL_PSCL_EN_MASK 0x10
++#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
++#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
++#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
++#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
++#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
++#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
++#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
++#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
++#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
++#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
++#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
++#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
++#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
++#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
++#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCLV_MODE__SCL_MODE_MASK 0x1
++#define SCLV_MODE__SCL_MODE__SHIFT 0x0
++#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10
++#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300
++#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
++#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
++#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
++#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100
++#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
++#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff
++#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
++#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
++#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff
++#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
++#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
++#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
++#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
++#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
++#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
++#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff
++#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
++#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
++#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
++#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
++#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
++#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
++#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
++#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
++#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
++#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3
++#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff
++#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
++#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
++#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0xc
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x2
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x4
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
++#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3
++#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
++#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff
++#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
++#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000
++#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
++#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff
++#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
++#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000
++#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
++#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff
++#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
++#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000
++#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
++#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7
++#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
++#define DENORM_CLAMP_CONTROL__DENORM_FACTOR_MASK 0x3
++#define DENORM_CLAMP_CONTROL__DENORM_FACTOR__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3
++#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0
++#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0x1ff
++#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0
++#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff
++#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0
++#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7
++#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff
++#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff
++#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff
++#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0
++#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1
++#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0
++#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
++#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
++#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
++#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30
++#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
++#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
++#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
++#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
++#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
++#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
++#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
++#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
++#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
++#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
++#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
++#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
++#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
++#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
++#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7
++#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
++#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
++#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
++#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
++#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
++#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L_MASK 0x1
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C_MASK 0x1
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L_MASK 0x1
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C_MASK 0x1
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff
++#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
++#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff
++#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
++#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff
++#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
++#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff
++#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
++#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff
++#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
++#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff
++#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
++#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff
++#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
++#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff
++#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
++#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff
++#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
++#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff
++#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
++#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
++#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
++#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
++#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
++#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
++#define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
++#define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
++#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
++#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
++#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
++#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1
++#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
++#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c
++#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
++#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300
++#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
++#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff
++#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
++#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff
++#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
++#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff
++#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
++#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0
++#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
++#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7
++#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
++#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10
++#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
++#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100
++#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
++#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff
++#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0
++#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff
++#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0
++#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
++#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_WT__VGA_RAM_EN_MASK 0x2
++#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_WT__VGA_CKSEL_MASK 0xc
++#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
++#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
++#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
++#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
++#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
++#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
++#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_RD__VGA_RAM_EN_MASK 0x2
++#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_RD__VGA_CKSEL_MASK 0xc
++#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
++#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
++#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
++#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
++#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
++#define GENENB__BLK_IO_BASE_MASK 0xff
++#define GENENB__BLK_IO_BASE__SHIFT 0x0
++#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
++#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
++#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
++#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
++#define GENS0__SENSE_SWITCH_MASK 0x10
++#define GENS0__SENSE_SWITCH__SHIFT 0x4
++#define GENS0__CRT_INTR_MASK 0x80
++#define GENS0__CRT_INTR__SHIFT 0x7
++#define GENS1__NO_DISPLAY_MASK 0x1
++#define GENS1__NO_DISPLAY__SHIFT 0x0
++#define GENS1__VGA_VSTATUS_MASK 0x8
++#define GENS1__VGA_VSTATUS__SHIFT 0x3
++#define GENS1__PIXEL_READ_BACK_MASK 0x30
++#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
++#define DAC_DATA__DAC_DATA_MASK 0x3f
++#define DAC_DATA__DAC_DATA__SHIFT 0x0
++#define DAC_MASK__DAC_MASK_MASK 0xff
++#define DAC_MASK__DAC_MASK__SHIFT 0x0
++#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
++#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
++#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
++#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
++#define SEQ8_IDX__SEQ_IDX_MASK 0x7
++#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
++#define SEQ8_DATA__SEQ_DATA_MASK 0xff
++#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
++#define SEQ00__SEQ_RST0B_MASK 0x1
++#define SEQ00__SEQ_RST0B__SHIFT 0x0
++#define SEQ00__SEQ_RST1B_MASK 0x2
++#define SEQ00__SEQ_RST1B__SHIFT 0x1
++#define SEQ01__SEQ_DOT8_MASK 0x1
++#define SEQ01__SEQ_DOT8__SHIFT 0x0
++#define SEQ01__SEQ_SHIFT2_MASK 0x4
++#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
++#define SEQ01__SEQ_PCLKBY2_MASK 0x8
++#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
++#define SEQ01__SEQ_SHIFT4_MASK 0x10
++#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
++#define SEQ01__SEQ_MAXBW_MASK 0x20
++#define SEQ01__SEQ_MAXBW__SHIFT 0x5
++#define SEQ02__SEQ_MAP0_EN_MASK 0x1
++#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
++#define SEQ02__SEQ_MAP1_EN_MASK 0x2
++#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
++#define SEQ02__SEQ_MAP2_EN_MASK 0x4
++#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
++#define SEQ02__SEQ_MAP3_EN_MASK 0x8
++#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B1_MASK 0x1
++#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
++#define SEQ03__SEQ_FONT_B2_MASK 0x2
++#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
++#define SEQ03__SEQ_FONT_A1_MASK 0x4
++#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
++#define SEQ03__SEQ_FONT_A2_MASK 0x8
++#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B0_MASK 0x10
++#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
++#define SEQ03__SEQ_FONT_A0_MASK 0x20
++#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
++#define SEQ04__SEQ_256K_MASK 0x2
++#define SEQ04__SEQ_256K__SHIFT 0x1
++#define SEQ04__SEQ_ODDEVEN_MASK 0x4
++#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
++#define SEQ04__SEQ_CHAIN_MASK 0x8
++#define SEQ04__SEQ_CHAIN__SHIFT 0x3
++#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
++#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
++#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
++#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
++#define CRT00__H_TOTAL_MASK 0xff
++#define CRT00__H_TOTAL__SHIFT 0x0
++#define CRT01__H_DISP_END_MASK 0xff
++#define CRT01__H_DISP_END__SHIFT 0x0
++#define CRT02__H_BLANK_START_MASK 0xff
++#define CRT02__H_BLANK_START__SHIFT 0x0
++#define CRT03__H_BLANK_END_MASK 0x1f
++#define CRT03__H_BLANK_END__SHIFT 0x0
++#define CRT03__H_DE_SKEW_MASK 0x60
++#define CRT03__H_DE_SKEW__SHIFT 0x5
++#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
++#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
++#define CRT04__H_SYNC_START_MASK 0xff
++#define CRT04__H_SYNC_START__SHIFT 0x0
++#define CRT05__H_SYNC_END_MASK 0x1f
++#define CRT05__H_SYNC_END__SHIFT 0x0
++#define CRT05__H_SYNC_SKEW_MASK 0x60
++#define CRT05__H_SYNC_SKEW__SHIFT 0x5
++#define CRT05__H_BLANK_END_B5_MASK 0x80
++#define CRT05__H_BLANK_END_B5__SHIFT 0x7
++#define CRT06__V_TOTAL_MASK 0xff
++#define CRT06__V_TOTAL__SHIFT 0x0
++#define CRT07__V_TOTAL_B8_MASK 0x1
++#define CRT07__V_TOTAL_B8__SHIFT 0x0
++#define CRT07__V_DISP_END_B8_MASK 0x2
++#define CRT07__V_DISP_END_B8__SHIFT 0x1
++#define CRT07__V_SYNC_START_B8_MASK 0x4
++#define CRT07__V_SYNC_START_B8__SHIFT 0x2
++#define CRT07__V_BLANK_START_B8_MASK 0x8
++#define CRT07__V_BLANK_START_B8__SHIFT 0x3
++#define CRT07__LINE_CMP_B8_MASK 0x10
++#define CRT07__LINE_CMP_B8__SHIFT 0x4
++#define CRT07__V_TOTAL_B9_MASK 0x20
++#define CRT07__V_TOTAL_B9__SHIFT 0x5
++#define CRT07__V_DISP_END_B9_MASK 0x40
++#define CRT07__V_DISP_END_B9__SHIFT 0x6
++#define CRT07__V_SYNC_START_B9_MASK 0x80
++#define CRT07__V_SYNC_START_B9__SHIFT 0x7
++#define CRT08__ROW_SCAN_START_MASK 0x1f
++#define CRT08__ROW_SCAN_START__SHIFT 0x0
++#define CRT08__BYTE_PAN_MASK 0x60
++#define CRT08__BYTE_PAN__SHIFT 0x5
++#define CRT09__MAX_ROW_SCAN_MASK 0x1f
++#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
++#define CRT09__V_BLANK_START_B9_MASK 0x20
++#define CRT09__V_BLANK_START_B9__SHIFT 0x5
++#define CRT09__LINE_CMP_B9_MASK 0x40
++#define CRT09__LINE_CMP_B9__SHIFT 0x6
++#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
++#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
++#define CRT0A__CURSOR_START_MASK 0x1f
++#define CRT0A__CURSOR_START__SHIFT 0x0
++#define CRT0A__CURSOR_DISABLE_MASK 0x20
++#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
++#define CRT0B__CURSOR_END_MASK 0x1f
++#define CRT0B__CURSOR_END__SHIFT 0x0
++#define CRT0B__CURSOR_SKEW_MASK 0x60
++#define CRT0B__CURSOR_SKEW__SHIFT 0x5
++#define CRT0C__DISP_START_MASK 0xff
++#define CRT0C__DISP_START__SHIFT 0x0
++#define CRT0D__DISP_START_MASK 0xff
++#define CRT0D__DISP_START__SHIFT 0x0
++#define CRT0E__CURSOR_LOC_HI_MASK 0xff
++#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
++#define CRT0F__CURSOR_LOC_LO_MASK 0xff
++#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
++#define CRT10__V_SYNC_START_MASK 0xff
++#define CRT10__V_SYNC_START__SHIFT 0x0
++#define CRT11__V_SYNC_END_MASK 0xf
++#define CRT11__V_SYNC_END__SHIFT 0x0
++#define CRT11__V_INTR_CLR_MASK 0x10
++#define CRT11__V_INTR_CLR__SHIFT 0x4
++#define CRT11__V_INTR_EN_MASK 0x20
++#define CRT11__V_INTR_EN__SHIFT 0x5
++#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
++#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
++#define CRT11__C0T7_WR_ONLY_MASK 0x80
++#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
++#define CRT12__V_DISP_END_MASK 0xff
++#define CRT12__V_DISP_END__SHIFT 0x0
++#define CRT13__DISP_PITCH_MASK 0xff
++#define CRT13__DISP_PITCH__SHIFT 0x0
++#define CRT14__UNDRLN_LOC_MASK 0x1f
++#define CRT14__UNDRLN_LOC__SHIFT 0x0
++#define CRT14__ADDR_CNT_BY4_MASK 0x20
++#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
++#define CRT14__DOUBLE_WORD_MASK 0x40
++#define CRT14__DOUBLE_WORD__SHIFT 0x6
++#define CRT15__V_BLANK_START_MASK 0xff
++#define CRT15__V_BLANK_START__SHIFT 0x0
++#define CRT16__V_BLANK_END_MASK 0xff
++#define CRT16__V_BLANK_END__SHIFT 0x0
++#define CRT17__RA0_AS_A13B_MASK 0x1
++#define CRT17__RA0_AS_A13B__SHIFT 0x0
++#define CRT17__RA1_AS_A14B_MASK 0x2
++#define CRT17__RA1_AS_A14B__SHIFT 0x1
++#define CRT17__VCOUNT_BY2_MASK 0x4
++#define CRT17__VCOUNT_BY2__SHIFT 0x2
++#define CRT17__ADDR_CNT_BY2_MASK 0x8
++#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
++#define CRT17__WRAP_A15TOA0_MASK 0x20
++#define CRT17__WRAP_A15TOA0__SHIFT 0x5
++#define CRT17__BYTE_MODE_MASK 0x40
++#define CRT17__BYTE_MODE__SHIFT 0x6
++#define CRT17__CRTC_SYNC_EN_MASK 0x80
++#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
++#define CRT18__LINE_CMP_MASK 0xff
++#define CRT18__LINE_CMP__SHIFT 0x0
++#define CRT1E__GRPH_DEC_RD1_MASK 0x2
++#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
++#define CRT1F__GRPH_DEC_RD0_MASK 0xff
++#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
++#define CRT22__GRPH_LATCH_DATA_MASK 0xff
++#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
++#define GRPH8_IDX__GRPH_IDX_MASK 0xf
++#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
++#define GRPH8_DATA__GRPH_DATA_MASK 0xff
++#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET0_MASK 0x1
++#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET1_MASK 0x2
++#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
++#define GRA00__GRPH_SET_RESET2_MASK 0x4
++#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
++#define GRA00__GRPH_SET_RESET3_MASK 0x8
++#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
++#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
++#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
++#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
++#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
++#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
++#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
++#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
++#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
++#define GRA02__GRPH_CCOMP_MASK 0xf
++#define GRA02__GRPH_CCOMP__SHIFT 0x0
++#define GRA03__GRPH_ROTATE_MASK 0x7
++#define GRA03__GRPH_ROTATE__SHIFT 0x0
++#define GRA03__GRPH_FN_SEL_MASK 0x18
++#define GRA03__GRPH_FN_SEL__SHIFT 0x3
++#define GRA04__GRPH_RMAP_MASK 0x3
++#define GRA04__GRPH_RMAP__SHIFT 0x0
++#define GRA05__GRPH_WRITE_MODE_MASK 0x3
++#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
++#define GRA05__GRPH_READ1_MASK 0x8
++#define GRA05__GRPH_READ1__SHIFT 0x3
++#define GRA05__CGA_ODDEVEN_MASK 0x10
++#define GRA05__CGA_ODDEVEN__SHIFT 0x4
++#define GRA05__GRPH_OES_MASK 0x20
++#define GRA05__GRPH_OES__SHIFT 0x5
++#define GRA05__GRPH_PACK_MASK 0x40
++#define GRA05__GRPH_PACK__SHIFT 0x6
++#define GRA06__GRPH_GRAPHICS_MASK 0x1
++#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
++#define GRA06__GRPH_ODDEVEN_MASK 0x2
++#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
++#define GRA06__GRPH_ADRSEL_MASK 0xc
++#define GRA06__GRPH_ADRSEL__SHIFT 0x2
++#define GRA07__GRPH_XCARE0_MASK 0x1
++#define GRA07__GRPH_XCARE0__SHIFT 0x0
++#define GRA07__GRPH_XCARE1_MASK 0x2
++#define GRA07__GRPH_XCARE1__SHIFT 0x1
++#define GRA07__GRPH_XCARE2_MASK 0x4
++#define GRA07__GRPH_XCARE2__SHIFT 0x2
++#define GRA07__GRPH_XCARE3_MASK 0x8
++#define GRA07__GRPH_XCARE3__SHIFT 0x3
++#define GRA08__GRPH_BMSK_MASK 0xff
++#define GRA08__GRPH_BMSK__SHIFT 0x0
++#define ATTRX__ATTR_IDX_MASK 0x1f
++#define ATTRX__ATTR_IDX__SHIFT 0x0
++#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
++#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
++#define ATTRDW__ATTR_DATA_MASK 0xff
++#define ATTRDW__ATTR_DATA__SHIFT 0x0
++#define ATTRDR__ATTR_DATA_MASK 0xff
++#define ATTRDR__ATTR_DATA__SHIFT 0x0
++#define ATTR00__ATTR_PAL_MASK 0x3f
++#define ATTR00__ATTR_PAL__SHIFT 0x0
++#define ATTR01__ATTR_PAL_MASK 0x3f
++#define ATTR01__ATTR_PAL__SHIFT 0x0
++#define ATTR02__ATTR_PAL_MASK 0x3f
++#define ATTR02__ATTR_PAL__SHIFT 0x0
++#define ATTR03__ATTR_PAL_MASK 0x3f
++#define ATTR03__ATTR_PAL__SHIFT 0x0
++#define ATTR04__ATTR_PAL_MASK 0x3f
++#define ATTR04__ATTR_PAL__SHIFT 0x0
++#define ATTR05__ATTR_PAL_MASK 0x3f
++#define ATTR05__ATTR_PAL__SHIFT 0x0
++#define ATTR06__ATTR_PAL_MASK 0x3f
++#define ATTR06__ATTR_PAL__SHIFT 0x0
++#define ATTR07__ATTR_PAL_MASK 0x3f
++#define ATTR07__ATTR_PAL__SHIFT 0x0
++#define ATTR08__ATTR_PAL_MASK 0x3f
++#define ATTR08__ATTR_PAL__SHIFT 0x0
++#define ATTR09__ATTR_PAL_MASK 0x3f
++#define ATTR09__ATTR_PAL__SHIFT 0x0
++#define ATTR0A__ATTR_PAL_MASK 0x3f
++#define ATTR0A__ATTR_PAL__SHIFT 0x0
++#define ATTR0B__ATTR_PAL_MASK 0x3f
++#define ATTR0B__ATTR_PAL__SHIFT 0x0
++#define ATTR0C__ATTR_PAL_MASK 0x3f
++#define ATTR0C__ATTR_PAL__SHIFT 0x0
++#define ATTR0D__ATTR_PAL_MASK 0x3f
++#define ATTR0D__ATTR_PAL__SHIFT 0x0
++#define ATTR0E__ATTR_PAL_MASK 0x3f
++#define ATTR0E__ATTR_PAL__SHIFT 0x0
++#define ATTR0F__ATTR_PAL_MASK 0x3f
++#define ATTR0F__ATTR_PAL__SHIFT 0x0
++#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
++#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
++#define ATTR10__ATTR_MONO_EN_MASK 0x2
++#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
++#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
++#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
++#define ATTR10__ATTR_BLINK_EN_MASK 0x8
++#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
++#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
++#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
++#define ATTR10__ATTR_PCLKBY2_MASK 0x40
++#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
++#define ATTR10__ATTR_CSEL_EN_MASK 0x80
++#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
++#define ATTR11__ATTR_OVSC_MASK 0xff
++#define ATTR11__ATTR_OVSC__SHIFT 0x0
++#define ATTR12__ATTR_MAP_EN_MASK 0xf
++#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
++#define ATTR12__ATTR_VSMUX_MASK 0x30
++#define ATTR12__ATTR_VSMUX__SHIFT 0x4
++#define ATTR13__ATTR_PPAN_MASK 0xf
++#define ATTR13__ATTR_PPAN__SHIFT 0x0
++#define ATTR14__ATTR_CSEL1_MASK 0x3
++#define ATTR14__ATTR_CSEL1__SHIFT 0x0
++#define ATTR14__ATTR_CSEL2_MASK 0xc
++#define ATTR14__ATTR_CSEL2__SHIFT 0x2
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
++#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
++#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
++#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
++#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
++#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
++#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
++#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
++#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
++#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff
++#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0
++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000
++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000
++#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10
++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f
++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7
++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf
++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10
++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff
++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8
++#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000
++#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc
++#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000
++#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd
++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000
++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10
++#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff
++#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0
++#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000
++#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10
++#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000
++#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12
++#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000
++#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3
++#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10
++#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10
++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000
++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14
++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000
++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16
++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000
++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18
++#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000
++#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a
++#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000
++#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c
++#define PLL_CNTL__PLL_RESET_MASK 0x1
++#define PLL_CNTL__PLL_RESET__SHIFT 0x0
++#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
++#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1
++#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4
++#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
++#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8
++#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3
++#define PLL_CNTL__PLL_VCOREF_MASK 0x30
++#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4
++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40
++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6
++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80
++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7
++#define PLL_CNTL__PLL_CALREF_MASK 0x300
++#define PLL_CNTL__PLL_CALREF__SHIFT 0x8
++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400
++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa
++#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800
++#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb
++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000
++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd
++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000
++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe
++#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000
++#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10
++#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000
++#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13
++#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000
++#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14
++#define PLL_CNTL__PLL_LOCKED_MASK 0x200000
++#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15
++#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000
++#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16
++#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000
++#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17
++#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000
++#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18
++#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000
++#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a
++#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f
++#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0
++#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60
++#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5
++#define PLL_ANALOG__PLL_CP_MASK 0xf00
++#define PLL_ANALOG__PLL_CP__SHIFT 0x8
++#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000
++#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc
++#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000
++#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15
++#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000
++#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18
++#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff
++#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0
++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000
++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14
++#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000
++#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a
++#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000
++#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8
++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1
++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0
++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0
++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4
++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00
++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b
++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1
++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0
++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1
++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0
++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100
++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8
++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000
++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1
++#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1
++#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00
++#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8
++#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000
++#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a
++#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000
++#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c
++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1
++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0
++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e
++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1
++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0
++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5
++#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00
++#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9
++#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000
++#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe
++#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000
++#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11
++#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000
++#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12
++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff
++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0
++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff
++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0
++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff
++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f
++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18
++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f
++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18
++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f
++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18
++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1
++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0
++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0
++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4
++#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1
++#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0
++#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2
++#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7
++#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff
++#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0
++#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000
++#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10
++#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000
++#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a
++#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f
++#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0
++#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff
++#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0
++#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff
++#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17
++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000
++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18
++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000
++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0
++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1
++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc
++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a
++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0
++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc
++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc
++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d
++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff
++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19
++#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000
++#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a
++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff
++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0
++#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1
++#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0
++#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2
++#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb
++#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000
++#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14
++#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000
++#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15
++#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000
++#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17
++#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000
++#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18
++#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000
++#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a
++#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000
++#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b
++#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000
++#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11
++#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000
++#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c
++#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000
++#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe
++#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000
++#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf
++#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000
++#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14
++#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000
++#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19
++#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff
++#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0
++#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000
++#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16
++#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1
++#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0
++#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2
++#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1
++#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4
++#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2
++#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8
++#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3
++#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10
++#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4
++#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20
++#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5
++#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40
++#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6
++#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80
++#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f
++#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1
++#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0
++#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2
++#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1
++#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4
++#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2
++#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78
++#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3
++#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780
++#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7
++#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800
++#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb
++#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff
++#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11
++#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff
++#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0
++#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000
++#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc
++#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000
++#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16
++#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000
++#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19
++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
++#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
++#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f
++#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0
++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0
++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
++#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
++#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
++#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
++#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
++#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
++#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
++#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
++#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
++#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
++#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff
++#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0
++#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1
++#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
++#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2
++#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
++#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4
++#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
++#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8
++#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
++#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10
++#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
++#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20
++#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
++#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40
++#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6
++#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80
++#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7
++#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100
++#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8
++#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200
++#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9
++#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400
++#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
++#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800
++#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb
++#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000
++#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc
++#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000
++#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd
++#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000
++#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe
++#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000
++#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf
++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
++#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1
++#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
++#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2
++#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
++#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4
++#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
++#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8
++#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
++#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10
++#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
++#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20
++#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
++#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40
++#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6
++#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80
++#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7
++#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100
++#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8
++#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200
++#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9
++#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400
++#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
++#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800
++#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb
++#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000
++#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc
++#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000
++#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd
++#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000
++#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe
++#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000
++#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf
++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
++#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40
++#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6
++#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80
++#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7
++#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100
++#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8
++#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200
++#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9
++#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400
++#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
++#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800
++#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb
++#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000
++#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc
++#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000
++#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd
++#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000
++#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe
++#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000
++#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
++#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_MASK 0x3
++#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
++#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
++#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
++#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
++#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
++#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
++#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
++#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1
++#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
++#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
++#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
++#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
++#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1
++#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
++#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND_CONTROL__BLND_MODE_MASK 0x300
++#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
++#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
++#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
++#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
++#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
++#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
++#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define SM_CONTROL2__SM_MODE_MASK 0x7
++#define SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
++#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
++#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
++#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
++#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
++#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1
++#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
++#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
++#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
++#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
++#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
++#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
++#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
++#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100
++#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
++#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
++#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING_MASK 0x10
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING__SHIFT 0x4
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING_MASK 0x20
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING__SHIFT 0x5
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
++#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
++#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
++#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
++#define WB_ENABLE__WB_ENABLE_MASK 0x1
++#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
++#define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS_MASK 0x8
++#define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS__SHIFT 0x3
++#define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS_MASK 0x10
++#define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS__SHIFT 0x4
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS_MASK 0x20
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS__SHIFT 0x5
++#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40
++#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6
++#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80
++#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7
++#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100
++#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
++#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000
++#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
++#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000
++#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
++#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000
++#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
++#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
++#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
++#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000
++#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
++#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000
++#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
++#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
++#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
++#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
++#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
++#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
++#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
++#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
++#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
++#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
++#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1
++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
++#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
++#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
++#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
++#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
++#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
++#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
++#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
++#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
++#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
++#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
++#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
++#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
++#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
++#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
++#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
++#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
++#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
++#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
++#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
++#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
++#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
++#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
++#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1
++#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0
++#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0
++#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
++#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1
++#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
++#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2
++#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
++#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4
++#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
++#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8
++#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100
++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000
++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
++#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff
++#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3
++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c
++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
++#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1
++#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
++#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000
++#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000
++#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2
++#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4
++#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8
++#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
++#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1
++#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0
++#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0
++#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4
++#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8
++#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
++#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000
++#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000
++#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2
++#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4
++#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8
++#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
++#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
++#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20
++#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
++#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40
++#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
++#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1
++#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100
++#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000
++#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff
++#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
++#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff
++#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
++#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff
++#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
++#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff
++#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
++#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff
++#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
++#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff
++#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
++#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff
++#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
++#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff
++#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1
++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE_MASK 0x2
++#define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE__SHIFT 0x1
++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4
++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8
++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10
++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20
++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40
++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80
++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100
++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200
++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00
++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000
++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000
++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000
++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000
++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000
++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000
++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
++#define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS_MASK 0x4
++#define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10
++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20
++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40
++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80
++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100
++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200
++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400
++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3
++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f
++#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400
++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
++#define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS_MASK 0x10
++#define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS__SHIFT 0x4
++#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20
++#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000
++#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e
++#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1
++#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0
++#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2
++#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1
++#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10
++#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4
++#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100
++#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8
++#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000
++#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
++#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
++#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000
++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
++#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
++#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
++#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
++#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
++#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
++#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
++#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000
++#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f
++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0
++#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
++#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
++#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
++#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
++#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
++#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
++#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
++#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
++#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
++#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
++#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
++#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
++#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
++#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000
++#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300
++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
++#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
++#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa
++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
++#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000
++#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18
++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
++
++#endif /* DCE_10_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0005-yocto-amd-i2c-driver_support_ACPI2Platform-1.0.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0005-yocto-amd-i2c-driver_support_ACPI2Platform-1.0.patch
new file mode 100644
index 00000000..992a54f8
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0005-yocto-amd-i2c-driver_support_ACPI2Platform-1.0.patch
@@ -0,0 +1,317 @@
+From a29dd45173a7e20e5e3f29fb8d71222b80fb0c12 Mon Sep 17 00:00:00 2001
+From: Ken Xue <Ken.Xue@amd.com>
+Date: Thu, 6 Nov 2014 08:21:37 +0800
+Subject: [PATCH 1/6] [CZ][FCH]support ACPI2Platform device for x86 system.
+
+This new feature is to interpret AMD specific ACPI device to platform device
+such as I2C, UART found on AMD CZ and later chipsets. It is based on example
+INTEL LPSS. Now, it just supports AMD I2C.
+
+Signed-off-by: Ken Xue <Ken.Xue@amd.com>
+Signed-off-by: Jeff Wu <Jeff.Wu@amd.com>
+Signed-off-by: Awais Belal <awais_belal@mentor.com>
+---
+ arch/x86/Kconfig        |  11 +++
+ drivers/acpi/Makefile   |   1 +
+ drivers/acpi/acpi_apd.c | 234 ++++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/acpi/internal.h |   6 ++
+ drivers/acpi/scan.c     |   1 +
+ 5 files changed, 253 insertions(+)
+ create mode 100644 drivers/acpi/acpi_apd.c
+diff -Naur a/arch/x86/Kconfig b/arch/x86/Kconfig
+--- a/arch/x86/Kconfig	2015-03-25 14:39:54.676737984 +0530
++++ b/arch/x86/Kconfig	2015-03-25 14:51:42.084751856 +0530
+@@ -474,6 +474,17 @@
+ 	  things like clock tree (common clock framework) and pincontrol
+ 	  which are needed by the LPSS peripheral drivers.
+ 
++config X86_AMD_PLATFORM_DEVICE
++       bool "AMD ACPI2Platform devices support"
++       depends on ACPI
++       select COMMON_CLK
++       select PINCTRL
++       ---help---
++         Select to interpret AMD specific ACPI device to platform device
++         such as I2C, UART found on AMD CARRIZO and later chipset. Selecting
++         this option enables things like clock tree (common clock framework)
++         and pincontrol.
++
+ config X86_RDC321X
+ 	bool "RDC R-321x SoC"
+ 	depends on X86_32
+diff -Naur a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
+--- a/drivers/acpi/acpi_apd.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/acpi/acpi_apd.c	2015-03-25 14:51:42.084751856 +0530
+@@ -0,0 +1,234 @@
++/*
++ * AMD ACPI support for ACPI2platform device.
++ *
++ * Copyright (c) 2014, AMD Corporation.
++ * Authors: Ken Xue <Ken.Xue@amd.com>
++ *	Peng, Carl <Carl.Peng@amd.com>
++ *	Wu, Jeff <Jeff.Wu@amd.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/acpi.h>
++#include <linux/clk.h>
++#include <linux/clkdev.h>
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++
++#include "internal.h"
++
++ACPI_MODULE_NAME("acpi_apd");
++struct apd_private_data;
++
++struct apd_device_desc {
++	bool clk_required;
++	bool fix_rate_root_clock;
++	const char *clk_name;
++	unsigned long	rate;
++	size_t prv_size_override;
++	void (*setup)(struct apd_private_data *pdata);
++};
++
++struct apd_private_data {
++	void __iomem *mmio_base;
++	resource_size_t mmio_size;
++	struct clk *clk;
++	const struct apd_device_desc *dev_desc;
++};
++
++static struct apd_device_desc amd_i2c_desc = {
++	.clk_required = true,
++	.fix_rate_root_clock = true,
++	.clk_name = "i2c_clk",
++	.rate = 136192000, /*(133 * 1024 * 1000)*/
++};
++
++static const struct acpi_device_id acpi_apd_device_ids[] = {
++	/* Generic apd devices */
++	{ "AMD0010", (unsigned long)&amd_i2c_desc },
++	/*{ "UART0000, (unsigned long)&amur_uart_dev_desc },*/
++	/*{"AMD0030", (unsigned long)&amur_gpio_dev_desc },*/
++	{ }
++};
++
++static int is_memory(struct acpi_resource *res, void *not_used)
++{
++	struct resource r;
++
++	return !acpi_dev_resource_memory(res, &r);
++}
++
++static int register_device_clock(struct acpi_device *adev,
++				 struct apd_private_data *pdata)
++{
++	const struct apd_device_desc *dev_desc = pdata->dev_desc;
++	struct clk *clk = ERR_PTR(-ENODEV);
++
++	clk = pdata->clk;
++	if (!clk && dev_desc->fix_rate_root_clock) {
++		clk = clk_register_fixed_rate(&adev->dev, dev_name(&adev->dev),
++				      NULL, CLK_IS_ROOT, dev_desc->rate);
++		pdata->clk = clk;
++		clk_register_clkdev(clk, NULL, dev_name(&adev->dev));
++	}
++
++	return 0;
++}
++
++static int acpi_apd_create_device(struct acpi_device *adev,
++				   const struct acpi_device_id *id)
++{
++	struct apd_device_desc *dev_desc;
++	struct apd_private_data *pdata;
++	struct resource_list_entry *rentry;
++	struct list_head resource_list;
++	int ret;
++
++	dev_desc = (struct apd_device_desc *)id->driver_data;
++	if (!dev_desc)
++		return acpi_create_platform_device(adev, id);
++
++	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
++	if (!pdata)
++		return -ENOMEM;
++
++	INIT_LIST_HEAD(&resource_list);
++	ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
++	if (ret < 0)
++		goto err_out;
++
++	list_for_each_entry(rentry, &resource_list, node)
++		if (resource_type(&rentry->res) == IORESOURCE_MEM) {
++			if (dev_desc->prv_size_override)
++				pdata->mmio_size = dev_desc->prv_size_override;
++			else
++				pdata->mmio_size = resource_size(&rentry->res);
++			pdata->mmio_base = ioremap(rentry->res.start,
++						   pdata->mmio_size);
++			break;
++		}
++
++	acpi_dev_free_resource_list(&resource_list);
++
++	pdata->dev_desc = dev_desc;
++
++	if (dev_desc->clk_required) {
++		ret = register_device_clock(adev, pdata);
++		if (ret) {
++			/* Skip the device, but continue the namespace scan. */
++			ret = 0;
++			goto err_out;
++		}
++	}
++
++	/*
++	 * This works around a known issue in ACPI tables where apd devices
++	 * have _PS0 and _PS3 without _PSC (and no power resources), so
++	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
++	 */
++	ret = acpi_device_fix_up_power(adev);
++	if (ret) {
++		/* Skip the device, but continue the namespace scan. */
++		ret = 0;
++		goto err_out;
++	}
++
++	if (dev_desc->setup)
++		dev_desc->setup(pdata);
++
++	adev->driver_data = pdata;
++	ret = acpi_create_platform_device(adev, id);
++	if (ret > 0)
++		return ret;
++
++	adev->driver_data = NULL;
++
++ err_out:
++	kfree(pdata);
++	return ret;
++}
++
++static ssize_t apd_device_desc_show(struct device *dev,
++				struct device_attribute *attr, char *buf)
++{
++	int ret;
++	struct acpi_device *adev;
++	struct apd_private_data *pdata;
++
++	ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
++	if (WARN_ON(ret))
++		return ret;
++
++	pdata = acpi_driver_data(adev);
++	if (WARN_ON(!pdata || !pdata->dev_desc))
++		return -ENODEV;
++
++	if (pdata->dev_desc->clk_required)
++		return sprintf(buf, "Required clk: %s %s %ld\n",
++		pdata->dev_desc->clk_name,
++		pdata->dev_desc->fix_rate_root_clock ?
++		"fix rate" : "no fix rate",
++		pdata->dev_desc->rate);
++	else
++		return sprintf(buf, "No need clk\n");
++}
++
++static DEVICE_ATTR(device_desc, S_IRUSR, apd_device_desc_show, NULL);
++
++static struct attribute *apd_attrs[] = {
++	&dev_attr_device_desc.attr,
++	NULL,
++};
++
++static struct attribute_group apd_attr_group = {
++	.attrs = apd_attrs,
++	.name = "apd_ltr",
++};
++
++static int acpi_apd_platform_notify(struct notifier_block *nb,
++				     unsigned long action, void *data)
++{
++	struct platform_device *pdev = to_platform_device(data);
++	struct apd_private_data *pdata;
++	struct acpi_device *adev;
++	const struct acpi_device_id *id;
++	int ret = 0;
++
++	id = acpi_match_device(acpi_apd_device_ids, &pdev->dev);
++	if (!id || !id->driver_data)
++		return 0;
++
++	if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
++		return 0;
++
++	pdata = acpi_driver_data(adev);
++	if (!pdata || !pdata->mmio_base)
++		return 0;
++
++	if (action == BUS_NOTIFY_ADD_DEVICE)
++		ret = sysfs_create_group(&pdev->dev.kobj, &apd_attr_group);
++	else if (action == BUS_NOTIFY_DEL_DEVICE)
++		sysfs_remove_group(&pdev->dev.kobj, &apd_attr_group);
++
++	return ret;
++}
++
++static struct notifier_block acpi_apd_nb = {
++	.notifier_call = acpi_apd_platform_notify,
++};
++
++static struct acpi_scan_handler apd_handler = {
++	.ids = acpi_apd_device_ids,
++	.attach = acpi_apd_create_device,
++};
++
++void __init acpi_apd_init(void)
++{
++	bus_register_notifier(&platform_bus_type, &acpi_apd_nb);
++	acpi_scan_add_handler(&apd_handler);
++}
+diff -Naur a/drivers/acpi/internal.h b/drivers/acpi/internal.h
+--- a/drivers/acpi/internal.h	2015-03-25 14:39:54.684737985 +0530
++++ b/drivers/acpi/internal.h	2015-03-25 14:51:42.084751856 +0530
+@@ -72,6 +72,12 @@
+ static inline void acpi_lpss_init(void) {}
+ #endif
+ 
++#ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
++void acpi_apd_init(void);
++#else
++static inline void acpi_apd_init(void) {}
++#endif
++
+ bool acpi_queue_hotplug_work(struct work_struct *work);
+ bool acpi_scan_is_offline(struct acpi_device *adev, bool uevent);
+ 
+diff -Naur a/drivers/acpi/Makefile b/drivers/acpi/Makefile
+--- a/drivers/acpi/Makefile	2015-03-25 14:39:54.684737985 +0530
++++ b/drivers/acpi/Makefile	2015-03-25 14:51:42.084751856 +0530
+@@ -40,6 +40,7 @@
+ acpi-$(CONFIG_ACPI_DOCK)	+= dock.o
+ acpi-y				+= pci_root.o pci_link.o pci_irq.o
+ acpi-$(CONFIG_X86_INTEL_LPSS)	+= acpi_lpss.o
++acpi-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += acpi_apd.o
+ acpi-y				+= acpi_platform.o
+ acpi-y				+= power.o
+ acpi-y				+= event.o
+diff -Naur a/drivers/acpi/scan.c b/drivers/acpi/scan.c
+--- a/drivers/acpi/scan.c	2015-03-25 14:39:54.688737985 +0530
++++ b/drivers/acpi/scan.c	2015-03-25 14:51:42.084751856 +0530
+@@ -2191,6 +2191,7 @@
+ 	acpi_processor_init();
+ 	acpi_platform_init();
+ 	acpi_lpss_init();
++	acpi_apd_init();
+ 	acpi_cmos_rtc_init();
+ 	acpi_container_init();
+ 	acpi_memory_hotplug_init();
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch
new file mode 100644
index 00000000..25aed9bd
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch
@@ -0,0 +1,31367 @@
+From ff26fbca833fe9106bdd91c63a2a231273f9f228 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:18:28 -0400
+Subject: drm/amdgpu: add DCE 11.0 register headers
+
+These are register headers for the DCE (Display and Composition Engine)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
+new file mode 100644
+index 0000000..c39234e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
+@@ -0,0 +1,7648 @@
++/*
++ * DCE_11_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_11_0_D_H
++#define DCE_11_0_D_H
++
++#define mmPIPE0_PG_CONFIG                                                       0x2c0
++#define mmPIPE0_PG_ENABLE                                                       0x2c1
++#define mmPIPE0_PG_STATUS                                                       0x2c2
++#define mmPIPE1_PG_CONFIG                                                       0x2c3
++#define mmPIPE1_PG_ENABLE                                                       0x2c4
++#define mmPIPE1_PG_STATUS                                                       0x2c5
++#define mmPIPE2_PG_CONFIG                                                       0x2c6
++#define mmPIPE2_PG_ENABLE                                                       0x2c7
++#define mmPIPE2_PG_STATUS                                                       0x2c8
++#define mmDCFEV0_PG_CONFIG                                                      0x2db
++#define mmDCFEV0_PG_ENABLE                                                      0x2dc
++#define mmDCFEV0_PG_STATUS                                                      0x2dd
++#define mmDCPG_INTERRUPT_STATUS                                                 0x2de
++#define mmDCPG_INTERRUPT_CONTROL                                                0x2df
++#define mmDC_IP_REQUEST_CNTL                                                    0x2d2
++#define mmDC_PGFSM_CONFIG_REG                                                   0x2d3
++#define mmDC_PGFSM_WRITE_REG                                                    0x2d4
++#define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
++#define mmDCPG_TEST_DEBUG_INDEX                                                 0x2d6
++#define mmDCPG_TEST_DEBUG_DATA                                                  0x2d7
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                           0x1628
++#define mmBL1_PWM_USER_LEVEL                                                    0x1629
++#define mmBL1_PWM_TARGET_ABM_LEVEL                                              0x162a
++#define mmBL1_PWM_CURRENT_ABM_LEVEL                                             0x162b
++#define mmBL1_PWM_FINAL_DUTY_CYCLE                                              0x162c
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                            0x162d
++#define mmBL1_PWM_ABM_CNTL                                                      0x162e
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
++#define mmBL1_PWM_GRP2_REG_LOCK                                                 0x1630
++#define mmDC_ABM1_CNTL                                                          0x1638
++#define mmDC_ABM1_IPCSC_COEFF_SEL                                               0x1639
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                            0x163a
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                            0x163b
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                            0x163c
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                            0x163d
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                            0x163e
++#define mmDC_ABM1_ACE_THRES_12                                                  0x163f
++#define mmDC_ABM1_ACE_THRES_34                                                  0x1640
++#define mmDC_ABM1_ACE_CNTL_MISC                                                 0x1641
++#define mmDC_ABM1_DEBUG_MISC                                                    0x1649
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                        0x164a
++#define mmDC_ABM1_HG_MISC_CTRL                                                  0x164b
++#define mmDC_ABM1_LS_SUM_OF_LUMA                                                0x164c
++#define mmDC_ABM1_LS_MIN_MAX_LUMA                                               0x164d
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                      0x164e
++#define mmDC_ABM1_LS_PIXEL_COUNT                                                0x164f
++#define mmDC_ABM1_LS_OVR_SCAN_BIN                                               0x1650
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                  0x1651
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                      0x1652
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                      0x1653
++#define mmDC_ABM1_HG_SAMPLE_RATE                                                0x1654
++#define mmDC_ABM1_LS_SAMPLE_RATE                                                0x1655
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                        0x1656
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                        0x1657
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                       0x1658
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                      0x1659
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                      0x165a
++#define mmDC_ABM1_HG_RESULT_1                                                   0x165b
++#define mmDC_ABM1_HG_RESULT_2                                                   0x165c
++#define mmDC_ABM1_HG_RESULT_3                                                   0x165d
++#define mmDC_ABM1_HG_RESULT_4                                                   0x165e
++#define mmDC_ABM1_HG_RESULT_5                                                   0x165f
++#define mmDC_ABM1_HG_RESULT_6                                                   0x1660
++#define mmDC_ABM1_HG_RESULT_7                                                   0x1661
++#define mmDC_ABM1_HG_RESULT_8                                                   0x1662
++#define mmDC_ABM1_HG_RESULT_9                                                   0x1663
++#define mmDC_ABM1_HG_RESULT_10                                                  0x1664
++#define mmDC_ABM1_HG_RESULT_11                                                  0x1665
++#define mmDC_ABM1_HG_RESULT_12                                                  0x1666
++#define mmDC_ABM1_HG_RESULT_13                                                  0x1667
++#define mmDC_ABM1_HG_RESULT_14                                                  0x1668
++#define mmDC_ABM1_HG_RESULT_15                                                  0x1669
++#define mmDC_ABM1_HG_RESULT_16                                                  0x166a
++#define mmDC_ABM1_HG_RESULT_17                                                  0x166b
++#define mmDC_ABM1_HG_RESULT_18                                                  0x166c
++#define mmDC_ABM1_HG_RESULT_19                                                  0x166d
++#define mmDC_ABM1_HG_RESULT_20                                                  0x166e
++#define mmDC_ABM1_HG_RESULT_21                                                  0x166f
++#define mmDC_ABM1_HG_RESULT_22                                                  0x1670
++#define mmDC_ABM1_HG_RESULT_23                                                  0x1671
++#define mmDC_ABM1_HG_RESULT_24                                                  0x1672
++#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                          0x169b
++#define mmDC_ABM1_BL_MASTER_LOCK                                                0x169c
++#define mmABM_TEST_DEBUG_INDEX                                                  0x169e
++#define mmABM_TEST_DEBUG_DATA                                                   0x169f
++#define mmCRTC_H_BLANK_EARLY_NUM                                                0x1b7d
++#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                          0x1b7d
++#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                          0x1d7d
++#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                          0x1f7d
++#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                          0x417d
++#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                          0x437d
++#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                          0x457d
++#define mmCRTC_H_TOTAL                                                          0x1b80
++#define mmCRTC0_CRTC_H_TOTAL                                                    0x1b80
++#define mmCRTC1_CRTC_H_TOTAL                                                    0x1d80
++#define mmCRTC2_CRTC_H_TOTAL                                                    0x1f80
++#define mmCRTC3_CRTC_H_TOTAL                                                    0x4180
++#define mmCRTC4_CRTC_H_TOTAL                                                    0x4380
++#define mmCRTC5_CRTC_H_TOTAL                                                    0x4580
++#define mmCRTC_H_BLANK_START_END                                                0x1b81
++#define mmCRTC0_CRTC_H_BLANK_START_END                                          0x1b81
++#define mmCRTC1_CRTC_H_BLANK_START_END                                          0x1d81
++#define mmCRTC2_CRTC_H_BLANK_START_END                                          0x1f81
++#define mmCRTC3_CRTC_H_BLANK_START_END                                          0x4181
++#define mmCRTC4_CRTC_H_BLANK_START_END                                          0x4381
++#define mmCRTC5_CRTC_H_BLANK_START_END                                          0x4581
++#define mmCRTC_H_SYNC_A                                                         0x1b82
++#define mmCRTC0_CRTC_H_SYNC_A                                                   0x1b82
++#define mmCRTC1_CRTC_H_SYNC_A                                                   0x1d82
++#define mmCRTC2_CRTC_H_SYNC_A                                                   0x1f82
++#define mmCRTC3_CRTC_H_SYNC_A                                                   0x4182
++#define mmCRTC4_CRTC_H_SYNC_A                                                   0x4382
++#define mmCRTC5_CRTC_H_SYNC_A                                                   0x4582
++#define mmCRTC_H_SYNC_A_CNTL                                                    0x1b83
++#define mmCRTC0_CRTC_H_SYNC_A_CNTL                                              0x1b83
++#define mmCRTC1_CRTC_H_SYNC_A_CNTL                                              0x1d83
++#define mmCRTC2_CRTC_H_SYNC_A_CNTL                                              0x1f83
++#define mmCRTC3_CRTC_H_SYNC_A_CNTL                                              0x4183
++#define mmCRTC4_CRTC_H_SYNC_A_CNTL                                              0x4383
++#define mmCRTC5_CRTC_H_SYNC_A_CNTL                                              0x4583
++#define mmCRTC_H_SYNC_B                                                         0x1b84
++#define mmCRTC0_CRTC_H_SYNC_B                                                   0x1b84
++#define mmCRTC1_CRTC_H_SYNC_B                                                   0x1d84
++#define mmCRTC2_CRTC_H_SYNC_B                                                   0x1f84
++#define mmCRTC3_CRTC_H_SYNC_B                                                   0x4184
++#define mmCRTC4_CRTC_H_SYNC_B                                                   0x4384
++#define mmCRTC5_CRTC_H_SYNC_B                                                   0x4584
++#define mmCRTC_H_SYNC_B_CNTL                                                    0x1b85
++#define mmCRTC0_CRTC_H_SYNC_B_CNTL                                              0x1b85
++#define mmCRTC1_CRTC_H_SYNC_B_CNTL                                              0x1d85
++#define mmCRTC2_CRTC_H_SYNC_B_CNTL                                              0x1f85
++#define mmCRTC3_CRTC_H_SYNC_B_CNTL                                              0x4185
++#define mmCRTC4_CRTC_H_SYNC_B_CNTL                                              0x4385
++#define mmCRTC5_CRTC_H_SYNC_B_CNTL                                              0x4585
++#define mmCRTC_VBI_END                                                          0x1b86
++#define mmCRTC0_CRTC_VBI_END                                                    0x1b86
++#define mmCRTC1_CRTC_VBI_END                                                    0x1d86
++#define mmCRTC2_CRTC_VBI_END                                                    0x1f86
++#define mmCRTC3_CRTC_VBI_END                                                    0x4186
++#define mmCRTC4_CRTC_VBI_END                                                    0x4386
++#define mmCRTC5_CRTC_VBI_END                                                    0x4586
++#define mmCRTC_V_TOTAL                                                          0x1b87
++#define mmCRTC0_CRTC_V_TOTAL                                                    0x1b87
++#define mmCRTC1_CRTC_V_TOTAL                                                    0x1d87
++#define mmCRTC2_CRTC_V_TOTAL                                                    0x1f87
++#define mmCRTC3_CRTC_V_TOTAL                                                    0x4187
++#define mmCRTC4_CRTC_V_TOTAL                                                    0x4387
++#define mmCRTC5_CRTC_V_TOTAL                                                    0x4587
++#define mmCRTC_V_TOTAL_MIN                                                      0x1b88
++#define mmCRTC0_CRTC_V_TOTAL_MIN                                                0x1b88
++#define mmCRTC1_CRTC_V_TOTAL_MIN                                                0x1d88
++#define mmCRTC2_CRTC_V_TOTAL_MIN                                                0x1f88
++#define mmCRTC3_CRTC_V_TOTAL_MIN                                                0x4188
++#define mmCRTC4_CRTC_V_TOTAL_MIN                                                0x4388
++#define mmCRTC5_CRTC_V_TOTAL_MIN                                                0x4588
++#define mmCRTC_V_TOTAL_MAX                                                      0x1b89
++#define mmCRTC0_CRTC_V_TOTAL_MAX                                                0x1b89
++#define mmCRTC1_CRTC_V_TOTAL_MAX                                                0x1d89
++#define mmCRTC2_CRTC_V_TOTAL_MAX                                                0x1f89
++#define mmCRTC3_CRTC_V_TOTAL_MAX                                                0x4189
++#define mmCRTC4_CRTC_V_TOTAL_MAX                                                0x4389
++#define mmCRTC5_CRTC_V_TOTAL_MAX                                                0x4589
++#define mmCRTC_V_TOTAL_CONTROL                                                  0x1b8a
++#define mmCRTC0_CRTC_V_TOTAL_CONTROL                                            0x1b8a
++#define mmCRTC1_CRTC_V_TOTAL_CONTROL                                            0x1d8a
++#define mmCRTC2_CRTC_V_TOTAL_CONTROL                                            0x1f8a
++#define mmCRTC3_CRTC_V_TOTAL_CONTROL                                            0x418a
++#define mmCRTC4_CRTC_V_TOTAL_CONTROL                                            0x438a
++#define mmCRTC5_CRTC_V_TOTAL_CONTROL                                            0x458a
++#define mmCRTC_V_TOTAL_INT_STATUS                                               0x1b8b
++#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                         0x1b8b
++#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                         0x1d8b
++#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                         0x1f8b
++#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                         0x418b
++#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                         0x438b
++#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                         0x458b
++#define mmCRTC_VSYNC_NOM_INT_STATUS                                             0x1b8c
++#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                       0x1b8c
++#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                       0x1d8c
++#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                       0x1f8c
++#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                       0x418c
++#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                       0x438c
++#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                       0x458c
++#define mmCRTC_V_BLANK_START_END                                                0x1b8d
++#define mmCRTC0_CRTC_V_BLANK_START_END                                          0x1b8d
++#define mmCRTC1_CRTC_V_BLANK_START_END                                          0x1d8d
++#define mmCRTC2_CRTC_V_BLANK_START_END                                          0x1f8d
++#define mmCRTC3_CRTC_V_BLANK_START_END                                          0x418d
++#define mmCRTC4_CRTC_V_BLANK_START_END                                          0x438d
++#define mmCRTC5_CRTC_V_BLANK_START_END                                          0x458d
++#define mmCRTC_V_SYNC_A                                                         0x1b8e
++#define mmCRTC0_CRTC_V_SYNC_A                                                   0x1b8e
++#define mmCRTC1_CRTC_V_SYNC_A                                                   0x1d8e
++#define mmCRTC2_CRTC_V_SYNC_A                                                   0x1f8e
++#define mmCRTC3_CRTC_V_SYNC_A                                                   0x418e
++#define mmCRTC4_CRTC_V_SYNC_A                                                   0x438e
++#define mmCRTC5_CRTC_V_SYNC_A                                                   0x458e
++#define mmCRTC_V_SYNC_A_CNTL                                                    0x1b8f
++#define mmCRTC0_CRTC_V_SYNC_A_CNTL                                              0x1b8f
++#define mmCRTC1_CRTC_V_SYNC_A_CNTL                                              0x1d8f
++#define mmCRTC2_CRTC_V_SYNC_A_CNTL                                              0x1f8f
++#define mmCRTC3_CRTC_V_SYNC_A_CNTL                                              0x418f
++#define mmCRTC4_CRTC_V_SYNC_A_CNTL                                              0x438f
++#define mmCRTC5_CRTC_V_SYNC_A_CNTL                                              0x458f
++#define mmCRTC_V_SYNC_B                                                         0x1b90
++#define mmCRTC0_CRTC_V_SYNC_B                                                   0x1b90
++#define mmCRTC1_CRTC_V_SYNC_B                                                   0x1d90
++#define mmCRTC2_CRTC_V_SYNC_B                                                   0x1f90
++#define mmCRTC3_CRTC_V_SYNC_B                                                   0x4190
++#define mmCRTC4_CRTC_V_SYNC_B                                                   0x4390
++#define mmCRTC5_CRTC_V_SYNC_B                                                   0x4590
++#define mmCRTC_V_SYNC_B_CNTL                                                    0x1b91
++#define mmCRTC0_CRTC_V_SYNC_B_CNTL                                              0x1b91
++#define mmCRTC1_CRTC_V_SYNC_B_CNTL                                              0x1d91
++#define mmCRTC2_CRTC_V_SYNC_B_CNTL                                              0x1f91
++#define mmCRTC3_CRTC_V_SYNC_B_CNTL                                              0x4191
++#define mmCRTC4_CRTC_V_SYNC_B_CNTL                                              0x4391
++#define mmCRTC5_CRTC_V_SYNC_B_CNTL                                              0x4591
++#define mmCRTC_DTMTEST_CNTL                                                     0x1b92
++#define mmCRTC0_CRTC_DTMTEST_CNTL                                               0x1b92
++#define mmCRTC1_CRTC_DTMTEST_CNTL                                               0x1d92
++#define mmCRTC2_CRTC_DTMTEST_CNTL                                               0x1f92
++#define mmCRTC3_CRTC_DTMTEST_CNTL                                               0x4192
++#define mmCRTC4_CRTC_DTMTEST_CNTL                                               0x4392
++#define mmCRTC5_CRTC_DTMTEST_CNTL                                               0x4592
++#define mmCRTC_DTMTEST_STATUS_POSITION                                          0x1b93
++#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                    0x1b93
++#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                    0x1d93
++#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                    0x1f93
++#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                    0x4193
++#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                    0x4393
++#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                    0x4593
++#define mmCRTC_TRIGA_CNTL                                                       0x1b94
++#define mmCRTC0_CRTC_TRIGA_CNTL                                                 0x1b94
++#define mmCRTC1_CRTC_TRIGA_CNTL                                                 0x1d94
++#define mmCRTC2_CRTC_TRIGA_CNTL                                                 0x1f94
++#define mmCRTC3_CRTC_TRIGA_CNTL                                                 0x4194
++#define mmCRTC4_CRTC_TRIGA_CNTL                                                 0x4394
++#define mmCRTC5_CRTC_TRIGA_CNTL                                                 0x4594
++#define mmCRTC_TRIGA_MANUAL_TRIG                                                0x1b95
++#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                          0x1b95
++#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                          0x1d95
++#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                          0x1f95
++#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                          0x4195
++#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                          0x4395
++#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                          0x4595
++#define mmCRTC_TRIGB_CNTL                                                       0x1b96
++#define mmCRTC0_CRTC_TRIGB_CNTL                                                 0x1b96
++#define mmCRTC1_CRTC_TRIGB_CNTL                                                 0x1d96
++#define mmCRTC2_CRTC_TRIGB_CNTL                                                 0x1f96
++#define mmCRTC3_CRTC_TRIGB_CNTL                                                 0x4196
++#define mmCRTC4_CRTC_TRIGB_CNTL                                                 0x4396
++#define mmCRTC5_CRTC_TRIGB_CNTL                                                 0x4596
++#define mmCRTC_TRIGB_MANUAL_TRIG                                                0x1b97
++#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                          0x1b97
++#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                          0x1d97
++#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                          0x1f97
++#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                          0x4197
++#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                          0x4397
++#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                          0x4597
++#define mmCRTC_FORCE_COUNT_NOW_CNTL                                             0x1b98
++#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1b98
++#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1d98
++#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1f98
++#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4198
++#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4398
++#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4598
++#define mmCRTC_FLOW_CONTROL                                                     0x1b99
++#define mmCRTC0_CRTC_FLOW_CONTROL                                               0x1b99
++#define mmCRTC1_CRTC_FLOW_CONTROL                                               0x1d99
++#define mmCRTC2_CRTC_FLOW_CONTROL                                               0x1f99
++#define mmCRTC3_CRTC_FLOW_CONTROL                                               0x4199
++#define mmCRTC4_CRTC_FLOW_CONTROL                                               0x4399
++#define mmCRTC5_CRTC_FLOW_CONTROL                                               0x4599
++#define mmCRTC_STEREO_FORCE_NEXT_EYE                                            0x1b9a
++#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1b9a
++#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1d9a
++#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1f9a
++#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                      0x419a
++#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                      0x439a
++#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                      0x459a
++#define mmCRTC_AVSYNC_COUNTER                                                   0x1b9b
++#define mmCRTC0_CRTC_AVSYNC_COUNTER                                             0x1b9b
++#define mmCRTC1_CRTC_AVSYNC_COUNTER                                             0x1d9b
++#define mmCRTC2_CRTC_AVSYNC_COUNTER                                             0x1f9b
++#define mmCRTC3_CRTC_AVSYNC_COUNTER                                             0x419b
++#define mmCRTC4_CRTC_AVSYNC_COUNTER                                             0x439b
++#define mmCRTC5_CRTC_AVSYNC_COUNTER                                             0x459b
++#define mmCRTC_CONTROL                                                          0x1b9c
++#define mmCRTC0_CRTC_CONTROL                                                    0x1b9c
++#define mmCRTC1_CRTC_CONTROL                                                    0x1d9c
++#define mmCRTC2_CRTC_CONTROL                                                    0x1f9c
++#define mmCRTC3_CRTC_CONTROL                                                    0x419c
++#define mmCRTC4_CRTC_CONTROL                                                    0x439c
++#define mmCRTC5_CRTC_CONTROL                                                    0x459c
++#define mmCRTC_BLANK_CONTROL                                                    0x1b9d
++#define mmCRTC0_CRTC_BLANK_CONTROL                                              0x1b9d
++#define mmCRTC1_CRTC_BLANK_CONTROL                                              0x1d9d
++#define mmCRTC2_CRTC_BLANK_CONTROL                                              0x1f9d
++#define mmCRTC3_CRTC_BLANK_CONTROL                                              0x419d
++#define mmCRTC4_CRTC_BLANK_CONTROL                                              0x439d
++#define mmCRTC5_CRTC_BLANK_CONTROL                                              0x459d
++#define mmCRTC_INTERLACE_CONTROL                                                0x1b9e
++#define mmCRTC0_CRTC_INTERLACE_CONTROL                                          0x1b9e
++#define mmCRTC1_CRTC_INTERLACE_CONTROL                                          0x1d9e
++#define mmCRTC2_CRTC_INTERLACE_CONTROL                                          0x1f9e
++#define mmCRTC3_CRTC_INTERLACE_CONTROL                                          0x419e
++#define mmCRTC4_CRTC_INTERLACE_CONTROL                                          0x439e
++#define mmCRTC5_CRTC_INTERLACE_CONTROL                                          0x459e
++#define mmCRTC_INTERLACE_STATUS                                                 0x1b9f
++#define mmCRTC0_CRTC_INTERLACE_STATUS                                           0x1b9f
++#define mmCRTC1_CRTC_INTERLACE_STATUS                                           0x1d9f
++#define mmCRTC2_CRTC_INTERLACE_STATUS                                           0x1f9f
++#define mmCRTC3_CRTC_INTERLACE_STATUS                                           0x419f
++#define mmCRTC4_CRTC_INTERLACE_STATUS                                           0x439f
++#define mmCRTC5_CRTC_INTERLACE_STATUS                                           0x459f
++#define mmCRTC_FIELD_INDICATION_CONTROL                                         0x1ba0
++#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                   0x1ba0
++#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                   0x1da0
++#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                   0x1fa0
++#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                   0x41a0
++#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                   0x43a0
++#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                   0x45a0
++#define mmCRTC_PIXEL_DATA_READBACK0                                             0x1ba1
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                       0x1ba1
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                       0x1da1
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                       0x1fa1
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                       0x41a1
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                       0x43a1
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                       0x45a1
++#define mmCRTC_PIXEL_DATA_READBACK1                                             0x1ba2
++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                       0x1ba2
++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                       0x1da2
++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                       0x1fa2
++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                       0x41a2
++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                       0x43a2
++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                       0x45a2
++#define mmCRTC_STATUS                                                           0x1ba3
++#define mmCRTC0_CRTC_STATUS                                                     0x1ba3
++#define mmCRTC1_CRTC_STATUS                                                     0x1da3
++#define mmCRTC2_CRTC_STATUS                                                     0x1fa3
++#define mmCRTC3_CRTC_STATUS                                                     0x41a3
++#define mmCRTC4_CRTC_STATUS                                                     0x43a3
++#define mmCRTC5_CRTC_STATUS                                                     0x45a3
++#define mmCRTC_STATUS_POSITION                                                  0x1ba4
++#define mmCRTC0_CRTC_STATUS_POSITION                                            0x1ba4
++#define mmCRTC1_CRTC_STATUS_POSITION                                            0x1da4
++#define mmCRTC2_CRTC_STATUS_POSITION                                            0x1fa4
++#define mmCRTC3_CRTC_STATUS_POSITION                                            0x41a4
++#define mmCRTC4_CRTC_STATUS_POSITION                                            0x43a4
++#define mmCRTC5_CRTC_STATUS_POSITION                                            0x45a4
++#define mmCRTC_NOM_VERT_POSITION                                                0x1ba5
++#define mmCRTC0_CRTC_NOM_VERT_POSITION                                          0x1ba5
++#define mmCRTC1_CRTC_NOM_VERT_POSITION                                          0x1da5
++#define mmCRTC2_CRTC_NOM_VERT_POSITION                                          0x1fa5
++#define mmCRTC3_CRTC_NOM_VERT_POSITION                                          0x41a5
++#define mmCRTC4_CRTC_NOM_VERT_POSITION                                          0x43a5
++#define mmCRTC5_CRTC_NOM_VERT_POSITION                                          0x45a5
++#define mmCRTC_STATUS_FRAME_COUNT                                               0x1ba6
++#define mmCRTC0_CRTC_STATUS_FRAME_COUNT                                         0x1ba6
++#define mmCRTC1_CRTC_STATUS_FRAME_COUNT                                         0x1da6
++#define mmCRTC2_CRTC_STATUS_FRAME_COUNT                                         0x1fa6
++#define mmCRTC3_CRTC_STATUS_FRAME_COUNT                                         0x41a6
++#define mmCRTC4_CRTC_STATUS_FRAME_COUNT                                         0x43a6
++#define mmCRTC5_CRTC_STATUS_FRAME_COUNT                                         0x45a6
++#define mmCRTC_STATUS_VF_COUNT                                                  0x1ba7
++#define mmCRTC0_CRTC_STATUS_VF_COUNT                                            0x1ba7
++#define mmCRTC1_CRTC_STATUS_VF_COUNT                                            0x1da7
++#define mmCRTC2_CRTC_STATUS_VF_COUNT                                            0x1fa7
++#define mmCRTC3_CRTC_STATUS_VF_COUNT                                            0x41a7
++#define mmCRTC4_CRTC_STATUS_VF_COUNT                                            0x43a7
++#define mmCRTC5_CRTC_STATUS_VF_COUNT                                            0x45a7
++#define mmCRTC_STATUS_HV_COUNT                                                  0x1ba8
++#define mmCRTC0_CRTC_STATUS_HV_COUNT                                            0x1ba8
++#define mmCRTC1_CRTC_STATUS_HV_COUNT                                            0x1da8
++#define mmCRTC2_CRTC_STATUS_HV_COUNT                                            0x1fa8
++#define mmCRTC3_CRTC_STATUS_HV_COUNT                                            0x41a8
++#define mmCRTC4_CRTC_STATUS_HV_COUNT                                            0x43a8
++#define mmCRTC5_CRTC_STATUS_HV_COUNT                                            0x45a8
++#define mmCRTC_COUNT_CONTROL                                                    0x1ba9
++#define mmCRTC0_CRTC_COUNT_CONTROL                                              0x1ba9
++#define mmCRTC1_CRTC_COUNT_CONTROL                                              0x1da9
++#define mmCRTC2_CRTC_COUNT_CONTROL                                              0x1fa9
++#define mmCRTC3_CRTC_COUNT_CONTROL                                              0x41a9
++#define mmCRTC4_CRTC_COUNT_CONTROL                                              0x43a9
++#define mmCRTC5_CRTC_COUNT_CONTROL                                              0x45a9
++#define mmCRTC_COUNT_RESET                                                      0x1baa
++#define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
++#define mmCRTC1_CRTC_COUNT_RESET                                                0x1daa
++#define mmCRTC2_CRTC_COUNT_RESET                                                0x1faa
++#define mmCRTC3_CRTC_COUNT_RESET                                                0x41aa
++#define mmCRTC4_CRTC_COUNT_RESET                                                0x43aa
++#define mmCRTC5_CRTC_COUNT_RESET                                                0x45aa
++#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                     0x1bab
++#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1bab
++#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1dab
++#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1fab
++#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x41ab
++#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x43ab
++#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x45ab
++#define mmCRTC_VERT_SYNC_CONTROL                                                0x1bac
++#define mmCRTC0_CRTC_VERT_SYNC_CONTROL                                          0x1bac
++#define mmCRTC1_CRTC_VERT_SYNC_CONTROL                                          0x1dac
++#define mmCRTC2_CRTC_VERT_SYNC_CONTROL                                          0x1fac
++#define mmCRTC3_CRTC_VERT_SYNC_CONTROL                                          0x41ac
++#define mmCRTC4_CRTC_VERT_SYNC_CONTROL                                          0x43ac
++#define mmCRTC5_CRTC_VERT_SYNC_CONTROL                                          0x45ac
++#define mmCRTC_STEREO_STATUS                                                    0x1bad
++#define mmCRTC0_CRTC_STEREO_STATUS                                              0x1bad
++#define mmCRTC1_CRTC_STEREO_STATUS                                              0x1dad
++#define mmCRTC2_CRTC_STEREO_STATUS                                              0x1fad
++#define mmCRTC3_CRTC_STEREO_STATUS                                              0x41ad
++#define mmCRTC4_CRTC_STEREO_STATUS                                              0x43ad
++#define mmCRTC5_CRTC_STEREO_STATUS                                              0x45ad
++#define mmCRTC_STEREO_CONTROL                                                   0x1bae
++#define mmCRTC0_CRTC_STEREO_CONTROL                                             0x1bae
++#define mmCRTC1_CRTC_STEREO_CONTROL                                             0x1dae
++#define mmCRTC2_CRTC_STEREO_CONTROL                                             0x1fae
++#define mmCRTC3_CRTC_STEREO_CONTROL                                             0x41ae
++#define mmCRTC4_CRTC_STEREO_CONTROL                                             0x43ae
++#define mmCRTC5_CRTC_STEREO_CONTROL                                             0x45ae
++#define mmCRTC_SNAPSHOT_STATUS                                                  0x1baf
++#define mmCRTC0_CRTC_SNAPSHOT_STATUS                                            0x1baf
++#define mmCRTC1_CRTC_SNAPSHOT_STATUS                                            0x1daf
++#define mmCRTC2_CRTC_SNAPSHOT_STATUS                                            0x1faf
++#define mmCRTC3_CRTC_SNAPSHOT_STATUS                                            0x41af
++#define mmCRTC4_CRTC_SNAPSHOT_STATUS                                            0x43af
++#define mmCRTC5_CRTC_SNAPSHOT_STATUS                                            0x45af
++#define mmCRTC_SNAPSHOT_CONTROL                                                 0x1bb0
++#define mmCRTC0_CRTC_SNAPSHOT_CONTROL                                           0x1bb0
++#define mmCRTC1_CRTC_SNAPSHOT_CONTROL                                           0x1db0
++#define mmCRTC2_CRTC_SNAPSHOT_CONTROL                                           0x1fb0
++#define mmCRTC3_CRTC_SNAPSHOT_CONTROL                                           0x41b0
++#define mmCRTC4_CRTC_SNAPSHOT_CONTROL                                           0x43b0
++#define mmCRTC5_CRTC_SNAPSHOT_CONTROL                                           0x45b0
++#define mmCRTC_SNAPSHOT_POSITION                                                0x1bb1
++#define mmCRTC0_CRTC_SNAPSHOT_POSITION                                          0x1bb1
++#define mmCRTC1_CRTC_SNAPSHOT_POSITION                                          0x1db1
++#define mmCRTC2_CRTC_SNAPSHOT_POSITION                                          0x1fb1
++#define mmCRTC3_CRTC_SNAPSHOT_POSITION                                          0x41b1
++#define mmCRTC4_CRTC_SNAPSHOT_POSITION                                          0x43b1
++#define mmCRTC5_CRTC_SNAPSHOT_POSITION                                          0x45b1
++#define mmCRTC_SNAPSHOT_FRAME                                                   0x1bb2
++#define mmCRTC0_CRTC_SNAPSHOT_FRAME                                             0x1bb2
++#define mmCRTC1_CRTC_SNAPSHOT_FRAME                                             0x1db2
++#define mmCRTC2_CRTC_SNAPSHOT_FRAME                                             0x1fb2
++#define mmCRTC3_CRTC_SNAPSHOT_FRAME                                             0x41b2
++#define mmCRTC4_CRTC_SNAPSHOT_FRAME                                             0x43b2
++#define mmCRTC5_CRTC_SNAPSHOT_FRAME                                             0x45b2
++#define mmCRTC_START_LINE_CONTROL                                               0x1bb3
++#define mmCRTC0_CRTC_START_LINE_CONTROL                                         0x1bb3
++#define mmCRTC1_CRTC_START_LINE_CONTROL                                         0x1db3
++#define mmCRTC2_CRTC_START_LINE_CONTROL                                         0x1fb3
++#define mmCRTC3_CRTC_START_LINE_CONTROL                                         0x41b3
++#define mmCRTC4_CRTC_START_LINE_CONTROL                                         0x43b3
++#define mmCRTC5_CRTC_START_LINE_CONTROL                                         0x45b3
++#define mmCRTC_INTERRUPT_CONTROL                                                0x1bb4
++#define mmCRTC0_CRTC_INTERRUPT_CONTROL                                          0x1bb4
++#define mmCRTC1_CRTC_INTERRUPT_CONTROL                                          0x1db4
++#define mmCRTC2_CRTC_INTERRUPT_CONTROL                                          0x1fb4
++#define mmCRTC3_CRTC_INTERRUPT_CONTROL                                          0x41b4
++#define mmCRTC4_CRTC_INTERRUPT_CONTROL                                          0x43b4
++#define mmCRTC5_CRTC_INTERRUPT_CONTROL                                          0x45b4
++#define mmCRTC_UPDATE_LOCK                                                      0x1bb5
++#define mmCRTC0_CRTC_UPDATE_LOCK                                                0x1bb5
++#define mmCRTC1_CRTC_UPDATE_LOCK                                                0x1db5
++#define mmCRTC2_CRTC_UPDATE_LOCK                                                0x1fb5
++#define mmCRTC3_CRTC_UPDATE_LOCK                                                0x41b5
++#define mmCRTC4_CRTC_UPDATE_LOCK                                                0x43b5
++#define mmCRTC5_CRTC_UPDATE_LOCK                                                0x45b5
++#define mmCRTC_DOUBLE_BUFFER_CONTROL                                            0x1bb6
++#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1bb6
++#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1db6
++#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1fb6
++#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                      0x41b6
++#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                      0x43b6
++#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                      0x45b6
++#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE                                       0x1bb7
++#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1bb7
++#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1db7
++#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1fb7
++#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x41b7
++#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x43b7
++#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x45b7
++#define mmCRTC_TEST_PATTERN_CONTROL                                             0x1bba
++#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                       0x1bba
++#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                       0x1dba
++#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                       0x1fba
++#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                       0x41ba
++#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                       0x43ba
++#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                       0x45ba
++#define mmCRTC_TEST_PATTERN_PARAMETERS                                          0x1bbb
++#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                    0x1bbb
++#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                    0x1dbb
++#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                    0x1fbb
++#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                    0x41bb
++#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                    0x43bb
++#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                    0x45bb
++#define mmCRTC_TEST_PATTERN_COLOR                                               0x1bbc
++#define mmCRTC0_CRTC_TEST_PATTERN_COLOR                                         0x1bbc
++#define mmCRTC1_CRTC_TEST_PATTERN_COLOR                                         0x1dbc
++#define mmCRTC2_CRTC_TEST_PATTERN_COLOR                                         0x1fbc
++#define mmCRTC3_CRTC_TEST_PATTERN_COLOR                                         0x41bc
++#define mmCRTC4_CRTC_TEST_PATTERN_COLOR                                         0x43bc
++#define mmCRTC5_CRTC_TEST_PATTERN_COLOR                                         0x45bc
++#define mmCRTC_MASTER_UPDATE_LOCK                                               0x1bbd
++#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK                                         0x1bbd
++#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK                                         0x1dbd
++#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK                                         0x1fbd
++#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK                                         0x41bd
++#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK                                         0x43bd
++#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK                                         0x45bd
++#define mmCRTC_MASTER_UPDATE_MODE                                               0x1bbe
++#define mmCRTC0_CRTC_MASTER_UPDATE_MODE                                         0x1bbe
++#define mmCRTC1_CRTC_MASTER_UPDATE_MODE                                         0x1dbe
++#define mmCRTC2_CRTC_MASTER_UPDATE_MODE                                         0x1fbe
++#define mmCRTC3_CRTC_MASTER_UPDATE_MODE                                         0x41be
++#define mmCRTC4_CRTC_MASTER_UPDATE_MODE                                         0x43be
++#define mmCRTC5_CRTC_MASTER_UPDATE_MODE                                         0x45be
++#define mmCRTC_MVP_INBAND_CNTL_INSERT                                           0x1bbf
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1bbf
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1dbf
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1fbf
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                     0x41bf
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                     0x43bf
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                     0x45bf
++#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER                                     0x1bc0
++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1bc0
++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1dc0
++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1fc0
++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x41c0
++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x43c0
++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x45c0
++#define mmCRTC_MVP_STATUS                                                       0x1bc1
++#define mmCRTC0_CRTC_MVP_STATUS                                                 0x1bc1
++#define mmCRTC1_CRTC_MVP_STATUS                                                 0x1dc1
++#define mmCRTC2_CRTC_MVP_STATUS                                                 0x1fc1
++#define mmCRTC3_CRTC_MVP_STATUS                                                 0x41c1
++#define mmCRTC4_CRTC_MVP_STATUS                                                 0x43c1
++#define mmCRTC5_CRTC_MVP_STATUS                                                 0x45c1
++#define mmCRTC_MASTER_EN                                                        0x1bc2
++#define mmCRTC0_CRTC_MASTER_EN                                                  0x1bc2
++#define mmCRTC1_CRTC_MASTER_EN                                                  0x1dc2
++#define mmCRTC2_CRTC_MASTER_EN                                                  0x1fc2
++#define mmCRTC3_CRTC_MASTER_EN                                                  0x41c2
++#define mmCRTC4_CRTC_MASTER_EN                                                  0x43c2
++#define mmCRTC5_CRTC_MASTER_EN                                                  0x45c2
++#define mmCRTC_ALLOW_STOP_OFF_V_CNT                                             0x1bc3
++#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1bc3
++#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1dc3
++#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1fc3
++#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x41c3
++#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x43c3
++#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x45c3
++#define mmCRTC_V_UPDATE_INT_STATUS                                              0x1bc4
++#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                        0x1bc4
++#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                        0x1dc4
++#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                        0x1fc4
++#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                        0x41c4
++#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                        0x43c4
++#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                        0x45c4
++#define mmCRTC_OVERSCAN_COLOR                                                   0x1bc8
++#define mmCRTC0_CRTC_OVERSCAN_COLOR                                             0x1bc8
++#define mmCRTC1_CRTC_OVERSCAN_COLOR                                             0x1dc8
++#define mmCRTC2_CRTC_OVERSCAN_COLOR                                             0x1fc8
++#define mmCRTC3_CRTC_OVERSCAN_COLOR                                             0x41c8
++#define mmCRTC4_CRTC_OVERSCAN_COLOR                                             0x43c8
++#define mmCRTC5_CRTC_OVERSCAN_COLOR                                             0x45c8
++#define mmCRTC_OVERSCAN_COLOR_EXT                                               0x1bc9
++#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                         0x1bc9
++#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                         0x1dc9
++#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                         0x1fc9
++#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                         0x41c9
++#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                         0x43c9
++#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                         0x45c9
++#define mmCRTC_BLANK_DATA_COLOR                                                 0x1bca
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR                                           0x1bca
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR                                           0x1dca
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR                                           0x1fca
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR                                           0x41ca
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR                                           0x43ca
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR                                           0x45ca
++#define mmCRTC_BLANK_DATA_COLOR_EXT                                             0x1bcb
++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                       0x1bcb
++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                       0x1dcb
++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                       0x1fcb
++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                       0x41cb
++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                       0x43cb
++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                       0x45cb
++#define mmCRTC_BLACK_COLOR                                                      0x1bcc
++#define mmCRTC0_CRTC_BLACK_COLOR                                                0x1bcc
++#define mmCRTC1_CRTC_BLACK_COLOR                                                0x1dcc
++#define mmCRTC2_CRTC_BLACK_COLOR                                                0x1fcc
++#define mmCRTC3_CRTC_BLACK_COLOR                                                0x41cc
++#define mmCRTC4_CRTC_BLACK_COLOR                                                0x43cc
++#define mmCRTC5_CRTC_BLACK_COLOR                                                0x45cc
++#define mmCRTC_BLACK_COLOR_EXT                                                  0x1bcd
++#define mmCRTC0_CRTC_BLACK_COLOR_EXT                                            0x1bcd
++#define mmCRTC1_CRTC_BLACK_COLOR_EXT                                            0x1dcd
++#define mmCRTC2_CRTC_BLACK_COLOR_EXT                                            0x1fcd
++#define mmCRTC3_CRTC_BLACK_COLOR_EXT                                            0x41cd
++#define mmCRTC4_CRTC_BLACK_COLOR_EXT                                            0x43cd
++#define mmCRTC5_CRTC_BLACK_COLOR_EXT                                            0x45cd
++#define mmCRTC_VERTICAL_INTERRUPT0_POSITION                                     0x1bce
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1bce
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1dce
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1fce
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x41ce
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x43ce
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x45ce
++#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL                                      0x1bcf
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1bcf
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1dcf
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1fcf
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x41cf
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x43cf
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x45cf
++#define mmCRTC_VERTICAL_INTERRUPT1_POSITION                                     0x1bd0
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1bd0
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1dd0
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1fd0
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x41d0
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x43d0
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x45d0
++#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL                                      0x1bd1
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1bd1
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1dd1
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1fd1
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x41d1
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x43d1
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x45d1
++#define mmCRTC_VERTICAL_INTERRUPT2_POSITION                                     0x1bd2
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1bd2
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1dd2
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1fd2
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x41d2
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x43d2
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x45d2
++#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL                                      0x1bd3
++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1bd3
++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1dd3
++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1fd3
++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x41d3
++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x43d3
++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x45d3
++#define mmCRTC_CRC_CNTL                                                         0x1bd4
++#define mmCRTC0_CRTC_CRC_CNTL                                                   0x1bd4
++#define mmCRTC1_CRTC_CRC_CNTL                                                   0x1dd4
++#define mmCRTC2_CRTC_CRC_CNTL                                                   0x1fd4
++#define mmCRTC3_CRTC_CRC_CNTL                                                   0x41d4
++#define mmCRTC4_CRTC_CRC_CNTL                                                   0x43d4
++#define mmCRTC5_CRTC_CRC_CNTL                                                   0x45d4
++#define mmCRTC_CRC0_WINDOWA_X_CONTROL                                           0x1bd5
++#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1bd5
++#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1dd5
++#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1fd5
++#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x41d5
++#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x43d5
++#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x45d5
++#define mmCRTC_CRC0_WINDOWA_Y_CONTROL                                           0x1bd6
++#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1bd6
++#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1dd6
++#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1fd6
++#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x41d6
++#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x43d6
++#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x45d6
++#define mmCRTC_CRC0_WINDOWB_X_CONTROL                                           0x1bd7
++#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1bd7
++#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1dd7
++#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1fd7
++#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x41d7
++#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x43d7
++#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x45d7
++#define mmCRTC_CRC0_WINDOWB_Y_CONTROL                                           0x1bd8
++#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1bd8
++#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1dd8
++#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1fd8
++#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x41d8
++#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x43d8
++#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x45d8
++#define mmCRTC_CRC0_DATA_RG                                                     0x1bd9
++#define mmCRTC0_CRTC_CRC0_DATA_RG                                               0x1bd9
++#define mmCRTC1_CRTC_CRC0_DATA_RG                                               0x1dd9
++#define mmCRTC2_CRTC_CRC0_DATA_RG                                               0x1fd9
++#define mmCRTC3_CRTC_CRC0_DATA_RG                                               0x41d9
++#define mmCRTC4_CRTC_CRC0_DATA_RG                                               0x43d9
++#define mmCRTC5_CRTC_CRC0_DATA_RG                                               0x45d9
++#define mmCRTC_CRC0_DATA_B                                                      0x1bda
++#define mmCRTC0_CRTC_CRC0_DATA_B                                                0x1bda
++#define mmCRTC1_CRTC_CRC0_DATA_B                                                0x1dda
++#define mmCRTC2_CRTC_CRC0_DATA_B                                                0x1fda
++#define mmCRTC3_CRTC_CRC0_DATA_B                                                0x41da
++#define mmCRTC4_CRTC_CRC0_DATA_B                                                0x43da
++#define mmCRTC5_CRTC_CRC0_DATA_B                                                0x45da
++#define mmCRTC_CRC1_WINDOWA_X_CONTROL                                           0x1bdb
++#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1bdb
++#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1ddb
++#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1fdb
++#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x41db
++#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x43db
++#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x45db
++#define mmCRTC_CRC1_WINDOWA_Y_CONTROL                                           0x1bdc
++#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1bdc
++#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1ddc
++#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1fdc
++#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x41dc
++#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x43dc
++#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x45dc
++#define mmCRTC_CRC1_WINDOWB_X_CONTROL                                           0x1bdd
++#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1bdd
++#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1ddd
++#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1fdd
++#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x41dd
++#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x43dd
++#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x45dd
++#define mmCRTC_CRC1_WINDOWB_Y_CONTROL                                           0x1bde
++#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1bde
++#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1dde
++#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1fde
++#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x41de
++#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x43de
++#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x45de
++#define mmCRTC_CRC1_DATA_RG                                                     0x1bdf
++#define mmCRTC0_CRTC_CRC1_DATA_RG                                               0x1bdf
++#define mmCRTC1_CRTC_CRC1_DATA_RG                                               0x1ddf
++#define mmCRTC2_CRTC_CRC1_DATA_RG                                               0x1fdf
++#define mmCRTC3_CRTC_CRC1_DATA_RG                                               0x41df
++#define mmCRTC4_CRTC_CRC1_DATA_RG                                               0x43df
++#define mmCRTC5_CRTC_CRC1_DATA_RG                                               0x45df
++#define mmCRTC_CRC1_DATA_B                                                      0x1be0
++#define mmCRTC0_CRTC_CRC1_DATA_B                                                0x1be0
++#define mmCRTC1_CRTC_CRC1_DATA_B                                                0x1de0
++#define mmCRTC2_CRTC_CRC1_DATA_B                                                0x1fe0
++#define mmCRTC3_CRTC_CRC1_DATA_B                                                0x41e0
++#define mmCRTC4_CRTC_CRC1_DATA_B                                                0x43e0
++#define mmCRTC5_CRTC_CRC1_DATA_B                                                0x45e0
++#define mmCRTC_STATIC_SCREEN_CONTROL                                            0x1be7
++#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                      0x1be7
++#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                      0x1de7
++#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                      0x1fe7
++#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                      0x41e7
++#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                      0x43e7
++#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                      0x45e7
++#define mmCRTC_3D_STRUCTURE_CONTROL                                             0x1b78
++#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                       0x1b78
++#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                       0x1d78
++#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                       0x1f78
++#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                       0x4178
++#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                       0x4378
++#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                       0x4578
++#define mmCRTC_GSL_VSYNC_GAP                                                    0x1b79
++#define mmCRTC0_CRTC_GSL_VSYNC_GAP                                              0x1b79
++#define mmCRTC1_CRTC_GSL_VSYNC_GAP                                              0x1d79
++#define mmCRTC2_CRTC_GSL_VSYNC_GAP                                              0x1f79
++#define mmCRTC3_CRTC_GSL_VSYNC_GAP                                              0x4179
++#define mmCRTC4_CRTC_GSL_VSYNC_GAP                                              0x4379
++#define mmCRTC5_CRTC_GSL_VSYNC_GAP                                              0x4579
++#define mmCRTC_GSL_WINDOW                                                       0x1b7a
++#define mmCRTC0_CRTC_GSL_WINDOW                                                 0x1b7a
++#define mmCRTC1_CRTC_GSL_WINDOW                                                 0x1d7a
++#define mmCRTC2_CRTC_GSL_WINDOW                                                 0x1f7a
++#define mmCRTC3_CRTC_GSL_WINDOW                                                 0x417a
++#define mmCRTC4_CRTC_GSL_WINDOW                                                 0x437a
++#define mmCRTC5_CRTC_GSL_WINDOW                                                 0x457a
++#define mmCRTC_GSL_CONTROL                                                      0x1b7b
++#define mmCRTC0_CRTC_GSL_CONTROL                                                0x1b7b
++#define mmCRTC1_CRTC_GSL_CONTROL                                                0x1d7b
++#define mmCRTC2_CRTC_GSL_CONTROL                                                0x1f7b
++#define mmCRTC3_CRTC_GSL_CONTROL                                                0x417b
++#define mmCRTC4_CRTC_GSL_CONTROL                                                0x437b
++#define mmCRTC5_CRTC_GSL_CONTROL                                                0x457b
++#define mmCRTC_TEST_DEBUG_INDEX                                                 0x1bc6
++#define mmCRTC0_CRTC_TEST_DEBUG_INDEX                                           0x1bc6
++#define mmCRTC1_CRTC_TEST_DEBUG_INDEX                                           0x1dc6
++#define mmCRTC2_CRTC_TEST_DEBUG_INDEX                                           0x1fc6
++#define mmCRTC3_CRTC_TEST_DEBUG_INDEX                                           0x41c6
++#define mmCRTC4_CRTC_TEST_DEBUG_INDEX                                           0x43c6
++#define mmCRTC5_CRTC_TEST_DEBUG_INDEX                                           0x45c6
++#define mmCRTC_TEST_DEBUG_DATA                                                  0x1bc7
++#define mmCRTC0_CRTC_TEST_DEBUG_DATA                                            0x1bc7
++#define mmCRTC1_CRTC_TEST_DEBUG_DATA                                            0x1dc7
++#define mmCRTC2_CRTC_TEST_DEBUG_DATA                                            0x1fc7
++#define mmCRTC3_CRTC_TEST_DEBUG_DATA                                            0x41c7
++#define mmCRTC4_CRTC_TEST_DEBUG_DATA                                            0x43c7
++#define mmCRTC5_CRTC_TEST_DEBUG_DATA                                            0x45c7
++#define mmDAC_ENABLE                                                            0x16aa
++#define mmDAC_SOURCE_SELECT                                                     0x16ab
++#define mmDAC_CRC_EN                                                            0x16ac
++#define mmDAC_CRC_CONTROL                                                       0x16ad
++#define mmDAC_CRC_SIG_RGB_MASK                                                  0x16ae
++#define mmDAC_CRC_SIG_CONTROL_MASK                                              0x16af
++#define mmDAC_CRC_SIG_RGB                                                       0x16b0
++#define mmDAC_CRC_SIG_CONTROL                                                   0x16b1
++#define mmDAC_SYNC_TRISTATE_CONTROL                                             0x16b2
++#define mmDAC_STEREOSYNC_SELECT                                                 0x16b3
++#define mmDAC_AUTODETECT_CONTROL                                                0x16b4
++#define mmDAC_AUTODETECT_CONTROL2                                               0x16b5
++#define mmDAC_AUTODETECT_CONTROL3                                               0x16b6
++#define mmDAC_AUTODETECT_STATUS                                                 0x16b7
++#define mmDAC_AUTODETECT_INT_CONTROL                                            0x16b8
++#define mmDAC_FORCE_OUTPUT_CNTL                                                 0x16b9
++#define mmDAC_FORCE_DATA                                                        0x16ba
++#define mmDAC_POWERDOWN                                                         0x16bb
++#define mmDAC_CONTROL                                                           0x16bc
++#define mmDAC_COMPARATOR_ENABLE                                                 0x16bd
++#define mmDAC_COMPARATOR_OUTPUT                                                 0x16be
++#define mmDAC_PWR_CNTL                                                          0x16bf
++#define mmDAC_DFT_CONFIG                                                        0x16c0
++#define mmDAC_FIFO_STATUS                                                       0x16c1
++#define mmDAC_TEST_DEBUG_INDEX                                                  0x16c2
++#define mmDAC_TEST_DEBUG_DATA                                                   0x16c3
++#define mmPERFCOUNTER_CNTL                                                      0x170
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                          0x170
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                          0x364
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                          0x18c8
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                          0x1b24
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                          0x1d24
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                          0x1f24
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                          0x4124
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                          0x4324
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                          0x4524
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                          0x4724
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                         0x59a0
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                         0x5f68
++#define mmPERFCOUNTER_STATE                                                     0x171
++#define mmDC_PERFMON0_PERFCOUNTER_STATE                                         0x171
++#define mmDC_PERFMON1_PERFCOUNTER_STATE                                         0x365
++#define mmDC_PERFMON2_PERFCOUNTER_STATE                                         0x18c9
++#define mmDC_PERFMON3_PERFCOUNTER_STATE                                         0x1b25
++#define mmDC_PERFMON4_PERFCOUNTER_STATE                                         0x1d25
++#define mmDC_PERFMON5_PERFCOUNTER_STATE                                         0x1f25
++#define mmDC_PERFMON6_PERFCOUNTER_STATE                                         0x4125
++#define mmDC_PERFMON7_PERFCOUNTER_STATE                                         0x4325
++#define mmDC_PERFMON8_PERFCOUNTER_STATE                                         0x4525
++#define mmDC_PERFMON9_PERFCOUNTER_STATE                                         0x4725
++#define mmDC_PERFMON10_PERFCOUNTER_STATE                                        0x59a1
++#define mmDC_PERFMON11_PERFCOUNTER_STATE                                        0x5f69
++#define mmPERFMON_CNTL                                                          0x173
++#define mmDC_PERFMON0_PERFMON_CNTL                                              0x173
++#define mmDC_PERFMON1_PERFMON_CNTL                                              0x367
++#define mmDC_PERFMON2_PERFMON_CNTL                                              0x18cb
++#define mmDC_PERFMON3_PERFMON_CNTL                                              0x1b27
++#define mmDC_PERFMON4_PERFMON_CNTL                                              0x1d27
++#define mmDC_PERFMON5_PERFMON_CNTL                                              0x1f27
++#define mmDC_PERFMON6_PERFMON_CNTL                                              0x4127
++#define mmDC_PERFMON7_PERFMON_CNTL                                              0x4327
++#define mmDC_PERFMON8_PERFMON_CNTL                                              0x4527
++#define mmDC_PERFMON9_PERFMON_CNTL                                              0x4727
++#define mmDC_PERFMON10_PERFMON_CNTL                                             0x59a3
++#define mmDC_PERFMON11_PERFMON_CNTL                                             0x5f6b
++#define mmPERFMON_CNTL2                                                         0x17a
++#define mmDC_PERFMON0_PERFMON_CNTL2                                             0x17a
++#define mmDC_PERFMON1_PERFMON_CNTL2                                             0x36e
++#define mmDC_PERFMON2_PERFMON_CNTL2                                             0x18d2
++#define mmDC_PERFMON3_PERFMON_CNTL2                                             0x1b2e
++#define mmDC_PERFMON4_PERFMON_CNTL2                                             0x1d2e
++#define mmDC_PERFMON5_PERFMON_CNTL2                                             0x1f2e
++#define mmDC_PERFMON6_PERFMON_CNTL2                                             0x412e
++#define mmDC_PERFMON7_PERFMON_CNTL2                                             0x432e
++#define mmDC_PERFMON8_PERFMON_CNTL2                                             0x452e
++#define mmDC_PERFMON9_PERFMON_CNTL2                                             0x472e
++#define mmDC_PERFMON10_PERFMON_CNTL2                                            0x59aa
++#define mmDC_PERFMON11_PERFMON_CNTL2                                            0x5f72
++#define mmPERFMON_CVALUE_INT_MISC                                               0x172
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                   0x172
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                   0x366
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                   0x18ca
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                   0x1b26
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                   0x1d26
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                   0x1f26
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                   0x4126
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                   0x4326
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                   0x4526
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                   0x4726
++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                  0x59a2
++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                  0x5f6a
++#define mmPERFMON_CVALUE_LOW                                                    0x174
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                        0x174
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                        0x368
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                        0x18cc
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                        0x1b28
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                        0x1d28
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                        0x1f28
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                        0x4128
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                        0x4328
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                        0x4528
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                        0x4728
++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                       0x59a4
++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                       0x5f6c
++#define mmPERFMON_HI                                                            0x175
++#define mmDC_PERFMON0_PERFMON_HI                                                0x175
++#define mmDC_PERFMON1_PERFMON_HI                                                0x369
++#define mmDC_PERFMON2_PERFMON_HI                                                0x18cd
++#define mmDC_PERFMON3_PERFMON_HI                                                0x1b29
++#define mmDC_PERFMON4_PERFMON_HI                                                0x1d29
++#define mmDC_PERFMON5_PERFMON_HI                                                0x1f29
++#define mmDC_PERFMON6_PERFMON_HI                                                0x4129
++#define mmDC_PERFMON7_PERFMON_HI                                                0x4329
++#define mmDC_PERFMON8_PERFMON_HI                                                0x4529
++#define mmDC_PERFMON9_PERFMON_HI                                                0x4729
++#define mmDC_PERFMON10_PERFMON_HI                                               0x59a5
++#define mmDC_PERFMON11_PERFMON_HI                                               0x5f6d
++#define mmPERFMON_LOW                                                           0x176
++#define mmDC_PERFMON0_PERFMON_LOW                                               0x176
++#define mmDC_PERFMON1_PERFMON_LOW                                               0x36a
++#define mmDC_PERFMON2_PERFMON_LOW                                               0x18ce
++#define mmDC_PERFMON3_PERFMON_LOW                                               0x1b2a
++#define mmDC_PERFMON4_PERFMON_LOW                                               0x1d2a
++#define mmDC_PERFMON5_PERFMON_LOW                                               0x1f2a
++#define mmDC_PERFMON6_PERFMON_LOW                                               0x412a
++#define mmDC_PERFMON7_PERFMON_LOW                                               0x432a
++#define mmDC_PERFMON8_PERFMON_LOW                                               0x452a
++#define mmDC_PERFMON9_PERFMON_LOW                                               0x472a
++#define mmDC_PERFMON10_PERFMON_LOW                                              0x59a6
++#define mmDC_PERFMON11_PERFMON_LOW                                              0x5f6e
++#define mmPERFMON_TEST_DEBUG_INDEX                                              0x177
++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX                                  0x177
++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX                                  0x36b
++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX                                  0x18cf
++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX                                  0x1b2b
++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX                                  0x1d2b
++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX                                  0x1f2b
++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                                  0x412b
++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                                  0x432b
++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                                  0x452b
++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                                  0x472b
++#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                                 0x59a7
++#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                                 0x5f6f
++#define mmPERFMON_TEST_DEBUG_DATA                                               0x178
++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA                                   0x178
++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA                                   0x36c
++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA                                   0x18d0
++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA                                   0x1b2c
++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA                                   0x1d2c
++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA                                   0x1f2c
++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                                   0x412c
++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                                   0x432c
++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                                   0x452c
++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                                   0x472c
++#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA                                  0x59a8
++#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA                                  0x5f70
++#define mmREFCLK_CNTL                                                           0x109
++#define mmDCCG_CBUS_WRCMD_DELAY                                                 0x110
++#define mmDPREFCLK_CNTL                                                         0x118
++#define mmDCE_VERSION                                                           0x11e
++#define mmAVSYNC_COUNTER_WRITE                                                  0x12a
++#define mmAVSYNC_COUNTER_CONTROL                                                0x12b
++#define mmAVSYNC_COUNTER_READ                                                   0x12f
++#define mmDCCG_GTC_CNTL                                                         0x120
++#define mmDCCG_GTC_DTO_INCR                                                     0x121
++#define mmDCCG_GTC_DTO_MODULO                                                   0x122
++#define mmDCCG_GTC_CURRENT                                                      0x123
++#define mmDCCG_DS_DTO_INCR                                                      0x113
++#define mmDCCG_DS_DTO_MODULO                                                    0x114
++#define mmDCCG_DS_CNTL                                                          0x115
++#define mmDCCG_DS_HW_CAL_INTERVAL                                               0x116
++#define mmDCCG_DS_DEBUG_CNTL                                                    0x112
++#define mmDMCU_SMU_INTERRUPT_CNTL                                               0x12c
++#define mmSMU_CONTROL                                                           0x12d
++#define mmSMU_INTERRUPT_CONTROL                                                 0x12e
++#define mmDAC_CLK_ENABLE                                                        0x128
++#define mmDVO_CLK_ENABLE                                                        0x129
++#define mmDCCG_GATE_DISABLE_CNTL                                                0x134
++#define mmDCCG_GATE_DISABLE_CNTL2                                               0x13c
++#define mmDISPCLK_CGTT_BLK_CTRL_REG                                             0x135
++#define mmSCLK_CGTT_BLK_CTRL_REG                                                0x136
++#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                            0x108
++#define mmREFCLK_CGTT_BLK_CTRL_REG                                              0x10b
++#define mmSYMCLK_CGTT_BLK_CTRL_REG                                              0x13d
++#define mmDCCG_CAC_STATUS                                                       0x137
++#define mmPIXCLK1_RESYNC_CNTL                                                   0x138
++#define mmPIXCLK2_RESYNC_CNTL                                                   0x139
++#define mmPIXCLK0_RESYNC_CNTL                                                   0x13a
++#define mmPHYPLL_PIXCLK_CNTL                                                    0x13e
++#define mmMICROSECOND_TIME_BASE_DIV                                             0x13b
++#define mmDCCG_DISP_CNTL_REG                                                    0x13f
++#define mmMILLISECOND_TIME_BASE_DIV                                             0x130
++#define mmDISPCLK_FREQ_CHANGE_CNTL                                              0x131
++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                            0x132
++#define mmDCCG_PERFMON_CNTL                                                     0x133
++#define mmDCCG_PERFMON_CNTL2                                                    0x10e
++#define mmCRTC0_PIXEL_RATE_CNTL                                                 0x140
++#define mmDP_DTO0_PHASE                                                         0x141
++#define mmDP_DTO0_MODULO                                                        0x142
++#define mmCRTC1_PIXEL_RATE_CNTL                                                 0x144
++#define mmDP_DTO1_PHASE                                                         0x145
++#define mmDP_DTO1_MODULO                                                        0x146
++#define mmCRTC2_PIXEL_RATE_CNTL                                                 0x148
++#define mmDP_DTO2_PHASE                                                         0x149
++#define mmDP_DTO2_MODULO                                                        0x14a
++#define mmCRTC3_PIXEL_RATE_CNTL                                                 0x14c
++#define mmDP_DTO3_PHASE                                                         0x14d
++#define mmDP_DTO3_MODULO                                                        0x14e
++#define mmCRTC4_PIXEL_RATE_CNTL                                                 0x150
++#define mmDP_DTO4_PHASE                                                         0x151
++#define mmDP_DTO4_MODULO                                                        0x152
++#define mmCRTC5_PIXEL_RATE_CNTL                                                 0x154
++#define mmDP_DTO5_PHASE                                                         0x155
++#define mmDP_DTO5_MODULO                                                        0x156
++#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL                                           0x104
++#define mmDCCG_SOFT_RESET                                                       0x15f
++#define mmSYMCLKA_CLOCK_ENABLE                                                  0x160
++#define mmSYMCLKB_CLOCK_ENABLE                                                  0x161
++#define mmSYMCLKC_CLOCK_ENABLE                                                  0x162
++#define mmSYMCLKD_CLOCK_ENABLE                                                  0x163
++#define mmSYMCLKE_CLOCK_ENABLE                                                  0x164
++#define mmSYMCLKF_CLOCK_ENABLE                                                  0x165
++#define mmSYMCLKG_CLOCK_ENABLE                                                  0x117
++#define mmDPDBG_CLK_FORCE_CONTROL                                               0x10d
++#define mmDCCG_AUDIO_DTO_SOURCE                                                 0x16b
++#define mmDCCG_AUDIO_DTO0_PHASE                                                 0x16c
++#define mmDCCG_AUDIO_DTO0_MODULE                                                0x16d
++#define mmDCCG_AUDIO_DTO1_PHASE                                                 0x16e
++#define mmDCCG_AUDIO_DTO1_MODULE                                                0x16f
++#define mmDCCG_TEST_DEBUG_INDEX                                                 0x17c
++#define mmDCCG_TEST_DEBUG_DATA                                                  0x17d
++#define mmDCCG_TEST_CLK_SEL                                                     0x17e
++#define mmCPLL_MACRO_CNTL_RESERVED0                                             0x5fd0
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0                                  0x5fd0
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                                  0x5fdc
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                                  0x5fe8
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                                  0x5ff4
++#define mmCPLL_MACRO_CNTL_RESERVED1                                             0x5fd1
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1                                  0x5fd1
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                                  0x5fdd
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                                  0x5fe9
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                                  0x5ff5
++#define mmCPLL_MACRO_CNTL_RESERVED2                                             0x5fd2
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2                                  0x5fd2
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                                  0x5fde
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                                  0x5fea
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                                  0x5ff6
++#define mmCPLL_MACRO_CNTL_RESERVED3                                             0x5fd3
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3                                  0x5fd3
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                                  0x5fdf
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                                  0x5feb
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                                  0x5ff7
++#define mmCPLL_MACRO_CNTL_RESERVED4                                             0x5fd4
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4                                  0x5fd4
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                                  0x5fe0
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                                  0x5fec
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                                  0x5ff8
++#define mmCPLL_MACRO_CNTL_RESERVED5                                             0x5fd5
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5                                  0x5fd5
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                                  0x5fe1
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                                  0x5fed
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                                  0x5ff9
++#define mmCPLL_MACRO_CNTL_RESERVED6                                             0x5fd6
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6                                  0x5fd6
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                                  0x5fe2
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                                  0x5fee
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                                  0x5ffa
++#define mmCPLL_MACRO_CNTL_RESERVED7                                             0x5fd7
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7                                  0x5fd7
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                                  0x5fe3
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                                  0x5fef
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                                  0x5ffb
++#define mmCPLL_MACRO_CNTL_RESERVED8                                             0x5fd8
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8                                  0x5fd8
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                                  0x5fe4
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                                  0x5ff0
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                                  0x5ffc
++#define mmCPLL_MACRO_CNTL_RESERVED9                                             0x5fd9
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9                                  0x5fd9
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                                  0x5fe5
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                                  0x5ff1
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                                  0x5ffd
++#define mmCPLL_MACRO_CNTL_RESERVED10                                            0x5fda
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10                                 0x5fda
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                                 0x5fe6
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                                 0x5ff2
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                                 0x5ffe
++#define mmCPLL_MACRO_CNTL_RESERVED11                                            0x5fdb
++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11                                 0x5fdb
++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                                 0x5fe7
++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                                 0x5ff3
++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                                 0x5fff
++#define mmPLL_MACRO_CNTL_RESERVED0                                              0x1700
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0                                    0x1700
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0                                    0x172a
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0                                    0x1754
++#define mmPLL_MACRO_CNTL_RESERVED1                                              0x1701
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1                                    0x1701
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1                                    0x172b
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1                                    0x1755
++#define mmPLL_MACRO_CNTL_RESERVED2                                              0x1702
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2                                    0x1702
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2                                    0x172c
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2                                    0x1756
++#define mmPLL_MACRO_CNTL_RESERVED3                                              0x1703
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3                                    0x1703
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3                                    0x172d
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3                                    0x1757
++#define mmPLL_MACRO_CNTL_RESERVED4                                              0x1704
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4                                    0x1704
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4                                    0x172e
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4                                    0x1758
++#define mmPLL_MACRO_CNTL_RESERVED5                                              0x1705
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5                                    0x1705
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5                                    0x172f
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5                                    0x1759
++#define mmPLL_MACRO_CNTL_RESERVED6                                              0x1706
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6                                    0x1706
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6                                    0x1730
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6                                    0x175a
++#define mmPLL_MACRO_CNTL_RESERVED7                                              0x1707
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7                                    0x1707
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7                                    0x1731
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7                                    0x175b
++#define mmPLL_MACRO_CNTL_RESERVED8                                              0x1708
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8                                    0x1708
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8                                    0x1732
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8                                    0x175c
++#define mmPLL_MACRO_CNTL_RESERVED9                                              0x1709
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9                                    0x1709
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9                                    0x1733
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9                                    0x175d
++#define mmPLL_MACRO_CNTL_RESERVED10                                             0x170a
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10                                   0x170a
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10                                   0x1734
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10                                   0x175e
++#define mmPLL_MACRO_CNTL_RESERVED11                                             0x170b
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11                                   0x170b
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11                                   0x1735
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11                                   0x175f
++#define mmPLL_MACRO_CNTL_RESERVED12                                             0x170c
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12                                   0x170c
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12                                   0x1736
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12                                   0x1760
++#define mmPLL_MACRO_CNTL_RESERVED13                                             0x170d
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13                                   0x170d
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13                                   0x1737
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13                                   0x1761
++#define mmPLL_MACRO_CNTL_RESERVED14                                             0x170e
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14                                   0x170e
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14                                   0x1738
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14                                   0x1762
++#define mmPLL_MACRO_CNTL_RESERVED15                                             0x170f
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15                                   0x170f
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15                                   0x1739
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15                                   0x1763
++#define mmPLL_MACRO_CNTL_RESERVED16                                             0x1710
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16                                   0x1710
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16                                   0x173a
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16                                   0x1764
++#define mmPLL_MACRO_CNTL_RESERVED17                                             0x1711
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17                                   0x1711
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17                                   0x173b
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17                                   0x1765
++#define mmPLL_MACRO_CNTL_RESERVED18                                             0x1712
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18                                   0x1712
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18                                   0x173c
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18                                   0x1766
++#define mmPLL_MACRO_CNTL_RESERVED19                                             0x1713
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19                                   0x1713
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19                                   0x173d
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19                                   0x1767
++#define mmPLL_MACRO_CNTL_RESERVED20                                             0x1714
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20                                   0x1714
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20                                   0x173e
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20                                   0x1768
++#define mmPLL_MACRO_CNTL_RESERVED21                                             0x1715
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21                                   0x1715
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21                                   0x173f
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21                                   0x1769
++#define mmPLL_MACRO_CNTL_RESERVED22                                             0x1716
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22                                   0x1716
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22                                   0x1740
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22                                   0x176a
++#define mmPLL_MACRO_CNTL_RESERVED23                                             0x1717
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23                                   0x1717
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23                                   0x1741
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23                                   0x176b
++#define mmPLL_MACRO_CNTL_RESERVED24                                             0x1718
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24                                   0x1718
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24                                   0x1742
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24                                   0x176c
++#define mmPLL_MACRO_CNTL_RESERVED25                                             0x1719
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25                                   0x1719
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25                                   0x1743
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25                                   0x176d
++#define mmPLL_MACRO_CNTL_RESERVED26                                             0x171a
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26                                   0x171a
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26                                   0x1744
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26                                   0x176e
++#define mmPLL_MACRO_CNTL_RESERVED27                                             0x171b
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27                                   0x171b
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27                                   0x1745
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27                                   0x176f
++#define mmPLL_MACRO_CNTL_RESERVED28                                             0x171c
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28                                   0x171c
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28                                   0x1746
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28                                   0x1770
++#define mmPLL_MACRO_CNTL_RESERVED29                                             0x171d
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29                                   0x171d
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29                                   0x1747
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29                                   0x1771
++#define mmPLL_MACRO_CNTL_RESERVED30                                             0x171e
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30                                   0x171e
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30                                   0x1748
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30                                   0x1772
++#define mmPLL_MACRO_CNTL_RESERVED31                                             0x171f
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31                                   0x171f
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31                                   0x1749
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31                                   0x1773
++#define mmPLL_MACRO_CNTL_RESERVED32                                             0x1720
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32                                   0x1720
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32                                   0x174a
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32                                   0x1774
++#define mmPLL_MACRO_CNTL_RESERVED33                                             0x1721
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33                                   0x1721
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33                                   0x174b
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33                                   0x1775
++#define mmPLL_MACRO_CNTL_RESERVED34                                             0x1722
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34                                   0x1722
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34                                   0x174c
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34                                   0x1776
++#define mmPLL_MACRO_CNTL_RESERVED35                                             0x1723
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35                                   0x1723
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35                                   0x174d
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35                                   0x1777
++#define mmPLL_MACRO_CNTL_RESERVED36                                             0x1724
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36                                   0x1724
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36                                   0x174e
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36                                   0x1778
++#define mmPLL_MACRO_CNTL_RESERVED37                                             0x1725
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37                                   0x1725
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37                                   0x174f
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37                                   0x1779
++#define mmPLL_MACRO_CNTL_RESERVED38                                             0x1726
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38                                   0x1726
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38                                   0x1750
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38                                   0x177a
++#define mmPLL_MACRO_CNTL_RESERVED39                                             0x1727
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39                                   0x1727
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39                                   0x1751
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39                                   0x177b
++#define mmPLL_MACRO_CNTL_RESERVED40                                             0x1728
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40                                   0x1728
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40                                   0x1752
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40                                   0x177c
++#define mmPLL_MACRO_CNTL_RESERVED41                                             0x1729
++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41                                   0x1729
++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41                                   0x1753
++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41                                   0x177d
++#define mmDENTIST_DISPCLK_CNTL                                                  0x124
++#define mmDCDEBUG_BUS_CLK1_SEL                                                  0x16c4
++#define mmDCDEBUG_BUS_CLK2_SEL                                                  0x16c5
++#define mmDCDEBUG_BUS_CLK3_SEL                                                  0x16c6
++#define mmDCDEBUG_BUS_CLK4_SEL                                                  0x16c7
++#define mmDCDEBUG_BUS_CLK5_SEL                                                  0x16c8
++#define mmDCDEBUG_OUT_PIN_OVERRIDE                                              0x16c9
++#define mmDCDEBUG_OUT_CNTL                                                      0x16ca
++#define mmDCDEBUG_OUT_DATA                                                      0x16cb
++#define mmDMIF_ADDR_CONFIG                                                      0x2f5
++#define mmDMIF_CONTROL                                                          0x2f6
++#define mmDMIF_STATUS                                                           0x2f7
++#define mmDMIF_HW_DEBUG                                                         0x2f8
++#define mmDMIF_ARBITRATION_CONTROL                                              0x2f9
++#define mmPIPE0_ARBITRATION_CONTROL3                                            0x2fa
++#define mmPIPE1_ARBITRATION_CONTROL3                                            0x2fb
++#define mmPIPE2_ARBITRATION_CONTROL3                                            0x2fc
++#define mmPIPE3_ARBITRATION_CONTROL3                                            0x2fd
++#define mmPIPE4_ARBITRATION_CONTROL3                                            0x2fe
++#define mmPIPE5_ARBITRATION_CONTROL3                                            0x2ff
++#define mmPIPE6_ARBITRATION_CONTROL3                                            0x32a
++#define mmPIPE7_ARBITRATION_CONTROL3                                            0x32b
++#define mmDMIF_P_VMID                                                           0x300
++#define mmDMIF_URG_OVERRIDE                                                     0x329
++#define mmDMIF_TEST_DEBUG_INDEX                                                 0x301
++#define mmDMIF_TEST_DEBUG_DATA                                                  0x302
++#define ixDMIF_DEBUG02_CORE0                                                    0x2
++#define ixDMIF_DEBUG02_CORE1                                                    0xa
++#define mmDMIF_ADDR_CALC                                                        0x303
++#define mmDMIF_STATUS2                                                          0x304
++#define mmPIPE0_MAX_REQUESTS                                                    0x305
++#define mmPIPE1_MAX_REQUESTS                                                    0x306
++#define mmPIPE2_MAX_REQUESTS                                                    0x307
++#define mmPIPE3_MAX_REQUESTS                                                    0x308
++#define mmPIPE4_MAX_REQUESTS                                                    0x309
++#define mmPIPE5_MAX_REQUESTS                                                    0x30a
++#define mmPIPE6_MAX_REQUESTS                                                    0x32c
++#define mmPIPE7_MAX_REQUESTS                                                    0x32d
++#define mmDVMM_REG_RD_STATUS                                                    0x32e
++#define mmDVMM_REG_RD_DATA                                                      0x32f
++#define mmDVMM_PTE_REQ                                                          0x330
++#define mmDVMM_CNTL                                                             0x331
++#define mmDVMM_FAULT_STATUS                                                     0x332
++#define mmDVMM_FAULT_ADDR                                                       0x333
++#define mmLOW_POWER_TILING_CONTROL                                              0x30b
++#define mmMCIF_CONTROL                                                          0x30c
++#define mmMCIF_WRITE_COMBINE_CONTROL                                            0x30d
++#define mmMCIF_TEST_DEBUG_INDEX                                                 0x30e
++#define mmMCIF_TEST_DEBUG_DATA                                                  0x30f
++#define ixIDDCCIF02_DBG_DCCIF_C                                                 0x9
++#define ixIDDCCIF04_DBG_DCCIF_E                                                 0xb
++#define ixIDDCCIF05_DBG_DCCIF_F                                                 0xc
++#define mmMCIF_VMID                                                             0x310
++#define mmMCIF_MEM_CONTROL                                                      0x311
++#define mmCC_DC_PIPE_DIS                                                        0x312
++#define mmMC_DC_INTERFACE_NACK_STATUS                                           0x313
++#define mmRBBMIF_TIMEOUT                                                        0x314
++#define mmRBBMIF_STATUS                                                         0x315
++#define mmRBBMIF_TIMEOUT_DIS                                                    0x316
++#define mmRBBMIF_STATUS_FLAG                                                    0x327
++#define mmDCI_MEM_PWR_STATUS                                                    0x317
++#define mmDCI_MEM_PWR_STATUS2                                                   0x318
++#define mmDCI_CLK_CNTL                                                          0x319
++#define mmDCI_CLK_RAMP_CNTL                                                     0x31a
++#define mmDCI_MEM_PWR_CNTL                                                      0x31b
++#define mmDCI_MEM_PWR_CNTL2                                                     0x31c
++#define mmDCI_MEM_PWR_CNTL3                                                     0x31d
++#define mmDVMM_PTE_PGMEM_CONTROL                                                0x335
++#define mmDVMM_PTE_PGMEM_STATE                                                  0x336
++#define mmDCI_SOFT_RESET                                                        0x328
++#define mmDCI_MISC                                                              0x334
++#define mmDCI_TEST_DEBUG_INDEX                                                  0x31e
++#define mmDCI_TEST_DEBUG_DATA                                                   0x31f
++#define mmDCI_DEBUG_CONFIG                                                      0x320
++#define mmPIPE0_DMIF_BUFFER_CONTROL                                             0x321
++#define mmPIPE1_DMIF_BUFFER_CONTROL                                             0x322
++#define mmPIPE2_DMIF_BUFFER_CONTROL                                             0x323
++#define mmPIPE3_DMIF_BUFFER_CONTROL                                             0x324
++#define mmPIPE4_DMIF_BUFFER_CONTROL                                             0x325
++#define mmPIPE5_DMIF_BUFFER_CONTROL                                             0x326
++#define mmDC_GENERICA                                                           0x4800
++#define mmDC_GENERICB                                                           0x4801
++#define mmDC_PAD_EXTERN_SIG                                                     0x4802
++#define mmDC_REF_CLK_CNTL                                                       0x4803
++#define mmDC_GPIO_DEBUG                                                         0x4804
++#define mmUNIPHYA_LINK_CNTL                                                     0x4805
++#define mmUNIPHYB_LINK_CNTL                                                     0x4807
++#define mmUNIPHYC_LINK_CNTL                                                     0x4809
++#define mmUNIPHYD_LINK_CNTL                                                     0x480b
++#define mmUNIPHYE_LINK_CNTL                                                     0x480d
++#define mmUNIPHYF_LINK_CNTL                                                     0x480f
++#define mmUNIPHYG_LINK_CNTL                                                     0x4811
++#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                             0x4806
++#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                             0x4808
++#define mmUNIPHYC_CHANNEL_XBAR_CNTL                                             0x480a
++#define mmUNIPHYD_CHANNEL_XBAR_CNTL                                             0x480c
++#define mmUNIPHYE_CHANNEL_XBAR_CNTL                                             0x480e
++#define mmUNIPHYF_CHANNEL_XBAR_CNTL                                             0x4810
++#define mmUNIPHYG_CHANNEL_XBAR_CNTL                                             0x4812
++#define mmUNIPHYLPA_LINK_CNTL                                                   0x4847
++#define mmUNIPHYLPB_LINK_CNTL                                                   0x4848
++#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL                                           0x4849
++#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL                                           0x484a
++#define mmUNIPHY_IMPCAL_LINKA                                                   0x4838
++#define mmUNIPHY_IMPCAL_LINKB                                                   0x4839
++#define mmUNIPHY_IMPCAL_LINKC                                                   0x483f
++#define mmUNIPHY_IMPCAL_LINKD                                                   0x4840
++#define mmUNIPHY_IMPCAL_LINKE                                                   0x4843
++#define mmUNIPHY_IMPCAL_LINKF                                                   0x4844
++#define mmUNIPHY_IMPCAL_PERIOD                                                  0x483a
++#define mmAUXP_IMPCAL                                                           0x483b
++#define mmAUXN_IMPCAL                                                           0x483c
++#define mmDCIO_IMPCAL_CNTL                                                      0x483d
++#define mmUNIPHY_IMPCAL_PSW_AB                                                  0x483e
++#define mmDCIO_IMPCAL_CNTL_CD                                                   0x4841
++#define mmUNIPHY_IMPCAL_PSW_CD                                                  0x4842
++#define mmDCIO_IMPCAL_CNTL_EF                                                   0x4845
++#define mmUNIPHY_IMPCAL_PSW_EF                                                  0x4846
++#define mmDCIO_WRCMD_DELAY                                                      0x4816
++#define mmDC_PINSTRAPS                                                          0x4818
++#define mmDC_DVODATA_CONFIG                                                     0x481a
++#define mmLVTMA_PWRSEQ_CNTL                                                     0x481b
++#define mmLVTMA_PWRSEQ_STATE                                                    0x481c
++#define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
++#define mmLVTMA_PWRSEQ_DELAY1                                                   0x481e
++#define mmLVTMA_PWRSEQ_DELAY2                                                   0x481f
++#define mmBL_PWM_CNTL                                                           0x4820
++#define mmBL_PWM_CNTL2                                                          0x4821
++#define mmBL_PWM_PERIOD_CNTL                                                    0x4822
++#define mmBL_PWM_GRP1_REG_LOCK                                                  0x4823
++#define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                            0x4825
++#define mmDCIO_GSL0_CNTL                                                        0x4826
++#define mmDCIO_GSL1_CNTL                                                        0x4827
++#define mmDCIO_GSL2_CNTL                                                        0x4828
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                  0x4829
++#define mmDC_GPU_TIMER_START_POSITION_P_FLIP                                    0x482a
++#define mmDC_GPU_TIMER_READ                                                     0x482b
++#define mmDC_GPU_TIMER_READ_CNTL                                                0x482c
++#define mmDCIO_CLOCK_CNTL                                                       0x482d
++#define mmDCIO_DEBUG                                                            0x482f
++#define mmDCO_DCFE_EXT_VSYNC_CNTL                                               0x4830
++#define mmDBG_OUT_CNTL                                                          0x4834
++#define mmDCIO_DEBUG_CONFIG                                                     0x4835
++#define mmDCIO_SOFT_RESET                                                       0x4836
++#define mmDCIO_DPHY_SEL                                                         0x4837
++#define mmDCIO_TEST_DEBUG_INDEX                                                 0x4831
++#define mmDCIO_TEST_DEBUG_DATA                                                  0x4832
++#define ixDCIO_DEBUG1                                                           0x1
++#define ixDCIO_DEBUG2                                                           0x2
++#define ixDCIO_DEBUG3                                                           0x3
++#define ixDCIO_DEBUG4                                                           0x4
++#define ixDCIO_DEBUG5                                                           0x5
++#define ixDCIO_DEBUG6                                                           0x6
++#define ixDCIO_DEBUG7                                                           0x7
++#define ixDCIO_DEBUG8                                                           0x8
++#define ixDCIO_DEBUG9                                                           0x9
++#define ixDCIO_DEBUGA                                                           0xa
++#define ixDCIO_DEBUGB                                                           0xb
++#define ixDCIO_DEBUGC                                                           0xc
++#define ixDCIO_DEBUGD                                                           0xd
++#define ixDCIO_DEBUGE                                                           0xe
++#define ixDCIO_DEBUGF                                                           0xf
++#define ixDCIO_DEBUG10                                                          0x10
++#define ixDCIO_DEBUG11                                                          0x11
++#define ixDCIO_DEBUG12                                                          0x12
++#define ixDCIO_DEBUG13                                                          0x13
++#define ixDCIO_DEBUG14                                                          0x14
++#define ixDCIO_DEBUG15                                                          0x15
++#define ixDCIO_DEBUG16                                                          0x16
++#define ixDCIO_DEBUG17                                                          0x17
++#define ixDCIO_DEBUG18                                                          0x18
++#define ixDCIO_DEBUG19                                                          0x19
++#define ixDCIO_DEBUG1A                                                          0x1a
++#define ixDCIO_DEBUG1B                                                          0x1b
++#define ixDCIO_DEBUG_ID                                                         0x0
++#define mmDC_GPIO_GENERIC_MASK                                                  0x4860
++#define mmDC_GPIO_GENERIC_A                                                     0x4861
++#define mmDC_GPIO_GENERIC_EN                                                    0x4862
++#define mmDC_GPIO_GENERIC_Y                                                     0x4863
++#define mmDC_GPIO_DVODATA_MASK                                                  0x4864
++#define mmDC_GPIO_DVODATA_A                                                     0x4865
++#define mmDC_GPIO_DVODATA_EN                                                    0x4866
++#define mmDC_GPIO_DVODATA_Y                                                     0x4867
++#define mmDC_GPIO_DDC1_MASK                                                     0x4868
++#define mmDC_GPIO_DDC1_A                                                        0x4869
++#define mmDC_GPIO_DDC1_EN                                                       0x486a
++#define mmDC_GPIO_DDC1_Y                                                        0x486b
++#define mmDC_GPIO_DDC2_MASK                                                     0x486c
++#define mmDC_GPIO_DDC2_A                                                        0x486d
++#define mmDC_GPIO_DDC2_EN                                                       0x486e
++#define mmDC_GPIO_DDC2_Y                                                        0x486f
++#define mmDC_GPIO_DDC3_MASK                                                     0x4870
++#define mmDC_GPIO_DDC3_A                                                        0x4871
++#define mmDC_GPIO_DDC3_EN                                                       0x4872
++#define mmDC_GPIO_DDC3_Y                                                        0x4873
++#define mmDC_GPIO_DDC4_MASK                                                     0x4874
++#define mmDC_GPIO_DDC4_A                                                        0x4875
++#define mmDC_GPIO_DDC4_EN                                                       0x4876
++#define mmDC_GPIO_DDC4_Y                                                        0x4877
++#define mmDC_GPIO_DDC5_MASK                                                     0x4878
++#define mmDC_GPIO_DDC5_A                                                        0x4879
++#define mmDC_GPIO_DDC5_EN                                                       0x487a
++#define mmDC_GPIO_DDC5_Y                                                        0x487b
++#define mmDC_GPIO_DDC6_MASK                                                     0x487c
++#define mmDC_GPIO_DDC6_A                                                        0x487d
++#define mmDC_GPIO_DDC6_EN                                                       0x487e
++#define mmDC_GPIO_DDC6_Y                                                        0x487f
++#define mmDC_GPIO_DDCVGA_MASK                                                   0x4880
++#define mmDC_GPIO_DDCVGA_A                                                      0x4881
++#define mmDC_GPIO_DDCVGA_EN                                                     0x4882
++#define mmDC_GPIO_DDCVGA_Y                                                      0x4883
++#define mmDC_GPIO_SYNCA_MASK                                                    0x4884
++#define mmDC_GPIO_SYNCA_A                                                       0x4885
++#define mmDC_GPIO_SYNCA_EN                                                      0x4886
++#define mmDC_GPIO_SYNCA_Y                                                       0x4887
++#define mmDC_GPIO_GENLK_MASK                                                    0x4888
++#define mmDC_GPIO_GENLK_A                                                       0x4889
++#define mmDC_GPIO_GENLK_EN                                                      0x488a
++#define mmDC_GPIO_GENLK_Y                                                       0x488b
++#define mmDC_GPIO_HPD_MASK                                                      0x488c
++#define mmDC_GPIO_HPD_A                                                         0x488d
++#define mmDC_GPIO_HPD_EN                                                        0x488e
++#define mmDC_GPIO_HPD_Y                                                         0x488f
++#define mmDC_GPIO_PWRSEQ_MASK                                                   0x4890
++#define mmDC_GPIO_PWRSEQ_A                                                      0x4891
++#define mmDC_GPIO_PWRSEQ_EN                                                     0x4892
++#define mmDC_GPIO_PWRSEQ_Y                                                      0x4893
++#define mmDC_GPIO_PAD_STRENGTH_1                                                0x4894
++#define mmDC_GPIO_PAD_STRENGTH_2                                                0x4895
++#define mmPHY_AUX_CNTL                                                          0x4897
++#define mmDC_GPIO_I2CPAD_MASK                                                   0x4898
++#define mmDC_GPIO_I2CPAD_A                                                      0x4899
++#define mmDC_GPIO_I2CPAD_EN                                                     0x489a
++#define mmDC_GPIO_I2CPAD_Y                                                      0x489b
++#define mmDC_GPIO_I2CPAD_STRENGTH                                               0x489c
++#define mmDVO_VREF_CONTROL                                                      0x489e
++#define mmDVO_SKEW_ADJUST                                                       0x489f
++#define mmDAC_MACRO_CNTL_RESERVED0                                              0x48b8
++#define mmDAC_MACRO_CNTL_RESERVED1                                              0x48b9
++#define mmDAC_MACRO_CNTL_RESERVED2                                              0x48ba
++#define mmDAC_MACRO_CNTL_RESERVED3                                              0x48bb
++#define mmUNIPHY_MACRO_CNTL_RESERVED0                                           0x48c0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                              0x48c0
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                              0x48e0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                              0x4900
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                              0x4920
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                              0x4940
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0                              0x4960
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0                              0x4980
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0                              0x49c0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0                              0x49e0
++#define mmUNIPHY_MACRO_CNTL_RESERVED1                                           0x48c1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                              0x48c1
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                              0x48e1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                              0x4901
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                              0x4921
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                              0x4941
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1                              0x4961
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1                              0x4981
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1                              0x49c1
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1                              0x49e1
++#define mmUNIPHY_MACRO_CNTL_RESERVED2                                           0x48c2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                              0x48c2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                              0x48e2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                              0x4902
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                              0x4922
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                              0x4942
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2                              0x4962
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2                              0x4982
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2                              0x49c2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2                              0x49e2
++#define mmUNIPHY_MACRO_CNTL_RESERVED3                                           0x48c3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                              0x48c3
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                              0x48e3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                              0x4903
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                              0x4923
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                              0x4943
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3                              0x4963
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3                              0x4983
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3                              0x49c3
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3                              0x49e3
++#define mmUNIPHY_MACRO_CNTL_RESERVED4                                           0x48c4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                              0x48c4
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                              0x48e4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                              0x4904
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                              0x4924
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                              0x4944
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4                              0x4964
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4                              0x4984
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4                              0x49c4
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4                              0x49e4
++#define mmUNIPHY_MACRO_CNTL_RESERVED5                                           0x48c5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                              0x48c5
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                              0x48e5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                              0x4905
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                              0x4925
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                              0x4945
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5                              0x4965
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5                              0x4985
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5                              0x49c5
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5                              0x49e5
++#define mmUNIPHY_MACRO_CNTL_RESERVED6                                           0x48c6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                              0x48c6
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                              0x48e6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                              0x4906
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                              0x4926
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                              0x4946
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6                              0x4966
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6                              0x4986
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6                              0x49c6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6                              0x49e6
++#define mmUNIPHY_MACRO_CNTL_RESERVED7                                           0x48c7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                              0x48c7
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                              0x48e7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                              0x4907
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                              0x4927
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                              0x4947
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7                              0x4967
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7                              0x4987
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7                              0x49c7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7                              0x49e7
++#define mmUNIPHY_MACRO_CNTL_RESERVED8                                           0x48c8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                              0x48c8
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                              0x48e8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                              0x4908
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                              0x4928
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                              0x4948
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8                              0x4968
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8                              0x4988
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8                              0x49c8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8                              0x49e8
++#define mmUNIPHY_MACRO_CNTL_RESERVED9                                           0x48c9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                              0x48c9
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                              0x48e9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                              0x4909
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                              0x4929
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                              0x4949
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9                              0x4969
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9                              0x4989
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9                              0x49c9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9                              0x49e9
++#define mmUNIPHY_MACRO_CNTL_RESERVED10                                          0x48ca
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                             0x48ca
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                             0x48ea
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                             0x490a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                             0x492a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                             0x494a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10                             0x496a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10                             0x498a
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10                             0x49ca
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10                             0x49ea
++#define mmUNIPHY_MACRO_CNTL_RESERVED11                                          0x48cb
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                             0x48cb
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                             0x48eb
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                             0x490b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                             0x492b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                             0x494b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11                             0x496b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11                             0x498b
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11                             0x49cb
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11                             0x49eb
++#define mmUNIPHY_MACRO_CNTL_RESERVED12                                          0x48cc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                             0x48cc
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                             0x48ec
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                             0x490c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                             0x492c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                             0x494c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12                             0x496c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12                             0x498c
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12                             0x49cc
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12                             0x49ec
++#define mmUNIPHY_MACRO_CNTL_RESERVED13                                          0x48cd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                             0x48cd
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                             0x48ed
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                             0x490d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                             0x492d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                             0x494d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13                             0x496d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13                             0x498d
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13                             0x49cd
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13                             0x49ed
++#define mmUNIPHY_MACRO_CNTL_RESERVED14                                          0x48ce
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                             0x48ce
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                             0x48ee
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                             0x490e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                             0x492e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                             0x494e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14                             0x496e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14                             0x498e
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14                             0x49ce
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14                             0x49ee
++#define mmUNIPHY_MACRO_CNTL_RESERVED15                                          0x48cf
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                             0x48cf
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                             0x48ef
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                             0x490f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                             0x492f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                             0x494f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15                             0x496f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15                             0x498f
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15                             0x49cf
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15                             0x49ef
++#define mmUNIPHY_MACRO_CNTL_RESERVED16                                          0x48d0
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                             0x48d0
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                             0x48f0
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                             0x4910
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                             0x4930
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                             0x4950
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16                             0x4970
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16                             0x4990
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16                             0x49d0
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16                             0x49f0
++#define mmUNIPHY_MACRO_CNTL_RESERVED17                                          0x48d1
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                             0x48d1
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                             0x48f1
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                             0x4911
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                             0x4931
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                             0x4951
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17                             0x4971
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17                             0x4991
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17                             0x49d1
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17                             0x49f1
++#define mmUNIPHY_MACRO_CNTL_RESERVED18                                          0x48d2
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                             0x48d2
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                             0x48f2
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                             0x4912
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                             0x4932
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                             0x4952
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18                             0x4972
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18                             0x4992
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18                             0x49d2
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18                             0x49f2
++#define mmUNIPHY_MACRO_CNTL_RESERVED19                                          0x48d3
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                             0x48d3
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                             0x48f3
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                             0x4913
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                             0x4933
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                             0x4953
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19                             0x4973
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19                             0x4993
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19                             0x49d3
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19                             0x49f3
++#define mmUNIPHY_MACRO_CNTL_RESERVED20                                          0x48d4
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                             0x48d4
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                             0x48f4
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                             0x4914
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                             0x4934
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                             0x4954
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20                             0x4974
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20                             0x4994
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20                             0x49d4
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20                             0x49f4
++#define mmUNIPHY_MACRO_CNTL_RESERVED21                                          0x48d5
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                             0x48d5
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                             0x48f5
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                             0x4915
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                             0x4935
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                             0x4955
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21                             0x4975
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21                             0x4995
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21                             0x49d5
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21                             0x49f5
++#define mmUNIPHY_MACRO_CNTL_RESERVED22                                          0x48d6
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                             0x48d6
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                             0x48f6
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                             0x4916
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                             0x4936
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                             0x4956
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22                             0x4976
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22                             0x4996
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22                             0x49d6
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22                             0x49f6
++#define mmUNIPHY_MACRO_CNTL_RESERVED23                                          0x48d7
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                             0x48d7
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                             0x48f7
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                             0x4917
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                             0x4937
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                             0x4957
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23                             0x4977
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23                             0x4997
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23                             0x49d7
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23                             0x49f7
++#define mmUNIPHY_MACRO_CNTL_RESERVED24                                          0x48d8
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                             0x48d8
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                             0x48f8
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                             0x4918
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                             0x4938
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                             0x4958
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24                             0x4978
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24                             0x4998
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24                             0x49d8
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24                             0x49f8
++#define mmUNIPHY_MACRO_CNTL_RESERVED25                                          0x48d9
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                             0x48d9
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                             0x48f9
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                             0x4919
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                             0x4939
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                             0x4959
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25                             0x4979
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25                             0x4999
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25                             0x49d9
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25                             0x49f9
++#define mmUNIPHY_MACRO_CNTL_RESERVED26                                          0x48da
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                             0x48da
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                             0x48fa
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                             0x491a
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                             0x493a
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                             0x495a
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26                             0x497a
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26                             0x499a
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26                             0x49da
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26                             0x49fa
++#define mmUNIPHY_MACRO_CNTL_RESERVED27                                          0x48db
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                             0x48db
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                             0x48fb
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                             0x491b
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                             0x493b
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                             0x495b
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27                             0x497b
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27                             0x499b
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27                             0x49db
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27                             0x49fb
++#define mmUNIPHY_MACRO_CNTL_RESERVED28                                          0x48dc
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                             0x48dc
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                             0x48fc
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                             0x491c
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                             0x493c
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                             0x495c
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28                             0x497c
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28                             0x499c
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28                             0x49dc
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28                             0x49fc
++#define mmUNIPHY_MACRO_CNTL_RESERVED29                                          0x48dd
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                             0x48dd
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                             0x48fd
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                             0x491d
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                             0x493d
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                             0x495d
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29                             0x497d
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29                             0x499d
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29                             0x49dd
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29                             0x49fd
++#define mmUNIPHY_MACRO_CNTL_RESERVED30                                          0x48de
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                             0x48de
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                             0x48fe
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                             0x491e
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                             0x493e
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                             0x495e
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30                             0x497e
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30                             0x499e
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30                             0x49de
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30                             0x49fe
++#define mmUNIPHY_MACRO_CNTL_RESERVED31                                          0x48df
++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                             0x48df
++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                             0x48ff
++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                             0x491f
++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                             0x493f
++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                             0x495f
++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31                             0x497f
++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31                             0x499f
++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31                             0x49df
++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31                             0x49ff
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED0                                         0x5a84
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED1                                         0x5a85
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED2                                         0x5a86
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED3                                         0x5a87
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED4                                         0x5a88
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED5                                         0x5a89
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED6                                         0x5a8a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED7                                         0x5a8b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED8                                         0x5a8c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED9                                         0x5a8d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED10                                        0x5a8e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED11                                        0x5a8f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED12                                        0x5a90
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED13                                        0x5a91
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED14                                        0x5a92
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED15                                        0x5a93
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED16                                        0x5a94
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED17                                        0x5a95
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED18                                        0x5a96
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED19                                        0x5a97
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED20                                        0x5a98
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED21                                        0x5a99
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED22                                        0x5a9a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED23                                        0x5a9b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED24                                        0x5a9c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED25                                        0x5a9d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED26                                        0x5a9e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED27                                        0x5a9f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED28                                        0x5aa0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED29                                        0x5aa1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED30                                        0x5aa2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED31                                        0x5aa3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED32                                        0x5aa4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED33                                        0x5aa5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED34                                        0x5aa6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED35                                        0x5aa7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED36                                        0x5aa8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED37                                        0x5aa9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED38                                        0x5aaa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED39                                        0x5aab
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED40                                        0x5aac
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED41                                        0x5aad
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED42                                        0x5aae
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED43                                        0x5aaf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED44                                        0x5ab0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED45                                        0x5ab1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED46                                        0x5ab2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED47                                        0x5ab3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED48                                        0x5ab4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED49                                        0x5ab5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED50                                        0x5ab6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED51                                        0x5ab7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED52                                        0x5ab8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED53                                        0x5ab9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED54                                        0x5aba
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED55                                        0x5abb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED56                                        0x5abc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED57                                        0x5abd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED58                                        0x5abe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED59                                        0x5abf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED60                                        0x5ac0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED61                                        0x5ac1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED62                                        0x5ac2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED63                                        0x5ac3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED64                                        0x5ac4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED65                                        0x5ac5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED66                                        0x5ac6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED67                                        0x5ac7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED68                                        0x5ac8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED69                                        0x5ac9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED70                                        0x5aca
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED71                                        0x5acb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED72                                        0x5acc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED73                                        0x5acd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED74                                        0x5ace
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED75                                        0x5acf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED76                                        0x5ad0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED77                                        0x5ad1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED78                                        0x5ad2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED79                                        0x5ad3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED80                                        0x5ad4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED81                                        0x5ad5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED82                                        0x5ad6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED83                                        0x5ad7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED84                                        0x5ad8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED85                                        0x5ad9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED86                                        0x5ada
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED87                                        0x5adb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED88                                        0x5adc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED89                                        0x5add
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED90                                        0x5ade
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED91                                        0x5adf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED92                                        0x5ae0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED93                                        0x5ae1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED94                                        0x5ae2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED95                                        0x5ae3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED96                                        0x5ae4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED97                                        0x5ae5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED98                                        0x5ae6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED99                                        0x5ae7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED100                                       0x5ae8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED101                                       0x5ae9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED102                                       0x5aea
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED103                                       0x5aeb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED104                                       0x5aec
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED105                                       0x5aed
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED106                                       0x5aee
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED107                                       0x5aef
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED108                                       0x5af0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED109                                       0x5af1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED110                                       0x5af2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED111                                       0x5af3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED112                                       0x5af4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED113                                       0x5af5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED114                                       0x5af6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED115                                       0x5af7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED116                                       0x5af8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED117                                       0x5af9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED118                                       0x5afa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED119                                       0x5afb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED120                                       0x5afc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED121                                       0x5afd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED122                                       0x5afe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED123                                       0x5aff
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED124                                       0x5b00
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED125                                       0x5b01
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED126                                       0x5b02
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED127                                       0x5b03
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED128                                       0x5b04
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED129                                       0x5b05
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED130                                       0x5b06
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED131                                       0x5b07
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED132                                       0x5b08
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED133                                       0x5b09
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED134                                       0x5b0a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED135                                       0x5b0b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED136                                       0x5b0c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED137                                       0x5b0d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED138                                       0x5b0e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED139                                       0x5b0f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED140                                       0x5b10
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED141                                       0x5b11
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED142                                       0x5b12
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED143                                       0x5b13
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED144                                       0x5b14
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED145                                       0x5b15
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED146                                       0x5b16
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED147                                       0x5b17
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED148                                       0x5b18
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED149                                       0x5b19
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED150                                       0x5b1a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED151                                       0x5b1b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED152                                       0x5b1c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED153                                       0x5b1d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED154                                       0x5b1e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED155                                       0x5b1f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED156                                       0x5b20
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED157                                       0x5b21
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED158                                       0x5b22
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED159                                       0x5b23
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED160                                       0x5b24
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED161                                       0x5b25
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED162                                       0x5b26
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED163                                       0x5b27
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED164                                       0x5b28
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED165                                       0x5b29
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED166                                       0x5b2a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED167                                       0x5b2b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED168                                       0x5b2c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED169                                       0x5b2d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED170                                       0x5b2e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED171                                       0x5b2f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED172                                       0x5b30
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED173                                       0x5b31
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED174                                       0x5b32
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED175                                       0x5b33
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED176                                       0x5b34
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED177                                       0x5b35
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED178                                       0x5b36
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED179                                       0x5b37
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED180                                       0x5b38
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED181                                       0x5b39
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED182                                       0x5b3a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED183                                       0x5b3b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED184                                       0x5b3c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED185                                       0x5b3d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED186                                       0x5b3e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED187                                       0x5b3f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED188                                       0x5b40
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED189                                       0x5b41
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED190                                       0x5b42
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED191                                       0x5b43
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED192                                       0x5b44
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED193                                       0x5b45
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED194                                       0x5b46
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED195                                       0x5b47
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED196                                       0x5b48
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED197                                       0x5b49
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED198                                       0x5b4a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED199                                       0x5b4b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED200                                       0x5b4c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED201                                       0x5b4d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED202                                       0x5b4e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED203                                       0x5b4f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED204                                       0x5b50
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED205                                       0x5b51
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED206                                       0x5b52
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED207                                       0x5b53
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED208                                       0x5b54
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED209                                       0x5b55
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED210                                       0x5b56
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED211                                       0x5b57
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED212                                       0x5b58
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED213                                       0x5b59
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED214                                       0x5b5a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED215                                       0x5b5b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED216                                       0x5b5c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED217                                       0x5b5d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED218                                       0x5b5e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED219                                       0x5b5f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED220                                       0x5b60
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED221                                       0x5b61
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED222                                       0x5b62
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED223                                       0x5b63
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED224                                       0x5b64
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED225                                       0x5b65
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED226                                       0x5b66
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED227                                       0x5b67
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED228                                       0x5b68
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED229                                       0x5b69
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED230                                       0x5b6a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED231                                       0x5b6b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED232                                       0x5b6c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED233                                       0x5b6d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED234                                       0x5b6e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED235                                       0x5b6f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED236                                       0x5b70
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED237                                       0x5b71
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED238                                       0x5b72
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED239                                       0x5b73
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED240                                       0x5b74
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED241                                       0x5b75
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED242                                       0x5b76
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED243                                       0x5b77
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED244                                       0x5b78
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED245                                       0x5b79
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED246                                       0x5b7a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED247                                       0x5b7b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED248                                       0x5b7c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED249                                       0x5b7d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED250                                       0x5b7e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED251                                       0x5b7f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED252                                       0x5b80
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED253                                       0x5b81
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED254                                       0x5b82
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED255                                       0x5b83
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED256                                       0x5b84
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED257                                       0x5b85
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED258                                       0x5b86
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED259                                       0x5b87
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED260                                       0x5b88
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED261                                       0x5b89
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED262                                       0x5b8a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED263                                       0x5b8b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED264                                       0x5b8c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED265                                       0x5b8d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED266                                       0x5b8e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED267                                       0x5b8f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED268                                       0x5b90
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED269                                       0x5b91
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED270                                       0x5b92
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED271                                       0x5b93
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED272                                       0x5b94
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED273                                       0x5b95
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED274                                       0x5b96
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED275                                       0x5b97
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED276                                       0x5b98
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED277                                       0x5b99
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED278                                       0x5b9a
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED279                                       0x5b9b
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED280                                       0x5b9c
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED281                                       0x5b9d
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED282                                       0x5b9e
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED283                                       0x5b9f
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED284                                       0x5ba0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED285                                       0x5ba1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED286                                       0x5ba2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED287                                       0x5ba3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED288                                       0x5ba4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED289                                       0x5ba5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED290                                       0x5ba6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED291                                       0x5ba7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED292                                       0x5ba8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED293                                       0x5ba9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED294                                       0x5baa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED295                                       0x5bab
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED296                                       0x5bac
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED297                                       0x5bad
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED298                                       0x5bae
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED299                                       0x5baf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED300                                       0x5bb0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED301                                       0x5bb1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED302                                       0x5bb2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED303                                       0x5bb3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED304                                       0x5bb4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED305                                       0x5bb5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED306                                       0x5bb6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED307                                       0x5bb7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED308                                       0x5bb8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED309                                       0x5bb9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED310                                       0x5bba
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED311                                       0x5bbb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED312                                       0x5bbc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED313                                       0x5bbd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED314                                       0x5bbe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED315                                       0x5bbf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED316                                       0x5bc0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED317                                       0x5bc1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED318                                       0x5bc2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED319                                       0x5bc3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED320                                       0x5bc4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED321                                       0x5bc5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED322                                       0x5bc6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED323                                       0x5bc7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED324                                       0x5bc8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED325                                       0x5bc9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED326                                       0x5bca
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED327                                       0x5bcb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED328                                       0x5bcc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED329                                       0x5bcd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED330                                       0x5bce
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED331                                       0x5bcf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED332                                       0x5bd0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED333                                       0x5bd1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED334                                       0x5bd2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED335                                       0x5bd3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED336                                       0x5bd4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED337                                       0x5bd5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED338                                       0x5bd6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED339                                       0x5bd7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED340                                       0x5bd8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED341                                       0x5bd9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED342                                       0x5bda
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED343                                       0x5bdb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED344                                       0x5bdc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED345                                       0x5bdd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED346                                       0x5bde
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED347                                       0x5bdf
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED348                                       0x5be0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED349                                       0x5be1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED350                                       0x5be2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED351                                       0x5be3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED352                                       0x5be4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED353                                       0x5be5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED354                                       0x5be6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED355                                       0x5be7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED356                                       0x5be8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED357                                       0x5be9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED358                                       0x5bea
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED359                                       0x5beb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED360                                       0x5bec
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED361                                       0x5bed
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED362                                       0x5bee
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED363                                       0x5bef
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED364                                       0x5bf0
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED365                                       0x5bf1
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED366                                       0x5bf2
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED367                                       0x5bf3
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED368                                       0x5bf4
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED369                                       0x5bf5
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED370                                       0x5bf6
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED371                                       0x5bf7
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED372                                       0x5bf8
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED373                                       0x5bf9
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED374                                       0x5bfa
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED375                                       0x5bfb
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED376                                       0x5bfc
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED377                                       0x5bfd
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED378                                       0x5bfe
++#define mmDCRX_PHY_MACRO_CNTL_RESERVED379                                       0x5bff
++#define mmDPHY_MACRO_CNTL_RESERVED0                                             0x5d98
++#define mmDPHY_MACRO_CNTL_RESERVED1                                             0x5d99
++#define mmDPHY_MACRO_CNTL_RESERVED2                                             0x5d9a
++#define mmDPHY_MACRO_CNTL_RESERVED3                                             0x5d9b
++#define mmDPHY_MACRO_CNTL_RESERVED4                                             0x5d9c
++#define mmDPHY_MACRO_CNTL_RESERVED5                                             0x5d9d
++#define mmDPHY_MACRO_CNTL_RESERVED6                                             0x5d9e
++#define mmDPHY_MACRO_CNTL_RESERVED7                                             0x5d9f
++#define mmDPHY_MACRO_CNTL_RESERVED8                                             0x5da0
++#define mmDPHY_MACRO_CNTL_RESERVED9                                             0x5da1
++#define mmDPHY_MACRO_CNTL_RESERVED10                                            0x5da2
++#define mmDPHY_MACRO_CNTL_RESERVED11                                            0x5da3
++#define mmDPHY_MACRO_CNTL_RESERVED12                                            0x5da4
++#define mmDPHY_MACRO_CNTL_RESERVED13                                            0x5da5
++#define mmDPHY_MACRO_CNTL_RESERVED14                                            0x5da6
++#define mmDPHY_MACRO_CNTL_RESERVED15                                            0x5da7
++#define mmDPHY_MACRO_CNTL_RESERVED16                                            0x5da8
++#define mmDPHY_MACRO_CNTL_RESERVED17                                            0x5da9
++#define mmDPHY_MACRO_CNTL_RESERVED18                                            0x5daa
++#define mmDPHY_MACRO_CNTL_RESERVED19                                            0x5dab
++#define mmDPHY_MACRO_CNTL_RESERVED20                                            0x5dac
++#define mmDPHY_MACRO_CNTL_RESERVED21                                            0x5dad
++#define mmDPHY_MACRO_CNTL_RESERVED22                                            0x5dae
++#define mmDPHY_MACRO_CNTL_RESERVED23                                            0x5daf
++#define mmDPHY_MACRO_CNTL_RESERVED24                                            0x5db0
++#define mmDPHY_MACRO_CNTL_RESERVED25                                            0x5db1
++#define mmDPHY_MACRO_CNTL_RESERVED26                                            0x5db2
++#define mmDPHY_MACRO_CNTL_RESERVED27                                            0x5db3
++#define mmDPHY_MACRO_CNTL_RESERVED28                                            0x5db4
++#define mmDPHY_MACRO_CNTL_RESERVED29                                            0x5db5
++#define mmDPHY_MACRO_CNTL_RESERVED30                                            0x5db6
++#define mmDPHY_MACRO_CNTL_RESERVED31                                            0x5db7
++#define mmDPHY_MACRO_CNTL_RESERVED32                                            0x5db8
++#define mmDPHY_MACRO_CNTL_RESERVED33                                            0x5db9
++#define mmDPHY_MACRO_CNTL_RESERVED34                                            0x5dba
++#define mmDPHY_MACRO_CNTL_RESERVED35                                            0x5dbb
++#define mmDPHY_MACRO_CNTL_RESERVED36                                            0x5dbc
++#define mmDPHY_MACRO_CNTL_RESERVED37                                            0x5dbd
++#define mmDPHY_MACRO_CNTL_RESERVED38                                            0x5dbe
++#define mmDPHY_MACRO_CNTL_RESERVED39                                            0x5dbf
++#define mmDPHY_MACRO_CNTL_RESERVED40                                            0x5dc0
++#define mmDPHY_MACRO_CNTL_RESERVED41                                            0x5dc1
++#define mmDPHY_MACRO_CNTL_RESERVED42                                            0x5dc2
++#define mmDPHY_MACRO_CNTL_RESERVED43                                            0x5dc3
++#define mmDPHY_MACRO_CNTL_RESERVED44                                            0x5dc4
++#define mmDPHY_MACRO_CNTL_RESERVED45                                            0x5dc5
++#define mmDPHY_MACRO_CNTL_RESERVED46                                            0x5dc6
++#define mmDPHY_MACRO_CNTL_RESERVED47                                            0x5dc7
++#define mmDPHY_MACRO_CNTL_RESERVED48                                            0x5dc8
++#define mmDPHY_MACRO_CNTL_RESERVED49                                            0x5dc9
++#define mmDPHY_MACRO_CNTL_RESERVED50                                            0x5dca
++#define mmDPHY_MACRO_CNTL_RESERVED51                                            0x5dcb
++#define mmDPHY_MACRO_CNTL_RESERVED52                                            0x5dcc
++#define mmDPHY_MACRO_CNTL_RESERVED53                                            0x5dcd
++#define mmDPHY_MACRO_CNTL_RESERVED54                                            0x5dce
++#define mmDPHY_MACRO_CNTL_RESERVED55                                            0x5dcf
++#define mmDPHY_MACRO_CNTL_RESERVED56                                            0x5dd0
++#define mmDPHY_MACRO_CNTL_RESERVED57                                            0x5dd1
++#define mmDPHY_MACRO_CNTL_RESERVED58                                            0x5dd2
++#define mmDPHY_MACRO_CNTL_RESERVED59                                            0x5dd3
++#define mmDPHY_MACRO_CNTL_RESERVED60                                            0x5dd4
++#define mmDPHY_MACRO_CNTL_RESERVED61                                            0x5dd5
++#define mmDPHY_MACRO_CNTL_RESERVED62                                            0x5dd6
++#define mmDPHY_MACRO_CNTL_RESERVED63                                            0x5dd7
++#define mmGRPH_ENABLE                                                           0x1a00
++#define mmDCP0_GRPH_ENABLE                                                      0x1a00
++#define mmDCP1_GRPH_ENABLE                                                      0x1c00
++#define mmDCP2_GRPH_ENABLE                                                      0x1e00
++#define mmDCP3_GRPH_ENABLE                                                      0x4000
++#define mmDCP4_GRPH_ENABLE                                                      0x4200
++#define mmDCP5_GRPH_ENABLE                                                      0x4400
++#define mmGRPH_CONTROL                                                          0x1a01
++#define mmDCP0_GRPH_CONTROL                                                     0x1a01
++#define mmDCP1_GRPH_CONTROL                                                     0x1c01
++#define mmDCP2_GRPH_CONTROL                                                     0x1e01
++#define mmDCP3_GRPH_CONTROL                                                     0x4001
++#define mmDCP4_GRPH_CONTROL                                                     0x4201
++#define mmDCP5_GRPH_CONTROL                                                     0x4401
++#define mmGRPH_LUT_10BIT_BYPASS                                                 0x1a02
++#define mmDCP0_GRPH_LUT_10BIT_BYPASS                                            0x1a02
++#define mmDCP1_GRPH_LUT_10BIT_BYPASS                                            0x1c02
++#define mmDCP2_GRPH_LUT_10BIT_BYPASS                                            0x1e02
++#define mmDCP3_GRPH_LUT_10BIT_BYPASS                                            0x4002
++#define mmDCP4_GRPH_LUT_10BIT_BYPASS                                            0x4202
++#define mmDCP5_GRPH_LUT_10BIT_BYPASS                                            0x4402
++#define mmGRPH_SWAP_CNTL                                                        0x1a03
++#define mmDCP0_GRPH_SWAP_CNTL                                                   0x1a03
++#define mmDCP1_GRPH_SWAP_CNTL                                                   0x1c03
++#define mmDCP2_GRPH_SWAP_CNTL                                                   0x1e03
++#define mmDCP3_GRPH_SWAP_CNTL                                                   0x4003
++#define mmDCP4_GRPH_SWAP_CNTL                                                   0x4203
++#define mmDCP5_GRPH_SWAP_CNTL                                                   0x4403
++#define mmGRPH_PRIMARY_SURFACE_ADDRESS                                          0x1a04
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1a04
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1c04
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1e04
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4004
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4204
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4404
++#define mmGRPH_SECONDARY_SURFACE_ADDRESS                                        0x1a05
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1a05
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1c05
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1e05
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4005
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4205
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4405
++#define mmGRPH_PITCH                                                            0x1a06
++#define mmDCP0_GRPH_PITCH                                                       0x1a06
++#define mmDCP1_GRPH_PITCH                                                       0x1c06
++#define mmDCP2_GRPH_PITCH                                                       0x1e06
++#define mmDCP3_GRPH_PITCH                                                       0x4006
++#define mmDCP4_GRPH_PITCH                                                       0x4206
++#define mmDCP5_GRPH_PITCH                                                       0x4406
++#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                     0x1a07
++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1a07
++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1c07
++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1e07
++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4007
++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4207
++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4407
++#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                   0x1a08
++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1a08
++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1c08
++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1e08
++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4008
++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4208
++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4408
++#define mmGRPH_SURFACE_OFFSET_X                                                 0x1a09
++#define mmDCP0_GRPH_SURFACE_OFFSET_X                                            0x1a09
++#define mmDCP1_GRPH_SURFACE_OFFSET_X                                            0x1c09
++#define mmDCP2_GRPH_SURFACE_OFFSET_X                                            0x1e09
++#define mmDCP3_GRPH_SURFACE_OFFSET_X                                            0x4009
++#define mmDCP4_GRPH_SURFACE_OFFSET_X                                            0x4209
++#define mmDCP5_GRPH_SURFACE_OFFSET_X                                            0x4409
++#define mmGRPH_SURFACE_OFFSET_Y                                                 0x1a0a
++#define mmDCP0_GRPH_SURFACE_OFFSET_Y                                            0x1a0a
++#define mmDCP1_GRPH_SURFACE_OFFSET_Y                                            0x1c0a
++#define mmDCP2_GRPH_SURFACE_OFFSET_Y                                            0x1e0a
++#define mmDCP3_GRPH_SURFACE_OFFSET_Y                                            0x400a
++#define mmDCP4_GRPH_SURFACE_OFFSET_Y                                            0x420a
++#define mmDCP5_GRPH_SURFACE_OFFSET_Y                                            0x440a
++#define mmGRPH_X_START                                                          0x1a0b
++#define mmDCP0_GRPH_X_START                                                     0x1a0b
++#define mmDCP1_GRPH_X_START                                                     0x1c0b
++#define mmDCP2_GRPH_X_START                                                     0x1e0b
++#define mmDCP3_GRPH_X_START                                                     0x400b
++#define mmDCP4_GRPH_X_START                                                     0x420b
++#define mmDCP5_GRPH_X_START                                                     0x440b
++#define mmGRPH_Y_START                                                          0x1a0c
++#define mmDCP0_GRPH_Y_START                                                     0x1a0c
++#define mmDCP1_GRPH_Y_START                                                     0x1c0c
++#define mmDCP2_GRPH_Y_START                                                     0x1e0c
++#define mmDCP3_GRPH_Y_START                                                     0x400c
++#define mmDCP4_GRPH_Y_START                                                     0x420c
++#define mmDCP5_GRPH_Y_START                                                     0x440c
++#define mmGRPH_X_END                                                            0x1a0d
++#define mmDCP0_GRPH_X_END                                                       0x1a0d
++#define mmDCP1_GRPH_X_END                                                       0x1c0d
++#define mmDCP2_GRPH_X_END                                                       0x1e0d
++#define mmDCP3_GRPH_X_END                                                       0x400d
++#define mmDCP4_GRPH_X_END                                                       0x420d
++#define mmDCP5_GRPH_X_END                                                       0x440d
++#define mmGRPH_Y_END                                                            0x1a0e
++#define mmDCP0_GRPH_Y_END                                                       0x1a0e
++#define mmDCP1_GRPH_Y_END                                                       0x1c0e
++#define mmDCP2_GRPH_Y_END                                                       0x1e0e
++#define mmDCP3_GRPH_Y_END                                                       0x400e
++#define mmDCP4_GRPH_Y_END                                                       0x420e
++#define mmDCP5_GRPH_Y_END                                                       0x440e
++#define mmINPUT_GAMMA_CONTROL                                                   0x1a10
++#define mmDCP0_INPUT_GAMMA_CONTROL                                              0x1a10
++#define mmDCP1_INPUT_GAMMA_CONTROL                                              0x1c10
++#define mmDCP2_INPUT_GAMMA_CONTROL                                              0x1e10
++#define mmDCP3_INPUT_GAMMA_CONTROL                                              0x4010
++#define mmDCP4_INPUT_GAMMA_CONTROL                                              0x4210
++#define mmDCP5_INPUT_GAMMA_CONTROL                                              0x4410
++#define mmGRPH_UPDATE                                                           0x1a11
++#define mmDCP0_GRPH_UPDATE                                                      0x1a11
++#define mmDCP1_GRPH_UPDATE                                                      0x1c11
++#define mmDCP2_GRPH_UPDATE                                                      0x1e11
++#define mmDCP3_GRPH_UPDATE                                                      0x4011
++#define mmDCP4_GRPH_UPDATE                                                      0x4211
++#define mmDCP5_GRPH_UPDATE                                                      0x4411
++#define mmGRPH_FLIP_CONTROL                                                     0x1a12
++#define mmDCP0_GRPH_FLIP_CONTROL                                                0x1a12
++#define mmDCP1_GRPH_FLIP_CONTROL                                                0x1c12
++#define mmDCP2_GRPH_FLIP_CONTROL                                                0x1e12
++#define mmDCP3_GRPH_FLIP_CONTROL                                                0x4012
++#define mmDCP4_GRPH_FLIP_CONTROL                                                0x4212
++#define mmDCP5_GRPH_FLIP_CONTROL                                                0x4412
++#define mmGRPH_SURFACE_ADDRESS_INUSE                                            0x1a13
++#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                       0x1a13
++#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                       0x1c13
++#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                       0x1e13
++#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                       0x4013
++#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                       0x4213
++#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                       0x4413
++#define mmGRPH_DFQ_CONTROL                                                      0x1a14
++#define mmDCP0_GRPH_DFQ_CONTROL                                                 0x1a14
++#define mmDCP1_GRPH_DFQ_CONTROL                                                 0x1c14
++#define mmDCP2_GRPH_DFQ_CONTROL                                                 0x1e14
++#define mmDCP3_GRPH_DFQ_CONTROL                                                 0x4014
++#define mmDCP4_GRPH_DFQ_CONTROL                                                 0x4214
++#define mmDCP5_GRPH_DFQ_CONTROL                                                 0x4414
++#define mmGRPH_DFQ_STATUS                                                       0x1a15
++#define mmDCP0_GRPH_DFQ_STATUS                                                  0x1a15
++#define mmDCP1_GRPH_DFQ_STATUS                                                  0x1c15
++#define mmDCP2_GRPH_DFQ_STATUS                                                  0x1e15
++#define mmDCP3_GRPH_DFQ_STATUS                                                  0x4015
++#define mmDCP4_GRPH_DFQ_STATUS                                                  0x4215
++#define mmDCP5_GRPH_DFQ_STATUS                                                  0x4415
++#define mmGRPH_INTERRUPT_STATUS                                                 0x1a16
++#define mmDCP0_GRPH_INTERRUPT_STATUS                                            0x1a16
++#define mmDCP1_GRPH_INTERRUPT_STATUS                                            0x1c16
++#define mmDCP2_GRPH_INTERRUPT_STATUS                                            0x1e16
++#define mmDCP3_GRPH_INTERRUPT_STATUS                                            0x4016
++#define mmDCP4_GRPH_INTERRUPT_STATUS                                            0x4216
++#define mmDCP5_GRPH_INTERRUPT_STATUS                                            0x4416
++#define mmGRPH_INTERRUPT_CONTROL                                                0x1a17
++#define mmDCP0_GRPH_INTERRUPT_CONTROL                                           0x1a17
++#define mmDCP1_GRPH_INTERRUPT_CONTROL                                           0x1c17
++#define mmDCP2_GRPH_INTERRUPT_CONTROL                                           0x1e17
++#define mmDCP3_GRPH_INTERRUPT_CONTROL                                           0x4017
++#define mmDCP4_GRPH_INTERRUPT_CONTROL                                           0x4217
++#define mmDCP5_GRPH_INTERRUPT_CONTROL                                           0x4417
++#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE                                       0x1a18
++#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1a18
++#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1c18
++#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1e18
++#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4018
++#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4218
++#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4418
++#define mmGRPH_COMPRESS_SURFACE_ADDRESS                                         0x1a19
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1a19
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1c19
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1e19
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4019
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4219
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4419
++#define mmGRPH_COMPRESS_PITCH                                                   0x1a1a
++#define mmDCP0_GRPH_COMPRESS_PITCH                                              0x1a1a
++#define mmDCP1_GRPH_COMPRESS_PITCH                                              0x1c1a
++#define mmDCP2_GRPH_COMPRESS_PITCH                                              0x1e1a
++#define mmDCP3_GRPH_COMPRESS_PITCH                                              0x401a
++#define mmDCP4_GRPH_COMPRESS_PITCH                                              0x421a
++#define mmDCP5_GRPH_COMPRESS_PITCH                                              0x441a
++#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                    0x1a1b
++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1a1b
++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1c1b
++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1e1b
++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x401b
++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x421b
++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x441b
++#define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                   0x1a1c
++#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1a1c
++#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1c1c
++#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1e1c
++#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x401c
++#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x421c
++#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x441c
++#define mmPRESCALE_GRPH_CONTROL                                                 0x1a2d
++#define mmDCP0_PRESCALE_GRPH_CONTROL                                            0x1a2d
++#define mmDCP1_PRESCALE_GRPH_CONTROL                                            0x1c2d
++#define mmDCP2_PRESCALE_GRPH_CONTROL                                            0x1e2d
++#define mmDCP3_PRESCALE_GRPH_CONTROL                                            0x402d
++#define mmDCP4_PRESCALE_GRPH_CONTROL                                            0x422d
++#define mmDCP5_PRESCALE_GRPH_CONTROL                                            0x442d
++#define mmPRESCALE_VALUES_GRPH_R                                                0x1a2e
++#define mmDCP0_PRESCALE_VALUES_GRPH_R                                           0x1a2e
++#define mmDCP1_PRESCALE_VALUES_GRPH_R                                           0x1c2e
++#define mmDCP2_PRESCALE_VALUES_GRPH_R                                           0x1e2e
++#define mmDCP3_PRESCALE_VALUES_GRPH_R                                           0x402e
++#define mmDCP4_PRESCALE_VALUES_GRPH_R                                           0x422e
++#define mmDCP5_PRESCALE_VALUES_GRPH_R                                           0x442e
++#define mmPRESCALE_VALUES_GRPH_G                                                0x1a2f
++#define mmDCP0_PRESCALE_VALUES_GRPH_G                                           0x1a2f
++#define mmDCP1_PRESCALE_VALUES_GRPH_G                                           0x1c2f
++#define mmDCP2_PRESCALE_VALUES_GRPH_G                                           0x1e2f
++#define mmDCP3_PRESCALE_VALUES_GRPH_G                                           0x402f
++#define mmDCP4_PRESCALE_VALUES_GRPH_G                                           0x422f
++#define mmDCP5_PRESCALE_VALUES_GRPH_G                                           0x442f
++#define mmPRESCALE_VALUES_GRPH_B                                                0x1a30
++#define mmDCP0_PRESCALE_VALUES_GRPH_B                                           0x1a30
++#define mmDCP1_PRESCALE_VALUES_GRPH_B                                           0x1c30
++#define mmDCP2_PRESCALE_VALUES_GRPH_B                                           0x1e30
++#define mmDCP3_PRESCALE_VALUES_GRPH_B                                           0x4030
++#define mmDCP4_PRESCALE_VALUES_GRPH_B                                           0x4230
++#define mmDCP5_PRESCALE_VALUES_GRPH_B                                           0x4430
++#define mmINPUT_CSC_CONTROL                                                     0x1a35
++#define mmDCP0_INPUT_CSC_CONTROL                                                0x1a35
++#define mmDCP1_INPUT_CSC_CONTROL                                                0x1c35
++#define mmDCP2_INPUT_CSC_CONTROL                                                0x1e35
++#define mmDCP3_INPUT_CSC_CONTROL                                                0x4035
++#define mmDCP4_INPUT_CSC_CONTROL                                                0x4235
++#define mmDCP5_INPUT_CSC_CONTROL                                                0x4435
++#define mmINPUT_CSC_C11_C12                                                     0x1a36
++#define mmDCP0_INPUT_CSC_C11_C12                                                0x1a36
++#define mmDCP1_INPUT_CSC_C11_C12                                                0x1c36
++#define mmDCP2_INPUT_CSC_C11_C12                                                0x1e36
++#define mmDCP3_INPUT_CSC_C11_C12                                                0x4036
++#define mmDCP4_INPUT_CSC_C11_C12                                                0x4236
++#define mmDCP5_INPUT_CSC_C11_C12                                                0x4436
++#define mmINPUT_CSC_C13_C14                                                     0x1a37
++#define mmDCP0_INPUT_CSC_C13_C14                                                0x1a37
++#define mmDCP1_INPUT_CSC_C13_C14                                                0x1c37
++#define mmDCP2_INPUT_CSC_C13_C14                                                0x1e37
++#define mmDCP3_INPUT_CSC_C13_C14                                                0x4037
++#define mmDCP4_INPUT_CSC_C13_C14                                                0x4237
++#define mmDCP5_INPUT_CSC_C13_C14                                                0x4437
++#define mmINPUT_CSC_C21_C22                                                     0x1a38
++#define mmDCP0_INPUT_CSC_C21_C22                                                0x1a38
++#define mmDCP1_INPUT_CSC_C21_C22                                                0x1c38
++#define mmDCP2_INPUT_CSC_C21_C22                                                0x1e38
++#define mmDCP3_INPUT_CSC_C21_C22                                                0x4038
++#define mmDCP4_INPUT_CSC_C21_C22                                                0x4238
++#define mmDCP5_INPUT_CSC_C21_C22                                                0x4438
++#define mmINPUT_CSC_C23_C24                                                     0x1a39
++#define mmDCP0_INPUT_CSC_C23_C24                                                0x1a39
++#define mmDCP1_INPUT_CSC_C23_C24                                                0x1c39
++#define mmDCP2_INPUT_CSC_C23_C24                                                0x1e39
++#define mmDCP3_INPUT_CSC_C23_C24                                                0x4039
++#define mmDCP4_INPUT_CSC_C23_C24                                                0x4239
++#define mmDCP5_INPUT_CSC_C23_C24                                                0x4439
++#define mmINPUT_CSC_C31_C32                                                     0x1a3a
++#define mmDCP0_INPUT_CSC_C31_C32                                                0x1a3a
++#define mmDCP1_INPUT_CSC_C31_C32                                                0x1c3a
++#define mmDCP2_INPUT_CSC_C31_C32                                                0x1e3a
++#define mmDCP3_INPUT_CSC_C31_C32                                                0x403a
++#define mmDCP4_INPUT_CSC_C31_C32                                                0x423a
++#define mmDCP5_INPUT_CSC_C31_C32                                                0x443a
++#define mmINPUT_CSC_C33_C34                                                     0x1a3b
++#define mmDCP0_INPUT_CSC_C33_C34                                                0x1a3b
++#define mmDCP1_INPUT_CSC_C33_C34                                                0x1c3b
++#define mmDCP2_INPUT_CSC_C33_C34                                                0x1e3b
++#define mmDCP3_INPUT_CSC_C33_C34                                                0x403b
++#define mmDCP4_INPUT_CSC_C33_C34                                                0x423b
++#define mmDCP5_INPUT_CSC_C33_C34                                                0x443b
++#define mmOUTPUT_CSC_CONTROL                                                    0x1a3c
++#define mmDCP0_OUTPUT_CSC_CONTROL                                               0x1a3c
++#define mmDCP1_OUTPUT_CSC_CONTROL                                               0x1c3c
++#define mmDCP2_OUTPUT_CSC_CONTROL                                               0x1e3c
++#define mmDCP3_OUTPUT_CSC_CONTROL                                               0x403c
++#define mmDCP4_OUTPUT_CSC_CONTROL                                               0x423c
++#define mmDCP5_OUTPUT_CSC_CONTROL                                               0x443c
++#define mmOUTPUT_CSC_C11_C12                                                    0x1a3d
++#define mmDCP0_OUTPUT_CSC_C11_C12                                               0x1a3d
++#define mmDCP1_OUTPUT_CSC_C11_C12                                               0x1c3d
++#define mmDCP2_OUTPUT_CSC_C11_C12                                               0x1e3d
++#define mmDCP3_OUTPUT_CSC_C11_C12                                               0x403d
++#define mmDCP4_OUTPUT_CSC_C11_C12                                               0x423d
++#define mmDCP5_OUTPUT_CSC_C11_C12                                               0x443d
++#define mmOUTPUT_CSC_C13_C14                                                    0x1a3e
++#define mmDCP0_OUTPUT_CSC_C13_C14                                               0x1a3e
++#define mmDCP1_OUTPUT_CSC_C13_C14                                               0x1c3e
++#define mmDCP2_OUTPUT_CSC_C13_C14                                               0x1e3e
++#define mmDCP3_OUTPUT_CSC_C13_C14                                               0x403e
++#define mmDCP4_OUTPUT_CSC_C13_C14                                               0x423e
++#define mmDCP5_OUTPUT_CSC_C13_C14                                               0x443e
++#define mmOUTPUT_CSC_C21_C22                                                    0x1a3f
++#define mmDCP0_OUTPUT_CSC_C21_C22                                               0x1a3f
++#define mmDCP1_OUTPUT_CSC_C21_C22                                               0x1c3f
++#define mmDCP2_OUTPUT_CSC_C21_C22                                               0x1e3f
++#define mmDCP3_OUTPUT_CSC_C21_C22                                               0x403f
++#define mmDCP4_OUTPUT_CSC_C21_C22                                               0x423f
++#define mmDCP5_OUTPUT_CSC_C21_C22                                               0x443f
++#define mmOUTPUT_CSC_C23_C24                                                    0x1a40
++#define mmDCP0_OUTPUT_CSC_C23_C24                                               0x1a40
++#define mmDCP1_OUTPUT_CSC_C23_C24                                               0x1c40
++#define mmDCP2_OUTPUT_CSC_C23_C24                                               0x1e40
++#define mmDCP3_OUTPUT_CSC_C23_C24                                               0x4040
++#define mmDCP4_OUTPUT_CSC_C23_C24                                               0x4240
++#define mmDCP5_OUTPUT_CSC_C23_C24                                               0x4440
++#define mmOUTPUT_CSC_C31_C32                                                    0x1a41
++#define mmDCP0_OUTPUT_CSC_C31_C32                                               0x1a41
++#define mmDCP1_OUTPUT_CSC_C31_C32                                               0x1c41
++#define mmDCP2_OUTPUT_CSC_C31_C32                                               0x1e41
++#define mmDCP3_OUTPUT_CSC_C31_C32                                               0x4041
++#define mmDCP4_OUTPUT_CSC_C31_C32                                               0x4241
++#define mmDCP5_OUTPUT_CSC_C31_C32                                               0x4441
++#define mmOUTPUT_CSC_C33_C34                                                    0x1a42
++#define mmDCP0_OUTPUT_CSC_C33_C34                                               0x1a42
++#define mmDCP1_OUTPUT_CSC_C33_C34                                               0x1c42
++#define mmDCP2_OUTPUT_CSC_C33_C34                                               0x1e42
++#define mmDCP3_OUTPUT_CSC_C33_C34                                               0x4042
++#define mmDCP4_OUTPUT_CSC_C33_C34                                               0x4242
++#define mmDCP5_OUTPUT_CSC_C33_C34                                               0x4442
++#define mmCOMM_MATRIXA_TRANS_C11_C12                                            0x1a43
++#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                       0x1a43
++#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                       0x1c43
++#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                       0x1e43
++#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                       0x4043
++#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                       0x4243
++#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                       0x4443
++#define mmCOMM_MATRIXA_TRANS_C13_C14                                            0x1a44
++#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                       0x1a44
++#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                       0x1c44
++#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                       0x1e44
++#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                       0x4044
++#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                       0x4244
++#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                       0x4444
++#define mmCOMM_MATRIXA_TRANS_C21_C22                                            0x1a45
++#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                       0x1a45
++#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                       0x1c45
++#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                       0x1e45
++#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                       0x4045
++#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                       0x4245
++#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                       0x4445
++#define mmCOMM_MATRIXA_TRANS_C23_C24                                            0x1a46
++#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                       0x1a46
++#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                       0x1c46
++#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                       0x1e46
++#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                       0x4046
++#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                       0x4246
++#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                       0x4446
++#define mmCOMM_MATRIXA_TRANS_C31_C32                                            0x1a47
++#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                       0x1a47
++#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                       0x1c47
++#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                       0x1e47
++#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                       0x4047
++#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                       0x4247
++#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                       0x4447
++#define mmCOMM_MATRIXA_TRANS_C33_C34                                            0x1a48
++#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                       0x1a48
++#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                       0x1c48
++#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                       0x1e48
++#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                       0x4048
++#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                       0x4248
++#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                       0x4448
++#define mmCOMM_MATRIXB_TRANS_C11_C12                                            0x1a49
++#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                       0x1a49
++#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                       0x1c49
++#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                       0x1e49
++#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                       0x4049
++#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                       0x4249
++#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                       0x4449
++#define mmCOMM_MATRIXB_TRANS_C13_C14                                            0x1a4a
++#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                       0x1a4a
++#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                       0x1c4a
++#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                       0x1e4a
++#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                       0x404a
++#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                       0x424a
++#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                       0x444a
++#define mmCOMM_MATRIXB_TRANS_C21_C22                                            0x1a4b
++#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                       0x1a4b
++#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                       0x1c4b
++#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                       0x1e4b
++#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                       0x404b
++#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                       0x424b
++#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                       0x444b
++#define mmCOMM_MATRIXB_TRANS_C23_C24                                            0x1a4c
++#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                       0x1a4c
++#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                       0x1c4c
++#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                       0x1e4c
++#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                       0x404c
++#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                       0x424c
++#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                       0x444c
++#define mmCOMM_MATRIXB_TRANS_C31_C32                                            0x1a4d
++#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                       0x1a4d
++#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                       0x1c4d
++#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                       0x1e4d
++#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                       0x404d
++#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                       0x424d
++#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                       0x444d
++#define mmCOMM_MATRIXB_TRANS_C33_C34                                            0x1a4e
++#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                       0x1a4e
++#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                       0x1c4e
++#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                       0x1e4e
++#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                       0x404e
++#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                       0x424e
++#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                       0x444e
++#define mmDENORM_CONTROL                                                        0x1a50
++#define mmDCP0_DENORM_CONTROL                                                   0x1a50
++#define mmDCP1_DENORM_CONTROL                                                   0x1c50
++#define mmDCP2_DENORM_CONTROL                                                   0x1e50
++#define mmDCP3_DENORM_CONTROL                                                   0x4050
++#define mmDCP4_DENORM_CONTROL                                                   0x4250
++#define mmDCP5_DENORM_CONTROL                                                   0x4450
++#define mmOUT_ROUND_CONTROL                                                     0x1a51
++#define mmDCP0_OUT_ROUND_CONTROL                                                0x1a51
++#define mmDCP1_OUT_ROUND_CONTROL                                                0x1c51
++#define mmDCP2_OUT_ROUND_CONTROL                                                0x1e51
++#define mmDCP3_OUT_ROUND_CONTROL                                                0x4051
++#define mmDCP4_OUT_ROUND_CONTROL                                                0x4251
++#define mmDCP5_OUT_ROUND_CONTROL                                                0x4451
++#define mmOUT_CLAMP_CONTROL_R_CR                                                0x1a52
++#define mmDCP0_OUT_CLAMP_CONTROL_R_CR                                           0x1a52
++#define mmDCP1_OUT_CLAMP_CONTROL_R_CR                                           0x1c52
++#define mmDCP2_OUT_CLAMP_CONTROL_R_CR                                           0x1e52
++#define mmDCP3_OUT_CLAMP_CONTROL_R_CR                                           0x4052
++#define mmDCP4_OUT_CLAMP_CONTROL_R_CR                                           0x4252
++#define mmDCP5_OUT_CLAMP_CONTROL_R_CR                                           0x4452
++#define mmOUT_CLAMP_CONTROL_G_Y                                                 0x1a9c
++#define mmDCP0_OUT_CLAMP_CONTROL_G_Y                                            0x1a9c
++#define mmDCP1_OUT_CLAMP_CONTROL_G_Y                                            0x1c9c
++#define mmDCP2_OUT_CLAMP_CONTROL_G_Y                                            0x1e9c
++#define mmDCP3_OUT_CLAMP_CONTROL_G_Y                                            0x409c
++#define mmDCP4_OUT_CLAMP_CONTROL_G_Y                                            0x429c
++#define mmDCP5_OUT_CLAMP_CONTROL_G_Y                                            0x449c
++#define mmOUT_CLAMP_CONTROL_B_CB                                                0x1a9d
++#define mmDCP0_OUT_CLAMP_CONTROL_B_CB                                           0x1a9d
++#define mmDCP1_OUT_CLAMP_CONTROL_B_CB                                           0x1c9d
++#define mmDCP2_OUT_CLAMP_CONTROL_B_CB                                           0x1e9d
++#define mmDCP3_OUT_CLAMP_CONTROL_B_CB                                           0x409d
++#define mmDCP4_OUT_CLAMP_CONTROL_B_CB                                           0x429d
++#define mmDCP5_OUT_CLAMP_CONTROL_B_CB                                           0x449d
++#define mmKEY_CONTROL                                                           0x1a53
++#define mmDCP0_KEY_CONTROL                                                      0x1a53
++#define mmDCP1_KEY_CONTROL                                                      0x1c53
++#define mmDCP2_KEY_CONTROL                                                      0x1e53
++#define mmDCP3_KEY_CONTROL                                                      0x4053
++#define mmDCP4_KEY_CONTROL                                                      0x4253
++#define mmDCP5_KEY_CONTROL                                                      0x4453
++#define mmKEY_RANGE_ALPHA                                                       0x1a54
++#define mmDCP0_KEY_RANGE_ALPHA                                                  0x1a54
++#define mmDCP1_KEY_RANGE_ALPHA                                                  0x1c54
++#define mmDCP2_KEY_RANGE_ALPHA                                                  0x1e54
++#define mmDCP3_KEY_RANGE_ALPHA                                                  0x4054
++#define mmDCP4_KEY_RANGE_ALPHA                                                  0x4254
++#define mmDCP5_KEY_RANGE_ALPHA                                                  0x4454
++#define mmKEY_RANGE_RED                                                         0x1a55
++#define mmDCP0_KEY_RANGE_RED                                                    0x1a55
++#define mmDCP1_KEY_RANGE_RED                                                    0x1c55
++#define mmDCP2_KEY_RANGE_RED                                                    0x1e55
++#define mmDCP3_KEY_RANGE_RED                                                    0x4055
++#define mmDCP4_KEY_RANGE_RED                                                    0x4255
++#define mmDCP5_KEY_RANGE_RED                                                    0x4455
++#define mmKEY_RANGE_GREEN                                                       0x1a56
++#define mmDCP0_KEY_RANGE_GREEN                                                  0x1a56
++#define mmDCP1_KEY_RANGE_GREEN                                                  0x1c56
++#define mmDCP2_KEY_RANGE_GREEN                                                  0x1e56
++#define mmDCP3_KEY_RANGE_GREEN                                                  0x4056
++#define mmDCP4_KEY_RANGE_GREEN                                                  0x4256
++#define mmDCP5_KEY_RANGE_GREEN                                                  0x4456
++#define mmKEY_RANGE_BLUE                                                        0x1a57
++#define mmDCP0_KEY_RANGE_BLUE                                                   0x1a57
++#define mmDCP1_KEY_RANGE_BLUE                                                   0x1c57
++#define mmDCP2_KEY_RANGE_BLUE                                                   0x1e57
++#define mmDCP3_KEY_RANGE_BLUE                                                   0x4057
++#define mmDCP4_KEY_RANGE_BLUE                                                   0x4257
++#define mmDCP5_KEY_RANGE_BLUE                                                   0x4457
++#define mmDEGAMMA_CONTROL                                                       0x1a58
++#define mmDCP0_DEGAMMA_CONTROL                                                  0x1a58
++#define mmDCP1_DEGAMMA_CONTROL                                                  0x1c58
++#define mmDCP2_DEGAMMA_CONTROL                                                  0x1e58
++#define mmDCP3_DEGAMMA_CONTROL                                                  0x4058
++#define mmDCP4_DEGAMMA_CONTROL                                                  0x4258
++#define mmDCP5_DEGAMMA_CONTROL                                                  0x4458
++#define mmGAMUT_REMAP_CONTROL                                                   0x1a59
++#define mmDCP0_GAMUT_REMAP_CONTROL                                              0x1a59
++#define mmDCP1_GAMUT_REMAP_CONTROL                                              0x1c59
++#define mmDCP2_GAMUT_REMAP_CONTROL                                              0x1e59
++#define mmDCP3_GAMUT_REMAP_CONTROL                                              0x4059
++#define mmDCP4_GAMUT_REMAP_CONTROL                                              0x4259
++#define mmDCP5_GAMUT_REMAP_CONTROL                                              0x4459
++#define mmGAMUT_REMAP_C11_C12                                                   0x1a5a
++#define mmDCP0_GAMUT_REMAP_C11_C12                                              0x1a5a
++#define mmDCP1_GAMUT_REMAP_C11_C12                                              0x1c5a
++#define mmDCP2_GAMUT_REMAP_C11_C12                                              0x1e5a
++#define mmDCP3_GAMUT_REMAP_C11_C12                                              0x405a
++#define mmDCP4_GAMUT_REMAP_C11_C12                                              0x425a
++#define mmDCP5_GAMUT_REMAP_C11_C12                                              0x445a
++#define mmGAMUT_REMAP_C13_C14                                                   0x1a5b
++#define mmDCP0_GAMUT_REMAP_C13_C14                                              0x1a5b
++#define mmDCP1_GAMUT_REMAP_C13_C14                                              0x1c5b
++#define mmDCP2_GAMUT_REMAP_C13_C14                                              0x1e5b
++#define mmDCP3_GAMUT_REMAP_C13_C14                                              0x405b
++#define mmDCP4_GAMUT_REMAP_C13_C14                                              0x425b
++#define mmDCP5_GAMUT_REMAP_C13_C14                                              0x445b
++#define mmGAMUT_REMAP_C21_C22                                                   0x1a5c
++#define mmDCP0_GAMUT_REMAP_C21_C22                                              0x1a5c
++#define mmDCP1_GAMUT_REMAP_C21_C22                                              0x1c5c
++#define mmDCP2_GAMUT_REMAP_C21_C22                                              0x1e5c
++#define mmDCP3_GAMUT_REMAP_C21_C22                                              0x405c
++#define mmDCP4_GAMUT_REMAP_C21_C22                                              0x425c
++#define mmDCP5_GAMUT_REMAP_C21_C22                                              0x445c
++#define mmGAMUT_REMAP_C23_C24                                                   0x1a5d
++#define mmDCP0_GAMUT_REMAP_C23_C24                                              0x1a5d
++#define mmDCP1_GAMUT_REMAP_C23_C24                                              0x1c5d
++#define mmDCP2_GAMUT_REMAP_C23_C24                                              0x1e5d
++#define mmDCP3_GAMUT_REMAP_C23_C24                                              0x405d
++#define mmDCP4_GAMUT_REMAP_C23_C24                                              0x425d
++#define mmDCP5_GAMUT_REMAP_C23_C24                                              0x445d
++#define mmGAMUT_REMAP_C31_C32                                                   0x1a5e
++#define mmDCP0_GAMUT_REMAP_C31_C32                                              0x1a5e
++#define mmDCP1_GAMUT_REMAP_C31_C32                                              0x1c5e
++#define mmDCP2_GAMUT_REMAP_C31_C32                                              0x1e5e
++#define mmDCP3_GAMUT_REMAP_C31_C32                                              0x405e
++#define mmDCP4_GAMUT_REMAP_C31_C32                                              0x425e
++#define mmDCP5_GAMUT_REMAP_C31_C32                                              0x445e
++#define mmGAMUT_REMAP_C33_C34                                                   0x1a5f
++#define mmDCP0_GAMUT_REMAP_C33_C34                                              0x1a5f
++#define mmDCP1_GAMUT_REMAP_C33_C34                                              0x1c5f
++#define mmDCP2_GAMUT_REMAP_C33_C34                                              0x1e5f
++#define mmDCP3_GAMUT_REMAP_C33_C34                                              0x405f
++#define mmDCP4_GAMUT_REMAP_C33_C34                                              0x425f
++#define mmDCP5_GAMUT_REMAP_C33_C34                                              0x445f
++#define mmDCP_SPATIAL_DITHER_CNTL                                               0x1a60
++#define mmDCP0_DCP_SPATIAL_DITHER_CNTL                                          0x1a60
++#define mmDCP1_DCP_SPATIAL_DITHER_CNTL                                          0x1c60
++#define mmDCP2_DCP_SPATIAL_DITHER_CNTL                                          0x1e60
++#define mmDCP3_DCP_SPATIAL_DITHER_CNTL                                          0x4060
++#define mmDCP4_DCP_SPATIAL_DITHER_CNTL                                          0x4260
++#define mmDCP5_DCP_SPATIAL_DITHER_CNTL                                          0x4460
++#define mmDCP_FP_CONVERTED_FIELD                                                0x1a65
++#define mmDCP0_DCP_FP_CONVERTED_FIELD                                           0x1a65
++#define mmDCP1_DCP_FP_CONVERTED_FIELD                                           0x1c65
++#define mmDCP2_DCP_FP_CONVERTED_FIELD                                           0x1e65
++#define mmDCP3_DCP_FP_CONVERTED_FIELD                                           0x4065
++#define mmDCP4_DCP_FP_CONVERTED_FIELD                                           0x4265
++#define mmDCP5_DCP_FP_CONVERTED_FIELD                                           0x4465
++#define mmCUR_CONTROL                                                           0x1a66
++#define mmDCP0_CUR_CONTROL                                                      0x1a66
++#define mmDCP1_CUR_CONTROL                                                      0x1c66
++#define mmDCP2_CUR_CONTROL                                                      0x1e66
++#define mmDCP3_CUR_CONTROL                                                      0x4066
++#define mmDCP4_CUR_CONTROL                                                      0x4266
++#define mmDCP5_CUR_CONTROL                                                      0x4466
++#define mmCUR_SURFACE_ADDRESS                                                   0x1a67
++#define mmDCP0_CUR_SURFACE_ADDRESS                                              0x1a67
++#define mmDCP1_CUR_SURFACE_ADDRESS                                              0x1c67
++#define mmDCP2_CUR_SURFACE_ADDRESS                                              0x1e67
++#define mmDCP3_CUR_SURFACE_ADDRESS                                              0x4067
++#define mmDCP4_CUR_SURFACE_ADDRESS                                              0x4267
++#define mmDCP5_CUR_SURFACE_ADDRESS                                              0x4467
++#define mmCUR_SIZE                                                              0x1a68
++#define mmDCP0_CUR_SIZE                                                         0x1a68
++#define mmDCP1_CUR_SIZE                                                         0x1c68
++#define mmDCP2_CUR_SIZE                                                         0x1e68
++#define mmDCP3_CUR_SIZE                                                         0x4068
++#define mmDCP4_CUR_SIZE                                                         0x4268
++#define mmDCP5_CUR_SIZE                                                         0x4468
++#define mmCUR_SURFACE_ADDRESS_HIGH                                              0x1a69
++#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                         0x1a69
++#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                         0x1c69
++#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                         0x1e69
++#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                         0x4069
++#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                         0x4269
++#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                         0x4469
++#define mmCUR_POSITION                                                          0x1a6a
++#define mmDCP0_CUR_POSITION                                                     0x1a6a
++#define mmDCP1_CUR_POSITION                                                     0x1c6a
++#define mmDCP2_CUR_POSITION                                                     0x1e6a
++#define mmDCP3_CUR_POSITION                                                     0x406a
++#define mmDCP4_CUR_POSITION                                                     0x426a
++#define mmDCP5_CUR_POSITION                                                     0x446a
++#define mmCUR_HOT_SPOT                                                          0x1a6b
++#define mmDCP0_CUR_HOT_SPOT                                                     0x1a6b
++#define mmDCP1_CUR_HOT_SPOT                                                     0x1c6b
++#define mmDCP2_CUR_HOT_SPOT                                                     0x1e6b
++#define mmDCP3_CUR_HOT_SPOT                                                     0x406b
++#define mmDCP4_CUR_HOT_SPOT                                                     0x426b
++#define mmDCP5_CUR_HOT_SPOT                                                     0x446b
++#define mmCUR_COLOR1                                                            0x1a6c
++#define mmDCP0_CUR_COLOR1                                                       0x1a6c
++#define mmDCP1_CUR_COLOR1                                                       0x1c6c
++#define mmDCP2_CUR_COLOR1                                                       0x1e6c
++#define mmDCP3_CUR_COLOR1                                                       0x406c
++#define mmDCP4_CUR_COLOR1                                                       0x426c
++#define mmDCP5_CUR_COLOR1                                                       0x446c
++#define mmCUR_COLOR2                                                            0x1a6d
++#define mmDCP0_CUR_COLOR2                                                       0x1a6d
++#define mmDCP1_CUR_COLOR2                                                       0x1c6d
++#define mmDCP2_CUR_COLOR2                                                       0x1e6d
++#define mmDCP3_CUR_COLOR2                                                       0x406d
++#define mmDCP4_CUR_COLOR2                                                       0x426d
++#define mmDCP5_CUR_COLOR2                                                       0x446d
++#define mmCUR_UPDATE                                                            0x1a6e
++#define mmDCP0_CUR_UPDATE                                                       0x1a6e
++#define mmDCP1_CUR_UPDATE                                                       0x1c6e
++#define mmDCP2_CUR_UPDATE                                                       0x1e6e
++#define mmDCP3_CUR_UPDATE                                                       0x406e
++#define mmDCP4_CUR_UPDATE                                                       0x426e
++#define mmDCP5_CUR_UPDATE                                                       0x446e
++#define mmCUR_REQUEST_FILTER_CNTL                                               0x1a99
++#define mmDCP0_CUR_REQUEST_FILTER_CNTL                                          0x1a99
++#define mmDCP1_CUR_REQUEST_FILTER_CNTL                                          0x1c99
++#define mmDCP2_CUR_REQUEST_FILTER_CNTL                                          0x1e99
++#define mmDCP3_CUR_REQUEST_FILTER_CNTL                                          0x4099
++#define mmDCP4_CUR_REQUEST_FILTER_CNTL                                          0x4299
++#define mmDCP5_CUR_REQUEST_FILTER_CNTL                                          0x4499
++#define mmCUR_STEREO_CONTROL                                                    0x1a9a
++#define mmDCP0_CUR_STEREO_CONTROL                                               0x1a9a
++#define mmDCP1_CUR_STEREO_CONTROL                                               0x1c9a
++#define mmDCP2_CUR_STEREO_CONTROL                                               0x1e9a
++#define mmDCP3_CUR_STEREO_CONTROL                                               0x409a
++#define mmDCP4_CUR_STEREO_CONTROL                                               0x429a
++#define mmDCP5_CUR_STEREO_CONTROL                                               0x449a
++#define mmDC_LUT_RW_MODE                                                        0x1a78
++#define mmDCP0_DC_LUT_RW_MODE                                                   0x1a78
++#define mmDCP1_DC_LUT_RW_MODE                                                   0x1c78
++#define mmDCP2_DC_LUT_RW_MODE                                                   0x1e78
++#define mmDCP3_DC_LUT_RW_MODE                                                   0x4078
++#define mmDCP4_DC_LUT_RW_MODE                                                   0x4278
++#define mmDCP5_DC_LUT_RW_MODE                                                   0x4478
++#define mmDC_LUT_RW_INDEX                                                       0x1a79
++#define mmDCP0_DC_LUT_RW_INDEX                                                  0x1a79
++#define mmDCP1_DC_LUT_RW_INDEX                                                  0x1c79
++#define mmDCP2_DC_LUT_RW_INDEX                                                  0x1e79
++#define mmDCP3_DC_LUT_RW_INDEX                                                  0x4079
++#define mmDCP4_DC_LUT_RW_INDEX                                                  0x4279
++#define mmDCP5_DC_LUT_RW_INDEX                                                  0x4479
++#define mmDC_LUT_SEQ_COLOR                                                      0x1a7a
++#define mmDCP0_DC_LUT_SEQ_COLOR                                                 0x1a7a
++#define mmDCP1_DC_LUT_SEQ_COLOR                                                 0x1c7a
++#define mmDCP2_DC_LUT_SEQ_COLOR                                                 0x1e7a
++#define mmDCP3_DC_LUT_SEQ_COLOR                                                 0x407a
++#define mmDCP4_DC_LUT_SEQ_COLOR                                                 0x427a
++#define mmDCP5_DC_LUT_SEQ_COLOR                                                 0x447a
++#define mmDC_LUT_PWL_DATA                                                       0x1a7b
++#define mmDCP0_DC_LUT_PWL_DATA                                                  0x1a7b
++#define mmDCP1_DC_LUT_PWL_DATA                                                  0x1c7b
++#define mmDCP2_DC_LUT_PWL_DATA                                                  0x1e7b
++#define mmDCP3_DC_LUT_PWL_DATA                                                  0x407b
++#define mmDCP4_DC_LUT_PWL_DATA                                                  0x427b
++#define mmDCP5_DC_LUT_PWL_DATA                                                  0x447b
++#define mmDC_LUT_30_COLOR                                                       0x1a7c
++#define mmDCP0_DC_LUT_30_COLOR                                                  0x1a7c
++#define mmDCP1_DC_LUT_30_COLOR                                                  0x1c7c
++#define mmDCP2_DC_LUT_30_COLOR                                                  0x1e7c
++#define mmDCP3_DC_LUT_30_COLOR                                                  0x407c
++#define mmDCP4_DC_LUT_30_COLOR                                                  0x427c
++#define mmDCP5_DC_LUT_30_COLOR                                                  0x447c
++#define mmDC_LUT_VGA_ACCESS_ENABLE                                              0x1a7d
++#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                         0x1a7d
++#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                         0x1c7d
++#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                         0x1e7d
++#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                         0x407d
++#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                         0x427d
++#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                         0x447d
++#define mmDC_LUT_WRITE_EN_MASK                                                  0x1a7e
++#define mmDCP0_DC_LUT_WRITE_EN_MASK                                             0x1a7e
++#define mmDCP1_DC_LUT_WRITE_EN_MASK                                             0x1c7e
++#define mmDCP2_DC_LUT_WRITE_EN_MASK                                             0x1e7e
++#define mmDCP3_DC_LUT_WRITE_EN_MASK                                             0x407e
++#define mmDCP4_DC_LUT_WRITE_EN_MASK                                             0x427e
++#define mmDCP5_DC_LUT_WRITE_EN_MASK                                             0x447e
++#define mmDC_LUT_AUTOFILL                                                       0x1a7f
++#define mmDCP0_DC_LUT_AUTOFILL                                                  0x1a7f
++#define mmDCP1_DC_LUT_AUTOFILL                                                  0x1c7f
++#define mmDCP2_DC_LUT_AUTOFILL                                                  0x1e7f
++#define mmDCP3_DC_LUT_AUTOFILL                                                  0x407f
++#define mmDCP4_DC_LUT_AUTOFILL                                                  0x427f
++#define mmDCP5_DC_LUT_AUTOFILL                                                  0x447f
++#define mmDC_LUT_CONTROL                                                        0x1a80
++#define mmDCP0_DC_LUT_CONTROL                                                   0x1a80
++#define mmDCP1_DC_LUT_CONTROL                                                   0x1c80
++#define mmDCP2_DC_LUT_CONTROL                                                   0x1e80
++#define mmDCP3_DC_LUT_CONTROL                                                   0x4080
++#define mmDCP4_DC_LUT_CONTROL                                                   0x4280
++#define mmDCP5_DC_LUT_CONTROL                                                   0x4480
++#define mmDC_LUT_BLACK_OFFSET_BLUE                                              0x1a81
++#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                         0x1a81
++#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                         0x1c81
++#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                         0x1e81
++#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                         0x4081
++#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                         0x4281
++#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                         0x4481
++#define mmDC_LUT_BLACK_OFFSET_GREEN                                             0x1a82
++#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                        0x1a82
++#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                        0x1c82
++#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                        0x1e82
++#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                        0x4082
++#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                        0x4282
++#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                        0x4482
++#define mmDC_LUT_BLACK_OFFSET_RED                                               0x1a83
++#define mmDCP0_DC_LUT_BLACK_OFFSET_RED                                          0x1a83
++#define mmDCP1_DC_LUT_BLACK_OFFSET_RED                                          0x1c83
++#define mmDCP2_DC_LUT_BLACK_OFFSET_RED                                          0x1e83
++#define mmDCP3_DC_LUT_BLACK_OFFSET_RED                                          0x4083
++#define mmDCP4_DC_LUT_BLACK_OFFSET_RED                                          0x4283
++#define mmDCP5_DC_LUT_BLACK_OFFSET_RED                                          0x4483
++#define mmDC_LUT_WHITE_OFFSET_BLUE                                              0x1a84
++#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                         0x1a84
++#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                         0x1c84
++#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                         0x1e84
++#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                         0x4084
++#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                         0x4284
++#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                         0x4484
++#define mmDC_LUT_WHITE_OFFSET_GREEN                                             0x1a85
++#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                        0x1a85
++#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                        0x1c85
++#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                        0x1e85
++#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                        0x4085
++#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                        0x4285
++#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                        0x4485
++#define mmDC_LUT_WHITE_OFFSET_RED                                               0x1a86
++#define mmDCP0_DC_LUT_WHITE_OFFSET_RED                                          0x1a86
++#define mmDCP1_DC_LUT_WHITE_OFFSET_RED                                          0x1c86
++#define mmDCP2_DC_LUT_WHITE_OFFSET_RED                                          0x1e86
++#define mmDCP3_DC_LUT_WHITE_OFFSET_RED                                          0x4086
++#define mmDCP4_DC_LUT_WHITE_OFFSET_RED                                          0x4286
++#define mmDCP5_DC_LUT_WHITE_OFFSET_RED                                          0x4486
++#define mmDCP_CRC_CONTROL                                                       0x1a87
++#define mmDCP0_DCP_CRC_CONTROL                                                  0x1a87
++#define mmDCP1_DCP_CRC_CONTROL                                                  0x1c87
++#define mmDCP2_DCP_CRC_CONTROL                                                  0x1e87
++#define mmDCP3_DCP_CRC_CONTROL                                                  0x4087
++#define mmDCP4_DCP_CRC_CONTROL                                                  0x4287
++#define mmDCP5_DCP_CRC_CONTROL                                                  0x4487
++#define mmDCP_CRC_MASK                                                          0x1a88
++#define mmDCP0_DCP_CRC_MASK                                                     0x1a88
++#define mmDCP1_DCP_CRC_MASK                                                     0x1c88
++#define mmDCP2_DCP_CRC_MASK                                                     0x1e88
++#define mmDCP3_DCP_CRC_MASK                                                     0x4088
++#define mmDCP4_DCP_CRC_MASK                                                     0x4288
++#define mmDCP5_DCP_CRC_MASK                                                     0x4488
++#define mmDCP_CRC_CURRENT                                                       0x1a89
++#define mmDCP0_DCP_CRC_CURRENT                                                  0x1a89
++#define mmDCP1_DCP_CRC_CURRENT                                                  0x1c89
++#define mmDCP2_DCP_CRC_CURRENT                                                  0x1e89
++#define mmDCP3_DCP_CRC_CURRENT                                                  0x4089
++#define mmDCP4_DCP_CRC_CURRENT                                                  0x4289
++#define mmDCP5_DCP_CRC_CURRENT                                                  0x4489
++#define mmDVMM_PTE_CONTROL                                                      0x1a8a
++#define mmDCP0_DVMM_PTE_CONTROL                                                 0x1a8a
++#define mmDCP1_DVMM_PTE_CONTROL                                                 0x1c8a
++#define mmDCP2_DVMM_PTE_CONTROL                                                 0x1e8a
++#define mmDCP3_DVMM_PTE_CONTROL                                                 0x408a
++#define mmDCP4_DVMM_PTE_CONTROL                                                 0x428a
++#define mmDCP5_DVMM_PTE_CONTROL                                                 0x448a
++#define mmDCP_CRC_LAST                                                          0x1a8b
++#define mmDCP0_DCP_CRC_LAST                                                     0x1a8b
++#define mmDCP1_DCP_CRC_LAST                                                     0x1c8b
++#define mmDCP2_DCP_CRC_LAST                                                     0x1e8b
++#define mmDCP3_DCP_CRC_LAST                                                     0x408b
++#define mmDCP4_DCP_CRC_LAST                                                     0x428b
++#define mmDCP5_DCP_CRC_LAST                                                     0x448b
++#define mmDVMM_PTE_ARB_CONTROL                                                  0x1a8c
++#define mmDCP0_DVMM_PTE_ARB_CONTROL                                             0x1a8c
++#define mmDCP1_DVMM_PTE_ARB_CONTROL                                             0x1c8c
++#define mmDCP2_DVMM_PTE_ARB_CONTROL                                             0x1e8c
++#define mmDCP3_DVMM_PTE_ARB_CONTROL                                             0x408c
++#define mmDCP4_DVMM_PTE_ARB_CONTROL                                             0x428c
++#define mmDCP5_DVMM_PTE_ARB_CONTROL                                             0x448c
++#define mmDCP_DEBUG                                                             0x1a8d
++#define mmDCP0_DCP_DEBUG                                                        0x1a8d
++#define mmDCP1_DCP_DEBUG                                                        0x1c8d
++#define mmDCP2_DCP_DEBUG                                                        0x1e8d
++#define mmDCP3_DCP_DEBUG                                                        0x408d
++#define mmDCP4_DCP_DEBUG                                                        0x428d
++#define mmDCP5_DCP_DEBUG                                                        0x448d
++#define mmGRPH_FLIP_RATE_CNTL                                                   0x1a8e
++#define mmDCP0_GRPH_FLIP_RATE_CNTL                                              0x1a8e
++#define mmDCP1_GRPH_FLIP_RATE_CNTL                                              0x1c8e
++#define mmDCP2_GRPH_FLIP_RATE_CNTL                                              0x1e8e
++#define mmDCP3_GRPH_FLIP_RATE_CNTL                                              0x408e
++#define mmDCP4_GRPH_FLIP_RATE_CNTL                                              0x428e
++#define mmDCP5_GRPH_FLIP_RATE_CNTL                                              0x448e
++#define mmDCP_GSL_CONTROL                                                       0x1a90
++#define mmDCP0_DCP_GSL_CONTROL                                                  0x1a90
++#define mmDCP1_DCP_GSL_CONTROL                                                  0x1c90
++#define mmDCP2_DCP_GSL_CONTROL                                                  0x1e90
++#define mmDCP3_DCP_GSL_CONTROL                                                  0x4090
++#define mmDCP4_DCP_GSL_CONTROL                                                  0x4290
++#define mmDCP5_DCP_GSL_CONTROL                                                  0x4490
++#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x1a91
++#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1a91
++#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1c91
++#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1e91
++#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4091
++#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4291
++#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4491
++#define mmDCP_DEBUG_SG                                                          0x1a92
++#define mmDCP0_DCP_DEBUG_SG                                                     0x1a92
++#define mmDCP1_DCP_DEBUG_SG                                                     0x1c92
++#define mmDCP2_DCP_DEBUG_SG                                                     0x1e92
++#define mmDCP3_DCP_DEBUG_SG                                                     0x4092
++#define mmDCP4_DCP_DEBUG_SG                                                     0x4292
++#define mmDCP5_DCP_DEBUG_SG                                                     0x4492
++#define mmDCP_DEBUG_SG2                                                         0x1a94
++#define mmDCP0_DCP_DEBUG_SG2                                                    0x1a94
++#define mmDCP1_DCP_DEBUG_SG2                                                    0x1c94
++#define mmDCP2_DCP_DEBUG_SG2                                                    0x1e94
++#define mmDCP3_DCP_DEBUG_SG2                                                    0x4094
++#define mmDCP4_DCP_DEBUG_SG2                                                    0x4294
++#define mmDCP5_DCP_DEBUG_SG2                                                    0x4494
++#define mmDCP_DVMM_DEBUG                                                        0x1a93
++#define mmDCP0_DCP_DVMM_DEBUG                                                   0x1a93
++#define mmDCP1_DCP_DVMM_DEBUG                                                   0x1c93
++#define mmDCP2_DCP_DVMM_DEBUG                                                   0x1e93
++#define mmDCP3_DCP_DVMM_DEBUG                                                   0x4093
++#define mmDCP4_DCP_DVMM_DEBUG                                                   0x4293
++#define mmDCP5_DCP_DVMM_DEBUG                                                   0x4493
++#define mmDCP_TEST_DEBUG_INDEX                                                  0x1a95
++#define mmDCP0_DCP_TEST_DEBUG_INDEX                                             0x1a95
++#define mmDCP1_DCP_TEST_DEBUG_INDEX                                             0x1c95
++#define mmDCP2_DCP_TEST_DEBUG_INDEX                                             0x1e95
++#define mmDCP3_DCP_TEST_DEBUG_INDEX                                             0x4095
++#define mmDCP4_DCP_TEST_DEBUG_INDEX                                             0x4295
++#define mmDCP5_DCP_TEST_DEBUG_INDEX                                             0x4495
++#define mmDCP_TEST_DEBUG_DATA                                                   0x1a96
++#define mmDCP0_DCP_TEST_DEBUG_DATA                                              0x1a96
++#define mmDCP1_DCP_TEST_DEBUG_DATA                                              0x1c96
++#define mmDCP2_DCP_TEST_DEBUG_DATA                                              0x1e96
++#define mmDCP3_DCP_TEST_DEBUG_DATA                                              0x4096
++#define mmDCP4_DCP_TEST_DEBUG_DATA                                              0x4296
++#define mmDCP5_DCP_TEST_DEBUG_DATA                                              0x4496
++#define mmGRPH_STEREOSYNC_FLIP                                                  0x1a97
++#define mmDCP0_GRPH_STEREOSYNC_FLIP                                             0x1a97
++#define mmDCP1_GRPH_STEREOSYNC_FLIP                                             0x1c97
++#define mmDCP2_GRPH_STEREOSYNC_FLIP                                             0x1e97
++#define mmDCP3_GRPH_STEREOSYNC_FLIP                                             0x4097
++#define mmDCP4_GRPH_STEREOSYNC_FLIP                                             0x4297
++#define mmDCP5_GRPH_STEREOSYNC_FLIP                                             0x4497
++#define mmDCP_DEBUG2                                                            0x1a98
++#define mmDCP0_DCP_DEBUG2                                                       0x1a98
++#define mmDCP1_DCP_DEBUG2                                                       0x1c98
++#define mmDCP2_DCP_DEBUG2                                                       0x1e98
++#define mmDCP3_DCP_DEBUG2                                                       0x4098
++#define mmDCP4_DCP_DEBUG2                                                       0x4298
++#define mmDCP5_DCP_DEBUG2                                                       0x4498
++#define mmHW_ROTATION                                                           0x1a9e
++#define mmDCP0_HW_ROTATION                                                      0x1a9e
++#define mmDCP1_HW_ROTATION                                                      0x1c9e
++#define mmDCP2_HW_ROTATION                                                      0x1e9e
++#define mmDCP3_HW_ROTATION                                                      0x409e
++#define mmDCP4_HW_ROTATION                                                      0x429e
++#define mmDCP5_HW_ROTATION                                                      0x449e
++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                    0x1a9f
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1a9f
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1c9f
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1e9f
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x409f
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x429f
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x449f
++#define mmREGAMMA_CONTROL                                                       0x1aa0
++#define mmDCP0_REGAMMA_CONTROL                                                  0x1aa0
++#define mmDCP1_REGAMMA_CONTROL                                                  0x1ca0
++#define mmDCP2_REGAMMA_CONTROL                                                  0x1ea0
++#define mmDCP3_REGAMMA_CONTROL                                                  0x40a0
++#define mmDCP4_REGAMMA_CONTROL                                                  0x42a0
++#define mmDCP5_REGAMMA_CONTROL                                                  0x44a0
++#define mmREGAMMA_LUT_INDEX                                                     0x1aa1
++#define mmDCP0_REGAMMA_LUT_INDEX                                                0x1aa1
++#define mmDCP1_REGAMMA_LUT_INDEX                                                0x1ca1
++#define mmDCP2_REGAMMA_LUT_INDEX                                                0x1ea1
++#define mmDCP3_REGAMMA_LUT_INDEX                                                0x40a1
++#define mmDCP4_REGAMMA_LUT_INDEX                                                0x42a1
++#define mmDCP5_REGAMMA_LUT_INDEX                                                0x44a1
++#define mmREGAMMA_LUT_DATA                                                      0x1aa2
++#define mmDCP0_REGAMMA_LUT_DATA                                                 0x1aa2
++#define mmDCP1_REGAMMA_LUT_DATA                                                 0x1ca2
++#define mmDCP2_REGAMMA_LUT_DATA                                                 0x1ea2
++#define mmDCP3_REGAMMA_LUT_DATA                                                 0x40a2
++#define mmDCP4_REGAMMA_LUT_DATA                                                 0x42a2
++#define mmDCP5_REGAMMA_LUT_DATA                                                 0x44a2
++#define mmREGAMMA_LUT_WRITE_EN_MASK                                             0x1aa3
++#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                        0x1aa3
++#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ca3
++#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ea3
++#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                        0x40a3
++#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                        0x42a3
++#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                        0x44a3
++#define mmREGAMMA_CNTLA_START_CNTL                                              0x1aa4
++#define mmDCP0_REGAMMA_CNTLA_START_CNTL                                         0x1aa4
++#define mmDCP1_REGAMMA_CNTLA_START_CNTL                                         0x1ca4
++#define mmDCP2_REGAMMA_CNTLA_START_CNTL                                         0x1ea4
++#define mmDCP3_REGAMMA_CNTLA_START_CNTL                                         0x40a4
++#define mmDCP4_REGAMMA_CNTLA_START_CNTL                                         0x42a4
++#define mmDCP5_REGAMMA_CNTLA_START_CNTL                                         0x44a4
++#define mmREGAMMA_CNTLA_SLOPE_CNTL                                              0x1aa5
++#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1aa5
++#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ca5
++#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ea5
++#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                         0x40a5
++#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                         0x42a5
++#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                         0x44a5
++#define mmREGAMMA_CNTLA_END_CNTL1                                               0x1aa6
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL1                                          0x1aa6
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL1                                          0x1ca6
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL1                                          0x1ea6
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL1                                          0x40a6
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL1                                          0x42a6
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL1                                          0x44a6
++#define mmREGAMMA_CNTLA_END_CNTL2                                               0x1aa7
++#define mmDCP0_REGAMMA_CNTLA_END_CNTL2                                          0x1aa7
++#define mmDCP1_REGAMMA_CNTLA_END_CNTL2                                          0x1ca7
++#define mmDCP2_REGAMMA_CNTLA_END_CNTL2                                          0x1ea7
++#define mmDCP3_REGAMMA_CNTLA_END_CNTL2                                          0x40a7
++#define mmDCP4_REGAMMA_CNTLA_END_CNTL2                                          0x42a7
++#define mmDCP5_REGAMMA_CNTLA_END_CNTL2                                          0x44a7
++#define mmREGAMMA_CNTLA_REGION_0_1                                              0x1aa8
++#define mmDCP0_REGAMMA_CNTLA_REGION_0_1                                         0x1aa8
++#define mmDCP1_REGAMMA_CNTLA_REGION_0_1                                         0x1ca8
++#define mmDCP2_REGAMMA_CNTLA_REGION_0_1                                         0x1ea8
++#define mmDCP3_REGAMMA_CNTLA_REGION_0_1                                         0x40a8
++#define mmDCP4_REGAMMA_CNTLA_REGION_0_1                                         0x42a8
++#define mmDCP5_REGAMMA_CNTLA_REGION_0_1                                         0x44a8
++#define mmREGAMMA_CNTLA_REGION_2_3                                              0x1aa9
++#define mmDCP0_REGAMMA_CNTLA_REGION_2_3                                         0x1aa9
++#define mmDCP1_REGAMMA_CNTLA_REGION_2_3                                         0x1ca9
++#define mmDCP2_REGAMMA_CNTLA_REGION_2_3                                         0x1ea9
++#define mmDCP3_REGAMMA_CNTLA_REGION_2_3                                         0x40a9
++#define mmDCP4_REGAMMA_CNTLA_REGION_2_3                                         0x42a9
++#define mmDCP5_REGAMMA_CNTLA_REGION_2_3                                         0x44a9
++#define mmREGAMMA_CNTLA_REGION_4_5                                              0x1aaa
++#define mmDCP0_REGAMMA_CNTLA_REGION_4_5                                         0x1aaa
++#define mmDCP1_REGAMMA_CNTLA_REGION_4_5                                         0x1caa
++#define mmDCP2_REGAMMA_CNTLA_REGION_4_5                                         0x1eaa
++#define mmDCP3_REGAMMA_CNTLA_REGION_4_5                                         0x40aa
++#define mmDCP4_REGAMMA_CNTLA_REGION_4_5                                         0x42aa
++#define mmDCP5_REGAMMA_CNTLA_REGION_4_5                                         0x44aa
++#define mmREGAMMA_CNTLA_REGION_6_7                                              0x1aab
++#define mmDCP0_REGAMMA_CNTLA_REGION_6_7                                         0x1aab
++#define mmDCP1_REGAMMA_CNTLA_REGION_6_7                                         0x1cab
++#define mmDCP2_REGAMMA_CNTLA_REGION_6_7                                         0x1eab
++#define mmDCP3_REGAMMA_CNTLA_REGION_6_7                                         0x40ab
++#define mmDCP4_REGAMMA_CNTLA_REGION_6_7                                         0x42ab
++#define mmDCP5_REGAMMA_CNTLA_REGION_6_7                                         0x44ab
++#define mmREGAMMA_CNTLA_REGION_8_9                                              0x1aac
++#define mmDCP0_REGAMMA_CNTLA_REGION_8_9                                         0x1aac
++#define mmDCP1_REGAMMA_CNTLA_REGION_8_9                                         0x1cac
++#define mmDCP2_REGAMMA_CNTLA_REGION_8_9                                         0x1eac
++#define mmDCP3_REGAMMA_CNTLA_REGION_8_9                                         0x40ac
++#define mmDCP4_REGAMMA_CNTLA_REGION_8_9                                         0x42ac
++#define mmDCP5_REGAMMA_CNTLA_REGION_8_9                                         0x44ac
++#define mmREGAMMA_CNTLA_REGION_10_11                                            0x1aad
++#define mmDCP0_REGAMMA_CNTLA_REGION_10_11                                       0x1aad
++#define mmDCP1_REGAMMA_CNTLA_REGION_10_11                                       0x1cad
++#define mmDCP2_REGAMMA_CNTLA_REGION_10_11                                       0x1ead
++#define mmDCP3_REGAMMA_CNTLA_REGION_10_11                                       0x40ad
++#define mmDCP4_REGAMMA_CNTLA_REGION_10_11                                       0x42ad
++#define mmDCP5_REGAMMA_CNTLA_REGION_10_11                                       0x44ad
++#define mmREGAMMA_CNTLA_REGION_12_13                                            0x1aae
++#define mmDCP0_REGAMMA_CNTLA_REGION_12_13                                       0x1aae
++#define mmDCP1_REGAMMA_CNTLA_REGION_12_13                                       0x1cae
++#define mmDCP2_REGAMMA_CNTLA_REGION_12_13                                       0x1eae
++#define mmDCP3_REGAMMA_CNTLA_REGION_12_13                                       0x40ae
++#define mmDCP4_REGAMMA_CNTLA_REGION_12_13                                       0x42ae
++#define mmDCP5_REGAMMA_CNTLA_REGION_12_13                                       0x44ae
++#define mmREGAMMA_CNTLA_REGION_14_15                                            0x1aaf
++#define mmDCP0_REGAMMA_CNTLA_REGION_14_15                                       0x1aaf
++#define mmDCP1_REGAMMA_CNTLA_REGION_14_15                                       0x1caf
++#define mmDCP2_REGAMMA_CNTLA_REGION_14_15                                       0x1eaf
++#define mmDCP3_REGAMMA_CNTLA_REGION_14_15                                       0x40af
++#define mmDCP4_REGAMMA_CNTLA_REGION_14_15                                       0x42af
++#define mmDCP5_REGAMMA_CNTLA_REGION_14_15                                       0x44af
++#define mmREGAMMA_CNTLB_START_CNTL                                              0x1ab0
++#define mmDCP0_REGAMMA_CNTLB_START_CNTL                                         0x1ab0
++#define mmDCP1_REGAMMA_CNTLB_START_CNTL                                         0x1cb0
++#define mmDCP2_REGAMMA_CNTLB_START_CNTL                                         0x1eb0
++#define mmDCP3_REGAMMA_CNTLB_START_CNTL                                         0x40b0
++#define mmDCP4_REGAMMA_CNTLB_START_CNTL                                         0x42b0
++#define mmDCP5_REGAMMA_CNTLB_START_CNTL                                         0x44b0
++#define mmREGAMMA_CNTLB_SLOPE_CNTL                                              0x1ab1
++#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1ab1
++#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1cb1
++#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1eb1
++#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                         0x40b1
++#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                         0x42b1
++#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                         0x44b1
++#define mmREGAMMA_CNTLB_END_CNTL1                                               0x1ab2
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL1                                          0x1ab2
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL1                                          0x1cb2
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL1                                          0x1eb2
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL1                                          0x40b2
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL1                                          0x42b2
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL1                                          0x44b2
++#define mmREGAMMA_CNTLB_END_CNTL2                                               0x1ab3
++#define mmDCP0_REGAMMA_CNTLB_END_CNTL2                                          0x1ab3
++#define mmDCP1_REGAMMA_CNTLB_END_CNTL2                                          0x1cb3
++#define mmDCP2_REGAMMA_CNTLB_END_CNTL2                                          0x1eb3
++#define mmDCP3_REGAMMA_CNTLB_END_CNTL2                                          0x40b3
++#define mmDCP4_REGAMMA_CNTLB_END_CNTL2                                          0x42b3
++#define mmDCP5_REGAMMA_CNTLB_END_CNTL2                                          0x44b3
++#define mmREGAMMA_CNTLB_REGION_0_1                                              0x1ab4
++#define mmDCP0_REGAMMA_CNTLB_REGION_0_1                                         0x1ab4
++#define mmDCP1_REGAMMA_CNTLB_REGION_0_1                                         0x1cb4
++#define mmDCP2_REGAMMA_CNTLB_REGION_0_1                                         0x1eb4
++#define mmDCP3_REGAMMA_CNTLB_REGION_0_1                                         0x40b4
++#define mmDCP4_REGAMMA_CNTLB_REGION_0_1                                         0x42b4
++#define mmDCP5_REGAMMA_CNTLB_REGION_0_1                                         0x44b4
++#define mmREGAMMA_CNTLB_REGION_2_3                                              0x1ab5
++#define mmDCP0_REGAMMA_CNTLB_REGION_2_3                                         0x1ab5
++#define mmDCP1_REGAMMA_CNTLB_REGION_2_3                                         0x1cb5
++#define mmDCP2_REGAMMA_CNTLB_REGION_2_3                                         0x1eb5
++#define mmDCP3_REGAMMA_CNTLB_REGION_2_3                                         0x40b5
++#define mmDCP4_REGAMMA_CNTLB_REGION_2_3                                         0x42b5
++#define mmDCP5_REGAMMA_CNTLB_REGION_2_3                                         0x44b5
++#define mmREGAMMA_CNTLB_REGION_4_5                                              0x1ab6
++#define mmDCP0_REGAMMA_CNTLB_REGION_4_5                                         0x1ab6
++#define mmDCP1_REGAMMA_CNTLB_REGION_4_5                                         0x1cb6
++#define mmDCP2_REGAMMA_CNTLB_REGION_4_5                                         0x1eb6
++#define mmDCP3_REGAMMA_CNTLB_REGION_4_5                                         0x40b6
++#define mmDCP4_REGAMMA_CNTLB_REGION_4_5                                         0x42b6
++#define mmDCP5_REGAMMA_CNTLB_REGION_4_5                                         0x44b6
++#define mmREGAMMA_CNTLB_REGION_6_7                                              0x1ab7
++#define mmDCP0_REGAMMA_CNTLB_REGION_6_7                                         0x1ab7
++#define mmDCP1_REGAMMA_CNTLB_REGION_6_7                                         0x1cb7
++#define mmDCP2_REGAMMA_CNTLB_REGION_6_7                                         0x1eb7
++#define mmDCP3_REGAMMA_CNTLB_REGION_6_7                                         0x40b7
++#define mmDCP4_REGAMMA_CNTLB_REGION_6_7                                         0x42b7
++#define mmDCP5_REGAMMA_CNTLB_REGION_6_7                                         0x44b7
++#define mmREGAMMA_CNTLB_REGION_8_9                                              0x1ab8
++#define mmDCP0_REGAMMA_CNTLB_REGION_8_9                                         0x1ab8
++#define mmDCP1_REGAMMA_CNTLB_REGION_8_9                                         0x1cb8
++#define mmDCP2_REGAMMA_CNTLB_REGION_8_9                                         0x1eb8
++#define mmDCP3_REGAMMA_CNTLB_REGION_8_9                                         0x40b8
++#define mmDCP4_REGAMMA_CNTLB_REGION_8_9                                         0x42b8
++#define mmDCP5_REGAMMA_CNTLB_REGION_8_9                                         0x44b8
++#define mmREGAMMA_CNTLB_REGION_10_11                                            0x1ab9
++#define mmDCP0_REGAMMA_CNTLB_REGION_10_11                                       0x1ab9
++#define mmDCP1_REGAMMA_CNTLB_REGION_10_11                                       0x1cb9
++#define mmDCP2_REGAMMA_CNTLB_REGION_10_11                                       0x1eb9
++#define mmDCP3_REGAMMA_CNTLB_REGION_10_11                                       0x40b9
++#define mmDCP4_REGAMMA_CNTLB_REGION_10_11                                       0x42b9
++#define mmDCP5_REGAMMA_CNTLB_REGION_10_11                                       0x44b9
++#define mmREGAMMA_CNTLB_REGION_12_13                                            0x1aba
++#define mmDCP0_REGAMMA_CNTLB_REGION_12_13                                       0x1aba
++#define mmDCP1_REGAMMA_CNTLB_REGION_12_13                                       0x1cba
++#define mmDCP2_REGAMMA_CNTLB_REGION_12_13                                       0x1eba
++#define mmDCP3_REGAMMA_CNTLB_REGION_12_13                                       0x40ba
++#define mmDCP4_REGAMMA_CNTLB_REGION_12_13                                       0x42ba
++#define mmDCP5_REGAMMA_CNTLB_REGION_12_13                                       0x44ba
++#define mmREGAMMA_CNTLB_REGION_14_15                                            0x1abb
++#define mmDCP0_REGAMMA_CNTLB_REGION_14_15                                       0x1abb
++#define mmDCP1_REGAMMA_CNTLB_REGION_14_15                                       0x1cbb
++#define mmDCP2_REGAMMA_CNTLB_REGION_14_15                                       0x1ebb
++#define mmDCP3_REGAMMA_CNTLB_REGION_14_15                                       0x40bb
++#define mmDCP4_REGAMMA_CNTLB_REGION_14_15                                       0x42bb
++#define mmDCP5_REGAMMA_CNTLB_REGION_14_15                                       0x44bb
++#define mmALPHA_CONTROL                                                         0x1abc
++#define mmDCP0_ALPHA_CONTROL                                                    0x1abc
++#define mmDCP1_ALPHA_CONTROL                                                    0x1cbc
++#define mmDCP2_ALPHA_CONTROL                                                    0x1ebc
++#define mmDCP3_ALPHA_CONTROL                                                    0x40bc
++#define mmDCP4_ALPHA_CONTROL                                                    0x42bc
++#define mmDCP5_ALPHA_CONTROL                                                    0x44bc
++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                    0x1abd
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1abd
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1cbd
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1ebd
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x40bd
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x42bd
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x44bd
++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                               0x1abe
++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1abe
++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1cbe
++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1ebe
++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x40be
++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x42be
++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x44be
++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                  0x1abf
++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1abf
++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1cbf
++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1ebf
++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x40bf
++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x42bf
++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x44bf
++#define mmGRPH_SURFACE_COUNTER_CONTROL                                          0x1a0f
++#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL                                     0x1a0f
++#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL                                     0x1c0f
++#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL                                     0x1e0f
++#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL                                     0x400f
++#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL                                     0x420f
++#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL                                     0x440f
++#define mmGRPH_SURFACE_COUNTER_OUTPUT                                           0x1a1d
++#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1a1d
++#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1c1d
++#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1e1d
++#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT                                      0x401d
++#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT                                      0x421d
++#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT                                      0x441d
++#define mmDIG_FE_CNTL                                                           0x4a00
++#define mmDIG0_DIG_FE_CNTL                                                      0x4a00
++#define mmDIG1_DIG_FE_CNTL                                                      0x4b00
++#define mmDIG2_DIG_FE_CNTL                                                      0x4c00
++#define mmDIG3_DIG_FE_CNTL                                                      0x4d00
++#define mmDIG4_DIG_FE_CNTL                                                      0x4e00
++#define mmDIG5_DIG_FE_CNTL                                                      0x4f00
++#define mmDIG6_DIG_FE_CNTL                                                      0x5400
++#define mmDIG7_DIG_FE_CNTL                                                      0x5600
++#define mmDIG8_DIG_FE_CNTL                                                      0x5700
++#define mmDIG_OUTPUT_CRC_CNTL                                                   0x4a01
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                              0x4a01
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                              0x4b01
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                              0x4c01
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                              0x4d01
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL                                              0x4e01
++#define mmDIG5_DIG_OUTPUT_CRC_CNTL                                              0x4f01
++#define mmDIG6_DIG_OUTPUT_CRC_CNTL                                              0x5401
++#define mmDIG7_DIG_OUTPUT_CRC_CNTL                                              0x5601
++#define mmDIG8_DIG_OUTPUT_CRC_CNTL                                              0x5701
++#define mmDIG_OUTPUT_CRC_RESULT                                                 0x4a02
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                            0x4a02
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                            0x4b02
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                            0x4c02
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                            0x4d02
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT                                            0x4e02
++#define mmDIG5_DIG_OUTPUT_CRC_RESULT                                            0x4f02
++#define mmDIG6_DIG_OUTPUT_CRC_RESULT                                            0x5402
++#define mmDIG7_DIG_OUTPUT_CRC_RESULT                                            0x5602
++#define mmDIG8_DIG_OUTPUT_CRC_RESULT                                            0x5702
++#define mmDIG_CLOCK_PATTERN                                                     0x4a03
++#define mmDIG0_DIG_CLOCK_PATTERN                                                0x4a03
++#define mmDIG1_DIG_CLOCK_PATTERN                                                0x4b03
++#define mmDIG2_DIG_CLOCK_PATTERN                                                0x4c03
++#define mmDIG3_DIG_CLOCK_PATTERN                                                0x4d03
++#define mmDIG4_DIG_CLOCK_PATTERN                                                0x4e03
++#define mmDIG5_DIG_CLOCK_PATTERN                                                0x4f03
++#define mmDIG6_DIG_CLOCK_PATTERN                                                0x5403
++#define mmDIG7_DIG_CLOCK_PATTERN                                                0x5603
++#define mmDIG8_DIG_CLOCK_PATTERN                                                0x5703
++#define mmDIG_TEST_PATTERN                                                      0x4a04
++#define mmDIG0_DIG_TEST_PATTERN                                                 0x4a04
++#define mmDIG1_DIG_TEST_PATTERN                                                 0x4b04
++#define mmDIG2_DIG_TEST_PATTERN                                                 0x4c04
++#define mmDIG3_DIG_TEST_PATTERN                                                 0x4d04
++#define mmDIG4_DIG_TEST_PATTERN                                                 0x4e04
++#define mmDIG5_DIG_TEST_PATTERN                                                 0x4f04
++#define mmDIG6_DIG_TEST_PATTERN                                                 0x5404
++#define mmDIG7_DIG_TEST_PATTERN                                                 0x5604
++#define mmDIG8_DIG_TEST_PATTERN                                                 0x5704
++#define mmDIG_RANDOM_PATTERN_SEED                                               0x4a05
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                          0x4a05
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                          0x4b05
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                          0x4c05
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                          0x4d05
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED                                          0x4e05
++#define mmDIG5_DIG_RANDOM_PATTERN_SEED                                          0x4f05
++#define mmDIG6_DIG_RANDOM_PATTERN_SEED                                          0x5405
++#define mmDIG7_DIG_RANDOM_PATTERN_SEED                                          0x5605
++#define mmDIG8_DIG_RANDOM_PATTERN_SEED                                          0x5705
++#define mmDIG_FIFO_STATUS                                                       0x4a06
++#define mmDIG0_DIG_FIFO_STATUS                                                  0x4a06
++#define mmDIG1_DIG_FIFO_STATUS                                                  0x4b06
++#define mmDIG2_DIG_FIFO_STATUS                                                  0x4c06
++#define mmDIG3_DIG_FIFO_STATUS                                                  0x4d06
++#define mmDIG4_DIG_FIFO_STATUS                                                  0x4e06
++#define mmDIG5_DIG_FIFO_STATUS                                                  0x4f06
++#define mmDIG6_DIG_FIFO_STATUS                                                  0x5406
++#define mmDIG7_DIG_FIFO_STATUS                                                  0x5606
++#define mmDIG8_DIG_FIFO_STATUS                                                  0x5706
++#define mmDIG_DISPCLK_SWITCH_CNTL                                               0x4a07
++#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL                                          0x4a07
++#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL                                          0x4b07
++#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL                                          0x4c07
++#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL                                          0x4d07
++#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL                                          0x4e07
++#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL                                          0x4f07
++#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL                                          0x5407
++#define mmDIG7_DIG_DISPCLK_SWITCH_CNTL                                          0x5607
++#define mmDIG8_DIG_DISPCLK_SWITCH_CNTL                                          0x5707
++#define mmDIG_DISPCLK_SWITCH_STATUS                                             0x4a08
++#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS                                        0x4a08
++#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS                                        0x4b08
++#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS                                        0x4c08
++#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS                                        0x4d08
++#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS                                        0x4e08
++#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS                                        0x4f08
++#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS                                        0x5408
++#define mmDIG7_DIG_DISPCLK_SWITCH_STATUS                                        0x5608
++#define mmDIG8_DIG_DISPCLK_SWITCH_STATUS                                        0x5708
++#define mmHDMI_CONTROL                                                          0x4a09
++#define mmDIG0_HDMI_CONTROL                                                     0x4a09
++#define mmDIG1_HDMI_CONTROL                                                     0x4b09
++#define mmDIG2_HDMI_CONTROL                                                     0x4c09
++#define mmDIG3_HDMI_CONTROL                                                     0x4d09
++#define mmDIG4_HDMI_CONTROL                                                     0x4e09
++#define mmDIG5_HDMI_CONTROL                                                     0x4f09
++#define mmDIG6_HDMI_CONTROL                                                     0x5409
++#define mmDIG7_HDMI_CONTROL                                                     0x5609
++#define mmDIG8_HDMI_CONTROL                                                     0x5709
++#define mmHDMI_STATUS                                                           0x4a0a
++#define mmDIG0_HDMI_STATUS                                                      0x4a0a
++#define mmDIG1_HDMI_STATUS                                                      0x4b0a
++#define mmDIG2_HDMI_STATUS                                                      0x4c0a
++#define mmDIG3_HDMI_STATUS                                                      0x4d0a
++#define mmDIG4_HDMI_STATUS                                                      0x4e0a
++#define mmDIG5_HDMI_STATUS                                                      0x4f0a
++#define mmDIG6_HDMI_STATUS                                                      0x540a
++#define mmDIG7_HDMI_STATUS                                                      0x560a
++#define mmDIG8_HDMI_STATUS                                                      0x570a
++#define mmHDMI_AUDIO_PACKET_CONTROL                                             0x4a0b
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                        0x4a0b
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                        0x4b0b
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                        0x4c0b
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                        0x4d0b
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                        0x4e0b
++#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                        0x4f0b
++#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                        0x540b
++#define mmDIG7_HDMI_AUDIO_PACKET_CONTROL                                        0x560b
++#define mmDIG8_HDMI_AUDIO_PACKET_CONTROL                                        0x570b
++#define mmHDMI_ACR_PACKET_CONTROL                                               0x4a0c
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                          0x4a0c
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                          0x4b0c
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                          0x4c0c
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                          0x4d0c
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL                                          0x4e0c
++#define mmDIG5_HDMI_ACR_PACKET_CONTROL                                          0x4f0c
++#define mmDIG6_HDMI_ACR_PACKET_CONTROL                                          0x540c
++#define mmDIG7_HDMI_ACR_PACKET_CONTROL                                          0x560c
++#define mmDIG8_HDMI_ACR_PACKET_CONTROL                                          0x570c
++#define mmHDMI_VBI_PACKET_CONTROL                                               0x4a0d
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                          0x4a0d
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                          0x4b0d
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                          0x4c0d
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                          0x4d0d
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL                                          0x4e0d
++#define mmDIG5_HDMI_VBI_PACKET_CONTROL                                          0x4f0d
++#define mmDIG6_HDMI_VBI_PACKET_CONTROL                                          0x540d
++#define mmDIG7_HDMI_VBI_PACKET_CONTROL                                          0x560d
++#define mmDIG8_HDMI_VBI_PACKET_CONTROL                                          0x570d
++#define mmHDMI_INFOFRAME_CONTROL0                                               0x4a0e
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                          0x4a0e
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                          0x4b0e
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                          0x4c0e
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                          0x4d0e
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0                                          0x4e0e
++#define mmDIG5_HDMI_INFOFRAME_CONTROL0                                          0x4f0e
++#define mmDIG6_HDMI_INFOFRAME_CONTROL0                                          0x540e
++#define mmDIG7_HDMI_INFOFRAME_CONTROL0                                          0x560e
++#define mmDIG8_HDMI_INFOFRAME_CONTROL0                                          0x570e
++#define mmHDMI_INFOFRAME_CONTROL1                                               0x4a0f
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                          0x4a0f
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                          0x4b0f
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                          0x4c0f
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                          0x4d0f
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1                                          0x4e0f
++#define mmDIG5_HDMI_INFOFRAME_CONTROL1                                          0x4f0f
++#define mmDIG6_HDMI_INFOFRAME_CONTROL1                                          0x540f
++#define mmDIG7_HDMI_INFOFRAME_CONTROL1                                          0x560f
++#define mmDIG8_HDMI_INFOFRAME_CONTROL1                                          0x570f
++#define mmHDMI_GENERIC_PACKET_CONTROL0                                          0x4a10
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                     0x4a10
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                     0x4b10
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                     0x4c10
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                     0x4d10
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                     0x4e10
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                     0x4f10
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                     0x5410
++#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0                                     0x5610
++#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0                                     0x5710
++#define mmAFMT_INTERRUPT_STATUS                                                 0x4a11
++#define mmDIG0_AFMT_INTERRUPT_STATUS                                            0x4a11
++#define mmDIG1_AFMT_INTERRUPT_STATUS                                            0x4b11
++#define mmDIG2_AFMT_INTERRUPT_STATUS                                            0x4c11
++#define mmDIG3_AFMT_INTERRUPT_STATUS                                            0x4d11
++#define mmDIG4_AFMT_INTERRUPT_STATUS                                            0x4e11
++#define mmDIG5_AFMT_INTERRUPT_STATUS                                            0x4f11
++#define mmDIG6_AFMT_INTERRUPT_STATUS                                            0x5411
++#define mmDIG7_AFMT_INTERRUPT_STATUS                                            0x5611
++#define mmDIG8_AFMT_INTERRUPT_STATUS                                            0x5711
++#define mmHDMI_GC                                                               0x4a13
++#define mmDIG0_HDMI_GC                                                          0x4a13
++#define mmDIG1_HDMI_GC                                                          0x4b13
++#define mmDIG2_HDMI_GC                                                          0x4c13
++#define mmDIG3_HDMI_GC                                                          0x4d13
++#define mmDIG4_HDMI_GC                                                          0x4e13
++#define mmDIG5_HDMI_GC                                                          0x4f13
++#define mmDIG6_HDMI_GC                                                          0x5413
++#define mmDIG7_HDMI_GC                                                          0x5613
++#define mmDIG8_HDMI_GC                                                          0x5713
++#define mmAFMT_AUDIO_PACKET_CONTROL2                                            0x4a14
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                       0x4a14
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                       0x4b14
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                       0x4c14
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                       0x4d14
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                       0x4e14
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                       0x4f14
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                       0x5414
++#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2                                       0x5614
++#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2                                       0x5714
++#define mmAFMT_ISRC1_0                                                          0x4a15
++#define mmDIG0_AFMT_ISRC1_0                                                     0x4a15
++#define mmDIG1_AFMT_ISRC1_0                                                     0x4b15
++#define mmDIG2_AFMT_ISRC1_0                                                     0x4c15
++#define mmDIG3_AFMT_ISRC1_0                                                     0x4d15
++#define mmDIG4_AFMT_ISRC1_0                                                     0x4e15
++#define mmDIG5_AFMT_ISRC1_0                                                     0x4f15
++#define mmDIG6_AFMT_ISRC1_0                                                     0x5415
++#define mmDIG7_AFMT_ISRC1_0                                                     0x5615
++#define mmDIG8_AFMT_ISRC1_0                                                     0x5715
++#define mmAFMT_ISRC1_1                                                          0x4a16
++#define mmDIG0_AFMT_ISRC1_1                                                     0x4a16
++#define mmDIG1_AFMT_ISRC1_1                                                     0x4b16
++#define mmDIG2_AFMT_ISRC1_1                                                     0x4c16
++#define mmDIG3_AFMT_ISRC1_1                                                     0x4d16
++#define mmDIG4_AFMT_ISRC1_1                                                     0x4e16
++#define mmDIG5_AFMT_ISRC1_1                                                     0x4f16
++#define mmDIG6_AFMT_ISRC1_1                                                     0x5416
++#define mmDIG7_AFMT_ISRC1_1                                                     0x5616
++#define mmDIG8_AFMT_ISRC1_1                                                     0x5716
++#define mmAFMT_ISRC1_2                                                          0x4a17
++#define mmDIG0_AFMT_ISRC1_2                                                     0x4a17
++#define mmDIG1_AFMT_ISRC1_2                                                     0x4b17
++#define mmDIG2_AFMT_ISRC1_2                                                     0x4c17
++#define mmDIG3_AFMT_ISRC1_2                                                     0x4d17
++#define mmDIG4_AFMT_ISRC1_2                                                     0x4e17
++#define mmDIG5_AFMT_ISRC1_2                                                     0x4f17
++#define mmDIG6_AFMT_ISRC1_2                                                     0x5417
++#define mmDIG7_AFMT_ISRC1_2                                                     0x5617
++#define mmDIG8_AFMT_ISRC1_2                                                     0x5717
++#define mmAFMT_ISRC1_3                                                          0x4a18
++#define mmDIG0_AFMT_ISRC1_3                                                     0x4a18
++#define mmDIG1_AFMT_ISRC1_3                                                     0x4b18
++#define mmDIG2_AFMT_ISRC1_3                                                     0x4c18
++#define mmDIG3_AFMT_ISRC1_3                                                     0x4d18
++#define mmDIG4_AFMT_ISRC1_3                                                     0x4e18
++#define mmDIG5_AFMT_ISRC1_3                                                     0x4f18
++#define mmDIG6_AFMT_ISRC1_3                                                     0x5418
++#define mmDIG7_AFMT_ISRC1_3                                                     0x5618
++#define mmDIG8_AFMT_ISRC1_3                                                     0x5718
++#define mmAFMT_ISRC1_4                                                          0x4a19
++#define mmDIG0_AFMT_ISRC1_4                                                     0x4a19
++#define mmDIG1_AFMT_ISRC1_4                                                     0x4b19
++#define mmDIG2_AFMT_ISRC1_4                                                     0x4c19
++#define mmDIG3_AFMT_ISRC1_4                                                     0x4d19
++#define mmDIG4_AFMT_ISRC1_4                                                     0x4e19
++#define mmDIG5_AFMT_ISRC1_4                                                     0x4f19
++#define mmDIG6_AFMT_ISRC1_4                                                     0x5419
++#define mmDIG7_AFMT_ISRC1_4                                                     0x5619
++#define mmDIG8_AFMT_ISRC1_4                                                     0x5719
++#define mmAFMT_ISRC2_0                                                          0x4a1a
++#define mmDIG0_AFMT_ISRC2_0                                                     0x4a1a
++#define mmDIG1_AFMT_ISRC2_0                                                     0x4b1a
++#define mmDIG2_AFMT_ISRC2_0                                                     0x4c1a
++#define mmDIG3_AFMT_ISRC2_0                                                     0x4d1a
++#define mmDIG4_AFMT_ISRC2_0                                                     0x4e1a
++#define mmDIG5_AFMT_ISRC2_0                                                     0x4f1a
++#define mmDIG6_AFMT_ISRC2_0                                                     0x541a
++#define mmDIG7_AFMT_ISRC2_0                                                     0x561a
++#define mmDIG8_AFMT_ISRC2_0                                                     0x571a
++#define mmAFMT_ISRC2_1                                                          0x4a1b
++#define mmDIG0_AFMT_ISRC2_1                                                     0x4a1b
++#define mmDIG1_AFMT_ISRC2_1                                                     0x4b1b
++#define mmDIG2_AFMT_ISRC2_1                                                     0x4c1b
++#define mmDIG3_AFMT_ISRC2_1                                                     0x4d1b
++#define mmDIG4_AFMT_ISRC2_1                                                     0x4e1b
++#define mmDIG5_AFMT_ISRC2_1                                                     0x4f1b
++#define mmDIG6_AFMT_ISRC2_1                                                     0x541b
++#define mmDIG7_AFMT_ISRC2_1                                                     0x561b
++#define mmDIG8_AFMT_ISRC2_1                                                     0x571b
++#define mmAFMT_ISRC2_2                                                          0x4a1c
++#define mmDIG0_AFMT_ISRC2_2                                                     0x4a1c
++#define mmDIG1_AFMT_ISRC2_2                                                     0x4b1c
++#define mmDIG2_AFMT_ISRC2_2                                                     0x4c1c
++#define mmDIG3_AFMT_ISRC2_2                                                     0x4d1c
++#define mmDIG4_AFMT_ISRC2_2                                                     0x4e1c
++#define mmDIG5_AFMT_ISRC2_2                                                     0x4f1c
++#define mmDIG6_AFMT_ISRC2_2                                                     0x541c
++#define mmDIG7_AFMT_ISRC2_2                                                     0x561c
++#define mmDIG8_AFMT_ISRC2_2                                                     0x571c
++#define mmAFMT_ISRC2_3                                                          0x4a1d
++#define mmDIG0_AFMT_ISRC2_3                                                     0x4a1d
++#define mmDIG1_AFMT_ISRC2_3                                                     0x4b1d
++#define mmDIG2_AFMT_ISRC2_3                                                     0x4c1d
++#define mmDIG3_AFMT_ISRC2_3                                                     0x4d1d
++#define mmDIG4_AFMT_ISRC2_3                                                     0x4e1d
++#define mmDIG5_AFMT_ISRC2_3                                                     0x4f1d
++#define mmDIG6_AFMT_ISRC2_3                                                     0x541d
++#define mmDIG7_AFMT_ISRC2_3                                                     0x561d
++#define mmDIG8_AFMT_ISRC2_3                                                     0x571d
++#define mmAFMT_AVI_INFO0                                                        0x4a1e
++#define mmDIG0_AFMT_AVI_INFO0                                                   0x4a1e
++#define mmDIG1_AFMT_AVI_INFO0                                                   0x4b1e
++#define mmDIG2_AFMT_AVI_INFO0                                                   0x4c1e
++#define mmDIG3_AFMT_AVI_INFO0                                                   0x4d1e
++#define mmDIG4_AFMT_AVI_INFO0                                                   0x4e1e
++#define mmDIG5_AFMT_AVI_INFO0                                                   0x4f1e
++#define mmDIG6_AFMT_AVI_INFO0                                                   0x541e
++#define mmDIG7_AFMT_AVI_INFO0                                                   0x561e
++#define mmDIG8_AFMT_AVI_INFO0                                                   0x571e
++#define mmAFMT_AVI_INFO1                                                        0x4a1f
++#define mmDIG0_AFMT_AVI_INFO1                                                   0x4a1f
++#define mmDIG1_AFMT_AVI_INFO1                                                   0x4b1f
++#define mmDIG2_AFMT_AVI_INFO1                                                   0x4c1f
++#define mmDIG3_AFMT_AVI_INFO1                                                   0x4d1f
++#define mmDIG4_AFMT_AVI_INFO1                                                   0x4e1f
++#define mmDIG5_AFMT_AVI_INFO1                                                   0x4f1f
++#define mmDIG6_AFMT_AVI_INFO1                                                   0x541f
++#define mmDIG7_AFMT_AVI_INFO1                                                   0x561f
++#define mmDIG8_AFMT_AVI_INFO1                                                   0x571f
++#define mmAFMT_AVI_INFO2                                                        0x4a20
++#define mmDIG0_AFMT_AVI_INFO2                                                   0x4a20
++#define mmDIG1_AFMT_AVI_INFO2                                                   0x4b20
++#define mmDIG2_AFMT_AVI_INFO2                                                   0x4c20
++#define mmDIG3_AFMT_AVI_INFO2                                                   0x4d20
++#define mmDIG4_AFMT_AVI_INFO2                                                   0x4e20
++#define mmDIG5_AFMT_AVI_INFO2                                                   0x4f20
++#define mmDIG6_AFMT_AVI_INFO2                                                   0x5420
++#define mmDIG7_AFMT_AVI_INFO2                                                   0x5620
++#define mmDIG8_AFMT_AVI_INFO2                                                   0x5720
++#define mmAFMT_AVI_INFO3                                                        0x4a21
++#define mmDIG0_AFMT_AVI_INFO3                                                   0x4a21
++#define mmDIG1_AFMT_AVI_INFO3                                                   0x4b21
++#define mmDIG2_AFMT_AVI_INFO3                                                   0x4c21
++#define mmDIG3_AFMT_AVI_INFO3                                                   0x4d21
++#define mmDIG4_AFMT_AVI_INFO3                                                   0x4e21
++#define mmDIG5_AFMT_AVI_INFO3                                                   0x4f21
++#define mmDIG6_AFMT_AVI_INFO3                                                   0x5421
++#define mmDIG7_AFMT_AVI_INFO3                                                   0x5621
++#define mmDIG8_AFMT_AVI_INFO3                                                   0x5721
++#define mmAFMT_MPEG_INFO0                                                       0x4a22
++#define mmDIG0_AFMT_MPEG_INFO0                                                  0x4a22
++#define mmDIG1_AFMT_MPEG_INFO0                                                  0x4b22
++#define mmDIG2_AFMT_MPEG_INFO0                                                  0x4c22
++#define mmDIG3_AFMT_MPEG_INFO0                                                  0x4d22
++#define mmDIG4_AFMT_MPEG_INFO0                                                  0x4e22
++#define mmDIG5_AFMT_MPEG_INFO0                                                  0x4f22
++#define mmDIG6_AFMT_MPEG_INFO0                                                  0x5422
++#define mmDIG7_AFMT_MPEG_INFO0                                                  0x5622
++#define mmDIG8_AFMT_MPEG_INFO0                                                  0x5722
++#define mmAFMT_MPEG_INFO1                                                       0x4a23
++#define mmDIG0_AFMT_MPEG_INFO1                                                  0x4a23
++#define mmDIG1_AFMT_MPEG_INFO1                                                  0x4b23
++#define mmDIG2_AFMT_MPEG_INFO1                                                  0x4c23
++#define mmDIG3_AFMT_MPEG_INFO1                                                  0x4d23
++#define mmDIG4_AFMT_MPEG_INFO1                                                  0x4e23
++#define mmDIG5_AFMT_MPEG_INFO1                                                  0x4f23
++#define mmDIG6_AFMT_MPEG_INFO1                                                  0x5423
++#define mmDIG7_AFMT_MPEG_INFO1                                                  0x5623
++#define mmDIG8_AFMT_MPEG_INFO1                                                  0x5723
++#define mmAFMT_GENERIC_HDR                                                      0x4a24
++#define mmDIG0_AFMT_GENERIC_HDR                                                 0x4a24
++#define mmDIG1_AFMT_GENERIC_HDR                                                 0x4b24
++#define mmDIG2_AFMT_GENERIC_HDR                                                 0x4c24
++#define mmDIG3_AFMT_GENERIC_HDR                                                 0x4d24
++#define mmDIG4_AFMT_GENERIC_HDR                                                 0x4e24
++#define mmDIG5_AFMT_GENERIC_HDR                                                 0x4f24
++#define mmDIG6_AFMT_GENERIC_HDR                                                 0x5424
++#define mmDIG7_AFMT_GENERIC_HDR                                                 0x5624
++#define mmDIG8_AFMT_GENERIC_HDR                                                 0x5724
++#define mmAFMT_GENERIC_0                                                        0x4a25
++#define mmDIG0_AFMT_GENERIC_0                                                   0x4a25
++#define mmDIG1_AFMT_GENERIC_0                                                   0x4b25
++#define mmDIG2_AFMT_GENERIC_0                                                   0x4c25
++#define mmDIG3_AFMT_GENERIC_0                                                   0x4d25
++#define mmDIG4_AFMT_GENERIC_0                                                   0x4e25
++#define mmDIG5_AFMT_GENERIC_0                                                   0x4f25
++#define mmDIG6_AFMT_GENERIC_0                                                   0x5425
++#define mmDIG7_AFMT_GENERIC_0                                                   0x5625
++#define mmDIG8_AFMT_GENERIC_0                                                   0x5725
++#define mmAFMT_GENERIC_1                                                        0x4a26
++#define mmDIG0_AFMT_GENERIC_1                                                   0x4a26
++#define mmDIG1_AFMT_GENERIC_1                                                   0x4b26
++#define mmDIG2_AFMT_GENERIC_1                                                   0x4c26
++#define mmDIG3_AFMT_GENERIC_1                                                   0x4d26
++#define mmDIG4_AFMT_GENERIC_1                                                   0x4e26
++#define mmDIG5_AFMT_GENERIC_1                                                   0x4f26
++#define mmDIG6_AFMT_GENERIC_1                                                   0x5426
++#define mmDIG7_AFMT_GENERIC_1                                                   0x5626
++#define mmDIG8_AFMT_GENERIC_1                                                   0x5726
++#define mmAFMT_GENERIC_2                                                        0x4a27
++#define mmDIG0_AFMT_GENERIC_2                                                   0x4a27
++#define mmDIG1_AFMT_GENERIC_2                                                   0x4b27
++#define mmDIG2_AFMT_GENERIC_2                                                   0x4c27
++#define mmDIG3_AFMT_GENERIC_2                                                   0x4d27
++#define mmDIG4_AFMT_GENERIC_2                                                   0x4e27
++#define mmDIG5_AFMT_GENERIC_2                                                   0x4f27
++#define mmDIG6_AFMT_GENERIC_2                                                   0x5427
++#define mmDIG7_AFMT_GENERIC_2                                                   0x5627
++#define mmDIG8_AFMT_GENERIC_2                                                   0x5727
++#define mmAFMT_GENERIC_3                                                        0x4a28
++#define mmDIG0_AFMT_GENERIC_3                                                   0x4a28
++#define mmDIG1_AFMT_GENERIC_3                                                   0x4b28
++#define mmDIG2_AFMT_GENERIC_3                                                   0x4c28
++#define mmDIG3_AFMT_GENERIC_3                                                   0x4d28
++#define mmDIG4_AFMT_GENERIC_3                                                   0x4e28
++#define mmDIG5_AFMT_GENERIC_3                                                   0x4f28
++#define mmDIG6_AFMT_GENERIC_3                                                   0x5428
++#define mmDIG7_AFMT_GENERIC_3                                                   0x5628
++#define mmDIG8_AFMT_GENERIC_3                                                   0x5728
++#define mmAFMT_GENERIC_4                                                        0x4a29
++#define mmDIG0_AFMT_GENERIC_4                                                   0x4a29
++#define mmDIG1_AFMT_GENERIC_4                                                   0x4b29
++#define mmDIG2_AFMT_GENERIC_4                                                   0x4c29
++#define mmDIG3_AFMT_GENERIC_4                                                   0x4d29
++#define mmDIG4_AFMT_GENERIC_4                                                   0x4e29
++#define mmDIG5_AFMT_GENERIC_4                                                   0x4f29
++#define mmDIG6_AFMT_GENERIC_4                                                   0x5429
++#define mmDIG7_AFMT_GENERIC_4                                                   0x5629
++#define mmDIG8_AFMT_GENERIC_4                                                   0x5729
++#define mmAFMT_GENERIC_5                                                        0x4a2a
++#define mmDIG0_AFMT_GENERIC_5                                                   0x4a2a
++#define mmDIG1_AFMT_GENERIC_5                                                   0x4b2a
++#define mmDIG2_AFMT_GENERIC_5                                                   0x4c2a
++#define mmDIG3_AFMT_GENERIC_5                                                   0x4d2a
++#define mmDIG4_AFMT_GENERIC_5                                                   0x4e2a
++#define mmDIG5_AFMT_GENERIC_5                                                   0x4f2a
++#define mmDIG6_AFMT_GENERIC_5                                                   0x542a
++#define mmDIG7_AFMT_GENERIC_5                                                   0x562a
++#define mmDIG8_AFMT_GENERIC_5                                                   0x572a
++#define mmAFMT_GENERIC_6                                                        0x4a2b
++#define mmDIG0_AFMT_GENERIC_6                                                   0x4a2b
++#define mmDIG1_AFMT_GENERIC_6                                                   0x4b2b
++#define mmDIG2_AFMT_GENERIC_6                                                   0x4c2b
++#define mmDIG3_AFMT_GENERIC_6                                                   0x4d2b
++#define mmDIG4_AFMT_GENERIC_6                                                   0x4e2b
++#define mmDIG5_AFMT_GENERIC_6                                                   0x4f2b
++#define mmDIG6_AFMT_GENERIC_6                                                   0x542b
++#define mmDIG7_AFMT_GENERIC_6                                                   0x562b
++#define mmDIG8_AFMT_GENERIC_6                                                   0x572b
++#define mmAFMT_GENERIC_7                                                        0x4a2c
++#define mmDIG0_AFMT_GENERIC_7                                                   0x4a2c
++#define mmDIG1_AFMT_GENERIC_7                                                   0x4b2c
++#define mmDIG2_AFMT_GENERIC_7                                                   0x4c2c
++#define mmDIG3_AFMT_GENERIC_7                                                   0x4d2c
++#define mmDIG4_AFMT_GENERIC_7                                                   0x4e2c
++#define mmDIG5_AFMT_GENERIC_7                                                   0x4f2c
++#define mmDIG6_AFMT_GENERIC_7                                                   0x542c
++#define mmDIG7_AFMT_GENERIC_7                                                   0x562c
++#define mmDIG8_AFMT_GENERIC_7                                                   0x572c
++#define mmHDMI_GENERIC_PACKET_CONTROL1                                          0x4a2d
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                     0x4a2d
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                     0x4b2d
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                     0x4c2d
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                     0x4d2d
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                     0x4e2d
++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                     0x4f2d
++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                     0x542d
++#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1                                     0x562d
++#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1                                     0x572d
++#define mmHDMI_ACR_32_0                                                         0x4a2e
++#define mmDIG0_HDMI_ACR_32_0                                                    0x4a2e
++#define mmDIG1_HDMI_ACR_32_0                                                    0x4b2e
++#define mmDIG2_HDMI_ACR_32_0                                                    0x4c2e
++#define mmDIG3_HDMI_ACR_32_0                                                    0x4d2e
++#define mmDIG4_HDMI_ACR_32_0                                                    0x4e2e
++#define mmDIG5_HDMI_ACR_32_0                                                    0x4f2e
++#define mmDIG6_HDMI_ACR_32_0                                                    0x542e
++#define mmDIG7_HDMI_ACR_32_0                                                    0x562e
++#define mmDIG8_HDMI_ACR_32_0                                                    0x572e
++#define mmHDMI_ACR_32_1                                                         0x4a2f
++#define mmDIG0_HDMI_ACR_32_1                                                    0x4a2f
++#define mmDIG1_HDMI_ACR_32_1                                                    0x4b2f
++#define mmDIG2_HDMI_ACR_32_1                                                    0x4c2f
++#define mmDIG3_HDMI_ACR_32_1                                                    0x4d2f
++#define mmDIG4_HDMI_ACR_32_1                                                    0x4e2f
++#define mmDIG5_HDMI_ACR_32_1                                                    0x4f2f
++#define mmDIG6_HDMI_ACR_32_1                                                    0x542f
++#define mmDIG7_HDMI_ACR_32_1                                                    0x562f
++#define mmDIG8_HDMI_ACR_32_1                                                    0x572f
++#define mmHDMI_ACR_44_0                                                         0x4a30
++#define mmDIG0_HDMI_ACR_44_0                                                    0x4a30
++#define mmDIG1_HDMI_ACR_44_0                                                    0x4b30
++#define mmDIG2_HDMI_ACR_44_0                                                    0x4c30
++#define mmDIG3_HDMI_ACR_44_0                                                    0x4d30
++#define mmDIG4_HDMI_ACR_44_0                                                    0x4e30
++#define mmDIG5_HDMI_ACR_44_0                                                    0x4f30
++#define mmDIG6_HDMI_ACR_44_0                                                    0x5430
++#define mmDIG7_HDMI_ACR_44_0                                                    0x5630
++#define mmDIG8_HDMI_ACR_44_0                                                    0x5730
++#define mmHDMI_ACR_44_1                                                         0x4a31
++#define mmDIG0_HDMI_ACR_44_1                                                    0x4a31
++#define mmDIG1_HDMI_ACR_44_1                                                    0x4b31
++#define mmDIG2_HDMI_ACR_44_1                                                    0x4c31
++#define mmDIG3_HDMI_ACR_44_1                                                    0x4d31
++#define mmDIG4_HDMI_ACR_44_1                                                    0x4e31
++#define mmDIG5_HDMI_ACR_44_1                                                    0x4f31
++#define mmDIG6_HDMI_ACR_44_1                                                    0x5431
++#define mmDIG7_HDMI_ACR_44_1                                                    0x5631
++#define mmDIG8_HDMI_ACR_44_1                                                    0x5731
++#define mmHDMI_ACR_48_0                                                         0x4a32
++#define mmDIG0_HDMI_ACR_48_0                                                    0x4a32
++#define mmDIG1_HDMI_ACR_48_0                                                    0x4b32
++#define mmDIG2_HDMI_ACR_48_0                                                    0x4c32
++#define mmDIG3_HDMI_ACR_48_0                                                    0x4d32
++#define mmDIG4_HDMI_ACR_48_0                                                    0x4e32
++#define mmDIG5_HDMI_ACR_48_0                                                    0x4f32
++#define mmDIG6_HDMI_ACR_48_0                                                    0x5432
++#define mmDIG7_HDMI_ACR_48_0                                                    0x5632
++#define mmDIG8_HDMI_ACR_48_0                                                    0x5732
++#define mmHDMI_ACR_48_1                                                         0x4a33
++#define mmDIG0_HDMI_ACR_48_1                                                    0x4a33
++#define mmDIG1_HDMI_ACR_48_1                                                    0x4b33
++#define mmDIG2_HDMI_ACR_48_1                                                    0x4c33
++#define mmDIG3_HDMI_ACR_48_1                                                    0x4d33
++#define mmDIG4_HDMI_ACR_48_1                                                    0x4e33
++#define mmDIG5_HDMI_ACR_48_1                                                    0x4f33
++#define mmDIG6_HDMI_ACR_48_1                                                    0x5433
++#define mmDIG7_HDMI_ACR_48_1                                                    0x5633
++#define mmDIG8_HDMI_ACR_48_1                                                    0x5733
++#define mmHDMI_ACR_STATUS_0                                                     0x4a34
++#define mmDIG0_HDMI_ACR_STATUS_0                                                0x4a34
++#define mmDIG1_HDMI_ACR_STATUS_0                                                0x4b34
++#define mmDIG2_HDMI_ACR_STATUS_0                                                0x4c34
++#define mmDIG3_HDMI_ACR_STATUS_0                                                0x4d34
++#define mmDIG4_HDMI_ACR_STATUS_0                                                0x4e34
++#define mmDIG5_HDMI_ACR_STATUS_0                                                0x4f34
++#define mmDIG6_HDMI_ACR_STATUS_0                                                0x5434
++#define mmDIG7_HDMI_ACR_STATUS_0                                                0x5634
++#define mmDIG8_HDMI_ACR_STATUS_0                                                0x5734
++#define mmHDMI_ACR_STATUS_1                                                     0x4a35
++#define mmDIG0_HDMI_ACR_STATUS_1                                                0x4a35
++#define mmDIG1_HDMI_ACR_STATUS_1                                                0x4b35
++#define mmDIG2_HDMI_ACR_STATUS_1                                                0x4c35
++#define mmDIG3_HDMI_ACR_STATUS_1                                                0x4d35
++#define mmDIG4_HDMI_ACR_STATUS_1                                                0x4e35
++#define mmDIG5_HDMI_ACR_STATUS_1                                                0x4f35
++#define mmDIG6_HDMI_ACR_STATUS_1                                                0x5435
++#define mmDIG7_HDMI_ACR_STATUS_1                                                0x5635
++#define mmDIG8_HDMI_ACR_STATUS_1                                                0x5735
++#define mmAFMT_AUDIO_INFO0                                                      0x4a36
++#define mmDIG0_AFMT_AUDIO_INFO0                                                 0x4a36
++#define mmDIG1_AFMT_AUDIO_INFO0                                                 0x4b36
++#define mmDIG2_AFMT_AUDIO_INFO0                                                 0x4c36
++#define mmDIG3_AFMT_AUDIO_INFO0                                                 0x4d36
++#define mmDIG4_AFMT_AUDIO_INFO0                                                 0x4e36
++#define mmDIG5_AFMT_AUDIO_INFO0                                                 0x4f36
++#define mmDIG6_AFMT_AUDIO_INFO0                                                 0x5436
++#define mmDIG7_AFMT_AUDIO_INFO0                                                 0x5636
++#define mmDIG8_AFMT_AUDIO_INFO0                                                 0x5736
++#define mmAFMT_AUDIO_INFO1                                                      0x4a37
++#define mmDIG0_AFMT_AUDIO_INFO1                                                 0x4a37
++#define mmDIG1_AFMT_AUDIO_INFO1                                                 0x4b37
++#define mmDIG2_AFMT_AUDIO_INFO1                                                 0x4c37
++#define mmDIG3_AFMT_AUDIO_INFO1                                                 0x4d37
++#define mmDIG4_AFMT_AUDIO_INFO1                                                 0x4e37
++#define mmDIG5_AFMT_AUDIO_INFO1                                                 0x4f37
++#define mmDIG6_AFMT_AUDIO_INFO1                                                 0x5437
++#define mmDIG7_AFMT_AUDIO_INFO1                                                 0x5637
++#define mmDIG8_AFMT_AUDIO_INFO1                                                 0x5737
++#define mmAFMT_60958_0                                                          0x4a38
++#define mmDIG0_AFMT_60958_0                                                     0x4a38
++#define mmDIG1_AFMT_60958_0                                                     0x4b38
++#define mmDIG2_AFMT_60958_0                                                     0x4c38
++#define mmDIG3_AFMT_60958_0                                                     0x4d38
++#define mmDIG4_AFMT_60958_0                                                     0x4e38
++#define mmDIG5_AFMT_60958_0                                                     0x4f38
++#define mmDIG6_AFMT_60958_0                                                     0x5438
++#define mmDIG7_AFMT_60958_0                                                     0x5638
++#define mmDIG8_AFMT_60958_0                                                     0x5738
++#define mmAFMT_60958_1                                                          0x4a39
++#define mmDIG0_AFMT_60958_1                                                     0x4a39
++#define mmDIG1_AFMT_60958_1                                                     0x4b39
++#define mmDIG2_AFMT_60958_1                                                     0x4c39
++#define mmDIG3_AFMT_60958_1                                                     0x4d39
++#define mmDIG4_AFMT_60958_1                                                     0x4e39
++#define mmDIG5_AFMT_60958_1                                                     0x4f39
++#define mmDIG6_AFMT_60958_1                                                     0x5439
++#define mmDIG7_AFMT_60958_1                                                     0x5639
++#define mmDIG8_AFMT_60958_1                                                     0x5739
++#define mmAFMT_AUDIO_CRC_CONTROL                                                0x4a3a
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                           0x4a3a
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                           0x4b3a
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                           0x4c3a
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                           0x4d3a
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                           0x4e3a
++#define mmDIG5_AFMT_AUDIO_CRC_CONTROL                                           0x4f3a
++#define mmDIG6_AFMT_AUDIO_CRC_CONTROL                                           0x543a
++#define mmDIG7_AFMT_AUDIO_CRC_CONTROL                                           0x563a
++#define mmDIG8_AFMT_AUDIO_CRC_CONTROL                                           0x573a
++#define mmAFMT_RAMP_CONTROL0                                                    0x4a3b
++#define mmDIG0_AFMT_RAMP_CONTROL0                                               0x4a3b
++#define mmDIG1_AFMT_RAMP_CONTROL0                                               0x4b3b
++#define mmDIG2_AFMT_RAMP_CONTROL0                                               0x4c3b
++#define mmDIG3_AFMT_RAMP_CONTROL0                                               0x4d3b
++#define mmDIG4_AFMT_RAMP_CONTROL0                                               0x4e3b
++#define mmDIG5_AFMT_RAMP_CONTROL0                                               0x4f3b
++#define mmDIG6_AFMT_RAMP_CONTROL0                                               0x543b
++#define mmDIG7_AFMT_RAMP_CONTROL0                                               0x563b
++#define mmDIG8_AFMT_RAMP_CONTROL0                                               0x573b
++#define mmAFMT_RAMP_CONTROL1                                                    0x4a3c
++#define mmDIG0_AFMT_RAMP_CONTROL1                                               0x4a3c
++#define mmDIG1_AFMT_RAMP_CONTROL1                                               0x4b3c
++#define mmDIG2_AFMT_RAMP_CONTROL1                                               0x4c3c
++#define mmDIG3_AFMT_RAMP_CONTROL1                                               0x4d3c
++#define mmDIG4_AFMT_RAMP_CONTROL1                                               0x4e3c
++#define mmDIG5_AFMT_RAMP_CONTROL1                                               0x4f3c
++#define mmDIG6_AFMT_RAMP_CONTROL1                                               0x543c
++#define mmDIG7_AFMT_RAMP_CONTROL1                                               0x563c
++#define mmDIG8_AFMT_RAMP_CONTROL1                                               0x573c
++#define mmAFMT_RAMP_CONTROL2                                                    0x4a3d
++#define mmDIG0_AFMT_RAMP_CONTROL2                                               0x4a3d
++#define mmDIG1_AFMT_RAMP_CONTROL2                                               0x4b3d
++#define mmDIG2_AFMT_RAMP_CONTROL2                                               0x4c3d
++#define mmDIG3_AFMT_RAMP_CONTROL2                                               0x4d3d
++#define mmDIG4_AFMT_RAMP_CONTROL2                                               0x4e3d
++#define mmDIG5_AFMT_RAMP_CONTROL2                                               0x4f3d
++#define mmDIG6_AFMT_RAMP_CONTROL2                                               0x543d
++#define mmDIG7_AFMT_RAMP_CONTROL2                                               0x563d
++#define mmDIG8_AFMT_RAMP_CONTROL2                                               0x573d
++#define mmAFMT_RAMP_CONTROL3                                                    0x4a3e
++#define mmDIG0_AFMT_RAMP_CONTROL3                                               0x4a3e
++#define mmDIG1_AFMT_RAMP_CONTROL3                                               0x4b3e
++#define mmDIG2_AFMT_RAMP_CONTROL3                                               0x4c3e
++#define mmDIG3_AFMT_RAMP_CONTROL3                                               0x4d3e
++#define mmDIG4_AFMT_RAMP_CONTROL3                                               0x4e3e
++#define mmDIG5_AFMT_RAMP_CONTROL3                                               0x4f3e
++#define mmDIG6_AFMT_RAMP_CONTROL3                                               0x543e
++#define mmDIG7_AFMT_RAMP_CONTROL3                                               0x563e
++#define mmDIG8_AFMT_RAMP_CONTROL3                                               0x573e
++#define mmAFMT_60958_2                                                          0x4a3f
++#define mmDIG0_AFMT_60958_2                                                     0x4a3f
++#define mmDIG1_AFMT_60958_2                                                     0x4b3f
++#define mmDIG2_AFMT_60958_2                                                     0x4c3f
++#define mmDIG3_AFMT_60958_2                                                     0x4d3f
++#define mmDIG4_AFMT_60958_2                                                     0x4e3f
++#define mmDIG5_AFMT_60958_2                                                     0x4f3f
++#define mmDIG6_AFMT_60958_2                                                     0x543f
++#define mmDIG7_AFMT_60958_2                                                     0x563f
++#define mmDIG8_AFMT_60958_2                                                     0x573f
++#define mmAFMT_AUDIO_CRC_RESULT                                                 0x4a40
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT                                            0x4a40
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT                                            0x4b40
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT                                            0x4c40
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT                                            0x4d40
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT                                            0x4e40
++#define mmDIG5_AFMT_AUDIO_CRC_RESULT                                            0x4f40
++#define mmDIG6_AFMT_AUDIO_CRC_RESULT                                            0x5440
++#define mmDIG7_AFMT_AUDIO_CRC_RESULT                                            0x5640
++#define mmDIG8_AFMT_AUDIO_CRC_RESULT                                            0x5740
++#define mmAFMT_STATUS                                                           0x4a41
++#define mmDIG0_AFMT_STATUS                                                      0x4a41
++#define mmDIG1_AFMT_STATUS                                                      0x4b41
++#define mmDIG2_AFMT_STATUS                                                      0x4c41
++#define mmDIG3_AFMT_STATUS                                                      0x4d41
++#define mmDIG4_AFMT_STATUS                                                      0x4e41
++#define mmDIG5_AFMT_STATUS                                                      0x4f41
++#define mmDIG6_AFMT_STATUS                                                      0x5441
++#define mmDIG7_AFMT_STATUS                                                      0x5641
++#define mmDIG8_AFMT_STATUS                                                      0x5741
++#define mmAFMT_AUDIO_PACKET_CONTROL                                             0x4a42
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                        0x4a42
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                        0x4b42
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                        0x4c42
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                        0x4d42
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                        0x4e42
++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                        0x4f42
++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                        0x5442
++#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL                                        0x5642
++#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL                                        0x5742
++#define mmAFMT_VBI_PACKET_CONTROL                                               0x4a43
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL                                          0x4a43
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL                                          0x4b43
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL                                          0x4c43
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL                                          0x4d43
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL                                          0x4e43
++#define mmDIG5_AFMT_VBI_PACKET_CONTROL                                          0x4f43
++#define mmDIG6_AFMT_VBI_PACKET_CONTROL                                          0x5443
++#define mmDIG7_AFMT_VBI_PACKET_CONTROL                                          0x5643
++#define mmDIG8_AFMT_VBI_PACKET_CONTROL                                          0x5743
++#define mmAFMT_INFOFRAME_CONTROL0                                               0x4a44
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0                                          0x4a44
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0                                          0x4b44
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0                                          0x4c44
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0                                          0x4d44
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0                                          0x4e44
++#define mmDIG5_AFMT_INFOFRAME_CONTROL0                                          0x4f44
++#define mmDIG6_AFMT_INFOFRAME_CONTROL0                                          0x5444
++#define mmDIG7_AFMT_INFOFRAME_CONTROL0                                          0x5644
++#define mmDIG8_AFMT_INFOFRAME_CONTROL0                                          0x5744
++#define mmAFMT_AUDIO_SRC_CONTROL                                                0x4a45
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                           0x4a45
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                           0x4b45
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                           0x4c45
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                           0x4d45
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                           0x4e45
++#define mmDIG5_AFMT_AUDIO_SRC_CONTROL                                           0x4f45
++#define mmDIG6_AFMT_AUDIO_SRC_CONTROL                                           0x5445
++#define mmDIG7_AFMT_AUDIO_SRC_CONTROL                                           0x5645
++#define mmDIG8_AFMT_AUDIO_SRC_CONTROL                                           0x5745
++#define mmAFMT_AUDIO_DBG_DTO_CNTL                                               0x4a46
++#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4a46
++#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4b46
++#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4c46
++#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4d46
++#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4e46
++#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4f46
++#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5446
++#define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5646
++#define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5746
++#define mmAFMT_CNTL                                                             0x4a7e
++#define mmDIG0_AFMT_CNTL                                                        0x4a7e
++#define mmDIG1_AFMT_CNTL                                                        0x4b7e
++#define mmDIG2_AFMT_CNTL                                                        0x4c7e
++#define mmDIG3_AFMT_CNTL                                                        0x4d7e
++#define mmDIG4_AFMT_CNTL                                                        0x4e7e
++#define mmDIG5_AFMT_CNTL                                                        0x4f7e
++#define mmDIG6_AFMT_CNTL                                                        0x547e
++#define mmDIG7_AFMT_CNTL                                                        0x567e
++#define mmDIG8_AFMT_CNTL                                                        0x577e
++#define mmDIG_BE_CNTL                                                           0x4a47
++#define mmDIG0_DIG_BE_CNTL                                                      0x4a47
++#define mmDIG1_DIG_BE_CNTL                                                      0x4b47
++#define mmDIG2_DIG_BE_CNTL                                                      0x4c47
++#define mmDIG3_DIG_BE_CNTL                                                      0x4d47
++#define mmDIG4_DIG_BE_CNTL                                                      0x4e47
++#define mmDIG5_DIG_BE_CNTL                                                      0x4f47
++#define mmDIG6_DIG_BE_CNTL                                                      0x5447
++#define mmDIG7_DIG_BE_CNTL                                                      0x5647
++#define mmDIG8_DIG_BE_CNTL                                                      0x5747
++#define mmDIG_BE_EN_CNTL                                                        0x4a48
++#define mmDIG0_DIG_BE_EN_CNTL                                                   0x4a48
++#define mmDIG1_DIG_BE_EN_CNTL                                                   0x4b48
++#define mmDIG2_DIG_BE_EN_CNTL                                                   0x4c48
++#define mmDIG3_DIG_BE_EN_CNTL                                                   0x4d48
++#define mmDIG4_DIG_BE_EN_CNTL                                                   0x4e48
++#define mmDIG5_DIG_BE_EN_CNTL                                                   0x4f48
++#define mmDIG6_DIG_BE_EN_CNTL                                                   0x5448
++#define mmDIG7_DIG_BE_EN_CNTL                                                   0x5648
++#define mmDIG8_DIG_BE_EN_CNTL                                                   0x5748
++#define mmTMDS_CNTL                                                             0x4a6b
++#define mmDIG0_TMDS_CNTL                                                        0x4a6b
++#define mmDIG1_TMDS_CNTL                                                        0x4b6b
++#define mmDIG2_TMDS_CNTL                                                        0x4c6b
++#define mmDIG3_TMDS_CNTL                                                        0x4d6b
++#define mmDIG4_TMDS_CNTL                                                        0x4e6b
++#define mmDIG5_TMDS_CNTL                                                        0x4f6b
++#define mmDIG6_TMDS_CNTL                                                        0x546b
++#define mmDIG7_TMDS_CNTL                                                        0x566b
++#define mmDIG8_TMDS_CNTL                                                        0x576b
++#define mmTMDS_CONTROL_CHAR                                                     0x4a6c
++#define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
++#define mmDIG1_TMDS_CONTROL_CHAR                                                0x4b6c
++#define mmDIG2_TMDS_CONTROL_CHAR                                                0x4c6c
++#define mmDIG3_TMDS_CONTROL_CHAR                                                0x4d6c
++#define mmDIG4_TMDS_CONTROL_CHAR                                                0x4e6c
++#define mmDIG5_TMDS_CONTROL_CHAR                                                0x4f6c
++#define mmDIG6_TMDS_CONTROL_CHAR                                                0x546c
++#define mmDIG7_TMDS_CONTROL_CHAR                                                0x566c
++#define mmDIG8_TMDS_CONTROL_CHAR                                                0x576c
++#define mmTMDS_CONTROL0_FEEDBACK                                                0x4a6d
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                           0x4a6d
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                           0x4b6d
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                           0x4c6d
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                           0x4d6d
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK                                           0x4e6d
++#define mmDIG5_TMDS_CONTROL0_FEEDBACK                                           0x4f6d
++#define mmDIG6_TMDS_CONTROL0_FEEDBACK                                           0x546d
++#define mmDIG7_TMDS_CONTROL0_FEEDBACK                                           0x566d
++#define mmDIG8_TMDS_CONTROL0_FEEDBACK                                           0x576d
++#define mmTMDS_STEREOSYNC_CTL_SEL                                               0x4a6e
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                          0x4a6e
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                          0x4b6e
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                          0x4c6e
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                          0x4d6e
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                          0x4e6e
++#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                          0x4f6e
++#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                          0x546e
++#define mmDIG7_TMDS_STEREOSYNC_CTL_SEL                                          0x566e
++#define mmDIG8_TMDS_STEREOSYNC_CTL_SEL                                          0x576e
++#define mmTMDS_SYNC_CHAR_PATTERN_0_1                                            0x4a6f
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4a6f
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4b6f
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4c6f
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4d6f
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4e6f
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4f6f
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x546f
++#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x566f
++#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x576f
++#define mmTMDS_SYNC_CHAR_PATTERN_2_3                                            0x4a70
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4a70
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4b70
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4c70
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4d70
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4e70
++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4f70
++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5470
++#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5670
++#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5770
++#define mmTMDS_DEBUG                                                            0x4a71
++#define mmDIG0_TMDS_DEBUG                                                       0x4a71
++#define mmDIG1_TMDS_DEBUG                                                       0x4b71
++#define mmDIG2_TMDS_DEBUG                                                       0x4c71
++#define mmDIG3_TMDS_DEBUG                                                       0x4d71
++#define mmDIG4_TMDS_DEBUG                                                       0x4e71
++#define mmDIG5_TMDS_DEBUG                                                       0x4f71
++#define mmDIG6_TMDS_DEBUG                                                       0x5471
++#define mmDIG7_TMDS_DEBUG                                                       0x5671
++#define mmDIG8_TMDS_DEBUG                                                       0x5771
++#define mmTMDS_CTL_BITS                                                         0x4a72
++#define mmDIG0_TMDS_CTL_BITS                                                    0x4a72
++#define mmDIG1_TMDS_CTL_BITS                                                    0x4b72
++#define mmDIG2_TMDS_CTL_BITS                                                    0x4c72
++#define mmDIG3_TMDS_CTL_BITS                                                    0x4d72
++#define mmDIG4_TMDS_CTL_BITS                                                    0x4e72
++#define mmDIG5_TMDS_CTL_BITS                                                    0x4f72
++#define mmDIG6_TMDS_CTL_BITS                                                    0x5472
++#define mmDIG7_TMDS_CTL_BITS                                                    0x5672
++#define mmDIG8_TMDS_CTL_BITS                                                    0x5772
++#define mmTMDS_DCBALANCER_CONTROL                                               0x4a73
++#define mmDIG0_TMDS_DCBALANCER_CONTROL                                          0x4a73
++#define mmDIG1_TMDS_DCBALANCER_CONTROL                                          0x4b73
++#define mmDIG2_TMDS_DCBALANCER_CONTROL                                          0x4c73
++#define mmDIG3_TMDS_DCBALANCER_CONTROL                                          0x4d73
++#define mmDIG4_TMDS_DCBALANCER_CONTROL                                          0x4e73
++#define mmDIG5_TMDS_DCBALANCER_CONTROL                                          0x4f73
++#define mmDIG6_TMDS_DCBALANCER_CONTROL                                          0x5473
++#define mmDIG7_TMDS_DCBALANCER_CONTROL                                          0x5673
++#define mmDIG8_TMDS_DCBALANCER_CONTROL                                          0x5773
++#define mmTMDS_CTL0_1_GEN_CNTL                                                  0x4a75
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                             0x4a75
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                             0x4b75
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                             0x4c75
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                             0x4d75
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                             0x4e75
++#define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                             0x4f75
++#define mmDIG6_TMDS_CTL0_1_GEN_CNTL                                             0x5475
++#define mmDIG7_TMDS_CTL0_1_GEN_CNTL                                             0x5675
++#define mmDIG8_TMDS_CTL0_1_GEN_CNTL                                             0x5775
++#define mmTMDS_CTL2_3_GEN_CNTL                                                  0x4a76
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                             0x4a76
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                             0x4b76
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                             0x4c76
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                             0x4d76
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                             0x4e76
++#define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                             0x4f76
++#define mmDIG6_TMDS_CTL2_3_GEN_CNTL                                             0x5476
++#define mmDIG7_TMDS_CTL2_3_GEN_CNTL                                             0x5676
++#define mmDIG8_TMDS_CTL2_3_GEN_CNTL                                             0x5776
++#define mmDIG_VERSION                                                           0x4a78
++#define mmDIG0_DIG_VERSION                                                      0x4a78
++#define mmDIG1_DIG_VERSION                                                      0x4b78
++#define mmDIG2_DIG_VERSION                                                      0x4c78
++#define mmDIG3_DIG_VERSION                                                      0x4d78
++#define mmDIG4_DIG_VERSION                                                      0x4e78
++#define mmDIG5_DIG_VERSION                                                      0x4f78
++#define mmDIG6_DIG_VERSION                                                      0x5478
++#define mmDIG7_DIG_VERSION                                                      0x5678
++#define mmDIG8_DIG_VERSION                                                      0x5778
++#define mmDIG_LANE_ENABLE                                                       0x4a79
++#define mmDIG0_DIG_LANE_ENABLE                                                  0x4a79
++#define mmDIG1_DIG_LANE_ENABLE                                                  0x4b79
++#define mmDIG2_DIG_LANE_ENABLE                                                  0x4c79
++#define mmDIG3_DIG_LANE_ENABLE                                                  0x4d79
++#define mmDIG4_DIG_LANE_ENABLE                                                  0x4e79
++#define mmDIG5_DIG_LANE_ENABLE                                                  0x4f79
++#define mmDIG6_DIG_LANE_ENABLE                                                  0x5479
++#define mmDIG7_DIG_LANE_ENABLE                                                  0x5679
++#define mmDIG8_DIG_LANE_ENABLE                                                  0x5779
++#define mmDIG_TEST_DEBUG_INDEX                                                  0x4a7a
++#define mmDIG0_DIG_TEST_DEBUG_INDEX                                             0x4a7a
++#define mmDIG1_DIG_TEST_DEBUG_INDEX                                             0x4b7a
++#define mmDIG2_DIG_TEST_DEBUG_INDEX                                             0x4c7a
++#define mmDIG3_DIG_TEST_DEBUG_INDEX                                             0x4d7a
++#define mmDIG4_DIG_TEST_DEBUG_INDEX                                             0x4e7a
++#define mmDIG5_DIG_TEST_DEBUG_INDEX                                             0x4f7a
++#define mmDIG6_DIG_TEST_DEBUG_INDEX                                             0x547a
++#define mmDIG7_DIG_TEST_DEBUG_INDEX                                             0x567a
++#define mmDIG8_DIG_TEST_DEBUG_INDEX                                             0x577a
++#define mmDIG_TEST_DEBUG_DATA                                                   0x4a7b
++#define mmDIG0_DIG_TEST_DEBUG_DATA                                              0x4a7b
++#define mmDIG1_DIG_TEST_DEBUG_DATA                                              0x4b7b
++#define mmDIG2_DIG_TEST_DEBUG_DATA                                              0x4c7b
++#define mmDIG3_DIG_TEST_DEBUG_DATA                                              0x4d7b
++#define mmDIG4_DIG_TEST_DEBUG_DATA                                              0x4e7b
++#define mmDIG5_DIG_TEST_DEBUG_DATA                                              0x4f7b
++#define mmDIG6_DIG_TEST_DEBUG_DATA                                              0x547b
++#define mmDIG7_DIG_TEST_DEBUG_DATA                                              0x567b
++#define mmDIG8_DIG_TEST_DEBUG_DATA                                              0x577b
++#define mmDIG_FE_TEST_DEBUG_INDEX                                               0x4a7c
++#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX                                          0x4a7c
++#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX                                          0x4b7c
++#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX                                          0x4c7c
++#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX                                          0x4d7c
++#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX                                          0x4e7c
++#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX                                          0x4f7c
++#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX                                          0x547c
++#define mmDIG7_DIG_FE_TEST_DEBUG_INDEX                                          0x567c
++#define mmDIG8_DIG_FE_TEST_DEBUG_INDEX                                          0x577c
++#define mmDIG_FE_TEST_DEBUG_DATA                                                0x4a7d
++#define mmDIG0_DIG_FE_TEST_DEBUG_DATA                                           0x4a7d
++#define mmDIG1_DIG_FE_TEST_DEBUG_DATA                                           0x4b7d
++#define mmDIG2_DIG_FE_TEST_DEBUG_DATA                                           0x4c7d
++#define mmDIG3_DIG_FE_TEST_DEBUG_DATA                                           0x4d7d
++#define mmDIG4_DIG_FE_TEST_DEBUG_DATA                                           0x4e7d
++#define mmDIG5_DIG_FE_TEST_DEBUG_DATA                                           0x4f7d
++#define mmDIG6_DIG_FE_TEST_DEBUG_DATA                                           0x547d
++#define mmDIG7_DIG_FE_TEST_DEBUG_DATA                                           0x567d
++#define mmDIG8_DIG_FE_TEST_DEBUG_DATA                                           0x577d
++#define mmDMCU_CTRL                                                             0x1600
++#define mmDMCU_STATUS                                                           0x1601
++#define mmDMCU_PC_START_ADDR                                                    0x1602
++#define mmDMCU_FW_START_ADDR                                                    0x1603
++#define mmDMCU_FW_END_ADDR                                                      0x1604
++#define mmDMCU_FW_ISR_START_ADDR                                                0x1605
++#define mmDMCU_FW_CS_HI                                                         0x1606
++#define mmDMCU_FW_CS_LO                                                         0x1607
++#define mmDMCU_RAM_ACCESS_CTRL                                                  0x1608
++#define mmDMCU_ERAM_WR_CTRL                                                     0x1609
++#define mmDMCU_ERAM_WR_DATA                                                     0x160a
++#define mmDMCU_ERAM_RD_CTRL                                                     0x160b
++#define mmDMCU_ERAM_RD_DATA                                                     0x160c
++#define mmDMCU_IRAM_WR_CTRL                                                     0x160d
++#define mmDMCU_IRAM_WR_DATA                                                     0x160e
++#define mmDMCU_IRAM_RD_CTRL                                                     0x160f
++#define mmDMCU_IRAM_RD_DATA                                                     0x1610
++#define mmDMCU_EVENT_TRIGGER                                                    0x1611
++#define mmDMCU_UC_INTERNAL_INT_STATUS                                           0x1612
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                         0x1613
++#define mmDMCU_INTERRUPT_STATUS                                                 0x1614
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                        0x1615
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                          0x1616
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                        0x1631
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                     0x1617
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                   0x1632
++#define mmDC_DMCU_SCRATCH                                                       0x1618
++#define mmDMCU_INT_CNT                                                          0x1619
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                        0x161a
++#define mmDMCU_UC_CLK_GATING_CNTL                                               0x161b
++#define mmMASTER_COMM_DATA_REG1                                                 0x161c
++#define mmMASTER_COMM_DATA_REG2                                                 0x161d
++#define mmMASTER_COMM_DATA_REG3                                                 0x161e
++#define mmMASTER_COMM_CMD_REG                                                   0x161f
++#define mmMASTER_COMM_CNTL_REG                                                  0x1620
++#define mmSLAVE_COMM_DATA_REG1                                                  0x1621
++#define mmSLAVE_COMM_DATA_REG2                                                  0x1622
++#define mmSLAVE_COMM_DATA_REG3                                                  0x1623
++#define mmSLAVE_COMM_CMD_REG                                                    0x1624
++#define mmSLAVE_COMM_CNTL_REG                                                   0x1625
++#define mmDMCU_TEST_DEBUG_INDEX                                                 0x1626
++#define mmDMCU_TEST_DEBUG_DATA                                                  0x1627
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                        0x1644
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                        0x1645
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                        0x1646
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                        0x1647
++#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                        0x1642
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                 0x1674
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                 0x1675
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                 0x1676
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                 0x1677
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                 0x1643
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                            0x1678
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                            0x1679
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                            0x167a
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                            0x167b
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                            0x1673
++#define mmDMCU_DPRX_INTERRUPT_STATUS1                                           0x1634
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                    0x1635
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                               0x1636
++#define mmDP_LINK_CNTL                                                          0x4aa0
++#define mmDP0_DP_LINK_CNTL                                                      0x4aa0
++#define mmDP1_DP_LINK_CNTL                                                      0x4ba0
++#define mmDP2_DP_LINK_CNTL                                                      0x4ca0
++#define mmDP3_DP_LINK_CNTL                                                      0x4da0
++#define mmDP4_DP_LINK_CNTL                                                      0x4ea0
++#define mmDP5_DP_LINK_CNTL                                                      0x4fa0
++#define mmDP6_DP_LINK_CNTL                                                      0x54a0
++#define mmDP7_DP_LINK_CNTL                                                      0x56a0
++#define mmDP8_DP_LINK_CNTL                                                      0x57a0
++#define mmDP_PIXEL_FORMAT                                                       0x4aa1
++#define mmDP0_DP_PIXEL_FORMAT                                                   0x4aa1
++#define mmDP1_DP_PIXEL_FORMAT                                                   0x4ba1
++#define mmDP2_DP_PIXEL_FORMAT                                                   0x4ca1
++#define mmDP3_DP_PIXEL_FORMAT                                                   0x4da1
++#define mmDP4_DP_PIXEL_FORMAT                                                   0x4ea1
++#define mmDP5_DP_PIXEL_FORMAT                                                   0x4fa1
++#define mmDP6_DP_PIXEL_FORMAT                                                   0x54a1
++#define mmDP7_DP_PIXEL_FORMAT                                                   0x56a1
++#define mmDP8_DP_PIXEL_FORMAT                                                   0x57a1
++#define mmDP_MSA_COLORIMETRY                                                    0x4aa2
++#define mmDP0_DP_MSA_COLORIMETRY                                                0x4aa2
++#define mmDP1_DP_MSA_COLORIMETRY                                                0x4ba2
++#define mmDP2_DP_MSA_COLORIMETRY                                                0x4ca2
++#define mmDP3_DP_MSA_COLORIMETRY                                                0x4da2
++#define mmDP4_DP_MSA_COLORIMETRY                                                0x4ea2
++#define mmDP5_DP_MSA_COLORIMETRY                                                0x4fa2
++#define mmDP6_DP_MSA_COLORIMETRY                                                0x54a2
++#define mmDP7_DP_MSA_COLORIMETRY                                                0x56a2
++#define mmDP8_DP_MSA_COLORIMETRY                                                0x57a2
++#define mmDP_CONFIG                                                             0x4aa3
++#define mmDP0_DP_CONFIG                                                         0x4aa3
++#define mmDP1_DP_CONFIG                                                         0x4ba3
++#define mmDP2_DP_CONFIG                                                         0x4ca3
++#define mmDP3_DP_CONFIG                                                         0x4da3
++#define mmDP4_DP_CONFIG                                                         0x4ea3
++#define mmDP5_DP_CONFIG                                                         0x4fa3
++#define mmDP6_DP_CONFIG                                                         0x54a3
++#define mmDP7_DP_CONFIG                                                         0x56a3
++#define mmDP8_DP_CONFIG                                                         0x57a3
++#define mmDP_VID_STREAM_CNTL                                                    0x4aa4
++#define mmDP0_DP_VID_STREAM_CNTL                                                0x4aa4
++#define mmDP1_DP_VID_STREAM_CNTL                                                0x4ba4
++#define mmDP2_DP_VID_STREAM_CNTL                                                0x4ca4
++#define mmDP3_DP_VID_STREAM_CNTL                                                0x4da4
++#define mmDP4_DP_VID_STREAM_CNTL                                                0x4ea4
++#define mmDP5_DP_VID_STREAM_CNTL                                                0x4fa4
++#define mmDP6_DP_VID_STREAM_CNTL                                                0x54a4
++#define mmDP7_DP_VID_STREAM_CNTL                                                0x56a4
++#define mmDP8_DP_VID_STREAM_CNTL                                                0x57a4
++#define mmDP_STEER_FIFO                                                         0x4aa5
++#define mmDP0_DP_STEER_FIFO                                                     0x4aa5
++#define mmDP1_DP_STEER_FIFO                                                     0x4ba5
++#define mmDP2_DP_STEER_FIFO                                                     0x4ca5
++#define mmDP3_DP_STEER_FIFO                                                     0x4da5
++#define mmDP4_DP_STEER_FIFO                                                     0x4ea5
++#define mmDP5_DP_STEER_FIFO                                                     0x4fa5
++#define mmDP6_DP_STEER_FIFO                                                     0x54a5
++#define mmDP7_DP_STEER_FIFO                                                     0x56a5
++#define mmDP8_DP_STEER_FIFO                                                     0x57a5
++#define mmDP_MSA_MISC                                                           0x4aa6
++#define mmDP0_DP_MSA_MISC                                                       0x4aa6
++#define mmDP1_DP_MSA_MISC                                                       0x4ba6
++#define mmDP2_DP_MSA_MISC                                                       0x4ca6
++#define mmDP3_DP_MSA_MISC                                                       0x4da6
++#define mmDP4_DP_MSA_MISC                                                       0x4ea6
++#define mmDP5_DP_MSA_MISC                                                       0x4fa6
++#define mmDP6_DP_MSA_MISC                                                       0x54a6
++#define mmDP7_DP_MSA_MISC                                                       0x56a6
++#define mmDP8_DP_MSA_MISC                                                       0x57a6
++#define mmDP_VID_TIMING                                                         0x4aa8
++#define mmDP0_DP_VID_TIMING                                                     0x4aa8
++#define mmDP1_DP_VID_TIMING                                                     0x4ba8
++#define mmDP2_DP_VID_TIMING                                                     0x4ca8
++#define mmDP3_DP_VID_TIMING                                                     0x4da8
++#define mmDP4_DP_VID_TIMING                                                     0x4ea8
++#define mmDP5_DP_VID_TIMING                                                     0x4fa8
++#define mmDP6_DP_VID_TIMING                                                     0x54a8
++#define mmDP7_DP_VID_TIMING                                                     0x56a8
++#define mmDP8_DP_VID_TIMING                                                     0x57a8
++#define mmDP_VID_N                                                              0x4aa9
++#define mmDP0_DP_VID_N                                                          0x4aa9
++#define mmDP1_DP_VID_N                                                          0x4ba9
++#define mmDP2_DP_VID_N                                                          0x4ca9
++#define mmDP3_DP_VID_N                                                          0x4da9
++#define mmDP4_DP_VID_N                                                          0x4ea9
++#define mmDP5_DP_VID_N                                                          0x4fa9
++#define mmDP6_DP_VID_N                                                          0x54a9
++#define mmDP7_DP_VID_N                                                          0x56a9
++#define mmDP8_DP_VID_N                                                          0x57a9
++#define mmDP_VID_M                                                              0x4aaa
++#define mmDP0_DP_VID_M                                                          0x4aaa
++#define mmDP1_DP_VID_M                                                          0x4baa
++#define mmDP2_DP_VID_M                                                          0x4caa
++#define mmDP3_DP_VID_M                                                          0x4daa
++#define mmDP4_DP_VID_M                                                          0x4eaa
++#define mmDP5_DP_VID_M                                                          0x4faa
++#define mmDP6_DP_VID_M                                                          0x54aa
++#define mmDP7_DP_VID_M                                                          0x56aa
++#define mmDP8_DP_VID_M                                                          0x57aa
++#define mmDP_LINK_FRAMING_CNTL                                                  0x4aab
++#define mmDP0_DP_LINK_FRAMING_CNTL                                              0x4aab
++#define mmDP1_DP_LINK_FRAMING_CNTL                                              0x4bab
++#define mmDP2_DP_LINK_FRAMING_CNTL                                              0x4cab
++#define mmDP3_DP_LINK_FRAMING_CNTL                                              0x4dab
++#define mmDP4_DP_LINK_FRAMING_CNTL                                              0x4eab
++#define mmDP5_DP_LINK_FRAMING_CNTL                                              0x4fab
++#define mmDP6_DP_LINK_FRAMING_CNTL                                              0x54ab
++#define mmDP7_DP_LINK_FRAMING_CNTL                                              0x56ab
++#define mmDP8_DP_LINK_FRAMING_CNTL                                              0x57ab
++#define mmDP_HBR2_EYE_PATTERN                                                   0x4aac
++#define mmDP0_DP_HBR2_EYE_PATTERN                                               0x4aac
++#define mmDP1_DP_HBR2_EYE_PATTERN                                               0x4bac
++#define mmDP2_DP_HBR2_EYE_PATTERN                                               0x4cac
++#define mmDP3_DP_HBR2_EYE_PATTERN                                               0x4dac
++#define mmDP4_DP_HBR2_EYE_PATTERN                                               0x4eac
++#define mmDP5_DP_HBR2_EYE_PATTERN                                               0x4fac
++#define mmDP6_DP_HBR2_EYE_PATTERN                                               0x54ac
++#define mmDP7_DP_HBR2_EYE_PATTERN                                               0x56ac
++#define mmDP8_DP_HBR2_EYE_PATTERN                                               0x57ac
++#define mmDP_VID_MSA_VBID                                                       0x4aad
++#define mmDP0_DP_VID_MSA_VBID                                                   0x4aad
++#define mmDP1_DP_VID_MSA_VBID                                                   0x4bad
++#define mmDP2_DP_VID_MSA_VBID                                                   0x4cad
++#define mmDP3_DP_VID_MSA_VBID                                                   0x4dad
++#define mmDP4_DP_VID_MSA_VBID                                                   0x4ead
++#define mmDP5_DP_VID_MSA_VBID                                                   0x4fad
++#define mmDP6_DP_VID_MSA_VBID                                                   0x54ad
++#define mmDP7_DP_VID_MSA_VBID                                                   0x56ad
++#define mmDP8_DP_VID_MSA_VBID                                                   0x57ad
++#define mmDP_VID_INTERRUPT_CNTL                                                 0x4aae
++#define mmDP0_DP_VID_INTERRUPT_CNTL                                             0x4aae
++#define mmDP1_DP_VID_INTERRUPT_CNTL                                             0x4bae
++#define mmDP2_DP_VID_INTERRUPT_CNTL                                             0x4cae
++#define mmDP3_DP_VID_INTERRUPT_CNTL                                             0x4dae
++#define mmDP4_DP_VID_INTERRUPT_CNTL                                             0x4eae
++#define mmDP5_DP_VID_INTERRUPT_CNTL                                             0x4fae
++#define mmDP6_DP_VID_INTERRUPT_CNTL                                             0x54ae
++#define mmDP7_DP_VID_INTERRUPT_CNTL                                             0x56ae
++#define mmDP8_DP_VID_INTERRUPT_CNTL                                             0x57ae
++#define mmDP_DPHY_CNTL                                                          0x4aaf
++#define mmDP0_DP_DPHY_CNTL                                                      0x4aaf
++#define mmDP1_DP_DPHY_CNTL                                                      0x4baf
++#define mmDP2_DP_DPHY_CNTL                                                      0x4caf
++#define mmDP3_DP_DPHY_CNTL                                                      0x4daf
++#define mmDP4_DP_DPHY_CNTL                                                      0x4eaf
++#define mmDP5_DP_DPHY_CNTL                                                      0x4faf
++#define mmDP6_DP_DPHY_CNTL                                                      0x54af
++#define mmDP7_DP_DPHY_CNTL                                                      0x56af
++#define mmDP8_DP_DPHY_CNTL                                                      0x57af
++#define mmDP_DPHY_TRAINING_PATTERN_SEL                                          0x4ab0
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4ab0
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4bb0
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4cb0
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4db0
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4eb0
++#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4fb0
++#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                      0x54b0
++#define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL                                      0x56b0
++#define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL                                      0x57b0
++#define mmDP_DPHY_SYM0                                                          0x4ab1
++#define mmDP0_DP_DPHY_SYM0                                                      0x4ab1
++#define mmDP1_DP_DPHY_SYM0                                                      0x4bb1
++#define mmDP2_DP_DPHY_SYM0                                                      0x4cb1
++#define mmDP3_DP_DPHY_SYM0                                                      0x4db1
++#define mmDP4_DP_DPHY_SYM0                                                      0x4eb1
++#define mmDP5_DP_DPHY_SYM0                                                      0x4fb1
++#define mmDP6_DP_DPHY_SYM0                                                      0x54b1
++#define mmDP7_DP_DPHY_SYM0                                                      0x56b1
++#define mmDP8_DP_DPHY_SYM0                                                      0x57b1
++#define mmDP_DPHY_SYM1                                                          0x4ab2
++#define mmDP0_DP_DPHY_SYM1                                                      0x4ab2
++#define mmDP1_DP_DPHY_SYM1                                                      0x4bb2
++#define mmDP2_DP_DPHY_SYM1                                                      0x4cb2
++#define mmDP3_DP_DPHY_SYM1                                                      0x4db2
++#define mmDP4_DP_DPHY_SYM1                                                      0x4eb2
++#define mmDP5_DP_DPHY_SYM1                                                      0x4fb2
++#define mmDP6_DP_DPHY_SYM1                                                      0x54b2
++#define mmDP7_DP_DPHY_SYM1                                                      0x56b2
++#define mmDP8_DP_DPHY_SYM1                                                      0x57b2
++#define mmDP_DPHY_SYM2                                                          0x4ab3
++#define mmDP0_DP_DPHY_SYM2                                                      0x4ab3
++#define mmDP1_DP_DPHY_SYM2                                                      0x4bb3
++#define mmDP2_DP_DPHY_SYM2                                                      0x4cb3
++#define mmDP3_DP_DPHY_SYM2                                                      0x4db3
++#define mmDP4_DP_DPHY_SYM2                                                      0x4eb3
++#define mmDP5_DP_DPHY_SYM2                                                      0x4fb3
++#define mmDP6_DP_DPHY_SYM2                                                      0x54b3
++#define mmDP7_DP_DPHY_SYM2                                                      0x56b3
++#define mmDP8_DP_DPHY_SYM2                                                      0x57b3
++#define mmDP_DPHY_8B10B_CNTL                                                    0x4ab4
++#define mmDP0_DP_DPHY_8B10B_CNTL                                                0x4ab4
++#define mmDP1_DP_DPHY_8B10B_CNTL                                                0x4bb4
++#define mmDP2_DP_DPHY_8B10B_CNTL                                                0x4cb4
++#define mmDP3_DP_DPHY_8B10B_CNTL                                                0x4db4
++#define mmDP4_DP_DPHY_8B10B_CNTL                                                0x4eb4
++#define mmDP5_DP_DPHY_8B10B_CNTL                                                0x4fb4
++#define mmDP6_DP_DPHY_8B10B_CNTL                                                0x54b4
++#define mmDP7_DP_DPHY_8B10B_CNTL                                                0x56b4
++#define mmDP8_DP_DPHY_8B10B_CNTL                                                0x57b4
++#define mmDP_DPHY_PRBS_CNTL                                                     0x4ab5
++#define mmDP0_DP_DPHY_PRBS_CNTL                                                 0x4ab5
++#define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
++#define mmDP2_DP_DPHY_PRBS_CNTL                                                 0x4cb5
++#define mmDP3_DP_DPHY_PRBS_CNTL                                                 0x4db5
++#define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
++#define mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4fb5
++#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5
++#define mmDP7_DP_DPHY_PRBS_CNTL                                                 0x56b5
++#define mmDP8_DP_DPHY_PRBS_CNTL                                                 0x57b5
++#define mmDP_DPHY_BS_SR_SWAP_CNTL                                               0x4adc
++#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4adc
++#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4bdc
++#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4cdc
++#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4ddc
++#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4edc
++#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4fdc
++#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                                           0x54dc
++#define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL                                           0x56dc
++#define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL                                           0x57dc
++#define mmDP_DPHY_CRC_EN                                                        0x4ab7
++#define mmDP0_DP_DPHY_CRC_EN                                                    0x4ab7
++#define mmDP1_DP_DPHY_CRC_EN                                                    0x4bb7
++#define mmDP2_DP_DPHY_CRC_EN                                                    0x4cb7
++#define mmDP3_DP_DPHY_CRC_EN                                                    0x4db7
++#define mmDP4_DP_DPHY_CRC_EN                                                    0x4eb7
++#define mmDP5_DP_DPHY_CRC_EN                                                    0x4fb7
++#define mmDP6_DP_DPHY_CRC_EN                                                    0x54b7
++#define mmDP7_DP_DPHY_CRC_EN                                                    0x56b7
++#define mmDP8_DP_DPHY_CRC_EN                                                    0x57b7
++#define mmDP_DPHY_CRC_CNTL                                                      0x4ab8
++#define mmDP0_DP_DPHY_CRC_CNTL                                                  0x4ab8
++#define mmDP1_DP_DPHY_CRC_CNTL                                                  0x4bb8
++#define mmDP2_DP_DPHY_CRC_CNTL                                                  0x4cb8
++#define mmDP3_DP_DPHY_CRC_CNTL                                                  0x4db8
++#define mmDP4_DP_DPHY_CRC_CNTL                                                  0x4eb8
++#define mmDP5_DP_DPHY_CRC_CNTL                                                  0x4fb8
++#define mmDP6_DP_DPHY_CRC_CNTL                                                  0x54b8
++#define mmDP7_DP_DPHY_CRC_CNTL                                                  0x56b8
++#define mmDP8_DP_DPHY_CRC_CNTL                                                  0x57b8
++#define mmDP_DPHY_CRC_RESULT                                                    0x4ab9
++#define mmDP0_DP_DPHY_CRC_RESULT                                                0x4ab9
++#define mmDP1_DP_DPHY_CRC_RESULT                                                0x4bb9
++#define mmDP2_DP_DPHY_CRC_RESULT                                                0x4cb9
++#define mmDP3_DP_DPHY_CRC_RESULT                                                0x4db9
++#define mmDP4_DP_DPHY_CRC_RESULT                                                0x4eb9
++#define mmDP5_DP_DPHY_CRC_RESULT                                                0x4fb9
++#define mmDP6_DP_DPHY_CRC_RESULT                                                0x54b9
++#define mmDP7_DP_DPHY_CRC_RESULT                                                0x56b9
++#define mmDP8_DP_DPHY_CRC_RESULT                                                0x57b9
++#define mmDP_DPHY_CRC_MST_CNTL                                                  0x4aba
++#define mmDP0_DP_DPHY_CRC_MST_CNTL                                              0x4aba
++#define mmDP1_DP_DPHY_CRC_MST_CNTL                                              0x4bba
++#define mmDP2_DP_DPHY_CRC_MST_CNTL                                              0x4cba
++#define mmDP3_DP_DPHY_CRC_MST_CNTL                                              0x4dba
++#define mmDP4_DP_DPHY_CRC_MST_CNTL                                              0x4eba
++#define mmDP5_DP_DPHY_CRC_MST_CNTL                                              0x4fba
++#define mmDP6_DP_DPHY_CRC_MST_CNTL                                              0x54ba
++#define mmDP7_DP_DPHY_CRC_MST_CNTL                                              0x56ba
++#define mmDP8_DP_DPHY_CRC_MST_CNTL                                              0x57ba
++#define mmDP_DPHY_CRC_MST_STATUS                                                0x4abb
++#define mmDP0_DP_DPHY_CRC_MST_STATUS                                            0x4abb
++#define mmDP1_DP_DPHY_CRC_MST_STATUS                                            0x4bbb
++#define mmDP2_DP_DPHY_CRC_MST_STATUS                                            0x4cbb
++#define mmDP3_DP_DPHY_CRC_MST_STATUS                                            0x4dbb
++#define mmDP4_DP_DPHY_CRC_MST_STATUS                                            0x4ebb
++#define mmDP5_DP_DPHY_CRC_MST_STATUS                                            0x4fbb
++#define mmDP6_DP_DPHY_CRC_MST_STATUS                                            0x54bb
++#define mmDP7_DP_DPHY_CRC_MST_STATUS                                            0x56bb
++#define mmDP8_DP_DPHY_CRC_MST_STATUS                                            0x57bb
++#define mmDP_DPHY_FAST_TRAINING                                                 0x4abc
++#define mmDP0_DP_DPHY_FAST_TRAINING                                             0x4abc
++#define mmDP1_DP_DPHY_FAST_TRAINING                                             0x4bbc
++#define mmDP2_DP_DPHY_FAST_TRAINING                                             0x4cbc
++#define mmDP3_DP_DPHY_FAST_TRAINING                                             0x4dbc
++#define mmDP4_DP_DPHY_FAST_TRAINING                                             0x4ebc
++#define mmDP5_DP_DPHY_FAST_TRAINING                                             0x4fbc
++#define mmDP6_DP_DPHY_FAST_TRAINING                                             0x54bc
++#define mmDP7_DP_DPHY_FAST_TRAINING                                             0x56bc
++#define mmDP8_DP_DPHY_FAST_TRAINING                                             0x57bc
++#define mmDP_DPHY_FAST_TRAINING_STATUS                                          0x4abd
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                      0x4abd
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                      0x4bbd
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                      0x4cbd
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                      0x4dbd
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                      0x4ebd
++#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                      0x4fbd
++#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                      0x54bd
++#define mmDP7_DP_DPHY_FAST_TRAINING_STATUS                                      0x56bd
++#define mmDP8_DP_DPHY_FAST_TRAINING_STATUS                                      0x57bd
++#define mmDP_DPHY_HBR2_PATTERN_CONTROL                                          0x4add
++#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4add
++#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4bdd
++#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4cdd
++#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4ddd
++#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4edd
++#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4fdd
++#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x54dd
++#define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x56dd
++#define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x57dd
++#define mmDP_MSA_V_TIMING_OVERRIDE1                                             0x4abe
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                         0x4abe
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                         0x4bbe
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                         0x4cbe
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                         0x4dbe
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                         0x4ebe
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                         0x4fbe
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                         0x54be
++#define mmDP7_DP_MSA_V_TIMING_OVERRIDE1                                         0x56be
++#define mmDP8_DP_MSA_V_TIMING_OVERRIDE1                                         0x57be
++#define mmDP_MSA_V_TIMING_OVERRIDE2                                             0x4abf
++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                         0x4abf
++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                         0x4bbf
++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                         0x4cbf
++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                         0x4dbf
++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                         0x4ebf
++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                         0x4fbf
++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                         0x54bf
++#define mmDP7_DP_MSA_V_TIMING_OVERRIDE2                                         0x56bf
++#define mmDP8_DP_MSA_V_TIMING_OVERRIDE2                                         0x57bf
++#define mmDP_SEC_CNTL                                                           0x4ac3
++#define mmDP0_DP_SEC_CNTL                                                       0x4ac3
++#define mmDP1_DP_SEC_CNTL                                                       0x4bc3
++#define mmDP2_DP_SEC_CNTL                                                       0x4cc3
++#define mmDP3_DP_SEC_CNTL                                                       0x4dc3
++#define mmDP4_DP_SEC_CNTL                                                       0x4ec3
++#define mmDP5_DP_SEC_CNTL                                                       0x4fc3
++#define mmDP6_DP_SEC_CNTL                                                       0x54c3
++#define mmDP7_DP_SEC_CNTL                                                       0x56c3
++#define mmDP8_DP_SEC_CNTL                                                       0x57c3
++#define mmDP_SEC_CNTL1                                                          0x4ac4
++#define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
++#define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
++#define mmDP2_DP_SEC_CNTL1                                                      0x4cc4
++#define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
++#define mmDP4_DP_SEC_CNTL1                                                      0x4ec4
++#define mmDP5_DP_SEC_CNTL1                                                      0x4fc4
++#define mmDP6_DP_SEC_CNTL1                                                      0x54c4
++#define mmDP7_DP_SEC_CNTL1                                                      0x56c4
++#define mmDP8_DP_SEC_CNTL1                                                      0x57c4
++#define mmDP_SEC_FRAMING1                                                       0x4ac5
++#define mmDP0_DP_SEC_FRAMING1                                                   0x4ac5
++#define mmDP1_DP_SEC_FRAMING1                                                   0x4bc5
++#define mmDP2_DP_SEC_FRAMING1                                                   0x4cc5
++#define mmDP3_DP_SEC_FRAMING1                                                   0x4dc5
++#define mmDP4_DP_SEC_FRAMING1                                                   0x4ec5
++#define mmDP5_DP_SEC_FRAMING1                                                   0x4fc5
++#define mmDP6_DP_SEC_FRAMING1                                                   0x54c5
++#define mmDP7_DP_SEC_FRAMING1                                                   0x56c5
++#define mmDP8_DP_SEC_FRAMING1                                                   0x57c5
++#define mmDP_SEC_FRAMING2                                                       0x4ac6
++#define mmDP0_DP_SEC_FRAMING2                                                   0x4ac6
++#define mmDP1_DP_SEC_FRAMING2                                                   0x4bc6
++#define mmDP2_DP_SEC_FRAMING2                                                   0x4cc6
++#define mmDP3_DP_SEC_FRAMING2                                                   0x4dc6
++#define mmDP4_DP_SEC_FRAMING2                                                   0x4ec6
++#define mmDP5_DP_SEC_FRAMING2                                                   0x4fc6
++#define mmDP6_DP_SEC_FRAMING2                                                   0x54c6
++#define mmDP7_DP_SEC_FRAMING2                                                   0x56c6
++#define mmDP8_DP_SEC_FRAMING2                                                   0x57c6
++#define mmDP_SEC_FRAMING3                                                       0x4ac7
++#define mmDP0_DP_SEC_FRAMING3                                                   0x4ac7
++#define mmDP1_DP_SEC_FRAMING3                                                   0x4bc7
++#define mmDP2_DP_SEC_FRAMING3                                                   0x4cc7
++#define mmDP3_DP_SEC_FRAMING3                                                   0x4dc7
++#define mmDP4_DP_SEC_FRAMING3                                                   0x4ec7
++#define mmDP5_DP_SEC_FRAMING3                                                   0x4fc7
++#define mmDP6_DP_SEC_FRAMING3                                                   0x54c7
++#define mmDP7_DP_SEC_FRAMING3                                                   0x56c7
++#define mmDP8_DP_SEC_FRAMING3                                                   0x57c7
++#define mmDP_SEC_FRAMING4                                                       0x4ac8
++#define mmDP0_DP_SEC_FRAMING4                                                   0x4ac8
++#define mmDP1_DP_SEC_FRAMING4                                                   0x4bc8
++#define mmDP2_DP_SEC_FRAMING4                                                   0x4cc8
++#define mmDP3_DP_SEC_FRAMING4                                                   0x4dc8
++#define mmDP4_DP_SEC_FRAMING4                                                   0x4ec8
++#define mmDP5_DP_SEC_FRAMING4                                                   0x4fc8
++#define mmDP6_DP_SEC_FRAMING4                                                   0x54c8
++#define mmDP7_DP_SEC_FRAMING4                                                   0x56c8
++#define mmDP8_DP_SEC_FRAMING4                                                   0x57c8
++#define mmDP_SEC_AUD_N                                                          0x4ac9
++#define mmDP0_DP_SEC_AUD_N                                                      0x4ac9
++#define mmDP1_DP_SEC_AUD_N                                                      0x4bc9
++#define mmDP2_DP_SEC_AUD_N                                                      0x4cc9
++#define mmDP3_DP_SEC_AUD_N                                                      0x4dc9
++#define mmDP4_DP_SEC_AUD_N                                                      0x4ec9
++#define mmDP5_DP_SEC_AUD_N                                                      0x4fc9
++#define mmDP6_DP_SEC_AUD_N                                                      0x54c9
++#define mmDP7_DP_SEC_AUD_N                                                      0x56c9
++#define mmDP8_DP_SEC_AUD_N                                                      0x57c9
++#define mmDP_SEC_AUD_N_READBACK                                                 0x4aca
++#define mmDP0_DP_SEC_AUD_N_READBACK                                             0x4aca
++#define mmDP1_DP_SEC_AUD_N_READBACK                                             0x4bca
++#define mmDP2_DP_SEC_AUD_N_READBACK                                             0x4cca
++#define mmDP3_DP_SEC_AUD_N_READBACK                                             0x4dca
++#define mmDP4_DP_SEC_AUD_N_READBACK                                             0x4eca
++#define mmDP5_DP_SEC_AUD_N_READBACK                                             0x4fca
++#define mmDP6_DP_SEC_AUD_N_READBACK                                             0x54ca
++#define mmDP7_DP_SEC_AUD_N_READBACK                                             0x56ca
++#define mmDP8_DP_SEC_AUD_N_READBACK                                             0x57ca
++#define mmDP_SEC_AUD_M                                                          0x4acb
++#define mmDP0_DP_SEC_AUD_M                                                      0x4acb
++#define mmDP1_DP_SEC_AUD_M                                                      0x4bcb
++#define mmDP2_DP_SEC_AUD_M                                                      0x4ccb
++#define mmDP3_DP_SEC_AUD_M                                                      0x4dcb
++#define mmDP4_DP_SEC_AUD_M                                                      0x4ecb
++#define mmDP5_DP_SEC_AUD_M                                                      0x4fcb
++#define mmDP6_DP_SEC_AUD_M                                                      0x54cb
++#define mmDP7_DP_SEC_AUD_M                                                      0x56cb
++#define mmDP8_DP_SEC_AUD_M                                                      0x57cb
++#define mmDP_SEC_AUD_M_READBACK                                                 0x4acc
++#define mmDP0_DP_SEC_AUD_M_READBACK                                             0x4acc
++#define mmDP1_DP_SEC_AUD_M_READBACK                                             0x4bcc
++#define mmDP2_DP_SEC_AUD_M_READBACK                                             0x4ccc
++#define mmDP3_DP_SEC_AUD_M_READBACK                                             0x4dcc
++#define mmDP4_DP_SEC_AUD_M_READBACK                                             0x4ecc
++#define mmDP5_DP_SEC_AUD_M_READBACK                                             0x4fcc
++#define mmDP6_DP_SEC_AUD_M_READBACK                                             0x54cc
++#define mmDP7_DP_SEC_AUD_M_READBACK                                             0x56cc
++#define mmDP8_DP_SEC_AUD_M_READBACK                                             0x57cc
++#define mmDP_SEC_TIMESTAMP                                                      0x4acd
++#define mmDP0_DP_SEC_TIMESTAMP                                                  0x4acd
++#define mmDP1_DP_SEC_TIMESTAMP                                                  0x4bcd
++#define mmDP2_DP_SEC_TIMESTAMP                                                  0x4ccd
++#define mmDP3_DP_SEC_TIMESTAMP                                                  0x4dcd
++#define mmDP4_DP_SEC_TIMESTAMP                                                  0x4ecd
++#define mmDP5_DP_SEC_TIMESTAMP                                                  0x4fcd
++#define mmDP6_DP_SEC_TIMESTAMP                                                  0x54cd
++#define mmDP7_DP_SEC_TIMESTAMP                                                  0x56cd
++#define mmDP8_DP_SEC_TIMESTAMP                                                  0x57cd
++#define mmDP_SEC_PACKET_CNTL                                                    0x4ace
++#define mmDP0_DP_SEC_PACKET_CNTL                                                0x4ace
++#define mmDP1_DP_SEC_PACKET_CNTL                                                0x4bce
++#define mmDP2_DP_SEC_PACKET_CNTL                                                0x4cce
++#define mmDP3_DP_SEC_PACKET_CNTL                                                0x4dce
++#define mmDP4_DP_SEC_PACKET_CNTL                                                0x4ece
++#define mmDP5_DP_SEC_PACKET_CNTL                                                0x4fce
++#define mmDP6_DP_SEC_PACKET_CNTL                                                0x54ce
++#define mmDP7_DP_SEC_PACKET_CNTL                                                0x56ce
++#define mmDP8_DP_SEC_PACKET_CNTL                                                0x57ce
++#define mmDP_MSE_RATE_CNTL                                                      0x4acf
++#define mmDP0_DP_MSE_RATE_CNTL                                                  0x4acf
++#define mmDP1_DP_MSE_RATE_CNTL                                                  0x4bcf
++#define mmDP2_DP_MSE_RATE_CNTL                                                  0x4ccf
++#define mmDP3_DP_MSE_RATE_CNTL                                                  0x4dcf
++#define mmDP4_DP_MSE_RATE_CNTL                                                  0x4ecf
++#define mmDP5_DP_MSE_RATE_CNTL                                                  0x4fcf
++#define mmDP6_DP_MSE_RATE_CNTL                                                  0x54cf
++#define mmDP7_DP_MSE_RATE_CNTL                                                  0x56cf
++#define mmDP8_DP_MSE_RATE_CNTL                                                  0x57cf
++#define mmDP_MSE_RATE_UPDATE                                                    0x4ad1
++#define mmDP0_DP_MSE_RATE_UPDATE                                                0x4ad1
++#define mmDP1_DP_MSE_RATE_UPDATE                                                0x4bd1
++#define mmDP2_DP_MSE_RATE_UPDATE                                                0x4cd1
++#define mmDP3_DP_MSE_RATE_UPDATE                                                0x4dd1
++#define mmDP4_DP_MSE_RATE_UPDATE                                                0x4ed1
++#define mmDP5_DP_MSE_RATE_UPDATE                                                0x4fd1
++#define mmDP6_DP_MSE_RATE_UPDATE                                                0x54d1
++#define mmDP7_DP_MSE_RATE_UPDATE                                                0x56d1
++#define mmDP8_DP_MSE_RATE_UPDATE                                                0x57d1
++#define mmDP_MSE_SAT0                                                           0x4ad2
++#define mmDP0_DP_MSE_SAT0                                                       0x4ad2
++#define mmDP1_DP_MSE_SAT0                                                       0x4bd2
++#define mmDP2_DP_MSE_SAT0                                                       0x4cd2
++#define mmDP3_DP_MSE_SAT0                                                       0x4dd2
++#define mmDP4_DP_MSE_SAT0                                                       0x4ed2
++#define mmDP5_DP_MSE_SAT0                                                       0x4fd2
++#define mmDP6_DP_MSE_SAT0                                                       0x54d2
++#define mmDP7_DP_MSE_SAT0                                                       0x56d2
++#define mmDP8_DP_MSE_SAT0                                                       0x57d2
++#define mmDP_MSE_SAT1                                                           0x4ad3
++#define mmDP0_DP_MSE_SAT1                                                       0x4ad3
++#define mmDP1_DP_MSE_SAT1                                                       0x4bd3
++#define mmDP2_DP_MSE_SAT1                                                       0x4cd3
++#define mmDP3_DP_MSE_SAT1                                                       0x4dd3
++#define mmDP4_DP_MSE_SAT1                                                       0x4ed3
++#define mmDP5_DP_MSE_SAT1                                                       0x4fd3
++#define mmDP6_DP_MSE_SAT1                                                       0x54d3
++#define mmDP7_DP_MSE_SAT1                                                       0x56d3
++#define mmDP8_DP_MSE_SAT1                                                       0x57d3
++#define mmDP_MSE_SAT2                                                           0x4ad4
++#define mmDP0_DP_MSE_SAT2                                                       0x4ad4
++#define mmDP1_DP_MSE_SAT2                                                       0x4bd4
++#define mmDP2_DP_MSE_SAT2                                                       0x4cd4
++#define mmDP3_DP_MSE_SAT2                                                       0x4dd4
++#define mmDP4_DP_MSE_SAT2                                                       0x4ed4
++#define mmDP5_DP_MSE_SAT2                                                       0x4fd4
++#define mmDP6_DP_MSE_SAT2                                                       0x54d4
++#define mmDP7_DP_MSE_SAT2                                                       0x56d4
++#define mmDP8_DP_MSE_SAT2                                                       0x57d4
++#define mmDP_MSE_SAT_UPDATE                                                     0x4ad5
++#define mmDP0_DP_MSE_SAT_UPDATE                                                 0x4ad5
++#define mmDP1_DP_MSE_SAT_UPDATE                                                 0x4bd5
++#define mmDP2_DP_MSE_SAT_UPDATE                                                 0x4cd5
++#define mmDP3_DP_MSE_SAT_UPDATE                                                 0x4dd5
++#define mmDP4_DP_MSE_SAT_UPDATE                                                 0x4ed5
++#define mmDP5_DP_MSE_SAT_UPDATE                                                 0x4fd5
++#define mmDP6_DP_MSE_SAT_UPDATE                                                 0x54d5
++#define mmDP7_DP_MSE_SAT_UPDATE                                                 0x56d5
++#define mmDP8_DP_MSE_SAT_UPDATE                                                 0x57d5
++#define mmDP_MSE_LINK_TIMING                                                    0x4ad6
++#define mmDP0_DP_MSE_LINK_TIMING                                                0x4ad6
++#define mmDP1_DP_MSE_LINK_TIMING                                                0x4bd6
++#define mmDP2_DP_MSE_LINK_TIMING                                                0x4cd6
++#define mmDP3_DP_MSE_LINK_TIMING                                                0x4dd6
++#define mmDP4_DP_MSE_LINK_TIMING                                                0x4ed6
++#define mmDP5_DP_MSE_LINK_TIMING                                                0x4fd6
++#define mmDP6_DP_MSE_LINK_TIMING                                                0x54d6
++#define mmDP7_DP_MSE_LINK_TIMING                                                0x56d6
++#define mmDP8_DP_MSE_LINK_TIMING                                                0x57d6
++#define mmDP_MSE_MISC_CNTL                                                      0x4ad7
++#define mmDP0_DP_MSE_MISC_CNTL                                                  0x4ad7
++#define mmDP1_DP_MSE_MISC_CNTL                                                  0x4bd7
++#define mmDP2_DP_MSE_MISC_CNTL                                                  0x4cd7
++#define mmDP3_DP_MSE_MISC_CNTL                                                  0x4dd7
++#define mmDP4_DP_MSE_MISC_CNTL                                                  0x4ed7
++#define mmDP5_DP_MSE_MISC_CNTL                                                  0x4fd7
++#define mmDP6_DP_MSE_MISC_CNTL                                                  0x54d7
++#define mmDP7_DP_MSE_MISC_CNTL                                                  0x56d7
++#define mmDP8_DP_MSE_MISC_CNTL                                                  0x57d7
++#define mmDP_TEST_DEBUG_INDEX                                                   0x4ad8
++#define mmDP0_DP_TEST_DEBUG_INDEX                                               0x4ad8
++#define mmDP1_DP_TEST_DEBUG_INDEX                                               0x4bd8
++#define mmDP2_DP_TEST_DEBUG_INDEX                                               0x4cd8
++#define mmDP3_DP_TEST_DEBUG_INDEX                                               0x4dd8
++#define mmDP4_DP_TEST_DEBUG_INDEX                                               0x4ed8
++#define mmDP5_DP_TEST_DEBUG_INDEX                                               0x4fd8
++#define mmDP6_DP_TEST_DEBUG_INDEX                                               0x54d8
++#define mmDP7_DP_TEST_DEBUG_INDEX                                               0x56d8
++#define mmDP8_DP_TEST_DEBUG_INDEX                                               0x57d8
++#define mmDP_TEST_DEBUG_DATA                                                    0x4ad9
++#define mmDP0_DP_TEST_DEBUG_DATA                                                0x4ad9
++#define mmDP1_DP_TEST_DEBUG_DATA                                                0x4bd9
++#define mmDP2_DP_TEST_DEBUG_DATA                                                0x4cd9
++#define mmDP3_DP_TEST_DEBUG_DATA                                                0x4dd9
++#define mmDP4_DP_TEST_DEBUG_DATA                                                0x4ed9
++#define mmDP5_DP_TEST_DEBUG_DATA                                                0x4fd9
++#define mmDP6_DP_TEST_DEBUG_DATA                                                0x54d9
++#define mmDP7_DP_TEST_DEBUG_DATA                                                0x56d9
++#define mmDP8_DP_TEST_DEBUG_DATA                                                0x57d9
++#define mmDP_FE_TEST_DEBUG_INDEX                                                0x4ada
++#define mmDP0_DP_FE_TEST_DEBUG_INDEX                                            0x4ada
++#define mmDP1_DP_FE_TEST_DEBUG_INDEX                                            0x4bda
++#define mmDP2_DP_FE_TEST_DEBUG_INDEX                                            0x4cda
++#define mmDP3_DP_FE_TEST_DEBUG_INDEX                                            0x4dda
++#define mmDP4_DP_FE_TEST_DEBUG_INDEX                                            0x4eda
++#define mmDP5_DP_FE_TEST_DEBUG_INDEX                                            0x4fda
++#define mmDP6_DP_FE_TEST_DEBUG_INDEX                                            0x54da
++#define mmDP7_DP_FE_TEST_DEBUG_INDEX                                            0x56da
++#define mmDP8_DP_FE_TEST_DEBUG_INDEX                                            0x57da
++#define mmDP_FE_TEST_DEBUG_DATA                                                 0x4adb
++#define mmDP0_DP_FE_TEST_DEBUG_DATA                                             0x4adb
++#define mmDP1_DP_FE_TEST_DEBUG_DATA                                             0x4bdb
++#define mmDP2_DP_FE_TEST_DEBUG_DATA                                             0x4cdb
++#define mmDP3_DP_FE_TEST_DEBUG_DATA                                             0x4ddb
++#define mmDP4_DP_FE_TEST_DEBUG_DATA                                             0x4edb
++#define mmDP5_DP_FE_TEST_DEBUG_DATA                                             0x4fdb
++#define mmDP6_DP_FE_TEST_DEBUG_DATA                                             0x54db
++#define mmDP7_DP_FE_TEST_DEBUG_DATA                                             0x56db
++#define mmDP8_DP_FE_TEST_DEBUG_DATA                                             0x57db
++#define mmAUX_CONTROL                                                           0x5c00
++#define mmDP_AUX0_AUX_CONTROL                                                   0x5c00
++#define mmDP_AUX1_AUX_CONTROL                                                   0x5c1c
++#define mmDP_AUX2_AUX_CONTROL                                                   0x5c38
++#define mmDP_AUX3_AUX_CONTROL                                                   0x5c54
++#define mmDP_AUX4_AUX_CONTROL                                                   0x5c70
++#define mmDP_AUX5_AUX_CONTROL                                                   0x5c8c
++#define mmAUX_SW_CONTROL                                                        0x5c01
++#define mmDP_AUX0_AUX_SW_CONTROL                                                0x5c01
++#define mmDP_AUX1_AUX_SW_CONTROL                                                0x5c1d
++#define mmDP_AUX2_AUX_SW_CONTROL                                                0x5c39
++#define mmDP_AUX3_AUX_SW_CONTROL                                                0x5c55
++#define mmDP_AUX4_AUX_SW_CONTROL                                                0x5c71
++#define mmDP_AUX5_AUX_SW_CONTROL                                                0x5c8d
++#define mmAUX_ARB_CONTROL                                                       0x5c02
++#define mmDP_AUX0_AUX_ARB_CONTROL                                               0x5c02
++#define mmDP_AUX1_AUX_ARB_CONTROL                                               0x5c1e
++#define mmDP_AUX2_AUX_ARB_CONTROL                                               0x5c3a
++#define mmDP_AUX3_AUX_ARB_CONTROL                                               0x5c56
++#define mmDP_AUX4_AUX_ARB_CONTROL                                               0x5c72
++#define mmDP_AUX5_AUX_ARB_CONTROL                                               0x5c8e
++#define mmAUX_INTERRUPT_CONTROL                                                 0x5c03
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                         0x5c03
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                         0x5c1f
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                         0x5c3b
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                         0x5c57
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                         0x5c73
++#define mmDP_AUX5_AUX_INTERRUPT_CONTROL                                         0x5c8f
++#define mmAUX_SW_STATUS                                                         0x5c04
++#define mmDP_AUX0_AUX_SW_STATUS                                                 0x5c04
++#define mmDP_AUX1_AUX_SW_STATUS                                                 0x5c20
++#define mmDP_AUX2_AUX_SW_STATUS                                                 0x5c3c
++#define mmDP_AUX3_AUX_SW_STATUS                                                 0x5c58
++#define mmDP_AUX4_AUX_SW_STATUS                                                 0x5c74
++#define mmDP_AUX5_AUX_SW_STATUS                                                 0x5c90
++#define mmAUX_LS_STATUS                                                         0x5c05
++#define mmDP_AUX0_AUX_LS_STATUS                                                 0x5c05
++#define mmDP_AUX1_AUX_LS_STATUS                                                 0x5c21
++#define mmDP_AUX2_AUX_LS_STATUS                                                 0x5c3d
++#define mmDP_AUX3_AUX_LS_STATUS                                                 0x5c59
++#define mmDP_AUX4_AUX_LS_STATUS                                                 0x5c75
++#define mmDP_AUX5_AUX_LS_STATUS                                                 0x5c91
++#define mmAUX_SW_DATA                                                           0x5c06
++#define mmDP_AUX0_AUX_SW_DATA                                                   0x5c06
++#define mmDP_AUX1_AUX_SW_DATA                                                   0x5c22
++#define mmDP_AUX2_AUX_SW_DATA                                                   0x5c3e
++#define mmDP_AUX3_AUX_SW_DATA                                                   0x5c5a
++#define mmDP_AUX4_AUX_SW_DATA                                                   0x5c76
++#define mmDP_AUX5_AUX_SW_DATA                                                   0x5c92
++#define mmAUX_LS_DATA                                                           0x5c07
++#define mmDP_AUX0_AUX_LS_DATA                                                   0x5c07
++#define mmDP_AUX1_AUX_LS_DATA                                                   0x5c23
++#define mmDP_AUX2_AUX_LS_DATA                                                   0x5c3f
++#define mmDP_AUX3_AUX_LS_DATA                                                   0x5c5b
++#define mmDP_AUX4_AUX_LS_DATA                                                   0x5c77
++#define mmDP_AUX5_AUX_LS_DATA                                                   0x5c93
++#define mmAUX_DPHY_TX_REF_CONTROL                                               0x5c08
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                       0x5c08
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                       0x5c24
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                       0x5c40
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                       0x5c5c
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                       0x5c78
++#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                       0x5c94
++#define mmAUX_DPHY_TX_CONTROL                                                   0x5c09
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                           0x5c09
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                           0x5c25
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                           0x5c41
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                           0x5c5d
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                           0x5c79
++#define mmDP_AUX5_AUX_DPHY_TX_CONTROL                                           0x5c95
++#define mmAUX_DPHY_RX_CONTROL0                                                  0x5c0a
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                          0x5c0a
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                          0x5c26
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                          0x5c42
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                          0x5c5e
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                          0x5c7a
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                          0x5c96
++#define mmAUX_DPHY_RX_CONTROL1                                                  0x5c0b
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                          0x5c0b
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                          0x5c27
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                          0x5c43
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                          0x5c5f
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                          0x5c7b
++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                          0x5c97
++#define mmAUX_DPHY_TX_STATUS                                                    0x5c0c
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                            0x5c0c
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                            0x5c28
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                            0x5c44
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                            0x5c60
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS                                            0x5c7c
++#define mmDP_AUX5_AUX_DPHY_TX_STATUS                                            0x5c98
++#define mmAUX_DPHY_RX_STATUS                                                    0x5c0d
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                            0x5c0d
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                            0x5c29
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                            0x5c45
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                            0x5c61
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS                                            0x5c7d
++#define mmDP_AUX5_AUX_DPHY_RX_STATUS                                            0x5c99
++#define mmAUX_GTC_SYNC_CONTROL                                                  0x5c0e
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                          0x5c0e
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                          0x5c2a
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                          0x5c46
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                          0x5c62
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                          0x5c7e
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL                                          0x5c9a
++#define mmAUX_GTC_SYNC_ERROR_CONTROL                                            0x5c0f
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c0f
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c2b
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c47
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c63
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c7f
++#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c9b
++#define mmAUX_GTC_SYNC_CONTROLLER_STATUS                                        0x5c10
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c10
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c2c
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c48
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c64
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c80
++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c9c
++#define mmAUX_GTC_SYNC_STATUS                                                   0x5c11
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                           0x5c11
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                           0x5c2d
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                           0x5c49
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                           0x5c65
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                           0x5c81
++#define mmDP_AUX5_AUX_GTC_SYNC_STATUS                                           0x5c9d
++#define mmAUX_GTC_SYNC_DATA                                                     0x5c12
++#define mmDP_AUX0_AUX_GTC_SYNC_DATA                                             0x5c12
++#define mmDP_AUX1_AUX_GTC_SYNC_DATA                                             0x5c2e
++#define mmDP_AUX2_AUX_GTC_SYNC_DATA                                             0x5c4a
++#define mmDP_AUX3_AUX_GTC_SYNC_DATA                                             0x5c66
++#define mmDP_AUX4_AUX_GTC_SYNC_DATA                                             0x5c82
++#define mmDP_AUX5_AUX_GTC_SYNC_DATA                                             0x5c9e
++#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                                    0x5c13
++#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c13
++#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c2f
++#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c4b
++#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c67
++#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c83
++#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE                            0x5c9f
++#define mmAUX_TEST_DEBUG_INDEX                                                  0x5c14
++#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX                                          0x5c14
++#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX                                          0x5c30
++#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX                                          0x5c4c
++#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX                                          0x5c68
++#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX                                          0x5c84
++#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX                                          0x5ca0
++#define mmAUX_TEST_DEBUG_DATA                                                   0x5c15
++#define mmDP_AUX0_AUX_TEST_DEBUG_DATA                                           0x5c15
++#define mmDP_AUX1_AUX_TEST_DEBUG_DATA                                           0x5c31
++#define mmDP_AUX2_AUX_TEST_DEBUG_DATA                                           0x5c4d
++#define mmDP_AUX3_AUX_TEST_DEBUG_DATA                                           0x5c69
++#define mmDP_AUX4_AUX_TEST_DEBUG_DATA                                           0x5c85
++#define mmDP_AUX5_AUX_TEST_DEBUG_DATA                                           0x5ca1
++#define ixDP_AUX_DEBUG_A                                                        0x10
++#define ixDP_AUX_DEBUG_B                                                        0x11
++#define ixDP_AUX_DEBUG_C                                                        0x12
++#define ixDP_AUX_DEBUG_D                                                        0x13
++#define ixDP_AUX_DEBUG_E                                                        0x14
++#define ixDP_AUX_DEBUG_F                                                        0x15
++#define ixDP_AUX_DEBUG_G                                                        0x16
++#define ixDP_AUX_DEBUG_H                                                        0x17
++#define ixDP_AUX_DEBUG_I                                                        0x18
++#define ixDP_AUX_DEBUG_J                                                        0x19
++#define ixDP_AUX_DEBUG_K                                                        0x1a
++#define ixDP_AUX_DEBUG_L                                                        0x1b
++#define ixDP_AUX_DEBUG_M                                                        0x1c
++#define ixDP_AUX_DEBUG_N                                                        0x1d
++#define ixDP_AUX_DEBUG_O                                                        0x1e
++#define ixDP_AUX_DEBUG_P                                                        0x1f
++#define ixDP_AUX_DEBUG_Q                                                        0x20
++#define mmDVO_ENABLE                                                            0x16a0
++#define mmDVO_SOURCE_SELECT                                                     0x16a1
++#define mmDVO_OUTPUT                                                            0x16a2
++#define mmDVO_CONTROL                                                           0x16a3
++#define mmDVO_CRC_EN                                                            0x16a4
++#define mmDVO_CRC2_SIG_MASK                                                     0x16a5
++#define mmDVO_CRC2_SIG_RESULT                                                   0x16a6
++#define mmDVO_FIFO_ERROR_STATUS                                                 0x16a7
++#define mmDVO_TEST_DEBUG_INDEX                                                  0x16a8
++#define mmDVO_TEST_DEBUG_DATA                                                   0x16a9
++#define mmFBC_CNTL                                                              0x280
++#define mmFBC_IDLE_MASK                                                         0x281
++#define mmFBC_IDLE_FORCE_CLEAR_MASK                                             0x282
++#define mmFBC_START_STOP_DELAY                                                  0x283
++#define mmFBC_COMP_CNTL                                                         0x284
++#define mmFBC_COMP_MODE                                                         0x285
++#define mmFBC_DEBUG0                                                            0x286
++#define mmFBC_DEBUG1                                                            0x287
++#define mmFBC_DEBUG2                                                            0x288
++#define mmFBC_IND_LUT0                                                          0x289
++#define mmFBC_IND_LUT1                                                          0x28a
++#define mmFBC_IND_LUT2                                                          0x28b
++#define mmFBC_IND_LUT3                                                          0x28c
++#define mmFBC_IND_LUT4                                                          0x28d
++#define mmFBC_IND_LUT5                                                          0x28e
++#define mmFBC_IND_LUT6                                                          0x28f
++#define mmFBC_IND_LUT7                                                          0x290
++#define mmFBC_IND_LUT8                                                          0x291
++#define mmFBC_IND_LUT9                                                          0x292
++#define mmFBC_IND_LUT10                                                         0x293
++#define mmFBC_IND_LUT11                                                         0x294
++#define mmFBC_IND_LUT12                                                         0x295
++#define mmFBC_IND_LUT13                                                         0x296
++#define mmFBC_IND_LUT14                                                         0x297
++#define mmFBC_IND_LUT15                                                         0x298
++#define mmFBC_CSM_REGION_OFFSET_01                                              0x299
++#define mmFBC_CSM_REGION_OFFSET_23                                              0x29a
++#define mmFBC_CLIENT_REGION_MASK                                                0x29b
++#define mmFBC_DEBUG_COMP                                                        0x29c
++#define mmFBC_DEBUG_CSR                                                         0x29d
++#define mmFBC_DEBUG_CSR_RDATA                                                   0x29e
++#define mmFBC_DEBUG_CSR_WDATA                                                   0x29f
++#define mmFBC_DEBUG_CSR_RDATA_HI                                                0x2a0
++#define mmFBC_DEBUG_CSR_WDATA_HI                                                0x2a1
++#define mmFBC_MISC                                                              0x2a2
++#define mmFBC_STATUS                                                            0x2a3
++#define mmFBC_TEST_DEBUG_INDEX                                                  0x2a4
++#define mmFBC_TEST_DEBUG_DATA                                                   0x2a5
++#define mmFMT_CLAMP_COMPONENT_R                                                 0x1be8
++#define mmFMT0_FMT_CLAMP_COMPONENT_R                                            0x1be8
++#define mmFMT1_FMT_CLAMP_COMPONENT_R                                            0x1de8
++#define mmFMT2_FMT_CLAMP_COMPONENT_R                                            0x1fe8
++#define mmFMT3_FMT_CLAMP_COMPONENT_R                                            0x41e8
++#define mmFMT4_FMT_CLAMP_COMPONENT_R                                            0x43e8
++#define mmFMT5_FMT_CLAMP_COMPONENT_R                                            0x45e8
++#define mmFMT_CLAMP_COMPONENT_G                                                 0x1be9
++#define mmFMT0_FMT_CLAMP_COMPONENT_G                                            0x1be9
++#define mmFMT1_FMT_CLAMP_COMPONENT_G                                            0x1de9
++#define mmFMT2_FMT_CLAMP_COMPONENT_G                                            0x1fe9
++#define mmFMT3_FMT_CLAMP_COMPONENT_G                                            0x41e9
++#define mmFMT4_FMT_CLAMP_COMPONENT_G                                            0x43e9
++#define mmFMT5_FMT_CLAMP_COMPONENT_G                                            0x45e9
++#define mmFMT_CLAMP_COMPONENT_B                                                 0x1bea
++#define mmFMT0_FMT_CLAMP_COMPONENT_B                                            0x1bea
++#define mmFMT1_FMT_CLAMP_COMPONENT_B                                            0x1dea
++#define mmFMT2_FMT_CLAMP_COMPONENT_B                                            0x1fea
++#define mmFMT3_FMT_CLAMP_COMPONENT_B                                            0x41ea
++#define mmFMT4_FMT_CLAMP_COMPONENT_B                                            0x43ea
++#define mmFMT5_FMT_CLAMP_COMPONENT_B                                            0x45ea
++#define mmFMT_DYNAMIC_EXP_CNTL                                                  0x1bed
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                             0x1bed
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                             0x1ded
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                             0x1fed
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                             0x41ed
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                             0x43ed
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                             0x45ed
++#define mmFMT_CONTROL                                                           0x1bee
++#define mmFMT0_FMT_CONTROL                                                      0x1bee
++#define mmFMT1_FMT_CONTROL                                                      0x1dee
++#define mmFMT2_FMT_CONTROL                                                      0x1fee
++#define mmFMT3_FMT_CONTROL                                                      0x41ee
++#define mmFMT4_FMT_CONTROL                                                      0x43ee
++#define mmFMT5_FMT_CONTROL                                                      0x45ee
++#define mmFMT_BIT_DEPTH_CONTROL                                                 0x1bf2
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                            0x1bf2
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                            0x1df2
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                            0x1ff2
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                            0x41f2
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL                                            0x43f2
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL                                            0x45f2
++#define mmFMT_DITHER_RAND_R_SEED                                                0x1bf3
++#define mmFMT0_FMT_DITHER_RAND_R_SEED                                           0x1bf3
++#define mmFMT1_FMT_DITHER_RAND_R_SEED                                           0x1df3
++#define mmFMT2_FMT_DITHER_RAND_R_SEED                                           0x1ff3
++#define mmFMT3_FMT_DITHER_RAND_R_SEED                                           0x41f3
++#define mmFMT4_FMT_DITHER_RAND_R_SEED                                           0x43f3
++#define mmFMT5_FMT_DITHER_RAND_R_SEED                                           0x45f3
++#define mmFMT_DITHER_RAND_G_SEED                                                0x1bf4
++#define mmFMT0_FMT_DITHER_RAND_G_SEED                                           0x1bf4
++#define mmFMT1_FMT_DITHER_RAND_G_SEED                                           0x1df4
++#define mmFMT2_FMT_DITHER_RAND_G_SEED                                           0x1ff4
++#define mmFMT3_FMT_DITHER_RAND_G_SEED                                           0x41f4
++#define mmFMT4_FMT_DITHER_RAND_G_SEED                                           0x43f4
++#define mmFMT5_FMT_DITHER_RAND_G_SEED                                           0x45f4
++#define mmFMT_DITHER_RAND_B_SEED                                                0x1bf5
++#define mmFMT0_FMT_DITHER_RAND_B_SEED                                           0x1bf5
++#define mmFMT1_FMT_DITHER_RAND_B_SEED                                           0x1df5
++#define mmFMT2_FMT_DITHER_RAND_B_SEED                                           0x1ff5
++#define mmFMT3_FMT_DITHER_RAND_B_SEED                                           0x41f5
++#define mmFMT4_FMT_DITHER_RAND_B_SEED                                           0x43f5
++#define mmFMT5_FMT_DITHER_RAND_B_SEED                                           0x45f5
++#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL                                   0x1bf6
++#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1bf6
++#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1df6
++#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1ff6
++#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x41f6
++#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x43f6
++#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x45f6
++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                     0x1bf7
++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1bf7
++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1df7
++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1ff7
++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x41f7
++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x43f7
++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x45f7
++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                     0x1bf8
++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1bf8
++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1df8
++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1ff8
++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x41f8
++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x43f8
++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x45f8
++#define mmFMT_CLAMP_CNTL                                                        0x1bf9
++#define mmFMT0_FMT_CLAMP_CNTL                                                   0x1bf9
++#define mmFMT1_FMT_CLAMP_CNTL                                                   0x1df9
++#define mmFMT2_FMT_CLAMP_CNTL                                                   0x1ff9
++#define mmFMT3_FMT_CLAMP_CNTL                                                   0x41f9
++#define mmFMT4_FMT_CLAMP_CNTL                                                   0x43f9
++#define mmFMT5_FMT_CLAMP_CNTL                                                   0x45f9
++#define mmFMT_CRC_CNTL                                                          0x1bfa
++#define mmFMT0_FMT_CRC_CNTL                                                     0x1bfa
++#define mmFMT1_FMT_CRC_CNTL                                                     0x1dfa
++#define mmFMT2_FMT_CRC_CNTL                                                     0x1ffa
++#define mmFMT3_FMT_CRC_CNTL                                                     0x41fa
++#define mmFMT4_FMT_CRC_CNTL                                                     0x43fa
++#define mmFMT5_FMT_CRC_CNTL                                                     0x45fa
++#define mmFMT_CRC_SIG_RED_GREEN_MASK                                            0x1bfb
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1bfb
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1dfb
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1ffb
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                                       0x41fb
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                                       0x43fb
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                                       0x45fb
++#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK                                         0x1bfc
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1bfc
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1dfc
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1ffc
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x41fc
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x43fc
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x45fc
++#define mmFMT_CRC_SIG_RED_GREEN                                                 0x1bfd
++#define mmFMT0_FMT_CRC_SIG_RED_GREEN                                            0x1bfd
++#define mmFMT1_FMT_CRC_SIG_RED_GREEN                                            0x1dfd
++#define mmFMT2_FMT_CRC_SIG_RED_GREEN                                            0x1ffd
++#define mmFMT3_FMT_CRC_SIG_RED_GREEN                                            0x41fd
++#define mmFMT4_FMT_CRC_SIG_RED_GREEN                                            0x43fd
++#define mmFMT5_FMT_CRC_SIG_RED_GREEN                                            0x45fd
++#define mmFMT_CRC_SIG_BLUE_CONTROL                                              0x1bfe
++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL                                         0x1bfe
++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL                                         0x1dfe
++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL                                         0x1ffe
++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                                         0x41fe
++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL                                         0x43fe
++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                                         0x45fe
++#define mmFMT_DEBUG_CNTL                                                        0x1bff
++#define mmFMT0_FMT_DEBUG_CNTL                                                   0x1bff
++#define mmFMT1_FMT_DEBUG_CNTL                                                   0x1dff
++#define mmFMT2_FMT_DEBUG_CNTL                                                   0x1fff
++#define mmFMT3_FMT_DEBUG_CNTL                                                   0x41ff
++#define mmFMT4_FMT_DEBUG_CNTL                                                   0x43ff
++#define mmFMT5_FMT_DEBUG_CNTL                                                   0x45ff
++#define mmFMT_TEST_DEBUG_INDEX                                                  0x1beb
++#define mmFMT0_FMT_TEST_DEBUG_INDEX                                             0x1beb
++#define mmFMT1_FMT_TEST_DEBUG_INDEX                                             0x1deb
++#define mmFMT2_FMT_TEST_DEBUG_INDEX                                             0x1feb
++#define mmFMT3_FMT_TEST_DEBUG_INDEX                                             0x41eb
++#define mmFMT4_FMT_TEST_DEBUG_INDEX                                             0x43eb
++#define mmFMT5_FMT_TEST_DEBUG_INDEX                                             0x45eb
++#define mmFMT_TEST_DEBUG_DATA                                                   0x1bec
++#define mmFMT0_FMT_TEST_DEBUG_DATA                                              0x1bec
++#define mmFMT1_FMT_TEST_DEBUG_DATA                                              0x1dec
++#define mmFMT2_FMT_TEST_DEBUG_DATA                                              0x1fec
++#define mmFMT3_FMT_TEST_DEBUG_DATA                                              0x41ec
++#define mmFMT4_FMT_TEST_DEBUG_DATA                                              0x43ec
++#define mmFMT5_FMT_TEST_DEBUG_DATA                                              0x45ec
++#define ixFMT_DEBUG0                                                            0x1
++#define ixFMT_DEBUG1                                                            0x2
++#define ixFMT_DEBUG2                                                            0x3
++#define ixFMT_DEBUG_ID                                                          0x0
++#define mmLB_DATA_FORMAT                                                        0x1ac0
++#define mmLB0_LB_DATA_FORMAT                                                    0x1ac0
++#define mmLB1_LB_DATA_FORMAT                                                    0x1cc0
++#define mmLB2_LB_DATA_FORMAT                                                    0x1ec0
++#define mmLB3_LB_DATA_FORMAT                                                    0x40c0
++#define mmLB4_LB_DATA_FORMAT                                                    0x42c0
++#define mmLB5_LB_DATA_FORMAT                                                    0x44c0
++#define mmLB_MEMORY_CTRL                                                        0x1ac1
++#define mmLB0_LB_MEMORY_CTRL                                                    0x1ac1
++#define mmLB1_LB_MEMORY_CTRL                                                    0x1cc1
++#define mmLB2_LB_MEMORY_CTRL                                                    0x1ec1
++#define mmLB3_LB_MEMORY_CTRL                                                    0x40c1
++#define mmLB4_LB_MEMORY_CTRL                                                    0x42c1
++#define mmLB5_LB_MEMORY_CTRL                                                    0x44c1
++#define mmLB_MEMORY_SIZE_STATUS                                                 0x1ac2
++#define mmLB0_LB_MEMORY_SIZE_STATUS                                             0x1ac2
++#define mmLB1_LB_MEMORY_SIZE_STATUS                                             0x1cc2
++#define mmLB2_LB_MEMORY_SIZE_STATUS                                             0x1ec2
++#define mmLB3_LB_MEMORY_SIZE_STATUS                                             0x40c2
++#define mmLB4_LB_MEMORY_SIZE_STATUS                                             0x42c2
++#define mmLB5_LB_MEMORY_SIZE_STATUS                                             0x44c2
++#define mmLB_DESKTOP_HEIGHT                                                     0x1ac3
++#define mmLB0_LB_DESKTOP_HEIGHT                                                 0x1ac3
++#define mmLB1_LB_DESKTOP_HEIGHT                                                 0x1cc3
++#define mmLB2_LB_DESKTOP_HEIGHT                                                 0x1ec3
++#define mmLB3_LB_DESKTOP_HEIGHT                                                 0x40c3
++#define mmLB4_LB_DESKTOP_HEIGHT                                                 0x42c3
++#define mmLB5_LB_DESKTOP_HEIGHT                                                 0x44c3
++#define mmLB_VLINE_START_END                                                    0x1ac4
++#define mmLB0_LB_VLINE_START_END                                                0x1ac4
++#define mmLB1_LB_VLINE_START_END                                                0x1cc4
++#define mmLB2_LB_VLINE_START_END                                                0x1ec4
++#define mmLB3_LB_VLINE_START_END                                                0x40c4
++#define mmLB4_LB_VLINE_START_END                                                0x42c4
++#define mmLB5_LB_VLINE_START_END                                                0x44c4
++#define mmLB_VLINE2_START_END                                                   0x1ac5
++#define mmLB0_LB_VLINE2_START_END                                               0x1ac5
++#define mmLB1_LB_VLINE2_START_END                                               0x1cc5
++#define mmLB2_LB_VLINE2_START_END                                               0x1ec5
++#define mmLB3_LB_VLINE2_START_END                                               0x40c5
++#define mmLB4_LB_VLINE2_START_END                                               0x42c5
++#define mmLB5_LB_VLINE2_START_END                                               0x44c5
++#define mmLB_V_COUNTER                                                          0x1ac6
++#define mmLB0_LB_V_COUNTER                                                      0x1ac6
++#define mmLB1_LB_V_COUNTER                                                      0x1cc6
++#define mmLB2_LB_V_COUNTER                                                      0x1ec6
++#define mmLB3_LB_V_COUNTER                                                      0x40c6
++#define mmLB4_LB_V_COUNTER                                                      0x42c6
++#define mmLB5_LB_V_COUNTER                                                      0x44c6
++#define mmLB_SNAPSHOT_V_COUNTER                                                 0x1ac7
++#define mmLB0_LB_SNAPSHOT_V_COUNTER                                             0x1ac7
++#define mmLB1_LB_SNAPSHOT_V_COUNTER                                             0x1cc7
++#define mmLB2_LB_SNAPSHOT_V_COUNTER                                             0x1ec7
++#define mmLB3_LB_SNAPSHOT_V_COUNTER                                             0x40c7
++#define mmLB4_LB_SNAPSHOT_V_COUNTER                                             0x42c7
++#define mmLB5_LB_SNAPSHOT_V_COUNTER                                             0x44c7
++#define mmLB_INTERRUPT_MASK                                                     0x1ac8
++#define mmLB0_LB_INTERRUPT_MASK                                                 0x1ac8
++#define mmLB1_LB_INTERRUPT_MASK                                                 0x1cc8
++#define mmLB2_LB_INTERRUPT_MASK                                                 0x1ec8
++#define mmLB3_LB_INTERRUPT_MASK                                                 0x40c8
++#define mmLB4_LB_INTERRUPT_MASK                                                 0x42c8
++#define mmLB5_LB_INTERRUPT_MASK                                                 0x44c8
++#define mmLB_VLINE_STATUS                                                       0x1ac9
++#define mmLB0_LB_VLINE_STATUS                                                   0x1ac9
++#define mmLB1_LB_VLINE_STATUS                                                   0x1cc9
++#define mmLB2_LB_VLINE_STATUS                                                   0x1ec9
++#define mmLB3_LB_VLINE_STATUS                                                   0x40c9
++#define mmLB4_LB_VLINE_STATUS                                                   0x42c9
++#define mmLB5_LB_VLINE_STATUS                                                   0x44c9
++#define mmLB_VLINE2_STATUS                                                      0x1aca
++#define mmLB0_LB_VLINE2_STATUS                                                  0x1aca
++#define mmLB1_LB_VLINE2_STATUS                                                  0x1cca
++#define mmLB2_LB_VLINE2_STATUS                                                  0x1eca
++#define mmLB3_LB_VLINE2_STATUS                                                  0x40ca
++#define mmLB4_LB_VLINE2_STATUS                                                  0x42ca
++#define mmLB5_LB_VLINE2_STATUS                                                  0x44ca
++#define mmLB_VBLANK_STATUS                                                      0x1acb
++#define mmLB0_LB_VBLANK_STATUS                                                  0x1acb
++#define mmLB1_LB_VBLANK_STATUS                                                  0x1ccb
++#define mmLB2_LB_VBLANK_STATUS                                                  0x1ecb
++#define mmLB3_LB_VBLANK_STATUS                                                  0x40cb
++#define mmLB4_LB_VBLANK_STATUS                                                  0x42cb
++#define mmLB5_LB_VBLANK_STATUS                                                  0x44cb
++#define mmLB_SYNC_RESET_SEL                                                     0x1acc
++#define mmLB0_LB_SYNC_RESET_SEL                                                 0x1acc
++#define mmLB1_LB_SYNC_RESET_SEL                                                 0x1ccc
++#define mmLB2_LB_SYNC_RESET_SEL                                                 0x1ecc
++#define mmLB3_LB_SYNC_RESET_SEL                                                 0x40cc
++#define mmLB4_LB_SYNC_RESET_SEL                                                 0x42cc
++#define mmLB5_LB_SYNC_RESET_SEL                                                 0x44cc
++#define mmLB_BLACK_KEYER_R_CR                                                   0x1acd
++#define mmLB0_LB_BLACK_KEYER_R_CR                                               0x1acd
++#define mmLB1_LB_BLACK_KEYER_R_CR                                               0x1ccd
++#define mmLB2_LB_BLACK_KEYER_R_CR                                               0x1ecd
++#define mmLB3_LB_BLACK_KEYER_R_CR                                               0x40cd
++#define mmLB4_LB_BLACK_KEYER_R_CR                                               0x42cd
++#define mmLB5_LB_BLACK_KEYER_R_CR                                               0x44cd
++#define mmLB_BLACK_KEYER_G_Y                                                    0x1ace
++#define mmLB0_LB_BLACK_KEYER_G_Y                                                0x1ace
++#define mmLB1_LB_BLACK_KEYER_G_Y                                                0x1cce
++#define mmLB2_LB_BLACK_KEYER_G_Y                                                0x1ece
++#define mmLB3_LB_BLACK_KEYER_G_Y                                                0x40ce
++#define mmLB4_LB_BLACK_KEYER_G_Y                                                0x42ce
++#define mmLB5_LB_BLACK_KEYER_G_Y                                                0x44ce
++#define mmLB_BLACK_KEYER_B_CB                                                   0x1acf
++#define mmLB0_LB_BLACK_KEYER_B_CB                                               0x1acf
++#define mmLB1_LB_BLACK_KEYER_B_CB                                               0x1ccf
++#define mmLB2_LB_BLACK_KEYER_B_CB                                               0x1ecf
++#define mmLB3_LB_BLACK_KEYER_B_CB                                               0x40cf
++#define mmLB4_LB_BLACK_KEYER_B_CB                                               0x42cf
++#define mmLB5_LB_BLACK_KEYER_B_CB                                               0x44cf
++#define mmLB_KEYER_COLOR_CTRL                                                   0x1ad0
++#define mmLB0_LB_KEYER_COLOR_CTRL                                               0x1ad0
++#define mmLB1_LB_KEYER_COLOR_CTRL                                               0x1cd0
++#define mmLB2_LB_KEYER_COLOR_CTRL                                               0x1ed0
++#define mmLB3_LB_KEYER_COLOR_CTRL                                               0x40d0
++#define mmLB4_LB_KEYER_COLOR_CTRL                                               0x42d0
++#define mmLB5_LB_KEYER_COLOR_CTRL                                               0x44d0
++#define mmLB_KEYER_COLOR_R_CR                                                   0x1ad1
++#define mmLB0_LB_KEYER_COLOR_R_CR                                               0x1ad1
++#define mmLB1_LB_KEYER_COLOR_R_CR                                               0x1cd1
++#define mmLB2_LB_KEYER_COLOR_R_CR                                               0x1ed1
++#define mmLB3_LB_KEYER_COLOR_R_CR                                               0x40d1
++#define mmLB4_LB_KEYER_COLOR_R_CR                                               0x42d1
++#define mmLB5_LB_KEYER_COLOR_R_CR                                               0x44d1
++#define mmLB_KEYER_COLOR_G_Y                                                    0x1ad2
++#define mmLB0_LB_KEYER_COLOR_G_Y                                                0x1ad2
++#define mmLB1_LB_KEYER_COLOR_G_Y                                                0x1cd2
++#define mmLB2_LB_KEYER_COLOR_G_Y                                                0x1ed2
++#define mmLB3_LB_KEYER_COLOR_G_Y                                                0x40d2
++#define mmLB4_LB_KEYER_COLOR_G_Y                                                0x42d2
++#define mmLB5_LB_KEYER_COLOR_G_Y                                                0x44d2
++#define mmLB_KEYER_COLOR_B_CB                                                   0x1ad3
++#define mmLB0_LB_KEYER_COLOR_B_CB                                               0x1ad3
++#define mmLB1_LB_KEYER_COLOR_B_CB                                               0x1cd3
++#define mmLB2_LB_KEYER_COLOR_B_CB                                               0x1ed3
++#define mmLB3_LB_KEYER_COLOR_B_CB                                               0x40d3
++#define mmLB4_LB_KEYER_COLOR_B_CB                                               0x42d3
++#define mmLB5_LB_KEYER_COLOR_B_CB                                               0x44d3
++#define mmLB_KEYER_COLOR_REP_R_CR                                               0x1ad4
++#define mmLB0_LB_KEYER_COLOR_REP_R_CR                                           0x1ad4
++#define mmLB1_LB_KEYER_COLOR_REP_R_CR                                           0x1cd4
++#define mmLB2_LB_KEYER_COLOR_REP_R_CR                                           0x1ed4
++#define mmLB3_LB_KEYER_COLOR_REP_R_CR                                           0x40d4
++#define mmLB4_LB_KEYER_COLOR_REP_R_CR                                           0x42d4
++#define mmLB5_LB_KEYER_COLOR_REP_R_CR                                           0x44d4
++#define mmLB_KEYER_COLOR_REP_G_Y                                                0x1ad5
++#define mmLB0_LB_KEYER_COLOR_REP_G_Y                                            0x1ad5
++#define mmLB1_LB_KEYER_COLOR_REP_G_Y                                            0x1cd5
++#define mmLB2_LB_KEYER_COLOR_REP_G_Y                                            0x1ed5
++#define mmLB3_LB_KEYER_COLOR_REP_G_Y                                            0x40d5
++#define mmLB4_LB_KEYER_COLOR_REP_G_Y                                            0x42d5
++#define mmLB5_LB_KEYER_COLOR_REP_G_Y                                            0x44d5
++#define mmLB_KEYER_COLOR_REP_B_CB                                               0x1ad6
++#define mmLB0_LB_KEYER_COLOR_REP_B_CB                                           0x1ad6
++#define mmLB1_LB_KEYER_COLOR_REP_B_CB                                           0x1cd6
++#define mmLB2_LB_KEYER_COLOR_REP_B_CB                                           0x1ed6
++#define mmLB3_LB_KEYER_COLOR_REP_B_CB                                           0x40d6
++#define mmLB4_LB_KEYER_COLOR_REP_B_CB                                           0x42d6
++#define mmLB5_LB_KEYER_COLOR_REP_B_CB                                           0x44d6
++#define mmLB_BUFFER_LEVEL_STATUS                                                0x1ad7
++#define mmLB0_LB_BUFFER_LEVEL_STATUS                                            0x1ad7
++#define mmLB1_LB_BUFFER_LEVEL_STATUS                                            0x1cd7
++#define mmLB2_LB_BUFFER_LEVEL_STATUS                                            0x1ed7
++#define mmLB3_LB_BUFFER_LEVEL_STATUS                                            0x40d7
++#define mmLB4_LB_BUFFER_LEVEL_STATUS                                            0x42d7
++#define mmLB5_LB_BUFFER_LEVEL_STATUS                                            0x44d7
++#define mmLB_BUFFER_URGENCY_CTRL                                                0x1ad8
++#define mmLB0_LB_BUFFER_URGENCY_CTRL                                            0x1ad8
++#define mmLB1_LB_BUFFER_URGENCY_CTRL                                            0x1cd8
++#define mmLB2_LB_BUFFER_URGENCY_CTRL                                            0x1ed8
++#define mmLB3_LB_BUFFER_URGENCY_CTRL                                            0x40d8
++#define mmLB4_LB_BUFFER_URGENCY_CTRL                                            0x42d8
++#define mmLB5_LB_BUFFER_URGENCY_CTRL                                            0x44d8
++#define mmLB_BUFFER_URGENCY_STATUS                                              0x1ad9
++#define mmLB0_LB_BUFFER_URGENCY_STATUS                                          0x1ad9
++#define mmLB1_LB_BUFFER_URGENCY_STATUS                                          0x1cd9
++#define mmLB2_LB_BUFFER_URGENCY_STATUS                                          0x1ed9
++#define mmLB3_LB_BUFFER_URGENCY_STATUS                                          0x40d9
++#define mmLB4_LB_BUFFER_URGENCY_STATUS                                          0x42d9
++#define mmLB5_LB_BUFFER_URGENCY_STATUS                                          0x44d9
++#define mmLB_BUFFER_STATUS                                                      0x1ada
++#define mmLB0_LB_BUFFER_STATUS                                                  0x1ada
++#define mmLB1_LB_BUFFER_STATUS                                                  0x1cda
++#define mmLB2_LB_BUFFER_STATUS                                                  0x1eda
++#define mmLB3_LB_BUFFER_STATUS                                                  0x40da
++#define mmLB4_LB_BUFFER_STATUS                                                  0x42da
++#define mmLB5_LB_BUFFER_STATUS                                                  0x44da
++#define mmLB_NO_OUTSTANDING_REQ_STATUS                                          0x1adc
++#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1adc
++#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1cdc
++#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1edc
++#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                                      0x40dc
++#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                                      0x42dc
++#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                                      0x44dc
++#define mmMVP_AFR_FLIP_MODE                                                     0x1ae0
++#define mmLB0_MVP_AFR_FLIP_MODE                                                 0x1ae0
++#define mmLB1_MVP_AFR_FLIP_MODE                                                 0x1ce0
++#define mmLB2_MVP_AFR_FLIP_MODE                                                 0x1ee0
++#define mmLB3_MVP_AFR_FLIP_MODE                                                 0x40e0
++#define mmLB4_MVP_AFR_FLIP_MODE                                                 0x42e0
++#define mmLB5_MVP_AFR_FLIP_MODE                                                 0x44e0
++#define mmMVP_AFR_FLIP_FIFO_CNTL                                                0x1ae1
++#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ae1
++#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ce1
++#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ee1
++#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL                                            0x40e1
++#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL                                            0x42e1
++#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL                                            0x44e1
++#define mmMVP_FLIP_LINE_NUM_INSERT                                              0x1ae2
++#define mmLB0_MVP_FLIP_LINE_NUM_INSERT                                          0x1ae2
++#define mmLB1_MVP_FLIP_LINE_NUM_INSERT                                          0x1ce2
++#define mmLB2_MVP_FLIP_LINE_NUM_INSERT                                          0x1ee2
++#define mmLB3_MVP_FLIP_LINE_NUM_INSERT                                          0x40e2
++#define mmLB4_MVP_FLIP_LINE_NUM_INSERT                                          0x42e2
++#define mmLB5_MVP_FLIP_LINE_NUM_INSERT                                          0x44e2
++#define mmDC_MVP_LB_CONTROL                                                     0x1ae3
++#define mmLB0_DC_MVP_LB_CONTROL                                                 0x1ae3
++#define mmLB1_DC_MVP_LB_CONTROL                                                 0x1ce3
++#define mmLB2_DC_MVP_LB_CONTROL                                                 0x1ee3
++#define mmLB3_DC_MVP_LB_CONTROL                                                 0x40e3
++#define mmLB4_DC_MVP_LB_CONTROL                                                 0x42e3
++#define mmLB5_DC_MVP_LB_CONTROL                                                 0x44e3
++#define mmLB_DEBUG                                                              0x1ae4
++#define mmLB0_LB_DEBUG                                                          0x1ae4
++#define mmLB1_LB_DEBUG                                                          0x1ce4
++#define mmLB2_LB_DEBUG                                                          0x1ee4
++#define mmLB3_LB_DEBUG                                                          0x40e4
++#define mmLB4_LB_DEBUG                                                          0x42e4
++#define mmLB5_LB_DEBUG                                                          0x44e4
++#define mmLB_DEBUG2                                                             0x1ae5
++#define mmLB0_LB_DEBUG2                                                         0x1ae5
++#define mmLB1_LB_DEBUG2                                                         0x1ce5
++#define mmLB2_LB_DEBUG2                                                         0x1ee5
++#define mmLB3_LB_DEBUG2                                                         0x40e5
++#define mmLB4_LB_DEBUG2                                                         0x42e5
++#define mmLB5_LB_DEBUG2                                                         0x44e5
++#define mmLB_DEBUG3                                                             0x1ae6
++#define mmLB0_LB_DEBUG3                                                         0x1ae6
++#define mmLB1_LB_DEBUG3                                                         0x1ce6
++#define mmLB2_LB_DEBUG3                                                         0x1ee6
++#define mmLB3_LB_DEBUG3                                                         0x40e6
++#define mmLB4_LB_DEBUG3                                                         0x42e6
++#define mmLB5_LB_DEBUG3                                                         0x44e6
++#define mmLB_TEST_DEBUG_INDEX                                                   0x1afe
++#define mmLB0_LB_TEST_DEBUG_INDEX                                               0x1afe
++#define mmLB1_LB_TEST_DEBUG_INDEX                                               0x1cfe
++#define mmLB2_LB_TEST_DEBUG_INDEX                                               0x1efe
++#define mmLB3_LB_TEST_DEBUG_INDEX                                               0x40fe
++#define mmLB4_LB_TEST_DEBUG_INDEX                                               0x42fe
++#define mmLB5_LB_TEST_DEBUG_INDEX                                               0x44fe
++#define mmLB_TEST_DEBUG_DATA                                                    0x1aff
++#define mmLB0_LB_TEST_DEBUG_DATA                                                0x1aff
++#define mmLB1_LB_TEST_DEBUG_DATA                                                0x1cff
++#define mmLB2_LB_TEST_DEBUG_DATA                                                0x1eff
++#define mmLB3_LB_TEST_DEBUG_DATA                                                0x40ff
++#define mmLB4_LB_TEST_DEBUG_DATA                                                0x42ff
++#define mmLB5_LB_TEST_DEBUG_DATA                                                0x44ff
++#define mmLBV_DATA_FORMAT                                                       0x463c
++#define mmLBV_MEMORY_CTRL                                                       0x463d
++#define mmLBV_MEMORY_SIZE_STATUS                                                0x463e
++#define mmLBV_DESKTOP_HEIGHT                                                    0x463f
++#define mmLBV_VLINE_START_END                                                   0x4640
++#define mmLBV_VLINE2_START_END                                                  0x4641
++#define mmLBV_V_COUNTER                                                         0x4642
++#define mmLBV_SNAPSHOT_V_COUNTER                                                0x4643
++#define mmLBV_V_COUNTER_CHROMA                                                  0x4644
++#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA                                         0x4645
++#define mmLBV_INTERRUPT_MASK                                                    0x4646
++#define mmLBV_VLINE_STATUS                                                      0x4647
++#define mmLBV_VLINE2_STATUS                                                     0x4648
++#define mmLBV_VBLANK_STATUS                                                     0x4649
++#define mmLBV_SYNC_RESET_SEL                                                    0x464a
++#define mmLBV_BLACK_KEYER_R_CR                                                  0x464b
++#define mmLBV_BLACK_KEYER_G_Y                                                   0x464c
++#define mmLBV_BLACK_KEYER_B_CB                                                  0x464d
++#define mmLBV_KEYER_COLOR_CTRL                                                  0x464e
++#define mmLBV_KEYER_COLOR_R_CR                                                  0x464f
++#define mmLBV_KEYER_COLOR_G_Y                                                   0x4650
++#define mmLBV_KEYER_COLOR_B_CB                                                  0x4651
++#define mmLBV_KEYER_COLOR_REP_R_CR                                              0x4652
++#define mmLBV_KEYER_COLOR_REP_G_Y                                               0x4653
++#define mmLBV_KEYER_COLOR_REP_B_CB                                              0x4654
++#define mmLBV_BUFFER_LEVEL_STATUS                                               0x4655
++#define mmLBV_BUFFER_URGENCY_CTRL                                               0x4656
++#define mmLBV_BUFFER_URGENCY_STATUS                                             0x4657
++#define mmLBV_BUFFER_STATUS                                                     0x4658
++#define mmLBV_NO_OUTSTANDING_REQ_STATUS                                         0x4659
++#define mmLBV_DEBUG                                                             0x465a
++#define mmLBV_DEBUG2                                                            0x465b
++#define mmLBV_DEBUG3                                                            0x465c
++#define mmLBV_TEST_DEBUG_INDEX                                                  0x4666
++#define mmLBV_TEST_DEBUG_DATA                                                   0x4667
++#define mmMVP_CONTROL1                                                          0x2ac
++#define mmMVP_CONTROL2                                                          0x2ad
++#define mmMVP_FIFO_CONTROL                                                      0x2ae
++#define mmMVP_FIFO_STATUS                                                       0x2af
++#define mmMVP_SLAVE_STATUS                                                      0x2b0
++#define mmMVP_INBAND_CNTL_CAP                                                   0x2b1
++#define mmMVP_BLACK_KEYER                                                       0x2b2
++#define mmMVP_CRC_CNTL                                                          0x2b3
++#define mmMVP_CRC_RESULT_BLUE_GREEN                                             0x2b4
++#define mmMVP_CRC_RESULT_RED                                                    0x2b5
++#define mmMVP_CONTROL3                                                          0x2b6
++#define mmMVP_RECEIVE_CNT_CNTL1                                                 0x2b7
++#define mmMVP_RECEIVE_CNT_CNTL2                                                 0x2b8
++#define mmMVP_DEBUG                                                             0x2bb
++#define mmMVP_TEST_DEBUG_INDEX                                                  0x2b9
++#define mmMVP_TEST_DEBUG_DATA                                                   0x2ba
++#define ixMVP_DEBUG_12                                                          0xc
++#define ixMVP_DEBUG_13                                                          0xd
++#define ixMVP_DEBUG_14                                                          0xe
++#define ixMVP_DEBUG_15                                                          0xf
++#define ixMVP_DEBUG_16                                                          0x10
++#define ixMVP_DEBUG_17                                                          0x11
++#define mmSCL_COEF_RAM_SELECT                                                   0x1b40
++#define mmSCL0_SCL_COEF_RAM_SELECT                                              0x1b40
++#define mmSCL1_SCL_COEF_RAM_SELECT                                              0x1d40
++#define mmSCL2_SCL_COEF_RAM_SELECT                                              0x1f40
++#define mmSCL3_SCL_COEF_RAM_SELECT                                              0x4140
++#define mmSCL4_SCL_COEF_RAM_SELECT                                              0x4340
++#define mmSCL5_SCL_COEF_RAM_SELECT                                              0x4540
++#define mmSCL_COEF_RAM_TAP_DATA                                                 0x1b41
++#define mmSCL0_SCL_COEF_RAM_TAP_DATA                                            0x1b41
++#define mmSCL1_SCL_COEF_RAM_TAP_DATA                                            0x1d41
++#define mmSCL2_SCL_COEF_RAM_TAP_DATA                                            0x1f41
++#define mmSCL3_SCL_COEF_RAM_TAP_DATA                                            0x4141
++#define mmSCL4_SCL_COEF_RAM_TAP_DATA                                            0x4341
++#define mmSCL5_SCL_COEF_RAM_TAP_DATA                                            0x4541
++#define mmSCL_MODE                                                              0x1b42
++#define mmSCL0_SCL_MODE                                                         0x1b42
++#define mmSCL1_SCL_MODE                                                         0x1d42
++#define mmSCL2_SCL_MODE                                                         0x1f42
++#define mmSCL3_SCL_MODE                                                         0x4142
++#define mmSCL4_SCL_MODE                                                         0x4342
++#define mmSCL5_SCL_MODE                                                         0x4542
++#define mmSCL_TAP_CONTROL                                                       0x1b43
++#define mmSCL0_SCL_TAP_CONTROL                                                  0x1b43
++#define mmSCL1_SCL_TAP_CONTROL                                                  0x1d43
++#define mmSCL2_SCL_TAP_CONTROL                                                  0x1f43
++#define mmSCL3_SCL_TAP_CONTROL                                                  0x4143
++#define mmSCL4_SCL_TAP_CONTROL                                                  0x4343
++#define mmSCL5_SCL_TAP_CONTROL                                                  0x4543
++#define mmSCL_CONTROL                                                           0x1b44
++#define mmSCL0_SCL_CONTROL                                                      0x1b44
++#define mmSCL1_SCL_CONTROL                                                      0x1d44
++#define mmSCL2_SCL_CONTROL                                                      0x1f44
++#define mmSCL3_SCL_CONTROL                                                      0x4144
++#define mmSCL4_SCL_CONTROL                                                      0x4344
++#define mmSCL5_SCL_CONTROL                                                      0x4544
++#define mmSCL_BYPASS_CONTROL                                                    0x1b45
++#define mmSCL0_SCL_BYPASS_CONTROL                                               0x1b45
++#define mmSCL1_SCL_BYPASS_CONTROL                                               0x1d45
++#define mmSCL2_SCL_BYPASS_CONTROL                                               0x1f45
++#define mmSCL3_SCL_BYPASS_CONTROL                                               0x4145
++#define mmSCL4_SCL_BYPASS_CONTROL                                               0x4345
++#define mmSCL5_SCL_BYPASS_CONTROL                                               0x4545
++#define mmSCL_MANUAL_REPLICATE_CONTROL                                          0x1b46
++#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL                                     0x1b46
++#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL                                     0x1d46
++#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL                                     0x1f46
++#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                                     0x4146
++#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                                     0x4346
++#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                                     0x4546
++#define mmSCL_AUTOMATIC_MODE_CONTROL                                            0x1b47
++#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL                                       0x1b47
++#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL                                       0x1d47
++#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL                                       0x1f47
++#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                                       0x4147
++#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                                       0x4347
++#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                                       0x4547
++#define mmSCL_HORZ_FILTER_CONTROL                                               0x1b48
++#define mmSCL0_SCL_HORZ_FILTER_CONTROL                                          0x1b48
++#define mmSCL1_SCL_HORZ_FILTER_CONTROL                                          0x1d48
++#define mmSCL2_SCL_HORZ_FILTER_CONTROL                                          0x1f48
++#define mmSCL3_SCL_HORZ_FILTER_CONTROL                                          0x4148
++#define mmSCL4_SCL_HORZ_FILTER_CONTROL                                          0x4348
++#define mmSCL5_SCL_HORZ_FILTER_CONTROL                                          0x4548
++#define mmSCL_HORZ_FILTER_SCALE_RATIO                                           0x1b49
++#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1b49
++#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1d49
++#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1f49
++#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4149
++#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4349
++#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4549
++#define mmSCL_HORZ_FILTER_INIT                                                  0x1b4a
++#define mmSCL0_SCL_HORZ_FILTER_INIT                                             0x1b4a
++#define mmSCL1_SCL_HORZ_FILTER_INIT                                             0x1d4a
++#define mmSCL2_SCL_HORZ_FILTER_INIT                                             0x1f4a
++#define mmSCL3_SCL_HORZ_FILTER_INIT                                             0x414a
++#define mmSCL4_SCL_HORZ_FILTER_INIT                                             0x434a
++#define mmSCL5_SCL_HORZ_FILTER_INIT                                             0x454a
++#define mmSCL_VERT_FILTER_CONTROL                                               0x1b4b
++#define mmSCL0_SCL_VERT_FILTER_CONTROL                                          0x1b4b
++#define mmSCL1_SCL_VERT_FILTER_CONTROL                                          0x1d4b
++#define mmSCL2_SCL_VERT_FILTER_CONTROL                                          0x1f4b
++#define mmSCL3_SCL_VERT_FILTER_CONTROL                                          0x414b
++#define mmSCL4_SCL_VERT_FILTER_CONTROL                                          0x434b
++#define mmSCL5_SCL_VERT_FILTER_CONTROL                                          0x454b
++#define mmSCL_VERT_FILTER_SCALE_RATIO                                           0x1b4c
++#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO                                      0x1b4c
++#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO                                      0x1d4c
++#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO                                      0x1f4c
++#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                                      0x414c
++#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                                      0x434c
++#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                                      0x454c
++#define mmSCL_VERT_FILTER_INIT                                                  0x1b4d
++#define mmSCL0_SCL_VERT_FILTER_INIT                                             0x1b4d
++#define mmSCL1_SCL_VERT_FILTER_INIT                                             0x1d4d
++#define mmSCL2_SCL_VERT_FILTER_INIT                                             0x1f4d
++#define mmSCL3_SCL_VERT_FILTER_INIT                                             0x414d
++#define mmSCL4_SCL_VERT_FILTER_INIT                                             0x434d
++#define mmSCL5_SCL_VERT_FILTER_INIT                                             0x454d
++#define mmSCL_VERT_FILTER_INIT_BOT                                              0x1b4e
++#define mmSCL0_SCL_VERT_FILTER_INIT_BOT                                         0x1b4e
++#define mmSCL1_SCL_VERT_FILTER_INIT_BOT                                         0x1d4e
++#define mmSCL2_SCL_VERT_FILTER_INIT_BOT                                         0x1f4e
++#define mmSCL3_SCL_VERT_FILTER_INIT_BOT                                         0x414e
++#define mmSCL4_SCL_VERT_FILTER_INIT_BOT                                         0x434e
++#define mmSCL5_SCL_VERT_FILTER_INIT_BOT                                         0x454e
++#define mmSCL_ROUND_OFFSET                                                      0x1b4f
++#define mmSCL0_SCL_ROUND_OFFSET                                                 0x1b4f
++#define mmSCL1_SCL_ROUND_OFFSET                                                 0x1d4f
++#define mmSCL2_SCL_ROUND_OFFSET                                                 0x1f4f
++#define mmSCL3_SCL_ROUND_OFFSET                                                 0x414f
++#define mmSCL4_SCL_ROUND_OFFSET                                                 0x434f
++#define mmSCL5_SCL_ROUND_OFFSET                                                 0x454f
++#define mmSCL_UPDATE                                                            0x1b51
++#define mmSCL0_SCL_UPDATE                                                       0x1b51
++#define mmSCL1_SCL_UPDATE                                                       0x1d51
++#define mmSCL2_SCL_UPDATE                                                       0x1f51
++#define mmSCL3_SCL_UPDATE                                                       0x4151
++#define mmSCL4_SCL_UPDATE                                                       0x4351
++#define mmSCL5_SCL_UPDATE                                                       0x4551
++#define mmSCL_F_SHARP_CONTROL                                                   0x1b53
++#define mmSCL0_SCL_F_SHARP_CONTROL                                              0x1b53
++#define mmSCL1_SCL_F_SHARP_CONTROL                                              0x1d53
++#define mmSCL2_SCL_F_SHARP_CONTROL                                              0x1f53
++#define mmSCL3_SCL_F_SHARP_CONTROL                                              0x4153
++#define mmSCL4_SCL_F_SHARP_CONTROL                                              0x4353
++#define mmSCL5_SCL_F_SHARP_CONTROL                                              0x4553
++#define mmSCL_ALU_CONTROL                                                       0x1b54
++#define mmSCL0_SCL_ALU_CONTROL                                                  0x1b54
++#define mmSCL1_SCL_ALU_CONTROL                                                  0x1d54
++#define mmSCL2_SCL_ALU_CONTROL                                                  0x1f54
++#define mmSCL3_SCL_ALU_CONTROL                                                  0x4154
++#define mmSCL4_SCL_ALU_CONTROL                                                  0x4354
++#define mmSCL5_SCL_ALU_CONTROL                                                  0x4554
++#define mmSCL_COEF_RAM_CONFLICT_STATUS                                          0x1b55
++#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1b55
++#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1d55
++#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1f55
++#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4155
++#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4355
++#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4555
++#define mmVIEWPORT_START_SECONDARY                                              0x1b5b
++#define mmSCL0_VIEWPORT_START_SECONDARY                                         0x1b5b
++#define mmSCL1_VIEWPORT_START_SECONDARY                                         0x1d5b
++#define mmSCL2_VIEWPORT_START_SECONDARY                                         0x1f5b
++#define mmSCL3_VIEWPORT_START_SECONDARY                                         0x415b
++#define mmSCL4_VIEWPORT_START_SECONDARY                                         0x435b
++#define mmSCL5_VIEWPORT_START_SECONDARY                                         0x455b
++#define mmVIEWPORT_START                                                        0x1b5c
++#define mmSCL0_VIEWPORT_START                                                   0x1b5c
++#define mmSCL1_VIEWPORT_START                                                   0x1d5c
++#define mmSCL2_VIEWPORT_START                                                   0x1f5c
++#define mmSCL3_VIEWPORT_START                                                   0x415c
++#define mmSCL4_VIEWPORT_START                                                   0x435c
++#define mmSCL5_VIEWPORT_START                                                   0x455c
++#define mmVIEWPORT_SIZE                                                         0x1b5d
++#define mmSCL0_VIEWPORT_SIZE                                                    0x1b5d
++#define mmSCL1_VIEWPORT_SIZE                                                    0x1d5d
++#define mmSCL2_VIEWPORT_SIZE                                                    0x1f5d
++#define mmSCL3_VIEWPORT_SIZE                                                    0x415d
++#define mmSCL4_VIEWPORT_SIZE                                                    0x435d
++#define mmSCL5_VIEWPORT_SIZE                                                    0x455d
++#define mmEXT_OVERSCAN_LEFT_RIGHT                                               0x1b5e
++#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT                                          0x1b5e
++#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT                                          0x1d5e
++#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT                                          0x1f5e
++#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                                          0x415e
++#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                                          0x435e
++#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                                          0x455e
++#define mmEXT_OVERSCAN_TOP_BOTTOM                                               0x1b5f
++#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM                                          0x1b5f
++#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM                                          0x1d5f
++#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM                                          0x1f5f
++#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                                          0x415f
++#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                                          0x435f
++#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                                          0x455f
++#define mmSCL_MODE_CHANGE_DET1                                                  0x1b60
++#define mmSCL0_SCL_MODE_CHANGE_DET1                                             0x1b60
++#define mmSCL1_SCL_MODE_CHANGE_DET1                                             0x1d60
++#define mmSCL2_SCL_MODE_CHANGE_DET1                                             0x1f60
++#define mmSCL3_SCL_MODE_CHANGE_DET1                                             0x4160
++#define mmSCL4_SCL_MODE_CHANGE_DET1                                             0x4360
++#define mmSCL5_SCL_MODE_CHANGE_DET1                                             0x4560
++#define mmSCL_MODE_CHANGE_DET2                                                  0x1b61
++#define mmSCL0_SCL_MODE_CHANGE_DET2                                             0x1b61
++#define mmSCL1_SCL_MODE_CHANGE_DET2                                             0x1d61
++#define mmSCL2_SCL_MODE_CHANGE_DET2                                             0x1f61
++#define mmSCL3_SCL_MODE_CHANGE_DET2                                             0x4161
++#define mmSCL4_SCL_MODE_CHANGE_DET2                                             0x4361
++#define mmSCL5_SCL_MODE_CHANGE_DET2                                             0x4561
++#define mmSCL_MODE_CHANGE_DET3                                                  0x1b62
++#define mmSCL0_SCL_MODE_CHANGE_DET3                                             0x1b62
++#define mmSCL1_SCL_MODE_CHANGE_DET3                                             0x1d62
++#define mmSCL2_SCL_MODE_CHANGE_DET3                                             0x1f62
++#define mmSCL3_SCL_MODE_CHANGE_DET3                                             0x4162
++#define mmSCL4_SCL_MODE_CHANGE_DET3                                             0x4362
++#define mmSCL5_SCL_MODE_CHANGE_DET3                                             0x4562
++#define mmSCL_MODE_CHANGE_MASK                                                  0x1b63
++#define mmSCL0_SCL_MODE_CHANGE_MASK                                             0x1b63
++#define mmSCL1_SCL_MODE_CHANGE_MASK                                             0x1d63
++#define mmSCL2_SCL_MODE_CHANGE_MASK                                             0x1f63
++#define mmSCL3_SCL_MODE_CHANGE_MASK                                             0x4163
++#define mmSCL4_SCL_MODE_CHANGE_MASK                                             0x4363
++#define mmSCL5_SCL_MODE_CHANGE_MASK                                             0x4563
++#define mmSCL_DEBUG2                                                            0x1b69
++#define mmSCL0_SCL_DEBUG2                                                       0x1b69
++#define mmSCL1_SCL_DEBUG2                                                       0x1d69
++#define mmSCL2_SCL_DEBUG2                                                       0x1f69
++#define mmSCL3_SCL_DEBUG2                                                       0x4169
++#define mmSCL4_SCL_DEBUG2                                                       0x4369
++#define mmSCL5_SCL_DEBUG2                                                       0x4569
++#define mmSCL_DEBUG                                                             0x1b6a
++#define mmSCL0_SCL_DEBUG                                                        0x1b6a
++#define mmSCL1_SCL_DEBUG                                                        0x1d6a
++#define mmSCL2_SCL_DEBUG                                                        0x1f6a
++#define mmSCL3_SCL_DEBUG                                                        0x416a
++#define mmSCL4_SCL_DEBUG                                                        0x436a
++#define mmSCL5_SCL_DEBUG                                                        0x456a
++#define mmSCL_TEST_DEBUG_INDEX                                                  0x1b6b
++#define mmSCL0_SCL_TEST_DEBUG_INDEX                                             0x1b6b
++#define mmSCL1_SCL_TEST_DEBUG_INDEX                                             0x1d6b
++#define mmSCL2_SCL_TEST_DEBUG_INDEX                                             0x1f6b
++#define mmSCL3_SCL_TEST_DEBUG_INDEX                                             0x416b
++#define mmSCL4_SCL_TEST_DEBUG_INDEX                                             0x436b
++#define mmSCL5_SCL_TEST_DEBUG_INDEX                                             0x456b
++#define mmSCL_TEST_DEBUG_DATA                                                   0x1b6c
++#define mmSCL0_SCL_TEST_DEBUG_DATA                                              0x1b6c
++#define mmSCL1_SCL_TEST_DEBUG_DATA                                              0x1d6c
++#define mmSCL2_SCL_TEST_DEBUG_DATA                                              0x1f6c
++#define mmSCL3_SCL_TEST_DEBUG_DATA                                              0x416c
++#define mmSCL4_SCL_TEST_DEBUG_DATA                                              0x436c
++#define mmSCL5_SCL_TEST_DEBUG_DATA                                              0x456c
++#define mmSCLV_COEF_RAM_SELECT                                                  0x4670
++#define mmSCLV_COEF_RAM_TAP_DATA                                                0x4671
++#define mmSCLV_MODE                                                             0x4672
++#define mmSCLV_TAP_CONTROL                                                      0x4673
++#define mmSCLV_CONTROL                                                          0x4674
++#define mmSCLV_MANUAL_REPLICATE_CONTROL                                         0x4675
++#define mmSCLV_AUTOMATIC_MODE_CONTROL                                           0x4676
++#define mmSCLV_HORZ_FILTER_CONTROL                                              0x4677
++#define mmSCLV_HORZ_FILTER_SCALE_RATIO                                          0x4678
++#define mmSCLV_HORZ_FILTER_INIT                                                 0x4679
++#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C                                        0x467a
++#define mmSCLV_HORZ_FILTER_INIT_C                                               0x467b
++#define mmSCLV_VERT_FILTER_CONTROL                                              0x467c
++#define mmSCLV_VERT_FILTER_SCALE_RATIO                                          0x467d
++#define mmSCLV_VERT_FILTER_INIT                                                 0x467e
++#define mmSCLV_VERT_FILTER_INIT_BOT                                             0x467f
++#define mmSCLV_VERT_FILTER_SCALE_RATIO_C                                        0x4680
++#define mmSCLV_VERT_FILTER_INIT_C                                               0x4681
++#define mmSCLV_VERT_FILTER_INIT_BOT_C                                           0x4682
++#define mmSCLV_ROUND_OFFSET                                                     0x4683
++#define mmSCLV_UPDATE                                                           0x4684
++#define mmSCLV_ALU_CONTROL                                                      0x4685
++#define mmSCLV_VIEWPORT_START                                                   0x4686
++#define mmSCLV_VIEWPORT_START_SECONDARY                                         0x4687
++#define mmSCLV_VIEWPORT_SIZE                                                    0x4688
++#define mmSCLV_VIEWPORT_START_C                                                 0x4689
++#define mmSCLV_VIEWPORT_START_SECONDARY_C                                       0x468a
++#define mmSCLV_VIEWPORT_SIZE_C                                                  0x468b
++#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT                                          0x468c
++#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM                                          0x468d
++#define mmSCLV_MODE_CHANGE_DET1                                                 0x468e
++#define mmSCLV_MODE_CHANGE_DET2                                                 0x468f
++#define mmSCLV_MODE_CHANGE_DET3                                                 0x4690
++#define mmSCLV_MODE_CHANGE_MASK                                                 0x4691
++#define mmSCLV_HORZ_FILTER_INIT_BOT                                             0x4692
++#define mmSCLV_HORZ_FILTER_INIT_BOT_C                                           0x4693
++#define mmSCLV_DEBUG2                                                           0x4694
++#define mmSCLV_DEBUG                                                            0x4695
++#define mmSCLV_TEST_DEBUG_INDEX                                                 0x4696
++#define mmSCLV_TEST_DEBUG_DATA                                                  0x4697
++#define mmCOL_MAN_UPDATE                                                        0x46a4
++#define mmCOL_MAN_INPUT_CSC_CONTROL                                             0x46a5
++#define mmINPUT_CSC_C11_C12_A                                                   0x46a6
++#define mmINPUT_CSC_C13_C14_A                                                   0x46a7
++#define mmINPUT_CSC_C21_C22_A                                                   0x46a8
++#define mmINPUT_CSC_C23_C24_A                                                   0x46a9
++#define mmINPUT_CSC_C31_C32_A                                                   0x46aa
++#define mmINPUT_CSC_C33_C34_A                                                   0x46ab
++#define mmINPUT_CSC_C11_C12_B                                                   0x46ac
++#define mmINPUT_CSC_C13_C14_B                                                   0x46ad
++#define mmINPUT_CSC_C21_C22_B                                                   0x46ae
++#define mmINPUT_CSC_C23_C24_B                                                   0x46af
++#define mmINPUT_CSC_C31_C32_B                                                   0x46b0
++#define mmINPUT_CSC_C33_C34_B                                                   0x46b1
++#define mmPRESCALE_CONTROL                                                      0x46b2
++#define mmPRESCALE_VALUES_R                                                     0x46b3
++#define mmPRESCALE_VALUES_G                                                     0x46b4
++#define mmPRESCALE_VALUES_B                                                     0x46b5
++#define mmCOL_MAN_OUTPUT_CSC_CONTROL                                            0x46b6
++#define mmOUTPUT_CSC_C11_C12_A                                                  0x46b7
++#define mmOUTPUT_CSC_C13_C14_A                                                  0x46b8
++#define mmOUTPUT_CSC_C21_C22_A                                                  0x46b9
++#define mmOUTPUT_CSC_C23_C24_A                                                  0x46ba
++#define mmOUTPUT_CSC_C31_C32_A                                                  0x46bb
++#define mmOUTPUT_CSC_C33_C34_A                                                  0x46bc
++#define mmOUTPUT_CSC_C11_C12_B                                                  0x46bd
++#define mmOUTPUT_CSC_C13_C14_B                                                  0x46be
++#define mmOUTPUT_CSC_C21_C22_B                                                  0x46bf
++#define mmOUTPUT_CSC_C23_C24_B                                                  0x46c0
++#define mmOUTPUT_CSC_C31_C32_B                                                  0x46c1
++#define mmOUTPUT_CSC_C33_C34_B                                                  0x46c2
++#define mmDENORM_CLAMP_CONTROL                                                  0x46c3
++#define mmDENORM_CLAMP_RANGE_R_CR                                               0x46c4
++#define mmDENORM_CLAMP_RANGE_G_Y                                                0x46c5
++#define mmDENORM_CLAMP_RANGE_B_CB                                               0x46c6
++#define mmCOL_MAN_FP_CONVERTED_FIELD                                            0x46c7
++#define mmGAMMA_CORR_CONTROL                                                    0x46c8
++#define mmGAMMA_CORR_LUT_INDEX                                                  0x46c9
++#define mmGAMMA_CORR_LUT_DATA                                                   0x46ca
++#define mmGAMMA_CORR_LUT_WRITE_EN_MASK                                          0x46cb
++#define mmGAMMA_CORR_CNTLA_START_CNTL                                           0x46cc
++#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL                                           0x46cd
++#define mmGAMMA_CORR_CNTLA_END_CNTL1                                            0x46ce
++#define mmGAMMA_CORR_CNTLA_END_CNTL2                                            0x46cf
++#define mmGAMMA_CORR_CNTLA_REGION_0_1                                           0x46d0
++#define mmGAMMA_CORR_CNTLA_REGION_2_3                                           0x46d1
++#define mmGAMMA_CORR_CNTLA_REGION_4_5                                           0x46d2
++#define mmGAMMA_CORR_CNTLA_REGION_6_7                                           0x46d3
++#define mmGAMMA_CORR_CNTLA_REGION_8_9                                           0x46d4
++#define mmGAMMA_CORR_CNTLA_REGION_10_11                                         0x46d5
++#define mmGAMMA_CORR_CNTLA_REGION_12_13                                         0x46d6
++#define mmGAMMA_CORR_CNTLA_REGION_14_15                                         0x46d7
++#define mmGAMMA_CORR_CNTLB_START_CNTL                                           0x46d8
++#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL                                           0x46d9
++#define mmGAMMA_CORR_CNTLB_END_CNTL1                                            0x46da
++#define mmGAMMA_CORR_CNTLB_END_CNTL2                                            0x46db
++#define mmGAMMA_CORR_CNTLB_REGION_0_1                                           0x46dc
++#define mmGAMMA_CORR_CNTLB_REGION_2_3                                           0x46dd
++#define mmGAMMA_CORR_CNTLB_REGION_4_5                                           0x46de
++#define mmGAMMA_CORR_CNTLB_REGION_6_7                                           0x46df
++#define mmGAMMA_CORR_CNTLB_REGION_8_9                                           0x46e0
++#define mmGAMMA_CORR_CNTLB_REGION_10_11                                         0x46e1
++#define mmGAMMA_CORR_CNTLB_REGION_12_13                                         0x46e2
++#define mmGAMMA_CORR_CNTLB_REGION_14_15                                         0x46e3
++#define mmPACK_FIFO_ERROR                                                       0x46e4
++#define mmOUTPUT_FIFO_ERROR                                                     0x46e5
++#define mmINPUT_GAMMA_LUT_AUTOFILL                                              0x46e6
++#define mmINPUT_GAMMA_LUT_RW_INDEX                                              0x46e7
++#define mmINPUT_GAMMA_LUT_SEQ_COLOR                                             0x46e8
++#define mmINPUT_GAMMA_LUT_PWL_DATA                                              0x46e9
++#define mmINPUT_GAMMA_LUT_30_COLOR                                              0x46ea
++#define mmCOL_MAN_INPUT_GAMMA_CONTROL1                                          0x46eb
++#define mmCOL_MAN_INPUT_GAMMA_CONTROL2                                          0x46ec
++#define mmINPUT_GAMMA_BW_OFFSETS_B                                              0x46ed
++#define mmINPUT_GAMMA_BW_OFFSETS_G                                              0x46ee
++#define mmINPUT_GAMMA_BW_OFFSETS_R                                              0x46ef
++#define mmCOL_MAN_DEBUG_CONTROL                                                 0x46f0
++#define mmCOL_MAN_TEST_DEBUG_INDEX                                              0x46f1
++#define mmCOL_MAN_TEST_DEBUG_DATA                                               0x46f3
++#define mmUNP_GRPH_ENABLE                                                       0x4600
++#define mmUNP_GRPH_CONTROL                                                      0x4601
++#define mmUNP_GRPH_CONTROL_C                                                    0x4602
++#define mmUNP_GRPH_CONTROL_EXP                                                  0x4603
++#define mmUNP_GRPH_SWAP_CNTL                                                    0x4605
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                                    0x4606
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                                    0x4607
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                               0x4608
++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                               0x4609
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                             0x460a
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                             0x460b
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                        0x460c
++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                        0x460d
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                                  0x460e
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                                  0x460f
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                             0x4610
++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                             0x4611
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                           0x4612
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                           0x4613
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                      0x4614
++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                      0x4615
++#define mmUNP_GRPH_PITCH_L                                                      0x4616
++#define mmUNP_GRPH_PITCH_C                                                      0x4617
++#define mmUNP_GRPH_SURFACE_OFFSET_X_L                                           0x4618
++#define mmUNP_GRPH_SURFACE_OFFSET_X_C                                           0x4619
++#define mmUNP_GRPH_SURFACE_OFFSET_Y_L                                           0x461a
++#define mmUNP_GRPH_SURFACE_OFFSET_Y_C                                           0x461b
++#define mmUNP_GRPH_X_START_L                                                    0x461c
++#define mmUNP_GRPH_X_START_C                                                    0x461d
++#define mmUNP_GRPH_Y_START_L                                                    0x461e
++#define mmUNP_GRPH_Y_START_C                                                    0x461f
++#define mmUNP_GRPH_X_END_L                                                      0x4620
++#define mmUNP_GRPH_X_END_C                                                      0x4621
++#define mmUNP_GRPH_Y_END_L                                                      0x4622
++#define mmUNP_GRPH_Y_END_C                                                      0x4623
++#define mmUNP_GRPH_UPDATE                                                       0x4624
++#define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT                                    0x463a
++#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L                                      0x4625
++#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C                                      0x4626
++#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                                 0x4627
++#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                                 0x4628
++#define mmUNP_DVMM_PTE_CONTROL                                                  0x4629
++#define mmUNP_DVMM_PTE_CONTROL_C                                                0x4604
++#define mmUNP_DVMM_PTE_ARB_CONTROL                                              0x462a
++#define mmUNP_DVMM_PTE_ARB_CONTROL_C                                            0x462d
++#define mmUNP_GRPH_INTERRUPT_STATUS                                             0x462b
++#define mmUNP_GRPH_INTERRUPT_CONTROL                                            0x462c
++#define mmUNP_GRPH_STEREOSYNC_FLIP                                              0x462e
++#define mmUNP_FLIP_CONTROL                                                      0x462f
++#define mmUNP_CRC_CONTROL                                                       0x4630
++#define mmUNP_CRC_MASK                                                          0x4631
++#define mmUNP_CRC_CURRENT                                                       0x4632
++#define mmUNP_CRC_LAST                                                          0x4633
++#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x4634
++#define mmUNP_HW_ROTATION                                                       0x4635
++#define mmUNP_DEBUG                                                             0x4636
++#define mmUNP_DEBUG2                                                            0x4637
++#define mmUNP_DVMM_DEBUG                                                        0x463b
++#define mmUNP_TEST_DEBUG_INDEX                                                  0x4638
++#define mmUNP_TEST_DEBUG_DATA                                                   0x4639
++#define mmGENMO_WT                                                              0xf0
++#define mmGENMO_RD                                                              0xf3
++#define mmGENENB                                                                0xf0
++#define mmGENFC_WT                                                              0xee
++#define mmVGA0_GENFC_WT                                                         0xee
++#define mmVGA1_GENFC_WT                                                         0xf6
++#define mmGENFC_RD                                                              0xf2
++#define mmGENS0                                                                 0xf0
++#define mmGENS1                                                                 0xee
++#define mmVGA0_GENS1                                                            0xee
++#define mmVGA1_GENS1                                                            0xf6
++#define mmDAC_DATA                                                              0xf2
++#define mmDAC_MASK                                                              0xf1
++#define mmDAC_R_INDEX                                                           0xf1
++#define mmDAC_W_INDEX                                                           0xf2
++#define mmSEQ8_IDX                                                              0xf1
++#define mmSEQ8_DATA                                                             0xf1
++#define ixSEQ00                                                                 0x0
++#define ixSEQ01                                                                 0x1
++#define ixSEQ02                                                                 0x2
++#define ixSEQ03                                                                 0x3
++#define ixSEQ04                                                                 0x4
++#define mmCRTC8_IDX                                                             0xed
++#define mmVGA0_CRTC8_IDX                                                        0xed
++#define mmVGA1_CRTC8_IDX                                                        0xf5
++#define mmCRTC8_DATA                                                            0xed
++#define mmVGA0_CRTC8_DATA                                                       0xed
++#define mmVGA1_CRTC8_DATA                                                       0xf5
++#define ixCRT00                                                                 0x0
++#define ixCRT01                                                                 0x1
++#define ixCRT02                                                                 0x2
++#define ixCRT03                                                                 0x3
++#define ixCRT04                                                                 0x4
++#define ixCRT05                                                                 0x5
++#define ixCRT06                                                                 0x6
++#define ixCRT07                                                                 0x7
++#define ixCRT08                                                                 0x8
++#define ixCRT09                                                                 0x9
++#define ixCRT0A                                                                 0xa
++#define ixCRT0B                                                                 0xb
++#define ixCRT0C                                                                 0xc
++#define ixCRT0D                                                                 0xd
++#define ixCRT0E                                                                 0xe
++#define ixCRT0F                                                                 0xf
++#define ixCRT10                                                                 0x10
++#define ixCRT11                                                                 0x11
++#define ixCRT12                                                                 0x12
++#define ixCRT13                                                                 0x13
++#define ixCRT14                                                                 0x14
++#define ixCRT15                                                                 0x15
++#define ixCRT16                                                                 0x16
++#define ixCRT17                                                                 0x17
++#define ixCRT18                                                                 0x18
++#define ixCRT1E                                                                 0x1e
++#define ixCRT1F                                                                 0x1f
++#define ixCRT22                                                                 0x22
++#define mmGRPH8_IDX                                                             0xf3
++#define mmGRPH8_DATA                                                            0xf3
++#define ixGRA00                                                                 0x0
++#define ixGRA01                                                                 0x1
++#define ixGRA02                                                                 0x2
++#define ixGRA03                                                                 0x3
++#define ixGRA04                                                                 0x4
++#define ixGRA05                                                                 0x5
++#define ixGRA06                                                                 0x6
++#define ixGRA07                                                                 0x7
++#define ixGRA08                                                                 0x8
++#define mmATTRX                                                                 0xf0
++#define mmATTRDW                                                                0xf0
++#define mmATTRDR                                                                0xf0
++#define ixATTR00                                                                0x0
++#define ixATTR01                                                                0x1
++#define ixATTR02                                                                0x2
++#define ixATTR03                                                                0x3
++#define ixATTR04                                                                0x4
++#define ixATTR05                                                                0x5
++#define ixATTR06                                                                0x6
++#define ixATTR07                                                                0x7
++#define ixATTR08                                                                0x8
++#define ixATTR09                                                                0x9
++#define ixATTR0A                                                                0xa
++#define ixATTR0B                                                                0xb
++#define ixATTR0C                                                                0xc
++#define ixATTR0D                                                                0xd
++#define ixATTR0E                                                                0xe
++#define ixATTR0F                                                                0xf
++#define ixATTR10                                                                0x10
++#define ixATTR11                                                                0x11
++#define ixATTR12                                                                0x12
++#define ixATTR13                                                                0x13
++#define ixATTR14                                                                0x14
++#define mmVGA_RENDER_CONTROL                                                    0xc0
++#define mmVGA_SOURCE_SELECT                                                     0xfc
++#define mmVGA_SEQUENCER_RESET_CONTROL                                           0xc1
++#define mmVGA_MODE_CONTROL                                                      0xc2
++#define mmVGA_SURFACE_PITCH_SELECT                                              0xc3
++#define mmVGA_MEMORY_BASE_ADDRESS                                               0xc4
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                          0xc9
++#define mmVGA_DISPBUF1_SURFACE_ADDR                                             0xc6
++#define mmVGA_DISPBUF2_SURFACE_ADDR                                             0xc8
++#define mmVGA_HDP_CONTROL                                                       0xca
++#define mmVGA_CACHE_CONTROL                                                     0xcb
++#define mmD1VGA_CONTROL                                                         0xcc
++#define mmD2VGA_CONTROL                                                         0xce
++#define mmD3VGA_CONTROL                                                         0xf8
++#define mmD4VGA_CONTROL                                                         0xf9
++#define mmD5VGA_CONTROL                                                         0xfa
++#define mmD6VGA_CONTROL                                                         0xfb
++#define mmVGA_HW_DEBUG                                                          0xcf
++#define mmVGA_STATUS                                                            0xd0
++#define mmVGA_INTERRUPT_CONTROL                                                 0xd1
++#define mmVGA_STATUS_CLEAR                                                      0xd2
++#define mmVGA_INTERRUPT_STATUS                                                  0xd3
++#define mmVGA_MAIN_CONTROL                                                      0xd4
++#define mmVGA_TEST_CONTROL                                                      0xd5
++#define mmVGA_DEBUG_READBACK_INDEX                                              0xd6
++#define mmVGA_DEBUG_READBACK_DATA                                               0xd7
++#define mmVGA_MEM_WRITE_PAGE_ADDR                                               0x12
++#define mmVGA_MEM_READ_PAGE_ADDR                                                0x13
++#define mmVGA_TEST_DEBUG_INDEX                                                  0xc5
++#define mmVGA_TEST_DEBUG_DATA                                                   0xc7
++#define ixVGADCC_DBG_DCCIF_C                                                    0x7e
++#define mmBPHYC_DAC_MACRO_CNTL                                                  0x48b9
++#define mmBPHYC_DAC_AUTO_CALIB_CONTROL                                          0x48ba
++#define mmPLL_REF_DIV                                                           0x1700
++#define mmBPHYC_PLL0_PLL_REF_DIV                                                0x1700
++#define mmBPHYC_PLL1_PLL_REF_DIV                                                0x172a
++#define mmBPHYC_PLL2_PLL_REF_DIV                                                0x1754
++#define mmPLL_FB_DIV                                                            0x1701
++#define mmBPHYC_PLL0_PLL_FB_DIV                                                 0x1701
++#define mmBPHYC_PLL1_PLL_FB_DIV                                                 0x172b
++#define mmBPHYC_PLL2_PLL_FB_DIV                                                 0x1755
++#define mmPLL_POST_DIV                                                          0x1702
++#define mmBPHYC_PLL0_PLL_POST_DIV                                               0x1702
++#define mmBPHYC_PLL1_PLL_POST_DIV                                               0x172c
++#define mmBPHYC_PLL2_PLL_POST_DIV                                               0x1756
++#define mmPLL_SS_AMOUNT_DSFRAC                                                  0x1703
++#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC                                       0x1703
++#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC                                       0x172d
++#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC                                       0x1757
++#define mmPLL_SS_CNTL                                                           0x1704
++#define mmBPHYC_PLL0_PLL_SS_CNTL                                                0x1704
++#define mmBPHYC_PLL1_PLL_SS_CNTL                                                0x172e
++#define mmBPHYC_PLL2_PLL_SS_CNTL                                                0x1758
++#define mmPLL_DS_CNTL                                                           0x1705
++#define mmBPHYC_PLL0_PLL_DS_CNTL                                                0x1705
++#define mmBPHYC_PLL1_PLL_DS_CNTL                                                0x172f
++#define mmBPHYC_PLL2_PLL_DS_CNTL                                                0x1759
++#define mmPLL_IDCLK_CNTL                                                        0x1706
++#define mmBPHYC_PLL0_PLL_IDCLK_CNTL                                             0x1706
++#define mmBPHYC_PLL1_PLL_IDCLK_CNTL                                             0x1730
++#define mmBPHYC_PLL2_PLL_IDCLK_CNTL                                             0x175a
++#define mmPLL_CNTL                                                              0x1707
++#define mmBPHYC_PLL0_PLL_CNTL                                                   0x1707
++#define mmBPHYC_PLL1_PLL_CNTL                                                   0x1731
++#define mmBPHYC_PLL2_PLL_CNTL                                                   0x175b
++#define mmPLL_ANALOG                                                            0x1708
++#define mmBPHYC_PLL0_PLL_ANALOG                                                 0x1708
++#define mmBPHYC_PLL1_PLL_ANALOG                                                 0x1732
++#define mmBPHYC_PLL2_PLL_ANALOG                                                 0x175c
++#define mmPLL_VREG_CNTL                                                         0x1709
++#define mmBPHYC_PLL0_PLL_VREG_CNTL                                              0x1709
++#define mmBPHYC_PLL1_PLL_VREG_CNTL                                              0x1733
++#define mmBPHYC_PLL2_PLL_VREG_CNTL                                              0x175d
++#define mmPLL_UNLOCK_DETECT_CNTL                                                0x170a
++#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL                                     0x170a
++#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL                                     0x1734
++#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL                                     0x175e
++#define mmPLL_DEBUG_CNTL                                                        0x170b
++#define mmBPHYC_PLL0_PLL_DEBUG_CNTL                                             0x170b
++#define mmBPHYC_PLL1_PLL_DEBUG_CNTL                                             0x1735
++#define mmBPHYC_PLL2_PLL_DEBUG_CNTL                                             0x175f
++#define mmPLL_UPDATE_LOCK                                                       0x170c
++#define mmBPHYC_PLL0_PLL_UPDATE_LOCK                                            0x170c
++#define mmBPHYC_PLL1_PLL_UPDATE_LOCK                                            0x1736
++#define mmBPHYC_PLL2_PLL_UPDATE_LOCK                                            0x1760
++#define mmPLL_UPDATE_CNTL                                                       0x170d
++#define mmBPHYC_PLL0_PLL_UPDATE_CNTL                                            0x170d
++#define mmBPHYC_PLL1_PLL_UPDATE_CNTL                                            0x1737
++#define mmBPHYC_PLL2_PLL_UPDATE_CNTL                                            0x1761
++#define mmPLL_XOR_LOCK                                                          0x1710
++#define mmBPHYC_PLL0_PLL_XOR_LOCK                                               0x1710
++#define mmBPHYC_PLL1_PLL_XOR_LOCK                                               0x173a
++#define mmBPHYC_PLL2_PLL_XOR_LOCK                                               0x1764
++#define mmPLL_ANALOG_CNTL                                                       0x1711
++#define mmBPHYC_PLL0_PLL_ANALOG_CNTL                                            0x1711
++#define mmBPHYC_PLL1_PLL_ANALOG_CNTL                                            0x173b
++#define mmBPHYC_PLL2_PLL_ANALOG_CNTL                                            0x1765
++#define mmVGA25_PPLL_REF_DIV                                                    0x1712
++#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV                                         0x1712
++#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV                                         0x173c
++#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV                                         0x1766
++#define mmVGA28_PPLL_REF_DIV                                                    0x1713
++#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV                                         0x1713
++#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV                                         0x173d
++#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV                                         0x1767
++#define mmVGA41_PPLL_REF_DIV                                                    0x1714
++#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV                                         0x1714
++#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV                                         0x173e
++#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV                                         0x1768
++#define mmVGA25_PPLL_FB_DIV                                                     0x1715
++#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV                                          0x1715
++#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV                                          0x173f
++#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV                                          0x1769
++#define mmVGA28_PPLL_FB_DIV                                                     0x1716
++#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV                                          0x1716
++#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV                                          0x1740
++#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV                                          0x176a
++#define mmVGA41_PPLL_FB_DIV                                                     0x1717
++#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV                                          0x1717
++#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV                                          0x1741
++#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV                                          0x176b
++#define mmVGA25_PPLL_POST_DIV                                                   0x1718
++#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV                                        0x1718
++#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV                                        0x1742
++#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV                                        0x176c
++#define mmVGA28_PPLL_POST_DIV                                                   0x1719
++#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV                                        0x1719
++#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV                                        0x1743
++#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV                                        0x176d
++#define mmVGA41_PPLL_POST_DIV                                                   0x171a
++#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV                                        0x171a
++#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV                                        0x1744
++#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV                                        0x176e
++#define mmVGA25_PPLL_ANALOG                                                     0x171b
++#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG                                          0x171b
++#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG                                          0x1745
++#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG                                          0x176f
++#define mmVGA28_PPLL_ANALOG                                                     0x171c
++#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG                                          0x171c
++#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG                                          0x1746
++#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG                                          0x1770
++#define mmVGA41_PPLL_ANALOG                                                     0x171d
++#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG                                          0x171d
++#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG                                          0x1747
++#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG                                          0x1771
++#define mmDISPPLL_BG_CNTL                                                       0x171e
++#define mmBPHYC_PLL0_DISPPLL_BG_CNTL                                            0x171e
++#define mmBPHYC_PLL1_DISPPLL_BG_CNTL                                            0x1748
++#define mmBPHYC_PLL2_DISPPLL_BG_CNTL                                            0x1772
++#define mmPPLL_DIV_UPDATE_DEBUG                                                 0x171f
++#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG                                      0x171f
++#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG                                      0x1749
++#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG                                      0x1773
++#define mmPPLL_STATUS_DEBUG                                                     0x1720
++#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG                                          0x1720
++#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG                                          0x174a
++#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG                                          0x1774
++#define mmPPLL_DEBUG_MUX_CNTL                                                   0x1721
++#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL                                        0x1721
++#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL                                        0x174b
++#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL                                        0x1775
++#define mmPPLL_SPARE0                                                           0x1722
++#define mmBPHYC_PLL0_PPLL_SPARE0                                                0x1722
++#define mmBPHYC_PLL1_PPLL_SPARE0                                                0x174c
++#define mmBPHYC_PLL2_PPLL_SPARE0                                                0x1776
++#define mmPPLL_SPARE1                                                           0x1723
++#define mmBPHYC_PLL0_PPLL_SPARE1                                                0x1723
++#define mmBPHYC_PLL1_PPLL_SPARE1                                                0x174d
++#define mmBPHYC_PLL2_PPLL_SPARE1                                                0x1777
++#define mmUNIPHY_TX_CONTROL1                                                    0x48c0
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1                                      0x48c0
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1                                      0x48e0
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1                                      0x4900
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1                                      0x4920
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1                                      0x4940
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1                                      0x4960
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1                                      0x4980
++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1                                      0x49c0
++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1                                      0x49e0
++#define mmUNIPHY_TX_CONTROL2                                                    0x48c1
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2                                      0x48c1
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2                                      0x48e1
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2                                      0x4901
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2                                      0x4921
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2                                      0x4941
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2                                      0x4961
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2                                      0x4981
++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2                                      0x49c1
++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2                                      0x49e1
++#define mmUNIPHY_TX_CONTROL3                                                    0x48c2
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3                                      0x48c2
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3                                      0x48e2
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3                                      0x4902
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3                                      0x4922
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3                                      0x4942
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3                                      0x4962
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3                                      0x4982
++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3                                      0x49c2
++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3                                      0x49e2
++#define mmUNIPHY_TX_CONTROL4                                                    0x48c3
++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4                                      0x48c3
++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4                                      0x48e3
++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4                                      0x4903
++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4                                      0x4923
++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4                                      0x4943
++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4                                      0x4963
++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4                                      0x4983
++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4                                      0x49c3
++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4                                      0x49e3
++#define mmUNIPHY_POWER_CONTROL                                                  0x48c4
++#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL                                    0x48c4
++#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL                                    0x48e4
++#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL                                    0x4904
++#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL                                    0x4924
++#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL                                    0x4944
++#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL                                    0x4964
++#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL                                    0x4984
++#define mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL                                    0x49c4
++#define mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL                                    0x49e4
++#define mmUNIPHY_PLL_FBDIV                                                      0x48c5
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV                                        0x48c5
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV                                        0x48e5
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV                                        0x4905
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV                                        0x4925
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV                                        0x4945
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV                                        0x4965
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV                                        0x4985
++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV                                        0x49c5
++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV                                        0x49e5
++#define mmUNIPHY_PLL_CONTROL1                                                   0x48c6
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1                                     0x48c6
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1                                     0x48e6
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1                                     0x4906
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1                                     0x4926
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1                                     0x4946
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1                                     0x4966
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1                                     0x4986
++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1                                     0x49c6
++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1                                     0x49e6
++#define mmUNIPHY_PLL_CONTROL2                                                   0x48c7
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2                                     0x48c7
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2                                     0x48e7
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2                                     0x4907
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2                                     0x4927
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2                                     0x4947
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2                                     0x4967
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2                                     0x4987
++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2                                     0x49c7
++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2                                     0x49e7
++#define mmUNIPHY_PLL_SS_STEP_SIZE                                               0x48c8
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE                                 0x48c8
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE                                 0x48e8
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE                                 0x4908
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE                                 0x4928
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE                                 0x4948
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE                                 0x4968
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE                                 0x4988
++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE                                 0x49c8
++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE                                 0x49e8
++#define mmUNIPHY_PLL_SS_CNTL                                                    0x48c9
++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL                                      0x48c9
++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL                                      0x48e9
++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL                                      0x4909
++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL                                      0x4929
++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL                                      0x4949
++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL                                      0x4969
++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL                                      0x4989
++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL                                      0x49c9
++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL                                      0x49e9
++#define mmUNIPHY_DATA_SYNCHRONIZATION                                           0x48ca
++#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION                             0x48ca
++#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION                             0x48ea
++#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION                             0x490a
++#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION                             0x492a
++#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION                             0x494a
++#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION                             0x496a
++#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION                             0x498a
++#define mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION                             0x49ca
++#define mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION                             0x49ea
++#define mmUNIPHY_REG_TEST_OUTPUT                                                0x48cb
++#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT                                  0x48cb
++#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT                                  0x48eb
++#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT                                  0x490b
++#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT                                  0x492b
++#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT                                  0x494b
++#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT                                  0x496b
++#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT                                  0x498b
++#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT                                  0x49cb
++#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT                                  0x49eb
++#define mmUNIPHY_ANG_BIST_CNTL                                                  0x48cc
++#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL                                    0x48cc
++#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL                                    0x48ec
++#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL                                    0x490c
++#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL                                    0x492c
++#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL                                    0x494c
++#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL                                    0x496c
++#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL                                    0x498c
++#define mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL                                    0x49cc
++#define mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL                                    0x49ec
++#define mmUNIPHY_REG_TEST_OUTPUT2                                               0x48cd
++#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2                                 0x48cd
++#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2                                 0x48ed
++#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2                                 0x490d
++#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2                                 0x492d
++#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2                                 0x494d
++#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2                                 0x496d
++#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2                                 0x498d
++#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2                                 0x49cd
++#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2                                 0x49ed
++#define mmUNIPHY_TMDP_REG0                                                      0x48ce
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0                                        0x48ce
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0                                        0x48ee
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0                                        0x490e
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0                                        0x492e
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0                                        0x494e
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0                                        0x496e
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0                                        0x498e
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0                                        0x49ce
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0                                        0x49ee
++#define mmUNIPHY_TMDP_REG1                                                      0x48cf
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1                                        0x48cf
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1                                        0x48ef
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1                                        0x490f
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1                                        0x492f
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1                                        0x494f
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1                                        0x496f
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1                                        0x498f
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1                                        0x49cf
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1                                        0x49ef
++#define mmUNIPHY_TMDP_REG2                                                      0x48d0
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2                                        0x48d0
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2                                        0x48f0
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2                                        0x4910
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2                                        0x4930
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2                                        0x4950
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2                                        0x4970
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2                                        0x4990
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2                                        0x49d0
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2                                        0x49f0
++#define mmUNIPHY_TMDP_REG3                                                      0x48d1
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3                                        0x48d1
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3                                        0x48f1
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3                                        0x4911
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3                                        0x4931
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3                                        0x4951
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3                                        0x4971
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3                                        0x4991
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3                                        0x49d1
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3                                        0x49f1
++#define mmUNIPHY_TMDP_REG4                                                      0x48d2
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4                                        0x48d2
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4                                        0x48f2
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4                                        0x4912
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4                                        0x4932
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4                                        0x4952
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4                                        0x4972
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4                                        0x4992
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4                                        0x49d2
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4                                        0x49f2
++#define mmUNIPHY_TMDP_REG5                                                      0x48d3
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5                                        0x48d3
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5                                        0x48f3
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5                                        0x4913
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5                                        0x4933
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5                                        0x4953
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5                                        0x4973
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5                                        0x4993
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5                                        0x49d3
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5                                        0x49f3
++#define mmUNIPHY_TMDP_REG6                                                      0x48d4
++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6                                        0x48d4
++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6                                        0x48f4
++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6                                        0x4914
++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6                                        0x4934
++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6                                        0x4954
++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6                                        0x4974
++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6                                        0x4994
++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6                                        0x49d4
++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6                                        0x49f4
++#define mmUNIPHY_TPG_CONTROL                                                    0x48d5
++#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL                                      0x48d5
++#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL                                      0x48f5
++#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL                                      0x4915
++#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL                                      0x4935
++#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL                                      0x4955
++#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL                                      0x4975
++#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL                                      0x4995
++#define mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL                                      0x49d5
++#define mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL                                      0x49f5
++#define mmUNIPHY_TPG_SEED                                                       0x48d6
++#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED                                         0x48d6
++#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED                                         0x48f6
++#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED                                         0x4916
++#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED                                         0x4936
++#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED                                         0x4956
++#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED                                         0x4976
++#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED                                         0x4996
++#define mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED                                         0x49d6
++#define mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED                                         0x49f6
++#define mmUNIPHY_DEBUG                                                          0x48d7
++#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG                                            0x48d7
++#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG                                            0x48f7
++#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG                                            0x4917
++#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG                                            0x4937
++#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG                                            0x4957
++#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG                                            0x4977
++#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG                                            0x4997
++#define mmBPHYC_UNIPHY7_UNIPHY_DEBUG                                            0x49d7
++#define mmBPHYC_UNIPHY8_UNIPHY_DEBUG                                            0x49f7
++#define mmDPG_PIPE_ARBITRATION_CONTROL1                                         0x1b30
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1                                0x1b30
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1                                0x1d30
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1                                0x1f30
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                                0x4130
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                                0x4330
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                                0x4530
++#define mmDPG_PIPE_ARBITRATION_CONTROL2                                         0x1b31
++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2                                0x1b31
++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2                                0x1d31
++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2                                0x1f31
++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                                0x4131
++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                                0x4331
++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                                0x4531
++#define mmDPG_WATERMARK_MASK_CONTROL                                            0x1b32
++#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL                                   0x1b32
++#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL                                   0x1d32
++#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL                                   0x1f32
++#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                                   0x4132
++#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                                   0x4332
++#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                                   0x4532
++#define mmDPG_PIPE_URGENCY_CONTROL                                              0x1b33
++#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL                                     0x1b33
++#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL                                     0x1d33
++#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL                                     0x1f33
++#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                                     0x4133
++#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                                     0x4333
++#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                                     0x4533
++#define mmDPG_PIPE_DPM_CONTROL                                                  0x1b34
++#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL                                         0x1b34
++#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL                                         0x1d34
++#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL                                         0x1f34
++#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                                         0x4134
++#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                                         0x4334
++#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                                         0x4534
++#define mmDPG_PIPE_STUTTER_CONTROL                                              0x1b35
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL                                     0x1b35
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL                                     0x1d35
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL                                     0x1f35
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                                     0x4135
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                                     0x4335
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                                     0x4535
++#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL                                     0x1b36
++#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1b36
++#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1d36
++#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1f36
++#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4136
++#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4336
++#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4536
++#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH                                     0x1b37
++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1b37
++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1d37
++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1f37
++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4137
++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4337
++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4537
++#define mmDPG_REPEATER_PROGRAM                                                  0x1b3a
++#define mmDMIF_PG0_DPG_REPEATER_PROGRAM                                         0x1b3a
++#define mmDMIF_PG1_DPG_REPEATER_PROGRAM                                         0x1d3a
++#define mmDMIF_PG2_DPG_REPEATER_PROGRAM                                         0x1f3a
++#define mmDMIF_PG3_DPG_REPEATER_PROGRAM                                         0x413a
++#define mmDMIF_PG4_DPG_REPEATER_PROGRAM                                         0x433a
++#define mmDMIF_PG5_DPG_REPEATER_PROGRAM                                         0x453a
++#define mmDPG_HW_DEBUG_A                                                        0x1b3b
++#define mmDMIF_PG0_DPG_HW_DEBUG_A                                               0x1b3b
++#define mmDMIF_PG1_DPG_HW_DEBUG_A                                               0x1d3b
++#define mmDMIF_PG2_DPG_HW_DEBUG_A                                               0x1f3b
++#define mmDMIF_PG3_DPG_HW_DEBUG_A                                               0x413b
++#define mmDMIF_PG4_DPG_HW_DEBUG_A                                               0x433b
++#define mmDMIF_PG5_DPG_HW_DEBUG_A                                               0x453b
++#define mmDPG_HW_DEBUG_B                                                        0x1b3c
++#define mmDMIF_PG0_DPG_HW_DEBUG_B                                               0x1b3c
++#define mmDMIF_PG1_DPG_HW_DEBUG_B                                               0x1d3c
++#define mmDMIF_PG2_DPG_HW_DEBUG_B                                               0x1f3c
++#define mmDMIF_PG3_DPG_HW_DEBUG_B                                               0x413c
++#define mmDMIF_PG4_DPG_HW_DEBUG_B                                               0x433c
++#define mmDMIF_PG5_DPG_HW_DEBUG_B                                               0x453c
++#define mmDPG_HW_DEBUG_11                                                       0x1b3d
++#define mmDMIF_PG0_DPG_HW_DEBUG_11                                              0x1b3d
++#define mmDMIF_PG1_DPG_HW_DEBUG_11                                              0x1d3d
++#define mmDMIF_PG2_DPG_HW_DEBUG_11                                              0x1f3d
++#define mmDMIF_PG3_DPG_HW_DEBUG_11                                              0x413d
++#define mmDMIF_PG4_DPG_HW_DEBUG_11                                              0x433d
++#define mmDMIF_PG5_DPG_HW_DEBUG_11                                              0x453d
++#define mmDPG_CHK_PRE_PROC_CNTL                                                 0x1b3e
++#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL                                        0x1b3e
++#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL                                        0x1d3e
++#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL                                        0x1f3e
++#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL                                        0x413e
++#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL                                        0x433e
++#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL                                        0x453e
++#define mmDPG_TEST_DEBUG_INDEX                                                  0x1b38
++#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX                                         0x1b38
++#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX                                         0x1d38
++#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX                                         0x1f38
++#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                                         0x4138
++#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                                         0x4338
++#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                                         0x4538
++#define mmDPG_TEST_DEBUG_DATA                                                   0x1b39
++#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA                                          0x1b39
++#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA                                          0x1d39
++#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA                                          0x1f39
++#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA                                          0x4139
++#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA                                          0x4339
++#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA                                          0x4539
++#define mmDPGV0_PIPE_ARBITRATION_CONTROL1                                       0x4730
++#define mmDPGV1_PIPE_ARBITRATION_CONTROL1                                       0x473d
++#define mmDPGV0_PIPE_ARBITRATION_CONTROL2                                       0x4731
++#define mmDPGV1_PIPE_ARBITRATION_CONTROL2                                       0x473e
++#define mmDPGV0_WATERMARK_MASK_CONTROL                                          0x4732
++#define mmDPGV1_WATERMARK_MASK_CONTROL                                          0x473f
++#define mmDPGV0_PIPE_URGENCY_CONTROL                                            0x4733
++#define mmDPGV1_PIPE_URGENCY_CONTROL                                            0x4740
++#define mmDPGV0_PIPE_DPM_CONTROL                                                0x4734
++#define mmDPGV1_PIPE_DPM_CONTROL                                                0x4741
++#define mmDPGV0_PIPE_STUTTER_CONTROL                                            0x4735
++#define mmDPGV1_PIPE_STUTTER_CONTROL                                            0x4742
++#define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                                   0x4736
++#define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                                   0x4743
++#define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                                   0x4737
++#define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                                   0x4744
++#define mmDPGV0_REPEATER_PROGRAM                                                0x4738
++#define mmDPGV1_REPEATER_PROGRAM                                                0x4745
++#define mmDPGV0_HW_DEBUG_A                                                      0x4739
++#define mmDPGV1_HW_DEBUG_A                                                      0x4746
++#define mmDPGV0_HW_DEBUG_B                                                      0x473a
++#define mmDPGV1_HW_DEBUG_B                                                      0x4747
++#define mmDPGV0_HW_DEBUG_11                                                     0x473b
++#define mmDPGV1_HW_DEBUG_11                                                     0x4748
++#define mmDPGV0_CHK_PRE_PROC_CNTL                                               0x473c
++#define mmDPGV1_CHK_PRE_PROC_CNTL                                               0x4749
++#define mmDPGV_TEST_DEBUG_INDEX                                                 0x474e
++#define mmDPGV_TEST_DEBUG_DATA                                                  0x474f
++#define ixDPGV0_DEBUG00_DMIFARB                                                 0x1
++#define ixDPGV1_DEBUG00_DMIFARB                                                 0x6a
++#define ixDPGV0_DEBUG01_DMIFARB                                                 0x2
++#define ixDPGV1_DEBUG01_DMIFARB                                                 0x6b
++#define ixDPGV0_DEBUG02_DMIFARB                                                 0x3
++#define ixDPGV1_DEBUG02_DMIFARB                                                 0x6c
++#define ixDPGV0_DEBUG03_DMIFARB                                                 0x4
++#define ixDPGV1_DEBUG03_DMIFARB                                                 0x6d
++#define ixDPGV0_DEBUG04_DMIFARB                                                 0x5
++#define ixDPGV1_DEBUG04_DMIFARB                                                 0x6e
++#define ixDPGV0_DEBUG00                                                         0x6
++#define ixDPGV1_DEBUG00                                                         0x6f
++#define ixDPGV0_DEBUG01                                                         0x7
++#define ixDPGV1_DEBUG01                                                         0x70
++#define ixDPGV0_DEBUG02                                                         0x8
++#define ixDPGV1_DEBUG02                                                         0x71
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                       0x18
++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                        0x18
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0xf00
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                            0xf02
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                 0xf04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT             0x1f04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x1f05
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x1f0a
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x1f0b
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x1f0f
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1705
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                0x17ff
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1720
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2              0x1721
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3              0x1722
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4              0x1723
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1770
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0x1828
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                            0x1829
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                   0x182b
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x182c
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x182d
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x182e
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x182f
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1830
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                0x1831
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1832
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1833
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                     0x1834
++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                               0x1835
++#define mmAZALIA_F0_CODEC_DEBUG                                                 0x1836
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                           0x1837
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                           0x1838
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                           0x1839
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                           0x183a
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                           0x183b
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                           0x183c
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                           0x183d
++#define mmGLOBAL_CAPABILITIES                                                   0x0
++#define mmMINOR_VERSION                                                         0x0
++#define mmMAJOR_VERSION                                                         0x0
++#define mmOUTPUT_PAYLOAD_CAPABILITY                                             0x1
++#define mmINPUT_PAYLOAD_CAPABILITY                                              0x1
++#define mmGLOBAL_CONTROL                                                        0x2
++#define mmWAKE_ENABLE                                                           0x3
++#define mmSTATE_CHANGE_STATUS                                                   0x3
++#define mmGLOBAL_STATUS                                                         0x4
++#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY                                      0x6
++#define mmINPUT_STREAM_PAYLOAD_CAPABILITY                                       0x6
++#define mmINTERRUPT_CONTROL                                                     0x8
++#define mmINTERRUPT_STATUS                                                      0x9
++#define mmWALL_CLOCK_COUNTER                                                    0xc
++#define mmSTREAM_SYNCHRONIZATION                                                0xe
++#define mmCORB_LOWER_BASE_ADDRESS                                               0x10
++#define mmCORB_UPPER_BASE_ADDRESS                                               0x11
++#define mmCORB_WRITE_POINTER                                                    0x12
++#define mmCORB_READ_POINTER                                                     0x12
++#define mmCORB_CONTROL                                                          0x13
++#define mmCORB_STATUS                                                           0x13
++#define mmCORB_SIZE                                                             0x13
++#define mmRIRB_LOWER_BASE_ADDRESS                                               0x14
++#define mmRIRB_UPPER_BASE_ADDRESS                                               0x15
++#define mmRIRB_WRITE_POINTER                                                    0x16
++#define mmRESPONSE_INTERRUPT_COUNT                                              0x16
++#define mmRIRB_CONTROL                                                          0x17
++#define mmRIRB_STATUS                                                           0x17
++#define mmRIRB_SIZE                                                             0x17
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                    0x18
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x18
++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x18
++#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                    0x19
++#define mmIMMEDIATE_COMMAND_STATUS                                              0x1a
++#define mmDMA_POSITION_LOWER_BASE_ADDRESS                                       0x1c
++#define mmDMA_POSITION_UPPER_BASE_ADDRESS                                       0x1d
++#define mmWALL_CLOCK_COUNTER_ALIAS                                              0x80c
++#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                           0x20
++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER              0x21
++#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                         0x22
++#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                             0x23
++#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                    0x24
++#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT                                       0x24
++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS               0x26
++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS               0x27
++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS        0x821
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                   0x18
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                    0x18
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x2f09
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x2f0a
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x2f0b
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2200
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x2706
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x270d
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                 0x270e
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                 0x273e
++#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                              0x2724
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x2770
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x2771
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x3f09
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                            0x3f0c
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                  0x3f0e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY            0x3702
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x3707
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x3708
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x3709
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x371c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2          0x371d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3          0x371e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4          0x371f
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION               0x3770
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                        0x3771
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                             0x3772
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                          0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                     0x3776
++#define ixAUDIO_DESCRIPTOR0                                                     0x1
++#define ixAUDIO_DESCRIPTOR1                                                     0x2
++#define ixAUDIO_DESCRIPTOR2                                                     0x3
++#define ixAUDIO_DESCRIPTOR3                                                     0x4
++#define ixAUDIO_DESCRIPTOR4                                                     0x5
++#define ixAUDIO_DESCRIPTOR5                                                     0x6
++#define ixAUDIO_DESCRIPTOR6                                                     0x7
++#define ixAUDIO_DESCRIPTOR7                                                     0x8
++#define ixAUDIO_DESCRIPTOR8                                                     0x9
++#define ixAUDIO_DESCRIPTOR9                                                     0xa
++#define ixAUDIO_DESCRIPTOR10                                                    0xb
++#define ixAUDIO_DESCRIPTOR11                                                    0xc
++#define ixAUDIO_DESCRIPTOR12                                                    0xd
++#define ixAUDIO_DESCRIPTOR13                                                    0xe
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                     0x3777
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                     0x3778
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                     0x3779
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                     0x377a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                   0x377b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                     0x3780
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                      0x3781
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                           0x0
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                0x1
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                      0x2
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                   0x3
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                   0x4
++#define ixSINK_DESCRIPTION0                                                     0x5
++#define ixSINK_DESCRIPTION1                                                     0x6
++#define ixSINK_DESCRIPTION2                                                     0x7
++#define ixSINK_DESCRIPTION3                                                     0x8
++#define ixSINK_DESCRIPTION4                                                     0x9
++#define ixSINK_DESCRIPTION5                                                     0xa
++#define ixSINK_DESCRIPTION6                                                     0xb
++#define ixSINK_DESCRIPTION7                                                     0xc
++#define ixSINK_DESCRIPTION8                                                     0xd
++#define ixSINK_DESCRIPTION9                                                     0xe
++#define ixSINK_DESCRIPTION10                                                    0xf
++#define ixSINK_DESCRIPTION11                                                    0x10
++#define ixSINK_DESCRIPTION12                                                    0x11
++#define ixSINK_DESCRIPTION13                                                    0x12
++#define ixSINK_DESCRIPTION14                                                    0x13
++#define ixSINK_DESCRIPTION15                                                    0x14
++#define ixSINK_DESCRIPTION16                                                    0x15
++#define ixSINK_DESCRIPTION17                                                    0x16
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                      0x3785
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                      0x3786
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                      0x3787
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                      0x3788
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x3789
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x378a
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x378b
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x378c
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x378d
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x378e
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x378f
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x3790
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x3791
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x3792
++#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                  0x3793
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x3797
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x3798
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                      0x3799
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x379a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                               0x379b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x379c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x379d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x379e
++#define mmAZALIA_CONTROLLER_CLOCK_GATING                                        0x17e4
++#define mmAZALIA_AUDIO_DTO                                                      0x17e5
++#define mmAZALIA_AUDIO_DTO_CONTROL                                              0x17e6
++#define mmAZALIA_SCLK_CONTROL                                                   0x17e7
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                        0x17e8
++#define mmAZALIA_DATA_DMA_CONTROL                                               0x17e9
++#define mmAZALIA_BDL_DMA_CONTROL                                                0x17ea
++#define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
++#define mmAZALIA_CORB_DMA_CONTROL                                               0x17ec
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                          0x17f3
++#define mmAZALIA_CYCLIC_BUFFER_SYNC                                             0x17f4
++#define mmAZALIA_GLOBAL_CAPABILITIES                                            0x17f5
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                      0x17f6
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                  0x17f7
++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                       0x17f8
++#define mmAZALIA_CONTROLLER_DEBUG                                               0x17f9
++#define mmAZALIA_MEM_PWR_CTRL                                                   0x1810
++#define mmAZALIA_MEM_PWR_STATUS                                                 0x1811
++#define mmDCI_PG_DEBUG_CONFIG                                                   0x1812
++#define mmAZALIA_INPUT_CRC0_CONTROL0                                            0x17fb
++#define mmAZALIA_INPUT_CRC0_CONTROL1                                            0x17fc
++#define mmAZALIA_INPUT_CRC0_CONTROL2                                            0x17fd
++#define mmAZALIA_INPUT_CRC0_CONTROL3                                            0x17fe
++#define mmAZALIA_INPUT_CRC0_RESULT                                              0x17ff
++#define ixAZALIA_INPUT_CRC0_CHANNEL0                                            0x0
++#define ixAZALIA_INPUT_CRC0_CHANNEL1                                            0x1
++#define ixAZALIA_INPUT_CRC0_CHANNEL2                                            0x2
++#define ixAZALIA_INPUT_CRC0_CHANNEL3                                            0x3
++#define ixAZALIA_INPUT_CRC0_CHANNEL4                                            0x4
++#define ixAZALIA_INPUT_CRC0_CHANNEL5                                            0x5
++#define ixAZALIA_INPUT_CRC0_CHANNEL6                                            0x6
++#define ixAZALIA_INPUT_CRC0_CHANNEL7                                            0x7
++#define mmAZALIA_INPUT_CRC1_CONTROL0                                            0x1800
++#define mmAZALIA_INPUT_CRC1_CONTROL1                                            0x1801
++#define mmAZALIA_INPUT_CRC1_CONTROL2                                            0x1802
++#define mmAZALIA_INPUT_CRC1_CONTROL3                                            0x1803
++#define mmAZALIA_INPUT_CRC1_RESULT                                              0x1804
++#define ixAZALIA_INPUT_CRC1_CHANNEL0                                            0x0
++#define ixAZALIA_INPUT_CRC1_CHANNEL1                                            0x1
++#define ixAZALIA_INPUT_CRC1_CHANNEL2                                            0x2
++#define ixAZALIA_INPUT_CRC1_CHANNEL3                                            0x3
++#define ixAZALIA_INPUT_CRC1_CHANNEL4                                            0x4
++#define ixAZALIA_INPUT_CRC1_CHANNEL5                                            0x5
++#define ixAZALIA_INPUT_CRC1_CHANNEL6                                            0x6
++#define ixAZALIA_INPUT_CRC1_CHANNEL7                                            0x7
++#define mmAZALIA_CRC0_CONTROL0                                                  0x1805
++#define mmAZALIA_CRC0_CONTROL1                                                  0x1806
++#define mmAZALIA_CRC0_CONTROL2                                                  0x1807
++#define mmAZALIA_CRC0_CONTROL3                                                  0x1808
++#define mmAZALIA_CRC0_RESULT                                                    0x1809
++#define ixAZALIA_CRC0_CHANNEL0                                                  0x0
++#define ixAZALIA_CRC0_CHANNEL1                                                  0x1
++#define ixAZALIA_CRC0_CHANNEL2                                                  0x2
++#define ixAZALIA_CRC0_CHANNEL3                                                  0x3
++#define ixAZALIA_CRC0_CHANNEL4                                                  0x4
++#define ixAZALIA_CRC0_CHANNEL5                                                  0x5
++#define ixAZALIA_CRC0_CHANNEL6                                                  0x6
++#define ixAZALIA_CRC0_CHANNEL7                                                  0x7
++#define mmAZALIA_CRC1_CONTROL0                                                  0x180a
++#define mmAZALIA_CRC1_CONTROL1                                                  0x180b
++#define mmAZALIA_CRC1_CONTROL2                                                  0x180c
++#define mmAZALIA_CRC1_CONTROL3                                                  0x180d
++#define mmAZALIA_CRC1_RESULT                                                    0x180e
++#define ixAZALIA_CRC1_CHANNEL0                                                  0x0
++#define ixAZALIA_CRC1_CHANNEL1                                                  0x1
++#define ixAZALIA_CRC1_CHANNEL2                                                  0x2
++#define ixAZALIA_CRC1_CHANNEL3                                                  0x3
++#define ixAZALIA_CRC1_CHANNEL4                                                  0x4
++#define ixAZALIA_CRC1_CHANNEL5                                                  0x5
++#define ixAZALIA_CRC1_CHANNEL6                                                  0x6
++#define ixAZALIA_CRC1_CHANNEL7                                                  0x7
++#define mmAZ_TEST_DEBUG_INDEX                                                   0x181f
++#define mmAZ_TEST_DEBUG_DATA                                                    0x1820
++#define mmAZALIA_STREAM_INDEX                                                   0x1780
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                       0x1780
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                       0x1782
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                       0x1784
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                       0x1786
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                       0x1788
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                       0x178a
++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                       0x178c
++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                       0x178e
++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                       0x59c0
++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                       0x59c2
++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                      0x59c4
++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                      0x59c6
++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                      0x59c8
++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                      0x59ca
++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                      0x59cc
++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                      0x59ce
++#define mmAZALIA_STREAM_DATA                                                    0x1781
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                        0x1781
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                        0x1783
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                        0x1785
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                        0x1787
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                        0x1789
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                        0x178b
++#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                        0x178d
++#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                        0x178f
++#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                        0x59c1
++#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                        0x59c3
++#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                       0x59c5
++#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                       0x59c7
++#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                       0x59c9
++#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                       0x59cb
++#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                       0x59cd
++#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                       0x59cf
++#define ixAZALIA_FIFO_SIZE_CONTROL                                              0x0
++#define ixAZALIA_LATENCY_COUNTER_CONTROL                                        0x1
++#define ixAZALIA_WORSTCASE_LATENCY_COUNT                                        0x2
++#define ixAZALIA_CUMULATIVE_LATENCY_COUNT                                       0x3
++#define ixAZALIA_CUMULATIVE_REQUEST_COUNT                                       0x4
++#define ixAZALIA_STREAM_DEBUG                                                   0x5
++#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX                                        0x17a8
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17a8
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17ac
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b0
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b4
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b8
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17bc
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c0
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c4
++#define mmAZALIA_F0_CODEC_ENDPOINT_DATA                                         0x17a9
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17a9
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17ad
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b1
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b5
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b9
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17bd
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c1
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c5
++#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG                                   0x0
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x1
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x3
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x4
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x5
++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x6
++#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                              0x7
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x8
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x9
++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG                    0xa
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                           0xc
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                       0xd
++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                       0xe
++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x20
++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                            0x21
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x22
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                         0x2b
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                         0x2c
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                         0x2d
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                         0x2e
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                         0x2f
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                         0x30
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                         0x31
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                        0x32
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                        0x33
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                        0x34
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                        0x35
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                       0x36
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                      0x57
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x58
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                          0x37
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                              0x38
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                0x3a
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                0x3b
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                0x3c
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                0x3d
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                0x3e
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                0x3f
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                0x40
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                0x41
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                0x42
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                          0x54
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                0x55
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x56
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x59
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x5a
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x5b
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x5c
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x5d
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x5e
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x5f
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x60
++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x61
++#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                  0x62
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x63
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x64
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB                                      0x65
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x66
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                               0x67
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x68
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x69
++#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x6a
++#define ixAZALIA_F0_AUDIO_ENABLE_STATUS                                         0x6b
++#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS                                    0x6c
++#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS                                   0x6d
++#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                             0x6e
++#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                  0x59d4
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d4
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d8
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59dc
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e0
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e4
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e8
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59ec
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59f0
++#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                   0x59d5
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d5
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d9
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59dd
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e1
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e5
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e9
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59ed
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59f1
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG                             0x0
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x1
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x2
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x3
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x4
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x5
++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6
++#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x20
++#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x21
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x22
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE            0x23
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x24
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                 0x36
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                0x37
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                        0x38
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x53
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                    0x54
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE          0x55
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x56
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x67
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x68
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x64
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                0x65
++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x66
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                    0x18
++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                     0x18
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x6f09
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6f0a
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x6f0b
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x6200
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x6706
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x670d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x7f09
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x7f0c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x7707
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x7708
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                  0x7709
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x771c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2    0x771d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3    0x771e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4    0x771f
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                0x7777
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                0x7785
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                0x7778
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                0x7786
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                 0x777c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                0x7779
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                0x7787
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                0x777a
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                0x7788
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x7771
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x779b
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x779c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                    0x779d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                    0x779e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x7798
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                0x7799
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x779a
++#define mmBLND_CONTROL                                                          0x1b6d
++#define mmBLND0_BLND_CONTROL                                                    0x1b6d
++#define mmBLND1_BLND_CONTROL                                                    0x1d6d
++#define mmBLND2_BLND_CONTROL                                                    0x1f6d
++#define mmBLND3_BLND_CONTROL                                                    0x416d
++#define mmBLND4_BLND_CONTROL                                                    0x436d
++#define mmBLND5_BLND_CONTROL                                                    0x456d
++#define mmBLND_SM_CONTROL2                                                      0x1b6e
++#define mmBLND0_BLND_SM_CONTROL2                                                0x1b6e
++#define mmBLND1_BLND_SM_CONTROL2                                                0x1d6e
++#define mmBLND2_BLND_SM_CONTROL2                                                0x1f6e
++#define mmBLND3_BLND_SM_CONTROL2                                                0x416e
++#define mmBLND4_BLND_SM_CONTROL2                                                0x436e
++#define mmBLND5_BLND_SM_CONTROL2                                                0x456e
++#define mmBLND_CONTROL2                                                         0x1b6f
++#define mmBLND0_BLND_CONTROL2                                                   0x1b6f
++#define mmBLND1_BLND_CONTROL2                                                   0x1d6f
++#define mmBLND2_BLND_CONTROL2                                                   0x1f6f
++#define mmBLND3_BLND_CONTROL2                                                   0x416f
++#define mmBLND4_BLND_CONTROL2                                                   0x436f
++#define mmBLND5_BLND_CONTROL2                                                   0x456f
++#define mmBLND_UPDATE                                                           0x1b70
++#define mmBLND0_BLND_UPDATE                                                     0x1b70
++#define mmBLND1_BLND_UPDATE                                                     0x1d70
++#define mmBLND2_BLND_UPDATE                                                     0x1f70
++#define mmBLND3_BLND_UPDATE                                                     0x4170
++#define mmBLND4_BLND_UPDATE                                                     0x4370
++#define mmBLND5_BLND_UPDATE                                                     0x4570
++#define mmBLND_UNDERFLOW_INTERRUPT                                              0x1b71
++#define mmBLND0_BLND_UNDERFLOW_INTERRUPT                                        0x1b71
++#define mmBLND1_BLND_UNDERFLOW_INTERRUPT                                        0x1d71
++#define mmBLND2_BLND_UNDERFLOW_INTERRUPT                                        0x1f71
++#define mmBLND3_BLND_UNDERFLOW_INTERRUPT                                        0x4171
++#define mmBLND4_BLND_UNDERFLOW_INTERRUPT                                        0x4371
++#define mmBLND5_BLND_UNDERFLOW_INTERRUPT                                        0x4571
++#define mmBLND_V_UPDATE_LOCK                                                    0x1b73
++#define mmBLND0_BLND_V_UPDATE_LOCK                                              0x1b73
++#define mmBLND1_BLND_V_UPDATE_LOCK                                              0x1d73
++#define mmBLND2_BLND_V_UPDATE_LOCK                                              0x1f73
++#define mmBLND3_BLND_V_UPDATE_LOCK                                              0x4173
++#define mmBLND4_BLND_V_UPDATE_LOCK                                              0x4373
++#define mmBLND5_BLND_V_UPDATE_LOCK                                              0x4573
++#define mmBLND_REG_UPDATE_STATUS                                                0x1b77
++#define mmBLND0_BLND_REG_UPDATE_STATUS                                          0x1b77
++#define mmBLND1_BLND_REG_UPDATE_STATUS                                          0x1d77
++#define mmBLND2_BLND_REG_UPDATE_STATUS                                          0x1f77
++#define mmBLND3_BLND_REG_UPDATE_STATUS                                          0x4177
++#define mmBLND4_BLND_REG_UPDATE_STATUS                                          0x4377
++#define mmBLND5_BLND_REG_UPDATE_STATUS                                          0x4577
++#define mmBLND_DEBUG                                                            0x1b74
++#define mmBLND0_BLND_DEBUG                                                      0x1b74
++#define mmBLND1_BLND_DEBUG                                                      0x1d74
++#define mmBLND2_BLND_DEBUG                                                      0x1f74
++#define mmBLND3_BLND_DEBUG                                                      0x4174
++#define mmBLND4_BLND_DEBUG                                                      0x4374
++#define mmBLND5_BLND_DEBUG                                                      0x4574
++#define mmBLND_TEST_DEBUG_INDEX                                                 0x1b75
++#define mmBLND0_BLND_TEST_DEBUG_INDEX                                           0x1b75
++#define mmBLND1_BLND_TEST_DEBUG_INDEX                                           0x1d75
++#define mmBLND2_BLND_TEST_DEBUG_INDEX                                           0x1f75
++#define mmBLND3_BLND_TEST_DEBUG_INDEX                                           0x4175
++#define mmBLND4_BLND_TEST_DEBUG_INDEX                                           0x4375
++#define mmBLND5_BLND_TEST_DEBUG_INDEX                                           0x4575
++#define mmBLND_TEST_DEBUG_DATA                                                  0x1b76
++#define mmBLND0_BLND_TEST_DEBUG_DATA                                            0x1b76
++#define mmBLND1_BLND_TEST_DEBUG_DATA                                            0x1d76
++#define mmBLND2_BLND_TEST_DEBUG_DATA                                            0x1f76
++#define mmBLND3_BLND_TEST_DEBUG_DATA                                            0x4176
++#define mmBLND4_BLND_TEST_DEBUG_DATA                                            0x4376
++#define mmBLND5_BLND_TEST_DEBUG_DATA                                            0x4576
++#define mmWB_ENABLE                                                             0x5e18
++#define mmWB_EC_CONFIG                                                          0x5e19
++#define mmCNV_MODE                                                              0x5e1a
++#define mmCNV_WINDOW_START                                                      0x5e1b
++#define mmCNV_WINDOW_SIZE                                                       0x5e1c
++#define mmCNV_UPDATE                                                            0x5e1d
++#define mmCNV_SOURCE_SIZE                                                       0x5e1e
++#define mmCNV_CSC_CONTROL                                                       0x5e1f
++#define mmCNV_CSC_C11_C12                                                       0x5e20
++#define mmCNV_CSC_C13_C14                                                       0x5e21
++#define mmCNV_CSC_C21_C22                                                       0x5e22
++#define mmCNV_CSC_C23_C24                                                       0x5e23
++#define mmCNV_CSC_C31_C32                                                       0x5e24
++#define mmCNV_CSC_C33_C34                                                       0x5e25
++#define mmCNV_CSC_ROUND_OFFSET_R                                                0x5e26
++#define mmCNV_CSC_ROUND_OFFSET_G                                                0x5e27
++#define mmCNV_CSC_ROUND_OFFSET_B                                                0x5e28
++#define mmCNV_CSC_CLAMP_R                                                       0x5e29
++#define mmCNV_CSC_CLAMP_G                                                       0x5e2a
++#define mmCNV_CSC_CLAMP_B                                                       0x5e2b
++#define mmCNV_TEST_CNTL                                                         0x5e2c
++#define mmCNV_TEST_CRC_RED                                                      0x5e2d
++#define mmCNV_TEST_CRC_GREEN                                                    0x5e2e
++#define mmCNV_TEST_CRC_BLUE                                                     0x5e2f
++#define mmWB_DEBUG_CTRL                                                         0x5e30
++#define mmWB_DBG_MODE                                                           0x5e31
++#define mmWB_HW_DEBUG                                                           0x5e32
++#define mmCNV_INPUT_SELECT                                                      0x5e33
++#define mmWB_SOFT_RESET                                                         0x5e36
++#define mmCNV_TEST_DEBUG_INDEX                                                  0x5e34
++#define mmCNV_TEST_DEBUG_DATA                                                   0x5e35
++#define mmDCFE_CLOCK_CONTROL                                                    0x1b00
++#define mmDCFE0_DCFE_CLOCK_CONTROL                                              0x1b00
++#define mmDCFE1_DCFE_CLOCK_CONTROL                                              0x1d00
++#define mmDCFE2_DCFE_CLOCK_CONTROL                                              0x1f00
++#define mmDCFE3_DCFE_CLOCK_CONTROL                                              0x4100
++#define mmDCFE4_DCFE_CLOCK_CONTROL                                              0x4300
++#define mmDCFE5_DCFE_CLOCK_CONTROL                                              0x4500
++#define mmDCFE_SOFT_RESET                                                       0x1b01
++#define mmDCFE0_DCFE_SOFT_RESET                                                 0x1b01
++#define mmDCFE1_DCFE_SOFT_RESET                                                 0x1d01
++#define mmDCFE2_DCFE_SOFT_RESET                                                 0x1f01
++#define mmDCFE3_DCFE_SOFT_RESET                                                 0x4101
++#define mmDCFE4_DCFE_SOFT_RESET                                                 0x4301
++#define mmDCFE5_DCFE_SOFT_RESET                                                 0x4501
++#define mmDCFE_DBG_CONFIG                                                       0x1b02
++#define mmDCFE0_DCFE_DBG_CONFIG                                                 0x1b02
++#define mmDCFE1_DCFE_DBG_CONFIG                                                 0x1d02
++#define mmDCFE2_DCFE_DBG_CONFIG                                                 0x1f02
++#define mmDCFE3_DCFE_DBG_CONFIG                                                 0x4102
++#define mmDCFE4_DCFE_DBG_CONFIG                                                 0x4302
++#define mmDCFE5_DCFE_DBG_CONFIG                                                 0x4502
++#define mmDCFE_MEM_PWR_CTRL                                                     0x1b03
++#define mmDCFE0_DCFE_MEM_PWR_CTRL                                               0x1b03
++#define mmDCFE1_DCFE_MEM_PWR_CTRL                                               0x1d03
++#define mmDCFE2_DCFE_MEM_PWR_CTRL                                               0x1f03
++#define mmDCFE3_DCFE_MEM_PWR_CTRL                                               0x4103
++#define mmDCFE4_DCFE_MEM_PWR_CTRL                                               0x4303
++#define mmDCFE5_DCFE_MEM_PWR_CTRL                                               0x4503
++#define mmDCFE_MEM_PWR_CTRL2                                                    0x1b04
++#define mmDCFE0_DCFE_MEM_PWR_CTRL2                                              0x1b04
++#define mmDCFE1_DCFE_MEM_PWR_CTRL2                                              0x1d04
++#define mmDCFE2_DCFE_MEM_PWR_CTRL2                                              0x1f04
++#define mmDCFE3_DCFE_MEM_PWR_CTRL2                                              0x4104
++#define mmDCFE4_DCFE_MEM_PWR_CTRL2                                              0x4304
++#define mmDCFE5_DCFE_MEM_PWR_CTRL2                                              0x4504
++#define mmDCFE_MEM_PWR_STATUS                                                   0x1b05
++#define mmDCFE0_DCFE_MEM_PWR_STATUS                                             0x1b05
++#define mmDCFE1_DCFE_MEM_PWR_STATUS                                             0x1d05
++#define mmDCFE2_DCFE_MEM_PWR_STATUS                                             0x1f05
++#define mmDCFE3_DCFE_MEM_PWR_STATUS                                             0x4105
++#define mmDCFE4_DCFE_MEM_PWR_STATUS                                             0x4305
++#define mmDCFE5_DCFE_MEM_PWR_STATUS                                             0x4505
++#define mmDCFE_MISC                                                             0x1b06
++#define mmDCFE0_DCFE_MISC                                                       0x1b06
++#define mmDCFE1_DCFE_MISC                                                       0x1d06
++#define mmDCFE2_DCFE_MISC                                                       0x1f06
++#define mmDCFE3_DCFE_MISC                                                       0x4106
++#define mmDCFE4_DCFE_MISC                                                       0x4306
++#define mmDCFE5_DCFE_MISC                                                       0x4506
++#define mmDCFEV_CLOCK_CONTROL                                                   0x46f4
++#define mmDCFEV_SOFT_RESET                                                      0x46f5
++#define mmDCFEV_DMIFV_CLOCK_CONTROL                                             0x46f6
++#define mmDCFEV_DBG_CONFIG                                                      0x46f7
++#define mmDCFEV_DMIFV_MEM_PWR_CTRL                                              0x46f8
++#define mmDCFEV_DMIFV_MEM_PWR_STATUS                                            0x46f9
++#define mmDCFEV_MEM_PWR_CTRL                                                    0x46fa
++#define mmDCFEV_MEM_PWR_CTRL2                                                   0x46fb
++#define mmDCFEV_MEM_PWR_STATUS                                                  0x46fc
++#define mmDCFEV_DMIFV_DEBUG                                                     0x46fd
++#define mmDCFEV_MISC                                                            0x46fe
++#define mmDC_HPD_INT_STATUS                                                     0x1898
++#define mmHPD0_DC_HPD_INT_STATUS                                                0x1898
++#define mmHPD1_DC_HPD_INT_STATUS                                                0x18a0
++#define mmHPD2_DC_HPD_INT_STATUS                                                0x18a8
++#define mmHPD3_DC_HPD_INT_STATUS                                                0x18b0
++#define mmHPD4_DC_HPD_INT_STATUS                                                0x18b8
++#define mmHPD5_DC_HPD_INT_STATUS                                                0x18c0
++#define mmDC_HPD_INT_CONTROL                                                    0x1899
++#define mmHPD0_DC_HPD_INT_CONTROL                                               0x1899
++#define mmHPD1_DC_HPD_INT_CONTROL                                               0x18a1
++#define mmHPD2_DC_HPD_INT_CONTROL                                               0x18a9
++#define mmHPD3_DC_HPD_INT_CONTROL                                               0x18b1
++#define mmHPD4_DC_HPD_INT_CONTROL                                               0x18b9
++#define mmHPD5_DC_HPD_INT_CONTROL                                               0x18c1
++#define mmDC_HPD_CONTROL                                                        0x189a
++#define mmHPD0_DC_HPD_CONTROL                                                   0x189a
++#define mmHPD1_DC_HPD_CONTROL                                                   0x18a2
++#define mmHPD2_DC_HPD_CONTROL                                                   0x18aa
++#define mmHPD3_DC_HPD_CONTROL                                                   0x18b2
++#define mmHPD4_DC_HPD_CONTROL                                                   0x18ba
++#define mmHPD5_DC_HPD_CONTROL                                                   0x18c2
++#define mmDC_HPD_FAST_TRAIN_CNTL                                                0x189b
++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                           0x189b
++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                           0x18a3
++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                           0x18ab
++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                           0x18b3
++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                           0x18bb
++#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL                                           0x18c3
++#define mmDC_HPD_TOGGLE_FILT_CNTL                                               0x189c
++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                          0x189c
++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                          0x18a4
++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                          0x18ac
++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                          0x18b4
++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                          0x18bc
++#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL                                          0x18c4
++#define mmDCO_SCRATCH0                                                          0x184e
++#define mmDCO_SCRATCH1                                                          0x184f
++#define mmDCO_SCRATCH2                                                          0x1850
++#define mmDCO_SCRATCH3                                                          0x1851
++#define mmDCO_SCRATCH4                                                          0x1852
++#define mmDCO_SCRATCH5                                                          0x1853
++#define mmDCO_SCRATCH6                                                          0x1854
++#define mmDCO_SCRATCH7                                                          0x1855
++#define mmDCE_VCE_CONTROL                                                       0x1856
++#define mmDISP_INTERRUPT_STATUS                                                 0x1857
++#define mmDISP_INTERRUPT_STATUS_CONTINUE                                        0x1858
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                       0x1859
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                       0x185a
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                       0x185b
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                       0x185c
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                       0x185d
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                       0x185e
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                       0x185f
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                       0x1860
++#define mmDISP_INTERRUPT_STATUS_CONTINUE10                                      0x1875
++#define mmDCO_MEM_PWR_STATUS                                                    0x1861
++#define mmDCO_MEM_PWR_STATUS1                                                   0x1874
++#define mmDCO_MEM_PWR_CTRL                                                      0x1862
++#define mmDCO_MEM_PWR_CTRL2                                                     0x1863
++#define mmDCO_CLK_CNTL                                                          0x1864
++#define mmDCO_CLK_CNTL2                                                         0x1876
++#define mmDCO_CLK_CNTL3                                                         0x1877
++#define mmDPDBG_CNTL                                                            0x1866
++#define mmDPDBG_INTERRUPT                                                       0x1867
++#define mmDCO_POWER_MANAGEMENT_CNTL                                             0x1868
++#define mmDCO_SOFT_RESET                                                        0x1871
++#define mmDIG_SOFT_RESET                                                        0x1872
++#define mmDIG_SOFT_RESET_2                                                      0x186a
++#define mmDCO_STEREOSYNC_SEL                                                    0x186e
++#define mmDCO_TEST_DEBUG_INDEX                                                  0x186f
++#define mmDCO_TEST_DEBUG_DATA                                                   0x1870
++#define mmDC_I2C_CONTROL                                                        0x16d4
++#define mmDC_I2C_ARBITRATION                                                    0x16d5
++#define mmDC_I2C_INTERRUPT_CONTROL                                              0x16d6
++#define mmDC_I2C_SW_STATUS                                                      0x16d7
++#define mmDC_I2C_DDC1_HW_STATUS                                                 0x16d8
++#define mmDC_I2C_DDC2_HW_STATUS                                                 0x16d9
++#define mmDC_I2C_DDC3_HW_STATUS                                                 0x16da
++#define mmDC_I2C_DDC4_HW_STATUS                                                 0x16db
++#define mmDC_I2C_DDC5_HW_STATUS                                                 0x16dc
++#define mmDC_I2C_DDC6_HW_STATUS                                                 0x16dd
++#define mmDC_I2C_DDC1_SPEED                                                     0x16de
++#define mmDC_I2C_DDC1_SETUP                                                     0x16df
++#define mmDC_I2C_DDC2_SPEED                                                     0x16e0
++#define mmDC_I2C_DDC2_SETUP                                                     0x16e1
++#define mmDC_I2C_DDC3_SPEED                                                     0x16e2
++#define mmDC_I2C_DDC3_SETUP                                                     0x16e3
++#define mmDC_I2C_DDC4_SPEED                                                     0x16e4
++#define mmDC_I2C_DDC4_SETUP                                                     0x16e5
++#define mmDC_I2C_DDC5_SPEED                                                     0x16e6
++#define mmDC_I2C_DDC5_SETUP                                                     0x16e7
++#define mmDC_I2C_DDC6_SPEED                                                     0x16e8
++#define mmDC_I2C_DDC6_SETUP                                                     0x16e9
++#define mmDC_I2C_TRANSACTION0                                                   0x16ea
++#define mmDC_I2C_TRANSACTION1                                                   0x16eb
++#define mmDC_I2C_TRANSACTION2                                                   0x16ec
++#define mmDC_I2C_TRANSACTION3                                                   0x16ed
++#define mmDC_I2C_DATA                                                           0x16ee
++#define mmDC_I2C_DDCVGA_HW_STATUS                                               0x16ef
++#define mmDC_I2C_DDCVGA_SPEED                                                   0x16f0
++#define mmDC_I2C_DDCVGA_SETUP                                                   0x16f1
++#define mmDC_I2C_EDID_DETECT_CTRL                                               0x16f2
++#define mmDC_I2C_READ_REQUEST_INTERRUPT                                         0x16f3
++#define mmGENERIC_I2C_CONTROL                                                   0x16f4
++#define mmGENERIC_I2C_INTERRUPT_CONTROL                                         0x16f5
++#define mmGENERIC_I2C_STATUS                                                    0x16f6
++#define mmGENERIC_I2C_SPEED                                                     0x16f7
++#define mmGENERIC_I2C_SETUP                                                     0x16f8
++#define mmGENERIC_I2C_TRANSACTION                                               0x16f9
++#define mmGENERIC_I2C_DATA                                                      0x16fa
++#define mmGENERIC_I2C_PIN_SELECTION                                             0x16fb
++#define mmGENERIC_I2C_PIN_DEBUG                                                 0x16fc
++#define mmBLNDV_CONTROL                                                         0x476d
++#define mmBLNDV_SM_CONTROL2                                                     0x476e
++#define mmBLNDV_CONTROL2                                                        0x476f
++#define mmBLNDV_UPDATE                                                          0x4770
++#define mmBLNDV_UNDERFLOW_INTERRUPT                                             0x4771
++#define mmBLNDV_V_UPDATE_LOCK                                                   0x4773
++#define mmBLNDV_REG_UPDATE_STATUS                                               0x4777
++#define mmBLNDV_DEBUG                                                           0x4774
++#define mmBLNDV_TEST_DEBUG_INDEX                                                0x4775
++#define mmBLNDV_TEST_DEBUG_DATA                                                 0x4776
++#define mmCRTCV_H_BLANK_EARLY_NUM                                               0x477d
++#define mmCRTCV_H_TOTAL                                                         0x4780
++#define mmCRTCV_H_BLANK_START_END                                               0x4781
++#define mmCRTCV_H_SYNC_A                                                        0x4782
++#define mmCRTCV_H_SYNC_A_CNTL                                                   0x4783
++#define mmCRTCV_H_SYNC_B                                                        0x4784
++#define mmCRTCV_H_SYNC_B_CNTL                                                   0x4785
++#define mmCRTCV_VBI_END                                                         0x4786
++#define mmCRTCV_V_TOTAL                                                         0x4787
++#define mmCRTCV_V_TOTAL_MIN                                                     0x4788
++#define mmCRTCV_V_TOTAL_MAX                                                     0x4789
++#define mmCRTCV_V_TOTAL_CONTROL                                                 0x478a
++#define mmCRTCV_V_TOTAL_INT_STATUS                                              0x478b
++#define mmCRTCV_VSYNC_NOM_INT_STATUS                                            0x478c
++#define mmCRTCV_V_BLANK_START_END                                               0x478d
++#define mmCRTCV_V_SYNC_A                                                        0x478e
++#define mmCRTCV_V_SYNC_A_CNTL                                                   0x478f
++#define mmCRTCV_V_SYNC_B                                                        0x4790
++#define mmCRTCV_V_SYNC_B_CNTL                                                   0x4791
++#define mmCRTCV_DTMTEST_CNTL                                                    0x4792
++#define mmCRTCV_DTMTEST_STATUS_POSITION                                         0x4793
++#define mmCRTCV_TRIGA_CNTL                                                      0x4794
++#define mmCRTCV_TRIGA_MANUAL_TRIG                                               0x4795
++#define mmCRTCV_TRIGB_CNTL                                                      0x4796
++#define mmCRTCV_TRIGB_MANUAL_TRIG                                               0x4797
++#define mmCRTCV_FORCE_COUNT_NOW_CNTL                                            0x4798
++#define mmCRTCV_FLOW_CONTROL                                                    0x4799
++#define mmCRTCV_STEREO_FORCE_NEXT_EYE                                           0x479a
++#define mmCRTCV_AVSYNC_COUNTER                                                  0x479b
++#define mmCRTCV_CONTROL                                                         0x479c
++#define mmCRTCV_BLANK_CONTROL                                                   0x479d
++#define mmCRTCV_INTERLACE_CONTROL                                               0x479e
++#define mmCRTCV_INTERLACE_STATUS                                                0x479f
++#define mmCRTCV_FIELD_INDICATION_CONTROL                                        0x47a0
++#define mmCRTCV_PIXEL_DATA_READBACK0                                            0x47a1
++#define mmCRTCV_PIXEL_DATA_READBACK1                                            0x47a2
++#define mmCRTCV_STATUS                                                          0x47a3
++#define mmCRTCV_STATUS_POSITION                                                 0x47a4
++#define mmCRTCV_NOM_VERT_POSITION                                               0x47a5
++#define mmCRTCV_STATUS_FRAME_COUNT                                              0x47a6
++#define mmCRTCV_STATUS_VF_COUNT                                                 0x47a7
++#define mmCRTCV_STATUS_HV_COUNT                                                 0x47a8
++#define mmCRTCV_COUNT_CONTROL                                                   0x47a9
++#define mmCRTCV_COUNT_RESET                                                     0x47aa
++#define mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE                                    0x47ab
++#define mmCRTCV_VERT_SYNC_CONTROL                                               0x47ac
++#define mmCRTCV_STEREO_STATUS                                                   0x47ad
++#define mmCRTCV_STEREO_CONTROL                                                  0x47ae
++#define mmCRTCV_SNAPSHOT_STATUS                                                 0x47af
++#define mmCRTCV_SNAPSHOT_CONTROL                                                0x47b0
++#define mmCRTCV_SNAPSHOT_POSITION                                               0x47b1
++#define mmCRTCV_SNAPSHOT_FRAME                                                  0x47b2
++#define mmCRTCV_START_LINE_CONTROL                                              0x47b3
++#define mmCRTCV_INTERRUPT_CONTROL                                               0x47b4
++#define mmCRTCV_UPDATE_LOCK                                                     0x47b5
++#define mmCRTCV_DOUBLE_BUFFER_CONTROL                                           0x47b6
++#define mmCRTCV_VGA_PARAMETER_CAPTURE_MODE                                      0x47b7
++#define mmCRTCV_TEST_PATTERN_CONTROL                                            0x47ba
++#define mmCRTCV_TEST_PATTERN_PARAMETERS                                         0x47bb
++#define mmCRTCV_TEST_PATTERN_COLOR                                              0x47bc
++#define mmCRTCV_MASTER_UPDATE_LOCK                                              0x47bd
++#define mmCRTCV_MASTER_UPDATE_MODE                                              0x47be
++#define mmCRTCV_MVP_INBAND_CNTL_INSERT                                          0x47bf
++#define mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER                                    0x47c0
++#define mmCRTCV_MVP_STATUS                                                      0x47c1
++#define mmCRTCV_MASTER_EN                                                       0x47c2
++#define mmCRTCV_ALLOW_STOP_OFF_V_CNT                                            0x47c3
++#define mmCRTCV_V_UPDATE_INT_STATUS                                             0x47c4
++#define mmCRTCV_OVERSCAN_COLOR                                                  0x47c8
++#define mmCRTCV_OVERSCAN_COLOR_EXT                                              0x47c9
++#define mmCRTCV_BLANK_DATA_COLOR                                                0x47ca
++#define mmCRTCV_BLANK_DATA_COLOR_EXT                                            0x47cb
++#define mmCRTCV_BLACK_COLOR                                                     0x47cc
++#define mmCRTCV_BLACK_COLOR_EXT                                                 0x47cd
++#define mmCRTCV_VERTICAL_INTERRUPT0_POSITION                                    0x47ce
++#define mmCRTCV_VERTICAL_INTERRUPT0_CONTROL                                     0x47cf
++#define mmCRTCV_VERTICAL_INTERRUPT1_POSITION                                    0x47d0
++#define mmCRTCV_VERTICAL_INTERRUPT1_CONTROL                                     0x47d1
++#define mmCRTCV_VERTICAL_INTERRUPT2_POSITION                                    0x47d2
++#define mmCRTCV_VERTICAL_INTERRUPT2_CONTROL                                     0x47d3
++#define mmCRTCV_CRC_CNTL                                                        0x47d4
++#define mmCRTCV_CRC0_WINDOWA_X_CONTROL                                          0x47d5
++#define mmCRTCV_CRC0_WINDOWA_Y_CONTROL                                          0x47d6
++#define mmCRTCV_CRC0_WINDOWB_X_CONTROL                                          0x47d7
++#define mmCRTCV_CRC0_WINDOWB_Y_CONTROL                                          0x47d8
++#define mmCRTCV_CRC0_DATA_RG                                                    0x47d9
++#define mmCRTCV_CRC0_DATA_B                                                     0x47da
++#define mmCRTCV_CRC1_WINDOWA_X_CONTROL                                          0x47db
++#define mmCRTCV_CRC1_WINDOWA_Y_CONTROL                                          0x47dc
++#define mmCRTCV_CRC1_WINDOWB_X_CONTROL                                          0x47dd
++#define mmCRTCV_CRC1_WINDOWB_Y_CONTROL                                          0x47de
++#define mmCRTCV_CRC1_DATA_RG                                                    0x47df
++#define mmCRTCV_CRC1_DATA_B                                                     0x47e0
++#define mmCRTCV_STATIC_SCREEN_CONTROL                                           0x47e7
++#define mmCRTCV_3D_STRUCTURE_CONTROL                                            0x4778
++#define mmCRTCV_GSL_VSYNC_GAP                                                   0x4779
++#define mmCRTCV_GSL_WINDOW                                                      0x477a
++#define mmCRTCV_GSL_CONTROL                                                     0x477b
++#define mmCRTCV_TEST_DEBUG_INDEX                                                0x47c6
++#define mmCRTCV_TEST_DEBUG_DATA                                                 0x47c7
++#define mmXDMA_MC_PCIE_CLIENT_CONFIG                                            0x3e0
++#define mmXDMA_LOCAL_SURFACE_TILING1                                            0x3e1
++#define mmXDMA_LOCAL_SURFACE_TILING2                                            0x3e2
++#define mmXDMA_INTERRUPT                                                        0x3e3
++#define mmXDMA_CLOCK_GATING_CNTL                                                0x3e4
++#define mmXDMA_MEM_POWER_CNTL                                                   0x3e6
++#define mmXDMA_IF_BIF_STATUS                                                    0x3e7
++#define mmXDMA_PERF_MEAS_STATUS                                                 0x3e8
++#define mmXDMA_IF_STATUS                                                        0x3e9
++#define mmXDMA_TEST_DEBUG_INDEX                                                 0x3ea
++#define mmXDMA_TEST_DEBUG_DATA                                                  0x3eb
++#define mmXDMA_RBBMIF_RDWR_CNTL                                                 0x3f8
++#define mmXDMA_PG_CONTROL                                                       0x3f9
++#define mmXDMA_PG_WDATA                                                         0x3fa
++#define mmXDMA_PG_STATUS                                                        0x3fb
++#define mmXDMA_AON_TEST_DEBUG_INDEX                                             0x3fc
++#define mmXDMA_AON_TEST_DEBUG_DATA                                              0x3fd
++#define mmXDMA_MSTR_CNTL                                                        0x3ec
++#define mmXDMA_MSTR_STATUS                                                      0x3ed
++#define mmXDMA_MSTR_MEM_CLIENT_CONFIG                                           0x3ee
++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR                                     0x3ef
++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH                                0x3f0
++#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH                                         0x3f1
++#define mmXDMA_MSTR_CMD_URGENT_CNTL                                             0x3f2
++#define mmXDMA_MSTR_MEM_URGENT_CNTL                                             0x3f3
++#define mmXDMA_MSTR_PCIE_NACK_STATUS                                            0x3f5
++#define mmXDMA_MSTR_MEM_NACK_STATUS                                             0x3f6
++#define mmXDMA_MSTR_VSYNC_GSL_CHECK                                             0x3f7
++#define mmXDMA_MSTR_PIPE_CNTL                                                   0x400
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL                                   0x400
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL                                   0x410
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL                                   0x420
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL                                   0x430
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL                                   0x440
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL                                   0x450
++#define mmXDMA_MSTR_READ_COMMAND                                                0x401
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND                                0x401
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND                                0x411
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND                                0x421
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND                                0x431
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND                                0x441
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND                                0x451
++#define mmXDMA_MSTR_CHANNEL_DIM                                                 0x402
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM                                 0x402
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM                                 0x412
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM                                 0x422
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM                                 0x432
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM                                 0x442
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM                                 0x452
++#define mmXDMA_MSTR_HEIGHT                                                      0x403
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT                                      0x403
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT                                      0x413
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT                                      0x423
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT                                      0x433
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT                                      0x443
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT                                      0x453
++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE                                         0x404
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x404
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x414
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x424
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x434
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x444
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x454
++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                                    0x405
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x405
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x415
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x425
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x435
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x445
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x455
++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS                                          0x406
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x406
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x416
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x426
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x436
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x446
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x456
++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                                     0x407
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x407
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x417
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x427
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x437
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x447
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x457
++#define mmXDMA_MSTR_CACHE_BASE_ADDR                                             0x408
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR                             0x408
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR                             0x418
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR                             0x428
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR                             0x438
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR                             0x448
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR                             0x458
++#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH                                        0x409
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x409
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x419
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x429
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x439
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x449
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x459
++#define mmXDMA_MSTR_CACHE                                                       0x40a
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE                                       0x40a
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE                                       0x41a
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE                                       0x42a
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE                                       0x43a
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE                                       0x44a
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE                                       0x45a
++#define mmXDMA_MSTR_CHANNEL_START                                               0x40b
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START                               0x40b
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START                               0x41b
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START                               0x42b
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START                               0x43b
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START                               0x44b
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START                               0x45b
++#define mmXDMA_MSTR_PERFMEAS_STATUS                                             0x40e
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS                             0x40e
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS                             0x41e
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS                             0x42e
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS                             0x43e
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS                             0x44e
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS                             0x45e
++#define mmXDMA_MSTR_PERFMEAS_CNTL                                               0x40f
++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL                               0x40f
++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL                               0x41f
++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL                               0x42f
++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL                               0x43f
++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL                               0x44f
++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL                               0x45f
++#define mmXDMA_SLV_CNTL                                                         0x460
++#define mmXDMA_SLV_MEM_CLIENT_CONFIG                                            0x461
++#define mmXDMA_SLV_SLS_PITCH                                                    0x462
++#define mmXDMA_SLV_READ_URGENT_CNTL                                             0x463
++#define mmXDMA_SLV_WRITE_URGENT_CNTL                                            0x464
++#define mmXDMA_SLV_WB_RATE_CNTL                                                 0x465
++#define mmXDMA_SLV_READ_LATENCY_MINMAX                                          0x466
++#define mmXDMA_SLV_READ_LATENCY_AVE                                             0x467
++#define mmXDMA_SLV_PCIE_NACK_STATUS                                             0x468
++#define mmXDMA_SLV_MEM_NACK_STATUS                                              0x469
++#define mmXDMA_SLV_RDRET_BUF_STATUS                                             0x46a
++#define mmXDMA_SLV_READ_LATENCY_TIMER                                           0x46b
++#define mmXDMA_SLV_FLIP_PENDING                                                 0x46c
++#define mmXDMA_SLV_CHANNEL_CNTL                                                 0x470
++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL                               0x470
++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL                               0x478
++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL                               0x480
++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL                               0x488
++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL                               0x490
++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL                               0x498
++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS                                           0x471
++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x471
++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x479
++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x481
++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x489
++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x491
++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x499
++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                                      0x472
++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x472
++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x47a
++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x482
++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x48a
++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x492
++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x49a
++
++#endif /* DCE_11_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h
+new file mode 100644
+index 0000000..d74bca7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h
+@@ -0,0 +1,6129 @@
++/*
++ * DCE_11_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_11_0_ENUM_H
++#define DCE_11_0_ENUM_H
++
++typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
++	CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL        = 0x0,
++	CRTC_CONTROL_CRTC_START_POINT_CNTL_DP            = 0x1,
++} CRTC_CONTROL_CRTC_START_POINT_CNTL;
++typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
++	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL       = 0x0,
++	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP           = 0x1,
++} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
++typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
++	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE     = 0x0,
++	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
++	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED    = 0x2,
++	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
++} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
++typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
++	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE    = 0x0,
++	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE     = 0x1,
++} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
++typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
++	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
++	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
++} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
++typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
++	CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE              = 0x0,
++	CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE               = 0x1,
++} CRTC_CONTROL_CRTC_SOF_PULL_EN;
++typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
++	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE       = 0x0,
++	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE        = 0x1,
++} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
++	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x0,
++	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE   = 0x1,
++} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
++	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x0,
++	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE   = 0x1,
++} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
++} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
++	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
++	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
++} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
++	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
++	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
++} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
++	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
++} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
++typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
++	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
++	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
++} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
++typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
++	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
++	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
++} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
++typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
++	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE       = 0x0,
++	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE        = 0x1,
++} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
++typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
++	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE     = 0x0,
++	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE      = 0x1,
++} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x7,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x8,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x9,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0xa,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1    = 0xb,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2    = 0xc,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO   = 0xf,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0   = 0x10,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1   = 0x11,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2   = 0x12,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON   = 0x13,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
++} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
++} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
++} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE           = 0x0,
++	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE            = 0x1,
++} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x7,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x8,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x9,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0xa,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1    = 0xb,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2    = 0xc,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO   = 0xf,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0   = 0x10,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1   = 0x11,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2   = 0x12,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON   = 0x13,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
++} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
++} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
++} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE           = 0x0,
++	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE            = 0x1,
++} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
++	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
++typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10,
++} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
++typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
++} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
++typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
++	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
++} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
++typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
++	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
++	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
++	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
++	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
++} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
++typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
++	CRTC_CONTROL_CRTC_MASTER_EN_FALSE                = 0x0,
++	CRTC_CONTROL_CRTC_MASTER_EN_TRUE                 = 0x1,
++} CRTC_CONTROL_CRTC_MASTER_EN;
++typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
++	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE      = 0x0,
++	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE       = 0x1,
++} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
++typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
++	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE      = 0x0,
++	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE       = 0x1,
++} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
++typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
++	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
++	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
++} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
++typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
++	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
++	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
++	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
++	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
++} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
++typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
++	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
++	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
++} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
++typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
++	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
++	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
++} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
++typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
++	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x0,
++	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE   = 0x1,
++} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
++typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
++	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
++	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
++} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
++typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
++	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
++	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
++} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
++typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
++	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
++	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
++	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
++	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
++} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
++	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
++	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
++} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
++	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
++	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
++} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
++	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
++	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
++} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
++	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE         = 0x0,
++	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE          = 0x1,
++} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
++typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
++	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE   = 0x0,
++	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE    = 0x1,
++} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
++typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
++	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
++	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
++	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
++	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
++} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
++typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
++	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
++	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
++} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
++typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
++	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
++	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
++} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
++typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
++	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
++	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
++} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
++typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
++	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE   = 0x0,
++	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE    = 0x1,
++} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE   = 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE   = 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
++	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
++	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
++	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
++} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
++typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
++	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE          = 0x0,
++	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE           = 0x1,
++} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
++typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
++	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
++	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
++} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
++typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
++	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
++	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
++} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
++typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
++	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
++	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
++} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
++	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
++typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
++	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE      = 0x0,
++	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE       = 0x1,
++} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
++typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
++	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
++	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
++} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
++typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
++	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE   = 0x0,
++	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE    = 0x1,
++} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
++typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
++	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN    = 0x0,
++	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA     = 0x1,
++	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA     = 0x2,
++	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE     = 0x3,
++} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
++typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
++	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
++	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
++	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
++	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
++} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
++typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
++	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
++	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
++	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
++} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
++typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
++	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE        = 0x0,
++	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE         = 0x1,
++} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
++typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
++	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
++	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
++} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
++typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
++	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
++	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
++} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
++typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
++	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
++typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
++	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
++typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
++	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
++typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
++	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
++typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
++	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
++typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
++	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
++	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
++} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
++typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
++	CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE                  = 0x0,
++	CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE                   = 0x1,
++} CRTC_CRC_CNTL_CRTC_CRC_EN;
++typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
++	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE             = 0x0,
++	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE              = 0x1,
++} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
++typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
++	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT          = 0x0,
++	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT         = 0x1,
++	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES     = 0x2,
++	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS   = 0x3,
++} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
++typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
++	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP        = 0x0,
++	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM     = 0x1,
++	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
++	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
++} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
++typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
++	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
++	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
++} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
++typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB          = 0x0,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B         = 0x1,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB         = 0x2,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B        = 0x3,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB          = 0x4,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B         = 0x5,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB         = 0x6,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B        = 0x7,
++} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
++typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB          = 0x0,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B         = 0x1,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB         = 0x2,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B        = 0x3,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB          = 0x4,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B         = 0x5,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB         = 0x6,
++	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B        = 0x7,
++} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
++typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
++	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
++	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
++} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
++typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
++	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
++	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
++} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
++typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
++	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
++	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
++} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
++	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
++typedef enum CRTC_V_SYNC_A_POL {
++	CRTC_V_SYNC_A_POL_HIGH                           = 0x0,
++	CRTC_V_SYNC_A_POL_LOW                            = 0x1,
++} CRTC_V_SYNC_A_POL;
++typedef enum CRTC_H_SYNC_A_POL {
++	CRTC_H_SYNC_A_POL_HIGH                           = 0x0,
++	CRTC_H_SYNC_A_POL_LOW                            = 0x1,
++} CRTC_H_SYNC_A_POL;
++typedef enum CRTC_HORZ_REPETITION_COUNT {
++	CRTC_HORZ_REPETITION_COUNT_0                     = 0x0,
++	CRTC_HORZ_REPETITION_COUNT_1                     = 0x1,
++	CRTC_HORZ_REPETITION_COUNT_2                     = 0x2,
++	CRTC_HORZ_REPETITION_COUNT_3                     = 0x3,
++	CRTC_HORZ_REPETITION_COUNT_4                     = 0x4,
++	CRTC_HORZ_REPETITION_COUNT_5                     = 0x5,
++	CRTC_HORZ_REPETITION_COUNT_6                     = 0x6,
++	CRTC_HORZ_REPETITION_COUNT_7                     = 0x7,
++	CRTC_HORZ_REPETITION_COUNT_8                     = 0x8,
++	CRTC_HORZ_REPETITION_COUNT_9                     = 0x9,
++	CRTC_HORZ_REPETITION_COUNT_10                    = 0xa,
++	CRTC_HORZ_REPETITION_COUNT_11                    = 0xb,
++	CRTC_HORZ_REPETITION_COUNT_12                    = 0xc,
++	CRTC_HORZ_REPETITION_COUNT_13                    = 0xd,
++	CRTC_HORZ_REPETITION_COUNT_14                    = 0xe,
++	CRTC_HORZ_REPETITION_COUNT_15                    = 0xf,
++} CRTC_HORZ_REPETITION_COUNT;
++typedef enum PERFCOUNTER_CVALUE_SEL {
++	PERFCOUNTER_CVALUE_SEL_47_0                      = 0x0,
++	PERFCOUNTER_CVALUE_SEL_15_0                      = 0x1,
++	PERFCOUNTER_CVALUE_SEL_31_16                     = 0x2,
++	PERFCOUNTER_CVALUE_SEL_47_32                     = 0x3,
++	PERFCOUNTER_CVALUE_SEL_11_0                      = 0x4,
++	PERFCOUNTER_CVALUE_SEL_23_12                     = 0x5,
++	PERFCOUNTER_CVALUE_SEL_35_24                     = 0x6,
++	PERFCOUNTER_CVALUE_SEL_47_36                     = 0x7,
++} PERFCOUNTER_CVALUE_SEL;
++typedef enum PERFCOUNTER_INC_MODE {
++	PERFCOUNTER_INC_MODE_MULTI_BIT                   = 0x0,
++	PERFCOUNTER_INC_MODE_BOTH_EDGE                   = 0x1,
++	PERFCOUNTER_INC_MODE_LSB                         = 0x2,
++	PERFCOUNTER_INC_MODE_POS_EDGE                    = 0x3,
++} PERFCOUNTER_INC_MODE;
++typedef enum PERFCOUNTER_HW_CNTL_SEL {
++	PERFCOUNTER_HW_CNTL_SEL_RUNEN                    = 0x0,
++	PERFCOUNTER_HW_CNTL_SEL_CNTOFF                   = 0x1,
++} PERFCOUNTER_HW_CNTL_SEL;
++typedef enum PERFCOUNTER_RUNEN_MODE {
++	PERFCOUNTER_RUNEN_MODE_LEVEL                     = 0x0,
++	PERFCOUNTER_RUNEN_MODE_EDGE                      = 0x1,
++} PERFCOUNTER_RUNEN_MODE;
++typedef enum PERFCOUNTER_CNTOFF_START_DIS {
++	PERFCOUNTER_CNTOFF_START_ENABLE                  = 0x0,
++	PERFCOUNTER_CNTOFF_START_DISABLE                 = 0x1,
++} PERFCOUNTER_CNTOFF_START_DIS;
++typedef enum PERFCOUNTER_RESTART_EN {
++	PERFCOUNTER_RESTART_DISABLE                      = 0x0,
++	PERFCOUNTER_RESTART_ENABLE                       = 0x1,
++} PERFCOUNTER_RESTART_EN;
++typedef enum PERFCOUNTER_INT_EN {
++	PERFCOUNTER_INT_DISABLE                          = 0x0,
++	PERFCOUNTER_INT_ENABLE                           = 0x1,
++} PERFCOUNTER_INT_EN;
++typedef enum PERFCOUNTER_OFF_MASK {
++	PERFCOUNTER_OFF_MASK_DISABLE                     = 0x0,
++	PERFCOUNTER_OFF_MASK_ENABLE                      = 0x1,
++} PERFCOUNTER_OFF_MASK;
++typedef enum PERFCOUNTER_ACTIVE {
++	PERFCOUNTER_IS_IDLE                              = 0x0,
++	PERFCOUNTER_IS_ACTIVE                            = 0x1,
++} PERFCOUNTER_ACTIVE;
++typedef enum PERFCOUNTER_INT_TYPE {
++	PERFCOUNTER_INT_TYPE_LEVEL                       = 0x0,
++	PERFCOUNTER_INT_TYPE_PULSE                       = 0x1,
++} PERFCOUNTER_INT_TYPE;
++typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
++	PERFCOUNTER_COUNTED_VALUE_TYPE_ACC               = 0x0,
++	PERFCOUNTER_COUNTED_VALUE_TYPE_MAX               = 0x1,
++} PERFCOUNTER_COUNTED_VALUE_TYPE;
++typedef enum PERFCOUNTER_CNTL_SEL {
++	PERFCOUNTER_CNTL_SEL_0                           = 0x0,
++	PERFCOUNTER_CNTL_SEL_1                           = 0x1,
++	PERFCOUNTER_CNTL_SEL_2                           = 0x2,
++	PERFCOUNTER_CNTL_SEL_3                           = 0x3,
++	PERFCOUNTER_CNTL_SEL_4                           = 0x4,
++	PERFCOUNTER_CNTL_SEL_5                           = 0x5,
++	PERFCOUNTER_CNTL_SEL_6                           = 0x6,
++	PERFCOUNTER_CNTL_SEL_7                           = 0x7,
++} PERFCOUNTER_CNTL_SEL;
++typedef enum PERFCOUNTER_CNT0_STATE {
++	PERFCOUNTER_CNT0_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT0_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT0_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT0_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT0_STATE;
++typedef enum PERFCOUNTER_STATE_SEL0 {
++	PERFCOUNTER_STATE_SEL0_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL0_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL0;
++typedef enum PERFCOUNTER_CNT1_STATE {
++	PERFCOUNTER_CNT1_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT1_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT1_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT1_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT1_STATE;
++typedef enum PERFCOUNTER_STATE_SEL1 {
++	PERFCOUNTER_STATE_SEL1_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL1_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL1;
++typedef enum PERFCOUNTER_CNT2_STATE {
++	PERFCOUNTER_CNT2_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT2_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT2_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT2_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT2_STATE;
++typedef enum PERFCOUNTER_STATE_SEL2 {
++	PERFCOUNTER_STATE_SEL2_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL2_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL2;
++typedef enum PERFCOUNTER_CNT3_STATE {
++	PERFCOUNTER_CNT3_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT3_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT3_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT3_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT3_STATE;
++typedef enum PERFCOUNTER_STATE_SEL3 {
++	PERFCOUNTER_STATE_SEL3_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL3_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL3;
++typedef enum PERFCOUNTER_CNT4_STATE {
++	PERFCOUNTER_CNT4_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT4_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT4_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT4_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT4_STATE;
++typedef enum PERFCOUNTER_STATE_SEL4 {
++	PERFCOUNTER_STATE_SEL4_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL4_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL4;
++typedef enum PERFCOUNTER_CNT5_STATE {
++	PERFCOUNTER_CNT5_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT5_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT5_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT5_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT5_STATE;
++typedef enum PERFCOUNTER_STATE_SEL5 {
++	PERFCOUNTER_STATE_SEL5_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL5_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL5;
++typedef enum PERFCOUNTER_CNT6_STATE {
++	PERFCOUNTER_CNT6_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT6_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT6_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT6_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT6_STATE;
++typedef enum PERFCOUNTER_STATE_SEL6 {
++	PERFCOUNTER_STATE_SEL6_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL6_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL6;
++typedef enum PERFCOUNTER_CNT7_STATE {
++	PERFCOUNTER_CNT7_STATE_RESET                     = 0x0,
++	PERFCOUNTER_CNT7_STATE_START                     = 0x1,
++	PERFCOUNTER_CNT7_STATE_FREEZE                    = 0x2,
++	PERFCOUNTER_CNT7_STATE_HW                        = 0x3,
++} PERFCOUNTER_CNT7_STATE;
++typedef enum PERFCOUNTER_STATE_SEL7 {
++	PERFCOUNTER_STATE_SEL7_GLOBAL                    = 0x0,
++	PERFCOUNTER_STATE_SEL7_LOCAL                     = 0x1,
++} PERFCOUNTER_STATE_SEL7;
++typedef enum PERFMON_STATE {
++	PERFMON_STATE_RESET                              = 0x0,
++	PERFMON_STATE_START                              = 0x1,
++	PERFMON_STATE_FREEZE                             = 0x2,
++	PERFMON_STATE_HW                                 = 0x3,
++} PERFMON_STATE;
++typedef enum PERFMON_CNTOFF_AND_OR {
++	PERFMON_CNTOFF_OR                                = 0x0,
++	PERFMON_CNTOFF_AND                               = 0x1,
++} PERFMON_CNTOFF_AND_OR;
++typedef enum PERFMON_CNTOFF_INT_EN {
++	PERFMON_CNTOFF_INT_DISABLE                       = 0x0,
++	PERFMON_CNTOFF_INT_ENABLE                        = 0x1,
++} PERFMON_CNTOFF_INT_EN;
++typedef enum PERFMON_CNTOFF_INT_TYPE {
++	PERFMON_CNTOFF_INT_TYPE_LEVEL                    = 0x0,
++	PERFMON_CNTOFF_INT_TYPE_PULSE                    = 0x1,
++} PERFMON_CNTOFF_INT_TYPE;
++typedef enum LptNumBanks {
++	LPT_NUM_BANKS_2BANK                              = 0x0,
++	LPT_NUM_BANKS_4BANK                              = 0x1,
++	LPT_NUM_BANKS_8BANK                              = 0x2,
++	LPT_NUM_BANKS_16BANK                             = 0x3,
++	LPT_NUM_BANKS_32BANK                             = 0x4,
++} LptNumBanks;
++typedef enum DCIO_DC_GENERICA_SEL {
++	DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
++	DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
++	DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
++	DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
++	DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
++	DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
++	DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
++	DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
++	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
++	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
++	DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
++	DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
++	DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
++	DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
++	DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
++	DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
++	DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
++	DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
++} DCIO_DC_GENERICA_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
++	DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
++	DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
++	DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
++	DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
++	DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
++	DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
++	DCIO_UNIPHYG_TEST_REFDIV_CLK                     = 0x6,
++	DCIO_UNIPHYLPA_TEST_REFDIV_CLK                   = 0x7,
++	DCIO_UNIPHYLPB_TEST_REFDIV_CLK                   = 0x8,
++} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
++	DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
++	DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
++	DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
++	DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
++	DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
++	DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
++	DCIO_UNIPHYG_FBDIV_CLK                           = 0x6,
++	DCIO_UNIPHYLPA_FBDIV_CLK                         = 0x7,
++	DCIO_UNIPHYLPB_FBDIV_CLK                         = 0x8,
++} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
++	DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
++	DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
++	DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
++	DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
++	DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
++	DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
++	DCIO_UNIPHYG_FBDIV_SSC_CLK                       = 0x6,
++	DCIO_UNIPHYLPA_FBDIV_SSC_CLK                     = 0x7,
++	DCIO_UNIPHYLPB_FBDIV_SSC_CLK                     = 0x8,
++} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
++	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
++	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
++	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
++	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
++	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
++	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
++	DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2                 = 0x6,
++	DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2               = 0x7,
++	DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2               = 0x8,
++} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
++typedef enum DCIO_DC_GENERICB_SEL {
++	DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
++	DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
++	DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
++	DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
++	DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
++	DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
++	DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
++	DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
++	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
++	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
++	DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
++	DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
++	DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
++	DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
++	DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
++	DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
++} DCIO_DC_GENERICB_SEL;
++typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
++	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
++	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,
++} DCIO_DC_PAD_EXTERN_SIG_SEL;
++typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
++	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA                 = 0x0,
++	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE       = 0x1,
++	DCIO_MVP_PIXEL_SRC_STATUS_CRTC                   = 0x2,
++	DCIO_MVP_PIXEL_SRC_STATUS_LB                     = 0x3,
++} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
++typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
++	DCIO_HSYNCA_OUTPUT_SEL_DISABLE                   = 0x0,
++	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
++	DCIO_HSYNCA_OUTPUT_SEL_PPLL2                     = 0x2,
++	DCIO_HSYNCA_OUTPUT_SEL_RESERVED                  = 0x3,
++} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
++typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
++	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE                = 0x0,
++	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1                  = 0x1,
++	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
++	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3        = 0x3,
++} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
++typedef enum DCIO_DC_GPIO_VIP_DEBUG {
++	DCIO_DC_GPIO_VIP_DEBUG_NORMAL                    = 0x0,
++	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG                    = 0x1,
++} DCIO_DC_GPIO_VIP_DEBUG;
++typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
++	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL                  = 0x0,
++	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF                = 0x1,
++	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2         = 0x2,
++	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3         = 0x3,
++} DCIO_DC_GPIO_MACRO_DEBUG;
++typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
++	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL       = 0x0,
++	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP         = 0x1,
++} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
++typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
++	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS            = 0x0,
++	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE            = 0x1,
++} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
++typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
++	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL                 = 0x0,
++	DCIO_DPRX_LOOPBACK_ENABLE_LOOP                   = 0x1,
++} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
++typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
++	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
++} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
++typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
++	DCIO_UNIPHY_CHANNEL_NO_INVERSION                 = 0x0,
++	DCIO_UNIPHY_CHANNEL_INVERTED                     = 0x1,
++} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
++typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW        = 0x0,
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW           = 0x1,
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
++	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
++} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
++typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0              = 0x0,
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1              = 0x1,
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2              = 0x2,
++	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3              = 0x3,
++} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
++typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
++	DCIO_VIP_MUX_EN_DVO                              = 0x0,
++	DCIO_VIP_MUX_EN_VIP                              = 0x1,
++} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
++typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
++	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT                = 0x0,
++	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
++} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
++typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
++	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT                = 0x0,
++	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
++} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
++	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
++	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
++	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF           = 0x0,
++	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON            = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
++	DCIO_LVTMA_SYNCEN_POL_NON_INVERT                 = 0x0,
++	DCIO_LVTMA_SYNCEN_POL_INVERT                     = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
++	DCIO_LVTMA_DIGON_OFF                             = 0x0,
++	DCIO_LVTMA_DIGON_ON                              = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
++	DCIO_LVTMA_DIGON_POL_NON_INVERT                  = 0x0,
++	DCIO_LVTMA_DIGON_POL_INVERT                      = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
++	DCIO_LVTMA_BLON_OFF                              = 0x0,
++	DCIO_LVTMA_BLON_ON                               = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
++	DCIO_LVTMA_BLON_POL_NON_INVERT                   = 0x0,
++	DCIO_LVTMA_BLON_POL_INVERT                       = 0x1,
++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
++typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
++	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON              = 0x0,
++	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE          = 0x1,
++} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
++typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
++	DCIO_BL_PWM_FRACTIONAL_DISABLE                   = 0x0,
++	DCIO_BL_PWM_FRACTIONAL_ENABLE                    = 0x1,
++} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
++typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
++	DCIO_BL_PWM_DISABLE                              = 0x0,
++	DCIO_BL_PWM_ENABLE                               = 0x1,
++} DCIO_BL_PWM_CNTL_BL_PWM_EN;
++typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL       = 0x0,
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1       = 0x1,
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2       = 0x2,
++	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3       = 0x3,
++} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
++typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
++	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE              = 0x0,
++	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE               = 0x1,
++} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
++typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
++	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL      = 0x0,
++	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM         = 0x1,
++} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
++typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
++	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE                = 0x0,
++	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE                 = 0x1,
++} DCIO_BL_PWM_GRP1_REG_LOCK;
++typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
++	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE   = 0x0,
++	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE    = 0x1,
++} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
++typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
++	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
++} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
++typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
++	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
++	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
++} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
++typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
++	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE       = 0x0,
++	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE      = 0x1,
++} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
++typedef enum DCIO_GSL_SEL {
++	DCIO_GSL_SEL_GROUP_0                             = 0x0,
++	DCIO_GSL_SEL_GROUP_1                             = 0x1,
++	DCIO_GSL_SEL_GROUP_2                             = 0x2,
++} DCIO_GSL_SEL;
++typedef enum DCIO_GENLK_CLK_GSL_MASK {
++	DCIO_GENLK_CLK_GSL_MASK_NO                       = 0x0,
++	DCIO_GENLK_CLK_GSL_MASK_TIMING                   = 0x1,
++	DCIO_GENLK_CLK_GSL_MASK_STEREO                   = 0x2,
++} DCIO_GENLK_CLK_GSL_MASK;
++typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
++	DCIO_GENLK_VSYNC_GSL_MASK_NO                     = 0x0,
++	DCIO_GENLK_VSYNC_GSL_MASK_TIMING                 = 0x1,
++	DCIO_GENLK_VSYNC_GSL_MASK_STEREO                 = 0x2,
++} DCIO_GENLK_VSYNC_GSL_MASK;
++typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
++	DCIO_SWAPLOCK_A_GSL_MASK_NO                      = 0x0,
++	DCIO_SWAPLOCK_A_GSL_MASK_TIMING                  = 0x1,
++	DCIO_SWAPLOCK_A_GSL_MASK_STEREO                  = 0x2,
++} DCIO_SWAPLOCK_A_GSL_MASK;
++typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
++	DCIO_SWAPLOCK_B_GSL_MASK_NO                      = 0x0,
++	DCIO_SWAPLOCK_B_GSL_MASK_TIMING                  = 0x1,
++	DCIO_SWAPLOCK_B_GSL_MASK_STEREO                  = 0x2,
++} DCIO_SWAPLOCK_B_GSL_MASK;
++typedef enum DCIO_GSL_VSYNC_SEL {
++	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
++	DCIO_GSL_VSYNC_SEL_PIPE1                         = 0x1,
++	DCIO_GSL_VSYNC_SEL_PIPE2                         = 0x2,
++	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
++	DCIO_GSL_VSYNC_SEL_PIPE4                         = 0x4,
++	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
++} DCIO_GSL_VSYNC_SEL;
++typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
++	DCIO_GSL0_TIMING_SYNC_SEL_PIPE                   = 0x0,
++	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
++	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
++	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
++	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
++} DCIO_GSL0_TIMING_SYNC_SEL;
++typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
++	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
++} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
++typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
++	DCIO_GSL1_TIMING_SYNC_SEL_PIPE                   = 0x0,
++	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
++	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
++	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
++	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
++} DCIO_GSL1_TIMING_SYNC_SEL;
++typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
++	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
++} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
++typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
++	DCIO_GSL2_TIMING_SYNC_SEL_PIPE                   = 0x0,
++	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
++	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
++	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
++	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
++} DCIO_GSL2_TIMING_SYNC_SEL;
++typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
++	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
++} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
++typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
++	DCIO_GPU_TIMER_START_0_END_27                    = 0x0,
++	DCIO_GPU_TIMER_START_1_END_28                    = 0x1,
++	DCIO_GPU_TIMER_START_2_END_29                    = 0x2,
++	DCIO_GPU_TIMER_START_3_END_30                    = 0x3,
++	DCIO_GPU_TIMER_START_4_END_31                    = 0x4,
++	DCIO_GPU_TIMER_START_6_END_33                    = 0x5,
++	DCIO_GPU_TIMER_START_8_END_35                    = 0x6,
++	DCIO_GPU_TIMER_START_10_END_37                   = 0x7,
++} DCIO_DC_GPU_TIMER_START_POSITION;
++typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
++	DCIO_TEST_CLK_SEL_DISPCLK                        = 0x0,
++	DCIO_TEST_CLK_SEL_GATED_DISPCLK                  = 0x1,
++	DCIO_TEST_CLK_SEL_SCLK                           = 0x2,
++} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
++typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
++	DCIO_DISPCLK_R_DCIO_GATE_DISABLE                 = 0x0,
++	DCIO_DISPCLK_R_DCIO_GATE_ENABLE                  = 0x1,
++} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
++typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
++	DCIO_EXT_VSYNC_MUX_SWAPLOCKB                     = 0x0,
++	DCIO_EXT_VSYNC_MUX_CRTC0                         = 0x1,
++	DCIO_EXT_VSYNC_MUX_CRTC1                         = 0x2,
++	DCIO_EXT_VSYNC_MUX_CRTC2                         = 0x3,
++	DCIO_EXT_VSYNC_MUX_CRTC3                         = 0x4,
++	DCIO_EXT_VSYNC_MUX_CRTC4                         = 0x5,
++	DCIO_EXT_VSYNC_MUX_CRTC5                         = 0x6,
++	DCIO_EXT_VSYNC_MUX_GENERICB                      = 0x7,
++} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
++typedef enum DCIO_DCO_EXT_VSYNC_MASK {
++	DCIO_EXT_VSYNC_MASK_NONE                         = 0x0,
++	DCIO_EXT_VSYNC_MASK_PIPE0                        = 0x1,
++	DCIO_EXT_VSYNC_MASK_PIPE1                        = 0x2,
++	DCIO_EXT_VSYNC_MASK_PIPE2                        = 0x3,
++	DCIO_EXT_VSYNC_MASK_PIPE3                        = 0x4,
++	DCIO_EXT_VSYNC_MASK_PIPE4                        = 0x5,
++	DCIO_EXT_VSYNC_MASK_PIPE5                        = 0x6,
++	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE               = 0x7,
++} DCIO_DCO_EXT_VSYNC_MASK;
++typedef enum DCIO_DBG_OUT_PIN_SEL {
++	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT                   = 0x0,
++	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT                  = 0x1,
++} DCIO_DBG_OUT_PIN_SEL;
++typedef enum DCIO_DBG_OUT_12BIT_SEL {
++	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT                 = 0x0,
++	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT                 = 0x1,
++	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT                = 0x2,
++	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE                  = 0x3,
++} DCIO_DBG_OUT_12BIT_SEL;
++typedef enum DCIO_DSYNC_SOFT_RESET {
++	DCIO_DSYNC_SOFT_RESET_DEASSERT                   = 0x0,
++	DCIO_DSYNC_SOFT_RESET_ASSERT                     = 0x1,
++} DCIO_DSYNC_SOFT_RESET;
++typedef enum DCIO_DACA_SOFT_RESET {
++	DCIO_DACA_SOFT_RESET_DEASSERT                    = 0x0,
++	DCIO_DACA_SOFT_RESET_ASSERT                      = 0x1,
++} DCIO_DACA_SOFT_RESET;
++typedef enum DCIO_DCRXPHY_SOFT_RESET {
++	DCIO_DCRXPHY_SOFT_RESET_DEASSERT                 = 0x0,
++	DCIO_DCRXPHY_SOFT_RESET_ASSERT                   = 0x1,
++} DCIO_DCRXPHY_SOFT_RESET;
++typedef enum DCIO_DPHY_LANE_SEL {
++	DCIO_DPHY_LANE_SEL_LANE0                         = 0x0,
++	DCIO_DPHY_LANE_SEL_LANE1                         = 0x1,
++	DCIO_DPHY_LANE_SEL_LANE2                         = 0x2,
++	DCIO_DPHY_LANE_SEL_LANE3                         = 0x3,
++} DCIO_DPHY_LANE_SEL;
++typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE     = 0x0,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE     = 0x1,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE     = 0x2,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE     = 0x3,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE     = 0x4,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE     = 0x5,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP       = 0xc,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP       = 0xd,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP       = 0xe,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP       = 0xf,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP       = 0x10,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP       = 0x11,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM    = 0x18,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM    = 0x19,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM    = 0x1a,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM    = 0x1b,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM    = 0x1c,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM    = 0x1d,
++	DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP    = 0x24,
++	DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP    = 0x25,
++} DCIO_DC_GPU_TIMER_READ_SELECT;
++typedef enum DCIO_IMPCAL_STEP_DELAY {
++	DCIO_IMPCAL_STEP_DELAY_1us                       = 0x0,
++	DCIO_IMPCAL_STEP_DELAY_2us                       = 0x1,
++	DCIO_IMPCAL_STEP_DELAY_3us                       = 0x2,
++	DCIO_IMPCAL_STEP_DELAY_4us                       = 0x3,
++	DCIO_IMPCAL_STEP_DELAY_5us                       = 0x4,
++	DCIO_IMPCAL_STEP_DELAY_6us                       = 0x5,
++	DCIO_IMPCAL_STEP_DELAY_7us                       = 0x6,
++	DCIO_IMPCAL_STEP_DELAY_8us                       = 0x7,
++	DCIO_IMPCAL_STEP_DELAY_9us                       = 0x8,
++	DCIO_IMPCAL_STEP_DELAY_10us                      = 0x9,
++	DCIO_IMPCAL_STEP_DELAY_11us                      = 0xa,
++	DCIO_IMPCAL_STEP_DELAY_12us                      = 0xb,
++	DCIO_IMPCAL_STEP_DELAY_13us                      = 0xc,
++	DCIO_IMPCAL_STEP_DELAY_14us                      = 0xd,
++	DCIO_IMPCAL_STEP_DELAY_15us                      = 0xe,
++	DCIO_IMPCAL_STEP_DELAY_16us                      = 0xf,
++} DCIO_IMPCAL_STEP_DELAY;
++typedef enum DCIO_UNIPHY_IMPCAL_SEL {
++	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE               = 0x0,
++	DCIO_UNIPHY_IMPCAL_SEL_BINARY                    = 0x1,
++} DCIO_UNIPHY_IMPCAL_SEL;
++typedef enum DCIOCHIP_HPD_SEL {
++	DCIOCHIP_HPD_SEL_ASYNC                           = 0x0,
++	DCIOCHIP_HPD_SEL_CLOCKED                         = 0x1,
++} DCIOCHIP_HPD_SEL;
++typedef enum DCIOCHIP_PAD_MODE {
++	DCIOCHIP_PAD_MODE_DDC                            = 0x0,
++	DCIOCHIP_PAD_MODE_DP                             = 0x1,
++} DCIOCHIP_PAD_MODE;
++typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
++	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C                   = 0x0,
++	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX                   = 0x1,
++} DCIOCHIP_AUXSLAVE_PAD_MODE;
++typedef enum DCIOCHIP_INVERT {
++	DCIOCHIP_POL_NON_INVERT                          = 0x0,
++	DCIOCHIP_POL_INVERT                              = 0x1,
++} DCIOCHIP_INVERT;
++typedef enum DCIOCHIP_PD_EN {
++	DCIOCHIP_PD_EN_NOTALLOW                          = 0x0,
++	DCIOCHIP_PD_EN_ALLOW                             = 0x1,
++} DCIOCHIP_PD_EN;
++typedef enum DCIOCHIP_GPIO_MASK_EN {
++	DCIOCHIP_GPIO_MASK_EN_HARDWARE                   = 0x0,
++	DCIOCHIP_GPIO_MASK_EN_SOFTWARE                   = 0x1,
++} DCIOCHIP_GPIO_MASK_EN;
++typedef enum DCIOCHIP_MASK {
++	DCIOCHIP_MASK_DISABLE                            = 0x0,
++	DCIOCHIP_MASK_ENABLE                             = 0x1,
++} DCIOCHIP_MASK;
++typedef enum DCIOCHIP_GPIO_I2C_MASK {
++	DCIOCHIP_GPIO_I2C_MASK_DISABLE                   = 0x0,
++	DCIOCHIP_GPIO_I2C_MASK_ENABLE                    = 0x1,
++} DCIOCHIP_GPIO_I2C_MASK;
++typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
++	DCIOCHIP_GPIO_I2C_DRIVE_LOW                      = 0x0,
++	DCIOCHIP_GPIO_I2C_DRIVE_HIGH                     = 0x1,
++} DCIOCHIP_GPIO_I2C_DRIVE;
++typedef enum DCIOCHIP_GPIO_I2C_EN {
++	DCIOCHIP_GPIO_I2C_DISABLE                        = 0x0,
++	DCIOCHIP_GPIO_I2C_ENABLE                         = 0x1,
++} DCIOCHIP_GPIO_I2C_EN;
++typedef enum DCIOCHIP_MASK_4BIT {
++	DCIOCHIP_MASK_4BIT_DISABLE                       = 0x0,
++	DCIOCHIP_MASK_4BIT_ENABLE                        = 0xf,
++} DCIOCHIP_MASK_4BIT;
++typedef enum DCIOCHIP_ENABLE_4BIT {
++	DCIOCHIP_4BIT_DISABLE                            = 0x0,
++	DCIOCHIP_4BIT_ENABLE                             = 0xf,
++} DCIOCHIP_ENABLE_4BIT;
++typedef enum DCIOCHIP_MASK_5BIT {
++	DCIOCHIP_MASIK_5BIT_DISABLE                      = 0x0,
++	DCIOCHIP_MASIK_5BIT_ENABLE                       = 0x1f,
++} DCIOCHIP_MASK_5BIT;
++typedef enum DCIOCHIP_ENABLE_5BIT {
++	DCIOCHIP_5BIT_DISABLE                            = 0x0,
++	DCIOCHIP_5BIT_ENABLE                             = 0x1f,
++} DCIOCHIP_ENABLE_5BIT;
++typedef enum DCIOCHIP_MASK_2BIT {
++	DCIOCHIP_MASK_2BIT_DISABLE                       = 0x0,
++	DCIOCHIP_MASK_2BIT_ENABLE                        = 0x3,
++} DCIOCHIP_MASK_2BIT;
++typedef enum DCIOCHIP_ENABLE_2BIT {
++	DCIOCHIP_2BIT_DISABLE                            = 0x0,
++	DCIOCHIP_2BIT_ENABLE                             = 0x3,
++} DCIOCHIP_ENABLE_2BIT;
++typedef enum DCIOCHIP_REF_27_SRC_SEL {
++	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER             = 0x0,
++	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER      = 0x1,
++	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS              = 0x2,
++	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS       = 0x3,
++} DCIOCHIP_REF_27_SRC_SEL;
++typedef enum DCIOCHIP_DVO_VREFPON {
++	DCIOCHIP_DVO_VREFPON_DISABLE                     = 0x0,
++	DCIOCHIP_DVO_VREFPON_ENABLE                      = 0x1,
++} DCIOCHIP_DVO_VREFPON;
++typedef enum DCIOCHIP_DVO_VREFSEL {
++	DCIOCHIP_DVO_VREFSEL_ONCHIP                      = 0x0,
++	DCIOCHIP_DVO_VREFSEL_EXTERNAL                    = 0x1,
++} DCIOCHIP_DVO_VREFSEL;
++typedef enum DCP_GRPH_ENABLE {
++	DCP_GRPH_ENABLE_FALSE                            = 0x0,
++	DCP_GRPH_ENABLE_TRUE                             = 0x1,
++} DCP_GRPH_ENABLE;
++typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
++	DCP_GRPH_KEYER_ALPHA_SEL_FALSE                   = 0x0,
++	DCP_GRPH_KEYER_ALPHA_SEL_TRUE                    = 0x1,
++} DCP_GRPH_KEYER_ALPHA_SEL;
++typedef enum DCP_GRPH_DEPTH {
++	DCP_GRPH_DEPTH_8BPP                              = 0x0,
++	DCP_GRPH_DEPTH_16BPP                             = 0x1,
++	DCP_GRPH_DEPTH_32BPP                             = 0x2,
++	DCP_GRPH_DEPTH_64BPP                             = 0x3,
++} DCP_GRPH_DEPTH;
++typedef enum DCP_GRPH_NUM_BANKS {
++	DCP_GRPH_NUM_BANKS_2BANK                         = 0x0,
++	DCP_GRPH_NUM_BANKS_4BANK                         = 0x1,
++	DCP_GRPH_NUM_BANKS_8BANK                         = 0x2,
++	DCP_GRPH_NUM_BANKS_16BANK                        = 0x3,
++} DCP_GRPH_NUM_BANKS;
++typedef enum DCP_GRPH_BANK_WIDTH {
++	DCP_GRPH_BANK_WIDTH_1                            = 0x0,
++	DCP_GRPH_BANK_WIDTH_2                            = 0x1,
++	DCP_GRPH_BANK_WIDTH_4                            = 0x2,
++	DCP_GRPH_BANK_WIDTH_8                            = 0x3,
++} DCP_GRPH_BANK_WIDTH;
++typedef enum DCP_GRPH_FORMAT {
++	DCP_GRPH_FORMAT_8BPP                             = 0x0,
++	DCP_GRPH_FORMAT_16BPP                            = 0x1,
++	DCP_GRPH_FORMAT_32BPP                            = 0x2,
++	DCP_GRPH_FORMAT_64BPP                            = 0x3,
++} DCP_GRPH_FORMAT;
++typedef enum DCP_GRPH_BANK_HEIGHT {
++	DCP_GRPH_BANK_HEIGHT_1                           = 0x0,
++	DCP_GRPH_BANK_HEIGHT_2                           = 0x1,
++	DCP_GRPH_BANK_HEIGHT_4                           = 0x2,
++	DCP_GRPH_BANK_HEIGHT_8                           = 0x3,
++} DCP_GRPH_BANK_HEIGHT;
++typedef enum DCP_GRPH_TILE_SPLIT {
++	DCP_GRPH_TILE_SPLIT_64B                          = 0x0,
++	DCP_GRPH_TILE_SPLIT_128B                         = 0x1,
++	DCP_GRPH_TILE_SPLIT_256B                         = 0x2,
++	DCP_GRPH_TILE_SPLIT_512B                         = 0x3,
++	DCP_GRPH_TILE_SPLIT_1B                           = 0x4,
++	DCP_GRPH_TILE_SPLIT_2B                           = 0x5,
++	DCP_GRPH_TILE_SPLIT_4B                           = 0x6,
++} DCP_GRPH_TILE_SPLIT;
++typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
++	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE        = 0x0,
++	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE         = 0x1,
++} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
++typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
++	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE          = 0x0,
++	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE           = 0x1,
++} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
++typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
++	DCP_GRPH_MACRO_TILE_ASPECT_1                     = 0x0,
++	DCP_GRPH_MACRO_TILE_ASPECT_2                     = 0x1,
++	DCP_GRPH_MACRO_TILE_ASPECT_4                     = 0x2,
++	DCP_GRPH_MACRO_TILE_ASPECT_8                     = 0x3,
++} DCP_GRPH_MACRO_TILE_ASPECT;
++typedef enum DCP_GRPH_ARRAY_MODE {
++	DCP_GRPH_ARRAY_MODE_0                            = 0x0,
++	DCP_GRPH_ARRAY_MODE_1                            = 0x1,
++	DCP_GRPH_ARRAY_MODE_2                            = 0x2,
++	DCP_GRPH_ARRAY_MODE_3                            = 0x3,
++	DCP_GRPH_ARRAY_MODE_4                            = 0x4,
++	DCP_GRPH_ARRAY_MODE_7                            = 0x7,
++	DCP_GRPH_ARRAY_MODE_12                           = 0xc,
++	DCP_GRPH_ARRAY_MODE_13                           = 0xd,
++} DCP_GRPH_ARRAY_MODE;
++typedef enum DCP_GRPH_MICRO_TILE_MODE {
++	DCP_GRPH_MICRO_TILE_MODE_0                       = 0x0,
++	DCP_GRPH_MICRO_TILE_MODE_1                       = 0x1,
++	DCP_GRPH_MICRO_TILE_MODE_2                       = 0x2,
++	DCP_GRPH_MICRO_TILE_MODE_3                       = 0x3,
++} DCP_GRPH_MICRO_TILE_MODE;
++typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
++	DCP_GRPH_COLOR_EXPANSION_MODE_DEXP               = 0x0,
++	DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP               = 0x1,
++} DCP_GRPH_COLOR_EXPANSION_MODE;
++typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
++	DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE               = 0x0,
++	DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE                = 0x1,
++} DCP_GRPH_LUT_10BIT_BYPASS_EN;
++typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
++	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE       = 0x0,
++	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE        = 0x1,
++} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
++typedef enum DCP_GRPH_ENDIAN_SWAP {
++	DCP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
++	DCP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
++	DCP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
++	DCP_GRPH_ENDIAN_SWAP_8IN64                       = 0x3,
++} DCP_GRPH_ENDIAN_SWAP;
++typedef enum DCP_GRPH_RED_CROSSBAR {
++	DCP_GRPH_RED_CROSSBAR_FROM_R                     = 0x0,
++	DCP_GRPH_RED_CROSSBAR_FROM_G                     = 0x1,
++	DCP_GRPH_RED_CROSSBAR_FROM_B                     = 0x2,
++	DCP_GRPH_RED_CROSSBAR_FROM_A                     = 0x3,
++} DCP_GRPH_RED_CROSSBAR;
++typedef enum DCP_GRPH_GREEN_CROSSBAR {
++	DCP_GRPH_GREEN_CROSSBAR_FROM_G                   = 0x0,
++	DCP_GRPH_GREEN_CROSSBAR_FROM_B                   = 0x1,
++	DCP_GRPH_GREEN_CROSSBAR_FROM_A                   = 0x2,
++	DCP_GRPH_GREEN_CROSSBAR_FROM_R                   = 0x3,
++} DCP_GRPH_GREEN_CROSSBAR;
++typedef enum DCP_GRPH_BLUE_CROSSBAR {
++	DCP_GRPH_BLUE_CROSSBAR_FROM_B                    = 0x0,
++	DCP_GRPH_BLUE_CROSSBAR_FROM_A                    = 0x1,
++	DCP_GRPH_BLUE_CROSSBAR_FROM_R                    = 0x2,
++	DCP_GRPH_BLUE_CROSSBAR_FROM_G                    = 0x3,
++} DCP_GRPH_BLUE_CROSSBAR;
++typedef enum DCP_GRPH_ALPHA_CROSSBAR {
++	DCP_GRPH_ALPHA_CROSSBAR_FROM_A                   = 0x0,
++	DCP_GRPH_ALPHA_CROSSBAR_FROM_R                   = 0x1,
++	DCP_GRPH_ALPHA_CROSSBAR_FROM_G                   = 0x2,
++	DCP_GRPH_ALPHA_CROSSBAR_FROM_B                   = 0x3,
++} DCP_GRPH_ALPHA_CROSSBAR;
++typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
++	DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE                = 0x0,
++	DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE                 = 0x1,
++} DCP_GRPH_PRIMARY_DFQ_ENABLE;
++typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
++	DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE              = 0x0,
++	DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE               = 0x1,
++} DCP_GRPH_SECONDARY_DFQ_ENABLE;
++typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
++	DCP_GRPH_INPUT_GAMMA_MODE_LUT                    = 0x0,
++	DCP_GRPH_INPUT_GAMMA_MODE_BYPASS                 = 0x1,
++} DCP_GRPH_INPUT_GAMMA_MODE;
++typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
++	DCP_GRPH_MODE_UPDATE_PENDING_FALSE               = 0x0,
++	DCP_GRPH_MODE_UPDATE_PENDING_TRUE                = 0x1,
++} DCP_GRPH_MODE_UPDATE_PENDING;
++typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
++	DCP_GRPH_MODE_UPDATE_TAKEN_FALSE                 = 0x0,
++	DCP_GRPH_MODE_UPDATE_TAKEN_TRUE                  = 0x1,
++} DCP_GRPH_MODE_UPDATE_TAKEN;
++typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
++	DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE            = 0x0,
++	DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE             = 0x1,
++} DCP_GRPH_SURFACE_UPDATE_PENDING;
++typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
++	DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE              = 0x0,
++	DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE               = 0x1,
++} DCP_GRPH_SURFACE_UPDATE_TAKEN;
++typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
++	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE       = 0x0,
++	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE        = 0x1,
++} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
++typedef enum DCP_GRPH_UPDATE_LOCK {
++	DCP_GRPH_UPDATE_LOCK_FALSE                       = 0x0,
++	DCP_GRPH_UPDATE_LOCK_TRUE                        = 0x1,
++} DCP_GRPH_UPDATE_LOCK;
++typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
++	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE        = 0x0,
++	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE         = 0x1,
++} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
++typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
++	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE      = 0x0,
++	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE       = 0x1,
++} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
++typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
++	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE   = 0x0,
++	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE    = 0x1,
++} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
++typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
++	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE       = 0x0,
++	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE        = 0x1,
++} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
++typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
++	DCP_GRPH_XDMA_SUPER_AA_EN_FALSE                  = 0x0,
++	DCP_GRPH_XDMA_SUPER_AA_EN_TRUE                   = 0x1,
++} DCP_GRPH_XDMA_SUPER_AA_EN;
++typedef enum DCP_GRPH_DFQ_RESET {
++	DCP_GRPH_DFQ_RESET_FALSE                         = 0x0,
++	DCP_GRPH_DFQ_RESET_TRUE                          = 0x1,
++} DCP_GRPH_DFQ_RESET;
++typedef enum DCP_GRPH_DFQ_SIZE {
++	DCP_GRPH_DFQ_SIZE_DEEP1                          = 0x0,
++	DCP_GRPH_DFQ_SIZE_DEEP2                          = 0x1,
++	DCP_GRPH_DFQ_SIZE_DEEP3                          = 0x2,
++	DCP_GRPH_DFQ_SIZE_DEEP4                          = 0x3,
++	DCP_GRPH_DFQ_SIZE_DEEP5                          = 0x4,
++	DCP_GRPH_DFQ_SIZE_DEEP6                          = 0x5,
++	DCP_GRPH_DFQ_SIZE_DEEP7                          = 0x6,
++	DCP_GRPH_DFQ_SIZE_DEEP8                          = 0x7,
++} DCP_GRPH_DFQ_SIZE;
++typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1                  = 0x0,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2                  = 0x1,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3                  = 0x2,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4                  = 0x3,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5                  = 0x4,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6                  = 0x5,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7                  = 0x6,
++	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8                  = 0x7,
++} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
++typedef enum DCP_GRPH_DFQ_RESET_ACK {
++	DCP_GRPH_DFQ_RESET_ACK_FALSE                     = 0x0,
++	DCP_GRPH_DFQ_RESET_ACK_TRUE                      = 0x1,
++} DCP_GRPH_DFQ_RESET_ACK;
++typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
++	DCP_GRPH_PFLIP_INT_CLEAR_FALSE                   = 0x0,
++	DCP_GRPH_PFLIP_INT_CLEAR_TRUE                    = 0x1,
++} DCP_GRPH_PFLIP_INT_CLEAR;
++typedef enum DCP_GRPH_PFLIP_INT_MASK {
++	DCP_GRPH_PFLIP_INT_MASK_FALSE                    = 0x0,
++	DCP_GRPH_PFLIP_INT_MASK_TRUE                     = 0x1,
++} DCP_GRPH_PFLIP_INT_MASK;
++typedef enum DCP_GRPH_PFLIP_INT_TYPE {
++	DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL             = 0x0,
++	DCP_GRPH_PFLIP_INT_TYPE_PULSE                    = 0x1,
++} DCP_GRPH_PFLIP_INT_TYPE;
++typedef enum DCP_GRPH_PRESCALE_SELECT {
++	DCP_GRPH_PRESCALE_SELECT_FIXED                   = 0x0,
++	DCP_GRPH_PRESCALE_SELECT_FLOATING                = 0x1,
++} DCP_GRPH_PRESCALE_SELECT;
++typedef enum DCP_GRPH_PRESCALE_R_SIGN {
++	DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED                = 0x0,
++	DCP_GRPH_PRESCALE_R_SIGN_SIGNED                  = 0x1,
++} DCP_GRPH_PRESCALE_R_SIGN;
++typedef enum DCP_GRPH_PRESCALE_G_SIGN {
++	DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED                = 0x0,
++	DCP_GRPH_PRESCALE_G_SIGN_SIGNED                  = 0x1,
++} DCP_GRPH_PRESCALE_G_SIGN;
++typedef enum DCP_GRPH_PRESCALE_B_SIGN {
++	DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED                = 0x0,
++	DCP_GRPH_PRESCALE_B_SIGN_SIGNED                  = 0x1,
++} DCP_GRPH_PRESCALE_B_SIGN;
++typedef enum DCP_GRPH_PRESCALE_BYPASS {
++	DCP_GRPH_PRESCALE_BYPASS_FALSE                   = 0x0,
++	DCP_GRPH_PRESCALE_BYPASS_TRUE                    = 0x1,
++} DCP_GRPH_PRESCALE_BYPASS;
++typedef enum DCP_INPUT_CSC_GRPH_MODE {
++	DCP_INPUT_CSC_GRPH_MODE_BYPASS                   = 0x0,
++	DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF           = 0x1,
++	DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF              = 0x2,
++	DCP_INPUT_CSC_GRPH_MODE_RESERVED                 = 0x3,
++} DCP_INPUT_CSC_GRPH_MODE;
++typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
++	DCP_OUTPUT_CSC_GRPH_MODE_BYPASS                  = 0x0,
++	DCP_OUTPUT_CSC_GRPH_MODE_RGB                     = 0x1,
++	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601                = 0x2,
++	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709                = 0x3,
++	DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF         = 0x4,
++	DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF             = 0x5,
++	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0               = 0x6,
++	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1               = 0x7,
++} DCP_OUTPUT_CSC_GRPH_MODE;
++typedef enum DCP_DENORM_MODE {
++	DCP_DENORM_MODE_UNITY                            = 0x0,
++	DCP_DENORM_MODE_6BIT                             = 0x1,
++	DCP_DENORM_MODE_8BIT                             = 0x2,
++	DCP_DENORM_MODE_10BIT                            = 0x3,
++	DCP_DENORM_MODE_11BIT                            = 0x4,
++	DCP_DENORM_MODE_12BIT                            = 0x5,
++	DCP_DENORM_MODE_RESERVED0                        = 0x6,
++	DCP_DENORM_MODE_RESERVED1                        = 0x7,
++} DCP_DENORM_MODE;
++typedef enum DCP_DENORM_14BIT_OUT {
++	DCP_DENORM_14BIT_OUT_FALSE                       = 0x0,
++	DCP_DENORM_14BIT_OUT_TRUE                        = 0x1,
++} DCP_DENORM_14BIT_OUT;
++typedef enum DCP_OUT_ROUND_TRUNC_MODE {
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12             = 0x0,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11             = 0x1,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10             = 0x2,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9              = 0x3,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8              = 0x4,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED       = 0x5,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14             = 0x6,
++	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13             = 0x7,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_12                = 0x8,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_11                = 0x9,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_10                = 0xa,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_9                 = 0xb,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_8                 = 0xc,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED          = 0xd,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_14                = 0xe,
++	DCP_OUT_ROUND_TRUNC_MODE_ROUND_13                = 0xf,
++} DCP_OUT_ROUND_TRUNC_MODE;
++typedef enum DCP_KEY_MODE {
++	DCP_KEY_MODE_ALPHA0                              = 0x0,
++	DCP_KEY_MODE_ALPHA1                              = 0x1,
++	DCP_KEY_MODE_IN_RANGE_ALPHA1                     = 0x2,
++	DCP_KEY_MODE_IN_RANGE_ALPHA0                     = 0x3,
++} DCP_KEY_MODE;
++typedef enum DCP_GRPH_DEGAMMA_MODE {
++	DCP_GRPH_DEGAMMA_MODE_BYPASS                     = 0x0,
++	DCP_GRPH_DEGAMMA_MODE_ROMA                       = 0x1,
++	DCP_GRPH_DEGAMMA_MODE_ROMB                       = 0x2,
++	DCP_GRPH_DEGAMMA_MODE_RESERVED                   = 0x3,
++} DCP_GRPH_DEGAMMA_MODE;
++typedef enum DCP_CURSOR2_DEGAMMA_MODE {
++	DCP_CURSOR2_DEGAMMA_MODE_BYPASS                  = 0x0,
++	DCP_CURSOR2_DEGAMMA_MODE_ROMA                    = 0x1,
++	DCP_CURSOR2_DEGAMMA_MODE_ROMB                    = 0x2,
++	DCP_CURSOR2_DEGAMMA_MODE_RESERVED                = 0x3,
++} DCP_CURSOR2_DEGAMMA_MODE;
++typedef enum DCP_CURSOR_DEGAMMA_MODE {
++	DCP_CURSOR_DEGAMMA_MODE_BYPASS                   = 0x0,
++	DCP_CURSOR_DEGAMMA_MODE_ROMA                     = 0x1,
++	DCP_CURSOR_DEGAMMA_MODE_ROMB                     = 0x2,
++	DCP_CURSOR_DEGAMMA_MODE_RESERVED                 = 0x3,
++} DCP_CURSOR_DEGAMMA_MODE;
++typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
++	DCP_GRPH_GAMUT_REMAP_MODE_BYPASS                 = 0x0,
++	DCP_GRPH_GAMUT_REMAP_MODE_ROMA                   = 0x1,
++	DCP_GRPH_GAMUT_REMAP_MODE_ROMB                   = 0x2,
++	DCP_GRPH_GAMUT_REMAP_MODE_RESERVED               = 0x3,
++} DCP_GRPH_GAMUT_REMAP_MODE;
++typedef enum DCP_SPATIAL_DITHER_EN {
++	DCP_SPATIAL_DITHER_EN_FALSE                      = 0x0,
++	DCP_SPATIAL_DITHER_EN_TRUE                       = 0x1,
++} DCP_SPATIAL_DITHER_EN;
++typedef enum DCP_SPATIAL_DITHER_MODE {
++	DCP_SPATIAL_DITHER_MODE_BYPASS                   = 0x0,
++	DCP_SPATIAL_DITHER_MODE_ROMA                     = 0x1,
++	DCP_SPATIAL_DITHER_MODE_ROMB                     = 0x2,
++	DCP_SPATIAL_DITHER_MODE_RESERVED                 = 0x3,
++} DCP_SPATIAL_DITHER_MODE;
++typedef enum DCP_SPATIAL_DITHER_DEPTH {
++	DCP_SPATIAL_DITHER_DEPTH_30BPP                   = 0x0,
++	DCP_SPATIAL_DITHER_DEPTH_24BPP                   = 0x1,
++	DCP_SPATIAL_DITHER_DEPTH_36BPP                   = 0x2,
++	DCP_SPATIAL_DITHER_DEPTH_UNDEFINED               = 0x3,
++} DCP_SPATIAL_DITHER_DEPTH;
++typedef enum DCP_FRAME_RANDOM_ENABLE {
++	DCP_FRAME_RANDOM_ENABLE_FALSE                    = 0x0,
++	DCP_FRAME_RANDOM_ENABLE_TRUE                     = 0x1,
++} DCP_FRAME_RANDOM_ENABLE;
++typedef enum DCP_RGB_RANDOM_ENABLE {
++	DCP_RGB_RANDOM_ENABLE_FALSE                      = 0x0,
++	DCP_RGB_RANDOM_ENABLE_TRUE                       = 0x1,
++} DCP_RGB_RANDOM_ENABLE;
++typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
++	DCP_HIGHPASS_RANDOM_ENABLE_FALSE                 = 0x0,
++	DCP_HIGHPASS_RANDOM_ENABLE_TRUE                  = 0x1,
++} DCP_HIGHPASS_RANDOM_ENABLE;
++typedef enum DCP_CURSOR_EN {
++	DCP_CURSOR_EN_FALSE                              = 0x0,
++	DCP_CURSOR_EN_TRUE                               = 0x1,
++} DCP_CURSOR_EN;
++typedef enum DCP_CUR_INV_TRANS_CLAMP {
++	DCP_CUR_INV_TRANS_CLAMP_FALSE                    = 0x0,
++	DCP_CUR_INV_TRANS_CLAMP_TRUE                     = 0x1,
++} DCP_CUR_INV_TRANS_CLAMP;
++typedef enum DCP_CURSOR_MODE {
++	DCP_CURSOR_MODE_MONO_2BPP                        = 0x0,
++	DCP_CURSOR_MODE_24BPP_1BIT                       = 0x1,
++	DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI              = 0x2,
++	DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI            = 0x3,
++} DCP_CURSOR_MODE;
++typedef enum DCP_CURSOR_2X_MAGNIFY {
++	DCP_CURSOR_2X_MAGNIFY_FALSE                      = 0x0,
++	DCP_CURSOR_2X_MAGNIFY_TRUE                       = 0x1,
++} DCP_CURSOR_2X_MAGNIFY;
++typedef enum DCP_CURSOR_FORCE_MC_ON {
++	DCP_CURSOR_FORCE_MC_ON_FALSE                     = 0x0,
++	DCP_CURSOR_FORCE_MC_ON_TRUE                      = 0x1,
++} DCP_CURSOR_FORCE_MC_ON;
++typedef enum DCP_CURSOR_URGENT_CONTROL {
++	DCP_CURSOR_URGENT_CONTROL_MODE_0                 = 0x0,
++	DCP_CURSOR_URGENT_CONTROL_MODE_1                 = 0x1,
++	DCP_CURSOR_URGENT_CONTROL_MODE_2                 = 0x2,
++	DCP_CURSOR_URGENT_CONTROL_MODE_3                 = 0x3,
++	DCP_CURSOR_URGENT_CONTROL_MODE_4                 = 0x4,
++} DCP_CURSOR_URGENT_CONTROL;
++typedef enum DCP_CURSOR_UPDATE_PENDING {
++	DCP_CURSOR_UPDATE_PENDING_FALSE                  = 0x0,
++	DCP_CURSOR_UPDATE_PENDING_TRUE                   = 0x1,
++} DCP_CURSOR_UPDATE_PENDING;
++typedef enum DCP_CURSOR_UPDATE_TAKEN {
++	DCP_CURSOR_UPDATE_TAKEN_FALSE                    = 0x0,
++	DCP_CURSOR_UPDATE_TAKEN_TRUE                     = 0x1,
++} DCP_CURSOR_UPDATE_TAKEN;
++typedef enum DCP_CURSOR_UPDATE_LOCK {
++	DCP_CURSOR_UPDATE_LOCK_FALSE                     = 0x0,
++	DCP_CURSOR_UPDATE_LOCK_TRUE                      = 0x1,
++} DCP_CURSOR_UPDATE_LOCK;
++typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
++	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE         = 0x0,
++	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE          = 0x1,
++} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
++typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
++	DCP_CURSOR_UPDATE_STEREO_MODE_BOTH               = 0x0,
++	DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY     = 0x1,
++	DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED          = 0x2,
++	DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY       = 0x3,
++} DCP_CURSOR_UPDATE_STEREO_MODE;
++typedef enum DCP_CURSOR2_EN {
++	DCP_CURSOR2_EN_FALSE                             = 0x0,
++	DCP_CURSOR2_EN_TRUE                              = 0x1,
++} DCP_CURSOR2_EN;
++typedef enum DCP_CUR2_INV_TRANS_CLAMP {
++	DCP_CUR2_INV_TRANS_CLAMP_FALSE                   = 0x0,
++	DCP_CUR2_INV_TRANS_CLAMP_TRUE                    = 0x1,
++} DCP_CUR2_INV_TRANS_CLAMP;
++typedef enum DCP_CURSOR2_MODE {
++	DCP_CURSOR2_MODE_MONO_2BPP                       = 0x0,
++	DCP_CURSOR2_MODE_24BPP_1BIT                      = 0x1,
++	DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI             = 0x2,
++	DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI           = 0x3,
++} DCP_CURSOR2_MODE;
++typedef enum DCP_CURSOR2_2X_MAGNIFY {
++	DCP_CURSOR2_2X_MAGNIFY_FALSE                     = 0x0,
++	DCP_CURSOR2_2X_MAGNIFY_TRUE                      = 0x1,
++} DCP_CURSOR2_2X_MAGNIFY;
++typedef enum DCP_CURSOR2_FORCE_MC_ON {
++	DCP_CURSOR2_FORCE_MC_ON_FALSE                    = 0x0,
++	DCP_CURSOR2_FORCE_MC_ON_TRUE                     = 0x1,
++} DCP_CURSOR2_FORCE_MC_ON;
++typedef enum DCP_CURSOR2_URGENT_CONTROL {
++	DCP_CURSOR2_URGENT_CONTROL_MODE_0                = 0x0,
++	DCP_CURSOR2_URGENT_CONTROL_MODE_1                = 0x1,
++	DCP_CURSOR2_URGENT_CONTROL_MODE_2                = 0x2,
++	DCP_CURSOR2_URGENT_CONTROL_MODE_3                = 0x3,
++	DCP_CURSOR2_URGENT_CONTROL_MODE_4                = 0x4,
++} DCP_CURSOR2_URGENT_CONTROL;
++typedef enum DCP_CURSOR2_UPDATE_PENDING {
++	DCP_CURSOR2_UPDATE_PENDING_FALSE                 = 0x0,
++	DCP_CURSOR2_UPDATE_PENDING_TRUE                  = 0x1,
++} DCP_CURSOR2_UPDATE_PENDING;
++typedef enum DCP_CURSOR2_UPDATE_TAKEN {
++	DCP_CURSOR2_UPDATE_TAKEN_FALSE                   = 0x0,
++	DCP_CURSOR2_UPDATE_TAKEN_TRUE                    = 0x1,
++} DCP_CURSOR2_UPDATE_TAKEN;
++typedef enum DCP_CURSOR2_UPDATE_LOCK {
++	DCP_CURSOR2_UPDATE_LOCK_FALSE                    = 0x0,
++	DCP_CURSOR2_UPDATE_LOCK_TRUE                     = 0x1,
++} DCP_CURSOR2_UPDATE_LOCK;
++typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
++	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE        = 0x0,
++	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE         = 0x1,
++} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
++typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
++	DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH              = 0x0,
++	DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY    = 0x1,
++	DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED         = 0x2,
++	DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY      = 0x3,
++} DCP_CURSOR2_UPDATE_STEREO_MODE;
++typedef enum DCP_CUR_REQUEST_FILTER_DIS {
++	DCP_CUR_REQUEST_FILTER_DIS_FALSE                 = 0x0,
++	DCP_CUR_REQUEST_FILTER_DIS_TRUE                  = 0x1,
++} DCP_CUR_REQUEST_FILTER_DIS;
++typedef enum DCP_CURSOR_STEREO_EN {
++	DCP_CURSOR_STEREO_EN_FALSE                       = 0x0,
++	DCP_CURSOR_STEREO_EN_TRUE                        = 0x1,
++} DCP_CURSOR_STEREO_EN;
++typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
++	DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION          = 0x0,
++	DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION          = 0x1,
++} DCP_CURSOR_STEREO_OFFSET_YNX;
++typedef enum DCP_CURSOR2_STEREO_EN {
++	DCP_CURSOR2_STEREO_EN_FALSE                      = 0x0,
++	DCP_CURSOR2_STEREO_EN_TRUE                       = 0x1,
++} DCP_CURSOR2_STEREO_EN;
++typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
++	DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION         = 0x0,
++	DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION         = 0x1,
++} DCP_CURSOR2_STEREO_OFFSET_YNX;
++typedef enum DCP_DC_LUT_RW_MODE {
++	DCP_DC_LUT_RW_MODE_256_ENTRY                     = 0x0,
++	DCP_DC_LUT_RW_MODE_PWL                           = 0x1,
++} DCP_DC_LUT_RW_MODE;
++typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
++	DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE               = 0x0,
++	DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE                = 0x1,
++} DCP_DC_LUT_VGA_ACCESS_ENABLE;
++typedef enum DCP_DC_LUT_AUTOFILL {
++	DCP_DC_LUT_AUTOFILL_FALSE                        = 0x0,
++	DCP_DC_LUT_AUTOFILL_TRUE                         = 0x1,
++} DCP_DC_LUT_AUTOFILL;
++typedef enum DCP_DC_LUT_AUTOFILL_DONE {
++	DCP_DC_LUT_AUTOFILL_DONE_FALSE                   = 0x0,
++	DCP_DC_LUT_AUTOFILL_DONE_TRUE                    = 0x1,
++} DCP_DC_LUT_AUTOFILL_DONE;
++typedef enum DCP_DC_LUT_INC_B {
++	DCP_DC_LUT_INC_B_NA                              = 0x0,
++	DCP_DC_LUT_INC_B_2                               = 0x1,
++	DCP_DC_LUT_INC_B_4                               = 0x2,
++	DCP_DC_LUT_INC_B_8                               = 0x3,
++	DCP_DC_LUT_INC_B_16                              = 0x4,
++	DCP_DC_LUT_INC_B_32                              = 0x5,
++	DCP_DC_LUT_INC_B_64                              = 0x6,
++	DCP_DC_LUT_INC_B_128                             = 0x7,
++	DCP_DC_LUT_INC_B_256                             = 0x8,
++	DCP_DC_LUT_INC_B_512                             = 0x9,
++} DCP_DC_LUT_INC_B;
++typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
++	DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE                = 0x0,
++	DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE                 = 0x1,
++} DCP_DC_LUT_DATA_B_SIGNED_EN;
++typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
++	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE           = 0x0,
++	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE            = 0x1,
++} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
++typedef enum DCP_DC_LUT_DATA_B_FORMAT {
++	DCP_DC_LUT_DATA_B_FORMAT_U0P10                   = 0x0,
++	DCP_DC_LUT_DATA_B_FORMAT_S1P10                   = 0x1,
++	DCP_DC_LUT_DATA_B_FORMAT_U1P11                   = 0x2,
++	DCP_DC_LUT_DATA_B_FORMAT_U0P12                   = 0x3,
++} DCP_DC_LUT_DATA_B_FORMAT;
++typedef enum DCP_DC_LUT_INC_G {
++	DCP_DC_LUT_INC_G_NA                              = 0x0,
++	DCP_DC_LUT_INC_G_2                               = 0x1,
++	DCP_DC_LUT_INC_G_4                               = 0x2,
++	DCP_DC_LUT_INC_G_8                               = 0x3,
++	DCP_DC_LUT_INC_G_16                              = 0x4,
++	DCP_DC_LUT_INC_G_32                              = 0x5,
++	DCP_DC_LUT_INC_G_64                              = 0x6,
++	DCP_DC_LUT_INC_G_128                             = 0x7,
++	DCP_DC_LUT_INC_G_256                             = 0x8,
++	DCP_DC_LUT_INC_G_512                             = 0x9,
++} DCP_DC_LUT_INC_G;
++typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
++	DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE                = 0x0,
++	DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE                 = 0x1,
++} DCP_DC_LUT_DATA_G_SIGNED_EN;
++typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
++	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE           = 0x0,
++	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE            = 0x1,
++} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
++typedef enum DCP_DC_LUT_DATA_G_FORMAT {
++	DCP_DC_LUT_DATA_G_FORMAT_U0P10                   = 0x0,
++	DCP_DC_LUT_DATA_G_FORMAT_S1P10                   = 0x1,
++	DCP_DC_LUT_DATA_G_FORMAT_U1P11                   = 0x2,
++	DCP_DC_LUT_DATA_G_FORMAT_U0P12                   = 0x3,
++} DCP_DC_LUT_DATA_G_FORMAT;
++typedef enum DCP_DC_LUT_INC_R {
++	DCP_DC_LUT_INC_R_NA                              = 0x0,
++	DCP_DC_LUT_INC_R_2                               = 0x1,
++	DCP_DC_LUT_INC_R_4                               = 0x2,
++	DCP_DC_LUT_INC_R_8                               = 0x3,
++	DCP_DC_LUT_INC_R_16                              = 0x4,
++	DCP_DC_LUT_INC_R_32                              = 0x5,
++	DCP_DC_LUT_INC_R_64                              = 0x6,
++	DCP_DC_LUT_INC_R_128                             = 0x7,
++	DCP_DC_LUT_INC_R_256                             = 0x8,
++	DCP_DC_LUT_INC_R_512                             = 0x9,
++} DCP_DC_LUT_INC_R;
++typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
++	DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE                = 0x0,
++	DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE                 = 0x1,
++} DCP_DC_LUT_DATA_R_SIGNED_EN;
++typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
++	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE           = 0x0,
++	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE            = 0x1,
++} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
++typedef enum DCP_DC_LUT_DATA_R_FORMAT {
++	DCP_DC_LUT_DATA_R_FORMAT_U0P10                   = 0x0,
++	DCP_DC_LUT_DATA_R_FORMAT_S1P10                   = 0x1,
++	DCP_DC_LUT_DATA_R_FORMAT_U1P11                   = 0x2,
++	DCP_DC_LUT_DATA_R_FORMAT_U0P12                   = 0x3,
++} DCP_DC_LUT_DATA_R_FORMAT;
++typedef enum DCP_CRC_ENABLE {
++	DCP_CRC_ENABLE_FALSE                             = 0x0,
++	DCP_CRC_ENABLE_TRUE                              = 0x1,
++} DCP_CRC_ENABLE;
++typedef enum DCP_CRC_SOURCE_SEL {
++	DCP_CRC_SOURCE_SEL_OUTPUT_PIX                    = 0x0,
++	DCP_CRC_SOURCE_SEL_INPUT_L32                     = 0x1,
++	DCP_CRC_SOURCE_SEL_INPUT_H32                     = 0x2,
++	DCP_CRC_SOURCE_SEL_OUTPUT_CNTL                   = 0x4,
++} DCP_CRC_SOURCE_SEL;
++typedef enum DCP_CRC_LINE_SEL {
++	DCP_CRC_LINE_SEL_RESERVED                        = 0x0,
++	DCP_CRC_LINE_SEL_EVEN                            = 0x1,
++	DCP_CRC_LINE_SEL_ODD                             = 0x2,
++	DCP_CRC_LINE_SEL_BOTH                            = 0x3,
++} DCP_CRC_LINE_SEL;
++typedef enum DCP_GRPH_FLIP_RATE {
++	DCP_GRPH_FLIP_RATE_1FRAME                        = 0x0,
++	DCP_GRPH_FLIP_RATE_2FRAME                        = 0x1,
++	DCP_GRPH_FLIP_RATE_3FRAME                        = 0x2,
++	DCP_GRPH_FLIP_RATE_4FRAME                        = 0x3,
++	DCP_GRPH_FLIP_RATE_5FRAME                        = 0x4,
++	DCP_GRPH_FLIP_RATE_6FRAME                        = 0x5,
++	DCP_GRPH_FLIP_RATE_7FRAME                        = 0x6,
++	DCP_GRPH_FLIP_RATE_8FRAME                        = 0x7,
++} DCP_GRPH_FLIP_RATE;
++typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
++	DCP_GRPH_FLIP_RATE_ENABLE_FALSE                  = 0x0,
++	DCP_GRPH_FLIP_RATE_ENABLE_TRUE                   = 0x1,
++} DCP_GRPH_FLIP_RATE_ENABLE;
++typedef enum DCP_GSL0_EN {
++	DCP_GSL0_EN_FALSE                                = 0x0,
++	DCP_GSL0_EN_TRUE                                 = 0x1,
++} DCP_GSL0_EN;
++typedef enum DCP_GSL1_EN {
++	DCP_GSL1_EN_FALSE                                = 0x0,
++	DCP_GSL1_EN_TRUE                                 = 0x1,
++} DCP_GSL1_EN;
++typedef enum DCP_GSL2_EN {
++	DCP_GSL2_EN_FALSE                                = 0x0,
++	DCP_GSL2_EN_TRUE                                 = 0x1,
++} DCP_GSL2_EN;
++typedef enum DCP_GSL_MASTER_EN {
++	DCP_GSL_MASTER_EN_FALSE                          = 0x0,
++	DCP_GSL_MASTER_EN_TRUE                           = 0x1,
++} DCP_GSL_MASTER_EN;
++typedef enum DCP_GSL_XDMA_GROUP {
++	DCP_GSL_XDMA_GROUP_VSYNC                         = 0x0,
++	DCP_GSL_XDMA_GROUP_HSYNC0                        = 0x1,
++	DCP_GSL_XDMA_GROUP_HSYNC1                        = 0x2,
++	DCP_GSL_XDMA_GROUP_HSYNC2                        = 0x3,
++} DCP_GSL_XDMA_GROUP;
++typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
++	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE            = 0x0,
++	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE             = 0x1,
++} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
++typedef enum DCP_GSL_SYNC_SOURCE {
++	DCP_GSL_SYNC_SOURCE_FLIP                         = 0x0,
++	DCP_GSL_SYNC_SOURCE_PHASE0                       = 0x1,
++	DCP_GSL_SYNC_SOURCE_RESET                        = 0x2,
++	DCP_GSL_SYNC_SOURCE_PHASE1                       = 0x3,
++} DCP_GSL_SYNC_SOURCE;
++typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
++	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE       = 0x0,
++	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE        = 0x1,
++} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
++typedef enum DCP_TEST_DEBUG_WRITE_EN {
++	DCP_TEST_DEBUG_WRITE_EN_FALSE                    = 0x0,
++	DCP_TEST_DEBUG_WRITE_EN_TRUE                     = 0x1,
++} DCP_TEST_DEBUG_WRITE_EN;
++typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
++	DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE                = 0x0,
++	DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE                 = 0x1,
++} DCP_GRPH_STEREOSYNC_FLIP_EN;
++typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
++	DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP               = 0x0,
++	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0             = 0x1,
++	DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET              = 0x2,
++	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1             = 0x3,
++} DCP_GRPH_STEREOSYNC_FLIP_MODE;
++typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
++	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE         = 0x0,
++	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE          = 0x1,
++} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
++typedef enum DCP_GRPH_ROTATION_ANGLE {
++	DCP_GRPH_ROTATION_ANGLE_0                        = 0x0,
++	DCP_GRPH_ROTATION_ANGLE_90                       = 0x1,
++	DCP_GRPH_ROTATION_ANGLE_180                      = 0x2,
++	DCP_GRPH_ROTATION_ANGLE_270                      = 0x3,
++} DCP_GRPH_ROTATION_ANGLE;
++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE       = 0x0,
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE        = 0x1,
++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x0,
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
++typedef enum DCP_GRPH_REGAMMA_MODE {
++	DCP_GRPH_REGAMMA_MODE_BYPASS                     = 0x0,
++	DCP_GRPH_REGAMMA_MODE_SRGB                       = 0x1,
++	DCP_GRPH_REGAMMA_MODE_XVYCC                      = 0x2,
++	DCP_GRPH_REGAMMA_MODE_PROGA                      = 0x3,
++	DCP_GRPH_REGAMMA_MODE_PROGB                      = 0x4,
++} DCP_GRPH_REGAMMA_MODE;
++typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
++	DCP_ALPHA_ROUND_TRUNC_MODE_ROUND                 = 0x0,
++	DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC                 = 0x1,
++} DCP_ALPHA_ROUND_TRUNC_MODE;
++typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
++	DCP_CURSOR_ALPHA_BLND_ENA_FALSE                  = 0x0,
++	DCP_CURSOR_ALPHA_BLND_ENA_TRUE                   = 0x1,
++} DCP_CURSOR_ALPHA_BLND_ENA;
++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE   = 0x0,
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE    = 0x1,
++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE    = 0x0,
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE     = 0x1,
++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE     = 0x0,
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE      = 0x1,
++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE      = 0x0,
++	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE       = 0x1,
++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
++typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
++	DCP_GRPH_SURFACE_COUNTER_EN_DISABLE              = 0x0,
++	DCP_GRPH_SURFACE_COUNTER_EN_ENABLE               = 0x1,
++} DCP_GRPH_SURFACE_COUNTER_EN;
++typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0          = 0x0,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1          = 0x1,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2          = 0x2,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3          = 0x3,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4          = 0x4,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5          = 0x5,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6          = 0x6,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7          = 0x7,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8          = 0x8,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9          = 0x9,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10         = 0xa,
++	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11         = 0xb,
++} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
++typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
++	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO     = 0x0,
++	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES    = 0x1,
++} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
++typedef enum HDMI_KEEPOUT_MODE {
++	HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC                = 0x0,
++	HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC              = 0x1,
++} HDMI_KEEPOUT_MODE;
++typedef enum HDMI_CLOCK_CHANNEL_RATE {
++	HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE       = 0x0,
++	HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE     = 0x1,
++} HDMI_CLOCK_CHANNEL_RATE;
++typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
++	HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE             = 0x0,
++	HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE            = 0x1,
++} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
++typedef enum HDMI_PACKET_GEN_VERSION {
++	HDMI_PACKET_GEN_VERSION_OLD                      = 0x0,
++	HDMI_PACKET_GEN_VERSION_NEW                      = 0x1,
++} HDMI_PACKET_GEN_VERSION;
++typedef enum HDMI_ERROR_ACK {
++	HDMI_ERROR_ACK_INT                               = 0x0,
++	HDMI_ERROR_NOT_ACK                               = 0x1,
++} HDMI_ERROR_ACK;
++typedef enum HDMI_ERROR_MASK {
++	HDMI_ERROR_MASK_INT                              = 0x0,
++	HDMI_ERROR_NOT_MASK                              = 0x1,
++} HDMI_ERROR_MASK;
++typedef enum HDMI_DEEP_COLOR_DEPTH {
++	HDMI_DEEP_COLOR_DEPTH_24BPP                      = 0x0,
++	HDMI_DEEP_COLOR_DEPTH_30BPP                      = 0x1,
++	HDMI_DEEP_COLOR_DEPTH_36BPP                      = 0x2,
++	HDMI_DEEP_COLOR_DEPTH_RESERVED                   = 0x3,
++} HDMI_DEEP_COLOR_DEPTH;
++typedef enum HDMI_AUDIO_DELAY_EN {
++	HDMI_AUDIO_DELAY_DISABLE                         = 0x0,
++	HDMI_AUDIO_DELAY_58CLK                           = 0x1,
++	HDMI_AUDIO_DELAY_56CLK                           = 0x2,
++	HDMI_AUDIO_DELAY_RESERVED                        = 0x3,
++} HDMI_AUDIO_DELAY_EN;
++typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
++	HDMI_NOT_SEND_MAX_AUDIO_PACKETS                  = 0x0,
++	HDMI_SEND_MAX_AUDIO_PACKETS                      = 0x1,
++} HDMI_AUDIO_SEND_MAX_PACKETS;
++typedef enum HDMI_ACR_SEND {
++	HDMI_ACR_NOT_SEND                                = 0x0,
++	HDMI_ACR_PKT_SEND                                = 0x1,
++} HDMI_ACR_SEND;
++typedef enum HDMI_ACR_CONT {
++	HDMI_ACR_CONT_DISABLE                            = 0x0,
++	HDMI_ACR_CONT_ENABLE                             = 0x1,
++} HDMI_ACR_CONT;
++typedef enum HDMI_ACR_SELECT {
++	HDMI_ACR_SELECT_HW                               = 0x0,
++	HDMI_ACR_SELECT_32K                              = 0x1,
++	HDMI_ACR_SELECT_44K                              = 0x2,
++	HDMI_ACR_SELECT_48K                              = 0x3,
++} HDMI_ACR_SELECT;
++typedef enum HDMI_ACR_SOURCE {
++	HDMI_ACR_SOURCE_HW                               = 0x0,
++	HDMI_ACR_SOURCE_SW                               = 0x1,
++} HDMI_ACR_SOURCE;
++typedef enum HDMI_ACR_N_MULTIPLE {
++	HDMI_ACR_0_MULTIPLE_RESERVED                     = 0x0,
++	HDMI_ACR_1_MULTIPLE                              = 0x1,
++	HDMI_ACR_2_MULTIPLE                              = 0x2,
++	HDMI_ACR_3_MULTIPLE_RESERVED                     = 0x3,
++	HDMI_ACR_4_MULTIPLE                              = 0x4,
++	HDMI_ACR_5_MULTIPLE_RESERVED                     = 0x5,
++	HDMI_ACR_6_MULTIPLE_RESERVED                     = 0x6,
++	HDMI_ACR_7_MULTIPLE_RESERVED                     = 0x7,
++} HDMI_ACR_N_MULTIPLE;
++typedef enum HDMI_ACR_AUDIO_PRIORITY {
++	HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE     = 0x0,
++	HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT     = 0x1,
++} HDMI_ACR_AUDIO_PRIORITY;
++typedef enum HDMI_NULL_SEND {
++	HDMI_NULL_NOT_SEND                               = 0x0,
++	HDMI_NULL_PKT_SEND                               = 0x1,
++} HDMI_NULL_SEND;
++typedef enum HDMI_GC_SEND {
++	HDMI_GC_NOT_SEND                                 = 0x0,
++	HDMI_GC_PKT_SEND                                 = 0x1,
++} HDMI_GC_SEND;
++typedef enum HDMI_GC_CONT {
++	HDMI_GC_CONT_DISABLE                             = 0x0,
++	HDMI_GC_CONT_ENABLE                              = 0x1,
++} HDMI_GC_CONT;
++typedef enum HDMI_ISRC_SEND {
++	HDMI_ISRC_NOT_SEND                               = 0x0,
++	HDMI_ISRC_PKT_SEND                               = 0x1,
++} HDMI_ISRC_SEND;
++typedef enum HDMI_ISRC_CONT {
++	HDMI_ISRC_CONT_DISABLE                           = 0x0,
++	HDMI_ISRC_CONT_ENABLE                            = 0x1,
++} HDMI_ISRC_CONT;
++typedef enum HDMI_AVI_INFO_SEND {
++	HDMI_AVI_INFO_NOT_SEND                           = 0x0,
++	HDMI_AVI_INFO_PKT_SEND                           = 0x1,
++} HDMI_AVI_INFO_SEND;
++typedef enum HDMI_AVI_INFO_CONT {
++	HDMI_AVI_INFO_CONT_DISABLE                       = 0x0,
++	HDMI_AVI_INFO_CONT_ENABLE                        = 0x1,
++} HDMI_AVI_INFO_CONT;
++typedef enum HDMI_AUDIO_INFO_SEND {
++	HDMI_AUDIO_INFO_NOT_SEND                         = 0x0,
++	HDMI_AUDIO_INFO_PKT_SEND                         = 0x1,
++} HDMI_AUDIO_INFO_SEND;
++typedef enum HDMI_AUDIO_INFO_CONT {
++	HDMI_AUDIO_INFO_CONT_DISABLE                     = 0x0,
++	HDMI_AUDIO_INFO_CONT_ENABLE                      = 0x1,
++} HDMI_AUDIO_INFO_CONT;
++typedef enum HDMI_MPEG_INFO_SEND {
++	HDMI_MPEG_INFO_NOT_SEND                          = 0x0,
++	HDMI_MPEG_INFO_PKT_SEND                          = 0x1,
++} HDMI_MPEG_INFO_SEND;
++typedef enum HDMI_MPEG_INFO_CONT {
++	HDMI_MPEG_INFO_CONT_DISABLE                      = 0x0,
++	HDMI_MPEG_INFO_CONT_ENABLE                       = 0x1,
++} HDMI_MPEG_INFO_CONT;
++typedef enum HDMI_GENERIC0_SEND {
++	HDMI_GENERIC0_NOT_SEND                           = 0x0,
++	HDMI_GENERIC0_PKT_SEND                           = 0x1,
++} HDMI_GENERIC0_SEND;
++typedef enum HDMI_GENERIC0_CONT {
++	HDMI_GENERIC0_CONT_DISABLE                       = 0x0,
++	HDMI_GENERIC0_CONT_ENABLE                        = 0x1,
++} HDMI_GENERIC0_CONT;
++typedef enum HDMI_GENERIC1_SEND {
++	HDMI_GENERIC1_NOT_SEND                           = 0x0,
++	HDMI_GENERIC1_PKT_SEND                           = 0x1,
++} HDMI_GENERIC1_SEND;
++typedef enum HDMI_GENERIC1_CONT {
++	HDMI_GENERIC1_CONT_DISABLE                       = 0x0,
++	HDMI_GENERIC1_CONT_ENABLE                        = 0x1,
++} HDMI_GENERIC1_CONT;
++typedef enum HDMI_GC_AVMUTE_CONT {
++	HDMI_GC_AVMUTE_CONT_DISABLE                      = 0x0,
++	HDMI_GC_AVMUTE_CONT_ENABLE                       = 0x1,
++} HDMI_GC_AVMUTE_CONT;
++typedef enum HDMI_PACKING_PHASE_OVERRIDE {
++	HDMI_PACKING_PHASE_SET_BY_HW                     = 0x0,
++	HDMI_PACKING_PHASE_SET_BY_SW                     = 0x1,
++} HDMI_PACKING_PHASE_OVERRIDE;
++typedef enum HDMI_GENERIC2_SEND {
++	HDMI_GENERIC2_NOT_SEND                           = 0x0,
++	HDMI_GENERIC2_PKT_SEND                           = 0x1,
++} HDMI_GENERIC2_SEND;
++typedef enum HDMI_GENERIC2_CONT {
++	HDMI_GENERIC2_CONT_DISABLE                       = 0x0,
++	HDMI_GENERIC2_CONT_ENABLE                        = 0x1,
++} HDMI_GENERIC2_CONT;
++typedef enum HDMI_GENERIC3_SEND {
++	HDMI_GENERIC3_NOT_SEND                           = 0x0,
++	HDMI_GENERIC3_PKT_SEND                           = 0x1,
++} HDMI_GENERIC3_SEND;
++typedef enum HDMI_GENERIC3_CONT {
++	HDMI_GENERIC3_CONT_DISABLE                       = 0x0,
++	HDMI_GENERIC3_CONT_ENABLE                        = 0x1,
++} HDMI_GENERIC3_CONT;
++typedef enum TMDS_PIXEL_ENCODING {
++	TMDS_PIXEL_ENCODING_444                          = 0x0,
++	TMDS_PIXEL_ENCODING_422                          = 0x1,
++} TMDS_PIXEL_ENCODING;
++typedef enum TMDS_COLOR_FORMAT {
++	TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
++	TMDS_COLOR_FORMAT_TWIN30BPP_LSB                  = 0x1,
++	TMDS_COLOR_FORMAT_DUAL30BPP                      = 0x2,
++	TMDS_COLOR_FORMAT_RESERVED                       = 0x3,
++} TMDS_COLOR_FORMAT;
++typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
++	TMDS_STEREOSYNC_CTL0                             = 0x0,
++	TMDS_STEREOSYNC_CTL1                             = 0x1,
++	TMDS_STEREOSYNC_CTL2                             = 0x2,
++	TMDS_STEREOSYNC_CTL3                             = 0x3,
++} TMDS_STEREOSYNC_CTL_SEL_REG;
++typedef enum TMDS_CTL0_DATA_SEL {
++	TMDS_CTL0_DATA_SEL0_RESERVED                     = 0x0,
++	TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
++	TMDS_CTL0_DATA_SEL2_VSYNC                        = 0x2,
++	TMDS_CTL0_DATA_SEL3_RESERVED                     = 0x3,
++	TMDS_CTL0_DATA_SEL4_HSYNC                        = 0x4,
++	TMDS_CTL0_DATA_SEL5_SEL7_RESERVED                = 0x5,
++	TMDS_CTL0_DATA_SEL8_RANDOM_DATA                  = 0x6,
++	TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA            = 0x7,
++} TMDS_CTL0_DATA_SEL;
++typedef enum TMDS_CTL0_DATA_DELAY {
++	TMDS_CTL0_DATA_DELAY_0PIX                        = 0x0,
++	TMDS_CTL0_DATA_DELAY_1PIX                        = 0x1,
++	TMDS_CTL0_DATA_DELAY_2PIX                        = 0x2,
++	TMDS_CTL0_DATA_DELAY_3PIX                        = 0x3,
++	TMDS_CTL0_DATA_DELAY_4PIX                        = 0x4,
++	TMDS_CTL0_DATA_DELAY_5PIX                        = 0x5,
++	TMDS_CTL0_DATA_DELAY_6PIX                        = 0x6,
++	TMDS_CTL0_DATA_DELAY_7PIX                        = 0x7,
++} TMDS_CTL0_DATA_DELAY;
++typedef enum TMDS_CTL0_DATA_INVERT {
++	TMDS_CTL0_DATA_NORMAL                            = 0x0,
++	TMDS_CTL0_DATA_INVERT_EN                         = 0x1,
++} TMDS_CTL0_DATA_INVERT;
++typedef enum TMDS_CTL0_DATA_MODULATION {
++	TMDS_CTL0_DATA_MODULATION_DISABLE                = 0x0,
++	TMDS_CTL0_DATA_MODULATION_BIT0                   = 0x1,
++	TMDS_CTL0_DATA_MODULATION_BIT1                   = 0x2,
++	TMDS_CTL0_DATA_MODULATION_BIT2                   = 0x3,
++} TMDS_CTL0_DATA_MODULATION;
++typedef enum TMDS_CTL0_PATTERN_OUT_EN {
++	TMDS_CTL0_PATTERN_OUT_DISABLE                    = 0x0,
++	TMDS_CTL0_PATTERN_OUT_ENABLE                     = 0x1,
++} TMDS_CTL0_PATTERN_OUT_EN;
++typedef enum TMDS_CTL1_DATA_SEL {
++	TMDS_CTL1_DATA_SEL0_RESERVED                     = 0x0,
++	TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
++	TMDS_CTL1_DATA_SEL2_VSYNC                        = 0x2,
++	TMDS_CTL1_DATA_SEL3_RESERVED                     = 0x3,
++	TMDS_CTL1_DATA_SEL4_HSYNC                        = 0x4,
++	TMDS_CTL1_DATA_SEL5_SEL7_RESERVED                = 0x5,
++	TMDS_CTL1_DATA_SEL8_BLANK_TIME                   = 0x6,
++	TMDS_CTL1_DATA_SEL9_SEL15_RESERVED               = 0x7,
++} TMDS_CTL1_DATA_SEL;
++typedef enum TMDS_CTL1_DATA_DELAY {
++	TMDS_CTL1_DATA_DELAY_0PIX                        = 0x0,
++	TMDS_CTL1_DATA_DELAY_1PIX                        = 0x1,
++	TMDS_CTL1_DATA_DELAY_2PIX                        = 0x2,
++	TMDS_CTL1_DATA_DELAY_3PIX                        = 0x3,
++	TMDS_CTL1_DATA_DELAY_4PIX                        = 0x4,
++	TMDS_CTL1_DATA_DELAY_5PIX                        = 0x5,
++	TMDS_CTL1_DATA_DELAY_6PIX                        = 0x6,
++	TMDS_CTL1_DATA_DELAY_7PIX                        = 0x7,
++} TMDS_CTL1_DATA_DELAY;
++typedef enum TMDS_CTL1_DATA_INVERT {
++	TMDS_CTL1_DATA_NORMAL                            = 0x0,
++	TMDS_CTL1_DATA_INVERT_EN                         = 0x1,
++} TMDS_CTL1_DATA_INVERT;
++typedef enum TMDS_CTL1_DATA_MODULATION {
++	TMDS_CTL1_DATA_MODULATION_DISABLE                = 0x0,
++	TMDS_CTL1_DATA_MODULATION_BIT0                   = 0x1,
++	TMDS_CTL1_DATA_MODULATION_BIT1                   = 0x2,
++	TMDS_CTL1_DATA_MODULATION_BIT2                   = 0x3,
++} TMDS_CTL1_DATA_MODULATION;
++typedef enum TMDS_CTL1_PATTERN_OUT_EN {
++	TMDS_CTL1_PATTERN_OUT_DISABLE                    = 0x0,
++	TMDS_CTL1_PATTERN_OUT_ENABLE                     = 0x1,
++} TMDS_CTL1_PATTERN_OUT_EN;
++typedef enum TMDS_CTL2_DATA_SEL {
++	TMDS_CTL2_DATA_SEL0_RESERVED                     = 0x0,
++	TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
++	TMDS_CTL2_DATA_SEL2_VSYNC                        = 0x2,
++	TMDS_CTL2_DATA_SEL3_RESERVED                     = 0x3,
++	TMDS_CTL2_DATA_SEL4_HSYNC                        = 0x4,
++	TMDS_CTL2_DATA_SEL5_SEL7_RESERVED                = 0x5,
++	TMDS_CTL2_DATA_SEL8_BLANK_TIME                   = 0x6,
++	TMDS_CTL2_DATA_SEL9_SEL15_RESERVED               = 0x7,
++} TMDS_CTL2_DATA_SEL;
++typedef enum TMDS_CTL2_DATA_DELAY {
++	TMDS_CTL2_DATA_DELAY_0PIX                        = 0x0,
++	TMDS_CTL2_DATA_DELAY_1PIX                        = 0x1,
++	TMDS_CTL2_DATA_DELAY_2PIX                        = 0x2,
++	TMDS_CTL2_DATA_DELAY_3PIX                        = 0x3,
++	TMDS_CTL2_DATA_DELAY_4PIX                        = 0x4,
++	TMDS_CTL2_DATA_DELAY_5PIX                        = 0x5,
++	TMDS_CTL2_DATA_DELAY_6PIX                        = 0x6,
++	TMDS_CTL2_DATA_DELAY_7PIX                        = 0x7,
++} TMDS_CTL2_DATA_DELAY;
++typedef enum TMDS_CTL2_DATA_INVERT {
++	TMDS_CTL2_DATA_NORMAL                            = 0x0,
++	TMDS_CTL2_DATA_INVERT_EN                         = 0x1,
++} TMDS_CTL2_DATA_INVERT;
++typedef enum TMDS_CTL2_DATA_MODULATION {
++	TMDS_CTL2_DATA_MODULATION_DISABLE                = 0x0,
++	TMDS_CTL2_DATA_MODULATION_BIT0                   = 0x1,
++	TMDS_CTL2_DATA_MODULATION_BIT1                   = 0x2,
++	TMDS_CTL2_DATA_MODULATION_BIT2                   = 0x3,
++} TMDS_CTL2_DATA_MODULATION;
++typedef enum TMDS_CTL2_PATTERN_OUT_EN {
++	TMDS_CTL2_PATTERN_OUT_DISABLE                    = 0x0,
++	TMDS_CTL2_PATTERN_OUT_ENABLE                     = 0x1,
++} TMDS_CTL2_PATTERN_OUT_EN;
++typedef enum TMDS_CTL3_DATA_DELAY {
++	TMDS_CTL3_DATA_DELAY_0PIX                        = 0x0,
++	TMDS_CTL3_DATA_DELAY_1PIX                        = 0x1,
++	TMDS_CTL3_DATA_DELAY_2PIX                        = 0x2,
++	TMDS_CTL3_DATA_DELAY_3PIX                        = 0x3,
++	TMDS_CTL3_DATA_DELAY_4PIX                        = 0x4,
++	TMDS_CTL3_DATA_DELAY_5PIX                        = 0x5,
++	TMDS_CTL3_DATA_DELAY_6PIX                        = 0x6,
++	TMDS_CTL3_DATA_DELAY_7PIX                        = 0x7,
++} TMDS_CTL3_DATA_DELAY;
++typedef enum TMDS_CTL3_DATA_INVERT {
++	TMDS_CTL3_DATA_NORMAL                            = 0x0,
++	TMDS_CTL3_DATA_INVERT_EN                         = 0x1,
++} TMDS_CTL3_DATA_INVERT;
++typedef enum TMDS_CTL3_DATA_MODULATION {
++	TMDS_CTL3_DATA_MODULATION_DISABLE                = 0x0,
++	TMDS_CTL3_DATA_MODULATION_BIT0                   = 0x1,
++	TMDS_CTL3_DATA_MODULATION_BIT1                   = 0x2,
++	TMDS_CTL3_DATA_MODULATION_BIT2                   = 0x3,
++} TMDS_CTL3_DATA_MODULATION;
++typedef enum TMDS_CTL3_PATTERN_OUT_EN {
++	TMDS_CTL3_PATTERN_OUT_DISABLE                    = 0x0,
++	TMDS_CTL3_PATTERN_OUT_ENABLE                     = 0x1,
++} TMDS_CTL3_PATTERN_OUT_EN;
++typedef enum TMDS_CTL3_DATA_SEL {
++	TMDS_CTL3_DATA_SEL0_RESERVED                     = 0x0,
++	TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
++	TMDS_CTL3_DATA_SEL2_VSYNC                        = 0x2,
++	TMDS_CTL3_DATA_SEL3_RESERVED                     = 0x3,
++	TMDS_CTL3_DATA_SEL4_HSYNC                        = 0x4,
++	TMDS_CTL3_DATA_SEL5_SEL7_RESERVED                = 0x5,
++	TMDS_CTL3_DATA_SEL8_BLANK_TIME                   = 0x6,
++	TMDS_CTL3_DATA_SEL9_SEL15_RESERVED               = 0x7,
++} TMDS_CTL3_DATA_SEL;
++typedef enum DIG_FE_CNTL_SOURCE_SELECT {
++	DIG_FE_SOURCE_FROM_FMT0                          = 0x0,
++	DIG_FE_SOURCE_FROM_FMT1                          = 0x1,
++	DIG_FE_SOURCE_FROM_FMT2                          = 0x2,
++	DIG_FE_SOURCE_FROM_FMT3                          = 0x3,
++} DIG_FE_CNTL_SOURCE_SELECT;
++typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
++	DIG_FE_STEREOSYNC_FROM_FMT0                      = 0x0,
++	DIG_FE_STEREOSYNC_FROM_FMT1                      = 0x1,
++	DIG_FE_STEREOSYNC_FROM_FMT2                      = 0x2,
++	DIG_FE_STEREOSYNC_FROM_FMT3                      = 0x3,
++} DIG_FE_CNTL_STEREOSYNC_SELECT;
++typedef enum DIG_FIFO_READ_CLOCK_SRC {
++	DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG                = 0x0,
++	DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE        = 0x1,
++} DIG_FIFO_READ_CLOCK_SRC;
++typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
++	DIG_OUTPUT_CRC_ON_LINK0                          = 0x0,
++	DIG_OUTPUT_CRC_ON_LINK1                          = 0x1,
++} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
++typedef enum DIG_OUTPUT_CRC_DATA_SEL {
++	DIG_OUTPUT_CRC_FOR_FULLFRAME                     = 0x0,
++	DIG_OUTPUT_CRC_FOR_ACTIVEONLY                    = 0x1,
++	DIG_OUTPUT_CRC_FOR_VBI                           = 0x2,
++	DIG_OUTPUT_CRC_FOR_AUDIO                         = 0x3,
++} DIG_OUTPUT_CRC_DATA_SEL;
++typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
++	DIG_IN_NORMAL_OPERATION                          = 0x0,
++	DIG_IN_DEBUG_MODE                                = 0x1,
++} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
++typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
++	DIG_10BIT_TEST_PATTERN                           = 0x0,
++	DIG_ALTERNATING_TEST_PATTERN                     = 0x1,
++} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
++typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
++	DIG_TEST_PATTERN_NORMAL                          = 0x0,
++	DIG_TEST_PATTERN_RANDOM                          = 0x1,
++} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
++typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
++	DIG_RANDOM_PATTERN_ENABLED                       = 0x0,
++	DIG_RANDOM_PATTERN_RESETED                       = 0x1,
++} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
++typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
++	DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE           = 0x0,
++	DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG       = 0x1,
++} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
++typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
++	DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS       = 0x0,
++	DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH          = 0x1,
++} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
++typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
++	DIG_FIFO_USE_OVERWRITE_LEVEL                     = 0x0,
++	DIG_FIFO_USE_CAL_AVERAGE_LEVEL                   = 0x1,
++} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
++typedef enum DIG_FIFO_ERROR_ACK {
++	DIG_FIFO_ERROR_ACK_INT                           = 0x0,
++	DIG_FIFO_ERROR_NOT_ACK                           = 0x1,
++} DIG_FIFO_ERROR_ACK;
++typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
++	DIG_FIFO_NOT_FORCE_RECAL_AVERAGE                 = 0x0,
++	DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL               = 0x1,
++} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
++typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
++	DIG_FIFO_NOT_FORCE_RECOMP_MINMAX                 = 0x0,
++	DIG_FIFO_FORCE_RECOMP_MINMAX                     = 0x1,
++} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
++typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
++	DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK               = 0x0,
++	DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC                = 0x1,
++} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
++typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
++	DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT               = 0x0,
++	DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK           = 0x1,
++} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
++typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
++	DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT              = 0x0,
++	DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK            = 0x1,
++} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
++typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
++	AFMT_INTERRUPT_DISABLE                           = 0x0,
++	AFMT_INTERRUPT_ENABLE                            = 0x1,
++} AFMT_INTERRUPT_STATUS_CHG_MASK;
++typedef enum HDMI_GC_AVMUTE {
++	HDMI_GC_AVMUTE_SET                               = 0x0,
++	HDMI_GC_AVMUTE_UNSET                             = 0x1,
++} HDMI_GC_AVMUTE;
++typedef enum HDMI_DEFAULT_PAHSE {
++	HDMI_DEFAULT_PHASE_IS_0                          = 0x0,
++	HDMI_DEFAULT_PHASE_IS_1                          = 0x1,
++} HDMI_DEFAULT_PAHSE;
++typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
++	AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
++	AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER               = 0x1,
++} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
++typedef enum AUDIO_LAYOUT_SELECT {
++	AUDIO_LAYOUT_0                                   = 0x0,
++	AUDIO_LAYOUT_1                                   = 0x1,
++} AUDIO_LAYOUT_SELECT;
++typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
++	AFMT_AUDIO_CRC_ONESHOT                           = 0x0,
++	AFMT_AUDIO_CRC_AUTO_RESTART                      = 0x1,
++} AFMT_AUDIO_CRC_CONTROL_CONT;
++typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
++	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT            = 0x0,
++	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT           = 0x1,
++} AFMT_AUDIO_CRC_CONTROL_SOURCE;
++typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
++	AFMT_AUDIO_CRC_CH0_SIG                           = 0x0,
++	AFMT_AUDIO_CRC_CH1_SIG                           = 0x1,
++	AFMT_AUDIO_CRC_CH2_SIG                           = 0x2,
++	AFMT_AUDIO_CRC_CH3_SIG                           = 0x3,
++	AFMT_AUDIO_CRC_CH4_SIG                           = 0x4,
++	AFMT_AUDIO_CRC_CH5_SIG                           = 0x5,
++	AFMT_AUDIO_CRC_CH6_SIG                           = 0x6,
++	AFMT_AUDIO_CRC_CH7_SIG                           = 0x7,
++	AFMT_AUDIO_CRC_RESERVED                          = 0x8,
++	AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT                = 0x9,
++} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
++typedef enum AFMT_RAMP_CONTROL0_SIGN {
++	AFMT_RAMP_SIGNED                                 = 0x0,
++	AFMT_RAMP_UNSIGNED                               = 0x1,
++} AFMT_RAMP_CONTROL0_SIGN;
++typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
++	AFMT_AUDIO_PACKET_SENT_DISABLED                  = 0x0,
++	AFMT_AUDIO_PACKET_SENT_ENABLED                   = 0x1,
++} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
++typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
++	AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
++	AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED        = 0x1,
++} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
++typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
++	AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK          = 0x0,
++	AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS        = 0x1,
++} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
++typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
++	AFMT_AUDIO_SRC_FROM_AZ_STREAM0                   = 0x0,
++	AFMT_AUDIO_SRC_FROM_AZ_STREAM1                   = 0x1,
++	AFMT_AUDIO_SRC_FROM_AZ_STREAM2                   = 0x2,
++	AFMT_AUDIO_SRC_FROM_AZ_STREAM3                   = 0x3,
++	AFMT_AUDIO_SRC_FROM_AZ_STREAM4                   = 0x4,
++	AFMT_AUDIO_SRC_FROM_AZ_STREAM5                   = 0x5,
++	AFMT_AUDIO_SRC_RESERVED                          = 0x6,
++} AFMT_AUDIO_SRC_CONTROL_SELECT;
++typedef enum DIG_BE_CNTL_MODE {
++	DIG_BE_DP_SST_MODE                               = 0x0,
++	DIG_BE_RESERVED1                                 = 0x1,
++	DIG_BE_TMDS_DVI_MODE                             = 0x2,
++	DIG_BE_TMDS_HDMI_MODE                            = 0x3,
++	DIG_BE_SDVO_RESERVED                             = 0x4,
++	DIG_BE_DP_MST_MODE                               = 0x5,
++	DIG_BE_RESERVED2                                 = 0x6,
++	DIG_BE_RESERVED3                                 = 0x7,
++} DIG_BE_CNTL_MODE;
++typedef enum DIG_BE_CNTL_HPD_SELECT {
++	DIG_BE_CNTL_HPD1                                 = 0x0,
++	DIG_BE_CNTL_HPD2                                 = 0x1,
++	DIG_BE_CNTL_HPD3                                 = 0x2,
++	DIG_BE_CNTL_HPD4                                 = 0x3,
++	DIG_BE_CNTL_HPD5                                 = 0x4,
++	DIG_BE_CNTL_HPD6                                 = 0x5,
++} DIG_BE_CNTL_HPD_SELECT;
++typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
++	LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS             = 0x0,
++	LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH           = 0x1,
++} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
++typedef enum TMDS_SYNC_PHASE {
++	TMDS_NOT_SYNC_PHASE_ON_FRAME_START               = 0x0,
++	TMDS_SYNC_PHASE_ON_FRAME_START                   = 0x1,
++} TMDS_SYNC_PHASE;
++typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
++	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS     = 0x0,
++	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL      = 0x1,
++} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
++typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
++	TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE           = 0x0,
++	TMDS_TRANSMITTER_HPD_MASK_OVERRIDE               = 0x1,
++} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
++typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
++	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
++	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE        = 0x1,
++} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
++typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
++	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
++	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE        = 0x1,
++} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
++typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
++	TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE     = 0x0,
++	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
++	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x2,
++	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE         = 0x3,
++} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
++typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
++	TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK           = 0x0,
++	TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK             = 0x1,
++} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
++typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
++	TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK           = 0x0,
++	TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK             = 0x1,
++} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
++typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
++	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE           = 0x0,
++	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE            = 0x1,
++} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
++typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
++	TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD              = 0x0,
++	TMDS_TRANSMITTER_PLL_RST_ON_HPD                  = 0x1,
++} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
++typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
++	TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK           = 0x0,
++	TMDS_TRANSMITTER_TMCLK_FROM_PADS                 = 0x1,
++} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
++typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
++	TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK           = 0x0,
++	TMDS_TRANSMITTER_TDCLK_FROM_PADS                 = 0x1,
++} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
++typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
++	TMDS_TRANSMITTER_PLLSEL_BY_HW                    = 0x0,
++	TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW          = 0x1,
++} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
++typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
++	TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT            = 0x0,
++	TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT          = 0x1,
++} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
++typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
++	TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT            = 0x0,
++	TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT          = 0x1,
++} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
++typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
++	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0              = 0x0,
++	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1              = 0x1,
++	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2              = 0x2,
++	TMDS_REG_TEST_OUTPUTA_CNTLA_NA                   = 0x3,
++} TMDS_REG_TEST_OUTPUTA_CNTLA;
++typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
++	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0              = 0x0,
++	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1              = 0x1,
++	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2              = 0x2,
++	TMDS_REG_TEST_OUTPUTB_CNTLB_NA                   = 0x3,
++} TMDS_REG_TEST_OUTPUTB_CNTLB;
++typedef enum DP_LINK_TRAINING_COMPLETE {
++	DP_LINK_TRAINING_NOT_COMPLETE                    = 0x0,
++	DP_LINK_TRAINING_ALREADY_COMPLETE                = 0x1,
++} DP_LINK_TRAINING_COMPLETE;
++typedef enum DP_EMBEDDED_PANEL_MODE {
++	DP_EXTERNAL_PANEL                                = 0x0,
++	DP_EMBEDDED_PANEL                                = 0x1,
++} DP_EMBEDDED_PANEL_MODE;
++typedef enum DP_PIXEL_ENCODING {
++	DP_PIXEL_ENCODING_RGB444                         = 0x0,
++	DP_PIXEL_ENCODING_YCBCR422                       = 0x1,
++	DP_PIXEL_ENCODING_YCBCR444                       = 0x2,
++	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT                 = 0x3,
++	DP_PIXEL_ENCODING_Y_ONLY                         = 0x4,
++	DP_PIXEL_ENCODING_RESERVED                       = 0x5,
++} DP_PIXEL_ENCODING;
++typedef enum DP_DYN_RANGE {
++	DP_DYN_VESA_RANGE                                = 0x0,
++	DP_DYN_CEA_RANGE                                 = 0x1,
++} DP_DYN_RANGE;
++typedef enum DP_YCBCR_RANGE {
++	DP_YCBCR_RANGE_BT601_5                           = 0x0,
++	DP_YCBCR_RANGE_BT709_5                           = 0x1,
++} DP_YCBCR_RANGE;
++typedef enum DP_COMPONENT_DEPTH {
++	DP_COMPONENT_DEPTH_6BPC                          = 0x0,
++	DP_COMPONENT_DEPTH_8BPC                          = 0x1,
++	DP_COMPONENT_DEPTH_10BPC                         = 0x2,
++	DP_COMPONENT_DEPTH_12BPC                         = 0x3,
++	DP_COMPONENT_DEPTH_16BPC                         = 0x4,
++	DP_COMPONENT_DEPTH_RESERVED                      = 0x5,
++} DP_COMPONENT_DEPTH;
++typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
++	MSA_MISC0_OVERRIDE_DISABLE                       = 0x0,
++	MSA_MISC0_OVERRIDE_ENABLE                        = 0x1,
++} DP_MSA_MISC0_OVERRIDE_ENABLE;
++typedef enum DP_UDI_LANES {
++	DP_UDI_1_LANE                                    = 0x0,
++	DP_UDI_2_LANES                                   = 0x1,
++	DP_UDI_LANES_RESERVED                            = 0x2,
++	DP_UDI_4_LANES                                   = 0x3,
++} DP_UDI_LANES;
++typedef enum DP_VID_STREAM_DIS_DEFER {
++	DP_VID_STREAM_DIS_NO_DEFER                       = 0x0,
++	DP_VID_STREAM_DIS_DEFER_TO_HBLANK                = 0x1,
++	DP_VID_STREAM_DIS_DEFER_TO_VBLANK                = 0x2,
++} DP_VID_STREAM_DIS_DEFER;
++typedef enum DP_STEER_OVERFLOW_ACK {
++	DP_STEER_OVERFLOW_ACK_NO_EFFECT                  = 0x0,
++	DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT              = 0x1,
++} DP_STEER_OVERFLOW_ACK;
++typedef enum DP_STEER_OVERFLOW_MASK {
++	DP_STEER_OVERFLOW_MASKED                         = 0x0,
++	DP_STEER_OVERFLOW_UNMASK                         = 0x1,
++} DP_STEER_OVERFLOW_MASK;
++typedef enum DP_TU_OVERFLOW_ACK {
++	DP_TU_OVERFLOW_ACK_NO_EFFECT                     = 0x0,
++	DP_TU_OVERFLOW_ACK_CLR_INTERRUPT                 = 0x1,
++} DP_TU_OVERFLOW_ACK;
++typedef enum DP_VID_TIMING_MODE {
++	DP_VID_TIMING_MODE_ASYNC                         = 0x0,
++	DP_VID_TIMING_MODE_SYNC                          = 0x1,
++} DP_VID_TIMING_MODE;
++typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
++	DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE      = 0x0,
++	DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START          = 0x1,
++} DP_VID_M_N_DOUBLE_BUFFER_MODE;
++typedef enum DP_VID_M_N_GEN_EN {
++	DP_VID_M_N_PROGRAMMED_VIA_REG                    = 0x0,
++	DP_VID_M_N_CALC_AUTO                             = 0x1,
++} DP_VID_M_N_GEN_EN;
++typedef enum DP_VID_ENHANCED_FRAME_MODE {
++	VID_NORMAL_FRAME_MODE                            = 0x0,
++	VID_ENHANCED_MODE                                = 0x1,
++} DP_VID_ENHANCED_FRAME_MODE;
++typedef enum DP_VID_MSA_TOP_FIELD_MODE {
++	DP_TOP_FIELD_ONLY                                = 0x0,
++	DP_TOP_PLUS_BOTTOM_FIELD                         = 0x1,
++} DP_VID_MSA_TOP_FIELD_MODE;
++typedef enum DP_VID_VBID_FIELD_POL {
++	DP_VID_VBID_FIELD_POL_NORMAL                     = 0x0,
++	DP_VID_VBID_FIELD_POL_INV                        = 0x1,
++} DP_VID_VBID_FIELD_POL;
++typedef enum DP_VID_STREAM_DISABLE_ACK {
++	ID_STREAM_DISABLE_NO_ACK                         = 0x0,
++	ID_STREAM_DISABLE_ACKED                          = 0x1,
++} DP_VID_STREAM_DISABLE_ACK;
++typedef enum DP_VID_STREAM_DISABLE_MASK {
++	VID_STREAM_DISABLE_MASKED                        = 0x0,
++	VID_STREAM_DISABLE_UNMASK                        = 0x1,
++} DP_VID_STREAM_DISABLE_MASK;
++typedef enum DPHY_ATEST_SEL_LANE0 {
++	DPHY_ATEST_LANE0_PRBS_PATTERN                    = 0x0,
++	DPHY_ATEST_LANE0_REG_PATTERN                     = 0x1,
++} DPHY_ATEST_SEL_LANE0;
++typedef enum DPHY_ATEST_SEL_LANE1 {
++	DPHY_ATEST_LANE1_PRBS_PATTERN                    = 0x0,
++	DPHY_ATEST_LANE1_REG_PATTERN                     = 0x1,
++} DPHY_ATEST_SEL_LANE1;
++typedef enum DPHY_ATEST_SEL_LANE2 {
++	DPHY_ATEST_LANE2_PRBS_PATTERN                    = 0x0,
++	DPHY_ATEST_LANE2_REG_PATTERN                     = 0x1,
++} DPHY_ATEST_SEL_LANE2;
++typedef enum DPHY_ATEST_SEL_LANE3 {
++	DPHY_ATEST_LANE3_PRBS_PATTERN                    = 0x0,
++	DPHY_ATEST_LANE3_REG_PATTERN                     = 0x1,
++} DPHY_ATEST_SEL_LANE3;
++typedef enum DPHY_BYPASS {
++	DPHY_8B10B_OUTPUT                                = 0x0,
++	DPHY_DBG_OUTPUT                                  = 0x1,
++} DPHY_BYPASS;
++typedef enum DPHY_SKEW_BYPASS {
++	DPHY_WITH_SKEW                                   = 0x0,
++	DPHY_NO_SKEW                                     = 0x1,
++} DPHY_SKEW_BYPASS;
++typedef enum DPHY_TRAINING_PATTERN_SEL {
++	DPHY_TRAINING_PATTERN_1                          = 0x0,
++	DPHY_TRAINING_PATTERN_2                          = 0x1,
++	DPHY_TRAINING_PATTERN_3                          = 0x2,
++} DPHY_TRAINING_PATTERN_SEL;
++typedef enum DPHY_8B10B_RESET {
++	DPHY_8B10B_NOT_RESET                             = 0x0,
++	DPHY_8B10B_RESETET                               = 0x1,
++} DPHY_8B10B_RESET;
++typedef enum DP_DPHY_8B10B_EXT_DISP {
++	DP_DPHY_8B10B_EXT_DISP_ZERO                      = 0x0,
++	DP_DPHY_8B10B_EXT_DISP_ONE                       = 0x1,
++} DP_DPHY_8B10B_EXT_DISP;
++typedef enum DPHY_8B10B_CUR_DISP {
++	DPHY_8B10B_CUR_DISP_ZERO                         = 0x0,
++	DPHY_8B10B_CUR_DISP_ONE                          = 0x1,
++} DPHY_8B10B_CUR_DISP;
++typedef enum DPHY_PRBS_EN {
++	DPHY_PRBS_DISABLE                                = 0x0,
++	DPHY_PRBS_ENABLE                                 = 0x1,
++} DPHY_PRBS_EN;
++typedef enum DPHY_PRBS_SEL {
++	DPHY_PRBS7_SELECTED                              = 0x0,
++	DPHY_PRBS23_SELECTED                             = 0x1,
++	DPHY_PRBS11_SELECTED                             = 0x2,
++} DPHY_PRBS_SEL;
++typedef enum DPHY_LOAD_BS_COUNT_START {
++	DPHY_LOAD_BS_COUNT_STARTED                       = 0x0,
++	DPHY_LOAD_BS_COUNT_NOT_STARTED                   = 0x1,
++} DPHY_LOAD_BS_COUNT_START;
++typedef enum DPHY_CRC_EN {
++	DPHY_CRC_DISABLED                                = 0x0,
++	DPHY_CRC_ENABLED                                 = 0x1,
++} DPHY_CRC_EN;
++typedef enum DPHY_CRC_CONT_EN {
++	DPHY_CRC_ONE_SHOT                                = 0x0,
++	DPHY_CRC_CONTINUOUS                              = 0x1,
++} DPHY_CRC_CONT_EN;
++typedef enum DPHY_CRC_FIELD {
++	DPHY_CRC_START_FROM_TOP_FIELD                    = 0x0,
++	DPHY_CRC_START_FROM_BOTTOM_FIELD                 = 0x1,
++} DPHY_CRC_FIELD;
++typedef enum DPHY_CRC_SEL {
++	DPHY_CRC_LANE0_SELECTED                          = 0x0,
++	DPHY_CRC_LANE1_SELECTED                          = 0x1,
++	DPHY_CRC_LANE2_SELECTED                          = 0x2,
++	DPHY_CRC_LANE3_SELECTED                          = 0x3,
++} DPHY_CRC_SEL;
++typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
++	DPHY_FAST_TRAINING_NOT_CAPABLE_0                 = 0x0,
++	DPHY_FAST_TRAINING_CAPABLE                       = 0x1,
++} DPHY_RX_FAST_TRAINING_CAPABLE;
++typedef enum DP_SEC_COLLISION_ACK {
++	DP_SEC_COLLISION_ACK_NO_EFFECT                   = 0x0,
++	DP_SEC_COLLISION_ACK_CLR_FLAG                    = 0x1,
++} DP_SEC_COLLISION_ACK;
++typedef enum DP_SEC_AUDIO_MUTE {
++	DP_SEC_AUDIO_MUTE_HW_CTRL                        = 0x0,
++	DP_SEC_AUDIO_MUTE_SW_CTRL                        = 0x1,
++} DP_SEC_AUDIO_MUTE;
++typedef enum DP_SEC_TIMESTAMP_MODE {
++	DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE               = 0x0,
++	DP_SEC_TIMESTAMP_AUTO_CALC_MODE                  = 0x1,
++} DP_SEC_TIMESTAMP_MODE;
++typedef enum DP_SEC_ASP_PRIORITY {
++	DP_SEC_ASP_LOW_PRIORITY                          = 0x0,
++	DP_SEC_ASP_HIGH_PRIORITY                         = 0x1,
++} DP_SEC_ASP_PRIORITY;
++typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
++	DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ                 = 0x0,
++	DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED        = 0x1,
++} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
++typedef enum DP_MSE_SAT_UPDATE_ACT {
++	DP_MSE_SAT_UPDATE_NO_ACTION                      = 0x0,
++	DP_MSE_SAT_UPDATE_WITH_TRIGGER                   = 0x1,
++	DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER                = 0x2,
++} DP_MSE_SAT_UPDATE_ACT;
++typedef enum DP_MSE_LINK_LINE {
++	DP_MSE_LINK_LINE_32_MTP_LONG                     = 0x0,
++	DP_MSE_LINK_LINE_64_MTP_LONG                     = 0x1,
++	DP_MSE_LINK_LINE_128_MTP_LONG                    = 0x2,
++	DP_MSE_LINK_LINE_256_MTP_LONG                    = 0x3,
++} DP_MSE_LINK_LINE;
++typedef enum DP_MSE_BLANK_CODE {
++	DP_MSE_BLANK_CODE_SF_FILLED                      = 0x0,
++	DP_MSE_BLANK_CODE_ZERO_FILLED                    = 0x1,
++} DP_MSE_BLANK_CODE;
++typedef enum DP_MSE_TIMESTAMP_MODE {
++	DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE         = 0x0,
++	DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE           = 0x1,
++} DP_MSE_TIMESTAMP_MODE;
++typedef enum DP_MSE_ZERO_ENCODER {
++	DP_MSE_NOT_ZERO_FE_ENCODER                       = 0x0,
++	DP_MSE_ZERO_FE_ENCODER                           = 0x1,
++} DP_MSE_ZERO_ENCODER;
++typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
++	DP_MSE_OUTPUT_DPDBG_DATA_DIS                     = 0x0,
++	DP_MSE_OUTPUT_DPDBG_DATA_EN                      = 0x1,
++} DP_MSE_OUTPUT_DPDBG_DATA;
++typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
++	DP_DPHY_HBR2_PASS_THROUGH                        = 0x0,
++	DP_DPHY_HBR2_PATTERN_1                           = 0x1,
++	DP_DPHY_HBR2_PATTERN_2_NEG                       = 0x2,
++	DP_DPHY_HBR2_PATTERN_3                           = 0x3,
++	DP_DPHY_HBR2_PATTERN_2_POS                       = 0x6,
++} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
++typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
++	DPHY_CRC_MST_PHASE_ERROR_NO_ACK                  = 0x0,
++	DPHY_CRC_MST_PHASE_ERROR_ACKED                   = 0x1,
++} DPHY_CRC_MST_PHASE_ERROR_ACK;
++typedef enum DPHY_SW_FAST_TRAINING_START {
++	DPHY_SW_FAST_TRAINING_NOT_STARTED                = 0x0,
++	DPHY_SW_FAST_TRAINING_STARTED                    = 0x1,
++} DPHY_SW_FAST_TRAINING_START;
++typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
++	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
++	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
++} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
++typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
++	DP_DPHY_FAST_TRAINING_COMPLETE_MASKED            = 0x0,
++	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED        = 0x1,
++} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
++typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
++	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED         = 0x0,
++	DP_DPHY_FAST_TRAINING_COMPLETE_ACKED             = 0x1,
++} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
++typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
++	MSA_V_TIMING_OVERRIDE_DISABLED                   = 0x0,
++	MSA_V_TIMING_OVERRIDE_ENABLED                    = 0x1,
++} DP_MSA_V_TIMING_OVERRIDE_EN;
++typedef enum DP_SEC_GSP0_PRIORITY {
++	SEC_GSP0_PRIORITY_LOW                            = 0x0,
++	SEC_GSP0_PRIORITY_HIGH                           = 0x1,
++} DP_SEC_GSP0_PRIORITY;
++typedef enum DP_SEC_GSP0_SEND {
++	NOT_SENT                                         = 0x0,
++	FORCE_SENT                                       = 0x1,
++} DP_SEC_GSP0_SEND;
++typedef enum DP_AUX_CONTROL_HPD_SEL {
++	DP_AUX_CONTROL_HPD1_SELECTED                     = 0x0,
++	DP_AUX_CONTROL_HPD2_SELECTED                     = 0x1,
++	DP_AUX_CONTROL_HPD3_SELECTED                     = 0x2,
++	DP_AUX_CONTROL_HPD4_SELECTED                     = 0x3,
++	DP_AUX_CONTROL_HPD5_SELECTED                     = 0x4,
++	DP_AUX_CONTROL_HPD6_SELECTED                     = 0x5,
++} DP_AUX_CONTROL_HPD_SEL;
++typedef enum DP_AUX_CONTROL_TEST_MODE {
++	DP_AUX_CONTROL_TEST_MODE_DISABLE                 = 0x0,
++	DP_AUX_CONTROL_TEST_MODE_ENABLE                  = 0x1,
++} DP_AUX_CONTROL_TEST_MODE;
++typedef enum DP_AUX_SW_CONTROL_SW_GO {
++	DP_AUX_SW_CONTROL_SW__NOT_GO                     = 0x0,
++	DP_AUX_SW_CONTROL_SW__GO                         = 0x1,
++} DP_AUX_SW_CONTROL_SW_GO;
++typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
++	DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG              = 0x0,
++	DP_AUX_SW_CONTROL_LS_READ__TRIG                  = 0x1,
++} DP_AUX_SW_CONTROL_LS_READ_TRIG;
++typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
++	DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW       = 0x0,
++	DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW       = 0x1,
++	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC       = 0x2,
++	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS       = 0x3,
++} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
++typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
++	DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ          = 0x0,
++	DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ              = 0x1,
++} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
++typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
++	DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG       = 0x0,
++	DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG           = 0x1,
++} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
++typedef enum DP_AUX_INT_ACK {
++	DP_AUX_INT__NOT_ACK                              = 0x0,
++	DP_AUX_INT__ACK                                  = 0x1,
++} DP_AUX_INT_ACK;
++typedef enum DP_AUX_LS_UPDATE_ACK {
++	DP_AUX_INT_LS_UPDATE_NOT_ACK                     = 0x0,
++	DP_AUX_INT_LS_UPDATE_ACK                         = 0x1,
++} DP_AUX_LS_UPDATE_ACK;
++typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
++	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
++	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
++} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
++typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
++	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ         = 0x0,
++	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ         = 0x1,
++	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ         = 0x2,
++	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ         = 0x3,
++} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
++typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US        = 0x0,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US        = 0x1,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US       = 0x2,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US       = 0x3,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US       = 0x4,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US       = 0x5,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US       = 0x6,
++	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US       = 0x7,
++} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
++typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
++	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0   = 0x0,
++	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
++	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
++	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
++	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
++	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
++} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
++typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
++	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
++} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
++typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
++	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
++} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
++typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
++	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
++	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
++	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
++	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
++} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
++typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
++	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
++	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
++} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
++typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
++	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
++	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
++} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
++typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
++	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
++	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
++} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
++typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
++	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
++	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
++	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
++	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
++} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
++typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US         = 0x0,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US         = 0x1,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US         = 0x2,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US         = 0x3,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US         = 0x4,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US         = 0x5,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US         = 0x6,
++	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US         = 0x7,
++} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
++typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2         = 0x0,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4         = 0x1,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8         = 0x2,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16       = 0x3,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32       = 0x4,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64       = 0x5,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128     = 0x6,
++	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256     = 0x7,
++} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
++typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
++	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
++	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
++} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
++typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
++	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
++	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
++	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
++	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
++} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
++typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
++	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
++	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
++	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
++	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
++} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
++typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
++	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
++	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
++	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
++	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
++} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
++typedef enum DP_AUX_ERR_OCCURRED_ACK {
++	DP_AUX_ERR_OCCURRED__NOT_ACK                     = 0x0,
++	DP_AUX_ERR_OCCURRED__ACK                         = 0x1,
++} DP_AUX_ERR_OCCURRED_ACK;
++typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
++	DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK            = 0x0,
++	DP_AUX_POTENTIAL_ERR_REACHED__ACK                = 0x1,
++} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
++typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
++	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK        = 0x0,
++	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK            = 0x1,
++} DP_AUX_DEFINITE_ERR_REACHED_ACK;
++typedef enum DP_AUX_RESET {
++	DP_AUX_RESET_DEASSERTED                          = 0x0,
++	DP_AUX_RESET_ASSERTED                            = 0x1,
++} DP_AUX_RESET;
++typedef enum DP_AUX_RESET_DONE {
++	DP_AUX_RESET_SEQUENCE_NOT_DONE                   = 0x0,
++	DP_AUX_RESET_SEQUENCE_DONE                       = 0x1,
++} DP_AUX_RESET_DONE;
++typedef enum FMT_CONTROL_PIXEL_ENCODING {
++	FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444    = 0x0,
++	FMT_CONTROL_PIXEL_ENCODING_YCBCR422              = 0x1,
++} FMT_CONTROL_PIXEL_ENCODING;
++typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
++	FMT_CONTROL_SUBSAMPLING_MODE_DROP                = 0x0,
++	FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE             = 0x1,
++} FMT_CONTROL_SUBSAMPLING_MODE;
++typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
++	FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR       = 0x0,
++	FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB       = 0x1,
++} FMT_CONTROL_SUBSAMPLING_ORDER;
++typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
++	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION   = 0x0,
++	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING     = 0x1,
++} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
++typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
++	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP       = 0x0,
++	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP       = 0x1,
++	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP       = 0x2,
++} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
++typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
++	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
++	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
++	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
++} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
++typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
++	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
++	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
++	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
++} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
++typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
++	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
++	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
++} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
++typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
++	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei               = 0x0,
++	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi               = 0x1,
++	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi               = 0x2,
++	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED         = 0x3,
++} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
++typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
++	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A                = 0x0,
++	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B                = 0x1,
++	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C                = 0x2,
++	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D                = 0x3,
++} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
++typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
++	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E                = 0x0,
++	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F                = 0x1,
++	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G                = 0x2,
++	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED         = 0x3,
++} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
++typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
++	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
++	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
++} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
++typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
++	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
++	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
++} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
++typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
++	FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC                 = 0x0,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC                 = 0x1,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC                = 0x2,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED0            = 0x3,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1            = 0x4,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2            = 0x5,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3            = 0x6,
++	FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE         = 0x7,
++} FMT_CLAMP_CNTL_COLOR_FORMAT;
++typedef enum FMT_CRC_CNTL_CONT_EN {
++	FMT_CRC_CNTL_CONT_EN_ONE_SHOT                    = 0x0,
++	FMT_CRC_CNTL_CONT_EN_CONT                        = 0x1,
++} FMT_CRC_CNTL_CONT_EN;
++typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
++	FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE        = 0x0,
++	FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE            = 0x1,
++} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
++typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
++	FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD            = 0x0,
++	FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK               = 0x1,
++} FMT_CRC_CNTL_ONLY_BLANKB;
++typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
++	FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL              = 0x0,
++	FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC         = 0x1,
++} FMT_CRC_CNTL_PSR_MODE_ENABLE;
++typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
++	FMT_CRC_CNTL_INTERLACE_MODE_TOP                  = 0x0,
++	FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM               = 0x1,
++	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM          = 0x2,
++	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH            = 0x3,
++} FMT_CRC_CNTL_INTERLACE_MODE;
++typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
++	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL             = 0x0,
++	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN        = 0x1,
++} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
++typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
++	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN            = 0x0,
++	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD             = 0x1,
++} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
++typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
++	FMT_DEBUG_CNTL_COLOR_SELECT_BLUE                 = 0x0,
++	FMT_DEBUG_CNTL_COLOR_SELECT_GREEN                = 0x1,
++	FMT_DEBUG_CNTL_COLOR_SELECT_RED1                 = 0x2,
++	FMT_DEBUG_CNTL_COLOR_SELECT_RED2                 = 0x3,
++} FMT_DEBUG_CNTL_COLOR_SELECT;
++typedef enum FMT_SPATIAL_DITHER_MODE {
++	FMT_SPATIAL_DITHER_MODE_0                        = 0x0,
++	FMT_SPATIAL_DITHER_MODE_1                        = 0x1,
++	FMT_SPATIAL_DITHER_MODE_2                        = 0x2,
++	FMT_SPATIAL_DITHER_MODE_3                        = 0x3,
++} FMT_SPATIAL_DITHER_MODE;
++typedef enum FMT_STEREOSYNC_OVR_POL {
++	FMT_STEREOSYNC_OVR_POL_INVERTED                  = 0x0,
++	FMT_STEREOSYNC_OVR_POL_NOT_INVERTED              = 0x1,
++} FMT_STEREOSYNC_OVR_POL;
++typedef enum FMT_DYNAMIC_EXP_MODE {
++	FMT_DYNAMIC_EXP_MODE_10to12                      = 0x0,
++	FMT_DYNAMIC_EXP_MODE_8to12                       = 0x1,
++} FMT_DYNAMIC_EXP_MODE;
++typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
++	LB_DATA_FORMAT_PIXEL_DEPTH_30BPP                 = 0x0,
++	LB_DATA_FORMAT_PIXEL_DEPTH_24BPP                 = 0x1,
++	LB_DATA_FORMAT_PIXEL_DEPTH_18BPP                 = 0x2,
++	LB_DATA_FORMAT_PIXEL_DEPTH_36BPP                 = 0x3,
++} LB_DATA_FORMAT_PIXEL_DEPTH;
++typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
++	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
++	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
++} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
++typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
++	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION      = 0x0,
++	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING        = 0x1,
++} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
++typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
++	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP         = 0x0,
++	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP         = 0x1,
++} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
++typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
++	LB_DATA_FORMAT_INTERLEAVE_DISABLE                = 0x0,
++	LB_DATA_FORMAT_INTERLEAVE_ENABLE                 = 0x1,
++} LB_DATA_FORMAT_INTERLEAVE_EN;
++typedef enum LB_DATA_FORMAT_REQUEST_MODE {
++	LB_DATA_FORMAT_REQUEST_MODE_NORMAL               = 0x0,
++	LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE        = 0x1,
++} LB_DATA_FORMAT_REQUEST_MODE;
++typedef enum LB_DATA_FORMAT_ALPHA_EN {
++	LB_DATA_FORMAT_ALPHA_DISABLE                     = 0x0,
++	LB_DATA_FORMAT_ALPHA_ENABLE                      = 0x1,
++} LB_DATA_FORMAT_ALPHA_EN;
++typedef enum LB_VLINE_START_END_VLINE_INV {
++	LB_VLINE_START_END_VLINE_NORMAL                  = 0x0,
++	LB_VLINE_START_END_VLINE_INVERSE                 = 0x1,
++} LB_VLINE_START_END_VLINE_INV;
++typedef enum LB_VLINE2_START_END_VLINE2_INV {
++	LB_VLINE2_START_END_VLINE2_NORMAL                = 0x0,
++	LB_VLINE2_START_END_VLINE2_INVERSE               = 0x1,
++} LB_VLINE2_START_END_VLINE2_INV;
++typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
++	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE       = 0x0,
++	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE        = 0x1,
++} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
++typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
++	LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE        = 0x0,
++	LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE         = 0x1,
++} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
++typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
++	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE       = 0x0,
++	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE        = 0x1,
++} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
++typedef enum LB_VLINE_STATUS_VLINE_ACK {
++	LB_VLINE_STATUS_VLINE_NORMAL                     = 0x0,
++	LB_VLINE_STATUS_VLINE_CLEAR                      = 0x1,
++} LB_VLINE_STATUS_VLINE_ACK;
++typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
++	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
++	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
++} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
++typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
++	LB_VLINE2_STATUS_VLINE2_NORMAL                   = 0x0,
++	LB_VLINE2_STATUS_VLINE2_CLEAR                    = 0x1,
++} LB_VLINE2_STATUS_VLINE2_ACK;
++typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
++	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
++	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
++} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
++typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
++	LB_VBLANK_STATUS_VBLANK_NORMAL                   = 0x0,
++	LB_VBLANK_STATUS_VBLANK_CLEAR                    = 0x1,
++} LB_VBLANK_STATUS_VBLANK_ACK;
++typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
++	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
++	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
++} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
++typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
++	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE      = 0x0,
++	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
++	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
++	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
++} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
++typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
++	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x0,
++	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC   = 0x1,
++} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
++typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
++	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS     = 0x0,
++	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS     = 0x1,
++	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS     = 0x2,
++	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS    = 0x3,
++} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
++typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
++	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE       = 0x0,
++	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE        = 0x1,
++} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
++typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
++	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
++	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
++} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
++typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
++	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL          = 0x0,
++	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET           = 0x1,
++} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
++typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
++	LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL           = 0x0,
++	LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET            = 0x1,
++} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
++typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
++	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
++	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
++} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
++typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
++	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
++	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
++} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
++typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
++	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
++	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
++} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
++typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
++	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
++	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
++	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
++} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
++typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
++	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
++	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN     = 0x1,
++} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
++typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
++	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
++	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
++} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
++typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
++	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
++	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
++} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
++typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
++	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
++	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
++} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
++typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
++	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
++	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
++} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
++typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
++	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
++	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
++} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
++typedef enum LBV_PIXEL_DEPTH {
++	PIXEL_DEPTH_30BPP                                = 0x0,
++	PIXEL_DEPTH_24BPP                                = 0x1,
++	PIXEL_DEPTH_18BPP                                = 0x2,
++	PIXEL_DEPTH_38BPP                                = 0x3,
++} LBV_PIXEL_DEPTH;
++typedef enum LBV_PIXEL_EXPAN_MODE {
++	PIXEL_EXPAN_MODE_ZERO_EXP                        = 0x0,
++	PIXEL_EXPAN_MODE_DYN_EXP                         = 0x1,
++} LBV_PIXEL_EXPAN_MODE;
++typedef enum LBV_INTERLEAVE_EN {
++	INTERLEAVE_DIS                                   = 0x0,
++	INTERLEAVE_EN                                    = 0x1,
++} LBV_INTERLEAVE_EN;
++typedef enum LBV_PIXEL_REDUCE_MODE {
++	PIXEL_REDUCE_MODE_TRUNCATION                     = 0x0,
++	PIXEL_REDUCE_MODE_ROUNDING                       = 0x1,
++} LBV_PIXEL_REDUCE_MODE;
++typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
++	DYNAMIC_PIXEL_DEPTH_36BPP                        = 0x0,
++	DYNAMIC_PIXEL_DEPTH_30BPP                        = 0x1,
++} LBV_DYNAMIC_PIXEL_DEPTH;
++typedef enum LBV_DITHER_EN {
++	DITHER_DIS                                       = 0x0,
++	DITHER_EN                                        = 0x1,
++} LBV_DITHER_EN;
++typedef enum LBV_DOWNSCALE_PREFETCH_EN {
++	DOWNSCALE_PREFETCH_DIS                           = 0x0,
++	DOWNSCALE_PREFETCH_EN                            = 0x1,
++} LBV_DOWNSCALE_PREFETCH_EN;
++typedef enum LBV_MEMORY_CONFIG {
++	MEMORY_CONFIG_0                                  = 0x0,
++	MEMORY_CONFIG_1                                  = 0x1,
++	MEMORY_CONFIG_2                                  = 0x2,
++	MEMORY_CONFIG_3                                  = 0x3,
++} LBV_MEMORY_CONFIG;
++typedef enum LBV_SYNC_RESET_SEL2 {
++	SYNC_RESET_SEL2_VBLANK                           = 0x0,
++	SYNC_RESET_SEL2_VSYNC                            = 0x1,
++} LBV_SYNC_RESET_SEL2;
++typedef enum LBV_SYNC_DURATION {
++	SYNC_DURATION_16                                 = 0x0,
++	SYNC_DURATION_32                                 = 0x1,
++	SYNC_DURATION_64                                 = 0x2,
++	SYNC_DURATION_128                                = 0x3,
++} LBV_SYNC_DURATION;
++typedef enum SCL_C_RAM_TAP_PAIR_IDX {
++	SCL_C_RAM_TAP_PAIR_ID0                           = 0x0,
++	SCL_C_RAM_TAP_PAIR_ID1                           = 0x1,
++	SCL_C_RAM_TAP_PAIR_ID2                           = 0x2,
++	SCL_C_RAM_TAP_PAIR_ID3                           = 0x3,
++	SCL_C_RAM_TAP_PAIR_ID4                           = 0x4,
++} SCL_C_RAM_TAP_PAIR_IDX;
++typedef enum SCL_C_RAM_PHASE {
++	SCL_C_RAM_PHASE_0                                = 0x0,
++	SCL_C_RAM_PHASE_1                                = 0x1,
++	SCL_C_RAM_PHASE_2                                = 0x2,
++	SCL_C_RAM_PHASE_3                                = 0x3,
++	SCL_C_RAM_PHASE_4                                = 0x4,
++	SCL_C_RAM_PHASE_5                                = 0x5,
++	SCL_C_RAM_PHASE_6                                = 0x6,
++	SCL_C_RAM_PHASE_7                                = 0x7,
++	SCL_C_RAM_PHASE_8                                = 0x8,
++} SCL_C_RAM_PHASE;
++typedef enum SCL_C_RAM_FILTER_TYPE {
++	SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT          = 0x0,
++	SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT            = 0x1,
++	SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT          = 0x2,
++	SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT            = 0x3,
++	SCL_C_RAM_FILTER_TYPE_VERT_ALPHA_LUT             = 0x4,
++	SCL_C_RAM_FILTER_TYPE_HORI_ALPHA_LUT             = 0x5,
++} SCL_C_RAM_FILTER_TYPE;
++typedef enum SCL_MODE_SEL {
++	SCL_MODE_SCL_BYPASS                              = 0x0,
++	SCL_MODE_RGB_SCALING                             = 0x1,
++	SCL_MODE_YCBCR_SCALING                           = 0x2,
++} SCL_MODE_SEL;
++typedef enum SCL_PSCL_EN {
++	SCL_PSCL_DISABLE                                 = 0x0,
++	SCL_PSCL_ENANBLE                                 = 0x1,
++} SCL_PSCL_EN;
++typedef enum SCL_V_NUM_OF_TAPS {
++	SCL_V_NUM_OF_TAPS_1                              = 0x0,
++	SCL_V_NUM_OF_TAPS_2                              = 0x1,
++	SCL_V_NUM_OF_TAPS_3                              = 0x2,
++	SCL_V_NUM_OF_TAPS_4                              = 0x3,
++	SCL_V_NUM_OF_TAPS_5                              = 0x4,
++	SCL_V_NUM_OF_TAPS_6                              = 0x5,
++} SCL_V_NUM_OF_TAPS;
++typedef enum SCL_H_NUM_OF_TAPS {
++	SCL_H_NUM_OF_TAPS_1                              = 0x0,
++	SCL_H_NUM_OF_TAPS_2                              = 0x1,
++	SCL_H_NUM_OF_TAPS_4                              = 0x3,
++	SCL_H_NUM_OF_TAPS_6                              = 0x5,
++	SCL_H_NUM_OF_TAPS_8                              = 0x7,
++	SCL_H_NUM_OF_TAPS_10                             = 0x9,
++} SCL_H_NUM_OF_TAPS;
++typedef enum SCL_BOUNDARY_MODE {
++	SCL_BOUNDARY_MODE_BLACK                          = 0x0,
++	SCL_BOUNDARY_MODE_EDGE                           = 0x1,
++} SCL_BOUNDARY_MODE;
++typedef enum SCL_EARLY_EOL_MOD {
++	SCL_EARLY_EOL_MODE_CRTC                          = 0x0,
++	SCL_EARLY_EOL_MODE_INTERNAL                      = 0x1,
++} SCL_EARLY_EOL_MOD;
++typedef enum SCL_BYPASS_MODE {
++	SCL_BYPASS_MODE_MC_MR                            = 0x0,
++	SCL_BYPASS_MODE_AC_NR                            = 0x1,
++	SCL_BYPASS_MODE_AC_AR                            = 0x2,
++	SCL_BYPASS_MODE_RESERVED                         = 0x3,
++} SCL_BYPASS_MODE;
++typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
++	SCL_V_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
++	SCL_V_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
++	SCL_V_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
++	SCL_V_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
++	SCL_V_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
++	SCL_V_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
++	SCL_V_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
++	SCL_V_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
++	SCL_V_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
++	SCL_V_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
++	SCL_V_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
++	SCL_V_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
++	SCL_V_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
++	SCL_V_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
++	SCL_V_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
++	SCL_V_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
++} SCL_V_MANUAL_REPLICATE_FACTOR;
++typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
++	SCL_H_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
++	SCL_H_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
++	SCL_H_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
++	SCL_H_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
++	SCL_H_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
++	SCL_H_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
++	SCL_H_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
++	SCL_H_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
++	SCL_H_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
++	SCL_H_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
++	SCL_H_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
++	SCL_H_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
++	SCL_H_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
++	SCL_H_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
++	SCL_H_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
++	SCL_H_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
++} SCL_H_MANUAL_REPLICATE_FACTOR;
++typedef enum SCL_V_CALC_AUTO_RATIO_EN {
++	SCL_V_CALC_AUTO_RATIO_DISABLE                    = 0x0,
++	SCL_V_CALC_AUTO_RATIO_ENABLE                     = 0x1,
++} SCL_V_CALC_AUTO_RATIO_EN;
++typedef enum SCL_H_CALC_AUTO_RATIO_EN {
++	SCL_H_CALC_AUTO_RATIO_DISABLE                    = 0x0,
++	SCL_H_CALC_AUTO_RATIO_ENABLE                     = 0x1,
++} SCL_H_CALC_AUTO_RATIO_EN;
++typedef enum SCL_H_FILTER_PICK_NEAREST {
++	SCL_H_FILTER_PICK_NEAREST_DISABLE                = 0x0,
++	SCL_H_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
++} SCL_H_FILTER_PICK_NEAREST;
++typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
++	SCL_H_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
++	SCL_H_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
++} SCL_H_2TAP_HARDCODE_COEF_EN;
++typedef enum SCL_V_FILTER_PICK_NEAREST {
++	SCL_V_FILTER_PICK_NEAREST_DISABLE                = 0x0,
++	SCL_V_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
++} SCL_V_FILTER_PICK_NEAREST;
++typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
++	SCL_V_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
++	SCL_V_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
++} SCL_V_2TAP_HARDCODE_COEF_EN;
++typedef enum SCL_UPDATE_TAKEN {
++	SCL_UPDATE_TAKEN_NO                              = 0x0,
++	SCL_UPDATE_TAKEN_YES                             = 0x1,
++} SCL_UPDATE_TAKEN;
++typedef enum SCL_UPDATE_LOCK {
++	SCL_UPDATE_UNLOCKED                              = 0x0,
++	SCL_UPDATE_LOCKED                                = 0x1,
++} SCL_UPDATE_LOCK;
++typedef enum SCL_COEF_UPDATE_COMPLETE {
++	SCL_COEF_UPDATE_NOT_COMPLETED                    = 0x0,
++	SCL_COEF_UPDATE_COMPLETED                        = 0x1,
++} SCL_COEF_UPDATE_COMPLETE;
++typedef enum SCL_HF_SHARP_SCALE_FACTOR {
++	SCL_HF_SHARP_SCALE_FACTOR_0                      = 0x0,
++	SCL_HF_SHARP_SCALE_FACTOR_1                      = 0x1,
++	SCL_HF_SHARP_SCALE_FACTOR_2                      = 0x2,
++	SCL_HF_SHARP_SCALE_FACTOR_3                      = 0x3,
++	SCL_HF_SHARP_SCALE_FACTOR_4                      = 0x4,
++	SCL_HF_SHARP_SCALE_FACTOR_5                      = 0x5,
++	SCL_HF_SHARP_SCALE_FACTOR_6                      = 0x6,
++	SCL_HF_SHARP_SCALE_FACTOR_7                      = 0x7,
++} SCL_HF_SHARP_SCALE_FACTOR;
++typedef enum SCL_HF_SHARP_EN {
++	SCL_HF_SHARP_DISABLE                             = 0x0,
++	SCL_HF_SHARP_ENABLE                              = 0x1,
++} SCL_HF_SHARP_EN;
++typedef enum SCL_VF_SHARP_SCALE_FACTOR {
++	SCL_VF_SHARP_SCALE_FACTOR_0                      = 0x0,
++	SCL_VF_SHARP_SCALE_FACTOR_1                      = 0x1,
++	SCL_VF_SHARP_SCALE_FACTOR_2                      = 0x2,
++	SCL_VF_SHARP_SCALE_FACTOR_3                      = 0x3,
++	SCL_VF_SHARP_SCALE_FACTOR_4                      = 0x4,
++	SCL_VF_SHARP_SCALE_FACTOR_5                      = 0x5,
++	SCL_VF_SHARP_SCALE_FACTOR_6                      = 0x6,
++	SCL_VF_SHARP_SCALE_FACTOR_7                      = 0x7,
++} SCL_VF_SHARP_SCALE_FACTOR;
++typedef enum SCL_VF_SHARP_EN {
++	SCL_VF_SHARP_DISABLE                             = 0x0,
++	SCL_VF_SHARP_ENABLE                              = 0x1,
++} SCL_VF_SHARP_EN;
++typedef enum SCL_ALU_DISABLE {
++	SCL_ALU_ENABLED                                  = 0x0,
++	SCL_ALU_DISABLED                                 = 0x1,
++} SCL_ALU_DISABLE;
++typedef enum SCL_HOST_CONFLICT_MASK {
++	SCL_HOST_CONFLICT_DISABLE_INTERRUPT              = 0x0,
++	SCL_HOST_CONFLICT_ENABLE_INTERRUPT               = 0x1,
++} SCL_HOST_CONFLICT_MASK;
++typedef enum SCL_SCL_MODE_CHANGE_MASK {
++	SCL_MODE_CHANGE_DISABLE_INTERRUPT                = 0x0,
++	SCL_MODE_CHANGE_ENABLE_INTERRUPT                 = 0x1,
++} SCL_SCL_MODE_CHANGE_MASK;
++typedef enum SCLV_INTERLACE_SOURCE {
++	INTERLACE_SOURCE_PROGRESSIVE                     = 0x0,
++	INTERLACE_SOURCE_INTERLEAVE                      = 0x1,
++	INTERLACE_SOURCE_STACK                           = 0x2,
++} SCLV_INTERLACE_SOURCE;
++typedef enum SCLV_UPDATE_LOCK {
++	UPDATE_UNLOCKED                                  = 0x0,
++	UPDATE_LOCKED                                    = 0x1,
++} SCLV_UPDATE_LOCK;
++typedef enum SCLV_COEF_UPDATE_COMPLETE {
++	COEF_UPDATE_NOT_COMPLETE                         = 0x0,
++	COEF_UPDATE_COMPLETE                             = 0x1,
++} SCLV_COEF_UPDATE_COMPLETE;
++typedef enum COL_MAN_UPDATE_LOCK {
++	COL_MAN_UPDATE_UNLOCKED                          = 0x0,
++	COL_MAN_UPDATE_LOCKED                            = 0x1,
++} COL_MAN_UPDATE_LOCK;
++typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
++	COL_MAN_MULTIPLE_UPDATE                          = 0x0,
++	COL_MAN_MULTIPLE_UPDAT_EDISABLE                  = 0x1,
++} COL_MAN_DISABLE_MULTIPLE_UPDATE;
++typedef enum COL_MAN_INPUTCSC_MODE {
++	INPUTCSC_MODE_BYPASS                             = 0x0,
++	INPUTCSC_MODE_A                                  = 0x1,
++	INPUTCSC_MODE_B                                  = 0x2,
++	INPUTCSC_MODE_UNITY                              = 0x3,
++} COL_MAN_INPUTCSC_MODE;
++typedef enum COL_MAN_INPUTCSC_TYPE {
++	INPUTCSC_TYPE_12_0                               = 0x0,
++	INPUTCSC_TYPE_10_2                               = 0x1,
++	INPUTCSC_TYPE_8_4                                = 0x2,
++} COL_MAN_INPUTCSC_TYPE;
++typedef enum COL_MAN_INPUTCSC_CONVERT {
++	INPUTCSC_ROUND                                   = 0x0,
++	INPUTCSC_TRUNCATE                                = 0x1,
++} COL_MAN_INPUTCSC_CONVERT;
++typedef enum COL_MAN_PRESCALE_MODE {
++	PRESCALE_MODE_BYPASS                             = 0x0,
++	PRESCALE_MODE_PROGRAM                            = 0x1,
++	PRESCALE_MODE_UNITY                              = 0x2,
++} COL_MAN_PRESCALE_MODE;
++typedef enum COL_MAN_INPUT_GAMMA_MODE {
++	INGAMMA_MODE_BYPASS                              = 0x0,
++	INGAMMA_MODE_FIX                                 = 0x1,
++	INGAMMA_MODE_FLOAT                               = 0x2,
++} COL_MAN_INPUT_GAMMA_MODE;
++typedef enum COL_MAN_OUTPUT_CSC_MODE {
++	COL_MAN_OUTPUT_CSC_BYPASS                        = 0x0,
++	COL_MAN_OUTPUT_CSC_RGB                           = 0x1,
++	COL_MAN_OUTPUT_CSC_YCrCb601                      = 0x2,
++	COL_MAN_OUTPUT_CSC_YCrCb709                      = 0x3,
++	COL_MAN_OUTPUT_CSC_A                             = 0x4,
++	COL_MAN_OUTPUT_CSC_B                             = 0x5,
++	COL_MAN_OUTPUT_CSC_UNITY                         = 0x6,
++} COL_MAN_OUTPUT_CSC_MODE;
++typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
++	DENORM_CLAMP_MODE_UNITY                          = 0x0,
++	DENORM_CLAMP_MODE_8                              = 0x1,
++	DENORM_CLAMP_MODE_10                             = 0x2,
++	DENORM_CLAMP_MODE_12                             = 0x3,
++} COL_MAN_DENORM_CLAMP_CONTROL;
++typedef enum COL_MAN_GAMMA_CORR_CONTROL {
++	GAMMA_CORR_MODE_BYPASS                           = 0x0,
++	GAMMA_CORR_MODE_A                                = 0x1,
++	GAMMA_CORR_MODE_B                                = 0x2,
++} COL_MAN_GAMMA_CORR_CONTROL;
++typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
++	CM_GLOBAL_PASSTHROUGH_DISBALE                    = 0x0,
++	CM_GLOBAL_PASSTHROUGH_ENABLE                     = 0x1,
++} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
++typedef enum UNP_GRPH_EN {
++	UNP_GRPH_DISABLED                                = 0x0,
++	UNP_GRPH_ENABLED                                 = 0x1,
++} UNP_GRPH_EN;
++typedef enum UNP_GRPH_DEPTH {
++	UNP_GRPH_8BPP                                    = 0x0,
++	UNP_GRPH_16BPP                                   = 0x1,
++	UNP_GRPH_32BPP                                   = 0x2,
++} UNP_GRPH_DEPTH;
++typedef enum UNP_GRPH_NUM_BANKS {
++	UNP_GRPH_ADDR_SURF_2_BANK                        = 0x0,
++	UNP_GRPH_ADDR_SURF_4_BANK                        = 0x1,
++	UNP_GRPH_ADDR_SURF_8_BANK                        = 0x2,
++	UNP_GRPH_ADDR_SURF_16_BANK                       = 0x3,
++} UNP_GRPH_NUM_BANKS;
++typedef enum UNP_GRPH_BANK_WIDTH {
++	UNP_GRPH_ADDR_SURF_BANK_WIDTH_1                  = 0x0,
++	UNP_GRPH_ADDR_SURF_BANK_WIDTH_2                  = 0x1,
++	UNP_GRPH_ADDR_SURF_BANK_WIDTH_4                  = 0x2,
++	UNP_GRPH_ADDR_SURF_BANK_WIDTH_8                  = 0x3,
++} UNP_GRPH_BANK_WIDTH;
++typedef enum UNP_GRPH_BANK_HEIGHT {
++	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1                 = 0x0,
++	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2                 = 0x1,
++	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4                 = 0x2,
++	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8                 = 0x3,
++} UNP_GRPH_BANK_HEIGHT;
++typedef enum UNP_GRPH_TILE_SPLIT {
++	UNP_ADDR_SURF_TILE_SPLIT_64B                     = 0x0,
++	UNP_ADDR_SURF_TILE_SPLIT_128B                    = 0x1,
++	UNP_ADDR_SURF_TILE_SPLIT_256B                    = 0x2,
++	UNP_ADDR_SURF_TILE_SPLIT_512B                    = 0x3,
++	UNP_ADDR_SURF_TILE_SPLIT_1KB                     = 0x4,
++	UNP_ADDR_SURF_TILE_SPLIT_2KB                     = 0x5,
++	UNP_ADDR_SURF_TILE_SPLIT_4KB                     = 0x6,
++} UNP_GRPH_TILE_SPLIT;
++typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
++	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0             = 0x0,
++	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1             = 0x1,
++} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
++typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
++	UNP_GRPH_PRIVILEGED_ACCESS_DIS                   = 0x0,
++	UNP_GRPH_PRIVILEGED_ACCESS_EN                    = 0x1,
++} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
++typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
++	UNP_ADDR_SURF_MACRO_ASPECT_1                     = 0x0,
++	UNP_ADDR_SURF_MACRO_ASPECT_2                     = 0x1,
++	UNP_ADDR_SURF_MACRO_ASPECT_4                     = 0x2,
++	UNP_ADDR_SURF_MACRO_ASPECT_8                     = 0x3,
++} UNP_GRPH_MACRO_TILE_ASPECT;
++typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
++	UNP_GRPH_DYNAMIC_EXPANSION                       = 0x0,
++	UNP_GRPH_ZERO_EXPANSION                          = 0x1,
++} UNP_GRPH_COLOR_EXPANSION_MODE;
++typedef enum UNP_VIDEO_FORMAT {
++	UNP_VIDEO_FORMAT0                                = 0x0,
++	UNP_VIDEO_FORMAT1                                = 0x1,
++	UNP_VIDEO_FORMAT_YUV420_YCbCr                    = 0x2,
++	UNP_VIDEO_FORMAT_YUV420_YCrCb                    = 0x3,
++	UNP_VIDEO_FORMAT_YUV422_YCb                      = 0x4,
++	UNP_VIDEO_FORMAT_YUV422_YCr                      = 0x5,
++	UNP_VIDEO_FORMAT_YUV422_CbY                      = 0x6,
++	UNP_VIDEO_FORMAT_YUV422_CrY                      = 0x7,
++} UNP_VIDEO_FORMAT;
++typedef enum UNP_GRPH_ENDIAN_SWAP {
++	UNP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
++	UNP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
++	UNP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
++	UNP_GRPH_ENDIAN_SWAP_8IN43                       = 0x3,
++} UNP_GRPH_ENDIAN_SWAP;
++typedef enum UNP_GRPH_RED_CROSSBAR {
++	UNP_GRPH_RED_CROSSBAR_R_Cr                       = 0x0,
++	UNP_GRPH_RED_CROSSBAR_G_Y                        = 0x1,
++	UNP_GRPH_RED_CROSSBAR_B_Cb                       = 0x2,
++	UNP_GRPH_RED_CROSSBAR_A                          = 0x3,
++} UNP_GRPH_RED_CROSSBAR;
++typedef enum UNP_GRPH_GREEN_CROSSBAR {
++	UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y             = 0x0,
++	UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C           = 0x1,
++	UNP_UNP_GRPH_GREEN_CROSSBAR_A                    = 0x2,
++	UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr                 = 0x3,
++} UNP_GRPH_GREEN_CROSSBAR;
++typedef enum UNP_GRPH_BLUE_CROSSBAR {
++	UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C                = 0x0,
++	UNP_GRPH_BLUE_CROSSBAR_A                         = 0x1,
++	UNP_GRPH_BLUE_CROSSBAR_R_Cr                      = 0x2,
++	UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y                  = 0x3,
++} UNP_GRPH_BLUE_CROSSBAR;
++typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
++	UNP_GRPH_UPDATE_LOCK_0                           = 0x0,
++	UNP_GRPH_UPDATE_LOCK_1                           = 0x1,
++} UNP_GRPH_MODE_UPDATE_LOCKG;
++typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
++	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0            = 0x0,
++	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1            = 0x1,
++} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
++typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
++	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0          = 0x0,
++	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1          = 0x1,
++} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
++typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
++	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0       = 0x0,
++	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1       = 0x1,
++} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
++typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
++	UNP_GRPH_STEREOSYNC_FLIP_DISABLE                 = 0x0,
++	UNP_GRPH_STEREOSYNC_FLIP_ENABLE                  = 0x1,
++} UNP_GRPH_STEREOSYNC_FLIP_EN;
++typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
++	UNP_GRPH_STEREOSYNC_FLIP_MODE_0                  = 0x0,
++	UNP_GRPH_STEREOSYNC_FLIP_MODE_1                  = 0x1,
++	UNP_GRPH_STEREOSYNC_FLIP_MODE_2                  = 0x2,
++	UNP_GRPH_STEREOSYNC_FLIP_MODE_3                  = 0x3,
++} UNP_GRPH_STEREOSYNC_FLIP_MODE;
++typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
++	UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE            = 0x0,
++	UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE             = 0x1,
++} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
++typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
++	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0             = 0x0,
++	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1             = 0x1,
++	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2             = 0x2,
++	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3             = 0x3,
++} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
++typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
++	UNP_GRPH_STEREOSYNC_SELECT_EN                    = 0x0,
++	UNP_GRPH_STEREOSYNC_SELECT_DIS                   = 0x1,
++} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
++typedef enum UNP_CRC_SOURCE_SEL {
++	UNP_CRC_SOURCE_SEL_NP_TO_LBV                     = 0x0,
++	UNP_CRC_SOURCE_SEL_LOWER32                       = 0x1,
++	UNP_CRC_SOURCE_SEL_RESERVED                      = 0x2,
++	UNP_CRC_SOURCE_SEL_LOWER16                       = 0x3,
++	UNP_CRC_SOURCE_SEL_UNP_TO_LBV                    = 0x4,
++} UNP_CRC_SOURCE_SEL;
++typedef enum UNP_CRC_LINE_SEL {
++	UNP_CRC_LINE_SEL_RESERVED                        = 0x0,
++	UNP_CRC_LINE_SEL_EVEN_ONLY                       = 0x1,
++	UNP_CRC_LINE_SEL_ODD_ONLY                        = 0x2,
++	UNP_CRC_LINE_SEL_ODD_EVEN                        = 0x3,
++} UNP_CRC_LINE_SEL;
++typedef enum UNP_ROTATION_ANGLE {
++	UNP_ROTATION_ANGLE_0                             = 0x0,
++	UNP_ROTATION_ANGLE_90                            = 0x1,
++	UNP_ROTATION_ANGLE_180                           = 0x2,
++	UNP_ROTATION_ANGLE_270                           = 0x3,
++	UNP_ROTATION_ANGLE_0m                            = 0x4,
++	UNP_ROTATION_ANGLE_90m                           = 0x5,
++	UNP_ROTATION_ANGLE_180m                          = 0x6,
++	UNP_ROTATION_ANGLE_270m                          = 0x7,
++} UNP_ROTATION_ANGLE;
++typedef enum UNP_PIXEL_DROP {
++	UNP_PIXEL_NO_DROP                                = 0x0,
++	UNP_PIXEL_DROPPING                               = 0x1,
++} UNP_PIXEL_DROP;
++typedef enum UNP_BUFFER_MODE {
++	UNP_BUFFER_MODE_LUMA                             = 0x0,
++	UNP_BUFFER_MODE_LUMA_CHROMA                      = 0x1,
++} UNP_BUFFER_MODE;
++typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
++	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
++	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
++} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
++typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
++	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
++} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
++typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
++	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
++} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
++	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE           = 0x0,
++	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE            = 0x1,
++} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
++	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x0,
++	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED   = 0x1,
++} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
++	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET    = 0x0,
++	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET        = 0x1,
++} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
++	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
++	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
++} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
++typedef enum AZ_GLOBAL_CAPABILITIES {
++	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
++	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
++} AZ_GLOBAL_CAPABILITIES;
++typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
++	ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE           = 0x0,
++	ACCEPT_UNSOLICITED_RESPONSE_ENABLE               = 0x1,
++} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
++typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
++	FLUSH_CONTROL_FLUSH_NOT_STARTED                  = 0x0,
++	FLUSH_CONTROL_FLUSH_STARTED                      = 0x1,
++} GLOBAL_CONTROL_FLUSH_CONTROL;
++typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
++	CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET          = 0x0,
++	CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET      = 0x1,
++} GLOBAL_CONTROL_CONTROLLER_RESET;
++typedef enum AZ_STATE_CHANGE_STATUS {
++	AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT         = 0x0,
++	AZ_STATE_CHANGE_STATUS_CODEC_PRESENT             = 0x1,
++} AZ_STATE_CHANGE_STATUS;
++typedef enum GLOBAL_STATUS_FLUSH_STATUS {
++	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED       = 0x0,
++	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED           = 0x1,
++} GLOBAL_STATUS_FLUSH_STATUS;
++typedef enum STREAM_0_SYNCHRONIZATION {
++	STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
++	STREAM_0_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
++} STREAM_0_SYNCHRONIZATION;
++typedef enum STREAM_1_SYNCHRONIZATION {
++	STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
++	STREAM_1_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
++} STREAM_1_SYNCHRONIZATION;
++typedef enum STREAM_2_SYNCHRONIZATION {
++	STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
++	STREAM_2_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
++} STREAM_2_SYNCHRONIZATION;
++typedef enum STREAM_3_SYNCHRONIZATION {
++	STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_3_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_3_SYNCHRONIZATION;
++typedef enum STREAM_4_SYNCHRONIZATION {
++	STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_4_SYNCHRONIZATION;
++typedef enum STREAM_5_SYNCHRONIZATION {
++	STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_5_SYNCHRONIZATION;
++typedef enum STREAM_6_SYNCHRONIZATION {
++	STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_6_SYNCHRONIZATION;
++typedef enum STREAM_7_SYNCHRONIZATION {
++	STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_7_SYNCHRONIZATION;
++typedef enum STREAM_8_SYNCHRONIZATION {
++	STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_8_SYNCHRONIZATION;
++typedef enum STREAM_9_SYNCHRONIZATION {
++	STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
++} STREAM_9_SYNCHRONIZATION;
++typedef enum STREAM_10_SYNCHRONIZATION {
++	STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
++} STREAM_10_SYNCHRONIZATION;
++typedef enum STREAM_11_SYNCHRONIZATION {
++	STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
++} STREAM_11_SYNCHRONIZATION;
++typedef enum STREAM_12_SYNCHRONIZATION {
++	STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
++} STREAM_12_SYNCHRONIZATION;
++typedef enum STREAM_13_SYNCHRONIZATION {
++	STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
++} STREAM_13_SYNCHRONIZATION;
++typedef enum STREAM_14_SYNCHRONIZATION {
++	STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
++} STREAM_14_SYNCHRONIZATION;
++typedef enum STREAM_15_SYNCHRONIZATION {
++	STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
++	STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
++} STREAM_15_SYNCHRONIZATION;
++typedef enum CORB_READ_POINTER_RESET {
++	CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET    = 0x0,
++	CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET        = 0x1,
++} CORB_READ_POINTER_RESET;
++typedef enum AZ_CORB_SIZE {
++	AZ_CORB_SIZE_2ENTRIES_RESERVED                   = 0x0,
++	AZ_CORB_SIZE_16ENTRIES_RESERVED                  = 0x1,
++	AZ_CORB_SIZE_256ENTRIES                          = 0x2,
++	AZ_CORB_SIZE_RESERVED                            = 0x3,
++} AZ_CORB_SIZE;
++typedef enum AZ_RIRB_WRITE_POINTER_RESET {
++	AZ_RIRB_WRITE_POINTER_NOT_RESET                  = 0x0,
++	AZ_RIRB_WRITE_POINTER_DO_RESET                   = 0x1,
++} AZ_RIRB_WRITE_POINTER_RESET;
++typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
++	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
++	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
++} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
++typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
++	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
++	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
++} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
++typedef enum AZ_RIRB_SIZE {
++	AZ_RIRB_SIZE_2ENTRIES_RESERVED                   = 0x0,
++	AZ_RIRB_SIZE_16ENTRIES_RESERVED                  = 0x1,
++	AZ_RIRB_SIZE_256ENTRIES                          = 0x2,
++	AZ_RIRB_SIZE_UNDEFINED                           = 0x3,
++} AZ_RIRB_SIZE;
++typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
++	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
++	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
++} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
++typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
++	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
++	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
++} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
++typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
++	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
++	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
++} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
++	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
++	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
++	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
++	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
++	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN   = 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
++	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
++typedef enum AZ_LATENCY_COUNTER_CONTROL {
++	AZ_LATENCY_COUNTER_NO_RESET                      = 0x0,
++	AZ_LATENCY_COUNTER_RESET_DONE                    = 0x1,
++} AZ_LATENCY_COUNTER_CONTROL;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
++	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
++typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
++	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
++	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
++} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
++typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
++	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
++	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
++} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
++	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
++typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
++	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
++	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
++} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
++	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
++	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
++typedef enum BLND_CONTROL_BLND_MODE {
++	BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY         = 0x0,
++	BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY           = 0x1,
++	BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE       = 0x2,
++	BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE         = 0x3,
++} BLND_CONTROL_BLND_MODE;
++typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
++	BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
++	BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
++	BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
++	BLND_CONTROL_BLND_STEREO_TYPE_UNUSED             = 0x3,
++} BLND_CONTROL_BLND_STEREO_TYPE;
++typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
++	BLND_CONTROL_BLND_STEREO_POLARITY_LOW            = 0x0,
++	BLND_CONTROL_BLND_STEREO_POLARITY_HIGH           = 0x1,
++} BLND_CONTROL_BLND_STEREO_POLARITY;
++typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
++	BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE           = 0x0,
++	BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE            = 0x1,
++} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
++typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
++	BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
++	BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
++	BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY   = 0x2,
++	BLND_CONTROL_BLND_ALPHA_MODE_UNUSED              = 0x3,
++} BLND_CONTROL_BLND_ALPHA_MODE;
++typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
++	BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE          = 0x0,
++	BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE           = 0x1,
++} BLND_CONTROL_BLND_MULTIPLIED_MODE;
++typedef enum BLND_SM_CONTROL2_SM_MODE {
++	BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE            = 0x0,
++	BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING         = 0x2,
++	BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING      = 0x4,
++	BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
++} BLND_SM_CONTROL2_SM_MODE;
++typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
++	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE        = 0x0,
++	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE         = 0x1,
++} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
++typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
++	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE        = 0x0,
++	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE         = 0x1,
++} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
++typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
++} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
++typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE  = 0x0,
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED  = 0x1,
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
++	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
++} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
++typedef enum BLND_CONTROL2_PTI_ENABLE {
++	BLND_CONTROL2_PTI_ENABLE_FALSE                   = 0x0,
++	BLND_CONTROL2_PTI_ENABLE_TRUE                    = 0x1,
++} BLND_CONTROL2_PTI_ENABLE;
++typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
++	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE      = 0x0,
++	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE       = 0x1,
++} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
++typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
++	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE      = 0x0,
++	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE       = 0x1,
++} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
++typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
++	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
++	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
++} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
++typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
++	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
++	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
++} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
++	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
++	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
++} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
++	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
++	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
++} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
++	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
++	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
++} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
++	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
++	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
++} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
++	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE  = 0x0,
++	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE   = 0x1,
++} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
++	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
++	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE  = 0x1,
++} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
++typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
++	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
++	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE  = 0x1,
++} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
++typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
++	BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW               = 0x0,
++	BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH              = 0x1,
++} BLND_DEBUG_BLND_CNV_MUX_SELECT;
++typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
++	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
++	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
++} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
++typedef enum DebugBlockId {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_UVDU                                = 0xd,
++	DBG_BLOCK_ID_SQA                                 = 0xe,
++	DBG_BLOCK_ID_SDMA0                               = 0xf,
++	DBG_BLOCK_ID_SDMA1                               = 0x10,
++	DBG_BLOCK_ID_SPIM                                = 0x11,
++	DBG_BLOCK_ID_GDS                                 = 0x12,
++	DBG_BLOCK_ID_VC0                                 = 0x13,
++	DBG_BLOCK_ID_VC1                                 = 0x14,
++	DBG_BLOCK_ID_PA0                                 = 0x15,
++	DBG_BLOCK_ID_PA1                                 = 0x16,
++	DBG_BLOCK_ID_CP0                                 = 0x17,
++	DBG_BLOCK_ID_CP1                                 = 0x18,
++	DBG_BLOCK_ID_CP2                                 = 0x19,
++	DBG_BLOCK_ID_XBR                                 = 0x1a,
++	DBG_BLOCK_ID_UVDM                                = 0x1b,
++	DBG_BLOCK_ID_VGT0                                = 0x1c,
++	DBG_BLOCK_ID_VGT1                                = 0x1d,
++	DBG_BLOCK_ID_IA                                  = 0x1e,
++	DBG_BLOCK_ID_SXM0                                = 0x1f,
++	DBG_BLOCK_ID_SXM1                                = 0x20,
++	DBG_BLOCK_ID_SCT0                                = 0x21,
++	DBG_BLOCK_ID_SCT1                                = 0x22,
++	DBG_BLOCK_ID_SPM0                                = 0x23,
++	DBG_BLOCK_ID_SPM1                                = 0x24,
++	DBG_BLOCK_ID_UNUSED0                             = 0x25,
++	DBG_BLOCK_ID_UNUSED1                             = 0x26,
++	DBG_BLOCK_ID_TCAA                                = 0x27,
++	DBG_BLOCK_ID_TCAB                                = 0x28,
++	DBG_BLOCK_ID_TCCA                                = 0x29,
++	DBG_BLOCK_ID_TCCB                                = 0x2a,
++	DBG_BLOCK_ID_MCC0                                = 0x2b,
++	DBG_BLOCK_ID_MCC1                                = 0x2c,
++	DBG_BLOCK_ID_MCC2                                = 0x2d,
++	DBG_BLOCK_ID_MCC3                                = 0x2e,
++	DBG_BLOCK_ID_SXS0                                = 0x2f,
++	DBG_BLOCK_ID_SXS1                                = 0x30,
++	DBG_BLOCK_ID_SXS2                                = 0x31,
++	DBG_BLOCK_ID_SXS3                                = 0x32,
++	DBG_BLOCK_ID_SXS4                                = 0x33,
++	DBG_BLOCK_ID_SXS5                                = 0x34,
++	DBG_BLOCK_ID_SXS6                                = 0x35,
++	DBG_BLOCK_ID_SXS7                                = 0x36,
++	DBG_BLOCK_ID_SXS8                                = 0x37,
++	DBG_BLOCK_ID_SXS9                                = 0x38,
++	DBG_BLOCK_ID_BCI0                                = 0x39,
++	DBG_BLOCK_ID_BCI1                                = 0x3a,
++	DBG_BLOCK_ID_BCI2                                = 0x3b,
++	DBG_BLOCK_ID_BCI3                                = 0x3c,
++	DBG_BLOCK_ID_MCB                                 = 0x3d,
++	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
++	DBG_BLOCK_ID_SQA00                               = 0x3f,
++	DBG_BLOCK_ID_SQA01                               = 0x40,
++	DBG_BLOCK_ID_SQA02                               = 0x41,
++	DBG_BLOCK_ID_SQA10                               = 0x42,
++	DBG_BLOCK_ID_SQA11                               = 0x43,
++	DBG_BLOCK_ID_SQA12                               = 0x44,
++	DBG_BLOCK_ID_UNUSED7                             = 0x45,
++	DBG_BLOCK_ID_UNUSED8                             = 0x46,
++	DBG_BLOCK_ID_SQB00                               = 0x47,
++	DBG_BLOCK_ID_SQB01                               = 0x48,
++	DBG_BLOCK_ID_SQB10                               = 0x49,
++	DBG_BLOCK_ID_SQB11                               = 0x4a,
++	DBG_BLOCK_ID_SQ00                                = 0x4b,
++	DBG_BLOCK_ID_SQ01                                = 0x4c,
++	DBG_BLOCK_ID_SQ10                                = 0x4d,
++	DBG_BLOCK_ID_SQ11                                = 0x4e,
++	DBG_BLOCK_ID_CB00                                = 0x4f,
++	DBG_BLOCK_ID_CB01                                = 0x50,
++	DBG_BLOCK_ID_CB02                                = 0x51,
++	DBG_BLOCK_ID_CB03                                = 0x52,
++	DBG_BLOCK_ID_CB04                                = 0x53,
++	DBG_BLOCK_ID_UNUSED9                             = 0x54,
++	DBG_BLOCK_ID_UNUSED10                            = 0x55,
++	DBG_BLOCK_ID_UNUSED11                            = 0x56,
++	DBG_BLOCK_ID_CB10                                = 0x57,
++	DBG_BLOCK_ID_CB11                                = 0x58,
++	DBG_BLOCK_ID_CB12                                = 0x59,
++	DBG_BLOCK_ID_CB13                                = 0x5a,
++	DBG_BLOCK_ID_CB14                                = 0x5b,
++	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
++	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
++	DBG_BLOCK_ID_TCP0                                = 0x5f,
++	DBG_BLOCK_ID_TCP1                                = 0x60,
++	DBG_BLOCK_ID_TCP2                                = 0x61,
++	DBG_BLOCK_ID_TCP3                                = 0x62,
++	DBG_BLOCK_ID_TCP4                                = 0x63,
++	DBG_BLOCK_ID_TCP5                                = 0x64,
++	DBG_BLOCK_ID_TCP6                                = 0x65,
++	DBG_BLOCK_ID_TCP7                                = 0x66,
++	DBG_BLOCK_ID_TCP8                                = 0x67,
++	DBG_BLOCK_ID_TCP9                                = 0x68,
++	DBG_BLOCK_ID_TCP10                               = 0x69,
++	DBG_BLOCK_ID_TCP11                               = 0x6a,
++	DBG_BLOCK_ID_TCP12                               = 0x6b,
++	DBG_BLOCK_ID_TCP13                               = 0x6c,
++	DBG_BLOCK_ID_TCP14                               = 0x6d,
++	DBG_BLOCK_ID_TCP15                               = 0x6e,
++	DBG_BLOCK_ID_TCP16                               = 0x6f,
++	DBG_BLOCK_ID_TCP17                               = 0x70,
++	DBG_BLOCK_ID_TCP18                               = 0x71,
++	DBG_BLOCK_ID_TCP19                               = 0x72,
++	DBG_BLOCK_ID_TCP20                               = 0x73,
++	DBG_BLOCK_ID_TCP21                               = 0x74,
++	DBG_BLOCK_ID_TCP22                               = 0x75,
++	DBG_BLOCK_ID_TCP23                               = 0x76,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
++	DBG_BLOCK_ID_DB00                                = 0x7f,
++	DBG_BLOCK_ID_DB01                                = 0x80,
++	DBG_BLOCK_ID_DB02                                = 0x81,
++	DBG_BLOCK_ID_DB03                                = 0x82,
++	DBG_BLOCK_ID_DB04                                = 0x83,
++	DBG_BLOCK_ID_UNUSED15                            = 0x84,
++	DBG_BLOCK_ID_UNUSED16                            = 0x85,
++	DBG_BLOCK_ID_UNUSED17                            = 0x86,
++	DBG_BLOCK_ID_DB10                                = 0x87,
++	DBG_BLOCK_ID_DB11                                = 0x88,
++	DBG_BLOCK_ID_DB12                                = 0x89,
++	DBG_BLOCK_ID_DB13                                = 0x8a,
++	DBG_BLOCK_ID_DB14                                = 0x8b,
++	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
++	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
++	DBG_BLOCK_ID_TCC0                                = 0x8f,
++	DBG_BLOCK_ID_TCC1                                = 0x90,
++	DBG_BLOCK_ID_TCC2                                = 0x91,
++	DBG_BLOCK_ID_TCC3                                = 0x92,
++	DBG_BLOCK_ID_TCC4                                = 0x93,
++	DBG_BLOCK_ID_TCC5                                = 0x94,
++	DBG_BLOCK_ID_TCC6                                = 0x95,
++	DBG_BLOCK_ID_TCC7                                = 0x96,
++	DBG_BLOCK_ID_SPS00                               = 0x97,
++	DBG_BLOCK_ID_SPS01                               = 0x98,
++	DBG_BLOCK_ID_SPS02                               = 0x99,
++	DBG_BLOCK_ID_SPS10                               = 0x9a,
++	DBG_BLOCK_ID_SPS11                               = 0x9b,
++	DBG_BLOCK_ID_SPS12                               = 0x9c,
++	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
++	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
++	DBG_BLOCK_ID_TA00                                = 0x9f,
++	DBG_BLOCK_ID_TA01                                = 0xa0,
++	DBG_BLOCK_ID_TA02                                = 0xa1,
++	DBG_BLOCK_ID_TA03                                = 0xa2,
++	DBG_BLOCK_ID_TA04                                = 0xa3,
++	DBG_BLOCK_ID_TA05                                = 0xa4,
++	DBG_BLOCK_ID_TA06                                = 0xa5,
++	DBG_BLOCK_ID_TA07                                = 0xa6,
++	DBG_BLOCK_ID_TA08                                = 0xa7,
++	DBG_BLOCK_ID_TA09                                = 0xa8,
++	DBG_BLOCK_ID_TA0A                                = 0xa9,
++	DBG_BLOCK_ID_TA0B                                = 0xaa,
++	DBG_BLOCK_ID_UNUSED23                            = 0xab,
++	DBG_BLOCK_ID_UNUSED24                            = 0xac,
++	DBG_BLOCK_ID_UNUSED25                            = 0xad,
++	DBG_BLOCK_ID_UNUSED26                            = 0xae,
++	DBG_BLOCK_ID_TA10                                = 0xaf,
++	DBG_BLOCK_ID_TA11                                = 0xb0,
++	DBG_BLOCK_ID_TA12                                = 0xb1,
++	DBG_BLOCK_ID_TA13                                = 0xb2,
++	DBG_BLOCK_ID_TA14                                = 0xb3,
++	DBG_BLOCK_ID_TA15                                = 0xb4,
++	DBG_BLOCK_ID_TA16                                = 0xb5,
++	DBG_BLOCK_ID_TA17                                = 0xb6,
++	DBG_BLOCK_ID_TA18                                = 0xb7,
++	DBG_BLOCK_ID_TA19                                = 0xb8,
++	DBG_BLOCK_ID_TA1A                                = 0xb9,
++	DBG_BLOCK_ID_TA1B                                = 0xba,
++	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
++	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
++	DBG_BLOCK_ID_TD00                                = 0xbf,
++	DBG_BLOCK_ID_TD01                                = 0xc0,
++	DBG_BLOCK_ID_TD02                                = 0xc1,
++	DBG_BLOCK_ID_TD03                                = 0xc2,
++	DBG_BLOCK_ID_TD04                                = 0xc3,
++	DBG_BLOCK_ID_TD05                                = 0xc4,
++	DBG_BLOCK_ID_TD06                                = 0xc5,
++	DBG_BLOCK_ID_TD07                                = 0xc6,
++	DBG_BLOCK_ID_TD08                                = 0xc7,
++	DBG_BLOCK_ID_TD09                                = 0xc8,
++	DBG_BLOCK_ID_TD0A                                = 0xc9,
++	DBG_BLOCK_ID_TD0B                                = 0xca,
++	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
++	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED34                            = 0xce,
++	DBG_BLOCK_ID_TD10                                = 0xcf,
++	DBG_BLOCK_ID_TD11                                = 0xd0,
++	DBG_BLOCK_ID_TD12                                = 0xd1,
++	DBG_BLOCK_ID_TD13                                = 0xd2,
++	DBG_BLOCK_ID_TD14                                = 0xd3,
++	DBG_BLOCK_ID_TD15                                = 0xd4,
++	DBG_BLOCK_ID_TD16                                = 0xd5,
++	DBG_BLOCK_ID_TD17                                = 0xd6,
++	DBG_BLOCK_ID_TD18                                = 0xd7,
++	DBG_BLOCK_ID_TD19                                = 0xd8,
++	DBG_BLOCK_ID_TD1A                                = 0xd9,
++	DBG_BLOCK_ID_TD1B                                = 0xda,
++	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
++	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED38                            = 0xde,
++	DBG_BLOCK_ID_LDS00                               = 0xdf,
++	DBG_BLOCK_ID_LDS01                               = 0xe0,
++	DBG_BLOCK_ID_LDS02                               = 0xe1,
++	DBG_BLOCK_ID_LDS03                               = 0xe2,
++	DBG_BLOCK_ID_LDS04                               = 0xe3,
++	DBG_BLOCK_ID_LDS05                               = 0xe4,
++	DBG_BLOCK_ID_LDS06                               = 0xe5,
++	DBG_BLOCK_ID_LDS07                               = 0xe6,
++	DBG_BLOCK_ID_LDS08                               = 0xe7,
++	DBG_BLOCK_ID_LDS09                               = 0xe8,
++	DBG_BLOCK_ID_LDS0A                               = 0xe9,
++	DBG_BLOCK_ID_LDS0B                               = 0xea,
++	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
++	DBG_BLOCK_ID_UNUSED40                            = 0xec,
++	DBG_BLOCK_ID_UNUSED41                            = 0xed,
++	DBG_BLOCK_ID_UNUSED42                            = 0xee,
++	DBG_BLOCK_ID_LDS10                               = 0xef,
++	DBG_BLOCK_ID_LDS11                               = 0xf0,
++	DBG_BLOCK_ID_LDS12                               = 0xf1,
++	DBG_BLOCK_ID_LDS13                               = 0xf2,
++	DBG_BLOCK_ID_LDS14                               = 0xf3,
++	DBG_BLOCK_ID_LDS15                               = 0xf4,
++	DBG_BLOCK_ID_LDS16                               = 0xf5,
++	DBG_BLOCK_ID_LDS17                               = 0xf6,
++	DBG_BLOCK_ID_LDS18                               = 0xf7,
++	DBG_BLOCK_ID_LDS19                               = 0xf8,
++	DBG_BLOCK_ID_LDS1A                               = 0xf9,
++	DBG_BLOCK_ID_LDS1B                               = 0xfa,
++	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
++	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
++	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
++	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
++} DebugBlockId;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
++	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
++	DBG_BLOCK_ID_PA_BY2                              = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
++	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
++	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
++	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
++	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
++	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
++	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
++	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
++	DBG_BLOCK_ID_CB_BY2                              = 0x24,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
++	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
++	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
++	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
++	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
++	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
++	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
++	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
++	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
++	DBG_BLOCK_ID_TA_BY2                              = 0x48,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
++	DBG_BLOCK_ID_TD_BY2                              = 0x58,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
++	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
++	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
++	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
++	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
++	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
++	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
++	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
++	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
++	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
++	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
++	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
++	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
++	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
++	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
++	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
++	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
++	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
++	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
++	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
++	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
++	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
++	DBG_BLOCK_ID_CB_BY4                              = 0x12,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
++	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
++	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
++	DBG_BLOCK_ID_DB_BY4                              = 0x16,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
++	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
++	DBG_BLOCK_ID_TA_BY4                              = 0x24,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
++	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
++	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
++	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
++	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
++	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
++	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
++	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
++	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
++	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
++	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
++	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
++	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
++	DBG_BLOCK_ID_CB_BY8                              = 0x9,
++	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
++	DBG_BLOCK_ID_DB_BY8                              = 0xb,
++	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
++	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
++	DBG_BLOCK_ID_TA_BY8                              = 0x12,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
++	DBG_BLOCK_ID_TD_BY8                              = 0x16,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
++	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
++	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
++	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
++	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
++	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
++	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
++	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
++	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
++	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
++	DBG_BLOCK_ID_TA_BY16                             = 0x9,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
++	DBG_BLOCK_ID_TD_BY16                             = 0xb,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
++	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
++	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
++} DebugBlockId_BY16;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++typedef enum HPD_INT_CONTROL_ACK {
++	HPD_INT_CONTROL_ACK_0                            = 0x0,
++	HPD_INT_CONTROL_ACK_1                            = 0x1,
++} HPD_INT_CONTROL_ACK;
++typedef enum HPD_INT_CONTROL_POLARITY {
++	HPD_INT_CONTROL_GEN_INT_ON_DISCON                = 0x0,
++	HPD_INT_CONTROL_GEN_INT_ON_CON                   = 0x1,
++} HPD_INT_CONTROL_POLARITY;
++typedef enum HPD_INT_CONTROL_RX_INT_ACK {
++	HPD_INT_CONTROL_RX_INT_ACK_0                     = 0x0,
++	HPD_INT_CONTROL_RX_INT_ACK_1                     = 0x1,
++} HPD_INT_CONTROL_RX_INT_ACK;
++typedef enum DPDBG_EN {
++	DPDBG_DISABLE                                    = 0x0,
++	DPDBG_ENABLE                                     = 0x1,
++} DPDBG_EN;
++typedef enum DPDBG_INPUT_EN {
++	DPDBG_INPUT_DISABLE                              = 0x0,
++	DPDBG_INPUT_ENABLE                               = 0x1,
++} DPDBG_INPUT_EN;
++typedef enum DPDBG_ERROR_DETECTION_MODE {
++	DPDBG_ERROR_DETECTION_MODE_CSC                   = 0x0,
++	DPDBG_ERROR_DETECTION_MODE_RS_ENCODING           = 0x1,
++} DPDBG_ERROR_DETECTION_MODE;
++typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
++	DPDBG_FIFO_OVERFLOW_INT_DISABLE                  = 0x0,
++	DPDBG_FIFO_OVERFLOW_INT_ENABLE                   = 0x1,
++} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
++typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
++	DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED              = 0x0,
++	DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED              = 0x1,
++} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
++typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
++	DPDBG_FIFO_OVERFLOW_INT_NO_ACK                   = 0x0,
++	DPDBG_FIFO_OVERFLOW_INT_CLEAR                    = 0x1,
++} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
++typedef enum PM_ASSERT_RESET {
++	PM_ASSERT_RESET_0                                = 0x0,
++	PM_ASSERT_RESET_1                                = 0x1,
++} PM_ASSERT_RESET;
++typedef enum DAC_MUX_SELECT {
++	DAC_MUX_SELECT_DACA                              = 0x0,
++	DAC_MUX_SELECT_DACB                              = 0x1,
++} DAC_MUX_SELECT;
++typedef enum TMDS_DVO_MUX_SELECT {
++	TMDS_DVO_MUX_SELECT_B                            = 0x0,
++	TMDS_DVO_MUX_SELECT_G                            = 0x1,
++	TMDS_DVO_MUX_SELECT_R                            = 0x2,
++	TMDS_DVO_MUX_SELECT_RESERVED                     = 0x3,
++} TMDS_DVO_MUX_SELECT;
++typedef enum DACA_SOFT_RESET {
++	DACA_SOFT_RESET_0                                = 0x0,
++	DACA_SOFT_RESET_1                                = 0x1,
++} DACA_SOFT_RESET;
++typedef enum I2S0_SPDIF0_SOFT_RESET {
++	I2S0_SPDIF0_SOFT_RESET_0                         = 0x0,
++	I2S0_SPDIF0_SOFT_RESET_1                         = 0x1,
++} I2S0_SPDIF0_SOFT_RESET;
++typedef enum I2S1_SOFT_RESET {
++	I2S1_SOFT_RESET_0                                = 0x0,
++	I2S1_SOFT_RESET_1                                = 0x1,
++} I2S1_SOFT_RESET;
++typedef enum SPDIF1_SOFT_RESET {
++	SPDIF1_SOFT_RESET_0                              = 0x0,
++	SPDIF1_SOFT_RESET_1                              = 0x1,
++} SPDIF1_SOFT_RESET;
++typedef enum DB_CLK_SOFT_RESET {
++	DB_CLK_SOFT_RESET_0                              = 0x0,
++	DB_CLK_SOFT_RESET_1                              = 0x1,
++} DB_CLK_SOFT_RESET;
++typedef enum FMT0_SOFT_RESET {
++	FMT0_SOFT_RESET_0                                = 0x0,
++	FMT0_SOFT_RESET_1                                = 0x1,
++} FMT0_SOFT_RESET;
++typedef enum FMT1_SOFT_RESET {
++	FMT1_SOFT_RESET_0                                = 0x0,
++	FMT1_SOFT_RESET_1                                = 0x1,
++} FMT1_SOFT_RESET;
++typedef enum FMT2_SOFT_RESET {
++	FMT2_SOFT_RESET_0                                = 0x0,
++	FMT2_SOFT_RESET_1                                = 0x1,
++} FMT2_SOFT_RESET;
++typedef enum FMT3_SOFT_RESET {
++	FMT3_SOFT_RESET_0                                = 0x0,
++	FMT3_SOFT_RESET_1                                = 0x1,
++} FMT3_SOFT_RESET;
++typedef enum FMT4_SOFT_RESET {
++	FMT4_SOFT_RESET_0                                = 0x0,
++	FMT4_SOFT_RESET_1                                = 0x1,
++} FMT4_SOFT_RESET;
++typedef enum FMT5_SOFT_RESET {
++	FMT5_SOFT_RESET_0                                = 0x0,
++	FMT5_SOFT_RESET_1                                = 0x1,
++} FMT5_SOFT_RESET;
++typedef enum MVP_SOFT_RESET {
++	MVP_SOFT_RESET_0                                 = 0x0,
++	MVP_SOFT_RESET_1                                 = 0x1,
++} MVP_SOFT_RESET;
++typedef enum ABM_SOFT_RESET {
++	ABM_SOFT_RESET_0                                 = 0x0,
++	ABM_SOFT_RESET_1                                 = 0x1,
++} ABM_SOFT_RESET;
++typedef enum DVO_SOFT_RESET {
++	DVO_SOFT_RESET_0                                 = 0x0,
++	DVO_SOFT_RESET_1                                 = 0x1,
++} DVO_SOFT_RESET;
++typedef enum DIGA_FE_SOFT_RESET {
++	DIGA_FE_SOFT_RESET_0                             = 0x0,
++	DIGA_FE_SOFT_RESET_1                             = 0x1,
++} DIGA_FE_SOFT_RESET;
++typedef enum DIGA_BE_SOFT_RESET {
++	DIGA_BE_SOFT_RESET_0                             = 0x0,
++	DIGA_BE_SOFT_RESET_1                             = 0x1,
++} DIGA_BE_SOFT_RESET;
++typedef enum DIGB_FE_SOFT_RESET {
++	DIGB_FE_SOFT_RESET_0                             = 0x0,
++	DIGB_FE_SOFT_RESET_1                             = 0x1,
++} DIGB_FE_SOFT_RESET;
++typedef enum DIGB_BE_SOFT_RESET {
++	DIGB_BE_SOFT_RESET_0                             = 0x0,
++	DIGB_BE_SOFT_RESET_1                             = 0x1,
++} DIGB_BE_SOFT_RESET;
++typedef enum DIGC_FE_SOFT_RESET {
++	DIGC_FE_SOFT_RESET_0                             = 0x0,
++	DIGC_FE_SOFT_RESET_1                             = 0x1,
++} DIGC_FE_SOFT_RESET;
++typedef enum DIGC_BE_SOFT_RESET {
++	DIGC_BE_SOFT_RESET_0                             = 0x0,
++	DIGC_BE_SOFT_RESET_1                             = 0x1,
++} DIGC_BE_SOFT_RESET;
++typedef enum DIGD_FE_SOFT_RESET {
++	DIGD_FE_SOFT_RESET_0                             = 0x0,
++	DIGD_FE_SOFT_RESET_1                             = 0x1,
++} DIGD_FE_SOFT_RESET;
++typedef enum DIGD_BE_SOFT_RESET {
++	DIGD_BE_SOFT_RESET_0                             = 0x0,
++	DIGD_BE_SOFT_RESET_1                             = 0x1,
++} DIGD_BE_SOFT_RESET;
++typedef enum DIGE_FE_SOFT_RESET {
++	DIGE_FE_SOFT_RESET_0                             = 0x0,
++	DIGE_FE_SOFT_RESET_1                             = 0x1,
++} DIGE_FE_SOFT_RESET;
++typedef enum DIGE_BE_SOFT_RESET {
++	DIGE_BE_SOFT_RESET_0                             = 0x0,
++	DIGE_BE_SOFT_RESET_1                             = 0x1,
++} DIGE_BE_SOFT_RESET;
++typedef enum DIGF_FE_SOFT_RESET {
++	DIGF_FE_SOFT_RESET_0                             = 0x0,
++	DIGF_FE_SOFT_RESET_1                             = 0x1,
++} DIGF_FE_SOFT_RESET;
++typedef enum DIGF_BE_SOFT_RESET {
++	DIGF_BE_SOFT_RESET_0                             = 0x0,
++	DIGF_BE_SOFT_RESET_1                             = 0x1,
++} DIGF_BE_SOFT_RESET;
++typedef enum DIGG_FE_SOFT_RESET {
++	DIGG_FE_SOFT_RESET_0                             = 0x0,
++	DIGG_FE_SOFT_RESET_1                             = 0x1,
++} DIGG_FE_SOFT_RESET;
++typedef enum DIGG_BE_SOFT_RESET {
++	DIGG_BE_SOFT_RESET_0                             = 0x0,
++	DIGG_BE_SOFT_RESET_1                             = 0x1,
++} DIGG_BE_SOFT_RESET;
++typedef enum DPDBG_SOFT_RESET {
++	DPDBG_SOFT_RESET_0                               = 0x0,
++	DPDBG_SOFT_RESET_1                               = 0x1,
++} DPDBG_SOFT_RESET;
++typedef enum DIGLPA_FE_SOFT_RESET {
++	DIGLPA_FE_SOFT_RESET_0                           = 0x0,
++	DIGLPA_FE_SOFT_RESET_1                           = 0x1,
++} DIGLPA_FE_SOFT_RESET;
++typedef enum DIGLPA_BE_SOFT_RESET {
++	DIGLPA_BE_SOFT_RESET_0                           = 0x0,
++	DIGLPA_BE_SOFT_RESET_1                           = 0x1,
++} DIGLPA_BE_SOFT_RESET;
++typedef enum DIGLPB_FE_SOFT_RESET {
++	DIGLPB_FE_SOFT_RESET_0                           = 0x0,
++	DIGLPB_FE_SOFT_RESET_1                           = 0x1,
++} DIGLPB_FE_SOFT_RESET;
++typedef enum DIGLPB_BE_SOFT_RESET {
++	DIGLPB_BE_SOFT_RESET_0                           = 0x0,
++	DIGLPB_BE_SOFT_RESET_1                           = 0x1,
++} DIGLPB_BE_SOFT_RESET;
++typedef enum GENERICA_STEREOSYNC_SEL {
++	GENERICA_STEREOSYNC_SEL_D1                       = 0x0,
++	GENERICA_STEREOSYNC_SEL_D2                       = 0x1,
++	GENERICA_STEREOSYNC_SEL_D3                       = 0x2,
++	GENERICA_STEREOSYNC_SEL_D4                       = 0x3,
++	GENERICA_STEREOSYNC_SEL_D5                       = 0x4,
++	GENERICA_STEREOSYNC_SEL_D6                       = 0x5,
++	GENERICA_STEREOSYNC_SEL_RESERVED                 = 0x6,
++} GENERICA_STEREOSYNC_SEL;
++typedef enum GENERICB_STEREOSYNC_SEL {
++	GENERICB_STEREOSYNC_SEL_D1                       = 0x0,
++	GENERICB_STEREOSYNC_SEL_D2                       = 0x1,
++	GENERICB_STEREOSYNC_SEL_D3                       = 0x2,
++	GENERICB_STEREOSYNC_SEL_D4                       = 0x3,
++	GENERICB_STEREOSYNC_SEL_D5                       = 0x4,
++	GENERICB_STEREOSYNC_SEL_D6                       = 0x5,
++	GENERICB_STEREOSYNC_SEL_RESERVED                 = 0x6,
++} GENERICB_STEREOSYNC_SEL;
++typedef enum DCO_DBG_BLOCK_SEL {
++	DCO_DBG_BLOCK_SEL_DCO                            = 0x0,
++	DCO_DBG_BLOCK_SEL_ABM                            = 0x1,
++	DCO_DBG_BLOCK_SEL_DVO                            = 0x2,
++	DCO_DBG_BLOCK_SEL_DAC                            = 0x3,
++	DCO_DBG_BLOCK_SEL_MVP                            = 0x4,
++	DCO_DBG_BLOCK_SEL_FMT0                           = 0x5,
++	DCO_DBG_BLOCK_SEL_FMT1                           = 0x6,
++	DCO_DBG_BLOCK_SEL_FMT2                           = 0x7,
++	DCO_DBG_BLOCK_SEL_FMT3                           = 0x8,
++	DCO_DBG_BLOCK_SEL_FMT4                           = 0x9,
++	DCO_DBG_BLOCK_SEL_FMT5                           = 0xa,
++	DCO_DBG_BLOCK_SEL_DIGFE_A                        = 0xb,
++	DCO_DBG_BLOCK_SEL_DIGFE_B                        = 0xc,
++	DCO_DBG_BLOCK_SEL_DIGFE_C                        = 0xd,
++	DCO_DBG_BLOCK_SEL_DIGFE_D                        = 0xe,
++	DCO_DBG_BLOCK_SEL_DIGFE_E                        = 0xf,
++	DCO_DBG_BLOCK_SEL_DIGFE_F                        = 0x10,
++	DCO_DBG_BLOCK_SEL_DIGFE_G                        = 0x11,
++	DCO_DBG_BLOCK_SEL_DIGA                           = 0x12,
++	DCO_DBG_BLOCK_SEL_DIGB                           = 0x13,
++	DCO_DBG_BLOCK_SEL_DIGC                           = 0x14,
++	DCO_DBG_BLOCK_SEL_DIGD                           = 0x15,
++	DCO_DBG_BLOCK_SEL_DIGE                           = 0x16,
++	DCO_DBG_BLOCK_SEL_DIGF                           = 0x17,
++	DCO_DBG_BLOCK_SEL_DIGG                           = 0x18,
++	DCO_DBG_BLOCK_SEL_DPFE_A                         = 0x19,
++	DCO_DBG_BLOCK_SEL_DPFE_B                         = 0x1a,
++	DCO_DBG_BLOCK_SEL_DPFE_C                         = 0x1b,
++	DCO_DBG_BLOCK_SEL_DPFE_D                         = 0x1c,
++	DCO_DBG_BLOCK_SEL_DPFE_E                         = 0x1d,
++	DCO_DBG_BLOCK_SEL_DPFE_F                         = 0x1e,
++	DCO_DBG_BLOCK_SEL_DPFE_G                         = 0x1f,
++	DCO_DBG_BLOCK_SEL_DPA                            = 0x20,
++	DCO_DBG_BLOCK_SEL_DPB                            = 0x21,
++	DCO_DBG_BLOCK_SEL_DPC                            = 0x22,
++	DCO_DBG_BLOCK_SEL_DPD                            = 0x23,
++	DCO_DBG_BLOCK_SEL_DPE                            = 0x24,
++	DCO_DBG_BLOCK_SEL_DPF                            = 0x25,
++	DCO_DBG_BLOCK_SEL_DPG                            = 0x26,
++	DCO_DBG_BLOCK_SEL_AUX0                           = 0x27,
++	DCO_DBG_BLOCK_SEL_AUX1                           = 0x28,
++	DCO_DBG_BLOCK_SEL_AUX2                           = 0x29,
++	DCO_DBG_BLOCK_SEL_AUX3                           = 0x2a,
++	DCO_DBG_BLOCK_SEL_AUX4                           = 0x2b,
++	DCO_DBG_BLOCK_SEL_AUX5                           = 0x2c,
++	DCO_DBG_BLOCK_SEL_PERFMON_DCO                    = 0x2d,
++	DCO_DBG_BLOCK_SEL_AUDIO_OUT                      = 0x2e,
++	DCO_DBG_BLOCK_SEL_DIGLPFEA                       = 0x2f,
++	DCO_DBG_BLOCK_SEL_DIGLPFEB                       = 0x30,
++	DCO_DBG_BLOCK_SEL_DIGLPA                         = 0x31,
++	DCO_DBG_BLOCK_SEL_DIGLPB                         = 0x32,
++	DCO_DBG_BLOCK_SEL_DPLPFEA                        = 0x33,
++	DCO_DBG_BLOCK_SEL_DPLPFEB                        = 0x34,
++	DCO_DBG_BLOCK_SEL_DPLPA                          = 0x35,
++	DCO_DBG_BLOCK_SEL_DPLPB                          = 0x36,
++} DCO_DBG_BLOCK_SEL;
++typedef enum DCO_DBG_CLOCK_SEL {
++	DCO_DBG_CLOCK_SEL_DISPCLK                        = 0x0,
++	DCO_DBG_CLOCK_SEL_SCLK                           = 0x1,
++	DCO_DBG_CLOCK_SEL_MVPCLK                         = 0x2,
++	DCO_DBG_CLOCK_SEL_DVOCLK                         = 0x3,
++	DCO_DBG_CLOCK_SEL_DACCLK                         = 0x4,
++	DCO_DBG_CLOCK_SEL_REFCLK                         = 0x5,
++	DCO_DBG_CLOCK_SEL_SYMCLKA                        = 0x6,
++	DCO_DBG_CLOCK_SEL_SYMCLKB                        = 0x7,
++	DCO_DBG_CLOCK_SEL_SYMCLKC                        = 0x8,
++	DCO_DBG_CLOCK_SEL_SYMCLKD                        = 0x9,
++	DCO_DBG_CLOCK_SEL_SYMCLKE                        = 0xa,
++	DCO_DBG_CLOCK_SEL_SYMCLKF                        = 0xb,
++	DCO_DBG_CLOCK_SEL_SYMCLKG                        = 0xc,
++	DCO_DBG_CLOCK_SEL_RESERVED                       = 0xd,
++	DCO_DBG_CLOCK_SEL_AM0CLK                         = 0xe,
++	DCO_DBG_CLOCK_SEL_AM1CLK                         = 0xf,
++	DCO_DBG_CLOCK_SEL_AM2CLK                         = 0x10,
++	DCO_DBG_CLOCK_SEL_SYMCLKLPA                      = 0x11,
++	DCO_DBG_CLOCK_SEL_SYMCLKLPB                      = 0x12,
++} DCO_DBG_CLOCK_SEL;
++typedef enum DOUT_I2C_CONTROL_GO {
++	DOUT_I2C_CONTROL_STOP_TRANSFER                   = 0x0,
++	DOUT_I2C_CONTROL_START_TRANSFER                  = 0x1,
++} DOUT_I2C_CONTROL_GO;
++typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
++	DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER        = 0x0,
++	DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER            = 0x1,
++} DOUT_I2C_CONTROL_SOFT_RESET;
++typedef enum DOUT_I2C_CONTROL_SEND_RESET {
++	DOUT_I2C_CONTROL__NOT_SEND_RESET                 = 0x0,
++	DOUT_I2C_CONTROL__SEND_RESET                     = 0x1,
++} DOUT_I2C_CONTROL_SEND_RESET;
++typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
++	DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS             = 0x0,
++	DOUT_I2C_CONTROL_RESET_SW_STATUS                 = 0x1,
++} DOUT_I2C_CONTROL_SW_STATUS_RESET;
++typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
++	DOUT_I2C_CONTROL_SELECT_DDC1                     = 0x0,
++	DOUT_I2C_CONTROL_SELECT_DDC2                     = 0x1,
++	DOUT_I2C_CONTROL_SELECT_DDC3                     = 0x2,
++	DOUT_I2C_CONTROL_SELECT_DDC4                     = 0x3,
++	DOUT_I2C_CONTROL_SELECT_DDC5                     = 0x4,
++	DOUT_I2C_CONTROL_SELECT_DDC6                     = 0x5,
++	DOUT_I2C_CONTROL_SELECT_DDCVGA                   = 0x6,
++} DOUT_I2C_CONTROL_DDC_SELECT;
++typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
++	DOUT_I2C_CONTROL_TRANS0                          = 0x0,
++	DOUT_I2C_CONTROL_TRANS0_TRANS1                   = 0x1,
++	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2            = 0x2,
++	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3     = 0x3,
++} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
++typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
++	DOUT_I2C_CONTROL_NORMAL_DEBUG                    = 0x0,
++	DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG            = 0x1,
++} DOUT_I2C_CONTROL_DBG_REF_SEL;
++typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
++	DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL          = 0x0,
++	DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH            = 0x1,
++	DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED      = 0x2,
++	DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED      = 0x3,
++} DOUT_I2C_ARBITRATION_SW_PRIORITY;
++typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
++	DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED            = 0x0,
++	DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED           = 0x1,
++} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
++typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
++	DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER  = 0x0,
++	DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER      = 0x1,
++} DOUT_I2C_ARBITRATION_ABORT_XFER;
++typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
++	DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ        = 0x0,
++	DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ            = 0x1,
++} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
++typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
++	DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG     = 0x0,
++	DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG         = 0x1,
++} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
++typedef enum DOUT_I2C_ACK {
++	DOUT_I2C_NO_ACK                                  = 0x0,
++	DOUT_I2C_ACK_TO_CLEAN                            = 0x1,
++} DOUT_I2C_ACK;
++typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
++	DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO       = 0x0,
++	DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
++	DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
++	DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
++} DOUT_I2C_DDC_SPEED_THRESHOLD;
++typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
++	DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
++	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA             = 0x1,
++} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
++typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
++	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS        = 0x0,
++	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS        = 0x1,
++} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
++typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
++	DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT           = 0x0,
++	DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT        = 0x1,
++} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
++typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
++	DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
++	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL             = 0x1,
++} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
++typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
++	DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS          = 0x0,
++	DOUT_I2C_TRANSACTION_STOP_ALL_TRANS              = 0x1,
++} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
++typedef enum DOUT_I2C_DATA_INDEX_WRITE {
++	DOUT_I2C_DATA__NOT_INDEX_WRITE                   = 0x0,
++	DOUT_I2C_DATA__INDEX_WRITE                       = 0x1,
++} DOUT_I2C_DATA_INDEX_WRITE;
++typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
++	DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
++	DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
++} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
++typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
++	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL      = 0x0,
++	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE      = 0x1,
++} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
++typedef enum BLNDV_CONTROL_BLND_MODE {
++	BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY        = 0x0,
++	BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY          = 0x1,
++	BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE      = 0x2,
++	BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE        = 0x3,
++} BLNDV_CONTROL_BLND_MODE;
++typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
++	BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
++	BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
++	BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
++	BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED            = 0x3,
++} BLNDV_CONTROL_BLND_STEREO_TYPE;
++typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
++	BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW           = 0x0,
++	BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH          = 0x1,
++} BLNDV_CONTROL_BLND_STEREO_POLARITY;
++typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
++	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE          = 0x0,
++	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE           = 0x1,
++} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
++typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
++	BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
++	BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
++	BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY  = 0x2,
++	BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED             = 0x3,
++} BLNDV_CONTROL_BLND_ALPHA_MODE;
++typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
++	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE         = 0x0,
++	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE          = 0x1,
++} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
++typedef enum BLNDV_SM_CONTROL2_SM_MODE {
++	BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE           = 0x0,
++	BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING        = 0x2,
++	BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING     = 0x4,
++	BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
++} BLNDV_SM_CONTROL2_SM_MODE;
++typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
++	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE       = 0x0,
++	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE        = 0x1,
++} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
++typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
++	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE       = 0x0,
++	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE        = 0x1,
++} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
++typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
++} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
++typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
++	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
++} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
++typedef enum BLNDV_CONTROL2_PTI_ENABLE {
++	BLNDV_CONTROL2_PTI_ENABLE_FALSE                  = 0x0,
++	BLNDV_CONTROL2_PTI_ENABLE_TRUE                   = 0x1,
++} BLNDV_CONTROL2_PTI_ENABLE;
++typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
++	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE     = 0x0,
++	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE      = 0x1,
++} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
++typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
++	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE     = 0x0,
++	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE      = 0x1,
++} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
++typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
++	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
++	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
++} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
++typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
++	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
++	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
++} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
++	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE  = 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
++	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
++typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
++	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
++	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
++} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
++typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
++	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW              = 0x0,
++	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH             = 0x1,
++} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
++typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
++	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
++	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
++} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
++
++#endif /* DCE_11_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
+new file mode 100644
+index 0000000..a438c2b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
+@@ -0,0 +1,17557 @@
++/*
++ * DCE_11_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DCE_11_0_SH_MASK_H
++#define DCE_11_0_SH_MASK_H
++
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x1
++#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0
++#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x1
++#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0
++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA_MASK 0xffffff
++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA__SHIFT 0x0
++#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS_MASK 0x3000000
++#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS__SHIFT 0x18
++#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000
++#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c
++#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE_MASK 0x20000000
++#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE__SHIFT 0x1d
++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xc0000000
++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x2
++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x4
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8
++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x20
++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x40
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x80
++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200
++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x400
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800
++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1000
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x2000
++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x4000
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x8000
++#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x1
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x2
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x4
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8
++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x20
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x40
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80
++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x400
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800
++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x1000
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x2000
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x4000
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x8000
++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x10000
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x20000
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x40000
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x80000
++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x100000
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x200000
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x400000
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x1000000
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x2000000
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x4000000
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x8000000
++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000
++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
++#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
++#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
++#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
++#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
++#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
++#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
++#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
++#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
++#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
++#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
++#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
++#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
++#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
++#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
++#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
++#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
++#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
++#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2
++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4
++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100
++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
++#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
++#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000
++#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
++#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
++#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
++#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
++#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
++#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
++#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
++#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
++#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
++#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
++#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
++#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
++#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
++#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
++#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
++#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
++#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100
++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000
++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
++#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
++#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
++#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
++#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
++#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
++#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
++#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
++#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
++#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
++#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
++#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
++#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
++#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0
++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a
++#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
++#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
++#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc
++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2
++#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
++#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
++#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1
++#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
++#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x2
++#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
++#define PERFMON_HI__PERFMON_HI_MASK 0xffff
++#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
++#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
++#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
++#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
++#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
++#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1
++#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
++#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2
++#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf
++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100
++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
++#define DCE_VERSION__MAJOR_VERSION_MASK 0xff
++#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
++#define DCE_VERSION__MINOR_VERSION_MASK 0xff00
++#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff
++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1
++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff
++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
++#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
++#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
++#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
++#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
++#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
++#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40
++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
++#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
++#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
++#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80
++#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000
++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x1
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x2
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x4
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x8
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x10
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x20
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x40
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x100
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x10000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x20000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x40000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x80000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x100000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x200000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x400000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x1000000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x2000000
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0xf
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0xff0
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30
++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30
++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
++#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE_MASK 0x1
++#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
++#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK_MASK 0x30
++#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK__SHIFT 0x4
++#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL_MASK 0x100
++#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL__SHIFT 0x8
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
++#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
++#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
++#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
++#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
++#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
++#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
++#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
++#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
++#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
++#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
++#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
++#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
++#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
++#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
++#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
++#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
++#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
++#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
++#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x3
++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700
++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700
++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
++#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
++#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff
++#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000
++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17
++#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000
++#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18
++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
++#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
++#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000
++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000
++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff
++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00
++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0xf00000
++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0xf000000
++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
++#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
++#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
++#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000
++#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d
++#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000
++#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f
++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
++#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf
++#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
++#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0
++#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
++#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00
++#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
++#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000
++#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
++#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000
++#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
++#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000
++#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
++#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000
++#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
++#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000
++#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0
++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
++#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
++#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
++#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
++#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x1
++#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0
++#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xffffffff
++#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0
++#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0xff
++#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0xff00
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x3f0000
++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10
++#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x3
++#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0
++#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK 0x30
++#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT 0x4
++#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x80
++#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7
++#define DVMM_CNTL__DBG_DCE_VMID_MASK 0xf00
++#define DVMM_CNTL__DBG_DCE_VMID__SHIFT 0x8
++#define DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK 0x8000
++#define DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT 0xf
++#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x20000
++#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11
++#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x40000
++#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12
++#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xffffffff
++#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0
++#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xffffffff
++#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
++#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
++#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
++#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
++#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
++#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
++#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
++#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
++#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
++#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x3f0000
++#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xfff00000
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x3
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc
++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10
++#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40
++#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6
++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100
++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600
++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000
++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000
++#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000
++#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10
++#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000
++#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12
++#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000
++#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000
++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000
++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000
++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000
++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3
++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc
++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10
++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60
++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180
++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200
++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00
++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000
++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000
++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000
++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000
++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000
++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000
++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000
++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
++#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000
++#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000
++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x1
++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0
++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x2
++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1
++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x4
++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2
++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x8
++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3
++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x10
++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4
++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000
++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10
++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40
++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100
++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000
++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000
++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000
++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000
++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000
++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000
++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20
++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80
++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400
++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000
++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000
++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000
++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000
++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000
++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000
++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4
++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20
++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80
++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400
++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000
++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000
++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000
++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000
++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000
++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000
++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000
++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000
++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000
++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x3
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x4
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x18
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x20
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0xc0
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x100
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x600
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x800
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x3000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x4000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x18000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x20000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0xc0000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x100000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x600000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x800000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x3000000
++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x3
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0xc
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x30
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0xc0
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x300
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0xc00
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x3000
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0xc000
++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe
++#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
++#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
++#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
++#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
++#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
++#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
++#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400
++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800
++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000
++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc
++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000
++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000
++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000
++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
++#define DCI_MISC__MCIF_WB_URG_OVRD_MASK 0x1
++#define DCI_MISC__MCIF_WB_URG_OVRD__SHIFT 0x0
++#define DCI_MISC__MCIF_WB_URG_LVL_MASK 0x1e
++#define DCI_MISC__MCIF_WB_URG_LVL__SHIFT 0x1
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1
++#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0
++#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0
++#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4
++#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00
++#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
++#define DC_GENERICA__GENERICA_EN_MASK 0x1
++#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
++#define DC_GENERICA__GENERICA_SEL_MASK 0xf80
++#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_GENERICB__GENERICB_EN_MASK 0x1
++#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
++#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
++#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000
++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000
++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000
++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000
++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
++#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0
++#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
++#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00
++#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000
++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11
++#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
++#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
++#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
++#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP_MASK 0x3800000
++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP__SHIFT 0x17
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
++#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
++#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1
++#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0
++#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10
++#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4
++#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300
++#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8
++#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000
++#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc
++#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1
++#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
++#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000
++#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c
++#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000
++#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d
++#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000
++#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e
++#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000
++#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f
++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3
++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc
++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30
++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0
++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000
++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
++#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
++#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
++#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17
++#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
++#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000
++#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
++#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
++#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
++#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
++#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
++#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
++#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
++#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
++#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
++#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
++#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
++#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
++#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
++#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
++#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
++#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
++#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
++#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
++#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
++#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
++#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
++#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
++#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
++#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
++#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
++#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
++#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff
++#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0
++#define DCIO_DEBUG17__DCIO_DEBUG17_MASK 0xffffffff
++#define DCIO_DEBUG17__DCIO_DEBUG17__SHIFT 0x0
++#define DCIO_DEBUG18__DCIO_DEBUG18_MASK 0xffffffff
++#define DCIO_DEBUG18__DCIO_DEBUG18__SHIFT 0x0
++#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK 0xffffffff
++#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT 0x0
++#define DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK 0xffffffff
++#define DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT 0x0
++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000
++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000
++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000
++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000
++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
++#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
++#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
++#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
++#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
++#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
++#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
++#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
++#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
++#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
++#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
++#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
++#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
++#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x20
++#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
++#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40
++#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x200
++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
++#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x400
++#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x20000
++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
++#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x40000
++#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x100000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x200000
++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
++#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x400000
++#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x1000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x2000000
++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
++#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x4000000
++#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000
++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
++#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000
++#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0xf0000
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0xf00000
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
++#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
++#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
++#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
++#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40
++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
++#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
++#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
++#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
++#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
++#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
++#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
++#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
++#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x2
++#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
++#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
++#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
++#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define GRPH_CONTROL__GRPH_Z_MASK 0x30
++#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
++#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
++#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
++#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
++#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
++#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
++#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
++#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
++#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
++#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
++#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
++#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
++#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
++#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
++#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
++#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
++#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
++#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
++#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x1
++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
++#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
++#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
++#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2
++#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x10
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x20
++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0xff
++#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
++#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
++#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
++#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
++#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
++#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
++#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
++#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
++#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
++#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
++#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
++#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
++#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
++#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
++#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
++#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
++#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
++#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
++#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
++#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
++#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
++#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
++#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
++#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
++#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
++#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
++#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
++#define KEY_CONTROL__KEY_MODE_MASK 0x6
++#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
++#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
++#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
++#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
++#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
++#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
++#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
++#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
++#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define CUR_CONTROL__CURSOR_EN_MASK 0x1
++#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
++#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
++#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
++#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
++#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
++#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
++#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
++#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
++#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
++#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
++#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
++#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
++#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
++#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
++#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
++#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
++#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
++#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
++#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
++#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
++#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
++#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
++#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
++#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
++#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
++#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
++#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
++#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
++#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
++#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
++#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
++#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
++#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000
++#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
++#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000
++#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
++#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
++#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
++#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
++#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
++#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
++#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
++#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
++#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
++#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
++#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
++#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
++#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1
++#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e
++#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0
++#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00
++#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000
++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000
++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
++#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
++#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f
++#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00
++#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
++#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
++#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
++#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
++#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
++#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
++#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
++#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000
++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13
++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0
++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
++#define DCP_DEBUG_SG__DCP_DEBUG_SG_MASK 0xffffffff
++#define DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT 0x0
++#define DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK 0xffffffff
++#define DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT 0x0
++#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK 0xffffffff
++#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT 0x0
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
++#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
++#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
++#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x1
++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x1e
++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x200
++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0xffff
++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xffff0000
++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
++#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
++#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
++#define DIG_FE_CNTL__DIG_START_MASK 0x400
++#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
++#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000
++#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
++#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000
++#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x4000000
++#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
++#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
++#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
++#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8
++#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
++#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
++#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
++#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
++#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
++#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
++#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
++#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
++#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
++#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
++#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
++#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
++#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
++#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
++#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
++#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
++#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
++#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
++#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
++#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
++#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
++#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
++#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
++#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
++#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
++#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
++#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
++#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
++#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
++#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
++#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
++#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
++#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
++#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
++#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
++#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
++#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
++#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
++#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
++#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
++#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x1
++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x100
++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
++#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1
++#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
++#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2
++#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
++#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4
++#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
++#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
++#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
++#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
++#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
++#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
++#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
++#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
++#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
++#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
++#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
++#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
++#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
++#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
++#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
++#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
++#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
++#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
++#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
++#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
++#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
++#define DIG_VERSION__DIG_TYPE_MASK 0x1
++#define DIG_VERSION__DIG_TYPE__SHIFT 0x0
++#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
++#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
++#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
++#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
++#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
++#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
++#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
++#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
++#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
++#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMCU_CTRL__RESET_UC_MASK 0x1
++#define DMCU_CTRL__RESET_UC__SHIFT 0x0
++#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
++#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
++#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
++#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x100
++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
++#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
++#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
++#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
++#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
++#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
++#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x40
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x6
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x40
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x6
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x80
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x80
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x7
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x40000000
++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x1e
++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR_MASK 0x40000000
++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x1e
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x80000000
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x1f
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x80000000
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x1f
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
++#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
++#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
++#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
++#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
++#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
++#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
++#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
++#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
++#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
++#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
++#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
++#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
++#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
++#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
++#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
++#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
++#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x10
++#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
++#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
++#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
++#define DP_VID_N__DP_VID_N_MASK 0xffffff
++#define DP_VID_N__DP_VID_N__SHIFT 0x0
++#define DP_VID_M__DP_VID_M_MASK 0xffffff
++#define DP_VID_M__DP_VID_M__SHIFT 0x0
++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
++#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
++#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
++#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
++#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
++#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
++#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
++#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
++#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
++#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
++#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
++#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
++#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
++#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
++#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
++#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
++#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
++#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
++#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff
++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000
++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x10000
++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
++#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
++#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
++#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x7
++#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0
++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000
++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
++#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x10
++#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x20
++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x40
++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x80
++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
++#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xffff0000
++#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
++#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
++#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
++#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
++#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
++#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000
++#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0
++#define AUX_CONTROL__AUX_EN_MASK 0x1
++#define AUX_CONTROL__AUX_EN__SHIFT 0x0
++#define AUX_CONTROL__AUX_RESET_MASK 0x10
++#define AUX_CONTROL__AUX_RESET__SHIFT 0x4
++#define AUX_CONTROL__AUX_RESET_DONE_MASK 0x20
++#define AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
++#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
++#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
++#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
++#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
++#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
++#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
++#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
++#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
++#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
++#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
++#define AUX_CONTROL__SPARE_0_MASK 0x40000000
++#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
++#define AUX_CONTROL__SPARE_1_MASK 0x80000000
++#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
++#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
++#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
++#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
++#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
++#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
++#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
++#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
++#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
++#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
++#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
++#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
++#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
++#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
++#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
++#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
++#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
++#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
++#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
++#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
++#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
++#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
++#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
++#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
++#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
++#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000
++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00
++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000
++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0
++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff
++#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0
++#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff
++#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0
++#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff
++#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0
++#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff
++#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0
++#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff
++#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0
++#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff
++#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0
++#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff
++#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0
++#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff
++#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0
++#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff
++#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0
++#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff
++#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0
++#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff
++#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0
++#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff
++#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0
++#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff
++#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0
++#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff
++#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0
++#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff
++#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0
++#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff
++#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0
++#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff
++#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0
++#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff
++#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0
++#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
++#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
++#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
++#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
++#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
++#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
++#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
++#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
++#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
++#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
++#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
++#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
++#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
++#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
++#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
++#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
++#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
++#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
++#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
++#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
++#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
++#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
++#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
++#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
++#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
++#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
++#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
++#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
++#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
++#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0
++#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
++#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
++#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
++#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
++#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x100
++#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8
++#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
++#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
++#define FBC_CNTL__FBC_EN_MASK 0x80000000
++#define FBC_CNTL__FBC_EN__SHIFT 0x1f
++#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff
++#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
++#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
++#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
++#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
++#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
++#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
++#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
++#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
++#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
++#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
++#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
++#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
++#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
++#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
++#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
++#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
++#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
++#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff
++#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
++#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff
++#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
++#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff
++#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
++#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff
++#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
++#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff
++#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
++#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff
++#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
++#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff
++#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
++#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff
++#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
++#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff
++#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
++#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff
++#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
++#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff
++#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
++#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff
++#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
++#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff
++#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
++#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff
++#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
++#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff
++#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
++#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff
++#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0xfff
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0xfff0000
++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0xfff
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0xfff0000
++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0xfff
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
++#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
++#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
++#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
++#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
++#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
++#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
++#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
++#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
++#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
++#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
++#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
++#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x2000
++#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
++#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
++#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
++#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
++#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000
++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
++#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000
++#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f
++#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
++#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000
++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
++#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000
++#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000
++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11
++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000
++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12
++#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
++#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10
++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff
++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0
++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
++#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
++#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
++#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x20
++#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
++#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x40
++#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100
++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
++#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x200
++#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
++#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
++#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
++#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
++#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
++#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
++#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
++#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
++#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
++#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
++#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
++#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
++#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
++#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
++#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
++#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
++#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
++#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
++#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
++#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
++#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
++#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
++#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
++#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
++#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
++#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
++#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
++#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
++#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
++#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
++#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
++#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
++#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
++#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
++#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
++#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
++#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
++#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
++#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
++#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
++#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
++#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
++#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
++#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
++#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
++#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
++#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
++#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
++#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
++#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
++#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40
++#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
++#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80
++#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
++#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000
++#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
++#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
++#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
++#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
++#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
++#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
++#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
++#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
++#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
++#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
++#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
++#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
++#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
++#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
++#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
++#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff
++#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
++#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000
++#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
++#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000
++#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
++#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff
++#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
++#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
++#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
++#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
++#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
++#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff
++#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
++#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
++#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
++#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff
++#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff
++#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
++#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
++#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
++#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
++#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
++#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
++#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
++#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
++#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
++#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10
++#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
++#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000
++#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
++#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
++#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
++#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
++#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
++#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
++#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
++#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
++#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
++#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
++#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
++#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
++#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
++#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
++#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
++#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
++#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
++#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
++#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
++#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
++#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
++#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
++#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
++#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
++#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
++#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
++#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
++#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
++#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
++#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
++#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
++#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
++#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
++#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
++#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
++#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
++#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
++#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff
++#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0
++#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff
++#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0
++#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff
++#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
++#define MVP_CONTROL1__MVP_EN_MASK 0x1
++#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
++#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
++#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
++#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
++#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
++#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
++#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
++#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
++#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
++#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
++#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
++#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
++#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6
++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6
++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
++#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
++#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
++#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
++#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
++#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
++#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
++#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
++#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
++#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
++#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
++#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
++#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
++#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
++#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
++#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
++#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
++#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCL_MODE__SCL_MODE_MASK 0x3
++#define SCL_MODE__SCL_MODE__SHIFT 0x0
++#define SCL_MODE__SCL_PSCL_EN_MASK 0x10
++#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
++#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
++#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
++#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
++#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
++#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
++#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
++#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
++#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
++#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
++#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
++#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
++#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
++#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
++#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
++#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
++#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000
++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
++#define SCLV_MODE__SCL_MODE_MASK 0x1
++#define SCLV_MODE__SCL_MODE__SHIFT 0x0
++#define SCLV_MODE__SCL_MODE_C_MASK 0x2
++#define SCLV_MODE__SCL_MODE_C__SHIFT 0x1
++#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10
++#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
++#define SCLV_MODE__SCL_PSCL_EN_C_MASK 0x20
++#define SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
++#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300
++#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700
++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000
++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
++#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
++#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
++#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
++#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
++#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100
++#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
++#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
++#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
++#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff
++#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000
++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
++#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
++#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
++#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
++#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
++#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff
++#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000
++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
++#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
++#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
++#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
++#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
++#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
++#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
++#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
++#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
++#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
++#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
++#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
++#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
++#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000
++#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
++#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff
++#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
++#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000
++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000
++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
++#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
++#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
++#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
++#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
++#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
++#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0xffffff
++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0xf000000
++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0xffffff
++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0xf000000
++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
++#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
++#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
++#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
++#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
++#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
++#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3
++#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff
++#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
++#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000
++#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
++#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x300
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10000
++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000
++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000
++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000
++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000
++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000
++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000
++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000
++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000
++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000
++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000
++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000
++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000
++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
++#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3
++#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
++#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff
++#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
++#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000
++#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
++#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff
++#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
++#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000
++#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
++#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff
++#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
++#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000
++#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
++#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7
++#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000
++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000
++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000
++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000
++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000
++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000
++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
++#define DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x3
++#define DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
++#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x100
++#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000
++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000
++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000
++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000
++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
++#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3
++#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0
++#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0xff
++#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0
++#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff
++#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0
++#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7
++#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff
++#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
++#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
++#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff
++#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x1
++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x2
++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x100
++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x200
++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x10000
++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x20000
++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x1000000
++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x2000000
++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x1
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x2
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x100
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x200
++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x1
++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x2
++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
++#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0xff
++#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
++#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0xffff
++#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0xffff
++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xffff0000
++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x3ff
++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0xffc00
++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3ff00000
++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x3
++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x4000000
++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x1e
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x20
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0xc0
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0xf00
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x1000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x6000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x78000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x80000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x300000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x400000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x3800000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x4000000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x8000000
++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0xffff
++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xffff0000
++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0xffff
++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xffff0000
++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0xffff
++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xffff0000
++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
++#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1
++#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff
++#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0
++#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
++#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
++#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
++#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
++#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
++#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
++#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30
++#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
++#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0xc0
++#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
++#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
++#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
++#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x1800
++#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
++#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0xe000
++#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
++#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
++#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
++#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
++#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
++#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0xc0000
++#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
++#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
++#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
++#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
++#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
++#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000
++#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
++#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
++#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
++#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0xc0
++#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
++#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x1800
++#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
++#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0xe000
++#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
++#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0xc0000
++#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
++#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000
++#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
++#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7
++#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
++#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
++#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
++#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
++#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
++#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
++#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
++#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
++#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
++#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff
++#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
++#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff
++#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
++#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff
++#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
++#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff
++#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
++#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff
++#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
++#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff
++#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
++#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff
++#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
++#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff
++#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
++#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff
++#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
++#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff
++#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
++#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff
++#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
++#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
++#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
++#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
++#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
++#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0xff
++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0xff00
++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00
++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff
++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
++#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1
++#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e
++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0
++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
++#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00
++#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000
++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000
++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x1
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x1e
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x1e0
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x7fe00
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x100000
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x200000
++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f
++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00
++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x3f
++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0xff00
++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
++#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x1
++#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
++#define UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK 0xfffffffc
++#define UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT 0x2
++#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1
++#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
++#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c
++#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
++#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300
++#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
++#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff
++#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
++#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff
++#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
++#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff
++#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
++#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0
++#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
++#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7
++#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
++#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10
++#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
++#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100
++#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
++#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff
++#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0
++#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff
++#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0
++#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK 0xffff
++#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT 0x0
++#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK 0xffff0000
++#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT 0x10
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff
++#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0
++#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
++#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_WT__VGA_RAM_EN_MASK 0x2
++#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_WT__VGA_CKSEL_MASK 0xc
++#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
++#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
++#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
++#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
++#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
++#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
++#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
++#define GENMO_RD__VGA_RAM_EN_MASK 0x2
++#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
++#define GENMO_RD__VGA_CKSEL_MASK 0xc
++#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
++#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
++#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
++#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
++#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
++#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
++#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
++#define GENENB__BLK_IO_BASE_MASK 0xff
++#define GENENB__BLK_IO_BASE__SHIFT 0x0
++#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
++#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
++#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
++#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
++#define GENS0__SENSE_SWITCH_MASK 0x10
++#define GENS0__SENSE_SWITCH__SHIFT 0x4
++#define GENS0__CRT_INTR_MASK 0x80
++#define GENS0__CRT_INTR__SHIFT 0x7
++#define GENS1__NO_DISPLAY_MASK 0x1
++#define GENS1__NO_DISPLAY__SHIFT 0x0
++#define GENS1__VGA_VSTATUS_MASK 0x8
++#define GENS1__VGA_VSTATUS__SHIFT 0x3
++#define GENS1__PIXEL_READ_BACK_MASK 0x30
++#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
++#define DAC_DATA__DAC_DATA_MASK 0x3f
++#define DAC_DATA__DAC_DATA__SHIFT 0x0
++#define DAC_MASK__DAC_MASK_MASK 0xff
++#define DAC_MASK__DAC_MASK__SHIFT 0x0
++#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
++#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
++#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
++#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
++#define SEQ8_IDX__SEQ_IDX_MASK 0x7
++#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
++#define SEQ8_DATA__SEQ_DATA_MASK 0xff
++#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
++#define SEQ00__SEQ_RST0B_MASK 0x1
++#define SEQ00__SEQ_RST0B__SHIFT 0x0
++#define SEQ00__SEQ_RST1B_MASK 0x2
++#define SEQ00__SEQ_RST1B__SHIFT 0x1
++#define SEQ01__SEQ_DOT8_MASK 0x1
++#define SEQ01__SEQ_DOT8__SHIFT 0x0
++#define SEQ01__SEQ_SHIFT2_MASK 0x4
++#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
++#define SEQ01__SEQ_PCLKBY2_MASK 0x8
++#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
++#define SEQ01__SEQ_SHIFT4_MASK 0x10
++#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
++#define SEQ01__SEQ_MAXBW_MASK 0x20
++#define SEQ01__SEQ_MAXBW__SHIFT 0x5
++#define SEQ02__SEQ_MAP0_EN_MASK 0x1
++#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
++#define SEQ02__SEQ_MAP1_EN_MASK 0x2
++#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
++#define SEQ02__SEQ_MAP2_EN_MASK 0x4
++#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
++#define SEQ02__SEQ_MAP3_EN_MASK 0x8
++#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B1_MASK 0x1
++#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
++#define SEQ03__SEQ_FONT_B2_MASK 0x2
++#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
++#define SEQ03__SEQ_FONT_A1_MASK 0x4
++#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
++#define SEQ03__SEQ_FONT_A2_MASK 0x8
++#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
++#define SEQ03__SEQ_FONT_B0_MASK 0x10
++#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
++#define SEQ03__SEQ_FONT_A0_MASK 0x20
++#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
++#define SEQ04__SEQ_256K_MASK 0x2
++#define SEQ04__SEQ_256K__SHIFT 0x1
++#define SEQ04__SEQ_ODDEVEN_MASK 0x4
++#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
++#define SEQ04__SEQ_CHAIN_MASK 0x8
++#define SEQ04__SEQ_CHAIN__SHIFT 0x3
++#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
++#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
++#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
++#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
++#define CRT00__H_TOTAL_MASK 0xff
++#define CRT00__H_TOTAL__SHIFT 0x0
++#define CRT01__H_DISP_END_MASK 0xff
++#define CRT01__H_DISP_END__SHIFT 0x0
++#define CRT02__H_BLANK_START_MASK 0xff
++#define CRT02__H_BLANK_START__SHIFT 0x0
++#define CRT03__H_BLANK_END_MASK 0x1f
++#define CRT03__H_BLANK_END__SHIFT 0x0
++#define CRT03__H_DE_SKEW_MASK 0x60
++#define CRT03__H_DE_SKEW__SHIFT 0x5
++#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
++#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
++#define CRT04__H_SYNC_START_MASK 0xff
++#define CRT04__H_SYNC_START__SHIFT 0x0
++#define CRT05__H_SYNC_END_MASK 0x1f
++#define CRT05__H_SYNC_END__SHIFT 0x0
++#define CRT05__H_SYNC_SKEW_MASK 0x60
++#define CRT05__H_SYNC_SKEW__SHIFT 0x5
++#define CRT05__H_BLANK_END_B5_MASK 0x80
++#define CRT05__H_BLANK_END_B5__SHIFT 0x7
++#define CRT06__V_TOTAL_MASK 0xff
++#define CRT06__V_TOTAL__SHIFT 0x0
++#define CRT07__V_TOTAL_B8_MASK 0x1
++#define CRT07__V_TOTAL_B8__SHIFT 0x0
++#define CRT07__V_DISP_END_B8_MASK 0x2
++#define CRT07__V_DISP_END_B8__SHIFT 0x1
++#define CRT07__V_SYNC_START_B8_MASK 0x4
++#define CRT07__V_SYNC_START_B8__SHIFT 0x2
++#define CRT07__V_BLANK_START_B8_MASK 0x8
++#define CRT07__V_BLANK_START_B8__SHIFT 0x3
++#define CRT07__LINE_CMP_B8_MASK 0x10
++#define CRT07__LINE_CMP_B8__SHIFT 0x4
++#define CRT07__V_TOTAL_B9_MASK 0x20
++#define CRT07__V_TOTAL_B9__SHIFT 0x5
++#define CRT07__V_DISP_END_B9_MASK 0x40
++#define CRT07__V_DISP_END_B9__SHIFT 0x6
++#define CRT07__V_SYNC_START_B9_MASK 0x80
++#define CRT07__V_SYNC_START_B9__SHIFT 0x7
++#define CRT08__ROW_SCAN_START_MASK 0x1f
++#define CRT08__ROW_SCAN_START__SHIFT 0x0
++#define CRT08__BYTE_PAN_MASK 0x60
++#define CRT08__BYTE_PAN__SHIFT 0x5
++#define CRT09__MAX_ROW_SCAN_MASK 0x1f
++#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
++#define CRT09__V_BLANK_START_B9_MASK 0x20
++#define CRT09__V_BLANK_START_B9__SHIFT 0x5
++#define CRT09__LINE_CMP_B9_MASK 0x40
++#define CRT09__LINE_CMP_B9__SHIFT 0x6
++#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
++#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
++#define CRT0A__CURSOR_START_MASK 0x1f
++#define CRT0A__CURSOR_START__SHIFT 0x0
++#define CRT0A__CURSOR_DISABLE_MASK 0x20
++#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
++#define CRT0B__CURSOR_END_MASK 0x1f
++#define CRT0B__CURSOR_END__SHIFT 0x0
++#define CRT0B__CURSOR_SKEW_MASK 0x60
++#define CRT0B__CURSOR_SKEW__SHIFT 0x5
++#define CRT0C__DISP_START_MASK 0xff
++#define CRT0C__DISP_START__SHIFT 0x0
++#define CRT0D__DISP_START_MASK 0xff
++#define CRT0D__DISP_START__SHIFT 0x0
++#define CRT0E__CURSOR_LOC_HI_MASK 0xff
++#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
++#define CRT0F__CURSOR_LOC_LO_MASK 0xff
++#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
++#define CRT10__V_SYNC_START_MASK 0xff
++#define CRT10__V_SYNC_START__SHIFT 0x0
++#define CRT11__V_SYNC_END_MASK 0xf
++#define CRT11__V_SYNC_END__SHIFT 0x0
++#define CRT11__V_INTR_CLR_MASK 0x10
++#define CRT11__V_INTR_CLR__SHIFT 0x4
++#define CRT11__V_INTR_EN_MASK 0x20
++#define CRT11__V_INTR_EN__SHIFT 0x5
++#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
++#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
++#define CRT11__C0T7_WR_ONLY_MASK 0x80
++#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
++#define CRT12__V_DISP_END_MASK 0xff
++#define CRT12__V_DISP_END__SHIFT 0x0
++#define CRT13__DISP_PITCH_MASK 0xff
++#define CRT13__DISP_PITCH__SHIFT 0x0
++#define CRT14__UNDRLN_LOC_MASK 0x1f
++#define CRT14__UNDRLN_LOC__SHIFT 0x0
++#define CRT14__ADDR_CNT_BY4_MASK 0x20
++#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
++#define CRT14__DOUBLE_WORD_MASK 0x40
++#define CRT14__DOUBLE_WORD__SHIFT 0x6
++#define CRT15__V_BLANK_START_MASK 0xff
++#define CRT15__V_BLANK_START__SHIFT 0x0
++#define CRT16__V_BLANK_END_MASK 0xff
++#define CRT16__V_BLANK_END__SHIFT 0x0
++#define CRT17__RA0_AS_A13B_MASK 0x1
++#define CRT17__RA0_AS_A13B__SHIFT 0x0
++#define CRT17__RA1_AS_A14B_MASK 0x2
++#define CRT17__RA1_AS_A14B__SHIFT 0x1
++#define CRT17__VCOUNT_BY2_MASK 0x4
++#define CRT17__VCOUNT_BY2__SHIFT 0x2
++#define CRT17__ADDR_CNT_BY2_MASK 0x8
++#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
++#define CRT17__WRAP_A15TOA0_MASK 0x20
++#define CRT17__WRAP_A15TOA0__SHIFT 0x5
++#define CRT17__BYTE_MODE_MASK 0x40
++#define CRT17__BYTE_MODE__SHIFT 0x6
++#define CRT17__CRTC_SYNC_EN_MASK 0x80
++#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
++#define CRT18__LINE_CMP_MASK 0xff
++#define CRT18__LINE_CMP__SHIFT 0x0
++#define CRT1E__GRPH_DEC_RD1_MASK 0x2
++#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
++#define CRT1F__GRPH_DEC_RD0_MASK 0xff
++#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
++#define CRT22__GRPH_LATCH_DATA_MASK 0xff
++#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
++#define GRPH8_IDX__GRPH_IDX_MASK 0xf
++#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
++#define GRPH8_DATA__GRPH_DATA_MASK 0xff
++#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET0_MASK 0x1
++#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
++#define GRA00__GRPH_SET_RESET1_MASK 0x2
++#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
++#define GRA00__GRPH_SET_RESET2_MASK 0x4
++#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
++#define GRA00__GRPH_SET_RESET3_MASK 0x8
++#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
++#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
++#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
++#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
++#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
++#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
++#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
++#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
++#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
++#define GRA02__GRPH_CCOMP_MASK 0xf
++#define GRA02__GRPH_CCOMP__SHIFT 0x0
++#define GRA03__GRPH_ROTATE_MASK 0x7
++#define GRA03__GRPH_ROTATE__SHIFT 0x0
++#define GRA03__GRPH_FN_SEL_MASK 0x18
++#define GRA03__GRPH_FN_SEL__SHIFT 0x3
++#define GRA04__GRPH_RMAP_MASK 0x3
++#define GRA04__GRPH_RMAP__SHIFT 0x0
++#define GRA05__GRPH_WRITE_MODE_MASK 0x3
++#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
++#define GRA05__GRPH_READ1_MASK 0x8
++#define GRA05__GRPH_READ1__SHIFT 0x3
++#define GRA05__CGA_ODDEVEN_MASK 0x10
++#define GRA05__CGA_ODDEVEN__SHIFT 0x4
++#define GRA05__GRPH_OES_MASK 0x20
++#define GRA05__GRPH_OES__SHIFT 0x5
++#define GRA05__GRPH_PACK_MASK 0x40
++#define GRA05__GRPH_PACK__SHIFT 0x6
++#define GRA06__GRPH_GRAPHICS_MASK 0x1
++#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
++#define GRA06__GRPH_ODDEVEN_MASK 0x2
++#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
++#define GRA06__GRPH_ADRSEL_MASK 0xc
++#define GRA06__GRPH_ADRSEL__SHIFT 0x2
++#define GRA07__GRPH_XCARE0_MASK 0x1
++#define GRA07__GRPH_XCARE0__SHIFT 0x0
++#define GRA07__GRPH_XCARE1_MASK 0x2
++#define GRA07__GRPH_XCARE1__SHIFT 0x1
++#define GRA07__GRPH_XCARE2_MASK 0x4
++#define GRA07__GRPH_XCARE2__SHIFT 0x2
++#define GRA07__GRPH_XCARE3_MASK 0x8
++#define GRA07__GRPH_XCARE3__SHIFT 0x3
++#define GRA08__GRPH_BMSK_MASK 0xff
++#define GRA08__GRPH_BMSK__SHIFT 0x0
++#define ATTRX__ATTR_IDX_MASK 0x1f
++#define ATTRX__ATTR_IDX__SHIFT 0x0
++#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
++#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
++#define ATTRDW__ATTR_DATA_MASK 0xff
++#define ATTRDW__ATTR_DATA__SHIFT 0x0
++#define ATTRDR__ATTR_DATA_MASK 0xff
++#define ATTRDR__ATTR_DATA__SHIFT 0x0
++#define ATTR00__ATTR_PAL_MASK 0x3f
++#define ATTR00__ATTR_PAL__SHIFT 0x0
++#define ATTR01__ATTR_PAL_MASK 0x3f
++#define ATTR01__ATTR_PAL__SHIFT 0x0
++#define ATTR02__ATTR_PAL_MASK 0x3f
++#define ATTR02__ATTR_PAL__SHIFT 0x0
++#define ATTR03__ATTR_PAL_MASK 0x3f
++#define ATTR03__ATTR_PAL__SHIFT 0x0
++#define ATTR04__ATTR_PAL_MASK 0x3f
++#define ATTR04__ATTR_PAL__SHIFT 0x0
++#define ATTR05__ATTR_PAL_MASK 0x3f
++#define ATTR05__ATTR_PAL__SHIFT 0x0
++#define ATTR06__ATTR_PAL_MASK 0x3f
++#define ATTR06__ATTR_PAL__SHIFT 0x0
++#define ATTR07__ATTR_PAL_MASK 0x3f
++#define ATTR07__ATTR_PAL__SHIFT 0x0
++#define ATTR08__ATTR_PAL_MASK 0x3f
++#define ATTR08__ATTR_PAL__SHIFT 0x0
++#define ATTR09__ATTR_PAL_MASK 0x3f
++#define ATTR09__ATTR_PAL__SHIFT 0x0
++#define ATTR0A__ATTR_PAL_MASK 0x3f
++#define ATTR0A__ATTR_PAL__SHIFT 0x0
++#define ATTR0B__ATTR_PAL_MASK 0x3f
++#define ATTR0B__ATTR_PAL__SHIFT 0x0
++#define ATTR0C__ATTR_PAL_MASK 0x3f
++#define ATTR0C__ATTR_PAL__SHIFT 0x0
++#define ATTR0D__ATTR_PAL_MASK 0x3f
++#define ATTR0D__ATTR_PAL__SHIFT 0x0
++#define ATTR0E__ATTR_PAL_MASK 0x3f
++#define ATTR0E__ATTR_PAL__SHIFT 0x0
++#define ATTR0F__ATTR_PAL_MASK 0x3f
++#define ATTR0F__ATTR_PAL__SHIFT 0x0
++#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
++#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
++#define ATTR10__ATTR_MONO_EN_MASK 0x2
++#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
++#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
++#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
++#define ATTR10__ATTR_BLINK_EN_MASK 0x8
++#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
++#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
++#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
++#define ATTR10__ATTR_PCLKBY2_MASK 0x40
++#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
++#define ATTR10__ATTR_CSEL_EN_MASK 0x80
++#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
++#define ATTR11__ATTR_OVSC_MASK 0xff
++#define ATTR11__ATTR_OVSC__SHIFT 0x0
++#define ATTR12__ATTR_MAP_EN_MASK 0xf
++#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
++#define ATTR12__ATTR_VSMUX_MASK 0x30
++#define ATTR12__ATTR_VSMUX__SHIFT 0x4
++#define ATTR13__ATTR_PPAN_MASK 0xf
++#define ATTR13__ATTR_PPAN__SHIFT 0x0
++#define ATTR14__ATTR_CSEL1_MASK 0x3
++#define ATTR14__ATTR_CSEL1__SHIFT 0x0
++#define ATTR14__ATTR_CSEL2_MASK 0xc
++#define ATTR14__ATTR_CSEL2__SHIFT 0x2
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
++#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
++#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
++#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
++#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
++#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
++#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
++#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
++#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
++#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
++#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff
++#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0
++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000
++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000
++#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10
++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f
++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7
++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000
++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf
++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10
++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff
++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00
++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8
++#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000
++#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc
++#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000
++#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd
++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000
++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10
++#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff
++#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0
++#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000
++#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10
++#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000
++#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12
++#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000
++#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8
++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3
++#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10
++#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000
++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10
++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000
++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14
++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000
++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16
++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000
++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18
++#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000
++#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a
++#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000
++#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c
++#define PLL_CNTL__PLL_RESET_MASK 0x1
++#define PLL_CNTL__PLL_RESET__SHIFT 0x0
++#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
++#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1
++#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4
++#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
++#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8
++#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3
++#define PLL_CNTL__PLL_VCOREF_MASK 0x30
++#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4
++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40
++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6
++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80
++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7
++#define PLL_CNTL__PLL_CALREF_MASK 0x300
++#define PLL_CNTL__PLL_CALREF__SHIFT 0x8
++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400
++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa
++#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800
++#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb
++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000
++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd
++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000
++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe
++#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000
++#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10
++#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000
++#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13
++#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000
++#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14
++#define PLL_CNTL__PLL_LOCKED_MASK 0x200000
++#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15
++#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000
++#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16
++#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000
++#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17
++#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000
++#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18
++#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000
++#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a
++#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f
++#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0
++#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60
++#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5
++#define PLL_ANALOG__PLL_CP_MASK 0xf00
++#define PLL_ANALOG__PLL_CP__SHIFT 0x8
++#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000
++#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc
++#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000
++#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15
++#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000
++#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18
++#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff
++#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0
++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000
++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14
++#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000
++#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a
++#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000
++#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100
++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8
++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1
++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0
++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0
++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4
++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00
++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000
++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b
++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1
++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0
++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1
++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0
++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100
++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8
++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000
++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1
++#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1
++#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00
++#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8
++#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000
++#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000
++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a
++#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000
++#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c
++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1
++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0
++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e
++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1
++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0
++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5
++#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00
++#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9
++#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000
++#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe
++#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000
++#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11
++#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000
++#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12
++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff
++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0
++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff
++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0
++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff
++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000
++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10
++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f
++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000
++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18
++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f
++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000
++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18
++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f
++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000
++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18
++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1
++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0
++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0
++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4
++#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1
++#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0
++#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2
++#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80
++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7
++#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff
++#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0
++#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000
++#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10
++#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000
++#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000
++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a
++#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f
++#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0
++#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff
++#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0
++#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff
++#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000
++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000
++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000
++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000
++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000
++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17
++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000
++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18
++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000
++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000
++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0
++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1
++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc
++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000
++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000
++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a
++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000
++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0
++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc
++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc
++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000
++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d
++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff
++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000
++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000
++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19
++#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000
++#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000
++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000
++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a
++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff
++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0
++#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1
++#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0
++#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2
++#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb
++#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000
++#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14
++#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000
++#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15
++#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000
++#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000
++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17
++#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000
++#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18
++#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000
++#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a
++#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000
++#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b
++#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000
++#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11
++#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000
++#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000
++#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c
++#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000
++#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000
++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000
++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe
++#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000
++#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf
++#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000
++#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14
++#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000
++#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19
++#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff
++#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0
++#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000
++#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16
++#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1
++#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0
++#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2
++#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1
++#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4
++#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2
++#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8
++#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3
++#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10
++#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4
++#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20
++#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5
++#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40
++#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6
++#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80
++#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000
++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f
++#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1
++#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0
++#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2
++#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1
++#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4
++#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2
++#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78
++#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3
++#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780
++#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7
++#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800
++#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb
++#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff
++#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000
++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11
++#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff
++#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0
++#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000
++#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc
++#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000
++#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16
++#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000
++#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19
++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
++#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
++#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
++#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
++#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
++#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
++#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
++#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
++#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
++#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
++#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
++#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
++#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
++#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
++#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
++#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
++#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
++#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
++#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
++#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
++#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
++#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
++#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
++#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
++#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
++#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
++#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
++#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
++#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
++#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
++#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
++#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
++#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
++#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
++#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
++#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
++#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
++#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
++#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
++#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
++#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
++#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
++#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
++#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
++#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
++#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
++#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
++#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
++#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
++#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
++#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
++#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
++#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
++#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f
++#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0
++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0
++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
++#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
++#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
++#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
++#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
++#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
++#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
++#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
++#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
++#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
++#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff
++#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0
++#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1
++#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
++#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2
++#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
++#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4
++#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
++#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8
++#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
++#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10
++#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
++#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20
++#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
++#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40
++#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6
++#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80
++#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7
++#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100
++#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8
++#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200
++#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9
++#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400
++#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
++#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800
++#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb
++#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000
++#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc
++#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000
++#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd
++#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000
++#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe
++#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000
++#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf
++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
++#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1
++#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
++#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2
++#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
++#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4
++#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
++#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8
++#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
++#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10
++#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
++#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20
++#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
++#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40
++#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6
++#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80
++#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7
++#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100
++#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8
++#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200
++#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9
++#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400
++#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
++#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800
++#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb
++#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000
++#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc
++#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000
++#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd
++#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000
++#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe
++#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000
++#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf
++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
++#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40
++#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6
++#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80
++#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7
++#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100
++#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8
++#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200
++#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9
++#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400
++#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
++#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800
++#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb
++#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000
++#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc
++#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000
++#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd
++#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000
++#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe
++#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000
++#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
++#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_MASK 0x3
++#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
++#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
++#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
++#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
++#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
++#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
++#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
++#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
++#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
++#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
++#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
++#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1
++#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
++#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
++#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
++#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
++#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
++#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
++#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
++#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
++#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1
++#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100
++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100
++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100
++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
++#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
++#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLND_CONTROL__BLND_MODE_MASK 0x300
++#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
++#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
++#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
++#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
++#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
++#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
++#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLND_SM_CONTROL2__SM_MODE_MASK 0x7
++#define BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
++#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
++#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
++#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1
++#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
++#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
++#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
++#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
++#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
++#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
++#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
++#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
++#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
++#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
++#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
++#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
++#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
++#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
++#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
++#define WB_ENABLE__WB_ENABLE_MASK 0x1
++#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
++#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40
++#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6
++#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80
++#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7
++#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100
++#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
++#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
++#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000
++#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
++#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000
++#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
++#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000
++#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
++#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
++#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
++#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000
++#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
++#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000
++#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
++#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
++#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
++#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
++#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
++#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
++#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
++#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
++#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
++#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
++#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1
++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
++#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
++#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
++#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
++#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
++#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
++#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
++#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
++#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
++#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
++#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
++#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
++#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
++#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
++#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
++#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
++#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
++#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
++#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
++#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
++#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
++#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
++#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
++#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
++#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1
++#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0
++#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0
++#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
++#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1
++#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
++#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2
++#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
++#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4
++#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
++#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8
++#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100
++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000
++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
++#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff
++#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3
++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c
++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
++#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1
++#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
++#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
++#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x8000
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE_MASK 0x20000
++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE__SHIFT 0x11
++#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000
++#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
++#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000
++#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2
++#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4
++#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8
++#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
++#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
++#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x20
++#define DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
++#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET_MASK 0x40
++#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET__SHIFT 0x6
++#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1
++#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0
++#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0
++#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4
++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20
++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100
++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000
++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000
++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000
++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000
++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000
++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
++#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3
++#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc
++#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
++#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300
++#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
++#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00
++#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000
++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000
++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
++#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
++#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
++#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc
++#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30
++#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300
++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
++#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00
++#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
++#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000
++#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
++#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000
++#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
++#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000
++#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
++#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
++#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
++#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000
++#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
++#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000
++#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
++#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x1
++#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8
++#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000
++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
++#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000
++#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000
++#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
++#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1
++#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
++#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2
++#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
++#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4
++#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
++#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8
++#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
++#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
++#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
++#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20
++#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
++#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40
++#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000
++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0
++#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800
++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000
++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK 0x3
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT 0x0
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK 0x4
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT 0x2
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x18
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x20
++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0xc0
++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x100
++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x600
++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x800
++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x3000
++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x4000
++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x18000
++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x20000
++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK 0x3
++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0xc
++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
++#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
++#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
++#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0xc0
++#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
++#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK 0x3
++#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT 0x0
++#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0xc
++#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
++#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x30
++#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
++#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0xc0
++#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
++#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x300
++#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
++#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0xc00
++#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
++#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x3000
++#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK 0xf
++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT 0x0
++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK 0x10
++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT 0x4
++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK 0x20
++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT 0x5
++#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x1
++#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
++#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1
++#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10
++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
++#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100
++#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000
++#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000
++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
++#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff
++#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
++#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000
++#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
++#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000
++#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000
++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
++#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff
++#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
++#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff
++#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
++#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff
++#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
++#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff
++#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
++#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff
++#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
++#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff
++#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
++#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff
++#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
++#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff
++#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x400
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x800
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb
++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1
++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4
++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8
++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10
++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20
++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40
++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80
++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100
++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200
++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00
++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000
++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000
++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000
++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000
++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000
++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000
++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
++#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x1
++#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0
++#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x2
++#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1
++#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0xc00
++#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa
++#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x3000
++#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2
++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10
++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20
++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40
++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80
++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100
++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200
++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400
++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000
++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000
++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000
++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000
++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000
++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000
++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000
++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3
++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
++#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x4
++#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2
++#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x8
++#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x30000
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x40000
++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x180000
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x200000
++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400
++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x400000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x800000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
++#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x7f
++#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0
++#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x80
++#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
++#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x100
++#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x200
++#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x400
++#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x800
++#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
++#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x1000
++#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
++#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x2000
++#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x8000
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x10000
++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x20000
++#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
++#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x40000
++#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x80000
++#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
++#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x100000
++#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
++#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x200000
++#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
++#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x400000
++#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
++#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x800000
++#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
++#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x2000000
++#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19
++#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x4000000
++#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a
++#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x1
++#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
++#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x2
++#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
++#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x4
++#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
++#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x8
++#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
++#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x10
++#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
++#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x20
++#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
++#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x40
++#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
++#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x100
++#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8
++#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x200
++#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9
++#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x400
++#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
++#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x800
++#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
++#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x1000
++#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
++#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x2000
++#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
++#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x4000
++#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
++#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x8000
++#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
++#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x10000
++#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
++#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x40000
++#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12
++#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x80000
++#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13
++#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1
++#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0
++#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2
++#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1
++#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10
++#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4
++#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100
++#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8
++#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000
++#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000
++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
++#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
++#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
++#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000
++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
++#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
++#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
++#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
++#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
++#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
++#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
++#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
++#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
++#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
++#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
++#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
++#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
++#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000
++#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f
++#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x1
++#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0
++#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x2
++#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1
++#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x10
++#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4
++#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x20
++#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5
++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0
++#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
++#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
++#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
++#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
++#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
++#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
++#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
++#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
++#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
++#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
++#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
++#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
++#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
++#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000
++#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000
++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300
++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
++#define BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
++#define BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
++#define BLNDV_CONTROL__BLND_MODE_MASK 0x300
++#define BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
++#define BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
++#define BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
++#define BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
++#define BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
++#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
++#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
++#define BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
++#define BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
++#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
++#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
++#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
++#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
++#define BLNDV_SM_CONTROL2__SM_MODE_MASK 0x7
++#define BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
++#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
++#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
++#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
++#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
++#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
++#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
++#define BLNDV_CONTROL2__PTI_ENABLE_MASK 0x1
++#define BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
++#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
++#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
++#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
++#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
++#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
++#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
++#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
++#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
++#define BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
++#define BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
++#define BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
++#define BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
++#define BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
++#define BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
++#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
++#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
++#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
++#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
++#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
++#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
++#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
++#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
++#define BLNDV_DEBUG__BLND_DEBUG_MASK 0xfffffffe
++#define BLNDV_DEBUG__BLND_DEBUG__SHIFT 0x1
++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
++#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
++#define CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
++#define CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
++#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
++#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
++#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
++#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
++#define CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
++#define CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
++#define CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
++#define CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
++#define CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
++#define CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
++#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
++#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
++#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
++#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
++#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
++#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
++#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
++#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
++#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
++#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
++#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
++#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
++#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
++#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
++#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
++#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
++#define CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x1
++#define CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
++#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
++#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
++#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
++#define CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
++#define CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
++#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
++#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
++#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
++#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
++#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
++#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
++#define CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
++#define CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
++#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
++#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
++#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
++#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
++#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
++#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
++#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
++#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
++#define CRTCV_STATUS__CRTC_V_BLANK_MASK 0x1
++#define CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
++#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
++#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
++#define CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x4
++#define CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
++#define CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x8
++#define CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
++#define CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x10
++#define CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
++#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
++#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
++#define CRTCV_STATUS__CRTC_H_BLANK_MASK 0x10000
++#define CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
++#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
++#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
++#define CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x40000
++#define CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
++#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
++#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
++#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
++#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
++#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
++#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
++#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
++#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
++#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
++#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
++#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
++#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
++#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
++#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
++#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
++#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
++#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
++#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
++#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
++#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
++#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
++#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
++#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
++#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
++#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
++#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2
++#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
++#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4
++#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
++#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100
++#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
++#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
++#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
++#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
++#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
++#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
++#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
++#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
++#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
++#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
++#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
++#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000
++#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
++#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
++#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
++#define CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
++#define CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
++#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
++#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
++#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
++#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
++#define CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
++#define CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
++#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
++#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
++#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
++#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
++#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
++#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
++#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
++#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
++#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
++#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
++#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
++#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
++#define CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
++#define CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
++#define CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
++#define CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
++#define CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
++#define CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
++#define CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
++#define CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
++#define CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
++#define CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
++#define CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
++#define CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
++#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
++#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000
++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
++#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
++#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400
++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa
++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000
++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
++#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000
++#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18
++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
++
++#endif /* DCE_11_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-tty-driver_enable_UART_support-1.0.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-tty-driver_enable_UART_support-1.0.patch
new file mode 100644
index 00000000..69134c0c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-tty-driver_enable_UART_support-1.0.patch
@@ -0,0 +1,46 @@
+From 5e8be0ace8901c35e63bef54f1864566346bcec7 Mon Sep 17 00:00:00 2001
+From: Ken Xue <Ken.Xue@amd.com>
+Date: Thu, 6 Nov 2014 09:37:28 +0800
+Subject: [PATCH 3/6] enable UART support based on driver from IP vendor.
+
+Signed-off-by: Ken Xue <Ken.Xue@amd.com>
+Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com>
+---
+ drivers/acpi/acpi_apd.c           | 11 +++++++++--
+ drivers/tty/serial/8250/8250_dw.c |  1 +
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+diff -Naur a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
+--- a/drivers/acpi/acpi_apd.c	2015-03-25 15:43:23.040812663 +0530
++++ b/drivers/acpi/acpi_apd.c	2015-03-25 15:41:26.028810368 +0530
+@@ -48,11 +48,18 @@
+ 	.rate = 136192000, /*(133 * 1024 * 1000)*/
+ };
+ 
++static struct apd_device_desc amd_uart_desc = {
++        .clk_required = true,
++        .fix_rate_root_clock = true,
++        .clk_name = "uart_clk",
++        .rate = 48000000,
++};
++
+ static const struct acpi_device_id acpi_apd_device_ids[] = {
+ 	/* Generic apd devices */
+ 	{ "AMD0010", (unsigned long)&amd_i2c_desc },
+-	/*{ "UART0000, (unsigned long)&amur_uart_dev_desc },*/
+-	/*{"AMD0030", (unsigned long)&amur_gpio_dev_desc },*/
++	{ "AMD0020", (unsigned long)&amd_uart_desc },
++	/*{"AMD0030", (unsigned long)&amd_gpio_desc },*/
+ 	{ }
+ };
+ 
+diff -Naur a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
+--- a/drivers/tty/serial/8250/8250_dw.c	2015-03-25 14:39:54.696737985 +0530
++++ b/drivers/tty/serial/8250/8250_dw.c	2015-03-25 15:41:26.028810368 +0530
+@@ -451,6 +451,7 @@
+ 	{ "INT3434", 0 },
+ 	{ "INT3435", 0 },
+ 	{ "80860F0A", 0 },
++	{ "AMD0020", 0 },
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0007-yocto-amd-backport-kernel-dependencies-for-amdgpu-driver.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0007-yocto-amd-backport-kernel-dependencies-for-amdgpu-driver.patch
new file mode 100644
index 00000000..d2bcdaca
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0007-yocto-amd-backport-kernel-dependencies-for-amdgpu-driver.patch
@@ -0,0 +1,35302 @@
+Backport of kernel dependencies for amdgpu driver to yocto
+kernel v3.14.24. The amdgpu driver will need these dependencies
+to be resolved before it can be compiled without any issues.
+
+Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com>
+diff -Naur a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
+--- a/arch/x86/include/asm/cpufeature.h	2015-03-26 14:43:28.362436395 +0530
++++ b/arch/x86/include/asm/cpufeature.h	2015-03-26 14:42:37.686435401 +0530
+@@ -37,7 +37,7 @@
+ #define X86_FEATURE_PAT		(0*32+16) /* Page Attribute Table */
+ #define X86_FEATURE_PSE36	(0*32+17) /* 36-bit PSEs */
+ #define X86_FEATURE_PN		(0*32+18) /* Processor serial number */
+-#define X86_FEATURE_CLFLSH	(0*32+19) /* "clflush" CLFLUSH instruction */
++#define X86_FEATURE_CLFLUSH	(0*32+19) /* "clflush" CLFLUSH instruction */
+ #define X86_FEATURE_DS		(0*32+21) /* "dts" Debug Store */
+ #define X86_FEATURE_ACPI	(0*32+22) /* ACPI via MSR */
+ #define X86_FEATURE_MMX		(0*32+23) /* Multimedia Extensions */
+@@ -224,6 +224,8 @@
+ #define X86_FEATURE_AVX512PF	(9*32+26) /* AVX-512 Prefetch */
+ #define X86_FEATURE_AVX512ER	(9*32+27) /* AVX-512 Exponential and Reciprocal */
+ #define X86_FEATURE_AVX512CD	(9*32+28) /* AVX-512 Conflict Detection */
++#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
++
+ 
+ /*
+  * BUG word(s)
+@@ -317,7 +319,7 @@
+ #define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)
+ #define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)
+ #define cpu_has_pebs		boot_cpu_has(X86_FEATURE_PEBS)
+-#define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
++#define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLUSH)
+ #define cpu_has_bts		boot_cpu_has(X86_FEATURE_BTS)
+ #define cpu_has_gbpages		boot_cpu_has(X86_FEATURE_GBPAGES)
+ #define cpu_has_arch_perfmon	boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
+diff -Naur a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
+--- a/arch/x86/include/asm/disabled-features.h	1970-01-01 05:30:00.000000000 +0530
++++ b/arch/x86/include/asm/disabled-features.h	2015-03-26 14:42:37.686435401 +0530
+@@ -0,0 +1,45 @@
++#ifndef _ASM_X86_DISABLED_FEATURES_H
++#define _ASM_X86_DISABLED_FEATURES_H
++
++/* These features, although they might be available in a CPU
++ * will not be used because the compile options to support
++ * them are not present.
++ *
++ * This code allows them to be checked and disabled at
++ * compile time without an explicit #ifdef.  Use
++ * cpu_feature_enabled().
++ */
++
++#ifdef CONFIG_X86_INTEL_MPX
++# define DISABLE_MPX	0
++#else
++# define DISABLE_MPX	(1<<(X86_FEATURE_MPX & 31))
++#endif
++
++#ifdef CONFIG_X86_64
++# define DISABLE_VME		(1<<(X86_FEATURE_VME & 31))
++# define DISABLE_K6_MTRR	(1<<(X86_FEATURE_K6_MTRR & 31))
++# define DISABLE_CYRIX_ARR	(1<<(X86_FEATURE_CYRIX_ARR & 31))
++# define DISABLE_CENTAUR_MCR	(1<<(X86_FEATURE_CENTAUR_MCR & 31))
++#else
++# define DISABLE_VME		0
++# define DISABLE_K6_MTRR	0
++# define DISABLE_CYRIX_ARR	0
++# define DISABLE_CENTAUR_MCR	0
++#endif /* CONFIG_X86_64 */
++
++/*
++ * Make sure to add features to the correct mask
++ */
++#define DISABLED_MASK0	(DISABLE_VME)
++#define DISABLED_MASK1	0
++#define DISABLED_MASK2	0
++#define DISABLED_MASK3	(DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR)
++#define DISABLED_MASK4	0
++#define DISABLED_MASK5	0
++#define DISABLED_MASK6	0
++#define DISABLED_MASK7	0
++#define DISABLED_MASK8	0
++#define DISABLED_MASK9	(DISABLE_MPX)
++
++#endif /* _ASM_X86_DISABLED_FEATURES_H */
+diff -Naur a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
+--- a/arch/x86/include/asm/special_insns.h	2015-03-26 14:43:28.362436395 +0530
++++ b/arch/x86/include/asm/special_insns.h	2015-03-26 14:42:37.686435401 +0530
+@@ -191,6 +191,14 @@
+ 	asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
+ }
+ 
++static inline void clflushopt(volatile void *__p)
++{
++	alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
++		       ".byte 0x66; clflush %P0",
++		       X86_FEATURE_CLFLUSHOPT,
++		       "+m" (*(volatile char __force *)__p));
++}
++
+ #define nop() asm volatile ("nop")
+ 
+ 
+diff -Naur a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
+--- a/arch/x86/kernel/cpu/common.c	2015-03-26 14:43:28.394436396 +0530
++++ b/arch/x86/kernel/cpu/common.c	2015-03-26 14:42:37.686435401 +0530
+@@ -1025,7 +1025,7 @@
+ 
+ static __init int setup_noclflush(char *arg)
+ {
+-	setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
++	setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
+ 	return 1;
+ }
+ __setup("noclflush", setup_noclflush);
+diff -Naur a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
+--- a/arch/x86/kernel/smpboot.c	2015-03-26 14:43:28.398436396 +0530
++++ b/arch/x86/kernel/smpboot.c	2015-03-26 14:42:37.686435401 +0530
+@@ -1389,7 +1389,7 @@
+ 
+ 	if (!this_cpu_has(X86_FEATURE_MWAIT))
+ 		return;
+-	if (!this_cpu_has(X86_FEATURE_CLFLSH))
++	if (!this_cpu_has(X86_FEATURE_CLFLUSH))
+ 		return;
+ 	if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
+ 		return;
+diff -Naur a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
+--- a/arch/x86/kvm/cpuid.c	2015-03-26 14:43:28.430436396 +0530
++++ b/arch/x86/kvm/cpuid.c	2015-03-26 14:42:37.690435401 +0530
+@@ -263,7 +263,7 @@
+ 		F(TSC) | F(MSR) | F(PAE) | F(MCE) |
+ 		F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
+ 		F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
+-		F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
++		F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
+ 		0 /* Reserved, DS, ACPI */ | F(MMX) |
+ 		F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
+ 		0 /* HTT, TM, Reserved, PBE */;
+diff -Naur a/Documentation/atomic_ops.txt b/Documentation/atomic_ops.txt
+--- a/Documentation/atomic_ops.txt	2015-03-26 14:43:29.098436410 +0530
++++ b/Documentation/atomic_ops.txt	2015-03-26 14:42:37.690435401 +0530
+@@ -7,12 +7,13 @@
+ maintainers on how to implement atomic counter, bitops, and spinlock
+ interfaces properly.
+ 
+-	The atomic_t type should be defined as a signed integer.
+-Also, it should be made opaque such that any kind of cast to a normal
+-C integer type will fail.  Something like the following should
+-suffice:
++	The atomic_t type should be defined as a signed integer and
++the atomic_long_t type as a signed long integer.  Also, they should
++be made opaque such that any kind of cast to a normal C integer type
++will fail.  Something like the following should suffice:
+ 
+ 	typedef struct { int counter; } atomic_t;
++	typedef struct { long counter; } atomic_long_t;
+ 
+ Historically, counter has been declared volatile.  This is now discouraged.
+ See Documentation/volatile-considered-harmful.txt for the complete rationale.
+@@ -37,6 +38,9 @@
+ proper implicit or explicit read memory barrier is needed before reading the
+ value with atomic_read from another thread.
+ 
++As with all of the atomic_ interfaces, replace the leading "atomic_"
++with "atomic_long_" to operate on atomic_long_t.
++
+ The second interface can be used at runtime, as in:
+ 
+ 	struct foo { atomic_t counter; };
+@@ -285,15 +289,13 @@
+ operation which does not return a value, a set of interfaces are
+ defined which accomplish this:
+ 
+-	void smp_mb__before_atomic_dec(void);
+-	void smp_mb__after_atomic_dec(void);
+-	void smp_mb__before_atomic_inc(void);
+-	void smp_mb__after_atomic_inc(void);
++	void smp_mb__before_atomic(void);
++	void smp_mb__after_atomic(void);
+ 
+-For example, smp_mb__before_atomic_dec() can be used like so:
++For example, smp_mb__before_atomic() can be used like so:
+ 
+ 	obj->dead = 1;
+-	smp_mb__before_atomic_dec();
++	smp_mb__before_atomic();
+ 	atomic_dec(&obj->ref_count);
+ 
+ It makes sure that all memory operations preceding the atomic_dec()
+@@ -302,15 +304,10 @@
+ "1" to obj->dead will be globally visible to other cpus before the
+ atomic counter decrement.
+ 
+-Without the explicit smp_mb__before_atomic_dec() call, the
++Without the explicit smp_mb__before_atomic() call, the
+ implementation could legally allow the atomic counter update visible
+ to other cpus before the "obj->dead = 1;" assignment.
+ 
+-The other three interfaces listed are used to provide explicit
+-ordering with respect to memory operations after an atomic_dec() call
+-(smp_mb__after_atomic_dec()) and around atomic_inc() calls
+-(smp_mb__{before,after}_atomic_inc()).
+-
+ A missing memory barrier in the cases where they are required by the
+ atomic_t implementation above can have disastrous results.  Here is
+ an example, which follows a pattern occurring frequently in the Linux
+@@ -487,12 +484,12 @@
+ Which returns a boolean indicating if bit "nr" is set in the bitmask
+ pointed to by "addr".
+ 
+-If explicit memory barriers are required around clear_bit() (which
+-does not return a value, and thus does not need to provide memory
+-barrier semantics), two interfaces are provided:
++If explicit memory barriers are required around {set,clear}_bit() (which do
++not return a value, and thus does not need to provide memory barrier
++semantics), two interfaces are provided:
+ 
+-	void smp_mb__before_clear_bit(void);
+-	void smp_mb__after_clear_bit(void);
++	void smp_mb__before_atomic(void);
++	void smp_mb__after_atomic(void);
+ 
+ They are used as follows, and are akin to their atomic_t operation
+ brothers:
+@@ -500,13 +497,13 @@
+ 	/* All memory operations before this call will
+ 	 * be globally visible before the clear_bit().
+ 	 */
+-	smp_mb__before_clear_bit();
++	smp_mb__before_atomic();
+ 	clear_bit( ... );
+ 
+ 	/* The clear_bit() will be visible before all
+ 	 * subsequent memory operations.
+ 	 */
+-	 smp_mb__after_clear_bit();
++	 smp_mb__after_atomic();
+ 
+ There are two special bitops with lock barrier semantics (acquire/release,
+ same as spinlocks). These operate in the same way as their non-_lock/unlock
+diff -Naur a/drivers/acpi/video.c b/drivers/acpi/video.c
+--- a/drivers/acpi/video.c	2015-03-26 14:43:30.918436445 +0530
++++ b/drivers/acpi/video.c	2015-03-26 14:42:37.690435401 +0530
+@@ -240,13 +240,14 @@
+ 		return use_native_backlight_dmi;
+ }
+ 
+-static bool acpi_video_verify_backlight_support(void)
++bool acpi_video_verify_backlight_support(void)
+ {
+ 	if (acpi_osi_is_win8() && acpi_video_use_native_backlight() &&
+ 	    backlight_device_registered(BACKLIGHT_RAW))
+ 		return false;
+ 	return acpi_video_backlight_support();
+ }
++EXPORT_SYMBOL_GPL(acpi_video_verify_backlight_support);
+ 
+ /* backlight device sysfs support */
+ static int acpi_video_get_brightness(struct backlight_device *bd)
+diff -Naur a/drivers/base/fence.c b/drivers/base/fence.c
+--- a/drivers/base/fence.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/base/fence.c	2015-03-26 14:42:37.690435401 +0530
+@@ -0,0 +1,431 @@
++/*
++ * Fence mechanism for dma-buf and to allow for asynchronous dma access
++ *
++ * Copyright (C) 2012 Canonical Ltd
++ * Copyright (C) 2012 Texas Instruments
++ *
++ * Authors:
++ * Rob Clark <robdclark@gmail.com>
++ * Maarten Lankhorst <maarten.lankhorst@canonical.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ */
++
++#include <linux/slab.h>
++#include <linux/export.h>
++#include <linux/atomic.h>
++#include <linux/fence.h>
++
++#define CREATE_TRACE_POINTS
++#include <trace/events/fence.h>
++
++EXPORT_TRACEPOINT_SYMBOL(fence_annotate_wait_on);
++EXPORT_TRACEPOINT_SYMBOL(fence_emit);
++
++/*
++ * fence context counter: each execution context should have its own
++ * fence context, this allows checking if fences belong to the same
++ * context or not. One device can have multiple separate contexts,
++ * and they're used if some engine can run independently of another.
++ */
++static atomic_t fence_context_counter = ATOMIC_INIT(0);
++
++/**
++ * fence_context_alloc - allocate an array of fence contexts
++ * @num:	[in]	amount of contexts to allocate
++ *
++ * This function will return the first index of the number of fences allocated.
++ * The fence context is used for setting fence->context to a unique number.
++ */
++unsigned fence_context_alloc(unsigned num)
++{
++	BUG_ON(!num);
++	return atomic_add_return(num, &fence_context_counter) - num;
++}
++EXPORT_SYMBOL(fence_context_alloc);
++
++/**
++ * fence_signal_locked - signal completion of a fence
++ * @fence: the fence to signal
++ *
++ * Signal completion for software callbacks on a fence, this will unblock
++ * fence_wait() calls and run all the callbacks added with
++ * fence_add_callback(). Can be called multiple times, but since a fence
++ * can only go from unsignaled to signaled state, it will only be effective
++ * the first time.
++ *
++ * Unlike fence_signal, this function must be called with fence->lock held.
++ */
++int fence_signal_locked(struct fence *fence)
++{
++	struct fence_cb *cur, *tmp;
++	int ret = 0;
++
++	if (WARN_ON(!fence))
++		return -EINVAL;
++
++	if (!ktime_to_ns(fence->timestamp)) {
++		fence->timestamp = ktime_get();
++		smp_mb__before_atomic_inc();
++	}
++
++	if (test_and_set_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
++		ret = -EINVAL;
++
++		/*
++		 * we might have raced with the unlocked fence_signal,
++		 * still run through all callbacks
++		 */
++	} else
++		trace_fence_signaled(fence);
++
++	list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
++		list_del_init(&cur->node);
++		cur->func(fence, cur);
++	}
++	return ret;
++}
++EXPORT_SYMBOL(fence_signal_locked);
++
++/**
++ * fence_signal - signal completion of a fence
++ * @fence: the fence to signal
++ *
++ * Signal completion for software callbacks on a fence, this will unblock
++ * fence_wait() calls and run all the callbacks added with
++ * fence_add_callback(). Can be called multiple times, but since a fence
++ * can only go from unsignaled to signaled state, it will only be effective
++ * the first time.
++ */
++int fence_signal(struct fence *fence)
++{
++	unsigned long flags;
++
++	if (!fence)
++		return -EINVAL;
++
++	if (!ktime_to_ns(fence->timestamp)) {
++		fence->timestamp = ktime_get();
++		smp_mb__before_atomic_inc();
++	}
++
++	if (test_and_set_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
++		return -EINVAL;
++
++	trace_fence_signaled(fence);
++
++	if (test_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) {
++		struct fence_cb *cur, *tmp;
++
++		spin_lock_irqsave(fence->lock, flags);
++		list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
++			list_del_init(&cur->node);
++			cur->func(fence, cur);
++		}
++		spin_unlock_irqrestore(fence->lock, flags);
++	}
++	return 0;
++}
++EXPORT_SYMBOL(fence_signal);
++
++/**
++ * fence_wait_timeout - sleep until the fence gets signaled
++ * or until timeout elapses
++ * @fence:	[in]	the fence to wait on
++ * @intr:	[in]	if true, do an interruptible wait
++ * @timeout:	[in]	timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
++ *
++ * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
++ * remaining timeout in jiffies on success. Other error values may be
++ * returned on custom implementations.
++ *
++ * Performs a synchronous wait on this fence. It is assumed the caller
++ * directly or indirectly (buf-mgr between reservation and committing)
++ * holds a reference to the fence, otherwise the fence might be
++ * freed before return, resulting in undefined behavior.
++ */
++signed long
++fence_wait_timeout(struct fence *fence, bool intr, signed long timeout)
++{
++	signed long ret;
++
++	if (WARN_ON(timeout < 0))
++		return -EINVAL;
++
++	trace_fence_wait_start(fence);
++	ret = fence->ops->wait(fence, intr, timeout);
++	trace_fence_wait_end(fence);
++	return ret;
++}
++EXPORT_SYMBOL(fence_wait_timeout);
++
++void fence_release(struct kref *kref)
++{
++	struct fence *fence =
++			container_of(kref, struct fence, refcount);
++
++	trace_fence_destroy(fence);
++
++	BUG_ON(!list_empty(&fence->cb_list));
++
++	if (fence->ops->release)
++		fence->ops->release(fence);
++	else
++		fence_free(fence);
++}
++EXPORT_SYMBOL(fence_release);
++
++void fence_free(struct fence *fence)
++{
++	kfree_rcu(fence, rcu);
++}
++EXPORT_SYMBOL(fence_free);
++
++/**
++ * fence_enable_sw_signaling - enable signaling on fence
++ * @fence:	[in]	the fence to enable
++ *
++ * this will request for sw signaling to be enabled, to make the fence
++ * complete as soon as possible
++ */
++void fence_enable_sw_signaling(struct fence *fence)
++{
++	unsigned long flags;
++
++	if (!test_and_set_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags) &&
++	    !test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
++		trace_fence_enable_signal(fence);
++
++		spin_lock_irqsave(fence->lock, flags);
++
++		if (!fence->ops->enable_signaling(fence))
++			fence_signal_locked(fence);
++
++		spin_unlock_irqrestore(fence->lock, flags);
++	}
++}
++EXPORT_SYMBOL(fence_enable_sw_signaling);
++
++/**
++ * fence_add_callback - add a callback to be called when the fence
++ * is signaled
++ * @fence:	[in]	the fence to wait on
++ * @cb:		[in]	the callback to register
++ * @func:	[in]	the function to call
++ *
++ * cb will be initialized by fence_add_callback, no initialization
++ * by the caller is required. Any number of callbacks can be registered
++ * to a fence, but a callback can only be registered to one fence at a time.
++ *
++ * Note that the callback can be called from an atomic context.  If
++ * fence is already signaled, this function will return -ENOENT (and
++ * *not* call the callback)
++ *
++ * Add a software callback to the fence. Same restrictions apply to
++ * refcount as it does to fence_wait, however the caller doesn't need to
++ * keep a refcount to fence afterwards: when software access is enabled,
++ * the creator of the fence is required to keep the fence alive until
++ * after it signals with fence_signal. The callback itself can be called
++ * from irq context.
++ *
++ */
++int fence_add_callback(struct fence *fence, struct fence_cb *cb,
++		       fence_func_t func)
++{
++	unsigned long flags;
++	int ret = 0;
++	bool was_set;
++
++	if (WARN_ON(!fence || !func))
++		return -EINVAL;
++
++	if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
++		INIT_LIST_HEAD(&cb->node);
++		return -ENOENT;
++	}
++
++	spin_lock_irqsave(fence->lock, flags);
++
++	was_set = test_and_set_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags);
++
++	if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
++		ret = -ENOENT;
++	else if (!was_set) {
++		trace_fence_enable_signal(fence);
++
++		if (!fence->ops->enable_signaling(fence)) {
++			fence_signal_locked(fence);
++			ret = -ENOENT;
++		}
++	}
++
++	if (!ret) {
++		cb->func = func;
++		list_add_tail(&cb->node, &fence->cb_list);
++	} else
++		INIT_LIST_HEAD(&cb->node);
++	spin_unlock_irqrestore(fence->lock, flags);
++
++	return ret;
++}
++EXPORT_SYMBOL(fence_add_callback);
++
++/**
++ * fence_remove_callback - remove a callback from the signaling list
++ * @fence:	[in]	the fence to wait on
++ * @cb:		[in]	the callback to remove
++ *
++ * Remove a previously queued callback from the fence. This function returns
++ * true if the callback is successfully removed, or false if the fence has
++ * already been signaled.
++ *
++ * *WARNING*:
++ * Cancelling a callback should only be done if you really know what you're
++ * doing, since deadlocks and race conditions could occur all too easily. For
++ * this reason, it should only ever be done on hardware lockup recovery,
++ * with a reference held to the fence.
++ */
++bool
++fence_remove_callback(struct fence *fence, struct fence_cb *cb)
++{
++	unsigned long flags;
++	bool ret;
++
++	spin_lock_irqsave(fence->lock, flags);
++
++	ret = !list_empty(&cb->node);
++	if (ret)
++		list_del_init(&cb->node);
++
++	spin_unlock_irqrestore(fence->lock, flags);
++
++	return ret;
++}
++EXPORT_SYMBOL(fence_remove_callback);
++
++struct default_wait_cb {
++	struct fence_cb base;
++	struct task_struct *task;
++};
++
++static void
++fence_default_wait_cb(struct fence *fence, struct fence_cb *cb)
++{
++	struct default_wait_cb *wait =
++		container_of(cb, struct default_wait_cb, base);
++
++	wake_up_state(wait->task, TASK_NORMAL);
++}
++
++/**
++ * fence_default_wait - default sleep until the fence gets signaled
++ * or until timeout elapses
++ * @fence:	[in]	the fence to wait on
++ * @intr:	[in]	if true, do an interruptible wait
++ * @timeout:	[in]	timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
++ *
++ * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
++ * remaining timeout in jiffies on success.
++ */
++signed long
++fence_default_wait(struct fence *fence, bool intr, signed long timeout)
++{
++	struct default_wait_cb cb;
++	unsigned long flags;
++	signed long ret = timeout;
++	bool was_set;
++
++	if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
++		return timeout;
++
++	spin_lock_irqsave(fence->lock, flags);
++
++	if (intr && signal_pending(current)) {
++		ret = -ERESTARTSYS;
++		goto out;
++	}
++
++	was_set = test_and_set_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags);
++
++	if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
++		goto out;
++
++	if (!was_set) {
++		trace_fence_enable_signal(fence);
++
++		if (!fence->ops->enable_signaling(fence)) {
++			fence_signal_locked(fence);
++			goto out;
++		}
++	}
++
++	cb.base.func = fence_default_wait_cb;
++	cb.task = current;
++	list_add(&cb.base.node, &fence->cb_list);
++
++	while (!test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) {
++		if (intr)
++			__set_current_state(TASK_INTERRUPTIBLE);
++		else
++			__set_current_state(TASK_UNINTERRUPTIBLE);
++		spin_unlock_irqrestore(fence->lock, flags);
++
++		ret = schedule_timeout(ret);
++
++		spin_lock_irqsave(fence->lock, flags);
++		if (ret > 0 && intr && signal_pending(current))
++			ret = -ERESTARTSYS;
++	}
++
++	if (!list_empty(&cb.base.node))
++		list_del(&cb.base.node);
++	__set_current_state(TASK_RUNNING);
++
++out:
++	spin_unlock_irqrestore(fence->lock, flags);
++	return ret;
++}
++EXPORT_SYMBOL(fence_default_wait);
++
++/**
++ * fence_init - Initialize a custom fence.
++ * @fence:	[in]	the fence to initialize
++ * @ops:	[in]	the fence_ops for operations on this fence
++ * @lock:	[in]	the irqsafe spinlock to use for locking this fence
++ * @context:	[in]	the execution context this fence is run on
++ * @seqno:	[in]	a linear increasing sequence number for this context
++ *
++ * Initializes an allocated fence, the caller doesn't have to keep its
++ * refcount after committing with this fence, but it will need to hold a
++ * refcount again if fence_ops.enable_signaling gets called. This can
++ * be used for other implementing other types of fence.
++ *
++ * context and seqno are used for easy comparison between fences, allowing
++ * to check which fence is later by simply using fence_later.
++ */
++void
++fence_init(struct fence *fence, const struct fence_ops *ops,
++	     spinlock_t *lock, unsigned context, unsigned seqno)
++{
++	BUG_ON(!lock);
++	BUG_ON(!ops || !ops->wait || !ops->enable_signaling ||
++	       !ops->get_driver_name || !ops->get_timeline_name);
++
++	kref_init(&fence->refcount);
++	fence->ops = ops;
++	INIT_LIST_HEAD(&fence->cb_list);
++	fence->lock = lock;
++	fence->context = context;
++	fence->seqno = seqno;
++	fence->flags = 0UL;
++
++	trace_fence_init(fence);
++}
++EXPORT_SYMBOL(fence_init);
+diff -Naur a/drivers/base/Makefile b/drivers/base/Makefile
+--- a/drivers/base/Makefile	2015-03-26 14:43:30.858436444 +0530
++++ b/drivers/base/Makefile	2015-03-26 14:42:37.694435402 +0530
+@@ -10,7 +10,7 @@
+ obj-y			+= power/
+ obj-$(CONFIG_HAS_DMA)	+= dma-mapping.o
+ obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o
+-obj-$(CONFIG_DMA_SHARED_BUFFER) += dma-buf.o reservation.o
++obj-$(CONFIG_DMA_SHARED_BUFFER) += dma-buf.o fence.o reservation.o seqno-fence.o
+ obj-$(CONFIG_ISA)	+= isa.o
+ obj-$(CONFIG_FW_LOADER)	+= firmware_class.o
+ obj-$(CONFIG_NUMA)	+= node.o
+diff -Naur a/drivers/base/reservation.c b/drivers/base/reservation.c
+--- a/drivers/base/reservation.c	2015-03-26 14:43:30.862436444 +0530
++++ b/drivers/base/reservation.c	2015-03-26 14:42:37.694435402 +0530
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2012-2013 Canonical Ltd
++ * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst)
+  *
+  * Based on bo.c which bears the following copyright notice,
+  * but is dual licensed:
+@@ -37,3 +37,439 @@
+ 
+ DEFINE_WW_CLASS(reservation_ww_class);
+ EXPORT_SYMBOL(reservation_ww_class);
++
++struct lock_class_key reservation_seqcount_class;
++EXPORT_SYMBOL(reservation_seqcount_class);
++
++const char reservation_seqcount_string[] = "reservation_seqcount";
++EXPORT_SYMBOL(reservation_seqcount_string);
++/*
++ * Reserve space to add a shared fence to a reservation_object,
++ * must be called with obj->lock held.
++ */
++int reservation_object_reserve_shared(struct reservation_object *obj)
++{
++	struct reservation_object_list *fobj, *old;
++	u32 max;
++
++	old = reservation_object_get_list(obj);
++
++	if (old && old->shared_max) {
++		if (old->shared_count < old->shared_max) {
++			/* perform an in-place update */
++			kfree(obj->staged);
++			obj->staged = NULL;
++			return 0;
++		} else
++			max = old->shared_max * 2;
++	} else
++		max = 4;
++
++	/*
++	 * resize obj->staged or allocate if it doesn't exist,
++	 * noop if already correct size
++	 */
++	fobj = krealloc(obj->staged, offsetof(typeof(*fobj), shared[max]),
++			GFP_KERNEL);
++	if (!fobj)
++		return -ENOMEM;
++
++	obj->staged = fobj;
++	fobj->shared_max = max;
++	return 0;
++}
++EXPORT_SYMBOL(reservation_object_reserve_shared);
++
++static void
++reservation_object_add_shared_inplace(struct reservation_object *obj,
++				      struct reservation_object_list *fobj,
++				      struct fence *fence)
++{
++	u32 i;
++
++	fence_get(fence);
++
++	preempt_disable();
++	write_seqcount_begin(&obj->seq);
++
++	for (i = 0; i < fobj->shared_count; ++i) {
++		struct fence *old_fence;
++
++		old_fence = rcu_dereference_protected(fobj->shared[i],
++						reservation_object_held(obj));
++
++		if (old_fence->context == fence->context) {
++			/* memory barrier is added by write_seqcount_begin */
++			RCU_INIT_POINTER(fobj->shared[i], fence);
++			write_seqcount_end(&obj->seq);
++			preempt_enable();
++
++			fence_put(old_fence);
++			return;
++		}
++	}
++
++	/*
++	 * memory barrier is added by write_seqcount_begin,
++	 * fobj->shared_count is protected by this lock too
++	 */
++	RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence);
++	fobj->shared_count++;
++
++	write_seqcount_end(&obj->seq);
++	preempt_enable();
++}
++
++static void
++reservation_object_add_shared_replace(struct reservation_object *obj,
++				      struct reservation_object_list *old,
++				      struct reservation_object_list *fobj,
++				      struct fence *fence)
++{
++	unsigned i;
++	struct fence *old_fence = NULL;
++
++	fence_get(fence);
++
++	if (!old) {
++		RCU_INIT_POINTER(fobj->shared[0], fence);
++		fobj->shared_count = 1;
++		goto done;
++	}
++
++	/*
++	 * no need to bump fence refcounts, rcu_read access
++	 * requires the use of kref_get_unless_zero, and the
++	 * references from the old struct are carried over to
++	 * the new.
++	 */
++	fobj->shared_count = old->shared_count;
++
++	for (i = 0; i < old->shared_count; ++i) {
++		struct fence *check;
++
++		check = rcu_dereference_protected(old->shared[i],
++						reservation_object_held(obj));
++
++		if (!old_fence && check->context == fence->context) {
++			old_fence = check;
++			RCU_INIT_POINTER(fobj->shared[i], fence);
++		} else
++			RCU_INIT_POINTER(fobj->shared[i], check);
++	}
++	if (!old_fence) {
++		RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence);
++		fobj->shared_count++;
++	}
++
++done:
++	preempt_disable();
++	write_seqcount_begin(&obj->seq);
++	/*
++	 * RCU_INIT_POINTER can be used here,
++	 * seqcount provides the necessary barriers
++	 */
++	RCU_INIT_POINTER(obj->fence, fobj);
++	write_seqcount_end(&obj->seq);
++	preempt_enable();
++
++	if (old)
++		kfree_rcu(old, rcu);
++
++	if (old_fence)
++		fence_put(old_fence);
++}
++
++/*
++ * Add a fence to a shared slot, obj->lock must be held, and
++ * reservation_object_reserve_shared_fence has been called.
++ */
++void reservation_object_add_shared_fence(struct reservation_object *obj,
++					 struct fence *fence)
++{
++	struct reservation_object_list *old, *fobj = obj->staged;
++
++	old = reservation_object_get_list(obj);
++	obj->staged = NULL;
++
++	if (!fobj) {
++		BUG_ON(old->shared_count >= old->shared_max);
++		reservation_object_add_shared_inplace(obj, old, fence);
++	} else
++		reservation_object_add_shared_replace(obj, old, fobj, fence);
++}
++EXPORT_SYMBOL(reservation_object_add_shared_fence);
++
++void reservation_object_add_excl_fence(struct reservation_object *obj,
++				       struct fence *fence)
++{
++	struct fence *old_fence = reservation_object_get_excl(obj);
++	struct reservation_object_list *old;
++	u32 i = 0;
++
++	old = reservation_object_get_list(obj);
++	if (old)
++		i = old->shared_count;
++
++	if (fence)
++		fence_get(fence);
++
++	preempt_disable();
++	write_seqcount_begin(&obj->seq);
++	/* write_seqcount_begin provides the necessary memory barrier */
++	RCU_INIT_POINTER(obj->fence_excl, fence);
++	if (old)
++		old->shared_count = 0;
++	write_seqcount_end(&obj->seq);
++	preempt_enable();
++
++	/* inplace update, no shared fences */
++	while (i--)
++		fence_put(rcu_dereference_protected(old->shared[i],
++						reservation_object_held(obj)));
++
++	if (old_fence)
++		fence_put(old_fence);
++}
++EXPORT_SYMBOL(reservation_object_add_excl_fence);
++
++int reservation_object_get_fences_rcu(struct reservation_object *obj,
++				      struct fence **pfence_excl,
++				      unsigned *pshared_count,
++				      struct fence ***pshared)
++{
++	unsigned shared_count = 0;
++	unsigned retry = 1;
++	struct fence **shared = NULL, *fence_excl = NULL;
++	int ret = 0;
++
++	while (retry) {
++		struct reservation_object_list *fobj;
++		unsigned seq;
++
++		seq = read_seqcount_begin(&obj->seq);
++
++		rcu_read_lock();
++
++		fobj = rcu_dereference(obj->fence);
++		if (fobj) {
++			struct fence **nshared;
++			size_t sz = sizeof(*shared) * fobj->shared_max;
++
++			nshared = krealloc(shared, sz,
++					   GFP_NOWAIT | __GFP_NOWARN);
++			if (!nshared) {
++				rcu_read_unlock();
++				nshared = krealloc(shared, sz, GFP_KERNEL);
++				if (nshared) {
++					shared = nshared;
++					continue;
++				}
++
++				ret = -ENOMEM;
++				shared_count = 0;
++				break;
++			}
++			shared = nshared;
++			memcpy(shared, fobj->shared, sz);
++			shared_count = fobj->shared_count;
++		} else
++			shared_count = 0;
++		fence_excl = rcu_dereference(obj->fence_excl);
++
++		retry = read_seqcount_retry(&obj->seq, seq);
++		if (retry)
++			goto unlock;
++
++		if (!fence_excl || fence_get_rcu(fence_excl)) {
++			unsigned i;
++
++			for (i = 0; i < shared_count; ++i) {
++				if (fence_get_rcu(shared[i]))
++					continue;
++
++				/* uh oh, refcount failed, abort and retry */
++				while (i--)
++					fence_put(shared[i]);
++
++				if (fence_excl) {
++					fence_put(fence_excl);
++					fence_excl = NULL;
++				}
++
++				retry = 1;
++				break;
++			}
++		} else
++			retry = 1;
++
++unlock:
++		rcu_read_unlock();
++	}
++	*pshared_count = shared_count;
++	if (shared_count)
++		*pshared = shared;
++	else {
++		*pshared = NULL;
++		kfree(shared);
++	}
++	*pfence_excl = fence_excl;
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(reservation_object_get_fences_rcu);
++
++long reservation_object_wait_timeout_rcu(struct reservation_object *obj,
++					 bool wait_all, bool intr,
++					 unsigned long timeout)
++{
++	struct fence *fence;
++	unsigned seq, shared_count, i = 0;
++	long ret = timeout;
++
++retry:
++	fence = NULL;
++	shared_count = 0;
++	seq = read_seqcount_begin(&obj->seq);
++	rcu_read_lock();
++
++	if (wait_all) {
++		struct reservation_object_list *fobj = rcu_dereference(obj->fence);
++
++		if (fobj)
++			shared_count = fobj->shared_count;
++
++		if (read_seqcount_retry(&obj->seq, seq))
++			goto unlock_retry;
++
++		for (i = 0; i < shared_count; ++i) {
++			struct fence *lfence = rcu_dereference(fobj->shared[i]);
++
++			if (test_bit(FENCE_FLAG_SIGNALED_BIT, &lfence->flags))
++				continue;
++
++			if (!fence_get_rcu(lfence))
++				goto unlock_retry;
++
++			if (fence_is_signaled(lfence)) {
++				fence_put(lfence);
++				continue;
++			}
++
++			fence = lfence;
++			break;
++		}
++	}
++
++	if (!shared_count) {
++		struct fence *fence_excl = rcu_dereference(obj->fence_excl);
++
++		if (read_seqcount_retry(&obj->seq, seq))
++			goto unlock_retry;
++
++		if (fence_excl &&
++		    !test_bit(FENCE_FLAG_SIGNALED_BIT, &fence_excl->flags)) {
++			if (!fence_get_rcu(fence_excl))
++				goto unlock_retry;
++
++			if (fence_is_signaled(fence_excl))
++				fence_put(fence_excl);
++			else
++				fence = fence_excl;
++		}
++	}
++
++	rcu_read_unlock();
++	if (fence) {
++		ret = fence_wait_timeout(fence, intr, ret);
++		fence_put(fence);
++		if (ret > 0 && wait_all && (i + 1 < shared_count))
++			goto retry;
++	}
++	return ret;
++
++unlock_retry:
++	rcu_read_unlock();
++	goto retry;
++}
++EXPORT_SYMBOL_GPL(reservation_object_wait_timeout_rcu);
++
++
++static inline int
++reservation_object_test_signaled_single(struct fence *passed_fence)
++{
++	struct fence *fence, *lfence = passed_fence;
++	int ret = 1;
++
++	if (!test_bit(FENCE_FLAG_SIGNALED_BIT, &lfence->flags)) {
++		fence = fence_get_rcu(lfence);
++		if (!fence)
++			return -1;
++
++		ret = !!fence_is_signaled(fence);
++		fence_put(fence);
++	}
++	return ret;
++}
++
++bool reservation_object_test_signaled_rcu(struct reservation_object *obj,
++					  bool test_all)
++{
++	unsigned seq, shared_count;
++	int ret = true;
++
++retry:
++	shared_count = 0;
++	seq = read_seqcount_begin(&obj->seq);
++	rcu_read_lock();
++
++	if (test_all) {
++		unsigned i;
++
++		struct reservation_object_list *fobj = rcu_dereference(obj->fence);
++
++		if (fobj)
++			shared_count = fobj->shared_count;
++
++		if (read_seqcount_retry(&obj->seq, seq))
++			goto unlock_retry;
++
++		for (i = 0; i < shared_count; ++i) {
++			struct fence *fence = rcu_dereference(fobj->shared[i]);
++
++			ret = reservation_object_test_signaled_single(fence);
++			if (ret < 0)
++				goto unlock_retry;
++			else if (!ret)
++				break;
++		}
++
++		/*
++		 * There could be a read_seqcount_retry here, but nothing cares
++		 * about whether it's the old or newer fence pointers that are
++		 * signaled. That race could still have happened after checking
++		 * read_seqcount_retry. If you care, use ww_mutex_lock.
++		 */
++	}
++
++	if (!shared_count) {
++		struct fence *fence_excl = rcu_dereference(obj->fence_excl);
++
++		if (read_seqcount_retry(&obj->seq, seq))
++			goto unlock_retry;
++
++		if (fence_excl) {
++			ret = reservation_object_test_signaled_single(fence_excl);
++			if (ret < 0)
++				goto unlock_retry;
++		}
++	}
++
++	rcu_read_unlock();
++	return ret;
++
++unlock_retry:
++	rcu_read_unlock();
++	goto retry;
++}
++EXPORT_SYMBOL_GPL(reservation_object_test_signaled_rcu);
+diff -Naur a/drivers/base/seqno-fence.c b/drivers/base/seqno-fence.c
+--- a/drivers/base/seqno-fence.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/base/seqno-fence.c	2015-03-26 14:42:37.694435402 +0530
+@@ -0,0 +1,73 @@
++/*
++ * seqno-fence, using a dma-buf to synchronize fencing
++ *
++ * Copyright (C) 2012 Texas Instruments
++ * Copyright (C) 2012-2014 Canonical Ltd
++ * Authors:
++ *   Rob Clark <robdclark@gmail.com>
++ *   Maarten Lankhorst <maarten.lankhorst@canonical.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ */
++
++#include <linux/slab.h>
++#include <linux/export.h>
++#include <linux/seqno-fence.h>
++
++static const char *seqno_fence_get_driver_name(struct fence *fence)
++{
++	struct seqno_fence *seqno_fence = to_seqno_fence(fence);
++	return seqno_fence->ops->get_driver_name(fence);
++}
++
++static const char *seqno_fence_get_timeline_name(struct fence *fence)
++{
++	struct seqno_fence *seqno_fence = to_seqno_fence(fence);
++	return seqno_fence->ops->get_timeline_name(fence);
++}
++
++static bool seqno_enable_signaling(struct fence *fence)
++{
++	struct seqno_fence *seqno_fence = to_seqno_fence(fence);
++	return seqno_fence->ops->enable_signaling(fence);
++}
++
++static bool seqno_signaled(struct fence *fence)
++{
++	struct seqno_fence *seqno_fence = to_seqno_fence(fence);
++	return seqno_fence->ops->signaled && seqno_fence->ops->signaled(fence);
++}
++
++static void seqno_release(struct fence *fence)
++{
++	struct seqno_fence *f = to_seqno_fence(fence);
++
++	dma_buf_put(f->sync_buf);
++	if (f->ops->release)
++		f->ops->release(fence);
++	else
++		fence_free(&f->base);
++}
++
++static signed long seqno_wait(struct fence *fence, bool intr, signed long timeout)
++{
++	struct seqno_fence *f = to_seqno_fence(fence);
++	return f->ops->wait(fence, intr, timeout);
++}
++
++const struct fence_ops seqno_fence_ops = {
++	.get_driver_name = seqno_fence_get_driver_name,
++	.get_timeline_name = seqno_fence_get_timeline_name,
++	.enable_signaling = seqno_enable_signaling,
++	.signaled = seqno_signaled,
++	.wait = seqno_wait,
++	.release = seqno_release,
++};
++EXPORT_SYMBOL(seqno_fence_ops);
+diff -Naur a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
+--- a/drivers/gpu/drm/ati_pcigart.c	2015-03-26 14:43:30.430436436 +0530
++++ b/drivers/gpu/drm/ati_pcigart.c	2015-03-26 14:42:38.702435421 +0530
+@@ -34,6 +34,8 @@
+ #include <linux/export.h>
+ #include <drm/drmP.h>
+ 
++#include <drm/ati_pcigart.h>
++
+ # define ATI_PCIGART_PAGE_SIZE		4096	/**< PCI GART page size */
+ 
+ static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
+diff -Naur a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c
+--- a/drivers/gpu/drm/drm_agpsupport.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/drm_agpsupport.c	2015-03-26 14:42:38.702435421 +0530
+@@ -34,6 +34,7 @@
+ #include <drm/drmP.h>
+ #include <linux/module.h>
+ #include <linux/slab.h>
++#include "drm_legacy.h"
+ 
+ #if __OS_HAS_AGP
+ 
+diff -Naur a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
+--- a/drivers/gpu/drm/drm_atomic.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_atomic.c	2015-03-26 14:42:38.702435421 +0530
+@@ -0,0 +1,657 @@
++/*
++ * Copyright (C) 2014 Red Hat
++ * Copyright (C) 2014 Intel Corp.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rob Clark <robdclark@gmail.com>
++ * Daniel Vetter <daniel.vetter@ffwll.ch>
++ */
++
++
++#include <drm/drmP.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_plane_helper.h>
++
++static void kfree_state(struct drm_atomic_state *state)
++{
++	kfree(state->connectors);
++	kfree(state->connector_states);
++	kfree(state->crtcs);
++	kfree(state->crtc_states);
++	kfree(state->planes);
++	kfree(state->plane_states);
++	kfree(state);
++}
++
++/**
++ * drm_atomic_state_alloc - allocate atomic state
++ * @dev: DRM device
++ *
++ * This allocates an empty atomic state to track updates.
++ */
++struct drm_atomic_state *
++drm_atomic_state_alloc(struct drm_device *dev)
++{
++	struct drm_atomic_state *state;
++
++	state = kzalloc(sizeof(*state), GFP_KERNEL);
++	if (!state)
++		return NULL;
++
++	state->num_connector = ACCESS_ONCE(dev->mode_config.num_connector);
++
++	state->crtcs = kcalloc(dev->mode_config.num_crtc,
++			       sizeof(*state->crtcs), GFP_KERNEL);
++	if (!state->crtcs)
++		goto fail;
++	state->crtc_states = kcalloc(dev->mode_config.num_crtc,
++				     sizeof(*state->crtc_states), GFP_KERNEL);
++	if (!state->crtc_states)
++		goto fail;
++	state->planes = kcalloc(dev->mode_config.num_total_plane,
++				sizeof(*state->planes), GFP_KERNEL);
++	if (!state->planes)
++		goto fail;
++	state->plane_states = kcalloc(dev->mode_config.num_total_plane,
++				      sizeof(*state->plane_states), GFP_KERNEL);
++	if (!state->plane_states)
++		goto fail;
++	state->connectors = kcalloc(state->num_connector,
++				    sizeof(*state->connectors),
++				    GFP_KERNEL);
++	if (!state->connectors)
++		goto fail;
++	state->connector_states = kcalloc(state->num_connector,
++					  sizeof(*state->connector_states),
++					  GFP_KERNEL);
++	if (!state->connector_states)
++		goto fail;
++
++	state->dev = dev;
++
++	DRM_DEBUG_KMS("Allocate atomic state %p\n", state);
++
++	return state;
++fail:
++	kfree_state(state);
++
++	return NULL;
++}
++EXPORT_SYMBOL(drm_atomic_state_alloc);
++
++/**
++ * drm_atomic_state_clear - clear state object
++ * @state: atomic state
++ *
++ * When the w/w mutex algorithm detects a deadlock we need to back off and drop
++ * all locks. So someone else could sneak in and change the current modeset
++ * configuration. Which means that all the state assembled in @state is no
++ * longer an atomic update to the current state, but to some arbitrary earlier
++ * state. Which could break assumptions the driver's ->atomic_check likely
++ * relies on.
++ *
++ * Hence we must clear all cached state and completely start over, using this
++ * function.
++ */
++void drm_atomic_state_clear(struct drm_atomic_state *state)
++{
++	struct drm_device *dev = state->dev;
++	struct drm_mode_config *config = &dev->mode_config;
++	int i;
++
++	DRM_DEBUG_KMS("Clearing atomic state %p\n", state);
++
++	for (i = 0; i < state->num_connector; i++) {
++		struct drm_connector *connector = state->connectors[i];
++
++		if (!connector)
++			continue;
++
++		WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
++
++		connector->funcs->atomic_destroy_state(connector,
++						       state->connector_states[i]);
++	}
++
++	for (i = 0; i < config->num_crtc; i++) {
++		struct drm_crtc *crtc = state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		crtc->funcs->atomic_destroy_state(crtc,
++						  state->crtc_states[i]);
++	}
++
++	for (i = 0; i < config->num_total_plane; i++) {
++		struct drm_plane *plane = state->planes[i];
++
++		if (!plane)
++			continue;
++
++		plane->funcs->atomic_destroy_state(plane,
++						   state->plane_states[i]);
++	}
++}
++EXPORT_SYMBOL(drm_atomic_state_clear);
++
++/**
++ * drm_atomic_state_free - free all memory for an atomic state
++ * @state: atomic state to deallocate
++ *
++ * This frees all memory associated with an atomic state, including all the
++ * per-object state for planes, crtcs and connectors.
++ */
++void drm_atomic_state_free(struct drm_atomic_state *state)
++{
++	drm_atomic_state_clear(state);
++
++	DRM_DEBUG_KMS("Freeing atomic state %p\n", state);
++
++	kfree_state(state);
++}
++EXPORT_SYMBOL(drm_atomic_state_free);
++
++/**
++ * drm_atomic_get_crtc_state - get crtc state
++ * @state: global atomic state object
++ * @crtc: crtc to get state object for
++ *
++ * This function returns the crtc state for the given crtc, allocating it if
++ * needed. It will also grab the relevant crtc lock to make sure that the state
++ * is consistent.
++ *
++ * Returns:
++ *
++ * Either the allocated state or the error code encoded into the pointer. When
++ * the error is EDEADLK then the w/w mutex code has detected a deadlock and the
++ * entire atomic sequence must be restarted. All other errors are fatal.
++ */
++struct drm_crtc_state *
++drm_atomic_get_crtc_state(struct drm_atomic_state *state,
++			  struct drm_crtc *crtc)
++{
++	int ret, index;
++	struct drm_crtc_state *crtc_state;
++
++	index = drm_crtc_index(crtc);
++
++	if (state->crtc_states[index])
++		return state->crtc_states[index];
++
++	ret = drm_modeset_lock(&crtc->mutex, state->acquire_ctx);
++	if (ret)
++		return ERR_PTR(ret);
++
++	crtc_state = crtc->funcs->atomic_duplicate_state(crtc);
++	if (!crtc_state)
++		return ERR_PTR(-ENOMEM);
++
++	state->crtc_states[index] = crtc_state;
++	state->crtcs[index] = crtc;
++	crtc_state->state = state;
++
++	DRM_DEBUG_KMS("Added [CRTC:%d] %p state to %p\n",
++		      crtc->base.id, crtc_state, state);
++
++	return crtc_state;
++}
++EXPORT_SYMBOL(drm_atomic_get_crtc_state);
++
++/**
++ * drm_atomic_get_plane_state - get plane state
++ * @state: global atomic state object
++ * @plane: plane to get state object for
++ *
++ * This function returns the plane state for the given plane, allocating it if
++ * needed. It will also grab the relevant plane lock to make sure that the state
++ * is consistent.
++ *
++ * Returns:
++ *
++ * Either the allocated state or the error code encoded into the pointer. When
++ * the error is EDEADLK then the w/w mutex code has detected a deadlock and the
++ * entire atomic sequence must be restarted. All other errors are fatal.
++ */
++struct drm_plane_state *
++drm_atomic_get_plane_state(struct drm_atomic_state *state,
++			  struct drm_plane *plane)
++{
++	int ret, index;
++	struct drm_plane_state *plane_state;
++
++	index = drm_plane_index(plane);
++
++	if (state->plane_states[index])
++		return state->plane_states[index];
++
++	ret = drm_modeset_lock(&plane->mutex, state->acquire_ctx);
++	if (ret)
++		return ERR_PTR(ret);
++
++	plane_state = plane->funcs->atomic_duplicate_state(plane);
++	if (!plane_state)
++		return ERR_PTR(-ENOMEM);
++
++	state->plane_states[index] = plane_state;
++	state->planes[index] = plane;
++	plane_state->state = state;
++
++	DRM_DEBUG_KMS("Added [PLANE:%d] %p state to %p\n",
++		      plane->base.id, plane_state, state);
++
++	if (plane_state->crtc) {
++		struct drm_crtc_state *crtc_state;
++
++		crtc_state = drm_atomic_get_crtc_state(state,
++						       plane_state->crtc);
++		if (IS_ERR(crtc_state))
++			return ERR_CAST(crtc_state);
++	}
++
++	return plane_state;
++}
++EXPORT_SYMBOL(drm_atomic_get_plane_state);
++
++/**
++ * drm_atomic_get_connector_state - get connector state
++ * @state: global atomic state object
++ * @connector: connector to get state object for
++ *
++ * This function returns the connector state for the given connector,
++ * allocating it if needed. It will also grab the relevant connector lock to
++ * make sure that the state is consistent.
++ *
++ * Returns:
++ *
++ * Either the allocated state or the error code encoded into the pointer. When
++ * the error is EDEADLK then the w/w mutex code has detected a deadlock and the
++ * entire atomic sequence must be restarted. All other errors are fatal.
++ */
++struct drm_connector_state *
++drm_atomic_get_connector_state(struct drm_atomic_state *state,
++			  struct drm_connector *connector)
++{
++	int ret, index;
++	struct drm_mode_config *config = &connector->dev->mode_config;
++	struct drm_connector_state *connector_state;
++
++	ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx);
++	if (ret)
++		return ERR_PTR(ret);
++
++	index = drm_connector_index(connector);
++
++	/*
++	 * Construction of atomic state updates can race with a connector
++	 * hot-add which might overflow. In this case flip the table and just
++	 * restart the entire ioctl - no one is fast enough to livelock a cpu
++	 * with physical hotplug events anyway.
++	 *
++	 * Note that we only grab the indexes once we have the right lock to
++	 * prevent hotplug/unplugging of connectors. So removal is no problem,
++	 * at most the array is a bit too large.
++	 */
++	if (index >= state->num_connector) {
++		DRM_DEBUG_KMS("Hot-added connector would overflow state array, restarting\n");
++		return ERR_PTR(-EAGAIN);
++	}
++
++	if (state->connector_states[index])
++		return state->connector_states[index];
++
++	connector_state = connector->funcs->atomic_duplicate_state(connector);
++	if (!connector_state)
++		return ERR_PTR(-ENOMEM);
++
++	state->connector_states[index] = connector_state;
++	state->connectors[index] = connector;
++	connector_state->state = state;
++
++	DRM_DEBUG_KMS("Added [CONNECTOR:%d] %p state to %p\n",
++		      connector->base.id, connector_state, state);
++
++	if (connector_state->crtc) {
++		struct drm_crtc_state *crtc_state;
++
++		crtc_state = drm_atomic_get_crtc_state(state,
++						       connector_state->crtc);
++		if (IS_ERR(crtc_state))
++			return ERR_CAST(crtc_state);
++	}
++
++	return connector_state;
++}
++EXPORT_SYMBOL(drm_atomic_get_connector_state);
++
++/**
++ * drm_atomic_set_crtc_for_plane - set crtc for plane
++ * @state: the incoming atomic state
++ * @plane: the plane whose incoming state to update
++ * @crtc: crtc to use for the plane
++ *
++ * Changing the assigned crtc for a plane requires us to grab the lock and state
++ * for the new crtc, as needed. This function takes care of all these details
++ * besides updating the pointer in the state object itself.
++ *
++ * Returns:
++ * 0 on success or can fail with -EDEADLK or -ENOMEM. When the error is EDEADLK
++ * then the w/w mutex code has detected a deadlock and the entire atomic
++ * sequence must be restarted. All other errors are fatal.
++ */
++int
++drm_atomic_set_crtc_for_plane(struct drm_atomic_state *state,
++			      struct drm_plane *plane, struct drm_crtc *crtc)
++{
++	struct drm_plane_state *plane_state =
++			drm_atomic_get_plane_state(state, plane);
++	struct drm_crtc_state *crtc_state;
++
++	if (WARN_ON(IS_ERR(plane_state)))
++		return PTR_ERR(plane_state);
++
++	if (plane_state->crtc) {
++		crtc_state = drm_atomic_get_crtc_state(plane_state->state,
++						       plane_state->crtc);
++		if (WARN_ON(IS_ERR(crtc_state)))
++			return PTR_ERR(crtc_state);
++
++		crtc_state->plane_mask &= ~(1 << drm_plane_index(plane));
++	}
++
++	plane_state->crtc = crtc;
++
++	if (crtc) {
++		crtc_state = drm_atomic_get_crtc_state(plane_state->state,
++						       crtc);
++		if (IS_ERR(crtc_state))
++			return PTR_ERR(crtc_state);
++		crtc_state->plane_mask |= (1 << drm_plane_index(plane));
++	}
++
++	if (crtc)
++		DRM_DEBUG_KMS("Link plane state %p to [CRTC:%d]\n",
++			      plane_state, crtc->base.id);
++	else
++		DRM_DEBUG_KMS("Link plane state %p to [NOCRTC]\n", plane_state);
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_atomic_set_crtc_for_plane);
++
++/**
++ * drm_atomic_set_fb_for_plane - set crtc for plane
++ * @plane_state: atomic state object for the plane
++ * @fb: fb to use for the plane
++ *
++ * Changing the assigned framebuffer for a plane requires us to grab a reference
++ * to the new fb and drop the reference to the old fb, if there is one. This
++ * function takes care of all these details besides updating the pointer in the
++ * state object itself.
++ */
++void
++drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
++			    struct drm_framebuffer *fb)
++{
++	if (plane_state->fb)
++		drm_framebuffer_unreference(plane_state->fb);
++	if (fb)
++		drm_framebuffer_reference(fb);
++	plane_state->fb = fb;
++
++	if (fb)
++		DRM_DEBUG_KMS("Set [FB:%d] for plane state %p\n",
++			      fb->base.id, plane_state);
++	else
++		DRM_DEBUG_KMS("Set [NOFB] for plane state %p\n", plane_state);
++}
++EXPORT_SYMBOL(drm_atomic_set_fb_for_plane);
++
++/**
++ * drm_atomic_set_crtc_for_connector - set crtc for connector
++ * @conn_state: atomic state object for the connector
++ * @crtc: crtc to use for the connector
++ *
++ * Changing the assigned crtc for a connector requires us to grab the lock and
++ * state for the new crtc, as needed. This function takes care of all these
++ * details besides updating the pointer in the state object itself.
++ *
++ * Returns:
++ * 0 on success or can fail with -EDEADLK or -ENOMEM. When the error is EDEADLK
++ * then the w/w mutex code has detected a deadlock and the entire atomic
++ * sequence must be restarted. All other errors are fatal.
++ */
++int
++drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
++				  struct drm_crtc *crtc)
++{
++	struct drm_crtc_state *crtc_state;
++
++	if (crtc) {
++		crtc_state = drm_atomic_get_crtc_state(conn_state->state, crtc);
++		if (IS_ERR(crtc_state))
++			return PTR_ERR(crtc_state);
++	}
++
++	conn_state->crtc = crtc;
++
++	if (crtc)
++		DRM_DEBUG_KMS("Link connector state %p to [CRTC:%d]\n",
++			      conn_state, crtc->base.id);
++	else
++		DRM_DEBUG_KMS("Link connector state %p to [NOCRTC]\n",
++			      conn_state);
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_atomic_set_crtc_for_connector);
++
++/**
++ * drm_atomic_add_affected_connectors - add connectors for crtc
++ * @state: atomic state
++ * @crtc: DRM crtc
++ *
++ * This function walks the current configuration and adds all connectors
++ * currently using @crtc to the atomic configuration @state. Note that this
++ * function must acquire the connection mutex. This can potentially cause
++ * unneeded seralization if the update is just for the planes on one crtc. Hence
++ * drivers and helpers should only call this when really needed (e.g. when a
++ * full modeset needs to happen due to some change).
++ *
++ * Returns:
++ * 0 on success or can fail with -EDEADLK or -ENOMEM. When the error is EDEADLK
++ * then the w/w mutex code has detected a deadlock and the entire atomic
++ * sequence must be restarted. All other errors are fatal.
++ */
++int
++drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
++				   struct drm_crtc *crtc)
++{
++	struct drm_mode_config *config = &state->dev->mode_config;
++	struct drm_connector *connector;
++	struct drm_connector_state *conn_state;
++	int ret;
++
++	ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx);
++	if (ret)
++		return ret;
++
++	DRM_DEBUG_KMS("Adding all current connectors for [CRTC:%d] to %p\n",
++		      crtc->base.id, state);
++
++	/*
++	 * Changed connectors are already in @state, so only need to look at the
++	 * current configuration.
++	 */
++	list_for_each_entry(connector, &config->connector_list, head) {
++		if (connector->state->crtc != crtc)
++			continue;
++
++		conn_state = drm_atomic_get_connector_state(state, connector);
++		if (IS_ERR(conn_state))
++			return PTR_ERR(conn_state);
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_atomic_add_affected_connectors);
++
++/**
++ * drm_atomic_connectors_for_crtc - count number of connected outputs
++ * @state: atomic state
++ * @crtc: DRM crtc
++ *
++ * This function counts all connectors which will be connected to @crtc
++ * according to @state. Useful to recompute the enable state for @crtc.
++ */
++int
++drm_atomic_connectors_for_crtc(struct drm_atomic_state *state,
++			       struct drm_crtc *crtc)
++{
++	int i, num_connected_connectors = 0;
++
++	for (i = 0; i < state->num_connector; i++) {
++		struct drm_connector_state *conn_state;
++
++		conn_state = state->connector_states[i];
++
++		if (conn_state && conn_state->crtc == crtc)
++			num_connected_connectors++;
++	}
++
++	DRM_DEBUG_KMS("State %p has %i connectors for [CRTC:%d]\n",
++		      state, num_connected_connectors, crtc->base.id);
++
++	return num_connected_connectors;
++}
++EXPORT_SYMBOL(drm_atomic_connectors_for_crtc);
++
++/**
++ * drm_atomic_legacy_backoff - locking backoff for legacy ioctls
++ * @state: atomic state
++ *
++ * This function should be used by legacy entry points which don't understand
++ * -EDEADLK semantics. For simplicity this one will grab all modeset locks after
++ *  the slowpath completed.
++ */
++void drm_atomic_legacy_backoff(struct drm_atomic_state *state)
++{
++	int ret;
++
++retry:
++	drm_modeset_backoff(state->acquire_ctx);
++
++	ret = drm_modeset_lock(&state->dev->mode_config.connection_mutex,
++			       state->acquire_ctx);
++	if (ret)
++		goto retry;
++	ret = drm_modeset_lock_all_crtcs(state->dev,
++					 state->acquire_ctx);
++	if (ret)
++		goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_legacy_backoff);
++
++/**
++ * drm_atomic_check_only - check whether a given config would work
++ * @state: atomic configuration to check
++ *
++ * Note that this function can return -EDEADLK if the driver needed to acquire
++ * more locks but encountered a deadlock. The caller must then do the usual w/w
++ * backoff dance and restart. All other errors are fatal.
++ *
++ * Returns:
++ * 0 on success, negative error code on failure.
++ */
++int drm_atomic_check_only(struct drm_atomic_state *state)
++{
++	struct drm_mode_config *config = &state->dev->mode_config;
++
++	DRM_DEBUG_KMS("checking %p\n", state);
++
++	if (config->funcs->atomic_check)
++		return config->funcs->atomic_check(state->dev, state);
++	else
++		return 0;
++}
++EXPORT_SYMBOL(drm_atomic_check_only);
++
++/**
++ * drm_atomic_commit - commit configuration atomically
++ * @state: atomic configuration to check
++ *
++ * Note that this function can return -EDEADLK if the driver needed to acquire
++ * more locks but encountered a deadlock. The caller must then do the usual w/w
++ * backoff dance and restart. All other errors are fatal.
++ *
++ * Also note that on successful execution ownership of @state is transferred
++ * from the caller of this function to the function itself. The caller must not
++ * free or in any other way access @state. If the function fails then the caller
++ * must clean up @state itself.
++ *
++ * Returns:
++ * 0 on success, negative error code on failure.
++ */
++int drm_atomic_commit(struct drm_atomic_state *state)
++{
++	struct drm_mode_config *config = &state->dev->mode_config;
++	int ret;
++
++	ret = drm_atomic_check_only(state);
++	if (ret)
++		return ret;
++
++	DRM_DEBUG_KMS("commiting %p\n", state);
++
++	return config->funcs->atomic_commit(state->dev, state, false);
++}
++EXPORT_SYMBOL(drm_atomic_commit);
++
++/**
++ * drm_atomic_async_commit - atomic&async configuration commit
++ * @state: atomic configuration to check
++ *
++ * Note that this function can return -EDEADLK if the driver needed to acquire
++ * more locks but encountered a deadlock. The caller must then do the usual w/w
++ * backoff dance and restart. All other errors are fatal.
++ *
++ * Also note that on successful execution ownership of @state is transferred
++ * from the caller of this function to the function itself. The caller must not
++ * free or in any other way access @state. If the function fails then the caller
++ * must clean up @state itself.
++ *
++ * Returns:
++ * 0 on success, negative error code on failure.
++ */
++int drm_atomic_async_commit(struct drm_atomic_state *state)
++{
++	struct drm_mode_config *config = &state->dev->mode_config;
++	int ret;
++
++	ret = drm_atomic_check_only(state);
++	if (ret)
++		return ret;
++
++	DRM_DEBUG_KMS("commiting %p asynchronously\n", state);
++
++	return config->funcs->atomic_commit(state->dev, state, true);
++}
++EXPORT_SYMBOL(drm_atomic_async_commit);
+diff -Naur a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
+--- a/drivers/gpu/drm/drm_atomic_helper.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_atomic_helper.c	2015-03-26 14:42:38.706435421 +0530
+@@ -0,0 +1,1966 @@
++/*
++ * Copyright (C) 2014 Red Hat
++ * Copyright (C) 2014 Intel Corp.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rob Clark <robdclark@gmail.com>
++ * Daniel Vetter <daniel.vetter@ffwll.ch>
++ */
++
++#include <drm/drmP.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_plane_helper.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_atomic_helper.h>
++#include <linux/fence.h>
++
++/**
++ * DOC: overview
++ *
++ * This helper library provides implementations of check and commit functions on
++ * top of the CRTC modeset helper callbacks and the plane helper callbacks. It
++ * also provides convenience implementations for the atomic state handling
++ * callbacks for drivers which don't need to subclass the drm core structures to
++ * add their own additional internal state.
++ *
++ * This library also provides default implementations for the check callback in
++ * drm_atomic_helper_check and for the commit callback with
++ * drm_atomic_helper_commit. But the individual stages and callbacks are expose
++ * to allow drivers to mix and match and e.g. use the plane helpers only
++ * together with a driver private modeset implementation.
++ *
++ * This library also provides implementations for all the legacy driver
++ * interfaces on top of the atomic interface. See drm_atomic_helper_set_config,
++ * drm_atomic_helper_disable_plane, drm_atomic_helper_disable_plane and the
++ * various functions to implement set_property callbacks. New drivers must not
++ * implement these functions themselves but must use the provided helpers.
++ */
++static void
++drm_atomic_helper_plane_changed(struct drm_atomic_state *state,
++				struct drm_plane_state *plane_state,
++				struct drm_plane *plane)
++{
++	struct drm_crtc_state *crtc_state;
++
++	if (plane->state->crtc) {
++		crtc_state = state->crtc_states[drm_crtc_index(plane->crtc)];
++
++		if (WARN_ON(!crtc_state))
++			return;
++
++		crtc_state->planes_changed = true;
++	}
++
++	if (plane_state->crtc) {
++		crtc_state =
++			state->crtc_states[drm_crtc_index(plane_state->crtc)];
++
++		if (WARN_ON(!crtc_state))
++			return;
++
++		crtc_state->planes_changed = true;
++	}
++}
++
++static struct drm_crtc *
++get_current_crtc_for_encoder(struct drm_device *dev,
++			     struct drm_encoder *encoder)
++{
++	struct drm_mode_config *config = &dev->mode_config;
++	struct drm_connector *connector;
++
++	WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
++
++	list_for_each_entry(connector, &config->connector_list, head) {
++		if (connector->state->best_encoder != encoder)
++			continue;
++
++		return connector->state->crtc;
++	}
++
++	return NULL;
++}
++
++static int
++steal_encoder(struct drm_atomic_state *state,
++	      struct drm_encoder *encoder,
++	      struct drm_crtc *encoder_crtc)
++{
++	struct drm_mode_config *config = &state->dev->mode_config;
++	struct drm_crtc_state *crtc_state;
++	struct drm_connector *connector;
++	struct drm_connector_state *connector_state;
++	int ret;
++
++	/*
++	 * We can only steal an encoder coming from a connector, which means we
++	 * must already hold the connection_mutex.
++	 */
++	WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
++
++	DRM_DEBUG_KMS("[ENCODER:%d:%s] in use on [CRTC:%d], stealing it\n",
++		      encoder->base.id, encoder->name,
++		      encoder_crtc->base.id);
++
++	crtc_state = drm_atomic_get_crtc_state(state, encoder_crtc);
++	if (IS_ERR(crtc_state))
++		return PTR_ERR(crtc_state);
++
++	crtc_state->mode_changed = true;
++
++	list_for_each_entry(connector, &config->connector_list, head) {
++		if (connector->state->best_encoder != encoder)
++			continue;
++
++		DRM_DEBUG_KMS("Stealing encoder from [CONNECTOR:%d:%s]\n",
++			      connector->base.id,
++			      connector->name);
++
++		connector_state = drm_atomic_get_connector_state(state,
++								 connector);
++		if (IS_ERR(connector_state))
++			return PTR_ERR(connector_state);
++
++		ret = drm_atomic_set_crtc_for_connector(connector_state, NULL);
++		if (ret)
++			return ret;
++		connector_state->best_encoder = NULL;
++	}
++
++	return 0;
++}
++
++static int
++update_connector_routing(struct drm_atomic_state *state, int conn_idx)
++{
++	struct drm_connector_helper_funcs *funcs;
++	struct drm_encoder *new_encoder;
++	struct drm_crtc *encoder_crtc;
++	struct drm_connector *connector;
++	struct drm_connector_state *connector_state;
++	struct drm_crtc_state *crtc_state;
++	int idx, ret;
++
++	connector = state->connectors[conn_idx];
++	connector_state = state->connector_states[conn_idx];
++
++	if (!connector)
++		return 0;
++
++	DRM_DEBUG_KMS("Updating routing for [CONNECTOR:%d:%s]\n",
++			connector->base.id,
++			connector->name);
++
++	if (connector->state->crtc != connector_state->crtc) {
++		if (connector->state->crtc) {
++			idx = drm_crtc_index(connector->state->crtc);
++
++			crtc_state = state->crtc_states[idx];
++			crtc_state->mode_changed = true;
++		}
++
++		if (connector_state->crtc) {
++			idx = drm_crtc_index(connector_state->crtc);
++
++			crtc_state = state->crtc_states[idx];
++			crtc_state->mode_changed = true;
++		}
++	}
++
++	if (!connector_state->crtc) {
++		DRM_DEBUG_KMS("Disabling [CONNECTOR:%d:%s]\n",
++				connector->base.id,
++				connector->name);
++
++		connector_state->best_encoder = NULL;
++
++		return 0;
++	}
++
++	funcs = connector->helper_private;
++	new_encoder = funcs->best_encoder(connector);
++
++	if (!new_encoder) {
++		DRM_DEBUG_KMS("No suitable encoder found for [CONNECTOR:%d:%s]\n",
++			      connector->base.id,
++			      connector->name);
++		return -EINVAL;
++	}
++
++	if (new_encoder == connector_state->best_encoder) {
++		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] keeps [ENCODER:%d:%s], now on [CRTC:%d]\n",
++			      connector->base.id,
++			      connector->name,
++			      new_encoder->base.id,
++			      new_encoder->name,
++			      connector_state->crtc->base.id);
++
++		return 0;
++	}
++
++	encoder_crtc = get_current_crtc_for_encoder(state->dev,
++						    new_encoder);
++
++	if (encoder_crtc) {
++		ret = steal_encoder(state, new_encoder, encoder_crtc);
++		if (ret) {
++			DRM_DEBUG_KMS("Encoder stealing failed for [CONNECTOR:%d:%s]\n",
++				      connector->base.id,
++				      connector->name);
++			return ret;
++		}
++	}
++
++	connector_state->best_encoder = new_encoder;
++	idx = drm_crtc_index(connector_state->crtc);
++
++	crtc_state = state->crtc_states[idx];
++	crtc_state->mode_changed = true;
++
++	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] using [ENCODER:%d:%s] on [CRTC:%d]\n",
++		      connector->base.id,
++		      connector->name,
++		      new_encoder->base.id,
++		      new_encoder->name,
++		      connector_state->crtc->base.id);
++
++	return 0;
++}
++
++static int
++mode_fixup(struct drm_atomic_state *state)
++{
++	int ncrtcs = state->dev->mode_config.num_crtc;
++	struct drm_crtc_state *crtc_state;
++	struct drm_connector_state *conn_state;
++	int i;
++	bool ret;
++
++	for (i = 0; i < ncrtcs; i++) {
++		crtc_state = state->crtc_states[i];
++
++		if (!crtc_state || !crtc_state->mode_changed)
++			continue;
++
++		drm_mode_copy(&crtc_state->adjusted_mode, &crtc_state->mode);
++	}
++
++	for (i = 0; i < state->num_connector; i++) {
++		struct drm_encoder_helper_funcs *funcs;
++		struct drm_encoder *encoder;
++
++		conn_state = state->connector_states[i];
++
++		if (!conn_state)
++			continue;
++
++		WARN_ON(!!conn_state->best_encoder != !!conn_state->crtc);
++
++		if (!conn_state->crtc || !conn_state->best_encoder)
++			continue;
++
++		crtc_state =
++			state->crtc_states[drm_crtc_index(conn_state->crtc)];
++
++		/*
++		 * Each encoder has at most one connector (since we always steal
++		 * it away), so we won't call ->mode_fixup twice.
++		 */
++		encoder = conn_state->best_encoder;
++		funcs = encoder->helper_private;
++
++		if (encoder->bridge && encoder->bridge->funcs->mode_fixup) {
++			ret = encoder->bridge->funcs->mode_fixup(
++					encoder->bridge, &crtc_state->mode,
++					&crtc_state->adjusted_mode);
++			if (!ret) {
++				DRM_DEBUG_KMS("Bridge fixup failed\n");
++				return -EINVAL;
++			}
++		}
++
++
++		ret = funcs->mode_fixup(encoder, &crtc_state->mode,
++					&crtc_state->adjusted_mode);
++		if (!ret) {
++			DRM_DEBUG_KMS("[ENCODER:%d:%s] fixup failed\n",
++				      encoder->base.id, encoder->name);
++			return -EINVAL;
++		}
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc;
++
++		crtc_state = state->crtc_states[i];
++		crtc = state->crtcs[i];
++
++		if (!crtc_state || !crtc_state->mode_changed)
++			continue;
++
++		funcs = crtc->helper_private;
++		ret = funcs->mode_fixup(crtc, &crtc_state->mode,
++					&crtc_state->adjusted_mode);
++		if (!ret) {
++			DRM_DEBUG_KMS("[CRTC:%d] fixup failed\n",
++				      crtc->base.id);
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int
++drm_atomic_helper_check_modeset(struct drm_device *dev,
++				struct drm_atomic_state *state)
++{
++	int ncrtcs = dev->mode_config.num_crtc;
++	struct drm_crtc *crtc;
++	struct drm_crtc_state *crtc_state;
++	int i, ret;
++
++	for (i = 0; i < ncrtcs; i++) {
++		crtc = state->crtcs[i];
++		crtc_state = state->crtc_states[i];
++
++		if (!crtc)
++			continue;
++
++		if (!drm_mode_equal(&crtc->state->mode, &crtc_state->mode)) {
++			DRM_DEBUG_KMS("[CRTC:%d] mode changed\n",
++				      crtc->base.id);
++			crtc_state->mode_changed = true;
++		}
++
++		if (crtc->state->enable != crtc_state->enable) {
++			DRM_DEBUG_KMS("[CRTC:%d] enable changed\n",
++				      crtc->base.id);
++			crtc_state->mode_changed = true;
++		}
++	}
++
++	for (i = 0; i < state->num_connector; i++) {
++		/*
++		 * This only sets crtc->mode_changed for routing changes,
++		 * drivers must set crtc->mode_changed themselves when connector
++		 * properties need to be updated.
++		 */
++		ret = update_connector_routing(state, i);
++		if (ret)
++			return ret;
++	}
++
++	/*
++	 * After all the routing has been prepared we need to add in any
++	 * connector which is itself unchanged, but who's crtc changes it's
++	 * configuration. This must be done before calling mode_fixup in case a
++	 * crtc only changed its mode but has the same set of connectors.
++	 */
++	for (i = 0; i < ncrtcs; i++) {
++		int num_connectors;
++
++		crtc = state->crtcs[i];
++		crtc_state = state->crtc_states[i];
++
++		if (!crtc || !crtc_state->mode_changed)
++			continue;
++
++		DRM_DEBUG_KMS("[CRTC:%d] needs full modeset, enable: %c\n",
++			      crtc->base.id,
++			      crtc_state->enable ? 'y' : 'n');
++
++		ret = drm_atomic_add_affected_connectors(state, crtc);
++		if (ret != 0)
++			return ret;
++
++		num_connectors = drm_atomic_connectors_for_crtc(state,
++								crtc);
++
++		if (crtc_state->enable != !!num_connectors) {
++			DRM_DEBUG_KMS("[CRTC:%d] enabled/connectors mismatch\n",
++				      crtc->base.id);
++
++			return -EINVAL;
++		}
++	}
++
++	return mode_fixup(state);
++}
++
++/**
++ * drm_atomic_helper_check - validate state object
++ * @dev: DRM device
++ * @state: the driver state object
++ *
++ * Check the state object to see if the requested state is physically possible.
++ * Only crtcs and planes have check callbacks, so for any additional (global)
++ * checking that a driver needs it can simply wrap that around this function.
++ * Drivers without such needs can directly use this as their ->atomic_check()
++ * callback.
++ *
++ * RETURNS
++ * Zero for success or -errno
++ */
++int drm_atomic_helper_check(struct drm_device *dev,
++			    struct drm_atomic_state *state)
++{
++	int nplanes = dev->mode_config.num_total_plane;
++	int ncrtcs = dev->mode_config.num_crtc;
++	int i, ret = 0;
++
++	for (i = 0; i < nplanes; i++) {
++		struct drm_plane_helper_funcs *funcs;
++		struct drm_plane *plane = state->planes[i];
++		struct drm_plane_state *plane_state = state->plane_states[i];
++
++		if (!plane)
++			continue;
++
++		funcs = plane->helper_private;
++
++		drm_atomic_helper_plane_changed(state, plane_state, plane);
++
++		if (!funcs || !funcs->atomic_check)
++			continue;
++
++		ret = funcs->atomic_check(plane, plane_state);
++		if (ret) {
++			DRM_DEBUG_KMS("[PLANE:%d] atomic check failed\n",
++				      plane->base.id);
++			return ret;
++		}
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc = state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		funcs = crtc->helper_private;
++
++		if (!funcs || !funcs->atomic_check)
++			continue;
++
++		ret = funcs->atomic_check(crtc, state->crtc_states[i]);
++		if (ret) {
++			DRM_DEBUG_KMS("[CRTC:%d] atomic check failed\n",
++				      crtc->base.id);
++			return ret;
++		}
++	}
++
++	ret = drm_atomic_helper_check_modeset(dev, state);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++EXPORT_SYMBOL(drm_atomic_helper_check);
++
++static void
++disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
++{
++	int ncrtcs = old_state->dev->mode_config.num_crtc;
++	int i;
++
++	for (i = 0; i < old_state->num_connector; i++) {
++		struct drm_connector_state *old_conn_state;
++		struct drm_connector *connector;
++		struct drm_encoder_helper_funcs *funcs;
++		struct drm_encoder *encoder;
++
++		old_conn_state = old_state->connector_states[i];
++		connector = old_state->connectors[i];
++
++		/* Shut down everything that's in the changeset and currently
++		 * still on. So need to check the old, saved state. */
++		if (!old_conn_state || !old_conn_state->crtc)
++			continue;
++
++		encoder = old_conn_state->best_encoder;
++
++		/* We shouldn't get this far if we didn't previously have
++		 * an encoder.. but WARN_ON() rather than explode.
++		 */
++		if (WARN_ON(!encoder))
++			continue;
++
++		funcs = encoder->helper_private;
++
++		/*
++		 * Each encoder has at most one connector (since we always steal
++		 * it away), so we won't call call disable hooks twice.
++		 */
++		if (encoder->bridge)
++			encoder->bridge->funcs->disable(encoder->bridge);
++
++		/* Right function depends upon target state. */
++		if (connector->state->crtc)
++			funcs->prepare(encoder);
++		else if (funcs->disable)
++			funcs->disable(encoder);
++		else
++			funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
++
++		if (encoder->bridge)
++			encoder->bridge->funcs->post_disable(encoder->bridge);
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc;
++
++		crtc = old_state->crtcs[i];
++
++		/* Shut down everything that needs a full modeset. */
++		if (!crtc || !crtc->state->mode_changed)
++			continue;
++
++		funcs = crtc->helper_private;
++
++		/* Right function depends upon target state. */
++		if (crtc->state->enable)
++			funcs->prepare(crtc);
++		else if (funcs->disable)
++			funcs->disable(crtc);
++		else
++			funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
++	}
++}
++
++static void
++set_routing_links(struct drm_device *dev, struct drm_atomic_state *old_state)
++{
++	int ncrtcs = old_state->dev->mode_config.num_crtc;
++	int i;
++
++	/* clear out existing links */
++	for (i = 0; i < old_state->num_connector; i++) {
++		struct drm_connector *connector;
++
++		connector = old_state->connectors[i];
++
++		if (!connector || !connector->encoder)
++			continue;
++
++		WARN_ON(!connector->encoder->crtc);
++
++		connector->encoder->crtc = NULL;
++		connector->encoder = NULL;
++	}
++
++	/* set new links */
++	for (i = 0; i < old_state->num_connector; i++) {
++		struct drm_connector *connector;
++
++		connector = old_state->connectors[i];
++
++		if (!connector || !connector->state->crtc)
++			continue;
++
++		if (WARN_ON(!connector->state->best_encoder))
++			continue;
++
++		connector->encoder = connector->state->best_encoder;
++		connector->encoder->crtc = connector->state->crtc;
++	}
++
++	/* set legacy state in the crtc structure */
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc *crtc;
++
++		crtc = old_state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		crtc->mode = crtc->state->mode;
++		crtc->enabled = crtc->state->enable;
++		crtc->x = crtc->primary->state->src_x >> 16;
++		crtc->y = crtc->primary->state->src_y >> 16;
++	}
++}
++
++static void
++crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state)
++{
++	int ncrtcs = old_state->dev->mode_config.num_crtc;
++	int i;
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc;
++
++		crtc = old_state->crtcs[i];
++
++		if (!crtc || !crtc->state->mode_changed)
++			continue;
++
++		funcs = crtc->helper_private;
++
++		if (crtc->state->enable)
++			funcs->mode_set_nofb(crtc);
++	}
++
++	for (i = 0; i < old_state->num_connector; i++) {
++		struct drm_connector *connector;
++		struct drm_crtc_state *new_crtc_state;
++		struct drm_encoder_helper_funcs *funcs;
++		struct drm_encoder *encoder;
++		struct drm_display_mode *mode, *adjusted_mode;
++
++		connector = old_state->connectors[i];
++
++		if (!connector || !connector->state->best_encoder)
++			continue;
++
++		encoder = connector->state->best_encoder;
++		funcs = encoder->helper_private;
++		new_crtc_state = connector->state->crtc->state;
++		mode = &new_crtc_state->mode;
++		adjusted_mode = &new_crtc_state->adjusted_mode;
++
++		/*
++		 * Each encoder has at most one connector (since we always steal
++		 * it away), so we won't call call mode_set hooks twice.
++		 */
++		funcs->mode_set(encoder, mode, adjusted_mode);
++
++		if (encoder->bridge && encoder->bridge->funcs->mode_set)
++			encoder->bridge->funcs->mode_set(encoder->bridge,
++							 mode, adjusted_mode);
++	}
++}
++
++/**
++ * drm_atomic_helper_commit_pre_planes - modeset commit before plane updates
++ * @dev: DRM device
++ * @state: atomic state
++ *
++ * This function commits the modeset changes that need to be committed before
++ * updating planes. It shuts down all the outputs that need to be shut down and
++ * prepares them (if required) with the new mode.
++ */
++void drm_atomic_helper_commit_pre_planes(struct drm_device *dev,
++					 struct drm_atomic_state *state)
++{
++	disable_outputs(dev, state);
++	set_routing_links(dev, state);
++	crtc_set_mode(dev, state);
++}
++EXPORT_SYMBOL(drm_atomic_helper_commit_pre_planes);
++
++/**
++ * drm_atomic_helper_commit_post_planes - modeset commit after plane updates
++ * @dev: DRM device
++ * @old_state: atomic state object with old state structures
++ *
++ * This function commits the modeset changes that need to be committed after
++ * updating planes: It enables all the outputs with the new configuration which
++ * had to be turned off for the update.
++ */
++void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
++					  struct drm_atomic_state *old_state)
++{
++	int ncrtcs = old_state->dev->mode_config.num_crtc;
++	int i;
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc;
++
++		crtc = old_state->crtcs[i];
++
++		/* Need to filter out CRTCs where only planes change. */
++		if (!crtc || !crtc->state->mode_changed)
++			continue;
++
++		funcs = crtc->helper_private;
++
++		if (crtc->state->enable)
++			funcs->commit(crtc);
++	}
++
++	for (i = 0; i < old_state->num_connector; i++) {
++		struct drm_connector *connector;
++		struct drm_encoder_helper_funcs *funcs;
++		struct drm_encoder *encoder;
++
++		connector = old_state->connectors[i];
++
++		if (!connector || !connector->state->best_encoder)
++			continue;
++
++		encoder = connector->state->best_encoder;
++		funcs = encoder->helper_private;
++
++		/*
++		 * Each encoder has at most one connector (since we always steal
++		 * it away), so we won't call call enable hooks twice.
++		 */
++		if (encoder->bridge)
++			encoder->bridge->funcs->pre_enable(encoder->bridge);
++
++		funcs->commit(encoder);
++
++		if (encoder->bridge)
++			encoder->bridge->funcs->enable(encoder->bridge);
++	}
++}
++EXPORT_SYMBOL(drm_atomic_helper_commit_post_planes);
++
++static void wait_for_fences(struct drm_device *dev,
++			    struct drm_atomic_state *state)
++{
++	int nplanes = dev->mode_config.num_total_plane;
++	int i;
++
++	for (i = 0; i < nplanes; i++) {
++		struct drm_plane *plane = state->planes[i];
++
++		if (!plane || !plane->state->fence)
++			continue;
++
++		WARN_ON(!plane->state->fb);
++
++		fence_wait(plane->state->fence, false);
++		fence_put(plane->state->fence);
++		plane->state->fence = NULL;
++	}
++}
++
++static bool framebuffer_changed(struct drm_device *dev,
++				struct drm_atomic_state *old_state,
++				struct drm_crtc *crtc)
++{
++	struct drm_plane *plane;
++	struct drm_plane_state *old_plane_state;
++	int nplanes = old_state->dev->mode_config.num_total_plane;
++	int i;
++
++	for (i = 0; i < nplanes; i++) {
++		plane = old_state->planes[i];
++		old_plane_state = old_state->plane_states[i];
++
++		if (!plane)
++			continue;
++
++		if (plane->state->crtc != crtc &&
++		    old_plane_state->crtc != crtc)
++			continue;
++
++		if (plane->state->fb != old_plane_state->fb)
++			return true;
++	}
++
++	return false;
++}
++
++/**
++ * drm_atomic_helper_wait_for_vblanks - wait for vblank on crtcs
++ * @dev: DRM device
++ * @old_state: atomic state object with old state structures
++ *
++ * Helper to, after atomic commit, wait for vblanks on all effected
++ * crtcs (ie. before cleaning up old framebuffers using
++ * drm_atomic_helper_cleanup_planes()). It will only wait on crtcs where the
++ * framebuffers have actually changed to optimize for the legacy cursor and
++ * plane update use-case.
++ */
++void
++drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
++		struct drm_atomic_state *old_state)
++{
++	struct drm_crtc *crtc;
++	struct drm_crtc_state *old_crtc_state;
++	int ncrtcs = old_state->dev->mode_config.num_crtc;
++	int i, ret;
++
++	for (i = 0; i < ncrtcs; i++) {
++		crtc = old_state->crtcs[i];
++		old_crtc_state = old_state->crtc_states[i];
++
++		if (!crtc)
++			continue;
++
++		/* No one cares about the old state, so abuse it for tracking
++		 * and store whether we hold a vblank reference (and should do a
++		 * vblank wait) in the ->enable boolean. */
++		old_crtc_state->enable = false;
++
++		if (!crtc->state->enable)
++			continue;
++
++		if (!framebuffer_changed(dev, old_state, crtc))
++			continue;
++
++		ret = drm_crtc_vblank_get(crtc);
++		if (ret != 0)
++			continue;
++
++		old_crtc_state->enable = true;
++		old_crtc_state->last_vblank_count = drm_vblank_count(dev, i);
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		crtc = old_state->crtcs[i];
++		old_crtc_state = old_state->crtc_states[i];
++
++		if (!crtc || !old_crtc_state->enable)
++			continue;
++
++		ret = wait_event_timeout(dev->vblank[i].queue,
++				old_crtc_state->last_vblank_count !=
++					drm_vblank_count(dev, i),
++				msecs_to_jiffies(50));
++
++		drm_crtc_vblank_put(crtc);
++	}
++}
++EXPORT_SYMBOL(drm_atomic_helper_wait_for_vblanks);
++
++/**
++ * drm_atomic_helper_commit - commit validated state object
++ * @dev: DRM device
++ * @state: the driver state object
++ * @async: asynchronous commit
++ *
++ * This function commits a with drm_atomic_helper_check() pre-validated state
++ * object. This can still fail when e.g. the framebuffer reservation fails. For
++ * now this doesn't implement asynchronous commits.
++ *
++ * RETURNS
++ * Zero for success or -errno.
++ */
++int drm_atomic_helper_commit(struct drm_device *dev,
++			     struct drm_atomic_state *state,
++			     bool async)
++{
++	int ret;
++
++	if (async)
++		return -EBUSY;
++
++	ret = drm_atomic_helper_prepare_planes(dev, state);
++	if (ret)
++		return ret;
++
++	/*
++	 * This is the point of no return - everything below never fails except
++	 * when the hw goes bonghits. Which means we can commit the new state on
++	 * the software side now.
++	 */
++
++	drm_atomic_helper_swap_state(dev, state);
++
++	/*
++	 * Everything below can be run asynchronously without the need to grab
++	 * any modeset locks at all under one conditions: It must be guaranteed
++	 * that the asynchronous work has either been cancelled (if the driver
++	 * supports it, which at least requires that the framebuffers get
++	 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
++	 * before the new state gets committed on the software side with
++	 * drm_atomic_helper_swap_state().
++	 *
++	 * This scheme allows new atomic state updates to be prepared and
++	 * checked in parallel to the asynchronous completion of the previous
++	 * update. Which is important since compositors need to figure out the
++	 * composition of the next frame right after having submitted the
++	 * current layout.
++	 */
++
++	wait_for_fences(dev, state);
++
++	drm_atomic_helper_commit_pre_planes(dev, state);
++
++	drm_atomic_helper_commit_planes(dev, state);
++
++	drm_atomic_helper_commit_post_planes(dev, state);
++
++	drm_atomic_helper_wait_for_vblanks(dev, state);
++
++	drm_atomic_helper_cleanup_planes(dev, state);
++
++	drm_atomic_state_free(state);
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_atomic_helper_commit);
++
++/**
++ * DOC: implementing async commit
++ *
++ * For now the atomic helpers don't support async commit directly. If there is
++ * real need it could be added though, using the dma-buf fence infrastructure
++ * for generic synchronization with outstanding rendering.
++ *
++ * For now drivers have to implement async commit themselves, with the following
++ * sequence being the recommended one:
++ *
++ * 1. Run drm_atomic_helper_prepare_planes() first. This is the only function
++ * which commit needs to call which can fail, so we want to run it first and
++ * synchronously.
++ *
++ * 2. Synchronize with any outstanding asynchronous commit worker threads which
++ * might be affected the new state update. This can be done by either cancelling
++ * or flushing the work items, depending upon whether the driver can deal with
++ * cancelled updates. Note that it is important to ensure that the framebuffer
++ * cleanup is still done when cancelling.
++ *
++ * For sufficient parallelism it is recommended to have a work item per crtc
++ * (for updates which don't touch global state) and a global one. Then we only
++ * need to synchronize with the crtc work items for changed crtcs and the global
++ * work item, which allows nice concurrent updates on disjoint sets of crtcs.
++ *
++ * 3. The software state is updated synchronously with
++ * drm_atomic_helper_swap_state. Doing this under the protection of all modeset
++ * locks means concurrent callers never see inconsistent state. And doing this
++ * while it's guaranteed that no relevant async worker runs means that async
++ * workers do not need grab any locks. Actually they must not grab locks, for
++ * otherwise the work flushing will deadlock.
++ *
++ * 4. Schedule a work item to do all subsequent steps, using the split-out
++ * commit helpers: a) pre-plane commit b) plane commit c) post-plane commit and
++ * then cleaning up the framebuffers after the old framebuffer is no longer
++ * being displayed.
++ */
++
++/**
++ * drm_atomic_helper_prepare_planes - prepare plane resources after commit
++ * @dev: DRM device
++ * @state: atomic state object with old state structures
++ *
++ * This function prepares plane state, specifically framebuffers, for the new
++ * configuration. If any failure is encountered this function will call
++ * ->cleanup_fb on any already successfully prepared framebuffer.
++ *
++ * Returns:
++ * 0 on success, negative error code on failure.
++ */
++int drm_atomic_helper_prepare_planes(struct drm_device *dev,
++				     struct drm_atomic_state *state)
++{
++	int nplanes = dev->mode_config.num_total_plane;
++	int ret, i;
++
++	for (i = 0; i < nplanes; i++) {
++		struct drm_plane_helper_funcs *funcs;
++		struct drm_plane *plane = state->planes[i];
++		struct drm_framebuffer *fb;
++
++		if (!plane)
++			continue;
++
++		funcs = plane->helper_private;
++
++		fb = state->plane_states[i]->fb;
++
++		if (fb && funcs->prepare_fb) {
++			ret = funcs->prepare_fb(plane, fb);
++			if (ret)
++				goto fail;
++		}
++	}
++
++	return 0;
++
++fail:
++	for (i--; i >= 0; i--) {
++		struct drm_plane_helper_funcs *funcs;
++		struct drm_plane *plane = state->planes[i];
++		struct drm_framebuffer *fb;
++
++		if (!plane)
++			continue;
++
++		funcs = plane->helper_private;
++
++		fb = state->plane_states[i]->fb;
++
++		if (fb && funcs->cleanup_fb)
++			funcs->cleanup_fb(plane, fb);
++
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL(drm_atomic_helper_prepare_planes);
++
++/**
++ * drm_atomic_helper_commit_planes - commit plane state
++ * @dev: DRM device
++ * @old_state: atomic state object with old state structures
++ *
++ * This function commits the new plane state using the plane and atomic helper
++ * functions for planes and crtcs. It assumes that the atomic state has already
++ * been pushed into the relevant object state pointers, since this step can no
++ * longer fail.
++ *
++ * It still requires the global state object @old_state to know which planes and
++ * crtcs need to be updated though.
++ */
++void drm_atomic_helper_commit_planes(struct drm_device *dev,
++				     struct drm_atomic_state *old_state)
++{
++	int nplanes = dev->mode_config.num_total_plane;
++	int ncrtcs = dev->mode_config.num_crtc;
++	int i;
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc = old_state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		funcs = crtc->helper_private;
++
++		if (!funcs || !funcs->atomic_begin)
++			continue;
++
++		funcs->atomic_begin(crtc);
++	}
++
++	for (i = 0; i < nplanes; i++) {
++		struct drm_plane_helper_funcs *funcs;
++		struct drm_plane *plane = old_state->planes[i];
++		struct drm_plane_state *old_plane_state;
++
++		if (!plane)
++			continue;
++
++		funcs = plane->helper_private;
++
++		if (!funcs || !funcs->atomic_update)
++			continue;
++
++		old_plane_state = old_state->plane_states[i];
++
++		funcs->atomic_update(plane, old_plane_state);
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc_helper_funcs *funcs;
++		struct drm_crtc *crtc = old_state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		funcs = crtc->helper_private;
++
++		if (!funcs || !funcs->atomic_flush)
++			continue;
++
++		funcs->atomic_flush(crtc);
++	}
++}
++EXPORT_SYMBOL(drm_atomic_helper_commit_planes);
++
++/**
++ * drm_atomic_helper_cleanup_planes - cleanup plane resources after commit
++ * @dev: DRM device
++ * @old_state: atomic state object with old state structures
++ *
++ * This function cleans up plane state, specifically framebuffers, from the old
++ * configuration. Hence the old configuration must be perserved in @old_state to
++ * be able to call this function.
++ *
++ * This function must also be called on the new state when the atomic update
++ * fails at any point after calling drm_atomic_helper_prepare_planes().
++ */
++void drm_atomic_helper_cleanup_planes(struct drm_device *dev,
++				      struct drm_atomic_state *old_state)
++{
++	int nplanes = dev->mode_config.num_total_plane;
++	int i;
++
++	for (i = 0; i < nplanes; i++) {
++		struct drm_plane_helper_funcs *funcs;
++		struct drm_plane *plane = old_state->planes[i];
++		struct drm_framebuffer *old_fb;
++
++		if (!plane)
++			continue;
++
++		funcs = plane->helper_private;
++
++		old_fb = old_state->plane_states[i]->fb;
++
++		if (old_fb && funcs->cleanup_fb)
++			funcs->cleanup_fb(plane, old_fb);
++	}
++}
++EXPORT_SYMBOL(drm_atomic_helper_cleanup_planes);
++
++/**
++ * drm_atomic_helper_swap_state - store atomic state into current sw state
++ * @dev: DRM device
++ * @state: atomic state
++ *
++ * This function stores the atomic state into the current state pointers in all
++ * driver objects. It should be called after all failing steps have been done
++ * and succeeded, but before the actual hardware state is committed.
++ *
++ * For cleanup and error recovery the current state for all changed objects will
++ * be swaped into @state.
++ *
++ * With that sequence it fits perfectly into the plane prepare/cleanup sequence:
++ *
++ * 1. Call drm_atomic_helper_prepare_planes() with the staged atomic state.
++ *
++ * 2. Do any other steps that might fail.
++ *
++ * 3. Put the staged state into the current state pointers with this function.
++ *
++ * 4. Actually commit the hardware state.
++ *
++ * 5. Call drm_atomic_helper_cleanup_planes with @state, which since step 3
++ * contains the old state. Also do any other cleanup required with that state.
++ */
++void drm_atomic_helper_swap_state(struct drm_device *dev,
++				  struct drm_atomic_state *state)
++{
++	int i;
++
++	for (i = 0; i < dev->mode_config.num_connector; i++) {
++		struct drm_connector *connector = state->connectors[i];
++
++		if (!connector)
++			continue;
++
++		connector->state->state = state;
++		swap(state->connector_states[i], connector->state);
++		connector->state->state = NULL;
++	}
++
++	for (i = 0; i < dev->mode_config.num_crtc; i++) {
++		struct drm_crtc *crtc = state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		crtc->state->state = state;
++		swap(state->crtc_states[i], crtc->state);
++		crtc->state->state = NULL;
++	}
++
++	for (i = 0; i < dev->mode_config.num_total_plane; i++) {
++		struct drm_plane *plane = state->planes[i];
++
++		if (!plane)
++			continue;
++
++		plane->state->state = state;
++		swap(state->plane_states[i], plane->state);
++		plane->state->state = NULL;
++	}
++}
++EXPORT_SYMBOL(drm_atomic_helper_swap_state);
++
++/**
++ * drm_atomic_helper_update_plane - Helper for primary plane update using atomic
++ * @plane: plane object to update
++ * @crtc: owning CRTC of owning plane
++ * @fb: framebuffer to flip onto plane
++ * @crtc_x: x offset of primary plane on crtc
++ * @crtc_y: y offset of primary plane on crtc
++ * @crtc_w: width of primary plane rectangle on crtc
++ * @crtc_h: height of primary plane rectangle on crtc
++ * @src_x: x offset of @fb for panning
++ * @src_y: y offset of @fb for panning
++ * @src_w: width of source rectangle in @fb
++ * @src_h: height of source rectangle in @fb
++ *
++ * Provides a default plane update handler using the atomic driver interface.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int drm_atomic_helper_update_plane(struct drm_plane *plane,
++				   struct drm_crtc *crtc,
++				   struct drm_framebuffer *fb,
++				   int crtc_x, int crtc_y,
++				   unsigned int crtc_w, unsigned int crtc_h,
++				   uint32_t src_x, uint32_t src_y,
++				   uint32_t src_w, uint32_t src_h)
++{
++	struct drm_atomic_state *state;
++	struct drm_plane_state *plane_state;
++	int ret = 0;
++
++	state = drm_atomic_state_alloc(plane->dev);
++	if (!state)
++		return -ENOMEM;
++
++	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
++retry:
++	plane_state = drm_atomic_get_plane_state(state, plane);
++	if (IS_ERR(plane_state)) {
++		ret = PTR_ERR(plane_state);
++		goto fail;
++	}
++
++	ret = drm_atomic_set_crtc_for_plane(state, plane, crtc);
++	if (ret != 0)
++		goto fail;
++	drm_atomic_set_fb_for_plane(plane_state, fb);
++	plane_state->crtc_x = crtc_x;
++	plane_state->crtc_y = crtc_y;
++	plane_state->crtc_h = crtc_h;
++	plane_state->crtc_w = crtc_w;
++	plane_state->src_x = src_x;
++	plane_state->src_y = src_y;
++	plane_state->src_h = src_h;
++	plane_state->src_w = src_w;
++
++	ret = drm_atomic_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* Driver takes ownership of state on successful commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	/*
++	 * Someone might have exchanged the framebuffer while we dropped locks
++	 * in the backoff code. We need to fix up the fb refcount tracking the
++	 * core does for us.
++	 */
++	plane->old_fb = plane->fb;
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_update_plane);
++
++/**
++ * drm_atomic_helper_disable_plane - Helper for primary plane disable using * atomic
++ * @plane: plane to disable
++ *
++ * Provides a default plane disable handler using the atomic driver interface.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int drm_atomic_helper_disable_plane(struct drm_plane *plane)
++{
++	struct drm_atomic_state *state;
++	struct drm_plane_state *plane_state;
++	int ret = 0;
++
++	/*
++	 * FIXME: Without plane->crtc set we can't get at the implicit legacy
++	 * acquire context. The real fix will be to wire the acquire ctx through
++	 * everywhere we need it, but meanwhile prevent chaos by just skipping
++	 * this noop. The critical case is the cursor ioctls which a) only grab
++	 * crtc/cursor-plane locks (so we need the crtc to get at the right
++	 * acquire context) and b) can try to disable the plane multiple times.
++	 */
++	if (!plane->crtc)
++		return 0;
++
++	state = drm_atomic_state_alloc(plane->dev);
++	if (!state)
++		return -ENOMEM;
++
++	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(plane->crtc);
++retry:
++	plane_state = drm_atomic_get_plane_state(state, plane);
++	if (IS_ERR(plane_state)) {
++		ret = PTR_ERR(plane_state);
++		goto fail;
++	}
++
++	ret = drm_atomic_set_crtc_for_plane(state, plane, NULL);
++	if (ret != 0)
++		goto fail;
++	drm_atomic_set_fb_for_plane(plane_state, NULL);
++	plane_state->crtc_x = 0;
++	plane_state->crtc_y = 0;
++	plane_state->crtc_h = 0;
++	plane_state->crtc_w = 0;
++	plane_state->src_x = 0;
++	plane_state->src_y = 0;
++	plane_state->src_h = 0;
++	plane_state->src_w = 0;
++
++	ret = drm_atomic_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* Driver takes ownership of state on successful commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	/*
++	 * Someone might have exchanged the framebuffer while we dropped locks
++	 * in the backoff code. We need to fix up the fb refcount tracking the
++	 * core does for us.
++	 */
++	plane->old_fb = plane->fb;
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_disable_plane);
++
++static int update_output_state(struct drm_atomic_state *state,
++			       struct drm_mode_set *set)
++{
++	struct drm_device *dev = set->crtc->dev;
++	struct drm_connector_state *conn_state;
++	int ncrtcs = state->dev->mode_config.num_crtc;
++	int ret, i, j;
++
++	ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
++			       state->acquire_ctx);
++	if (ret)
++		return ret;
++
++	/* First grab all affected connector/crtc states. */
++	for (i = 0; i < set->num_connectors; i++) {
++		conn_state = drm_atomic_get_connector_state(state,
++							    set->connectors[i]);
++		if (IS_ERR(conn_state))
++			return PTR_ERR(conn_state);
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc *crtc = state->crtcs[i];
++
++		if (!crtc)
++			continue;
++
++		ret = drm_atomic_add_affected_connectors(state, crtc);
++		if (ret)
++			return ret;
++	}
++
++	/* Then recompute connector->crtc links and crtc enabling state. */
++	for (i = 0; i < state->num_connector; i++) {
++		struct drm_connector *connector;
++
++		connector = state->connectors[i];
++		conn_state = state->connector_states[i];
++
++		if (!connector)
++			continue;
++
++		if (conn_state->crtc == set->crtc) {
++			ret = drm_atomic_set_crtc_for_connector(conn_state,
++								NULL);
++			if (ret)
++				return ret;
++		}
++
++		for (j = 0; j < set->num_connectors; j++) {
++			if (set->connectors[j] == connector) {
++				ret = drm_atomic_set_crtc_for_connector(conn_state,
++									set->crtc);
++				if (ret)
++					return ret;
++				break;
++			}
++		}
++	}
++
++	for (i = 0; i < ncrtcs; i++) {
++		struct drm_crtc *crtc = state->crtcs[i];
++		struct drm_crtc_state *crtc_state = state->crtc_states[i];
++
++		if (!crtc)
++			continue;
++
++		/* Don't update ->enable for the CRTC in the set_config request,
++		 * since a mismatch would indicate a bug in the upper layers.
++		 * The actual modeset code later on will catch any
++		 * inconsistencies here. */
++		if (crtc == set->crtc)
++			continue;
++
++		crtc_state->enable =
++			drm_atomic_connectors_for_crtc(state, crtc);
++	}
++
++	return 0;
++}
++
++/**
++ * drm_atomic_helper_set_config - set a new config from userspace
++ * @set: mode set configuration
++ *
++ * Provides a default crtc set_config handler using the atomic driver interface.
++ *
++ * Returns:
++ * Returns 0 on success, negative errno numbers on failure.
++ */
++int drm_atomic_helper_set_config(struct drm_mode_set *set)
++{
++	struct drm_atomic_state *state;
++	struct drm_crtc *crtc = set->crtc;
++	struct drm_crtc_state *crtc_state;
++	struct drm_plane_state *primary_state;
++	int ret = 0;
++
++	state = drm_atomic_state_alloc(crtc->dev);
++	if (!state)
++		return -ENOMEM;
++
++	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
++retry:
++	crtc_state = drm_atomic_get_crtc_state(state, crtc);
++	if (IS_ERR(crtc_state)) {
++		ret = PTR_ERR(crtc_state);
++		goto fail;
++	}
++
++	primary_state = drm_atomic_get_plane_state(state, crtc->primary);
++	if (IS_ERR(primary_state)) {
++		ret = PTR_ERR(primary_state);
++		goto fail;
++	}
++
++	if (!set->mode) {
++		WARN_ON(set->fb);
++		WARN_ON(set->num_connectors);
++
++		crtc_state->enable = false;
++
++		ret = drm_atomic_set_crtc_for_plane(state, crtc->primary, NULL);
++		if (ret != 0)
++			goto fail;
++
++		drm_atomic_set_fb_for_plane(primary_state, NULL);
++
++		goto commit;
++	}
++
++	WARN_ON(!set->fb);
++	WARN_ON(!set->num_connectors);
++
++	crtc_state->enable = true;
++	drm_mode_copy(&crtc_state->mode, set->mode);
++
++	ret = drm_atomic_set_crtc_for_plane(state, crtc->primary, crtc);
++	if (ret != 0)
++		goto fail;
++	drm_atomic_set_fb_for_plane(primary_state, set->fb);
++	primary_state->crtc_x = 0;
++	primary_state->crtc_y = 0;
++	primary_state->crtc_h = set->mode->vdisplay;
++	primary_state->crtc_w = set->mode->hdisplay;
++	primary_state->src_x = set->x << 16;
++	primary_state->src_y = set->y << 16;
++	primary_state->src_h = set->mode->vdisplay << 16;
++	primary_state->src_w = set->mode->hdisplay << 16;
++
++commit:
++	ret = update_output_state(state, set);
++	if (ret)
++		goto fail;
++
++	ret = drm_atomic_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* Driver takes ownership of state on successful commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	/*
++	 * Someone might have exchanged the framebuffer while we dropped locks
++	 * in the backoff code. We need to fix up the fb refcount tracking the
++	 * core does for us.
++	 */
++	crtc->primary->old_fb = crtc->primary->fb;
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_set_config);
++
++/**
++ * drm_atomic_helper_crtc_set_property - helper for crtc prorties
++ * @crtc: DRM crtc
++ * @property: DRM property
++ * @val: value of property
++ *
++ * Provides a default plane disablle handler using the atomic driver interface.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int
++drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc,
++				    struct drm_property *property,
++				    uint64_t val)
++{
++	struct drm_atomic_state *state;
++	struct drm_crtc_state *crtc_state;
++	int ret = 0;
++
++	state = drm_atomic_state_alloc(crtc->dev);
++	if (!state)
++		return -ENOMEM;
++
++	/* ->set_property is always called with all locks held. */
++	state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
++retry:
++	crtc_state = drm_atomic_get_crtc_state(state, crtc);
++	if (IS_ERR(crtc_state)) {
++		ret = PTR_ERR(crtc_state);
++		goto fail;
++	}
++
++	ret = crtc->funcs->atomic_set_property(crtc, crtc_state,
++					       property, val);
++	if (ret)
++		goto fail;
++
++	ret = drm_atomic_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* Driver takes ownership of state on successful commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_crtc_set_property);
++
++/**
++ * drm_atomic_helper_plane_set_property - helper for plane prorties
++ * @plane: DRM plane
++ * @property: DRM property
++ * @val: value of property
++ *
++ * Provides a default plane disable handler using the atomic driver interface.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int
++drm_atomic_helper_plane_set_property(struct drm_plane *plane,
++				    struct drm_property *property,
++				    uint64_t val)
++{
++	struct drm_atomic_state *state;
++	struct drm_plane_state *plane_state;
++	int ret = 0;
++
++	state = drm_atomic_state_alloc(plane->dev);
++	if (!state)
++		return -ENOMEM;
++
++	/* ->set_property is always called with all locks held. */
++	state->acquire_ctx = plane->dev->mode_config.acquire_ctx;
++retry:
++	plane_state = drm_atomic_get_plane_state(state, plane);
++	if (IS_ERR(plane_state)) {
++		ret = PTR_ERR(plane_state);
++		goto fail;
++	}
++
++	ret = plane->funcs->atomic_set_property(plane, plane_state,
++					       property, val);
++	if (ret)
++		goto fail;
++
++	ret = drm_atomic_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* Driver takes ownership of state on successful commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_plane_set_property);
++
++/**
++ * drm_atomic_helper_connector_set_property - helper for connector prorties
++ * @connector: DRM connector
++ * @property: DRM property
++ * @val: value of property
++ *
++ * Provides a default plane disablle handler using the atomic driver interface.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int
++drm_atomic_helper_connector_set_property(struct drm_connector *connector,
++				    struct drm_property *property,
++				    uint64_t val)
++{
++	struct drm_atomic_state *state;
++	struct drm_connector_state *connector_state;
++	int ret = 0;
++
++	state = drm_atomic_state_alloc(connector->dev);
++	if (!state)
++		return -ENOMEM;
++
++	/* ->set_property is always called with all locks held. */
++	state->acquire_ctx = connector->dev->mode_config.acquire_ctx;
++retry:
++	connector_state = drm_atomic_get_connector_state(state, connector);
++	if (IS_ERR(connector_state)) {
++		ret = PTR_ERR(connector_state);
++		goto fail;
++	}
++
++	ret = connector->funcs->atomic_set_property(connector, connector_state,
++					       property, val);
++	if (ret)
++		goto fail;
++
++	ret = drm_atomic_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* Driver takes ownership of state on successful commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_connector_set_property);
++
++/**
++ * drm_atomic_helper_page_flip - execute a legacy page flip
++ * @crtc: DRM crtc
++ * @fb: DRM framebuffer
++ * @event: optional DRM event to signal upon completion
++ * @flags: flip flags for non-vblank sync'ed updates
++ *
++ * Provides a default page flip implementation using the atomic driver interface.
++ *
++ * Note that for now so called async page flips (i.e. updates which are not
++ * synchronized to vblank) are not supported, since the atomic interfaces have
++ * no provisions for this yet.
++ *
++ * Returns:
++ * Returns 0 on success, negative errno numbers on failure.
++ */
++int drm_atomic_helper_page_flip(struct drm_crtc *crtc,
++				struct drm_framebuffer *fb,
++				struct drm_pending_vblank_event *event,
++				uint32_t flags)
++{
++	struct drm_plane *plane = crtc->primary;
++	struct drm_atomic_state *state;
++	struct drm_plane_state *plane_state;
++	struct drm_crtc_state *crtc_state;
++	int ret = 0;
++
++	if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
++		return -EINVAL;
++
++	state = drm_atomic_state_alloc(plane->dev);
++	if (!state)
++		return -ENOMEM;
++
++	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
++retry:
++	crtc_state = drm_atomic_get_crtc_state(state, crtc);
++	if (IS_ERR(crtc_state)) {
++		ret = PTR_ERR(crtc_state);
++		goto fail;
++	}
++	crtc_state->event = event;
++
++	plane_state = drm_atomic_get_plane_state(state, plane);
++	if (IS_ERR(plane_state)) {
++		ret = PTR_ERR(plane_state);
++		goto fail;
++	}
++
++	ret = drm_atomic_set_crtc_for_plane(state, plane, crtc);
++	if (ret != 0)
++		goto fail;
++	drm_atomic_set_fb_for_plane(plane_state, fb);
++
++	ret = drm_atomic_async_commit(state);
++	if (ret != 0)
++		goto fail;
++
++	/* TODO: ->page_flip is the only driver callback where the core
++	 * doesn't update plane->fb. For now patch it up here. */
++	plane->fb = plane->state->fb;
++
++	/* Driver takes ownership of state on successful async commit. */
++	return 0;
++fail:
++	if (ret == -EDEADLK)
++		goto backoff;
++
++	drm_atomic_state_free(state);
++
++	return ret;
++backoff:
++	drm_atomic_state_clear(state);
++	drm_atomic_legacy_backoff(state);
++
++	/*
++	 * Someone might have exchanged the framebuffer while we dropped locks
++	 * in the backoff code. We need to fix up the fb refcount tracking the
++	 * core does for us.
++	 */
++	plane->old_fb = plane->fb;
++
++	goto retry;
++}
++EXPORT_SYMBOL(drm_atomic_helper_page_flip);
++
++/**
++ * DOC: atomic state reset and initialization
++ *
++ * Both the drm core and the atomic helpers assume that there is always the full
++ * and correct atomic software state for all connectors, CRTCs and planes
++ * available. Which is a bit a problem on driver load and also after system
++ * suspend. One way to solve this is to have a hardware state read-out
++ * infrastructure which reconstructs the full software state (e.g. the i915
++ * driver).
++ *
++ * The simpler solution is to just reset the software state to everything off,
++ * which is easiest to do by calling drm_mode_config_reset(). To facilitate this
++ * the atomic helpers provide default reset implementations for all hooks.
++ */
++
++/**
++ * drm_atomic_helper_crtc_reset - default ->reset hook for CRTCs
++ * @crtc: drm CRTC
++ *
++ * Resets the atomic state for @crtc by freeing the state pointer (which might
++ * be NULL, e.g. at driver load time) and allocating a new empty state object.
++ */
++void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc)
++{
++	kfree(crtc->state);
++	crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL);
++}
++EXPORT_SYMBOL(drm_atomic_helper_crtc_reset);
++
++/**
++ * drm_atomic_helper_crtc_duplicate_state - default state duplicate hook
++ * @crtc: drm CRTC
++ *
++ * Default CRTC state duplicate hook for drivers which don't have their own
++ * subclassed CRTC state structure.
++ */
++struct drm_crtc_state *
++drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc)
++{
++	struct drm_crtc_state *state;
++
++	if (WARN_ON(!crtc->state))
++		return NULL;
++
++	state = kmemdup(crtc->state, sizeof(*crtc->state), GFP_KERNEL);
++
++	if (state) {
++		state->mode_changed = false;
++		state->planes_changed = false;
++		state->event = NULL;
++	}
++
++	return state;
++}
++EXPORT_SYMBOL(drm_atomic_helper_crtc_duplicate_state);
++
++/**
++ * drm_atomic_helper_crtc_destroy_state - default state destroy hook
++ * @crtc: drm CRTC
++ * @state: CRTC state object to release
++ *
++ * Default CRTC state destroy hook for drivers which don't have their own
++ * subclassed CRTC state structure.
++ */
++void drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
++					  struct drm_crtc_state *state)
++{
++	kfree(state);
++}
++EXPORT_SYMBOL(drm_atomic_helper_crtc_destroy_state);
++
++/**
++ * drm_atomic_helper_plane_reset - default ->reset hook for planes
++ * @plane: drm plane
++ *
++ * Resets the atomic state for @plane by freeing the state pointer (which might
++ * be NULL, e.g. at driver load time) and allocating a new empty state object.
++ */
++void drm_atomic_helper_plane_reset(struct drm_plane *plane)
++{
++	if (plane->state && plane->state->fb)
++		drm_framebuffer_unreference(plane->state->fb);
++
++	kfree(plane->state);
++	plane->state = kzalloc(sizeof(*plane->state), GFP_KERNEL);
++}
++EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
++
++/**
++ * drm_atomic_helper_plane_duplicate_state - default state duplicate hook
++ * @plane: drm plane
++ *
++ * Default plane state duplicate hook for drivers which don't have their own
++ * subclassed plane state structure.
++ */
++struct drm_plane_state *
++drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane)
++{
++	struct drm_plane_state *state;
++
++	if (WARN_ON(!plane->state))
++		return NULL;
++
++	state = kmemdup(plane->state, sizeof(*plane->state), GFP_KERNEL);
++
++	if (state && state->fb)
++		drm_framebuffer_reference(state->fb);
++
++	return state;
++}
++EXPORT_SYMBOL(drm_atomic_helper_plane_duplicate_state);
++
++/**
++ * drm_atomic_helper_plane_destroy_state - default state destroy hook
++ * @plane: drm plane
++ * @state: plane state object to release
++ *
++ * Default plane state destroy hook for drivers which don't have their own
++ * subclassed plane state structure.
++ */
++void drm_atomic_helper_plane_destroy_state(struct drm_plane *plane,
++					   struct drm_plane_state *state)
++{
++	if (state->fb)
++		drm_framebuffer_unreference(state->fb);
++
++	kfree(state);
++}
++EXPORT_SYMBOL(drm_atomic_helper_plane_destroy_state);
++
++/**
++ * drm_atomic_helper_connector_reset - default ->reset hook for connectors
++ * @connector: drm connector
++ *
++ * Resets the atomic state for @connector by freeing the state pointer (which
++ * might be NULL, e.g. at driver load time) and allocating a new empty state
++ * object.
++ */
++void drm_atomic_helper_connector_reset(struct drm_connector *connector)
++{
++	kfree(connector->state);
++	connector->state = kzalloc(sizeof(*connector->state), GFP_KERNEL);
++}
++EXPORT_SYMBOL(drm_atomic_helper_connector_reset);
++
++/**
++ * drm_atomic_helper_connector_duplicate_state - default state duplicate hook
++ * @connector: drm connector
++ *
++ * Default connector state duplicate hook for drivers which don't have their own
++ * subclassed connector state structure.
++ */
++struct drm_connector_state *
++drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector)
++{
++	if (WARN_ON(!connector->state))
++		return NULL;
++
++	return kmemdup(connector->state, sizeof(*connector->state), GFP_KERNEL);
++}
++EXPORT_SYMBOL(drm_atomic_helper_connector_duplicate_state);
++
++/**
++ * drm_atomic_helper_connector_destroy_state - default state destroy hook
++ * @connector: drm connector
++ * @state: connector state object to release
++ *
++ * Default connector state destroy hook for drivers which don't have their own
++ * subclassed connector state structure.
++ */
++void drm_atomic_helper_connector_destroy_state(struct drm_connector *connector,
++					  struct drm_connector_state *state)
++{
++	kfree(state);
++}
++EXPORT_SYMBOL(drm_atomic_helper_connector_destroy_state);
+diff -Naur a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
+--- a/drivers/gpu/drm/drm_auth.c	2015-03-26 14:43:30.430436436 +0530
++++ b/drivers/gpu/drm/drm_auth.c	2015-03-26 14:42:38.706435421 +0530
+@@ -34,6 +34,13 @@
+  */
+ 
+ #include <drm/drmP.h>
++#include "drm_internal.h"
++
++struct drm_magic_entry {
++	struct list_head head;
++	struct drm_hash_item hash_item;
++	struct drm_file *priv;
++};
+ 
+ /**
+  * Find the file with the given magic number.
+diff -Naur a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
+--- a/drivers/gpu/drm/drm_bufs.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_bufs.c	2015-03-26 14:42:38.706435421 +0530
+@@ -1,18 +1,13 @@
+-/**
+- * \file drm_bufs.c
+- * Generic buffer template
+- *
+- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+- * \author Gareth Hughes <gareth@valinux.com>
+- */
+-
+ /*
+- * Created: Thu Nov 23 03:10:50 2000 by gareth@valinux.com
++ * Legacy: Generic DRM Buffer Management
+  *
+  * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+  * All Rights Reserved.
+  *
++ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
++ * Author: Gareth Hughes <gareth@valinux.com>
++ *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+@@ -39,6 +34,7 @@
+ #include <linux/export.h>
+ #include <asm/shmparam.h>
+ #include <drm/drmP.h>
++#include "drm_legacy.h"
+ 
+ static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
+ 						  struct drm_local_map *map)
+@@ -363,11 +359,11 @@
+ 		list->master = dev->primary->master;
+ 	*maplist = list;
+ 	return 0;
+-	}
++}
+ 
+-int drm_addmap(struct drm_device * dev, resource_size_t offset,
+-	       unsigned int size, enum drm_map_type type,
+-	       enum drm_map_flags flags, struct drm_local_map ** map_ptr)
++int drm_legacy_addmap(struct drm_device * dev, resource_size_t offset,
++		      unsigned int size, enum drm_map_type type,
++		      enum drm_map_flags flags, struct drm_local_map **map_ptr)
+ {
+ 	struct drm_map_list *list;
+ 	int rc;
+@@ -377,8 +373,7 @@
+ 		*map_ptr = list->map;
+ 	return rc;
+ }
+-
+-EXPORT_SYMBOL(drm_addmap);
++EXPORT_SYMBOL(drm_legacy_addmap);
+ 
+ /**
+  * Ioctl to specify a range of memory that is available for mapping by a
+@@ -391,8 +386,8 @@
+  * \return zero on success or a negative value on error.
+  *
+  */
+-int drm_addmap_ioctl(struct drm_device *dev, void *data,
+-		     struct drm_file *file_priv)
++int drm_legacy_addmap_ioctl(struct drm_device *dev, void *data,
++			    struct drm_file *file_priv)
+ {
+ 	struct drm_map *map = data;
+ 	struct drm_map_list *maplist;
+@@ -429,9 +424,9 @@
+  * its being used, and free any associate resource (such as MTRR's) if it's not
+  * being on use.
+  *
+- * \sa drm_addmap
++ * \sa drm_legacy_addmap
+  */
+-int drm_rmmap_locked(struct drm_device *dev, struct drm_local_map *map)
++int drm_legacy_rmmap_locked(struct drm_device *dev, struct drm_local_map *map)
+ {
+ 	struct drm_map_list *r_list = NULL, *list_t;
+ 	drm_dma_handle_t dmah;
+@@ -478,26 +473,26 @@
+ 		dmah.vaddr = map->handle;
+ 		dmah.busaddr = map->offset;
+ 		dmah.size = map->size;
+-		__drm_pci_free(dev, &dmah);
++		__drm_legacy_pci_free(dev, &dmah);
+ 		break;
+ 	}
+ 	kfree(map);
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL(drm_rmmap_locked);
++EXPORT_SYMBOL(drm_legacy_rmmap_locked);
+ 
+-int drm_rmmap(struct drm_device *dev, struct drm_local_map *map)
++int drm_legacy_rmmap(struct drm_device *dev, struct drm_local_map *map)
+ {
+ 	int ret;
+ 
+ 	mutex_lock(&dev->struct_mutex);
+-	ret = drm_rmmap_locked(dev, map);
++	ret = drm_legacy_rmmap_locked(dev, map);
+ 	mutex_unlock(&dev->struct_mutex);
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL(drm_rmmap);
++EXPORT_SYMBOL(drm_legacy_rmmap);
+ 
+ /* The rmmap ioctl appears to be unnecessary.  All mappings are torn down on
+  * the last close of the device, and this is necessary for cleanup when things
+@@ -514,8 +509,8 @@
+  * \param arg pointer to a struct drm_map structure.
+  * \return zero on success or a negative value on error.
+  */
+-int drm_rmmap_ioctl(struct drm_device *dev, void *data,
+-		    struct drm_file *file_priv)
++int drm_legacy_rmmap_ioctl(struct drm_device *dev, void *data,
++			   struct drm_file *file_priv)
+ {
+ 	struct drm_map *request = data;
+ 	struct drm_local_map *map = NULL;
+@@ -546,7 +541,7 @@
+ 		return 0;
+ 	}
+ 
+-	ret = drm_rmmap_locked(dev, map);
++	ret = drm_legacy_rmmap_locked(dev, map);
+ 
+ 	mutex_unlock(&dev->struct_mutex);
+ 
+@@ -599,7 +594,8 @@
+  * reallocates the buffer list of the same size order to accommodate the new
+  * buffers.
+  */
+-int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
++int drm_legacy_addbufs_agp(struct drm_device *dev,
++			   struct drm_buf_desc *request)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	struct drm_buf_entry *entry;
+@@ -656,13 +652,13 @@
+ 		DRM_DEBUG("zone invalid\n");
+ 		return -EINVAL;
+ 	}
+-	spin_lock(&dev->count_lock);
++	spin_lock(&dev->buf_lock);
+ 	if (dev->buf_use) {
+-		spin_unlock(&dev->count_lock);
++		spin_unlock(&dev->buf_lock);
+ 		return -EBUSY;
+ 	}
+ 	atomic_inc(&dev->buf_alloc);
+-	spin_unlock(&dev->count_lock);
++	spin_unlock(&dev->buf_lock);
+ 
+ 	mutex_lock(&dev->struct_mutex);
+ 	entry = &dma->bufs[order];
+@@ -759,10 +755,11 @@
+ 	atomic_dec(&dev->buf_alloc);
+ 	return 0;
+ }
+-EXPORT_SYMBOL(drm_addbufs_agp);
++EXPORT_SYMBOL(drm_legacy_addbufs_agp);
+ #endif				/* __OS_HAS_AGP */
+ 
+-int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
++int drm_legacy_addbufs_pci(struct drm_device *dev,
++			   struct drm_buf_desc *request)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	int count;
+@@ -805,13 +802,13 @@
+ 	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
+ 	total = PAGE_SIZE << page_order;
+ 
+-	spin_lock(&dev->count_lock);
++	spin_lock(&dev->buf_lock);
+ 	if (dev->buf_use) {
+-		spin_unlock(&dev->count_lock);
++		spin_unlock(&dev->buf_lock);
+ 		return -EBUSY;
+ 	}
+ 	atomic_inc(&dev->buf_alloc);
+-	spin_unlock(&dev->count_lock);
++	spin_unlock(&dev->buf_lock);
+ 
+ 	mutex_lock(&dev->struct_mutex);
+ 	entry = &dma->bufs[order];
+@@ -964,9 +961,10 @@
+ 	return 0;
+ 
+ }
+-EXPORT_SYMBOL(drm_addbufs_pci);
++EXPORT_SYMBOL(drm_legacy_addbufs_pci);
+ 
+-static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request)
++static int drm_legacy_addbufs_sg(struct drm_device *dev,
++				 struct drm_buf_desc *request)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	struct drm_buf_entry *entry;
+@@ -1015,13 +1013,13 @@
+ 	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
+ 		return -EINVAL;
+ 
+-	spin_lock(&dev->count_lock);
++	spin_lock(&dev->buf_lock);
+ 	if (dev->buf_use) {
+-		spin_unlock(&dev->count_lock);
++		spin_unlock(&dev->buf_lock);
+ 		return -EBUSY;
+ 	}
+ 	atomic_inc(&dev->buf_alloc);
+-	spin_unlock(&dev->count_lock);
++	spin_unlock(&dev->buf_lock);
+ 
+ 	mutex_lock(&dev->struct_mutex);
+ 	entry = &dma->bufs[order];
+@@ -1135,8 +1133,8 @@
+  * addbufs_sg() or addbufs_pci() for AGP, scatter-gather or consistent
+  * PCI memory respectively.
+  */
+-int drm_addbufs(struct drm_device *dev, void *data,
+-		struct drm_file *file_priv)
++int drm_legacy_addbufs(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv)
+ {
+ 	struct drm_buf_desc *request = data;
+ 	int ret;
+@@ -1149,15 +1147,15 @@
+ 
+ #if __OS_HAS_AGP
+ 	if (request->flags & _DRM_AGP_BUFFER)
+-		ret = drm_addbufs_agp(dev, request);
++		ret = drm_legacy_addbufs_agp(dev, request);
+ 	else
+ #endif
+ 	if (request->flags & _DRM_SG_BUFFER)
+-		ret = drm_addbufs_sg(dev, request);
++		ret = drm_legacy_addbufs_sg(dev, request);
+ 	else if (request->flags & _DRM_FB_BUFFER)
+ 		ret = -EINVAL;
+ 	else
+-		ret = drm_addbufs_pci(dev, request);
++		ret = drm_legacy_addbufs_pci(dev, request);
+ 
+ 	return ret;
+ }
+@@ -1175,12 +1173,12 @@
+  * \param arg pointer to a drm_buf_info structure.
+  * \return zero on success or a negative number on failure.
+  *
+- * Increments drm_device::buf_use while holding the drm_device::count_lock
++ * Increments drm_device::buf_use while holding the drm_device::buf_lock
+  * lock, preventing of allocating more buffers after this call. Information
+  * about each requested buffer is then copied into user space.
+  */
+-int drm_infobufs(struct drm_device *dev, void *data,
+-		 struct drm_file *file_priv)
++int drm_legacy_infobufs(struct drm_device *dev, void *data,
++			struct drm_file *file_priv)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	struct drm_buf_info *request = data;
+@@ -1196,13 +1194,13 @@
+ 	if (!dma)
+ 		return -EINVAL;
+ 
+-	spin_lock(&dev->count_lock);
++	spin_lock(&dev->buf_lock);
+ 	if (atomic_read(&dev->buf_alloc)) {
+-		spin_unlock(&dev->count_lock);
++		spin_unlock(&dev->buf_lock);
+ 		return -EBUSY;
+ 	}
+ 	++dev->buf_use;		/* Can't allocate more after this call */
+-	spin_unlock(&dev->count_lock);
++	spin_unlock(&dev->buf_lock);
+ 
+ 	for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) {
+ 		if (dma->bufs[i].buf_count)
+@@ -1217,7 +1215,6 @@
+ 				struct drm_buf_desc __user *to =
+ 				    &request->list[count];
+ 				struct drm_buf_entry *from = &dma->bufs[i];
+-				struct drm_freelist *list = &dma->bufs[i].freelist;
+ 				if (copy_to_user(&to->count,
+ 						 &from->buf_count,
+ 						 sizeof(from->buf_count)) ||
+@@ -1225,19 +1222,19 @@
+ 						 &from->buf_size,
+ 						 sizeof(from->buf_size)) ||
+ 				    copy_to_user(&to->low_mark,
+-						 &list->low_mark,
+-						 sizeof(list->low_mark)) ||
++						 &from->low_mark,
++						 sizeof(from->low_mark)) ||
+ 				    copy_to_user(&to->high_mark,
+-						 &list->high_mark,
+-						 sizeof(list->high_mark)))
++						 &from->high_mark,
++						 sizeof(from->high_mark)))
+ 					return -EFAULT;
+ 
+ 				DRM_DEBUG("%d %d %d %d %d\n",
+ 					  i,
+ 					  dma->bufs[i].buf_count,
+ 					  dma->bufs[i].buf_size,
+-					  dma->bufs[i].freelist.low_mark,
+-					  dma->bufs[i].freelist.high_mark);
++					  dma->bufs[i].low_mark,
++					  dma->bufs[i].high_mark);
+ 				++count;
+ 			}
+ 		}
+@@ -1261,8 +1258,8 @@
+  *
+  * \note This ioctl is deprecated and mostly never used.
+  */
+-int drm_markbufs(struct drm_device *dev, void *data,
+-		 struct drm_file *file_priv)
++int drm_legacy_markbufs(struct drm_device *dev, void *data,
++			struct drm_file *file_priv)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	struct drm_buf_desc *request = data;
+@@ -1290,8 +1287,8 @@
+ 	if (request->high_mark < 0 || request->high_mark > entry->buf_count)
+ 		return -EINVAL;
+ 
+-	entry->freelist.low_mark = request->low_mark;
+-	entry->freelist.high_mark = request->high_mark;
++	entry->low_mark = request->low_mark;
++	entry->high_mark = request->high_mark;
+ 
+ 	return 0;
+ }
+@@ -1308,8 +1305,8 @@
+  * Calls free_buffer() for each used buffer.
+  * This function is primarily used for debugging.
+  */
+-int drm_freebufs(struct drm_device *dev, void *data,
+-		 struct drm_file *file_priv)
++int drm_legacy_freebufs(struct drm_device *dev, void *data,
++			struct drm_file *file_priv)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	struct drm_buf_free *request = data;
+@@ -1341,7 +1338,7 @@
+ 				  task_pid_nr(current));
+ 			return -EINVAL;
+ 		}
+-		drm_free_buffer(dev, buf);
++		drm_legacy_free_buffer(dev, buf);
+ 	}
+ 
+ 	return 0;
+@@ -1361,8 +1358,8 @@
+  * offset equal to 0, which drm_mmap() interpretes as PCI buffers and calls
+  * drm_mmap_dma().
+  */
+-int drm_mapbufs(struct drm_device *dev, void *data,
+-	        struct drm_file *file_priv)
++int drm_legacy_mapbufs(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	int retcode = 0;
+@@ -1381,13 +1378,13 @@
+ 	if (!dma)
+ 		return -EINVAL;
+ 
+-	spin_lock(&dev->count_lock);
++	spin_lock(&dev->buf_lock);
+ 	if (atomic_read(&dev->buf_alloc)) {
+-		spin_unlock(&dev->count_lock);
++		spin_unlock(&dev->buf_lock);
+ 		return -EBUSY;
+ 	}
+ 	dev->buf_use++;		/* Can't allocate more after this call */
+-	spin_unlock(&dev->count_lock);
++	spin_unlock(&dev->buf_lock);
+ 
+ 	if (request->count >= dma->buf_count) {
+ 		if ((dev->agp && (dma->flags & _DRM_DMA_USE_AGP))
+@@ -1449,7 +1446,7 @@
+ 	return retcode;
+ }
+ 
+-int drm_dma_ioctl(struct drm_device *dev, void *data,
++int drm_legacy_dma_ioctl(struct drm_device *dev, void *data,
+ 		  struct drm_file *file_priv)
+ {
+ 	if (drm_core_check_feature(dev, DRIVER_MODESET))
+@@ -1461,7 +1458,7 @@
+ 		return -EINVAL;
+ }
+ 
+-struct drm_local_map *drm_getsarea(struct drm_device *dev)
++struct drm_local_map *drm_legacy_getsarea(struct drm_device *dev)
+ {
+ 	struct drm_map_list *entry;
+ 
+@@ -1473,4 +1470,4 @@
+ 	}
+ 	return NULL;
+ }
+-EXPORT_SYMBOL(drm_getsarea);
++EXPORT_SYMBOL(drm_legacy_getsarea);
+diff -Naur a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
+--- a/drivers/gpu/drm/drm_cache.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_cache.c	2015-03-26 14:42:38.706435421 +0530
+@@ -32,6 +32,12 @@
+ #include <drm/drmP.h>
+ 
+ #if defined(CONFIG_X86)
++
++/*
++ * clflushopt is an unordered instruction which needs fencing with mfence or
++ * sfence to avoid ordering issues.  For drm_clflush_page this fencing happens
++ * in the caller.
++ */
+ static void
+ drm_clflush_page(struct page *page)
+ {
+@@ -44,7 +50,7 @@
+ 
+ 	page_virtual = kmap_atomic(page);
+ 	for (i = 0; i < PAGE_SIZE; i += size)
+-		clflush(page_virtual + i);
++		clflushopt(page_virtual + i);
+ 	kunmap_atomic(page_virtual);
+ }
+ 
+@@ -125,15 +131,15 @@
+ EXPORT_SYMBOL(drm_clflush_sg);
+ 
+ void
+-drm_clflush_virt_range(char *addr, unsigned long length)
++drm_clflush_virt_range(void *addr, unsigned long length)
+ {
+ #if defined(CONFIG_X86)
+ 	if (cpu_has_clflush) {
+-		char *end = addr + length;
++		void *end = addr + length;
+ 		mb();
+ 		for (; addr < end; addr += boot_cpu_data.x86_clflush_size)
+-			clflush(addr);
+-		clflush(end - 1);
++			clflushopt(addr);
++		clflushopt(end - 1);
+ 		mb();
+ 		return;
+ 	}
+diff -Naur a/drivers/gpu/drm/drm_context.c b/drivers/gpu/drm/drm_context.c
+--- a/drivers/gpu/drm/drm_context.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/drm_context.c	2015-03-26 14:42:38.706435421 +0530
+@@ -1,18 +1,13 @@
+-/**
+- * \file drm_context.c
+- * IOCTLs for generic contexts
+- *
+- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+- * \author Gareth Hughes <gareth@valinux.com>
+- */
+-
+ /*
+- * Created: Fri Nov 24 18:31:37 2000 by gareth@valinux.com
++ * Legacy: Generic DRM Contexts
+  *
+  * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+  * All Rights Reserved.
+  *
++ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
++ * Author: Gareth Hughes <gareth@valinux.com>
++ *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+@@ -33,14 +28,14 @@
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+-/*
+- * ChangeLog:
+- *  2001-11-16	Torsten Duwe <duwe@caldera.de>
+- *		added context constructor/destructor hooks,
+- *		needed by SiS driver's memory management.
+- */
+-
+ #include <drm/drmP.h>
++#include "drm_legacy.h"
++
++struct drm_ctx_list {
++	struct list_head head;
++	drm_context_t handle;
++	struct drm_file *tag;
++};
+ 
+ /******************************************************************/
+ /** \name Context bitmap support */
+@@ -56,7 +51,7 @@
+  * in drm_device::ctx_idr, while holding the drm_device::struct_mutex
+  * lock.
+  */
+-void drm_ctxbitmap_free(struct drm_device * dev, int ctx_handle)
++void drm_legacy_ctxbitmap_free(struct drm_device * dev, int ctx_handle)
+ {
+ 	mutex_lock(&dev->struct_mutex);
+ 	idr_remove(&dev->ctx_idr, ctx_handle);
+@@ -72,7 +67,7 @@
+  * Allocate a new idr from drm_device::ctx_idr while holding the
+  * drm_device::struct_mutex lock.
+  */
+-static int drm_ctxbitmap_next(struct drm_device * dev)
++static int drm_legacy_ctxbitmap_next(struct drm_device * dev)
+ {
+ 	int ret;
+ 
+@@ -90,7 +85,7 @@
+  *
+  * Initialise the drm_device::ctx_idr
+  */
+-int drm_ctxbitmap_init(struct drm_device * dev)
++int drm_legacy_ctxbitmap_init(struct drm_device * dev)
+ {
+ 	idr_init(&dev->ctx_idr);
+ 	return 0;
+@@ -104,13 +99,43 @@
+  * Free all idr members using drm_ctx_sarea_free helper function
+  * while holding the drm_device::struct_mutex lock.
+  */
+-void drm_ctxbitmap_cleanup(struct drm_device * dev)
++void drm_legacy_ctxbitmap_cleanup(struct drm_device * dev)
+ {
+ 	mutex_lock(&dev->struct_mutex);
+ 	idr_destroy(&dev->ctx_idr);
+ 	mutex_unlock(&dev->struct_mutex);
+ }
+ 
++/**
++ * drm_ctxbitmap_flush() - Flush all contexts owned by a file
++ * @dev: DRM device to operate on
++ * @file: Open file to flush contexts for
++ *
++ * This iterates over all contexts on @dev and drops them if they're owned by
++ * @file. Note that after this call returns, new contexts might be added if
++ * the file is still alive.
++ */
++void drm_legacy_ctxbitmap_flush(struct drm_device *dev, struct drm_file *file)
++{
++	struct drm_ctx_list *pos, *tmp;
++
++	mutex_lock(&dev->ctxlist_mutex);
++
++	list_for_each_entry_safe(pos, tmp, &dev->ctxlist, head) {
++		if (pos->tag == file &&
++		    pos->handle != DRM_KERNEL_CONTEXT) {
++			if (dev->driver->context_dtor)
++				dev->driver->context_dtor(dev, pos->handle);
++
++			drm_legacy_ctxbitmap_free(dev, pos->handle);
++			list_del(&pos->head);
++			kfree(pos);
++		}
++	}
++
++	mutex_unlock(&dev->ctxlist_mutex);
++}
++
+ /*@}*/
+ 
+ /******************************************************************/
+@@ -129,8 +154,8 @@
+  * Gets the map from drm_device::ctx_idr with the handle specified and
+  * returns its handle.
+  */
+-int drm_getsareactx(struct drm_device *dev, void *data,
+-		    struct drm_file *file_priv)
++int drm_legacy_getsareactx(struct drm_device *dev, void *data,
++			   struct drm_file *file_priv)
+ {
+ 	struct drm_ctx_priv_map *request = data;
+ 	struct drm_local_map *map;
+@@ -173,8 +198,8 @@
+  * Searches the mapping specified in \p arg and update the entry in
+  * drm_device::ctx_idr with it.
+  */
+-int drm_setsareactx(struct drm_device *dev, void *data,
+-		    struct drm_file *file_priv)
++int drm_legacy_setsareactx(struct drm_device *dev, void *data,
++			   struct drm_file *file_priv)
+ {
+ 	struct drm_ctx_priv_map *request = data;
+ 	struct drm_local_map *map = NULL;
+@@ -273,8 +298,8 @@
+  * \param arg user argument pointing to a drm_ctx_res structure.
+  * \return zero on success or a negative number on failure.
+  */
+-int drm_resctx(struct drm_device *dev, void *data,
+-	       struct drm_file *file_priv)
++int drm_legacy_resctx(struct drm_device *dev, void *data,
++		      struct drm_file *file_priv)
+ {
+ 	struct drm_ctx_res *res = data;
+ 	struct drm_ctx ctx;
+@@ -304,16 +329,16 @@
+  *
+  * Get a new handle for the context and copy to userspace.
+  */
+-int drm_addctx(struct drm_device *dev, void *data,
+-	       struct drm_file *file_priv)
++int drm_legacy_addctx(struct drm_device *dev, void *data,
++		      struct drm_file *file_priv)
+ {
+ 	struct drm_ctx_list *ctx_entry;
+ 	struct drm_ctx *ctx = data;
+ 
+-	ctx->handle = drm_ctxbitmap_next(dev);
++	ctx->handle = drm_legacy_ctxbitmap_next(dev);
+ 	if (ctx->handle == DRM_KERNEL_CONTEXT) {
+ 		/* Skip kernel's context and get a new one. */
+-		ctx->handle = drm_ctxbitmap_next(dev);
++		ctx->handle = drm_legacy_ctxbitmap_next(dev);
+ 	}
+ 	DRM_DEBUG("%d\n", ctx->handle);
+ 	if (ctx->handle == -1) {
+@@ -348,7 +373,8 @@
+  * \param arg user argument pointing to a drm_ctx structure.
+  * \return zero on success or a negative number on failure.
+  */
+-int drm_getctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
++int drm_legacy_getctx(struct drm_device *dev, void *data,
++		      struct drm_file *file_priv)
+ {
+ 	struct drm_ctx *ctx = data;
+ 
+@@ -369,8 +395,8 @@
+  *
+  * Calls context_switch().
+  */
+-int drm_switchctx(struct drm_device *dev, void *data,
+-		  struct drm_file *file_priv)
++int drm_legacy_switchctx(struct drm_device *dev, void *data,
++			 struct drm_file *file_priv)
+ {
+ 	struct drm_ctx *ctx = data;
+ 
+@@ -389,8 +415,8 @@
+  *
+  * Calls context_switch_complete().
+  */
+-int drm_newctx(struct drm_device *dev, void *data,
+-	       struct drm_file *file_priv)
++int drm_legacy_newctx(struct drm_device *dev, void *data,
++		      struct drm_file *file_priv)
+ {
+ 	struct drm_ctx *ctx = data;
+ 
+@@ -411,8 +437,8 @@
+  *
+  * If not the special kernel context, calls ctxbitmap_free() to free the specified context.
+  */
+-int drm_rmctx(struct drm_device *dev, void *data,
+-	      struct drm_file *file_priv)
++int drm_legacy_rmctx(struct drm_device *dev, void *data,
++		     struct drm_file *file_priv)
+ {
+ 	struct drm_ctx *ctx = data;
+ 
+@@ -420,7 +446,7 @@
+ 	if (ctx->handle != DRM_KERNEL_CONTEXT) {
+ 		if (dev->driver->context_dtor)
+ 			dev->driver->context_dtor(dev, ctx->handle);
+-		drm_ctxbitmap_free(dev, ctx->handle);
++		drm_legacy_ctxbitmap_free(dev, ctx->handle);
+ 	}
+ 
+ 	mutex_lock(&dev->ctxlist_mutex);
+diff -Naur a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
+--- a/drivers/gpu/drm/drm_crtc.c	2015-03-26 14:43:30.426436436 +0530
++++ b/drivers/gpu/drm/drm_crtc.c	2015-03-26 14:42:38.710435421 +0530
+@@ -37,58 +37,14 @@
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_edid.h>
+ #include <drm/drm_fourcc.h>
++#include <drm/drm_modeset_lock.h>
+ 
+-/**
+- * drm_modeset_lock_all - take all modeset locks
+- * @dev: drm device
+- *
+- * This function takes all modeset locks, suitable where a more fine-grained
+- * scheme isn't (yet) implemented.
+- */
+-void drm_modeset_lock_all(struct drm_device *dev)
+-{
+-	struct drm_crtc *crtc;
+-
+-	mutex_lock(&dev->mode_config.mutex);
+-
+-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+-		mutex_lock_nest_lock(&crtc->mutex, &dev->mode_config.mutex);
+-}
+-EXPORT_SYMBOL(drm_modeset_lock_all);
+-
+-/**
+- * drm_modeset_unlock_all - drop all modeset locks
+- * @dev: device
+- */
+-void drm_modeset_unlock_all(struct drm_device *dev)
+-{
+-	struct drm_crtc *crtc;
+-
+-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+-		mutex_unlock(&crtc->mutex);
+-
+-	mutex_unlock(&dev->mode_config.mutex);
+-}
+-EXPORT_SYMBOL(drm_modeset_unlock_all);
+-
+-/**
+- * drm_warn_on_modeset_not_all_locked - check that all modeset locks are locked
+- * @dev: device
+- */
+-void drm_warn_on_modeset_not_all_locked(struct drm_device *dev)
+-{
+-	struct drm_crtc *crtc;
++#include "drm_crtc_internal.h"
++#include "drm_internal.h"
+ 
+-	/* Locking is currently fubar in the panic handler. */
+-	if (oops_in_progress)
+-		return;
+-
+-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+-		WARN_ON(!mutex_is_locked(&crtc->mutex));
+-
+-	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
+-}
+-EXPORT_SYMBOL(drm_warn_on_modeset_not_all_locked);
++static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
++							struct drm_mode_fb_cmd2 *r,
++							struct drm_file *file_priv);
+ 
+ /* Avoid boilerplate.  I'm tired of typing. */
+ #define DRM_ENUM_NAME_FN(fnname, list)				\
+@@ -114,6 +70,13 @@
+ 
+ DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list)
+ 
++static const struct drm_prop_enum_list drm_plane_type_enum_list[] =
++{
++	{ DRM_PLANE_TYPE_OVERLAY, "Overlay" },
++	{ DRM_PLANE_TYPE_PRIMARY, "Primary" },
++	{ DRM_PLANE_TYPE_CURSOR, "Cursor" },
++};
++
+ /*
+  * Optional properties
+  */
+@@ -125,6 +88,12 @@
+ 	{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
+ };
+ 
++static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
++	{ DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
++	{ DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
++	{ DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
++};
++
+ /*
+  * Non-global properties, but "required" for certain connectors.
+  */
+@@ -213,6 +182,17 @@
+ 	{ DRM_MODE_ENCODER_TVDAC, "TV" },
+ 	{ DRM_MODE_ENCODER_VIRTUAL, "Virtual" },
+ 	{ DRM_MODE_ENCODER_DSI, "DSI" },
++	{ DRM_MODE_ENCODER_DPMST, "DP MST" },
++};
++
++static const struct drm_prop_enum_list drm_subpixel_enum_list[] =
++{
++	{ SubPixelUnknown, "Unknown" },
++	{ SubPixelHorizontalRGB, "Horizontal RGB" },
++	{ SubPixelHorizontalBGR, "Horizontal BGR" },
++	{ SubPixelVerticalRGB, "Vertical RGB" },
++	{ SubPixelVerticalBGR, "Vertical BGR" },
++	{ SubPixelNone, "None" },
+ };
+ 
+ void drm_connector_ida_init(void)
+@@ -231,28 +211,13 @@
+ 		ida_destroy(&drm_connector_enum_list[i].ida);
+ }
+ 
+-const char *drm_get_encoder_name(const struct drm_encoder *encoder)
+-{
+-	static char buf[32];
+-
+-	snprintf(buf, 32, "%s-%d",
+-		 drm_encoder_enum_list[encoder->encoder_type].name,
+-		 encoder->base.id);
+-	return buf;
+-}
+-EXPORT_SYMBOL(drm_get_encoder_name);
+-
+-const char *drm_get_connector_name(const struct drm_connector *connector)
+-{
+-	static char buf[32];
+-
+-	snprintf(buf, 32, "%s-%d",
+-		 drm_connector_enum_list[connector->connector_type].name,
+-		 connector->connector_type_id);
+-	return buf;
+-}
+-EXPORT_SYMBOL(drm_get_connector_name);
+-
++/**
++ * drm_get_connector_status_name - return a string for connector status
++ * @status: connector status to compute name of
++ *
++ * In contrast to the other drm_get_*_name functions this one here returns a
++ * const pointer and hence is threadsafe.
++ */
+ const char *drm_get_connector_status_name(enum drm_connector_status status)
+ {
+ 	if (status == connector_status_connected)
+@@ -264,11 +229,33 @@
+ }
+ EXPORT_SYMBOL(drm_get_connector_status_name);
+ 
++/**
++ * drm_get_subpixel_order_name - return a string for a given subpixel enum
++ * @order: enum of subpixel_order
++ *
++ * Note you could abuse this and return something out of bounds, but that
++ * would be a caller error.  No unscrubbed user data should make it here.
++ */
++const char *drm_get_subpixel_order_name(enum subpixel_order order)
++{
++	return drm_subpixel_enum_list[order].name;
++}
++EXPORT_SYMBOL(drm_get_subpixel_order_name);
++
+ static char printable_char(int c)
+ {
+ 	return isascii(c) && isprint(c) ? c : '?';
+ }
+ 
++/**
++ * drm_get_format_name - return a string for drm fourcc format
++ * @format: format to compute name of
++ *
++ * Note that the buffer used by this function is globally shared and owned by
++ * the function itself.
++ *
++ * FIXME: This isn't really multithreading safe.
++ */
+ const char *drm_get_format_name(uint32_t format)
+ {
+ 	static char buf[32];
+@@ -286,26 +273,19 @@
+ }
+ EXPORT_SYMBOL(drm_get_format_name);
+ 
+-/**
+- * drm_mode_object_get - allocate a new modeset identifier
+- * @dev: DRM device
+- * @obj: object pointer, used to generate unique ID
+- * @obj_type: object type
+- *
+- * Create a unique identifier based on @ptr in @dev's identifier space.  Used
+- * for tracking modes, CRTCs and connectors.
+- *
+- * RETURNS:
+- * New unique (relative to other objects in @dev) integer identifier for the
+- * object.
++/*
++ * Internal function to assign a slot in the object idr and optionally
++ * register the object into the idr.
+  */
+-static int drm_mode_object_get(struct drm_device *dev,
+-			       struct drm_mode_object *obj, uint32_t obj_type)
++static int drm_mode_object_get_reg(struct drm_device *dev,
++				   struct drm_mode_object *obj,
++				   uint32_t obj_type,
++				   bool register_obj)
+ {
+ 	int ret;
+ 
+ 	mutex_lock(&dev->mode_config.idr_mutex);
+-	ret = idr_alloc(&dev->mode_config.crtc_idr, obj, 1, 0, GFP_KERNEL);
++	ret = idr_alloc(&dev->mode_config.crtc_idr, register_obj ? obj : NULL, 1, 0, GFP_KERNEL);
+ 	if (ret >= 0) {
+ 		/*
+ 		 * Set up the object linking under the protection of the idr
+@@ -320,20 +300,70 @@
+ }
+ 
+ /**
++ * drm_mode_object_get - allocate a new modeset identifier
++ * @dev: DRM device
++ * @obj: object pointer, used to generate unique ID
++ * @obj_type: object type
++ *
++ * Create a unique identifier based on @ptr in @dev's identifier space.  Used
++ * for tracking modes, CRTCs and connectors. Note that despite the _get postfix
++ * modeset identifiers are _not_ reference counted. Hence don't use this for
++ * reference counted modeset objects like framebuffers.
++ *
++ * Returns:
++ * New unique (relative to other objects in @dev) integer identifier for the
++ * object.
++ */
++int drm_mode_object_get(struct drm_device *dev,
++			struct drm_mode_object *obj, uint32_t obj_type)
++{
++	return drm_mode_object_get_reg(dev, obj, obj_type, true);
++}
++
++static void drm_mode_object_register(struct drm_device *dev,
++				     struct drm_mode_object *obj)
++{
++	mutex_lock(&dev->mode_config.idr_mutex);
++	idr_replace(&dev->mode_config.crtc_idr, obj, obj->id);
++	mutex_unlock(&dev->mode_config.idr_mutex);
++}
++
++/**
+  * drm_mode_object_put - free a modeset identifer
+  * @dev: DRM device
+  * @object: object to free
+  *
+- * Free @id from @dev's unique identifier pool.
++ * Free @id from @dev's unique identifier pool. Note that despite the _get
++ * postfix modeset identifiers are _not_ reference counted. Hence don't use this
++ * for reference counted modeset objects like framebuffers.
+  */
+-static void drm_mode_object_put(struct drm_device *dev,
+-				struct drm_mode_object *object)
++void drm_mode_object_put(struct drm_device *dev,
++			 struct drm_mode_object *object)
+ {
+ 	mutex_lock(&dev->mode_config.idr_mutex);
+ 	idr_remove(&dev->mode_config.crtc_idr, object->id);
+ 	mutex_unlock(&dev->mode_config.idr_mutex);
+ }
+ 
++static struct drm_mode_object *_object_find(struct drm_device *dev,
++		uint32_t id, uint32_t type)
++{
++	struct drm_mode_object *obj = NULL;
++
++	mutex_lock(&dev->mode_config.idr_mutex);
++	obj = idr_find(&dev->mode_config.crtc_idr, id);
++	if (obj && type != DRM_MODE_OBJECT_ANY && obj->type != type)
++		obj = NULL;
++	if (obj && obj->id != id)
++		obj = NULL;
++	/* don't leak out unref'd fb's */
++	if (obj && (obj->type == DRM_MODE_OBJECT_FB))
++		obj = NULL;
++	mutex_unlock(&dev->mode_config.idr_mutex);
++
++	return obj;
++}
++
+ /**
+  * drm_mode_object_find - look up a drm object with static lifetime
+  * @dev: drm device
+@@ -341,7 +371,9 @@
+  * @type: type of the mode object
+  *
+  * Note that framebuffers cannot be looked up with this functions - since those
+- * are reference counted, they need special treatment.
++ * are reference counted, they need special treatment.  Even with
++ * DRM_MODE_OBJECT_ANY (although that will simply return NULL
++ * rather than WARN_ON()).
+  */
+ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
+ 		uint32_t id, uint32_t type)
+@@ -351,13 +383,7 @@
+ 	/* Framebuffers are reference counted and need their own lookup
+ 	 * function.*/
+ 	WARN_ON(type == DRM_MODE_OBJECT_FB);
+-
+-	mutex_lock(&dev->mode_config.idr_mutex);
+-	obj = idr_find(&dev->mode_config.crtc_idr, id);
+-	if (!obj || (obj->type != type) || (obj->id != id))
+-		obj = NULL;
+-	mutex_unlock(&dev->mode_config.idr_mutex);
+-
++	obj = _object_find(dev, id, type);
+ 	return obj;
+ }
+ EXPORT_SYMBOL(drm_mode_object_find);
+@@ -377,7 +403,7 @@
+  * since all the fb attributes are invariant over its lifetime, no further
+  * locking but only correct reference counting is required.
+  *
+- * RETURNS:
++ * Returns:
+  * Zero on success, error code on failure.
+  */
+ int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb,
+@@ -395,9 +421,6 @@
+ 	if (ret)
+ 		goto out;
+ 
+-	/* Grab the idr reference. */
+-	drm_framebuffer_reference(fb);
+-
+ 	dev->mode_config.num_fb++;
+ 	list_add(&fb->head, &dev->mode_config.fb_list);
+ out:
+@@ -407,10 +430,34 @@
+ }
+ EXPORT_SYMBOL(drm_framebuffer_init);
+ 
++/* dev->mode_config.fb_lock must be held! */
++static void __drm_framebuffer_unregister(struct drm_device *dev,
++					 struct drm_framebuffer *fb)
++{
++	mutex_lock(&dev->mode_config.idr_mutex);
++	idr_remove(&dev->mode_config.crtc_idr, fb->base.id);
++	mutex_unlock(&dev->mode_config.idr_mutex);
++
++	fb->base.id = 0;
++}
++
+ static void drm_framebuffer_free(struct kref *kref)
+ {
+ 	struct drm_framebuffer *fb =
+ 			container_of(kref, struct drm_framebuffer, refcount);
++	struct drm_device *dev = fb->dev;
++
++	/*
++	 * The lookup idr holds a weak reference, which has not necessarily been
++	 * removed at this point. Check for that.
++	 */
++	mutex_lock(&dev->mode_config.fb_lock);
++	if (fb->base.id) {
++		/* Mark fb as reaped and drop idr ref. */
++		__drm_framebuffer_unregister(dev, fb);
++	}
++	mutex_unlock(&dev->mode_config.fb_lock);
++
+ 	fb->funcs->destroy(fb);
+ }
+ 
+@@ -438,7 +485,7 @@
+  *
+  * If successful, this grabs an additional reference to the framebuffer -
+  * callers need to make sure to eventually unreference the returned framebuffer
+- * again.
++ * again, using @drm_framebuffer_unreference.
+  */
+ struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev,
+ 					       uint32_t id)
+@@ -447,8 +494,10 @@
+ 
+ 	mutex_lock(&dev->mode_config.fb_lock);
+ 	fb = __drm_framebuffer_lookup(dev, id);
+-	if (fb)
+-		drm_framebuffer_reference(fb);
++	if (fb) {
++		if (!kref_get_unless_zero(&fb->refcount))
++			fb = NULL;
++	}
+ 	mutex_unlock(&dev->mode_config.fb_lock);
+ 
+ 	return fb;
+@@ -463,7 +512,7 @@
+  */
+ void drm_framebuffer_unreference(struct drm_framebuffer *fb)
+ {
+-	DRM_DEBUG("FB ID: %d\n", fb->base.id);
++	DRM_DEBUG("%p: FB ID: %d (%d)\n", fb, fb->base.id, atomic_read(&fb->refcount.refcount));
+ 	kref_put(&fb->refcount, drm_framebuffer_free);
+ }
+ EXPORT_SYMBOL(drm_framebuffer_unreference);
+@@ -471,10 +520,12 @@
+ /**
+  * drm_framebuffer_reference - incr the fb refcnt
+  * @fb: framebuffer
++ *
++ * This functions increments the fb's refcount.
+  */
+ void drm_framebuffer_reference(struct drm_framebuffer *fb)
+ {
+-	DRM_DEBUG("FB ID: %d\n", fb->base.id);
++	DRM_DEBUG("%p: FB ID: %d (%d)\n", fb, fb->base.id, atomic_read(&fb->refcount.refcount));
+ 	kref_get(&fb->refcount);
+ }
+ EXPORT_SYMBOL(drm_framebuffer_reference);
+@@ -486,23 +537,10 @@
+ 
+ static void __drm_framebuffer_unreference(struct drm_framebuffer *fb)
+ {
+-	DRM_DEBUG("FB ID: %d\n", fb->base.id);
++	DRM_DEBUG("%p: FB ID: %d (%d)\n", fb, fb->base.id, atomic_read(&fb->refcount.refcount));
+ 	kref_put(&fb->refcount, drm_framebuffer_free_bug);
+ }
+ 
+-/* dev->mode_config.fb_lock must be held! */
+-static void __drm_framebuffer_unregister(struct drm_device *dev,
+-					 struct drm_framebuffer *fb)
+-{
+-	mutex_lock(&dev->mode_config.idr_mutex);
+-	idr_remove(&dev->mode_config.crtc_idr, fb->base.id);
+-	mutex_unlock(&dev->mode_config.idr_mutex);
+-
+-	fb->base.id = 0;
+-
+-	__drm_framebuffer_unreference(fb);
+-}
+-
+ /**
+  * drm_framebuffer_unregister_private - unregister a private fb from the lookup idr
+  * @fb: fb to unregister
+@@ -527,8 +565,9 @@
+  * drm_framebuffer_cleanup - remove a framebuffer object
+  * @fb: framebuffer to remove
+  *
+- * Cleanup references to a user-created framebuffer. This function is intended
+- * to be used from the drivers ->destroy callback.
++ * Cleanup framebuffer. This function is intended to be used from the drivers
++ * ->destroy callback. It can also be used to clean up driver private
++ *  framebuffers embedded into a larger structure.
+  *
+  * Note that this function does not remove the fb from active usuage - if it is
+  * still used anywhere, hilarity can ensue since userspace could call getfb on
+@@ -591,7 +630,7 @@
+ 		drm_modeset_lock_all(dev);
+ 		/* remove from any CRTC */
+ 		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+-			if (crtc->fb == fb) {
++			if (crtc->primary->fb == fb) {
+ 				/* should turn off the crtc */
+ 				memset(&set, 0, sizeof(struct drm_mode_set));
+ 				set.crtc = crtc;
+@@ -613,45 +652,54 @@
+ }
+ EXPORT_SYMBOL(drm_framebuffer_remove);
+ 
++DEFINE_WW_CLASS(crtc_ww_class);
++
+ /**
+- * drm_crtc_init - Initialise a new CRTC object
++ * drm_crtc_init_with_planes - Initialise a new CRTC object with
++ *    specified primary and cursor planes.
+  * @dev: DRM device
+  * @crtc: CRTC object to init
++ * @primary: Primary plane for CRTC
++ * @cursor: Cursor plane for CRTC
+  * @funcs: callbacks for the new CRTC
+  *
+  * Inits a new object created as base part of a driver crtc object.
+  *
+- * RETURNS:
++ * Returns:
+  * Zero on success, error code on failure.
+  */
+-int drm_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
+-		   const struct drm_crtc_funcs *funcs)
++int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc,
++			      struct drm_plane *primary,
++			      struct drm_plane *cursor,
++			      const struct drm_crtc_funcs *funcs)
+ {
++	struct drm_mode_config *config = &dev->mode_config;
+ 	int ret;
+ 
+ 	crtc->dev = dev;
+ 	crtc->funcs = funcs;
+ 	crtc->invert_dimensions = false;
+ 
+-	drm_modeset_lock_all(dev);
+-	mutex_init(&crtc->mutex);
+-	mutex_lock_nest_lock(&crtc->mutex, &dev->mode_config.mutex);
+-
++	drm_modeset_lock_init(&crtc->mutex);
+ 	ret = drm_mode_object_get(dev, &crtc->base, DRM_MODE_OBJECT_CRTC);
+ 	if (ret)
+-		goto out;
++		return ret;
+ 
+ 	crtc->base.properties = &crtc->properties;
+ 
+-	list_add_tail(&crtc->head, &dev->mode_config.crtc_list);
+-	dev->mode_config.num_crtc++;
++	list_add_tail(&crtc->head, &config->crtc_list);
++	config->num_crtc++;
+ 
+- out:
+-	drm_modeset_unlock_all(dev);
++	crtc->primary = primary;
++	crtc->cursor = cursor;
++	if (primary)
++		primary->possible_crtcs = 1 << drm_crtc_index(crtc);
++	if (cursor)
++		cursor->possible_crtcs = 1 << drm_crtc_index(crtc);
+ 
+-	return ret;
++	return 0;
+ }
+-EXPORT_SYMBOL(drm_crtc_init);
++EXPORT_SYMBOL(drm_crtc_init_with_planes);
+ 
+ /**
+  * drm_crtc_cleanup - Clean up the core crtc usage
+@@ -668,9 +716,17 @@
+ 	kfree(crtc->gamma_store);
+ 	crtc->gamma_store = NULL;
+ 
++	drm_modeset_lock_fini(&crtc->mutex);
++
+ 	drm_mode_object_put(dev, &crtc->base);
+ 	list_del(&crtc->head);
+ 	dev->mode_config.num_crtc--;
++
++	WARN_ON(crtc->state && !crtc->funcs->atomic_destroy_state);
++	if (crtc->state && crtc->funcs->atomic_destroy_state)
++		crtc->funcs->atomic_destroy_state(crtc, crtc->state);
++
++	memset(crtc, 0, sizeof(*crtc));
+ }
+ EXPORT_SYMBOL(drm_crtc_cleanup);
+ 
+@@ -697,20 +753,6 @@
+ }
+ EXPORT_SYMBOL(drm_crtc_index);
+ 
+-/**
+- * drm_mode_probed_add - add a mode to a connector's probed mode list
+- * @connector: connector the new mode
+- * @mode: mode data
+- *
+- * Add @mode to @connector's mode list for later use.
+- */
+-void drm_mode_probed_add(struct drm_connector *connector,
+-			 struct drm_display_mode *mode)
+-{
+-	list_add_tail(&mode->head, &connector->probed_modes);
+-}
+-EXPORT_SYMBOL(drm_mode_probed_add);
+-
+ /*
+  * drm_mode_remove - remove and free a mode
+  * @connector: connector list to modify
+@@ -726,6 +768,58 @@
+ }
+ 
+ /**
++ * drm_connector_get_cmdline_mode - reads the user's cmdline mode
++ * @connector: connector to quwery
++ *
++ * The kernel supports per-connector configration of its consoles through
++ * use of the video= parameter. This function parses that option and
++ * extracts the user's specified mode (or enable/disable status) for a
++ * particular connector. This is typically only used during the early fbdev
++ * setup.
++ */
++static void drm_connector_get_cmdline_mode(struct drm_connector *connector)
++{
++	struct drm_cmdline_mode *mode = &connector->cmdline_mode;
++	char *option = NULL;
++
++	if (fb_get_options(connector->name, &option))
++		return;
++
++	if (!drm_mode_parse_command_line_for_connector(option,
++						       connector,
++						       mode))
++		return;
++
++	if (mode->force) {
++		const char *s;
++
++		switch (mode->force) {
++		case DRM_FORCE_OFF:
++			s = "OFF";
++			break;
++		case DRM_FORCE_ON_DIGITAL:
++			s = "ON - dig";
++			break;
++		default:
++		case DRM_FORCE_ON:
++			s = "ON";
++			break;
++		}
++
++		DRM_INFO("forcing %s connector %s\n", connector->name, s);
++		connector->force = mode->force;
++	}
++
++	DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n",
++		      connector->name,
++		      mode->xres, mode->yres,
++		      mode->refresh_specified ? mode->refresh : 60,
++		      mode->rb ? " reduced blanking" : "",
++		      mode->margins ? " with margins" : "",
++		      mode->interlace ?  " interlaced" : "");
++}
++
++/**
+  * drm_connector_init - Init a preallocated connector
+  * @dev: DRM device
+  * @connector: the connector to init
+@@ -735,7 +829,7 @@
+  * Initialises a preallocated connector. Connectors should be
+  * subclassed as part of driver connector objects.
+  *
+- * RETURNS:
++ * Returns:
+  * Zero on success, error code on failure.
+  */
+ int drm_connector_init(struct drm_device *dev,
+@@ -749,9 +843,9 @@
+ 
+ 	drm_modeset_lock_all(dev);
+ 
+-	ret = drm_mode_object_get(dev, &connector->base, DRM_MODE_OBJECT_CONNECTOR);
++	ret = drm_mode_object_get_reg(dev, &connector->base, DRM_MODE_OBJECT_CONNECTOR, false);
+ 	if (ret)
+-		goto out;
++		goto out_unlock;
+ 
+ 	connector->base.properties = &connector->properties;
+ 	connector->dev = dev;
+@@ -761,14 +855,26 @@
+ 		ida_simple_get(connector_ida, 1, 0, GFP_KERNEL);
+ 	if (connector->connector_type_id < 0) {
+ 		ret = connector->connector_type_id;
+-		drm_mode_object_put(dev, &connector->base);
+-		goto out;
++		goto out_put;
+ 	}
++	connector->name =
++		kasprintf(GFP_KERNEL, "%s-%d",
++			  drm_connector_enum_list[connector_type].name,
++			  connector->connector_type_id);
++	if (!connector->name) {
++		ret = -ENOMEM;
++		goto out_put;
++	}
++
+ 	INIT_LIST_HEAD(&connector->probed_modes);
+ 	INIT_LIST_HEAD(&connector->modes);
+ 	connector->edid_blob_ptr = NULL;
+ 	connector->status = connector_status_unknown;
+ 
++	drm_connector_get_cmdline_mode(connector);
++
++	/* We should add connectors at the end to avoid upsetting the connector
++	 * index too much. */
+ 	list_add_tail(&connector->head, &dev->mode_config.connector_list);
+ 	dev->mode_config.num_connector++;
+ 
+@@ -780,7 +886,13 @@
+ 	drm_object_attach_property(&connector->base,
+ 				      dev->mode_config.dpms_property, 0);
+ 
+- out:
++	connector->debugfs_entry = NULL;
++
++out_put:
++	if (ret)
++		drm_mode_object_put(dev, &connector->base);
++
++out_unlock:
+ 	drm_modeset_unlock_all(dev);
+ 
+ 	return ret;
+@@ -798,6 +910,11 @@
+ 	struct drm_device *dev = connector->dev;
+ 	struct drm_display_mode *mode, *t;
+ 
++	if (connector->tile_group) {
++		drm_mode_put_tile_group(dev, connector->tile_group);
++		connector->tile_group = NULL;
++	}
++
+ 	list_for_each_entry_safe(mode, t, &connector->probed_modes, head)
+ 		drm_mode_remove(connector, mode);
+ 
+@@ -808,22 +925,120 @@
+ 		   connector->connector_type_id);
+ 
+ 	drm_mode_object_put(dev, &connector->base);
++	kfree(connector->name);
++	connector->name = NULL;
+ 	list_del(&connector->head);
+ 	dev->mode_config.num_connector--;
++
++	WARN_ON(connector->state && !connector->funcs->atomic_destroy_state);
++	if (connector->state && connector->funcs->atomic_destroy_state)
++		connector->funcs->atomic_destroy_state(connector,
++						       connector->state);
++
++	memset(connector, 0, sizeof(*connector));
+ }
+ EXPORT_SYMBOL(drm_connector_cleanup);
+ 
++/**
++ * drm_connector_index - find the index of a registered connector
++ * @connector: connector to find index for
++ *
++ * Given a registered connector, return the index of that connector within a DRM
++ * device's list of connectors.
++ */
++unsigned int drm_connector_index(struct drm_connector *connector)
++{
++	unsigned int index = 0;
++	struct drm_connector *tmp;
++	struct drm_mode_config *config = &connector->dev->mode_config;
++
++	WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
++
++	list_for_each_entry(tmp, &connector->dev->mode_config.connector_list, head) {
++		if (tmp == connector)
++			return index;
++
++		index++;
++	}
++
++	BUG();
++}
++EXPORT_SYMBOL(drm_connector_index);
++
++/**
++ * drm_connector_register - register a connector
++ * @connector: the connector to register
++ *
++ * Register userspace interfaces for a connector
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
++int drm_connector_register(struct drm_connector *connector)
++{
++	int ret;
++
++	drm_mode_object_register(connector->dev, &connector->base);
++
++	ret = drm_sysfs_connector_add(connector);
++	if (ret)
++		return ret;
++
++	ret = drm_debugfs_connector_add(connector);
++	if (ret) {
++		drm_sysfs_connector_remove(connector);
++		return ret;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_connector_register);
++
++/**
++ * drm_connector_unregister - unregister a connector
++ * @connector: the connector to unregister
++ *
++ * Unregister userspace interfaces for a connector
++ */
++void drm_connector_unregister(struct drm_connector *connector)
++{
++	drm_sysfs_connector_remove(connector);
++	drm_debugfs_connector_remove(connector);
++}
++EXPORT_SYMBOL(drm_connector_unregister);
++
++
++/**
++ * drm_connector_unplug_all - unregister connector userspace interfaces
++ * @dev: drm device
++ *
++ * This function unregisters all connector userspace interfaces in sysfs. Should
++ * be call when the device is disconnected, e.g. from an usb driver's
++ * ->disconnect callback.
++ */
+ void drm_connector_unplug_all(struct drm_device *dev)
+ {
+ 	struct drm_connector *connector;
+ 
+ 	/* taking the mode config mutex ends up in a clash with sysfs */
+ 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
+-		drm_sysfs_connector_remove(connector);
++		drm_connector_unregister(connector);
+ 
+ }
+ EXPORT_SYMBOL(drm_connector_unplug_all);
+ 
++/**
++ * drm_bridge_init - initialize a drm transcoder/bridge
++ * @dev: drm device
++ * @bridge: transcoder/bridge to set up
++ * @funcs: bridge function table
++ *
++ * Initialises a preallocated bridge. Bridges should be
++ * subclassed as part of driver connector objects.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
+ int drm_bridge_init(struct drm_device *dev, struct drm_bridge *bridge,
+ 		const struct drm_bridge_funcs *funcs)
+ {
+@@ -847,6 +1062,12 @@
+ }
+ EXPORT_SYMBOL(drm_bridge_init);
+ 
++/**
++ * drm_bridge_cleanup - cleans up an initialised bridge
++ * @bridge: bridge to cleanup
++ *
++ * Cleans up the bridge but doesn't free the object.
++ */
+ void drm_bridge_cleanup(struct drm_bridge *bridge)
+ {
+ 	struct drm_device *dev = bridge->dev;
+@@ -856,9 +1077,24 @@
+ 	list_del(&bridge->head);
+ 	dev->mode_config.num_bridge--;
+ 	drm_modeset_unlock_all(dev);
++
++	memset(bridge, 0, sizeof(*bridge));
+ }
+ EXPORT_SYMBOL(drm_bridge_cleanup);
+ 
++/**
++ * drm_encoder_init - Init a preallocated encoder
++ * @dev: drm device
++ * @encoder: the encoder to init
++ * @funcs: callbacks for this encoder
++ * @encoder_type: user visible type of the encoder
++ *
++ * Initialises a preallocated encoder. Encoder should be
++ * subclassed as part of driver encoder objects.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
+ int drm_encoder_init(struct drm_device *dev,
+ 		      struct drm_encoder *encoder,
+ 		      const struct drm_encoder_funcs *funcs,
+@@ -870,61 +1106,81 @@
+ 
+ 	ret = drm_mode_object_get(dev, &encoder->base, DRM_MODE_OBJECT_ENCODER);
+ 	if (ret)
+-		goto out;
++		goto out_unlock;
+ 
+ 	encoder->dev = dev;
+ 	encoder->encoder_type = encoder_type;
+ 	encoder->funcs = funcs;
++	encoder->name = kasprintf(GFP_KERNEL, "%s-%d",
++				  drm_encoder_enum_list[encoder_type].name,
++				  encoder->base.id);
++	if (!encoder->name) {
++		ret = -ENOMEM;
++		goto out_put;
++	}
+ 
+ 	list_add_tail(&encoder->head, &dev->mode_config.encoder_list);
+ 	dev->mode_config.num_encoder++;
+ 
+- out:
++out_put:
++	if (ret)
++		drm_mode_object_put(dev, &encoder->base);
++
++out_unlock:
+ 	drm_modeset_unlock_all(dev);
+ 
+ 	return ret;
+ }
+ EXPORT_SYMBOL(drm_encoder_init);
+ 
++/**
++ * drm_encoder_cleanup - cleans up an initialised encoder
++ * @encoder: encoder to cleanup
++ *
++ * Cleans up the encoder but doesn't free the object.
++ */
+ void drm_encoder_cleanup(struct drm_encoder *encoder)
+ {
+ 	struct drm_device *dev = encoder->dev;
+ 	drm_modeset_lock_all(dev);
+ 	drm_mode_object_put(dev, &encoder->base);
++	kfree(encoder->name);
+ 	list_del(&encoder->head);
+ 	dev->mode_config.num_encoder--;
+ 	drm_modeset_unlock_all(dev);
++
++	memset(encoder, 0, sizeof(*encoder));
+ }
+ EXPORT_SYMBOL(drm_encoder_cleanup);
+ 
+ /**
+- * drm_plane_init - Initialise a new plane object
++ * drm_universal_plane_init - Initialize a new universal plane object
+  * @dev: DRM device
+  * @plane: plane object to init
+  * @possible_crtcs: bitmask of possible CRTCs
+  * @funcs: callbacks for the new plane
+  * @formats: array of supported formats (%DRM_FORMAT_*)
+  * @format_count: number of elements in @formats
+- * @priv: plane is private (hidden from userspace)?
++ * @type: type of plane (overlay, primary, cursor)
+  *
+- * Inits a new object created as base part of a driver plane object.
++ * Initializes a plane object of type @type.
+  *
+- * RETURNS:
++ * Returns:
+  * Zero on success, error code on failure.
+  */
+-int drm_plane_init(struct drm_device *dev, struct drm_plane *plane,
+-		   unsigned long possible_crtcs,
+-		   const struct drm_plane_funcs *funcs,
+-		   const uint32_t *formats, uint32_t format_count,
+-		   bool priv)
++int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane,
++			     unsigned long possible_crtcs,
++			     const struct drm_plane_funcs *funcs,
++			     const uint32_t *formats, uint32_t format_count,
++			     enum drm_plane_type type)
+ {
+ 	int ret;
+ 
+-	drm_modeset_lock_all(dev);
+-
+ 	ret = drm_mode_object_get(dev, &plane->base, DRM_MODE_OBJECT_PLANE);
+ 	if (ret)
+-		goto out;
++		return ret;
++
++	drm_modeset_lock_init(&plane->mutex);
+ 
+ 	plane->base.properties = &plane->properties;
+ 	plane->dev = dev;
+@@ -934,29 +1190,55 @@
+ 	if (!plane->format_types) {
+ 		DRM_DEBUG_KMS("out of memory when allocating plane\n");
+ 		drm_mode_object_put(dev, &plane->base);
+-		ret = -ENOMEM;
+-		goto out;
++		return -ENOMEM;
+ 	}
+ 
+ 	memcpy(plane->format_types, formats, format_count * sizeof(uint32_t));
+ 	plane->format_count = format_count;
+ 	plane->possible_crtcs = possible_crtcs;
++	plane->type = type;
+ 
+-	/* private planes are not exposed to userspace, but depending on
+-	 * display hardware, might be convenient to allow sharing programming
+-	 * for the scanout engine with the crtc implementation.
+-	 */
+-	if (!priv) {
+-		list_add_tail(&plane->head, &dev->mode_config.plane_list);
+-		dev->mode_config.num_plane++;
+-	} else {
+-		INIT_LIST_HEAD(&plane->head);
+-	}
++	list_add_tail(&plane->head, &dev->mode_config.plane_list);
++	dev->mode_config.num_total_plane++;
++	if (plane->type == DRM_PLANE_TYPE_OVERLAY)
++		dev->mode_config.num_overlay_plane++;
++
++	drm_object_attach_property(&plane->base,
++				   dev->mode_config.plane_type_property,
++				   plane->type);
+ 
+- out:
+-	drm_modeset_unlock_all(dev);
++	return 0;
++}
++EXPORT_SYMBOL(drm_universal_plane_init);
+ 
+-	return ret;
++/**
++ * drm_plane_init - Initialize a legacy plane
++ * @dev: DRM device
++ * @plane: plane object to init
++ * @possible_crtcs: bitmask of possible CRTCs
++ * @funcs: callbacks for the new plane
++ * @formats: array of supported formats (%DRM_FORMAT_*)
++ * @format_count: number of elements in @formats
++ * @is_primary: plane type (primary vs overlay)
++ *
++ * Legacy API to initialize a DRM plane.
++ *
++ * New drivers should call drm_universal_plane_init() instead.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
++int drm_plane_init(struct drm_device *dev, struct drm_plane *plane,
++		   unsigned long possible_crtcs,
++		   const struct drm_plane_funcs *funcs,
++		   const uint32_t *formats, uint32_t format_count,
++		   bool is_primary)
++{
++	enum drm_plane_type type;
++
++	type = is_primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
++	return drm_universal_plane_init(dev, plane, possible_crtcs, funcs,
++					formats, format_count, type);
+ }
+ EXPORT_SYMBOL(drm_plane_init);
+ 
+@@ -975,16 +1257,47 @@
+ 	drm_modeset_lock_all(dev);
+ 	kfree(plane->format_types);
+ 	drm_mode_object_put(dev, &plane->base);
+-	/* if not added to a list, it must be a private plane */
+-	if (!list_empty(&plane->head)) {
+-		list_del(&plane->head);
+-		dev->mode_config.num_plane--;
+-	}
++
++	BUG_ON(list_empty(&plane->head));
++
++	list_del(&plane->head);
++	dev->mode_config.num_total_plane--;
++	if (plane->type == DRM_PLANE_TYPE_OVERLAY)
++		dev->mode_config.num_overlay_plane--;
+ 	drm_modeset_unlock_all(dev);
++
++	WARN_ON(plane->state && !plane->funcs->atomic_destroy_state);
++	if (plane->state && plane->funcs->atomic_destroy_state)
++		plane->funcs->atomic_destroy_state(plane, plane->state);
++
++	memset(plane, 0, sizeof(*plane));
+ }
+ EXPORT_SYMBOL(drm_plane_cleanup);
+ 
+ /**
++ * drm_plane_index - find the index of a registered plane
++ * @plane: plane to find index for
++ *
++ * Given a registered plane, return the index of that CRTC within a DRM
++ * device's list of planes.
++ */
++unsigned int drm_plane_index(struct drm_plane *plane)
++{
++	unsigned int index = 0;
++	struct drm_plane *tmp;
++
++	list_for_each_entry(tmp, &plane->dev->mode_config.plane_list, head) {
++		if (tmp == plane)
++			return index;
++
++		index++;
++	}
++
++	BUG();
++}
++EXPORT_SYMBOL(drm_plane_index);
++
++/**
+  * drm_plane_force_disable - Forcibly disable a plane
+  * @plane: plane to disable
+  *
+@@ -1000,64 +1313,26 @@
+ 	if (!plane->fb)
+ 		return;
+ 
++	plane->old_fb = plane->fb;
+ 	ret = plane->funcs->disable_plane(plane);
+-	if (ret)
++	if (ret) {
+ 		DRM_ERROR("failed to disable plane with busy fb\n");
++		plane->old_fb = NULL;
++		return;
++	}
+ 	/* disconnect the plane from the fb and crtc: */
+-	__drm_framebuffer_unreference(plane->fb);
++	__drm_framebuffer_unreference(plane->old_fb);
++	plane->old_fb = NULL;
+ 	plane->fb = NULL;
+ 	plane->crtc = NULL;
+ }
+ EXPORT_SYMBOL(drm_plane_force_disable);
+ 
+-/**
+- * drm_mode_create - create a new display mode
+- * @dev: DRM device
+- *
+- * Create a new drm_display_mode, give it an ID, and return it.
+- *
+- * RETURNS:
+- * Pointer to new mode on success, NULL on error.
+- */
+-struct drm_display_mode *drm_mode_create(struct drm_device *dev)
+-{
+-	struct drm_display_mode *nmode;
+-
+-	nmode = kzalloc(sizeof(struct drm_display_mode), GFP_KERNEL);
+-	if (!nmode)
+-		return NULL;
+-
+-	if (drm_mode_object_get(dev, &nmode->base, DRM_MODE_OBJECT_MODE)) {
+-		kfree(nmode);
+-		return NULL;
+-	}
+-
+-	return nmode;
+-}
+-EXPORT_SYMBOL(drm_mode_create);
+-
+-/**
+- * drm_mode_destroy - remove a mode
+- * @dev: DRM device
+- * @mode: mode to remove
+- *
+- * Free @mode's unique identifier, then free it.
+- */
+-void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode)
+-{
+-	if (!mode)
+-		return;
+-
+-	drm_mode_object_put(dev, &mode->base);
+-
+-	kfree(mode);
+-}
+-EXPORT_SYMBOL(drm_mode_destroy);
+-
+ static int drm_mode_create_standard_connector_properties(struct drm_device *dev)
+ {
+ 	struct drm_property *edid;
+ 	struct drm_property *dpms;
++	struct drm_property *dev_path;
+ 
+ 	/*
+ 	 * Standard properties (apply to all connectors)
+@@ -1072,6 +1347,32 @@
+ 				   ARRAY_SIZE(drm_dpms_enum_list));
+ 	dev->mode_config.dpms_property = dpms;
+ 
++	dev_path = drm_property_create(dev,
++				       DRM_MODE_PROP_BLOB |
++				       DRM_MODE_PROP_IMMUTABLE,
++				       "PATH", 0);
++	dev->mode_config.path_property = dev_path;
++
++	dev->mode_config.tile_property = drm_property_create(dev,
++							     DRM_MODE_PROP_BLOB |
++							     DRM_MODE_PROP_IMMUTABLE,
++							     "TILE", 0);
++
++	return 0;
++}
++
++static int drm_mode_create_standard_plane_properties(struct drm_device *dev)
++{
++	struct drm_property *type;
++
++	/*
++	 * Standard properties (apply to all planes)
++	 */
++	type = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
++					"type", drm_plane_type_enum_list,
++					ARRAY_SIZE(drm_plane_type_enum_list));
++	dev->mode_config.plane_type_property = type;
++
+ 	return 0;
+ }
+ 
+@@ -1117,12 +1418,13 @@
+  * responsible for allocating a list of format names and passing them to
+  * this routine.
+  */
+-int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes,
++int drm_mode_create_tv_properties(struct drm_device *dev,
++				  unsigned int num_modes,
+ 				  char *modes[])
+ {
+ 	struct drm_property *tv_selector;
+ 	struct drm_property *tv_subconnector;
+-	int i;
++	unsigned int i;
+ 
+ 	if (dev->mode_config.tv_select_subconnector_property)
+ 		return 0;
+@@ -1213,6 +1515,33 @@
+ EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
+ 
+ /**
++ * drm_mode_create_aspect_ratio_property - create aspect ratio property
++ * @dev: DRM device
++ *
++ * Called by a driver the first time it's needed, must be attached to desired
++ * connectors.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
++int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
++{
++	if (dev->mode_config.aspect_ratio_property)
++		return 0;
++
++	dev->mode_config.aspect_ratio_property =
++		drm_property_create_enum(dev, 0, "aspect ratio",
++				drm_aspect_ratio_enum_list,
++				ARRAY_SIZE(drm_aspect_ratio_enum_list));
++
++	if (dev->mode_config.aspect_ratio_property == NULL)
++		return -ENOMEM;
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
++
++/**
+  * drm_mode_create_dirty_property - create dirty property
+  * @dev: DRM device
+  *
+@@ -1237,6 +1566,30 @@
+ }
+ EXPORT_SYMBOL(drm_mode_create_dirty_info_property);
+ 
++/**
++ * drm_mode_create_suggested_offset_properties - create suggests offset properties
++ * @dev: DRM device
++ *
++ * Create the the suggested x/y offset property for connectors.
++ */
++int drm_mode_create_suggested_offset_properties(struct drm_device *dev)
++{
++	if (dev->mode_config.suggested_x_property && dev->mode_config.suggested_y_property)
++		return 0;
++
++	dev->mode_config.suggested_x_property =
++		drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE, "suggested X", 0, 0xffffffff);
++
++	dev->mode_config.suggested_y_property =
++		drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE, "suggested Y", 0, 0xffffffff);
++
++	if (dev->mode_config.suggested_x_property == NULL ||
++	    dev->mode_config.suggested_y_property == NULL)
++		return -ENOMEM;
++	return 0;
++}
++EXPORT_SYMBOL(drm_mode_create_suggested_offset_properties);
++
+ static int drm_mode_group_init(struct drm_device *dev, struct drm_mode_group *group)
+ {
+ 	uint32_t total_objects = 0;
+@@ -1257,6 +1610,16 @@
+ 	return 0;
+ }
+ 
++void drm_mode_group_destroy(struct drm_mode_group *group)
++{
++	kfree(group->id_list);
++	group->id_list = NULL;
++}
++
++/*
++ * NOTE: Driver's shouldn't ever call drm_mode_group_init_legacy_group - it is
++ * the drm core's responsibility to set up mode control groups.
++ */
+ int drm_mode_group_init_legacy_group(struct drm_device *dev,
+ 				     struct drm_mode_group *group)
+ {
+@@ -1289,6 +1652,15 @@
+ }
+ EXPORT_SYMBOL(drm_mode_group_init_legacy_group);
+ 
++void drm_reinit_primary_mode_group(struct drm_device *dev)
++{
++	drm_modeset_lock_all(dev);
++	drm_mode_group_destroy(&dev->primary->mode_group);
++	drm_mode_group_init_legacy_group(dev, &dev->primary->mode_group);
++	drm_modeset_unlock_all(dev);
++}
++EXPORT_SYMBOL(drm_reinit_primary_mode_group);
++
+ /**
+  * drm_crtc_convert_to_umode - convert a drm_display_mode into a modeinfo
+  * @out: drm_mode_modeinfo struct to return to the user
+@@ -1333,8 +1705,8 @@
+  * Convert a drm_mode_modeinfo into a drm_display_mode structure to return to
+  * the caller.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ static int drm_crtc_convert_umode(struct drm_display_mode *out,
+ 				  const struct drm_mode_modeinfo *in)
+@@ -1376,8 +1748,8 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_getresources(struct drm_device *dev, void *data,
+ 			  struct drm_file *file_priv)
+@@ -1428,10 +1800,12 @@
+ 	card_res->count_fbs = fb_count;
+ 	mutex_unlock(&file_priv->fbs_lock);
+ 
+-	drm_modeset_lock_all(dev);
+-	mode_group = &file_priv->master->minor->mode_group;
+-	if (file_priv->master->minor->type == DRM_MINOR_CONTROL) {
++	/* mode_config.mutex protects the connector list against e.g. DP MST
++	 * connector hot-adding. CRTC/Plane lists are invariant. */
++	mutex_lock(&dev->mode_config.mutex);
++	if (!drm_is_primary_client(file_priv)) {
+ 
++		mode_group = NULL;
+ 		list_for_each(lh, &dev->mode_config.crtc_list)
+ 			crtc_count++;
+ 
+@@ -1442,6 +1816,7 @@
+ 			encoder_count++;
+ 	} else {
+ 
++		mode_group = &file_priv->master->minor->mode_group;
+ 		crtc_count = mode_group->num_crtcs;
+ 		connector_count = mode_group->num_connectors;
+ 		encoder_count = mode_group->num_encoders;
+@@ -1456,7 +1831,7 @@
+ 	if (card_res->count_crtcs >= crtc_count) {
+ 		copied = 0;
+ 		crtc_id = (uint32_t __user *)(unsigned long)card_res->crtc_id_ptr;
+-		if (file_priv->master->minor->type == DRM_MINOR_CONTROL) {
++		if (!mode_group) {
+ 			list_for_each_entry(crtc, &dev->mode_config.crtc_list,
+ 					    head) {
+ 				DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
+@@ -1483,12 +1858,12 @@
+ 	if (card_res->count_encoders >= encoder_count) {
+ 		copied = 0;
+ 		encoder_id = (uint32_t __user *)(unsigned long)card_res->encoder_id_ptr;
+-		if (file_priv->master->minor->type == DRM_MINOR_CONTROL) {
++		if (!mode_group) {
+ 			list_for_each_entry(encoder,
+ 					    &dev->mode_config.encoder_list,
+ 					    head) {
+ 				DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", encoder->base.id,
+-						drm_get_encoder_name(encoder));
++						encoder->name);
+ 				if (put_user(encoder->base.id, encoder_id +
+ 					     copied)) {
+ 					ret = -EFAULT;
+@@ -1514,13 +1889,13 @@
+ 	if (card_res->count_connectors >= connector_count) {
+ 		copied = 0;
+ 		connector_id = (uint32_t __user *)(unsigned long)card_res->connector_id_ptr;
+-		if (file_priv->master->minor->type == DRM_MINOR_CONTROL) {
++		if (!mode_group) {
+ 			list_for_each_entry(connector,
+ 					    &dev->mode_config.connector_list,
+ 					    head) {
+ 				DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
+ 					connector->base.id,
+-					drm_get_connector_name(connector));
++					connector->name);
+ 				if (put_user(connector->base.id,
+ 					     connector_id + copied)) {
+ 					ret = -EFAULT;
+@@ -1547,7 +1922,7 @@
+ 		  card_res->count_connectors, card_res->count_encoders);
+ 
+ out:
+-	drm_modeset_unlock_all(dev);
++	mutex_unlock(&dev->mode_config.mutex);
+ 	return ret;
+ }
+ 
+@@ -1561,35 +1936,28 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_getcrtc(struct drm_device *dev,
+ 		     void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_crtc *crtc_resp = data;
+ 	struct drm_crtc *crtc;
+-	struct drm_mode_object *obj;
+-	int ret = 0;
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 		return -EINVAL;
+ 
+-	drm_modeset_lock_all(dev);
+-
+-	obj = drm_mode_object_find(dev, crtc_resp->crtc_id,
+-				   DRM_MODE_OBJECT_CRTC);
+-	if (!obj) {
+-		ret = -ENOENT;
+-		goto out;
+-	}
+-	crtc = obj_to_crtc(obj);
++	crtc = drm_crtc_find(dev, crtc_resp->crtc_id);
++	if (!crtc)
++		return -ENOENT;
+ 
++	drm_modeset_lock_crtc(crtc, crtc->primary);
+ 	crtc_resp->x = crtc->x;
+ 	crtc_resp->y = crtc->y;
+ 	crtc_resp->gamma_size = crtc->gamma_size;
+-	if (crtc->fb)
+-		crtc_resp->fb_id = crtc->fb->base.id;
++	if (crtc->primary->fb)
++		crtc_resp->fb_id = crtc->primary->fb->base.id;
+ 	else
+ 		crtc_resp->fb_id = 0;
+ 
+@@ -1601,10 +1969,9 @@
+ 	} else {
+ 		crtc_resp->mode_valid = 0;
+ 	}
++	drm_modeset_unlock_crtc(crtc);
+ 
+-out:
+-	drm_modeset_unlock_all(dev);
+-	return ret;
++	return 0;
+ }
+ 
+ static bool drm_mode_expose_to_userspace(const struct drm_display_mode *mode,
+@@ -1620,6 +1987,15 @@
+ 	return true;
+ }
+ 
++static struct drm_encoder *drm_connector_get_encoder(struct drm_connector *connector)
++{
++	/* For atomic drivers only state objects are synchronously updated and
++	 * protected by modeset locks, so check those first. */
++	if (connector->state)
++		return connector->state->best_encoder;
++	return connector->encoder;
++}
++
+ /**
+  * drm_mode_getconnector - get connector configuration
+  * @dev: drm device for the ioctl
+@@ -1630,15 +2006,15 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_getconnector(struct drm_device *dev, void *data,
+ 			  struct drm_file *file_priv)
+ {
+ 	struct drm_mode_get_connector *out_resp = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_connector *connector;
++	struct drm_encoder *encoder;
+ 	struct drm_display_mode *mode;
+ 	int mode_count = 0;
+ 	int props_count = 0;
+@@ -1661,13 +2037,11 @@
+ 
+ 	mutex_lock(&dev->mode_config.mutex);
+ 
+-	obj = drm_mode_object_find(dev, out_resp->connector_id,
+-				   DRM_MODE_OBJECT_CONNECTOR);
+-	if (!obj) {
++	connector = drm_connector_find(dev, out_resp->connector_id);
++	if (!connector) {
+ 		ret = -ENOENT;
+ 		goto out;
+ 	}
+-	connector = obj_to_connector(obj);
+ 
+ 	props_count = connector->properties.count;
+ 
+@@ -1695,10 +2069,14 @@
+ 	out_resp->mm_height = connector->display_info.height_mm;
+ 	out_resp->subpixel = connector->display_info.subpixel_order;
+ 	out_resp->connection = connector->status;
+-	if (connector->encoder)
+-		out_resp->encoder_id = connector->encoder->base.id;
++	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
++
++	encoder = drm_connector_get_encoder(connector);
++	if (encoder)
++		out_resp->encoder_id = encoder->base.id;
+ 	else
+ 		out_resp->encoder_id = 0;
++	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ 
+ 	/*
+ 	 * This ioctl is called twice, once to determine how much space is
+@@ -1765,116 +2143,167 @@
+ 	return ret;
+ }
+ 
++static struct drm_crtc *drm_encoder_get_crtc(struct drm_encoder *encoder)
++{
++	struct drm_connector *connector;
++	struct drm_device *dev = encoder->dev;
++	bool uses_atomic = false;
++
++	/* For atomic drivers only state objects are synchronously updated and
++	 * protected by modeset locks, so check those first. */
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		if (!connector->state)
++			continue;
++
++		uses_atomic = true;
++
++		if (connector->state->best_encoder != encoder)
++			continue;
++
++		return connector->state->crtc;
++	}
++
++	/* Don't return stale data (e.g. pending async disable). */
++	if (uses_atomic)
++		return NULL;
++
++	return encoder->crtc;
++}
++
++/**
++ * drm_mode_getencoder - get encoder configuration
++ * @dev: drm device for the ioctl
++ * @data: data pointer for the ioctl
++ * @file_priv: drm file for the ioctl call
++ *
++ * Construct a encoder configuration structure to return to the user.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_getencoder(struct drm_device *dev, void *data,
+ 			struct drm_file *file_priv)
+ {
+ 	struct drm_mode_get_encoder *enc_resp = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_encoder *encoder;
+-	int ret = 0;
++	struct drm_crtc *crtc;
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 		return -EINVAL;
+ 
+-	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, enc_resp->encoder_id,
+-				   DRM_MODE_OBJECT_ENCODER);
+-	if (!obj) {
+-		ret = -ENOENT;
+-		goto out;
+-	}
+-	encoder = obj_to_encoder(obj);
++	encoder = drm_encoder_find(dev, enc_resp->encoder_id);
++	if (!encoder)
++		return -ENOENT;
+ 
+-	if (encoder->crtc)
++	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
++	crtc = drm_encoder_get_crtc(encoder);
++	if (crtc)
++		enc_resp->crtc_id = crtc->base.id;
++	else if (encoder->crtc)
+ 		enc_resp->crtc_id = encoder->crtc->base.id;
+ 	else
+ 		enc_resp->crtc_id = 0;
++	drm_modeset_unlock(&dev->mode_config.connection_mutex);
++
+ 	enc_resp->encoder_type = encoder->encoder_type;
+ 	enc_resp->encoder_id = encoder->base.id;
+ 	enc_resp->possible_crtcs = encoder->possible_crtcs;
+ 	enc_resp->possible_clones = encoder->possible_clones;
+ 
+-out:
+-	drm_modeset_unlock_all(dev);
+-	return ret;
++	return 0;
+ }
+ 
+ /**
+- * drm_mode_getplane_res - get plane info
++ * drm_mode_getplane_res - enumerate all plane resources
+  * @dev: DRM device
+  * @data: ioctl data
+  * @file_priv: DRM file info
+  *
+- * Return an plane count and set of IDs.
++ * Construct a list of plane ids to return to the user.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_getplane_res(struct drm_device *dev, void *data,
+-			    struct drm_file *file_priv)
++			  struct drm_file *file_priv)
+ {
+ 	struct drm_mode_get_plane_res *plane_resp = data;
+ 	struct drm_mode_config *config;
+ 	struct drm_plane *plane;
+ 	uint32_t __user *plane_ptr;
+-	int copied = 0, ret = 0;
++	int copied = 0;
++	unsigned num_planes;
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 		return -EINVAL;
+ 
+-	drm_modeset_lock_all(dev);
+ 	config = &dev->mode_config;
+ 
++	if (file_priv->universal_planes)
++		num_planes = config->num_total_plane;
++	else
++		num_planes = config->num_overlay_plane;
++
+ 	/*
+ 	 * This ioctl is called twice, once to determine how much space is
+ 	 * needed, and the 2nd time to fill it.
+ 	 */
+-	if (config->num_plane &&
+-	    (plane_resp->count_planes >= config->num_plane)) {
++	if (num_planes &&
++	    (plane_resp->count_planes >= num_planes)) {
+ 		plane_ptr = (uint32_t __user *)(unsigned long)plane_resp->plane_id_ptr;
+ 
++		/* Plane lists are invariant, no locking needed. */
+ 		list_for_each_entry(plane, &config->plane_list, head) {
+-			if (put_user(plane->base.id, plane_ptr + copied)) {
+-				ret = -EFAULT;
+-				goto out;
+-			}
++			/*
++			 * Unless userspace set the 'universal planes'
++			 * capability bit, only advertise overlays.
++			 */
++			if (plane->type != DRM_PLANE_TYPE_OVERLAY &&
++			    !file_priv->universal_planes)
++				continue;
++
++			if (put_user(plane->base.id, plane_ptr + copied))
++				return -EFAULT;
+ 			copied++;
+ 		}
+ 	}
+-	plane_resp->count_planes = config->num_plane;
++	plane_resp->count_planes = num_planes;
+ 
+-out:
+-	drm_modeset_unlock_all(dev);
+-	return ret;
++	return 0;
+ }
+ 
+ /**
+- * drm_mode_getplane - get plane info
++ * drm_mode_getplane - get plane configuration
+  * @dev: DRM device
+  * @data: ioctl data
+  * @file_priv: DRM file info
+  *
+- * Return plane info, including formats supported, gamma size, any
+- * current fb, etc.
++ * Construct a plane configuration structure to return to the user.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_getplane(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv)
++		      struct drm_file *file_priv)
+ {
+ 	struct drm_mode_get_plane *plane_resp = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_plane *plane;
+ 	uint32_t __user *format_ptr;
+-	int ret = 0;
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 		return -EINVAL;
+ 
+-	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, plane_resp->plane_id,
+-				   DRM_MODE_OBJECT_PLANE);
+-	if (!obj) {
+-		ret = -ENOENT;
+-		goto out;
+-	}
+-	plane = obj_to_plane(obj);
++	plane = drm_plane_find(dev, plane_resp->plane_id);
++	if (!plane)
++		return -ENOENT;
+ 
++	drm_modeset_lock(&plane->mutex, NULL);
+ 	if (plane->crtc)
+ 		plane_resp->crtc_id = plane->crtc->base.id;
+ 	else
+@@ -1884,6 +2313,7 @@
+ 		plane_resp->fb_id = plane->fb->base.id;
+ 	else
+ 		plane_resp->fb_id = 0;
++	drm_modeset_unlock(&plane->mutex);
+ 
+ 	plane_resp->plane_id = plane->base.id;
+ 	plane_resp->possible_crtcs = plane->possible_crtcs;
+@@ -1899,80 +2329,53 @@
+ 		if (copy_to_user(format_ptr,
+ 				 plane->format_types,
+ 				 sizeof(uint32_t) * plane->format_count)) {
+-			ret = -EFAULT;
+-			goto out;
++			return -EFAULT;
+ 		}
+ 	}
+ 	plane_resp->count_format_types = plane->format_count;
+ 
+-out:
+-	drm_modeset_unlock_all(dev);
+-	return ret;
++	return 0;
+ }
+ 
+-/**
+- * drm_mode_setplane - set up or tear down an plane
+- * @dev: DRM device
+- * @data: ioctl data*
+- * @file_priv: DRM file info
++/*
++ * setplane_internal - setplane handler for internal callers
+  *
+- * Set plane info, including placement, fb, scaling, and other factors.
+- * Or pass a NULL fb to disable.
+- */
+-int drm_mode_setplane(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv)
++ * Note that we assume an extra reference has already been taken on fb.  If the
++ * update fails, this reference will be dropped before return; if it succeeds,
++ * the previous framebuffer (if any) will be unreferenced instead.
++ *
++ * src_{x,y,w,h} are provided in 16.16 fixed point format
++ */
++static int __setplane_internal(struct drm_plane *plane,
++			       struct drm_crtc *crtc,
++			       struct drm_framebuffer *fb,
++			       int32_t crtc_x, int32_t crtc_y,
++			       uint32_t crtc_w, uint32_t crtc_h,
++			       /* src_{x,y,w,h} values are 16.16 fixed point */
++			       uint32_t src_x, uint32_t src_y,
++			       uint32_t src_w, uint32_t src_h)
+ {
+-	struct drm_mode_set_plane *plane_req = data;
+-	struct drm_mode_object *obj;
+-	struct drm_plane *plane;
+-	struct drm_crtc *crtc;
+-	struct drm_framebuffer *fb = NULL, *old_fb = NULL;
+ 	int ret = 0;
+ 	unsigned int fb_width, fb_height;
+-	int i;
+-
+-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+-		return -EINVAL;
+-
+-	/*
+-	 * First, find the plane, crtc, and fb objects.  If not available,
+-	 * we don't bother to call the driver.
+-	 */
+-	obj = drm_mode_object_find(dev, plane_req->plane_id,
+-				   DRM_MODE_OBJECT_PLANE);
+-	if (!obj) {
+-		DRM_DEBUG_KMS("Unknown plane ID %d\n",
+-			      plane_req->plane_id);
+-		return -ENOENT;
+-	}
+-	plane = obj_to_plane(obj);
++	unsigned int i;
+ 
+ 	/* No fb means shut it down */
+-	if (!plane_req->fb_id) {
+-		drm_modeset_lock_all(dev);
+-		old_fb = plane->fb;
+-		plane->funcs->disable_plane(plane);
+-		plane->crtc = NULL;
+-		plane->fb = NULL;
+-		drm_modeset_unlock_all(dev);
+-		goto out;
+-	}
+-
+-	obj = drm_mode_object_find(dev, plane_req->crtc_id,
+-				   DRM_MODE_OBJECT_CRTC);
+-	if (!obj) {
+-		DRM_DEBUG_KMS("Unknown crtc ID %d\n",
+-			      plane_req->crtc_id);
+-		ret = -ENOENT;
++	if (!fb) {
++		plane->old_fb = plane->fb;
++		ret = plane->funcs->disable_plane(plane);
++		if (!ret) {
++			plane->crtc = NULL;
++			plane->fb = NULL;
++		} else {
++			plane->old_fb = NULL;
++		}
+ 		goto out;
+ 	}
+-	crtc = obj_to_crtc(obj);
+ 
+-	fb = drm_framebuffer_lookup(dev, plane_req->fb_id);
+-	if (!fb) {
+-		DRM_DEBUG_KMS("Unknown framebuffer ID %d\n",
+-			      plane_req->fb_id);
+-		ret = -ENOENT;
++	/* Check whether this plane is usable on this CRTC */
++	if (!(plane->possible_crtcs & drm_crtc_mask(crtc))) {
++		DRM_DEBUG_KMS("Invalid crtc for plane\n");
++		ret = -EINVAL;
+ 		goto out;
+ 	}
+ 
+@@ -1991,24 +2394,86 @@
+ 	fb_height = fb->height << 16;
+ 
+ 	/* Make sure source coordinates are inside the fb. */
+-	if (plane_req->src_w > fb_width ||
+-	    plane_req->src_x > fb_width - plane_req->src_w ||
+-	    plane_req->src_h > fb_height ||
+-	    plane_req->src_y > fb_height - plane_req->src_h) {
++	if (src_w > fb_width ||
++	    src_x > fb_width - src_w ||
++	    src_h > fb_height ||
++	    src_y > fb_height - src_h) {
+ 		DRM_DEBUG_KMS("Invalid source coordinates "
+ 			      "%u.%06ux%u.%06u+%u.%06u+%u.%06u\n",
+-			      plane_req->src_w >> 16,
+-			      ((plane_req->src_w & 0xffff) * 15625) >> 10,
+-			      plane_req->src_h >> 16,
+-			      ((plane_req->src_h & 0xffff) * 15625) >> 10,
+-			      plane_req->src_x >> 16,
+-			      ((plane_req->src_x & 0xffff) * 15625) >> 10,
+-			      plane_req->src_y >> 16,
+-			      ((plane_req->src_y & 0xffff) * 15625) >> 10);
++			      src_w >> 16, ((src_w & 0xffff) * 15625) >> 10,
++			      src_h >> 16, ((src_h & 0xffff) * 15625) >> 10,
++			      src_x >> 16, ((src_x & 0xffff) * 15625) >> 10,
++			      src_y >> 16, ((src_y & 0xffff) * 15625) >> 10);
+ 		ret = -ENOSPC;
+ 		goto out;
+ 	}
+ 
++	plane->old_fb = plane->fb;
++	ret = plane->funcs->update_plane(plane, crtc, fb,
++					 crtc_x, crtc_y, crtc_w, crtc_h,
++					 src_x, src_y, src_w, src_h);
++	if (!ret) {
++		plane->crtc = crtc;
++		plane->fb = fb;
++		fb = NULL;
++	} else {
++		plane->old_fb = NULL;
++	}
++
++out:
++	if (fb)
++		drm_framebuffer_unreference(fb);
++	if (plane->old_fb)
++		drm_framebuffer_unreference(plane->old_fb);
++	plane->old_fb = NULL;
++
++	return ret;
++}
++
++static int setplane_internal(struct drm_plane *plane,
++			     struct drm_crtc *crtc,
++			     struct drm_framebuffer *fb,
++			     int32_t crtc_x, int32_t crtc_y,
++			     uint32_t crtc_w, uint32_t crtc_h,
++			     /* src_{x,y,w,h} values are 16.16 fixed point */
++			     uint32_t src_x, uint32_t src_y,
++			     uint32_t src_w, uint32_t src_h)
++{
++	int ret;
++
++	drm_modeset_lock_all(plane->dev);
++	ret = __setplane_internal(plane, crtc, fb,
++				  crtc_x, crtc_y, crtc_w, crtc_h,
++				  src_x, src_y, src_w, src_h);
++	drm_modeset_unlock_all(plane->dev);
++
++	return ret;
++}
++
++/**
++ * drm_mode_setplane - configure a plane's configuration
++ * @dev: DRM device
++ * @data: ioctl data*
++ * @file_priv: DRM file info
++ *
++ * Set plane configuration, including placement, fb, scaling, and other factors.
++ * Or pass a NULL fb to disable (planes may be disabled without providing a
++ * valid crtc).
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
++int drm_mode_setplane(struct drm_device *dev, void *data,
++		      struct drm_file *file_priv)
++{
++	struct drm_mode_set_plane *plane_req = data;
++	struct drm_plane *plane;
++	struct drm_crtc *crtc = NULL;
++	struct drm_framebuffer *fb = NULL;
++
++	if (!drm_core_check_feature(dev, DRIVER_MODESET))
++		return -EINVAL;
++
+ 	/* Give drivers some help against integer overflows */
+ 	if (plane_req->crtc_w > INT_MAX ||
+ 	    plane_req->crtc_x > INT_MAX - (int32_t) plane_req->crtc_w ||
+@@ -2017,31 +2482,45 @@
+ 		DRM_DEBUG_KMS("Invalid CRTC coordinates %ux%u+%d+%d\n",
+ 			      plane_req->crtc_w, plane_req->crtc_h,
+ 			      plane_req->crtc_x, plane_req->crtc_y);
+-		ret = -ERANGE;
+-		goto out;
++		return -ERANGE;
+ 	}
+ 
+-	drm_modeset_lock_all(dev);
+-	ret = plane->funcs->update_plane(plane, crtc, fb,
+-					 plane_req->crtc_x, plane_req->crtc_y,
+-					 plane_req->crtc_w, plane_req->crtc_h,
+-					 plane_req->src_x, plane_req->src_y,
+-					 plane_req->src_w, plane_req->src_h);
+-	if (!ret) {
+-		old_fb = plane->fb;
+-		plane->crtc = crtc;
+-		plane->fb = fb;
+-		fb = NULL;
++	/*
++	 * First, find the plane, crtc, and fb objects.  If not available,
++	 * we don't bother to call the driver.
++	 */
++	plane = drm_plane_find(dev, plane_req->plane_id);
++	if (!plane) {
++		DRM_DEBUG_KMS("Unknown plane ID %d\n",
++			      plane_req->plane_id);
++		return -ENOENT;
+ 	}
+-	drm_modeset_unlock_all(dev);
+ 
+-out:
+-	if (fb)
+-		drm_framebuffer_unreference(fb);
+-	if (old_fb)
+-		drm_framebuffer_unreference(old_fb);
++	if (plane_req->fb_id) {
++		fb = drm_framebuffer_lookup(dev, plane_req->fb_id);
++		if (!fb) {
++			DRM_DEBUG_KMS("Unknown framebuffer ID %d\n",
++				      plane_req->fb_id);
++			return -ENOENT;
++		}
+ 
+-	return ret;
++		crtc = drm_crtc_find(dev, plane_req->crtc_id);
++		if (!crtc) {
++			DRM_DEBUG_KMS("Unknown crtc ID %d\n",
++				      plane_req->crtc_id);
++			return -ENOENT;
++		}
++	}
++
++	/*
++	 * setplane_internal will take care of deref'ing either the old or new
++	 * framebuffer depending on success.
++	 */
++	return setplane_internal(plane, crtc, fb,
++				 plane_req->crtc_x, plane_req->crtc_y,
++				 plane_req->crtc_w, plane_req->crtc_h,
++				 plane_req->src_x, plane_req->src_y,
++				 plane_req->src_w, plane_req->src_h);
+ }
+ 
+ /**
+@@ -2050,6 +2529,9 @@
+  *
+  * This is a little helper to wrap internal calls to the ->set_config driver
+  * interface. The only thing it adds is correct refcounting dance.
++ * 
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_set_config_internal(struct drm_mode_set *set)
+ {
+@@ -2064,35 +2546,41 @@
+ 	 * crtcs. Atomic modeset will have saner semantics ...
+ 	 */
+ 	list_for_each_entry(tmp, &crtc->dev->mode_config.crtc_list, head)
+-		tmp->old_fb = tmp->fb;
++		tmp->primary->old_fb = tmp->primary->fb;
+ 
+ 	fb = set->fb;
+ 
+ 	ret = crtc->funcs->set_config(set);
+ 	if (ret == 0) {
+-		/* crtc->fb must be updated by ->set_config, enforces this. */
+-		WARN_ON(fb != crtc->fb);
++		crtc->primary->crtc = crtc;
++		crtc->primary->fb = fb;
+ 	}
+ 
+ 	list_for_each_entry(tmp, &crtc->dev->mode_config.crtc_list, head) {
+-		if (tmp->fb)
+-			drm_framebuffer_reference(tmp->fb);
+-		if (tmp->old_fb)
+-			drm_framebuffer_unreference(tmp->old_fb);
++		if (tmp->primary->fb)
++			drm_framebuffer_reference(tmp->primary->fb);
++		if (tmp->primary->old_fb)
++			drm_framebuffer_unreference(tmp->primary->old_fb);
++		tmp->primary->old_fb = NULL;
+ 	}
+ 
+ 	return ret;
+ }
+ EXPORT_SYMBOL(drm_mode_set_config_internal);
+ 
+-/*
+- * Checks that the framebuffer is big enough for the CRTC viewport
+- * (x, y, hdisplay, vdisplay)
+- */
+-static int drm_crtc_check_viewport(const struct drm_crtc *crtc,
+-				   int x, int y,
+-				   const struct drm_display_mode *mode,
+-				   const struct drm_framebuffer *fb)
++/**
++ * drm_crtc_check_viewport - Checks that a framebuffer is big enough for the
++ *     CRTC viewport
++ * @crtc: CRTC that framebuffer will be displayed on
++ * @x: x panning
++ * @y: y panning
++ * @mode: mode that framebuffer will be displayed under
++ * @fb: framebuffer to check size of
++ */
++int drm_crtc_check_viewport(const struct drm_crtc *crtc,
++			    int x, int y,
++			    const struct drm_display_mode *mode,
++			    const struct drm_framebuffer *fb)
+ 
+ {
+ 	int hdisplay, vdisplay;
+@@ -2123,6 +2611,7 @@
+ 
+ 	return 0;
+ }
++EXPORT_SYMBOL(drm_crtc_check_viewport);
+ 
+ /**
+  * drm_mode_setcrtc - set CRTC configuration
+@@ -2134,15 +2623,14 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_setcrtc(struct drm_device *dev, void *data,
+ 		     struct drm_file *file_priv)
+ {
+ 	struct drm_mode_config *config = &dev->mode_config;
+ 	struct drm_mode_crtc *crtc_req = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_crtc *crtc;
+ 	struct drm_connector **connector_set = NULL, *connector;
+ 	struct drm_framebuffer *fb = NULL;
+@@ -2160,26 +2648,24 @@
+ 		return -ERANGE;
+ 
+ 	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, crtc_req->crtc_id,
+-				   DRM_MODE_OBJECT_CRTC);
+-	if (!obj) {
++	crtc = drm_crtc_find(dev, crtc_req->crtc_id);
++	if (!crtc) {
+ 		DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id);
+ 		ret = -ENOENT;
+ 		goto out;
+ 	}
+-	crtc = obj_to_crtc(obj);
+ 	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
+ 
+ 	if (crtc_req->mode_valid) {
+ 		/* If we have a mode we need a framebuffer. */
+ 		/* If we pass -1, set the mode with the currently bound fb */
+ 		if (crtc_req->fb_id == -1) {
+-			if (!crtc->fb) {
++			if (!crtc->primary->fb) {
+ 				DRM_DEBUG_KMS("CRTC doesn't have current FB\n");
+ 				ret = -EINVAL;
+ 				goto out;
+ 			}
+-			fb = crtc->fb;
++			fb = crtc->primary->fb;
+ 			/* Make refcounting symmetric with the lookup path. */
+ 			drm_framebuffer_reference(fb);
+ 		} else {
+@@ -2250,39 +2736,132 @@
+ 				goto out;
+ 			}
+ 
+-			obj = drm_mode_object_find(dev, out_id,
+-						   DRM_MODE_OBJECT_CONNECTOR);
+-			if (!obj) {
++			connector = drm_connector_find(dev, out_id);
++			if (!connector) {
+ 				DRM_DEBUG_KMS("Connector id %d unknown\n",
+ 						out_id);
+ 				ret = -ENOENT;
+ 				goto out;
+ 			}
+-			connector = obj_to_connector(obj);
+-			DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
+-					connector->base.id,
+-					drm_get_connector_name(connector));
++			DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
++					connector->base.id,
++					connector->name);
++
++			connector_set[i] = connector;
++		}
++	}
++
++	set.crtc = crtc;
++	set.x = crtc_req->x;
++	set.y = crtc_req->y;
++	set.mode = mode;
++	set.connectors = connector_set;
++	set.num_connectors = crtc_req->count_connectors;
++	set.fb = fb;
++	ret = drm_mode_set_config_internal(&set);
++
++out:
++	if (fb)
++		drm_framebuffer_unreference(fb);
++
++	kfree(connector_set);
++	drm_mode_destroy(dev, mode);
++	drm_modeset_unlock_all(dev);
++	return ret;
++}
++
++/**
++ * drm_mode_cursor_universal - translate legacy cursor ioctl call into a
++ *     universal plane handler call
++ * @crtc: crtc to update cursor for
++ * @req: data pointer for the ioctl
++ * @file_priv: drm file for the ioctl call
++ *
++ * Legacy cursor ioctl's work directly with driver buffer handles.  To
++ * translate legacy ioctl calls into universal plane handler calls, we need to
++ * wrap the native buffer handle in a drm_framebuffer.
++ *
++ * Note that we assume any handle passed to the legacy ioctls was a 32-bit ARGB
++ * buffer with a pitch of 4*width; the universal plane interface should be used
++ * directly in cases where the hardware can support other buffer settings and
++ * userspace wants to make use of these capabilities.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
++static int drm_mode_cursor_universal(struct drm_crtc *crtc,
++				     struct drm_mode_cursor2 *req,
++				     struct drm_file *file_priv)
++{
++	struct drm_device *dev = crtc->dev;
++	struct drm_framebuffer *fb = NULL;
++	struct drm_mode_fb_cmd2 fbreq = {
++		.width = req->width,
++		.height = req->height,
++		.pixel_format = DRM_FORMAT_ARGB8888,
++		.pitches = { req->width * 4 },
++		.handles = { req->handle },
++	};
++	int32_t crtc_x, crtc_y;
++	uint32_t crtc_w = 0, crtc_h = 0;
++	uint32_t src_w = 0, src_h = 0;
++	int ret = 0;
++
++	BUG_ON(!crtc->cursor);
++	WARN_ON(crtc->cursor->crtc != crtc && crtc->cursor->crtc != NULL);
++
++	/*
++	 * Obtain fb we'll be using (either new or existing) and take an extra
++	 * reference to it if fb != null.  setplane will take care of dropping
++	 * the reference if the plane update fails.
++	 */
++	if (req->flags & DRM_MODE_CURSOR_BO) {
++		if (req->handle) {
++			fb = add_framebuffer_internal(dev, &fbreq, file_priv);
++			if (IS_ERR(fb)) {
++				DRM_DEBUG_KMS("failed to wrap cursor buffer in drm framebuffer\n");
++				return PTR_ERR(fb);
++			}
+ 
+-			connector_set[i] = connector;
++			drm_framebuffer_reference(fb);
++		} else {
++			fb = NULL;
+ 		}
++	} else {
++		fb = crtc->cursor->fb;
++		if (fb)
++			drm_framebuffer_reference(fb);
+ 	}
+ 
+-	set.crtc = crtc;
+-	set.x = crtc_req->x;
+-	set.y = crtc_req->y;
+-	set.mode = mode;
+-	set.connectors = connector_set;
+-	set.num_connectors = crtc_req->count_connectors;
+-	set.fb = fb;
+-	ret = drm_mode_set_config_internal(&set);
++	if (req->flags & DRM_MODE_CURSOR_MOVE) {
++		crtc_x = req->x;
++		crtc_y = req->y;
++	} else {
++		crtc_x = crtc->cursor_x;
++		crtc_y = crtc->cursor_y;
++	}
+ 
+-out:
+-	if (fb)
+-		drm_framebuffer_unreference(fb);
++	if (fb) {
++		crtc_w = fb->width;
++		crtc_h = fb->height;
++		src_w = fb->width << 16;
++		src_h = fb->height << 16;
++	}
++
++	/*
++	 * setplane_internal will take care of deref'ing either the old or new
++	 * framebuffer depending on success.
++	 */
++	ret = __setplane_internal(crtc->cursor, crtc, fb,
++				crtc_x, crtc_y, crtc_w, crtc_h,
++				0, 0, src_w, src_h);
++
++	/* Update successful; save new cursor position, if necessary */
++	if (ret == 0 && req->flags & DRM_MODE_CURSOR_MOVE) {
++		crtc->cursor_x = req->x;
++		crtc->cursor_y = req->y;
++	}
+ 
+-	kfree(connector_set);
+-	drm_mode_destroy(dev, mode);
+-	drm_modeset_unlock_all(dev);
+ 	return ret;
+ }
+ 
+@@ -2290,7 +2869,6 @@
+ 				  struct drm_mode_cursor2 *req,
+ 				  struct drm_file *file_priv)
+ {
+-	struct drm_mode_object *obj;
+ 	struct drm_crtc *crtc;
+ 	int ret = 0;
+ 
+@@ -2300,14 +2878,22 @@
+ 	if (!req->flags || (~DRM_MODE_CURSOR_FLAGS & req->flags))
+ 		return -EINVAL;
+ 
+-	obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC);
+-	if (!obj) {
++	crtc = drm_crtc_find(dev, req->crtc_id);
++	if (!crtc) {
+ 		DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id);
+ 		return -ENOENT;
+ 	}
+-	crtc = obj_to_crtc(obj);
+ 
+-	mutex_lock(&crtc->mutex);
++	/*
++	 * If this crtc has a universal cursor plane, call that plane's update
++	 * handler rather than using legacy cursor handlers.
++	 */
++	drm_modeset_lock_crtc(crtc, crtc->cursor);
++	if (crtc->cursor) {
++		ret = drm_mode_cursor_universal(crtc, req, file_priv);
++		goto out;
++	}
++
+ 	if (req->flags & DRM_MODE_CURSOR_BO) {
+ 		if (!crtc->funcs->cursor_set && !crtc->funcs->cursor_set2) {
+ 			ret = -ENXIO;
+@@ -2331,13 +2917,28 @@
+ 		}
+ 	}
+ out:
+-	mutex_unlock(&crtc->mutex);
++	drm_modeset_unlock_crtc(crtc);
+ 
+ 	return ret;
+ 
+ }
++
++
++/**
++ * drm_mode_cursor_ioctl - set CRTC's cursor configuration
++ * @dev: drm device for the ioctl
++ * @data: data pointer for the ioctl
++ * @file_priv: drm file for the ioctl call
++ *
++ * Set the cursor configuration based on user request.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_cursor_ioctl(struct drm_device *dev,
+-			void *data, struct drm_file *file_priv)
++			  void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_cursor *req = data;
+ 	struct drm_mode_cursor2 new_req;
+@@ -2348,6 +2949,21 @@
+ 	return drm_mode_cursor_common(dev, &new_req, file_priv);
+ }
+ 
++/**
++ * drm_mode_cursor2_ioctl - set CRTC's cursor configuration
++ * @dev: drm device for the ioctl
++ * @data: data pointer for the ioctl
++ * @file_priv: drm file for the ioctl call
++ *
++ * Set the cursor configuration based on user request. This implements the 2nd
++ * version of the cursor ioctl, which allows userspace to additionally specify
++ * the hotspot of the pointer.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_cursor2_ioctl(struct drm_device *dev,
+ 			   void *data, struct drm_file *file_priv)
+ {
+@@ -2355,7 +2971,14 @@
+ 	return drm_mode_cursor_common(dev, req, file_priv);
+ }
+ 
+-/* Original addfb only supported RGB formats, so figure out which one */
++/**
++ * drm_mode_legacy_fb_format - compute drm fourcc code from legacy description
++ * @bpp: bits per pixels
++ * @depth: bit depth per pixel
++ *
++ * Computes a drm fourcc pixel format code for the given @bpp/@depth values.
++ * Useful in fbdev emulation code, since that deals in those values.
++ */
+ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
+ {
+ 	uint32_t fmt;
+@@ -2397,23 +3020,22 @@
+  * @data: data pointer for the ioctl
+  * @file_priv: drm file for the ioctl call
+  *
+- * Add a new FB to the specified CRTC, given a user request.
++ * Add a new FB to the specified CRTC, given a user request. This is the
++ * original addfb ioctl which only supported RGB formats.
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_addfb(struct drm_device *dev,
+ 		   void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_fb_cmd *or = data;
+ 	struct drm_mode_fb_cmd2 r = {};
+-	struct drm_mode_config *config = &dev->mode_config;
+-	struct drm_framebuffer *fb;
+-	int ret = 0;
++	int ret;
+ 
+-	/* Use new struct with format internally */
++	/* convert to new format and call new ioctl */
+ 	r.fb_id = or->fb_id;
+ 	r.width = or->width;
+ 	r.height = or->height;
+@@ -2421,28 +3043,13 @@
+ 	r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
+ 	r.handles[0] = or->handle;
+ 
+-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+-		return -EINVAL;
+-
+-	if ((config->min_width > r.width) || (r.width > config->max_width))
+-		return -EINVAL;
+-
+-	if ((config->min_height > r.height) || (r.height > config->max_height))
+-		return -EINVAL;
+-
+-	fb = dev->mode_config.funcs->fb_create(dev, file_priv, &r);
+-	if (IS_ERR(fb)) {
+-		DRM_DEBUG_KMS("could not create framebuffer\n");
+-		return PTR_ERR(fb);
+-	}
++	ret = drm_mode_addfb2(dev, &r, file_priv);
++	if (ret)
++		return ret;
+ 
+-	mutex_lock(&file_priv->fbs_lock);
+-	or->fb_id = fb->base.id;
+-	list_add(&fb->filp_head, &file_priv->fbs);
+-	DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id);
+-	mutex_unlock(&file_priv->fbs_lock);
++	or->fb_id = r.fb_id;
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ static int format_check(const struct drm_mode_fb_cmd2 *r)
+@@ -2534,7 +3141,7 @@
+ 	num_planes = drm_format_num_planes(r->pixel_format);
+ 
+ 	if (r->width == 0 || r->width % hsub) {
+-		DRM_DEBUG_KMS("bad framebuffer width %u\n", r->height);
++		DRM_DEBUG_KMS("bad framebuffer width %u\n", r->width);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -2568,54 +3175,38 @@
+ 	return 0;
+ }
+ 
+-/**
+- * drm_mode_addfb2 - add an FB to the graphics configuration
+- * @dev: drm device for the ioctl
+- * @data: data pointer for the ioctl
+- * @file_priv: drm file for the ioctl call
+- *
+- * Add a new FB to the specified CRTC, given a user request with format.
+- *
+- * Called by the user via ioctl.
+- *
+- * RETURNS:
+- * Zero on success, errno on failure.
+- */
+-int drm_mode_addfb2(struct drm_device *dev,
+-		    void *data, struct drm_file *file_priv)
++static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
++							struct drm_mode_fb_cmd2 *r,
++							struct drm_file *file_priv)
+ {
+-	struct drm_mode_fb_cmd2 *r = data;
+ 	struct drm_mode_config *config = &dev->mode_config;
+ 	struct drm_framebuffer *fb;
+ 	int ret;
+ 
+-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+-		return -EINVAL;
+-
+ 	if (r->flags & ~DRM_MODE_FB_INTERLACED) {
+ 		DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
+-		return -EINVAL;
++		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	if ((config->min_width > r->width) || (r->width > config->max_width)) {
+ 		DRM_DEBUG_KMS("bad framebuffer width %d, should be >= %d && <= %d\n",
+ 			  r->width, config->min_width, config->max_width);
+-		return -EINVAL;
++		return ERR_PTR(-EINVAL);
+ 	}
+ 	if ((config->min_height > r->height) || (r->height > config->max_height)) {
+ 		DRM_DEBUG_KMS("bad framebuffer height %d, should be >= %d && <= %d\n",
+ 			  r->height, config->min_height, config->max_height);
+-		return -EINVAL;
++		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	ret = framebuffer_check(r);
+ 	if (ret)
+-		return ret;
++		return ERR_PTR(ret);
+ 
+ 	fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
+ 	if (IS_ERR(fb)) {
+ 		DRM_DEBUG_KMS("could not create framebuffer\n");
+-		return PTR_ERR(fb);
++		return fb;
+ 	}
+ 
+ 	mutex_lock(&file_priv->fbs_lock);
+@@ -2624,8 +3215,37 @@
+ 	DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id);
+ 	mutex_unlock(&file_priv->fbs_lock);
+ 
++	return fb;
++}
++
++/**
++ * drm_mode_addfb2 - add an FB to the graphics configuration
++ * @dev: drm device for the ioctl
++ * @data: data pointer for the ioctl
++ * @file_priv: drm file for the ioctl call
++ *
++ * Add a new FB to the specified CRTC, given a user request with format. This is
++ * the 2nd version of the addfb ioctl, which supports multi-planar framebuffers
++ * and uses fourcc codes as pixel format specifiers.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
++int drm_mode_addfb2(struct drm_device *dev,
++		    void *data, struct drm_file *file_priv)
++{
++	struct drm_framebuffer *fb;
+ 
+-	return ret;
++	if (!drm_core_check_feature(dev, DRIVER_MODESET))
++		return -EINVAL;
++
++	fb = add_framebuffer_internal(dev, data, file_priv);
++	if (IS_ERR(fb))
++		return PTR_ERR(fb);
++
++	return 0;
+ }
+ 
+ /**
+@@ -2638,8 +3258,8 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_rmfb(struct drm_device *dev,
+ 		   void *data, struct drm_file *file_priv)
+@@ -2692,8 +3312,8 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ int drm_mode_getfb(struct drm_device *dev,
+ 		   void *data, struct drm_file *file_priv)
+@@ -2715,7 +3335,8 @@
+ 	r->bpp = fb->bits_per_pixel;
+ 	r->pitch = fb->pitches[0];
+ 	if (fb->funcs->create_handle) {
+-		if (file_priv->is_master || capable(CAP_SYS_ADMIN)) {
++		if (file_priv->is_master || capable(CAP_SYS_ADMIN) ||
++		    drm_is_control_client(file_priv)) {
+ 			ret = fb->funcs->create_handle(fb, file_priv,
+ 						       &r->handle);
+ 		} else {
+@@ -2736,6 +3357,25 @@
+ 	return ret;
+ }
+ 
++/**
++ * drm_mode_dirtyfb_ioctl - flush frontbuffer rendering on an FB
++ * @dev: drm device for the ioctl
++ * @data: data pointer for the ioctl
++ * @file_priv: drm file for the ioctl call
++ *
++ * Lookup the FB and flush out the damaged area supplied by userspace as a clip
++ * rectangle list. Generic userspace which does frontbuffer rendering must call
++ * this ioctl to flush out the changes on manual-update display outputs, e.g.
++ * usb display-link, mipi manual update panels or edp panel self refresh modes.
++ *
++ * Modesetting drivers which always update the frontbuffer do not need to
++ * implement the corresponding ->dirty framebuffer callback.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
+ 			   void *data, struct drm_file *file_priv)
+ {
+@@ -2813,15 +3453,24 @@
+  *
+  * Called by the user via ioctl.
+  *
+- * RETURNS:
+- * Zero on success, errno on failure.
++ * Returns:
++ * Zero on success, negative errno on failure.
+  */
+ void drm_fb_release(struct drm_file *priv)
+ {
+ 	struct drm_device *dev = priv->minor->dev;
+ 	struct drm_framebuffer *fb, *tfb;
+ 
+-	mutex_lock(&priv->fbs_lock);
++	/*
++	 * When the file gets released that means no one else can access the fb
++	 * list any more, so no need to grab fpriv->fbs_lock. And we need to
++	 * avoid upsetting lockdep since the universal cursor code adds a
++	 * framebuffer while holding mutex locks.
++	 *
++	 * Note that a real deadlock between fpriv->fbs_lock and the modeset
++	 * locks is impossible here since no one else but this function can get
++	 * at it any more.
++	 */
+ 	list_for_each_entry_safe(fb, tfb, &priv->fbs, filp_head) {
+ 
+ 		mutex_lock(&dev->mode_config.fb_lock);
+@@ -2834,9 +3483,26 @@
+ 		/* This will also drop the fpriv->fbs reference. */
+ 		drm_framebuffer_remove(fb);
+ 	}
+-	mutex_unlock(&priv->fbs_lock);
+ }
+ 
++/**
++ * drm_property_create - create a new property type
++ * @dev: drm device
++ * @flags: flags specifying the property type
++ * @name: name of the property
++ * @num_values: number of pre-defined values
++ *
++ * This creates a new generic drm property which can then be attached to a drm
++ * object with drm_object_attach_property. The returned property object must be
++ * freed with drm_property_destroy.
++ *
++ * Note that the DRM core keeps a per-device list of properties and that, if
++ * drm_mode_config_cleanup() is called, it will destroy all properties created
++ * by the driver.
++ *
++ * Returns:
++ * A pointer to the newly created property on success, NULL on failure.
++ */
+ struct drm_property *drm_property_create(struct drm_device *dev, int flags,
+ 					 const char *name, int num_values)
+ {
+@@ -2847,6 +3513,8 @@
+ 	if (!property)
+ 		return NULL;
+ 
++	property->dev = dev;
++
+ 	if (num_values) {
+ 		property->values = kzalloc(sizeof(uint64_t)*num_values, GFP_KERNEL);
+ 		if (!property->values)
+@@ -2859,7 +3527,7 @@
+ 
+ 	property->flags = flags;
+ 	property->num_values = num_values;
+-	INIT_LIST_HEAD(&property->enum_blob_list);
++	INIT_LIST_HEAD(&property->enum_list);
+ 
+ 	if (name) {
+ 		strncpy(property->name, name, DRM_PROP_NAME_LEN);
+@@ -2867,6 +3535,9 @@
+ 	}
+ 
+ 	list_add_tail(&property->head, &dev->mode_config.property_list);
++
++	WARN_ON(!drm_property_type_valid(property));
++
+ 	return property;
+ fail:
+ 	kfree(property->values);
+@@ -2875,6 +3546,24 @@
+ }
+ EXPORT_SYMBOL(drm_property_create);
+ 
++/**
++ * drm_property_create_enum - create a new enumeration property type
++ * @dev: drm device
++ * @flags: flags specifying the property type
++ * @name: name of the property
++ * @props: enumeration lists with property values
++ * @num_values: number of pre-defined values
++ *
++ * This creates a new generic drm property which can then be attached to a drm
++ * object with drm_object_attach_property. The returned property object must be
++ * freed with drm_property_destroy.
++ *
++ * Userspace is only allowed to set one of the predefined values for enumeration
++ * properties.
++ *
++ * Returns:
++ * A pointer to the newly created property on success, NULL on failure.
++ */
+ struct drm_property *drm_property_create_enum(struct drm_device *dev, int flags,
+ 					 const char *name,
+ 					 const struct drm_prop_enum_list *props,
+@@ -2903,22 +3592,50 @@
+ }
+ EXPORT_SYMBOL(drm_property_create_enum);
+ 
++/**
++ * drm_property_create_bitmask - create a new bitmask property type
++ * @dev: drm device
++ * @flags: flags specifying the property type
++ * @name: name of the property
++ * @props: enumeration lists with property bitflags
++ * @num_props: size of the @props array
++ * @supported_bits: bitmask of all supported enumeration values
++ *
++ * This creates a new bitmask drm property which can then be attached to a drm
++ * object with drm_object_attach_property. The returned property object must be
++ * freed with drm_property_destroy.
++ *
++ * Compared to plain enumeration properties userspace is allowed to set any
++ * or'ed together combination of the predefined property bitflag values
++ *
++ * Returns:
++ * A pointer to the newly created property on success, NULL on failure.
++ */
+ struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
+ 					 int flags, const char *name,
+ 					 const struct drm_prop_enum_list *props,
+-					 int num_values)
++					 int num_props,
++					 uint64_t supported_bits)
+ {
+ 	struct drm_property *property;
+-	int i, ret;
++	int i, ret, index = 0;
++	int num_values = hweight64(supported_bits);
+ 
+ 	flags |= DRM_MODE_PROP_BITMASK;
+ 
+ 	property = drm_property_create(dev, flags, name, num_values);
+ 	if (!property)
+ 		return NULL;
++	for (i = 0; i < num_props; i++) {
++		if (!(supported_bits & (1ULL << props[i].type)))
++			continue;
+ 
+-	for (i = 0; i < num_values; i++) {
+-		ret = drm_property_add_enum(property, i,
++		if (WARN_ON(index >= num_values)) {
++			drm_property_destroy(dev, property);
++			return NULL;
++		}
++
++		ret = drm_property_add_enum(property, index++,
+ 				      props[i].type,
+ 				      props[i].name);
+ 		if (ret) {
+@@ -2931,14 +3648,12 @@
+ }
+ EXPORT_SYMBOL(drm_property_create_bitmask);
+ 
+-struct drm_property *drm_property_create_range(struct drm_device *dev, int flags,
+-					 const char *name,
++static struct drm_property *property_create_range(struct drm_device *dev,
++					 int flags, const char *name,
+ 					 uint64_t min, uint64_t max)
+ {
+ 	struct drm_property *property;
+ 
+-	flags |= DRM_MODE_PROP_RANGE;
+-
+ 	property = drm_property_create(dev, flags, name, 2);
+ 	if (!property)
+ 		return NULL;
+@@ -2948,25 +3663,94 @@
+ 
+ 	return property;
+ }
++
++/**
++ * drm_property_create_range - create a new ranged property type
++ * @dev: drm device
++ * @flags: flags specifying the property type
++ * @name: name of the property
++ * @min: minimum value of the property
++ * @max: maximum value of the property
++ *
++ * This creates a new generic drm property which can then be attached to a drm
++ * object with drm_object_attach_property. The returned property object must be
++ * freed with drm_property_destroy.
++ *
++ * Userspace is allowed to set any integer value in the (min, max) range
++ * inclusive.
++ *
++ * Returns:
++ * A pointer to the newly created property on success, NULL on failure.
++ */
++struct drm_property *drm_property_create_range(struct drm_device *dev, int flags,
++					 const char *name,
++					 uint64_t min, uint64_t max)
++{
++	return property_create_range(dev, DRM_MODE_PROP_RANGE | flags,
++			name, min, max);
++}
+ EXPORT_SYMBOL(drm_property_create_range);
+ 
++struct drm_property *drm_property_create_signed_range(struct drm_device *dev,
++					 int flags, const char *name,
++					 int64_t min, int64_t max)
++{
++	return property_create_range(dev, DRM_MODE_PROP_SIGNED_RANGE | flags,
++			name, I642U64(min), I642U64(max));
++}
++EXPORT_SYMBOL(drm_property_create_signed_range);
++
++struct drm_property *drm_property_create_object(struct drm_device *dev,
++					 int flags, const char *name, uint32_t type)
++{
++	struct drm_property *property;
++
++	flags |= DRM_MODE_PROP_OBJECT;
++
++	property = drm_property_create(dev, flags, name, 1);
++	if (!property)
++		return NULL;
++
++	property->values[0] = type;
++
++	return property;
++}
++EXPORT_SYMBOL(drm_property_create_object);
++
++/**
++ * drm_property_add_enum - add a possible value to an enumeration property
++ * @property: enumeration property to change
++ * @index: index of the new enumeration
++ * @value: value of the new enumeration
++ * @name: symbolic name of the new enumeration
++ *
++ * This functions adds enumerations to a property.
++ *
++ * It's use is deprecated, drivers should use one of the more specific helpers
++ * to directly create the property with all enumerations already attached.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
+ int drm_property_add_enum(struct drm_property *property, int index,
+ 			  uint64_t value, const char *name)
+ {
+ 	struct drm_property_enum *prop_enum;
+ 
+-	if (!(property->flags & (DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BITMASK)))
++	if (!(drm_property_type_is(property, DRM_MODE_PROP_ENUM) ||
++			drm_property_type_is(property, DRM_MODE_PROP_BITMASK)))
+ 		return -EINVAL;
+ 
+ 	/*
+ 	 * Bitmask enum properties have the additional constraint of values
+ 	 * from 0 to 63
+ 	 */
+-	if ((property->flags & DRM_MODE_PROP_BITMASK) && (value > 63))
++	if (drm_property_type_is(property, DRM_MODE_PROP_BITMASK) &&
++			(value > 63))
+ 		return -EINVAL;
+ 
+-	if (!list_empty(&property->enum_blob_list)) {
+-		list_for_each_entry(prop_enum, &property->enum_blob_list, head) {
++	if (!list_empty(&property->enum_list)) {
++		list_for_each_entry(prop_enum, &property->enum_list, head) {
+ 			if (prop_enum->value == value) {
+ 				strncpy(prop_enum->name, name, DRM_PROP_NAME_LEN);
+ 				prop_enum->name[DRM_PROP_NAME_LEN-1] = '\0';
+@@ -2984,16 +3768,24 @@
+ 	prop_enum->value = value;
+ 
+ 	property->values[index] = value;
+-	list_add_tail(&prop_enum->head, &property->enum_blob_list);
++	list_add_tail(&prop_enum->head, &property->enum_list);
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_property_add_enum);
+ 
++/**
++ * drm_property_destroy - destroy a drm property
++ * @dev: drm device
++ * @property: property to destry
++ *
++ * This function frees a property including any attached resources like
++ * enumeration values.
++ */
+ void drm_property_destroy(struct drm_device *dev, struct drm_property *property)
+ {
+ 	struct drm_property_enum *prop_enum, *pt;
+ 
+-	list_for_each_entry_safe(prop_enum, pt, &property->enum_blob_list, head) {
++	list_for_each_entry_safe(prop_enum, pt, &property->enum_list, head) {
+ 		list_del(&prop_enum->head);
+ 		kfree(prop_enum);
+ 	}
+@@ -3006,6 +3798,16 @@
+ }
+ EXPORT_SYMBOL(drm_property_destroy);
+ 
++/**
++ * drm_object_attach_property - attach a property to a modeset object
++ * @obj: drm modeset object
++ * @property: property to attach
++ * @init_val: initial value of the property
++ *
++ * This attaches the given property to the modeset object with the given initial
++ * value. Currently this function cannot fail since the properties are stored in
++ * a statically sized array.
++ */
+ void drm_object_attach_property(struct drm_mode_object *obj,
+ 				struct drm_property *property,
+ 				uint64_t init_val)
+@@ -3026,6 +3828,19 @@
+ }
+ EXPORT_SYMBOL(drm_object_attach_property);
+ 
++/**
++ * drm_object_property_set_value - set the value of a property
++ * @obj: drm mode object to set property value for
++ * @property: property to set
++ * @val: value the property should be set to
++ *
++ * This functions sets a given property on a given object. This function only
++ * changes the software state of the property, it does not call into the
++ * driver's ->set_property callback.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
+ int drm_object_property_set_value(struct drm_mode_object *obj,
+ 				  struct drm_property *property, uint64_t val)
+ {
+@@ -3042,6 +3857,20 @@
+ }
+ EXPORT_SYMBOL(drm_object_property_set_value);
+ 
++/**
++ * drm_object_property_get_value - retrieve the value of a property
++ * @obj: drm mode object to get property value from
++ * @property: property to retrieve
++ * @val: storage for the property value
++ *
++ * This function retrieves the softare state of the given property for the given
++ * property. Since there is no driver callback to retrieve the current property
++ * value this might be out of sync with the hardware, depending upon the driver
++ * and property.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
+ int drm_object_property_get_value(struct drm_mode_object *obj,
+ 				  struct drm_property *property, uint64_t *val)
+ {
+@@ -3058,41 +3887,49 @@
+ }
+ EXPORT_SYMBOL(drm_object_property_get_value);
+ 
++/**
++ * drm_mode_getproperty_ioctl - get the property metadata
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This function retrieves the metadata for a given property, like the different
++ * possible values for an enum property or the limits for a range property.
++ *
++ * Blob properties are special
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_getproperty_ioctl(struct drm_device *dev,
+ 			       void *data, struct drm_file *file_priv)
+ {
+-	struct drm_mode_object *obj;
+ 	struct drm_mode_get_property *out_resp = data;
+ 	struct drm_property *property;
+ 	int enum_count = 0;
+-	int blob_count = 0;
+ 	int value_count = 0;
+ 	int ret = 0, i;
+ 	int copied;
+ 	struct drm_property_enum *prop_enum;
+ 	struct drm_mode_property_enum __user *enum_ptr;
+-	struct drm_property_blob *prop_blob;
+-	uint32_t __user *blob_id_ptr;
+ 	uint64_t __user *values_ptr;
+-	uint32_t __user *blob_length_ptr;
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 		return -EINVAL;
+ 
+ 	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, out_resp->prop_id, DRM_MODE_OBJECT_PROPERTY);
+-	if (!obj) {
++	property = drm_property_find(dev, out_resp->prop_id);
++	if (!property) {
+ 		ret = -ENOENT;
+ 		goto done;
+ 	}
+-	property = obj_to_property(obj);
+ 
+-	if (property->flags & (DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BITMASK)) {
+-		list_for_each_entry(prop_enum, &property->enum_blob_list, head)
++	if (drm_property_type_is(property, DRM_MODE_PROP_ENUM) ||
++			drm_property_type_is(property, DRM_MODE_PROP_BITMASK)) {
++		list_for_each_entry(prop_enum, &property->enum_list, head)
+ 			enum_count++;
+-	} else if (property->flags & DRM_MODE_PROP_BLOB) {
+-		list_for_each_entry(prop_blob, &property->enum_blob_list, head)
+-			blob_count++;
+ 	}
+ 
+ 	value_count = property->num_values;
+@@ -3112,11 +3949,12 @@
+ 	}
+ 	out_resp->count_values = value_count;
+ 
+-	if (property->flags & (DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BITMASK)) {
++	if (drm_property_type_is(property, DRM_MODE_PROP_ENUM) ||
++			drm_property_type_is(property, DRM_MODE_PROP_BITMASK)) {
+ 		if ((out_resp->count_enum_blobs >= enum_count) && enum_count) {
+ 			copied = 0;
+ 			enum_ptr = (struct drm_mode_property_enum __user *)(unsigned long)out_resp->enum_blob_ptr;
+-			list_for_each_entry(prop_enum, &property->enum_blob_list, head) {
++			list_for_each_entry(prop_enum, &property->enum_list, head) {
+ 
+ 				if (copy_to_user(&enum_ptr[copied].value, &prop_enum->value, sizeof(uint64_t))) {
+ 					ret = -EFAULT;
+@@ -3124,45 +3962,34 @@
+ 				}
+ 
+ 				if (copy_to_user(&enum_ptr[copied].name,
+-						 &prop_enum->name, DRM_PROP_NAME_LEN)) {
+-					ret = -EFAULT;
+-					goto done;
+-				}
+-				copied++;
+-			}
+-		}
+-		out_resp->count_enum_blobs = enum_count;
+-	}
+-
+-	if (property->flags & DRM_MODE_PROP_BLOB) {
+-		if ((out_resp->count_enum_blobs >= blob_count) && blob_count) {
+-			copied = 0;
+-			blob_id_ptr = (uint32_t __user *)(unsigned long)out_resp->enum_blob_ptr;
+-			blob_length_ptr = (uint32_t __user *)(unsigned long)out_resp->values_ptr;
+-
+-			list_for_each_entry(prop_blob, &property->enum_blob_list, head) {
+-				if (put_user(prop_blob->base.id, blob_id_ptr + copied)) {
+-					ret = -EFAULT;
+-					goto done;
+-				}
+-
+-				if (put_user(prop_blob->length, blob_length_ptr + copied)) {
++						 &prop_enum->name, DRM_PROP_NAME_LEN)) {
+ 					ret = -EFAULT;
+ 					goto done;
+ 				}
+-
+ 				copied++;
+ 			}
+ 		}
+-		out_resp->count_enum_blobs = blob_count;
++		out_resp->count_enum_blobs = enum_count;
+ 	}
++
++	/*
++	 * NOTE: The idea seems to have been to use this to read all the blob
++	 * property values. But nothing ever added them to the corresponding
++	 * list, userspace always used the special-purpose get_blob ioctl to
++	 * read the value for a blob property. It also doesn't make a lot of
++	 * sense to return values here when everything else is just metadata for
++	 * the property itself.
++	 */
++	if (drm_property_type_is(property, DRM_MODE_PROP_BLOB))
++		out_resp->count_enum_blobs = 0;
+ done:
+ 	drm_modeset_unlock_all(dev);
+ 	return ret;
+ }
+ 
+-static struct drm_property_blob *drm_property_create_blob(struct drm_device *dev, int length,
+-							  void *data)
++static struct drm_property_blob *
++drm_property_create_blob(struct drm_device *dev, size_t length,
++			 const void *data)
+ {
+ 	struct drm_property_blob *blob;
+ 	int ret;
+@@ -3196,10 +4023,23 @@
+ 	kfree(blob);
+ }
+ 
++/**
++ * drm_mode_getblob_ioctl - get the contents of a blob property value
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This function retrieves the contents of a blob property. The value stored in
++ * an object's blob property is just a normal modeset object id.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_getblob_ioctl(struct drm_device *dev,
+ 			   void *data, struct drm_file *file_priv)
+ {
+-	struct drm_mode_object *obj;
+ 	struct drm_mode_get_blob *out_resp = data;
+ 	struct drm_property_blob *blob;
+ 	int ret = 0;
+@@ -3209,12 +4049,11 @@
+ 		return -EINVAL;
+ 
+ 	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, out_resp->blob_id, DRM_MODE_OBJECT_BLOB);
+-	if (!obj) {
++	blob = drm_property_blob_find(dev, out_resp->blob_id);
++	if (!blob) {
+ 		ret = -ENOENT;
+ 		goto done;
+ 	}
+-	blob = obj_to_blob(obj);
+ 
+ 	if (out_resp->length == blob->length) {
+ 		blob_ptr = (void __user *)(unsigned long)out_resp->data;
+@@ -3230,11 +4069,105 @@
+ 	return ret;
+ }
+ 
+-int drm_mode_connector_update_edid_property(struct drm_connector *connector,
+-					    struct edid *edid)
++/**
++ * drm_mode_connector_set_path_property - set tile property on connector
++ * @connector: connector to set property on.
++ * @path: path to use for property.
++ *
++ * This creates a property to expose to userspace to specify a
++ * connector path. This is mainly used for DisplayPort MST where
++ * connectors have a topology and we want to allow userspace to give
++ * them more meaningful names.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
++int drm_mode_connector_set_path_property(struct drm_connector *connector,
++					 const char *path)
++{
++	struct drm_device *dev = connector->dev;
++	size_t size = strlen(path) + 1;
++	int ret;
++
++	connector->path_blob_ptr = drm_property_create_blob(connector->dev,
++							    size, path);
++	if (!connector->path_blob_ptr)
++		return -EINVAL;
++
++	ret = drm_object_property_set_value(&connector->base,
++					    dev->mode_config.path_property,
++					    connector->path_blob_ptr->base.id);
++	return ret;
++}
++EXPORT_SYMBOL(drm_mode_connector_set_path_property);
++
++/**
++ * drm_mode_connector_set_tile_property - set tile property on connector
++ * @connector: connector to set property on.
++ *
++ * This looks up the tile information for a connector, and creates a
++ * property for userspace to parse if it exists. The property is of
++ * the form of 8 integers using ':' as a separator.
++ *
++ * Returns:
++ * Zero on success, errno on failure.
++ */
++int drm_mode_connector_set_tile_property(struct drm_connector *connector)
+ {
+ 	struct drm_device *dev = connector->dev;
+ 	int ret, size;
++	char tile[256];
++
++	if (connector->tile_blob_ptr)
++		drm_property_destroy_blob(dev, connector->tile_blob_ptr);
++
++	if (!connector->has_tile) {
++		connector->tile_blob_ptr = NULL;
++		ret = drm_object_property_set_value(&connector->base,
++						    dev->mode_config.tile_property, 0);
++		return ret;
++	}
++
++	snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d",
++		 connector->tile_group->id, connector->tile_is_single_monitor,
++		 connector->num_h_tile, connector->num_v_tile,
++		 connector->tile_h_loc, connector->tile_v_loc,
++		 connector->tile_h_size, connector->tile_v_size);
++	size = strlen(tile) + 1;
++
++	connector->tile_blob_ptr = drm_property_create_blob(connector->dev,
++							    size, tile);
++	if (!connector->tile_blob_ptr)
++		return -EINVAL;
++
++	ret = drm_object_property_set_value(&connector->base,
++					    dev->mode_config.tile_property,
++					    connector->tile_blob_ptr->base.id);
++	return ret;
++}
++EXPORT_SYMBOL(drm_mode_connector_set_tile_property);
++
++/**
++ * drm_mode_connector_update_edid_property - update the edid property of a connector
++ * @connector: drm connector
++ * @edid: new value of the edid property
++ *
++ * This function creates a new blob modeset object and assigns its id to the
++ * connector's edid property.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
++int drm_mode_connector_update_edid_property(struct drm_connector *connector,
++					    const struct edid *edid)
++{
++	struct drm_device *dev = connector->dev;
++	size_t size;
++	int ret;
++
++	/* ignore requests to set edid when overridden */
++	if (connector->override_edid)
++		return 0;
+ 
+ 	if (connector->edid_blob_ptr)
+ 		drm_property_destroy_blob(dev, connector->edid_blob_ptr);
+@@ -3265,19 +4198,40 @@
+ {
+ 	if (property->flags & DRM_MODE_PROP_IMMUTABLE)
+ 		return false;
+-	if (property->flags & DRM_MODE_PROP_RANGE) {
++
++	if (drm_property_type_is(property, DRM_MODE_PROP_RANGE)) {
+ 		if (value < property->values[0] || value > property->values[1])
+ 			return false;
+ 		return true;
+-	} else if (property->flags & DRM_MODE_PROP_BITMASK) {
++	} else if (drm_property_type_is(property, DRM_MODE_PROP_SIGNED_RANGE)) {
++		int64_t svalue = U642I64(value);
++		if (svalue < U642I64(property->values[0]) ||
++				svalue > U642I64(property->values[1]))
++			return false;
++		return true;
++	} else if (drm_property_type_is(property, DRM_MODE_PROP_BITMASK)) {
+ 		int i;
+ 		uint64_t valid_mask = 0;
+ 		for (i = 0; i < property->num_values; i++)
+ 			valid_mask |= (1ULL << property->values[i]);
+ 		return !(value & ~valid_mask);
+-	} else if (property->flags & DRM_MODE_PROP_BLOB) {
++	} else if (drm_property_type_is(property, DRM_MODE_PROP_BLOB)) {
+ 		/* Only the driver knows */
+ 		return true;
++	} else if (drm_property_type_is(property, DRM_MODE_PROP_OBJECT)) {
++		struct drm_mode_object *obj;
++		/* a zero value for an object property translates to null: */
++		if (value == 0)
++			return true;
++		/*
++		 * NOTE: use _object_find() directly to bypass restriction on
++		 * looking up refcnt'd objects (ie. fb's).  For a refcnt'd
++		 * object this could race against object finalization, so it
++		 * simply tells us that the object *was* valid.  Which is good
++		 * enough.
++		 */
++		obj = _object_find(property->dev, value, property->values[0]);
++		return obj != NULL;
+ 	} else {
+ 		int i;
+ 		for (i = 0; i < property->num_values; i++)
+@@ -3287,6 +4241,20 @@
+ 	}
+ }
+ 
++/**
++ * drm_mode_connector_property_set_ioctl - set the current value of a connector property
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This function sets the current value for a connectors's property. It also
++ * calls into a driver's ->set_property callback to update the hardware state
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
+ 				       void *data, struct drm_file *file_priv)
+ {
+@@ -3338,12 +4306,25 @@
+ 	return ret;
+ }
+ 
+-static int drm_mode_plane_set_obj_prop(struct drm_mode_object *obj,
+-				      struct drm_property *property,
+-				      uint64_t value)
++/**
++ * drm_mode_plane_set_obj_prop - set the value of a property
++ * @plane: drm plane object to set property value for
++ * @property: property to set
++ * @value: value the property should be set to
++ *
++ * This functions sets a given property on a given plane object. This function
++ * calls the driver's ->set_property callback and changes the software state of
++ * the property if the callback succeeds.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
++int drm_mode_plane_set_obj_prop(struct drm_plane *plane,
++				struct drm_property *property,
++				uint64_t value)
+ {
+ 	int ret = -EINVAL;
+-	struct drm_plane *plane = obj_to_plane(obj);
++	struct drm_mode_object *obj = &plane->base;
+ 
+ 	if (plane->funcs->set_property)
+ 		ret = plane->funcs->set_property(plane, property, value);
+@@ -3352,7 +4333,23 @@
+ 
+ 	return ret;
+ }
++EXPORT_SYMBOL(drm_mode_plane_set_obj_prop);
+ 
++/**
++ * drm_mode_obj_get_properties_ioctl - get the current value of a object's property
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This function retrieves the current value for an object's property. Compared
++ * to the connector specific ioctl this one is extended to also work on crtc and
++ * plane objects.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data,
+ 				      struct drm_file *file_priv)
+ {
+@@ -3409,6 +4406,22 @@
+ 	return ret;
+ }
+ 
++/**
++ * drm_mode_obj_set_property_ioctl - set the current value of an object's property
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This function sets the current value for an object's property. It also calls
++ * into a driver's ->set_property callback to update the hardware state.
++ * Compared to the connector specific ioctl this one is extended to also work on
++ * crtc and plane objects.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data,
+ 				    struct drm_file *file_priv)
+ {
+@@ -3459,7 +4472,8 @@
+ 		ret = drm_mode_crtc_set_obj_prop(arg_obj, property, arg->value);
+ 		break;
+ 	case DRM_MODE_OBJECT_PLANE:
+-		ret = drm_mode_plane_set_obj_prop(arg_obj, property, arg->value);
++		ret = drm_mode_plane_set_obj_prop(obj_to_plane(arg_obj),
++						  property, arg->value);
+ 		break;
+ 	}
+ 
+@@ -3468,6 +4482,18 @@
+ 	return ret;
+ }
+ 
++/**
++ * drm_mode_connector_attach_encoder - attach a connector to an encoder
++ * @connector: connector to attach
++ * @encoder: encoder to attach @connector to
++ *
++ * This function links up a connector to an encoder. Note that the routing
++ * restrictions between encoders and crtcs are exposed to userspace through the
++ * possible_clones and possible_crtcs bitmasks.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_connector_attach_encoder(struct drm_connector *connector,
+ 				      struct drm_encoder *encoder)
+ {
+@@ -3483,23 +4509,20 @@
+ }
+ EXPORT_SYMBOL(drm_mode_connector_attach_encoder);
+ 
+-void drm_mode_connector_detach_encoder(struct drm_connector *connector,
+-				    struct drm_encoder *encoder)
+-{
+-	int i;
+-	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+-		if (connector->encoder_ids[i] == encoder->base.id) {
+-			connector->encoder_ids[i] = 0;
+-			if (connector->encoder == encoder)
+-				connector->encoder = NULL;
+-			break;
+-		}
+-	}
+-}
+-EXPORT_SYMBOL(drm_mode_connector_detach_encoder);
+-
++/**
++ * drm_mode_crtc_set_gamma_size - set the gamma table size
++ * @crtc: CRTC to set the gamma table size for
++ * @gamma_size: size of the gamma table
++ *
++ * Drivers which support gamma tables should set this to the supported gamma
++ * table size when initializing the CRTC. Currently the drm core only supports a
++ * fixed gamma table size.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
+-				  int gamma_size)
++				 int gamma_size)
+ {
+ 	crtc->gamma_size = gamma_size;
+ 
+@@ -3513,11 +4536,24 @@
+ }
+ EXPORT_SYMBOL(drm_mode_crtc_set_gamma_size);
+ 
++/**
++ * drm_mode_gamma_set_ioctl - set the gamma table
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * Set the gamma table of a CRTC to the one passed in by the user. Userspace can
++ * inquire the required gamma table size through drm_mode_gamma_get_ioctl.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
+ 			     void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_crtc_lut *crtc_lut = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_crtc *crtc;
+ 	void *r_base, *g_base, *b_base;
+ 	int size;
+@@ -3527,12 +4563,11 @@
+ 		return -EINVAL;
+ 
+ 	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, crtc_lut->crtc_id, DRM_MODE_OBJECT_CRTC);
+-	if (!obj) {
++	crtc = drm_crtc_find(dev, crtc_lut->crtc_id);
++	if (!crtc) {
+ 		ret = -ENOENT;
+ 		goto out;
+ 	}
+-	crtc = obj_to_crtc(obj);
+ 
+ 	if (crtc->funcs->gamma_set == NULL) {
+ 		ret = -ENOSYS;
+@@ -3572,11 +4607,25 @@
+ 
+ }
+ 
++/**
++ * drm_mode_gamma_get_ioctl - get the gamma table
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * Copy the current gamma table into the storage provided. This also provides
++ * the gamma table size the driver expects, which can be used to size the
++ * allocated storage.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
+ 			     void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_crtc_lut *crtc_lut = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_crtc *crtc;
+ 	void *r_base, *g_base, *b_base;
+ 	int size;
+@@ -3586,12 +4635,11 @@
+ 		return -EINVAL;
+ 
+ 	drm_modeset_lock_all(dev);
+-	obj = drm_mode_object_find(dev, crtc_lut->crtc_id, DRM_MODE_OBJECT_CRTC);
+-	if (!obj) {
++	crtc = drm_crtc_find(dev, crtc_lut->crtc_id);
++	if (!crtc) {
+ 		ret = -ENOENT;
+ 		goto out;
+ 	}
+-	crtc = obj_to_crtc(obj);
+ 
+ 	/* memcpy into gamma store */
+ 	if (crtc_lut->gamma_size != crtc->gamma_size) {
+@@ -3622,13 +4670,30 @@
+ 	return ret;
+ }
+ 
++/**
++ * drm_mode_page_flip_ioctl - schedule an asynchronous fb update
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This schedules an asynchronous update on a given CRTC, called page flip.
++ * Optionally a drm event is generated to signal the completion of the event.
++ * Generic drivers cannot assume that a pageflip with changed framebuffer
++ * properties (including driver specific metadata like tiling layout) will work,
++ * but some drivers support e.g. pixel format changes through the pageflip
++ * ioctl.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_page_flip_ioctl(struct drm_device *dev,
+ 			     void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_crtc_page_flip *page_flip = data;
+-	struct drm_mode_object *obj;
+ 	struct drm_crtc *crtc;
+-	struct drm_framebuffer *fb = NULL, *old_fb = NULL;
++	struct drm_framebuffer *fb = NULL;
+ 	struct drm_pending_vblank_event *e = NULL;
+ 	unsigned long flags;
+ 	int ret = -EINVAL;
+@@ -3640,13 +4705,12 @@
+ 	if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) && !dev->mode_config.async_page_flip)
+ 		return -EINVAL;
+ 
+-	obj = drm_mode_object_find(dev, page_flip->crtc_id, DRM_MODE_OBJECT_CRTC);
+-	if (!obj)
++	crtc = drm_crtc_find(dev, page_flip->crtc_id);
++	if (!crtc)
+ 		return -ENOENT;
+-	crtc = obj_to_crtc(obj);
+ 
+-	mutex_lock(&crtc->mutex);
+-	if (crtc->fb == NULL) {
++	drm_modeset_lock_crtc(crtc, crtc->primary);
++	if (crtc->primary->fb == NULL) {
+ 		/* The framebuffer is currently unbound, presumably
+ 		 * due to a hotplug event, that userspace has not
+ 		 * yet discovered.
+@@ -3668,7 +4732,7 @@
+ 	if (ret)
+ 		goto out;
+ 
+-	if (crtc->fb->pixel_format != fb->pixel_format) {
++	if (crtc->primary->fb->pixel_format != fb->pixel_format) {
+ 		DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
+ 		ret = -EINVAL;
+ 		goto out;
+@@ -3701,7 +4765,7 @@
+ 			(void (*) (struct drm_pending_event *)) kfree;
+ 	}
+ 
+-	old_fb = crtc->fb;
++	crtc->primary->old_fb = crtc->primary->fb;
+ 	ret = crtc->funcs->page_flip(crtc, fb, e, page_flip->flags);
+ 	if (ret) {
+ 		if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
+@@ -3711,7 +4775,7 @@
+ 			kfree(e);
+ 		}
+ 		/* Keep the old fb, don't unref it. */
+-		old_fb = NULL;
++		crtc->primary->old_fb = NULL;
+ 	} else {
+ 		/*
+ 		 * Warn if the driver hasn't properly updated the crtc->fb
+@@ -3719,7 +4783,7 @@
+ 		 * Failing to do so will screw with the reference counting
+ 		 * on framebuffers.
+ 		 */
+-		WARN_ON(crtc->fb != fb);
++		WARN_ON(crtc->primary->fb != fb);
+ 		/* Unref only the old framebuffer. */
+ 		fb = NULL;
+ 	}
+@@ -3727,19 +4791,33 @@
+ out:
+ 	if (fb)
+ 		drm_framebuffer_unreference(fb);
+-	if (old_fb)
+-		drm_framebuffer_unreference(old_fb);
+-	mutex_unlock(&crtc->mutex);
++	if (crtc->primary->old_fb)
++		drm_framebuffer_unreference(crtc->primary->old_fb);
++	crtc->primary->old_fb = NULL;
++	drm_modeset_unlock_crtc(crtc);
+ 
+ 	return ret;
+ }
+ 
++/**
++ * drm_mode_config_reset - call ->reset callbacks
++ * @dev: drm device
++ *
++ * This functions calls all the crtc's, encoder's and connector's ->reset
++ * callback. Drivers can use this in e.g. their driver load or resume code to
++ * reset hardware and software state.
++ */
+ void drm_mode_config_reset(struct drm_device *dev)
+ {
+ 	struct drm_crtc *crtc;
++	struct drm_plane *plane;
+ 	struct drm_encoder *encoder;
+ 	struct drm_connector *connector;
+ 
++	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
++		if (plane->funcs->reset)
++			plane->funcs->reset(plane);
++
+ 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+ 		if (crtc->funcs->reset)
+ 			crtc->funcs->reset(crtc);
+@@ -3757,16 +4835,77 @@
+ }
+ EXPORT_SYMBOL(drm_mode_config_reset);
+ 
++/**
++ * drm_mode_create_dumb_ioctl - create a dumb backing storage buffer
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This creates a new dumb buffer in the driver's backing storage manager (GEM,
++ * TTM or something else entirely) and returns the resulting buffer handle. This
++ * handle can then be wrapped up into a framebuffer modeset object.
++ *
++ * Note that userspace is not allowed to use such objects for render
++ * acceleration - drivers must create their own private ioctls for such a use
++ * case.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_create_dumb_ioctl(struct drm_device *dev,
+ 			       void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_mode_create_dumb *args = data;
++	u32 cpp, stride, size;
+ 
+ 	if (!dev->driver->dumb_create)
+ 		return -ENOSYS;
++	if (!args->width || !args->height || !args->bpp)
++		return -EINVAL;
++
++	/* overflow checks for 32bit size calculations */
++	/* NOTE: DIV_ROUND_UP() can overflow */
++	cpp = DIV_ROUND_UP(args->bpp, 8);
++	if (!cpp || cpp > 0xffffffffU / args->width)
++		return -EINVAL;
++	stride = cpp * args->width;
++	if (args->height > 0xffffffffU / stride)
++		return -EINVAL;
++
++	/* test for wrap-around */
++	size = args->height * stride;
++	if (PAGE_ALIGN(size) == 0)
++		return -EINVAL;
++
++	/*
++	 * handle, pitch and size are output parameters. Zero them out to
++	 * prevent drivers from accidentally using uninitialized data. Since
++	 * not all existing userspace is clearing these fields properly we
++	 * cannot reject IOCTL with garbage in them.
++	 */
++	args->handle = 0;
++	args->pitch = 0;
++	args->size = 0;
++
+ 	return dev->driver->dumb_create(file_priv, dev, args);
+ }
+ 
++/**
++ * drm_mode_mmap_dumb_ioctl - create an mmap offset for a dumb backing storage buffer
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * Allocate an offset in the drm device node's address space to be able to
++ * memory map a dumb buffer.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_mmap_dumb_ioctl(struct drm_device *dev,
+ 			     void *data, struct drm_file *file_priv)
+ {
+@@ -3779,6 +4918,21 @@
+ 	return dev->driver->dumb_map_offset(file_priv, dev, args->handle, &args->offset);
+ }
+ 
++/**
++ * drm_mode_destroy_dumb_ioctl - destroy a dumb backing strage buffer
++ * @dev: DRM device
++ * @data: ioctl data
++ * @file_priv: DRM file info
++ *
++ * This destroys the userspace handle for the given dumb backing storage buffer.
++ * Since buffer objects must be reference counted in the kernel a buffer object
++ * won't be immediately freed if a framebuffer modeset object still uses it.
++ *
++ * Called by the user via ioctl.
++ *
++ * Returns:
++ * Zero on success, negative errno on failure.
++ */
+ int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
+ 				void *data, struct drm_file *file_priv)
+ {
+@@ -3790,9 +4944,14 @@
+ 	return dev->driver->dumb_destroy(file_priv, dev, args->handle);
+ }
+ 
+-/*
+- * Just need to support RGB formats here for compat with code that doesn't
+- * use pixel formats directly yet.
++/**
++ * drm_fb_get_bpp_depth - get the bpp/depth values for format
++ * @format: pixel format (DRM_FORMAT_*)
++ * @depth: storage for the depth value
++ * @bpp: storage for the bpp value
++ *
++ * This only supports RGB formats here for compat with code that doesn't use
++ * pixel formats directly yet.
+  */
+ void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth,
+ 			  int *bpp)
+@@ -3864,7 +5023,7 @@
+  * drm_format_num_planes - get the number of planes for format
+  * @format: pixel format (DRM_FORMAT_*)
+  *
+- * RETURNS:
++ * Returns:
+  * The number of planes used by the specified pixel format.
+  */
+ int drm_format_num_planes(uint32_t format)
+@@ -3899,7 +5058,7 @@
+  * @format: pixel format (DRM_FORMAT_*)
+  * @plane: plane index
+  *
+- * RETURNS:
++ * Returns:
+  * The bytes per pixel value for the specified plane.
+  */
+ int drm_format_plane_cpp(uint32_t format, int plane)
+@@ -3945,7 +5104,7 @@
+  * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor
+  * @format: pixel format (DRM_FORMAT_*)
+  *
+- * RETURNS:
++ * Returns:
+  * The horizontal chroma subsampling factor for the
+  * specified pixel format.
+  */
+@@ -3980,7 +5139,7 @@
+  * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor
+  * @format: pixel format (DRM_FORMAT_*)
+  *
+- * RETURNS:
++ * Returns:
+  * The vertical chroma subsampling factor for the
+  * specified pixel format.
+  */
+@@ -4002,6 +5161,36 @@
+ EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
+ 
+ /**
++ * drm_rotation_simplify() - Try to simplify the rotation
++ * @rotation: Rotation to be simplified
++ * @supported_rotations: Supported rotations
++ *
++ * Attempt to simplify the rotation to a form that is supported.
++ * Eg. if the hardware supports everything except DRM_REFLECT_X
++ * one could call this function like this:
++ *
++ * drm_rotation_simplify(rotation, BIT(DRM_ROTATE_0) |
++ *                       BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_180) |
++ *                       BIT(DRM_ROTATE_270) | BIT(DRM_REFLECT_Y));
++ *
++ * to eliminate the DRM_ROTATE_X flag. Depending on what kind of
++ * transforms the hardware supports, this function may not
++ * be able to produce a supported transform, so the caller should
++ * check the result afterwards.
++ */
++unsigned int drm_rotation_simplify(unsigned int rotation,
++				   unsigned int supported_rotations)
++{
++	if (rotation & ~supported_rotations) {
++		rotation ^= BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y);
++		rotation = (rotation & ~0xf) | BIT((ffs(rotation & 0xf) + 1) % 4);
++	}
++
++	return rotation;
++}
++EXPORT_SYMBOL(drm_rotation_simplify);
++
++/**
+  * drm_mode_config_init - initialize DRM mode_configuration structure
+  * @dev: DRM device
+  *
+@@ -4016,6 +5205,7 @@
+ void drm_mode_config_init(struct drm_device *dev)
+ {
+ 	mutex_init(&dev->mode_config.mutex);
++	drm_modeset_lock_init(&dev->mode_config.connection_mutex);
+ 	mutex_init(&dev->mode_config.idr_mutex);
+ 	mutex_init(&dev->mode_config.fb_lock);
+ 	INIT_LIST_HEAD(&dev->mode_config.fb_list);
+@@ -4027,9 +5217,11 @@
+ 	INIT_LIST_HEAD(&dev->mode_config.property_blob_list);
+ 	INIT_LIST_HEAD(&dev->mode_config.plane_list);
+ 	idr_init(&dev->mode_config.crtc_idr);
++	idr_init(&dev->mode_config.tile_idr);
+ 
+ 	drm_modeset_lock_all(dev);
+ 	drm_mode_create_standard_connector_properties(dev);
++	drm_mode_create_standard_plane_properties(dev);
+ 	drm_modeset_unlock_all(dev);
+ 
+ 	/* Just to be sure */
+@@ -4037,6 +5229,8 @@
+ 	dev->mode_config.num_connector = 0;
+ 	dev->mode_config.num_crtc = 0;
+ 	dev->mode_config.num_encoder = 0;
++	dev->mode_config.num_overlay_plane = 0;
++	dev->mode_config.num_total_plane = 0;
+ }
+ EXPORT_SYMBOL(drm_mode_config_init);
+ 
+@@ -4111,6 +5305,123 @@
+ 		crtc->funcs->destroy(crtc);
+ 	}
+ 
++	idr_destroy(&dev->mode_config.tile_idr);
+ 	idr_destroy(&dev->mode_config.crtc_idr);
++	drm_modeset_lock_fini(&dev->mode_config.connection_mutex);
+ }
+ EXPORT_SYMBOL(drm_mode_config_cleanup);
++
++struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
++						       unsigned int supported_rotations)
++{
++	static const struct drm_prop_enum_list props[] = {
++		{ DRM_ROTATE_0,   "rotate-0" },
++		{ DRM_ROTATE_90,  "rotate-90" },
++		{ DRM_ROTATE_180, "rotate-180" },
++		{ DRM_ROTATE_270, "rotate-270" },
++		{ DRM_REFLECT_X,  "reflect-x" },
++		{ DRM_REFLECT_Y,  "reflect-y" },
++	};
++
++	return drm_property_create_bitmask(dev, 0, "rotation",
++					   props, ARRAY_SIZE(props),
++					   supported_rotations);
++}
++EXPORT_SYMBOL(drm_mode_create_rotation_property);
++
++/**
++ * DOC: Tile group
++ *
++ * Tile groups are used to represent tiled monitors with a unique
++ * integer identifier. Tiled monitors using DisplayID v1.3 have
++ * a unique 8-byte handle, we store this in a tile group, so we
++ * have a common identifier for all tiles in a monitor group.
++ */
++static void drm_tile_group_free(struct kref *kref)
++{
++	struct drm_tile_group *tg = container_of(kref, struct drm_tile_group, refcount);
++	struct drm_device *dev = tg->dev;
++	mutex_lock(&dev->mode_config.idr_mutex);
++	idr_remove(&dev->mode_config.tile_idr, tg->id);
++	mutex_unlock(&dev->mode_config.idr_mutex);
++	kfree(tg);
++}
++
++/**
++ * drm_mode_put_tile_group - drop a reference to a tile group.
++ * @dev: DRM device
++ * @tg: tile group to drop reference to.
++ *
++ * drop reference to tile group and free if 0.
++ */
++void drm_mode_put_tile_group(struct drm_device *dev,
++			     struct drm_tile_group *tg)
++{
++	kref_put(&tg->refcount, drm_tile_group_free);
++}
++
++/**
++ * drm_mode_get_tile_group - get a reference to an existing tile group
++ * @dev: DRM device
++ * @topology: 8-bytes unique per monitor.
++ *
++ * Use the unique bytes to get a reference to an existing tile group.
++ *
++ * RETURNS:
++ * tile group or NULL if not found.
++ */
++struct drm_tile_group *drm_mode_get_tile_group(struct drm_device *dev,
++					       char topology[8])
++{
++	struct drm_tile_group *tg;
++	int id;
++	mutex_lock(&dev->mode_config.idr_mutex);
++	idr_for_each_entry(&dev->mode_config.tile_idr, tg, id) {
++		if (!memcmp(tg->group_data, topology, 8)) {
++			if (!kref_get_unless_zero(&tg->refcount))
++				tg = NULL;
++			mutex_unlock(&dev->mode_config.idr_mutex);
++			return tg;
++		}
++	}
++	mutex_unlock(&dev->mode_config.idr_mutex);
++	return NULL;
++}
++
++/**
++ * drm_mode_create_tile_group - create a tile group from a displayid description
++ * @dev: DRM device
++ * @topology: 8-bytes unique per monitor.
++ *
++ * Create a tile group for the unique monitor, and get a unique
++ * identifier for the tile group.
++ *
++ * RETURNS:
++ * new tile group or error.
++ */
++struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev,
++						  char topology[8])
++{
++	struct drm_tile_group *tg;
++	int ret;
++
++	tg = kzalloc(sizeof(*tg), GFP_KERNEL);
++	if (!tg)
++		return ERR_PTR(-ENOMEM);
++
++	kref_init(&tg->refcount);
++	memcpy(tg->group_data, topology, 8);
++	tg->dev = dev;
++
++	mutex_lock(&dev->mode_config.idr_mutex);
++	ret = idr_alloc(&dev->mode_config.tile_idr, tg, 1, 0, GFP_KERNEL);
++	if (ret >= 0) {
++		tg->id = ret;
++	} else {
++		kfree(tg);
++		tg = ERR_PTR(ret);
++	}
++
++	mutex_unlock(&dev->mode_config.idr_mutex);
++	return tg;
++}
+diff -Naur a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
+--- a/drivers/gpu/drm/drm_crtc_helper.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_crtc_helper.c	2015-03-26 14:42:38.714435422 +0530
+@@ -29,16 +29,40 @@
+  *      Jesse Barnes <jesse.barnes@intel.com>
+  */
+ 
++#include <linux/kernel.h>
+ #include <linux/export.h>
+ #include <linux/moduleparam.h>
+ 
+ #include <drm/drmP.h>
++#include <drm/drm_atomic.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_fb_helper.h>
++#include <drm/drm_plane_helper.h>
++#include <drm/drm_atomic_helper.h>
+ #include <drm/drm_edid.h>
+ 
++/**
++ * DOC: overview
++ *
++ * The CRTC modeset helper library provides a default set_config implementation
++ * in drm_crtc_helper_set_config(). Plus a few other convenience functions using
++ * the same callbacks which drivers can use to e.g. restore the modeset
++ * configuration on resume with drm_helper_resume_force_mode().
++ *
++ * The driver callbacks are mostly compatible with the atomic modeset helpers,
++ * except for the handling of the primary plane: Atomic helpers require that the
++ * primary plane is implemented as a real standalone plane and not directly tied
++ * to the CRTC state. For easier transition this library provides functions to
++ * implement the old semantics required by the CRTC helpers using the new plane
++ * and atomic helper callbacks.
++ *
++ * Drivers are strongly urged to convert to the atomic helpers (by way of first
++ * converting to the plane helpers). New drivers must not use these functions
++ * but need to implement the atomic interface instead, potentially using the
++ * atomic helpers for that.
++ */
+ MODULE_AUTHOR("David Airlie, Jesse Barnes");
+ MODULE_DESCRIPTION("DRM KMS helper");
+ MODULE_LICENSE("GPL and additional rights");
+@@ -72,165 +96,31 @@
+ }
+ EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head);
+ 
+-static bool drm_kms_helper_poll = true;
+-module_param_named(poll, drm_kms_helper_poll, bool, 0600);
+-
+-static void drm_mode_validate_flag(struct drm_connector *connector,
+-				   int flags)
+-{
+-	struct drm_display_mode *mode;
+-
+-	if (flags == (DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_INTERLACE |
+-		      DRM_MODE_FLAG_3D_MASK))
+-		return;
+-
+-	list_for_each_entry(mode, &connector->modes, head) {
+-		if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
+-				!(flags & DRM_MODE_FLAG_INTERLACE))
+-			mode->status = MODE_NO_INTERLACE;
+-		if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) &&
+-				!(flags & DRM_MODE_FLAG_DBLSCAN))
+-			mode->status = MODE_NO_DBLESCAN;
+-		if ((mode->flags & DRM_MODE_FLAG_3D_MASK) &&
+-				!(flags & DRM_MODE_FLAG_3D_MASK))
+-			mode->status = MODE_NO_STEREO;
+-	}
+-
+-	return;
+-}
+-
+-/**
+- * drm_helper_probe_single_connector_modes - get complete set of display modes
+- * @connector: connector to probe
+- * @maxX: max width for modes
+- * @maxY: max height for modes
+- *
+- * LOCKING:
+- * Caller must hold mode config lock.
+- *
+- * Based on the helper callbacks implemented by @connector try to detect all
+- * valid modes.  Modes will first be added to the connector's probed_modes list,
+- * then culled (based on validity and the @maxX, @maxY parameters) and put into
+- * the normal modes list.
+- *
+- * Intended to be use as a generic implementation of the ->fill_modes()
+- * @connector vfunc for drivers that use the crtc helpers for output mode
+- * filtering and detection.
+- *
+- * RETURNS:
+- * Number of modes found on @connector.
+- */
+-int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
+-					    uint32_t maxX, uint32_t maxY)
+-{
+-	struct drm_device *dev = connector->dev;
+-	struct drm_display_mode *mode;
+-	struct drm_connector_helper_funcs *connector_funcs =
+-		connector->helper_private;
+-	int count = 0;
+-	int mode_flags = 0;
+-	bool verbose_prune = true;
+-
+-	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
+-			drm_get_connector_name(connector));
+-	/* set all modes to the unverified state */
+-	list_for_each_entry(mode, &connector->modes, head)
+-		mode->status = MODE_UNVERIFIED;
+-
+-	if (connector->force) {
+-		if (connector->force == DRM_FORCE_ON)
+-			connector->status = connector_status_connected;
+-		else
+-			connector->status = connector_status_disconnected;
+-		if (connector->funcs->force)
+-			connector->funcs->force(connector);
+-	} else {
+-		connector->status = connector->funcs->detect(connector, true);
+-	}
+-
+-	/* Re-enable polling in case the global poll config changed. */
+-	if (drm_kms_helper_poll != dev->mode_config.poll_running)
+-		drm_kms_helper_poll_enable(dev);
+-
+-	dev->mode_config.poll_running = drm_kms_helper_poll;
+-
+-	if (connector->status == connector_status_disconnected) {
+-		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] disconnected\n",
+-			connector->base.id, drm_get_connector_name(connector));
+-		drm_mode_connector_update_edid_property(connector, NULL);
+-		verbose_prune = false;
+-		goto prune;
+-	}
+-
+-#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
+-	count = drm_load_edid_firmware(connector);
+-	if (count == 0)
+-#endif
+-		count = (*connector_funcs->get_modes)(connector);
+-
+-	if (count == 0 && connector->status == connector_status_connected)
+-		count = drm_add_modes_noedid(connector, 1024, 768);
+-	if (count == 0)
+-		goto prune;
+-
+-	drm_mode_connector_list_update(connector);
+-
+-	if (maxX && maxY)
+-		drm_mode_validate_size(dev, &connector->modes, maxX,
+-				       maxY, 0);
+-
+-	if (connector->interlace_allowed)
+-		mode_flags |= DRM_MODE_FLAG_INTERLACE;
+-	if (connector->doublescan_allowed)
+-		mode_flags |= DRM_MODE_FLAG_DBLSCAN;
+-	if (connector->stereo_allowed)
+-		mode_flags |= DRM_MODE_FLAG_3D_MASK;
+-	drm_mode_validate_flag(connector, mode_flags);
+-
+-	list_for_each_entry(mode, &connector->modes, head) {
+-		if (mode->status == MODE_OK)
+-			mode->status = connector_funcs->mode_valid(connector,
+-								   mode);
+-	}
+-
+-prune:
+-	drm_mode_prune_invalid(dev, &connector->modes, verbose_prune);
+-
+-	if (list_empty(&connector->modes))
+-		return 0;
+-
+-	list_for_each_entry(mode, &connector->modes, head)
+-		mode->vrefresh = drm_mode_vrefresh(mode);
+-
+-	drm_mode_sort(&connector->modes);
+-
+-	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed modes :\n", connector->base.id,
+-			drm_get_connector_name(connector));
+-	list_for_each_entry(mode, &connector->modes, head) {
+-		drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
+-		drm_mode_debug_printmodeline(mode);
+-	}
+-
+-	return count;
+-}
+-EXPORT_SYMBOL(drm_helper_probe_single_connector_modes);
+-
+ /**
+  * drm_helper_encoder_in_use - check if a given encoder is in use
+  * @encoder: encoder to check
+  *
+- * LOCKING:
+- * Caller must hold mode config lock.
++ * Checks whether @encoder is with the current mode setting output configuration
++ * in use by any connector. This doesn't mean that it is actually enabled since
++ * the DPMS state is tracked separately.
+  *
+- * Walk @encoders's DRM device's mode_config and see if it's in use.
+- *
+- * RETURNS:
+- * True if @encoder is part of the mode_config, false otherwise.
++ * Returns:
++ * True if @encoder is used, false otherwise.
+  */
+ bool drm_helper_encoder_in_use(struct drm_encoder *encoder)
+ {
+ 	struct drm_connector *connector;
+ 	struct drm_device *dev = encoder->dev;
++
++	/*
++	 * We can expect this mutex to be locked if we are not panicking.
++	 * Locking is currently fubar in the panic handler.
++	 */
++	if (!oops_in_progress) {
++		WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
++		WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
++	}
++
+ 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
+ 		if (connector->encoder == encoder)
+ 			return true;
+@@ -242,19 +132,25 @@
+  * drm_helper_crtc_in_use - check if a given CRTC is in a mode_config
+  * @crtc: CRTC to check
+  *
+- * LOCKING:
+- * Caller must hold mode config lock.
+- *
+- * Walk @crtc's DRM device's mode_config and see if it's in use.
++ * Checks whether @crtc is with the current mode setting output configuration
++ * in use by any connector. This doesn't mean that it is actually enabled since
++ * the DPMS state is tracked separately.
+  *
+- * RETURNS:
+- * True if @crtc is part of the mode_config, false otherwise.
++ * Returns:
++ * True if @crtc is used, false otherwise.
+  */
+ bool drm_helper_crtc_in_use(struct drm_crtc *crtc)
+ {
+ 	struct drm_encoder *encoder;
+ 	struct drm_device *dev = crtc->dev;
+-	/* FIXME: Locking around list access? */
++
++	/*
++	 * We can expect this mutex to be locked if we are not panicking.
++	 * Locking is currently fubar in the panic handler.
++	 */
++	if (!oops_in_progress)
++		WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
++
+ 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
+ 		if (encoder->crtc == crtc && drm_helper_encoder_in_use(encoder))
+ 			return true;
+@@ -279,33 +175,17 @@
+ 		encoder->bridge->funcs->post_disable(encoder->bridge);
+ }
+ 
+-/**
+- * drm_helper_disable_unused_functions - disable unused objects
+- * @dev: DRM device
+- *
+- * LOCKING:
+- * Caller must hold mode config lock.
+- *
+- * If an connector or CRTC isn't part of @dev's mode_config, it can be disabled
+- * by calling its dpms function, which should power it off.
+- */
+-void drm_helper_disable_unused_functions(struct drm_device *dev)
++static void __drm_helper_disable_unused_functions(struct drm_device *dev)
+ {
+ 	struct drm_encoder *encoder;
+-	struct drm_connector *connector;
+ 	struct drm_crtc *crtc;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+-		if (!connector->encoder)
+-			continue;
+-		if (connector->status == connector_status_disconnected)
+-			connector->encoder = NULL;
+-	}
++	drm_warn_on_modeset_not_all_locked(dev);
+ 
+ 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ 		if (!drm_helper_encoder_in_use(encoder)) {
+ 			drm_encoder_disable(encoder);
+-			/* disconnector encoder from any connector */
++			/* disconnect encoder from any connector */
+ 			encoder->crtc = NULL;
+ 		}
+ 	}
+@@ -318,10 +198,27 @@
+ 				(*crtc_funcs->disable)(crtc);
+ 			else
+ 				(*crtc_funcs->dpms)(crtc, DRM_MODE_DPMS_OFF);
+-			crtc->fb = NULL;
++			crtc->primary->fb = NULL;
+ 		}
+ 	}
+ }
++
++/**
++ * drm_helper_disable_unused_functions - disable unused objects
++ * @dev: DRM device
++ *
++ * This function walks through the entire mode setting configuration of @dev. It
++ * will remove any crtc links of unused encoders and encoder links of
++ * disconnected connectors. Then it will disable all unused encoders and crtcs
++ * either by calling their disable callback if available or by calling their
++ * dpms callback with DRM_MODE_DPMS_OFF.
++ */
++void drm_helper_disable_unused_functions(struct drm_device *dev)
++{
++	drm_modeset_lock_all(dev);
++	__drm_helper_disable_unused_functions(dev);
++	drm_modeset_unlock_all(dev);
++}
+ EXPORT_SYMBOL(drm_helper_disable_unused_functions);
+ 
+ /*
+@@ -355,9 +252,6 @@
+  * @y: vertical offset into the surface
+  * @old_fb: old framebuffer, for cleanup
+  *
+- * LOCKING:
+- * Caller must hold mode config lock.
+- *
+  * Try to set @mode on @crtc.  Give @crtc and its associated connectors a chance
+  * to fixup or reject the mode prior to trying to set it. This is an internal
+  * helper that drivers could e.g. use to update properties that require the
+@@ -367,8 +261,8 @@
+  * drm_crtc_helper_set_config() helper function to drive the mode setting
+  * sequence.
+  *
+- * RETURNS:
+- * True if the mode was set successfully, or false otherwise.
++ * Returns:
++ * True if the mode was set successfully, false otherwise.
+  */
+ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ 			      struct drm_display_mode *mode,
+@@ -384,6 +278,8 @@
+ 	struct drm_encoder *encoder;
+ 	bool ret = true;
+ 
++	drm_warn_on_modeset_not_all_locked(dev);
++
+ 	saved_enabled = crtc->enabled;
+ 	crtc->enabled = drm_helper_crtc_in_use(crtc);
+ 	if (!crtc->enabled)
+@@ -472,7 +368,7 @@
+ 			continue;
+ 
+ 		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
+-			encoder->base.id, drm_get_encoder_name(encoder),
++			encoder->base.id, encoder->name,
+ 			mode->base.id, mode->name);
+ 		encoder_funcs = encoder->helper_private;
+ 		encoder_funcs->mode_set(encoder, mode, adjusted_mode);
+@@ -523,8 +419,7 @@
+ }
+ EXPORT_SYMBOL(drm_crtc_helper_set_mode);
+ 
+-
+-static int
++static void
+ drm_crtc_helper_disable(struct drm_crtc *crtc)
+ {
+ 	struct drm_device *dev = crtc->dev;
+@@ -552,25 +447,21 @@
+ 		}
+ 	}
+ 
+-	drm_helper_disable_unused_functions(dev);
+-	return 0;
++	__drm_helper_disable_unused_functions(dev);
+ }
+ 
+ /**
+  * drm_crtc_helper_set_config - set a new config from userspace
+  * @set: mode set configuration
+  *
+- * LOCKING:
+- * Caller must hold mode config lock.
+- *
+  * Setup a new configuration, provided by the upper layers (either an ioctl call
+- * from userspace or internally e.g. from the fbdev suppport code) in @set, and
++ * from userspace or internally e.g. from the fbdev support code) in @set, and
+  * enable it. This is the main helper functions for drivers that implement
+  * kernel mode setting with the crtc helper functions and the assorted
+  * ->prepare(), ->modeset() and ->commit() helper callbacks.
+  *
+- * RETURNS:
+- * Returns 0 on success, -ERRNO on failure.
++ * Returns:
++ * Returns 0 on success, negative errno numbers on failure.
+  */
+ int drm_crtc_helper_set_config(struct drm_mode_set *set)
+ {
+@@ -607,11 +498,14 @@
+ 				(int)set->num_connectors, set->x, set->y);
+ 	} else {
+ 		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
+-		return drm_crtc_helper_disable(set->crtc);
++		drm_crtc_helper_disable(set->crtc);
++		return 0;
+ 	}
+ 
+ 	dev = set->crtc->dev;
+ 
++	drm_warn_on_modeset_not_all_locked(dev);
++
+ 	/*
+ 	 * Allocate space for the backup of all (non-pointer) encoder and
+ 	 * connector data.
+@@ -647,19 +541,19 @@
+ 	save_set.mode = &set->crtc->mode;
+ 	save_set.x = set->crtc->x;
+ 	save_set.y = set->crtc->y;
+-	save_set.fb = set->crtc->fb;
++	save_set.fb = set->crtc->primary->fb;
+ 
+ 	/* We should be able to check here if the fb has the same properties
+ 	 * and then just flip_or_move it */
+-	if (set->crtc->fb != set->fb) {
++	if (set->crtc->primary->fb != set->fb) {
+ 		/* If we have no fb then treat it as a full mode set */
+-		if (set->crtc->fb == NULL) {
++		if (set->crtc->primary->fb == NULL) {
+ 			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
+ 			mode_changed = true;
+ 		} else if (set->fb == NULL) {
+ 			mode_changed = true;
+ 		} else if (set->fb->pixel_format !=
+-			   set->crtc->fb->pixel_format) {
++			   set->crtc->primary->fb->pixel_format) {
+ 			mode_changed = true;
+ 		} else
+ 			fb_changed = true;
+@@ -689,12 +583,13 @@
+ 				if (new_encoder == NULL)
+ 					/* don't break so fail path works correct */
+ 					fail = 1;
+-				break;
+ 
+ 				if (connector->dpms != DRM_MODE_DPMS_ON) {
+ 					DRM_DEBUG_KMS("connector dpms not on, full mode switch\n");
+ 					mode_changed = true;
+ 				}
++
++				break;
+ 			}
+ 		}
+ 
+@@ -743,11 +638,11 @@
+ 		}
+ 		if (new_crtc) {
+ 			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
+-				connector->base.id, drm_get_connector_name(connector),
++				connector->base.id, connector->name,
+ 				new_crtc->base.id);
+ 		} else {
+ 			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
+-				connector->base.id, drm_get_connector_name(connector));
++				connector->base.id, connector->name);
+ 		}
+ 	}
+ 
+@@ -760,34 +655,34 @@
+ 			DRM_DEBUG_KMS("attempting to set mode from"
+ 					" userspace\n");
+ 			drm_mode_debug_printmodeline(set->mode);
+-			set->crtc->fb = set->fb;
++			set->crtc->primary->fb = set->fb;
+ 			if (!drm_crtc_helper_set_mode(set->crtc, set->mode,
+ 						      set->x, set->y,
+ 						      save_set.fb)) {
+ 				DRM_ERROR("failed to set mode on [CRTC:%d]\n",
+ 					  set->crtc->base.id);
+-				set->crtc->fb = save_set.fb;
++				set->crtc->primary->fb = save_set.fb;
+ 				ret = -EINVAL;
+ 				goto fail;
+ 			}
+ 			DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
+ 			for (i = 0; i < set->num_connectors; i++) {
+ 				DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
+-					      drm_get_connector_name(set->connectors[i]));
++					      set->connectors[i]->name);
+ 				set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
+ 			}
+ 		}
+-		drm_helper_disable_unused_functions(dev);
++		__drm_helper_disable_unused_functions(dev);
+ 	} else if (fb_changed) {
+ 		set->crtc->x = set->x;
+ 		set->crtc->y = set->y;
+-		set->crtc->fb = set->fb;
++		set->crtc->primary->fb = set->fb;
+ 		ret = crtc_funcs->mode_set_base(set->crtc,
+ 						set->x, set->y, save_set.fb);
+ 		if (ret != 0) {
+ 			set->crtc->x = save_set.x;
+ 			set->crtc->y = save_set.y;
+-			set->crtc->fb = save_set.fb;
++			set->crtc->primary->fb = save_set.fb;
+ 			goto fail;
+ 		}
+ 	}
+@@ -924,8 +819,16 @@
+ }
+ EXPORT_SYMBOL(drm_helper_connector_dpms);
+ 
+-int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
+-				   struct drm_mode_fb_cmd2 *mode_cmd)
++/**
++ * drm_helper_mode_fill_fb_struct - fill out framebuffer metadata
++ * @fb: drm_framebuffer object to fill out
++ * @mode_cmd: metadata from the userspace fb creation request
++ *
++ * This helper can be used in a drivers fb_create callback to pre-fill the fb's
++ * metadata fields.
++ */
++void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
++				    struct drm_mode_fb_cmd2 *mode_cmd)
+ {
+ 	int i;
+ 
+@@ -938,26 +841,48 @@
+ 	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
+ 				    &fb->bits_per_pixel);
+ 	fb->pixel_format = mode_cmd->pixel_format;
+-
+-	return 0;
++	fb->flags = mode_cmd->flags;
+ }
+ EXPORT_SYMBOL(drm_helper_mode_fill_fb_struct);
+ 
+-int drm_helper_resume_force_mode(struct drm_device *dev)
++/**
++ * drm_helper_resume_force_mode - force-restore mode setting configuration
++ * @dev: drm_device which should be restored
++ *
++ * Drivers which use the mode setting helpers can use this function to
++ * force-restore the mode setting configuration e.g. on resume or when something
++ * else might have trampled over the hw state (like some overzealous old BIOSen
++ * tended to do).
++ *
++ * This helper doesn't provide a error return value since restoring the old
++ * config should never fail due to resource allocation issues since the driver
++ * has successfully set the restored configuration already. Hence this should
++ * boil down to the equivalent of a few dpms on calls, which also don't provide
++ * an error code.
++ *
++ * Drivers where simply restoring an old configuration again might fail (e.g.
++ * due to slight differences in allocating shared resources when the
++ * configuration is restored in a different order than when userspace set it up)
++ * need to use their own restore logic.
++ */
++void drm_helper_resume_force_mode(struct drm_device *dev)
+ {
+ 	struct drm_crtc *crtc;
+ 	struct drm_encoder *encoder;
+ 	struct drm_crtc_helper_funcs *crtc_funcs;
+-	int ret, encoder_dpms;
++	int encoder_dpms;
++	bool ret;
+ 
++	drm_modeset_lock_all(dev);
+ 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ 
+ 		if (!crtc->enabled)
+ 			continue;
+ 
+ 		ret = drm_crtc_helper_set_mode(crtc, &crtc->mode,
+-					       crtc->x, crtc->y, crtc->fb);
++					       crtc->x, crtc->y, crtc->primary->fb);
+ 
++		/* Restoring the old config should never fail! */
+ 		if (ret == false)
+ 			DRM_ERROR("failed to set mode on crtc %p\n", crtc);
+ 
+@@ -980,155 +905,118 @@
+ 						     drm_helper_choose_crtc_dpms(crtc));
+ 		}
+ 	}
++
+ 	/* disable the unused connectors while restoring the modesetting */
+-	drm_helper_disable_unused_functions(dev);
+-	return 0;
++	__drm_helper_disable_unused_functions(dev);
++	drm_modeset_unlock_all(dev);
+ }
+ EXPORT_SYMBOL(drm_helper_resume_force_mode);
+ 
+-void drm_kms_helper_hotplug_event(struct drm_device *dev)
+-{
+-	/* send a uevent + call fbdev */
+-	drm_sysfs_hotplug_event(dev);
+-	if (dev->mode_config.funcs->output_poll_changed)
+-		dev->mode_config.funcs->output_poll_changed(dev);
+-}
+-EXPORT_SYMBOL(drm_kms_helper_hotplug_event);
+-
+-#define DRM_OUTPUT_POLL_PERIOD (10*HZ)
+-static void output_poll_execute(struct work_struct *work)
++/**
++ * drm_helper_crtc_mode_set - mode_set implementation for atomic plane helpers
++ * @crtc: DRM CRTC
++ * @mode: DRM display mode which userspace requested
++ * @adjusted_mode: DRM display mode adjusted by ->mode_fixup callbacks
++ * @x: x offset of the CRTC scanout area on the underlying framebuffer
++ * @y: y offset of the CRTC scanout area on the underlying framebuffer
++ * @old_fb: previous framebuffer
++ *
++ * This function implements a callback useable as the ->mode_set callback
++ * required by the crtc helpers. Besides the atomic plane helper functions for
++ * the primary plane the driver must also provide the ->mode_set_nofb callback
++ * to set up the crtc.
++ *
++ * This is a transitional helper useful for converting drivers to the atomic
++ * interfaces.
++ */
++int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
++			     struct drm_display_mode *adjusted_mode, int x, int y,
++			     struct drm_framebuffer *old_fb)
+ {
+-	struct delayed_work *delayed_work = to_delayed_work(work);
+-	struct drm_device *dev = container_of(delayed_work, struct drm_device, mode_config.output_poll_work);
+-	struct drm_connector *connector;
+-	enum drm_connector_status old_status;
+-	bool repoll = false, changed = false;
+-
+-	if (!drm_kms_helper_poll)
+-		return;
+-
+-	mutex_lock(&dev->mode_config.mutex);
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+-
+-		/* Ignore forced connectors. */
+-		if (connector->force)
+-			continue;
+-
+-		/* Ignore HPD capable connectors and connectors where we don't
+-		 * want any hotplug detection at all for polling. */
+-		if (!connector->polled || connector->polled == DRM_CONNECTOR_POLL_HPD)
+-			continue;
++	struct drm_crtc_state *crtc_state;
++	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
++	int ret;
+ 
+-		repoll = true;
++	if (crtc->funcs->atomic_duplicate_state)
++		crtc_state = crtc->funcs->atomic_duplicate_state(crtc);
++	else if (crtc->state)
++		crtc_state = kmemdup(crtc->state, sizeof(*crtc_state),
++				     GFP_KERNEL);
++	else
++		crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
++	if (!crtc_state)
++		return -ENOMEM;
+ 
+-		old_status = connector->status;
+-		/* if we are connected and don't want to poll for disconnect
+-		   skip it */
+-		if (old_status == connector_status_connected &&
+-		    !(connector->polled & DRM_CONNECTOR_POLL_DISCONNECT))
+-			continue;
++	crtc_state->enable = true;
++	crtc_state->planes_changed = true;
++	crtc_state->mode_changed = true;
++	drm_mode_copy(&crtc_state->mode, mode);
++	drm_mode_copy(&crtc_state->adjusted_mode, adjusted_mode);
+ 
+-		connector->status = connector->funcs->detect(connector, false);
+-		if (old_status != connector->status) {
+-			const char *old, *new;
+-
+-			old = drm_get_connector_status_name(old_status);
+-			new = drm_get_connector_status_name(connector->status);
+-
+-			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] "
+-				      "status updated from %s to %s\n",
+-				      connector->base.id,
+-				      drm_get_connector_name(connector),
+-				      old, new);
++	if (crtc_funcs->atomic_check) {
++		ret = crtc_funcs->atomic_check(crtc, crtc_state);
++		if (ret) {
++			kfree(crtc_state);
+ 
+-			changed = true;
++			return ret;
+ 		}
+ 	}
+ 
+-	mutex_unlock(&dev->mode_config.mutex);
+-
+-	if (changed)
+-		drm_kms_helper_hotplug_event(dev);
+-
+-	if (repoll)
+-		schedule_delayed_work(delayed_work, DRM_OUTPUT_POLL_PERIOD);
+-}
++	swap(crtc->state, crtc_state);
+ 
+-void drm_kms_helper_poll_disable(struct drm_device *dev)
+-{
+-	if (!dev->mode_config.poll_enabled)
+-		return;
+-	cancel_delayed_work_sync(&dev->mode_config.output_poll_work);
+-}
+-EXPORT_SYMBOL(drm_kms_helper_poll_disable);
++	crtc_funcs->mode_set_nofb(crtc);
+ 
+-void drm_kms_helper_poll_enable(struct drm_device *dev)
+-{
+-	bool poll = false;
+-	struct drm_connector *connector;
+-
+-	if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll)
+-		return;
+-
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+-		if (connector->polled & (DRM_CONNECTOR_POLL_CONNECT |
+-					 DRM_CONNECTOR_POLL_DISCONNECT))
+-			poll = true;
++	if (crtc_state) {
++		if (crtc->funcs->atomic_destroy_state)
++			crtc->funcs->atomic_destroy_state(crtc, crtc_state);
++		else
++			kfree(crtc_state);
+ 	}
+ 
+-	if (poll)
+-		schedule_delayed_work(&dev->mode_config.output_poll_work, DRM_OUTPUT_POLL_PERIOD);
+-}
+-EXPORT_SYMBOL(drm_kms_helper_poll_enable);
+-
+-void drm_kms_helper_poll_init(struct drm_device *dev)
+-{
+-	INIT_DELAYED_WORK(&dev->mode_config.output_poll_work, output_poll_execute);
+-	dev->mode_config.poll_enabled = true;
+-
+-	drm_kms_helper_poll_enable(dev);
++	return drm_helper_crtc_mode_set_base(crtc, x, y, old_fb);
+ }
+-EXPORT_SYMBOL(drm_kms_helper_poll_init);
++EXPORT_SYMBOL(drm_helper_crtc_mode_set);
+ 
+-void drm_kms_helper_poll_fini(struct drm_device *dev)
+-{
+-	drm_kms_helper_poll_disable(dev);
+-}
+-EXPORT_SYMBOL(drm_kms_helper_poll_fini);
+-
+-bool drm_helper_hpd_irq_event(struct drm_device *dev)
++/**
++ * drm_helper_crtc_mode_set_base - mode_set_base implementation for atomic plane helpers
++ * @crtc: DRM CRTC
++ * @x: x offset of the CRTC scanout area on the underlying framebuffer
++ * @y: y offset of the CRTC scanout area on the underlying framebuffer
++ * @old_fb: previous framebuffer
++ *
++ * This function implements a callback useable as the ->mode_set_base used
++ * required by the crtc helpers. The driver must provide the atomic plane helper
++ * functions for the primary plane.
++ *
++ * This is a transitional helper useful for converting drivers to the atomic
++ * interfaces.
++ */
++int drm_helper_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
++				  struct drm_framebuffer *old_fb)
+ {
+-	struct drm_connector *connector;
+-	enum drm_connector_status old_status;
+-	bool changed = false;
+-
+-	if (!dev->mode_config.poll_enabled)
+-		return false;
++	struct drm_plane_state *plane_state;
++	struct drm_plane *plane = crtc->primary;
+ 
+-	mutex_lock(&dev->mode_config.mutex);
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+-
+-		/* Only handle HPD capable connectors. */
+-		if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
+-			continue;
+-
+-		old_status = connector->status;
+-
+-		connector->status = connector->funcs->detect(connector, false);
+-		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
+-			      connector->base.id,
+-			      drm_get_connector_name(connector),
+-			      drm_get_connector_status_name(old_status),
+-			      drm_get_connector_status_name(connector->status));
+-		if (old_status != connector->status)
+-			changed = true;
+-	}
+-
+-	mutex_unlock(&dev->mode_config.mutex);
++	if (plane->funcs->atomic_duplicate_state)
++		plane_state = plane->funcs->atomic_duplicate_state(plane);
++	else if (plane->state)
++		plane_state = drm_atomic_helper_plane_duplicate_state(plane);
++	else
++		plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
++	if (!plane_state)
++		return -ENOMEM;
+ 
+-	if (changed)
+-		drm_kms_helper_hotplug_event(dev);
++	plane_state->crtc = crtc;
++	drm_atomic_set_fb_for_plane(plane_state, crtc->primary->fb);
++	plane_state->crtc_x = 0;
++	plane_state->crtc_y = 0;
++	plane_state->crtc_h = crtc->mode.vdisplay;
++	plane_state->crtc_w = crtc->mode.hdisplay;
++	plane_state->src_x = x << 16;
++	plane_state->src_y = y << 16;
++	plane_state->src_h = crtc->mode.vdisplay << 16;
++	plane_state->src_w = crtc->mode.hdisplay << 16;
+ 
+-	return changed;
++	return drm_plane_helper_commit(plane, plane_state, old_fb);
+ }
+-EXPORT_SYMBOL(drm_helper_hpd_irq_event);
++EXPORT_SYMBOL(drm_helper_crtc_mode_set_base);
+diff -Naur a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h
+--- a/drivers/gpu/drm/drm_crtc_internal.h	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_crtc_internal.h	2015-03-26 14:42:38.714435422 +0530
+@@ -0,0 +1,38 @@
++/*
++ * Copyright © 2006 Keith Packard
++ * Copyright © 2007-2008 Dave Airlie
++ * Copyright © 2007-2008 Intel Corporation
++ *   Jesse Barnes <jesse.barnes@intel.com>
++ * Copyright © 2014 Intel Corporation
++ *   Daniel Vetter <daniel.vetter@ffwll.ch>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/*
++ * This header file contains mode setting related functions and definitions
++ * which are only used within the drm module as internal implementation details
++ * and are not exported to drivers.
++ */
++
++int drm_mode_object_get(struct drm_device *dev,
++			struct drm_mode_object *obj, uint32_t obj_type);
++void drm_mode_object_put(struct drm_device *dev,
++			 struct drm_mode_object *object);
++
+diff -Naur a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
+--- a/drivers/gpu/drm/drm_debugfs.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_debugfs.c	2015-03-26 14:42:38.714435422 +0530
+@@ -35,6 +35,8 @@
+ #include <linux/slab.h>
+ #include <linux/export.h>
+ #include <drm/drmP.h>
++#include <drm/drm_edid.h>
++#include "drm_internal.h"
+ 
+ #if defined(CONFIG_DEBUG_FS)
+ 
+@@ -48,9 +50,7 @@
+ 	{"clients", drm_clients_info, 0},
+ 	{"bufs", drm_bufs_info, 0},
+ 	{"gem_names", drm_gem_name_info, DRIVER_GEM},
+-#if DRM_DEBUG_CODE
+ 	{"vma", drm_vma_info, 0},
+-#endif
+ };
+ #define DRM_DEBUGFS_ENTRIES ARRAY_SIZE(drm_debugfs_list)
+ 
+@@ -237,5 +237,186 @@
+ 	return 0;
+ }
+ 
++static int connector_show(struct seq_file *m, void *data)
++{
++	struct drm_connector *connector = m->private;
++	const char *status;
++
++	switch (connector->force) {
++	case DRM_FORCE_ON:
++		status = "on\n";
++		break;
++
++	case DRM_FORCE_ON_DIGITAL:
++		status = "digital\n";
++		break;
++
++	case DRM_FORCE_OFF:
++		status = "off\n";
++		break;
++
++	case DRM_FORCE_UNSPECIFIED:
++		status = "unspecified\n";
++		break;
++
++	default:
++		return 0;
++	}
++
++	seq_puts(m, status);
++
++	return 0;
++}
++
++static int connector_open(struct inode *inode, struct file *file)
++{
++	struct drm_connector *dev = inode->i_private;
++
++	return single_open(file, connector_show, dev);
++}
++
++static ssize_t connector_write(struct file *file, const char __user *ubuf,
++			       size_t len, loff_t *offp)
++{
++	struct seq_file *m = file->private_data;
++	struct drm_connector *connector = m->private;
++	char buf[12];
++
++	if (len > sizeof(buf) - 1)
++		return -EINVAL;
++
++	if (copy_from_user(buf, ubuf, len))
++		return -EFAULT;
++
++	buf[len] = '\0';
++
++	if (!strcmp(buf, "on"))
++		connector->force = DRM_FORCE_ON;
++	else if (!strcmp(buf, "digital"))
++		connector->force = DRM_FORCE_ON_DIGITAL;
++	else if (!strcmp(buf, "off"))
++		connector->force = DRM_FORCE_OFF;
++	else if (!strcmp(buf, "unspecified"))
++		connector->force = DRM_FORCE_UNSPECIFIED;
++	else
++		return -EINVAL;
++
++	return len;
++}
++
++static int edid_show(struct seq_file *m, void *data)
++{
++	struct drm_connector *connector = m->private;
++	struct drm_property_blob *edid = connector->edid_blob_ptr;
++
++	if (connector->override_edid && edid)
++		seq_write(m, edid->data, edid->length);
++
++	return 0;
++}
++
++static int edid_open(struct inode *inode, struct file *file)
++{
++	struct drm_connector *dev = inode->i_private;
++
++	return single_open(file, edid_show, dev);
++}
++
++static ssize_t edid_write(struct file *file, const char __user *ubuf,
++			  size_t len, loff_t *offp)
++{
++	struct seq_file *m = file->private_data;
++	struct drm_connector *connector = m->private;
++	char *buf;
++	struct edid *edid;
++	int ret;
++
++	buf = memdup_user(ubuf, len);
++	if (IS_ERR(buf))
++		return PTR_ERR(buf);
++
++	edid = (struct edid *) buf;
++
++	if (len == 5 && !strncmp(buf, "reset", 5)) {
++		connector->override_edid = false;
++		ret = drm_mode_connector_update_edid_property(connector, NULL);
++	} else if (len < EDID_LENGTH ||
++		   EDID_LENGTH * (1 + edid->extensions) > len)
++		ret = -EINVAL;
++	else {
++		connector->override_edid = false;
++		ret = drm_mode_connector_update_edid_property(connector, edid);
++		if (!ret)
++			connector->override_edid = true;
++	}
++
++	kfree(buf);
++
++	return (ret) ? ret : len;
++}
++
++static const struct file_operations drm_edid_fops = {
++	.owner = THIS_MODULE,
++	.open = edid_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++	.write = edid_write
++};
++
++
++static const struct file_operations drm_connector_fops = {
++	.owner = THIS_MODULE,
++	.open = connector_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++	.write = connector_write
++};
++
++int drm_debugfs_connector_add(struct drm_connector *connector)
++{
++	struct drm_minor *minor = connector->dev->primary;
++	struct dentry *root, *ent;
++
++	if (!minor->debugfs_root)
++		return -1;
++
++	root = debugfs_create_dir(connector->name, minor->debugfs_root);
++	if (!root)
++		return -ENOMEM;
++
++	connector->debugfs_entry = root;
++
++	/* force */
++	ent = debugfs_create_file("force", S_IRUGO | S_IWUSR, root, connector,
++				  &drm_connector_fops);
++	if (!ent)
++		goto error;
++
++	/* edid */
++	ent = debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root,
++				  connector, &drm_edid_fops);
++	if (!ent)
++		goto error;
++
++	return 0;
++
++error:
++	debugfs_remove_recursive(connector->debugfs_entry);
++	connector->debugfs_entry = NULL;
++	return -ENOMEM;
++}
++
++void drm_debugfs_connector_remove(struct drm_connector *connector)
++{
++	if (!connector->debugfs_entry)
++		return;
++
++	debugfs_remove_recursive(connector->debugfs_entry);
++
++	connector->debugfs_entry = NULL;
++}
++
+ #endif /* CONFIG_DEBUG_FS */
+ 
+diff -Naur a/drivers/gpu/drm/drm_dma.c b/drivers/gpu/drm/drm_dma.c
+--- a/drivers/gpu/drm/drm_dma.c	2015-03-26 14:43:30.418436435 +0530
++++ b/drivers/gpu/drm/drm_dma.c	2015-03-26 14:42:38.714435422 +0530
+@@ -35,6 +35,7 @@
+ 
+ #include <linux/export.h>
+ #include <drm/drmP.h>
++#include "drm_legacy.h"
+ 
+ /**
+  * Initialize the DMA data.
+@@ -124,7 +125,7 @@
+  *
+  * Resets the fields of \p buf.
+  */
+-void drm_free_buffer(struct drm_device *dev, struct drm_buf * buf)
++void drm_legacy_free_buffer(struct drm_device *dev, struct drm_buf * buf)
+ {
+ 	if (!buf)
+ 		return;
+@@ -142,8 +143,8 @@
+  *
+  * Frees each buffer associated with \p file_priv not already on the hardware.
+  */
+-void drm_core_reclaim_buffers(struct drm_device *dev,
+-			      struct drm_file *file_priv)
++void drm_legacy_reclaim_buffers(struct drm_device *dev,
++				struct drm_file *file_priv)
+ {
+ 	struct drm_device_dma *dma = dev->dma;
+ 	int i;
+@@ -154,7 +155,7 @@
+ 		if (dma->buflist[i]->file_priv == file_priv) {
+ 			switch (dma->buflist[i]->list) {
+ 			case DRM_LIST_NONE:
+-				drm_free_buffer(dev, dma->buflist[i]);
++				drm_legacy_free_buffer(dev, dma->buflist[i]);
+ 				break;
+ 			case DRM_LIST_WAIT:
+ 				dma->buflist[i]->list = DRM_LIST_RECLAIM;
+@@ -166,5 +167,3 @@
+ 		}
+ 	}
+ }
+-
+-EXPORT_SYMBOL(drm_core_reclaim_buffers);
+diff -Naur a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
+--- a/drivers/gpu/drm/drm_dp_helper.c	2015-03-26 14:43:30.410436435 +0530
++++ b/drivers/gpu/drm/drm_dp_helper.c	2015-03-26 14:42:38.714435422 +0530
+@@ -39,194 +39,6 @@
+  * blocks, ...
+  */
+ 
+-/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
+-static int
+-i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
+-			    uint8_t write_byte, uint8_t *read_byte)
+-{
+-	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+-	int ret;
+-
+-	ret = (*algo_data->aux_ch)(adapter, mode,
+-				   write_byte, read_byte);
+-	return ret;
+-}
+-
+-/*
+- * I2C over AUX CH
+- */
+-
+-/*
+- * Send the address. If the I2C link is running, this 'restarts'
+- * the connection with the new address, this is used for doing
+- * a write followed by a read (as needed for DDC)
+- */
+-static int
+-i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
+-{
+-	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+-	int mode = MODE_I2C_START;
+-	int ret;
+-
+-	if (reading)
+-		mode |= MODE_I2C_READ;
+-	else
+-		mode |= MODE_I2C_WRITE;
+-	algo_data->address = address;
+-	algo_data->running = true;
+-	ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
+-	return ret;
+-}
+-
+-/*
+- * Stop the I2C transaction. This closes out the link, sending
+- * a bare address packet with the MOT bit turned off
+- */
+-static void
+-i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
+-{
+-	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+-	int mode = MODE_I2C_STOP;
+-
+-	if (reading)
+-		mode |= MODE_I2C_READ;
+-	else
+-		mode |= MODE_I2C_WRITE;
+-	if (algo_data->running) {
+-		(void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
+-		algo_data->running = false;
+-	}
+-}
+-
+-/*
+- * Write a single byte to the current I2C address, the
+- * the I2C link must be running or this returns -EIO
+- */
+-static int
+-i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
+-{
+-	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+-	int ret;
+-
+-	if (!algo_data->running)
+-		return -EIO;
+-
+-	ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
+-	return ret;
+-}
+-
+-/*
+- * Read a single byte from the current I2C address, the
+- * I2C link must be running or this returns -EIO
+- */
+-static int
+-i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
+-{
+-	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+-	int ret;
+-
+-	if (!algo_data->running)
+-		return -EIO;
+-
+-	ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
+-	return ret;
+-}
+-
+-static int
+-i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
+-		     struct i2c_msg *msgs,
+-		     int num)
+-{
+-	int ret = 0;
+-	bool reading = false;
+-	int m;
+-	int b;
+-
+-	for (m = 0; m < num; m++) {
+-		u16 len = msgs[m].len;
+-		u8 *buf = msgs[m].buf;
+-		reading = (msgs[m].flags & I2C_M_RD) != 0;
+-		ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
+-		if (ret < 0)
+-			break;
+-		if (reading) {
+-			for (b = 0; b < len; b++) {
+-				ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
+-				if (ret < 0)
+-					break;
+-			}
+-		} else {
+-			for (b = 0; b < len; b++) {
+-				ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
+-				if (ret < 0)
+-					break;
+-			}
+-		}
+-		if (ret < 0)
+-			break;
+-	}
+-	if (ret >= 0)
+-		ret = num;
+-	i2c_algo_dp_aux_stop(adapter, reading);
+-	DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
+-	return ret;
+-}
+-
+-static u32
+-i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
+-{
+-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
+-	       I2C_FUNC_SMBUS_READ_BLOCK_DATA |
+-	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
+-	       I2C_FUNC_10BIT_ADDR;
+-}
+-
+-static const struct i2c_algorithm i2c_dp_aux_algo = {
+-	.master_xfer	= i2c_algo_dp_aux_xfer,
+-	.functionality	= i2c_algo_dp_aux_functionality,
+-};
+-
+-static void
+-i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
+-{
+-	(void) i2c_algo_dp_aux_address(adapter, 0, false);
+-	(void) i2c_algo_dp_aux_stop(adapter, false);
+-}
+-
+-static int
+-i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
+-{
+-	adapter->algo = &i2c_dp_aux_algo;
+-	adapter->retries = 3;
+-	i2c_dp_aux_reset_bus(adapter);
+-	return 0;
+-}
+-
+-/**
+- * i2c_dp_aux_add_bus() - register an i2c adapter using the aux ch helper
+- * @adapter: i2c adapter to register
+- *
+- * This registers an i2c adapater that uses dp aux channel as it's underlaying
+- * transport. The driver needs to fill out the &i2c_algo_dp_aux_data structure
+- * and store it in the algo_data member of the @adapter argument. This will be
+- * used by the i2c over dp aux algorithm to drive the hardware.
+- *
+- * RETURNS:
+- * 0 on success, -ERRNO on failure.
+- */
+-int
+-i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
+-{
+-	int error;
+-
+-	error = i2c_dp_aux_prepare_bus(adapter);
+-	if (error)
+-		return error;
+-	error = i2c_add_adapter(adapter);
+-	return error;
+-}
+-EXPORT_SYMBOL(i2c_dp_aux_add_bus);
+-
+ /* Helpers for DP link training */
+ static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
+ {
+@@ -346,3 +158,424 @@
+ 	}
+ }
+ EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
++
++/**
++ * DOC: dp helpers
++ *
++ * The DisplayPort AUX channel is an abstraction to allow generic, driver-
++ * independent access to AUX functionality. Drivers can take advantage of
++ * this by filling in the fields of the drm_dp_aux structure.
++ *
++ * Transactions are described using a hardware-independent drm_dp_aux_msg
++ * structure, which is passed into a driver's .transfer() implementation.
++ * Both native and I2C-over-AUX transactions are supported.
++ */
++
++static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
++			      unsigned int offset, void *buffer, size_t size)
++{
++	struct drm_dp_aux_msg msg;
++	unsigned int retry;
++	int err;
++
++	memset(&msg, 0, sizeof(msg));
++	msg.address = offset;
++	msg.request = request;
++	msg.buffer = buffer;
++	msg.size = size;
++
++	/*
++	 * The specification doesn't give any recommendation on how often to
++	 * retry native transactions. We used to retry 7 times like for
++	 * aux i2c transactions but real world devices this wasn't
++	 * sufficient, bump to 32 which makes Dell 4k monitors happier.
++	 */
++	for (retry = 0; retry < 32; retry++) {
++
++		mutex_lock(&aux->hw_mutex);
++		err = aux->transfer(aux, &msg);
++		mutex_unlock(&aux->hw_mutex);
++		if (err < 0) {
++			if (err == -EBUSY)
++				continue;
++
++			return err;
++		}
++
++
++		switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) {
++		case DP_AUX_NATIVE_REPLY_ACK:
++			if (err < size)
++				return -EPROTO;
++			return err;
++
++		case DP_AUX_NATIVE_REPLY_NACK:
++			return -EIO;
++
++		case DP_AUX_NATIVE_REPLY_DEFER:
++			usleep_range(400, 500);
++			break;
++		}
++	}
++
++	DRM_DEBUG_KMS("too many retries, giving up\n");
++	return -EIO;
++}
++
++/**
++ * drm_dp_dpcd_read() - read a series of bytes from the DPCD
++ * @aux: DisplayPort AUX channel
++ * @offset: address of the (first) register to read
++ * @buffer: buffer to store the register values
++ * @size: number of bytes in @buffer
++ *
++ * Returns the number of bytes transferred on success, or a negative error
++ * code on failure. -EIO is returned if the request was NAKed by the sink or
++ * if the retry count was exceeded. If not all bytes were transferred, this
++ * function returns -EPROTO. Errors from the underlying AUX channel transfer
++ * function, with the exception of -EBUSY (which causes the transaction to
++ * be retried), are propagated to the caller.
++ */
++ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
++			 void *buffer, size_t size)
++{
++	return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
++				  size);
++}
++EXPORT_SYMBOL(drm_dp_dpcd_read);
++
++/**
++ * drm_dp_dpcd_write() - write a series of bytes to the DPCD
++ * @aux: DisplayPort AUX channel
++ * @offset: address of the (first) register to write
++ * @buffer: buffer containing the values to write
++ * @size: number of bytes in @buffer
++ *
++ * Returns the number of bytes transferred on success, or a negative error
++ * code on failure. -EIO is returned if the request was NAKed by the sink or
++ * if the retry count was exceeded. If not all bytes were transferred, this
++ * function returns -EPROTO. Errors from the underlying AUX channel transfer
++ * function, with the exception of -EBUSY (which causes the transaction to
++ * be retried), are propagated to the caller.
++ */
++ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
++			  void *buffer, size_t size)
++{
++	return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
++				  size);
++}
++EXPORT_SYMBOL(drm_dp_dpcd_write);
++
++/**
++ * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
++ * @aux: DisplayPort AUX channel
++ * @status: buffer to store the link status in (must be at least 6 bytes)
++ *
++ * Returns the number of bytes transferred on success or a negative error
++ * code on failure.
++ */
++int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
++				 u8 status[DP_LINK_STATUS_SIZE])
++{
++	return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
++				DP_LINK_STATUS_SIZE);
++}
++EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
++
++/**
++ * drm_dp_link_probe() - probe a DisplayPort link for capabilities
++ * @aux: DisplayPort AUX channel
++ * @link: pointer to structure in which to return link capabilities
++ *
++ * The structure filled in by this function can usually be passed directly
++ * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
++ * configure the link based on the link's capabilities.
++ *
++ * Returns 0 on success or a negative error code on failure.
++ */
++int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
++{
++	u8 values[3];
++	int err;
++
++	memset(link, 0, sizeof(*link));
++
++	err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
++	if (err < 0)
++		return err;
++
++	link->revision = values[0];
++	link->rate = drm_dp_bw_code_to_link_rate(values[1]);
++	link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
++
++	if (values[2] & DP_ENHANCED_FRAME_CAP)
++		link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_dp_link_probe);
++
++/**
++ * drm_dp_link_power_up() - power up a DisplayPort link
++ * @aux: DisplayPort AUX channel
++ * @link: pointer to a structure containing the link configuration
++ *
++ * Returns 0 on success or a negative error code on failure.
++ */
++int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
++{
++	u8 value;
++	int err;
++
++	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
++	if (link->revision < 0x11)
++		return 0;
++
++	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
++	if (err < 0)
++		return err;
++
++	value &= ~DP_SET_POWER_MASK;
++	value |= DP_SET_POWER_D0;
++
++	err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
++	if (err < 0)
++		return err;
++
++	/*
++	 * According to the DP 1.1 specification, a "Sink Device must exit the
++	 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
++	 * Control Field" (register 0x600).
++	 */
++	usleep_range(1000, 2000);
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_dp_link_power_up);
++
++/**
++ * drm_dp_link_configure() - configure a DisplayPort link
++ * @aux: DisplayPort AUX channel
++ * @link: pointer to a structure containing the link configuration
++ *
++ * Returns 0 on success or a negative error code on failure.
++ */
++int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
++{
++	u8 values[2];
++	int err;
++
++	values[0] = drm_dp_link_rate_to_bw_code(link->rate);
++	values[1] = link->num_lanes;
++
++	if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
++		values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
++
++	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_dp_link_configure);
++
++/*
++ * I2C-over-AUX implementation
++ */
++
++static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
++	       I2C_FUNC_SMBUS_READ_BLOCK_DATA |
++	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
++	       I2C_FUNC_10BIT_ADDR;
++}
++
++/*
++ * Transfer a single I2C-over-AUX message and handle various error conditions,
++ * retrying the transaction as appropriate.  It is assumed that the
++ * aux->transfer function does not modify anything in the msg other than the
++ * reply field.
++ */
++static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
++{
++	unsigned int retry;
++	int err;
++
++	/*
++	 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
++	 * is required to retry at least seven times upon receiving AUX_DEFER
++	 * before giving up the AUX transaction.
++	 */
++	for (retry = 0; retry < 7; retry++) {
++		mutex_lock(&aux->hw_mutex);
++		err = aux->transfer(aux, msg);
++		mutex_unlock(&aux->hw_mutex);
++		if (err < 0) {
++			if (err == -EBUSY)
++				continue;
++
++			DRM_DEBUG_KMS("transaction failed: %d\n", err);
++			return err;
++		}
++
++
++		switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
++		case DP_AUX_NATIVE_REPLY_ACK:
++			/*
++			 * For I2C-over-AUX transactions this isn't enough, we
++			 * need to check for the I2C ACK reply.
++			 */
++			break;
++
++		case DP_AUX_NATIVE_REPLY_NACK:
++			DRM_DEBUG_KMS("native nack\n");
++			return -EREMOTEIO;
++
++		case DP_AUX_NATIVE_REPLY_DEFER:
++			DRM_DEBUG_KMS("native defer");
++			/*
++			 * We could check for I2C bit rate capabilities and if
++			 * available adjust this interval. We could also be
++			 * more careful with DP-to-legacy adapters where a
++			 * long legacy cable may force very low I2C bit rates.
++			 *
++			 * For now just defer for long enough to hopefully be
++			 * safe for all use-cases.
++			 */
++			usleep_range(500, 600);
++			continue;
++
++		default:
++			DRM_ERROR("invalid native reply %#04x\n", msg->reply);
++			return -EREMOTEIO;
++		}
++
++		switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
++		case DP_AUX_I2C_REPLY_ACK:
++			/*
++			 * Both native ACK and I2C ACK replies received. We
++			 * can assume the transfer was successful.
++			 */
++			if (err < msg->size)
++				return -EPROTO;
++			return 0;
++
++		case DP_AUX_I2C_REPLY_NACK:
++			DRM_DEBUG_KMS("I2C nack\n");
++			aux->i2c_nack_count++;
++			return -EREMOTEIO;
++
++		case DP_AUX_I2C_REPLY_DEFER:
++			DRM_DEBUG_KMS("I2C defer\n");
++			aux->i2c_defer_count++;
++			usleep_range(400, 500);
++			continue;
++
++		default:
++			DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
++			return -EREMOTEIO;
++		}
++	}
++
++	DRM_DEBUG_KMS("too many retries, giving up\n");
++	return -EREMOTEIO;
++}
++
++static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
++			   int num)
++{
++	struct drm_dp_aux *aux = adapter->algo_data;
++	unsigned int i, j;
++	struct drm_dp_aux_msg msg;
++	int err = 0;
++
++	memset(&msg, 0, sizeof(msg));
++
++	for (i = 0; i < num; i++) {
++		msg.address = msgs[i].addr;
++		msg.request = (msgs[i].flags & I2C_M_RD) ?
++			DP_AUX_I2C_READ :
++			DP_AUX_I2C_WRITE;
++		msg.request |= DP_AUX_I2C_MOT;
++		/* Send a bare address packet to start the transaction.
++		 * Zero sized messages specify an address only (bare
++		 * address) transaction.
++		 */
++		msg.buffer = NULL;
++		msg.size = 0;
++		err = drm_dp_i2c_do_msg(aux, &msg);
++		if (err < 0)
++			break;
++		/*
++		 * Many hardware implementations support FIFOs larger than a
++		 * single byte, but it has been empirically determined that
++		 * transferring data in larger chunks can actually lead to
++		 * decreased performance. Therefore each message is simply
++		 * transferred byte-by-byte.
++		 */
++		for (j = 0; j < msgs[i].len; j++) {
++			msg.buffer = msgs[i].buf + j;
++			msg.size = 1;
++
++			err = drm_dp_i2c_do_msg(aux, &msg);
++			if (err < 0)
++				break;
++		}
++		if (err < 0)
++			break;
++	}
++	if (err >= 0)
++		err = num;
++	/* Send a bare address packet to close out the transaction.
++	 * Zero sized messages specify an address only (bare
++	 * address) transaction.
++	 */
++	msg.request &= ~DP_AUX_I2C_MOT;
++	msg.buffer = NULL;
++	msg.size = 0;
++	(void)drm_dp_i2c_do_msg(aux, &msg);
++
++	return err;
++}
++
++static const struct i2c_algorithm drm_dp_i2c_algo = {
++	.functionality = drm_dp_i2c_functionality,
++	.master_xfer = drm_dp_i2c_xfer,
++};
++
++/**
++ * drm_dp_aux_register() - initialise and register aux channel
++ * @aux: DisplayPort AUX channel
++ *
++ * Returns 0 on success or a negative error code on failure.
++ */
++int drm_dp_aux_register(struct drm_dp_aux *aux)
++{
++	mutex_init(&aux->hw_mutex);
++
++	aux->ddc.algo = &drm_dp_i2c_algo;
++	aux->ddc.algo_data = aux;
++	aux->ddc.retries = 3;
++
++	aux->ddc.class = I2C_CLASS_DDC;
++	aux->ddc.owner = THIS_MODULE;
++	aux->ddc.dev.parent = aux->dev;
++	aux->ddc.dev.of_node = aux->dev->of_node;
++
++	strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
++		sizeof(aux->ddc.name));
++
++	return i2c_add_adapter(&aux->ddc);
++}
++EXPORT_SYMBOL(drm_dp_aux_register);
++
++/**
++ * drm_dp_aux_unregister() - unregister an AUX adapter
++ * @aux: DisplayPort AUX channel
++ */
++void drm_dp_aux_unregister(struct drm_dp_aux *aux)
++{
++	i2c_del_adapter(&aux->ddc);
++}
++EXPORT_SYMBOL(drm_dp_aux_unregister);
+diff -Naur a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
+--- a/drivers/gpu/drm/drm_dp_mst_topology.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_dp_mst_topology.c	2015-03-26 14:42:38.718435422 +0530
+@@ -0,0 +1,2789 @@
++/*
++ * Copyright © 2014 Red Hat
++ *
++ * Permission to use, copy, modify, distribute, and sell this software and its
++ * documentation for any purpose is hereby granted without fee, provided that
++ * the above copyright notice appear in all copies and that both that copyright
++ * notice and this permission notice appear in supporting documentation, and
++ * that the name of the copyright holders not be used in advertising or
++ * publicity pertaining to distribution of the software without specific,
++ * written prior permission.  The copyright holders make no representations
++ * about the suitability of this software for any purpose.  It is provided "as
++ * is" without express or implied warranty.
++ *
++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
++ * OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/sched.h>
++#include <linux/seq_file.h>
++#include <linux/i2c.h>
++#include <drm/drm_dp_mst_helper.h>
++#include <drm/drmP.h>
++
++#include <drm/drm_fixed.h>
++
++/**
++ * DOC: dp mst helper
++ *
++ * These functions contain parts of the DisplayPort 1.2a MultiStream Transport
++ * protocol. The helpers contain a topology manager and bandwidth manager.
++ * The helpers encapsulate the sending and received of sideband msgs.
++ */
++static bool dump_dp_payload_table(struct drm_dp_mst_topology_mgr *mgr,
++				  char *buf);
++static int test_calc_pbn_mode(void);
++
++static void drm_dp_put_port(struct drm_dp_mst_port *port);
++
++static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr,
++				     int id,
++				     struct drm_dp_payload *payload);
++
++static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr,
++				  struct drm_dp_mst_port *port,
++				  int offset, int size, u8 *bytes);
++
++static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr,
++				    struct drm_dp_mst_branch *mstb);
++static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
++					   struct drm_dp_mst_branch *mstb,
++					   struct drm_dp_mst_port *port);
++static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
++				 u8 *guid);
++
++static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux);
++static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux);
++static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr);
++/* sideband msg handling */
++static u8 drm_dp_msg_header_crc4(const uint8_t *data, size_t num_nibbles)
++{
++	u8 bitmask = 0x80;
++	u8 bitshift = 7;
++	u8 array_index = 0;
++	int number_of_bits = num_nibbles * 4;
++	u8 remainder = 0;
++
++	while (number_of_bits != 0) {
++		number_of_bits--;
++		remainder <<= 1;
++		remainder |= (data[array_index] & bitmask) >> bitshift;
++		bitmask >>= 1;
++		bitshift--;
++		if (bitmask == 0) {
++			bitmask = 0x80;
++			bitshift = 7;
++			array_index++;
++		}
++		if ((remainder & 0x10) == 0x10)
++			remainder ^= 0x13;
++	}
++
++	number_of_bits = 4;
++	while (number_of_bits != 0) {
++		number_of_bits--;
++		remainder <<= 1;
++		if ((remainder & 0x10) != 0)
++			remainder ^= 0x13;
++	}
++
++	return remainder;
++}
++
++static u8 drm_dp_msg_data_crc4(const uint8_t *data, u8 number_of_bytes)
++{
++	u8 bitmask = 0x80;
++	u8 bitshift = 7;
++	u8 array_index = 0;
++	int number_of_bits = number_of_bytes * 8;
++	u16 remainder = 0;
++
++	while (number_of_bits != 0) {
++		number_of_bits--;
++		remainder <<= 1;
++		remainder |= (data[array_index] & bitmask) >> bitshift;
++		bitmask >>= 1;
++		bitshift--;
++		if (bitmask == 0) {
++			bitmask = 0x80;
++			bitshift = 7;
++			array_index++;
++		}
++		if ((remainder & 0x100) == 0x100)
++			remainder ^= 0xd5;
++	}
++
++	number_of_bits = 8;
++	while (number_of_bits != 0) {
++		number_of_bits--;
++		remainder <<= 1;
++		if ((remainder & 0x100) != 0)
++			remainder ^= 0xd5;
++	}
++
++	return remainder & 0xff;
++}
++static inline u8 drm_dp_calc_sb_hdr_size(struct drm_dp_sideband_msg_hdr *hdr)
++{
++	u8 size = 3;
++	size += (hdr->lct / 2);
++	return size;
++}
++
++static void drm_dp_encode_sideband_msg_hdr(struct drm_dp_sideband_msg_hdr *hdr,
++					   u8 *buf, int *len)
++{
++	int idx = 0;
++	int i;
++	u8 crc4;
++	buf[idx++] = ((hdr->lct & 0xf) << 4) | (hdr->lcr & 0xf);
++	for (i = 0; i < (hdr->lct / 2); i++)
++		buf[idx++] = hdr->rad[i];
++	buf[idx++] = (hdr->broadcast << 7) | (hdr->path_msg << 6) |
++		(hdr->msg_len & 0x3f);
++	buf[idx++] = (hdr->somt << 7) | (hdr->eomt << 6) | (hdr->seqno << 4);
++
++	crc4 = drm_dp_msg_header_crc4(buf, (idx * 2) - 1);
++	buf[idx - 1] |= (crc4 & 0xf);
++
++	*len = idx;
++}
++
++static bool drm_dp_decode_sideband_msg_hdr(struct drm_dp_sideband_msg_hdr *hdr,
++					   u8 *buf, int buflen, u8 *hdrlen)
++{
++	u8 crc4;
++	u8 len;
++	int i;
++	u8 idx;
++	if (buf[0] == 0)
++		return false;
++	len = 3;
++	len += ((buf[0] & 0xf0) >> 4) / 2;
++	if (len > buflen)
++		return false;
++	crc4 = drm_dp_msg_header_crc4(buf, (len * 2) - 1);
++
++	if ((crc4 & 0xf) != (buf[len - 1] & 0xf)) {
++		DRM_DEBUG_KMS("crc4 mismatch 0x%x 0x%x\n", crc4, buf[len - 1]);
++		return false;
++	}
++
++	hdr->lct = (buf[0] & 0xf0) >> 4;
++	hdr->lcr = (buf[0] & 0xf);
++	idx = 1;
++	for (i = 0; i < (hdr->lct / 2); i++)
++		hdr->rad[i] = buf[idx++];
++	hdr->broadcast = (buf[idx] >> 7) & 0x1;
++	hdr->path_msg = (buf[idx] >> 6) & 0x1;
++	hdr->msg_len = buf[idx] & 0x3f;
++	idx++;
++	hdr->somt = (buf[idx] >> 7) & 0x1;
++	hdr->eomt = (buf[idx] >> 6) & 0x1;
++	hdr->seqno = (buf[idx] >> 4) & 0x1;
++	idx++;
++	*hdrlen = idx;
++	return true;
++}
++
++static void drm_dp_encode_sideband_req(struct drm_dp_sideband_msg_req_body *req,
++				       struct drm_dp_sideband_msg_tx *raw)
++{
++	int idx = 0;
++	int i;
++	u8 *buf = raw->msg;
++	buf[idx++] = req->req_type & 0x7f;
++
++	switch (req->req_type) {
++	case DP_ENUM_PATH_RESOURCES:
++		buf[idx] = (req->u.port_num.port_number & 0xf) << 4;
++		idx++;
++		break;
++	case DP_ALLOCATE_PAYLOAD:
++		buf[idx] = (req->u.allocate_payload.port_number & 0xf) << 4 |
++			(req->u.allocate_payload.number_sdp_streams & 0xf);
++		idx++;
++		buf[idx] = (req->u.allocate_payload.vcpi & 0x7f);
++		idx++;
++		buf[idx] = (req->u.allocate_payload.pbn >> 8);
++		idx++;
++		buf[idx] = (req->u.allocate_payload.pbn & 0xff);
++		idx++;
++		for (i = 0; i < req->u.allocate_payload.number_sdp_streams / 2; i++) {
++			buf[idx] = ((req->u.allocate_payload.sdp_stream_sink[i * 2] & 0xf) << 4) |
++				(req->u.allocate_payload.sdp_stream_sink[i * 2 + 1] & 0xf);
++			idx++;
++		}
++		if (req->u.allocate_payload.number_sdp_streams & 1) {
++			i = req->u.allocate_payload.number_sdp_streams - 1;
++			buf[idx] = (req->u.allocate_payload.sdp_stream_sink[i] & 0xf) << 4;
++			idx++;
++		}
++		break;
++	case DP_QUERY_PAYLOAD:
++		buf[idx] = (req->u.query_payload.port_number & 0xf) << 4;
++		idx++;
++		buf[idx] = (req->u.query_payload.vcpi & 0x7f);
++		idx++;
++		break;
++	case DP_REMOTE_DPCD_READ:
++		buf[idx] = (req->u.dpcd_read.port_number & 0xf) << 4;
++		buf[idx] |= ((req->u.dpcd_read.dpcd_address & 0xf0000) >> 16) & 0xf;
++		idx++;
++		buf[idx] = (req->u.dpcd_read.dpcd_address & 0xff00) >> 8;
++		idx++;
++		buf[idx] = (req->u.dpcd_read.dpcd_address & 0xff);
++		idx++;
++		buf[idx] = (req->u.dpcd_read.num_bytes);
++		idx++;
++		break;
++
++	case DP_REMOTE_DPCD_WRITE:
++		buf[idx] = (req->u.dpcd_write.port_number & 0xf) << 4;
++		buf[idx] |= ((req->u.dpcd_write.dpcd_address & 0xf0000) >> 16) & 0xf;
++		idx++;
++		buf[idx] = (req->u.dpcd_write.dpcd_address & 0xff00) >> 8;
++		idx++;
++		buf[idx] = (req->u.dpcd_write.dpcd_address & 0xff);
++		idx++;
++		buf[idx] = (req->u.dpcd_write.num_bytes);
++		idx++;
++		memcpy(&buf[idx], req->u.dpcd_write.bytes, req->u.dpcd_write.num_bytes);
++		idx += req->u.dpcd_write.num_bytes;
++		break;
++	case DP_REMOTE_I2C_READ:
++		buf[idx] = (req->u.i2c_read.port_number & 0xf) << 4;
++		buf[idx] |= (req->u.i2c_read.num_transactions & 0x3);
++		idx++;
++		for (i = 0; i < (req->u.i2c_read.num_transactions & 0x3); i++) {
++			buf[idx] = req->u.i2c_read.transactions[i].i2c_dev_id & 0x7f;
++			idx++;
++			buf[idx] = req->u.i2c_read.transactions[i].num_bytes;
++			idx++;
++			memcpy(&buf[idx], req->u.i2c_read.transactions[i].bytes, req->u.i2c_read.transactions[i].num_bytes);
++			idx += req->u.i2c_read.transactions[i].num_bytes;
++
++			buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 5;
++			buf[idx] |= (req->u.i2c_read.transactions[i].i2c_transaction_delay & 0xf);
++			idx++;
++		}
++		buf[idx] = (req->u.i2c_read.read_i2c_device_id) & 0x7f;
++		idx++;
++		buf[idx] = (req->u.i2c_read.num_bytes_read);
++		idx++;
++		break;
++
++	case DP_REMOTE_I2C_WRITE:
++		buf[idx] = (req->u.i2c_write.port_number & 0xf) << 4;
++		idx++;
++		buf[idx] = (req->u.i2c_write.write_i2c_device_id) & 0x7f;
++		idx++;
++		buf[idx] = (req->u.i2c_write.num_bytes);
++		idx++;
++		memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes);
++		idx += req->u.i2c_write.num_bytes;
++		break;
++	}
++	raw->cur_len = idx;
++}
++
++static void drm_dp_crc_sideband_chunk_req(u8 *msg, u8 len)
++{
++	u8 crc4;
++	crc4 = drm_dp_msg_data_crc4(msg, len);
++	msg[len] = crc4;
++}
++
++static void drm_dp_encode_sideband_reply(struct drm_dp_sideband_msg_reply_body *rep,
++					 struct drm_dp_sideband_msg_tx *raw)
++{
++	int idx = 0;
++	u8 *buf = raw->msg;
++
++	buf[idx++] = (rep->reply_type & 0x1) << 7 | (rep->req_type & 0x7f);
++
++	raw->cur_len = idx;
++}
++
++/* this adds a chunk of msg to the builder to get the final msg */
++static bool drm_dp_sideband_msg_build(struct drm_dp_sideband_msg_rx *msg,
++				      u8 *replybuf, u8 replybuflen, bool hdr)
++{
++	int ret;
++	u8 crc4;
++
++	if (hdr) {
++		u8 hdrlen;
++		struct drm_dp_sideband_msg_hdr recv_hdr;
++		ret = drm_dp_decode_sideband_msg_hdr(&recv_hdr, replybuf, replybuflen, &hdrlen);
++		if (ret == false) {
++			print_hex_dump(KERN_DEBUG, "failed hdr", DUMP_PREFIX_NONE, 16, 1, replybuf, replybuflen, false);
++			return false;
++		}
++
++		/* get length contained in this portion */
++		msg->curchunk_len = recv_hdr.msg_len;
++		msg->curchunk_hdrlen = hdrlen;
++
++		/* we have already gotten an somt - don't bother parsing */
++		if (recv_hdr.somt && msg->have_somt)
++			return false;
++
++		if (recv_hdr.somt) {
++			memcpy(&msg->initial_hdr, &recv_hdr, sizeof(struct drm_dp_sideband_msg_hdr));
++			msg->have_somt = true;
++		}
++		if (recv_hdr.eomt)
++			msg->have_eomt = true;
++
++		/* copy the bytes for the remainder of this header chunk */
++		msg->curchunk_idx = min(msg->curchunk_len, (u8)(replybuflen - hdrlen));
++		memcpy(&msg->chunk[0], replybuf + hdrlen, msg->curchunk_idx);
++	} else {
++		memcpy(&msg->chunk[msg->curchunk_idx], replybuf, replybuflen);
++		msg->curchunk_idx += replybuflen;
++	}
++
++	if (msg->curchunk_idx >= msg->curchunk_len) {
++		/* do CRC */
++		crc4 = drm_dp_msg_data_crc4(msg->chunk, msg->curchunk_len - 1);
++		/* copy chunk into bigger msg */
++		memcpy(&msg->msg[msg->curlen], msg->chunk, msg->curchunk_len - 1);
++		msg->curlen += msg->curchunk_len - 1;
++	}
++	return true;
++}
++
++static bool drm_dp_sideband_parse_link_address(struct drm_dp_sideband_msg_rx *raw,
++					       struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++	int i;
++	memcpy(repmsg->u.link_addr.guid, &raw->msg[idx], 16);
++	idx += 16;
++	repmsg->u.link_addr.nports = raw->msg[idx] & 0xf;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	for (i = 0; i < repmsg->u.link_addr.nports; i++) {
++		if (raw->msg[idx] & 0x80)
++			repmsg->u.link_addr.ports[i].input_port = 1;
++
++		repmsg->u.link_addr.ports[i].peer_device_type = (raw->msg[idx] >> 4) & 0x7;
++		repmsg->u.link_addr.ports[i].port_number = (raw->msg[idx] & 0xf);
++
++		idx++;
++		if (idx > raw->curlen)
++			goto fail_len;
++		repmsg->u.link_addr.ports[i].mcs = (raw->msg[idx] >> 7) & 0x1;
++		repmsg->u.link_addr.ports[i].ddps = (raw->msg[idx] >> 6) & 0x1;
++		if (repmsg->u.link_addr.ports[i].input_port == 0)
++			repmsg->u.link_addr.ports[i].legacy_device_plug_status = (raw->msg[idx] >> 5) & 0x1;
++		idx++;
++		if (idx > raw->curlen)
++			goto fail_len;
++		if (repmsg->u.link_addr.ports[i].input_port == 0) {
++			repmsg->u.link_addr.ports[i].dpcd_revision = (raw->msg[idx]);
++			idx++;
++			if (idx > raw->curlen)
++				goto fail_len;
++			memcpy(repmsg->u.link_addr.ports[i].peer_guid, &raw->msg[idx], 16);
++			idx += 16;
++			if (idx > raw->curlen)
++				goto fail_len;
++			repmsg->u.link_addr.ports[i].num_sdp_streams = (raw->msg[idx] >> 4) & 0xf;
++			repmsg->u.link_addr.ports[i].num_sdp_stream_sinks = (raw->msg[idx] & 0xf);
++			idx++;
++
++		}
++		if (idx > raw->curlen)
++			goto fail_len;
++	}
++
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("link address reply parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_remote_dpcd_read(struct drm_dp_sideband_msg_rx *raw,
++						   struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++	repmsg->u.remote_dpcd_read_ack.port_number = raw->msg[idx] & 0xf;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.remote_dpcd_read_ack.num_bytes = raw->msg[idx];
++	if (idx > raw->curlen)
++		goto fail_len;
++
++	memcpy(repmsg->u.remote_dpcd_read_ack.bytes, &raw->msg[idx], repmsg->u.remote_dpcd_read_ack.num_bytes);
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("link address reply parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_remote_dpcd_write(struct drm_dp_sideband_msg_rx *raw,
++						      struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++	repmsg->u.remote_dpcd_write_ack.port_number = raw->msg[idx] & 0xf;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_remote_i2c_read_ack(struct drm_dp_sideband_msg_rx *raw,
++						      struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++
++	repmsg->u.remote_i2c_read_ack.port_number = (raw->msg[idx] & 0xf);
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.remote_i2c_read_ack.num_bytes = raw->msg[idx];
++	idx++;
++	/* TODO check */
++	memcpy(repmsg->u.remote_i2c_read_ack.bytes, &raw->msg[idx], repmsg->u.remote_i2c_read_ack.num_bytes);
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("remote i2c reply parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband_msg_rx *raw,
++							  struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++	repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.path_resources.full_payload_bw_number = (raw->msg[idx] << 8) | (raw->msg[idx+1]);
++	idx += 2;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.path_resources.avail_payload_bw_number = (raw->msg[idx] << 8) | (raw->msg[idx+1]);
++	idx += 2;
++	if (idx > raw->curlen)
++		goto fail_len;
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("enum resource parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_allocate_payload_ack(struct drm_dp_sideband_msg_rx *raw,
++							  struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++	repmsg->u.allocate_payload.port_number = (raw->msg[idx] >> 4) & 0xf;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.allocate_payload.vcpi = raw->msg[idx];
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.allocate_payload.allocated_pbn = (raw->msg[idx] << 8) | (raw->msg[idx+1]);
++	idx += 2;
++	if (idx > raw->curlen)
++		goto fail_len;
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("allocate payload parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_query_payload_ack(struct drm_dp_sideband_msg_rx *raw,
++						    struct drm_dp_sideband_msg_reply_body *repmsg)
++{
++	int idx = 1;
++	repmsg->u.query_payload.port_number = (raw->msg[idx] >> 4) & 0xf;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++	repmsg->u.query_payload.allocated_pbn = (raw->msg[idx] << 8) | (raw->msg[idx + 1]);
++	idx += 2;
++	if (idx > raw->curlen)
++		goto fail_len;
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("query payload parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
++					struct drm_dp_sideband_msg_reply_body *msg)
++{
++	memset(msg, 0, sizeof(*msg));
++	msg->reply_type = (raw->msg[0] & 0x80) >> 7;
++	msg->req_type = (raw->msg[0] & 0x7f);
++
++	if (msg->reply_type) {
++		memcpy(msg->u.nak.guid, &raw->msg[1], 16);
++		msg->u.nak.reason = raw->msg[17];
++		msg->u.nak.nak_data = raw->msg[18];
++		return false;
++	}
++
++	switch (msg->req_type) {
++	case DP_LINK_ADDRESS:
++		return drm_dp_sideband_parse_link_address(raw, msg);
++	case DP_QUERY_PAYLOAD:
++		return drm_dp_sideband_parse_query_payload_ack(raw, msg);
++	case DP_REMOTE_DPCD_READ:
++		return drm_dp_sideband_parse_remote_dpcd_read(raw, msg);
++	case DP_REMOTE_DPCD_WRITE:
++		return drm_dp_sideband_parse_remote_dpcd_write(raw, msg);
++	case DP_REMOTE_I2C_READ:
++		return drm_dp_sideband_parse_remote_i2c_read_ack(raw, msg);
++	case DP_ENUM_PATH_RESOURCES:
++		return drm_dp_sideband_parse_enum_path_resources_ack(raw, msg);
++	case DP_ALLOCATE_PAYLOAD:
++		return drm_dp_sideband_parse_allocate_payload_ack(raw, msg);
++	default:
++		DRM_ERROR("Got unknown reply 0x%02x\n", msg->req_type);
++		return false;
++	}
++}
++
++static bool drm_dp_sideband_parse_connection_status_notify(struct drm_dp_sideband_msg_rx *raw,
++							   struct drm_dp_sideband_msg_req_body *msg)
++{
++	int idx = 1;
++
++	msg->u.conn_stat.port_number = (raw->msg[idx] & 0xf0) >> 4;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++
++	memcpy(msg->u.conn_stat.guid, &raw->msg[idx], 16);
++	idx += 16;
++	if (idx > raw->curlen)
++		goto fail_len;
++
++	msg->u.conn_stat.legacy_device_plug_status = (raw->msg[idx] >> 6) & 0x1;
++	msg->u.conn_stat.displayport_device_plug_status = (raw->msg[idx] >> 5) & 0x1;
++	msg->u.conn_stat.message_capability_status = (raw->msg[idx] >> 4) & 0x1;
++	msg->u.conn_stat.input_port = (raw->msg[idx] >> 3) & 0x1;
++	msg->u.conn_stat.peer_device_type = (raw->msg[idx] & 0x7);
++	idx++;
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("connection status reply parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_resource_status_notify(struct drm_dp_sideband_msg_rx *raw,
++							   struct drm_dp_sideband_msg_req_body *msg)
++{
++	int idx = 1;
++
++	msg->u.resource_stat.port_number = (raw->msg[idx] & 0xf0) >> 4;
++	idx++;
++	if (idx > raw->curlen)
++		goto fail_len;
++
++	memcpy(msg->u.resource_stat.guid, &raw->msg[idx], 16);
++	idx += 16;
++	if (idx > raw->curlen)
++		goto fail_len;
++
++	msg->u.resource_stat.available_pbn = (raw->msg[idx] << 8) | (raw->msg[idx + 1]);
++	idx++;
++	return true;
++fail_len:
++	DRM_DEBUG_KMS("resource status reply parse length fail %d %d\n", idx, raw->curlen);
++	return false;
++}
++
++static bool drm_dp_sideband_parse_req(struct drm_dp_sideband_msg_rx *raw,
++				      struct drm_dp_sideband_msg_req_body *msg)
++{
++	memset(msg, 0, sizeof(*msg));
++	msg->req_type = (raw->msg[0] & 0x7f);
++
++	switch (msg->req_type) {
++	case DP_CONNECTION_STATUS_NOTIFY:
++		return drm_dp_sideband_parse_connection_status_notify(raw, msg);
++	case DP_RESOURCE_STATUS_NOTIFY:
++		return drm_dp_sideband_parse_resource_status_notify(raw, msg);
++	default:
++		DRM_ERROR("Got unknown request 0x%02x\n", msg->req_type);
++		return false;
++	}
++}
++
++static int build_dpcd_write(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes, u8 *bytes)
++{
++	struct drm_dp_sideband_msg_req_body req;
++
++	req.req_type = DP_REMOTE_DPCD_WRITE;
++	req.u.dpcd_write.port_number = port_num;
++	req.u.dpcd_write.dpcd_address = offset;
++	req.u.dpcd_write.num_bytes = num_bytes;
++	req.u.dpcd_write.bytes = bytes;
++	drm_dp_encode_sideband_req(&req, msg);
++
++	return 0;
++}
++
++static int build_link_address(struct drm_dp_sideband_msg_tx *msg)
++{
++	struct drm_dp_sideband_msg_req_body req;
++
++	req.req_type = DP_LINK_ADDRESS;
++	drm_dp_encode_sideband_req(&req, msg);
++	return 0;
++}
++
++static int build_enum_path_resources(struct drm_dp_sideband_msg_tx *msg, int port_num)
++{
++	struct drm_dp_sideband_msg_req_body req;
++
++	req.req_type = DP_ENUM_PATH_RESOURCES;
++	req.u.port_num.port_number = port_num;
++	drm_dp_encode_sideband_req(&req, msg);
++	msg->path_msg = true;
++	return 0;
++}
++
++static int build_allocate_payload(struct drm_dp_sideband_msg_tx *msg, int port_num,
++				  u8 vcpi, uint16_t pbn)
++{
++	struct drm_dp_sideband_msg_req_body req;
++	memset(&req, 0, sizeof(req));
++	req.req_type = DP_ALLOCATE_PAYLOAD;
++	req.u.allocate_payload.port_number = port_num;
++	req.u.allocate_payload.vcpi = vcpi;
++	req.u.allocate_payload.pbn = pbn;
++	drm_dp_encode_sideband_req(&req, msg);
++	msg->path_msg = true;
++	return 0;
++}
++
++static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr,
++					struct drm_dp_vcpi *vcpi)
++{
++	int ret, vcpi_ret;
++
++	mutex_lock(&mgr->payload_lock);
++	ret = find_first_zero_bit(&mgr->payload_mask, mgr->max_payloads + 1);
++	if (ret > mgr->max_payloads) {
++		ret = -EINVAL;
++		DRM_DEBUG_KMS("out of payload ids %d\n", ret);
++		goto out_unlock;
++	}
++
++	vcpi_ret = find_first_zero_bit(&mgr->vcpi_mask, mgr->max_payloads + 1);
++	if (vcpi_ret > mgr->max_payloads) {
++		ret = -EINVAL;
++		DRM_DEBUG_KMS("out of vcpi ids %d\n", ret);
++		goto out_unlock;
++	}
++
++	set_bit(ret, &mgr->payload_mask);
++	set_bit(vcpi_ret, &mgr->vcpi_mask);
++	vcpi->vcpi = vcpi_ret + 1;
++	mgr->proposed_vcpis[ret - 1] = vcpi;
++out_unlock:
++	mutex_unlock(&mgr->payload_lock);
++	return ret;
++}
++
++static void drm_dp_mst_put_payload_id(struct drm_dp_mst_topology_mgr *mgr,
++				      int vcpi)
++{
++	int i;
++	if (vcpi == 0)
++		return;
++
++	mutex_lock(&mgr->payload_lock);
++	DRM_DEBUG_KMS("putting payload %d\n", vcpi);
++	clear_bit(vcpi - 1, &mgr->vcpi_mask);
++
++	for (i = 0; i < mgr->max_payloads; i++) {
++		if (mgr->proposed_vcpis[i])
++			if (mgr->proposed_vcpis[i]->vcpi == vcpi) {
++				mgr->proposed_vcpis[i] = NULL;
++				clear_bit(i + 1, &mgr->payload_mask);
++			}
++	}
++	mutex_unlock(&mgr->payload_lock);
++}
++
++static bool check_txmsg_state(struct drm_dp_mst_topology_mgr *mgr,
++			      struct drm_dp_sideband_msg_tx *txmsg)
++{
++	bool ret;
++	mutex_lock(&mgr->qlock);
++	ret = (txmsg->state == DRM_DP_SIDEBAND_TX_RX ||
++	       txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT);
++	mutex_unlock(&mgr->qlock);
++	return ret;
++}
++
++static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb,
++				    struct drm_dp_sideband_msg_tx *txmsg)
++{
++	struct drm_dp_mst_topology_mgr *mgr = mstb->mgr;
++	int ret;
++
++	ret = wait_event_timeout(mgr->tx_waitq,
++				 check_txmsg_state(mgr, txmsg),
++				 (4 * HZ));
++	mutex_lock(&mstb->mgr->qlock);
++	if (ret > 0) {
++		if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) {
++			ret = -EIO;
++			goto out;
++		}
++	} else {
++		DRM_DEBUG_KMS("timedout msg send %p %d %d\n", txmsg, txmsg->state, txmsg->seqno);
++
++		/* dump some state */
++		ret = -EIO;
++
++		/* remove from q */
++		if (txmsg->state == DRM_DP_SIDEBAND_TX_QUEUED ||
++		    txmsg->state == DRM_DP_SIDEBAND_TX_START_SEND) {
++			list_del(&txmsg->next);
++		}
++
++		if (txmsg->state == DRM_DP_SIDEBAND_TX_START_SEND ||
++		    txmsg->state == DRM_DP_SIDEBAND_TX_SENT) {
++			mstb->tx_slots[txmsg->seqno] = NULL;
++		}
++	}
++out:
++	mutex_unlock(&mgr->qlock);
++
++	return ret;
++}
++
++static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad)
++{
++	struct drm_dp_mst_branch *mstb;
++
++	mstb = kzalloc(sizeof(*mstb), GFP_KERNEL);
++	if (!mstb)
++		return NULL;
++
++	mstb->lct = lct;
++	if (lct > 1)
++		memcpy(mstb->rad, rad, lct / 2);
++	INIT_LIST_HEAD(&mstb->ports);
++	kref_init(&mstb->kref);
++	return mstb;
++}
++
++static void drm_dp_destroy_mst_branch_device(struct kref *kref)
++{
++	struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref);
++	struct drm_dp_mst_port *port, *tmp;
++	bool wake_tx = false;
++
++	cancel_work_sync(&mstb->mgr->work);
++
++	/*
++	 * destroy all ports - don't need lock
++	 * as there are no more references to the mst branch
++	 * device at this point.
++	 */
++	list_for_each_entry_safe(port, tmp, &mstb->ports, next) {
++		list_del(&port->next);
++		drm_dp_put_port(port);
++	}
++
++	/* drop any tx slots msg */
++	mutex_lock(&mstb->mgr->qlock);
++	if (mstb->tx_slots[0]) {
++		mstb->tx_slots[0]->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
++		mstb->tx_slots[0] = NULL;
++		wake_tx = true;
++	}
++	if (mstb->tx_slots[1]) {
++		mstb->tx_slots[1]->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
++		mstb->tx_slots[1] = NULL;
++		wake_tx = true;
++	}
++	mutex_unlock(&mstb->mgr->qlock);
++
++	if (wake_tx)
++		wake_up(&mstb->mgr->tx_waitq);
++	kfree(mstb);
++}
++
++static void drm_dp_put_mst_branch_device(struct drm_dp_mst_branch *mstb)
++{
++	kref_put(&mstb->kref, drm_dp_destroy_mst_branch_device);
++}
++
++
++static void drm_dp_port_teardown_pdt(struct drm_dp_mst_port *port, int old_pdt)
++{
++	struct drm_dp_mst_branch *mstb;
++
++	switch (old_pdt) {
++	case DP_PEER_DEVICE_DP_LEGACY_CONV:
++	case DP_PEER_DEVICE_SST_SINK:
++		/* remove i2c over sideband */
++		drm_dp_mst_unregister_i2c_bus(&port->aux);
++		break;
++	case DP_PEER_DEVICE_MST_BRANCHING:
++		mstb = port->mstb;
++		port->mstb = NULL;
++		drm_dp_put_mst_branch_device(mstb);
++		break;
++	}
++}
++
++static void drm_dp_destroy_port(struct kref *kref)
++{
++	struct drm_dp_mst_port *port = container_of(kref, struct drm_dp_mst_port, kref);
++	struct drm_dp_mst_topology_mgr *mgr = port->mgr;
++	if (!port->input) {
++		port->vcpi.num_slots = 0;
++
++		kfree(port->cached_edid);
++		if (port->connector)
++			(*port->mgr->cbs->destroy_connector)(mgr, port->connector);
++		drm_dp_port_teardown_pdt(port, port->pdt);
++
++		if (!port->input && port->vcpi.vcpi > 0)
++			drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
++	}
++	kfree(port);
++
++	(*mgr->cbs->hotplug)(mgr);
++}
++
++static void drm_dp_put_port(struct drm_dp_mst_port *port)
++{
++	kref_put(&port->kref, drm_dp_destroy_port);
++}
++
++static struct drm_dp_mst_branch *drm_dp_mst_get_validated_mstb_ref_locked(struct drm_dp_mst_branch *mstb, struct drm_dp_mst_branch *to_find)
++{
++	struct drm_dp_mst_port *port;
++	struct drm_dp_mst_branch *rmstb;
++	if (to_find == mstb) {
++		kref_get(&mstb->kref);
++		return mstb;
++	}
++	list_for_each_entry(port, &mstb->ports, next) {
++		if (port->mstb) {
++			rmstb = drm_dp_mst_get_validated_mstb_ref_locked(port->mstb, to_find);
++			if (rmstb)
++				return rmstb;
++		}
++	}
++	return NULL;
++}
++
++static struct drm_dp_mst_branch *drm_dp_get_validated_mstb_ref(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_branch *mstb)
++{
++	struct drm_dp_mst_branch *rmstb = NULL;
++	mutex_lock(&mgr->lock);
++	if (mgr->mst_primary)
++		rmstb = drm_dp_mst_get_validated_mstb_ref_locked(mgr->mst_primary, mstb);
++	mutex_unlock(&mgr->lock);
++	return rmstb;
++}
++
++static struct drm_dp_mst_port *drm_dp_mst_get_port_ref_locked(struct drm_dp_mst_branch *mstb, struct drm_dp_mst_port *to_find)
++{
++	struct drm_dp_mst_port *port, *mport;
++
++	list_for_each_entry(port, &mstb->ports, next) {
++		if (port == to_find) {
++			kref_get(&port->kref);
++			return port;
++		}
++		if (port->mstb) {
++			mport = drm_dp_mst_get_port_ref_locked(port->mstb, to_find);
++			if (mport)
++				return mport;
++		}
++	}
++	return NULL;
++}
++
++static struct drm_dp_mst_port *drm_dp_get_validated_port_ref(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port)
++{
++	struct drm_dp_mst_port *rport = NULL;
++	mutex_lock(&mgr->lock);
++	if (mgr->mst_primary)
++		rport = drm_dp_mst_get_port_ref_locked(mgr->mst_primary, port);
++	mutex_unlock(&mgr->lock);
++	return rport;
++}
++
++static struct drm_dp_mst_port *drm_dp_get_port(struct drm_dp_mst_branch *mstb, u8 port_num)
++{
++	struct drm_dp_mst_port *port;
++
++	list_for_each_entry(port, &mstb->ports, next) {
++		if (port->port_num == port_num) {
++			kref_get(&port->kref);
++			return port;
++		}
++	}
++
++	return NULL;
++}
++
++/*
++ * calculate a new RAD for this MST branch device
++ * if parent has an LCT of 2 then it has 1 nibble of RAD,
++ * if parent has an LCT of 3 then it has 2 nibbles of RAD,
++ */
++static u8 drm_dp_calculate_rad(struct drm_dp_mst_port *port,
++				 u8 *rad)
++{
++	int lct = port->parent->lct;
++	int shift = 4;
++	int idx = lct / 2;
++	if (lct > 1) {
++		memcpy(rad, port->parent->rad, idx);
++		shift = (lct % 2) ? 4 : 0;
++	} else
++		rad[0] = 0;
++
++	rad[idx] |= port->port_num << shift;
++	return lct + 1;
++}
++
++/*
++ * return sends link address for new mstb
++ */
++static bool drm_dp_port_setup_pdt(struct drm_dp_mst_port *port)
++{
++	int ret;
++	u8 rad[6], lct;
++	bool send_link = false;
++	switch (port->pdt) {
++	case DP_PEER_DEVICE_DP_LEGACY_CONV:
++	case DP_PEER_DEVICE_SST_SINK:
++		/* add i2c over sideband */
++		ret = drm_dp_mst_register_i2c_bus(&port->aux);
++		break;
++	case DP_PEER_DEVICE_MST_BRANCHING:
++		lct = drm_dp_calculate_rad(port, rad);
++
++		port->mstb = drm_dp_add_mst_branch_device(lct, rad);
++		port->mstb->mgr = port->mgr;
++		port->mstb->port_parent = port;
++
++		send_link = true;
++		break;
++	}
++	return send_link;
++}
++
++static void drm_dp_check_port_guid(struct drm_dp_mst_branch *mstb,
++				   struct drm_dp_mst_port *port)
++{
++	int ret;
++	if (port->dpcd_rev >= 0x12) {
++		port->guid_valid = drm_dp_validate_guid(mstb->mgr, port->guid);
++		if (!port->guid_valid) {
++			ret = drm_dp_send_dpcd_write(mstb->mgr,
++						     port,
++						     DP_GUID,
++						     16, port->guid);
++			port->guid_valid = true;
++		}
++	}
++}
++
++static void build_mst_prop_path(struct drm_dp_mst_port *port,
++				struct drm_dp_mst_branch *mstb,
++				char *proppath,
++				size_t proppath_size)
++{
++	int i;
++	char temp[8];
++	snprintf(proppath, proppath_size, "mst:%d", mstb->mgr->conn_base_id);
++	for (i = 0; i < (mstb->lct - 1); i++) {
++		int shift = (i % 2) ? 0 : 4;
++		int port_num = mstb->rad[i / 2] >> shift;
++		snprintf(temp, sizeof(temp), "-%d", port_num);
++		strlcat(proppath, temp, proppath_size);
++	}
++	snprintf(temp, sizeof(temp), "-%d", port->port_num);
++	strlcat(proppath, temp, proppath_size);
++}
++
++static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
++			    struct device *dev,
++			    struct drm_dp_link_addr_reply_port *port_msg)
++{
++	struct drm_dp_mst_port *port;
++	bool ret;
++	bool created = false;
++	int old_pdt = 0;
++	int old_ddps = 0;
++	port = drm_dp_get_port(mstb, port_msg->port_number);
++	if (!port) {
++		port = kzalloc(sizeof(*port), GFP_KERNEL);
++		if (!port)
++			return;
++		kref_init(&port->kref);
++		port->parent = mstb;
++		port->port_num = port_msg->port_number;
++		port->mgr = mstb->mgr;
++		port->aux.name = "DPMST";
++		port->aux.dev = dev;
++		created = true;
++	} else {
++		old_pdt = port->pdt;
++		old_ddps = port->ddps;
++	}
++
++	port->pdt = port_msg->peer_device_type;
++	port->input = port_msg->input_port;
++	port->mcs = port_msg->mcs;
++	port->ddps = port_msg->ddps;
++	port->ldps = port_msg->legacy_device_plug_status;
++	port->dpcd_rev = port_msg->dpcd_revision;
++	port->num_sdp_streams = port_msg->num_sdp_streams;
++	port->num_sdp_stream_sinks = port_msg->num_sdp_stream_sinks;
++	memcpy(port->guid, port_msg->peer_guid, 16);
++
++	/* manage mstb port lists with mgr lock - take a reference
++	   for this list */
++	if (created) {
++		mutex_lock(&mstb->mgr->lock);
++		kref_get(&port->kref);
++		list_add(&port->next, &mstb->ports);
++		mutex_unlock(&mstb->mgr->lock);
++	}
++
++	if (old_ddps != port->ddps) {
++		if (port->ddps) {
++			drm_dp_check_port_guid(mstb, port);
++			if (!port->input)
++				drm_dp_send_enum_path_resources(mstb->mgr, mstb, port);
++		} else {
++			port->guid_valid = false;
++			port->available_pbn = 0;
++			}
++	}
++
++	if (old_pdt != port->pdt && !port->input) {
++		drm_dp_port_teardown_pdt(port, old_pdt);
++
++		ret = drm_dp_port_setup_pdt(port);
++		if (ret == true) {
++			drm_dp_send_link_address(mstb->mgr, port->mstb);
++			port->mstb->link_address_sent = true;
++		}
++	}
++
++	if (created && !port->input) {
++		char proppath[255];
++		build_mst_prop_path(port, mstb, proppath, sizeof(proppath));
++		port->connector = (*mstb->mgr->cbs->add_connector)(mstb->mgr, port, proppath);
++
++		if (port->port_num >= 8) {
++			port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc);
++		}
++	}
++
++	/* put reference to this port */
++	drm_dp_put_port(port);
++}
++
++static void drm_dp_update_port(struct drm_dp_mst_branch *mstb,
++			       struct drm_dp_connection_status_notify *conn_stat)
++{
++	struct drm_dp_mst_port *port;
++	int old_pdt;
++	int old_ddps;
++	bool dowork = false;
++	port = drm_dp_get_port(mstb, conn_stat->port_number);
++	if (!port)
++		return;
++
++	old_ddps = port->ddps;
++	old_pdt = port->pdt;
++	port->pdt = conn_stat->peer_device_type;
++	port->mcs = conn_stat->message_capability_status;
++	port->ldps = conn_stat->legacy_device_plug_status;
++	port->ddps = conn_stat->displayport_device_plug_status;
++
++	if (old_ddps != port->ddps) {
++		if (port->ddps) {
++			drm_dp_check_port_guid(mstb, port);
++			dowork = true;
++		} else {
++			port->guid_valid = false;
++			port->available_pbn = 0;
++		}
++	}
++	if (old_pdt != port->pdt && !port->input) {
++		drm_dp_port_teardown_pdt(port, old_pdt);
++
++		if (drm_dp_port_setup_pdt(port))
++			dowork = true;
++	}
++
++	drm_dp_put_port(port);
++	if (dowork)
++		queue_work(system_long_wq, &mstb->mgr->work);
++
++}
++
++static struct drm_dp_mst_branch *drm_dp_get_mst_branch_device(struct drm_dp_mst_topology_mgr *mgr,
++							       u8 lct, u8 *rad)
++{
++	struct drm_dp_mst_branch *mstb;
++	struct drm_dp_mst_port *port;
++	int i;
++	/* find the port by iterating down */
++	mstb = mgr->mst_primary;
++
++	for (i = 0; i < lct - 1; i++) {
++		int shift = (i % 2) ? 0 : 4;
++		int port_num = rad[i / 2] >> shift;
++
++		list_for_each_entry(port, &mstb->ports, next) {
++			if (port->port_num == port_num) {
++				if (!port->mstb) {
++					DRM_ERROR("failed to lookup MSTB with lct %d, rad %02x\n", lct, rad[0]);
++					return NULL;
++				}
++
++				mstb = port->mstb;
++				break;
++			}
++		}
++	}
++	kref_get(&mstb->kref);
++	return mstb;
++}
++
++static void drm_dp_check_and_send_link_address(struct drm_dp_mst_topology_mgr *mgr,
++					       struct drm_dp_mst_branch *mstb)
++{
++	struct drm_dp_mst_port *port;
++
++	if (!mstb->link_address_sent) {
++		drm_dp_send_link_address(mgr, mstb);
++		mstb->link_address_sent = true;
++	}
++	list_for_each_entry(port, &mstb->ports, next) {
++		if (port->input)
++			continue;
++
++		if (!port->ddps)
++			continue;
++
++		if (!port->available_pbn)
++			drm_dp_send_enum_path_resources(mgr, mstb, port);
++
++		if (port->mstb)
++			drm_dp_check_and_send_link_address(mgr, port->mstb);
++	}
++}
++
++static void drm_dp_mst_link_probe_work(struct work_struct *work)
++{
++	struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, work);
++
++	drm_dp_check_and_send_link_address(mgr, mgr->mst_primary);
++
++}
++
++static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
++				 u8 *guid)
++{
++	static u8 zero_guid[16];
++
++	if (!memcmp(guid, zero_guid, 16)) {
++		u64 salt = get_jiffies_64();
++		memcpy(&guid[0], &salt, sizeof(u64));
++		memcpy(&guid[8], &salt, sizeof(u64));
++		return false;
++	}
++	return true;
++}
++
++#if 0
++static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes)
++{
++	struct drm_dp_sideband_msg_req_body req;
++
++	req.req_type = DP_REMOTE_DPCD_READ;
++	req.u.dpcd_read.port_number = port_num;
++	req.u.dpcd_read.dpcd_address = offset;
++	req.u.dpcd_read.num_bytes = num_bytes;
++	drm_dp_encode_sideband_req(&req, msg);
++
++	return 0;
++}
++#endif
++
++static int drm_dp_send_sideband_msg(struct drm_dp_mst_topology_mgr *mgr,
++				    bool up, u8 *msg, int len)
++{
++	int ret;
++	int regbase = up ? DP_SIDEBAND_MSG_UP_REP_BASE : DP_SIDEBAND_MSG_DOWN_REQ_BASE;
++	int tosend, total, offset;
++	int retries = 0;
++
++retry:
++	total = len;
++	offset = 0;
++	do {
++		tosend = min3(mgr->max_dpcd_transaction_bytes, 16, total);
++
++		ret = drm_dp_dpcd_write(mgr->aux, regbase + offset,
++					&msg[offset],
++					tosend);
++		if (ret != tosend) {
++			if (ret == -EIO && retries < 5) {
++				retries++;
++				goto retry;
++			}
++			DRM_DEBUG_KMS("failed to dpcd write %d %d\n", tosend, ret);
++			WARN(1, "fail\n");
++
++			return -EIO;
++		}
++		offset += tosend;
++		total -= tosend;
++	} while (total > 0);
++	return 0;
++}
++
++static int set_hdr_from_dst_qlock(struct drm_dp_sideband_msg_hdr *hdr,
++				  struct drm_dp_sideband_msg_tx *txmsg)
++{
++	struct drm_dp_mst_branch *mstb = txmsg->dst;
++
++	/* both msg slots are full */
++	if (txmsg->seqno == -1) {
++		if (mstb->tx_slots[0] && mstb->tx_slots[1]) {
++			DRM_DEBUG_KMS("%s: failed to find slot\n", __func__);
++			return -EAGAIN;
++		}
++		if (mstb->tx_slots[0] == NULL && mstb->tx_slots[1] == NULL) {
++			txmsg->seqno = mstb->last_seqno;
++			mstb->last_seqno ^= 1;
++		} else if (mstb->tx_slots[0] == NULL)
++			txmsg->seqno = 0;
++		else
++			txmsg->seqno = 1;
++		mstb->tx_slots[txmsg->seqno] = txmsg;
++	}
++	hdr->broadcast = 0;
++	hdr->path_msg = txmsg->path_msg;
++	hdr->lct = mstb->lct;
++	hdr->lcr = mstb->lct - 1;
++	if (mstb->lct > 1)
++		memcpy(hdr->rad, mstb->rad, mstb->lct / 2);
++	hdr->seqno = txmsg->seqno;
++	return 0;
++}
++/*
++ * process a single block of the next message in the sideband queue
++ */
++static int process_single_tx_qlock(struct drm_dp_mst_topology_mgr *mgr,
++				   struct drm_dp_sideband_msg_tx *txmsg,
++				   bool up)
++{
++	u8 chunk[48];
++	struct drm_dp_sideband_msg_hdr hdr;
++	int len, space, idx, tosend;
++	int ret;
++
++	memset(&hdr, 0, sizeof(struct drm_dp_sideband_msg_hdr));
++
++	if (txmsg->state == DRM_DP_SIDEBAND_TX_QUEUED) {
++		txmsg->seqno = -1;
++		txmsg->state = DRM_DP_SIDEBAND_TX_START_SEND;
++	}
++
++	/* make hdr from dst mst - for replies use seqno
++	   otherwise assign one */
++	ret = set_hdr_from_dst_qlock(&hdr, txmsg);
++	if (ret < 0)
++		return ret;
++
++	/* amount left to send in this message */
++	len = txmsg->cur_len - txmsg->cur_offset;
++
++	/* 48 - sideband msg size - 1 byte for data CRC, x header bytes */
++	space = 48 - 1 - drm_dp_calc_sb_hdr_size(&hdr);
++
++	tosend = min(len, space);
++	if (len == txmsg->cur_len)
++		hdr.somt = 1;
++	if (space >= len)
++		hdr.eomt = 1;
++
++
++	hdr.msg_len = tosend + 1;
++	drm_dp_encode_sideband_msg_hdr(&hdr, chunk, &idx);
++	memcpy(&chunk[idx], &txmsg->msg[txmsg->cur_offset], tosend);
++	/* add crc at end */
++	drm_dp_crc_sideband_chunk_req(&chunk[idx], tosend);
++	idx += tosend + 1;
++
++	ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
++	if (ret) {
++		DRM_DEBUG_KMS("sideband msg failed to send\n");
++		return ret;
++	}
++
++	txmsg->cur_offset += tosend;
++	if (txmsg->cur_offset == txmsg->cur_len) {
++		txmsg->state = DRM_DP_SIDEBAND_TX_SENT;
++		return 1;
++	}
++	return 0;
++}
++
++/* must be called holding qlock */
++static void process_single_down_tx_qlock(struct drm_dp_mst_topology_mgr *mgr)
++{
++	struct drm_dp_sideband_msg_tx *txmsg;
++	int ret;
++
++	/* construct a chunk from the first msg in the tx_msg queue */
++	if (list_empty(&mgr->tx_msg_downq)) {
++		mgr->tx_down_in_progress = false;
++		return;
++	}
++	mgr->tx_down_in_progress = true;
++
++	txmsg = list_first_entry(&mgr->tx_msg_downq, struct drm_dp_sideband_msg_tx, next);
++	ret = process_single_tx_qlock(mgr, txmsg, false);
++	if (ret == 1) {
++		/* txmsg is sent it should be in the slots now */
++		list_del(&txmsg->next);
++	} else if (ret) {
++		DRM_DEBUG_KMS("failed to send msg in q %d\n", ret);
++		list_del(&txmsg->next);
++		if (txmsg->seqno != -1)
++			txmsg->dst->tx_slots[txmsg->seqno] = NULL;
++		txmsg->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
++		wake_up(&mgr->tx_waitq);
++	}
++	if (list_empty(&mgr->tx_msg_downq)) {
++		mgr->tx_down_in_progress = false;
++		return;
++	}
++}
++
++/* called holding qlock */
++static void process_single_up_tx_qlock(struct drm_dp_mst_topology_mgr *mgr)
++{
++	struct drm_dp_sideband_msg_tx *txmsg;
++	int ret;
++
++	/* construct a chunk from the first msg in the tx_msg queue */
++	if (list_empty(&mgr->tx_msg_upq)) {
++		mgr->tx_up_in_progress = false;
++		return;
++	}
++
++	txmsg = list_first_entry(&mgr->tx_msg_upq, struct drm_dp_sideband_msg_tx, next);
++	ret = process_single_tx_qlock(mgr, txmsg, true);
++	if (ret == 1) {
++		/* up txmsgs aren't put in slots - so free after we send it */
++		list_del(&txmsg->next);
++		kfree(txmsg);
++	} else if (ret)
++		DRM_DEBUG_KMS("failed to send msg in q %d\n", ret);
++	mgr->tx_up_in_progress = true;
++}
++
++static void drm_dp_queue_down_tx(struct drm_dp_mst_topology_mgr *mgr,
++				 struct drm_dp_sideband_msg_tx *txmsg)
++{
++	mutex_lock(&mgr->qlock);
++	list_add_tail(&txmsg->next, &mgr->tx_msg_downq);
++	if (!mgr->tx_down_in_progress)
++		process_single_down_tx_qlock(mgr);
++	mutex_unlock(&mgr->qlock);
++}
++
++static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr,
++				    struct drm_dp_mst_branch *mstb)
++{
++	int len;
++	struct drm_dp_sideband_msg_tx *txmsg;
++	int ret;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg)
++		return -ENOMEM;
++
++	txmsg->dst = mstb;
++	len = build_link_address(txmsg);
++
++	drm_dp_queue_down_tx(mgr, txmsg);
++
++	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
++	if (ret > 0) {
++		int i;
++
++		if (txmsg->reply.reply_type == 1)
++			DRM_DEBUG_KMS("link address nak received\n");
++		else {
++			DRM_DEBUG_KMS("link address reply: %d\n", txmsg->reply.u.link_addr.nports);
++			for (i = 0; i < txmsg->reply.u.link_addr.nports; i++) {
++				DRM_DEBUG_KMS("port %d: input %d, pdt: %d, pn: %d, dpcd_rev: %02x, mcs: %d, ddps: %d, ldps %d, sdp %d/%d\n", i,
++				       txmsg->reply.u.link_addr.ports[i].input_port,
++				       txmsg->reply.u.link_addr.ports[i].peer_device_type,
++				       txmsg->reply.u.link_addr.ports[i].port_number,
++				       txmsg->reply.u.link_addr.ports[i].dpcd_revision,
++				       txmsg->reply.u.link_addr.ports[i].mcs,
++				       txmsg->reply.u.link_addr.ports[i].ddps,
++				       txmsg->reply.u.link_addr.ports[i].legacy_device_plug_status,
++				       txmsg->reply.u.link_addr.ports[i].num_sdp_streams,
++				       txmsg->reply.u.link_addr.ports[i].num_sdp_stream_sinks);
++			}
++			for (i = 0; i < txmsg->reply.u.link_addr.nports; i++) {
++				drm_dp_add_port(mstb, mgr->dev, &txmsg->reply.u.link_addr.ports[i]);
++			}
++			(*mgr->cbs->hotplug)(mgr);
++		}
++	} else
++		DRM_DEBUG_KMS("link address failed %d\n", ret);
++
++	kfree(txmsg);
++	return 0;
++}
++
++static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
++					   struct drm_dp_mst_branch *mstb,
++					   struct drm_dp_mst_port *port)
++{
++	int len;
++	struct drm_dp_sideband_msg_tx *txmsg;
++	int ret;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg)
++		return -ENOMEM;
++
++	txmsg->dst = mstb;
++	len = build_enum_path_resources(txmsg, port->port_num);
++
++	drm_dp_queue_down_tx(mgr, txmsg);
++
++	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
++	if (ret > 0) {
++		if (txmsg->reply.reply_type == 1)
++			DRM_DEBUG_KMS("enum path resources nak received\n");
++		else {
++			if (port->port_num != txmsg->reply.u.path_resources.port_number)
++				DRM_ERROR("got incorrect port in response\n");
++			DRM_DEBUG_KMS("enum path resources %d: %d %d\n", txmsg->reply.u.path_resources.port_number, txmsg->reply.u.path_resources.full_payload_bw_number,
++			       txmsg->reply.u.path_resources.avail_payload_bw_number);
++			port->available_pbn = txmsg->reply.u.path_resources.avail_payload_bw_number;
++		}
++	}
++
++	kfree(txmsg);
++	return 0;
++}
++
++static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
++				   struct drm_dp_mst_port *port,
++				   int id,
++				   int pbn)
++{
++	struct drm_dp_sideband_msg_tx *txmsg;
++	struct drm_dp_mst_branch *mstb;
++	int len, ret;
++
++	mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
++	if (!mstb)
++		return -EINVAL;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg) {
++		ret = -ENOMEM;
++		goto fail_put;
++	}
++
++	txmsg->dst = mstb;
++	len = build_allocate_payload(txmsg, port->port_num,
++				     id,
++				     pbn);
++
++	drm_dp_queue_down_tx(mgr, txmsg);
++
++	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
++	if (ret > 0) {
++		if (txmsg->reply.reply_type == 1) {
++			ret = -EINVAL;
++		} else
++			ret = 0;
++	}
++	kfree(txmsg);
++fail_put:
++	drm_dp_put_mst_branch_device(mstb);
++	return ret;
++}
++
++static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr,
++				       int id,
++				       struct drm_dp_payload *payload)
++{
++	int ret;
++
++	ret = drm_dp_dpcd_write_payload(mgr, id, payload);
++	if (ret < 0) {
++		payload->payload_state = 0;
++		return ret;
++	}
++	payload->payload_state = DP_PAYLOAD_LOCAL;
++	return 0;
++}
++
++static int drm_dp_create_payload_step2(struct drm_dp_mst_topology_mgr *mgr,
++				       struct drm_dp_mst_port *port,
++				       int id,
++				       struct drm_dp_payload *payload)
++{
++	int ret;
++	ret = drm_dp_payload_send_msg(mgr, port, id, port->vcpi.pbn);
++	if (ret < 0)
++		return ret;
++	payload->payload_state = DP_PAYLOAD_REMOTE;
++	return ret;
++}
++
++static int drm_dp_destroy_payload_step1(struct drm_dp_mst_topology_mgr *mgr,
++					struct drm_dp_mst_port *port,
++					int id,
++					struct drm_dp_payload *payload)
++{
++	DRM_DEBUG_KMS("\n");
++	/* its okay for these to fail */
++	if (port) {
++		drm_dp_payload_send_msg(mgr, port, id, 0);
++	}
++
++	drm_dp_dpcd_write_payload(mgr, id, payload);
++	payload->payload_state = DP_PAYLOAD_DELETE_LOCAL;
++	return 0;
++}
++
++static int drm_dp_destroy_payload_step2(struct drm_dp_mst_topology_mgr *mgr,
++					int id,
++					struct drm_dp_payload *payload)
++{
++	payload->payload_state = 0;
++	return 0;
++}
++
++/**
++ * drm_dp_update_payload_part1() - Execute payload update part 1
++ * @mgr: manager to use.
++ *
++ * This iterates over all proposed virtual channels, and tries to
++ * allocate space in the link for them. For 0->slots transitions,
++ * this step just writes the VCPI to the MST device. For slots->0
++ * transitions, this writes the updated VCPIs and removes the
++ * remote VC payloads.
++ *
++ * after calling this the driver should generate ACT and payload
++ * packets.
++ */
++int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr)
++{
++	int i, j;
++	int cur_slots = 1;
++	struct drm_dp_payload req_payload;
++	struct drm_dp_mst_port *port;
++
++	mutex_lock(&mgr->payload_lock);
++	for (i = 0; i < mgr->max_payloads; i++) {
++		/* solve the current payloads - compare to the hw ones
++		   - update the hw view */
++		req_payload.start_slot = cur_slots;
++		if (mgr->proposed_vcpis[i]) {
++			port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
++			req_payload.num_slots = mgr->proposed_vcpis[i]->num_slots;
++		} else {
++			port = NULL;
++			req_payload.num_slots = 0;
++		}
++
++		if (mgr->payloads[i].start_slot != req_payload.start_slot) {
++			mgr->payloads[i].start_slot = req_payload.start_slot;
++		}
++		/* work out what is required to happen with this payload */
++		if (mgr->payloads[i].num_slots != req_payload.num_slots) {
++
++			/* need to push an update for this payload */
++			if (req_payload.num_slots) {
++				drm_dp_create_payload_step1(mgr, mgr->proposed_vcpis[i]->vcpi, &req_payload);
++				mgr->payloads[i].num_slots = req_payload.num_slots;
++			} else if (mgr->payloads[i].num_slots) {
++				mgr->payloads[i].num_slots = 0;
++				drm_dp_destroy_payload_step1(mgr, port, port->vcpi.vcpi, &mgr->payloads[i]);
++				req_payload.payload_state = mgr->payloads[i].payload_state;
++				mgr->payloads[i].start_slot = 0;
++			}
++			mgr->payloads[i].payload_state = req_payload.payload_state;
++		}
++		cur_slots += req_payload.num_slots;
++	}
++
++	for (i = 0; i < mgr->max_payloads; i++) {
++		if (mgr->payloads[i].payload_state == DP_PAYLOAD_DELETE_LOCAL) {
++			DRM_DEBUG_KMS("removing payload %d\n", i);
++			for (j = i; j < mgr->max_payloads - 1; j++) {
++				memcpy(&mgr->payloads[j], &mgr->payloads[j + 1], sizeof(struct drm_dp_payload));
++				mgr->proposed_vcpis[j] = mgr->proposed_vcpis[j + 1];
++				if (mgr->proposed_vcpis[j] && mgr->proposed_vcpis[j]->num_slots) {
++					set_bit(j + 1, &mgr->payload_mask);
++				} else {
++					clear_bit(j + 1, &mgr->payload_mask);
++				}
++			}
++			memset(&mgr->payloads[mgr->max_payloads - 1], 0, sizeof(struct drm_dp_payload));
++			mgr->proposed_vcpis[mgr->max_payloads - 1] = NULL;
++			clear_bit(mgr->max_payloads, &mgr->payload_mask);
++
++		}
++	}
++	mutex_unlock(&mgr->payload_lock);
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_dp_update_payload_part1);
++
++/**
++ * drm_dp_update_payload_part2() - Execute payload update part 2
++ * @mgr: manager to use.
++ *
++ * This iterates over all proposed virtual channels, and tries to
++ * allocate space in the link for them. For 0->slots transitions,
++ * this step writes the remote VC payload commands. For slots->0
++ * this just resets some internal state.
++ */
++int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr)
++{
++	struct drm_dp_mst_port *port;
++	int i;
++	int ret = 0;
++	mutex_lock(&mgr->payload_lock);
++	for (i = 0; i < mgr->max_payloads; i++) {
++
++		if (!mgr->proposed_vcpis[i])
++			continue;
++
++		port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
++
++		DRM_DEBUG_KMS("payload %d %d\n", i, mgr->payloads[i].payload_state);
++		if (mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL) {
++			ret = drm_dp_create_payload_step2(mgr, port, mgr->proposed_vcpis[i]->vcpi, &mgr->payloads[i]);
++		} else if (mgr->payloads[i].payload_state == DP_PAYLOAD_DELETE_LOCAL) {
++			ret = drm_dp_destroy_payload_step2(mgr, mgr->proposed_vcpis[i]->vcpi, &mgr->payloads[i]);
++		}
++		if (ret) {
++			mutex_unlock(&mgr->payload_lock);
++			return ret;
++		}
++	}
++	mutex_unlock(&mgr->payload_lock);
++	return 0;
++}
++EXPORT_SYMBOL(drm_dp_update_payload_part2);
++
++#if 0 /* unused as of yet */
++static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
++				 struct drm_dp_mst_port *port,
++				 int offset, int size)
++{
++	int len;
++	struct drm_dp_sideband_msg_tx *txmsg;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg)
++		return -ENOMEM;
++
++	len = build_dpcd_read(txmsg, port->port_num, 0, 8);
++	txmsg->dst = port->parent;
++
++	drm_dp_queue_down_tx(mgr, txmsg);
++
++	return 0;
++}
++#endif
++
++static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr,
++				  struct drm_dp_mst_port *port,
++				  int offset, int size, u8 *bytes)
++{
++	int len;
++	int ret;
++	struct drm_dp_sideband_msg_tx *txmsg;
++	struct drm_dp_mst_branch *mstb;
++
++	mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
++	if (!mstb)
++		return -EINVAL;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg) {
++		ret = -ENOMEM;
++		goto fail_put;
++	}
++
++	len = build_dpcd_write(txmsg, port->port_num, offset, size, bytes);
++	txmsg->dst = mstb;
++
++	drm_dp_queue_down_tx(mgr, txmsg);
++
++	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
++	if (ret > 0) {
++		if (txmsg->reply.reply_type == 1) {
++			ret = -EINVAL;
++		} else
++			ret = 0;
++	}
++	kfree(txmsg);
++fail_put:
++	drm_dp_put_mst_branch_device(mstb);
++	return ret;
++}
++
++static int drm_dp_encode_up_ack_reply(struct drm_dp_sideband_msg_tx *msg, u8 req_type)
++{
++	struct drm_dp_sideband_msg_reply_body reply;
++
++	reply.reply_type = 1;
++	reply.req_type = req_type;
++	drm_dp_encode_sideband_reply(&reply, msg);
++	return 0;
++}
++
++static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
++				    struct drm_dp_mst_branch *mstb,
++				    int req_type, int seqno, bool broadcast)
++{
++	struct drm_dp_sideband_msg_tx *txmsg;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg)
++		return -ENOMEM;
++
++	txmsg->dst = mstb;
++	txmsg->seqno = seqno;
++	drm_dp_encode_up_ack_reply(txmsg, req_type);
++
++	mutex_lock(&mgr->qlock);
++	list_add_tail(&txmsg->next, &mgr->tx_msg_upq);
++	if (!mgr->tx_up_in_progress) {
++		process_single_up_tx_qlock(mgr);
++	}
++	mutex_unlock(&mgr->qlock);
++	return 0;
++}
++
++static bool drm_dp_get_vc_payload_bw(int dp_link_bw,
++				     int dp_link_count,
++				     int *out)
++{
++	switch (dp_link_bw) {
++	default:
++		DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",
++			      dp_link_bw, dp_link_count);
++		return false;
++
++	case DP_LINK_BW_1_62:
++		*out = 3 * dp_link_count;
++		break;
++	case DP_LINK_BW_2_7:
++		*out = 5 * dp_link_count;
++		break;
++	case DP_LINK_BW_5_4:
++		*out = 10 * dp_link_count;
++		break;
++	}
++	return true;
++}
++
++/**
++ * drm_dp_mst_topology_mgr_set_mst() - Set the MST state for a topology manager
++ * @mgr: manager to set state for
++ * @mst_state: true to enable MST on this connector - false to disable.
++ *
++ * This is called by the driver when it detects an MST capable device plugged
++ * into a DP MST capable port, or when a DP MST capable device is unplugged.
++ */
++int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state)
++{
++	int ret = 0;
++	struct drm_dp_mst_branch *mstb = NULL;
++
++	mutex_lock(&mgr->lock);
++	if (mst_state == mgr->mst_state)
++		goto out_unlock;
++
++	mgr->mst_state = mst_state;
++	/* set the device into MST mode */
++	if (mst_state) {
++		WARN_ON(mgr->mst_primary);
++
++		/* get dpcd info */
++		ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
++		if (ret != DP_RECEIVER_CAP_SIZE) {
++			DRM_DEBUG_KMS("failed to read DPCD\n");
++			goto out_unlock;
++		}
++
++		if (!drm_dp_get_vc_payload_bw(mgr->dpcd[1],
++					      mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK,
++					      &mgr->pbn_div)) {
++			ret = -EINVAL;
++			goto out_unlock;
++		}
++
++		mgr->total_pbn = 2560;
++		mgr->total_slots = DIV_ROUND_UP(mgr->total_pbn, mgr->pbn_div);
++		mgr->avail_slots = mgr->total_slots;
++
++		/* add initial branch device at LCT 1 */
++		mstb = drm_dp_add_mst_branch_device(1, NULL);
++		if (mstb == NULL) {
++			ret = -ENOMEM;
++			goto out_unlock;
++		}
++		mstb->mgr = mgr;
++
++		/* give this the main reference */
++		mgr->mst_primary = mstb;
++		kref_get(&mgr->mst_primary->kref);
++
++		{
++			struct drm_dp_payload reset_pay;
++			reset_pay.start_slot = 0;
++			reset_pay.num_slots = 0x3f;
++			drm_dp_dpcd_write_payload(mgr, 0, &reset_pay);
++		}
++
++		ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
++					 DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC);
++		if (ret < 0) {
++			goto out_unlock;
++		}
++
++
++		/* sort out guid */
++		ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, mgr->guid, 16);
++		if (ret != 16) {
++			DRM_DEBUG_KMS("failed to read DP GUID %d\n", ret);
++			goto out_unlock;
++		}
++
++		mgr->guid_valid = drm_dp_validate_guid(mgr, mgr->guid);
++		if (!mgr->guid_valid) {
++			ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, mgr->guid, 16);
++			mgr->guid_valid = true;
++		}
++
++		queue_work(system_long_wq, &mgr->work);
++
++		ret = 0;
++	} else {
++		/* disable MST on the device */
++		mstb = mgr->mst_primary;
++		mgr->mst_primary = NULL;
++		/* this can fail if the device is gone */
++		drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
++		ret = 0;
++		memset(mgr->payloads, 0, mgr->max_payloads * sizeof(struct drm_dp_payload));
++		mgr->payload_mask = 0;
++		set_bit(0, &mgr->payload_mask);
++		mgr->vcpi_mask = 0;
++	}
++
++out_unlock:
++	mutex_unlock(&mgr->lock);
++	if (mstb)
++		drm_dp_put_mst_branch_device(mstb);
++	return ret;
++
++}
++EXPORT_SYMBOL(drm_dp_mst_topology_mgr_set_mst);
++
++/**
++ * drm_dp_mst_topology_mgr_suspend() - suspend the MST manager
++ * @mgr: manager to suspend
++ *
++ * This function tells the MST device that we can't handle UP messages
++ * anymore. This should stop it from sending any since we are suspended.
++ */
++void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr)
++{
++	mutex_lock(&mgr->lock);
++	drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
++			   DP_MST_EN | DP_UPSTREAM_IS_SRC);
++	mutex_unlock(&mgr->lock);
++}
++EXPORT_SYMBOL(drm_dp_mst_topology_mgr_suspend);
++
++/**
++ * drm_dp_mst_topology_mgr_resume() - resume the MST manager
++ * @mgr: manager to resume
++ *
++ * This will fetch DPCD and see if the device is still there,
++ * if it is, it will rewrite the MSTM control bits, and return.
++ *
++ * if the device fails this returns -1, and the driver should do
++ * a full MST reprobe, in case we were undocked.
++ */
++int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr)
++{
++	int ret = 0;
++
++	mutex_lock(&mgr->lock);
++
++	if (mgr->mst_primary) {
++		int sret;
++		sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
++		if (sret != DP_RECEIVER_CAP_SIZE) {
++			DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
++			ret = -1;
++			goto out_unlock;
++		}
++
++		ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
++					 DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC);
++		if (ret < 0) {
++			DRM_DEBUG_KMS("mst write failed - undocked during suspend?\n");
++			ret = -1;
++			goto out_unlock;
++		}
++		ret = 0;
++	} else
++		ret = -1;
++
++out_unlock:
++	mutex_unlock(&mgr->lock);
++	return ret;
++}
++EXPORT_SYMBOL(drm_dp_mst_topology_mgr_resume);
++
++static void drm_dp_get_one_sb_msg(struct drm_dp_mst_topology_mgr *mgr, bool up)
++{
++	int len;
++	u8 replyblock[32];
++	int replylen, origlen, curreply;
++	int ret;
++	struct drm_dp_sideband_msg_rx *msg;
++	int basereg = up ? DP_SIDEBAND_MSG_UP_REQ_BASE : DP_SIDEBAND_MSG_DOWN_REP_BASE;
++	msg = up ? &mgr->up_req_recv : &mgr->down_rep_recv;
++
++	len = min(mgr->max_dpcd_transaction_bytes, 16);
++	ret = drm_dp_dpcd_read(mgr->aux, basereg,
++			       replyblock, len);
++	if (ret != len) {
++		DRM_DEBUG_KMS("failed to read DPCD down rep %d %d\n", len, ret);
++		return;
++	}
++	ret = drm_dp_sideband_msg_build(msg, replyblock, len, true);
++	if (!ret) {
++		DRM_DEBUG_KMS("sideband msg build failed %d\n", replyblock[0]);
++		return;
++	}
++	replylen = msg->curchunk_len + msg->curchunk_hdrlen;
++
++	origlen = replylen;
++	replylen -= len;
++	curreply = len;
++	while (replylen > 0) {
++		len = min3(replylen, mgr->max_dpcd_transaction_bytes, 16);
++		ret = drm_dp_dpcd_read(mgr->aux, basereg + curreply,
++				    replyblock, len);
++		if (ret != len) {
++			DRM_DEBUG_KMS("failed to read a chunk\n");
++		}
++		ret = drm_dp_sideband_msg_build(msg, replyblock, len, false);
++		if (ret == false)
++			DRM_DEBUG_KMS("failed to build sideband msg\n");
++		curreply += len;
++		replylen -= len;
++	}
++}
++
++static int drm_dp_mst_handle_down_rep(struct drm_dp_mst_topology_mgr *mgr)
++{
++	int ret = 0;
++
++	drm_dp_get_one_sb_msg(mgr, false);
++
++	if (mgr->down_rep_recv.have_eomt) {
++		struct drm_dp_sideband_msg_tx *txmsg;
++		struct drm_dp_mst_branch *mstb;
++		int slot = -1;
++		mstb = drm_dp_get_mst_branch_device(mgr,
++						    mgr->down_rep_recv.initial_hdr.lct,
++						    mgr->down_rep_recv.initial_hdr.rad);
++
++		if (!mstb) {
++			DRM_DEBUG_KMS("Got MST reply from unknown device %d\n", mgr->down_rep_recv.initial_hdr.lct);
++			memset(&mgr->down_rep_recv, 0, sizeof(struct drm_dp_sideband_msg_rx));
++			return 0;
++		}
++
++		/* find the message */
++		slot = mgr->down_rep_recv.initial_hdr.seqno;
++		mutex_lock(&mgr->qlock);
++		txmsg = mstb->tx_slots[slot];
++		/* remove from slots */
++		mutex_unlock(&mgr->qlock);
++
++		if (!txmsg) {
++			DRM_DEBUG_KMS("Got MST reply with no msg %p %d %d %02x %02x\n",
++			       mstb,
++			       mgr->down_rep_recv.initial_hdr.seqno,
++			       mgr->down_rep_recv.initial_hdr.lct,
++				      mgr->down_rep_recv.initial_hdr.rad[0],
++				      mgr->down_rep_recv.msg[0]);
++			drm_dp_put_mst_branch_device(mstb);
++			memset(&mgr->down_rep_recv, 0, sizeof(struct drm_dp_sideband_msg_rx));
++			return 0;
++		}
++
++		drm_dp_sideband_parse_reply(&mgr->down_rep_recv, &txmsg->reply);
++		if (txmsg->reply.reply_type == 1) {
++			DRM_DEBUG_KMS("Got NAK reply: req 0x%02x, reason 0x%02x, nak data 0x%02x\n", txmsg->reply.req_type, txmsg->reply.u.nak.reason, txmsg->reply.u.nak.nak_data);
++		}
++
++		memset(&mgr->down_rep_recv, 0, sizeof(struct drm_dp_sideband_msg_rx));
++		drm_dp_put_mst_branch_device(mstb);
++
++		mutex_lock(&mgr->qlock);
++		txmsg->state = DRM_DP_SIDEBAND_TX_RX;
++		mstb->tx_slots[slot] = NULL;
++		mutex_unlock(&mgr->qlock);
++
++		wake_up(&mgr->tx_waitq);
++	}
++	return ret;
++}
++
++static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
++{
++	int ret = 0;
++	drm_dp_get_one_sb_msg(mgr, true);
++
++	if (mgr->up_req_recv.have_eomt) {
++		struct drm_dp_sideband_msg_req_body msg;
++		struct drm_dp_mst_branch *mstb;
++		bool seqno;
++		mstb = drm_dp_get_mst_branch_device(mgr,
++						    mgr->up_req_recv.initial_hdr.lct,
++						    mgr->up_req_recv.initial_hdr.rad);
++		if (!mstb) {
++			DRM_DEBUG_KMS("Got MST reply from unknown device %d\n", mgr->up_req_recv.initial_hdr.lct);
++			memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx));
++			return 0;
++		}
++
++		seqno = mgr->up_req_recv.initial_hdr.seqno;
++		drm_dp_sideband_parse_req(&mgr->up_req_recv, &msg);
++
++		if (msg.req_type == DP_CONNECTION_STATUS_NOTIFY) {
++			drm_dp_send_up_ack_reply(mgr, mstb, msg.req_type, seqno, false);
++			drm_dp_update_port(mstb, &msg.u.conn_stat);
++			DRM_DEBUG_KMS("Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n", msg.u.conn_stat.port_number, msg.u.conn_stat.legacy_device_plug_status, msg.u.conn_stat.displayport_device_plug_status, msg.u.conn_stat.message_capability_status, msg.u.conn_stat.input_port, msg.u.conn_stat.peer_device_type);
++			(*mgr->cbs->hotplug)(mgr);
++
++		} else if (msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
++			drm_dp_send_up_ack_reply(mgr, mstb, msg.req_type, seqno, false);
++			DRM_DEBUG_KMS("Got RSN: pn: %d avail_pbn %d\n", msg.u.resource_stat.port_number, msg.u.resource_stat.available_pbn);
++		}
++
++		drm_dp_put_mst_branch_device(mstb);
++		memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx));
++	}
++	return ret;
++}
++
++/**
++ * drm_dp_mst_hpd_irq() - MST hotplug IRQ notify
++ * @mgr: manager to notify irq for.
++ * @esi: 4 bytes from SINK_COUNT_ESI
++ * @handled: whether the hpd interrupt was consumed or not
++ *
++ * This should be called from the driver when it detects a short IRQ,
++ * along with the value of the DEVICE_SERVICE_IRQ_VECTOR_ESI0. The
++ * topology manager will process the sideband messages received as a result
++ * of this.
++ */
++int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled)
++{
++	int ret = 0;
++	int sc;
++	*handled = false;
++	sc = esi[0] & 0x3f;
++
++	if (sc != mgr->sink_count) {
++		mgr->sink_count = sc;
++		*handled = true;
++	}
++
++	if (esi[1] & DP_DOWN_REP_MSG_RDY) {
++		ret = drm_dp_mst_handle_down_rep(mgr);
++		*handled = true;
++	}
++
++	if (esi[1] & DP_UP_REQ_MSG_RDY) {
++		ret |= drm_dp_mst_handle_up_req(mgr);
++		*handled = true;
++	}
++
++	drm_dp_mst_kick_tx(mgr);
++	return ret;
++}
++EXPORT_SYMBOL(drm_dp_mst_hpd_irq);
++
++/**
++ * drm_dp_mst_detect_port() - get connection status for an MST port
++ * @mgr: manager for this port
++ * @port: unverified pointer to a port
++ *
++ * This returns the current connection state for a port. It validates the
++ * port pointer still exists so the caller doesn't require a reference
++ */
++enum drm_connector_status drm_dp_mst_detect_port(struct drm_connector *connector,
++						 struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port)
++{
++	enum drm_connector_status status = connector_status_disconnected;
++
++	/* we need to search for the port in the mgr in case its gone */
++	port = drm_dp_get_validated_port_ref(mgr, port);
++	if (!port)
++		return connector_status_disconnected;
++
++	if (!port->ddps)
++		goto out;
++
++	switch (port->pdt) {
++	case DP_PEER_DEVICE_NONE:
++	case DP_PEER_DEVICE_MST_BRANCHING:
++		break;
++
++	case DP_PEER_DEVICE_SST_SINK:
++		status = connector_status_connected;
++		/* for logical ports - cache the EDID */
++		if (port->port_num >= 8 && !port->cached_edid) {
++			port->cached_edid = drm_get_edid(connector, &port->aux.ddc);
++		}
++		break;
++	case DP_PEER_DEVICE_DP_LEGACY_CONV:
++		if (port->ldps)
++			status = connector_status_connected;
++		break;
++	}
++out:
++	drm_dp_put_port(port);
++	return status;
++}
++EXPORT_SYMBOL(drm_dp_mst_detect_port);
++
++/**
++ * drm_dp_mst_get_edid() - get EDID for an MST port
++ * @connector: toplevel connector to get EDID for
++ * @mgr: manager for this port
++ * @port: unverified pointer to a port.
++ *
++ * This returns an EDID for the port connected to a connector,
++ * It validates the pointer still exists so the caller doesn't require a
++ * reference.
++ */
++struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port)
++{
++	struct edid *edid = NULL;
++
++	/* we need to search for the port in the mgr in case its gone */
++	port = drm_dp_get_validated_port_ref(mgr, port);
++	if (!port)
++		return NULL;
++
++	if (port->cached_edid)
++		edid = drm_edid_duplicate(port->cached_edid);
++	else
++		edid = drm_get_edid(connector, &port->aux.ddc);
++
++	drm_mode_connector_set_tile_property(connector);
++	drm_dp_put_port(port);
++	return edid;
++}
++EXPORT_SYMBOL(drm_dp_mst_get_edid);
++
++/**
++ * drm_dp_find_vcpi_slots() - find slots for this PBN value
++ * @mgr: manager to use
++ * @pbn: payload bandwidth to convert into slots.
++ */
++int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr,
++			   int pbn)
++{
++	int num_slots;
++
++	num_slots = DIV_ROUND_UP(pbn, mgr->pbn_div);
++
++	if (num_slots > mgr->avail_slots)
++		return -ENOSPC;
++	return num_slots;
++}
++EXPORT_SYMBOL(drm_dp_find_vcpi_slots);
++
++static int drm_dp_init_vcpi(struct drm_dp_mst_topology_mgr *mgr,
++			    struct drm_dp_vcpi *vcpi, int pbn)
++{
++	int num_slots;
++	int ret;
++
++	num_slots = DIV_ROUND_UP(pbn, mgr->pbn_div);
++
++	if (num_slots > mgr->avail_slots)
++		return -ENOSPC;
++
++	vcpi->pbn = pbn;
++	vcpi->aligned_pbn = num_slots * mgr->pbn_div;
++	vcpi->num_slots = num_slots;
++
++	ret = drm_dp_mst_assign_payload_id(mgr, vcpi);
++	if (ret < 0)
++		return ret;
++	return 0;
++}
++
++/**
++ * drm_dp_mst_allocate_vcpi() - Allocate a virtual channel
++ * @mgr: manager for this port
++ * @port: port to allocate a virtual channel for.
++ * @pbn: payload bandwidth number to request
++ * @slots: returned number of slots for this PBN.
++ */
++bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn, int *slots)
++{
++	int ret;
++
++	port = drm_dp_get_validated_port_ref(mgr, port);
++	if (!port)
++		return false;
++
++	if (port->vcpi.vcpi > 0) {
++		DRM_DEBUG_KMS("payload: vcpi %d already allocated for pbn %d - requested pbn %d\n", port->vcpi.vcpi, port->vcpi.pbn, pbn);
++		if (pbn == port->vcpi.pbn) {
++			*slots = port->vcpi.num_slots;
++			return true;
++		}
++	}
++
++	ret = drm_dp_init_vcpi(mgr, &port->vcpi, pbn);
++	if (ret) {
++		DRM_DEBUG_KMS("failed to init vcpi %d %d %d\n", DIV_ROUND_UP(pbn, mgr->pbn_div), mgr->avail_slots, ret);
++		goto out;
++	}
++	DRM_DEBUG_KMS("initing vcpi for %d %d\n", pbn, port->vcpi.num_slots);
++	*slots = port->vcpi.num_slots;
++
++	drm_dp_put_port(port);
++	return true;
++out:
++	return false;
++}
++EXPORT_SYMBOL(drm_dp_mst_allocate_vcpi);
++
++/**
++ * drm_dp_mst_reset_vcpi_slots() - Reset number of slots to 0 for VCPI
++ * @mgr: manager for this port
++ * @port: unverified pointer to a port.
++ *
++ * This just resets the number of slots for the ports VCPI for later programming.
++ */
++void drm_dp_mst_reset_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port)
++{
++	port = drm_dp_get_validated_port_ref(mgr, port);
++	if (!port)
++		return;
++	port->vcpi.num_slots = 0;
++	drm_dp_put_port(port);
++}
++EXPORT_SYMBOL(drm_dp_mst_reset_vcpi_slots);
++
++/**
++ * drm_dp_mst_deallocate_vcpi() - deallocate a VCPI
++ * @mgr: manager for this port
++ * @port: unverified port to deallocate vcpi for
++ */
++void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port)
++{
++	port = drm_dp_get_validated_port_ref(mgr, port);
++	if (!port)
++		return;
++
++	drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
++	port->vcpi.num_slots = 0;
++	port->vcpi.pbn = 0;
++	port->vcpi.aligned_pbn = 0;
++	port->vcpi.vcpi = 0;
++	drm_dp_put_port(port);
++}
++EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi);
++
++static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr,
++				     int id, struct drm_dp_payload *payload)
++{
++	u8 payload_alloc[3], status;
++	int ret;
++	int retries = 0;
++
++	drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
++			   DP_PAYLOAD_TABLE_UPDATED);
++
++	payload_alloc[0] = id;
++	payload_alloc[1] = payload->start_slot;
++	payload_alloc[2] = payload->num_slots;
++
++	ret = drm_dp_dpcd_write(mgr->aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3);
++	if (ret != 3) {
++		DRM_DEBUG_KMS("failed to write payload allocation %d\n", ret);
++		goto fail;
++	}
++
++retry:
++	ret = drm_dp_dpcd_readb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
++	if (ret < 0) {
++		DRM_DEBUG_KMS("failed to read payload table status %d\n", ret);
++		goto fail;
++	}
++
++	if (!(status & DP_PAYLOAD_TABLE_UPDATED)) {
++		retries++;
++		if (retries < 20) {
++			usleep_range(10000, 20000);
++			goto retry;
++		}
++		DRM_DEBUG_KMS("status not set after read payload table status %d\n", status);
++		ret = -EINVAL;
++		goto fail;
++	}
++	ret = 0;
++fail:
++	return ret;
++}
++
++
++/**
++ * drm_dp_check_act_status() - Check ACT handled status.
++ * @mgr: manager to use
++ *
++ * Check the payload status bits in the DPCD for ACT handled completion.
++ */
++int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr)
++{
++	u8 status;
++	int ret;
++	int count = 0;
++
++	do {
++		ret = drm_dp_dpcd_readb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
++
++		if (ret < 0) {
++			DRM_DEBUG_KMS("failed to read payload table status %d\n", ret);
++			goto fail;
++		}
++
++		if (status & DP_PAYLOAD_ACT_HANDLED)
++			break;
++		count++;
++		udelay(100);
++
++	} while (count < 30);
++
++	if (!(status & DP_PAYLOAD_ACT_HANDLED)) {
++		DRM_DEBUG_KMS("failed to get ACT bit %d after %d retries\n", status, count);
++		ret = -EINVAL;
++		goto fail;
++	}
++	return 0;
++fail:
++	return ret;
++}
++EXPORT_SYMBOL(drm_dp_check_act_status);
++
++/**
++ * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
++ * @clock: dot clock for the mode
++ * @bpp: bpp for the mode.
++ *
++ * This uses the formula in the spec to calculate the PBN value for a mode.
++ */
++int drm_dp_calc_pbn_mode(int clock, int bpp)
++{
++	fixed20_12 pix_bw;
++	fixed20_12 fbpp;
++	fixed20_12 result;
++	fixed20_12 margin, tmp;
++	u32 res;
++
++	pix_bw.full = dfixed_const(clock);
++	fbpp.full = dfixed_const(bpp);
++	tmp.full = dfixed_const(8);
++	fbpp.full = dfixed_div(fbpp, tmp);
++
++	result.full = dfixed_mul(pix_bw, fbpp);
++	margin.full = dfixed_const(54);
++	tmp.full = dfixed_const(64);
++	margin.full = dfixed_div(margin, tmp);
++	result.full = dfixed_div(result, margin);
++
++	margin.full = dfixed_const(1006);
++	tmp.full = dfixed_const(1000);
++	margin.full = dfixed_div(margin, tmp);
++	result.full = dfixed_mul(result, margin);
++
++	result.full = dfixed_div(result, tmp);
++	result.full = dfixed_ceil(result);
++	res = dfixed_trunc(result);
++	return res;
++}
++EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
++
++static int test_calc_pbn_mode(void)
++{
++	int ret;
++	ret = drm_dp_calc_pbn_mode(154000, 30);
++	if (ret != 689)
++		return -EINVAL;
++	ret = drm_dp_calc_pbn_mode(234000, 30);
++	if (ret != 1047)
++		return -EINVAL;
++	return 0;
++}
++
++/* we want to kick the TX after we've ack the up/down IRQs. */
++static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr)
++{
++	queue_work(system_long_wq, &mgr->tx_work);
++}
++
++static void drm_dp_mst_dump_mstb(struct seq_file *m,
++				 struct drm_dp_mst_branch *mstb)
++{
++	struct drm_dp_mst_port *port;
++	int tabs = mstb->lct;
++	char prefix[10];
++	int i;
++
++	for (i = 0; i < tabs; i++)
++		prefix[i] = '\t';
++	prefix[i] = '\0';
++
++	seq_printf(m, "%smst: %p, %d\n", prefix, mstb, mstb->num_ports);
++	list_for_each_entry(port, &mstb->ports, next) {
++		seq_printf(m, "%sport: %d: ddps: %d ldps: %d, %p, conn: %p\n", prefix, port->port_num, port->ddps, port->ldps, port, port->connector);
++		if (port->mstb)
++			drm_dp_mst_dump_mstb(m, port->mstb);
++	}
++}
++
++static bool dump_dp_payload_table(struct drm_dp_mst_topology_mgr *mgr,
++				  char *buf)
++{
++	int ret;
++	int i;
++	for (i = 0; i < 4; i++) {
++		ret = drm_dp_dpcd_read(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS + (i * 16), &buf[i * 16], 16);
++		if (ret != 16)
++			break;
++	}
++	if (i == 4)
++		return true;
++	return false;
++}
++
++/**
++ * drm_dp_mst_dump_topology(): dump topology to seq file.
++ * @m: seq_file to dump output to
++ * @mgr: manager to dump current topology for.
++ *
++ * helper to dump MST topology to a seq file for debugfs.
++ */
++void drm_dp_mst_dump_topology(struct seq_file *m,
++			      struct drm_dp_mst_topology_mgr *mgr)
++{
++	int i;
++	struct drm_dp_mst_port *port;
++	mutex_lock(&mgr->lock);
++	if (mgr->mst_primary)
++		drm_dp_mst_dump_mstb(m, mgr->mst_primary);
++
++	/* dump VCPIs */
++	mutex_unlock(&mgr->lock);
++
++	mutex_lock(&mgr->payload_lock);
++	seq_printf(m, "vcpi: %lx %lx\n", mgr->payload_mask, mgr->vcpi_mask);
++
++	for (i = 0; i < mgr->max_payloads; i++) {
++		if (mgr->proposed_vcpis[i]) {
++			port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
++			seq_printf(m, "vcpi %d: %d %d %d\n", i, port->port_num, port->vcpi.vcpi, port->vcpi.num_slots);
++		} else
++			seq_printf(m, "vcpi %d:unsed\n", i);
++	}
++	for (i = 0; i < mgr->max_payloads; i++) {
++		seq_printf(m, "payload %d: %d, %d, %d\n",
++			   i,
++			   mgr->payloads[i].payload_state,
++			   mgr->payloads[i].start_slot,
++			   mgr->payloads[i].num_slots);
++
++
++	}
++	mutex_unlock(&mgr->payload_lock);
++
++	mutex_lock(&mgr->lock);
++	if (mgr->mst_primary) {
++		u8 buf[64];
++		bool bret;
++		int ret;
++		ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE);
++		seq_printf(m, "dpcd: ");
++		for (i = 0; i < DP_RECEIVER_CAP_SIZE; i++)
++			seq_printf(m, "%02x ", buf[i]);
++		seq_printf(m, "\n");
++		ret = drm_dp_dpcd_read(mgr->aux, DP_FAUX_CAP, buf, 2);
++		seq_printf(m, "faux/mst: ");
++		for (i = 0; i < 2; i++)
++			seq_printf(m, "%02x ", buf[i]);
++		seq_printf(m, "\n");
++		ret = drm_dp_dpcd_read(mgr->aux, DP_MSTM_CTRL, buf, 1);
++		seq_printf(m, "mst ctrl: ");
++		for (i = 0; i < 1; i++)
++			seq_printf(m, "%02x ", buf[i]);
++		seq_printf(m, "\n");
++
++		bret = dump_dp_payload_table(mgr, buf);
++		if (bret == true) {
++			seq_printf(m, "payload table: ");
++			for (i = 0; i < 63; i++)
++				seq_printf(m, "%02x ", buf[i]);
++			seq_printf(m, "\n");
++		}
++
++	}
++
++	mutex_unlock(&mgr->lock);
++
++}
++EXPORT_SYMBOL(drm_dp_mst_dump_topology);
++
++static void drm_dp_tx_work(struct work_struct *work)
++{
++	struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, tx_work);
++
++	mutex_lock(&mgr->qlock);
++	if (mgr->tx_down_in_progress)
++		process_single_down_tx_qlock(mgr);
++	mutex_unlock(&mgr->qlock);
++}
++
++/**
++ * drm_dp_mst_topology_mgr_init - initialise a topology manager
++ * @mgr: manager struct to initialise
++ * @dev: device providing this structure - for i2c addition.
++ * @aux: DP helper aux channel to talk to this device
++ * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit
++ * @max_payloads: maximum number of payloads this GPU can source
++ * @conn_base_id: the connector object ID the MST device is connected to.
++ *
++ * Return 0 for success, or negative error code on failure
++ */
++int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr,
++				 struct device *dev, struct drm_dp_aux *aux,
++				 int max_dpcd_transaction_bytes,
++				 int max_payloads, int conn_base_id)
++{
++	mutex_init(&mgr->lock);
++	mutex_init(&mgr->qlock);
++	mutex_init(&mgr->payload_lock);
++	INIT_LIST_HEAD(&mgr->tx_msg_upq);
++	INIT_LIST_HEAD(&mgr->tx_msg_downq);
++	INIT_WORK(&mgr->work, drm_dp_mst_link_probe_work);
++	INIT_WORK(&mgr->tx_work, drm_dp_tx_work);
++	init_waitqueue_head(&mgr->tx_waitq);
++	mgr->dev = dev;
++	mgr->aux = aux;
++	mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes;
++	mgr->max_payloads = max_payloads;
++	mgr->conn_base_id = conn_base_id;
++	mgr->payloads = kcalloc(max_payloads, sizeof(struct drm_dp_payload), GFP_KERNEL);
++	if (!mgr->payloads)
++		return -ENOMEM;
++	mgr->proposed_vcpis = kcalloc(max_payloads, sizeof(struct drm_dp_vcpi *), GFP_KERNEL);
++	if (!mgr->proposed_vcpis)
++		return -ENOMEM;
++	set_bit(0, &mgr->payload_mask);
++	test_calc_pbn_mode();
++	return 0;
++}
++EXPORT_SYMBOL(drm_dp_mst_topology_mgr_init);
++
++/**
++ * drm_dp_mst_topology_mgr_destroy() - destroy topology manager.
++ * @mgr: manager to destroy
++ */
++void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr)
++{
++	mutex_lock(&mgr->payload_lock);
++	kfree(mgr->payloads);
++	mgr->payloads = NULL;
++	kfree(mgr->proposed_vcpis);
++	mgr->proposed_vcpis = NULL;
++	mutex_unlock(&mgr->payload_lock);
++	mgr->dev = NULL;
++	mgr->aux = NULL;
++}
++EXPORT_SYMBOL(drm_dp_mst_topology_mgr_destroy);
++
++/* I2C device */
++static int drm_dp_mst_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
++			       int num)
++{
++	struct drm_dp_aux *aux = adapter->algo_data;
++	struct drm_dp_mst_port *port = container_of(aux, struct drm_dp_mst_port, aux);
++	struct drm_dp_mst_branch *mstb;
++	struct drm_dp_mst_topology_mgr *mgr = port->mgr;
++	unsigned int i;
++	bool reading = false;
++	struct drm_dp_sideband_msg_req_body msg;
++	struct drm_dp_sideband_msg_tx *txmsg = NULL;
++	int ret;
++
++	mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
++	if (!mstb)
++		return -EREMOTEIO;
++
++	/* construct i2c msg */
++	/* see if last msg is a read */
++	if (msgs[num - 1].flags & I2C_M_RD)
++		reading = true;
++
++	if (!reading) {
++		DRM_DEBUG_KMS("Unsupported I2C transaction for MST device\n");
++		ret = -EIO;
++		goto out;
++	}
++
++	msg.req_type = DP_REMOTE_I2C_READ;
++	msg.u.i2c_read.num_transactions = num - 1;
++	msg.u.i2c_read.port_number = port->port_num;
++	for (i = 0; i < num - 1; i++) {
++		msg.u.i2c_read.transactions[i].i2c_dev_id = msgs[i].addr;
++		msg.u.i2c_read.transactions[i].num_bytes = msgs[i].len;
++		msg.u.i2c_read.transactions[i].bytes = msgs[i].buf;
++	}
++	msg.u.i2c_read.read_i2c_device_id = msgs[num - 1].addr;
++	msg.u.i2c_read.num_bytes_read = msgs[num - 1].len;
++
++	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
++	if (!txmsg) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	txmsg->dst = mstb;
++	drm_dp_encode_sideband_req(&msg, txmsg);
++
++	drm_dp_queue_down_tx(mgr, txmsg);
++
++	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
++	if (ret > 0) {
++
++		if (txmsg->reply.reply_type == 1) { /* got a NAK back */
++			ret = -EREMOTEIO;
++			goto out;
++		}
++		if (txmsg->reply.u.remote_i2c_read_ack.num_bytes != msgs[num - 1].len) {
++			ret = -EIO;
++			goto out;
++		}
++		memcpy(msgs[num - 1].buf, txmsg->reply.u.remote_i2c_read_ack.bytes, msgs[num - 1].len);
++		ret = num;
++	}
++out:
++	kfree(txmsg);
++	drm_dp_put_mst_branch_device(mstb);
++	return ret;
++}
++
++static u32 drm_dp_mst_i2c_functionality(struct i2c_adapter *adapter)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
++	       I2C_FUNC_SMBUS_READ_BLOCK_DATA |
++	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
++	       I2C_FUNC_10BIT_ADDR;
++}
++
++static const struct i2c_algorithm drm_dp_mst_i2c_algo = {
++	.functionality = drm_dp_mst_i2c_functionality,
++	.master_xfer = drm_dp_mst_i2c_xfer,
++};
++
++/**
++ * drm_dp_mst_register_i2c_bus() - register an I2C adapter for I2C-over-AUX
++ * @aux: DisplayPort AUX channel
++ *
++ * Returns 0 on success or a negative error code on failure.
++ */
++static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux)
++{
++	aux->ddc.algo = &drm_dp_mst_i2c_algo;
++	aux->ddc.algo_data = aux;
++	aux->ddc.retries = 3;
++
++	aux->ddc.class = I2C_CLASS_DDC;
++	aux->ddc.owner = THIS_MODULE;
++	aux->ddc.dev.parent = aux->dev;
++	aux->ddc.dev.of_node = aux->dev->of_node;
++
++	strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
++		sizeof(aux->ddc.name));
++
++	return i2c_add_adapter(&aux->ddc);
++}
++
++/**
++ * drm_dp_mst_unregister_i2c_bus() - unregister an I2C-over-AUX adapter
++ * @aux: DisplayPort AUX channel
++ */
++static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux)
++{
++	i2c_del_adapter(&aux->ddc);
++}
+diff -Naur a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
+--- a/drivers/gpu/drm/drm_drv.c	2015-03-26 14:43:30.486436437 +0530
++++ b/drivers/gpu/drm/drm_drv.c	2015-03-26 14:42:38.718435422 +0530
+@@ -1,31 +1,11 @@
+-/**
+- * \file drm_drv.c
+- * Generic driver template
+- *
+- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+- * \author Gareth Hughes <gareth@valinux.com>
+- *
+- * To use this template, you must at least define the following (samples
+- * given for the MGA driver):
+- *
+- * \code
+- * #define DRIVER_AUTHOR	"VA Linux Systems, Inc."
+- *
+- * #define DRIVER_NAME		"mga"
+- * #define DRIVER_DESC		"Matrox G200/G400"
+- * #define DRIVER_DATE		"20001127"
+- *
+- * #define drm_x		mga_##x
+- * \endcode
+- */
+-
+ /*
+- * Created: Thu Nov 23 03:10:50 2000 by gareth@valinux.com
++ * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org
+  *
+- * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
+- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
++ * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California.
+  * All Rights Reserved.
+  *
++ * Author Rickard E. (Rik) Faith <faith@valinux.com>
++ *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+@@ -40,138 +20,835 @@
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
+  */
+ 
+ #include <linux/debugfs.h>
++#include <linux/fs.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/mount.h>
+ #include <linux/slab.h>
+-#include <linux/export.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_core.h>
++#include "drm_legacy.h"
++#include "drm_internal.h"
++
++unsigned int drm_debug = 0;	/* 1 to enable debug output */
++EXPORT_SYMBOL(drm_debug);
++
++MODULE_AUTHOR(CORE_AUTHOR);
++MODULE_DESCRIPTION(CORE_DESC);
++MODULE_LICENSE("GPL and additional rights");
++MODULE_PARM_DESC(debug, "Enable debug output");
++MODULE_PARM_DESC(vblankoffdelay, "Delay until vblank irq auto-disable [msecs] (0: never disable, <0: disable immediately)");
++MODULE_PARM_DESC(timestamp_precision_usec, "Max. error on timestamps [usecs]");
++MODULE_PARM_DESC(timestamp_monotonic, "Use monotonic timestamps");
++
++module_param_named(debug, drm_debug, int, 0600);
++
++static DEFINE_SPINLOCK(drm_minor_lock);
++static struct idr drm_minors_idr;
++
++struct class *drm_class;
++static struct dentry *drm_debugfs_root;
++
++void drm_err(const char *format, ...)
++{
++	struct va_format vaf;
++	va_list args;
++
++	va_start(args, format);
++
++	vaf.fmt = format;
++	vaf.va = &args;
++
++	printk(KERN_ERR "[" DRM_NAME ":%pf] *ERROR* %pV",
++	       __builtin_return_address(0), &vaf);
++
++	va_end(args);
++}
++EXPORT_SYMBOL(drm_err);
++
++void drm_ut_debug_printk(const char *function_name, const char *format, ...)
++{
++	struct va_format vaf;
++	va_list args;
++
++	va_start(args, format);
++	vaf.fmt = format;
++	vaf.va = &args;
++
++	printk(KERN_DEBUG "[" DRM_NAME ":%s] %pV", function_name, &vaf);
++
++	va_end(args);
++}
++EXPORT_SYMBOL(drm_ut_debug_printk);
++
++#define DRM_MAGIC_HASH_ORDER  4  /**< Size of key hash table. Must be power of 2. */
++
++struct drm_master *drm_master_create(struct drm_minor *minor)
++{
++	struct drm_master *master;
++
++	master = kzalloc(sizeof(*master), GFP_KERNEL);
++	if (!master)
++		return NULL;
++
++	kref_init(&master->refcount);
++	spin_lock_init(&master->lock.spinlock);
++	init_waitqueue_head(&master->lock.lock_queue);
++	if (drm_ht_create(&master->magiclist, DRM_MAGIC_HASH_ORDER)) {
++		kfree(master);
++		return NULL;
++	}
++	INIT_LIST_HEAD(&master->magicfree);
++	master->minor = minor;
++
++	return master;
++}
++
++struct drm_master *drm_master_get(struct drm_master *master)
++{
++	kref_get(&master->refcount);
++	return master;
++}
++EXPORT_SYMBOL(drm_master_get);
++
++static void drm_master_destroy(struct kref *kref)
++{
++	struct drm_master *master = container_of(kref, struct drm_master, refcount);
++	struct drm_device *dev = master->minor->dev;
++	struct drm_map_list *r_list, *list_temp;
++
++	mutex_lock(&dev->struct_mutex);
++	if (dev->driver->master_destroy)
++		dev->driver->master_destroy(dev, master);
++
++	list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) {
++		if (r_list->master == master) {
++			drm_legacy_rmmap_locked(dev, r_list->map);
++			r_list = NULL;
++		}
++	}
++
++	if (master->unique) {
++		kfree(master->unique);
++		master->unique = NULL;
++		master->unique_len = 0;
++	}
++
++	drm_ht_remove(&master->magiclist);
++
++	mutex_unlock(&dev->struct_mutex);
++	kfree(master);
++}
++
++void drm_master_put(struct drm_master **master)
++{
++	kref_put(&(*master)->refcount, drm_master_destroy);
++	*master = NULL;
++}
++EXPORT_SYMBOL(drm_master_put);
++
++int drm_setmaster_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *file_priv)
++{
++	int ret = 0;
++
++	mutex_lock(&dev->master_mutex);
++	if (file_priv->is_master)
++		goto out_unlock;
++
++	if (file_priv->minor->master) {
++		ret = -EINVAL;
++		goto out_unlock;
++	}
++
++	if (!file_priv->master) {
++		ret = -EINVAL;
++		goto out_unlock;
++	}
++
++	file_priv->minor->master = drm_master_get(file_priv->master);
++	file_priv->is_master = 1;
++	if (dev->driver->master_set) {
++		ret = dev->driver->master_set(dev, file_priv, false);
++		if (unlikely(ret != 0)) {
++			file_priv->is_master = 0;
++			drm_master_put(&file_priv->minor->master);
++		}
++	}
++
++out_unlock:
++	mutex_unlock(&dev->master_mutex);
++	return ret;
++}
++
++int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
++			 struct drm_file *file_priv)
++{
++	int ret = -EINVAL;
++
++	mutex_lock(&dev->master_mutex);
++	if (!file_priv->is_master)
++		goto out_unlock;
++
++	if (!file_priv->minor->master)
++		goto out_unlock;
++
++	ret = 0;
++	if (dev->driver->master_drop)
++		dev->driver->master_drop(dev, file_priv, false);
++	drm_master_put(&file_priv->minor->master);
++	file_priv->is_master = 0;
++
++out_unlock:
++	mutex_unlock(&dev->master_mutex);
++	return ret;
++}
++
++/*
++ * DRM Minors
++ * A DRM device can provide several char-dev interfaces on the DRM-Major. Each
++ * of them is represented by a drm_minor object. Depending on the capabilities
++ * of the device-driver, different interfaces are registered.
++ *
++ * Minors can be accessed via dev->$minor_name. This pointer is either
++ * NULL or a valid drm_minor pointer and stays valid as long as the device is
++ * valid. This means, DRM minors have the same life-time as the underlying
++ * device. However, this doesn't mean that the minor is active. Minors are
++ * registered and unregistered dynamically according to device-state.
++ */
++
++static struct drm_minor **drm_minor_get_slot(struct drm_device *dev,
++					     unsigned int type)
++{
++	switch (type) {
++	case DRM_MINOR_LEGACY:
++		return &dev->primary;
++	case DRM_MINOR_RENDER:
++		return &dev->render;
++	case DRM_MINOR_CONTROL:
++		return &dev->control;
++	default:
++		return NULL;
++	}
++}
++
++static int drm_minor_alloc(struct drm_device *dev, unsigned int type)
++{
++	struct drm_minor *minor;
++	unsigned long flags;
++	int r;
++
++	minor = kzalloc(sizeof(*minor), GFP_KERNEL);
++	if (!minor)
++		return -ENOMEM;
++
++	minor->type = type;
++	minor->dev = dev;
++
++	idr_preload(GFP_KERNEL);
++	spin_lock_irqsave(&drm_minor_lock, flags);
++	r = idr_alloc(&drm_minors_idr,
++		      NULL,
++		      64 * type,
++		      64 * (type + 1),
++		      GFP_NOWAIT);
++	spin_unlock_irqrestore(&drm_minor_lock, flags);
++	idr_preload_end();
++
++	if (r < 0)
++		goto err_free;
++
++	minor->index = r;
++
++	minor->kdev = drm_sysfs_minor_alloc(minor);
++	if (IS_ERR(minor->kdev)) {
++		r = PTR_ERR(minor->kdev);
++		goto err_index;
++	}
++
++	*drm_minor_get_slot(dev, type) = minor;
++	return 0;
++
++err_index:
++	spin_lock_irqsave(&drm_minor_lock, flags);
++	idr_remove(&drm_minors_idr, minor->index);
++	spin_unlock_irqrestore(&drm_minor_lock, flags);
++err_free:
++	kfree(minor);
++	return r;
++}
++
++static void drm_minor_free(struct drm_device *dev, unsigned int type)
++{
++	struct drm_minor **slot, *minor;
++	unsigned long flags;
+ 
++	slot = drm_minor_get_slot(dev, type);
++	minor = *slot;
++	if (!minor)
++		return;
++
++	drm_mode_group_destroy(&minor->mode_group);
++	put_device(minor->kdev);
++
++	spin_lock_irqsave(&drm_minor_lock, flags);
++	idr_remove(&drm_minors_idr, minor->index);
++	spin_unlock_irqrestore(&drm_minor_lock, flags);
+ 
+-static int drm_version(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv);
++	kfree(minor);
++	*slot = NULL;
++}
++
++static int drm_minor_register(struct drm_device *dev, unsigned int type)
++{
++	struct drm_minor *minor;
++	unsigned long flags;
++	int ret;
++
++	DRM_DEBUG("\n");
++
++	minor = *drm_minor_get_slot(dev, type);
++	if (!minor)
++		return 0;
++
++	ret = drm_debugfs_init(minor, minor->index, drm_debugfs_root);
++	if (ret) {
++		DRM_ERROR("DRM: Failed to initialize /sys/kernel/debug/dri.\n");
++		return ret;
++	}
+ 
+-#define DRM_IOCTL_DEF(ioctl, _func, _flags) \
+-	[DRM_IOCTL_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl}
++	ret = device_add(minor->kdev);
++	if (ret)
++		goto err_debugfs;
++
++	/* replace NULL with @minor so lookups will succeed from now on */
++	spin_lock_irqsave(&drm_minor_lock, flags);
++	idr_replace(&drm_minors_idr, minor, minor->index);
++	spin_unlock_irqrestore(&drm_minor_lock, flags);
+ 
+-/** Ioctl table */
+-static const struct drm_ioctl_desc drm_ioctls[] = {
+-	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),
+-	DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+-	DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, 0),
+-	DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_SET_SAREA_CTX, drm_setsareactx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_SAREA_CTX, drm_getsareactx, DRM_AUTH),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_SET_MASTER, drm_setmaster_ioctl, DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_DROP_MASTER, drm_dropmaster_ioctl, DRM_ROOT_ONLY),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_addctx, DRM_AUTH|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_RM_CTX, drm_rmctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MOD_CTX, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GET_CTX, drm_getctx, DRM_AUTH),
+-	DRM_IOCTL_DEF(DRM_IOCTL_SWITCH_CTX, drm_switchctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_NEW_CTX, drm_newctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_RES_CTX, drm_resctx, DRM_AUTH),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_ADD_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_RM_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_LOCK, drm_lock, DRM_AUTH),
+-	DRM_IOCTL_DEF(DRM_IOCTL_UNLOCK, drm_unlock, DRM_AUTH),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_FINISH, drm_noop, DRM_AUTH),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_ADD_BUFS, drm_addbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MARK_BUFS, drm_markbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_INFO_BUFS, drm_infobufs, DRM_AUTH),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MAP_BUFS, drm_mapbufs, DRM_AUTH),
+-	DRM_IOCTL_DEF(DRM_IOCTL_FREE_BUFS, drm_freebufs, DRM_AUTH),
+-	DRM_IOCTL_DEF(DRM_IOCTL_DMA, drm_dma_ioctl, DRM_AUTH),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_CONTROL, drm_control, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-
+-#if __OS_HAS_AGP
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_ACQUIRE, drm_agp_acquire_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_RELEASE, drm_agp_release_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_ENABLE, drm_agp_enable_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_INFO, drm_agp_info_ioctl, DRM_AUTH),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_ALLOC, drm_agp_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_FREE, drm_agp_free_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_BIND, drm_agp_bind_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_AGP_UNBIND, drm_agp_unbind_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-#endif
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_sg_alloc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-	DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_sg_free, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_HANDLE_TO_FD, drm_prime_handle_to_fd_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
+-	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_FD_TO_HANDLE, drm_prime_fd_to_handle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
+-
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANERESOURCES, drm_mode_getplane_res, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANE, drm_mode_getplane, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPLANE, drm_mode_setplane, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB2, drm_mode_addfb2, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_DEBUG("new minor registered %d\n", minor->index);
++	return 0;
++
++err_debugfs:
++	drm_debugfs_cleanup(minor);
++	return ret;
++}
++
++static void drm_minor_unregister(struct drm_device *dev, unsigned int type)
++{
++	struct drm_minor *minor;
++	unsigned long flags;
++
++	minor = *drm_minor_get_slot(dev, type);
++	if (!minor || !device_is_registered(minor->kdev))
++		return;
++
++	/* replace @minor with NULL so lookups will fail from now on */
++	spin_lock_irqsave(&drm_minor_lock, flags);
++	idr_replace(&drm_minors_idr, NULL, minor->index);
++	spin_unlock_irqrestore(&drm_minor_lock, flags);
++
++	device_del(minor->kdev);
++	dev_set_drvdata(minor->kdev, NULL); /* safety belt */
++	drm_debugfs_cleanup(minor);
++}
++
++/**
++ * drm_minor_acquire - Acquire a DRM minor
++ * @minor_id: Minor ID of the DRM-minor
++ *
++ * Looks up the given minor-ID and returns the respective DRM-minor object. The
++ * refence-count of the underlying device is increased so you must release this
++ * object with drm_minor_release().
++ *
++ * As long as you hold this minor, it is guaranteed that the object and the
++ * minor->dev pointer will stay valid! However, the device may get unplugged and
++ * unregistered while you hold the minor.
++ *
++ * Returns:
++ * Pointer to minor-object with increased device-refcount, or PTR_ERR on
++ * failure.
++ */
++struct drm_minor *drm_minor_acquire(unsigned int minor_id)
++{
++	struct drm_minor *minor;
++	unsigned long flags;
++
++	spin_lock_irqsave(&drm_minor_lock, flags);
++	minor = idr_find(&drm_minors_idr, minor_id);
++	if (minor)
++		drm_dev_ref(minor->dev);
++	spin_unlock_irqrestore(&drm_minor_lock, flags);
++
++	if (!minor) {
++		return ERR_PTR(-ENODEV);
++	} else if (drm_device_is_unplugged(minor->dev)) {
++		drm_dev_unref(minor->dev);
++		return ERR_PTR(-ENODEV);
++	}
++
++	return minor;
++}
++
++/**
++ * drm_minor_release - Release DRM minor
++ * @minor: Pointer to DRM minor object
++ *
++ * Release a minor that was previously acquired via drm_minor_acquire().
++ */
++void drm_minor_release(struct drm_minor *minor)
++{
++	drm_dev_unref(minor->dev);
++}
++
++/**
++ * drm_put_dev - Unregister and release a DRM device
++ * @dev: DRM device
++ *
++ * Called at module unload time or when a PCI device is unplugged.
++ *
++ * Use of this function is discouraged. It will eventually go away completely.
++ * Please use drm_dev_unregister() and drm_dev_unref() explicitly instead.
++ *
++ * Cleans up all DRM device, calling drm_lastclose().
++ */
++void drm_put_dev(struct drm_device *dev)
++{
++	DRM_DEBUG("\n");
++
++	if (!dev) {
++		DRM_ERROR("cleanup called no dev\n");
++		return;
++	}
++
++	drm_dev_unregister(dev);
++	drm_dev_unref(dev);
++}
++EXPORT_SYMBOL(drm_put_dev);
++
++void drm_unplug_dev(struct drm_device *dev)
++{
++	/* for a USB device */
++	drm_minor_unregister(dev, DRM_MINOR_LEGACY);
++	drm_minor_unregister(dev, DRM_MINOR_RENDER);
++	drm_minor_unregister(dev, DRM_MINOR_CONTROL);
++
++	mutex_lock(&drm_global_mutex);
++
++	drm_device_set_unplugged(dev);
++
++	if (dev->open_count == 0) {
++		drm_put_dev(dev);
++	}
++	mutex_unlock(&drm_global_mutex);
++}
++EXPORT_SYMBOL(drm_unplug_dev);
++
++/*
++ * DRM internal mount
++ * We want to be able to allocate our own "struct address_space" to control
++ * memory-mappings in VRAM (or stolen RAM, ...). However, core MM does not allow
++ * stand-alone address_space objects, so we need an underlying inode. As there
++ * is no way to allocate an independent inode easily, we need a fake internal
++ * VFS mount-point.
++ *
++ * The drm_fs_inode_new() function allocates a new inode, drm_fs_inode_free()
++ * frees it again. You are allowed to use iget() and iput() to get references to
++ * the inode. But each drm_fs_inode_new() call must be paired with exactly one
++ * drm_fs_inode_free() call (which does not have to be the last iput()).
++ * We use drm_fs_inode_*() to manage our internal VFS mount-point and share it
++ * between multiple inode-users. You could, technically, call
++ * iget() + drm_fs_inode_free() directly after alloc and sometime later do an
++ * iput(), but this way you'd end up with a new vfsmount for each inode.
++ */
++
++static int drm_fs_cnt;
++static struct vfsmount *drm_fs_mnt;
++
++static const struct dentry_operations drm_fs_dops = {
++	.d_dname	= simple_dname,
++};
++
++static const struct super_operations drm_fs_sops = {
++	.statfs		= simple_statfs,
+ };
+ 
+-#define DRM_CORE_IOCTL_COUNT	ARRAY_SIZE( drm_ioctls )
++static struct dentry *drm_fs_mount(struct file_system_type *fs_type, int flags,
++				   const char *dev_name, void *data)
++{
++	return mount_pseudo(fs_type,
++			    "drm:",
++			    &drm_fs_sops,
++			    &drm_fs_dops,
++			    0x010203ff);
++}
++
++static struct file_system_type drm_fs_type = {
++	.name		= "drm",
++	.owner		= THIS_MODULE,
++	.mount		= drm_fs_mount,
++	.kill_sb	= kill_anon_super,
++};
++
++static struct inode *drm_fs_inode_new(void)
++{
++	struct inode *inode;
++	int r;
++
++	r = simple_pin_fs(&drm_fs_type, &drm_fs_mnt, &drm_fs_cnt);
++	if (r < 0) {
++		DRM_ERROR("Cannot mount pseudo fs: %d\n", r);
++		return ERR_PTR(r);
++	}
++
++	inode = alloc_anon_inode(drm_fs_mnt->mnt_sb);
++	if (IS_ERR(inode))
++		simple_release_fs(&drm_fs_mnt, &drm_fs_cnt);
++
++	return inode;
++}
++
++static void drm_fs_inode_free(struct inode *inode)
++{
++	if (inode) {
++		iput(inode);
++		simple_release_fs(&drm_fs_mnt, &drm_fs_cnt);
++	}
++}
++
++/**
++ * drm_dev_alloc - Allocate new DRM device
++ * @driver: DRM driver to allocate device for
++ * @parent: Parent device object
++ *
++ * Allocate and initialize a new DRM device. No device registration is done.
++ * Call drm_dev_register() to advertice the device to user space and register it
++ * with other core subsystems.
++ *
++ * The initial ref-count of the object is 1. Use drm_dev_ref() and
++ * drm_dev_unref() to take and drop further ref-counts.
++ *
++ * Note that for purely virtual devices @parent can be NULL.
++ *
++ * RETURNS:
++ * Pointer to new DRM device, or NULL if out of memory.
++ */
++struct drm_device *drm_dev_alloc(struct drm_driver *driver,
++				 struct device *parent)
++{
++	struct drm_device *dev;
++	int ret;
++
++	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++	if (!dev)
++		return NULL;
++
++	kref_init(&dev->ref);
++	dev->dev = parent;
++	dev->driver = driver;
++
++	INIT_LIST_HEAD(&dev->filelist);
++	INIT_LIST_HEAD(&dev->ctxlist);
++	INIT_LIST_HEAD(&dev->vmalist);
++	INIT_LIST_HEAD(&dev->maplist);
++	INIT_LIST_HEAD(&dev->vblank_event_list);
++
++	spin_lock_init(&dev->buf_lock);
++	spin_lock_init(&dev->event_lock);
++	mutex_init(&dev->struct_mutex);
++	mutex_init(&dev->ctxlist_mutex);
++	mutex_init(&dev->master_mutex);
++
++	dev->anon_inode = drm_fs_inode_new();
++	if (IS_ERR(dev->anon_inode)) {
++		ret = PTR_ERR(dev->anon_inode);
++		DRM_ERROR("Cannot allocate anonymous inode: %d\n", ret);
++		goto err_free;
++	}
++
++	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
++		ret = drm_minor_alloc(dev, DRM_MINOR_CONTROL);
++		if (ret)
++			goto err_minors;
++	}
++
++	if (drm_core_check_feature(dev, DRIVER_RENDER)) {
++		ret = drm_minor_alloc(dev, DRM_MINOR_RENDER);
++		if (ret)
++			goto err_minors;
++	}
++
++	ret = drm_minor_alloc(dev, DRM_MINOR_LEGACY);
++	if (ret)
++		goto err_minors;
++
++	if (drm_ht_create(&dev->map_hash, 12))
++		goto err_minors;
++
++	ret = drm_legacy_ctxbitmap_init(dev);
++	if (ret) {
++		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
++		goto err_ht;
++	}
++
++	if (drm_core_check_feature(dev, DRIVER_GEM)) {
++		ret = drm_gem_init(dev);
++		if (ret) {
++			DRM_ERROR("Cannot initialize graphics execution manager (GEM)\n");
++			goto err_ctxbitmap;
++		}
++	}
++
++	return dev;
++
++err_ctxbitmap:
++	drm_legacy_ctxbitmap_cleanup(dev);
++err_ht:
++	drm_ht_remove(&dev->map_hash);
++err_minors:
++	drm_minor_free(dev, DRM_MINOR_LEGACY);
++	drm_minor_free(dev, DRM_MINOR_RENDER);
++	drm_minor_free(dev, DRM_MINOR_CONTROL);
++	drm_fs_inode_free(dev->anon_inode);
++err_free:
++	mutex_destroy(&dev->master_mutex);
++	kfree(dev);
++	return NULL;
++}
++EXPORT_SYMBOL(drm_dev_alloc);
++
++static void drm_dev_release(struct kref *ref)
++{
++	struct drm_device *dev = container_of(ref, struct drm_device, ref);
++
++	if (drm_core_check_feature(dev, DRIVER_GEM))
++		drm_gem_destroy(dev);
++
++	drm_legacy_ctxbitmap_cleanup(dev);
++	drm_ht_remove(&dev->map_hash);
++	drm_fs_inode_free(dev->anon_inode);
++
++	drm_minor_free(dev, DRM_MINOR_LEGACY);
++	drm_minor_free(dev, DRM_MINOR_RENDER);
++	drm_minor_free(dev, DRM_MINOR_CONTROL);
++
++	mutex_destroy(&dev->master_mutex);
++	kfree(dev->unique);
++	kfree(dev);
++}
++
++/**
++ * drm_dev_ref - Take reference of a DRM device
++ * @dev: device to take reference of or NULL
++ *
++ * This increases the ref-count of @dev by one. You *must* already own a
++ * reference when calling this. Use drm_dev_unref() to drop this reference
++ * again.
++ *
++ * This function never fails. However, this function does not provide *any*
++ * guarantee whether the device is alive or running. It only provides a
++ * reference to the object and the memory associated with it.
++ */
++void drm_dev_ref(struct drm_device *dev)
++{
++	if (dev)
++		kref_get(&dev->ref);
++}
++EXPORT_SYMBOL(drm_dev_ref);
++
++/**
++ * drm_dev_unref - Drop reference of a DRM device
++ * @dev: device to drop reference of or NULL
++ *
++ * This decreases the ref-count of @dev by one. The device is destroyed if the
++ * ref-count drops to zero.
++ */
++void drm_dev_unref(struct drm_device *dev)
++{
++	if (dev)
++		kref_put(&dev->ref, drm_dev_release);
++}
++EXPORT_SYMBOL(drm_dev_unref);
++
++/**
++ * drm_dev_register - Register DRM device
++ * @dev: Device to register
++ * @flags: Flags passed to the driver's .load() function
++ *
++ * Register the DRM device @dev with the system, advertise device to user-space
++ * and start normal device operation. @dev must be allocated via drm_dev_alloc()
++ * previously.
++ *
++ * Never call this twice on any device!
++ *
++ * RETURNS:
++ * 0 on success, negative error code on failure.
++ */
++int drm_dev_register(struct drm_device *dev, unsigned long flags)
++{
++	int ret;
++
++	mutex_lock(&drm_global_mutex);
++
++	ret = drm_minor_register(dev, DRM_MINOR_CONTROL);
++	if (ret)
++		goto err_minors;
++
++	ret = drm_minor_register(dev, DRM_MINOR_RENDER);
++	if (ret)
++		goto err_minors;
++
++	ret = drm_minor_register(dev, DRM_MINOR_LEGACY);
++	if (ret)
++		goto err_minors;
++
++	if (dev->driver->load) {
++		ret = dev->driver->load(dev, flags);
++		if (ret)
++			goto err_minors;
++	}
++
++	/* setup grouping for legacy outputs */
++	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
++		ret = drm_mode_group_init_legacy_group(dev,
++				&dev->primary->mode_group);
++		if (ret)
++			goto err_unload;
++	}
++
++	ret = 0;
++	goto out_unlock;
++
++err_unload:
++	if (dev->driver->unload)
++		dev->driver->unload(dev);
++err_minors:
++	drm_minor_unregister(dev, DRM_MINOR_LEGACY);
++	drm_minor_unregister(dev, DRM_MINOR_RENDER);
++	drm_minor_unregister(dev, DRM_MINOR_CONTROL);
++out_unlock:
++	mutex_unlock(&drm_global_mutex);
++	return ret;
++}
++EXPORT_SYMBOL(drm_dev_register);
++
++/**
++ * drm_dev_unregister - Unregister DRM device
++ * @dev: Device to unregister
++ *
++ * Unregister the DRM device from the system. This does the reverse of
++ * drm_dev_register() but does not deallocate the device. The caller must call
++ * drm_dev_unref() to drop their final reference.
++ */
++void drm_dev_unregister(struct drm_device *dev)
++{
++	struct drm_map_list *r_list, *list_temp;
++
++	drm_lastclose(dev);
++
++	if (dev->driver->unload)
++		dev->driver->unload(dev);
++
++	if (dev->agp)
++		drm_pci_agp_destroy(dev);
++
++	drm_vblank_cleanup(dev);
++
++	list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
++		drm_legacy_rmmap(dev, r_list->map);
++
++	drm_minor_unregister(dev, DRM_MINOR_LEGACY);
++	drm_minor_unregister(dev, DRM_MINOR_RENDER);
++	drm_minor_unregister(dev, DRM_MINOR_CONTROL);
++}
++EXPORT_SYMBOL(drm_dev_unregister);
++
++/**
++ * drm_dev_set_unique - Set the unique name of a DRM device
++ * @dev: device of which to set the unique name
++ * @fmt: format string for unique name
++ *
++ * Sets the unique name of a DRM device using the specified format string and
++ * a variable list of arguments. Drivers can use this at driver probe time if
++ * the unique name of the devices they drive is static.
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int drm_dev_set_unique(struct drm_device *dev, const char *fmt, ...)
++{
++	va_list ap;
++
++	kfree(dev->unique);
++
++	va_start(ap, fmt);
++	dev->unique = kvasprintf(GFP_KERNEL, fmt, ap);
++	va_end(ap);
++
++	return dev->unique ? 0 : -ENOMEM;
++}
++EXPORT_SYMBOL(drm_dev_set_unique);
++
++/*
++ * DRM Core
++ * The DRM core module initializes all global DRM objects and makes them
++ * available to drivers. Once setup, drivers can probe their respective
++ * devices.
++ * Currently, core management includes:
++ *  - The "DRM-Global" key/value database
++ *  - Global ID management for connectors
++ *  - DRM major number allocation
++ *  - DRM minor management
++ *  - DRM sysfs class
++ *  - DRM debugfs root
++ *
++ * Furthermore, the DRM core provides dynamic char-dev lookups. For each
++ * interface registered on a DRM device, you can request minor numbers from DRM
++ * core. DRM core takes care of major-number management and char-dev
++ * registration. A stub ->open() callback forwards any open() requests to the
++ * registered minor.
++ */
++
++static int drm_stub_open(struct inode *inode, struct file *filp)
++{
++	const struct file_operations *new_fops;
++	struct drm_minor *minor;
++	int err;
++
++	DRM_DEBUG("\n");
++
++	mutex_lock(&drm_global_mutex);
++	minor = drm_minor_acquire(iminor(inode));
++	if (IS_ERR(minor)) {
++		err = PTR_ERR(minor);
++		goto out_unlock;
++	}
++
++	new_fops = fops_get(minor->dev->driver->fops);
++	if (!new_fops) {
++		err = -ENODEV;
++		goto out_release;
++	}
++
++	replace_fops(filp, new_fops);
++	if (filp->f_op->open)
++		err = filp->f_op->open(inode, filp);
++	else
++		err = 0;
++
++out_release:
++	drm_minor_release(minor);
++out_unlock:
++	mutex_unlock(&drm_global_mutex);
++	return err;
++}
+ 
+-/** File operations structure */
+ static const struct file_operations drm_stub_fops = {
+ 	.owner = THIS_MODULE,
+ 	.open = drm_stub_open,
+@@ -229,186 +906,3 @@
+ 
+ module_init(drm_core_init);
+ module_exit(drm_core_exit);
+-
+-/**
+- * Copy and IOCTL return string to user space
+- */
+-static int drm_copy_field(char *buf, size_t *buf_len, const char *value)
+-{
+-	int len;
+-
+-	/* don't overflow userbuf */
+-	len = strlen(value);
+-	if (len > *buf_len)
+-		len = *buf_len;
+-
+-	/* let userspace know exact length of driver value (which could be
+-	 * larger than the userspace-supplied buffer) */
+-	*buf_len = strlen(value);
+-
+-	/* finally, try filling in the userbuf */
+-	if (len && buf)
+-		if (copy_to_user(buf, value, len))
+-			return -EFAULT;
+-	return 0;
+-}
+-
+-/**
+- * Get version information
+- *
+- * \param inode device inode.
+- * \param filp file pointer.
+- * \param cmd command.
+- * \param arg user argument, pointing to a drm_version structure.
+- * \return zero on success or negative number on failure.
+- *
+- * Fills in the version information in \p arg.
+- */
+-static int drm_version(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv)
+-{
+-	struct drm_version *version = data;
+-	int err;
+-
+-	version->version_major = dev->driver->major;
+-	version->version_minor = dev->driver->minor;
+-	version->version_patchlevel = dev->driver->patchlevel;
+-	err = drm_copy_field(version->name, &version->name_len,
+-			dev->driver->name);
+-	if (!err)
+-		err = drm_copy_field(version->date, &version->date_len,
+-				dev->driver->date);
+-	if (!err)
+-		err = drm_copy_field(version->desc, &version->desc_len,
+-				dev->driver->desc);
+-
+-	return err;
+-}
+-
+-/**
+- * Called whenever a process performs an ioctl on /dev/drm.
+- *
+- * \param inode device inode.
+- * \param file_priv DRM file private.
+- * \param cmd command.
+- * \param arg user argument.
+- * \return zero on success or negative number on failure.
+- *
+- * Looks up the ioctl function in the ::ioctls table, checking for root
+- * previleges if so required, and dispatches to the respective function.
+- */
+-long drm_ioctl(struct file *filp,
+-	      unsigned int cmd, unsigned long arg)
+-{
+-	struct drm_file *file_priv = filp->private_data;
+-	struct drm_device *dev;
+-	const struct drm_ioctl_desc *ioctl = NULL;
+-	drm_ioctl_t *func;
+-	unsigned int nr = DRM_IOCTL_NR(cmd);
+-	int retcode = -EINVAL;
+-	char stack_kdata[128];
+-	char *kdata = NULL;
+-	unsigned int usize, asize;
+-
+-	dev = file_priv->minor->dev;
+-
+-	if (drm_device_is_unplugged(dev))
+-		return -ENODEV;
+-
+-	if ((nr >= DRM_CORE_IOCTL_COUNT) &&
+-	    ((nr < DRM_COMMAND_BASE) || (nr >= DRM_COMMAND_END)))
+-		goto err_i1;
+-	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
+-	    (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
+-		u32 drv_size;
+-		ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
+-		drv_size = _IOC_SIZE(ioctl->cmd_drv);
+-		usize = asize = _IOC_SIZE(cmd);
+-		if (drv_size > asize)
+-			asize = drv_size;
+-		cmd = ioctl->cmd_drv;
+-	}
+-	else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
+-		u32 drv_size;
+-
+-		ioctl = &drm_ioctls[nr];
+-
+-		drv_size = _IOC_SIZE(ioctl->cmd);
+-		usize = asize = _IOC_SIZE(cmd);
+-		if (drv_size > asize)
+-			asize = drv_size;
+-
+-		cmd = ioctl->cmd;
+-	} else
+-		goto err_i1;
+-
+-	DRM_DEBUG("pid=%d, dev=0x%lx, auth=%d, %s\n",
+-		  task_pid_nr(current),
+-		  (long)old_encode_dev(file_priv->minor->device),
+-		  file_priv->authenticated, ioctl->name);
+-
+-	/* Do not trust userspace, use our own definition */
+-	func = ioctl->func;
+-
+-	if (!func) {
+-		DRM_DEBUG("no function\n");
+-		retcode = -EINVAL;
+-	} else if (((ioctl->flags & DRM_ROOT_ONLY) && !capable(CAP_SYS_ADMIN)) ||
+-		   ((ioctl->flags & DRM_AUTH) && !drm_is_render_client(file_priv) && !file_priv->authenticated) ||
+-		   ((ioctl->flags & DRM_MASTER) && !file_priv->is_master) ||
+-		   (!(ioctl->flags & DRM_CONTROL_ALLOW) && (file_priv->minor->type == DRM_MINOR_CONTROL)) ||
+-		   (!(ioctl->flags & DRM_RENDER_ALLOW) && drm_is_render_client(file_priv))) {
+-		retcode = -EACCES;
+-	} else {
+-		if (cmd & (IOC_IN | IOC_OUT)) {
+-			if (asize <= sizeof(stack_kdata)) {
+-				kdata = stack_kdata;
+-			} else {
+-				kdata = kmalloc(asize, GFP_KERNEL);
+-				if (!kdata) {
+-					retcode = -ENOMEM;
+-					goto err_i1;
+-				}
+-			}
+-			if (asize > usize)
+-				memset(kdata + usize, 0, asize - usize);
+-		}
+-
+-		if (cmd & IOC_IN) {
+-			if (copy_from_user(kdata, (void __user *)arg,
+-					   usize) != 0) {
+-				retcode = -EFAULT;
+-				goto err_i1;
+-			}
+-		} else
+-			memset(kdata, 0, usize);
+-
+-		if (ioctl->flags & DRM_UNLOCKED)
+-			retcode = func(dev, kdata, file_priv);
+-		else {
+-			mutex_lock(&drm_global_mutex);
+-			retcode = func(dev, kdata, file_priv);
+-			mutex_unlock(&drm_global_mutex);
+-		}
+-
+-		if (cmd & IOC_OUT) {
+-			if (copy_to_user((void __user *)arg, kdata,
+-					 usize) != 0)
+-				retcode = -EFAULT;
+-		}
+-	}
+-
+-      err_i1:
+-	if (!ioctl)
+-		DRM_DEBUG("invalid ioctl: pid=%d, dev=0x%lx, auth=%d, cmd=0x%02x, nr=0x%02x\n",
+-			  task_pid_nr(current),
+-			  (long)old_encode_dev(file_priv->minor->device),
+-			  file_priv->authenticated, cmd, nr);
+-
+-	if (kdata != stack_kdata)
+-		kfree(kdata);
+-	if (retcode)
+-		DRM_DEBUG("ret = %d\n", retcode);
+-	return retcode;
+-}
+-EXPORT_SYMBOL(drm_ioctl);
+diff -Naur a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
+--- a/drivers/gpu/drm/drm_edid.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/drm_edid.c	2015-03-26 14:42:38.722435422 +0530
+@@ -34,6 +34,7 @@
+ #include <linux/module.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_edid.h>
++#include <drm/drm_displayid.h>
+ 
+ #define version_greater(edid, maj, min) \
+ 	(((edid)->version > (maj)) || \
+@@ -70,6 +71,8 @@
+ #define EDID_QUIRK_FORCE_REDUCED_BLANKING	(1 << 7)
+ /* Force 8bpc */
+ #define EDID_QUIRK_FORCE_8BPC			(1 << 8)
++/* Force 12bpc */
++#define EDID_QUIRK_FORCE_12BPC			(1 << 9)
+ 
+ struct detailed_mode_closure {
+ 	struct drm_connector *connector;
+@@ -125,6 +128,9 @@
+ 	{ "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
+ 	{ "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
+ 
++	/* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
++	{ "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
++
+ 	/* ViewSonic VA2026w */
+ 	{ "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
+ 
+@@ -627,27 +633,27 @@
+ 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE),
+ 	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 6 - 1440x480i@60Hz */
+-	{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+-		   1602, 1716, 0, 480, 488, 494, 525, 0,
++	/* 6 - 720(1440)x480i@60Hz */
++	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
++		   801, 858, 0, 480, 488, 494, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 7 - 1440x480i@60Hz */
+-	{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+-		   1602, 1716, 0, 480, 488, 494, 525, 0,
++	/* 7 - 720(1440)x480i@60Hz */
++	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
++		   801, 858, 0, 480, 488, 494, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 8 - 1440x240@60Hz */
+-	{ DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+-		   1602, 1716, 0, 240, 244, 247, 262, 0,
++	/* 8 - 720(1440)x240@60Hz */
++	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
++		   801, 858, 0, 240, 244, 247, 262, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 9 - 1440x240@60Hz */
+-	{ DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
+-		   1602, 1716, 0, 240, 244, 247, 262, 0,
++	/* 9 - 720(1440)x240@60Hz */
++	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
++		   801, 858, 0, 240, 244, 247, 262, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+@@ -709,27 +715,27 @@
+ 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE),
+ 	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 21 - 1440x576i@50Hz */
+-	{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+-		   1590, 1728, 0, 576, 580, 586, 625, 0,
++	/* 21 - 720(1440)x576i@50Hz */
++	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
++		   795, 864, 0, 576, 580, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 22 - 1440x576i@50Hz */
+-	{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+-		   1590, 1728, 0, 576, 580, 586, 625, 0,
++	/* 22 - 720(1440)x576i@50Hz */
++	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
++		   795, 864, 0, 576, 580, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 23 - 1440x288@50Hz */
+-	{ DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+-		   1590, 1728, 0, 288, 290, 293, 312, 0,
++	/* 23 - 720(1440)x288@50Hz */
++	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
++		   795, 864, 0, 288, 290, 293, 312, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 24 - 1440x288@50Hz */
+-	{ DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
+-		   1590, 1728, 0, 288, 290, 293, 312, 0,
++	/* 24 - 720(1440)x288@50Hz */
++	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
++		   795, 864, 0, 288, 290, 293, 312, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+@@ -832,17 +838,17 @@
+ 		   796, 864, 0, 576, 581, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ 	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 44 - 1440x576i@100Hz */
+-	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
+-		   1590, 1728, 0, 576, 580, 586, 625, 0,
++	/* 44 - 720(1440)x576i@100Hz */
++	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
++		   795, 864, 0, 576, 580, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+-			DRM_MODE_FLAG_DBLCLK),
++			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 45 - 1440x576i@100Hz */
+-	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
+-		   1590, 1728, 0, 576, 580, 586, 625, 0,
++	/* 45 - 720(1440)x576i@100Hz */
++	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
++		   795, 864, 0, 576, 580, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+-			DRM_MODE_FLAG_DBLCLK),
++			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ 	/* 46 - 1920x1080i@120Hz */
+ 	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
+@@ -865,15 +871,15 @@
+ 		   798, 858, 0, 480, 489, 495, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ 	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 50 - 1440x480i@120Hz */
+-	{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
+-		   1602, 1716, 0, 480, 488, 494, 525, 0,
++	/* 50 - 720(1440)x480i@120Hz */
++	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
++		   801, 858, 0, 480, 488, 494, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 51 - 1440x480i@120Hz */
+-	{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
+-		   1602, 1716, 0, 480, 488, 494, 525, 0,
++	/* 51 - 720(1440)x480i@120Hz */
++	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
++		   801, 858, 0, 480, 488, 494, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+@@ -887,15 +893,15 @@
+ 		   796, 864, 0, 576, 581, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ 	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 54 - 1440x576i@200Hz */
+-	{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
+-		   1590, 1728, 0, 576, 580, 586, 625, 0,
++	/* 54 - 720(1440)x576i@200Hz */
++	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
++		   795, 864, 0, 576, 580, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 55 - 1440x576i@200Hz */
+-	{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
+-		   1590, 1728, 0, 576, 580, 586, 625, 0,
++	/* 55 - 720(1440)x576i@200Hz */
++	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
++		   795, 864, 0, 576, 580, 586, 625, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+@@ -909,15 +915,15 @@
+ 		   798, 858, 0, 480, 489, 495, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ 	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+-	/* 58 - 1440x480i@240 */
+-	{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
+-		   1602, 1716, 0, 480, 488, 494, 525, 0,
++	/* 58 - 720(1440)x480i@240 */
++	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
++		   801, 858, 0, 480, 488, 494, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
+-	/* 59 - 1440x480i@240 */
+-	{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
+-		   1602, 1716, 0, 480, 488, 494, 525, 0,
++	/* 59 - 720(1440)x480i@240 */
++	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
++		   801, 858, 0, 480, 488, 494, 525, 0,
+ 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
+ 			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ 	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+@@ -984,9 +990,13 @@
+ 	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
+ };
+ 
+- /*
+- * Sanity check the header of the base EDID block.  Return 8 if the header
+- * is perfect, down to 0 if it's totally wrong.
++/**
++ * drm_edid_header_is_valid - sanity check the header of the base EDID block
++ * @raw_edid: pointer to raw base EDID block
++ *
++ * Sanity check the header of the base EDID block.
++ *
++ * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
+  */
+ int drm_edid_header_is_valid(const u8 *raw_edid)
+ {
+@@ -1005,14 +1015,41 @@
+ MODULE_PARM_DESC(edid_fixup,
+ 		 "Minimum number of valid EDID header bytes (0-8, default 6)");
+ 
+-/*
+- * Sanity check the EDID block (base or extension).  Return 0 if the block
+- * doesn't check out, or 1 if it's valid.
+- */
+-bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
++static void drm_get_displayid(struct drm_connector *connector,
++			      struct edid *edid);
++
++static int drm_edid_block_checksum(const u8 *raw_edid)
+ {
+ 	int i;
+ 	u8 csum = 0;
++	for (i = 0; i < EDID_LENGTH; i++)
++		csum += raw_edid[i];
++
++	return csum;
++}
++
++static bool drm_edid_is_zero(const u8 *in_edid, int length)
++{
++	if (memchr_inv(in_edid, 0, length))
++		return false;
++
++	return true;
++}
++
++/**
++ * drm_edid_block_valid - Sanity check the EDID block (base or extension)
++ * @raw_edid: pointer to raw EDID block
++ * @block: type of block to validate (0 for base, extension otherwise)
++ * @print_bad_edid: if true, dump bad EDID blocks to the console
++ *
++ * Validate a base or extension EDID block and optionally dump bad blocks to
++ * the console.
++ *
++ * Return: True if the block is valid, false otherwise.
++ */
++bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
++{
++	u8 csum;
+ 	struct edid *edid = (struct edid *)raw_edid;
+ 
+ 	if (WARN_ON(!raw_edid))
+@@ -1032,8 +1069,7 @@
+ 		}
+ 	}
+ 
+-	for (i = 0; i < EDID_LENGTH; i++)
+-		csum += raw_edid[i];
++	csum = drm_edid_block_checksum(raw_edid);
+ 	if (csum) {
+ 		if (print_bad_edid) {
+ 			DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
+@@ -1064,9 +1100,13 @@
+ 
+ bad:
+ 	if (print_bad_edid) {
+-		printk(KERN_ERR "Raw EDID:\n");
+-		print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
++		if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
++			printk(KERN_ERR "EDID block is all zeroes\n");
++		} else {
++			printk(KERN_ERR "Raw EDID:\n");
++			print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
+ 			       raw_edid, EDID_LENGTH, false);
++		}
+ 	}
+ 	return false;
+ }
+@@ -1077,6 +1117,8 @@
+  * @edid: EDID data
+  *
+  * Sanity-check an entire EDID record (including extensions)
++ *
++ * Return: True if the EDID data is valid, false otherwise.
+  */
+ bool drm_edid_is_valid(struct edid *edid)
+ {
+@@ -1096,25 +1138,27 @@
+ 
+ #define DDC_SEGMENT_ADDR 0x30
+ /**
+- * Get EDID information via I2C.
++ * drm_do_probe_ddc_edid() - get EDID information via I2C
++ * @data: I2C device adapter
++ * @buf: EDID data buffer to be filled
++ * @block: 128 byte EDID block to start fetching from
++ * @len: EDID data buffer length to fetch
+  *
+- * \param adapter : i2c device adaptor
+- * \param buf     : EDID data buffer to be filled
+- * \param len     : EDID data buffer length
+- * \return 0 on success or -1 on failure.
++ * Try to fetch EDID information by calling I2C driver functions.
+  *
+- * Try to fetch EDID information by calling i2c driver function.
++ * Return: 0 on success or -1 on failure.
+  */
+ static int
+-drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
+-		      int block, int len)
++drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
+ {
++	struct i2c_adapter *adapter = data;
+ 	unsigned char start = block * EDID_LENGTH;
+ 	unsigned char segment = block >> 1;
+ 	unsigned char xfers = segment ? 3 : 2;
+ 	int ret, retries = 5;
+ 
+-	/* The core i2c driver will automatically retry the transfer if the
++	/*
++	 * The core I2C driver will automatically retry the transfer if the
+ 	 * adapter reports EAGAIN. However, we find that bit-banging transfers
+ 	 * are susceptible to errors under a heavily loaded machine and
+ 	 * generate spurious NAKs and timeouts. Retrying the transfer
+@@ -1140,10 +1184,10 @@
+ 			}
+ 		};
+ 
+-	/*
+-	 * Avoid sending the segment addr to not upset non-compliant ddc
+-	 * monitors.
+-	 */
++		/*
++		 * Avoid sending the segment addr to not upset non-compliant
++		 * DDC monitors.
++		 */
+ 		ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
+ 
+ 		if (ret == -ENXIO) {
+@@ -1156,16 +1200,26 @@
+ 	return ret == xfers ? 0 : -1;
+ }
+ 
+-static bool drm_edid_is_zero(u8 *in_edid, int length)
+-{
+-	if (memchr_inv(in_edid, 0, length))
+-		return false;
+-
+-	return true;
+-}
+-
+-static u8 *
+-drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
++/**
++ * drm_do_get_edid - get EDID data using a custom EDID block read function
++ * @connector: connector we're probing
++ * @get_edid_block: EDID block read function
++ * @data: private data passed to the block read function
++ *
++ * When the I2C adapter connected to the DDC bus is hidden behind a device that
++ * exposes a different interface to read EDID blocks this function can be used
++ * to get EDID data using a custom block read function.
++ *
++ * As in the general case the DDC bus is accessible by the kernel at the I2C
++ * level, drivers must make all reasonable efforts to expose it as an I2C
++ * adapter and use drm_get_edid() instead of abusing this function.
++ *
++ * Return: Pointer to valid EDID or NULL if we couldn't find any.
++ */
++struct edid *drm_do_get_edid(struct drm_connector *connector,
++	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
++			      size_t len),
++	void *data)
+ {
+ 	int i, j = 0, valid_extensions = 0;
+ 	u8 *block, *new;
+@@ -1176,7 +1230,7 @@
+ 
+ 	/* base block fetch */
+ 	for (i = 0; i < 4; i++) {
+-		if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
++		if (get_edid_block(data, block, 0, EDID_LENGTH))
+ 			goto out;
+ 		if (drm_edid_block_valid(block, 0, print_bad_edid))
+ 			break;
+@@ -1190,7 +1244,7 @@
+ 
+ 	/* if there's no extensions, we're done */
+ 	if (block[0x7e] == 0)
+-		return block;
++		return (struct edid *)block;
+ 
+ 	new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
+ 	if (!new)
+@@ -1199,7 +1253,7 @@
+ 
+ 	for (j = 1; j <= block[0x7e]; j++) {
+ 		for (i = 0; i < 4; i++) {
+-			if (drm_do_probe_ddc_edid(adapter,
++			if (get_edid_block(data,
+ 				  block + (valid_extensions + 1) * EDID_LENGTH,
+ 				  j, EDID_LENGTH))
+ 				goto out;
+@@ -1212,7 +1266,7 @@
+ 		if (i == 4 && print_bad_edid) {
+ 			dev_warn(connector->dev->dev,
+ 			 "%s: Ignoring invalid EDID block %d.\n",
+-			 drm_get_connector_name(connector), j);
++			 connector->name, j);
+ 
+ 			connector->bad_edid_counter++;
+ 		}
+@@ -1227,12 +1281,12 @@
+ 		block = new;
+ 	}
+ 
+-	return block;
++	return (struct edid *)block;
+ 
+ carp:
+ 	if (print_bad_edid) {
+ 		dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
+-			 drm_get_connector_name(connector), j);
++			 connector->name, j);
+ 	}
+ 	connector->bad_edid_counter++;
+ 
+@@ -1240,12 +1294,13 @@
+ 	kfree(block);
+ 	return NULL;
+ }
++EXPORT_SYMBOL_GPL(drm_do_get_edid);
+ 
+ /**
+- * Probe DDC presence.
++ * drm_probe_ddc() - probe DDC presence
++ * @adapter: I2C adapter to probe
+  *
+- * \param adapter : i2c device adaptor
+- * \return 1 on success
++ * Return: True on success, false on failure.
+  */
+ bool
+ drm_probe_ddc(struct i2c_adapter *adapter)
+@@ -1259,21 +1314,24 @@
+ /**
+  * drm_get_edid - get EDID data, if available
+  * @connector: connector we're probing
+- * @adapter: i2c adapter to use for DDC
++ * @adapter: I2C adapter to use for DDC
+  *
+- * Poke the given i2c channel to grab EDID data if possible.  If found,
++ * Poke the given I2C channel to grab EDID data if possible.  If found,
+  * attach it to the connector.
+  *
+- * Return edid data or NULL if we couldn't find any.
++ * Return: Pointer to valid EDID or NULL if we couldn't find any.
+  */
+ struct edid *drm_get_edid(struct drm_connector *connector,
+ 			  struct i2c_adapter *adapter)
+ {
+-	struct edid *edid = NULL;
++	struct edid *edid;
+ 
+-	if (drm_probe_ddc(adapter))
+-		edid = (struct edid *)drm_do_get_edid(connector, adapter);
++	if (!drm_probe_ddc(adapter))
++		return NULL;
+ 
++	edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
++	if (edid)
++		drm_get_displayid(connector, edid);
+ 	return edid;
+ }
+ EXPORT_SYMBOL(drm_get_edid);
+@@ -1282,7 +1340,7 @@
+  * drm_edid_duplicate - duplicate an EDID and the extensions
+  * @edid: EDID to duplicate
+  *
+- * Return duplicate edid or NULL on allocation failure.
++ * Return: Pointer to duplicated EDID or NULL on allocation failure.
+  */
+ struct edid *drm_edid_duplicate(const struct edid *edid)
+ {
+@@ -1405,7 +1463,8 @@
+  * @rb: Mode reduced-blanking-ness
+  *
+  * Walk the DMT mode list looking for a match for the given parameters.
+- * Return a newly allocated copy of the mode, or NULL if not found.
++ *
++ * Return: A newly allocated copy of the mode, or NULL if not found.
+  */
+ struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
+ 					   int hsize, int vsize, int fresh,
+@@ -1586,15 +1645,16 @@
+ 
+ /**
+  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
++ * @connector: connector of for the EDID block
++ * @edid: EDID block to scan
+  * @t: standard timing params
+- * @timing_level: standard timing level
+  *
+  * Take the standard timing params (in this case width, aspect, and refresh)
+  * and convert them into a real mode using CVT/GTF/DMT.
+  */
+ static struct drm_display_mode *
+ drm_mode_std(struct drm_connector *connector, struct edid *edid,
+-	     struct std_timing *t, int revision)
++	     struct std_timing *t)
+ {
+ 	struct drm_device *dev = connector->dev;
+ 	struct drm_display_mode *m, *mode = NULL;
+@@ -1615,7 +1675,7 @@
+ 	vrefresh_rate = vfreq + 60;
+ 	/* the vdisplay is calculated based on the aspect ratio */
+ 	if (aspect_ratio == 0) {
+-		if (revision < 3)
++		if (edid->revision < 3)
+ 			vsize = hsize;
+ 		else
+ 			vsize = (hsize * 10) / 16;
+@@ -2081,7 +2141,8 @@
+ add_inferred_modes(struct drm_connector *connector, struct edid *edid)
+ {
+ 	struct detailed_mode_closure closure = {
+-		connector, edid, 0, 0, 0
++		.connector = connector,
++		.edid = edid,
+ 	};
+ 
+ 	if (version_greater(edid, 1, 0))
+@@ -2132,6 +2193,7 @@
+ 
+ /**
+  * add_established_modes - get est. modes from EDID and add them
++ * @connector: connector to add mode(s) to
+  * @edid: EDID block to scan
+  *
+  * Each EDID block contains a bitmap of the supported "established modes" list
+@@ -2146,7 +2208,8 @@
+ 		((edid->established_timings.mfg_rsvd & 0x80) << 9);
+ 	int i, modes = 0;
+ 	struct detailed_mode_closure closure = {
+-		connector, edid, 0, 0, 0
++		.connector = connector,
++		.edid = edid,
+ 	};
+ 
+ 	for (i = 0; i <= EDID_EST_TIMINGS; i++) {
+@@ -2182,8 +2245,7 @@
+ 			struct drm_display_mode *newmode;
+ 
+ 			std = &data->data.timings[i];
+-			newmode = drm_mode_std(connector, edid, std,
+-					       edid->revision);
++			newmode = drm_mode_std(connector, edid, std);
+ 			if (newmode) {
+ 				drm_mode_probed_add(connector, newmode);
+ 				closure->modes++;
+@@ -2194,6 +2256,7 @@
+ 
+ /**
+  * add_standard_modes - get std. modes from EDID and add them
++ * @connector: connector to add mode(s) to
+  * @edid: EDID block to scan
+  *
+  * Standard modes can be calculated using the appropriate standard (DMT,
+@@ -2204,15 +2267,15 @@
+ {
+ 	int i, modes = 0;
+ 	struct detailed_mode_closure closure = {
+-		connector, edid, 0, 0, 0
++		.connector = connector,
++		.edid = edid,
+ 	};
+ 
+ 	for (i = 0; i < EDID_STD_TIMINGS; i++) {
+ 		struct drm_display_mode *newmode;
+ 
+ 		newmode = drm_mode_std(connector, edid,
+-				       &edid->standard_timings[i],
+-				       edid->revision);
++				       &edid->standard_timings[i]);
+ 		if (newmode) {
+ 			drm_mode_probed_add(connector, newmode);
+ 			modes++;
+@@ -2291,7 +2354,8 @@
+ add_cvt_modes(struct drm_connector *connector, struct edid *edid)
+ {	
+ 	struct detailed_mode_closure closure = {
+-		connector, edid, 0, 0, 0
++		.connector = connector,
++		.edid = edid,
+ 	};
+ 
+ 	if (version_greater(edid, 1, 2))
+@@ -2335,11 +2399,10 @@
+ 		   u32 quirks)
+ {
+ 	struct detailed_mode_closure closure = {
+-		connector,
+-		edid,
+-		1,
+-		quirks,
+-		0
++		.connector = connector,
++		.edid = edid,
++		.preferred = 1,
++		.quirks = quirks,
+ 	};
+ 
+ 	if (closure.preferred && !version_greater(edid, 1, 3))
+@@ -2364,7 +2427,7 @@
+ /*
+  * Search EDID for CEA extension block.
+  */
+-static u8 *drm_find_cea_extension(struct edid *edid)
++static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
+ {
+ 	u8 *edid_ext = NULL;
+ 	int i;
+@@ -2376,7 +2439,7 @@
+ 	/* Find CEA extension */
+ 	for (i = 0; i < edid->extensions; i++) {
+ 		edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
+-		if (edid_ext[0] == CEA_EXT)
++		if (edid_ext[0] == ext_id)
+ 			break;
+ 	}
+ 
+@@ -2386,6 +2449,16 @@
+ 	return edid_ext;
+ }
+ 
++static u8 *drm_find_cea_extension(struct edid *edid)
++{
++	return drm_find_edid_extension(edid, CEA_EXT);
++}
++
++static u8 *drm_find_displayid_extension(struct edid *edid)
++{
++	return drm_find_edid_extension(edid, DISPLAYID_EXT);
++}
++
+ /*
+  * Calculate the alternate clock for the CEA mode
+  * (60Hz vs. 59.94Hz etc.)
+@@ -2415,7 +2488,7 @@
+  * drm_match_cea_mode - look for a CEA mode matching given mode
+  * @to_match: display mode
+  *
+- * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
++ * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
+  * mode.
+  */
+ u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
+@@ -2442,6 +2515,22 @@
+ }
+ EXPORT_SYMBOL(drm_match_cea_mode);
+ 
++/**
++ * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
++ * the input VIC from the CEA mode list
++ * @video_code: ID given to each of the CEA modes
++ *
++ * Returns picture aspect ratio
++ */
++enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
++{
++	/* return picture aspect ratio for video_code - 1 to access the
++	 * right array element
++	*/
++	return edid_cea_modes[video_code-1].picture_aspect_ratio;
++}
++EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
++
+ /*
+  * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
+  * specific block).
+@@ -2580,6 +2669,9 @@
+ 		return NULL;
+ 
+ 	newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
++	if (!newmode)
++		return NULL;
++
+ 	newmode->vrefresh = 0;
+ 
+ 	return newmode;
+@@ -3010,11 +3102,9 @@
+  * @connector: connector corresponding to the HDMI/DP sink
+  * @edid: EDID to parse
+  *
+- * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver.
+- * Some ELD fields are left to the graphics driver caller:
+- * - Conn_Type
+- * - HDCP
+- * - Port_ID
++ * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
++ * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
++ * fill in.
+  */
+ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
+ {
+@@ -3086,9 +3176,12 @@
+ 		}
+ 	}
+ 	eld[5] |= sad_count << 4;
+-	eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
+ 
+-	DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);
++	eld[DRM_ELD_BASELINE_ELD_LEN] =
++		DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
++
++	DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
++		      drm_eld_size(eld), sad_count);
+ }
+ EXPORT_SYMBOL(drm_edid_to_eld);
+ 
+@@ -3098,9 +3191,10 @@
+  * @sads: pointer that will be set to the extracted SADs
+  *
+  * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
+- * Note: returned pointer needs to be kfreed
+  *
+- * Return number of found SADs or negative number on error.
++ * Note: The returned pointer needs to be freed using kfree().
++ *
++ * Return: The number of found SADs or negative number on error.
+  */
+ int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
+ {
+@@ -3157,9 +3251,11 @@
+  * @sadb: pointer to the speaker block
+  *
+  * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
+- * Note: returned pointer needs to be kfreed
+  *
+- * Return number of found Speaker Allocation Blocks or negative number on error.
++ * Note: The returned pointer needs to be freed using kfree().
++ *
++ * Return: The number of found Speaker Allocation Blocks or negative number on
++ * error.
+  */
+ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
+ {
+@@ -3191,10 +3287,9 @@
+ 
+ 			/* Speaker Allocation Data Block */
+ 			if (dbl == 3) {
+-				*sadb = kmalloc(dbl, GFP_KERNEL);
++				*sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
+ 				if (!*sadb)
+ 					return -ENOMEM;
+-				memcpy(*sadb, &db[1], dbl);
+ 				count = dbl;
+ 				break;
+ 			}
+@@ -3206,9 +3301,12 @@
+ EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
+ 
+ /**
+- * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond
++ * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
+  * @connector: connector associated with the HDMI/DP sink
+  * @mode: the display mode
++ *
++ * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
++ * the sink doesn't support audio or video.
+  */
+ int drm_av_sync_delay(struct drm_connector *connector,
+ 		      struct drm_display_mode *mode)
+@@ -3250,6 +3348,9 @@
+  *
+  * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
+  * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
++ *
++ * Return: The connector associated with the first HDMI/DP sink that has ELD
++ * attached to it.
+  */
+ struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
+ 				     struct drm_display_mode *mode)
+@@ -3257,6 +3358,9 @@
+ 	struct drm_connector *connector;
+ 	struct drm_device *dev = encoder->dev;
+ 
++	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
++	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
++
+ 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
+ 		if (connector->encoder == encoder && connector->eld[0])
+ 			return connector;
+@@ -3266,11 +3370,12 @@
+ EXPORT_SYMBOL(drm_select_eld);
+ 
+ /**
+- * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
++ * drm_detect_hdmi_monitor - detect whether monitor is HDMI
+  * @edid: monitor EDID information
+  *
+  * Parse the CEA extension according to CEA-861-B.
+- * Return true if HDMI, false if not or unknown.
++ *
++ * Return: True if the monitor is HDMI, false if not or unknown.
+  */
+ bool drm_detect_hdmi_monitor(struct edid *edid)
+ {
+@@ -3300,6 +3405,7 @@
+ 
+ /**
+  * drm_detect_monitor_audio - check monitor audio capability
++ * @edid: EDID block to scan
+  *
+  * Monitor should have CEA extension block.
+  * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
+@@ -3307,6 +3413,7 @@
+  * audio format, assume at least 'basic audio' support, even if 'basic
+  * audio' is not defined in EDID.
+  *
++ * Return: True if the monitor supports audio, false otherwise.
+  */
+ bool drm_detect_monitor_audio(struct edid *edid)
+ {
+@@ -3345,10 +3452,13 @@
+ 
+ /**
+  * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
++ * @edid: EDID block to scan
+  *
+  * Check whether the monitor reports the RGB quantization range selection
+  * as supported. The AVI infoframe can then be used to inform the monitor
+  * which quantization range (full or limited) is used.
++ *
++ * Return: True if the RGB quantization range is selectable, false otherwise.
+  */
+ bool drm_rgb_quant_range_selectable(struct edid *edid)
+ {
+@@ -3375,16 +3485,119 @@
+ EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
+ 
+ /**
++ * drm_assign_hdmi_deep_color_info - detect whether monitor supports
++ * hdmi deep color modes and update drm_display_info if so.
++ * @edid: monitor EDID information
++ * @info: Updated with maximum supported deep color bpc and color format
++ *        if deep color supported.
++ * @connector: DRM connector, used only for debug output
++ *
++ * Parse the CEA extension according to CEA-861-B.
++ * Return true if HDMI deep color supported, false if not or unknown.
++ */
++static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
++                                            struct drm_display_info *info,
++                                            struct drm_connector *connector)
++{
++	u8 *edid_ext, *hdmi;
++	int i;
++	int start_offset, end_offset;
++	unsigned int dc_bpc = 0;
++
++	edid_ext = drm_find_cea_extension(edid);
++	if (!edid_ext)
++		return false;
++
++	if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
++		return false;
++
++	/*
++	 * Because HDMI identifier is in Vendor Specific Block,
++	 * search it from all data blocks of CEA extension.
++	 */
++	for_each_cea_db(edid_ext, i, start_offset, end_offset) {
++		if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
++			/* HDMI supports at least 8 bpc */
++			info->bpc = 8;
++
++			hdmi = &edid_ext[i];
++			if (cea_db_payload_len(hdmi) < 6)
++				return false;
++
++			if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
++				dc_bpc = 10;
++				info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
++				DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
++						  connector->name);
++			}
++
++			if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
++				dc_bpc = 12;
++				info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
++				DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
++						  connector->name);
++			}
++
++			if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
++				dc_bpc = 16;
++				info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
++				DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
++						  connector->name);
++			}
++
++			if (dc_bpc > 0) {
++				DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
++						  connector->name, dc_bpc);
++				info->bpc = dc_bpc;
++
++				/*
++				 * Deep color support mandates RGB444 support for all video
++				 * modes and forbids YCRCB422 support for all video modes per
++				 * HDMI 1.3 spec.
++				 */
++				info->color_formats = DRM_COLOR_FORMAT_RGB444;
++
++				/* YCRCB444 is optional according to spec. */
++				if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
++					info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
++					DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
++							  connector->name);
++				}
++
++				/*
++				 * Spec says that if any deep color mode is supported at all,
++				 * then deep color 36 bit must be supported.
++				 */
++				if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
++					DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
++							  connector->name);
++				}
++
++				return true;
++			}
++			else {
++				DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
++						  connector->name);
++			}
++		}
++	}
++
++	return false;
++}
++
++/**
+  * drm_add_display_info - pull display info out if present
+  * @edid: EDID data
+  * @info: display info (attached to connector)
++ * @connector: connector whose edid is used to build display info
+  *
+  * Grab any available display info and stuff it into the drm_display_info
+  * structure that's part of the connector.  Useful for tracking bpp and
+  * color spaces.
+  */
+ static void drm_add_display_info(struct edid *edid,
+-				 struct drm_display_info *info)
++                                 struct drm_display_info *info,
++                                 struct drm_connector *connector)
+ {
+ 	u8 *edid_ext;
+ 
+@@ -3414,6 +3627,9 @@
+ 			info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
+ 	}
+ 
++	/* HDMI deep color modes supported? Assign to info, if so */
++	drm_assign_hdmi_deep_color_info(edid, info, connector);
++
+ 	/* Only defined for 1.4 with digital displays */
+ 	if (edid->revision < 4)
+ 		return;
+@@ -3443,6 +3659,9 @@
+ 		break;
+ 	}
+ 
++	DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
++			  connector->name, info->bpc);
++
+ 	info->color_formats |= DRM_COLOR_FORMAT_RGB444;
+ 	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
+ 		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
+@@ -3453,11 +3672,11 @@
+ /**
+  * drm_add_edid_modes - add modes from EDID data, if available
+  * @connector: connector we're probing
+- * @edid: edid data
++ * @edid: EDID data
+  *
+  * Add the specified modes to the connector's mode list.
+  *
+- * Return number of modes added or 0 if we couldn't find any.
++ * Return: The number of modes added or 0 if we couldn't find any.
+  */
+ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
+ {
+@@ -3469,7 +3688,7 @@
+ 	}
+ 	if (!drm_edid_is_valid(edid)) {
+ 		dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
+-			 drm_get_connector_name(connector));
++			 connector->name);
+ 		return 0;
+ 	}
+ 
+@@ -3501,11 +3720,14 @@
+ 	if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
+ 		edid_fixup_preferred(connector, quirks);
+ 
+-	drm_add_display_info(edid, &connector->display_info);
++	drm_add_display_info(edid, &connector->display_info, connector);
+ 
+ 	if (quirks & EDID_QUIRK_FORCE_8BPC)
+ 		connector->display_info.bpc = 8;
+ 
++	if (quirks & EDID_QUIRK_FORCE_12BPC)
++		connector->display_info.bpc = 12;
++
+ 	return num_modes;
+ }
+ EXPORT_SYMBOL(drm_add_edid_modes);
+@@ -3519,7 +3741,7 @@
+  * Add the specified modes to the connector's mode list. Only when the
+  * hdisplay/vdisplay is not beyond the given limit, it will be added.
+  *
+- * Return number of modes added or 0 if we couldn't find any.
++ * Return: The number of modes added or 0 if we couldn't find any.
+  */
+ int drm_add_modes_noedid(struct drm_connector *connector,
+ 			int hdisplay, int vdisplay)
+@@ -3558,14 +3780,23 @@
+ }
+ EXPORT_SYMBOL(drm_add_modes_noedid);
+ 
++/**
++ * drm_set_preferred_mode - Sets the preferred mode of a connector
++ * @connector: connector whose mode list should be processed
++ * @hpref: horizontal resolution of preferred mode
++ * @vpref: vertical resolution of preferred mode
++ *
++ * Marks a mode as preferred if it matches the resolution specified by @hpref
++ * and @vpref.
++ */
+ void drm_set_preferred_mode(struct drm_connector *connector,
+ 			   int hpref, int vpref)
+ {
+ 	struct drm_display_mode *mode;
+ 
+ 	list_for_each_entry(mode, &connector->probed_modes, head) {
+-		if (drm_mode_width(mode)  == hpref &&
+-		    drm_mode_height(mode) == vpref)
++		if (mode->hdisplay == hpref &&
++		    mode->vdisplay == vpref)
+ 			mode->type |= DRM_MODE_TYPE_PREFERRED;
+ 	}
+ }
+@@ -3577,7 +3808,7 @@
+  * @frame: HDMI AVI infoframe
+  * @mode: DRM display mode
+  *
+- * Returns 0 on success or a negative error code on failure.
++ * Return: 0 on success or a negative error code on failure.
+  */
+ int
+ drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
+@@ -3598,7 +3829,20 @@
+ 	frame->video_code = drm_match_cea_mode(mode);
+ 
+ 	frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
++
++	/*
++	 * Populate picture aspect ratio from either
++	 * user input (if specified) or from the CEA mode list.
++	 */
++	if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
++		mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
++		frame->picture_aspect = mode->picture_aspect_ratio;
++	else if (frame->video_code > 0)
++		frame->picture_aspect = drm_get_cea_aspect_ratio(
++						frame->video_code);
++
+ 	frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
++	frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
+ 
+ 	return 0;
+ }
+@@ -3641,7 +3885,7 @@
+  * 4k or stereoscopic 3D mode. So when giving any other mode as input this
+  * function will return -EINVAL, error that can be safely ignored.
+  *
+- * Returns 0 on success or a negative error code on failure.
++ * Return: 0 on success or a negative error code on failure.
+  */
+ int
+ drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
+@@ -3675,3 +3919,123 @@
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
++
++static int drm_parse_display_id(struct drm_connector *connector,
++				u8 *displayid, int length,
++				bool is_edid_extension)
++{
++	/* if this is an EDID extension the first byte will be 0x70 */
++	int idx = 0;
++	struct displayid_hdr *base;
++	struct displayid_block *block;
++	u8 csum = 0;
++	int i;
++
++	if (is_edid_extension)
++		idx = 1;
++
++	base = (struct displayid_hdr *)&displayid[idx];
++
++	DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
++		      base->rev, base->bytes, base->prod_id, base->ext_count);
++
++	if (base->bytes + 5 > length - idx)
++		return -EINVAL;
++
++	for (i = idx; i <= base->bytes + 5; i++) {
++		csum += displayid[i];
++	}
++	if (csum) {
++		DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
++		return -EINVAL;
++	}
++
++	block = (struct displayid_block *)&displayid[idx + 4];
++	DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
++		      block->tag, block->rev, block->num_bytes);
++
++	switch (block->tag) {
++	case DATA_BLOCK_TILED_DISPLAY: {
++		struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
++
++		u16 w, h;
++		u8 tile_v_loc, tile_h_loc;
++		u8 num_v_tile, num_h_tile;
++		struct drm_tile_group *tg;
++
++		w = tile->tile_size[0] | tile->tile_size[1] << 8;
++		h = tile->tile_size[2] | tile->tile_size[3] << 8;
++
++		num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
++		num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
++		tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
++		tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
++
++		connector->has_tile = true;
++		if (tile->tile_cap & 0x80)
++			connector->tile_is_single_monitor = true;
++
++		connector->num_h_tile = num_h_tile + 1;
++		connector->num_v_tile = num_v_tile + 1;
++		connector->tile_h_loc = tile_h_loc;
++		connector->tile_v_loc = tile_v_loc;
++		connector->tile_h_size = w + 1;
++		connector->tile_v_size = h + 1;
++
++		DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
++		DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
++		DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
++		       num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
++		DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
++
++		tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
++		if (!tg) {
++			tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
++		}
++		if (!tg)
++			return -ENOMEM;
++
++		if (connector->tile_group != tg) {
++			/* if we haven't got a pointer,
++			   take the reference, drop ref to old tile group */
++			if (connector->tile_group) {
++				drm_mode_put_tile_group(connector->dev, connector->tile_group);
++			}
++			connector->tile_group = tg;
++		} else
++			/* if same tile group, then release the ref we just took. */
++			drm_mode_put_tile_group(connector->dev, tg);
++	}
++		break;
++	default:
++		printk("unknown displayid tag %d\n", block->tag);
++		break;
++	}
++	return 0;
++}
++
++static void drm_get_displayid(struct drm_connector *connector,
++			      struct edid *edid)
++{
++	void *displayid = NULL;
++	int ret;
++	connector->has_tile = false;
++	displayid = drm_find_displayid_extension(edid);
++	if (!displayid) {
++		/* drop reference to any tile group we had */
++		goto out_drop_ref;
++	}
++
++	ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
++	if (ret < 0)
++		goto out_drop_ref;
++	if (!connector->has_tile)
++		goto out_drop_ref;
++	return;
++out_drop_ref:
++	if (connector->tile_group) {
++		drm_mode_put_tile_group(connector->dev, connector->tile_group);
++		connector->tile_group = NULL;
++	}
++	return;
++}
+diff -Naur a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
+--- a/drivers/gpu/drm/drm_edid_load.c	2015-03-26 14:43:30.398436435 +0530
++++ b/drivers/gpu/drm/drm_edid_load.c	2015-03-26 14:42:38.722435422 +0530
+@@ -31,8 +31,9 @@
+ MODULE_PARM_DESC(edid_firmware, "Do not probe monitor, use specified EDID blob "
+ 	"from built-in data or /lib/firmware instead. ");
+ 
+-#define GENERIC_EDIDS 5
++#define GENERIC_EDIDS 6
+ static const char *generic_edid_name[GENERIC_EDIDS] = {
++	"edid/800x600.bin",
+ 	"edid/1024x768.bin",
+ 	"edid/1280x1024.bin",
+ 	"edid/1600x1200.bin",
+@@ -44,6 +45,24 @@
+ 	{
+ 	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
+ 	0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++	0x05, 0x16, 0x01, 0x03, 0x6d, 0x1b, 0x14, 0x78,
++	0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
++	0x20, 0x50, 0x54, 0x01, 0x00, 0x00, 0x45, 0x40,
++	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
++	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xa0, 0x0f,
++	0x20, 0x00, 0x31, 0x58, 0x1c, 0x20, 0x28, 0x80,
++	0x14, 0x00, 0x15, 0xd0, 0x10, 0x00, 0x00, 0x1e,
++	0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
++	0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
++	0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
++	0x3d, 0x24, 0x26, 0x05, 0x00, 0x0a, 0x20, 0x20,
++	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
++	0x00, 0x4c, 0x69, 0x6e, 0x75, 0x78, 0x20, 0x53,
++	0x56, 0x47, 0x41, 0x0a, 0x20, 0x20, 0x00, 0xc2,
++	},
++	{
++	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
++	0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 	0x05, 0x16, 0x01, 0x03, 0x6d, 0x23, 0x1a, 0x78,
+ 	0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
+ 	0x20, 0x50, 0x54, 0x00, 0x08, 0x00, 0x61, 0x40,
+@@ -235,14 +254,13 @@
+ 	    name, connector_name);
+ 
+ out:
+-	if (fw)
+-		release_firmware(fw);
++	release_firmware(fw);
+ 	return edid;
+ }
+ 
+ int drm_load_edid_firmware(struct drm_connector *connector)
+ {
+-	const char *connector_name = drm_get_connector_name(connector);
++	const char *connector_name = connector->name;
+ 	char *edidname = edid_firmware, *last, *colon;
+ 	int ret;
+ 	struct edid *edid;
+diff -Naur a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
+--- a/drivers/gpu/drm/drm_fb_cma_helper.c	2015-03-26 14:43:30.398436435 +0530
++++ b/drivers/gpu/drm/drm_fb_cma_helper.c	2015-03-26 14:42:38.722435422 +0530
+@@ -327,7 +327,7 @@
+ 	return ret;
+ }
+ 
+-static struct drm_fb_helper_funcs drm_fb_cma_helper_funcs = {
++static const struct drm_fb_helper_funcs drm_fb_cma_helper_funcs = {
+ 	.fb_probe = drm_fbdev_cma_create,
+ };
+ 
+@@ -354,9 +354,10 @@
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+-	fbdev_cma->fb_helper.funcs = &drm_fb_cma_helper_funcs;
+ 	helper = &fbdev_cma->fb_helper;
+ 
++	drm_fb_helper_prepare(dev, helper, &drm_fb_cma_helper_funcs);
++
+ 	ret = drm_fb_helper_init(dev, helper, num_crtc, max_conn_count);
+ 	if (ret < 0) {
+ 		dev_err(dev->dev, "Failed to initialize drm fb helper.\n");
+@@ -429,13 +430,8 @@
+  */
+ void drm_fbdev_cma_restore_mode(struct drm_fbdev_cma *fbdev_cma)
+ {
+-	if (fbdev_cma) {
+-		struct drm_device *dev = fbdev_cma->fb_helper.dev;
+-
+-		drm_modeset_lock_all(dev);
+-		drm_fb_helper_restore_fbdev_mode(&fbdev_cma->fb_helper);
+-		drm_modeset_unlock_all(dev);
+-	}
++	if (fbdev_cma)
++		drm_fb_helper_restore_fbdev_mode_unlocked(&fbdev_cma->fb_helper);
+ }
+ EXPORT_SYMBOL_GPL(drm_fbdev_cma_restore_mode);
+ 
+diff -Naur a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
+--- a/drivers/gpu/drm/drm_fb_helper.c	2015-03-26 14:43:30.398436435 +0530
++++ b/drivers/gpu/drm/drm_fb_helper.c	2015-03-26 14:42:38.722435422 +0530
+@@ -45,24 +45,38 @@
+  * DOC: fbdev helpers
+  *
+  * The fb helper functions are useful to provide an fbdev on top of a drm kernel
+- * mode setting driver. They can be used mostly independantely from the crtc
++ * mode setting driver. They can be used mostly independently from the crtc
+  * helper functions used by many drivers to implement the kernel mode setting
+  * interfaces.
+  *
+- * Initialization is done as a three-step process with drm_fb_helper_init(),
+- * drm_fb_helper_single_add_all_connectors() and drm_fb_helper_initial_config().
+- * Drivers with fancier requirements than the default beheviour can override the
+- * second step with their own code.  Teardown is done with drm_fb_helper_fini().
++ * Initialization is done as a four-step process with drm_fb_helper_prepare(),
++ * drm_fb_helper_init(), drm_fb_helper_single_add_all_connectors() and
++ * drm_fb_helper_initial_config(). Drivers with fancier requirements than the
++ * default behaviour can override the third step with their own code.
++ * Teardown is done with drm_fb_helper_fini().
+  *
+  * At runtime drivers should restore the fbdev console by calling
+  * drm_fb_helper_restore_fbdev_mode() from their ->lastclose callback. They
+  * should also notify the fb helper code from updates to the output
+  * configuration by calling drm_fb_helper_hotplug_event(). For easier
+  * integration with the output polling code in drm_crtc_helper.c the modeset
+- * code proves a ->output_poll_changed callback.
++ * code provides a ->output_poll_changed callback.
+  *
+  * All other functions exported by the fb helper library can be used to
+  * implement the fbdev driver interface by the driver.
++ *
++ * It is possible, though perhaps somewhat tricky, to implement race-free
++ * hotplug detection using the fbdev helpers. The drm_fb_helper_prepare()
++ * helper must be called first to initialize the minimum required to make
++ * hotplug detection work. Drivers also need to make sure to properly set up
++ * the dev->mode_config.funcs member. After calling drm_kms_helper_poll_init()
++ * it is safe to enable interrupts and start processing hotplug events. At the
++ * same time, drivers should initialize all modeset objects such as CRTCs,
++ * encoders and connectors. To finish up the fbdev helper initialization, the
++ * drm_fb_helper_init() function is called. To probe for all attached displays
++ * and set up an initial configuration using the detected hardware, drivers
++ * should call drm_fb_helper_single_add_all_connectors() followed by
++ * drm_fb_helper_initial_config().
+  */
+ 
+ /**
+@@ -105,59 +119,57 @@
+ }
+ EXPORT_SYMBOL(drm_fb_helper_single_add_all_connectors);
+ 
+-static int drm_fb_helper_parse_command_line(struct drm_fb_helper *fb_helper)
++int drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper, struct drm_connector *connector)
+ {
+-	struct drm_fb_helper_connector *fb_helper_conn;
+-	int i;
++	struct drm_fb_helper_connector **temp;
++	struct drm_fb_helper_connector *fb_helper_connector;
+ 
+-	for (i = 0; i < fb_helper->connector_count; i++) {
+-		struct drm_cmdline_mode *mode;
+-		struct drm_connector *connector;
+-		char *option = NULL;
++	WARN_ON(!mutex_is_locked(&fb_helper->dev->mode_config.mutex));
++	if (fb_helper->connector_count + 1 > fb_helper->connector_info_alloc_count) {
++		temp = krealloc(fb_helper->connector_info, sizeof(struct drm_fb_helper_connector *) * (fb_helper->connector_count + 1), GFP_KERNEL);
++		if (!temp)
++			return -ENOMEM;
+ 
+-		fb_helper_conn = fb_helper->connector_info[i];
+-		connector = fb_helper_conn->connector;
+-		mode = &fb_helper_conn->cmdline_mode;
++		fb_helper->connector_info_alloc_count = fb_helper->connector_count + 1;
++		fb_helper->connector_info = temp;
++	}
+ 
+-		/* do something on return - turn off connector maybe */
+-		if (fb_get_options(drm_get_connector_name(connector), &option))
+-			continue;
+ 
+-		if (drm_mode_parse_command_line_for_connector(option,
+-							      connector,
+-							      mode)) {
+-			if (mode->force) {
+-				const char *s;
+-				switch (mode->force) {
+-				case DRM_FORCE_OFF:
+-					s = "OFF";
+-					break;
+-				case DRM_FORCE_ON_DIGITAL:
+-					s = "ON - dig";
+-					break;
+-				default:
+-				case DRM_FORCE_ON:
+-					s = "ON";
+-					break;
+-				}
+-
+-				DRM_INFO("forcing %s connector %s\n",
+-					 drm_get_connector_name(connector), s);
+-				connector->force = mode->force;
+-			}
++	fb_helper_connector = kzalloc(sizeof(struct drm_fb_helper_connector), GFP_KERNEL);
++	if (!fb_helper_connector)
++		return -ENOMEM;
+ 
+-			DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n",
+-				      drm_get_connector_name(connector),
+-				      mode->xres, mode->yres,
+-				      mode->refresh_specified ? mode->refresh : 60,
+-				      mode->rb ? " reduced blanking" : "",
+-				      mode->margins ? " with margins" : "",
+-				      mode->interlace ?  " interlaced" : "");
+-		}
++	fb_helper_connector->connector = connector;
++	fb_helper->connector_info[fb_helper->connector_count++] = fb_helper_connector;
++	return 0;
++}
++EXPORT_SYMBOL(drm_fb_helper_add_one_connector);
++
++int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,
++				       struct drm_connector *connector)
++{
++	struct drm_fb_helper_connector *fb_helper_connector;
++	int i, j;
++
++	WARN_ON(!mutex_is_locked(&fb_helper->dev->mode_config.mutex));
+ 
++	for (i = 0; i < fb_helper->connector_count; i++) {
++		if (fb_helper->connector_info[i]->connector == connector)
++			break;
+ 	}
++
++	if (i == fb_helper->connector_count)
++		return -EINVAL;
++	fb_helper_connector = fb_helper->connector_info[i];
++
++	for (j = i + 1; j < fb_helper->connector_count; j++) {
++		fb_helper->connector_info[j - 1] = fb_helper->connector_info[j];
++	}
++	fb_helper->connector_count--;
++	kfree(fb_helper_connector);
+ 	return 0;
+ }
++EXPORT_SYMBOL(drm_fb_helper_remove_one_connector);
+ 
+ static void drm_fb_helper_save_lut_atomic(struct drm_crtc *crtc, struct drm_fb_helper *helper)
+ {
+@@ -199,9 +211,6 @@
+ 	struct drm_crtc_helper_funcs *funcs;
+ 	int i;
+ 
+-	if (list_empty(&kernel_fb_helper_list))
+-		return false;
+-
+ 	list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) {
+ 		for (i = 0; i < helper->crtc_count; i++) {
+ 			struct drm_mode_set *mode_set =
+@@ -232,7 +241,7 @@
+ 
+ 	list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
+ 		if (crtc->base.id == c->base.id)
+-			return c->fb;
++			return c->primary->fb;
+ 	}
+ 
+ 	return NULL;
+@@ -273,15 +282,7 @@
+ }
+ EXPORT_SYMBOL(drm_fb_helper_debug_leave);
+ 
+-/**
+- * drm_fb_helper_restore_fbdev_mode - restore fbdev configuration
+- * @fb_helper: fbcon to restore
+- *
+- * This should be called from driver's drm ->lastclose callback
+- * when implementing an fbcon on top of kms using this helper. This ensures that
+- * the user isn't greeted with a black screen when e.g. X dies.
+- */
+-bool drm_fb_helper_restore_fbdev_mode(struct drm_fb_helper *fb_helper)
++static bool restore_fbdev_mode(struct drm_fb_helper *fb_helper)
+ {
+ 	struct drm_device *dev = fb_helper->dev;
+ 	struct drm_plane *plane;
+@@ -290,8 +291,16 @@
+ 
+ 	drm_warn_on_modeset_not_all_locked(dev);
+ 
+-	list_for_each_entry(plane, &dev->mode_config.plane_list, head)
+-		drm_plane_force_disable(plane);
++	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
++		if (plane->type != DRM_PLANE_TYPE_PRIMARY)
++			drm_plane_force_disable(plane);
++
++		if (dev->mode_config.rotation_property) {
++			drm_mode_plane_set_obj_prop(plane,
++						    dev->mode_config.rotation_property,
++						    BIT(DRM_ROTATE_0));
++		}
++	}
+ 
+ 	for (i = 0; i < fb_helper->crtc_count; i++) {
+ 		struct drm_mode_set *mode_set = &fb_helper->crtc_info[i].mode_set;
+@@ -310,7 +319,49 @@
+ 	}
+ 	return error;
+ }
+-EXPORT_SYMBOL(drm_fb_helper_restore_fbdev_mode);
++/**
++ * drm_fb_helper_restore_fbdev_mode - restore fbdev configuration
++ * @fb_helper: fbcon to restore
++ *
++ * This should be called from driver's drm ->lastclose callback
++ * when implementing an fbcon on top of kms using this helper. This ensures that
++ * the user isn't greeted with a black screen when e.g. X dies.
++ *
++ * Use this variant if you need to bypass locking (panic), or already
++ * hold all modeset locks.  Otherwise use drm_fb_helper_restore_fbdev_mode_unlocked()
++ */
++static bool drm_fb_helper_restore_fbdev_mode(struct drm_fb_helper *fb_helper)
++{
++	return restore_fbdev_mode(fb_helper);
++}
++
++/**
++ * drm_fb_helper_restore_fbdev_mode_unlocked - restore fbdev configuration
++ * @fb_helper: fbcon to restore
++ *
++ * This should be called from driver's drm ->lastclose callback
++ * when implementing an fbcon on top of kms using this helper. This ensures that
++ * the user isn't greeted with a black screen when e.g. X dies.
++ */
++bool drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper)
++{
++	struct drm_device *dev = fb_helper->dev;
++	bool ret;
++	bool do_delayed = false;
++
++	drm_modeset_lock_all(dev);
++	ret = restore_fbdev_mode(fb_helper);
++
++	do_delayed = fb_helper->delayed_hotplug;
++	if (do_delayed)
++		fb_helper->delayed_hotplug = false;
++	drm_modeset_unlock_all(dev);
++
++	if (do_delayed)
++		drm_fb_helper_hotplug_event(fb_helper);
++	return ret;
++}
++EXPORT_SYMBOL(drm_fb_helper_restore_fbdev_mode_unlocked);
+ 
+ /*
+  * restore fbcon display for all kms driver's using this helper, used for sysrq
+@@ -325,12 +376,25 @@
+ 		return false;
+ 
+ 	list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) {
+-		if (helper->dev->switch_power_state == DRM_SWITCH_POWER_OFF)
++		struct drm_device *dev = helper->dev;
++
++		if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+ 			continue;
+ 
++		/*
++		 * NOTE: Use trylock mode to avoid deadlocks and sleeping in
++		 * panic context.
++		 */
++		if (__drm_modeset_lock_all(dev, true) != 0) {
++			error = true;
++			continue;
++		}
++
+ 		ret = drm_fb_helper_restore_fbdev_mode(helper);
+ 		if (ret)
+ 			error = true;
++
++		drm_modeset_unlock_all(dev);
+ 	}
+ 	return error;
+ }
+@@ -365,9 +429,9 @@
+ 		return false;
+ 
+ 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+-		if (crtc->fb)
++		if (crtc->primary->fb)
+ 			crtcs_bound++;
+-		if (crtc->fb == fb_helper->fb)
++		if (crtc->primary->fb == fb_helper->fb)
+ 			bound++;
+ 	}
+ 
+@@ -492,6 +556,24 @@
+ }
+ 
+ /**
++ * drm_fb_helper_prepare - setup a drm_fb_helper structure
++ * @dev: DRM device
++ * @helper: driver-allocated fbdev helper structure to set up
++ * @funcs: pointer to structure of functions associate with this helper
++ *
++ * Sets up the bare minimum to make the framebuffer helper usable. This is
++ * useful to implement race-free initialization of the polling helpers.
++ */
++void drm_fb_helper_prepare(struct drm_device *dev, struct drm_fb_helper *helper,
++			   const struct drm_fb_helper_funcs *funcs)
++{
++	INIT_LIST_HEAD(&helper->kernel_fb_list);
++	helper->funcs = funcs;
++	helper->dev = dev;
++}
++EXPORT_SYMBOL(drm_fb_helper_prepare);
++
++/**
+  * drm_fb_helper_init - initialize a drm_fb_helper structure
+  * @dev: drm device
+  * @fb_helper: driver-allocated fbdev helper structure to initialize
+@@ -503,8 +585,7 @@
+  * nor register the fbdev. This is only done in drm_fb_helper_initial_config()
+  * to allow driver writes more control over the exact init sequence.
+  *
+- * Drivers must set fb_helper->funcs before calling
+- * drm_fb_helper_initial_config().
++ * Drivers must call drm_fb_helper_prepare() before calling this function.
+  *
+  * RETURNS:
+  * Zero if everything went ok, nonzero otherwise.
+@@ -516,9 +597,8 @@
+ 	struct drm_crtc *crtc;
+ 	int i;
+ 
+-	fb_helper->dev = dev;
+-
+-	INIT_LIST_HEAD(&fb_helper->kernel_fb_list);
++	if (!max_conn_count)
++		return -EINVAL;
+ 
+ 	fb_helper->crtc_info = kcalloc(crtc_count, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL);
+ 	if (!fb_helper->crtc_info)
+@@ -530,6 +610,7 @@
+ 		kfree(fb_helper->crtc_info);
+ 		return -ENOMEM;
+ 	}
++	fb_helper->connector_info_alloc_count = dev->mode_config.num_connector;
+ 	fb_helper->connector_count = 0;
+ 
+ 	for (i = 0; i < crtc_count; i++) {
+@@ -807,30 +888,15 @@
+ int drm_fb_helper_set_par(struct fb_info *info)
+ {
+ 	struct drm_fb_helper *fb_helper = info->par;
+-	struct drm_device *dev = fb_helper->dev;
+ 	struct fb_var_screeninfo *var = &info->var;
+-	int ret;
+-	int i;
+ 
+ 	if (var->pixclock != 0) {
+ 		DRM_ERROR("PIXEL CLOCK SET\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	drm_modeset_lock_all(dev);
+-	for (i = 0; i < fb_helper->crtc_count; i++) {
+-		ret = drm_mode_set_config_internal(&fb_helper->crtc_info[i].mode_set);
+-		if (ret) {
+-			drm_modeset_unlock_all(dev);
+-			return ret;
+-		}
+-	}
+-	drm_modeset_unlock_all(dev);
++	drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
+ 
+-	if (fb_helper->delayed_hotplug) {
+-		fb_helper->delayed_hotplug = false;
+-		drm_fb_helper_hotplug_event(fb_helper);
+-	}
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_fb_helper_set_par);
+@@ -905,7 +971,7 @@
+ 		struct drm_fb_helper_connector *fb_helper_conn = fb_helper->connector_info[i];
+ 		struct drm_cmdline_mode *cmdline_mode;
+ 
+-		cmdline_mode = &fb_helper_conn->cmdline_mode;
++		cmdline_mode = &fb_helper_conn->connector->cmdline_mode;
+ 
+ 		if (cmdline_mode->bpp_specified) {
+ 			switch (cmdline_mode->bpp) {
+@@ -934,19 +1000,21 @@
+ 	crtc_count = 0;
+ 	for (i = 0; i < fb_helper->crtc_count; i++) {
+ 		struct drm_display_mode *desired_mode;
++		int x, y;
+ 		desired_mode = fb_helper->crtc_info[i].desired_mode;
+-
++		x = fb_helper->crtc_info[i].x;
++		y = fb_helper->crtc_info[i].y;
+ 		if (desired_mode) {
+ 			if (gamma_size == 0)
+ 				gamma_size = fb_helper->crtc_info[i].mode_set.crtc->gamma_size;
+-			if (desired_mode->hdisplay < sizes.fb_width)
+-				sizes.fb_width = desired_mode->hdisplay;
+-			if (desired_mode->vdisplay < sizes.fb_height)
+-				sizes.fb_height = desired_mode->vdisplay;
+-			if (desired_mode->hdisplay > sizes.surface_width)
+-				sizes.surface_width = desired_mode->hdisplay;
+-			if (desired_mode->vdisplay > sizes.surface_height)
+-				sizes.surface_height = desired_mode->vdisplay;
++			if (desired_mode->hdisplay + x < sizes.fb_width)
++				sizes.fb_width = desired_mode->hdisplay + x;
++			if (desired_mode->vdisplay + y < sizes.fb_height)
++				sizes.fb_height = desired_mode->vdisplay + y;
++			if (desired_mode->hdisplay + x > sizes.surface_width)
++				sizes.surface_width = desired_mode->hdisplay + x;
++			if (desired_mode->vdisplay + y > sizes.surface_height)
++				sizes.surface_height = desired_mode->vdisplay + y;
+ 			crtc_count++;
+ 		}
+ 	}
+@@ -1025,7 +1093,6 @@
+ 	info->fix.ypanstep = 1; /* doing it in hw */
+ 	info->fix.ywrapstep = 0;
+ 	info->fix.accel = FB_ACCEL_NONE;
+-	info->fix.type_aux = 0;
+ 
+ 	info->fix.line_length = pitch;
+ 	return;
+@@ -1136,34 +1203,34 @@
+ 	return count;
+ }
+ 
+-static struct drm_display_mode *drm_has_preferred_mode(struct drm_fb_helper_connector *fb_connector, int width, int height)
++struct drm_display_mode *drm_has_preferred_mode(struct drm_fb_helper_connector *fb_connector, int width, int height)
+ {
+ 	struct drm_display_mode *mode;
+ 
+ 	list_for_each_entry(mode, &fb_connector->connector->modes, head) {
+-		if (drm_mode_width(mode) > width ||
+-		    drm_mode_height(mode) > height)
++		if (mode->hdisplay > width ||
++		    mode->vdisplay > height)
+ 			continue;
+ 		if (mode->type & DRM_MODE_TYPE_PREFERRED)
+ 			return mode;
+ 	}
+ 	return NULL;
+ }
++EXPORT_SYMBOL(drm_has_preferred_mode);
+ 
+ static bool drm_has_cmdline_mode(struct drm_fb_helper_connector *fb_connector)
+ {
+-	struct drm_cmdline_mode *cmdline_mode;
+-	cmdline_mode = &fb_connector->cmdline_mode;
+-	return cmdline_mode->specified;
++	return fb_connector->connector->cmdline_mode.specified;
+ }
+ 
+-static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn,
++struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn,
+ 						      int width, int height)
+ {
+ 	struct drm_cmdline_mode *cmdline_mode;
+ 	struct drm_display_mode *mode = NULL;
++	bool prefer_non_interlace;
+ 
+-	cmdline_mode = &fb_helper_conn->cmdline_mode;
++	cmdline_mode = &fb_helper_conn->connector->cmdline_mode;
+ 	if (cmdline_mode->specified == false)
+ 		return mode;
+ 
+@@ -1173,6 +1240,8 @@
+ 	if (cmdline_mode->rb || cmdline_mode->margins)
+ 		goto create_mode;
+ 
++	prefer_non_interlace = !cmdline_mode->interlace;
++ again:
+ 	list_for_each_entry(mode, &fb_helper_conn->connector->modes, head) {
+ 		/* check width/height */
+ 		if (mode->hdisplay != cmdline_mode->xres ||
+@@ -1187,16 +1256,25 @@
+ 		if (cmdline_mode->interlace) {
+ 			if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
+ 				continue;
++		} else if (prefer_non_interlace) {
++			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++				continue;
+ 		}
+ 		return mode;
+ 	}
+ 
++	if (prefer_non_interlace) {
++		prefer_non_interlace = false;
++		goto again;
++	}
++
+ create_mode:
+ 	mode = drm_mode_create_from_cmdline_mode(fb_helper_conn->connector->dev,
+ 						 cmdline_mode);
+ 	list_add(&mode->head, &fb_helper_conn->connector->modes);
+ 	return mode;
+ }
++EXPORT_SYMBOL(drm_pick_cmdline_mode);
+ 
+ static bool drm_connector_enabled(struct drm_connector *connector, bool strict)
+ {
+@@ -1236,6 +1314,7 @@
+ 
+ static bool drm_target_cloned(struct drm_fb_helper *fb_helper,
+ 			      struct drm_display_mode **modes,
++			      struct drm_fb_offset *offsets,
+ 			      bool *enabled, int width, int height)
+ {
+ 	int count, i, j;
+@@ -1307,27 +1386,88 @@
+ 	return false;
+ }
+ 
++static int drm_get_tile_offsets(struct drm_fb_helper *fb_helper,
++				struct drm_display_mode **modes,
++				struct drm_fb_offset *offsets,
++				int idx,
++				int h_idx, int v_idx)
++{
++	struct drm_fb_helper_connector *fb_helper_conn;
++	int i;
++	int hoffset = 0, voffset = 0;
++
++	for (i = 0; i < fb_helper->connector_count; i++) {
++		fb_helper_conn = fb_helper->connector_info[i];
++		if (!fb_helper_conn->connector->has_tile)
++			continue;
++
++		if (!modes[i] && (h_idx || v_idx)) {
++			DRM_DEBUG_KMS("no modes for connector tiled %d %d\n", i,
++				      fb_helper_conn->connector->base.id);
++			continue;
++		}
++		if (fb_helper_conn->connector->tile_h_loc < h_idx)
++			hoffset += modes[i]->hdisplay;
++
++		if (fb_helper_conn->connector->tile_v_loc < v_idx)
++			voffset += modes[i]->vdisplay;
++	}
++	offsets[idx].x = hoffset;
++	offsets[idx].y = voffset;
++	DRM_DEBUG_KMS("returned %d %d for %d %d\n", hoffset, voffset, h_idx, v_idx);
++	return 0;
++}
++
+ static bool drm_target_preferred(struct drm_fb_helper *fb_helper,
+ 				 struct drm_display_mode **modes,
++				 struct drm_fb_offset *offsets,
+ 				 bool *enabled, int width, int height)
+ {
+ 	struct drm_fb_helper_connector *fb_helper_conn;
+ 	int i;
+-
++	uint64_t conn_configured = 0, mask;
++	int tile_pass = 0;
++	mask = (1 << fb_helper->connector_count) - 1;
++retry:
+ 	for (i = 0; i < fb_helper->connector_count; i++) {
+ 		fb_helper_conn = fb_helper->connector_info[i];
+ 
+-		if (enabled[i] == false)
++		if (conn_configured & (1 << i))
+ 			continue;
+ 
++		if (enabled[i] == false) {
++			conn_configured |= (1 << i);
++			continue;
++		}
++
++		/* first pass over all the untiled connectors */
++		if (tile_pass == 0 && fb_helper_conn->connector->has_tile)
++			continue;
++
++		if (tile_pass == 1) {
++			if (fb_helper_conn->connector->tile_h_loc != 0 ||
++			    fb_helper_conn->connector->tile_v_loc != 0)
++				continue;
++
++		} else {
++			if (fb_helper_conn->connector->tile_h_loc != tile_pass -1 &&
++			    fb_helper_conn->connector->tile_v_loc != tile_pass - 1)
++			/* if this tile_pass doesn't cover any of the tiles - keep going */
++				continue;
++
++			/* find the tile offsets for this pass - need
++			   to find all tiles left and above */
++			drm_get_tile_offsets(fb_helper, modes, offsets,
++					     i, fb_helper_conn->connector->tile_h_loc, fb_helper_conn->connector->tile_v_loc);
++		}
+ 		DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n",
+ 			      fb_helper_conn->connector->base.id);
+ 
+ 		/* got for command line mode first */
+ 		modes[i] = drm_pick_cmdline_mode(fb_helper_conn, width, height);
+ 		if (!modes[i]) {
+-			DRM_DEBUG_KMS("looking for preferred mode on connector %d\n",
+-				      fb_helper_conn->connector->base.id);
++			DRM_DEBUG_KMS("looking for preferred mode on connector %d %d\n",
++				      fb_helper_conn->connector->base.id, fb_helper_conn->connector->tile_group ? fb_helper_conn->connector->tile_group->id : 0);
+ 			modes[i] = drm_has_preferred_mode(fb_helper_conn, width, height);
+ 		}
+ 		/* No preferred modes, pick one off the list */
+@@ -1337,6 +1477,12 @@
+ 		}
+ 		DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name :
+ 			  "none");
++		conn_configured |= (1 << i);
++	}
++
++	if ((conn_configured & mask) != mask) {
++		tile_pass++;
++		goto retry;
+ 	}
+ 	return true;
+ }
+@@ -1426,6 +1572,7 @@
+ 	struct drm_device *dev = fb_helper->dev;
+ 	struct drm_fb_helper_crtc **crtcs;
+ 	struct drm_display_mode **modes;
++	struct drm_fb_offset *offsets;
+ 	struct drm_mode_set *modeset;
+ 	bool *enabled;
+ 	int width, height;
+@@ -1440,9 +1587,11 @@
+ 			sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL);
+ 	modes = kcalloc(dev->mode_config.num_connector,
+ 			sizeof(struct drm_display_mode *), GFP_KERNEL);
++	offsets = kcalloc(dev->mode_config.num_connector,
++			  sizeof(struct drm_fb_offset), GFP_KERNEL);
+ 	enabled = kcalloc(dev->mode_config.num_connector,
+ 			  sizeof(bool), GFP_KERNEL);
+-	if (!crtcs || !modes || !enabled) {
++	if (!crtcs || !modes || !enabled || !offsets) {
+ 		DRM_ERROR("Memory allocation failed\n");
+ 		goto out;
+ 	}
+@@ -1452,14 +1601,16 @@
+ 
+ 	if (!(fb_helper->funcs->initial_config &&
+ 	      fb_helper->funcs->initial_config(fb_helper, crtcs, modes,
++					       offsets,
+ 					       enabled, width, height))) {
+ 		memset(modes, 0, dev->mode_config.num_connector*sizeof(modes[0]));
+ 		memset(crtcs, 0, dev->mode_config.num_connector*sizeof(crtcs[0]));
++		memset(offsets, 0, dev->mode_config.num_connector*sizeof(offsets[0]));
+ 
+-		if (!drm_target_cloned(fb_helper,
+-				       modes, enabled, width, height) &&
+-		    !drm_target_preferred(fb_helper,
+-					  modes, enabled, width, height))
++		if (!drm_target_cloned(fb_helper, modes, offsets,
++				       enabled, width, height) &&
++		    !drm_target_preferred(fb_helper, modes, offsets,
++					  enabled, width, height))
+ 			DRM_ERROR("Unable to find initial modes\n");
+ 
+ 		DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n",
+@@ -1479,18 +1630,23 @@
+ 	for (i = 0; i < fb_helper->connector_count; i++) {
+ 		struct drm_display_mode *mode = modes[i];
+ 		struct drm_fb_helper_crtc *fb_crtc = crtcs[i];
++		struct drm_fb_offset *offset = &offsets[i];
+ 		modeset = &fb_crtc->mode_set;
+ 
+ 		if (mode && fb_crtc) {
+-			DRM_DEBUG_KMS("desired mode %s set on crtc %d\n",
+-				      mode->name, fb_crtc->mode_set.crtc->base.id);
++			DRM_DEBUG_KMS("desired mode %s set on crtc %d (%d,%d)\n",
++				      mode->name, fb_crtc->mode_set.crtc->base.id, offset->x, offset->y);
+ 			fb_crtc->desired_mode = mode;
++			fb_crtc->x = offset->x;
++			fb_crtc->y = offset->y;
+ 			if (modeset->mode)
+ 				drm_mode_destroy(dev, modeset->mode);
+ 			modeset->mode = drm_mode_duplicate(dev,
+ 							   fb_crtc->desired_mode);
+ 			modeset->connectors[modeset->num_connectors++] = fb_helper->connector_info[i]->connector;
+ 			modeset->fb = fb_helper->fb;
++			modeset->x = offset->x;
++			modeset->y = offset->y;
+ 		}
+ 	}
+ 
+@@ -1499,7 +1655,6 @@
+ 		modeset = &fb_helper->crtc_info[i].mode_set;
+ 		if (modeset->num_connectors == 0) {
+ 			BUG_ON(modeset->fb);
+-			BUG_ON(modeset->num_connectors);
+ 			if (modeset->mode)
+ 				drm_mode_destroy(dev, modeset->mode);
+ 			modeset->mode = NULL;
+@@ -1508,6 +1663,7 @@
+ out:
+ 	kfree(crtcs);
+ 	kfree(modes);
++	kfree(offsets);
+ 	kfree(enabled);
+ }
+ 
+@@ -1537,11 +1693,11 @@
+ 	struct drm_device *dev = fb_helper->dev;
+ 	int count = 0;
+ 
+-	drm_fb_helper_parse_command_line(fb_helper);
+-
++	mutex_lock(&dev->mode_config.mutex);
+ 	count = drm_fb_helper_probe_connector_modes(fb_helper,
+ 						    dev->mode_config.max_width,
+ 						    dev->mode_config.max_height);
++	mutex_unlock(&dev->mode_config.mutex);
+ 	/*
+ 	 * we shouldn't end up with no modes here.
+ 	 */
+@@ -1567,8 +1723,10 @@
+  * either the output polling work or a work item launched from the driver's
+  * hotplug interrupt).
+  *
+- * Note that the driver must ensure that this is only called _after_ the fb has
+- * been fully set up, i.e. after the call to drm_fb_helper_initial_config.
++ * Note that drivers may call this even before calling
++ * drm_fb_helper_initial_config but only aftert drm_fb_helper_init. This allows
++ * for a race-free fbcon setup and will make sure that the fbdev emulation will
++ * not miss any hotplug events.
+  *
+  * RETURNS:
+  * 0 on success and a non-zero error code otherwise.
+@@ -1578,11 +1736,8 @@
+ 	struct drm_device *dev = fb_helper->dev;
+ 	u32 max_width, max_height;
+ 
+-	if (!fb_helper->fb)
+-		return 0;
+-
+ 	mutex_lock(&fb_helper->dev->mode_config.mutex);
+-	if (!drm_fb_helper_is_bound(fb_helper)) {
++	if (!fb_helper->fb || !drm_fb_helper_is_bound(fb_helper)) {
+ 		fb_helper->delayed_hotplug = true;
+ 		mutex_unlock(&fb_helper->dev->mode_config.mutex);
+ 		return 0;
+diff -Naur a/drivers/gpu/drm/drm_flip_work.c b/drivers/gpu/drm/drm_flip_work.c
+--- a/drivers/gpu/drm/drm_flip_work.c	2015-03-26 14:43:30.430436436 +0530
++++ b/drivers/gpu/drm/drm_flip_work.c	2015-03-26 14:42:38.722435422 +0530
+@@ -25,6 +25,44 @@
+ #include "drm_flip_work.h"
+ 
+ /**
++ * drm_flip_work_allocate_task - allocate a flip-work task
++ * @data: data associated to the task
++ * @flags: allocator flags
++ *
++ * Allocate a drm_flip_task object and attach private data to it.
++ */
++struct drm_flip_task *drm_flip_work_allocate_task(void *data, gfp_t flags)
++{
++	struct drm_flip_task *task;
++
++	task = kzalloc(sizeof(*task), flags);
++	if (task)
++		task->data = data;
++
++	return task;
++}
++EXPORT_SYMBOL(drm_flip_work_allocate_task);
++
++/**
++ * drm_flip_work_queue_task - queue a specific task
++ * @work: the flip-work
++ * @task: the task to handle
++ *
++ * Queues task, that will later be run (passed back to drm_flip_func_t
++ * func) on a work queue after drm_flip_work_commit() is called.
++ */
++void drm_flip_work_queue_task(struct drm_flip_work *work,
++			      struct drm_flip_task *task)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&work->lock, flags);
++	list_add_tail(&task->node, &work->queued);
++	spin_unlock_irqrestore(&work->lock, flags);
++}
++EXPORT_SYMBOL(drm_flip_work_queue_task);
++
++/**
+  * drm_flip_work_queue - queue work
+  * @work: the flip-work
+  * @val: the value to queue
+@@ -34,10 +72,14 @@
+  */
+ void drm_flip_work_queue(struct drm_flip_work *work, void *val)
+ {
+-	if (kfifo_put(&work->fifo, val)) {
+-		atomic_inc(&work->pending);
++	struct drm_flip_task *task;
++
++	task = drm_flip_work_allocate_task(val,
++				drm_can_sleep() ? GFP_KERNEL : GFP_ATOMIC);
++	if (task) {
++		drm_flip_work_queue_task(work, task);
+ 	} else {
+-		DRM_ERROR("%s fifo full!\n", work->name);
++		DRM_ERROR("%s could not allocate task!\n", work->name);
+ 		work->func(work, val);
+ 	}
+ }
+@@ -56,9 +98,12 @@
+ void drm_flip_work_commit(struct drm_flip_work *work,
+ 		struct workqueue_struct *wq)
+ {
+-	uint32_t pending = atomic_read(&work->pending);
+-	atomic_add(pending, &work->count);
+-	atomic_sub(pending, &work->pending);
++	unsigned long flags;
++
++	spin_lock_irqsave(&work->lock, flags);
++	list_splice_tail(&work->queued, &work->commited);
++	INIT_LIST_HEAD(&work->queued);
++	spin_unlock_irqrestore(&work->lock, flags);
+ 	queue_work(wq, &work->worker);
+ }
+ EXPORT_SYMBOL(drm_flip_work_commit);
+@@ -66,47 +111,46 @@
+ static void flip_worker(struct work_struct *w)
+ {
+ 	struct drm_flip_work *work = container_of(w, struct drm_flip_work, worker);
+-	uint32_t count = atomic_read(&work->count);
+-	void *val = NULL;
++	struct list_head tasks;
++	unsigned long flags;
+ 
+-	atomic_sub(count, &work->count);
++	while (1) {
++		struct drm_flip_task *task, *tmp;
+ 
+-	while(count--)
+-		if (!WARN_ON(!kfifo_get(&work->fifo, &val)))
+-			work->func(work, val);
++		INIT_LIST_HEAD(&tasks);
++		spin_lock_irqsave(&work->lock, flags);
++		list_splice_tail(&work->commited, &tasks);
++		INIT_LIST_HEAD(&work->commited);
++		spin_unlock_irqrestore(&work->lock, flags);
++
++		if (list_empty(&tasks))
++			break;
++
++		list_for_each_entry_safe(task, tmp, &tasks, node) {
++			work->func(work, task->data);
++			kfree(task);
++		}
++	}
+ }
+ 
+ /**
+  * drm_flip_work_init - initialize flip-work
+  * @work: the flip-work to initialize
+- * @size: the max queue depth
+  * @name: debug name
+  * @func: the callback work function
+  *
+  * Initializes/allocates resources for the flip-work
+- *
+- * RETURNS:
+- * Zero on success, error code on failure.
+  */
+-int drm_flip_work_init(struct drm_flip_work *work, int size,
++void drm_flip_work_init(struct drm_flip_work *work,
+ 		const char *name, drm_flip_func_t func)
+ {
+-	int ret;
+-
+ 	work->name = name;
+-	atomic_set(&work->count, 0);
+-	atomic_set(&work->pending, 0);
++	INIT_LIST_HEAD(&work->queued);
++	INIT_LIST_HEAD(&work->commited);
++	spin_lock_init(&work->lock);
+ 	work->func = func;
+ 
+-	ret = kfifo_alloc(&work->fifo, size, GFP_KERNEL);
+-	if (ret) {
+-		DRM_ERROR("could not allocate %s fifo\n", name);
+-		return ret;
+-	}
+-
+ 	INIT_WORK(&work->worker, flip_worker);
+-
+-	return 0;
+ }
+ EXPORT_SYMBOL(drm_flip_work_init);
+ 
+@@ -118,7 +162,6 @@
+  */
+ void drm_flip_work_cleanup(struct drm_flip_work *work)
+ {
+-	WARN_ON(!kfifo_is_empty(&work->fifo));
+-	kfifo_free(&work->fifo);
++	WARN_ON(!list_empty(&work->queued) || !list_empty(&work->commited));
+ }
+ EXPORT_SYMBOL(drm_flip_work_cleanup);
+diff -Naur a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
+--- a/drivers/gpu/drm/drm_fops.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_fops.c	2015-03-26 14:42:38.722435422 +0530
+@@ -38,13 +38,13 @@
+ #include <linux/poll.h>
+ #include <linux/slab.h>
+ #include <linux/module.h>
++#include "drm_legacy.h"
++#include "drm_internal.h"
+ 
+-/* from BKL pushdown: note that nothing else serializes idr_find() */
++/* from BKL pushdown */
+ DEFINE_MUTEX(drm_global_mutex);
+-EXPORT_SYMBOL(drm_global_mutex);
+ 
+-static int drm_open_helper(struct inode *inode, struct file *filp,
+-			   struct drm_device * dev);
++static int drm_open_helper(struct file *filp, struct drm_minor *minor);
+ 
+ static int drm_setup(struct drm_device * dev)
+ {
+@@ -79,38 +79,23 @@
+  */
+ int drm_open(struct inode *inode, struct file *filp)
+ {
+-	struct drm_device *dev = NULL;
+-	int minor_id = iminor(inode);
++	struct drm_device *dev;
+ 	struct drm_minor *minor;
+-	int retcode = 0;
++	int retcode;
+ 	int need_setup = 0;
+-	struct address_space *old_mapping;
+-	struct address_space *old_imapping;
+-
+-	minor = idr_find(&drm_minors_idr, minor_id);
+-	if (!minor)
+-		return -ENODEV;
+-
+-	if (!(dev = minor->dev))
+-		return -ENODEV;
+ 
+-	if (drm_device_is_unplugged(dev))
+-		return -ENODEV;
++	minor = drm_minor_acquire(iminor(inode));
++	if (IS_ERR(minor))
++		return PTR_ERR(minor);
+ 
++	dev = minor->dev;
+ 	if (!dev->open_count++)
+ 		need_setup = 1;
+-	mutex_lock(&dev->struct_mutex);
+-	old_imapping = inode->i_mapping;
+-	old_mapping = dev->dev_mapping;
+-	if (old_mapping == NULL)
+-		dev->dev_mapping = &inode->i_data;
+-	/* ihold ensures nobody can remove inode with our i_data */
+-	ihold(container_of(dev->dev_mapping, struct inode, i_data));
+-	inode->i_mapping = dev->dev_mapping;
+-	filp->f_mapping = dev->dev_mapping;
+-	mutex_unlock(&dev->struct_mutex);
+ 
+-	retcode = drm_open_helper(inode, filp, dev);
++	/* share address_space across all char-devs of a single device */
++	filp->f_mapping = dev->anon_inode->i_mapping;
++
++	retcode = drm_open_helper(filp, minor);
+ 	if (retcode)
+ 		goto err_undo;
+ 	if (need_setup) {
+@@ -121,70 +106,19 @@
+ 	return 0;
+ 
+ err_undo:
+-	mutex_lock(&dev->struct_mutex);
+-	filp->f_mapping = old_imapping;
+-	inode->i_mapping = old_imapping;
+-	iput(container_of(dev->dev_mapping, struct inode, i_data));
+-	dev->dev_mapping = old_mapping;
+-	mutex_unlock(&dev->struct_mutex);
+ 	dev->open_count--;
++	drm_minor_release(minor);
+ 	return retcode;
+ }
+ EXPORT_SYMBOL(drm_open);
+ 
+ /**
+- * File \c open operation.
+- *
+- * \param inode device inode.
+- * \param filp file pointer.
+- *
+- * Puts the dev->fops corresponding to the device minor number into
+- * \p filp, call the \c open method, and restore the file operations.
+- */
+-int drm_stub_open(struct inode *inode, struct file *filp)
+-{
+-	struct drm_device *dev = NULL;
+-	struct drm_minor *minor;
+-	int minor_id = iminor(inode);
+-	int err = -ENODEV;
+-	const struct file_operations *new_fops;
+-
+-	DRM_DEBUG("\n");
+-
+-	mutex_lock(&drm_global_mutex);
+-	minor = idr_find(&drm_minors_idr, minor_id);
+-	if (!minor)
+-		goto out;
+-
+-	if (!(dev = minor->dev))
+-		goto out;
+-
+-	if (drm_device_is_unplugged(dev))
+-		goto out;
+-
+-	new_fops = fops_get(dev->driver->fops);
+-	if (!new_fops)
+-		goto out;
+-
+-	replace_fops(filp, new_fops);
+-	if (filp->f_op->open)
+-		err = filp->f_op->open(inode, filp);
+-out:
+-	mutex_unlock(&drm_global_mutex);
+-	return err;
+-}
+-
+-/**
+  * Check whether DRI will run on this CPU.
+  *
+  * \return non-zero if the DRI will run on this CPU, or zero otherwise.
+  */
+ static int drm_cpu_valid(void)
+ {
+-#if defined(__i386__)
+-	if (boot_cpu_data.x86 == 3)
+-		return 0;	/* No cmpxchg on a 386 */
+-#endif
+ #if defined(__sparc__) && !defined(__sparc_v9__)
+ 	return 0;		/* No cmpxchg before v9 sparc. */
+ #endif
+@@ -194,18 +128,16 @@
+ /**
+  * Called whenever a process opens /dev/drm.
+  *
+- * \param inode device inode.
+  * \param filp file pointer.
+- * \param dev device.
++ * \param minor acquired minor-object.
+  * \return zero on success or a negative number on failure.
+  *
+  * Creates and initializes a drm_file structure for the file private data in \p
+  * filp and add it into the double linked list in \p dev.
+  */
+-static int drm_open_helper(struct inode *inode, struct file *filp,
+-			   struct drm_device * dev)
++static int drm_open_helper(struct file *filp, struct drm_minor *minor)
+ {
+-	int minor_id = iminor(inode);
++	struct drm_device *dev = minor->dev;
+ 	struct drm_file *priv;
+ 	int ret;
+ 
+@@ -216,7 +148,7 @@
+ 	if (dev->switch_power_state != DRM_SWITCH_POWER_ON && dev->switch_power_state != DRM_SWITCH_POWER_DYNAMIC_OFF)
+ 		return -EINVAL;
+ 
+-	DRM_DEBUG("pid = %d, minor = %d\n", task_pid_nr(current), minor_id);
++	DRM_DEBUG("pid = %d, minor = %d\n", task_pid_nr(current), minor->index);
+ 
+ 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+@@ -226,15 +158,10 @@
+ 	priv->filp = filp;
+ 	priv->uid = current_euid();
+ 	priv->pid = get_pid(task_pid(current));
+-	priv->minor = idr_find(&drm_minors_idr, minor_id);
+-	if (!priv->minor) {
+-		ret = -ENODEV;
+-		goto out_put_pid;
+-	}
++	priv->minor = minor;
+ 
+ 	/* for compatibility root is always authenticated */
+-	priv->always_authenticated = capable(CAP_SYS_ADMIN);
+-	priv->authenticated = priv->always_authenticated;
++	priv->authenticated = capable(CAP_SYS_ADMIN);
+ 	priv->lock_count = 0;
+ 
+ 	INIT_LIST_HEAD(&priv->lhead);
+@@ -244,7 +171,7 @@
+ 	init_waitqueue_head(&priv->event_wait);
+ 	priv->event_space = 4096; /* set aside 4k for event buffer */
+ 
+-	if (dev->driver->driver_features & DRIVER_GEM)
++	if (drm_core_check_feature(dev, DRIVER_GEM))
+ 		drm_gem_open(dev, priv);
+ 
+ 	if (drm_core_check_feature(dev, DRIVER_PRIME))
+@@ -258,12 +185,11 @@
+ 
+ 	/* if there is no current master make this fd it, but do not create
+ 	 * any master object for render clients */
+-	mutex_lock(&dev->struct_mutex);
+-	if (!priv->minor->master && !drm_is_render_client(priv)) {
++	mutex_lock(&dev->master_mutex);
++	if (drm_is_primary_client(priv) && !priv->minor->master) {
+ 		/* create a new master */
+ 		priv->minor->master = drm_master_create(priv->minor);
+ 		if (!priv->minor->master) {
+-			mutex_unlock(&dev->struct_mutex);
+ 			ret = -ENOMEM;
+ 			goto out_close;
+ 		}
+@@ -271,37 +197,31 @@
+ 		priv->is_master = 1;
+ 		/* take another reference for the copy in the local file priv */
+ 		priv->master = drm_master_get(priv->minor->master);
+-
+ 		priv->authenticated = 1;
+ 
+-		mutex_unlock(&dev->struct_mutex);
+ 		if (dev->driver->master_create) {
+ 			ret = dev->driver->master_create(dev, priv->master);
+ 			if (ret) {
+-				mutex_lock(&dev->struct_mutex);
+ 				/* drop both references if this fails */
+ 				drm_master_put(&priv->minor->master);
+ 				drm_master_put(&priv->master);
+-				mutex_unlock(&dev->struct_mutex);
+ 				goto out_close;
+ 			}
+ 		}
+-		mutex_lock(&dev->struct_mutex);
+ 		if (dev->driver->master_set) {
+ 			ret = dev->driver->master_set(dev, priv, true);
+ 			if (ret) {
+ 				/* drop both references if this fails */
+ 				drm_master_put(&priv->minor->master);
+ 				drm_master_put(&priv->master);
+-				mutex_unlock(&dev->struct_mutex);
+ 				goto out_close;
+ 			}
+ 		}
+-	} else if (!drm_is_render_client(priv)) {
++	} else if (drm_is_primary_client(priv)) {
+ 		/* get a reference to the master */
+ 		priv->master = drm_master_get(priv->minor->master);
+ 	}
+-	mutex_unlock(&dev->struct_mutex);
++	mutex_unlock(&dev->master_mutex);
+ 
+ 	mutex_lock(&dev->struct_mutex);
+ 	list_add(&priv->lhead, &dev->filelist);
+@@ -319,7 +239,8 @@
+ 			pci_dev_put(pci_dev);
+ 		}
+ 		if (!dev->hose) {
+-			struct pci_bus *b = pci_bus_b(pci_root_buses.next);
++			struct pci_bus *b = list_entry(pci_root_buses.next,
++				struct pci_bus, node);
+ 			if (b)
+ 				dev->hose = b->sysdata;
+ 		}
+@@ -329,14 +250,14 @@
+ 	return 0;
+ 
+ out_close:
++	mutex_unlock(&dev->master_mutex);
+ 	if (dev->driver->postclose)
+ 		dev->driver->postclose(dev, priv);
+ out_prime_destroy:
+ 	if (drm_core_check_feature(dev, DRIVER_PRIME))
+ 		drm_prime_destroy_file_private(&priv->prime);
+-	if (dev->driver->driver_features & DRIVER_GEM)
++	if (drm_core_check_feature(dev, DRIVER_GEM))
+ 		drm_gem_release(dev, priv);
+-out_put_pid:
+ 	put_pid(priv->pid);
+ 	kfree(priv);
+ 	filp->private_data = NULL;
+@@ -347,11 +268,11 @@
+ {
+ 	struct drm_file *file_priv = filp->private_data;
+ 
+-	if (drm_i_have_hw_lock(dev, file_priv)) {
++	if (drm_legacy_i_have_hw_lock(dev, file_priv)) {
+ 		DRM_DEBUG("File %p released, freeing lock for context %d\n",
+ 			  filp, _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
+-		drm_lock_free(&file_priv->master->lock,
+-			      _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
++		drm_legacy_lock_free(&file_priv->master->lock,
++				     _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
+ 	}
+ }
+ 
+@@ -409,8 +330,6 @@
+  */
+ int drm_lastclose(struct drm_device * dev)
+ {
+-	struct drm_vma_entry *vma, *vma_temp;
+-
+ 	DRM_DEBUG("\n");
+ 
+ 	if (dev->driver->lastclose)
+@@ -425,16 +344,9 @@
+ 	drm_agp_clear(dev);
+ 
+ 	drm_legacy_sg_cleanup(dev);
+-
+-	/* Clear vma list (only built for debugging) */
+-	list_for_each_entry_safe(vma, vma_temp, &dev->vmalist, head) {
+-		list_del(&vma->head);
+-		kfree(vma);
+-	}
+-
++	drm_legacy_vma_flush(dev);
+ 	drm_legacy_dma_takedown(dev);
+ 
+-	dev->dev_mapping = NULL;
+ 	mutex_unlock(&dev->struct_mutex);
+ 
+ 	drm_legacy_dev_reinit(dev);
+@@ -458,13 +370,18 @@
+ int drm_release(struct inode *inode, struct file *filp)
+ {
+ 	struct drm_file *file_priv = filp->private_data;
+-	struct drm_device *dev = file_priv->minor->dev;
++	struct drm_minor *minor = file_priv->minor;
++	struct drm_device *dev = minor->dev;
+ 	int retcode = 0;
+ 
+ 	mutex_lock(&drm_global_mutex);
+ 
+ 	DRM_DEBUG("open_count = %d\n", dev->open_count);
+ 
++	mutex_lock(&dev->struct_mutex);
++	list_del(&file_priv->lhead);
++	mutex_unlock(&dev->struct_mutex);
++
+ 	if (dev->driver->preclose)
+ 		dev->driver->preclose(dev, file_priv);
+ 
+@@ -474,7 +391,7 @@
+ 
+ 	DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n",
+ 		  task_pid_nr(current),
+-		  (long)old_encode_dev(file_priv->minor->device),
++		  (long)old_encode_dev(file_priv->minor->kdev->devt),
+ 		  dev->open_count);
+ 
+ 	/* Release any auth tokens that might point to this file_priv,
+@@ -487,52 +404,28 @@
+ 		drm_master_release(dev, filp);
+ 
+ 	if (drm_core_check_feature(dev, DRIVER_HAVE_DMA))
+-		drm_core_reclaim_buffers(dev, file_priv);
++		drm_legacy_reclaim_buffers(dev, file_priv);
+ 
+ 	drm_events_release(file_priv);
+ 
+-	if (dev->driver->driver_features & DRIVER_MODESET)
++	if (drm_core_check_feature(dev, DRIVER_MODESET))
+ 		drm_fb_release(file_priv);
+ 
+-	if (dev->driver->driver_features & DRIVER_GEM)
++	if (drm_core_check_feature(dev, DRIVER_GEM))
+ 		drm_gem_release(dev, file_priv);
+ 
+-	mutex_lock(&dev->ctxlist_mutex);
+-	if (!list_empty(&dev->ctxlist)) {
+-		struct drm_ctx_list *pos, *n;
+-
+-		list_for_each_entry_safe(pos, n, &dev->ctxlist, head) {
+-			if (pos->tag == file_priv &&
+-			    pos->handle != DRM_KERNEL_CONTEXT) {
+-				if (dev->driver->context_dtor)
+-					dev->driver->context_dtor(dev,
+-								  pos->handle);
+-
+-				drm_ctxbitmap_free(dev, pos->handle);
+-
+-				list_del(&pos->head);
+-				kfree(pos);
+-			}
+-		}
+-	}
+-	mutex_unlock(&dev->ctxlist_mutex);
++	drm_legacy_ctxbitmap_flush(dev, file_priv);
+ 
+-	mutex_lock(&dev->struct_mutex);
++	mutex_lock(&dev->master_mutex);
+ 
+ 	if (file_priv->is_master) {
+ 		struct drm_master *master = file_priv->master;
+-		struct drm_file *temp;
+-		list_for_each_entry(temp, &dev->filelist, lhead) {
+-			if ((temp->master == file_priv->master) &&
+-			    (temp != file_priv))
+-				temp->authenticated = temp->always_authenticated;
+-		}
+ 
+ 		/**
+ 		 * Since the master is disappearing, so is the
+ 		 * possibility to lock.
+ 		 */
+-
++		mutex_lock(&dev->struct_mutex);
+ 		if (master->lock.hw_lock) {
+ 			if (dev->sigdata.lock == master->lock.hw_lock)
+ 				dev->sigdata.lock = NULL;
+@@ -540,6 +433,7 @@
+ 			master->lock.file_priv = NULL;
+ 			wake_up_interruptible_all(&master->lock.lock_queue);
+ 		}
++		mutex_unlock(&dev->struct_mutex);
+ 
+ 		if (file_priv->minor->master == file_priv->master) {
+ 			/* drop the reference held my the minor */
+@@ -549,15 +443,11 @@
+ 		}
+ 	}
+ 
+-	BUG_ON(dev->dev_mapping == NULL);
+-	iput(container_of(dev->dev_mapping, struct inode, i_data));
+-
+-	/* drop the reference held my the file priv */
++	/* drop the master reference held by the file priv */
+ 	if (file_priv->master)
+ 		drm_master_put(&file_priv->master);
+ 	file_priv->is_master = 0;
+-	list_del(&file_priv->lhead);
+-	mutex_unlock(&dev->struct_mutex);
++	mutex_unlock(&dev->master_mutex);
+ 
+ 	if (dev->driver->postclose)
+ 		dev->driver->postclose(dev, file_priv);
+@@ -566,6 +456,8 @@
+ 	if (drm_core_check_feature(dev, DRIVER_PRIME))
+ 		drm_prime_destroy_file_private(&file_priv->prime);
+ 
++	WARN_ON(!list_empty(&file_priv->event_list));
++
+ 	put_pid(file_priv->pid);
+ 	kfree(file_priv);
+ 
+@@ -580,6 +472,8 @@
+ 	}
+ 	mutex_unlock(&drm_global_mutex);
+ 
++	drm_minor_release(minor);
++
+ 	return retcode;
+ }
+ EXPORT_SYMBOL(drm_release);
+@@ -621,16 +515,19 @@
+ 	size_t total;
+ 	ssize_t ret;
+ 
+-	ret = wait_event_interruptible(file_priv->event_wait,
+-				       !list_empty(&file_priv->event_list));
+-	if (ret < 0)
+-		return ret;
++	if ((filp->f_flags & O_NONBLOCK) == 0) {
++		ret = wait_event_interruptible(file_priv->event_wait,
++					       !list_empty(&file_priv->event_list));
++		if (ret < 0)
++			return ret;
++	}
+ 
+ 	total = 0;
+ 	while (drm_dequeue_event(file_priv, total, count, &e)) {
+ 		if (copy_to_user(buffer + total,
+ 				 e->event, e->event->length)) {
+ 			total = -EFAULT;
++			e->destroy(e);
+ 			break;
+ 		}
+ 
+@@ -638,7 +535,7 @@
+ 		e->destroy(e);
+ 	}
+ 
+-	return total;
++	return total ?: -EAGAIN;
+ }
+ EXPORT_SYMBOL(drm_read);
+ 
+diff -Naur a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
+--- a/drivers/gpu/drm/drm_gem.c	2015-03-26 14:43:30.462436436 +0530
++++ b/drivers/gpu/drm/drm_gem.c	2015-03-26 14:42:38.726435422 +0530
+@@ -38,6 +38,8 @@
+ #include <linux/dma-buf.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_vma_manager.h>
++#include <drm/drm_gem.h>
++#include "drm_internal.h"
+ 
+ /** @file drm_gem.c
+  *
+@@ -85,9 +87,9 @@
+ #endif
+ 
+ /**
+- * Initialize the GEM device fields
++ * drm_gem_init - Initialize the GEM device fields
++ * @dev: drm_devic structure to initialize
+  */
+-
+ int
+ drm_gem_init(struct drm_device *dev)
+ {
+@@ -120,6 +122,11 @@
+ }
+ 
+ /**
++ * drm_gem_object_init - initialize an allocated shmem-backed GEM object
++ * @dev: drm_device the object should be initialized for
++ * @obj: drm_gem_object to initialize
++ * @size: object size
++ *
+  * Initialize an already allocated GEM object of the specified size with
+  * shmfs backing store.
+  */
+@@ -141,6 +148,11 @@
+ EXPORT_SYMBOL(drm_gem_object_init);
+ 
+ /**
++ * drm_gem_private_object_init - initialize an allocated private GEM object
++ * @dev: drm_device the object should be initialized for
++ * @obj: drm_gem_object to initialize
++ * @size: object size
++ *
+  * Initialize an already allocated GEM object of the specified size with
+  * no GEM provided backing store. Instead the caller is responsible for
+  * backing the object and handling it.
+@@ -176,6 +188,9 @@
+ }
+ 
+ /**
++ * drm_gem_object_handle_free - release resources bound to userspace handles
++ * @obj: GEM object to clean up.
++ *
+  * Called after the last handle to the object has been closed
+  *
+  * Removes any name for the object. Note that this must be
+@@ -225,7 +240,12 @@
+ }
+ 
+ /**
+- * Removes the mapping from handle to filp for this object.
++ * drm_gem_handle_delete - deletes the given file-private handle
++ * @filp: drm file-private structure to use for the handle look up
++ * @handle: userspace handle to delete
++ *
++ * Removes the GEM handle from the @filp lookup table and if this is the last
++ * handle also cleans up linked resources like GEM names.
+  */
+ int
+ drm_gem_handle_delete(struct drm_file *filp, u32 handle)
+@@ -270,6 +290,9 @@
+ 
+ /**
+  * drm_gem_dumb_destroy - dumb fb callback helper for gem based drivers
++ * @file: drm file-private structure to remove the dumb handle from
++ * @dev: corresponding drm_device
++ * @handle: the dumb handle to remove
+  * 
+  * This implements the ->dumb_destroy kms driver callback for drivers which use
+  * gem to manage their backing storage.
+@@ -284,6 +307,9 @@
+ 
+ /**
+  * drm_gem_handle_create_tail - internal functions to create a handle
++ * @file_priv: drm file-private structure to register the handle for
++ * @obj: object to register
++ * @handlep: pointer to return the created handle to the caller
+  * 
+  * This expects the dev->object_name_lock to be held already and will drop it
+  * before returning. Used to avoid races in establishing new handles when
+@@ -336,14 +362,18 @@
+ }
+ 
+ /**
++ * drm_gem_handle_create - create a gem handle for an object
++ * @file_priv: drm file-private structure to register the handle for
++ * @obj: object to register
++ * @handlep: pionter to return the created handle to the caller
++ *
+  * Create a handle for this object. This adds a handle reference
+  * to the object, which includes a regular reference count. Callers
+  * will likely want to dereference the object afterwards.
+  */
+-int
+-drm_gem_handle_create(struct drm_file *file_priv,
+-		       struct drm_gem_object *obj,
+-		       u32 *handlep)
++int drm_gem_handle_create(struct drm_file *file_priv,
++			  struct drm_gem_object *obj,
++			  u32 *handlep)
+ {
+ 	mutex_lock(&obj->dev->object_name_lock);
+ 
+@@ -412,18 +442,31 @@
+  * drm_gem_get_pages - helper to allocate backing pages for a GEM object
+  * from shmem
+  * @obj: obj in question
+- * @gfpmask: gfp mask of requested pages
++ *
++ * This reads the page-array of the shmem-backing storage of the given gem
++ * object. An array of pages is returned. If a page is not allocated or
++ * swapped-out, this will allocate/swap-in the required pages. Note that the
++ * whole object is covered by the page-array and pinned in memory.
++ *
++ * Use drm_gem_put_pages() to release the array and unpin all pages.
++ *
++ * This uses the GFP-mask set on the shmem-mapping (see mapping_set_gfp_mask()).
++ * If you require other GFP-masks, you have to do those allocations yourself.
++ *
++ * Note that you are not allowed to change gfp-zones during runtime. That is,
++ * shmem_read_mapping_page_gfp() must be called with the same gfp_zone(gfp) as
++ * set during initialization. If you have special zone constraints, set them
++ * after drm_gem_init_object() via mapping_set_gfp_mask(). shmem-core takes care
++ * to keep pages in the required zone during swap-in.
+  */
+-struct page **drm_gem_get_pages(struct drm_gem_object *obj, gfp_t gfpmask)
++struct page **drm_gem_get_pages(struct drm_gem_object *obj)
+ {
+-	struct inode *inode;
+ 	struct address_space *mapping;
+ 	struct page *p, **pages;
+ 	int i, npages;
+ 
+ 	/* This is the shared memory object that backs the GEM resource */
+-	inode = file_inode(obj->filp);
+-	mapping = inode->i_mapping;
++	mapping = file_inode(obj->filp)->i_mapping;
+ 
+ 	/* We already BUG_ON() for non-page-aligned sizes in
+ 	 * drm_gem_object_init(), so we should never hit this unless
+@@ -437,31 +480,18 @@
+ 	if (pages == NULL)
+ 		return ERR_PTR(-ENOMEM);
+ 
+-	gfpmask |= mapping_gfp_mask(mapping);
+-
+ 	for (i = 0; i < npages; i++) {
+-		p = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
++		p = shmem_read_mapping_page(mapping, i);
+ 		if (IS_ERR(p))
+ 			goto fail;
+ 		pages[i] = p;
+ 
+-		/* There is a hypothetical issue w/ drivers that require
+-		 * buffer memory in the low 4GB.. if the pages are un-
+-		 * pinned, and swapped out, they can end up swapped back
+-		 * in above 4GB.  If pages are already in memory, then
+-		 * shmem_read_mapping_page_gfp will ignore the gfpmask,
+-		 * even if the already in-memory page disobeys the mask.
+-		 *
+-		 * It is only a theoretical issue today, because none of
+-		 * the devices with this limitation can be populated with
+-		 * enough memory to trigger the issue.  But this BUG_ON()
+-		 * is here as a reminder in case the problem with
+-		 * shmem_read_mapping_page_gfp() isn't solved by the time
+-		 * it does become a real issue.
+-		 *
+-		 * See this thread: http://lkml.org/lkml/2011/7/11/238
++		/* Make sure shmem keeps __GFP_DMA32 allocated pages in the
++		 * correct region during swapin. Note that this requires
++		 * __GFP_DMA32 to be set in mapping_gfp_mask(inode->i_mapping)
++		 * so shmem can relocate pages during swapin if required.
+ 		 */
+-		BUG_ON((gfpmask & __GFP_DMA32) &&
++		BUG_ON((mapping_gfp_mask(mapping) & __GFP_DMA32) &&
+ 				(page_to_pfn(p) >= 0x00100000UL));
+ 	}
+ 
+@@ -536,6 +566,11 @@
+ EXPORT_SYMBOL(drm_gem_object_lookup);
+ 
+ /**
++ * drm_gem_close_ioctl - implementation of the GEM_CLOSE ioctl
++ * @dev: drm_device
++ * @data: ioctl data
++ * @file_priv: drm file-private structure
++ *
+  * Releases the handle to an mm object.
+  */
+ int
+@@ -545,7 +580,7 @@
+ 	struct drm_gem_close *args = data;
+ 	int ret;
+ 
+-	if (!(dev->driver->driver_features & DRIVER_GEM))
++	if (!drm_core_check_feature(dev, DRIVER_GEM))
+ 		return -ENODEV;
+ 
+ 	ret = drm_gem_handle_delete(file_priv, args->handle);
+@@ -554,6 +589,11 @@
+ }
+ 
+ /**
++ * drm_gem_flink_ioctl - implementation of the GEM_FLINK ioctl
++ * @dev: drm_device
++ * @data: ioctl data
++ * @file_priv: drm file-private structure
++ *
+  * Create a global name for an object, returning the name.
+  *
+  * Note that the name does not hold a reference; when the object
+@@ -567,7 +607,7 @@
+ 	struct drm_gem_object *obj;
+ 	int ret;
+ 
+-	if (!(dev->driver->driver_features & DRIVER_GEM))
++	if (!drm_core_check_feature(dev, DRIVER_GEM))
+ 		return -ENODEV;
+ 
+ 	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
+@@ -601,6 +641,11 @@
+ }
+ 
+ /**
++ * drm_gem_open - implementation of the GEM_OPEN ioctl
++ * @dev: drm_device
++ * @data: ioctl data
++ * @file_priv: drm file-private structure
++ *
+  * Open an object using the global name, returning a handle and the size.
+  *
+  * This handle (of course) holds a reference to the object, so the object
+@@ -615,7 +660,7 @@
+ 	int ret;
+ 	u32 handle;
+ 
+-	if (!(dev->driver->driver_features & DRIVER_GEM))
++	if (!drm_core_check_feature(dev, DRIVER_GEM))
+ 		return -ENODEV;
+ 
+ 	mutex_lock(&dev->object_name_lock);
+@@ -640,6 +685,10 @@
+ }
+ 
+ /**
++ * gem_gem_open - initalizes GEM file-private structures at devnode open time
++ * @dev: drm_device which is being opened by userspace
++ * @file_private: drm file-private structure to set up
++ *
+  * Called at device open time, sets up the structure for handling refcounting
+  * of mm objects.
+  */
+@@ -650,7 +699,7 @@
+ 	spin_lock_init(&file_private->table_lock);
+ }
+ 
+-/**
++/*
+  * Called at device close to release the file's
+  * handle references on objects.
+  */
+@@ -674,6 +723,10 @@
+ }
+ 
+ /**
++ * drm_gem_release - release file-private GEM resources
++ * @dev: drm_device which is being closed by userspace
++ * @file_private: drm file-private structure to clean up
++ *
+  * Called at close time when the filp is going away.
+  *
+  * Releases any remaining references on objects by this filp.
+@@ -692,11 +745,16 @@
+ 	WARN_ON(obj->dma_buf);
+ 
+ 	if (obj->filp)
+-	    fput(obj->filp);
++		fput(obj->filp);
++
++	drm_gem_free_mmap_offset(obj);
+ }
+ EXPORT_SYMBOL(drm_gem_object_release);
+ 
+ /**
++ * drm_gem_object_free - free a GEM object
++ * @kref: kref of the object to free
++ *
+  * Called after the last reference to the object has been lost.
+  * Must be called holding struct_ mutex
+  *
+@@ -782,7 +840,7 @@
+ 	vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
+ 	vma->vm_ops = dev->driver->gem_vm_ops;
+ 	vma->vm_private_data = obj;
+-	vma->vm_page_prot =  pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
++	vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
+ 
+ 	/* Take a ref for this mapping of the object, so that the fault
+ 	 * handler can dereference the mmap offset's pointer to the object.
+@@ -818,7 +876,7 @@
+ 	struct drm_device *dev = priv->minor->dev;
+ 	struct drm_gem_object *obj;
+ 	struct drm_vma_offset_node *node;
+-	int ret = 0;
++	int ret;
+ 
+ 	if (drm_device_is_unplugged(dev))
+ 		return -ENODEV;
+@@ -830,7 +888,7 @@
+ 					   vma_pages(vma));
+ 	if (!node) {
+ 		mutex_unlock(&dev->struct_mutex);
+-		return drm_mmap(filp, vma);
++		return -EINVAL;
+ 	} else if (!drm_vma_node_is_allowed(node, filp)) {
+ 		mutex_unlock(&dev->struct_mutex);
+ 		return -EACCES;
+diff -Naur a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c
+--- a/drivers/gpu/drm/drm_gem_cma_helper.c	2015-03-26 14:43:30.418436435 +0530
++++ b/drivers/gpu/drm/drm_gem_cma_helper.c	2015-03-26 14:42:38.726435422 +0530
+@@ -29,18 +29,31 @@
+ #include <drm/drm_gem_cma_helper.h>
+ #include <drm/drm_vma_manager.h>
+ 
+-/*
++/**
++ * DOC: cma helpers
++ *
++ * The Contiguous Memory Allocator reserves a pool of memory at early boot
++ * that is used to service requests for large blocks of contiguous memory.
++ *
++ * The DRM GEM/CMA helpers use this allocator as a means to provide buffer
++ * objects that are physically contiguous in memory. This is useful for
++ * display drivers that are unable to map scattered buffers via an IOMMU.
++ */
++
++/**
+  * __drm_gem_cma_create - Create a GEM CMA object without allocating memory
+- * @drm: The drm device
+- * @size: The GEM object size
++ * @drm: DRM device
++ * @size: size of the object to allocate
+  *
+- * This function creates and initializes a GEM CMA object of the given size, but
+- * doesn't allocate any memory to back the object.
++ * This function creates and initializes a GEM CMA object of the given size,
++ * but doesn't allocate any memory to back the object.
+  *
+- * Return a struct drm_gem_cma_object* on success or ERR_PTR values on failure.
++ * Returns:
++ * A struct drm_gem_cma_object * on success or an ERR_PTR()-encoded negative
++ * error code on failure.
+  */
+ static struct drm_gem_cma_object *
+-__drm_gem_cma_create(struct drm_device *drm, unsigned int size)
++__drm_gem_cma_create(struct drm_device *drm, size_t size)
+ {
+ 	struct drm_gem_cma_object *cma_obj;
+ 	struct drm_gem_object *gem_obj;
+@@ -69,17 +82,23 @@
+ 	return ERR_PTR(ret);
+ }
+ 
+-/*
++/**
+  * drm_gem_cma_create - allocate an object with the given size
++ * @drm: DRM device
++ * @size: size of the object to allocate
+  *
+- * returns a struct drm_gem_cma_object* on success or ERR_PTR values
+- * on failure.
++ * This function creates a CMA GEM object and allocates a contiguous chunk of
++ * memory as backing store. The backing memory has the writecombine attribute
++ * set.
++ *
++ * Returns:
++ * A struct drm_gem_cma_object * on success or an ERR_PTR()-encoded negative
++ * error code on failure.
+  */
+ struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm,
+-		unsigned int size)
++					      size_t size)
+ {
+ 	struct drm_gem_cma_object *cma_obj;
+-	struct sg_table *sgt = NULL;
+ 	int ret;
+ 
+ 	size = round_up(size, PAGE_SIZE);
+@@ -97,39 +116,34 @@
+ 		goto error;
+ 	}
+ 
+-	sgt = kzalloc(sizeof(*cma_obj->sgt), GFP_KERNEL);
+-	if (sgt == NULL) {
+-		ret = -ENOMEM;
+-		goto error;
+-	}
+-
+-	ret = dma_get_sgtable(drm->dev, sgt, cma_obj->vaddr,
+-			      cma_obj->paddr, size);
+-	if (ret < 0)
+-		goto error;
+-
+-	cma_obj->sgt = sgt;
+-
+ 	return cma_obj;
+ 
+ error:
+-	kfree(sgt);
+ 	drm_gem_cma_free_object(&cma_obj->base);
+ 	return ERR_PTR(ret);
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_create);
+ 
+-/*
+- * drm_gem_cma_create_with_handle - allocate an object with the given
+- * size and create a gem handle on it
+- *
+- * returns a struct drm_gem_cma_object* on success or ERR_PTR values
+- * on failure.
+- */
+-static struct drm_gem_cma_object *drm_gem_cma_create_with_handle(
+-		struct drm_file *file_priv,
+-		struct drm_device *drm, unsigned int size,
+-		unsigned int *handle)
++/**
++ * drm_gem_cma_create_with_handle - allocate an object with the given size and
++ *     return a GEM handle to it
++ * @file_priv: DRM file-private structure to register the handle for
++ * @drm: DRM device
++ * @size: size of the object to allocate
++ * @handle: return location for the GEM handle
++ *
++ * This function creates a CMA GEM object, allocating a physically contiguous
++ * chunk of memory as backing store. The GEM object is then added to the list
++ * of object associated with the given file and a handle to it is returned.
++ *
++ * Returns:
++ * A struct drm_gem_cma_object * on success or an ERR_PTR()-encoded negative
++ * error code on failure.
++ */
++static struct drm_gem_cma_object *
++drm_gem_cma_create_with_handle(struct drm_file *file_priv,
++			       struct drm_device *drm, size_t size,
++			       uint32_t *handle)
+ {
+ 	struct drm_gem_cma_object *cma_obj;
+ 	struct drm_gem_object *gem_obj;
+@@ -160,25 +174,24 @@
+ 	return ERR_PTR(ret);
+ }
+ 
+-/*
+- * drm_gem_cma_free_object - (struct drm_driver)->gem_free_object callback
+- * function
++/**
++ * drm_gem_cma_free_object - free resources associated with a CMA GEM object
++ * @gem_obj: GEM object to free
++ *
++ * This function frees the backing memory of the CMA GEM object, cleans up the
++ * GEM object state and frees the memory used to store the object itself.
++ * Drivers using the CMA helpers should set this as their DRM driver's
++ * ->gem_free_object() callback.
+  */
+ void drm_gem_cma_free_object(struct drm_gem_object *gem_obj)
+ {
+ 	struct drm_gem_cma_object *cma_obj;
+ 
+-	drm_gem_free_mmap_offset(gem_obj);
+-
+ 	cma_obj = to_drm_gem_cma_obj(gem_obj);
+ 
+ 	if (cma_obj->vaddr) {
+ 		dma_free_writecombine(gem_obj->dev->dev, cma_obj->base.size,
+ 				      cma_obj->vaddr, cma_obj->paddr);
+-		if (cma_obj->sgt) {
+-			sg_free_table(cma_obj->sgt);
+-			kfree(cma_obj->sgt);
+-		}
+ 	} else if (gem_obj->import_attach) {
+ 		drm_prime_gem_destroy(gem_obj, cma_obj->sgt);
+ 	}
+@@ -189,18 +202,26 @@
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_free_object);
+ 
+-/*
+- * drm_gem_cma_dumb_create - (struct drm_driver)->dumb_create callback
+- * function
++/**
++ * drm_gem_cma_dumb_create_internal - create a dumb buffer object
++ * @file_priv: DRM file-private structure to create the dumb buffer for
++ * @drm: DRM device
++ * @args: IOCTL data
++ *
++ * This aligns the pitch and size arguments to the minimum required. This is
++ * an internal helper that can be wrapped by a driver to account for hardware
++ * with more specific alignment requirements. It should not be used directly
++ * as the ->dumb_create() callback in a DRM driver.
+  *
+- * This aligns the pitch and size arguments to the minimum required. wrap
+- * this into your own function if you need bigger alignment.
++ * Returns:
++ * 0 on success or a negative error code on failure.
+  */
+-int drm_gem_cma_dumb_create(struct drm_file *file_priv,
+-		struct drm_device *dev, struct drm_mode_create_dumb *args)
++int drm_gem_cma_dumb_create_internal(struct drm_file *file_priv,
++				     struct drm_device *drm,
++				     struct drm_mode_create_dumb *args)
+ {
++	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+ 	struct drm_gem_cma_object *cma_obj;
+-	int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+ 
+ 	if (args->pitch < min_pitch)
+ 		args->pitch = min_pitch;
+@@ -208,18 +229,63 @@
+ 	if (args->size < args->pitch * args->height)
+ 		args->size = args->pitch * args->height;
+ 
+-	cma_obj = drm_gem_cma_create_with_handle(file_priv, dev,
+-			args->size, &args->handle);
++	cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, args->size,
++						 &args->handle);
++	return PTR_ERR_OR_ZERO(cma_obj);
++}
++EXPORT_SYMBOL_GPL(drm_gem_cma_dumb_create_internal);
++
++/**
++ * drm_gem_cma_dumb_create - create a dumb buffer object
++ * @file_priv: DRM file-private structure to create the dumb buffer for
++ * @drm: DRM device
++ * @args: IOCTL data
++ *
++ * This function computes the pitch of the dumb buffer and rounds it up to an
++ * integer number of bytes per pixel. Drivers for hardware that doesn't have
++ * any additional restrictions on the pitch can directly use this function as
++ * their ->dumb_create() callback.
++ *
++ * For hardware with additional restrictions, drivers can adjust the fields
++ * set up by userspace and pass the IOCTL data along to the
++ * drm_gem_cma_dumb_create_internal() function.
++ *
++ * Returns:
++ * 0 on success or a negative error code on failure.
++ */
++int drm_gem_cma_dumb_create(struct drm_file *file_priv,
++			    struct drm_device *drm,
++			    struct drm_mode_create_dumb *args)
++{
++	struct drm_gem_cma_object *cma_obj;
++
++	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
++	args->size = args->pitch * args->height;
++
++	cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, args->size,
++						 &args->handle);
+ 	return PTR_ERR_OR_ZERO(cma_obj);
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_dumb_create);
+ 
+-/*
+- * drm_gem_cma_dumb_map_offset - (struct drm_driver)->dumb_map_offset callback
+- * function
++/**
++ * drm_gem_cma_dumb_map_offset - return the fake mmap offset for a CMA GEM
++ *     object
++ * @file_priv: DRM file-private structure containing the GEM object
++ * @drm: DRM device
++ * @handle: GEM object handle
++ * @offset: return location for the fake mmap offset
++ *
++ * This function look up an object by its handle and returns the fake mmap
++ * offset associated with it. Drivers using the CMA helpers should set this
++ * as their DRM driver's ->dumb_map_offset() callback.
++ *
++ * Returns:
++ * 0 on success or a negative error code on failure.
+  */
+ int drm_gem_cma_dumb_map_offset(struct drm_file *file_priv,
+-		struct drm_device *drm, uint32_t handle, uint64_t *offset)
++				struct drm_device *drm, u32 handle,
++				u64 *offset)
+ {
+ 	struct drm_gem_object *gem_obj;
+ 
+@@ -227,7 +293,7 @@
+ 
+ 	gem_obj = drm_gem_object_lookup(drm, file_priv, handle);
+ 	if (!gem_obj) {
+-		dev_err(drm->dev, "failed to lookup gem object\n");
++		dev_err(drm->dev, "failed to lookup GEM object\n");
+ 		mutex_unlock(&drm->struct_mutex);
+ 		return -EINVAL;
+ 	}
+@@ -253,16 +319,37 @@
+ {
+ 	int ret;
+ 
+-	ret = remap_pfn_range(vma, vma->vm_start, cma_obj->paddr >> PAGE_SHIFT,
+-			vma->vm_end - vma->vm_start, vma->vm_page_prot);
++	/*
++	 * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
++	 * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
++	 * the whole buffer.
++	 */
++	vma->vm_flags &= ~VM_PFNMAP;
++	vma->vm_pgoff = 0;
++
++	ret = dma_mmap_writecombine(cma_obj->base.dev->dev, vma,
++				    cma_obj->vaddr, cma_obj->paddr,
++				    vma->vm_end - vma->vm_start);
+ 	if (ret)
+ 		drm_gem_vm_close(vma);
+ 
+ 	return ret;
+ }
+ 
+-/*
+- * drm_gem_cma_mmap - (struct file_operation)->mmap callback function
++/**
++ * drm_gem_cma_mmap - memory-map a CMA GEM object
++ * @filp: file object
++ * @vma: VMA for the area to be mapped
++ *
++ * This function implements an augmented version of the GEM DRM file mmap
++ * operation for CMA objects: In addition to the usual GEM VMA setup it
++ * immediately faults in the entire object instead of using on-demaind
++ * faulting. Drivers which employ the CMA helpers should use this function
++ * as their ->mmap() handler in the DRM device file's file_operations
++ * structure.
++ *
++ * Returns:
++ * 0 on success or a negative error code on failure.
+  */
+ int drm_gem_cma_mmap(struct file *filp, struct vm_area_struct *vma)
+ {
+@@ -282,7 +369,16 @@
+ EXPORT_SYMBOL_GPL(drm_gem_cma_mmap);
+ 
+ #ifdef CONFIG_DEBUG_FS
+-void drm_gem_cma_describe(struct drm_gem_cma_object *cma_obj, struct seq_file *m)
++/**
++ * drm_gem_cma_describe - describe a CMA GEM object for debugfs
++ * @cma_obj: CMA GEM object
++ * @m: debugfs file handle
++ *
++ * This function can be used to dump a human-readable representation of the
++ * CMA GEM object into a synthetic file.
++ */
++void drm_gem_cma_describe(struct drm_gem_cma_object *cma_obj,
++			  struct seq_file *m)
+ {
+ 	struct drm_gem_object *obj = &cma_obj->base;
+ 	struct drm_device *dev = obj->dev;
+@@ -292,16 +388,27 @@
+ 
+ 	off = drm_vma_node_start(&obj->vma_node);
+ 
+-	seq_printf(m, "%2d (%2d) %08llx %08Zx %p %d",
++	seq_printf(m, "%2d (%2d) %08llx %pad %p %d",
+ 			obj->name, obj->refcount.refcount.counter,
+-			off, cma_obj->paddr, cma_obj->vaddr, obj->size);
++			off, &cma_obj->paddr, cma_obj->vaddr, obj->size);
+ 
+ 	seq_printf(m, "\n");
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_describe);
+ #endif
+ 
+-/* low-level interface prime helpers */
++/**
++ * drm_gem_cma_prime_get_sg_table - provide a scatter/gather table of pinned
++ *     pages for a CMA GEM object
++ * @obj: GEM object
++ *
++ * This function exports a scatter/gather table suitable for PRIME usage by
++ * calling the standard DMA mapping API. Drivers using the CMA helpers should
++ * set this as their DRM driver's ->gem_prime_get_sg_table() callback.
++ *
++ * Returns:
++ * A pointer to the scatter/gather table of pinned pages or NULL on failure.
++ */
+ struct sg_table *drm_gem_cma_prime_get_sg_table(struct drm_gem_object *obj)
+ {
+ 	struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj);
+@@ -325,8 +432,26 @@
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_prime_get_sg_table);
+ 
++/**
++ * drm_gem_cma_prime_import_sg_table - produce a CMA GEM object from another
++ *     driver's scatter/gather table of pinned pages
++ * @dev: device to import into
++ * @attach: DMA-BUF attachment
++ * @sgt: scatter/gather table of pinned pages
++ *
++ * This function imports a scatter/gather table exported via DMA-BUF by
++ * another driver. Imported buffers must be physically contiguous in memory
++ * (i.e. the scatter/gather table must contain a single entry). Drivers that
++ * use the CMA helpers should set this as their DRM driver's
++ * ->gem_prime_import_sg_table() callback.
++ *
++ * Returns:
++ * A pointer to a newly created GEM object or an ERR_PTR-encoded negative
++ * error code on failure.
++ */
+ struct drm_gem_object *
+-drm_gem_cma_prime_import_sg_table(struct drm_device *dev, size_t size,
++drm_gem_cma_prime_import_sg_table(struct drm_device *dev,
++				  struct dma_buf_attachment *attach,
+ 				  struct sg_table *sgt)
+ {
+ 	struct drm_gem_cma_object *cma_obj;
+@@ -335,19 +460,31 @@
+ 		return ERR_PTR(-EINVAL);
+ 
+ 	/* Create a CMA GEM buffer. */
+-	cma_obj = __drm_gem_cma_create(dev, size);
++	cma_obj = __drm_gem_cma_create(dev, attach->dmabuf->size);
+ 	if (IS_ERR(cma_obj))
+-		return ERR_PTR(PTR_ERR(cma_obj));
++		return ERR_CAST(cma_obj);
+ 
+ 	cma_obj->paddr = sg_dma_address(sgt->sgl);
+ 	cma_obj->sgt = sgt;
+ 
+-	DRM_DEBUG_PRIME("dma_addr = 0x%x, size = %zu\n", cma_obj->paddr, size);
++	DRM_DEBUG_PRIME("dma_addr = %pad, size = %zu\n", &cma_obj->paddr, attach->dmabuf->size);
+ 
+ 	return &cma_obj->base;
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_prime_import_sg_table);
+ 
++/**
++ * drm_gem_cma_prime_mmap - memory-map an exported CMA GEM object
++ * @obj: GEM object
++ * @vma: VMA for the area to be mapped
++ *
++ * This function maps a buffer imported via DRM PRIME into a userspace
++ * process's address space. Drivers that use the CMA helpers should set this
++ * as their DRM driver's ->gem_prime_mmap() callback.
++ *
++ * Returns:
++ * 0 on success or a negative error code on failure.
++ */
+ int drm_gem_cma_prime_mmap(struct drm_gem_object *obj,
+ 			   struct vm_area_struct *vma)
+ {
+@@ -366,6 +503,20 @@
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_prime_mmap);
+ 
++/**
++ * drm_gem_cma_prime_vmap - map a CMA GEM object into the kernel's virtual
++ *     address space
++ * @obj: GEM object
++ *
++ * This function maps a buffer exported via DRM PRIME into the kernel's
++ * virtual address space. Since the CMA buffers are already mapped into the
++ * kernel virtual address space this simply returns the cached virtual
++ * address. Drivers using the CMA helpers should set this as their DRM
++ * driver's ->gem_prime_vmap() callback.
++ *
++ * Returns:
++ * The kernel virtual address of the CMA GEM object's backing store.
++ */
+ void *drm_gem_cma_prime_vmap(struct drm_gem_object *obj)
+ {
+ 	struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj);
+@@ -374,6 +525,17 @@
+ }
+ EXPORT_SYMBOL_GPL(drm_gem_cma_prime_vmap);
+ 
++/**
++ * drm_gem_cma_prime_vunmap - unmap a CMA GEM object from the kernel's virtual
++ *     address space
++ * @obj: GEM object
++ * @vaddr: kernel virtual address where the CMA GEM object was mapped
++ *
++ * This function removes a buffer exported via DRM PRIME from the kernel's
++ * virtual address space. This is a no-op because CMA buffers cannot be
++ * unmapped from kernel space. Drivers using the CMA helpers should set this
++ * as their DRM driver's ->gem_prime_vunmap() callback.
++ */
+ void drm_gem_cma_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
+ {
+ 	/* Nothing to do */
+diff -Naur a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c
+--- a/drivers/gpu/drm/drm_info.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/drm_info.c	2015-03-26 14:42:38.726435422 +0530
+@@ -35,6 +35,9 @@
+ 
+ #include <linux/seq_file.h>
+ #include <drm/drmP.h>
++#include <drm/drm_gem.h>
++
++#include "drm_legacy.h"
+ 
+ /**
+  * Called when "/proc/dri/.../name" is read.
+@@ -47,18 +50,16 @@
+ 	struct drm_minor *minor = node->minor;
+ 	struct drm_device *dev = minor->dev;
+ 	struct drm_master *master = minor->master;
+-	const char *bus_name;
+ 	if (!master)
+ 		return 0;
+ 
+-	bus_name = dev->driver->bus->get_name(dev);
+ 	if (master->unique) {
+ 		seq_printf(m, "%s %s %s\n",
+-			   bus_name,
++			   dev->driver->name,
+ 			   dev_name(dev->dev), master->unique);
+ 	} else {
+ 		seq_printf(m, "%s %s\n",
+-			   bus_name, dev_name(dev->dev));
++			   dev->driver->name, dev_name(dev->dev));
+ 	}
+ 	return 0;
+ }
+@@ -134,7 +135,7 @@
+ 				   i,
+ 				   dma->bufs[i].buf_size,
+ 				   dma->bufs[i].buf_count,
+-				   atomic_read(&dma->bufs[i].freelist.count),
++				   0,
+ 				   dma->bufs[i].seg_count,
+ 				   seg_pages,
+ 				   seg_pages * PAGE_SIZE / 1024);
+@@ -185,15 +186,32 @@
+ 	struct drm_device *dev = node->minor->dev;
+ 	struct drm_file *priv;
+ 
++	seq_printf(m,
++		   "%20s %5s %3s master a %5s %10s\n",
++		   "command",
++		   "pid",
++		   "dev",
++		   "uid",
++		   "magic");
++
++	/* dev->filelist is sorted youngest first, but we want to present
++	 * oldest first (i.e. kernel, servers, clients), so walk backwardss.
++	 */
+ 	mutex_lock(&dev->struct_mutex);
+-	seq_printf(m, "a dev	pid    uid	magic\n\n");
+-	list_for_each_entry(priv, &dev->filelist, lhead) {
+-		seq_printf(m, "%c %3d %5d %5d %10u\n",
+-			   priv->authenticated ? 'y' : 'n',
+-			   priv->minor->index,
++	list_for_each_entry_reverse(priv, &dev->filelist, lhead) {
++		struct task_struct *task;
++
++		rcu_read_lock(); /* locks pid_task()->comm */
++		task = pid_task(priv->pid, PIDTYPE_PID);
++		seq_printf(m, "%20s %5d %3d   %c    %c %5d %10u\n",
++			   task ? task->comm : "<unknown>",
+ 			   pid_vnr(priv->pid),
++			   priv->minor->index,
++			   priv->is_master ? 'y' : 'n',
++			   priv->authenticated ? 'y' : 'n',
+ 			   from_kuid_munged(seq_user_ns(m), priv->uid),
+ 			   priv->magic);
++		rcu_read_unlock();
+ 	}
+ 	mutex_unlock(&dev->struct_mutex);
+ 	return 0;
+@@ -225,62 +243,3 @@
+ 
+ 	return 0;
+ }
+-
+-#if DRM_DEBUG_CODE
+-
+-int drm_vma_info(struct seq_file *m, void *data)
+-{
+-	struct drm_info_node *node = (struct drm_info_node *) m->private;
+-	struct drm_device *dev = node->minor->dev;
+-	struct drm_vma_entry *pt;
+-	struct vm_area_struct *vma;
+-	unsigned long vma_count = 0;
+-#if defined(__i386__)
+-	unsigned int pgprot;
+-#endif
+-
+-	mutex_lock(&dev->struct_mutex);
+-	list_for_each_entry(pt, &dev->vmalist, head)
+-		vma_count++;
+-
+-	seq_printf(m, "vma use count: %lu, high_memory = %pK, 0x%pK\n",
+-		   vma_count, high_memory,
+-		   (void *)(unsigned long)virt_to_phys(high_memory));
+-
+-	list_for_each_entry(pt, &dev->vmalist, head) {
+-		vma = pt->vma;
+-		if (!vma)
+-			continue;
+-		seq_printf(m,
+-			   "\n%5d 0x%pK-0x%pK %c%c%c%c%c%c 0x%08lx000",
+-			   pt->pid,
+-			   (void *)vma->vm_start, (void *)vma->vm_end,
+-			   vma->vm_flags & VM_READ ? 'r' : '-',
+-			   vma->vm_flags & VM_WRITE ? 'w' : '-',
+-			   vma->vm_flags & VM_EXEC ? 'x' : '-',
+-			   vma->vm_flags & VM_MAYSHARE ? 's' : 'p',
+-			   vma->vm_flags & VM_LOCKED ? 'l' : '-',
+-			   vma->vm_flags & VM_IO ? 'i' : '-',
+-			   vma->vm_pgoff);
+-
+-#if defined(__i386__)
+-		pgprot = pgprot_val(vma->vm_page_prot);
+-		seq_printf(m, " %c%c%c%c%c%c%c%c%c",
+-			   pgprot & _PAGE_PRESENT ? 'p' : '-',
+-			   pgprot & _PAGE_RW ? 'w' : 'r',
+-			   pgprot & _PAGE_USER ? 'u' : 's',
+-			   pgprot & _PAGE_PWT ? 't' : 'b',
+-			   pgprot & _PAGE_PCD ? 'u' : 'c',
+-			   pgprot & _PAGE_ACCESSED ? 'a' : '-',
+-			   pgprot & _PAGE_DIRTY ? 'd' : '-',
+-			   pgprot & _PAGE_PSE ? 'm' : 'k',
+-			   pgprot & _PAGE_GLOBAL ? 'g' : 'l');
+-#endif
+-		seq_printf(m, "\n");
+-	}
+-	mutex_unlock(&dev->struct_mutex);
+-	return 0;
+-}
+-
+-#endif
+-
+diff -Naur a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
+--- a/drivers/gpu/drm/drm_internal.h	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_internal.h	2015-03-26 14:42:38.726435422 +0530
+@@ -0,0 +1,132 @@
++/*
++ * Copyright © 2014 Intel Corporation
++ *   Daniel Vetter <daniel.vetter@ffwll.ch>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/* drm_irq.c */
++extern unsigned int drm_timestamp_monotonic;
++
++/* drm_fops.c */
++extern struct mutex drm_global_mutex;
++int drm_lastclose(struct drm_device *dev);
++
++/* drm_pci.c */
++int drm_pci_set_unique(struct drm_device *dev,
++		       struct drm_master *master,
++		       struct drm_unique *u);
++int drm_irq_by_busid(struct drm_device *dev, void *data,
++		     struct drm_file *file_priv);
++
++/* drm_vm.c */
++int drm_vma_info(struct seq_file *m, void *data);
++void drm_vm_open_locked(struct drm_device *dev, struct vm_area_struct *vma);
++void drm_vm_close_locked(struct drm_device *dev, struct vm_area_struct *vma);
++
++/* drm_prime.c */
++int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
++				 struct drm_file *file_priv);
++int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
++				 struct drm_file *file_priv);
++
++void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv);
++void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv);
++void drm_prime_remove_buf_handle_locked(struct drm_prime_file_private *prime_fpriv,
++					struct dma_buf *dma_buf);
++
++/* drm_info.c */
++int drm_name_info(struct seq_file *m, void *data);
++int drm_vm_info(struct seq_file *m, void *data);
++int drm_bufs_info(struct seq_file *m, void *data);
++int drm_vblank_info(struct seq_file *m, void *data);
++int drm_clients_info(struct seq_file *m, void* data);
++int drm_gem_name_info(struct seq_file *m, void *data);
++
++/* drm_irq.c */
++int drm_control(struct drm_device *dev, void *data,
++		struct drm_file *file_priv);
++int drm_modeset_ctl(struct drm_device *dev, void *data,
++		    struct drm_file *file_priv);
++
++/* drm_auth.c */
++int drm_getmagic(struct drm_device *dev, void *data,
++		 struct drm_file *file_priv);
++int drm_authmagic(struct drm_device *dev, void *data,
++		  struct drm_file *file_priv);
++int drm_remove_magic(struct drm_master *master, drm_magic_t magic);
++
++/* drm_sysfs.c */
++extern struct class *drm_class;
++
++struct class *drm_sysfs_create(struct module *owner, char *name);
++void drm_sysfs_destroy(void);
++struct device *drm_sysfs_minor_alloc(struct drm_minor *minor);
++int drm_sysfs_connector_add(struct drm_connector *connector);
++void drm_sysfs_connector_remove(struct drm_connector *connector);
++
++/* drm_gem.c */
++int drm_gem_init(struct drm_device *dev);
++void drm_gem_destroy(struct drm_device *dev);
++int drm_gem_handle_create_tail(struct drm_file *file_priv,
++			       struct drm_gem_object *obj,
++			       u32 *handlep);
++int drm_gem_close_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *file_priv);
++int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *file_priv);
++int drm_gem_open_ioctl(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv);
++void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
++void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
++
++/* drm_drv.c */
++int drm_setmaster_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *file_priv);
++int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
++			 struct drm_file *file_priv);
++struct drm_master *drm_master_create(struct drm_minor *minor);
++
++/* drm_debugfs.c */
++#if defined(CONFIG_DEBUG_FS)
++int drm_debugfs_init(struct drm_minor *minor, int minor_id,
++		     struct dentry *root);
++int drm_debugfs_cleanup(struct drm_minor *minor);
++int drm_debugfs_connector_add(struct drm_connector *connector);
++void drm_debugfs_connector_remove(struct drm_connector *connector);
++#else
++static inline int drm_debugfs_init(struct drm_minor *minor, int minor_id,
++				   struct dentry *root)
++{
++	return 0;
++}
++
++static inline int drm_debugfs_cleanup(struct drm_minor *minor)
++{
++	return 0;
++}
++
++static inline int drm_debugfs_connector_add(struct drm_connector *connector)
++{
++	return 0;
++}
++static inline void drm_debugfs_connector_remove(struct drm_connector *connector)
++{
++}
++#endif
+diff -Naur a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
+--- a/drivers/gpu/drm/drm_ioctl.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_ioctl.c	2015-03-26 14:42:38.726435422 +0530
+@@ -1,11 +1,3 @@
+-/**
+- * \file drm_ioctl.c
+- * IOCTL processing for DRM
+- *
+- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+- * \author Gareth Hughes <gareth@valinux.com>
+- */
+-
+ /*
+  * Created: Fri Jan  8 09:01:26 1999 by faith@valinux.com
+  *
+@@ -13,6 +5,9 @@
+  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+  * All Rights Reserved.
+  *
++ * Author Rickard E. (Rik) Faith <faith@valinux.com>
++ * Author Gareth Hughes <gareth@valinux.com>
++ *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+@@ -35,6 +30,8 @@
+ 
+ #include <drm/drmP.h>
+ #include <drm/drm_core.h>
++#include "drm_legacy.h"
++#include "drm_internal.h"
+ 
+ #include <linux/pci.h>
+ #include <linux/export.h>
+@@ -42,6 +39,9 @@
+ #include <asm/mtrr.h>
+ #endif
+ 
++static int drm_version(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv);
++
+ /**
+  * Get the bus id.
+  *
+@@ -53,7 +53,7 @@
+  *
+  * Copies the bus id from drm_device::unique into user space.
+  */
+-int drm_getunique(struct drm_device *dev, void *data,
++static int drm_getunique(struct drm_device *dev, void *data,
+ 		  struct drm_file *file_priv)
+ {
+ 	struct drm_unique *u = data;
+@@ -72,13 +72,9 @@
+ drm_unset_busid(struct drm_device *dev,
+ 		struct drm_master *master)
+ {
+-	kfree(dev->devname);
+-	dev->devname = NULL;
+-
+ 	kfree(master->unique);
+ 	master->unique = NULL;
+ 	master->unique_len = 0;
+-	master->unique_size = 0;
+ }
+ 
+ /**
+@@ -93,9 +89,10 @@
+  * Copies the bus id from userspace into drm_device::unique, and verifies that
+  * it matches the device this DRM is attached to (EINVAL otherwise).  Deprecated
+  * in interface version 1.1 and will return EBUSY when setversion has requested
+- * version 1.1 or greater.
++ * version 1.1 or greater. Also note that KMS is all version 1.1 and later and
++ * UMS was only ever supported on pci devices.
+  */
+-int drm_setunique(struct drm_device *dev, void *data,
++static int drm_setunique(struct drm_device *dev, void *data,
+ 		  struct drm_file *file_priv)
+ {
+ 	struct drm_unique *u = data;
+@@ -108,10 +105,13 @@
+ 	if (!u->unique_len || u->unique_len > 1024)
+ 		return -EINVAL;
+ 
+-	if (!dev->driver->bus->set_unique)
++	if (drm_core_check_feature(dev, DRIVER_MODESET))
++		return 0;
++
++	if (WARN_ON(!dev->pdev))
+ 		return -EINVAL;
+ 
+-	ret = dev->driver->bus->set_unique(dev, master, u);
++	ret = drm_pci_set_unique(dev, master, u);
+ 	if (ret)
+ 		goto err;
+ 
+@@ -130,13 +130,25 @@
+ 	if (master->unique != NULL)
+ 		drm_unset_busid(dev, master);
+ 
+-	ret = dev->driver->bus->set_busid(dev, master);
+-	if (ret)
+-		goto err;
++	if (dev->driver->set_busid) {
++		ret = dev->driver->set_busid(dev, master);
++		if (ret) {
++			drm_unset_busid(dev, master);
++			return ret;
++		}
++	} else {
++		if (WARN(dev->unique == NULL,
++			 "No drm_driver.set_busid() implementation provided by "
++			 "%ps. Use drm_dev_set_unique() to set the unique "
++			 "name explicitly.", dev->driver))
++			return -EINVAL;
++
++		master->unique = kstrdup(dev->unique, GFP_KERNEL);
++		if (master->unique)
++			master->unique_len = strlen(dev->unique);
++	}
++
+ 	return 0;
+-err:
+-	drm_unset_busid(dev, master);
+-	return ret;
+ }
+ 
+ /**
+@@ -152,7 +164,7 @@
+  * Searches for the mapping with the specified offset and copies its information
+  * into userspace
+  */
+-int drm_getmap(struct drm_device *dev, void *data,
++static int drm_getmap(struct drm_device *dev, void *data,
+ 	       struct drm_file *file_priv)
+ {
+ 	struct drm_map *map = data;
+@@ -213,7 +225,7 @@
+  * Searches for the client with the specified index and copies its information
+  * into userspace
+  */
+-int drm_getclient(struct drm_device *dev, void *data,
++static int drm_getclient(struct drm_device *dev, void *data,
+ 		  struct drm_file *file_priv)
+ {
+ 	struct drm_client *client = data;
+@@ -253,7 +265,7 @@
+  *
+  * \return zero on success or a negative number on failure.
+  */
+-int drm_getstats(struct drm_device *dev, void *data,
++static int drm_getstats(struct drm_device *dev, void *data,
+ 		 struct drm_file *file_priv)
+ {
+ 	struct drm_stats *stats = data;
+@@ -267,7 +279,7 @@
+ /**
+  * Get device/driver capabilities
+  */
+-int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
++static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_get_cap *req = data;
+ 
+@@ -317,7 +329,7 @@
+ /**
+  * Set device/driver capabilities
+  */
+-int
++static int
+ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_set_client_cap *req = data;
+@@ -328,6 +340,11 @@
+ 			return -EINVAL;
+ 		file_priv->stereo_allowed = req->value;
+ 		break;
++	case DRM_CLIENT_CAP_UNIVERSAL_PLANES:
++		if (req->value > 1)
++			return -EINVAL;
++		file_priv->universal_planes = req->value;
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -346,7 +363,7 @@
+  *
+  * Sets the requested interface version
+  */
+-int drm_setversion(struct drm_device *dev, void *data, struct drm_file *file_priv)
++static int drm_setversion(struct drm_device *dev, void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_set_version *sv = data;
+ 	int if_version, retcode = 0;
+@@ -397,3 +414,358 @@
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_noop);
++
++/**
++ * Copy and IOCTL return string to user space
++ */
++static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value)
++{
++	int len;
++
++	/* don't overflow userbuf */
++	len = strlen(value);
++	if (len > *buf_len)
++		len = *buf_len;
++
++	/* let userspace know exact length of driver value (which could be
++	 * larger than the userspace-supplied buffer) */
++	*buf_len = strlen(value);
++
++	/* finally, try filling in the userbuf */
++	if (len && buf)
++		if (copy_to_user(buf, value, len))
++			return -EFAULT;
++	return 0;
++}
++
++/**
++ * Get version information
++ *
++ * \param inode device inode.
++ * \param filp file pointer.
++ * \param cmd command.
++ * \param arg user argument, pointing to a drm_version structure.
++ * \return zero on success or negative number on failure.
++ *
++ * Fills in the version information in \p arg.
++ */
++static int drm_version(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv)
++{
++	struct drm_version *version = data;
++	int err;
++
++	version->version_major = dev->driver->major;
++	version->version_minor = dev->driver->minor;
++	version->version_patchlevel = dev->driver->patchlevel;
++	err = drm_copy_field(version->name, &version->name_len,
++			dev->driver->name);
++	if (!err)
++		err = drm_copy_field(version->date, &version->date_len,
++				dev->driver->date);
++	if (!err)
++		err = drm_copy_field(version->desc, &version->desc_len,
++				dev->driver->desc);
++
++	return err;
++}
++
++/**
++ * drm_ioctl_permit - Check ioctl permissions against caller
++ *
++ * @flags: ioctl permission flags.
++ * @file_priv: Pointer to struct drm_file identifying the caller.
++ *
++ * Checks whether the caller is allowed to run an ioctl with the
++ * indicated permissions. If so, returns zero. Otherwise returns an
++ * error code suitable for ioctl return.
++ */
++static int drm_ioctl_permit(u32 flags, struct drm_file *file_priv)
++{
++	/* ROOT_ONLY is only for CAP_SYS_ADMIN */
++	if (unlikely((flags & DRM_ROOT_ONLY) && !capable(CAP_SYS_ADMIN)))
++		return -EACCES;
++
++	/* AUTH is only for authenticated or render client */
++	if (unlikely((flags & DRM_AUTH) && !drm_is_render_client(file_priv) &&
++		     !file_priv->authenticated))
++		return -EACCES;
++
++	/* MASTER is only for master or control clients */
++	if (unlikely((flags & DRM_MASTER) && !file_priv->is_master &&
++		     !drm_is_control_client(file_priv)))
++		return -EACCES;
++
++	/* Control clients must be explicitly allowed */
++	if (unlikely(!(flags & DRM_CONTROL_ALLOW) &&
++		     drm_is_control_client(file_priv)))
++		return -EACCES;
++
++	/* Render clients must be explicitly allowed */
++	if (unlikely(!(flags & DRM_RENDER_ALLOW) &&
++		     drm_is_render_client(file_priv)))
++		return -EACCES;
++
++	return 0;
++}
++
++#define DRM_IOCTL_DEF(ioctl, _func, _flags) \
++	[DRM_IOCTL_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl}
++
++/** Ioctl table */
++static const struct drm_ioctl_desc drm_ioctls[] = {
++	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),
++	DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, 0),
++	DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_legacy_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_legacy_rmmap_ioctl, DRM_AUTH),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_SET_SAREA_CTX, drm_legacy_setsareactx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_SAREA_CTX, drm_legacy_getsareactx, DRM_AUTH),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_SET_MASTER, drm_setmaster_ioctl, DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_DROP_MASTER, drm_dropmaster_ioctl, DRM_ROOT_ONLY),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_legacy_addctx, DRM_AUTH|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_RM_CTX, drm_legacy_rmctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_MOD_CTX, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_GET_CTX, drm_legacy_getctx, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_IOCTL_SWITCH_CTX, drm_legacy_switchctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_NEW_CTX, drm_legacy_newctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_RES_CTX, drm_legacy_resctx, DRM_AUTH),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_ADD_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_RM_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_LOCK, drm_legacy_lock, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_IOCTL_UNLOCK, drm_legacy_unlock, DRM_AUTH),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_FINISH, drm_noop, DRM_AUTH),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_ADD_BUFS, drm_legacy_addbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_MARK_BUFS, drm_legacy_markbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_INFO_BUFS, drm_legacy_infobufs, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_IOCTL_MAP_BUFS, drm_legacy_mapbufs, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_IOCTL_FREE_BUFS, drm_legacy_freebufs, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_IOCTL_DMA, drm_legacy_dma_ioctl, DRM_AUTH),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_CONTROL, drm_control, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++
++#if __OS_HAS_AGP
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_ACQUIRE, drm_agp_acquire_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_RELEASE, drm_agp_release_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_ENABLE, drm_agp_enable_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_INFO, drm_agp_info_ioctl, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_ALLOC, drm_agp_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_FREE, drm_agp_free_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_BIND, drm_agp_bind_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_AGP_UNBIND, drm_agp_unbind_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++#endif
++
++	DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_legacy_sg_alloc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++	DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_legacy_sg_free, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_HANDLE_TO_FD, drm_prime_handle_to_fd_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_FD_TO_HANDLE, drm_prime_fd_to_handle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANERESOURCES, drm_mode_getplane_res, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANE, drm_mode_getplane, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPLANE, drm_mode_setplane, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB2, drm_mode_addfb2, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
++};
++
++#define DRM_CORE_IOCTL_COUNT	ARRAY_SIZE( drm_ioctls )
++
++/**
++ * Called whenever a process performs an ioctl on /dev/drm.
++ *
++ * \param inode device inode.
++ * \param file_priv DRM file private.
++ * \param cmd command.
++ * \param arg user argument.
++ * \return zero on success or negative number on failure.
++ *
++ * Looks up the ioctl function in the ::ioctls table, checking for root
++ * previleges if so required, and dispatches to the respective function.
++ */
++long drm_ioctl(struct file *filp,
++	      unsigned int cmd, unsigned long arg)
++{
++	struct drm_file *file_priv = filp->private_data;
++	struct drm_device *dev;
++	const struct drm_ioctl_desc *ioctl = NULL;
++	drm_ioctl_t *func;
++	unsigned int nr = DRM_IOCTL_NR(cmd);
++	int retcode = -EINVAL;
++	char stack_kdata[128];
++	char *kdata = NULL;
++	unsigned int usize, asize;
++
++	dev = file_priv->minor->dev;
++
++	if (drm_device_is_unplugged(dev))
++		return -ENODEV;
++
++	if ((nr >= DRM_CORE_IOCTL_COUNT) &&
++	    ((nr < DRM_COMMAND_BASE) || (nr >= DRM_COMMAND_END)))
++		goto err_i1;
++	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
++	    (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
++		u32 drv_size;
++		ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
++		drv_size = _IOC_SIZE(ioctl->cmd_drv);
++		usize = asize = _IOC_SIZE(cmd);
++		if (drv_size > asize)
++			asize = drv_size;
++		cmd = ioctl->cmd_drv;
++	}
++	else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
++		u32 drv_size;
++
++		ioctl = &drm_ioctls[nr];
++
++		drv_size = _IOC_SIZE(ioctl->cmd);
++		usize = asize = _IOC_SIZE(cmd);
++		if (drv_size > asize)
++			asize = drv_size;
++
++		cmd = ioctl->cmd;
++	} else
++		goto err_i1;
++
++	DRM_DEBUG("pid=%d, dev=0x%lx, auth=%d, %s\n",
++		  task_pid_nr(current),
++		  (long)old_encode_dev(file_priv->minor->kdev->devt),
++		  file_priv->authenticated, ioctl->name);
++
++	/* Do not trust userspace, use our own definition */
++	func = ioctl->func;
++
++	if (unlikely(!func)) {
++		DRM_DEBUG("no function\n");
++		retcode = -EINVAL;
++		goto err_i1;
++	}
++
++	retcode = drm_ioctl_permit(ioctl->flags, file_priv);
++	if (unlikely(retcode))
++		goto err_i1;
++
++	if (cmd & (IOC_IN | IOC_OUT)) {
++		if (asize <= sizeof(stack_kdata)) {
++			kdata = stack_kdata;
++		} else {
++			kdata = kmalloc(asize, GFP_KERNEL);
++			if (!kdata) {
++				retcode = -ENOMEM;
++				goto err_i1;
++			}
++		}
++		if (asize > usize)
++			memset(kdata + usize, 0, asize - usize);
++	}
++
++	if (cmd & IOC_IN) {
++		if (copy_from_user(kdata, (void __user *)arg,
++				   usize) != 0) {
++			retcode = -EFAULT;
++			goto err_i1;
++		}
++	} else if (cmd & IOC_OUT) {
++		memset(kdata, 0, usize);
++	}
++
++	if (ioctl->flags & DRM_UNLOCKED)
++		retcode = func(dev, kdata, file_priv);
++	else {
++		mutex_lock(&drm_global_mutex);
++		retcode = func(dev, kdata, file_priv);
++		mutex_unlock(&drm_global_mutex);
++	}
++
++	if (cmd & IOC_OUT) {
++		if (copy_to_user((void __user *)arg, kdata,
++				 usize) != 0)
++			retcode = -EFAULT;
++	}
++
++      err_i1:
++	if (!ioctl)
++		DRM_DEBUG("invalid ioctl: pid=%d, dev=0x%lx, auth=%d, cmd=0x%02x, nr=0x%02x\n",
++			  task_pid_nr(current),
++			  (long)old_encode_dev(file_priv->minor->kdev->devt),
++			  file_priv->authenticated, cmd, nr);
++
++	if (kdata != stack_kdata)
++		kfree(kdata);
++	if (retcode)
++		DRM_DEBUG("ret = %d\n", retcode);
++	return retcode;
++}
++EXPORT_SYMBOL(drm_ioctl);
++
++/**
++ * drm_ioctl_flags - Check for core ioctl and return ioctl permission flags
++ *
++ * @nr: Ioctl number.
++ * @flags: Where to return the ioctl permission flags
++ */
++bool drm_ioctl_flags(unsigned int nr, unsigned int *flags)
++{
++	if ((nr >= DRM_COMMAND_END && nr < DRM_CORE_IOCTL_COUNT) ||
++	    (nr < DRM_COMMAND_BASE)) {
++		*flags = drm_ioctls[nr].flags;
++		return true;
++	}
++
++	return false;
++}
++EXPORT_SYMBOL(drm_ioctl_flags);
+diff -Naur a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
+--- a/drivers/gpu/drm/drm_irq.c	2015-03-26 14:43:30.426436436 +0530
++++ b/drivers/gpu/drm/drm_irq.c	2015-03-26 14:42:38.730435422 +0530
+@@ -1,6 +1,5 @@
+-/**
+- * \file drm_irq.c
+- * IRQ support
++/*
++ * drm_irq.c IRQ and vblank support
+  *
+  * \author Rickard E. (Rik) Faith <faith@valinux.com>
+  * \author Gareth Hughes <gareth@valinux.com>
+@@ -35,6 +34,7 @@
+ 
+ #include <drm/drmP.h>
+ #include "drm_trace.h"
++#include "drm_internal.h"
+ 
+ #include <linux/interrupt.h>	/* For task queue support */
+ #include <linux/slab.h>
+@@ -56,39 +56,91 @@
+  */
+ #define DRM_REDUNDANT_VBLIRQ_THRESH_NS 1000000
+ 
++static bool
++drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
++			  struct timeval *tvblank, unsigned flags);
++
++static unsigned int drm_timestamp_precision = 20;  /* Default to 20 usecs. */
++
++/*
++ * Default to use monotonic timestamps for wait-for-vblank and page-flip
++ * complete events.
++ */
++unsigned int drm_timestamp_monotonic = 1;
++
++static int drm_vblank_offdelay = 5000;    /* Default to 5000 msecs. */
++
++module_param_named(vblankoffdelay, drm_vblank_offdelay, int, 0600);
++module_param_named(timestamp_precision_usec, drm_timestamp_precision, int, 0600);
++module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
++
+ /**
+- * Get interrupt from bus id.
++ * drm_update_vblank_count - update the master vblank counter
++ * @dev: DRM device
++ * @crtc: counter to update
+  *
+- * \param inode device inode.
+- * \param file_priv DRM file private.
+- * \param cmd command.
+- * \param arg user argument, pointing to a drm_irq_busid structure.
+- * \return zero on success or a negative number on failure.
++ * Call back into the driver to update the appropriate vblank counter
++ * (specified by @crtc).  Deal with wraparound, if it occurred, and
++ * update the last read value so we can deal with wraparound on the next
++ * call if necessary.
++ *
++ * Only necessary when going from off->on, to account for frames we
++ * didn't get an interrupt for.
+  *
+- * Finds the PCI device with the specified bus id and gets its IRQ number.
+- * This IOCTL is deprecated, and will now return EINVAL for any busid not equal
+- * to that of the device that this DRM instance attached to.
++ * Note: caller must hold dev->vbl_lock since this reads & writes
++ * device vblank fields.
+  */
+-int drm_irq_by_busid(struct drm_device *dev, void *data,
+-		     struct drm_file *file_priv)
++static void drm_update_vblank_count(struct drm_device *dev, int crtc)
+ {
+-	struct drm_irq_busid *p = data;
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++	u32 cur_vblank, diff, tslot;
++	bool rc;
++	struct timeval t_vblank;
+ 
+-	if (!dev->driver->bus->irq_by_busid)
+-		return -EINVAL;
++	/*
++	 * Interrupts were disabled prior to this call, so deal with counter
++	 * wrap if needed.
++	 * NOTE!  It's possible we lost a full dev->max_vblank_count events
++	 * here if the register is small or we had vblank interrupts off for
++	 * a long time.
++	 *
++	 * We repeat the hardware vblank counter & timestamp query until
++	 * we get consistent results. This to prevent races between gpu
++	 * updating its hardware counter while we are retrieving the
++	 * corresponding vblank timestamp.
++	 */
++	do {
++		cur_vblank = dev->driver->get_vblank_counter(dev, crtc);
++		rc = drm_get_last_vbltimestamp(dev, crtc, &t_vblank, 0);
++	} while (cur_vblank != dev->driver->get_vblank_counter(dev, crtc));
+ 
+-	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
+-		return -EINVAL;
++	/* Deal with counter wrap */
++	diff = cur_vblank - vblank->last;
++	if (cur_vblank < vblank->last) {
++		diff += dev->max_vblank_count;
+ 
+-	return dev->driver->bus->irq_by_busid(dev, p);
+-}
++		DRM_DEBUG("last_vblank[%d]=0x%x, cur_vblank=0x%x => diff=0x%x\n",
++			  crtc, vblank->last, cur_vblank, diff);
++	}
+ 
+-/*
+- * Clear vblank timestamp buffer for a crtc.
+- */
+-static void clear_vblank_timestamps(struct drm_device *dev, int crtc)
+-{
+-	memset(dev->vblank[crtc].time, 0, sizeof(dev->vblank[crtc].time));
++	DRM_DEBUG("updating vblank count on crtc %d, missed %d\n",
++		  crtc, diff);
++
++	if (diff == 0)
++		return;
++
++	/* Reinitialize corresponding vblank timestamp if high-precision query
++	 * available. Skip this step if query unsupported or failed. Will
++	 * reinitialize delayed at next vblank interrupt in that case.
++	 */
++	if (rc) {
++		tslot = atomic_read(&vblank->count) + diff;
++		vblanktimestamp(dev, crtc, tslot) = t_vblank;
++	}
++
++	smp_mb__before_atomic_inc();
++	atomic_add(diff, &vblank->count);
++	smp_mb__after_atomic_inc();
+ }
+ 
+ /*
+@@ -99,10 +151,11 @@
+  */
+ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+ 	unsigned long irqflags;
+ 	u32 vblcount;
+ 	s64 diff_ns;
+-	int vblrc;
++	bool vblrc;
+ 	struct timeval tvblank;
+ 	int count = DRM_TIMESTAMP_MAXRETRIES;
+ 
+@@ -112,8 +165,28 @@
+ 	 */
+ 	spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
+ 
++	/*
++	 * If the vblank interrupt was already disabled update the count
++	 * and timestamp to maintain the appearance that the counter
++	 * has been ticking all along until this time. This makes the
++	 * count account for the entire time between drm_vblank_on() and
++	 * drm_vblank_off().
++	 *
++	 * But only do this if precise vblank timestamps are available.
++	 * Otherwise we might read a totally bogus timestamp since drivers
++	 * lacking precise timestamp support rely upon sampling the system clock
++	 * at vblank interrupt time. Which obviously won't work out well if the
++	 * vblank interrupt is disabled.
++	 */
++	if (!vblank->enabled &&
++	    drm_get_last_vbltimestamp(dev, crtc, &tvblank, 0)) {
++		drm_update_vblank_count(dev, crtc);
++		spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
++		return;
++	}
++
+ 	dev->driver->disable_vblank(dev, crtc);
+-	dev->vblank[crtc].enabled = false;
++	vblank->enabled = false;
+ 
+ 	/* No further vblank irq's will be processed after
+ 	 * this point. Get current hardware vblank count and
+@@ -128,9 +201,9 @@
+ 	 * delayed gpu counter increment.
+ 	 */
+ 	do {
+-		dev->vblank[crtc].last = dev->driver->get_vblank_counter(dev, crtc);
++		vblank->last = dev->driver->get_vblank_counter(dev, crtc);
+ 		vblrc = drm_get_last_vbltimestamp(dev, crtc, &tvblank, 0);
+-	} while (dev->vblank[crtc].last != dev->driver->get_vblank_counter(dev, crtc) && (--count) && vblrc);
++	} while (vblank->last != dev->driver->get_vblank_counter(dev, crtc) && (--count) && vblrc);
+ 
+ 	if (!count)
+ 		vblrc = 0;
+@@ -138,7 +211,7 @@
+ 	/* Compute time difference to stored timestamp of last vblank
+ 	 * as updated by last invocation of drm_handle_vblank() in vblank irq.
+ 	 */
+-	vblcount = atomic_read(&dev->vblank[crtc].count);
++	vblcount = atomic_read(&vblank->count);
+ 	diff_ns = timeval_to_ns(&tvblank) -
+ 		  timeval_to_ns(&vblanktimestamp(dev, crtc, vblcount));
+ 
+@@ -154,46 +227,63 @@
+ 	 * available. In that case we can't account for this and just
+ 	 * hope for the best.
+ 	 */
+-	if ((vblrc > 0) && (abs64(diff_ns) > 1000000)) {
+-		atomic_inc(&dev->vblank[crtc].count);
++	if (vblrc && (abs64(diff_ns) > 1000000)) {
++		/* Store new timestamp in ringbuffer. */
++		vblanktimestamp(dev, crtc, vblcount + 1) = tvblank;
++
++		/* Increment cooked vblank count. This also atomically commits
++		 * the timestamp computed above.
++		 */
++		smp_mb__before_atomic_inc();
++		atomic_inc(&vblank->count);
+ 		smp_mb__after_atomic_inc();
+ 	}
+ 
+-	/* Invalidate all timestamps while vblank irq's are off. */
+-	clear_vblank_timestamps(dev, crtc);
+-
+ 	spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
+ }
+ 
+ static void vblank_disable_fn(unsigned long arg)
+ {
+-	struct drm_device *dev = (struct drm_device *)arg;
++	struct drm_vblank_crtc *vblank = (void *)arg;
++	struct drm_device *dev = vblank->dev;
+ 	unsigned long irqflags;
+-	int i;
++	int crtc = vblank->crtc;
+ 
+ 	if (!dev->vblank_disable_allowed)
+ 		return;
+ 
+-	for (i = 0; i < dev->num_crtcs; i++) {
+-		spin_lock_irqsave(&dev->vbl_lock, irqflags);
+-		if (atomic_read(&dev->vblank[i].refcount) == 0 &&
+-		    dev->vblank[i].enabled) {
+-			DRM_DEBUG("disabling vblank on crtc %d\n", i);
+-			vblank_disable_and_save(dev, i);
+-		}
+-		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
++	spin_lock_irqsave(&dev->vbl_lock, irqflags);
++	if (atomic_read(&vblank->refcount) == 0 && vblank->enabled) {
++		DRM_DEBUG("disabling vblank on crtc %d\n", crtc);
++		vblank_disable_and_save(dev, crtc);
+ 	}
++	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+ }
+ 
++/**
++ * drm_vblank_cleanup - cleanup vblank support
++ * @dev: DRM device
++ *
++ * This function cleans up any resources allocated in drm_vblank_init.
++ */
+ void drm_vblank_cleanup(struct drm_device *dev)
+ {
++	int crtc;
++	unsigned long irqflags;
++
+ 	/* Bail if the driver didn't call drm_vblank_init() */
+ 	if (dev->num_crtcs == 0)
+ 		return;
+ 
+-	del_timer_sync(&dev->vblank_disable_timer);
++	for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
++		struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+ 
+-	vblank_disable_fn((unsigned long)dev);
++		del_timer_sync(&vblank->disable_timer);
++
++		spin_lock_irqsave(&dev->vbl_lock, irqflags);
++		vblank_disable_and_save(dev, crtc);
++		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
++	}
+ 
+ 	kfree(dev->vblank);
+ 
+@@ -201,12 +291,20 @@
+ }
+ EXPORT_SYMBOL(drm_vblank_cleanup);
+ 
++/**
++ * drm_vblank_init - initialize vblank support
++ * @dev: drm_device
++ * @num_crtcs: number of crtcs supported by @dev
++ *
++ * This function initializes vblank support for @num_crtcs display pipelines.
++ *
++ * Returns:
++ * Zero on success or a negative error code on failure.
++ */
+ int drm_vblank_init(struct drm_device *dev, int num_crtcs)
+ {
+ 	int i, ret = -ENOMEM;
+ 
+-	setup_timer(&dev->vblank_disable_timer, vblank_disable_fn,
+-		    (unsigned long)dev);
+ 	spin_lock_init(&dev->vbl_lock);
+ 	spin_lock_init(&dev->vblank_time_lock);
+ 
+@@ -216,8 +314,15 @@
+ 	if (!dev->vblank)
+ 		goto err;
+ 
+-	for (i = 0; i < num_crtcs; i++)
+-		init_waitqueue_head(&dev->vblank[i].queue);
++	for (i = 0; i < num_crtcs; i++) {
++		struct drm_vblank_crtc *vblank = &dev->vblank[i];
++
++		vblank->dev = dev;
++		vblank->crtc = i;
++		init_waitqueue_head(&vblank->queue);
++		setup_timer(&vblank->disable_timer, vblank_disable_fn,
++			    (unsigned long)vblank);
++	}
+ 
+ 	DRM_INFO("Supports vblank timestamp caching Rev 2 (21.10.2013).\n");
+ 
+@@ -232,7 +337,7 @@
+ 	return 0;
+ 
+ err:
+-	drm_vblank_cleanup(dev);
++	dev->num_crtcs = 0;
+ 	return ret;
+ }
+ EXPORT_SYMBOL(drm_vblank_init);
+@@ -261,42 +366,42 @@
+ }
+ 
+ /**
+- * Install IRQ handler.
+- *
+- * \param dev DRM device.
++ * drm_irq_install - install IRQ handler
++ * @dev: DRM device
++ * @irq: IRQ number to install the handler for
+  *
+  * Initializes the IRQ related data. Installs the handler, calling the driver
+- * \c irq_preinstall() and \c irq_postinstall() functions
+- * before and after the installation.
++ * irq_preinstall() and irq_postinstall() functions before and after the
++ * installation.
++ *
++ * This is the simplified helper interface provided for drivers with no special
++ * needs. Drivers which need to install interrupt handlers for multiple
++ * interrupts must instead set drm_device->irq_enabled to signal the DRM core
++ * that vblank interrupts are available.
++ *
++ * Returns:
++ * Zero on success or a negative error code on failure.
+  */
+-int drm_irq_install(struct drm_device *dev)
++int drm_irq_install(struct drm_device *dev, int irq)
+ {
+ 	int ret;
+ 	unsigned long sh_flags = 0;
+-	char *irqname;
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
+ 		return -EINVAL;
+ 
+-	if (drm_dev_to_irq(dev) == 0)
++	if (irq == 0)
+ 		return -EINVAL;
+ 
+-	mutex_lock(&dev->struct_mutex);
+-
+ 	/* Driver must have been initialized */
+-	if (!dev->dev_private) {
+-		mutex_unlock(&dev->struct_mutex);
++	if (!dev->dev_private)
+ 		return -EINVAL;
+-	}
+ 
+-	if (dev->irq_enabled) {
+-		mutex_unlock(&dev->struct_mutex);
++	if (dev->irq_enabled)
+ 		return -EBUSY;
+-	}
+ 	dev->irq_enabled = true;
+-	mutex_unlock(&dev->struct_mutex);
+ 
+-	DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
++	DRM_DEBUG("irq=%d\n", irq);
+ 
+ 	/* Before installing handler */
+ 	if (dev->driver->irq_preinstall)
+@@ -306,18 +411,11 @@
+ 	if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
+ 		sh_flags = IRQF_SHARED;
+ 
+-	if (dev->devname)
+-		irqname = dev->devname;
+-	else
+-		irqname = dev->driver->name;
+-
+-	ret = request_irq(drm_dev_to_irq(dev), dev->driver->irq_handler,
+-			  sh_flags, irqname, dev);
++	ret = request_irq(irq, dev->driver->irq_handler,
++			  sh_flags, dev->driver->name, dev);
+ 
+ 	if (ret < 0) {
+-		mutex_lock(&dev->struct_mutex);
+ 		dev->irq_enabled = false;
+-		mutex_unlock(&dev->struct_mutex);
+ 		return ret;
+ 	}
+ 
+@@ -329,12 +427,12 @@
+ 		ret = dev->driver->irq_postinstall(dev);
+ 
+ 	if (ret < 0) {
+-		mutex_lock(&dev->struct_mutex);
+ 		dev->irq_enabled = false;
+-		mutex_unlock(&dev->struct_mutex);
+ 		if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 			vga_client_register(dev->pdev, NULL, NULL, NULL);
+-		free_irq(drm_dev_to_irq(dev), dev);
++		free_irq(irq, dev);
++	} else {
++		dev->irq = irq;
+ 	}
+ 
+ 	return ret;
+@@ -342,11 +440,20 @@
+ EXPORT_SYMBOL(drm_irq_install);
+ 
+ /**
+- * Uninstall the IRQ handler.
++ * drm_irq_uninstall - uninstall the IRQ handler
++ * @dev: DRM device
+  *
+- * \param dev DRM device.
++ * Calls the driver's irq_uninstall() function and unregisters the IRQ handler.
++ * This should only be called by drivers which used drm_irq_install() to set up
++ * their interrupt handler. Other drivers must only reset
++ * drm_device->irq_enabled to false.
++ *
++ * Note that for kernel modesetting drivers it is a bug if this function fails.
++ * The sanity checks are only to catch buggy user modesetting drivers which call
++ * the same function through an ioctl.
+  *
+- * Calls the driver's \c irq_uninstall() function, and stops the irq.
++ * Returns:
++ * Zero on success or a negative error code on failure.
+  */
+ int drm_irq_uninstall(struct drm_device *dev)
+ {
+@@ -357,10 +464,8 @@
+ 	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
+ 		return -EINVAL;
+ 
+-	mutex_lock(&dev->struct_mutex);
+ 	irq_enabled = dev->irq_enabled;
+ 	dev->irq_enabled = false;
+-	mutex_unlock(&dev->struct_mutex);
+ 
+ 	/*
+ 	 * Wake up any waiters so they don't hang.
+@@ -368,9 +473,11 @@
+ 	if (dev->num_crtcs) {
+ 		spin_lock_irqsave(&dev->vbl_lock, irqflags);
+ 		for (i = 0; i < dev->num_crtcs; i++) {
+-			wake_up(&dev->vblank[i].queue);
+-			dev->vblank[i].enabled = false;
+-			dev->vblank[i].last =
++			struct drm_vblank_crtc *vblank = &dev->vblank[i];
++
++			wake_up(&vblank->queue);
++			vblank->enabled = false;
++			vblank->last =
+ 				dev->driver->get_vblank_counter(dev, i);
+ 		}
+ 		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+@@ -379,7 +486,7 @@
+ 	if (!irq_enabled)
+ 		return -EINVAL;
+ 
+-	DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
++	DRM_DEBUG("irq=%d\n", dev->irq);
+ 
+ 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ 		vga_client_register(dev->pdev, NULL, NULL, NULL);
+@@ -387,13 +494,13 @@
+ 	if (dev->driver->irq_uninstall)
+ 		dev->driver->irq_uninstall(dev);
+ 
+-	free_irq(drm_dev_to_irq(dev), dev);
++	free_irq(dev->irq, dev);
+ 
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_irq_uninstall);
+ 
+-/**
++/*
+  * IRQ control ioctl.
+  *
+  * \param inode device inode.
+@@ -408,43 +515,52 @@
+ 		struct drm_file *file_priv)
+ {
+ 	struct drm_control *ctl = data;
++	int ret = 0, irq;
+ 
+ 	/* if we haven't irq we fallback for compatibility reasons -
+ 	 * this used to be a separate function in drm_dma.h
+ 	 */
+ 
++	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
++		return 0;
++	if (drm_core_check_feature(dev, DRIVER_MODESET))
++		return 0;
++	/* UMS was only ever support on pci devices. */
++	if (WARN_ON(!dev->pdev))
++		return -EINVAL;
+ 
+ 	switch (ctl->func) {
+ 	case DRM_INST_HANDLER:
+-		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
+-			return 0;
+-		if (drm_core_check_feature(dev, DRIVER_MODESET))
+-			return 0;
++		irq = dev->pdev->irq;
++
+ 		if (dev->if_version < DRM_IF_VERSION(1, 2) &&
+-		    ctl->irq != drm_dev_to_irq(dev))
++		    ctl->irq != irq)
+ 			return -EINVAL;
+-		return drm_irq_install(dev);
++		mutex_lock(&dev->struct_mutex);
++		ret = drm_irq_install(dev, irq);
++		mutex_unlock(&dev->struct_mutex);
++
++		return ret;
+ 	case DRM_UNINST_HANDLER:
+-		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
+-			return 0;
+-		if (drm_core_check_feature(dev, DRIVER_MODESET))
+-			return 0;
+-		return drm_irq_uninstall(dev);
++		mutex_lock(&dev->struct_mutex);
++		ret = drm_irq_uninstall(dev);
++		mutex_unlock(&dev->struct_mutex);
++
++		return ret;
+ 	default:
+ 		return -EINVAL;
+ 	}
+ }
+ 
+ /**
+- * drm_calc_timestamping_constants - Calculate vblank timestamp constants
+- *
+- * @crtc drm_crtc whose timestamp constants should be updated.
+- * @mode display mode containing the scanout timings
++ * drm_calc_timestamping_constants - calculate vblank timestamp constants
++ * @crtc: drm_crtc whose timestamp constants should be updated.
++ * @mode: display mode containing the scanout timings
+  *
+  * Calculate and store various constants which are later
+  * needed by vblank and swap-completion timestamping, e.g,
+  * by drm_calc_vbltimestamp_from_scanoutpos(). They are
+- * derived from crtc's true scanout timing, so they take
++ * derived from CRTC's true scanout timing, so they take
+  * things like panel scaling or other adjustments into account.
+  */
+ void drm_calc_timestamping_constants(struct drm_crtc *crtc,
+@@ -489,11 +605,22 @@
+ EXPORT_SYMBOL(drm_calc_timestamping_constants);
+ 
+ /**
+- * drm_calc_vbltimestamp_from_scanoutpos - helper routine for kms
+- * drivers. Implements calculation of exact vblank timestamps from
+- * given drm_display_mode timings and current video scanout position
+- * of a crtc. This can be called from within get_vblank_timestamp()
+- * implementation of a kms driver to implement the actual timestamping.
++ * drm_calc_vbltimestamp_from_scanoutpos - precise vblank timestamp helper
++ * @dev: DRM device
++ * @crtc: Which CRTC's vblank timestamp to retrieve
++ * @max_error: Desired maximum allowable error in timestamps (nanosecs)
++ *             On return contains true maximum error of timestamp
++ * @vblank_time: Pointer to struct timeval which should receive the timestamp
++ * @flags: Flags to pass to driver:
++ *         0 = Default,
++ *         DRM_CALLED_FROM_VBLIRQ = If function is called from vbl IRQ handler
++ * @refcrtc: CRTC which defines scanout timing
++ * @mode: mode which defines the scanout timings
++ *
++ * Implements calculation of exact vblank timestamps from given drm_display_mode
++ * timings and current video scanout position of a CRTC. This can be called from
++ * within get_vblank_timestamp() implementation of a kms driver to implement the
++ * actual timestamping.
+  *
+  * Should return timestamps conforming to the OML_sync_control OpenML
+  * extension specification. The timestamp corresponds to the end of
+@@ -508,21 +635,11 @@
+  * returns as no operation if a doublescan or interlaced video mode is
+  * active. Higher level code is expected to handle this.
+  *
+- * @dev: DRM device.
+- * @crtc: Which crtc's vblank timestamp to retrieve.
+- * @max_error: Desired maximum allowable error in timestamps (nanosecs).
+- *             On return contains true maximum error of timestamp.
+- * @vblank_time: Pointer to struct timeval which should receive the timestamp.
+- * @flags: Flags to pass to driver:
+- *         0 = Default.
+- *         DRM_CALLED_FROM_VBLIRQ = If function is called from vbl irq handler.
+- * @refcrtc: drm_crtc* of crtc which defines scanout timing.
+- * @mode: mode which defines the scanout timings
+- *
+- * Returns negative value on error, failure or if not supported in current
++ * Returns:
++ * Negative value on error, failure or if not supported in current
+  * video mode:
+  *
+- * -EINVAL   - Invalid crtc.
++ * -EINVAL   - Invalid CRTC.
+  * -EAGAIN   - Temporary unavailable, e.g., called before initial modeset.
+  * -ENOTSUPP - Function not supported in current display mode.
+  * -EIO      - Failed, e.g., due to failed scanout position query.
+@@ -540,8 +657,8 @@
+ 					  const struct drm_crtc *refcrtc,
+ 					  const struct drm_display_mode *mode)
+ {
+-	ktime_t stime, etime, mono_time_offset;
+ 	struct timeval tv_etime;
++	ktime_t stime, etime;
+ 	int vbl_status;
+ 	int vpos, hpos, i;
+ 	int framedur_ns, linedur_ns, pixeldur_ns, delta_ns, duration_ns;
+@@ -586,13 +703,6 @@
+ 		vbl_status = dev->driver->get_scanout_position(dev, crtc, flags, &vpos,
+ 							       &hpos, &stime, &etime);
+ 
+-		/*
+-		 * Get correction for CLOCK_MONOTONIC -> CLOCK_REALTIME if
+-		 * CLOCK_REALTIME is requested.
+-		 */
+-		if (!drm_timestamp_monotonic)
+-			mono_time_offset = ktime_get_monotonic_offset();
+-
+ 		/* Return as no-op if scanout query unsupported or failed. */
+ 		if (!(vbl_status & DRM_SCANOUTPOS_VALID)) {
+ 			DRM_DEBUG("crtc %d : scanoutpos query failed [%d].\n",
+@@ -622,7 +732,7 @@
+ 	 * within vblank area, counting down the number of lines until
+ 	 * start of scanout.
+ 	 */
+-	invbl = vbl_status & DRM_SCANOUTPOS_INVBL;
++	invbl = vbl_status & DRM_SCANOUTPOS_IN_VBLANK;
+ 
+ 	/* Convert scanout position into elapsed time at raw_time query
+ 	 * since start of scanout at first display scanline. delta_ns
+@@ -631,7 +741,7 @@
+ 	delta_ns = vpos * linedur_ns + hpos * pixeldur_ns;
+ 
+ 	if (!drm_timestamp_monotonic)
+-		etime = ktime_sub(etime, mono_time_offset);
++		etime = ktime_mono_to_real(etime);
+ 
+ 	/* save this only for debugging purposes */
+ 	tv_etime = ktime_to_timeval(etime);
+@@ -652,7 +762,7 @@
+ 
+ 	vbl_status = DRM_VBLANKTIME_SCANOUTPOS_METHOD;
+ 	if (invbl)
+-		vbl_status |= DRM_VBLANKTIME_INVBL;
++		vbl_status |= DRM_VBLANKTIME_IN_VBLANK;
+ 
+ 	return vbl_status;
+ }
+@@ -662,35 +772,33 @@
+ {
+ 	ktime_t now;
+ 
+-	now = ktime_get();
+-	if (!drm_timestamp_monotonic)
+-		now = ktime_sub(now, ktime_get_monotonic_offset());
+-
++	now = drm_timestamp_monotonic ? ktime_get() : ktime_get_real();
+ 	return ktime_to_timeval(now);
+ }
+ 
+ /**
+  * drm_get_last_vbltimestamp - retrieve raw timestamp for the most recent
+- * vblank interval.
+- *
++ * 			       vblank interval
+  * @dev: DRM device
+- * @crtc: which crtc's vblank timestamp to retrieve
++ * @crtc: which CRTC's vblank timestamp to retrieve
+  * @tvblank: Pointer to target struct timeval which should receive the timestamp
+  * @flags: Flags to pass to driver:
+- *         0 = Default.
+- *         DRM_CALLED_FROM_VBLIRQ = If function is called from vbl irq handler.
++ *         0 = Default,
++ *         DRM_CALLED_FROM_VBLIRQ = If function is called from vbl IRQ handler
+  *
+  * Fetches the system timestamp corresponding to the time of the most recent
+- * vblank interval on specified crtc. May call into kms-driver to
++ * vblank interval on specified CRTC. May call into kms-driver to
+  * compute the timestamp with a high-precision GPU specific method.
+  *
+  * Returns zero if timestamp originates from uncorrected do_gettimeofday()
+  * call, i.e., it isn't very precisely locked to the true vblank.
+  *
+- * Returns non-zero if timestamp is considered to be very precise.
++ * Returns:
++ * True if timestamp is considered to be very precise, false otherwise.
+  */
+-u32 drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
+-			      struct timeval *tvblank, unsigned flags)
++static bool
++drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
++			  struct timeval *tvblank, unsigned flags)
+ {
+ 	int ret;
+ 
+@@ -702,7 +810,7 @@
+ 		ret = dev->driver->get_vblank_timestamp(dev, crtc, &max_error,
+ 							tvblank, flags);
+ 		if (ret > 0)
+-			return (u32) ret;
++			return true;
+ 	}
+ 
+ 	/* GPU high precision timestamp query unsupported or failed.
+@@ -710,9 +818,8 @@
+ 	 */
+ 	*tvblank = get_drm_timestamp();
+ 
+-	return 0;
++	return false;
+ }
+-EXPORT_SYMBOL(drm_get_last_vbltimestamp);
+ 
+ /**
+  * drm_vblank_count - retrieve "cooked" vblank counter value
+@@ -722,10 +829,17 @@
+  * Fetches the "cooked" vblank count value that represents the number of
+  * vblank events since the system was booted, including lost events due to
+  * modesetting activity.
++ *
++ * Returns:
++ * The software vblank counter.
+  */
+ u32 drm_vblank_count(struct drm_device *dev, int crtc)
+ {
+-	return atomic_read(&dev->vblank[crtc].count);
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return 0;
++	return atomic_read(&vblank->count);
+ }
+ EXPORT_SYMBOL(drm_vblank_count);
+ 
+@@ -740,24 +854,27 @@
+  * Fetches the "cooked" vblank count value that represents the number of
+  * vblank events since the system was booted, including lost events due to
+  * modesetting activity. Returns corresponding system timestamp of the time
+- * of the vblank interval that corresponds to the current value vblank counter
+- * value.
++ * of the vblank interval that corresponds to the current vblank counter value.
+  */
+ u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
+ 			      struct timeval *vblanktime)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+ 	u32 cur_vblank;
+ 
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return 0;
++
+ 	/* Read timestamp from slot of _vblank_time ringbuffer
+ 	 * that corresponds to current vblank count. Retry if
+ 	 * count has incremented during readout. This works like
+ 	 * a seqlock.
+ 	 */
+ 	do {
+-		cur_vblank = atomic_read(&dev->vblank[crtc].count);
++		cur_vblank = atomic_read(&vblank->count);
+ 		*vblanktime = vblanktimestamp(dev, crtc, cur_vblank);
+ 		smp_rmb();
+-	} while (cur_vblank != atomic_read(&dev->vblank[crtc].count));
++	} while (cur_vblank != atomic_read(&vblank->count));
+ 
+ 	return cur_vblank;
+ }
+@@ -806,67 +923,40 @@
+ EXPORT_SYMBOL(drm_send_vblank_event);
+ 
+ /**
+- * drm_update_vblank_count - update the master vblank counter
++ * drm_vblank_enable - enable the vblank interrupt on a CRTC
+  * @dev: DRM device
+- * @crtc: counter to update
+- *
+- * Call back into the driver to update the appropriate vblank counter
+- * (specified by @crtc).  Deal with wraparound, if it occurred, and
+- * update the last read value so we can deal with wraparound on the next
+- * call if necessary.
+- *
+- * Only necessary when going from off->on, to account for frames we
+- * didn't get an interrupt for.
+- *
+- * Note: caller must hold dev->vbl_lock since this reads & writes
+- * device vblank fields.
++ * @crtc: CRTC in question
+  */
+-static void drm_update_vblank_count(struct drm_device *dev, int crtc)
++static int drm_vblank_enable(struct drm_device *dev, int crtc)
+ {
+-	u32 cur_vblank, diff, tslot, rc;
+-	struct timeval t_vblank;
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++	int ret = 0;
+ 
+-	/*
+-	 * Interrupts were disabled prior to this call, so deal with counter
+-	 * wrap if needed.
+-	 * NOTE!  It's possible we lost a full dev->max_vblank_count events
+-	 * here if the register is small or we had vblank interrupts off for
+-	 * a long time.
+-	 *
+-	 * We repeat the hardware vblank counter & timestamp query until
+-	 * we get consistent results. This to prevent races between gpu
+-	 * updating its hardware counter while we are retrieving the
+-	 * corresponding vblank timestamp.
+-	 */
+-	do {
+-		cur_vblank = dev->driver->get_vblank_counter(dev, crtc);
+-		rc = drm_get_last_vbltimestamp(dev, crtc, &t_vblank, 0);
+-	} while (cur_vblank != dev->driver->get_vblank_counter(dev, crtc));
++	assert_spin_locked(&dev->vbl_lock);
+ 
+-	/* Deal with counter wrap */
+-	diff = cur_vblank - dev->vblank[crtc].last;
+-	if (cur_vblank < dev->vblank[crtc].last) {
+-		diff += dev->max_vblank_count;
++	spin_lock(&dev->vblank_time_lock);
+ 
+-		DRM_DEBUG("last_vblank[%d]=0x%x, cur_vblank=0x%x => diff=0x%x\n",
+-			  crtc, dev->vblank[crtc].last, cur_vblank, diff);
++	if (!vblank->enabled) {
++		/*
++		 * Enable vblank irqs under vblank_time_lock protection.
++		 * All vblank count & timestamp updates are held off
++		 * until we are done reinitializing master counter and
++		 * timestamps. Filtercode in drm_handle_vblank() will
++		 * prevent double-accounting of same vblank interval.
++		 */
++		ret = dev->driver->enable_vblank(dev, crtc);
++		DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n", crtc, ret);
++		if (ret)
++			atomic_dec(&vblank->refcount);
++		else {
++			vblank->enabled = true;
++			drm_update_vblank_count(dev, crtc);
++		}
+ 	}
+ 
+-	DRM_DEBUG("enabling vblank interrupts on crtc %d, missed %d\n",
+-		  crtc, diff);
++	spin_unlock(&dev->vblank_time_lock);
+ 
+-	/* Reinitialize corresponding vblank timestamp if high-precision query
+-	 * available. Skip this step if query unsupported or failed. Will
+-	 * reinitialize delayed at next vblank interrupt in that case.
+-	 */
+-	if (rc) {
+-		tslot = atomic_read(&dev->vblank[crtc].count) + diff;
+-		vblanktimestamp(dev, crtc, tslot) = t_vblank;
+-	}
+-
+-	smp_mb__before_atomic_inc();
+-	atomic_add(diff, &dev->vblank[crtc].count);
+-	smp_mb__after_atomic_inc();
++	return ret;
+ }
+ 
+ /**
+@@ -877,39 +967,27 @@
+  * Acquire a reference count on vblank events to avoid having them disabled
+  * while in use.
+  *
+- * RETURNS
++ * This is the legacy version of drm_crtc_vblank_get().
++ *
++ * Returns:
+  * Zero on success, nonzero on failure.
+  */
+ int drm_vblank_get(struct drm_device *dev, int crtc)
+ {
+-	unsigned long irqflags, irqflags2;
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++	unsigned long irqflags;
+ 	int ret = 0;
+ 
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return -EINVAL;
++
+ 	spin_lock_irqsave(&dev->vbl_lock, irqflags);
+ 	/* Going from 0->1 means we have to enable interrupts again */
+-	if (atomic_add_return(1, &dev->vblank[crtc].refcount) == 1) {
+-		spin_lock_irqsave(&dev->vblank_time_lock, irqflags2);
+-		if (!dev->vblank[crtc].enabled) {
+-			/* Enable vblank irqs under vblank_time_lock protection.
+-			 * All vblank count & timestamp updates are held off
+-			 * until we are done reinitializing master counter and
+-			 * timestamps. Filtercode in drm_handle_vblank() will
+-			 * prevent double-accounting of same vblank interval.
+-			 */
+-			ret = dev->driver->enable_vblank(dev, crtc);
+-			DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n",
+-				  crtc, ret);
+-			if (ret)
+-				atomic_dec(&dev->vblank[crtc].refcount);
+-			else {
+-				dev->vblank[crtc].enabled = true;
+-				drm_update_vblank_count(dev, crtc);
+-			}
+-		}
+-		spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags2);
++	if (atomic_add_return(1, &vblank->refcount) == 1) {
++		ret = drm_vblank_enable(dev, crtc);
+ 	} else {
+-		if (!dev->vblank[crtc].enabled) {
+-			atomic_dec(&dev->vblank[crtc].refcount);
++		if (!vblank->enabled) {
++			atomic_dec(&vblank->refcount);
+ 			ret = -EINVAL;
+ 		}
+ 	}
+@@ -920,47 +998,159 @@
+ EXPORT_SYMBOL(drm_vblank_get);
+ 
+ /**
++ * drm_crtc_vblank_get - get a reference count on vblank events
++ * @crtc: which CRTC to own
++ *
++ * Acquire a reference count on vblank events to avoid having them disabled
++ * while in use.
++ *
++ * This is the native kms version of drm_vblank_off().
++ *
++ * Returns:
++ * Zero on success, nonzero on failure.
++ */
++int drm_crtc_vblank_get(struct drm_crtc *crtc)
++{
++	return drm_vblank_get(crtc->dev, drm_crtc_index(crtc));
++}
++EXPORT_SYMBOL(drm_crtc_vblank_get);
++
++/**
+  * drm_vblank_put - give up ownership of vblank events
+  * @dev: DRM device
+  * @crtc: which counter to give up
+  *
+  * Release ownership of a given vblank counter, turning off interrupts
+  * if possible. Disable interrupts after drm_vblank_offdelay milliseconds.
++ *
++ * This is the legacy version of drm_crtc_vblank_put().
+  */
+ void drm_vblank_put(struct drm_device *dev, int crtc)
+ {
+-	BUG_ON(atomic_read(&dev->vblank[crtc].refcount) == 0);
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++
++	if (WARN_ON(atomic_read(&vblank->refcount) == 0))
++		return;
++
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return;
+ 
+ 	/* Last user schedules interrupt disable */
+-	if (atomic_dec_and_test(&dev->vblank[crtc].refcount) &&
+-	    (drm_vblank_offdelay > 0))
+-		mod_timer(&dev->vblank_disable_timer,
+-			  jiffies + ((drm_vblank_offdelay * HZ)/1000));
++	if (atomic_dec_and_test(&vblank->refcount)) {
++		if (drm_vblank_offdelay == 0)
++			return;
++		else if (dev->vblank_disable_immediate || drm_vblank_offdelay < 0)
++			vblank_disable_fn((unsigned long)vblank);
++		else
++			mod_timer(&vblank->disable_timer,
++				  jiffies + ((drm_vblank_offdelay * HZ)/1000));
++	}
+ }
+ EXPORT_SYMBOL(drm_vblank_put);
+ 
+ /**
++ * drm_crtc_vblank_put - give up ownership of vblank events
++ * @crtc: which counter to give up
++ *
++ * Release ownership of a given vblank counter, turning off interrupts
++ * if possible. Disable interrupts after drm_vblank_offdelay milliseconds.
++ *
++ * This is the native kms version of drm_vblank_put().
++ */
++void drm_crtc_vblank_put(struct drm_crtc *crtc)
++{
++	drm_vblank_put(crtc->dev, drm_crtc_index(crtc));
++}
++EXPORT_SYMBOL(drm_crtc_vblank_put);
++
++/**
++ * drm_wait_one_vblank - wait for one vblank
++ * @dev: DRM device
++ * @crtc: crtc index
++ *
++ * This waits for one vblank to pass on @crtc, using the irq driver interfaces.
++ * It is a failure to call this when the vblank irq for @crtc is disabled, e.g.
++ * due to lack of driver support or because the crtc is off.
++ */
++void drm_wait_one_vblank(struct drm_device *dev, int crtc)
++{
++	int ret;
++	u32 last;
++
++	ret = drm_vblank_get(dev, crtc);
++	if (WARN(ret, "vblank not available on crtc %i, ret=%i\n", crtc, ret))
++		return;
++
++	last = drm_vblank_count(dev, crtc);
++
++	ret = wait_event_timeout(dev->vblank[crtc].queue,
++				 last != drm_vblank_count(dev, crtc),
++				 msecs_to_jiffies(100));
++
++	WARN(ret == 0, "vblank wait timed out on crtc %i\n", crtc);
++
++	drm_vblank_put(dev, crtc);
++}
++EXPORT_SYMBOL(drm_wait_one_vblank);
++
++/**
++ * drm_crtc_wait_one_vblank - wait for one vblank
++ * @crtc: DRM crtc
++ *
++ * This waits for one vblank to pass on @crtc, using the irq driver interfaces.
++ * It is a failure to call this when the vblank irq for @crtc is disabled, e.g.
++ * due to lack of driver support or because the crtc is off.
++ */
++void drm_crtc_wait_one_vblank(struct drm_crtc *crtc)
++{
++	drm_wait_one_vblank(crtc->dev, drm_crtc_index(crtc));
++}
++EXPORT_SYMBOL(drm_crtc_wait_one_vblank);
++
++/**
+  * drm_vblank_off - disable vblank events on a CRTC
+  * @dev: DRM device
+  * @crtc: CRTC in question
+  *
+- * Caller must hold event lock.
++ * Drivers can use this function to shut down the vblank interrupt handling when
++ * disabling a crtc. This function ensures that the latest vblank frame count is
++ * stored so that drm_vblank_on() can restore it again.
++ *
++ * Drivers must use this function when the hardware vblank counter can get
++ * reset, e.g. when suspending.
++ *
++ * This is the legacy version of drm_crtc_vblank_off().
+  */
+ void drm_vblank_off(struct drm_device *dev, int crtc)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+ 	struct drm_pending_vblank_event *e, *t;
+ 	struct timeval now;
+ 	unsigned long irqflags;
+ 	unsigned int seq;
+ 
+-	spin_lock_irqsave(&dev->vbl_lock, irqflags);
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return;
++
++	spin_lock_irqsave(&dev->event_lock, irqflags);
++
++	spin_lock(&dev->vbl_lock);
+ 	vblank_disable_and_save(dev, crtc);
+-	wake_up(&dev->vblank[crtc].queue);
++	wake_up(&vblank->queue);
++
++	/*
++	 * Prevent subsequent drm_vblank_get() from re-enabling
++	 * the vblank interrupt by bumping the refcount.
++	 */
++	if (!vblank->inmodeset) {
++		atomic_inc(&vblank->refcount);
++		vblank->inmodeset = 1;
++	}
++	spin_unlock(&dev->vbl_lock);
+ 
+ 	/* Send any queued vblank events, lest the natives grow disquiet */
+ 	seq = drm_vblank_count_and_time(dev, crtc, &now);
+ 
+-	spin_lock(&dev->event_lock);
+ 	list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) {
+ 		if (e->pipe != crtc)
+ 			continue;
+@@ -971,11 +1161,93 @@
+ 		drm_vblank_put(dev, e->pipe);
+ 		send_vblank_event(dev, e, seq, &now);
+ 	}
+-	spin_unlock(&dev->event_lock);
++	spin_unlock_irqrestore(&dev->event_lock, irqflags);
++}
++EXPORT_SYMBOL(drm_vblank_off);
++
++/**
++ * drm_crtc_vblank_off - disable vblank events on a CRTC
++ * @crtc: CRTC in question
++ *
++ * Drivers can use this function to shut down the vblank interrupt handling when
++ * disabling a crtc. This function ensures that the latest vblank frame count is
++ * stored so that drm_vblank_on can restore it again.
++ *
++ * Drivers must use this function when the hardware vblank counter can get
++ * reset, e.g. when suspending.
++ *
++ * This is the native kms version of drm_vblank_off().
++ */
++void drm_crtc_vblank_off(struct drm_crtc *crtc)
++{
++	drm_vblank_off(crtc->dev, drm_crtc_index(crtc));
++}
++EXPORT_SYMBOL(drm_crtc_vblank_off);
++
++/**
++ * drm_vblank_on - enable vblank events on a CRTC
++ * @dev: DRM device
++ * @crtc: CRTC in question
++ *
++ * This functions restores the vblank interrupt state captured with
++ * drm_vblank_off() again. Note that calls to drm_vblank_on() and
++ * drm_vblank_off() can be unbalanced and so can also be unconditionally called
++ * in driver load code to reflect the current hardware state of the crtc.
++ *
++ * This is the legacy version of drm_crtc_vblank_on().
++ */
++void drm_vblank_on(struct drm_device *dev, int crtc)
++{
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++	unsigned long irqflags;
++
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return;
++
++	spin_lock_irqsave(&dev->vbl_lock, irqflags);
++	/* Drop our private "prevent drm_vblank_get" refcount */
++	if (vblank->inmodeset) {
++		atomic_dec(&vblank->refcount);
++		vblank->inmodeset = 0;
++	}
+ 
++	/*
++	 * sample the current counter to avoid random jumps
++	 * when drm_vblank_enable() applies the diff
++	 *
++	 * -1 to make sure user will never see the same
++	 * vblank counter value before and after a modeset
++	 */
++	vblank->last =
++		(dev->driver->get_vblank_counter(dev, crtc) - 1) &
++		dev->max_vblank_count;
++	/*
++	 * re-enable interrupts if there are users left, or the
++	 * user wishes vblank interrupts to be enabled all the time.
++	 */
++	if (atomic_read(&vblank->refcount) != 0 ||
++	    (!dev->vblank_disable_immediate && drm_vblank_offdelay == 0))
++		WARN_ON(drm_vblank_enable(dev, crtc));
+ 	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+ }
+-EXPORT_SYMBOL(drm_vblank_off);
++EXPORT_SYMBOL(drm_vblank_on);
++
++/**
++ * drm_crtc_vblank_on - enable vblank events on a CRTC
++ * @crtc: CRTC in question
++ *
++ * This functions restores the vblank interrupt state captured with
++ * drm_vblank_off() again. Note that calls to drm_vblank_on() and
++ * drm_vblank_off() can be unbalanced and so can also be unconditionally called
++ * in driver load code to reflect the current hardware state of the crtc.
++ *
++ * This is the native kms version of drm_vblank_on().
++ */
++void drm_crtc_vblank_on(struct drm_crtc *crtc)
++{
++	drm_vblank_on(crtc->dev, drm_crtc_index(crtc));
++}
++EXPORT_SYMBOL(drm_crtc_vblank_on);
+ 
+ /**
+  * drm_vblank_pre_modeset - account for vblanks across mode sets
+@@ -984,12 +1256,33 @@
+  *
+  * Account for vblank events across mode setting events, which will likely
+  * reset the hardware frame counter.
++ *
++ * This is done by grabbing a temporary vblank reference to ensure that the
++ * vblank interrupt keeps running across the modeset sequence. With this the
++ * software-side vblank frame counting will ensure that there are no jumps or
++ * discontinuities.
++ *
++ * Unfortunately this approach is racy and also doesn't work when the vblank
++ * interrupt stops running, e.g. across system suspend resume. It is therefore
++ * highly recommended that drivers use the newer drm_vblank_off() and
++ * drm_vblank_on() instead. drm_vblank_pre_modeset() only works correctly when
++ * using "cooked" software vblank frame counters and not relying on any hardware
++ * counters.
++ *
++ * Drivers must call drm_vblank_post_modeset() when re-enabling the same crtc
++ * again.
+  */
+ void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
++
+ 	/* vblank is not initialized (IRQ not installed ?), or has been freed */
+ 	if (!dev->num_crtcs)
+ 		return;
++
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return;
++
+ 	/*
+ 	 * To avoid all the problems that might happen if interrupts
+ 	 * were enabled/disabled around or between these calls, we just
+@@ -997,36 +1290,45 @@
+ 	 * to avoid corrupting the count if multiple, mismatch calls occur),
+ 	 * so that interrupts remain enabled in the interim.
+ 	 */
+-	if (!dev->vblank[crtc].inmodeset) {
+-		dev->vblank[crtc].inmodeset = 0x1;
++	if (!vblank->inmodeset) {
++		vblank->inmodeset = 0x1;
+ 		if (drm_vblank_get(dev, crtc) == 0)
+-			dev->vblank[crtc].inmodeset |= 0x2;
++			vblank->inmodeset |= 0x2;
+ 	}
+ }
+ EXPORT_SYMBOL(drm_vblank_pre_modeset);
+ 
++/**
++ * drm_vblank_post_modeset - undo drm_vblank_pre_modeset changes
++ * @dev: DRM device
++ * @crtc: CRTC in question
++ *
++ * This function again drops the temporary vblank reference acquired in
++ * drm_vblank_pre_modeset.
++ */
+ void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+ 	unsigned long irqflags;
+ 
+ 	/* vblank is not initialized (IRQ not installed ?), or has been freed */
+ 	if (!dev->num_crtcs)
+ 		return;
+ 
+-	if (dev->vblank[crtc].inmodeset) {
++	if (vblank->inmodeset) {
+ 		spin_lock_irqsave(&dev->vbl_lock, irqflags);
+ 		dev->vblank_disable_allowed = true;
+ 		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+ 
+-		if (dev->vblank[crtc].inmodeset & 0x2)
++		if (vblank->inmodeset & 0x2)
+ 			drm_vblank_put(dev, crtc);
+ 
+-		dev->vblank[crtc].inmodeset = 0;
++		vblank->inmodeset = 0;
+ 	}
+ }
+ EXPORT_SYMBOL(drm_vblank_post_modeset);
+ 
+-/**
++/*
+  * drm_modeset_ctl - handle vblank event counter changes across mode switch
+  * @DRM_IOCTL_ARGS: standard ioctl arguments
+  *
+@@ -1073,6 +1375,7 @@
+ 				  union drm_wait_vblank *vblwait,
+ 				  struct drm_file *file_priv)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
+ 	struct drm_pending_vblank_event *e;
+ 	struct timeval now;
+ 	unsigned long flags;
+@@ -1096,6 +1399,18 @@
+ 
+ 	spin_lock_irqsave(&dev->event_lock, flags);
+ 
++	/*
++	 * drm_vblank_off() might have been called after we called
++	 * drm_vblank_get(). drm_vblank_off() holds event_lock
++	 * around the vblank disable, so no need for further locking.
++	 * The reference from drm_vblank_get() protects against
++	 * vblank disable from another source.
++	 */
++	if (!vblank->enabled) {
++		ret = -EINVAL;
++		goto err_unlock;
++	}
++
+ 	if (file_priv->event_space < sizeof e->event) {
+ 		ret = -EBUSY;
+ 		goto err_unlock;
+@@ -1139,7 +1454,7 @@
+ 	return ret;
+ }
+ 
+-/**
++/*
+  * Wait for VBLANK.
+  *
+  * \param inode device inode.
+@@ -1150,19 +1465,19 @@
+  *
+  * This function enables the vblank interrupt on the pipe requested, then
+  * sleeps waiting for the requested sequence number to occur, and drops
+- * the vblank interrupt refcount afterwards. (vblank irq disable follows that
++ * the vblank interrupt refcount afterwards. (vblank IRQ disable follows that
+  * after a timeout with no further vblank waits scheduled).
+  */
+ int drm_wait_vblank(struct drm_device *dev, void *data,
+ 		    struct drm_file *file_priv)
+ {
++	struct drm_vblank_crtc *vblank;
+ 	union drm_wait_vblank *vblwait = data;
+ 	int ret;
+ 	unsigned int flags, seq, crtc, high_crtc;
+ 
+-	if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
+-		if ((!drm_dev_to_irq(dev)) || (!dev->irq_enabled))
+-			return -EINVAL;
++	if (!dev->irq_enabled)
++		return -EINVAL;
+ 
+ 	if (vblwait->request.type & _DRM_VBLANK_SIGNAL)
+ 		return -EINVAL;
+@@ -1186,6 +1501,8 @@
+ 	if (crtc >= dev->num_crtcs)
+ 		return -EINVAL;
+ 
++	vblank = &dev->vblank[crtc];
++
+ 	ret = drm_vblank_get(dev, crtc);
+ 	if (ret) {
+ 		DRM_DEBUG("failed to acquire vblank counter, %d\n", ret);
+@@ -1218,10 +1535,11 @@
+ 
+ 	DRM_DEBUG("waiting on vblank count %d, crtc %d\n",
+ 		  vblwait->request.sequence, crtc);
+-	dev->vblank[crtc].last_wait = vblwait->request.sequence;
+-	DRM_WAIT_ON(ret, dev->vblank[crtc].queue, 3 * HZ,
++	vblank->last_wait = vblwait->request.sequence;
++	DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
+ 		    (((drm_vblank_count(dev, crtc) -
+ 		       vblwait->request.sequence) <= (1 << 23)) ||
++		     !vblank->enabled ||
+ 		     !dev->irq_enabled));
+ 
+ 	if (ret != -EINTR) {
+@@ -1246,12 +1564,11 @@
+ {
+ 	struct drm_pending_vblank_event *e, *t;
+ 	struct timeval now;
+-	unsigned long flags;
+ 	unsigned int seq;
+ 
+-	seq = drm_vblank_count_and_time(dev, crtc, &now);
++	assert_spin_locked(&dev->event_lock);
+ 
+-	spin_lock_irqsave(&dev->event_lock, flags);
++	seq = drm_vblank_count_and_time(dev, crtc, &now);
+ 
+ 	list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) {
+ 		if (e->pipe != crtc)
+@@ -1267,8 +1584,6 @@
+ 		send_vblank_event(dev, e, seq, &now);
+ 	}
+ 
+-	spin_unlock_irqrestore(&dev->event_lock, flags);
+-
+ 	trace_drm_vblank_event(crtc, seq);
+ }
+ 
+@@ -1282,6 +1597,7 @@
+  */
+ bool drm_handle_vblank(struct drm_device *dev, int crtc)
+ {
++	struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+ 	u32 vblcount;
+ 	s64 diff_ns;
+ 	struct timeval tvblank;
+@@ -1290,15 +1606,21 @@
+ 	if (!dev->num_crtcs)
+ 		return false;
+ 
++	if (WARN_ON(crtc >= dev->num_crtcs))
++		return false;
++
++	spin_lock_irqsave(&dev->event_lock, irqflags);
++
+ 	/* Need timestamp lock to prevent concurrent execution with
+ 	 * vblank enable/disable, as this would cause inconsistent
+ 	 * or corrupted timestamps and vblank counts.
+ 	 */
+-	spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
++	spin_lock(&dev->vblank_time_lock);
+ 
+ 	/* Vblank irq handling disabled. Nothing to do. */
+-	if (!dev->vblank[crtc].enabled) {
+-		spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
++	if (!vblank->enabled) {
++		spin_unlock(&dev->vblank_time_lock);
++		spin_unlock_irqrestore(&dev->event_lock, irqflags);
+ 		return false;
+ 	}
+ 
+@@ -1307,7 +1629,7 @@
+ 	 */
+ 
+ 	/* Get current timestamp and count. */
+-	vblcount = atomic_read(&dev->vblank[crtc].count);
++	vblcount = atomic_read(&vblank->count);
+ 	drm_get_last_vbltimestamp(dev, crtc, &tvblank, DRM_CALLED_FROM_VBLIRQ);
+ 
+ 	/* Compute time difference to timestamp of last vblank */
+@@ -1331,17 +1653,20 @@
+ 		 * the timestamp computed above.
+ 		 */
+ 		smp_mb__before_atomic_inc();
+-		atomic_inc(&dev->vblank[crtc].count);
++		atomic_inc(&vblank->count);
+ 		smp_mb__after_atomic_inc();
+ 	} else {
+ 		DRM_DEBUG("crtc %d: Redundant vblirq ignored. diff_ns = %d\n",
+ 			  crtc, (int) diff_ns);
+ 	}
+ 
+-	wake_up(&dev->vblank[crtc].queue);
++	spin_unlock(&dev->vblank_time_lock);
++
++	wake_up(&vblank->queue);
+ 	drm_handle_vblank_events(dev, crtc);
+ 
+-	spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
++	spin_unlock_irqrestore(&dev->event_lock, irqflags);
++
+ 	return true;
+ }
+ EXPORT_SYMBOL(drm_handle_vblank);
+diff -Naur a/drivers/gpu/drm/drm_legacy.h b/drivers/gpu/drm/drm_legacy.h
+--- a/drivers/gpu/drm/drm_legacy.h	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_legacy.h	2015-03-26 14:42:38.730435422 +0530
+@@ -0,0 +1,113 @@
++#ifndef __DRM_LEGACY_H__
++#define __DRM_LEGACY_H__
++
++/*
++ * Copyright (c) 2014 David Herrmann <dh.herrmann@gmail.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/*
++ * This file contains legacy interfaces that modern drm drivers
++ * should no longer be using. They cannot be removed as legacy
++ * drivers use them, and removing them are API breaks.
++ */
++#include <linux/list.h>
++#include <drm/drm_legacy.h>
++
++struct agp_memory;
++struct drm_device;
++struct drm_file;
++
++/*
++ * Generic DRM Contexts
++ */
++
++#define DRM_KERNEL_CONTEXT		0
++#define DRM_RESERVED_CONTEXTS		1
++
++int drm_legacy_ctxbitmap_init(struct drm_device *dev);
++void drm_legacy_ctxbitmap_cleanup(struct drm_device *dev);
++void drm_legacy_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
++void drm_legacy_ctxbitmap_flush(struct drm_device *dev, struct drm_file *file);
++
++int drm_legacy_resctx(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_addctx(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_getctx(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_switchctx(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_newctx(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_rmctx(struct drm_device *d, void *v, struct drm_file *f);
++
++int drm_legacy_setsareactx(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_getsareactx(struct drm_device *d, void *v, struct drm_file *f);
++
++/*
++ * Generic Buffer Management
++ */
++
++#define DRM_MAP_HASH_OFFSET 0x10000000
++
++int drm_legacy_addmap_ioctl(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_rmmap_ioctl(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_addbufs(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_infobufs(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_markbufs(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_freebufs(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_mapbufs(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_dma_ioctl(struct drm_device *d, void *v, struct drm_file *f);
++
++void drm_legacy_vma_flush(struct drm_device *d);
++
++/*
++ * AGP Support
++ */
++
++struct drm_agp_mem {
++	unsigned long handle;
++	struct agp_memory *memory;
++	unsigned long bound;
++	int pages;
++	struct list_head head;
++};
++
++/*
++ * Generic Userspace Locking-API
++ */
++
++int drm_legacy_i_have_hw_lock(struct drm_device *d, struct drm_file *f);
++int drm_legacy_lock(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_unlock(struct drm_device *d, void *v, struct drm_file *f);
++int drm_legacy_lock_free(struct drm_lock_data *lock, unsigned int ctx);
++
++/* DMA support */
++int drm_legacy_dma_setup(struct drm_device *dev);
++void drm_legacy_dma_takedown(struct drm_device *dev);
++void drm_legacy_free_buffer(struct drm_device *dev,
++			    struct drm_buf * buf);
++void drm_legacy_reclaim_buffers(struct drm_device *dev,
++				struct drm_file *filp);
++
++/* Scatter Gather Support */
++void drm_legacy_sg_cleanup(struct drm_device *dev);
++int drm_legacy_sg_alloc(struct drm_device *dev, void *data,
++			struct drm_file *file_priv);
++int drm_legacy_sg_free(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv);
++
++#endif /* __DRM_LEGACY_H__ */
+diff -Naur a/drivers/gpu/drm/drm_lock.c b/drivers/gpu/drm/drm_lock.c
+--- a/drivers/gpu/drm/drm_lock.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/drm_lock.c	2015-03-26 14:42:38.730435422 +0530
+@@ -35,6 +35,8 @@
+ 
+ #include <linux/export.h>
+ #include <drm/drmP.h>
++#include "drm_legacy.h"
++#include "drm_internal.h"
+ 
+ static int drm_notifier(void *priv);
+ 
+@@ -51,7 +53,8 @@
+  *
+  * Add the current task to the lock wait queue, and attempt to take to lock.
+  */
+-int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
++int drm_legacy_lock(struct drm_device *dev, void *data,
++		    struct drm_file *file_priv)
+ {
+ 	DECLARE_WAITQUEUE(entry, current);
+ 	struct drm_lock *lock = data;
+@@ -119,7 +122,7 @@
+ 		sigaddset(&dev->sigmask, SIGTTOU);
+ 		dev->sigdata.context = lock->context;
+ 		dev->sigdata.lock = master->lock.hw_lock;
+-		block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
++		block_all_signals(drm_notifier, dev, &dev->sigmask);
+ 	}
+ 
+ 	if (dev->driver->dma_quiescent && (lock->flags & _DRM_LOCK_QUIESCENT))
+@@ -145,7 +148,7 @@
+  *
+  * Transfer and free the lock.
+  */
+-int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
++int drm_legacy_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
+ {
+ 	struct drm_lock *lock = data;
+ 	struct drm_master *master = file_priv->master;
+@@ -156,7 +159,7 @@
+ 		return -EINVAL;
+ 	}
+ 
+-	if (drm_lock_free(&master->lock, lock->context)) {
++	if (drm_legacy_lock_free(&master->lock, lock->context)) {
+ 		/* FIXME: Should really bail out here. */
+ 	}
+ 
+@@ -249,7 +252,7 @@
+  * Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task
+  * waiting on the lock queue.
+  */
+-int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context)
++int drm_legacy_lock_free(struct drm_lock_data *lock_data, unsigned int context)
+ {
+ 	unsigned int old, new, prev;
+ 	volatile unsigned int *lock = &lock_data->hw_lock->lock;
+@@ -285,26 +288,27 @@
+  * If the lock is not held, then let the signal proceed as usual.  If the lock
+  * is held, then set the contended flag and keep the signal blocked.
+  *
+- * \param priv pointer to a drm_sigdata structure.
++ * \param priv pointer to a drm_device structure.
+  * \return one if the signal should be delivered normally, or zero if the
+  * signal should be blocked.
+  */
+ static int drm_notifier(void *priv)
+ {
+-	struct drm_sigdata *s = (struct drm_sigdata *) priv;
++	struct drm_device *dev = priv;
++	struct drm_hw_lock *lock = dev->sigdata.lock;
+ 	unsigned int old, new, prev;
+ 
+ 	/* Allow signal delivery if lock isn't held */
+-	if (!s->lock || !_DRM_LOCK_IS_HELD(s->lock->lock)
+-	    || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context)
++	if (!lock || !_DRM_LOCK_IS_HELD(lock->lock)
++	    || _DRM_LOCKING_CONTEXT(lock->lock) != dev->sigdata.context)
+ 		return 1;
+ 
+ 	/* Otherwise, set flag to force call to
+ 	   drmUnlock */
+ 	do {
+-		old = s->lock->lock;
++		old = lock->lock;
+ 		new = old | _DRM_LOCK_CONT;
+-		prev = cmpxchg(&s->lock->lock, old, new);
++		prev = cmpxchg(&lock->lock, old, new);
+ 	} while (prev != old);
+ 	return 0;
+ }
+@@ -322,7 +326,7 @@
+  * having to worry about starvation.
+  */
+ 
+-void drm_idlelock_take(struct drm_lock_data *lock_data)
++void drm_legacy_idlelock_take(struct drm_lock_data *lock_data)
+ {
+ 	int ret;
+ 
+@@ -339,9 +343,9 @@
+ 	}
+ 	spin_unlock_bh(&lock_data->spinlock);
+ }
+-EXPORT_SYMBOL(drm_idlelock_take);
++EXPORT_SYMBOL(drm_legacy_idlelock_take);
+ 
+-void drm_idlelock_release(struct drm_lock_data *lock_data)
++void drm_legacy_idlelock_release(struct drm_lock_data *lock_data)
+ {
+ 	unsigned int old, prev;
+ 	volatile unsigned int *lock = &lock_data->hw_lock->lock;
+@@ -359,9 +363,10 @@
+ 	}
+ 	spin_unlock_bh(&lock_data->spinlock);
+ }
+-EXPORT_SYMBOL(drm_idlelock_release);
++EXPORT_SYMBOL(drm_legacy_idlelock_release);
+ 
+-int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv)
++int drm_legacy_i_have_hw_lock(struct drm_device *dev,
++			      struct drm_file *file_priv)
+ {
+ 	struct drm_master *master = file_priv->master;
+ 	return (file_priv->lock_count && master->lock.hw_lock &&
+diff -Naur a/drivers/gpu/drm/drm_memory.c b/drivers/gpu/drm/drm_memory.c
+--- a/drivers/gpu/drm/drm_memory.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_memory.c	2015-03-26 14:42:38.730435422 +0530
+@@ -36,8 +36,20 @@
+ #include <linux/highmem.h>
+ #include <linux/export.h>
+ #include <drm/drmP.h>
++#include "drm_legacy.h"
+ 
+ #if __OS_HAS_AGP
++
++#ifdef HAVE_PAGE_AGP
++# include <asm/agp.h>
++#else
++# ifdef __powerpc__
++#  define PAGE_AGP	__pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
++# else
++#  define PAGE_AGP	PAGE_KERNEL
++# endif
++#endif
++
+ static void *agp_remap(unsigned long offset, unsigned long size,
+ 		       struct drm_device * dev)
+ {
+@@ -108,25 +120,25 @@
+ 
+ #endif				/* agp */
+ 
+-void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev)
++void drm_legacy_ioremap(struct drm_local_map *map, struct drm_device *dev)
+ {
+ 	if (dev->agp && dev->agp->cant_use_aperture && map->type == _DRM_AGP)
+ 		map->handle = agp_remap(map->offset, map->size, dev);
+ 	else
+ 		map->handle = ioremap(map->offset, map->size);
+ }
+-EXPORT_SYMBOL(drm_core_ioremap);
++EXPORT_SYMBOL(drm_legacy_ioremap);
+ 
+-void drm_core_ioremap_wc(struct drm_local_map *map, struct drm_device *dev)
++void drm_legacy_ioremap_wc(struct drm_local_map *map, struct drm_device *dev)
+ {
+ 	if (dev->agp && dev->agp->cant_use_aperture && map->type == _DRM_AGP)
+ 		map->handle = agp_remap(map->offset, map->size, dev);
+ 	else
+ 		map->handle = ioremap_wc(map->offset, map->size);
+ }
+-EXPORT_SYMBOL(drm_core_ioremap_wc);
++EXPORT_SYMBOL(drm_legacy_ioremap_wc);
+ 
+-void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev)
++void drm_legacy_ioremapfree(struct drm_local_map *map, struct drm_device *dev)
+ {
+ 	if (!map->handle || !map->size)
+ 		return;
+@@ -136,4 +148,4 @@
+ 	else
+ 		iounmap(map->handle);
+ }
+-EXPORT_SYMBOL(drm_core_ioremapfree);
++EXPORT_SYMBOL(drm_legacy_ioremapfree);
+diff -Naur a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
+--- a/drivers/gpu/drm/drm_mipi_dsi.c	2015-03-26 14:43:30.410436435 +0530
++++ b/drivers/gpu/drm/drm_mipi_dsi.c	2015-03-26 14:42:38.730435422 +0530
+@@ -35,6 +35,16 @@
+ 
+ #include <video/mipi_display.h>
+ 
++/**
++ * DOC: dsi helpers
++ *
++ * These functions contain some common logic and helpers to deal with MIPI DSI
++ * peripherals.
++ *
++ * Helpers are provided for a number of standard MIPI DSI command as well as a
++ * subset of the MIPI DCS command set.
++ */
++
+ static int mipi_dsi_device_match(struct device *dev, struct device_driver *drv)
+ {
+ 	return of_driver_match_device(dev, drv);
+@@ -57,6 +67,29 @@
+ 	.pm = &mipi_dsi_device_pm_ops,
+ };
+ 
++static int of_device_match(struct device *dev, void *data)
++{
++	return dev->of_node == data;
++}
++
++/**
++ * of_find_mipi_dsi_device_by_node() - find the MIPI DSI device matching a
++ *    device tree node
++ * @np: device tree node
++ *
++ * Return: A pointer to the MIPI DSI device corresponding to @np or NULL if no
++ *    such device exists (or has not been registered yet).
++ */
++struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node *np)
++{
++	struct device *dev;
++
++	dev = bus_find_device(&mipi_dsi_bus_type, NULL, np, of_device_match);
++
++	return dev ? to_mipi_dsi_device(dev) : NULL;
++}
++EXPORT_SYMBOL(of_find_mipi_dsi_device_by_node);
++
+ static void mipi_dsi_dev_release(struct device *dev)
+ {
+ 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+@@ -142,8 +175,12 @@
+ {
+ 	struct device_node *node;
+ 
+-	for_each_available_child_of_node(host->dev->of_node, node)
++	for_each_available_child_of_node(host->dev->of_node, node) {
++		/* skip nodes without reg property */
++		if (!of_find_property(node, "reg", NULL))
++			continue;
+ 		of_mipi_dsi_device_add(host, node);
++	}
+ 
+ 	return 0;
+ }
+@@ -194,60 +231,353 @@
+ }
+ EXPORT_SYMBOL(mipi_dsi_detach);
+ 
++static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
++					struct mipi_dsi_msg *msg)
++{
++	const struct mipi_dsi_host_ops *ops = dsi->host->ops;
++
++	if (!ops || !ops->transfer)
++		return -ENOSYS;
++
++	if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
++		msg->flags |= MIPI_DSI_MSG_USE_LPM;
++
++	return ops->transfer(dsi->host, msg);
++}
++
+ /**
+- * mipi_dsi_dcs_write - send DCS write command
+- * @dsi: DSI device
+- * @channel: virtual channel
+- * @data: pointer to the command followed by parameters
+- * @len: length of @data
++ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
++ * @type: MIPI DSI data type of the packet
++ *
++ * Return: true if the packet for the given data type is a short packet, false
++ * otherwise.
+  */
+-int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int channel,
+-		       const void *data, size_t len)
++bool mipi_dsi_packet_format_is_short(u8 type)
+ {
+-	const struct mipi_dsi_host_ops *ops = dsi->host->ops;
++	switch (type) {
++	case MIPI_DSI_V_SYNC_START:
++	case MIPI_DSI_V_SYNC_END:
++	case MIPI_DSI_H_SYNC_START:
++	case MIPI_DSI_H_SYNC_END:
++	case MIPI_DSI_END_OF_TRANSMISSION:
++	case MIPI_DSI_COLOR_MODE_OFF:
++	case MIPI_DSI_COLOR_MODE_ON:
++	case MIPI_DSI_SHUTDOWN_PERIPHERAL:
++	case MIPI_DSI_TURN_ON_PERIPHERAL:
++	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
++	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
++	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
++	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
++	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
++	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
++	case MIPI_DSI_DCS_SHORT_WRITE:
++	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
++	case MIPI_DSI_DCS_READ:
++	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
++		return true;
++	}
++
++	return false;
++}
++EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
++
++/**
++ * mipi_dsi_packet_format_is_long - check if a packet is of the long format
++ * @type: MIPI DSI data type of the packet
++ *
++ * Return: true if the packet for the given data type is a long packet, false
++ * otherwise.
++ */
++bool mipi_dsi_packet_format_is_long(u8 type)
++{
++	switch (type) {
++	case MIPI_DSI_NULL_PACKET:
++	case MIPI_DSI_BLANKING_PACKET:
++	case MIPI_DSI_GENERIC_LONG_WRITE:
++	case MIPI_DSI_DCS_LONG_WRITE:
++	case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_30:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_36:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_16:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_18:
++	case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
++	case MIPI_DSI_PACKED_PIXEL_STREAM_24:
++		return true;
++	}
++
++	return false;
++}
++EXPORT_SYMBOL(mipi_dsi_packet_format_is_long);
++
++/**
++ * mipi_dsi_create_packet - create a packet from a message according to the
++ *     DSI protocol
++ * @packet: pointer to a DSI packet structure
++ * @msg: message to translate into a packet
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
++			   const struct mipi_dsi_msg *msg)
++{
++	const u8 *tx = msg->tx_buf;
++
++	if (!packet || !msg)
++		return -EINVAL;
++
++	/* do some minimum sanity checking */
++	if (!mipi_dsi_packet_format_is_short(msg->type) &&
++	    !mipi_dsi_packet_format_is_long(msg->type))
++		return -EINVAL;
++
++	if (msg->channel > 3)
++		return -EINVAL;
++
++	memset(packet, 0, sizeof(*packet));
++	packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f);
++
++	/* TODO: compute ECC if hardware support is not available */
++
++	/*
++	 * Long write packets contain the word count in header bytes 1 and 2.
++	 * The payload follows the header and is word count bytes long.
++	 *
++	 * Short write packets encode up to two parameters in header bytes 1
++	 * and 2.
++	 */
++	if (mipi_dsi_packet_format_is_long(msg->type)) {
++		packet->header[1] = (msg->tx_len >> 0) & 0xff;
++		packet->header[2] = (msg->tx_len >> 8) & 0xff;
++
++		packet->payload_length = msg->tx_len;
++		packet->payload = tx;
++	} else {
++		packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0;
++		packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0;
++	}
++
++	packet->size = sizeof(packet->header) + packet->payload_length;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_create_packet);
++
++/*
++ * mipi_dsi_set_maximum_return_packet_size() - specify the maximum size of the
++ *    the payload in a long packet transmitted from the peripheral back to the
++ *    host processor
++ * @dsi: DSI peripheral device
++ * @value: the maximum size of the payload
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
++					    u16 value)
++{
++	u8 tx[2] = { value & 0xff, value >> 8 };
+ 	struct mipi_dsi_msg msg = {
+-		.channel = channel,
++		.channel = dsi->channel,
++		.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
++		.tx_len = sizeof(tx),
++		.tx_buf = tx,
++	};
++
++	return mipi_dsi_device_transfer(dsi, &msg);
++}
++EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
++
++/**
++ * mipi_dsi_generic_write() - transmit data using a generic write packet
++ * @dsi: DSI peripheral device
++ * @payload: buffer containing the payload
++ * @size: size of payload buffer
++ *
++ * This function will automatically choose the right data type depending on
++ * the payload length.
++ *
++ * Return: The number of bytes transmitted on success or a negative error code
++ * on failure.
++ */
++ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
++			       size_t size)
++{
++	struct mipi_dsi_msg msg = {
++		.channel = dsi->channel,
++		.tx_buf = payload,
++		.tx_len = size
++	};
++
++	switch (size) {
++	case 0:
++		msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
++		break;
++
++	case 1:
++		msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
++		break;
++
++	case 2:
++		msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
++		break;
++
++	default:
++		msg.type = MIPI_DSI_GENERIC_LONG_WRITE;
++		break;
++	}
++
++	return mipi_dsi_device_transfer(dsi, &msg);
++}
++EXPORT_SYMBOL(mipi_dsi_generic_write);
++
++/**
++ * mipi_dsi_generic_read() - receive data using a generic read packet
++ * @dsi: DSI peripheral device
++ * @params: buffer containing the request parameters
++ * @num_params: number of request parameters
++ * @data: buffer in which to return the received data
++ * @size: size of receive buffer
++ *
++ * This function will automatically choose the right data type depending on
++ * the number of parameters passed in.
++ *
++ * Return: The number of bytes successfully read or a negative error code on
++ * failure.
++ */
++ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params,
++			      size_t num_params, void *data, size_t size)
++{
++	struct mipi_dsi_msg msg = {
++		.channel = dsi->channel,
++		.tx_len = num_params,
++		.tx_buf = params,
++		.rx_len = size,
++		.rx_buf = data
++	};
++
++	switch (num_params) {
++	case 0:
++		msg.type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
++		break;
++
++	case 1:
++		msg.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
++		break;
++
++	case 2:
++		msg.type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	return mipi_dsi_device_transfer(dsi, &msg);
++}
++EXPORT_SYMBOL(mipi_dsi_generic_read);
++
++/**
++ * mipi_dsi_dcs_write_buffer() - transmit a DCS command with payload
++ * @dsi: DSI peripheral device
++ * @data: buffer containing data to be transmitted
++ * @len: size of transmission buffer
++ *
++ * This function will automatically choose the right data type depending on
++ * the command payload length.
++ *
++ * Return: The number of bytes successfully transmitted or a negative error
++ * code on failure.
++ */
++ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
++				  const void *data, size_t len)
++{
++	struct mipi_dsi_msg msg = {
++		.channel = dsi->channel,
+ 		.tx_buf = data,
+ 		.tx_len = len
+ 	};
+ 
+-	if (!ops || !ops->transfer)
+-		return -ENOSYS;
+-
+ 	switch (len) {
+ 	case 0:
+ 		return -EINVAL;
++
+ 	case 1:
+ 		msg.type = MIPI_DSI_DCS_SHORT_WRITE;
+ 		break;
++
+ 	case 2:
+ 		msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+ 		break;
++
+ 	default:
+ 		msg.type = MIPI_DSI_DCS_LONG_WRITE;
+ 		break;
+ 	}
+ 
+-	return ops->transfer(dsi->host, &msg);
++	return mipi_dsi_device_transfer(dsi, &msg);
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_write_buffer);
++
++/**
++ * mipi_dsi_dcs_write() - send DCS write command
++ * @dsi: DSI peripheral device
++ * @cmd: DCS command
++ * @data: buffer containing the command payload
++ * @len: command payload length
++ *
++ * This function will automatically choose the right data type depending on
++ * the command payload length.
++ *
++ * Return: The number of bytes successfully transmitted or a negative error
++ * code on failure.
++ */
++ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
++			   const void *data, size_t len)
++{
++	ssize_t err;
++	size_t size;
++	u8 *tx;
++
++	if (len > 0) {
++		size = 1 + len;
++
++		tx = kmalloc(size, GFP_KERNEL);
++		if (!tx)
++			return -ENOMEM;
++
++		/* concatenate the DCS command byte and the payload */
++		tx[0] = cmd;
++		memcpy(&tx[1], data, len);
++	} else {
++		tx = &cmd;
++		size = 1;
++	}
++
++	err = mipi_dsi_dcs_write_buffer(dsi, tx, size);
++
++	if (len > 0)
++		kfree(tx);
++
++	return err;
+ }
+ EXPORT_SYMBOL(mipi_dsi_dcs_write);
+ 
+ /**
+- * mipi_dsi_dcs_read - send DCS read request command
+- * @dsi: DSI device
+- * @channel: virtual channel
+- * @cmd: DCS read command
+- * @data: pointer to read buffer
+- * @len: length of @data
++ * mipi_dsi_dcs_read() - send DCS read request command
++ * @dsi: DSI peripheral device
++ * @cmd: DCS command
++ * @data: buffer in which to receive data
++ * @len: size of receive buffer
+  *
+- * Function returns number of read bytes or error code.
++ * Return: The number of bytes read or a negative error code on failure.
+  */
+-ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, unsigned int channel,
+-			  u8 cmd, void *data, size_t len)
++ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
++			  size_t len)
+ {
+-	const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+ 	struct mipi_dsi_msg msg = {
+-		.channel = channel,
++		.channel = dsi->channel,
+ 		.type = MIPI_DSI_DCS_READ,
+ 		.tx_buf = &cmd,
+ 		.tx_len = 1,
+@@ -255,13 +585,283 @@
+ 		.rx_len = len
+ 	};
+ 
+-	if (!ops || !ops->transfer)
+-		return -ENOSYS;
+-
+-	return ops->transfer(dsi->host, &msg);
++	return mipi_dsi_device_transfer(dsi, &msg);
+ }
+ EXPORT_SYMBOL(mipi_dsi_dcs_read);
+ 
++/**
++ * mipi_dsi_dcs_nop() - send DCS nop packet
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_NOP, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_nop);
++
++/**
++ * mipi_dsi_dcs_soft_reset() - perform a software reset of the display module
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SOFT_RESET, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_soft_reset);
++
++/**
++ * mipi_dsi_dcs_get_power_mode() - query the display module's current power
++ *    mode
++ * @dsi: DSI peripheral device
++ * @mode: return location for the current power mode
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_POWER_MODE, mode,
++				sizeof(*mode));
++	if (err <= 0) {
++		if (err == 0)
++			err = -ENODATA;
++
++		return err;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_get_power_mode);
++
++/**
++ * mipi_dsi_dcs_get_pixel_format() - gets the pixel format for the RGB image
++ *    data used by the interface
++ * @dsi: DSI peripheral device
++ * @format: return location for the pixel format
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_PIXEL_FORMAT, format,
++				sizeof(*format));
++	if (err <= 0) {
++		if (err == 0)
++			err = -ENODATA;
++
++		return err;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_get_pixel_format);
++
++/**
++ * mipi_dsi_dcs_enter_sleep_mode() - disable all unnecessary blocks inside the
++ *    display module except interface communication
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_enter_sleep_mode);
++
++/**
++ * mipi_dsi_dcs_exit_sleep_mode() - enable all blocks inside the display
++ *    module
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_exit_sleep_mode);
++
++/**
++ * mipi_dsi_dcs_set_display_off() - stop displaying the image data on the
++ *    display device
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_set_display_off(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_display_off);
++
++/**
++ * mipi_dsi_dcs_set_display_on() - start displaying the image data on the
++ *    display device
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure
++ */
++int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_display_on);
++
++/**
++ * mipi_dsi_dcs_set_column_address() - define the column extent of the frame
++ *    memory accessed by the host processor
++ * @dsi: DSI peripheral device
++ * @start: first column of frame memory
++ * @end: last column of frame memory
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start,
++				    u16 end)
++{
++	u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff };
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, payload,
++				 sizeof(payload));
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_column_address);
++
++/**
++ * mipi_dsi_dcs_set_page_address() - define the page extent of the frame
++ *    memory accessed by the host processor
++ * @dsi: DSI peripheral device
++ * @start: first page of frame memory
++ * @end: last page of frame memory
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start,
++				  u16 end)
++{
++	u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff };
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PAGE_ADDRESS, payload,
++				 sizeof(payload));
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_page_address);
++
++/**
++ * mipi_dsi_dcs_set_tear_off() - turn off the display module's Tearing Effect
++ *    output signal on the TE signal line
++ * @dsi: DSI peripheral device
++ *
++ * Return: 0 on success or a negative error code on failure
++ */
++int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_OFF, NULL, 0);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_off);
++
++/**
++ * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect
++ *    output signal on the TE signal line.
++ * @dsi: DSI peripheral device
++ * @mode: the Tearing Effect Output Line mode
++ *
++ * Return: 0 on success or a negative error code on failure
++ */
++int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
++			     enum mipi_dsi_dcs_tear_mode mode)
++{
++	u8 value = mode;
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_ON, &value,
++				 sizeof(value));
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_on);
++
++/**
++ * mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image
++ *    data used by the interface
++ * @dsi: DSI peripheral device
++ * @format: pixel format
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format)
++{
++	ssize_t err;
++
++	err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PIXEL_FORMAT, &format,
++				 sizeof(format));
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++EXPORT_SYMBOL(mipi_dsi_dcs_set_pixel_format);
++
+ static int mipi_dsi_drv_probe(struct device *dev)
+ {
+ 	struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver);
+@@ -278,25 +878,43 @@
+ 	return drv->remove(dsi);
+ }
+ 
++static void mipi_dsi_drv_shutdown(struct device *dev)
++{
++	struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver);
++	struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
++
++	drv->shutdown(dsi);
++}
++
+ /**
+- * mipi_dsi_driver_register - register a driver for DSI devices
++ * mipi_dsi_driver_register_full() - register a driver for DSI devices
+  * @drv: DSI driver structure
++ * @owner: owner module
++ *
++ * Return: 0 on success or a negative error code on failure.
+  */
+-int mipi_dsi_driver_register(struct mipi_dsi_driver *drv)
++int mipi_dsi_driver_register_full(struct mipi_dsi_driver *drv,
++				  struct module *owner)
+ {
+ 	drv->driver.bus = &mipi_dsi_bus_type;
++	drv->driver.owner = owner;
++
+ 	if (drv->probe)
+ 		drv->driver.probe = mipi_dsi_drv_probe;
+ 	if (drv->remove)
+ 		drv->driver.remove = mipi_dsi_drv_remove;
++	if (drv->shutdown)
++		drv->driver.shutdown = mipi_dsi_drv_shutdown;
+ 
+ 	return driver_register(&drv->driver);
+ }
+-EXPORT_SYMBOL(mipi_dsi_driver_register);
++EXPORT_SYMBOL(mipi_dsi_driver_register_full);
+ 
+ /**
+- * mipi_dsi_driver_unregister - unregister a driver for DSI devices
++ * mipi_dsi_driver_unregister() - unregister a driver for DSI devices
+  * @drv: DSI driver structure
++ *
++ * Return: 0 on success or a negative error code on failure.
+  */
+ void mipi_dsi_driver_unregister(struct mipi_dsi_driver *drv)
+ {
+diff -Naur a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
+--- a/drivers/gpu/drm/drm_mm.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_mm.c	2015-03-26 14:42:38.730435422 +0530
+@@ -47,7 +47,48 @@
+ #include <linux/seq_file.h>
+ #include <linux/export.h>
+ 
+-#define MM_UNUSED_TARGET 4
++/**
++ * DOC: Overview
++ *
++ * drm_mm provides a simple range allocator. The drivers are free to use the
++ * resource allocator from the linux core if it suits them, the upside of drm_mm
++ * is that it's in the DRM core. Which means that it's easier to extend for
++ * some of the crazier special purpose needs of gpus.
++ *
++ * The main data struct is &drm_mm, allocations are tracked in &drm_mm_node.
++ * Drivers are free to embed either of them into their own suitable
++ * datastructures. drm_mm itself will not do any allocations of its own, so if
++ * drivers choose not to embed nodes they need to still allocate them
++ * themselves.
++ *
++ * The range allocator also supports reservation of preallocated blocks. This is
++ * useful for taking over initial mode setting configurations from the firmware,
++ * where an object needs to be created which exactly matches the firmware's
++ * scanout target. As long as the range is still free it can be inserted anytime
++ * after the allocator is initialized, which helps with avoiding looped
++ * depencies in the driver load sequence.
++ *
++ * drm_mm maintains a stack of most recently freed holes, which of all
++ * simplistic datastructures seems to be a fairly decent approach to clustering
++ * allocations and avoiding too much fragmentation. This means free space
++ * searches are O(num_holes). Given that all the fancy features drm_mm supports
++ * something better would be fairly complex and since gfx thrashing is a fairly
++ * steep cliff not a real concern. Removing a node again is O(1).
++ *
++ * drm_mm supports a few features: Alignment and range restrictions can be
++ * supplied. Further more every &drm_mm_node has a color value (which is just an
++ * opaqua unsigned long) which in conjunction with a driver callback can be used
++ * to implement sophisticated placement restrictions. The i915 DRM driver uses
++ * this to implement guard pages between incompatible caching domains in the
++ * graphics TT.
++ *
++ * Two behaviors are supported for searching and allocating: bottom-up and top-down.
++ * The default is bottom-up. Top-down allocation can be used if the memory area
++ * has different restrictions, or just to reduce fragmentation.
++ *
++ * Finally iteration helpers to walk all nodes and all holes are provided as are
++ * some basic allocator dumpers for debugging.
++ */
+ 
+ static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm,
+ 						unsigned long size,
+@@ -65,7 +106,8 @@
+ static void drm_mm_insert_helper(struct drm_mm_node *hole_node,
+ 				 struct drm_mm_node *node,
+ 				 unsigned long size, unsigned alignment,
+-				 unsigned long color)
++				 unsigned long color,
++				 enum drm_mm_allocator_flags flags)
+ {
+ 	struct drm_mm *mm = hole_node->mm;
+ 	unsigned long hole_start = drm_mm_hole_node_start(hole_node);
+@@ -78,12 +120,22 @@
+ 	if (mm->color_adjust)
+ 		mm->color_adjust(hole_node, color, &adj_start, &adj_end);
+ 
++	if (flags & DRM_MM_CREATE_TOP)
++		adj_start = adj_end - size;
++
+ 	if (alignment) {
+ 		unsigned tmp = adj_start % alignment;
+-		if (tmp)
+-			adj_start += alignment - tmp;
++		if (tmp) {
++			if (flags & DRM_MM_CREATE_TOP)
++				adj_start -= tmp;
++			else
++				adj_start += alignment - tmp;
++		}
+ 	}
+ 
++	BUG_ON(adj_start < hole_start);
++	BUG_ON(adj_end > hole_end);
++
+ 	if (adj_start == hole_start) {
+ 		hole_node->hole_follows = 0;
+ 		list_del(&hole_node->hole_stack);
+@@ -107,6 +159,20 @@
+ 	}
+ }
+ 
++/**
++ * drm_mm_reserve_node - insert an pre-initialized node
++ * @mm: drm_mm allocator to insert @node into
++ * @node: drm_mm_node to insert
++ *
++ * This functions inserts an already set-up drm_mm_node into the allocator,
++ * meaning that start, size and color must be set by the caller. This is useful
++ * to initialize the allocator with preallocated objects which must be set-up
++ * before the range allocator can be set-up, e.g. when taking over a firmware
++ * framebuffer.
++ *
++ * Returns:
++ * 0 on success, -ENOSPC if there's no hole where @node is.
++ */
+ int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node)
+ {
+ 	struct drm_mm_node *hole;
+@@ -141,30 +207,39 @@
+ 		return 0;
+ 	}
+ 
+-	WARN(1, "no hole found for node 0x%lx + 0x%lx\n",
+-	     node->start, node->size);
+ 	return -ENOSPC;
+ }
+ EXPORT_SYMBOL(drm_mm_reserve_node);
+ 
+ /**
+- * Search for free space and insert a preallocated memory node. Returns
+- * -ENOSPC if no suitable free area is available. The preallocated memory node
+- * must be cleared.
++ * drm_mm_insert_node_generic - search for space and insert @node
++ * @mm: drm_mm to allocate from
++ * @node: preallocate node to insert
++ * @size: size of the allocation
++ * @alignment: alignment of the allocation
++ * @color: opaque tag value to use for this node
++ * @sflags: flags to fine-tune the allocation search
++ * @aflags: flags to fine-tune the allocation behavior
++ *
++ * The preallocated node must be cleared to 0.
++ *
++ * Returns:
++ * 0 on success, -ENOSPC if there's no suitable hole.
+  */
+ int drm_mm_insert_node_generic(struct drm_mm *mm, struct drm_mm_node *node,
+ 			       unsigned long size, unsigned alignment,
+ 			       unsigned long color,
+-			       enum drm_mm_search_flags flags)
++			       enum drm_mm_search_flags sflags,
++			       enum drm_mm_allocator_flags aflags)
+ {
+ 	struct drm_mm_node *hole_node;
+ 
+ 	hole_node = drm_mm_search_free_generic(mm, size, alignment,
+-					       color, flags);
++					       color, sflags);
+ 	if (!hole_node)
+ 		return -ENOSPC;
+ 
+-	drm_mm_insert_helper(hole_node, node, size, alignment, color);
++	drm_mm_insert_helper(hole_node, node, size, alignment, color, aflags);
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_mm_insert_node_generic);
+@@ -173,7 +248,8 @@
+ 				       struct drm_mm_node *node,
+ 				       unsigned long size, unsigned alignment,
+ 				       unsigned long color,
+-				       unsigned long start, unsigned long end)
++				       unsigned long start, unsigned long end,
++				       enum drm_mm_allocator_flags flags)
+ {
+ 	struct drm_mm *mm = hole_node->mm;
+ 	unsigned long hole_start = drm_mm_hole_node_start(hole_node);
+@@ -188,13 +264,20 @@
+ 	if (adj_end > end)
+ 		adj_end = end;
+ 
++	if (flags & DRM_MM_CREATE_TOP)
++		adj_start = adj_end - size;
++
+ 	if (mm->color_adjust)
+ 		mm->color_adjust(hole_node, color, &adj_start, &adj_end);
+ 
+ 	if (alignment) {
+ 		unsigned tmp = adj_start % alignment;
+-		if (tmp)
+-			adj_start += alignment - tmp;
++		if (tmp) {
++			if (flags & DRM_MM_CREATE_TOP)
++				adj_start -= tmp;
++			else
++				adj_start += alignment - tmp;
++		}
+ 	}
+ 
+ 	if (adj_start == hole_start) {
+@@ -211,6 +294,8 @@
+ 	INIT_LIST_HEAD(&node->hole_stack);
+ 	list_add(&node->node_list, &hole_node->node_list);
+ 
++	BUG_ON(node->start < start);
++	BUG_ON(node->start < adj_start);
+ 	BUG_ON(node->start + node->size > adj_end);
+ 	BUG_ON(node->start + node->size > end);
+ 
+@@ -222,32 +307,51 @@
+ }
+ 
+ /**
+- * Search for free space and insert a preallocated memory node. Returns
+- * -ENOSPC if no suitable free area is available. This is for range
+- * restricted allocations. The preallocated memory node must be cleared.
++ * drm_mm_insert_node_in_range_generic - ranged search for space and insert @node
++ * @mm: drm_mm to allocate from
++ * @node: preallocate node to insert
++ * @size: size of the allocation
++ * @alignment: alignment of the allocation
++ * @color: opaque tag value to use for this node
++ * @start: start of the allowed range for this node
++ * @end: end of the allowed range for this node
++ * @sflags: flags to fine-tune the allocation search
++ * @aflags: flags to fine-tune the allocation behavior
++ *
++ * The preallocated node must be cleared to 0.
++ *
++ * Returns:
++ * 0 on success, -ENOSPC if there's no suitable hole.
+  */
+ int drm_mm_insert_node_in_range_generic(struct drm_mm *mm, struct drm_mm_node *node,
+-					unsigned long size, unsigned alignment, unsigned long color,
++					unsigned long size, unsigned alignment,
++					unsigned long color,
+ 					unsigned long start, unsigned long end,
+-					enum drm_mm_search_flags flags)
++					enum drm_mm_search_flags sflags,
++					enum drm_mm_allocator_flags aflags)
+ {
+ 	struct drm_mm_node *hole_node;
+ 
+ 	hole_node = drm_mm_search_free_in_range_generic(mm,
+ 							size, alignment, color,
+-							start, end, flags);
++							start, end, sflags);
+ 	if (!hole_node)
+ 		return -ENOSPC;
+ 
+ 	drm_mm_insert_helper_range(hole_node, node,
+ 				   size, alignment, color,
+-				   start, end);
++				   start, end, aflags);
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_mm_insert_node_in_range_generic);
+ 
+ /**
+- * Remove a memory node from the allocator.
++ * drm_mm_remove_node - Remove a memory node from the allocator.
++ * @node: drm_mm_node to remove
++ *
++ * This just removes a node from its drm_mm allocator. The node does not need to
++ * be cleared again before it can be re-inserted into this or any other drm_mm
++ * allocator. It is a bug to call this function on a un-allocated node.
+  */
+ void drm_mm_remove_node(struct drm_mm_node *node)
+ {
+@@ -315,7 +419,10 @@
+ 	best = NULL;
+ 	best_size = ~0UL;
+ 
+-	drm_mm_for_each_hole(entry, mm, adj_start, adj_end) {
++	__drm_mm_for_each_hole(entry, mm, adj_start, adj_end,
++			       flags & DRM_MM_SEARCH_BELOW) {
++		unsigned long hole_size = adj_end - adj_start;
++
+ 		if (mm->color_adjust) {
+ 			mm->color_adjust(entry, color, &adj_start, &adj_end);
+ 			if (adj_end <= adj_start)
+@@ -328,9 +435,9 @@
+ 		if (!(flags & DRM_MM_SEARCH_BEST))
+ 			return entry;
+ 
+-		if (entry->size < best_size) {
++		if (hole_size < best_size) {
+ 			best = entry;
+-			best_size = entry->size;
++			best_size = hole_size;
+ 		}
+ 	}
+ 
+@@ -356,7 +463,10 @@
+ 	best = NULL;
+ 	best_size = ~0UL;
+ 
+-	drm_mm_for_each_hole(entry, mm, adj_start, adj_end) {
++	__drm_mm_for_each_hole(entry, mm, adj_start, adj_end,
++			       flags & DRM_MM_SEARCH_BELOW) {
++		unsigned long hole_size = adj_end - adj_start;
++
+ 		if (adj_start < start)
+ 			adj_start = start;
+ 		if (adj_end > end)
+@@ -374,9 +484,9 @@
+ 		if (!(flags & DRM_MM_SEARCH_BEST))
+ 			return entry;
+ 
+-		if (entry->size < best_size) {
++		if (hole_size < best_size) {
+ 			best = entry;
+-			best_size = entry->size;
++			best_size = hole_size;
+ 		}
+ 	}
+ 
+@@ -384,7 +494,13 @@
+ }
+ 
+ /**
+- * Moves an allocation. To be used with embedded struct drm_mm_node.
++ * drm_mm_replace_node - move an allocation from @old to @new
++ * @old: drm_mm_node to remove from the allocator
++ * @new: drm_mm_node which should inherit @old's allocation
++ *
++ * This is useful for when drivers embed the drm_mm_node structure and hence
++ * can't move allocations by reassigning pointers. It's a combination of remove
++ * and insert with the guarantee that the allocation start will match.
+  */
+ void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new)
+ {
+@@ -402,12 +518,46 @@
+ EXPORT_SYMBOL(drm_mm_replace_node);
+ 
+ /**
+- * Initializa lru scanning.
++ * DOC: lru scan roaster
++ *
++ * Very often GPUs need to have continuous allocations for a given object. When
++ * evicting objects to make space for a new one it is therefore not most
++ * efficient when we simply start to select all objects from the tail of an LRU
++ * until there's a suitable hole: Especially for big objects or nodes that
++ * otherwise have special allocation constraints there's a good chance we evict
++ * lots of (smaller) objects unecessarily.
++ *
++ * The DRM range allocator supports this use-case through the scanning
++ * interfaces. First a scan operation needs to be initialized with
++ * drm_mm_init_scan() or drm_mm_init_scan_with_range(). The the driver adds
++ * objects to the roaster (probably by walking an LRU list, but this can be
++ * freely implemented) until a suitable hole is found or there's no further
++ * evitable object.
++ *
++ * The the driver must walk through all objects again in exactly the reverse
++ * order to restore the allocator state. Note that while the allocator is used
++ * in the scan mode no other operation is allowed.
++ *
++ * Finally the driver evicts all objects selected in the scan. Adding and
++ * removing an object is O(1), and since freeing a node is also O(1) the overall
++ * complexity is O(scanned_objects). So like the free stack which needs to be
++ * walked before a scan operation even begins this is linear in the number of
++ * objects. It doesn't seem to hurt badly.
++ */
++
++/**
++ * drm_mm_init_scan - initialize lru scanning
++ * @mm: drm_mm to scan
++ * @size: size of the allocation
++ * @alignment: alignment of the allocation
++ * @color: opaque tag value to use for the allocation
+  *
+  * This simply sets up the scanning routines with the parameters for the desired
+- * hole.
++ * hole. Note that there's no need to specify allocation flags, since they only
++ * change the place a node is allocated from within a suitable hole.
+  *
+- * Warning: As long as the scan list is non-empty, no other operations than
++ * Warning:
++ * As long as the scan list is non-empty, no other operations than
+  * adding/removing nodes to/from the scan list are allowed.
+  */
+ void drm_mm_init_scan(struct drm_mm *mm,
+@@ -427,12 +577,20 @@
+ EXPORT_SYMBOL(drm_mm_init_scan);
+ 
+ /**
+- * Initializa lru scanning.
++ * drm_mm_init_scan - initialize range-restricted lru scanning
++ * @mm: drm_mm to scan
++ * @size: size of the allocation
++ * @alignment: alignment of the allocation
++ * @color: opaque tag value to use for the allocation
++ * @start: start of the allowed range for the allocation
++ * @end: end of the allowed range for the allocation
+  *
+  * This simply sets up the scanning routines with the parameters for the desired
+- * hole. This version is for range-restricted scans.
++ * hole. Note that there's no need to specify allocation flags, since they only
++ * change the place a node is allocated from within a suitable hole.
+  *
+- * Warning: As long as the scan list is non-empty, no other operations than
++ * Warning:
++ * As long as the scan list is non-empty, no other operations than
+  * adding/removing nodes to/from the scan list are allowed.
+  */
+ void drm_mm_init_scan_with_range(struct drm_mm *mm,
+@@ -456,12 +614,16 @@
+ EXPORT_SYMBOL(drm_mm_init_scan_with_range);
+ 
+ /**
++ * drm_mm_scan_add_block - add a node to the scan list
++ * @node: drm_mm_node to add
++ *
+  * Add a node to the scan list that might be freed to make space for the desired
+  * hole.
+  *
+- * Returns non-zero, if a hole has been found, zero otherwise.
++ * Returns:
++ * True if a hole has been found, false otherwise.
+  */
+-int drm_mm_scan_add_block(struct drm_mm_node *node)
++bool drm_mm_scan_add_block(struct drm_mm_node *node)
+ {
+ 	struct drm_mm *mm = node->mm;
+ 	struct drm_mm_node *prev_node;
+@@ -501,15 +663,16 @@
+ 			    mm->scan_size, mm->scan_alignment)) {
+ 		mm->scan_hit_start = hole_start;
+ 		mm->scan_hit_end = hole_end;
+-		return 1;
++		return true;
+ 	}
+ 
+-	return 0;
++	return false;
+ }
+ EXPORT_SYMBOL(drm_mm_scan_add_block);
+ 
+ /**
+- * Remove a node from the scan list.
++ * drm_mm_scan_remove_block - remove a node from the scan list
++ * @node: drm_mm_node to remove
+  *
+  * Nodes _must_ be removed in the exact same order from the scan list as they
+  * have been added, otherwise the internal state of the memory manager will be
+@@ -519,10 +682,11 @@
+  * immediately following drm_mm_search_free with !DRM_MM_SEARCH_BEST will then
+  * return the just freed block (because its at the top of the free_stack list).
+  *
+- * Returns one if this block should be evicted, zero otherwise. Will always
+- * return zero when no hole has been found.
++ * Returns:
++ * True if this block should be evicted, false otherwise. Will always
++ * return false when no hole has been found.
+  */
+-int drm_mm_scan_remove_block(struct drm_mm_node *node)
++bool drm_mm_scan_remove_block(struct drm_mm_node *node)
+ {
+ 	struct drm_mm *mm = node->mm;
+ 	struct drm_mm_node *prev_node;
+@@ -543,7 +707,15 @@
+ }
+ EXPORT_SYMBOL(drm_mm_scan_remove_block);
+ 
+-int drm_mm_clean(struct drm_mm * mm)
++/**
++ * drm_mm_clean - checks whether an allocator is clean
++ * @mm: drm_mm allocator to check
++ *
++ * Returns:
++ * True if the allocator is completely free, false if there's still a node
++ * allocated in it.
++ */
++bool drm_mm_clean(struct drm_mm * mm)
+ {
+ 	struct list_head *head = &mm->head_node.node_list;
+ 
+@@ -551,6 +723,14 @@
+ }
+ EXPORT_SYMBOL(drm_mm_clean);
+ 
++/**
++ * drm_mm_init - initialize a drm-mm allocator
++ * @mm: the drm_mm structure to initialize
++ * @start: start of the range managed by @mm
++ * @size: end of the range managed by @mm
++ *
++ * Note that @mm must be cleared to 0 before calling this function.
++ */
+ void drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size)
+ {
+ 	INIT_LIST_HEAD(&mm->hole_stack);
+@@ -572,6 +752,13 @@
+ }
+ EXPORT_SYMBOL(drm_mm_init);
+ 
++/**
++ * drm_mm_takedown - clean up a drm_mm allocator
++ * @mm: drm_mm allocator to clean up
++ *
++ * Note that it is a bug to call this function on an allocator which is not
++ * clean.
++ */
+ void drm_mm_takedown(struct drm_mm * mm)
+ {
+ 	WARN(!list_empty(&mm->head_node.node_list),
+@@ -597,6 +784,11 @@
+ 	return 0;
+ }
+ 
++/**
++ * drm_mm_debug_table - dump allocator state to dmesg
++ * @mm: drm_mm allocator to dump
++ * @prefix: prefix to use for dumping to dmesg
++ */
+ void drm_mm_debug_table(struct drm_mm *mm, const char *prefix)
+ {
+ 	struct drm_mm_node *entry;
+@@ -635,6 +827,11 @@
+ 	return 0;
+ }
+ 
++/**
++ * drm_mm_dump_table - dump allocator state to a seq_file
++ * @m: seq_file to dump to
++ * @mm: drm_mm allocator to dump
++ */
+ int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm)
+ {
+ 	struct drm_mm_node *entry;
+diff -Naur a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
+--- a/drivers/gpu/drm/drm_modes.c	2015-03-26 14:43:30.410436435 +0530
++++ b/drivers/gpu/drm/drm_modes.c	2015-03-26 14:42:38.734435422 +0530
+@@ -37,15 +37,14 @@
+ #include <drm/drm_crtc.h>
+ #include <video/of_videomode.h>
+ #include <video/videomode.h>
++#include <drm/drm_modes.h>
++
++#include "drm_crtc_internal.h"
+ 
+ /**
+- * drm_mode_debug_printmodeline - debug print a mode
+- * @dev: DRM device
++ * drm_mode_debug_printmodeline - print a mode to dmesg
+  * @mode: mode to print
+  *
+- * LOCKING:
+- * None.
+- *
+  * Describe @mode using DRM_DEBUG.
+  */
+ void drm_mode_debug_printmodeline(const struct drm_display_mode *mode)
+@@ -61,18 +60,77 @@
+ EXPORT_SYMBOL(drm_mode_debug_printmodeline);
+ 
+ /**
+- * drm_cvt_mode -create a modeline based on CVT algorithm
++ * drm_mode_create - create a new display mode
+  * @dev: DRM device
+- * @hdisplay: hdisplay size
+- * @vdisplay: vdisplay size
+- * @vrefresh  : vrefresh rate
+- * @reduced : Whether the GTF calculation is simplified
+- * @interlaced:Whether the interlace is supported
+  *
+- * LOCKING:
+- * none.
++ * Create a new, cleared drm_display_mode with kzalloc, allocate an ID for it
++ * and return it.
++ *
++ * Returns:
++ * Pointer to new mode on success, NULL on error.
++ */
++struct drm_display_mode *drm_mode_create(struct drm_device *dev)
++{
++	struct drm_display_mode *nmode;
++
++	nmode = kzalloc(sizeof(struct drm_display_mode), GFP_KERNEL);
++	if (!nmode)
++		return NULL;
++
++	if (drm_mode_object_get(dev, &nmode->base, DRM_MODE_OBJECT_MODE)) {
++		kfree(nmode);
++		return NULL;
++	}
++
++	return nmode;
++}
++EXPORT_SYMBOL(drm_mode_create);
++
++/**
++ * drm_mode_destroy - remove a mode
++ * @dev: DRM device
++ * @mode: mode to remove
++ *
++ * Release @mode's unique ID, then free it @mode structure itself using kfree.
++ */
++void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode)
++{
++	if (!mode)
++		return;
++
++	drm_mode_object_put(dev, &mode->base);
++
++	kfree(mode);
++}
++EXPORT_SYMBOL(drm_mode_destroy);
++
++/**
++ * drm_mode_probed_add - add a mode to a connector's probed_mode list
++ * @connector: connector the new mode
++ * @mode: mode data
+  *
+- * return the modeline based on CVT algorithm
++ * Add @mode to @connector's probed_mode list for later use. This list should
++ * then in a second step get filtered and all the modes actually supported by
++ * the hardware moved to the @connector's modes list.
++ */
++void drm_mode_probed_add(struct drm_connector *connector,
++			 struct drm_display_mode *mode)
++{
++	WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex));
++
++	list_add_tail(&mode->head, &connector->probed_modes);
++}
++EXPORT_SYMBOL(drm_mode_probed_add);
++
++/**
++ * drm_cvt_mode -create a modeline based on the CVT algorithm
++ * @dev: drm device
++ * @hdisplay: hdisplay size
++ * @vdisplay: vdisplay size
++ * @vrefresh: vrefresh rate
++ * @reduced: whether to use reduced blanking
++ * @interlaced: whether to compute an interlaced mode
++ * @margins: whether to add margins (borders)
+  *
+  * This function is called to generate the modeline based on CVT algorithm
+  * according to the hdisplay, vdisplay, vrefresh.
+@@ -82,12 +140,17 @@
+  *
+  * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
+  * What I have done is to translate it by using integer calculation.
++ *
++ * Returns:
++ * The modeline based on the CVT algorithm stored in a drm_display_mode object.
++ * The display mode object is allocated with drm_mode_create(). Returns NULL
++ * when no mode could be allocated.
+  */
+-#define HV_FACTOR			1000
+ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
+ 				      int vdisplay, int vrefresh,
+ 				      bool reduced, bool interlaced, bool margins)
+ {
++#define HV_FACTOR			1000
+ 	/* 1) top/bottom margin size (% of height) - default: 1.8, */
+ #define	CVT_MARGIN_PERCENTAGE		18
+ 	/* 2) character cell horizontal granularity (pixels) - default 8 */
+@@ -281,23 +344,25 @@
+ EXPORT_SYMBOL(drm_cvt_mode);
+ 
+ /**
+- * drm_gtf_mode_complex - create the modeline based on full GTF algorithm
+- *
+- * @dev		:drm device
+- * @hdisplay	:hdisplay size
+- * @vdisplay	:vdisplay size
+- * @vrefresh	:vrefresh rate.
+- * @interlaced	:whether the interlace is supported
+- * @margins	:desired margin size
+- * @GTF_[MCKJ]  :extended GTF formula parameters
+- *
+- * LOCKING.
+- * none.
+- *
+- * return the modeline based on full GTF algorithm.
++ * drm_gtf_mode_complex - create the modeline based on the full GTF algorithm
++ * @dev: drm device
++ * @hdisplay: hdisplay size
++ * @vdisplay: vdisplay size
++ * @vrefresh: vrefresh rate.
++ * @interlaced: whether to compute an interlaced mode
++ * @margins: desired margin (borders) size
++ * @GTF_M: extended GTF formula parameters
++ * @GTF_2C: extended GTF formula parameters
++ * @GTF_K: extended GTF formula parameters
++ * @GTF_2J: extended GTF formula parameters
+  *
+  * GTF feature blocks specify C and J in multiples of 0.5, so we pass them
+  * in here multiplied by two.  For a C of 40, pass in 80.
++ *
++ * Returns:
++ * The modeline based on the full GTF algorithm stored in a drm_display_mode object.
++ * The display mode object is allocated with drm_mode_create(). Returns NULL
++ * when no mode could be allocated.
+  */
+ struct drm_display_mode *
+ drm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay,
+@@ -467,17 +532,13 @@
+ EXPORT_SYMBOL(drm_gtf_mode_complex);
+ 
+ /**
+- * drm_gtf_mode - create the modeline based on GTF algorithm
+- *
+- * @dev		:drm device
+- * @hdisplay	:hdisplay size
+- * @vdisplay	:vdisplay size
+- * @vrefresh	:vrefresh rate.
+- * @interlaced	:whether the interlace is supported
+- * @margins	:whether the margin is supported
+- *
+- * LOCKING.
+- * none.
++ * drm_gtf_mode - create the modeline based on the GTF algorithm
++ * @dev: drm device
++ * @hdisplay: hdisplay size
++ * @vdisplay: vdisplay size
++ * @vrefresh: vrefresh rate.
++ * @interlaced: whether to compute an interlaced mode
++ * @margins: desired margin (borders) size
+  *
+  * return the modeline based on GTF algorithm
+  *
+@@ -496,19 +557,32 @@
+  * C = 40
+  * K = 128
+  * J = 20
++ *
++ * Returns:
++ * The modeline based on the GTF algorithm stored in a drm_display_mode object.
++ * The display mode object is allocated with drm_mode_create(). Returns NULL
++ * when no mode could be allocated.
+  */
+ struct drm_display_mode *
+ drm_gtf_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh,
+-	     bool lace, int margins)
++	     bool interlaced, int margins)
+ {
+-	return drm_gtf_mode_complex(dev, hdisplay, vdisplay, vrefresh, lace,
+-				    margins, 600, 40 * 2, 128, 20 * 2);
++	return drm_gtf_mode_complex(dev, hdisplay, vdisplay, vrefresh,
++				    interlaced, margins,
++				    600, 40 * 2, 128, 20 * 2);
+ }
+ EXPORT_SYMBOL(drm_gtf_mode);
+ 
+ #ifdef CONFIG_VIDEOMODE_HELPERS
+-int drm_display_mode_from_videomode(const struct videomode *vm,
+-				    struct drm_display_mode *dmode)
++/**
++ * drm_display_mode_from_videomode - fill in @dmode using @vm,
++ * @vm: videomode structure to use as source
++ * @dmode: drm_display_mode structure to use as destination
++ *
++ * Fills out @dmode using the display mode specified in @vm.
++ */
++void drm_display_mode_from_videomode(const struct videomode *vm,
++				     struct drm_display_mode *dmode)
+ {
+ 	dmode->hdisplay = vm->hactive;
+ 	dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
+@@ -538,8 +612,6 @@
+ 	if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
+ 		dmode->flags |= DRM_MODE_FLAG_DBLCLK;
+ 	drm_mode_set_name(dmode);
+-
+-	return 0;
+ }
+ EXPORT_SYMBOL_GPL(drm_display_mode_from_videomode);
+ 
+@@ -553,6 +625,9 @@
+  * This function is expensive and should only be used, if only one mode is to be
+  * read from DT. To get multiple modes start with of_get_display_timings and
+  * work with that instead.
++ *
++ * Returns:
++ * 0 on success, a negative errno code when no of videomode node was found.
+  */
+ int of_get_drm_display_mode(struct device_node *np,
+ 			    struct drm_display_mode *dmode, int index)
+@@ -580,10 +655,8 @@
+  * drm_mode_set_name - set the name on a mode
+  * @mode: name will be set in this mode
+  *
+- * LOCKING:
+- * None.
+- *
+- * Set the name of @mode to a standard format.
++ * Set the name of @mode to a standard format which is <hdisplay>x<vdisplay>
++ * with an optional 'i' suffix for interlaced modes.
+  */
+ void drm_mode_set_name(struct drm_display_mode *mode)
+ {
+@@ -595,54 +668,12 @@
+ }
+ EXPORT_SYMBOL(drm_mode_set_name);
+ 
+-/**
+- * drm_mode_width - get the width of a mode
+- * @mode: mode
+- *
+- * LOCKING:
+- * None.
+- *
+- * Return @mode's width (hdisplay) value.
+- *
+- * FIXME: is this needed?
+- *
+- * RETURNS:
+- * @mode->hdisplay
+- */
+-int drm_mode_width(const struct drm_display_mode *mode)
+-{
+-	return mode->hdisplay;
+-
+-}
+-EXPORT_SYMBOL(drm_mode_width);
+-
+-/**
+- * drm_mode_height - get the height of a mode
+- * @mode: mode
+- *
+- * LOCKING:
+- * None.
+- *
+- * Return @mode's height (vdisplay) value.
+- *
+- * FIXME: is this needed?
+- *
+- * RETURNS:
+- * @mode->vdisplay
+- */
+-int drm_mode_height(const struct drm_display_mode *mode)
+-{
+-	return mode->vdisplay;
+-}
+-EXPORT_SYMBOL(drm_mode_height);
+-
+ /** drm_mode_hsync - get the hsync of a mode
+  * @mode: mode
+  *
+- * LOCKING:
+- * None.
+- *
+- * Return @modes's hsync rate in kHz, rounded to the nearest int.
++ * Returns:
++ * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the
++ * value first if it is not yet set.
+  */
+ int drm_mode_hsync(const struct drm_display_mode *mode)
+ {
+@@ -666,17 +697,9 @@
+  * drm_mode_vrefresh - get the vrefresh of a mode
+  * @mode: mode
+  *
+- * LOCKING:
+- * None.
+- *
+- * Return @mode's vrefresh rate in Hz or calculate it if necessary.
+- *
+- * FIXME: why is this needed?  shouldn't vrefresh be set already?
+- *
+- * RETURNS:
+- * Vertical refresh rate. It will be the result of actual value plus 0.5.
+- * If it is 70.288, it will return 70Hz.
+- * If it is 59.6, it will return 60Hz.
++ * Returns:
++ * @modes's vrefresh rate in Hz, rounded to the nearest integer. Calculates the
++ * value first if it is not yet set.
+  */
+ int drm_mode_vrefresh(const struct drm_display_mode *mode)
+ {
+@@ -705,14 +728,11 @@
+ EXPORT_SYMBOL(drm_mode_vrefresh);
+ 
+ /**
+- * drm_mode_set_crtcinfo - set CRTC modesetting parameters
++ * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
+  * @p: mode
+  * @adjust_flags: a combination of adjustment flags
+  *
+- * LOCKING:
+- * None.
+- *
+- * Setup the CRTC modesetting parameters for @p, adjusting if necessary.
++ * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
+  *
+  * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
+  *   interlaced modes.
+@@ -780,15 +800,11 @@
+ }
+ EXPORT_SYMBOL(drm_mode_set_crtcinfo);
+ 
+-
+ /**
+  * drm_mode_copy - copy the mode
+  * @dst: mode to overwrite
+  * @src: mode to copy
+  *
+- * LOCKING:
+- * None.
+- *
+  * Copy an existing mode into another mode, preserving the object id and
+  * list head of the destination mode.
+  */
+@@ -805,13 +821,14 @@
+ 
+ /**
+  * drm_mode_duplicate - allocate and duplicate an existing mode
+- * @m: mode to duplicate
+- *
+- * LOCKING:
+- * None.
++ * @dev: drm_device to allocate the duplicated mode for
++ * @mode: mode to duplicate
+  *
+  * Just allocate a new mode, copy the existing mode into it, and return
+  * a pointer to it.  Used to create new instances of established modes.
++ *
++ * Returns:
++ * Pointer to duplicated mode on success, NULL on error.
+  */
+ struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
+ 					    const struct drm_display_mode *mode)
+@@ -833,12 +850,9 @@
+  * @mode1: first mode
+  * @mode2: second mode
+  *
+- * LOCKING:
+- * None.
+- *
+  * Check to see if @mode1 and @mode2 are equivalent.
+  *
+- * RETURNS:
++ * Returns:
+  * True if the modes are equal, false otherwise.
+  */
+ bool drm_mode_equal(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
+@@ -864,13 +878,10 @@
+  * @mode1: first mode
+  * @mode2: second mode
+  *
+- * LOCKING:
+- * None.
+- *
+  * Check to see if @mode1 and @mode2 are equivalent, but
+  * don't check the pixel clocks nor the stereo layout.
+  *
+- * RETURNS:
++ * Returns:
+  * True if the modes are equal, false otherwise.
+  */
+ bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
+@@ -900,25 +911,19 @@
+  * @mode_list: list of modes to check
+  * @maxX: maximum width
+  * @maxY: maximum height
+- * @maxPitch: max pitch
+- *
+- * LOCKING:
+- * Caller must hold a lock protecting @mode_list.
+  *
+- * The DRM device (@dev) has size and pitch limits.  Here we validate the
+- * modes we probed for @dev against those limits and set their status as
+- * necessary.
++ * This function is a helper which can be used to validate modes against size
++ * limitations of the DRM device/connector. If a mode is too big its status
++ * member is updated with the appropriate validation failure code. The list
++ * itself is not changed.
+  */
+ void drm_mode_validate_size(struct drm_device *dev,
+ 			    struct list_head *mode_list,
+-			    int maxX, int maxY, int maxPitch)
++			    int maxX, int maxY)
+ {
+ 	struct drm_display_mode *mode;
+ 
+ 	list_for_each_entry(mode, mode_list, head) {
+-		if (maxPitch > 0 && mode->hdisplay > maxPitch)
+-			mode->status = MODE_BAD_WIDTH;
+-
+ 		if (maxX > 0 && mode->hdisplay > maxX)
+ 			mode->status = MODE_VIRTUAL_X;
+ 
+@@ -934,12 +939,10 @@
+  * @mode_list: list of modes to check
+  * @verbose: be verbose about it
+  *
+- * LOCKING:
+- * Caller must hold a lock protecting @mode_list.
+- *
+- * Once mode list generation is complete, a caller can use this routine to
+- * remove invalid modes from a mode list.  If any of the modes have a
+- * status other than %MODE_OK, they are removed from @mode_list and freed.
++ * This helper function can be used to prune a display mode list after
++ * validation has been completed. All modes who's status is not MODE_OK will be
++ * removed from the list, and if @verbose the status code and mode name is also
++ * printed to dmesg.
+  */
+ void drm_mode_prune_invalid(struct drm_device *dev,
+ 			    struct list_head *mode_list, bool verbose)
+@@ -966,13 +969,10 @@
+  * @lh_a: list_head for first mode
+  * @lh_b: list_head for second mode
+  *
+- * LOCKING:
+- * None.
+- *
+  * Compare two modes, given by @lh_a and @lh_b, returning a value indicating
+  * which is better.
+  *
+- * RETURNS:
++ * Returns:
+  * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
+  * positive if @lh_b is better than @lh_a.
+  */
+@@ -1000,12 +1000,9 @@
+ 
+ /**
+  * drm_mode_sort - sort mode list
+- * @mode_list: list to sort
+- *
+- * LOCKING:
+- * Caller must hold a lock protecting @mode_list.
++ * @mode_list: list of drm_display_mode structures to sort
+  *
+- * Sort @mode_list by favorability, putting good modes first.
++ * Sort @mode_list by favorability, moving good modes to the head of the list.
+  */
+ void drm_mode_sort(struct list_head *mode_list)
+ {
+@@ -1016,21 +1013,24 @@
+ /**
+  * drm_mode_connector_list_update - update the mode list for the connector
+  * @connector: the connector to update
+- *
+- * LOCKING:
+- * Caller must hold a lock protecting @mode_list.
++ * @merge_type_bits: whether to merge or overright type bits.
+  *
+  * This moves the modes from the @connector probed_modes list
+  * to the actual mode list. It compares the probed mode against the current
+- * list and only adds different modes. All modes unverified after this point
+- * will be removed by the prune invalid modes.
++ * list and only adds different/new modes.
++ *
++ * This is just a helper functions doesn't validate any modes itself and also
++ * doesn't prune any invalid modes. Callers need to do that themselves.
+  */
+-void drm_mode_connector_list_update(struct drm_connector *connector)
++void drm_mode_connector_list_update(struct drm_connector *connector,
++				    bool merge_type_bits)
+ {
+ 	struct drm_display_mode *mode;
+ 	struct drm_display_mode *pmode, *pt;
+ 	int found_it;
+ 
++	WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex));
++
+ 	list_for_each_entry_safe(pmode, pt, &connector->probed_modes,
+ 				 head) {
+ 		found_it = 0;
+@@ -1041,7 +1041,10 @@
+ 				/* if equal delete the probed mode */
+ 				mode->status = pmode->status;
+ 				/* Merge type bits together */
+-				mode->type |= pmode->type;
++				if (merge_type_bits)
++					mode->type |= pmode->type;
++				else
++					mode->type = pmode->type;
+ 				list_del(&pmode->head);
+ 				drm_mode_destroy(connector->dev, pmode);
+ 				break;
+@@ -1056,17 +1059,25 @@
+ EXPORT_SYMBOL(drm_mode_connector_list_update);
+ 
+ /**
+- * drm_mode_parse_command_line_for_connector - parse command line for connector
+- * @mode_option - per connector mode option
+- * @connector - connector to parse line for
++ * drm_mode_parse_command_line_for_connector - parse command line modeline for connector
++ * @mode_option: optional per connector mode option
++ * @connector: connector to parse modeline for
++ * @mode: preallocated drm_cmdline_mode structure to fill out
++ *
++ * This parses @mode_option command line modeline for modes and options to
++ * configure the connector. If @mode_option is NULL the default command line
++ * modeline in fb_mode_option will be parsed instead.
+  *
+- * This parses the connector specific then generic command lines for
+- * modes and options to configure the connector.
++ * This uses the same parameters as the fb modedb.c, except for an extra
++ * force-enable, force-enable-digital and force-disable bit at the end:
+  *
+- * This uses the same parameters as the fb modedb.c, except for extra
+  *	<xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
+  *
+- * enable/enable Digital/disable bit at the end
++ * The intermediate drm_cmdline_mode structure is required to store additional
++ * options from the command line modline like the force-enabel/disable flag.
++ *
++ * Returns:
++ * True if a valid modeline has been parsed, false otherwise.
+  */
+ bool drm_mode_parse_command_line_for_connector(const char *mode_option,
+ 					       struct drm_connector *connector,
+@@ -1219,6 +1230,14 @@
+ }
+ EXPORT_SYMBOL(drm_mode_parse_command_line_for_connector);
+ 
++/**
++ * drm_mode_create_from_cmdline_mode - convert a command line modeline into a DRM display mode
++ * @dev: DRM device to create the new mode for
++ * @cmd: input command line modeline
++ *
++ * Returns:
++ * Pointer to converted mode on success, NULL on error.
++ */
+ struct drm_display_mode *
+ drm_mode_create_from_cmdline_mode(struct drm_device *dev,
+ 				  struct drm_cmdline_mode *cmd)
+@@ -1240,6 +1259,7 @@
+ 	if (!mode)
+ 		return NULL;
+ 
++	mode->type |= DRM_MODE_TYPE_USERDEF;
+ 	drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
+ 	return mode;
+ }
+diff -Naur a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c
+--- a/drivers/gpu/drm/drm_modeset_lock.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_modeset_lock.c	2015-03-26 14:42:38.734435422 +0530
+@@ -0,0 +1,482 @@
++/*
++ * Copyright (C) 2014 Red Hat
++ * Author: Rob Clark <robdclark@gmail.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_modeset_lock.h>
++
++/**
++ * DOC: kms locking
++ *
++ * As KMS moves toward more fine grained locking, and atomic ioctl where
++ * userspace can indirectly control locking order, it becomes necessary
++ * to use ww_mutex and acquire-contexts to avoid deadlocks.  But because
++ * the locking is more distributed around the driver code, we want a bit
++ * of extra utility/tracking out of our acquire-ctx.  This is provided
++ * by drm_modeset_lock / drm_modeset_acquire_ctx.
++ *
++ * For basic principles of ww_mutex, see: Documentation/locking/ww-mutex-design.txt
++ *
++ * The basic usage pattern is to:
++ *
++ *     drm_modeset_acquire_init(&ctx)
++ *   retry:
++ *     foreach (lock in random_ordered_set_of_locks) {
++ *       ret = drm_modeset_lock(lock, &ctx)
++ *       if (ret == -EDEADLK) {
++ *          drm_modeset_backoff(&ctx);
++ *          goto retry;
++ *       }
++ *     }
++ *
++ *     ... do stuff ...
++ *
++ *     drm_modeset_drop_locks(&ctx);
++ *     drm_modeset_acquire_fini(&ctx);
++ */
++
++
++/**
++ * __drm_modeset_lock_all - internal helper to grab all modeset locks
++ * @dev: DRM device
++ * @trylock: trylock mode for atomic contexts
++ *
++ * This is a special version of drm_modeset_lock_all() which can also be used in
++ * atomic contexts. Then @trylock must be set to true.
++ *
++ * Returns:
++ * 0 on success or negative error code on failure.
++ */
++int __drm_modeset_lock_all(struct drm_device *dev,
++			   bool trylock)
++{
++	struct drm_mode_config *config = &dev->mode_config;
++	struct drm_modeset_acquire_ctx *ctx;
++	int ret;
++
++	ctx = kzalloc(sizeof(*ctx),
++		      trylock ? GFP_ATOMIC : GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	if (trylock) {
++		if (!mutex_trylock(&config->mutex))
++			return -EBUSY;
++	} else {
++		mutex_lock(&config->mutex);
++	}
++
++	drm_modeset_acquire_init(ctx, 0);
++	ctx->trylock_only = trylock;
++
++retry:
++	ret = drm_modeset_lock(&config->connection_mutex, ctx);
++	if (ret)
++		goto fail;
++	ret = drm_modeset_lock_all_crtcs(dev, ctx);
++	if (ret)
++		goto fail;
++
++	WARN_ON(config->acquire_ctx);
++
++	/* now we hold the locks, so now that it is safe, stash the
++	 * ctx for drm_modeset_unlock_all():
++	 */
++	config->acquire_ctx = ctx;
++
++	drm_warn_on_modeset_not_all_locked(dev);
++
++	return 0;
++
++fail:
++	if (ret == -EDEADLK) {
++		drm_modeset_backoff(ctx);
++		goto retry;
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL(__drm_modeset_lock_all);
++
++/**
++ * drm_modeset_lock_all - take all modeset locks
++ * @dev: drm device
++ *
++ * This function takes all modeset locks, suitable where a more fine-grained
++ * scheme isn't (yet) implemented. Locks must be dropped with
++ * drm_modeset_unlock_all.
++ */
++void drm_modeset_lock_all(struct drm_device *dev)
++{
++	WARN_ON(__drm_modeset_lock_all(dev, false) != 0);
++}
++EXPORT_SYMBOL(drm_modeset_lock_all);
++
++/**
++ * drm_modeset_unlock_all - drop all modeset locks
++ * @dev: device
++ *
++ * This function drop all modeset locks taken by drm_modeset_lock_all.
++ */
++void drm_modeset_unlock_all(struct drm_device *dev)
++{
++	struct drm_mode_config *config = &dev->mode_config;
++	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
++
++	if (WARN_ON(!ctx))
++		return;
++
++	config->acquire_ctx = NULL;
++	drm_modeset_drop_locks(ctx);
++	drm_modeset_acquire_fini(ctx);
++
++	kfree(ctx);
++
++	mutex_unlock(&dev->mode_config.mutex);
++}
++EXPORT_SYMBOL(drm_modeset_unlock_all);
++
++/**
++ * drm_modeset_lock_crtc - lock crtc with hidden acquire ctx for a plane update
++ * @crtc: DRM CRTC
++ * @plane: DRM plane to be updated on @crtc
++ *
++ * This function locks the given crtc and plane (which should be either the
++ * primary or cursor plane) using a hidden acquire context. This is necessary so
++ * that drivers internally using the atomic interfaces can grab further locks
++ * with the lock acquire context.
++ *
++ * Note that @plane can be NULL, e.g. when the cursor support hasn't yet been
++ * converted to universal planes yet.
++ */
++void drm_modeset_lock_crtc(struct drm_crtc *crtc,
++			   struct drm_plane *plane)
++{
++	struct drm_modeset_acquire_ctx *ctx;
++	int ret;
++
++	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
++	if (WARN_ON(!ctx))
++		return;
++
++	drm_modeset_acquire_init(ctx, 0);
++
++retry:
++	ret = drm_modeset_lock(&crtc->mutex, ctx);
++	if (ret)
++		goto fail;
++
++	if (plane) {
++		ret = drm_modeset_lock(&plane->mutex, ctx);
++		if (ret)
++			goto fail;
++
++		if (plane->crtc) {
++			ret = drm_modeset_lock(&plane->crtc->mutex, ctx);
++			if (ret)
++				goto fail;
++		}
++	}
++
++	WARN_ON(crtc->acquire_ctx);
++
++	/* now we hold the locks, so now that it is safe, stash the
++	 * ctx for drm_modeset_unlock_crtc():
++	 */
++	crtc->acquire_ctx = ctx;
++
++	return;
++
++fail:
++	if (ret == -EDEADLK) {
++		drm_modeset_backoff(ctx);
++		goto retry;
++	}
++}
++EXPORT_SYMBOL(drm_modeset_lock_crtc);
++
++/**
++ * drm_modeset_legacy_acquire_ctx - find acquire ctx for legacy ioctls
++ * @crtc: drm crtc
++ *
++ * Legacy ioctl operations like cursor updates or page flips only have per-crtc
++ * locking, and store the acquire ctx in the corresponding crtc. All other
++ * legacy operations take all locks and use a global acquire context. This
++ * function grabs the right one.
++ */
++struct drm_modeset_acquire_ctx *
++drm_modeset_legacy_acquire_ctx(struct drm_crtc *crtc)
++{
++	if (crtc->acquire_ctx)
++		return crtc->acquire_ctx;
++
++	WARN_ON(!crtc->dev->mode_config.acquire_ctx);
++
++	return crtc->dev->mode_config.acquire_ctx;
++}
++EXPORT_SYMBOL(drm_modeset_legacy_acquire_ctx);
++
++/**
++ * drm_modeset_unlock_crtc - drop crtc lock
++ * @crtc: drm crtc
++ *
++ * This drops the crtc lock acquire with drm_modeset_lock_crtc() and all other
++ * locks acquired through the hidden context.
++ */
++void drm_modeset_unlock_crtc(struct drm_crtc *crtc)
++{
++	struct drm_modeset_acquire_ctx *ctx = crtc->acquire_ctx;
++
++	if (WARN_ON(!ctx))
++		return;
++
++	crtc->acquire_ctx = NULL;
++	drm_modeset_drop_locks(ctx);
++	drm_modeset_acquire_fini(ctx);
++
++	kfree(ctx);
++}
++EXPORT_SYMBOL(drm_modeset_unlock_crtc);
++
++/**
++ * drm_warn_on_modeset_not_all_locked - check that all modeset locks are locked
++ * @dev: device
++ *
++ * Useful as a debug assert.
++ */
++void drm_warn_on_modeset_not_all_locked(struct drm_device *dev)
++{
++	struct drm_crtc *crtc;
++
++	/* Locking is currently fubar in the panic handler. */
++	if (oops_in_progress)
++		return;
++
++	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
++		WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
++
++	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
++	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
++}
++EXPORT_SYMBOL(drm_warn_on_modeset_not_all_locked);
++
++/**
++ * drm_modeset_acquire_init - initialize acquire context
++ * @ctx: the acquire context
++ * @flags: for future
++ */
++void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
++		uint32_t flags)
++{
++	memset(ctx, 0, sizeof(*ctx));
++	ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class);
++	INIT_LIST_HEAD(&ctx->locked);
++}
++EXPORT_SYMBOL(drm_modeset_acquire_init);
++
++/**
++ * drm_modeset_acquire_fini - cleanup acquire context
++ * @ctx: the acquire context
++ */
++void drm_modeset_acquire_fini(struct drm_modeset_acquire_ctx *ctx)
++{
++	ww_acquire_fini(&ctx->ww_ctx);
++}
++EXPORT_SYMBOL(drm_modeset_acquire_fini);
++
++/**
++ * drm_modeset_drop_locks - drop all locks
++ * @ctx: the acquire context
++ *
++ * Drop all locks currently held against this acquire context.
++ */
++void drm_modeset_drop_locks(struct drm_modeset_acquire_ctx *ctx)
++{
++	WARN_ON(ctx->contended);
++	while (!list_empty(&ctx->locked)) {
++		struct drm_modeset_lock *lock;
++
++		lock = list_first_entry(&ctx->locked,
++				struct drm_modeset_lock, head);
++
++		drm_modeset_unlock(lock);
++	}
++}
++EXPORT_SYMBOL(drm_modeset_drop_locks);
++
++static inline int modeset_lock(struct drm_modeset_lock *lock,
++		struct drm_modeset_acquire_ctx *ctx,
++		bool interruptible, bool slow)
++{
++	int ret;
++
++	WARN_ON(ctx->contended);
++
++	if (ctx->trylock_only) {
++		if (!ww_mutex_trylock(&lock->mutex))
++			return -EBUSY;
++		else
++			return 0;
++	} else if (interruptible && slow) {
++		ret = ww_mutex_lock_slow_interruptible(&lock->mutex, &ctx->ww_ctx);
++	} else if (interruptible) {
++		ret = ww_mutex_lock_interruptible(&lock->mutex, &ctx->ww_ctx);
++	} else if (slow) {
++		ww_mutex_lock_slow(&lock->mutex, &ctx->ww_ctx);
++		ret = 0;
++	} else {
++		ret = ww_mutex_lock(&lock->mutex, &ctx->ww_ctx);
++	}
++	if (!ret) {
++		WARN_ON(!list_empty(&lock->head));
++		list_add(&lock->head, &ctx->locked);
++	} else if (ret == -EALREADY) {
++		/* we already hold the lock.. this is fine.  For atomic
++		 * we will need to be able to drm_modeset_lock() things
++		 * without having to keep track of what is already locked
++		 * or not.
++		 */
++		ret = 0;
++	} else if (ret == -EDEADLK) {
++		ctx->contended = lock;
++	}
++
++	return ret;
++}
++
++static int modeset_backoff(struct drm_modeset_acquire_ctx *ctx,
++		bool interruptible)
++{
++	struct drm_modeset_lock *contended = ctx->contended;
++
++	ctx->contended = NULL;
++
++	if (WARN_ON(!contended))
++		return 0;
++
++	drm_modeset_drop_locks(ctx);
++
++	return modeset_lock(contended, ctx, interruptible, true);
++}
++
++/**
++ * drm_modeset_backoff - deadlock avoidance backoff
++ * @ctx: the acquire context
++ *
++ * If deadlock is detected (ie. drm_modeset_lock() returns -EDEADLK),
++ * you must call this function to drop all currently held locks and
++ * block until the contended lock becomes available.
++ */
++void drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx)
++{
++	modeset_backoff(ctx, false);
++}
++EXPORT_SYMBOL(drm_modeset_backoff);
++
++/**
++ * drm_modeset_backoff_interruptible - deadlock avoidance backoff
++ * @ctx: the acquire context
++ *
++ * Interruptible version of drm_modeset_backoff()
++ */
++int drm_modeset_backoff_interruptible(struct drm_modeset_acquire_ctx *ctx)
++{
++	return modeset_backoff(ctx, true);
++}
++EXPORT_SYMBOL(drm_modeset_backoff_interruptible);
++
++/**
++ * drm_modeset_lock - take modeset lock
++ * @lock: lock to take
++ * @ctx: acquire ctx
++ *
++ * If ctx is not NULL, then its ww acquire context is used and the
++ * lock will be tracked by the context and can be released by calling
++ * drm_modeset_drop_locks().  If -EDEADLK is returned, this means a
++ * deadlock scenario has been detected and it is an error to attempt
++ * to take any more locks without first calling drm_modeset_backoff().
++ */
++int drm_modeset_lock(struct drm_modeset_lock *lock,
++		struct drm_modeset_acquire_ctx *ctx)
++{
++	if (ctx)
++		return modeset_lock(lock, ctx, false, false);
++
++	ww_mutex_lock(&lock->mutex, NULL);
++	return 0;
++}
++EXPORT_SYMBOL(drm_modeset_lock);
++
++/**
++ * drm_modeset_lock_interruptible - take modeset lock
++ * @lock: lock to take
++ * @ctx: acquire ctx
++ *
++ * Interruptible version of drm_modeset_lock()
++ */
++int drm_modeset_lock_interruptible(struct drm_modeset_lock *lock,
++		struct drm_modeset_acquire_ctx *ctx)
++{
++	if (ctx)
++		return modeset_lock(lock, ctx, true, false);
++
++	return ww_mutex_lock_interruptible(&lock->mutex, NULL);
++}
++EXPORT_SYMBOL(drm_modeset_lock_interruptible);
++
++/**
++ * drm_modeset_unlock - drop modeset lock
++ * @lock: lock to release
++ */
++void drm_modeset_unlock(struct drm_modeset_lock *lock)
++{
++	list_del_init(&lock->head);
++	ww_mutex_unlock(&lock->mutex);
++}
++EXPORT_SYMBOL(drm_modeset_unlock);
++
++/* In some legacy codepaths it's convenient to just grab all the crtc and plane
++ * related locks. */
++int drm_modeset_lock_all_crtcs(struct drm_device *dev,
++		struct drm_modeset_acquire_ctx *ctx)
++{
++	struct drm_mode_config *config = &dev->mode_config;
++	struct drm_crtc *crtc;
++	struct drm_plane *plane;
++	int ret = 0;
++
++	list_for_each_entry(crtc, &config->crtc_list, head) {
++		ret = drm_modeset_lock(&crtc->mutex, ctx);
++		if (ret)
++			return ret;
++	}
++
++	list_for_each_entry(plane, &config->plane_list, head) {
++		ret = drm_modeset_lock(&plane->mutex, ctx);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_modeset_lock_all_crtcs);
+diff -Naur a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
+--- a/drivers/gpu/drm/drm_of.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_of.c	2015-03-26 14:42:38.734435422 +0530
+@@ -0,0 +1,67 @@
++#include <linux/export.h>
++#include <linux/list.h>
++#include <linux/of_graph.h>
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_of.h>
++
++/**
++ * drm_crtc_port_mask - find the mask of a registered CRTC by port OF node
++ * @dev: DRM device
++ * @port: port OF node
++ *
++ * Given a port OF node, return the possible mask of the corresponding
++ * CRTC within a device's list of CRTCs.  Returns zero if not found.
++ */
++static uint32_t drm_crtc_port_mask(struct drm_device *dev,
++				   struct device_node *port)
++{
++	unsigned int index = 0;
++	struct drm_crtc *tmp;
++
++	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
++		if (tmp->port == port)
++			return 1 << index;
++
++		index++;
++	}
++
++	return 0;
++}
++
++/**
++ * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
++ * @dev: DRM device
++ * @port: encoder port to scan for endpoints
++ *
++ * Scan all endpoints attached to a port, locate their attached CRTCs,
++ * and generate the DRM mask of CRTCs which may be attached to this
++ * encoder.
++ *
++ * See Documentation/devicetree/bindings/graph.txt for the bindings.
++ */
++uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
++				    struct device_node *port)
++{
++	struct device_node *remote_port, *ep = NULL;
++	uint32_t possible_crtcs = 0;
++
++	do {
++		ep = of_graph_get_next_endpoint(port, ep);
++		if (!ep)
++			break;
++
++		remote_port = of_graph_get_remote_port(ep);
++		if (!remote_port) {
++			of_node_put(ep);
++			return 0;
++		}
++
++		possible_crtcs |= drm_crtc_port_mask(dev, remote_port);
++
++		of_node_put(remote_port);
++	} while (1);
++
++	return possible_crtcs;
++}
++EXPORT_SYMBOL(drm_of_find_possible_crtcs);
+diff -Naur a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
+--- a/drivers/gpu/drm/drm_pci.c	2015-03-26 14:43:30.426436436 +0530
++++ b/drivers/gpu/drm/drm_pci.c	2015-03-26 14:42:38.734435422 +0530
+@@ -1,17 +1,3 @@
+-/* drm_pci.h -- PCI DMA memory management wrappers for DRM -*- linux-c -*- */
+-/**
+- * \file drm_pci.c
+- * \brief Functions and ioctls to manage PCI memory
+- *
+- * \warning These interfaces aren't stable yet.
+- *
+- * \todo Implement the remaining ioctl's for the PCI pools.
+- * \todo The wrappers here are so thin that they would be better off inlined..
+- *
+- * \author José Fonseca <jrfonseca@tungstengraphics.com>
+- * \author Leif Delgass <ldelgass@retinalburn.net>
+- */
+-
+ /*
+  * Copyright 2003 José Fonseca.
+  * Copyright 2003 Leif Delgass.
+@@ -41,13 +27,16 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/export.h>
+ #include <drm/drmP.h>
+-
+-/**********************************************************************/
+-/** \name PCI memory */
+-/*@{*/
++#include "drm_legacy.h"
+ 
+ /**
+- * \brief Allocate a PCI consistent memory block, for DMA.
++ * drm_pci_alloc - Allocate a PCI consistent memory block, for DMA.
++ * @dev: DRM device
++ * @size: size of block to allocate
++ * @align: alignment of block
++ *
++ * Return: A handle to the allocated memory block on success or NULL on
++ * failure.
+  */
+ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align)
+ {
+@@ -88,12 +77,12 @@
+ 
+ EXPORT_SYMBOL(drm_pci_alloc);
+ 
+-/**
+- * \brief Free a PCI consistent memory block without freeing its descriptor.
++/*
++ * Free a PCI consistent memory block without freeing its descriptor.
+  *
+  * This function is for internal use in the Linux-specific DRM core code.
+  */
+-void __drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
++void __drm_legacy_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
+ {
+ 	unsigned long addr;
+ 	size_t sz;
+@@ -111,11 +100,13 @@
+ }
+ 
+ /**
+- * \brief Free a PCI consistent memory block
++ * drm_pci_free - Free a PCI consistent memory block
++ * @dev: DRM device
++ * @dmah: handle to memory block
+  */
+ void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
+ {
+-	__drm_pci_free(dev, dmah);
++	__drm_legacy_pci_free(dev, dmah);
+ 	kfree(dmah);
+ }
+ 
+@@ -137,69 +128,29 @@
+ 	return pci_domain_nr(dev->pdev->bus);
+ }
+ 
+-static int drm_pci_get_irq(struct drm_device *dev)
+-{
+-	return dev->pdev->irq;
+-}
+-
+-static const char *drm_pci_get_name(struct drm_device *dev)
+-{
+-	struct pci_driver *pdriver = dev->driver->kdriver.pci;
+-	return pdriver->name;
+-}
+-
+-static int drm_pci_set_busid(struct drm_device *dev, struct drm_master *master)
++int drm_pci_set_busid(struct drm_device *dev, struct drm_master *master)
+ {
+-	int len, ret;
+-	struct pci_driver *pdriver = dev->driver->kdriver.pci;
+-	master->unique_len = 40;
+-	master->unique_size = master->unique_len;
+-	master->unique = kmalloc(master->unique_size, GFP_KERNEL);
+-	if (master->unique == NULL)
++	master->unique = kasprintf(GFP_KERNEL, "pci:%04x:%02x:%02x.%d",
++					drm_get_pci_domain(dev),
++					dev->pdev->bus->number,
++					PCI_SLOT(dev->pdev->devfn),
++					PCI_FUNC(dev->pdev->devfn));
++	if (!master->unique)
+ 		return -ENOMEM;
+ 
+-
+-	len = snprintf(master->unique, master->unique_len,
+-		       "pci:%04x:%02x:%02x.%d",
+-		       drm_get_pci_domain(dev),
+-		       dev->pdev->bus->number,
+-		       PCI_SLOT(dev->pdev->devfn),
+-		       PCI_FUNC(dev->pdev->devfn));
+-
+-	if (len >= master->unique_len) {
+-		DRM_ERROR("buffer overflow");
+-		ret = -EINVAL;
+-		goto err;
+-	} else
+-		master->unique_len = len;
+-
+-	dev->devname =
+-		kmalloc(strlen(pdriver->name) +
+-			master->unique_len + 2, GFP_KERNEL);
+-
+-	if (dev->devname == NULL) {
+-		ret = -ENOMEM;
+-		goto err;
+-	}
+-
+-	sprintf(dev->devname, "%s@%s", pdriver->name,
+-		master->unique);
+-
++	master->unique_len = strlen(master->unique);
+ 	return 0;
+-err:
+-	return ret;
+ }
++EXPORT_SYMBOL(drm_pci_set_busid);
+ 
+-static int drm_pci_set_unique(struct drm_device *dev,
+-			      struct drm_master *master,
+-			      struct drm_unique *u)
++int drm_pci_set_unique(struct drm_device *dev,
++		       struct drm_master *master,
++		       struct drm_unique *u)
+ {
+ 	int domain, bus, slot, func, ret;
+-	const char *bus_name;
+ 
+ 	master->unique_len = u->unique_len;
+-	master->unique_size = u->unique_len + 1;
+-	master->unique = kmalloc(master->unique_size, GFP_KERNEL);
++	master->unique = kmalloc(master->unique_len + 1, GFP_KERNEL);
+ 	if (!master->unique) {
+ 		ret = -ENOMEM;
+ 		goto err;
+@@ -212,17 +163,6 @@
+ 
+ 	master->unique[master->unique_len] = '\0';
+ 
+-	bus_name = dev->driver->bus->get_name(dev);
+-	dev->devname = kmalloc(strlen(bus_name) +
+-			       strlen(master->unique) + 2, GFP_KERNEL);
+-	if (!dev->devname) {
+-		ret = -ENOMEM;
+-		goto err;
+-	}
+-
+-	sprintf(dev->devname, "%s@%s", bus_name,
+-		master->unique);
+-
+ 	/* Return error if the busid submitted doesn't match the device's actual
+ 	 * busid.
+ 	 */
+@@ -247,7 +187,6 @@
+ 	return ret;
+ }
+ 
+-
+ static int drm_pci_irq_by_busid(struct drm_device *dev, struct drm_irq_busid *p)
+ {
+ 	if ((p->busnum >> 8) != drm_get_pci_domain(dev) ||
+@@ -262,6 +201,36 @@
+ 	return 0;
+ }
+ 
++/**
++ * drm_irq_by_busid - Get interrupt from bus ID
++ * @dev: DRM device
++ * @data: IOCTL parameter pointing to a drm_irq_busid structure
++ * @file_priv: DRM file private.
++ *
++ * Finds the PCI device with the specified bus id and gets its IRQ number.
++ * This IOCTL is deprecated, and will now return EINVAL for any busid not equal
++ * to that of the device that this DRM instance attached to.
++ *
++ * Return: 0 on success or a negative error code on failure.
++ */
++int drm_irq_by_busid(struct drm_device *dev, void *data,
++		     struct drm_file *file_priv)
++{
++	struct drm_irq_busid *p = data;
++
++	if (drm_core_check_feature(dev, DRIVER_MODESET))
++		return -EINVAL;
++
++	/* UMS was only ever support on PCI devices. */
++	if (WARN_ON(!dev->pdev))
++		return -EINVAL;
++
++	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
++		return -EINVAL;
++
++	return drm_pci_irq_by_busid(dev, p);
++}
++
+ static void drm_pci_agp_init(struct drm_device *dev)
+ {
+ 	if (drm_core_check_feature(dev, DRIVER_USE_AGP)) {
+@@ -286,25 +255,17 @@
+ 	}
+ }
+ 
+-static struct drm_bus drm_pci_bus = {
+-	.bus_type = DRIVER_BUS_PCI,
+-	.get_irq = drm_pci_get_irq,
+-	.get_name = drm_pci_get_name,
+-	.set_busid = drm_pci_set_busid,
+-	.set_unique = drm_pci_set_unique,
+-	.irq_by_busid = drm_pci_irq_by_busid,
+-};
+-
+ /**
+- * Register.
+- *
+- * \param pdev - PCI device structure
+- * \param ent entry from the PCI ID table with device type flags
+- * \return zero on success or a negative number on failure.
++ * drm_get_pci_dev - Register a PCI device with the DRM subsystem
++ * @pdev: PCI device
++ * @ent: entry from the PCI ID table that matches @pdev
++ * @driver: DRM device driver
+  *
+  * Attempt to gets inter module "drm" information. If we are first
+  * then register the character device and inter module information.
+  * Try and register, if we fail to register, backout previous work.
++ *
++ * Return: 0 on success or a negative error code on failure.
+  */
+ int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
+ 		    struct drm_driver *driver)
+@@ -351,21 +312,20 @@
+ 	drm_pci_agp_destroy(dev);
+ 	pci_disable_device(pdev);
+ err_free:
+-	drm_dev_free(dev);
++	drm_dev_unref(dev);
+ 	return ret;
+ }
+ EXPORT_SYMBOL(drm_get_pci_dev);
+ 
+ /**
+- * PCI device initialization. Called direct from modules at load time.
++ * drm_pci_init - Register matching PCI devices with the DRM subsystem
++ * @driver: DRM device driver
++ * @pdriver: PCI device driver
+  *
+- * \return zero on success or a negative number on failure.
++ * Initializes a drm_device structures, registering the stubs and initializing
++ * the AGP device.
+  *
+- * Initializes a drm_device structures,registering the
+- * stubs and initializing the AGP device.
+- *
+- * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
+- * after the initialization for driver customization.
++ * Return: 0 on success or a negative error code on failure.
+  */
+ int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver)
+ {
+@@ -375,9 +335,6 @@
+ 
+ 	DRM_DEBUG("\n");
+ 
+-	driver->kdriver.pci = pdriver;
+-	driver->bus = &drm_pci_bus;
+-
+ 	if (driver->driver_features & DRIVER_MODESET)
+ 		return pci_register_driver(pdriver);
+ 
+@@ -453,11 +410,31 @@
+ }
+ 
+ void drm_pci_agp_destroy(struct drm_device *dev) {}
++
++int drm_irq_by_busid(struct drm_device *dev, void *data,
++		     struct drm_file *file_priv)
++{
++	return -EINVAL;
++}
++
++int drm_pci_set_unique(struct drm_device *dev,
++		       struct drm_master *master,
++		       struct drm_unique *u)
++{
++	return -EINVAL;
++}
+ #endif
+ 
+ EXPORT_SYMBOL(drm_pci_init);
+ 
+-/*@}*/
++/**
++ * drm_pci_exit - Unregister matching PCI devices from the DRM subsystem
++ * @driver: DRM device driver
++ * @pdriver: PCI device driver
++ *
++ * Unregisters one or more devices matched by a PCI driver from the DRM
++ * subsystem.
++ */
+ void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver)
+ {
+ 	struct drm_device *dev, *tmp;
+diff -Naur a/drivers/gpu/drm/drm_plane_helper.c b/drivers/gpu/drm/drm_plane_helper.c
+--- a/drivers/gpu/drm/drm_plane_helper.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_plane_helper.c	2015-03-26 14:42:38.734435422 +0530
+@@ -0,0 +1,572 @@
++/*
++ * Copyright (C) 2014 Intel Corporation
++ *
++ * DRM universal plane helper functions
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ */
++
++#include <linux/list.h>
++#include <drm/drmP.h>
++#include <drm/drm_plane_helper.h>
++#include <drm/drm_rect.h>
++#include <drm/drm_atomic.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_atomic_helper.h>
++
++#define SUBPIXEL_MASK 0xffff
++
++/**
++ * DOC: overview
++ *
++ * This helper library has two parts. The first part has support to implement
++ * primary plane support on top of the normal CRTC configuration interface.
++ * Since the legacy ->set_config interface ties the primary plane together with
++ * the CRTC state this does not allow userspace to disable the primary plane
++ * itself.  To avoid too much duplicated code use
++ * drm_plane_helper_check_update() which can be used to enforce the same
++ * restrictions as primary planes had thus. The default primary plane only
++ * expose XRBG8888 and ARGB8888 as valid pixel formats for the attached
++ * framebuffer.
++ *
++ * Drivers are highly recommended to implement proper support for primary
++ * planes, and newly merged drivers must not rely upon these transitional
++ * helpers.
++ *
++ * The second part also implements transitional helpers which allow drivers to
++ * gradually switch to the atomic helper infrastructure for plane updates. Once
++ * that switch is complete drivers shouldn't use these any longer, instead using
++ * the proper legacy implementations for update and disable plane hooks provided
++ * by the atomic helpers.
++ *
++ * Again drivers are strongly urged to switch to the new interfaces.
++ */
++
++/*
++ * This is the minimal list of formats that seem to be safe for modeset use
++ * with all current DRM drivers.  Most hardware can actually support more
++ * formats than this and drivers may specify a more accurate list when
++ * creating the primary plane.  However drivers that still call
++ * drm_plane_init() will use this minimal format list as the default.
++ */
++static const uint32_t safe_modeset_formats[] = {
++	DRM_FORMAT_XRGB8888,
++	DRM_FORMAT_ARGB8888,
++};
++
++/*
++ * Returns the connectors currently associated with a CRTC.  This function
++ * should be called twice:  once with a NULL connector list to retrieve
++ * the list size, and once with the properly allocated list to be filled in.
++ */
++static int get_connectors_for_crtc(struct drm_crtc *crtc,
++				   struct drm_connector **connector_list,
++				   int num_connectors)
++{
++	struct drm_device *dev = crtc->dev;
++	struct drm_connector *connector;
++	int count = 0;
++
++	/*
++	 * Note: Once we change the plane hooks to more fine-grained locking we
++	 * need to grab the connection_mutex here to be able to make these
++	 * checks.
++	 */
++	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
++		if (connector->encoder && connector->encoder->crtc == crtc) {
++			if (connector_list != NULL && count < num_connectors)
++				*(connector_list++) = connector;
++
++			count++;
++		}
++
++	return count;
++}
++
++/**
++ * drm_plane_helper_check_update() - Check plane update for validity
++ * @plane: plane object to update
++ * @crtc: owning CRTC of owning plane
++ * @fb: framebuffer to flip onto plane
++ * @src: source coordinates in 16.16 fixed point
++ * @dest: integer destination coordinates
++ * @clip: integer clipping coordinates
++ * @min_scale: minimum @src:@dest scaling factor in 16.16 fixed point
++ * @max_scale: maximum @src:@dest scaling factor in 16.16 fixed point
++ * @can_position: is it legal to position the plane such that it
++ *                doesn't cover the entire crtc?  This will generally
++ *                only be false for primary planes.
++ * @can_update_disabled: can the plane be updated while the crtc
++ *                       is disabled?
++ * @visible: output parameter indicating whether plane is still visible after
++ *           clipping
++ *
++ * Checks that a desired plane update is valid.  Drivers that provide
++ * their own plane handling rather than helper-provided implementations may
++ * still wish to call this function to avoid duplication of error checking
++ * code.
++ *
++ * RETURNS:
++ * Zero if update appears valid, error code on failure
++ */
++int drm_plane_helper_check_update(struct drm_plane *plane,
++				    struct drm_crtc *crtc,
++				    struct drm_framebuffer *fb,
++				    struct drm_rect *src,
++				    struct drm_rect *dest,
++				    const struct drm_rect *clip,
++				    int min_scale,
++				    int max_scale,
++				    bool can_position,
++				    bool can_update_disabled,
++				    bool *visible)
++{
++	int hscale, vscale;
++
++	if (!crtc->enabled && !can_update_disabled) {
++		DRM_DEBUG_KMS("Cannot update plane of a disabled CRTC.\n");
++		return -EINVAL;
++	}
++
++	/* Check scaling */
++	hscale = drm_rect_calc_hscale(src, dest, min_scale, max_scale);
++	vscale = drm_rect_calc_vscale(src, dest, min_scale, max_scale);
++	if (hscale < 0 || vscale < 0) {
++		DRM_DEBUG_KMS("Invalid scaling of plane\n");
++		return -ERANGE;
++	}
++
++	if (!fb) {
++		*visible = false;
++		return 0;
++	}
++
++	*visible = drm_rect_clip_scaled(src, dest, clip, hscale, vscale);
++	if (!*visible)
++		/*
++		 * Plane isn't visible; some drivers can handle this
++		 * so we just return success here.  Drivers that can't
++		 * (including those that use the primary plane helper's
++		 * update function) will return an error from their
++		 * update_plane handler.
++		 */
++		return 0;
++
++	if (!can_position && !drm_rect_equals(dest, clip)) {
++		DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(drm_plane_helper_check_update);
++
++/**
++ * drm_primary_helper_update() - Helper for primary plane update
++ * @plane: plane object to update
++ * @crtc: owning CRTC of owning plane
++ * @fb: framebuffer to flip onto plane
++ * @crtc_x: x offset of primary plane on crtc
++ * @crtc_y: y offset of primary plane on crtc
++ * @crtc_w: width of primary plane rectangle on crtc
++ * @crtc_h: height of primary plane rectangle on crtc
++ * @src_x: x offset of @fb for panning
++ * @src_y: y offset of @fb for panning
++ * @src_w: width of source rectangle in @fb
++ * @src_h: height of source rectangle in @fb
++ *
++ * Provides a default plane update handler for primary planes.  This is handler
++ * is called in response to a userspace SetPlane operation on the plane with a
++ * non-NULL framebuffer.  We call the driver's modeset handler to update the
++ * framebuffer.
++ *
++ * SetPlane() on a primary plane of a disabled CRTC is not supported, and will
++ * return an error.
++ *
++ * Note that we make some assumptions about hardware limitations that may not be
++ * true for all hardware --
++ *   1) Primary plane cannot be repositioned.
++ *   2) Primary plane cannot be scaled.
++ *   3) Primary plane must cover the entire CRTC.
++ *   4) Subpixel positioning is not supported.
++ * Drivers for hardware that don't have these restrictions can provide their
++ * own implementation rather than using this helper.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int drm_primary_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
++			      struct drm_framebuffer *fb,
++			      int crtc_x, int crtc_y,
++			      unsigned int crtc_w, unsigned int crtc_h,
++			      uint32_t src_x, uint32_t src_y,
++			      uint32_t src_w, uint32_t src_h)
++{
++	struct drm_mode_set set = {
++		.crtc = crtc,
++		.fb = fb,
++		.mode = &crtc->mode,
++		.x = src_x >> 16,
++		.y = src_y >> 16,
++	};
++	struct drm_rect src = {
++		.x1 = src_x,
++		.y1 = src_y,
++		.x2 = src_x + src_w,
++		.y2 = src_y + src_h,
++	};
++	struct drm_rect dest = {
++		.x1 = crtc_x,
++		.y1 = crtc_y,
++		.x2 = crtc_x + crtc_w,
++		.y2 = crtc_y + crtc_h,
++	};
++	const struct drm_rect clip = {
++		.x2 = crtc->mode.hdisplay,
++		.y2 = crtc->mode.vdisplay,
++	};
++	struct drm_connector **connector_list;
++	int num_connectors, ret;
++	bool visible;
++
++	ret = drm_plane_helper_check_update(plane, crtc, fb,
++					    &src, &dest, &clip,
++					    DRM_PLANE_HELPER_NO_SCALING,
++					    DRM_PLANE_HELPER_NO_SCALING,
++					    false, false, &visible);
++	if (ret)
++		return ret;
++
++	if (!visible)
++		/*
++		 * Primary plane isn't visible.  Note that unless a driver
++		 * provides their own disable function, this will just
++		 * wind up returning -EINVAL to userspace.
++		 */
++		return plane->funcs->disable_plane(plane);
++
++	/* Find current connectors for CRTC */
++	num_connectors = get_connectors_for_crtc(crtc, NULL, 0);
++	BUG_ON(num_connectors == 0);
++	connector_list = kzalloc(num_connectors * sizeof(*connector_list),
++				 GFP_KERNEL);
++	if (!connector_list)
++		return -ENOMEM;
++	get_connectors_for_crtc(crtc, connector_list, num_connectors);
++
++	set.connectors = connector_list;
++	set.num_connectors = num_connectors;
++
++	/*
++	 * We call set_config() directly here rather than using
++	 * drm_mode_set_config_internal.  We're reprogramming the same
++	 * connectors that were already in use, so we shouldn't need the extra
++	 * cross-CRTC fb refcounting to accomodate stealing connectors.
++	 * drm_mode_setplane() already handles the basic refcounting for the
++	 * framebuffers involved in this operation.
++	 */
++	ret = crtc->funcs->set_config(&set);
++
++	kfree(connector_list);
++	return ret;
++}
++EXPORT_SYMBOL(drm_primary_helper_update);
++
++/**
++ * drm_primary_helper_disable() - Helper for primary plane disable
++ * @plane: plane to disable
++ *
++ * Provides a default plane disable handler for primary planes.  This is handler
++ * is called in response to a userspace SetPlane operation on the plane with a
++ * NULL framebuffer parameter.  It unconditionally fails the disable call with
++ * -EINVAL the only way to disable the primary plane without driver support is
++ * to disable the entier CRTC. Which does not match the plane ->disable hook.
++ *
++ * Note that some hardware may be able to disable the primary plane without
++ * disabling the whole CRTC.  Drivers for such hardware should provide their
++ * own disable handler that disables just the primary plane (and they'll likely
++ * need to provide their own update handler as well to properly re-enable a
++ * disabled primary plane).
++ *
++ * RETURNS:
++ * Unconditionally returns -EINVAL.
++ */
++int drm_primary_helper_disable(struct drm_plane *plane)
++{
++	return -EINVAL;
++}
++EXPORT_SYMBOL(drm_primary_helper_disable);
++
++/**
++ * drm_primary_helper_destroy() - Helper for primary plane destruction
++ * @plane: plane to destroy
++ *
++ * Provides a default plane destroy handler for primary planes.  This handler
++ * is called during CRTC destruction.  We disable the primary plane, remove
++ * it from the DRM plane list, and deallocate the plane structure.
++ */
++void drm_primary_helper_destroy(struct drm_plane *plane)
++{
++	drm_plane_cleanup(plane);
++	kfree(plane);
++}
++EXPORT_SYMBOL(drm_primary_helper_destroy);
++
++const struct drm_plane_funcs drm_primary_helper_funcs = {
++	.update_plane = drm_primary_helper_update,
++	.disable_plane = drm_primary_helper_disable,
++	.destroy = drm_primary_helper_destroy,
++};
++EXPORT_SYMBOL(drm_primary_helper_funcs);
++
++/**
++ * drm_primary_helper_create_plane() - Create a generic primary plane
++ * @dev: drm device
++ * @formats: pixel formats supported, or NULL for a default safe list
++ * @num_formats: size of @formats; ignored if @formats is NULL
++ *
++ * Allocates and initializes a primary plane that can be used with the primary
++ * plane helpers.  Drivers that wish to use driver-specific plane structures or
++ * provide custom handler functions may perform their own allocation and
++ * initialization rather than calling this function.
++ */
++struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev,
++						  const uint32_t *formats,
++						  int num_formats)
++{
++	struct drm_plane *primary;
++	int ret;
++
++	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
++	if (primary == NULL) {
++		DRM_DEBUG_KMS("Failed to allocate primary plane\n");
++		return NULL;
++	}
++
++	if (formats == NULL) {
++		formats = safe_modeset_formats;
++		num_formats = ARRAY_SIZE(safe_modeset_formats);
++	}
++
++	/* possible_crtc's will be filled in later by crtc_init */
++	ret = drm_universal_plane_init(dev, primary, 0,
++				       &drm_primary_helper_funcs,
++				       formats, num_formats,
++				       DRM_PLANE_TYPE_PRIMARY);
++	if (ret) {
++		kfree(primary);
++		primary = NULL;
++	}
++
++	return primary;
++}
++EXPORT_SYMBOL(drm_primary_helper_create_plane);
++
++/**
++ * drm_crtc_init - Legacy CRTC initialization function
++ * @dev: DRM device
++ * @crtc: CRTC object to init
++ * @funcs: callbacks for the new CRTC
++ *
++ * Initialize a CRTC object with a default helper-provided primary plane and no
++ * cursor plane.
++ *
++ * Returns:
++ * Zero on success, error code on failure.
++ */
++int drm_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
++		  const struct drm_crtc_funcs *funcs)
++{
++	struct drm_plane *primary;
++
++	primary = drm_primary_helper_create_plane(dev, NULL, 0);
++	return drm_crtc_init_with_planes(dev, crtc, primary, NULL, funcs);
++}
++EXPORT_SYMBOL(drm_crtc_init);
++
++int drm_plane_helper_commit(struct drm_plane *plane,
++			    struct drm_plane_state *plane_state,
++			    struct drm_framebuffer *old_fb)
++{
++	struct drm_plane_helper_funcs *plane_funcs;
++	struct drm_crtc *crtc[2];
++	struct drm_crtc_helper_funcs *crtc_funcs[2];
++	int i, ret = 0;
++
++	plane_funcs = plane->helper_private;
++
++	/* Since this is a transitional helper we can't assume that plane->state
++	 * is always valid. Hence we need to use plane->crtc instead of
++	 * plane->state->crtc as the old crtc. */
++	crtc[0] = plane->crtc;
++	crtc[1] = crtc[0] != plane_state->crtc ? plane_state->crtc : NULL;
++
++	for (i = 0; i < 2; i++)
++		crtc_funcs[i] = crtc[i] ? crtc[i]->helper_private : NULL;
++
++	if (plane_funcs->atomic_check) {
++		ret = plane_funcs->atomic_check(plane, plane_state);
++		if (ret)
++			goto out;
++	}
++
++	if (plane_funcs->prepare_fb && plane_state->fb) {
++		ret = plane_funcs->prepare_fb(plane, plane_state->fb);
++		if (ret)
++			goto out;
++	}
++
++	/* Point of no return, commit sw state. */
++	swap(plane->state, plane_state);
++
++	for (i = 0; i < 2; i++) {
++		if (crtc_funcs[i] && crtc_funcs[i]->atomic_begin)
++			crtc_funcs[i]->atomic_begin(crtc[i]);
++	}
++
++	plane_funcs->atomic_update(plane, plane_state);
++
++	for (i = 0; i < 2; i++) {
++		if (crtc_funcs[i] && crtc_funcs[i]->atomic_flush)
++			crtc_funcs[i]->atomic_flush(crtc[i]);
++	}
++
++	for (i = 0; i < 2; i++) {
++		if (!crtc[i])
++			continue;
++
++		/* There's no other way to figure out whether the crtc is running. */
++		ret = drm_crtc_vblank_get(crtc[i]);
++		if (ret == 0) {
++			drm_crtc_wait_one_vblank(crtc[i]);
++			drm_crtc_vblank_put(crtc[i]);
++		}
++
++		ret = 0;
++	}
++
++	if (plane_funcs->cleanup_fb && old_fb)
++		plane_funcs->cleanup_fb(plane, old_fb);
++out:
++	if (plane_state) {
++		if (plane->funcs->atomic_destroy_state)
++			plane->funcs->atomic_destroy_state(plane, plane_state);
++		else
++			drm_atomic_helper_plane_destroy_state(plane, plane_state);
++	}
++
++	return ret;
++}
++
++/**
++ * drm_plane_helper_update() - Helper for primary plane update
++ * @plane: plane object to update
++ * @crtc: owning CRTC of owning plane
++ * @fb: framebuffer to flip onto plane
++ * @crtc_x: x offset of primary plane on crtc
++ * @crtc_y: y offset of primary plane on crtc
++ * @crtc_w: width of primary plane rectangle on crtc
++ * @crtc_h: height of primary plane rectangle on crtc
++ * @src_x: x offset of @fb for panning
++ * @src_y: y offset of @fb for panning
++ * @src_w: width of source rectangle in @fb
++ * @src_h: height of source rectangle in @fb
++ *
++ * Provides a default plane update handler using the atomic plane update
++ * functions. It is fully left to the driver to check plane constraints and
++ * handle corner-cases like a fully occluded or otherwise invisible plane.
++ *
++ * This is useful for piecewise transitioning of a driver to the atomic helpers.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int drm_plane_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
++			    struct drm_framebuffer *fb,
++			    int crtc_x, int crtc_y,
++			    unsigned int crtc_w, unsigned int crtc_h,
++			    uint32_t src_x, uint32_t src_y,
++			    uint32_t src_w, uint32_t src_h)
++{
++	struct drm_plane_state *plane_state;
++
++	if (plane->funcs->atomic_duplicate_state)
++		plane_state = plane->funcs->atomic_duplicate_state(plane);
++	else if (plane->state)
++		plane_state = drm_atomic_helper_plane_duplicate_state(plane);
++	else
++		plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
++	if (!plane_state)
++		return -ENOMEM;
++
++	plane_state->crtc = crtc;
++	drm_atomic_set_fb_for_plane(plane_state, fb);
++	plane_state->crtc_x = crtc_x;
++	plane_state->crtc_y = crtc_y;
++	plane_state->crtc_h = crtc_h;
++	plane_state->crtc_w = crtc_w;
++	plane_state->src_x = src_x;
++	plane_state->src_y = src_y;
++	plane_state->src_h = src_h;
++	plane_state->src_w = src_w;
++
++	return drm_plane_helper_commit(plane, plane_state, plane->fb);
++}
++EXPORT_SYMBOL(drm_plane_helper_update);
++
++/**
++ * drm_plane_helper_disable() - Helper for primary plane disable
++ * @plane: plane to disable
++ *
++ * Provides a default plane disable handler using the atomic plane update
++ * functions. It is fully left to the driver to check plane constraints and
++ * handle corner-cases like a fully occluded or otherwise invisible plane.
++ *
++ * This is useful for piecewise transitioning of a driver to the atomic helpers.
++ *
++ * RETURNS:
++ * Zero on success, error code on failure
++ */
++int drm_plane_helper_disable(struct drm_plane *plane)
++{
++	struct drm_plane_state *plane_state;
++
++	/* crtc helpers love to call disable functions for already disabled hw
++	 * functions. So cope with that. */
++	if (!plane->crtc)
++		return 0;
++
++	if (plane->funcs->atomic_duplicate_state)
++		plane_state = plane->funcs->atomic_duplicate_state(plane);
++	else if (plane->state)
++		plane_state = drm_atomic_helper_plane_duplicate_state(plane);
++	else
++		plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
++	if (!plane_state)
++		return -ENOMEM;
++
++	plane_state->crtc = NULL;
++	drm_atomic_set_fb_for_plane(plane_state, NULL);
++
++	return drm_plane_helper_commit(plane, plane_state, plane->fb);
++}
++EXPORT_SYMBOL(drm_plane_helper_disable);
+diff -Naur a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c
+--- a/drivers/gpu/drm/drm_platform.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_platform.c	2015-03-26 14:42:38.734435422 +0530
+@@ -64,89 +64,43 @@
+ 	return 0;
+ 
+ err_free:
+-	drm_dev_free(dev);
++	drm_dev_unref(dev);
+ 	return ret;
+ }
+ 
+-static int drm_platform_get_irq(struct drm_device *dev)
++int drm_platform_set_busid(struct drm_device *dev, struct drm_master *master)
+ {
+-	return platform_get_irq(dev->platformdev, 0);
+-}
+-
+-static const char *drm_platform_get_name(struct drm_device *dev)
+-{
+-	return dev->platformdev->name;
+-}
+-
+-static int drm_platform_set_busid(struct drm_device *dev, struct drm_master *master)
+-{
+-	int len, ret, id;
+-
+-	master->unique_len = 13 + strlen(dev->platformdev->name);
+-	master->unique_size = master->unique_len;
+-	master->unique = kmalloc(master->unique_len + 1, GFP_KERNEL);
+-
+-	if (master->unique == NULL)
+-		return -ENOMEM;
++	int id;
+ 
+ 	id = dev->platformdev->id;
+-
+-	/* if only a single instance of the platform device, id will be
+-	 * set to -1.. use 0 instead to avoid a funny looking bus-id:
+-	 */
+-	if (id == -1)
++	if (id < 0)
+ 		id = 0;
+ 
+-	len = snprintf(master->unique, master->unique_len,
+-			"platform:%s:%02d", dev->platformdev->name, id);
+-
+-	if (len > master->unique_len) {
+-		DRM_ERROR("Unique buffer overflowed\n");
+-		ret = -EINVAL;
+-		goto err;
+-	}
+-
+-	dev->devname =
+-		kmalloc(strlen(dev->platformdev->name) +
+-			master->unique_len + 2, GFP_KERNEL);
+-
+-	if (dev->devname == NULL) {
+-		ret = -ENOMEM;
+-		goto err;
+-	}
++	master->unique = kasprintf(GFP_KERNEL, "platform:%s:%02d",
++						dev->platformdev->name, id);
++	if (!master->unique)
++		return -ENOMEM;
+ 
+-	sprintf(dev->devname, "%s@%s", dev->platformdev->name,
+-		master->unique);
++	master->unique_len = strlen(master->unique);
+ 	return 0;
+-err:
+-	return ret;
+ }
+-
+-static struct drm_bus drm_platform_bus = {
+-	.bus_type = DRIVER_BUS_PLATFORM,
+-	.get_irq = drm_platform_get_irq,
+-	.get_name = drm_platform_get_name,
+-	.set_busid = drm_platform_set_busid,
+-};
++EXPORT_SYMBOL(drm_platform_set_busid);
+ 
+ /**
+- * Platform device initialization. Called direct from modules.
++ * drm_platform_init - Register a platform device with the DRM subsystem
++ * @driver: DRM device driver
++ * @platform_device: platform device to register
+  *
+- * \return zero on success or a negative number on failure.
++ * Registers the specified DRM device driver and platform device with the DRM
++ * subsystem, initializing a drm_device structure and calling the driver's
++ * .load() function.
+  *
+- * Initializes a drm_device structures,registering the
+- * stubs
+- *
+- * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
+- * after the initialization for driver customization.
++ * Return: 0 on success or a negative error code on failure.
+  */
+-
+ int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device)
+ {
+ 	DRM_DEBUG("\n");
+ 
+-	driver->kdriver.platform_device = platform_device;
+-	driver->bus = &drm_platform_bus;
+ 	return drm_get_platform_dev(platform_device, driver);
+ }
+ EXPORT_SYMBOL(drm_platform_init);
+diff -Naur a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+--- a/drivers/gpu/drm/drm_prime.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_prime.c	2015-03-26 14:42:38.734435422 +0530
+@@ -29,6 +29,9 @@
+ #include <linux/export.h>
+ #include <linux/dma-buf.h>
+ #include <drm/drmP.h>
++#include <drm/drm_gem.h>
++
++#include "drm_internal.h"
+ 
+ /*
+  * DMA-BUF/GEM Object references and lifetime overview:
+@@ -68,7 +71,8 @@
+ 	enum dma_data_direction dir;
+ };
+ 
+-static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t handle)
++static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
++				    struct dma_buf *dma_buf, uint32_t handle)
+ {
+ 	struct drm_prime_member *member;
+ 
+@@ -174,7 +178,7 @@
+ }
+ 
+ static struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment *attach,
+-		enum dma_data_direction dir)
++					    enum dma_data_direction dir)
+ {
+ 	struct drm_prime_attachment *prime_attach = attach->priv;
+ 	struct drm_gem_object *obj = attach->dmabuf->priv;
+@@ -211,11 +215,19 @@
+ }
+ 
+ static void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
+-		struct sg_table *sgt, enum dma_data_direction dir)
++				  struct sg_table *sgt,
++				  enum dma_data_direction dir)
+ {
+ 	/* nothing to be done here */
+ }
+ 
++/**
++ * drm_gem_dmabuf_release - dma_buf release implementation for GEM
++ * @dma_buf: buffer to be released
++ *
++ * Generic release function for dma_bufs exported as PRIME buffers. GEM drivers
++ * must use this in their dma_buf ops structure as the release callback.
++ */
+ void drm_gem_dmabuf_release(struct dma_buf *dma_buf)
+ {
+ 	struct drm_gem_object *obj = dma_buf->priv;
+@@ -242,30 +254,30 @@
+ }
+ 
+ static void *drm_gem_dmabuf_kmap_atomic(struct dma_buf *dma_buf,
+-		unsigned long page_num)
++					unsigned long page_num)
+ {
+ 	return NULL;
+ }
+ 
+ static void drm_gem_dmabuf_kunmap_atomic(struct dma_buf *dma_buf,
+-		unsigned long page_num, void *addr)
++					 unsigned long page_num, void *addr)
+ {
+ 
+ }
+ static void *drm_gem_dmabuf_kmap(struct dma_buf *dma_buf,
+-		unsigned long page_num)
++				 unsigned long page_num)
+ {
+ 	return NULL;
+ }
+ 
+ static void drm_gem_dmabuf_kunmap(struct dma_buf *dma_buf,
+-		unsigned long page_num, void *addr)
++				  unsigned long page_num, void *addr)
+ {
+ 
+ }
+ 
+ static int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf,
+-		struct vm_area_struct *vma)
++			       struct vm_area_struct *vma)
+ {
+ 	struct drm_gem_object *obj = dma_buf->priv;
+ 	struct drm_device *dev = obj->dev;
+@@ -315,10 +327,25 @@
+  *    driver's scatter/gather table
+  */
+ 
++/**
++ * drm_gem_prime_export - helper library implementation of the export callback
++ * @dev: drm_device to export from
++ * @obj: GEM object to export
++ * @flags: flags like DRM_CLOEXEC
++ *
++ * This is the implementation of the gem_prime_export functions for GEM drivers
++ * using the PRIME helpers.
++ */
+ struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
+ 				     struct drm_gem_object *obj, int flags)
+ {
+-	return dma_buf_export(obj, &drm_gem_prime_dmabuf_ops, obj->size, flags);
++	struct reservation_object *robj = NULL;
++
++	if (dev->driver->gem_prime_res_obj)
++		robj = dev->driver->gem_prime_res_obj(obj);
++
++	return dma_buf_export(obj, &drm_gem_prime_dmabuf_ops, obj->size,
++			      flags);
+ }
+ EXPORT_SYMBOL(drm_gem_prime_export);
+ 
+@@ -355,9 +382,23 @@
+ 	return dmabuf;
+ }
+ 
++/**
++ * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers
++ * @dev: dev to export the buffer from
++ * @file_priv: drm file-private structure
++ * @handle: buffer handle to export
++ * @flags: flags like DRM_CLOEXEC
++ * @prime_fd: pointer to storage for the fd id of the create dma-buf
++ *
++ * This is the PRIME export function which must be used mandatorily by GEM
++ * drivers to ensure correct lifetime management of the underlying GEM object.
++ * The actual exporting from GEM object to a dma-buf is done through the
++ * gem_prime_export driver callback.
++ */
+ int drm_gem_prime_handle_to_fd(struct drm_device *dev,
+-		struct drm_file *file_priv, uint32_t handle, uint32_t flags,
+-		int *prime_fd)
++			       struct drm_file *file_priv, uint32_t handle,
++			       uint32_t flags,
++			       int *prime_fd)
+ {
+ 	struct drm_gem_object *obj;
+ 	int ret = 0;
+@@ -441,6 +482,14 @@
+ }
+ EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
+ 
++/**
++ * drm_gem_prime_import - helper library implementation of the import callback
++ * @dev: drm_device to import into
++ * @dma_buf: dma-buf object to import
++ *
++ * This is the implementation of the gem_prime_import functions for GEM drivers
++ * using the PRIME helpers.
++ */
+ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
+ 					    struct dma_buf *dma_buf)
+ {
+@@ -471,12 +520,12 @@
+ 	get_dma_buf(dma_buf);
+ 
+ 	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
+-	if (IS_ERR_OR_NULL(sgt)) {
++	if (IS_ERR(sgt)) {
+ 		ret = PTR_ERR(sgt);
+ 		goto fail_detach;
+ 	}
+ 
+-	obj = dev->driver->gem_prime_import_sg_table(dev, dma_buf->size, sgt);
++	obj = dev->driver->gem_prime_import_sg_table(dev, attach, sgt);
+ 	if (IS_ERR(obj)) {
+ 		ret = PTR_ERR(obj);
+ 		goto fail_unmap;
+@@ -496,8 +545,21 @@
+ }
+ EXPORT_SYMBOL(drm_gem_prime_import);
+ 
++/**
++ * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers
++ * @dev: dev to export the buffer from
++ * @file_priv: drm file-private structure
++ * @prime_fd: fd id of the dma-buf which should be imported
++ * @handle: pointer to storage for the handle of the imported buffer object
++ *
++ * This is the PRIME import function which must be used mandatorily by GEM
++ * drivers to ensure correct lifetime management of the underlying GEM object.
++ * The actual importing of GEM object from the dma-buf is done through the
++ * gem_import_export driver callback.
++ */
+ int drm_gem_prime_fd_to_handle(struct drm_device *dev,
+-		struct drm_file *file_priv, int prime_fd, uint32_t *handle)
++			       struct drm_file *file_priv, int prime_fd,
++			       uint32_t *handle)
+ {
+ 	struct dma_buf *dma_buf;
+ 	struct drm_gem_object *obj;
+@@ -598,14 +660,16 @@
+ 			args->fd, &args->handle);
+ }
+ 
+-/*
+- * drm_prime_pages_to_sg
++/**
++ * drm_prime_pages_to_sg - converts a page array into an sg list
++ * @pages: pointer to the array of page pointers to convert
++ * @nr_pages: length of the page vector
+  *
+- * this helper creates an sg table object from a set of pages
++ * This helper creates an sg table object from a set of pages
+  * the driver is responsible for mapping the pages into the
+- * importers address space
++ * importers address space for use with dma_buf itself.
+  */
+-struct sg_table *drm_prime_pages_to_sg(struct page **pages, int nr_pages)
++struct sg_table *drm_prime_pages_to_sg(struct page **pages, unsigned int nr_pages)
+ {
+ 	struct sg_table *sg = NULL;
+ 	int ret;
+@@ -628,9 +692,16 @@
+ }
+ EXPORT_SYMBOL(drm_prime_pages_to_sg);
+ 
+-/* export an sg table into an array of pages and addresses
+-   this is currently required by the TTM driver in order to do correct fault
+-   handling */
++/**
++ * drm_prime_sg_to_page_addr_arrays - convert an sg table into a page array
++ * @sgt: scatter-gather table to convert
++ * @pages: array of page pointers to store the page array in
++ * @addrs: optional array to store the dma bus address of each page
++ * @max_pages: size of both the passed-in arrays
++ *
++ * Exports an sg table into an array of pages and addresses. This is currently
++ * required by the TTM driver in order to do correct fault handling.
++ */
+ int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
+ 				     dma_addr_t *addrs, int max_pages)
+ {
+@@ -663,7 +734,15 @@
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_prime_sg_to_page_addr_arrays);
+-/* helper function to cleanup a GEM/prime object */
++
++/**
++ * drm_prime_gem_destroy - helper to clean up a PRIME-imported GEM object
++ * @obj: GEM object which was created from a dma-buf
++ * @sg: the sg-table which was pinned at import time
++ *
++ * This is the cleanup functions which GEM drivers need to call when they use
++ * @drm_gem_prime_import to import dma-bufs.
++ */
+ void drm_prime_gem_destroy(struct drm_gem_object *obj, struct sg_table *sg)
+ {
+ 	struct dma_buf_attachment *attach;
+@@ -683,11 +762,9 @@
+ 	INIT_LIST_HEAD(&prime_fpriv->head);
+ 	mutex_init(&prime_fpriv->lock);
+ }
+-EXPORT_SYMBOL(drm_prime_init_file_private);
+ 
+ void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv)
+ {
+ 	/* by now drm_gem_release should've made sure the list is empty */
+ 	WARN_ON(!list_empty(&prime_fpriv->head));
+ }
+-EXPORT_SYMBOL(drm_prime_destroy_file_private);
+diff -Naur a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
+--- a/drivers/gpu/drm/drm_probe_helper.c	1970-01-01 05:30:00.000000000 +0530
++++ b/drivers/gpu/drm/drm_probe_helper.c	2015-03-26 14:42:38.738435422 +0530
+@@ -0,0 +1,473 @@
++/*
++ * Copyright (c) 2006-2008 Intel Corporation
++ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
++ *
++ * DRM core CRTC related functions
++ *
++ * Permission to use, copy, modify, distribute, and sell this software and its
++ * documentation for any purpose is hereby granted without fee, provided that
++ * the above copyright notice appear in all copies and that both that copyright
++ * notice and this permission notice appear in supporting documentation, and
++ * that the name of the copyright holders not be used in advertising or
++ * publicity pertaining to distribution of the software without specific,
++ * written prior permission.  The copyright holders make no representations
++ * about the suitability of this software for any purpose.  It is provided "as
++ * is" without express or implied warranty.
++ *
++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
++ * OF THIS SOFTWARE.
++ *
++ * Authors:
++ *      Keith Packard
++ *	Eric Anholt <eric@anholt.net>
++ *      Dave Airlie <airlied@linux.ie>
++ *      Jesse Barnes <jesse.barnes@intel.com>
++ */
++
++#include <linux/export.h>
++#include <linux/moduleparam.h>
++
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_fourcc.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_fb_helper.h>
++#include <drm/drm_edid.h>
++
++/**
++ * DOC: output probing helper overview
++ *
++ * This library provides some helper code for output probing. It provides an
++ * implementation of the core connector->fill_modes interface with
++ * drm_helper_probe_single_connector_modes.
++ *
++ * It also provides support for polling connectors with a work item and for
++ * generic hotplug interrupt handling where the driver doesn't or cannot keep
++ * track of a per-connector hpd interrupt.
++ *
++ * This helper library can be used independently of the modeset helper library.
++ * Drivers can also overwrite different parts e.g. use their own hotplug
++ * handling code to avoid probing unrelated outputs.
++ */
++
++static bool drm_kms_helper_poll = true;
++module_param_named(poll, drm_kms_helper_poll, bool, 0600);
++
++static void drm_mode_validate_flag(struct drm_connector *connector,
++				   int flags)
++{
++	struct drm_display_mode *mode;
++
++	if (flags == (DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_INTERLACE |
++		      DRM_MODE_FLAG_3D_MASK))
++		return;
++
++	list_for_each_entry(mode, &connector->modes, head) {
++		if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
++				!(flags & DRM_MODE_FLAG_INTERLACE))
++			mode->status = MODE_NO_INTERLACE;
++		if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) &&
++				!(flags & DRM_MODE_FLAG_DBLSCAN))
++			mode->status = MODE_NO_DBLESCAN;
++		if ((mode->flags & DRM_MODE_FLAG_3D_MASK) &&
++				!(flags & DRM_MODE_FLAG_3D_MASK))
++			mode->status = MODE_NO_STEREO;
++	}
++
++	return;
++}
++
++static int drm_helper_probe_add_cmdline_mode(struct drm_connector *connector)
++{
++	struct drm_display_mode *mode;
++
++	if (!connector->cmdline_mode.specified)
++		return 0;
++
++	mode = drm_mode_create_from_cmdline_mode(connector->dev,
++						 &connector->cmdline_mode);
++	if (mode == NULL)
++		return 0;
++
++	drm_mode_probed_add(connector, mode);
++	return 1;
++}
++
++static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connector *connector,
++							      uint32_t maxX, uint32_t maxY, bool merge_type_bits)
++{
++	struct drm_device *dev = connector->dev;
++	struct drm_display_mode *mode;
++	struct drm_connector_helper_funcs *connector_funcs =
++		connector->helper_private;
++	int count = 0;
++	int mode_flags = 0;
++	bool verbose_prune = true;
++
++	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
++
++	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
++			connector->name);
++	/* set all modes to the unverified state */
++	list_for_each_entry(mode, &connector->modes, head)
++		mode->status = MODE_UNVERIFIED;
++
++	if (connector->force) {
++		if (connector->force == DRM_FORCE_ON ||
++		    connector->force == DRM_FORCE_ON_DIGITAL)
++			connector->status = connector_status_connected;
++		else
++			connector->status = connector_status_disconnected;
++		if (connector->funcs->force)
++			connector->funcs->force(connector);
++	} else {
++		connector->status = connector->funcs->detect(connector, true);
++	}
++
++	/* Re-enable polling in case the global poll config changed. */
++	if (drm_kms_helper_poll != dev->mode_config.poll_running)
++		drm_kms_helper_poll_enable(dev);
++
++	dev->mode_config.poll_running = drm_kms_helper_poll;
++
++	if (connector->status == connector_status_disconnected) {
++		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] disconnected\n",
++			connector->base.id, connector->name);
++		drm_mode_connector_update_edid_property(connector, NULL);
++		verbose_prune = false;
++		goto prune;
++	}
++
++#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
++	count = drm_load_edid_firmware(connector);
++	if (count == 0)
++#endif
++	{
++		if (connector->override_edid) {
++			struct edid *edid = (struct edid *) connector->edid_blob_ptr->data;
++
++			count = drm_add_edid_modes(connector, edid);
++		} else
++			count = (*connector_funcs->get_modes)(connector);
++	}
++
++	if (count == 0 && connector->status == connector_status_connected)
++		count = drm_add_modes_noedid(connector, 1024, 768);
++	count += drm_helper_probe_add_cmdline_mode(connector);
++	if (count == 0)
++		goto prune;
++
++	drm_mode_connector_list_update(connector, merge_type_bits);
++
++	if (maxX && maxY)
++		drm_mode_validate_size(dev, &connector->modes, maxX, maxY);
++
++	if (connector->interlace_allowed)
++		mode_flags |= DRM_MODE_FLAG_INTERLACE;
++	if (connector->doublescan_allowed)
++		mode_flags |= DRM_MODE_FLAG_DBLSCAN;
++	if (connector->stereo_allowed)
++		mode_flags |= DRM_MODE_FLAG_3D_MASK;
++	drm_mode_validate_flag(connector, mode_flags);
++
++	list_for_each_entry(mode, &connector->modes, head) {
++		if (mode->status == MODE_OK && connector_funcs->mode_valid)
++			mode->status = connector_funcs->mode_valid(connector,
++								   mode);
++	}
++
++prune:
++	drm_mode_prune_invalid(dev, &connector->modes, verbose_prune);
++
++	if (list_empty(&connector->modes))
++		return 0;
++
++	list_for_each_entry(mode, &connector->modes, head)
++		mode->vrefresh = drm_mode_vrefresh(mode);
++
++	drm_mode_sort(&connector->modes);
++
++	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed modes :\n", connector->base.id,
++			connector->name);
++	list_for_each_entry(mode, &connector->modes, head) {
++		drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
++		drm_mode_debug_printmodeline(mode);
++	}
++
++	return count;
++}
++
++/**
++ * drm_helper_probe_single_connector_modes - get complete set of display modes
++ * @connector: connector to probe
++ * @maxX: max width for modes
++ * @maxY: max height for modes
++ *
++ * Based on the helper callbacks implemented by @connector try to detect all
++ * valid modes.  Modes will first be added to the connector's probed_modes list,
++ * then culled (based on validity and the @maxX, @maxY parameters) and put into
++ * the normal modes list.
++ *
++ * Intended to be use as a generic implementation of the ->fill_modes()
++ * @connector vfunc for drivers that use the crtc helpers for output mode
++ * filtering and detection.
++ *
++ * Returns:
++ * The number of modes found on @connector.
++ */
++int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
++					    uint32_t maxX, uint32_t maxY)
++{
++	return drm_helper_probe_single_connector_modes_merge_bits(connector, maxX, maxY, true);
++}
++EXPORT_SYMBOL(drm_helper_probe_single_connector_modes);
++
++/**
++ * drm_helper_probe_single_connector_modes_nomerge - get complete set of display modes
++ * @connector: connector to probe
++ * @maxX: max width for modes
++ * @maxY: max height for modes
++ *
++ * This operates like drm_hehlper_probe_single_connector_modes except it
++ * replaces the mode bits instead of merging them for preferred modes.
++ */
++int drm_helper_probe_single_connector_modes_nomerge(struct drm_connector *connector,
++					    uint32_t maxX, uint32_t maxY)
++{
++	return drm_helper_probe_single_connector_modes_merge_bits(connector, maxX, maxY, false);
++}
++EXPORT_SYMBOL(drm_helper_probe_single_connector_modes_nomerge);
++
++/**
++ * drm_kms_helper_hotplug_event - fire off KMS hotplug events
++ * @dev: drm_device whose connector state changed
++ *
++ * This function fires off the uevent for userspace and also calls the
++ * output_poll_changed function, which is most commonly used to inform the fbdev
++ * emulation code and allow it to update the fbcon output configuration.
++ *
++ * Drivers should call this from their hotplug handling code when a change is
++ * detected. Note that this function does not do any output detection of its
++ * own, like drm_helper_hpd_irq_event() does - this is assumed to be done by the
++ * driver already.
++ *
++ * This function must be called from process context with no mode
++ * setting locks held.
++ */
++void drm_kms_helper_hotplug_event(struct drm_device *dev)
++{
++	/* send a uevent + call fbdev */
++	drm_sysfs_hotplug_event(dev);
++	if (dev->mode_config.funcs->output_poll_changed)
++		dev->mode_config.funcs->output_poll_changed(dev);
++}
++EXPORT_SYMBOL(drm_kms_helper_hotplug_event);
++
++#define DRM_OUTPUT_POLL_PERIOD (10*HZ)
++static void output_poll_execute(struct work_struct *work)
++{
++	struct delayed_work *delayed_work = to_delayed_work(work);
++	struct drm_device *dev = container_of(delayed_work, struct drm_device, mode_config.output_poll_work);
++	struct drm_connector *connector;
++	enum drm_connector_status old_status;
++	bool repoll = false, changed = false;
++
++	if (!drm_kms_helper_poll)
++		return;
++
++	mutex_lock(&dev->mode_config.mutex);
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++
++		/* Ignore forced connectors. */
++		if (connector->force)
++			continue;
++
++		/* Ignore HPD capable connectors and connectors where we don't
++		 * want any hotplug detection at all for polling. */
++		if (!connector->polled || connector->polled == DRM_CONNECTOR_POLL_HPD)
++			continue;
++
++		repoll = true;
++
++		old_status = connector->status;
++		/* if we are connected and don't want to poll for disconnect
++		   skip it */
++		if (old_status == connector_status_connected &&
++		    !(connector->polled & DRM_CONNECTOR_POLL_DISCONNECT))
++			continue;
++
++		connector->status = connector->funcs->detect(connector, false);
++		if (old_status != connector->status) {
++			const char *old, *new;
++
++			old = drm_get_connector_status_name(old_status);
++			new = drm_get_connector_status_name(connector->status);
++
++			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] "
++				      "status updated from %s to %s\n",
++				      connector->base.id,
++				      connector->name,
++				      old, new);
++
++			changed = true;
++		}
++	}
++
++	mutex_unlock(&dev->mode_config.mutex);
++
++	if (changed)
++		drm_kms_helper_hotplug_event(dev);
++
++	if (repoll)
++		schedule_delayed_work(delayed_work, DRM_OUTPUT_POLL_PERIOD);
++}
++
++/**
++ * drm_kms_helper_poll_disable - disable output polling
++ * @dev: drm_device
++ *
++ * This function disables the output polling work.
++ *
++ * Drivers can call this helper from their device suspend implementation. It is
++ * not an error to call this even when output polling isn't enabled or arlready
++ * disabled.
++ */
++void drm_kms_helper_poll_disable(struct drm_device *dev)
++{
++	if (!dev->mode_config.poll_enabled)
++		return;
++	cancel_delayed_work_sync(&dev->mode_config.output_poll_work);
++}
++EXPORT_SYMBOL(drm_kms_helper_poll_disable);
++
++/**
++ * drm_kms_helper_poll_enable - re-enable output polling.
++ * @dev: drm_device
++ *
++ * This function re-enables the output polling work.
++ *
++ * Drivers can call this helper from their device resume implementation. It is
++ * an error to call this when the output polling support has not yet been set
++ * up.
++ */
++void drm_kms_helper_poll_enable(struct drm_device *dev)
++{
++	bool poll = false;
++	struct drm_connector *connector;
++
++	if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll)
++		return;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		if (connector->polled & (DRM_CONNECTOR_POLL_CONNECT |
++					 DRM_CONNECTOR_POLL_DISCONNECT))
++			poll = true;
++	}
++
++	if (poll)
++		schedule_delayed_work(&dev->mode_config.output_poll_work, DRM_OUTPUT_POLL_PERIOD);
++}
++EXPORT_SYMBOL(drm_kms_helper_poll_enable);
++
++/**
++ * drm_kms_helper_poll_init - initialize and enable output polling
++ * @dev: drm_device
++ *
++ * This function intializes and then also enables output polling support for
++ * @dev. Drivers which do not have reliable hotplug support in hardware can use
++ * this helper infrastructure to regularly poll such connectors for changes in
++ * their connection state.
++ *
++ * Drivers can control which connectors are polled by setting the
++ * DRM_CONNECTOR_POLL_CONNECT and DRM_CONNECTOR_POLL_DISCONNECT flags. On
++ * connectors where probing live outputs can result in visual distortion drivers
++ * should not set the DRM_CONNECTOR_POLL_DISCONNECT flag to avoid this.
++ * Connectors which have no flag or only DRM_CONNECTOR_POLL_HPD set are
++ * completely ignored by the polling logic.
++ *
++ * Note that a connector can be both polled and probed from the hotplug handler,
++ * in case the hotplug interrupt is known to be unreliable.
++ */
++void drm_kms_helper_poll_init(struct drm_device *dev)
++{
++	INIT_DELAYED_WORK(&dev->mode_config.output_poll_work, output_poll_execute);
++	dev->mode_config.poll_enabled = true;
++
++	drm_kms_helper_poll_enable(dev);
++}
++EXPORT_SYMBOL(drm_kms_helper_poll_init);
++
++/**
++ * drm_kms_helper_poll_fini - disable output polling and clean it up
++ * @dev: drm_device
++ */
++void drm_kms_helper_poll_fini(struct drm_device *dev)
++{
++	drm_kms_helper_poll_disable(dev);
++}
++EXPORT_SYMBOL(drm_kms_helper_poll_fini);
++
++/**
++ * drm_helper_hpd_irq_event - hotplug processing
++ * @dev: drm_device
++ *
++ * Drivers can use this helper function to run a detect cycle on all connectors
++ * which have the DRM_CONNECTOR_POLL_HPD flag set in their &polled member. All
++ * other connectors are ignored, which is useful to avoid reprobing fixed
++ * panels.
++ *
++ * This helper function is useful for drivers which can't or don't track hotplug
++ * interrupts for each connector.
++ *
++ * Drivers which support hotplug interrupts for each connector individually and
++ * which have a more fine-grained detect logic should bypass this code and
++ * directly call drm_kms_helper_hotplug_event() in case the connector state
++ * changed.
++ *
++ * This function must be called from process context with no mode
++ * setting locks held.
++ *
++ * Note that a connector can be both polled and probed from the hotplug handler,
++ * in case the hotplug interrupt is known to be unreliable.
++ */
++bool drm_helper_hpd_irq_event(struct drm_device *dev)
++{
++	struct drm_connector *connector;
++	enum drm_connector_status old_status;
++	bool changed = false;
++
++	if (!dev->mode_config.poll_enabled)
++		return false;
++
++	mutex_lock(&dev->mode_config.mutex);
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++
++		/* Only handle HPD capable connectors. */
++		if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
++			continue;
++
++		old_status = connector->status;
++
++		connector->status = connector->funcs->detect(connector, false);
++		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
++			      connector->base.id,
++			      connector->name,
++			      drm_get_connector_status_name(old_status),
++			      drm_get_connector_status_name(connector->status));
++		if (old_status != connector->status)
++			changed = true;
++	}
++
++	mutex_unlock(&dev->mode_config.mutex);
++
++	if (changed)
++		drm_kms_helper_hotplug_event(dev);
++
++	return changed;
++}
++EXPORT_SYMBOL(drm_helper_hpd_irq_event);
+diff -Naur a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c
+--- a/drivers/gpu/drm/drm_rect.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_rect.c	2015-03-26 14:42:38.738435422 +0530
+@@ -293,3 +293,143 @@
+ 		DRM_DEBUG_KMS("%dx%d%+d%+d\n", w, h, r->x1, r->y1);
+ }
+ EXPORT_SYMBOL(drm_rect_debug_print);
++
++/**
++ * drm_rect_rotate - Rotate the rectangle
++ * @r: rectangle to be rotated
++ * @width: Width of the coordinate space
++ * @height: Height of the coordinate space
++ * @rotation: Transformation to be applied
++ *
++ * Apply @rotation to the coordinates of rectangle @r.
++ *
++ * @width and @height combined with @rotation define
++ * the location of the new origin.
++ *
++ * @width correcsponds to the horizontal and @height
++ * to the vertical axis of the untransformed coordinate
++ * space.
++ */
++void drm_rect_rotate(struct drm_rect *r,
++		     int width, int height,
++		     unsigned int rotation)
++{
++	struct drm_rect tmp;
++
++	if (rotation & (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
++		tmp = *r;
++
++		if (rotation & BIT(DRM_REFLECT_X)) {
++			r->x1 = width - tmp.x2;
++			r->x2 = width - tmp.x1;
++		}
++
++		if (rotation & BIT(DRM_REFLECT_Y)) {
++			r->y1 = height - tmp.y2;
++			r->y2 = height - tmp.y1;
++		}
++	}
++
++	switch (rotation & 0xf) {
++	case BIT(DRM_ROTATE_0):
++		break;
++	case BIT(DRM_ROTATE_90):
++		tmp = *r;
++		r->x1 = tmp.y1;
++		r->x2 = tmp.y2;
++		r->y1 = width - tmp.x2;
++		r->y2 = width - tmp.x1;
++		break;
++	case BIT(DRM_ROTATE_180):
++		tmp = *r;
++		r->x1 = width - tmp.x2;
++		r->x2 = width - tmp.x1;
++		r->y1 = height - tmp.y2;
++		r->y2 = height - tmp.y1;
++		break;
++	case BIT(DRM_ROTATE_270):
++		tmp = *r;
++		r->x1 = height - tmp.y2;
++		r->x2 = height - tmp.y1;
++		r->y1 = tmp.x1;
++		r->y2 = tmp.x2;
++		break;
++	default:
++		break;
++	}
++}
++EXPORT_SYMBOL(drm_rect_rotate);
++
++/**
++ * drm_rect_rotate_inv - Inverse rotate the rectangle
++ * @r: rectangle to be rotated
++ * @width: Width of the coordinate space
++ * @height: Height of the coordinate space
++ * @rotation: Transformation whose inverse is to be applied
++ *
++ * Apply the inverse of @rotation to the coordinates
++ * of rectangle @r.
++ *
++ * @width and @height combined with @rotation define
++ * the location of the new origin.
++ *
++ * @width correcsponds to the horizontal and @height
++ * to the vertical axis of the original untransformed
++ * coordinate space, so that you never have to flip
++ * them when doing a rotatation and its inverse.
++ * That is, if you do:
++ *
++ * drm_rotate(&r, width, height, rotation);
++ * drm_rotate_inv(&r, width, height, rotation);
++ *
++ * you will always get back the original rectangle.
++ */
++void drm_rect_rotate_inv(struct drm_rect *r,
++			 int width, int height,
++			 unsigned int rotation)
++{
++	struct drm_rect tmp;
++
++	switch (rotation & 0xf) {
++	case BIT(DRM_ROTATE_0):
++		break;
++	case BIT(DRM_ROTATE_90):
++		tmp = *r;
++		r->x1 = width - tmp.y2;
++		r->x2 = width - tmp.y1;
++		r->y1 = tmp.x1;
++		r->y2 = tmp.x2;
++		break;
++	case BIT(DRM_ROTATE_180):
++		tmp = *r;
++		r->x1 = width - tmp.x2;
++		r->x2 = width - tmp.x1;
++		r->y1 = height - tmp.y2;
++		r->y2 = height - tmp.y1;
++		break;
++	case BIT(DRM_ROTATE_270):
++		tmp = *r;
++		r->x1 = tmp.y1;
++		r->x2 = tmp.y2;
++		r->y1 = height - tmp.x2;
++		r->y2 = height - tmp.x1;
++		break;
++	default:
++		break;
++	}
++
++	if (rotation & (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
++		tmp = *r;
++
++		if (rotation & BIT(DRM_REFLECT_X)) {
++			r->x1 = width - tmp.x2;
++			r->x2 = width - tmp.x1;
++		}
++
++		if (rotation & BIT(DRM_REFLECT_Y)) {
++			r->y1 = height - tmp.y2;
++			r->y2 = height - tmp.y1;
++		}
++	}
++}
++EXPORT_SYMBOL(drm_rect_rotate_inv);
+diff -Naur a/drivers/gpu/drm/drm_scatter.c b/drivers/gpu/drm/drm_scatter.c
+--- a/drivers/gpu/drm/drm_scatter.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_scatter.c	2015-03-26 14:42:38.738435422 +0530
+@@ -34,6 +34,7 @@
+ #include <linux/vmalloc.h>
+ #include <linux/slab.h>
+ #include <drm/drmP.h>
++#include "drm_legacy.h"
+ 
+ #define DEBUG_SCATTER 0
+ 
+@@ -78,8 +79,8 @@
+ # define ScatterHandle(x) (unsigned int)(x)
+ #endif
+ 
+-int drm_sg_alloc(struct drm_device *dev, void *data,
+-		 struct drm_file *file_priv)
++int drm_legacy_sg_alloc(struct drm_device *dev, void *data,
++			struct drm_file *file_priv)
+ {
+ 	struct drm_scatter_gather *request = data;
+ 	struct drm_sg_mem *entry;
+@@ -194,8 +195,8 @@
+ 	return -ENOMEM;
+ }
+ 
+-int drm_sg_free(struct drm_device *dev, void *data,
+-		struct drm_file *file_priv)
++int drm_legacy_sg_free(struct drm_device *dev, void *data,
++		       struct drm_file *file_priv)
+ {
+ 	struct drm_scatter_gather *request = data;
+ 	struct drm_sg_mem *entry;
+diff -Naur a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
+--- a/drivers/gpu/drm/drm_stub.c	2015-03-26 14:43:30.398436435 +0530
++++ b/drivers/gpu/drm/drm_stub.c	1970-01-01 05:30:00.000000000 +0530
+@@ -1,607 +0,0 @@
+-/**
+- * \file drm_stub.h
+- * Stub support
+- *
+- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+- */
+-
+-/*
+- * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org
+- *
+- * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California.
+- * All Rights Reserved.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice (including the next
+- * paragraph) shall be included in all copies or substantial portions of the
+- * Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+- * DEALINGS IN THE SOFTWARE.
+- */
+-
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/slab.h>
+-#include <drm/drmP.h>
+-#include <drm/drm_core.h>
+-
+-unsigned int drm_debug = 0;	/* 1 to enable debug output */
+-EXPORT_SYMBOL(drm_debug);
+-
+-unsigned int drm_rnodes = 0;	/* 1 to enable experimental render nodes API */
+-EXPORT_SYMBOL(drm_rnodes);
+-
+-unsigned int drm_vblank_offdelay = 5000;    /* Default to 5000 msecs. */
+-EXPORT_SYMBOL(drm_vblank_offdelay);
+-
+-unsigned int drm_timestamp_precision = 20;  /* Default to 20 usecs. */
+-EXPORT_SYMBOL(drm_timestamp_precision);
+-
+-/*
+- * Default to use monotonic timestamps for wait-for-vblank and page-flip
+- * complete events.
+- */
+-unsigned int drm_timestamp_monotonic = 1;
+-
+-MODULE_AUTHOR(CORE_AUTHOR);
+-MODULE_DESCRIPTION(CORE_DESC);
+-MODULE_LICENSE("GPL and additional rights");
+-MODULE_PARM_DESC(debug, "Enable debug output");
+-MODULE_PARM_DESC(rnodes, "Enable experimental render nodes API");
+-MODULE_PARM_DESC(vblankoffdelay, "Delay until vblank irq auto-disable [msecs]");
+-MODULE_PARM_DESC(timestamp_precision_usec, "Max. error on timestamps [usecs]");
+-MODULE_PARM_DESC(timestamp_monotonic, "Use monotonic timestamps");
+-
+-module_param_named(debug, drm_debug, int, 0600);
+-module_param_named(rnodes, drm_rnodes, int, 0600);
+-module_param_named(vblankoffdelay, drm_vblank_offdelay, int, 0600);
+-module_param_named(timestamp_precision_usec, drm_timestamp_precision, int, 0600);
+-module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
+-
+-struct idr drm_minors_idr;
+-
+-struct class *drm_class;
+-struct dentry *drm_debugfs_root;
+-
+-int drm_err(const char *func, const char *format, ...)
+-{
+-	struct va_format vaf;
+-	va_list args;
+-	int r;
+-
+-	va_start(args, format);
+-
+-	vaf.fmt = format;
+-	vaf.va = &args;
+-
+-	r = printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* %pV", func, &vaf);
+-
+-	va_end(args);
+-
+-	return r;
+-}
+-EXPORT_SYMBOL(drm_err);
+-
+-void drm_ut_debug_printk(unsigned int request_level,
+-			 const char *prefix,
+-			 const char *function_name,
+-			 const char *format, ...)
+-{
+-	struct va_format vaf;
+-	va_list args;
+-
+-	if (drm_debug & request_level) {
+-		va_start(args, format);
+-		vaf.fmt = format;
+-		vaf.va = &args;
+-
+-		if (function_name)
+-			printk(KERN_DEBUG "[%s:%s], %pV", prefix,
+-			       function_name, &vaf);
+-		else
+-			printk(KERN_DEBUG "%pV", &vaf);
+-		va_end(args);
+-	}
+-}
+-EXPORT_SYMBOL(drm_ut_debug_printk);
+-
+-static int drm_minor_get_id(struct drm_device *dev, int type)
+-{
+-	int ret;
+-	int base = 0, limit = 63;
+-
+-	if (type == DRM_MINOR_CONTROL) {
+-		base += 64;
+-		limit = base + 63;
+-	} else if (type == DRM_MINOR_RENDER) {
+-		base += 128;
+-		limit = base + 63;
+-	}
+-
+-	mutex_lock(&dev->struct_mutex);
+-	ret = idr_alloc(&drm_minors_idr, NULL, base, limit, GFP_KERNEL);
+-	mutex_unlock(&dev->struct_mutex);
+-
+-	return ret == -ENOSPC ? -EINVAL : ret;
+-}
+-
+-struct drm_master *drm_master_create(struct drm_minor *minor)
+-{
+-	struct drm_master *master;
+-
+-	master = kzalloc(sizeof(*master), GFP_KERNEL);
+-	if (!master)
+-		return NULL;
+-
+-	kref_init(&master->refcount);
+-	spin_lock_init(&master->lock.spinlock);
+-	init_waitqueue_head(&master->lock.lock_queue);
+-	drm_ht_create(&master->magiclist, DRM_MAGIC_HASH_ORDER);
+-	INIT_LIST_HEAD(&master->magicfree);
+-	master->minor = minor;
+-
+-	list_add_tail(&master->head, &minor->master_list);
+-
+-	return master;
+-}
+-
+-struct drm_master *drm_master_get(struct drm_master *master)
+-{
+-	kref_get(&master->refcount);
+-	return master;
+-}
+-EXPORT_SYMBOL(drm_master_get);
+-
+-static void drm_master_destroy(struct kref *kref)
+-{
+-	struct drm_master *master = container_of(kref, struct drm_master, refcount);
+-	struct drm_magic_entry *pt, *next;
+-	struct drm_device *dev = master->minor->dev;
+-	struct drm_map_list *r_list, *list_temp;
+-
+-	list_del(&master->head);
+-
+-	if (dev->driver->master_destroy)
+-		dev->driver->master_destroy(dev, master);
+-
+-	list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) {
+-		if (r_list->master == master) {
+-			drm_rmmap_locked(dev, r_list->map);
+-			r_list = NULL;
+-		}
+-	}
+-
+-	if (master->unique) {
+-		kfree(master->unique);
+-		master->unique = NULL;
+-		master->unique_len = 0;
+-	}
+-
+-	kfree(dev->devname);
+-	dev->devname = NULL;
+-
+-	list_for_each_entry_safe(pt, next, &master->magicfree, head) {
+-		list_del(&pt->head);
+-		drm_ht_remove_item(&master->magiclist, &pt->hash_item);
+-		kfree(pt);
+-	}
+-
+-	drm_ht_remove(&master->magiclist);
+-
+-	kfree(master);
+-}
+-
+-void drm_master_put(struct drm_master **master)
+-{
+-	kref_put(&(*master)->refcount, drm_master_destroy);
+-	*master = NULL;
+-}
+-EXPORT_SYMBOL(drm_master_put);
+-
+-int drm_setmaster_ioctl(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv)
+-{
+-	int ret = 0;
+-
+-	if (file_priv->is_master)
+-		return 0;
+-
+-	if (file_priv->minor->master && file_priv->minor->master != file_priv->master)
+-		return -EINVAL;
+-
+-	if (!file_priv->master)
+-		return -EINVAL;
+-
+-	if (file_priv->minor->master)
+-		return -EINVAL;
+-
+-	mutex_lock(&dev->struct_mutex);
+-	file_priv->minor->master = drm_master_get(file_priv->master);
+-	file_priv->is_master = 1;
+-	if (dev->driver->master_set) {
+-		ret = dev->driver->master_set(dev, file_priv, false);
+-		if (unlikely(ret != 0)) {
+-			file_priv->is_master = 0;
+-			drm_master_put(&file_priv->minor->master);
+-		}
+-	}
+-	mutex_unlock(&dev->struct_mutex);
+-
+-	return ret;
+-}
+-
+-int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv)
+-{
+-	if (!file_priv->is_master)
+-		return -EINVAL;
+-
+-	if (!file_priv->minor->master)
+-		return -EINVAL;
+-
+-	mutex_lock(&dev->struct_mutex);
+-	if (dev->driver->master_drop)
+-		dev->driver->master_drop(dev, file_priv, false);
+-	drm_master_put(&file_priv->minor->master);
+-	file_priv->is_master = 0;
+-	mutex_unlock(&dev->struct_mutex);
+-	return 0;
+-}
+-
+-/**
+- * drm_get_minor - Allocate and register new DRM minor
+- * @dev: DRM device
+- * @minor: Pointer to where new minor is stored
+- * @type: Type of minor
+- *
+- * Allocate a new minor of the given type and register it. A pointer to the new
+- * minor is returned in @minor.
+- * Caller must hold the global DRM mutex.
+- *
+- * RETURNS:
+- * 0 on success, negative error code on failure.
+- */
+-static int drm_get_minor(struct drm_device *dev, struct drm_minor **minor,
+-			 int type)
+-{
+-	struct drm_minor *new_minor;
+-	int ret;
+-	int minor_id;
+-
+-	DRM_DEBUG("\n");
+-
+-	minor_id = drm_minor_get_id(dev, type);
+-	if (minor_id < 0)
+-		return minor_id;
+-
+-	new_minor = kzalloc(sizeof(struct drm_minor), GFP_KERNEL);
+-	if (!new_minor) {
+-		ret = -ENOMEM;
+-		goto err_idr;
+-	}
+-
+-	new_minor->type = type;
+-	new_minor->device = MKDEV(DRM_MAJOR, minor_id);
+-	new_minor->dev = dev;
+-	new_minor->index = minor_id;
+-	INIT_LIST_HEAD(&new_minor->master_list);
+-
+-	idr_replace(&drm_minors_idr, new_minor, minor_id);
+-
+-#if defined(CONFIG_DEBUG_FS)
+-	ret = drm_debugfs_init(new_minor, minor_id, drm_debugfs_root);
+-	if (ret) {
+-		DRM_ERROR("DRM: Failed to initialize /sys/kernel/debug/dri.\n");
+-		goto err_mem;
+-	}
+-#endif
+-
+-	ret = drm_sysfs_device_add(new_minor);
+-	if (ret) {
+-		printk(KERN_ERR
+-		       "DRM: Error sysfs_device_add.\n");
+-		goto err_debugfs;
+-	}
+-	*minor = new_minor;
+-
+-	DRM_DEBUG("new minor assigned %d\n", minor_id);
+-	return 0;
+-
+-
+-err_debugfs:
+-#if defined(CONFIG_DEBUG_FS)
+-	drm_debugfs_cleanup(new_minor);
+-err_mem:
+-#endif
+-	kfree(new_minor);
+-err_idr:
+-	idr_remove(&drm_minors_idr, minor_id);
+-	*minor = NULL;
+-	return ret;
+-}
+-
+-/**
+- * drm_unplug_minor - Unplug DRM minor
+- * @minor: Minor to unplug
+- *
+- * Unplugs the given DRM minor but keeps the object. So after this returns,
+- * minor->dev is still valid so existing open-files can still access it to get
+- * device information from their drm_file ojects.
+- * If the minor is already unplugged or if @minor is NULL, nothing is done.
+- * The global DRM mutex must be held by the caller.
+- */
+-static void drm_unplug_minor(struct drm_minor *minor)
+-{
+-	if (!minor || !minor->kdev)
+-		return;
+-
+-#if defined(CONFIG_DEBUG_FS)
+-	drm_debugfs_cleanup(minor);
+-#endif
+-
+-	drm_sysfs_device_remove(minor);
+-	idr_remove(&drm_minors_idr, minor->index);
+-}
+-
+-/**
+- * drm_put_minor - Destroy DRM minor
+- * @minor: Minor to destroy
+- *
+- * This calls drm_unplug_minor() on the given minor and then frees it. Nothing
+- * is done if @minor is NULL. It is fine to call this on already unplugged
+- * minors.
+- * The global DRM mutex must be held by the caller.
+- */
+-static void drm_put_minor(struct drm_minor *minor)
+-{
+-	if (!minor)
+-		return;
+-
+-	DRM_DEBUG("release secondary minor %d\n", minor->index);
+-
+-	drm_unplug_minor(minor);
+-	kfree(minor);
+-}
+-
+-/**
+- * Called via drm_exit() at module unload time or when pci device is
+- * unplugged.
+- *
+- * Cleans up all DRM device, calling drm_lastclose().
+- *
+- */
+-void drm_put_dev(struct drm_device *dev)
+-{
+-	DRM_DEBUG("\n");
+-
+-	if (!dev) {
+-		DRM_ERROR("cleanup called no dev\n");
+-		return;
+-	}
+-
+-	drm_dev_unregister(dev);
+-	drm_dev_free(dev);
+-}
+-EXPORT_SYMBOL(drm_put_dev);
+-
+-void drm_unplug_dev(struct drm_device *dev)
+-{
+-	/* for a USB device */
+-	if (drm_core_check_feature(dev, DRIVER_MODESET))
+-		drm_unplug_minor(dev->control);
+-	if (dev->render)
+-		drm_unplug_minor(dev->render);
+-	drm_unplug_minor(dev->primary);
+-
+-	mutex_lock(&drm_global_mutex);
+-
+-	drm_device_set_unplugged(dev);
+-
+-	if (dev->open_count == 0) {
+-		drm_put_dev(dev);
+-	}
+-	mutex_unlock(&drm_global_mutex);
+-}
+-EXPORT_SYMBOL(drm_unplug_dev);
+-
+-/**
+- * drm_dev_alloc - Allocate new drm device
+- * @driver: DRM driver to allocate device for
+- * @parent: Parent device object
+- *
+- * Allocate and initialize a new DRM device. No device registration is done.
+- * Call drm_dev_register() to advertice the device to user space and register it
+- * with other core subsystems.
+- *
+- * RETURNS:
+- * Pointer to new DRM device, or NULL if out of memory.
+- */
+-struct drm_device *drm_dev_alloc(struct drm_driver *driver,
+-				 struct device *parent)
+-{
+-	struct drm_device *dev;
+-	int ret;
+-
+-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+-	if (!dev)
+-		return NULL;
+-
+-	dev->dev = parent;
+-	dev->driver = driver;
+-
+-	INIT_LIST_HEAD(&dev->filelist);
+-	INIT_LIST_HEAD(&dev->ctxlist);
+-	INIT_LIST_HEAD(&dev->vmalist);
+-	INIT_LIST_HEAD(&dev->maplist);
+-	INIT_LIST_HEAD(&dev->vblank_event_list);
+-
+-	spin_lock_init(&dev->count_lock);
+-	spin_lock_init(&dev->event_lock);
+-	mutex_init(&dev->struct_mutex);
+-	mutex_init(&dev->ctxlist_mutex);
+-
+-	if (drm_ht_create(&dev->map_hash, 12))
+-		goto err_free;
+-
+-	ret = drm_ctxbitmap_init(dev);
+-	if (ret) {
+-		DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+-		goto err_ht;
+-	}
+-
+-	if (driver->driver_features & DRIVER_GEM) {
+-		ret = drm_gem_init(dev);
+-		if (ret) {
+-			DRM_ERROR("Cannot initialize graphics execution manager (GEM)\n");
+-			goto err_ctxbitmap;
+-		}
+-	}
+-
+-	return dev;
+-
+-err_ctxbitmap:
+-	drm_ctxbitmap_cleanup(dev);
+-err_ht:
+-	drm_ht_remove(&dev->map_hash);
+-err_free:
+-	kfree(dev);
+-	return NULL;
+-}
+-EXPORT_SYMBOL(drm_dev_alloc);
+-
+-/**
+- * drm_dev_free - Free DRM device
+- * @dev: DRM device to free
+- *
+- * Free a DRM device that has previously been allocated via drm_dev_alloc().
+- * You must not use kfree() instead or you will leak memory.
+- *
+- * This must not be called once the device got registered. Use drm_put_dev()
+- * instead, which then calls drm_dev_free().
+- */
+-void drm_dev_free(struct drm_device *dev)
+-{
+-	drm_put_minor(dev->control);
+-	drm_put_minor(dev->render);
+-	drm_put_minor(dev->primary);
+-
+-	if (dev->driver->driver_features & DRIVER_GEM)
+-		drm_gem_destroy(dev);
+-
+-	drm_ctxbitmap_cleanup(dev);
+-	drm_ht_remove(&dev->map_hash);
+-
+-	kfree(dev->devname);
+-	kfree(dev);
+-}
+-EXPORT_SYMBOL(drm_dev_free);
+-
+-/**
+- * drm_dev_register - Register DRM device
+- * @dev: Device to register
+- *
+- * Register the DRM device @dev with the system, advertise device to user-space
+- * and start normal device operation. @dev must be allocated via drm_dev_alloc()
+- * previously.
+- *
+- * Never call this twice on any device!
+- *
+- * RETURNS:
+- * 0 on success, negative error code on failure.
+- */
+-int drm_dev_register(struct drm_device *dev, unsigned long flags)
+-{
+-	int ret;
+-
+-	mutex_lock(&drm_global_mutex);
+-
+-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+-		ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
+-		if (ret)
+-			goto out_unlock;
+-	}
+-
+-	if (drm_core_check_feature(dev, DRIVER_RENDER) && drm_rnodes) {
+-		ret = drm_get_minor(dev, &dev->render, DRM_MINOR_RENDER);
+-		if (ret)
+-			goto err_control_node;
+-	}
+-
+-	ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY);
+-	if (ret)
+-		goto err_render_node;
+-
+-	if (dev->driver->load) {
+-		ret = dev->driver->load(dev, flags);
+-		if (ret)
+-			goto err_primary_node;
+-	}
+-
+-	/* setup grouping for legacy outputs */
+-	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+-		ret = drm_mode_group_init_legacy_group(dev,
+-				&dev->primary->mode_group);
+-		if (ret)
+-			goto err_unload;
+-	}
+-
+-	ret = 0;
+-	goto out_unlock;
+-
+-err_unload:
+-	if (dev->driver->unload)
+-		dev->driver->unload(dev);
+-err_primary_node:
+-	drm_unplug_minor(dev->primary);
+-err_render_node:
+-	drm_unplug_minor(dev->render);
+-err_control_node:
+-	drm_unplug_minor(dev->control);
+-out_unlock:
+-	mutex_unlock(&drm_global_mutex);
+-	return ret;
+-}
+-EXPORT_SYMBOL(drm_dev_register);
+-
+-/**
+- * drm_dev_unregister - Unregister DRM device
+- * @dev: Device to unregister
+- *
+- * Unregister the DRM device from the system. This does the reverse of
+- * drm_dev_register() but does not deallocate the device. The caller must call
+- * drm_dev_free() to free all resources.
+- */
+-void drm_dev_unregister(struct drm_device *dev)
+-{
+-	struct drm_map_list *r_list, *list_temp;
+-
+-	drm_lastclose(dev);
+-
+-	if (dev->driver->unload)
+-		dev->driver->unload(dev);
+-
+-	if (dev->agp)
+-		drm_pci_agp_destroy(dev);
+-
+-	drm_vblank_cleanup(dev);
+-
+-	list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
+-		drm_rmmap(dev, r_list->map);
+-
+-	drm_unplug_minor(dev->control);
+-	drm_unplug_minor(dev->render);
+-	drm_unplug_minor(dev->primary);
+-}
+-EXPORT_SYMBOL(drm_dev_unregister);
+diff -Naur a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
+--- a/drivers/gpu/drm/drm_sysfs.c	2015-03-26 14:43:30.462436436 +0530
++++ b/drivers/gpu/drm/drm_sysfs.c	2015-03-26 14:42:38.738435422 +0530
+@@ -21,6 +21,7 @@
+ #include <drm/drm_sysfs.h>
+ #include <drm/drm_core.h>
+ #include <drm/drmP.h>
++#include "drm_internal.h"
+ 
+ #define to_drm_minor(d) dev_get_drvdata(d)
+ #define to_drm_connector(d) dev_get_drvdata(d)
+@@ -380,9 +381,9 @@
+ 
+ 	connector->kdev = device_create(drm_class, dev->primary->kdev,
+ 					0, connector, "card%d-%s",
+-					dev->primary->index, drm_get_connector_name(connector));
++					dev->primary->index, connector->name);
+ 	DRM_DEBUG("adding \"%s\" to sysfs\n",
+-		  drm_get_connector_name(connector));
++		  connector->name);
+ 
+ 	if (IS_ERR(connector->kdev)) {
+ 		DRM_ERROR("failed to register connector device: %ld\n", PTR_ERR(connector->kdev));
+@@ -438,7 +439,6 @@
+ out:
+ 	return ret;
+ }
+-EXPORT_SYMBOL(drm_sysfs_connector_add);
+ 
+ /**
+  * drm_sysfs_connector_remove - remove an connector device from sysfs
+@@ -460,7 +460,7 @@
+ 	if (!connector->kdev)
+ 		return;
+ 	DRM_DEBUG("removing \"%s\" from sysfs\n",
+-		  drm_get_connector_name(connector));
++		  connector->name);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(connector_attrs); i++)
+ 		device_remove_file(connector->kdev, &connector_attrs[i]);
+@@ -468,7 +468,6 @@
+ 	device_unregister(connector->kdev);
+ 	connector->kdev = NULL;
+ }
+-EXPORT_SYMBOL(drm_sysfs_connector_remove);
+ 
+ /**
+  * drm_sysfs_hotplug_event - generate a DRM uevent
+@@ -495,71 +494,55 @@
+ }
+ 
+ /**
+- * drm_sysfs_device_add - adds a class device to sysfs for a character driver
+- * @dev: DRM device to be added
+- * @head: DRM head in question
++ * drm_sysfs_minor_alloc() - Allocate sysfs device for given minor
++ * @minor: minor to allocate sysfs device for
+  *
+- * Add a DRM device to the DRM's device model class.  We use @dev's PCI device
+- * as the parent for the Linux device, and make sure it has a file containing
+- * the driver we're using (for userspace compatibility).
++ * This allocates a new sysfs device for @minor and returns it. The device is
++ * not registered nor linked. The caller has to use device_add() and
++ * device_del() to register and unregister it.
++ *
++ * Note that dev_get_drvdata() on the new device will return the minor.
++ * However, the device does not hold a ref-count to the minor nor to the
++ * underlying drm_device. This is unproblematic as long as you access the
++ * private data only in sysfs callbacks. device_del() disables those
++ * synchronously, so they cannot be called after you cleanup a minor.
+  */
+-int drm_sysfs_device_add(struct drm_minor *minor)
++struct device *drm_sysfs_minor_alloc(struct drm_minor *minor)
+ {
+-	char *minor_str;
++	const char *minor_str;
++	struct device *kdev;
+ 	int r;
+ 
+ 	if (minor->type == DRM_MINOR_CONTROL)
+ 		minor_str = "controlD%d";
+-        else if (minor->type == DRM_MINOR_RENDER)
+-                minor_str = "renderD%d";
+-        else
+-                minor_str = "card%d";
+-
+-	minor->kdev = kzalloc(sizeof(*minor->kdev), GFP_KERNEL);
+-	if (!minor->kdev) {
+-		r = -ENOMEM;
+-		goto error;
+-	}
+-
+-	device_initialize(minor->kdev);
+-	minor->kdev->devt = MKDEV(DRM_MAJOR, minor->index);
+-	minor->kdev->class = drm_class;
+-	minor->kdev->type = &drm_sysfs_device_minor;
+-	minor->kdev->parent = minor->dev->dev;
+-	minor->kdev->release = drm_sysfs_release;
+-	dev_set_drvdata(minor->kdev, minor);
++	else if (minor->type == DRM_MINOR_RENDER)
++		minor_str = "renderD%d";
++	else
++		minor_str = "card%d";
++
++	kdev = kzalloc(sizeof(*kdev), GFP_KERNEL);
++	if (!kdev)
++		return ERR_PTR(-ENOMEM);
++
++	device_initialize(kdev);
++	kdev->devt = MKDEV(DRM_MAJOR, minor->index);
++	kdev->class = drm_class;
++	kdev->type = &drm_sysfs_device_minor;
++	kdev->parent = minor->dev->dev;
++	kdev->release = drm_sysfs_release;
++	dev_set_drvdata(kdev, minor);
+ 
+-	r = dev_set_name(minor->kdev, minor_str, minor->index);
++	r = dev_set_name(kdev, minor_str, minor->index);
+ 	if (r < 0)
+-		goto error;
++		goto err_free;
+ 
+-	r = device_add(minor->kdev);
+-	if (r < 0)
+-		goto error;
+-
+-	return 0;
+-
+-error:
+-	DRM_ERROR("device create failed %d\n", r);
+-	put_device(minor->kdev);
+-	return r;
+-}
++	return kdev;
+ 
+-/**
+- * drm_sysfs_device_remove - remove DRM device
+- * @dev: DRM device to remove
+- *
+- * This call unregisters and cleans up a class device that was created with a
+- * call to drm_sysfs_device_add()
+- */
+-void drm_sysfs_device_remove(struct drm_minor *minor)
+-{
+-	if (minor->kdev)
+-		device_unregister(minor->kdev);
+-	minor->kdev = NULL;
++err_free:
++	put_device(kdev);
++	return ERR_PTR(r);
+ }
+ 
+-
+ /**
+  * drm_class_device_register - Register a struct device in the drm class.
+  *
+diff -Naur a/drivers/gpu/drm/drm_usb.c b/drivers/gpu/drm/drm_usb.c
+--- a/drivers/gpu/drm/drm_usb.c	2015-03-26 14:43:30.402436435 +0530
++++ b/drivers/gpu/drm/drm_usb.c	1970-01-01 05:30:00.000000000 +0530
+@@ -1,84 +0,0 @@
+-#include <drm/drmP.h>
+-#include <drm/drm_usb.h>
+-#include <linux/usb.h>
+-#include <linux/module.h>
+-
+-int drm_get_usb_dev(struct usb_interface *interface,
+-		    const struct usb_device_id *id,
+-		    struct drm_driver *driver)
+-{
+-	struct drm_device *dev;
+-	int ret;
+-
+-	DRM_DEBUG("\n");
+-
+-	dev = drm_dev_alloc(driver, &interface->dev);
+-	if (!dev)
+-		return -ENOMEM;
+-
+-	dev->usbdev = interface_to_usbdev(interface);
+-	usb_set_intfdata(interface, dev);
+-
+-	ret = drm_dev_register(dev, 0);
+-	if (ret)
+-		goto err_free;
+-
+-	DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+-		 driver->name, driver->major, driver->minor, driver->patchlevel,
+-		 driver->date, dev->primary->index);
+-
+-	return 0;
+-
+-err_free:
+-	drm_dev_free(dev);
+-	return ret;
+-
+-}
+-EXPORT_SYMBOL(drm_get_usb_dev);
+-
+-static int drm_usb_get_irq(struct drm_device *dev)
+-{
+-	return 0;
+-}
+-
+-static const char *drm_usb_get_name(struct drm_device *dev)
+-{
+-	return "USB";
+-}
+-
+-static int drm_usb_set_busid(struct drm_device *dev,
+-			       struct drm_master *master)
+-{
+-	return 0;
+-}
+-
+-static struct drm_bus drm_usb_bus = {
+-	.bus_type = DRIVER_BUS_USB,
+-	.get_irq = drm_usb_get_irq,
+-	.get_name = drm_usb_get_name,
+-	.set_busid = drm_usb_set_busid,
+-};
+-    
+-int drm_usb_init(struct drm_driver *driver, struct usb_driver *udriver)
+-{
+-	int res;
+-	DRM_DEBUG("\n");
+-
+-	driver->kdriver.usb = udriver;
+-	driver->bus = &drm_usb_bus;
+-
+-	res = usb_register(udriver);
+-	return res;
+-}
+-EXPORT_SYMBOL(drm_usb_init);
+-
+-void drm_usb_exit(struct drm_driver *driver,
+-		  struct usb_driver *udriver)
+-{
+-	usb_deregister(udriver);
+-}
+-EXPORT_SYMBOL(drm_usb_exit);
+-
+-MODULE_AUTHOR("David Airlie");
+-MODULE_DESCRIPTION("USB DRM support");
+-MODULE_LICENSE("GPL and additional rights");
+diff -Naur a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
+--- a/drivers/gpu/drm/drm_vm.c	2015-03-26 14:43:30.422436435 +0530
++++ b/drivers/gpu/drm/drm_vm.c	2015-03-26 14:42:38.738435422 +0530
+@@ -35,10 +35,19 @@
+ 
+ #include <drm/drmP.h>
+ #include <linux/export.h>
++#include <linux/seq_file.h>
+ #if defined(__ia64__)
+ #include <linux/efi.h>
+ #include <linux/slab.h>
+ #endif
++#include <asm/pgtable.h>
++#include "drm_legacy.h"
++
++struct drm_vma_entry {
++	struct list_head head;
++	struct vm_area_struct *vma;
++	pid_t pid;
++};
+ 
+ static void drm_vm_open(struct vm_area_struct *vma);
+ static void drm_vm_close(struct vm_area_struct *vma);
+@@ -48,15 +57,11 @@
+ {
+ 	pgprot_t tmp = vm_get_page_prot(vma->vm_flags);
+ 
+-#if defined(__i386__) || defined(__x86_64__)
++#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__)
+ 	if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))
+ 		tmp = pgprot_noncached(tmp);
+ 	else
+ 		tmp = pgprot_writecombine(tmp);
+-#elif defined(__powerpc__)
+-	pgprot_val(tmp) |= _PAGE_NO_CACHE;
+-	if (map->type == _DRM_REGISTERS)
+-		pgprot_val(tmp) |= _PAGE_GUARDED;
+ #elif defined(__ia64__)
+ 	if (efi_range_is_wc(vma->vm_start, vma->vm_end -
+ 				    vma->vm_start))
+@@ -263,7 +268,7 @@
+ 				dmah.vaddr = map->handle;
+ 				dmah.busaddr = map->offset;
+ 				dmah.size = map->size;
+-				__drm_pci_free(dev, &dmah);
++				__drm_legacy_pci_free(dev, &dmah);
+ 				break;
+ 			}
+ 			kfree(map);
+@@ -412,7 +417,6 @@
+ 		list_add(&vma_entry->head, &dev->vmalist);
+ 	}
+ }
+-EXPORT_SYMBOL_GPL(drm_vm_open_locked);
+ 
+ static void drm_vm_open(struct vm_area_struct *vma)
+ {
+@@ -532,7 +536,7 @@
+  * according to the mapping type and remaps the pages. Finally sets the file
+  * pointer and calls vm_open().
+  */
+-int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma)
++static int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma)
+ {
+ 	struct drm_file *priv = filp->private_data;
+ 	struct drm_device *dev = priv->minor->dev;
+@@ -646,7 +650,7 @@
+ 	return 0;
+ }
+ 
+-int drm_mmap(struct file *filp, struct vm_area_struct *vma)
++int drm_legacy_mmap(struct file *filp, struct vm_area_struct *vma)
+ {
+ 	struct drm_file *priv = filp->private_data;
+ 	struct drm_device *dev = priv->minor->dev;
+@@ -661,4 +665,69 @@
+ 
+ 	return ret;
+ }
+-EXPORT_SYMBOL(drm_mmap);
++EXPORT_SYMBOL(drm_legacy_mmap);
++
++void drm_legacy_vma_flush(struct drm_device *dev)
++{
++	struct drm_vma_entry *vma, *vma_temp;
++
++	/* Clear vma list (only needed for legacy drivers) */
++	list_for_each_entry_safe(vma, vma_temp, &dev->vmalist, head) {
++		list_del(&vma->head);
++		kfree(vma);
++	}
++}
++
++int drm_vma_info(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *) m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct drm_vma_entry *pt;
++	struct vm_area_struct *vma;
++	unsigned long vma_count = 0;
++#if defined(__i386__)
++	unsigned int pgprot;
++#endif
++
++	mutex_lock(&dev->struct_mutex);
++	list_for_each_entry(pt, &dev->vmalist, head)
++		vma_count++;
++
++	seq_printf(m, "vma use count: %lu, high_memory = %pK, 0x%pK\n",
++		   vma_count, high_memory,
++		   (void *)(unsigned long)virt_to_phys(high_memory));
++
++	list_for_each_entry(pt, &dev->vmalist, head) {
++		vma = pt->vma;
++		if (!vma)
++			continue;
++		seq_printf(m,
++			   "\n%5d 0x%pK-0x%pK %c%c%c%c%c%c 0x%08lx000",
++			   pt->pid,
++			   (void *)vma->vm_start, (void *)vma->vm_end,
++			   vma->vm_flags & VM_READ ? 'r' : '-',
++			   vma->vm_flags & VM_WRITE ? 'w' : '-',
++			   vma->vm_flags & VM_EXEC ? 'x' : '-',
++			   vma->vm_flags & VM_MAYSHARE ? 's' : 'p',
++			   vma->vm_flags & VM_LOCKED ? 'l' : '-',
++			   vma->vm_flags & VM_IO ? 'i' : '-',
++			   vma->vm_pgoff);
++
++#if defined(__i386__)
++		pgprot = pgprot_val(vma->vm_page_prot);
++		seq_printf(m, " %c%c%c%c%c%c%c%c%c",
++			   pgprot & _PAGE_PRESENT ? 'p' : '-',
++			   pgprot & _PAGE_RW ? 'w' : 'r',
++			   pgprot & _PAGE_USER ? 'u' : 's',
++			   pgprot & _PAGE_PWT ? 't' : 'b',
++			   pgprot & _PAGE_PCD ? 'u' : 'c',
++			   pgprot & _PAGE_ACCESSED ? 'a' : '-',
++			   pgprot & _PAGE_DIRTY ? 'd' : '-',
++			   pgprot & _PAGE_PSE ? 'm' : 'k',
++			   pgprot & _PAGE_GLOBAL ? 'g' : 'l');
++#endif
++		seq_printf(m, "\n");
++	}
++	mutex_unlock(&dev->struct_mutex);
++	return 0;
++}
+diff -Naur a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
+--- a/drivers/gpu/drm/Makefile	2015-03-26 14:43:51.314436845 +0530
++++ b/drivers/gpu/drm/Makefile	2015-03-26 14:42:38.738435422 +0530
+@@ -6,23 +6,24 @@
+ 
+ drm-y       :=	drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \
+ 		drm_context.o drm_dma.o \
+-		drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \
+-		drm_lock.o drm_memory.o drm_stub.o drm_vm.o \
++		drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \
++		drm_lock.o drm_memory.o drm_drv.o drm_vm.o \
+ 		drm_agpsupport.o drm_scatter.o drm_pci.o \
+ 		drm_platform.o drm_sysfs.o drm_hashtab.o drm_mm.o \
+ 		drm_crtc.o drm_modes.o drm_edid.o \
+ 		drm_info.o drm_debugfs.o drm_encoder_slave.o \
+ 		drm_trace_points.o drm_global.o drm_prime.o \
+-		drm_rect.o drm_vma_manager.o drm_flip_work.o
++		drm_rect.o drm_vma_manager.o drm_flip_work.o \
++		drm_modeset_lock.o drm_atomic.o
+ 
+ drm-$(CONFIG_COMPAT) += drm_ioc32.o
+ drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
+ drm-$(CONFIG_PCI) += ati_pcigart.o
+ drm-$(CONFIG_DRM_PANEL) += drm_panel.o
++drm-$(CONFIG_OF) += drm_of.o
+ 
+-drm-usb-y   := drm_usb.o
+-
+-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o
++drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
++		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o
+ drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
+ drm_kms_helper-$(CONFIG_DRM_KMS_FB_HELPER) += drm_fb_helper.o
+ drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o
+@@ -33,7 +34,6 @@
+ 
+ obj-$(CONFIG_DRM)	+= drm.o
+ obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
+-obj-$(CONFIG_DRM_USB)   += drm_usb.o
+ obj-$(CONFIG_DRM_TTM)	+= ttm/
+ obj-$(CONFIG_DRM_TDFX)	+= tdfx/
+ obj-$(CONFIG_DRM_R128)	+= r128/
+diff -Naur a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
+--- a/drivers/gpu/drm/ttm/ttm_bo.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_bo.c	2015-03-26 14:42:38.742435422 +0530
+@@ -40,6 +40,7 @@
+ #include <linux/file.h>
+ #include <linux/module.h>
+ #include <linux/atomic.h>
++#include <linux/reservation.h>
+ 
+ #define TTM_ASSERT_LOCKED(param)
+ #define TTM_DEBUG(fmt, arg...)
+@@ -53,12 +54,13 @@
+ 	.mode = S_IRUGO
+ };
+ 
+-static inline int ttm_mem_type_from_flags(uint32_t flags, uint32_t *mem_type)
++static inline int ttm_mem_type_from_place(const struct ttm_place *place,
++					  uint32_t *mem_type)
+ {
+ 	int i;
+ 
+ 	for (i = 0; i <= TTM_PL_PRIV5; i++)
+-		if (flags & (1 << i)) {
++		if (place->flags & (1 << i)) {
+ 			*mem_type = i;
+ 			return 0;
+ 		}
+@@ -89,12 +91,12 @@
+ 	       bo, bo->mem.num_pages, bo->mem.size >> 10,
+ 	       bo->mem.size >> 20);
+ 	for (i = 0; i < placement->num_placement; i++) {
+-		ret = ttm_mem_type_from_flags(placement->placement[i],
++		ret = ttm_mem_type_from_place(&placement->placement[i],
+ 						&mem_type);
+ 		if (ret)
+ 			return;
+ 		pr_err("  placement[%d]=0x%08X (%d)\n",
+-		       i, placement->placement[i], mem_type);
++		       i, placement->placement[i].flags, mem_type);
+ 		ttm_mem_type_debug(bo->bdev, mem_type);
+ 	}
+ }
+@@ -141,7 +143,6 @@
+ 	BUG_ON(atomic_read(&bo->list_kref.refcount));
+ 	BUG_ON(atomic_read(&bo->kref.refcount));
+ 	BUG_ON(atomic_read(&bo->cpu_writers));
+-	BUG_ON(bo->sync_obj != NULL);
+ 	BUG_ON(bo->mem.mm_node != NULL);
+ 	BUG_ON(!list_empty(&bo->lru));
+ 	BUG_ON(!list_empty(&bo->ddestroy));
+@@ -402,36 +403,48 @@
+ 	ww_mutex_unlock (&bo->resv->lock);
+ }
+ 
++static void ttm_bo_flush_all_fences(struct ttm_buffer_object *bo)
++{
++	struct reservation_object_list *fobj;
++	struct fence *fence;
++	int i;
++
++	fobj = reservation_object_get_list(bo->resv);
++	fence = reservation_object_get_excl(bo->resv);
++	if (fence && !fence->ops->signaled)
++		fence_enable_sw_signaling(fence);
++
++	for (i = 0; fobj && i < fobj->shared_count; ++i) {
++		fence = rcu_dereference_protected(fobj->shared[i],
++					reservation_object_held(bo->resv));
++
++		if (!fence->ops->signaled)
++			fence_enable_sw_signaling(fence);
++	}
++}
++
+ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo)
+ {
+ 	struct ttm_bo_device *bdev = bo->bdev;
+ 	struct ttm_bo_global *glob = bo->glob;
+-	struct ttm_bo_driver *driver = bdev->driver;
+-	void *sync_obj = NULL;
+ 	int put_count;
+ 	int ret;
+ 
+ 	spin_lock(&glob->lru_lock);
+-	ret = ttm_bo_reserve_nolru(bo, false, true, false, 0);
+-
+-	spin_lock(&bdev->fence_lock);
+-	(void) ttm_bo_wait(bo, false, false, true);
+-	if (!ret && !bo->sync_obj) {
+-		spin_unlock(&bdev->fence_lock);
+-		put_count = ttm_bo_del_from_lru(bo);
++	ret = __ttm_bo_reserve(bo, false, true, false, NULL);
+ 
+-		spin_unlock(&glob->lru_lock);
+-		ttm_bo_cleanup_memtype_use(bo);
++	if (!ret) {
++		if (!ttm_bo_wait(bo, false, false, true)) {
++			put_count = ttm_bo_del_from_lru(bo);
+ 
+-		ttm_bo_list_ref_sub(bo, put_count, true);
++			spin_unlock(&glob->lru_lock);
++			ttm_bo_cleanup_memtype_use(bo);
+ 
+-		return;
+-	}
+-	if (bo->sync_obj)
+-		sync_obj = driver->sync_obj_ref(bo->sync_obj);
+-	spin_unlock(&bdev->fence_lock);
++			ttm_bo_list_ref_sub(bo, put_count, true);
+ 
+-	if (!ret) {
++			return;
++		} else
++			ttm_bo_flush_all_fences(bo);
+ 
+ 		/*
+ 		 * Make NO_EVICT bos immediately available to
+@@ -443,17 +456,13 @@
+ 			ttm_bo_add_to_lru(bo);
+ 		}
+ 
+-		ww_mutex_unlock(&bo->resv->lock);
++		__ttm_bo_unreserve(bo);
+ 	}
+ 
+ 	kref_get(&bo->list_kref);
+ 	list_add_tail(&bo->ddestroy, &bdev->ddestroy);
+ 	spin_unlock(&glob->lru_lock);
+ 
+-	if (sync_obj) {
+-		driver->sync_obj_flush(sync_obj);
+-		driver->sync_obj_unref(&sync_obj);
+-	}
+ 	schedule_delayed_work(&bdev->wq,
+ 			      ((HZ / 100) < 1) ? 1 : HZ / 100);
+ }
+@@ -474,47 +483,29 @@
+ 					  bool interruptible,
+ 					  bool no_wait_gpu)
+ {
+-	struct ttm_bo_device *bdev = bo->bdev;
+-	struct ttm_bo_driver *driver = bdev->driver;
+ 	struct ttm_bo_global *glob = bo->glob;
+ 	int put_count;
+ 	int ret;
+ 
+-	spin_lock(&bdev->fence_lock);
+ 	ret = ttm_bo_wait(bo, false, false, true);
+ 
+ 	if (ret && !no_wait_gpu) {
+-		void *sync_obj;
+-
+-		/*
+-		 * Take a reference to the fence and unreserve,
+-		 * at this point the buffer should be dead, so
+-		 * no new sync objects can be attached.
+-		 */
+-		sync_obj = driver->sync_obj_ref(bo->sync_obj);
+-		spin_unlock(&bdev->fence_lock);
+-
++		long lret;
+ 		ww_mutex_unlock(&bo->resv->lock);
+ 		spin_unlock(&glob->lru_lock);
+ 
+-		ret = driver->sync_obj_wait(sync_obj, false, interruptible);
+-		driver->sync_obj_unref(&sync_obj);
+-		if (ret)
+-			return ret;
+-
+-		/*
+-		 * remove sync_obj with ttm_bo_wait, the wait should be
+-		 * finished, and no new wait object should have been added.
+-		 */
+-		spin_lock(&bdev->fence_lock);
+-		ret = ttm_bo_wait(bo, false, false, true);
+-		WARN_ON(ret);
+-		spin_unlock(&bdev->fence_lock);
+-		if (ret)
+-			return ret;
++		lret = reservation_object_wait_timeout_rcu(bo->resv,
++							   true,
++							   interruptible,
++							   30 * HZ);
++
++		if (lret < 0)
++			return lret;
++		else if (lret == 0)
++			return -EBUSY;
+ 
+ 		spin_lock(&glob->lru_lock);
+-		ret = ttm_bo_reserve_nolru(bo, false, true, false, 0);
++		ret = __ttm_bo_reserve(bo, false, true, false, NULL);
+ 
+ 		/*
+ 		 * We raced, and lost, someone else holds the reservation now,
+@@ -528,11 +519,17 @@
+ 			spin_unlock(&glob->lru_lock);
+ 			return 0;
+ 		}
+-	} else
+-		spin_unlock(&bdev->fence_lock);
++
++		/*
++		 * remove sync_obj with ttm_bo_wait, the wait should be
++		 * finished, and no new wait object should have been added.
++		 */
++		ret = ttm_bo_wait(bo, false, false, true);
++		WARN_ON(ret);
++	}
+ 
+ 	if (ret || unlikely(list_empty(&bo->ddestroy))) {
+-		ww_mutex_unlock(&bo->resv->lock);
++		__ttm_bo_unreserve(bo);
+ 		spin_unlock(&glob->lru_lock);
+ 		return ret;
+ 	}
+@@ -577,11 +574,11 @@
+ 			kref_get(&nentry->list_kref);
+ 		}
+ 
+-		ret = ttm_bo_reserve_nolru(entry, false, true, false, 0);
++		ret = __ttm_bo_reserve(entry, false, true, false, NULL);
+ 		if (remove_all && ret) {
+ 			spin_unlock(&glob->lru_lock);
+-			ret = ttm_bo_reserve_nolru(entry, false, false,
+-						   false, 0);
++			ret = __ttm_bo_reserve(entry, false, false,
++					       false, NULL);
+ 			spin_lock(&glob->lru_lock);
+ 		}
+ 
+@@ -667,9 +664,7 @@
+ 	struct ttm_placement placement;
+ 	int ret = 0;
+ 
+-	spin_lock(&bdev->fence_lock);
+ 	ret = ttm_bo_wait(bo, false, interruptible, no_wait_gpu);
+-	spin_unlock(&bdev->fence_lock);
+ 
+ 	if (unlikely(ret != 0)) {
+ 		if (ret != -ERESTARTSYS) {
+@@ -685,8 +680,6 @@
+ 	evict_mem.bus.io_reserved_vm = false;
+ 	evict_mem.bus.io_reserved_count = 0;
+ 
+-	placement.fpfn = 0;
+-	placement.lpfn = 0;
+ 	placement.num_placement = 0;
+ 	placement.num_busy_placement = 0;
+ 	bdev->driver->evict_flags(bo, &placement);
+@@ -716,6 +709,7 @@
+ 
+ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
+ 				uint32_t mem_type,
++				const struct ttm_place *place,
+ 				bool interruptible,
+ 				bool no_wait_gpu)
+ {
+@@ -726,9 +720,22 @@
+ 
+ 	spin_lock(&glob->lru_lock);
+ 	list_for_each_entry(bo, &man->lru, lru) {
+-		ret = ttm_bo_reserve_nolru(bo, false, true, false, 0);
+-		if (!ret)
++		ret = __ttm_bo_reserve(bo, false, true, false, NULL);
++		if (!ret) {
++			if (place && (place->fpfn || place->lpfn)) {
++				/* Don't evict this BO if it's outside of the
++				 * requested placement range
++				 */
++				if (place->fpfn >= (bo->mem.start + bo->mem.size) ||
++				    (place->lpfn && place->lpfn <= bo->mem.start)) {
++					__ttm_bo_unreserve(bo);
++					ret = -EBUSY;
++					continue;
++				}
++			}
++
+ 			break;
++		}
+ 	}
+ 
+ 	if (ret) {
+@@ -774,7 +781,7 @@
+  */
+ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo,
+ 					uint32_t mem_type,
+-					struct ttm_placement *placement,
++					const struct ttm_place *place,
+ 					struct ttm_mem_reg *mem,
+ 					bool interruptible,
+ 					bool no_wait_gpu)
+@@ -784,12 +791,12 @@
+ 	int ret;
+ 
+ 	do {
+-		ret = (*man->func->get_node)(man, bo, placement, mem);
++		ret = (*man->func->get_node)(man, bo, place, mem);
+ 		if (unlikely(ret != 0))
+ 			return ret;
+ 		if (mem->mm_node)
+ 			break;
+-		ret = ttm_mem_evict_first(bdev, mem_type,
++		ret = ttm_mem_evict_first(bdev, mem_type, place,
+ 					  interruptible, no_wait_gpu);
+ 		if (unlikely(ret != 0))
+ 			return ret;
+@@ -827,18 +834,18 @@
+ 
+ static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man,
+ 				 uint32_t mem_type,
+-				 uint32_t proposed_placement,
++				 const struct ttm_place *place,
+ 				 uint32_t *masked_placement)
+ {
+ 	uint32_t cur_flags = ttm_bo_type_flags(mem_type);
+ 
+-	if ((cur_flags & proposed_placement & TTM_PL_MASK_MEM) == 0)
++	if ((cur_flags & place->flags & TTM_PL_MASK_MEM) == 0)
+ 		return false;
+ 
+-	if ((proposed_placement & man->available_caching) == 0)
++	if ((place->flags & man->available_caching) == 0)
+ 		return false;
+ 
+-	cur_flags |= (proposed_placement & man->available_caching);
++	cur_flags |= (place->flags & man->available_caching);
+ 
+ 	*masked_placement = cur_flags;
+ 	return true;
+@@ -869,15 +876,14 @@
+ 
+ 	mem->mm_node = NULL;
+ 	for (i = 0; i < placement->num_placement; ++i) {
+-		ret = ttm_mem_type_from_flags(placement->placement[i],
+-						&mem_type);
++		const struct ttm_place *place = &placement->placement[i];
++
++		ret = ttm_mem_type_from_place(place, &mem_type);
+ 		if (ret)
+ 			return ret;
+ 		man = &bdev->man[mem_type];
+ 
+-		type_ok = ttm_bo_mt_compatible(man,
+-						mem_type,
+-						placement->placement[i],
++		type_ok = ttm_bo_mt_compatible(man, mem_type, place,
+ 						&cur_flags);
+ 
+ 		if (!type_ok)
+@@ -889,7 +895,7 @@
+ 		 * Use the access and other non-mapping-related flag bits from
+ 		 * the memory placement flags to the current flags
+ 		 */
+-		ttm_flag_masked(&cur_flags, placement->placement[i],
++		ttm_flag_masked(&cur_flags, place->flags,
+ 				~TTM_PL_MASK_MEMTYPE);
+ 
+ 		if (mem_type == TTM_PL_SYSTEM)
+@@ -897,7 +903,7 @@
+ 
+ 		if (man->has_type && man->use_type) {
+ 			type_found = true;
+-			ret = (*man->func->get_node)(man, bo, placement, mem);
++			ret = (*man->func->get_node)(man, bo, place, mem);
+ 			if (unlikely(ret))
+ 				return ret;
+ 		}
+@@ -915,17 +921,15 @@
+ 		return -EINVAL;
+ 
+ 	for (i = 0; i < placement->num_busy_placement; ++i) {
+-		ret = ttm_mem_type_from_flags(placement->busy_placement[i],
+-						&mem_type);
++		const struct ttm_place *place = &placement->busy_placement[i];
++
++		ret = ttm_mem_type_from_place(place, &mem_type);
+ 		if (ret)
+ 			return ret;
+ 		man = &bdev->man[mem_type];
+ 		if (!man->has_type)
+ 			continue;
+-		if (!ttm_bo_mt_compatible(man,
+-						mem_type,
+-						placement->busy_placement[i],
+-						&cur_flags))
++		if (!ttm_bo_mt_compatible(man, mem_type, place, &cur_flags))
+ 			continue;
+ 
+ 		cur_flags = ttm_bo_select_caching(man, bo->mem.placement,
+@@ -934,10 +938,9 @@
+ 		 * Use the access and other non-mapping-related flag bits from
+ 		 * the memory placement flags to the current flags
+ 		 */
+-		ttm_flag_masked(&cur_flags, placement->busy_placement[i],
++		ttm_flag_masked(&cur_flags, place->flags,
+ 				~TTM_PL_MASK_MEMTYPE);
+ 
+-
+ 		if (mem_type == TTM_PL_SYSTEM) {
+ 			mem->mem_type = mem_type;
+ 			mem->placement = cur_flags;
+@@ -945,7 +948,7 @@
+ 			return 0;
+ 		}
+ 
+-		ret = ttm_bo_mem_force_space(bo, mem_type, placement, mem,
++		ret = ttm_bo_mem_force_space(bo, mem_type, place, mem,
+ 						interruptible, no_wait_gpu);
+ 		if (ret == 0 && mem->mm_node) {
+ 			mem->placement = cur_flags;
+@@ -966,7 +969,6 @@
+ {
+ 	int ret = 0;
+ 	struct ttm_mem_reg mem;
+-	struct ttm_bo_device *bdev = bo->bdev;
+ 
+ 	lockdep_assert_held(&bo->resv->lock.base);
+ 
+@@ -975,9 +977,7 @@
+ 	 * Have the driver move function wait for idle when necessary,
+ 	 * instead of doing it here.
+ 	 */
+-	spin_lock(&bdev->fence_lock);
+ 	ret = ttm_bo_wait(bo, false, interruptible, no_wait_gpu);
+-	spin_unlock(&bdev->fence_lock);
+ 	if (ret)
+ 		return ret;
+ 	mem.num_pages = bo->num_pages;
+@@ -1006,20 +1006,27 @@
+ {
+ 	int i;
+ 
+-	if (mem->mm_node && placement->lpfn != 0 &&
+-	    (mem->start < placement->fpfn ||
+-	     mem->start + mem->num_pages > placement->lpfn))
+-		return false;
+-
+ 	for (i = 0; i < placement->num_placement; i++) {
+-		*new_flags = placement->placement[i];
++		const struct ttm_place *heap = &placement->placement[i];
++		if (mem->mm_node &&
++		    (mem->start < heap->fpfn ||
++		     (heap->lpfn != 0 && (mem->start + mem->num_pages) > heap->lpfn)))
++			continue;
++
++		*new_flags = heap->flags;
+ 		if ((*new_flags & mem->placement & TTM_PL_MASK_CACHING) &&
+ 		    (*new_flags & mem->placement & TTM_PL_MASK_MEM))
+ 			return true;
+ 	}
+ 
+ 	for (i = 0; i < placement->num_busy_placement; i++) {
+-		*new_flags = placement->busy_placement[i];
++		const struct ttm_place *heap = &placement->busy_placement[i];
++		if (mem->mm_node &&
++		    (mem->start < heap->fpfn ||
++		     (heap->lpfn != 0 && (mem->start + mem->num_pages) > heap->lpfn)))
++			continue;
++
++		*new_flags = heap->flags;
+ 		if ((*new_flags & mem->placement & TTM_PL_MASK_CACHING) &&
+ 		    (*new_flags & mem->placement & TTM_PL_MASK_MEM))
+ 			return true;
+@@ -1037,11 +1044,6 @@
+ 	uint32_t new_flags;
+ 
+ 	lockdep_assert_held(&bo->resv->lock.base);
+-	/* Check that range is valid */
+-	if (placement->lpfn || placement->fpfn)
+-		if (placement->fpfn > placement->lpfn ||
+-			(placement->lpfn - placement->fpfn) < bo->num_pages)
+-			return -EINVAL;
+ 	/*
+ 	 * Check whether we need to move buffer.
+ 	 */
+@@ -1070,15 +1072,6 @@
+ }
+ EXPORT_SYMBOL(ttm_bo_validate);
+ 
+-int ttm_bo_check_placement(struct ttm_buffer_object *bo,
+-				struct ttm_placement *placement)
+-{
+-	BUG_ON((placement->fpfn || placement->lpfn) &&
+-	       (bo->mem.num_pages > (placement->lpfn - placement->fpfn)));
+-
+-	return 0;
+-}
+-
+ int ttm_bo_init(struct ttm_bo_device *bdev,
+ 		struct ttm_buffer_object *bo,
+ 		unsigned long size,
+@@ -1089,6 +1082,7 @@
+ 		struct file *persistent_swap_storage,
+ 		size_t acc_size,
+ 		struct sg_table *sg,
++		struct reservation_object *resv,
+ 		void (*destroy) (struct ttm_buffer_object *))
+ {
+ 	int ret = 0;
+@@ -1142,30 +1136,38 @@
+ 	bo->persistent_swap_storage = persistent_swap_storage;
+ 	bo->acc_size = acc_size;
+ 	bo->sg = sg;
+-	bo->resv = &bo->ttm_resv;
+-	reservation_object_init(bo->resv);
++	if (resv) {
++		bo->resv = resv;
++		lockdep_assert_held(&bo->resv->lock.base);
++	} else {
++		bo->resv = &bo->ttm_resv;
++		reservation_object_init(&bo->ttm_resv);
++	}
+ 	atomic_inc(&bo->glob->bo_count);
+ 	drm_vma_node_reset(&bo->vma_node);
+ 
+-	ret = ttm_bo_check_placement(bo, placement);
+-
+ 	/*
+ 	 * For ttm_bo_type_device buffers, allocate
+ 	 * address space from the device.
+ 	 */
+-	if (likely(!ret) &&
+-	    (bo->type == ttm_bo_type_device ||
+-	     bo->type == ttm_bo_type_sg))
++	if (bo->type == ttm_bo_type_device ||
++	    bo->type == ttm_bo_type_sg)
+ 		ret = drm_vma_offset_add(&bdev->vma_manager, &bo->vma_node,
+ 					 bo->mem.num_pages);
+ 
+-	locked = ww_mutex_trylock(&bo->resv->lock);
+-	WARN_ON(!locked);
++	/* passed reservation objects should already be locked,
++	 * since otherwise lockdep will be angered in radeon.
++	 */
++	if (!resv) {
++		locked = ww_mutex_trylock(&bo->resv->lock);
++		WARN_ON(!locked);
++	}
+ 
+ 	if (likely(!ret))
+ 		ret = ttm_bo_validate(bo, placement, interruptible, false);
+ 
+-	ttm_bo_unreserve(bo);
++	if (!resv)
++		ttm_bo_unreserve(bo);
+ 
+ 	if (unlikely(ret))
+ 		ttm_bo_unref(&bo);
+@@ -1223,7 +1225,7 @@
+ 	acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
+ 	ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
+ 			  interruptible, persistent_swap_storage, acc_size,
+-			  NULL, NULL);
++			  NULL, NULL, NULL);
+ 	if (likely(ret == 0))
+ 		*p_bo = bo;
+ 
+@@ -1245,7 +1247,7 @@
+ 	spin_lock(&glob->lru_lock);
+ 	while (!list_empty(&man->lru)) {
+ 		spin_unlock(&glob->lru_lock);
+-		ret = ttm_mem_evict_first(bdev, mem_type, false, false);
++		ret = ttm_mem_evict_first(bdev, mem_type, NULL, false, false);
+ 		if (ret) {
+ 			if (allow_errors) {
+ 				return ret;
+@@ -1451,6 +1453,7 @@
+ int ttm_bo_device_init(struct ttm_bo_device *bdev,
+ 		       struct ttm_bo_global *glob,
+ 		       struct ttm_bo_driver *driver,
++		       struct address_space *mapping,
+ 		       uint64_t file_page_offset,
+ 		       bool need_dma32)
+ {
+@@ -1472,11 +1475,10 @@
+ 				    0x10000000);
+ 	INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue);
+ 	INIT_LIST_HEAD(&bdev->ddestroy);
+-	bdev->dev_mapping = NULL;
++	bdev->dev_mapping = mapping;
+ 	bdev->glob = glob;
+ 	bdev->need_dma32 = need_dma32;
+ 	bdev->val_seq = 0;
+-	spin_lock_init(&bdev->fence_lock);
+ 	mutex_lock(&glob->device_list_mutex);
+ 	list_add_tail(&bdev->device_list, &glob->device_list);
+ 	mutex_unlock(&glob->device_list_mutex);
+@@ -1529,77 +1531,66 @@
+ 
+ EXPORT_SYMBOL(ttm_bo_unmap_virtual);
+ 
+-
+ int ttm_bo_wait(struct ttm_buffer_object *bo,
+ 		bool lazy, bool interruptible, bool no_wait)
+ {
+-	struct ttm_bo_driver *driver = bo->bdev->driver;
+-	struct ttm_bo_device *bdev = bo->bdev;
+-	void *sync_obj;
+-	int ret = 0;
+-
+-	if (likely(bo->sync_obj == NULL))
+-		return 0;
++	struct reservation_object_list *fobj;
++	struct reservation_object *resv;
++	struct fence *excl;
++	long timeout = 15 * HZ;
++	int i;
+ 
+-	while (bo->sync_obj) {
++	resv = bo->resv;
++	fobj = reservation_object_get_list(resv);
++	excl = reservation_object_get_excl(resv);
++	if (excl) {
++		if (!fence_is_signaled(excl)) {
++			if (no_wait)
++				return -EBUSY;
+ 
+-		if (driver->sync_obj_signaled(bo->sync_obj)) {
+-			void *tmp_obj = bo->sync_obj;
+-			bo->sync_obj = NULL;
+-			clear_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags);
+-			spin_unlock(&bdev->fence_lock);
+-			driver->sync_obj_unref(&tmp_obj);
+-			spin_lock(&bdev->fence_lock);
+-			continue;
++			timeout = fence_wait_timeout(excl,
++						     interruptible, timeout);
+ 		}
++	}
+ 
+-		if (no_wait)
+-			return -EBUSY;
++	for (i = 0; fobj && timeout > 0 && i < fobj->shared_count; ++i) {
++		struct fence *fence;
++		fence = rcu_dereference_protected(fobj->shared[i],
++						reservation_object_held(resv));
+ 
+-		sync_obj = driver->sync_obj_ref(bo->sync_obj);
+-		spin_unlock(&bdev->fence_lock);
+-		ret = driver->sync_obj_wait(sync_obj,
+-					    lazy, interruptible);
+-		if (unlikely(ret != 0)) {
+-			driver->sync_obj_unref(&sync_obj);
+-			spin_lock(&bdev->fence_lock);
+-			return ret;
+-		}
+-		spin_lock(&bdev->fence_lock);
+-		if (likely(bo->sync_obj == sync_obj)) {
+-			void *tmp_obj = bo->sync_obj;
+-			bo->sync_obj = NULL;
+-			clear_bit(TTM_BO_PRIV_FLAG_MOVING,
+-				  &bo->priv_flags);
+-			spin_unlock(&bdev->fence_lock);
+-			driver->sync_obj_unref(&sync_obj);
+-			driver->sync_obj_unref(&tmp_obj);
+-			spin_lock(&bdev->fence_lock);
+-		} else {
+-			spin_unlock(&bdev->fence_lock);
+-			driver->sync_obj_unref(&sync_obj);
+-			spin_lock(&bdev->fence_lock);
++		if (!fence_is_signaled(fence)) {
++			if (no_wait)
++				return -EBUSY;
++
++			timeout = fence_wait_timeout(fence,
++						     interruptible, timeout);
+ 		}
+ 	}
++
++	if (timeout < 0)
++		return timeout;
++
++	if (timeout == 0)
++		return -EBUSY;
++
++	reservation_object_add_excl_fence(resv, NULL);
++	clear_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags);
+ 	return 0;
+ }
+ EXPORT_SYMBOL(ttm_bo_wait);
+ 
+ int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait)
+ {
+-	struct ttm_bo_device *bdev = bo->bdev;
+ 	int ret = 0;
+ 
+ 	/*
+ 	 * Using ttm_bo_reserve makes sure the lru lists are updated.
+ 	 */
+ 
+-	ret = ttm_bo_reserve(bo, true, no_wait, false, 0);
++	ret = ttm_bo_reserve(bo, true, no_wait, false, NULL);
+ 	if (unlikely(ret != 0))
+ 		return ret;
+-	spin_lock(&bdev->fence_lock);
+ 	ret = ttm_bo_wait(bo, false, true, no_wait);
+-	spin_unlock(&bdev->fence_lock);
+ 	if (likely(ret == 0))
+ 		atomic_inc(&bo->cpu_writers);
+ 	ttm_bo_unreserve(bo);
+@@ -1629,7 +1620,7 @@
+ 
+ 	spin_lock(&glob->lru_lock);
+ 	list_for_each_entry(bo, &glob->swap_lru, swap) {
+-		ret = ttm_bo_reserve_nolru(bo, false, true, false, 0);
++		ret = __ttm_bo_reserve(bo, false, true, false, NULL);
+ 		if (!ret)
+ 			break;
+ 	}
+@@ -1656,9 +1647,7 @@
+ 	 * Wait for GPU, then move to system cached.
+ 	 */
+ 
+-	spin_lock(&bo->bdev->fence_lock);
+ 	ret = ttm_bo_wait(bo, false, false, false);
+-	spin_unlock(&bo->bdev->fence_lock);
+ 
+ 	if (unlikely(ret != 0))
+ 		goto out;
+@@ -1696,7 +1685,7 @@
+ 	 * already swapped buffer.
+ 	 */
+ 
+-	ww_mutex_unlock(&bo->resv->lock);
++	__ttm_bo_unreserve(bo);
+ 	kref_put(&bo->list_kref, ttm_bo_release_list);
+ 	return ret;
+ }
+@@ -1730,10 +1719,10 @@
+ 		return -ERESTARTSYS;
+ 	if (!ww_mutex_is_locked(&bo->resv->lock))
+ 		goto out_unlock;
+-	ret = ttm_bo_reserve_nolru(bo, true, false, false, NULL);
++	ret = __ttm_bo_reserve(bo, true, false, false, NULL);
+ 	if (unlikely(ret != 0))
+ 		goto out_unlock;
+-	ww_mutex_unlock(&bo->resv->lock);
++	__ttm_bo_unreserve(bo);
+ 
+ out_unlock:
+ 	mutex_unlock(&bo->wu_mutex);
+diff -Naur a/drivers/gpu/drm/ttm/ttm_bo_manager.c b/drivers/gpu/drm/ttm/ttm_bo_manager.c
+--- a/drivers/gpu/drm/ttm/ttm_bo_manager.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_bo_manager.c	2015-03-26 14:42:38.742435422 +0530
+@@ -49,16 +49,18 @@
+ 
+ static int ttm_bo_man_get_node(struct ttm_mem_type_manager *man,
+ 			       struct ttm_buffer_object *bo,
+-			       struct ttm_placement *placement,
++			       const struct ttm_place *place,
+ 			       struct ttm_mem_reg *mem)
+ {
+ 	struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv;
+ 	struct drm_mm *mm = &rman->mm;
+ 	struct drm_mm_node *node = NULL;
++	enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST;
++	enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT;
+ 	unsigned long lpfn;
+ 	int ret;
+ 
+-	lpfn = placement->lpfn;
++	lpfn = place->lpfn;
+ 	if (!lpfn)
+ 		lpfn = man->size;
+ 
+@@ -66,11 +68,16 @@
+ 	if (!node)
+ 		return -ENOMEM;
+ 
++	if (place->flags & TTM_PL_FLAG_TOPDOWN) {
++		sflags = DRM_MM_SEARCH_BELOW;
++		aflags = DRM_MM_CREATE_TOP;
++	}
++
+ 	spin_lock(&rman->lock);
+-	ret = drm_mm_insert_node_in_range(mm, node, mem->num_pages,
+-					  mem->page_alignment,
+-					  placement->fpfn, lpfn,
+-					  DRM_MM_SEARCH_BEST);
++	ret = drm_mm_insert_node_in_range_generic(mm, node, mem->num_pages,
++					  mem->page_alignment, 0,
++					  place->fpfn, lpfn,
++					  sflags, aflags);
+ 	spin_unlock(&rman->lock);
+ 
+ 	if (unlikely(ret)) {
+diff -Naur a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
+--- a/drivers/gpu/drm/ttm/ttm_bo_util.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_bo_util.c	2015-03-26 14:42:38.742435422 +0530
+@@ -37,6 +37,7 @@
+ #include <linux/slab.h>
+ #include <linux/vmalloc.h>
+ #include <linux/module.h>
++#include <linux/reservation.h>
+ 
+ void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
+ {
+@@ -444,8 +445,6 @@
+ 				      struct ttm_buffer_object **new_obj)
+ {
+ 	struct ttm_buffer_object *fbo;
+-	struct ttm_bo_device *bdev = bo->bdev;
+-	struct ttm_bo_driver *driver = bdev->driver;
+ 	int ret;
+ 
+ 	fbo = kmalloc(sizeof(*fbo), GFP_KERNEL);
+@@ -466,12 +465,6 @@
+ 	drm_vma_node_reset(&fbo->vma_node);
+ 	atomic_set(&fbo->cpu_writers, 0);
+ 
+-	spin_lock(&bdev->fence_lock);
+-	if (bo->sync_obj)
+-		fbo->sync_obj = driver->sync_obj_ref(bo->sync_obj);
+-	else
+-		fbo->sync_obj = NULL;
+-	spin_unlock(&bdev->fence_lock);
+ 	kref_init(&fbo->list_kref);
+ 	kref_init(&fbo->kref);
+ 	fbo->destroy = &ttm_transfered_destroy;
+@@ -487,28 +480,24 @@
+ 
+ pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp)
+ {
++	/* Cached mappings need no adjustment */
++	if (caching_flags & TTM_PL_FLAG_CACHED)
++		return tmp;
++
+ #if defined(__i386__) || defined(__x86_64__)
+ 	if (caching_flags & TTM_PL_FLAG_WC)
+ 		tmp = pgprot_writecombine(tmp);
+ 	else if (boot_cpu_data.x86 > 3)
+ 		tmp = pgprot_noncached(tmp);
+-
+-#elif defined(__powerpc__)
+-	if (!(caching_flags & TTM_PL_FLAG_CACHED)) {
+-		pgprot_val(tmp) |= _PAGE_NO_CACHE;
+-		if (caching_flags & TTM_PL_FLAG_UNCACHED)
+-			pgprot_val(tmp) |= _PAGE_GUARDED;
+-	}
+ #endif
+-#if defined(__ia64__)
++#if defined(__ia64__) || defined(__arm__) || defined(__powerpc__)
+ 	if (caching_flags & TTM_PL_FLAG_WC)
+ 		tmp = pgprot_writecombine(tmp);
+ 	else
+ 		tmp = pgprot_noncached(tmp);
+ #endif
+ #if defined(__sparc__) || defined(__mips__)
+-	if (!(caching_flags & TTM_PL_FLAG_CACHED))
+-		tmp = pgprot_noncached(tmp);
++	tmp = pgprot_noncached(tmp);
+ #endif
+ 	return tmp;
+ }
+@@ -567,9 +556,7 @@
+ 		 * We need to use vmap to get the desired page protection
+ 		 * or to make the buffer object look contiguous.
+ 		 */
+-		prot = (mem->placement & TTM_PL_FLAG_CACHED) ?
+-			PAGE_KERNEL :
+-			ttm_io_prot(mem->placement, PAGE_KERNEL);
++		prot = ttm_io_prot(mem->placement, PAGE_KERNEL);
+ 		map->bo_kmap_type = ttm_bo_map_vmap;
+ 		map->virtual = vmap(ttm->pages + start_page, num_pages,
+ 				    0, prot);
+@@ -644,30 +631,20 @@
+ EXPORT_SYMBOL(ttm_bo_kunmap);
+ 
+ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
+-			      void *sync_obj,
++			      struct fence *fence,
+ 			      bool evict,
+ 			      bool no_wait_gpu,
+ 			      struct ttm_mem_reg *new_mem)
+ {
+ 	struct ttm_bo_device *bdev = bo->bdev;
+-	struct ttm_bo_driver *driver = bdev->driver;
+ 	struct ttm_mem_type_manager *man = &bdev->man[new_mem->mem_type];
+ 	struct ttm_mem_reg *old_mem = &bo->mem;
+ 	int ret;
+ 	struct ttm_buffer_object *ghost_obj;
+-	void *tmp_obj = NULL;
+ 
+-	spin_lock(&bdev->fence_lock);
+-	if (bo->sync_obj) {
+-		tmp_obj = bo->sync_obj;
+-		bo->sync_obj = NULL;
+-	}
+-	bo->sync_obj = driver->sync_obj_ref(sync_obj);
++	reservation_object_add_excl_fence(bo->resv, fence);
+ 	if (evict) {
+ 		ret = ttm_bo_wait(bo, false, false, false);
+-		spin_unlock(&bdev->fence_lock);
+-		if (tmp_obj)
+-			driver->sync_obj_unref(&tmp_obj);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -688,14 +665,13 @@
+ 		 */
+ 
+ 		set_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags);
+-		spin_unlock(&bdev->fence_lock);
+-		if (tmp_obj)
+-			driver->sync_obj_unref(&tmp_obj);
+ 
+ 		ret = ttm_buffer_object_transfer(bo, &ghost_obj);
+ 		if (ret)
+ 			return ret;
+ 
++		reservation_object_add_excl_fence(ghost_obj->resv, fence);
++
+ 		/**
+ 		 * If we're not moving to fixed memory, the TTM object
+ 		 * needs to stay alive. Otherwhise hang it on the ghost
+diff -Naur a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
+--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c	2015-03-26 14:42:38.742435422 +0530
+@@ -45,10 +45,8 @@
+ 				struct vm_area_struct *vma,
+ 				struct vm_fault *vmf)
+ {
+-	struct ttm_bo_device *bdev = bo->bdev;
+ 	int ret = 0;
+ 
+-	spin_lock(&bdev->fence_lock);
+ 	if (likely(!test_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags)))
+ 		goto out_unlock;
+ 
+@@ -82,7 +80,6 @@
+ 			VM_FAULT_NOPAGE;
+ 
+ out_unlock:
+-	spin_unlock(&bdev->fence_lock);
+ 	return ret;
+ }
+ 
+@@ -200,9 +197,8 @@
+ 						cvma.vm_page_prot);
+ 	} else {
+ 		ttm = bo->ttm;
+-		if (!(bo->mem.placement & TTM_PL_FLAG_CACHED))
+-			cvma.vm_page_prot = ttm_io_prot(bo->mem.placement,
+-							cvma.vm_page_prot);
++		cvma.vm_page_prot = ttm_io_prot(bo->mem.placement,
++						cvma.vm_page_prot);
+ 
+ 		/* Allocate all page at once, most common usage */
+ 		if (ttm->bdev->driver->ttm_tt_populate(ttm)) {
+diff -Naur a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
+--- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c	2015-03-26 14:42:38.742435422 +0530
+@@ -32,21 +32,13 @@
+ #include <linux/sched.h>
+ #include <linux/module.h>
+ 
+-static void ttm_eu_backoff_reservation_locked(struct list_head *list)
++static void ttm_eu_backoff_reservation_reverse(struct list_head *list,
++					      struct ttm_validate_buffer *entry)
+ {
+-	struct ttm_validate_buffer *entry;
+-
+-	list_for_each_entry(entry, list, head) {
++	list_for_each_entry_continue_reverse(entry, list, head) {
+ 		struct ttm_buffer_object *bo = entry->bo;
+-		if (!entry->reserved)
+-			continue;
+ 
+-		entry->reserved = false;
+-		if (entry->removed) {
+-			ttm_bo_add_to_lru(bo);
+-			entry->removed = false;
+-		}
+-		ww_mutex_unlock(&bo->resv->lock);
++		__ttm_bo_unreserve(bo);
+ 	}
+ }
+ 
+@@ -56,27 +48,9 @@
+ 
+ 	list_for_each_entry(entry, list, head) {
+ 		struct ttm_buffer_object *bo = entry->bo;
+-		if (!entry->reserved)
+-			continue;
+-
+-		if (!entry->removed) {
+-			entry->put_count = ttm_bo_del_from_lru(bo);
+-			entry->removed = true;
+-		}
+-	}
+-}
+-
+-static void ttm_eu_list_ref_sub(struct list_head *list)
+-{
+-	struct ttm_validate_buffer *entry;
+-
+-	list_for_each_entry(entry, list, head) {
+-		struct ttm_buffer_object *bo = entry->bo;
++		unsigned put_count = ttm_bo_del_from_lru(bo);
+ 
+-		if (entry->put_count) {
+-			ttm_bo_list_ref_sub(bo, entry->put_count, true);
+-			entry->put_count = 0;
+-		}
++		ttm_bo_list_ref_sub(bo, put_count, true);
+ 	}
+ }
+ 
+@@ -91,11 +65,18 @@
+ 
+ 	entry = list_first_entry(list, struct ttm_validate_buffer, head);
+ 	glob = entry->bo->glob;
++
+ 	spin_lock(&glob->lru_lock);
+-	ttm_eu_backoff_reservation_locked(list);
++	list_for_each_entry(entry, list, head) {
++		struct ttm_buffer_object *bo = entry->bo;
++
++		ttm_bo_add_to_lru(bo);
++		__ttm_bo_unreserve(bo);
++	}
++	spin_unlock(&glob->lru_lock);
++
+ 	if (ticket)
+ 		ww_acquire_fini(ticket);
+-	spin_unlock(&glob->lru_lock);
+ }
+ EXPORT_SYMBOL(ttm_eu_backoff_reservation);
+ 
+@@ -112,7 +93,8 @@
+  */
+ 
+ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket,
+-			   struct list_head *list)
++			   struct list_head *list, bool intr,
++			   struct list_head *dups)
+ {
+ 	struct ttm_bo_global *glob;
+ 	struct ttm_validate_buffer *entry;
+@@ -121,60 +103,71 @@
+ 	if (list_empty(list))
+ 		return 0;
+ 
+-	list_for_each_entry(entry, list, head) {
+-		entry->reserved = false;
+-		entry->put_count = 0;
+-		entry->removed = false;
+-	}
+-
+ 	entry = list_first_entry(list, struct ttm_validate_buffer, head);
+ 	glob = entry->bo->glob;
+ 
+ 	if (ticket)
+ 		ww_acquire_init(ticket, &reservation_ww_class);
+-retry:
++
+ 	list_for_each_entry(entry, list, head) {
+ 		struct ttm_buffer_object *bo = entry->bo;
+ 
+-		/* already slowpath reserved? */
+-		if (entry->reserved)
++		ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), true,
++				       ticket);
++		if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) {
++			__ttm_bo_unreserve(bo);
++
++			ret = -EBUSY;
++
++		} else if (ret == -EALREADY && dups) {
++			struct ttm_validate_buffer *safe = entry;
++			entry = list_prev_entry(entry, head);
++			list_del(&safe->head);
++			list_add(&safe->head, dups);
+ 			continue;
++		}
++
++		if (!ret) {
++			if (!entry->shared)
++				continue;
++
++			ret = reservation_object_reserve_shared(bo->resv);
++			if (!ret)
++				continue;
++		}
+ 
+-		ret = ttm_bo_reserve_nolru(bo, true, (ticket == NULL), true,
+-					   ticket);
++		/* uh oh, we lost out, drop every reservation and try
++		 * to only reserve this buffer, then start over if
++		 * this succeeds.
++		 */
++		ttm_eu_backoff_reservation_reverse(list, entry);
+ 
+-		if (ret == -EDEADLK) {
+-			/* uh oh, we lost out, drop every reservation and try
+-			 * to only reserve this buffer, then start over if
+-			 * this succeeds.
+-			 */
+-			BUG_ON(ticket == NULL);
+-			spin_lock(&glob->lru_lock);
+-			ttm_eu_backoff_reservation_locked(list);
+-			spin_unlock(&glob->lru_lock);
+-			ttm_eu_list_ref_sub(list);
++		if (ret == -EDEADLK && intr) {
+ 			ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
+ 							       ticket);
+-			if (unlikely(ret != 0)) {
+-				if (ret == -EINTR)
+-					ret = -ERESTARTSYS;
+-				goto err_fini;
+-			}
++		} else if (ret == -EDEADLK) {
++			ww_mutex_lock_slow(&bo->resv->lock, ticket);
++			ret = 0;
++		}
+ 
+-			entry->reserved = true;
+-			if (unlikely(atomic_read(&bo->cpu_writers) > 0)) {
+-				ret = -EBUSY;
+-				goto err;
+-			}
+-			goto retry;
+-		} else if (ret)
+-			goto err;
++		if (!ret && entry->shared)
++			ret = reservation_object_reserve_shared(bo->resv);
+ 
+-		entry->reserved = true;
+-		if (unlikely(atomic_read(&bo->cpu_writers) > 0)) {
+-			ret = -EBUSY;
+-			goto err;
++		if (unlikely(ret != 0)) {
++			if (ret == -EINTR)
++				ret = -ERESTARTSYS;
++			if (ticket) {
++				ww_acquire_done(ticket);
++				ww_acquire_fini(ticket);
++			}
++			return ret;
+ 		}
++
++		/* move this item to the front of the list,
++		 * forces correct iteration of the loop without keeping track
++		 */
++		list_del(&entry->head);
++		list_add(&entry->head, list);
+ 	}
+ 
+ 	if (ticket)
+@@ -182,25 +175,12 @@
+ 	spin_lock(&glob->lru_lock);
+ 	ttm_eu_del_from_lru_locked(list);
+ 	spin_unlock(&glob->lru_lock);
+-	ttm_eu_list_ref_sub(list);
+ 	return 0;
+-
+-err:
+-	spin_lock(&glob->lru_lock);
+-	ttm_eu_backoff_reservation_locked(list);
+-	spin_unlock(&glob->lru_lock);
+-	ttm_eu_list_ref_sub(list);
+-err_fini:
+-	if (ticket) {
+-		ww_acquire_done(ticket);
+-		ww_acquire_fini(ticket);
+-	}
+-	return ret;
+ }
+ EXPORT_SYMBOL(ttm_eu_reserve_buffers);
+ 
+ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket,
+-				 struct list_head *list, void *sync_obj)
++				 struct list_head *list, struct fence *fence)
+ {
+ 	struct ttm_validate_buffer *entry;
+ 	struct ttm_buffer_object *bo;
+@@ -217,24 +197,18 @@
+ 	glob = bo->glob;
+ 
+ 	spin_lock(&glob->lru_lock);
+-	spin_lock(&bdev->fence_lock);
+ 
+ 	list_for_each_entry(entry, list, head) {
+ 		bo = entry->bo;
+-		entry->old_sync_obj = bo->sync_obj;
+-		bo->sync_obj = driver->sync_obj_ref(sync_obj);
++		if (entry->shared)
++			reservation_object_add_shared_fence(bo->resv, fence);
++		else
++			reservation_object_add_excl_fence(bo->resv, fence);
+ 		ttm_bo_add_to_lru(bo);
+-		ww_mutex_unlock(&bo->resv->lock);
+-		entry->reserved = false;
++		__ttm_bo_unreserve(bo);
+ 	}
+-	spin_unlock(&bdev->fence_lock);
+ 	spin_unlock(&glob->lru_lock);
+ 	if (ticket)
+ 		ww_acquire_fini(ticket);
+-
+-	list_for_each_entry(entry, list, head) {
+-		if (entry->old_sync_obj)
+-			driver->sync_obj_unref(&entry->old_sync_obj);
+-	}
+ }
+ EXPORT_SYMBOL(ttm_eu_fence_buffer_objects);
+diff -Naur a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
+--- a/drivers/gpu/drm/ttm/ttm_memory.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_memory.c	2015-03-26 14:42:38.742435422 +0530
+@@ -300,7 +300,8 @@
+ 	zone->glob = glob;
+ 	glob->zone_highmem = zone;
+ 	ret = kobject_init_and_add(
+-		&zone->kobj, &ttm_mem_zone_kobj_type, &glob->kobj, zone->name);
++		&zone->kobj, &ttm_mem_zone_kobj_type, &glob->kobj, "%s",
++		zone->name);
+ 	if (unlikely(ret != 0)) {
+ 		kobject_put(&zone->kobj);
+ 		return ret;
+diff -Naur a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
+--- a/drivers/gpu/drm/ttm/ttm_module.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_module.c	2015-03-26 14:42:38.742435422 +0530
+@@ -35,7 +35,7 @@
+ #include <drm/drm_sysfs.h>
+ 
+ static DECLARE_WAIT_QUEUE_HEAD(exit_q);
+-atomic_t device_released;
++static atomic_t device_released;
+ 
+ static struct device_type ttm_drm_class_type = {
+ 	.name = "ttm",
+diff -Naur a/drivers/gpu/drm/ttm/ttm_object.c b/drivers/gpu/drm/ttm/ttm_object.c
+--- a/drivers/gpu/drm/ttm/ttm_object.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_object.c	2015-03-26 14:42:38.742435422 +0530
+@@ -270,6 +270,52 @@
+ }
+ EXPORT_SYMBOL(ttm_base_object_lookup_for_ref);
+ 
++/**
++ * ttm_ref_object_exists - Check whether a caller has a valid ref object
++ * (has opened) a base object.
++ *
++ * @tfile: Pointer to a struct ttm_object_file identifying the caller.
++ * @base: Pointer to a struct base object.
++ *
++ * Checks wether the caller identified by @tfile has put a valid USAGE
++ * reference object on the base object identified by @base.
++ */
++bool ttm_ref_object_exists(struct ttm_object_file *tfile,
++			   struct ttm_base_object *base)
++{
++	struct drm_open_hash *ht = &tfile->ref_hash[TTM_REF_USAGE];
++	struct drm_hash_item *hash;
++	struct ttm_ref_object *ref;
++
++	rcu_read_lock();
++	if (unlikely(drm_ht_find_item_rcu(ht, base->hash.key, &hash) != 0))
++		goto out_false;
++
++	/*
++	 * Verify that the ref object is really pointing to our base object.
++	 * Our base object could actually be dead, and the ref object pointing
++	 * to another base object with the same handle.
++	 */
++	ref = drm_hash_entry(hash, struct ttm_ref_object, hash);
++	if (unlikely(base != ref->obj))
++		goto out_false;
++
++	/*
++	 * Verify that the ref->obj pointer was actually valid!
++	 */
++	rmb();
++	if (unlikely(atomic_read(&ref->kref.refcount) == 0))
++		goto out_false;
++
++	rcu_read_unlock();
++	return true;
++
++ out_false:
++	rcu_read_unlock();
++	return false;
++}
++EXPORT_SYMBOL(ttm_ref_object_exists);
++
+ int ttm_ref_object_add(struct ttm_object_file *tfile,
+ 		       struct ttm_base_object *base,
+ 		       enum ttm_ref_type ref_type, bool *existed)
+diff -Naur a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
+--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c	2015-03-26 14:42:38.746435422 +0530
+@@ -297,11 +297,12 @@
+  *
+  * @pool: to free the pages from
+  * @free_all: If set to true will free all pages in pool
+- * @gfp: GFP flags.
++ * @use_static: Safe to use static buffer
+  **/
+ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free,
+-			      gfp_t gfp)
++			      bool use_static)
+ {
++	static struct page *static_buf[NUM_PAGES_TO_ALLOC];
+ 	unsigned long irq_flags;
+ 	struct page *p;
+ 	struct page **pages_to_free;
+@@ -311,7 +312,11 @@
+ 	if (NUM_PAGES_TO_ALLOC < nr_free)
+ 		npages_to_free = NUM_PAGES_TO_ALLOC;
+ 
+-	pages_to_free = kmalloc(npages_to_free * sizeof(struct page *), gfp);
++	if (use_static)
++		pages_to_free = static_buf;
++	else
++		pages_to_free = kmalloc(npages_to_free * sizeof(struct page *),
++					GFP_KERNEL);
+ 	if (!pages_to_free) {
+ 		pr_err("Failed to allocate memory for pool free operation\n");
+ 		return 0;
+@@ -374,7 +379,8 @@
+ 	if (freed_pages)
+ 		ttm_pages_put(pages_to_free, freed_pages);
+ out:
+-	kfree(pages_to_free);
++	if (pages_to_free != static_buf)
++		kfree(pages_to_free);
+ 	return nr_free;
+ }
+ 
+@@ -383,8 +389,6 @@
+  *
+  * XXX: (dchinner) Deadlock warning!
+  *
+- * We need to pass sc->gfp_mask to ttm_page_pool_free().
+- *
+  * This code is crying out for a shrinker per pool....
+  */
+ static unsigned long
+@@ -407,8 +411,8 @@
+ 		if (shrink_pages == 0)
+ 			break;
+ 		pool = &_manager->pools[(i + pool_offset)%NUM_POOLS];
+-		shrink_pages = ttm_page_pool_free(pool, nr_free,
+-						  sc->gfp_mask);
++		/* OK to use static buffer since global mutex is held. */
++		shrink_pages = ttm_page_pool_free(pool, nr_free, true);
+ 		freed += nr_free - shrink_pages;
+ 	}
+ 	mutex_unlock(&lock);
+@@ -710,7 +714,7 @@
+ 	}
+ 	spin_unlock_irqrestore(&pool->lock, irq_flags);
+ 	if (npages)
+-		ttm_page_pool_free(pool, npages, GFP_KERNEL);
++		ttm_page_pool_free(pool, npages, false);
+ }
+ 
+ /*
+@@ -794,7 +798,7 @@
+ 	return 0;
+ }
+ 
+-static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, int flags,
++static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags,
+ 		char *name)
+ {
+ 	spin_lock_init(&pool->lock);
+@@ -849,9 +853,9 @@
+ 	pr_info("Finalizing pool allocator\n");
+ 	ttm_pool_mm_shrink_fini(_manager);
+ 
++	/* OK to use static buffer since global mutex is no longer used. */
+ 	for (i = 0; i < NUM_POOLS; ++i)
+-		ttm_page_pool_free(&_manager->pools[i], FREE_ALL_PAGES,
+-				   GFP_KERNEL);
++		ttm_page_pool_free(&_manager->pools[i], FREE_ALL_PAGES, true);
+ 
+ 	kobject_put(&_manager->kobj);
+ 	_manager = NULL;
+diff -Naur a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c	2015-03-26 14:42:38.746435422 +0530
+@@ -411,11 +411,12 @@
+  *
+  * @pool: to free the pages from
+  * @nr_free: If set to true will free all pages in pool
+- * @gfp: GFP flags.
++ * @use_static: Safe to use static buffer
+  **/
+ static unsigned ttm_dma_page_pool_free(struct dma_pool *pool, unsigned nr_free,
+-				       gfp_t gfp)
++				       bool use_static)
+ {
++	static struct page *static_buf[NUM_PAGES_TO_ALLOC];
+ 	unsigned long irq_flags;
+ 	struct dma_page *dma_p, *tmp;
+ 	struct page **pages_to_free;
+@@ -432,7 +433,11 @@
+ 			 npages_to_free, nr_free);
+ 	}
+ #endif
+-	pages_to_free = kmalloc(npages_to_free * sizeof(struct page *), gfp);
++	if (use_static)
++		pages_to_free = static_buf;
++	else
++		pages_to_free = kmalloc(npages_to_free * sizeof(struct page *),
++					GFP_KERNEL);
+ 
+ 	if (!pages_to_free) {
+ 		pr_err("%s: Failed to allocate memory for pool free operation\n",
+@@ -502,7 +507,8 @@
+ 	if (freed_pages)
+ 		ttm_dma_pages_put(pool, &d_pages, pages_to_free, freed_pages);
+ out:
+-	kfree(pages_to_free);
++	if (pages_to_free != static_buf)
++		kfree(pages_to_free);
+ 	return nr_free;
+ }
+ 
+@@ -531,7 +537,8 @@
+ 		if (pool->type != type)
+ 			continue;
+ 		/* Takes a spinlock.. */
+-		ttm_dma_page_pool_free(pool, FREE_ALL_PAGES, GFP_KERNEL);
++		/* OK to use static buffer since global mutex is held. */
++		ttm_dma_page_pool_free(pool, FREE_ALL_PAGES, true);
+ 		WARN_ON(((pool->npages_in_use + pool->npages_free) != 0));
+ 		/* This code path is called after _all_ references to the
+ 		 * struct device has been dropped - so nobody should be
+@@ -848,6 +855,7 @@
+ 	if (count) {
+ 		d_page = list_first_entry(&pool->free_list, struct dma_page, page_list);
+ 		ttm->pages[index] = d_page->p;
++		ttm_dma->cpu_address[index] = d_page->vaddr;
+ 		ttm_dma->dma_address[index] = d_page->dma;
+ 		list_move_tail(&d_page->page_list, &ttm_dma->pages_list);
+ 		r = 0;
+@@ -979,12 +987,13 @@
+ 	INIT_LIST_HEAD(&ttm_dma->pages_list);
+ 	for (i = 0; i < ttm->num_pages; i++) {
+ 		ttm->pages[i] = NULL;
++		ttm_dma->cpu_address[i] = 0;
+ 		ttm_dma->dma_address[i] = 0;
+ 	}
+ 
+ 	/* shrink pool if necessary (only on !is_cached pools)*/
+ 	if (npages)
+-		ttm_dma_page_pool_free(pool, npages, GFP_KERNEL);
++		ttm_dma_page_pool_free(pool, npages, false);
+ 	ttm->state = tt_unpopulated;
+ }
+ EXPORT_SYMBOL_GPL(ttm_dma_unpopulate);
+@@ -994,8 +1003,6 @@
+  *
+  * XXX: (dchinner) Deadlock warning!
+  *
+- * We need to pass sc->gfp_mask to ttm_dma_page_pool_free().
+- *
+  * I'm getting sadder as I hear more pathetical whimpers about needing per-pool
+  * shrinkers
+  */
+@@ -1028,8 +1035,8 @@
+ 		if (++idx < pool_offset)
+ 			continue;
+ 		nr_free = shrink_pages;
+-		shrink_pages = ttm_dma_page_pool_free(p->pool, nr_free,
+-						      sc->gfp_mask);
++		/* OK to use static buffer since global mutex is held. */
++		shrink_pages = ttm_dma_page_pool_free(p->pool, nr_free, true);
+ 		freed += nr_free - shrink_pages;
+ 
+ 		pr_debug("%s: (%s:%d) Asked to shrink %d, have %d more to go\n",
+diff -Naur a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
+--- a/drivers/gpu/drm/ttm/ttm_tt.c	2015-03-26 14:43:30.490436437 +0530
++++ b/drivers/gpu/drm/ttm/ttm_tt.c	2015-03-26 14:42:38.746435422 +0530
+@@ -55,9 +55,12 @@
+ 
+ static void ttm_dma_tt_alloc_page_directory(struct ttm_dma_tt *ttm)
+ {
+-	ttm->ttm.pages = drm_calloc_large(ttm->ttm.num_pages, sizeof(void*));
+-	ttm->dma_address = drm_calloc_large(ttm->ttm.num_pages,
+-					    sizeof(*ttm->dma_address));
++	ttm->ttm.pages = drm_calloc_large(ttm->ttm.num_pages,
++					  sizeof(*ttm->ttm.pages) +
++					  sizeof(*ttm->dma_address) +
++					  sizeof(*ttm->cpu_address));
++	ttm->cpu_address = (void *) (ttm->ttm.pages + ttm->ttm.num_pages);
++	ttm->dma_address = (void *) (ttm->cpu_address + ttm->ttm.num_pages);
+ }
+ 
+ #ifdef CONFIG_X86
+@@ -228,7 +231,7 @@
+ 
+ 	INIT_LIST_HEAD(&ttm_dma->pages_list);
+ 	ttm_dma_tt_alloc_page_directory(ttm_dma);
+-	if (!ttm->pages || !ttm_dma->dma_address) {
++	if (!ttm->pages) {
+ 		ttm_tt_destroy(ttm);
+ 		pr_err("Failed allocating page table\n");
+ 		return -ENOMEM;
+@@ -243,7 +246,7 @@
+ 
+ 	drm_free_large(ttm->pages);
+ 	ttm->pages = NULL;
+-	drm_free_large(ttm_dma->dma_address);
++	ttm_dma->cpu_address = NULL;
+ 	ttm_dma->dma_address = NULL;
+ }
+ EXPORT_SYMBOL(ttm_dma_tt_fini);
+diff -Naur a/fs/dcache.c b/fs/dcache.c
+--- a/fs/dcache.c	2015-03-26 14:43:29.274436413 +0530
++++ b/fs/dcache.c	2015-03-26 14:42:38.746435422 +0530
+@@ -3115,7 +3115,7 @@
+ 		end = ERR_PTR(-ENAMETOOLONG);
+ 	return end;
+ }
+-
++EXPORT_SYMBOL(simple_dname);
+ /*
+  * Write full pathname from the root of the filesystem into the buffer.
+  */
+diff -Naur a/include/acpi/video.h b/include/acpi/video.h
+--- a/include/acpi/video.h	2015-03-26 14:43:28.078436390 +0530
++++ b/include/acpi/video.h	2015-03-26 14:42:38.746435422 +0530
+@@ -19,16 +19,20 @@
+ #if (defined CONFIG_ACPI_VIDEO || defined CONFIG_ACPI_VIDEO_MODULE)
+ extern int acpi_video_register(void);
+ extern void acpi_video_unregister(void);
++extern void acpi_video_unregister_backlight(void);
+ extern int acpi_video_get_edid(struct acpi_device *device, int type,
+ 			       int device_id, void **edid);
++extern bool acpi_video_verify_backlight_support(void);
+ #else
+ static inline int acpi_video_register(void) { return 0; }
+ static inline void acpi_video_unregister(void) { return; }
++static inline void acpi_video_unregister_backlight(void) { return; }
+ static inline int acpi_video_get_edid(struct acpi_device *device, int type,
+ 				      int device_id, void **edid)
+ {
+ 	return -ENODEV;
+ }
++static inline bool acpi_video_verify_backlight_support(void) { return false; }
+ #endif
+ 
+ #endif
+diff -Naur a/include/asm-generic/pci-dma-compat.h b/include/asm-generic/pci-dma-compat.h
+--- a/include/asm-generic/pci-dma-compat.h	2015-03-26 14:43:27.886436386 +0530
++++ b/include/asm-generic/pci-dma-compat.h	2015-03-26 14:42:38.746435422 +0530
+@@ -19,6 +19,14 @@
+ 	return dma_alloc_coherent(hwdev == NULL ? NULL : &hwdev->dev, size, dma_handle, GFP_ATOMIC);
+ }
+ 
++static inline void *
++pci_zalloc_consistent(struct pci_dev *hwdev, size_t size,
++		      dma_addr_t *dma_handle)
++{
++	return dma_zalloc_coherent(hwdev == NULL ? NULL : &hwdev->dev,
++				   size, dma_handle, GFP_ATOMIC);
++}
++
+ static inline void
+ pci_free_consistent(struct pci_dev *hwdev, size_t size,
+ 		    void *vaddr, dma_addr_t dma_handle)
+diff -Naur a/include/drm/ati_pcigart.h b/include/drm/ati_pcigart.h
+--- a/include/drm/ati_pcigart.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/ati_pcigart.h	2015-03-26 14:42:38.746435422 +0530
+@@ -0,0 +1,30 @@
++#ifndef DRM_ATI_PCIGART_H
++#define DRM_ATI_PCIGART_H
++
++#include <drm/drm_legacy.h>
++
++/* location of GART table */
++#define DRM_ATI_GART_MAIN 1
++#define DRM_ATI_GART_FB   2
++
++#define DRM_ATI_GART_PCI 1
++#define DRM_ATI_GART_PCIE 2
++#define DRM_ATI_GART_IGP 3
++
++struct drm_ati_pcigart_info {
++	int gart_table_location;
++	int gart_reg_if;
++	void *addr;
++	dma_addr_t bus_addr;
++	dma_addr_t table_mask;
++	struct drm_dma_handle *table_handle;
++	struct drm_local_map mapping;
++	int table_size;
++};
++
++extern int drm_ati_pcigart_init(struct drm_device *dev,
++				struct drm_ati_pcigart_info * gart_info);
++extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
++				   struct drm_ati_pcigart_info * gart_info);
++
++#endif
+diff -Naur a/include/drm/drm_agpsupport.h b/include/drm/drm_agpsupport.h
+--- a/include/drm/drm_agpsupport.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/drm_agpsupport.h	2015-03-26 14:42:38.746435422 +0530
+@@ -1,12 +1,32 @@
+ #ifndef _DRM_AGPSUPPORT_H_
+ #define _DRM_AGPSUPPORT_H_
+ 
++#include <linux/agp_backend.h>
+ #include <linux/kernel.h>
++#include <linux/list.h>
+ #include <linux/mm.h>
+ #include <linux/mutex.h>
+ #include <linux/types.h>
+-#include <linux/agp_backend.h>
+-#include <drm/drmP.h>
++#include <uapi/drm/drm.h>
++
++struct drm_device;
++struct drm_file;
++
++#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && \
++					      defined(MODULE)))
++
++struct drm_agp_head {
++	struct agp_kern_info agp_info;
++	struct list_head memory;
++	unsigned long mode;
++	struct agp_bridge_data *bridge;
++	int enabled;
++	int acquired;
++	unsigned long base;
++	int agp_mtrr;
++	int cant_use_aperture;
++	unsigned long page_mask;
++};
+ 
+ #if __OS_HAS_AGP
+ 
+@@ -45,6 +65,7 @@
+ int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request);
+ int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
+ 		       struct drm_file *file_priv);
++
+ #else /* __OS_HAS_AGP */
+ 
+ static inline void drm_free_agp(struct agp_memory * handle, int pages)
+@@ -172,6 +193,7 @@
+ {
+ 	return -ENODEV;
+ }
++
+ #endif /* __OS_HAS_AGP */
+ 
+ #endif /* _DRM_AGPSUPPORT_H_ */
+diff -Naur a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
+--- a/include/drm/drm_atomic.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_atomic.h	2015-03-26 14:42:38.750435422 +0530
+@@ -0,0 +1,69 @@
++/*
++ * Copyright (C) 2014 Red Hat
++ * Copyright (C) 2014 Intel Corp.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rob Clark <robdclark@gmail.com>
++ * Daniel Vetter <daniel.vetter@ffwll.ch>
++ */
++
++#ifndef DRM_ATOMIC_H_
++#define DRM_ATOMIC_H_
++
++#include <drm/drm_crtc.h>
++
++struct drm_atomic_state * __must_check
++drm_atomic_state_alloc(struct drm_device *dev);
++void drm_atomic_state_clear(struct drm_atomic_state *state);
++void drm_atomic_state_free(struct drm_atomic_state *state);
++
++struct drm_crtc_state * __must_check
++drm_atomic_get_crtc_state(struct drm_atomic_state *state,
++			  struct drm_crtc *crtc);
++struct drm_plane_state * __must_check
++drm_atomic_get_plane_state(struct drm_atomic_state *state,
++			   struct drm_plane *plane);
++struct drm_connector_state * __must_check
++drm_atomic_get_connector_state(struct drm_atomic_state *state,
++			       struct drm_connector *connector);
++
++int __must_check
++drm_atomic_set_crtc_for_plane(struct drm_atomic_state *state,
++			      struct drm_plane *plane, struct drm_crtc *crtc);
++void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
++				 struct drm_framebuffer *fb);
++int __must_check
++drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
++				  struct drm_crtc *crtc);
++int __must_check
++drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
++				   struct drm_crtc *crtc);
++int
++drm_atomic_connectors_for_crtc(struct drm_atomic_state *state,
++			       struct drm_crtc *crtc);
++
++void drm_atomic_legacy_backoff(struct drm_atomic_state *state);
++
++int __must_check drm_atomic_check_only(struct drm_atomic_state *state);
++int __must_check drm_atomic_commit(struct drm_atomic_state *state);
++int __must_check drm_atomic_async_commit(struct drm_atomic_state *state);
++
++#endif /* DRM_ATOMIC_H_ */
+diff -Naur a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
+--- a/include/drm/drm_atomic_helper.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_atomic_helper.h	2015-03-26 14:42:38.750435422 +0530
+@@ -0,0 +1,126 @@
++/*
++ * Copyright (C) 2014 Red Hat
++ * Copyright (C) 2014 Intel Corp.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rob Clark <robdclark@gmail.com>
++ * Daniel Vetter <daniel.vetter@ffwll.ch>
++ */
++
++#ifndef DRM_ATOMIC_HELPER_H_
++#define DRM_ATOMIC_HELPER_H_
++
++#include <drm/drm_crtc.h>
++
++int drm_atomic_helper_check(struct drm_device *dev,
++			    struct drm_atomic_state *state);
++int drm_atomic_helper_commit(struct drm_device *dev,
++			     struct drm_atomic_state *state,
++			     bool async);
++
++void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
++					struct drm_atomic_state *old_state);
++
++void drm_atomic_helper_commit_pre_planes(struct drm_device *dev,
++					 struct drm_atomic_state *state);
++void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
++					  struct drm_atomic_state *old_state);
++
++int drm_atomic_helper_prepare_planes(struct drm_device *dev,
++				     struct drm_atomic_state *state);
++void drm_atomic_helper_commit_planes(struct drm_device *dev,
++				     struct drm_atomic_state *state);
++void drm_atomic_helper_cleanup_planes(struct drm_device *dev,
++				      struct drm_atomic_state *old_state);
++
++void drm_atomic_helper_swap_state(struct drm_device *dev,
++				  struct drm_atomic_state *state);
++
++/* implementations for legacy interfaces */
++int drm_atomic_helper_update_plane(struct drm_plane *plane,
++				   struct drm_crtc *crtc,
++				   struct drm_framebuffer *fb,
++				   int crtc_x, int crtc_y,
++				   unsigned int crtc_w, unsigned int crtc_h,
++				   uint32_t src_x, uint32_t src_y,
++				   uint32_t src_w, uint32_t src_h);
++int drm_atomic_helper_disable_plane(struct drm_plane *plane);
++int drm_atomic_helper_set_config(struct drm_mode_set *set);
++
++int drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc,
++					struct drm_property *property,
++					uint64_t val);
++int drm_atomic_helper_plane_set_property(struct drm_plane *plane,
++					struct drm_property *property,
++					uint64_t val);
++int drm_atomic_helper_connector_set_property(struct drm_connector *connector,
++					struct drm_property *property,
++					uint64_t val);
++int drm_atomic_helper_page_flip(struct drm_crtc *crtc,
++				struct drm_framebuffer *fb,
++				struct drm_pending_vblank_event *event,
++				uint32_t flags);
++
++/* default implementations for state handling */
++void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc);
++struct drm_crtc_state *
++drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc);
++void drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
++					  struct drm_crtc_state *state);
++
++void drm_atomic_helper_plane_reset(struct drm_plane *plane);
++struct drm_plane_state *
++drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane);
++void drm_atomic_helper_plane_destroy_state(struct drm_plane *plane,
++					  struct drm_plane_state *state);
++
++void drm_atomic_helper_connector_reset(struct drm_connector *connector);
++struct drm_connector_state *
++drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector);
++void drm_atomic_helper_connector_destroy_state(struct drm_connector *connector,
++					  struct drm_connector_state *state);
++
++/**
++ * drm_atomic_crtc_for_each_plane - iterate over planes currently attached to CRTC
++ * @plane: the loop cursor
++ * @crtc:  the crtc whose planes are iterated
++ *
++ * This iterates over the current state, useful (for example) when applying
++ * atomic state after it has been checked and swapped.  To iterate over the
++ * planes which *will* be attached (for ->atomic_check()) see
++ * drm_crtc_for_each_pending_plane()
++ */
++#define drm_atomic_crtc_for_each_plane(plane, crtc) \
++	drm_for_each_plane_mask(plane, (crtc)->dev, (crtc)->state->plane_mask)
++
++/**
++ * drm_crtc_atomic_state_for_each_plane - iterate over attached planes in new state
++ * @plane: the loop cursor
++ * @crtc_state: the incoming crtc-state
++ *
++ * Similar to drm_crtc_for_each_plane(), but iterates the planes that will be
++ * attached if the specified state is applied.  Useful during (for example)
++ * ->atomic_check() operations, to validate the incoming state
++ */
++#define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \
++	drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)
++
++#endif /* DRM_ATOMIC_HELPER_H_ */
+diff -Naur a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
+--- a/include/drm/drm_crtc.h	2015-03-26 14:43:27.886436386 +0530
++++ b/include/drm/drm_crtc.h	2015-03-26 14:42:38.750435422 +0530
+@@ -31,9 +31,9 @@
+ #include <linux/idr.h>
+ #include <linux/fb.h>
+ #include <linux/hdmi.h>
+-#include <drm/drm_mode.h>
+-
+-#include <drm/drm_fourcc.h>
++#include <uapi/drm/drm_mode.h>
++#include <uapi/drm/drm_fourcc.h>
++#include <drm/drm_modeset_lock.h>
+ 
+ struct drm_device;
+ struct drm_mode_set;
+@@ -41,6 +41,8 @@
+ struct drm_object_properties;
+ struct drm_file;
+ struct drm_clip_rect;
++struct device_node;
++struct fence;
+ 
+ #define DRM_MODE_OBJECT_CRTC 0xcccccccc
+ #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
+@@ -51,6 +53,7 @@
+ #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
+ #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
+ #define DRM_MODE_OBJECT_BRIDGE 0xbdbdbdbd
++#define DRM_MODE_OBJECT_ANY 0
+ 
+ struct drm_mode_object {
+ 	uint32_t id;
+@@ -65,130 +68,31 @@
+ 	uint64_t values[DRM_OBJECT_MAX_PROPERTY];
+ };
+ 
+-/*
+- * Note on terminology:  here, for brevity and convenience, we refer to connector
+- * control chips as 'CRTCs'.  They can control any type of connector, VGA, LVDS,
+- * DVI, etc.  And 'screen' refers to the whole of the visible display, which
+- * may span multiple monitors (and therefore multiple CRTC and connector
+- * structures).
+- */
+-
+-enum drm_mode_status {
+-    MODE_OK	= 0,	/* Mode OK */
+-    MODE_HSYNC,		/* hsync out of range */
+-    MODE_VSYNC,		/* vsync out of range */
+-    MODE_H_ILLEGAL,	/* mode has illegal horizontal timings */
+-    MODE_V_ILLEGAL,	/* mode has illegal horizontal timings */
+-    MODE_BAD_WIDTH,	/* requires an unsupported linepitch */
+-    MODE_NOMODE,	/* no mode with a matching name */
+-    MODE_NO_INTERLACE,	/* interlaced mode not supported */
+-    MODE_NO_DBLESCAN,	/* doublescan mode not supported */
+-    MODE_NO_VSCAN,	/* multiscan mode not supported */
+-    MODE_MEM,		/* insufficient video memory */
+-    MODE_VIRTUAL_X,	/* mode width too large for specified virtual size */
+-    MODE_VIRTUAL_Y,	/* mode height too large for specified virtual size */
+-    MODE_MEM_VIRT,	/* insufficient video memory given virtual size */
+-    MODE_NOCLOCK,	/* no fixed clock available */
+-    MODE_CLOCK_HIGH,	/* clock required is too high */
+-    MODE_CLOCK_LOW,	/* clock required is too low */
+-    MODE_CLOCK_RANGE,	/* clock/mode isn't in a ClockRange */
+-    MODE_BAD_HVALUE,	/* horizontal timing was out of range */
+-    MODE_BAD_VVALUE,	/* vertical timing was out of range */
+-    MODE_BAD_VSCAN,	/* VScan value out of range */
+-    MODE_HSYNC_NARROW,	/* horizontal sync too narrow */
+-    MODE_HSYNC_WIDE,	/* horizontal sync too wide */
+-    MODE_HBLANK_NARROW,	/* horizontal blanking too narrow */
+-    MODE_HBLANK_WIDE,	/* horizontal blanking too wide */
+-    MODE_VSYNC_NARROW,	/* vertical sync too narrow */
+-    MODE_VSYNC_WIDE,	/* vertical sync too wide */
+-    MODE_VBLANK_NARROW,	/* vertical blanking too narrow */
+-    MODE_VBLANK_WIDE,	/* vertical blanking too wide */
+-    MODE_PANEL,         /* exceeds panel dimensions */
+-    MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */
+-    MODE_ONE_WIDTH,     /* only one width is supported */
+-    MODE_ONE_HEIGHT,    /* only one height is supported */
+-    MODE_ONE_SIZE,      /* only one resolution is supported */
+-    MODE_NO_REDUCED,    /* monitor doesn't accept reduced blanking */
+-    MODE_NO_STEREO,	/* stereo modes not supported */
+-    MODE_UNVERIFIED = -3, /* mode needs to reverified */
+-    MODE_BAD = -2,	/* unspecified reason */
+-    MODE_ERROR	= -1	/* error condition */
+-};
+-
+-#define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
+-				    DRM_MODE_TYPE_CRTC_C)
+-
+-#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
+-	.name = nm, .status = 0, .type = (t), .clock = (c), \
+-	.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
+-	.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
+-	.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
+-	.vscan = (vs), .flags = (f), \
+-	.base.type = DRM_MODE_OBJECT_MODE
+-
+-#define CRTC_INTERLACE_HALVE_V	(1 << 0) /* halve V values for interlacing */
+-#define CRTC_STEREO_DOUBLE	(1 << 1) /* adjust timings for stereo modes */
+-
+-#define DRM_MODE_FLAG_3D_MAX	DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+-
+-struct drm_display_mode {
+-	/* Header */
+-	struct list_head head;
+-	struct drm_mode_object base;
+-
+-	char name[DRM_DISPLAY_MODE_LEN];
++static inline int64_t U642I64(uint64_t val)
++{
++	return (int64_t)*((int64_t *)&val);
++}
++static inline uint64_t I642U64(int64_t val)
++{
++	return (uint64_t)*((uint64_t *)&val);
++}
+ 
+-	enum drm_mode_status status;
+-	unsigned int type;
++/* rotation property bits */
++#define DRM_ROTATE_0	0
++#define DRM_ROTATE_90	1
++#define DRM_ROTATE_180	2
++#define DRM_ROTATE_270	3
++#define DRM_REFLECT_X	4
++#define DRM_REFLECT_Y	5
+ 
+-	/* Proposed mode values */
+-	int clock;		/* in kHz */
+-	int hdisplay;
+-	int hsync_start;
+-	int hsync_end;
+-	int htotal;
+-	int hskew;
+-	int vdisplay;
+-	int vsync_start;
+-	int vsync_end;
+-	int vtotal;
+-	int vscan;
+-	unsigned int flags;
+-
+-	/* Addressable image size (may be 0 for projectors, etc.) */
+-	int width_mm;
+-	int height_mm;
+-
+-	/* Actual mode we give to hw */
+-	int crtc_clock;		/* in KHz */
+-	int crtc_hdisplay;
+-	int crtc_hblank_start;
+-	int crtc_hblank_end;
+-	int crtc_hsync_start;
+-	int crtc_hsync_end;
+-	int crtc_htotal;
+-	int crtc_hskew;
+-	int crtc_vdisplay;
+-	int crtc_vblank_start;
+-	int crtc_vblank_end;
+-	int crtc_vsync_start;
+-	int crtc_vsync_end;
+-	int crtc_vtotal;
+-
+-	/* Driver private mode info */
+-	int private_size;
+-	int *private;
+-	int private_flags;
+-
+-	int vrefresh;		/* in Hz */
+-	int hsync;		/* in kHz */
+-	enum hdmi_picture_aspect picture_aspect_ratio;
++enum drm_connector_force {
++	DRM_FORCE_UNSPECIFIED,
++	DRM_FORCE_OFF,
++	DRM_FORCE_ON,         /* force on analog part normally */
++	DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */
+ };
+ 
+-static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
+-{
+-	return mode->flags & DRM_MODE_FLAG_3D_MASK;
+-}
++#include <drm/drm_modes.h>
+ 
+ enum drm_connector_status {
+ 	connector_status_connected = 1,
+@@ -227,17 +131,28 @@
+ 	enum subpixel_order subpixel_order;
+ 	u32 color_formats;
+ 
++	/* Mask of supported hdmi deep color modes */
++	u8 edid_hdmi_dc_modes;
++
+ 	u8 cea_rev;
+ };
+ 
++/* data corresponds to displayid vend/prod/serial */
++struct drm_tile_group {
++	struct kref refcount;
++	struct drm_device *dev;
++	int id;
++	u8 group_data[8];
++};
++
+ struct drm_framebuffer_funcs {
+ 	/* note: use drm_framebuffer_remove() */
+ 	void (*destroy)(struct drm_framebuffer *framebuffer);
+ 	int (*create_handle)(struct drm_framebuffer *fb,
+ 			     struct drm_file *file_priv,
+ 			     unsigned int *handle);
+-	/**
+-	 * Optinal callback for the dirty fb ioctl.
++	/*
++	 * Optional callback for the dirty fb ioctl.
+ 	 *
+ 	 * Userspace can notify the driver via this callback
+ 	 * that a area of the framebuffer has changed and should
+@@ -290,7 +205,7 @@
+ struct drm_property_blob {
+ 	struct drm_mode_object base;
+ 	struct list_head head;
+-	unsigned int length;
++	size_t length;
+ 	unsigned char data[];
+ };
+ 
+@@ -307,8 +222,9 @@
+ 	char name[DRM_PROP_NAME_LEN];
+ 	uint32_t num_values;
+ 	uint64_t *values;
++	struct drm_device *dev;
+ 
+-	struct list_head enum_blob_list;
++	struct list_head enum_list;
+ };
+ 
+ struct drm_crtc;
+@@ -317,19 +233,65 @@
+ struct drm_pending_vblank_event;
+ struct drm_plane;
+ struct drm_bridge;
++struct drm_atomic_state;
++
++/**
++ * struct drm_crtc_state - mutable CRTC state
++ * @enable: whether the CRTC should be enabled, gates all other state
++ * @mode_changed: for use by helpers and drivers when computing state updates
++ * @plane_mask: bitmask of (1 << drm_plane_index(plane)) of attached planes
++ * @last_vblank_count: for helpers and drivers to capture the vblank of the
++ * 	update to ensure framebuffer cleanup isn't done too early
++ * @planes_changed: for use by helpers and drivers when computing state updates
++ * @adjusted_mode: for use by helpers and drivers to compute adjusted mode timings
++ * @mode: current mode timings
++ * @event: optional pointer to a DRM event to signal upon completion of the
++ * 	state update
++ * @state: backpointer to global drm_atomic_state
++ */
++struct drm_crtc_state {
++	bool enable;
++
++	/* computed state bits used by helpers and drivers */
++	bool planes_changed : 1;
++	bool mode_changed : 1;
++
++	/* attached planes bitmask:
++	 * WARNING: transitional helpers do not maintain plane_mask so
++	 * drivers not converted over to atomic helpers should not rely
++	 * on plane_mask being accurate!
++	 */
++	u32 plane_mask;
++
++	/* last_vblank_count: for vblank waits before cleanup */
++	u32 last_vblank_count;
++
++	/* adjusted_mode: for use by helpers and drivers */
++	struct drm_display_mode adjusted_mode;
++
++	struct drm_display_mode mode;
++
++	struct drm_pending_vblank_event *event;
++
++	struct drm_atomic_state *state;
++};
+ 
+ /**
+- * drm_crtc_funcs - control CRTCs for a given device
++ * struct drm_crtc_funcs - control CRTCs for a given device
+  * @save: save CRTC state
+  * @restore: restore CRTC state
+  * @reset: reset CRTC after state has been invalidated (e.g. resume)
+  * @cursor_set: setup the cursor
++ * @cursor_set2: setup the cursor with hotspot, superseeds @cursor_set if set
+  * @cursor_move: move the cursor
+  * @gamma_set: specify color ramp for CRTC
+  * @destroy: deinit and free object
+  * @set_property: called when a property is changed
+  * @set_config: apply a new CRTC configuration
+  * @page_flip: initiate a page flip
++ * @atomic_duplicate_state: duplicate the atomic state for this CRTC
++ * @atomic_destroy_state: destroy an atomic state for this CRTC
++ * @atomic_set_property: set a property on an atomic state for this CRTC
+  *
+  * The drm_crtc_funcs structure is the central CRTC management structure
+  * in the DRM.  Each CRTC controls one or more connectors (note that the name
+@@ -380,13 +342,28 @@
+ 
+ 	int (*set_property)(struct drm_crtc *crtc,
+ 			    struct drm_property *property, uint64_t val);
++
++	/* atomic update handling */
++	struct drm_crtc_state *(*atomic_duplicate_state)(struct drm_crtc *crtc);
++	void (*atomic_destroy_state)(struct drm_crtc *crtc,
++				     struct drm_crtc_state *state);
++	int (*atomic_set_property)(struct drm_crtc *crtc,
++				   struct drm_crtc_state *state,
++				   struct drm_property *property,
++				   uint64_t val);
+ };
+ 
+ /**
+- * drm_crtc - central CRTC control structure
++ * struct drm_crtc - central CRTC control structure
+  * @dev: parent DRM device
++ * @port: OF node used by drm_of_find_possible_crtcs()
+  * @head: list management
++ * @mutex: per-CRTC locking
+  * @base: base KMS object for ID tracking etc.
++ * @primary: primary plane for this CRTC
++ * @cursor: cursor plane for this CRTC
++ * @cursor_x: current x position of the cursor, used for universal cursor planes
++ * @cursor_y: current y position of the cursor, used for universal cursor planes
+  * @enabled: is this CRTC enabled?
+  * @mode: current mode timings
+  * @hwmode: mode timings as programmed to hw regs
+@@ -399,35 +376,40 @@
+  * @gamma_size: size of gamma ramp
+  * @gamma_store: gamma ramp values
+  * @framedur_ns: precise frame timing
+- * @framedur_ns: precise line timing
++ * @linedur_ns: precise line timing
+  * @pixeldur_ns: precise pixel timing
+  * @helper_private: mid-layer private data
+  * @properties: property tracking for this CRTC
++ * @state: current atomic state for this CRTC
++ * @acquire_ctx: per-CRTC implicit acquire context used by atomic drivers for
++ * 	legacy ioctls
+  *
+  * Each CRTC may have one or more connectors associated with it.  This structure
+  * allows the CRTC to be controlled.
+  */
+ struct drm_crtc {
+ 	struct drm_device *dev;
++	struct device_node *port;
+ 	struct list_head head;
+ 
+-	/**
++	/*
+ 	 * crtc mutex
+ 	 *
+ 	 * This provides a read lock for the overall crtc state (mode, dpms
+ 	 * state, ...) and a write lock for everything which can be update
+ 	 * without a full modeset (fb, cursor data, ...)
+ 	 */
+-	struct mutex mutex;
++	struct drm_modeset_lock mutex;
+ 
+ 	struct drm_mode_object base;
+ 
+-	/* framebuffer the connector is currently bound to */
+-	struct drm_framebuffer *fb;
+-
+-	/* Temporary tracking of the old fb while a modeset is ongoing. Used
+-	 * by drm_mode_set_config_internal to implement correct refcounting. */
+-	struct drm_framebuffer *old_fb;
++	/* primary and cursor planes for CRTC */
++	struct drm_plane *primary;
++	struct drm_plane *cursor;
++
++	/* position of cursor plane on crtc */
++	int cursor_x;
++	int cursor_y;
+ 
+ 	bool enabled;
+ 
+@@ -455,11 +437,32 @@
+ 	void *helper_private;
+ 
+ 	struct drm_object_properties properties;
++
++	struct drm_crtc_state *state;
++
++	/*
++	 * For legacy crtc ioctls so that atomic drivers can get at the locking
++	 * acquire context.
++	 */
++	struct drm_modeset_acquire_ctx *acquire_ctx;
+ };
+ 
++/**
++ * struct drm_connector_state - mutable connector state
++ * @crtc: CRTC to connect connector to, NULL if disabled
++ * @best_encoder: can be used by helpers and drivers to select the encoder
++ * @state: backpointer to global drm_atomic_state
++ */
++struct drm_connector_state {
++	struct drm_crtc *crtc;  /* do not write directly, use drm_atomic_set_crtc_for_connector() */
++
++	struct drm_encoder *best_encoder;
++
++	struct drm_atomic_state *state;
++};
+ 
+ /**
+- * drm_connector_funcs - control connectors on a given device
++ * struct drm_connector_funcs - control connectors on a given device
+  * @dpms: set power state (see drm_crtc_funcs above)
+  * @save: save connector state
+  * @restore: restore connector state
+@@ -469,6 +472,9 @@
+  * @set_property: property for this connector may need an update
+  * @destroy: make object go away
+  * @force: notify the driver that the connector is forced on
++ * @atomic_duplicate_state: duplicate the atomic state for this connector
++ * @atomic_destroy_state: destroy an atomic state for this connector
++ * @atomic_set_property: set a property on an atomic state for this connector
+  *
+  * Each CRTC may have one or more connectors attached to it.  The functions
+  * below allow the core DRM code to control connectors, enumerate available modes,
+@@ -493,10 +499,19 @@
+ 			     uint64_t val);
+ 	void (*destroy)(struct drm_connector *connector);
+ 	void (*force)(struct drm_connector *connector);
++
++	/* atomic update handling */
++	struct drm_connector_state *(*atomic_duplicate_state)(struct drm_connector *connector);
++	void (*atomic_destroy_state)(struct drm_connector *connector,
++				     struct drm_connector_state *state);
++	int (*atomic_set_property)(struct drm_connector *connector,
++				   struct drm_connector_state *state,
++				   struct drm_property *property,
++				   uint64_t val);
+ };
+ 
+ /**
+- * drm_encoder_funcs - encoder controls
++ * struct drm_encoder_funcs - encoder controls
+  * @reset: reset state (e.g. at init or resume time)
+  * @destroy: cleanup and free associated data
+  *
+@@ -510,10 +525,11 @@
+ #define DRM_CONNECTOR_MAX_ENCODER 3
+ 
+ /**
+- * drm_encoder - central DRM encoder structure
++ * struct drm_encoder - central DRM encoder structure
+  * @dev: parent DRM device
+  * @head: list management
+  * @base: base KMS object
++ * @name: encoder name
+  * @encoder_type: one of the %DRM_MODE_ENCODER_<foo> types in drm_mode.h
+  * @possible_crtcs: bitmask of potential CRTC bindings
+  * @possible_clones: bitmask of potential sibling encoders for cloning
+@@ -530,6 +546,7 @@
+ 	struct list_head head;
+ 
+ 	struct drm_mode_object base;
++	char *name;
+ 	int encoder_type;
+ 	uint32_t possible_crtcs;
+ 	uint32_t possible_clones;
+@@ -540,13 +557,6 @@
+ 	void *helper_private;
+ };
+ 
+-enum drm_connector_force {
+-	DRM_FORCE_UNSPECIFIED,
+-	DRM_FORCE_OFF,
+-	DRM_FORCE_ON,         /* force on analog part normally */
+-	DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */
+-};
+-
+ /* should we poll this connector for connects and disconnects */
+ /* hot plug detectable */
+ #define DRM_CONNECTOR_POLL_HPD (1 << 0)
+@@ -559,16 +569,18 @@
+ #define MAX_ELD_BYTES	128
+ 
+ /**
+- * drm_connector - central DRM connector control structure
++ * struct drm_connector - central DRM connector control structure
+  * @dev: parent DRM device
+  * @kdev: kernel device for sysfs attributes
+  * @attr: sysfs attributes
+  * @head: list management
+  * @base: base KMS object
++ * @name: connector name
+  * @connector_type: one of the %DRM_MODE_CONNECTOR_<foo> types from drm_mode.h
+  * @connector_type_id: index into connector type enum
+  * @interlace_allowed: can this connector handle interlaced modes?
+  * @doublescan_allowed: can this connector handle doublescan?
++ * @stereo_allowed: can this connector handle stereo modes?
+  * @modes: modes available on this connector (from fill_modes() + user)
+  * @status: one of the drm_connector_status enums (connected, not, or unknown)
+  * @probed_modes: list of modes derived directly from the display
+@@ -576,10 +588,13 @@
+  * @funcs: connector control functions
+  * @edid_blob_ptr: DRM property containing EDID if present
+  * @properties: property tracking for this connector
++ * @path_blob_ptr: DRM blob property data for the DP MST path property
+  * @polled: a %DRM_CONNECTOR_POLL_<foo> value for core driven polling
+  * @dpms: current dpms state
+  * @helper_private: mid-layer private data
++ * @cmdline_mode: mode line parsed from the kernel cmdline for this connector
+  * @force: a %DRM_FORCE_<foo> state for forced mode sets
++ * @override_edid: has the EDID been overwritten through debugfs for testing?
+  * @encoder_ids: valid encoders for this connector
+  * @encoder: encoder driving this connector, if any
+  * @eld: EDID-like data, if present
+@@ -589,6 +604,18 @@
+  * @video_latency: video latency info from ELD, if found
+  * @audio_latency: audio latency info from ELD, if found
+  * @null_edid_counter: track sinks that give us all zeros for the EDID
++ * @bad_edid_counter: track sinks that give us an EDID with invalid checksum
++ * @debugfs_entry: debugfs directory for this connector
++ * @state: current atomic state for this connector
++ * @has_tile: is this connector connected to a tiled monitor
++ * @tile_group: tile group for the connected monitor
++ * @tile_is_single_monitor: whether the tile is one monitor housing
++ * @num_h_tile: number of horizontal tiles in the tile group
++ * @num_v_tile: number of vertical tiles in the tile group
++ * @tile_h_loc: horizontal location of this tile
++ * @tile_v_loc: vertical location of this tile
++ * @tile_h_size: horizontal size of this tile.
++ * @tile_v_size: vertical size of this tile.
+  *
+  * Each connector may be connected to one or more CRTCs, or may be clonable by
+  * another connector if they can share a CRTC.  Each connector also has a specific
+@@ -603,6 +630,7 @@
+ 
+ 	struct drm_mode_object base;
+ 
++	char *name;
+ 	int connector_type;
+ 	int connector_type_id;
+ 	bool interlace_allowed;
+@@ -621,6 +649,10 @@
+ 	struct drm_property_blob *edid_blob_ptr;
+ 	struct drm_object_properties properties;
+ 
++	struct drm_property_blob *path_blob_ptr;
++
++	struct drm_property_blob *tile_blob_ptr;
++
+ 	uint8_t polled; /* DRM_CONNECTOR_POLL_* */
+ 
+ 	/* requested DPMS state */
+@@ -629,7 +661,9 @@
+ 	void *helper_private;
+ 
+ 	/* forced on connector */
++	struct drm_cmdline_mode cmdline_mode;
+ 	enum drm_connector_force force;
++	bool override_edid;
+ 	uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
+ 	struct drm_encoder *encoder; /* currently active encoder */
+ 
+@@ -642,14 +676,65 @@
+ 	int audio_latency[2];
+ 	int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */
+ 	unsigned bad_edid_counter;
++
++	struct dentry *debugfs_entry;
++
++	struct drm_connector_state *state;
++
++	/* DisplayID bits */
++	bool has_tile;
++	struct drm_tile_group *tile_group;
++	bool tile_is_single_monitor;
++
++	uint8_t num_h_tile, num_v_tile;
++	uint8_t tile_h_loc, tile_v_loc;
++	uint16_t tile_h_size, tile_v_size;
++};
++
++/**
++ * struct drm_plane_state - mutable plane state
++ * @crtc: currently bound CRTC, NULL if disabled
++ * @fb: currently bound framebuffer
++ * @fence: optional fence to wait for before scanning out @fb
++ * @crtc_x: left position of visible portion of plane on crtc
++ * @crtc_y: upper position of visible portion of plane on crtc
++ * @crtc_w: width of visible portion of plane on crtc
++ * @crtc_h: height of visible portion of plane on crtc
++ * @src_x: left position of visible portion of plane within
++ *	plane (in 16.16)
++ * @src_y: upper position of visible portion of plane within
++ *	plane (in 16.16)
++ * @src_w: width of visible portion of plane (in 16.16)
++ * @src_h: height of visible portion of plane (in 16.16)
++ * @state: backpointer to global drm_atomic_state
++ */
++struct drm_plane_state {
++	struct drm_crtc *crtc;   /* do not write directly, use drm_atomic_set_crtc_for_plane() */
++	struct drm_framebuffer *fb;  /* do not write directly, use drm_atomic_set_fb_for_plane() */
++	struct fence *fence;
++
++	/* Signed dest location allows it to be partially off screen */
++	int32_t crtc_x, crtc_y;
++	uint32_t crtc_w, crtc_h;
++
++	/* Source values are 16.16 fixed point */
++	uint32_t src_x, src_y;
++	uint32_t src_h, src_w;
++
++	struct drm_atomic_state *state;
+ };
+ 
++
+ /**
+- * drm_plane_funcs - driver plane control functions
++ * struct drm_plane_funcs - driver plane control functions
+  * @update_plane: update the plane configuration
+  * @disable_plane: shut down the plane
+  * @destroy: clean up plane resources
++ * @reset: reset plane after state has been invalidated (e.g. resume)
+  * @set_property: called when a property is changed
++ * @atomic_duplicate_state: duplicate the atomic state for this plane
++ * @atomic_destroy_state: destroy an atomic state for this plane
++ * @atomic_set_property: set a property on an atomic state for this plane
+  */
+ struct drm_plane_funcs {
+ 	int (*update_plane)(struct drm_plane *plane,
+@@ -660,13 +745,29 @@
+ 			    uint32_t src_w, uint32_t src_h);
+ 	int (*disable_plane)(struct drm_plane *plane);
+ 	void (*destroy)(struct drm_plane *plane);
++	void (*reset)(struct drm_plane *plane);
+ 
+ 	int (*set_property)(struct drm_plane *plane,
+ 			    struct drm_property *property, uint64_t val);
++
++	/* atomic update handling */
++	struct drm_plane_state *(*atomic_duplicate_state)(struct drm_plane *plane);
++	void (*atomic_destroy_state)(struct drm_plane *plane,
++				     struct drm_plane_state *state);
++	int (*atomic_set_property)(struct drm_plane *plane,
++				   struct drm_plane_state *state,
++				   struct drm_property *property,
++				   uint64_t val);
++};
++
++enum drm_plane_type {
++	DRM_PLANE_TYPE_OVERLAY,
++	DRM_PLANE_TYPE_PRIMARY,
++	DRM_PLANE_TYPE_CURSOR,
+ };
+ 
+ /**
+- * drm_plane - central DRM plane control structure
++ * struct drm_plane - central DRM plane control structure
+  * @dev: DRM device this plane belongs to
+  * @head: for list management
+  * @base: base mode object
+@@ -675,13 +776,19 @@
+  * @format_count: number of formats supported
+  * @crtc: currently bound CRTC
+  * @fb: currently bound fb
++ * @old_fb: Temporary tracking of the old fb while a modeset is ongoing. Used by
++ * 	drm_mode_set_config_internal() to implement correct refcounting.
+  * @funcs: helper functions
+  * @properties: property tracking for this plane
++ * @type: type of plane (overlay, primary, cursor)
++ * @state: current atomic state for this plane
+  */
+ struct drm_plane {
+ 	struct drm_device *dev;
+ 	struct list_head head;
+ 
++	struct drm_modeset_lock mutex;
++
+ 	struct drm_mode_object base;
+ 
+ 	uint32_t possible_crtcs;
+@@ -691,13 +798,21 @@
+ 	struct drm_crtc *crtc;
+ 	struct drm_framebuffer *fb;
+ 
++	struct drm_framebuffer *old_fb;
++
+ 	const struct drm_plane_funcs *funcs;
+ 
+ 	struct drm_object_properties properties;
++
++	enum drm_plane_type type;
++
++	void *helper_private;
++
++	struct drm_plane_state *state;
+ };
+ 
+ /**
+- * drm_bridge_funcs - drm_bridge control functions
++ * struct drm_bridge_funcs - drm_bridge control functions
+  * @mode_fixup: Try to fixup (or reject entirely) proposed mode for this bridge
+  * @disable: Called right before encoder prepare, disables the bridge
+  * @post_disable: Called right after encoder prepare, for lockstepped disable
+@@ -721,7 +836,7 @@
+ };
+ 
+ /**
+- * drm_bridge - central DRM bridge control structure
++ * struct drm_bridge - central DRM bridge control structure
+  * @dev: DRM device this bridge belongs to
+  * @head: list management
+  * @base: base mode object
+@@ -739,8 +854,35 @@
+ };
+ 
+ /**
+- * drm_mode_set - new values for a CRTC config change
+- * @head: list management
++ * struct struct drm_atomic_state - the global state object for atomic updates
++ * @dev: parent DRM device
++ * @flags: state flags like async update
++ * @planes: pointer to array of plane pointers
++ * @plane_states: pointer to array of plane states pointers
++ * @crtcs: pointer to array of CRTC pointers
++ * @crtc_states: pointer to array of CRTC states pointers
++ * @num_connector: size of the @connectors and @connector_states arrays
++ * @connectors: pointer to array of connector pointers
++ * @connector_states: pointer to array of connector states pointers
++ * @acquire_ctx: acquire context for this atomic modeset state update
++ */
++struct drm_atomic_state {
++	struct drm_device *dev;
++	uint32_t flags;
++	struct drm_plane **planes;
++	struct drm_plane_state **plane_states;
++	struct drm_crtc **crtcs;
++	struct drm_crtc_state **crtc_states;
++	int num_connector;
++	struct drm_connector **connectors;
++	struct drm_connector_state **connector_states;
++
++	struct drm_modeset_acquire_ctx *acquire_ctx;
++};
++
++
++/**
++ * struct drm_mode_set - new values for a CRTC config change
+  * @fb: framebuffer to use for new config
+  * @crtc: CRTC whose configuration we're about to change
+  * @mode: mode timings to use
+@@ -770,6 +912,9 @@
+  * struct drm_mode_config_funcs - basic driver provided mode setting functions
+  * @fb_create: create a new framebuffer object
+  * @output_poll_changed: function to handle output configuration changes
++ * @atomic_check: check whether a give atomic state update is possible
++ * @atomic_commit: commit an atomic state update previously verified with
++ * 	atomic_check()
+  *
+  * Some global (i.e. not per-CRTC, connector, etc) mode setting functions that
+  * involve drivers.
+@@ -779,13 +924,20 @@
+ 					     struct drm_file *file_priv,
+ 					     struct drm_mode_fb_cmd2 *mode_cmd);
+ 	void (*output_poll_changed)(struct drm_device *dev);
++
++	int (*atomic_check)(struct drm_device *dev,
++			    struct drm_atomic_state *a);
++	int (*atomic_commit)(struct drm_device *dev,
++			     struct drm_atomic_state *a,
++			     bool async);
+ };
+ 
+ /**
+- * drm_mode_group - group of mode setting resources for potential sub-grouping
++ * struct drm_mode_group - group of mode setting resources for potential sub-grouping
+  * @num_crtcs: CRTC count
+  * @num_encoders: encoder count
+  * @num_connectors: connector count
++ * @num_bridges: bridge count
+  * @id_list: list of KMS object IDs in this group
+  *
+  * Currently this simply tracks the global mode setting state.  But in the
+@@ -805,10 +957,14 @@
+ };
+ 
+ /**
+- * drm_mode_config - Mode configuration control structure
++ * struct drm_mode_config - Mode configuration control structure
+  * @mutex: mutex protecting KMS related lists and structures
++ * @connection_mutex: ww mutex protecting connector state and routing
++ * @acquire_ctx: global implicit acquire context used by atomic drivers for
++ * 	legacy ioctls
+  * @idr_mutex: mutex for KMS ID allocation and management
+  * @crtc_idr: main KMS ID tracking object
++ * @fb_lock: mutex to protect fb state and lists
+  * @num_fb: number of fbs available
+  * @fb_list: list of framebuffers available
+  * @num_connector: number of connectors on this device
+@@ -817,17 +973,28 @@
+  * @bridge_list: list of bridge objects
+  * @num_encoder: number of encoders on this device
+  * @encoder_list: list of encoder objects
++ * @num_overlay_plane: number of overlay planes on this device
++ * @num_total_plane: number of universal (i.e. with primary/curso) planes on this device
++ * @plane_list: list of plane objects
+  * @num_crtc: number of CRTCs on this device
+  * @crtc_list: list of CRTC objects
++ * @property_list: list of property objects
+  * @min_width: minimum pixel width on this device
+  * @min_height: minimum pixel height on this device
+  * @max_width: maximum pixel width on this device
+  * @max_height: maximum pixel height on this device
+  * @funcs: core driver provided mode setting functions
+  * @fb_base: base address of the framebuffer
+- * @poll_enabled: track polling status for this device
++ * @poll_enabled: track polling support for this device
++ * @poll_running: track polling status for this device
+  * @output_poll_work: delayed work for polling in process context
++ * @property_blob_list: list of all the blob property objects
+  * @*_property: core property tracking
++ * @preferred_depth: preferred RBG pixel depth, used by fb helpers
++ * @prefer_shadow: hint to userspace to prefer shadow-fb rendering
++ * @async_page_flip: does this device support async flips on the primary plane?
++ * @cursor_width: hint to userspace for max cursor width
++ * @cursor_height: hint to userspace for max cursor height
+  *
+  * Core mode resource tracking structure.  All CRTC, encoders, and connectors
+  * enumerated by the driver are added here, as are global properties.  Some
+@@ -835,18 +1002,14 @@
+  */
+ struct drm_mode_config {
+ 	struct mutex mutex; /* protects configuration (mode lists etc.) */
++	struct drm_modeset_lock connection_mutex; /* protects connector->encoder and encoder->crtc links */
++	struct drm_modeset_acquire_ctx *acquire_ctx; /* for legacy _lock_all() / _unlock_all() */
+ 	struct mutex idr_mutex; /* for IDR management */
+ 	struct idr crtc_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */
++	struct idr tile_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */
+ 	/* this is limited to one for now */
+ 
+-
+-	/**
+-	 * fb_lock - mutex to protect fb state
+-	 *
+-	 * Besides the global fb list his also protects the fbs list in the
+-	 * file_priv
+-	 */
+-	struct mutex fb_lock;
++	struct mutex fb_lock; /* proctects global and per-file fb lists */
+ 	int num_fb;
+ 	struct list_head fb_list;
+ 
+@@ -856,7 +1019,15 @@
+ 	struct list_head bridge_list;
+ 	int num_encoder;
+ 	struct list_head encoder_list;
+-	int num_plane;
++
++	/*
++	 * Track # of overlay planes separately from # of total planes.  By
++	 * default we only advertise overlay planes to userspace; if userspace
++	 * sets the "universal plane" capability bit, we'll go ahead and
++	 * expose all planes.
++	 */
++	int num_overlay_plane;
++	int num_total_plane;
+ 	struct list_head plane_list;
+ 
+ 	int num_crtc;
+@@ -878,6 +1049,10 @@
+ 	struct list_head property_blob_list;
+ 	struct drm_property *edid_property;
+ 	struct drm_property *dpms_property;
++	struct drm_property *path_property;
++	struct drm_property *tile_property;
++	struct drm_property *plane_type_property;
++	struct drm_property *rotation_property;
+ 
+ 	/* DVI-I properties */
+ 	struct drm_property *dvi_i_subconnector_property;
+@@ -900,8 +1075,13 @@
+ 
+ 	/* Optional properties */
+ 	struct drm_property *scaling_mode_property;
++	struct drm_property *aspect_ratio_property;
+ 	struct drm_property *dirty_info_property;
+ 
++	/* properties for virtual machine layout */
++	struct drm_property *suggested_x_property;
++	struct drm_property *suggested_y_property;
++
+ 	/* dumb ioctl parameters */
+ 	uint32_t preferred_depth, prefer_shadow;
+ 
+@@ -912,6 +1092,19 @@
+ 	uint32_t cursor_width, cursor_height;
+ };
+ 
++/**
++ * drm_for_each_plane_mask - iterate over planes specified by bitmask
++ * @plane: the loop cursor
++ * @dev: the DRM device
++ * @plane_mask: bitmask of plane indices
++ *
++ * Iterate over all planes specified by bitmask.
++ */
++#define drm_for_each_plane_mask(plane, dev, plane_mask) \
++	list_for_each_entry((plane), &(dev)->mode_config.plane_list, head) \
++		if ((plane_mask) & (1 << drm_plane_index(plane)))
++
++
+ #define obj_to_crtc(x) container_of(x, struct drm_crtc, base)
+ #define obj_to_connector(x) container_of(x, struct drm_connector, base)
+ #define obj_to_encoder(x) container_of(x, struct drm_encoder, base)
+@@ -926,13 +1119,11 @@
+ 	char *name;
+ };
+ 
+-extern void drm_modeset_lock_all(struct drm_device *dev);
+-extern void drm_modeset_unlock_all(struct drm_device *dev);
+-extern void drm_warn_on_modeset_not_all_locked(struct drm_device *dev);
+-
+-extern int drm_crtc_init(struct drm_device *dev,
+-			 struct drm_crtc *crtc,
+-			 const struct drm_crtc_funcs *funcs);
++extern int drm_crtc_init_with_planes(struct drm_device *dev,
++				     struct drm_crtc *crtc,
++				     struct drm_plane *primary,
++				     struct drm_plane *cursor,
++				     const struct drm_crtc_funcs *funcs);
+ extern void drm_crtc_cleanup(struct drm_crtc *crtc);
+ extern unsigned int drm_crtc_index(struct drm_crtc *crtc);
+ 
+@@ -954,8 +1145,11 @@
+ 			      struct drm_connector *connector,
+ 			      const struct drm_connector_funcs *funcs,
+ 			      int connector_type);
++int drm_connector_register(struct drm_connector *connector);
++void drm_connector_unregister(struct drm_connector *connector);
+ 
+ extern void drm_connector_cleanup(struct drm_connector *connector);
++extern unsigned int drm_connector_index(struct drm_connector *connector);
+ /* helper to unplug all connectors from sysfs for device */
+ extern void drm_connector_unplug_all(struct drm_device *dev);
+ 
+@@ -981,19 +1175,31 @@
+ 	return !!(encoder->possible_crtcs & drm_crtc_mask(crtc));
+ }
+ 
++extern int drm_universal_plane_init(struct drm_device *dev,
++				    struct drm_plane *plane,
++				    unsigned long possible_crtcs,
++				    const struct drm_plane_funcs *funcs,
++				    const uint32_t *formats,
++				    uint32_t format_count,
++				    enum drm_plane_type type);
+ extern int drm_plane_init(struct drm_device *dev,
+ 			  struct drm_plane *plane,
+ 			  unsigned long possible_crtcs,
+ 			  const struct drm_plane_funcs *funcs,
+ 			  const uint32_t *formats, uint32_t format_count,
+-			  bool priv);
++			  bool is_primary);
+ extern void drm_plane_cleanup(struct drm_plane *plane);
++extern unsigned int drm_plane_index(struct drm_plane *plane);
+ extern void drm_plane_force_disable(struct drm_plane *plane);
++extern int drm_crtc_check_viewport(const struct drm_crtc *crtc,
++				   int x, int y,
++				   const struct drm_display_mode *mode,
++				   const struct drm_framebuffer *fb);
+ 
+ extern void drm_encoder_cleanup(struct drm_encoder *encoder);
+ 
+-extern const char *drm_get_connector_name(const struct drm_connector *connector);
+ extern const char *drm_get_connector_status_name(enum drm_connector_status status);
++extern const char *drm_get_subpixel_order_name(enum subpixel_order order);
+ extern const char *drm_get_dpms_name(int val);
+ extern const char *drm_get_dvi_i_subconnector_name(int val);
+ extern const char *drm_get_dvi_i_select_name(int val);
+@@ -1001,41 +1207,39 @@
+ extern const char *drm_get_tv_select_name(int val);
+ extern void drm_fb_release(struct drm_file *file_priv);
+ extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
++extern void drm_mode_group_destroy(struct drm_mode_group *group);
++extern void drm_reinit_primary_mode_group(struct drm_device *dev);
+ extern bool drm_probe_ddc(struct i2c_adapter *adapter);
+ extern struct edid *drm_get_edid(struct drm_connector *connector,
+ 				 struct i2c_adapter *adapter);
+ extern struct edid *drm_edid_duplicate(const struct edid *edid);
+ extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
+-extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
+-extern void drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src);
+-extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
+-						   const struct drm_display_mode *mode);
+-extern void drm_mode_debug_printmodeline(const struct drm_display_mode *mode);
+ extern void drm_mode_config_init(struct drm_device *dev);
+ extern void drm_mode_config_reset(struct drm_device *dev);
+ extern void drm_mode_config_cleanup(struct drm_device *dev);
+-extern void drm_mode_set_name(struct drm_display_mode *mode);
+-extern bool drm_mode_equal(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2);
+-extern bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2);
+-extern int drm_mode_width(const struct drm_display_mode *mode);
+-extern int drm_mode_height(const struct drm_display_mode *mode);
+-
+-/* for us by fb module */
+-extern struct drm_display_mode *drm_mode_create(struct drm_device *dev);
+-extern void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode);
+-extern void drm_mode_validate_size(struct drm_device *dev,
+-				   struct list_head *mode_list,
+-				   int maxX, int maxY, int maxPitch);
+-extern void drm_mode_prune_invalid(struct drm_device *dev,
+-				   struct list_head *mode_list, bool verbose);
+-extern void drm_mode_sort(struct list_head *mode_list);
+-extern int drm_mode_hsync(const struct drm_display_mode *mode);
+-extern int drm_mode_vrefresh(const struct drm_display_mode *mode);
+-extern void drm_mode_set_crtcinfo(struct drm_display_mode *p,
+-				  int adjust_flags);
+-extern void drm_mode_connector_list_update(struct drm_connector *connector);
++
++extern int drm_mode_connector_set_path_property(struct drm_connector *connector,
++						const char *path);
++int drm_mode_connector_set_tile_property(struct drm_connector *connector);
+ extern int drm_mode_connector_update_edid_property(struct drm_connector *connector,
+-						struct edid *edid);
++						   const struct edid *edid);
++
++static inline bool drm_property_type_is(struct drm_property *property,
++		uint32_t type)
++{
++	/* instanceof for props.. handles extended type vs original types: */
++	if (property->flags & DRM_MODE_PROP_EXTENDED_TYPE)
++		return (property->flags & DRM_MODE_PROP_EXTENDED_TYPE) == type;
++	return property->flags & type;
++}
++
++static inline bool drm_property_type_valid(struct drm_property *property)
++{
++	if (property->flags & DRM_MODE_PROP_EXTENDED_TYPE)
++		return !(property->flags & DRM_MODE_PROP_LEGACY_TYPE);
++	return !!(property->flags & DRM_MODE_PROP_LEGACY_TYPE);
++}
++
+ extern int drm_object_property_set_value(struct drm_mode_object *obj,
+ 					 struct drm_property *property,
+ 					 uint64_t val);
+@@ -1065,28 +1269,35 @@
+ struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
+ 					 int flags, const char *name,
+ 					 const struct drm_prop_enum_list *props,
+-					 int num_values);
++					 int num_props,
++					 uint64_t supported_bits);
+ struct drm_property *drm_property_create_range(struct drm_device *dev, int flags,
+ 					 const char *name,
+ 					 uint64_t min, uint64_t max);
++struct drm_property *drm_property_create_signed_range(struct drm_device *dev,
++					 int flags, const char *name,
++					 int64_t min, int64_t max);
++struct drm_property *drm_property_create_object(struct drm_device *dev,
++					 int flags, const char *name, uint32_t type);
+ extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property);
+ extern int drm_property_add_enum(struct drm_property *property, int index,
+ 				 uint64_t value, const char *name);
+ extern int drm_mode_create_dvi_i_properties(struct drm_device *dev);
+-extern int drm_mode_create_tv_properties(struct drm_device *dev, int num_formats,
+-				     char *formats[]);
++extern int drm_mode_create_tv_properties(struct drm_device *dev,
++					 unsigned int num_modes,
++					 char *modes[]);
+ extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
++extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
+ extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
+-extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
++extern int drm_mode_create_suggested_offset_properties(struct drm_device *dev);
+ 
+ extern int drm_mode_connector_attach_encoder(struct drm_connector *connector,
+ 					     struct drm_encoder *encoder);
+-extern void drm_mode_connector_detach_encoder(struct drm_connector *connector,
+-					   struct drm_encoder *encoder);
+ extern int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
+ 					 int gamma_size);
+ extern struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
+ 		uint32_t id, uint32_t type);
++
+ /* IOCTLs */
+ extern int drm_mode_getresources(struct drm_device *dev,
+ 				 void *data, struct drm_file *file_priv);
+@@ -1132,21 +1343,12 @@
+ extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
+ 				    void *data, struct drm_file *file_priv);
+ extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
++extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
+ extern bool drm_detect_hdmi_monitor(struct edid *edid);
+ extern bool drm_detect_monitor_audio(struct edid *edid);
+ extern bool drm_rgb_quant_range_selectable(struct edid *edid);
+ extern int drm_mode_page_flip_ioctl(struct drm_device *dev,
+ 				    void *data, struct drm_file *file_priv);
+-extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
+-				int hdisplay, int vdisplay, int vrefresh,
+-				bool reduced, bool interlaced, bool margins);
+-extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
+-				int hdisplay, int vdisplay, int vrefresh,
+-				bool interlaced, int margins);
+-extern struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev,
+-				int hdisplay, int vdisplay, int vrefresh,
+-				bool interlaced, int margins, int GTF_M,
+-				int GTF_2C, int GTF_K, int GTF_2J);
+ extern int drm_add_modes_noedid(struct drm_connector *connector,
+ 				int hdisplay, int vdisplay);
+ extern void drm_set_preferred_mode(struct drm_connector *connector,
+@@ -1155,6 +1357,13 @@
+ extern int drm_edid_header_is_valid(const u8 *raw_edid);
+ extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid);
+ extern bool drm_edid_is_valid(struct edid *edid);
++
++extern struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev,
++							 char topology[8]);
++extern struct drm_tile_group *drm_mode_get_tile_group(struct drm_device *dev,
++					       char topology[8]);
++extern void drm_mode_put_tile_group(struct drm_device *dev,
++				   struct drm_tile_group *tg);
+ struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
+ 					   int hsize, int vsize, int fresh,
+ 					   bool rb);
+@@ -1169,6 +1378,9 @@
+ 					     struct drm_file *file_priv);
+ extern int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data,
+ 					   struct drm_file *file_priv);
++extern int drm_mode_plane_set_obj_prop(struct drm_plane *plane,
++				       struct drm_property *property,
++				       uint64_t value);
+ 
+ extern void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth,
+ 				 int *bpp);
+@@ -1177,8 +1389,21 @@
+ extern int drm_format_horz_chroma_subsampling(uint32_t format);
+ extern int drm_format_vert_chroma_subsampling(uint32_t format);
+ extern const char *drm_get_format_name(uint32_t format);
++extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
++							      unsigned int supported_rotations);
++extern unsigned int drm_rotation_simplify(unsigned int rotation,
++					  unsigned int supported_rotations);
+ 
+ /* Helpers */
++
++static inline struct drm_plane *drm_plane_find(struct drm_device *dev,
++		uint32_t id)
++{
++	struct drm_mode_object *mo;
++	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PLANE);
++	return mo ? obj_to_plane(mo) : NULL;
++}
++
+ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
+ 	uint32_t id)
+ {
+@@ -1195,4 +1420,33 @@
+ 	return mo ? obj_to_encoder(mo) : NULL;
+ }
+ 
++static inline struct drm_connector *drm_connector_find(struct drm_device *dev,
++		uint32_t id)
++{
++	struct drm_mode_object *mo;
++	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CONNECTOR);
++	return mo ? obj_to_connector(mo) : NULL;
++}
++
++static inline struct drm_property *drm_property_find(struct drm_device *dev,
++		uint32_t id)
++{
++	struct drm_mode_object *mo;
++	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PROPERTY);
++	return mo ? obj_to_property(mo) : NULL;
++}
++
++static inline struct drm_property_blob *
++drm_property_blob_find(struct drm_device *dev, uint32_t id)
++{
++	struct drm_mode_object *mo;
++	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_BLOB);
++	return mo ? obj_to_blob(mo) : NULL;
++}
++
++/* Plane list iterator for legacy (overlay only) planes. */
++#define drm_for_each_legacy_plane(plane, planelist) \
++	list_for_each_entry(plane, planelist, head) \
++		if (plane->type == DRM_PLANE_TYPE_OVERLAY)
++
+ #endif /* __DRM_CRTC_H__ */
+diff -Naur a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
+--- a/include/drm/drm_crtc_helper.h	2015-03-26 14:43:27.886436386 +0530
++++ b/include/drm/drm_crtc_helper.h	2015-03-26 14:42:38.750435422 +0530
+@@ -68,6 +68,7 @@
+ 	int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode,
+ 			struct drm_display_mode *adjusted_mode, int x, int y,
+ 			struct drm_framebuffer *old_fb);
++	void (*mode_set_nofb)(struct drm_crtc *crtc);
+ 
+ 	/* Move the crtc on the current fb to the given position *optional* */
+ 	int (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
+@@ -81,6 +82,12 @@
+ 
+ 	/* disable crtc when not in use - more explicit than dpms off */
+ 	void (*disable)(struct drm_crtc *crtc);
++
++	/* atomic helpers */
++	int (*atomic_check)(struct drm_crtc *crtc,
++			    struct drm_crtc_state *state);
++	void (*atomic_begin)(struct drm_crtc *crtc);
++	void (*atomic_flush)(struct drm_crtc *crtc);
+ };
+ 
+ /**
+@@ -114,7 +121,7 @@
+ /**
+  * drm_connector_helper_funcs - helper operations for connectors
+  * @get_modes: get mode list for this connector
+- * @mode_valid: is this mode valid on the given connector?
++ * @mode_valid (optional): is this mode valid on the given connector?
+  *
+  * The helper operations are called by the mid-layer CRTC helper.
+  */
+@@ -125,7 +132,6 @@
+ 	struct drm_encoder *(*best_encoder)(struct drm_connector *connector);
+ };
+ 
+-extern int drm_helper_probe_single_connector_modes(struct drm_connector *connector, uint32_t maxX, uint32_t maxY);
+ extern void drm_helper_disable_unused_functions(struct drm_device *dev);
+ extern int drm_crtc_helper_set_config(struct drm_mode_set *set);
+ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+@@ -139,8 +145,8 @@
+ 
+ extern void drm_helper_move_panel_connectors_to_head(struct drm_device *);
+ 
+-extern int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
+-					  struct drm_mode_fb_cmd2 *mode_cmd);
++extern void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
++					   struct drm_mode_fb_cmd2 *mode_cmd);
+ 
+ static inline void drm_crtc_helper_add(struct drm_crtc *crtc,
+ 				       const struct drm_crtc_helper_funcs *funcs)
+@@ -160,7 +166,22 @@
+ 	connector->helper_private = (void *)funcs;
+ }
+ 
+-extern int drm_helper_resume_force_mode(struct drm_device *dev);
++extern void drm_helper_resume_force_mode(struct drm_device *dev);
++
++int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
++			     struct drm_display_mode *adjusted_mode, int x, int y,
++			     struct drm_framebuffer *old_fb);
++int drm_helper_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
++				  struct drm_framebuffer *old_fb);
++
++/* drm_probe_helper.c */
++extern int drm_helper_probe_single_connector_modes(struct drm_connector
++						   *connector, uint32_t maxX,
++						   uint32_t maxY);
++extern int drm_helper_probe_single_connector_modes_nomerge(struct drm_connector
++							   *connector,
++							   uint32_t maxX,
++							   uint32_t maxY);
+ extern void drm_kms_helper_poll_init(struct drm_device *dev);
+ extern void drm_kms_helper_poll_fini(struct drm_device *dev);
+ extern bool drm_helper_hpd_irq_event(struct drm_device *dev);
+diff -Naur a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
+--- a/include/drm/drm_displayid.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_displayid.h	2015-03-26 14:42:38.750435422 +0530
+@@ -0,0 +1,76 @@
++/*
++ * Copyright © 2014 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef DRM_DISPLAYID_H
++#define DRM_DISPLAYID_H
++
++#define DATA_BLOCK_PRODUCT_ID 0x00
++#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
++#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
++#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
++#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
++#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
++#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
++#define DATA_BLOCK_VESA_TIMING 0x07
++#define DATA_BLOCK_CEA_TIMING 0x08
++#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
++#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
++#define DATA_BLOCK_GP_ASCII_STRING 0x0b
++#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
++#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
++#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
++#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
++#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
++#define DATA_BLOCK_TILED_DISPLAY 0x12
++
++#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
++
++#define PRODUCT_TYPE_EXTENSION 0
++#define PRODUCT_TYPE_TEST 1
++#define PRODUCT_TYPE_PANEL 2
++#define PRODUCT_TYPE_MONITOR 3
++#define PRODUCT_TYPE_TV 4
++#define PRODUCT_TYPE_REPEATER 5
++#define PRODUCT_TYPE_DIRECT_DRIVE 6
++
++struct displayid_hdr {
++	u8 rev;
++	u8 bytes;
++	u8 prod_id;
++	u8 ext_count;
++} __packed;
++
++struct displayid_block {
++	u8 tag;
++	u8 rev;
++	u8 num_bytes;
++} __packed;
++
++struct displayid_tiled_block {
++	struct displayid_block base;
++	u8 tile_cap;
++	u8 topo[3];
++	u8 tile_size[4];
++	u8 tile_pixel_bezel[5];
++	u8 topology_id[8];
++} __packed;
++
++#endif
+diff -Naur a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+--- a/include/drm/drm_dp_helper.h	2015-03-26 14:43:27.886436386 +0530
++++ b/include/drm/drm_dp_helper.h	2015-03-26 14:42:38.750435422 +0530
+@@ -37,6 +37,7 @@
+  * eDP: Embedded DisplayPort version 1
+  * DPI: DisplayPort Interoperability Guideline v1.1a
+  * 1.2: DisplayPort 1.2
++ * MST: Multistream Transport - part of DP 1.2a
+  *
+  * 1.2 formally includes both eDP and DPI definitions.
+  */
+@@ -103,9 +104,14 @@
+ #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
+ 
+ /* Multiple stream transport */
++#define DP_FAUX_CAP			    0x020   /* 1.2 */
++# define DP_FAUX_CAP_1			    (1 << 0)
++
+ #define DP_MSTM_CAP			    0x021   /* 1.2 */
+ # define DP_MST_CAP			    (1 << 0)
+ 
++#define DP_GUID				    0x030   /* 1.2 */
++
+ #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
+ # define DP_PSR_IS_SUPPORTED                1
+ #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
+@@ -184,16 +190,16 @@
+ # define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
+ # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
+ # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
+-# define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
+-# define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
+-# define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
+-# define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)
++# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
++# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
++# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
++# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
+ 
+ # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
+-# define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
+-# define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
+-# define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
+-# define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
++# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
++# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
++# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
++# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
+ 
+ # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
+ # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
+@@ -221,6 +227,16 @@
+ # define DP_PSR_CRC_VERIFICATION	    (1 << 2)
+ # define DP_PSR_FRAME_CAPTURE		    (1 << 3)
+ 
++#define DP_ADAPTER_CTRL			    0x1a0
++# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
++
++#define DP_BRANCH_DEVICE_CTRL		    0x1a1
++# define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
++
++#define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
++#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
++#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
++
+ #define DP_SINK_COUNT			    0x200
+ /* prior to 1.2 bit 7 was reserved mbz */
+ # define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
+@@ -230,6 +246,9 @@
+ # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
+ # define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
+ # define DP_CP_IRQ			    (1 << 2)
++# define DP_MCCS_IRQ			    (1 << 3)
++# define DP_DOWN_REP_MSG_RDY		    (1 << 4) /* 1.2 MST */
++# define DP_UP_REQ_MSG_RDY		    (1 << 5) /* 1.2 MST */
+ # define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
+ 
+ #define DP_LANE0_1_STATUS		    0x202
+@@ -279,11 +298,31 @@
+ 
+ #define DP_TEST_PATTERN			    0x221
+ 
++#define DP_TEST_CRC_R_CR		    0x240
++#define DP_TEST_CRC_G_Y			    0x242
++#define DP_TEST_CRC_B_CB		    0x244
++
++#define DP_TEST_SINK_MISC		    0x246
++# define DP_TEST_CRC_SUPPORTED		    (1 << 5)
++# define DP_TEST_COUNT_MASK		    0x7
++
+ #define DP_TEST_RESPONSE		    0x260
+ # define DP_TEST_ACK			    (1 << 0)
+ # define DP_TEST_NAK			    (1 << 1)
+ # define DP_TEST_EDID_CHECKSUM_WRITE	    (1 << 2)
+ 
++#define DP_TEST_EDID_CHECKSUM		    0x261
++
++#define DP_TEST_SINK			    0x270
++# define DP_TEST_SINK_START		    (1 << 0)
++
++#define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
++# define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
++# define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
++
++#define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
++/* up to ID_SLOT_63 at 0x2ff */
++
+ #define DP_SOURCE_OUI			    0x300
+ #define DP_SINK_OUI			    0x400
+ #define DP_BRANCH_OUI			    0x500
+@@ -291,6 +330,22 @@
+ #define DP_SET_POWER                        0x600
+ # define DP_SET_POWER_D0                    0x1
+ # define DP_SET_POWER_D3                    0x2
++# define DP_SET_POWER_MASK                  0x3
++
++#define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
++#define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
++#define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
++#define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */
++
++#define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */
++/* 0-5 sink count */
++# define DP_SINK_COUNT_CP_READY             (1 << 6)
++
++#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
++
++#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
++
++#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
+ 
+ #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
+ # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
+@@ -308,31 +363,48 @@
+ # define DP_PSR_SINK_INTERNAL_ERROR         7
+ # define DP_PSR_SINK_STATE_MASK             0x07
+ 
++/* DP 1.2 Sideband message defines */
++/* peer device type - DP 1.2a Table 2-92 */
++#define DP_PEER_DEVICE_NONE		0x0
++#define DP_PEER_DEVICE_SOURCE_OR_SST	0x1
++#define DP_PEER_DEVICE_MST_BRANCHING	0x2
++#define DP_PEER_DEVICE_SST_SINK		0x3
++#define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
++
++/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
++#define DP_LINK_ADDRESS			0x01
++#define DP_CONNECTION_STATUS_NOTIFY	0x02
++#define DP_ENUM_PATH_RESOURCES		0x10
++#define DP_ALLOCATE_PAYLOAD		0x11
++#define DP_QUERY_PAYLOAD		0x12
++#define DP_RESOURCE_STATUS_NOTIFY	0x13
++#define DP_CLEAR_PAYLOAD_ID_TABLE	0x14
++#define DP_REMOTE_DPCD_READ		0x20
++#define DP_REMOTE_DPCD_WRITE		0x21
++#define DP_REMOTE_I2C_READ		0x22
++#define DP_REMOTE_I2C_WRITE		0x23
++#define DP_POWER_UP_PHY			0x24
++#define DP_POWER_DOWN_PHY		0x25
++#define DP_SINK_EVENT_NOTIFY		0x30
++#define DP_QUERY_STREAM_ENC_STATUS	0x38
++
++/* DP 1.2 MST sideband nak reasons - table 2.84 */
++#define DP_NAK_WRITE_FAILURE		0x01
++#define DP_NAK_INVALID_READ		0x02
++#define DP_NAK_CRC_FAILURE		0x03
++#define DP_NAK_BAD_PARAM		0x04
++#define DP_NAK_DEFER			0x05
++#define DP_NAK_LINK_FAILURE		0x06
++#define DP_NAK_NO_RESOURCES		0x07
++#define DP_NAK_DPCD_FAIL		0x08
++#define DP_NAK_I2C_NAK			0x09
++#define DP_NAK_ALLOCATE_FAIL		0x0a
++
+ #define MODE_I2C_START	1
+ #define MODE_I2C_WRITE	2
+ #define MODE_I2C_READ	4
+ #define MODE_I2C_STOP	8
+ 
+-/**
+- * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
+- * 				 aux algorithm
+- * @running: set by the algo indicating whether an i2c is ongoing or whether
+- * 	     the i2c bus is quiescent
+- * @address: i2c target address for the currently ongoing transfer
+- * @aux_ch: driver callback to transfer a single byte of the i2c payload
+- */
+-struct i2c_algo_dp_aux_data {
+-	bool running;
+-	u16 address;
+-	int (*aux_ch) (struct i2c_adapter *adapter,
+-		       int mode, uint8_t write_byte,
+-		       uint8_t *read_byte);
+-};
+-
+-int
+-i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
+-
+-
+ #define DP_LINK_STATUS_SIZE	   6
+ bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+ 			  int lane_count);
+@@ -398,4 +470,125 @@
+ 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
+ }
+ 
++/*
++ * DisplayPort AUX channel
++ */
++
++/**
++ * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
++ * @address: address of the (first) register to access
++ * @request: contains the type of transaction (see DP_AUX_* macros)
++ * @reply: upon completion, contains the reply type of the transaction
++ * @buffer: pointer to a transmission or reception buffer
++ * @size: size of @buffer
++ */
++struct drm_dp_aux_msg {
++	unsigned int address;
++	u8 request;
++	u8 reply;
++	void *buffer;
++	size_t size;
++};
++
++/**
++ * struct drm_dp_aux - DisplayPort AUX channel
++ * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
++ * @ddc: I2C adapter that can be used for I2C-over-AUX communication
++ * @dev: pointer to struct device that is the parent for this AUX channel
++ * @hw_mutex: internal mutex used for locking transfers
++ * @transfer: transfers a message representing a single AUX transaction
++ *
++ * The .dev field should be set to a pointer to the device that implements
++ * the AUX channel.
++ *
++ * The .name field may be used to specify the name of the I2C adapter. If set to
++ * NULL, dev_name() of .dev will be used.
++ *
++ * Drivers provide a hardware-specific implementation of how transactions
++ * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
++ * structure describing the transaction is passed into this function. Upon
++ * success, the implementation should return the number of payload bytes
++ * that were transferred, or a negative error-code on failure. Helpers
++ * propagate errors from the .transfer() function, with the exception of
++ * the -EBUSY error, which causes a transaction to be retried. On a short,
++ * helpers will return -EPROTO to make it simpler to check for failure.
++ *
++ * An AUX channel can also be used to transport I2C messages to a sink. A
++ * typical application of that is to access an EDID that's present in the
++ * sink device. The .transfer() function can also be used to execute such
++ * transactions. The drm_dp_aux_register_i2c_bus() function registers an
++ * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
++ * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter.
++ *
++ * Note that the aux helper code assumes that the .transfer() function
++ * only modifies the reply field of the drm_dp_aux_msg structure.  The
++ * retry logic and i2c helpers assume this is the case.
++ */
++struct drm_dp_aux {
++	const char *name;
++	struct i2c_adapter ddc;
++	struct device *dev;
++	struct mutex hw_mutex;
++	ssize_t (*transfer)(struct drm_dp_aux *aux,
++			    struct drm_dp_aux_msg *msg);
++	unsigned i2c_nack_count, i2c_defer_count;
++};
++
++ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
++			 void *buffer, size_t size);
++ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
++			  void *buffer, size_t size);
++
++/**
++ * drm_dp_dpcd_readb() - read a single byte from the DPCD
++ * @aux: DisplayPort AUX channel
++ * @offset: address of the register to read
++ * @valuep: location where the value of the register will be stored
++ *
++ * Returns the number of bytes transferred (1) on success, or a negative
++ * error code on failure.
++ */
++static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
++					unsigned int offset, u8 *valuep)
++{
++	return drm_dp_dpcd_read(aux, offset, valuep, 1);
++}
++
++/**
++ * drm_dp_dpcd_writeb() - write a single byte to the DPCD
++ * @aux: DisplayPort AUX channel
++ * @offset: address of the register to write
++ * @value: value to write to the register
++ *
++ * Returns the number of bytes transferred (1) on success, or a negative
++ * error code on failure.
++ */
++static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
++					 unsigned int offset, u8 value)
++{
++	return drm_dp_dpcd_write(aux, offset, &value, 1);
++}
++
++int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
++				 u8 status[DP_LINK_STATUS_SIZE]);
++
++/*
++ * DisplayPort link
++ */
++#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
++
++struct drm_dp_link {
++	unsigned char revision;
++	unsigned int rate;
++	unsigned int num_lanes;
++	unsigned long capabilities;
++};
++
++int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
++int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
++int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
++
++int drm_dp_aux_register(struct drm_dp_aux *aux);
++void drm_dp_aux_unregister(struct drm_dp_aux *aux);
++
+ #endif /* _DRM_DP_HELPER_H_ */
+diff -Naur a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
+--- a/include/drm/drm_dp_mst_helper.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_dp_mst_helper.h	2015-03-26 14:42:38.750435422 +0530
+@@ -0,0 +1,513 @@
++/*
++ * Copyright © 2014 Red Hat.
++ *
++ * Permission to use, copy, modify, distribute, and sell this software and its
++ * documentation for any purpose is hereby granted without fee, provided that
++ * the above copyright notice appear in all copies and that both that copyright
++ * notice and this permission notice appear in supporting documentation, and
++ * that the name of the copyright holders not be used in advertising or
++ * publicity pertaining to distribution of the software without specific,
++ * written prior permission.  The copyright holders make no representations
++ * about the suitability of this software for any purpose.  It is provided "as
++ * is" without express or implied warranty.
++ *
++ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
++ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
++ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
++ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
++ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
++ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
++ * OF THIS SOFTWARE.
++ */
++#ifndef _DRM_DP_MST_HELPER_H_
++#define _DRM_DP_MST_HELPER_H_
++
++#include <linux/types.h>
++#include <drm/drm_dp_helper.h>
++
++struct drm_dp_mst_branch;
++
++/**
++ * struct drm_dp_vcpi - Virtual Channel Payload Identifier
++ * @vcpi: Virtual channel ID.
++ * @pbn: Payload Bandwidth Number for this channel
++ * @aligned_pbn: PBN aligned with slot size
++ * @num_slots: number of slots for this PBN
++ */
++struct drm_dp_vcpi {
++	int vcpi;
++	int pbn;
++	int aligned_pbn;
++	int num_slots;
++};
++
++/**
++ * struct drm_dp_mst_port - MST port
++ * @kref: reference count for this port.
++ * @guid_valid: for DP 1.2 devices if we have validated the GUID.
++ * @guid: guid for DP 1.2 device on this port.
++ * @port_num: port number
++ * @input: if this port is an input port.
++ * @mcs: message capability status - DP 1.2 spec.
++ * @ddps: DisplayPort Device Plug Status - DP 1.2
++ * @pdt: Peer Device Type
++ * @ldps: Legacy Device Plug Status
++ * @dpcd_rev: DPCD revision of device on this port
++ * @num_sdp_streams: Number of simultaneous streams
++ * @num_sdp_stream_sinks: Number of stream sinks
++ * @available_pbn: Available bandwidth for this port.
++ * @next: link to next port on this branch device
++ * @mstb: branch device attach below this port
++ * @aux: i2c aux transport to talk to device connected to this port.
++ * @parent: branch device parent of this port
++ * @vcpi: Virtual Channel Payload info for this port.
++ * @connector: DRM connector this port is connected to.
++ * @mgr: topology manager this port lives under.
++ *
++ * This structure represents an MST port endpoint on a device somewhere
++ * in the MST topology.
++ */
++struct drm_dp_mst_port {
++	struct kref kref;
++
++	/* if dpcd 1.2 device is on this port - its GUID info */
++	bool guid_valid;
++	u8 guid[16];
++
++	u8 port_num;
++	bool input;
++	bool mcs;
++	bool ddps;
++	u8 pdt;
++	bool ldps;
++	u8 dpcd_rev;
++	u8 num_sdp_streams;
++	u8 num_sdp_stream_sinks;
++	uint16_t available_pbn;
++	struct list_head next;
++	struct drm_dp_mst_branch *mstb; /* pointer to an mstb if this port has one */
++	struct drm_dp_aux aux; /* i2c bus for this port? */
++	struct drm_dp_mst_branch *parent;
++
++	struct drm_dp_vcpi vcpi;
++	struct drm_connector *connector;
++	struct drm_dp_mst_topology_mgr *mgr;
++
++	struct edid *cached_edid; /* for DP logical ports - make tiling work */
++};
++
++/**
++ * struct drm_dp_mst_branch - MST branch device.
++ * @kref: reference count for this port.
++ * @rad: Relative Address to talk to this branch device.
++ * @lct: Link count total to talk to this branch device.
++ * @num_ports: number of ports on the branch.
++ * @msg_slots: one bit per transmitted msg slot.
++ * @ports: linked list of ports on this branch.
++ * @port_parent: pointer to the port parent, NULL if toplevel.
++ * @mgr: topology manager for this branch device.
++ * @tx_slots: transmission slots for this device.
++ * @last_seqno: last sequence number used to talk to this.
++ * @link_address_sent: if a link address message has been sent to this device yet.
++ *
++ * This structure represents an MST branch device, there is one
++ * primary branch device at the root, along with any others connected
++ * to downstream ports
++ */
++struct drm_dp_mst_branch {
++	struct kref kref;
++	u8 rad[8];
++	u8 lct;
++	int num_ports;
++
++	int msg_slots;
++	struct list_head ports;
++
++	/* list of tx ops queue for this port */
++	struct drm_dp_mst_port *port_parent;
++	struct drm_dp_mst_topology_mgr *mgr;
++
++	/* slots are protected by mstb->mgr->qlock */
++	struct drm_dp_sideband_msg_tx *tx_slots[2];
++	int last_seqno;
++	bool link_address_sent;
++};
++
++
++/* sideband msg header - not bit struct */
++struct drm_dp_sideband_msg_hdr {
++	u8 lct;
++	u8 lcr;
++	u8 rad[8];
++	bool broadcast;
++	bool path_msg;
++	u8 msg_len;
++	bool somt;
++	bool eomt;
++	bool seqno;
++};
++
++struct drm_dp_nak_reply {
++	u8 guid[16];
++	u8 reason;
++	u8 nak_data;
++};
++
++struct drm_dp_link_address_ack_reply {
++	u8 guid[16];
++	u8 nports;
++	struct drm_dp_link_addr_reply_port {
++		bool input_port;
++		u8 peer_device_type;
++		u8 port_number;
++		bool mcs;
++		bool ddps;
++		bool legacy_device_plug_status;
++		u8 dpcd_revision;
++		u8 peer_guid[16];
++		u8 num_sdp_streams;
++		u8 num_sdp_stream_sinks;
++	} ports[16];
++};
++
++struct drm_dp_remote_dpcd_read_ack_reply {
++	u8 port_number;
++	u8 num_bytes;
++	u8 bytes[255];
++};
++
++struct drm_dp_remote_dpcd_write_ack_reply {
++	u8 port_number;
++};
++
++struct drm_dp_remote_dpcd_write_nak_reply {
++	u8 port_number;
++	u8 reason;
++	u8 bytes_written_before_failure;
++};
++
++struct drm_dp_remote_i2c_read_ack_reply {
++	u8 port_number;
++	u8 num_bytes;
++	u8 bytes[255];
++};
++
++struct drm_dp_remote_i2c_read_nak_reply {
++	u8 port_number;
++	u8 nak_reason;
++	u8 i2c_nak_transaction;
++};
++
++struct drm_dp_remote_i2c_write_ack_reply {
++	u8 port_number;
++};
++
++
++struct drm_dp_sideband_msg_rx {
++	u8 chunk[48];
++	u8 msg[256];
++	u8 curchunk_len;
++	u8 curchunk_idx; /* chunk we are parsing now */
++	u8 curchunk_hdrlen;
++	u8 curlen; /* total length of the msg */
++	bool have_somt;
++	bool have_eomt;
++	struct drm_dp_sideband_msg_hdr initial_hdr;
++};
++
++
++struct drm_dp_allocate_payload {
++	u8 port_number;
++	u8 number_sdp_streams;
++	u8 vcpi;
++	u16 pbn;
++	u8 sdp_stream_sink[8];
++};
++
++struct drm_dp_allocate_payload_ack_reply {
++	u8 port_number;
++	u8 vcpi;
++	u16 allocated_pbn;
++};
++
++struct drm_dp_connection_status_notify {
++	u8 guid[16];
++	u8 port_number;
++	bool legacy_device_plug_status;
++	bool displayport_device_plug_status;
++	bool message_capability_status;
++	bool input_port;
++	u8 peer_device_type;
++};
++
++struct drm_dp_remote_dpcd_read {
++	u8 port_number;
++	u32 dpcd_address;
++	u8 num_bytes;
++};
++
++struct drm_dp_remote_dpcd_write {
++	u8 port_number;
++	u32 dpcd_address;
++	u8 num_bytes;
++	u8 *bytes;
++};
++
++struct drm_dp_remote_i2c_read {
++	u8 num_transactions;
++	u8 port_number;
++	struct {
++		u8 i2c_dev_id;
++		u8 num_bytes;
++		u8 *bytes;
++		u8 no_stop_bit;
++		u8 i2c_transaction_delay;
++	} transactions[4];
++	u8 read_i2c_device_id;
++	u8 num_bytes_read;
++};
++
++struct drm_dp_remote_i2c_write {
++	u8 port_number;
++	u8 write_i2c_device_id;
++	u8 num_bytes;
++	u8 *bytes;
++};
++
++/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */
++struct drm_dp_port_number_req {
++	u8 port_number;
++};
++
++struct drm_dp_enum_path_resources_ack_reply {
++	u8 port_number;
++	u16 full_payload_bw_number;
++	u16 avail_payload_bw_number;
++};
++
++/* covers POWER_DOWN_PHY, POWER_UP_PHY */
++struct drm_dp_port_number_rep {
++	u8 port_number;
++};
++
++struct drm_dp_query_payload {
++	u8 port_number;
++	u8 vcpi;
++};
++
++struct drm_dp_resource_status_notify {
++	u8 port_number;
++	u8 guid[16];
++	u16 available_pbn;
++};
++
++struct drm_dp_query_payload_ack_reply {
++	u8 port_number;
++	u8 allocated_pbn;
++};
++
++struct drm_dp_sideband_msg_req_body {
++	u8 req_type;
++	union ack_req {
++		struct drm_dp_connection_status_notify conn_stat;
++		struct drm_dp_port_number_req port_num;
++		struct drm_dp_resource_status_notify resource_stat;
++
++		struct drm_dp_query_payload query_payload;
++		struct drm_dp_allocate_payload allocate_payload;
++
++		struct drm_dp_remote_dpcd_read dpcd_read;
++		struct drm_dp_remote_dpcd_write dpcd_write;
++
++		struct drm_dp_remote_i2c_read i2c_read;
++		struct drm_dp_remote_i2c_write i2c_write;
++	} u;
++};
++
++struct drm_dp_sideband_msg_reply_body {
++	u8 reply_type;
++	u8 req_type;
++	union ack_replies {
++		struct drm_dp_nak_reply nak;
++		struct drm_dp_link_address_ack_reply link_addr;
++		struct drm_dp_port_number_rep port_number;
++
++		struct drm_dp_enum_path_resources_ack_reply path_resources;
++		struct drm_dp_allocate_payload_ack_reply allocate_payload;
++		struct drm_dp_query_payload_ack_reply query_payload;
++
++		struct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;
++		struct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;
++		struct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;
++
++		struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;
++		struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;
++		struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;
++	} u;
++};
++
++/* msg is queued to be put into a slot */
++#define DRM_DP_SIDEBAND_TX_QUEUED 0
++/* msg has started transmitting on a slot - still on msgq */
++#define DRM_DP_SIDEBAND_TX_START_SEND 1
++/* msg has finished transmitting on a slot - removed from msgq only in slot */
++#define DRM_DP_SIDEBAND_TX_SENT 2
++/* msg has received a response - removed from slot */
++#define DRM_DP_SIDEBAND_TX_RX 3
++#define DRM_DP_SIDEBAND_TX_TIMEOUT 4
++
++struct drm_dp_sideband_msg_tx {
++	u8 msg[256];
++	u8 chunk[48];
++	u8 cur_offset;
++	u8 cur_len;
++	struct drm_dp_mst_branch *dst;
++	struct list_head next;
++	int seqno;
++	int state;
++	bool path_msg;
++	struct drm_dp_sideband_msg_reply_body reply;
++};
++
++/* sideband msg handler */
++struct drm_dp_mst_topology_mgr;
++struct drm_dp_mst_topology_cbs {
++	/* create a connector for a port */
++	struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path);
++	void (*destroy_connector)(struct drm_dp_mst_topology_mgr *mgr,
++				  struct drm_connector *connector);
++	void (*hotplug)(struct drm_dp_mst_topology_mgr *mgr);
++
++};
++
++#define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8)
++
++#define DP_PAYLOAD_LOCAL 1
++#define DP_PAYLOAD_REMOTE 2
++#define DP_PAYLOAD_DELETE_LOCAL 3
++
++struct drm_dp_payload {
++	int payload_state;
++	int start_slot;
++	int num_slots;
++	int vcpi;
++};
++
++/**
++ * struct drm_dp_mst_topology_mgr - DisplayPort MST manager
++ * @dev: device pointer for adding i2c devices etc.
++ * @cbs: callbacks for connector addition and destruction.
++ * @max_dpcd_transaction_bytes - maximum number of bytes to read/write in one go.
++ * @aux: aux channel for the DP connector.
++ * @max_payloads: maximum number of payloads the GPU can generate.
++ * @conn_base_id: DRM connector ID this mgr is connected to.
++ * @down_rep_recv: msg receiver state for down replies.
++ * @up_req_recv: msg receiver state for up requests.
++ * @lock: protects mst state, primary, guid, dpcd.
++ * @mst_state: if this manager is enabled for an MST capable port.
++ * @mst_primary: pointer to the primary branch device.
++ * @guid_valid: GUID valid for the primary branch device.
++ * @guid: GUID for primary port.
++ * @dpcd: cache of DPCD for primary port.
++ * @pbn_div: PBN to slots divisor.
++ *
++ * This struct represents the toplevel displayport MST topology manager.
++ * There should be one instance of this for every MST capable DP connector
++ * on the GPU.
++ */
++struct drm_dp_mst_topology_mgr {
++
++	struct device *dev;
++	struct drm_dp_mst_topology_cbs *cbs;
++	int max_dpcd_transaction_bytes;
++	struct drm_dp_aux *aux; /* auxch for this topology mgr to use */
++	int max_payloads;
++	int conn_base_id;
++
++	/* only ever accessed from the workqueue - which should be serialised */
++	struct drm_dp_sideband_msg_rx down_rep_recv;
++	struct drm_dp_sideband_msg_rx up_req_recv;
++
++	/* pointer to info about the initial MST device */
++	struct mutex lock; /* protects mst_state + primary + guid + dpcd */
++
++	bool mst_state;
++	struct drm_dp_mst_branch *mst_primary;
++	/* primary MST device GUID */
++	bool guid_valid;
++	u8 guid[16];
++	u8 dpcd[DP_RECEIVER_CAP_SIZE];
++	u8 sink_count;
++	int pbn_div;
++	int total_slots;
++	int avail_slots;
++	int total_pbn;
++
++	/* messages to be transmitted */
++	/* qlock protects the upq/downq and in_progress,
++	   the mstb tx_slots and txmsg->state once they are queued */
++	struct mutex qlock;
++	struct list_head tx_msg_downq;
++	struct list_head tx_msg_upq;
++	bool tx_down_in_progress;
++	bool tx_up_in_progress;
++
++	/* payload info + lock for it */
++	struct mutex payload_lock;
++	struct drm_dp_vcpi **proposed_vcpis;
++	struct drm_dp_payload *payloads;
++	unsigned long payload_mask;
++	unsigned long vcpi_mask;
++
++	wait_queue_head_t tx_waitq;
++	struct work_struct work;
++
++	struct work_struct tx_work;
++};
++
++int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, int conn_base_id);
++
++void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr);
++
++
++int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state);
++
++
++int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled);
++
++
++enum drm_connector_status drm_dp_mst_detect_port(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
++
++struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
++
++
++int drm_dp_calc_pbn_mode(int clock, int bpp);
++
++
++bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn, int *slots);
++
++
++void drm_dp_mst_reset_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
++
++
++void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr,
++				struct drm_dp_mst_port *port);
++
++
++int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr,
++			   int pbn);
++
++
++int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr);
++
++
++int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr);
++
++int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr);
++
++void drm_dp_mst_dump_topology(struct seq_file *m,
++			      struct drm_dp_mst_topology_mgr *mgr);
++
++void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr);
++int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr);
++#endif
+diff -Naur a/include/drm/drm_edid.h b/include/drm/drm_edid.h
+--- a/include/drm/drm_edid.h	2015-03-26 14:43:27.886436386 +0530
++++ b/include/drm/drm_edid.h	2015-03-26 14:42:38.754435422 +0530
+@@ -27,12 +27,14 @@
+ 
+ #define EDID_LENGTH 128
+ #define DDC_ADDR 0x50
++#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
+ 
+ #define CEA_EXT	    0x02
+ #define VTB_EXT	    0x10
+ #define DI_EXT	    0x40
+ #define LS_EXT	    0x50
+ #define MI_EXT	    0x60
++#define DISPLAYID_EXT 0x70
+ 
+ struct est_timings {
+ 	u8 t1;
+@@ -202,6 +204,66 @@
+ #define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
+ #define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
+ 
++#define DRM_EDID_HDMI_DC_48               (1 << 6)
++#define DRM_EDID_HDMI_DC_36               (1 << 5)
++#define DRM_EDID_HDMI_DC_30               (1 << 4)
++#define DRM_EDID_HDMI_DC_Y444             (1 << 3)
++
++/* ELD Header Block */
++#define DRM_ELD_HEADER_BLOCK_SIZE	4
++
++#define DRM_ELD_VER			0
++# define DRM_ELD_VER_SHIFT		3
++# define DRM_ELD_VER_MASK		(0x1f << 3)
++
++#define DRM_ELD_BASELINE_ELD_LEN	2	/* in dwords! */
++
++/* ELD Baseline Block for ELD_Ver == 2 */
++#define DRM_ELD_CEA_EDID_VER_MNL	4
++# define DRM_ELD_CEA_EDID_VER_SHIFT	5
++# define DRM_ELD_CEA_EDID_VER_MASK	(7 << 5)
++# define DRM_ELD_CEA_EDID_VER_NONE	(0 << 5)
++# define DRM_ELD_CEA_EDID_VER_CEA861	(1 << 5)
++# define DRM_ELD_CEA_EDID_VER_CEA861A	(2 << 5)
++# define DRM_ELD_CEA_EDID_VER_CEA861BCD	(3 << 5)
++# define DRM_ELD_MNL_SHIFT		0
++# define DRM_ELD_MNL_MASK		(0x1f << 0)
++
++#define DRM_ELD_SAD_COUNT_CONN_TYPE	5
++# define DRM_ELD_SAD_COUNT_SHIFT	4
++# define DRM_ELD_SAD_COUNT_MASK		(0xf << 4)
++# define DRM_ELD_CONN_TYPE_SHIFT	2
++# define DRM_ELD_CONN_TYPE_MASK		(3 << 2)
++# define DRM_ELD_CONN_TYPE_HDMI		(0 << 2)
++# define DRM_ELD_CONN_TYPE_DP		(1 << 2)
++# define DRM_ELD_SUPPORTS_AI		(1 << 1)
++# define DRM_ELD_SUPPORTS_HDCP		(1 << 0)
++
++#define DRM_ELD_AUD_SYNCH_DELAY		6	/* in units of 2 ms */
++# define DRM_ELD_AUD_SYNCH_DELAY_MAX	0xfa	/* 500 ms */
++
++#define DRM_ELD_SPEAKER			7
++# define DRM_ELD_SPEAKER_RLRC		(1 << 6)
++# define DRM_ELD_SPEAKER_FLRC		(1 << 5)
++# define DRM_ELD_SPEAKER_RC		(1 << 4)
++# define DRM_ELD_SPEAKER_RLR		(1 << 3)
++# define DRM_ELD_SPEAKER_FC		(1 << 2)
++# define DRM_ELD_SPEAKER_LFE		(1 << 1)
++# define DRM_ELD_SPEAKER_FLR		(1 << 0)
++
++#define DRM_ELD_PORT_ID			8	/* offsets 8..15 inclusive */
++# define DRM_ELD_PORT_ID_LEN		8
++
++#define DRM_ELD_MANUFACTURER_NAME0	16
++#define DRM_ELD_MANUFACTURER_NAME1	17
++
++#define DRM_ELD_PRODUCT_CODE0		18
++#define DRM_ELD_PRODUCT_CODE1		19
++
++#define DRM_ELD_MONITOR_NAME_STRING	20	/* offsets 20..(20+mnl-1) inclusive */
++
++#define DRM_ELD_CEA_SAD(mnl, sad)	(20 + (mnl) + 3 * (sad))
++
+ struct edid {
+ 	u8 header[8];
+ 	/* Vendor & product info */
+@@ -274,4 +336,56 @@
+ drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
+ 					    const struct drm_display_mode *mode);
+ 
++/**
++ * drm_eld_mnl - Get ELD monitor name length in bytes.
++ * @eld: pointer to an eld memory structure with mnl set
++ */
++static inline int drm_eld_mnl(const uint8_t *eld)
++{
++	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
++}
++
++/**
++ * drm_eld_sad_count - Get ELD SAD count.
++ * @eld: pointer to an eld memory structure with sad_count set
++ */
++static inline int drm_eld_sad_count(const uint8_t *eld)
++{
++	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
++		DRM_ELD_SAD_COUNT_SHIFT;
++}
++
++/**
++ * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
++ * @eld: pointer to an eld memory structure with mnl and sad_count set
++ *
++ * This is a helper for determining the payload size of the baseline block, in
++ * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
++ */
++static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
++{
++	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
++		drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
++}
++
++/**
++ * drm_eld_size - Get ELD size in bytes
++ * @eld: pointer to a complete eld memory structure
++ *
++ * The returned value does not include the vendor block. It's vendor specific,
++ * and comprises of the remaining bytes in the ELD memory buffer after
++ * drm_eld_size() bytes of header and baseline block.
++ *
++ * The returned value is guaranteed to be a multiple of 4.
++ */
++static inline int drm_eld_size(const uint8_t *eld)
++{
++	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
++}
++
++struct edid *drm_do_get_edid(struct drm_connector *connector,
++	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
++			      size_t len),
++	void *data);
++
+ #endif /* __DRM_EDID_H__ */
+diff -Naur a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
+--- a/include/drm/drm_fb_helper.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/drm_fb_helper.h	2015-03-26 14:42:38.754435422 +0530
+@@ -34,9 +34,14 @@
+ 
+ #include <linux/kgdb.h>
+ 
++struct drm_fb_offset {
++	int x, y;
++};
++
+ struct drm_fb_helper_crtc {
+ 	struct drm_mode_set mode_set;
+ 	struct drm_display_mode *desired_mode;
++	int x, y;
+ };
+ 
+ struct drm_fb_helper_surface_size {
+@@ -55,7 +60,7 @@
+  *             save the current lut when force-restoring the fbdev for e.g.
+  *             kdbg.
+  * @fb_probe: Driver callback to allocate and initialize the fbdev info
+- *            structure. Futhermore it also needs to allocate the drm
++ *            structure. Furthermore it also needs to allocate the drm
+  *            framebuffer used to back the fbdev.
+  * @initial_config: Setup an initial fbdev display configuration
+  *
+@@ -72,12 +77,12 @@
+ 	bool (*initial_config)(struct drm_fb_helper *fb_helper,
+ 			       struct drm_fb_helper_crtc **crtcs,
+ 			       struct drm_display_mode **modes,
++			       struct drm_fb_offset *offsets,
+ 			       bool *enabled, int width, int height);
+ };
+ 
+ struct drm_fb_helper_connector {
+ 	struct drm_connector *connector;
+-	struct drm_cmdline_mode cmdline_mode;
+ };
+ 
+ struct drm_fb_helper {
+@@ -86,8 +91,9 @@
+ 	int crtc_count;
+ 	struct drm_fb_helper_crtc *crtc_info;
+ 	int connector_count;
++	int connector_info_alloc_count;
+ 	struct drm_fb_helper_connector **connector_info;
+-	struct drm_fb_helper_funcs *funcs;
++	const struct drm_fb_helper_funcs *funcs;
+ 	struct fb_info *fbdev;
+ 	u32 pseudo_palette[17];
+ 	struct list_head kernel_fb_list;
+@@ -97,6 +103,8 @@
+ 	bool delayed_hotplug;
+ };
+ 
++void drm_fb_helper_prepare(struct drm_device *dev, struct drm_fb_helper *helper,
++			   const struct drm_fb_helper_funcs *funcs);
+ int drm_fb_helper_init(struct drm_device *dev,
+ 		       struct drm_fb_helper *helper, int crtc_count,
+ 		       int max_conn);
+@@ -108,7 +116,7 @@
+ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
+ 			    struct fb_info *info);
+ 
+-bool drm_fb_helper_restore_fbdev_mode(struct drm_fb_helper *fb_helper);
++bool drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper);
+ void drm_fb_helper_fill_var(struct fb_info *info, struct drm_fb_helper *fb_helper,
+ 			    uint32_t fb_width, uint32_t fb_height);
+ void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
+@@ -121,5 +129,14 @@
+ int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper *fb_helper);
+ int drm_fb_helper_debug_enter(struct fb_info *info);
+ int drm_fb_helper_debug_leave(struct fb_info *info);
+-
++struct drm_display_mode *
++drm_has_preferred_mode(struct drm_fb_helper_connector *fb_connector,
++			int width, int height);
++struct drm_display_mode *
++drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn,
++		      int width, int height);
++
++int drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper, struct drm_connector *connector);
++int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,
++				       struct drm_connector *connector);
+ #endif
+diff -Naur a/include/drm/drm_flip_work.h b/include/drm/drm_flip_work.h
+--- a/include/drm/drm_flip_work.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/drm_flip_work.h	2015-03-26 14:42:38.754435422 +0530
+@@ -25,6 +25,7 @@
+ #define DRM_FLIP_WORK_H
+ 
+ #include <linux/kfifo.h>
++#include <linux/spinlock.h>
+ #include <linux/workqueue.h>
+ 
+ /**
+@@ -32,9 +33,9 @@
+  *
+  * Util to queue up work to run from work-queue context after flip/vblank.
+  * Typically this can be used to defer unref of framebuffer's, cursor
+- * bo's, etc until after vblank.  The APIs are all safe (and lockless)
+- * for up to one producer and once consumer at a time.  The single-consumer
+- * aspect is ensured by committing the queued work to a single work-queue.
++ * bo's, etc until after vblank.  The APIs are all thread-safe.
++ * Moreover, drm_flip_work_queue_task and drm_flip_work_queue can be called
++ * in atomic context.
+  */
+ 
+ struct drm_flip_work;
+@@ -51,25 +52,40 @@
+ typedef void (*drm_flip_func_t)(struct drm_flip_work *work, void *val);
+ 
+ /**
++ * struct drm_flip_task - flip work task
++ * @node: list entry element
++ * @data: data to pass to work->func
++ */
++struct drm_flip_task {
++	struct list_head node;
++	void *data;
++};
++
++/**
+  * struct drm_flip_work - flip work queue
+  * @name: debug name
+- * @pending: number of queued but not committed items
+- * @count: number of committed items
+  * @func: callback fxn called for each committed item
+  * @worker: worker which calls @func
++ * @queued: queued tasks
++ * @commited: commited tasks
++ * @lock: lock to access queued and commited lists
+  */
+ struct drm_flip_work {
+ 	const char *name;
+-	atomic_t pending, count;
+ 	drm_flip_func_t func;
+ 	struct work_struct worker;
+-	DECLARE_KFIFO_PTR(fifo, void *);
++	struct list_head queued;
++	struct list_head commited;
++	spinlock_t lock;
+ };
+ 
++struct drm_flip_task *drm_flip_work_allocate_task(void *data, gfp_t flags);
++void drm_flip_work_queue_task(struct drm_flip_work *work,
++			      struct drm_flip_task *task);
+ void drm_flip_work_queue(struct drm_flip_work *work, void *val);
+ void drm_flip_work_commit(struct drm_flip_work *work,
+ 		struct workqueue_struct *wq);
+-int drm_flip_work_init(struct drm_flip_work *work, int size,
++void drm_flip_work_init(struct drm_flip_work *work,
+ 		const char *name, drm_flip_func_t func);
+ void drm_flip_work_cleanup(struct drm_flip_work *work);
+ 
+diff -Naur a/include/drm/drm_gem.h b/include/drm/drm_gem.h
+--- a/include/drm/drm_gem.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_gem.h	2015-03-26 14:42:38.754435422 +0530
+@@ -0,0 +1,190 @@
++#ifndef __DRM_GEM_H__
++#define __DRM_GEM_H__
++
++/*
++ * GEM Graphics Execution Manager Driver Interfaces
++ *
++ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
++ * Copyright (c) 2009-2010, Code Aurora Forum.
++ * All rights reserved.
++ * Copyright © 2014 Intel Corporation
++ *   Daniel Vetter <daniel.vetter@ffwll.ch>
++ *
++ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
++ * Author: Gareth Hughes <gareth@valinux.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/**
++ * This structure defines the drm_mm memory object, which will be used by the
++ * DRM for its buffer objects.
++ */
++struct drm_gem_object {
++	/** Reference count of this object */
++	struct kref refcount;
++
++	/**
++	 * handle_count - gem file_priv handle count of this object
++	 *
++	 * Each handle also holds a reference. Note that when the handle_count
++	 * drops to 0 any global names (e.g. the id in the flink namespace) will
++	 * be cleared.
++	 *
++	 * Protected by dev->object_name_lock.
++	 * */
++	unsigned handle_count;
++
++	/** Related drm device */
++	struct drm_device *dev;
++
++	/** File representing the shmem storage */
++	struct file *filp;
++
++	/* Mapping info for this object */
++	struct drm_vma_offset_node vma_node;
++
++	/**
++	 * Size of the object, in bytes.  Immutable over the object's
++	 * lifetime.
++	 */
++	size_t size;
++
++	/**
++	 * Global name for this object, starts at 1. 0 means unnamed.
++	 * Access is covered by the object_name_lock in the related drm_device
++	 */
++	int name;
++
++	/**
++	 * Memory domains. These monitor which caches contain read/write data
++	 * related to the object. When transitioning from one set of domains
++	 * to another, the driver is called to ensure that caches are suitably
++	 * flushed and invalidated
++	 */
++	uint32_t read_domains;
++	uint32_t write_domain;
++
++	/**
++	 * While validating an exec operation, the
++	 * new read/write domain values are computed here.
++	 * They will be transferred to the above values
++	 * at the point that any cache flushing occurs
++	 */
++	uint32_t pending_read_domains;
++	uint32_t pending_write_domain;
++
++	/**
++	 * dma_buf - dma buf associated with this GEM object
++	 *
++	 * Pointer to the dma-buf associated with this gem object (either
++	 * through importing or exporting). We break the resulting reference
++	 * loop when the last gem handle for this object is released.
++	 *
++	 * Protected by obj->object_name_lock
++	 */
++	struct dma_buf *dma_buf;
++
++	/**
++	 * import_attach - dma buf attachment backing this object
++	 *
++	 * Any foreign dma_buf imported as a gem object has this set to the
++	 * attachment point for the device. This is invariant over the lifetime
++	 * of a gem object.
++	 *
++	 * The driver's ->gem_free_object callback is responsible for cleaning
++	 * up the dma_buf attachment and references acquired at import time.
++	 *
++	 * Note that the drm gem/prime core does not depend upon drivers setting
++	 * this field any more. So for drivers where this doesn't make sense
++	 * (e.g. virtual devices or a displaylink behind an usb bus) they can
++	 * simply leave it as NULL.
++	 */
++	struct dma_buf_attachment *import_attach;
++
++	/**
++	 * dumb - created as dumb buffer
++	 * Whether the gem object was created using the dumb buffer interface
++	 * as such it may not be used for GPU rendering.
++	 */
++	bool dumb;
++};
++
++void drm_gem_object_release(struct drm_gem_object *obj);
++void drm_gem_object_free(struct kref *kref);
++int drm_gem_object_init(struct drm_device *dev,
++			struct drm_gem_object *obj, size_t size);
++void drm_gem_private_object_init(struct drm_device *dev,
++				 struct drm_gem_object *obj, size_t size);
++void drm_gem_vm_open(struct vm_area_struct *vma);
++void drm_gem_vm_close(struct vm_area_struct *vma);
++int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
++		     struct vm_area_struct *vma);
++int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
++
++static inline void
++drm_gem_object_reference(struct drm_gem_object *obj)
++{
++	kref_get(&obj->refcount);
++}
++
++static inline void
++drm_gem_object_unreference(struct drm_gem_object *obj)
++{
++	if (obj != NULL)
++		kref_put(&obj->refcount, drm_gem_object_free);
++}
++
++static inline void
++drm_gem_object_unreference_unlocked(struct drm_gem_object *obj)
++{
++	if (obj && !atomic_add_unless(&obj->refcount.refcount, -1, 1)) {
++		struct drm_device *dev = obj->dev;
++
++		mutex_lock(&dev->struct_mutex);
++		if (likely(atomic_dec_and_test(&obj->refcount.refcount)))
++			drm_gem_object_free(&obj->refcount);
++		mutex_unlock(&dev->struct_mutex);
++	}
++}
++
++int drm_gem_handle_create(struct drm_file *file_priv,
++			  struct drm_gem_object *obj,
++			  u32 *handlep);
++int drm_gem_handle_delete(struct drm_file *filp, u32 handle);
++
++
++void drm_gem_free_mmap_offset(struct drm_gem_object *obj);
++int drm_gem_create_mmap_offset(struct drm_gem_object *obj);
++int drm_gem_create_mmap_offset_size(struct drm_gem_object *obj, size_t size);
++
++struct page **drm_gem_get_pages(struct drm_gem_object *obj);
++void drm_gem_put_pages(struct drm_gem_object *obj, struct page **pages,
++		bool dirty, bool accessed);
++
++struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
++					     struct drm_file *filp,
++					     u32 handle);
++int drm_gem_dumb_destroy(struct drm_file *file,
++			 struct drm_device *dev,
++			 uint32_t handle);
++
++#endif /* __DRM_GEM_H__ */
+diff -Naur a/include/drm/drm_legacy.h b/include/drm/drm_legacy.h
+--- a/include/drm/drm_legacy.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_legacy.h	2015-03-26 14:42:38.754435422 +0530
+@@ -0,0 +1,203 @@
++#ifndef __DRM_DRM_LEGACY_H__
++#define __DRM_DRM_LEGACY_H__
++
++/*
++ * Legacy driver interfaces for the Direct Rendering Manager
++ *
++ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
++ * Copyright (c) 2009-2010, Code Aurora Forum.
++ * All rights reserved.
++ * Copyright © 2014 Intel Corporation
++ *   Daniel Vetter <daniel.vetter@ffwll.ch>
++ *
++ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
++ * Author: Gareth Hughes <gareth@valinux.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++
++/*
++ * Legacy Support for palateontologic DRM drivers
++ *
++ * If you add a new driver and it uses any of these functions or structures,
++ * you're doing it terribly wrong.
++ */
++
++/**
++ * DMA buffer.
++ */
++struct drm_buf {
++	int idx;		       /**< Index into master buflist */
++	int total;		       /**< Buffer size */
++	int order;		       /**< log-base-2(total) */
++	int used;		       /**< Amount of buffer in use (for DMA) */
++	unsigned long offset;	       /**< Byte offset (used internally) */
++	void *address;		       /**< Address of buffer */
++	unsigned long bus_address;     /**< Bus address of buffer */
++	struct drm_buf *next;	       /**< Kernel-only: used for free list */
++	__volatile__ int waiting;      /**< On kernel DMA queue */
++	__volatile__ int pending;      /**< On hardware DMA queue */
++	struct drm_file *file_priv;    /**< Private of holding file descr */
++	int context;		       /**< Kernel queue for this buffer */
++	int while_locked;	       /**< Dispatch this buffer while locked */
++	enum {
++		DRM_LIST_NONE = 0,
++		DRM_LIST_FREE = 1,
++		DRM_LIST_WAIT = 2,
++		DRM_LIST_PEND = 3,
++		DRM_LIST_PRIO = 4,
++		DRM_LIST_RECLAIM = 5
++	} list;			       /**< Which list we're on */
++
++	int dev_priv_size;		 /**< Size of buffer private storage */
++	void *dev_private;		 /**< Per-buffer private storage */
++};
++
++typedef struct drm_dma_handle {
++	dma_addr_t busaddr;
++	void *vaddr;
++	size_t size;
++} drm_dma_handle_t;
++
++/**
++ * Buffer entry.  There is one of this for each buffer size order.
++ */
++struct drm_buf_entry {
++	int buf_size;			/**< size */
++	int buf_count;			/**< number of buffers */
++	struct drm_buf *buflist;		/**< buffer list */
++	int seg_count;
++	int page_order;
++	struct drm_dma_handle **seglist;
++
++	int low_mark;			/**< Low water mark */
++	int high_mark;			/**< High water mark */
++};
++
++/**
++ * DMA data.
++ */
++struct drm_device_dma {
++
++	struct drm_buf_entry bufs[DRM_MAX_ORDER + 1];	/**< buffers, grouped by their size order */
++	int buf_count;			/**< total number of buffers */
++	struct drm_buf **buflist;		/**< Vector of pointers into drm_device_dma::bufs */
++	int seg_count;
++	int page_count;			/**< number of pages */
++	unsigned long *pagelist;	/**< page list */
++	unsigned long byte_count;
++	enum {
++		_DRM_DMA_USE_AGP = 0x01,
++		_DRM_DMA_USE_SG = 0x02,
++		_DRM_DMA_USE_FB = 0x04,
++		_DRM_DMA_USE_PCI_RO = 0x08
++	} flags;
++
++};
++
++/**
++ * Scatter-gather memory.
++ */
++struct drm_sg_mem {
++	unsigned long handle;
++	void *virtual;
++	int pages;
++	struct page **pagelist;
++	dma_addr_t *busaddr;
++};
++
++/**
++ * Kernel side of a mapping
++ */
++struct drm_local_map {
++	resource_size_t offset;	 /**< Requested physical address (0 for SAREA)*/
++	unsigned long size;	 /**< Requested physical size (bytes) */
++	enum drm_map_type type;	 /**< Type of memory to map */
++	enum drm_map_flags flags;	 /**< Flags */
++	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
++				 /**< Kernel-space: kernel-virtual address */
++	int mtrr;		 /**< MTRR slot used */
++};
++
++typedef struct drm_local_map drm_local_map_t;
++
++/**
++ * Mappings list
++ */
++struct drm_map_list {
++	struct list_head head;		/**< list head */
++	struct drm_hash_item hash;
++	struct drm_local_map *map;	/**< mapping */
++	uint64_t user_token;
++	struct drm_master *master;
++};
++
++int drm_legacy_addmap(struct drm_device *d, resource_size_t offset,
++		      unsigned int size, enum drm_map_type type,
++		      enum drm_map_flags flags, struct drm_local_map **map_p);
++int drm_legacy_rmmap(struct drm_device *d, struct drm_local_map *map);
++int drm_legacy_rmmap_locked(struct drm_device *d, struct drm_local_map *map);
++struct drm_local_map *drm_legacy_getsarea(struct drm_device *dev);
++int drm_legacy_mmap(struct file *filp, struct vm_area_struct *vma);
++
++int drm_legacy_addbufs_agp(struct drm_device *d, struct drm_buf_desc *req);
++int drm_legacy_addbufs_pci(struct drm_device *d, struct drm_buf_desc *req);
++
++/**
++ * Test that the hardware lock is held by the caller, returning otherwise.
++ *
++ * \param dev DRM device.
++ * \param filp file pointer of the caller.
++ */
++#define LOCK_TEST_WITH_RETURN( dev, _file_priv )				\
++do {										\
++	if (!_DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock) ||	\
++	    _file_priv->master->lock.file_priv != _file_priv)	{		\
++		DRM_ERROR( "%s called without lock held, held  %d owner %p %p\n",\
++			   __func__, _DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock),\
++			   _file_priv->master->lock.file_priv, _file_priv);	\
++		return -EINVAL;							\
++	}									\
++} while (0)
++
++void drm_legacy_idlelock_take(struct drm_lock_data *lock);
++void drm_legacy_idlelock_release(struct drm_lock_data *lock);
++
++/* drm_pci.c dma alloc wrappers */
++void __drm_legacy_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
++
++/* drm_memory.c */
++void drm_legacy_ioremap(struct drm_local_map *map, struct drm_device *dev);
++void drm_legacy_ioremap_wc(struct drm_local_map *map, struct drm_device *dev);
++void drm_legacy_ioremapfree(struct drm_local_map *map, struct drm_device *dev);
++
++static __inline__ struct drm_local_map *drm_legacy_findmap(struct drm_device *dev,
++							   unsigned int token)
++{
++	struct drm_map_list *_entry;
++	list_for_each_entry(_entry, &dev->maplist, head)
++	    if (_entry->user_token == token)
++		return _entry->map;
++	return NULL;
++}
++
++#endif /* __DRM_DRM_LEGACY_H__ */
+diff -Naur a/include/drm/drm_mm.h b/include/drm/drm_mm.h
+--- a/include/drm/drm_mm.h	2015-03-26 14:43:27.886436386 +0530
++++ b/include/drm/drm_mm.h	2015-03-26 14:42:38.754435422 +0530
+@@ -47,8 +47,17 @@
+ enum drm_mm_search_flags {
+ 	DRM_MM_SEARCH_DEFAULT =		0,
+ 	DRM_MM_SEARCH_BEST =		1 << 0,
++	DRM_MM_SEARCH_BELOW =		1 << 1,
+ };
+ 
++enum drm_mm_allocator_flags {
++	DRM_MM_CREATE_DEFAULT =		0,
++	DRM_MM_CREATE_TOP =		1 << 0,
++};
++
++#define DRM_MM_BOTTOMUP DRM_MM_SEARCH_DEFAULT, DRM_MM_CREATE_DEFAULT
++#define DRM_MM_TOPDOWN DRM_MM_SEARCH_BELOW, DRM_MM_CREATE_TOP
++
+ struct drm_mm_node {
+ 	struct list_head node_list;
+ 	struct list_head hole_stack;
+@@ -85,11 +94,31 @@
+ 			     unsigned long *start, unsigned long *end);
+ };
+ 
++/**
++ * drm_mm_node_allocated - checks whether a node is allocated
++ * @node: drm_mm_node to check
++ *
++ * Drivers should use this helpers for proper encapusulation of drm_mm
++ * internals.
++ *
++ * Returns:
++ * True if the @node is allocated.
++ */
+ static inline bool drm_mm_node_allocated(struct drm_mm_node *node)
+ {
+ 	return node->allocated;
+ }
+ 
++/**
++ * drm_mm_initialized - checks whether an allocator is initialized
++ * @mm: drm_mm to check
++ *
++ * Drivers should use this helpers for proper encapusulation of drm_mm
++ * internals.
++ *
++ * Returns:
++ * True if the @mm is initialized.
++ */
+ static inline bool drm_mm_initialized(struct drm_mm *mm)
+ {
+ 	return mm->hole_stack.next;
+@@ -100,6 +129,17 @@
+ 	return hole_node->start + hole_node->size;
+ }
+ 
++/**
++ * drm_mm_hole_node_start - computes the start of the hole following @node
++ * @hole_node: drm_mm_node which implicitly tracks the following hole
++ *
++ * This is useful for driver-sepific debug dumpers. Otherwise drivers should not
++ * inspect holes themselves. Drivers must check first whether a hole indeed
++ * follows by looking at node->hole_follows.
++ *
++ * Returns:
++ * Start of the subsequent hole.
++ */
+ static inline unsigned long drm_mm_hole_node_start(struct drm_mm_node *hole_node)
+ {
+ 	BUG_ON(!hole_node->hole_follows);
+@@ -112,18 +152,52 @@
+ 			  struct drm_mm_node, node_list)->start;
+ }
+ 
++/**
++ * drm_mm_hole_node_end - computes the end of the hole following @node
++ * @hole_node: drm_mm_node which implicitly tracks the following hole
++ *
++ * This is useful for driver-sepific debug dumpers. Otherwise drivers should not
++ * inspect holes themselves. Drivers must check first whether a hole indeed
++ * follows by looking at node->hole_follows.
++ *
++ * Returns:
++ * End of the subsequent hole.
++ */
+ static inline unsigned long drm_mm_hole_node_end(struct drm_mm_node *hole_node)
+ {
+ 	return __drm_mm_hole_node_end(hole_node);
+ }
+ 
++/**
++ * drm_mm_for_each_node - iterator to walk over all allocated nodes
++ * @entry: drm_mm_node structure to assign to in each iteration step
++ * @mm: drm_mm allocator to walk
++ *
++ * This iterator walks over all nodes in the range allocator. It is implemented
++ * with list_for_each, so not save against removal of elements.
++ */
+ #define drm_mm_for_each_node(entry, mm) list_for_each_entry(entry, \
+ 						&(mm)->head_node.node_list, \
+ 						node_list)
+ 
+-/* Note that we need to unroll list_for_each_entry in order to inline
+- * setting hole_start and hole_end on each iteration and keep the
+- * macro sane.
++/**
++ * drm_mm_for_each_hole - iterator to walk over all holes
++ * @entry: drm_mm_node used internally to track progress
++ * @mm: drm_mm allocator to walk
++ * @hole_start: ulong variable to assign the hole start to on each iteration
++ * @hole_end: ulong variable to assign the hole end to on each iteration
++ *
++ * This iterator walks over all holes in the range allocator. It is implemented
++ * with list_for_each, so not save against removal of elements. @entry is used
++ * internally and will not reflect a real drm_mm_node for the very first hole.
++ * Hence users of this iterator may not access it.
++ *
++ * Implementation Note:
++ * We need to inline list_for_each_entry in order to be able to set hole_start
++ * and hole_end on each iteration while keeping the macro sane.
++ *
++ * The __drm_mm_for_each_hole version is similar, but with added support for
++ * going backwards.
+  */
+ #define drm_mm_for_each_hole(entry, mm, hole_start, hole_end) \
+ 	for (entry = list_entry((mm)->hole_stack.next, struct drm_mm_node, hole_stack); \
+@@ -133,34 +207,79 @@
+ 	     1 : 0; \
+ 	     entry = list_entry(entry->hole_stack.next, struct drm_mm_node, hole_stack))
+ 
++#define __drm_mm_for_each_hole(entry, mm, hole_start, hole_end, backwards) \
++	for (entry = list_entry((backwards) ? (mm)->hole_stack.prev : (mm)->hole_stack.next, struct drm_mm_node, hole_stack); \
++	     &entry->hole_stack != &(mm)->hole_stack ? \
++	     hole_start = drm_mm_hole_node_start(entry), \
++	     hole_end = drm_mm_hole_node_end(entry), \
++	     1 : 0; \
++	     entry = list_entry((backwards) ? entry->hole_stack.prev : entry->hole_stack.next, struct drm_mm_node, hole_stack))
++
+ /*
+  * Basic range manager support (drm_mm.c)
+  */
+-extern int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node);
++int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node);
+ 
+-extern int drm_mm_insert_node_generic(struct drm_mm *mm,
+-				      struct drm_mm_node *node,
+-				      unsigned long size,
+-				      unsigned alignment,
+-				      unsigned long color,
+-				      enum drm_mm_search_flags flags);
++int drm_mm_insert_node_generic(struct drm_mm *mm,
++			       struct drm_mm_node *node,
++			       unsigned long size,
++			       unsigned alignment,
++			       unsigned long color,
++			       enum drm_mm_search_flags sflags,
++			       enum drm_mm_allocator_flags aflags);
++/**
++ * drm_mm_insert_node - search for space and insert @node
++ * @mm: drm_mm to allocate from
++ * @node: preallocate node to insert
++ * @size: size of the allocation
++ * @alignment: alignment of the allocation
++ * @flags: flags to fine-tune the allocation
++ *
++ * This is a simplified version of drm_mm_insert_node_generic() with @color set
++ * to 0.
++ *
++ * The preallocated node must be cleared to 0.
++ *
++ * Returns:
++ * 0 on success, -ENOSPC if there's no suitable hole.
++ */
+ static inline int drm_mm_insert_node(struct drm_mm *mm,
+ 				     struct drm_mm_node *node,
+ 				     unsigned long size,
+ 				     unsigned alignment,
+ 				     enum drm_mm_search_flags flags)
+ {
+-	return drm_mm_insert_node_generic(mm, node, size, alignment, 0, flags);
++	return drm_mm_insert_node_generic(mm, node, size, alignment, 0, flags,
++					  DRM_MM_CREATE_DEFAULT);
+ }
+ 
+-extern int drm_mm_insert_node_in_range_generic(struct drm_mm *mm,
+-				       struct drm_mm_node *node,
+-				       unsigned long size,
+-				       unsigned alignment,
+-				       unsigned long color,
+-				       unsigned long start,
+-				       unsigned long end,
+-				       enum drm_mm_search_flags flags);
++int drm_mm_insert_node_in_range_generic(struct drm_mm *mm,
++					struct drm_mm_node *node,
++					unsigned long size,
++					unsigned alignment,
++					unsigned long color,
++					unsigned long start,
++					unsigned long end,
++					enum drm_mm_search_flags sflags,
++					enum drm_mm_allocator_flags aflags);
++/**
++ * drm_mm_insert_node_in_range - ranged search for space and insert @node
++ * @mm: drm_mm to allocate from
++ * @node: preallocate node to insert
++ * @size: size of the allocation
++ * @alignment: alignment of the allocation
++ * @start: start of the allowed range for this node
++ * @end: end of the allowed range for this node
++ * @flags: flags to fine-tune the allocation
++ *
++ * This is a simplified version of drm_mm_insert_node_in_range_generic() with
++ * @color set to 0.
++ *
++ * The preallocated node must be cleared to 0.
++ *
++ * Returns:
++ * 0 on success, -ENOSPC if there's no suitable hole.
++ */
+ static inline int drm_mm_insert_node_in_range(struct drm_mm *mm,
+ 					      struct drm_mm_node *node,
+ 					      unsigned long size,
+@@ -170,16 +289,17 @@
+ 					      enum drm_mm_search_flags flags)
+ {
+ 	return drm_mm_insert_node_in_range_generic(mm, node, size, alignment,
+-						   0, start, end, flags);
++						   0, start, end, flags,
++						   DRM_MM_CREATE_DEFAULT);
+ }
+ 
+-extern void drm_mm_remove_node(struct drm_mm_node *node);
+-extern void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new);
+-extern void drm_mm_init(struct drm_mm *mm,
+-			unsigned long start,
+-			unsigned long size);
+-extern void drm_mm_takedown(struct drm_mm *mm);
+-extern int drm_mm_clean(struct drm_mm *mm);
++void drm_mm_remove_node(struct drm_mm_node *node);
++void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new);
++void drm_mm_init(struct drm_mm *mm,
++		 unsigned long start,
++		 unsigned long size);
++void drm_mm_takedown(struct drm_mm *mm);
++bool drm_mm_clean(struct drm_mm *mm);
+ 
+ void drm_mm_init_scan(struct drm_mm *mm,
+ 		      unsigned long size,
+@@ -191,10 +311,10 @@
+ 				 unsigned long color,
+ 				 unsigned long start,
+ 				 unsigned long end);
+-int drm_mm_scan_add_block(struct drm_mm_node *node);
+-int drm_mm_scan_remove_block(struct drm_mm_node *node);
++bool drm_mm_scan_add_block(struct drm_mm_node *node);
++bool drm_mm_scan_remove_block(struct drm_mm_node *node);
+ 
+-extern void drm_mm_debug_table(struct drm_mm *mm, const char *prefix);
++void drm_mm_debug_table(struct drm_mm *mm, const char *prefix);
+ #ifdef CONFIG_DEBUG_FS
+ int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm);
+ #endif
+diff -Naur a/include/drm/drm_modeset_lock.h b/include/drm/drm_modeset_lock.h
+--- a/include/drm/drm_modeset_lock.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_modeset_lock.h	2015-03-26 14:42:38.754435422 +0530
+@@ -0,0 +1,145 @@
++/*
++ * Copyright (C) 2014 Red Hat
++ * Author: Rob Clark <robdclark@gmail.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef DRM_MODESET_LOCK_H_
++#define DRM_MODESET_LOCK_H_
++
++#include <linux/ww_mutex.h>
++
++struct drm_modeset_lock;
++
++/**
++ * struct drm_modeset_acquire_ctx - locking context (see ww_acquire_ctx)
++ * @ww_ctx: base acquire ctx
++ * @contended: used internally for -EDEADLK handling
++ * @locked: list of held locks
++ * @trylock_only: trylock mode used in atomic contexts/panic notifiers
++ *
++ * Each thread competing for a set of locks must use one acquire
++ * ctx.  And if any lock fxn returns -EDEADLK, it must backoff and
++ * retry.
++ */
++struct drm_modeset_acquire_ctx {
++
++	struct ww_acquire_ctx ww_ctx;
++
++	/**
++	 * Contended lock: if a lock is contended you should only call
++	 * drm_modeset_backoff() which drops locks and slow-locks the
++	 * contended lock.
++	 */
++	struct drm_modeset_lock *contended;
++
++	/**
++	 * list of held locks (drm_modeset_lock)
++	 */
++	struct list_head locked;
++
++	/**
++	 * Trylock mode, use only for panic handlers!
++	 */
++	bool trylock_only;
++};
++
++/**
++ * struct drm_modeset_lock - used for locking modeset resources.
++ * @mutex: resource locking
++ * @head: used to hold it's place on state->locked list when
++ *    part of an atomic update
++ *
++ * Used for locking CRTCs and other modeset resources.
++ */
++struct drm_modeset_lock {
++	/**
++	 * modeset lock
++	 */
++	struct ww_mutex mutex;
++
++	/**
++	 * Resources that are locked as part of an atomic update are added
++	 * to a list (so we know what to unlock at the end).
++	 */
++	struct list_head head;
++};
++
++extern struct ww_class crtc_ww_class;
++
++void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
++		uint32_t flags);
++void drm_modeset_acquire_fini(struct drm_modeset_acquire_ctx *ctx);
++void drm_modeset_drop_locks(struct drm_modeset_acquire_ctx *ctx);
++void drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx);
++int drm_modeset_backoff_interruptible(struct drm_modeset_acquire_ctx *ctx);
++
++/**
++ * drm_modeset_lock_init - initialize lock
++ * @lock: lock to init
++ */
++static inline void drm_modeset_lock_init(struct drm_modeset_lock *lock)
++{
++	ww_mutex_init(&lock->mutex, &crtc_ww_class);
++	INIT_LIST_HEAD(&lock->head);
++}
++
++/**
++ * drm_modeset_lock_fini - cleanup lock
++ * @lock: lock to cleanup
++ */
++static inline void drm_modeset_lock_fini(struct drm_modeset_lock *lock)
++{
++	WARN_ON(!list_empty(&lock->head));
++}
++
++/**
++ * drm_modeset_is_locked - equivalent to mutex_is_locked()
++ * @lock: lock to check
++ */
++static inline bool drm_modeset_is_locked(struct drm_modeset_lock *lock)
++{
++	return ww_mutex_is_locked(&lock->mutex);
++}
++
++int drm_modeset_lock(struct drm_modeset_lock *lock,
++		struct drm_modeset_acquire_ctx *ctx);
++int drm_modeset_lock_interruptible(struct drm_modeset_lock *lock,
++		struct drm_modeset_acquire_ctx *ctx);
++void drm_modeset_unlock(struct drm_modeset_lock *lock);
++
++struct drm_device;
++struct drm_crtc;
++struct drm_plane;
++
++void drm_modeset_lock_all(struct drm_device *dev);
++int __drm_modeset_lock_all(struct drm_device *dev, bool trylock);
++void drm_modeset_unlock_all(struct drm_device *dev);
++void drm_modeset_lock_crtc(struct drm_crtc *crtc,
++			   struct drm_plane *plane);
++void drm_modeset_unlock_crtc(struct drm_crtc *crtc);
++void drm_warn_on_modeset_not_all_locked(struct drm_device *dev);
++struct drm_modeset_acquire_ctx *
++drm_modeset_legacy_acquire_ctx(struct drm_crtc *crtc);
++
++int drm_modeset_lock_all_crtcs(struct drm_device *dev,
++		struct drm_modeset_acquire_ctx *ctx);
++
++#endif /* DRM_MODESET_LOCK_H_ */
+diff -Naur a/include/drm/drm_modes.h b/include/drm/drm_modes.h
+--- a/include/drm/drm_modes.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_modes.h	2015-03-26 14:42:38.754435422 +0530
+@@ -0,0 +1,237 @@
++/*
++ * Copyright © 2006 Keith Packard
++ * Copyright © 2007-2008 Dave Airlie
++ * Copyright © 2007-2008 Intel Corporation
++ *   Jesse Barnes <jesse.barnes@intel.com>
++ * Copyright © 2014 Intel Corporation
++ *   Daniel Vetter <daniel.vetter@ffwll.ch>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef __DRM_MODES_H__
++#define __DRM_MODES_H__
++
++/*
++ * Note on terminology:  here, for brevity and convenience, we refer to connector
++ * control chips as 'CRTCs'.  They can control any type of connector, VGA, LVDS,
++ * DVI, etc.  And 'screen' refers to the whole of the visible display, which
++ * may span multiple monitors (and therefore multiple CRTC and connector
++ * structures).
++ */
++
++enum drm_mode_status {
++    MODE_OK	= 0,	/* Mode OK */
++    MODE_HSYNC,		/* hsync out of range */
++    MODE_VSYNC,		/* vsync out of range */
++    MODE_H_ILLEGAL,	/* mode has illegal horizontal timings */
++    MODE_V_ILLEGAL,	/* mode has illegal horizontal timings */
++    MODE_BAD_WIDTH,	/* requires an unsupported linepitch */
++    MODE_NOMODE,	/* no mode with a matching name */
++    MODE_NO_INTERLACE,	/* interlaced mode not supported */
++    MODE_NO_DBLESCAN,	/* doublescan mode not supported */
++    MODE_NO_VSCAN,	/* multiscan mode not supported */
++    MODE_MEM,		/* insufficient video memory */
++    MODE_VIRTUAL_X,	/* mode width too large for specified virtual size */
++    MODE_VIRTUAL_Y,	/* mode height too large for specified virtual size */
++    MODE_MEM_VIRT,	/* insufficient video memory given virtual size */
++    MODE_NOCLOCK,	/* no fixed clock available */
++    MODE_CLOCK_HIGH,	/* clock required is too high */
++    MODE_CLOCK_LOW,	/* clock required is too low */
++    MODE_CLOCK_RANGE,	/* clock/mode isn't in a ClockRange */
++    MODE_BAD_HVALUE,	/* horizontal timing was out of range */
++    MODE_BAD_VVALUE,	/* vertical timing was out of range */
++    MODE_BAD_VSCAN,	/* VScan value out of range */
++    MODE_HSYNC_NARROW,	/* horizontal sync too narrow */
++    MODE_HSYNC_WIDE,	/* horizontal sync too wide */
++    MODE_HBLANK_NARROW,	/* horizontal blanking too narrow */
++    MODE_HBLANK_WIDE,	/* horizontal blanking too wide */
++    MODE_VSYNC_NARROW,	/* vertical sync too narrow */
++    MODE_VSYNC_WIDE,	/* vertical sync too wide */
++    MODE_VBLANK_NARROW,	/* vertical blanking too narrow */
++    MODE_VBLANK_WIDE,	/* vertical blanking too wide */
++    MODE_PANEL,         /* exceeds panel dimensions */
++    MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */
++    MODE_ONE_WIDTH,     /* only one width is supported */
++    MODE_ONE_HEIGHT,    /* only one height is supported */
++    MODE_ONE_SIZE,      /* only one resolution is supported */
++    MODE_NO_REDUCED,    /* monitor doesn't accept reduced blanking */
++    MODE_NO_STEREO,	/* stereo modes not supported */
++    MODE_UNVERIFIED = -3, /* mode needs to reverified */
++    MODE_BAD = -2,	/* unspecified reason */
++    MODE_ERROR	= -1	/* error condition */
++};
++
++#define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
++				    DRM_MODE_TYPE_CRTC_C)
++
++#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
++	.name = nm, .status = 0, .type = (t), .clock = (c), \
++	.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
++	.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
++	.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
++	.vscan = (vs), .flags = (f), \
++	.base.type = DRM_MODE_OBJECT_MODE
++
++#define CRTC_INTERLACE_HALVE_V	(1 << 0) /* halve V values for interlacing */
++#define CRTC_STEREO_DOUBLE	(1 << 1) /* adjust timings for stereo modes */
++
++#define DRM_MODE_FLAG_3D_MAX	DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
++
++struct drm_display_mode {
++	/* Header */
++	struct list_head head;
++	struct drm_mode_object base;
++
++	char name[DRM_DISPLAY_MODE_LEN];
++
++	enum drm_mode_status status;
++	unsigned int type;
++
++	/* Proposed mode values */
++	int clock;		/* in kHz */
++	int hdisplay;
++	int hsync_start;
++	int hsync_end;
++	int htotal;
++	int hskew;
++	int vdisplay;
++	int vsync_start;
++	int vsync_end;
++	int vtotal;
++	int vscan;
++	unsigned int flags;
++
++	/* Addressable image size (may be 0 for projectors, etc.) */
++	int width_mm;
++	int height_mm;
++
++	/* Actual mode we give to hw */
++	int crtc_clock;		/* in KHz */
++	int crtc_hdisplay;
++	int crtc_hblank_start;
++	int crtc_hblank_end;
++	int crtc_hsync_start;
++	int crtc_hsync_end;
++	int crtc_htotal;
++	int crtc_hskew;
++	int crtc_vdisplay;
++	int crtc_vblank_start;
++	int crtc_vblank_end;
++	int crtc_vsync_start;
++	int crtc_vsync_end;
++	int crtc_vtotal;
++
++	/* Driver private mode info */
++	int *private;
++	int private_flags;
++
++	int vrefresh;		/* in Hz */
++	int hsync;		/* in kHz */
++	enum hdmi_picture_aspect picture_aspect_ratio;
++};
++
++/* mode specified on the command line */
++struct drm_cmdline_mode {
++	bool specified;
++	bool refresh_specified;
++	bool bpp_specified;
++	int xres, yres;
++	int bpp;
++	int refresh;
++	bool rb;
++	bool interlace;
++	bool cvt;
++	bool margins;
++	enum drm_connector_force force;
++};
++
++/**
++ * drm_mode_is_stereo - check for stereo mode flags
++ * @mode: drm_display_mode to check
++ *
++ * Returns:
++ * True if the mode is one of the stereo modes (like side-by-side), false if
++ * not.
++ */
++static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
++{
++	return mode->flags & DRM_MODE_FLAG_3D_MASK;
++}
++
++struct drm_connector;
++struct drm_cmdline_mode;
++
++struct drm_display_mode *drm_mode_create(struct drm_device *dev);
++void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode);
++void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
++void drm_mode_debug_printmodeline(const struct drm_display_mode *mode);
++
++struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
++				      int hdisplay, int vdisplay, int vrefresh,
++				      bool reduced, bool interlaced,
++				      bool margins);
++struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
++				      int hdisplay, int vdisplay, int vrefresh,
++				      bool interlaced, int margins);
++struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev,
++					      int hdisplay, int vdisplay,
++					      int vrefresh, bool interlaced,
++					      int margins,
++					      int GTF_M, int GTF_2C,
++					      int GTF_K, int GTF_2J);
++void drm_display_mode_from_videomode(const struct videomode *vm,
++				     struct drm_display_mode *dmode);
++int of_get_drm_display_mode(struct device_node *np,
++			    struct drm_display_mode *dmode,
++			    int index);
++
++void drm_mode_set_name(struct drm_display_mode *mode);
++int drm_mode_hsync(const struct drm_display_mode *mode);
++int drm_mode_vrefresh(const struct drm_display_mode *mode);
++
++void drm_mode_set_crtcinfo(struct drm_display_mode *p,
++			   int adjust_flags);
++void drm_mode_copy(struct drm_display_mode *dst,
++		   const struct drm_display_mode *src);
++struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
++					    const struct drm_display_mode *mode);
++bool drm_mode_equal(const struct drm_display_mode *mode1,
++		    const struct drm_display_mode *mode2);
++bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
++					const struct drm_display_mode *mode2);
++
++/* for use by the crtc helper probe functions */
++void drm_mode_validate_size(struct drm_device *dev,
++			    struct list_head *mode_list,
++			    int maxX, int maxY);
++void drm_mode_prune_invalid(struct drm_device *dev,
++			    struct list_head *mode_list, bool verbose);
++void drm_mode_sort(struct list_head *mode_list);
++void drm_mode_connector_list_update(struct drm_connector *connector, bool merge_type_bits);
++
++/* parsing cmdline modes */
++bool
++drm_mode_parse_command_line_for_connector(const char *mode_option,
++					  struct drm_connector *connector,
++					  struct drm_cmdline_mode *mode);
++struct drm_display_mode *
++drm_mode_create_from_cmdline_mode(struct drm_device *dev,
++				  struct drm_cmdline_mode *cmd);
++
++#endif /* __DRM_MODES_H__ */
+diff -Naur a/include/drm/drmP.h b/include/drm/drmP.h
+--- a/include/drm/drmP.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/drmP.h	2015-03-26 14:42:38.758435422 +0530
+@@ -1,17 +1,14 @@
+-/**
+- * \file drmP.h
+- * Private header for Direct Rendering Manager
+- *
+- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+- * \author Gareth Hughes <gareth@valinux.com>
+- */
+-
+ /*
++ * Internal Header for the Direct Rendering Manager
++ *
+  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
+  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
+  * Copyright (c) 2009-2010, Code Aurora Forum.
+  * All rights reserved.
+  *
++ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
++ * Author: Gareth Hughes <gareth@valinux.com>
++ *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+  * to deal in the Software without restriction, including without limitation
+@@ -35,101 +32,101 @@
+ #ifndef _DRM_P_H_
+ #define _DRM_P_H_
+ 
+-#ifdef __KERNEL__
+-#ifdef __alpha__
+-/* add include of current.h so that "current" is defined
+- * before static inline funcs in wait.h. Doing this so we
+- * can build the DRM (part of PI DRI). 4/21/2000 S + B */
+-#include <asm/current.h>
+-#endif				/* __alpha__ */
+-#include <linux/kernel.h>
+-#include <linux/miscdevice.h>
++#include <linux/agp_backend.h>
++#include <linux/cdev.h>
++#include <linux/dma-mapping.h>
++#include <linux/file.h>
+ #include <linux/fs.h>
++#include <linux/highmem.h>
++#include <linux/idr.h>
+ #include <linux/init.h>
+-#include <linux/file.h>
+-#include <linux/platform_device.h>
+-#include <linux/pci.h>
++#include <linux/io.h>
+ #include <linux/jiffies.h>
+-#include <linux/dma-mapping.h>
++#include <linux/kernel.h>
++#include <linux/kref.h>
++#include <linux/miscdevice.h>
+ #include <linux/mm.h>
+-#include <linux/cdev.h>
+ #include <linux/mutex.h>
+-#include <linux/io.h>
+-#include <linux/slab.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
+ #include <linux/ratelimit.h>
+-#if defined(__alpha__) || defined(__powerpc__)
+-#include <asm/pgtable.h>	/* For pte_wrprotect */
+-#endif
+-#include <asm/mman.h>
+-#include <asm/uaccess.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
+ #include <linux/types.h>
+-#include <linux/agp_backend.h>
++#include <linux/vmalloc.h>
+ #include <linux/workqueue.h>
+-#include <linux/poll.h>
++
++#include <asm/mman.h>
+ #include <asm/pgalloc.h>
+-#include <drm/drm.h>
+-#include <drm/drm_sarea.h>
+-#include <drm/drm_vma_manager.h>
++#include <asm/uaccess.h>
+ 
+-#include <linux/idr.h>
++#include <uapi/drm/drm.h>
++#include <uapi/drm/drm_mode.h>
+ 
+-#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
++#include <drm/drm_agpsupport.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_global.h>
++#include <drm/drm_hashtab.h>
++#include <drm/drm_mem_util.h>
++#include <drm/drm_mm.h>
++#include <drm/drm_os_linux.h>
++#include <drm/drm_sarea.h>
++#include <drm/drm_vma_manager.h>
+ 
+ struct module;
+ 
+ struct drm_file;
+ struct drm_device;
++struct drm_agp_head;
++struct drm_local_map;
++struct drm_device_dma;
++struct drm_dma_handle;
++struct drm_gem_object;
+ 
+ struct device_node;
+ struct videomode;
++struct reservation_object;
++struct dma_buf_attachment;
+ 
+-#include <drm/drm_os_linux.h>
+-#include <drm/drm_hashtab.h>
+-#include <drm/drm_mm.h>
+-
+-#define DRM_UT_CORE 		0x01
+-#define DRM_UT_DRIVER		0x02
+-#define DRM_UT_KMS		0x04
+-#define DRM_UT_PRIME		0x08
+ /*
+- * Three debug levels are defined.
+- * drm_core, drm_driver, drm_kms
+- * drm_core level can be used in the generic drm code. For example:
+- * 	drm_ioctl, drm_mm, drm_memory
+- * The macro definition of DRM_DEBUG is used.
+- * 	DRM_DEBUG(fmt, args...)
+- * 	The debug info by using the DRM_DEBUG can be obtained by adding
+- * 	the boot option of "drm.debug=1".
++ * 4 debug categories are defined:
++ *
++ * CORE: Used in the generic drm code: drm_ioctl.c, drm_mm.c, drm_memory.c, ...
++ *	 This is the category used by the DRM_DEBUG() macro.
+  *
+- * drm_driver level can be used in the specific drm driver. It is used
+- * to add the debug info related with the drm driver. For example:
+- * i915_drv, i915_dma, i915_gem, radeon_drv,
+- * 	The macro definition of DRM_DEBUG_DRIVER can be used.
+- * 	DRM_DEBUG_DRIVER(fmt, args...)
+- * 	The debug info by using the DRM_DEBUG_DRIVER can be obtained by
+- * 	adding the boot option of "drm.debug=0x02"
++ * DRIVER: Used in the vendor specific part of the driver: i915, radeon, ...
++ *	   This is the category used by the DRM_DEBUG_DRIVER() macro.
+  *
+- * drm_kms level can be used in the KMS code related with specific drm driver.
+- * It is used to add the debug info related with KMS mode. For example:
+- * the connector/crtc ,
+- * 	The macro definition of DRM_DEBUG_KMS can be used.
+- * 	DRM_DEBUG_KMS(fmt, args...)
+- * 	The debug info by using the DRM_DEBUG_KMS can be obtained by
+- * 	adding the boot option of "drm.debug=0x04"
++ * KMS: used in the modesetting code.
++ *	This is the category used by the DRM_DEBUG_KMS() macro.
+  *
+- * If we add the boot option of "drm.debug=0x06", we can get the debug info by
+- * using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER.
+- * If we add the boot option of "drm.debug=0x05", we can get the debug info by
+- * using the DRM_DEBUG_KMS and DRM_DEBUG.
++ * PRIME: used in the prime code.
++ *	  This is the category used by the DRM_DEBUG_PRIME() macro.
++ *
++ * Enabling verbose debug messages is done through the drm.debug parameter,
++ * each category being enabled by a bit.
++ *
++ * drm.debug=0x1 will enable CORE messages
++ * drm.debug=0x2 will enable DRIVER messages
++ * drm.debug=0x3 will enable CORE and DRIVER messages
++ * ...
++ * drm.debug=0xf will enable all messages
++ *
++ * An interesting feature is that it's possible to enable verbose logging at
++ * run-time by echoing the debug value in its sysfs node:
++ *   # echo 0xf > /sys/module/drm/parameters/debug
+  */
++#define DRM_UT_CORE 		0x01
++#define DRM_UT_DRIVER		0x02
++#define DRM_UT_KMS		0x04
++#define DRM_UT_PRIME		0x08
+ 
+-extern __printf(4, 5)
+-void drm_ut_debug_printk(unsigned int request_level,
+-			 const char *prefix,
+-			 const char *function_name,
+-			 const char *format, ...);
+ extern __printf(2, 3)
+-int drm_err(const char *func, const char *format, ...);
++void drm_ut_debug_printk(const char *function_name,
++			 const char *format, ...);
++extern __printf(1, 2)
++void drm_err(const char *format, ...);
+ 
+ /***********************************************************************/
+ /** \name DRM template customization defaults */
+@@ -147,26 +144,6 @@
+ #define DRIVER_PRIME       0x4000
+ #define DRIVER_RENDER      0x8000
+ 
+-#define DRIVER_BUS_PCI 0x1
+-#define DRIVER_BUS_PLATFORM 0x2
+-#define DRIVER_BUS_USB 0x3
+-#define DRIVER_BUS_HOST1X 0x4
+-
+-/***********************************************************************/
+-/** \name Begin the DRM... */
+-/*@{*/
+-
+-#define DRM_DEBUG_CODE 2	  /**< Include debugging code if > 1, then
+-				     also include looping detection. */
+-
+-#define DRM_MAGIC_HASH_ORDER  4  /**< Size of key hash table. Must be power of 2. */
+-#define DRM_KERNEL_CONTEXT    0	 /**< Change drm_resctx if changed */
+-#define DRM_RESERVED_CONTEXTS 1	 /**< Change drm_resctx if changed */
+-
+-#define DRM_MAP_HASH_OFFSET 0x10000000
+-
+-/*@}*/
+-
+ /***********************************************************************/
+ /** \name Macros to make printk easier */
+ /*@{*/
+@@ -178,7 +155,7 @@
+  * \param arg arguments
+  */
+ #define DRM_ERROR(fmt, ...)				\
+-	drm_err(__func__, fmt, ##__VA_ARGS__)
++	drm_err(fmt, ##__VA_ARGS__)
+ 
+ /**
+  * Rate limited error output.  Like DRM_ERROR() but won't flood the log.
+@@ -193,7 +170,7 @@
+ 				      DEFAULT_RATELIMIT_BURST);		\
+ 									\
+ 	if (__ratelimit(&_rs))						\
+-		drm_err(__func__, fmt, ##__VA_ARGS__);			\
++		drm_err(fmt, ##__VA_ARGS__);				\
+ })
+ 
+ #define DRM_INFO(fmt, ...)				\
+@@ -208,59 +185,27 @@
+  * \param fmt printf() like format string.
+  * \param arg arguments
+  */
+-#if DRM_DEBUG_CODE
+ #define DRM_DEBUG(fmt, args...)						\
+ 	do {								\
+-		drm_ut_debug_printk(DRM_UT_CORE, DRM_NAME, 		\
+-					__func__, fmt, ##args);		\
++		if (unlikely(drm_debug & DRM_UT_CORE))			\
++			drm_ut_debug_printk(__func__, fmt, ##args);	\
+ 	} while (0)
+ 
+ #define DRM_DEBUG_DRIVER(fmt, args...)					\
+ 	do {								\
+-		drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME,		\
+-					__func__, fmt, ##args);		\
++		if (unlikely(drm_debug & DRM_UT_DRIVER))		\
++			drm_ut_debug_printk(__func__, fmt, ##args);	\
+ 	} while (0)
+-#define DRM_DEBUG_KMS(fmt, args...)				\
++#define DRM_DEBUG_KMS(fmt, args...)					\
+ 	do {								\
+-		drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, 		\
+-					 __func__, fmt, ##args);	\
++		if (unlikely(drm_debug & DRM_UT_KMS))			\
++			drm_ut_debug_printk(__func__, fmt, ##args);	\
+ 	} while (0)
+ #define DRM_DEBUG_PRIME(fmt, args...)					\
+ 	do {								\
+-		drm_ut_debug_printk(DRM_UT_PRIME, DRM_NAME,		\
+-					__func__, fmt, ##args);		\
++		if (unlikely(drm_debug & DRM_UT_PRIME))			\
++			drm_ut_debug_printk(__func__, fmt, ##args);	\
+ 	} while (0)
+-#define DRM_LOG(fmt, args...)						\
+-	do {								\
+-		drm_ut_debug_printk(DRM_UT_CORE, NULL,			\
+-					NULL, fmt, ##args);		\
+-	} while (0)
+-#define DRM_LOG_KMS(fmt, args...)					\
+-	do {								\
+-		drm_ut_debug_printk(DRM_UT_KMS, NULL,			\
+-					NULL, fmt, ##args);		\
+-	} while (0)
+-#define DRM_LOG_MODE(fmt, args...)					\
+-	do {								\
+-		drm_ut_debug_printk(DRM_UT_MODE, NULL,			\
+-					NULL, fmt, ##args);		\
+-	} while (0)
+-#define DRM_LOG_DRIVER(fmt, args...)					\
+-	do {								\
+-		drm_ut_debug_printk(DRM_UT_DRIVER, NULL,		\
+-					NULL, fmt, ##args);		\
+-	} while (0)
+-#else
+-#define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0)
+-#define DRM_DEBUG_KMS(fmt, args...)	do { } while (0)
+-#define DRM_DEBUG_PRIME(fmt, args...)	do { } while (0)
+-#define DRM_DEBUG(fmt, arg...)		 do { } while (0)
+-#define DRM_LOG(fmt, arg...)		do { } while (0)
+-#define DRM_LOG_KMS(fmt, args...) do { } while (0)
+-#define DRM_LOG_MODE(fmt, arg...) do { } while (0)
+-#define DRM_LOG_DRIVER(fmt, arg...) do { } while (0)
+-
+-#endif
+ 
+ /*@}*/
+ 
+@@ -268,28 +213,9 @@
+ /** \name Internal types and structures */
+ /*@{*/
+ 
+-#define DRM_ARRAY_SIZE(x) ARRAY_SIZE(x)
+-
+ #define DRM_IF_VERSION(maj, min) (maj << 16 | min)
+ 
+ /**
+- * Test that the hardware lock is held by the caller, returning otherwise.
+- *
+- * \param dev DRM device.
+- * \param filp file pointer of the caller.
+- */
+-#define LOCK_TEST_WITH_RETURN( dev, _file_priv )				\
+-do {										\
+-	if (!_DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock) ||	\
+-	    _file_priv->master->lock.file_priv != _file_priv)	{		\
+-		DRM_ERROR( "%s called without lock held, held  %d owner %p %p\n",\
+-			   __func__, _DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock),\
+-			   _file_priv->master->lock.file_priv, _file_priv);	\
+-		return -EINVAL;							\
+-	}									\
+-} while (0)
+-
+-/**
+  * Ioctl function type.
+  *
+  * \param inode device inode.
+@@ -329,91 +255,6 @@
+ #define DRM_IOCTL_DEF_DRV(ioctl, _func, _flags)			\
+ 	[DRM_IOCTL_NR(DRM_##ioctl)] = {.cmd = DRM_##ioctl, .func = _func, .flags = _flags, .cmd_drv = DRM_IOCTL_##ioctl, .name = #ioctl}
+ 
+-struct drm_magic_entry {
+-	struct list_head head;
+-	struct drm_hash_item hash_item;
+-	struct drm_file *priv;
+-};
+-
+-struct drm_vma_entry {
+-	struct list_head head;
+-	struct vm_area_struct *vma;
+-	pid_t pid;
+-};
+-
+-/**
+- * DMA buffer.
+- */
+-struct drm_buf {
+-	int idx;		       /**< Index into master buflist */
+-	int total;		       /**< Buffer size */
+-	int order;		       /**< log-base-2(total) */
+-	int used;		       /**< Amount of buffer in use (for DMA) */
+-	unsigned long offset;	       /**< Byte offset (used internally) */
+-	void *address;		       /**< Address of buffer */
+-	unsigned long bus_address;     /**< Bus address of buffer */
+-	struct drm_buf *next;	       /**< Kernel-only: used for free list */
+-	__volatile__ int waiting;      /**< On kernel DMA queue */
+-	__volatile__ int pending;      /**< On hardware DMA queue */
+-	struct drm_file *file_priv;    /**< Private of holding file descr */
+-	int context;		       /**< Kernel queue for this buffer */
+-	int while_locked;	       /**< Dispatch this buffer while locked */
+-	enum {
+-		DRM_LIST_NONE = 0,
+-		DRM_LIST_FREE = 1,
+-		DRM_LIST_WAIT = 2,
+-		DRM_LIST_PEND = 3,
+-		DRM_LIST_PRIO = 4,
+-		DRM_LIST_RECLAIM = 5
+-	} list;			       /**< Which list we're on */
+-
+-	int dev_priv_size;		 /**< Size of buffer private storage */
+-	void *dev_private;		 /**< Per-buffer private storage */
+-};
+-
+-/** bufs is one longer than it has to be */
+-struct drm_waitlist {
+-	int count;			/**< Number of possible buffers */
+-	struct drm_buf **bufs;		/**< List of pointers to buffers */
+-	struct drm_buf **rp;			/**< Read pointer */
+-	struct drm_buf **wp;			/**< Write pointer */
+-	struct drm_buf **end;		/**< End pointer */
+-	spinlock_t read_lock;
+-	spinlock_t write_lock;
+-};
+-
+-struct drm_freelist {
+-	int initialized;	       /**< Freelist in use */
+-	atomic_t count;		       /**< Number of free buffers */
+-	struct drm_buf *next;	       /**< End pointer */
+-
+-	wait_queue_head_t waiting;     /**< Processes waiting on free bufs */
+-	int low_mark;		       /**< Low water mark */
+-	int high_mark;		       /**< High water mark */
+-	atomic_t wfh;		       /**< If waiting for high mark */
+-	spinlock_t lock;
+-};
+-
+-typedef struct drm_dma_handle {
+-	dma_addr_t busaddr;
+-	void *vaddr;
+-	size_t size;
+-} drm_dma_handle_t;
+-
+-/**
+- * Buffer entry.  There is one of this for each buffer size order.
+- */
+-struct drm_buf_entry {
+-	int buf_size;			/**< size */
+-	int buf_count;			/**< number of buffers */
+-	struct drm_buf *buflist;		/**< buffer list */
+-	int seg_count;
+-	int page_order;
+-	struct drm_dma_handle **seglist;
+-
+-	struct drm_freelist freelist;
+-};
+-
+ /* Event queued up for userspace to read */
+ struct drm_pending_event {
+ 	struct drm_event *event;
+@@ -432,11 +273,16 @@
+ 
+ /** File private data */
+ struct drm_file {
+-	unsigned always_authenticated :1;
+ 	unsigned authenticated :1;
+-	unsigned is_master :1; /* this file private is a master for a minor */
++	/* Whether we're master for a minor. Protected by master_mutex */
++	unsigned is_master :1;
+ 	/* true when the client has asked us to expose stereo 3D mode flags */
+ 	unsigned stereo_allowed :1;
++	/*
++	 * true if client understands CRTC primary planes and cursor planes
++	 * in the plane list
++	 */
++	unsigned universal_planes:1;
+ 
+ 	struct pid *pid;
+ 	kuid_t uid;
+@@ -471,23 +317,6 @@
+ 	struct drm_prime_file_private prime;
+ };
+ 
+-/** Wait queue */
+-struct drm_queue {
+-	atomic_t use_count;		/**< Outstanding uses (+1) */
+-	atomic_t finalization;		/**< Finalization in progress */
+-	atomic_t block_count;		/**< Count of processes waiting */
+-	atomic_t block_read;		/**< Queue blocked for reads */
+-	wait_queue_head_t read_queue;	/**< Processes waiting on block_read */
+-	atomic_t block_write;		/**< Queue blocked for writes */
+-	wait_queue_head_t write_queue;	/**< Processes waiting on block_write */
+-	atomic_t total_queued;		/**< Total queued statistic */
+-	atomic_t total_flushed;		/**< Total flushes statistic */
+-	atomic_t total_locks;		/**< Total locks statistics */
+-	enum drm_ctx_flags flags;	/**< Context preserving and 2D-only */
+-	struct drm_waitlist waitlist;	/**< Pending buffers */
+-	wait_queue_head_t flush_queue;	/**< Processes waiting until flush */
+-};
+-
+ /**
+  * Lock data.
+  */
+@@ -504,238 +333,26 @@
+ };
+ 
+ /**
+- * DMA data.
+- */
+-struct drm_device_dma {
+-
+-	struct drm_buf_entry bufs[DRM_MAX_ORDER + 1];	/**< buffers, grouped by their size order */
+-	int buf_count;			/**< total number of buffers */
+-	struct drm_buf **buflist;		/**< Vector of pointers into drm_device_dma::bufs */
+-	int seg_count;
+-	int page_count;			/**< number of pages */
+-	unsigned long *pagelist;	/**< page list */
+-	unsigned long byte_count;
+-	enum {
+-		_DRM_DMA_USE_AGP = 0x01,
+-		_DRM_DMA_USE_SG = 0x02,
+-		_DRM_DMA_USE_FB = 0x04,
+-		_DRM_DMA_USE_PCI_RO = 0x08
+-	} flags;
+-
+-};
+-
+-/**
+- * AGP memory entry.  Stored as a doubly linked list.
+- */
+-struct drm_agp_mem {
+-	unsigned long handle;		/**< handle */
+-	struct agp_memory *memory;
+-	unsigned long bound;		/**< address */
+-	int pages;
+-	struct list_head head;
+-};
+-
+-/**
+- * AGP data.
++ * struct drm_master - drm master structure
+  *
+- * \sa drm_agp_init() and drm_device::agp.
++ * @refcount: Refcount for this master object.
++ * @minor: Link back to minor char device we are master for. Immutable.
++ * @unique: Unique identifier: e.g. busid. Protected by drm_global_mutex.
++ * @unique_len: Length of unique field. Protected by drm_global_mutex.
++ * @magiclist: Hash of used authentication tokens. Protected by struct_mutex.
++ * @magicfree: List of used authentication tokens. Protected by struct_mutex.
++ * @lock: DRI lock information.
++ * @driver_priv: Pointer to driver-private information.
+  */
+-struct drm_agp_head {
+-	struct agp_kern_info agp_info;		/**< AGP device information */
+-	struct list_head memory;
+-	unsigned long mode;		/**< AGP mode */
+-	struct agp_bridge_data *bridge;
+-	int enabled;			/**< whether the AGP bus as been enabled */
+-	int acquired;			/**< whether the AGP device has been acquired */
+-	unsigned long base;
+-	int agp_mtrr;
+-	int cant_use_aperture;
+-	unsigned long page_mask;
+-};
+-
+-/**
+- * Scatter-gather memory.
+- */
+-struct drm_sg_mem {
+-	unsigned long handle;
+-	void *virtual;
+-	int pages;
+-	struct page **pagelist;
+-	dma_addr_t *busaddr;
+-};
+-
+-struct drm_sigdata {
+-	int context;
+-	struct drm_hw_lock *lock;
+-};
+-
+-
+-/**
+- * Kernel side of a mapping
+- */
+-struct drm_local_map {
+-	resource_size_t offset;	 /**< Requested physical address (0 for SAREA)*/
+-	unsigned long size;	 /**< Requested physical size (bytes) */
+-	enum drm_map_type type;	 /**< Type of memory to map */
+-	enum drm_map_flags flags;	 /**< Flags */
+-	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
+-				 /**< Kernel-space: kernel-virtual address */
+-	int mtrr;		 /**< MTRR slot used */
+-};
+-
+-typedef struct drm_local_map drm_local_map_t;
+-
+-/**
+- * Mappings list
+- */
+-struct drm_map_list {
+-	struct list_head head;		/**< list head */
+-	struct drm_hash_item hash;
+-	struct drm_local_map *map;	/**< mapping */
+-	uint64_t user_token;
+-	struct drm_master *master;
+-};
+-
+-/**
+- * Context handle list
+- */
+-struct drm_ctx_list {
+-	struct list_head head;		/**< list head */
+-	drm_context_t handle;		/**< context handle */
+-	struct drm_file *tag;		/**< associated fd private data */
+-};
+-
+-/* location of GART table */
+-#define DRM_ATI_GART_MAIN 1
+-#define DRM_ATI_GART_FB   2
+-
+-#define DRM_ATI_GART_PCI 1
+-#define DRM_ATI_GART_PCIE 2
+-#define DRM_ATI_GART_IGP 3
+-
+-struct drm_ati_pcigart_info {
+-	int gart_table_location;
+-	int gart_reg_if;
+-	void *addr;
+-	dma_addr_t bus_addr;
+-	dma_addr_t table_mask;
+-	struct drm_dma_handle *table_handle;
+-	struct drm_local_map mapping;
+-	int table_size;
+-};
+-
+-/**
+- * This structure defines the drm_mm memory object, which will be used by the
+- * DRM for its buffer objects.
+- */
+-struct drm_gem_object {
+-	/** Reference count of this object */
+-	struct kref refcount;
+-
+-	/**
+-	 * handle_count - gem file_priv handle count of this object
+-	 *
+-	 * Each handle also holds a reference. Note that when the handle_count
+-	 * drops to 0 any global names (e.g. the id in the flink namespace) will
+-	 * be cleared.
+-	 *
+-	 * Protected by dev->object_name_lock.
+-	 * */
+-	unsigned handle_count;
+-
+-	/** Related drm device */
+-	struct drm_device *dev;
+-
+-	/** File representing the shmem storage */
+-	struct file *filp;
+-
+-	/* Mapping info for this object */
+-	struct drm_vma_offset_node vma_node;
+-
+-	/**
+-	 * Size of the object, in bytes.  Immutable over the object's
+-	 * lifetime.
+-	 */
+-	size_t size;
+-
+-	/**
+-	 * Global name for this object, starts at 1. 0 means unnamed.
+-	 * Access is covered by the object_name_lock in the related drm_device
+-	 */
+-	int name;
+-
+-	/**
+-	 * Memory domains. These monitor which caches contain read/write data
+-	 * related to the object. When transitioning from one set of domains
+-	 * to another, the driver is called to ensure that caches are suitably
+-	 * flushed and invalidated
+-	 */
+-	uint32_t read_domains;
+-	uint32_t write_domain;
+-
+-	/**
+-	 * While validating an exec operation, the
+-	 * new read/write domain values are computed here.
+-	 * They will be transferred to the above values
+-	 * at the point that any cache flushing occurs
+-	 */
+-	uint32_t pending_read_domains;
+-	uint32_t pending_write_domain;
+-
+-	/**
+-	 * dma_buf - dma buf associated with this GEM object
+-	 *
+-	 * Pointer to the dma-buf associated with this gem object (either
+-	 * through importing or exporting). We break the resulting reference
+-	 * loop when the last gem handle for this object is released.
+-	 *
+-	 * Protected by obj->object_name_lock
+-	 */
+-	struct dma_buf *dma_buf;
+-
+-	/**
+-	 * import_attach - dma buf attachment backing this object
+-	 *
+-	 * Any foreign dma_buf imported as a gem object has this set to the
+-	 * attachment point for the device. This is invariant over the lifetime
+-	 * of a gem object.
+-	 *
+-	 * The driver's ->gem_free_object callback is responsible for cleaning
+-	 * up the dma_buf attachment and references acquired at import time.
+-	 *
+-	 * Note that the drm gem/prime core does not depend upon drivers setting
+-	 * this field any more. So for drivers where this doesn't make sense
+-	 * (e.g. virtual devices or a displaylink behind an usb bus) they can
+-	 * simply leave it as NULL.
+-	 */
+-	struct dma_buf_attachment *import_attach;
+-};
+-
+-#include <drm/drm_crtc.h>
+-
+-/* per-master structure */
+ struct drm_master {
+-
+-	struct kref refcount; /* refcount for this master */
+-
+-	struct list_head head; /**< each minor contains a list of masters */
+-	struct drm_minor *minor; /**< link back to minor we are a master for */
+-
+-	char *unique;			/**< Unique identifier: e.g., busid */
+-	int unique_len;			/**< Length of unique field */
+-	int unique_size;		/**< amount allocated */
+-
+-	int blocked;			/**< Blocked due to VC switch? */
+-
+-	/** \name Authentication */
+-	/*@{ */
++	struct kref refcount;
++	struct drm_minor *minor;
++	char *unique;
++	int unique_len;
+ 	struct drm_open_hash magiclist;
+ 	struct list_head magicfree;
+-	/*@} */
+-
+-	struct drm_lock_data lock;	/**< Information on hardware lock */
+-
+-	void *driver_priv; /**< Private structure for driver to use */
++	struct drm_lock_data lock;
++	void *driver_priv;
+ };
+ 
+ /* Size of ringbuffer for vblank timestamps. Just double-buffer
+@@ -746,23 +363,13 @@
+ /* Flags and return codes for get_vblank_timestamp() driver function. */
+ #define DRM_CALLED_FROM_VBLIRQ 1
+ #define DRM_VBLANKTIME_SCANOUTPOS_METHOD (1 << 0)
+-#define DRM_VBLANKTIME_INVBL             (1 << 1)
++#define DRM_VBLANKTIME_IN_VBLANK         (1 << 1)
+ 
+ /* get_scanout_position() return flags */
+ #define DRM_SCANOUTPOS_VALID        (1 << 0)
+-#define DRM_SCANOUTPOS_INVBL        (1 << 1)
++#define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
+ #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
+ 
+-struct drm_bus {
+-	int bus_type;
+-	int (*get_irq)(struct drm_device *dev);
+-	const char *(*get_name)(struct drm_device *dev);
+-	int (*set_busid)(struct drm_device *dev, struct drm_master *master);
+-	int (*set_unique)(struct drm_device *dev, struct drm_master *master,
+-			  struct drm_unique *unique);
+-	int (*irq_by_busid)(struct drm_device *dev, struct drm_irq_busid *p);
+-};
+-
+ /**
+  * DRM driver structure. This structure represent the common code for
+  * a family of cards. There will one drm_device for each card present
+@@ -781,6 +388,7 @@
+ 	int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file *file_priv);
+ 	int (*dma_quiescent) (struct drm_device *);
+ 	int (*context_dtor) (struct drm_device *dev, int context);
++	int (*set_busid)(struct drm_device *dev, struct drm_master *master);
+ 
+ 	/**
+ 	 * get_vblank_counter - get raw hardware vblank counter
+@@ -959,9 +567,12 @@
+ 	/* low-level interface used by drm_gem_prime_{import,export} */
+ 	int (*gem_prime_pin)(struct drm_gem_object *obj);
+ 	void (*gem_prime_unpin)(struct drm_gem_object *obj);
++	struct reservation_object * (*gem_prime_res_obj)(
++				struct drm_gem_object *obj);
+ 	struct sg_table *(*gem_prime_get_sg_table)(struct drm_gem_object *obj);
+ 	struct drm_gem_object *(*gem_prime_import_sg_table)(
+-				struct drm_device *dev, size_t size,
++				struct drm_device *dev,
++				struct dma_buf_attachment *attach,
+ 				struct sg_table *sgt);
+ 	void *(*gem_prime_vmap)(struct drm_gem_object *obj);
+ 	void (*gem_prime_vunmap)(struct drm_gem_object *obj, void *vaddr);
+@@ -997,21 +608,17 @@
+ 	const struct drm_ioctl_desc *ioctls;
+ 	int num_ioctls;
+ 	const struct file_operations *fops;
+-	union {
+-		struct pci_driver *pci;
+-		struct platform_device *platform_device;
+-		struct usb_driver *usb;
+-	} kdriver;
+-	struct drm_bus *bus;
+ 
+ 	/* List of devices hanging off this driver with stealth attach. */
+ 	struct list_head legacy_dev_list;
+ };
+ 
+-#define DRM_MINOR_UNASSIGNED 0
+-#define DRM_MINOR_LEGACY 1
+-#define DRM_MINOR_CONTROL 2
+-#define DRM_MINOR_RENDER 3
++enum drm_minor_type {
++	DRM_MINOR_LEGACY,
++	DRM_MINOR_CONTROL,
++	DRM_MINOR_RENDER,
++	DRM_MINOR_CNT,
++};
+ 
+ /**
+  * Info file list entry. This structure represents a debugfs or proc file to
+@@ -1040,7 +647,6 @@
+ struct drm_minor {
+ 	int index;			/**< Minor device number */
+ 	int type;                       /**< Control or render */
+-	dev_t device;			/**< Device number for mknod */
+ 	struct device *kdev;		/**< Linux device */
+ 	struct drm_device *dev;
+ 
+@@ -1049,26 +655,11 @@
+ 	struct list_head debugfs_list;
+ 	struct mutex debugfs_lock; /* Protects debugfs_list. */
+ 
+-	struct drm_master *master; /* currently active master for this node */
+-	struct list_head master_list;
++	/* currently active master for this node. Protected by master_mutex */
++	struct drm_master *master;
+ 	struct drm_mode_group mode_group;
+ };
+ 
+-/* mode specified on the command line */
+-struct drm_cmdline_mode {
+-	bool specified;
+-	bool refresh_specified;
+-	bool bpp_specified;
+-	int xres, yres;
+-	int bpp;
+-	int refresh;
+-	bool rb;
+-	bool interlace;
+-	bool cvt;
+-	bool margins;
+-	enum drm_connector_force force;
+-};
+-
+ 
+ struct drm_pending_vblank_event {
+ 	struct drm_pending_event base;
+@@ -1077,14 +668,17 @@
+ };
+ 
+ struct drm_vblank_crtc {
++	struct drm_device *dev;		/* pointer to the drm_device */
+ 	wait_queue_head_t queue;	/**< VBLANK wait queue */
+ 	struct timeval time[DRM_VBLANKTIME_RBSIZE];	/**< timestamp of current count */
++	struct timer_list disable_timer;		/* delayed disable timer */
+ 	atomic_t count;			/**< number of VBLANK interrupts */
+ 	atomic_t refcount;		/* number of users of vblank interruptsper crtc */
+ 	u32 last;			/* protected by dev->vbl_lock, used */
+ 					/* for wraparound handling */
+ 	u32 last_wait;			/* Last vblank seqno waited per CRTC */
+ 	unsigned int inmodeset;		/* Display driver is setting mode */
++	int crtc;			/* crtc index */
+ 	bool enabled;			/* so we don't call enable more than
+ 					   once per disable */
+ };
+@@ -1095,18 +689,32 @@
+  */
+ struct drm_device {
+ 	struct list_head legacy_dev_list;/**< list of devices per driver for stealth attach cleanup */
+-	char *devname;			/**< For /proc/interrupts */
+ 	int if_version;			/**< Highest interface version set */
+ 
++	/** \name Lifetime Management */
++	/*@{ */
++	struct kref ref;		/**< Object ref-count */
++	struct device *dev;		/**< Device structure of bus-device */
++	struct drm_driver *driver;	/**< DRM driver managing the device */
++	void *dev_private;		/**< DRM driver private data */
++	struct drm_minor *control;		/**< Control node */
++	struct drm_minor *primary;		/**< Primary node */
++	struct drm_minor *render;		/**< Render node */
++	atomic_t unplugged;			/**< Flag whether dev is dead */
++	struct inode *anon_inode;		/**< inode for private address-space */
++	char *unique;				/**< unique name of the device */
++	/*@} */
++
+ 	/** \name Locks */
+ 	/*@{ */
+-	spinlock_t count_lock;		/**< For inuse, drm_device::open_count, drm_device::buf_use */
+ 	struct mutex struct_mutex;	/**< For others */
++	struct mutex master_mutex;      /**< For drm_minor::master and drm_file::is_master */
+ 	/*@} */
+ 
+ 	/** \name Usage Counters */
+ 	/*@{ */
+-	int open_count;			/**< Outstanding files open */
++	int open_count;			/**< Outstanding files open, protected by drm_global_mutex. */
++	spinlock_t buf_lock;		/**< For drm_device::buf_use and a few other things. */
+ 	int buf_use;			/**< Buffers in use -- cannot alloc */
+ 	atomic_t buf_alloc;		/**< Buffer allocation in progress */
+ 	/*@} */
+@@ -1137,6 +745,8 @@
+ 	/** \name Context support */
+ 	/*@{ */
+ 	bool irq_enabled;		/**< True if irq handler is enabled */
++	int irq;
++
+ 	__volatile__ long context_flag;	/**< Context swapping flag */
+ 	int last_context;		/**< Last current context */
+ 	/*@} */
+@@ -1152,12 +762,21 @@
+ 	 */
+ 	bool vblank_disable_allowed;
+ 
++	/*
++	 * If true, vblank interrupt will be disabled immediately when the
++	 * refcount drops to zero, as opposed to via the vblank disable
++	 * timer.
++	 * This can be set to true it the hardware has a working vblank
++	 * counter and the driver uses drm_vblank_on() and drm_vblank_off()
++	 * appropriately.
++	 */
++	bool vblank_disable_immediate;
++
+ 	/* array of size num_crtcs */
+ 	struct drm_vblank_crtc *vblank;
+ 
+ 	spinlock_t vblank_time_lock;    /**< Protects vblank count and time updates during vblank enable/disable */
+ 	spinlock_t vbl_lock;
+-	struct timer_list vblank_disable_timer;
+ 
+ 	u32 max_vblank_count;           /**< size of vblank counter register */
+ 
+@@ -1171,30 +790,26 @@
+ 
+ 	struct drm_agp_head *agp;	/**< AGP data */
+ 
+-	struct device *dev;             /**< Device structure */
+ 	struct pci_dev *pdev;		/**< PCI device structure */
+ #ifdef __alpha__
+ 	struct pci_controller *hose;
+ #endif
+ 
+ 	struct platform_device *platformdev; /**< Platform device struture */
+-	struct usb_device *usbdev;
+ 
+ 	struct drm_sg_mem *sg;	/**< Scatter gather memory */
+ 	unsigned int num_crtcs;                  /**< Number of CRTCs on this device */
+-	void *dev_private;		/**< device private data */
+-	struct address_space *dev_mapping;
+-	struct drm_sigdata sigdata;	   /**< For block_all_signals */
+ 	sigset_t sigmask;
+ 
+-	struct drm_driver *driver;
++	struct {
++		int context;
++		struct drm_hw_lock *lock;
++	} sigdata;
++
+ 	struct drm_local_map *agp_buffer_map;
+ 	unsigned int agp_buffer_token;
+-	struct drm_minor *control;		/**< Control node for card */
+-	struct drm_minor *primary;		/**< render type primary screen head */
+-	struct drm_minor *render;		/**< render node for card */
+ 
+-        struct drm_mode_config mode_config;	/**< Current mode config */
++	struct drm_mode_config mode_config;	/**< Current mode config */
+ 
+ 	/** \name GEM information */
+ 	/*@{ */
+@@ -1203,8 +818,6 @@
+ 	struct drm_vma_offset_manager *vma_offset_manager;
+ 	/*@} */
+ 	int switch_power_state;
+-
+-	atomic_t unplugged; /* device has been unplugged or gone away */
+ };
+ 
+ #define DRM_SWITCH_POWER_ON 0
+@@ -1218,11 +831,6 @@
+ 	return ((dev->driver->driver_features & feature) ? 1 : 0);
+ }
+ 
+-static inline int drm_dev_to_irq(struct drm_device *dev)
+-{
+-	return dev->driver->bus->get_irq(dev);
+-}
+-
+ static inline void drm_device_set_unplugged(struct drm_device *dev)
+ {
+ 	smp_wmb();
+@@ -1236,14 +844,19 @@
+ 	return ret;
+ }
+ 
+-static inline bool drm_modeset_is_locked(struct drm_device *dev)
++static inline bool drm_is_render_client(const struct drm_file *file_priv)
+ {
+-	return mutex_is_locked(&dev->mode_config.mutex);
++	return file_priv->minor->type == DRM_MINOR_RENDER;
+ }
+ 
+-static inline bool drm_is_render_client(struct drm_file *file_priv)
++static inline bool drm_is_control_client(const struct drm_file *file_priv)
+ {
+-	return file_priv->minor->type == DRM_MINOR_RENDER;
++	return file_priv->minor->type == DRM_MINOR_CONTROL;
++}
++
++static inline bool drm_is_primary_client(const struct drm_file *file_priv)
++{
++	return file_priv->minor->type == DRM_MINOR_LEGACY;
+ }
+ 
+ /******************************************************************/
+@@ -1255,136 +868,33 @@
+ 		      unsigned int cmd, unsigned long arg);
+ extern long drm_compat_ioctl(struct file *filp,
+ 			     unsigned int cmd, unsigned long arg);
+-extern int drm_lastclose(struct drm_device *dev);
++extern bool drm_ioctl_flags(unsigned int nr, unsigned int *flags);
+ 
+ 				/* Device support (drm_fops.h) */
+-extern struct mutex drm_global_mutex;
+ extern int drm_open(struct inode *inode, struct file *filp);
+-extern int drm_stub_open(struct inode *inode, struct file *filp);
+ extern ssize_t drm_read(struct file *filp, char __user *buffer,
+ 			size_t count, loff_t *offset);
+ extern int drm_release(struct inode *inode, struct file *filp);
+ 
+ 				/* Mapping support (drm_vm.h) */
+-extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
+-extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma);
+-extern void drm_vm_open_locked(struct drm_device *dev, struct vm_area_struct *vma);
+-extern void drm_vm_close_locked(struct drm_device *dev, struct vm_area_struct *vma);
+ extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
+ 
+-				/* Memory management support (drm_memory.h) */
+-#include <drm/drm_memory.h>
+-
+-
+-				/* Misc. IOCTL support (drm_ioctl.h) */
+-extern int drm_irq_by_busid(struct drm_device *dev, void *data,
+-			    struct drm_file *file_priv);
+-extern int drm_getunique(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv);
+-extern int drm_setunique(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv);
+-extern int drm_getmap(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_getclient(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv);
+-extern int drm_getstats(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-extern int drm_getcap(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_setclientcap(struct drm_device *dev, void *data,
+-			    struct drm_file *file_priv);
+-extern int drm_setversion(struct drm_device *dev, void *data,
+-			  struct drm_file *file_priv);
+-extern int drm_noop(struct drm_device *dev, void *data,
+-		    struct drm_file *file_priv);
+-
+-				/* Context IOCTL support (drm_context.h) */
+-extern int drm_resctx(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_addctx(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_getctx(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_switchctx(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv);
+-extern int drm_newctx(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_rmctx(struct drm_device *dev, void *data,
+-		     struct drm_file *file_priv);
+-
+-extern int drm_ctxbitmap_init(struct drm_device *dev);
+-extern void drm_ctxbitmap_cleanup(struct drm_device *dev);
+-extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
+-
+-extern int drm_setsareactx(struct drm_device *dev, void *data,
+-			   struct drm_file *file_priv);
+-extern int drm_getsareactx(struct drm_device *dev, void *data,
+-			   struct drm_file *file_priv);
+-
+-				/* Authentication IOCTL support (drm_auth.h) */
+-extern int drm_getmagic(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-extern int drm_authmagic(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv);
+-extern int drm_remove_magic(struct drm_master *master, drm_magic_t magic);
++/* Misc. IOCTL support (drm_ioctl.c) */
++int drm_noop(struct drm_device *dev, void *data,
++	     struct drm_file *file_priv);
+ 
+ /* Cache management (drm_cache.c) */
+ void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
+ void drm_clflush_sg(struct sg_table *st);
+-void drm_clflush_virt_range(char *addr, unsigned long length);
+-
+-				/* Locking IOCTL support (drm_lock.h) */
+-extern int drm_lock(struct drm_device *dev, void *data,
+-		    struct drm_file *file_priv);
+-extern int drm_unlock(struct drm_device *dev, void *data,
+-		      struct drm_file *file_priv);
+-extern int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context);
+-extern void drm_idlelock_take(struct drm_lock_data *lock_data);
+-extern void drm_idlelock_release(struct drm_lock_data *lock_data);
++void drm_clflush_virt_range(void *addr, unsigned long length);
+ 
+ /*
+  * These are exported to drivers so that they can implement fencing using
+  * DMA quiscent + idle. DMA quiescent usually requires the hardware lock.
+  */
+ 
+-extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv);
+-
+-				/* Buffer management support (drm_bufs.h) */
+-extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request);
+-extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request);
+-extern int drm_addmap(struct drm_device *dev, resource_size_t offset,
+-		      unsigned int size, enum drm_map_type type,
+-		      enum drm_map_flags flags, struct drm_local_map **map_ptr);
+-extern int drm_addmap_ioctl(struct drm_device *dev, void *data,
+-			    struct drm_file *file_priv);
+-extern int drm_rmmap(struct drm_device *dev, struct drm_local_map *map);
+-extern int drm_rmmap_locked(struct drm_device *dev, struct drm_local_map *map);
+-extern int drm_rmmap_ioctl(struct drm_device *dev, void *data,
+-			   struct drm_file *file_priv);
+-extern int drm_addbufs(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv);
+-extern int drm_infobufs(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-extern int drm_markbufs(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-extern int drm_freebufs(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-extern int drm_mapbufs(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv);
+-extern int drm_dma_ioctl(struct drm_device *dev, void *data,
+-			 struct drm_file *file_priv);
+-
+-				/* DMA support (drm_dma.h) */
+-extern int drm_legacy_dma_setup(struct drm_device *dev);
+-extern void drm_legacy_dma_takedown(struct drm_device *dev);
+-extern void drm_free_buffer(struct drm_device *dev, struct drm_buf * buf);
+-extern void drm_core_reclaim_buffers(struct drm_device *dev,
+-				     struct drm_file *filp);
+-
+ 				/* IRQ support (drm_irq.h) */
+-extern int drm_control(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv);
+-extern int drm_irq_install(struct drm_device *dev);
++extern int drm_irq_install(struct drm_device *dev, int irq);
+ extern int drm_irq_uninstall(struct drm_device *dev);
+ 
+ extern int drm_vblank_init(struct drm_device *dev, int num_crtcs);
+@@ -1398,10 +908,16 @@
+ extern bool drm_handle_vblank(struct drm_device *dev, int crtc);
+ extern int drm_vblank_get(struct drm_device *dev, int crtc);
+ extern void drm_vblank_put(struct drm_device *dev, int crtc);
++extern int drm_crtc_vblank_get(struct drm_crtc *crtc);
++extern void drm_crtc_vblank_put(struct drm_crtc *crtc);
++extern void drm_wait_one_vblank(struct drm_device *dev, int crtc);
++extern void drm_crtc_wait_one_vblank(struct drm_crtc *crtc);
+ extern void drm_vblank_off(struct drm_device *dev, int crtc);
++extern void drm_vblank_on(struct drm_device *dev, int crtc);
++extern void drm_crtc_vblank_off(struct drm_crtc *crtc);
++extern void drm_crtc_vblank_on(struct drm_crtc *crtc);
+ extern void drm_vblank_cleanup(struct drm_device *dev);
+-extern u32 drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
+-				     struct timeval *tvblank, unsigned flags);
++
+ extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
+ 						 int crtc, int *max_error,
+ 						 struct timeval *vblank_time,
+@@ -1411,73 +927,38 @@
+ extern void drm_calc_timestamping_constants(struct drm_crtc *crtc,
+ 					    const struct drm_display_mode *mode);
+ 
+-extern bool
+-drm_mode_parse_command_line_for_connector(const char *mode_option,
+-					  struct drm_connector *connector,
+-					  struct drm_cmdline_mode *mode);
+-
+-extern struct drm_display_mode *
+-drm_mode_create_from_cmdline_mode(struct drm_device *dev,
+-				  struct drm_cmdline_mode *cmd);
+-
+-extern int drm_display_mode_from_videomode(const struct videomode *vm,
+-					   struct drm_display_mode *dmode);
+-extern int of_get_drm_display_mode(struct device_node *np,
+-				   struct drm_display_mode *dmode,
+-				   int index);
++/**
++ * drm_crtc_vblank_waitqueue - get vblank waitqueue for the CRTC
++ * @crtc: which CRTC's vblank waitqueue to retrieve
++ *
++ * This function returns a pointer to the vblank waitqueue for the CRTC.
++ * Drivers can use this to implement vblank waits using wait_event() & co.
++ */
++static inline wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc)
++{
++	return &crtc->dev->vblank[drm_crtc_index(crtc)].queue;
++}
+ 
+ /* Modesetting support */
+ extern void drm_vblank_pre_modeset(struct drm_device *dev, int crtc);
+ extern void drm_vblank_post_modeset(struct drm_device *dev, int crtc);
+-extern int drm_modeset_ctl(struct drm_device *dev, void *data,
+-			   struct drm_file *file_priv);
+-
+-				/* AGP/GART support (drm_agpsupport.h) */
+-
+-#include <drm/drm_agpsupport.h>
+ 
+ 				/* Stub support (drm_stub.h) */
+-extern int drm_setmaster_ioctl(struct drm_device *dev, void *data,
+-			       struct drm_file *file_priv);
+-extern int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
+-				struct drm_file *file_priv);
+-struct drm_master *drm_master_create(struct drm_minor *minor);
+ extern struct drm_master *drm_master_get(struct drm_master *master);
+ extern void drm_master_put(struct drm_master **master);
+ 
+ extern void drm_put_dev(struct drm_device *dev);
+ extern void drm_unplug_dev(struct drm_device *dev);
+ extern unsigned int drm_debug;
+-extern unsigned int drm_rnodes;
+-
+-extern unsigned int drm_vblank_offdelay;
+-extern unsigned int drm_timestamp_precision;
+-extern unsigned int drm_timestamp_monotonic;
+-
+-extern struct class *drm_class;
+-extern struct dentry *drm_debugfs_root;
+-
+-extern struct idr drm_minors_idr;
+-
+-extern struct drm_local_map *drm_getsarea(struct drm_device *dev);
+ 
+ 				/* Debugfs support */
+ #if defined(CONFIG_DEBUG_FS)
+-extern int drm_debugfs_init(struct drm_minor *minor, int minor_id,
+-			    struct dentry *root);
+ extern int drm_debugfs_create_files(const struct drm_info_list *files,
+ 				    int count, struct dentry *root,
+ 				    struct drm_minor *minor);
+ extern int drm_debugfs_remove_files(const struct drm_info_list *files,
+ 				    int count, struct drm_minor *minor);
+-extern int drm_debugfs_cleanup(struct drm_minor *minor);
+ #else
+-static inline int drm_debugfs_init(struct drm_minor *minor, int minor_id,
+-				   struct dentry *root)
+-{
+-	return 0;
+-}
+-
+ static inline int drm_debugfs_create_files(const struct drm_info_list *files,
+ 					   int count, struct dentry *root,
+ 					   struct drm_minor *minor)
+@@ -1490,22 +971,8 @@
+ {
+ 	return 0;
+ }
+-
+-static inline int drm_debugfs_cleanup(struct drm_minor *minor)
+-{
+-	return 0;
+-}
+ #endif
+ 
+-				/* Info file support */
+-extern int drm_name_info(struct seq_file *m, void *data);
+-extern int drm_vm_info(struct seq_file *m, void *data);
+-extern int drm_bufs_info(struct seq_file *m, void *data);
+-extern int drm_vblank_info(struct seq_file *m, void *data);
+-extern int drm_clients_info(struct seq_file *m, void* data);
+-extern int drm_gem_name_info(struct seq_file *m, void *data);
+-
+-
+ extern struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
+ 		struct drm_gem_object *obj, int flags);
+ extern int drm_gem_prime_handle_to_fd(struct drm_device *dev,
+@@ -1517,153 +984,31 @@
+ 		struct drm_file *file_priv, int prime_fd, uint32_t *handle);
+ extern void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
+ 
+-extern int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
+-					struct drm_file *file_priv);
+-extern int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
+-					struct drm_file *file_priv);
+-
+ extern int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
+ 					    dma_addr_t *addrs, int max_pages);
+-extern struct sg_table *drm_prime_pages_to_sg(struct page **pages, int nr_pages);
++extern struct sg_table *drm_prime_pages_to_sg(struct page **pages, unsigned int nr_pages);
+ extern void drm_prime_gem_destroy(struct drm_gem_object *obj, struct sg_table *sg);
+ 
+-int drm_gem_dumb_destroy(struct drm_file *file,
+-			 struct drm_device *dev,
+-			 uint32_t handle);
+-
+-void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv);
+-void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv);
+-void drm_prime_remove_buf_handle_locked(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf);
+-
+-#if DRM_DEBUG_CODE
+-extern int drm_vma_info(struct seq_file *m, void *data);
+-#endif
+-
+-				/* Scatter Gather Support (drm_scatter.h) */
+-extern void drm_legacy_sg_cleanup(struct drm_device *dev);
+-extern int drm_sg_alloc(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-extern int drm_sg_free(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv);
+ 
+-			       /* ATI PCIGART support (ati_pcigart.h) */
+-extern int drm_ati_pcigart_init(struct drm_device *dev,
+-				struct drm_ati_pcigart_info * gart_info);
+-extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
+-				   struct drm_ati_pcigart_info * gart_info);
+-
+-extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
+-				       size_t align);
+-extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
+-extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
++extern struct drm_dma_handle *drm_pci_alloc(struct drm_device *dev, size_t size,
++					    size_t align);
++extern void drm_pci_free(struct drm_device *dev, struct drm_dma_handle * dmah);
+ 
+ 			       /* sysfs support (drm_sysfs.c) */
+-struct drm_sysfs_class;
+-extern struct class *drm_sysfs_create(struct module *owner, char *name);
+-extern void drm_sysfs_destroy(void);
+-extern int drm_sysfs_device_add(struct drm_minor *minor);
+ extern void drm_sysfs_hotplug_event(struct drm_device *dev);
+-extern void drm_sysfs_device_remove(struct drm_minor *minor);
+-extern int drm_sysfs_connector_add(struct drm_connector *connector);
+-extern void drm_sysfs_connector_remove(struct drm_connector *connector);
+-
+-/* Graphics Execution Manager library functions (drm_gem.c) */
+-int drm_gem_init(struct drm_device *dev);
+-void drm_gem_destroy(struct drm_device *dev);
+-void drm_gem_object_release(struct drm_gem_object *obj);
+-void drm_gem_object_free(struct kref *kref);
+-int drm_gem_object_init(struct drm_device *dev,
+-			struct drm_gem_object *obj, size_t size);
+-void drm_gem_private_object_init(struct drm_device *dev,
+-				 struct drm_gem_object *obj, size_t size);
+-void drm_gem_vm_open(struct vm_area_struct *vma);
+-void drm_gem_vm_close(struct vm_area_struct *vma);
+-int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
+-		     struct vm_area_struct *vma);
+-int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+ 
+-#include <drm/drm_global.h>
+-
+-static inline void
+-drm_gem_object_reference(struct drm_gem_object *obj)
+-{
+-	kref_get(&obj->refcount);
+-}
+-
+-static inline void
+-drm_gem_object_unreference(struct drm_gem_object *obj)
+-{
+-	if (obj != NULL)
+-		kref_put(&obj->refcount, drm_gem_object_free);
+-}
+-
+-static inline void
+-drm_gem_object_unreference_unlocked(struct drm_gem_object *obj)
+-{
+-	if (obj && !atomic_add_unless(&obj->refcount.refcount, -1, 1)) {
+-		struct drm_device *dev = obj->dev;
+-
+-		mutex_lock(&dev->struct_mutex);
+-		if (likely(atomic_dec_and_test(&obj->refcount.refcount)))
+-			drm_gem_object_free(&obj->refcount);
+-		mutex_unlock(&dev->struct_mutex);
+-	}
+-}
+-
+-int drm_gem_handle_create_tail(struct drm_file *file_priv,
+-			       struct drm_gem_object *obj,
+-			       u32 *handlep);
+-int drm_gem_handle_create(struct drm_file *file_priv,
+-			  struct drm_gem_object *obj,
+-			  u32 *handlep);
+-int drm_gem_handle_delete(struct drm_file *filp, u32 handle);
+-
+-
+-void drm_gem_free_mmap_offset(struct drm_gem_object *obj);
+-int drm_gem_create_mmap_offset(struct drm_gem_object *obj);
+-int drm_gem_create_mmap_offset_size(struct drm_gem_object *obj, size_t size);
+-
+-struct page **drm_gem_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
+-void drm_gem_put_pages(struct drm_gem_object *obj, struct page **pages,
+-		bool dirty, bool accessed);
+-
+-struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
+-					     struct drm_file *filp,
+-					     u32 handle);
+-int drm_gem_close_ioctl(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
+-			struct drm_file *file_priv);
+-int drm_gem_open_ioctl(struct drm_device *dev, void *data,
+-		       struct drm_file *file_priv);
+-void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
+-void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
+-
+-extern void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev);
+-extern void drm_core_ioremap_wc(struct drm_local_map *map, struct drm_device *dev);
+-extern void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev);
+-
+-static __inline__ struct drm_local_map *drm_core_findmap(struct drm_device *dev,
+-							 unsigned int token)
+-{
+-	struct drm_map_list *_entry;
+-	list_for_each_entry(_entry, &dev->maplist, head)
+-	    if (_entry->user_token == token)
+-		return _entry->map;
+-	return NULL;
+-}
+-
+-static __inline__ void drm_core_dropmap(struct drm_local_map *map)
+-{
+-}
+-
+-#include <drm/drm_mem_util.h>
+ 
+ struct drm_device *drm_dev_alloc(struct drm_driver *driver,
+ 				 struct device *parent);
+-void drm_dev_free(struct drm_device *dev);
++void drm_dev_ref(struct drm_device *dev);
++void drm_dev_unref(struct drm_device *dev);
+ int drm_dev_register(struct drm_device *dev, unsigned long flags);
+ void drm_dev_unregister(struct drm_device *dev);
++int drm_dev_set_unique(struct drm_device *dev, const char *fmt, ...);
++
++struct drm_minor *drm_minor_acquire(unsigned int minor_id);
++void drm_minor_release(struct drm_minor *minor);
++
+ /*@}*/
+ 
+ /* PCI section */
+@@ -1683,9 +1028,25 @@
+ 
+ extern int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver);
+ extern void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver);
++#ifdef CONFIG_PCI
+ extern int drm_get_pci_dev(struct pci_dev *pdev,
+ 			   const struct pci_device_id *ent,
+ 			   struct drm_driver *driver);
++extern int drm_pci_set_busid(struct drm_device *dev, struct drm_master *master);
++#else
++static inline int drm_get_pci_dev(struct pci_dev *pdev,
++				  const struct pci_device_id *ent,
++				  struct drm_driver *driver)
++{
++	return -ENOSYS;
++}
++
++static inline int drm_pci_set_busid(struct drm_device *dev,
++				    struct drm_master *master)
++{
++	return -ENOSYS;
++}
++#endif
+ 
+ #define DRM_PCIE_SPEED_25 1
+ #define DRM_PCIE_SPEED_50 2
+@@ -1695,6 +1056,7 @@
+ 
+ /* platform section */
+ extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
++extern int drm_platform_set_busid(struct drm_device *d, struct drm_master *m);
+ 
+ /* returns true if currently okay to sleep */
+ static __inline__ bool drm_can_sleep(void)
+@@ -1704,5 +1066,4 @@
+ 	return true;
+ }
+ 
+-#endif				/* __KERNEL__ */
+ #endif
+diff -Naur a/include/drm/drm_plane_helper.h b/include/drm/drm_plane_helper.h
+--- a/include/drm/drm_plane_helper.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/drm/drm_plane_helper.h	2015-03-26 14:42:38.758435422 +0530
+@@ -0,0 +1,115 @@
++/*
++ * Copyright (C) 2011-2013 Intel Corporation
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ */
++
++#ifndef DRM_PLANE_HELPER_H
++#define DRM_PLANE_HELPER_H
++
++#include <drm/drm_rect.h>
++#include <drm/drm_crtc.h>
++
++/*
++ * Drivers that don't allow primary plane scaling may pass this macro in place
++ * of the min/max scale parameters of the update checker function.
++ *
++ * Due to src being in 16.16 fixed point and dest being in integer pixels,
++ * 1<<16 represents no scaling.
++ */
++#define DRM_PLANE_HELPER_NO_SCALING (1<<16)
++
++/**
++ * DOC: plane helpers
++ *
++ * Helper functions to assist with creation and handling of CRTC primary
++ * planes.
++ */
++
++extern int drm_crtc_init(struct drm_device *dev,
++			 struct drm_crtc *crtc,
++			 const struct drm_crtc_funcs *funcs);
++
++/**
++ * drm_plane_helper_funcs - helper operations for CRTCs
++ * @prepare_fb: prepare a framebuffer for use by the plane
++ * @cleanup_fb: cleanup a framebuffer when it's no longer used by the plane
++ * @atomic_check: check that a given atomic state is valid and can be applied
++ * @atomic_update: apply an atomic state to the plane
++ *
++ * The helper operations are called by the mid-layer CRTC helper.
++ */
++struct drm_plane_helper_funcs {
++	int (*prepare_fb)(struct drm_plane *plane,
++			  struct drm_framebuffer *fb);
++	void (*cleanup_fb)(struct drm_plane *plane,
++			   struct drm_framebuffer *fb);
++
++	int (*atomic_check)(struct drm_plane *plane,
++			    struct drm_plane_state *state);
++	void (*atomic_update)(struct drm_plane *plane,
++			      struct drm_plane_state *old_state);
++};
++
++static inline void drm_plane_helper_add(struct drm_plane *plane,
++					const struct drm_plane_helper_funcs *funcs)
++{
++	plane->helper_private = (void *)funcs;
++}
++
++extern int drm_plane_helper_check_update(struct drm_plane *plane,
++					 struct drm_crtc *crtc,
++					 struct drm_framebuffer *fb,
++					 struct drm_rect *src,
++					 struct drm_rect *dest,
++					 const struct drm_rect *clip,
++					 int min_scale,
++					 int max_scale,
++					 bool can_position,
++					 bool can_update_disabled,
++					 bool *visible);
++extern int drm_primary_helper_update(struct drm_plane *plane,
++				     struct drm_crtc *crtc,
++				     struct drm_framebuffer *fb,
++				     int crtc_x, int crtc_y,
++				     unsigned int crtc_w, unsigned int crtc_h,
++				     uint32_t src_x, uint32_t src_y,
++				     uint32_t src_w, uint32_t src_h);
++extern int drm_primary_helper_disable(struct drm_plane *plane);
++extern void drm_primary_helper_destroy(struct drm_plane *plane);
++extern const struct drm_plane_funcs drm_primary_helper_funcs;
++extern struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev,
++							 const uint32_t *formats,
++							 int num_formats);
++
++
++int drm_plane_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
++			    struct drm_framebuffer *fb,
++			    int crtc_x, int crtc_y,
++			    unsigned int crtc_w, unsigned int crtc_h,
++			    uint32_t src_x, uint32_t src_y,
++			    uint32_t src_w, uint32_t src_h);
++int drm_plane_helper_disable(struct drm_plane *plane);
++
++/* For use by drm_crtc_helper.c */
++int drm_plane_helper_commit(struct drm_plane *plane,
++			    struct drm_plane_state *plane_state,
++			    struct drm_framebuffer *old_fb);
++#endif
+diff -Naur a/include/drm/drm_rect.h b/include/drm/drm_rect.h
+--- a/include/drm/drm_rect.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/drm_rect.h	2015-03-26 14:42:38.758435422 +0530
+@@ -163,5 +163,11 @@
+ 				 struct drm_rect *dst,
+ 				 int min_vscale, int max_vscale);
+ void drm_rect_debug_print(const struct drm_rect *r, bool fixed_point);
++void drm_rect_rotate(struct drm_rect *r,
++		     int width, int height,
++		     unsigned int rotation);
++void drm_rect_rotate_inv(struct drm_rect *r,
++			 int width, int height,
++			 unsigned int rotation);
+ 
+ #endif
+diff -Naur a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
+--- a/include/drm/i915_pciids.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/i915_pciids.h	2015-03-26 14:42:38.758435422 +0530
+@@ -191,8 +191,8 @@
+ 	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
+ 	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
+ 	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+-	INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
+-	INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
++	INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
++	INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
+ 	INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
+ 	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
+ 	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
+@@ -223,14 +223,57 @@
+ 	_INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
+ 	_INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
+ 
+-#define INTEL_BDW_M_IDS(info) \
++#define INTEL_BDW_GT12M_IDS(info) \
+ 	_INTEL_BDW_M_IDS(1, info), \
+-	_INTEL_BDW_M_IDS(2, info), \
+-	_INTEL_BDW_M_IDS(3, info)
++	_INTEL_BDW_M_IDS(2, info)
+ 
+-#define INTEL_BDW_D_IDS(info) \
++#define INTEL_BDW_GT12D_IDS(info) \
+ 	_INTEL_BDW_D_IDS(1, info), \
+-	_INTEL_BDW_D_IDS(2, info), \
++	_INTEL_BDW_D_IDS(2, info)
++
++#define INTEL_BDW_GT3M_IDS(info) \
++	_INTEL_BDW_M_IDS(3, info)
++
++#define INTEL_BDW_GT3D_IDS(info) \
+ 	_INTEL_BDW_D_IDS(3, info)
+ 
++#define INTEL_BDW_RSVDM_IDS(info) \
++	_INTEL_BDW_M_IDS(4, info)
++
++#define INTEL_BDW_RSVDD_IDS(info) \
++	_INTEL_BDW_D_IDS(4, info)
++
++#define INTEL_BDW_M_IDS(info) \
++	INTEL_BDW_GT12M_IDS(info), \
++	INTEL_BDW_GT3M_IDS(info), \
++	INTEL_BDW_RSVDM_IDS(info)
++
++#define INTEL_BDW_D_IDS(info) \
++	INTEL_BDW_GT12D_IDS(info), \
++	INTEL_BDW_GT3D_IDS(info), \
++	INTEL_BDW_RSVDD_IDS(info)
++
++#define INTEL_CHV_IDS(info) \
++	INTEL_VGA_DEVICE(0x22b0, info), \
++	INTEL_VGA_DEVICE(0x22b1, info), \
++	INTEL_VGA_DEVICE(0x22b2, info), \
++	INTEL_VGA_DEVICE(0x22b3, info)
++
++#define INTEL_SKL_IDS(info) \
++	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
++	INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
++	INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
++	INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
++	INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
++	INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
++	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
++	INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
++	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
++	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
++	INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
++	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
++	INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
++	INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
++	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
++
+ #endif /* _I915_PCIIDS_H */
+diff -Naur a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
+--- a/include/drm/i915_powerwell.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/i915_powerwell.h	2015-03-26 14:42:38.758435422 +0530
+@@ -30,7 +30,8 @@
+ #define _I915_POWERWELL_H_
+ 
+ /* For use by hda_i915 driver */
+-extern void i915_request_power_well(void);
+-extern void i915_release_power_well(void);
++extern int i915_request_power_well(void);
++extern int i915_release_power_well(void);
++extern int i915_get_cdclk_freq(void);
+ 
+ #endif				/* _I915_POWERWELL_H_ */
+diff -Naur a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
+--- a/include/drm/ttm/ttm_bo_api.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/ttm/ttm_bo_api.h	2015-03-26 14:42:38.758435422 +0530
+@@ -45,12 +45,24 @@
+ 
+ struct drm_mm_node;
+ 
++/**
++ * struct ttm_place
++ *
++ * @fpfn:	first valid page frame number to put the object
++ * @lpfn:	last valid page frame number to put the object
++ * @flags:	memory domain and caching flags for the object
++ *
++ * Structure indicating a possible place to put an object.
++ */
++struct ttm_place {
++	unsigned	fpfn;
++	unsigned	lpfn;
++	uint32_t	flags;
++};
+ 
+ /**
+  * struct ttm_placement
+  *
+- * @fpfn:		first valid page frame number to put the object
+- * @lpfn:		last valid page frame number to put the object
+  * @num_placement:	number of preferred placements
+  * @placement:		preferred placements
+  * @num_busy_placement:	number of preferred placements when need to evict buffer
+@@ -59,12 +71,10 @@
+  * Structure indicating the placement you request for an object.
+  */
+ struct ttm_placement {
+-	unsigned	fpfn;
+-	unsigned	lpfn;
+-	unsigned	num_placement;
+-	const uint32_t	*placement;
+-	unsigned	num_busy_placement;
+-	const uint32_t	*busy_placement;
++	unsigned		num_placement;
++	const struct ttm_place	*placement;
++	unsigned		num_busy_placement;
++	const struct ttm_place	*busy_placement;
+ };
+ 
+ /**
+@@ -163,7 +173,6 @@
+  * @lru: List head for the lru list.
+  * @ddestroy: List head for the delayed destroy list.
+  * @swap: List head for swap LRU list.
+- * @sync_obj: Pointer to a synchronization object.
+  * @priv_flags: Flags describing buffer object internal state.
+  * @vma_node: Address space manager node.
+  * @offset: The current GPU offset, which can have different meanings
+@@ -227,13 +236,9 @@
+ 	struct list_head io_reserve_lru;
+ 
+ 	/**
+-	 * Members protected by struct buffer_object_device::fence_lock
+-	 * In addition, setting sync_obj to anything else
+-	 * than NULL requires bo::reserved to be held. This allows for
+-	 * checking NULL while reserved but not holding the mentioned lock.
++	 * Members protected by a bo reservation.
+ 	 */
+ 
+-	void *sync_obj;
+ 	unsigned long priv_flags;
+ 
+ 	struct drm_vma_offset_node vma_node;
+@@ -455,6 +460,7 @@
+  * point to the shmem object backing a GEM object if TTM is used to back a
+  * GEM user interface.
+  * @acc_size: Accounted size for this object.
++ * @resv: Pointer to a reservation_object, or NULL to let ttm allocate one.
+  * @destroy: Destroy function. Use NULL for kfree().
+  *
+  * This function initializes a pre-allocated struct ttm_buffer_object.
+@@ -482,16 +488,16 @@
+ 			struct file *persistent_swap_storage,
+ 			size_t acc_size,
+ 			struct sg_table *sg,
++			struct reservation_object *resv,
+ 			void (*destroy) (struct ttm_buffer_object *));
+ 
+ /**
+- * ttm_bo_synccpu_object_init
++ * ttm_bo_create
+  *
+  * @bdev: Pointer to a ttm_bo_device struct.
+- * @bo: Pointer to a ttm_buffer_object to be initialized.
+  * @size: Requested size of buffer object.
+  * @type: Requested type of buffer object.
+- * @flags: Initial placement flags.
++ * @placement: Initial placement.
+  * @page_alignment: Data alignment in pages.
+  * @interruptible: If needing to sleep while waiting for GPU resources,
+  * sleep interruptible.
+@@ -520,20 +526,6 @@
+ 				struct ttm_buffer_object **p_bo);
+ 
+ /**
+- * ttm_bo_check_placement
+- *
+- * @bo:		the buffer object.
+- * @placement:	placements
+- *
+- * Performs minimal validity checking on an intended change of
+- * placement flags.
+- * Returns
+- * -EINVAL: Intended change is invalid or not allowed.
+- */
+-extern int ttm_bo_check_placement(struct ttm_buffer_object *bo,
+-					struct ttm_placement *placement);
+-
+-/**
+  * ttm_bo_init_mm
+  *
+  * @bdev: Pointer to a ttm_bo_device struct.
+diff -Naur a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
+--- a/include/drm/ttm/ttm_bo_driver.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/ttm/ttm_bo_driver.h	2015-03-26 14:42:38.758435422 +0530
+@@ -133,6 +133,7 @@
+  * struct ttm_dma_tt
+  *
+  * @ttm: Base ttm_tt struct.
++ * @cpu_address: The CPU address of the pages
+  * @dma_address: The DMA (bus) addresses of the pages
+  * @pages_list: used by some page allocation backend
+  *
+@@ -142,6 +143,7 @@
+  */
+ struct ttm_dma_tt {
+ 	struct ttm_tt ttm;
++	void **cpu_address;
+ 	dma_addr_t *dma_address;
+ 	struct list_head pages_list;
+ };
+@@ -182,6 +184,7 @@
+ 	 * @man: Pointer to a memory type manager.
+ 	 * @bo: Pointer to the buffer object we're allocating space for.
+ 	 * @placement: Placement details.
++	 * @flags: Additional placement flags.
+ 	 * @mem: Pointer to a struct ttm_mem_reg to be filled in.
+ 	 *
+ 	 * This function should allocate space in the memory type managed
+@@ -205,7 +208,7 @@
+ 	 */
+ 	int  (*get_node)(struct ttm_mem_type_manager *man,
+ 			 struct ttm_buffer_object *bo,
+-			 struct ttm_placement *placement,
++			 const struct ttm_place *place,
+ 			 struct ttm_mem_reg *mem);
+ 
+ 	/**
+@@ -309,11 +312,6 @@
+  * @move: Callback for a driver to hook in accelerated functions to
+  * move a buffer.
+  * If set to NULL, a potentially slow memcpy() move is used.
+- * @sync_obj_signaled: See ttm_fence_api.h
+- * @sync_obj_wait: See ttm_fence_api.h
+- * @sync_obj_flush: See ttm_fence_api.h
+- * @sync_obj_unref: See ttm_fence_api.h
+- * @sync_obj_ref: See ttm_fence_api.h
+  */
+ 
+ struct ttm_bo_driver {
+@@ -415,23 +413,6 @@
+ 	int (*verify_access) (struct ttm_buffer_object *bo,
+ 			      struct file *filp);
+ 
+-	/**
+-	 * In case a driver writer dislikes the TTM fence objects,
+-	 * the driver writer can replace those with sync objects of
+-	 * his / her own. If it turns out that no driver writer is
+-	 * using these. I suggest we remove these hooks and plug in
+-	 * fences directly. The bo driver needs the following functionality:
+-	 * See the corresponding functions in the fence object API
+-	 * documentation.
+-	 */
+-
+-	bool (*sync_obj_signaled) (void *sync_obj);
+-	int (*sync_obj_wait) (void *sync_obj,
+-			      bool lazy, bool interruptible);
+-	int (*sync_obj_flush) (void *sync_obj);
+-	void (*sync_obj_unref) (void **sync_obj);
+-	void *(*sync_obj_ref) (void *sync_obj);
+-
+ 	/* hook to notify driver about a driver move so it
+ 	 * can do tiling things */
+ 	void (*move_notify)(struct ttm_buffer_object *bo,
+@@ -518,8 +499,6 @@
+  *
+  * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver.
+  * @man: An array of mem_type_managers.
+- * @fence_lock: Protects the synchronizing members on *all* bos belonging
+- * to this device.
+  * @vma_manager: Address space manager
+  * lru_lock: Spinlock that protects the buffer+device lru lists and
+  * ddestroy lists.
+@@ -539,7 +518,6 @@
+ 	struct ttm_bo_global *glob;
+ 	struct ttm_bo_driver *driver;
+ 	struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES];
+-	spinlock_t fence_lock;
+ 
+ 	/*
+ 	 * Protected by internal locks.
+@@ -653,18 +631,6 @@
+ extern int ttm_tt_swapin(struct ttm_tt *ttm);
+ 
+ /**
+- * ttm_tt_cache_flush:
+- *
+- * @pages: An array of pointers to struct page:s to flush.
+- * @num_pages: Number of pages to flush.
+- *
+- * Flush the data of the indicated pages from the cpu caches.
+- * This is used when changing caching attributes of the pages from
+- * cache-coherent.
+- */
+-extern void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages);
+-
+-/**
+  * ttm_tt_set_placement_caching:
+  *
+  * @ttm A struct ttm_tt the backing pages of which will change caching policy.
+@@ -747,6 +713,7 @@
+  * @bdev: A pointer to a struct ttm_bo_device to initialize.
+  * @glob: A pointer to an initialized struct ttm_bo_global.
+  * @driver: A pointer to a struct ttm_bo_driver set up by the caller.
++ * @mapping: The address space to use for this bo.
+  * @file_page_offset: Offset into the device address space that is available
+  * for buffer data. This ensures compatibility with other users of the
+  * address space.
+@@ -758,6 +725,7 @@
+ extern int ttm_bo_device_init(struct ttm_bo_device *bdev,
+ 			      struct ttm_bo_global *glob,
+ 			      struct ttm_bo_driver *driver,
++			      struct address_space *mapping,
+ 			      uint64_t file_page_offset, bool need_dma32);
+ 
+ /**
+@@ -786,7 +754,7 @@
+ extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
+ 
+ /**
+- * ttm_bo_reserve_nolru:
++ * __ttm_bo_reserve:
+  *
+  * @bo: A pointer to a struct ttm_buffer_object.
+  * @interruptible: Sleep interruptible if waiting.
+@@ -807,10 +775,10 @@
+  * -EALREADY: Bo already reserved using @ticket. This error code will only
+  * be returned if @use_ticket is set to true.
+  */
+-static inline int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo,
+-				       bool interruptible,
+-				       bool no_wait, bool use_ticket,
+-				       struct ww_acquire_ctx *ticket)
++static inline int __ttm_bo_reserve(struct ttm_buffer_object *bo,
++				   bool interruptible,
++				   bool no_wait, bool use_ticket,
++				   struct ww_acquire_ctx *ticket)
+ {
+ 	int ret = 0;
+ 
+@@ -886,8 +854,7 @@
+ 
+ 	WARN_ON(!atomic_read(&bo->kref.refcount));
+ 
+-	ret = ttm_bo_reserve_nolru(bo, interruptible, no_wait, use_ticket,
+-				    ticket);
++	ret = __ttm_bo_reserve(bo, interruptible, no_wait, use_ticket, ticket);
+ 	if (likely(ret == 0))
+ 		ttm_bo_del_sub_from_lru(bo);
+ 
+@@ -927,20 +894,14 @@
+ }
+ 
+ /**
+- * ttm_bo_unreserve_ticket
++ * __ttm_bo_unreserve
+  * @bo: A pointer to a struct ttm_buffer_object.
+- * @ticket: ww_acquire_ctx used for reserving
+  *
+- * Unreserve a previous reservation of @bo made with @ticket.
++ * Unreserve a previous reservation of @bo where the buffer object is
++ * already on lru lists.
+  */
+-static inline void ttm_bo_unreserve_ticket(struct ttm_buffer_object *bo,
+-					   struct ww_acquire_ctx *t)
++static inline void __ttm_bo_unreserve(struct ttm_buffer_object *bo)
+ {
+-	if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
+-		spin_lock(&bo->glob->lru_lock);
+-		ttm_bo_add_to_lru(bo);
+-		spin_unlock(&bo->glob->lru_lock);
+-	}
+ 	ww_mutex_unlock(&bo->resv->lock);
+ }
+ 
+@@ -953,7 +914,25 @@
+  */
+ static inline void ttm_bo_unreserve(struct ttm_buffer_object *bo)
+ {
+-	ttm_bo_unreserve_ticket(bo, NULL);
++	if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
++		spin_lock(&bo->glob->lru_lock);
++		ttm_bo_add_to_lru(bo);
++		spin_unlock(&bo->glob->lru_lock);
++	}
++	__ttm_bo_unreserve(bo);
++}
++
++/**
++ * ttm_bo_unreserve_ticket
++ * @bo: A pointer to a struct ttm_buffer_object.
++ * @ticket: ww_acquire_ctx used for reserving
++ *
++ * Unreserve a previous reservation of @bo made with @ticket.
++ */
++static inline void ttm_bo_unreserve_ticket(struct ttm_buffer_object *bo,
++					   struct ww_acquire_ctx *t)
++{
++	ttm_bo_unreserve(bo);
+ }
+ 
+ /*
+@@ -1021,7 +1000,7 @@
+  * ttm_bo_move_accel_cleanup.
+  *
+  * @bo: A pointer to a struct ttm_buffer_object.
+- * @sync_obj: A sync object that signals when moving is complete.
++ * @fence: A fence object that signals when moving is complete.
+  * @evict: This is an evict move. Don't return until the buffer is idle.
+  * @no_wait_gpu: Return immediately if the GPU is busy.
+  * @new_mem: struct ttm_mem_reg indicating where to move.
+@@ -1035,7 +1014,7 @@
+  */
+ 
+ extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
+-				     void *sync_obj,
++				     struct fence *fence,
+ 				     bool evict, bool no_wait_gpu,
+ 				     struct ttm_mem_reg *new_mem);
+ /**
+diff -Naur a/include/drm/ttm/ttm_execbuf_util.h b/include/drm/ttm/ttm_execbuf_util.h
+--- a/include/drm/ttm/ttm_execbuf_util.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/ttm/ttm_execbuf_util.h	2015-03-26 14:42:38.758435422 +0530
+@@ -39,19 +39,13 @@
+  *
+  * @head:           list head for thread-private list.
+  * @bo:             refcounted buffer object pointer.
+- * @reserved:       Indicates whether @bo has been reserved for validation.
+- * @removed:        Indicates whether @bo has been removed from lru lists.
+- * @put_count:      Number of outstanding references on bo::list_kref.
+- * @old_sync_obj:   Pointer to a sync object about to be unreferenced
++ * @shared:         should the fence be added shared?
+  */
+ 
+ struct ttm_validate_buffer {
+ 	struct list_head head;
+ 	struct ttm_buffer_object *bo;
+-	bool reserved;
+-	bool removed;
+-	int put_count;
+-	void *old_sync_obj;
++	bool shared;
+ };
+ 
+ /**
+@@ -73,6 +67,8 @@
+  * @ticket:  [out] ww_acquire_ctx filled in by call, or NULL if only
+  *           non-blocking reserves should be tried.
+  * @list:    thread private list of ttm_validate_buffer structs.
++ * @intr:    should the wait be interruptible
++ * @dups:    [out] optional list of duplicates.
+  *
+  * Tries to reserve bos pointed to by the list entries for validation.
+  * If the function returns 0, all buffers are marked as "unfenced",
+@@ -84,9 +80,14 @@
+  * CPU write reservations to be cleared, and for other threads to
+  * unreserve their buffers.
+  *
+- * This function may return -ERESTART or -EAGAIN if the calling process
+- * receives a signal while waiting. In that case, no buffers on the list
+- * will be reserved upon return.
++ * If intr is set to true, this function may return -ERESTARTSYS if the
++ * calling process receives a signal while waiting. In that case, no
++ * buffers on the list will be reserved upon return.
++ *
++ * If dups is non NULL all buffers already reserved by the current thread
++ * (e.g. duplicates) are added to this list, otherwise -EALREADY is returned
++ * on the first already reserved buffer and all buffers from the list are
++ * unreserved again.
+  *
+  * Buffers reserved by this function should be unreserved by
+  * a call to either ttm_eu_backoff_reservation() or
+@@ -95,14 +96,15 @@
+  */
+ 
+ extern int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket,
+-				  struct list_head *list);
++				  struct list_head *list, bool intr,
++				  struct list_head *dups);
+ 
+ /**
+  * function ttm_eu_fence_buffer_objects.
+  *
+  * @ticket:      ww_acquire_ctx from reserve call
+  * @list:        thread private list of ttm_validate_buffer structs.
+- * @sync_obj:    The new sync object for the buffers.
++ * @fence:       The new exclusive fence for the buffers.
+  *
+  * This function should be called when command submission is complete, and
+  * it will add a new sync object to bos pointed to by entries on @list.
+@@ -111,6 +113,7 @@
+  */
+ 
+ extern void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket,
+-					struct list_head *list, void *sync_obj);
++					struct list_head *list,
++					struct fence *fence);
+ 
+ #endif
+diff -Naur a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h
+--- a/include/drm/ttm/ttm_placement.h	2015-03-26 14:43:27.890436386 +0530
++++ b/include/drm/ttm/ttm_placement.h	2015-03-26 14:42:38.758435422 +0530
+@@ -65,6 +65,8 @@
+  * reference the buffer.
+  * TTM_PL_FLAG_NO_EVICT means that the buffer may never
+  * be evicted to make room for other buffers.
++ * TTM_PL_FLAG_TOPDOWN requests to be placed from the
++ * top of the memory area, instead of the bottom.
+  */
+ 
+ #define TTM_PL_FLAG_CACHED      (1 << 16)
+@@ -72,6 +74,7 @@
+ #define TTM_PL_FLAG_WC          (1 << 18)
+ #define TTM_PL_FLAG_SHARED      (1 << 20)
+ #define TTM_PL_FLAG_NO_EVICT    (1 << 21)
++#define TTM_PL_FLAG_TOPDOWN     (1 << 22)
+ 
+ #define TTM_PL_MASK_CACHING     (TTM_PL_FLAG_CACHED | \
+ 				 TTM_PL_FLAG_UNCACHED | \
+diff -Naur a/include/linux/fence.h b/include/linux/fence.h
+--- a/include/linux/fence.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/linux/fence.h	2015-03-26 14:42:38.762435422 +0530
+@@ -0,0 +1,360 @@
++/*
++ * Fence mechanism for dma-buf to allow for asynchronous dma access
++ *
++ * Copyright (C) 2012 Canonical Ltd
++ * Copyright (C) 2012 Texas Instruments
++ *
++ * Authors:
++ * Rob Clark <robdclark@gmail.com>
++ * Maarten Lankhorst <maarten.lankhorst@canonical.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ */
++
++#ifndef __LINUX_FENCE_H
++#define __LINUX_FENCE_H
++
++#include <linux/err.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/bitops.h>
++#include <linux/kref.h>
++#include <linux/sched.h>
++#include <linux/printk.h>
++#include <linux/rcupdate.h>
++
++struct fence;
++struct fence_ops;
++struct fence_cb;
++
++/**
++ * struct fence - software synchronization primitive
++ * @refcount: refcount for this fence
++ * @ops: fence_ops associated with this fence
++ * @rcu: used for releasing fence with kfree_rcu
++ * @cb_list: list of all callbacks to call
++ * @lock: spin_lock_irqsave used for locking
++ * @context: execution context this fence belongs to, returned by
++ *           fence_context_alloc()
++ * @seqno: the sequence number of this fence inside the execution context,
++ * can be compared to decide which fence would be signaled later.
++ * @flags: A mask of FENCE_FLAG_* defined below
++ * @timestamp: Timestamp when the fence was signaled.
++ * @status: Optional, only valid if < 0, must be set before calling
++ * fence_signal, indicates that the fence has completed with an error.
++ *
++ * the flags member must be manipulated and read using the appropriate
++ * atomic ops (bit_*), so taking the spinlock will not be needed most
++ * of the time.
++ *
++ * FENCE_FLAG_SIGNALED_BIT - fence is already signaled
++ * FENCE_FLAG_ENABLE_SIGNAL_BIT - enable_signaling might have been called*
++ * FENCE_FLAG_USER_BITS - start of the unused bits, can be used by the
++ * implementer of the fence for its own purposes. Can be used in different
++ * ways by different fence implementers, so do not rely on this.
++ *
++ * *) Since atomic bitops are used, this is not guaranteed to be the case.
++ * Particularly, if the bit was set, but fence_signal was called right
++ * before this bit was set, it would have been able to set the
++ * FENCE_FLAG_SIGNALED_BIT, before enable_signaling was called.
++ * Adding a check for FENCE_FLAG_SIGNALED_BIT after setting
++ * FENCE_FLAG_ENABLE_SIGNAL_BIT closes this race, and makes sure that
++ * after fence_signal was called, any enable_signaling call will have either
++ * been completed, or never called at all.
++ */
++struct fence {
++	struct kref refcount;
++	const struct fence_ops *ops;
++	struct rcu_head rcu;
++	struct list_head cb_list;
++	spinlock_t *lock;
++	unsigned context, seqno;
++	unsigned long flags;
++	ktime_t timestamp;
++	int status;
++};
++
++enum fence_flag_bits {
++	FENCE_FLAG_SIGNALED_BIT,
++	FENCE_FLAG_ENABLE_SIGNAL_BIT,
++	FENCE_FLAG_USER_BITS, /* must always be last member */
++};
++
++typedef void (*fence_func_t)(struct fence *fence, struct fence_cb *cb);
++
++/**
++ * struct fence_cb - callback for fence_add_callback
++ * @node: used by fence_add_callback to append this struct to fence::cb_list
++ * @func: fence_func_t to call
++ *
++ * This struct will be initialized by fence_add_callback, additional
++ * data can be passed along by embedding fence_cb in another struct.
++ */
++struct fence_cb {
++	struct list_head node;
++	fence_func_t func;
++};
++
++/**
++ * struct fence_ops - operations implemented for fence
++ * @get_driver_name: returns the driver name.
++ * @get_timeline_name: return the name of the context this fence belongs to.
++ * @enable_signaling: enable software signaling of fence.
++ * @signaled: [optional] peek whether the fence is signaled, can be null.
++ * @wait: custom wait implementation, or fence_default_wait.
++ * @release: [optional] called on destruction of fence, can be null
++ * @fill_driver_data: [optional] callback to fill in free-form debug info
++ * Returns amount of bytes filled, or -errno.
++ * @fence_value_str: [optional] fills in the value of the fence as a string
++ * @timeline_value_str: [optional] fills in the current value of the timeline
++ * as a string
++ *
++ * Notes on enable_signaling:
++ * For fence implementations that have the capability for hw->hw
++ * signaling, they can implement this op to enable the necessary
++ * irqs, or insert commands into cmdstream, etc.  This is called
++ * in the first wait() or add_callback() path to let the fence
++ * implementation know that there is another driver waiting on
++ * the signal (ie. hw->sw case).
++ *
++ * This function can be called called from atomic context, but not
++ * from irq context, so normal spinlocks can be used.
++ *
++ * A return value of false indicates the fence already passed,
++ * or some failure occurred that made it impossible to enable
++ * signaling. True indicates successful enabling.
++ *
++ * fence->status may be set in enable_signaling, but only when false is
++ * returned.
++ *
++ * Calling fence_signal before enable_signaling is called allows
++ * for a tiny race window in which enable_signaling is called during,
++ * before, or after fence_signal. To fight this, it is recommended
++ * that before enable_signaling returns true an extra reference is
++ * taken on the fence, to be released when the fence is signaled.
++ * This will mean fence_signal will still be called twice, but
++ * the second time will be a noop since it was already signaled.
++ *
++ * Notes on signaled:
++ * May set fence->status if returning true.
++ *
++ * Notes on wait:
++ * Must not be NULL, set to fence_default_wait for default implementation.
++ * the fence_default_wait implementation should work for any fence, as long
++ * as enable_signaling works correctly.
++ *
++ * Must return -ERESTARTSYS if the wait is intr = true and the wait was
++ * interrupted, and remaining jiffies if fence has signaled, or 0 if wait
++ * timed out. Can also return other error values on custom implementations,
++ * which should be treated as if the fence is signaled. For example a hardware
++ * lockup could be reported like that.
++ *
++ * Notes on release:
++ * Can be NULL, this function allows additional commands to run on
++ * destruction of the fence. Can be called from irq context.
++ * If pointer is set to NULL, kfree will get called instead.
++ */
++
++struct fence_ops {
++	const char * (*get_driver_name)(struct fence *fence);
++	const char * (*get_timeline_name)(struct fence *fence);
++	bool (*enable_signaling)(struct fence *fence);
++	bool (*signaled)(struct fence *fence);
++	signed long (*wait)(struct fence *fence, bool intr, signed long timeout);
++	void (*release)(struct fence *fence);
++
++	int (*fill_driver_data)(struct fence *fence, void *data, int size);
++	void (*fence_value_str)(struct fence *fence, char *str, int size);
++	void (*timeline_value_str)(struct fence *fence, char *str, int size);
++};
++
++void fence_init(struct fence *fence, const struct fence_ops *ops,
++		spinlock_t *lock, unsigned context, unsigned seqno);
++
++void fence_release(struct kref *kref);
++void fence_free(struct fence *fence);
++
++/**
++ * fence_get - increases refcount of the fence
++ * @fence:	[in]	fence to increase refcount of
++ *
++ * Returns the same fence, with refcount increased by 1.
++ */
++static inline struct fence *fence_get(struct fence *fence)
++{
++	if (fence)
++		kref_get(&fence->refcount);
++	return fence;
++}
++
++/**
++ * fence_get_rcu - get a fence from a reservation_object_list with rcu read lock
++ * @fence:	[in]	fence to increase refcount of
++ *
++ * Function returns NULL if no refcount could be obtained, or the fence.
++ */
++static inline struct fence *fence_get_rcu(struct fence *fence)
++{
++	if (kref_get_unless_zero(&fence->refcount))
++		return fence;
++	else
++		return NULL;
++}
++
++/**
++ * fence_put - decreases refcount of the fence
++ * @fence:	[in]	fence to reduce refcount of
++ */
++static inline void fence_put(struct fence *fence)
++{
++	if (fence)
++		kref_put(&fence->refcount, fence_release);
++}
++
++int fence_signal(struct fence *fence);
++int fence_signal_locked(struct fence *fence);
++signed long fence_default_wait(struct fence *fence, bool intr, signed long timeout);
++int fence_add_callback(struct fence *fence, struct fence_cb *cb,
++		       fence_func_t func);
++bool fence_remove_callback(struct fence *fence, struct fence_cb *cb);
++void fence_enable_sw_signaling(struct fence *fence);
++
++/**
++ * fence_is_signaled_locked - Return an indication if the fence is signaled yet.
++ * @fence:	[in]	the fence to check
++ *
++ * Returns true if the fence was already signaled, false if not. Since this
++ * function doesn't enable signaling, it is not guaranteed to ever return
++ * true if fence_add_callback, fence_wait or fence_enable_sw_signaling
++ * haven't been called before.
++ *
++ * This function requires fence->lock to be held.
++ */
++static inline bool
++fence_is_signaled_locked(struct fence *fence)
++{
++	if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
++		return true;
++
++	if (fence->ops->signaled && fence->ops->signaled(fence)) {
++		fence_signal_locked(fence);
++		return true;
++	}
++
++	return false;
++}
++
++/**
++ * fence_is_signaled - Return an indication if the fence is signaled yet.
++ * @fence:	[in]	the fence to check
++ *
++ * Returns true if the fence was already signaled, false if not. Since this
++ * function doesn't enable signaling, it is not guaranteed to ever return
++ * true if fence_add_callback, fence_wait or fence_enable_sw_signaling
++ * haven't been called before.
++ *
++ * It's recommended for seqno fences to call fence_signal when the
++ * operation is complete, it makes it possible to prevent issues from
++ * wraparound between time of issue and time of use by checking the return
++ * value of this function before calling hardware-specific wait instructions.
++ */
++static inline bool
++fence_is_signaled(struct fence *fence)
++{
++	if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
++		return true;
++
++	if (fence->ops->signaled && fence->ops->signaled(fence)) {
++		fence_signal(fence);
++		return true;
++	}
++
++	return false;
++}
++
++/**
++ * fence_later - return the chronologically later fence
++ * @f1:	[in]	the first fence from the same context
++ * @f2:	[in]	the second fence from the same context
++ *
++ * Returns NULL if both fences are signaled, otherwise the fence that would be
++ * signaled last. Both fences must be from the same context, since a seqno is
++ * not re-used across contexts.
++ */
++static inline struct fence *fence_later(struct fence *f1, struct fence *f2)
++{
++	if (WARN_ON(f1->context != f2->context))
++		return NULL;
++
++	/*
++	 * can't check just FENCE_FLAG_SIGNALED_BIT here, it may never have been
++	 * set if enable_signaling wasn't called, and enabling that here is
++	 * overkill.
++	 */
++	if (f2->seqno - f1->seqno <= INT_MAX)
++		return fence_is_signaled(f2) ? NULL : f2;
++	else
++		return fence_is_signaled(f1) ? NULL : f1;
++}
++
++signed long fence_wait_timeout(struct fence *, bool intr, signed long timeout);
++
++
++/**
++ * fence_wait - sleep until the fence gets signaled
++ * @fence:	[in]	the fence to wait on
++ * @intr:	[in]	if true, do an interruptible wait
++ *
++ * This function will return -ERESTARTSYS if interrupted by a signal,
++ * or 0 if the fence was signaled. Other error values may be
++ * returned on custom implementations.
++ *
++ * Performs a synchronous wait on this fence. It is assumed the caller
++ * directly or indirectly holds a reference to the fence, otherwise the
++ * fence might be freed before return, resulting in undefined behavior.
++ */
++static inline signed long fence_wait(struct fence *fence, bool intr)
++{
++	signed long ret;
++
++	/* Since fence_wait_timeout cannot timeout with
++	 * MAX_SCHEDULE_TIMEOUT, only valid return values are
++	 * -ERESTARTSYS and MAX_SCHEDULE_TIMEOUT.
++	 */
++	ret = fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
++
++	return ret < 0 ? ret : 0;
++}
++
++unsigned fence_context_alloc(unsigned num);
++
++#define FENCE_TRACE(f, fmt, args...) \
++	do {								\
++		struct fence *__ff = (f);				\
++		if (config_enabled(CONFIG_FENCE_TRACE))			\
++			pr_info("f %u#%u: " fmt,			\
++				__ff->context, __ff->seqno, ##args);	\
++	} while (0)
++
++#define FENCE_WARN(f, fmt, args...) \
++	do {								\
++		struct fence *__ff = (f);				\
++		pr_warn("f %u#%u: " fmt, __ff->context, __ff->seqno,	\
++			 ##args);					\
++	} while (0)
++
++#define FENCE_ERR(f, fmt, args...) \
++	do {								\
++		struct fence *__ff = (f);				\
++		pr_err("f %u#%u: " fmt, __ff->context, __ff->seqno,	\
++			##args);					\
++	} while (0)
++
++#endif /* __LINUX_FENCE_H */
+diff -Naur a/include/linux/ktime.h b/include/linux/ktime.h
+--- a/include/linux/ktime.h	2015-03-26 14:43:27.914436386 +0530
++++ b/include/linux/ktime.h	2015-03-26 14:42:38.762435422 +0530
+@@ -386,4 +386,6 @@
+ 	return ktime_add_ms(ktime_zero, ms);
+ }
+ 
++# include <linux/timekeeping.h>
++
+ #endif
+diff -Naur a/include/linux/moduleparam.h b/include/linux/moduleparam.h
+--- a/include/linux/moduleparam.h	2015-03-26 14:43:27.942436387 +0530
++++ b/include/linux/moduleparam.h	2015-03-26 14:42:38.762435422 +0530
+@@ -111,6 +111,11 @@
+  */
+ #define module_param(name, type, perm)				\
+ 	module_param_named(name, name, type, perm)
++/**
++ * module_param_unsafe - same as module_param but taints kernel
++ */
++#define module_param_unsafe(name, type, perm)                  \
++	module_param_named_unsafe(name, name, type, perm)
+ 
+ /**
+  * module_param_named - typesafe helper for a renamed module/cmdline parameter
+@@ -129,6 +134,14 @@
+ 	__MODULE_PARM_TYPE(name, #type)
+ 
+ /**
++ * module_param_named_unsafe - same as module_param_named but taints kernel
++ */
++#define module_param_named_unsafe(name, value, type, perm)             \
++	param_check_##type(name, &(value));                             \
++	module_param_cb_unsafe(name, &param_ops_##type, &value, perm);  \
++	__MODULE_PARM_TYPE(name, #type)
++
++/**
+  * module_param_cb - general callback for a module/cmdline parameter
+  * @name: a valid C identifier which is the parameter name.
+  * @ops: the set & get operations for this parameter.
+@@ -139,6 +152,8 @@
+ #define module_param_cb(name, ops, arg, perm)				      \
+ 	__module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1)
+ 
++#define module_param_cb_unsafe(name, ops, arg, perm)                         \
++	__module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1)
+ /**
+  * <level>_param_cb - general callback for a module/cmdline parameter
+  *                    to be evaluated before certain initcall level
+diff -Naur a/include/linux/pci.h b/include/linux/pci.h
+--- a/include/linux/pci.h	2015-03-26 14:43:27.938436387 +0530
++++ b/include/linux/pci.h	2015-03-26 14:42:38.762435422 +0530
+@@ -297,6 +297,7 @@
+ 						   D3cold, not set for devices
+ 						   powered on/off by the
+ 						   corresponding bridge */
++	unsigned int	ignore_hotplug:1;	/* Ignore hotplug events */
+ 	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
+ 	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
+ 
+@@ -997,6 +998,11 @@
+ bool pci_check_pme_status(struct pci_dev *dev);
+ void pci_pme_wakeup_bus(struct pci_bus *bus);
+ 
++static inline void pci_ignore_hotplug(struct pci_dev *dev)
++{
++	dev->ignore_hotplug = 1;
++}
++
+ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
+ 				  bool enable)
+ {
+diff -Naur a/include/linux/reservation.h b/include/linux/reservation.h
+--- a/include/linux/reservation.h	2015-03-26 14:43:27.946436387 +0530
++++ b/include/linux/reservation.h	2015-03-26 14:42:38.762435422 +0530
+@@ -6,7 +6,7 @@
+  * Copyright (C) 2012 Texas Instruments
+  *
+  * Authors:
+- * Rob Clark <rob.clark@linaro.org>
++ * Rob Clark <robdclark@gmail.com>
+  * Maarten Lankhorst <maarten.lankhorst@canonical.com>
+  * Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+  *
+@@ -40,23 +40,103 @@
+ #define _LINUX_RESERVATION_H
+ 
+ #include <linux/ww_mutex.h>
++#include <linux/fence.h>
++#include <linux/slab.h>
++#include <linux/seqlock.h>
++#include <linux/rcupdate.h>
+ 
+ extern struct ww_class reservation_ww_class;
++extern struct lock_class_key reservation_seqcount_class;
++extern const char reservation_seqcount_string[];
++
++struct reservation_object_list {
++	struct rcu_head rcu;
++	u32 shared_count, shared_max;
++	struct fence __rcu *shared[];
++};
+ 
+ struct reservation_object {
+ 	struct ww_mutex lock;
++	seqcount_t seq;
++
++	struct fence __rcu *fence_excl;
++	struct reservation_object_list __rcu *fence;
++	struct reservation_object_list *staged;
+ };
+ 
++#define reservation_object_held(obj) lockdep_is_held(&(obj)->lock.base)
++#define reservation_object_assert_held(obj) \
++	lockdep_assert_held(&(obj)->lock.base)
++
+ static inline void
+ reservation_object_init(struct reservation_object *obj)
+ {
+ 	ww_mutex_init(&obj->lock, &reservation_ww_class);
++
++	__seqcount_init(&obj->seq, reservation_seqcount_string, &reservation_seqcount_class);
++	RCU_INIT_POINTER(obj->fence, NULL);
++	RCU_INIT_POINTER(obj->fence_excl, NULL);
++	obj->staged = NULL;
+ }
+ 
+ static inline void
+ reservation_object_fini(struct reservation_object *obj)
+ {
++	int i;
++	struct reservation_object_list *fobj;
++	struct fence *excl;
++
++	/*
++	 * This object should be dead and all references must have
++	 * been released to it, so no need to be protected with rcu.
++	 */
++	excl = rcu_dereference_protected(obj->fence_excl, 1);
++	if (excl)
++		fence_put(excl);
++
++	fobj = rcu_dereference_protected(obj->fence, 1);
++	if (fobj) {
++		for (i = 0; i < fobj->shared_count; ++i)
++			fence_put(rcu_dereference_protected(fobj->shared[i], 1));
++
++		kfree(fobj);
++	}
++	kfree(obj->staged);
++
+ 	ww_mutex_destroy(&obj->lock);
+ }
+ 
++static inline struct reservation_object_list *
++reservation_object_get_list(struct reservation_object *obj)
++{
++	return rcu_dereference_protected(obj->fence,
++					 reservation_object_held(obj));
++}
++
++static inline struct fence *
++reservation_object_get_excl(struct reservation_object *obj)
++{
++	return rcu_dereference_protected(obj->fence_excl,
++					 reservation_object_held(obj));
++}
++
++int reservation_object_reserve_shared(struct reservation_object *obj);
++void reservation_object_add_shared_fence(struct reservation_object *obj,
++					 struct fence *fence);
++
++void reservation_object_add_excl_fence(struct reservation_object *obj,
++				       struct fence *fence);
++
++int reservation_object_get_fences_rcu(struct reservation_object *obj,
++				      struct fence **pfence_excl,
++				      unsigned *pshared_count,
++				      struct fence ***pshared);
++
++long reservation_object_wait_timeout_rcu(struct reservation_object *obj,
++					 bool wait_all, bool intr,
++					 unsigned long timeout);
++
++bool reservation_object_test_signaled_rcu(struct reservation_object *obj,
++					  bool test_all);
++
+ #endif /* _LINUX_RESERVATION_H */
+diff -Naur a/include/linux/seqno-fence.h b/include/linux/seqno-fence.h
+--- a/include/linux/seqno-fence.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/linux/seqno-fence.h	2015-03-26 14:42:38.762435422 +0530
+@@ -0,0 +1,117 @@
++/*
++ * seqno-fence, using a dma-buf to synchronize fencing
++ *
++ * Copyright (C) 2012 Texas Instruments
++ * Copyright (C) 2012 Canonical Ltd
++ * Authors:
++ *   Rob Clark <robdclark@gmail.com>
++ *   Maarten Lankhorst <maarten.lankhorst@canonical.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ */
++
++#ifndef __LINUX_SEQNO_FENCE_H
++#define __LINUX_SEQNO_FENCE_H
++
++#include <linux/fence.h>
++#include <linux/dma-buf.h>
++
++enum seqno_fence_condition {
++	SEQNO_FENCE_WAIT_GEQUAL,
++	SEQNO_FENCE_WAIT_NONZERO
++};
++
++struct seqno_fence {
++	struct fence base;
++
++	const struct fence_ops *ops;
++	struct dma_buf *sync_buf;
++	uint32_t seqno_ofs;
++	enum seqno_fence_condition condition;
++};
++
++extern const struct fence_ops seqno_fence_ops;
++
++/**
++ * to_seqno_fence - cast a fence to a seqno_fence
++ * @fence: fence to cast to a seqno_fence
++ *
++ * Returns NULL if the fence is not a seqno_fence,
++ * or the seqno_fence otherwise.
++ */
++static inline struct seqno_fence *
++to_seqno_fence(struct fence *fence)
++{
++	if (fence->ops != &seqno_fence_ops)
++		return NULL;
++	return container_of(fence, struct seqno_fence, base);
++}
++
++/**
++ * seqno_fence_init - initialize a seqno fence
++ * @fence: seqno_fence to initialize
++ * @lock: pointer to spinlock to use for fence
++ * @sync_buf: buffer containing the memory location to signal on
++ * @context: the execution context this fence is a part of
++ * @seqno_ofs: the offset within @sync_buf
++ * @seqno: the sequence # to signal on
++ * @cond: fence wait condition
++ * @ops: the fence_ops for operations on this seqno fence
++ *
++ * This function initializes a struct seqno_fence with passed parameters,
++ * and takes a reference on sync_buf which is released on fence destruction.
++ *
++ * A seqno_fence is a dma_fence which can complete in software when
++ * enable_signaling is called, but it also completes when
++ * (s32)((sync_buf)[seqno_ofs] - seqno) >= 0 is true
++ *
++ * The seqno_fence will take a refcount on the sync_buf until it's
++ * destroyed, but actual lifetime of sync_buf may be longer if one of the
++ * callers take a reference to it.
++ *
++ * Certain hardware have instructions to insert this type of wait condition
++ * in the command stream, so no intervention from software would be needed.
++ * This type of fence can be destroyed before completed, however a reference
++ * on the sync_buf dma-buf can be taken. It is encouraged to re-use the same
++ * dma-buf for sync_buf, since mapping or unmapping the sync_buf to the
++ * device's vm can be expensive.
++ *
++ * It is recommended for creators of seqno_fence to call fence_signal
++ * before destruction. This will prevent possible issues from wraparound at
++ * time of issue vs time of check, since users can check fence_is_signaled
++ * before submitting instructions for the hardware to wait on the fence.
++ * However, when ops.enable_signaling is not called, it doesn't have to be
++ * done as soon as possible, just before there's any real danger of seqno
++ * wraparound.
++ */
++static inline void
++seqno_fence_init(struct seqno_fence *fence, spinlock_t *lock,
++		 struct dma_buf *sync_buf,  uint32_t context,
++		 uint32_t seqno_ofs, uint32_t seqno,
++		 enum seqno_fence_condition cond,
++		 const struct fence_ops *ops)
++{
++	BUG_ON(!fence || !sync_buf || !ops);
++	BUG_ON(!ops->wait || !ops->enable_signaling ||
++	       !ops->get_driver_name || !ops->get_timeline_name);
++
++	/*
++	 * ops is used in fence_init for get_driver_name, so needs to be
++	 * initialized first
++	 */
++	fence->ops = ops;
++	fence_init(&fence->base, &seqno_fence_ops, lock, context, seqno);
++	get_dma_buf(sync_buf);
++	fence->sync_buf = sync_buf;
++	fence->seqno_ofs = seqno_ofs;
++	fence->condition = cond;
++}
++
++#endif /* __LINUX_SEQNO_FENCE_H */
+diff -Naur a/include/linux/time64.h b/include/linux/time64.h
+--- a/include/linux/time64.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/linux/time64.h	2015-03-26 14:42:38.762435422 +0530
+@@ -0,0 +1,190 @@
++#ifndef _LINUX_TIME64_H
++#define _LINUX_TIME64_H
++
++#include <uapi/linux/time.h>
++
++typedef __s64 time64_t;
++
++/*
++ * This wants to go into uapi/linux/time.h once we agreed about the
++ * userspace interfaces.
++ */
++#if __BITS_PER_LONG == 64
++# define timespec64 timespec
++#else
++struct timespec64 {
++	time64_t	tv_sec;			/* seconds */
++	long		tv_nsec;		/* nanoseconds */
++};
++#endif
++
++/* Parameters used to convert the timespec values: */
++#define MSEC_PER_SEC	1000L
++#define USEC_PER_MSEC	1000L
++#define NSEC_PER_USEC	1000L
++#define NSEC_PER_MSEC	1000000L
++#define USEC_PER_SEC	1000000L
++#define NSEC_PER_SEC	1000000000L
++#define FSEC_PER_SEC	1000000000000000LL
++
++/* Located here for timespec[64]_valid_strict */
++#define KTIME_MAX			((s64)~((u64)1 << 63))
++#define KTIME_SEC_MAX			(KTIME_MAX / NSEC_PER_SEC)
++
++#if __BITS_PER_LONG == 64
++
++static inline struct timespec timespec64_to_timespec(const struct timespec64 ts64)
++{
++	return ts64;
++}
++
++static inline struct timespec64 timespec_to_timespec64(const struct timespec ts)
++{
++	return ts;
++}
++
++# define timespec64_equal		timespec_equal
++# define timespec64_compare		timespec_compare
++# define set_normalized_timespec64	set_normalized_timespec
++# define timespec64_add_safe		timespec_add_safe
++# define timespec64_add			timespec_add
++# define timespec64_sub			timespec_sub
++# define timespec64_valid		timespec_valid
++# define timespec64_valid_strict	timespec_valid_strict
++# define timespec64_to_ns		timespec_to_ns
++# define ns_to_timespec64		ns_to_timespec
++# define timespec64_add_ns		timespec_add_ns
++
++#else
++
++static inline struct timespec timespec64_to_timespec(const struct timespec64 ts64)
++{
++	struct timespec ret;
++
++	ret.tv_sec = (time_t)ts64.tv_sec;
++	ret.tv_nsec = ts64.tv_nsec;
++	return ret;
++}
++
++static inline struct timespec64 timespec_to_timespec64(const struct timespec ts)
++{
++	struct timespec64 ret;
++
++	ret.tv_sec = ts.tv_sec;
++	ret.tv_nsec = ts.tv_nsec;
++	return ret;
++}
++
++static inline int timespec64_equal(const struct timespec64 *a,
++				   const struct timespec64 *b)
++{
++	return (a->tv_sec == b->tv_sec) && (a->tv_nsec == b->tv_nsec);
++}
++
++/*
++ * lhs < rhs:  return <0
++ * lhs == rhs: return 0
++ * lhs > rhs:  return >0
++ */
++static inline int timespec64_compare(const struct timespec64 *lhs, const struct timespec64 *rhs)
++{
++	if (lhs->tv_sec < rhs->tv_sec)
++		return -1;
++	if (lhs->tv_sec > rhs->tv_sec)
++		return 1;
++	return lhs->tv_nsec - rhs->tv_nsec;
++}
++
++extern void set_normalized_timespec64(struct timespec64 *ts, time64_t sec, s64 nsec);
++
++/*
++ * timespec64_add_safe assumes both values are positive and checks for
++ * overflow. It will return TIME_T_MAX if the returned value would be
++ * smaller then either of the arguments.
++ */
++extern struct timespec64 timespec64_add_safe(const struct timespec64 lhs,
++					 const struct timespec64 rhs);
++
++
++static inline struct timespec64 timespec64_add(struct timespec64 lhs,
++						struct timespec64 rhs)
++{
++	struct timespec64 ts_delta;
++	set_normalized_timespec64(&ts_delta, lhs.tv_sec + rhs.tv_sec,
++				lhs.tv_nsec + rhs.tv_nsec);
++	return ts_delta;
++}
++
++/*
++ * sub = lhs - rhs, in normalized form
++ */
++static inline struct timespec64 timespec64_sub(struct timespec64 lhs,
++						struct timespec64 rhs)
++{
++	struct timespec64 ts_delta;
++	set_normalized_timespec64(&ts_delta, lhs.tv_sec - rhs.tv_sec,
++				lhs.tv_nsec - rhs.tv_nsec);
++	return ts_delta;
++}
++
++/*
++ * Returns true if the timespec64 is norm, false if denorm:
++ */
++static inline bool timespec64_valid(const struct timespec64 *ts)
++{
++	/* Dates before 1970 are bogus */
++	if (ts->tv_sec < 0)
++		return false;
++	/* Can't have more nanoseconds then a second */
++	if ((unsigned long)ts->tv_nsec >= NSEC_PER_SEC)
++		return false;
++	return true;
++}
++
++static inline bool timespec64_valid_strict(const struct timespec64 *ts)
++{
++	if (!timespec64_valid(ts))
++		return false;
++	/* Disallow values that could overflow ktime_t */
++	if ((unsigned long long)ts->tv_sec >= KTIME_SEC_MAX)
++		return false;
++	return true;
++}
++
++/**
++ * timespec64_to_ns - Convert timespec64 to nanoseconds
++ * @ts:		pointer to the timespec64 variable to be converted
++ *
++ * Returns the scalar nanosecond representation of the timespec64
++ * parameter.
++ */
++static inline s64 timespec64_to_ns(const struct timespec64 *ts)
++{
++	return ((s64) ts->tv_sec * NSEC_PER_SEC) + ts->tv_nsec;
++}
++
++/**
++ * ns_to_timespec64 - Convert nanoseconds to timespec64
++ * @nsec:	the nanoseconds value to be converted
++ *
++ * Returns the timespec64 representation of the nsec parameter.
++ */
++extern struct timespec64 ns_to_timespec64(const s64 nsec);
++
++/**
++ * timespec64_add_ns - Adds nanoseconds to a timespec64
++ * @a:		pointer to timespec64 to be incremented
++ * @ns:		unsigned nanoseconds value to be added
++ *
++ * This must always be inlined because its used from the x86-64 vdso,
++ * which cannot call other kernel functions.
++ */
++static __always_inline void timespec64_add_ns(struct timespec64 *a, u64 ns)
++{
++	a->tv_sec += __iter_div_u64_rem(a->tv_nsec + ns, NSEC_PER_SEC, &ns);
++	a->tv_nsec = ns;
++}
++
++#endif
++
++#endif /* _LINUX_TIME64_H */
+diff -Naur a/include/linux/timekeeping_bkp.h b/include/linux/timekeeping_bkp.h
+--- a/include/linux/timekeeping_bkp.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/linux/timekeeping_bkp.h	2015-03-26 14:42:38.762435422 +0530
+@@ -0,0 +1,252 @@
++#ifndef _LINUX_TIMEKEEPING_H
++#define _LINUX_TIMEKEEPING_H
++
++/* Included from linux/ktime.h */
++
++void timekeeping_init(void);
++extern int timekeeping_suspended;
++
++/*
++ * Get and set timeofday
++ */
++extern void do_gettimeofday(struct timeval *tv);
++extern int do_settimeofday64(const struct timespec64 *ts);
++extern int do_sys_settimeofday(const struct timespec *tv,
++			       const struct timezone *tz);
++
++/*
++ * Kernel time accessors
++ */
++unsigned long get_seconds(void);
++struct timespec current_kernel_time(void);
++/* does not take xtime_lock */
++struct timespec __current_kernel_time(void);
++
++/*
++ * timespec based interfaces
++ */
++struct timespec64 get_monotonic_coarse64(void);
++extern void getrawmonotonic64(struct timespec64 *ts);
++extern void ktime_get_ts64(struct timespec64 *ts);
++extern time64_t ktime_get_seconds(void);
++extern time64_t ktime_get_real_seconds(void);
++
++extern int __getnstimeofday64(struct timespec64 *tv);
++extern void getnstimeofday64(struct timespec64 *tv);
++
++#if BITS_PER_LONG == 64
++/**
++ * Deprecated. Use do_settimeofday64().
++ */
++static inline int do_settimeofday(const struct timespec *ts)
++{
++	return do_settimeofday64(ts);
++}
++
++static inline int __getnstimeofday(struct timespec *ts)
++{
++	return __getnstimeofday64(ts);
++}
++
++static inline void getnstimeofday(struct timespec *ts)
++{
++	getnstimeofday64(ts);
++}
++
++static inline void ktime_get_ts(struct timespec *ts)
++{
++	ktime_get_ts64(ts);
++}
++
++static inline void ktime_get_real_ts(struct timespec *ts)
++{
++	getnstimeofday64(ts);
++}
++
++static inline void getrawmonotonic(struct timespec *ts)
++{
++	getrawmonotonic64(ts);
++}
++
++static inline struct timespec get_monotonic_coarse(void)
++{
++	return get_monotonic_coarse64();
++}
++#else
++/**
++ * Deprecated. Use do_settimeofday64().
++ */
++static inline int do_settimeofday(const struct timespec *ts)
++{
++	struct timespec64 ts64;
++
++	ts64 = timespec_to_timespec64(*ts);
++	return do_settimeofday64(&ts64);
++}
++
++static inline int __getnstimeofday(struct timespec *ts)
++{
++	struct timespec64 ts64;
++	int ret = __getnstimeofday64(&ts64);
++
++	*ts = timespec64_to_timespec(ts64);
++	return ret;
++}
++
++static inline void getnstimeofday(struct timespec *ts)
++{
++	struct timespec64 ts64;
++
++	getnstimeofday64(&ts64);
++	*ts = timespec64_to_timespec(ts64);
++}
++
++static inline void ktime_get_ts(struct timespec *ts)
++{
++	struct timespec64 ts64;
++
++	ktime_get_ts64(&ts64);
++	*ts = timespec64_to_timespec(ts64);
++}
++
++static inline void ktime_get_real_ts(struct timespec *ts)
++{
++	struct timespec64 ts64;
++
++	getnstimeofday64(&ts64);
++	*ts = timespec64_to_timespec(ts64);
++}
++
++static inline void getrawmonotonic(struct timespec *ts)
++{
++	struct timespec64 ts64;
++
++	getrawmonotonic64(&ts64);
++	*ts = timespec64_to_timespec(ts64);
++}
++
++static inline struct timespec get_monotonic_coarse(void)
++{
++	return timespec64_to_timespec(get_monotonic_coarse64());
++}
++#endif
++
++extern void getboottime(struct timespec *ts);
++
++#define do_posix_clock_monotonic_gettime(ts) ktime_get_ts(ts)
++#define ktime_get_real_ts64(ts)	getnstimeofday64(ts)
++
++/*
++ * ktime_t based interfaces
++ */
++
++enum tk_offsets {
++	TK_OFFS_REAL,
++	TK_OFFS_BOOT,
++	TK_OFFS_TAI,
++	TK_OFFS_MAX,
++};
++
++extern ktime_t ktime_get(void);
++extern ktime_t ktime_get_with_offset(enum tk_offsets offs);
++extern ktime_t ktime_mono_to_any(ktime_t tmono, enum tk_offsets offs);
++extern ktime_t ktime_get_raw(void);
++
++/**
++ * ktime_get_real - get the real (wall-) time in ktime_t format
++ */
++static inline ktime_t ktime_get_real(void)
++{
++	return ktime_get_with_offset(TK_OFFS_REAL);
++}
++
++/**
++ * ktime_get_boottime - Returns monotonic time since boot in ktime_t format
++ *
++ * This is similar to CLOCK_MONTONIC/ktime_get, but also includes the
++ * time spent in suspend.
++ */
++static inline ktime_t ktime_get_boottime(void)
++{
++	return ktime_get_with_offset(TK_OFFS_BOOT);
++}
++
++/**
++ * ktime_get_clocktai - Returns the TAI time of day in ktime_t format
++ */
++static inline ktime_t ktime_get_clocktai(void)
++{
++	return ktime_get_with_offset(TK_OFFS_TAI);
++}
++
++/**
++ * ktime_mono_to_real - Convert monotonic time to clock realtime
++ */
++static inline ktime_t ktime_mono_to_real(ktime_t mono)
++{
++	return ktime_mono_to_any(mono, TK_OFFS_REAL);
++}
++
++static inline u64 ktime_get_ns(void)
++{
++	return ktime_to_ns(ktime_get());
++}
++
++static inline u64 ktime_get_real_ns(void)
++{
++	return ktime_to_ns(ktime_get_real());
++}
++
++static inline u64 ktime_get_boot_ns(void)
++{
++	return ktime_to_ns(ktime_get_boottime());
++}
++
++static inline u64 ktime_get_raw_ns(void)
++{
++	return ktime_to_ns(ktime_get_raw());
++}
++
++extern u64 ktime_get_mono_fast_ns(void);
++
++/*
++ * Timespec interfaces utilizing the ktime based ones
++ */
++static inline void get_monotonic_boottime(struct timespec *ts)
++{
++	*ts = ktime_to_timespec(ktime_get_boottime());
++}
++
++static inline void timekeeping_clocktai(struct timespec *ts)
++{
++	*ts = ktime_to_timespec(ktime_get_clocktai());
++}
++
++/*
++ * RTC specific
++ */
++extern void timekeeping_inject_sleeptime64(struct timespec64 *delta);
++
++/*
++ * PPS accessor
++ */
++extern void getnstime_raw_and_real(struct timespec *ts_raw,
++				   struct timespec *ts_real);
++
++/*
++ * Persistent clock related interfaces
++ */
++extern bool persistent_clock_exist;
++extern int persistent_clock_is_local;
++
++static inline bool has_persistent_clock(void)
++{
++	return persistent_clock_exist;
++}
++
++extern void read_persistent_clock(struct timespec *ts);
++extern void read_boot_clock(struct timespec *ts);
++extern int update_persistent_clock(struct timespec now);
++
++
++#endif
+diff -Naur a/include/linux/timekeeping.h b/include/linux/timekeeping.h
+--- a/include/linux/timekeeping.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/linux/timekeeping.h	2015-03-26 14:42:38.762435422 +0530
+@@ -0,0 +1,34 @@
++#ifndef _LINUX_TIMEKEEPING_H
++#define _LINUX_TIMEKEEPING_H
++
++/*
++ * ktime_t based interfaces
++ */
++
++enum tk_offsets {
++	TK_OFFS_REAL,
++	TK_OFFS_BOOT,
++	TK_OFFS_TAI,
++	TK_OFFS_MAX,
++};
++
++
++
++
++extern ktime_t ktime_get_raw(void);
++extern ktime_t ktime_mono_to_any(ktime_t tmono, enum tk_offsets offs);
++
++
++static inline ktime_t ktime_mono_to_real(ktime_t mono)
++{
++	return ktime_mono_to_any(mono, TK_OFFS_REAL);
++}
++
++
++static inline u64 ktime_get_raw_ns(void)
++{
++	return ktime_to_ns(ktime_get_raw());
++}
++
++
++#endif
+diff -Naur a/include/trace/events/fence.h b/include/trace/events/fence.h
+--- a/include/trace/events/fence.h	1970-01-01 05:30:00.000000000 +0530
++++ b/include/trace/events/fence.h	2015-03-26 14:42:38.762435422 +0530
+@@ -0,0 +1,128 @@
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM fence
++
++#if !defined(_TRACE_FENCE_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_FENCE_H
++
++#include <linux/tracepoint.h>
++
++struct fence;
++
++TRACE_EVENT(fence_annotate_wait_on,
++
++	/* fence: the fence waiting on f1, f1: the fence to be waited on. */
++	TP_PROTO(struct fence *fence, struct fence *f1),
++
++	TP_ARGS(fence, f1),
++
++	TP_STRUCT__entry(
++		__string(driver, fence->ops->get_driver_name(fence))
++		__string(timeline, fence->ops->get_driver_name(fence))
++		__field(unsigned int, context)
++		__field(unsigned int, seqno)
++
++		__string(waiting_driver, f1->ops->get_driver_name(f1))
++		__string(waiting_timeline, f1->ops->get_timeline_name(f1))
++		__field(unsigned int, waiting_context)
++		__field(unsigned int, waiting_seqno)
++	),
++
++	TP_fast_assign(
++		__assign_str(driver, fence->ops->get_driver_name(fence))
++		__assign_str(timeline, fence->ops->get_timeline_name(fence))
++		__entry->context = fence->context;
++		__entry->seqno = fence->seqno;
++
++		__assign_str(waiting_driver, f1->ops->get_driver_name(f1))
++		__assign_str(waiting_timeline, f1->ops->get_timeline_name(f1))
++		__entry->waiting_context = f1->context;
++		__entry->waiting_seqno = f1->seqno;
++
++	),
++
++	TP_printk("driver=%s timeline=%s context=%u seqno=%u "	\
++		  "waits on driver=%s timeline=%s context=%u seqno=%u",
++		  __get_str(driver), __get_str(timeline), __entry->context,
++		  __entry->seqno,
++		  __get_str(waiting_driver), __get_str(waiting_timeline),
++		  __entry->waiting_context, __entry->waiting_seqno)
++);
++
++DECLARE_EVENT_CLASS(fence,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence),
++
++	TP_STRUCT__entry(
++		__string(driver, fence->ops->get_driver_name(fence))
++		__string(timeline, fence->ops->get_timeline_name(fence))
++		__field(unsigned int, context)
++		__field(unsigned int, seqno)
++	),
++
++	TP_fast_assign(
++		__assign_str(driver, fence->ops->get_driver_name(fence))
++		__assign_str(timeline, fence->ops->get_timeline_name(fence))
++		__entry->context = fence->context;
++		__entry->seqno = fence->seqno;
++	),
++
++	TP_printk("driver=%s timeline=%s context=%u seqno=%u",
++		  __get_str(driver), __get_str(timeline), __entry->context,
++		  __entry->seqno)
++);
++
++DEFINE_EVENT(fence, fence_emit,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++DEFINE_EVENT(fence, fence_init,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++DEFINE_EVENT(fence, fence_destroy,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++DEFINE_EVENT(fence, fence_enable_signal,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++DEFINE_EVENT(fence, fence_signaled,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++DEFINE_EVENT(fence, fence_wait_start,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++DEFINE_EVENT(fence, fence_wait_end,
++
++	TP_PROTO(struct fence *fence),
++
++	TP_ARGS(fence)
++);
++
++#endif /*  _TRACE_FENCE_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>
+diff -Naur a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
+--- a/include/uapi/drm/drm.h	2015-03-26 14:43:28.038436389 +0530
++++ b/include/uapi/drm/drm.h	2015-03-26 14:42:38.766435423 +0530
+@@ -619,6 +619,15 @@
+ #define  DRM_PRIME_CAP_EXPORT		0x2
+ #define DRM_CAP_TIMESTAMP_MONOTONIC	0x6
+ #define DRM_CAP_ASYNC_PAGE_FLIP		0x7
++/*
++ * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
++ * combination for the hardware cursor. The intention is that a hardware
++ * agnostic userspace can query a cursor plane size to use.
++ *
++ * Note that the cross-driver contract is to merely return a valid size;
++ * drivers are free to attach another meaning on top, eg. i915 returns the
++ * maximum plane size.
++ */
+ #define DRM_CAP_CURSOR_WIDTH		0x8
+ #define DRM_CAP_CURSOR_HEIGHT		0x9
+ 
+@@ -637,6 +646,14 @@
+  */
+ #define DRM_CLIENT_CAP_STEREO_3D	1
+ 
++/**
++ * DRM_CLIENT_CAP_UNIVERSAL_PLANES
++ *
++ * If set to 1, the DRM core will expose all planes (overlay, primary, and
++ * cursor) to userspace.
++ */
++#define DRM_CLIENT_CAP_UNIVERSAL_PLANES  2
++
+ /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
+ struct drm_set_client_cap {
+ 	__u64 capability;
+@@ -763,7 +780,7 @@
+ 
+ /**
+  * Device specific ioctls should only be in their respective headers
+- * The device specific ioctl range is from 0x40 to 0x99.
++ * The device specific ioctl range is from 0x40 to 0x9f.
+  * Generic IOCTLS restart at 0xA0.
+  *
+  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
+diff -Naur a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
+--- a/include/uapi/drm/drm_mode.h	2015-03-26 14:43:28.038436389 +0530
++++ b/include/uapi/drm/drm_mode.h	2015-03-26 14:42:38.766435423 +0530
+@@ -88,6 +88,11 @@
+ #define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
+ #define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
+ 
++/* Picture aspect ratio options */
++#define DRM_MODE_PICTURE_ASPECT_NONE	0
++#define DRM_MODE_PICTURE_ASPECT_4_3	1
++#define DRM_MODE_PICTURE_ASPECT_16_9	2
++
+ /* Dithering mode options */
+ #define DRM_MODE_DITHERING_OFF	0
+ #define DRM_MODE_DITHERING_ON	1
+@@ -181,6 +186,7 @@
+ #define DRM_MODE_ENCODER_TVDAC	4
+ #define DRM_MODE_ENCODER_VIRTUAL 5
+ #define DRM_MODE_ENCODER_DSI	6
++#define DRM_MODE_ENCODER_DPMST	7
+ 
+ struct drm_mode_get_encoder {
+ 	__u32 encoder_id;
+@@ -251,6 +257,21 @@
+ #define DRM_MODE_PROP_BLOB	(1<<4)
+ #define DRM_MODE_PROP_BITMASK	(1<<5) /* bitmask of enumerated types */
+ 
++/* non-extended types: legacy bitmask, one bit per type: */
++#define DRM_MODE_PROP_LEGACY_TYPE  ( \
++		DRM_MODE_PROP_RANGE | \
++		DRM_MODE_PROP_ENUM | \
++		DRM_MODE_PROP_BLOB | \
++		DRM_MODE_PROP_BITMASK)
++
++/* extended-types: rather than continue to consume a bit per type,
++ * grab a chunk of the bits to use as integer type id.
++ */
++#define DRM_MODE_PROP_EXTENDED_TYPE	0x0000ffc0
++#define DRM_MODE_PROP_TYPE(n)		((n) << 6)
++#define DRM_MODE_PROP_OBJECT		DRM_MODE_PROP_TYPE(1)
++#define DRM_MODE_PROP_SIGNED_RANGE	DRM_MODE_PROP_TYPE(2)
++
+ struct drm_mode_property_enum {
+ 	__u64 value;
+ 	char name[DRM_PROP_NAME_LEN];
+@@ -265,6 +286,8 @@
+ 	char name[DRM_PROP_NAME_LEN];
+ 
+ 	__u32 count_values;
++	/* This is only used to count enum values, not blobs. The _blobs is
++	 * simply because of a historical reason, i.e. backwards compat. */
+ 	__u32 count_enum_blobs;
+ };
+ 
+diff -Naur a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
+--- a/include/uapi/drm/i915_drm.h	2015-03-26 14:43:28.038436389 +0530
++++ b/include/uapi/drm/i915_drm.h	2015-03-26 14:42:38.766435423 +0530
+@@ -223,6 +223,7 @@
+ #define DRM_I915_GEM_GET_CACHING	0x30
+ #define DRM_I915_REG_READ		0x31
+ #define DRM_I915_GET_RESET_STATS	0x32
++#define DRM_I915_GEM_USERPTR		0x33
+ 
+ #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
+ #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
+@@ -273,6 +274,7 @@
+ #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
+ #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
+ #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
++#define DRM_IOCTL_I915_GEM_USERPTR			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
+ 
+ /* Allow drivers to submit batchbuffers directly to hardware, relying
+  * on the security mechanisms provided by hardware.
+@@ -337,6 +339,8 @@
+ #define I915_PARAM_HAS_EXEC_NO_RELOC	 25
+ #define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
+ #define I915_PARAM_HAS_WT     	 	 27
++#define I915_PARAM_CMD_PARSER_VERSION	 28
++#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
+ 
+ typedef struct drm_i915_getparam {
+ 	int param;
+@@ -873,6 +877,12 @@
+ 	 * mmap mapping.
+ 	 */
+ 	__u32 swizzle_mode;
++
++	/**
++	 * Returned address bit 6 swizzling required for CPU access through
++	 * mmap mapping whilst bound.
++	 */
++	__u32 phys_swizzle_mode;
+ };
+ 
+ struct drm_i915_gem_get_aperture {
+@@ -1049,4 +1059,18 @@
+ 	__u32 pad;
+ };
+ 
++struct drm_i915_gem_userptr {
++	__u64 user_ptr;
++	__u64 user_size;
++	__u32 flags;
++#define I915_USERPTR_READ_ONLY 0x1
++#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
++	/**
++	 * Returned handle for the object.
++	 *
++	 * Object handles are nonzero.
++	 */
++	__u32 handle;
++};
++
+ #endif /* _UAPI_I915_DRM_H_ */
+diff -Naur a/include/uapi/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h
+--- a/include/uapi/drm/nouveau_drm.h	2015-03-26 14:43:28.038436389 +0530
++++ b/include/uapi/drm/nouveau_drm.h	2015-03-26 14:42:38.766435423 +0530
+@@ -25,6 +25,16 @@
+ #ifndef __NOUVEAU_DRM_H__
+ #define __NOUVEAU_DRM_H__
+ 
++#define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000
++
++/* reserved object handles when using deprecated object APIs - these
++ * are here so that libdrm can allow interoperability with the new
++ * object APIs
++ */
++#define NOUVEAU_ABI16_CLIENT   0xffffffff
++#define NOUVEAU_ABI16_DEVICE   0xdddddddd
++#define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n))
++
+ #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
+ #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
+ #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
+@@ -123,6 +133,7 @@
+ #define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
+ #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
+ #define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
++#define DRM_NOUVEAU_NVIF               0x07
+ #define DRM_NOUVEAU_GEM_NEW            0x40
+ #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
+ #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
+diff -Naur a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
+--- a/kernel/time/timekeeping.c	2015-03-26 14:43:29.038436408 +0530
++++ b/kernel/time/timekeeping.c	2015-03-26 14:42:38.766435423 +0530
+@@ -388,6 +388,33 @@
+ }
+ EXPORT_SYMBOL_GPL(ktime_get_ts);
+ 
++static ktime_t *offsets[TK_OFFS_MAX] = {
++	[TK_OFFS_REAL]  = &timekeeper.offs_real,
++	[TK_OFFS_BOOT]  = &timekeeper.offs_boot,
++	[TK_OFFS_TAI]   = &timekeeper.offs_tai,
++};
++
++
++
++/**
++ * ktime_mono_to_any() - convert mononotic time to any other time
++ * @tmono:     time to convert.
++ * @offs:      which offset to use
++ */
++ktime_t ktime_mono_to_any(ktime_t tmono, enum tk_offsets offs)
++{
++	ktime_t *offset = offsets[offs];
++	unsigned long seq;
++	ktime_t tconv;
++
++	do {
++		seq = read_seqcount_begin(&timekeeper_seq);
++		tconv = ktime_add(tmono, *offset);
++	} while (read_seqcount_retry(&timekeeper_seq, seq));
++
++	return tconv;
++}
++EXPORT_SYMBOL_GPL(ktime_mono_to_any);
+ 
+ /**
+  * timekeeping_clocktai - Returns the TAI time of day in a timespec
+diff -Naur a/kernel/time.c b/kernel/time.c
+--- a/kernel/time.c	2015-03-26 14:43:29.058436409 +0530
++++ b/kernel/time.c	2015-03-26 14:42:38.766435423 +0530
+@@ -700,6 +700,7 @@
+ {
+ 	return (unsigned long)nsecs_to_jiffies64(n);
+ }
++EXPORT_SYMBOL_GPL(nsecs_to_jiffies);
+ 
+ /*
+  * Add two timespec values and do a safety check for overflow.
+diff -Naur a/lib/interval_tree.c b/lib/interval_tree.c
+--- a/lib/interval_tree.c	2015-03-26 14:43:29.510436418 +0530
++++ b/lib/interval_tree.c	2015-03-26 14:42:38.766435423 +0530
+@@ -1,6 +1,7 @@
+ #include <linux/init.h>
+ #include <linux/interval_tree.h>
+ #include <linux/interval_tree_generic.h>
++#include <linux/module.h>
+ 
+ #define START(node) ((node)->start)
+ #define LAST(node)  ((node)->last)
+@@ -8,3 +9,8 @@
+ INTERVAL_TREE_DEFINE(struct interval_tree_node, rb,
+ 		     unsigned long, __subtree_last,
+ 		     START, LAST,, interval_tree)
++
++EXPORT_SYMBOL_GPL(interval_tree_insert);
++EXPORT_SYMBOL_GPL(interval_tree_remove);
++EXPORT_SYMBOL_GPL(interval_tree_iter_first);
++EXPORT_SYMBOL_GPL(interval_tree_iter_next);
+diff -Naur a/lib/interval_tree_test.c b/lib/interval_tree_test.c
+--- a/lib/interval_tree_test.c	1970-01-01 05:30:00.000000000 +0530
++++ b/lib/interval_tree_test.c	2015-03-26 14:42:38.770435423 +0530
+@@ -0,0 +1,106 @@
++#include <linux/module.h>
++#include <linux/interval_tree.h>
++#include <linux/random.h>
++#include <asm/timex.h>
++
++#define NODES        100
++#define PERF_LOOPS   100000
++#define SEARCHES     100
++#define SEARCH_LOOPS 10000
++
++static struct rb_root root = RB_ROOT;
++static struct interval_tree_node nodes[NODES];
++static u32 queries[SEARCHES];
++
++static struct rnd_state rnd;
++
++static inline unsigned long
++search(unsigned long query, struct rb_root *root)
++{
++	struct interval_tree_node *node;
++	unsigned long results = 0;
++
++	for (node = interval_tree_iter_first(root, query, query); node;
++	     node = interval_tree_iter_next(node, query, query))
++		results++;
++	return results;
++}
++
++static void init(void)
++{
++	int i;
++	for (i = 0; i < NODES; i++) {
++		u32 a = prandom_u32_state(&rnd);
++		u32 b = prandom_u32_state(&rnd);
++		if (a <= b) {
++			nodes[i].start = a;
++			nodes[i].last = b;
++		} else {
++			nodes[i].start = b;
++			nodes[i].last = a;
++		}
++	}
++	for (i = 0; i < SEARCHES; i++)
++		queries[i] = prandom_u32_state(&rnd);
++}
++
++static int interval_tree_test_init(void)
++{
++	int i, j;
++	unsigned long results;
++	cycles_t time1, time2, time;
++
++	printk(KERN_ALERT "interval tree insert/remove");
++
++	prandom_seed_state(&rnd, 3141592653589793238ULL);
++	init();
++
++	time1 = get_cycles();
++
++	for (i = 0; i < PERF_LOOPS; i++) {
++		for (j = 0; j < NODES; j++)
++			interval_tree_insert(nodes + j, &root);
++		for (j = 0; j < NODES; j++)
++			interval_tree_remove(nodes + j, &root);
++	}
++
++	time2 = get_cycles();
++	time = time2 - time1;
++
++	time = div_u64(time, PERF_LOOPS);
++	printk(" -> %llu cycles\n", (unsigned long long)time);
++
++	printk(KERN_ALERT "interval tree search");
++
++	for (j = 0; j < NODES; j++)
++		interval_tree_insert(nodes + j, &root);
++
++	time1 = get_cycles();
++
++	results = 0;
++	for (i = 0; i < SEARCH_LOOPS; i++)
++		for (j = 0; j < SEARCHES; j++)
++			results += search(queries[j], &root);
++
++	time2 = get_cycles();
++	time = time2 - time1;
++
++	time = div_u64(time, SEARCH_LOOPS);
++	results = div_u64(results, SEARCH_LOOPS);
++	printk(" -> %llu cycles (%lu results)\n",
++	       (unsigned long long)time, results);
++
++	return -EAGAIN; /* Fail will directly unload the module */
++}
++
++static void interval_tree_test_exit(void)
++{
++	printk(KERN_ALERT "test exit\n");
++}
++
++module_init(interval_tree_test_init)
++module_exit(interval_tree_test_exit)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Michel Lespinasse");
++MODULE_DESCRIPTION("Interval Tree test");
+diff -Naur a/lib/interval_tree_test_main.c b/lib/interval_tree_test_main.c
+--- a/lib/interval_tree_test_main.c	2015-03-26 14:43:29.518436418 +0530
++++ b/lib/interval_tree_test_main.c	1970-01-01 05:30:00.000000000 +0530
+@@ -1,106 +0,0 @@
+-#include <linux/module.h>
+-#include <linux/interval_tree.h>
+-#include <linux/random.h>
+-#include <asm/timex.h>
+-
+-#define NODES        100
+-#define PERF_LOOPS   100000
+-#define SEARCHES     100
+-#define SEARCH_LOOPS 10000
+-
+-static struct rb_root root = RB_ROOT;
+-static struct interval_tree_node nodes[NODES];
+-static u32 queries[SEARCHES];
+-
+-static struct rnd_state rnd;
+-
+-static inline unsigned long
+-search(unsigned long query, struct rb_root *root)
+-{
+-	struct interval_tree_node *node;
+-	unsigned long results = 0;
+-
+-	for (node = interval_tree_iter_first(root, query, query); node;
+-	     node = interval_tree_iter_next(node, query, query))
+-		results++;
+-	return results;
+-}
+-
+-static void init(void)
+-{
+-	int i;
+-	for (i = 0; i < NODES; i++) {
+-		u32 a = prandom_u32_state(&rnd);
+-		u32 b = prandom_u32_state(&rnd);
+-		if (a <= b) {
+-			nodes[i].start = a;
+-			nodes[i].last = b;
+-		} else {
+-			nodes[i].start = b;
+-			nodes[i].last = a;
+-		}
+-	}
+-	for (i = 0; i < SEARCHES; i++)
+-		queries[i] = prandom_u32_state(&rnd);
+-}
+-
+-static int interval_tree_test_init(void)
+-{
+-	int i, j;
+-	unsigned long results;
+-	cycles_t time1, time2, time;
+-
+-	printk(KERN_ALERT "interval tree insert/remove");
+-
+-	prandom_seed_state(&rnd, 3141592653589793238ULL);
+-	init();
+-
+-	time1 = get_cycles();
+-
+-	for (i = 0; i < PERF_LOOPS; i++) {
+-		for (j = 0; j < NODES; j++)
+-			interval_tree_insert(nodes + j, &root);
+-		for (j = 0; j < NODES; j++)
+-			interval_tree_remove(nodes + j, &root);
+-	}
+-
+-	time2 = get_cycles();
+-	time = time2 - time1;
+-
+-	time = div_u64(time, PERF_LOOPS);
+-	printk(" -> %llu cycles\n", (unsigned long long)time);
+-
+-	printk(KERN_ALERT "interval tree search");
+-
+-	for (j = 0; j < NODES; j++)
+-		interval_tree_insert(nodes + j, &root);
+-
+-	time1 = get_cycles();
+-
+-	results = 0;
+-	for (i = 0; i < SEARCH_LOOPS; i++)
+-		for (j = 0; j < SEARCHES; j++)
+-			results += search(queries[j], &root);
+-
+-	time2 = get_cycles();
+-	time = time2 - time1;
+-
+-	time = div_u64(time, SEARCH_LOOPS);
+-	results = div_u64(results, SEARCH_LOOPS);
+-	printk(" -> %llu cycles (%lu results)\n",
+-	       (unsigned long long)time, results);
+-
+-	return -EAGAIN; /* Fail will directly unload the module */
+-}
+-
+-static void interval_tree_test_exit(void)
+-{
+-	printk(KERN_ALERT "test exit\n");
+-}
+-
+-module_init(interval_tree_test_init)
+-module_exit(interval_tree_test_exit)
+-
+-MODULE_LICENSE("GPL");
+-MODULE_AUTHOR("Michel Lespinasse");
+-MODULE_DESCRIPTION("Interval Tree test");
+diff -Naur a/lib/Kconfig b/lib/Kconfig
+--- a/lib/Kconfig	2015-03-26 14:43:29.510436418 +0530
++++ b/lib/Kconfig	2015-03-26 14:42:38.770435423 +0530
+@@ -322,6 +322,20 @@
+ config BTREE
+ 	boolean
+ 
++config INTERVAL_TREE
++	boolean
++	help
++	  Simple, embeddable, interval-tree. Can find the start of an
++	  overlapping range in log(n) time and then iterate over all
++	  overlapping nodes. The algorithm is implemented as an
++	  augmented rbtree.
++
++	  See:
++
++		Documentation/rbtree.txt
++
++	  for more information.
++
+ config ASSOCIATIVE_ARRAY
+ 	bool
+ 	help
+diff -Naur a/lib/Kconfig.debug b/lib/Kconfig.debug
+--- a/lib/Kconfig.debug	2015-03-26 14:43:29.526436418 +0530
++++ b/lib/Kconfig.debug	2015-03-26 14:42:38.770435423 +0530
+@@ -1487,6 +1487,7 @@
+ config INTERVAL_TREE_TEST
+ 	tristate "Interval tree test"
+ 	depends on m && DEBUG_KERNEL
++	select INTERVAL_TREE
+ 	help
+ 	  A benchmark measuring the performance of the interval tree library
+ 
+diff -Naur a/lib/Makefile b/lib/Makefile
+--- a/lib/Makefile	2015-03-26 14:43:29.514436418 +0530
++++ b/lib/Makefile	2015-03-26 14:42:38.770435423 +0530
+@@ -50,6 +50,7 @@
+ obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
+ 
+ obj-$(CONFIG_BTREE) += btree.o
++obj-$(CONFIG_INTERVAL_TREE) += interval_tree.o
+ obj-$(CONFIG_ASSOCIATIVE_ARRAY) += assoc_array.o
+ obj-$(CONFIG_DEBUG_PREEMPT) += smp_processor_id.o
+ obj-$(CONFIG_DEBUG_LIST) += list_debug.o
+@@ -155,8 +156,6 @@
+ obj-$(CONFIG_RBTREE_TEST) += rbtree_test.o
+ obj-$(CONFIG_INTERVAL_TREE_TEST) += interval_tree_test.o
+ 
+-interval_tree_test-objs := interval_tree_test_main.o interval_tree.o
+-
+ obj-$(CONFIG_PERCPU_TEST) += percpu_test.o
+ 
+ obj-$(CONFIG_ASN1) += asn1_decoder.o
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0007-yocto-amd-drm-amdgpu-add-core-driver.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0007-yocto-amd-drm-amdgpu-add-core-driver.patch
new file mode 100644
index 00000000..7ae6ffae
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0007-yocto-amd-drm-amdgpu-add-core-driver.patch
@@ -0,0 +1,2552 @@
+From f80c787f56e4c2fec25c172f8e717fa4ea2865f4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:19:28 -0400
+Subject: drm/amdgpu: add GCA 7.0 register headers
+
+These are register headers for the GCA (Graphics and Compute Array)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h
+new file mode 100644
+index 0000000..b1d7cef
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h
+@@ -0,0 +1,2532 @@
++/*
++ * GFX_7_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_7_0_D_H
++#define GFX_7_0_D_H
++
++#define mmCB_BLEND_RED                                                          0xa105
++#define mmCB_BLEND_GREEN                                                        0xa106
++#define mmCB_BLEND_BLUE                                                         0xa107
++#define mmCB_BLEND_ALPHA                                                        0xa108
++#define mmCB_COLOR_CONTROL                                                      0xa202
++#define mmCB_BLEND0_CONTROL                                                     0xa1e0
++#define mmCB_BLEND1_CONTROL                                                     0xa1e1
++#define mmCB_BLEND2_CONTROL                                                     0xa1e2
++#define mmCB_BLEND3_CONTROL                                                     0xa1e3
++#define mmCB_BLEND4_CONTROL                                                     0xa1e4
++#define mmCB_BLEND5_CONTROL                                                     0xa1e5
++#define mmCB_BLEND6_CONTROL                                                     0xa1e6
++#define mmCB_BLEND7_CONTROL                                                     0xa1e7
++#define mmCB_COLOR0_BASE                                                        0xa318
++#define mmCB_COLOR1_BASE                                                        0xa327
++#define mmCB_COLOR2_BASE                                                        0xa336
++#define mmCB_COLOR3_BASE                                                        0xa345
++#define mmCB_COLOR4_BASE                                                        0xa354
++#define mmCB_COLOR5_BASE                                                        0xa363
++#define mmCB_COLOR6_BASE                                                        0xa372
++#define mmCB_COLOR7_BASE                                                        0xa381
++#define mmCB_COLOR0_PITCH                                                       0xa319
++#define mmCB_COLOR1_PITCH                                                       0xa328
++#define mmCB_COLOR2_PITCH                                                       0xa337
++#define mmCB_COLOR3_PITCH                                                       0xa346
++#define mmCB_COLOR4_PITCH                                                       0xa355
++#define mmCB_COLOR5_PITCH                                                       0xa364
++#define mmCB_COLOR6_PITCH                                                       0xa373
++#define mmCB_COLOR7_PITCH                                                       0xa382
++#define mmCB_COLOR0_SLICE                                                       0xa31a
++#define mmCB_COLOR1_SLICE                                                       0xa329
++#define mmCB_COLOR2_SLICE                                                       0xa338
++#define mmCB_COLOR3_SLICE                                                       0xa347
++#define mmCB_COLOR4_SLICE                                                       0xa356
++#define mmCB_COLOR5_SLICE                                                       0xa365
++#define mmCB_COLOR6_SLICE                                                       0xa374
++#define mmCB_COLOR7_SLICE                                                       0xa383
++#define mmCB_COLOR0_VIEW                                                        0xa31b
++#define mmCB_COLOR1_VIEW                                                        0xa32a
++#define mmCB_COLOR2_VIEW                                                        0xa339
++#define mmCB_COLOR3_VIEW                                                        0xa348
++#define mmCB_COLOR4_VIEW                                                        0xa357
++#define mmCB_COLOR5_VIEW                                                        0xa366
++#define mmCB_COLOR6_VIEW                                                        0xa375
++#define mmCB_COLOR7_VIEW                                                        0xa384
++#define mmCB_COLOR0_INFO                                                        0xa31c
++#define mmCB_COLOR1_INFO                                                        0xa32b
++#define mmCB_COLOR2_INFO                                                        0xa33a
++#define mmCB_COLOR3_INFO                                                        0xa349
++#define mmCB_COLOR4_INFO                                                        0xa358
++#define mmCB_COLOR5_INFO                                                        0xa367
++#define mmCB_COLOR6_INFO                                                        0xa376
++#define mmCB_COLOR7_INFO                                                        0xa385
++#define mmCB_COLOR0_ATTRIB                                                      0xa31d
++#define mmCB_COLOR1_ATTRIB                                                      0xa32c
++#define mmCB_COLOR2_ATTRIB                                                      0xa33b
++#define mmCB_COLOR3_ATTRIB                                                      0xa34a
++#define mmCB_COLOR4_ATTRIB                                                      0xa359
++#define mmCB_COLOR5_ATTRIB                                                      0xa368
++#define mmCB_COLOR6_ATTRIB                                                      0xa377
++#define mmCB_COLOR7_ATTRIB                                                      0xa386
++#define mmCB_COLOR0_CMASK                                                       0xa31f
++#define mmCB_COLOR1_CMASK                                                       0xa32e
++#define mmCB_COLOR2_CMASK                                                       0xa33d
++#define mmCB_COLOR3_CMASK                                                       0xa34c
++#define mmCB_COLOR4_CMASK                                                       0xa35b
++#define mmCB_COLOR5_CMASK                                                       0xa36a
++#define mmCB_COLOR6_CMASK                                                       0xa379
++#define mmCB_COLOR7_CMASK                                                       0xa388
++#define mmCB_COLOR0_CMASK_SLICE                                                 0xa320
++#define mmCB_COLOR1_CMASK_SLICE                                                 0xa32f
++#define mmCB_COLOR2_CMASK_SLICE                                                 0xa33e
++#define mmCB_COLOR3_CMASK_SLICE                                                 0xa34d
++#define mmCB_COLOR4_CMASK_SLICE                                                 0xa35c
++#define mmCB_COLOR5_CMASK_SLICE                                                 0xa36b
++#define mmCB_COLOR6_CMASK_SLICE                                                 0xa37a
++#define mmCB_COLOR7_CMASK_SLICE                                                 0xa389
++#define mmCB_COLOR0_FMASK                                                       0xa321
++#define mmCB_COLOR1_FMASK                                                       0xa330
++#define mmCB_COLOR2_FMASK                                                       0xa33f
++#define mmCB_COLOR3_FMASK                                                       0xa34e
++#define mmCB_COLOR4_FMASK                                                       0xa35d
++#define mmCB_COLOR5_FMASK                                                       0xa36c
++#define mmCB_COLOR6_FMASK                                                       0xa37b
++#define mmCB_COLOR7_FMASK                                                       0xa38a
++#define mmCB_COLOR0_FMASK_SLICE                                                 0xa322
++#define mmCB_COLOR1_FMASK_SLICE                                                 0xa331
++#define mmCB_COLOR2_FMASK_SLICE                                                 0xa340
++#define mmCB_COLOR3_FMASK_SLICE                                                 0xa34f
++#define mmCB_COLOR4_FMASK_SLICE                                                 0xa35e
++#define mmCB_COLOR5_FMASK_SLICE                                                 0xa36d
++#define mmCB_COLOR6_FMASK_SLICE                                                 0xa37c
++#define mmCB_COLOR7_FMASK_SLICE                                                 0xa38b
++#define mmCB_COLOR0_CLEAR_WORD0                                                 0xa323
++#define mmCB_COLOR1_CLEAR_WORD0                                                 0xa332
++#define mmCB_COLOR2_CLEAR_WORD0                                                 0xa341
++#define mmCB_COLOR3_CLEAR_WORD0                                                 0xa350
++#define mmCB_COLOR4_CLEAR_WORD0                                                 0xa35f
++#define mmCB_COLOR5_CLEAR_WORD0                                                 0xa36e
++#define mmCB_COLOR6_CLEAR_WORD0                                                 0xa37d
++#define mmCB_COLOR7_CLEAR_WORD0                                                 0xa38c
++#define mmCB_COLOR0_CLEAR_WORD1                                                 0xa324
++#define mmCB_COLOR1_CLEAR_WORD1                                                 0xa333
++#define mmCB_COLOR2_CLEAR_WORD1                                                 0xa342
++#define mmCB_COLOR3_CLEAR_WORD1                                                 0xa351
++#define mmCB_COLOR4_CLEAR_WORD1                                                 0xa360
++#define mmCB_COLOR5_CLEAR_WORD1                                                 0xa36f
++#define mmCB_COLOR6_CLEAR_WORD1                                                 0xa37e
++#define mmCB_COLOR7_CLEAR_WORD1                                                 0xa38d
++#define mmCB_TARGET_MASK                                                        0xa08e
++#define mmCB_SHADER_MASK                                                        0xa08f
++#define mmCB_HW_CONTROL                                                         0x2684
++#define mmCB_HW_CONTROL_1                                                       0x2685
++#define mmCB_HW_CONTROL_2                                                       0x2686
++#define mmCB_HW_CONTROL_3                                                       0x2683
++#define mmCB_PERFCOUNTER_FILTER                                                 0xdc00
++#define mmCB_PERFCOUNTER0_SELECT                                                0xdc01
++#define mmCB_PERFCOUNTER0_SELECT1                                               0xdc02
++#define mmCB_PERFCOUNTER1_SELECT                                                0xdc03
++#define mmCB_PERFCOUNTER2_SELECT                                                0xdc04
++#define mmCB_PERFCOUNTER3_SELECT                                                0xdc05
++#define mmCB_PERFCOUNTER0_LO                                                    0xd406
++#define mmCB_PERFCOUNTER1_LO                                                    0xd408
++#define mmCB_PERFCOUNTER2_LO                                                    0xd40a
++#define mmCB_PERFCOUNTER3_LO                                                    0xd40c
++#define mmCB_PERFCOUNTER0_HI                                                    0xd407
++#define mmCB_PERFCOUNTER1_HI                                                    0xd409
++#define mmCB_PERFCOUNTER2_HI                                                    0xd40b
++#define mmCB_PERFCOUNTER3_HI                                                    0xd40d
++#define mmCB_CGTT_SCLK_CTRL                                                     0xf0a8
++#define mmCB_DEBUG_BUS_1                                                        0x2699
++#define mmCB_DEBUG_BUS_2                                                        0x269a
++#define mmCB_DEBUG_BUS_3                                                        0x269b
++#define mmCB_DEBUG_BUS_4                                                        0x269c
++#define mmCB_DEBUG_BUS_5                                                        0x269d
++#define mmCB_DEBUG_BUS_6                                                        0x269e
++#define mmCB_DEBUG_BUS_7                                                        0x269f
++#define mmCB_DEBUG_BUS_8                                                        0x26a0
++#define mmCB_DEBUG_BUS_9                                                        0x26a1
++#define mmCB_DEBUG_BUS_10                                                       0x26a2
++#define mmCB_DEBUG_BUS_11                                                       0x26a3
++#define mmCB_DEBUG_BUS_12                                                       0x26a4
++#define mmCB_DEBUG_BUS_13                                                       0x26a5
++#define mmCB_DEBUG_BUS_14                                                       0x26a6
++#define mmCB_DEBUG_BUS_15                                                       0x26a7
++#define mmCB_DEBUG_BUS_16                                                       0x26a8
++#define mmCB_DEBUG_BUS_17                                                       0x26a9
++#define mmCB_DEBUG_BUS_18                                                       0x26aa
++#define mmCP_DFY_CNTL                                                           0x3020
++#define mmCP_DFY_STAT                                                           0x3021
++#define mmCP_DFY_ADDR_HI                                                        0x3022
++#define mmCP_DFY_ADDR_LO                                                        0x3023
++#define mmCP_DFY_DATA_0                                                         0x3024
++#define mmCP_DFY_DATA_1                                                         0x3025
++#define mmCP_DFY_DATA_2                                                         0x3026
++#define mmCP_DFY_DATA_3                                                         0x3027
++#define mmCP_DFY_DATA_4                                                         0x3028
++#define mmCP_DFY_DATA_5                                                         0x3029
++#define mmCP_DFY_DATA_6                                                         0x302a
++#define mmCP_DFY_DATA_7                                                         0x302b
++#define mmCP_DFY_DATA_8                                                         0x302c
++#define mmCP_DFY_DATA_9                                                         0x302d
++#define mmCP_DFY_DATA_10                                                        0x302e
++#define mmCP_DFY_DATA_11                                                        0x302f
++#define mmCP_DFY_DATA_12                                                        0x3030
++#define mmCP_DFY_DATA_13                                                        0x3031
++#define mmCP_DFY_DATA_14                                                        0x3032
++#define mmCP_DFY_DATA_15                                                        0x3033
++#define mmCP_RB0_BASE                                                           0x3040
++#define mmCP_RB0_BASE_HI                                                        0x30b1
++#define mmCP_RB_BASE                                                            0x3040
++#define mmCP_RB1_BASE                                                           0x3060
++#define mmCP_RB1_BASE_HI                                                        0x30b2
++#define mmCP_RB2_BASE                                                           0x3065
++#define mmCP_RB0_CNTL                                                           0x3041
++#define mmCP_RB_CNTL                                                            0x3041
++#define mmCP_RB1_CNTL                                                           0x3061
++#define mmCP_RB2_CNTL                                                           0x3066
++#define mmCP_RB_RPTR_WR                                                         0x3042
++#define mmCP_RB0_RPTR_ADDR                                                      0x3043
++#define mmCP_RB_RPTR_ADDR                                                       0x3043
++#define mmCP_RB1_RPTR_ADDR                                                      0x3062
++#define mmCP_RB2_RPTR_ADDR                                                      0x3067
++#define mmCP_RB0_RPTR_ADDR_HI                                                   0x3044
++#define mmCP_RB_RPTR_ADDR_HI                                                    0x3044
++#define mmCP_RB1_RPTR_ADDR_HI                                                   0x3063
++#define mmCP_RB2_RPTR_ADDR_HI                                                   0x3068
++#define mmCP_RB0_WPTR                                                           0x3045
++#define mmCP_RB_WPTR                                                            0x3045
++#define mmCP_RB1_WPTR                                                           0x3064
++#define mmCP_RB2_WPTR                                                           0x3069
++#define mmCP_RB_WPTR_POLL_ADDR_LO                                               0x3046
++#define mmCP_RB_WPTR_POLL_ADDR_HI                                               0x3047
++#define mmGC_PRIV_MODE                                                          0x3048
++#define mmCP_INT_CNTL                                                           0x3049
++#define mmCP_INT_CNTL_RING0                                                     0x306a
++#define mmCP_INT_CNTL_RING1                                                     0x306b
++#define mmCP_INT_CNTL_RING2                                                     0x306c
++#define mmCP_INT_STATUS                                                         0x304a
++#define mmCP_INT_STATUS_RING0                                                   0x306d
++#define mmCP_INT_STATUS_RING1                                                   0x306e
++#define mmCP_INT_STATUS_RING2                                                   0x306f
++#define mmCP_DEVICE_ID                                                          0x304b
++#define mmCP_RING_PRIORITY_CNTS                                                 0x304c
++#define mmCP_ME0_PIPE_PRIORITY_CNTS                                             0x304c
++#define mmCP_RING0_PRIORITY                                                     0x304d
++#define mmCP_ME0_PIPE0_PRIORITY                                                 0x304d
++#define mmCP_RING1_PRIORITY                                                     0x304e
++#define mmCP_ME0_PIPE1_PRIORITY                                                 0x304e
++#define mmCP_RING2_PRIORITY                                                     0x304f
++#define mmCP_ME0_PIPE2_PRIORITY                                                 0x304f
++#define mmCP_ENDIAN_SWAP                                                        0x3050
++#define mmCP_RB_VMID                                                            0x3051
++#define mmCP_PFP_UCODE_ADDR                                                     0x3054
++#define mmCP_PFP_UCODE_DATA                                                     0x3055
++#define mmCP_ME_RAM_RADDR                                                       0x3056
++#define mmCP_ME_RAM_WADDR                                                       0x3057
++#define mmCP_ME_RAM_DATA                                                        0x3058
++#define mmCGTT_CPC_CLK_CTRL                                                     0xf0b2
++#define mmCGTT_CPF_CLK_CTRL                                                     0xf0b1
++#define mmCGTT_CP_CLK_CTRL                                                      0xf0b0
++#define mmCP_CE_UCODE_ADDR                                                      0x305a
++#define mmCP_CE_UCODE_DATA                                                      0x305b
++#define mmCP_MEC_ME1_UCODE_ADDR                                                 0x305c
++#define mmCP_MEC_ME1_UCODE_DATA                                                 0x305d
++#define mmCP_MEC_ME2_UCODE_ADDR                                                 0x305e
++#define mmCP_MEC_ME2_UCODE_DATA                                                 0x305f
++#define mmCP_PWR_CNTL                                                           0x3078
++#define mmCP_MEM_SLP_CNTL                                                       0x3079
++#define mmCP_ECC_FIRSTOCCURRENCE                                                0x307a
++#define mmCP_ECC_FIRSTOCCURRENCE_RING0                                          0x307b
++#define mmCP_ECC_FIRSTOCCURRENCE_RING1                                          0x307c
++#define mmCP_ECC_FIRSTOCCURRENCE_RING2                                          0x307d
++#define mmCP_CPF_DEBUG                                                          0x3080
++#define mmCP_FETCHER_SOURCE                                                     0x3082
++#define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
++#define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
++#define mmCPC_INT_CNTL                                                          0x30b4
++#define mmCP_ME1_PIPE0_INT_CNTL                                                 0x3085
++#define mmCP_ME1_PIPE1_INT_CNTL                                                 0x3086
++#define mmCP_ME1_PIPE2_INT_CNTL                                                 0x3087
++#define mmCP_ME1_PIPE3_INT_CNTL                                                 0x3088
++#define mmCP_ME2_PIPE0_INT_CNTL                                                 0x3089
++#define mmCP_ME2_PIPE1_INT_CNTL                                                 0x308a
++#define mmCP_ME2_PIPE2_INT_CNTL                                                 0x308b
++#define mmCP_ME2_PIPE3_INT_CNTL                                                 0x308c
++#define mmCPC_INT_STATUS                                                        0x30b5
++#define mmCP_ME1_PIPE0_INT_STATUS                                               0x308d
++#define mmCP_ME1_PIPE1_INT_STATUS                                               0x308e
++#define mmCP_ME1_PIPE2_INT_STATUS                                               0x308f
++#define mmCP_ME1_PIPE3_INT_STATUS                                               0x3090
++#define mmCP_ME2_PIPE0_INT_STATUS                                               0x3091
++#define mmCP_ME2_PIPE1_INT_STATUS                                               0x3092
++#define mmCP_ME2_PIPE2_INT_STATUS                                               0x3093
++#define mmCP_ME2_PIPE3_INT_STATUS                                               0x3094
++#define mmCP_ME1_INT_STAT_DEBUG                                                 0x3095
++#define mmCP_ME2_INT_STAT_DEBUG                                                 0x3096
++#define mmCP_ME1_PIPE_PRIORITY_CNTS                                             0x3099
++#define mmCP_ME1_PIPE0_PRIORITY                                                 0x309a
++#define mmCP_ME1_PIPE1_PRIORITY                                                 0x309b
++#define mmCP_ME1_PIPE2_PRIORITY                                                 0x309c
++#define mmCP_ME1_PIPE3_PRIORITY                                                 0x309d
++#define mmCP_ME2_PIPE_PRIORITY_CNTS                                             0x309e
++#define mmCP_ME2_PIPE0_PRIORITY                                                 0x309f
++#define mmCP_ME2_PIPE1_PRIORITY                                                 0x30a0
++#define mmCP_ME2_PIPE2_PRIORITY                                                 0x30a1
++#define mmCP_ME2_PIPE3_PRIORITY                                                 0x30a2
++#define mmCP_CE_PRGRM_CNTR_START                                                0x30a3
++#define mmCP_PFP_PRGRM_CNTR_START                                               0x30a4
++#define mmCP_ME_PRGRM_CNTR_START                                                0x30a5
++#define mmCP_MEC1_PRGRM_CNTR_START                                              0x30a6
++#define mmCP_MEC2_PRGRM_CNTR_START                                              0x30a7
++#define mmCP_CE_INTR_ROUTINE_START                                              0x30a8
++#define mmCP_PFP_INTR_ROUTINE_START                                             0x30a9
++#define mmCP_ME_INTR_ROUTINE_START                                              0x30aa
++#define mmCP_MEC1_INTR_ROUTINE_START                                            0x30ab
++#define mmCP_MEC2_INTR_ROUTINE_START                                            0x30ac
++#define mmCP_CONTEXT_CNTL                                                       0x30ad
++#define mmCP_MAX_CONTEXT                                                        0x30ae
++#define mmCP_IQ_WAIT_TIME1                                                      0x30af
++#define mmCP_IQ_WAIT_TIME2                                                      0x30b0
++#define mmCP_VMID_RESET                                                         0x30b3
++#define mmCP_VMID_PREEMPT                                                       0x30b6
++#define mmCP_PQ_STATUS                                                          0x30b8
++#define mmCP_CPC_STATUS                                                         0x2084
++#define mmCP_CPC_BUSY_STAT                                                      0x2085
++#define mmCP_CPC_STALLED_STAT1                                                  0x2086
++#define mmCP_CPF_STATUS                                                         0x2087
++#define mmCP_CPF_BUSY_STAT                                                      0x2088
++#define mmCP_CPF_STALLED_STAT1                                                  0x2089
++#define mmCP_CPC_MC_CNTL                                                        0x208a
++#define mmCP_CPC_GRBM_FREE_COUNT                                                0x208b
++#define mmCP_MEC_CNTL                                                           0x208d
++#define mmCP_MEC_ME1_HEADER_DUMP                                                0x208e
++#define mmCP_MEC_ME2_HEADER_DUMP                                                0x208f
++#define mmCP_CPC_SCRATCH_INDEX                                                  0x2090
++#define mmCP_CPC_SCRATCH_DATA                                                   0x2091
++#define mmCPG_PERFCOUNTER1_SELECT                                               0xd800
++#define mmCPG_PERFCOUNTER1_LO                                                   0xd000
++#define mmCPG_PERFCOUNTER1_HI                                                   0xd001
++#define mmCPG_PERFCOUNTER0_SELECT1                                              0xd801
++#define mmCPG_PERFCOUNTER0_SELECT                                               0xd802
++#define mmCPG_PERFCOUNTER0_LO                                                   0xd002
++#define mmCPG_PERFCOUNTER0_HI                                                   0xd003
++#define mmCPC_PERFCOUNTER1_SELECT                                               0xd803
++#define mmCPC_PERFCOUNTER1_LO                                                   0xd004
++#define mmCPC_PERFCOUNTER1_HI                                                   0xd005
++#define mmCPC_PERFCOUNTER0_SELECT1                                              0xd804
++#define mmCPC_PERFCOUNTER0_SELECT                                               0xd809
++#define mmCPC_PERFCOUNTER0_LO                                                   0xd006
++#define mmCPC_PERFCOUNTER0_HI                                                   0xd007
++#define mmCPF_PERFCOUNTER1_SELECT                                               0xd805
++#define mmCPF_PERFCOUNTER1_LO                                                   0xd008
++#define mmCPF_PERFCOUNTER1_HI                                                   0xd009
++#define mmCPF_PERFCOUNTER0_SELECT1                                              0xd806
++#define mmCPF_PERFCOUNTER0_SELECT                                               0xd807
++#define mmCPF_PERFCOUNTER0_LO                                                   0xd00a
++#define mmCPF_PERFCOUNTER0_HI                                                   0xd00b
++#define mmCP_CPC_HALT_HYST_COUNT                                                0x20a7
++#define mmCP_CE_COMPARE_COUNT                                                   0x20c0
++#define mmCP_CE_DE_COUNT                                                        0x20c1
++#define mmCP_DE_CE_COUNT                                                        0x20c2
++#define mmCP_DE_LAST_INVAL_COUNT                                                0x20c3
++#define mmCP_DE_DE_COUNT                                                        0x20c4
++#define mmCP_EOP_DONE_EVENT_CNTL                                                0xc0d5
++#define mmCP_EOP_DONE_DATA_CNTL                                                 0xc0d6
++#define mmCP_EOP_DONE_ADDR_LO                                                   0xc000
++#define mmCP_EOP_DONE_ADDR_HI                                                   0xc001
++#define mmCP_EOP_DONE_DATA_LO                                                   0xc002
++#define mmCP_EOP_DONE_DATA_HI                                                   0xc003
++#define mmCP_EOP_LAST_FENCE_LO                                                  0xc004
++#define mmCP_EOP_LAST_FENCE_HI                                                  0xc005
++#define mmCP_STREAM_OUT_ADDR_LO                                                 0xc006
++#define mmCP_STREAM_OUT_ADDR_HI                                                 0xc007
++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                                         0xc008
++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                                         0xc009
++#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO                                          0xc00a
++#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI                                          0xc00b
++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                                         0xc00c
++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                                         0xc00d
++#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO                                          0xc00e
++#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI                                          0xc00f
++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                                         0xc010
++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                                         0xc011
++#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO                                          0xc012
++#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI                                          0xc013
++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                                         0xc014
++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                                         0xc015
++#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO                                          0xc016
++#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI                                          0xc017
++#define mmCP_PIPE_STATS_ADDR_LO                                                 0xc018
++#define mmCP_PIPE_STATS_ADDR_HI                                                 0xc019
++#define mmCP_VGT_IAVERT_COUNT_LO                                                0xc01a
++#define mmCP_VGT_IAVERT_COUNT_HI                                                0xc01b
++#define mmCP_VGT_IAPRIM_COUNT_LO                                                0xc01c
++#define mmCP_VGT_IAPRIM_COUNT_HI                                                0xc01d
++#define mmCP_VGT_GSPRIM_COUNT_LO                                                0xc01e
++#define mmCP_VGT_GSPRIM_COUNT_HI                                                0xc01f
++#define mmCP_VGT_VSINVOC_COUNT_LO                                               0xc020
++#define mmCP_VGT_VSINVOC_COUNT_HI                                               0xc021
++#define mmCP_VGT_GSINVOC_COUNT_LO                                               0xc022
++#define mmCP_VGT_GSINVOC_COUNT_HI                                               0xc023
++#define mmCP_VGT_HSINVOC_COUNT_LO                                               0xc024
++#define mmCP_VGT_HSINVOC_COUNT_HI                                               0xc025
++#define mmCP_VGT_DSINVOC_COUNT_LO                                               0xc026
++#define mmCP_VGT_DSINVOC_COUNT_HI                                               0xc027
++#define mmCP_PA_CINVOC_COUNT_LO                                                 0xc028
++#define mmCP_PA_CINVOC_COUNT_HI                                                 0xc029
++#define mmCP_PA_CPRIM_COUNT_LO                                                  0xc02a
++#define mmCP_PA_CPRIM_COUNT_HI                                                  0xc02b
++#define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
++#define mmCP_SC_PSINVOC_COUNT0_HI                                               0xc02d
++#define mmCP_SC_PSINVOC_COUNT1_LO                                               0xc02e
++#define mmCP_SC_PSINVOC_COUNT1_HI                                               0xc02f
++#define mmCP_VGT_CSINVOC_COUNT_LO                                               0xc030
++#define mmCP_VGT_CSINVOC_COUNT_HI                                               0xc031
++#define mmCP_STRMOUT_CNTL                                                       0xc03f
++#define mmSCRATCH_REG0                                                          0xc040
++#define mmSCRATCH_REG1                                                          0xc041
++#define mmSCRATCH_REG2                                                          0xc042
++#define mmSCRATCH_REG3                                                          0xc043
++#define mmSCRATCH_REG4                                                          0xc044
++#define mmSCRATCH_REG5                                                          0xc045
++#define mmSCRATCH_REG6                                                          0xc046
++#define mmSCRATCH_REG7                                                          0xc047
++#define mmSCRATCH_UMSK                                                          0xc050
++#define mmSCRATCH_ADDR                                                          0xc051
++#define mmCP_PFP_ATOMIC_PREOP_LO                                                0xc052
++#define mmCP_PFP_ATOMIC_PREOP_HI                                                0xc053
++#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO                                           0xc054
++#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI                                           0xc055
++#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO                                           0xc056
++#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI                                           0xc057
++#define mmCP_APPEND_ADDR_LO                                                     0xc058
++#define mmCP_APPEND_ADDR_HI                                                     0xc059
++#define mmCP_APPEND_DATA                                                        0xc05a
++#define mmCP_APPEND_LAST_CS_FENCE                                               0xc05b
++#define mmCP_APPEND_LAST_PS_FENCE                                               0xc05c
++#define mmCP_ATOMIC_PREOP_LO                                                    0xc05d
++#define mmCP_ME_ATOMIC_PREOP_LO                                                 0xc05d
++#define mmCP_ATOMIC_PREOP_HI                                                    0xc05e
++#define mmCP_ME_ATOMIC_PREOP_HI                                                 0xc05e
++#define mmCP_GDS_ATOMIC0_PREOP_LO                                               0xc05f
++#define mmCP_ME_GDS_ATOMIC0_PREOP_LO                                            0xc05f
++#define mmCP_GDS_ATOMIC0_PREOP_HI                                               0xc060
++#define mmCP_ME_GDS_ATOMIC0_PREOP_HI                                            0xc060
++#define mmCP_GDS_ATOMIC1_PREOP_LO                                               0xc061
++#define mmCP_ME_GDS_ATOMIC1_PREOP_LO                                            0xc061
++#define mmCP_GDS_ATOMIC1_PREOP_HI                                               0xc062
++#define mmCP_ME_GDS_ATOMIC1_PREOP_HI                                            0xc062
++#define mmCP_ME_MC_WADDR_LO                                                     0xc069
++#define mmCP_ME_MC_WADDR_HI                                                     0xc06a
++#define mmCP_ME_MC_WDATA_LO                                                     0xc06b
++#define mmCP_ME_MC_WDATA_HI                                                     0xc06c
++#define mmCP_ME_MC_RADDR_LO                                                     0xc06d
++#define mmCP_ME_MC_RADDR_HI                                                     0xc06e
++#define mmCP_SEM_WAIT_TIMER                                                     0xc06f
++#define mmCP_SIG_SEM_ADDR_LO                                                    0xc070
++#define mmCP_SIG_SEM_ADDR_HI                                                    0xc071
++#define mmCP_SEM_INCOMPLETE_TIMER_CNTL                                          0xc072
++#define mmCP_WAIT_SEM_STATUS                                                    0xc073
++#define mmCP_WAIT_SEM_ADDR_LO                                                   0xc075
++#define mmCP_WAIT_SEM_ADDR_HI                                                   0xc076
++#define mmCP_WAIT_REG_MEM_TIMEOUT                                               0xc074
++#define mmCP_COHER_START_DELAY                                                  0xc07b
++#define mmCP_COHER_CNTL                                                         0xc07c
++#define mmCP_COHER_SIZE                                                         0xc07d
++#define mmCP_COHER_SIZE_HI                                                      0xc08c
++#define mmCP_COHER_BASE                                                         0xc07e
++#define mmCP_COHER_BASE_HI                                                      0xc079
++#define mmCP_COHER_STATUS                                                       0xc07f
++#define mmCOHER_DEST_BASE_0                                                     0xa092
++#define mmCOHER_DEST_BASE_1                                                     0xa093
++#define mmCOHER_DEST_BASE_2                                                     0xa07e
++#define mmCOHER_DEST_BASE_3                                                     0xa07f
++#define mmCOHER_DEST_BASE_HI_0                                                  0xa07a
++#define mmCOHER_DEST_BASE_HI_1                                                  0xa07b
++#define mmCOHER_DEST_BASE_HI_2                                                  0xa07c
++#define mmCOHER_DEST_BASE_HI_3                                                  0xa07d
++#define mmCP_DMA_ME_SRC_ADDR                                                    0xc080
++#define mmCP_DMA_ME_SRC_ADDR_HI                                                 0xc081
++#define mmCP_DMA_ME_DST_ADDR                                                    0xc082
++#define mmCP_DMA_ME_DST_ADDR_HI                                                 0xc083
++#define mmCP_DMA_ME_CONTROL                                                     0xc078
++#define mmCP_DMA_ME_COMMAND                                                     0xc084
++#define mmCP_DMA_PFP_SRC_ADDR                                                   0xc085
++#define mmCP_DMA_PFP_SRC_ADDR_HI                                                0xc086
++#define mmCP_DMA_PFP_DST_ADDR                                                   0xc087
++#define mmCP_DMA_PFP_DST_ADDR_HI                                                0xc088
++#define mmCP_DMA_PFP_CONTROL                                                    0xc077
++#define mmCP_DMA_PFP_COMMAND                                                    0xc089
++#define mmCP_DMA_CNTL                                                           0xc08a
++#define mmCP_DMA_READ_TAGS                                                      0xc08b
++#define mmCP_PFP_IB_CONTROL                                                     0xc08d
++#define mmCP_PFP_LOAD_CONTROL                                                   0xc08e
++#define mmCP_SCRATCH_INDEX                                                      0xc08f
++#define mmCP_SCRATCH_DATA                                                       0xc090
++#define mmCP_RB_OFFSET                                                          0xc091
++#define mmCP_IB1_OFFSET                                                         0xc092
++#define mmCP_IB2_OFFSET                                                         0xc093
++#define mmCP_IB1_PREAMBLE_BEGIN                                                 0xc094
++#define mmCP_IB1_PREAMBLE_END                                                   0xc095
++#define mmCP_IB2_PREAMBLE_BEGIN                                                 0xc096
++#define mmCP_IB2_PREAMBLE_END                                                   0xc097
++#define mmCP_STALLED_STAT1                                                      0x219d
++#define mmCP_STALLED_STAT2                                                      0x219e
++#define mmCP_STALLED_STAT3                                                      0x219c
++#define mmCP_BUSY_STAT                                                          0x219f
++#define mmCP_STAT                                                               0x21a0
++#define mmCP_ME_HEADER_DUMP                                                     0x21a1
++#define mmCP_PFP_HEADER_DUMP                                                    0x21a2
++#define mmCP_GRBM_FREE_COUNT                                                    0x21a3
++#define mmCP_CE_HEADER_DUMP                                                     0x21a4
++#define mmCP_MC_PACK_DELAY_CNT                                                  0x21a7
++#define mmCP_MC_TAG_CNTL                                                        0x21a8
++#define mmCP_MC_TAG_DATA                                                        0x21a9
++#define mmCP_CSF_STAT                                                           0x21b4
++#define mmCP_CSF_CNTL                                                           0x21b5
++#define mmCP_ME_CNTL                                                            0x21b6
++#define mmCP_CNTX_STAT                                                          0x21b8
++#define mmCP_ME_PREEMPTION                                                      0x21b9
++#define mmCP_RB0_RPTR                                                           0x21c0
++#define mmCP_RB_RPTR                                                            0x21c0
++#define mmCP_RB1_RPTR                                                           0x21bf
++#define mmCP_RB2_RPTR                                                           0x21be
++#define mmCP_RB_WPTR_DELAY                                                      0x21c1
++#define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
++#define mmCP_CE_INIT_BASE_LO                                                    0xc0c3
++#define mmCP_CE_INIT_BASE_HI                                                    0xc0c4
++#define mmCP_CE_INIT_BUFSZ                                                      0xc0c5
++#define mmCP_CE_IB1_BASE_LO                                                     0xc0c6
++#define mmCP_CE_IB1_BASE_HI                                                     0xc0c7
++#define mmCP_CE_IB1_BUFSZ                                                       0xc0c8
++#define mmCP_CE_IB2_BASE_LO                                                     0xc0c9
++#define mmCP_CE_IB2_BASE_HI                                                     0xc0ca
++#define mmCP_CE_IB2_BUFSZ                                                       0xc0cb
++#define mmCP_IB1_BASE_LO                                                        0xc0cc
++#define mmCP_IB1_BASE_HI                                                        0xc0cd
++#define mmCP_IB1_BUFSZ                                                          0xc0ce
++#define mmCP_IB2_BASE_LO                                                        0xc0cf
++#define mmCP_IB2_BASE_HI                                                        0xc0d0
++#define mmCP_IB2_BUFSZ                                                          0xc0d1
++#define mmCP_ST_BASE_LO                                                         0xc0d2
++#define mmCP_ST_BASE_HI                                                         0xc0d3
++#define mmCP_ST_BUFSZ                                                           0xc0d4
++#define mmCP_ROQ_THRESHOLDS                                                     0x21bc
++#define mmCP_MEQ_STQ_THRESHOLD                                                  0x21bd
++#define mmCP_ROQ1_THRESHOLDS                                                    0x21d5
++#define mmCP_ROQ2_THRESHOLDS                                                    0x21d6
++#define mmCP_STQ_THRESHOLDS                                                     0x21d7
++#define mmCP_QUEUE_THRESHOLDS                                                   0x21d8
++#define mmCP_MEQ_THRESHOLDS                                                     0x21d9
++#define mmCP_ROQ_AVAIL                                                          0x21da
++#define mmCP_STQ_AVAIL                                                          0x21db
++#define mmCP_ROQ2_AVAIL                                                         0x21dc
++#define mmCP_MEQ_AVAIL                                                          0x21dd
++#define mmCP_CMD_INDEX                                                          0x21de
++#define mmCP_CMD_DATA                                                           0x21df
++#define mmCP_ROQ_RB_STAT                                                        0x21e0
++#define mmCP_ROQ_IB1_STAT                                                       0x21e1
++#define mmCP_ROQ_IB2_STAT                                                       0x21e2
++#define mmCP_STQ_STAT                                                           0x21e3
++#define mmCP_STQ_WR_STAT                                                        0x21e4
++#define mmCP_MEQ_STAT                                                           0x21e5
++#define mmCP_CEQ1_AVAIL                                                         0x21e6
++#define mmCP_CEQ2_AVAIL                                                         0x21e7
++#define mmCP_CE_ROQ_RB_STAT                                                     0x21e8
++#define mmCP_CE_ROQ_IB1_STAT                                                    0x21e9
++#define mmCP_CE_ROQ_IB2_STAT                                                    0x21ea
++#define mmCP_INT_STAT_DEBUG                                                     0x21f7
++#define mmCP_PERFMON_CNTL                                                       0xd808
++#define mmCP_PERFMON_CNTX_CNTL                                                  0xa0d8
++#define mmCP_RINGID                                                             0xa0d9
++#define mmCP_PIPEID                                                             0xa0d9
++#define mmCP_VMID                                                               0xa0da
++#define mmCP_HPD_ROQ_OFFSETS                                                    0x3240
++#define mmCP_HPD_EOP_BASE_ADDR                                                  0x3241
++#define mmCP_HPD_EOP_BASE_ADDR_HI                                               0x3242
++#define mmCP_HPD_EOP_VMID                                                       0x3243
++#define mmCP_HPD_EOP_CONTROL                                                    0x3244
++#define mmCP_MQD_BASE_ADDR                                                      0x3245
++#define mmCP_MQD_BASE_ADDR_HI                                                   0x3246
++#define mmCP_HQD_ACTIVE                                                         0x3247
++#define mmCP_HQD_VMID                                                           0x3248
++#define mmCP_HQD_PERSISTENT_STATE                                               0x3249
++#define mmCP_HQD_PIPE_PRIORITY                                                  0x324a
++#define mmCP_HQD_QUEUE_PRIORITY                                                 0x324b
++#define mmCP_HQD_QUANTUM                                                        0x324c
++#define mmCP_HQD_PQ_BASE                                                        0x324d
++#define mmCP_HQD_PQ_BASE_HI                                                     0x324e
++#define mmCP_HQD_PQ_RPTR                                                        0x324f
++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
++#define mmCP_HQD_PQ_WPTR_POLL_ADDR                                              0x3252
++#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                                           0x3253
++#define mmCP_HQD_PQ_DOORBELL_CONTROL                                            0x3254
++#define mmCP_HQD_PQ_WPTR                                                        0x3255
++#define mmCP_HQD_PQ_CONTROL                                                     0x3256
++#define mmCP_HQD_IB_BASE_ADDR                                                   0x3257
++#define mmCP_HQD_IB_BASE_ADDR_HI                                                0x3258
++#define mmCP_HQD_IB_RPTR                                                        0x3259
++#define mmCP_HQD_IB_CONTROL                                                     0x325a
++#define mmCP_HQD_IQ_TIMER                                                       0x325b
++#define mmCP_HQD_IQ_RPTR                                                        0x325c
++#define mmCP_HQD_DEQUEUE_REQUEST                                                0x325d
++#define mmCP_HQD_DMA_OFFLOAD                                                    0x325e
++#define mmCP_HQD_SEMA_CMD                                                       0x325f
++#define mmCP_HQD_MSG_TYPE                                                       0x3260
++#define mmCP_HQD_ATOMIC0_PREOP_LO                                               0x3261
++#define mmCP_HQD_ATOMIC0_PREOP_HI                                               0x3262
++#define mmCP_HQD_ATOMIC1_PREOP_LO                                               0x3263
++#define mmCP_HQD_ATOMIC1_PREOP_HI                                               0x3264
++#define mmCP_HQD_HQ_SCHEDULER0                                                  0x3265
++#define mmCP_HQD_HQ_SCHEDULER1                                                  0x3266
++#define mmCP_MQD_CONTROL                                                        0x3267
++#define mmDB_Z_READ_BASE                                                        0xa012
++#define mmDB_STENCIL_READ_BASE                                                  0xa013
++#define mmDB_Z_WRITE_BASE                                                       0xa014
++#define mmDB_STENCIL_WRITE_BASE                                                 0xa015
++#define mmDB_DEPTH_INFO                                                         0xa00f
++#define mmDB_Z_INFO                                                             0xa010
++#define mmDB_STENCIL_INFO                                                       0xa011
++#define mmDB_DEPTH_SIZE                                                         0xa016
++#define mmDB_DEPTH_SLICE                                                        0xa017
++#define mmDB_DEPTH_VIEW                                                         0xa002
++#define mmDB_RENDER_CONTROL                                                     0xa000
++#define mmDB_COUNT_CONTROL                                                      0xa001
++#define mmDB_RENDER_OVERRIDE                                                    0xa003
++#define mmDB_RENDER_OVERRIDE2                                                   0xa004
++#define mmDB_EQAA                                                               0xa201
++#define mmDB_SHADER_CONTROL                                                     0xa203
++#define mmDB_DEPTH_BOUNDS_MIN                                                   0xa008
++#define mmDB_DEPTH_BOUNDS_MAX                                                   0xa009
++#define mmDB_STENCIL_CLEAR                                                      0xa00a
++#define mmDB_DEPTH_CLEAR                                                        0xa00b
++#define mmDB_HTILE_DATA_BASE                                                    0xa005
++#define mmDB_HTILE_SURFACE                                                      0xa2af
++#define mmDB_PRELOAD_CONTROL                                                    0xa2b2
++#define mmDB_STENCILREFMASK                                                     0xa10c
++#define mmDB_STENCILREFMASK_BF                                                  0xa10d
++#define mmDB_SRESULTS_COMPARE_STATE0                                            0xa2b0
++#define mmDB_SRESULTS_COMPARE_STATE1                                            0xa2b1
++#define mmDB_DEPTH_CONTROL                                                      0xa200
++#define mmDB_STENCIL_CONTROL                                                    0xa10b
++#define mmDB_ALPHA_TO_MASK                                                      0xa2dc
++#define mmDB_PERFCOUNTER0_SELECT                                                0xdc40
++#define mmDB_PERFCOUNTER1_SELECT                                                0xdc42
++#define mmDB_PERFCOUNTER2_SELECT                                                0xdc44
++#define mmDB_PERFCOUNTER3_SELECT                                                0xdc46
++#define mmDB_PERFCOUNTER0_SELECT1                                               0xdc41
++#define mmDB_PERFCOUNTER1_SELECT1                                               0xdc43
++#define mmDB_PERFCOUNTER0_LO                                                    0xd440
++#define mmDB_PERFCOUNTER1_LO                                                    0xd442
++#define mmDB_PERFCOUNTER2_LO                                                    0xd444
++#define mmDB_PERFCOUNTER3_LO                                                    0xd446
++#define mmDB_PERFCOUNTER0_HI                                                    0xd441
++#define mmDB_PERFCOUNTER1_HI                                                    0xd443
++#define mmDB_PERFCOUNTER2_HI                                                    0xd445
++#define mmDB_PERFCOUNTER3_HI                                                    0xd447
++#define mmDB_DEBUG                                                              0x260c
++#define mmDB_DEBUG2                                                             0x260d
++#define mmDB_DEBUG3                                                             0x260e
++#define mmDB_DEBUG4                                                             0x260f
++#define mmDB_CREDIT_LIMIT                                                       0x2614
++#define mmDB_WATERMARKS                                                         0x2615
++#define mmDB_SUBTILE_CONTROL                                                    0x2616
++#define mmDB_FREE_CACHELINES                                                    0x2617
++#define mmDB_FIFO_DEPTH1                                                        0x2618
++#define mmDB_FIFO_DEPTH2                                                        0x2619
++#define mmDB_CGTT_CLK_CTRL_0                                                    0xf0a4
++#define mmDB_ZPASS_COUNT_LOW                                                    0xc3fe
++#define mmDB_ZPASS_COUNT_HI                                                     0xc3ff
++#define mmDB_RING_CONTROL                                                       0x261b
++#define mmDB_READ_DEBUG_0                                                       0x2620
++#define mmDB_READ_DEBUG_1                                                       0x2621
++#define mmDB_READ_DEBUG_2                                                       0x2622
++#define mmDB_READ_DEBUG_3                                                       0x2623
++#define mmDB_READ_DEBUG_4                                                       0x2624
++#define mmDB_READ_DEBUG_5                                                       0x2625
++#define mmDB_READ_DEBUG_6                                                       0x2626
++#define mmDB_READ_DEBUG_7                                                       0x2627
++#define mmDB_READ_DEBUG_8                                                       0x2628
++#define mmDB_READ_DEBUG_9                                                       0x2629
++#define mmDB_READ_DEBUG_A                                                       0x262a
++#define mmDB_READ_DEBUG_B                                                       0x262b
++#define mmDB_READ_DEBUG_C                                                       0x262c
++#define mmDB_READ_DEBUG_D                                                       0x262d
++#define mmDB_READ_DEBUG_E                                                       0x262e
++#define mmDB_READ_DEBUG_F                                                       0x262f
++#define mmDB_OCCLUSION_COUNT0_LOW                                               0xc3c0
++#define mmDB_OCCLUSION_COUNT0_HI                                                0xc3c1
++#define mmDB_OCCLUSION_COUNT1_LOW                                               0xc3c2
++#define mmDB_OCCLUSION_COUNT1_HI                                                0xc3c3
++#define mmDB_OCCLUSION_COUNT2_LOW                                               0xc3c4
++#define mmDB_OCCLUSION_COUNT2_HI                                                0xc3c5
++#define mmDB_OCCLUSION_COUNT3_LOW                                               0xc3c6
++#define mmDB_OCCLUSION_COUNT3_HI                                                0xc3c7
++#define mmCC_RB_REDUNDANCY                                                      0x263c
++#define mmCC_RB_BACKEND_DISABLE                                                 0x263d
++#define mmGC_USER_RB_REDUNDANCY                                                 0x26de
++#define mmGC_USER_RB_BACKEND_DISABLE                                            0x26df
++#define mmGB_ADDR_CONFIG                                                        0x263e
++#define mmGB_BACKEND_MAP                                                        0x263f
++#define mmGB_GPU_ID                                                             0x2640
++#define mmCC_RB_DAISY_CHAIN                                                     0x2641
++#define mmGB_TILE_MODE0                                                         0x2644
++#define mmGB_TILE_MODE1                                                         0x2645
++#define mmGB_TILE_MODE2                                                         0x2646
++#define mmGB_TILE_MODE3                                                         0x2647
++#define mmGB_TILE_MODE4                                                         0x2648
++#define mmGB_TILE_MODE5                                                         0x2649
++#define mmGB_TILE_MODE6                                                         0x264a
++#define mmGB_TILE_MODE7                                                         0x264b
++#define mmGB_TILE_MODE8                                                         0x264c
++#define mmGB_TILE_MODE9                                                         0x264d
++#define mmGB_TILE_MODE10                                                        0x264e
++#define mmGB_TILE_MODE11                                                        0x264f
++#define mmGB_TILE_MODE12                                                        0x2650
++#define mmGB_TILE_MODE13                                                        0x2651
++#define mmGB_TILE_MODE14                                                        0x2652
++#define mmGB_TILE_MODE15                                                        0x2653
++#define mmGB_TILE_MODE16                                                        0x2654
++#define mmGB_TILE_MODE17                                                        0x2655
++#define mmGB_TILE_MODE18                                                        0x2656
++#define mmGB_TILE_MODE19                                                        0x2657
++#define mmGB_TILE_MODE20                                                        0x2658
++#define mmGB_TILE_MODE21                                                        0x2659
++#define mmGB_TILE_MODE22                                                        0x265a
++#define mmGB_TILE_MODE23                                                        0x265b
++#define mmGB_TILE_MODE24                                                        0x265c
++#define mmGB_TILE_MODE25                                                        0x265d
++#define mmGB_TILE_MODE26                                                        0x265e
++#define mmGB_TILE_MODE27                                                        0x265f
++#define mmGB_TILE_MODE28                                                        0x2660
++#define mmGB_TILE_MODE29                                                        0x2661
++#define mmGB_TILE_MODE30                                                        0x2662
++#define mmGB_TILE_MODE31                                                        0x2663
++#define mmGB_MACROTILE_MODE0                                                    0x2664
++#define mmGB_MACROTILE_MODE1                                                    0x2665
++#define mmGB_MACROTILE_MODE2                                                    0x2666
++#define mmGB_MACROTILE_MODE3                                                    0x2667
++#define mmGB_MACROTILE_MODE4                                                    0x2668
++#define mmGB_MACROTILE_MODE5                                                    0x2669
++#define mmGB_MACROTILE_MODE6                                                    0x266a
++#define mmGB_MACROTILE_MODE7                                                    0x266b
++#define mmGB_MACROTILE_MODE8                                                    0x266c
++#define mmGB_MACROTILE_MODE9                                                    0x266d
++#define mmGB_MACROTILE_MODE10                                                   0x266e
++#define mmGB_MACROTILE_MODE11                                                   0x266f
++#define mmGB_MACROTILE_MODE12                                                   0x2670
++#define mmGB_MACROTILE_MODE13                                                   0x2671
++#define mmGB_MACROTILE_MODE14                                                   0x2672
++#define mmGB_MACROTILE_MODE15                                                   0x2673
++#define mmGB_EDC_MODE                                                           0x307e
++#define mmCC_GC_EDC_CONFIG                                                      0x3098
++#define mmRAS_SIGNATURE_CONTROL                                                 0x3380
++#define mmRAS_SIGNATURE_MASK                                                    0x3381
++#define mmRAS_SX_SIGNATURE0                                                     0x3382
++#define mmRAS_SX_SIGNATURE1                                                     0x3383
++#define mmRAS_SX_SIGNATURE2                                                     0x3384
++#define mmRAS_SX_SIGNATURE3                                                     0x3385
++#define mmRAS_DB_SIGNATURE0                                                     0x338b
++#define mmRAS_PA_SIGNATURE0                                                     0x338c
++#define mmRAS_VGT_SIGNATURE0                                                    0x338d
++#define mmRAS_SQ_SIGNATURE0                                                     0x338e
++#define mmRAS_SC_SIGNATURE0                                                     0x338f
++#define mmRAS_SC_SIGNATURE1                                                     0x3390
++#define mmRAS_SC_SIGNATURE2                                                     0x3391
++#define mmRAS_SC_SIGNATURE3                                                     0x3392
++#define mmRAS_SC_SIGNATURE4                                                     0x3393
++#define mmRAS_SC_SIGNATURE5                                                     0x3394
++#define mmRAS_SC_SIGNATURE6                                                     0x3395
++#define mmRAS_SC_SIGNATURE7                                                     0x3396
++#define mmRAS_IA_SIGNATURE0                                                     0x3397
++#define mmRAS_IA_SIGNATURE1                                                     0x3398
++#define mmRAS_SPI_SIGNATURE0                                                    0x3399
++#define mmRAS_SPI_SIGNATURE1                                                    0x339a
++#define mmRAS_TA_SIGNATURE0                                                     0x339b
++#define mmRAS_TD_SIGNATURE0                                                     0x339c
++#define mmRAS_CB_SIGNATURE0                                                     0x339d
++#define mmRAS_BCI_SIGNATURE0                                                    0x339e
++#define mmRAS_BCI_SIGNATURE1                                                    0x339f
++#define mmGRBM_CAM_INDEX                                                        0x3000
++#define mmGRBM_CAM_DATA                                                         0x3001
++#define mmGRBM_CNTL                                                             0x2000
++#define mmGRBM_SKEW_CNTL                                                        0x2001
++#define mmGRBM_PWR_CNTL                                                         0x2003
++#define mmGRBM_STATUS                                                           0x2004
++#define mmGRBM_STATUS2                                                          0x2002
++#define mmGRBM_STATUS_SE0                                                       0x2005
++#define mmGRBM_STATUS_SE1                                                       0x2006
++#define mmGRBM_STATUS_SE2                                                       0x200e
++#define mmGRBM_STATUS_SE3                                                       0x200f
++#define mmGRBM_SOFT_RESET                                                       0x2008
++#define mmGRBM_DEBUG_CNTL                                                       0x2009
++#define mmGRBM_DEBUG_DATA                                                       0x200a
++#define mmGRBM_GFX_INDEX                                                        0xc200
++#define mmGRBM_GFX_CLKEN_CNTL                                                   0x200c
++#define mmGRBM_WAIT_IDLE_CLOCKS                                                 0x200d
++#define mmGRBM_DEBUG                                                            0x2014
++#define mmGRBM_DEBUG_SNAPSHOT                                                   0x2015
++#define mmGRBM_READ_ERROR                                                       0x2016
++#define mmGRBM_READ_ERROR2                                                      0x2017
++#define mmGRBM_INT_CNTL                                                         0x2018
++#define mmGRBM_PERFCOUNTER0_SELECT                                              0xd840
++#define mmGRBM_PERFCOUNTER1_SELECT                                              0xd841
++#define mmGRBM_SE0_PERFCOUNTER_SELECT                                           0xd842
++#define mmGRBM_SE1_PERFCOUNTER_SELECT                                           0xd843
++#define mmGRBM_SE2_PERFCOUNTER_SELECT                                           0xd844
++#define mmGRBM_SE3_PERFCOUNTER_SELECT                                           0xd845
++#define mmGRBM_PERFCOUNTER0_LO                                                  0xd040
++#define mmGRBM_PERFCOUNTER0_HI                                                  0xd041
++#define mmGRBM_PERFCOUNTER1_LO                                                  0xd043
++#define mmGRBM_PERFCOUNTER1_HI                                                  0xd044
++#define mmGRBM_SE0_PERFCOUNTER_LO                                               0xd045
++#define mmGRBM_SE0_PERFCOUNTER_HI                                               0xd046
++#define mmGRBM_SE1_PERFCOUNTER_LO                                               0xd047
++#define mmGRBM_SE1_PERFCOUNTER_HI                                               0xd048
++#define mmGRBM_SE2_PERFCOUNTER_LO                                               0xd049
++#define mmGRBM_SE2_PERFCOUNTER_HI                                               0xd04a
++#define mmGRBM_SE3_PERFCOUNTER_LO                                               0xd04b
++#define mmGRBM_SE3_PERFCOUNTER_HI                                               0xd04c
++#define mmGRBM_SCRATCH_REG0                                                     0x2040
++#define mmGRBM_SCRATCH_REG1                                                     0x2041
++#define mmGRBM_SCRATCH_REG2                                                     0x2042
++#define mmGRBM_SCRATCH_REG3                                                     0x2043
++#define mmGRBM_SCRATCH_REG4                                                     0x2044
++#define mmGRBM_SCRATCH_REG5                                                     0x2045
++#define mmGRBM_SCRATCH_REG6                                                     0x2046
++#define mmGRBM_SCRATCH_REG7                                                     0x2047
++#define mmDEBUG_INDEX                                                           0x203c
++#define mmDEBUG_DATA                                                            0x203d
++#define mmGRBM_NOWHERE                                                          0x203f
++#define mmPA_CL_VPORT_XSCALE                                                    0xa10f
++#define mmPA_CL_VPORT_XOFFSET                                                   0xa110
++#define mmPA_CL_VPORT_YSCALE                                                    0xa111
++#define mmPA_CL_VPORT_YOFFSET                                                   0xa112
++#define mmPA_CL_VPORT_ZSCALE                                                    0xa113
++#define mmPA_CL_VPORT_ZOFFSET                                                   0xa114
++#define mmPA_CL_VPORT_XSCALE_1                                                  0xa115
++#define mmPA_CL_VPORT_XSCALE_2                                                  0xa11b
++#define mmPA_CL_VPORT_XSCALE_3                                                  0xa121
++#define mmPA_CL_VPORT_XSCALE_4                                                  0xa127
++#define mmPA_CL_VPORT_XSCALE_5                                                  0xa12d
++#define mmPA_CL_VPORT_XSCALE_6                                                  0xa133
++#define mmPA_CL_VPORT_XSCALE_7                                                  0xa139
++#define mmPA_CL_VPORT_XSCALE_8                                                  0xa13f
++#define mmPA_CL_VPORT_XSCALE_9                                                  0xa145
++#define mmPA_CL_VPORT_XSCALE_10                                                 0xa14b
++#define mmPA_CL_VPORT_XSCALE_11                                                 0xa151
++#define mmPA_CL_VPORT_XSCALE_12                                                 0xa157
++#define mmPA_CL_VPORT_XSCALE_13                                                 0xa15d
++#define mmPA_CL_VPORT_XSCALE_14                                                 0xa163
++#define mmPA_CL_VPORT_XSCALE_15                                                 0xa169
++#define mmPA_CL_VPORT_XOFFSET_1                                                 0xa116
++#define mmPA_CL_VPORT_XOFFSET_2                                                 0xa11c
++#define mmPA_CL_VPORT_XOFFSET_3                                                 0xa122
++#define mmPA_CL_VPORT_XOFFSET_4                                                 0xa128
++#define mmPA_CL_VPORT_XOFFSET_5                                                 0xa12e
++#define mmPA_CL_VPORT_XOFFSET_6                                                 0xa134
++#define mmPA_CL_VPORT_XOFFSET_7                                                 0xa13a
++#define mmPA_CL_VPORT_XOFFSET_8                                                 0xa140
++#define mmPA_CL_VPORT_XOFFSET_9                                                 0xa146
++#define mmPA_CL_VPORT_XOFFSET_10                                                0xa14c
++#define mmPA_CL_VPORT_XOFFSET_11                                                0xa152
++#define mmPA_CL_VPORT_XOFFSET_12                                                0xa158
++#define mmPA_CL_VPORT_XOFFSET_13                                                0xa15e
++#define mmPA_CL_VPORT_XOFFSET_14                                                0xa164
++#define mmPA_CL_VPORT_XOFFSET_15                                                0xa16a
++#define mmPA_CL_VPORT_YSCALE_1                                                  0xa117
++#define mmPA_CL_VPORT_YSCALE_2                                                  0xa11d
++#define mmPA_CL_VPORT_YSCALE_3                                                  0xa123
++#define mmPA_CL_VPORT_YSCALE_4                                                  0xa129
++#define mmPA_CL_VPORT_YSCALE_5                                                  0xa12f
++#define mmPA_CL_VPORT_YSCALE_6                                                  0xa135
++#define mmPA_CL_VPORT_YSCALE_7                                                  0xa13b
++#define mmPA_CL_VPORT_YSCALE_8                                                  0xa141
++#define mmPA_CL_VPORT_YSCALE_9                                                  0xa147
++#define mmPA_CL_VPORT_YSCALE_10                                                 0xa14d
++#define mmPA_CL_VPORT_YSCALE_11                                                 0xa153
++#define mmPA_CL_VPORT_YSCALE_12                                                 0xa159
++#define mmPA_CL_VPORT_YSCALE_13                                                 0xa15f
++#define mmPA_CL_VPORT_YSCALE_14                                                 0xa165
++#define mmPA_CL_VPORT_YSCALE_15                                                 0xa16b
++#define mmPA_CL_VPORT_YOFFSET_1                                                 0xa118
++#define mmPA_CL_VPORT_YOFFSET_2                                                 0xa11e
++#define mmPA_CL_VPORT_YOFFSET_3                                                 0xa124
++#define mmPA_CL_VPORT_YOFFSET_4                                                 0xa12a
++#define mmPA_CL_VPORT_YOFFSET_5                                                 0xa130
++#define mmPA_CL_VPORT_YOFFSET_6                                                 0xa136
++#define mmPA_CL_VPORT_YOFFSET_7                                                 0xa13c
++#define mmPA_CL_VPORT_YOFFSET_8                                                 0xa142
++#define mmPA_CL_VPORT_YOFFSET_9                                                 0xa148
++#define mmPA_CL_VPORT_YOFFSET_10                                                0xa14e
++#define mmPA_CL_VPORT_YOFFSET_11                                                0xa154
++#define mmPA_CL_VPORT_YOFFSET_12                                                0xa15a
++#define mmPA_CL_VPORT_YOFFSET_13                                                0xa160
++#define mmPA_CL_VPORT_YOFFSET_14                                                0xa166
++#define mmPA_CL_VPORT_YOFFSET_15                                                0xa16c
++#define mmPA_CL_VPORT_ZSCALE_1                                                  0xa119
++#define mmPA_CL_VPORT_ZSCALE_2                                                  0xa11f
++#define mmPA_CL_VPORT_ZSCALE_3                                                  0xa125
++#define mmPA_CL_VPORT_ZSCALE_4                                                  0xa12b
++#define mmPA_CL_VPORT_ZSCALE_5                                                  0xa131
++#define mmPA_CL_VPORT_ZSCALE_6                                                  0xa137
++#define mmPA_CL_VPORT_ZSCALE_7                                                  0xa13d
++#define mmPA_CL_VPORT_ZSCALE_8                                                  0xa143
++#define mmPA_CL_VPORT_ZSCALE_9                                                  0xa149
++#define mmPA_CL_VPORT_ZSCALE_10                                                 0xa14f
++#define mmPA_CL_VPORT_ZSCALE_11                                                 0xa155
++#define mmPA_CL_VPORT_ZSCALE_12                                                 0xa15b
++#define mmPA_CL_VPORT_ZSCALE_13                                                 0xa161
++#define mmPA_CL_VPORT_ZSCALE_14                                                 0xa167
++#define mmPA_CL_VPORT_ZSCALE_15                                                 0xa16d
++#define mmPA_CL_VPORT_ZOFFSET_1                                                 0xa11a
++#define mmPA_CL_VPORT_ZOFFSET_2                                                 0xa120
++#define mmPA_CL_VPORT_ZOFFSET_3                                                 0xa126
++#define mmPA_CL_VPORT_ZOFFSET_4                                                 0xa12c
++#define mmPA_CL_VPORT_ZOFFSET_5                                                 0xa132
++#define mmPA_CL_VPORT_ZOFFSET_6                                                 0xa138
++#define mmPA_CL_VPORT_ZOFFSET_7                                                 0xa13e
++#define mmPA_CL_VPORT_ZOFFSET_8                                                 0xa144
++#define mmPA_CL_VPORT_ZOFFSET_9                                                 0xa14a
++#define mmPA_CL_VPORT_ZOFFSET_10                                                0xa150
++#define mmPA_CL_VPORT_ZOFFSET_11                                                0xa156
++#define mmPA_CL_VPORT_ZOFFSET_12                                                0xa15c
++#define mmPA_CL_VPORT_ZOFFSET_13                                                0xa162
++#define mmPA_CL_VPORT_ZOFFSET_14                                                0xa168
++#define mmPA_CL_VPORT_ZOFFSET_15                                                0xa16e
++#define mmPA_CL_VTE_CNTL                                                        0xa206
++#define mmPA_CL_VS_OUT_CNTL                                                     0xa207
++#define mmPA_CL_NANINF_CNTL                                                     0xa208
++#define mmPA_CL_CLIP_CNTL                                                       0xa204
++#define mmPA_CL_GB_VERT_CLIP_ADJ                                                0xa2fa
++#define mmPA_CL_GB_VERT_DISC_ADJ                                                0xa2fb
++#define mmPA_CL_GB_HORZ_CLIP_ADJ                                                0xa2fc
++#define mmPA_CL_GB_HORZ_DISC_ADJ                                                0xa2fd
++#define mmPA_CL_UCP_0_X                                                         0xa16f
++#define mmPA_CL_UCP_0_Y                                                         0xa170
++#define mmPA_CL_UCP_0_Z                                                         0xa171
++#define mmPA_CL_UCP_0_W                                                         0xa172
++#define mmPA_CL_UCP_1_X                                                         0xa173
++#define mmPA_CL_UCP_1_Y                                                         0xa174
++#define mmPA_CL_UCP_1_Z                                                         0xa175
++#define mmPA_CL_UCP_1_W                                                         0xa176
++#define mmPA_CL_UCP_2_X                                                         0xa177
++#define mmPA_CL_UCP_2_Y                                                         0xa178
++#define mmPA_CL_UCP_2_Z                                                         0xa179
++#define mmPA_CL_UCP_2_W                                                         0xa17a
++#define mmPA_CL_UCP_3_X                                                         0xa17b
++#define mmPA_CL_UCP_3_Y                                                         0xa17c
++#define mmPA_CL_UCP_3_Z                                                         0xa17d
++#define mmPA_CL_UCP_3_W                                                         0xa17e
++#define mmPA_CL_UCP_4_X                                                         0xa17f
++#define mmPA_CL_UCP_4_Y                                                         0xa180
++#define mmPA_CL_UCP_4_Z                                                         0xa181
++#define mmPA_CL_UCP_4_W                                                         0xa182
++#define mmPA_CL_UCP_5_X                                                         0xa183
++#define mmPA_CL_UCP_5_Y                                                         0xa184
++#define mmPA_CL_UCP_5_Z                                                         0xa185
++#define mmPA_CL_UCP_5_W                                                         0xa186
++#define mmPA_CL_POINT_X_RAD                                                     0xa1f5
++#define mmPA_CL_POINT_Y_RAD                                                     0xa1f6
++#define mmPA_CL_POINT_SIZE                                                      0xa1f7
++#define mmPA_CL_POINT_CULL_RAD                                                  0xa1f8
++#define mmPA_CL_ENHANCE                                                         0x2285
++#define mmPA_CL_RESET_DEBUG                                                     0x2286
++#define mmPA_SU_VTX_CNTL                                                        0xa2f9
++#define mmPA_SU_POINT_SIZE                                                      0xa280
++#define mmPA_SU_POINT_MINMAX                                                    0xa281
++#define mmPA_SU_LINE_CNTL                                                       0xa282
++#define mmPA_SU_LINE_STIPPLE_CNTL                                               0xa209
++#define mmPA_SU_LINE_STIPPLE_SCALE                                              0xa20a
++#define mmPA_SU_PRIM_FILTER_CNTL                                                0xa20b
++#define mmPA_SU_SC_MODE_CNTL                                                    0xa205
++#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                                         0xa2de
++#define mmPA_SU_POLY_OFFSET_CLAMP                                               0xa2df
++#define mmPA_SU_POLY_OFFSET_FRONT_SCALE                                         0xa2e0
++#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                                        0xa2e1
++#define mmPA_SU_POLY_OFFSET_BACK_SCALE                                          0xa2e2
++#define mmPA_SU_POLY_OFFSET_BACK_OFFSET                                         0xa2e3
++#define mmPA_SU_HARDWARE_SCREEN_OFFSET                                          0xa08d
++#define mmPA_SU_LINE_STIPPLE_VALUE                                              0xc280
++#define mmPA_SU_PERFCOUNTER0_SELECT                                             0xd900
++#define mmPA_SU_PERFCOUNTER0_SELECT1                                            0xd901
++#define mmPA_SU_PERFCOUNTER1_SELECT                                             0xd902
++#define mmPA_SU_PERFCOUNTER1_SELECT1                                            0xd903
++#define mmPA_SU_PERFCOUNTER2_SELECT                                             0xd904
++#define mmPA_SU_PERFCOUNTER3_SELECT                                             0xd905
++#define mmPA_SU_PERFCOUNTER0_LO                                                 0xd100
++#define mmPA_SU_PERFCOUNTER0_HI                                                 0xd101
++#define mmPA_SU_PERFCOUNTER1_LO                                                 0xd102
++#define mmPA_SU_PERFCOUNTER1_HI                                                 0xd103
++#define mmPA_SU_PERFCOUNTER2_LO                                                 0xd104
++#define mmPA_SU_PERFCOUNTER2_HI                                                 0xd105
++#define mmPA_SU_PERFCOUNTER3_LO                                                 0xd106
++#define mmPA_SU_PERFCOUNTER3_HI                                                 0xd107
++#define mmPA_SC_AA_CONFIG                                                       0xa2f8
++#define mmPA_SC_AA_MASK_X0Y0_X1Y0                                               0xa30e
++#define mmPA_SC_AA_MASK_X0Y1_X1Y1                                               0xa30f
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                     0xa2fe
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                     0xa2ff
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                     0xa300
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                     0xa301
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                     0xa302
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                     0xa303
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                     0xa304
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                     0xa305
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                     0xa306
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                     0xa307
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                     0xa308
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                     0xa309
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                     0xa30a
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                     0xa30b
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                     0xa30c
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                     0xa30d
++#define mmPA_SC_CENTROID_PRIORITY_0                                             0xa2f5
++#define mmPA_SC_CENTROID_PRIORITY_1                                             0xa2f6
++#define mmPA_SC_CLIPRECT_0_TL                                                   0xa084
++#define mmPA_SC_CLIPRECT_0_BR                                                   0xa085
++#define mmPA_SC_CLIPRECT_1_TL                                                   0xa086
++#define mmPA_SC_CLIPRECT_1_BR                                                   0xa087
++#define mmPA_SC_CLIPRECT_2_TL                                                   0xa088
++#define mmPA_SC_CLIPRECT_2_BR                                                   0xa089
++#define mmPA_SC_CLIPRECT_3_TL                                                   0xa08a
++#define mmPA_SC_CLIPRECT_3_BR                                                   0xa08b
++#define mmPA_SC_CLIPRECT_RULE                                                   0xa083
++#define mmPA_SC_EDGERULE                                                        0xa08c
++#define mmPA_SC_LINE_CNTL                                                       0xa2f7
++#define mmPA_SC_LINE_STIPPLE                                                    0xa283
++#define mmPA_SC_MODE_CNTL_0                                                     0xa292
++#define mmPA_SC_MODE_CNTL_1                                                     0xa293
++#define mmPA_SC_RASTER_CONFIG                                                   0xa0d4
++#define mmPA_SC_RASTER_CONFIG_1                                                 0xa0d5
++#define mmPA_SC_SCREEN_EXTENT_CONTROL                                           0xa0d6
++#define mmPA_SC_GENERIC_SCISSOR_TL                                              0xa090
++#define mmPA_SC_GENERIC_SCISSOR_BR                                              0xa091
++#define mmPA_SC_SCREEN_SCISSOR_TL                                               0xa00c
++#define mmPA_SC_SCREEN_SCISSOR_BR                                               0xa00d
++#define mmPA_SC_WINDOW_OFFSET                                                   0xa080
++#define mmPA_SC_WINDOW_SCISSOR_TL                                               0xa081
++#define mmPA_SC_WINDOW_SCISSOR_BR                                               0xa082
++#define mmPA_SC_VPORT_SCISSOR_0_TL                                              0xa094
++#define mmPA_SC_VPORT_SCISSOR_1_TL                                              0xa096
++#define mmPA_SC_VPORT_SCISSOR_2_TL                                              0xa098
++#define mmPA_SC_VPORT_SCISSOR_3_TL                                              0xa09a
++#define mmPA_SC_VPORT_SCISSOR_4_TL                                              0xa09c
++#define mmPA_SC_VPORT_SCISSOR_5_TL                                              0xa09e
++#define mmPA_SC_VPORT_SCISSOR_6_TL                                              0xa0a0
++#define mmPA_SC_VPORT_SCISSOR_7_TL                                              0xa0a2
++#define mmPA_SC_VPORT_SCISSOR_8_TL                                              0xa0a4
++#define mmPA_SC_VPORT_SCISSOR_9_TL                                              0xa0a6
++#define mmPA_SC_VPORT_SCISSOR_10_TL                                             0xa0a8
++#define mmPA_SC_VPORT_SCISSOR_11_TL                                             0xa0aa
++#define mmPA_SC_VPORT_SCISSOR_12_TL                                             0xa0ac
++#define mmPA_SC_VPORT_SCISSOR_13_TL                                             0xa0ae
++#define mmPA_SC_VPORT_SCISSOR_14_TL                                             0xa0b0
++#define mmPA_SC_VPORT_SCISSOR_15_TL                                             0xa0b2
++#define mmPA_SC_VPORT_SCISSOR_0_BR                                              0xa095
++#define mmPA_SC_VPORT_SCISSOR_1_BR                                              0xa097
++#define mmPA_SC_VPORT_SCISSOR_2_BR                                              0xa099
++#define mmPA_SC_VPORT_SCISSOR_3_BR                                              0xa09b
++#define mmPA_SC_VPORT_SCISSOR_4_BR                                              0xa09d
++#define mmPA_SC_VPORT_SCISSOR_5_BR                                              0xa09f
++#define mmPA_SC_VPORT_SCISSOR_6_BR                                              0xa0a1
++#define mmPA_SC_VPORT_SCISSOR_7_BR                                              0xa0a3
++#define mmPA_SC_VPORT_SCISSOR_8_BR                                              0xa0a5
++#define mmPA_SC_VPORT_SCISSOR_9_BR                                              0xa0a7
++#define mmPA_SC_VPORT_SCISSOR_10_BR                                             0xa0a9
++#define mmPA_SC_VPORT_SCISSOR_11_BR                                             0xa0ab
++#define mmPA_SC_VPORT_SCISSOR_12_BR                                             0xa0ad
++#define mmPA_SC_VPORT_SCISSOR_13_BR                                             0xa0af
++#define mmPA_SC_VPORT_SCISSOR_14_BR                                             0xa0b1
++#define mmPA_SC_VPORT_SCISSOR_15_BR                                             0xa0b3
++#define mmPA_SC_VPORT_ZMIN_0                                                    0xa0b4
++#define mmPA_SC_VPORT_ZMIN_1                                                    0xa0b6
++#define mmPA_SC_VPORT_ZMIN_2                                                    0xa0b8
++#define mmPA_SC_VPORT_ZMIN_3                                                    0xa0ba
++#define mmPA_SC_VPORT_ZMIN_4                                                    0xa0bc
++#define mmPA_SC_VPORT_ZMIN_5                                                    0xa0be
++#define mmPA_SC_VPORT_ZMIN_6                                                    0xa0c0
++#define mmPA_SC_VPORT_ZMIN_7                                                    0xa0c2
++#define mmPA_SC_VPORT_ZMIN_8                                                    0xa0c4
++#define mmPA_SC_VPORT_ZMIN_9                                                    0xa0c6
++#define mmPA_SC_VPORT_ZMIN_10                                                   0xa0c8
++#define mmPA_SC_VPORT_ZMIN_11                                                   0xa0ca
++#define mmPA_SC_VPORT_ZMIN_12                                                   0xa0cc
++#define mmPA_SC_VPORT_ZMIN_13                                                   0xa0ce
++#define mmPA_SC_VPORT_ZMIN_14                                                   0xa0d0
++#define mmPA_SC_VPORT_ZMIN_15                                                   0xa0d2
++#define mmPA_SC_VPORT_ZMAX_0                                                    0xa0b5
++#define mmPA_SC_VPORT_ZMAX_1                                                    0xa0b7
++#define mmPA_SC_VPORT_ZMAX_2                                                    0xa0b9
++#define mmPA_SC_VPORT_ZMAX_3                                                    0xa0bb
++#define mmPA_SC_VPORT_ZMAX_4                                                    0xa0bd
++#define mmPA_SC_VPORT_ZMAX_5                                                    0xa0bf
++#define mmPA_SC_VPORT_ZMAX_6                                                    0xa0c1
++#define mmPA_SC_VPORT_ZMAX_7                                                    0xa0c3
++#define mmPA_SC_VPORT_ZMAX_8                                                    0xa0c5
++#define mmPA_SC_VPORT_ZMAX_9                                                    0xa0c7
++#define mmPA_SC_VPORT_ZMAX_10                                                   0xa0c9
++#define mmPA_SC_VPORT_ZMAX_11                                                   0xa0cb
++#define mmPA_SC_VPORT_ZMAX_12                                                   0xa0cd
++#define mmPA_SC_VPORT_ZMAX_13                                                   0xa0cf
++#define mmPA_SC_VPORT_ZMAX_14                                                   0xa0d1
++#define mmPA_SC_VPORT_ZMAX_15                                                   0xa0d3
++#define mmPA_SC_ENHANCE                                                         0x22fc
++#define mmPA_SC_FIFO_SIZE                                                       0x22f3
++#define mmPA_SC_IF_FIFO_SIZE                                                    0x22f5
++#define mmPA_SC_FORCE_EOV_MAX_CNTS                                              0x22c9
++#define mmPA_SC_LINE_STIPPLE_STATE                                              0xc281
++#define mmPA_SC_SCREEN_EXTENT_MIN_0                                             0xc284
++#define mmPA_SC_SCREEN_EXTENT_MAX_0                                             0xc285
++#define mmPA_SC_SCREEN_EXTENT_MIN_1                                             0xc286
++#define mmPA_SC_SCREEN_EXTENT_MAX_1                                             0xc28b
++#define mmPA_SC_PERFCOUNTER0_SELECT                                             0xd940
++#define mmPA_SC_PERFCOUNTER0_SELECT1                                            0xd941
++#define mmPA_SC_PERFCOUNTER1_SELECT                                             0xd942
++#define mmPA_SC_PERFCOUNTER2_SELECT                                             0xd943
++#define mmPA_SC_PERFCOUNTER3_SELECT                                             0xd944
++#define mmPA_SC_PERFCOUNTER4_SELECT                                             0xd945
++#define mmPA_SC_PERFCOUNTER5_SELECT                                             0xd946
++#define mmPA_SC_PERFCOUNTER6_SELECT                                             0xd947
++#define mmPA_SC_PERFCOUNTER7_SELECT                                             0xd948
++#define mmPA_SC_PERFCOUNTER0_LO                                                 0xd140
++#define mmPA_SC_PERFCOUNTER0_HI                                                 0xd141
++#define mmPA_SC_PERFCOUNTER1_LO                                                 0xd142
++#define mmPA_SC_PERFCOUNTER1_HI                                                 0xd143
++#define mmPA_SC_PERFCOUNTER2_LO                                                 0xd144
++#define mmPA_SC_PERFCOUNTER2_HI                                                 0xd145
++#define mmPA_SC_PERFCOUNTER3_LO                                                 0xd146
++#define mmPA_SC_PERFCOUNTER3_HI                                                 0xd147
++#define mmPA_SC_PERFCOUNTER4_LO                                                 0xd148
++#define mmPA_SC_PERFCOUNTER4_HI                                                 0xd149
++#define mmPA_SC_PERFCOUNTER5_LO                                                 0xd14a
++#define mmPA_SC_PERFCOUNTER5_HI                                                 0xd14b
++#define mmPA_SC_PERFCOUNTER6_LO                                                 0xd14c
++#define mmPA_SC_PERFCOUNTER6_HI                                                 0xd14d
++#define mmPA_SC_PERFCOUNTER7_LO                                                 0xd14e
++#define mmPA_SC_PERFCOUNTER7_HI                                                 0xd14f
++#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN                                           0xc2a0
++#define mmPA_SC_P3D_TRAP_SCREEN_H                                               0xc2a1
++#define mmPA_SC_P3D_TRAP_SCREEN_V                                               0xc2a2
++#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                      0xc2a3
++#define mmPA_SC_P3D_TRAP_SCREEN_COUNT                                           0xc2a4
++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                                          0xc2a8
++#define mmPA_SC_HP3D_TRAP_SCREEN_H                                              0xc2a9
++#define mmPA_SC_HP3D_TRAP_SCREEN_V                                              0xc2aa
++#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                     0xc2ab
++#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT                                          0xc2ac
++#define mmPA_SC_TRAP_SCREEN_HV_EN                                               0xc2b0
++#define mmPA_SC_TRAP_SCREEN_H                                                   0xc2b1
++#define mmPA_SC_TRAP_SCREEN_V                                                   0xc2b2
++#define mmPA_SC_TRAP_SCREEN_OCCURRENCE                                          0xc2b3
++#define mmPA_SC_TRAP_SCREEN_COUNT                                               0xc2b4
++#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                         0x22c0
++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                        0x22c1
++#define mmPA_SC_TRAP_SCREEN_HV_LOCK                                             0x22c2
++#define mmPA_CL_CNTL_STATUS                                                     0x2284
++#define mmPA_SU_CNTL_STATUS                                                     0x2294
++#define mmPA_SC_FIFO_DEPTH_CNTL                                                 0x2295
++#define mmCGTT_PA_CLK_CTRL                                                      0xf088
++#define mmCGTT_SC_CLK_CTRL                                                      0xf089
++#define mmPA_SU_DEBUG_CNTL                                                      0x2280
++#define mmPA_SU_DEBUG_DATA                                                      0x2281
++#define mmPA_SC_DEBUG_CNTL                                                      0x22f6
++#define mmPA_SC_DEBUG_DATA                                                      0x22f7
++#define ixCLIPPER_DEBUG_REG00                                                   0x0
++#define ixCLIPPER_DEBUG_REG01                                                   0x1
++#define ixCLIPPER_DEBUG_REG02                                                   0x2
++#define ixCLIPPER_DEBUG_REG03                                                   0x3
++#define ixCLIPPER_DEBUG_REG04                                                   0x4
++#define ixCLIPPER_DEBUG_REG05                                                   0x5
++#define ixCLIPPER_DEBUG_REG06                                                   0x6
++#define ixCLIPPER_DEBUG_REG07                                                   0x7
++#define ixCLIPPER_DEBUG_REG08                                                   0x8
++#define ixCLIPPER_DEBUG_REG09                                                   0x9
++#define ixCLIPPER_DEBUG_REG10                                                   0xa
++#define ixCLIPPER_DEBUG_REG11                                                   0xb
++#define ixCLIPPER_DEBUG_REG12                                                   0xc
++#define ixCLIPPER_DEBUG_REG13                                                   0xd
++#define ixCLIPPER_DEBUG_REG14                                                   0xe
++#define ixCLIPPER_DEBUG_REG15                                                   0xf
++#define ixCLIPPER_DEBUG_REG16                                                   0x10
++#define ixCLIPPER_DEBUG_REG17                                                   0x11
++#define ixCLIPPER_DEBUG_REG18                                                   0x12
++#define ixCLIPPER_DEBUG_REG19                                                   0x13
++#define ixSXIFCCG_DEBUG_REG0                                                    0x14
++#define ixSXIFCCG_DEBUG_REG1                                                    0x15
++#define ixSXIFCCG_DEBUG_REG2                                                    0x16
++#define ixSXIFCCG_DEBUG_REG3                                                    0x17
++#define ixSETUP_DEBUG_REG0                                                      0x18
++#define ixSETUP_DEBUG_REG1                                                      0x19
++#define ixSETUP_DEBUG_REG2                                                      0x1a
++#define ixSETUP_DEBUG_REG3                                                      0x1b
++#define ixSETUP_DEBUG_REG4                                                      0x1c
++#define ixSETUP_DEBUG_REG5                                                      0x1d
++#define ixPA_SC_DEBUG_REG0                                                      0x0
++#define ixPA_SC_DEBUG_REG1                                                      0x1
++#define mmCOMPUTE_DISPATCH_INITIATOR                                            0x2e00
++#define mmCOMPUTE_DIM_X                                                         0x2e01
++#define mmCOMPUTE_DIM_Y                                                         0x2e02
++#define mmCOMPUTE_DIM_Z                                                         0x2e03
++#define mmCOMPUTE_START_X                                                       0x2e04
++#define mmCOMPUTE_START_Y                                                       0x2e05
++#define mmCOMPUTE_START_Z                                                       0x2e06
++#define mmCOMPUTE_NUM_THREAD_X                                                  0x2e07
++#define mmCOMPUTE_NUM_THREAD_Y                                                  0x2e08
++#define mmCOMPUTE_NUM_THREAD_Z                                                  0x2e09
++#define mmCOMPUTE_PIPELINESTAT_ENABLE                                           0x2e0a
++#define mmCOMPUTE_PERFCOUNT_ENABLE                                              0x2e0b
++#define mmCOMPUTE_PGM_LO                                                        0x2e0c
++#define mmCOMPUTE_PGM_HI                                                        0x2e0d
++#define mmCOMPUTE_TBA_LO                                                        0x2e0e
++#define mmCOMPUTE_TBA_HI                                                        0x2e0f
++#define mmCOMPUTE_TMA_LO                                                        0x2e10
++#define mmCOMPUTE_TMA_HI                                                        0x2e11
++#define mmCOMPUTE_PGM_RSRC1                                                     0x2e12
++#define mmCOMPUTE_PGM_RSRC2                                                     0x2e13
++#define mmCOMPUTE_VMID                                                          0x2e14
++#define mmCOMPUTE_RESOURCE_LIMITS                                               0x2e15
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                                        0x2e16
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                                        0x2e17
++#define mmCOMPUTE_TMPRING_SIZE                                                  0x2e18
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2                                        0x2e19
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3                                        0x2e1a
++#define mmCOMPUTE_RESTART_X                                                     0x2e1b
++#define mmCOMPUTE_RESTART_Y                                                     0x2e1c
++#define mmCOMPUTE_RESTART_Z                                                     0x2e1d
++#define mmCOMPUTE_THREAD_TRACE_ENABLE                                           0x2e1e
++#define mmCOMPUTE_MISC_RESERVED                                                 0x2e1f
++#define mmCOMPUTE_USER_DATA_0                                                   0x2e40
++#define mmCOMPUTE_USER_DATA_1                                                   0x2e41
++#define mmCOMPUTE_USER_DATA_2                                                   0x2e42
++#define mmCOMPUTE_USER_DATA_3                                                   0x2e43
++#define mmCOMPUTE_USER_DATA_4                                                   0x2e44
++#define mmCOMPUTE_USER_DATA_5                                                   0x2e45
++#define mmCOMPUTE_USER_DATA_6                                                   0x2e46
++#define mmCOMPUTE_USER_DATA_7                                                   0x2e47
++#define mmCOMPUTE_USER_DATA_8                                                   0x2e48
++#define mmCOMPUTE_USER_DATA_9                                                   0x2e49
++#define mmCOMPUTE_USER_DATA_10                                                  0x2e4a
++#define mmCOMPUTE_USER_DATA_11                                                  0x2e4b
++#define mmCOMPUTE_USER_DATA_12                                                  0x2e4c
++#define mmCOMPUTE_USER_DATA_13                                                  0x2e4d
++#define mmCOMPUTE_USER_DATA_14                                                  0x2e4e
++#define mmCOMPUTE_USER_DATA_15                                                  0x2e4f
++#define mmCSPRIV_CONNECT                                                        0x0
++#define mmCSPRIV_THREAD_TRACE_TG0                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG1                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG2                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG3                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_EVENT                                             0x1f
++#define mmRLC_CNTL                                                              0x30c0
++#define mmRLC_DEBUG_SELECT                                                      0x30c1
++#define mmRLC_DEBUG                                                             0x30c2
++#define mmRLC_MC_CNTL                                                           0x30c3
++#define mmRLC_STAT                                                              0x30c4
++#define mmRLC_SAFE_MODE                                                         0x313a
++#define mmRLC_SOFT_RESET_GPU                                                    0x30c5
++#define mmRLC_MEM_SLP_CNTL                                                      0x30c6
++#define mmRLC_PERFMON_CNTL                                                      0xdcc0
++#define mmRLC_PERFCOUNTER0_SELECT                                               0xdcc1
++#define mmRLC_PERFCOUNTER1_SELECT                                               0xdcc2
++#define mmRLC_PERFCOUNTER0_LO                                                   0xd480
++#define mmRLC_PERFCOUNTER1_LO                                                   0xd482
++#define mmRLC_PERFCOUNTER0_HI                                                   0xd481
++#define mmRLC_PERFCOUNTER1_HI                                                   0xd483
++#define mmCGTT_RLC_CLK_CTRL                                                     0xf0b8
++#define mmRLC_LB_CNTL                                                           0x30d9
++#define mmRLC_LB_CNTR_MAX                                                       0x30d2
++#define mmRLC_LB_CNTR_INIT                                                      0x30db
++#define mmRLC_LOAD_BALANCE_CNTR                                                 0x30dc
++#define mmRLC_SAVE_AND_RESTORE_BASE                                             0x30dd
++#define mmRLC_JUMP_TABLE_RESTORE                                                0x30de
++#define mmRLC_DRIVER_CPDMA_STATUS                                               0x30de
++#define mmRLC_PG_DELAY_2                                                        0x30df
++#define mmRLC_GPM_DEBUG_SELECT                                                  0x30e0
++#define mmRLC_GPM_DEBUG                                                         0x30e1
++#define mmRLC_GPM_UCODE_ADDR                                                    0x30e2
++#define mmRLC_GPM_UCODE_DATA                                                    0x30e3
++#define mmRLC_GPU_CLOCK_COUNT_LSB                                               0x30e4
++#define mmRLC_GPU_CLOCK_COUNT_MSB                                               0x30e5
++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT                                           0x30e6
++#define mmRLC_UCODE_CNTL                                                        0x30e7
++#define mmRLC_GPM_STAT                                                          0x3100
++#define mmRLC_GPU_CLOCK_32_RES_SEL                                              0x3101
++#define mmRLC_GPU_CLOCK_32                                                      0x3102
++#define mmRLC_PG_CNTL                                                           0x3103
++#define mmRLC_GPM_THREAD_PRIORITY                                               0x3104
++#define mmRLC_GPM_THREAD_ENABLE                                                 0x3105
++#define mmRLC_GPM_VMID_THREAD0                                                  0x3106
++#define mmRLC_GPM_VMID_THREAD1                                                  0x3107
++#define mmRLC_CGTT_MGCG_OVERRIDE                                                0x3108
++#define mmRLC_CGCG_CGLS_CTRL                                                    0x3109
++#define mmRLC_CGCG_RAMP_CTRL                                                    0x310a
++#define mmRLC_DYN_PG_STATUS                                                     0x310b
++#define mmRLC_DYN_PG_REQUEST                                                    0x310c
++#define mmRLC_PG_DELAY                                                          0x310d
++#define mmRLC_CU_STATUS                                                         0x310e
++#define mmRLC_LB_INIT_CU_MASK                                                   0x310f
++#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK                                          0x3110
++#define mmRLC_LB_PARAMS                                                         0x3111
++#define mmRLC_THREAD1_DELAY                                                     0x3112
++#define mmRLC_PG_ALWAYS_ON_CU_MASK                                              0x3113
++#define mmRLC_MAX_PG_CU                                                         0x3114
++#define mmRLC_AUTO_PG_CTRL                                                      0x3115
++#define mmRLC_SMU_GRBM_REG_SAVE_CTRL                                            0x3116
++#define mmRLC_SMU_PG_CTRL                                                       0x3117
++#define mmRLC_SMU_PG_WAKE_UP_CTRL                                               0x3118
++#define mmRLC_SERDES_RD_MASTER_INDEX                                            0x3119
++#define mmRLC_SERDES_RD_DATA_0                                                  0x311a
++#define mmRLC_SERDES_RD_DATA_1                                                  0x311b
++#define mmRLC_SERDES_RD_DATA_2                                                  0x311c
++#define mmRLC_SERDES_WR_CU_MASTER_MASK                                          0x311d
++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK                                       0x311e
++#define mmRLC_SERDES_WR_CTRL                                                    0x311f
++#define mmRLC_SERDES_WR_DATA                                                    0x3120
++#define mmRLC_SERDES_CU_MASTER_BUSY                                             0x3121
++#define mmRLC_SERDES_NONCU_MASTER_BUSY                                          0x3122
++#define mmRLC_GPM_GENERAL_0                                                     0x3123
++#define mmRLC_GPM_GENERAL_1                                                     0x3124
++#define mmRLC_GPM_GENERAL_2                                                     0x3125
++#define mmRLC_GPM_GENERAL_3                                                     0x3126
++#define mmRLC_GPM_GENERAL_4                                                     0x3127
++#define mmRLC_GPM_GENERAL_5                                                     0x3128
++#define mmRLC_GPM_GENERAL_6                                                     0x3129
++#define mmRLC_GPM_GENERAL_7                                                     0x312a
++#define mmRLC_GPM_CU_PD_TIMEOUT                                                 0x312b
++#define mmRLC_GPM_SCRATCH_ADDR                                                  0x312c
++#define mmRLC_GPM_SCRATCH_DATA                                                  0x312d
++#define mmRLC_STATIC_PG_STATUS                                                  0x312e
++#define mmRLC_GPM_PERF_COUNT_0                                                  0x312f
++#define mmRLC_GPM_PERF_COUNT_1                                                  0x3130
++#define mmRLC_GPR_REG1                                                          0x3139
++#define mmRLC_GPR_REG2                                                          0x313a
++#define mmRLC_SPM_VMID                                                          0x3131
++#define mmRLC_SPM_INT_CNTL                                                      0x3132
++#define mmRLC_SPM_INT_STATUS                                                    0x3133
++#define mmRLC_SPM_DEBUG_SELECT                                                  0x3134
++#define mmRLC_SPM_DEBUG                                                         0x3135
++#define mmRLC_GPM_LOG_ADDR                                                      0x3136
++#define mmRLC_GPM_LOG_SIZE                                                      0x3137
++#define mmRLC_GPM_LOG_CONT                                                      0x3138
++#define mmRLC_SPM_PERFMON_CNTL                                                  0xdc80
++#define mmRLC_SPM_PERFMON_RING_BASE_LO                                          0xdc81
++#define mmRLC_SPM_PERFMON_RING_BASE_HI                                          0xdc82
++#define mmRLC_SPM_PERFMON_RING_SIZE                                             0xdc83
++#define mmRLC_SPM_PERFMON_SEGMENT_SIZE                                          0xdc84
++#define mmRLC_SPM_SE_MUXSEL_ADDR                                                0xdc85
++#define mmRLC_SPM_SE_MUXSEL_DATA                                                0xdc86
++#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY                                      0xdc87
++#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY                                      0xdc88
++#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY                                      0xdc89
++#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY                                       0xdc8a
++#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY                                       0xdc8b
++#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY                                       0xdc8c
++#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY                                      0xdc8d
++#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY                                       0xdc8e
++#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY                                       0xdc90
++#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY                                      0xdc91
++#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY                                      0xdc92
++#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY                                      0xdc93
++#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY                                       0xdc94
++#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY                                       0xdc95
++#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY                                      0xdc96
++#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY                                      0xdc97
++#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY                                      0xdc98
++#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY                                      0xdc99
++#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY                                       0xdc9a
++#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR                                            0xdc9b
++#define mmRLC_SPM_GLOBAL_MUXSEL_DATA                                            0xdc9c
++#define mmRLC_SPM_RING_RDPTR                                                    0xdc9d
++#define mmRLC_SPM_SEGMENT_THRESHOLD                                             0xdc9e
++#define mmSPI_PS_INPUT_CNTL_0                                                   0xa191
++#define mmSPI_PS_INPUT_CNTL_1                                                   0xa192
++#define mmSPI_PS_INPUT_CNTL_2                                                   0xa193
++#define mmSPI_PS_INPUT_CNTL_3                                                   0xa194
++#define mmSPI_PS_INPUT_CNTL_4                                                   0xa195
++#define mmSPI_PS_INPUT_CNTL_5                                                   0xa196
++#define mmSPI_PS_INPUT_CNTL_6                                                   0xa197
++#define mmSPI_PS_INPUT_CNTL_7                                                   0xa198
++#define mmSPI_PS_INPUT_CNTL_8                                                   0xa199
++#define mmSPI_PS_INPUT_CNTL_9                                                   0xa19a
++#define mmSPI_PS_INPUT_CNTL_10                                                  0xa19b
++#define mmSPI_PS_INPUT_CNTL_11                                                  0xa19c
++#define mmSPI_PS_INPUT_CNTL_12                                                  0xa19d
++#define mmSPI_PS_INPUT_CNTL_13                                                  0xa19e
++#define mmSPI_PS_INPUT_CNTL_14                                                  0xa19f
++#define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
++#define mmSPI_PS_INPUT_CNTL_16                                                  0xa1a1
++#define mmSPI_PS_INPUT_CNTL_17                                                  0xa1a2
++#define mmSPI_PS_INPUT_CNTL_18                                                  0xa1a3
++#define mmSPI_PS_INPUT_CNTL_19                                                  0xa1a4
++#define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
++#define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
++#define mmSPI_PS_INPUT_CNTL_22                                                  0xa1a7
++#define mmSPI_PS_INPUT_CNTL_23                                                  0xa1a8
++#define mmSPI_PS_INPUT_CNTL_24                                                  0xa1a9
++#define mmSPI_PS_INPUT_CNTL_25                                                  0xa1aa
++#define mmSPI_PS_INPUT_CNTL_26                                                  0xa1ab
++#define mmSPI_PS_INPUT_CNTL_27                                                  0xa1ac
++#define mmSPI_PS_INPUT_CNTL_28                                                  0xa1ad
++#define mmSPI_PS_INPUT_CNTL_29                                                  0xa1ae
++#define mmSPI_PS_INPUT_CNTL_30                                                  0xa1af
++#define mmSPI_PS_INPUT_CNTL_31                                                  0xa1b0
++#define mmSPI_VS_OUT_CONFIG                                                     0xa1b1
++#define mmSPI_PS_INPUT_ENA                                                      0xa1b3
++#define mmSPI_PS_INPUT_ADDR                                                     0xa1b4
++#define mmSPI_INTERP_CONTROL_0                                                  0xa1b5
++#define mmSPI_PS_IN_CONTROL                                                     0xa1b6
++#define mmSPI_BARYC_CNTL                                                        0xa1b8
++#define mmSPI_TMPRING_SIZE                                                      0xa1ba
++#define mmSPI_SHADER_POS_FORMAT                                                 0xa1c3
++#define mmSPI_SHADER_Z_FORMAT                                                   0xa1c4
++#define mmSPI_SHADER_COL_FORMAT                                                 0xa1c5
++#define mmSPI_ARB_PRIORITY                                                      0x31c0
++#define mmSPI_ARB_CYCLES_0                                                      0x31c1
++#define mmSPI_ARB_CYCLES_1                                                      0x31c2
++#define mmSPI_CDBG_SYS_GFX                                                      0x31c3
++#define mmSPI_CDBG_SYS_HP3D                                                     0x31c4
++#define mmSPI_CDBG_SYS_CS0                                                      0x31c5
++#define mmSPI_CDBG_SYS_CS1                                                      0x31c6
++#define mmSPI_WCL_PIPE_PERCENT_GFX                                              0x31c7
++#define mmSPI_WCL_PIPE_PERCENT_HP3D                                             0x31c8
++#define mmSPI_WCL_PIPE_PERCENT_CS0                                              0x31c9
++#define mmSPI_WCL_PIPE_PERCENT_CS1                                              0x31ca
++#define mmSPI_WCL_PIPE_PERCENT_CS2                                              0x31cb
++#define mmSPI_WCL_PIPE_PERCENT_CS3                                              0x31cc
++#define mmSPI_WCL_PIPE_PERCENT_CS4                                              0x31cd
++#define mmSPI_WCL_PIPE_PERCENT_CS5                                              0x31ce
++#define mmSPI_WCL_PIPE_PERCENT_CS6                                              0x31cf
++#define mmSPI_WCL_PIPE_PERCENT_CS7                                              0x31d0
++#define mmSPI_GDBG_WAVE_CNTL                                                    0x31d1
++#define mmSPI_GDBG_TRAP_CONFIG                                                  0x31d2
++#define mmSPI_GDBG_TRAP_MASK                                                    0x31d3
++#define mmSPI_GDBG_TBA_LO                                                       0x31d4
++#define mmSPI_GDBG_TBA_HI                                                       0x31d5
++#define mmSPI_GDBG_TMA_LO                                                       0x31d6
++#define mmSPI_GDBG_TMA_HI                                                       0x31d7
++#define mmSPI_GDBG_TRAP_DATA0                                                   0x31d8
++#define mmSPI_GDBG_TRAP_DATA1                                                   0x31d9
++#define mmSPI_RESET_DEBUG                                                       0x31da
++#define mmSPI_COMPUTE_QUEUE_RESET                                               0x31db
++#define mmSPI_RESOURCE_RESERVE_CU_0                                             0x31dc
++#define mmSPI_RESOURCE_RESERVE_CU_1                                             0x31dd
++#define mmSPI_RESOURCE_RESERVE_CU_2                                             0x31de
++#define mmSPI_RESOURCE_RESERVE_CU_3                                             0x31df
++#define mmSPI_RESOURCE_RESERVE_CU_4                                             0x31e0
++#define mmSPI_RESOURCE_RESERVE_CU_5                                             0x31e1
++#define mmSPI_RESOURCE_RESERVE_CU_6                                             0x31e2
++#define mmSPI_RESOURCE_RESERVE_CU_7                                             0x31e3
++#define mmSPI_RESOURCE_RESERVE_CU_8                                             0x31e4
++#define mmSPI_RESOURCE_RESERVE_CU_9                                             0x31e5
++#define mmSPI_RESOURCE_RESERVE_EN_CU_0                                          0x31e6
++#define mmSPI_RESOURCE_RESERVE_EN_CU_1                                          0x31e7
++#define mmSPI_RESOURCE_RESERVE_EN_CU_2                                          0x31e8
++#define mmSPI_RESOURCE_RESERVE_EN_CU_3                                          0x31e9
++#define mmSPI_RESOURCE_RESERVE_EN_CU_4                                          0x31ea
++#define mmSPI_RESOURCE_RESERVE_EN_CU_5                                          0x31eb
++#define mmSPI_RESOURCE_RESERVE_EN_CU_6                                          0x31ec
++#define mmSPI_RESOURCE_RESERVE_EN_CU_7                                          0x31ed
++#define mmSPI_RESOURCE_RESERVE_EN_CU_8                                          0x31ee
++#define mmSPI_RESOURCE_RESERVE_EN_CU_9                                          0x31ef
++#define mmSPI_PS_MAX_WAVE_ID                                                    0x243a
++#define mmSPI_CONFIG_CNTL                                                       0x2440
++#define mmSPI_DEBUG_CNTL                                                        0x2441
++#define mmSPI_DEBUG_READ                                                        0x2442
++#define mmSPI_PERFCOUNTER0_SELECT                                               0xd980
++#define mmSPI_PERFCOUNTER1_SELECT                                               0xd981
++#define mmSPI_PERFCOUNTER2_SELECT                                               0xd982
++#define mmSPI_PERFCOUNTER3_SELECT                                               0xd983
++#define mmSPI_PERFCOUNTER0_SELECT1                                              0xd984
++#define mmSPI_PERFCOUNTER1_SELECT1                                              0xd985
++#define mmSPI_PERFCOUNTER2_SELECT1                                              0xd986
++#define mmSPI_PERFCOUNTER3_SELECT1                                              0xd987
++#define mmSPI_PERFCOUNTER4_SELECT                                               0xd988
++#define mmSPI_PERFCOUNTER5_SELECT                                               0xd989
++#define mmSPI_PERFCOUNTER_BINS                                                  0xd98a
++#define mmSPI_PERFCOUNTER0_HI                                                   0xd180
++#define mmSPI_PERFCOUNTER0_LO                                                   0xd181
++#define mmSPI_PERFCOUNTER1_HI                                                   0xd182
++#define mmSPI_PERFCOUNTER1_LO                                                   0xd183
++#define mmSPI_PERFCOUNTER2_HI                                                   0xd184
++#define mmSPI_PERFCOUNTER2_LO                                                   0xd185
++#define mmSPI_PERFCOUNTER3_HI                                                   0xd186
++#define mmSPI_PERFCOUNTER3_LO                                                   0xd187
++#define mmSPI_PERFCOUNTER4_HI                                                   0xd188
++#define mmSPI_PERFCOUNTER4_LO                                                   0xd189
++#define mmSPI_PERFCOUNTER5_HI                                                   0xd18a
++#define mmSPI_PERFCOUNTER5_LO                                                   0xd18b
++#define mmSPI_CONFIG_CNTL_1                                                     0x244f
++#define mmSPI_DEBUG_BUSY                                                        0x2450
++#define mmCGTS_SM_CTRL_REG                                                      0xf000
++#define mmCGTS_RD_CTRL_REG                                                      0xf001
++#define mmCGTS_RD_REG                                                           0xf002
++#define mmCGTS_TCC_DISABLE                                                      0xf003
++#define mmCGTS_USER_TCC_DISABLE                                                 0xf004
++#define mmCGTS_CU0_SP0_CTRL_REG                                                 0xf008
++#define mmCGTS_CU0_LDS_SQ_CTRL_REG                                              0xf009
++#define mmCGTS_CU0_TA_SQC_CTRL_REG                                              0xf00a
++#define mmCGTS_CU0_SP1_CTRL_REG                                                 0xf00b
++#define mmCGTS_CU0_TD_TCP_CTRL_REG                                              0xf00c
++#define mmCGTS_CU1_SP0_CTRL_REG                                                 0xf00d
++#define mmCGTS_CU1_LDS_SQ_CTRL_REG                                              0xf00e
++#define mmCGTS_CU1_TA_CTRL_REG                                                  0xf00f
++#define mmCGTS_CU1_SP1_CTRL_REG                                                 0xf010
++#define mmCGTS_CU1_TD_TCP_CTRL_REG                                              0xf011
++#define mmCGTS_CU2_SP0_CTRL_REG                                                 0xf012
++#define mmCGTS_CU2_LDS_SQ_CTRL_REG                                              0xf013
++#define mmCGTS_CU2_TA_CTRL_REG                                                  0xf014
++#define mmCGTS_CU2_SP1_CTRL_REG                                                 0xf015
++#define mmCGTS_CU2_TD_TCP_CTRL_REG                                              0xf016
++#define mmCGTS_CU3_SP0_CTRL_REG                                                 0xf017
++#define mmCGTS_CU3_LDS_SQ_CTRL_REG                                              0xf018
++#define mmCGTS_CU3_TA_CTRL_REG                                                  0xf019
++#define mmCGTS_CU3_SP1_CTRL_REG                                                 0xf01a
++#define mmCGTS_CU3_TD_TCP_CTRL_REG                                              0xf01b
++#define mmCGTS_CU4_SP0_CTRL_REG                                                 0xf01c
++#define mmCGTS_CU4_LDS_SQ_CTRL_REG                                              0xf01d
++#define mmCGTS_CU4_TA_SQC_CTRL_REG                                              0xf01e
++#define mmCGTS_CU4_SP1_CTRL_REG                                                 0xf01f
++#define mmCGTS_CU4_TD_TCP_CTRL_REG                                              0xf020
++#define mmCGTS_CU5_SP0_CTRL_REG                                                 0xf021
++#define mmCGTS_CU5_LDS_SQ_CTRL_REG                                              0xf022
++#define mmCGTS_CU5_TA_CTRL_REG                                                  0xf023
++#define mmCGTS_CU5_SP1_CTRL_REG                                                 0xf024
++#define mmCGTS_CU5_TD_TCP_CTRL_REG                                              0xf025
++#define mmCGTS_CU6_SP0_CTRL_REG                                                 0xf026
++#define mmCGTS_CU6_LDS_SQ_CTRL_REG                                              0xf027
++#define mmCGTS_CU6_TA_CTRL_REG                                                  0xf028
++#define mmCGTS_CU6_SP1_CTRL_REG                                                 0xf029
++#define mmCGTS_CU6_TD_TCP_CTRL_REG                                              0xf02a
++#define mmCGTS_CU7_SP0_CTRL_REG                                                 0xf02b
++#define mmCGTS_CU7_LDS_SQ_CTRL_REG                                              0xf02c
++#define mmCGTS_CU7_TA_CTRL_REG                                                  0xf02d
++#define mmCGTS_CU7_SP1_CTRL_REG                                                 0xf02e
++#define mmCGTS_CU7_TD_TCP_CTRL_REG                                              0xf02f
++#define mmCGTS_CU8_SP0_CTRL_REG                                                 0xf030
++#define mmCGTS_CU8_LDS_SQ_CTRL_REG                                              0xf031
++#define mmCGTS_CU8_TA_SQC_CTRL_REG                                              0xf032
++#define mmCGTS_CU8_SP1_CTRL_REG                                                 0xf033
++#define mmCGTS_CU8_TD_TCP_CTRL_REG                                              0xf034
++#define mmCGTS_CU9_SP0_CTRL_REG                                                 0xf035
++#define mmCGTS_CU9_LDS_SQ_CTRL_REG                                              0xf036
++#define mmCGTS_CU9_TA_CTRL_REG                                                  0xf037
++#define mmCGTS_CU9_SP1_CTRL_REG                                                 0xf038
++#define mmCGTS_CU9_TD_TCP_CTRL_REG                                              0xf039
++#define mmCGTS_CU10_SP0_CTRL_REG                                                0xf03a
++#define mmCGTS_CU10_LDS_SQ_CTRL_REG                                             0xf03b
++#define mmCGTS_CU10_TA_CTRL_REG                                                 0xf03c
++#define mmCGTS_CU10_SP1_CTRL_REG                                                0xf03d
++#define mmCGTS_CU10_TD_TCP_CTRL_REG                                             0xf03e
++#define mmCGTS_CU11_SP0_CTRL_REG                                                0xf03f
++#define mmCGTS_CU11_LDS_SQ_CTRL_REG                                             0xf040
++#define mmCGTS_CU11_TA_CTRL_REG                                                 0xf041
++#define mmCGTS_CU11_SP1_CTRL_REG                                                0xf042
++#define mmCGTS_CU11_TD_TCP_CTRL_REG                                             0xf043
++#define mmCGTS_CU12_SP0_CTRL_REG                                                0xf044
++#define mmCGTS_CU12_LDS_SQ_CTRL_REG                                             0xf045
++#define mmCGTS_CU12_TA_SQC_CTRL_REG                                             0xf046
++#define mmCGTS_CU12_SP1_CTRL_REG                                                0xf047
++#define mmCGTS_CU12_TD_TCP_CTRL_REG                                             0xf048
++#define mmCGTS_CU13_SP0_CTRL_REG                                                0xf049
++#define mmCGTS_CU13_LDS_SQ_CTRL_REG                                             0xf04a
++#define mmCGTS_CU13_TA_CTRL_REG                                                 0xf04b
++#define mmCGTS_CU13_SP1_CTRL_REG                                                0xf04c
++#define mmCGTS_CU13_TD_TCP_CTRL_REG                                             0xf04d
++#define mmCGTS_CU14_SP0_CTRL_REG                                                0xf04e
++#define mmCGTS_CU14_LDS_SQ_CTRL_REG                                             0xf04f
++#define mmCGTS_CU14_TA_CTRL_REG                                                 0xf050
++#define mmCGTS_CU14_SP1_CTRL_REG                                                0xf051
++#define mmCGTS_CU14_TD_TCP_CTRL_REG                                             0xf052
++#define mmCGTS_CU15_SP0_CTRL_REG                                                0xf053
++#define mmCGTS_CU15_LDS_SQ_CTRL_REG                                             0xf054
++#define mmCGTS_CU15_TA_CTRL_REG                                                 0xf055
++#define mmCGTS_CU15_SP1_CTRL_REG                                                0xf056
++#define mmCGTS_CU15_TD_TCP_CTRL_REG                                             0xf057
++#define mmCGTT_SPI_CLK_CTRL                                                     0xf080
++#define mmCGTT_PC_CLK_CTRL                                                      0xf081
++#define mmCGTT_BCI_CLK_CTRL                                                     0xf082
++#define mmSPI_WF_LIFETIME_CNTL                                                  0x24aa
++#define mmSPI_WF_LIFETIME_LIMIT_0                                               0x24ab
++#define mmSPI_WF_LIFETIME_LIMIT_1                                               0x24ac
++#define mmSPI_WF_LIFETIME_LIMIT_2                                               0x24ad
++#define mmSPI_WF_LIFETIME_LIMIT_3                                               0x24ae
++#define mmSPI_WF_LIFETIME_LIMIT_4                                               0x24af
++#define mmSPI_WF_LIFETIME_LIMIT_5                                               0x24b0
++#define mmSPI_WF_LIFETIME_LIMIT_6                                               0x24b1
++#define mmSPI_WF_LIFETIME_LIMIT_7                                               0x24b2
++#define mmSPI_WF_LIFETIME_LIMIT_8                                               0x24b3
++#define mmSPI_WF_LIFETIME_LIMIT_9                                               0x24b4
++#define mmSPI_WF_LIFETIME_STATUS_0                                              0x24b5
++#define mmSPI_WF_LIFETIME_STATUS_1                                              0x24b6
++#define mmSPI_WF_LIFETIME_STATUS_2                                              0x24b7
++#define mmSPI_WF_LIFETIME_STATUS_3                                              0x24b8
++#define mmSPI_WF_LIFETIME_STATUS_4                                              0x24b9
++#define mmSPI_WF_LIFETIME_STATUS_5                                              0x24ba
++#define mmSPI_WF_LIFETIME_STATUS_6                                              0x24bb
++#define mmSPI_WF_LIFETIME_STATUS_7                                              0x24bc
++#define mmSPI_WF_LIFETIME_STATUS_8                                              0x24bd
++#define mmSPI_WF_LIFETIME_STATUS_9                                              0x24be
++#define mmSPI_WF_LIFETIME_STATUS_10                                             0x24bf
++#define mmSPI_WF_LIFETIME_STATUS_11                                             0x24c0
++#define mmSPI_WF_LIFETIME_STATUS_12                                             0x24c1
++#define mmSPI_WF_LIFETIME_STATUS_13                                             0x24c2
++#define mmSPI_WF_LIFETIME_STATUS_14                                             0x24c3
++#define mmSPI_WF_LIFETIME_STATUS_15                                             0x24c4
++#define mmSPI_WF_LIFETIME_STATUS_16                                             0x24c5
++#define mmSPI_WF_LIFETIME_STATUS_17                                             0x24c6
++#define mmSPI_WF_LIFETIME_STATUS_18                                             0x24c7
++#define mmSPI_WF_LIFETIME_STATUS_19                                             0x24c8
++#define mmSPI_WF_LIFETIME_STATUS_20                                             0x24c9
++#define mmSPI_WF_LIFETIME_DEBUG                                                 0x24ca
++#define mmSPI_SLAVE_DEBUG_BUSY                                                  0x24d3
++#define mmSPI_LB_CTR_CTRL                                                       0x24d4
++#define mmSPI_LB_CU_MASK                                                        0x24d5
++#define mmSPI_LB_DATA_REG                                                       0x24d6
++#define mmSPI_PG_ENABLE_STATIC_CU_MASK                                          0x24d7
++#define mmSPI_GDS_CREDITS                                                       0x24d8
++#define mmSPI_SX_EXPORT_BUFFER_SIZES                                            0x24d9
++#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                                        0x24da
++#define mmSPI_CSQ_WF_ACTIVE_STATUS                                              0x24db
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_0                                             0x24dc
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_1                                             0x24dd
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_2                                             0x24de
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_3                                             0x24df
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_4                                             0x24e0
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_5                                             0x24e1
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_6                                             0x24e2
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_7                                             0x24e3
++#define mmBCI_DEBUG_READ                                                        0x24eb
++#define mmSPI_P0_TRAP_SCREEN_PSBA_LO                                            0x24ec
++#define mmSPI_P0_TRAP_SCREEN_PSBA_HI                                            0x24ed
++#define mmSPI_P0_TRAP_SCREEN_PSMA_LO                                            0x24ee
++#define mmSPI_P0_TRAP_SCREEN_PSMA_HI                                            0x24ef
++#define mmSPI_P0_TRAP_SCREEN_GPR_MIN                                            0x24f0
++#define mmSPI_P1_TRAP_SCREEN_PSBA_LO                                            0x24f1
++#define mmSPI_P1_TRAP_SCREEN_PSBA_HI                                            0x24f2
++#define mmSPI_P1_TRAP_SCREEN_PSMA_LO                                            0x24f3
++#define mmSPI_P1_TRAP_SCREEN_PSMA_HI                                            0x24f4
++#define mmSPI_P1_TRAP_SCREEN_GPR_MIN                                            0x24f5
++#define mmSPI_SHADER_TBA_LO_PS                                                  0x2c00
++#define mmSPI_SHADER_TBA_HI_PS                                                  0x2c01
++#define mmSPI_SHADER_TMA_LO_PS                                                  0x2c02
++#define mmSPI_SHADER_TMA_HI_PS                                                  0x2c03
++#define mmSPI_SHADER_PGM_LO_PS                                                  0x2c08
++#define mmSPI_SHADER_PGM_HI_PS                                                  0x2c09
++#define mmSPI_SHADER_PGM_RSRC1_PS                                               0x2c0a
++#define mmSPI_SHADER_PGM_RSRC2_PS                                               0x2c0b
++#define mmSPI_SHADER_PGM_RSRC3_PS                                               0x2c07
++#define mmSPI_SHADER_USER_DATA_PS_0                                             0x2c0c
++#define mmSPI_SHADER_USER_DATA_PS_1                                             0x2c0d
++#define mmSPI_SHADER_USER_DATA_PS_2                                             0x2c0e
++#define mmSPI_SHADER_USER_DATA_PS_3                                             0x2c0f
++#define mmSPI_SHADER_USER_DATA_PS_4                                             0x2c10
++#define mmSPI_SHADER_USER_DATA_PS_5                                             0x2c11
++#define mmSPI_SHADER_USER_DATA_PS_6                                             0x2c12
++#define mmSPI_SHADER_USER_DATA_PS_7                                             0x2c13
++#define mmSPI_SHADER_USER_DATA_PS_8                                             0x2c14
++#define mmSPI_SHADER_USER_DATA_PS_9                                             0x2c15
++#define mmSPI_SHADER_USER_DATA_PS_10                                            0x2c16
++#define mmSPI_SHADER_USER_DATA_PS_11                                            0x2c17
++#define mmSPI_SHADER_USER_DATA_PS_12                                            0x2c18
++#define mmSPI_SHADER_USER_DATA_PS_13                                            0x2c19
++#define mmSPI_SHADER_USER_DATA_PS_14                                            0x2c1a
++#define mmSPI_SHADER_USER_DATA_PS_15                                            0x2c1b
++#define mmSPI_SHADER_TBA_LO_VS                                                  0x2c40
++#define mmSPI_SHADER_TBA_HI_VS                                                  0x2c41
++#define mmSPI_SHADER_TMA_LO_VS                                                  0x2c42
++#define mmSPI_SHADER_TMA_HI_VS                                                  0x2c43
++#define mmSPI_SHADER_PGM_LO_VS                                                  0x2c48
++#define mmSPI_SHADER_PGM_HI_VS                                                  0x2c49
++#define mmSPI_SHADER_PGM_RSRC1_VS                                               0x2c4a
++#define mmSPI_SHADER_PGM_RSRC2_VS                                               0x2c4b
++#define mmSPI_SHADER_PGM_RSRC3_VS                                               0x2c46
++#define mmSPI_SHADER_LATE_ALLOC_VS                                              0x2c47
++#define mmSPI_SHADER_USER_DATA_VS_0                                             0x2c4c
++#define mmSPI_SHADER_USER_DATA_VS_1                                             0x2c4d
++#define mmSPI_SHADER_USER_DATA_VS_2                                             0x2c4e
++#define mmSPI_SHADER_USER_DATA_VS_3                                             0x2c4f
++#define mmSPI_SHADER_USER_DATA_VS_4                                             0x2c50
++#define mmSPI_SHADER_USER_DATA_VS_5                                             0x2c51
++#define mmSPI_SHADER_USER_DATA_VS_6                                             0x2c52
++#define mmSPI_SHADER_USER_DATA_VS_7                                             0x2c53
++#define mmSPI_SHADER_USER_DATA_VS_8                                             0x2c54
++#define mmSPI_SHADER_USER_DATA_VS_9                                             0x2c55
++#define mmSPI_SHADER_USER_DATA_VS_10                                            0x2c56
++#define mmSPI_SHADER_USER_DATA_VS_11                                            0x2c57
++#define mmSPI_SHADER_USER_DATA_VS_12                                            0x2c58
++#define mmSPI_SHADER_USER_DATA_VS_13                                            0x2c59
++#define mmSPI_SHADER_USER_DATA_VS_14                                            0x2c5a
++#define mmSPI_SHADER_USER_DATA_VS_15                                            0x2c5b
++#define mmSPI_SHADER_PGM_RSRC2_ES_VS                                            0x2c7c
++#define mmSPI_SHADER_PGM_RSRC2_LS_VS                                            0x2c7d
++#define mmSPI_SHADER_TBA_LO_GS                                                  0x2c80
++#define mmSPI_SHADER_TBA_HI_GS                                                  0x2c81
++#define mmSPI_SHADER_TMA_LO_GS                                                  0x2c82
++#define mmSPI_SHADER_TMA_HI_GS                                                  0x2c83
++#define mmSPI_SHADER_PGM_LO_GS                                                  0x2c88
++#define mmSPI_SHADER_PGM_HI_GS                                                  0x2c89
++#define mmSPI_SHADER_PGM_RSRC1_GS                                               0x2c8a
++#define mmSPI_SHADER_PGM_RSRC2_GS                                               0x2c8b
++#define mmSPI_SHADER_PGM_RSRC3_GS                                               0x2c87
++#define mmSPI_SHADER_USER_DATA_GS_0                                             0x2c8c
++#define mmSPI_SHADER_USER_DATA_GS_1                                             0x2c8d
++#define mmSPI_SHADER_USER_DATA_GS_2                                             0x2c8e
++#define mmSPI_SHADER_USER_DATA_GS_3                                             0x2c8f
++#define mmSPI_SHADER_USER_DATA_GS_4                                             0x2c90
++#define mmSPI_SHADER_USER_DATA_GS_5                                             0x2c91
++#define mmSPI_SHADER_USER_DATA_GS_6                                             0x2c92
++#define mmSPI_SHADER_USER_DATA_GS_7                                             0x2c93
++#define mmSPI_SHADER_USER_DATA_GS_8                                             0x2c94
++#define mmSPI_SHADER_USER_DATA_GS_9                                             0x2c95
++#define mmSPI_SHADER_USER_DATA_GS_10                                            0x2c96
++#define mmSPI_SHADER_USER_DATA_GS_11                                            0x2c97
++#define mmSPI_SHADER_USER_DATA_GS_12                                            0x2c98
++#define mmSPI_SHADER_USER_DATA_GS_13                                            0x2c99
++#define mmSPI_SHADER_USER_DATA_GS_14                                            0x2c9a
++#define mmSPI_SHADER_USER_DATA_GS_15                                            0x2c9b
++#define mmSPI_SHADER_PGM_RSRC2_ES_GS                                            0x2cbc
++#define mmSPI_SHADER_TBA_LO_ES                                                  0x2cc0
++#define mmSPI_SHADER_TBA_HI_ES                                                  0x2cc1
++#define mmSPI_SHADER_TMA_LO_ES                                                  0x2cc2
++#define mmSPI_SHADER_TMA_HI_ES                                                  0x2cc3
++#define mmSPI_SHADER_PGM_LO_ES                                                  0x2cc8
++#define mmSPI_SHADER_PGM_HI_ES                                                  0x2cc9
++#define mmSPI_SHADER_PGM_RSRC1_ES                                               0x2cca
++#define mmSPI_SHADER_PGM_RSRC2_ES                                               0x2ccb
++#define mmSPI_SHADER_PGM_RSRC3_ES                                               0x2cc7
++#define mmSPI_SHADER_USER_DATA_ES_0                                             0x2ccc
++#define mmSPI_SHADER_USER_DATA_ES_1                                             0x2ccd
++#define mmSPI_SHADER_USER_DATA_ES_2                                             0x2cce
++#define mmSPI_SHADER_USER_DATA_ES_3                                             0x2ccf
++#define mmSPI_SHADER_USER_DATA_ES_4                                             0x2cd0
++#define mmSPI_SHADER_USER_DATA_ES_5                                             0x2cd1
++#define mmSPI_SHADER_USER_DATA_ES_6                                             0x2cd2
++#define mmSPI_SHADER_USER_DATA_ES_7                                             0x2cd3
++#define mmSPI_SHADER_USER_DATA_ES_8                                             0x2cd4
++#define mmSPI_SHADER_USER_DATA_ES_9                                             0x2cd5
++#define mmSPI_SHADER_USER_DATA_ES_10                                            0x2cd6
++#define mmSPI_SHADER_USER_DATA_ES_11                                            0x2cd7
++#define mmSPI_SHADER_USER_DATA_ES_12                                            0x2cd8
++#define mmSPI_SHADER_USER_DATA_ES_13                                            0x2cd9
++#define mmSPI_SHADER_USER_DATA_ES_14                                            0x2cda
++#define mmSPI_SHADER_USER_DATA_ES_15                                            0x2cdb
++#define mmSPI_SHADER_PGM_RSRC2_LS_ES                                            0x2cfd
++#define mmSPI_SHADER_TBA_LO_HS                                                  0x2d00
++#define mmSPI_SHADER_TBA_HI_HS                                                  0x2d01
++#define mmSPI_SHADER_TMA_LO_HS                                                  0x2d02
++#define mmSPI_SHADER_TMA_HI_HS                                                  0x2d03
++#define mmSPI_SHADER_PGM_LO_HS                                                  0x2d08
++#define mmSPI_SHADER_PGM_HI_HS                                                  0x2d09
++#define mmSPI_SHADER_PGM_RSRC1_HS                                               0x2d0a
++#define mmSPI_SHADER_PGM_RSRC2_HS                                               0x2d0b
++#define mmSPI_SHADER_PGM_RSRC3_HS                                               0x2d07
++#define mmSPI_SHADER_USER_DATA_HS_0                                             0x2d0c
++#define mmSPI_SHADER_USER_DATA_HS_1                                             0x2d0d
++#define mmSPI_SHADER_USER_DATA_HS_2                                             0x2d0e
++#define mmSPI_SHADER_USER_DATA_HS_3                                             0x2d0f
++#define mmSPI_SHADER_USER_DATA_HS_4                                             0x2d10
++#define mmSPI_SHADER_USER_DATA_HS_5                                             0x2d11
++#define mmSPI_SHADER_USER_DATA_HS_6                                             0x2d12
++#define mmSPI_SHADER_USER_DATA_HS_7                                             0x2d13
++#define mmSPI_SHADER_USER_DATA_HS_8                                             0x2d14
++#define mmSPI_SHADER_USER_DATA_HS_9                                             0x2d15
++#define mmSPI_SHADER_USER_DATA_HS_10                                            0x2d16
++#define mmSPI_SHADER_USER_DATA_HS_11                                            0x2d17
++#define mmSPI_SHADER_USER_DATA_HS_12                                            0x2d18
++#define mmSPI_SHADER_USER_DATA_HS_13                                            0x2d19
++#define mmSPI_SHADER_USER_DATA_HS_14                                            0x2d1a
++#define mmSPI_SHADER_USER_DATA_HS_15                                            0x2d1b
++#define mmSPI_SHADER_PGM_RSRC2_LS_HS                                            0x2d3d
++#define mmSPI_SHADER_TBA_LO_LS                                                  0x2d40
++#define mmSPI_SHADER_TBA_HI_LS                                                  0x2d41
++#define mmSPI_SHADER_TMA_LO_LS                                                  0x2d42
++#define mmSPI_SHADER_TMA_HI_LS                                                  0x2d43
++#define mmSPI_SHADER_PGM_LO_LS                                                  0x2d48
++#define mmSPI_SHADER_PGM_HI_LS                                                  0x2d49
++#define mmSPI_SHADER_PGM_RSRC1_LS                                               0x2d4a
++#define mmSPI_SHADER_PGM_RSRC2_LS                                               0x2d4b
++#define mmSPI_SHADER_PGM_RSRC3_LS                                               0x2d47
++#define mmSPI_SHADER_USER_DATA_LS_0                                             0x2d4c
++#define mmSPI_SHADER_USER_DATA_LS_1                                             0x2d4d
++#define mmSPI_SHADER_USER_DATA_LS_2                                             0x2d4e
++#define mmSPI_SHADER_USER_DATA_LS_3                                             0x2d4f
++#define mmSPI_SHADER_USER_DATA_LS_4                                             0x2d50
++#define mmSPI_SHADER_USER_DATA_LS_5                                             0x2d51
++#define mmSPI_SHADER_USER_DATA_LS_6                                             0x2d52
++#define mmSPI_SHADER_USER_DATA_LS_7                                             0x2d53
++#define mmSPI_SHADER_USER_DATA_LS_8                                             0x2d54
++#define mmSPI_SHADER_USER_DATA_LS_9                                             0x2d55
++#define mmSPI_SHADER_USER_DATA_LS_10                                            0x2d56
++#define mmSPI_SHADER_USER_DATA_LS_11                                            0x2d57
++#define mmSPI_SHADER_USER_DATA_LS_12                                            0x2d58
++#define mmSPI_SHADER_USER_DATA_LS_13                                            0x2d59
++#define mmSPI_SHADER_USER_DATA_LS_14                                            0x2d5a
++#define mmSPI_SHADER_USER_DATA_LS_15                                            0x2d5b
++#define mmSQ_CONFIG                                                             0x2300
++#define mmSQC_CONFIG                                                            0x2301
++#define mmSQC_CACHES                                                            0xc348
++#define mmSQ_RANDOM_WAVE_PRI                                                    0x2303
++#define mmSQ_REG_CREDITS                                                        0x2304
++#define mmSQ_FIFO_SIZES                                                         0x2305
++#define mmSQ_INTERRUPT_AUTO_MASK                                                0x2314
++#define mmSQ_INTERRUPT_MSG_CTRL                                                 0x2315
++#define mmSQ_PERFCOUNTER_CTRL                                                   0xd9e0
++#define mmSQ_PERFCOUNTER_MASK                                                   0xd9e1
++#define mmSQ_PERFCOUNTER_CTRL2                                                  0xd9e2
++#define mmCC_SQC_BANK_DISABLE                                                   0x2307
++#define mmUSER_SQC_BANK_DISABLE                                                 0x2308
++#define mmSQ_PERFCOUNTER0_LO                                                    0xd1c0
++#define mmSQ_PERFCOUNTER1_LO                                                    0xd1c2
++#define mmSQ_PERFCOUNTER2_LO                                                    0xd1c4
++#define mmSQ_PERFCOUNTER3_LO                                                    0xd1c6
++#define mmSQ_PERFCOUNTER4_LO                                                    0xd1c8
++#define mmSQ_PERFCOUNTER5_LO                                                    0xd1ca
++#define mmSQ_PERFCOUNTER6_LO                                                    0xd1cc
++#define mmSQ_PERFCOUNTER7_LO                                                    0xd1ce
++#define mmSQ_PERFCOUNTER8_LO                                                    0xd1d0
++#define mmSQ_PERFCOUNTER9_LO                                                    0xd1d2
++#define mmSQ_PERFCOUNTER10_LO                                                   0xd1d4
++#define mmSQ_PERFCOUNTER11_LO                                                   0xd1d6
++#define mmSQ_PERFCOUNTER12_LO                                                   0xd1d8
++#define mmSQ_PERFCOUNTER13_LO                                                   0xd1da
++#define mmSQ_PERFCOUNTER14_LO                                                   0xd1dc
++#define mmSQ_PERFCOUNTER15_LO                                                   0xd1de
++#define mmSQ_PERFCOUNTER0_HI                                                    0xd1c1
++#define mmSQ_PERFCOUNTER1_HI                                                    0xd1c3
++#define mmSQ_PERFCOUNTER2_HI                                                    0xd1c5
++#define mmSQ_PERFCOUNTER3_HI                                                    0xd1c7
++#define mmSQ_PERFCOUNTER4_HI                                                    0xd1c9
++#define mmSQ_PERFCOUNTER5_HI                                                    0xd1cb
++#define mmSQ_PERFCOUNTER6_HI                                                    0xd1cd
++#define mmSQ_PERFCOUNTER7_HI                                                    0xd1cf
++#define mmSQ_PERFCOUNTER8_HI                                                    0xd1d1
++#define mmSQ_PERFCOUNTER9_HI                                                    0xd1d3
++#define mmSQ_PERFCOUNTER10_HI                                                   0xd1d5
++#define mmSQ_PERFCOUNTER11_HI                                                   0xd1d7
++#define mmSQ_PERFCOUNTER12_HI                                                   0xd1d9
++#define mmSQ_PERFCOUNTER13_HI                                                   0xd1db
++#define mmSQ_PERFCOUNTER14_HI                                                   0xd1dd
++#define mmSQ_PERFCOUNTER15_HI                                                   0xd1df
++#define mmSQ_PERFCOUNTER0_SELECT                                                0xd9c0
++#define mmSQ_PERFCOUNTER1_SELECT                                                0xd9c1
++#define mmSQ_PERFCOUNTER2_SELECT                                                0xd9c2
++#define mmSQ_PERFCOUNTER3_SELECT                                                0xd9c3
++#define mmSQ_PERFCOUNTER4_SELECT                                                0xd9c4
++#define mmSQ_PERFCOUNTER5_SELECT                                                0xd9c5
++#define mmSQ_PERFCOUNTER6_SELECT                                                0xd9c6
++#define mmSQ_PERFCOUNTER7_SELECT                                                0xd9c7
++#define mmSQ_PERFCOUNTER8_SELECT                                                0xd9c8
++#define mmSQ_PERFCOUNTER9_SELECT                                                0xd9c9
++#define mmSQ_PERFCOUNTER10_SELECT                                               0xd9ca
++#define mmSQ_PERFCOUNTER11_SELECT                                               0xd9cb
++#define mmSQ_PERFCOUNTER12_SELECT                                               0xd9cc
++#define mmSQ_PERFCOUNTER13_SELECT                                               0xd9cd
++#define mmSQ_PERFCOUNTER14_SELECT                                               0xd9ce
++#define mmSQ_PERFCOUNTER15_SELECT                                               0xd9cf
++#define mmCGTT_SQ_CLK_CTRL                                                      0xf08c
++#define mmCGTT_SQG_CLK_CTRL                                                     0xf08d
++#define mmSQ_ALU_CLK_CTRL                                                       0xf08e
++#define mmSQ_TEX_CLK_CTRL                                                       0xf08f
++#define mmSQ_LDS_CLK_CTRL                                                       0xf090
++#define mmSQ_POWER_THROTTLE                                                     0xf091
++#define mmSQ_POWER_THROTTLE2                                                    0xf092
++#define mmSQ_TIME_HI                                                            0x237c
++#define mmSQ_TIME_LO                                                            0x237d
++#define mmSQ_THREAD_TRACE_BASE                                                  0x2380
++#define mmSQ_THREAD_TRACE_BASE2                                                 0x2385
++#define mmSQ_THREAD_TRACE_SIZE                                                  0x2381
++#define mmSQ_THREAD_TRACE_MASK                                                  0x2382
++#define mmSQ_THREAD_TRACE_USERDATA_0                                            0xc340
++#define mmSQ_THREAD_TRACE_USERDATA_1                                            0xc341
++#define mmSQ_THREAD_TRACE_USERDATA_2                                            0xc342
++#define mmSQ_THREAD_TRACE_USERDATA_3                                            0xc343
++#define mmSQ_THREAD_TRACE_MODE                                                  0x238e
++#define mmSQ_THREAD_TRACE_CTRL                                                  0x238f
++#define mmSQ_THREAD_TRACE_TOKEN_MASK                                            0x2383
++#define mmSQ_THREAD_TRACE_TOKEN_MASK2                                           0x2386
++#define mmSQ_THREAD_TRACE_PERF_MASK                                             0x2384
++#define mmSQ_THREAD_TRACE_WPTR                                                  0x238c
++#define mmSQ_THREAD_TRACE_STATUS                                                0x238d
++#define mmSQ_THREAD_TRACE_CNTR                                                  0x2390
++#define mmSQ_THREAD_TRACE_HIWATER                                               0x2392
++#define mmSQ_LB_CTR_CTRL                                                        0x2398
++#define mmSQ_LB_DATA_ALU_CYCLES                                                 0x2399
++#define mmSQ_LB_DATA_TEX_CYCLES                                                 0x239a
++#define mmSQ_LB_DATA_ALU_STALLS                                                 0x239b
++#define mmSQ_LB_DATA_TEX_STALLS                                                 0x239c
++#define mmSQC_SECDED_CNT                                                        0x23a0
++#define mmSQ_SEC_CNT                                                            0x23a1
++#define mmSQ_DED_CNT                                                            0x23a2
++#define mmSQ_DED_INFO                                                           0x23a3
++#define mmSQ_BUF_RSRC_WORD0                                                     0x23c0
++#define mmSQ_BUF_RSRC_WORD1                                                     0x23c1
++#define mmSQ_BUF_RSRC_WORD2                                                     0x23c2
++#define mmSQ_BUF_RSRC_WORD3                                                     0x23c3
++#define mmSQ_IMG_RSRC_WORD0                                                     0x23c4
++#define mmSQ_IMG_RSRC_WORD1                                                     0x23c5
++#define mmSQ_IMG_RSRC_WORD2                                                     0x23c6
++#define mmSQ_IMG_RSRC_WORD3                                                     0x23c7
++#define mmSQ_IMG_RSRC_WORD4                                                     0x23c8
++#define mmSQ_IMG_RSRC_WORD5                                                     0x23c9
++#define mmSQ_IMG_RSRC_WORD6                                                     0x23ca
++#define mmSQ_IMG_RSRC_WORD7                                                     0x23cb
++#define mmSQ_IMG_SAMP_WORD0                                                     0x23cc
++#define mmSQ_IMG_SAMP_WORD1                                                     0x23cd
++#define mmSQ_IMG_SAMP_WORD2                                                     0x23ce
++#define mmSQ_IMG_SAMP_WORD3                                                     0x23cf
++#define mmSQ_FLAT_SCRATCH_WORD0                                                 0x23d0
++#define mmSQ_FLAT_SCRATCH_WORD1                                                 0x23d1
++#define mmSQ_IND_INDEX                                                          0x2378
++#define mmSQ_IND_CMD                                                            0x237a
++#define mmSQ_CMD                                                                0x237b
++#define mmSQ_IND_DATA                                                           0x2379
++#define mmSQ_REG_TIMESTAMP                                                      0x2374
++#define mmSQ_CMD_TIMESTAMP                                                      0x2375
++#define mmSQ_HV_VMID_CTRL                                                       0xf840
++#define ixSQ_WAVE_INST_DW0                                                      0x1a
++#define ixSQ_WAVE_INST_DW1                                                      0x1b
++#define ixSQ_WAVE_PC_LO                                                         0x18
++#define ixSQ_WAVE_PC_HI                                                         0x19
++#define ixSQ_WAVE_IB_DBG0                                                       0x1c
++#define ixSQ_WAVE_EXEC_LO                                                       0x27e
++#define ixSQ_WAVE_EXEC_HI                                                       0x27f
++#define ixSQ_WAVE_STATUS                                                        0x12
++#define ixSQ_WAVE_MODE                                                          0x11
++#define ixSQ_WAVE_TRAPSTS                                                       0x13
++#define ixSQ_WAVE_HW_ID                                                         0x14
++#define ixSQ_WAVE_GPR_ALLOC                                                     0x15
++#define ixSQ_WAVE_LDS_ALLOC                                                     0x16
++#define ixSQ_WAVE_IB_STS                                                        0x17
++#define ixSQ_WAVE_M0                                                            0x27c
++#define ixSQ_WAVE_TBA_LO                                                        0x26c
++#define ixSQ_WAVE_TBA_HI                                                        0x26d
++#define ixSQ_WAVE_TMA_LO                                                        0x26e
++#define ixSQ_WAVE_TMA_HI                                                        0x26f
++#define ixSQ_WAVE_TTMP0                                                         0x270
++#define ixSQ_WAVE_TTMP1                                                         0x271
++#define ixSQ_WAVE_TTMP2                                                         0x272
++#define ixSQ_WAVE_TTMP3                                                         0x273
++#define ixSQ_WAVE_TTMP4                                                         0x274
++#define ixSQ_WAVE_TTMP5                                                         0x275
++#define ixSQ_WAVE_TTMP6                                                         0x276
++#define ixSQ_WAVE_TTMP7                                                         0x277
++#define ixSQ_WAVE_TTMP8                                                         0x278
++#define ixSQ_WAVE_TTMP9                                                         0x279
++#define ixSQ_WAVE_TTMP10                                                        0x27a
++#define ixSQ_WAVE_TTMP11                                                        0x27b
++#define mmSQ_DEBUG_STS_GLOBAL                                                   0x2309
++#define mmSQ_DEBUG_STS_GLOBAL2                                                  0x2310
++#define mmSQ_DEBUG_STS_GLOBAL3                                                  0x2311
++#define ixSQ_DEBUG_STS_LOCAL                                                    0x8
++#define ixSQ_DEBUG_CTRL_LOCAL                                                   0x9
++#define mmSH_MEM_BASES                                                          0x230a
++#define mmSH_MEM_APE1_BASE                                                      0x230b
++#define mmSH_MEM_APE1_LIMIT                                                     0x230c
++#define mmSH_MEM_CONFIG                                                         0x230d
++#define mmSQC_POLICY                                                            0x230e
++#define mmSQC_VOLATILE                                                          0x230f
++#define mmSQ_THREAD_TRACE_WORD_CMN                                              0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2                                   0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2                                   0x23b1
++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2                             0x23b1
++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2                                 0x23b0
++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2                                 0x23b1
++#define mmSQ_THREAD_TRACE_WORD_WAVE                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_MISC                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_WAVE_START                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                                    0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2                                    0x23b0
++#define mmSQ_THREAD_TRACE_WORD_EVENT                                            0x23b0
++#define mmSQ_THREAD_TRACE_WORD_ISSUE                                            0x23b0
++#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2                                      0x23b0
++#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2                                      0x23b1
++#define ixSQ_INTERRUPT_WORD_CMN                                                 0x20c0
++#define ixSQ_INTERRUPT_WORD_AUTO                                                0x20c0
++#define ixSQ_INTERRUPT_WORD_WAVE                                                0x20c0
++#define mmSQ_SOP2                                                               0x237f
++#define mmSQ_VOP1                                                               0x237f
++#define mmSQ_MTBUF_1                                                            0x237f
++#define mmSQ_EXP_1                                                              0x237f
++#define mmSQ_MUBUF_1                                                            0x237f
++#define mmSQ_INST                                                               0x237f
++#define mmSQ_EXP_0                                                              0x237f
++#define mmSQ_MUBUF_0                                                            0x237f
++#define mmSQ_VOP3_0                                                             0x237f
++#define mmSQ_VOP2                                                               0x237f
++#define mmSQ_MTBUF_0                                                            0x237f
++#define mmSQ_SOPP                                                               0x237f
++#define mmSQ_FLAT_0                                                             0x237f
++#define mmSQ_VOP3_0_SDST_ENC                                                    0x237f
++#define mmSQ_MIMG_1                                                             0x237f
++#define mmSQ_SMRD                                                               0x237f
++#define mmSQ_SOP1                                                               0x237f
++#define mmSQ_SOPC                                                               0x237f
++#define mmSQ_FLAT_1                                                             0x237f
++#define mmSQ_DS_1                                                               0x237f
++#define mmSQ_VOP3_1                                                             0x237f
++#define mmSQ_MIMG_0                                                             0x237f
++#define mmSQ_SOPK                                                               0x237f
++#define mmSQ_DS_0                                                               0x237f
++#define mmSQ_VOPC                                                               0x237f
++#define mmSQ_VINTRP                                                             0x237f
++#define mmCGTT_SX_CLK_CTRL0                                                     0xf094
++#define mmCGTT_SX_CLK_CTRL1                                                     0xf095
++#define mmCGTT_SX_CLK_CTRL2                                                     0xf096
++#define mmCGTT_SX_CLK_CTRL3                                                     0xf097
++#define mmCGTT_SX_CLK_CTRL4                                                     0xf098
++#define mmSX_DEBUG_BUSY                                                         0x2414
++#define mmSX_DEBUG_BUSY_2                                                       0x2415
++#define mmSX_DEBUG_BUSY_3                                                       0x2416
++#define mmSX_DEBUG_BUSY_4                                                       0x2417
++#define mmSX_DEBUG_1                                                            0x2418
++#define mmSX_PERFCOUNTER0_SELECT                                                0xda40
++#define mmSX_PERFCOUNTER1_SELECT                                                0xda41
++#define mmSX_PERFCOUNTER2_SELECT                                                0xda42
++#define mmSX_PERFCOUNTER3_SELECT                                                0xda43
++#define mmSX_PERFCOUNTER0_SELECT1                                               0xda44
++#define mmSX_PERFCOUNTER1_SELECT1                                               0xda45
++#define mmSX_PERFCOUNTER0_LO                                                    0xd240
++#define mmSX_PERFCOUNTER0_HI                                                    0xd241
++#define mmSX_PERFCOUNTER1_LO                                                    0xd242
++#define mmSX_PERFCOUNTER1_HI                                                    0xd243
++#define mmSX_PERFCOUNTER2_LO                                                    0xd244
++#define mmSX_PERFCOUNTER2_HI                                                    0xd245
++#define mmSX_PERFCOUNTER3_LO                                                    0xd246
++#define mmSX_PERFCOUNTER3_HI                                                    0xd247
++#define mmTCC_CTRL                                                              0x2b80
++#define mmTCC_EDC_COUNTER                                                       0x2b82
++#define mmTCC_REDUNDANCY                                                        0x2b83
++#define mmTCC_CGTT_SCLK_CTRL                                                    0xf0ac
++#define mmTCA_CGTT_SCLK_CTRL                                                    0xf0ad
++#define mmTCS_CGTT_SCLK_CTRL                                                    0xf0ae
++#define mmTCC_PERFCOUNTER0_SELECT                                               0xdb80
++#define mmTCC_PERFCOUNTER1_SELECT                                               0xdb82
++#define mmTCC_PERFCOUNTER0_SELECT1                                              0xdb81
++#define mmTCC_PERFCOUNTER1_SELECT1                                              0xdb83
++#define mmTCC_PERFCOUNTER2_SELECT                                               0xdb84
++#define mmTCC_PERFCOUNTER3_SELECT                                               0xdb85
++#define mmTCC_PERFCOUNTER0_LO                                                   0xd380
++#define mmTCC_PERFCOUNTER1_LO                                                   0xd382
++#define mmTCC_PERFCOUNTER2_LO                                                   0xd384
++#define mmTCC_PERFCOUNTER3_LO                                                   0xd386
++#define mmTCC_PERFCOUNTER0_HI                                                   0xd381
++#define mmTCC_PERFCOUNTER1_HI                                                   0xd383
++#define mmTCC_PERFCOUNTER2_HI                                                   0xd385
++#define mmTCC_PERFCOUNTER3_HI                                                   0xd387
++#define mmTCA_CTRL                                                              0x2bc0
++#define mmTCA_PERFCOUNTER0_SELECT                                               0xdb90
++#define mmTCA_PERFCOUNTER1_SELECT                                               0xdb92
++#define mmTCA_PERFCOUNTER0_SELECT1                                              0xdb91
++#define mmTCA_PERFCOUNTER1_SELECT1                                              0xdb93
++#define mmTCA_PERFCOUNTER2_SELECT                                               0xdb94
++#define mmTCA_PERFCOUNTER3_SELECT                                               0xdb95
++#define mmTCA_PERFCOUNTER0_LO                                                   0xd390
++#define mmTCA_PERFCOUNTER1_LO                                                   0xd392
++#define mmTCA_PERFCOUNTER2_LO                                                   0xd394
++#define mmTCA_PERFCOUNTER3_LO                                                   0xd396
++#define mmTCA_PERFCOUNTER0_HI                                                   0xd391
++#define mmTCA_PERFCOUNTER1_HI                                                   0xd393
++#define mmTCA_PERFCOUNTER2_HI                                                   0xd395
++#define mmTCA_PERFCOUNTER3_HI                                                   0xd397
++#define mmTCS_CTRL                                                              0x2be0
++#define mmTCS_PERFCOUNTER0_SELECT                                               0xdba0
++#define mmTCS_PERFCOUNTER0_SELECT1                                              0xdba1
++#define mmTCS_PERFCOUNTER1_SELECT                                               0xdba2
++#define mmTCS_PERFCOUNTER2_SELECT                                               0xdba3
++#define mmTCS_PERFCOUNTER3_SELECT                                               0xdba4
++#define mmTCS_PERFCOUNTER0_LO                                                   0xd3a0
++#define mmTCS_PERFCOUNTER1_LO                                                   0xd3a2
++#define mmTCS_PERFCOUNTER2_LO                                                   0xd3a4
++#define mmTCS_PERFCOUNTER3_LO                                                   0xd3a6
++#define mmTCS_PERFCOUNTER0_HI                                                   0xd3a1
++#define mmTCS_PERFCOUNTER1_HI                                                   0xd3a3
++#define mmTCS_PERFCOUNTER2_HI                                                   0xd3a5
++#define mmTCS_PERFCOUNTER3_HI                                                   0xd3a7
++#define mmTA_BC_BASE_ADDR                                                       0xa020
++#define mmTA_BC_BASE_ADDR_HI                                                    0xa021
++#define mmTD_CNTL                                                               0x2525
++#define mmTD_STATUS                                                             0x2526
++#define mmTD_DEBUG_INDEX                                                        0x2528
++#define mmTD_DEBUG_DATA                                                         0x2529
++#define mmTD_PERFCOUNTER0_SELECT                                                0xdb00
++#define mmTD_PERFCOUNTER1_SELECT                                                0xdb02
++#define mmTD_PERFCOUNTER0_SELECT1                                               0xdb01
++#define mmTD_PERFCOUNTER0_LO                                                    0xd300
++#define mmTD_PERFCOUNTER1_LO                                                    0xd302
++#define mmTD_PERFCOUNTER0_HI                                                    0xd301
++#define mmTD_PERFCOUNTER1_HI                                                    0xd303
++#define mmTD_SCRATCH                                                            0x2533
++#define mmTA_CNTL                                                               0x2541
++#define mmTA_CNTL_AUX                                                           0x2542
++#define mmTA_RESERVED_010C                                                      0x2543
++#define mmTA_CS_BC_BASE_ADDR                                                    0xc380
++#define mmTA_CS_BC_BASE_ADDR_HI                                                 0xc381
++#define mmTA_STATUS                                                             0x2548
++#define mmTA_DEBUG_INDEX                                                        0x254c
++#define mmTA_DEBUG_DATA                                                         0x254d
++#define mmTA_PERFCOUNTER0_SELECT                                                0xdac0
++#define mmTA_PERFCOUNTER1_SELECT                                                0xdac2
++#define mmTA_PERFCOUNTER0_SELECT1                                               0xdac1
++#define mmTA_PERFCOUNTER0_LO                                                    0xd2c0
++#define mmTA_PERFCOUNTER1_LO                                                    0xd2c2
++#define mmTA_PERFCOUNTER0_HI                                                    0xd2c1
++#define mmTA_PERFCOUNTER1_HI                                                    0xd2c3
++#define mmTA_SCRATCH                                                            0x2564
++#define mmSH_HIDDEN_PRIVATE_BASE_VMID                                           0x2580
++#define mmSH_STATIC_MEM_CONFIG                                                  0x2581
++#define mmTCP_INVALIDATE                                                        0x2b00
++#define mmTCP_STATUS                                                            0x2b01
++#define mmTCP_CNTL                                                              0x2b02
++#define mmTCP_CHAN_STEER_LO                                                     0x2b03
++#define mmTCP_CHAN_STEER_HI                                                     0x2b04
++#define mmTCP_ADDR_CONFIG                                                       0x2b05
++#define mmTCP_CREDIT                                                            0x2b06
++#define mmTCP_PERFCOUNTER0_SELECT                                               0xdb40
++#define mmTCP_PERFCOUNTER1_SELECT                                               0xdb42
++#define mmTCP_PERFCOUNTER0_SELECT1                                              0xdb41
++#define mmTCP_PERFCOUNTER1_SELECT1                                              0xdb43
++#define mmTCP_PERFCOUNTER2_SELECT                                               0xdb44
++#define mmTCP_PERFCOUNTER3_SELECT                                               0xdb45
++#define mmTCP_PERFCOUNTER0_LO                                                   0xd340
++#define mmTCP_PERFCOUNTER1_LO                                                   0xd342
++#define mmTCP_PERFCOUNTER2_LO                                                   0xd344
++#define mmTCP_PERFCOUNTER3_LO                                                   0xd346
++#define mmTCP_PERFCOUNTER0_HI                                                   0xd341
++#define mmTCP_PERFCOUNTER1_HI                                                   0xd343
++#define mmTCP_PERFCOUNTER2_HI                                                   0xd345
++#define mmTCP_PERFCOUNTER3_HI                                                   0xd347
++#define mmTCP_BUFFER_ADDR_HASH_CNTL                                             0x2b16
++#define mmTCP_EDC_COUNTER                                                       0x2b17
++#define mmTC_CFG_L1_LOAD_POLICY0                                                0x2b1a
++#define mmTC_CFG_L1_LOAD_POLICY1                                                0x2b1b
++#define mmTC_CFG_L1_STORE_POLICY                                                0x2b1c
++#define mmTC_CFG_L2_LOAD_POLICY0                                                0x2b1d
++#define mmTC_CFG_L2_LOAD_POLICY1                                                0x2b1e
++#define mmTC_CFG_L2_STORE_POLICY0                                               0x2b1f
++#define mmTC_CFG_L2_STORE_POLICY1                                               0x2b20
++#define mmTC_CFG_L2_ATOMIC_POLICY                                               0x2b21
++#define mmTC_CFG_L1_VOLATILE                                                    0x2b22
++#define mmTC_CFG_L2_VOLATILE                                                    0x2b23
++#define mmTCP_WATCH0_ADDR_H                                                     0x32a0
++#define mmTCP_WATCH1_ADDR_H                                                     0x32a3
++#define mmTCP_WATCH2_ADDR_H                                                     0x32a6
++#define mmTCP_WATCH3_ADDR_H                                                     0x32a9
++#define mmTCP_WATCH0_ADDR_L                                                     0x32a1
++#define mmTCP_WATCH1_ADDR_L                                                     0x32a4
++#define mmTCP_WATCH2_ADDR_L                                                     0x32a7
++#define mmTCP_WATCH3_ADDR_L                                                     0x32aa
++#define mmTCP_WATCH0_CNTL                                                       0x32a2
++#define mmTCP_WATCH1_CNTL                                                       0x32a5
++#define mmTCP_WATCH2_CNTL                                                       0x32a8
++#define mmTCP_WATCH3_CNTL                                                       0x32ab
++#define mmTD_CGTT_CTRL                                                          0xf09c
++#define mmTA_CGTT_CTRL                                                          0xf09d
++#define mmCGTT_TCP_CLK_CTRL                                                     0xf09e
++#define mmCGTT_TCI_CLK_CTRL                                                     0xf09f
++#define mmTCI_STATUS                                                            0x2b61
++#define mmTCI_CNTL_1                                                            0x2b62
++#define mmTCI_CNTL_2                                                            0x2b63
++#define mmGDS_CONFIG                                                            0x25c0
++#define mmGDS_CNTL_STATUS                                                       0x25c1
++#define mmGDS_ENHANCE                                                           0x25c2
++#define mmGDS_PROTECTION_FAULT                                                  0x25c3
++#define mmGDS_VM_PROTECTION_FAULT                                               0x25c4
++#define mmGDS_SECDED_CNT                                                        0x25c5
++#define mmGDS_GRBM_SECDED_CNT                                                   0x25c6
++#define mmGDS_OA_DED                                                            0x25c7
++#define mmGDS_DEBUG_CNTL                                                        0x25c8
++#define mmGDS_DEBUG_DATA                                                        0x25c9
++#define mmCGTT_GDS_CLK_CTRL                                                     0xf0a0
++#define mmGDS_RD_ADDR                                                           0xc400
++#define mmGDS_RD_DATA                                                           0xc401
++#define mmGDS_RD_BURST_ADDR                                                     0xc402
++#define mmGDS_RD_BURST_COUNT                                                    0xc403
++#define mmGDS_RD_BURST_DATA                                                     0xc404
++#define mmGDS_WR_ADDR                                                           0xc405
++#define mmGDS_WR_DATA                                                           0xc406
++#define mmGDS_WR_BURST_ADDR                                                     0xc407
++#define mmGDS_WR_BURST_DATA                                                     0xc408
++#define mmGDS_WRITE_COMPLETE                                                    0xc409
++#define mmGDS_ATOM_CNTL                                                         0xc40a
++#define mmGDS_ATOM_COMPLETE                                                     0xc40b
++#define mmGDS_ATOM_BASE                                                         0xc40c
++#define mmGDS_ATOM_SIZE                                                         0xc40d
++#define mmGDS_ATOM_OFFSET0                                                      0xc40e
++#define mmGDS_ATOM_OFFSET1                                                      0xc40f
++#define mmGDS_ATOM_DST                                                          0xc410
++#define mmGDS_ATOM_OP                                                           0xc411
++#define mmGDS_ATOM_SRC0                                                         0xc412
++#define mmGDS_ATOM_SRC0_U                                                       0xc413
++#define mmGDS_ATOM_SRC1                                                         0xc414
++#define mmGDS_ATOM_SRC1_U                                                       0xc415
++#define mmGDS_ATOM_READ0                                                        0xc416
++#define mmGDS_ATOM_READ0_U                                                      0xc417
++#define mmGDS_ATOM_READ1                                                        0xc418
++#define mmGDS_ATOM_READ1_U                                                      0xc419
++#define mmGDS_GWS_RESOURCE_CNTL                                                 0xc41a
++#define mmGDS_GWS_RESOURCE                                                      0xc41b
++#define mmGDS_GWS_RESOURCE_CNT                                                  0xc41c
++#define mmGDS_OA_CNTL                                                           0xc41d
++#define mmGDS_OA_COUNTER                                                        0xc41e
++#define mmGDS_OA_ADDRESS                                                        0xc41f
++#define mmGDS_OA_INCDEC                                                         0xc420
++#define ixGDS_DEBUG_REG0                                                        0x0
++#define ixGDS_DEBUG_REG1                                                        0x1
++#define ixGDS_DEBUG_REG2                                                        0x2
++#define ixGDS_DEBUG_REG3                                                        0x3
++#define ixGDS_DEBUG_REG4                                                        0x4
++#define ixGDS_DEBUG_REG5                                                        0x5
++#define ixGDS_DEBUG_REG6                                                        0x6
++#define mmGDS_PERFCOUNTER0_SELECT                                               0xda80
++#define mmGDS_PERFCOUNTER1_SELECT                                               0xda81
++#define mmGDS_PERFCOUNTER2_SELECT                                               0xda82
++#define mmGDS_PERFCOUNTER3_SELECT                                               0xda83
++#define mmGDS_PERFCOUNTER0_LO                                                   0xd280
++#define mmGDS_PERFCOUNTER1_LO                                                   0xd282
++#define mmGDS_PERFCOUNTER2_LO                                                   0xd284
++#define mmGDS_PERFCOUNTER3_LO                                                   0xd286
++#define mmGDS_PERFCOUNTER0_HI                                                   0xd281
++#define mmGDS_PERFCOUNTER1_HI                                                   0xd283
++#define mmGDS_PERFCOUNTER2_HI                                                   0xd285
++#define mmGDS_PERFCOUNTER3_HI                                                   0xd287
++#define mmGDS_PERFCOUNTER0_SELECT1                                              0xda84
++#define mmGDS_VMID0_BASE                                                        0x3300
++#define mmGDS_VMID1_BASE                                                        0x3302
++#define mmGDS_VMID2_BASE                                                        0x3304
++#define mmGDS_VMID3_BASE                                                        0x3306
++#define mmGDS_VMID4_BASE                                                        0x3308
++#define mmGDS_VMID5_BASE                                                        0x330a
++#define mmGDS_VMID6_BASE                                                        0x330c
++#define mmGDS_VMID7_BASE                                                        0x330e
++#define mmGDS_VMID8_BASE                                                        0x3310
++#define mmGDS_VMID9_BASE                                                        0x3312
++#define mmGDS_VMID10_BASE                                                       0x3314
++#define mmGDS_VMID11_BASE                                                       0x3316
++#define mmGDS_VMID12_BASE                                                       0x3318
++#define mmGDS_VMID13_BASE                                                       0x331a
++#define mmGDS_VMID14_BASE                                                       0x331c
++#define mmGDS_VMID15_BASE                                                       0x331e
++#define mmGDS_VMID0_SIZE                                                        0x3301
++#define mmGDS_VMID1_SIZE                                                        0x3303
++#define mmGDS_VMID2_SIZE                                                        0x3305
++#define mmGDS_VMID3_SIZE                                                        0x3307
++#define mmGDS_VMID4_SIZE                                                        0x3309
++#define mmGDS_VMID5_SIZE                                                        0x330b
++#define mmGDS_VMID6_SIZE                                                        0x330d
++#define mmGDS_VMID7_SIZE                                                        0x330f
++#define mmGDS_VMID8_SIZE                                                        0x3311
++#define mmGDS_VMID9_SIZE                                                        0x3313
++#define mmGDS_VMID10_SIZE                                                       0x3315
++#define mmGDS_VMID11_SIZE                                                       0x3317
++#define mmGDS_VMID12_SIZE                                                       0x3319
++#define mmGDS_VMID13_SIZE                                                       0x331b
++#define mmGDS_VMID14_SIZE                                                       0x331d
++#define mmGDS_VMID15_SIZE                                                       0x331f
++#define mmGDS_GWS_VMID0                                                         0x3320
++#define mmGDS_GWS_VMID1                                                         0x3321
++#define mmGDS_GWS_VMID2                                                         0x3322
++#define mmGDS_GWS_VMID3                                                         0x3323
++#define mmGDS_GWS_VMID4                                                         0x3324
++#define mmGDS_GWS_VMID5                                                         0x3325
++#define mmGDS_GWS_VMID6                                                         0x3326
++#define mmGDS_GWS_VMID7                                                         0x3327
++#define mmGDS_GWS_VMID8                                                         0x3328
++#define mmGDS_GWS_VMID9                                                         0x3329
++#define mmGDS_GWS_VMID10                                                        0x332a
++#define mmGDS_GWS_VMID11                                                        0x332b
++#define mmGDS_GWS_VMID12                                                        0x332c
++#define mmGDS_GWS_VMID13                                                        0x332d
++#define mmGDS_GWS_VMID14                                                        0x332e
++#define mmGDS_GWS_VMID15                                                        0x332f
++#define mmGDS_OA_VMID0                                                          0x3330
++#define mmGDS_OA_VMID1                                                          0x3331
++#define mmGDS_OA_VMID2                                                          0x3332
++#define mmGDS_OA_VMID3                                                          0x3333
++#define mmGDS_OA_VMID4                                                          0x3334
++#define mmGDS_OA_VMID5                                                          0x3335
++#define mmGDS_OA_VMID6                                                          0x3336
++#define mmGDS_OA_VMID7                                                          0x3337
++#define mmGDS_OA_VMID8                                                          0x3338
++#define mmGDS_OA_VMID9                                                          0x3339
++#define mmGDS_OA_VMID10                                                         0x333a
++#define mmGDS_OA_VMID11                                                         0x333b
++#define mmGDS_OA_VMID12                                                         0x333c
++#define mmGDS_OA_VMID13                                                         0x333d
++#define mmGDS_OA_VMID14                                                         0x333e
++#define mmGDS_OA_VMID15                                                         0x333f
++#define mmGDS_GWS_RESET0                                                        0x3344
++#define mmGDS_GWS_RESET1                                                        0x3345
++#define mmGDS_GWS_RESOURCE_RESET                                                0x3346
++#define mmGDS_COMPUTE_MAX_WAVE_ID                                               0x3348
++#define mmGDS_OA_RESET_MASK                                                     0x3349
++#define mmGDS_OA_RESET                                                          0x334a
++#define mmCS_COPY_STATE                                                         0xa1f3
++#define mmGFX_COPY_STATE                                                        0xa1f4
++#define mmVGT_DRAW_INITIATOR                                                    0xa1fc
++#define mmVGT_EVENT_INITIATOR                                                   0xa2a4
++#define mmVGT_EVENT_ADDRESS_REG                                                 0xa1fe
++#define mmVGT_DMA_BASE_HI                                                       0xa1f9
++#define mmVGT_DMA_BASE                                                          0xa1fa
++#define mmVGT_DMA_INDEX_TYPE                                                    0xa29f
++#define mmVGT_DMA_NUM_INSTANCES                                                 0xa2a2
++#define mmIA_ENHANCE                                                            0xa29c
++#define mmVGT_DMA_SIZE                                                          0xa29d
++#define mmVGT_DMA_MAX_SIZE                                                      0xa29e
++#define mmVGT_DMA_PRIMITIVE_TYPE                                                0x2271
++#define mmVGT_DMA_CONTROL                                                       0x2272
++#define mmVGT_IMMED_DATA                                                        0xa1fd
++#define mmVGT_INDEX_TYPE                                                        0xc243
++#define mmVGT_NUM_INDICES                                                       0xc24c
++#define mmVGT_NUM_INSTANCES                                                     0xc24d
++#define mmVGT_PRIMITIVE_TYPE                                                    0xc242
++#define mmVGT_PRIMITIVEID_EN                                                    0xa2a1
++#define mmVGT_PRIMITIVEID_RESET                                                 0xa2a3
++#define mmVGT_VTX_CNT_EN                                                        0xa2ae
++#define mmVGT_REUSE_OFF                                                         0xa2ad
++#define mmVGT_INSTANCE_STEP_RATE_0                                              0xa2a8
++#define mmVGT_INSTANCE_STEP_RATE_1                                              0xa2a9
++#define mmVGT_MAX_VTX_INDX                                                      0xa100
++#define mmVGT_MIN_VTX_INDX                                                      0xa101
++#define mmVGT_INDX_OFFSET                                                       0xa102
++#define mmVGT_VERTEX_REUSE_BLOCK_CNTL                                           0xa316
++#define mmVGT_OUT_DEALLOC_CNTL                                                  0xa317
++#define mmVGT_MULTI_PRIM_IB_RESET_INDX                                          0xa103
++#define mmVGT_MULTI_PRIM_IB_RESET_EN                                            0xa2a5
++#define mmVGT_ENHANCE                                                           0xa294
++#define mmVGT_OUTPUT_PATH_CNTL                                                  0xa284
++#define mmVGT_HOS_CNTL                                                          0xa285
++#define mmVGT_HOS_MAX_TESS_LEVEL                                                0xa286
++#define mmVGT_HOS_MIN_TESS_LEVEL                                                0xa287
++#define mmVGT_HOS_REUSE_DEPTH                                                   0xa288
++#define mmVGT_GROUP_PRIM_TYPE                                                   0xa289
++#define mmVGT_GROUP_FIRST_DECR                                                  0xa28a
++#define mmVGT_GROUP_DECR                                                        0xa28b
++#define mmVGT_GROUP_VECT_0_CNTL                                                 0xa28c
++#define mmVGT_GROUP_VECT_1_CNTL                                                 0xa28d
++#define mmVGT_GROUP_VECT_0_FMT_CNTL                                             0xa28e
++#define mmVGT_GROUP_VECT_1_FMT_CNTL                                             0xa28f
++#define mmVGT_VTX_VECT_EJECT_REG                                                0x222c
++#define mmVGT_DMA_DATA_FIFO_DEPTH                                               0x222d
++#define mmVGT_DMA_REQ_FIFO_DEPTH                                                0x222e
++#define mmVGT_DRAW_INIT_FIFO_DEPTH                                              0x222f
++#define mmVGT_LAST_COPY_STATE                                                   0x2230
++#define mmCC_GC_SHADER_ARRAY_CONFIG                                             0x226f
++#define mmGC_USER_SHADER_ARRAY_CONFIG                                           0x2270
++#define mmVGT_GS_MODE                                                           0xa290
++#define mmVGT_GS_ONCHIP_CNTL                                                    0xa291
++#define mmVGT_GS_OUT_PRIM_TYPE                                                  0xa29b
++#define mmVGT_CACHE_INVALIDATION                                                0x2231
++#define mmVGT_RESET_DEBUG                                                       0x2232
++#define mmVGT_STRMOUT_DELAY                                                     0x2233
++#define mmVGT_FIFO_DEPTHS                                                       0x2234
++#define mmVGT_GS_PER_ES                                                         0xa295
++#define mmVGT_ES_PER_GS                                                         0xa296
++#define mmVGT_GS_PER_VS                                                         0xa297
++#define mmVGT_GS_VERTEX_REUSE                                                   0x2235
++#define mmVGT_MC_LAT_CNTL                                                       0x2236
++#define mmIA_CNTL_STATUS                                                        0x2237
++#define mmVGT_STRMOUT_CONFIG                                                    0xa2e5
++#define mmVGT_STRMOUT_BUFFER_SIZE_0                                             0xa2b4
++#define mmVGT_STRMOUT_BUFFER_SIZE_1                                             0xa2b8
++#define mmVGT_STRMOUT_BUFFER_SIZE_2                                             0xa2bc
++#define mmVGT_STRMOUT_BUFFER_SIZE_3                                             0xa2c0
++#define mmVGT_STRMOUT_BUFFER_OFFSET_0                                           0xa2b7
++#define mmVGT_STRMOUT_BUFFER_OFFSET_1                                           0xa2bb
++#define mmVGT_STRMOUT_BUFFER_OFFSET_2                                           0xa2bf
++#define mmVGT_STRMOUT_BUFFER_OFFSET_3                                           0xa2c3
++#define mmVGT_STRMOUT_VTX_STRIDE_0                                              0xa2b5
++#define mmVGT_STRMOUT_VTX_STRIDE_1                                              0xa2b9
++#define mmVGT_STRMOUT_VTX_STRIDE_2                                              0xa2bd
++#define mmVGT_STRMOUT_VTX_STRIDE_3                                              0xa2c1
++#define mmVGT_STRMOUT_BUFFER_CONFIG                                             0xa2e6
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                                      0xc244
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                                      0xc245
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                                      0xc246
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                                      0xc247
++#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                        0xa2ca
++#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                            0xa2cb
++#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                 0xa2cc
++#define mmVGT_GS_MAX_VERT_OUT                                                   0xa2ce
++#define mmIA_VMID_OVERRIDE                                                      0x2260
++#define mmVGT_SHADER_STAGES_EN                                                  0xa2d5
++#define mmVGT_LS_HS_CONFIG                                                      0xa2d6
++#define mmVGT_DMA_LS_HS_CONFIG                                                  0x2273
++#define mmVGT_TF_PARAM                                                          0xa2db
++#define mmVGT_TF_RING_SIZE                                                      0xc24e
++#define mmVGT_SYS_CONFIG                                                        0x2263
++#define mmVGT_HS_OFFCHIP_PARAM                                                  0xc24f
++#define mmVGT_TF_MEMORY_BASE                                                    0xc250
++#define mmVGT_GS_INSTANCE_CNT                                                   0xa2e4
++#define mmIA_MULTI_VGT_PARAM                                                    0xa2aa
++#define mmVGT_VS_MAX_WAVE_ID                                                    0x2268
++#define mmVGT_ESGS_RING_SIZE                                                    0xc240
++#define mmVGT_GSVS_RING_SIZE                                                    0xc241
++#define mmVGT_GSVS_RING_OFFSET_1                                                0xa298
++#define mmVGT_GSVS_RING_OFFSET_2                                                0xa299
++#define mmVGT_GSVS_RING_OFFSET_3                                                0xa29a
++#define mmVGT_ESGS_RING_ITEMSIZE                                                0xa2ab
++#define mmVGT_GSVS_RING_ITEMSIZE                                                0xa2ac
++#define mmVGT_GS_VERT_ITEMSIZE                                                  0xa2d7
++#define mmVGT_GS_VERT_ITEMSIZE_1                                                0xa2d8
++#define mmVGT_GS_VERT_ITEMSIZE_2                                                0xa2d9
++#define mmVGT_GS_VERT_ITEMSIZE_3                                                0xa2da
++#define mmWD_CNTL_STATUS                                                        0x223f
++#define mmWD_ENHANCE                                                            0xa2a0
++#define mmGFX_PIPE_CONTROL                                                      0x226d
++#define mmGFX_PIPE_PRIORITY                                                     0xf87f
++#define mmCGTT_VGT_CLK_CTRL                                                     0xf084
++#define mmCGTT_IA_CLK_CTRL                                                      0xf085
++#define mmCGTT_WD_CLK_CTRL                                                      0xf086
++#define mmVGT_DEBUG_CNTL                                                        0x2238
++#define mmVGT_DEBUG_DATA                                                        0x2239
++#define mmIA_DEBUG_CNTL                                                         0x223a
++#define mmIA_DEBUG_DATA                                                         0x223b
++#define mmVGT_CNTL_STATUS                                                       0x223c
++#define mmWD_DEBUG_CNTL                                                         0x223d
++#define mmWD_DEBUG_DATA                                                         0x223e
++#define mmCC_GC_PRIM_CONFIG                                                     0x2240
++#define mmGC_USER_PRIM_CONFIG                                                   0x2241
++#define ixWD_DEBUG_REG0                                                         0x0
++#define ixWD_DEBUG_REG1                                                         0x1
++#define ixWD_DEBUG_REG2                                                         0x2
++#define ixWD_DEBUG_REG3                                                         0x3
++#define ixWD_DEBUG_REG4                                                         0x4
++#define ixWD_DEBUG_REG5                                                         0x5
++#define ixIA_DEBUG_REG0                                                         0x0
++#define ixIA_DEBUG_REG1                                                         0x1
++#define ixIA_DEBUG_REG2                                                         0x2
++#define ixIA_DEBUG_REG3                                                         0x3
++#define ixIA_DEBUG_REG4                                                         0x4
++#define ixIA_DEBUG_REG5                                                         0x5
++#define ixIA_DEBUG_REG6                                                         0x6
++#define ixIA_DEBUG_REG7                                                         0x7
++#define ixIA_DEBUG_REG8                                                         0x8
++#define ixIA_DEBUG_REG9                                                         0x9
++#define ixVGT_DEBUG_REG0                                                        0x0
++#define ixVGT_DEBUG_REG1                                                        0x1
++#define ixVGT_DEBUG_REG2                                                        0x1e
++#define ixVGT_DEBUG_REG3                                                        0x1f
++#define ixVGT_DEBUG_REG4                                                        0x20
++#define ixVGT_DEBUG_REG5                                                        0x21
++#define ixVGT_DEBUG_REG6                                                        0x22
++#define ixVGT_DEBUG_REG7                                                        0x23
++#define ixVGT_DEBUG_REG8                                                        0x8
++#define ixVGT_DEBUG_REG9                                                        0x9
++#define ixVGT_DEBUG_REG10                                                       0xa
++#define ixVGT_DEBUG_REG11                                                       0xb
++#define ixVGT_DEBUG_REG12                                                       0xc
++#define ixVGT_DEBUG_REG13                                                       0xd
++#define ixVGT_DEBUG_REG14                                                       0xe
++#define ixVGT_DEBUG_REG15                                                       0xf
++#define ixVGT_DEBUG_REG16                                                       0x10
++#define ixVGT_DEBUG_REG17                                                       0x11
++#define ixVGT_DEBUG_REG18                                                       0x7
++#define ixVGT_DEBUG_REG19                                                       0x13
++#define ixVGT_DEBUG_REG20                                                       0x14
++#define ixVGT_DEBUG_REG21                                                       0x15
++#define ixVGT_DEBUG_REG22                                                       0x16
++#define ixVGT_DEBUG_REG23                                                       0x17
++#define ixVGT_DEBUG_REG24                                                       0x18
++#define ixVGT_DEBUG_REG25                                                       0x19
++#define ixVGT_DEBUG_REG26                                                       0x24
++#define ixVGT_DEBUG_REG27                                                       0x1b
++#define ixVGT_DEBUG_REG28                                                       0x1c
++#define ixVGT_DEBUG_REG29                                                       0x1d
++#define ixVGT_DEBUG_REG30                                                       0x25
++#define ixVGT_DEBUG_REG31                                                       0x26
++#define ixVGT_DEBUG_REG32                                                       0x27
++#define ixVGT_DEBUG_REG33                                                       0x28
++#define ixVGT_DEBUG_REG34                                                       0x29
++#define ixVGT_DEBUG_REG35                                                       0x2a
++#define mmVGT_PERFCOUNTER_SEID_MASK                                             0xd894
++#define mmVGT_PERFCOUNTER0_SELECT                                               0xd88c
++#define mmVGT_PERFCOUNTER1_SELECT                                               0xd88d
++#define mmVGT_PERFCOUNTER2_SELECT                                               0xd88e
++#define mmVGT_PERFCOUNTER3_SELECT                                               0xd88f
++#define mmVGT_PERFCOUNTER0_SELECT1                                              0xd890
++#define mmVGT_PERFCOUNTER1_SELECT1                                              0xd891
++#define mmVGT_PERFCOUNTER0_LO                                                   0xd090
++#define mmVGT_PERFCOUNTER1_LO                                                   0xd092
++#define mmVGT_PERFCOUNTER2_LO                                                   0xd094
++#define mmVGT_PERFCOUNTER3_LO                                                   0xd096
++#define mmVGT_PERFCOUNTER0_HI                                                   0xd091
++#define mmVGT_PERFCOUNTER1_HI                                                   0xd093
++#define mmVGT_PERFCOUNTER2_HI                                                   0xd095
++#define mmVGT_PERFCOUNTER3_HI                                                   0xd097
++#define mmIA_PERFCOUNTER0_SELECT                                                0xd884
++#define mmIA_PERFCOUNTER1_SELECT                                                0xd885
++#define mmIA_PERFCOUNTER2_SELECT                                                0xd886
++#define mmIA_PERFCOUNTER3_SELECT                                                0xd887
++#define mmIA_PERFCOUNTER0_SELECT1                                               0xd888
++#define mmIA_PERFCOUNTER0_LO                                                    0xd088
++#define mmIA_PERFCOUNTER1_LO                                                    0xd08a
++#define mmIA_PERFCOUNTER2_LO                                                    0xd08c
++#define mmIA_PERFCOUNTER3_LO                                                    0xd08e
++#define mmIA_PERFCOUNTER0_HI                                                    0xd089
++#define mmIA_PERFCOUNTER1_HI                                                    0xd08b
++#define mmIA_PERFCOUNTER2_HI                                                    0xd08d
++#define mmIA_PERFCOUNTER3_HI                                                    0xd08f
++#define mmWD_PERFCOUNTER0_SELECT                                                0xd880
++#define mmWD_PERFCOUNTER1_SELECT                                                0xd881
++#define mmWD_PERFCOUNTER2_SELECT                                                0xd882
++#define mmWD_PERFCOUNTER3_SELECT                                                0xd883
++#define mmWD_PERFCOUNTER0_LO                                                    0xd080
++#define mmWD_PERFCOUNTER1_LO                                                    0xd082
++#define mmWD_PERFCOUNTER2_LO                                                    0xd084
++#define mmWD_PERFCOUNTER3_LO                                                    0xd086
++#define mmWD_PERFCOUNTER0_HI                                                    0xd081
++#define mmWD_PERFCOUNTER1_HI                                                    0xd083
++#define mmWD_PERFCOUNTER2_HI                                                    0xd085
++#define mmWD_PERFCOUNTER3_HI                                                    0xd087
++#define mmDIDT_IND_INDEX                                                        0x3280
++#define mmDIDT_IND_DATA                                                         0x3281
++#define ixDIDT_SQ_CTRL0                                                         0x0
++#define ixDIDT_SQ_CTRL1                                                         0x1
++#define ixDIDT_SQ_CTRL2                                                         0x2
++#define ixDIDT_SQ_WEIGHT0_3                                                     0x10
++#define ixDIDT_SQ_WEIGHT4_7                                                     0x11
++#define ixDIDT_SQ_WEIGHT8_11                                                    0x12
++#define ixDIDT_DB_CTRL0                                                         0x20
++#define ixDIDT_DB_CTRL1                                                         0x21
++#define ixDIDT_DB_CTRL2                                                         0x22
++#define ixDIDT_DB_WEIGHT0_3                                                     0x30
++#define ixDIDT_DB_WEIGHT4_7                                                     0x31
++#define ixDIDT_DB_WEIGHT8_11                                                    0x32
++#define ixDIDT_TD_CTRL0                                                         0x40
++#define ixDIDT_TD_CTRL1                                                         0x41
++#define ixDIDT_TD_CTRL2                                                         0x42
++#define ixDIDT_TD_WEIGHT0_3                                                     0x50
++#define ixDIDT_TD_WEIGHT4_7                                                     0x51
++#define ixDIDT_TD_WEIGHT8_11                                                    0x52
++#define ixDIDT_TCP_CTRL0                                                        0x60
++#define ixDIDT_TCP_CTRL1                                                        0x61
++#define ixDIDT_TCP_CTRL2                                                        0x62
++#define ixDIDT_TCP_WEIGHT0_3                                                    0x70
++#define ixDIDT_TCP_WEIGHT4_7                                                    0x71
++#define ixDIDT_TCP_WEIGHT8_11                                                   0x72
++
++#endif /* GFX_7_0_D_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0008-yocto-amd-drm-amdgpu-add-amdgpu-h.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0008-yocto-amd-drm-amdgpu-add-amdgpu-h.patch
new file mode 100644
index 00000000..ea288dcf
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0008-yocto-amd-drm-amdgpu-add-amdgpu-h.patch
@@ -0,0 +1,27307 @@
+From 6bc04d9b9c93bac4ec60353620d631d0e470f890 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:20:39 -0400
+Subject: drm/amdgpu: add GCA 7.2 register headers
+
+These are register headers for the GCA (Graphics and Compute Array)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h
+new file mode 100644
+index 0000000..290ce6a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h
+@@ -0,0 +1,2557 @@
++/*
++ * GFX_7_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_7_2_D_H
++#define GFX_7_2_D_H
++
++#define mmCB_BLEND_RED                                                          0xa105
++#define mmCB_BLEND_GREEN                                                        0xa106
++#define mmCB_BLEND_BLUE                                                         0xa107
++#define mmCB_BLEND_ALPHA                                                        0xa108
++#define mmCB_COLOR_CONTROL                                                      0xa202
++#define mmCB_BLEND0_CONTROL                                                     0xa1e0
++#define mmCB_BLEND1_CONTROL                                                     0xa1e1
++#define mmCB_BLEND2_CONTROL                                                     0xa1e2
++#define mmCB_BLEND3_CONTROL                                                     0xa1e3
++#define mmCB_BLEND4_CONTROL                                                     0xa1e4
++#define mmCB_BLEND5_CONTROL                                                     0xa1e5
++#define mmCB_BLEND6_CONTROL                                                     0xa1e6
++#define mmCB_BLEND7_CONTROL                                                     0xa1e7
++#define mmCB_COLOR0_BASE                                                        0xa318
++#define mmCB_COLOR1_BASE                                                        0xa327
++#define mmCB_COLOR2_BASE                                                        0xa336
++#define mmCB_COLOR3_BASE                                                        0xa345
++#define mmCB_COLOR4_BASE                                                        0xa354
++#define mmCB_COLOR5_BASE                                                        0xa363
++#define mmCB_COLOR6_BASE                                                        0xa372
++#define mmCB_COLOR7_BASE                                                        0xa381
++#define mmCB_COLOR0_PITCH                                                       0xa319
++#define mmCB_COLOR1_PITCH                                                       0xa328
++#define mmCB_COLOR2_PITCH                                                       0xa337
++#define mmCB_COLOR3_PITCH                                                       0xa346
++#define mmCB_COLOR4_PITCH                                                       0xa355
++#define mmCB_COLOR5_PITCH                                                       0xa364
++#define mmCB_COLOR6_PITCH                                                       0xa373
++#define mmCB_COLOR7_PITCH                                                       0xa382
++#define mmCB_COLOR0_SLICE                                                       0xa31a
++#define mmCB_COLOR1_SLICE                                                       0xa329
++#define mmCB_COLOR2_SLICE                                                       0xa338
++#define mmCB_COLOR3_SLICE                                                       0xa347
++#define mmCB_COLOR4_SLICE                                                       0xa356
++#define mmCB_COLOR5_SLICE                                                       0xa365
++#define mmCB_COLOR6_SLICE                                                       0xa374
++#define mmCB_COLOR7_SLICE                                                       0xa383
++#define mmCB_COLOR0_VIEW                                                        0xa31b
++#define mmCB_COLOR1_VIEW                                                        0xa32a
++#define mmCB_COLOR2_VIEW                                                        0xa339
++#define mmCB_COLOR3_VIEW                                                        0xa348
++#define mmCB_COLOR4_VIEW                                                        0xa357
++#define mmCB_COLOR5_VIEW                                                        0xa366
++#define mmCB_COLOR6_VIEW                                                        0xa375
++#define mmCB_COLOR7_VIEW                                                        0xa384
++#define mmCB_COLOR0_INFO                                                        0xa31c
++#define mmCB_COLOR1_INFO                                                        0xa32b
++#define mmCB_COLOR2_INFO                                                        0xa33a
++#define mmCB_COLOR3_INFO                                                        0xa349
++#define mmCB_COLOR4_INFO                                                        0xa358
++#define mmCB_COLOR5_INFO                                                        0xa367
++#define mmCB_COLOR6_INFO                                                        0xa376
++#define mmCB_COLOR7_INFO                                                        0xa385
++#define mmCB_COLOR0_ATTRIB                                                      0xa31d
++#define mmCB_COLOR1_ATTRIB                                                      0xa32c
++#define mmCB_COLOR2_ATTRIB                                                      0xa33b
++#define mmCB_COLOR3_ATTRIB                                                      0xa34a
++#define mmCB_COLOR4_ATTRIB                                                      0xa359
++#define mmCB_COLOR5_ATTRIB                                                      0xa368
++#define mmCB_COLOR6_ATTRIB                                                      0xa377
++#define mmCB_COLOR7_ATTRIB                                                      0xa386
++#define mmCB_COLOR0_CMASK                                                       0xa31f
++#define mmCB_COLOR1_CMASK                                                       0xa32e
++#define mmCB_COLOR2_CMASK                                                       0xa33d
++#define mmCB_COLOR3_CMASK                                                       0xa34c
++#define mmCB_COLOR4_CMASK                                                       0xa35b
++#define mmCB_COLOR5_CMASK                                                       0xa36a
++#define mmCB_COLOR6_CMASK                                                       0xa379
++#define mmCB_COLOR7_CMASK                                                       0xa388
++#define mmCB_COLOR0_CMASK_SLICE                                                 0xa320
++#define mmCB_COLOR1_CMASK_SLICE                                                 0xa32f
++#define mmCB_COLOR2_CMASK_SLICE                                                 0xa33e
++#define mmCB_COLOR3_CMASK_SLICE                                                 0xa34d
++#define mmCB_COLOR4_CMASK_SLICE                                                 0xa35c
++#define mmCB_COLOR5_CMASK_SLICE                                                 0xa36b
++#define mmCB_COLOR6_CMASK_SLICE                                                 0xa37a
++#define mmCB_COLOR7_CMASK_SLICE                                                 0xa389
++#define mmCB_COLOR0_FMASK                                                       0xa321
++#define mmCB_COLOR1_FMASK                                                       0xa330
++#define mmCB_COLOR2_FMASK                                                       0xa33f
++#define mmCB_COLOR3_FMASK                                                       0xa34e
++#define mmCB_COLOR4_FMASK                                                       0xa35d
++#define mmCB_COLOR5_FMASK                                                       0xa36c
++#define mmCB_COLOR6_FMASK                                                       0xa37b
++#define mmCB_COLOR7_FMASK                                                       0xa38a
++#define mmCB_COLOR0_FMASK_SLICE                                                 0xa322
++#define mmCB_COLOR1_FMASK_SLICE                                                 0xa331
++#define mmCB_COLOR2_FMASK_SLICE                                                 0xa340
++#define mmCB_COLOR3_FMASK_SLICE                                                 0xa34f
++#define mmCB_COLOR4_FMASK_SLICE                                                 0xa35e
++#define mmCB_COLOR5_FMASK_SLICE                                                 0xa36d
++#define mmCB_COLOR6_FMASK_SLICE                                                 0xa37c
++#define mmCB_COLOR7_FMASK_SLICE                                                 0xa38b
++#define mmCB_COLOR0_CLEAR_WORD0                                                 0xa323
++#define mmCB_COLOR1_CLEAR_WORD0                                                 0xa332
++#define mmCB_COLOR2_CLEAR_WORD0                                                 0xa341
++#define mmCB_COLOR3_CLEAR_WORD0                                                 0xa350
++#define mmCB_COLOR4_CLEAR_WORD0                                                 0xa35f
++#define mmCB_COLOR5_CLEAR_WORD0                                                 0xa36e
++#define mmCB_COLOR6_CLEAR_WORD0                                                 0xa37d
++#define mmCB_COLOR7_CLEAR_WORD0                                                 0xa38c
++#define mmCB_COLOR0_CLEAR_WORD1                                                 0xa324
++#define mmCB_COLOR1_CLEAR_WORD1                                                 0xa333
++#define mmCB_COLOR2_CLEAR_WORD1                                                 0xa342
++#define mmCB_COLOR3_CLEAR_WORD1                                                 0xa351
++#define mmCB_COLOR4_CLEAR_WORD1                                                 0xa360
++#define mmCB_COLOR5_CLEAR_WORD1                                                 0xa36f
++#define mmCB_COLOR6_CLEAR_WORD1                                                 0xa37e
++#define mmCB_COLOR7_CLEAR_WORD1                                                 0xa38d
++#define mmCB_TARGET_MASK                                                        0xa08e
++#define mmCB_SHADER_MASK                                                        0xa08f
++#define mmCB_HW_CONTROL                                                         0x2684
++#define mmCB_HW_CONTROL_1                                                       0x2685
++#define mmCB_HW_CONTROL_2                                                       0x2686
++#define mmCB_HW_CONTROL_3                                                       0x2683
++#define mmCB_PERFCOUNTER_FILTER                                                 0xdc00
++#define mmCB_PERFCOUNTER0_SELECT                                                0xdc01
++#define mmCB_PERFCOUNTER0_SELECT1                                               0xdc02
++#define mmCB_PERFCOUNTER1_SELECT                                                0xdc03
++#define mmCB_PERFCOUNTER2_SELECT                                                0xdc04
++#define mmCB_PERFCOUNTER3_SELECT                                                0xdc05
++#define mmCB_PERFCOUNTER0_LO                                                    0xd406
++#define mmCB_PERFCOUNTER1_LO                                                    0xd408
++#define mmCB_PERFCOUNTER2_LO                                                    0xd40a
++#define mmCB_PERFCOUNTER3_LO                                                    0xd40c
++#define mmCB_PERFCOUNTER0_HI                                                    0xd407
++#define mmCB_PERFCOUNTER1_HI                                                    0xd409
++#define mmCB_PERFCOUNTER2_HI                                                    0xd40b
++#define mmCB_PERFCOUNTER3_HI                                                    0xd40d
++#define mmCB_CGTT_SCLK_CTRL                                                     0xf0a8
++#define mmCB_DEBUG_BUS_1                                                        0x2699
++#define mmCB_DEBUG_BUS_2                                                        0x269a
++#define mmCB_DEBUG_BUS_3                                                        0x269b
++#define mmCB_DEBUG_BUS_4                                                        0x269c
++#define mmCB_DEBUG_BUS_5                                                        0x269d
++#define mmCB_DEBUG_BUS_6                                                        0x269e
++#define mmCB_DEBUG_BUS_7                                                        0x269f
++#define mmCB_DEBUG_BUS_8                                                        0x26a0
++#define mmCB_DEBUG_BUS_9                                                        0x26a1
++#define mmCB_DEBUG_BUS_10                                                       0x26a2
++#define mmCB_DEBUG_BUS_11                                                       0x26a3
++#define mmCB_DEBUG_BUS_12                                                       0x26a4
++#define mmCB_DEBUG_BUS_13                                                       0x26a5
++#define mmCB_DEBUG_BUS_14                                                       0x26a6
++#define mmCB_DEBUG_BUS_15                                                       0x26a7
++#define mmCB_DEBUG_BUS_16                                                       0x26a8
++#define mmCB_DEBUG_BUS_17                                                       0x26a9
++#define mmCB_DEBUG_BUS_18                                                       0x26aa
++#define mmCP_DFY_CNTL                                                           0x3020
++#define mmCP_DFY_STAT                                                           0x3021
++#define mmCP_DFY_ADDR_HI                                                        0x3022
++#define mmCP_DFY_ADDR_LO                                                        0x3023
++#define mmCP_DFY_DATA_0                                                         0x3024
++#define mmCP_DFY_DATA_1                                                         0x3025
++#define mmCP_DFY_DATA_2                                                         0x3026
++#define mmCP_DFY_DATA_3                                                         0x3027
++#define mmCP_DFY_DATA_4                                                         0x3028
++#define mmCP_DFY_DATA_5                                                         0x3029
++#define mmCP_DFY_DATA_6                                                         0x302a
++#define mmCP_DFY_DATA_7                                                         0x302b
++#define mmCP_DFY_DATA_8                                                         0x302c
++#define mmCP_DFY_DATA_9                                                         0x302d
++#define mmCP_DFY_DATA_10                                                        0x302e
++#define mmCP_DFY_DATA_11                                                        0x302f
++#define mmCP_DFY_DATA_12                                                        0x3030
++#define mmCP_DFY_DATA_13                                                        0x3031
++#define mmCP_DFY_DATA_14                                                        0x3032
++#define mmCP_DFY_DATA_15                                                        0x3033
++#define mmCP_RB0_BASE                                                           0x3040
++#define mmCP_RB0_BASE_HI                                                        0x30b1
++#define mmCP_RB_BASE                                                            0x3040
++#define mmCP_RB1_BASE                                                           0x3060
++#define mmCP_RB1_BASE_HI                                                        0x30b2
++#define mmCP_RB2_BASE                                                           0x3065
++#define mmCP_RB0_CNTL                                                           0x3041
++#define mmCP_RB_CNTL                                                            0x3041
++#define mmCP_RB1_CNTL                                                           0x3061
++#define mmCP_RB2_CNTL                                                           0x3066
++#define mmCP_RB_RPTR_WR                                                         0x3042
++#define mmCP_RB0_RPTR_ADDR                                                      0x3043
++#define mmCP_RB_RPTR_ADDR                                                       0x3043
++#define mmCP_RB1_RPTR_ADDR                                                      0x3062
++#define mmCP_RB2_RPTR_ADDR                                                      0x3067
++#define mmCP_RB0_RPTR_ADDR_HI                                                   0x3044
++#define mmCP_RB_RPTR_ADDR_HI                                                    0x3044
++#define mmCP_RB1_RPTR_ADDR_HI                                                   0x3063
++#define mmCP_RB2_RPTR_ADDR_HI                                                   0x3068
++#define mmCP_RB0_WPTR                                                           0x3045
++#define mmCP_RB_WPTR                                                            0x3045
++#define mmCP_RB1_WPTR                                                           0x3064
++#define mmCP_RB2_WPTR                                                           0x3069
++#define mmCP_RB_WPTR_POLL_ADDR_LO                                               0x3046
++#define mmCP_RB_WPTR_POLL_ADDR_HI                                               0x3047
++#define mmGC_PRIV_MODE                                                          0x3048
++#define mmCP_INT_CNTL                                                           0x3049
++#define mmCP_INT_CNTL_RING0                                                     0x306a
++#define mmCP_INT_CNTL_RING1                                                     0x306b
++#define mmCP_INT_CNTL_RING2                                                     0x306c
++#define mmCP_INT_STATUS                                                         0x304a
++#define mmCP_INT_STATUS_RING0                                                   0x306d
++#define mmCP_INT_STATUS_RING1                                                   0x306e
++#define mmCP_INT_STATUS_RING2                                                   0x306f
++#define mmCP_DEVICE_ID                                                          0x304b
++#define mmCP_RING_PRIORITY_CNTS                                                 0x304c
++#define mmCP_ME0_PIPE_PRIORITY_CNTS                                             0x304c
++#define mmCP_RING0_PRIORITY                                                     0x304d
++#define mmCP_ME0_PIPE0_PRIORITY                                                 0x304d
++#define mmCP_RING1_PRIORITY                                                     0x304e
++#define mmCP_ME0_PIPE1_PRIORITY                                                 0x304e
++#define mmCP_RING2_PRIORITY                                                     0x304f
++#define mmCP_ME0_PIPE2_PRIORITY                                                 0x304f
++#define mmCP_ENDIAN_SWAP                                                        0x3050
++#define mmCP_RB_VMID                                                            0x3051
++#define mmCP_ME0_PIPE0_VMID                                                     0x3052
++#define mmCP_ME0_PIPE1_VMID                                                     0x3053
++#define mmCP_PFP_UCODE_ADDR                                                     0x3054
++#define mmCP_PFP_UCODE_DATA                                                     0x3055
++#define mmCP_ME_RAM_RADDR                                                       0x3056
++#define mmCP_ME_RAM_WADDR                                                       0x3057
++#define mmCP_ME_RAM_DATA                                                        0x3058
++#define mmCGTT_CPC_CLK_CTRL                                                     0xf0b2
++#define mmCGTT_CPF_CLK_CTRL                                                     0xf0b1
++#define mmCGTT_CP_CLK_CTRL                                                      0xf0b0
++#define mmCP_CE_UCODE_ADDR                                                      0x305a
++#define mmCP_CE_UCODE_DATA                                                      0x305b
++#define mmCP_MEC_ME1_UCODE_ADDR                                                 0x305c
++#define mmCP_MEC_ME1_UCODE_DATA                                                 0x305d
++#define mmCP_MEC_ME2_UCODE_ADDR                                                 0x305e
++#define mmCP_MEC_ME2_UCODE_DATA                                                 0x305f
++#define mmCP_PWR_CNTL                                                           0x3078
++#define mmCP_MEM_SLP_CNTL                                                       0x3079
++#define mmCP_ECC_FIRSTOCCURRENCE                                                0x307a
++#define mmCP_ECC_FIRSTOCCURRENCE_RING0                                          0x307b
++#define mmCP_ECC_FIRSTOCCURRENCE_RING1                                          0x307c
++#define mmCP_ECC_FIRSTOCCURRENCE_RING2                                          0x307d
++#define mmCP_CPF_DEBUG                                                          0x3080
++#define mmCP_FETCHER_SOURCE                                                     0x3082
++#define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
++#define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
++#define mmCPC_INT_CNTL                                                          0x30b4
++#define mmCP_ME1_PIPE0_INT_CNTL                                                 0x3085
++#define mmCP_ME1_PIPE1_INT_CNTL                                                 0x3086
++#define mmCP_ME1_PIPE2_INT_CNTL                                                 0x3087
++#define mmCP_ME1_PIPE3_INT_CNTL                                                 0x3088
++#define mmCP_ME2_PIPE0_INT_CNTL                                                 0x3089
++#define mmCP_ME2_PIPE1_INT_CNTL                                                 0x308a
++#define mmCP_ME2_PIPE2_INT_CNTL                                                 0x308b
++#define mmCP_ME2_PIPE3_INT_CNTL                                                 0x308c
++#define mmCPC_INT_STATUS                                                        0x30b5
++#define mmCP_ME1_PIPE0_INT_STATUS                                               0x308d
++#define mmCP_ME1_PIPE1_INT_STATUS                                               0x308e
++#define mmCP_ME1_PIPE2_INT_STATUS                                               0x308f
++#define mmCP_ME1_PIPE3_INT_STATUS                                               0x3090
++#define mmCP_ME2_PIPE0_INT_STATUS                                               0x3091
++#define mmCP_ME2_PIPE1_INT_STATUS                                               0x3092
++#define mmCP_ME2_PIPE2_INT_STATUS                                               0x3093
++#define mmCP_ME2_PIPE3_INT_STATUS                                               0x3094
++#define mmCP_ME1_INT_STAT_DEBUG                                                 0x3095
++#define mmCP_ME2_INT_STAT_DEBUG                                                 0x3096
++#define mmCP_ME1_PIPE_PRIORITY_CNTS                                             0x3099
++#define mmCP_ME1_PIPE0_PRIORITY                                                 0x309a
++#define mmCP_ME1_PIPE1_PRIORITY                                                 0x309b
++#define mmCP_ME1_PIPE2_PRIORITY                                                 0x309c
++#define mmCP_ME1_PIPE3_PRIORITY                                                 0x309d
++#define mmCP_ME2_PIPE_PRIORITY_CNTS                                             0x309e
++#define mmCP_ME2_PIPE0_PRIORITY                                                 0x309f
++#define mmCP_ME2_PIPE1_PRIORITY                                                 0x30a0
++#define mmCP_ME2_PIPE2_PRIORITY                                                 0x30a1
++#define mmCP_ME2_PIPE3_PRIORITY                                                 0x30a2
++#define mmCP_CE_PRGRM_CNTR_START                                                0x30a3
++#define mmCP_PFP_PRGRM_CNTR_START                                               0x30a4
++#define mmCP_ME_PRGRM_CNTR_START                                                0x30a5
++#define mmCP_MEC1_PRGRM_CNTR_START                                              0x30a6
++#define mmCP_MEC2_PRGRM_CNTR_START                                              0x30a7
++#define mmCP_CE_INTR_ROUTINE_START                                              0x30a8
++#define mmCP_PFP_INTR_ROUTINE_START                                             0x30a9
++#define mmCP_ME_INTR_ROUTINE_START                                              0x30aa
++#define mmCP_MEC1_INTR_ROUTINE_START                                            0x30ab
++#define mmCP_MEC2_INTR_ROUTINE_START                                            0x30ac
++#define mmCP_CONTEXT_CNTL                                                       0x30ad
++#define mmCP_MAX_CONTEXT                                                        0x30ae
++#define mmCP_IQ_WAIT_TIME1                                                      0x30af
++#define mmCP_IQ_WAIT_TIME2                                                      0x30b0
++#define mmCP_VMID_RESET                                                         0x30b3
++#define mmCP_VMID_PREEMPT                                                       0x30b6
++#define mmCPC_INT_CNTX_ID                                                       0x30b7
++#define mmCP_PQ_STATUS                                                          0x30b8
++#define mmCP_CPC_STATUS                                                         0x2084
++#define mmCP_CPC_BUSY_STAT                                                      0x2085
++#define mmCP_CPC_STALLED_STAT1                                                  0x2086
++#define mmCP_CPF_STATUS                                                         0x2087
++#define mmCP_CPF_BUSY_STAT                                                      0x2088
++#define mmCP_CPF_STALLED_STAT1                                                  0x2089
++#define mmCP_CPC_MC_CNTL                                                        0x208a
++#define mmCP_CPC_GRBM_FREE_COUNT                                                0x208b
++#define mmCP_MEC_CNTL                                                           0x208d
++#define mmCP_MEC_ME1_HEADER_DUMP                                                0x208e
++#define mmCP_MEC_ME2_HEADER_DUMP                                                0x208f
++#define mmCP_CPC_SCRATCH_INDEX                                                  0x2090
++#define mmCP_CPC_SCRATCH_DATA                                                   0x2091
++#define mmCPG_PERFCOUNTER1_SELECT                                               0xd800
++#define mmCPG_PERFCOUNTER1_LO                                                   0xd000
++#define mmCPG_PERFCOUNTER1_HI                                                   0xd001
++#define mmCPG_PERFCOUNTER0_SELECT1                                              0xd801
++#define mmCPG_PERFCOUNTER0_SELECT                                               0xd802
++#define mmCPG_PERFCOUNTER0_LO                                                   0xd002
++#define mmCPG_PERFCOUNTER0_HI                                                   0xd003
++#define mmCPC_PERFCOUNTER1_SELECT                                               0xd803
++#define mmCPC_PERFCOUNTER1_LO                                                   0xd004
++#define mmCPC_PERFCOUNTER1_HI                                                   0xd005
++#define mmCPC_PERFCOUNTER0_SELECT1                                              0xd804
++#define mmCPC_PERFCOUNTER0_SELECT                                               0xd809
++#define mmCPC_PERFCOUNTER0_LO                                                   0xd006
++#define mmCPC_PERFCOUNTER0_HI                                                   0xd007
++#define mmCPF_PERFCOUNTER1_SELECT                                               0xd805
++#define mmCPF_PERFCOUNTER1_LO                                                   0xd008
++#define mmCPF_PERFCOUNTER1_HI                                                   0xd009
++#define mmCPF_PERFCOUNTER0_SELECT1                                              0xd806
++#define mmCPF_PERFCOUNTER0_SELECT                                               0xd807
++#define mmCPF_PERFCOUNTER0_LO                                                   0xd00a
++#define mmCPF_PERFCOUNTER0_HI                                                   0xd00b
++#define mmCP_CPC_HALT_HYST_COUNT                                                0x20a7
++#define mmCP_DRAW_OBJECT                                                        0xd810
++#define mmCP_DRAW_OBJECT_COUNTER                                                0xd811
++#define mmCP_DRAW_WINDOW_MASK_HI                                                0xd812
++#define mmCP_DRAW_WINDOW_HI                                                     0xd813
++#define mmCP_DRAW_WINDOW_LO                                                     0xd814
++#define mmCP_DRAW_WINDOW_CNTL                                                   0xd815
++#define mmCP_PRT_LOD_STATS_CNTL0                                                0x20ad
++#define mmCP_PRT_LOD_STATS_CNTL1                                                0x20ae
++#define mmCP_PRT_LOD_STATS_CNTL2                                                0x20af
++#define mmCP_CE_COMPARE_COUNT                                                   0x20c0
++#define mmCP_CE_DE_COUNT                                                        0x20c1
++#define mmCP_DE_CE_COUNT                                                        0x20c2
++#define mmCP_DE_LAST_INVAL_COUNT                                                0x20c3
++#define mmCP_DE_DE_COUNT                                                        0x20c4
++#define mmCP_EOP_DONE_EVENT_CNTL                                                0xc0d5
++#define mmCP_EOP_DONE_DATA_CNTL                                                 0xc0d6
++#define mmCP_EOP_DONE_ADDR_LO                                                   0xc000
++#define mmCP_EOP_DONE_ADDR_HI                                                   0xc001
++#define mmCP_EOP_DONE_DATA_LO                                                   0xc002
++#define mmCP_EOP_DONE_DATA_HI                                                   0xc003
++#define mmCP_EOP_LAST_FENCE_LO                                                  0xc004
++#define mmCP_EOP_LAST_FENCE_HI                                                  0xc005
++#define mmCP_STREAM_OUT_ADDR_LO                                                 0xc006
++#define mmCP_STREAM_OUT_ADDR_HI                                                 0xc007
++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                                         0xc008
++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                                         0xc009
++#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO                                          0xc00a
++#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI                                          0xc00b
++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                                         0xc00c
++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                                         0xc00d
++#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO                                          0xc00e
++#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI                                          0xc00f
++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                                         0xc010
++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                                         0xc011
++#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO                                          0xc012
++#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI                                          0xc013
++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                                         0xc014
++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                                         0xc015
++#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO                                          0xc016
++#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI                                          0xc017
++#define mmCP_PIPE_STATS_ADDR_LO                                                 0xc018
++#define mmCP_PIPE_STATS_ADDR_HI                                                 0xc019
++#define mmCP_VGT_IAVERT_COUNT_LO                                                0xc01a
++#define mmCP_VGT_IAVERT_COUNT_HI                                                0xc01b
++#define mmCP_VGT_IAPRIM_COUNT_LO                                                0xc01c
++#define mmCP_VGT_IAPRIM_COUNT_HI                                                0xc01d
++#define mmCP_VGT_GSPRIM_COUNT_LO                                                0xc01e
++#define mmCP_VGT_GSPRIM_COUNT_HI                                                0xc01f
++#define mmCP_VGT_VSINVOC_COUNT_LO                                               0xc020
++#define mmCP_VGT_VSINVOC_COUNT_HI                                               0xc021
++#define mmCP_VGT_GSINVOC_COUNT_LO                                               0xc022
++#define mmCP_VGT_GSINVOC_COUNT_HI                                               0xc023
++#define mmCP_VGT_HSINVOC_COUNT_LO                                               0xc024
++#define mmCP_VGT_HSINVOC_COUNT_HI                                               0xc025
++#define mmCP_VGT_DSINVOC_COUNT_LO                                               0xc026
++#define mmCP_VGT_DSINVOC_COUNT_HI                                               0xc027
++#define mmCP_PA_CINVOC_COUNT_LO                                                 0xc028
++#define mmCP_PA_CINVOC_COUNT_HI                                                 0xc029
++#define mmCP_PA_CPRIM_COUNT_LO                                                  0xc02a
++#define mmCP_PA_CPRIM_COUNT_HI                                                  0xc02b
++#define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
++#define mmCP_SC_PSINVOC_COUNT0_HI                                               0xc02d
++#define mmCP_SC_PSINVOC_COUNT1_LO                                               0xc02e
++#define mmCP_SC_PSINVOC_COUNT1_HI                                               0xc02f
++#define mmCP_VGT_CSINVOC_COUNT_LO                                               0xc030
++#define mmCP_VGT_CSINVOC_COUNT_HI                                               0xc031
++#define mmCP_STRMOUT_CNTL                                                       0xc03f
++#define mmSCRATCH_REG0                                                          0xc040
++#define mmSCRATCH_REG1                                                          0xc041
++#define mmSCRATCH_REG2                                                          0xc042
++#define mmSCRATCH_REG3                                                          0xc043
++#define mmSCRATCH_REG4                                                          0xc044
++#define mmSCRATCH_REG5                                                          0xc045
++#define mmSCRATCH_REG6                                                          0xc046
++#define mmSCRATCH_REG7                                                          0xc047
++#define mmSCRATCH_UMSK                                                          0xc050
++#define mmSCRATCH_ADDR                                                          0xc051
++#define mmCP_PFP_ATOMIC_PREOP_LO                                                0xc052
++#define mmCP_PFP_ATOMIC_PREOP_HI                                                0xc053
++#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO                                           0xc054
++#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI                                           0xc055
++#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO                                           0xc056
++#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI                                           0xc057
++#define mmCP_APPEND_ADDR_LO                                                     0xc058
++#define mmCP_APPEND_ADDR_HI                                                     0xc059
++#define mmCP_APPEND_DATA                                                        0xc05a
++#define mmCP_APPEND_LAST_CS_FENCE                                               0xc05b
++#define mmCP_APPEND_LAST_PS_FENCE                                               0xc05c
++#define mmCP_ATOMIC_PREOP_LO                                                    0xc05d
++#define mmCP_ME_ATOMIC_PREOP_LO                                                 0xc05d
++#define mmCP_ATOMIC_PREOP_HI                                                    0xc05e
++#define mmCP_ME_ATOMIC_PREOP_HI                                                 0xc05e
++#define mmCP_GDS_ATOMIC0_PREOP_LO                                               0xc05f
++#define mmCP_ME_GDS_ATOMIC0_PREOP_LO                                            0xc05f
++#define mmCP_GDS_ATOMIC0_PREOP_HI                                               0xc060
++#define mmCP_ME_GDS_ATOMIC0_PREOP_HI                                            0xc060
++#define mmCP_GDS_ATOMIC1_PREOP_LO                                               0xc061
++#define mmCP_ME_GDS_ATOMIC1_PREOP_LO                                            0xc061
++#define mmCP_GDS_ATOMIC1_PREOP_HI                                               0xc062
++#define mmCP_ME_GDS_ATOMIC1_PREOP_HI                                            0xc062
++#define mmCP_ME_MC_WADDR_LO                                                     0xc069
++#define mmCP_ME_MC_WADDR_HI                                                     0xc06a
++#define mmCP_ME_MC_WDATA_LO                                                     0xc06b
++#define mmCP_ME_MC_WDATA_HI                                                     0xc06c
++#define mmCP_ME_MC_RADDR_LO                                                     0xc06d
++#define mmCP_ME_MC_RADDR_HI                                                     0xc06e
++#define mmCP_SEM_WAIT_TIMER                                                     0xc06f
++#define mmCP_SIG_SEM_ADDR_LO                                                    0xc070
++#define mmCP_SIG_SEM_ADDR_HI                                                    0xc071
++#define mmCP_WAIT_SEM_ADDR_LO                                                   0xc075
++#define mmCP_WAIT_SEM_ADDR_HI                                                   0xc076
++#define mmCP_WAIT_REG_MEM_TIMEOUT                                               0xc074
++#define mmCP_COHER_START_DELAY                                                  0xc07b
++#define mmCP_COHER_CNTL                                                         0xc07c
++#define mmCP_COHER_SIZE                                                         0xc07d
++#define mmCP_COHER_SIZE_HI                                                      0xc08c
++#define mmCP_COHER_BASE                                                         0xc07e
++#define mmCP_COHER_BASE_HI                                                      0xc079
++#define mmCP_COHER_STATUS                                                       0xc07f
++#define mmCOHER_DEST_BASE_0                                                     0xa092
++#define mmCOHER_DEST_BASE_1                                                     0xa093
++#define mmCOHER_DEST_BASE_2                                                     0xa07e
++#define mmCOHER_DEST_BASE_3                                                     0xa07f
++#define mmCOHER_DEST_BASE_HI_0                                                  0xa07a
++#define mmCOHER_DEST_BASE_HI_1                                                  0xa07b
++#define mmCOHER_DEST_BASE_HI_2                                                  0xa07c
++#define mmCOHER_DEST_BASE_HI_3                                                  0xa07d
++#define mmCP_DMA_ME_SRC_ADDR                                                    0xc080
++#define mmCP_DMA_ME_SRC_ADDR_HI                                                 0xc081
++#define mmCP_DMA_ME_DST_ADDR                                                    0xc082
++#define mmCP_DMA_ME_DST_ADDR_HI                                                 0xc083
++#define mmCP_DMA_ME_CONTROL                                                     0xc078
++#define mmCP_DMA_ME_COMMAND                                                     0xc084
++#define mmCP_DMA_PFP_SRC_ADDR                                                   0xc085
++#define mmCP_DMA_PFP_SRC_ADDR_HI                                                0xc086
++#define mmCP_DMA_PFP_DST_ADDR                                                   0xc087
++#define mmCP_DMA_PFP_DST_ADDR_HI                                                0xc088
++#define mmCP_DMA_PFP_CONTROL                                                    0xc077
++#define mmCP_DMA_PFP_COMMAND                                                    0xc089
++#define mmCP_DMA_CNTL                                                           0xc08a
++#define mmCP_DMA_READ_TAGS                                                      0xc08b
++#define mmCP_PFP_IB_CONTROL                                                     0xc08d
++#define mmCP_PFP_LOAD_CONTROL                                                   0xc08e
++#define mmCP_SCRATCH_INDEX                                                      0xc08f
++#define mmCP_SCRATCH_DATA                                                       0xc090
++#define mmCP_RB_OFFSET                                                          0xc091
++#define mmCP_IB1_OFFSET                                                         0xc092
++#define mmCP_IB2_OFFSET                                                         0xc093
++#define mmCP_IB1_PREAMBLE_BEGIN                                                 0xc094
++#define mmCP_IB1_PREAMBLE_END                                                   0xc095
++#define mmCP_IB2_PREAMBLE_BEGIN                                                 0xc096
++#define mmCP_IB2_PREAMBLE_END                                                   0xc097
++#define mmCP_CE_IB1_OFFSET                                                      0xc098
++#define mmCP_CE_IB2_OFFSET                                                      0xc099
++#define mmCP_CE_COUNTER                                                         0xc09a
++#define mmCP_STALLED_STAT1                                                      0x219d
++#define mmCP_STALLED_STAT2                                                      0x219e
++#define mmCP_STALLED_STAT3                                                      0x219c
++#define mmCP_BUSY_STAT                                                          0x219f
++#define mmCP_STAT                                                               0x21a0
++#define mmCP_ME_HEADER_DUMP                                                     0x21a1
++#define mmCP_PFP_HEADER_DUMP                                                    0x21a2
++#define mmCP_GRBM_FREE_COUNT                                                    0x21a3
++#define mmCP_CE_HEADER_DUMP                                                     0x21a4
++#define mmCP_MC_PACK_DELAY_CNT                                                  0x21a7
++#define mmCP_MC_TAG_CNTL                                                        0x21a8
++#define mmCP_MC_TAG_DATA                                                        0x21a9
++#define mmCP_CSF_STAT                                                           0x21b4
++#define mmCP_CSF_CNTL                                                           0x21b5
++#define mmCP_ME_CNTL                                                            0x21b6
++#define mmCP_CNTX_STAT                                                          0x21b8
++#define mmCP_ME_PREEMPTION                                                      0x21b9
++#define mmCP_RB0_RPTR                                                           0x21c0
++#define mmCP_RB_RPTR                                                            0x21c0
++#define mmCP_RB1_RPTR                                                           0x21bf
++#define mmCP_RB2_RPTR                                                           0x21be
++#define mmCP_RB_WPTR_DELAY                                                      0x21c1
++#define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
++#define mmCP_CE_INIT_BASE_LO                                                    0xc0c3
++#define mmCP_CE_INIT_BASE_HI                                                    0xc0c4
++#define mmCP_CE_INIT_BUFSZ                                                      0xc0c5
++#define mmCP_CE_IB1_BASE_LO                                                     0xc0c6
++#define mmCP_CE_IB1_BASE_HI                                                     0xc0c7
++#define mmCP_CE_IB1_BUFSZ                                                       0xc0c8
++#define mmCP_CE_IB2_BASE_LO                                                     0xc0c9
++#define mmCP_CE_IB2_BASE_HI                                                     0xc0ca
++#define mmCP_CE_IB2_BUFSZ                                                       0xc0cb
++#define mmCP_IB1_BASE_LO                                                        0xc0cc
++#define mmCP_IB1_BASE_HI                                                        0xc0cd
++#define mmCP_IB1_BUFSZ                                                          0xc0ce
++#define mmCP_IB2_BASE_LO                                                        0xc0cf
++#define mmCP_IB2_BASE_HI                                                        0xc0d0
++#define mmCP_IB2_BUFSZ                                                          0xc0d1
++#define mmCP_ST_BASE_LO                                                         0xc0d2
++#define mmCP_ST_BASE_HI                                                         0xc0d3
++#define mmCP_ST_BUFSZ                                                           0xc0d4
++#define mmCP_ROQ_THRESHOLDS                                                     0x21bc
++#define mmCP_MEQ_STQ_THRESHOLD                                                  0x21bd
++#define mmCP_ROQ1_THRESHOLDS                                                    0x21d5
++#define mmCP_ROQ2_THRESHOLDS                                                    0x21d6
++#define mmCP_STQ_THRESHOLDS                                                     0x21d7
++#define mmCP_QUEUE_THRESHOLDS                                                   0x21d8
++#define mmCP_MEQ_THRESHOLDS                                                     0x21d9
++#define mmCP_ROQ_AVAIL                                                          0x21da
++#define mmCP_STQ_AVAIL                                                          0x21db
++#define mmCP_ROQ2_AVAIL                                                         0x21dc
++#define mmCP_MEQ_AVAIL                                                          0x21dd
++#define mmCP_CMD_INDEX                                                          0x21de
++#define mmCP_CMD_DATA                                                           0x21df
++#define mmCP_ROQ_RB_STAT                                                        0x21e0
++#define mmCP_ROQ_IB1_STAT                                                       0x21e1
++#define mmCP_ROQ_IB2_STAT                                                       0x21e2
++#define mmCP_STQ_STAT                                                           0x21e3
++#define mmCP_STQ_WR_STAT                                                        0x21e4
++#define mmCP_MEQ_STAT                                                           0x21e5
++#define mmCP_CEQ1_AVAIL                                                         0x21e6
++#define mmCP_CEQ2_AVAIL                                                         0x21e7
++#define mmCP_CE_ROQ_RB_STAT                                                     0x21e8
++#define mmCP_CE_ROQ_IB1_STAT                                                    0x21e9
++#define mmCP_CE_ROQ_IB2_STAT                                                    0x21ea
++#define mmCP_INT_STAT_DEBUG                                                     0x21f7
++#define mmCP_PERFMON_CNTL                                                       0xd808
++#define mmCP_PERFMON_CNTX_CNTL                                                  0xa0d8
++#define mmCP_RINGID                                                             0xa0d9
++#define mmCP_PIPEID                                                             0xa0d9
++#define mmCP_VMID                                                               0xa0da
++#define mmCP_HPD_ROQ_OFFSETS                                                    0x3240
++#define mmCP_HPD_EOP_BASE_ADDR                                                  0x3241
++#define mmCP_HPD_EOP_BASE_ADDR_HI                                               0x3242
++#define mmCP_HPD_EOP_VMID                                                       0x3243
++#define mmCP_HPD_EOP_CONTROL                                                    0x3244
++#define mmCP_MQD_BASE_ADDR                                                      0x3245
++#define mmCP_MQD_BASE_ADDR_HI                                                   0x3246
++#define mmCP_HQD_ACTIVE                                                         0x3247
++#define mmCP_HQD_VMID                                                           0x3248
++#define mmCP_HQD_PERSISTENT_STATE                                               0x3249
++#define mmCP_HQD_PIPE_PRIORITY                                                  0x324a
++#define mmCP_HQD_QUEUE_PRIORITY                                                 0x324b
++#define mmCP_HQD_QUANTUM                                                        0x324c
++#define mmCP_HQD_PQ_BASE                                                        0x324d
++#define mmCP_HQD_PQ_BASE_HI                                                     0x324e
++#define mmCP_HQD_PQ_RPTR                                                        0x324f
++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
++#define mmCP_HQD_PQ_WPTR_POLL_ADDR                                              0x3252
++#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                                           0x3253
++#define mmCP_HQD_PQ_DOORBELL_CONTROL                                            0x3254
++#define mmCP_HQD_PQ_WPTR                                                        0x3255
++#define mmCP_HQD_PQ_CONTROL                                                     0x3256
++#define mmCP_HQD_IB_BASE_ADDR                                                   0x3257
++#define mmCP_HQD_IB_BASE_ADDR_HI                                                0x3258
++#define mmCP_HQD_IB_RPTR                                                        0x3259
++#define mmCP_HQD_IB_CONTROL                                                     0x325a
++#define mmCP_HQD_IQ_TIMER                                                       0x325b
++#define mmCP_HQD_IQ_RPTR                                                        0x325c
++#define mmCP_HQD_DEQUEUE_REQUEST                                                0x325d
++#define mmCP_HQD_DMA_OFFLOAD                                                    0x325e
++#define mmCP_HQD_SEMA_CMD                                                       0x325f
++#define mmCP_HQD_MSG_TYPE                                                       0x3260
++#define mmCP_HQD_ATOMIC0_PREOP_LO                                               0x3261
++#define mmCP_HQD_ATOMIC0_PREOP_HI                                               0x3262
++#define mmCP_HQD_ATOMIC1_PREOP_LO                                               0x3263
++#define mmCP_HQD_ATOMIC1_PREOP_HI                                               0x3264
++#define mmCP_HQD_HQ_SCHEDULER0                                                  0x3265
++#define mmCP_HQD_HQ_SCHEDULER1                                                  0x3266
++#define mmCP_MQD_CONTROL                                                        0x3267
++#define mmDB_Z_READ_BASE                                                        0xa012
++#define mmDB_STENCIL_READ_BASE                                                  0xa013
++#define mmDB_Z_WRITE_BASE                                                       0xa014
++#define mmDB_STENCIL_WRITE_BASE                                                 0xa015
++#define mmDB_DEPTH_INFO                                                         0xa00f
++#define mmDB_Z_INFO                                                             0xa010
++#define mmDB_STENCIL_INFO                                                       0xa011
++#define mmDB_DEPTH_SIZE                                                         0xa016
++#define mmDB_DEPTH_SLICE                                                        0xa017
++#define mmDB_DEPTH_VIEW                                                         0xa002
++#define mmDB_RENDER_CONTROL                                                     0xa000
++#define mmDB_COUNT_CONTROL                                                      0xa001
++#define mmDB_RENDER_OVERRIDE                                                    0xa003
++#define mmDB_RENDER_OVERRIDE2                                                   0xa004
++#define mmDB_EQAA                                                               0xa201
++#define mmDB_SHADER_CONTROL                                                     0xa203
++#define mmDB_DEPTH_BOUNDS_MIN                                                   0xa008
++#define mmDB_DEPTH_BOUNDS_MAX                                                   0xa009
++#define mmDB_STENCIL_CLEAR                                                      0xa00a
++#define mmDB_DEPTH_CLEAR                                                        0xa00b
++#define mmDB_HTILE_DATA_BASE                                                    0xa005
++#define mmDB_HTILE_SURFACE                                                      0xa2af
++#define mmDB_PRELOAD_CONTROL                                                    0xa2b2
++#define mmDB_STENCILREFMASK                                                     0xa10c
++#define mmDB_STENCILREFMASK_BF                                                  0xa10d
++#define mmDB_SRESULTS_COMPARE_STATE0                                            0xa2b0
++#define mmDB_SRESULTS_COMPARE_STATE1                                            0xa2b1
++#define mmDB_DEPTH_CONTROL                                                      0xa200
++#define mmDB_STENCIL_CONTROL                                                    0xa10b
++#define mmDB_ALPHA_TO_MASK                                                      0xa2dc
++#define mmDB_PERFCOUNTER0_SELECT                                                0xdc40
++#define mmDB_PERFCOUNTER1_SELECT                                                0xdc42
++#define mmDB_PERFCOUNTER2_SELECT                                                0xdc44
++#define mmDB_PERFCOUNTER3_SELECT                                                0xdc46
++#define mmDB_PERFCOUNTER0_SELECT1                                               0xdc41
++#define mmDB_PERFCOUNTER1_SELECT1                                               0xdc43
++#define mmDB_PERFCOUNTER0_LO                                                    0xd440
++#define mmDB_PERFCOUNTER1_LO                                                    0xd442
++#define mmDB_PERFCOUNTER2_LO                                                    0xd444
++#define mmDB_PERFCOUNTER3_LO                                                    0xd446
++#define mmDB_PERFCOUNTER0_HI                                                    0xd441
++#define mmDB_PERFCOUNTER1_HI                                                    0xd443
++#define mmDB_PERFCOUNTER2_HI                                                    0xd445
++#define mmDB_PERFCOUNTER3_HI                                                    0xd447
++#define mmDB_DEBUG                                                              0x260c
++#define mmDB_DEBUG2                                                             0x260d
++#define mmDB_DEBUG3                                                             0x260e
++#define mmDB_DEBUG4                                                             0x260f
++#define mmDB_CREDIT_LIMIT                                                       0x2614
++#define mmDB_WATERMARKS                                                         0x2615
++#define mmDB_SUBTILE_CONTROL                                                    0x2616
++#define mmDB_FREE_CACHELINES                                                    0x2617
++#define mmDB_FIFO_DEPTH1                                                        0x2618
++#define mmDB_FIFO_DEPTH2                                                        0x2619
++#define mmDB_CGTT_CLK_CTRL_0                                                    0xf0a4
++#define mmDB_ZPASS_COUNT_LOW                                                    0xc3fe
++#define mmDB_ZPASS_COUNT_HI                                                     0xc3ff
++#define mmDB_RING_CONTROL                                                       0x261b
++#define mmDB_READ_DEBUG_0                                                       0x2620
++#define mmDB_READ_DEBUG_1                                                       0x2621
++#define mmDB_READ_DEBUG_2                                                       0x2622
++#define mmDB_READ_DEBUG_3                                                       0x2623
++#define mmDB_READ_DEBUG_4                                                       0x2624
++#define mmDB_READ_DEBUG_5                                                       0x2625
++#define mmDB_READ_DEBUG_6                                                       0x2626
++#define mmDB_READ_DEBUG_7                                                       0x2627
++#define mmDB_READ_DEBUG_8                                                       0x2628
++#define mmDB_READ_DEBUG_9                                                       0x2629
++#define mmDB_READ_DEBUG_A                                                       0x262a
++#define mmDB_READ_DEBUG_B                                                       0x262b
++#define mmDB_READ_DEBUG_C                                                       0x262c
++#define mmDB_READ_DEBUG_D                                                       0x262d
++#define mmDB_READ_DEBUG_E                                                       0x262e
++#define mmDB_READ_DEBUG_F                                                       0x262f
++#define mmDB_OCCLUSION_COUNT0_LOW                                               0xc3c0
++#define mmDB_OCCLUSION_COUNT0_HI                                                0xc3c1
++#define mmDB_OCCLUSION_COUNT1_LOW                                               0xc3c2
++#define mmDB_OCCLUSION_COUNT1_HI                                                0xc3c3
++#define mmDB_OCCLUSION_COUNT2_LOW                                               0xc3c4
++#define mmDB_OCCLUSION_COUNT2_HI                                                0xc3c5
++#define mmDB_OCCLUSION_COUNT3_LOW                                               0xc3c6
++#define mmDB_OCCLUSION_COUNT3_HI                                                0xc3c7
++#define mmCC_RB_REDUNDANCY                                                      0x263c
++#define mmCC_RB_BACKEND_DISABLE                                                 0x263d
++#define mmGC_USER_RB_REDUNDANCY                                                 0x26de
++#define mmGC_USER_RB_BACKEND_DISABLE                                            0x26df
++#define mmGB_ADDR_CONFIG                                                        0x263e
++#define mmGB_BACKEND_MAP                                                        0x263f
++#define mmGB_GPU_ID                                                             0x2640
++#define mmCC_RB_DAISY_CHAIN                                                     0x2641
++#define mmGB_TILE_MODE0                                                         0x2644
++#define mmGB_TILE_MODE1                                                         0x2645
++#define mmGB_TILE_MODE2                                                         0x2646
++#define mmGB_TILE_MODE3                                                         0x2647
++#define mmGB_TILE_MODE4                                                         0x2648
++#define mmGB_TILE_MODE5                                                         0x2649
++#define mmGB_TILE_MODE6                                                         0x264a
++#define mmGB_TILE_MODE7                                                         0x264b
++#define mmGB_TILE_MODE8                                                         0x264c
++#define mmGB_TILE_MODE9                                                         0x264d
++#define mmGB_TILE_MODE10                                                        0x264e
++#define mmGB_TILE_MODE11                                                        0x264f
++#define mmGB_TILE_MODE12                                                        0x2650
++#define mmGB_TILE_MODE13                                                        0x2651
++#define mmGB_TILE_MODE14                                                        0x2652
++#define mmGB_TILE_MODE15                                                        0x2653
++#define mmGB_TILE_MODE16                                                        0x2654
++#define mmGB_TILE_MODE17                                                        0x2655
++#define mmGB_TILE_MODE18                                                        0x2656
++#define mmGB_TILE_MODE19                                                        0x2657
++#define mmGB_TILE_MODE20                                                        0x2658
++#define mmGB_TILE_MODE21                                                        0x2659
++#define mmGB_TILE_MODE22                                                        0x265a
++#define mmGB_TILE_MODE23                                                        0x265b
++#define mmGB_TILE_MODE24                                                        0x265c
++#define mmGB_TILE_MODE25                                                        0x265d
++#define mmGB_TILE_MODE26                                                        0x265e
++#define mmGB_TILE_MODE27                                                        0x265f
++#define mmGB_TILE_MODE28                                                        0x2660
++#define mmGB_TILE_MODE29                                                        0x2661
++#define mmGB_TILE_MODE30                                                        0x2662
++#define mmGB_TILE_MODE31                                                        0x2663
++#define mmGB_MACROTILE_MODE0                                                    0x2664
++#define mmGB_MACROTILE_MODE1                                                    0x2665
++#define mmGB_MACROTILE_MODE2                                                    0x2666
++#define mmGB_MACROTILE_MODE3                                                    0x2667
++#define mmGB_MACROTILE_MODE4                                                    0x2668
++#define mmGB_MACROTILE_MODE5                                                    0x2669
++#define mmGB_MACROTILE_MODE6                                                    0x266a
++#define mmGB_MACROTILE_MODE7                                                    0x266b
++#define mmGB_MACROTILE_MODE8                                                    0x266c
++#define mmGB_MACROTILE_MODE9                                                    0x266d
++#define mmGB_MACROTILE_MODE10                                                   0x266e
++#define mmGB_MACROTILE_MODE11                                                   0x266f
++#define mmGB_MACROTILE_MODE12                                                   0x2670
++#define mmGB_MACROTILE_MODE13                                                   0x2671
++#define mmGB_MACROTILE_MODE14                                                   0x2672
++#define mmGB_MACROTILE_MODE15                                                   0x2673
++#define mmGB_EDC_MODE                                                           0x307e
++#define mmCC_GC_EDC_CONFIG                                                      0x3098
++#define mmRAS_SIGNATURE_CONTROL                                                 0x3380
++#define mmRAS_SIGNATURE_MASK                                                    0x3381
++#define mmRAS_SX_SIGNATURE0                                                     0x3382
++#define mmRAS_SX_SIGNATURE1                                                     0x3383
++#define mmRAS_SX_SIGNATURE2                                                     0x3384
++#define mmRAS_SX_SIGNATURE3                                                     0x3385
++#define mmRAS_DB_SIGNATURE0                                                     0x338b
++#define mmRAS_PA_SIGNATURE0                                                     0x338c
++#define mmRAS_VGT_SIGNATURE0                                                    0x338d
++#define mmRAS_SQ_SIGNATURE0                                                     0x338e
++#define mmRAS_SC_SIGNATURE0                                                     0x338f
++#define mmRAS_SC_SIGNATURE1                                                     0x3390
++#define mmRAS_SC_SIGNATURE2                                                     0x3391
++#define mmRAS_SC_SIGNATURE3                                                     0x3392
++#define mmRAS_SC_SIGNATURE4                                                     0x3393
++#define mmRAS_SC_SIGNATURE5                                                     0x3394
++#define mmRAS_SC_SIGNATURE6                                                     0x3395
++#define mmRAS_SC_SIGNATURE7                                                     0x3396
++#define mmRAS_IA_SIGNATURE0                                                     0x3397
++#define mmRAS_IA_SIGNATURE1                                                     0x3398
++#define mmRAS_SPI_SIGNATURE0                                                    0x3399
++#define mmRAS_SPI_SIGNATURE1                                                    0x339a
++#define mmRAS_TA_SIGNATURE0                                                     0x339b
++#define mmRAS_TD_SIGNATURE0                                                     0x339c
++#define mmRAS_CB_SIGNATURE0                                                     0x339d
++#define mmRAS_BCI_SIGNATURE0                                                    0x339e
++#define mmRAS_BCI_SIGNATURE1                                                    0x339f
++#define mmGRBM_CAM_INDEX                                                        0x3000
++#define mmGRBM_CAM_DATA                                                         0x3001
++#define mmGRBM_CNTL                                                             0x2000
++#define mmGRBM_SKEW_CNTL                                                        0x2001
++#define mmGRBM_PWR_CNTL                                                         0x2003
++#define mmGRBM_STATUS                                                           0x2004
++#define mmGRBM_STATUS2                                                          0x2002
++#define mmGRBM_STATUS_SE0                                                       0x2005
++#define mmGRBM_STATUS_SE1                                                       0x2006
++#define mmGRBM_STATUS_SE2                                                       0x200e
++#define mmGRBM_STATUS_SE3                                                       0x200f
++#define mmGRBM_SOFT_RESET                                                       0x2008
++#define mmGRBM_DEBUG_CNTL                                                       0x2009
++#define mmGRBM_DEBUG_DATA                                                       0x200a
++#define mmGRBM_GFX_INDEX                                                        0xc200
++#define mmGRBM_GFX_CLKEN_CNTL                                                   0x200c
++#define mmGRBM_WAIT_IDLE_CLOCKS                                                 0x200d
++#define mmGRBM_DEBUG                                                            0x2014
++#define mmGRBM_DEBUG_SNAPSHOT                                                   0x2015
++#define mmGRBM_READ_ERROR                                                       0x2016
++#define mmGRBM_READ_ERROR2                                                      0x2017
++#define mmGRBM_INT_CNTL                                                         0x2018
++#define mmGRBM_PERFCOUNTER0_SELECT                                              0xd840
++#define mmGRBM_PERFCOUNTER1_SELECT                                              0xd841
++#define mmGRBM_SE0_PERFCOUNTER_SELECT                                           0xd842
++#define mmGRBM_SE1_PERFCOUNTER_SELECT                                           0xd843
++#define mmGRBM_SE2_PERFCOUNTER_SELECT                                           0xd844
++#define mmGRBM_SE3_PERFCOUNTER_SELECT                                           0xd845
++#define mmGRBM_PERFCOUNTER0_LO                                                  0xd040
++#define mmGRBM_PERFCOUNTER0_HI                                                  0xd041
++#define mmGRBM_PERFCOUNTER1_LO                                                  0xd043
++#define mmGRBM_PERFCOUNTER1_HI                                                  0xd044
++#define mmGRBM_SE0_PERFCOUNTER_LO                                               0xd045
++#define mmGRBM_SE0_PERFCOUNTER_HI                                               0xd046
++#define mmGRBM_SE1_PERFCOUNTER_LO                                               0xd047
++#define mmGRBM_SE1_PERFCOUNTER_HI                                               0xd048
++#define mmGRBM_SE2_PERFCOUNTER_LO                                               0xd049
++#define mmGRBM_SE2_PERFCOUNTER_HI                                               0xd04a
++#define mmGRBM_SE3_PERFCOUNTER_LO                                               0xd04b
++#define mmGRBM_SE3_PERFCOUNTER_HI                                               0xd04c
++#define mmGRBM_SCRATCH_REG0                                                     0x2040
++#define mmGRBM_SCRATCH_REG1                                                     0x2041
++#define mmGRBM_SCRATCH_REG2                                                     0x2042
++#define mmGRBM_SCRATCH_REG3                                                     0x2043
++#define mmGRBM_SCRATCH_REG4                                                     0x2044
++#define mmGRBM_SCRATCH_REG5                                                     0x2045
++#define mmGRBM_SCRATCH_REG6                                                     0x2046
++#define mmGRBM_SCRATCH_REG7                                                     0x2047
++#define mmDEBUG_INDEX                                                           0x203c
++#define mmDEBUG_DATA                                                            0x203d
++#define mmGRBM_NOWHERE                                                          0x203f
++#define mmPA_CL_VPORT_XSCALE                                                    0xa10f
++#define mmPA_CL_VPORT_XOFFSET                                                   0xa110
++#define mmPA_CL_VPORT_YSCALE                                                    0xa111
++#define mmPA_CL_VPORT_YOFFSET                                                   0xa112
++#define mmPA_CL_VPORT_ZSCALE                                                    0xa113
++#define mmPA_CL_VPORT_ZOFFSET                                                   0xa114
++#define mmPA_CL_VPORT_XSCALE_1                                                  0xa115
++#define mmPA_CL_VPORT_XSCALE_2                                                  0xa11b
++#define mmPA_CL_VPORT_XSCALE_3                                                  0xa121
++#define mmPA_CL_VPORT_XSCALE_4                                                  0xa127
++#define mmPA_CL_VPORT_XSCALE_5                                                  0xa12d
++#define mmPA_CL_VPORT_XSCALE_6                                                  0xa133
++#define mmPA_CL_VPORT_XSCALE_7                                                  0xa139
++#define mmPA_CL_VPORT_XSCALE_8                                                  0xa13f
++#define mmPA_CL_VPORT_XSCALE_9                                                  0xa145
++#define mmPA_CL_VPORT_XSCALE_10                                                 0xa14b
++#define mmPA_CL_VPORT_XSCALE_11                                                 0xa151
++#define mmPA_CL_VPORT_XSCALE_12                                                 0xa157
++#define mmPA_CL_VPORT_XSCALE_13                                                 0xa15d
++#define mmPA_CL_VPORT_XSCALE_14                                                 0xa163
++#define mmPA_CL_VPORT_XSCALE_15                                                 0xa169
++#define mmPA_CL_VPORT_XOFFSET_1                                                 0xa116
++#define mmPA_CL_VPORT_XOFFSET_2                                                 0xa11c
++#define mmPA_CL_VPORT_XOFFSET_3                                                 0xa122
++#define mmPA_CL_VPORT_XOFFSET_4                                                 0xa128
++#define mmPA_CL_VPORT_XOFFSET_5                                                 0xa12e
++#define mmPA_CL_VPORT_XOFFSET_6                                                 0xa134
++#define mmPA_CL_VPORT_XOFFSET_7                                                 0xa13a
++#define mmPA_CL_VPORT_XOFFSET_8                                                 0xa140
++#define mmPA_CL_VPORT_XOFFSET_9                                                 0xa146
++#define mmPA_CL_VPORT_XOFFSET_10                                                0xa14c
++#define mmPA_CL_VPORT_XOFFSET_11                                                0xa152
++#define mmPA_CL_VPORT_XOFFSET_12                                                0xa158
++#define mmPA_CL_VPORT_XOFFSET_13                                                0xa15e
++#define mmPA_CL_VPORT_XOFFSET_14                                                0xa164
++#define mmPA_CL_VPORT_XOFFSET_15                                                0xa16a
++#define mmPA_CL_VPORT_YSCALE_1                                                  0xa117
++#define mmPA_CL_VPORT_YSCALE_2                                                  0xa11d
++#define mmPA_CL_VPORT_YSCALE_3                                                  0xa123
++#define mmPA_CL_VPORT_YSCALE_4                                                  0xa129
++#define mmPA_CL_VPORT_YSCALE_5                                                  0xa12f
++#define mmPA_CL_VPORT_YSCALE_6                                                  0xa135
++#define mmPA_CL_VPORT_YSCALE_7                                                  0xa13b
++#define mmPA_CL_VPORT_YSCALE_8                                                  0xa141
++#define mmPA_CL_VPORT_YSCALE_9                                                  0xa147
++#define mmPA_CL_VPORT_YSCALE_10                                                 0xa14d
++#define mmPA_CL_VPORT_YSCALE_11                                                 0xa153
++#define mmPA_CL_VPORT_YSCALE_12                                                 0xa159
++#define mmPA_CL_VPORT_YSCALE_13                                                 0xa15f
++#define mmPA_CL_VPORT_YSCALE_14                                                 0xa165
++#define mmPA_CL_VPORT_YSCALE_15                                                 0xa16b
++#define mmPA_CL_VPORT_YOFFSET_1                                                 0xa118
++#define mmPA_CL_VPORT_YOFFSET_2                                                 0xa11e
++#define mmPA_CL_VPORT_YOFFSET_3                                                 0xa124
++#define mmPA_CL_VPORT_YOFFSET_4                                                 0xa12a
++#define mmPA_CL_VPORT_YOFFSET_5                                                 0xa130
++#define mmPA_CL_VPORT_YOFFSET_6                                                 0xa136
++#define mmPA_CL_VPORT_YOFFSET_7                                                 0xa13c
++#define mmPA_CL_VPORT_YOFFSET_8                                                 0xa142
++#define mmPA_CL_VPORT_YOFFSET_9                                                 0xa148
++#define mmPA_CL_VPORT_YOFFSET_10                                                0xa14e
++#define mmPA_CL_VPORT_YOFFSET_11                                                0xa154
++#define mmPA_CL_VPORT_YOFFSET_12                                                0xa15a
++#define mmPA_CL_VPORT_YOFFSET_13                                                0xa160
++#define mmPA_CL_VPORT_YOFFSET_14                                                0xa166
++#define mmPA_CL_VPORT_YOFFSET_15                                                0xa16c
++#define mmPA_CL_VPORT_ZSCALE_1                                                  0xa119
++#define mmPA_CL_VPORT_ZSCALE_2                                                  0xa11f
++#define mmPA_CL_VPORT_ZSCALE_3                                                  0xa125
++#define mmPA_CL_VPORT_ZSCALE_4                                                  0xa12b
++#define mmPA_CL_VPORT_ZSCALE_5                                                  0xa131
++#define mmPA_CL_VPORT_ZSCALE_6                                                  0xa137
++#define mmPA_CL_VPORT_ZSCALE_7                                                  0xa13d
++#define mmPA_CL_VPORT_ZSCALE_8                                                  0xa143
++#define mmPA_CL_VPORT_ZSCALE_9                                                  0xa149
++#define mmPA_CL_VPORT_ZSCALE_10                                                 0xa14f
++#define mmPA_CL_VPORT_ZSCALE_11                                                 0xa155
++#define mmPA_CL_VPORT_ZSCALE_12                                                 0xa15b
++#define mmPA_CL_VPORT_ZSCALE_13                                                 0xa161
++#define mmPA_CL_VPORT_ZSCALE_14                                                 0xa167
++#define mmPA_CL_VPORT_ZSCALE_15                                                 0xa16d
++#define mmPA_CL_VPORT_ZOFFSET_1                                                 0xa11a
++#define mmPA_CL_VPORT_ZOFFSET_2                                                 0xa120
++#define mmPA_CL_VPORT_ZOFFSET_3                                                 0xa126
++#define mmPA_CL_VPORT_ZOFFSET_4                                                 0xa12c
++#define mmPA_CL_VPORT_ZOFFSET_5                                                 0xa132
++#define mmPA_CL_VPORT_ZOFFSET_6                                                 0xa138
++#define mmPA_CL_VPORT_ZOFFSET_7                                                 0xa13e
++#define mmPA_CL_VPORT_ZOFFSET_8                                                 0xa144
++#define mmPA_CL_VPORT_ZOFFSET_9                                                 0xa14a
++#define mmPA_CL_VPORT_ZOFFSET_10                                                0xa150
++#define mmPA_CL_VPORT_ZOFFSET_11                                                0xa156
++#define mmPA_CL_VPORT_ZOFFSET_12                                                0xa15c
++#define mmPA_CL_VPORT_ZOFFSET_13                                                0xa162
++#define mmPA_CL_VPORT_ZOFFSET_14                                                0xa168
++#define mmPA_CL_VPORT_ZOFFSET_15                                                0xa16e
++#define mmPA_CL_VTE_CNTL                                                        0xa206
++#define mmPA_CL_VS_OUT_CNTL                                                     0xa207
++#define mmPA_CL_NANINF_CNTL                                                     0xa208
++#define mmPA_CL_CLIP_CNTL                                                       0xa204
++#define mmPA_CL_GB_VERT_CLIP_ADJ                                                0xa2fa
++#define mmPA_CL_GB_VERT_DISC_ADJ                                                0xa2fb
++#define mmPA_CL_GB_HORZ_CLIP_ADJ                                                0xa2fc
++#define mmPA_CL_GB_HORZ_DISC_ADJ                                                0xa2fd
++#define mmPA_CL_UCP_0_X                                                         0xa16f
++#define mmPA_CL_UCP_0_Y                                                         0xa170
++#define mmPA_CL_UCP_0_Z                                                         0xa171
++#define mmPA_CL_UCP_0_W                                                         0xa172
++#define mmPA_CL_UCP_1_X                                                         0xa173
++#define mmPA_CL_UCP_1_Y                                                         0xa174
++#define mmPA_CL_UCP_1_Z                                                         0xa175
++#define mmPA_CL_UCP_1_W                                                         0xa176
++#define mmPA_CL_UCP_2_X                                                         0xa177
++#define mmPA_CL_UCP_2_Y                                                         0xa178
++#define mmPA_CL_UCP_2_Z                                                         0xa179
++#define mmPA_CL_UCP_2_W                                                         0xa17a
++#define mmPA_CL_UCP_3_X                                                         0xa17b
++#define mmPA_CL_UCP_3_Y                                                         0xa17c
++#define mmPA_CL_UCP_3_Z                                                         0xa17d
++#define mmPA_CL_UCP_3_W                                                         0xa17e
++#define mmPA_CL_UCP_4_X                                                         0xa17f
++#define mmPA_CL_UCP_4_Y                                                         0xa180
++#define mmPA_CL_UCP_4_Z                                                         0xa181
++#define mmPA_CL_UCP_4_W                                                         0xa182
++#define mmPA_CL_UCP_5_X                                                         0xa183
++#define mmPA_CL_UCP_5_Y                                                         0xa184
++#define mmPA_CL_UCP_5_Z                                                         0xa185
++#define mmPA_CL_UCP_5_W                                                         0xa186
++#define mmPA_CL_POINT_X_RAD                                                     0xa1f5
++#define mmPA_CL_POINT_Y_RAD                                                     0xa1f6
++#define mmPA_CL_POINT_SIZE                                                      0xa1f7
++#define mmPA_CL_POINT_CULL_RAD                                                  0xa1f8
++#define mmPA_CL_ENHANCE                                                         0x2285
++#define mmPA_CL_RESET_DEBUG                                                     0x2286
++#define mmPA_SU_VTX_CNTL                                                        0xa2f9
++#define mmPA_SU_POINT_SIZE                                                      0xa280
++#define mmPA_SU_POINT_MINMAX                                                    0xa281
++#define mmPA_SU_LINE_CNTL                                                       0xa282
++#define mmPA_SU_LINE_STIPPLE_CNTL                                               0xa209
++#define mmPA_SU_LINE_STIPPLE_SCALE                                              0xa20a
++#define mmPA_SU_PRIM_FILTER_CNTL                                                0xa20b
++#define mmPA_SU_SC_MODE_CNTL                                                    0xa205
++#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                                         0xa2de
++#define mmPA_SU_POLY_OFFSET_CLAMP                                               0xa2df
++#define mmPA_SU_POLY_OFFSET_FRONT_SCALE                                         0xa2e0
++#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                                        0xa2e1
++#define mmPA_SU_POLY_OFFSET_BACK_SCALE                                          0xa2e2
++#define mmPA_SU_POLY_OFFSET_BACK_OFFSET                                         0xa2e3
++#define mmPA_SU_HARDWARE_SCREEN_OFFSET                                          0xa08d
++#define mmPA_SU_LINE_STIPPLE_VALUE                                              0xc280
++#define mmPA_SU_PERFCOUNTER0_SELECT                                             0xd900
++#define mmPA_SU_PERFCOUNTER0_SELECT1                                            0xd901
++#define mmPA_SU_PERFCOUNTER1_SELECT                                             0xd902
++#define mmPA_SU_PERFCOUNTER1_SELECT1                                            0xd903
++#define mmPA_SU_PERFCOUNTER2_SELECT                                             0xd904
++#define mmPA_SU_PERFCOUNTER3_SELECT                                             0xd905
++#define mmPA_SU_PERFCOUNTER0_LO                                                 0xd100
++#define mmPA_SU_PERFCOUNTER0_HI                                                 0xd101
++#define mmPA_SU_PERFCOUNTER1_LO                                                 0xd102
++#define mmPA_SU_PERFCOUNTER1_HI                                                 0xd103
++#define mmPA_SU_PERFCOUNTER2_LO                                                 0xd104
++#define mmPA_SU_PERFCOUNTER2_HI                                                 0xd105
++#define mmPA_SU_PERFCOUNTER3_LO                                                 0xd106
++#define mmPA_SU_PERFCOUNTER3_HI                                                 0xd107
++#define mmPA_SC_AA_CONFIG                                                       0xa2f8
++#define mmPA_SC_AA_MASK_X0Y0_X1Y0                                               0xa30e
++#define mmPA_SC_AA_MASK_X0Y1_X1Y1                                               0xa30f
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                     0xa2fe
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                     0xa2ff
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                     0xa300
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                     0xa301
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                     0xa302
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                     0xa303
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                     0xa304
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                     0xa305
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                     0xa306
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                     0xa307
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                     0xa308
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                     0xa309
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                     0xa30a
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                     0xa30b
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                     0xa30c
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                     0xa30d
++#define mmPA_SC_CENTROID_PRIORITY_0                                             0xa2f5
++#define mmPA_SC_CENTROID_PRIORITY_1                                             0xa2f6
++#define mmPA_SC_CLIPRECT_0_TL                                                   0xa084
++#define mmPA_SC_CLIPRECT_0_BR                                                   0xa085
++#define mmPA_SC_CLIPRECT_1_TL                                                   0xa086
++#define mmPA_SC_CLIPRECT_1_BR                                                   0xa087
++#define mmPA_SC_CLIPRECT_2_TL                                                   0xa088
++#define mmPA_SC_CLIPRECT_2_BR                                                   0xa089
++#define mmPA_SC_CLIPRECT_3_TL                                                   0xa08a
++#define mmPA_SC_CLIPRECT_3_BR                                                   0xa08b
++#define mmPA_SC_CLIPRECT_RULE                                                   0xa083
++#define mmPA_SC_EDGERULE                                                        0xa08c
++#define mmPA_SC_LINE_CNTL                                                       0xa2f7
++#define mmPA_SC_LINE_STIPPLE                                                    0xa283
++#define mmPA_SC_MODE_CNTL_0                                                     0xa292
++#define mmPA_SC_MODE_CNTL_1                                                     0xa293
++#define mmPA_SC_RASTER_CONFIG                                                   0xa0d4
++#define mmPA_SC_RASTER_CONFIG_1                                                 0xa0d5
++#define mmPA_SC_SCREEN_EXTENT_CONTROL                                           0xa0d6
++#define mmPA_SC_GENERIC_SCISSOR_TL                                              0xa090
++#define mmPA_SC_GENERIC_SCISSOR_BR                                              0xa091
++#define mmPA_SC_SCREEN_SCISSOR_TL                                               0xa00c
++#define mmPA_SC_SCREEN_SCISSOR_BR                                               0xa00d
++#define mmPA_SC_WINDOW_OFFSET                                                   0xa080
++#define mmPA_SC_WINDOW_SCISSOR_TL                                               0xa081
++#define mmPA_SC_WINDOW_SCISSOR_BR                                               0xa082
++#define mmPA_SC_VPORT_SCISSOR_0_TL                                              0xa094
++#define mmPA_SC_VPORT_SCISSOR_1_TL                                              0xa096
++#define mmPA_SC_VPORT_SCISSOR_2_TL                                              0xa098
++#define mmPA_SC_VPORT_SCISSOR_3_TL                                              0xa09a
++#define mmPA_SC_VPORT_SCISSOR_4_TL                                              0xa09c
++#define mmPA_SC_VPORT_SCISSOR_5_TL                                              0xa09e
++#define mmPA_SC_VPORT_SCISSOR_6_TL                                              0xa0a0
++#define mmPA_SC_VPORT_SCISSOR_7_TL                                              0xa0a2
++#define mmPA_SC_VPORT_SCISSOR_8_TL                                              0xa0a4
++#define mmPA_SC_VPORT_SCISSOR_9_TL                                              0xa0a6
++#define mmPA_SC_VPORT_SCISSOR_10_TL                                             0xa0a8
++#define mmPA_SC_VPORT_SCISSOR_11_TL                                             0xa0aa
++#define mmPA_SC_VPORT_SCISSOR_12_TL                                             0xa0ac
++#define mmPA_SC_VPORT_SCISSOR_13_TL                                             0xa0ae
++#define mmPA_SC_VPORT_SCISSOR_14_TL                                             0xa0b0
++#define mmPA_SC_VPORT_SCISSOR_15_TL                                             0xa0b2
++#define mmPA_SC_VPORT_SCISSOR_0_BR                                              0xa095
++#define mmPA_SC_VPORT_SCISSOR_1_BR                                              0xa097
++#define mmPA_SC_VPORT_SCISSOR_2_BR                                              0xa099
++#define mmPA_SC_VPORT_SCISSOR_3_BR                                              0xa09b
++#define mmPA_SC_VPORT_SCISSOR_4_BR                                              0xa09d
++#define mmPA_SC_VPORT_SCISSOR_5_BR                                              0xa09f
++#define mmPA_SC_VPORT_SCISSOR_6_BR                                              0xa0a1
++#define mmPA_SC_VPORT_SCISSOR_7_BR                                              0xa0a3
++#define mmPA_SC_VPORT_SCISSOR_8_BR                                              0xa0a5
++#define mmPA_SC_VPORT_SCISSOR_9_BR                                              0xa0a7
++#define mmPA_SC_VPORT_SCISSOR_10_BR                                             0xa0a9
++#define mmPA_SC_VPORT_SCISSOR_11_BR                                             0xa0ab
++#define mmPA_SC_VPORT_SCISSOR_12_BR                                             0xa0ad
++#define mmPA_SC_VPORT_SCISSOR_13_BR                                             0xa0af
++#define mmPA_SC_VPORT_SCISSOR_14_BR                                             0xa0b1
++#define mmPA_SC_VPORT_SCISSOR_15_BR                                             0xa0b3
++#define mmPA_SC_VPORT_ZMIN_0                                                    0xa0b4
++#define mmPA_SC_VPORT_ZMIN_1                                                    0xa0b6
++#define mmPA_SC_VPORT_ZMIN_2                                                    0xa0b8
++#define mmPA_SC_VPORT_ZMIN_3                                                    0xa0ba
++#define mmPA_SC_VPORT_ZMIN_4                                                    0xa0bc
++#define mmPA_SC_VPORT_ZMIN_5                                                    0xa0be
++#define mmPA_SC_VPORT_ZMIN_6                                                    0xa0c0
++#define mmPA_SC_VPORT_ZMIN_7                                                    0xa0c2
++#define mmPA_SC_VPORT_ZMIN_8                                                    0xa0c4
++#define mmPA_SC_VPORT_ZMIN_9                                                    0xa0c6
++#define mmPA_SC_VPORT_ZMIN_10                                                   0xa0c8
++#define mmPA_SC_VPORT_ZMIN_11                                                   0xa0ca
++#define mmPA_SC_VPORT_ZMIN_12                                                   0xa0cc
++#define mmPA_SC_VPORT_ZMIN_13                                                   0xa0ce
++#define mmPA_SC_VPORT_ZMIN_14                                                   0xa0d0
++#define mmPA_SC_VPORT_ZMIN_15                                                   0xa0d2
++#define mmPA_SC_VPORT_ZMAX_0                                                    0xa0b5
++#define mmPA_SC_VPORT_ZMAX_1                                                    0xa0b7
++#define mmPA_SC_VPORT_ZMAX_2                                                    0xa0b9
++#define mmPA_SC_VPORT_ZMAX_3                                                    0xa0bb
++#define mmPA_SC_VPORT_ZMAX_4                                                    0xa0bd
++#define mmPA_SC_VPORT_ZMAX_5                                                    0xa0bf
++#define mmPA_SC_VPORT_ZMAX_6                                                    0xa0c1
++#define mmPA_SC_VPORT_ZMAX_7                                                    0xa0c3
++#define mmPA_SC_VPORT_ZMAX_8                                                    0xa0c5
++#define mmPA_SC_VPORT_ZMAX_9                                                    0xa0c7
++#define mmPA_SC_VPORT_ZMAX_10                                                   0xa0c9
++#define mmPA_SC_VPORT_ZMAX_11                                                   0xa0cb
++#define mmPA_SC_VPORT_ZMAX_12                                                   0xa0cd
++#define mmPA_SC_VPORT_ZMAX_13                                                   0xa0cf
++#define mmPA_SC_VPORT_ZMAX_14                                                   0xa0d1
++#define mmPA_SC_VPORT_ZMAX_15                                                   0xa0d3
++#define mmPA_SC_ENHANCE                                                         0x22fc
++#define mmPA_SC_FIFO_SIZE                                                       0x22f3
++#define mmPA_SC_IF_FIFO_SIZE                                                    0x22f5
++#define mmPA_SC_FORCE_EOV_MAX_CNTS                                              0x22c9
++#define mmPA_SC_LINE_STIPPLE_STATE                                              0xc281
++#define mmPA_SC_SCREEN_EXTENT_MIN_0                                             0xc284
++#define mmPA_SC_SCREEN_EXTENT_MAX_0                                             0xc285
++#define mmPA_SC_SCREEN_EXTENT_MIN_1                                             0xc286
++#define mmPA_SC_SCREEN_EXTENT_MAX_1                                             0xc28b
++#define mmPA_SC_PERFCOUNTER0_SELECT                                             0xd940
++#define mmPA_SC_PERFCOUNTER0_SELECT1                                            0xd941
++#define mmPA_SC_PERFCOUNTER1_SELECT                                             0xd942
++#define mmPA_SC_PERFCOUNTER2_SELECT                                             0xd943
++#define mmPA_SC_PERFCOUNTER3_SELECT                                             0xd944
++#define mmPA_SC_PERFCOUNTER4_SELECT                                             0xd945
++#define mmPA_SC_PERFCOUNTER5_SELECT                                             0xd946
++#define mmPA_SC_PERFCOUNTER6_SELECT                                             0xd947
++#define mmPA_SC_PERFCOUNTER7_SELECT                                             0xd948
++#define mmPA_SC_PERFCOUNTER0_LO                                                 0xd140
++#define mmPA_SC_PERFCOUNTER0_HI                                                 0xd141
++#define mmPA_SC_PERFCOUNTER1_LO                                                 0xd142
++#define mmPA_SC_PERFCOUNTER1_HI                                                 0xd143
++#define mmPA_SC_PERFCOUNTER2_LO                                                 0xd144
++#define mmPA_SC_PERFCOUNTER2_HI                                                 0xd145
++#define mmPA_SC_PERFCOUNTER3_LO                                                 0xd146
++#define mmPA_SC_PERFCOUNTER3_HI                                                 0xd147
++#define mmPA_SC_PERFCOUNTER4_LO                                                 0xd148
++#define mmPA_SC_PERFCOUNTER4_HI                                                 0xd149
++#define mmPA_SC_PERFCOUNTER5_LO                                                 0xd14a
++#define mmPA_SC_PERFCOUNTER5_HI                                                 0xd14b
++#define mmPA_SC_PERFCOUNTER6_LO                                                 0xd14c
++#define mmPA_SC_PERFCOUNTER6_HI                                                 0xd14d
++#define mmPA_SC_PERFCOUNTER7_LO                                                 0xd14e
++#define mmPA_SC_PERFCOUNTER7_HI                                                 0xd14f
++#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN                                           0xc2a0
++#define mmPA_SC_P3D_TRAP_SCREEN_H                                               0xc2a1
++#define mmPA_SC_P3D_TRAP_SCREEN_V                                               0xc2a2
++#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                      0xc2a3
++#define mmPA_SC_P3D_TRAP_SCREEN_COUNT                                           0xc2a4
++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                                          0xc2a8
++#define mmPA_SC_HP3D_TRAP_SCREEN_H                                              0xc2a9
++#define mmPA_SC_HP3D_TRAP_SCREEN_V                                              0xc2aa
++#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                     0xc2ab
++#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT                                          0xc2ac
++#define mmPA_SC_TRAP_SCREEN_HV_EN                                               0xc2b0
++#define mmPA_SC_TRAP_SCREEN_H                                                   0xc2b1
++#define mmPA_SC_TRAP_SCREEN_V                                                   0xc2b2
++#define mmPA_SC_TRAP_SCREEN_OCCURRENCE                                          0xc2b3
++#define mmPA_SC_TRAP_SCREEN_COUNT                                               0xc2b4
++#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                         0x22c0
++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                        0x22c1
++#define mmPA_SC_TRAP_SCREEN_HV_LOCK                                             0x22c2
++#define mmPA_CL_CNTL_STATUS                                                     0x2284
++#define mmPA_SU_CNTL_STATUS                                                     0x2294
++#define mmPA_SC_FIFO_DEPTH_CNTL                                                 0x2295
++#define mmCGTT_PA_CLK_CTRL                                                      0xf088
++#define mmCGTT_SC_CLK_CTRL                                                      0xf089
++#define mmPA_SU_DEBUG_CNTL                                                      0x2280
++#define mmPA_SU_DEBUG_DATA                                                      0x2281
++#define mmPA_SC_DEBUG_CNTL                                                      0x22f6
++#define mmPA_SC_DEBUG_DATA                                                      0x22f7
++#define ixCLIPPER_DEBUG_REG00                                                   0x0
++#define ixCLIPPER_DEBUG_REG01                                                   0x1
++#define ixCLIPPER_DEBUG_REG02                                                   0x2
++#define ixCLIPPER_DEBUG_REG03                                                   0x3
++#define ixCLIPPER_DEBUG_REG04                                                   0x4
++#define ixCLIPPER_DEBUG_REG05                                                   0x5
++#define ixCLIPPER_DEBUG_REG06                                                   0x6
++#define ixCLIPPER_DEBUG_REG07                                                   0x7
++#define ixCLIPPER_DEBUG_REG08                                                   0x8
++#define ixCLIPPER_DEBUG_REG09                                                   0x9
++#define ixCLIPPER_DEBUG_REG10                                                   0xa
++#define ixCLIPPER_DEBUG_REG11                                                   0xb
++#define ixCLIPPER_DEBUG_REG12                                                   0xc
++#define ixCLIPPER_DEBUG_REG13                                                   0xd
++#define ixCLIPPER_DEBUG_REG14                                                   0xe
++#define ixCLIPPER_DEBUG_REG15                                                   0xf
++#define ixCLIPPER_DEBUG_REG16                                                   0x10
++#define ixCLIPPER_DEBUG_REG17                                                   0x11
++#define ixCLIPPER_DEBUG_REG18                                                   0x12
++#define ixCLIPPER_DEBUG_REG19                                                   0x13
++#define ixSXIFCCG_DEBUG_REG0                                                    0x14
++#define ixSXIFCCG_DEBUG_REG1                                                    0x15
++#define ixSXIFCCG_DEBUG_REG2                                                    0x16
++#define ixSXIFCCG_DEBUG_REG3                                                    0x17
++#define ixSETUP_DEBUG_REG0                                                      0x18
++#define ixSETUP_DEBUG_REG1                                                      0x19
++#define ixSETUP_DEBUG_REG2                                                      0x1a
++#define ixSETUP_DEBUG_REG3                                                      0x1b
++#define ixSETUP_DEBUG_REG4                                                      0x1c
++#define ixSETUP_DEBUG_REG5                                                      0x1d
++#define ixPA_SC_DEBUG_REG0                                                      0x0
++#define ixPA_SC_DEBUG_REG1                                                      0x1
++#define mmCOMPUTE_DISPATCH_INITIATOR                                            0x2e00
++#define mmCOMPUTE_DIM_X                                                         0x2e01
++#define mmCOMPUTE_DIM_Y                                                         0x2e02
++#define mmCOMPUTE_DIM_Z                                                         0x2e03
++#define mmCOMPUTE_START_X                                                       0x2e04
++#define mmCOMPUTE_START_Y                                                       0x2e05
++#define mmCOMPUTE_START_Z                                                       0x2e06
++#define mmCOMPUTE_NUM_THREAD_X                                                  0x2e07
++#define mmCOMPUTE_NUM_THREAD_Y                                                  0x2e08
++#define mmCOMPUTE_NUM_THREAD_Z                                                  0x2e09
++#define mmCOMPUTE_PIPELINESTAT_ENABLE                                           0x2e0a
++#define mmCOMPUTE_PERFCOUNT_ENABLE                                              0x2e0b
++#define mmCOMPUTE_PGM_LO                                                        0x2e0c
++#define mmCOMPUTE_PGM_HI                                                        0x2e0d
++#define mmCOMPUTE_TBA_LO                                                        0x2e0e
++#define mmCOMPUTE_TBA_HI                                                        0x2e0f
++#define mmCOMPUTE_TMA_LO                                                        0x2e10
++#define mmCOMPUTE_TMA_HI                                                        0x2e11
++#define mmCOMPUTE_PGM_RSRC1                                                     0x2e12
++#define mmCOMPUTE_PGM_RSRC2                                                     0x2e13
++#define mmCOMPUTE_VMID                                                          0x2e14
++#define mmCOMPUTE_RESOURCE_LIMITS                                               0x2e15
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                                        0x2e16
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                                        0x2e17
++#define mmCOMPUTE_TMPRING_SIZE                                                  0x2e18
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2                                        0x2e19
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3                                        0x2e1a
++#define mmCOMPUTE_RESTART_X                                                     0x2e1b
++#define mmCOMPUTE_RESTART_Y                                                     0x2e1c
++#define mmCOMPUTE_RESTART_Z                                                     0x2e1d
++#define mmCOMPUTE_THREAD_TRACE_ENABLE                                           0x2e1e
++#define mmCOMPUTE_MISC_RESERVED                                                 0x2e1f
++#define mmCOMPUTE_USER_DATA_0                                                   0x2e40
++#define mmCOMPUTE_USER_DATA_1                                                   0x2e41
++#define mmCOMPUTE_USER_DATA_2                                                   0x2e42
++#define mmCOMPUTE_USER_DATA_3                                                   0x2e43
++#define mmCOMPUTE_USER_DATA_4                                                   0x2e44
++#define mmCOMPUTE_USER_DATA_5                                                   0x2e45
++#define mmCOMPUTE_USER_DATA_6                                                   0x2e46
++#define mmCOMPUTE_USER_DATA_7                                                   0x2e47
++#define mmCOMPUTE_USER_DATA_8                                                   0x2e48
++#define mmCOMPUTE_USER_DATA_9                                                   0x2e49
++#define mmCOMPUTE_USER_DATA_10                                                  0x2e4a
++#define mmCOMPUTE_USER_DATA_11                                                  0x2e4b
++#define mmCOMPUTE_USER_DATA_12                                                  0x2e4c
++#define mmCOMPUTE_USER_DATA_13                                                  0x2e4d
++#define mmCOMPUTE_USER_DATA_14                                                  0x2e4e
++#define mmCOMPUTE_USER_DATA_15                                                  0x2e4f
++#define mmCSPRIV_CONNECT                                                        0x0
++#define mmCSPRIV_THREAD_TRACE_TG0                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG1                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG2                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG3                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_EVENT                                             0x1f
++#define mmRLC_CNTL                                                              0x30c0
++#define mmRLC_DEBUG_SELECT                                                      0x30c1
++#define mmRLC_DEBUG                                                             0x30c2
++#define mmRLC_MC_CNTL                                                           0x30c3
++#define mmRLC_STAT                                                              0x30c4
++#define mmRLC_SAFE_MODE                                                         0x313a
++#define mmRLC_SOFT_RESET_GPU                                                    0x30c5
++#define mmRLC_MEM_SLP_CNTL                                                      0x30c6
++#define mmRLC_PERFMON_CNTL                                                      0xdcc0
++#define mmRLC_PERFCOUNTER0_SELECT                                               0xdcc1
++#define mmRLC_PERFCOUNTER1_SELECT                                               0xdcc2
++#define mmRLC_PERFCOUNTER0_LO                                                   0xd480
++#define mmRLC_PERFCOUNTER1_LO                                                   0xd482
++#define mmRLC_PERFCOUNTER0_HI                                                   0xd481
++#define mmRLC_PERFCOUNTER1_HI                                                   0xd483
++#define mmCGTT_RLC_CLK_CTRL                                                     0xf0b8
++#define mmRLC_LB_CNTL                                                           0x30d9
++#define mmRLC_LB_CNTR_MAX                                                       0x30d2
++#define mmRLC_LB_CNTR_INIT                                                      0x30db
++#define mmRLC_LOAD_BALANCE_CNTR                                                 0x30dc
++#define mmRLC_SAVE_AND_RESTORE_BASE                                             0x30dd
++#define mmRLC_JUMP_TABLE_RESTORE                                                0x30de
++#define mmRLC_DRIVER_CPDMA_STATUS                                               0x30de
++#define mmRLC_PG_DELAY_2                                                        0x30df
++#define mmRLC_GPM_DEBUG_SELECT                                                  0x30e0
++#define mmRLC_GPM_DEBUG                                                         0x30e1
++#define mmRLC_GPM_UCODE_ADDR                                                    0x30e2
++#define mmRLC_GPM_UCODE_DATA                                                    0x30e3
++#define mmRLC_GPU_CLOCK_COUNT_LSB                                               0x30e4
++#define mmRLC_GPU_CLOCK_COUNT_MSB                                               0x30e5
++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT                                           0x30e6
++#define mmRLC_UCODE_CNTL                                                        0x30e7
++#define mmRLC_GPM_STAT                                                          0x3100
++#define mmRLC_GPU_CLOCK_32_RES_SEL                                              0x3101
++#define mmRLC_GPU_CLOCK_32                                                      0x3102
++#define mmRLC_PG_CNTL                                                           0x3103
++#define mmRLC_GPM_THREAD_PRIORITY                                               0x3104
++#define mmRLC_GPM_THREAD_ENABLE                                                 0x3105
++#define mmRLC_GPM_VMID_THREAD0                                                  0x3106
++#define mmRLC_GPM_VMID_THREAD1                                                  0x3107
++#define mmRLC_CGTT_MGCG_OVERRIDE                                                0x3108
++#define mmRLC_CGCG_CGLS_CTRL                                                    0x3109
++#define mmRLC_CGCG_RAMP_CTRL                                                    0x310a
++#define mmRLC_DYN_PG_STATUS                                                     0x310b
++#define mmRLC_DYN_PG_REQUEST                                                    0x310c
++#define mmRLC_PG_DELAY                                                          0x310d
++#define mmRLC_CU_STATUS                                                         0x310e
++#define mmRLC_LB_INIT_CU_MASK                                                   0x310f
++#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK                                          0x3110
++#define mmRLC_LB_PARAMS                                                         0x3111
++#define mmRLC_THREAD1_DELAY                                                     0x3112
++#define mmRLC_PG_ALWAYS_ON_CU_MASK                                              0x3113
++#define mmRLC_MAX_PG_CU                                                         0x3114
++#define mmRLC_AUTO_PG_CTRL                                                      0x3115
++#define mmRLC_SMU_GRBM_REG_SAVE_CTRL                                            0x3116
++#define mmRLC_SMU_PG_CTRL                                                       0x3117
++#define mmRLC_SMU_PG_WAKE_UP_CTRL                                               0x3118
++#define mmRLC_SERDES_RD_MASTER_INDEX                                            0x3119
++#define mmRLC_SERDES_RD_DATA_0                                                  0x311a
++#define mmRLC_SERDES_RD_DATA_1                                                  0x311b
++#define mmRLC_SERDES_RD_DATA_2                                                  0x311c
++#define mmRLC_SERDES_WR_CU_MASTER_MASK                                          0x311d
++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK                                       0x311e
++#define mmRLC_SERDES_WR_CTRL                                                    0x311f
++#define mmRLC_SERDES_WR_DATA                                                    0x3120
++#define mmRLC_SERDES_CU_MASTER_BUSY                                             0x3121
++#define mmRLC_SERDES_NONCU_MASTER_BUSY                                          0x3122
++#define mmRLC_GPM_GENERAL_0                                                     0x3123
++#define mmRLC_GPM_GENERAL_1                                                     0x3124
++#define mmRLC_GPM_GENERAL_2                                                     0x3125
++#define mmRLC_GPM_GENERAL_3                                                     0x3126
++#define mmRLC_GPM_GENERAL_4                                                     0x3127
++#define mmRLC_GPM_GENERAL_5                                                     0x3128
++#define mmRLC_GPM_GENERAL_6                                                     0x3129
++#define mmRLC_GPM_GENERAL_7                                                     0x312a
++#define mmRLC_GPM_CU_PD_TIMEOUT                                                 0x312b
++#define mmRLC_GPM_SCRATCH_ADDR                                                  0x312c
++#define mmRLC_GPM_SCRATCH_DATA                                                  0x312d
++#define mmRLC_STATIC_PG_STATUS                                                  0x312e
++#define mmRLC_GPM_PERF_COUNT_0                                                  0x312f
++#define mmRLC_GPM_PERF_COUNT_1                                                  0x3130
++#define mmRLC_GPR_REG1                                                          0x3139
++#define mmRLC_GPR_REG2                                                          0x313a
++#define mmRLC_SPM_VMID                                                          0x3131
++#define mmRLC_SPM_INT_CNTL                                                      0x3132
++#define mmRLC_SPM_INT_STATUS                                                    0x3133
++#define mmRLC_SPM_DEBUG_SELECT                                                  0x3134
++#define mmRLC_SPM_DEBUG                                                         0x3135
++#define mmRLC_GPM_LOG_ADDR                                                      0x3136
++#define mmRLC_GPM_LOG_SIZE                                                      0x3137
++#define mmRLC_GPM_LOG_CONT                                                      0x3138
++#define mmRLC_SPM_PERFMON_CNTL                                                  0xdc80
++#define mmRLC_SPM_PERFMON_RING_BASE_LO                                          0xdc81
++#define mmRLC_SPM_PERFMON_RING_BASE_HI                                          0xdc82
++#define mmRLC_SPM_PERFMON_RING_SIZE                                             0xdc83
++#define mmRLC_SPM_PERFMON_SEGMENT_SIZE                                          0xdc84
++#define mmRLC_SPM_SE_MUXSEL_ADDR                                                0xdc85
++#define mmRLC_SPM_SE_MUXSEL_DATA                                                0xdc86
++#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY                                      0xdc87
++#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY                                      0xdc88
++#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY                                      0xdc89
++#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY                                       0xdc8a
++#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY                                       0xdc8b
++#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY                                       0xdc8c
++#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY                                      0xdc8d
++#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY                                       0xdc8e
++#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY                                       0xdc90
++#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY                                      0xdc91
++#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY                                      0xdc92
++#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY                                      0xdc93
++#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY                                       0xdc94
++#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY                                       0xdc95
++#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY                                      0xdc96
++#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY                                      0xdc97
++#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY                                      0xdc98
++#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY                                      0xdc99
++#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY                                       0xdc9a
++#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR                                            0xdc9b
++#define mmRLC_SPM_GLOBAL_MUXSEL_DATA                                            0xdc9c
++#define mmRLC_SPM_RING_RDPTR                                                    0xdc9d
++#define mmRLC_SPM_SEGMENT_THRESHOLD                                             0xdc9e
++#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY                                     0xdc9f
++#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY                                     0xdca0
++#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY                                     0xdca1
++#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY                                     0xdca2
++#define mmSPI_PS_INPUT_CNTL_0                                                   0xa191
++#define mmSPI_PS_INPUT_CNTL_1                                                   0xa192
++#define mmSPI_PS_INPUT_CNTL_2                                                   0xa193
++#define mmSPI_PS_INPUT_CNTL_3                                                   0xa194
++#define mmSPI_PS_INPUT_CNTL_4                                                   0xa195
++#define mmSPI_PS_INPUT_CNTL_5                                                   0xa196
++#define mmSPI_PS_INPUT_CNTL_6                                                   0xa197
++#define mmSPI_PS_INPUT_CNTL_7                                                   0xa198
++#define mmSPI_PS_INPUT_CNTL_8                                                   0xa199
++#define mmSPI_PS_INPUT_CNTL_9                                                   0xa19a
++#define mmSPI_PS_INPUT_CNTL_10                                                  0xa19b
++#define mmSPI_PS_INPUT_CNTL_11                                                  0xa19c
++#define mmSPI_PS_INPUT_CNTL_12                                                  0xa19d
++#define mmSPI_PS_INPUT_CNTL_13                                                  0xa19e
++#define mmSPI_PS_INPUT_CNTL_14                                                  0xa19f
++#define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
++#define mmSPI_PS_INPUT_CNTL_16                                                  0xa1a1
++#define mmSPI_PS_INPUT_CNTL_17                                                  0xa1a2
++#define mmSPI_PS_INPUT_CNTL_18                                                  0xa1a3
++#define mmSPI_PS_INPUT_CNTL_19                                                  0xa1a4
++#define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
++#define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
++#define mmSPI_PS_INPUT_CNTL_22                                                  0xa1a7
++#define mmSPI_PS_INPUT_CNTL_23                                                  0xa1a8
++#define mmSPI_PS_INPUT_CNTL_24                                                  0xa1a9
++#define mmSPI_PS_INPUT_CNTL_25                                                  0xa1aa
++#define mmSPI_PS_INPUT_CNTL_26                                                  0xa1ab
++#define mmSPI_PS_INPUT_CNTL_27                                                  0xa1ac
++#define mmSPI_PS_INPUT_CNTL_28                                                  0xa1ad
++#define mmSPI_PS_INPUT_CNTL_29                                                  0xa1ae
++#define mmSPI_PS_INPUT_CNTL_30                                                  0xa1af
++#define mmSPI_PS_INPUT_CNTL_31                                                  0xa1b0
++#define mmSPI_VS_OUT_CONFIG                                                     0xa1b1
++#define mmSPI_PS_INPUT_ENA                                                      0xa1b3
++#define mmSPI_PS_INPUT_ADDR                                                     0xa1b4
++#define mmSPI_INTERP_CONTROL_0                                                  0xa1b5
++#define mmSPI_PS_IN_CONTROL                                                     0xa1b6
++#define mmSPI_BARYC_CNTL                                                        0xa1b8
++#define mmSPI_TMPRING_SIZE                                                      0xa1ba
++#define mmSPI_SHADER_POS_FORMAT                                                 0xa1c3
++#define mmSPI_SHADER_Z_FORMAT                                                   0xa1c4
++#define mmSPI_SHADER_COL_FORMAT                                                 0xa1c5
++#define mmSPI_ARB_PRIORITY                                                      0x31c0
++#define mmSPI_ARB_CYCLES_0                                                      0x31c1
++#define mmSPI_ARB_CYCLES_1                                                      0x31c2
++#define mmSPI_CDBG_SYS_GFX                                                      0x31c3
++#define mmSPI_CDBG_SYS_HP3D                                                     0x31c4
++#define mmSPI_CDBG_SYS_CS0                                                      0x31c5
++#define mmSPI_CDBG_SYS_CS1                                                      0x31c6
++#define mmSPI_WCL_PIPE_PERCENT_GFX                                              0x31c7
++#define mmSPI_WCL_PIPE_PERCENT_HP3D                                             0x31c8
++#define mmSPI_WCL_PIPE_PERCENT_CS0                                              0x31c9
++#define mmSPI_WCL_PIPE_PERCENT_CS1                                              0x31ca
++#define mmSPI_WCL_PIPE_PERCENT_CS2                                              0x31cb
++#define mmSPI_WCL_PIPE_PERCENT_CS3                                              0x31cc
++#define mmSPI_WCL_PIPE_PERCENT_CS4                                              0x31cd
++#define mmSPI_WCL_PIPE_PERCENT_CS5                                              0x31ce
++#define mmSPI_WCL_PIPE_PERCENT_CS6                                              0x31cf
++#define mmSPI_WCL_PIPE_PERCENT_CS7                                              0x31d0
++#define mmSPI_GDBG_WAVE_CNTL                                                    0x31d1
++#define mmSPI_GDBG_TRAP_CONFIG                                                  0x31d2
++#define mmSPI_GDBG_TRAP_MASK                                                    0x31d3
++#define mmSPI_GDBG_TBA_LO                                                       0x31d4
++#define mmSPI_GDBG_TBA_HI                                                       0x31d5
++#define mmSPI_GDBG_TMA_LO                                                       0x31d6
++#define mmSPI_GDBG_TMA_HI                                                       0x31d7
++#define mmSPI_GDBG_TRAP_DATA0                                                   0x31d8
++#define mmSPI_GDBG_TRAP_DATA1                                                   0x31d9
++#define mmSPI_RESET_DEBUG                                                       0x31da
++#define mmSPI_COMPUTE_QUEUE_RESET                                               0x31db
++#define mmSPI_RESOURCE_RESERVE_CU_0                                             0x31dc
++#define mmSPI_RESOURCE_RESERVE_CU_1                                             0x31dd
++#define mmSPI_RESOURCE_RESERVE_CU_2                                             0x31de
++#define mmSPI_RESOURCE_RESERVE_CU_3                                             0x31df
++#define mmSPI_RESOURCE_RESERVE_CU_4                                             0x31e0
++#define mmSPI_RESOURCE_RESERVE_CU_5                                             0x31e1
++#define mmSPI_RESOURCE_RESERVE_CU_6                                             0x31e2
++#define mmSPI_RESOURCE_RESERVE_CU_7                                             0x31e3
++#define mmSPI_RESOURCE_RESERVE_CU_8                                             0x31e4
++#define mmSPI_RESOURCE_RESERVE_CU_9                                             0x31e5
++#define mmSPI_RESOURCE_RESERVE_CU_10                                            0x31f0
++#define mmSPI_RESOURCE_RESERVE_CU_11                                            0x31f1
++#define mmSPI_RESOURCE_RESERVE_EN_CU_0                                          0x31e6
++#define mmSPI_RESOURCE_RESERVE_EN_CU_1                                          0x31e7
++#define mmSPI_RESOURCE_RESERVE_EN_CU_2                                          0x31e8
++#define mmSPI_RESOURCE_RESERVE_EN_CU_3                                          0x31e9
++#define mmSPI_RESOURCE_RESERVE_EN_CU_4                                          0x31ea
++#define mmSPI_RESOURCE_RESERVE_EN_CU_5                                          0x31eb
++#define mmSPI_RESOURCE_RESERVE_EN_CU_6                                          0x31ec
++#define mmSPI_RESOURCE_RESERVE_EN_CU_7                                          0x31ed
++#define mmSPI_RESOURCE_RESERVE_EN_CU_8                                          0x31ee
++#define mmSPI_RESOURCE_RESERVE_EN_CU_9                                          0x31ef
++#define mmSPI_RESOURCE_RESERVE_EN_CU_10                                         0x31f2
++#define mmSPI_RESOURCE_RESERVE_EN_CU_11                                         0x31f3
++#define mmSPI_PS_MAX_WAVE_ID                                                    0x243a
++#define mmSPI_CONFIG_CNTL                                                       0x2440
++#define mmSPI_DEBUG_CNTL                                                        0x2441
++#define mmSPI_DEBUG_READ                                                        0x2442
++#define mmSPI_PERFCOUNTER0_SELECT                                               0xd980
++#define mmSPI_PERFCOUNTER1_SELECT                                               0xd981
++#define mmSPI_PERFCOUNTER2_SELECT                                               0xd982
++#define mmSPI_PERFCOUNTER3_SELECT                                               0xd983
++#define mmSPI_PERFCOUNTER0_SELECT1                                              0xd984
++#define mmSPI_PERFCOUNTER1_SELECT1                                              0xd985
++#define mmSPI_PERFCOUNTER2_SELECT1                                              0xd986
++#define mmSPI_PERFCOUNTER3_SELECT1                                              0xd987
++#define mmSPI_PERFCOUNTER4_SELECT                                               0xd988
++#define mmSPI_PERFCOUNTER5_SELECT                                               0xd989
++#define mmSPI_PERFCOUNTER_BINS                                                  0xd98a
++#define mmSPI_PERFCOUNTER0_HI                                                   0xd180
++#define mmSPI_PERFCOUNTER0_LO                                                   0xd181
++#define mmSPI_PERFCOUNTER1_HI                                                   0xd182
++#define mmSPI_PERFCOUNTER1_LO                                                   0xd183
++#define mmSPI_PERFCOUNTER2_HI                                                   0xd184
++#define mmSPI_PERFCOUNTER2_LO                                                   0xd185
++#define mmSPI_PERFCOUNTER3_HI                                                   0xd186
++#define mmSPI_PERFCOUNTER3_LO                                                   0xd187
++#define mmSPI_PERFCOUNTER4_HI                                                   0xd188
++#define mmSPI_PERFCOUNTER4_LO                                                   0xd189
++#define mmSPI_PERFCOUNTER5_HI                                                   0xd18a
++#define mmSPI_PERFCOUNTER5_LO                                                   0xd18b
++#define mmSPI_CONFIG_CNTL_1                                                     0x244f
++#define mmSPI_DEBUG_BUSY                                                        0x2450
++#define mmCGTS_SM_CTRL_REG                                                      0xf000
++#define mmCGTS_RD_CTRL_REG                                                      0xf001
++#define mmCGTS_RD_REG                                                           0xf002
++#define mmCGTS_TCC_DISABLE                                                      0xf003
++#define mmCGTS_USER_TCC_DISABLE                                                 0xf004
++#define mmCGTS_CU0_SP0_CTRL_REG                                                 0xf008
++#define mmCGTS_CU0_LDS_SQ_CTRL_REG                                              0xf009
++#define mmCGTS_CU0_TA_SQC_CTRL_REG                                              0xf00a
++#define mmCGTS_CU0_SP1_CTRL_REG                                                 0xf00b
++#define mmCGTS_CU0_TD_TCP_CTRL_REG                                              0xf00c
++#define mmCGTS_CU1_SP0_CTRL_REG                                                 0xf00d
++#define mmCGTS_CU1_LDS_SQ_CTRL_REG                                              0xf00e
++#define mmCGTS_CU1_TA_CTRL_REG                                                  0xf00f
++#define mmCGTS_CU1_SP1_CTRL_REG                                                 0xf010
++#define mmCGTS_CU1_TD_TCP_CTRL_REG                                              0xf011
++#define mmCGTS_CU2_SP0_CTRL_REG                                                 0xf012
++#define mmCGTS_CU2_LDS_SQ_CTRL_REG                                              0xf013
++#define mmCGTS_CU2_TA_CTRL_REG                                                  0xf014
++#define mmCGTS_CU2_SP1_CTRL_REG                                                 0xf015
++#define mmCGTS_CU2_TD_TCP_CTRL_REG                                              0xf016
++#define mmCGTS_CU3_SP0_CTRL_REG                                                 0xf017
++#define mmCGTS_CU3_LDS_SQ_CTRL_REG                                              0xf018
++#define mmCGTS_CU3_TA_CTRL_REG                                                  0xf019
++#define mmCGTS_CU3_SP1_CTRL_REG                                                 0xf01a
++#define mmCGTS_CU3_TD_TCP_CTRL_REG                                              0xf01b
++#define mmCGTS_CU4_SP0_CTRL_REG                                                 0xf01c
++#define mmCGTS_CU4_LDS_SQ_CTRL_REG                                              0xf01d
++#define mmCGTS_CU4_TA_SQC_CTRL_REG                                              0xf01e
++#define mmCGTS_CU4_SP1_CTRL_REG                                                 0xf01f
++#define mmCGTS_CU4_TD_TCP_CTRL_REG                                              0xf020
++#define mmCGTS_CU5_SP0_CTRL_REG                                                 0xf021
++#define mmCGTS_CU5_LDS_SQ_CTRL_REG                                              0xf022
++#define mmCGTS_CU5_TA_CTRL_REG                                                  0xf023
++#define mmCGTS_CU5_SP1_CTRL_REG                                                 0xf024
++#define mmCGTS_CU5_TD_TCP_CTRL_REG                                              0xf025
++#define mmCGTS_CU6_SP0_CTRL_REG                                                 0xf026
++#define mmCGTS_CU6_LDS_SQ_CTRL_REG                                              0xf027
++#define mmCGTS_CU6_TA_CTRL_REG                                                  0xf028
++#define mmCGTS_CU6_SP1_CTRL_REG                                                 0xf029
++#define mmCGTS_CU6_TD_TCP_CTRL_REG                                              0xf02a
++#define mmCGTS_CU7_SP0_CTRL_REG                                                 0xf02b
++#define mmCGTS_CU7_LDS_SQ_CTRL_REG                                              0xf02c
++#define mmCGTS_CU7_TA_CTRL_REG                                                  0xf02d
++#define mmCGTS_CU7_SP1_CTRL_REG                                                 0xf02e
++#define mmCGTS_CU7_TD_TCP_CTRL_REG                                              0xf02f
++#define mmCGTS_CU8_SP0_CTRL_REG                                                 0xf030
++#define mmCGTS_CU8_LDS_SQ_CTRL_REG                                              0xf031
++#define mmCGTS_CU8_TA_SQC_CTRL_REG                                              0xf032
++#define mmCGTS_CU8_SP1_CTRL_REG                                                 0xf033
++#define mmCGTS_CU8_TD_TCP_CTRL_REG                                              0xf034
++#define mmCGTS_CU9_SP0_CTRL_REG                                                 0xf035
++#define mmCGTS_CU9_LDS_SQ_CTRL_REG                                              0xf036
++#define mmCGTS_CU9_TA_CTRL_REG                                                  0xf037
++#define mmCGTS_CU9_SP1_CTRL_REG                                                 0xf038
++#define mmCGTS_CU9_TD_TCP_CTRL_REG                                              0xf039
++#define mmCGTS_CU10_SP0_CTRL_REG                                                0xf03a
++#define mmCGTS_CU10_LDS_SQ_CTRL_REG                                             0xf03b
++#define mmCGTS_CU10_TA_CTRL_REG                                                 0xf03c
++#define mmCGTS_CU10_SP1_CTRL_REG                                                0xf03d
++#define mmCGTS_CU10_TD_TCP_CTRL_REG                                             0xf03e
++#define mmCGTS_CU11_SP0_CTRL_REG                                                0xf03f
++#define mmCGTS_CU11_LDS_SQ_CTRL_REG                                             0xf040
++#define mmCGTS_CU11_TA_CTRL_REG                                                 0xf041
++#define mmCGTS_CU11_SP1_CTRL_REG                                                0xf042
++#define mmCGTS_CU11_TD_TCP_CTRL_REG                                             0xf043
++#define mmCGTS_CU12_SP0_CTRL_REG                                                0xf044
++#define mmCGTS_CU12_LDS_SQ_CTRL_REG                                             0xf045
++#define mmCGTS_CU12_TA_SQC_CTRL_REG                                             0xf046
++#define mmCGTS_CU12_SP1_CTRL_REG                                                0xf047
++#define mmCGTS_CU12_TD_TCP_CTRL_REG                                             0xf048
++#define mmCGTS_CU13_SP0_CTRL_REG                                                0xf049
++#define mmCGTS_CU13_LDS_SQ_CTRL_REG                                             0xf04a
++#define mmCGTS_CU13_TA_CTRL_REG                                                 0xf04b
++#define mmCGTS_CU13_SP1_CTRL_REG                                                0xf04c
++#define mmCGTS_CU13_TD_TCP_CTRL_REG                                             0xf04d
++#define mmCGTS_CU14_SP0_CTRL_REG                                                0xf04e
++#define mmCGTS_CU14_LDS_SQ_CTRL_REG                                             0xf04f
++#define mmCGTS_CU14_TA_CTRL_REG                                                 0xf050
++#define mmCGTS_CU14_SP1_CTRL_REG                                                0xf051
++#define mmCGTS_CU14_TD_TCP_CTRL_REG                                             0xf052
++#define mmCGTS_CU15_SP0_CTRL_REG                                                0xf053
++#define mmCGTS_CU15_LDS_SQ_CTRL_REG                                             0xf054
++#define mmCGTS_CU15_TA_CTRL_REG                                                 0xf055
++#define mmCGTS_CU15_SP1_CTRL_REG                                                0xf056
++#define mmCGTS_CU15_TD_TCP_CTRL_REG                                             0xf057
++#define mmCGTT_SPI_CLK_CTRL                                                     0xf080
++#define mmCGTT_PC_CLK_CTRL                                                      0xf081
++#define mmCGTT_BCI_CLK_CTRL                                                     0xf082
++#define mmSPI_WF_LIFETIME_CNTL                                                  0x24aa
++#define mmSPI_WF_LIFETIME_LIMIT_0                                               0x24ab
++#define mmSPI_WF_LIFETIME_LIMIT_1                                               0x24ac
++#define mmSPI_WF_LIFETIME_LIMIT_2                                               0x24ad
++#define mmSPI_WF_LIFETIME_LIMIT_3                                               0x24ae
++#define mmSPI_WF_LIFETIME_LIMIT_4                                               0x24af
++#define mmSPI_WF_LIFETIME_LIMIT_5                                               0x24b0
++#define mmSPI_WF_LIFETIME_LIMIT_6                                               0x24b1
++#define mmSPI_WF_LIFETIME_LIMIT_7                                               0x24b2
++#define mmSPI_WF_LIFETIME_LIMIT_8                                               0x24b3
++#define mmSPI_WF_LIFETIME_LIMIT_9                                               0x24b4
++#define mmSPI_WF_LIFETIME_STATUS_0                                              0x24b5
++#define mmSPI_WF_LIFETIME_STATUS_1                                              0x24b6
++#define mmSPI_WF_LIFETIME_STATUS_2                                              0x24b7
++#define mmSPI_WF_LIFETIME_STATUS_3                                              0x24b8
++#define mmSPI_WF_LIFETIME_STATUS_4                                              0x24b9
++#define mmSPI_WF_LIFETIME_STATUS_5                                              0x24ba
++#define mmSPI_WF_LIFETIME_STATUS_6                                              0x24bb
++#define mmSPI_WF_LIFETIME_STATUS_7                                              0x24bc
++#define mmSPI_WF_LIFETIME_STATUS_8                                              0x24bd
++#define mmSPI_WF_LIFETIME_STATUS_9                                              0x24be
++#define mmSPI_WF_LIFETIME_STATUS_10                                             0x24bf
++#define mmSPI_WF_LIFETIME_STATUS_11                                             0x24c0
++#define mmSPI_WF_LIFETIME_STATUS_12                                             0x24c1
++#define mmSPI_WF_LIFETIME_STATUS_13                                             0x24c2
++#define mmSPI_WF_LIFETIME_STATUS_14                                             0x24c3
++#define mmSPI_WF_LIFETIME_STATUS_15                                             0x24c4
++#define mmSPI_WF_LIFETIME_STATUS_16                                             0x24c5
++#define mmSPI_WF_LIFETIME_STATUS_17                                             0x24c6
++#define mmSPI_WF_LIFETIME_STATUS_18                                             0x24c7
++#define mmSPI_WF_LIFETIME_STATUS_19                                             0x24c8
++#define mmSPI_WF_LIFETIME_STATUS_20                                             0x24c9
++#define mmSPI_WF_LIFETIME_DEBUG                                                 0x24ca
++#define mmSPI_SLAVE_DEBUG_BUSY                                                  0x24d3
++#define mmSPI_LB_CTR_CTRL                                                       0x24d4
++#define mmSPI_LB_CU_MASK                                                        0x24d5
++#define mmSPI_LB_DATA_REG                                                       0x24d6
++#define mmSPI_PG_ENABLE_STATIC_CU_MASK                                          0x24d7
++#define mmSPI_GDS_CREDITS                                                       0x24d8
++#define mmSPI_SX_EXPORT_BUFFER_SIZES                                            0x24d9
++#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                                        0x24da
++#define mmSPI_CSQ_WF_ACTIVE_STATUS                                              0x24db
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_0                                             0x24dc
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_1                                             0x24dd
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_2                                             0x24de
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_3                                             0x24df
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_4                                             0x24e0
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_5                                             0x24e1
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_6                                             0x24e2
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_7                                             0x24e3
++#define mmBCI_DEBUG_READ                                                        0x24eb
++#define mmSPI_P0_TRAP_SCREEN_PSBA_LO                                            0x24ec
++#define mmSPI_P0_TRAP_SCREEN_PSBA_HI                                            0x24ed
++#define mmSPI_P0_TRAP_SCREEN_PSMA_LO                                            0x24ee
++#define mmSPI_P0_TRAP_SCREEN_PSMA_HI                                            0x24ef
++#define mmSPI_P0_TRAP_SCREEN_GPR_MIN                                            0x24f0
++#define mmSPI_P1_TRAP_SCREEN_PSBA_LO                                            0x24f1
++#define mmSPI_P1_TRAP_SCREEN_PSBA_HI                                            0x24f2
++#define mmSPI_P1_TRAP_SCREEN_PSMA_LO                                            0x24f3
++#define mmSPI_P1_TRAP_SCREEN_PSMA_HI                                            0x24f4
++#define mmSPI_P1_TRAP_SCREEN_GPR_MIN                                            0x24f5
++#define mmSPI_SHADER_TBA_LO_PS                                                  0x2c00
++#define mmSPI_SHADER_TBA_HI_PS                                                  0x2c01
++#define mmSPI_SHADER_TMA_LO_PS                                                  0x2c02
++#define mmSPI_SHADER_TMA_HI_PS                                                  0x2c03
++#define mmSPI_SHADER_PGM_LO_PS                                                  0x2c08
++#define mmSPI_SHADER_PGM_HI_PS                                                  0x2c09
++#define mmSPI_SHADER_PGM_RSRC1_PS                                               0x2c0a
++#define mmSPI_SHADER_PGM_RSRC2_PS                                               0x2c0b
++#define mmSPI_SHADER_PGM_RSRC3_PS                                               0x2c07
++#define mmSPI_SHADER_USER_DATA_PS_0                                             0x2c0c
++#define mmSPI_SHADER_USER_DATA_PS_1                                             0x2c0d
++#define mmSPI_SHADER_USER_DATA_PS_2                                             0x2c0e
++#define mmSPI_SHADER_USER_DATA_PS_3                                             0x2c0f
++#define mmSPI_SHADER_USER_DATA_PS_4                                             0x2c10
++#define mmSPI_SHADER_USER_DATA_PS_5                                             0x2c11
++#define mmSPI_SHADER_USER_DATA_PS_6                                             0x2c12
++#define mmSPI_SHADER_USER_DATA_PS_7                                             0x2c13
++#define mmSPI_SHADER_USER_DATA_PS_8                                             0x2c14
++#define mmSPI_SHADER_USER_DATA_PS_9                                             0x2c15
++#define mmSPI_SHADER_USER_DATA_PS_10                                            0x2c16
++#define mmSPI_SHADER_USER_DATA_PS_11                                            0x2c17
++#define mmSPI_SHADER_USER_DATA_PS_12                                            0x2c18
++#define mmSPI_SHADER_USER_DATA_PS_13                                            0x2c19
++#define mmSPI_SHADER_USER_DATA_PS_14                                            0x2c1a
++#define mmSPI_SHADER_USER_DATA_PS_15                                            0x2c1b
++#define mmSPI_SHADER_TBA_LO_VS                                                  0x2c40
++#define mmSPI_SHADER_TBA_HI_VS                                                  0x2c41
++#define mmSPI_SHADER_TMA_LO_VS                                                  0x2c42
++#define mmSPI_SHADER_TMA_HI_VS                                                  0x2c43
++#define mmSPI_SHADER_PGM_LO_VS                                                  0x2c48
++#define mmSPI_SHADER_PGM_HI_VS                                                  0x2c49
++#define mmSPI_SHADER_PGM_RSRC1_VS                                               0x2c4a
++#define mmSPI_SHADER_PGM_RSRC2_VS                                               0x2c4b
++#define mmSPI_SHADER_PGM_RSRC3_VS                                               0x2c46
++#define mmSPI_SHADER_LATE_ALLOC_VS                                              0x2c47
++#define mmSPI_SHADER_USER_DATA_VS_0                                             0x2c4c
++#define mmSPI_SHADER_USER_DATA_VS_1                                             0x2c4d
++#define mmSPI_SHADER_USER_DATA_VS_2                                             0x2c4e
++#define mmSPI_SHADER_USER_DATA_VS_3                                             0x2c4f
++#define mmSPI_SHADER_USER_DATA_VS_4                                             0x2c50
++#define mmSPI_SHADER_USER_DATA_VS_5                                             0x2c51
++#define mmSPI_SHADER_USER_DATA_VS_6                                             0x2c52
++#define mmSPI_SHADER_USER_DATA_VS_7                                             0x2c53
++#define mmSPI_SHADER_USER_DATA_VS_8                                             0x2c54
++#define mmSPI_SHADER_USER_DATA_VS_9                                             0x2c55
++#define mmSPI_SHADER_USER_DATA_VS_10                                            0x2c56
++#define mmSPI_SHADER_USER_DATA_VS_11                                            0x2c57
++#define mmSPI_SHADER_USER_DATA_VS_12                                            0x2c58
++#define mmSPI_SHADER_USER_DATA_VS_13                                            0x2c59
++#define mmSPI_SHADER_USER_DATA_VS_14                                            0x2c5a
++#define mmSPI_SHADER_USER_DATA_VS_15                                            0x2c5b
++#define mmSPI_SHADER_PGM_RSRC2_ES_VS                                            0x2c7c
++#define mmSPI_SHADER_PGM_RSRC2_LS_VS                                            0x2c7d
++#define mmSPI_SHADER_TBA_LO_GS                                                  0x2c80
++#define mmSPI_SHADER_TBA_HI_GS                                                  0x2c81
++#define mmSPI_SHADER_TMA_LO_GS                                                  0x2c82
++#define mmSPI_SHADER_TMA_HI_GS                                                  0x2c83
++#define mmSPI_SHADER_PGM_LO_GS                                                  0x2c88
++#define mmSPI_SHADER_PGM_HI_GS                                                  0x2c89
++#define mmSPI_SHADER_PGM_RSRC1_GS                                               0x2c8a
++#define mmSPI_SHADER_PGM_RSRC2_GS                                               0x2c8b
++#define mmSPI_SHADER_PGM_RSRC3_GS                                               0x2c87
++#define mmSPI_SHADER_USER_DATA_GS_0                                             0x2c8c
++#define mmSPI_SHADER_USER_DATA_GS_1                                             0x2c8d
++#define mmSPI_SHADER_USER_DATA_GS_2                                             0x2c8e
++#define mmSPI_SHADER_USER_DATA_GS_3                                             0x2c8f
++#define mmSPI_SHADER_USER_DATA_GS_4                                             0x2c90
++#define mmSPI_SHADER_USER_DATA_GS_5                                             0x2c91
++#define mmSPI_SHADER_USER_DATA_GS_6                                             0x2c92
++#define mmSPI_SHADER_USER_DATA_GS_7                                             0x2c93
++#define mmSPI_SHADER_USER_DATA_GS_8                                             0x2c94
++#define mmSPI_SHADER_USER_DATA_GS_9                                             0x2c95
++#define mmSPI_SHADER_USER_DATA_GS_10                                            0x2c96
++#define mmSPI_SHADER_USER_DATA_GS_11                                            0x2c97
++#define mmSPI_SHADER_USER_DATA_GS_12                                            0x2c98
++#define mmSPI_SHADER_USER_DATA_GS_13                                            0x2c99
++#define mmSPI_SHADER_USER_DATA_GS_14                                            0x2c9a
++#define mmSPI_SHADER_USER_DATA_GS_15                                            0x2c9b
++#define mmSPI_SHADER_PGM_RSRC2_ES_GS                                            0x2cbc
++#define mmSPI_SHADER_TBA_LO_ES                                                  0x2cc0
++#define mmSPI_SHADER_TBA_HI_ES                                                  0x2cc1
++#define mmSPI_SHADER_TMA_LO_ES                                                  0x2cc2
++#define mmSPI_SHADER_TMA_HI_ES                                                  0x2cc3
++#define mmSPI_SHADER_PGM_LO_ES                                                  0x2cc8
++#define mmSPI_SHADER_PGM_HI_ES                                                  0x2cc9
++#define mmSPI_SHADER_PGM_RSRC1_ES                                               0x2cca
++#define mmSPI_SHADER_PGM_RSRC2_ES                                               0x2ccb
++#define mmSPI_SHADER_PGM_RSRC3_ES                                               0x2cc7
++#define mmSPI_SHADER_USER_DATA_ES_0                                             0x2ccc
++#define mmSPI_SHADER_USER_DATA_ES_1                                             0x2ccd
++#define mmSPI_SHADER_USER_DATA_ES_2                                             0x2cce
++#define mmSPI_SHADER_USER_DATA_ES_3                                             0x2ccf
++#define mmSPI_SHADER_USER_DATA_ES_4                                             0x2cd0
++#define mmSPI_SHADER_USER_DATA_ES_5                                             0x2cd1
++#define mmSPI_SHADER_USER_DATA_ES_6                                             0x2cd2
++#define mmSPI_SHADER_USER_DATA_ES_7                                             0x2cd3
++#define mmSPI_SHADER_USER_DATA_ES_8                                             0x2cd4
++#define mmSPI_SHADER_USER_DATA_ES_9                                             0x2cd5
++#define mmSPI_SHADER_USER_DATA_ES_10                                            0x2cd6
++#define mmSPI_SHADER_USER_DATA_ES_11                                            0x2cd7
++#define mmSPI_SHADER_USER_DATA_ES_12                                            0x2cd8
++#define mmSPI_SHADER_USER_DATA_ES_13                                            0x2cd9
++#define mmSPI_SHADER_USER_DATA_ES_14                                            0x2cda
++#define mmSPI_SHADER_USER_DATA_ES_15                                            0x2cdb
++#define mmSPI_SHADER_PGM_RSRC2_LS_ES                                            0x2cfd
++#define mmSPI_SHADER_TBA_LO_HS                                                  0x2d00
++#define mmSPI_SHADER_TBA_HI_HS                                                  0x2d01
++#define mmSPI_SHADER_TMA_LO_HS                                                  0x2d02
++#define mmSPI_SHADER_TMA_HI_HS                                                  0x2d03
++#define mmSPI_SHADER_PGM_LO_HS                                                  0x2d08
++#define mmSPI_SHADER_PGM_HI_HS                                                  0x2d09
++#define mmSPI_SHADER_PGM_RSRC1_HS                                               0x2d0a
++#define mmSPI_SHADER_PGM_RSRC2_HS                                               0x2d0b
++#define mmSPI_SHADER_PGM_RSRC3_HS                                               0x2d07
++#define mmSPI_SHADER_USER_DATA_HS_0                                             0x2d0c
++#define mmSPI_SHADER_USER_DATA_HS_1                                             0x2d0d
++#define mmSPI_SHADER_USER_DATA_HS_2                                             0x2d0e
++#define mmSPI_SHADER_USER_DATA_HS_3                                             0x2d0f
++#define mmSPI_SHADER_USER_DATA_HS_4                                             0x2d10
++#define mmSPI_SHADER_USER_DATA_HS_5                                             0x2d11
++#define mmSPI_SHADER_USER_DATA_HS_6                                             0x2d12
++#define mmSPI_SHADER_USER_DATA_HS_7                                             0x2d13
++#define mmSPI_SHADER_USER_DATA_HS_8                                             0x2d14
++#define mmSPI_SHADER_USER_DATA_HS_9                                             0x2d15
++#define mmSPI_SHADER_USER_DATA_HS_10                                            0x2d16
++#define mmSPI_SHADER_USER_DATA_HS_11                                            0x2d17
++#define mmSPI_SHADER_USER_DATA_HS_12                                            0x2d18
++#define mmSPI_SHADER_USER_DATA_HS_13                                            0x2d19
++#define mmSPI_SHADER_USER_DATA_HS_14                                            0x2d1a
++#define mmSPI_SHADER_USER_DATA_HS_15                                            0x2d1b
++#define mmSPI_SHADER_PGM_RSRC2_LS_HS                                            0x2d3d
++#define mmSPI_SHADER_TBA_LO_LS                                                  0x2d40
++#define mmSPI_SHADER_TBA_HI_LS                                                  0x2d41
++#define mmSPI_SHADER_TMA_LO_LS                                                  0x2d42
++#define mmSPI_SHADER_TMA_HI_LS                                                  0x2d43
++#define mmSPI_SHADER_PGM_LO_LS                                                  0x2d48
++#define mmSPI_SHADER_PGM_HI_LS                                                  0x2d49
++#define mmSPI_SHADER_PGM_RSRC1_LS                                               0x2d4a
++#define mmSPI_SHADER_PGM_RSRC2_LS                                               0x2d4b
++#define mmSPI_SHADER_PGM_RSRC3_LS                                               0x2d47
++#define mmSPI_SHADER_USER_DATA_LS_0                                             0x2d4c
++#define mmSPI_SHADER_USER_DATA_LS_1                                             0x2d4d
++#define mmSPI_SHADER_USER_DATA_LS_2                                             0x2d4e
++#define mmSPI_SHADER_USER_DATA_LS_3                                             0x2d4f
++#define mmSPI_SHADER_USER_DATA_LS_4                                             0x2d50
++#define mmSPI_SHADER_USER_DATA_LS_5                                             0x2d51
++#define mmSPI_SHADER_USER_DATA_LS_6                                             0x2d52
++#define mmSPI_SHADER_USER_DATA_LS_7                                             0x2d53
++#define mmSPI_SHADER_USER_DATA_LS_8                                             0x2d54
++#define mmSPI_SHADER_USER_DATA_LS_9                                             0x2d55
++#define mmSPI_SHADER_USER_DATA_LS_10                                            0x2d56
++#define mmSPI_SHADER_USER_DATA_LS_11                                            0x2d57
++#define mmSPI_SHADER_USER_DATA_LS_12                                            0x2d58
++#define mmSPI_SHADER_USER_DATA_LS_13                                            0x2d59
++#define mmSPI_SHADER_USER_DATA_LS_14                                            0x2d5a
++#define mmSPI_SHADER_USER_DATA_LS_15                                            0x2d5b
++#define mmSQ_CONFIG                                                             0x2300
++#define mmSQC_CONFIG                                                            0x2301
++#define mmSQC_CACHES                                                            0xc348
++#define mmSQ_RANDOM_WAVE_PRI                                                    0x2303
++#define mmSQ_REG_CREDITS                                                        0x2304
++#define mmSQ_FIFO_SIZES                                                         0x2305
++#define mmSQ_INTERRUPT_AUTO_MASK                                                0x2314
++#define mmSQ_INTERRUPT_MSG_CTRL                                                 0x2315
++#define mmSQ_PERFCOUNTER_CTRL                                                   0xd9e0
++#define mmSQ_PERFCOUNTER_MASK                                                   0xd9e1
++#define mmSQ_PERFCOUNTER_CTRL2                                                  0xd9e2
++#define mmCC_SQC_BANK_DISABLE                                                   0x2307
++#define mmUSER_SQC_BANK_DISABLE                                                 0x2308
++#define mmSQ_PERFCOUNTER0_LO                                                    0xd1c0
++#define mmSQ_PERFCOUNTER1_LO                                                    0xd1c2
++#define mmSQ_PERFCOUNTER2_LO                                                    0xd1c4
++#define mmSQ_PERFCOUNTER3_LO                                                    0xd1c6
++#define mmSQ_PERFCOUNTER4_LO                                                    0xd1c8
++#define mmSQ_PERFCOUNTER5_LO                                                    0xd1ca
++#define mmSQ_PERFCOUNTER6_LO                                                    0xd1cc
++#define mmSQ_PERFCOUNTER7_LO                                                    0xd1ce
++#define mmSQ_PERFCOUNTER8_LO                                                    0xd1d0
++#define mmSQ_PERFCOUNTER9_LO                                                    0xd1d2
++#define mmSQ_PERFCOUNTER10_LO                                                   0xd1d4
++#define mmSQ_PERFCOUNTER11_LO                                                   0xd1d6
++#define mmSQ_PERFCOUNTER12_LO                                                   0xd1d8
++#define mmSQ_PERFCOUNTER13_LO                                                   0xd1da
++#define mmSQ_PERFCOUNTER14_LO                                                   0xd1dc
++#define mmSQ_PERFCOUNTER15_LO                                                   0xd1de
++#define mmSQ_PERFCOUNTER0_HI                                                    0xd1c1
++#define mmSQ_PERFCOUNTER1_HI                                                    0xd1c3
++#define mmSQ_PERFCOUNTER2_HI                                                    0xd1c5
++#define mmSQ_PERFCOUNTER3_HI                                                    0xd1c7
++#define mmSQ_PERFCOUNTER4_HI                                                    0xd1c9
++#define mmSQ_PERFCOUNTER5_HI                                                    0xd1cb
++#define mmSQ_PERFCOUNTER6_HI                                                    0xd1cd
++#define mmSQ_PERFCOUNTER7_HI                                                    0xd1cf
++#define mmSQ_PERFCOUNTER8_HI                                                    0xd1d1
++#define mmSQ_PERFCOUNTER9_HI                                                    0xd1d3
++#define mmSQ_PERFCOUNTER10_HI                                                   0xd1d5
++#define mmSQ_PERFCOUNTER11_HI                                                   0xd1d7
++#define mmSQ_PERFCOUNTER12_HI                                                   0xd1d9
++#define mmSQ_PERFCOUNTER13_HI                                                   0xd1db
++#define mmSQ_PERFCOUNTER14_HI                                                   0xd1dd
++#define mmSQ_PERFCOUNTER15_HI                                                   0xd1df
++#define mmSQ_PERFCOUNTER0_SELECT                                                0xd9c0
++#define mmSQ_PERFCOUNTER1_SELECT                                                0xd9c1
++#define mmSQ_PERFCOUNTER2_SELECT                                                0xd9c2
++#define mmSQ_PERFCOUNTER3_SELECT                                                0xd9c3
++#define mmSQ_PERFCOUNTER4_SELECT                                                0xd9c4
++#define mmSQ_PERFCOUNTER5_SELECT                                                0xd9c5
++#define mmSQ_PERFCOUNTER6_SELECT                                                0xd9c6
++#define mmSQ_PERFCOUNTER7_SELECT                                                0xd9c7
++#define mmSQ_PERFCOUNTER8_SELECT                                                0xd9c8
++#define mmSQ_PERFCOUNTER9_SELECT                                                0xd9c9
++#define mmSQ_PERFCOUNTER10_SELECT                                               0xd9ca
++#define mmSQ_PERFCOUNTER11_SELECT                                               0xd9cb
++#define mmSQ_PERFCOUNTER12_SELECT                                               0xd9cc
++#define mmSQ_PERFCOUNTER13_SELECT                                               0xd9cd
++#define mmSQ_PERFCOUNTER14_SELECT                                               0xd9ce
++#define mmSQ_PERFCOUNTER15_SELECT                                               0xd9cf
++#define mmCGTT_SQ_CLK_CTRL                                                      0xf08c
++#define mmCGTT_SQG_CLK_CTRL                                                     0xf08d
++#define mmSQ_ALU_CLK_CTRL                                                       0xf08e
++#define mmSQ_TEX_CLK_CTRL                                                       0xf08f
++#define mmSQ_LDS_CLK_CTRL                                                       0xf090
++#define mmSQ_POWER_THROTTLE                                                     0xf091
++#define mmSQ_POWER_THROTTLE2                                                    0xf092
++#define mmSQ_TIME_HI                                                            0x237c
++#define mmSQ_TIME_LO                                                            0x237d
++#define mmSQ_THREAD_TRACE_BASE                                                  0x2380
++#define mmSQ_THREAD_TRACE_BASE2                                                 0x2385
++#define mmSQ_THREAD_TRACE_SIZE                                                  0x2381
++#define mmSQ_THREAD_TRACE_MASK                                                  0x2382
++#define mmSQ_THREAD_TRACE_USERDATA_0                                            0xc340
++#define mmSQ_THREAD_TRACE_USERDATA_1                                            0xc341
++#define mmSQ_THREAD_TRACE_USERDATA_2                                            0xc342
++#define mmSQ_THREAD_TRACE_USERDATA_3                                            0xc343
++#define mmSQ_THREAD_TRACE_MODE                                                  0x238e
++#define mmSQ_THREAD_TRACE_CTRL                                                  0x238f
++#define mmSQ_THREAD_TRACE_TOKEN_MASK                                            0x2383
++#define mmSQ_THREAD_TRACE_TOKEN_MASK2                                           0x2386
++#define mmSQ_THREAD_TRACE_PERF_MASK                                             0x2384
++#define mmSQ_THREAD_TRACE_WPTR                                                  0x238c
++#define mmSQ_THREAD_TRACE_STATUS                                                0x238d
++#define mmSQ_THREAD_TRACE_CNTR                                                  0x2390
++#define mmSQ_THREAD_TRACE_HIWATER                                               0x2392
++#define mmSQ_LB_CTR_CTRL                                                        0x2398
++#define mmSQ_LB_DATA_ALU_CYCLES                                                 0x2399
++#define mmSQ_LB_DATA_TEX_CYCLES                                                 0x239a
++#define mmSQ_LB_DATA_ALU_STALLS                                                 0x239b
++#define mmSQ_LB_DATA_TEX_STALLS                                                 0x239c
++#define mmSQC_SECDED_CNT                                                        0x23a0
++#define mmSQ_SEC_CNT                                                            0x23a1
++#define mmSQ_DED_CNT                                                            0x23a2
++#define mmSQ_DED_INFO                                                           0x23a3
++#define mmSQ_BUF_RSRC_WORD0                                                     0x23c0
++#define mmSQ_BUF_RSRC_WORD1                                                     0x23c1
++#define mmSQ_BUF_RSRC_WORD2                                                     0x23c2
++#define mmSQ_BUF_RSRC_WORD3                                                     0x23c3
++#define mmSQ_IMG_RSRC_WORD0                                                     0x23c4
++#define mmSQ_IMG_RSRC_WORD1                                                     0x23c5
++#define mmSQ_IMG_RSRC_WORD2                                                     0x23c6
++#define mmSQ_IMG_RSRC_WORD3                                                     0x23c7
++#define mmSQ_IMG_RSRC_WORD4                                                     0x23c8
++#define mmSQ_IMG_RSRC_WORD5                                                     0x23c9
++#define mmSQ_IMG_RSRC_WORD6                                                     0x23ca
++#define mmSQ_IMG_RSRC_WORD7                                                     0x23cb
++#define mmSQ_IMG_SAMP_WORD0                                                     0x23cc
++#define mmSQ_IMG_SAMP_WORD1                                                     0x23cd
++#define mmSQ_IMG_SAMP_WORD2                                                     0x23ce
++#define mmSQ_IMG_SAMP_WORD3                                                     0x23cf
++#define mmSQ_FLAT_SCRATCH_WORD0                                                 0x23d0
++#define mmSQ_FLAT_SCRATCH_WORD1                                                 0x23d1
++#define mmSQ_IND_INDEX                                                          0x2378
++#define mmSQ_IND_CMD                                                            0x237a
++#define mmSQ_CMD                                                                0x237b
++#define mmSQ_IND_DATA                                                           0x2379
++#define mmSQ_REG_TIMESTAMP                                                      0x2374
++#define mmSQ_CMD_TIMESTAMP                                                      0x2375
++#define mmSQ_HV_VMID_CTRL                                                       0xf840
++#define ixSQ_WAVE_INST_DW0                                                      0x1a
++#define ixSQ_WAVE_INST_DW1                                                      0x1b
++#define ixSQ_WAVE_PC_LO                                                         0x18
++#define ixSQ_WAVE_PC_HI                                                         0x19
++#define ixSQ_WAVE_IB_DBG0                                                       0x1c
++#define ixSQ_WAVE_EXEC_LO                                                       0x27e
++#define ixSQ_WAVE_EXEC_HI                                                       0x27f
++#define ixSQ_WAVE_STATUS                                                        0x12
++#define ixSQ_WAVE_MODE                                                          0x11
++#define ixSQ_WAVE_TRAPSTS                                                       0x13
++#define ixSQ_WAVE_HW_ID                                                         0x14
++#define ixSQ_WAVE_GPR_ALLOC                                                     0x15
++#define ixSQ_WAVE_LDS_ALLOC                                                     0x16
++#define ixSQ_WAVE_IB_STS                                                        0x17
++#define ixSQ_WAVE_M0                                                            0x27c
++#define ixSQ_WAVE_TBA_LO                                                        0x26c
++#define ixSQ_WAVE_TBA_HI                                                        0x26d
++#define ixSQ_WAVE_TMA_LO                                                        0x26e
++#define ixSQ_WAVE_TMA_HI                                                        0x26f
++#define ixSQ_WAVE_TTMP0                                                         0x270
++#define ixSQ_WAVE_TTMP1                                                         0x271
++#define ixSQ_WAVE_TTMP2                                                         0x272
++#define ixSQ_WAVE_TTMP3                                                         0x273
++#define ixSQ_WAVE_TTMP4                                                         0x274
++#define ixSQ_WAVE_TTMP5                                                         0x275
++#define ixSQ_WAVE_TTMP6                                                         0x276
++#define ixSQ_WAVE_TTMP7                                                         0x277
++#define ixSQ_WAVE_TTMP8                                                         0x278
++#define ixSQ_WAVE_TTMP9                                                         0x279
++#define ixSQ_WAVE_TTMP10                                                        0x27a
++#define ixSQ_WAVE_TTMP11                                                        0x27b
++#define mmSQ_DEBUG_STS_GLOBAL                                                   0x2309
++#define mmSQ_DEBUG_STS_GLOBAL2                                                  0x2310
++#define mmSQ_DEBUG_STS_GLOBAL3                                                  0x2311
++#define ixSQ_DEBUG_STS_LOCAL                                                    0x8
++#define ixSQ_DEBUG_CTRL_LOCAL                                                   0x9
++#define mmSH_MEM_BASES                                                          0x230a
++#define mmSH_MEM_APE1_BASE                                                      0x230b
++#define mmSH_MEM_APE1_LIMIT                                                     0x230c
++#define mmSH_MEM_CONFIG                                                         0x230d
++#define mmSQC_POLICY                                                            0x230e
++#define mmSQC_VOLATILE                                                          0x230f
++#define mmSQ_THREAD_TRACE_WORD_CMN                                              0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2                                   0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2                                   0x23b1
++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2                             0x23b1
++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2                                 0x23b0
++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2                                 0x23b1
++#define mmSQ_THREAD_TRACE_WORD_WAVE                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_MISC                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_WAVE_START                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                                    0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2                                    0x23b0
++#define mmSQ_THREAD_TRACE_WORD_EVENT                                            0x23b0
++#define mmSQ_THREAD_TRACE_WORD_ISSUE                                            0x23b0
++#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2                                      0x23b0
++#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2                                      0x23b1
++#define ixSQ_INTERRUPT_WORD_CMN                                                 0x20c0
++#define ixSQ_INTERRUPT_WORD_AUTO                                                0x20c0
++#define ixSQ_INTERRUPT_WORD_WAVE                                                0x20c0
++#define mmSQ_SOP2                                                               0x237f
++#define mmSQ_VOP1                                                               0x237f
++#define mmSQ_MTBUF_1                                                            0x237f
++#define mmSQ_EXP_1                                                              0x237f
++#define mmSQ_MUBUF_1                                                            0x237f
++#define mmSQ_INST                                                               0x237f
++#define mmSQ_EXP_0                                                              0x237f
++#define mmSQ_MUBUF_0                                                            0x237f
++#define mmSQ_VOP3_0                                                             0x237f
++#define mmSQ_VOP2                                                               0x237f
++#define mmSQ_MTBUF_0                                                            0x237f
++#define mmSQ_SOPP                                                               0x237f
++#define mmSQ_FLAT_0                                                             0x237f
++#define mmSQ_VOP3_0_SDST_ENC                                                    0x237f
++#define mmSQ_MIMG_1                                                             0x237f
++#define mmSQ_SMRD                                                               0x237f
++#define mmSQ_SOP1                                                               0x237f
++#define mmSQ_SOPC                                                               0x237f
++#define mmSQ_FLAT_1                                                             0x237f
++#define mmSQ_DS_1                                                               0x237f
++#define mmSQ_VOP3_1                                                             0x237f
++#define mmSQ_MIMG_0                                                             0x237f
++#define mmSQ_SOPK                                                               0x237f
++#define mmSQ_DS_0                                                               0x237f
++#define mmSQ_VOPC                                                               0x237f
++#define mmSQ_VINTRP                                                             0x237f
++#define mmCGTT_SX_CLK_CTRL0                                                     0xf094
++#define mmCGTT_SX_CLK_CTRL1                                                     0xf095
++#define mmCGTT_SX_CLK_CTRL2                                                     0xf096
++#define mmCGTT_SX_CLK_CTRL3                                                     0xf097
++#define mmCGTT_SX_CLK_CTRL4                                                     0xf098
++#define mmSX_DEBUG_BUSY                                                         0x2414
++#define mmSX_DEBUG_BUSY_2                                                       0x2415
++#define mmSX_DEBUG_BUSY_3                                                       0x2416
++#define mmSX_DEBUG_BUSY_4                                                       0x2417
++#define mmSX_DEBUG_1                                                            0x2418
++#define mmSX_PERFCOUNTER0_SELECT                                                0xda40
++#define mmSX_PERFCOUNTER1_SELECT                                                0xda41
++#define mmSX_PERFCOUNTER2_SELECT                                                0xda42
++#define mmSX_PERFCOUNTER3_SELECT                                                0xda43
++#define mmSX_PERFCOUNTER0_SELECT1                                               0xda44
++#define mmSX_PERFCOUNTER1_SELECT1                                               0xda45
++#define mmSX_PERFCOUNTER0_LO                                                    0xd240
++#define mmSX_PERFCOUNTER0_HI                                                    0xd241
++#define mmSX_PERFCOUNTER1_LO                                                    0xd242
++#define mmSX_PERFCOUNTER1_HI                                                    0xd243
++#define mmSX_PERFCOUNTER2_LO                                                    0xd244
++#define mmSX_PERFCOUNTER2_HI                                                    0xd245
++#define mmSX_PERFCOUNTER3_LO                                                    0xd246
++#define mmSX_PERFCOUNTER3_HI                                                    0xd247
++#define mmTCC_CTRL                                                              0x2b80
++#define mmTCC_EDC_COUNTER                                                       0x2b82
++#define mmTCC_REDUNDANCY                                                        0x2b83
++#define mmTCC_CGTT_SCLK_CTRL                                                    0xf0ac
++#define mmTCA_CGTT_SCLK_CTRL                                                    0xf0ad
++#define mmTCS_CGTT_SCLK_CTRL                                                    0xf0ae
++#define mmTCC_PERFCOUNTER0_SELECT                                               0xdb80
++#define mmTCC_PERFCOUNTER1_SELECT                                               0xdb82
++#define mmTCC_PERFCOUNTER0_SELECT1                                              0xdb81
++#define mmTCC_PERFCOUNTER1_SELECT1                                              0xdb83
++#define mmTCC_PERFCOUNTER2_SELECT                                               0xdb84
++#define mmTCC_PERFCOUNTER3_SELECT                                               0xdb85
++#define mmTCC_PERFCOUNTER0_LO                                                   0xd380
++#define mmTCC_PERFCOUNTER1_LO                                                   0xd382
++#define mmTCC_PERFCOUNTER2_LO                                                   0xd384
++#define mmTCC_PERFCOUNTER3_LO                                                   0xd386
++#define mmTCC_PERFCOUNTER0_HI                                                   0xd381
++#define mmTCC_PERFCOUNTER1_HI                                                   0xd383
++#define mmTCC_PERFCOUNTER2_HI                                                   0xd385
++#define mmTCC_PERFCOUNTER3_HI                                                   0xd387
++#define mmTCA_CTRL                                                              0x2bc0
++#define mmTCA_PERFCOUNTER0_SELECT                                               0xdb90
++#define mmTCA_PERFCOUNTER1_SELECT                                               0xdb92
++#define mmTCA_PERFCOUNTER0_SELECT1                                              0xdb91
++#define mmTCA_PERFCOUNTER1_SELECT1                                              0xdb93
++#define mmTCA_PERFCOUNTER2_SELECT                                               0xdb94
++#define mmTCA_PERFCOUNTER3_SELECT                                               0xdb95
++#define mmTCA_PERFCOUNTER0_LO                                                   0xd390
++#define mmTCA_PERFCOUNTER1_LO                                                   0xd392
++#define mmTCA_PERFCOUNTER2_LO                                                   0xd394
++#define mmTCA_PERFCOUNTER3_LO                                                   0xd396
++#define mmTCA_PERFCOUNTER0_HI                                                   0xd391
++#define mmTCA_PERFCOUNTER1_HI                                                   0xd393
++#define mmTCA_PERFCOUNTER2_HI                                                   0xd395
++#define mmTCA_PERFCOUNTER3_HI                                                   0xd397
++#define mmTCS_CTRL                                                              0x2be0
++#define mmTCS_PERFCOUNTER0_SELECT                                               0xdba0
++#define mmTCS_PERFCOUNTER0_SELECT1                                              0xdba1
++#define mmTCS_PERFCOUNTER1_SELECT                                               0xdba2
++#define mmTCS_PERFCOUNTER2_SELECT                                               0xdba3
++#define mmTCS_PERFCOUNTER3_SELECT                                               0xdba4
++#define mmTCS_PERFCOUNTER0_LO                                                   0xd3a0
++#define mmTCS_PERFCOUNTER1_LO                                                   0xd3a2
++#define mmTCS_PERFCOUNTER2_LO                                                   0xd3a4
++#define mmTCS_PERFCOUNTER3_LO                                                   0xd3a6
++#define mmTCS_PERFCOUNTER0_HI                                                   0xd3a1
++#define mmTCS_PERFCOUNTER1_HI                                                   0xd3a3
++#define mmTCS_PERFCOUNTER2_HI                                                   0xd3a5
++#define mmTCS_PERFCOUNTER3_HI                                                   0xd3a7
++#define mmTA_BC_BASE_ADDR                                                       0xa020
++#define mmTA_BC_BASE_ADDR_HI                                                    0xa021
++#define mmTD_CNTL                                                               0x2525
++#define mmTD_STATUS                                                             0x2526
++#define mmTD_DEBUG_INDEX                                                        0x2528
++#define mmTD_DEBUG_DATA                                                         0x2529
++#define mmTD_PERFCOUNTER0_SELECT                                                0xdb00
++#define mmTD_PERFCOUNTER1_SELECT                                                0xdb02
++#define mmTD_PERFCOUNTER0_SELECT1                                               0xdb01
++#define mmTD_PERFCOUNTER0_LO                                                    0xd300
++#define mmTD_PERFCOUNTER1_LO                                                    0xd302
++#define mmTD_PERFCOUNTER0_HI                                                    0xd301
++#define mmTD_PERFCOUNTER1_HI                                                    0xd303
++#define mmTD_SCRATCH                                                            0x2533
++#define mmTA_CNTL                                                               0x2541
++#define mmTA_CNTL_AUX                                                           0x2542
++#define mmTA_RESERVED_010C                                                      0x2543
++#define mmTA_CS_BC_BASE_ADDR                                                    0xc380
++#define mmTA_CS_BC_BASE_ADDR_HI                                                 0xc381
++#define mmTA_STATUS                                                             0x2548
++#define mmTA_DEBUG_INDEX                                                        0x254c
++#define mmTA_DEBUG_DATA                                                         0x254d
++#define mmTA_PERFCOUNTER0_SELECT                                                0xdac0
++#define mmTA_PERFCOUNTER1_SELECT                                                0xdac2
++#define mmTA_PERFCOUNTER0_SELECT1                                               0xdac1
++#define mmTA_PERFCOUNTER0_LO                                                    0xd2c0
++#define mmTA_PERFCOUNTER1_LO                                                    0xd2c2
++#define mmTA_PERFCOUNTER0_HI                                                    0xd2c1
++#define mmTA_PERFCOUNTER1_HI                                                    0xd2c3
++#define mmTA_SCRATCH                                                            0x2564
++#define mmSH_HIDDEN_PRIVATE_BASE_VMID                                           0x2580
++#define mmSH_STATIC_MEM_CONFIG                                                  0x2581
++#define mmTCP_INVALIDATE                                                        0x2b00
++#define mmTCP_STATUS                                                            0x2b01
++#define mmTCP_CNTL                                                              0x2b02
++#define mmTCP_CHAN_STEER_LO                                                     0x2b03
++#define mmTCP_CHAN_STEER_HI                                                     0x2b04
++#define mmTCP_ADDR_CONFIG                                                       0x2b05
++#define mmTCP_CREDIT                                                            0x2b06
++#define mmTCP_PERFCOUNTER0_SELECT                                               0xdb40
++#define mmTCP_PERFCOUNTER1_SELECT                                               0xdb42
++#define mmTCP_PERFCOUNTER0_SELECT1                                              0xdb41
++#define mmTCP_PERFCOUNTER1_SELECT1                                              0xdb43
++#define mmTCP_PERFCOUNTER2_SELECT                                               0xdb44
++#define mmTCP_PERFCOUNTER3_SELECT                                               0xdb45
++#define mmTCP_PERFCOUNTER0_LO                                                   0xd340
++#define mmTCP_PERFCOUNTER1_LO                                                   0xd342
++#define mmTCP_PERFCOUNTER2_LO                                                   0xd344
++#define mmTCP_PERFCOUNTER3_LO                                                   0xd346
++#define mmTCP_PERFCOUNTER0_HI                                                   0xd341
++#define mmTCP_PERFCOUNTER1_HI                                                   0xd343
++#define mmTCP_PERFCOUNTER2_HI                                                   0xd345
++#define mmTCP_PERFCOUNTER3_HI                                                   0xd347
++#define mmTCP_BUFFER_ADDR_HASH_CNTL                                             0x2b16
++#define mmTCP_EDC_COUNTER                                                       0x2b17
++#define mmTC_CFG_L1_LOAD_POLICY0                                                0x2b1a
++#define mmTC_CFG_L1_LOAD_POLICY1                                                0x2b1b
++#define mmTC_CFG_L1_STORE_POLICY                                                0x2b1c
++#define mmTC_CFG_L2_LOAD_POLICY0                                                0x2b1d
++#define mmTC_CFG_L2_LOAD_POLICY1                                                0x2b1e
++#define mmTC_CFG_L2_STORE_POLICY0                                               0x2b1f
++#define mmTC_CFG_L2_STORE_POLICY1                                               0x2b20
++#define mmTC_CFG_L2_ATOMIC_POLICY                                               0x2b21
++#define mmTC_CFG_L1_VOLATILE                                                    0x2b22
++#define mmTC_CFG_L2_VOLATILE                                                    0x2b23
++#define mmTCP_WATCH0_ADDR_H                                                     0x32a0
++#define mmTCP_WATCH1_ADDR_H                                                     0x32a3
++#define mmTCP_WATCH2_ADDR_H                                                     0x32a6
++#define mmTCP_WATCH3_ADDR_H                                                     0x32a9
++#define mmTCP_WATCH0_ADDR_L                                                     0x32a1
++#define mmTCP_WATCH1_ADDR_L                                                     0x32a4
++#define mmTCP_WATCH2_ADDR_L                                                     0x32a7
++#define mmTCP_WATCH3_ADDR_L                                                     0x32aa
++#define mmTCP_WATCH0_CNTL                                                       0x32a2
++#define mmTCP_WATCH1_CNTL                                                       0x32a5
++#define mmTCP_WATCH2_CNTL                                                       0x32a8
++#define mmTCP_WATCH3_CNTL                                                       0x32ab
++#define mmTD_CGTT_CTRL                                                          0xf09c
++#define mmTA_CGTT_CTRL                                                          0xf09d
++#define mmCGTT_TCP_CLK_CTRL                                                     0xf09e
++#define mmCGTT_TCI_CLK_CTRL                                                     0xf09f
++#define mmTCI_STATUS                                                            0x2b61
++#define mmTCI_CNTL_1                                                            0x2b62
++#define mmTCI_CNTL_2                                                            0x2b63
++#define mmGDS_CONFIG                                                            0x25c0
++#define mmGDS_CNTL_STATUS                                                       0x25c1
++#define mmGDS_ENHANCE2                                                          0x25c2
++#define mmGDS_PROTECTION_FAULT                                                  0x25c3
++#define mmGDS_VM_PROTECTION_FAULT                                               0x25c4
++#define mmGDS_SECDED_CNT                                                        0x25c5
++#define mmGDS_GRBM_SECDED_CNT                                                   0x25c6
++#define mmGDS_OA_DED                                                            0x25c7
++#define mmGDS_DEBUG_CNTL                                                        0x25c8
++#define mmGDS_DEBUG_DATA                                                        0x25c9
++#define mmCGTT_GDS_CLK_CTRL                                                     0xf0a0
++#define mmGDS_RD_ADDR                                                           0xc400
++#define mmGDS_RD_DATA                                                           0xc401
++#define mmGDS_RD_BURST_ADDR                                                     0xc402
++#define mmGDS_RD_BURST_COUNT                                                    0xc403
++#define mmGDS_RD_BURST_DATA                                                     0xc404
++#define mmGDS_WR_ADDR                                                           0xc405
++#define mmGDS_WR_DATA                                                           0xc406
++#define mmGDS_WR_BURST_ADDR                                                     0xc407
++#define mmGDS_WR_BURST_DATA                                                     0xc408
++#define mmGDS_WRITE_COMPLETE                                                    0xc409
++#define mmGDS_ATOM_CNTL                                                         0xc40a
++#define mmGDS_ATOM_COMPLETE                                                     0xc40b
++#define mmGDS_ATOM_BASE                                                         0xc40c
++#define mmGDS_ATOM_SIZE                                                         0xc40d
++#define mmGDS_ATOM_OFFSET0                                                      0xc40e
++#define mmGDS_ATOM_OFFSET1                                                      0xc40f
++#define mmGDS_ATOM_DST                                                          0xc410
++#define mmGDS_ATOM_OP                                                           0xc411
++#define mmGDS_ATOM_SRC0                                                         0xc412
++#define mmGDS_ATOM_SRC0_U                                                       0xc413
++#define mmGDS_ATOM_SRC1                                                         0xc414
++#define mmGDS_ATOM_SRC1_U                                                       0xc415
++#define mmGDS_ATOM_READ0                                                        0xc416
++#define mmGDS_ATOM_READ0_U                                                      0xc417
++#define mmGDS_ATOM_READ1                                                        0xc418
++#define mmGDS_ATOM_READ1_U                                                      0xc419
++#define mmGDS_GWS_RESOURCE_CNTL                                                 0xc41a
++#define mmGDS_GWS_RESOURCE                                                      0xc41b
++#define mmGDS_GWS_RESOURCE_CNT                                                  0xc41c
++#define mmGDS_OA_CNTL                                                           0xc41d
++#define mmGDS_OA_COUNTER                                                        0xc41e
++#define mmGDS_OA_ADDRESS                                                        0xc41f
++#define mmGDS_OA_INCDEC                                                         0xc420
++#define mmGDS_OA_RING_SIZE                                                      0xc421
++#define ixGDS_DEBUG_REG0                                                        0x0
++#define ixGDS_DEBUG_REG1                                                        0x1
++#define ixGDS_DEBUG_REG2                                                        0x2
++#define ixGDS_DEBUG_REG3                                                        0x3
++#define ixGDS_DEBUG_REG4                                                        0x4
++#define ixGDS_DEBUG_REG5                                                        0x5
++#define ixGDS_DEBUG_REG6                                                        0x6
++#define mmGDS_PERFCOUNTER0_SELECT                                               0xda80
++#define mmGDS_PERFCOUNTER1_SELECT                                               0xda81
++#define mmGDS_PERFCOUNTER2_SELECT                                               0xda82
++#define mmGDS_PERFCOUNTER3_SELECT                                               0xda83
++#define mmGDS_PERFCOUNTER0_LO                                                   0xd280
++#define mmGDS_PERFCOUNTER1_LO                                                   0xd282
++#define mmGDS_PERFCOUNTER2_LO                                                   0xd284
++#define mmGDS_PERFCOUNTER3_LO                                                   0xd286
++#define mmGDS_PERFCOUNTER0_HI                                                   0xd281
++#define mmGDS_PERFCOUNTER1_HI                                                   0xd283
++#define mmGDS_PERFCOUNTER2_HI                                                   0xd285
++#define mmGDS_PERFCOUNTER3_HI                                                   0xd287
++#define mmGDS_PERFCOUNTER0_SELECT1                                              0xda84
++#define mmGDS_VMID0_BASE                                                        0x3300
++#define mmGDS_VMID1_BASE                                                        0x3302
++#define mmGDS_VMID2_BASE                                                        0x3304
++#define mmGDS_VMID3_BASE                                                        0x3306
++#define mmGDS_VMID4_BASE                                                        0x3308
++#define mmGDS_VMID5_BASE                                                        0x330a
++#define mmGDS_VMID6_BASE                                                        0x330c
++#define mmGDS_VMID7_BASE                                                        0x330e
++#define mmGDS_VMID8_BASE                                                        0x3310
++#define mmGDS_VMID9_BASE                                                        0x3312
++#define mmGDS_VMID10_BASE                                                       0x3314
++#define mmGDS_VMID11_BASE                                                       0x3316
++#define mmGDS_VMID12_BASE                                                       0x3318
++#define mmGDS_VMID13_BASE                                                       0x331a
++#define mmGDS_VMID14_BASE                                                       0x331c
++#define mmGDS_VMID15_BASE                                                       0x331e
++#define mmGDS_VMID0_SIZE                                                        0x3301
++#define mmGDS_VMID1_SIZE                                                        0x3303
++#define mmGDS_VMID2_SIZE                                                        0x3305
++#define mmGDS_VMID3_SIZE                                                        0x3307
++#define mmGDS_VMID4_SIZE                                                        0x3309
++#define mmGDS_VMID5_SIZE                                                        0x330b
++#define mmGDS_VMID6_SIZE                                                        0x330d
++#define mmGDS_VMID7_SIZE                                                        0x330f
++#define mmGDS_VMID8_SIZE                                                        0x3311
++#define mmGDS_VMID9_SIZE                                                        0x3313
++#define mmGDS_VMID10_SIZE                                                       0x3315
++#define mmGDS_VMID11_SIZE                                                       0x3317
++#define mmGDS_VMID12_SIZE                                                       0x3319
++#define mmGDS_VMID13_SIZE                                                       0x331b
++#define mmGDS_VMID14_SIZE                                                       0x331d
++#define mmGDS_VMID15_SIZE                                                       0x331f
++#define mmGDS_GWS_VMID0                                                         0x3320
++#define mmGDS_GWS_VMID1                                                         0x3321
++#define mmGDS_GWS_VMID2                                                         0x3322
++#define mmGDS_GWS_VMID3                                                         0x3323
++#define mmGDS_GWS_VMID4                                                         0x3324
++#define mmGDS_GWS_VMID5                                                         0x3325
++#define mmGDS_GWS_VMID6                                                         0x3326
++#define mmGDS_GWS_VMID7                                                         0x3327
++#define mmGDS_GWS_VMID8                                                         0x3328
++#define mmGDS_GWS_VMID9                                                         0x3329
++#define mmGDS_GWS_VMID10                                                        0x332a
++#define mmGDS_GWS_VMID11                                                        0x332b
++#define mmGDS_GWS_VMID12                                                        0x332c
++#define mmGDS_GWS_VMID13                                                        0x332d
++#define mmGDS_GWS_VMID14                                                        0x332e
++#define mmGDS_GWS_VMID15                                                        0x332f
++#define mmGDS_OA_VMID0                                                          0x3330
++#define mmGDS_OA_VMID1                                                          0x3331
++#define mmGDS_OA_VMID2                                                          0x3332
++#define mmGDS_OA_VMID3                                                          0x3333
++#define mmGDS_OA_VMID4                                                          0x3334
++#define mmGDS_OA_VMID5                                                          0x3335
++#define mmGDS_OA_VMID6                                                          0x3336
++#define mmGDS_OA_VMID7                                                          0x3337
++#define mmGDS_OA_VMID8                                                          0x3338
++#define mmGDS_OA_VMID9                                                          0x3339
++#define mmGDS_OA_VMID10                                                         0x333a
++#define mmGDS_OA_VMID11                                                         0x333b
++#define mmGDS_OA_VMID12                                                         0x333c
++#define mmGDS_OA_VMID13                                                         0x333d
++#define mmGDS_OA_VMID14                                                         0x333e
++#define mmGDS_OA_VMID15                                                         0x333f
++#define mmGDS_GWS_RESET0                                                        0x3344
++#define mmGDS_GWS_RESET1                                                        0x3345
++#define mmGDS_GWS_RESOURCE_RESET                                                0x3346
++#define mmGDS_COMPUTE_MAX_WAVE_ID                                               0x3348
++#define mmGDS_OA_RESET_MASK                                                     0x3349
++#define mmGDS_OA_RESET                                                          0x334a
++#define mmGDS_ENHANCE                                                           0x334b
++#define mmGDS_OA_CGPG_RESTORE                                                   0x334c
++#define mmCS_COPY_STATE                                                         0xa1f3
++#define mmGFX_COPY_STATE                                                        0xa1f4
++#define mmVGT_DRAW_INITIATOR                                                    0xa1fc
++#define mmVGT_EVENT_INITIATOR                                                   0xa2a4
++#define mmVGT_EVENT_ADDRESS_REG                                                 0xa1fe
++#define mmVGT_DMA_BASE_HI                                                       0xa1f9
++#define mmVGT_DMA_BASE                                                          0xa1fa
++#define mmVGT_DMA_INDEX_TYPE                                                    0xa29f
++#define mmVGT_DMA_NUM_INSTANCES                                                 0xa2a2
++#define mmIA_ENHANCE                                                            0xa29c
++#define mmVGT_DMA_SIZE                                                          0xa29d
++#define mmVGT_DMA_MAX_SIZE                                                      0xa29e
++#define mmVGT_DMA_PRIMITIVE_TYPE                                                0x2271
++#define mmVGT_DMA_CONTROL                                                       0x2272
++#define mmVGT_IMMED_DATA                                                        0xa1fd
++#define mmVGT_INDEX_TYPE                                                        0xc243
++#define mmVGT_NUM_INDICES                                                       0xc24c
++#define mmVGT_NUM_INSTANCES                                                     0xc24d
++#define mmVGT_PRIMITIVE_TYPE                                                    0xc242
++#define mmVGT_PRIMITIVEID_EN                                                    0xa2a1
++#define mmVGT_PRIMITIVEID_RESET                                                 0xa2a3
++#define mmVGT_VTX_CNT_EN                                                        0xa2ae
++#define mmVGT_REUSE_OFF                                                         0xa2ad
++#define mmVGT_INSTANCE_STEP_RATE_0                                              0xa2a8
++#define mmVGT_INSTANCE_STEP_RATE_1                                              0xa2a9
++#define mmVGT_MAX_VTX_INDX                                                      0xa100
++#define mmVGT_MIN_VTX_INDX                                                      0xa101
++#define mmVGT_INDX_OFFSET                                                       0xa102
++#define mmVGT_VERTEX_REUSE_BLOCK_CNTL                                           0xa316
++#define mmVGT_OUT_DEALLOC_CNTL                                                  0xa317
++#define mmVGT_MULTI_PRIM_IB_RESET_INDX                                          0xa103
++#define mmVGT_MULTI_PRIM_IB_RESET_EN                                            0xa2a5
++#define mmVGT_ENHANCE                                                           0xa294
++#define mmVGT_OUTPUT_PATH_CNTL                                                  0xa284
++#define mmVGT_HOS_CNTL                                                          0xa285
++#define mmVGT_HOS_MAX_TESS_LEVEL                                                0xa286
++#define mmVGT_HOS_MIN_TESS_LEVEL                                                0xa287
++#define mmVGT_HOS_REUSE_DEPTH                                                   0xa288
++#define mmVGT_GROUP_PRIM_TYPE                                                   0xa289
++#define mmVGT_GROUP_FIRST_DECR                                                  0xa28a
++#define mmVGT_GROUP_DECR                                                        0xa28b
++#define mmVGT_GROUP_VECT_0_CNTL                                                 0xa28c
++#define mmVGT_GROUP_VECT_1_CNTL                                                 0xa28d
++#define mmVGT_GROUP_VECT_0_FMT_CNTL                                             0xa28e
++#define mmVGT_GROUP_VECT_1_FMT_CNTL                                             0xa28f
++#define mmVGT_VTX_VECT_EJECT_REG                                                0x222c
++#define mmVGT_DMA_DATA_FIFO_DEPTH                                               0x222d
++#define mmVGT_DMA_REQ_FIFO_DEPTH                                                0x222e
++#define mmVGT_DRAW_INIT_FIFO_DEPTH                                              0x222f
++#define mmVGT_LAST_COPY_STATE                                                   0x2230
++#define mmCC_GC_SHADER_ARRAY_CONFIG                                             0x226f
++#define mmGC_USER_SHADER_ARRAY_CONFIG                                           0x2270
++#define mmVGT_GS_MODE                                                           0xa290
++#define mmVGT_GS_ONCHIP_CNTL                                                    0xa291
++#define mmVGT_GS_OUT_PRIM_TYPE                                                  0xa29b
++#define mmVGT_CACHE_INVALIDATION                                                0x2231
++#define mmVGT_RESET_DEBUG                                                       0x2232
++#define mmVGT_STRMOUT_DELAY                                                     0x2233
++#define mmVGT_FIFO_DEPTHS                                                       0x2234
++#define mmVGT_GS_PER_ES                                                         0xa295
++#define mmVGT_ES_PER_GS                                                         0xa296
++#define mmVGT_GS_PER_VS                                                         0xa297
++#define mmVGT_GS_VERTEX_REUSE                                                   0x2235
++#define mmVGT_MC_LAT_CNTL                                                       0x2236
++#define mmIA_CNTL_STATUS                                                        0x2237
++#define mmVGT_STRMOUT_CONFIG                                                    0xa2e5
++#define mmVGT_STRMOUT_BUFFER_SIZE_0                                             0xa2b4
++#define mmVGT_STRMOUT_BUFFER_SIZE_1                                             0xa2b8
++#define mmVGT_STRMOUT_BUFFER_SIZE_2                                             0xa2bc
++#define mmVGT_STRMOUT_BUFFER_SIZE_3                                             0xa2c0
++#define mmVGT_STRMOUT_BUFFER_OFFSET_0                                           0xa2b7
++#define mmVGT_STRMOUT_BUFFER_OFFSET_1                                           0xa2bb
++#define mmVGT_STRMOUT_BUFFER_OFFSET_2                                           0xa2bf
++#define mmVGT_STRMOUT_BUFFER_OFFSET_3                                           0xa2c3
++#define mmVGT_STRMOUT_VTX_STRIDE_0                                              0xa2b5
++#define mmVGT_STRMOUT_VTX_STRIDE_1                                              0xa2b9
++#define mmVGT_STRMOUT_VTX_STRIDE_2                                              0xa2bd
++#define mmVGT_STRMOUT_VTX_STRIDE_3                                              0xa2c1
++#define mmVGT_STRMOUT_BUFFER_CONFIG                                             0xa2e6
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                                      0xc244
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                                      0xc245
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                                      0xc246
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                                      0xc247
++#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                        0xa2ca
++#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                            0xa2cb
++#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                 0xa2cc
++#define mmVGT_GS_MAX_VERT_OUT                                                   0xa2ce
++#define mmIA_VMID_OVERRIDE                                                      0x2260
++#define mmVGT_SHADER_STAGES_EN                                                  0xa2d5
++#define mmVGT_DISPATCH_DRAW_INDEX                                               0xa2dd
++#define mmVGT_LS_HS_CONFIG                                                      0xa2d6
++#define mmVGT_DMA_LS_HS_CONFIG                                                  0x2273
++#define mmVGT_TF_PARAM                                                          0xa2db
++#define mmVGT_TF_RING_SIZE                                                      0xc24e
++#define mmVGT_SYS_CONFIG                                                        0x2263
++#define mmVGT_HS_OFFCHIP_PARAM                                                  0xc24f
++#define mmVGT_TF_MEMORY_BASE                                                    0xc250
++#define mmVGT_GS_INSTANCE_CNT                                                   0xa2e4
++#define mmIA_MULTI_VGT_PARAM                                                    0xa2aa
++#define mmVGT_VS_MAX_WAVE_ID                                                    0x2268
++#define mmVGT_ESGS_RING_SIZE                                                    0xc240
++#define mmVGT_GSVS_RING_SIZE                                                    0xc241
++#define mmVGT_GSVS_RING_OFFSET_1                                                0xa298
++#define mmVGT_GSVS_RING_OFFSET_2                                                0xa299
++#define mmVGT_GSVS_RING_OFFSET_3                                                0xa29a
++#define mmVGT_ESGS_RING_ITEMSIZE                                                0xa2ab
++#define mmVGT_GSVS_RING_ITEMSIZE                                                0xa2ac
++#define mmVGT_GS_VERT_ITEMSIZE                                                  0xa2d7
++#define mmVGT_GS_VERT_ITEMSIZE_1                                                0xa2d8
++#define mmVGT_GS_VERT_ITEMSIZE_2                                                0xa2d9
++#define mmVGT_GS_VERT_ITEMSIZE_3                                                0xa2da
++#define mmWD_CNTL_STATUS                                                        0x223f
++#define mmWD_ENHANCE                                                            0xa2a0
++#define mmGFX_PIPE_CONTROL                                                      0x226d
++#define mmGFX_PIPE_PRIORITY                                                     0xf87f
++#define mmCGTT_VGT_CLK_CTRL                                                     0xf084
++#define mmCGTT_IA_CLK_CTRL                                                      0xf085
++#define mmCGTT_WD_CLK_CTRL                                                      0xf086
++#define mmVGT_DEBUG_CNTL                                                        0x2238
++#define mmVGT_DEBUG_DATA                                                        0x2239
++#define mmIA_DEBUG_CNTL                                                         0x223a
++#define mmIA_DEBUG_DATA                                                         0x223b
++#define mmVGT_CNTL_STATUS                                                       0x223c
++#define mmWD_DEBUG_CNTL                                                         0x223d
++#define mmWD_DEBUG_DATA                                                         0x223e
++#define mmCC_GC_PRIM_CONFIG                                                     0x2240
++#define mmGC_USER_PRIM_CONFIG                                                   0x2241
++#define ixWD_DEBUG_REG0                                                         0x0
++#define ixWD_DEBUG_REG1                                                         0x1
++#define ixWD_DEBUG_REG2                                                         0x2
++#define ixWD_DEBUG_REG3                                                         0x3
++#define ixWD_DEBUG_REG4                                                         0x4
++#define ixWD_DEBUG_REG5                                                         0x5
++#define ixIA_DEBUG_REG0                                                         0x0
++#define ixIA_DEBUG_REG1                                                         0x1
++#define ixIA_DEBUG_REG2                                                         0x2
++#define ixIA_DEBUG_REG3                                                         0x3
++#define ixIA_DEBUG_REG4                                                         0x4
++#define ixIA_DEBUG_REG5                                                         0x5
++#define ixIA_DEBUG_REG6                                                         0x6
++#define ixIA_DEBUG_REG7                                                         0x7
++#define ixIA_DEBUG_REG8                                                         0x8
++#define ixIA_DEBUG_REG9                                                         0x9
++#define ixVGT_DEBUG_REG0                                                        0x0
++#define ixVGT_DEBUG_REG1                                                        0x1
++#define ixVGT_DEBUG_REG2                                                        0x1e
++#define ixVGT_DEBUG_REG3                                                        0x1f
++#define ixVGT_DEBUG_REG4                                                        0x20
++#define ixVGT_DEBUG_REG5                                                        0x21
++#define ixVGT_DEBUG_REG6                                                        0x22
++#define ixVGT_DEBUG_REG7                                                        0x23
++#define ixVGT_DEBUG_REG8                                                        0x8
++#define ixVGT_DEBUG_REG9                                                        0x9
++#define ixVGT_DEBUG_REG10                                                       0xa
++#define ixVGT_DEBUG_REG11                                                       0xb
++#define ixVGT_DEBUG_REG12                                                       0xc
++#define ixVGT_DEBUG_REG13                                                       0xd
++#define ixVGT_DEBUG_REG14                                                       0xe
++#define ixVGT_DEBUG_REG15                                                       0xf
++#define ixVGT_DEBUG_REG16                                                       0x10
++#define ixVGT_DEBUG_REG17                                                       0x11
++#define ixVGT_DEBUG_REG18                                                       0x7
++#define ixVGT_DEBUG_REG19                                                       0x13
++#define ixVGT_DEBUG_REG20                                                       0x14
++#define ixVGT_DEBUG_REG21                                                       0x15
++#define ixVGT_DEBUG_REG22                                                       0x16
++#define ixVGT_DEBUG_REG23                                                       0x17
++#define ixVGT_DEBUG_REG24                                                       0x18
++#define ixVGT_DEBUG_REG25                                                       0x19
++#define ixVGT_DEBUG_REG26                                                       0x24
++#define ixVGT_DEBUG_REG27                                                       0x1b
++#define ixVGT_DEBUG_REG28                                                       0x1c
++#define ixVGT_DEBUG_REG29                                                       0x1d
++#define ixVGT_DEBUG_REG30                                                       0x25
++#define ixVGT_DEBUG_REG31                                                       0x26
++#define ixVGT_DEBUG_REG32                                                       0x27
++#define ixVGT_DEBUG_REG33                                                       0x28
++#define ixVGT_DEBUG_REG34                                                       0x29
++#define ixVGT_DEBUG_REG35                                                       0x2a
++#define mmVGT_PERFCOUNTER_SEID_MASK                                             0xd894
++#define mmVGT_PERFCOUNTER0_SELECT                                               0xd88c
++#define mmVGT_PERFCOUNTER1_SELECT                                               0xd88d
++#define mmVGT_PERFCOUNTER2_SELECT                                               0xd88e
++#define mmVGT_PERFCOUNTER3_SELECT                                               0xd88f
++#define mmVGT_PERFCOUNTER0_SELECT1                                              0xd890
++#define mmVGT_PERFCOUNTER1_SELECT1                                              0xd891
++#define mmVGT_PERFCOUNTER0_LO                                                   0xd090
++#define mmVGT_PERFCOUNTER1_LO                                                   0xd092
++#define mmVGT_PERFCOUNTER2_LO                                                   0xd094
++#define mmVGT_PERFCOUNTER3_LO                                                   0xd096
++#define mmVGT_PERFCOUNTER0_HI                                                   0xd091
++#define mmVGT_PERFCOUNTER1_HI                                                   0xd093
++#define mmVGT_PERFCOUNTER2_HI                                                   0xd095
++#define mmVGT_PERFCOUNTER3_HI                                                   0xd097
++#define mmIA_PERFCOUNTER0_SELECT                                                0xd884
++#define mmIA_PERFCOUNTER1_SELECT                                                0xd885
++#define mmIA_PERFCOUNTER2_SELECT                                                0xd886
++#define mmIA_PERFCOUNTER3_SELECT                                                0xd887
++#define mmIA_PERFCOUNTER0_SELECT1                                               0xd888
++#define mmIA_PERFCOUNTER0_LO                                                    0xd088
++#define mmIA_PERFCOUNTER1_LO                                                    0xd08a
++#define mmIA_PERFCOUNTER2_LO                                                    0xd08c
++#define mmIA_PERFCOUNTER3_LO                                                    0xd08e
++#define mmIA_PERFCOUNTER0_HI                                                    0xd089
++#define mmIA_PERFCOUNTER1_HI                                                    0xd08b
++#define mmIA_PERFCOUNTER2_HI                                                    0xd08d
++#define mmIA_PERFCOUNTER3_HI                                                    0xd08f
++#define mmWD_PERFCOUNTER0_SELECT                                                0xd880
++#define mmWD_PERFCOUNTER1_SELECT                                                0xd881
++#define mmWD_PERFCOUNTER2_SELECT                                                0xd882
++#define mmWD_PERFCOUNTER3_SELECT                                                0xd883
++#define mmWD_PERFCOUNTER0_LO                                                    0xd080
++#define mmWD_PERFCOUNTER1_LO                                                    0xd082
++#define mmWD_PERFCOUNTER2_LO                                                    0xd084
++#define mmWD_PERFCOUNTER3_LO                                                    0xd086
++#define mmWD_PERFCOUNTER0_HI                                                    0xd081
++#define mmWD_PERFCOUNTER1_HI                                                    0xd083
++#define mmWD_PERFCOUNTER2_HI                                                    0xd085
++#define mmWD_PERFCOUNTER3_HI                                                    0xd087
++#define mmDIDT_IND_INDEX                                                        0x3280
++#define mmDIDT_IND_DATA                                                         0x3281
++#define ixDIDT_SQ_CTRL0                                                         0x0
++#define ixDIDT_SQ_CTRL1                                                         0x1
++#define ixDIDT_SQ_CTRL2                                                         0x2
++#define ixDIDT_SQ_WEIGHT0_3                                                     0x10
++#define ixDIDT_SQ_WEIGHT4_7                                                     0x11
++#define ixDIDT_SQ_WEIGHT8_11                                                    0x12
++#define ixDIDT_DB_CTRL0                                                         0x20
++#define ixDIDT_DB_CTRL1                                                         0x21
++#define ixDIDT_DB_CTRL2                                                         0x22
++#define ixDIDT_DB_WEIGHT0_3                                                     0x30
++#define ixDIDT_DB_WEIGHT4_7                                                     0x31
++#define ixDIDT_DB_WEIGHT8_11                                                    0x32
++#define ixDIDT_TD_CTRL0                                                         0x40
++#define ixDIDT_TD_CTRL1                                                         0x41
++#define ixDIDT_TD_CTRL2                                                         0x42
++#define ixDIDT_TD_WEIGHT0_3                                                     0x50
++#define ixDIDT_TD_WEIGHT4_7                                                     0x51
++#define ixDIDT_TD_WEIGHT8_11                                                    0x52
++#define ixDIDT_TCP_CTRL0                                                        0x60
++#define ixDIDT_TCP_CTRL1                                                        0x61
++#define ixDIDT_TCP_CTRL2                                                        0x62
++#define ixDIDT_TCP_WEIGHT0_3                                                    0x70
++#define ixDIDT_TCP_WEIGHT4_7                                                    0x71
++#define ixDIDT_TCP_WEIGHT8_11                                                   0x72
++
++#endif /* GFX_7_2_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
+new file mode 100644
+index 0000000..9d4347d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
+@@ -0,0 +1,6274 @@
++/*
++ * GFX_7_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_7_2_ENUM_H
++#define GFX_7_2_ENUM_H
++
++typedef enum SurfaceNumber {
++	NUMBER_UNORM                                     = 0x0,
++	NUMBER_SNORM                                     = 0x1,
++	NUMBER_USCALED                                   = 0x2,
++	NUMBER_SSCALED                                   = 0x3,
++	NUMBER_UINT                                      = 0x4,
++	NUMBER_SINT                                      = 0x5,
++	NUMBER_SRGB                                      = 0x6,
++	NUMBER_FLOAT                                     = 0x7,
++} SurfaceNumber;
++typedef enum SurfaceSwap {
++	SWAP_STD                                         = 0x0,
++	SWAP_ALT                                         = 0x1,
++	SWAP_STD_REV                                     = 0x2,
++	SWAP_ALT_REV                                     = 0x3,
++} SurfaceSwap;
++typedef enum CBMode {
++	CB_DISABLE                                       = 0x0,
++	CB_NORMAL                                        = 0x1,
++	CB_ELIMINATE_FAST_CLEAR                          = 0x2,
++	CB_RESOLVE                                       = 0x3,
++	CB_DECOMPRESS                                    = 0x4,
++	CB_FMASK_DECOMPRESS                              = 0x5,
++} CBMode;
++typedef enum RoundMode {
++	ROUND_BY_HALF                                    = 0x0,
++	ROUND_TRUNCATE                                   = 0x1,
++} RoundMode;
++typedef enum SourceFormat {
++	EXPORT_4C_32BPC                                  = 0x0,
++	EXPORT_4C_16BPC                                  = 0x1,
++	EXPORT_2C_32BPC_GR                               = 0x2,
++	EXPORT_2C_32BPC_AR                               = 0x3,
++} SourceFormat;
++typedef enum BlendOp {
++	BLEND_ZERO                                       = 0x0,
++	BLEND_ONE                                        = 0x1,
++	BLEND_SRC_COLOR                                  = 0x2,
++	BLEND_ONE_MINUS_SRC_COLOR                        = 0x3,
++	BLEND_SRC_ALPHA                                  = 0x4,
++	BLEND_ONE_MINUS_SRC_ALPHA                        = 0x5,
++	BLEND_DST_ALPHA                                  = 0x6,
++	BLEND_ONE_MINUS_DST_ALPHA                        = 0x7,
++	BLEND_DST_COLOR                                  = 0x8,
++	BLEND_ONE_MINUS_DST_COLOR                        = 0x9,
++	BLEND_SRC_ALPHA_SATURATE                         = 0xa,
++	BLEND_BOTH_SRC_ALPHA                             = 0xb,
++	BLEND_BOTH_INV_SRC_ALPHA                         = 0xc,
++	BLEND_CONSTANT_COLOR                             = 0xd,
++	BLEND_ONE_MINUS_CONSTANT_COLOR                   = 0xe,
++	BLEND_SRC1_COLOR                                 = 0xf,
++	BLEND_INV_SRC1_COLOR                             = 0x10,
++	BLEND_SRC1_ALPHA                                 = 0x11,
++	BLEND_INV_SRC1_ALPHA                             = 0x12,
++	BLEND_CONSTANT_ALPHA                             = 0x13,
++	BLEND_ONE_MINUS_CONSTANT_ALPHA                   = 0x14,
++} BlendOp;
++typedef enum CombFunc {
++	COMB_DST_PLUS_SRC                                = 0x0,
++	COMB_SRC_MINUS_DST                               = 0x1,
++	COMB_MIN_DST_SRC                                 = 0x2,
++	COMB_MAX_DST_SRC                                 = 0x3,
++	COMB_DST_MINUS_SRC                               = 0x4,
++} CombFunc;
++typedef enum BlendOpt {
++	FORCE_OPT_AUTO                                   = 0x0,
++	FORCE_OPT_DISABLE                                = 0x1,
++	FORCE_OPT_ENABLE_IF_SRC_A_0                      = 0x2,
++	FORCE_OPT_ENABLE_IF_SRC_RGB_0                    = 0x3,
++	FORCE_OPT_ENABLE_IF_SRC_ARGB_0                   = 0x4,
++	FORCE_OPT_ENABLE_IF_SRC_A_1                      = 0x5,
++	FORCE_OPT_ENABLE_IF_SRC_RGB_1                    = 0x6,
++	FORCE_OPT_ENABLE_IF_SRC_ARGB_1                   = 0x7,
++} BlendOpt;
++typedef enum CmaskCode {
++	CMASK_CLR00_F0                                   = 0x0,
++	CMASK_CLR00_F1                                   = 0x1,
++	CMASK_CLR00_F2                                   = 0x2,
++	CMASK_CLR00_FX                                   = 0x3,
++	CMASK_CLR01_F0                                   = 0x4,
++	CMASK_CLR01_F1                                   = 0x5,
++	CMASK_CLR01_F2                                   = 0x6,
++	CMASK_CLR01_FX                                   = 0x7,
++	CMASK_CLR10_F0                                   = 0x8,
++	CMASK_CLR10_F1                                   = 0x9,
++	CMASK_CLR10_F2                                   = 0xa,
++	CMASK_CLR10_FX                                   = 0xb,
++	CMASK_CLR11_F0                                   = 0xc,
++	CMASK_CLR11_F1                                   = 0xd,
++	CMASK_CLR11_F2                                   = 0xe,
++	CMASK_CLR11_FX                                   = 0xf,
++} CmaskCode;
++typedef enum CBPerfSel {
++	CB_PERF_SEL_NONE                                 = 0x0,
++	CB_PERF_SEL_BUSY                                 = 0x1,
++	CB_PERF_SEL_CORE_SCLK_VLD                        = 0x2,
++	CB_PERF_SEL_REG_SCLK0_VLD                        = 0x3,
++	CB_PERF_SEL_REG_SCLK1_VLD                        = 0x4,
++	CB_PERF_SEL_DRAWN_QUAD                           = 0x5,
++	CB_PERF_SEL_DRAWN_PIXEL                          = 0x6,
++	CB_PERF_SEL_DRAWN_QUAD_FRAGMENT                  = 0x7,
++	CB_PERF_SEL_DRAWN_TILE                           = 0x8,
++	CB_PERF_SEL_DB_CB_TILE_VALID_READY               = 0x9,
++	CB_PERF_SEL_DB_CB_TILE_VALID_READYB              = 0xa,
++	CB_PERF_SEL_DB_CB_TILE_VALIDB_READY              = 0xb,
++	CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB             = 0xc,
++	CB_PERF_SEL_CM_FC_TILE_VALID_READY               = 0xd,
++	CB_PERF_SEL_CM_FC_TILE_VALID_READYB              = 0xe,
++	CB_PERF_SEL_CM_FC_TILE_VALIDB_READY              = 0xf,
++	CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB             = 0x10,
++	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY          = 0x11,
++	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB         = 0x12,
++	CB_PERF_SEL_DB_CB_LQUAD_VALID_READY              = 0x13,
++	CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB             = 0x14,
++	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY             = 0x15,
++	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB            = 0x16,
++	CB_PERF_SEL_LQUAD_NO_TILE                        = 0x17,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R          = 0x18,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR         = 0x19,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR         = 0x1a,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR       = 0x1b,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR     = 0x1c,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
++	CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT    = 0x1f,
++	CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID         = 0x20,
++	CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
++	CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK      = 0x22,
++	CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL         = 0x23,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY            = 0x24,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB           = 0x25,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY           = 0x26,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB          = 0x27,
++	CB_PERF_SEL_FOP_IN_VALID_READY                   = 0x28,
++	CB_PERF_SEL_FOP_IN_VALID_READYB                  = 0x29,
++	CB_PERF_SEL_FOP_IN_VALIDB_READY                  = 0x2a,
++	CB_PERF_SEL_FOP_IN_VALIDB_READYB                 = 0x2b,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY           = 0x2c,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB          = 0x2d,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY          = 0x2e,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB         = 0x2f,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY            = 0x30,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB           = 0x31,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY           = 0x32,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB          = 0x33,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY            = 0x34,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB           = 0x35,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY           = 0x36,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB          = 0x37,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY        = 0x38,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB       = 0x39,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY       = 0x3a,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB      = 0x3b,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY         = 0x3c,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB        = 0x3d,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY        = 0x3e,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB       = 0x3f,
++	CB_PERF_SEL_CC_BC_CS_FRAG_VALID                  = 0x40,
++	CB_PERF_SEL_CM_CACHE_HIT                         = 0x41,
++	CB_PERF_SEL_CM_CACHE_TAG_MISS                    = 0x42,
++	CB_PERF_SEL_CM_CACHE_SECTOR_MISS                 = 0x43,
++	CB_PERF_SEL_CM_CACHE_REEVICTION_STALL            = 0x44,
++	CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
++	CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
++	CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
++	CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL           = 0x48,
++	CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL          = 0x49,
++	CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL            = 0x4a,
++	CB_PERF_SEL_CM_CACHE_STALL                       = 0x4b,
++	CB_PERF_SEL_CM_CACHE_FLUSH                       = 0x4c,
++	CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED                = 0x4d,
++	CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED             = 0x4e,
++	CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED       = 0x4f,
++	CB_PERF_SEL_FC_CACHE_HIT                         = 0x50,
++	CB_PERF_SEL_FC_CACHE_TAG_MISS                    = 0x51,
++	CB_PERF_SEL_FC_CACHE_SECTOR_MISS                 = 0x52,
++	CB_PERF_SEL_FC_CACHE_REEVICTION_STALL            = 0x53,
++	CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
++	CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
++	CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
++	CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL           = 0x57,
++	CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL          = 0x58,
++	CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL            = 0x59,
++	CB_PERF_SEL_FC_CACHE_STALL                       = 0x5a,
++	CB_PERF_SEL_FC_CACHE_FLUSH                       = 0x5b,
++	CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED                = 0x5c,
++	CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED             = 0x5d,
++	CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x5e,
++	CB_PERF_SEL_CC_CACHE_HIT                         = 0x5f,
++	CB_PERF_SEL_CC_CACHE_TAG_MISS                    = 0x60,
++	CB_PERF_SEL_CC_CACHE_SECTOR_MISS                 = 0x61,
++	CB_PERF_SEL_CC_CACHE_REEVICTION_STALL            = 0x62,
++	CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
++	CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
++	CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
++	CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL           = 0x66,
++	CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL          = 0x67,
++	CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL            = 0x68,
++	CB_PERF_SEL_CC_CACHE_STALL                       = 0x69,
++	CB_PERF_SEL_CC_CACHE_FLUSH                       = 0x6a,
++	CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED                = 0x6b,
++	CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED             = 0x6c,
++	CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x6d,
++	CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION        = 0x6e,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY             = 0x6f,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB            = 0x70,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY            = 0x71,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB           = 0x72,
++	CB_PERF_SEL_CM_MC_WRITE_REQUEST                  = 0x73,
++	CB_PERF_SEL_FC_MC_WRITE_REQUEST                  = 0x74,
++	CB_PERF_SEL_CC_MC_WRITE_REQUEST                  = 0x75,
++	CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x76,
++	CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x77,
++	CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x78,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY             = 0x79,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB            = 0x7a,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY            = 0x7b,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB           = 0x7c,
++	CB_PERF_SEL_CM_MC_READ_REQUEST                   = 0x7d,
++	CB_PERF_SEL_FC_MC_READ_REQUEST                   = 0x7e,
++	CB_PERF_SEL_CC_MC_READ_REQUEST                   = 0x7f,
++	CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT        = 0x80,
++	CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT        = 0x81,
++	CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT        = 0x82,
++	CB_PERF_SEL_CM_TQ_FULL                           = 0x83,
++	CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL      = 0x84,
++	CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL              = 0x85,
++	CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL              = 0x86,
++	CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL   = 0x87,
++	CB_PERF_SEL_FOP_FMASK_RAW_STALL                  = 0x88,
++	CB_PERF_SEL_FOP_FMASK_BYPASS_STALL               = 0x89,
++	CB_PERF_SEL_CC_SF_FULL                           = 0x8a,
++	CB_PERF_SEL_CC_RB_FULL                           = 0x8b,
++	CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL     = 0x8c,
++	CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL      = 0x8d,
++	CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL             = 0x8e,
++	CB_PERF_SEL_EVENT                                = 0x8f,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH_TS                 = 0x90,
++	CB_PERF_SEL_EVENT_CONTEXT_DONE                   = 0x91,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH                    = 0x92,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT   = 0x93,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT      = 0x94,
++	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS       = 0x95,
++	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META          = 0x96,
++	CB_PERF_SEL_CC_SURFACE_SYNC                      = 0x97,
++	CB_PERF_SEL_CMASK_READ_DATA_0xC                  = 0x98,
++	CB_PERF_SEL_CMASK_READ_DATA_0xD                  = 0x99,
++	CB_PERF_SEL_CMASK_READ_DATA_0xE                  = 0x9a,
++	CB_PERF_SEL_CMASK_READ_DATA_0xF                  = 0x9b,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xC                 = 0x9c,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xD                 = 0x9d,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xE                 = 0x9e,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xF                 = 0x9f,
++	CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT              = 0xa0,
++	CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT         = 0xa1,
++	CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT      = 0xa2,
++	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE    = 0xa3,
++	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE   = 0xa4,
++	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE   = 0xa5,
++	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE   = 0xa6,
++	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE   = 0xa7,
++	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE   = 0xa8,
++	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE   = 0xa9,
++	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE   = 0xaa,
++	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE     = 0xab,
++	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE    = 0xac,
++	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE    = 0xad,
++	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE    = 0xae,
++	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE    = 0xaf,
++	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE    = 0xb0,
++	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE    = 0xb1,
++	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE    = 0xb2,
++	CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT                = 0xb3,
++	CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS               = 0xb4,
++	CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS               = 0xb5,
++	CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS               = 0xb6,
++	CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS               = 0xb7,
++	CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS               = 0xb8,
++	CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS               = 0xb9,
++	CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT              = 0xba,
++	CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS             = 0xbb,
++	CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS             = 0xbc,
++	CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS             = 0xbd,
++	CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS             = 0xbe,
++	CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS             = 0xbf,
++	CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS             = 0xc0,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_0                = 0xc1,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_1                = 0xc2,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_2                = 0xc3,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_3                = 0xc4,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_4                = 0xc5,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_5                = 0xc6,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_6                = 0xc7,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_7                = 0xc8,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0               = 0xc9,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1               = 0xca,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2               = 0xcb,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3               = 0xcc,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4               = 0xcd,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5               = 0xce,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6               = 0xcf,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7               = 0xd0,
++	CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST         = 0xd1,
++	CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS          = 0xd2,
++	CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS        = 0xd3,
++	CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd4,
++	CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd5,
++	CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED       = 0xd6,
++	CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST      = 0xd7,
++	CB_PERF_SEL_DRAWN_BUSY                           = 0xd8,
++	CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY              = 0xd9,
++	CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY               = 0xda,
++	CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY               = 0xdb,
++	CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY               = 0xdc,
++	CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xdd,
++	CB_PERF_SEL_FC_SEQUENCER_CLEAR                   = 0xde,
++	CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR    = 0xdf,
++	CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS        = 0xe0,
++	CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe1,
++} CBPerfSel;
++typedef enum CBPerfOpFilterSel {
++	CB_PERF_OP_FILTER_SEL_WRITE_ONLY                 = 0x0,
++	CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION          = 0x1,
++	CB_PERF_OP_FILTER_SEL_RESOLVE                    = 0x2,
++	CB_PERF_OP_FILTER_SEL_DECOMPRESS                 = 0x3,
++	CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS           = 0x4,
++	CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR       = 0x5,
++} CBPerfOpFilterSel;
++typedef enum CBPerfClearFilterSel {
++	CB_PERF_CLEAR_FILTER_SEL_NONCLEAR                = 0x0,
++	CB_PERF_CLEAR_FILTER_SEL_CLEAR                   = 0x1,
++} CBPerfClearFilterSel;
++typedef enum CP_RING_ID {
++	RINGID0                                          = 0x0,
++	RINGID1                                          = 0x1,
++	RINGID2                                          = 0x2,
++	RINGID3                                          = 0x3,
++} CP_RING_ID;
++typedef enum CP_PIPE_ID {
++	PIPE_ID0                                         = 0x0,
++	PIPE_ID1                                         = 0x1,
++	PIPE_ID2                                         = 0x2,
++	PIPE_ID3                                         = 0x3,
++} CP_PIPE_ID;
++typedef enum CP_ME_ID {
++	ME_ID0                                           = 0x0,
++	ME_ID1                                           = 0x1,
++	ME_ID2                                           = 0x2,
++	ME_ID3                                           = 0x3,
++} CP_ME_ID;
++typedef enum SPM_PERFMON_STATE {
++	STRM_PERFMON_STATE_DISABLE_AND_RESET             = 0x0,
++	STRM_PERFMON_STATE_START_COUNTING                = 0x1,
++	STRM_PERFMON_STATE_STOP_COUNTING                 = 0x2,
++	STRM_PERFMON_STATE_RESERVED_3                    = 0x3,
++	STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM     = 0x4,
++	STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM        = 0x5,
++} SPM_PERFMON_STATE;
++typedef enum CP_PERFMON_STATE {
++	CP_PERFMON_STATE_DISABLE_AND_RESET               = 0x0,
++	CP_PERFMON_STATE_START_COUNTING                  = 0x1,
++	CP_PERFMON_STATE_STOP_COUNTING                   = 0x2,
++	CP_PERFMON_STATE_RESERVED_3                      = 0x3,
++	CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM       = 0x4,
++	CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM          = 0x5,
++} CP_PERFMON_STATE;
++typedef enum CP_PERFMON_ENABLE_MODE {
++	CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT              = 0x0,
++	CP_PERFMON_ENABLE_MODE_RESERVED_1                = 0x1,
++	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE        = 0x2,
++	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE       = 0x3,
++} CP_PERFMON_ENABLE_MODE;
++typedef enum CPG_PERFCOUNT_SEL {
++	CPG_PERF_SEL_ALWAYS_COUNT                        = 0x0,
++	CPG_PERF_SEL_RBIU_FIFO_FULL                      = 0x1,
++	CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR             = 0x2,
++	CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL          = 0x3,
++	CPG_PERF_SEL_CP_GRBM_DWORDS_SENT                 = 0x4,
++	CPG_PERF_SEL_ME_PARSER_BUSY                      = 0x5,
++	CPG_PERF_SEL_COUNT_TYPE0_PACKETS                 = 0x6,
++	CPG_PERF_SEL_COUNT_TYPE3_PACKETS                 = 0x7,
++	CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0x8,
++	CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS              = 0x9,
++	CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS          = 0xa,
++	CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS          = 0xb,
++	CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ             = 0xc,
++	CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ            = 0xd,
++	CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX          = 0xe,
++	CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS        = 0xf,
++	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE        = 0x10,
++	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM   = 0x11,
++	CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY            = 0x12,
++	CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY            = 0x13,
++	CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY           = 0x14,
++	CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ       = 0x15,
++	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP        = 0x16,
++	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ        = 0x17,
++	CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX     = 0x18,
++	CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU          = 0x19,
++	CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS        = 0x1a,
++	CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH         = 0x1b,
++	CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER               = 0x1c,
++	CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER             = 0x1d,
++	CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS     = 0x1e,
++	CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY       = 0x1f,
++	CPG_PERF_SEL_DYNAMIC_CLK_VALID                   = 0x20,
++	CPG_PERF_SEL_REGISTER_CLK_VALID                  = 0x21,
++	CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT              = 0x22,
++	CPG_PERF_SEL_MIU_READ_REQUEST_SENT               = 0x23,
++	CPG_PERF_SEL_CE_STALL_RAM_DUMP                   = 0x24,
++	CPG_PERF_SEL_CE_STALL_RAM_WRITE                  = 0x25,
++	CPG_PERF_SEL_CE_STALL_ON_INC_FIFO                = 0x26,
++	CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO             = 0x27,
++	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU           = 0x28,
++	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ           = 0x29,
++	CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG          = 0x2a,
++	CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER              = 0x2b,
++	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x2c,
++	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS             = 0x2d,
++} CPG_PERFCOUNT_SEL;
++typedef enum CPF_PERFCOUNT_SEL {
++	CPF_PERF_SEL_ALWAYS_COUNT                        = 0x0,
++	CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE      = 0x1,
++	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE        = 0x2,
++	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS        = 0x3,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING          = 0x4,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1           = 0x5,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2           = 0x6,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE         = 0x7,
++	CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS       = 0x8,
++	CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR                 = 0x9,
++	CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR              = 0xa,
++	CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0xb,
++	CPF_PERF_SEL_GRBM_DWORDS_SENT                    = 0xc,
++	CPF_PERF_SEL_DYNAMIC_CLOCK_VALID                 = 0xd,
++	CPF_PERF_SEL_REGISTER_CLOCK_VALID                = 0xe,
++	CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND              = 0xf,
++	CPF_PERF_SEL_MIU_READ_REQUEST_SEND               = 0x10,
++} CPF_PERFCOUNT_SEL;
++typedef enum CPC_PERFCOUNT_SEL {
++	CPC_PERF_SEL_ALWAYS_COUNT                        = 0x0,
++	CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE             = 0x1,
++	CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION           = 0x2,
++	CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE             = 0x3,
++	CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE             = 0x4,
++	CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x5,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY        = 0x6,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF   = 0x7,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ         = 0x8,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ          = 0x9,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE         = 0xa,
++	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ          = 0xb,
++	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF     = 0xc,
++	CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE          = 0xd,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY        = 0xe,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF   = 0xf,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ         = 0x10,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ          = 0x11,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE         = 0x12,
++	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ          = 0x13,
++	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF     = 0x14,
++	CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE          = 0x15,
++} CPC_PERFCOUNT_SEL;
++typedef enum CP_ALPHA_TAG_RAM_SEL {
++	CPG_TAG_RAM                                      = 0x0,
++	CPC_TAG_RAM                                      = 0x1,
++	CPF_TAG_RAM                                      = 0x2,
++	RSV_TAG_RAM                                      = 0x3,
++} CP_ALPHA_TAG_RAM_SEL;
++#define SEM_ECC_ERROR                             0x0
++#define SEM_RESERVED                              0x1
++#define SEM_FAILED                                0x2
++#define SEM_PASSED                                0x3
++#define IQ_QUEUE_SLEEP                            0x0
++#define IQ_OFFLOAD_RETRY                          0x1
++#define IQ_SCH_WAVE_MSG                           0x2
++#define IQ_SEM_REARM                              0x3
++#define IQ_DEQUEUE_RETRY                          0x4
++#define IQ_INTR_TYPE_PQ                           0x0
++#define IQ_INTR_TYPE_IB                           0x1
++#define IQ_INTR_TYPE_MQD                          0x2
++#define VMID_SZ                                   0x4
++#define CONFIG_SPACE_START                        0x2000
++#define CONFIG_SPACE_END                          0x9fff
++#define CONFIG_SPACE1_START                       0x2000
++#define CONFIG_SPACE1_END                         0x2bff
++#define CONFIG_SPACE2_START                       0x3000
++#define CONFIG_SPACE2_END                         0x9fff
++#define UCONFIG_SPACE_START                       0xc000
++#define UCONFIG_SPACE_END                         0xffff
++#define PERSISTENT_SPACE_START                    0x2c00
++#define PERSISTENT_SPACE_END                      0x2fff
++#define CONTEXT_SPACE_START                       0xa000
++#define CONTEXT_SPACE_END                         0xbfff
++typedef enum ForceControl {
++	FORCE_OFF                                        = 0x0,
++	FORCE_ENABLE                                     = 0x1,
++	FORCE_DISABLE                                    = 0x2,
++	FORCE_RESERVED                                   = 0x3,
++} ForceControl;
++typedef enum ZSamplePosition {
++	Z_SAMPLE_CENTER                                  = 0x0,
++	Z_SAMPLE_CENTROID                                = 0x1,
++} ZSamplePosition;
++typedef enum ZOrder {
++	LATE_Z                                           = 0x0,
++	EARLY_Z_THEN_LATE_Z                              = 0x1,
++	RE_Z                                             = 0x2,
++	EARLY_Z_THEN_RE_Z                                = 0x3,
++} ZOrder;
++typedef enum ZpassControl {
++	ZPASS_DISABLE                                    = 0x0,
++	ZPASS_SAMPLES                                    = 0x1,
++	ZPASS_PIXELS                                     = 0x2,
++} ZpassControl;
++typedef enum ZModeForce {
++	NO_FORCE                                         = 0x0,
++	FORCE_EARLY_Z                                    = 0x1,
++	FORCE_LATE_Z                                     = 0x2,
++	FORCE_RE_Z                                       = 0x3,
++} ZModeForce;
++typedef enum ZLimitSumm {
++	FORCE_SUMM_OFF                                   = 0x0,
++	FORCE_SUMM_MINZ                                  = 0x1,
++	FORCE_SUMM_MAXZ                                  = 0x2,
++	FORCE_SUMM_BOTH                                  = 0x3,
++} ZLimitSumm;
++typedef enum CompareFrag {
++	FRAG_NEVER                                       = 0x0,
++	FRAG_LESS                                        = 0x1,
++	FRAG_EQUAL                                       = 0x2,
++	FRAG_LEQUAL                                      = 0x3,
++	FRAG_GREATER                                     = 0x4,
++	FRAG_NOTEQUAL                                    = 0x5,
++	FRAG_GEQUAL                                      = 0x6,
++	FRAG_ALWAYS                                      = 0x7,
++} CompareFrag;
++typedef enum StencilOp {
++	STENCIL_KEEP                                     = 0x0,
++	STENCIL_ZERO                                     = 0x1,
++	STENCIL_ONES                                     = 0x2,
++	STENCIL_REPLACE_TEST                             = 0x3,
++	STENCIL_REPLACE_OP                               = 0x4,
++	STENCIL_ADD_CLAMP                                = 0x5,
++	STENCIL_SUB_CLAMP                                = 0x6,
++	STENCIL_INVERT                                   = 0x7,
++	STENCIL_ADD_WRAP                                 = 0x8,
++	STENCIL_SUB_WRAP                                 = 0x9,
++	STENCIL_AND                                      = 0xa,
++	STENCIL_OR                                       = 0xb,
++	STENCIL_XOR                                      = 0xc,
++	STENCIL_NAND                                     = 0xd,
++	STENCIL_NOR                                      = 0xe,
++	STENCIL_XNOR                                     = 0xf,
++} StencilOp;
++typedef enum ConservativeZExport {
++	EXPORT_ANY_Z                                     = 0x0,
++	EXPORT_LESS_THAN_Z                               = 0x1,
++	EXPORT_GREATER_THAN_Z                            = 0x2,
++	EXPORT_RESERVED                                  = 0x3,
++} ConservativeZExport;
++typedef enum DbPSLControl {
++	PSLC_AUTO                                        = 0x0,
++	PSLC_ON_HANG_ONLY                                = 0x1,
++	PSLC_ASAP                                        = 0x2,
++	PSLC_COUNTDOWN                                   = 0x3,
++} DbPSLControl;
++typedef enum PerfCounter_Vals {
++	DB_PERF_SEL_SC_DB_tile_sends                     = 0x0,
++	DB_PERF_SEL_SC_DB_tile_busy                      = 0x1,
++	DB_PERF_SEL_SC_DB_tile_stalls                    = 0x2,
++	DB_PERF_SEL_SC_DB_tile_events                    = 0x3,
++	DB_PERF_SEL_SC_DB_tile_tiles                     = 0x4,
++	DB_PERF_SEL_SC_DB_tile_covered                   = 0x5,
++	DB_PERF_SEL_hiz_tc_read_starved                  = 0x6,
++	DB_PERF_SEL_hiz_tc_write_stall                   = 0x7,
++	DB_PERF_SEL_hiz_qtiles_culled                    = 0x8,
++	DB_PERF_SEL_his_qtiles_culled                    = 0x9,
++	DB_PERF_SEL_DB_SC_tile_sends                     = 0xa,
++	DB_PERF_SEL_DB_SC_tile_busy                      = 0xb,
++	DB_PERF_SEL_DB_SC_tile_stalls                    = 0xc,
++	DB_PERF_SEL_DB_SC_tile_df_stalls                 = 0xd,
++	DB_PERF_SEL_DB_SC_tile_tiles                     = 0xe,
++	DB_PERF_SEL_DB_SC_tile_culled                    = 0xf,
++	DB_PERF_SEL_DB_SC_tile_hier_kill                 = 0x10,
++	DB_PERF_SEL_DB_SC_tile_fast_ops                  = 0x11,
++	DB_PERF_SEL_DB_SC_tile_no_ops                    = 0x12,
++	DB_PERF_SEL_DB_SC_tile_tile_rate                 = 0x13,
++	DB_PERF_SEL_DB_SC_tile_ssaa_kill                 = 0x14,
++	DB_PERF_SEL_DB_SC_tile_fast_z_ops                = 0x15,
++	DB_PERF_SEL_DB_SC_tile_fast_stencil_ops          = 0x16,
++	DB_PERF_SEL_SC_DB_quad_sends                     = 0x17,
++	DB_PERF_SEL_SC_DB_quad_busy                      = 0x18,
++	DB_PERF_SEL_SC_DB_quad_squads                    = 0x19,
++	DB_PERF_SEL_SC_DB_quad_tiles                     = 0x1a,
++	DB_PERF_SEL_SC_DB_quad_pixels                    = 0x1b,
++	DB_PERF_SEL_SC_DB_quad_killed_tiles              = 0x1c,
++	DB_PERF_SEL_DB_SC_quad_sends                     = 0x1d,
++	DB_PERF_SEL_DB_SC_quad_busy                      = 0x1e,
++	DB_PERF_SEL_DB_SC_quad_stalls                    = 0x1f,
++	DB_PERF_SEL_DB_SC_quad_tiles                     = 0x20,
++	DB_PERF_SEL_DB_SC_quad_lit_quad                  = 0x21,
++	DB_PERF_SEL_DB_CB_tile_sends                     = 0x22,
++	DB_PERF_SEL_DB_CB_tile_busy                      = 0x23,
++	DB_PERF_SEL_DB_CB_tile_stalls                    = 0x24,
++	DB_PERF_SEL_SX_DB_quad_sends                     = 0x25,
++	DB_PERF_SEL_SX_DB_quad_busy                      = 0x26,
++	DB_PERF_SEL_SX_DB_quad_stalls                    = 0x27,
++	DB_PERF_SEL_SX_DB_quad_quads                     = 0x28,
++	DB_PERF_SEL_SX_DB_quad_pixels                    = 0x29,
++	DB_PERF_SEL_SX_DB_quad_exports                   = 0x2a,
++	DB_PERF_SEL_SH_quads_outstanding_sum             = 0x2b,
++	DB_PERF_SEL_DB_CB_lquad_sends                    = 0x2c,
++	DB_PERF_SEL_DB_CB_lquad_busy                     = 0x2d,
++	DB_PERF_SEL_DB_CB_lquad_stalls                   = 0x2e,
++	DB_PERF_SEL_DB_CB_lquad_quads                    = 0x2f,
++	DB_PERF_SEL_tile_rd_sends                        = 0x30,
++	DB_PERF_SEL_mi_tile_rd_outstanding_sum           = 0x31,
++	DB_PERF_SEL_quad_rd_sends                        = 0x32,
++	DB_PERF_SEL_quad_rd_busy                         = 0x33,
++	DB_PERF_SEL_quad_rd_mi_stall                     = 0x34,
++	DB_PERF_SEL_quad_rd_rw_collision                 = 0x35,
++	DB_PERF_SEL_quad_rd_tag_stall                    = 0x36,
++	DB_PERF_SEL_quad_rd_32byte_reqs                  = 0x37,
++	DB_PERF_SEL_quad_rd_panic                        = 0x38,
++	DB_PERF_SEL_mi_quad_rd_outstanding_sum           = 0x39,
++	DB_PERF_SEL_quad_rdret_sends                     = 0x3a,
++	DB_PERF_SEL_quad_rdret_busy                      = 0x3b,
++	DB_PERF_SEL_tile_wr_sends                        = 0x3c,
++	DB_PERF_SEL_tile_wr_acks                         = 0x3d,
++	DB_PERF_SEL_mi_tile_wr_outstanding_sum           = 0x3e,
++	DB_PERF_SEL_quad_wr_sends                        = 0x3f,
++	DB_PERF_SEL_quad_wr_busy                         = 0x40,
++	DB_PERF_SEL_quad_wr_mi_stall                     = 0x41,
++	DB_PERF_SEL_quad_wr_coherency_stall              = 0x42,
++	DB_PERF_SEL_quad_wr_acks                         = 0x43,
++	DB_PERF_SEL_mi_quad_wr_outstanding_sum           = 0x44,
++	DB_PERF_SEL_Tile_Cache_misses                    = 0x45,
++	DB_PERF_SEL_Tile_Cache_hits                      = 0x46,
++	DB_PERF_SEL_Tile_Cache_flushes                   = 0x47,
++	DB_PERF_SEL_Tile_Cache_surface_stall             = 0x48,
++	DB_PERF_SEL_Tile_Cache_starves                   = 0x49,
++	DB_PERF_SEL_Tile_Cache_mem_return_starve         = 0x4a,
++	DB_PERF_SEL_tcp_dispatcher_reads                 = 0x4b,
++	DB_PERF_SEL_tcp_prefetcher_reads                 = 0x4c,
++	DB_PERF_SEL_tcp_preloader_reads                  = 0x4d,
++	DB_PERF_SEL_tcp_dispatcher_flushes               = 0x4e,
++	DB_PERF_SEL_tcp_prefetcher_flushes               = 0x4f,
++	DB_PERF_SEL_tcp_preloader_flushes                = 0x50,
++	DB_PERF_SEL_Depth_Tile_Cache_sends               = 0x51,
++	DB_PERF_SEL_Depth_Tile_Cache_busy                = 0x52,
++	DB_PERF_SEL_Depth_Tile_Cache_starves             = 0x53,
++	DB_PERF_SEL_Depth_Tile_Cache_dtile_locked        = 0x54,
++	DB_PERF_SEL_Depth_Tile_Cache_alloc_stall         = 0x55,
++	DB_PERF_SEL_Depth_Tile_Cache_misses              = 0x56,
++	DB_PERF_SEL_Depth_Tile_Cache_hits                = 0x57,
++	DB_PERF_SEL_Depth_Tile_Cache_flushes             = 0x58,
++	DB_PERF_SEL_Depth_Tile_Cache_noop_tile           = 0x59,
++	DB_PERF_SEL_Depth_Tile_Cache_detailed_noop       = 0x5a,
++	DB_PERF_SEL_Depth_Tile_Cache_event               = 0x5b,
++	DB_PERF_SEL_Depth_Tile_Cache_tile_frees          = 0x5c,
++	DB_PERF_SEL_Depth_Tile_Cache_data_frees          = 0x5d,
++	DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve   = 0x5e,
++	DB_PERF_SEL_Stencil_Cache_misses                 = 0x5f,
++	DB_PERF_SEL_Stencil_Cache_hits                   = 0x60,
++	DB_PERF_SEL_Stencil_Cache_flushes                = 0x61,
++	DB_PERF_SEL_Stencil_Cache_starves                = 0x62,
++	DB_PERF_SEL_Stencil_Cache_frees                  = 0x63,
++	DB_PERF_SEL_Z_Cache_separate_Z_misses            = 0x64,
++	DB_PERF_SEL_Z_Cache_separate_Z_hits              = 0x65,
++	DB_PERF_SEL_Z_Cache_separate_Z_flushes           = 0x66,
++	DB_PERF_SEL_Z_Cache_separate_Z_starves           = 0x67,
++	DB_PERF_SEL_Z_Cache_pmask_misses                 = 0x68,
++	DB_PERF_SEL_Z_Cache_pmask_hits                   = 0x69,
++	DB_PERF_SEL_Z_Cache_pmask_flushes                = 0x6a,
++	DB_PERF_SEL_Z_Cache_pmask_starves                = 0x6b,
++	DB_PERF_SEL_Z_Cache_frees                        = 0x6c,
++	DB_PERF_SEL_Plane_Cache_misses                   = 0x6d,
++	DB_PERF_SEL_Plane_Cache_hits                     = 0x6e,
++	DB_PERF_SEL_Plane_Cache_flushes                  = 0x6f,
++	DB_PERF_SEL_Plane_Cache_starves                  = 0x70,
++	DB_PERF_SEL_Plane_Cache_frees                    = 0x71,
++	DB_PERF_SEL_flush_expanded_stencil               = 0x72,
++	DB_PERF_SEL_flush_compressed_stencil             = 0x73,
++	DB_PERF_SEL_flush_single_stencil                 = 0x74,
++	DB_PERF_SEL_planes_flushed                       = 0x75,
++	DB_PERF_SEL_flush_1plane                         = 0x76,
++	DB_PERF_SEL_flush_2plane                         = 0x77,
++	DB_PERF_SEL_flush_3plane                         = 0x78,
++	DB_PERF_SEL_flush_4plane                         = 0x79,
++	DB_PERF_SEL_flush_5plane                         = 0x7a,
++	DB_PERF_SEL_flush_6plane                         = 0x7b,
++	DB_PERF_SEL_flush_7plane                         = 0x7c,
++	DB_PERF_SEL_flush_8plane                         = 0x7d,
++	DB_PERF_SEL_flush_9plane                         = 0x7e,
++	DB_PERF_SEL_flush_10plane                        = 0x7f,
++	DB_PERF_SEL_flush_11plane                        = 0x80,
++	DB_PERF_SEL_flush_12plane                        = 0x81,
++	DB_PERF_SEL_flush_13plane                        = 0x82,
++	DB_PERF_SEL_flush_14plane                        = 0x83,
++	DB_PERF_SEL_flush_15plane                        = 0x84,
++	DB_PERF_SEL_flush_16plane                        = 0x85,
++	DB_PERF_SEL_flush_expanded_z                     = 0x86,
++	DB_PERF_SEL_earlyZ_waiting_for_postZ_done        = 0x87,
++	DB_PERF_SEL_reZ_waiting_for_postZ_done           = 0x88,
++	DB_PERF_SEL_dk_tile_sends                        = 0x89,
++	DB_PERF_SEL_dk_tile_busy                         = 0x8a,
++	DB_PERF_SEL_dk_tile_quad_starves                 = 0x8b,
++	DB_PERF_SEL_dk_tile_stalls                       = 0x8c,
++	DB_PERF_SEL_dk_squad_sends                       = 0x8d,
++	DB_PERF_SEL_dk_squad_busy                        = 0x8e,
++	DB_PERF_SEL_dk_squad_stalls                      = 0x8f,
++	DB_PERF_SEL_Op_Pipe_Busy                         = 0x90,
++	DB_PERF_SEL_Op_Pipe_MC_Read_stall                = 0x91,
++	DB_PERF_SEL_qc_busy                              = 0x92,
++	DB_PERF_SEL_qc_xfc                               = 0x93,
++	DB_PERF_SEL_qc_conflicts                         = 0x94,
++	DB_PERF_SEL_qc_full_stall                        = 0x95,
++	DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ         = 0x96,
++	DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ         = 0x97,
++	DB_PERF_SEL_tsc_insert_summarize_stall           = 0x98,
++	DB_PERF_SEL_tl_busy                              = 0x99,
++	DB_PERF_SEL_tl_dtc_read_starved                  = 0x9a,
++	DB_PERF_SEL_tl_z_fetch_stall                     = 0x9b,
++	DB_PERF_SEL_tl_stencil_stall                     = 0x9c,
++	DB_PERF_SEL_tl_z_decompress_stall                = 0x9d,
++	DB_PERF_SEL_tl_stencil_locked_stall              = 0x9e,
++	DB_PERF_SEL_tl_events                            = 0x9f,
++	DB_PERF_SEL_tl_summarize_squads                  = 0xa0,
++	DB_PERF_SEL_tl_flush_expand_squads               = 0xa1,
++	DB_PERF_SEL_tl_expand_squads                     = 0xa2,
++	DB_PERF_SEL_tl_preZ_squads                       = 0xa3,
++	DB_PERF_SEL_tl_postZ_squads                      = 0xa4,
++	DB_PERF_SEL_tl_preZ_noop_squads                  = 0xa5,
++	DB_PERF_SEL_tl_postZ_noop_squads                 = 0xa6,
++	DB_PERF_SEL_tl_tile_ops                          = 0xa7,
++	DB_PERF_SEL_tl_in_xfc                            = 0xa8,
++	DB_PERF_SEL_tl_in_single_stencil_expand_stall    = 0xa9,
++	DB_PERF_SEL_tl_in_fast_z_stall                   = 0xaa,
++	DB_PERF_SEL_tl_out_xfc                           = 0xab,
++	DB_PERF_SEL_tl_out_squads                        = 0xac,
++	DB_PERF_SEL_zf_plane_multicycle                  = 0xad,
++	DB_PERF_SEL_PostZ_Samples_passing_Z              = 0xae,
++	DB_PERF_SEL_PostZ_Samples_failing_Z              = 0xaf,
++	DB_PERF_SEL_PostZ_Samples_failing_S              = 0xb0,
++	DB_PERF_SEL_PreZ_Samples_passing_Z               = 0xb1,
++	DB_PERF_SEL_PreZ_Samples_failing_Z               = 0xb2,
++	DB_PERF_SEL_PreZ_Samples_failing_S               = 0xb3,
++	DB_PERF_SEL_ts_tc_update_stall                   = 0xb4,
++	DB_PERF_SEL_sc_kick_start                        = 0xb5,
++	DB_PERF_SEL_sc_kick_end                          = 0xb6,
++	DB_PERF_SEL_clock_reg_active                     = 0xb7,
++	DB_PERF_SEL_clock_main_active                    = 0xb8,
++	DB_PERF_SEL_clock_mem_export_active              = 0xb9,
++	DB_PERF_SEL_esr_ps_out_busy                      = 0xba,
++	DB_PERF_SEL_esr_ps_lqf_busy                      = 0xbb,
++	DB_PERF_SEL_esr_ps_lqf_stall                     = 0xbc,
++	DB_PERF_SEL_etr_out_send                         = 0xbd,
++	DB_PERF_SEL_etr_out_busy                         = 0xbe,
++	DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0xbf,
++	DB_PERF_SEL_etr_out_cb_tile_stall                = 0xc0,
++	DB_PERF_SEL_etr_out_esr_stall                    = 0xc1,
++	DB_PERF_SEL_esr_ps_sqq_busy                      = 0xc2,
++	DB_PERF_SEL_esr_ps_sqq_stall                     = 0xc3,
++	DB_PERF_SEL_esr_eot_fwd_busy                     = 0xc4,
++	DB_PERF_SEL_esr_eot_fwd_holding_squad            = 0xc5,
++	DB_PERF_SEL_esr_eot_fwd_forward                  = 0xc6,
++	DB_PERF_SEL_esr_sqq_zi_busy                      = 0xc7,
++	DB_PERF_SEL_esr_sqq_zi_stall                     = 0xc8,
++	DB_PERF_SEL_postzl_sq_pt_busy                    = 0xc9,
++	DB_PERF_SEL_postzl_sq_pt_stall                   = 0xca,
++	DB_PERF_SEL_postzl_se_busy                       = 0xcb,
++	DB_PERF_SEL_postzl_se_stall                      = 0xcc,
++	DB_PERF_SEL_postzl_partial_launch                = 0xcd,
++	DB_PERF_SEL_postzl_full_launch                   = 0xce,
++	DB_PERF_SEL_postzl_partial_waiting               = 0xcf,
++	DB_PERF_SEL_postzl_tile_mem_stall                = 0xd0,
++	DB_PERF_SEL_postzl_tile_init_stall               = 0xd1,
++	DB_PEFF_SEL_prezl_tile_mem_stall                 = 0xd2,
++	DB_PERF_SEL_prezl_tile_init_stall                = 0xd3,
++	DB_PERF_SEL_dtt_sm_clash_stall                   = 0xd4,
++	DB_PERF_SEL_dtt_sm_slot_stall                    = 0xd5,
++	DB_PERF_SEL_dtt_sm_miss_stall                    = 0xd6,
++	DB_PERF_SEL_mi_rdreq_busy                        = 0xd7,
++	DB_PERF_SEL_mi_rdreq_stall                       = 0xd8,
++	DB_PERF_SEL_mi_wrreq_busy                        = 0xd9,
++	DB_PERF_SEL_mi_wrreq_stall                       = 0xda,
++	DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop     = 0xdb,
++	DB_PERF_SEL_dkg_tile_rate_tile                   = 0xdc,
++	DB_PERF_SEL_prezl_src_in_sends                   = 0xdd,
++	DB_PERF_SEL_prezl_src_in_stall                   = 0xde,
++	DB_PERF_SEL_prezl_src_in_squads                  = 0xdf,
++	DB_PERF_SEL_prezl_src_in_squads_unrolled         = 0xe0,
++	DB_PERF_SEL_prezl_src_in_tile_rate               = 0xe1,
++	DB_PERF_SEL_prezl_src_in_tile_rate_unrolled      = 0xe2,
++	DB_PERF_SEL_prezl_src_out_stall                  = 0xe3,
++	DB_PERF_SEL_postzl_src_in_sends                  = 0xe4,
++	DB_PERF_SEL_postzl_src_in_stall                  = 0xe5,
++	DB_PERF_SEL_postzl_src_in_squads                 = 0xe6,
++	DB_PERF_SEL_postzl_src_in_squads_unrolled        = 0xe7,
++	DB_PERF_SEL_postzl_src_in_tile_rate              = 0xe8,
++	DB_PERF_SEL_postzl_src_in_tile_rate_unrolled     = 0xe9,
++	DB_PERF_SEL_postzl_src_out_stall                 = 0xea,
++	DB_PERF_SEL_esr_ps_src_in_sends                  = 0xeb,
++	DB_PERF_SEL_esr_ps_src_in_stall                  = 0xec,
++	DB_PERF_SEL_esr_ps_src_in_squads                 = 0xed,
++	DB_PERF_SEL_esr_ps_src_in_squads_unrolled        = 0xee,
++	DB_PERF_SEL_esr_ps_src_in_tile_rate              = 0xef,
++	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled     = 0xf0,
++	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
++	DB_PERF_SEL_esr_ps_src_out_stall                 = 0xf2,
++	DB_PERF_SEL_depth_bounds_qtiles_culled           = 0xf3,
++	DB_PERF_SEL_PreZ_Samples_failing_DB              = 0xf4,
++	DB_PERF_SEL_PostZ_Samples_failing_DB             = 0xf5,
++	DB_PERF_SEL_flush_compressed                     = 0xf6,
++	DB_PERF_SEL_flush_plane_le4                      = 0xf7,
++	DB_PERF_SEL_tiles_z_fully_summarized             = 0xf8,
++	DB_PERF_SEL_tiles_stencil_fully_summarized       = 0xf9,
++	DB_PERF_SEL_tiles_z_clear_on_expclear            = 0xfa,
++	DB_PERF_SEL_tiles_s_clear_on_expclear            = 0xfb,
++	DB_PERF_SEL_tiles_decomp_on_expclear             = 0xfc,
++	DB_PERF_SEL_tiles_compressed_to_decompressed     = 0xfd,
++	DB_PERF_SEL_Op_Pipe_Prez_Busy                    = 0xfe,
++	DB_PERF_SEL_Op_Pipe_Postz_Busy                   = 0xff,
++	DB_PERF_SEL_di_dt_stall                          = 0x100,
++} PerfCounter_Vals;
++typedef enum RingCounterControl {
++	COUNTER_RING_SPLIT                               = 0x0,
++	COUNTER_RING_0                                   = 0x1,
++	COUNTER_RING_1                                   = 0x2,
++} RingCounterControl;
++typedef enum PixelPipeCounterId {
++	PIXEL_PIPE_OCCLUSION_COUNT_0                     = 0x0,
++	PIXEL_PIPE_OCCLUSION_COUNT_1                     = 0x1,
++	PIXEL_PIPE_OCCLUSION_COUNT_2                     = 0x2,
++	PIXEL_PIPE_OCCLUSION_COUNT_3                     = 0x3,
++	PIXEL_PIPE_SCREEN_MIN_EXTENTS_0                  = 0x4,
++	PIXEL_PIPE_SCREEN_MAX_EXTENTS_0                  = 0x5,
++	PIXEL_PIPE_SCREEN_MIN_EXTENTS_1                  = 0x6,
++	PIXEL_PIPE_SCREEN_MAX_EXTENTS_1                  = 0x7,
++} PixelPipeCounterId;
++typedef enum PixelPipeStride {
++	PIXEL_PIPE_STRIDE_32_BITS                        = 0x0,
++	PIXEL_PIPE_STRIDE_64_BITS                        = 0x1,
++	PIXEL_PIPE_STRIDE_128_BITS                       = 0x2,
++	PIXEL_PIPE_STRIDE_256_BITS                       = 0x3,
++} PixelPipeStride;
++typedef enum GB_EDC_DED_MODE {
++	GB_EDC_DED_MODE_LOG                              = 0x0,
++	GB_EDC_DED_MODE_HALT                             = 0x1,
++	GB_EDC_DED_MODE_INT_HALT                         = 0x2,
++} GB_EDC_DED_MODE;
++#define GB_TILING_CONFIG_TABLE_SIZE               0x20
++#define GB_TILING_CONFIG_MACROTABLE_SIZE          0x10
++typedef enum GRBM_PERF_SEL {
++	GRBM_PERF_SEL_COUNT                              = 0x0,
++	GRBM_PERF_SEL_USER_DEFINED                       = 0x1,
++	GRBM_PERF_SEL_GUI_ACTIVE                         = 0x2,
++	GRBM_PERF_SEL_CP_BUSY                            = 0x3,
++	GRBM_PERF_SEL_CP_COHER_BUSY                      = 0x4,
++	GRBM_PERF_SEL_CP_DMA_BUSY                        = 0x5,
++	GRBM_PERF_SEL_CB_BUSY                            = 0x6,
++	GRBM_PERF_SEL_DB_BUSY                            = 0x7,
++	GRBM_PERF_SEL_PA_BUSY                            = 0x8,
++	GRBM_PERF_SEL_SC_BUSY                            = 0x9,
++	GRBM_PERF_SEL_RESERVED_6                         = 0xa,
++	GRBM_PERF_SEL_SPI_BUSY                           = 0xb,
++	GRBM_PERF_SEL_SX_BUSY                            = 0xc,
++	GRBM_PERF_SEL_TA_BUSY                            = 0xd,
++	GRBM_PERF_SEL_CB_CLEAN                           = 0xe,
++	GRBM_PERF_SEL_DB_CLEAN                           = 0xf,
++	GRBM_PERF_SEL_RESERVED_5                         = 0x10,
++	GRBM_PERF_SEL_VGT_BUSY                           = 0x11,
++	GRBM_PERF_SEL_RESERVED_4                         = 0x12,
++	GRBM_PERF_SEL_RESERVED_3                         = 0x13,
++	GRBM_PERF_SEL_RESERVED_2                         = 0x14,
++	GRBM_PERF_SEL_RESERVED_1                         = 0x15,
++	GRBM_PERF_SEL_RESERVED_0                         = 0x16,
++	GRBM_PERF_SEL_IA_BUSY                            = 0x17,
++	GRBM_PERF_SEL_IA_NO_DMA_BUSY                     = 0x18,
++	GRBM_PERF_SEL_GDS_BUSY                           = 0x19,
++	GRBM_PERF_SEL_BCI_BUSY                           = 0x1a,
++	GRBM_PERF_SEL_RLC_BUSY                           = 0x1b,
++	GRBM_PERF_SEL_TC_BUSY                            = 0x1c,
++	GRBM_PERF_SEL_CPG_BUSY                           = 0x1d,
++	GRBM_PERF_SEL_CPC_BUSY                           = 0x1e,
++	GRBM_PERF_SEL_CPF_BUSY                           = 0x1f,
++	GRBM_PERF_SEL_WD_BUSY                            = 0x20,
++	GRBM_PERF_SEL_WD_NO_DMA_BUSY                     = 0x21,
++} GRBM_PERF_SEL;
++typedef enum GRBM_SE0_PERF_SEL {
++	GRBM_SE0_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE0_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE0_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE0_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE0_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE0_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE0_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE0_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE0_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE0_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE0_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE0_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE0_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE0_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE0_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE0_PERF_SEL;
++typedef enum GRBM_SE1_PERF_SEL {
++	GRBM_SE1_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE1_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE1_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE1_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE1_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE1_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE1_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE1_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE1_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE1_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE1_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE1_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE1_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE1_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE1_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE1_PERF_SEL;
++typedef enum GRBM_SE2_PERF_SEL {
++	GRBM_SE2_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE2_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE2_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE2_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE2_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE2_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE2_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE2_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE2_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE2_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE2_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE2_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE2_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE2_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE2_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE2_PERF_SEL;
++typedef enum GRBM_SE3_PERF_SEL {
++	GRBM_SE3_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE3_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE3_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE3_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE3_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE3_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE3_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE3_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE3_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE3_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE3_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE3_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE3_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE3_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE3_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE3_PERF_SEL;
++typedef enum SU_PERFCNT_SEL {
++	PERF_PAPC_PASX_REQ                               = 0x0,
++	PERF_PAPC_PASX_DISABLE_PIPE                      = 0x1,
++	PERF_PAPC_PASX_FIRST_VECTOR                      = 0x2,
++	PERF_PAPC_PASX_SECOND_VECTOR                     = 0x3,
++	PERF_PAPC_PASX_FIRST_DEAD                        = 0x4,
++	PERF_PAPC_PASX_SECOND_DEAD                       = 0x5,
++	PERF_PAPC_PASX_VTX_KILL_DISCARD                  = 0x6,
++	PERF_PAPC_PASX_VTX_NAN_DISCARD                   = 0x7,
++	PERF_PAPC_PA_INPUT_PRIM                          = 0x8,
++	PERF_PAPC_PA_INPUT_NULL_PRIM                     = 0x9,
++	PERF_PAPC_PA_INPUT_EVENT_FLAG                    = 0xa,
++	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT               = 0xb,
++	PERF_PAPC_PA_INPUT_END_OF_PACKET                 = 0xc,
++	PERF_PAPC_PA_INPUT_EXTENDED_EVENT                = 0xd,
++	PERF_PAPC_CLPR_CULL_PRIM                         = 0xe,
++	PERF_PAPC_CLPR_VVUCP_CULL_PRIM                   = 0xf,
++	PERF_PAPC_CLPR_VV_CULL_PRIM                      = 0x10,
++	PERF_PAPC_CLPR_UCP_CULL_PRIM                     = 0x11,
++	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM                = 0x12,
++	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM                 = 0x13,
++	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM                 = 0x14,
++	PERF_PAPC_CLPR_VVUCP_CLIP_PRIM                   = 0x15,
++	PERF_PAPC_CLPR_VV_CLIP_PRIM                      = 0x16,
++	PERF_PAPC_CLPR_UCP_CLIP_PRIM                     = 0x17,
++	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE              = 0x18,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1                  = 0x19,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2                  = 0x1a,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3                  = 0x1b,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4                  = 0x1c,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8                = 0x1d,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12               = 0x1e,
++	PERF_PAPC_CLPR_CLIP_PLANE_NEAR                   = 0x1f,
++	PERF_PAPC_CLPR_CLIP_PLANE_FAR                    = 0x20,
++	PERF_PAPC_CLPR_CLIP_PLANE_LEFT                   = 0x21,
++	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT                  = 0x22,
++	PERF_PAPC_CLPR_CLIP_PLANE_TOP                    = 0x23,
++	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM                 = 0x24,
++	PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM                = 0x25,
++	PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM             = 0x26,
++	PERF_PAPC_CLSM_NULL_PRIM                         = 0x27,
++	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM              = 0x28,
++	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM                 = 0x29,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_1                    = 0x2a,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_2                    = 0x2b,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_3                    = 0x2c,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_4                    = 0x2d,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8                  = 0x2e,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13                 = 0x2f,
++	PERF_PAPC_CLIPGA_VTE_KILL_PRIM                   = 0x30,
++	PERF_PAPC_SU_INPUT_PRIM                          = 0x31,
++	PERF_PAPC_SU_INPUT_CLIP_PRIM                     = 0x32,
++	PERF_PAPC_SU_INPUT_NULL_PRIM                     = 0x33,
++	PERF_PAPC_SU_INPUT_PRIM_DUAL                     = 0x34,
++	PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL                = 0x35,
++	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM                 = 0x36,
++	PERF_PAPC_SU_BACK_FACE_CULL_PRIM                 = 0x37,
++	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM                = 0x38,
++	PERF_PAPC_SU_POLYMODE_FACE_CULL                  = 0x39,
++	PERF_PAPC_SU_POLYMODE_BACK_CULL                  = 0x3a,
++	PERF_PAPC_SU_POLYMODE_FRONT_CULL                 = 0x3b,
++	PERF_PAPC_SU_POLYMODE_INVALID_FILL               = 0x3c,
++	PERF_PAPC_SU_OUTPUT_PRIM                         = 0x3d,
++	PERF_PAPC_SU_OUTPUT_CLIP_PRIM                    = 0x3e,
++	PERF_PAPC_SU_OUTPUT_NULL_PRIM                    = 0x3f,
++	PERF_PAPC_SU_OUTPUT_EVENT_FLAG                   = 0x40,
++	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT              = 0x41,
++	PERF_PAPC_SU_OUTPUT_END_OF_PACKET                = 0x42,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE                = 0x43,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK                = 0x44,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT               = 0x45,
++	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE              = 0x46,
++	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK              = 0x47,
++	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT             = 0x48,
++	PERF_PAPC_SU_OUTPUT_PRIM_DUAL                    = 0x49,
++	PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL               = 0x4a,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL                = 0x4b,
++	PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL           = 0x4c,
++	PERF_PAPC_PASX_REQ_IDLE                          = 0x4d,
++	PERF_PAPC_PASX_REQ_BUSY                          = 0x4e,
++	PERF_PAPC_PASX_REQ_STALLED                       = 0x4f,
++	PERF_PAPC_PASX_REC_IDLE                          = 0x50,
++	PERF_PAPC_PASX_REC_BUSY                          = 0x51,
++	PERF_PAPC_PASX_REC_STARVED_SX                    = 0x52,
++	PERF_PAPC_PASX_REC_STALLED                       = 0x53,
++	PERF_PAPC_PASX_REC_STALLED_POS_MEM               = 0x54,
++	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN              = 0x55,
++	PERF_PAPC_CCGSM_IDLE                             = 0x56,
++	PERF_PAPC_CCGSM_BUSY                             = 0x57,
++	PERF_PAPC_CCGSM_STALLED                          = 0x58,
++	PERF_PAPC_CLPRIM_IDLE                            = 0x59,
++	PERF_PAPC_CLPRIM_BUSY                            = 0x5a,
++	PERF_PAPC_CLPRIM_STALLED                         = 0x5b,
++	PERF_PAPC_CLPRIM_STARVED_CCGSM                   = 0x5c,
++	PERF_PAPC_CLIPSM_IDLE                            = 0x5d,
++	PERF_PAPC_CLIPSM_BUSY                            = 0x5e,
++	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH             = 0x5f,
++	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ               = 0x60,
++	PERF_PAPC_CLIPSM_WAIT_CLIPGA                     = 0x61,
++	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP             = 0x62,
++	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM                 = 0x63,
++	PERF_PAPC_CLIPGA_IDLE                            = 0x64,
++	PERF_PAPC_CLIPGA_BUSY                            = 0x65,
++	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP                = 0x66,
++	PERF_PAPC_CLIPGA_STALLED                         = 0x67,
++	PERF_PAPC_CLIP_IDLE                              = 0x68,
++	PERF_PAPC_CLIP_BUSY                              = 0x69,
++	PERF_PAPC_SU_IDLE                                = 0x6a,
++	PERF_PAPC_SU_BUSY                                = 0x6b,
++	PERF_PAPC_SU_STARVED_CLIP                        = 0x6c,
++	PERF_PAPC_SU_STALLED_SC                          = 0x6d,
++	PERF_PAPC_CL_DYN_SCLK_VLD                        = 0x6e,
++	PERF_PAPC_SU_DYN_SCLK_VLD                        = 0x6f,
++	PERF_PAPC_PA_REG_SCLK_VLD                        = 0x70,
++	PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL          = 0x71,
++	PERF_PAPC_PASX_SE0_REQ                           = 0x72,
++	PERF_PAPC_PASX_SE1_REQ                           = 0x73,
++	PERF_PAPC_PASX_SE0_FIRST_VECTOR                  = 0x74,
++	PERF_PAPC_PASX_SE0_SECOND_VECTOR                 = 0x75,
++	PERF_PAPC_PASX_SE1_FIRST_VECTOR                  = 0x76,
++	PERF_PAPC_PASX_SE1_SECOND_VECTOR                 = 0x77,
++	PERF_PAPC_SU_SE0_PRIM_FILTER_CULL                = 0x78,
++	PERF_PAPC_SU_SE1_PRIM_FILTER_CULL                = 0x79,
++	PERF_PAPC_SU_SE01_PRIM_FILTER_CULL               = 0x7a,
++	PERF_PAPC_SU_SE0_OUTPUT_PRIM                     = 0x7b,
++	PERF_PAPC_SU_SE1_OUTPUT_PRIM                     = 0x7c,
++	PERF_PAPC_SU_SE01_OUTPUT_PRIM                    = 0x7d,
++	PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM                = 0x7e,
++	PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM                = 0x7f,
++	PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM               = 0x80,
++	PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT          = 0x81,
++	PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT          = 0x82,
++	PERF_PAPC_SU_SE0_STALLED_SC                      = 0x83,
++	PERF_PAPC_SU_SE1_STALLED_SC                      = 0x84,
++	PERF_PAPC_SU_SE01_STALLED_SC                     = 0x85,
++	PERF_PAPC_CLSM_CLIPPING_PRIM                     = 0x86,
++	PERF_PAPC_SU_CULLED_PRIM                         = 0x87,
++	PERF_PAPC_SU_OUTPUT_EOPG                         = 0x88,
++	PERF_PAPC_SU_SE2_PRIM_FILTER_CULL                = 0x89,
++	PERF_PAPC_SU_SE3_PRIM_FILTER_CULL                = 0x8a,
++	PERF_PAPC_SU_SE2_OUTPUT_PRIM                     = 0x8b,
++	PERF_PAPC_SU_SE3_OUTPUT_PRIM                     = 0x8c,
++	PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM                = 0x8d,
++	PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM                = 0x8e,
++	PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET            = 0x8f,
++	PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET            = 0x90,
++	PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET            = 0x91,
++	PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET            = 0x92,
++	PERF_PAPC_SU_SE0_OUTPUT_EOPG                     = 0x93,
++	PERF_PAPC_SU_SE1_OUTPUT_EOPG                     = 0x94,
++	PERF_PAPC_SU_SE2_OUTPUT_EOPG                     = 0x95,
++	PERF_PAPC_SU_SE3_OUTPUT_EOPG                     = 0x96,
++	PERF_PAPC_SU_SE2_STALLED_SC                      = 0x97,
++	PERF_PAPC_SU_SE3_STALLED_SC                      = 0x98,
++} SU_PERFCNT_SEL;
++typedef enum SC_PERFCNT_SEL {
++	SC_SRPS_WINDOW_VALID                             = 0x0,
++	SC_PSSW_WINDOW_VALID                             = 0x1,
++	SC_TPQZ_WINDOW_VALID                             = 0x2,
++	SC_QZQP_WINDOW_VALID                             = 0x3,
++	SC_TRPK_WINDOW_VALID                             = 0x4,
++	SC_SRPS_WINDOW_VALID_BUSY                        = 0x5,
++	SC_PSSW_WINDOW_VALID_BUSY                        = 0x6,
++	SC_TPQZ_WINDOW_VALID_BUSY                        = 0x7,
++	SC_QZQP_WINDOW_VALID_BUSY                        = 0x8,
++	SC_TRPK_WINDOW_VALID_BUSY                        = 0x9,
++	SC_STARVED_BY_PA                                 = 0xa,
++	SC_STALLED_BY_PRIMFIFO                           = 0xb,
++	SC_STALLED_BY_DB_TILE                            = 0xc,
++	SC_STARVED_BY_DB_TILE                            = 0xd,
++	SC_STALLED_BY_TILEORDERFIFO                      = 0xe,
++	SC_STALLED_BY_TILEFIFO                           = 0xf,
++	SC_STALLED_BY_DB_QUAD                            = 0x10,
++	SC_STARVED_BY_DB_QUAD                            = 0x11,
++	SC_STALLED_BY_QUADFIFO                           = 0x12,
++	SC_STALLED_BY_BCI                                = 0x13,
++	SC_STALLED_BY_SPI                                = 0x14,
++	SC_SCISSOR_DISCARD                               = 0x15,
++	SC_BB_DISCARD                                    = 0x16,
++	SC_SUPERTILE_COUNT                               = 0x17,
++	SC_SUPERTILE_PER_PRIM_H0                         = 0x18,
++	SC_SUPERTILE_PER_PRIM_H1                         = 0x19,
++	SC_SUPERTILE_PER_PRIM_H2                         = 0x1a,
++	SC_SUPERTILE_PER_PRIM_H3                         = 0x1b,
++	SC_SUPERTILE_PER_PRIM_H4                         = 0x1c,
++	SC_SUPERTILE_PER_PRIM_H5                         = 0x1d,
++	SC_SUPERTILE_PER_PRIM_H6                         = 0x1e,
++	SC_SUPERTILE_PER_PRIM_H7                         = 0x1f,
++	SC_SUPERTILE_PER_PRIM_H8                         = 0x20,
++	SC_SUPERTILE_PER_PRIM_H9                         = 0x21,
++	SC_SUPERTILE_PER_PRIM_H10                        = 0x22,
++	SC_SUPERTILE_PER_PRIM_H11                        = 0x23,
++	SC_SUPERTILE_PER_PRIM_H12                        = 0x24,
++	SC_SUPERTILE_PER_PRIM_H13                        = 0x25,
++	SC_SUPERTILE_PER_PRIM_H14                        = 0x26,
++	SC_SUPERTILE_PER_PRIM_H15                        = 0x27,
++	SC_SUPERTILE_PER_PRIM_H16                        = 0x28,
++	SC_TILE_PER_PRIM_H0                              = 0x29,
++	SC_TILE_PER_PRIM_H1                              = 0x2a,
++	SC_TILE_PER_PRIM_H2                              = 0x2b,
++	SC_TILE_PER_PRIM_H3                              = 0x2c,
++	SC_TILE_PER_PRIM_H4                              = 0x2d,
++	SC_TILE_PER_PRIM_H5                              = 0x2e,
++	SC_TILE_PER_PRIM_H6                              = 0x2f,
++	SC_TILE_PER_PRIM_H7                              = 0x30,
++	SC_TILE_PER_PRIM_H8                              = 0x31,
++	SC_TILE_PER_PRIM_H9                              = 0x32,
++	SC_TILE_PER_PRIM_H10                             = 0x33,
++	SC_TILE_PER_PRIM_H11                             = 0x34,
++	SC_TILE_PER_PRIM_H12                             = 0x35,
++	SC_TILE_PER_PRIM_H13                             = 0x36,
++	SC_TILE_PER_PRIM_H14                             = 0x37,
++	SC_TILE_PER_PRIM_H15                             = 0x38,
++	SC_TILE_PER_PRIM_H16                             = 0x39,
++	SC_TILE_PER_SUPERTILE_H0                         = 0x3a,
++	SC_TILE_PER_SUPERTILE_H1                         = 0x3b,
++	SC_TILE_PER_SUPERTILE_H2                         = 0x3c,
++	SC_TILE_PER_SUPERTILE_H3                         = 0x3d,
++	SC_TILE_PER_SUPERTILE_H4                         = 0x3e,
++	SC_TILE_PER_SUPERTILE_H5                         = 0x3f,
++	SC_TILE_PER_SUPERTILE_H6                         = 0x40,
++	SC_TILE_PER_SUPERTILE_H7                         = 0x41,
++	SC_TILE_PER_SUPERTILE_H8                         = 0x42,
++	SC_TILE_PER_SUPERTILE_H9                         = 0x43,
++	SC_TILE_PER_SUPERTILE_H10                        = 0x44,
++	SC_TILE_PER_SUPERTILE_H11                        = 0x45,
++	SC_TILE_PER_SUPERTILE_H12                        = 0x46,
++	SC_TILE_PER_SUPERTILE_H13                        = 0x47,
++	SC_TILE_PER_SUPERTILE_H14                        = 0x48,
++	SC_TILE_PER_SUPERTILE_H15                        = 0x49,
++	SC_TILE_PER_SUPERTILE_H16                        = 0x4a,
++	SC_TILE_PICKED_H1                                = 0x4b,
++	SC_TILE_PICKED_H2                                = 0x4c,
++	SC_TILE_PICKED_H3                                = 0x4d,
++	SC_TILE_PICKED_H4                                = 0x4e,
++	SC_QZ0_MULTI_GPU_TILE_DISCARD                    = 0x4f,
++	SC_QZ1_MULTI_GPU_TILE_DISCARD                    = 0x50,
++	SC_QZ2_MULTI_GPU_TILE_DISCARD                    = 0x51,
++	SC_QZ3_MULTI_GPU_TILE_DISCARD                    = 0x52,
++	SC_QZ0_TILE_COUNT                                = 0x53,
++	SC_QZ1_TILE_COUNT                                = 0x54,
++	SC_QZ2_TILE_COUNT                                = 0x55,
++	SC_QZ3_TILE_COUNT                                = 0x56,
++	SC_QZ0_TILE_COVERED_COUNT                        = 0x57,
++	SC_QZ1_TILE_COVERED_COUNT                        = 0x58,
++	SC_QZ2_TILE_COVERED_COUNT                        = 0x59,
++	SC_QZ3_TILE_COVERED_COUNT                        = 0x5a,
++	SC_QZ0_TILE_NOT_COVERED_COUNT                    = 0x5b,
++	SC_QZ1_TILE_NOT_COVERED_COUNT                    = 0x5c,
++	SC_QZ2_TILE_NOT_COVERED_COUNT                    = 0x5d,
++	SC_QZ3_TILE_NOT_COVERED_COUNT                    = 0x5e,
++	SC_QZ0_QUAD_PER_TILE_H0                          = 0x5f,
++	SC_QZ0_QUAD_PER_TILE_H1                          = 0x60,
++	SC_QZ0_QUAD_PER_TILE_H2                          = 0x61,
++	SC_QZ0_QUAD_PER_TILE_H3                          = 0x62,
++	SC_QZ0_QUAD_PER_TILE_H4                          = 0x63,
++	SC_QZ0_QUAD_PER_TILE_H5                          = 0x64,
++	SC_QZ0_QUAD_PER_TILE_H6                          = 0x65,
++	SC_QZ0_QUAD_PER_TILE_H7                          = 0x66,
++	SC_QZ0_QUAD_PER_TILE_H8                          = 0x67,
++	SC_QZ0_QUAD_PER_TILE_H9                          = 0x68,
++	SC_QZ0_QUAD_PER_TILE_H10                         = 0x69,
++	SC_QZ0_QUAD_PER_TILE_H11                         = 0x6a,
++	SC_QZ0_QUAD_PER_TILE_H12                         = 0x6b,
++	SC_QZ0_QUAD_PER_TILE_H13                         = 0x6c,
++	SC_QZ0_QUAD_PER_TILE_H14                         = 0x6d,
++	SC_QZ0_QUAD_PER_TILE_H15                         = 0x6e,
++	SC_QZ0_QUAD_PER_TILE_H16                         = 0x6f,
++	SC_QZ1_QUAD_PER_TILE_H0                          = 0x70,
++	SC_QZ1_QUAD_PER_TILE_H1                          = 0x71,
++	SC_QZ1_QUAD_PER_TILE_H2                          = 0x72,
++	SC_QZ1_QUAD_PER_TILE_H3                          = 0x73,
++	SC_QZ1_QUAD_PER_TILE_H4                          = 0x74,
++	SC_QZ1_QUAD_PER_TILE_H5                          = 0x75,
++	SC_QZ1_QUAD_PER_TILE_H6                          = 0x76,
++	SC_QZ1_QUAD_PER_TILE_H7                          = 0x77,
++	SC_QZ1_QUAD_PER_TILE_H8                          = 0x78,
++	SC_QZ1_QUAD_PER_TILE_H9                          = 0x79,
++	SC_QZ1_QUAD_PER_TILE_H10                         = 0x7a,
++	SC_QZ1_QUAD_PER_TILE_H11                         = 0x7b,
++	SC_QZ1_QUAD_PER_TILE_H12                         = 0x7c,
++	SC_QZ1_QUAD_PER_TILE_H13                         = 0x7d,
++	SC_QZ1_QUAD_PER_TILE_H14                         = 0x7e,
++	SC_QZ1_QUAD_PER_TILE_H15                         = 0x7f,
++	SC_QZ1_QUAD_PER_TILE_H16                         = 0x80,
++	SC_QZ2_QUAD_PER_TILE_H0                          = 0x81,
++	SC_QZ2_QUAD_PER_TILE_H1                          = 0x82,
++	SC_QZ2_QUAD_PER_TILE_H2                          = 0x83,
++	SC_QZ2_QUAD_PER_TILE_H3                          = 0x84,
++	SC_QZ2_QUAD_PER_TILE_H4                          = 0x85,
++	SC_QZ2_QUAD_PER_TILE_H5                          = 0x86,
++	SC_QZ2_QUAD_PER_TILE_H6                          = 0x87,
++	SC_QZ2_QUAD_PER_TILE_H7                          = 0x88,
++	SC_QZ2_QUAD_PER_TILE_H8                          = 0x89,
++	SC_QZ2_QUAD_PER_TILE_H9                          = 0x8a,
++	SC_QZ2_QUAD_PER_TILE_H10                         = 0x8b,
++	SC_QZ2_QUAD_PER_TILE_H11                         = 0x8c,
++	SC_QZ2_QUAD_PER_TILE_H12                         = 0x8d,
++	SC_QZ2_QUAD_PER_TILE_H13                         = 0x8e,
++	SC_QZ2_QUAD_PER_TILE_H14                         = 0x8f,
++	SC_QZ2_QUAD_PER_TILE_H15                         = 0x90,
++	SC_QZ2_QUAD_PER_TILE_H16                         = 0x91,
++	SC_QZ3_QUAD_PER_TILE_H0                          = 0x92,
++	SC_QZ3_QUAD_PER_TILE_H1                          = 0x93,
++	SC_QZ3_QUAD_PER_TILE_H2                          = 0x94,
++	SC_QZ3_QUAD_PER_TILE_H3                          = 0x95,
++	SC_QZ3_QUAD_PER_TILE_H4                          = 0x96,
++	SC_QZ3_QUAD_PER_TILE_H5                          = 0x97,
++	SC_QZ3_QUAD_PER_TILE_H6                          = 0x98,
++	SC_QZ3_QUAD_PER_TILE_H7                          = 0x99,
++	SC_QZ3_QUAD_PER_TILE_H8                          = 0x9a,
++	SC_QZ3_QUAD_PER_TILE_H9                          = 0x9b,
++	SC_QZ3_QUAD_PER_TILE_H10                         = 0x9c,
++	SC_QZ3_QUAD_PER_TILE_H11                         = 0x9d,
++	SC_QZ3_QUAD_PER_TILE_H12                         = 0x9e,
++	SC_QZ3_QUAD_PER_TILE_H13                         = 0x9f,
++	SC_QZ3_QUAD_PER_TILE_H14                         = 0xa0,
++	SC_QZ3_QUAD_PER_TILE_H15                         = 0xa1,
++	SC_QZ3_QUAD_PER_TILE_H16                         = 0xa2,
++	SC_QZ0_QUAD_COUNT                                = 0xa3,
++	SC_QZ1_QUAD_COUNT                                = 0xa4,
++	SC_QZ2_QUAD_COUNT                                = 0xa5,
++	SC_QZ3_QUAD_COUNT                                = 0xa6,
++	SC_P0_HIZ_TILE_COUNT                             = 0xa7,
++	SC_P1_HIZ_TILE_COUNT                             = 0xa8,
++	SC_P2_HIZ_TILE_COUNT                             = 0xa9,
++	SC_P3_HIZ_TILE_COUNT                             = 0xaa,
++	SC_P0_HIZ_QUAD_PER_TILE_H0                       = 0xab,
++	SC_P0_HIZ_QUAD_PER_TILE_H1                       = 0xac,
++	SC_P0_HIZ_QUAD_PER_TILE_H2                       = 0xad,
++	SC_P0_HIZ_QUAD_PER_TILE_H3                       = 0xae,
++	SC_P0_HIZ_QUAD_PER_TILE_H4                       = 0xaf,
++	SC_P0_HIZ_QUAD_PER_TILE_H5                       = 0xb0,
++	SC_P0_HIZ_QUAD_PER_TILE_H6                       = 0xb1,
++	SC_P0_HIZ_QUAD_PER_TILE_H7                       = 0xb2,
++	SC_P0_HIZ_QUAD_PER_TILE_H8                       = 0xb3,
++	SC_P0_HIZ_QUAD_PER_TILE_H9                       = 0xb4,
++	SC_P0_HIZ_QUAD_PER_TILE_H10                      = 0xb5,
++	SC_P0_HIZ_QUAD_PER_TILE_H11                      = 0xb6,
++	SC_P0_HIZ_QUAD_PER_TILE_H12                      = 0xb7,
++	SC_P0_HIZ_QUAD_PER_TILE_H13                      = 0xb8,
++	SC_P0_HIZ_QUAD_PER_TILE_H14                      = 0xb9,
++	SC_P0_HIZ_QUAD_PER_TILE_H15                      = 0xba,
++	SC_P0_HIZ_QUAD_PER_TILE_H16                      = 0xbb,
++	SC_P1_HIZ_QUAD_PER_TILE_H0                       = 0xbc,
++	SC_P1_HIZ_QUAD_PER_TILE_H1                       = 0xbd,
++	SC_P1_HIZ_QUAD_PER_TILE_H2                       = 0xbe,
++	SC_P1_HIZ_QUAD_PER_TILE_H3                       = 0xbf,
++	SC_P1_HIZ_QUAD_PER_TILE_H4                       = 0xc0,
++	SC_P1_HIZ_QUAD_PER_TILE_H5                       = 0xc1,
++	SC_P1_HIZ_QUAD_PER_TILE_H6                       = 0xc2,
++	SC_P1_HIZ_QUAD_PER_TILE_H7                       = 0xc3,
++	SC_P1_HIZ_QUAD_PER_TILE_H8                       = 0xc4,
++	SC_P1_HIZ_QUAD_PER_TILE_H9                       = 0xc5,
++	SC_P1_HIZ_QUAD_PER_TILE_H10                      = 0xc6,
++	SC_P1_HIZ_QUAD_PER_TILE_H11                      = 0xc7,
++	SC_P1_HIZ_QUAD_PER_TILE_H12                      = 0xc8,
++	SC_P1_HIZ_QUAD_PER_TILE_H13                      = 0xc9,
++	SC_P1_HIZ_QUAD_PER_TILE_H14                      = 0xca,
++	SC_P1_HIZ_QUAD_PER_TILE_H15                      = 0xcb,
++	SC_P1_HIZ_QUAD_PER_TILE_H16                      = 0xcc,
++	SC_P2_HIZ_QUAD_PER_TILE_H0                       = 0xcd,
++	SC_P2_HIZ_QUAD_PER_TILE_H1                       = 0xce,
++	SC_P2_HIZ_QUAD_PER_TILE_H2                       = 0xcf,
++	SC_P2_HIZ_QUAD_PER_TILE_H3                       = 0xd0,
++	SC_P2_HIZ_QUAD_PER_TILE_H4                       = 0xd1,
++	SC_P2_HIZ_QUAD_PER_TILE_H5                       = 0xd2,
++	SC_P2_HIZ_QUAD_PER_TILE_H6                       = 0xd3,
++	SC_P2_HIZ_QUAD_PER_TILE_H7                       = 0xd4,
++	SC_P2_HIZ_QUAD_PER_TILE_H8                       = 0xd5,
++	SC_P2_HIZ_QUAD_PER_TILE_H9                       = 0xd6,
++	SC_P2_HIZ_QUAD_PER_TILE_H10                      = 0xd7,
++	SC_P2_HIZ_QUAD_PER_TILE_H11                      = 0xd8,
++	SC_P2_HIZ_QUAD_PER_TILE_H12                      = 0xd9,
++	SC_P2_HIZ_QUAD_PER_TILE_H13                      = 0xda,
++	SC_P2_HIZ_QUAD_PER_TILE_H14                      = 0xdb,
++	SC_P2_HIZ_QUAD_PER_TILE_H15                      = 0xdc,
++	SC_P2_HIZ_QUAD_PER_TILE_H16                      = 0xdd,
++	SC_P3_HIZ_QUAD_PER_TILE_H0                       = 0xde,
++	SC_P3_HIZ_QUAD_PER_TILE_H1                       = 0xdf,
++	SC_P3_HIZ_QUAD_PER_TILE_H2                       = 0xe0,
++	SC_P3_HIZ_QUAD_PER_TILE_H3                       = 0xe1,
++	SC_P3_HIZ_QUAD_PER_TILE_H4                       = 0xe2,
++	SC_P3_HIZ_QUAD_PER_TILE_H5                       = 0xe3,
++	SC_P3_HIZ_QUAD_PER_TILE_H6                       = 0xe4,
++	SC_P3_HIZ_QUAD_PER_TILE_H7                       = 0xe5,
++	SC_P3_HIZ_QUAD_PER_TILE_H8                       = 0xe6,
++	SC_P3_HIZ_QUAD_PER_TILE_H9                       = 0xe7,
++	SC_P3_HIZ_QUAD_PER_TILE_H10                      = 0xe8,
++	SC_P3_HIZ_QUAD_PER_TILE_H11                      = 0xe9,
++	SC_P3_HIZ_QUAD_PER_TILE_H12                      = 0xea,
++	SC_P3_HIZ_QUAD_PER_TILE_H13                      = 0xeb,
++	SC_P3_HIZ_QUAD_PER_TILE_H14                      = 0xec,
++	SC_P3_HIZ_QUAD_PER_TILE_H15                      = 0xed,
++	SC_P3_HIZ_QUAD_PER_TILE_H16                      = 0xee,
++	SC_P0_HIZ_QUAD_COUNT                             = 0xef,
++	SC_P1_HIZ_QUAD_COUNT                             = 0xf0,
++	SC_P2_HIZ_QUAD_COUNT                             = 0xf1,
++	SC_P3_HIZ_QUAD_COUNT                             = 0xf2,
++	SC_P0_DETAIL_QUAD_COUNT                          = 0xf3,
++	SC_P1_DETAIL_QUAD_COUNT                          = 0xf4,
++	SC_P2_DETAIL_QUAD_COUNT                          = 0xf5,
++	SC_P3_DETAIL_QUAD_COUNT                          = 0xf6,
++	SC_P0_DETAIL_QUAD_WITH_1_PIX                     = 0xf7,
++	SC_P0_DETAIL_QUAD_WITH_2_PIX                     = 0xf8,
++	SC_P0_DETAIL_QUAD_WITH_3_PIX                     = 0xf9,
++	SC_P0_DETAIL_QUAD_WITH_4_PIX                     = 0xfa,
++	SC_P1_DETAIL_QUAD_WITH_1_PIX                     = 0xfb,
++	SC_P1_DETAIL_QUAD_WITH_2_PIX                     = 0xfc,
++	SC_P1_DETAIL_QUAD_WITH_3_PIX                     = 0xfd,
++	SC_P1_DETAIL_QUAD_WITH_4_PIX                     = 0xfe,
++	SC_P2_DETAIL_QUAD_WITH_1_PIX                     = 0xff,
++	SC_P2_DETAIL_QUAD_WITH_2_PIX                     = 0x100,
++	SC_P2_DETAIL_QUAD_WITH_3_PIX                     = 0x101,
++	SC_P2_DETAIL_QUAD_WITH_4_PIX                     = 0x102,
++	SC_P3_DETAIL_QUAD_WITH_1_PIX                     = 0x103,
++	SC_P3_DETAIL_QUAD_WITH_2_PIX                     = 0x104,
++	SC_P3_DETAIL_QUAD_WITH_3_PIX                     = 0x105,
++	SC_P3_DETAIL_QUAD_WITH_4_PIX                     = 0x106,
++	SC_EARLYZ_QUAD_COUNT                             = 0x107,
++	SC_EARLYZ_QUAD_WITH_1_PIX                        = 0x108,
++	SC_EARLYZ_QUAD_WITH_2_PIX                        = 0x109,
++	SC_EARLYZ_QUAD_WITH_3_PIX                        = 0x10a,
++	SC_EARLYZ_QUAD_WITH_4_PIX                        = 0x10b,
++	SC_PKR_QUAD_PER_ROW_H1                           = 0x10c,
++	SC_PKR_QUAD_PER_ROW_H2                           = 0x10d,
++	SC_PKR_QUAD_PER_ROW_H3                           = 0x10e,
++	SC_PKR_QUAD_PER_ROW_H4                           = 0x10f,
++	SC_PKR_END_OF_VECTOR                             = 0x110,
++	SC_PKR_CONTROL_XFER                              = 0x111,
++	SC_PKR_DBHANG_FORCE_EOV                          = 0x112,
++	SC_REG_SCLK_BUSY                                 = 0x113,
++	SC_GRP0_DYN_SCLK_BUSY                            = 0x114,
++	SC_GRP1_DYN_SCLK_BUSY                            = 0x115,
++	SC_GRP2_DYN_SCLK_BUSY                            = 0x116,
++	SC_GRP3_DYN_SCLK_BUSY                            = 0x117,
++	SC_GRP4_DYN_SCLK_BUSY                            = 0x118,
++	SC_PA0_SC_DATA_FIFO_RD                           = 0x119,
++	SC_PA0_SC_DATA_FIFO_WE                           = 0x11a,
++	SC_PA1_SC_DATA_FIFO_RD                           = 0x11b,
++	SC_PA1_SC_DATA_FIFO_WE                           = 0x11c,
++	SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES           = 0x11d,
++	SC_PS_ARB_XFC_ONLY_PRIM_CYCLES                   = 0x11e,
++	SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM              = 0x11f,
++	SC_PS_ARB_STALLED_FROM_BELOW                     = 0x120,
++	SC_PS_ARB_STARVED_FROM_ABOVE                     = 0x121,
++	SC_PS_ARB_SC_BUSY                                = 0x122,
++	SC_PS_ARB_PA_SC_BUSY                             = 0x123,
++	SC_PA2_SC_DATA_FIFO_RD                           = 0x124,
++	SC_PA2_SC_DATA_FIFO_WE                           = 0x125,
++	SC_PA3_SC_DATA_FIFO_RD                           = 0x126,
++	SC_PA3_SC_DATA_FIFO_WE                           = 0x127,
++	SC_PA_SC_DEALLOC_0_0_WE                          = 0x128,
++	SC_PA_SC_DEALLOC_0_1_WE                          = 0x129,
++	SC_PA_SC_DEALLOC_1_0_WE                          = 0x12a,
++	SC_PA_SC_DEALLOC_1_1_WE                          = 0x12b,
++	SC_PA_SC_DEALLOC_2_0_WE                          = 0x12c,
++	SC_PA_SC_DEALLOC_2_1_WE                          = 0x12d,
++	SC_PA_SC_DEALLOC_3_0_WE                          = 0x12e,
++	SC_PA_SC_DEALLOC_3_1_WE                          = 0x12f,
++	SC_PA0_SC_EOP_WE                                 = 0x130,
++	SC_PA0_SC_EOPG_WE                                = 0x131,
++	SC_PA0_SC_EVENT_WE                               = 0x132,
++	SC_PA1_SC_EOP_WE                                 = 0x133,
++	SC_PA1_SC_EOPG_WE                                = 0x134,
++	SC_PA1_SC_EVENT_WE                               = 0x135,
++	SC_PA2_SC_EOP_WE                                 = 0x136,
++	SC_PA2_SC_EOPG_WE                                = 0x137,
++	SC_PA2_SC_EVENT_WE                               = 0x138,
++	SC_PA3_SC_EOP_WE                                 = 0x139,
++	SC_PA3_SC_EOPG_WE                                = 0x13a,
++	SC_PA3_SC_EVENT_WE                               = 0x13b,
++	SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO   = 0x13c,
++	SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH                  = 0x13d,
++	SC_PS_ARB_NULL_PRIM_BUBBLE_POP                   = 0x13e,
++	SC_PS_ARB_EOP_POP_SYNC_POP                       = 0x13f,
++	SC_PS_ARB_EVENT_SYNC_POP                         = 0x140,
++	SC_SC_PS_ENG_MULTICYCLE_BUBBLE                   = 0x141,
++	SC_PA0_SC_FPOV_WE                                = 0x142,
++	SC_PA1_SC_FPOV_WE                                = 0x143,
++	SC_PA2_SC_FPOV_WE                                = 0x144,
++	SC_PA3_SC_FPOV_WE                                = 0x145,
++	SC_PA0_SC_LPOV_WE                                = 0x146,
++	SC_PA1_SC_LPOV_WE                                = 0x147,
++	SC_PA2_SC_LPOV_WE                                = 0x148,
++	SC_PA3_SC_LPOV_WE                                = 0x149,
++	SC_SC_SPI_DEALLOC_0_0                            = 0x14a,
++	SC_SC_SPI_DEALLOC_0_1                            = 0x14b,
++	SC_SC_SPI_DEALLOC_0_2                            = 0x14c,
++	SC_SC_SPI_DEALLOC_1_0                            = 0x14d,
++	SC_SC_SPI_DEALLOC_1_1                            = 0x14e,
++	SC_SC_SPI_DEALLOC_1_2                            = 0x14f,
++	SC_SC_SPI_DEALLOC_2_0                            = 0x150,
++	SC_SC_SPI_DEALLOC_2_1                            = 0x151,
++	SC_SC_SPI_DEALLOC_2_2                            = 0x152,
++	SC_SC_SPI_DEALLOC_3_0                            = 0x153,
++	SC_SC_SPI_DEALLOC_3_1                            = 0x154,
++	SC_SC_SPI_DEALLOC_3_2                            = 0x155,
++	SC_SC_SPI_FPOV_0                                 = 0x156,
++	SC_SC_SPI_FPOV_1                                 = 0x157,
++	SC_SC_SPI_FPOV_2                                 = 0x158,
++	SC_SC_SPI_FPOV_3                                 = 0x159,
++	SC_SC_SPI_EVENT                                  = 0x15a,
++	SC_PS_TS_EVENT_FIFO_PUSH                         = 0x15b,
++	SC_PS_TS_EVENT_FIFO_POP                          = 0x15c,
++	SC_PS_CTX_DONE_FIFO_PUSH                         = 0x15d,
++	SC_PS_CTX_DONE_FIFO_POP                          = 0x15e,
++	SC_MULTICYCLE_BUBBLE_FREEZE                      = 0x15f,
++	SC_EOP_SYNC_WINDOW                               = 0x160,
++	SC_PA0_SC_NULL_WE                                = 0x161,
++	SC_PA0_SC_NULL_DEALLOC_WE                        = 0x162,
++	SC_PA0_SC_DATA_FIFO_EOPG_RD                      = 0x163,
++	SC_PA0_SC_DATA_FIFO_EOP_RD                       = 0x164,
++	SC_PA0_SC_DEALLOC_0_RD                           = 0x165,
++	SC_PA0_SC_DEALLOC_1_RD                           = 0x166,
++	SC_PA1_SC_DATA_FIFO_EOPG_RD                      = 0x167,
++	SC_PA1_SC_DATA_FIFO_EOP_RD                       = 0x168,
++	SC_PA1_SC_DEALLOC_0_RD                           = 0x169,
++	SC_PA1_SC_DEALLOC_1_RD                           = 0x16a,
++	SC_PA1_SC_NULL_WE                                = 0x16b,
++	SC_PA1_SC_NULL_DEALLOC_WE                        = 0x16c,
++	SC_PA2_SC_DATA_FIFO_EOPG_RD                      = 0x16d,
++	SC_PA2_SC_DATA_FIFO_EOP_RD                       = 0x16e,
++	SC_PA2_SC_DEALLOC_0_RD                           = 0x16f,
++	SC_PA2_SC_DEALLOC_1_RD                           = 0x170,
++	SC_PA2_SC_NULL_WE                                = 0x171,
++	SC_PA2_SC_NULL_DEALLOC_WE                        = 0x172,
++	SC_PA3_SC_DATA_FIFO_EOPG_RD                      = 0x173,
++	SC_PA3_SC_DATA_FIFO_EOP_RD                       = 0x174,
++	SC_PA3_SC_DEALLOC_0_RD                           = 0x175,
++	SC_PA3_SC_DEALLOC_1_RD                           = 0x176,
++	SC_PA3_SC_NULL_WE                                = 0x177,
++	SC_PA3_SC_NULL_DEALLOC_WE                        = 0x178,
++	SC_PS_PA0_SC_FIFO_EMPTY                          = 0x179,
++	SC_PS_PA0_SC_FIFO_FULL                           = 0x17a,
++	SC_PA0_PS_DATA_SEND                              = 0x17b,
++	SC_PS_PA1_SC_FIFO_EMPTY                          = 0x17c,
++	SC_PS_PA1_SC_FIFO_FULL                           = 0x17d,
++	SC_PA1_PS_DATA_SEND                              = 0x17e,
++	SC_PS_PA2_SC_FIFO_EMPTY                          = 0x17f,
++	SC_PS_PA2_SC_FIFO_FULL                           = 0x180,
++	SC_PA2_PS_DATA_SEND                              = 0x181,
++	SC_PS_PA3_SC_FIFO_EMPTY                          = 0x182,
++	SC_PS_PA3_SC_FIFO_FULL                           = 0x183,
++	SC_PA3_PS_DATA_SEND                              = 0x184,
++	SC_BUSY_PROCESSING_MULTICYCLE_PRIM               = 0x185,
++	SC_BUSY_CNT_NOT_ZERO                             = 0x186,
++	SC_BM_BUSY                                       = 0x187,
++	SC_BACKEND_BUSY                                  = 0x188,
++	SC_SCF_SCB_INTERFACE_BUSY                        = 0x189,
++	SC_SCB_BUSY                                      = 0x18a,
++} SC_PERFCNT_SEL;
++typedef enum SePairXsel {
++	RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE           = 0x0,
++	RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE          = 0x1,
++	RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE          = 0x2,
++	RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE          = 0x3,
++} SePairXsel;
++typedef enum SePairYsel {
++	RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE           = 0x0,
++	RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE          = 0x1,
++	RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE          = 0x2,
++	RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE          = 0x3,
++} SePairYsel;
++typedef enum SePairMap {
++	RASTER_CONFIG_SE_PAIR_MAP_0                      = 0x0,
++	RASTER_CONFIG_SE_PAIR_MAP_1                      = 0x1,
++	RASTER_CONFIG_SE_PAIR_MAP_2                      = 0x2,
++	RASTER_CONFIG_SE_PAIR_MAP_3                      = 0x3,
++} SePairMap;
++typedef enum SeXsel {
++	RASTER_CONFIG_SE_XSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SE_XSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SE_XSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SE_XSEL_64_WIDE_TILE               = 0x3,
++} SeXsel;
++typedef enum SeYsel {
++	RASTER_CONFIG_SE_YSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SE_YSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SE_YSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SE_YSEL_64_WIDE_TILE               = 0x3,
++} SeYsel;
++typedef enum SeMap {
++	RASTER_CONFIG_SE_MAP_0                           = 0x0,
++	RASTER_CONFIG_SE_MAP_1                           = 0x1,
++	RASTER_CONFIG_SE_MAP_2                           = 0x2,
++	RASTER_CONFIG_SE_MAP_3                           = 0x3,
++} SeMap;
++typedef enum ScXsel {
++	RASTER_CONFIG_SC_XSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SC_XSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SC_XSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SC_XSEL_64_WIDE_TILE               = 0x3,
++} ScXsel;
++typedef enum ScYsel {
++	RASTER_CONFIG_SC_YSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SC_YSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SC_YSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SC_YSEL_64_WIDE_TILE               = 0x3,
++} ScYsel;
++typedef enum ScMap {
++	RASTER_CONFIG_SC_MAP_0                           = 0x0,
++	RASTER_CONFIG_SC_MAP_1                           = 0x1,
++	RASTER_CONFIG_SC_MAP_2                           = 0x2,
++	RASTER_CONFIG_SC_MAP_3                           = 0x3,
++} ScMap;
++typedef enum PkrXsel2 {
++	RASTER_CONFIG_PKR_XSEL2_0                        = 0x0,
++	RASTER_CONFIG_PKR_XSEL2_1                        = 0x1,
++	RASTER_CONFIG_PKR_XSEL2_2                        = 0x2,
++	RASTER_CONFIG_PKR_XSEL2_3                        = 0x3,
++} PkrXsel2;
++typedef enum PkrXsel {
++	RASTER_CONFIG_PKR_XSEL_0                         = 0x0,
++	RASTER_CONFIG_PKR_XSEL_1                         = 0x1,
++	RASTER_CONFIG_PKR_XSEL_2                         = 0x2,
++	RASTER_CONFIG_PKR_XSEL_3                         = 0x3,
++} PkrXsel;
++typedef enum PkrYsel {
++	RASTER_CONFIG_PKR_YSEL_0                         = 0x0,
++	RASTER_CONFIG_PKR_YSEL_1                         = 0x1,
++	RASTER_CONFIG_PKR_YSEL_2                         = 0x2,
++	RASTER_CONFIG_PKR_YSEL_3                         = 0x3,
++} PkrYsel;
++typedef enum PkrMap {
++	RASTER_CONFIG_PKR_MAP_0                          = 0x0,
++	RASTER_CONFIG_PKR_MAP_1                          = 0x1,
++	RASTER_CONFIG_PKR_MAP_2                          = 0x2,
++	RASTER_CONFIG_PKR_MAP_3                          = 0x3,
++} PkrMap;
++typedef enum RbXsel {
++	RASTER_CONFIG_RB_XSEL_0                          = 0x0,
++	RASTER_CONFIG_RB_XSEL_1                          = 0x1,
++} RbXsel;
++typedef enum RbYsel {
++	RASTER_CONFIG_RB_YSEL_0                          = 0x0,
++	RASTER_CONFIG_RB_YSEL_1                          = 0x1,
++} RbYsel;
++typedef enum RbXsel2 {
++	RASTER_CONFIG_RB_XSEL2_0                         = 0x0,
++	RASTER_CONFIG_RB_XSEL2_1                         = 0x1,
++	RASTER_CONFIG_RB_XSEL2_2                         = 0x2,
++	RASTER_CONFIG_RB_XSEL2_3                         = 0x3,
++} RbXsel2;
++typedef enum RbMap {
++	RASTER_CONFIG_RB_MAP_0                           = 0x0,
++	RASTER_CONFIG_RB_MAP_1                           = 0x1,
++	RASTER_CONFIG_RB_MAP_2                           = 0x2,
++	RASTER_CONFIG_RB_MAP_3                           = 0x3,
++} RbMap;
++typedef enum CSDATA_TYPE {
++	CSDATA_TYPE_TG                                   = 0x0,
++	CSDATA_TYPE_STATE                                = 0x1,
++	CSDATA_TYPE_EVENT                                = 0x2,
++	CSDATA_TYPE_PRIVATE                              = 0x3,
++} CSDATA_TYPE;
++#define CSDATA_TYPE_WIDTH                         0x2
++#define CSDATA_ADDR_WIDTH                         0x7
++#define CSDATA_DATA_WIDTH                         0x20
++typedef enum SPI_SAMPLE_CNTL {
++	CENTROIDS_ONLY                                   = 0x0,
++	CENTERS_ONLY                                     = 0x1,
++	CENTROIDS_AND_CENTERS                            = 0x2,
++	UNDEF                                            = 0x3,
++} SPI_SAMPLE_CNTL;
++typedef enum SPI_FOG_MODE {
++	SPI_FOG_NONE                                     = 0x0,
++	SPI_FOG_EXP                                      = 0x1,
++	SPI_FOG_EXP2                                     = 0x2,
++	SPI_FOG_LINEAR                                   = 0x3,
++} SPI_FOG_MODE;
++typedef enum SPI_PNT_SPRITE_OVERRIDE {
++	SPI_PNT_SPRITE_SEL_0                             = 0x0,
++	SPI_PNT_SPRITE_SEL_1                             = 0x1,
++	SPI_PNT_SPRITE_SEL_S                             = 0x2,
++	SPI_PNT_SPRITE_SEL_T                             = 0x3,
++	SPI_PNT_SPRITE_SEL_NONE                          = 0x4,
++} SPI_PNT_SPRITE_OVERRIDE;
++typedef enum SPI_PERFCNT_SEL {
++	SPI_PERF_VS_WINDOW_VALID                         = 0x0,
++	SPI_PERF_VS_BUSY                                 = 0x1,
++	SPI_PERF_VS_FIRST_WAVE                           = 0x2,
++	SPI_PERF_VS_LAST_WAVE                            = 0x3,
++	SPI_PERF_VS_LSHS_DEALLOC                         = 0x4,
++	SPI_PERF_VS_PC_STALL                             = 0x5,
++	SPI_PERF_VS_POS0_STALL                           = 0x6,
++	SPI_PERF_VS_POS1_STALL                           = 0x7,
++	SPI_PERF_VS_CRAWLER_STALL                        = 0x8,
++	SPI_PERF_VS_EVENT_WAVE                           = 0x9,
++	SPI_PERF_VS_WAVE                                 = 0xa,
++	SPI_PERF_VS_PERS_UPD_FULL0                       = 0xb,
++	SPI_PERF_VS_PERS_UPD_FULL1                       = 0xc,
++	SPI_PERF_VS_LATE_ALLOC_FULL                      = 0xd,
++	SPI_PERF_VS_FIRST_SUBGRP                         = 0xe,
++	SPI_PERF_VS_LAST_SUBGRP                          = 0xf,
++	SPI_PERF_GS_WINDOW_VALID                         = 0x10,
++	SPI_PERF_GS_BUSY                                 = 0x11,
++	SPI_PERF_GS_CRAWLER_STALL                        = 0x12,
++	SPI_PERF_GS_EVENT_WAVE                           = 0x13,
++	SPI_PERF_GS_WAVE                                 = 0x14,
++	SPI_PERF_GS_PERS_UPD_FULL0                       = 0x15,
++	SPI_PERF_GS_PERS_UPD_FULL1                       = 0x16,
++	SPI_PERF_GS_FIRST_SUBGRP                         = 0x17,
++	SPI_PERF_GS_LAST_SUBGRP                          = 0x18,
++	SPI_PERF_ES_WINDOW_VALID                         = 0x19,
++	SPI_PERF_ES_BUSY                                 = 0x1a,
++	SPI_PERF_ES_CRAWLER_STALL                        = 0x1b,
++	SPI_PERF_ES_FIRST_WAVE                           = 0x1c,
++	SPI_PERF_ES_LAST_WAVE                            = 0x1d,
++	SPI_PERF_ES_LSHS_DEALLOC                         = 0x1e,
++	SPI_PERF_ES_EVENT_WAVE                           = 0x1f,
++	SPI_PERF_ES_WAVE                                 = 0x20,
++	SPI_PERF_ES_PERS_UPD_FULL0                       = 0x21,
++	SPI_PERF_ES_PERS_UPD_FULL1                       = 0x22,
++	SPI_PERF_ES_FIRST_SUBGRP                         = 0x23,
++	SPI_PERF_ES_LAST_SUBGRP                          = 0x24,
++	SPI_PERF_HS_WINDOW_VALID                         = 0x25,
++	SPI_PERF_HS_BUSY                                 = 0x26,
++	SPI_PERF_HS_CRAWLER_STALL                        = 0x27,
++	SPI_PERF_HS_FIRST_WAVE                           = 0x28,
++	SPI_PERF_HS_LAST_WAVE                            = 0x29,
++	SPI_PERF_HS_LSHS_DEALLOC                         = 0x2a,
++	SPI_PERF_HS_EVENT_WAVE                           = 0x2b,
++	SPI_PERF_HS_WAVE                                 = 0x2c,
++	SPI_PERF_HS_PERS_UPD_FULL0                       = 0x2d,
++	SPI_PERF_HS_PERS_UPD_FULL1                       = 0x2e,
++	SPI_PERF_LS_WINDOW_VALID                         = 0x2f,
++	SPI_PERF_LS_BUSY                                 = 0x30,
++	SPI_PERF_LS_CRAWLER_STALL                        = 0x31,
++	SPI_PERF_LS_FIRST_WAVE                           = 0x32,
++	SPI_PERF_LS_LAST_WAVE                            = 0x33,
++	SPI_PERF_OFFCHIP_LDS_STALL_LS                    = 0x34,
++	SPI_PERF_LS_EVENT_WAVE                           = 0x35,
++	SPI_PERF_LS_WAVE                                 = 0x36,
++	SPI_PERF_LS_PERS_UPD_FULL0                       = 0x37,
++	SPI_PERF_LS_PERS_UPD_FULL1                       = 0x38,
++	SPI_PERF_CSG_WINDOW_VALID                        = 0x39,
++	SPI_PERF_CSG_BUSY                                = 0x3a,
++	SPI_PERF_CSG_NUM_THREADGROUPS                    = 0x3b,
++	SPI_PERF_CSG_CRAWLER_STALL                       = 0x3c,
++	SPI_PERF_CSG_EVENT_WAVE                          = 0x3d,
++	SPI_PERF_CSG_WAVE                                = 0x3e,
++	SPI_PERF_CSN_WINDOW_VALID                        = 0x3f,
++	SPI_PERF_CSN_BUSY                                = 0x40,
++	SPI_PERF_CSN_NUM_THREADGROUPS                    = 0x41,
++	SPI_PERF_CSN_CRAWLER_STALL                       = 0x42,
++	SPI_PERF_CSN_EVENT_WAVE                          = 0x43,
++	SPI_PERF_CSN_WAVE                                = 0x44,
++	SPI_PERF_PS_CTL_WINDOW_VALID                     = 0x45,
++	SPI_PERF_PS_CTL_BUSY                             = 0x46,
++	SPI_PERF_PS_CTL_ACTIVE                           = 0x47,
++	SPI_PERF_PS_CTL_DEALLOC_BIN0                     = 0x48,
++	SPI_PERF_PS_CTL_FPOS_BIN1_STALL                  = 0x49,
++	SPI_PERF_PS_CTL_EVENT_WAVE                       = 0x4a,
++	SPI_PERF_PS_CTL_WAVE                             = 0x4b,
++	SPI_PERF_PS_CTL_OPT_WAVE                         = 0x4c,
++	SPI_PERF_PS_CTL_PASS_BIN0                        = 0x4d,
++	SPI_PERF_PS_CTL_PASS_BIN1                        = 0x4e,
++	SPI_PERF_PS_CTL_FPOS_BIN2                        = 0x4f,
++	SPI_PERF_PS_CTL_PRIM_BIN0                        = 0x50,
++	SPI_PERF_PS_CTL_PRIM_BIN1                        = 0x51,
++	SPI_PERF_PS_CTL_CNF_BIN2                         = 0x52,
++	SPI_PERF_PS_CTL_CNF_BIN3                         = 0x53,
++	SPI_PERF_PS_CTL_CRAWLER_STALL                    = 0x54,
++	SPI_PERF_PS_CTL_LDS_RES_FULL                     = 0x55,
++	SPI_PERF_PS_PERS_UPD_FULL0                       = 0x56,
++	SPI_PERF_PS_PERS_UPD_FULL1                       = 0x57,
++	SPI_PERF_PIX_ALLOC_PEND_CNT                      = 0x58,
++	SPI_PERF_PIX_ALLOC_SCB_STALL                     = 0x59,
++	SPI_PERF_PIX_ALLOC_DB0_STALL                     = 0x5a,
++	SPI_PERF_PIX_ALLOC_DB1_STALL                     = 0x5b,
++	SPI_PERF_PIX_ALLOC_DB2_STALL                     = 0x5c,
++	SPI_PERF_PIX_ALLOC_DB3_STALL                     = 0x5d,
++	SPI_PERF_LDS0_PC_VALID                           = 0x5e,
++	SPI_PERF_LDS1_PC_VALID                           = 0x5f,
++	SPI_PERF_RA_PIPE_REQ_BIN2                        = 0x60,
++	SPI_PERF_RA_TASK_REQ_BIN3                        = 0x61,
++	SPI_PERF_RA_WR_CTL_FULL                          = 0x62,
++	SPI_PERF_RA_REQ_NO_ALLOC                         = 0x63,
++	SPI_PERF_RA_REQ_NO_ALLOC_PS                      = 0x64,
++	SPI_PERF_RA_REQ_NO_ALLOC_VS                      = 0x65,
++	SPI_PERF_RA_REQ_NO_ALLOC_GS                      = 0x66,
++	SPI_PERF_RA_REQ_NO_ALLOC_ES                      = 0x67,
++	SPI_PERF_RA_REQ_NO_ALLOC_HS                      = 0x68,
++	SPI_PERF_RA_REQ_NO_ALLOC_LS                      = 0x69,
++	SPI_PERF_RA_REQ_NO_ALLOC_CSG                     = 0x6a,
++	SPI_PERF_RA_REQ_NO_ALLOC_CSN                     = 0x6b,
++	SPI_PERF_RA_RES_STALL_PS                         = 0x6c,
++	SPI_PERF_RA_RES_STALL_VS                         = 0x6d,
++	SPI_PERF_RA_RES_STALL_GS                         = 0x6e,
++	SPI_PERF_RA_RES_STALL_ES                         = 0x6f,
++	SPI_PERF_RA_RES_STALL_HS                         = 0x70,
++	SPI_PERF_RA_RES_STALL_LS                         = 0x71,
++	SPI_PERF_RA_RES_STALL_CSG                        = 0x72,
++	SPI_PERF_RA_RES_STALL_CSN                        = 0x73,
++	SPI_PERF_RA_TMP_STALL_PS                         = 0x74,
++	SPI_PERF_RA_TMP_STALL_VS                         = 0x75,
++	SPI_PERF_RA_TMP_STALL_GS                         = 0x76,
++	SPI_PERF_RA_TMP_STALL_ES                         = 0x77,
++	SPI_PERF_RA_TMP_STALL_HS                         = 0x78,
++	SPI_PERF_RA_TMP_STALL_LS                         = 0x79,
++	SPI_PERF_RA_TMP_STALL_CSG                        = 0x7a,
++	SPI_PERF_RA_TMP_STALL_CSN                        = 0x7b,
++	SPI_PERF_RA_WAVE_SIMD_FULL_PS                    = 0x7c,
++	SPI_PERF_RA_WAVE_SIMD_FULL_VS                    = 0x7d,
++	SPI_PERF_RA_WAVE_SIMD_FULL_GS                    = 0x7e,
++	SPI_PERF_RA_WAVE_SIMD_FULL_ES                    = 0x7f,
++	SPI_PERF_RA_WAVE_SIMD_FULL_HS                    = 0x80,
++	SPI_PERF_RA_WAVE_SIMD_FULL_LS                    = 0x81,
++	SPI_PERF_RA_WAVE_SIMD_FULL_CSG                   = 0x82,
++	SPI_PERF_RA_WAVE_SIMD_FULL_CSN                   = 0x83,
++	SPI_PERF_RA_VGPR_SIMD_FULL_PS                    = 0x84,
++	SPI_PERF_RA_VGPR_SIMD_FULL_VS                    = 0x85,
++	SPI_PERF_RA_VGPR_SIMD_FULL_GS                    = 0x86,
++	SPI_PERF_RA_VGPR_SIMD_FULL_ES                    = 0x87,
++	SPI_PERF_RA_VGPR_SIMD_FULL_HS                    = 0x88,
++	SPI_PERF_RA_VGPR_SIMD_FULL_LS                    = 0x89,
++	SPI_PERF_RA_VGPR_SIMD_FULL_CSG                   = 0x8a,
++	SPI_PERF_RA_VGPR_SIMD_FULL_CSN                   = 0x8b,
++	SPI_PERF_RA_SGPR_SIMD_FULL_PS                    = 0x8c,
++	SPI_PERF_RA_SGPR_SIMD_FULL_VS                    = 0x8d,
++	SPI_PERF_RA_SGPR_SIMD_FULL_GS                    = 0x8e,
++	SPI_PERF_RA_SGPR_SIMD_FULL_ES                    = 0x8f,
++	SPI_PERF_RA_SGPR_SIMD_FULL_HS                    = 0x90,
++	SPI_PERF_RA_SGPR_SIMD_FULL_LS                    = 0x91,
++	SPI_PERF_RA_SGPR_SIMD_FULL_CSG                   = 0x92,
++	SPI_PERF_RA_SGPR_SIMD_FULL_CSN                   = 0x93,
++	SPI_PERF_RA_LDS_CU_FULL_PS                       = 0x94,
++	SPI_PERF_RA_LDS_CU_FULL_LS                       = 0x95,
++	SPI_PERF_RA_LDS_CU_FULL_ES                       = 0x96,
++	SPI_PERF_RA_LDS_CU_FULL_CSG                      = 0x97,
++	SPI_PERF_RA_LDS_CU_FULL_CSN                      = 0x98,
++	SPI_PERF_RA_BAR_CU_FULL_HS                       = 0x99,
++	SPI_PERF_RA_BAR_CU_FULL_CSG                      = 0x9a,
++	SPI_PERF_RA_BAR_CU_FULL_CSN                      = 0x9b,
++	SPI_PERF_RA_BULKY_CU_FULL_CSG                    = 0x9c,
++	SPI_PERF_RA_BULKY_CU_FULL_CSN                    = 0x9d,
++	SPI_PERF_RA_TGLIM_CU_FULL_CSG                    = 0x9e,
++	SPI_PERF_RA_TGLIM_CU_FULL_CSN                    = 0x9f,
++	SPI_PERF_RA_WVLIM_STALL_PS                       = 0xa0,
++	SPI_PERF_RA_WVLIM_STALL_VS                       = 0xa1,
++	SPI_PERF_RA_WVLIM_STALL_GS                       = 0xa2,
++	SPI_PERF_RA_WVLIM_STALL_ES                       = 0xa3,
++	SPI_PERF_RA_WVLIM_STALL_HS                       = 0xa4,
++	SPI_PERF_RA_WVLIM_STALL_LS                       = 0xa5,
++	SPI_PERF_RA_WVLIM_STALL_CSG                      = 0xa6,
++	SPI_PERF_RA_WVLIM_STALL_CSN                      = 0xa7,
++	SPI_PERF_RA_PS_LOCK                              = 0xa8,
++	SPI_PERF_RA_VS_LOCK                              = 0xa9,
++	SPI_PERF_RA_GS_LOCK                              = 0xaa,
++	SPI_PERF_RA_ES_LOCK                              = 0xab,
++	SPI_PERF_RA_HS_LOCK                              = 0xac,
++	SPI_PERF_RA_LS_LOCK                              = 0xad,
++	SPI_PERF_RA_CSG_LOCK                             = 0xae,
++	SPI_PERF_RA_CSN_LOCK                             = 0xaf,
++	SPI_PERF_RA_RSV_UPD                              = 0xb0,
++	SPI_PERF_EXP_ARB_COL_CNT                         = 0xb1,
++	SPI_PERF_EXP_ARB_PAR_CNT                         = 0xb2,
++	SPI_PERF_EXP_ARB_POS_CNT                         = 0xb3,
++	SPI_PERF_EXP_ARB_GDS_CNT                         = 0xb4,
++	SPI_PERF_CLKGATE_BUSY_STALL                      = 0xb5,
++	SPI_PERF_CLKGATE_ACTIVE_STALL                    = 0xb6,
++	SPI_PERF_CLKGATE_ALL_CLOCKS_ON                   = 0xb7,
++	SPI_PERF_CLKGATE_CGTT_DYN_ON                     = 0xb8,
++	SPI_PERF_CLKGATE_CGTT_REG_ON                     = 0xb9,
++} SPI_PERFCNT_SEL;
++typedef enum SPI_SHADER_FORMAT {
++	SPI_SHADER_NONE                                  = 0x0,
++	SPI_SHADER_1COMP                                 = 0x1,
++	SPI_SHADER_2COMP                                 = 0x2,
++	SPI_SHADER_4COMPRESS                             = 0x3,
++	SPI_SHADER_4COMP                                 = 0x4,
++} SPI_SHADER_FORMAT;
++typedef enum SPI_SHADER_EX_FORMAT {
++	SPI_SHADER_ZERO                                  = 0x0,
++	SPI_SHADER_32_R                                  = 0x1,
++	SPI_SHADER_32_GR                                 = 0x2,
++	SPI_SHADER_32_AR                                 = 0x3,
++	SPI_SHADER_FP16_ABGR                             = 0x4,
++	SPI_SHADER_UNORM16_ABGR                          = 0x5,
++	SPI_SHADER_SNORM16_ABGR                          = 0x6,
++	SPI_SHADER_UINT16_ABGR                           = 0x7,
++	SPI_SHADER_SINT16_ABGR                           = 0x8,
++	SPI_SHADER_32_ABGR                               = 0x9,
++} SPI_SHADER_EX_FORMAT;
++typedef enum CLKGATE_SM_MODE {
++	ON_SEQ                                           = 0x0,
++	OFF_SEQ                                          = 0x1,
++	PROG_SEQ                                         = 0x2,
++	READ_SEQ                                         = 0x3,
++	SM_MODE_RESERVED                                 = 0x4,
++} CLKGATE_SM_MODE;
++typedef enum CLKGATE_BASE_MODE {
++	MULT_8                                           = 0x0,
++	MULT_16                                          = 0x1,
++} CLKGATE_BASE_MODE;
++typedef enum SQ_TEX_CLAMP {
++	SQ_TEX_WRAP                                      = 0x0,
++	SQ_TEX_MIRROR                                    = 0x1,
++	SQ_TEX_CLAMP_LAST_TEXEL                          = 0x2,
++	SQ_TEX_MIRROR_ONCE_LAST_TEXEL                    = 0x3,
++	SQ_TEX_CLAMP_HALF_BORDER                         = 0x4,
++	SQ_TEX_MIRROR_ONCE_HALF_BORDER                   = 0x5,
++	SQ_TEX_CLAMP_BORDER                              = 0x6,
++	SQ_TEX_MIRROR_ONCE_BORDER                        = 0x7,
++} SQ_TEX_CLAMP;
++typedef enum SQ_TEX_XY_FILTER {
++	SQ_TEX_XY_FILTER_POINT                           = 0x0,
++	SQ_TEX_XY_FILTER_BILINEAR                        = 0x1,
++	SQ_TEX_XY_FILTER_ANISO_POINT                     = 0x2,
++	SQ_TEX_XY_FILTER_ANISO_BILINEAR                  = 0x3,
++} SQ_TEX_XY_FILTER;
++typedef enum SQ_TEX_Z_FILTER {
++	SQ_TEX_Z_FILTER_NONE                             = 0x0,
++	SQ_TEX_Z_FILTER_POINT                            = 0x1,
++	SQ_TEX_Z_FILTER_LINEAR                           = 0x2,
++} SQ_TEX_Z_FILTER;
++typedef enum SQ_TEX_MIP_FILTER {
++	SQ_TEX_MIP_FILTER_NONE                           = 0x0,
++	SQ_TEX_MIP_FILTER_POINT                          = 0x1,
++	SQ_TEX_MIP_FILTER_LINEAR                         = 0x2,
++} SQ_TEX_MIP_FILTER;
++typedef enum SQ_TEX_ANISO_RATIO {
++	SQ_TEX_ANISO_RATIO_1                             = 0x0,
++	SQ_TEX_ANISO_RATIO_2                             = 0x1,
++	SQ_TEX_ANISO_RATIO_4                             = 0x2,
++	SQ_TEX_ANISO_RATIO_8                             = 0x3,
++	SQ_TEX_ANISO_RATIO_16                            = 0x4,
++} SQ_TEX_ANISO_RATIO;
++typedef enum SQ_TEX_DEPTH_COMPARE {
++	SQ_TEX_DEPTH_COMPARE_NEVER                       = 0x0,
++	SQ_TEX_DEPTH_COMPARE_LESS                        = 0x1,
++	SQ_TEX_DEPTH_COMPARE_EQUAL                       = 0x2,
++	SQ_TEX_DEPTH_COMPARE_LESSEQUAL                   = 0x3,
++	SQ_TEX_DEPTH_COMPARE_GREATER                     = 0x4,
++	SQ_TEX_DEPTH_COMPARE_NOTEQUAL                    = 0x5,
++	SQ_TEX_DEPTH_COMPARE_GREATEREQUAL                = 0x6,
++	SQ_TEX_DEPTH_COMPARE_ALWAYS                      = 0x7,
++} SQ_TEX_DEPTH_COMPARE;
++typedef enum SQ_TEX_BORDER_COLOR {
++	SQ_TEX_BORDER_COLOR_TRANS_BLACK                  = 0x0,
++	SQ_TEX_BORDER_COLOR_OPAQUE_BLACK                 = 0x1,
++	SQ_TEX_BORDER_COLOR_OPAQUE_WHITE                 = 0x2,
++	SQ_TEX_BORDER_COLOR_REGISTER                     = 0x3,
++} SQ_TEX_BORDER_COLOR;
++typedef enum SQ_RSRC_BUF_TYPE {
++	SQ_RSRC_BUF                                      = 0x0,
++	SQ_RSRC_BUF_RSVD_1                               = 0x1,
++	SQ_RSRC_BUF_RSVD_2                               = 0x2,
++	SQ_RSRC_BUF_RSVD_3                               = 0x3,
++} SQ_RSRC_BUF_TYPE;
++typedef enum SQ_RSRC_IMG_TYPE {
++	SQ_RSRC_IMG_RSVD_0                               = 0x0,
++	SQ_RSRC_IMG_RSVD_1                               = 0x1,
++	SQ_RSRC_IMG_RSVD_2                               = 0x2,
++	SQ_RSRC_IMG_RSVD_3                               = 0x3,
++	SQ_RSRC_IMG_RSVD_4                               = 0x4,
++	SQ_RSRC_IMG_RSVD_5                               = 0x5,
++	SQ_RSRC_IMG_RSVD_6                               = 0x6,
++	SQ_RSRC_IMG_RSVD_7                               = 0x7,
++	SQ_RSRC_IMG_1D                                   = 0x8,
++	SQ_RSRC_IMG_2D                                   = 0x9,
++	SQ_RSRC_IMG_3D                                   = 0xa,
++	SQ_RSRC_IMG_CUBE                                 = 0xb,
++	SQ_RSRC_IMG_1D_ARRAY                             = 0xc,
++	SQ_RSRC_IMG_2D_ARRAY                             = 0xd,
++	SQ_RSRC_IMG_2D_MSAA                              = 0xe,
++	SQ_RSRC_IMG_2D_MSAA_ARRAY                        = 0xf,
++} SQ_RSRC_IMG_TYPE;
++typedef enum SQ_RSRC_FLAT_TYPE {
++	SQ_RSRC_FLAT_RSVD_0                              = 0x0,
++	SQ_RSRC_FLAT                                     = 0x1,
++	SQ_RSRC_FLAT_RSVD_2                              = 0x2,
++	SQ_RSRC_FLAT_RSVD_3                              = 0x3,
++} SQ_RSRC_FLAT_TYPE;
++typedef enum SQ_IMG_FILTER_TYPE {
++	SQ_IMG_FILTER_MODE_BLEND                         = 0x0,
++	SQ_IMG_FILTER_MODE_MIN                           = 0x1,
++	SQ_IMG_FILTER_MODE_MAX                           = 0x2,
++} SQ_IMG_FILTER_TYPE;
++typedef enum SQ_SEL_XYZW01 {
++	SQ_SEL_0                                         = 0x0,
++	SQ_SEL_1                                         = 0x1,
++	SQ_SEL_RESERVED_0                                = 0x2,
++	SQ_SEL_RESERVED_1                                = 0x3,
++	SQ_SEL_X                                         = 0x4,
++	SQ_SEL_Y                                         = 0x5,
++	SQ_SEL_Z                                         = 0x6,
++	SQ_SEL_W                                         = 0x7,
++} SQ_SEL_XYZW01;
++typedef enum SQ_WAVE_TYPE {
++	SQ_WAVE_TYPE_PS                                  = 0x0,
++	SQ_WAVE_TYPE_VS                                  = 0x1,
++	SQ_WAVE_TYPE_GS                                  = 0x2,
++	SQ_WAVE_TYPE_ES                                  = 0x3,
++	SQ_WAVE_TYPE_HS                                  = 0x4,
++	SQ_WAVE_TYPE_LS                                  = 0x5,
++	SQ_WAVE_TYPE_CS                                  = 0x6,
++	SQ_WAVE_TYPE_PS1                                 = 0x7,
++} SQ_WAVE_TYPE;
++typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
++	SQ_THREAD_TRACE_TOKEN_MISC                       = 0x0,
++	SQ_THREAD_TRACE_TOKEN_TIMESTAMP                  = 0x1,
++	SQ_THREAD_TRACE_TOKEN_REG                        = 0x2,
++	SQ_THREAD_TRACE_TOKEN_WAVE_START                 = 0x3,
++	SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC                 = 0x4,
++	SQ_THREAD_TRACE_TOKEN_REG_CSPRIV                 = 0x5,
++	SQ_THREAD_TRACE_TOKEN_WAVE_END                   = 0x6,
++	SQ_THREAD_TRACE_TOKEN_EVENT                      = 0x7,
++	SQ_THREAD_TRACE_TOKEN_EVENT_CS                   = 0x8,
++	SQ_THREAD_TRACE_TOKEN_EVENT_GFX1                 = 0x9,
++	SQ_THREAD_TRACE_TOKEN_INST                       = 0xa,
++	SQ_THREAD_TRACE_TOKEN_INST_PC                    = 0xb,
++	SQ_THREAD_TRACE_TOKEN_INST_USERDATA              = 0xc,
++	SQ_THREAD_TRACE_TOKEN_ISSUE                      = 0xd,
++	SQ_THREAD_TRACE_TOKEN_PERF                       = 0xe,
++	SQ_THREAD_TRACE_TOKEN_REG_CS                     = 0xf,
++} SQ_THREAD_TRACE_TOKEN_TYPE;
++typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
++	SQ_THREAD_TRACE_MISC_TOKEN_TIME                  = 0x0,
++	SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET            = 0x1,
++	SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST           = 0x2,
++	SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC             = 0x3,
++	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN    = 0x4,
++	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END      = 0x5,
++} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
++typedef enum SQ_THREAD_TRACE_INST_TYPE {
++	SQ_THREAD_TRACE_INST_TYPE_SMEM                   = 0x0,
++	SQ_THREAD_TRACE_INST_TYPE_SALU                   = 0x1,
++	SQ_THREAD_TRACE_INST_TYPE_VMEM_RD                = 0x2,
++	SQ_THREAD_TRACE_INST_TYPE_VMEM_WR                = 0x3,
++	SQ_THREAD_TRACE_INST_TYPE_FLAT_WR                = 0x4,
++	SQ_THREAD_TRACE_INST_TYPE_VALU                   = 0x5,
++	SQ_THREAD_TRACE_INST_TYPE_LDS                    = 0x6,
++	SQ_THREAD_TRACE_INST_TYPE_PC                     = 0x7,
++	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS             = 0x8,
++	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX             = 0x9,
++	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL         = 0xa,
++	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS         = 0xb,
++	SQ_THREAD_TRACE_INST_TYPE_JUMP                   = 0xc,
++	SQ_THREAD_TRACE_INST_TYPE_NEXT                   = 0xd,
++	SQ_THREAD_TRACE_INST_TYPE_FLAT_RD                = 0xe,
++	SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG              = 0xf,
++} SQ_THREAD_TRACE_INST_TYPE;
++typedef enum SQ_THREAD_TRACE_REG_TYPE {
++	SQ_THREAD_TRACE_REG_TYPE_EVENT                   = 0x0,
++	SQ_THREAD_TRACE_REG_TYPE_DRAW                    = 0x1,
++	SQ_THREAD_TRACE_REG_TYPE_DISPATCH                = 0x2,
++	SQ_THREAD_TRACE_REG_TYPE_USERDATA                = 0x3,
++	SQ_THREAD_TRACE_REG_TYPE_MARKER                  = 0x4,
++	SQ_THREAD_TRACE_REG_TYPE_GFXDEC                  = 0x5,
++	SQ_THREAD_TRACE_REG_TYPE_SHDEC                   = 0x6,
++	SQ_THREAD_TRACE_REG_TYPE_OTHER                   = 0x7,
++} SQ_THREAD_TRACE_REG_TYPE;
++typedef enum SQ_THREAD_TRACE_REG_OP {
++	SQ_THREAD_TRACE_REG_OP_READ                      = 0x0,
++	SQ_THREAD_TRACE_REG_OP_WRITE                     = 0x1,
++} SQ_THREAD_TRACE_REG_OP;
++typedef enum SQ_THREAD_TRACE_MODE_SEL {
++	SQ_THREAD_TRACE_MODE_OFF                         = 0x0,
++	SQ_THREAD_TRACE_MODE_ON                          = 0x1,
++	SQ_THREAD_TRACE_MODE_RANDOM                      = 0x2,
++} SQ_THREAD_TRACE_MODE_SEL;
++typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
++	SQ_THREAD_TRACE_CAPTURE_MODE_ALL                 = 0x0,
++	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT              = 0x1,
++	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL       = 0x2,
++} SQ_THREAD_TRACE_CAPTURE_MODE;
++typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
++	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE                = 0x0,
++	SQ_THREAD_TRACE_VM_ID_MASK_ALL                   = 0x1,
++	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL         = 0x2,
++} SQ_THREAD_TRACE_VM_ID_MASK;
++typedef enum SQ_THREAD_TRACE_WAVE_MASK {
++	SQ_THREAD_TRACE_WAVE_MASK_NONE                   = 0x0,
++	SQ_THREAD_TRACE_WAVE_MASK_ALL                    = 0x1,
++	SQ_THREAD_TRACE_WAVE_MASK_1_2                    = 0x2,
++	SQ_THREAD_TRACE_WAVE_MASK_1_4                    = 0x3,
++	SQ_THREAD_TRACE_WAVE_MASK_1_8                    = 0x4,
++	SQ_THREAD_TRACE_WAVE_MASK_1_16                   = 0x5,
++	SQ_THREAD_TRACE_WAVE_MASK_1_32                   = 0x6,
++	SQ_THREAD_TRACE_WAVE_MASK_1_64                   = 0x7,
++} SQ_THREAD_TRACE_WAVE_MASK;
++typedef enum SQ_THREAD_TRACE_ISSUE {
++	SQ_THREAD_TRACE_ISSUE_NULL                       = 0x0,
++	SQ_THREAD_TRACE_ISSUE_STALL                      = 0x1,
++	SQ_THREAD_TRACE_ISSUE_INST                       = 0x2,
++	SQ_THREAD_TRACE_ISSUE_IMMED                      = 0x3,
++} SQ_THREAD_TRACE_ISSUE;
++typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
++	SQ_THREAD_TRACE_ISSUE_MASK_ALL                   = 0x0,
++	SQ_THREAD_TRACE_ISSUE_MASK_STALLED               = 0x1,
++	SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED     = 0x2,
++	SQ_THREAD_TRACE_ISSUE_MASK_IMMED                 = 0x3,
++} SQ_THREAD_TRACE_ISSUE_MASK;
++typedef enum SQ_PERF_SEL {
++	SQ_PERF_SEL_NONE                                 = 0x0,
++	SQ_PERF_SEL_ACCUM_PREV                           = 0x1,
++	SQ_PERF_SEL_CYCLES                               = 0x2,
++	SQ_PERF_SEL_BUSY_CYCLES                          = 0x3,
++	SQ_PERF_SEL_WAVES                                = 0x4,
++	SQ_PERF_SEL_LEVEL_WAVES                          = 0x5,
++	SQ_PERF_SEL_WAVES_EQ_64                          = 0x6,
++	SQ_PERF_SEL_WAVES_LT_64                          = 0x7,
++	SQ_PERF_SEL_WAVES_LT_48                          = 0x8,
++	SQ_PERF_SEL_WAVES_LT_32                          = 0x9,
++	SQ_PERF_SEL_WAVES_LT_16                          = 0xa,
++	SQ_PERF_SEL_WAVES_CU                             = 0xb,
++	SQ_PERF_SEL_LEVEL_WAVES_CU                       = 0xc,
++	SQ_PERF_SEL_BUSY_CU_CYCLES                       = 0xd,
++	SQ_PERF_SEL_ITEMS                                = 0xe,
++	SQ_PERF_SEL_QUADS                                = 0xf,
++	SQ_PERF_SEL_EVENTS                               = 0x10,
++	SQ_PERF_SEL_SURF_SYNCS                           = 0x11,
++	SQ_PERF_SEL_TTRACE_REQS                          = 0x12,
++	SQ_PERF_SEL_TTRACE_INFLIGHT_REQS                 = 0x13,
++	SQ_PERF_SEL_TTRACE_STALL                         = 0x14,
++	SQ_PERF_SEL_MSG_CNTR                             = 0x15,
++	SQ_PERF_SEL_MSG_PERF                             = 0x16,
++	SQ_PERF_SEL_MSG_GSCNT                            = 0x17,
++	SQ_PERF_SEL_MSG_INTERRUPT                        = 0x18,
++	SQ_PERF_SEL_INSTS                                = 0x19,
++	SQ_PERF_SEL_INSTS_VALU                           = 0x1a,
++	SQ_PERF_SEL_INSTS_VMEM_WR                        = 0x1b,
++	SQ_PERF_SEL_INSTS_VMEM_RD                        = 0x1c,
++	SQ_PERF_SEL_INSTS_VMEM                           = 0x1d,
++	SQ_PERF_SEL_INSTS_SALU                           = 0x1e,
++	SQ_PERF_SEL_INSTS_SMEM                           = 0x1f,
++	SQ_PERF_SEL_INSTS_FLAT                           = 0x20,
++	SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY                  = 0x21,
++	SQ_PERF_SEL_INSTS_LDS                            = 0x22,
++	SQ_PERF_SEL_INSTS_GDS                            = 0x23,
++	SQ_PERF_SEL_INSTS_EXP                            = 0x24,
++	SQ_PERF_SEL_INSTS_EXP_GDS                        = 0x25,
++	SQ_PERF_SEL_INSTS_BRANCH                         = 0x26,
++	SQ_PERF_SEL_INSTS_SENDMSG                        = 0x27,
++	SQ_PERF_SEL_INSTS_VSKIPPED                       = 0x28,
++	SQ_PERF_SEL_INST_LEVEL_VMEM                      = 0x29,
++	SQ_PERF_SEL_INST_LEVEL_SMEM                      = 0x2a,
++	SQ_PERF_SEL_INST_LEVEL_LDS                       = 0x2b,
++	SQ_PERF_SEL_INST_LEVEL_GDS                       = 0x2c,
++	SQ_PERF_SEL_INST_LEVEL_EXP                       = 0x2d,
++	SQ_PERF_SEL_WAVE_CYCLES                          = 0x2e,
++	SQ_PERF_SEL_WAVE_READY                           = 0x2f,
++	SQ_PERF_SEL_WAIT_CNT_VM                          = 0x30,
++	SQ_PERF_SEL_WAIT_CNT_LGKM                        = 0x31,
++	SQ_PERF_SEL_WAIT_CNT_EXP                         = 0x32,
++	SQ_PERF_SEL_WAIT_CNT_ANY                         = 0x33,
++	SQ_PERF_SEL_WAIT_BARRIER                         = 0x34,
++	SQ_PERF_SEL_WAIT_EXP_ALLOC                       = 0x35,
++	SQ_PERF_SEL_WAIT_SLEEP                           = 0x36,
++	SQ_PERF_SEL_WAIT_OTHER                           = 0x37,
++	SQ_PERF_SEL_WAIT_ANY                             = 0x38,
++	SQ_PERF_SEL_WAIT_TTRACE                          = 0x39,
++	SQ_PERF_SEL_WAIT_IFETCH                          = 0x3a,
++	SQ_PERF_SEL_WAIT_INST_VMEM                       = 0x3b,
++	SQ_PERF_SEL_WAIT_INST_SCA                        = 0x3c,
++	SQ_PERF_SEL_WAIT_INST_LDS                        = 0x3d,
++	SQ_PERF_SEL_WAIT_INST_VALU                       = 0x3e,
++	SQ_PERF_SEL_WAIT_INST_EXP_GDS                    = 0x3f,
++	SQ_PERF_SEL_WAIT_INST_MISC                       = 0x40,
++	SQ_PERF_SEL_WAIT_INST_FLAT                       = 0x41,
++	SQ_PERF_SEL_ACTIVE_INST_ANY                      = 0x42,
++	SQ_PERF_SEL_ACTIVE_INST_VMEM                     = 0x43,
++	SQ_PERF_SEL_ACTIVE_INST_LDS                      = 0x44,
++	SQ_PERF_SEL_ACTIVE_INST_VALU                     = 0x45,
++	SQ_PERF_SEL_ACTIVE_INST_SCA                      = 0x46,
++	SQ_PERF_SEL_ACTIVE_INST_EXP_GDS                  = 0x47,
++	SQ_PERF_SEL_ACTIVE_INST_MISC                     = 0x48,
++	SQ_PERF_SEL_ACTIVE_INST_FLAT                     = 0x49,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_WR                  = 0x4a,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_RD                  = 0x4b,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR                = 0x4c,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_DATA                = 0x4d,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_CMD                 = 0x4e,
++	SQ_PERF_SEL_INST_CYCLES_VMEM                     = 0x4f,
++	SQ_PERF_SEL_INST_CYCLES_LDS                      = 0x50,
++	SQ_PERF_SEL_INST_CYCLES_VALU                     = 0x51,
++	SQ_PERF_SEL_INST_CYCLES_EXP                      = 0x52,
++	SQ_PERF_SEL_INST_CYCLES_GDS                      = 0x53,
++	SQ_PERF_SEL_INST_CYCLES_SCA                      = 0x54,
++	SQ_PERF_SEL_INST_CYCLES_SMEM                     = 0x55,
++	SQ_PERF_SEL_INST_CYCLES_SALU                     = 0x56,
++	SQ_PERF_SEL_INST_CYCLES_EXP_GDS                  = 0x57,
++	SQ_PERF_SEL_INST_CYCLES_MISC                     = 0x58,
++	SQ_PERF_SEL_THREAD_CYCLES_VALU                   = 0x59,
++	SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX               = 0x5a,
++	SQ_PERF_SEL_IFETCH                               = 0x5b,
++	SQ_PERF_SEL_IFETCH_LEVEL                         = 0x5c,
++	SQ_PERF_SEL_CBRANCH_FORK                         = 0x5d,
++	SQ_PERF_SEL_CBRANCH_FORK_SPLIT                   = 0x5e,
++	SQ_PERF_SEL_VALU_LDS_DIRECT_RD                   = 0x5f,
++	SQ_PERF_SEL_VALU_LDS_INTERP_OP                   = 0x60,
++	SQ_PERF_SEL_LDS_BANK_CONFLICT                    = 0x61,
++	SQ_PERF_SEL_LDS_ADDR_CONFLICT                    = 0x62,
++	SQ_PERF_SEL_LDS_UNALIGNED_STALL                  = 0x63,
++	SQ_PERF_SEL_LDS_MEM_VIOLATIONS                   = 0x64,
++	SQ_PERF_SEL_LDS_ATOMIC_RETURN                    = 0x65,
++	SQ_PERF_SEL_LDS_IDX_ACTIVE                       = 0x66,
++	SQ_PERF_SEL_VALU_DEP_STALL                       = 0x67,
++	SQ_PERF_SEL_VALU_STARVE                          = 0x68,
++	SQ_PERF_SEL_EXP_REQ_FIFO_FULL                    = 0x69,
++	SQ_PERF_SEL_LDS_BACK2BACK_STALL                  = 0x6a,
++	SQ_PERF_SEL_LDS_DATA_FIFO_FULL                   = 0x6b,
++	SQ_PERF_SEL_LDS_CMD_FIFO_FULL                    = 0x6c,
++	SQ_PERF_SEL_VMEM_BACK2BACK_STALL                 = 0x6d,
++	SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL               = 0x6e,
++	SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL                = 0x6f,
++	SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY                = 0x70,
++	SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL              = 0x71,
++	SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL            = 0x72,
++	SQ_PERF_SEL_VALU_SRC_C_CONFLICT                  = 0x73,
++	SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT              = 0x74,
++	SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT              = 0x75,
++	SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT                 = 0x76,
++	SQ_PERF_SEL_LDS_SRC_CD_CONFLICT                  = 0x77,
++	SQ_PERF_SEL_SRC_CD_BUSY                          = 0x78,
++	SQ_PERF_SEL_PT_POWER_STALL                       = 0x79,
++	SQ_PERF_SEL_USER0                                = 0x7a,
++	SQ_PERF_SEL_USER1                                = 0x7b,
++	SQ_PERF_SEL_USER2                                = 0x7c,
++	SQ_PERF_SEL_USER3                                = 0x7d,
++	SQ_PERF_SEL_USER4                                = 0x7e,
++	SQ_PERF_SEL_USER5                                = 0x7f,
++	SQ_PERF_SEL_USER6                                = 0x80,
++	SQ_PERF_SEL_USER7                                = 0x81,
++	SQ_PERF_SEL_USER8                                = 0x82,
++	SQ_PERF_SEL_USER9                                = 0x83,
++	SQ_PERF_SEL_USER10                               = 0x84,
++	SQ_PERF_SEL_USER11                               = 0x85,
++	SQ_PERF_SEL_USER12                               = 0x86,
++	SQ_PERF_SEL_USER13                               = 0x87,
++	SQ_PERF_SEL_USER14                               = 0x88,
++	SQ_PERF_SEL_USER15                               = 0x89,
++	SQ_PERF_SEL_USER_LEVEL0                          = 0x8a,
++	SQ_PERF_SEL_USER_LEVEL1                          = 0x8b,
++	SQ_PERF_SEL_USER_LEVEL2                          = 0x8c,
++	SQ_PERF_SEL_USER_LEVEL3                          = 0x8d,
++	SQ_PERF_SEL_USER_LEVEL4                          = 0x8e,
++	SQ_PERF_SEL_USER_LEVEL5                          = 0x8f,
++	SQ_PERF_SEL_USER_LEVEL6                          = 0x90,
++	SQ_PERF_SEL_USER_LEVEL7                          = 0x91,
++	SQ_PERF_SEL_USER_LEVEL8                          = 0x92,
++	SQ_PERF_SEL_USER_LEVEL9                          = 0x93,
++	SQ_PERF_SEL_USER_LEVEL10                         = 0x94,
++	SQ_PERF_SEL_USER_LEVEL11                         = 0x95,
++	SQ_PERF_SEL_USER_LEVEL12                         = 0x96,
++	SQ_PERF_SEL_USER_LEVEL13                         = 0x97,
++	SQ_PERF_SEL_USER_LEVEL14                         = 0x98,
++	SQ_PERF_SEL_USER_LEVEL15                         = 0x99,
++	SQ_PERF_SEL_POWER_VALU                           = 0x9a,
++	SQ_PERF_SEL_POWER_VALU0                          = 0x9b,
++	SQ_PERF_SEL_POWER_VALU1                          = 0x9c,
++	SQ_PERF_SEL_POWER_VALU2                          = 0x9d,
++	SQ_PERF_SEL_POWER_GPR_RD                         = 0x9e,
++	SQ_PERF_SEL_POWER_GPR_WR                         = 0x9f,
++	SQ_PERF_SEL_POWER_LDS_BUSY                       = 0xa0,
++	SQ_PERF_SEL_POWER_ALU_BUSY                       = 0xa1,
++	SQ_PERF_SEL_POWER_TEX_BUSY                       = 0xa2,
++	SQ_PERF_SEL_ACCUM_PREV_HIRES                     = 0xa3,
++	SQ_PERF_SEL_DUMMY_LAST                           = 0xa7,
++	SQC_PERF_SEL_ICACHE_INPUT_VALID_READY            = 0xa8,
++	SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB           = 0xa9,
++	SQC_PERF_SEL_ICACHE_INPUT_VALIDB                 = 0xaa,
++	SQC_PERF_SEL_DCACHE_INPUT_VALID_READY            = 0xab,
++	SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB           = 0xac,
++	SQC_PERF_SEL_DCACHE_INPUT_VALIDB                 = 0xad,
++	SQC_PERF_SEL_TC_REQ                              = 0xae,
++	SQC_PERF_SEL_TC_INST_REQ                         = 0xaf,
++	SQC_PERF_SEL_TC_DATA_REQ                         = 0xb0,
++	SQC_PERF_SEL_TC_STALL                            = 0xb1,
++	SQC_PERF_SEL_TC_STARVE                           = 0xb2,
++	SQC_PERF_SEL_ICACHE_BUSY_CYCLES                  = 0xb3,
++	SQC_PERF_SEL_ICACHE_REQ                          = 0xb4,
++	SQC_PERF_SEL_ICACHE_HITS                         = 0xb5,
++	SQC_PERF_SEL_ICACHE_MISSES                       = 0xb6,
++	SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE             = 0xb7,
++	SQC_PERF_SEL_ICACHE_UNCACHED                     = 0xb8,
++	SQC_PERF_SEL_ICACHE_VOLATILE                     = 0xb9,
++	SQC_PERF_SEL_ICACHE_INVAL_INST                   = 0xba,
++	SQC_PERF_SEL_ICACHE_INVAL_ASYNC                  = 0xbb,
++	SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST          = 0xbc,
++	SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC         = 0xbd,
++	SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT     = 0xbe,
++	SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB      = 0xbf,
++	SQC_PERF_SEL_ICACHE_CACHE_STALLED                = 0xc0,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xc1,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX     = 0xc2,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xc3,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT     = 0xc4,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT           = 0xc5,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc6,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xc7,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xc8,
++	SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xc9,
++	SQC_PERF_SEL_DCACHE_BUSY_CYCLES                  = 0xca,
++	SQC_PERF_SEL_DCACHE_REQ                          = 0xcb,
++	SQC_PERF_SEL_DCACHE_HITS                         = 0xcc,
++	SQC_PERF_SEL_DCACHE_MISSES                       = 0xcd,
++	SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE             = 0xce,
++	SQC_PERF_SEL_DCACHE_UNCACHED                     = 0xcf,
++	SQC_PERF_SEL_DCACHE_VOLATILE                     = 0xd0,
++	SQC_PERF_SEL_DCACHE_INVAL_INST                   = 0xd1,
++	SQC_PERF_SEL_DCACHE_INVAL_ASYNC                  = 0xd2,
++	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST          = 0xd3,
++	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC         = 0xd4,
++	SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT     = 0xd5,
++	SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB      = 0xd6,
++	SQC_PERF_SEL_DCACHE_CACHE_STALLED                = 0xd7,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xd8,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX     = 0xd9,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xda,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT     = 0xdb,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT           = 0xdc,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xdd,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xde,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xdf,
++	SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xe0,
++	SQC_PERF_SEL_DCACHE_REQ_1                        = 0xe1,
++	SQC_PERF_SEL_DCACHE_REQ_2                        = 0xe2,
++	SQC_PERF_SEL_DCACHE_REQ_4                        = 0xe3,
++	SQC_PERF_SEL_DCACHE_REQ_8                        = 0xe4,
++	SQC_PERF_SEL_DCACHE_REQ_16                       = 0xe5,
++	SQC_PERF_SEL_DCACHE_REQ_TIME                     = 0xe6,
++	SQC_PERF_SEL_SQ_DCACHE_REQS                      = 0xe7,
++	SQC_PERF_SEL_DCACHE_FLAT_REQ                     = 0xe8,
++	SQC_PERF_SEL_DCACHE_NONFLAT_REQ                  = 0xe9,
++	SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL               = 0xea,
++	SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL                 = 0xeb,
++	SQC_PERF_SEL_ICACHE_POST_CC_LEVEL                = 0xec,
++	SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL            = 0xed,
++	SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL           = 0xee,
++	SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL               = 0xef,
++	SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL                 = 0xf0,
++	SQC_PERF_SEL_DCACHE_POST_CC_LEVEL                = 0xf1,
++	SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL            = 0xf2,
++	SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL           = 0xf3,
++	SQC_PERF_SEL_TC_INFLIGHT_LEVEL                   = 0xf4,
++	SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL            = 0xf5,
++	SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL            = 0xf6,
++	SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED = 0xf7,
++	SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED = 0xf8,
++	SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED = 0xf9,
++	SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED= 0xfa,
++	SQC_PERF_SEL_DUMMY_LAST                          = 0xfb,
++} SQ_PERF_SEL;
++typedef enum SQC_DATA_CACHE_POLICIES {
++	SQC_DATA_CACHE_POLICY_HIT_LRU                    = 0x0,
++	SQC_DATA_CACHE_POLICY_MISS_EVICT                 = 0x1,
++} SQC_DATA_CACHE_POLICIES;
++typedef enum SQ_CAC_POWER_SEL {
++	SQ_CAC_POWER_VALU                                = 0x0,
++	SQ_CAC_POWER_VALU0                               = 0x1,
++	SQ_CAC_POWER_VALU1                               = 0x2,
++	SQ_CAC_POWER_VALU2                               = 0x3,
++	SQ_CAC_POWER_GPR_RD                              = 0x4,
++	SQ_CAC_POWER_GPR_WR                              = 0x5,
++	SQ_CAC_POWER_LDS_BUSY                            = 0x6,
++	SQ_CAC_POWER_ALU_BUSY                            = 0x7,
++	SQ_CAC_POWER_TEX_BUSY                            = 0x8,
++} SQ_CAC_POWER_SEL;
++typedef enum SQ_IND_CMD_CMD {
++	SQ_IND_CMD_CMD_NULL                              = 0x0,
++	SQ_IND_CMD_CMD_HALT                              = 0x1,
++	SQ_IND_CMD_CMD_RESUME                            = 0x2,
++	SQ_IND_CMD_CMD_KILL                              = 0x3,
++	SQ_IND_CMD_CMD_DEBUG                             = 0x4,
++	SQ_IND_CMD_CMD_TRAP                              = 0x5,
++} SQ_IND_CMD_CMD;
++typedef enum SQ_IND_CMD_MODE {
++	SQ_IND_CMD_MODE_SINGLE                           = 0x0,
++	SQ_IND_CMD_MODE_BROADCAST                        = 0x1,
++	SQ_IND_CMD_MODE_BROADCAST_QUEUE                  = 0x2,
++	SQ_IND_CMD_MODE_BROADCAST_PIPE                   = 0x3,
++	SQ_IND_CMD_MODE_BROADCAST_ME                     = 0x4,
++} SQ_IND_CMD_MODE;
++typedef enum SQ_DED_INFO_SOURCE {
++	SQ_DED_INFO_SOURCE_INVALID                       = 0x0,
++	SQ_DED_INFO_SOURCE_INST                          = 0x1,
++	SQ_DED_INFO_SOURCE_SGPR                          = 0x2,
++	SQ_DED_INFO_SOURCE_VGPR                          = 0x3,
++	SQ_DED_INFO_SOURCE_LDS                           = 0x4,
++	SQ_DED_INFO_SOURCE_GDS                           = 0x5,
++	SQ_DED_INFO_SOURCE_TA                            = 0x6,
++} SQ_DED_INFO_SOURCE;
++typedef enum SQ_ROUND_MODE {
++	SQ_ROUND_NEAREST_EVEN                            = 0x0,
++	SQ_ROUND_PLUS_INFINITY                           = 0x1,
++	SQ_ROUND_MINUS_INFINITY                          = 0x2,
++	SQ_ROUND_TO_ZERO                                 = 0x3,
++} SQ_ROUND_MODE;
++typedef enum SQ_INTERRUPT_WORD_ENCODING {
++	SQ_INTERRUPT_WORD_ENCODING_AUTO                  = 0x0,
++	SQ_INTERRUPT_WORD_ENCODING_INST                  = 0x1,
++	SQ_INTERRUPT_WORD_ENCODING_ERROR                 = 0x2,
++} SQ_INTERRUPT_WORD_ENCODING;
++typedef enum ENUM_SQ_EXPORT_RAT_INST {
++	SQ_EXPORT_RAT_INST_NOP                           = 0x0,
++	SQ_EXPORT_RAT_INST_STORE_TYPED                   = 0x1,
++	SQ_EXPORT_RAT_INST_STORE_RAW                     = 0x2,
++	SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM             = 0x3,
++	SQ_EXPORT_RAT_INST_CMPXCHG_INT                   = 0x4,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FLT                   = 0x5,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM               = 0x6,
++	SQ_EXPORT_RAT_INST_ADD                           = 0x7,
++	SQ_EXPORT_RAT_INST_SUB                           = 0x8,
++	SQ_EXPORT_RAT_INST_RSUB                          = 0x9,
++	SQ_EXPORT_RAT_INST_MIN_INT                       = 0xa,
++	SQ_EXPORT_RAT_INST_MIN_UINT                      = 0xb,
++	SQ_EXPORT_RAT_INST_MAX_INT                       = 0xc,
++	SQ_EXPORT_RAT_INST_MAX_UINT                      = 0xd,
++	SQ_EXPORT_RAT_INST_AND                           = 0xe,
++	SQ_EXPORT_RAT_INST_OR                            = 0xf,
++	SQ_EXPORT_RAT_INST_XOR                           = 0x10,
++	SQ_EXPORT_RAT_INST_MSKOR                         = 0x11,
++	SQ_EXPORT_RAT_INST_INC_UINT                      = 0x12,
++	SQ_EXPORT_RAT_INST_DEC_UINT                      = 0x13,
++	SQ_EXPORT_RAT_INST_STORE_DWORD                   = 0x14,
++	SQ_EXPORT_RAT_INST_STORE_SHORT                   = 0x15,
++	SQ_EXPORT_RAT_INST_STORE_BYTE                    = 0x16,
++	SQ_EXPORT_RAT_INST_NOP_RTN                       = 0x20,
++	SQ_EXPORT_RAT_INST_XCHG_RTN                      = 0x22,
++	SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN              = 0x23,
++	SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN               = 0x24,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN               = 0x25,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN           = 0x26,
++	SQ_EXPORT_RAT_INST_ADD_RTN                       = 0x27,
++	SQ_EXPORT_RAT_INST_SUB_RTN                       = 0x28,
++	SQ_EXPORT_RAT_INST_RSUB_RTN                      = 0x29,
++	SQ_EXPORT_RAT_INST_MIN_INT_RTN                   = 0x2a,
++	SQ_EXPORT_RAT_INST_MIN_UINT_RTN                  = 0x2b,
++	SQ_EXPORT_RAT_INST_MAX_INT_RTN                   = 0x2c,
++	SQ_EXPORT_RAT_INST_MAX_UINT_RTN                  = 0x2d,
++	SQ_EXPORT_RAT_INST_AND_RTN                       = 0x2e,
++	SQ_EXPORT_RAT_INST_OR_RTN                        = 0x2f,
++	SQ_EXPORT_RAT_INST_XOR_RTN                       = 0x30,
++	SQ_EXPORT_RAT_INST_MSKOR_RTN                     = 0x31,
++	SQ_EXPORT_RAT_INST_INC_UINT_RTN                  = 0x32,
++	SQ_EXPORT_RAT_INST_DEC_UINT_RTN                  = 0x33,
++} ENUM_SQ_EXPORT_RAT_INST;
++typedef enum SQ_IBUF_ST {
++	SQ_IBUF_IB_IDLE                                  = 0x0,
++	SQ_IBUF_IB_INI_WAIT_GNT                          = 0x1,
++	SQ_IBUF_IB_INI_WAIT_DRET                         = 0x2,
++	SQ_IBUF_IB_LE_4DW                                = 0x3,
++	SQ_IBUF_IB_WAIT_DRET                             = 0x4,
++	SQ_IBUF_IB_EMPTY_WAIT_DRET                       = 0x5,
++	SQ_IBUF_IB_DRET                                  = 0x6,
++	SQ_IBUF_IB_EMPTY_WAIT_GNT                        = 0x7,
++} SQ_IBUF_ST;
++typedef enum SQ_INST_STR_ST {
++	SQ_INST_STR_IB_WAVE_NORML                        = 0x0,
++	SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV            = 0x1,
++	SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV             = 0x2,
++	SQ_INST_STR_IB_WAVE_INST_SKIP_AV                 = 0x3,
++	SQ_INST_STR_IB_WAVE_SETVSKIP_ST0                 = 0x4,
++	SQ_INST_STR_IB_WAVE_SETVSKIP_ST1                 = 0x5,
++	SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT               = 0x6,
++	SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT        = 0x7,
++} SQ_INST_STR_ST;
++typedef enum SQ_WAVE_IB_ECC_ST {
++	SQ_WAVE_IB_ECC_CLEAN                             = 0x0,
++	SQ_WAVE_IB_ECC_ERR_CONTINUE                      = 0x1,
++	SQ_WAVE_IB_ECC_ERR_HALT                          = 0x2,
++	SQ_WAVE_IB_ECC_WITH_ERR_MSG                      = 0x3,
++} SQ_WAVE_IB_ECC_ST;
++typedef enum SH_MEM_ALIGNMENT_MODE {
++	SH_MEM_ALIGNMENT_MODE_DWORD                      = 0x0,
++	SH_MEM_ALIGNMENT_MODE_DWORD_STRICT               = 0x1,
++	SH_MEM_ALIGNMENT_MODE_STRICT                     = 0x2,
++	SH_MEM_ALIGNMENT_MODE_UNALIGNED                  = 0x3,
++} SH_MEM_ALIGNMENT_MODE;
++#define SQ_WAVE_TYPE_PS0                          0x0
++#define SQ_THREAD_TRACE_LFSR_PS                   0x8016
++#define SQ_THREAD_TRACE_LFSR_VS                   0x801c
++#define SQ_THREAD_TRACE_LFSR_GS                   0x801f
++#define SQ_THREAD_TRACE_LFSR_ES                   0x8029
++#define SQ_THREAD_TRACE_LFSR_HS                   0x805e
++#define SQ_THREAD_TRACE_LFSR_LS                   0x806b
++#define SQ_THREAD_TRACE_LFSR_CS                   0x8097
++#define SQIND_GLOBAL_REGS_OFFSET                  0x0
++#define SQIND_GLOBAL_REGS_SIZE                    0x8
++#define SQIND_LOCAL_REGS_OFFSET                   0x8
++#define SQIND_LOCAL_REGS_SIZE                     0x8
++#define SQIND_WAVE_HWREGS_OFFSET                  0x10
++#define SQIND_WAVE_HWREGS_SIZE                    0x1f0
++#define SQIND_WAVE_SGPRS_OFFSET                   0x200
++#define SQIND_WAVE_SGPRS_SIZE                     0x200
++#define SQ_GFXDEC_BEGIN                           0xa000
++#define SQ_GFXDEC_END                             0xc000
++#define SQ_GFXDEC_STATE_ID_SHIFT                  0xa
++#define SQDEC_BEGIN                               0x2300
++#define SQDEC_END                                 0x23ff
++#define SQPERFSDEC_BEGIN                          0xd9c0
++#define SQPERFSDEC_END                            0xda40
++#define SQPERFDDEC_BEGIN                          0xd1c0
++#define SQPERFDDEC_END                            0xd240
++#define SQGFXUDEC_BEGIN                           0xc340
++#define SQGFXUDEC_END                             0xc380
++#define SQPWRDEC_BEGIN                            0xf08c
++#define SQPWRDEC_END                              0xf094
++#define SQ_DISPATCHER_GFX_MIN                     0x10
++#define SQ_DISPATCHER_GFX_CNT_PER_RING            0x8
++#define SQ_MAX_PGM_SGPRS                          0x68
++#define SQ_MAX_PGM_VGPRS                          0x100
++#define SQ_THREAD_TRACE_TIME_UNIT                 0x4
++#define SQ_INTERRUPT_ID                           0xef
++#define SQ_EX_MODE_EXCP_VALU_BASE                 0x0
++#define SQ_EX_MODE_EXCP_VALU_SIZE                 0x7
++#define SQ_EX_MODE_EXCP_INVALID                   0x0
++#define SQ_EX_MODE_EXCP_INPUT_DENORM              0x1
++#define SQ_EX_MODE_EXCP_DIV0                      0x2
++#define SQ_EX_MODE_EXCP_OVERFLOW                  0x3
++#define SQ_EX_MODE_EXCP_UNDERFLOW                 0x4
++#define SQ_EX_MODE_EXCP_INEXACT                   0x5
++#define SQ_EX_MODE_EXCP_INT_DIV0                  0x6
++#define SQ_EX_MODE_EXCP_ADDR_WATCH                0x7
++#define SQ_EX_MODE_EXCP_MEM_VIOL                  0x8
++#define INST_ID_ECC_INTERRUPT_MSG                 0xfffffff0
++#define INST_ID_TTRACE_NEW_PC_MSG                 0xfffffff1
++#define INST_ID_HW_TRAP                           0xfffffff2
++#define INST_ID_KILL_SEQ                          0xfffffff3
++#define INST_ID_HOST_REG_TRAP_MSG                 0xfffffffe
++#define SQ_ENC_SOP1_BITS                          0xbe800000
++#define SQ_ENC_SOP1_MASK                          0xff800000
++#define SQ_ENC_SOP1_FIELD                         0x17d
++#define SQ_ENC_SOPC_BITS                          0xbf000000
++#define SQ_ENC_SOPC_MASK                          0xff800000
++#define SQ_ENC_SOPC_FIELD                         0x17e
++#define SQ_ENC_SOPP_BITS                          0xbf800000
++#define SQ_ENC_SOPP_MASK                          0xff800000
++#define SQ_ENC_SOPP_FIELD                         0x17f
++#define SQ_ENC_SOPK_BITS                          0xb0000000
++#define SQ_ENC_SOPK_MASK                          0xf0000000
++#define SQ_ENC_SOPK_FIELD                         0xb
++#define SQ_ENC_SOP2_BITS                          0x80000000
++#define SQ_ENC_SOP2_MASK                          0xc0000000
++#define SQ_ENC_SOP2_FIELD                         0x2
++#define SQ_ENC_SMRD_BITS                          0xc0000000
++#define SQ_ENC_SMRD_MASK                          0xf8000000
++#define SQ_ENC_SMRD_FIELD                         0x18
++#define SQ_ENC_VOP1_BITS                          0x7e000000
++#define SQ_ENC_VOP1_MASK                          0xfe000000
++#define SQ_ENC_VOP1_FIELD                         0x3f
++#define SQ_ENC_VOPC_BITS                          0x7c000000
++#define SQ_ENC_VOPC_MASK                          0xfe000000
++#define SQ_ENC_VOPC_FIELD                         0x3e
++#define SQ_ENC_VOP2_BITS                          0x0
++#define SQ_ENC_VOP2_MASK                          0x80000000
++#define SQ_ENC_VOP2_FIELD                         0x0
++#define SQ_ENC_VINTRP_BITS                        0xc8000000
++#define SQ_ENC_VINTRP_MASK                        0xfc000000
++#define SQ_ENC_VINTRP_FIELD                       0x32
++#define SQ_ENC_VOP3_BITS                          0xd0000000
++#define SQ_ENC_VOP3_MASK                          0xfc000000
++#define SQ_ENC_VOP3_FIELD                         0x34
++#define SQ_ENC_DS_BITS                            0xd8000000
++#define SQ_ENC_DS_MASK                            0xfc000000
++#define SQ_ENC_DS_FIELD                           0x36
++#define SQ_ENC_MUBUF_BITS                         0xe0000000
++#define SQ_ENC_MUBUF_MASK                         0xfc000000
++#define SQ_ENC_MUBUF_FIELD                        0x38
++#define SQ_ENC_MTBUF_BITS                         0xe8000000
++#define SQ_ENC_MTBUF_MASK                         0xfc000000
++#define SQ_ENC_MTBUF_FIELD                        0x3a
++#define SQ_ENC_MIMG_BITS                          0xf0000000
++#define SQ_ENC_MIMG_MASK                          0xfc000000
++#define SQ_ENC_MIMG_FIELD                         0x3c
++#define SQ_ENC_EXP_BITS                           0xf8000000
++#define SQ_ENC_EXP_MASK                           0xfc000000
++#define SQ_ENC_EXP_FIELD                          0x3e
++#define SQ_ENC_FLAT_BITS                          0xdc000000
++#define SQ_ENC_FLAT_MASK                          0xfc000000
++#define SQ_ENC_FLAT_FIELD                         0x37
++#define SQ_WAITCNT_VM_SHIFT                       0x0
++#define SQ_SENDMSG_STREAMID_SIZE                  0x2
++#define SQ_V_OPC_COUNT                            0x100
++#define SQ_HWREG_OFFSET_SIZE                      0x5
++#define SQ_HWREG_OFFSET_SHIFT                     0x6
++#define SQ_NUM_ATTR                               0x21
++#define SQ_NUM_VGPR                               0x100
++#define SQ_SENDMSG_MSG_SIZE                       0x4
++#define SQ_NUM_TTMP                               0xc
++#define SQ_HWREG_ID_SIZE                          0x6
++#define SQ_SENDMSG_GSOP_SIZE                      0x2
++#define SQ_NUM_SGPR                               0x68
++#define SQ_EXP_NUM_MRT                            0x8
++#define SQ_SENDMSG_SYSTEM_SIZE                    0x3
++#define SQ_WAITCNT_LGKM_SHIFT                     0x8
++#define SQ_WAITCNT_EXP_SIZE                       0x3
++#define SQ_SENDMSG_SYSTEM_SHIFT                   0x4
++#define SQ_HWREG_SIZE_SHIFT                       0xb
++#define SQ_EXP_NUM_GDS                            0x5
++#define SQ_SENDMSG_MSG_SHIFT                      0x0
++#define SQ_WAITCNT_EXP_SHIFT                      0x4
++#define SQ_WAITCNT_VM_SIZE                        0x4
++#define SQ_SENDMSG_GSOP_SHIFT                     0x4
++#define SQ_SRC_VGPR_BIT                           0x100
++#define SQ_V_OP2_COUNT                            0x40
++#define SQ_EXP_NUM_PARAM                          0x20
++#define SQ_SENDMSG_STREAMID_SHIFT                 0x8
++#define SQ_V_OP1_COUNT                            0x80
++#define SQ_WAITCNT_LGKM_SIZE                      0x5
++#define SQ_EXP_NUM_POS                            0x4
++#define SQ_HWREG_SIZE_SIZE                        0x5
++#define SQ_HWREG_ID_SHIFT                         0x0
++#define SQ_S_MOV_B32                              0x3
++#define SQ_S_MOV_B64                              0x4
++#define SQ_S_CMOV_B32                             0x5
++#define SQ_S_CMOV_B64                             0x6
++#define SQ_S_NOT_B32                              0x7
++#define SQ_S_NOT_B64                              0x8
++#define SQ_S_WQM_B32                              0x9
++#define SQ_S_WQM_B64                              0xa
++#define SQ_S_BREV_B32                             0xb
++#define SQ_S_BREV_B64                             0xc
++#define SQ_S_BCNT0_I32_B32                        0xd
++#define SQ_S_BCNT0_I32_B64                        0xe
++#define SQ_S_BCNT1_I32_B32                        0xf
++#define SQ_S_BCNT1_I32_B64                        0x10
++#define SQ_S_FF0_I32_B32                          0x11
++#define SQ_S_FF0_I32_B64                          0x12
++#define SQ_S_FF1_I32_B32                          0x13
++#define SQ_S_FF1_I32_B64                          0x14
++#define SQ_S_FLBIT_I32_B32                        0x15
++#define SQ_S_FLBIT_I32_B64                        0x16
++#define SQ_S_FLBIT_I32                            0x17
++#define SQ_S_FLBIT_I32_I64                        0x18
++#define SQ_S_SEXT_I32_I8                          0x19
++#define SQ_S_SEXT_I32_I16                         0x1a
++#define SQ_S_BITSET0_B32                          0x1b
++#define SQ_S_BITSET0_B64                          0x1c
++#define SQ_S_BITSET1_B32                          0x1d
++#define SQ_S_BITSET1_B64                          0x1e
++#define SQ_S_GETPC_B64                            0x1f
++#define SQ_S_SETPC_B64                            0x20
++#define SQ_S_SWAPPC_B64                           0x21
++#define SQ_S_RFE_B64                              0x22
++#define SQ_S_AND_SAVEEXEC_B64                     0x24
++#define SQ_S_OR_SAVEEXEC_B64                      0x25
++#define SQ_S_XOR_SAVEEXEC_B64                     0x26
++#define SQ_S_ANDN2_SAVEEXEC_B64                   0x27
++#define SQ_S_ORN2_SAVEEXEC_B64                    0x28
++#define SQ_S_NAND_SAVEEXEC_B64                    0x29
++#define SQ_S_NOR_SAVEEXEC_B64                     0x2a
++#define SQ_S_XNOR_SAVEEXEC_B64                    0x2b
++#define SQ_S_QUADMASK_B32                         0x2c
++#define SQ_S_QUADMASK_B64                         0x2d
++#define SQ_S_MOVRELS_B32                          0x2e
++#define SQ_S_MOVRELS_B64                          0x2f
++#define SQ_S_MOVRELD_B32                          0x30
++#define SQ_S_MOVRELD_B64                          0x31
++#define SQ_S_CBRANCH_JOIN                         0x32
++#define SQ_S_MOV_REGRD_B32                        0x33
++#define SQ_S_ABS_I32                              0x34
++#define SQ_S_MOV_FED_B32                          0x35
++#define SQ_ATTR0                                  0x0
++#define SQ_S_MOVK_I32                             0x0
++#define SQ_S_CMOVK_I32                            0x2
++#define SQ_S_CMPK_EQ_I32                          0x3
++#define SQ_S_CMPK_LG_I32                          0x4
++#define SQ_S_CMPK_GT_I32                          0x5
++#define SQ_S_CMPK_GE_I32                          0x6
++#define SQ_S_CMPK_LT_I32                          0x7
++#define SQ_S_CMPK_LE_I32                          0x8
++#define SQ_S_CMPK_EQ_U32                          0x9
++#define SQ_S_CMPK_LG_U32                          0xa
++#define SQ_S_CMPK_GT_U32                          0xb
++#define SQ_S_CMPK_GE_U32                          0xc
++#define SQ_S_CMPK_LT_U32                          0xd
++#define SQ_S_CMPK_LE_U32                          0xe
++#define SQ_S_ADDK_I32                             0xf
++#define SQ_S_MULK_I32                             0x10
++#define SQ_S_CBRANCH_I_FORK                       0x11
++#define SQ_S_GETREG_B32                           0x12
++#define SQ_S_SETREG_B32                           0x13
++#define SQ_S_GETREG_REGRD_B32                     0x14
++#define SQ_S_SETREG_IMM32_B32                     0x15
++#define SQ_TBA_LO                                 0x6c
++#define SQ_TBA_HI                                 0x6d
++#define SQ_TMA_LO                                 0x6e
++#define SQ_TMA_HI                                 0x6f
++#define SQ_TTMP0                                  0x70
++#define SQ_TTMP1                                  0x71
++#define SQ_TTMP2                                  0x72
++#define SQ_TTMP3                                  0x73
++#define SQ_TTMP4                                  0x74
++#define SQ_TTMP5                                  0x75
++#define SQ_TTMP6                                  0x76
++#define SQ_TTMP7                                  0x77
++#define SQ_TTMP8                                  0x78
++#define SQ_TTMP9                                  0x79
++#define SQ_TTMP10                                 0x7a
++#define SQ_TTMP11                                 0x7b
++#define SQ_VGPR0                                  0x0
++#define SQ_EXP                                    0x0
++#define SQ_EXP_MRT0                               0x0
++#define SQ_EXP_MRTZ                               0x8
++#define SQ_EXP_NULL                               0x9
++#define SQ_EXP_POS0                               0xc
++#define SQ_EXP_PARAM0                             0x20
++#define SQ_CNT1                                   0x0
++#define SQ_CNT2                                   0x1
++#define SQ_CNT3                                   0x2
++#define SQ_CNT4                                   0x3
++#define SQ_F                                      0x0
++#define SQ_LT                                     0x1
++#define SQ_EQ                                     0x2
++#define SQ_LE                                     0x3
++#define SQ_GT                                     0x4
++#define SQ_LG                                     0x5
++#define SQ_GE                                     0x6
++#define SQ_O                                      0x7
++#define SQ_U                                      0x8
++#define SQ_NGE                                    0x9
++#define SQ_NLG                                    0xa
++#define SQ_NGT                                    0xb
++#define SQ_NLE                                    0xc
++#define SQ_NEQ                                    0xd
++#define SQ_NLT                                    0xe
++#define SQ_TRU                                    0xf
++#define SQ_V_CMP_F_F32                            0x0
++#define SQ_V_CMP_LT_F32                           0x1
++#define SQ_V_CMP_EQ_F32                           0x2
++#define SQ_V_CMP_LE_F32                           0x3
++#define SQ_V_CMP_GT_F32                           0x4
++#define SQ_V_CMP_LG_F32                           0x5
++#define SQ_V_CMP_GE_F32                           0x6
++#define SQ_V_CMP_O_F32                            0x7
++#define SQ_V_CMP_U_F32                            0x8
++#define SQ_V_CMP_NGE_F32                          0x9
++#define SQ_V_CMP_NLG_F32                          0xa
++#define SQ_V_CMP_NGT_F32                          0xb
++#define SQ_V_CMP_NLE_F32                          0xc
++#define SQ_V_CMP_NEQ_F32                          0xd
++#define SQ_V_CMP_NLT_F32                          0xe
++#define SQ_V_CMP_TRU_F32                          0xf
++#define SQ_V_CMPX_F_F32                           0x10
++#define SQ_V_CMPX_LT_F32                          0x11
++#define SQ_V_CMPX_EQ_F32                          0x12
++#define SQ_V_CMPX_LE_F32                          0x13
++#define SQ_V_CMPX_GT_F32                          0x14
++#define SQ_V_CMPX_LG_F32                          0x15
++#define SQ_V_CMPX_GE_F32                          0x16
++#define SQ_V_CMPX_O_F32                           0x17
++#define SQ_V_CMPX_U_F32                           0x18
++#define SQ_V_CMPX_NGE_F32                         0x19
++#define SQ_V_CMPX_NLG_F32                         0x1a
++#define SQ_V_CMPX_NGT_F32                         0x1b
++#define SQ_V_CMPX_NLE_F32                         0x1c
++#define SQ_V_CMPX_NEQ_F32                         0x1d
++#define SQ_V_CMPX_NLT_F32                         0x1e
++#define SQ_V_CMPX_TRU_F32                         0x1f
++#define SQ_V_CMP_F_F64                            0x20
++#define SQ_V_CMP_LT_F64                           0x21
++#define SQ_V_CMP_EQ_F64                           0x22
++#define SQ_V_CMP_LE_F64                           0x23
++#define SQ_V_CMP_GT_F64                           0x24
++#define SQ_V_CMP_LG_F64                           0x25
++#define SQ_V_CMP_GE_F64                           0x26
++#define SQ_V_CMP_O_F64                            0x27
++#define SQ_V_CMP_U_F64                            0x28
++#define SQ_V_CMP_NGE_F64                          0x29
++#define SQ_V_CMP_NLG_F64                          0x2a
++#define SQ_V_CMP_NGT_F64                          0x2b
++#define SQ_V_CMP_NLE_F64                          0x2c
++#define SQ_V_CMP_NEQ_F64                          0x2d
++#define SQ_V_CMP_NLT_F64                          0x2e
++#define SQ_V_CMP_TRU_F64                          0x2f
++#define SQ_V_CMPX_F_F64                           0x30
++#define SQ_V_CMPX_LT_F64                          0x31
++#define SQ_V_CMPX_EQ_F64                          0x32
++#define SQ_V_CMPX_LE_F64                          0x33
++#define SQ_V_CMPX_GT_F64                          0x34
++#define SQ_V_CMPX_LG_F64                          0x35
++#define SQ_V_CMPX_GE_F64                          0x36
++#define SQ_V_CMPX_O_F64                           0x37
++#define SQ_V_CMPX_U_F64                           0x38
++#define SQ_V_CMPX_NGE_F64                         0x39
++#define SQ_V_CMPX_NLG_F64                         0x3a
++#define SQ_V_CMPX_NGT_F64                         0x3b
++#define SQ_V_CMPX_NLE_F64                         0x3c
++#define SQ_V_CMPX_NEQ_F64                         0x3d
++#define SQ_V_CMPX_NLT_F64                         0x3e
++#define SQ_V_CMPX_TRU_F64                         0x3f
++#define SQ_V_CMPS_F_F32                           0x40
++#define SQ_V_CMPS_LT_F32                          0x41
++#define SQ_V_CMPS_EQ_F32                          0x42
++#define SQ_V_CMPS_LE_F32                          0x43
++#define SQ_V_CMPS_GT_F32                          0x44
++#define SQ_V_CMPS_LG_F32                          0x45
++#define SQ_V_CMPS_GE_F32                          0x46
++#define SQ_V_CMPS_O_F32                           0x47
++#define SQ_V_CMPS_U_F32                           0x48
++#define SQ_V_CMPS_NGE_F32                         0x49
++#define SQ_V_CMPS_NLG_F32                         0x4a
++#define SQ_V_CMPS_NGT_F32                         0x4b
++#define SQ_V_CMPS_NLE_F32                         0x4c
++#define SQ_V_CMPS_NEQ_F32                         0x4d
++#define SQ_V_CMPS_NLT_F32                         0x4e
++#define SQ_V_CMPS_TRU_F32                         0x4f
++#define SQ_V_CMPSX_F_F32                          0x50
++#define SQ_V_CMPSX_LT_F32                         0x51
++#define SQ_V_CMPSX_EQ_F32                         0x52
++#define SQ_V_CMPSX_LE_F32                         0x53
++#define SQ_V_CMPSX_GT_F32                         0x54
++#define SQ_V_CMPSX_LG_F32                         0x55
++#define SQ_V_CMPSX_GE_F32                         0x56
++#define SQ_V_CMPSX_O_F32                          0x57
++#define SQ_V_CMPSX_U_F32                          0x58
++#define SQ_V_CMPSX_NGE_F32                        0x59
++#define SQ_V_CMPSX_NLG_F32                        0x5a
++#define SQ_V_CMPSX_NGT_F32                        0x5b
++#define SQ_V_CMPSX_NLE_F32                        0x5c
++#define SQ_V_CMPSX_NEQ_F32                        0x5d
++#define SQ_V_CMPSX_NLT_F32                        0x5e
++#define SQ_V_CMPSX_TRU_F32                        0x5f
++#define SQ_V_CMPS_F_F64                           0x60
++#define SQ_V_CMPS_LT_F64                          0x61
++#define SQ_V_CMPS_EQ_F64                          0x62
++#define SQ_V_CMPS_LE_F64                          0x63
++#define SQ_V_CMPS_GT_F64                          0x64
++#define SQ_V_CMPS_LG_F64                          0x65
++#define SQ_V_CMPS_GE_F64                          0x66
++#define SQ_V_CMPS_O_F64                           0x67
++#define SQ_V_CMPS_U_F64                           0x68
++#define SQ_V_CMPS_NGE_F64                         0x69
++#define SQ_V_CMPS_NLG_F64                         0x6a
++#define SQ_V_CMPS_NGT_F64                         0x6b
++#define SQ_V_CMPS_NLE_F64                         0x6c
++#define SQ_V_CMPS_NEQ_F64                         0x6d
++#define SQ_V_CMPS_NLT_F64                         0x6e
++#define SQ_V_CMPS_TRU_F64                         0x6f
++#define SQ_V_CMPSX_F_F64                          0x70
++#define SQ_V_CMPSX_LT_F64                         0x71
++#define SQ_V_CMPSX_EQ_F64                         0x72
++#define SQ_V_CMPSX_LE_F64                         0x73
++#define SQ_V_CMPSX_GT_F64                         0x74
++#define SQ_V_CMPSX_LG_F64                         0x75
++#define SQ_V_CMPSX_GE_F64                         0x76
++#define SQ_V_CMPSX_O_F64                          0x77
++#define SQ_V_CMPSX_U_F64                          0x78
++#define SQ_V_CMPSX_NGE_F64                        0x79
++#define SQ_V_CMPSX_NLG_F64                        0x7a
++#define SQ_V_CMPSX_NGT_F64                        0x7b
++#define SQ_V_CMPSX_NLE_F64                        0x7c
++#define SQ_V_CMPSX_NEQ_F64                        0x7d
++#define SQ_V_CMPSX_NLT_F64                        0x7e
++#define SQ_V_CMPSX_TRU_F64                        0x7f
++#define SQ_V_CMP_F_I32                            0x80
++#define SQ_V_CMP_LT_I32                           0x81
++#define SQ_V_CMP_EQ_I32                           0x82
++#define SQ_V_CMP_LE_I32                           0x83
++#define SQ_V_CMP_GT_I32                           0x84
++#define SQ_V_CMP_NE_I32                           0x85
++#define SQ_V_CMP_GE_I32                           0x86
++#define SQ_V_CMP_T_I32                            0x87
++#define SQ_V_CMPX_F_I32                           0x90
++#define SQ_V_CMPX_LT_I32                          0x91
++#define SQ_V_CMPX_EQ_I32                          0x92
++#define SQ_V_CMPX_LE_I32                          0x93
++#define SQ_V_CMPX_GT_I32                          0x94
++#define SQ_V_CMPX_NE_I32                          0x95
++#define SQ_V_CMPX_GE_I32                          0x96
++#define SQ_V_CMPX_T_I32                           0x97
++#define SQ_V_CMP_F_I64                            0xa0
++#define SQ_V_CMP_LT_I64                           0xa1
++#define SQ_V_CMP_EQ_I64                           0xa2
++#define SQ_V_CMP_LE_I64                           0xa3
++#define SQ_V_CMP_GT_I64                           0xa4
++#define SQ_V_CMP_NE_I64                           0xa5
++#define SQ_V_CMP_GE_I64                           0xa6
++#define SQ_V_CMP_T_I64                            0xa7
++#define SQ_V_CMPX_F_I64                           0xb0
++#define SQ_V_CMPX_LT_I64                          0xb1
++#define SQ_V_CMPX_EQ_I64                          0xb2
++#define SQ_V_CMPX_LE_I64                          0xb3
++#define SQ_V_CMPX_GT_I64                          0xb4
++#define SQ_V_CMPX_NE_I64                          0xb5
++#define SQ_V_CMPX_GE_I64                          0xb6
++#define SQ_V_CMPX_T_I64                           0xb7
++#define SQ_V_CMP_F_U32                            0xc0
++#define SQ_V_CMP_LT_U32                           0xc1
++#define SQ_V_CMP_EQ_U32                           0xc2
++#define SQ_V_CMP_LE_U32                           0xc3
++#define SQ_V_CMP_GT_U32                           0xc4
++#define SQ_V_CMP_NE_U32                           0xc5
++#define SQ_V_CMP_GE_U32                           0xc6
++#define SQ_V_CMP_T_U32                            0xc7
++#define SQ_V_CMPX_F_U32                           0xd0
++#define SQ_V_CMPX_LT_U32                          0xd1
++#define SQ_V_CMPX_EQ_U32                          0xd2
++#define SQ_V_CMPX_LE_U32                          0xd3
++#define SQ_V_CMPX_GT_U32                          0xd4
++#define SQ_V_CMPX_NE_U32                          0xd5
++#define SQ_V_CMPX_GE_U32                          0xd6
++#define SQ_V_CMPX_T_U32                           0xd7
++#define SQ_V_CMP_F_U64                            0xe0
++#define SQ_V_CMP_LT_U64                           0xe1
++#define SQ_V_CMP_EQ_U64                           0xe2
++#define SQ_V_CMP_LE_U64                           0xe3
++#define SQ_V_CMP_GT_U64                           0xe4
++#define SQ_V_CMP_NE_U64                           0xe5
++#define SQ_V_CMP_GE_U64                           0xe6
++#define SQ_V_CMP_T_U64                            0xe7
++#define SQ_V_CMPX_F_U64                           0xf0
++#define SQ_V_CMPX_LT_U64                          0xf1
++#define SQ_V_CMPX_EQ_U64                          0xf2
++#define SQ_V_CMPX_LE_U64                          0xf3
++#define SQ_V_CMPX_GT_U64                          0xf4
++#define SQ_V_CMPX_NE_U64                          0xf5
++#define SQ_V_CMPX_GE_U64                          0xf6
++#define SQ_V_CMPX_T_U64                           0xf7
++#define SQ_V_CMP_CLASS_F32                        0x88
++#define SQ_V_CMPX_CLASS_F32                       0x98
++#define SQ_V_CMP_CLASS_F64                        0xa8
++#define SQ_V_CMPX_CLASS_F64                       0xb8
++#define SQ_SGPR0                                  0x0
++#define SQ_F                                      0x0
++#define SQ_LT                                     0x1
++#define SQ_EQ                                     0x2
++#define SQ_LE                                     0x3
++#define SQ_GT                                     0x4
++#define SQ_NE                                     0x5
++#define SQ_GE                                     0x6
++#define SQ_T                                      0x7
++#define SQ_SRC_64_INT                             0xc0
++#define SQ_SRC_M_1_INT                            0xc1
++#define SQ_SRC_M_2_INT                            0xc2
++#define SQ_SRC_M_3_INT                            0xc3
++#define SQ_SRC_M_4_INT                            0xc4
++#define SQ_SRC_M_5_INT                            0xc5
++#define SQ_SRC_M_6_INT                            0xc6
++#define SQ_SRC_M_7_INT                            0xc7
++#define SQ_SRC_M_8_INT                            0xc8
++#define SQ_SRC_M_9_INT                            0xc9
++#define SQ_SRC_M_10_INT                           0xca
++#define SQ_SRC_M_11_INT                           0xcb
++#define SQ_SRC_M_12_INT                           0xcc
++#define SQ_SRC_M_13_INT                           0xcd
++#define SQ_SRC_M_14_INT                           0xce
++#define SQ_SRC_M_15_INT                           0xcf
++#define SQ_SRC_M_16_INT                           0xd0
++#define SQ_SRC_0_5                                0xf0
++#define SQ_SRC_M_0_5                              0xf1
++#define SQ_SRC_1                                  0xf2
++#define SQ_SRC_M_1                                0xf3
++#define SQ_SRC_2                                  0xf4
++#define SQ_SRC_M_2                                0xf5
++#define SQ_SRC_4                                  0xf6
++#define SQ_SRC_M_4                                0xf7
++#define SQ_SRC_0                                  0x80
++#define SQ_SRC_1_INT                              0x81
++#define SQ_SRC_2_INT                              0x82
++#define SQ_SRC_3_INT                              0x83
++#define SQ_SRC_4_INT                              0x84
++#define SQ_SRC_5_INT                              0x85
++#define SQ_SRC_6_INT                              0x86
++#define SQ_SRC_7_INT                              0x87
++#define SQ_SRC_8_INT                              0x88
++#define SQ_SRC_9_INT                              0x89
++#define SQ_SRC_10_INT                             0x8a
++#define SQ_SRC_11_INT                             0x8b
++#define SQ_SRC_12_INT                             0x8c
++#define SQ_SRC_13_INT                             0x8d
++#define SQ_SRC_14_INT                             0x8e
++#define SQ_SRC_15_INT                             0x8f
++#define SQ_SRC_16_INT                             0x90
++#define SQ_SRC_17_INT                             0x91
++#define SQ_SRC_18_INT                             0x92
++#define SQ_SRC_19_INT                             0x93
++#define SQ_SRC_20_INT                             0x94
++#define SQ_SRC_21_INT                             0x95
++#define SQ_SRC_22_INT                             0x96
++#define SQ_SRC_23_INT                             0x97
++#define SQ_SRC_24_INT                             0x98
++#define SQ_SRC_25_INT                             0x99
++#define SQ_SRC_26_INT                             0x9a
++#define SQ_SRC_27_INT                             0x9b
++#define SQ_SRC_28_INT                             0x9c
++#define SQ_SRC_29_INT                             0x9d
++#define SQ_SRC_30_INT                             0x9e
++#define SQ_SRC_31_INT                             0x9f
++#define SQ_SRC_32_INT                             0xa0
++#define SQ_SRC_33_INT                             0xa1
++#define SQ_SRC_34_INT                             0xa2
++#define SQ_SRC_35_INT                             0xa3
++#define SQ_SRC_36_INT                             0xa4
++#define SQ_SRC_37_INT                             0xa5
++#define SQ_SRC_38_INT                             0xa6
++#define SQ_SRC_39_INT                             0xa7
++#define SQ_SRC_40_INT                             0xa8
++#define SQ_SRC_41_INT                             0xa9
++#define SQ_SRC_42_INT                             0xaa
++#define SQ_SRC_43_INT                             0xab
++#define SQ_SRC_44_INT                             0xac
++#define SQ_SRC_45_INT                             0xad
++#define SQ_SRC_46_INT                             0xae
++#define SQ_SRC_47_INT                             0xaf
++#define SQ_SRC_48_INT                             0xb0
++#define SQ_SRC_49_INT                             0xb1
++#define SQ_SRC_50_INT                             0xb2
++#define SQ_SRC_51_INT                             0xb3
++#define SQ_SRC_52_INT                             0xb4
++#define SQ_SRC_53_INT                             0xb5
++#define SQ_SRC_54_INT                             0xb6
++#define SQ_SRC_55_INT                             0xb7
++#define SQ_SRC_56_INT                             0xb8
++#define SQ_SRC_57_INT                             0xb9
++#define SQ_SRC_58_INT                             0xba
++#define SQ_SRC_59_INT                             0xbb
++#define SQ_SRC_60_INT                             0xbc
++#define SQ_SRC_61_INT                             0xbd
++#define SQ_SRC_62_INT                             0xbe
++#define SQ_SRC_63_INT                             0xbf
++#define SQ_BUFFER_LOAD_FORMAT_X                   0x0
++#define SQ_BUFFER_LOAD_FORMAT_XY                  0x1
++#define SQ_BUFFER_LOAD_FORMAT_XYZ                 0x2
++#define SQ_BUFFER_LOAD_FORMAT_XYZW                0x3
++#define SQ_BUFFER_STORE_FORMAT_X                  0x4
++#define SQ_BUFFER_STORE_FORMAT_XY                 0x5
++#define SQ_BUFFER_STORE_FORMAT_XYZ                0x6
++#define SQ_BUFFER_STORE_FORMAT_XYZW               0x7
++#define SQ_BUFFER_LOAD_UBYTE                      0x8
++#define SQ_BUFFER_LOAD_SBYTE                      0x9
++#define SQ_BUFFER_LOAD_USHORT                     0xa
++#define SQ_BUFFER_LOAD_SSHORT                     0xb
++#define SQ_BUFFER_LOAD_DWORD                      0xc
++#define SQ_BUFFER_LOAD_DWORDX2                    0xd
++#define SQ_BUFFER_LOAD_DWORDX4                    0xe
++#define SQ_BUFFER_LOAD_DWORDX3                    0xf
++#define SQ_BUFFER_STORE_BYTE                      0x18
++#define SQ_BUFFER_STORE_SHORT                     0x1a
++#define SQ_BUFFER_STORE_DWORD                     0x1c
++#define SQ_BUFFER_STORE_DWORDX2                   0x1d
++#define SQ_BUFFER_STORE_DWORDX4                   0x1e
++#define SQ_BUFFER_STORE_DWORDX3                   0x1f
++#define SQ_BUFFER_ATOMIC_SWAP                     0x30
++#define SQ_BUFFER_ATOMIC_CMPSWAP                  0x31
++#define SQ_BUFFER_ATOMIC_ADD                      0x32
++#define SQ_BUFFER_ATOMIC_SUB                      0x33
++#define SQ_BUFFER_ATOMIC_SMIN                     0x35
++#define SQ_BUFFER_ATOMIC_UMIN                     0x36
++#define SQ_BUFFER_ATOMIC_SMAX                     0x37
++#define SQ_BUFFER_ATOMIC_UMAX                     0x38
++#define SQ_BUFFER_ATOMIC_AND                      0x39
++#define SQ_BUFFER_ATOMIC_OR                       0x3a
++#define SQ_BUFFER_ATOMIC_XOR                      0x3b
++#define SQ_BUFFER_ATOMIC_INC                      0x3c
++#define SQ_BUFFER_ATOMIC_DEC                      0x3d
++#define SQ_BUFFER_ATOMIC_FCMPSWAP                 0x3e
++#define SQ_BUFFER_ATOMIC_FMIN                     0x3f
++#define SQ_BUFFER_ATOMIC_FMAX                     0x40
++#define SQ_BUFFER_ATOMIC_SWAP_X2                  0x50
++#define SQ_BUFFER_ATOMIC_CMPSWAP_X2               0x51
++#define SQ_BUFFER_ATOMIC_ADD_X2                   0x52
++#define SQ_BUFFER_ATOMIC_SUB_X2                   0x53
++#define SQ_BUFFER_ATOMIC_SMIN_X2                  0x55
++#define SQ_BUFFER_ATOMIC_UMIN_X2                  0x56
++#define SQ_BUFFER_ATOMIC_SMAX_X2                  0x57
++#define SQ_BUFFER_ATOMIC_UMAX_X2                  0x58
++#define SQ_BUFFER_ATOMIC_AND_X2                   0x59
++#define SQ_BUFFER_ATOMIC_OR_X2                    0x5a
++#define SQ_BUFFER_ATOMIC_XOR_X2                   0x5b
++#define SQ_BUFFER_ATOMIC_INC_X2                   0x5c
++#define SQ_BUFFER_ATOMIC_DEC_X2                   0x5d
++#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2              0x5e
++#define SQ_BUFFER_ATOMIC_FMIN_X2                  0x5f
++#define SQ_BUFFER_ATOMIC_FMAX_X2                  0x60
++#define SQ_BUFFER_WBINVL1_VOL                     0x70
++#define SQ_BUFFER_WBINVL1                         0x71
++#define SQ_DS_ADD_U32                             0x0
++#define SQ_DS_SUB_U32                             0x1
++#define SQ_DS_RSUB_U32                            0x2
++#define SQ_DS_INC_U32                             0x3
++#define SQ_DS_DEC_U32                             0x4
++#define SQ_DS_MIN_I32                             0x5
++#define SQ_DS_MAX_I32                             0x6
++#define SQ_DS_MIN_U32                             0x7
++#define SQ_DS_MAX_U32                             0x8
++#define SQ_DS_AND_B32                             0x9
++#define SQ_DS_OR_B32                              0xa
++#define SQ_DS_XOR_B32                             0xb
++#define SQ_DS_MSKOR_B32                           0xc
++#define SQ_DS_WRITE_B32                           0xd
++#define SQ_DS_WRITE2_B32                          0xe
++#define SQ_DS_WRITE2ST64_B32                      0xf
++#define SQ_DS_CMPST_B32                           0x10
++#define SQ_DS_CMPST_F32                           0x11
++#define SQ_DS_MIN_F32                             0x12
++#define SQ_DS_MAX_F32                             0x13
++#define SQ_DS_NOP                                 0x14
++#define SQ_DS_GWS_SEMA_RELEASE_ALL                0x18
++#define SQ_DS_GWS_INIT                            0x19
++#define SQ_DS_GWS_SEMA_V                          0x1a
++#define SQ_DS_GWS_SEMA_BR                         0x1b
++#define SQ_DS_GWS_SEMA_P                          0x1c
++#define SQ_DS_GWS_BARRIER                         0x1d
++#define SQ_DS_WRITE_B8                            0x1e
++#define SQ_DS_WRITE_B16                           0x1f
++#define SQ_DS_ADD_RTN_U32                         0x20
++#define SQ_DS_SUB_RTN_U32                         0x21
++#define SQ_DS_RSUB_RTN_U32                        0x22
++#define SQ_DS_INC_RTN_U32                         0x23
++#define SQ_DS_DEC_RTN_U32                         0x24
++#define SQ_DS_MIN_RTN_I32                         0x25
++#define SQ_DS_MAX_RTN_I32                         0x26
++#define SQ_DS_MIN_RTN_U32                         0x27
++#define SQ_DS_MAX_RTN_U32                         0x28
++#define SQ_DS_AND_RTN_B32                         0x29
++#define SQ_DS_OR_RTN_B32                          0x2a
++#define SQ_DS_XOR_RTN_B32                         0x2b
++#define SQ_DS_MSKOR_RTN_B32                       0x2c
++#define SQ_DS_WRXCHG_RTN_B32                      0x2d
++#define SQ_DS_WRXCHG2_RTN_B32                     0x2e
++#define SQ_DS_WRXCHG2ST64_RTN_B32                 0x2f
++#define SQ_DS_CMPST_RTN_B32                       0x30
++#define SQ_DS_CMPST_RTN_F32                       0x31
++#define SQ_DS_MIN_RTN_F32                         0x32
++#define SQ_DS_MAX_RTN_F32                         0x33
++#define SQ_DS_WRAP_RTN_B32                        0x34
++#define SQ_DS_SWIZZLE_B32                         0x35
++#define SQ_DS_READ_B32                            0x36
++#define SQ_DS_READ2_B32                           0x37
++#define SQ_DS_READ2ST64_B32                       0x38
++#define SQ_DS_READ_I8                             0x39
++#define SQ_DS_READ_U8                             0x3a
++#define SQ_DS_READ_I16                            0x3b
++#define SQ_DS_READ_U16                            0x3c
++#define SQ_DS_CONSUME                             0x3d
++#define SQ_DS_APPEND                              0x3e
++#define SQ_DS_ORDERED_COUNT                       0x3f
++#define SQ_DS_ADD_U64                             0x40
++#define SQ_DS_SUB_U64                             0x41
++#define SQ_DS_RSUB_U64                            0x42
++#define SQ_DS_INC_U64                             0x43
++#define SQ_DS_DEC_U64                             0x44
++#define SQ_DS_MIN_I64                             0x45
++#define SQ_DS_MAX_I64                             0x46
++#define SQ_DS_MIN_U64                             0x47
++#define SQ_DS_MAX_U64                             0x48
++#define SQ_DS_AND_B64                             0x49
++#define SQ_DS_OR_B64                              0x4a
++#define SQ_DS_XOR_B64                             0x4b
++#define SQ_DS_MSKOR_B64                           0x4c
++#define SQ_DS_WRITE_B64                           0x4d
++#define SQ_DS_WRITE2_B64                          0x4e
++#define SQ_DS_WRITE2ST64_B64                      0x4f
++#define SQ_DS_CMPST_B64                           0x50
++#define SQ_DS_CMPST_F64                           0x51
++#define SQ_DS_MIN_F64                             0x52
++#define SQ_DS_MAX_F64                             0x53
++#define SQ_DS_ADD_RTN_U64                         0x60
++#define SQ_DS_SUB_RTN_U64                         0x61
++#define SQ_DS_RSUB_RTN_U64                        0x62
++#define SQ_DS_INC_RTN_U64                         0x63
++#define SQ_DS_DEC_RTN_U64                         0x64
++#define SQ_DS_MIN_RTN_I64                         0x65
++#define SQ_DS_MAX_RTN_I64                         0x66
++#define SQ_DS_MIN_RTN_U64                         0x67
++#define SQ_DS_MAX_RTN_U64                         0x68
++#define SQ_DS_AND_RTN_B64                         0x69
++#define SQ_DS_OR_RTN_B64                          0x6a
++#define SQ_DS_XOR_RTN_B64                         0x6b
++#define SQ_DS_MSKOR_RTN_B64                       0x6c
++#define SQ_DS_WRXCHG_RTN_B64                      0x6d
++#define SQ_DS_WRXCHG2_RTN_B64                     0x6e
++#define SQ_DS_WRXCHG2ST64_RTN_B64                 0x6f
++#define SQ_DS_CMPST_RTN_B64                       0x70
++#define SQ_DS_CMPST_RTN_F64                       0x71
++#define SQ_DS_MIN_RTN_F64                         0x72
++#define SQ_DS_MAX_RTN_F64                         0x73
++#define SQ_DS_READ_B64                            0x76
++#define SQ_DS_READ2_B64                           0x77
++#define SQ_DS_READ2ST64_B64                       0x78
++#define SQ_DS_CONDXCHG32_RTN_B64                  0x7e
++#define SQ_DS_ADD_SRC2_U32                        0x80
++#define SQ_DS_SUB_SRC2_U32                        0x81
++#define SQ_DS_RSUB_SRC2_U32                       0x82
++#define SQ_DS_INC_SRC2_U32                        0x83
++#define SQ_DS_DEC_SRC2_U32                        0x84
++#define SQ_DS_MIN_SRC2_I32                        0x85
++#define SQ_DS_MAX_SRC2_I32                        0x86
++#define SQ_DS_MIN_SRC2_U32                        0x87
++#define SQ_DS_MAX_SRC2_U32                        0x88
++#define SQ_DS_AND_SRC2_B32                        0x89
++#define SQ_DS_OR_SRC2_B32                         0x8a
++#define SQ_DS_XOR_SRC2_B32                        0x8b
++#define SQ_DS_WRITE_SRC2_B32                      0x8d
++#define SQ_DS_MIN_SRC2_F32                        0x92
++#define SQ_DS_MAX_SRC2_F32                        0x93
++#define SQ_DS_ADD_SRC2_U64                        0xc0
++#define SQ_DS_SUB_SRC2_U64                        0xc1
++#define SQ_DS_RSUB_SRC2_U64                       0xc2
++#define SQ_DS_INC_SRC2_U64                        0xc3
++#define SQ_DS_DEC_SRC2_U64                        0xc4
++#define SQ_DS_MIN_SRC2_I64                        0xc5
++#define SQ_DS_MAX_SRC2_I64                        0xc6
++#define SQ_DS_MIN_SRC2_U64                        0xc7
++#define SQ_DS_MAX_SRC2_U64                        0xc8
++#define SQ_DS_AND_SRC2_B64                        0xc9
++#define SQ_DS_OR_SRC2_B64                         0xca
++#define SQ_DS_XOR_SRC2_B64                        0xcb
++#define SQ_DS_WRITE_SRC2_B64                      0xcd
++#define SQ_DS_MIN_SRC2_F64                        0xd2
++#define SQ_DS_MAX_SRC2_F64                        0xd3
++#define SQ_DS_WRITE_B96                           0xde
++#define SQ_DS_WRITE_B128                          0xdf
++#define SQ_DS_CONDXCHG32_RTN_B128                 0xfd
++#define SQ_DS_READ_B96                            0xfe
++#define SQ_DS_READ_B128                           0xff
++#define SQ_SRC_SCC                                0xfd
++#define SQ_OMOD_OFF                               0x0
++#define SQ_OMOD_M2                                0x1
++#define SQ_OMOD_M4                                0x2
++#define SQ_OMOD_D2                                0x3
++#define SQ_EXP_GDS0                               0x18
++#define SQ_GS_OP_NOP                              0x0
++#define SQ_GS_OP_CUT                              0x1
++#define SQ_GS_OP_EMIT                             0x2
++#define SQ_GS_OP_EMIT_CUT                         0x3
++#define SQ_IMAGE_LOAD                             0x0
++#define SQ_IMAGE_LOAD_MIP                         0x1
++#define SQ_IMAGE_LOAD_PCK                         0x2
++#define SQ_IMAGE_LOAD_PCK_SGN                     0x3
++#define SQ_IMAGE_LOAD_MIP_PCK                     0x4
++#define SQ_IMAGE_LOAD_MIP_PCK_SGN                 0x5
++#define SQ_IMAGE_STORE                            0x8
++#define SQ_IMAGE_STORE_MIP                        0x9
++#define SQ_IMAGE_STORE_PCK                        0xa
++#define SQ_IMAGE_STORE_MIP_PCK                    0xb
++#define SQ_IMAGE_GET_RESINFO                      0xe
++#define SQ_IMAGE_ATOMIC_SWAP                      0xf
++#define SQ_IMAGE_ATOMIC_CMPSWAP                   0x10
++#define SQ_IMAGE_ATOMIC_ADD                       0x11
++#define SQ_IMAGE_ATOMIC_SUB                       0x12
++#define SQ_IMAGE_ATOMIC_SMIN                      0x14
++#define SQ_IMAGE_ATOMIC_UMIN                      0x15
++#define SQ_IMAGE_ATOMIC_SMAX                      0x16
++#define SQ_IMAGE_ATOMIC_UMAX                      0x17
++#define SQ_IMAGE_ATOMIC_AND                       0x18
++#define SQ_IMAGE_ATOMIC_OR                        0x19
++#define SQ_IMAGE_ATOMIC_XOR                       0x1a
++#define SQ_IMAGE_ATOMIC_INC                       0x1b
++#define SQ_IMAGE_ATOMIC_DEC                       0x1c
++#define SQ_IMAGE_ATOMIC_FCMPSWAP                  0x1d
++#define SQ_IMAGE_ATOMIC_FMIN                      0x1e
++#define SQ_IMAGE_ATOMIC_FMAX                      0x1f
++#define SQ_IMAGE_SAMPLE                           0x20
++#define SQ_IMAGE_SAMPLE_CL                        0x21
++#define SQ_IMAGE_SAMPLE_D                         0x22
++#define SQ_IMAGE_SAMPLE_D_CL                      0x23
++#define SQ_IMAGE_SAMPLE_L                         0x24
++#define SQ_IMAGE_SAMPLE_B                         0x25
++#define SQ_IMAGE_SAMPLE_B_CL                      0x26
++#define SQ_IMAGE_SAMPLE_LZ                        0x27
++#define SQ_IMAGE_SAMPLE_C                         0x28
++#define SQ_IMAGE_SAMPLE_C_CL                      0x29
++#define SQ_IMAGE_SAMPLE_C_D                       0x2a
++#define SQ_IMAGE_SAMPLE_C_D_CL                    0x2b
++#define SQ_IMAGE_SAMPLE_C_L                       0x2c
++#define SQ_IMAGE_SAMPLE_C_B                       0x2d
++#define SQ_IMAGE_SAMPLE_C_B_CL                    0x2e
++#define SQ_IMAGE_SAMPLE_C_LZ                      0x2f
++#define SQ_IMAGE_SAMPLE_O                         0x30
++#define SQ_IMAGE_SAMPLE_CL_O                      0x31
++#define SQ_IMAGE_SAMPLE_D_O                       0x32
++#define SQ_IMAGE_SAMPLE_D_CL_O                    0x33
++#define SQ_IMAGE_SAMPLE_L_O                       0x34
++#define SQ_IMAGE_SAMPLE_B_O                       0x35
++#define SQ_IMAGE_SAMPLE_B_CL_O                    0x36
++#define SQ_IMAGE_SAMPLE_LZ_O                      0x37
++#define SQ_IMAGE_SAMPLE_C_O                       0x38
++#define SQ_IMAGE_SAMPLE_C_CL_O                    0x39
++#define SQ_IMAGE_SAMPLE_C_D_O                     0x3a
++#define SQ_IMAGE_SAMPLE_C_D_CL_O                  0x3b
++#define SQ_IMAGE_SAMPLE_C_L_O                     0x3c
++#define SQ_IMAGE_SAMPLE_C_B_O                     0x3d
++#define SQ_IMAGE_SAMPLE_C_B_CL_O                  0x3e
++#define SQ_IMAGE_SAMPLE_C_LZ_O                    0x3f
++#define SQ_IMAGE_GATHER4                          0x40
++#define SQ_IMAGE_GATHER4_CL                       0x41
++#define SQ_IMAGE_GATHER4_L                        0x44
++#define SQ_IMAGE_GATHER4_B                        0x45
++#define SQ_IMAGE_GATHER4_B_CL                     0x46
++#define SQ_IMAGE_GATHER4_LZ                       0x47
++#define SQ_IMAGE_GATHER4_C                        0x48
++#define SQ_IMAGE_GATHER4_C_CL                     0x49
++#define SQ_IMAGE_GATHER4_C_L                      0x4c
++#define SQ_IMAGE_GATHER4_C_B                      0x4d
++#define SQ_IMAGE_GATHER4_C_B_CL                   0x4e
++#define SQ_IMAGE_GATHER4_C_LZ                     0x4f
++#define SQ_IMAGE_GATHER4_O                        0x50
++#define SQ_IMAGE_GATHER4_CL_O                     0x51
++#define SQ_IMAGE_GATHER4_L_O                      0x54
++#define SQ_IMAGE_GATHER4_B_O                      0x55
++#define SQ_IMAGE_GATHER4_B_CL_O                   0x56
++#define SQ_IMAGE_GATHER4_LZ_O                     0x57
++#define SQ_IMAGE_GATHER4_C_O                      0x58
++#define SQ_IMAGE_GATHER4_C_CL_O                   0x59
++#define SQ_IMAGE_GATHER4_C_L_O                    0x5c
++#define SQ_IMAGE_GATHER4_C_B_O                    0x5d
++#define SQ_IMAGE_GATHER4_C_B_CL_O                 0x5e
++#define SQ_IMAGE_GATHER4_C_LZ_O                   0x5f
++#define SQ_IMAGE_GET_LOD                          0x60
++#define SQ_IMAGE_SAMPLE_CD                        0x68
++#define SQ_IMAGE_SAMPLE_CD_CL                     0x69
++#define SQ_IMAGE_SAMPLE_C_CD                      0x6a
++#define SQ_IMAGE_SAMPLE_C_CD_CL                   0x6b
++#define SQ_IMAGE_SAMPLE_CD_O                      0x6c
++#define SQ_IMAGE_SAMPLE_CD_CL_O                   0x6d
++#define SQ_IMAGE_SAMPLE_C_CD_O                    0x6e
++#define SQ_IMAGE_SAMPLE_C_CD_CL_O                 0x6f
++#define SQ_IMAGE_RSRC256                          0x7e
++#define SQ_IMAGE_SAMPLER                          0x7f
++#define SQ_SRC_VCCZ                               0xfb
++#define SQ_SRC_VGPR0                              0x100
++#define SQ_DFMT_INVALID                           0x0
++#define SQ_DFMT_8                                 0x1
++#define SQ_DFMT_16                                0x2
++#define SQ_DFMT_8_8                               0x3
++#define SQ_DFMT_32                                0x4
++#define SQ_DFMT_16_16                             0x5
++#define SQ_DFMT_10_11_11                          0x6
++#define SQ_DFMT_11_11_10                          0x7
++#define SQ_DFMT_10_10_10_2                        0x8
++#define SQ_DFMT_2_10_10_10                        0x9
++#define SQ_DFMT_8_8_8_8                           0xa
++#define SQ_DFMT_32_32                             0xb
++#define SQ_DFMT_16_16_16_16                       0xc
++#define SQ_DFMT_32_32_32                          0xd
++#define SQ_DFMT_32_32_32_32                       0xe
++#define SQ_TBUFFER_LOAD_FORMAT_X                  0x0
++#define SQ_TBUFFER_LOAD_FORMAT_XY                 0x1
++#define SQ_TBUFFER_LOAD_FORMAT_XYZ                0x2
++#define SQ_TBUFFER_LOAD_FORMAT_XYZW               0x3
++#define SQ_TBUFFER_STORE_FORMAT_X                 0x4
++#define SQ_TBUFFER_STORE_FORMAT_XY                0x5
++#define SQ_TBUFFER_STORE_FORMAT_XYZ               0x6
++#define SQ_TBUFFER_STORE_FORMAT_XYZW              0x7
++#define SQ_CHAN_X                                 0x0
++#define SQ_CHAN_Y                                 0x1
++#define SQ_CHAN_Z                                 0x2
++#define SQ_CHAN_W                                 0x3
++#define SQ_EXEC_LO                                0x7e
++#define SQ_EXEC_HI                                0x7f
++#define SQ_S_LOAD_DWORD                           0x0
++#define SQ_S_LOAD_DWORDX2                         0x1
++#define SQ_S_LOAD_DWORDX4                         0x2
++#define SQ_S_LOAD_DWORDX8                         0x3
++#define SQ_S_LOAD_DWORDX16                        0x4
++#define SQ_S_BUFFER_LOAD_DWORD                    0x8
++#define SQ_S_BUFFER_LOAD_DWORDX2                  0x9
++#define SQ_S_BUFFER_LOAD_DWORDX4                  0xa
++#define SQ_S_BUFFER_LOAD_DWORDX8                  0xb
++#define SQ_S_BUFFER_LOAD_DWORDX16                 0xc
++#define SQ_S_DCACHE_INV_VOL                       0x1d
++#define SQ_S_MEMTIME                              0x1e
++#define SQ_S_DCACHE_INV                           0x1f
++#define SQ_V_NOP                                  0x0
++#define SQ_V_MOV_B32                              0x1
++#define SQ_V_READFIRSTLANE_B32                    0x2
++#define SQ_V_CVT_I32_F64                          0x3
++#define SQ_V_CVT_F64_I32                          0x4
++#define SQ_V_CVT_F32_I32                          0x5
++#define SQ_V_CVT_F32_U32                          0x6
++#define SQ_V_CVT_U32_F32                          0x7
++#define SQ_V_CVT_I32_F32                          0x8
++#define SQ_V_MOV_FED_B32                          0x9
++#define SQ_V_CVT_F16_F32                          0xa
++#define SQ_V_CVT_F32_F16                          0xb
++#define SQ_V_CVT_RPI_I32_F32                      0xc
++#define SQ_V_CVT_FLR_I32_F32                      0xd
++#define SQ_V_CVT_OFF_F32_I4                       0xe
++#define SQ_V_CVT_F32_F64                          0xf
++#define SQ_V_CVT_F64_F32                          0x10
++#define SQ_V_CVT_F32_UBYTE0                       0x11
++#define SQ_V_CVT_F32_UBYTE1                       0x12
++#define SQ_V_CVT_F32_UBYTE2                       0x13
++#define SQ_V_CVT_F32_UBYTE3                       0x14
++#define SQ_V_CVT_U32_F64                          0x15
++#define SQ_V_CVT_F64_U32                          0x16
++#define SQ_V_TRUNC_F64                            0x17
++#define SQ_V_CEIL_F64                             0x18
++#define SQ_V_RNDNE_F64                            0x19
++#define SQ_V_FLOOR_F64                            0x1a
++#define SQ_V_FRACT_F32                            0x20
++#define SQ_V_TRUNC_F32                            0x21
++#define SQ_V_CEIL_F32                             0x22
++#define SQ_V_RNDNE_F32                            0x23
++#define SQ_V_FLOOR_F32                            0x24
++#define SQ_V_EXP_F32                              0x25
++#define SQ_V_LOG_CLAMP_F32                        0x26
++#define SQ_V_LOG_F32                              0x27
++#define SQ_V_RCP_CLAMP_F32                        0x28
++#define SQ_V_RCP_LEGACY_F32                       0x29
++#define SQ_V_RCP_F32                              0x2a
++#define SQ_V_RCP_IFLAG_F32                        0x2b
++#define SQ_V_RSQ_CLAMP_F32                        0x2c
++#define SQ_V_RSQ_LEGACY_F32                       0x2d
++#define SQ_V_RSQ_F32                              0x2e
++#define SQ_V_RCP_F64                              0x2f
++#define SQ_V_RCP_CLAMP_F64                        0x30
++#define SQ_V_RSQ_F64                              0x31
++#define SQ_V_RSQ_CLAMP_F64                        0x32
++#define SQ_V_SQRT_F32                             0x33
++#define SQ_V_SQRT_F64                             0x34
++#define SQ_V_SIN_F32                              0x35
++#define SQ_V_COS_F32                              0x36
++#define SQ_V_NOT_B32                              0x37
++#define SQ_V_BFREV_B32                            0x38
++#define SQ_V_FFBH_U32                             0x39
++#define SQ_V_FFBL_B32                             0x3a
++#define SQ_V_FFBH_I32                             0x3b
++#define SQ_V_FREXP_EXP_I32_F64                    0x3c
++#define SQ_V_FREXP_MANT_F64                       0x3d
++#define SQ_V_FRACT_F64                            0x3e
++#define SQ_V_FREXP_EXP_I32_F32                    0x3f
++#define SQ_V_FREXP_MANT_F32                       0x40
++#define SQ_V_CLREXCP                              0x41
++#define SQ_V_MOVRELD_B32                          0x42
++#define SQ_V_MOVRELS_B32                          0x43
++#define SQ_V_MOVRELSD_B32                         0x44
++#define SQ_V_LOG_LEGACY_F32                       0x45
++#define SQ_V_EXP_LEGACY_F32                       0x46
++#define SQ_NFMT_UNORM                             0x0
++#define SQ_NFMT_SNORM                             0x1
++#define SQ_NFMT_USCALED                           0x2
++#define SQ_NFMT_SSCALED                           0x3
++#define SQ_NFMT_UINT                              0x4
++#define SQ_NFMT_SINT                              0x5
++#define SQ_NFMT_SNORM_OGL                         0x6
++#define SQ_NFMT_FLOAT                             0x7
++#define SQ_V_OP1_OFFSET                           0x180
++#define SQ_V_OP2_OFFSET                           0x100
++#define SQ_V_OPC_OFFSET                           0x0
++#define SQ_V_INTERP_P1_F32                        0x0
++#define SQ_V_INTERP_P2_F32                        0x1
++#define SQ_V_INTERP_MOV_F32                       0x2
++#define SQ_S_NOP                                  0x0
++#define SQ_S_ENDPGM                               0x1
++#define SQ_S_BRANCH                               0x2
++#define SQ_S_CBRANCH_SCC0                         0x4
++#define SQ_S_CBRANCH_SCC1                         0x5
++#define SQ_S_CBRANCH_VCCZ                         0x6
++#define SQ_S_CBRANCH_VCCNZ                        0x7
++#define SQ_S_CBRANCH_EXECZ                        0x8
++#define SQ_S_CBRANCH_EXECNZ                       0x9
++#define SQ_S_BARRIER                              0xa
++#define SQ_S_SETKILL                              0xb
++#define SQ_S_WAITCNT                              0xc
++#define SQ_S_SETHALT                              0xd
++#define SQ_S_SLEEP                                0xe
++#define SQ_S_SETPRIO                              0xf
++#define SQ_S_SENDMSG                              0x10
++#define SQ_S_SENDMSGHALT                          0x11
++#define SQ_S_TRAP                                 0x12
++#define SQ_S_ICACHE_INV                           0x13
++#define SQ_S_INCPERFLEVEL                         0x14
++#define SQ_S_DECPERFLEVEL                         0x15
++#define SQ_S_TTRACEDATA                           0x16
++#define SQ_S_CBRANCH_CDBGSYS                      0x17
++#define SQ_S_CBRANCH_CDBGUSER                     0x18
++#define SQ_S_CBRANCH_CDBGSYS_OR_USER              0x19
++#define SQ_S_CBRANCH_CDBGSYS_AND_USER             0x1a
++#define SQ_SRC_LITERAL                            0xff
++#define SQ_VCC_LO                                 0x6a
++#define SQ_VCC_HI                                 0x6b
++#define SQ_PARAM_P10                              0x0
++#define SQ_PARAM_P20                              0x1
++#define SQ_PARAM_P0                               0x2
++#define SQ_SRC_LDS_DIRECT                         0xfe
++#define SQ_FLAT_SCRATCH_LO                        0x68
++#define SQ_FLAT_SCRATCH_HI                        0x69
++#define SQ_V_CNDMASK_B32                          0x0
++#define SQ_V_READLANE_B32                         0x1
++#define SQ_V_WRITELANE_B32                        0x2
++#define SQ_V_ADD_F32                              0x3
++#define SQ_V_SUB_F32                              0x4
++#define SQ_V_SUBREV_F32                           0x5
++#define SQ_V_MAC_LEGACY_F32                       0x6
++#define SQ_V_MUL_LEGACY_F32                       0x7
++#define SQ_V_MUL_F32                              0x8
++#define SQ_V_MUL_I32_I24                          0x9
++#define SQ_V_MUL_HI_I32_I24                       0xa
++#define SQ_V_MUL_U32_U24                          0xb
++#define SQ_V_MUL_HI_U32_U24                       0xc
++#define SQ_V_MIN_LEGACY_F32                       0xd
++#define SQ_V_MAX_LEGACY_F32                       0xe
++#define SQ_V_MIN_F32                              0xf
++#define SQ_V_MAX_F32                              0x10
++#define SQ_V_MIN_I32                              0x11
++#define SQ_V_MAX_I32                              0x12
++#define SQ_V_MIN_U32                              0x13
++#define SQ_V_MAX_U32                              0x14
++#define SQ_V_LSHR_B32                             0x15
++#define SQ_V_LSHRREV_B32                          0x16
++#define SQ_V_ASHR_I32                             0x17
++#define SQ_V_ASHRREV_I32                          0x18
++#define SQ_V_LSHL_B32                             0x19
++#define SQ_V_LSHLREV_B32                          0x1a
++#define SQ_V_AND_B32                              0x1b
++#define SQ_V_OR_B32                               0x1c
++#define SQ_V_XOR_B32                              0x1d
++#define SQ_V_BFM_B32                              0x1e
++#define SQ_V_MAC_F32                              0x1f
++#define SQ_V_MADMK_F32                            0x20
++#define SQ_V_MADAK_F32                            0x21
++#define SQ_V_BCNT_U32_B32                         0x22
++#define SQ_V_MBCNT_LO_U32_B32                     0x23
++#define SQ_V_MBCNT_HI_U32_B32                     0x24
++#define SQ_V_ADD_I32                              0x25
++#define SQ_V_SUB_I32                              0x26
++#define SQ_V_SUBREV_I32                           0x27
++#define SQ_V_ADDC_U32                             0x28
++#define SQ_V_SUBB_U32                             0x29
++#define SQ_V_SUBBREV_U32                          0x2a
++#define SQ_V_LDEXP_F32                            0x2b
++#define SQ_V_CVT_PKACCUM_U8_F32                   0x2c
++#define SQ_V_CVT_PKNORM_I16_F32                   0x2d
++#define SQ_V_CVT_PKNORM_U16_F32                   0x2e
++#define SQ_V_CVT_PKRTZ_F16_F32                    0x2f
++#define SQ_V_CVT_PK_U16_U32                       0x30
++#define SQ_V_CVT_PK_I16_I32                       0x31
++#define SQ_FLAT_LOAD_UBYTE                        0x8
++#define SQ_FLAT_LOAD_SBYTE                        0x9
++#define SQ_FLAT_LOAD_USHORT                       0xa
++#define SQ_FLAT_LOAD_SSHORT                       0xb
++#define SQ_FLAT_LOAD_DWORD                        0xc
++#define SQ_FLAT_LOAD_DWORDX2                      0xd
++#define SQ_FLAT_LOAD_DWORDX4                      0xe
++#define SQ_FLAT_LOAD_DWORDX3                      0xf
++#define SQ_FLAT_STORE_BYTE                        0x18
++#define SQ_FLAT_STORE_SHORT                       0x1a
++#define SQ_FLAT_STORE_DWORD                       0x1c
++#define SQ_FLAT_STORE_DWORDX2                     0x1d
++#define SQ_FLAT_STORE_DWORDX4                     0x1e
++#define SQ_FLAT_STORE_DWORDX3                     0x1f
++#define SQ_FLAT_ATOMIC_SWAP                       0x30
++#define SQ_FLAT_ATOMIC_CMPSWAP                    0x31
++#define SQ_FLAT_ATOMIC_ADD                        0x32
++#define SQ_FLAT_ATOMIC_SUB                        0x33
++#define SQ_FLAT_ATOMIC_SMIN                       0x35
++#define SQ_FLAT_ATOMIC_UMIN                       0x36
++#define SQ_FLAT_ATOMIC_SMAX                       0x37
++#define SQ_FLAT_ATOMIC_UMAX                       0x38
++#define SQ_FLAT_ATOMIC_AND                        0x39
++#define SQ_FLAT_ATOMIC_OR                         0x3a
++#define SQ_FLAT_ATOMIC_XOR                        0x3b
++#define SQ_FLAT_ATOMIC_INC                        0x3c
++#define SQ_FLAT_ATOMIC_DEC                        0x3d
++#define SQ_FLAT_ATOMIC_FCMPSWAP                   0x3e
++#define SQ_FLAT_ATOMIC_FMIN                       0x3f
++#define SQ_FLAT_ATOMIC_FMAX                       0x40
++#define SQ_FLAT_ATOMIC_SWAP_X2                    0x50
++#define SQ_FLAT_ATOMIC_CMPSWAP_X2                 0x51
++#define SQ_FLAT_ATOMIC_ADD_X2                     0x52
++#define SQ_FLAT_ATOMIC_SUB_X2                     0x53
++#define SQ_FLAT_ATOMIC_SMIN_X2                    0x55
++#define SQ_FLAT_ATOMIC_UMIN_X2                    0x56
++#define SQ_FLAT_ATOMIC_SMAX_X2                    0x57
++#define SQ_FLAT_ATOMIC_UMAX_X2                    0x58
++#define SQ_FLAT_ATOMIC_AND_X2                     0x59
++#define SQ_FLAT_ATOMIC_OR_X2                      0x5a
++#define SQ_FLAT_ATOMIC_XOR_X2                     0x5b
++#define SQ_FLAT_ATOMIC_INC_X2                     0x5c
++#define SQ_FLAT_ATOMIC_DEC_X2                     0x5d
++#define SQ_FLAT_ATOMIC_FCMPSWAP_X2                0x5e
++#define SQ_FLAT_ATOMIC_FMIN_X2                    0x5f
++#define SQ_FLAT_ATOMIC_FMAX_X2                    0x60
++#define SQ_S_CMP_EQ_I32                           0x0
++#define SQ_S_CMP_LG_I32                           0x1
++#define SQ_S_CMP_GT_I32                           0x2
++#define SQ_S_CMP_GE_I32                           0x3
++#define SQ_S_CMP_LT_I32                           0x4
++#define SQ_S_CMP_LE_I32                           0x5
++#define SQ_S_CMP_EQ_U32                           0x6
++#define SQ_S_CMP_LG_U32                           0x7
++#define SQ_S_CMP_GT_U32                           0x8
++#define SQ_S_CMP_GE_U32                           0x9
++#define SQ_S_CMP_LT_U32                           0xa
++#define SQ_S_CMP_LE_U32                           0xb
++#define SQ_S_BITCMP0_B32                          0xc
++#define SQ_S_BITCMP1_B32                          0xd
++#define SQ_S_BITCMP0_B64                          0xe
++#define SQ_S_BITCMP1_B64                          0xf
++#define SQ_S_SETVSKIP                             0x10
++#define SQ_M0                                     0x7c
++#define SQ_V_MAD_LEGACY_F32                       0x140
++#define SQ_V_MAD_F32                              0x141
++#define SQ_V_MAD_I32_I24                          0x142
++#define SQ_V_MAD_U32_U24                          0x143
++#define SQ_V_CUBEID_F32                           0x144
++#define SQ_V_CUBESC_F32                           0x145
++#define SQ_V_CUBETC_F32                           0x146
++#define SQ_V_CUBEMA_F32                           0x147
++#define SQ_V_BFE_U32                              0x148
++#define SQ_V_BFE_I32                              0x149
++#define SQ_V_BFI_B32                              0x14a
++#define SQ_V_FMA_F32                              0x14b
++#define SQ_V_FMA_F64                              0x14c
++#define SQ_V_LERP_U8                              0x14d
++#define SQ_V_ALIGNBIT_B32                         0x14e
++#define SQ_V_ALIGNBYTE_B32                        0x14f
++#define SQ_V_MULLIT_F32                           0x150
++#define SQ_V_MIN3_F32                             0x151
++#define SQ_V_MIN3_I32                             0x152
++#define SQ_V_MIN3_U32                             0x153
++#define SQ_V_MAX3_F32                             0x154
++#define SQ_V_MAX3_I32                             0x155
++#define SQ_V_MAX3_U32                             0x156
++#define SQ_V_MED3_F32                             0x157
++#define SQ_V_MED3_I32                             0x158
++#define SQ_V_MED3_U32                             0x159
++#define SQ_V_SAD_U8                               0x15a
++#define SQ_V_SAD_HI_U8                            0x15b
++#define SQ_V_SAD_U16                              0x15c
++#define SQ_V_SAD_U32                              0x15d
++#define SQ_V_CVT_PK_U8_F32                        0x15e
++#define SQ_V_DIV_FIXUP_F32                        0x15f
++#define SQ_V_DIV_FIXUP_F64                        0x160
++#define SQ_V_LSHL_B64                             0x161
++#define SQ_V_LSHR_B64                             0x162
++#define SQ_V_ASHR_I64                             0x163
++#define SQ_V_ADD_F64                              0x164
++#define SQ_V_MUL_F64                              0x165
++#define SQ_V_MIN_F64                              0x166
++#define SQ_V_MAX_F64                              0x167
++#define SQ_V_LDEXP_F64                            0x168
++#define SQ_V_MUL_LO_U32                           0x169
++#define SQ_V_MUL_HI_U32                           0x16a
++#define SQ_V_MUL_LO_I32                           0x16b
++#define SQ_V_MUL_HI_I32                           0x16c
++#define SQ_V_DIV_SCALE_F32                        0x16d
++#define SQ_V_DIV_SCALE_F64                        0x16e
++#define SQ_V_DIV_FMAS_F32                         0x16f
++#define SQ_V_DIV_FMAS_F64                         0x170
++#define SQ_V_MSAD_U8                              0x171
++#define SQ_V_QSAD_PK_U16_U8                       0x172
++#define SQ_V_MQSAD_PK_U16_U8                      0x173
++#define SQ_V_TRIG_PREOP_F64                       0x174
++#define SQ_V_MQSAD_U32_U8                         0x175
++#define SQ_V_MAD_U64_U32                          0x176
++#define SQ_V_MAD_I64_I32                          0x177
++#define SQ_VCC_ALL                                0x0
++#define SQ_SRC_EXECZ                              0xfc
++#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT            0x1
++#define SQ_SYSMSG_OP_REG_RD                       0x2
++#define SQ_SYSMSG_OP_HOST_TRAP_ACK                0x3
++#define SQ_SYSMSG_OP_TTRACE_PC                    0x4
++#define SQ_HW_REG_MODE                            0x1
++#define SQ_HW_REG_STATUS                          0x2
++#define SQ_HW_REG_TRAPSTS                         0x3
++#define SQ_HW_REG_HW_ID                           0x4
++#define SQ_HW_REG_GPR_ALLOC                       0x5
++#define SQ_HW_REG_LDS_ALLOC                       0x6
++#define SQ_HW_REG_IB_STS                          0x7
++#define SQ_HW_REG_PC_LO                           0x8
++#define SQ_HW_REG_PC_HI                           0x9
++#define SQ_HW_REG_INST_DW0                        0xa
++#define SQ_HW_REG_INST_DW1                        0xb
++#define SQ_HW_REG_IB_DBG0                         0xc
++#define SQ_S_ADD_U32                              0x0
++#define SQ_S_SUB_U32                              0x1
++#define SQ_S_ADD_I32                              0x2
++#define SQ_S_SUB_I32                              0x3
++#define SQ_S_ADDC_U32                             0x4
++#define SQ_S_SUBB_U32                             0x5
++#define SQ_S_MIN_I32                              0x6
++#define SQ_S_MIN_U32                              0x7
++#define SQ_S_MAX_I32                              0x8
++#define SQ_S_MAX_U32                              0x9
++#define SQ_S_CSELECT_B32                          0xa
++#define SQ_S_CSELECT_B64                          0xb
++#define SQ_S_AND_B32                              0xe
++#define SQ_S_AND_B64                              0xf
++#define SQ_S_OR_B32                               0x10
++#define SQ_S_OR_B64                               0x11
++#define SQ_S_XOR_B32                              0x12
++#define SQ_S_XOR_B64                              0x13
++#define SQ_S_ANDN2_B32                            0x14
++#define SQ_S_ANDN2_B64                            0x15
++#define SQ_S_ORN2_B32                             0x16
++#define SQ_S_ORN2_B64                             0x17
++#define SQ_S_NAND_B32                             0x18
++#define SQ_S_NAND_B64                             0x19
++#define SQ_S_NOR_B32                              0x1a
++#define SQ_S_NOR_B64                              0x1b
++#define SQ_S_XNOR_B32                             0x1c
++#define SQ_S_XNOR_B64                             0x1d
++#define SQ_S_LSHL_B32                             0x1e
++#define SQ_S_LSHL_B64                             0x1f
++#define SQ_S_LSHR_B32                             0x20
++#define SQ_S_LSHR_B64                             0x21
++#define SQ_S_ASHR_I32                             0x22
++#define SQ_S_ASHR_I64                             0x23
++#define SQ_S_BFM_B32                              0x24
++#define SQ_S_BFM_B64                              0x25
++#define SQ_S_MUL_I32                              0x26
++#define SQ_S_BFE_U32                              0x27
++#define SQ_S_BFE_I32                              0x28
++#define SQ_S_BFE_U64                              0x29
++#define SQ_S_BFE_I64                              0x2a
++#define SQ_S_CBRANCH_G_FORK                       0x2b
++#define SQ_S_ABSDIFF_I32                          0x2c
++#define SQ_MSG_INTERRUPT                          0x1
++#define SQ_MSG_GS                                 0x2
++#define SQ_MSG_GS_DONE                            0x3
++#define SQ_MSG_SYSMSG                             0xf
++typedef enum TEX_BORDER_COLOR_TYPE {
++	TEX_BorderColor_TransparentBlack                 = 0x0,
++	TEX_BorderColor_OpaqueBlack                      = 0x1,
++	TEX_BorderColor_OpaqueWhite                      = 0x2,
++	TEX_BorderColor_Register                         = 0x3,
++} TEX_BORDER_COLOR_TYPE;
++typedef enum TEX_CHROMA_KEY {
++	TEX_ChromaKey_Disabled                           = 0x0,
++	TEX_ChromaKey_Kill                               = 0x1,
++	TEX_ChromaKey_Blend                              = 0x2,
++	TEX_ChromaKey_RESERVED_3                         = 0x3,
++} TEX_CHROMA_KEY;
++typedef enum TEX_CLAMP {
++	TEX_Clamp_Repeat                                 = 0x0,
++	TEX_Clamp_Mirror                                 = 0x1,
++	TEX_Clamp_ClampToLast                            = 0x2,
++	TEX_Clamp_MirrorOnceToLast                       = 0x3,
++	TEX_Clamp_ClampHalfToBorder                      = 0x4,
++	TEX_Clamp_MirrorOnceHalfToBorder                 = 0x5,
++	TEX_Clamp_ClampToBorder                          = 0x6,
++	TEX_Clamp_MirrorOnceToBorder                     = 0x7,
++} TEX_CLAMP;
++typedef enum TEX_COORD_TYPE {
++	TEX_CoordType_Unnormalized                       = 0x0,
++	TEX_CoordType_Normalized                         = 0x1,
++} TEX_COORD_TYPE;
++typedef enum TEX_DEPTH_COMPARE_FUNCTION {
++	TEX_DepthCompareFunction_Never                   = 0x0,
++	TEX_DepthCompareFunction_Less                    = 0x1,
++	TEX_DepthCompareFunction_Equal                   = 0x2,
++	TEX_DepthCompareFunction_LessEqual               = 0x3,
++	TEX_DepthCompareFunction_Greater                 = 0x4,
++	TEX_DepthCompareFunction_NotEqual                = 0x5,
++	TEX_DepthCompareFunction_GreaterEqual            = 0x6,
++	TEX_DepthCompareFunction_Always                  = 0x7,
++} TEX_DEPTH_COMPARE_FUNCTION;
++typedef enum TEX_DIM {
++	TEX_Dim_1D                                       = 0x0,
++	TEX_Dim_2D                                       = 0x1,
++	TEX_Dim_3D                                       = 0x2,
++	TEX_Dim_CubeMap                                  = 0x3,
++	TEX_Dim_1DArray                                  = 0x4,
++	TEX_Dim_2DArray                                  = 0x5,
++	TEX_Dim_2D_MSAA                                  = 0x6,
++	TEX_Dim_2DArray_MSAA                             = 0x7,
++} TEX_DIM;
++typedef enum TEX_FORMAT_COMP {
++	TEX_FormatComp_Unsigned                          = 0x0,
++	TEX_FormatComp_Signed                            = 0x1,
++	TEX_FormatComp_UnsignedBiased                    = 0x2,
++	TEX_FormatComp_RESERVED_3                        = 0x3,
++} TEX_FORMAT_COMP;
++typedef enum TEX_MAX_ANISO_RATIO {
++	TEX_MaxAnisoRatio_1to1                           = 0x0,
++	TEX_MaxAnisoRatio_2to1                           = 0x1,
++	TEX_MaxAnisoRatio_4to1                           = 0x2,
++	TEX_MaxAnisoRatio_8to1                           = 0x3,
++	TEX_MaxAnisoRatio_16to1                          = 0x4,
++	TEX_MaxAnisoRatio_RESERVED_5                     = 0x5,
++	TEX_MaxAnisoRatio_RESERVED_6                     = 0x6,
++	TEX_MaxAnisoRatio_RESERVED_7                     = 0x7,
++} TEX_MAX_ANISO_RATIO;
++typedef enum TEX_MIP_FILTER {
++	TEX_MipFilter_None                               = 0x0,
++	TEX_MipFilter_Point                              = 0x1,
++	TEX_MipFilter_Linear                             = 0x2,
++	TEX_MipFilter_RESERVED_3                         = 0x3,
++} TEX_MIP_FILTER;
++typedef enum TEX_REQUEST_SIZE {
++	TEX_RequestSize_32B                              = 0x0,
++	TEX_RequestSize_64B                              = 0x1,
++	TEX_RequestSize_128B                             = 0x2,
++	TEX_RequestSize_2X64B                            = 0x3,
++} TEX_REQUEST_SIZE;
++typedef enum TEX_SAMPLER_TYPE {
++	TEX_SamplerType_Invalid                          = 0x0,
++	TEX_SamplerType_Valid                            = 0x1,
++} TEX_SAMPLER_TYPE;
++typedef enum TEX_XY_FILTER {
++	TEX_XYFilter_Point                               = 0x0,
++	TEX_XYFilter_Linear                              = 0x1,
++	TEX_XYFilter_AnisoPoint                          = 0x2,
++	TEX_XYFilter_AnisoLinear                         = 0x3,
++} TEX_XY_FILTER;
++typedef enum TEX_Z_FILTER {
++	TEX_ZFilter_None                                 = 0x0,
++	TEX_ZFilter_Point                                = 0x1,
++	TEX_ZFilter_Linear                               = 0x2,
++	TEX_ZFilter_RESERVED_3                           = 0x3,
++} TEX_Z_FILTER;
++typedef enum VTX_CLAMP {
++	VTX_Clamp_ClampToZero                            = 0x0,
++	VTX_Clamp_ClampToNAN                             = 0x1,
++} VTX_CLAMP;
++typedef enum VTX_FETCH_TYPE {
++	VTX_FetchType_VertexData                         = 0x0,
++	VTX_FetchType_InstanceData                       = 0x1,
++	VTX_FetchType_NoIndexOffset                      = 0x2,
++	VTX_FetchType_RESERVED_3                         = 0x3,
++} VTX_FETCH_TYPE;
++typedef enum VTX_FORMAT_COMP_ALL {
++	VTX_FormatCompAll_Unsigned                       = 0x0,
++	VTX_FormatCompAll_Signed                         = 0x1,
++} VTX_FORMAT_COMP_ALL;
++typedef enum VTX_MEM_REQUEST_SIZE {
++	VTX_MemRequestSize_32B                           = 0x0,
++	VTX_MemRequestSize_64B                           = 0x1,
++} VTX_MEM_REQUEST_SIZE;
++typedef enum TVX_DATA_FORMAT {
++	TVX_FMT_INVALID                                  = 0x0,
++	TVX_FMT_8                                        = 0x1,
++	TVX_FMT_4_4                                      = 0x2,
++	TVX_FMT_3_3_2                                    = 0x3,
++	TVX_FMT_RESERVED_4                               = 0x4,
++	TVX_FMT_16                                       = 0x5,
++	TVX_FMT_16_FLOAT                                 = 0x6,
++	TVX_FMT_8_8                                      = 0x7,
++	TVX_FMT_5_6_5                                    = 0x8,
++	TVX_FMT_6_5_5                                    = 0x9,
++	TVX_FMT_1_5_5_5                                  = 0xa,
++	TVX_FMT_4_4_4_4                                  = 0xb,
++	TVX_FMT_5_5_5_1                                  = 0xc,
++	TVX_FMT_32                                       = 0xd,
++	TVX_FMT_32_FLOAT                                 = 0xe,
++	TVX_FMT_16_16                                    = 0xf,
++	TVX_FMT_16_16_FLOAT                              = 0x10,
++	TVX_FMT_8_24                                     = 0x11,
++	TVX_FMT_8_24_FLOAT                               = 0x12,
++	TVX_FMT_24_8                                     = 0x13,
++	TVX_FMT_24_8_FLOAT                               = 0x14,
++	TVX_FMT_10_11_11                                 = 0x15,
++	TVX_FMT_10_11_11_FLOAT                           = 0x16,
++	TVX_FMT_11_11_10                                 = 0x17,
++	TVX_FMT_11_11_10_FLOAT                           = 0x18,
++	TVX_FMT_2_10_10_10                               = 0x19,
++	TVX_FMT_8_8_8_8                                  = 0x1a,
++	TVX_FMT_10_10_10_2                               = 0x1b,
++	TVX_FMT_X24_8_32_FLOAT                           = 0x1c,
++	TVX_FMT_32_32                                    = 0x1d,
++	TVX_FMT_32_32_FLOAT                              = 0x1e,
++	TVX_FMT_16_16_16_16                              = 0x1f,
++	TVX_FMT_16_16_16_16_FLOAT                        = 0x20,
++	TVX_FMT_RESERVED_33                              = 0x21,
++	TVX_FMT_32_32_32_32                              = 0x22,
++	TVX_FMT_32_32_32_32_FLOAT                        = 0x23,
++	TVX_FMT_RESERVED_36                              = 0x24,
++	TVX_FMT_1                                        = 0x25,
++	TVX_FMT_1_REVERSED                               = 0x26,
++	TVX_FMT_GB_GR                                    = 0x27,
++	TVX_FMT_BG_RG                                    = 0x28,
++	TVX_FMT_32_AS_8                                  = 0x29,
++	TVX_FMT_32_AS_8_8                                = 0x2a,
++	TVX_FMT_5_9_9_9_SHAREDEXP                        = 0x2b,
++	TVX_FMT_8_8_8                                    = 0x2c,
++	TVX_FMT_16_16_16                                 = 0x2d,
++	TVX_FMT_16_16_16_FLOAT                           = 0x2e,
++	TVX_FMT_32_32_32                                 = 0x2f,
++	TVX_FMT_32_32_32_FLOAT                           = 0x30,
++	TVX_FMT_BC1                                      = 0x31,
++	TVX_FMT_BC2                                      = 0x32,
++	TVX_FMT_BC3                                      = 0x33,
++	TVX_FMT_BC4                                      = 0x34,
++	TVX_FMT_BC5                                      = 0x35,
++	TVX_FMT_APC0                                     = 0x36,
++	TVX_FMT_APC1                                     = 0x37,
++	TVX_FMT_APC2                                     = 0x38,
++	TVX_FMT_APC3                                     = 0x39,
++	TVX_FMT_APC4                                     = 0x3a,
++	TVX_FMT_APC5                                     = 0x3b,
++	TVX_FMT_APC6                                     = 0x3c,
++	TVX_FMT_APC7                                     = 0x3d,
++	TVX_FMT_CTX1                                     = 0x3e,
++	TVX_FMT_RESERVED_63                              = 0x3f,
++} TVX_DATA_FORMAT;
++typedef enum TVX_DST_SEL {
++	TVX_DstSel_X                                     = 0x0,
++	TVX_DstSel_Y                                     = 0x1,
++	TVX_DstSel_Z                                     = 0x2,
++	TVX_DstSel_W                                     = 0x3,
++	TVX_DstSel_0f                                    = 0x4,
++	TVX_DstSel_1f                                    = 0x5,
++	TVX_DstSel_RESERVED_6                            = 0x6,
++	TVX_DstSel_Mask                                  = 0x7,
++} TVX_DST_SEL;
++typedef enum TVX_ENDIAN_SWAP {
++	TVX_EndianSwap_None                              = 0x0,
++	TVX_EndianSwap_8in16                             = 0x1,
++	TVX_EndianSwap_8in32                             = 0x2,
++	TVX_EndianSwap_8in64                             = 0x3,
++} TVX_ENDIAN_SWAP;
++typedef enum TVX_INST {
++	TVX_Inst_NormalVertexFetch                       = 0x0,
++	TVX_Inst_SemanticVertexFetch                     = 0x1,
++	TVX_Inst_RESERVED_2                              = 0x2,
++	TVX_Inst_LD                                      = 0x3,
++	TVX_Inst_GetTextureResInfo                       = 0x4,
++	TVX_Inst_GetNumberOfSamples                      = 0x5,
++	TVX_Inst_GetLOD                                  = 0x6,
++	TVX_Inst_GetGradientsH                           = 0x7,
++	TVX_Inst_GetGradientsV                           = 0x8,
++	TVX_Inst_SetTextureOffsets                       = 0x9,
++	TVX_Inst_KeepGradients                           = 0xa,
++	TVX_Inst_SetGradientsH                           = 0xb,
++	TVX_Inst_SetGradientsV                           = 0xc,
++	TVX_Inst_Pass                                    = 0xd,
++	TVX_Inst_GetBufferResInfo                        = 0xe,
++	TVX_Inst_RESERVED_15                             = 0xf,
++	TVX_Inst_Sample                                  = 0x10,
++	TVX_Inst_Sample_L                                = 0x11,
++	TVX_Inst_Sample_LB                               = 0x12,
++	TVX_Inst_Sample_LZ                               = 0x13,
++	TVX_Inst_Sample_G                                = 0x14,
++	TVX_Inst_Gather4                                 = 0x15,
++	TVX_Inst_Sample_G_LB                             = 0x16,
++	TVX_Inst_Gather4_O                               = 0x17,
++	TVX_Inst_Sample_C                                = 0x18,
++	TVX_Inst_Sample_C_L                              = 0x19,
++	TVX_Inst_Sample_C_LB                             = 0x1a,
++	TVX_Inst_Sample_C_LZ                             = 0x1b,
++	TVX_Inst_Sample_C_G                              = 0x1c,
++	TVX_Inst_Gather4_C                               = 0x1d,
++	TVX_Inst_Sample_C_G_LB                           = 0x1e,
++	TVX_Inst_Gather4_C_O                             = 0x1f,
++} TVX_INST;
++typedef enum TVX_NUM_FORMAT_ALL {
++	TVX_NumFormatAll_Norm                            = 0x0,
++	TVX_NumFormatAll_Int                             = 0x1,
++	TVX_NumFormatAll_Scaled                          = 0x2,
++	TVX_NumFormatAll_RESERVED_3                      = 0x3,
++} TVX_NUM_FORMAT_ALL;
++typedef enum TVX_SRC_SEL {
++	TVX_SrcSel_X                                     = 0x0,
++	TVX_SrcSel_Y                                     = 0x1,
++	TVX_SrcSel_Z                                     = 0x2,
++	TVX_SrcSel_W                                     = 0x3,
++	TVX_SrcSel_0f                                    = 0x4,
++	TVX_SrcSel_1f                                    = 0x5,
++} TVX_SRC_SEL;
++typedef enum TVX_SRF_MODE_ALL {
++	TVX_SRFModeAll_ZCMO                              = 0x0,
++	TVX_SRFModeAll_NZ                                = 0x1,
++} TVX_SRF_MODE_ALL;
++typedef enum TVX_TYPE {
++	TVX_Type_InvalidTextureResource                  = 0x0,
++	TVX_Type_InvalidVertexBuffer                     = 0x1,
++	TVX_Type_ValidTextureResource                    = 0x2,
++	TVX_Type_ValidVertexBuffer                       = 0x3,
++} TVX_TYPE;
++typedef enum TC_OP_MASKS {
++	TC_OP_MASK_FLUSH_DENROM                          = 0x8,
++	TC_OP_MASK_64                                    = 0x20,
++	TC_OP_MASK_NO_RTN                                = 0x40,
++} TC_OP_MASKS;
++typedef enum TC_OP {
++	TC_OP_READ                                       = 0x0,
++	TC_OP_ATOMIC_FCMPSWAP_RTN_32                     = 0x1,
++	TC_OP_ATOMIC_FMIN_RTN_32                         = 0x2,
++	TC_OP_ATOMIC_FMAX_RTN_32                         = 0x3,
++	TC_OP_RESERVED_FOP_RTN_32_0                      = 0x4,
++	TC_OP_RESERVED_FOP_RTN_32_1                      = 0x5,
++	TC_OP_RESERVED_FOP_RTN_32_2                      = 0x6,
++	TC_OP_ATOMIC_SWAP_RTN_32                         = 0x7,
++	TC_OP_ATOMIC_CMPSWAP_RTN_32                      = 0x8,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32        = 0x9,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32            = 0xa,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32            = 0xb,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0         = 0xc,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1         = 0xd,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2         = 0xe,
++	TC_OP_ATOMIC_ADD_RTN_32                          = 0xf,
++	TC_OP_ATOMIC_SUB_RTN_32                          = 0x10,
++	TC_OP_ATOMIC_SMIN_RTN_32                         = 0x11,
++	TC_OP_ATOMIC_UMIN_RTN_32                         = 0x12,
++	TC_OP_ATOMIC_SMAX_RTN_32                         = 0x13,
++	TC_OP_ATOMIC_UMAX_RTN_32                         = 0x14,
++	TC_OP_ATOMIC_AND_RTN_32                          = 0x15,
++	TC_OP_ATOMIC_OR_RTN_32                           = 0x16,
++	TC_OP_ATOMIC_XOR_RTN_32                          = 0x17,
++	TC_OP_ATOMIC_INC_RTN_32                          = 0x18,
++	TC_OP_ATOMIC_DEC_RTN_32                          = 0x19,
++	TC_OP_WBINVL1_VOL                                = 0x1a,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_0                = 0x1b,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_1                = 0x1c,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_2                = 0x1d,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_3                = 0x1e,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_4                = 0x1f,
++	TC_OP_WRITE                                      = 0x20,
++	TC_OP_ATOMIC_FCMPSWAP_RTN_64                     = 0x21,
++	TC_OP_ATOMIC_FMIN_RTN_64                         = 0x22,
++	TC_OP_ATOMIC_FMAX_RTN_64                         = 0x23,
++	TC_OP_RESERVED_FOP_RTN_64_0                      = 0x24,
++	TC_OP_RESERVED_FOP_RTN_64_1                      = 0x25,
++	TC_OP_RESERVED_FOP_RTN_64_2                      = 0x26,
++	TC_OP_ATOMIC_SWAP_RTN_64                         = 0x27,
++	TC_OP_ATOMIC_CMPSWAP_RTN_64                      = 0x28,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64        = 0x29,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64            = 0x2a,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64            = 0x2b,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0         = 0x2c,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1         = 0x2d,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2         = 0x2e,
++	TC_OP_ATOMIC_ADD_RTN_64                          = 0x2f,
++	TC_OP_ATOMIC_SUB_RTN_64                          = 0x30,
++	TC_OP_ATOMIC_SMIN_RTN_64                         = 0x31,
++	TC_OP_ATOMIC_UMIN_RTN_64                         = 0x32,
++	TC_OP_ATOMIC_SMAX_RTN_64                         = 0x33,
++	TC_OP_ATOMIC_UMAX_RTN_64                         = 0x34,
++	TC_OP_ATOMIC_AND_RTN_64                          = 0x35,
++	TC_OP_ATOMIC_OR_RTN_64                           = 0x36,
++	TC_OP_ATOMIC_XOR_RTN_64                          = 0x37,
++	TC_OP_ATOMIC_INC_RTN_64                          = 0x38,
++	TC_OP_ATOMIC_DEC_RTN_64                          = 0x39,
++	TC_OP_WBL2_VOL                                   = 0x3a,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_0                = 0x3b,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_1                = 0x3c,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_2                = 0x3d,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_3                = 0x3e,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_4                = 0x3f,
++	TC_OP_WBINVL1                                    = 0x40,
++	TC_OP_ATOMIC_FCMPSWAP_32                         = 0x41,
++	TC_OP_ATOMIC_FMIN_32                             = 0x42,
++	TC_OP_ATOMIC_FMAX_32                             = 0x43,
++	TC_OP_RESERVED_FOP_32_0                          = 0x44,
++	TC_OP_RESERVED_FOP_32_1                          = 0x45,
++	TC_OP_RESERVED_FOP_32_2                          = 0x46,
++	TC_OP_ATOMIC_SWAP_32                             = 0x47,
++	TC_OP_ATOMIC_CMPSWAP_32                          = 0x48,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32            = 0x49,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32                = 0x4a,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32                = 0x4b,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0             = 0x4c,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1             = 0x4d,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2             = 0x4e,
++	TC_OP_ATOMIC_ADD_32                              = 0x4f,
++	TC_OP_ATOMIC_SUB_32                              = 0x50,
++	TC_OP_ATOMIC_SMIN_32                             = 0x51,
++	TC_OP_ATOMIC_UMIN_32                             = 0x52,
++	TC_OP_ATOMIC_SMAX_32                             = 0x53,
++	TC_OP_ATOMIC_UMAX_32                             = 0x54,
++	TC_OP_ATOMIC_AND_32                              = 0x55,
++	TC_OP_ATOMIC_OR_32                               = 0x56,
++	TC_OP_ATOMIC_XOR_32                              = 0x57,
++	TC_OP_ATOMIC_INC_32                              = 0x58,
++	TC_OP_ATOMIC_DEC_32                              = 0x59,
++	TC_OP_INVL2_VOL                                  = 0x5a,
++	TC_OP_RESERVED_NON_FLOAT_32_0                    = 0x5b,
++	TC_OP_RESERVED_NON_FLOAT_32_1                    = 0x5c,
++	TC_OP_RESERVED_NON_FLOAT_32_2                    = 0x5d,
++	TC_OP_RESERVED_NON_FLOAT_32_3                    = 0x5e,
++	TC_OP_RESERVED_NON_FLOAT_32_4                    = 0x5f,
++	TC_OP_WBINVL2                                    = 0x60,
++	TC_OP_ATOMIC_FCMPSWAP_64                         = 0x61,
++	TC_OP_ATOMIC_FMIN_64                             = 0x62,
++	TC_OP_ATOMIC_FMAX_64                             = 0x63,
++	TC_OP_RESERVED_FOP_64_0                          = 0x64,
++	TC_OP_RESERVED_FOP_64_1                          = 0x65,
++	TC_OP_RESERVED_FOP_64_2                          = 0x66,
++	TC_OP_ATOMIC_SWAP_64                             = 0x67,
++	TC_OP_ATOMIC_CMPSWAP_64                          = 0x68,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64            = 0x69,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64                = 0x6a,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64                = 0x6b,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0             = 0x6c,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1             = 0x6d,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2             = 0x6e,
++	TC_OP_ATOMIC_ADD_64                              = 0x6f,
++	TC_OP_ATOMIC_SUB_64                              = 0x70,
++	TC_OP_ATOMIC_SMIN_64                             = 0x71,
++	TC_OP_ATOMIC_UMIN_64                             = 0x72,
++	TC_OP_ATOMIC_SMAX_64                             = 0x73,
++	TC_OP_ATOMIC_UMAX_64                             = 0x74,
++	TC_OP_ATOMIC_AND_64                              = 0x75,
++	TC_OP_ATOMIC_OR_64                               = 0x76,
++	TC_OP_ATOMIC_XOR_64                              = 0x77,
++	TC_OP_ATOMIC_INC_64                              = 0x78,
++	TC_OP_ATOMIC_DEC_64                              = 0x79,
++	TC_OP_INVL1L2_VOL                                = 0x7a,
++	TC_OP_RESERVED_NON_FLOAT_64_0                    = 0x7b,
++	TC_OP_RESERVED_NON_FLOAT_64_1                    = 0x7c,
++	TC_OP_RESERVED_NON_FLOAT_64_2                    = 0x7d,
++	TC_OP_RESERVED_NON_FLOAT_64_3                    = 0x7e,
++	TC_OP_RESERVED_NON_FLOAT_64_4                    = 0x7f,
++} TC_OP;
++typedef enum TC_CHUB_REQ_CREDITS_ENUM {
++	TC_CHUB_REQ_CREDITS                              = 0x10,
++} TC_CHUB_REQ_CREDITS_ENUM;
++typedef enum CHUB_TC_RET_CREDITS_ENUM {
++	CHUB_TC_RET_CREDITS                              = 0x20,
++} CHUB_TC_RET_CREDITS_ENUM;
++typedef enum TC_NACKS {
++	TC_NACK_NO_FAULT                                 = 0x0,
++	TC_NACK_PAGE_FAULT                               = 0x1,
++	TC_NACK_PROTECTION_FAULT                         = 0x2,
++	TC_NACK_DATA_ERROR                               = 0x3,
++} TC_NACKS;
++typedef enum TCC_PERF_SEL {
++	TCC_PERF_SEL_NONE                                = 0x0,
++	TCC_PERF_SEL_CYCLE                               = 0x1,
++	TCC_PERF_SEL_BUSY                                = 0x2,
++	TCC_PERF_SEL_REQ                                 = 0x3,
++	TCC_PERF_SEL_STREAMING_REQ                       = 0x4,
++	TCC_PERF_SEL_READ                                = 0x5,
++	TCC_PERF_SEL_WRITE                               = 0x6,
++	TCC_PERF_SEL_ATOMIC                              = 0x7,
++	TCC_PERF_SEL_WBINVL2                             = 0x8,
++	TCC_PERF_SEL_WBINVL2_CYCLE                       = 0x9,
++	TCC_PERF_SEL_HIT                                 = 0xa,
++	TCC_PERF_SEL_MISS                                = 0xb,
++	TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT                = 0xc,
++	TCC_PERF_SEL_FULLY_WRITTEN_HIT                   = 0xd,
++	TCC_PERF_SEL_WRITEBACK                           = 0xe,
++	TCC_PERF_SEL_LATENCY_FIFO_FULL                   = 0xf,
++	TCC_PERF_SEL_SRC_FIFO_FULL                       = 0x10,
++	TCC_PERF_SEL_HOLE_FIFO_FULL                      = 0x11,
++	TCC_PERF_SEL_MC_WRREQ                            = 0x12,
++	TCC_PERF_SEL_MC_WRREQ_STALL                      = 0x13,
++	TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL               = 0x14,
++	TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL              = 0x15,
++	TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL            = 0x16,
++	TCC_PERF_SEL_MC_WRREQ_LEVEL                      = 0x17,
++	TCC_PERF_SEL_MC_RDREQ                            = 0x18,
++	TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL               = 0x19,
++	TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL              = 0x1a,
++	TCC_PERF_SEL_MC_RDREQ_LEVEL                      = 0x1b,
++	TCC_PERF_SEL_TAG_STALL                           = 0x1c,
++	TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL             = 0x1d,
++	TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x1e,
++	TCC_PERF_SEL_READ_RETURN_TIMEOUT                 = 0x1f,
++	TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT              = 0x20,
++	TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE             = 0x21,
++	TCC_PERF_SEL_BUBBLE                              = 0x22,
++	TCC_PERF_SEL_RETURN_ACK                          = 0x23,
++	TCC_PERF_SEL_RETURN_DATA                         = 0x24,
++	TCC_PERF_SEL_RETURN_HOLE                         = 0x25,
++	TCC_PERF_SEL_RETURN_ACK_HOLE                     = 0x26,
++	TCC_PERF_SEL_IB_STALL                            = 0x27,
++	TCC_PERF_SEL_TCA_LEVEL                           = 0x28,
++	TCC_PERF_SEL_HOLE_LEVEL                          = 0x29,
++	TCC_PERF_SEL_MC_RDRET_NACK                       = 0x2a,
++	TCC_PERF_SEL_MC_WRRET_NACK                       = 0x2b,
++	TCC_PERF_SEL_EXE_REQ                             = 0x2c,
++	TCC_PERF_SEL_CLIENT0_REQ                         = 0x40,
++	TCC_PERF_SEL_CLIENT1_REQ                         = 0x41,
++	TCC_PERF_SEL_CLIENT2_REQ                         = 0x42,
++	TCC_PERF_SEL_CLIENT3_REQ                         = 0x43,
++	TCC_PERF_SEL_CLIENT4_REQ                         = 0x44,
++	TCC_PERF_SEL_CLIENT5_REQ                         = 0x45,
++	TCC_PERF_SEL_CLIENT6_REQ                         = 0x46,
++	TCC_PERF_SEL_CLIENT7_REQ                         = 0x47,
++	TCC_PERF_SEL_CLIENT8_REQ                         = 0x48,
++	TCC_PERF_SEL_CLIENT9_REQ                         = 0x49,
++	TCC_PERF_SEL_CLIENT10_REQ                        = 0x4a,
++	TCC_PERF_SEL_CLIENT11_REQ                        = 0x4b,
++	TCC_PERF_SEL_CLIENT12_REQ                        = 0x4c,
++	TCC_PERF_SEL_CLIENT13_REQ                        = 0x4d,
++	TCC_PERF_SEL_CLIENT14_REQ                        = 0x4e,
++	TCC_PERF_SEL_CLIENT15_REQ                        = 0x4f,
++	TCC_PERF_SEL_CLIENT16_REQ                        = 0x50,
++	TCC_PERF_SEL_CLIENT17_REQ                        = 0x51,
++	TCC_PERF_SEL_CLIENT18_REQ                        = 0x52,
++	TCC_PERF_SEL_CLIENT19_REQ                        = 0x53,
++	TCC_PERF_SEL_CLIENT20_REQ                        = 0x54,
++	TCC_PERF_SEL_CLIENT21_REQ                        = 0x55,
++	TCC_PERF_SEL_CLIENT22_REQ                        = 0x56,
++	TCC_PERF_SEL_CLIENT23_REQ                        = 0x57,
++	TCC_PERF_SEL_CLIENT24_REQ                        = 0x58,
++	TCC_PERF_SEL_CLIENT25_REQ                        = 0x59,
++	TCC_PERF_SEL_CLIENT26_REQ                        = 0x5a,
++	TCC_PERF_SEL_CLIENT27_REQ                        = 0x5b,
++	TCC_PERF_SEL_CLIENT28_REQ                        = 0x5c,
++	TCC_PERF_SEL_CLIENT29_REQ                        = 0x5d,
++	TCC_PERF_SEL_CLIENT30_REQ                        = 0x5e,
++	TCC_PERF_SEL_CLIENT31_REQ                        = 0x5f,
++	TCC_PERF_SEL_CLIENT32_REQ                        = 0x60,
++	TCC_PERF_SEL_CLIENT33_REQ                        = 0x61,
++	TCC_PERF_SEL_CLIENT34_REQ                        = 0x62,
++	TCC_PERF_SEL_CLIENT35_REQ                        = 0x63,
++	TCC_PERF_SEL_CLIENT36_REQ                        = 0x64,
++	TCC_PERF_SEL_CLIENT37_REQ                        = 0x65,
++	TCC_PERF_SEL_CLIENT38_REQ                        = 0x66,
++	TCC_PERF_SEL_CLIENT39_REQ                        = 0x67,
++	TCC_PERF_SEL_CLIENT40_REQ                        = 0x68,
++	TCC_PERF_SEL_CLIENT41_REQ                        = 0x69,
++	TCC_PERF_SEL_CLIENT42_REQ                        = 0x6a,
++	TCC_PERF_SEL_CLIENT43_REQ                        = 0x6b,
++	TCC_PERF_SEL_CLIENT44_REQ                        = 0x6c,
++	TCC_PERF_SEL_CLIENT45_REQ                        = 0x6d,
++	TCC_PERF_SEL_CLIENT46_REQ                        = 0x6e,
++	TCC_PERF_SEL_CLIENT47_REQ                        = 0x6f,
++	TCC_PERF_SEL_CLIENT48_REQ                        = 0x70,
++	TCC_PERF_SEL_CLIENT49_REQ                        = 0x71,
++	TCC_PERF_SEL_CLIENT50_REQ                        = 0x72,
++	TCC_PERF_SEL_CLIENT51_REQ                        = 0x73,
++	TCC_PERF_SEL_CLIENT52_REQ                        = 0x74,
++	TCC_PERF_SEL_CLIENT53_REQ                        = 0x75,
++	TCC_PERF_SEL_CLIENT54_REQ                        = 0x76,
++	TCC_PERF_SEL_CLIENT55_REQ                        = 0x77,
++	TCC_PERF_SEL_CLIENT56_REQ                        = 0x78,
++	TCC_PERF_SEL_CLIENT57_REQ                        = 0x79,
++	TCC_PERF_SEL_CLIENT58_REQ                        = 0x7a,
++	TCC_PERF_SEL_CLIENT59_REQ                        = 0x7b,
++	TCC_PERF_SEL_CLIENT60_REQ                        = 0x7c,
++	TCC_PERF_SEL_CLIENT61_REQ                        = 0x7d,
++	TCC_PERF_SEL_CLIENT62_REQ                        = 0x7e,
++	TCC_PERF_SEL_CLIENT63_REQ                        = 0x7f,
++	TCC_PERF_SEL_NORMAL_WRITEBACK                    = 0x80,
++	TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK            = 0x81,
++	TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK             = 0x82,
++	TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK              = 0x83,
++	TCC_PERF_SEL_NORMAL_EVICT                        = 0x84,
++	TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT               = 0x85,
++	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT             = 0x86,
++	TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT                = 0x87,
++	TCC_PERF_SEL_TC_OP_WBINVL2_EVICT                 = 0x88,
++	TCC_PERF_SEL_ALL_TC_OP_INV_EVICT                 = 0x89,
++	TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT             = 0x8a,
++	TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE                = 0x8b,
++	TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE               = 0x8c,
++	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE             = 0x8d,
++	TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE                 = 0x8e,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE           = 0x8f,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE       = 0x90,
++	TCC_PERF_SEL_TC_OP_WBL2_VOL_START                = 0x91,
++	TCC_PERF_SEL_TC_OP_INVL2_VOL_START               = 0x92,
++	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START             = 0x93,
++	TCC_PERF_SEL_TC_OP_WBINVL2_START                 = 0x94,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START           = 0x95,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START       = 0x96,
++	TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH               = 0x97,
++	TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH              = 0x98,
++	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH            = 0x99,
++	TCC_PERF_SEL_TC_OP_WBINVL2_FINISH                = 0x9a,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH          = 0x9b,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH      = 0x9c,
++	TCC_PERF_SEL_VOL_MC_WRREQ                        = 0x9d,
++	TCC_PERF_SEL_VOL_MC_RDREQ                        = 0x9e,
++	TCC_PERF_SEL_VOL_REQ                             = 0x9f,
++} TCC_PERF_SEL;
++typedef enum TCA_PERF_SEL {
++	TCA_PERF_SEL_NONE                                = 0x0,
++	TCA_PERF_SEL_CYCLE                               = 0x1,
++	TCA_PERF_SEL_BUSY                                = 0x2,
++	TCA_PERF_SEL_FORCED_HOLE_TCC0                    = 0x3,
++	TCA_PERF_SEL_FORCED_HOLE_TCC1                    = 0x4,
++	TCA_PERF_SEL_FORCED_HOLE_TCC2                    = 0x5,
++	TCA_PERF_SEL_FORCED_HOLE_TCC3                    = 0x6,
++	TCA_PERF_SEL_FORCED_HOLE_TCC4                    = 0x7,
++	TCA_PERF_SEL_FORCED_HOLE_TCC5                    = 0x8,
++	TCA_PERF_SEL_FORCED_HOLE_TCC6                    = 0x9,
++	TCA_PERF_SEL_FORCED_HOLE_TCC7                    = 0xa,
++	TCA_PERF_SEL_REQ_TCC0                            = 0xb,
++	TCA_PERF_SEL_REQ_TCC1                            = 0xc,
++	TCA_PERF_SEL_REQ_TCC2                            = 0xd,
++	TCA_PERF_SEL_REQ_TCC3                            = 0xe,
++	TCA_PERF_SEL_REQ_TCC4                            = 0xf,
++	TCA_PERF_SEL_REQ_TCC5                            = 0x10,
++	TCA_PERF_SEL_REQ_TCC6                            = 0x11,
++	TCA_PERF_SEL_REQ_TCC7                            = 0x12,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0            = 0x13,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1            = 0x14,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2            = 0x15,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3            = 0x16,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4            = 0x17,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5            = 0x18,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6            = 0x19,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7            = 0x1a,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC0                 = 0x1b,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC1                 = 0x1c,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC2                 = 0x1d,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC3                 = 0x1e,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC4                 = 0x1f,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC5                 = 0x20,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC6                 = 0x21,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC7                 = 0x22,
++	TCA_PERF_SEL_FORCED_HOLE_TCS                     = 0x23,
++	TCA_PERF_SEL_REQ_TCS                             = 0x24,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS             = 0x25,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCS                  = 0x26,
++} TCA_PERF_SEL;
++typedef enum TCS_PERF_SEL {
++	TCS_PERF_SEL_NONE                                = 0x0,
++	TCS_PERF_SEL_CYCLE                               = 0x1,
++	TCS_PERF_SEL_BUSY                                = 0x2,
++	TCS_PERF_SEL_REQ                                 = 0x3,
++	TCS_PERF_SEL_READ                                = 0x4,
++	TCS_PERF_SEL_WRITE                               = 0x5,
++	TCS_PERF_SEL_ATOMIC                              = 0x6,
++	TCS_PERF_SEL_HOLE_FIFO_FULL                      = 0x7,
++	TCS_PERF_SEL_REQ_FIFO_FULL                       = 0x8,
++	TCS_PERF_SEL_REQ_CREDIT_STALL                    = 0x9,
++	TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL               = 0xa,
++	TCS_PERF_SEL_REQ_STALL                           = 0xb,
++	TCS_PERF_SEL_TCS_CHUB_REQ_SEND                   = 0xc,
++	TCS_PERF_SEL_CHUB_TCS_RET_SEND                   = 0xd,
++	TCS_PERF_SEL_RETURN_ACK                          = 0xe,
++	TCS_PERF_SEL_RETURN_DATA                         = 0xf,
++	TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL             = 0x10,
++	TCS_PERF_SEL_IB_STALL                            = 0x11,
++	TCS_PERF_SEL_TCA_LEVEL                           = 0x12,
++	TCS_PERF_SEL_HOLE_LEVEL                          = 0x13,
++	TCS_PERF_SEL_CHUB_LEVEL                          = 0x14,
++	TCS_PERF_SEL_CLIENT0_REQ                         = 0x40,
++	TCS_PERF_SEL_CLIENT1_REQ                         = 0x41,
++	TCS_PERF_SEL_CLIENT2_REQ                         = 0x42,
++	TCS_PERF_SEL_CLIENT3_REQ                         = 0x43,
++	TCS_PERF_SEL_CLIENT4_REQ                         = 0x44,
++	TCS_PERF_SEL_CLIENT5_REQ                         = 0x45,
++	TCS_PERF_SEL_CLIENT6_REQ                         = 0x46,
++	TCS_PERF_SEL_CLIENT7_REQ                         = 0x47,
++	TCS_PERF_SEL_CLIENT8_REQ                         = 0x48,
++	TCS_PERF_SEL_CLIENT9_REQ                         = 0x49,
++	TCS_PERF_SEL_CLIENT10_REQ                        = 0x4a,
++	TCS_PERF_SEL_CLIENT11_REQ                        = 0x4b,
++	TCS_PERF_SEL_CLIENT12_REQ                        = 0x4c,
++	TCS_PERF_SEL_CLIENT13_REQ                        = 0x4d,
++	TCS_PERF_SEL_CLIENT14_REQ                        = 0x4e,
++	TCS_PERF_SEL_CLIENT15_REQ                        = 0x4f,
++	TCS_PERF_SEL_CLIENT16_REQ                        = 0x50,
++	TCS_PERF_SEL_CLIENT17_REQ                        = 0x51,
++	TCS_PERF_SEL_CLIENT18_REQ                        = 0x52,
++	TCS_PERF_SEL_CLIENT19_REQ                        = 0x53,
++	TCS_PERF_SEL_CLIENT20_REQ                        = 0x54,
++	TCS_PERF_SEL_CLIENT21_REQ                        = 0x55,
++	TCS_PERF_SEL_CLIENT22_REQ                        = 0x56,
++	TCS_PERF_SEL_CLIENT23_REQ                        = 0x57,
++	TCS_PERF_SEL_CLIENT24_REQ                        = 0x58,
++	TCS_PERF_SEL_CLIENT25_REQ                        = 0x59,
++	TCS_PERF_SEL_CLIENT26_REQ                        = 0x5a,
++	TCS_PERF_SEL_CLIENT27_REQ                        = 0x5b,
++	TCS_PERF_SEL_CLIENT28_REQ                        = 0x5c,
++	TCS_PERF_SEL_CLIENT29_REQ                        = 0x5d,
++	TCS_PERF_SEL_CLIENT30_REQ                        = 0x5e,
++	TCS_PERF_SEL_CLIENT31_REQ                        = 0x5f,
++	TCS_PERF_SEL_CLIENT32_REQ                        = 0x60,
++	TCS_PERF_SEL_CLIENT33_REQ                        = 0x61,
++	TCS_PERF_SEL_CLIENT34_REQ                        = 0x62,
++	TCS_PERF_SEL_CLIENT35_REQ                        = 0x63,
++	TCS_PERF_SEL_CLIENT36_REQ                        = 0x64,
++	TCS_PERF_SEL_CLIENT37_REQ                        = 0x65,
++	TCS_PERF_SEL_CLIENT38_REQ                        = 0x66,
++	TCS_PERF_SEL_CLIENT39_REQ                        = 0x67,
++	TCS_PERF_SEL_CLIENT40_REQ                        = 0x68,
++	TCS_PERF_SEL_CLIENT41_REQ                        = 0x69,
++	TCS_PERF_SEL_CLIENT42_REQ                        = 0x6a,
++	TCS_PERF_SEL_CLIENT43_REQ                        = 0x6b,
++	TCS_PERF_SEL_CLIENT44_REQ                        = 0x6c,
++	TCS_PERF_SEL_CLIENT45_REQ                        = 0x6d,
++	TCS_PERF_SEL_CLIENT46_REQ                        = 0x6e,
++	TCS_PERF_SEL_CLIENT47_REQ                        = 0x6f,
++	TCS_PERF_SEL_CLIENT48_REQ                        = 0x70,
++	TCS_PERF_SEL_CLIENT49_REQ                        = 0x71,
++	TCS_PERF_SEL_CLIENT50_REQ                        = 0x72,
++	TCS_PERF_SEL_CLIENT51_REQ                        = 0x73,
++	TCS_PERF_SEL_CLIENT52_REQ                        = 0x74,
++	TCS_PERF_SEL_CLIENT53_REQ                        = 0x75,
++	TCS_PERF_SEL_CLIENT54_REQ                        = 0x76,
++	TCS_PERF_SEL_CLIENT55_REQ                        = 0x77,
++	TCS_PERF_SEL_CLIENT56_REQ                        = 0x78,
++	TCS_PERF_SEL_CLIENT57_REQ                        = 0x79,
++	TCS_PERF_SEL_CLIENT58_REQ                        = 0x7a,
++	TCS_PERF_SEL_CLIENT59_REQ                        = 0x7b,
++	TCS_PERF_SEL_CLIENT60_REQ                        = 0x7c,
++	TCS_PERF_SEL_CLIENT61_REQ                        = 0x7d,
++	TCS_PERF_SEL_CLIENT62_REQ                        = 0x7e,
++	TCS_PERF_SEL_CLIENT63_REQ                        = 0x7f,
++} TCS_PERF_SEL;
++typedef enum TA_TC_ADDR_MODES {
++	TA_TC_ADDR_MODE_DEFAULT                          = 0x0,
++	TA_TC_ADDR_MODE_COMP0                            = 0x1,
++	TA_TC_ADDR_MODE_COMP1                            = 0x2,
++	TA_TC_ADDR_MODE_COMP2                            = 0x3,
++	TA_TC_ADDR_MODE_COMP3                            = 0x4,
++	TA_TC_ADDR_MODE_UNALIGNED                        = 0x5,
++	TA_TC_ADDR_MODE_BORDER_COLOR                     = 0x6,
++} TA_TC_ADDR_MODES;
++typedef enum TA_PERFCOUNT_SEL {
++	TA_PERF_SEL_ta_busy                              = 0x0,
++	TA_PERF_SEL_sh_fifo_busy                         = 0x1,
++	TA_PERF_SEL_sh_fifo_cmd_busy                     = 0x2,
++	TA_PERF_SEL_sh_fifo_addr_busy                    = 0x3,
++	TA_PERF_SEL_sh_fifo_data_busy                    = 0x4,
++	TA_PERF_SEL_sh_fifo_data_sfifo_busy              = 0x5,
++	TA_PERF_SEL_sh_fifo_data_tfifo_busy              = 0x6,
++	TA_PERF_SEL_gradient_busy                        = 0x7,
++	TA_PERF_SEL_gradient_fifo_busy                   = 0x8,
++	TA_PERF_SEL_lod_busy                             = 0x9,
++	TA_PERF_SEL_lod_fifo_busy                        = 0xa,
++	TA_PERF_SEL_addresser_busy                       = 0xb,
++	TA_PERF_SEL_addresser_fifo_busy                  = 0xc,
++	TA_PERF_SEL_aligner_busy                         = 0xd,
++	TA_PERF_SEL_write_path_busy                      = 0xe,
++	TA_PERF_SEL_RESERVED_15                          = 0xf,
++	TA_PERF_SEL_sq_ta_cmd_cycles                     = 0x10,
++	TA_PERF_SEL_sp_ta_addr_cycles                    = 0x11,
++	TA_PERF_SEL_sp_ta_data_cycles                    = 0x12,
++	TA_PERF_SEL_ta_fa_data_state_cycles              = 0x13,
++	TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles   = 0x14,
++	TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles   = 0x15,
++	TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
++	TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
++	TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
++	TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
++	TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
++	TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
++	TA_PERF_SEL_RESERVED_28                          = 0x1c,
++	TA_PERF_SEL_RESERVED_29                          = 0x1d,
++	TA_PERF_SEL_sh_fifo_addr_cycles                  = 0x1e,
++	TA_PERF_SEL_sh_fifo_data_cycles                  = 0x1f,
++	TA_PERF_SEL_total_wavefronts                     = 0x20,
++	TA_PERF_SEL_gradient_cycles                      = 0x21,
++	TA_PERF_SEL_walker_cycles                        = 0x22,
++	TA_PERF_SEL_aligner_cycles                       = 0x23,
++	TA_PERF_SEL_image_wavefronts                     = 0x24,
++	TA_PERF_SEL_image_read_wavefronts                = 0x25,
++	TA_PERF_SEL_image_write_wavefronts               = 0x26,
++	TA_PERF_SEL_image_atomic_wavefronts              = 0x27,
++	TA_PERF_SEL_image_total_cycles                   = 0x28,
++	TA_PERF_SEL_RESERVED_41                          = 0x29,
++	TA_PERF_SEL_RESERVED_42                          = 0x2a,
++	TA_PERF_SEL_RESERVED_43                          = 0x2b,
++	TA_PERF_SEL_buffer_wavefronts                    = 0x2c,
++	TA_PERF_SEL_buffer_read_wavefronts               = 0x2d,
++	TA_PERF_SEL_buffer_write_wavefronts              = 0x2e,
++	TA_PERF_SEL_buffer_atomic_wavefronts             = 0x2f,
++	TA_PERF_SEL_buffer_coalescable_wavefronts        = 0x30,
++	TA_PERF_SEL_buffer_total_cycles                  = 0x31,
++	TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
++	TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
++	TA_PERF_SEL_buffer_coalesced_read_cycles         = 0x34,
++	TA_PERF_SEL_buffer_coalesced_write_cycles        = 0x35,
++	TA_PERF_SEL_addr_stalled_by_tc_cycles            = 0x36,
++	TA_PERF_SEL_addr_stalled_by_td_cycles            = 0x37,
++	TA_PERF_SEL_data_stalled_by_tc_cycles            = 0x38,
++	TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
++	TA_PERF_SEL_addresser_stalled_cycles             = 0x3a,
++	TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
++	TA_PERF_SEL_aniso_stalled_cycles                 = 0x3c,
++	TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles   = 0x3d,
++	TA_PERF_SEL_deriv_stalled_cycles                 = 0x3e,
++	TA_PERF_SEL_aniso_gt1_cycle_quads                = 0x3f,
++	TA_PERF_SEL_color_1_cycle_pixels                 = 0x40,
++	TA_PERF_SEL_color_2_cycle_pixels                 = 0x41,
++	TA_PERF_SEL_color_3_cycle_pixels                 = 0x42,
++	TA_PERF_SEL_color_4_cycle_pixels                 = 0x43,
++	TA_PERF_SEL_mip_1_cycle_pixels                   = 0x44,
++	TA_PERF_SEL_mip_2_cycle_pixels                   = 0x45,
++	TA_PERF_SEL_vol_1_cycle_pixels                   = 0x46,
++	TA_PERF_SEL_vol_2_cycle_pixels                   = 0x47,
++	TA_PERF_SEL_bilin_point_1_cycle_pixels           = 0x48,
++	TA_PERF_SEL_mipmap_lod_0_samples                 = 0x49,
++	TA_PERF_SEL_mipmap_lod_1_samples                 = 0x4a,
++	TA_PERF_SEL_mipmap_lod_2_samples                 = 0x4b,
++	TA_PERF_SEL_mipmap_lod_3_samples                 = 0x4c,
++	TA_PERF_SEL_mipmap_lod_4_samples                 = 0x4d,
++	TA_PERF_SEL_mipmap_lod_5_samples                 = 0x4e,
++	TA_PERF_SEL_mipmap_lod_6_samples                 = 0x4f,
++	TA_PERF_SEL_mipmap_lod_7_samples                 = 0x50,
++	TA_PERF_SEL_mipmap_lod_8_samples                 = 0x51,
++	TA_PERF_SEL_mipmap_lod_9_samples                 = 0x52,
++	TA_PERF_SEL_mipmap_lod_10_samples                = 0x53,
++	TA_PERF_SEL_mipmap_lod_11_samples                = 0x54,
++	TA_PERF_SEL_mipmap_lod_12_samples                = 0x55,
++	TA_PERF_SEL_mipmap_lod_13_samples                = 0x56,
++	TA_PERF_SEL_mipmap_lod_14_samples                = 0x57,
++	TA_PERF_SEL_mipmap_invalid_samples               = 0x58,
++	TA_PERF_SEL_aniso_1_cycle_quads                  = 0x59,
++	TA_PERF_SEL_aniso_2_cycle_quads                  = 0x5a,
++	TA_PERF_SEL_aniso_4_cycle_quads                  = 0x5b,
++	TA_PERF_SEL_aniso_6_cycle_quads                  = 0x5c,
++	TA_PERF_SEL_aniso_8_cycle_quads                  = 0x5d,
++	TA_PERF_SEL_aniso_10_cycle_quads                 = 0x5e,
++	TA_PERF_SEL_aniso_12_cycle_quads                 = 0x5f,
++	TA_PERF_SEL_aniso_14_cycle_quads                 = 0x60,
++	TA_PERF_SEL_aniso_16_cycle_quads                 = 0x61,
++	TA_PERF_SEL_write_path_input_cycles              = 0x62,
++	TA_PERF_SEL_write_path_output_cycles             = 0x63,
++	TA_PERF_SEL_flat_wavefronts                      = 0x64,
++	TA_PERF_SEL_flat_read_wavefronts                 = 0x65,
++	TA_PERF_SEL_flat_write_wavefronts                = 0x66,
++	TA_PERF_SEL_flat_atomic_wavefronts               = 0x67,
++	TA_PERF_SEL_flat_coalesceable_wavefronts         = 0x68,
++	TA_PERF_SEL_reg_sclk_vld                         = 0x69,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6a,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x6b,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en       = 0x6c,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x6d,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x6e,
++} TA_PERFCOUNT_SEL;
++typedef enum TD_PERFCOUNT_SEL {
++	TD_PERF_SEL_td_busy                              = 0x0,
++	TD_PERF_SEL_input_busy                           = 0x1,
++	TD_PERF_SEL_output_busy                          = 0x2,
++	TD_PERF_SEL_lerp_busy                            = 0x3,
++	TD_PERF_SEL_RESERVED_4                           = 0x4,
++	TD_PERF_SEL_reg_sclk_vld                         = 0x5,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x7,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x8,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x9,
++	TD_PERF_SEL_tc_td_fifo_full                      = 0xa,
++	TD_PERF_SEL_constant_state_full                  = 0xb,
++	TD_PERF_SEL_sample_state_full                    = 0xc,
++	TD_PERF_SEL_output_fifo_full                     = 0xd,
++	TD_PERF_SEL_RESERVED_14                          = 0xe,
++	TD_PERF_SEL_tc_stall                             = 0xf,
++	TD_PERF_SEL_pc_stall                             = 0x10,
++	TD_PERF_SEL_gds_stall                            = 0x11,
++	TD_PERF_SEL_RESERVED_18                          = 0x12,
++	TD_PERF_SEL_RESERVED_19                          = 0x13,
++	TD_PERF_SEL_gather4_wavefront                    = 0x14,
++	TD_PERF_SEL_sample_c_wavefront                   = 0x15,
++	TD_PERF_SEL_load_wavefront                       = 0x16,
++	TD_PERF_SEL_atomic_wavefront                     = 0x17,
++	TD_PERF_SEL_store_wavefront                      = 0x18,
++	TD_PERF_SEL_ldfptr_wavefront                     = 0x19,
++	TD_PERF_SEL_RESERVED_26                          = 0x1a,
++	TD_PERF_SEL_RESERVED_27                          = 0x1b,
++	TD_PERF_SEL_RESERVED_28                          = 0x1c,
++	TD_PERF_SEL_RESERVED_29                          = 0x1d,
++	TD_PERF_SEL_bypass_filter_wavefront              = 0x1e,
++	TD_PERF_SEL_min_max_filter_wavefront             = 0x1f,
++	TD_PERF_SEL_coalescable_wavefront                = 0x20,
++	TD_PERF_SEL_coalesced_phase                      = 0x21,
++	TD_PERF_SEL_four_phase_wavefront                 = 0x22,
++	TD_PERF_SEL_eight_phase_wavefront                = 0x23,
++	TD_PERF_SEL_sixteen_phase_wavefront              = 0x24,
++	TD_PERF_SEL_four_phase_forward_wavefront         = 0x25,
++	TD_PERF_SEL_write_ack_wavefront                  = 0x26,
++	TD_PERF_SEL_RESERVED_39                          = 0x27,
++	TD_PERF_SEL_user_defined_border                  = 0x28,
++	TD_PERF_SEL_white_border                         = 0x29,
++	TD_PERF_SEL_opaque_black_border                  = 0x2a,
++	TD_PERF_SEL_RESERVED_43                          = 0x2b,
++	TD_PERF_SEL_RESERVED_44                          = 0x2c,
++	TD_PERF_SEL_nack                                 = 0x2d,
++	TD_PERF_SEL_td_sp_traffic                        = 0x2e,
++	TD_PERF_SEL_consume_gds_traffic                  = 0x2f,
++	TD_PERF_SEL_addresscmd_poison                    = 0x30,
++	TD_PERF_SEL_data_poison                          = 0x31,
++	TD_PERF_SEL_start_cycle_0                        = 0x32,
++	TD_PERF_SEL_start_cycle_1                        = 0x33,
++	TD_PERF_SEL_start_cycle_2                        = 0x34,
++	TD_PERF_SEL_start_cycle_3                        = 0x35,
++	TD_PERF_SEL_null_cycle_output                    = 0x36,
++} TD_PERFCOUNT_SEL;
++typedef enum TCP_PERFCOUNT_SELECT {
++	TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES           = 0x0,
++	TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES           = 0x1,
++	TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES            = 0x2,
++	TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES            = 0x3,
++	TCP_PERF_SEL_TD_TCP_STALL_CYCLES                 = 0x4,
++	TCP_PERF_SEL_TCR_TCP_STALL_CYCLES                = 0x5,
++	TCP_PERF_SEL_LOD_STALL_CYCLES                    = 0x6,
++	TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES       = 0x7,
++	TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES      = 0x8,
++	TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES     = 0x9,
++	TCP_PERF_SEL_ALLOC_STALL_CYCLES                  = 0xa,
++	TCP_PERF_SEL_LFIFO_STALL_CYCLES                  = 0xb,
++	TCP_PERF_SEL_RFIFO_STALL_CYCLES                  = 0xc,
++	TCP_PERF_SEL_TCR_RDRET_STALL                     = 0xd,
++	TCP_PERF_SEL_WRITE_CONFLICT_STALL                = 0xe,
++	TCP_PERF_SEL_HOLE_READ_STALL                     = 0xf,
++	TCP_PERF_SEL_READCONFLICT_STALL_CYCLES           = 0x10,
++	TCP_PERF_SEL_PENDING_STALL_CYCLES                = 0x11,
++	TCP_PERF_SEL_READFIFO_STALL_CYCLES               = 0x12,
++	TCP_PERF_SEL_TCP_LATENCY                         = 0x13,
++	TCP_PERF_SEL_TCC_READ_REQ_LATENCY                = 0x14,
++	TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY               = 0x15,
++	TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY          = 0x16,
++	TCP_PERF_SEL_TCC_READ_REQ                        = 0x17,
++	TCP_PERF_SEL_TCC_WRITE_REQ                       = 0x18,
++	TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ             = 0x19,
++	TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ          = 0x1a,
++	TCP_PERF_SEL_TOTAL_LOCAL_READ                    = 0x1b,
++	TCP_PERF_SEL_TOTAL_GLOBAL_READ                   = 0x1c,
++	TCP_PERF_SEL_TOTAL_LOCAL_WRITE                   = 0x1d,
++	TCP_PERF_SEL_TOTAL_GLOBAL_WRITE                  = 0x1e,
++	TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET               = 0x1f,
++	TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET            = 0x20,
++	TCP_PERF_SEL_TOTAL_WBINVL1                       = 0x21,
++	TCP_PERF_SEL_IMG_READ_FMT_1                      = 0x22,
++	TCP_PERF_SEL_IMG_READ_FMT_8                      = 0x23,
++	TCP_PERF_SEL_IMG_READ_FMT_16                     = 0x24,
++	TCP_PERF_SEL_IMG_READ_FMT_32                     = 0x25,
++	TCP_PERF_SEL_IMG_READ_FMT_32_AS_8                = 0x26,
++	TCP_PERF_SEL_IMG_READ_FMT_32_AS_16               = 0x27,
++	TCP_PERF_SEL_IMG_READ_FMT_32_AS_128              = 0x28,
++	TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE             = 0x29,
++	TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE             = 0x2a,
++	TCP_PERF_SEL_IMG_READ_FMT_96                     = 0x2b,
++	TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE            = 0x2c,
++	TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE            = 0x2d,
++	TCP_PERF_SEL_IMG_READ_FMT_BC1                    = 0x2e,
++	TCP_PERF_SEL_IMG_READ_FMT_BC2                    = 0x2f,
++	TCP_PERF_SEL_IMG_READ_FMT_BC3                    = 0x30,
++	TCP_PERF_SEL_IMG_READ_FMT_BC4                    = 0x31,
++	TCP_PERF_SEL_IMG_READ_FMT_BC5                    = 0x32,
++	TCP_PERF_SEL_IMG_READ_FMT_BC6                    = 0x33,
++	TCP_PERF_SEL_IMG_READ_FMT_BC7                    = 0x34,
++	TCP_PERF_SEL_IMG_READ_FMT_I8                     = 0x35,
++	TCP_PERF_SEL_IMG_READ_FMT_I16                    = 0x36,
++	TCP_PERF_SEL_IMG_READ_FMT_I32                    = 0x37,
++	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8               = 0x38,
++	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16              = 0x39,
++	TCP_PERF_SEL_IMG_READ_FMT_D8                     = 0x3a,
++	TCP_PERF_SEL_IMG_READ_FMT_D16                    = 0x3b,
++	TCP_PERF_SEL_IMG_READ_FMT_D32                    = 0x3c,
++	TCP_PERF_SEL_IMG_WRITE_FMT_8                     = 0x3d,
++	TCP_PERF_SEL_IMG_WRITE_FMT_16                    = 0x3e,
++	TCP_PERF_SEL_IMG_WRITE_FMT_32                    = 0x3f,
++	TCP_PERF_SEL_IMG_WRITE_FMT_64                    = 0x40,
++	TCP_PERF_SEL_IMG_WRITE_FMT_128                   = 0x41,
++	TCP_PERF_SEL_IMG_WRITE_FMT_D8                    = 0x42,
++	TCP_PERF_SEL_IMG_WRITE_FMT_D16                   = 0x43,
++	TCP_PERF_SEL_IMG_WRITE_FMT_D32                   = 0x44,
++	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32          = 0x45,
++	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32       = 0x46,
++	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64          = 0x47,
++	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64       = 0x48,
++	TCP_PERF_SEL_BUF_READ_FMT_8                      = 0x49,
++	TCP_PERF_SEL_BUF_READ_FMT_16                     = 0x4a,
++	TCP_PERF_SEL_BUF_READ_FMT_32                     = 0x4b,
++	TCP_PERF_SEL_BUF_WRITE_FMT_8                     = 0x4c,
++	TCP_PERF_SEL_BUF_WRITE_FMT_16                    = 0x4d,
++	TCP_PERF_SEL_BUF_WRITE_FMT_32                    = 0x4e,
++	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32          = 0x4f,
++	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32       = 0x50,
++	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64          = 0x51,
++	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64       = 0x52,
++	TCP_PERF_SEL_ARR_LINEAR_GENERAL                  = 0x53,
++	TCP_PERF_SEL_ARR_LINEAR_ALIGNED                  = 0x54,
++	TCP_PERF_SEL_ARR_1D_THIN1                        = 0x55,
++	TCP_PERF_SEL_ARR_1D_THICK                        = 0x56,
++	TCP_PERF_SEL_ARR_2D_THIN1                        = 0x57,
++	TCP_PERF_SEL_ARR_2D_THICK                        = 0x58,
++	TCP_PERF_SEL_ARR_2D_XTHICK                       = 0x59,
++	TCP_PERF_SEL_ARR_3D_THIN1                        = 0x5a,
++	TCP_PERF_SEL_ARR_3D_THICK                        = 0x5b,
++	TCP_PERF_SEL_ARR_3D_XTHICK                       = 0x5c,
++	TCP_PERF_SEL_DIM_1D                              = 0x5d,
++	TCP_PERF_SEL_DIM_2D                              = 0x5e,
++	TCP_PERF_SEL_DIM_3D                              = 0x5f,
++	TCP_PERF_SEL_DIM_1D_ARRAY                        = 0x60,
++	TCP_PERF_SEL_DIM_2D_ARRAY                        = 0x61,
++	TCP_PERF_SEL_DIM_2D_MSAA                         = 0x62,
++	TCP_PERF_SEL_DIM_2D_ARRAY_MSAA                   = 0x63,
++	TCP_PERF_SEL_DIM_CUBE_ARRAY                      = 0x64,
++	TCP_PERF_SEL_CP_TCP_INVALIDATE                   = 0x65,
++	TCP_PERF_SEL_TA_TCP_STATE_READ                   = 0x66,
++	TCP_PERF_SEL_TAGRAM0_REQ                         = 0x67,
++	TCP_PERF_SEL_TAGRAM1_REQ                         = 0x68,
++	TCP_PERF_SEL_TAGRAM2_REQ                         = 0x69,
++	TCP_PERF_SEL_TAGRAM3_REQ                         = 0x6a,
++	TCP_PERF_SEL_GATE_EN1                            = 0x6b,
++	TCP_PERF_SEL_GATE_EN2                            = 0x6c,
++	TCP_PERF_SEL_CORE_REG_SCLK_VLD                   = 0x6d,
++	TCP_PERF_SEL_TCC_REQ                             = 0x6e,
++	TCP_PERF_SEL_TCC_NON_READ_REQ                    = 0x6f,
++	TCP_PERF_SEL_TCC_BYPASS_READ_REQ                 = 0x70,
++	TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ             = 0x71,
++	TCP_PERF_SEL_TCC_VOLATILE_READ_REQ               = 0x72,
++	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ        = 0x73,
++	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ    = 0x74,
++	TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ                = 0x75,
++	TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ            = 0x76,
++	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ       = 0x77,
++	TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ              = 0x78,
++	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ   = 0x79,
++	TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ               = 0x7a,
++	TCP_PERF_SEL_TCC_ATOMIC_REQ                      = 0x7b,
++	TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ             = 0x7c,
++	TCP_PERF_SEL_TCC_DATA_BUS_BUSY                   = 0x7d,
++	TCP_PERF_SEL_TOTAL_ACCESSES                      = 0x7e,
++	TCP_PERF_SEL_TOTAL_READ                          = 0x7f,
++	TCP_PERF_SEL_TOTAL_HIT_LRU_READ                  = 0x80,
++	TCP_PERF_SEL_TOTAL_HIT_EVICT_READ                = 0x81,
++	TCP_PERF_SEL_TOTAL_MISS_LRU_READ                 = 0x82,
++	TCP_PERF_SEL_TOTAL_MISS_EVICT_READ               = 0x83,
++	TCP_PERF_SEL_TOTAL_NON_READ                      = 0x84,
++	TCP_PERF_SEL_TOTAL_WRITE                         = 0x85,
++	TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE                = 0x86,
++	TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE              = 0x87,
++	TCP_PERF_SEL_TOTAL_WBINVL1_VOL                   = 0x88,
++	TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES         = 0x89,
++	TCP_PERF_SEL_DISPLAY_MICROTILING                 = 0x8a,
++	TCP_PERF_SEL_THIN_MICROTILING                    = 0x8b,
++	TCP_PERF_SEL_DEPTH_MICROTILING                   = 0x8c,
++	TCP_PERF_SEL_ARR_PRT_THIN1                       = 0x8d,
++	TCP_PERF_SEL_ARR_PRT_2D_THIN1                    = 0x8e,
++	TCP_PERF_SEL_ARR_PRT_3D_THIN1                    = 0x8f,
++	TCP_PERF_SEL_ARR_PRT_THICK                       = 0x90,
++	TCP_PERF_SEL_ARR_PRT_2D_THICK                    = 0x91,
++	TCP_PERF_SEL_ARR_PRT_3D_THICK                    = 0x92,
++	TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL               = 0x93,
++	TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL               = 0x94,
++	TCP_PERF_SEL_UNALIGNED                           = 0x95,
++	TCP_PERF_SEL_ROTATED_MICROTILING                 = 0x96,
++	TCP_PERF_SEL_THICK_MICROTILING                   = 0x97,
++	TCP_PERF_SEL_ATC                                 = 0x98,
++	TCP_PERF_SEL_POWER_STALL                         = 0x99,
++} TCP_PERFCOUNT_SELECT;
++typedef enum TCP_CACHE_POLICIES {
++	TCP_CACHE_POLICY_MISS_LRU                        = 0x0,
++	TCP_CACHE_POLICY_MISS_EVICT                      = 0x1,
++	TCP_CACHE_POLICY_HIT_LRU                         = 0x2,
++	TCP_CACHE_POLICY_HIT_EVICT                       = 0x3,
++} TCP_CACHE_POLICIES;
++typedef enum TCP_CACHE_STORE_POLICIES {
++	TCP_CACHE_STORE_POLICY_MISS_LRU                  = 0x0,
++	TCP_CACHE_STORE_POLICY_MISS_EVICT                = 0x1,
++} TCP_CACHE_STORE_POLICIES;
++typedef enum TCP_WATCH_MODES {
++	TCP_WATCH_MODE_READ                              = 0x0,
++	TCP_WATCH_MODE_NONREAD                           = 0x1,
++	TCP_WATCH_MODE_ATOMIC                            = 0x2,
++	TCP_WATCH_MODE_ALL                               = 0x3,
++} TCP_WATCH_MODES;
++typedef enum VGT_OUT_PRIM_TYPE {
++	VGT_OUT_POINT                                    = 0x0,
++	VGT_OUT_LINE                                     = 0x1,
++	VGT_OUT_TRI                                      = 0x2,
++	VGT_OUT_RECT_V0                                  = 0x3,
++	VGT_OUT_RECT_V1                                  = 0x4,
++	VGT_OUT_RECT_V2                                  = 0x5,
++	VGT_OUT_RECT_V3                                  = 0x6,
++	VGT_OUT_RESERVED                                 = 0x7,
++	VGT_TE_QUAD                                      = 0x8,
++	VGT_TE_PRIM_INDEX_LINE                           = 0x9,
++	VGT_TE_PRIM_INDEX_TRI                            = 0xa,
++	VGT_TE_PRIM_INDEX_QUAD                           = 0xb,
++	VGT_OUT_LINE_ADJ                                 = 0xc,
++	VGT_OUT_TRI_ADJ                                  = 0xd,
++	VGT_OUT_PATCH                                    = 0xe,
++} VGT_OUT_PRIM_TYPE;
++typedef enum VGT_DI_PRIM_TYPE {
++	DI_PT_NONE                                       = 0x0,
++	DI_PT_POINTLIST                                  = 0x1,
++	DI_PT_LINELIST                                   = 0x2,
++	DI_PT_LINESTRIP                                  = 0x3,
++	DI_PT_TRILIST                                    = 0x4,
++	DI_PT_TRIFAN                                     = 0x5,
++	DI_PT_TRISTRIP                                   = 0x6,
++	DI_PT_UNUSED_0                                   = 0x7,
++	DI_PT_UNUSED_1                                   = 0x8,
++	DI_PT_PATCH                                      = 0x9,
++	DI_PT_LINELIST_ADJ                               = 0xa,
++	DI_PT_LINESTRIP_ADJ                              = 0xb,
++	DI_PT_TRILIST_ADJ                                = 0xc,
++	DI_PT_TRISTRIP_ADJ                               = 0xd,
++	DI_PT_UNUSED_3                                   = 0xe,
++	DI_PT_UNUSED_4                                   = 0xf,
++	DI_PT_TRI_WITH_WFLAGS                            = 0x10,
++	DI_PT_RECTLIST                                   = 0x11,
++	DI_PT_LINELOOP                                   = 0x12,
++	DI_PT_QUADLIST                                   = 0x13,
++	DI_PT_QUADSTRIP                                  = 0x14,
++	DI_PT_POLYGON                                    = 0x15,
++	DI_PT_2D_COPY_RECT_LIST_V0                       = 0x16,
++	DI_PT_2D_COPY_RECT_LIST_V1                       = 0x17,
++	DI_PT_2D_COPY_RECT_LIST_V2                       = 0x18,
++	DI_PT_2D_COPY_RECT_LIST_V3                       = 0x19,
++	DI_PT_2D_FILL_RECT_LIST                          = 0x1a,
++	DI_PT_2D_LINE_STRIP                              = 0x1b,
++	DI_PT_2D_TRI_STRIP                               = 0x1c,
++} VGT_DI_PRIM_TYPE;
++typedef enum VGT_DI_SOURCE_SELECT {
++	DI_SRC_SEL_DMA                                   = 0x0,
++	DI_SRC_SEL_IMMEDIATE                             = 0x1,
++	DI_SRC_SEL_AUTO_INDEX                            = 0x2,
++	DI_SRC_SEL_RESERVED                              = 0x3,
++} VGT_DI_SOURCE_SELECT;
++typedef enum VGT_DI_MAJOR_MODE_SELECT {
++	DI_MAJOR_MODE_0                                  = 0x0,
++	DI_MAJOR_MODE_1                                  = 0x1,
++} VGT_DI_MAJOR_MODE_SELECT;
++typedef enum VGT_DI_INDEX_SIZE {
++	DI_INDEX_SIZE_16_BIT                             = 0x0,
++	DI_INDEX_SIZE_32_BIT                             = 0x1,
++} VGT_DI_INDEX_SIZE;
++typedef enum VGT_EVENT_TYPE {
++	Reserved_0x00                                    = 0x0,
++	SAMPLE_STREAMOUTSTATS1                           = 0x1,
++	SAMPLE_STREAMOUTSTATS2                           = 0x2,
++	SAMPLE_STREAMOUTSTATS3                           = 0x3,
++	CACHE_FLUSH_TS                                   = 0x4,
++	CONTEXT_DONE                                     = 0x5,
++	CACHE_FLUSH                                      = 0x6,
++	CS_PARTIAL_FLUSH                                 = 0x7,
++	VGT_STREAMOUT_SYNC                               = 0x8,
++	Reserved_0x09                                    = 0x9,
++	VGT_STREAMOUT_RESET                              = 0xa,
++	END_OF_PIPE_INCR_DE                              = 0xb,
++	END_OF_PIPE_IB_END                               = 0xc,
++	RST_PIX_CNT                                      = 0xd,
++	Reserved_0x0E                                    = 0xe,
++	VS_PARTIAL_FLUSH                                 = 0xf,
++	PS_PARTIAL_FLUSH                                 = 0x10,
++	FLUSH_HS_OUTPUT                                  = 0x11,
++	FLUSH_LS_OUTPUT                                  = 0x12,
++	Reserved_0x13                                    = 0x13,
++	CACHE_FLUSH_AND_INV_TS_EVENT                     = 0x14,
++	ZPASS_DONE                                       = 0x15,
++	CACHE_FLUSH_AND_INV_EVENT                        = 0x16,
++	PERFCOUNTER_START                                = 0x17,
++	PERFCOUNTER_STOP                                 = 0x18,
++	PIPELINESTAT_START                               = 0x19,
++	PIPELINESTAT_STOP                                = 0x1a,
++	PERFCOUNTER_SAMPLE                               = 0x1b,
++	FLUSH_ES_OUTPUT                                  = 0x1c,
++	FLUSH_GS_OUTPUT                                  = 0x1d,
++	SAMPLE_PIPELINESTAT                              = 0x1e,
++	SO_VGTSTREAMOUT_FLUSH                            = 0x1f,
++	SAMPLE_STREAMOUTSTATS                            = 0x20,
++	RESET_VTX_CNT                                    = 0x21,
++	BLOCK_CONTEXT_DONE                               = 0x22,
++	CS_CONTEXT_DONE                                  = 0x23,
++	VGT_FLUSH                                        = 0x24,
++	Reserved_0x25                                    = 0x25,
++	SQ_NON_EVENT                                     = 0x26,
++	SC_SEND_DB_VPZ                                   = 0x27,
++	BOTTOM_OF_PIPE_TS                                = 0x28,
++	FLUSH_SX_TS                                      = 0x29,
++	DB_CACHE_FLUSH_AND_INV                           = 0x2a,
++	FLUSH_AND_INV_DB_DATA_TS                         = 0x2b,
++	FLUSH_AND_INV_DB_META                            = 0x2c,
++	FLUSH_AND_INV_CB_DATA_TS                         = 0x2d,
++	FLUSH_AND_INV_CB_META                            = 0x2e,
++	CS_DONE                                          = 0x2f,
++	PS_DONE                                          = 0x30,
++	FLUSH_AND_INV_CB_PIXEL_DATA                      = 0x31,
++	SX_CB_RAT_ACK_REQUEST                            = 0x32,
++	THREAD_TRACE_START                               = 0x33,
++	THREAD_TRACE_STOP                                = 0x34,
++	THREAD_TRACE_MARKER                              = 0x35,
++	THREAD_TRACE_FLUSH                               = 0x36,
++	THREAD_TRACE_FINISH                              = 0x37,
++	PIXEL_PIPE_STAT_CONTROL                          = 0x38,
++	PIXEL_PIPE_STAT_DUMP                             = 0x39,
++	PIXEL_PIPE_STAT_RESET                            = 0x3a,
++	CONTEXT_SUSPEND                                  = 0x3b,
++} VGT_EVENT_TYPE;
++typedef enum VGT_DMA_SWAP_MODE {
++	VGT_DMA_SWAP_NONE                                = 0x0,
++	VGT_DMA_SWAP_16_BIT                              = 0x1,
++	VGT_DMA_SWAP_32_BIT                              = 0x2,
++	VGT_DMA_SWAP_WORD                                = 0x3,
++} VGT_DMA_SWAP_MODE;
++typedef enum VGT_INDEX_TYPE_MODE {
++	VGT_INDEX_16                                     = 0x0,
++	VGT_INDEX_32                                     = 0x1,
++} VGT_INDEX_TYPE_MODE;
++typedef enum VGT_DMA_BUF_TYPE {
++	VGT_DMA_BUF_MEM                                  = 0x0,
++	VGT_DMA_BUF_RING                                 = 0x1,
++	VGT_DMA_BUF_SETUP                                = 0x2,
++} VGT_DMA_BUF_TYPE;
++typedef enum VGT_OUTPATH_SELECT {
++	VGT_OUTPATH_VTX_REUSE                            = 0x0,
++	VGT_OUTPATH_TESS_EN                              = 0x1,
++	VGT_OUTPATH_PASSTHRU                             = 0x2,
++	VGT_OUTPATH_GS_BLOCK                             = 0x3,
++	VGT_OUTPATH_HS_BLOCK                             = 0x4,
++} VGT_OUTPATH_SELECT;
++typedef enum VGT_GRP_PRIM_TYPE {
++	VGT_GRP_3D_POINT                                 = 0x0,
++	VGT_GRP_3D_LINE                                  = 0x1,
++	VGT_GRP_3D_TRI                                   = 0x2,
++	VGT_GRP_3D_RECT                                  = 0x3,
++	VGT_GRP_3D_QUAD                                  = 0x4,
++	VGT_GRP_2D_COPY_RECT_V0                          = 0x5,
++	VGT_GRP_2D_COPY_RECT_V1                          = 0x6,
++	VGT_GRP_2D_COPY_RECT_V2                          = 0x7,
++	VGT_GRP_2D_COPY_RECT_V3                          = 0x8,
++	VGT_GRP_2D_FILL_RECT                             = 0x9,
++	VGT_GRP_2D_LINE                                  = 0xa,
++	VGT_GRP_2D_TRI                                   = 0xb,
++	VGT_GRP_PRIM_INDEX_LINE                          = 0xc,
++	VGT_GRP_PRIM_INDEX_TRI                           = 0xd,
++	VGT_GRP_PRIM_INDEX_QUAD                          = 0xe,
++	VGT_GRP_3D_LINE_ADJ                              = 0xf,
++	VGT_GRP_3D_TRI_ADJ                               = 0x10,
++	VGT_GRP_3D_PATCH                                 = 0x11,
++} VGT_GRP_PRIM_TYPE;
++typedef enum VGT_GRP_PRIM_ORDER {
++	VGT_GRP_LIST                                     = 0x0,
++	VGT_GRP_STRIP                                    = 0x1,
++	VGT_GRP_FAN                                      = 0x2,
++	VGT_GRP_LOOP                                     = 0x3,
++	VGT_GRP_POLYGON                                  = 0x4,
++} VGT_GRP_PRIM_ORDER;
++typedef enum VGT_GROUP_CONV_SEL {
++	VGT_GRP_INDEX_16                                 = 0x0,
++	VGT_GRP_INDEX_32                                 = 0x1,
++	VGT_GRP_UINT_16                                  = 0x2,
++	VGT_GRP_UINT_32                                  = 0x3,
++	VGT_GRP_SINT_16                                  = 0x4,
++	VGT_GRP_SINT_32                                  = 0x5,
++	VGT_GRP_FLOAT_32                                 = 0x6,
++	VGT_GRP_AUTO_PRIM                                = 0x7,
++	VGT_GRP_FIX_1_23_TO_FLOAT                        = 0x8,
++} VGT_GROUP_CONV_SEL;
++typedef enum VGT_GS_MODE_TYPE {
++	GS_OFF                                           = 0x0,
++	GS_SCENARIO_A                                    = 0x1,
++	GS_SCENARIO_B                                    = 0x2,
++	GS_SCENARIO_G                                    = 0x3,
++	GS_SCENARIO_C                                    = 0x4,
++	SPRITE_EN                                        = 0x5,
++} VGT_GS_MODE_TYPE;
++typedef enum VGT_GS_CUT_MODE {
++	GS_CUT_1024                                      = 0x0,
++	GS_CUT_512                                       = 0x1,
++	GS_CUT_256                                       = 0x2,
++	GS_CUT_128                                       = 0x3,
++} VGT_GS_CUT_MODE;
++typedef enum VGT_GS_OUTPRIM_TYPE {
++	POINTLIST                                        = 0x0,
++	LINESTRIP                                        = 0x1,
++	TRISTRIP                                         = 0x2,
++} VGT_GS_OUTPRIM_TYPE;
++typedef enum VGT_CACHE_INVALID_MODE {
++	VC_ONLY                                          = 0x0,
++	TC_ONLY                                          = 0x1,
++	VC_AND_TC                                        = 0x2,
++} VGT_CACHE_INVALID_MODE;
++typedef enum VGT_TESS_TYPE {
++	TESS_ISOLINE                                     = 0x0,
++	TESS_TRIANGLE                                    = 0x1,
++	TESS_QUAD                                        = 0x2,
++} VGT_TESS_TYPE;
++typedef enum VGT_TESS_PARTITION {
++	PART_INTEGER                                     = 0x0,
++	PART_POW2                                        = 0x1,
++	PART_FRAC_ODD                                    = 0x2,
++	PART_FRAC_EVEN                                   = 0x3,
++} VGT_TESS_PARTITION;
++typedef enum VGT_TESS_TOPOLOGY {
++	OUTPUT_POINT                                     = 0x0,
++	OUTPUT_LINE                                      = 0x1,
++	OUTPUT_TRIANGLE_CW                               = 0x2,
++	OUTPUT_TRIANGLE_CCW                              = 0x3,
++} VGT_TESS_TOPOLOGY;
++typedef enum VGT_RDREQ_POLICY {
++	VGT_POLICY_LRU                                   = 0x0,
++	VGT_POLICY_STREAM                                = 0x1,
++	VGT_POLICY_BYPASS                                = 0x2,
++	VGT_POLICY_RESERVED                              = 0x3,
++} VGT_RDREQ_POLICY;
++typedef enum VGT_STAGES_LS_EN {
++	LS_STAGE_OFF                                     = 0x0,
++	LS_STAGE_ON                                      = 0x1,
++	CS_STAGE_ON                                      = 0x2,
++	RESERVED_LS                                      = 0x3,
++} VGT_STAGES_LS_EN;
++typedef enum VGT_STAGES_HS_EN {
++	HS_STAGE_OFF                                     = 0x0,
++	HS_STAGE_ON                                      = 0x1,
++} VGT_STAGES_HS_EN;
++typedef enum VGT_STAGES_ES_EN {
++	ES_STAGE_OFF                                     = 0x0,
++	ES_STAGE_DS                                      = 0x1,
++	ES_STAGE_REAL                                    = 0x2,
++	RESERVED_ES                                      = 0x3,
++} VGT_STAGES_ES_EN;
++typedef enum VGT_STAGES_GS_EN {
++	GS_STAGE_OFF                                     = 0x0,
++	GS_STAGE_ON                                      = 0x1,
++} VGT_STAGES_GS_EN;
++typedef enum VGT_STAGES_VS_EN {
++	VS_STAGE_REAL                                    = 0x0,
++	VS_STAGE_DS                                      = 0x1,
++	VS_STAGE_COPY_SHADER                             = 0x2,
++	RESERVED_VS                                      = 0x3,
++} VGT_STAGES_VS_EN;
++typedef enum VGT_PERFCOUNT_SELECT {
++	vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE    = 0x0,
++	vgt_perf_VGT_SPI_ESVERT_VALID                    = 0x1,
++	vgt_perf_VGT_SPI_ESVERT_EOV                      = 0x2,
++	vgt_perf_VGT_SPI_ESVERT_STALLED                  = 0x3,
++	vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY             = 0x4,
++	vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE             = 0x5,
++	vgt_perf_VGT_SPI_ESVERT_STATIC                   = 0x6,
++	vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT               = 0x7,
++	vgt_perf_VGT_SPI_ESTHREAD_SEND                   = 0x8,
++	vgt_perf_VGT_SPI_GSPRIM_VALID                    = 0x9,
++	vgt_perf_VGT_SPI_GSPRIM_EOV                      = 0xa,
++	vgt_perf_VGT_SPI_GSPRIM_CONT                     = 0xb,
++	vgt_perf_VGT_SPI_GSPRIM_STALLED                  = 0xc,
++	vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY             = 0xd,
++	vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE             = 0xe,
++	vgt_perf_VGT_SPI_GSPRIM_STATIC                   = 0xf,
++	vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE    = 0x10,
++	vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT               = 0x11,
++	vgt_perf_VGT_SPI_GSTHREAD_SEND                   = 0x12,
++	vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE    = 0x13,
++	vgt_perf_VGT_SPI_VSVERT_SEND                     = 0x14,
++	vgt_perf_VGT_SPI_VSVERT_EOV                      = 0x15,
++	vgt_perf_VGT_SPI_VSVERT_STALLED                  = 0x16,
++	vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY             = 0x17,
++	vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE             = 0x18,
++	vgt_perf_VGT_SPI_VSVERT_STATIC                   = 0x19,
++	vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT               = 0x1a,
++	vgt_perf_VGT_SPI_VSTHREAD_SEND                   = 0x1b,
++	vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE              = 0x1c,
++	vgt_perf_VGT_PA_CLIPV_SEND                       = 0x1d,
++	vgt_perf_VGT_PA_CLIPV_FIRSTVERT                  = 0x1e,
++	vgt_perf_VGT_PA_CLIPV_STALLED                    = 0x1f,
++	vgt_perf_VGT_PA_CLIPV_STARVED_BUSY               = 0x20,
++	vgt_perf_VGT_PA_CLIPV_STARVED_IDLE               = 0x21,
++	vgt_perf_VGT_PA_CLIPV_STATIC                     = 0x22,
++	vgt_perf_VGT_PA_CLIPP_SEND                       = 0x23,
++	vgt_perf_VGT_PA_CLIPP_EOP                        = 0x24,
++	vgt_perf_VGT_PA_CLIPP_IS_EVENT                   = 0x25,
++	vgt_perf_VGT_PA_CLIPP_NULL_PRIM                  = 0x26,
++	vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT               = 0x27,
++	vgt_perf_VGT_PA_CLIPP_STALLED                    = 0x28,
++	vgt_perf_VGT_PA_CLIPP_STARVED_BUSY               = 0x29,
++	vgt_perf_VGT_PA_CLIPP_STARVED_IDLE               = 0x2a,
++	vgt_perf_VGT_PA_CLIPP_STATIC                     = 0x2b,
++	vgt_perf_VGT_PA_CLIPS_SEND                       = 0x2c,
++	vgt_perf_VGT_PA_CLIPS_STALLED                    = 0x2d,
++	vgt_perf_VGT_PA_CLIPS_STARVED_BUSY               = 0x2e,
++	vgt_perf_VGT_PA_CLIPS_STARVED_IDLE               = 0x2f,
++	vgt_perf_VGT_PA_CLIPS_STATIC                     = 0x30,
++	vgt_perf_vsvert_ds_send                          = 0x31,
++	vgt_perf_vsvert_api_send                         = 0x32,
++	vgt_perf_hs_tif_stall                            = 0x33,
++	vgt_perf_hs_input_stall                          = 0x34,
++	vgt_perf_hs_interface_stall                      = 0x35,
++	vgt_perf_hs_tfm_stall                            = 0x36,
++	vgt_perf_te11_starved                            = 0x37,
++	vgt_perf_gs_event_stall                          = 0x38,
++	vgt_perf_vgt_pa_clipp_send_not_event             = 0x39,
++	vgt_perf_vgt_pa_clipp_valid_prim                 = 0x3a,
++	vgt_perf_reused_es_indices                       = 0x3b,
++	vgt_perf_vs_cache_hits                           = 0x3c,
++	vgt_perf_gs_cache_hits                           = 0x3d,
++	vgt_perf_ds_cache_hits                           = 0x3e,
++	vgt_perf_total_cache_hits                        = 0x3f,
++	vgt_perf_vgt_busy                                = 0x40,
++	vgt_perf_vgt_gs_busy                             = 0x41,
++	vgt_perf_esvert_stalled_es_tbl                   = 0x42,
++	vgt_perf_esvert_stalled_gs_tbl                   = 0x43,
++	vgt_perf_esvert_stalled_gs_event                 = 0x44,
++	vgt_perf_esvert_stalled_gsprim                   = 0x45,
++	vgt_perf_gsprim_stalled_es_tbl                   = 0x46,
++	vgt_perf_gsprim_stalled_gs_tbl                   = 0x47,
++	vgt_perf_gsprim_stalled_gs_event                 = 0x48,
++	vgt_perf_gsprim_stalled_esvert                   = 0x49,
++	vgt_perf_esthread_stalled_es_rb_full             = 0x4a,
++	vgt_perf_esthread_stalled_spi_bp                 = 0x4b,
++	vgt_perf_counters_avail_stalled                  = 0x4c,
++	vgt_perf_gs_rb_space_avail_stalled               = 0x4d,
++	vgt_perf_gs_issue_rtr_stalled                    = 0x4e,
++	vgt_perf_gsthread_stalled                        = 0x4f,
++	vgt_perf_strmout_stalled                         = 0x50,
++	vgt_perf_wait_for_es_done_stalled                = 0x51,
++	vgt_perf_cm_stalled_by_gog                       = 0x52,
++	vgt_perf_cm_reading_stalled                      = 0x53,
++	vgt_perf_cm_stalled_by_gsfetch_done              = 0x54,
++	vgt_perf_gog_vs_tbl_stalled                      = 0x55,
++	vgt_perf_gog_out_indx_stalled                    = 0x56,
++	vgt_perf_gog_out_prim_stalled                    = 0x57,
++	vgt_perf_waveid_stalled                          = 0x58,
++	vgt_perf_gog_busy                                = 0x59,
++	vgt_perf_reused_vs_indices                       = 0x5a,
++	vgt_perf_sclk_reg_vld_event                      = 0x5b,
++	vgt_perf_RESERVED0                               = 0x5c,
++	vgt_perf_sclk_core_vld_event                     = 0x5d,
++	vgt_perf_RESERVED1                               = 0x5e,
++	vgt_perf_sclk_gs_vld_event                       = 0x5f,
++	vgt_perf_VGT_SPI_LSVERT_VALID                    = 0x60,
++	vgt_perf_VGT_SPI_LSVERT_EOV                      = 0x61,
++	vgt_perf_VGT_SPI_LSVERT_STALLED                  = 0x62,
++	vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY             = 0x63,
++	vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE             = 0x64,
++	vgt_perf_VGT_SPI_LSVERT_STATIC                   = 0x65,
++	vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE      = 0x66,
++	vgt_perf_VGT_SPI_LSWAVE_IS_EVENT                 = 0x67,
++	vgt_perf_VGT_SPI_LSWAVE_SEND                     = 0x68,
++	vgt_perf_VGT_SPI_HSVERT_VALID                    = 0x69,
++	vgt_perf_VGT_SPI_HSVERT_EOV                      = 0x6a,
++	vgt_perf_VGT_SPI_HSVERT_STALLED                  = 0x6b,
++	vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY             = 0x6c,
++	vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE             = 0x6d,
++	vgt_perf_VGT_SPI_HSVERT_STATIC                   = 0x6e,
++	vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE      = 0x6f,
++	vgt_perf_VGT_SPI_HSWAVE_IS_EVENT                 = 0x70,
++	vgt_perf_VGT_SPI_HSWAVE_SEND                     = 0x71,
++	vgt_perf_ds_prims                                = 0x72,
++	vgt_perf_null_tess_patches                       = 0x73,
++	vgt_perf_ls_thread_groups                        = 0x74,
++	vgt_perf_hs_thread_groups                        = 0x75,
++	vgt_perf_es_thread_groups                        = 0x76,
++	vgt_perf_vs_thread_groups                        = 0x77,
++	vgt_perf_ls_done_latency                         = 0x78,
++	vgt_perf_hs_done_latency                         = 0x79,
++	vgt_perf_es_done_latency                         = 0x7a,
++	vgt_perf_gs_done_latency                         = 0x7b,
++	vgt_perf_vgt_hs_busy                             = 0x7c,
++	vgt_perf_vgt_te11_busy                           = 0x7d,
++	vgt_perf_ls_flush                                = 0x7e,
++	vgt_perf_hs_flush                                = 0x7f,
++	vgt_perf_es_flush                                = 0x80,
++	vgt_perf_gs_flush                                = 0x81,
++	vgt_perf_ls_done                                 = 0x82,
++	vgt_perf_hs_done                                 = 0x83,
++	vgt_perf_es_done                                 = 0x84,
++	vgt_perf_gs_done                                 = 0x85,
++	vgt_perf_vsfetch_done                            = 0x86,
++	vgt_perf_RESERVED2                               = 0x87,
++	vgt_perf_es_ring_high_water_mark                 = 0x88,
++	vgt_perf_gs_ring_high_water_mark                 = 0x89,
++	vgt_perf_vs_table_high_water_mark                = 0x8a,
++	vgt_perf_hs_tgs_active_high_water_mark           = 0x8b,
++} VGT_PERFCOUNT_SELECT;
++typedef enum IA_PERFCOUNT_SELECT {
++	ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE            = 0x0,
++	ia_perf_MC_LAT_BIN_0                             = 0x1,
++	ia_perf_MC_LAT_BIN_1                             = 0x2,
++	ia_perf_MC_LAT_BIN_2                             = 0x3,
++	ia_perf_MC_LAT_BIN_3                             = 0x4,
++	ia_perf_MC_LAT_BIN_4                             = 0x5,
++	ia_perf_MC_LAT_BIN_5                             = 0x6,
++	ia_perf_MC_LAT_BIN_6                             = 0x7,
++	ia_perf_MC_LAT_BIN_7                             = 0x8,
++	ia_perf_ia_busy                                  = 0x9,
++	ia_perf_ia_sclk_reg_vld_event                    = 0xa,
++	ia_perf_RESERVED0                                = 0xb,
++	ia_perf_ia_sclk_core_vld_event                   = 0xc,
++	ia_perf_RESERVED1                                = 0xd,
++	ia_perf_ia_dma_return                            = 0xe,
++	ia_perf_shift_starved_pipe1_event                = 0xf,
++	ia_perf_shift_starved_pipe0_event                = 0x10,
++	ia_perf_ia_stalled                               = 0x11,
++} IA_PERFCOUNT_SELECT;
++typedef enum WD_PERFCOUNT_SELECT {
++	wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE           = 0x0,
++	wd_perf_RBIU_DR_FIFO_STARVED                     = 0x1,
++	wd_perf_RBIU_DR_FIFO_STALLED                     = 0x2,
++	wd_perf_RBIU_DI_FIFO_STARVED                     = 0x3,
++	wd_perf_RBIU_DI_FIFO_STALLED                     = 0x4,
++	wd_perf_wd_busy                                  = 0x5,
++	wd_perf_wd_sclk_reg_vld_event                    = 0x6,
++	wd_perf_wd_sclk_input_vld_event                  = 0x7,
++	wd_perf_wd_sclk_core_vld_event                   = 0x8,
++	wd_perf_wd_stalled                               = 0x9,
++} WD_PERFCOUNT_SELECT;
++typedef enum WD_IA_DRAW_TYPE {
++	WD_IA_DRAW_TYPE_DI_MM0                           = 0x0,
++	WD_IA_DRAW_TYPE_DI_MM1                           = 0x1,
++	WD_IA_DRAW_TYPE_EVENT_INIT                       = 0x2,
++	WD_IA_DRAW_TYPE_EVENT_ADDR                       = 0x3,
++	WD_IA_DRAW_TYPE_MIN_INDX                         = 0x4,
++	WD_IA_DRAW_TYPE_MAX_INDX                         = 0x5,
++	WD_IA_DRAW_TYPE_INDX_OFF                         = 0x6,
++	WD_IA_DRAW_TYPE_IMM_DATA                         = 0x7,
++} WD_IA_DRAW_TYPE;
++#define GSTHREADID_SIZE                           0x2
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++	ADDR_CONFIG_16_PIPE                              = 0x4,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_dco0                            = 0x2,
++	DBG_CLIENT_BLKID_wd                              = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_scf2                            = 0x5,
++	DBG_CLIENT_BLKID_spim3                           = 0x6,
++	DBG_CLIENT_BLKID_cb3                             = 0x7,
++	DBG_CLIENT_BLKID_sx0                             = 0x8,
++	DBG_CLIENT_BLKID_cb2                             = 0x9,
++	DBG_CLIENT_BLKID_bci1                            = 0xa,
++	DBG_CLIENT_BLKID_xdma                            = 0xb,
++	DBG_CLIENT_BLKID_bci0                            = 0xc,
++	DBG_CLIENT_BLKID_spim0                           = 0xd,
++	DBG_CLIENT_BLKID_mcd0                            = 0xe,
++	DBG_CLIENT_BLKID_mcc0                            = 0xf,
++	DBG_CLIENT_BLKID_cb0                             = 0x10,
++	DBG_CLIENT_BLKID_cb1                             = 0x11,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x12,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x13,
++	DBG_CLIENT_BLKID_cpf                             = 0x14,
++	DBG_CLIENT_BLKID_rlc                             = 0x15,
++	DBG_CLIENT_BLKID_grbm                            = 0x16,
++	DBG_CLIENT_BLKID_bif                             = 0x17,
++	DBG_CLIENT_BLKID_scf1                            = 0x18,
++	DBG_CLIENT_BLKID_sam                             = 0x19,
++	DBG_CLIENT_BLKID_mcd4                            = 0x1a,
++	DBG_CLIENT_BLKID_mcc4                            = 0x1b,
++	DBG_CLIENT_BLKID_gmcon                           = 0x1c,
++	DBG_CLIENT_BLKID_mcb                             = 0x1d,
++	DBG_CLIENT_BLKID_vgt0                            = 0x1e,
++	DBG_CLIENT_BLKID_pc0                             = 0x1f,
++	DBG_CLIENT_BLKID_spim1                           = 0x20,
++	DBG_CLIENT_BLKID_bci2                            = 0x21,
++	DBG_CLIENT_BLKID_mcd6                            = 0x22,
++	DBG_CLIENT_BLKID_mcc6                            = 0x23,
++	DBG_CLIENT_BLKID_mcd3                            = 0x24,
++	DBG_CLIENT_BLKID_mcc3                            = 0x25,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x26,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x27,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x28,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x29,
++	DBG_CLIENT_BLKID_spim2                           = 0x2a,
++	DBG_CLIENT_BLKID_ds                              = 0x2b,
++	DBG_CLIENT_BLKID_srbm                            = 0x2c,
++	DBG_CLIENT_BLKID_ih                              = 0x2d,
++	DBG_CLIENT_BLKID_sem                             = 0x2e,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x2f,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x30,
++	DBG_CLIENT_BLKID_hdp                             = 0x31,
++	DBG_CLIENT_BLKID_acp_0                           = 0x32,
++	DBG_CLIENT_BLKID_acp_1                           = 0x33,
++	DBG_CLIENT_BLKID_vceb_0                          = 0x34,
++	DBG_CLIENT_BLKID_vceb_1                          = 0x35,
++	DBG_CLIENT_BLKID_vceb_2                          = 0x36,
++	DBG_CLIENT_BLKID_mcd2                            = 0x37,
++	DBG_CLIENT_BLKID_mcc2                            = 0x38,
++	DBG_CLIENT_BLKID_scf3                            = 0x39,
++	DBG_CLIENT_BLKID_bci3                            = 0x3a,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3b,
++	DBG_CLIENT_BLKID_mcc5                            = 0x3c,
++	DBG_CLIENT_BLKID_vgt2                            = 0x3d,
++	DBG_CLIENT_BLKID_pc2                             = 0x3e,
++	DBG_CLIENT_BLKID_smu_0                           = 0x3f,
++	DBG_CLIENT_BLKID_smu_1                           = 0x40,
++	DBG_CLIENT_BLKID_smu_2                           = 0x41,
++	DBG_CLIENT_BLKID_vcea_0                          = 0x42,
++	DBG_CLIENT_BLKID_vcea_1                          = 0x43,
++	DBG_CLIENT_BLKID_vcea_2                          = 0x44,
++	DBG_CLIENT_BLKID_vcea_3                          = 0x45,
++	DBG_CLIENT_BLKID_vcea_4                          = 0x46,
++	DBG_CLIENT_BLKID_vcea_5                          = 0x47,
++	DBG_CLIENT_BLKID_vcea_6                          = 0x48,
++	DBG_CLIENT_BLKID_scf0                            = 0x49,
++	DBG_CLIENT_BLKID_vgt1                            = 0x4a,
++	DBG_CLIENT_BLKID_pc1                             = 0x4b,
++	DBG_CLIENT_BLKID_gdc_0                           = 0x4c,
++	DBG_CLIENT_BLKID_gdc_1                           = 0x4d,
++	DBG_CLIENT_BLKID_gdc_2                           = 0x4e,
++	DBG_CLIENT_BLKID_gdc_3                           = 0x4f,
++	DBG_CLIENT_BLKID_gdc_4                           = 0x50,
++	DBG_CLIENT_BLKID_gdc_5                           = 0x51,
++	DBG_CLIENT_BLKID_gdc_6                           = 0x52,
++	DBG_CLIENT_BLKID_gdc_7                           = 0x53,
++	DBG_CLIENT_BLKID_gdc_8                           = 0x54,
++	DBG_CLIENT_BLKID_gdc_9                           = 0x55,
++	DBG_CLIENT_BLKID_gdc_10                          = 0x56,
++	DBG_CLIENT_BLKID_gdc_11                          = 0x57,
++	DBG_CLIENT_BLKID_gdc_12                          = 0x58,
++	DBG_CLIENT_BLKID_gdc_13                          = 0x59,
++	DBG_CLIENT_BLKID_gdc_14                          = 0x5a,
++	DBG_CLIENT_BLKID_gdc_15                          = 0x5b,
++	DBG_CLIENT_BLKID_gdc_16                          = 0x5c,
++	DBG_CLIENT_BLKID_gdc_17                          = 0x5d,
++	DBG_CLIENT_BLKID_gdc_18                          = 0x5e,
++	DBG_CLIENT_BLKID_gdc_19                          = 0x5f,
++	DBG_CLIENT_BLKID_gdc_20                          = 0x60,
++	DBG_CLIENT_BLKID_gdc_21                          = 0x61,
++	DBG_CLIENT_BLKID_gdc_22                          = 0x62,
++	DBG_CLIENT_BLKID_vgt3                            = 0x63,
++	DBG_CLIENT_BLKID_pc3                             = 0x64,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x65,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x66,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x67,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x68,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x69,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x6a,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x6b,
++	DBG_CLIENT_BLKID_mcd7                            = 0x6c,
++	DBG_CLIENT_BLKID_mcc7                            = 0x6d,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x6e,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x6f,
++	DBG_CLIENT_BLKID_gck                             = 0x70,
++	DBG_CLIENT_BLKID_mcd1                            = 0x71,
++	DBG_CLIENT_BLKID_mcc1                            = 0x72,
++	DBG_CLIENT_BLKID_cb101                           = 0x73,
++	DBG_CLIENT_BLKID_cb103                           = 0x74,
++	DBG_CLIENT_BLKID_sx10                            = 0x75,
++	DBG_CLIENT_BLKID_cb102                           = 0x76,
++	DBG_CLIENT_BLKID_cb002                           = 0x77,
++	DBG_CLIENT_BLKID_cb100                           = 0x78,
++	DBG_CLIENT_BLKID_cb000                           = 0x79,
++	DBG_CLIENT_BLKID_pa00                            = 0x7a,
++	DBG_CLIENT_BLKID_pa10                            = 0x7b,
++	DBG_CLIENT_BLKID_ia0                             = 0x7c,
++	DBG_CLIENT_BLKID_ia1                             = 0x7d,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x7e,
++	DBG_CLIENT_BLKID_cb001                           = 0x7f,
++	DBG_CLIENT_BLKID_cb003                           = 0x80,
++	DBG_CLIENT_BLKID_sx00                            = 0x81,
++	DBG_CLIENT_BLKID_sx20                            = 0x82,
++	DBG_CLIENT_BLKID_cb203                           = 0x83,
++	DBG_CLIENT_BLKID_cb201                           = 0x84,
++	DBG_CLIENT_BLKID_cb302                           = 0x85,
++	DBG_CLIENT_BLKID_cb202                           = 0x86,
++	DBG_CLIENT_BLKID_cb300                           = 0x87,
++	DBG_CLIENT_BLKID_cb200                           = 0x88,
++	DBG_CLIENT_BLKID_pa01                            = 0x89,
++	DBG_CLIENT_BLKID_pa11                            = 0x8a,
++	DBG_CLIENT_BLKID_sx30                            = 0x8b,
++	DBG_CLIENT_BLKID_cb303                           = 0x8c,
++	DBG_CLIENT_BLKID_cb301                           = 0x8d,
++	DBG_CLIENT_BLKID_dco                             = 0x8e,
++	DBG_CLIENT_BLKID_scb0                            = 0x8f,
++	DBG_CLIENT_BLKID_scb1                            = 0x90,
++	DBG_CLIENT_BLKID_scb2                            = 0x91,
++	DBG_CLIENT_BLKID_scb3                            = 0x92,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x93,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x94,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_SNORM_OGL                         = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_SNORM_OGL                         = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_UBNORM                            = 0xa,
++	IMG_NUM_FORMAT_UBNORM_OGL                        = 0xb,
++	IMG_NUM_FORMAT_UBINT                             = 0xc,
++	IMG_NUM_FORMAT_UBSCALED                          = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++	TCC_CACHE_POLICY_BYPASS                          = 0x2,
++} TCC_CACHE_POLICIES;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++
++#endif /* GFX_7_2_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h
+new file mode 100644
+index 0000000..4509c82
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h
+@@ -0,0 +1,18444 @@
++/*
++ * GFX_7_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_7_2_SH_MASK_H
++#define GFX_7_2_SH_MASK_H
++
++#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
++#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
++#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
++#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
++#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
++#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
++#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
++#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
++#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
++#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
++#define CB_COLOR_CONTROL__MODE_MASK 0x70
++#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
++#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
++#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
++#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
++#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
++#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
++#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
++#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
++#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
++#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
++#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
++#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
++#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
++#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
++#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
++#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
++#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
++#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
++#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
++#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
++#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
++#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
++#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
++#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
++#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
++#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
++#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
++#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
++#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
++#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
++#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
++#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
++#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
++#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
++#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
++#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
++#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
++#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
++#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
++#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
++#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
++#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
++#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
++#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
++#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
++#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
++#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
++#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
++#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
++#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
++#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
++#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
++#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
++#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
++#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
++#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
++#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
++#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
++#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
++#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
++#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
++#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
++#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
++#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
++#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
++#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
++#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
++#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
++#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
++#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
++#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
++#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
++#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
++#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
++#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
++#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
++#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
++#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000
++#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18
++#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
++#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1
++#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0
++#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2
++#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1
++#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4
++#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2
++#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20
++#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5
++#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40
++#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6
++#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80
++#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7
++#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100
++#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8
++#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200
++#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9
++#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400
++#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa
++#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800
++#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb
++#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1
++#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0
++#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2
++#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1
++#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4
++#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2
++#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20
++#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5
++#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40
++#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6
++#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80
++#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7
++#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100
++#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8
++#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3
++#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0
++#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4
++#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2
++#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20
++#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5
++#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40
++#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6
++#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80
++#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7
++#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100
++#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8
++#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f
++#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0
++#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0
++#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6
++#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00
++#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa
++#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000
++#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10
++#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
++#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
++#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
++#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
++#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
++#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
++#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1
++#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0
++#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2
++#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1
++#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4
++#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2
++#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20
++#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5
++#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40
++#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6
++#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80
++#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7
++#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff
++#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0
++#define CP_DFY_CNTL__POLICY_MASK 0x300
++#define CP_DFY_CNTL__POLICY__SHIFT 0x8
++#define CP_DFY_CNTL__VOL_MASK 0x400
++#define CP_DFY_CNTL__VOL__SHIFT 0xa
++#define CP_DFY_CNTL__ATC_MASK 0x800
++#define CP_DFY_CNTL__ATC__SHIFT 0xb
++#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
++#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
++#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000
++#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
++#define CP_DFY_STAT__BUSY_MASK 0x80000000
++#define CP_DFY_STAT__BUSY__SHIFT 0x1f
++#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
++#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
++#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
++#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_0__DATA__SHIFT 0x0
++#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_1__DATA__SHIFT 0x0
++#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_2__DATA__SHIFT 0x0
++#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_3__DATA__SHIFT 0x0
++#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_4__DATA__SHIFT 0x0
++#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_5__DATA__SHIFT 0x0
++#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_6__DATA__SHIFT 0x0
++#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_7__DATA__SHIFT 0x0
++#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_8__DATA__SHIFT 0x0
++#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_9__DATA__SHIFT 0x0
++#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_10__DATA__SHIFT 0x0
++#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_11__DATA__SHIFT 0x0
++#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_12__DATA__SHIFT 0x0
++#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_13__DATA__SHIFT 0x0
++#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_14__DATA__SHIFT 0x0
++#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_15__DATA__SHIFT 0x0
++#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
++#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
++#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000
++#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10
++#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000
++#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000
++#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a
++#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000
++#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10
++#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000
++#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000
++#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a
++#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000
++#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000
++#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a
++#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000
++#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000
++#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a
++#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
++#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
++#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc
++#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2
++#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff
++#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0
++#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
++#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
++#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
++#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
++#define CP_RB_VMID__RB0_VMID_MASK 0xf
++#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
++#define CP_RB_VMID__RB1_VMID_MASK 0xf00
++#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
++#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
++#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
++#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
++#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
++#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
++#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
++#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff
++#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
++#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff
++#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
++#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
++#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
++#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
++#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
++#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
++#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
++#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
++#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
++#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1
++#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
++#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
++#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
++#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc
++#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
++#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
++#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
++#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
++#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0
++#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4
++#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00
++#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa
++#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
++#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
++#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3
++#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0
++#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4
++#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00
++#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa
++#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000
++#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10
++#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3
++#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0
++#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4
++#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00
++#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa
++#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000
++#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10
++#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3
++#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0
++#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4
++#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00
++#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa
++#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000
++#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10
++#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1
++#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0
++#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
++#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
++#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
++#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
++#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
++#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
++#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
++#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
++#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
++#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
++#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
++#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
++#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
++#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
++#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
++#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
++#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
++#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
++#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
++#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
++#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
++#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
++#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
++#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
++#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
++#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
++#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
++#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
++#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
++#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
++#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
++#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
++#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
++#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
++#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
++#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
++#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
++#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
++#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
++#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
++#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
++#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
++#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
++#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
++#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
++#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
++#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
++#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
++#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff
++#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff
++#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff
++#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff
++#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
++#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff
++#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff
++#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff
++#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff
++#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
++#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
++#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
++#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
++#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
++#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
++#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
++#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
++#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
++#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
++#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
++#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
++#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
++#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
++#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
++#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
++#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
++#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
++#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
++#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
++#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
++#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
++#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
++#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
++#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
++#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000
++#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10
++#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff
++#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
++#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
++#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
++#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
++#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
++#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
++#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
++#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
++#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
++#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
++#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
++#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
++#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
++#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
++#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
++#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
++#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
++#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
++#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
++#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
++#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
++#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100
++#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8
++#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200
++#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9
++#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
++#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
++#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
++#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
++#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
++#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
++#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
++#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
++#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
++#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
++#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
++#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
++#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
++#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
++#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
++#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
++#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
++#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
++#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
++#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
++#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
++#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
++#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
++#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
++#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
++#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
++#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
++#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
++#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
++#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
++#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
++#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
++#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
++#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
++#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
++#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
++#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
++#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
++#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
++#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
++#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
++#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
++#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
++#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
++#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
++#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
++#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
++#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
++#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
++#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
++#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
++#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
++#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
++#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
++#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
++#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
++#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
++#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
++#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
++#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
++#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
++#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
++#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
++#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
++#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1
++#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0
++#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2
++#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1
++#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
++#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
++#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
++#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
++#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
++#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
++#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
++#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
++#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
++#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
++#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
++#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
++#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
++#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
++#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4
++#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2
++#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8
++#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3
++#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
++#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
++#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
++#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
++#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
++#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
++#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
++#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
++#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
++#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
++#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
++#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
++#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
++#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
++#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
++#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
++#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
++#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
++#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
++#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
++#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
++#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
++#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
++#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
++#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
++#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
++#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
++#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
++#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
++#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
++#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
++#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
++#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
++#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
++#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
++#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
++#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
++#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
++#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
++#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
++#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
++#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
++#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
++#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
++#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
++#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
++#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
++#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
++#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
++#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
++#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
++#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
++#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
++#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
++#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
++#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
++#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
++#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
++#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
++#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
++#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
++#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
++#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
++#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
++#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
++#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
++#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
++#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
++#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
++#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
++#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
++#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
++#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
++#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
++#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
++#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
++#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
++#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
++#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
++#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10
++#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
++#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f
++#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0
++#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
++#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
++#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
++#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
++#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
++#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
++#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
++#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
++#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
++#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
++#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
++#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
++#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
++#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
++#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
++#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
++#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
++#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
++#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
++#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
++#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
++#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
++#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
++#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
++#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
++#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
++#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
++#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
++#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
++#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
++#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
++#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
++#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
++#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
++#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
++#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
++#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
++#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
++#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
++#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
++#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
++#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
++#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
++#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
++#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
++#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
++#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
++#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
++#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
++#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
++#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000
++#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14
++#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
++#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
++#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
++#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
++#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
++#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
++#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
++#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
++#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
++#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
++#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
++#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
++#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000
++#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
++#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000
++#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b
++#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
++#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
++#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
++#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
++#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
++#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
++#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
++#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
++#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3
++#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0
++#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
++#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
++#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
++#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
++#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
++#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
++#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
++#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
++#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
++#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3
++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0
++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
++#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
++#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3
++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0
++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
++#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
++#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
++#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
++#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
++#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
++#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
++#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
++#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
++#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
++#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
++#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
++#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
++#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
++#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
++#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
++#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
++#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
++#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
++#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
++#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
++#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
++#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
++#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
++#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
++#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
++#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
++#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
++#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
++#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
++#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
++#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
++#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
++#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
++#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
++#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
++#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
++#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
++#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
++#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
++#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
++#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
++#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
++#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
++#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
++#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
++#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
++#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
++#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
++#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
++#define CP_APPEND_DATA__DATA_MASK 0xffffffff
++#define CP_APPEND_DATA__DATA__SHIFT 0x0
++#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
++#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
++#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
++#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
++#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
++#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
++#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
++#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
++#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
++#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
++#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
++#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
++#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
++#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
++#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
++#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
++#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
++#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
++#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
++#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
++#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
++#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
++#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
++#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
++#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
++#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
++#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
++#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
++#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
++#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
++#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
++#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
++#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
++#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
++#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
++#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
++#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
++#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
++#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
++#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
++#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
++#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
++#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
++#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
++#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
++#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
++#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
++#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
++#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
++#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
++#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
++#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
++#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
++#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
++#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
++#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
++#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
++#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
++#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
++#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
++#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
++#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
++#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
++#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
++#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
++#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
++#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
++#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
++#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
++#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
++#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
++#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000
++#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10
++#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
++#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
++#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
++#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
++#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
++#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
++#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
++#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
++#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
++#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
++#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
++#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
++#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
++#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
++#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
++#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
++#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
++#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
++#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
++#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
++#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
++#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
++#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
++#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
++#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
++#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
++#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
++#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
++#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
++#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
++#define CP_COHER_STATUS__MEID_MASK 0x3000000
++#define CP_COHER_STATUS__MEID__SHIFT 0x18
++#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
++#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
++#define CP_COHER_STATUS__STATUS_MASK 0x80000000
++#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
++#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
++#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
++#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
++#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
++#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
++#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
++#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
++#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
++#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
++#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
++#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
++#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
++#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
++#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000
++#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf
++#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
++#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
++#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
++#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
++#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
++#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
++#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000
++#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b
++#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
++#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
++#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
++#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
++#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
++#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
++#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
++#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
++#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
++#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
++#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
++#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
++#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
++#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
++#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
++#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
++#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
++#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
++#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
++#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
++#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
++#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
++#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
++#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
++#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
++#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
++#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
++#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
++#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
++#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
++#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
++#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
++#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000
++#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf
++#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
++#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
++#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
++#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
++#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
++#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
++#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000
++#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b
++#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
++#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
++#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
++#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
++#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
++#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
++#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
++#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
++#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
++#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
++#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
++#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
++#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
++#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
++#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
++#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
++#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
++#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
++#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
++#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
++#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
++#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
++#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
++#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
++#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
++#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
++#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
++#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
++#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
++#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
++#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
++#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
++#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
++#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
++#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
++#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
++#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
++#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
++#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
++#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
++#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000
++#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf
++#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
++#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
++#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
++#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
++#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
++#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
++#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
++#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
++#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
++#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
++#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
++#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
++#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
++#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
++#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
++#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
++#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
++#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
++#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
++#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
++#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
++#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
++#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
++#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
++#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
++#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
++#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
++#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
++#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
++#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
++#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
++#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
++#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
++#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
++#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
++#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
++#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
++#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
++#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000
++#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe
++#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
++#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
++#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000
++#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10
++#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000
++#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
++#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
++#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
++#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
++#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
++#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
++#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
++#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
++#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
++#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
++#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
++#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
++#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
++#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40
++#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6
++#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80
++#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7
++#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
++#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
++#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
++#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
++#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
++#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
++#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
++#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
++#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
++#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
++#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
++#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
++#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
++#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
++#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
++#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
++#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
++#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
++#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
++#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
++#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
++#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
++#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
++#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
++#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
++#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
++#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
++#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
++#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
++#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
++#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
++#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
++#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
++#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
++#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
++#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
++#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
++#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
++#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
++#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
++#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
++#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
++#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
++#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
++#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100
++#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8
++#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
++#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
++#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
++#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
++#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
++#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
++#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
++#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
++#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
++#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
++#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
++#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
++#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
++#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
++#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
++#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
++#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
++#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
++#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
++#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
++#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
++#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
++#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
++#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
++#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
++#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
++#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
++#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
++#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
++#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
++#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
++#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
++#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
++#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
++#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
++#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
++#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80
++#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7
++#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100
++#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8
++#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
++#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
++#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
++#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
++#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
++#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
++#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
++#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
++#define CP_STAT__DC_BUSY_MASK 0x2000
++#define CP_STAT__DC_BUSY__SHIFT 0xd
++#define CP_STAT__PFP_BUSY_MASK 0x8000
++#define CP_STAT__PFP_BUSY__SHIFT 0xf
++#define CP_STAT__MEQ_BUSY_MASK 0x10000
++#define CP_STAT__MEQ_BUSY__SHIFT 0x10
++#define CP_STAT__ME_BUSY_MASK 0x20000
++#define CP_STAT__ME_BUSY__SHIFT 0x11
++#define CP_STAT__QUERY_BUSY_MASK 0x40000
++#define CP_STAT__QUERY_BUSY__SHIFT 0x12
++#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
++#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
++#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
++#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
++#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
++#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
++#define CP_STAT__DMA_BUSY_MASK 0x400000
++#define CP_STAT__DMA_BUSY__SHIFT 0x16
++#define CP_STAT__RCIU_BUSY_MASK 0x800000
++#define CP_STAT__RCIU_BUSY__SHIFT 0x17
++#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
++#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
++#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
++#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
++#define CP_STAT__CE_BUSY_MASK 0x4000000
++#define CP_STAT__CE_BUSY__SHIFT 0x1a
++#define CP_STAT__TCIU_BUSY_MASK 0x8000000
++#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
++#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
++#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
++#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
++#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
++#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
++#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
++#define CP_STAT__CP_BUSY_MASK 0x80000000
++#define CP_STAT__CP_BUSY__SHIFT 0x1f
++#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
++#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
++#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
++#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
++#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
++#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
++#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
++#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f
++#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0
++#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f
++#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0
++#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000
++#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10
++#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff
++#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0
++#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
++#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
++#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00
++#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
++#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
++#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
++#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
++#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
++#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
++#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
++#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
++#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
++#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
++#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
++#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
++#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
++#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
++#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
++#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
++#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
++#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
++#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
++#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
++#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
++#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
++#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
++#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
++#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
++#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
++#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
++#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
++#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
++#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1
++#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0
++#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
++#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
++#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
++#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
++#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
++#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
++#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
++#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
++#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
++#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
++#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
++#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
++#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
++#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
++#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
++#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
++#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
++#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
++#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
++#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
++#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
++#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
++#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
++#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
++#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
++#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
++#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
++#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
++#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
++#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
++#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
++#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
++#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
++#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
++#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
++#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
++#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
++#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
++#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
++#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
++#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
++#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
++#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
++#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
++#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
++#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
++#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
++#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
++#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
++#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
++#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
++#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
++#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
++#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
++#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
++#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
++#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
++#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
++#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
++#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
++#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
++#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
++#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
++#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
++#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
++#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
++#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
++#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
++#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
++#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
++#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
++#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
++#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
++#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
++#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
++#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
++#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
++#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
++#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
++#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
++#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
++#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
++#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
++#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
++#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
++#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
++#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
++#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
++#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
++#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
++#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
++#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
++#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000
++#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
++#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
++#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
++#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
++#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
++#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
++#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
++#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
++#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
++#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
++#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
++#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
++#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
++#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
++#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
++#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
++#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
++#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
++#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
++#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
++#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
++#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
++#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
++#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
++#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
++#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
++#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
++#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
++#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
++#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
++#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
++#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
++#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
++#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
++#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
++#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
++#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
++#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
++#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
++#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
++#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
++#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
++#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
++#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
++#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
++#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
++#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
++#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
++#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
++#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
++#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
++#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
++#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
++#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
++#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
++#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
++#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
++#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
++#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
++#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
++#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
++#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
++#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
++#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
++#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
++#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
++#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
++#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
++#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
++#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
++#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
++#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
++#define CP_RINGID__RINGID_MASK 0x3
++#define CP_RINGID__RINGID__SHIFT 0x0
++#define CP_PIPEID__PIPE_ID_MASK 0x3
++#define CP_PIPEID__PIPE_ID__SHIFT 0x0
++#define CP_VMID__VMID_MASK 0xf
++#define CP_VMID__VMID__SHIFT 0x0
++#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
++#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
++#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
++#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
++#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
++#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
++#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
++#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
++#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
++#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
++#define CP_HPD_EOP_VMID__VMID_MASK 0xf
++#define CP_HPD_EOP_VMID__VMID__SHIFT 0x0
++#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
++#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
++#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
++#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
++#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00
++#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9
++#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
++#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
++#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
++#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
++#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
++#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
++#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000
++#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
++#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000
++#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
++#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000
++#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a
++#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000
++#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c
++#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
++#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
++#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
++#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
++#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
++#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
++#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
++#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
++#define CP_HQD_VMID__VMID_MASK 0xf
++#define CP_HQD_VMID__VMID__SHIFT 0x0
++#define CP_HQD_VMID__IB_VMID_MASK 0xf00
++#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
++#define CP_HQD_VMID__VQID_MASK 0x3ff0000
++#define CP_HQD_VMID__VQID__SHIFT 0x10
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
++#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
++#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
++#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
++#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
++#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
++#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
++#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
++#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
++#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
++#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
++#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
++#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
++#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
++#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
++#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
++#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
++#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
++#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
++#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
++#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
++#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
++#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
++#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
++#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
++#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
++#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
++#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
++#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
++#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
++#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
++#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
++#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
++#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000
++#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10
++#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
++#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
++#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
++#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
++#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000
++#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000
++#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a
++#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
++#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
++#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
++#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
++#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
++#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
++#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
++#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
++#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
++#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
++#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
++#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
++#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
++#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
++#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
++#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
++#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
++#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
++#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
++#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
++#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
++#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
++#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000
++#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000
++#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a
++#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
++#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
++#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
++#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
++#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
++#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
++#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
++#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
++#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
++#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
++#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
++#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
++#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000
++#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000
++#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a
++#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
++#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
++#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
++#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
++#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
++#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
++#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
++#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
++#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
++#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
++#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
++#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
++#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
++#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
++#define CP_HQD_MSG_TYPE__ACTION_MASK 0x3
++#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
++#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3
++#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0
++#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc
++#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2
++#define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30
++#define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4
++#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40
++#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6
++#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80
++#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7
++#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100
++#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8
++#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200
++#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9
++#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400
++#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa
++#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800
++#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb
++#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
++#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
++#define CP_MQD_CONTROL__VMID_MASK 0xf
++#define CP_MQD_CONTROL__VMID__SHIFT 0x0
++#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
++#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
++#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000
++#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
++#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000
++#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a
++#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
++#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
++#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
++#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
++#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
++#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
++#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
++#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
++#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
++#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
++#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
++#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
++#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
++#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
++#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
++#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
++#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
++#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
++#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
++#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
++#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
++#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
++#define DB_Z_INFO__FORMAT_MASK 0x3
++#define DB_Z_INFO__FORMAT__SHIFT 0x0
++#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
++#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
++#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
++#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
++#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
++#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
++#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
++#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
++#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
++#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
++#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
++#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
++#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
++#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
++#define DB_STENCIL_INFO__FORMAT_MASK 0x1
++#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
++#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
++#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
++#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
++#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
++#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
++#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
++#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
++#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
++#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
++#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
++#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
++#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
++#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
++#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
++#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
++#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
++#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
++#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
++#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
++#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
++#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
++#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
++#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
++#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
++#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
++#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
++#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
++#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
++#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
++#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
++#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
++#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
++#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
++#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
++#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
++#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
++#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
++#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
++#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
++#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
++#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
++#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
++#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
++#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
++#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
++#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
++#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
++#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
++#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
++#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
++#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
++#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
++#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
++#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
++#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
++#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
++#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
++#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
++#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
++#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
++#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
++#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
++#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
++#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
++#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
++#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
++#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
++#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
++#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
++#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
++#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
++#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
++#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
++#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
++#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
++#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
++#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
++#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
++#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
++#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
++#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
++#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
++#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
++#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
++#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
++#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
++#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
++#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
++#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
++#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
++#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
++#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
++#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
++#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
++#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
++#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
++#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
++#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
++#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
++#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
++#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
++#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
++#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
++#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
++#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
++#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
++#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
++#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
++#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
++#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
++#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
++#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
++#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
++#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
++#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
++#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
++#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
++#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
++#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
++#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
++#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
++#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
++#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
++#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
++#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
++#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
++#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
++#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
++#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
++#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
++#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
++#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
++#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
++#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
++#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
++#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
++#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
++#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
++#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
++#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
++#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
++#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
++#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
++#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
++#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
++#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
++#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
++#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
++#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
++#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
++#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
++#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
++#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
++#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
++#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
++#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
++#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
++#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
++#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
++#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
++#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
++#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
++#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
++#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
++#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
++#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
++#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
++#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
++#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
++#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
++#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
++#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
++#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
++#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
++#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
++#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
++#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
++#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
++#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
++#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
++#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
++#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
++#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
++#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
++#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
++#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
++#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
++#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
++#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
++#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
++#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
++#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
++#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
++#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
++#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
++#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
++#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
++#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
++#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
++#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
++#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
++#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
++#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
++#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
++#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
++#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
++#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
++#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
++#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
++#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
++#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
++#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
++#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
++#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
++#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
++#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
++#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
++#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
++#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
++#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
++#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
++#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
++#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
++#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
++#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
++#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
++#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
++#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
++#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
++#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
++#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
++#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
++#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
++#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
++#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
++#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
++#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
++#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
++#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
++#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
++#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
++#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
++#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
++#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
++#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
++#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
++#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
++#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
++#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
++#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
++#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
++#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
++#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
++#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
++#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
++#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
++#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
++#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
++#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
++#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
++#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
++#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
++#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
++#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
++#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
++#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
++#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
++#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
++#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
++#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
++#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
++#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
++#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
++#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
++#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
++#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
++#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
++#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
++#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
++#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
++#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
++#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
++#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
++#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
++#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
++#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
++#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
++#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
++#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
++#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
++#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
++#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
++#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
++#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
++#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
++#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
++#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
++#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
++#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
++#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
++#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
++#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
++#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
++#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
++#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
++#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
++#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
++#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
++#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
++#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
++#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
++#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
++#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
++#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
++#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
++#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
++#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
++#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
++#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
++#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
++#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
++#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
++#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
++#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
++#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
++#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
++#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
++#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
++#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
++#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
++#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
++#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
++#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
++#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
++#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
++#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
++#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
++#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
++#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
++#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
++#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
++#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
++#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
++#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
++#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
++#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
++#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
++#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
++#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
++#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
++#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
++#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
++#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
++#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
++#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
++#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
++#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
++#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
++#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
++#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
++#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
++#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
++#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
++#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
++#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
++#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
++#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
++#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
++#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
++#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
++#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
++#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
++#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
++#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
++#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
++#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
++#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
++#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
++#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
++#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
++#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
++#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
++#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
++#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
++#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
++#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000
++#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e
++#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
++#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
++#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
++#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
++#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
++#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
++#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
++#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
++#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
++#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
++#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
++#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
++#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
++#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
++#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
++#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
++#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
++#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
++#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
++#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
++#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
++#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
++#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
++#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
++#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
++#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
++#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
++#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
++#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
++#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
++#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
++#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
++#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
++#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
++#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
++#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
++#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
++#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
++#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
++#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
++#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
++#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
++#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
++#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
++#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
++#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
++#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
++#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
++#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
++#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
++#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
++#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
++#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
++#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
++#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
++#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
++#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
++#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
++#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
++#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
++#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
++#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
++#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
++#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
++#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
++#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
++#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
++#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
++#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
++#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
++#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
++#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
++#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
++#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
++#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
++#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
++#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
++#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
++#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
++#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
++#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
++#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
++#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
++#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
++#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
++#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
++#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
++#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
++#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
++#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
++#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
++#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
++#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
++#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
++#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
++#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
++#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
++#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
++#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
++#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
++#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
++#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
++#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
++#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
++#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
++#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
++#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
++#define GB_GPU_ID__GPU_ID_MASK 0xf
++#define GB_GPU_ID__GPU_ID__SHIFT 0x0
++#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
++#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
++#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
++#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
++#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
++#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
++#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
++#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
++#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
++#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
++#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
++#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
++#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
++#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
++#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
++#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
++#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
++#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
++#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
++#define GB_EDC_MODE__DED_MODE_MASK 0x300000
++#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
++#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
++#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
++#define GB_EDC_MODE__BYPASS_MASK 0x80000000
++#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
++#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
++#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
++#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
++#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
++#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
++#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
++#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
++#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
++#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
++#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
++#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
++#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
++#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
++#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
++#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0xf
++#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x0
++#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0xf0
++#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x4
++#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
++#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
++#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
++#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
++#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
++#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
++#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
++#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
++#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
++#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
++#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
++#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
++#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
++#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
++#define GRBM_STATUS__TA_BUSY_MASK 0x4000
++#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
++#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
++#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
++#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
++#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
++#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
++#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
++#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
++#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
++#define GRBM_STATUS__IA_BUSY_MASK 0x80000
++#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
++#define GRBM_STATUS__SX_BUSY_MASK 0x100000
++#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
++#define GRBM_STATUS__WD_BUSY_MASK 0x200000
++#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
++#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
++#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
++#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
++#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
++#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
++#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
++#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
++#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
++#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
++#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
++#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
++#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
++#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
++#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
++#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
++#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
++#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
++#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
++#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
++#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
++#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
++#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
++#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
++#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
++#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
++#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
++#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
++#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
++#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
++#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
++#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
++#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
++#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
++#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
++#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
++#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
++#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
++#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
++#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
++#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
++#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
++#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
++#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
++#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
++#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
++#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
++#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
++#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
++#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
++#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
++#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
++#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
++#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
++#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
++#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
++#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
++#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
++#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
++#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
++#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
++#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
++#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
++#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
++#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
++#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
++#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
++#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
++#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
++#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
++#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
++#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
++#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
++#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
++#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
++#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
++#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
++#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
++#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
++#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
++#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
++#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
++#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
++#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
++#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
++#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
++#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
++#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
++#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
++#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
++#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
++#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
++#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
++#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
++#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
++#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
++#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
++#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
++#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
++#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
++#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
++#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
++#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
++#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
++#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
++#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
++#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
++#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
++#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
++#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
++#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
++#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
++#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
++#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
++#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
++#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
++#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
++#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
++#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
++#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
++#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
++#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
++#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
++#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
++#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
++#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
++#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
++#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
++#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
++#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
++#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
++#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
++#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
++#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
++#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
++#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
++#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
++#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
++#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
++#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
++#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
++#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
++#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
++#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
++#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
++#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
++#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
++#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
++#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
++#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
++#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
++#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
++#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
++#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
++#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
++#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
++#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
++#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
++#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
++#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
++#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
++#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
++#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
++#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
++#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
++#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
++#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
++#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
++#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
++#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
++#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
++#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
++#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
++#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
++#define GRBM_NOWHERE__DATA_MASK 0xffffffff
++#define GRBM_NOWHERE__DATA__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
++#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
++#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
++#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
++#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
++#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
++#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
++#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
++#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
++#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
++#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
++#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
++#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
++#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
++#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
++#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
++#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
++#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
++#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
++#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
++#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
++#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
++#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
++#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
++#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
++#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
++#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
++#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
++#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
++#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
++#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
++#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
++#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
++#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
++#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
++#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
++#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
++#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
++#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
++#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
++#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
++#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
++#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
++#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
++#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
++#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
++#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
++#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
++#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
++#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
++#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
++#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
++#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
++#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
++#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
++#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
++#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
++#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
++#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
++#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
++#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
++#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
++#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
++#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
++#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
++#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
++#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
++#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
++#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
++#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
++#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
++#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
++#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
++#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
++#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
++#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
++#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
++#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
++#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
++#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
++#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
++#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
++#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
++#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
++#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
++#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
++#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
++#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
++#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
++#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
++#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
++#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
++#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
++#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
++#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
++#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
++#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
++#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
++#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
++#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
++#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
++#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
++#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
++#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
++#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
++#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
++#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
++#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
++#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
++#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
++#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
++#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
++#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
++#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
++#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
++#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
++#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
++#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
++#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
++#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
++#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
++#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
++#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
++#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
++#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
++#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
++#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
++#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
++#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
++#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
++#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
++#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
++#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
++#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
++#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
++#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
++#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
++#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
++#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
++#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
++#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
++#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
++#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
++#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
++#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
++#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
++#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
++#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
++#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
++#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
++#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
++#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
++#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
++#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
++#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
++#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
++#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
++#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
++#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
++#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
++#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
++#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
++#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
++#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
++#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
++#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
++#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
++#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
++#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
++#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
++#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
++#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
++#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
++#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
++#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
++#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
++#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
++#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
++#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
++#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
++#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
++#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
++#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
++#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
++#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
++#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
++#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
++#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
++#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
++#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
++#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
++#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
++#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
++#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
++#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
++#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
++#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
++#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
++#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
++#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
++#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
++#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
++#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
++#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
++#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
++#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
++#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
++#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
++#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
++#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
++#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
++#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
++#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
++#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
++#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
++#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
++#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
++#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
++#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
++#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
++#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
++#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
++#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
++#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
++#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
++#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
++#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
++#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
++#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
++#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
++#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
++#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
++#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
++#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
++#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
++#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
++#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
++#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
++#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
++#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
++#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
++#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
++#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
++#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
++#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
++#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
++#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
++#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
++#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
++#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
++#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
++#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
++#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
++#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
++#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
++#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
++#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
++#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
++#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
++#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
++#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
++#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
++#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
++#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
++#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
++#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
++#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
++#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
++#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
++#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
++#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
++#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
++#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
++#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
++#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
++#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
++#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
++#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
++#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
++#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
++#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
++#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
++#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
++#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
++#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
++#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
++#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
++#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
++#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
++#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
++#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
++#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
++#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
++#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
++#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
++#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
++#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
++#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
++#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
++#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
++#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
++#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
++#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
++#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
++#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
++#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
++#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
++#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
++#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
++#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
++#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
++#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
++#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
++#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
++#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
++#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
++#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
++#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
++#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
++#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
++#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
++#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
++#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
++#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
++#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
++#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
++#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
++#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
++#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
++#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
++#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
++#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
++#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
++#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
++#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
++#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
++#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
++#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
++#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
++#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
++#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
++#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
++#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
++#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
++#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
++#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
++#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
++#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
++#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
++#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
++#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
++#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
++#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
++#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
++#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
++#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
++#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
++#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
++#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
++#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
++#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
++#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
++#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
++#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
++#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
++#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
++#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
++#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
++#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
++#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
++#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
++#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
++#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
++#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
++#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
++#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
++#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
++#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
++#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
++#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
++#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
++#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
++#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
++#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
++#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
++#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
++#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
++#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
++#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
++#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
++#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
++#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
++#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
++#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
++#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
++#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
++#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
++#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
++#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
++#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
++#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
++#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
++#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
++#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
++#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
++#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
++#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
++#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
++#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
++#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
++#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
++#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
++#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
++#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
++#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
++#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
++#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
++#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
++#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
++#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
++#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
++#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
++#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
++#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
++#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
++#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
++#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
++#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
++#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
++#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
++#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
++#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
++#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
++#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
++#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
++#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
++#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
++#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
++#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
++#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
++#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
++#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
++#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
++#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
++#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
++#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
++#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
++#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
++#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
++#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
++#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
++#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
++#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
++#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
++#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
++#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
++#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
++#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
++#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
++#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
++#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
++#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
++#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
++#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
++#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
++#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
++#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
++#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
++#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
++#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
++#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
++#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
++#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
++#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
++#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
++#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
++#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
++#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
++#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
++#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
++#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
++#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
++#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
++#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
++#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
++#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
++#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
++#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
++#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
++#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
++#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
++#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
++#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
++#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
++#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
++#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
++#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
++#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
++#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
++#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
++#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
++#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
++#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
++#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
++#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
++#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
++#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
++#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
++#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
++#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
++#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
++#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
++#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
++#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
++#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
++#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
++#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
++#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
++#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
++#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
++#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
++#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
++#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
++#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
++#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
++#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
++#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
++#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
++#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
++#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
++#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
++#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
++#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
++#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
++#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
++#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
++#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
++#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
++#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
++#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
++#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
++#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
++#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
++#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
++#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
++#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
++#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
++#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
++#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
++#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
++#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
++#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
++#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
++#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
++#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
++#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
++#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
++#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
++#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
++#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
++#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
++#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
++#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
++#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
++#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
++#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
++#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
++#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
++#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
++#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
++#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
++#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
++#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
++#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
++#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
++#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
++#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
++#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
++#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
++#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
++#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
++#define COMPUTE_START_X__START_MASK 0xffffffff
++#define COMPUTE_START_X__START__SHIFT 0x0
++#define COMPUTE_START_Y__START_MASK 0xffffffff
++#define COMPUTE_START_Y__START__SHIFT 0x0
++#define COMPUTE_START_Z__START_MASK 0xffffffff
++#define COMPUTE_START_Z__START__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
++#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
++#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
++#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
++#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
++#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
++#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
++#define COMPUTE_PGM_HI__DATA_MASK 0xff
++#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
++#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
++#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
++#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
++#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
++#define COMPUTE_TBA_HI__DATA_MASK 0xff
++#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
++#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
++#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
++#define COMPUTE_TMA_HI__DATA_MASK 0xff
++#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
++#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
++#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
++#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
++#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
++#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
++#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
++#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
++#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
++#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
++#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
++#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
++#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
++#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
++#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
++#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
++#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
++#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
++#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
++#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
++#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
++#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
++#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
++#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
++#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
++#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
++#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
++#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
++#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
++#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
++#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
++#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
++#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
++#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
++#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
++#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
++#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
++#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
++#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
++#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
++#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
++#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
++#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
++#define COMPUTE_VMID__DATA_MASK 0xf
++#define COMPUTE_VMID__DATA__SHIFT 0x0
++#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
++#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
++#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
++#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
++#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
++#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
++#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
++#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
++#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
++#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
++#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
++#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
++#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
++#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
++#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
++#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
++#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
++#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
++#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
++#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
++#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
++#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
++#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
++#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
++#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
++#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
++#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
++#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
++#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
++#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
++#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
++#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
++#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
++#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
++#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
++#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
++#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
++#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
++#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
++#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
++#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
++#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
++#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
++#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
++#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
++#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
++#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
++#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
++#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
++#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
++#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
++#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
++#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
++#define RLC_CNTL__FORCE_RETRY_MASK 0x2
++#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
++#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
++#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
++#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
++#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
++#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
++#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
++#define RLC_CNTL__RESERVED_MASK 0xffffff00
++#define RLC_CNTL__RESERVED__SHIFT 0x8
++#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
++#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
++#define RLC_DEBUG__DATA_MASK 0xffffffff
++#define RLC_DEBUG__DATA__SHIFT 0x0
++#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
++#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
++#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
++#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
++#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
++#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
++#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
++#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
++#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
++#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
++#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
++#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
++#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
++#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
++#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
++#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
++#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
++#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
++#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
++#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
++#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
++#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
++#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
++#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
++#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
++#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
++#define RLC_STAT__RLC_BUSY_MASK 0x1
++#define RLC_STAT__RLC_BUSY__SHIFT 0x0
++#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
++#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
++#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
++#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
++#define RLC_STAT__RESERVED_MASK 0xfffffff8
++#define RLC_STAT__RESERVED__SHIFT 0x3
++#define RLC_SAFE_MODE__REQ_MASK 0x1
++#define RLC_SAFE_MODE__REQ__SHIFT 0x0
++#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
++#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
++#define RLC_SAFE_MODE__RESERVED_MASK 0xffffffe0
++#define RLC_SAFE_MODE__RESERVED__SHIFT 0x5
++#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
++#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
++#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
++#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
++#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
++#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
++#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0xfc
++#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
++#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
++#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
++#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
++#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
++#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
++#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
++#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
++#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
++#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
++#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
++#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
++#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
++#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
++#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
++#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
++#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
++#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
++#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
++#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
++#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
++#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
++#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
++#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
++#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
++#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
++#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
++#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
++#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
++#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
++#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
++#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
++#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
++#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
++#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
++#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
++#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
++#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
++#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
++#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
++#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
++#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
++#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
++#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
++#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
++#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
++#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
++#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
++#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
++#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
++#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
++#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
++#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
++#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
++#define RLC_GPM_STAT__RESERVED_MASK 0xfffffff0
++#define RLC_GPM_STAT__RESERVED__SHIFT 0x4
++#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
++#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
++#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
++#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
++#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
++#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
++#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
++#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
++#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
++#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
++#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
++#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
++#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
++#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
++#define RLC_PG_CNTL__RESERVED_MASK 0xfff0
++#define RLC_PG_CNTL__RESERVED__SHIFT 0x4
++#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
++#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
++#define RLC_PG_CNTL__RESERVED1_MASK 0xf80000
++#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13
++#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000
++#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x18
++#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
++#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
++#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
++#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
++#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
++#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
++#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
++#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
++#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
++#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
++#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
++#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
++#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
++#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
++#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
++#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
++#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
++#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
++#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
++#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
++#define RLC_GPM_VMID_THREAD0__RESERVED_MASK 0xfffffff0
++#define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT 0x4
++#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
++#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
++#define RLC_GPM_VMID_THREAD1__RESERVED_MASK 0xfffffff0
++#define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT 0x4
++#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
++#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
++#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
++#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
++#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
++#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
++#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
++#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
++#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
++#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
++#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
++#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
++#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
++#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
++#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
++#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
++#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000
++#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x1f
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
++#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
++#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
++#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
++#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
++#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
++#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
++#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
++#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
++#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
++#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
++#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
++#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
++#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
++#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
++#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
++#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
++#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
++#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
++#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
++#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
++#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
++#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
++#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
++#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
++#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
++#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
++#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
++#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
++#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
++#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
++#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
++#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
++#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
++#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
++#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
++#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
++#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
++#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
++#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
++#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
++#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
++#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
++#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
++#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
++#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
++#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
++#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
++#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
++#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
++#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
++#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
++#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
++#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
++#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
++#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
++#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
++#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
++#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
++#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
++#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
++#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x3800
++#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
++#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0xc000
++#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xe
++#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffff0000
++#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x10
++#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
++#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
++#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
++#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
++#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
++#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
++#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
++#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x20000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x11
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x40000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x12
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x80000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x13
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x100000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x14
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x200000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x15
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x400000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x16
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff800000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x17
++#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
++#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
++#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
++#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
++#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
++#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
++#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
++#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
++#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
++#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
++#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
++#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
++#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
++#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
++#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0xc000
++#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0xe
++#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x10000
++#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x10
++#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x20000
++#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x11
++#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x40000
++#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x12
++#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x80000
++#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x13
++#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x100000
++#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x14
++#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x200000
++#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x15
++#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x400000
++#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x16
++#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x800000
++#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x17
++#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0xf000000
++#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x18
++#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
++#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
++#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
++#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
++#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
++#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
++#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
++#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x20000
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x11
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x40000
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x12
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x80000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x13
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x100000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x14
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x200000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x15
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x400000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x16
++#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff800000
++#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x17
++#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
++#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
++#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
++#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
++#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
++#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
++#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
++#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
++#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
++#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
++#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
++#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
++#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
++#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
++#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
++#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
++#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
++#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
++#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
++#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
++#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
++#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
++#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
++#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
++#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
++#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
++#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
++#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
++#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
++#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
++#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
++#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
++#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
++#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
++#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
++#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
++#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
++#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
++#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
++#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
++#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
++#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
++#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
++#define RLC_GPR_REG1__DATA_MASK 0xffffffff
++#define RLC_GPR_REG1__DATA__SHIFT 0x0
++#define RLC_GPR_REG2__DATA_MASK 0xffffffff
++#define RLC_GPR_REG2__DATA__SHIFT 0x0
++#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
++#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
++#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
++#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
++#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
++#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
++#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
++#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
++#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
++#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
++#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
++#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
++#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
++#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
++#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
++#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
++#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
++#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
++#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
++#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
++#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
++#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
++#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
++#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
++#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
++#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
++#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
++#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
++#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
++#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
++#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
++#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
++#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
++#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
++#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
++#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
++#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
++#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
++#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
++#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
++#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
++#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
++#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
++#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
++#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
++#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
++#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
++#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
++#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
++#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
++#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
++#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
++#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
++#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
++#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
++#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
++#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
++#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
++#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
++#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
++#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
++#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
++#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
++#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
++#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
++#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
++#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
++#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
++#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
++#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
++#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
++#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
++#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
++#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
++#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
++#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
++#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
++#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
++#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
++#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
++#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
++#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
++#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
++#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
++#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
++#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
++#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
++#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
++#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
++#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
++#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
++#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
++#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
++#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
++#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
++#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
++#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
++#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
++#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
++#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
++#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
++#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
++#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
++#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
++#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
++#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
++#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
++#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
++#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
++#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
++#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
++#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
++#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
++#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
++#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
++#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
++#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
++#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
++#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
++#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
++#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
++#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
++#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
++#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
++#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
++#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
++#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
++#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
++#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
++#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
++#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
++#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
++#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
++#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
++#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
++#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
++#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
++#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
++#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
++#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
++#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
++#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
++#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
++#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
++#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
++#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
++#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
++#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
++#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
++#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
++#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
++#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
++#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
++#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
++#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
++#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
++#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
++#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
++#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
++#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
++#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
++#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
++#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
++#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
++#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
++#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
++#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
++#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
++#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
++#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
++#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
++#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
++#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
++#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
++#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
++#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
++#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
++#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
++#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
++#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
++#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
++#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
++#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
++#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
++#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
++#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
++#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
++#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
++#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
++#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
++#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
++#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
++#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
++#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
++#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
++#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
++#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
++#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
++#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
++#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
++#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
++#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
++#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
++#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
++#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
++#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
++#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
++#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
++#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
++#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
++#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
++#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
++#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
++#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
++#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
++#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
++#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
++#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
++#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
++#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
++#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
++#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
++#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
++#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x1f
++#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
++#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
++#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
++#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
++#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
++#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
++#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
++#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
++#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
++#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
++#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
++#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
++#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
++#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
++#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
++#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
++#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
++#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
++#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
++#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
++#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
++#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
++#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
++#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
++#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
++#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
++#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
++#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
++#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
++#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
++#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
++#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
++#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
++#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
++#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
++#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
++#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
++#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
++#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
++#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
++#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
++#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
++#define SPI_DEBUG_READ__DATA_MASK 0xffffff
++#define SPI_DEBUG_READ__DATA__SHIFT 0x0
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
++#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
++#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
++#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
++#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
++#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
++#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
++#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
++#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
++#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
++#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
++#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
++#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
++#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
++#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
++#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
++#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
++#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
++#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
++#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
++#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
++#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
++#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
++#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
++#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
++#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
++#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
++#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
++#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
++#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
++#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
++#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
++#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
++#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
++#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
++#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
++#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
++#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
++#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
++#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
++#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
++#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
++#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
++#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
++#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
++#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
++#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
++#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
++#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
++#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
++#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
++#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
++#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
++#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
++#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
++#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
++#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
++#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
++#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
++#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
++#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
++#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
++#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
++#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
++#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
++#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
++#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
++#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
++#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
++#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
++#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
++#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
++#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
++#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
++#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
++#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
++#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
++#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
++#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
++#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
++#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
++#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
++#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
++#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
++#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
++#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
++#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
++#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
++#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
++#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
++#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
++#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
++#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
++#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
++#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
++#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
++#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
++#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
++#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
++#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
++#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
++#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
++#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
++#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
++#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
++#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
++#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
++#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
++#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
++#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
++#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
++#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
++#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
++#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
++#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
++#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
++#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
++#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
++#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
++#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
++#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
++#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
++#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
++#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
++#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
++#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
++#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
++#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
++#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
++#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
++#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
++#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
++#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
++#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
++#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
++#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
++#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
++#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
++#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
++#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
++#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
++#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
++#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
++#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
++#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
++#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
++#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
++#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
++#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
++#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
++#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
++#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
++#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
++#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
++#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
++#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
++#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
++#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
++#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
++#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
++#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
++#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
++#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
++#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
++#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
++#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
++#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
++#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
++#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
++#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
++#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
++#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
++#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
++#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
++#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
++#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
++#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
++#define BCI_DEBUG_READ__DATA_MASK 0xffffff
++#define BCI_DEBUG_READ__DATA__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
++#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
++#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
++#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
++#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
++#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
++#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
++#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
++#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
++#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
++#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
++#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
++#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
++#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
++#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
++#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
++#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
++#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
++#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
++#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
++#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
++#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
++#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
++#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
++#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
++#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
++#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
++#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
++#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
++#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
++#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
++#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
++#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
++#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
++#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
++#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
++#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
++#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
++#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
++#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
++#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
++#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
++#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
++#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
++#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
++#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
++#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
++#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
++#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
++#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
++#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
++#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
++#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
++#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
++#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
++#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
++#define SQ_CONFIG__UNUSED_MASK 0xff
++#define SQ_CONFIG__UNUSED__SHIFT 0x0
++#define SQ_CONFIG__DEBUG_EN_MASK 0x100
++#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
++#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x200
++#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x9
++#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x400
++#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0xa
++#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x800
++#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0xb
++#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
++#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
++#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
++#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
++#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
++#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
++#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
++#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
++#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
++#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
++#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
++#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
++#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
++#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
++#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
++#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
++#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
++#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
++#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
++#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
++#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
++#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
++#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
++#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
++#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
++#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
++#define SQC_CACHES__INST_INVALIDATE_MASK 0x1
++#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x0
++#define SQC_CACHES__DATA_INVALIDATE_MASK 0x2
++#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x1
++#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x4
++#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x2
++#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
++#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
++#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
++#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
++#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
++#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
++#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
++#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
++#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
++#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
++#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
++#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
++#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
++#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
++#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
++#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
++#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
++#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
++#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
++#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
++#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
++#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
++#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
++#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
++#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
++#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
++#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
++#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
++#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
++#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
++#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
++#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
++#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
++#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
++#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
++#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
++#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
++#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
++#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
++#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
++#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
++#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
++#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
++#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
++#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
++#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
++#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
++#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
++#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
++#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
++#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
++#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
++#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
++#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
++#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
++#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
++#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
++#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
++#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
++#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
++#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
++#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
++#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
++#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
++#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
++#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
++#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
++#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
++#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
++#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0xff
++#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
++#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
++#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
++#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
++#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
++#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
++#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
++#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
++#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
++#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
++#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
++#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
++#define SQ_TIME_HI__TIME_MASK 0xffffffff
++#define SQ_TIME_HI__TIME__SHIFT 0x0
++#define SQ_TIME_LO__TIME_MASK 0xffffffff
++#define SQ_TIME_LO__TIME__SHIFT 0x0
++#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
++#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
++#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
++#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x10
++#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x4
++#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
++#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
++#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
++#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
++#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
++#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
++#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
++#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
++#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
++#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
++#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
++#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
++#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
++#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
++#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
++#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
++#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000
++#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x10
++#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
++#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
++#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
++#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
++#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
++#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
++#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
++#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
++#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
++#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
++#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
++#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
++#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
++#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
++#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
++#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
++#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
++#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
++#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
++#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
++#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
++#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
++#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
++#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
++#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
++#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
++#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
++#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
++#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
++#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
++#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
++#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
++#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
++#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
++#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffff
++#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
++#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
++#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
++#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
++#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
++#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
++#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
++#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
++#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
++#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
++#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
++#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
++#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
++#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
++#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
++#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
++#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
++#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
++#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
++#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
++#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
++#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
++#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
++#define SQ_LB_CTR_CTRL__START_MASK 0x1
++#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
++#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
++#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
++#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
++#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
++#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
++#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
++#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
++#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
++#define SQC_SECDED_CNT__INST_SEC_MASK 0xff
++#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x0
++#define SQC_SECDED_CNT__INST_DED_MASK 0xff00
++#define SQC_SECDED_CNT__INST_DED__SHIFT 0x8
++#define SQC_SECDED_CNT__DATA_SEC_MASK 0xff0000
++#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x10
++#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000
++#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x18
++#define SQ_SEC_CNT__LDS_SEC_MASK 0x3f
++#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x0
++#define SQ_SEC_CNT__SGPR_SEC_MASK 0x1f00
++#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x8
++#define SQ_SEC_CNT__VGPR_SEC_MASK 0x1ff0000
++#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x10
++#define SQ_DED_CNT__LDS_DED_MASK 0x3f
++#define SQ_DED_CNT__LDS_DED__SHIFT 0x0
++#define SQ_DED_CNT__SGPR_DED_MASK 0x1f00
++#define SQ_DED_CNT__SGPR_DED__SHIFT 0x8
++#define SQ_DED_CNT__VGPR_DED_MASK 0x1ff0000
++#define SQ_DED_CNT__VGPR_DED__SHIFT 0x10
++#define SQ_DED_INFO__WAVE_ID_MASK 0xf
++#define SQ_DED_INFO__WAVE_ID__SHIFT 0x0
++#define SQ_DED_INFO__SIMD_ID_MASK 0x30
++#define SQ_DED_INFO__SIMD_ID__SHIFT 0x4
++#define SQ_DED_INFO__SOURCE_MASK 0x1c0
++#define SQ_DED_INFO__SOURCE__SHIFT 0x6
++#define SQ_DED_INFO__VM_ID_MASK 0x1e00
++#define SQ_DED_INFO__VM_ID__SHIFT 0x9
++#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
++#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
++#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
++#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
++#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
++#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
++#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
++#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
++#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
++#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
++#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
++#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
++#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
++#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
++#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
++#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
++#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
++#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
++#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
++#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
++#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
++#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
++#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
++#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
++#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
++#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
++#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
++#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
++#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
++#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
++#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
++#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
++#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
++#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
++#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
++#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
++#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
++#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
++#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
++#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
++#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
++#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
++#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
++#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
++#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
++#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
++#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
++#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
++#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
++#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
++#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
++#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
++#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
++#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
++#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
++#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
++#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
++#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
++#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
++#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
++#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
++#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
++#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
++#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
++#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
++#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
++#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
++#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
++#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
++#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
++#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
++#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
++#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
++#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
++#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
++#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
++#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
++#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
++#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
++#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000
++#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x15
++#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffff
++#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
++#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
++#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
++#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
++#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
++#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
++#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
++#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
++#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
++#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
++#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
++#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
++#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
++#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
++#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
++#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
++#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
++#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
++#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
++#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
++#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
++#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
++#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
++#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
++#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
++#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
++#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
++#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
++#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
++#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
++#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
++#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
++#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
++#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
++#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
++#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
++#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
++#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
++#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
++#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
++#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
++#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
++#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
++#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
++#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
++#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
++#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
++#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
++#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
++#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
++#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
++#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
++#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
++#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
++#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
++#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
++#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
++#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
++#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
++#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
++#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
++#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
++#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
++#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
++#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
++#define SQ_IND_INDEX__INDEX__SHIFT 0x10
++#define SQ_CMD__CMD_MASK 0x7
++#define SQ_CMD__CMD__SHIFT 0x0
++#define SQ_CMD__MODE_MASK 0x70
++#define SQ_CMD__MODE__SHIFT 0x4
++#define SQ_CMD__CHECK_VMID_MASK 0x80
++#define SQ_CMD__CHECK_VMID__SHIFT 0x7
++#define SQ_CMD__TRAP_ID_MASK 0x700
++#define SQ_CMD__TRAP_ID__SHIFT 0x8
++#define SQ_CMD__WAVE_ID_MASK 0xf0000
++#define SQ_CMD__WAVE_ID__SHIFT 0x10
++#define SQ_CMD__SIMD_ID_MASK 0x300000
++#define SQ_CMD__SIMD_ID__SHIFT 0x14
++#define SQ_CMD__QUEUE_ID_MASK 0x7000000
++#define SQ_CMD__QUEUE_ID__SHIFT 0x18
++#define SQ_CMD__VM_ID_MASK 0xf0000000
++#define SQ_CMD__VM_ID__SHIFT 0x1c
++#define SQ_IND_DATA__DATA_MASK 0xffffffff
++#define SQ_IND_DATA__DATA__SHIFT 0x0
++#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
++#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
++#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
++#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
++#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
++#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
++#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
++#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
++#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
++#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
++#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
++#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
++#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
++#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
++#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
++#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
++#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
++#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
++#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
++#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
++#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
++#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
++#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
++#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
++#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
++#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
++#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x70000
++#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
++#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x380000
++#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x13
++#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0xc00000
++#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x16
++#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x1000000
++#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x18
++#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x6000000
++#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x19
++#define SQ_WAVE_IB_DBG0__KILL_MASK 0x8000000
++#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1b
++#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000
++#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1c
++#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
++#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
++#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
++#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
++#define SQ_WAVE_STATUS__SCC_MASK 0x1
++#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
++#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
++#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
++#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x18
++#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x3
++#define SQ_WAVE_STATUS__PRIV_MASK 0x20
++#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
++#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
++#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
++#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
++#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
++#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
++#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
++#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
++#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
++#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
++#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
++#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
++#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
++#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
++#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
++#define SQ_WAVE_STATUS__HALT_MASK 0x2000
++#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
++#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
++#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
++#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
++#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
++#define SQ_WAVE_STATUS__VALID_MASK 0x10000
++#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
++#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
++#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
++#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
++#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
++#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
++#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
++#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
++#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
++#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
++#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
++#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x400000
++#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x16
++#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
++#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
++#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x7000000
++#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x18
++#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
++#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
++#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
++#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
++#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
++#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
++#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
++#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
++#define SQ_WAVE_MODE__IEEE_MASK 0x200
++#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
++#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
++#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
++#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
++#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
++#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
++#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
++#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
++#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
++#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
++#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
++#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
++#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
++#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
++#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
++#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
++#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
++#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
++#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
++#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
++#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
++#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
++#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
++#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
++#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
++#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
++#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
++#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
++#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
++#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
++#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
++#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
++#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
++#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
++#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
++#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
++#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
++#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
++#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
++#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
++#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
++#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
++#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
++#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
++#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
++#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
++#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
++#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
++#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
++#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
++#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
++#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
++#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
++#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
++#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
++#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
++#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
++#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
++#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
++#define SQ_WAVE_M0__M0_MASK 0xffffffff
++#define SQ_WAVE_M0__M0__SHIFT 0x0
++#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
++#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
++#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
++#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
++#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
++#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
++#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
++#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
++#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
++#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
++#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0xf0
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
++#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
++#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
++#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
++#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
++#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
++#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
++#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
++#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
++#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
++#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
++#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
++#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
++#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
++#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
++#define SH_MEM_CONFIG__PTR32_MASK 0x1
++#define SH_MEM_CONFIG__PTR32__SHIFT 0x0
++#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x2
++#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x1
++#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0xc
++#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2
++#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x70
++#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4
++#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x380
++#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x7
++#define SQC_POLICY__DATA_L1_POLICY_0_MASK 0x1
++#define SQC_POLICY__DATA_L1_POLICY_0__SHIFT 0x0
++#define SQC_POLICY__DATA_L1_POLICY_1_MASK 0x2
++#define SQC_POLICY__DATA_L1_POLICY_1__SHIFT 0x1
++#define SQC_POLICY__DATA_L1_POLICY_2_MASK 0x4
++#define SQC_POLICY__DATA_L1_POLICY_2__SHIFT 0x2
++#define SQC_POLICY__DATA_L1_POLICY_3_MASK 0x8
++#define SQC_POLICY__DATA_L1_POLICY_3__SHIFT 0x3
++#define SQC_POLICY__DATA_L1_POLICY_4_MASK 0x10
++#define SQC_POLICY__DATA_L1_POLICY_4__SHIFT 0x4
++#define SQC_POLICY__DATA_L1_POLICY_5_MASK 0x20
++#define SQC_POLICY__DATA_L1_POLICY_5__SHIFT 0x5
++#define SQC_POLICY__DATA_L1_POLICY_6_MASK 0x40
++#define SQC_POLICY__DATA_L1_POLICY_6__SHIFT 0x6
++#define SQC_POLICY__DATA_L1_POLICY_7_MASK 0x80
++#define SQC_POLICY__DATA_L1_POLICY_7__SHIFT 0x7
++#define SQC_POLICY__DATA_L2_POLICY_0_MASK 0x300
++#define SQC_POLICY__DATA_L2_POLICY_0__SHIFT 0x8
++#define SQC_POLICY__DATA_L2_POLICY_1_MASK 0xc00
++#define SQC_POLICY__DATA_L2_POLICY_1__SHIFT 0xa
++#define SQC_POLICY__DATA_L2_POLICY_2_MASK 0x3000
++#define SQC_POLICY__DATA_L2_POLICY_2__SHIFT 0xc
++#define SQC_POLICY__DATA_L2_POLICY_3_MASK 0xc000
++#define SQC_POLICY__DATA_L2_POLICY_3__SHIFT 0xe
++#define SQC_POLICY__DATA_L2_POLICY_4_MASK 0x30000
++#define SQC_POLICY__DATA_L2_POLICY_4__SHIFT 0x10
++#define SQC_POLICY__DATA_L2_POLICY_5_MASK 0xc0000
++#define SQC_POLICY__DATA_L2_POLICY_5__SHIFT 0x12
++#define SQC_POLICY__DATA_L2_POLICY_6_MASK 0x300000
++#define SQC_POLICY__DATA_L2_POLICY_6__SHIFT 0x14
++#define SQC_POLICY__DATA_L2_POLICY_7_MASK 0xc00000
++#define SQC_POLICY__DATA_L2_POLICY_7__SHIFT 0x16
++#define SQC_POLICY__INST_L2_POLICY_MASK 0x3000000
++#define SQC_POLICY__INST_L2_POLICY__SHIFT 0x18
++#define SQC_VOLATILE__DATA_L1_MASK 0xf
++#define SQC_VOLATILE__DATA_L1__SHIFT 0x0
++#define SQC_VOLATILE__DATA_L2_MASK 0xf0
++#define SQC_VOLATILE__DATA_L2__SHIFT 0x4
++#define SQC_VOLATILE__INST_L2_MASK 0x100
++#define SQC_VOLATILE__INST_L2__SHIFT 0x8
++#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
++#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
++#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x800
++#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0xb
++#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf000
++#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
++#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
++#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
++#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
++#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
++#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
++#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
++#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
++#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
++#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
++#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
++#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
++#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
++#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
++#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
++#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
++#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
++#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
++#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
++#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
++#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
++#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
++#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
++#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
++#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
++#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
++#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
++#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
++#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
++#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
++#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
++#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
++#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
++#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
++#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
++#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
++#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
++#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
++#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
++#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
++#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
++#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
++#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
++#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
++#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
++#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
++#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
++#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
++#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
++#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
++#define SQ_SOP2__SSRC0_MASK 0xff
++#define SQ_SOP2__SSRC0__SHIFT 0x0
++#define SQ_SOP2__SSRC1_MASK 0xff00
++#define SQ_SOP2__SSRC1__SHIFT 0x8
++#define SQ_SOP2__SDST_MASK 0x7f0000
++#define SQ_SOP2__SDST__SHIFT 0x10
++#define SQ_SOP2__OP_MASK 0x3f800000
++#define SQ_SOP2__OP__SHIFT 0x17
++#define SQ_SOP2__ENCODING_MASK 0xc0000000
++#define SQ_SOP2__ENCODING__SHIFT 0x1e
++#define SQ_VOP1__SRC0_MASK 0x1ff
++#define SQ_VOP1__SRC0__SHIFT 0x0
++#define SQ_VOP1__OP_MASK 0x1fe00
++#define SQ_VOP1__OP__SHIFT 0x9
++#define SQ_VOP1__VDST_MASK 0x1fe0000
++#define SQ_VOP1__VDST__SHIFT 0x11
++#define SQ_VOP1__ENCODING_MASK 0xfe000000
++#define SQ_VOP1__ENCODING__SHIFT 0x19
++#define SQ_MTBUF_1__VADDR_MASK 0xff
++#define SQ_MTBUF_1__VADDR__SHIFT 0x0
++#define SQ_MTBUF_1__VDATA_MASK 0xff00
++#define SQ_MTBUF_1__VDATA__SHIFT 0x8
++#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
++#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
++#define SQ_MTBUF_1__SLC_MASK 0x400000
++#define SQ_MTBUF_1__SLC__SHIFT 0x16
++#define SQ_MTBUF_1__TFE_MASK 0x800000
++#define SQ_MTBUF_1__TFE__SHIFT 0x17
++#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
++#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
++#define SQ_EXP_1__VSRC0_MASK 0xff
++#define SQ_EXP_1__VSRC0__SHIFT 0x0
++#define SQ_EXP_1__VSRC1_MASK 0xff00
++#define SQ_EXP_1__VSRC1__SHIFT 0x8
++#define SQ_EXP_1__VSRC2_MASK 0xff0000
++#define SQ_EXP_1__VSRC2__SHIFT 0x10
++#define SQ_EXP_1__VSRC3_MASK 0xff000000
++#define SQ_EXP_1__VSRC3__SHIFT 0x18
++#define SQ_MUBUF_1__VADDR_MASK 0xff
++#define SQ_MUBUF_1__VADDR__SHIFT 0x0
++#define SQ_MUBUF_1__VDATA_MASK 0xff00
++#define SQ_MUBUF_1__VDATA__SHIFT 0x8
++#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
++#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
++#define SQ_MUBUF_1__SLC_MASK 0x400000
++#define SQ_MUBUF_1__SLC__SHIFT 0x16
++#define SQ_MUBUF_1__TFE_MASK 0x800000
++#define SQ_MUBUF_1__TFE__SHIFT 0x17
++#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
++#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
++#define SQ_INST__ENCODING_MASK 0xffffffff
++#define SQ_INST__ENCODING__SHIFT 0x0
++#define SQ_EXP_0__EN_MASK 0xf
++#define SQ_EXP_0__EN__SHIFT 0x0
++#define SQ_EXP_0__TGT_MASK 0x3f0
++#define SQ_EXP_0__TGT__SHIFT 0x4
++#define SQ_EXP_0__COMPR_MASK 0x400
++#define SQ_EXP_0__COMPR__SHIFT 0xa
++#define SQ_EXP_0__DONE_MASK 0x800
++#define SQ_EXP_0__DONE__SHIFT 0xb
++#define SQ_EXP_0__VM_MASK 0x1000
++#define SQ_EXP_0__VM__SHIFT 0xc
++#define SQ_EXP_0__ENCODING_MASK 0xfc000000
++#define SQ_EXP_0__ENCODING__SHIFT 0x1a
++#define SQ_MUBUF_0__OFFSET_MASK 0xfff
++#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
++#define SQ_MUBUF_0__OFFEN_MASK 0x1000
++#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
++#define SQ_MUBUF_0__IDXEN_MASK 0x2000
++#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
++#define SQ_MUBUF_0__GLC_MASK 0x4000
++#define SQ_MUBUF_0__GLC__SHIFT 0xe
++#define SQ_MUBUF_0__ADDR64_MASK 0x8000
++#define SQ_MUBUF_0__ADDR64__SHIFT 0xf
++#define SQ_MUBUF_0__LDS_MASK 0x10000
++#define SQ_MUBUF_0__LDS__SHIFT 0x10
++#define SQ_MUBUF_0__OP_MASK 0x1fc0000
++#define SQ_MUBUF_0__OP__SHIFT 0x12
++#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
++#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP3_0__VDST_MASK 0xff
++#define SQ_VOP3_0__VDST__SHIFT 0x0
++#define SQ_VOP3_0__ABS_MASK 0x700
++#define SQ_VOP3_0__ABS__SHIFT 0x8
++#define SQ_VOP3_0__CLAMP_MASK 0x800
++#define SQ_VOP3_0__CLAMP__SHIFT 0xb
++#define SQ_VOP3_0__OP_MASK 0x3fe0000
++#define SQ_VOP3_0__OP__SHIFT 0x11
++#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
++#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP2__SRC0_MASK 0x1ff
++#define SQ_VOP2__SRC0__SHIFT 0x0
++#define SQ_VOP2__VSRC1_MASK 0x1fe00
++#define SQ_VOP2__VSRC1__SHIFT 0x9
++#define SQ_VOP2__VDST_MASK 0x1fe0000
++#define SQ_VOP2__VDST__SHIFT 0x11
++#define SQ_VOP2__OP_MASK 0x7e000000
++#define SQ_VOP2__OP__SHIFT 0x19
++#define SQ_VOP2__ENCODING_MASK 0x80000000
++#define SQ_VOP2__ENCODING__SHIFT 0x1f
++#define SQ_MTBUF_0__OFFSET_MASK 0xfff
++#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
++#define SQ_MTBUF_0__OFFEN_MASK 0x1000
++#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
++#define SQ_MTBUF_0__IDXEN_MASK 0x2000
++#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
++#define SQ_MTBUF_0__GLC_MASK 0x4000
++#define SQ_MTBUF_0__GLC__SHIFT 0xe
++#define SQ_MTBUF_0__ADDR64_MASK 0x8000
++#define SQ_MTBUF_0__ADDR64__SHIFT 0xf
++#define SQ_MTBUF_0__OP_MASK 0x70000
++#define SQ_MTBUF_0__OP__SHIFT 0x10
++#define SQ_MTBUF_0__DFMT_MASK 0x780000
++#define SQ_MTBUF_0__DFMT__SHIFT 0x13
++#define SQ_MTBUF_0__NFMT_MASK 0x3800000
++#define SQ_MTBUF_0__NFMT__SHIFT 0x17
++#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
++#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
++#define SQ_SOPP__SIMM16_MASK 0xffff
++#define SQ_SOPP__SIMM16__SHIFT 0x0
++#define SQ_SOPP__OP_MASK 0x7f0000
++#define SQ_SOPP__OP__SHIFT 0x10
++#define SQ_SOPP__ENCODING_MASK 0xff800000
++#define SQ_SOPP__ENCODING__SHIFT 0x17
++#define SQ_FLAT_0__GLC_MASK 0x10000
++#define SQ_FLAT_0__GLC__SHIFT 0x10
++#define SQ_FLAT_0__SLC_MASK 0x20000
++#define SQ_FLAT_0__SLC__SHIFT 0x11
++#define SQ_FLAT_0__OP_MASK 0x1fc0000
++#define SQ_FLAT_0__OP__SHIFT 0x12
++#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
++#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
++#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
++#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
++#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
++#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3fe0000
++#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x11
++#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
++#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
++#define SQ_MIMG_1__VADDR_MASK 0xff
++#define SQ_MIMG_1__VADDR__SHIFT 0x0
++#define SQ_MIMG_1__VDATA_MASK 0xff00
++#define SQ_MIMG_1__VDATA__SHIFT 0x8
++#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
++#define SQ_MIMG_1__SRSRC__SHIFT 0x10
++#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
++#define SQ_MIMG_1__SSAMP__SHIFT 0x15
++#define SQ_SMRD__OFFSET_MASK 0xff
++#define SQ_SMRD__OFFSET__SHIFT 0x0
++#define SQ_SMRD__IMM_MASK 0x100
++#define SQ_SMRD__IMM__SHIFT 0x8
++#define SQ_SMRD__SBASE_MASK 0x7e00
++#define SQ_SMRD__SBASE__SHIFT 0x9
++#define SQ_SMRD__SDST_MASK 0x3f8000
++#define SQ_SMRD__SDST__SHIFT 0xf
++#define SQ_SMRD__OP_MASK 0x7c00000
++#define SQ_SMRD__OP__SHIFT 0x16
++#define SQ_SMRD__ENCODING_MASK 0xf8000000
++#define SQ_SMRD__ENCODING__SHIFT 0x1b
++#define SQ_SOP1__SSRC0_MASK 0xff
++#define SQ_SOP1__SSRC0__SHIFT 0x0
++#define SQ_SOP1__OP_MASK 0xff00
++#define SQ_SOP1__OP__SHIFT 0x8
++#define SQ_SOP1__SDST_MASK 0x7f0000
++#define SQ_SOP1__SDST__SHIFT 0x10
++#define SQ_SOP1__ENCODING_MASK 0xff800000
++#define SQ_SOP1__ENCODING__SHIFT 0x17
++#define SQ_SOPC__SSRC0_MASK 0xff
++#define SQ_SOPC__SSRC0__SHIFT 0x0
++#define SQ_SOPC__SSRC1_MASK 0xff00
++#define SQ_SOPC__SSRC1__SHIFT 0x8
++#define SQ_SOPC__OP_MASK 0x7f0000
++#define SQ_SOPC__OP__SHIFT 0x10
++#define SQ_SOPC__ENCODING_MASK 0xff800000
++#define SQ_SOPC__ENCODING__SHIFT 0x17
++#define SQ_FLAT_1__ADDR_MASK 0xff
++#define SQ_FLAT_1__ADDR__SHIFT 0x0
++#define SQ_FLAT_1__DATA_MASK 0xff00
++#define SQ_FLAT_1__DATA__SHIFT 0x8
++#define SQ_FLAT_1__TFE_MASK 0x800000
++#define SQ_FLAT_1__TFE__SHIFT 0x17
++#define SQ_FLAT_1__VDST_MASK 0xff000000
++#define SQ_FLAT_1__VDST__SHIFT 0x18
++#define SQ_DS_1__ADDR_MASK 0xff
++#define SQ_DS_1__ADDR__SHIFT 0x0
++#define SQ_DS_1__DATA0_MASK 0xff00
++#define SQ_DS_1__DATA0__SHIFT 0x8
++#define SQ_DS_1__DATA1_MASK 0xff0000
++#define SQ_DS_1__DATA1__SHIFT 0x10
++#define SQ_DS_1__VDST_MASK 0xff000000
++#define SQ_DS_1__VDST__SHIFT 0x18
++#define SQ_VOP3_1__SRC0_MASK 0x1ff
++#define SQ_VOP3_1__SRC0__SHIFT 0x0
++#define SQ_VOP3_1__SRC1_MASK 0x3fe00
++#define SQ_VOP3_1__SRC1__SHIFT 0x9
++#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
++#define SQ_VOP3_1__SRC2__SHIFT 0x12
++#define SQ_VOP3_1__OMOD_MASK 0x18000000
++#define SQ_VOP3_1__OMOD__SHIFT 0x1b
++#define SQ_VOP3_1__NEG_MASK 0xe0000000
++#define SQ_VOP3_1__NEG__SHIFT 0x1d
++#define SQ_MIMG_0__DMASK_MASK 0xf00
++#define SQ_MIMG_0__DMASK__SHIFT 0x8
++#define SQ_MIMG_0__UNORM_MASK 0x1000
++#define SQ_MIMG_0__UNORM__SHIFT 0xc
++#define SQ_MIMG_0__GLC_MASK 0x2000
++#define SQ_MIMG_0__GLC__SHIFT 0xd
++#define SQ_MIMG_0__DA_MASK 0x4000
++#define SQ_MIMG_0__DA__SHIFT 0xe
++#define SQ_MIMG_0__R128_MASK 0x8000
++#define SQ_MIMG_0__R128__SHIFT 0xf
++#define SQ_MIMG_0__TFE_MASK 0x10000
++#define SQ_MIMG_0__TFE__SHIFT 0x10
++#define SQ_MIMG_0__LWE_MASK 0x20000
++#define SQ_MIMG_0__LWE__SHIFT 0x11
++#define SQ_MIMG_0__OP_MASK 0x1fc0000
++#define SQ_MIMG_0__OP__SHIFT 0x12
++#define SQ_MIMG_0__SLC_MASK 0x2000000
++#define SQ_MIMG_0__SLC__SHIFT 0x19
++#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
++#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
++#define SQ_SOPK__SIMM16_MASK 0xffff
++#define SQ_SOPK__SIMM16__SHIFT 0x0
++#define SQ_SOPK__SDST_MASK 0x7f0000
++#define SQ_SOPK__SDST__SHIFT 0x10
++#define SQ_SOPK__OP_MASK 0xf800000
++#define SQ_SOPK__OP__SHIFT 0x17
++#define SQ_SOPK__ENCODING_MASK 0xf0000000
++#define SQ_SOPK__ENCODING__SHIFT 0x1c
++#define SQ_DS_0__OFFSET0_MASK 0xff
++#define SQ_DS_0__OFFSET0__SHIFT 0x0
++#define SQ_DS_0__OFFSET1_MASK 0xff00
++#define SQ_DS_0__OFFSET1__SHIFT 0x8
++#define SQ_DS_0__GDS_MASK 0x20000
++#define SQ_DS_0__GDS__SHIFT 0x11
++#define SQ_DS_0__OP_MASK 0x3fc0000
++#define SQ_DS_0__OP__SHIFT 0x12
++#define SQ_DS_0__ENCODING_MASK 0xfc000000
++#define SQ_DS_0__ENCODING__SHIFT 0x1a
++#define SQ_VOPC__SRC0_MASK 0x1ff
++#define SQ_VOPC__SRC0__SHIFT 0x0
++#define SQ_VOPC__VSRC1_MASK 0x1fe00
++#define SQ_VOPC__VSRC1__SHIFT 0x9
++#define SQ_VOPC__OP_MASK 0x1fe0000
++#define SQ_VOPC__OP__SHIFT 0x11
++#define SQ_VOPC__ENCODING_MASK 0xfe000000
++#define SQ_VOPC__ENCODING__SHIFT 0x19
++#define SQ_VINTRP__VSRC_MASK 0xff
++#define SQ_VINTRP__VSRC__SHIFT 0x0
++#define SQ_VINTRP__ATTRCHAN_MASK 0x300
++#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
++#define SQ_VINTRP__ATTR_MASK 0xfc00
++#define SQ_VINTRP__ATTR__SHIFT 0xa
++#define SQ_VINTRP__OP_MASK 0x30000
++#define SQ_VINTRP__OP__SHIFT 0x10
++#define SQ_VINTRP__VDST_MASK 0x3fc0000
++#define SQ_VINTRP__VDST__SHIFT 0x12
++#define SQ_VINTRP__ENCODING_MASK 0xfc000000
++#define SQ_VINTRP__ENCODING__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
++#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
++#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
++#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
++#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
++#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
++#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
++#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
++#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
++#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
++#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
++#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
++#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
++#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
++#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
++#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
++#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
++#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
++#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
++#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
++#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
++#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
++#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
++#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
++#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
++#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
++#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
++#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
++#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
++#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
++#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
++#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
++#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
++#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
++#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
++#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
++#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
++#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
++#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
++#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
++#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
++#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
++#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
++#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
++#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
++#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
++#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
++#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
++#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
++#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
++#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
++#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
++#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
++#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
++#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
++#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
++#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
++#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
++#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
++#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
++#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
++#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
++#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
++#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
++#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
++#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
++#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
++#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
++#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
++#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
++#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
++#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
++#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_CTRL__CACHE_SIZE_MASK 0x3
++#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
++#define TCC_CTRL__RATE_MASK 0xc
++#define TCC_CTRL__RATE__SHIFT 0x2
++#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
++#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
++#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
++#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
++#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
++#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
++#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
++#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
++#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0xf
++#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x0
++#define TCC_EDC_COUNTER__DED_COUNT_MASK 0xf0000
++#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x10
++#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
++#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
++#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
++#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
++#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
++#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCS_CTRL__RATE_MASK 0x3
++#define TCS_CTRL__RATE__SHIFT 0x0
++#define TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
++#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
++#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
++#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
++#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
++#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
++#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
++#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
++#define TD_CNTL__PAD_STALL_EN_MASK 0x100
++#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
++#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
++#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
++#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
++#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
++#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
++#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
++#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
++#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
++#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
++#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
++#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
++#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
++#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
++#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
++#define TD_STATUS__BUSY_MASK 0x80000000
++#define TD_STATUS__BUSY__SHIFT 0x1f
++#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
++#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
++#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
++#define TD_DEBUG_DATA__DATA__SHIFT 0x0
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
++#define TD_SCRATCH__SCRATCH__SHIFT 0x0
++#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
++#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
++#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
++#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
++#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
++#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
++#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
++#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
++#define TA_CNTL_AUX__RESERVED_MASK 0xe
++#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
++#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
++#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
++#define TA_RESERVED_010C__Unused_MASK 0xffffffff
++#define TA_RESERVED_010C__Unused__SHIFT 0x0
++#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
++#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
++#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
++#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
++#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
++#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
++#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
++#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
++#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
++#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
++#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
++#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
++#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
++#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
++#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
++#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
++#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
++#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
++#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
++#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
++#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
++#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
++#define TA_STATUS__IN_BUSY_MASK 0x1000000
++#define TA_STATUS__IN_BUSY__SHIFT 0x18
++#define TA_STATUS__FG_BUSY_MASK 0x2000000
++#define TA_STATUS__FG_BUSY__SHIFT 0x19
++#define TA_STATUS__LA_BUSY_MASK 0x4000000
++#define TA_STATUS__LA_BUSY__SHIFT 0x1a
++#define TA_STATUS__FL_BUSY_MASK 0x8000000
++#define TA_STATUS__FL_BUSY__SHIFT 0x1b
++#define TA_STATUS__TA_BUSY_MASK 0x10000000
++#define TA_STATUS__TA_BUSY__SHIFT 0x1c
++#define TA_STATUS__FA_BUSY_MASK 0x20000000
++#define TA_STATUS__FA_BUSY__SHIFT 0x1d
++#define TA_STATUS__AL_BUSY_MASK 0x40000000
++#define TA_STATUS__AL_BUSY__SHIFT 0x1e
++#define TA_STATUS__BUSY_MASK 0x80000000
++#define TA_STATUS__BUSY__SHIFT 0x1f
++#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
++#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
++#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
++#define TA_DEBUG_DATA__DATA__SHIFT 0x0
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
++#define TA_SCRATCH__SCRATCH__SHIFT 0x0
++#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
++#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
++#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
++#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
++#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
++#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
++#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
++#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
++#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
++#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
++#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
++#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
++#define TCP_INVALIDATE__START_MASK 0x1
++#define TCP_INVALIDATE__START__SHIFT 0x0
++#define TCP_STATUS__TCP_BUSY_MASK 0x1
++#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
++#define TCP_CNTL__FORCE_HIT_MASK 0x1
++#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
++#define TCP_CNTL__FORCE_MISS_MASK 0x2
++#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
++#define TCP_CNTL__L1_SIZE_MASK 0xc
++#define TCP_CNTL__L1_SIZE__SHIFT 0x2
++#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
++#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
++#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
++#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
++#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
++#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
++#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
++#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
++#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
++#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
++#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
++#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
++#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
++#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
++#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
++#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
++#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
++#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
++#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
++#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
++#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
++#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
++#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
++#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
++#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
++#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
++#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
++#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
++#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
++#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
++#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
++#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
++#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
++#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
++#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
++#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
++#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
++#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
++#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
++#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
++#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
++#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
++#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
++#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
++#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
++#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
++#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
++#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
++#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
++#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
++#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
++#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
++#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
++#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
++#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
++#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
++#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
++#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
++#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0xf
++#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x0
++#define TCP_EDC_COUNTER__DED_COUNT_MASK 0xf0000
++#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x10
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
++#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
++#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
++#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
++#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
++#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
++#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
++#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
++#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
++#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
++#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
++#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
++#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
++#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
++#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
++#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
++#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
++#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
++#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
++#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
++#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
++#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
++#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
++#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
++#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
++#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
++#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
++#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
++#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
++#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
++#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
++#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
++#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
++#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
++#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
++#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
++#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
++#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
++#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
++#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
++#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
++#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
++#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
++#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
++#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
++#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
++#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
++#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
++#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
++#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
++#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
++#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
++#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
++#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
++#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
++#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
++#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
++#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
++#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
++#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
++#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
++#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
++#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
++#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
++#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
++#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
++#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
++#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
++#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
++#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
++#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
++#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
++#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
++#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
++#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
++#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
++#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
++#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
++#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
++#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
++#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
++#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
++#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
++#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
++#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
++#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
++#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
++#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
++#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
++#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
++#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
++#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
++#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
++#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
++#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
++#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
++#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
++#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
++#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
++#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
++#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
++#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
++#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
++#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
++#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
++#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
++#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
++#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
++#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
++#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCI_STATUS__TCI_BUSY_MASK 0x1
++#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
++#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
++#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
++#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
++#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
++#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
++#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
++#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
++#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
++#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
++#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
++#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
++#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
++#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
++#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
++#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
++#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
++#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
++#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
++#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
++#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
++#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
++#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
++#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
++#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
++#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
++#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
++#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
++#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
++#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
++#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
++#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
++#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
++#define GDS_ENHANCE2__MISC_MASK 0xffff
++#define GDS_ENHANCE2__MISC__SHIFT 0x0
++#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
++#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
++#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
++#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
++#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
++#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
++#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
++#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
++#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
++#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
++#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
++#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
++#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
++#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
++#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
++#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
++#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
++#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
++#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
++#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
++#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
++#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
++#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
++#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
++#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
++#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
++#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
++#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
++#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
++#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
++#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
++#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
++#define GDS_SECDED_CNT__DED_MASK 0xffff
++#define GDS_SECDED_CNT__DED__SHIFT 0x0
++#define GDS_SECDED_CNT__SEC_MASK 0xffff0000
++#define GDS_SECDED_CNT__SEC__SHIFT 0x10
++#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff
++#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x0
++#define GDS_GRBM_SECDED_CNT__SEC_MASK 0xffff0000
++#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x10
++#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
++#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
++#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
++#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
++#define GDS_OA_DED__ME0_CS_DED_MASK 0x4
++#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x2
++#define GDS_OA_DED__UNUSED0_MASK 0x8
++#define GDS_OA_DED__UNUSED0__SHIFT 0x3
++#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x10
++#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
++#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x20
++#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
++#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x40
++#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
++#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x80
++#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
++#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x100
++#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
++#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x200
++#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
++#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x400
++#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
++#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x800
++#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
++#define GDS_OA_DED__UNUSED1_MASK 0xfffff000
++#define GDS_OA_DED__UNUSED1__SHIFT 0xc
++#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
++#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
++#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
++#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
++#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
++#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
++#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
++#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
++#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
++#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
++#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
++#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
++#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
++#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
++#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
++#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
++#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
++#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
++#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
++#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
++#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
++#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
++#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
++#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
++#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
++#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
++#define GDS_ATOM_CNTL__AINC_MASK 0x3f
++#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
++#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
++#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
++#define GDS_ATOM_CNTL__DMODE_MASK 0x100
++#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
++#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00
++#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x9
++#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
++#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
++#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
++#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
++#define GDS_ATOM_BASE__BASE_MASK 0xffff
++#define GDS_ATOM_BASE__BASE__SHIFT 0x0
++#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
++#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
++#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
++#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
++#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
++#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
++#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
++#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
++#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
++#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
++#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
++#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
++#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
++#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
++#define GDS_ATOM_DST__DST_MASK 0xffffffff
++#define GDS_ATOM_DST__DST__SHIFT 0x0
++#define GDS_ATOM_OP__OP_MASK 0xff
++#define GDS_ATOM_OP__OP__SHIFT 0x0
++#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
++#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
++#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
++#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
++#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
++#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
++#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ0__DATA__SHIFT 0x0
++#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
++#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ1__DATA__SHIFT 0x0
++#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
++#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
++#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
++#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
++#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
++#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
++#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
++#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
++#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
++#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
++#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
++#define GDS_GWS_RESOURCE__DED_MASK 0x4000
++#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
++#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
++#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
++#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
++#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
++#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
++#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
++#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
++#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
++#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
++#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
++#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
++#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
++#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
++#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
++#define GDS_OA_CNTL__INDEX_MASK 0xf
++#define GDS_OA_CNTL__INDEX__SHIFT 0x0
++#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
++#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
++#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
++#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
++#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
++#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
++#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0xf0000
++#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10
++#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf00000
++#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14
++#define GDS_OA_ADDRESS__UNUSED_MASK 0x3f000000
++#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18
++#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
++#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
++#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
++#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
++#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
++#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
++#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
++#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
++#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
++#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
++#define GDS_DEBUG_REG0__spare1_MASK 0x3f
++#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
++#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
++#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
++#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
++#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
++#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
++#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
++#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
++#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
++#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
++#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
++#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
++#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
++#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
++#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
++#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
++#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
++#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
++#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
++#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
++#define GDS_DEBUG_REG0__spare__SHIFT 0x16
++#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
++#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
++#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
++#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
++#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
++#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
++#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
++#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
++#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
++#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
++#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
++#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
++#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
++#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
++#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
++#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
++#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
++#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
++#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
++#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
++#define GDS_DEBUG_REG1__spare_MASK 0xff000000
++#define GDS_DEBUG_REG1__spare__SHIFT 0x18
++#define GDS_DEBUG_REG2__ds_full_MASK 0x1
++#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
++#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
++#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
++#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
++#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
++#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
++#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
++#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
++#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
++#define GDS_DEBUG_REG2__req_MASK 0x7fff00
++#define GDS_DEBUG_REG2__req__SHIFT 0x8
++#define GDS_DEBUG_REG2__spare_MASK 0xff800000
++#define GDS_DEBUG_REG2__spare__SHIFT 0x17
++#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
++#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
++#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
++#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
++#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
++#define GDS_DEBUG_REG3__spare__SHIFT 0xf
++#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
++#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
++#define GDS_DEBUG_REG4__gws_req_MASK 0x2
++#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
++#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
++#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
++#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
++#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
++#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
++#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
++#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
++#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
++#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
++#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
++#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
++#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
++#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
++#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
++#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
++#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
++#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
++#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
++#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
++#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
++#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
++#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
++#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
++#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
++#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
++#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
++#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
++#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
++#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
++#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
++#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
++#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
++#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
++#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
++#define GDS_DEBUG_REG4__spare_MASK 0xff000000
++#define GDS_DEBUG_REG4__spare__SHIFT 0x18
++#define GDS_DEBUG_REG5__write_dis_MASK 0x1
++#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
++#define GDS_DEBUG_REG5__dec_error_MASK 0x2
++#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
++#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
++#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
++#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
++#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
++#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
++#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
++#define GDS_DEBUG_REG5__spare_MASK 0xe0
++#define GDS_DEBUG_REG5__spare__SHIFT 0x5
++#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
++#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
++#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
++#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
++#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
++#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
++#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
++#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
++#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
++#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
++#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
++#define GDS_DEBUG_REG6__spare__SHIFT 0x15
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
++#define GDS_VMID0_BASE__BASE_MASK 0xffff
++#define GDS_VMID0_BASE__BASE__SHIFT 0x0
++#define GDS_VMID1_BASE__BASE_MASK 0xffff
++#define GDS_VMID1_BASE__BASE__SHIFT 0x0
++#define GDS_VMID2_BASE__BASE_MASK 0xffff
++#define GDS_VMID2_BASE__BASE__SHIFT 0x0
++#define GDS_VMID3_BASE__BASE_MASK 0xffff
++#define GDS_VMID3_BASE__BASE__SHIFT 0x0
++#define GDS_VMID4_BASE__BASE_MASK 0xffff
++#define GDS_VMID4_BASE__BASE__SHIFT 0x0
++#define GDS_VMID5_BASE__BASE_MASK 0xffff
++#define GDS_VMID5_BASE__BASE__SHIFT 0x0
++#define GDS_VMID6_BASE__BASE_MASK 0xffff
++#define GDS_VMID6_BASE__BASE__SHIFT 0x0
++#define GDS_VMID7_BASE__BASE_MASK 0xffff
++#define GDS_VMID7_BASE__BASE__SHIFT 0x0
++#define GDS_VMID8_BASE__BASE_MASK 0xffff
++#define GDS_VMID8_BASE__BASE__SHIFT 0x0
++#define GDS_VMID9_BASE__BASE_MASK 0xffff
++#define GDS_VMID9_BASE__BASE__SHIFT 0x0
++#define GDS_VMID10_BASE__BASE_MASK 0xffff
++#define GDS_VMID10_BASE__BASE__SHIFT 0x0
++#define GDS_VMID11_BASE__BASE_MASK 0xffff
++#define GDS_VMID11_BASE__BASE__SHIFT 0x0
++#define GDS_VMID12_BASE__BASE_MASK 0xffff
++#define GDS_VMID12_BASE__BASE__SHIFT 0x0
++#define GDS_VMID13_BASE__BASE_MASK 0xffff
++#define GDS_VMID13_BASE__BASE__SHIFT 0x0
++#define GDS_VMID14_BASE__BASE_MASK 0xffff
++#define GDS_VMID14_BASE__BASE__SHIFT 0x0
++#define GDS_VMID15_BASE__BASE_MASK 0xffff
++#define GDS_VMID15_BASE__BASE__SHIFT 0x0
++#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
++#define GDS_GWS_VMID0__BASE_MASK 0x3f
++#define GDS_GWS_VMID0__BASE__SHIFT 0x0
++#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID1__BASE_MASK 0x3f
++#define GDS_GWS_VMID1__BASE__SHIFT 0x0
++#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID2__BASE_MASK 0x3f
++#define GDS_GWS_VMID2__BASE__SHIFT 0x0
++#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID3__BASE_MASK 0x3f
++#define GDS_GWS_VMID3__BASE__SHIFT 0x0
++#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID4__BASE_MASK 0x3f
++#define GDS_GWS_VMID4__BASE__SHIFT 0x0
++#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID5__BASE_MASK 0x3f
++#define GDS_GWS_VMID5__BASE__SHIFT 0x0
++#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID6__BASE_MASK 0x3f
++#define GDS_GWS_VMID6__BASE__SHIFT 0x0
++#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID7__BASE_MASK 0x3f
++#define GDS_GWS_VMID7__BASE__SHIFT 0x0
++#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID8__BASE_MASK 0x3f
++#define GDS_GWS_VMID8__BASE__SHIFT 0x0
++#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID9__BASE_MASK 0x3f
++#define GDS_GWS_VMID9__BASE__SHIFT 0x0
++#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID10__BASE_MASK 0x3f
++#define GDS_GWS_VMID10__BASE__SHIFT 0x0
++#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID11__BASE_MASK 0x3f
++#define GDS_GWS_VMID11__BASE__SHIFT 0x0
++#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID12__BASE_MASK 0x3f
++#define GDS_GWS_VMID12__BASE__SHIFT 0x0
++#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID13__BASE_MASK 0x3f
++#define GDS_GWS_VMID13__BASE__SHIFT 0x0
++#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID14__BASE_MASK 0x3f
++#define GDS_GWS_VMID14__BASE__SHIFT 0x0
++#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID15__BASE_MASK 0x3f
++#define GDS_GWS_VMID15__BASE__SHIFT 0x0
++#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
++#define GDS_OA_VMID0__MASK_MASK 0xffff
++#define GDS_OA_VMID0__MASK__SHIFT 0x0
++#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID1__MASK_MASK 0xffff
++#define GDS_OA_VMID1__MASK__SHIFT 0x0
++#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID2__MASK_MASK 0xffff
++#define GDS_OA_VMID2__MASK__SHIFT 0x0
++#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID3__MASK_MASK 0xffff
++#define GDS_OA_VMID3__MASK__SHIFT 0x0
++#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID4__MASK_MASK 0xffff
++#define GDS_OA_VMID4__MASK__SHIFT 0x0
++#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID5__MASK_MASK 0xffff
++#define GDS_OA_VMID5__MASK__SHIFT 0x0
++#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID6__MASK_MASK 0xffff
++#define GDS_OA_VMID6__MASK__SHIFT 0x0
++#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID7__MASK_MASK 0xffff
++#define GDS_OA_VMID7__MASK__SHIFT 0x0
++#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID8__MASK_MASK 0xffff
++#define GDS_OA_VMID8__MASK__SHIFT 0x0
++#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID9__MASK_MASK 0xffff
++#define GDS_OA_VMID9__MASK__SHIFT 0x0
++#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID10__MASK_MASK 0xffff
++#define GDS_OA_VMID10__MASK__SHIFT 0x0
++#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID11__MASK_MASK 0xffff
++#define GDS_OA_VMID11__MASK__SHIFT 0x0
++#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID12__MASK_MASK 0xffff
++#define GDS_OA_VMID12__MASK__SHIFT 0x0
++#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID13__MASK_MASK 0xffff
++#define GDS_OA_VMID13__MASK__SHIFT 0x0
++#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID14__MASK_MASK 0xffff
++#define GDS_OA_VMID14__MASK__SHIFT 0x0
++#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID15__MASK_MASK 0xffff
++#define GDS_OA_VMID15__MASK__SHIFT 0x0
++#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
++#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
++#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
++#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
++#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
++#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
++#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
++#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
++#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
++#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
++#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
++#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
++#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
++#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
++#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
++#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
++#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
++#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
++#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
++#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
++#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
++#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
++#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
++#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
++#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
++#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
++#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
++#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
++#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
++#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
++#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
++#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
++#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
++#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
++#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
++#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
++#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
++#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
++#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
++#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
++#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
++#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
++#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
++#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
++#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
++#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
++#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
++#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
++#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
++#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
++#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
++#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
++#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
++#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
++#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
++#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
++#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
++#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
++#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
++#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
++#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
++#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
++#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
++#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
++#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
++#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
++#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
++#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
++#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
++#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
++#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
++#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
++#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
++#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
++#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
++#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
++#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
++#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
++#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
++#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
++#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
++#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
++#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
++#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
++#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
++#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
++#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
++#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
++#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
++#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
++#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
++#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
++#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
++#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
++#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
++#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
++#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
++#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
++#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
++#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
++#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
++#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
++#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
++#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
++#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
++#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
++#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
++#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
++#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
++#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
++#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
++#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
++#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
++#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
++#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
++#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
++#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
++#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
++#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
++#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
++#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
++#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
++#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
++#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
++#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
++#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
++#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
++#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
++#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
++#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
++#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
++#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
++#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
++#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
++#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
++#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
++#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
++#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
++#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
++#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
++#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
++#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
++#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
++#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
++#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
++#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
++#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
++#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
++#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
++#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
++#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
++#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
++#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
++#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
++#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
++#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
++#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
++#define GDS_OA_RESET__RESET_MASK 0x1
++#define GDS_OA_RESET__RESET__SHIFT 0x0
++#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
++#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
++#define GDS_ENHANCE__MISC_MASK 0xffff
++#define GDS_ENHANCE__MISC__SHIFT 0x0
++#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
++#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
++#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
++#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
++#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
++#define GDS_ENHANCE__UNUSED__SHIFT 0x12
++#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
++#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
++#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
++#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
++#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
++#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
++#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xffff0000
++#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x10
++#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
++#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
++#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
++#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
++#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
++#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
++#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
++#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
++#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
++#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
++#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
++#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
++#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
++#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
++#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
++#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
++#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
++#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
++#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
++#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
++#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
++#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
++#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
++#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
++#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
++#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
++#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
++#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
++#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
++#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
++#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
++#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
++#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0xc0
++#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
++#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x100
++#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8
++#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
++#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
++#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
++#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
++#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
++#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
++#define IA_ENHANCE__MISC_MASK 0xffffffff
++#define IA_ENHANCE__MISC__SHIFT 0x0
++#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
++#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
++#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
++#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
++#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
++#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
++#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
++#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
++#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
++#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
++#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
++#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
++#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
++#define VGT_IMMED_DATA__DATA__SHIFT 0x0
++#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
++#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
++#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
++#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
++#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
++#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
++#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
++#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
++#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
++#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
++#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
++#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
++#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
++#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
++#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
++#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
++#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
++#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
++#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
++#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
++#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
++#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
++#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
++#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
++#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
++#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
++#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
++#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
++#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
++#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
++#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
++#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
++#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
++#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
++#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
++#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
++#define VGT_ENHANCE__MISC_MASK 0xffffffff
++#define VGT_ENHANCE__MISC__SHIFT 0x0
++#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
++#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
++#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
++#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
++#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
++#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
++#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
++#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
++#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
++#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
++#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
++#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
++#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
++#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
++#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
++#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
++#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
++#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
++#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
++#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
++#define VGT_GROUP_DECR__DECR_MASK 0xf
++#define VGT_GROUP_DECR__DECR__SHIFT 0x0
++#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
++#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
++#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
++#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
++#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
++#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
++#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
++#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
++#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
++#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
++#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
++#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
++#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
++#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
++#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
++#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
++#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
++#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
++#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
++#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
++#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
++#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
++#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
++#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
++#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
++#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
++#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
++#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
++#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
++#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
++#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
++#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
++#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
++#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
++#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
++#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
++#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6
++#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1
++#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
++#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
++#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10
++#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4
++#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
++#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
++#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6
++#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1
++#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
++#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
++#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10
++#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4
++#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
++#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
++#define VGT_GS_MODE__MODE_MASK 0x7
++#define VGT_GS_MODE__MODE__SHIFT 0x0
++#define VGT_GS_MODE__RESERVED_0_MASK 0x8
++#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
++#define VGT_GS_MODE__CUT_MODE_MASK 0x30
++#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
++#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
++#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
++#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
++#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
++#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
++#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
++#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
++#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
++#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x4000
++#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe
++#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x8000
++#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf
++#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x10000
++#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10
++#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
++#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
++#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
++#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
++#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
++#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
++#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
++#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
++#define VGT_GS_MODE__ONCHIP_MASK 0x600000
++#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
++#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
++#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
++#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
++#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
++#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
++#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
++#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
++#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
++#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
++#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
++#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
++#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
++#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
++#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
++#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
++#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
++#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
++#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
++#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
++#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
++#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
++#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
++#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
++#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
++#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
++#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
++#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
++#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
++#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
++#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
++#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
++#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
++#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
++#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
++#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
++#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
++#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
++#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
++#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
++#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
++#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
++#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
++#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
++#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
++#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x400000
++#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16
++#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
++#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
++#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
++#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
++#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
++#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
++#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
++#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
++#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
++#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
++#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
++#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
++#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
++#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
++#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
++#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
++#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
++#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
++#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
++#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
++#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
++#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
++#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
++#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
++#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
++#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
++#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
++#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
++#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
++#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
++#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
++#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
++#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
++#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
++#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
++#define IA_VMID_OVERRIDE__ENABLE_MASK 0x1
++#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x0
++#define IA_VMID_OVERRIDE__VMID_MASK 0x1e
++#define IA_VMID_OVERRIDE__VMID__SHIFT 0x1
++#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
++#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
++#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
++#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
++#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
++#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
++#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
++#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
++#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
++#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
++#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
++#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
++#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
++#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
++#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
++#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
++#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
++#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
++#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
++#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
++#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
++#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
++#define VGT_TF_PARAM__TYPE_MASK 0x3
++#define VGT_TF_PARAM__TYPE__SHIFT 0x0
++#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
++#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
++#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
++#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
++#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
++#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
++#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
++#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
++#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
++#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
++#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
++#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
++#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x18000
++#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
++#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
++#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
++#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
++#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
++#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
++#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
++#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
++#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
++#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
++#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
++#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
++#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
++#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
++#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
++#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
++#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
++#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
++#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
++#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
++#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
++#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
++#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
++#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
++#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
++#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
++#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
++#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
++#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
++#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
++#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
++#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
++#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
++#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
++#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
++#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
++#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
++#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
++#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
++#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
++#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
++#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
++#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
++#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
++#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
++#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
++#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
++#define WD_ENHANCE__MISC_MASK 0xffffffff
++#define WD_ENHANCE__MISC__SHIFT 0x0
++#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
++#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
++#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
++#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
++#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
++#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
++#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
++#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
++#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
++#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
++#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
++#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
++#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
++#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
++#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
++#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
++#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
++#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
++#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
++#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
++#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
++#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
++#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
++#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
++#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
++#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
++#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
++#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
++#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
++#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
++#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
++#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
++#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
++#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
++#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
++#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
++#define IA_DEBUG_DATA__DATA__SHIFT 0x0
++#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
++#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
++#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
++#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
++#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
++#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
++#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
++#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
++#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
++#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
++#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
++#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
++#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
++#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
++#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
++#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
++#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
++#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
++#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
++#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
++#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
++#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
++#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
++#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
++#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
++#define WD_DEBUG_DATA__DATA__SHIFT 0x0
++#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
++#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
++#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
++#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
++#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
++#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
++#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
++#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
++#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
++#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
++#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
++#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
++#define WD_DEBUG_REG0__wd_busy_MASK 0x4
++#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
++#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
++#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
++#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
++#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
++#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
++#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
++#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
++#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
++#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
++#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
++#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
++#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
++#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
++#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
++#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
++#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
++#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
++#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
++#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
++#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
++#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
++#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
++#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
++#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
++#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
++#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
++#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
++#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
++#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
++#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
++#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
++#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
++#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
++#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
++#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
++#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
++#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
++#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
++#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
++#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
++#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
++#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
++#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
++#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
++#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
++#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
++#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
++#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
++#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
++#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
++#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
++#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
++#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
++#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
++#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
++#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
++#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
++#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
++#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
++#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
++#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
++#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
++#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
++#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
++#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
++#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
++#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
++#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
++#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
++#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
++#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
++#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
++#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
++#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
++#define WD_DEBUG_REG1__SPARE0_MASK 0x100
++#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
++#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
++#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
++#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
++#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
++#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
++#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
++#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
++#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
++#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
++#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
++#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
++#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
++#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
++#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
++#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
++#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
++#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
++#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
++#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
++#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
++#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
++#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
++#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
++#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
++#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
++#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
++#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
++#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
++#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
++#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
++#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
++#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
++#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
++#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
++#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
++#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
++#define WD_DEBUG_REG2__SPARE0_MASK 0x100
++#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
++#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
++#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
++#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
++#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
++#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
++#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
++#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
++#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
++#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
++#define WD_DEBUG_REG3__SPARE0_MASK 0x2
++#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
++#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
++#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
++#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
++#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
++#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
++#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
++#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
++#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
++#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
++#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
++#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
++#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
++#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
++#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
++#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
++#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
++#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
++#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
++#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
++#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
++#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
++#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
++#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
++#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
++#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
++#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
++#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
++#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
++#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
++#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
++#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
++#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
++#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
++#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
++#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
++#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
++#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
++#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
++#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
++#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
++#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
++#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
++#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
++#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
++#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
++#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
++#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
++#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
++#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
++#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
++#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
++#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
++#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
++#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
++#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
++#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
++#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
++#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
++#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
++#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
++#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
++#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
++#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
++#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
++#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
++#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
++#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
++#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
++#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
++#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
++#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
++#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
++#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
++#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
++#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
++#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
++#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
++#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
++#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
++#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
++#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
++#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
++#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
++#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
++#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
++#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
++#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
++#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
++#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
++#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
++#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
++#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
++#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
++#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
++#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
++#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
++#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
++#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
++#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
++#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
++#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
++#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
++#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
++#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
++#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
++#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
++#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
++#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
++#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
++#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
++#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
++#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
++#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
++#define WD_DEBUG_REG5__SPARE0_MASK 0x2
++#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
++#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
++#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
++#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
++#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
++#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
++#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
++#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
++#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
++#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
++#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
++#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
++#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
++#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
++#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
++#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
++#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
++#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
++#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
++#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
++#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
++#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
++#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
++#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
++#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
++#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
++#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
++#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
++#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
++#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
++#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
++#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
++#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
++#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
++#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
++#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
++#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
++#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
++#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
++#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
++#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
++#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
++#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
++#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
++#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
++#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
++#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
++#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
++#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
++#define IA_DEBUG_REG0__ia_busy_MASK 0x4
++#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
++#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
++#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
++#define IA_DEBUG_REG0__SPARE0_MASK 0x10
++#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
++#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
++#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
++#define IA_DEBUG_REG0__dma_busy_MASK 0x40
++#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
++#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
++#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
++#define IA_DEBUG_REG0__grp_busy_MASK 0x100
++#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
++#define IA_DEBUG_REG0__SPARE1_MASK 0x200
++#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
++#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
++#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
++#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
++#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
++#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
++#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
++#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
++#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
++#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
++#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
++#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
++#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
++#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
++#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
++#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
++#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
++#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
++#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
++#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
++#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
++#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
++#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
++#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
++#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
++#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
++#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
++#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
++#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
++#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
++#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
++#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
++#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
++#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
++#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
++#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
++#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
++#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
++#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
++#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
++#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
++#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
++#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
++#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
++#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
++#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
++#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
++#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
++#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
++#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
++#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
++#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
++#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
++#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
++#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
++#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
++#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
++#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
++#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
++#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
++#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
++#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
++#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
++#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
++#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
++#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
++#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
++#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
++#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
++#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
++#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
++#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
++#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
++#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
++#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
++#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
++#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
++#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
++#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
++#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
++#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
++#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
++#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
++#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
++#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
++#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
++#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
++#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
++#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
++#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
++#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
++#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
++#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
++#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
++#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
++#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
++#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
++#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
++#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
++#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
++#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
++#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
++#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
++#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
++#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
++#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
++#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
++#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
++#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
++#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
++#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
++#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
++#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
++#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
++#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
++#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
++#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
++#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
++#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
++#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
++#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
++#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
++#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
++#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
++#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
++#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
++#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
++#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
++#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
++#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
++#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
++#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
++#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
++#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
++#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
++#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
++#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
++#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
++#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
++#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
++#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
++#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
++#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
++#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
++#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
++#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
++#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
++#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
++#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
++#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
++#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
++#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
++#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
++#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
++#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
++#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
++#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
++#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
++#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
++#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
++#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
++#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
++#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
++#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
++#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
++#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
++#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
++#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
++#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
++#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
++#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
++#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
++#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
++#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
++#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
++#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
++#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
++#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
++#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
++#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
++#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
++#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
++#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
++#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
++#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
++#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
++#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
++#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
++#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
++#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
++#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
++#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
++#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
++#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
++#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
++#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
++#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
++#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
++#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
++#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
++#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
++#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
++#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
++#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
++#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
++#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
++#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
++#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
++#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
++#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
++#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
++#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
++#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
++#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
++#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
++#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
++#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
++#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
++#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
++#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
++#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
++#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
++#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
++#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
++#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
++#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
++#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
++#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
++#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
++#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
++#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
++#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
++#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
++#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
++#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
++#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
++#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
++#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
++#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
++#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
++#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
++#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
++#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
++#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
++#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
++#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
++#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
++#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
++#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
++#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
++#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
++#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
++#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
++#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
++#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
++#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
++#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
++#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
++#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
++#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
++#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
++#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
++#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
++#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
++#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
++#define IA_DEBUG_REG6__extract_group_MASK 0x800000
++#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
++#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
++#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
++#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
++#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
++#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
++#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
++#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
++#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
++#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
++#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
++#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
++#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
++#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
++#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
++#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
++#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
++#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
++#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
++#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
++#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
++#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
++#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
++#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
++#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
++#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
++#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
++#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
++#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
++#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
++#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
++#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
++#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
++#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
++#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
++#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
++#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
++#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
++#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
++#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
++#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
++#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
++#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
++#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
++#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
++#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
++#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
++#define IA_DEBUG_REG8__grp_continued_MASK 0x800
++#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
++#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
++#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
++#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
++#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
++#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
++#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
++#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
++#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
++#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
++#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
++#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
++#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
++#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
++#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
++#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
++#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
++#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
++#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
++#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
++#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
++#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
++#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
++#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
++#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
++#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
++#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
++#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
++#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
++#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
++#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
++#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
++#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
++#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
++#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
++#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
++#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
++#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
++#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
++#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
++#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
++#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
++#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
++#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
++#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
++#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
++#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
++#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
++#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
++#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
++#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
++#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
++#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
++#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
++#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
++#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
++#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
++#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
++#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
++#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
++#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
++#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
++#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
++#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
++#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
++#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
++#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
++#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
++#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
++#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
++#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
++#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
++#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
++#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
++#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
++#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
++#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
++#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
++#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
++#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
++#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
++#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
++#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
++#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
++#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
++#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
++#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
++#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
++#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
++#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
++#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
++#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
++#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
++#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
++#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
++#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
++#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
++#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
++#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
++#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
++#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
++#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
++#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
++#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
++#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
++#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
++#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
++#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
++#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
++#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
++#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
++#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
++#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
++#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
++#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
++#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
++#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
++#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
++#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
++#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
++#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
++#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
++#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
++#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
++#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
++#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
++#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
++#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
++#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
++#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
++#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
++#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
++#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
++#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
++#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
++#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
++#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
++#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
++#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
++#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
++#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
++#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
++#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
++#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
++#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
++#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
++#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
++#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
++#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
++#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
++#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
++#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
++#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
++#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
++#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
++#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
++#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
++#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
++#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
++#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
++#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
++#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
++#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
++#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
++#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
++#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
++#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
++#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
++#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
++#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
++#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
++#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
++#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
++#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
++#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
++#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
++#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
++#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
++#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
++#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
++#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
++#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
++#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
++#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
++#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
++#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
++#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
++#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
++#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
++#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
++#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
++#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
++#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
++#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
++#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
++#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
++#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
++#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
++#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
++#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
++#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
++#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
++#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
++#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
++#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
++#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
++#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
++#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
++#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
++#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
++#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
++#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
++#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
++#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
++#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
++#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
++#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
++#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
++#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
++#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
++#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
++#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
++#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
++#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
++#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
++#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
++#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
++#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
++#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
++#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
++#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
++#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
++#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
++#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
++#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
++#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
++#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
++#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
++#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
++#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
++#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
++#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
++#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
++#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
++#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
++#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
++#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
++#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
++#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
++#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
++#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
++#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
++#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
++#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
++#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
++#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
++#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
++#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
++#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
++#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
++#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
++#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
++#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
++#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
++#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
++#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
++#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
++#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
++#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
++#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
++#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
++#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
++#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
++#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
++#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
++#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
++#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
++#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
++#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
++#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
++#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
++#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
++#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
++#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
++#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
++#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
++#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
++#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
++#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
++#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
++#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
++#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
++#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
++#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
++#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
++#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
++#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
++#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
++#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
++#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
++#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
++#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
++#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
++#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
++#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
++#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
++#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
++#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
++#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
++#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
++#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
++#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
++#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
++#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
++#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
++#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
++#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
++#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
++#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
++#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
++#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
++#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
++#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
++#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
++#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
++#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
++#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
++#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
++#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
++#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
++#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
++#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
++#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
++#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
++#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
++#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
++#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
++#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
++#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
++#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
++#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
++#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
++#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
++#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
++#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
++#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
++#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
++#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
++#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
++#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
++#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
++#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
++#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
++#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
++#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
++#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
++#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
++#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
++#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
++#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
++#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
++#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
++#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
++#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
++#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
++#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
++#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
++#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
++#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
++#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
++#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
++#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
++#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
++#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
++#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
++#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
++#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
++#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
++#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
++#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
++#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
++#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
++#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
++#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
++#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
++#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
++#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
++#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
++#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
++#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
++#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
++#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
++#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
++#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
++#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
++#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
++#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
++#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
++#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
++#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
++#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
++#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
++#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
++#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
++#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
++#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
++#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
++#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
++#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
++#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
++#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
++#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
++#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
++#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
++#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
++#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
++#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
++#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
++#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
++#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
++#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
++#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
++#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
++#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
++#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
++#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
++#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
++#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
++#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
++#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
++#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
++#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
++#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
++#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
++#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
++#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
++#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
++#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
++#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
++#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
++#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
++#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
++#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
++#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
++#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
++#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
++#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
++#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
++#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
++#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
++#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
++#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
++#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
++#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
++#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
++#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
++#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
++#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
++#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
++#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
++#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
++#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
++#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
++#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
++#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
++#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
++#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
++#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
++#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
++#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
++#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
++#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
++#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
++#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
++#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
++#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
++#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
++#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
++#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
++#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
++#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
++#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
++#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
++#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
++#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
++#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
++#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
++#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
++#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
++#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
++#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
++#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
++#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
++#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
++#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
++#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
++#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
++#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
++#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
++#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
++#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
++#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
++#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
++#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
++#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
++#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
++#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
++#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
++#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
++#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
++#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
++#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
++#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
++#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
++#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
++#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
++#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
++#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
++#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
++#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
++#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
++#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
++#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
++#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
++#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
++#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
++#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
++#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
++#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
++#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
++#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
++#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
++#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
++#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
++#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
++#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
++#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
++#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
++#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
++#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
++#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
++#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
++#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
++#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
++#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
++#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
++#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
++#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
++#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
++#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
++#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
++#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
++#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
++#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
++#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
++#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
++#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
++#define VGT_DEBUG_REG15__counters_full_MASK 0x10
++#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
++#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
++#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
++#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
++#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
++#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
++#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
++#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
++#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
++#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
++#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
++#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
++#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
++#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
++#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
++#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
++#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
++#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
++#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
++#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
++#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
++#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
++#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
++#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
++#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
++#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
++#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
++#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
++#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
++#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
++#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
++#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
++#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
++#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
++#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
++#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
++#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
++#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
++#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
++#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
++#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
++#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
++#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
++#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
++#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
++#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
++#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
++#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
++#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
++#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
++#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
++#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
++#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
++#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
++#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
++#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
++#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
++#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
++#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
++#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
++#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
++#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
++#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
++#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
++#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
++#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
++#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
++#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
++#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
++#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
++#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
++#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
++#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
++#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
++#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
++#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
++#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
++#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
++#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
++#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
++#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
++#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
++#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
++#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
++#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
++#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
++#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
++#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
++#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
++#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
++#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
++#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
++#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
++#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
++#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
++#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
++#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
++#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
++#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
++#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
++#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
++#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
++#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
++#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
++#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
++#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
++#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
++#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
++#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
++#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
++#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
++#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
++#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
++#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
++#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
++#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
++#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
++#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
++#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
++#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
++#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
++#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
++#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
++#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
++#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
++#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
++#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
++#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
++#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
++#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
++#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
++#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
++#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
++#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
++#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
++#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
++#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
++#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
++#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
++#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
++#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
++#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
++#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
++#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
++#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
++#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
++#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
++#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
++#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
++#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
++#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
++#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
++#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
++#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
++#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
++#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
++#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
++#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
++#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
++#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
++#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
++#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
++#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
++#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
++#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
++#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
++#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
++#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
++#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
++#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
++#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
++#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
++#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
++#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
++#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
++#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
++#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
++#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
++#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
++#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
++#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
++#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
++#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
++#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
++#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
++#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
++#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
++#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
++#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
++#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
++#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
++#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
++#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
++#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
++#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
++#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
++#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
++#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
++#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
++#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
++#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
++#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
++#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
++#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
++#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
++#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
++#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
++#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
++#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
++#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
++#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
++#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
++#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
++#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
++#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
++#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
++#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
++#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
++#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
++#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
++#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
++#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
++#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
++#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
++#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
++#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
++#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
++#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
++#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
++#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
++#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
++#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
++#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
++#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
++#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
++#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
++#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
++#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
++#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
++#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
++#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
++#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
++#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
++#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
++#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
++#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
++#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
++#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
++#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
++#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
++#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
++#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
++#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
++#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
++#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
++#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
++#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
++#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
++#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
++#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
++#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
++#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
++#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
++#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
++#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
++#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
++#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
++#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
++#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
++#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
++#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
++#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
++#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
++#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
++#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
++#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
++#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
++#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
++#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
++#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
++#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
++#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
++#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
++#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
++#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
++#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
++#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
++#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
++#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
++#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
++#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
++#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
++#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
++#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
++#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
++#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
++#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
++#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
++#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
++#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
++#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
++#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
++#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
++#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
++#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
++#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
++#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
++#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
++#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
++#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
++#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
++#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
++#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
++#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
++#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
++#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
++#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
++#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
++#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
++#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
++#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
++#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
++#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
++#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
++#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
++#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
++#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
++#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
++#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
++#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
++#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
++#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
++#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
++#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
++#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
++#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
++#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
++#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
++#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
++#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
++#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
++#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
++#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
++#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
++#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
++#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
++#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
++#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
++#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
++#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
++#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
++#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
++#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
++#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
++#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
++#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
++#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
++#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
++#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
++#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
++#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
++#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
++#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
++#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
++#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
++#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
++#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
++#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
++#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
++#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
++#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
++#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
++#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
++#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
++#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
++#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
++#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
++#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
++#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
++#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
++#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
++#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
++#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
++#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
++#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
++#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
++#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
++#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
++#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
++#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
++#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
++#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
++#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
++#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
++#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
++#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
++#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
++#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
++#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
++#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
++#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
++#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
++#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
++#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
++#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
++#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
++#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
++#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
++#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
++#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
++#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
++#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
++#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
++#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
++#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
++#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
++#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
++#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
++#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
++#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
++#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
++#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
++#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
++#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
++#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
++#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
++#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
++#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
++#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
++#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
++#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
++#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
++#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
++#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
++#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
++#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
++#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
++#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
++#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
++#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
++#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
++#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
++#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
++#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x1
++#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x0
++#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x2
++#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x1
++#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x4
++#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x2
++#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x8
++#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x3
++#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x10
++#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x20
++#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x40
++#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x80
++#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x100
++#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x8
++#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x200
++#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x9
++#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x400
++#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0xa
++#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x800
++#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0xb
++#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x1000
++#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0xc
++#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x2000
++#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0xd
++#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x4000
++#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0xe
++#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x8000
++#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0xf
++#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x70000
++#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x10
++#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x80000
++#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x13
++#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0xf00000
++#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x2000000
++#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x19
++#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x4000000
++#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x1a
++#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x8000000
++#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000
++#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x1c
++#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000
++#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x1e
++#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000
++#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x1f
++#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
++#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
++#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
++#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
++#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
++#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
++#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
++#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
++#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
++#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
++#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
++#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
++#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
++#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
++#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
++#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
++#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
++#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
++#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
++#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
++#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
++#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
++#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
++#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
++#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
++#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
++#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
++#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
++#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
++#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
++#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
++#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
++#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
++#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
++#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
++#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
++#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
++#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
++#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
++#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
++#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
++#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
++#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
++#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
++#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
++#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
++#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
++#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
++#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
++#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
++#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
++#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
++#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
++#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
++#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
++#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
++#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
++#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
++#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
++#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
++#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
++#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
++#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
++#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
++#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
++#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
++#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
++#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
++#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
++#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
++#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
++#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
++#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
++#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
++#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
++#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
++#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
++#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
++#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
++#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
++#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
++#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
++#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
++#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
++#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
++#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
++#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
++#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
++#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
++#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
++#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
++#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
++#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
++#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
++#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
++#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
++#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
++#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
++#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
++#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
++#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
++#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
++#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
++#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
++#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
++#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
++#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
++#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
++#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
++#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
++#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
++#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
++#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
++#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
++#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
++#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
++#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
++#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
++#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
++#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
++#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
++#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
++#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
++#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
++#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
++#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
++#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
++#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
++#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
++#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
++#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
++#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
++#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
++#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
++#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
++#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
++#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
++#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
++#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
++#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
++#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
++#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
++#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
++#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
++#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
++#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
++#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
++#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
++#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
++#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
++#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
++#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
++#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
++#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
++#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
++#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
++#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
++#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
++#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
++#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
++#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
++#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
++#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
++#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
++#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
++#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
++#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
++#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
++#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
++#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
++#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
++#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
++#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
++#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
++#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
++#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
++#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
++#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
++#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
++#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
++#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
++#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
++#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
++#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
++#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
++#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
++#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
++#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
++#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
++#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
++#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
++#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
++#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
++#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
++#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
++#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
++#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
++#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
++#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
++#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x1
++#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x0
++#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x2
++#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x1
++#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x4
++#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x2
++#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x8
++#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x10
++#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x4
++#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x20
++#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x5
++#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x40
++#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x6
++#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x80
++#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x7
++#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x100
++#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x8
++#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x200
++#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x9
++#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x400
++#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0xa
++#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x800
++#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0xb
++#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x3f000
++#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0xc
++#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x40000
++#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x12
++#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x80000
++#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x13
++#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x7f00000
++#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x14
++#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x8000000
++#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x1b
++#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000
++#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x1c
++#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000
++#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x1d
++#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000
++#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x1e
++#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000
++#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x1f
++#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
++#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
++#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
++#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
++#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
++#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++
++#endif /* GFX_7_2_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0009-yocto-amd-drm-amdgpu-add-amdgpu_family-h.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0009-yocto-amd-drm-amdgpu-add-amdgpu_family-h.patch
new file mode 100644
index 00000000..1625382e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0009-yocto-amd-drm-amdgpu-add-amdgpu_family-h.patch
@@ -0,0 +1,30477 @@
+From f6b2805750801fe5bccbef01e25f29a8353ab6ac Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:21:21 -0400
+Subject: drm/amdgpu: add GCA 8.0 register headers
+
+These are register headers for the GCA (Graphics and Compute Array)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
+new file mode 100644
+index 0000000..daf763b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
+@@ -0,0 +1,2811 @@
++/*
++ * GFX_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_8_0_D_H
++#define GFX_8_0_D_H
++
++#define mmCB_BLEND_RED                                                          0xa105
++#define mmCB_BLEND_GREEN                                                        0xa106
++#define mmCB_BLEND_BLUE                                                         0xa107
++#define mmCB_BLEND_ALPHA                                                        0xa108
++#define mmCB_DCC_CONTROL                                                        0xa109
++#define mmCB_COLOR_CONTROL                                                      0xa202
++#define mmCB_BLEND0_CONTROL                                                     0xa1e0
++#define mmCB_BLEND1_CONTROL                                                     0xa1e1
++#define mmCB_BLEND2_CONTROL                                                     0xa1e2
++#define mmCB_BLEND3_CONTROL                                                     0xa1e3
++#define mmCB_BLEND4_CONTROL                                                     0xa1e4
++#define mmCB_BLEND5_CONTROL                                                     0xa1e5
++#define mmCB_BLEND6_CONTROL                                                     0xa1e6
++#define mmCB_BLEND7_CONTROL                                                     0xa1e7
++#define mmCB_COLOR0_BASE                                                        0xa318
++#define mmCB_COLOR1_BASE                                                        0xa327
++#define mmCB_COLOR2_BASE                                                        0xa336
++#define mmCB_COLOR3_BASE                                                        0xa345
++#define mmCB_COLOR4_BASE                                                        0xa354
++#define mmCB_COLOR5_BASE                                                        0xa363
++#define mmCB_COLOR6_BASE                                                        0xa372
++#define mmCB_COLOR7_BASE                                                        0xa381
++#define mmCB_COLOR0_PITCH                                                       0xa319
++#define mmCB_COLOR1_PITCH                                                       0xa328
++#define mmCB_COLOR2_PITCH                                                       0xa337
++#define mmCB_COLOR3_PITCH                                                       0xa346
++#define mmCB_COLOR4_PITCH                                                       0xa355
++#define mmCB_COLOR5_PITCH                                                       0xa364
++#define mmCB_COLOR6_PITCH                                                       0xa373
++#define mmCB_COLOR7_PITCH                                                       0xa382
++#define mmCB_COLOR0_SLICE                                                       0xa31a
++#define mmCB_COLOR1_SLICE                                                       0xa329
++#define mmCB_COLOR2_SLICE                                                       0xa338
++#define mmCB_COLOR3_SLICE                                                       0xa347
++#define mmCB_COLOR4_SLICE                                                       0xa356
++#define mmCB_COLOR5_SLICE                                                       0xa365
++#define mmCB_COLOR6_SLICE                                                       0xa374
++#define mmCB_COLOR7_SLICE                                                       0xa383
++#define mmCB_COLOR0_VIEW                                                        0xa31b
++#define mmCB_COLOR1_VIEW                                                        0xa32a
++#define mmCB_COLOR2_VIEW                                                        0xa339
++#define mmCB_COLOR3_VIEW                                                        0xa348
++#define mmCB_COLOR4_VIEW                                                        0xa357
++#define mmCB_COLOR5_VIEW                                                        0xa366
++#define mmCB_COLOR6_VIEW                                                        0xa375
++#define mmCB_COLOR7_VIEW                                                        0xa384
++#define mmCB_COLOR0_INFO                                                        0xa31c
++#define mmCB_COLOR1_INFO                                                        0xa32b
++#define mmCB_COLOR2_INFO                                                        0xa33a
++#define mmCB_COLOR3_INFO                                                        0xa349
++#define mmCB_COLOR4_INFO                                                        0xa358
++#define mmCB_COLOR5_INFO                                                        0xa367
++#define mmCB_COLOR6_INFO                                                        0xa376
++#define mmCB_COLOR7_INFO                                                        0xa385
++#define mmCB_COLOR0_ATTRIB                                                      0xa31d
++#define mmCB_COLOR1_ATTRIB                                                      0xa32c
++#define mmCB_COLOR2_ATTRIB                                                      0xa33b
++#define mmCB_COLOR3_ATTRIB                                                      0xa34a
++#define mmCB_COLOR4_ATTRIB                                                      0xa359
++#define mmCB_COLOR5_ATTRIB                                                      0xa368
++#define mmCB_COLOR6_ATTRIB                                                      0xa377
++#define mmCB_COLOR7_ATTRIB                                                      0xa386
++#define mmCB_COLOR0_DCC_CONTROL                                                 0xa31e
++#define mmCB_COLOR1_DCC_CONTROL                                                 0xa32d
++#define mmCB_COLOR2_DCC_CONTROL                                                 0xa33c
++#define mmCB_COLOR3_DCC_CONTROL                                                 0xa34b
++#define mmCB_COLOR4_DCC_CONTROL                                                 0xa35a
++#define mmCB_COLOR5_DCC_CONTROL                                                 0xa369
++#define mmCB_COLOR6_DCC_CONTROL                                                 0xa378
++#define mmCB_COLOR7_DCC_CONTROL                                                 0xa387
++#define mmCB_COLOR0_CMASK                                                       0xa31f
++#define mmCB_COLOR1_CMASK                                                       0xa32e
++#define mmCB_COLOR2_CMASK                                                       0xa33d
++#define mmCB_COLOR3_CMASK                                                       0xa34c
++#define mmCB_COLOR4_CMASK                                                       0xa35b
++#define mmCB_COLOR5_CMASK                                                       0xa36a
++#define mmCB_COLOR6_CMASK                                                       0xa379
++#define mmCB_COLOR7_CMASK                                                       0xa388
++#define mmCB_COLOR0_CMASK_SLICE                                                 0xa320
++#define mmCB_COLOR1_CMASK_SLICE                                                 0xa32f
++#define mmCB_COLOR2_CMASK_SLICE                                                 0xa33e
++#define mmCB_COLOR3_CMASK_SLICE                                                 0xa34d
++#define mmCB_COLOR4_CMASK_SLICE                                                 0xa35c
++#define mmCB_COLOR5_CMASK_SLICE                                                 0xa36b
++#define mmCB_COLOR6_CMASK_SLICE                                                 0xa37a
++#define mmCB_COLOR7_CMASK_SLICE                                                 0xa389
++#define mmCB_COLOR0_FMASK                                                       0xa321
++#define mmCB_COLOR1_FMASK                                                       0xa330
++#define mmCB_COLOR2_FMASK                                                       0xa33f
++#define mmCB_COLOR3_FMASK                                                       0xa34e
++#define mmCB_COLOR4_FMASK                                                       0xa35d
++#define mmCB_COLOR5_FMASK                                                       0xa36c
++#define mmCB_COLOR6_FMASK                                                       0xa37b
++#define mmCB_COLOR7_FMASK                                                       0xa38a
++#define mmCB_COLOR0_FMASK_SLICE                                                 0xa322
++#define mmCB_COLOR1_FMASK_SLICE                                                 0xa331
++#define mmCB_COLOR2_FMASK_SLICE                                                 0xa340
++#define mmCB_COLOR3_FMASK_SLICE                                                 0xa34f
++#define mmCB_COLOR4_FMASK_SLICE                                                 0xa35e
++#define mmCB_COLOR5_FMASK_SLICE                                                 0xa36d
++#define mmCB_COLOR6_FMASK_SLICE                                                 0xa37c
++#define mmCB_COLOR7_FMASK_SLICE                                                 0xa38b
++#define mmCB_COLOR0_CLEAR_WORD0                                                 0xa323
++#define mmCB_COLOR1_CLEAR_WORD0                                                 0xa332
++#define mmCB_COLOR2_CLEAR_WORD0                                                 0xa341
++#define mmCB_COLOR3_CLEAR_WORD0                                                 0xa350
++#define mmCB_COLOR4_CLEAR_WORD0                                                 0xa35f
++#define mmCB_COLOR5_CLEAR_WORD0                                                 0xa36e
++#define mmCB_COLOR6_CLEAR_WORD0                                                 0xa37d
++#define mmCB_COLOR7_CLEAR_WORD0                                                 0xa38c
++#define mmCB_COLOR0_CLEAR_WORD1                                                 0xa324
++#define mmCB_COLOR1_CLEAR_WORD1                                                 0xa333
++#define mmCB_COLOR2_CLEAR_WORD1                                                 0xa342
++#define mmCB_COLOR3_CLEAR_WORD1                                                 0xa351
++#define mmCB_COLOR4_CLEAR_WORD1                                                 0xa360
++#define mmCB_COLOR5_CLEAR_WORD1                                                 0xa36f
++#define mmCB_COLOR6_CLEAR_WORD1                                                 0xa37e
++#define mmCB_COLOR7_CLEAR_WORD1                                                 0xa38d
++#define mmCB_COLOR0_DCC_BASE                                                    0xa325
++#define mmCB_COLOR1_DCC_BASE                                                    0xa334
++#define mmCB_COLOR2_DCC_BASE                                                    0xa343
++#define mmCB_COLOR3_DCC_BASE                                                    0xa352
++#define mmCB_COLOR4_DCC_BASE                                                    0xa361
++#define mmCB_COLOR5_DCC_BASE                                                    0xa370
++#define mmCB_COLOR6_DCC_BASE                                                    0xa37f
++#define mmCB_COLOR7_DCC_BASE                                                    0xa38e
++#define mmCB_TARGET_MASK                                                        0xa08e
++#define mmCB_SHADER_MASK                                                        0xa08f
++#define mmCB_HW_CONTROL                                                         0x2684
++#define mmCB_HW_CONTROL_1                                                       0x2685
++#define mmCB_HW_CONTROL_2                                                       0x2686
++#define mmCB_HW_CONTROL_3                                                       0x2683
++#define mmCB_DCC_CONFIG                                                         0x2687
++#define mmCB_PERFCOUNTER_FILTER                                                 0xdc00
++#define mmCB_PERFCOUNTER0_SELECT                                                0xdc01
++#define mmCB_PERFCOUNTER0_SELECT1                                               0xdc02
++#define mmCB_PERFCOUNTER1_SELECT                                                0xdc03
++#define mmCB_PERFCOUNTER2_SELECT                                                0xdc04
++#define mmCB_PERFCOUNTER3_SELECT                                                0xdc05
++#define mmCB_PERFCOUNTER0_LO                                                    0xd406
++#define mmCB_PERFCOUNTER1_LO                                                    0xd408
++#define mmCB_PERFCOUNTER2_LO                                                    0xd40a
++#define mmCB_PERFCOUNTER3_LO                                                    0xd40c
++#define mmCB_PERFCOUNTER0_HI                                                    0xd407
++#define mmCB_PERFCOUNTER1_HI                                                    0xd409
++#define mmCB_PERFCOUNTER2_HI                                                    0xd40b
++#define mmCB_PERFCOUNTER3_HI                                                    0xd40d
++#define mmCB_CGTT_SCLK_CTRL                                                     0xf0a8
++#define mmCB_DEBUG_BUS_1                                                        0x2699
++#define mmCB_DEBUG_BUS_2                                                        0x269a
++#define mmCB_DEBUG_BUS_3                                                        0x269b
++#define mmCB_DEBUG_BUS_4                                                        0x269c
++#define mmCB_DEBUG_BUS_5                                                        0x269d
++#define mmCB_DEBUG_BUS_6                                                        0x269e
++#define mmCB_DEBUG_BUS_7                                                        0x269f
++#define mmCB_DEBUG_BUS_8                                                        0x26a0
++#define mmCB_DEBUG_BUS_9                                                        0x26a1
++#define mmCB_DEBUG_BUS_10                                                       0x26a2
++#define mmCB_DEBUG_BUS_11                                                       0x26a3
++#define mmCB_DEBUG_BUS_12                                                       0x26a4
++#define mmCB_DEBUG_BUS_13                                                       0x26a5
++#define mmCB_DEBUG_BUS_14                                                       0x26a6
++#define mmCB_DEBUG_BUS_15                                                       0x26a7
++#define mmCB_DEBUG_BUS_16                                                       0x26a8
++#define mmCB_DEBUG_BUS_17                                                       0x26a9
++#define mmCB_DEBUG_BUS_18                                                       0x26aa
++#define mmCB_DEBUG_BUS_19                                                       0x26ab
++#define mmCB_DEBUG_BUS_20                                                       0x26ac
++#define mmCB_DEBUG_BUS_21                                                       0x26ad
++#define mmCB_DEBUG_BUS_22                                                       0x26ae
++#define mmCP_DFY_CNTL                                                           0x3020
++#define mmCP_DFY_STAT                                                           0x3021
++#define mmCP_DFY_ADDR_HI                                                        0x3022
++#define mmCP_DFY_ADDR_LO                                                        0x3023
++#define mmCP_DFY_DATA_0                                                         0x3024
++#define mmCP_DFY_DATA_1                                                         0x3025
++#define mmCP_DFY_DATA_2                                                         0x3026
++#define mmCP_DFY_DATA_3                                                         0x3027
++#define mmCP_DFY_DATA_4                                                         0x3028
++#define mmCP_DFY_DATA_5                                                         0x3029
++#define mmCP_DFY_DATA_6                                                         0x302a
++#define mmCP_DFY_DATA_7                                                         0x302b
++#define mmCP_DFY_DATA_8                                                         0x302c
++#define mmCP_DFY_DATA_9                                                         0x302d
++#define mmCP_DFY_DATA_10                                                        0x302e
++#define mmCP_DFY_DATA_11                                                        0x302f
++#define mmCP_DFY_DATA_12                                                        0x3030
++#define mmCP_DFY_DATA_13                                                        0x3031
++#define mmCP_DFY_DATA_14                                                        0x3032
++#define mmCP_DFY_DATA_15                                                        0x3033
++#define mmCP_DFY_CMD                                                            0x3034
++#define mmCP_CPC_MGCG_SYNC_CNTL                                                 0x3036
++#define mmCP_RB0_BASE                                                           0x3040
++#define mmCP_RB0_BASE_HI                                                        0x30b1
++#define mmCP_RB_BASE                                                            0x3040
++#define mmCP_RB1_BASE                                                           0x3060
++#define mmCP_RB1_BASE_HI                                                        0x30b2
++#define mmCP_RB2_BASE                                                           0x3065
++#define mmCP_RB0_CNTL                                                           0x3041
++#define mmCP_RB_CNTL                                                            0x3041
++#define mmCP_RB1_CNTL                                                           0x3061
++#define mmCP_RB2_CNTL                                                           0x3066
++#define mmCP_RB_RPTR_WR                                                         0x3042
++#define mmCP_RB0_RPTR_ADDR                                                      0x3043
++#define mmCP_RB_RPTR_ADDR                                                       0x3043
++#define mmCP_RB1_RPTR_ADDR                                                      0x3062
++#define mmCP_RB2_RPTR_ADDR                                                      0x3067
++#define mmCP_RB0_RPTR_ADDR_HI                                                   0x3044
++#define mmCP_RB_RPTR_ADDR_HI                                                    0x3044
++#define mmCP_RB1_RPTR_ADDR_HI                                                   0x3063
++#define mmCP_RB2_RPTR_ADDR_HI                                                   0x3068
++#define mmCP_RB0_WPTR                                                           0x3045
++#define mmCP_RB_WPTR                                                            0x3045
++#define mmCP_RB1_WPTR                                                           0x3064
++#define mmCP_RB2_WPTR                                                           0x3069
++#define mmCP_RB_WPTR_POLL_ADDR_LO                                               0x3046
++#define mmCP_RB_WPTR_POLL_ADDR_HI                                               0x3047
++#define mmGC_PRIV_MODE                                                          0x3048
++#define mmCP_INT_CNTL                                                           0x3049
++#define mmCP_INT_CNTL_RING0                                                     0x306a
++#define mmCP_INT_CNTL_RING1                                                     0x306b
++#define mmCP_INT_CNTL_RING2                                                     0x306c
++#define mmCP_INT_STATUS                                                         0x304a
++#define mmCP_INT_STATUS_RING0                                                   0x306d
++#define mmCP_INT_STATUS_RING1                                                   0x306e
++#define mmCP_INT_STATUS_RING2                                                   0x306f
++#define mmCP_DEVICE_ID                                                          0x304b
++#define mmCP_RING_PRIORITY_CNTS                                                 0x304c
++#define mmCP_ME0_PIPE_PRIORITY_CNTS                                             0x304c
++#define mmCP_RING0_PRIORITY                                                     0x304d
++#define mmCP_ME0_PIPE0_PRIORITY                                                 0x304d
++#define mmCP_RING1_PRIORITY                                                     0x304e
++#define mmCP_ME0_PIPE1_PRIORITY                                                 0x304e
++#define mmCP_RING2_PRIORITY                                                     0x304f
++#define mmCP_ME0_PIPE2_PRIORITY                                                 0x304f
++#define mmCP_ENDIAN_SWAP                                                        0x3050
++#define mmCP_RB_VMID                                                            0x3051
++#define mmCP_ME0_PIPE0_VMID                                                     0x3052
++#define mmCP_ME0_PIPE1_VMID                                                     0x3053
++#define mmCP_RB_DOORBELL_CONTROL                                                0x3059
++#define mmCP_RB_DOORBELL_RANGE_LOWER                                            0x305a
++#define mmCP_RB_DOORBELL_RANGE_UPPER                                            0x305b
++#define mmCP_MEC_DOORBELL_RANGE_LOWER                                           0x305c
++#define mmCP_MEC_DOORBELL_RANGE_UPPER                                           0x305d
++#define mmCP_PFP_UCODE_ADDR                                                     0xf814
++#define mmCP_PFP_UCODE_DATA                                                     0xf815
++#define mmCP_ME_RAM_RADDR                                                       0xf816
++#define mmCP_ME_RAM_WADDR                                                       0xf816
++#define mmCP_ME_RAM_DATA                                                        0xf817
++#define mmCGTT_CPC_CLK_CTRL                                                     0xf0b2
++#define mmCGTT_CPF_CLK_CTRL                                                     0xf0b1
++#define mmCGTT_CP_CLK_CTRL                                                      0xf0b0
++#define mmCP_CE_UCODE_ADDR                                                      0xf818
++#define mmCP_CE_UCODE_DATA                                                      0xf819
++#define mmCP_MEC_ME1_UCODE_ADDR                                                 0xf81a
++#define mmCP_MEC_ME1_UCODE_DATA                                                 0xf81b
++#define mmCP_MEC_ME2_UCODE_ADDR                                                 0xf81c
++#define mmCP_MEC_ME2_UCODE_DATA                                                 0xf81d
++#define mmCP_MEC1_F32_INT_DIS                                                   0x30bd
++#define mmCP_MEC2_F32_INT_DIS                                                   0x30be
++#define mmCP_VIRT_STATUS                                                        0x3038
++#define mmCP_PWR_CNTL                                                           0x3078
++#define mmCP_MEM_SLP_CNTL                                                       0x3079
++#define mmCP_ECC_FIRSTOCCURRENCE                                                0x307a
++#define mmCP_ECC_FIRSTOCCURRENCE_RING0                                          0x307b
++#define mmCP_ECC_FIRSTOCCURRENCE_RING1                                          0x307c
++#define mmCP_ECC_FIRSTOCCURRENCE_RING2                                          0x307d
++#define mmCP_CPF_DEBUG                                                          0x3080
++#define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
++#define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
++#define mmCPC_INT_CNTL                                                          0x30b4
++#define mmCP_ME1_PIPE0_INT_CNTL                                                 0x3085
++#define mmCP_ME1_PIPE1_INT_CNTL                                                 0x3086
++#define mmCP_ME1_PIPE2_INT_CNTL                                                 0x3087
++#define mmCP_ME1_PIPE3_INT_CNTL                                                 0x3088
++#define mmCP_ME2_PIPE0_INT_CNTL                                                 0x3089
++#define mmCP_ME2_PIPE1_INT_CNTL                                                 0x308a
++#define mmCP_ME2_PIPE2_INT_CNTL                                                 0x308b
++#define mmCP_ME2_PIPE3_INT_CNTL                                                 0x308c
++#define mmCPC_INT_STATUS                                                        0x30b5
++#define mmCP_ME1_PIPE0_INT_STATUS                                               0x308d
++#define mmCP_ME1_PIPE1_INT_STATUS                                               0x308e
++#define mmCP_ME1_PIPE2_INT_STATUS                                               0x308f
++#define mmCP_ME1_PIPE3_INT_STATUS                                               0x3090
++#define mmCP_ME2_PIPE0_INT_STATUS                                               0x3091
++#define mmCP_ME2_PIPE1_INT_STATUS                                               0x3092
++#define mmCP_ME2_PIPE2_INT_STATUS                                               0x3093
++#define mmCP_ME2_PIPE3_INT_STATUS                                               0x3094
++#define mmCP_ME1_INT_STAT_DEBUG                                                 0x3095
++#define mmCP_ME2_INT_STAT_DEBUG                                                 0x3096
++#define mmCP_ME1_PIPE_PRIORITY_CNTS                                             0x3099
++#define mmCP_ME1_PIPE0_PRIORITY                                                 0x309a
++#define mmCP_ME1_PIPE1_PRIORITY                                                 0x309b
++#define mmCP_ME1_PIPE2_PRIORITY                                                 0x309c
++#define mmCP_ME1_PIPE3_PRIORITY                                                 0x309d
++#define mmCP_ME2_PIPE_PRIORITY_CNTS                                             0x309e
++#define mmCP_ME2_PIPE0_PRIORITY                                                 0x309f
++#define mmCP_ME2_PIPE1_PRIORITY                                                 0x30a0
++#define mmCP_ME2_PIPE2_PRIORITY                                                 0x30a1
++#define mmCP_ME2_PIPE3_PRIORITY                                                 0x30a2
++#define mmCP_CE_PRGRM_CNTR_START                                                0x30a3
++#define mmCP_PFP_PRGRM_CNTR_START                                               0x30a4
++#define mmCP_ME_PRGRM_CNTR_START                                                0x30a5
++#define mmCP_MEC1_PRGRM_CNTR_START                                              0x30a6
++#define mmCP_MEC2_PRGRM_CNTR_START                                              0x30a7
++#define mmCP_CE_INTR_ROUTINE_START                                              0x30a8
++#define mmCP_PFP_INTR_ROUTINE_START                                             0x30a9
++#define mmCP_ME_INTR_ROUTINE_START                                              0x30aa
++#define mmCP_MEC1_INTR_ROUTINE_START                                            0x30ab
++#define mmCP_MEC2_INTR_ROUTINE_START                                            0x30ac
++#define mmCP_CONTEXT_CNTL                                                       0x30ad
++#define mmCP_MAX_CONTEXT                                                        0x30ae
++#define mmCP_IQ_WAIT_TIME1                                                      0x30af
++#define mmCP_IQ_WAIT_TIME2                                                      0x30b0
++#define mmCP_VMID_RESET                                                         0x30b3
++#define mmCP_VMID_PREEMPT                                                       0x30b6
++#define mmCP_VMID_STATUS                                                        0x30bf
++#define mmCPC_INT_CNTX_ID                                                       0x30b7
++#define mmCP_PQ_STATUS                                                          0x30b8
++#define mmCP_CPC_IC_BASE_LO                                                     0x30b9
++#define mmCP_CPC_IC_BASE_HI                                                     0x30ba
++#define mmCP_CPC_IC_BASE_CNTL                                                   0x30bb
++#define mmCP_CPC_IC_OP_CNTL                                                     0x30bc
++#define mmCP_CPC_STATUS                                                         0x2084
++#define mmCP_CPC_BUSY_STAT                                                      0x2085
++#define mmCP_CPC_STALLED_STAT1                                                  0x2086
++#define mmCP_CPF_STATUS                                                         0x2087
++#define mmCP_CPF_BUSY_STAT                                                      0x2088
++#define mmCP_CPF_STALLED_STAT1                                                  0x2089
++#define mmCP_CPC_GRBM_FREE_COUNT                                                0x208b
++#define mmCP_MEC_CNTL                                                           0x208d
++#define mmCP_MEC_ME1_HEADER_DUMP                                                0x208e
++#define mmCP_MEC_ME2_HEADER_DUMP                                                0x208f
++#define mmCP_CPC_SCRATCH_INDEX                                                  0x2090
++#define mmCP_CPC_SCRATCH_DATA                                                   0x2091
++#define mmCPG_PERFCOUNTER1_SELECT                                               0xd800
++#define mmCPG_PERFCOUNTER1_LO                                                   0xd000
++#define mmCPG_PERFCOUNTER1_HI                                                   0xd001
++#define mmCPG_PERFCOUNTER0_SELECT1                                              0xd801
++#define mmCPG_PERFCOUNTER0_SELECT                                               0xd802
++#define mmCPG_PERFCOUNTER0_LO                                                   0xd002
++#define mmCPG_PERFCOUNTER0_HI                                                   0xd003
++#define mmCPC_PERFCOUNTER1_SELECT                                               0xd803
++#define mmCPC_PERFCOUNTER1_LO                                                   0xd004
++#define mmCPC_PERFCOUNTER1_HI                                                   0xd005
++#define mmCPC_PERFCOUNTER0_SELECT1                                              0xd804
++#define mmCPC_PERFCOUNTER0_SELECT                                               0xd809
++#define mmCPC_PERFCOUNTER0_LO                                                   0xd006
++#define mmCPC_PERFCOUNTER0_HI                                                   0xd007
++#define mmCPF_PERFCOUNTER1_SELECT                                               0xd805
++#define mmCPF_PERFCOUNTER1_LO                                                   0xd008
++#define mmCPF_PERFCOUNTER1_HI                                                   0xd009
++#define mmCPF_PERFCOUNTER0_SELECT1                                              0xd806
++#define mmCPF_PERFCOUNTER0_SELECT                                               0xd807
++#define mmCPF_PERFCOUNTER0_LO                                                   0xd00a
++#define mmCPF_PERFCOUNTER0_HI                                                   0xd00b
++#define mmCP_CPC_HALT_HYST_COUNT                                                0x20a7
++#define mmCP_DRAW_OBJECT                                                        0xd810
++#define mmCP_DRAW_OBJECT_COUNTER                                                0xd811
++#define mmCP_DRAW_WINDOW_MASK_HI                                                0xd812
++#define mmCP_DRAW_WINDOW_HI                                                     0xd813
++#define mmCP_DRAW_WINDOW_LO                                                     0xd814
++#define mmCP_DRAW_WINDOW_CNTL                                                   0xd815
++#define mmCP_PRT_LOD_STATS_CNTL0                                                0x20ad
++#define mmCP_PRT_LOD_STATS_CNTL1                                                0x20ae
++#define mmCP_PRT_LOD_STATS_CNTL2                                                0x20af
++#define mmCP_CE_COMPARE_COUNT                                                   0x20c0
++#define mmCP_CE_DE_COUNT                                                        0x20c1
++#define mmCP_DE_CE_COUNT                                                        0x20c2
++#define mmCP_DE_LAST_INVAL_COUNT                                                0x20c3
++#define mmCP_DE_DE_COUNT                                                        0x20c4
++#define mmCP_EOP_DONE_EVENT_CNTL                                                0xc0d5
++#define mmCP_EOP_DONE_DATA_CNTL                                                 0xc0d6
++#define mmCP_EOP_DONE_CNTX_ID                                                   0xc0d7
++#define mmCP_EOP_DONE_ADDR_LO                                                   0xc000
++#define mmCP_EOP_DONE_ADDR_HI                                                   0xc001
++#define mmCP_EOP_DONE_DATA_LO                                                   0xc002
++#define mmCP_EOP_DONE_DATA_HI                                                   0xc003
++#define mmCP_EOP_LAST_FENCE_LO                                                  0xc004
++#define mmCP_EOP_LAST_FENCE_HI                                                  0xc005
++#define mmCP_STREAM_OUT_ADDR_LO                                                 0xc006
++#define mmCP_STREAM_OUT_ADDR_HI                                                 0xc007
++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                                         0xc008
++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                                         0xc009
++#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO                                          0xc00a
++#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI                                          0xc00b
++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                                         0xc00c
++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                                         0xc00d
++#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO                                          0xc00e
++#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI                                          0xc00f
++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                                         0xc010
++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                                         0xc011
++#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO                                          0xc012
++#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI                                          0xc013
++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                                         0xc014
++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                                         0xc015
++#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO                                          0xc016
++#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI                                          0xc017
++#define mmCP_PIPE_STATS_ADDR_LO                                                 0xc018
++#define mmCP_PIPE_STATS_ADDR_HI                                                 0xc019
++#define mmCP_VGT_IAVERT_COUNT_LO                                                0xc01a
++#define mmCP_VGT_IAVERT_COUNT_HI                                                0xc01b
++#define mmCP_VGT_IAPRIM_COUNT_LO                                                0xc01c
++#define mmCP_VGT_IAPRIM_COUNT_HI                                                0xc01d
++#define mmCP_VGT_GSPRIM_COUNT_LO                                                0xc01e
++#define mmCP_VGT_GSPRIM_COUNT_HI                                                0xc01f
++#define mmCP_VGT_VSINVOC_COUNT_LO                                               0xc020
++#define mmCP_VGT_VSINVOC_COUNT_HI                                               0xc021
++#define mmCP_VGT_GSINVOC_COUNT_LO                                               0xc022
++#define mmCP_VGT_GSINVOC_COUNT_HI                                               0xc023
++#define mmCP_VGT_HSINVOC_COUNT_LO                                               0xc024
++#define mmCP_VGT_HSINVOC_COUNT_HI                                               0xc025
++#define mmCP_VGT_DSINVOC_COUNT_LO                                               0xc026
++#define mmCP_VGT_DSINVOC_COUNT_HI                                               0xc027
++#define mmCP_PA_CINVOC_COUNT_LO                                                 0xc028
++#define mmCP_PA_CINVOC_COUNT_HI                                                 0xc029
++#define mmCP_PA_CPRIM_COUNT_LO                                                  0xc02a
++#define mmCP_PA_CPRIM_COUNT_HI                                                  0xc02b
++#define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
++#define mmCP_SC_PSINVOC_COUNT0_HI                                               0xc02d
++#define mmCP_SC_PSINVOC_COUNT1_LO                                               0xc02e
++#define mmCP_SC_PSINVOC_COUNT1_HI                                               0xc02f
++#define mmCP_VGT_CSINVOC_COUNT_LO                                               0xc030
++#define mmCP_VGT_CSINVOC_COUNT_HI                                               0xc031
++#define mmCP_PIPE_STATS_CONTROL                                                 0xc03d
++#define mmCP_STREAM_OUT_CONTROL                                                 0xc03e
++#define mmCP_STRMOUT_CNTL                                                       0xc03f
++#define mmSCRATCH_REG0                                                          0xc040
++#define mmSCRATCH_REG1                                                          0xc041
++#define mmSCRATCH_REG2                                                          0xc042
++#define mmSCRATCH_REG3                                                          0xc043
++#define mmSCRATCH_REG4                                                          0xc044
++#define mmSCRATCH_REG5                                                          0xc045
++#define mmSCRATCH_REG6                                                          0xc046
++#define mmSCRATCH_REG7                                                          0xc047
++#define mmSCRATCH_UMSK                                                          0xc050
++#define mmSCRATCH_ADDR                                                          0xc051
++#define mmCP_PFP_ATOMIC_PREOP_LO                                                0xc052
++#define mmCP_PFP_ATOMIC_PREOP_HI                                                0xc053
++#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO                                           0xc054
++#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI                                           0xc055
++#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO                                           0xc056
++#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI                                           0xc057
++#define mmCP_APPEND_ADDR_LO                                                     0xc058
++#define mmCP_APPEND_ADDR_HI                                                     0xc059
++#define mmCP_APPEND_DATA                                                        0xc05a
++#define mmCP_APPEND_LAST_CS_FENCE                                               0xc05b
++#define mmCP_APPEND_LAST_PS_FENCE                                               0xc05c
++#define mmCP_ATOMIC_PREOP_LO                                                    0xc05d
++#define mmCP_ME_ATOMIC_PREOP_LO                                                 0xc05d
++#define mmCP_ATOMIC_PREOP_HI                                                    0xc05e
++#define mmCP_ME_ATOMIC_PREOP_HI                                                 0xc05e
++#define mmCP_GDS_ATOMIC0_PREOP_LO                                               0xc05f
++#define mmCP_ME_GDS_ATOMIC0_PREOP_LO                                            0xc05f
++#define mmCP_GDS_ATOMIC0_PREOP_HI                                               0xc060
++#define mmCP_ME_GDS_ATOMIC0_PREOP_HI                                            0xc060
++#define mmCP_GDS_ATOMIC1_PREOP_LO                                               0xc061
++#define mmCP_ME_GDS_ATOMIC1_PREOP_LO                                            0xc061
++#define mmCP_GDS_ATOMIC1_PREOP_HI                                               0xc062
++#define mmCP_ME_GDS_ATOMIC1_PREOP_HI                                            0xc062
++#define mmCP_ME_MC_WADDR_LO                                                     0xc069
++#define mmCP_ME_MC_WADDR_HI                                                     0xc06a
++#define mmCP_ME_MC_WDATA_LO                                                     0xc06b
++#define mmCP_ME_MC_WDATA_HI                                                     0xc06c
++#define mmCP_ME_MC_RADDR_LO                                                     0xc06d
++#define mmCP_ME_MC_RADDR_HI                                                     0xc06e
++#define mmCP_SEM_WAIT_TIMER                                                     0xc06f
++#define mmCP_SIG_SEM_ADDR_LO                                                    0xc070
++#define mmCP_SIG_SEM_ADDR_HI                                                    0xc071
++#define mmCP_WAIT_SEM_ADDR_LO                                                   0xc075
++#define mmCP_WAIT_SEM_ADDR_HI                                                   0xc076
++#define mmCP_WAIT_REG_MEM_TIMEOUT                                               0xc074
++#define mmCP_COHER_START_DELAY                                                  0xc07b
++#define mmCP_COHER_CNTL                                                         0xc07c
++#define mmCP_COHER_SIZE                                                         0xc07d
++#define mmCP_COHER_SIZE_HI                                                      0xc08c
++#define mmCP_COHER_BASE                                                         0xc07e
++#define mmCP_COHER_BASE_HI                                                      0xc079
++#define mmCP_COHER_STATUS                                                       0xc07f
++#define mmCOHER_DEST_BASE_0                                                     0xa092
++#define mmCOHER_DEST_BASE_1                                                     0xa093
++#define mmCOHER_DEST_BASE_2                                                     0xa07e
++#define mmCOHER_DEST_BASE_3                                                     0xa07f
++#define mmCOHER_DEST_BASE_HI_0                                                  0xa07a
++#define mmCOHER_DEST_BASE_HI_1                                                  0xa07b
++#define mmCOHER_DEST_BASE_HI_2                                                  0xa07c
++#define mmCOHER_DEST_BASE_HI_3                                                  0xa07d
++#define mmCP_DMA_ME_SRC_ADDR                                                    0xc080
++#define mmCP_DMA_ME_SRC_ADDR_HI                                                 0xc081
++#define mmCP_DMA_ME_DST_ADDR                                                    0xc082
++#define mmCP_DMA_ME_DST_ADDR_HI                                                 0xc083
++#define mmCP_DMA_ME_CONTROL                                                     0xc078
++#define mmCP_DMA_ME_COMMAND                                                     0xc084
++#define mmCP_DMA_PFP_SRC_ADDR                                                   0xc085
++#define mmCP_DMA_PFP_SRC_ADDR_HI                                                0xc086
++#define mmCP_DMA_PFP_DST_ADDR                                                   0xc087
++#define mmCP_DMA_PFP_DST_ADDR_HI                                                0xc088
++#define mmCP_DMA_PFP_CONTROL                                                    0xc077
++#define mmCP_DMA_PFP_COMMAND                                                    0xc089
++#define mmCP_DMA_CNTL                                                           0xc08a
++#define mmCP_DMA_READ_TAGS                                                      0xc08b
++#define mmCP_PFP_IB_CONTROL                                                     0xc08d
++#define mmCP_PFP_LOAD_CONTROL                                                   0xc08e
++#define mmCP_SCRATCH_INDEX                                                      0xc08f
++#define mmCP_SCRATCH_DATA                                                       0xc090
++#define mmCP_RB_OFFSET                                                          0xc091
++#define mmCP_IB1_OFFSET                                                         0xc092
++#define mmCP_IB2_OFFSET                                                         0xc093
++#define mmCP_IB1_PREAMBLE_BEGIN                                                 0xc094
++#define mmCP_IB1_PREAMBLE_END                                                   0xc095
++#define mmCP_IB2_PREAMBLE_BEGIN                                                 0xc096
++#define mmCP_IB2_PREAMBLE_END                                                   0xc097
++#define mmCP_CE_IB1_OFFSET                                                      0xc098
++#define mmCP_CE_IB2_OFFSET                                                      0xc099
++#define mmCP_CE_COUNTER                                                         0xc09a
++#define mmCP_CE_RB_OFFSET                                                       0xc09b
++#define mmCP_PFP_COMPLETION_STATUS                                              0xc0ec
++#define mmCP_CE_COMPLETION_STATUS                                               0xc0ed
++#define mmCP_PRED_NOT_VISIBLE                                                   0xc0ee
++#define mmCP_PFP_METADATA_BASE_ADDR                                             0xc0f0
++#define mmCP_PFP_METADATA_BASE_ADDR_HI                                          0xc0f1
++#define mmCP_CE_METADATA_BASE_ADDR                                              0xc0f2
++#define mmCP_CE_METADATA_BASE_ADDR_HI                                           0xc0f3
++#define mmCP_DRAW_INDX_INDR_ADDR                                                0xc0f4
++#define mmCP_DRAW_INDX_INDR_ADDR_HI                                             0xc0f5
++#define mmCP_DISPATCH_INDR_ADDR                                                 0xc0f6
++#define mmCP_DISPATCH_INDR_ADDR_HI                                              0xc0f7
++#define mmCP_INDEX_BASE_ADDR                                                    0xc0f8
++#define mmCP_INDEX_BASE_ADDR_HI                                                 0xc0f9
++#define mmCP_INDEX_TYPE                                                         0xc0fa
++#define mmCP_GDS_BKUP_ADDR                                                      0xc0fb
++#define mmCP_GDS_BKUP_ADDR_HI                                                   0xc0fc
++#define mmCP_SAMPLE_STATUS                                                      0xc0fd
++#define mmCP_STALLED_STAT1                                                      0x219d
++#define mmCP_STALLED_STAT2                                                      0x219e
++#define mmCP_STALLED_STAT3                                                      0x219c
++#define mmCP_BUSY_STAT                                                          0x219f
++#define mmCP_STAT                                                               0x21a0
++#define mmCP_ME_HEADER_DUMP                                                     0x21a1
++#define mmCP_PFP_HEADER_DUMP                                                    0x21a2
++#define mmCP_GRBM_FREE_COUNT                                                    0x21a3
++#define mmCP_CE_HEADER_DUMP                                                     0x21a4
++#define mmCP_CSF_STAT                                                           0x21b4
++#define mmCP_CSF_CNTL                                                           0x21b5
++#define mmCP_ME_CNTL                                                            0x21b6
++#define mmCP_CNTX_STAT                                                          0x21b8
++#define mmCP_ME_PREEMPTION                                                      0x21b9
++#define mmCP_RB0_RPTR                                                           0x21c0
++#define mmCP_RB_RPTR                                                            0x21c0
++#define mmCP_RB1_RPTR                                                           0x21bf
++#define mmCP_RB2_RPTR                                                           0x21be
++#define mmCP_RB_WPTR_DELAY                                                      0x21c1
++#define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
++#define mmCP_CE_INIT_BASE_LO                                                    0xc0c3
++#define mmCP_CE_INIT_BASE_HI                                                    0xc0c4
++#define mmCP_CE_INIT_BUFSZ                                                      0xc0c5
++#define mmCP_CE_IB1_BASE_LO                                                     0xc0c6
++#define mmCP_CE_IB1_BASE_HI                                                     0xc0c7
++#define mmCP_CE_IB1_BUFSZ                                                       0xc0c8
++#define mmCP_CE_IB2_BASE_LO                                                     0xc0c9
++#define mmCP_CE_IB2_BASE_HI                                                     0xc0ca
++#define mmCP_CE_IB2_BUFSZ                                                       0xc0cb
++#define mmCP_IB1_BASE_LO                                                        0xc0cc
++#define mmCP_IB1_BASE_HI                                                        0xc0cd
++#define mmCP_IB1_BUFSZ                                                          0xc0ce
++#define mmCP_IB2_BASE_LO                                                        0xc0cf
++#define mmCP_IB2_BASE_HI                                                        0xc0d0
++#define mmCP_IB2_BUFSZ                                                          0xc0d1
++#define mmCP_ST_BASE_LO                                                         0xc0d2
++#define mmCP_ST_BASE_HI                                                         0xc0d3
++#define mmCP_ST_BUFSZ                                                           0xc0d4
++#define mmCP_ROQ_THRESHOLDS                                                     0x21bc
++#define mmCP_MEQ_STQ_THRESHOLD                                                  0x21bd
++#define mmCP_ROQ1_THRESHOLDS                                                    0x21d5
++#define mmCP_ROQ2_THRESHOLDS                                                    0x21d6
++#define mmCP_STQ_THRESHOLDS                                                     0x21d7
++#define mmCP_QUEUE_THRESHOLDS                                                   0x21d8
++#define mmCP_MEQ_THRESHOLDS                                                     0x21d9
++#define mmCP_ROQ_AVAIL                                                          0x21da
++#define mmCP_STQ_AVAIL                                                          0x21db
++#define mmCP_ROQ2_AVAIL                                                         0x21dc
++#define mmCP_MEQ_AVAIL                                                          0x21dd
++#define mmCP_CMD_INDEX                                                          0x21de
++#define mmCP_CMD_DATA                                                           0x21df
++#define mmCP_ROQ_RB_STAT                                                        0x21e0
++#define mmCP_ROQ_IB1_STAT                                                       0x21e1
++#define mmCP_ROQ_IB2_STAT                                                       0x21e2
++#define mmCP_STQ_STAT                                                           0x21e3
++#define mmCP_STQ_WR_STAT                                                        0x21e4
++#define mmCP_MEQ_STAT                                                           0x21e5
++#define mmCP_CEQ1_AVAIL                                                         0x21e6
++#define mmCP_CEQ2_AVAIL                                                         0x21e7
++#define mmCP_CE_ROQ_RB_STAT                                                     0x21e8
++#define mmCP_CE_ROQ_IB1_STAT                                                    0x21e9
++#define mmCP_CE_ROQ_IB2_STAT                                                    0x21ea
++#define mmCP_INT_STAT_DEBUG                                                     0x21f7
++#define mmCP_PERFMON_CNTL                                                       0xd808
++#define mmCP_PERFMON_CNTX_CNTL                                                  0xa0d8
++#define mmCP_RINGID                                                             0xa0d9
++#define mmCP_PIPEID                                                             0xa0d9
++#define mmCP_VMID                                                               0xa0da
++#define mmCP_HPD_ROQ_OFFSETS                                                    0x3240
++#define mmCP_HPD_STATUS0                                                        0x3241
++#define mmCP_MQD_BASE_ADDR                                                      0x3245
++#define mmCP_MQD_BASE_ADDR_HI                                                   0x3246
++#define mmCP_HQD_ACTIVE                                                         0x3247
++#define mmCP_HQD_VMID                                                           0x3248
++#define mmCP_HQD_PERSISTENT_STATE                                               0x3249
++#define mmCP_HQD_PIPE_PRIORITY                                                  0x324a
++#define mmCP_HQD_QUEUE_PRIORITY                                                 0x324b
++#define mmCP_HQD_QUANTUM                                                        0x324c
++#define mmCP_HQD_PQ_BASE                                                        0x324d
++#define mmCP_HQD_PQ_BASE_HI                                                     0x324e
++#define mmCP_HQD_PQ_RPTR                                                        0x324f
++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
++#define mmCP_HQD_PQ_WPTR_POLL_ADDR                                              0x3252
++#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                                           0x3253
++#define mmCP_HQD_PQ_DOORBELL_CONTROL                                            0x3254
++#define mmCP_HQD_PQ_WPTR                                                        0x3255
++#define mmCP_HQD_PQ_CONTROL                                                     0x3256
++#define mmCP_HQD_IB_BASE_ADDR                                                   0x3257
++#define mmCP_HQD_IB_BASE_ADDR_HI                                                0x3258
++#define mmCP_HQD_IB_RPTR                                                        0x3259
++#define mmCP_HQD_IB_CONTROL                                                     0x325a
++#define mmCP_HQD_IQ_TIMER                                                       0x325b
++#define mmCP_HQD_IQ_RPTR                                                        0x325c
++#define mmCP_HQD_DEQUEUE_REQUEST                                                0x325d
++#define mmCP_HQD_DMA_OFFLOAD                                                    0x325e
++#define mmCP_HQD_OFFLOAD                                                        0x325e
++#define mmCP_HQD_SEMA_CMD                                                       0x325f
++#define mmCP_HQD_MSG_TYPE                                                       0x3260
++#define mmCP_HQD_ATOMIC0_PREOP_LO                                               0x3261
++#define mmCP_HQD_ATOMIC0_PREOP_HI                                               0x3262
++#define mmCP_HQD_ATOMIC1_PREOP_LO                                               0x3263
++#define mmCP_HQD_ATOMIC1_PREOP_HI                                               0x3264
++#define mmCP_HQD_HQ_SCHEDULER0                                                  0x3265
++#define mmCP_HQD_HQ_STATUS0                                                     0x3265
++#define mmCP_HQD_HQ_SCHEDULER1                                                  0x3266
++#define mmCP_HQD_HQ_CONTROL0                                                    0x3266
++#define mmCP_MQD_CONTROL                                                        0x3267
++#define mmCP_HQD_HQ_STATUS1                                                     0x3268
++#define mmCP_HQD_HQ_CONTROL1                                                    0x3269
++#define mmCP_HQD_EOP_BASE_ADDR                                                  0x326a
++#define mmCP_HQD_EOP_BASE_ADDR_HI                                               0x326b
++#define mmCP_HQD_EOP_CONTROL                                                    0x326c
++#define mmCP_HQD_EOP_RPTR                                                       0x326d
++#define mmCP_HQD_EOP_WPTR                                                       0x326e
++#define mmCP_HQD_EOP_EVENTS                                                     0x326f
++#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO                                          0x3270
++#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI                                          0x3271
++#define mmCP_HQD_CTX_SAVE_CONTROL                                               0x3272
++#define mmCP_HQD_CNTL_STACK_OFFSET                                              0x3273
++#define mmCP_HQD_CNTL_STACK_SIZE                                                0x3274
++#define mmCP_HQD_WG_STATE_OFFSET                                                0x3275
++#define mmCP_HQD_CTX_SAVE_SIZE                                                  0x3276
++#define mmCP_HQD_GDS_RESOURCE_STATE                                             0x3277
++#define mmCP_HQD_ERROR                                                          0x3278
++#define mmCP_HQD_EOP_WPTR_MEM                                                   0x3279
++#define mmCP_HQD_EOP_DONES                                                      0x327a
++#define mmDB_Z_READ_BASE                                                        0xa012
++#define mmDB_STENCIL_READ_BASE                                                  0xa013
++#define mmDB_Z_WRITE_BASE                                                       0xa014
++#define mmDB_STENCIL_WRITE_BASE                                                 0xa015
++#define mmDB_DEPTH_INFO                                                         0xa00f
++#define mmDB_Z_INFO                                                             0xa010
++#define mmDB_STENCIL_INFO                                                       0xa011
++#define mmDB_DEPTH_SIZE                                                         0xa016
++#define mmDB_DEPTH_SLICE                                                        0xa017
++#define mmDB_DEPTH_VIEW                                                         0xa002
++#define mmDB_RENDER_CONTROL                                                     0xa000
++#define mmDB_COUNT_CONTROL                                                      0xa001
++#define mmDB_RENDER_OVERRIDE                                                    0xa003
++#define mmDB_RENDER_OVERRIDE2                                                   0xa004
++#define mmDB_EQAA                                                               0xa201
++#define mmDB_SHADER_CONTROL                                                     0xa203
++#define mmDB_DEPTH_BOUNDS_MIN                                                   0xa008
++#define mmDB_DEPTH_BOUNDS_MAX                                                   0xa009
++#define mmDB_STENCIL_CLEAR                                                      0xa00a
++#define mmDB_DEPTH_CLEAR                                                        0xa00b
++#define mmDB_HTILE_DATA_BASE                                                    0xa005
++#define mmDB_HTILE_SURFACE                                                      0xa2af
++#define mmDB_PRELOAD_CONTROL                                                    0xa2b2
++#define mmDB_STENCILREFMASK                                                     0xa10c
++#define mmDB_STENCILREFMASK_BF                                                  0xa10d
++#define mmDB_SRESULTS_COMPARE_STATE0                                            0xa2b0
++#define mmDB_SRESULTS_COMPARE_STATE1                                            0xa2b1
++#define mmDB_DEPTH_CONTROL                                                      0xa200
++#define mmDB_STENCIL_CONTROL                                                    0xa10b
++#define mmDB_ALPHA_TO_MASK                                                      0xa2dc
++#define mmDB_PERFCOUNTER0_SELECT                                                0xdc40
++#define mmDB_PERFCOUNTER1_SELECT                                                0xdc42
++#define mmDB_PERFCOUNTER2_SELECT                                                0xdc44
++#define mmDB_PERFCOUNTER3_SELECT                                                0xdc46
++#define mmDB_PERFCOUNTER0_SELECT1                                               0xdc41
++#define mmDB_PERFCOUNTER1_SELECT1                                               0xdc43
++#define mmDB_PERFCOUNTER0_LO                                                    0xd440
++#define mmDB_PERFCOUNTER1_LO                                                    0xd442
++#define mmDB_PERFCOUNTER2_LO                                                    0xd444
++#define mmDB_PERFCOUNTER3_LO                                                    0xd446
++#define mmDB_PERFCOUNTER0_HI                                                    0xd441
++#define mmDB_PERFCOUNTER1_HI                                                    0xd443
++#define mmDB_PERFCOUNTER2_HI                                                    0xd445
++#define mmDB_PERFCOUNTER3_HI                                                    0xd447
++#define mmDB_DEBUG                                                              0x260c
++#define mmDB_DEBUG2                                                             0x260d
++#define mmDB_DEBUG3                                                             0x260e
++#define mmDB_DEBUG4                                                             0x260f
++#define mmDB_CREDIT_LIMIT                                                       0x2614
++#define mmDB_WATERMARKS                                                         0x2615
++#define mmDB_SUBTILE_CONTROL                                                    0x2616
++#define mmDB_FREE_CACHELINES                                                    0x2617
++#define mmDB_FIFO_DEPTH1                                                        0x2618
++#define mmDB_FIFO_DEPTH2                                                        0x2619
++#define mmDB_CGTT_CLK_CTRL_0                                                    0xf0a4
++#define mmDB_ZPASS_COUNT_LOW                                                    0xc3fe
++#define mmDB_ZPASS_COUNT_HI                                                     0xc3ff
++#define mmDB_RING_CONTROL                                                       0x261b
++#define mmDB_READ_DEBUG_0                                                       0x2620
++#define mmDB_READ_DEBUG_1                                                       0x2621
++#define mmDB_READ_DEBUG_2                                                       0x2622
++#define mmDB_READ_DEBUG_3                                                       0x2623
++#define mmDB_READ_DEBUG_4                                                       0x2624
++#define mmDB_READ_DEBUG_5                                                       0x2625
++#define mmDB_READ_DEBUG_6                                                       0x2626
++#define mmDB_READ_DEBUG_7                                                       0x2627
++#define mmDB_READ_DEBUG_8                                                       0x2628
++#define mmDB_READ_DEBUG_9                                                       0x2629
++#define mmDB_READ_DEBUG_A                                                       0x262a
++#define mmDB_READ_DEBUG_B                                                       0x262b
++#define mmDB_READ_DEBUG_C                                                       0x262c
++#define mmDB_READ_DEBUG_D                                                       0x262d
++#define mmDB_READ_DEBUG_E                                                       0x262e
++#define mmDB_READ_DEBUG_F                                                       0x262f
++#define mmDB_OCCLUSION_COUNT0_LOW                                               0xc3c0
++#define mmDB_OCCLUSION_COUNT0_HI                                                0xc3c1
++#define mmDB_OCCLUSION_COUNT1_LOW                                               0xc3c2
++#define mmDB_OCCLUSION_COUNT1_HI                                                0xc3c3
++#define mmDB_OCCLUSION_COUNT2_LOW                                               0xc3c4
++#define mmDB_OCCLUSION_COUNT2_HI                                                0xc3c5
++#define mmDB_OCCLUSION_COUNT3_LOW                                               0xc3c6
++#define mmDB_OCCLUSION_COUNT3_HI                                                0xc3c7
++#define mmCC_RB_REDUNDANCY                                                      0x263c
++#define mmCC_RB_BACKEND_DISABLE                                                 0x263d
++#define mmGC_USER_RB_REDUNDANCY                                                 0x26de
++#define mmGC_USER_RB_BACKEND_DISABLE                                            0x26df
++#define mmGB_ADDR_CONFIG                                                        0x263e
++#define mmGB_BACKEND_MAP                                                        0x263f
++#define mmGB_GPU_ID                                                             0x2640
++#define mmCC_RB_DAISY_CHAIN                                                     0x2641
++#define mmGB_TILE_MODE0                                                         0x2644
++#define mmGB_TILE_MODE1                                                         0x2645
++#define mmGB_TILE_MODE2                                                         0x2646
++#define mmGB_TILE_MODE3                                                         0x2647
++#define mmGB_TILE_MODE4                                                         0x2648
++#define mmGB_TILE_MODE5                                                         0x2649
++#define mmGB_TILE_MODE6                                                         0x264a
++#define mmGB_TILE_MODE7                                                         0x264b
++#define mmGB_TILE_MODE8                                                         0x264c
++#define mmGB_TILE_MODE9                                                         0x264d
++#define mmGB_TILE_MODE10                                                        0x264e
++#define mmGB_TILE_MODE11                                                        0x264f
++#define mmGB_TILE_MODE12                                                        0x2650
++#define mmGB_TILE_MODE13                                                        0x2651
++#define mmGB_TILE_MODE14                                                        0x2652
++#define mmGB_TILE_MODE15                                                        0x2653
++#define mmGB_TILE_MODE16                                                        0x2654
++#define mmGB_TILE_MODE17                                                        0x2655
++#define mmGB_TILE_MODE18                                                        0x2656
++#define mmGB_TILE_MODE19                                                        0x2657
++#define mmGB_TILE_MODE20                                                        0x2658
++#define mmGB_TILE_MODE21                                                        0x2659
++#define mmGB_TILE_MODE22                                                        0x265a
++#define mmGB_TILE_MODE23                                                        0x265b
++#define mmGB_TILE_MODE24                                                        0x265c
++#define mmGB_TILE_MODE25                                                        0x265d
++#define mmGB_TILE_MODE26                                                        0x265e
++#define mmGB_TILE_MODE27                                                        0x265f
++#define mmGB_TILE_MODE28                                                        0x2660
++#define mmGB_TILE_MODE29                                                        0x2661
++#define mmGB_TILE_MODE30                                                        0x2662
++#define mmGB_TILE_MODE31                                                        0x2663
++#define mmGB_MACROTILE_MODE0                                                    0x2664
++#define mmGB_MACROTILE_MODE1                                                    0x2665
++#define mmGB_MACROTILE_MODE2                                                    0x2666
++#define mmGB_MACROTILE_MODE3                                                    0x2667
++#define mmGB_MACROTILE_MODE4                                                    0x2668
++#define mmGB_MACROTILE_MODE5                                                    0x2669
++#define mmGB_MACROTILE_MODE6                                                    0x266a
++#define mmGB_MACROTILE_MODE7                                                    0x266b
++#define mmGB_MACROTILE_MODE8                                                    0x266c
++#define mmGB_MACROTILE_MODE9                                                    0x266d
++#define mmGB_MACROTILE_MODE10                                                   0x266e
++#define mmGB_MACROTILE_MODE11                                                   0x266f
++#define mmGB_MACROTILE_MODE12                                                   0x2670
++#define mmGB_MACROTILE_MODE13                                                   0x2671
++#define mmGB_MACROTILE_MODE14                                                   0x2672
++#define mmGB_MACROTILE_MODE15                                                   0x2673
++#define mmGB_EDC_MODE                                                           0x307e
++#define mmCC_GC_EDC_CONFIG                                                      0x3098
++#define mmRAS_SIGNATURE_CONTROL                                                 0x3380
++#define mmRAS_SIGNATURE_MASK                                                    0x3381
++#define mmRAS_SX_SIGNATURE0                                                     0x3382
++#define mmRAS_SX_SIGNATURE1                                                     0x3383
++#define mmRAS_SX_SIGNATURE2                                                     0x3384
++#define mmRAS_SX_SIGNATURE3                                                     0x3385
++#define mmRAS_DB_SIGNATURE0                                                     0x338b
++#define mmRAS_PA_SIGNATURE0                                                     0x338c
++#define mmRAS_VGT_SIGNATURE0                                                    0x338d
++#define mmRAS_SQ_SIGNATURE0                                                     0x338e
++#define mmRAS_SC_SIGNATURE0                                                     0x338f
++#define mmRAS_SC_SIGNATURE1                                                     0x3390
++#define mmRAS_SC_SIGNATURE2                                                     0x3391
++#define mmRAS_SC_SIGNATURE3                                                     0x3392
++#define mmRAS_SC_SIGNATURE4                                                     0x3393
++#define mmRAS_SC_SIGNATURE5                                                     0x3394
++#define mmRAS_SC_SIGNATURE6                                                     0x3395
++#define mmRAS_SC_SIGNATURE7                                                     0x3396
++#define mmRAS_IA_SIGNATURE0                                                     0x3397
++#define mmRAS_IA_SIGNATURE1                                                     0x3398
++#define mmRAS_SPI_SIGNATURE0                                                    0x3399
++#define mmRAS_SPI_SIGNATURE1                                                    0x339a
++#define mmRAS_TA_SIGNATURE0                                                     0x339b
++#define mmRAS_TD_SIGNATURE0                                                     0x339c
++#define mmRAS_CB_SIGNATURE0                                                     0x339d
++#define mmRAS_BCI_SIGNATURE0                                                    0x339e
++#define mmRAS_BCI_SIGNATURE1                                                    0x339f
++#define mmRAS_TA_SIGNATURE1                                                     0x33a0
++#define mmGRBM_HYP_CAM_INDEX                                                    0xf83e
++#define mmGRBM_CAM_INDEX                                                        0xf83e
++#define mmGRBM_HYP_CAM_DATA                                                     0xf83f
++#define mmGRBM_CAM_DATA                                                         0xf83f
++#define mmGRBM_CNTL                                                             0x2000
++#define mmGRBM_SKEW_CNTL                                                        0x2001
++#define mmGRBM_PWR_CNTL                                                         0x2003
++#define mmGRBM_STATUS                                                           0x2004
++#define mmGRBM_STATUS2                                                          0x2002
++#define mmGRBM_STATUS_SE0                                                       0x2005
++#define mmGRBM_STATUS_SE1                                                       0x2006
++#define mmGRBM_STATUS_SE2                                                       0x200e
++#define mmGRBM_STATUS_SE3                                                       0x200f
++#define mmGRBM_SOFT_RESET                                                       0x2008
++#define mmGRBM_DEBUG_CNTL                                                       0x2009
++#define mmGRBM_DEBUG_DATA                                                       0x200a
++#define mmGRBM_GFX_INDEX                                                        0xc200
++#define mmGRBM_GFX_CLKEN_CNTL                                                   0x200c
++#define mmGRBM_WAIT_IDLE_CLOCKS                                                 0x200d
++#define mmGRBM_DEBUG                                                            0x2014
++#define mmGRBM_DEBUG_SNAPSHOT                                                   0x2015
++#define mmGRBM_READ_ERROR                                                       0x2016
++#define mmGRBM_READ_ERROR2                                                      0x2017
++#define mmGRBM_INT_CNTL                                                         0x2018
++#define mmGRBM_TRAP_OP                                                          0x2019
++#define mmGRBM_TRAP_ADDR                                                        0x201a
++#define mmGRBM_TRAP_ADDR_MSK                                                    0x201b
++#define mmGRBM_TRAP_WD                                                          0x201c
++#define mmGRBM_TRAP_WD_MSK                                                      0x201d
++#define mmGRBM_DSM_BYPASS                                                       0x201e
++#define mmGRBM_WRITE_ERROR                                                      0x201f
++#define mmGRBM_PERFCOUNTER0_SELECT                                              0xd840
++#define mmGRBM_PERFCOUNTER1_SELECT                                              0xd841
++#define mmGRBM_SE0_PERFCOUNTER_SELECT                                           0xd842
++#define mmGRBM_SE1_PERFCOUNTER_SELECT                                           0xd843
++#define mmGRBM_SE2_PERFCOUNTER_SELECT                                           0xd844
++#define mmGRBM_SE3_PERFCOUNTER_SELECT                                           0xd845
++#define mmGRBM_PERFCOUNTER0_LO                                                  0xd040
++#define mmGRBM_PERFCOUNTER0_HI                                                  0xd041
++#define mmGRBM_PERFCOUNTER1_LO                                                  0xd043
++#define mmGRBM_PERFCOUNTER1_HI                                                  0xd044
++#define mmGRBM_SE0_PERFCOUNTER_LO                                               0xd045
++#define mmGRBM_SE0_PERFCOUNTER_HI                                               0xd046
++#define mmGRBM_SE1_PERFCOUNTER_LO                                               0xd047
++#define mmGRBM_SE1_PERFCOUNTER_HI                                               0xd048
++#define mmGRBM_SE2_PERFCOUNTER_LO                                               0xd049
++#define mmGRBM_SE2_PERFCOUNTER_HI                                               0xd04a
++#define mmGRBM_SE3_PERFCOUNTER_LO                                               0xd04b
++#define mmGRBM_SE3_PERFCOUNTER_HI                                               0xd04c
++#define mmGRBM_SCRATCH_REG0                                                     0x2040
++#define mmGRBM_SCRATCH_REG1                                                     0x2041
++#define mmGRBM_SCRATCH_REG2                                                     0x2042
++#define mmGRBM_SCRATCH_REG3                                                     0x2043
++#define mmGRBM_SCRATCH_REG4                                                     0x2044
++#define mmGRBM_SCRATCH_REG5                                                     0x2045
++#define mmGRBM_SCRATCH_REG6                                                     0x2046
++#define mmGRBM_SCRATCH_REG7                                                     0x2047
++#define mmDEBUG_INDEX                                                           0x203c
++#define mmDEBUG_DATA                                                            0x203d
++#define mmGRBM_NOWHERE                                                          0x203f
++#define mmPA_CL_VPORT_XSCALE                                                    0xa10f
++#define mmPA_CL_VPORT_XOFFSET                                                   0xa110
++#define mmPA_CL_VPORT_YSCALE                                                    0xa111
++#define mmPA_CL_VPORT_YOFFSET                                                   0xa112
++#define mmPA_CL_VPORT_ZSCALE                                                    0xa113
++#define mmPA_CL_VPORT_ZOFFSET                                                   0xa114
++#define mmPA_CL_VPORT_XSCALE_1                                                  0xa115
++#define mmPA_CL_VPORT_XSCALE_2                                                  0xa11b
++#define mmPA_CL_VPORT_XSCALE_3                                                  0xa121
++#define mmPA_CL_VPORT_XSCALE_4                                                  0xa127
++#define mmPA_CL_VPORT_XSCALE_5                                                  0xa12d
++#define mmPA_CL_VPORT_XSCALE_6                                                  0xa133
++#define mmPA_CL_VPORT_XSCALE_7                                                  0xa139
++#define mmPA_CL_VPORT_XSCALE_8                                                  0xa13f
++#define mmPA_CL_VPORT_XSCALE_9                                                  0xa145
++#define mmPA_CL_VPORT_XSCALE_10                                                 0xa14b
++#define mmPA_CL_VPORT_XSCALE_11                                                 0xa151
++#define mmPA_CL_VPORT_XSCALE_12                                                 0xa157
++#define mmPA_CL_VPORT_XSCALE_13                                                 0xa15d
++#define mmPA_CL_VPORT_XSCALE_14                                                 0xa163
++#define mmPA_CL_VPORT_XSCALE_15                                                 0xa169
++#define mmPA_CL_VPORT_XOFFSET_1                                                 0xa116
++#define mmPA_CL_VPORT_XOFFSET_2                                                 0xa11c
++#define mmPA_CL_VPORT_XOFFSET_3                                                 0xa122
++#define mmPA_CL_VPORT_XOFFSET_4                                                 0xa128
++#define mmPA_CL_VPORT_XOFFSET_5                                                 0xa12e
++#define mmPA_CL_VPORT_XOFFSET_6                                                 0xa134
++#define mmPA_CL_VPORT_XOFFSET_7                                                 0xa13a
++#define mmPA_CL_VPORT_XOFFSET_8                                                 0xa140
++#define mmPA_CL_VPORT_XOFFSET_9                                                 0xa146
++#define mmPA_CL_VPORT_XOFFSET_10                                                0xa14c
++#define mmPA_CL_VPORT_XOFFSET_11                                                0xa152
++#define mmPA_CL_VPORT_XOFFSET_12                                                0xa158
++#define mmPA_CL_VPORT_XOFFSET_13                                                0xa15e
++#define mmPA_CL_VPORT_XOFFSET_14                                                0xa164
++#define mmPA_CL_VPORT_XOFFSET_15                                                0xa16a
++#define mmPA_CL_VPORT_YSCALE_1                                                  0xa117
++#define mmPA_CL_VPORT_YSCALE_2                                                  0xa11d
++#define mmPA_CL_VPORT_YSCALE_3                                                  0xa123
++#define mmPA_CL_VPORT_YSCALE_4                                                  0xa129
++#define mmPA_CL_VPORT_YSCALE_5                                                  0xa12f
++#define mmPA_CL_VPORT_YSCALE_6                                                  0xa135
++#define mmPA_CL_VPORT_YSCALE_7                                                  0xa13b
++#define mmPA_CL_VPORT_YSCALE_8                                                  0xa141
++#define mmPA_CL_VPORT_YSCALE_9                                                  0xa147
++#define mmPA_CL_VPORT_YSCALE_10                                                 0xa14d
++#define mmPA_CL_VPORT_YSCALE_11                                                 0xa153
++#define mmPA_CL_VPORT_YSCALE_12                                                 0xa159
++#define mmPA_CL_VPORT_YSCALE_13                                                 0xa15f
++#define mmPA_CL_VPORT_YSCALE_14                                                 0xa165
++#define mmPA_CL_VPORT_YSCALE_15                                                 0xa16b
++#define mmPA_CL_VPORT_YOFFSET_1                                                 0xa118
++#define mmPA_CL_VPORT_YOFFSET_2                                                 0xa11e
++#define mmPA_CL_VPORT_YOFFSET_3                                                 0xa124
++#define mmPA_CL_VPORT_YOFFSET_4                                                 0xa12a
++#define mmPA_CL_VPORT_YOFFSET_5                                                 0xa130
++#define mmPA_CL_VPORT_YOFFSET_6                                                 0xa136
++#define mmPA_CL_VPORT_YOFFSET_7                                                 0xa13c
++#define mmPA_CL_VPORT_YOFFSET_8                                                 0xa142
++#define mmPA_CL_VPORT_YOFFSET_9                                                 0xa148
++#define mmPA_CL_VPORT_YOFFSET_10                                                0xa14e
++#define mmPA_CL_VPORT_YOFFSET_11                                                0xa154
++#define mmPA_CL_VPORT_YOFFSET_12                                                0xa15a
++#define mmPA_CL_VPORT_YOFFSET_13                                                0xa160
++#define mmPA_CL_VPORT_YOFFSET_14                                                0xa166
++#define mmPA_CL_VPORT_YOFFSET_15                                                0xa16c
++#define mmPA_CL_VPORT_ZSCALE_1                                                  0xa119
++#define mmPA_CL_VPORT_ZSCALE_2                                                  0xa11f
++#define mmPA_CL_VPORT_ZSCALE_3                                                  0xa125
++#define mmPA_CL_VPORT_ZSCALE_4                                                  0xa12b
++#define mmPA_CL_VPORT_ZSCALE_5                                                  0xa131
++#define mmPA_CL_VPORT_ZSCALE_6                                                  0xa137
++#define mmPA_CL_VPORT_ZSCALE_7                                                  0xa13d
++#define mmPA_CL_VPORT_ZSCALE_8                                                  0xa143
++#define mmPA_CL_VPORT_ZSCALE_9                                                  0xa149
++#define mmPA_CL_VPORT_ZSCALE_10                                                 0xa14f
++#define mmPA_CL_VPORT_ZSCALE_11                                                 0xa155
++#define mmPA_CL_VPORT_ZSCALE_12                                                 0xa15b
++#define mmPA_CL_VPORT_ZSCALE_13                                                 0xa161
++#define mmPA_CL_VPORT_ZSCALE_14                                                 0xa167
++#define mmPA_CL_VPORT_ZSCALE_15                                                 0xa16d
++#define mmPA_CL_VPORT_ZOFFSET_1                                                 0xa11a
++#define mmPA_CL_VPORT_ZOFFSET_2                                                 0xa120
++#define mmPA_CL_VPORT_ZOFFSET_3                                                 0xa126
++#define mmPA_CL_VPORT_ZOFFSET_4                                                 0xa12c
++#define mmPA_CL_VPORT_ZOFFSET_5                                                 0xa132
++#define mmPA_CL_VPORT_ZOFFSET_6                                                 0xa138
++#define mmPA_CL_VPORT_ZOFFSET_7                                                 0xa13e
++#define mmPA_CL_VPORT_ZOFFSET_8                                                 0xa144
++#define mmPA_CL_VPORT_ZOFFSET_9                                                 0xa14a
++#define mmPA_CL_VPORT_ZOFFSET_10                                                0xa150
++#define mmPA_CL_VPORT_ZOFFSET_11                                                0xa156
++#define mmPA_CL_VPORT_ZOFFSET_12                                                0xa15c
++#define mmPA_CL_VPORT_ZOFFSET_13                                                0xa162
++#define mmPA_CL_VPORT_ZOFFSET_14                                                0xa168
++#define mmPA_CL_VPORT_ZOFFSET_15                                                0xa16e
++#define mmPA_CL_VTE_CNTL                                                        0xa206
++#define mmPA_CL_VS_OUT_CNTL                                                     0xa207
++#define mmPA_CL_NANINF_CNTL                                                     0xa208
++#define mmPA_CL_CLIP_CNTL                                                       0xa204
++#define mmPA_CL_GB_VERT_CLIP_ADJ                                                0xa2fa
++#define mmPA_CL_GB_VERT_DISC_ADJ                                                0xa2fb
++#define mmPA_CL_GB_HORZ_CLIP_ADJ                                                0xa2fc
++#define mmPA_CL_GB_HORZ_DISC_ADJ                                                0xa2fd
++#define mmPA_CL_UCP_0_X                                                         0xa16f
++#define mmPA_CL_UCP_0_Y                                                         0xa170
++#define mmPA_CL_UCP_0_Z                                                         0xa171
++#define mmPA_CL_UCP_0_W                                                         0xa172
++#define mmPA_CL_UCP_1_X                                                         0xa173
++#define mmPA_CL_UCP_1_Y                                                         0xa174
++#define mmPA_CL_UCP_1_Z                                                         0xa175
++#define mmPA_CL_UCP_1_W                                                         0xa176
++#define mmPA_CL_UCP_2_X                                                         0xa177
++#define mmPA_CL_UCP_2_Y                                                         0xa178
++#define mmPA_CL_UCP_2_Z                                                         0xa179
++#define mmPA_CL_UCP_2_W                                                         0xa17a
++#define mmPA_CL_UCP_3_X                                                         0xa17b
++#define mmPA_CL_UCP_3_Y                                                         0xa17c
++#define mmPA_CL_UCP_3_Z                                                         0xa17d
++#define mmPA_CL_UCP_3_W                                                         0xa17e
++#define mmPA_CL_UCP_4_X                                                         0xa17f
++#define mmPA_CL_UCP_4_Y                                                         0xa180
++#define mmPA_CL_UCP_4_Z                                                         0xa181
++#define mmPA_CL_UCP_4_W                                                         0xa182
++#define mmPA_CL_UCP_5_X                                                         0xa183
++#define mmPA_CL_UCP_5_Y                                                         0xa184
++#define mmPA_CL_UCP_5_Z                                                         0xa185
++#define mmPA_CL_UCP_5_W                                                         0xa186
++#define mmPA_CL_POINT_X_RAD                                                     0xa1f5
++#define mmPA_CL_POINT_Y_RAD                                                     0xa1f6
++#define mmPA_CL_POINT_SIZE                                                      0xa1f7
++#define mmPA_CL_POINT_CULL_RAD                                                  0xa1f8
++#define mmPA_CL_ENHANCE                                                         0x2285
++#define mmPA_CL_RESET_DEBUG                                                     0x2286
++#define mmPA_SU_VTX_CNTL                                                        0xa2f9
++#define mmPA_SU_POINT_SIZE                                                      0xa280
++#define mmPA_SU_POINT_MINMAX                                                    0xa281
++#define mmPA_SU_LINE_CNTL                                                       0xa282
++#define mmPA_SU_LINE_STIPPLE_CNTL                                               0xa209
++#define mmPA_SU_LINE_STIPPLE_SCALE                                              0xa20a
++#define mmPA_SU_PRIM_FILTER_CNTL                                                0xa20b
++#define mmPA_SU_SC_MODE_CNTL                                                    0xa205
++#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                                         0xa2de
++#define mmPA_SU_POLY_OFFSET_CLAMP                                               0xa2df
++#define mmPA_SU_POLY_OFFSET_FRONT_SCALE                                         0xa2e0
++#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                                        0xa2e1
++#define mmPA_SU_POLY_OFFSET_BACK_SCALE                                          0xa2e2
++#define mmPA_SU_POLY_OFFSET_BACK_OFFSET                                         0xa2e3
++#define mmPA_SU_HARDWARE_SCREEN_OFFSET                                          0xa08d
++#define mmPA_SU_LINE_STIPPLE_VALUE                                              0xc280
++#define mmPA_SU_PERFCOUNTER0_SELECT                                             0xd900
++#define mmPA_SU_PERFCOUNTER0_SELECT1                                            0xd901
++#define mmPA_SU_PERFCOUNTER1_SELECT                                             0xd902
++#define mmPA_SU_PERFCOUNTER1_SELECT1                                            0xd903
++#define mmPA_SU_PERFCOUNTER2_SELECT                                             0xd904
++#define mmPA_SU_PERFCOUNTER3_SELECT                                             0xd905
++#define mmPA_SU_PERFCOUNTER0_LO                                                 0xd100
++#define mmPA_SU_PERFCOUNTER0_HI                                                 0xd101
++#define mmPA_SU_PERFCOUNTER1_LO                                                 0xd102
++#define mmPA_SU_PERFCOUNTER1_HI                                                 0xd103
++#define mmPA_SU_PERFCOUNTER2_LO                                                 0xd104
++#define mmPA_SU_PERFCOUNTER2_HI                                                 0xd105
++#define mmPA_SU_PERFCOUNTER3_LO                                                 0xd106
++#define mmPA_SU_PERFCOUNTER3_HI                                                 0xd107
++#define mmPA_SC_AA_CONFIG                                                       0xa2f8
++#define mmPA_SC_AA_MASK_X0Y0_X1Y0                                               0xa30e
++#define mmPA_SC_AA_MASK_X0Y1_X1Y1                                               0xa30f
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                     0xa2fe
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                     0xa2ff
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                     0xa300
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                     0xa301
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                     0xa302
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                     0xa303
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                     0xa304
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                     0xa305
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                     0xa306
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                     0xa307
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                     0xa308
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                     0xa309
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                     0xa30a
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                     0xa30b
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                     0xa30c
++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                     0xa30d
++#define mmPA_SC_CENTROID_PRIORITY_0                                             0xa2f5
++#define mmPA_SC_CENTROID_PRIORITY_1                                             0xa2f6
++#define mmPA_SC_CLIPRECT_0_TL                                                   0xa084
++#define mmPA_SC_CLIPRECT_0_BR                                                   0xa085
++#define mmPA_SC_CLIPRECT_1_TL                                                   0xa086
++#define mmPA_SC_CLIPRECT_1_BR                                                   0xa087
++#define mmPA_SC_CLIPRECT_2_TL                                                   0xa088
++#define mmPA_SC_CLIPRECT_2_BR                                                   0xa089
++#define mmPA_SC_CLIPRECT_3_TL                                                   0xa08a
++#define mmPA_SC_CLIPRECT_3_BR                                                   0xa08b
++#define mmPA_SC_CLIPRECT_RULE                                                   0xa083
++#define mmPA_SC_EDGERULE                                                        0xa08c
++#define mmPA_SC_LINE_CNTL                                                       0xa2f7
++#define mmPA_SC_LINE_STIPPLE                                                    0xa283
++#define mmPA_SC_MODE_CNTL_0                                                     0xa292
++#define mmPA_SC_MODE_CNTL_1                                                     0xa293
++#define mmPA_SC_RASTER_CONFIG                                                   0xa0d4
++#define mmPA_SC_RASTER_CONFIG_1                                                 0xa0d5
++#define mmPA_SC_SCREEN_EXTENT_CONTROL                                           0xa0d6
++#define mmPA_SC_GENERIC_SCISSOR_TL                                              0xa090
++#define mmPA_SC_GENERIC_SCISSOR_BR                                              0xa091
++#define mmPA_SC_SCREEN_SCISSOR_TL                                               0xa00c
++#define mmPA_SC_SCREEN_SCISSOR_BR                                               0xa00d
++#define mmPA_SC_WINDOW_OFFSET                                                   0xa080
++#define mmPA_SC_WINDOW_SCISSOR_TL                                               0xa081
++#define mmPA_SC_WINDOW_SCISSOR_BR                                               0xa082
++#define mmPA_SC_VPORT_SCISSOR_0_TL                                              0xa094
++#define mmPA_SC_VPORT_SCISSOR_1_TL                                              0xa096
++#define mmPA_SC_VPORT_SCISSOR_2_TL                                              0xa098
++#define mmPA_SC_VPORT_SCISSOR_3_TL                                              0xa09a
++#define mmPA_SC_VPORT_SCISSOR_4_TL                                              0xa09c
++#define mmPA_SC_VPORT_SCISSOR_5_TL                                              0xa09e
++#define mmPA_SC_VPORT_SCISSOR_6_TL                                              0xa0a0
++#define mmPA_SC_VPORT_SCISSOR_7_TL                                              0xa0a2
++#define mmPA_SC_VPORT_SCISSOR_8_TL                                              0xa0a4
++#define mmPA_SC_VPORT_SCISSOR_9_TL                                              0xa0a6
++#define mmPA_SC_VPORT_SCISSOR_10_TL                                             0xa0a8
++#define mmPA_SC_VPORT_SCISSOR_11_TL                                             0xa0aa
++#define mmPA_SC_VPORT_SCISSOR_12_TL                                             0xa0ac
++#define mmPA_SC_VPORT_SCISSOR_13_TL                                             0xa0ae
++#define mmPA_SC_VPORT_SCISSOR_14_TL                                             0xa0b0
++#define mmPA_SC_VPORT_SCISSOR_15_TL                                             0xa0b2
++#define mmPA_SC_VPORT_SCISSOR_0_BR                                              0xa095
++#define mmPA_SC_VPORT_SCISSOR_1_BR                                              0xa097
++#define mmPA_SC_VPORT_SCISSOR_2_BR                                              0xa099
++#define mmPA_SC_VPORT_SCISSOR_3_BR                                              0xa09b
++#define mmPA_SC_VPORT_SCISSOR_4_BR                                              0xa09d
++#define mmPA_SC_VPORT_SCISSOR_5_BR                                              0xa09f
++#define mmPA_SC_VPORT_SCISSOR_6_BR                                              0xa0a1
++#define mmPA_SC_VPORT_SCISSOR_7_BR                                              0xa0a3
++#define mmPA_SC_VPORT_SCISSOR_8_BR                                              0xa0a5
++#define mmPA_SC_VPORT_SCISSOR_9_BR                                              0xa0a7
++#define mmPA_SC_VPORT_SCISSOR_10_BR                                             0xa0a9
++#define mmPA_SC_VPORT_SCISSOR_11_BR                                             0xa0ab
++#define mmPA_SC_VPORT_SCISSOR_12_BR                                             0xa0ad
++#define mmPA_SC_VPORT_SCISSOR_13_BR                                             0xa0af
++#define mmPA_SC_VPORT_SCISSOR_14_BR                                             0xa0b1
++#define mmPA_SC_VPORT_SCISSOR_15_BR                                             0xa0b3
++#define mmPA_SC_VPORT_ZMIN_0                                                    0xa0b4
++#define mmPA_SC_VPORT_ZMIN_1                                                    0xa0b6
++#define mmPA_SC_VPORT_ZMIN_2                                                    0xa0b8
++#define mmPA_SC_VPORT_ZMIN_3                                                    0xa0ba
++#define mmPA_SC_VPORT_ZMIN_4                                                    0xa0bc
++#define mmPA_SC_VPORT_ZMIN_5                                                    0xa0be
++#define mmPA_SC_VPORT_ZMIN_6                                                    0xa0c0
++#define mmPA_SC_VPORT_ZMIN_7                                                    0xa0c2
++#define mmPA_SC_VPORT_ZMIN_8                                                    0xa0c4
++#define mmPA_SC_VPORT_ZMIN_9                                                    0xa0c6
++#define mmPA_SC_VPORT_ZMIN_10                                                   0xa0c8
++#define mmPA_SC_VPORT_ZMIN_11                                                   0xa0ca
++#define mmPA_SC_VPORT_ZMIN_12                                                   0xa0cc
++#define mmPA_SC_VPORT_ZMIN_13                                                   0xa0ce
++#define mmPA_SC_VPORT_ZMIN_14                                                   0xa0d0
++#define mmPA_SC_VPORT_ZMIN_15                                                   0xa0d2
++#define mmPA_SC_VPORT_ZMAX_0                                                    0xa0b5
++#define mmPA_SC_VPORT_ZMAX_1                                                    0xa0b7
++#define mmPA_SC_VPORT_ZMAX_2                                                    0xa0b9
++#define mmPA_SC_VPORT_ZMAX_3                                                    0xa0bb
++#define mmPA_SC_VPORT_ZMAX_4                                                    0xa0bd
++#define mmPA_SC_VPORT_ZMAX_5                                                    0xa0bf
++#define mmPA_SC_VPORT_ZMAX_6                                                    0xa0c1
++#define mmPA_SC_VPORT_ZMAX_7                                                    0xa0c3
++#define mmPA_SC_VPORT_ZMAX_8                                                    0xa0c5
++#define mmPA_SC_VPORT_ZMAX_9                                                    0xa0c7
++#define mmPA_SC_VPORT_ZMAX_10                                                   0xa0c9
++#define mmPA_SC_VPORT_ZMAX_11                                                   0xa0cb
++#define mmPA_SC_VPORT_ZMAX_12                                                   0xa0cd
++#define mmPA_SC_VPORT_ZMAX_13                                                   0xa0cf
++#define mmPA_SC_VPORT_ZMAX_14                                                   0xa0d1
++#define mmPA_SC_VPORT_ZMAX_15                                                   0xa0d3
++#define mmPA_SC_ENHANCE                                                         0x22fc
++#define mmPA_SC_FIFO_SIZE                                                       0x22f3
++#define mmPA_SC_IF_FIFO_SIZE                                                    0x22f5
++#define mmPA_SC_FORCE_EOV_MAX_CNTS                                              0x22c9
++#define mmPA_SC_LINE_STIPPLE_STATE                                              0xc281
++#define mmPA_SC_SCREEN_EXTENT_MIN_0                                             0xc284
++#define mmPA_SC_SCREEN_EXTENT_MAX_0                                             0xc285
++#define mmPA_SC_SCREEN_EXTENT_MIN_1                                             0xc286
++#define mmPA_SC_SCREEN_EXTENT_MAX_1                                             0xc28b
++#define mmPA_SC_PERFCOUNTER0_SELECT                                             0xd940
++#define mmPA_SC_PERFCOUNTER0_SELECT1                                            0xd941
++#define mmPA_SC_PERFCOUNTER1_SELECT                                             0xd942
++#define mmPA_SC_PERFCOUNTER2_SELECT                                             0xd943
++#define mmPA_SC_PERFCOUNTER3_SELECT                                             0xd944
++#define mmPA_SC_PERFCOUNTER4_SELECT                                             0xd945
++#define mmPA_SC_PERFCOUNTER5_SELECT                                             0xd946
++#define mmPA_SC_PERFCOUNTER6_SELECT                                             0xd947
++#define mmPA_SC_PERFCOUNTER7_SELECT                                             0xd948
++#define mmPA_SC_PERFCOUNTER0_LO                                                 0xd140
++#define mmPA_SC_PERFCOUNTER0_HI                                                 0xd141
++#define mmPA_SC_PERFCOUNTER1_LO                                                 0xd142
++#define mmPA_SC_PERFCOUNTER1_HI                                                 0xd143
++#define mmPA_SC_PERFCOUNTER2_LO                                                 0xd144
++#define mmPA_SC_PERFCOUNTER2_HI                                                 0xd145
++#define mmPA_SC_PERFCOUNTER3_LO                                                 0xd146
++#define mmPA_SC_PERFCOUNTER3_HI                                                 0xd147
++#define mmPA_SC_PERFCOUNTER4_LO                                                 0xd148
++#define mmPA_SC_PERFCOUNTER4_HI                                                 0xd149
++#define mmPA_SC_PERFCOUNTER5_LO                                                 0xd14a
++#define mmPA_SC_PERFCOUNTER5_HI                                                 0xd14b
++#define mmPA_SC_PERFCOUNTER6_LO                                                 0xd14c
++#define mmPA_SC_PERFCOUNTER6_HI                                                 0xd14d
++#define mmPA_SC_PERFCOUNTER7_LO                                                 0xd14e
++#define mmPA_SC_PERFCOUNTER7_HI                                                 0xd14f
++#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN                                           0xc2a0
++#define mmPA_SC_P3D_TRAP_SCREEN_H                                               0xc2a1
++#define mmPA_SC_P3D_TRAP_SCREEN_V                                               0xc2a2
++#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                      0xc2a3
++#define mmPA_SC_P3D_TRAP_SCREEN_COUNT                                           0xc2a4
++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                                          0xc2a8
++#define mmPA_SC_HP3D_TRAP_SCREEN_H                                              0xc2a9
++#define mmPA_SC_HP3D_TRAP_SCREEN_V                                              0xc2aa
++#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                     0xc2ab
++#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT                                          0xc2ac
++#define mmPA_SC_TRAP_SCREEN_HV_EN                                               0xc2b0
++#define mmPA_SC_TRAP_SCREEN_H                                                   0xc2b1
++#define mmPA_SC_TRAP_SCREEN_V                                                   0xc2b2
++#define mmPA_SC_TRAP_SCREEN_OCCURRENCE                                          0xc2b3
++#define mmPA_SC_TRAP_SCREEN_COUNT                                               0xc2b4
++#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                         0x22c0
++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                        0x22c1
++#define mmPA_SC_TRAP_SCREEN_HV_LOCK                                             0x22c2
++#define mmPA_CL_CNTL_STATUS                                                     0x2284
++#define mmPA_SU_CNTL_STATUS                                                     0x2294
++#define mmPA_SC_FIFO_DEPTH_CNTL                                                 0x2295
++#define mmCGTT_PA_CLK_CTRL                                                      0xf088
++#define mmCGTT_SC_CLK_CTRL                                                      0xf089
++#define mmPA_SU_DEBUG_CNTL                                                      0x2280
++#define mmPA_SU_DEBUG_DATA                                                      0x2281
++#define mmPA_SC_DEBUG_CNTL                                                      0x22f6
++#define mmPA_SC_DEBUG_DATA                                                      0x22f7
++#define ixCLIPPER_DEBUG_REG00                                                   0x0
++#define ixCLIPPER_DEBUG_REG01                                                   0x1
++#define ixCLIPPER_DEBUG_REG02                                                   0x2
++#define ixCLIPPER_DEBUG_REG03                                                   0x3
++#define ixCLIPPER_DEBUG_REG04                                                   0x4
++#define ixCLIPPER_DEBUG_REG05                                                   0x5
++#define ixCLIPPER_DEBUG_REG06                                                   0x6
++#define ixCLIPPER_DEBUG_REG07                                                   0x7
++#define ixCLIPPER_DEBUG_REG08                                                   0x8
++#define ixCLIPPER_DEBUG_REG09                                                   0x9
++#define ixCLIPPER_DEBUG_REG10                                                   0xa
++#define ixCLIPPER_DEBUG_REG11                                                   0xb
++#define ixCLIPPER_DEBUG_REG12                                                   0xc
++#define ixCLIPPER_DEBUG_REG13                                                   0xd
++#define ixCLIPPER_DEBUG_REG14                                                   0xe
++#define ixCLIPPER_DEBUG_REG15                                                   0xf
++#define ixCLIPPER_DEBUG_REG16                                                   0x10
++#define ixCLIPPER_DEBUG_REG17                                                   0x11
++#define ixCLIPPER_DEBUG_REG18                                                   0x12
++#define ixCLIPPER_DEBUG_REG19                                                   0x13
++#define ixSXIFCCG_DEBUG_REG0                                                    0x14
++#define ixSXIFCCG_DEBUG_REG1                                                    0x15
++#define ixSXIFCCG_DEBUG_REG2                                                    0x16
++#define ixSXIFCCG_DEBUG_REG3                                                    0x17
++#define ixSETUP_DEBUG_REG0                                                      0x18
++#define ixSETUP_DEBUG_REG1                                                      0x19
++#define ixSETUP_DEBUG_REG2                                                      0x1a
++#define ixSETUP_DEBUG_REG3                                                      0x1b
++#define ixSETUP_DEBUG_REG4                                                      0x1c
++#define ixSETUP_DEBUG_REG5                                                      0x1d
++#define ixPA_SC_DEBUG_REG0                                                      0x0
++#define ixPA_SC_DEBUG_REG1                                                      0x1
++#define mmCOMPUTE_DISPATCH_INITIATOR                                            0x2e00
++#define mmCOMPUTE_DIM_X                                                         0x2e01
++#define mmCOMPUTE_DIM_Y                                                         0x2e02
++#define mmCOMPUTE_DIM_Z                                                         0x2e03
++#define mmCOMPUTE_START_X                                                       0x2e04
++#define mmCOMPUTE_START_Y                                                       0x2e05
++#define mmCOMPUTE_START_Z                                                       0x2e06
++#define mmCOMPUTE_NUM_THREAD_X                                                  0x2e07
++#define mmCOMPUTE_NUM_THREAD_Y                                                  0x2e08
++#define mmCOMPUTE_NUM_THREAD_Z                                                  0x2e09
++#define mmCOMPUTE_PIPELINESTAT_ENABLE                                           0x2e0a
++#define mmCOMPUTE_PERFCOUNT_ENABLE                                              0x2e0b
++#define mmCOMPUTE_PGM_LO                                                        0x2e0c
++#define mmCOMPUTE_PGM_HI                                                        0x2e0d
++#define mmCOMPUTE_TBA_LO                                                        0x2e0e
++#define mmCOMPUTE_TBA_HI                                                        0x2e0f
++#define mmCOMPUTE_TMA_LO                                                        0x2e10
++#define mmCOMPUTE_TMA_HI                                                        0x2e11
++#define mmCOMPUTE_PGM_RSRC1                                                     0x2e12
++#define mmCOMPUTE_PGM_RSRC2                                                     0x2e13
++#define mmCOMPUTE_VMID                                                          0x2e14
++#define mmCOMPUTE_RESOURCE_LIMITS                                               0x2e15
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                                        0x2e16
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                                        0x2e17
++#define mmCOMPUTE_TMPRING_SIZE                                                  0x2e18
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2                                        0x2e19
++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3                                        0x2e1a
++#define mmCOMPUTE_RESTART_X                                                     0x2e1b
++#define mmCOMPUTE_RESTART_Y                                                     0x2e1c
++#define mmCOMPUTE_RESTART_Z                                                     0x2e1d
++#define mmCOMPUTE_THREAD_TRACE_ENABLE                                           0x2e1e
++#define mmCOMPUTE_MISC_RESERVED                                                 0x2e1f
++#define mmCOMPUTE_DISPATCH_ID                                                   0x2e20
++#define mmCOMPUTE_THREADGROUP_ID                                                0x2e21
++#define mmCOMPUTE_RELAUNCH                                                      0x2e22
++#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO                                          0x2e23
++#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI                                          0x2e24
++#define mmCOMPUTE_WAVE_RESTORE_CONTROL                                          0x2e25
++#define mmCOMPUTE_USER_DATA_0                                                   0x2e40
++#define mmCOMPUTE_USER_DATA_1                                                   0x2e41
++#define mmCOMPUTE_USER_DATA_2                                                   0x2e42
++#define mmCOMPUTE_USER_DATA_3                                                   0x2e43
++#define mmCOMPUTE_USER_DATA_4                                                   0x2e44
++#define mmCOMPUTE_USER_DATA_5                                                   0x2e45
++#define mmCOMPUTE_USER_DATA_6                                                   0x2e46
++#define mmCOMPUTE_USER_DATA_7                                                   0x2e47
++#define mmCOMPUTE_USER_DATA_8                                                   0x2e48
++#define mmCOMPUTE_USER_DATA_9                                                   0x2e49
++#define mmCOMPUTE_USER_DATA_10                                                  0x2e4a
++#define mmCOMPUTE_USER_DATA_11                                                  0x2e4b
++#define mmCOMPUTE_USER_DATA_12                                                  0x2e4c
++#define mmCOMPUTE_USER_DATA_13                                                  0x2e4d
++#define mmCOMPUTE_USER_DATA_14                                                  0x2e4e
++#define mmCOMPUTE_USER_DATA_15                                                  0x2e4f
++#define mmCOMPUTE_NOWHERE                                                       0x2e7f
++#define mmCSPRIV_CONNECT                                                        0x0
++#define mmCSPRIV_THREAD_TRACE_TG0                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG1                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG2                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_TG3                                               0x1e
++#define mmCSPRIV_THREAD_TRACE_EVENT                                             0x1f
++#define mmRLC_CNTL                                                              0xec00
++#define mmRLC_DEBUG_SELECT                                                      0xec01
++#define mmRLC_DEBUG                                                             0xec02
++#define mmRLC_MC_CNTL                                                           0xec03
++#define mmRLC_STAT                                                              0xec04
++#define mmRLC_SAFE_MODE                                                         0xec05
++#define mmRLC_SOFT_RESET_GPU                                                    0xec05
++#define mmRLC_MEM_SLP_CNTL                                                      0xec06
++#define mmSMU_RLC_RESPONSE                                                      0xec07
++#define mmRLC_RLCV_SAFE_MODE                                                    0xec08
++#define mmRLC_SMU_SAFE_MODE                                                     0xec09
++#define mmRLC_RLCV_COMMAND                                                      0xec0a
++#define mmRLC_PERFMON_CLK_CNTL                                                  0xdcbf
++#define mmRLC_PERFMON_CNTL                                                      0xdcc0
++#define mmRLC_PERFCOUNTER0_SELECT                                               0xdcc1
++#define mmRLC_PERFCOUNTER1_SELECT                                               0xdcc2
++#define mmRLC_PERFCOUNTER0_LO                                                   0xd480
++#define mmRLC_PERFCOUNTER1_LO                                                   0xd482
++#define mmRLC_PERFCOUNTER0_HI                                                   0xd481
++#define mmRLC_PERFCOUNTER1_HI                                                   0xd483
++#define mmCGTT_RLC_CLK_CTRL                                                     0xf0b8
++#define mmRLC_LB_CNTL                                                           0xec19
++#define mmRLC_LB_CNTR_MAX                                                       0xec12
++#define mmRLC_LB_CNTR_INIT                                                      0xec1b
++#define mmRLC_LOAD_BALANCE_CNTR                                                 0xec1c
++#define mmRLC_SAVE_AND_RESTORE_BASE                                             0xec1d
++#define mmRLC_JUMP_TABLE_RESTORE                                                0xec1e
++#define mmRLC_DRIVER_CPDMA_STATUS                                               0xec1e
++#define mmRLC_PG_DELAY_2                                                        0xec1f
++#define mmRLC_GPM_DEBUG_SELECT                                                  0xec20
++#define mmRLC_GPM_DEBUG                                                         0xec21
++#define mmRLC_HYP_GPM_UCODE_ADDR                                                0xf83c
++#define mmRLC_GPM_UCODE_ADDR                                                    0xf83c
++#define mmRLC_HYP_GPM_UCODE_DATA                                                0xf83d
++#define mmRLC_GPM_UCODE_DATA                                                    0xf83d
++#define mmGPU_BIST_CONTROL                                                      0xf835
++#define mmRLC_ROM_CNTL                                                          0xf836
++#define mmRLC_GPU_CLOCK_COUNT_LSB                                               0xec24
++#define mmRLC_GPU_CLOCK_COUNT_MSB                                               0xec25
++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT                                           0xec26
++#define mmRLC_UCODE_CNTL                                                        0xec27
++#define mmRLC_GPM_STAT                                                          0xec40
++#define mmRLC_GPU_CLOCK_32_RES_SEL                                              0xec41
++#define mmRLC_GPU_CLOCK_32                                                      0xec42
++#define mmRLC_PG_CNTL                                                           0xec43
++#define mmRLC_GPM_THREAD_PRIORITY                                               0xec44
++#define mmRLC_GPM_THREAD_ENABLE                                                 0xec45
++#define mmRLC_GPM_VMID_THREAD0                                                  0xec46
++#define mmRLC_GPM_VMID_THREAD1                                                  0xec47
++#define mmRLC_CGTT_MGCG_OVERRIDE                                                0xec48
++#define mmRLC_CGCG_CGLS_CTRL                                                    0xec49
++#define mmRLC_CGCG_RAMP_CTRL                                                    0xec4a
++#define mmRLC_DYN_PG_STATUS                                                     0xec4b
++#define mmRLC_DYN_PG_REQUEST                                                    0xec4c
++#define mmRLC_PG_DELAY                                                          0xec4d
++#define mmRLC_CU_STATUS                                                         0xec4e
++#define mmRLC_LB_INIT_CU_MASK                                                   0xec4f
++#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK                                          0xec50
++#define mmRLC_LB_PARAMS                                                         0xec51
++#define mmRLC_THREAD1_DELAY                                                     0xec52
++#define mmRLC_PG_ALWAYS_ON_CU_MASK                                              0xec53
++#define mmRLC_MAX_PG_CU                                                         0xec54
++#define mmRLC_AUTO_PG_CTRL                                                      0xec55
++#define mmRLC_SMU_GRBM_REG_SAVE_CTRL                                            0xec56
++#define mmRLC_SMU_PG_CTRL                                                       0xec57
++#define mmRLC_SMU_PG_WAKE_UP_CTRL                                               0xec58
++#define mmRLC_SERDES_RD_MASTER_INDEX                                            0xec59
++#define mmRLC_SERDES_RD_DATA_0                                                  0xec5a
++#define mmRLC_SERDES_RD_DATA_1                                                  0xec5b
++#define mmRLC_SERDES_RD_DATA_2                                                  0xec5c
++#define mmRLC_SERDES_WR_CU_MASTER_MASK                                          0xec5d
++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK                                       0xec5e
++#define mmRLC_SERDES_WR_CTRL                                                    0xec5f
++#define mmRLC_SERDES_WR_DATA                                                    0xec60
++#define mmRLC_SERDES_CU_MASTER_BUSY                                             0xec61
++#define mmRLC_SERDES_NONCU_MASTER_BUSY                                          0xec62
++#define mmRLC_GPM_GENERAL_0                                                     0xec63
++#define mmRLC_GPM_GENERAL_1                                                     0xec64
++#define mmRLC_GPM_GENERAL_2                                                     0xec65
++#define mmRLC_GPM_GENERAL_3                                                     0xec66
++#define mmRLC_GPM_GENERAL_4                                                     0xec67
++#define mmRLC_GPM_GENERAL_5                                                     0xec68
++#define mmRLC_GPM_GENERAL_6                                                     0xec69
++#define mmRLC_GPM_GENERAL_7                                                     0xec6a
++#define mmRLC_GPM_CU_PD_TIMEOUT                                                 0xec6b
++#define mmRLC_GPM_SCRATCH_ADDR                                                  0xec6c
++#define mmRLC_GPM_SCRATCH_DATA                                                  0xec6d
++#define mmRLC_STATIC_PG_STATUS                                                  0xec6e
++#define mmRLC_GPM_PERF_COUNT_0                                                  0xec6f
++#define mmRLC_GPM_PERF_COUNT_1                                                  0xec70
++#define mmRLC_GPR_REG1                                                          0xec79
++#define mmRLC_GPR_REG2                                                          0xec7a
++#define mmRLC_MGCG_CTRL                                                         0xec1a
++#define mmRLC_GPM_THREAD_RESET                                                  0xec28
++#define mmRLC_SPM_VMID                                                          0xec71
++#define mmRLC_SPM_INT_CNTL                                                      0xec72
++#define mmRLC_SPM_INT_STATUS                                                    0xec73
++#define mmRLC_SPM_DEBUG_SELECT                                                  0xec74
++#define mmRLC_SPM_DEBUG                                                         0xec75
++#define mmRLC_GPM_LOG_ADDR                                                      0xec76
++#define mmRLC_SMU_MESSAGE                                                       0xec76
++#define mmRLC_GPM_LOG_SIZE                                                      0xec77
++#define mmRLC_GPM_LOG_CONT                                                      0xec7b
++#define mmRLC_PG_DELAY_3                                                        0xec78
++#define mmRLC_GPM_INT_DISABLE_TH0                                               0xec7c
++#define mmRLC_GPM_INT_DISABLE_TH1                                               0xec7d
++#define mmRLC_GPM_INT_FORCE_TH0                                                 0xec7e
++#define mmRLC_GPM_INT_FORCE_TH1                                                 0xec7f
++#define mmRLC_SRM_CNTL                                                          0xec80
++#define mmRLC_SRM_DEBUG_SELECT                                                  0xec81
++#define mmRLC_SRM_DEBUG                                                         0xec82
++#define mmRLC_SRM_ARAM_ADDR                                                     0xec83
++#define mmRLC_SRM_ARAM_DATA                                                     0xec84
++#define mmRLC_SRM_DRAM_ADDR                                                     0xec85
++#define mmRLC_SRM_DRAM_DATA                                                     0xec86
++#define mmRLC_SRM_GPM_COMMAND                                                   0xec87
++#define mmRLC_SRM_GPM_COMMAND_STATUS                                            0xec88
++#define mmRLC_SRM_RLCV_COMMAND                                                  0xec89
++#define mmRLC_SRM_RLCV_COMMAND_STATUS                                           0xec8a
++#define mmRLC_SRM_INDEX_CNTL_ADDR_0                                             0xec8b
++#define mmRLC_SRM_INDEX_CNTL_ADDR_1                                             0xec8c
++#define mmRLC_SRM_INDEX_CNTL_ADDR_2                                             0xec8d
++#define mmRLC_SRM_INDEX_CNTL_ADDR_3                                             0xec8e
++#define mmRLC_SRM_INDEX_CNTL_ADDR_4                                             0xec8f
++#define mmRLC_SRM_INDEX_CNTL_ADDR_5                                             0xec90
++#define mmRLC_SRM_INDEX_CNTL_ADDR_6                                             0xec91
++#define mmRLC_SRM_INDEX_CNTL_ADDR_7                                             0xec92
++#define mmRLC_SRM_INDEX_CNTL_DATA_0                                             0xec93
++#define mmRLC_SRM_INDEX_CNTL_DATA_1                                             0xec94
++#define mmRLC_SRM_INDEX_CNTL_DATA_2                                             0xec95
++#define mmRLC_SRM_INDEX_CNTL_DATA_3                                             0xec96
++#define mmRLC_SRM_INDEX_CNTL_DATA_4                                             0xec97
++#define mmRLC_SRM_INDEX_CNTL_DATA_5                                             0xec98
++#define mmRLC_SRM_INDEX_CNTL_DATA_6                                             0xec99
++#define mmRLC_SRM_INDEX_CNTL_DATA_7                                             0xec9a
++#define mmRLC_SRM_STAT                                                          0xec9b
++#define mmRLC_SRM_GPM_ABORT                                                     0xec9c
++#define mmRLC_CSIB_ADDR_LO                                                      0xeca2
++#define mmRLC_CSIB_ADDR_HI                                                      0xeca3
++#define mmRLC_CSIB_LENGTH                                                       0xeca4
++#define mmRLC_CP_RESPONSE0                                                      0xeca5
++#define mmRLC_CP_RESPONSE1                                                      0xeca6
++#define mmRLC_CP_RESPONSE2                                                      0xeca7
++#define mmRLC_CP_RESPONSE3                                                      0xeca8
++#define mmRLC_SMU_COMMAND                                                       0xeca9
++#define mmRLC_CP_SCHEDULERS                                                     0xecaa
++#define mmRLC_SPM_PERFMON_CNTL                                                  0xdc80
++#define mmRLC_SPM_PERFMON_RING_BASE_LO                                          0xdc81
++#define mmRLC_SPM_PERFMON_RING_BASE_HI                                          0xdc82
++#define mmRLC_SPM_PERFMON_RING_SIZE                                             0xdc83
++#define mmRLC_SPM_PERFMON_SEGMENT_SIZE                                          0xdc84
++#define mmRLC_SPM_SE_MUXSEL_ADDR                                                0xdc85
++#define mmRLC_SPM_SE_MUXSEL_DATA                                                0xdc86
++#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY                                      0xdc87
++#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY                                      0xdc88
++#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY                                      0xdc89
++#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY                                       0xdc8a
++#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY                                       0xdc8b
++#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY                                       0xdc8c
++#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY                                      0xdc8d
++#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY                                       0xdc8e
++#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY                                       0xdc90
++#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY                                      0xdc91
++#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY                                      0xdc92
++#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY                                      0xdc93
++#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY                                       0xdc94
++#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY                                       0xdc95
++#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY                                      0xdc96
++#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY                                      0xdc97
++#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY                                      0xdc98
++#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY                                       0xdc9a
++#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR                                            0xdc9b
++#define mmRLC_SPM_GLOBAL_MUXSEL_DATA                                            0xdc9c
++#define mmRLC_SPM_RING_RDPTR                                                    0xdc9d
++#define mmRLC_SPM_SEGMENT_THRESHOLD                                             0xdc9e
++#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY                                     0xdc9f
++#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY                                     0xdca0
++#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY                                     0xdca1
++#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY                                     0xdca2
++#define mmRLC_GPU_IOV_VF_ENABLE                                                 0xfb00
++#define mmRLC_GPU_IOV_CFG_REG1                                                  0xfb01
++#define mmRLC_GPU_IOV_CFG_REG2                                                  0xfb02
++#define mmRLC_GPU_IOV_CFG_REG6                                                  0xfb06
++#define mmRLC_GPU_IOV_CFG_REG8                                                  0xfb08
++#define mmRLC_GPU_IOV_CFG_REG9                                                  0xfb21
++#define mmRLC_GPU_IOV_CFG_REG10                                                 0xfb22
++#define mmRLC_GPU_IOV_CFG_REG11                                                 0xfb23
++#define mmRLC_GPU_IOV_CFG_REG12                                                 0xfb24
++#define mmRLC_GPU_IOV_CFG_REG13                                                 0xfb25
++#define mmRLC_GPU_IOV_CFG_REG14                                                 0xfb26
++#define mmRLC_GPU_IOV_CFG_REG15                                                 0xfb27
++#define mmRLC_GPU_IOV_ACTIVE_FCN_ID                                             0xfb40
++#define mmRLC_GPM_VMID_THREAD2                                                  0xfb41
++#define mmRLC_GPU_IOV_UCODE_ADDR                                                0xfb42
++#define mmRLC_GPU_IOV_UCODE_DATA                                                0xfb43
++#define mmRLC_GPU_IOV_SCRATCH_ADDR                                              0xfb44
++#define mmRLC_GPU_IOV_SCRATCH_DATA                                              0xfb45
++#define mmRLC_GPU_IOV_F32_CNTL                                                  0xfb46
++#define mmRLC_GPU_IOV_F32_RESET                                                 0xfb47
++#define mmRLC_GPU_IOV_SDMA0_STATUS                                              0xfb48
++#define mmRLC_GPU_IOV_SDMA1_STATUS                                              0xfb49
++#define mmRLC_GPU_IOV_SMU_RESPONSE                                              0xfb4a
++#define mmRLC_GPU_IOV_VIRT_RESET_REQ                                            0xfb4c
++#define mmRLC_GPU_IOV_RLC_RESPONSE                                              0xfb4d
++#define mmRLC_GPU_IOV_INT_DISABLE                                               0xfb4e
++#define mmRLC_GPU_IOV_INT_FORCE                                                 0xfb4f
++#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS                                         0xfb50
++#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS                                         0xfb51
++#define mmRLC_GPU_IOV_SCH_0                                                     0xfb52
++#define mmRLC_GPU_IOV_SCH_1                                                     0xfb53
++#define mmRLC_GPU_IOV_SCH_2                                                     0xfb54
++#define mmRLC_GPU_IOV_SCH_3                                                     0xfb55
++#define mmRLC_GPU_IOV_SCH_INT                                                   0xfb56
++#define mmSPI_PS_INPUT_CNTL_0                                                   0xa191
++#define mmSPI_PS_INPUT_CNTL_1                                                   0xa192
++#define mmSPI_PS_INPUT_CNTL_2                                                   0xa193
++#define mmSPI_PS_INPUT_CNTL_3                                                   0xa194
++#define mmSPI_PS_INPUT_CNTL_4                                                   0xa195
++#define mmSPI_PS_INPUT_CNTL_5                                                   0xa196
++#define mmSPI_PS_INPUT_CNTL_6                                                   0xa197
++#define mmSPI_PS_INPUT_CNTL_7                                                   0xa198
++#define mmSPI_PS_INPUT_CNTL_8                                                   0xa199
++#define mmSPI_PS_INPUT_CNTL_9                                                   0xa19a
++#define mmSPI_PS_INPUT_CNTL_10                                                  0xa19b
++#define mmSPI_PS_INPUT_CNTL_11                                                  0xa19c
++#define mmSPI_PS_INPUT_CNTL_12                                                  0xa19d
++#define mmSPI_PS_INPUT_CNTL_13                                                  0xa19e
++#define mmSPI_PS_INPUT_CNTL_14                                                  0xa19f
++#define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
++#define mmSPI_PS_INPUT_CNTL_16                                                  0xa1a1
++#define mmSPI_PS_INPUT_CNTL_17                                                  0xa1a2
++#define mmSPI_PS_INPUT_CNTL_18                                                  0xa1a3
++#define mmSPI_PS_INPUT_CNTL_19                                                  0xa1a4
++#define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
++#define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
++#define mmSPI_PS_INPUT_CNTL_22                                                  0xa1a7
++#define mmSPI_PS_INPUT_CNTL_23                                                  0xa1a8
++#define mmSPI_PS_INPUT_CNTL_24                                                  0xa1a9
++#define mmSPI_PS_INPUT_CNTL_25                                                  0xa1aa
++#define mmSPI_PS_INPUT_CNTL_26                                                  0xa1ab
++#define mmSPI_PS_INPUT_CNTL_27                                                  0xa1ac
++#define mmSPI_PS_INPUT_CNTL_28                                                  0xa1ad
++#define mmSPI_PS_INPUT_CNTL_29                                                  0xa1ae
++#define mmSPI_PS_INPUT_CNTL_30                                                  0xa1af
++#define mmSPI_PS_INPUT_CNTL_31                                                  0xa1b0
++#define mmSPI_VS_OUT_CONFIG                                                     0xa1b1
++#define mmSPI_PS_INPUT_ENA                                                      0xa1b3
++#define mmSPI_PS_INPUT_ADDR                                                     0xa1b4
++#define mmSPI_INTERP_CONTROL_0                                                  0xa1b5
++#define mmSPI_PS_IN_CONTROL                                                     0xa1b6
++#define mmSPI_BARYC_CNTL                                                        0xa1b8
++#define mmSPI_TMPRING_SIZE                                                      0xa1ba
++#define mmSPI_SHADER_POS_FORMAT                                                 0xa1c3
++#define mmSPI_SHADER_Z_FORMAT                                                   0xa1c4
++#define mmSPI_SHADER_COL_FORMAT                                                 0xa1c5
++#define mmSPI_ARB_PRIORITY                                                      0x31c0
++#define mmSPI_ARB_CYCLES_0                                                      0x31c1
++#define mmSPI_ARB_CYCLES_1                                                      0x31c2
++#define mmSPI_CDBG_SYS_GFX                                                      0x31c3
++#define mmSPI_CDBG_SYS_HP3D                                                     0x31c4
++#define mmSPI_CDBG_SYS_CS0                                                      0x31c5
++#define mmSPI_CDBG_SYS_CS1                                                      0x31c6
++#define mmSPI_WCL_PIPE_PERCENT_GFX                                              0x31c7
++#define mmSPI_WCL_PIPE_PERCENT_HP3D                                             0x31c8
++#define mmSPI_WCL_PIPE_PERCENT_CS0                                              0x31c9
++#define mmSPI_WCL_PIPE_PERCENT_CS1                                              0x31ca
++#define mmSPI_WCL_PIPE_PERCENT_CS2                                              0x31cb
++#define mmSPI_WCL_PIPE_PERCENT_CS3                                              0x31cc
++#define mmSPI_WCL_PIPE_PERCENT_CS4                                              0x31cd
++#define mmSPI_WCL_PIPE_PERCENT_CS5                                              0x31ce
++#define mmSPI_WCL_PIPE_PERCENT_CS6                                              0x31cf
++#define mmSPI_WCL_PIPE_PERCENT_CS7                                              0x31d0
++#define mmSPI_GDBG_WAVE_CNTL                                                    0x31d1
++#define mmSPI_GDBG_TRAP_CONFIG                                                  0x31d2
++#define mmSPI_GDBG_TRAP_MASK                                                    0x31d3
++#define mmSPI_GDBG_TBA_LO                                                       0x31d4
++#define mmSPI_GDBG_TBA_HI                                                       0x31d5
++#define mmSPI_GDBG_TMA_LO                                                       0x31d6
++#define mmSPI_GDBG_TMA_HI                                                       0x31d7
++#define mmSPI_GDBG_TRAP_DATA0                                                   0x31d8
++#define mmSPI_GDBG_TRAP_DATA1                                                   0x31d9
++#define mmSPI_RESET_DEBUG                                                       0x31da
++#define mmSPI_COMPUTE_QUEUE_RESET                                               0x31db
++#define mmSPI_RESOURCE_RESERVE_CU_0                                             0x31dc
++#define mmSPI_RESOURCE_RESERVE_CU_1                                             0x31dd
++#define mmSPI_RESOURCE_RESERVE_CU_2                                             0x31de
++#define mmSPI_RESOURCE_RESERVE_CU_3                                             0x31df
++#define mmSPI_RESOURCE_RESERVE_CU_4                                             0x31e0
++#define mmSPI_RESOURCE_RESERVE_CU_5                                             0x31e1
++#define mmSPI_RESOURCE_RESERVE_CU_6                                             0x31e2
++#define mmSPI_RESOURCE_RESERVE_CU_7                                             0x31e3
++#define mmSPI_RESOURCE_RESERVE_CU_8                                             0x31e4
++#define mmSPI_RESOURCE_RESERVE_CU_9                                             0x31e5
++#define mmSPI_RESOURCE_RESERVE_CU_10                                            0x31f0
++#define mmSPI_RESOURCE_RESERVE_CU_11                                            0x31f1
++#define mmSPI_RESOURCE_RESERVE_CU_12                                            0x31f4
++#define mmSPI_RESOURCE_RESERVE_CU_13                                            0x31f5
++#define mmSPI_RESOURCE_RESERVE_CU_14                                            0x31f6
++#define mmSPI_RESOURCE_RESERVE_CU_15                                            0x31f7
++#define mmSPI_RESOURCE_RESERVE_EN_CU_0                                          0x31e6
++#define mmSPI_RESOURCE_RESERVE_EN_CU_1                                          0x31e7
++#define mmSPI_RESOURCE_RESERVE_EN_CU_2                                          0x31e8
++#define mmSPI_RESOURCE_RESERVE_EN_CU_3                                          0x31e9
++#define mmSPI_RESOURCE_RESERVE_EN_CU_4                                          0x31ea
++#define mmSPI_RESOURCE_RESERVE_EN_CU_5                                          0x31eb
++#define mmSPI_RESOURCE_RESERVE_EN_CU_6                                          0x31ec
++#define mmSPI_RESOURCE_RESERVE_EN_CU_7                                          0x31ed
++#define mmSPI_RESOURCE_RESERVE_EN_CU_8                                          0x31ee
++#define mmSPI_RESOURCE_RESERVE_EN_CU_9                                          0x31ef
++#define mmSPI_RESOURCE_RESERVE_EN_CU_10                                         0x31f2
++#define mmSPI_RESOURCE_RESERVE_EN_CU_11                                         0x31f3
++#define mmSPI_RESOURCE_RESERVE_EN_CU_12                                         0x31f8
++#define mmSPI_RESOURCE_RESERVE_EN_CU_13                                         0x31f9
++#define mmSPI_RESOURCE_RESERVE_EN_CU_14                                         0x31fa
++#define mmSPI_RESOURCE_RESERVE_EN_CU_15                                         0x31fb
++#define mmSPI_COMPUTE_WF_CTX_SAVE                                               0x31fc
++#define mmSPI_PS_MAX_WAVE_ID                                                    0x243a
++#define mmSPI_START_PHASE                                                       0x243b
++#define mmSPI_GFX_CNTL                                                          0x243c
++#define mmSPI_CONFIG_CNTL                                                       0x2440
++#define mmSPI_DEBUG_CNTL                                                        0x2441
++#define mmSPI_DEBUG_READ                                                        0x2442
++#define mmSPI_DSM_CNTL                                                          0x2443
++#define mmSPI_EDC_CNT                                                           0x2444
++#define mmSPI_PERFCOUNTER0_SELECT                                               0xd980
++#define mmSPI_PERFCOUNTER1_SELECT                                               0xd981
++#define mmSPI_PERFCOUNTER2_SELECT                                               0xd982
++#define mmSPI_PERFCOUNTER3_SELECT                                               0xd983
++#define mmSPI_PERFCOUNTER0_SELECT1                                              0xd984
++#define mmSPI_PERFCOUNTER1_SELECT1                                              0xd985
++#define mmSPI_PERFCOUNTER2_SELECT1                                              0xd986
++#define mmSPI_PERFCOUNTER3_SELECT1                                              0xd987
++#define mmSPI_PERFCOUNTER4_SELECT                                               0xd988
++#define mmSPI_PERFCOUNTER5_SELECT                                               0xd989
++#define mmSPI_PERFCOUNTER_BINS                                                  0xd98a
++#define mmSPI_PERFCOUNTER0_HI                                                   0xd180
++#define mmSPI_PERFCOUNTER0_LO                                                   0xd181
++#define mmSPI_PERFCOUNTER1_HI                                                   0xd182
++#define mmSPI_PERFCOUNTER1_LO                                                   0xd183
++#define mmSPI_PERFCOUNTER2_HI                                                   0xd184
++#define mmSPI_PERFCOUNTER2_LO                                                   0xd185
++#define mmSPI_PERFCOUNTER3_HI                                                   0xd186
++#define mmSPI_PERFCOUNTER3_LO                                                   0xd187
++#define mmSPI_PERFCOUNTER4_HI                                                   0xd188
++#define mmSPI_PERFCOUNTER4_LO                                                   0xd189
++#define mmSPI_PERFCOUNTER5_HI                                                   0xd18a
++#define mmSPI_PERFCOUNTER5_LO                                                   0xd18b
++#define mmSPI_CONFIG_CNTL_1                                                     0x244f
++#define mmSPI_DEBUG_BUSY                                                        0x2450
++#define mmSPI_CONFIG_CNTL_2                                                     0x2451
++#define mmCGTS_SM_CTRL_REG                                                      0xf000
++#define mmCGTS_RD_CTRL_REG                                                      0xf001
++#define mmCGTS_RD_REG                                                           0xf002
++#define mmCGTS_TCC_DISABLE                                                      0xf003
++#define mmCGTS_USER_TCC_DISABLE                                                 0xf004
++#define mmCGTS_CU0_SP0_CTRL_REG                                                 0xf008
++#define mmCGTS_CU0_LDS_SQ_CTRL_REG                                              0xf009
++#define mmCGTS_CU0_TA_SQC_CTRL_REG                                              0xf00a
++#define mmCGTS_CU0_SP1_CTRL_REG                                                 0xf00b
++#define mmCGTS_CU0_TD_TCP_CTRL_REG                                              0xf00c
++#define mmCGTS_CU1_SP0_CTRL_REG                                                 0xf00d
++#define mmCGTS_CU1_LDS_SQ_CTRL_REG                                              0xf00e
++#define mmCGTS_CU1_TA_CTRL_REG                                                  0xf00f
++#define mmCGTS_CU1_SP1_CTRL_REG                                                 0xf010
++#define mmCGTS_CU1_TD_TCP_CTRL_REG                                              0xf011
++#define mmCGTS_CU2_SP0_CTRL_REG                                                 0xf012
++#define mmCGTS_CU2_LDS_SQ_CTRL_REG                                              0xf013
++#define mmCGTS_CU2_TA_CTRL_REG                                                  0xf014
++#define mmCGTS_CU2_SP1_CTRL_REG                                                 0xf015
++#define mmCGTS_CU2_TD_TCP_CTRL_REG                                              0xf016
++#define mmCGTS_CU3_SP0_CTRL_REG                                                 0xf017
++#define mmCGTS_CU3_LDS_SQ_CTRL_REG                                              0xf018
++#define mmCGTS_CU3_TA_CTRL_REG                                                  0xf019
++#define mmCGTS_CU3_SP1_CTRL_REG                                                 0xf01a
++#define mmCGTS_CU3_TD_TCP_CTRL_REG                                              0xf01b
++#define mmCGTS_CU4_SP0_CTRL_REG                                                 0xf01c
++#define mmCGTS_CU4_LDS_SQ_CTRL_REG                                              0xf01d
++#define mmCGTS_CU4_TA_SQC_CTRL_REG                                              0xf01e
++#define mmCGTS_CU4_SP1_CTRL_REG                                                 0xf01f
++#define mmCGTS_CU4_TD_TCP_CTRL_REG                                              0xf020
++#define mmCGTS_CU5_SP0_CTRL_REG                                                 0xf021
++#define mmCGTS_CU5_LDS_SQ_CTRL_REG                                              0xf022
++#define mmCGTS_CU5_TA_CTRL_REG                                                  0xf023
++#define mmCGTS_CU5_SP1_CTRL_REG                                                 0xf024
++#define mmCGTS_CU5_TD_TCP_CTRL_REG                                              0xf025
++#define mmCGTS_CU6_SP0_CTRL_REG                                                 0xf026
++#define mmCGTS_CU6_LDS_SQ_CTRL_REG                                              0xf027
++#define mmCGTS_CU6_TA_CTRL_REG                                                  0xf028
++#define mmCGTS_CU6_SP1_CTRL_REG                                                 0xf029
++#define mmCGTS_CU6_TD_TCP_CTRL_REG                                              0xf02a
++#define mmCGTS_CU7_SP0_CTRL_REG                                                 0xf02b
++#define mmCGTS_CU7_LDS_SQ_CTRL_REG                                              0xf02c
++#define mmCGTS_CU7_TA_CTRL_REG                                                  0xf02d
++#define mmCGTS_CU7_SP1_CTRL_REG                                                 0xf02e
++#define mmCGTS_CU7_TD_TCP_CTRL_REG                                              0xf02f
++#define mmCGTS_CU8_SP0_CTRL_REG                                                 0xf030
++#define mmCGTS_CU8_LDS_SQ_CTRL_REG                                              0xf031
++#define mmCGTS_CU8_TA_SQC_CTRL_REG                                              0xf032
++#define mmCGTS_CU8_SP1_CTRL_REG                                                 0xf033
++#define mmCGTS_CU8_TD_TCP_CTRL_REG                                              0xf034
++#define mmCGTS_CU9_SP0_CTRL_REG                                                 0xf035
++#define mmCGTS_CU9_LDS_SQ_CTRL_REG                                              0xf036
++#define mmCGTS_CU9_TA_CTRL_REG                                                  0xf037
++#define mmCGTS_CU9_SP1_CTRL_REG                                                 0xf038
++#define mmCGTS_CU9_TD_TCP_CTRL_REG                                              0xf039
++#define mmCGTS_CU10_SP0_CTRL_REG                                                0xf03a
++#define mmCGTS_CU10_LDS_SQ_CTRL_REG                                             0xf03b
++#define mmCGTS_CU10_TA_CTRL_REG                                                 0xf03c
++#define mmCGTS_CU10_SP1_CTRL_REG                                                0xf03d
++#define mmCGTS_CU10_TD_TCP_CTRL_REG                                             0xf03e
++#define mmCGTS_CU11_SP0_CTRL_REG                                                0xf03f
++#define mmCGTS_CU11_LDS_SQ_CTRL_REG                                             0xf040
++#define mmCGTS_CU11_TA_CTRL_REG                                                 0xf041
++#define mmCGTS_CU11_SP1_CTRL_REG                                                0xf042
++#define mmCGTS_CU11_TD_TCP_CTRL_REG                                             0xf043
++#define mmCGTS_CU12_SP0_CTRL_REG                                                0xf044
++#define mmCGTS_CU12_LDS_SQ_CTRL_REG                                             0xf045
++#define mmCGTS_CU12_TA_SQC_CTRL_REG                                             0xf046
++#define mmCGTS_CU12_SP1_CTRL_REG                                                0xf047
++#define mmCGTS_CU12_TD_TCP_CTRL_REG                                             0xf048
++#define mmCGTS_CU13_SP0_CTRL_REG                                                0xf049
++#define mmCGTS_CU13_LDS_SQ_CTRL_REG                                             0xf04a
++#define mmCGTS_CU13_TA_CTRL_REG                                                 0xf04b
++#define mmCGTS_CU13_SP1_CTRL_REG                                                0xf04c
++#define mmCGTS_CU13_TD_TCP_CTRL_REG                                             0xf04d
++#define mmCGTS_CU14_SP0_CTRL_REG                                                0xf04e
++#define mmCGTS_CU14_LDS_SQ_CTRL_REG                                             0xf04f
++#define mmCGTS_CU14_TA_CTRL_REG                                                 0xf050
++#define mmCGTS_CU14_SP1_CTRL_REG                                                0xf051
++#define mmCGTS_CU14_TD_TCP_CTRL_REG                                             0xf052
++#define mmCGTS_CU15_SP0_CTRL_REG                                                0xf053
++#define mmCGTS_CU15_LDS_SQ_CTRL_REG                                             0xf054
++#define mmCGTS_CU15_TA_CTRL_REG                                                 0xf055
++#define mmCGTS_CU15_SP1_CTRL_REG                                                0xf056
++#define mmCGTS_CU15_TD_TCP_CTRL_REG                                             0xf057
++#define mmCGTT_SPI_CLK_CTRL                                                     0xf080
++#define mmCGTT_PC_CLK_CTRL                                                      0xf081
++#define mmCGTT_BCI_CLK_CTRL                                                     0xf082
++#define mmSPI_WF_LIFETIME_CNTL                                                  0x24aa
++#define mmSPI_WF_LIFETIME_LIMIT_0                                               0x24ab
++#define mmSPI_WF_LIFETIME_LIMIT_1                                               0x24ac
++#define mmSPI_WF_LIFETIME_LIMIT_2                                               0x24ad
++#define mmSPI_WF_LIFETIME_LIMIT_3                                               0x24ae
++#define mmSPI_WF_LIFETIME_LIMIT_4                                               0x24af
++#define mmSPI_WF_LIFETIME_LIMIT_5                                               0x24b0
++#define mmSPI_WF_LIFETIME_LIMIT_6                                               0x24b1
++#define mmSPI_WF_LIFETIME_LIMIT_7                                               0x24b2
++#define mmSPI_WF_LIFETIME_LIMIT_8                                               0x24b3
++#define mmSPI_WF_LIFETIME_LIMIT_9                                               0x24b4
++#define mmSPI_WF_LIFETIME_STATUS_0                                              0x24b5
++#define mmSPI_WF_LIFETIME_STATUS_1                                              0x24b6
++#define mmSPI_WF_LIFETIME_STATUS_2                                              0x24b7
++#define mmSPI_WF_LIFETIME_STATUS_3                                              0x24b8
++#define mmSPI_WF_LIFETIME_STATUS_4                                              0x24b9
++#define mmSPI_WF_LIFETIME_STATUS_5                                              0x24ba
++#define mmSPI_WF_LIFETIME_STATUS_6                                              0x24bb
++#define mmSPI_WF_LIFETIME_STATUS_7                                              0x24bc
++#define mmSPI_WF_LIFETIME_STATUS_8                                              0x24bd
++#define mmSPI_WF_LIFETIME_STATUS_9                                              0x24be
++#define mmSPI_WF_LIFETIME_STATUS_10                                             0x24bf
++#define mmSPI_WF_LIFETIME_STATUS_11                                             0x24c0
++#define mmSPI_WF_LIFETIME_STATUS_12                                             0x24c1
++#define mmSPI_WF_LIFETIME_STATUS_13                                             0x24c2
++#define mmSPI_WF_LIFETIME_STATUS_14                                             0x24c3
++#define mmSPI_WF_LIFETIME_STATUS_15                                             0x24c4
++#define mmSPI_WF_LIFETIME_STATUS_16                                             0x24c5
++#define mmSPI_WF_LIFETIME_STATUS_17                                             0x24c6
++#define mmSPI_WF_LIFETIME_STATUS_18                                             0x24c7
++#define mmSPI_WF_LIFETIME_STATUS_19                                             0x24c8
++#define mmSPI_WF_LIFETIME_STATUS_20                                             0x24c9
++#define mmSPI_WF_LIFETIME_DEBUG                                                 0x24ca
++#define mmSPI_SLAVE_DEBUG_BUSY                                                  0x24d3
++#define mmSPI_LB_CTR_CTRL                                                       0x24d4
++#define mmSPI_LB_CU_MASK                                                        0x24d5
++#define mmSPI_LB_DATA_REG                                                       0x24d6
++#define mmSPI_PG_ENABLE_STATIC_CU_MASK                                          0x24d7
++#define mmSPI_GDS_CREDITS                                                       0x24d8
++#define mmSPI_SX_EXPORT_BUFFER_SIZES                                            0x24d9
++#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                                        0x24da
++#define mmSPI_CSQ_WF_ACTIVE_STATUS                                              0x24db
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_0                                             0x24dc
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_1                                             0x24dd
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_2                                             0x24de
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_3                                             0x24df
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_4                                             0x24e0
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_5                                             0x24e1
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_6                                             0x24e2
++#define mmSPI_CSQ_WF_ACTIVE_COUNT_7                                             0x24e3
++#define mmBCI_DEBUG_READ                                                        0x24eb
++#define mmSPI_P0_TRAP_SCREEN_PSBA_LO                                            0x24ec
++#define mmSPI_P0_TRAP_SCREEN_PSBA_HI                                            0x24ed
++#define mmSPI_P0_TRAP_SCREEN_PSMA_LO                                            0x24ee
++#define mmSPI_P0_TRAP_SCREEN_PSMA_HI                                            0x24ef
++#define mmSPI_P0_TRAP_SCREEN_GPR_MIN                                            0x24f0
++#define mmSPI_P1_TRAP_SCREEN_PSBA_LO                                            0x24f1
++#define mmSPI_P1_TRAP_SCREEN_PSBA_HI                                            0x24f2
++#define mmSPI_P1_TRAP_SCREEN_PSMA_LO                                            0x24f3
++#define mmSPI_P1_TRAP_SCREEN_PSMA_HI                                            0x24f4
++#define mmSPI_P1_TRAP_SCREEN_GPR_MIN                                            0x24f5
++#define mmSPI_SHADER_TBA_LO_PS                                                  0x2c00
++#define mmSPI_SHADER_TBA_HI_PS                                                  0x2c01
++#define mmSPI_SHADER_TMA_LO_PS                                                  0x2c02
++#define mmSPI_SHADER_TMA_HI_PS                                                  0x2c03
++#define mmSPI_SHADER_PGM_LO_PS                                                  0x2c08
++#define mmSPI_SHADER_PGM_HI_PS                                                  0x2c09
++#define mmSPI_SHADER_PGM_RSRC1_PS                                               0x2c0a
++#define mmSPI_SHADER_PGM_RSRC2_PS                                               0x2c0b
++#define mmSPI_SHADER_PGM_RSRC3_PS                                               0x2c07
++#define mmSPI_SHADER_USER_DATA_PS_0                                             0x2c0c
++#define mmSPI_SHADER_USER_DATA_PS_1                                             0x2c0d
++#define mmSPI_SHADER_USER_DATA_PS_2                                             0x2c0e
++#define mmSPI_SHADER_USER_DATA_PS_3                                             0x2c0f
++#define mmSPI_SHADER_USER_DATA_PS_4                                             0x2c10
++#define mmSPI_SHADER_USER_DATA_PS_5                                             0x2c11
++#define mmSPI_SHADER_USER_DATA_PS_6                                             0x2c12
++#define mmSPI_SHADER_USER_DATA_PS_7                                             0x2c13
++#define mmSPI_SHADER_USER_DATA_PS_8                                             0x2c14
++#define mmSPI_SHADER_USER_DATA_PS_9                                             0x2c15
++#define mmSPI_SHADER_USER_DATA_PS_10                                            0x2c16
++#define mmSPI_SHADER_USER_DATA_PS_11                                            0x2c17
++#define mmSPI_SHADER_USER_DATA_PS_12                                            0x2c18
++#define mmSPI_SHADER_USER_DATA_PS_13                                            0x2c19
++#define mmSPI_SHADER_USER_DATA_PS_14                                            0x2c1a
++#define mmSPI_SHADER_USER_DATA_PS_15                                            0x2c1b
++#define mmSPI_SHADER_TBA_LO_VS                                                  0x2c40
++#define mmSPI_SHADER_TBA_HI_VS                                                  0x2c41
++#define mmSPI_SHADER_TMA_LO_VS                                                  0x2c42
++#define mmSPI_SHADER_TMA_HI_VS                                                  0x2c43
++#define mmSPI_SHADER_PGM_LO_VS                                                  0x2c48
++#define mmSPI_SHADER_PGM_HI_VS                                                  0x2c49
++#define mmSPI_SHADER_PGM_RSRC1_VS                                               0x2c4a
++#define mmSPI_SHADER_PGM_RSRC2_VS                                               0x2c4b
++#define mmSPI_SHADER_PGM_RSRC3_VS                                               0x2c46
++#define mmSPI_SHADER_LATE_ALLOC_VS                                              0x2c47
++#define mmSPI_SHADER_USER_DATA_VS_0                                             0x2c4c
++#define mmSPI_SHADER_USER_DATA_VS_1                                             0x2c4d
++#define mmSPI_SHADER_USER_DATA_VS_2                                             0x2c4e
++#define mmSPI_SHADER_USER_DATA_VS_3                                             0x2c4f
++#define mmSPI_SHADER_USER_DATA_VS_4                                             0x2c50
++#define mmSPI_SHADER_USER_DATA_VS_5                                             0x2c51
++#define mmSPI_SHADER_USER_DATA_VS_6                                             0x2c52
++#define mmSPI_SHADER_USER_DATA_VS_7                                             0x2c53
++#define mmSPI_SHADER_USER_DATA_VS_8                                             0x2c54
++#define mmSPI_SHADER_USER_DATA_VS_9                                             0x2c55
++#define mmSPI_SHADER_USER_DATA_VS_10                                            0x2c56
++#define mmSPI_SHADER_USER_DATA_VS_11                                            0x2c57
++#define mmSPI_SHADER_USER_DATA_VS_12                                            0x2c58
++#define mmSPI_SHADER_USER_DATA_VS_13                                            0x2c59
++#define mmSPI_SHADER_USER_DATA_VS_14                                            0x2c5a
++#define mmSPI_SHADER_USER_DATA_VS_15                                            0x2c5b
++#define mmSPI_SHADER_PGM_RSRC2_ES_VS                                            0x2c7c
++#define mmSPI_SHADER_PGM_RSRC2_LS_VS                                            0x2c7d
++#define mmSPI_SHADER_TBA_LO_GS                                                  0x2c80
++#define mmSPI_SHADER_TBA_HI_GS                                                  0x2c81
++#define mmSPI_SHADER_TMA_LO_GS                                                  0x2c82
++#define mmSPI_SHADER_TMA_HI_GS                                                  0x2c83
++#define mmSPI_SHADER_PGM_LO_GS                                                  0x2c88
++#define mmSPI_SHADER_PGM_HI_GS                                                  0x2c89
++#define mmSPI_SHADER_PGM_RSRC1_GS                                               0x2c8a
++#define mmSPI_SHADER_PGM_RSRC2_GS                                               0x2c8b
++#define mmSPI_SHADER_PGM_RSRC3_GS                                               0x2c87
++#define mmSPI_SHADER_USER_DATA_GS_0                                             0x2c8c
++#define mmSPI_SHADER_USER_DATA_GS_1                                             0x2c8d
++#define mmSPI_SHADER_USER_DATA_GS_2                                             0x2c8e
++#define mmSPI_SHADER_USER_DATA_GS_3                                             0x2c8f
++#define mmSPI_SHADER_USER_DATA_GS_4                                             0x2c90
++#define mmSPI_SHADER_USER_DATA_GS_5                                             0x2c91
++#define mmSPI_SHADER_USER_DATA_GS_6                                             0x2c92
++#define mmSPI_SHADER_USER_DATA_GS_7                                             0x2c93
++#define mmSPI_SHADER_USER_DATA_GS_8                                             0x2c94
++#define mmSPI_SHADER_USER_DATA_GS_9                                             0x2c95
++#define mmSPI_SHADER_USER_DATA_GS_10                                            0x2c96
++#define mmSPI_SHADER_USER_DATA_GS_11                                            0x2c97
++#define mmSPI_SHADER_USER_DATA_GS_12                                            0x2c98
++#define mmSPI_SHADER_USER_DATA_GS_13                                            0x2c99
++#define mmSPI_SHADER_USER_DATA_GS_14                                            0x2c9a
++#define mmSPI_SHADER_USER_DATA_GS_15                                            0x2c9b
++#define mmSPI_SHADER_PGM_RSRC2_ES_GS                                            0x2cbc
++#define mmSPI_SHADER_TBA_LO_ES                                                  0x2cc0
++#define mmSPI_SHADER_TBA_HI_ES                                                  0x2cc1
++#define mmSPI_SHADER_TMA_LO_ES                                                  0x2cc2
++#define mmSPI_SHADER_TMA_HI_ES                                                  0x2cc3
++#define mmSPI_SHADER_PGM_LO_ES                                                  0x2cc8
++#define mmSPI_SHADER_PGM_HI_ES                                                  0x2cc9
++#define mmSPI_SHADER_PGM_RSRC1_ES                                               0x2cca
++#define mmSPI_SHADER_PGM_RSRC2_ES                                               0x2ccb
++#define mmSPI_SHADER_PGM_RSRC3_ES                                               0x2cc7
++#define mmSPI_SHADER_USER_DATA_ES_0                                             0x2ccc
++#define mmSPI_SHADER_USER_DATA_ES_1                                             0x2ccd
++#define mmSPI_SHADER_USER_DATA_ES_2                                             0x2cce
++#define mmSPI_SHADER_USER_DATA_ES_3                                             0x2ccf
++#define mmSPI_SHADER_USER_DATA_ES_4                                             0x2cd0
++#define mmSPI_SHADER_USER_DATA_ES_5                                             0x2cd1
++#define mmSPI_SHADER_USER_DATA_ES_6                                             0x2cd2
++#define mmSPI_SHADER_USER_DATA_ES_7                                             0x2cd3
++#define mmSPI_SHADER_USER_DATA_ES_8                                             0x2cd4
++#define mmSPI_SHADER_USER_DATA_ES_9                                             0x2cd5
++#define mmSPI_SHADER_USER_DATA_ES_10                                            0x2cd6
++#define mmSPI_SHADER_USER_DATA_ES_11                                            0x2cd7
++#define mmSPI_SHADER_USER_DATA_ES_12                                            0x2cd8
++#define mmSPI_SHADER_USER_DATA_ES_13                                            0x2cd9
++#define mmSPI_SHADER_USER_DATA_ES_14                                            0x2cda
++#define mmSPI_SHADER_USER_DATA_ES_15                                            0x2cdb
++#define mmSPI_SHADER_PGM_RSRC2_LS_ES                                            0x2cfd
++#define mmSPI_SHADER_TBA_LO_HS                                                  0x2d00
++#define mmSPI_SHADER_TBA_HI_HS                                                  0x2d01
++#define mmSPI_SHADER_TMA_LO_HS                                                  0x2d02
++#define mmSPI_SHADER_TMA_HI_HS                                                  0x2d03
++#define mmSPI_SHADER_PGM_LO_HS                                                  0x2d08
++#define mmSPI_SHADER_PGM_HI_HS                                                  0x2d09
++#define mmSPI_SHADER_PGM_RSRC1_HS                                               0x2d0a
++#define mmSPI_SHADER_PGM_RSRC2_HS                                               0x2d0b
++#define mmSPI_SHADER_PGM_RSRC3_HS                                               0x2d07
++#define mmSPI_SHADER_USER_DATA_HS_0                                             0x2d0c
++#define mmSPI_SHADER_USER_DATA_HS_1                                             0x2d0d
++#define mmSPI_SHADER_USER_DATA_HS_2                                             0x2d0e
++#define mmSPI_SHADER_USER_DATA_HS_3                                             0x2d0f
++#define mmSPI_SHADER_USER_DATA_HS_4                                             0x2d10
++#define mmSPI_SHADER_USER_DATA_HS_5                                             0x2d11
++#define mmSPI_SHADER_USER_DATA_HS_6                                             0x2d12
++#define mmSPI_SHADER_USER_DATA_HS_7                                             0x2d13
++#define mmSPI_SHADER_USER_DATA_HS_8                                             0x2d14
++#define mmSPI_SHADER_USER_DATA_HS_9                                             0x2d15
++#define mmSPI_SHADER_USER_DATA_HS_10                                            0x2d16
++#define mmSPI_SHADER_USER_DATA_HS_11                                            0x2d17
++#define mmSPI_SHADER_USER_DATA_HS_12                                            0x2d18
++#define mmSPI_SHADER_USER_DATA_HS_13                                            0x2d19
++#define mmSPI_SHADER_USER_DATA_HS_14                                            0x2d1a
++#define mmSPI_SHADER_USER_DATA_HS_15                                            0x2d1b
++#define mmSPI_SHADER_PGM_RSRC2_LS_HS                                            0x2d3d
++#define mmSPI_SHADER_TBA_LO_LS                                                  0x2d40
++#define mmSPI_SHADER_TBA_HI_LS                                                  0x2d41
++#define mmSPI_SHADER_TMA_LO_LS                                                  0x2d42
++#define mmSPI_SHADER_TMA_HI_LS                                                  0x2d43
++#define mmSPI_SHADER_PGM_LO_LS                                                  0x2d48
++#define mmSPI_SHADER_PGM_HI_LS                                                  0x2d49
++#define mmSPI_SHADER_PGM_RSRC1_LS                                               0x2d4a
++#define mmSPI_SHADER_PGM_RSRC2_LS                                               0x2d4b
++#define mmSPI_SHADER_PGM_RSRC3_LS                                               0x2d47
++#define mmSPI_SHADER_USER_DATA_LS_0                                             0x2d4c
++#define mmSPI_SHADER_USER_DATA_LS_1                                             0x2d4d
++#define mmSPI_SHADER_USER_DATA_LS_2                                             0x2d4e
++#define mmSPI_SHADER_USER_DATA_LS_3                                             0x2d4f
++#define mmSPI_SHADER_USER_DATA_LS_4                                             0x2d50
++#define mmSPI_SHADER_USER_DATA_LS_5                                             0x2d51
++#define mmSPI_SHADER_USER_DATA_LS_6                                             0x2d52
++#define mmSPI_SHADER_USER_DATA_LS_7                                             0x2d53
++#define mmSPI_SHADER_USER_DATA_LS_8                                             0x2d54
++#define mmSPI_SHADER_USER_DATA_LS_9                                             0x2d55
++#define mmSPI_SHADER_USER_DATA_LS_10                                            0x2d56
++#define mmSPI_SHADER_USER_DATA_LS_11                                            0x2d57
++#define mmSPI_SHADER_USER_DATA_LS_12                                            0x2d58
++#define mmSPI_SHADER_USER_DATA_LS_13                                            0x2d59
++#define mmSPI_SHADER_USER_DATA_LS_14                                            0x2d5a
++#define mmSPI_SHADER_USER_DATA_LS_15                                            0x2d5b
++#define mmSQ_CONFIG                                                             0x2300
++#define mmSQC_CONFIG                                                            0x2301
++#define mmSQC_CACHES                                                            0xc348
++#define mmSQC_WRITEBACK                                                         0xc349
++#define mmSQC_DSM_CNTL                                                          0x230f
++#define mmSQ_RANDOM_WAVE_PRI                                                    0x2303
++#define mmSQ_REG_CREDITS                                                        0x2304
++#define mmSQ_FIFO_SIZES                                                         0x2305
++#define mmSQ_DSM_CNTL                                                           0x2306
++#define mmCC_GC_SHADER_RATE_CONFIG                                              0x2312
++#define mmGC_USER_SHADER_RATE_CONFIG                                            0x2313
++#define mmSQ_INTERRUPT_AUTO_MASK                                                0x2314
++#define mmSQ_INTERRUPT_MSG_CTRL                                                 0x2315
++#define mmSQ_PERFCOUNTER_CTRL                                                   0xd9e0
++#define mmSQ_PERFCOUNTER_MASK                                                   0xd9e1
++#define mmSQ_PERFCOUNTER_CTRL2                                                  0xd9e2
++#define mmCC_SQC_BANK_DISABLE                                                   0x2307
++#define mmUSER_SQC_BANK_DISABLE                                                 0x2308
++#define mmSQ_PERFCOUNTER0_LO                                                    0xd1c0
++#define mmSQ_PERFCOUNTER1_LO                                                    0xd1c2
++#define mmSQ_PERFCOUNTER2_LO                                                    0xd1c4
++#define mmSQ_PERFCOUNTER3_LO                                                    0xd1c6
++#define mmSQ_PERFCOUNTER4_LO                                                    0xd1c8
++#define mmSQ_PERFCOUNTER5_LO                                                    0xd1ca
++#define mmSQ_PERFCOUNTER6_LO                                                    0xd1cc
++#define mmSQ_PERFCOUNTER7_LO                                                    0xd1ce
++#define mmSQ_PERFCOUNTER8_LO                                                    0xd1d0
++#define mmSQ_PERFCOUNTER9_LO                                                    0xd1d2
++#define mmSQ_PERFCOUNTER10_LO                                                   0xd1d4
++#define mmSQ_PERFCOUNTER11_LO                                                   0xd1d6
++#define mmSQ_PERFCOUNTER12_LO                                                   0xd1d8
++#define mmSQ_PERFCOUNTER13_LO                                                   0xd1da
++#define mmSQ_PERFCOUNTER14_LO                                                   0xd1dc
++#define mmSQ_PERFCOUNTER15_LO                                                   0xd1de
++#define mmSQ_PERFCOUNTER0_HI                                                    0xd1c1
++#define mmSQ_PERFCOUNTER1_HI                                                    0xd1c3
++#define mmSQ_PERFCOUNTER2_HI                                                    0xd1c5
++#define mmSQ_PERFCOUNTER3_HI                                                    0xd1c7
++#define mmSQ_PERFCOUNTER4_HI                                                    0xd1c9
++#define mmSQ_PERFCOUNTER5_HI                                                    0xd1cb
++#define mmSQ_PERFCOUNTER6_HI                                                    0xd1cd
++#define mmSQ_PERFCOUNTER7_HI                                                    0xd1cf
++#define mmSQ_PERFCOUNTER8_HI                                                    0xd1d1
++#define mmSQ_PERFCOUNTER9_HI                                                    0xd1d3
++#define mmSQ_PERFCOUNTER10_HI                                                   0xd1d5
++#define mmSQ_PERFCOUNTER11_HI                                                   0xd1d7
++#define mmSQ_PERFCOUNTER12_HI                                                   0xd1d9
++#define mmSQ_PERFCOUNTER13_HI                                                   0xd1db
++#define mmSQ_PERFCOUNTER14_HI                                                   0xd1dd
++#define mmSQ_PERFCOUNTER15_HI                                                   0xd1df
++#define mmSQ_PERFCOUNTER0_SELECT                                                0xd9c0
++#define mmSQ_PERFCOUNTER1_SELECT                                                0xd9c1
++#define mmSQ_PERFCOUNTER2_SELECT                                                0xd9c2
++#define mmSQ_PERFCOUNTER3_SELECT                                                0xd9c3
++#define mmSQ_PERFCOUNTER4_SELECT                                                0xd9c4
++#define mmSQ_PERFCOUNTER5_SELECT                                                0xd9c5
++#define mmSQ_PERFCOUNTER6_SELECT                                                0xd9c6
++#define mmSQ_PERFCOUNTER7_SELECT                                                0xd9c7
++#define mmSQ_PERFCOUNTER8_SELECT                                                0xd9c8
++#define mmSQ_PERFCOUNTER9_SELECT                                                0xd9c9
++#define mmSQ_PERFCOUNTER10_SELECT                                               0xd9ca
++#define mmSQ_PERFCOUNTER11_SELECT                                               0xd9cb
++#define mmSQ_PERFCOUNTER12_SELECT                                               0xd9cc
++#define mmSQ_PERFCOUNTER13_SELECT                                               0xd9cd
++#define mmSQ_PERFCOUNTER14_SELECT                                               0xd9ce
++#define mmSQ_PERFCOUNTER15_SELECT                                               0xd9cf
++#define mmCGTT_SQ_CLK_CTRL                                                      0xf08c
++#define mmCGTT_SQG_CLK_CTRL                                                     0xf08d
++#define mmSQ_ALU_CLK_CTRL                                                       0xf08e
++#define mmSQ_TEX_CLK_CTRL                                                       0xf08f
++#define mmSQ_LDS_CLK_CTRL                                                       0xf090
++#define mmSQ_POWER_THROTTLE                                                     0xf091
++#define mmSQ_POWER_THROTTLE2                                                    0xf092
++#define mmSQ_TIME_HI                                                            0x237c
++#define mmSQ_TIME_LO                                                            0x237d
++#define mmSQ_THREAD_TRACE_BASE                                                  0xc330
++#define mmSQ_THREAD_TRACE_BASE2                                                 0xc337
++#define mmSQ_THREAD_TRACE_SIZE                                                  0xc331
++#define mmSQ_THREAD_TRACE_MASK                                                  0xc332
++#define mmSQ_THREAD_TRACE_USERDATA_0                                            0xc340
++#define mmSQ_THREAD_TRACE_USERDATA_1                                            0xc341
++#define mmSQ_THREAD_TRACE_USERDATA_2                                            0xc342
++#define mmSQ_THREAD_TRACE_USERDATA_3                                            0xc343
++#define mmSQ_THREAD_TRACE_MODE                                                  0xc336
++#define mmSQ_THREAD_TRACE_CTRL                                                  0xc335
++#define mmSQ_THREAD_TRACE_TOKEN_MASK                                            0xc333
++#define mmSQ_THREAD_TRACE_TOKEN_MASK2                                           0xc338
++#define mmSQ_THREAD_TRACE_PERF_MASK                                             0xc334
++#define mmSQ_THREAD_TRACE_WPTR                                                  0xc339
++#define mmSQ_THREAD_TRACE_STATUS                                                0xc33a
++#define mmSQ_THREAD_TRACE_CNTR                                                  0x2390
++#define mmSQ_THREAD_TRACE_HIWATER                                               0xc33b
++#define mmSQ_LB_CTR_CTRL                                                        0x2398
++#define mmSQ_LB_DATA_ALU_CYCLES                                                 0x2399
++#define mmSQ_LB_DATA_TEX_CYCLES                                                 0x239a
++#define mmSQ_LB_DATA_ALU_STALLS                                                 0x239b
++#define mmSQ_LB_DATA_TEX_STALLS                                                 0x239c
++#define mmSQC_EDC_CNT                                                           0x23a0
++#define mmSQ_EDC_SEC_CNT                                                        0x23a1
++#define mmSQ_EDC_DED_CNT                                                        0x23a2
++#define mmSQ_EDC_INFO                                                           0x23a3
++#define mmSQ_BUF_RSRC_WORD0                                                     0x23c0
++#define mmSQ_BUF_RSRC_WORD1                                                     0x23c1
++#define mmSQ_BUF_RSRC_WORD2                                                     0x23c2
++#define mmSQ_BUF_RSRC_WORD3                                                     0x23c3
++#define mmSQ_IMG_RSRC_WORD0                                                     0x23c4
++#define mmSQ_IMG_RSRC_WORD1                                                     0x23c5
++#define mmSQ_IMG_RSRC_WORD2                                                     0x23c6
++#define mmSQ_IMG_RSRC_WORD3                                                     0x23c7
++#define mmSQ_IMG_RSRC_WORD4                                                     0x23c8
++#define mmSQ_IMG_RSRC_WORD5                                                     0x23c9
++#define mmSQ_IMG_RSRC_WORD6                                                     0x23ca
++#define mmSQ_IMG_RSRC_WORD7                                                     0x23cb
++#define mmSQ_IMG_SAMP_WORD0                                                     0x23cc
++#define mmSQ_IMG_SAMP_WORD1                                                     0x23cd
++#define mmSQ_IMG_SAMP_WORD2                                                     0x23ce
++#define mmSQ_IMG_SAMP_WORD3                                                     0x23cf
++#define mmSQ_FLAT_SCRATCH_WORD0                                                 0x23d0
++#define mmSQ_FLAT_SCRATCH_WORD1                                                 0x23d1
++#define mmSQ_M0_GPR_IDX_WORD                                                    0x23d2
++#define mmSQ_IND_INDEX                                                          0x2378
++#define mmSQ_CMD                                                                0x237b
++#define mmSQ_IND_DATA                                                           0x2379
++#define mmSQ_REG_TIMESTAMP                                                      0x2374
++#define mmSQ_CMD_TIMESTAMP                                                      0x2375
++#define mmSQ_HV_VMID_CTRL                                                       0xf840
++#define ixSQ_WAVE_INST_DW0                                                      0x1a
++#define ixSQ_WAVE_INST_DW1                                                      0x1b
++#define ixSQ_WAVE_PC_LO                                                         0x18
++#define ixSQ_WAVE_PC_HI                                                         0x19
++#define ixSQ_WAVE_IB_DBG0                                                       0x1c
++#define ixSQ_WAVE_IB_DBG1                                                       0x1d
++#define ixSQ_WAVE_EXEC_LO                                                       0x27e
++#define ixSQ_WAVE_EXEC_HI                                                       0x27f
++#define ixSQ_WAVE_STATUS                                                        0x12
++#define ixSQ_WAVE_MODE                                                          0x11
++#define ixSQ_WAVE_TRAPSTS                                                       0x13
++#define ixSQ_WAVE_HW_ID                                                         0x14
++#define ixSQ_WAVE_GPR_ALLOC                                                     0x15
++#define ixSQ_WAVE_LDS_ALLOC                                                     0x16
++#define ixSQ_WAVE_IB_STS                                                        0x17
++#define ixSQ_WAVE_M0                                                            0x27c
++#define ixSQ_WAVE_TBA_LO                                                        0x26c
++#define ixSQ_WAVE_TBA_HI                                                        0x26d
++#define ixSQ_WAVE_TMA_LO                                                        0x26e
++#define ixSQ_WAVE_TMA_HI                                                        0x26f
++#define ixSQ_WAVE_TTMP0                                                         0x270
++#define ixSQ_WAVE_TTMP1                                                         0x271
++#define ixSQ_WAVE_TTMP2                                                         0x272
++#define ixSQ_WAVE_TTMP3                                                         0x273
++#define ixSQ_WAVE_TTMP4                                                         0x274
++#define ixSQ_WAVE_TTMP5                                                         0x275
++#define ixSQ_WAVE_TTMP6                                                         0x276
++#define ixSQ_WAVE_TTMP7                                                         0x277
++#define ixSQ_WAVE_TTMP8                                                         0x278
++#define ixSQ_WAVE_TTMP9                                                         0x279
++#define ixSQ_WAVE_TTMP10                                                        0x27a
++#define ixSQ_WAVE_TTMP11                                                        0x27b
++#define mmSQ_DEBUG_STS_GLOBAL                                                   0x2309
++#define mmSQ_DEBUG_STS_GLOBAL2                                                  0x2310
++#define mmSQ_DEBUG_STS_GLOBAL3                                                  0x2311
++#define ixSQ_DEBUG_STS_LOCAL                                                    0x8
++#define ixSQ_DEBUG_CTRL_LOCAL                                                   0x9
++#define mmSH_MEM_BASES                                                          0x230a
++#define mmSH_MEM_APE1_BASE                                                      0x230b
++#define mmSH_MEM_APE1_LIMIT                                                     0x230c
++#define mmSH_MEM_CONFIG                                                         0x230d
++#define mmSQ_THREAD_TRACE_WORD_CMN                                              0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2                                   0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2                                   0x23b1
++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2                             0x23b1
++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2                                 0x23b0
++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2                                 0x23b1
++#define mmSQ_THREAD_TRACE_WORD_WAVE                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_MISC                                             0x23b0
++#define mmSQ_THREAD_TRACE_WORD_WAVE_START                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2                                       0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                                    0x23b0
++#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2                                    0x23b0
++#define mmSQ_THREAD_TRACE_WORD_EVENT                                            0x23b0
++#define mmSQ_THREAD_TRACE_WORD_ISSUE                                            0x23b0
++#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2                                      0x23b0
++#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2                                      0x23b1
++#define mmSQ_WREXEC_EXEC_LO                                                     0x23b1
++#define mmSQ_WREXEC_EXEC_HI                                                     0x23b1
++#define mmSQC_GATCL1_CNTL                                                       0x23b2
++#define mmSQC_ATC_EDC_GATCL1_CNT                                                0x23b3
++#define ixSQ_INTERRUPT_WORD_CMN                                                 0x20c0
++#define ixSQ_INTERRUPT_WORD_AUTO                                                0x20c0
++#define ixSQ_INTERRUPT_WORD_WAVE                                                0x20c0
++#define mmSQ_SOP2                                                               0x237f
++#define mmSQ_VOP1                                                               0x237f
++#define mmSQ_MTBUF_1                                                            0x237f
++#define mmSQ_EXP_1                                                              0x237f
++#define mmSQ_MUBUF_1                                                            0x237f
++#define mmSQ_SMEM_1                                                             0x237f
++#define mmSQ_INST                                                               0x237f
++#define mmSQ_EXP_0                                                              0x237f
++#define mmSQ_MUBUF_0                                                            0x237f
++#define mmSQ_VOP_SDWA                                                           0x237f
++#define mmSQ_VOP3_0                                                             0x237f
++#define mmSQ_VOP2                                                               0x237f
++#define mmSQ_MTBUF_0                                                            0x237f
++#define mmSQ_SOPP                                                               0x237f
++#define mmSQ_FLAT_0                                                             0x237f
++#define mmSQ_VOP3_0_SDST_ENC                                                    0x237f
++#define mmSQ_MIMG_1                                                             0x237f
++#define mmSQ_SOP1                                                               0x237f
++#define mmSQ_SOPC                                                               0x237f
++#define mmSQ_FLAT_1                                                             0x237f
++#define mmSQ_DS_1                                                               0x237f
++#define mmSQ_VOP3_1                                                             0x237f
++#define mmSQ_SMEM_0                                                             0x237f
++#define mmSQ_MIMG_0                                                             0x237f
++#define mmSQ_SOPK                                                               0x237f
++#define mmSQ_DS_0                                                               0x237f
++#define mmSQ_VOP_DPP                                                            0x237f
++#define mmSQ_VOPC                                                               0x237f
++#define mmSQ_VINTRP                                                             0x237f
++#define mmCGTT_SX_CLK_CTRL0                                                     0xf094
++#define mmCGTT_SX_CLK_CTRL1                                                     0xf095
++#define mmCGTT_SX_CLK_CTRL2                                                     0xf096
++#define mmCGTT_SX_CLK_CTRL3                                                     0xf097
++#define mmCGTT_SX_CLK_CTRL4                                                     0xf098
++#define mmSX_DEBUG_BUSY                                                         0x2414
++#define mmSX_DEBUG_BUSY_2                                                       0x2415
++#define mmSX_DEBUG_BUSY_3                                                       0x2416
++#define mmSX_DEBUG_BUSY_4                                                       0x2417
++#define mmSX_DEBUG_1                                                            0x2418
++#define mmSX_PERFCOUNTER0_SELECT                                                0xda40
++#define mmSX_PERFCOUNTER1_SELECT                                                0xda41
++#define mmSX_PERFCOUNTER2_SELECT                                                0xda42
++#define mmSX_PERFCOUNTER3_SELECT                                                0xda43
++#define mmSX_PERFCOUNTER0_SELECT1                                               0xda44
++#define mmSX_PERFCOUNTER1_SELECT1                                               0xda45
++#define mmSX_PERFCOUNTER0_LO                                                    0xd240
++#define mmSX_PERFCOUNTER0_HI                                                    0xd241
++#define mmSX_PERFCOUNTER1_LO                                                    0xd242
++#define mmSX_PERFCOUNTER1_HI                                                    0xd243
++#define mmSX_PERFCOUNTER2_LO                                                    0xd244
++#define mmSX_PERFCOUNTER2_HI                                                    0xd245
++#define mmSX_PERFCOUNTER3_LO                                                    0xd246
++#define mmSX_PERFCOUNTER3_HI                                                    0xd247
++#define mmTCC_CTRL                                                              0x2b80
++#define mmTCC_EDC_CNT                                                           0x2b82
++#define mmTCC_REDUNDANCY                                                        0x2b83
++#define mmTCC_EXE_DISABLE                                                       0x2b84
++#define mmTCC_DSM_CNTL                                                          0x2b85
++#define mmTCC_CGTT_SCLK_CTRL                                                    0xf0ac
++#define mmTCA_CGTT_SCLK_CTRL                                                    0xf0ad
++#define mmTCC_PERFCOUNTER0_SELECT                                               0xdb80
++#define mmTCC_PERFCOUNTER1_SELECT                                               0xdb82
++#define mmTCC_PERFCOUNTER0_SELECT1                                              0xdb81
++#define mmTCC_PERFCOUNTER1_SELECT1                                              0xdb83
++#define mmTCC_PERFCOUNTER2_SELECT                                               0xdb84
++#define mmTCC_PERFCOUNTER3_SELECT                                               0xdb85
++#define mmTCC_PERFCOUNTER0_LO                                                   0xd380
++#define mmTCC_PERFCOUNTER1_LO                                                   0xd382
++#define mmTCC_PERFCOUNTER2_LO                                                   0xd384
++#define mmTCC_PERFCOUNTER3_LO                                                   0xd386
++#define mmTCC_PERFCOUNTER0_HI                                                   0xd381
++#define mmTCC_PERFCOUNTER1_HI                                                   0xd383
++#define mmTCC_PERFCOUNTER2_HI                                                   0xd385
++#define mmTCC_PERFCOUNTER3_HI                                                   0xd387
++#define mmTCA_CTRL                                                              0x2bc0
++#define mmTCA_PERFCOUNTER0_SELECT                                               0xdb90
++#define mmTCA_PERFCOUNTER1_SELECT                                               0xdb92
++#define mmTCA_PERFCOUNTER0_SELECT1                                              0xdb91
++#define mmTCA_PERFCOUNTER1_SELECT1                                              0xdb93
++#define mmTCA_PERFCOUNTER2_SELECT                                               0xdb94
++#define mmTCA_PERFCOUNTER3_SELECT                                               0xdb95
++#define mmTCA_PERFCOUNTER0_LO                                                   0xd390
++#define mmTCA_PERFCOUNTER1_LO                                                   0xd392
++#define mmTCA_PERFCOUNTER2_LO                                                   0xd394
++#define mmTCA_PERFCOUNTER3_LO                                                   0xd396
++#define mmTCA_PERFCOUNTER0_HI                                                   0xd391
++#define mmTCA_PERFCOUNTER1_HI                                                   0xd393
++#define mmTCA_PERFCOUNTER2_HI                                                   0xd395
++#define mmTCA_PERFCOUNTER3_HI                                                   0xd397
++#define mmTA_BC_BASE_ADDR                                                       0xa020
++#define mmTA_BC_BASE_ADDR_HI                                                    0xa021
++#define mmTD_CNTL                                                               0x2525
++#define mmTD_STATUS                                                             0x2526
++#define mmTD_DEBUG_INDEX                                                        0x2528
++#define mmTD_DEBUG_DATA                                                         0x2529
++#define mmTD_DSM_CNTL                                                           0x252f
++#define mmTD_PERFCOUNTER0_SELECT                                                0xdb00
++#define mmTD_PERFCOUNTER1_SELECT                                                0xdb02
++#define mmTD_PERFCOUNTER0_SELECT1                                               0xdb01
++#define mmTD_PERFCOUNTER0_LO                                                    0xd300
++#define mmTD_PERFCOUNTER1_LO                                                    0xd302
++#define mmTD_PERFCOUNTER0_HI                                                    0xd301
++#define mmTD_PERFCOUNTER1_HI                                                    0xd303
++#define mmTD_SCRATCH                                                            0x2533
++#define mmTA_CNTL                                                               0x2541
++#define mmTA_CNTL_AUX                                                           0x2542
++#define mmTA_RESERVED_010C                                                      0x2543
++#define mmTA_CS_BC_BASE_ADDR                                                    0xc380
++#define mmTA_CS_BC_BASE_ADDR_HI                                                 0xc381
++#define mmTA_STATUS                                                             0x2548
++#define mmTA_DEBUG_INDEX                                                        0x254c
++#define mmTA_DEBUG_DATA                                                         0x254d
++#define mmTA_PERFCOUNTER0_SELECT                                                0xdac0
++#define mmTA_PERFCOUNTER1_SELECT                                                0xdac2
++#define mmTA_PERFCOUNTER0_SELECT1                                               0xdac1
++#define mmTA_PERFCOUNTER0_LO                                                    0xd2c0
++#define mmTA_PERFCOUNTER1_LO                                                    0xd2c2
++#define mmTA_PERFCOUNTER0_HI                                                    0xd2c1
++#define mmTA_PERFCOUNTER1_HI                                                    0xd2c3
++#define mmTA_SCRATCH                                                            0x2564
++#define mmSH_HIDDEN_PRIVATE_BASE_VMID                                           0x2580
++#define mmSH_STATIC_MEM_CONFIG                                                  0x2581
++#define mmTCP_INVALIDATE                                                        0x2b00
++#define mmTCP_STATUS                                                            0x2b01
++#define mmTCP_CNTL                                                              0x2b02
++#define mmTCP_CHAN_STEER_LO                                                     0x2b03
++#define mmTCP_CHAN_STEER_HI                                                     0x2b04
++#define mmTCP_ADDR_CONFIG                                                       0x2b05
++#define mmTCP_CREDIT                                                            0x2b06
++#define mmTCP_PERFCOUNTER0_SELECT                                               0xdb40
++#define mmTCP_PERFCOUNTER1_SELECT                                               0xdb42
++#define mmTCP_PERFCOUNTER0_SELECT1                                              0xdb41
++#define mmTCP_PERFCOUNTER1_SELECT1                                              0xdb43
++#define mmTCP_PERFCOUNTER2_SELECT                                               0xdb44
++#define mmTCP_PERFCOUNTER3_SELECT                                               0xdb45
++#define mmTCP_PERFCOUNTER0_LO                                                   0xd340
++#define mmTCP_PERFCOUNTER1_LO                                                   0xd342
++#define mmTCP_PERFCOUNTER2_LO                                                   0xd344
++#define mmTCP_PERFCOUNTER3_LO                                                   0xd346
++#define mmTCP_PERFCOUNTER0_HI                                                   0xd341
++#define mmTCP_PERFCOUNTER1_HI                                                   0xd343
++#define mmTCP_PERFCOUNTER2_HI                                                   0xd345
++#define mmTCP_PERFCOUNTER3_HI                                                   0xd347
++#define mmTCP_BUFFER_ADDR_HASH_CNTL                                             0x2b16
++#define mmTCP_EDC_CNT                                                           0x2b17
++#define mmTC_CFG_L1_LOAD_POLICY0                                                0x2b1a
++#define mmTC_CFG_L1_LOAD_POLICY1                                                0x2b1b
++#define mmTC_CFG_L1_STORE_POLICY                                                0x2b1c
++#define mmTC_CFG_L2_LOAD_POLICY0                                                0x2b1d
++#define mmTC_CFG_L2_LOAD_POLICY1                                                0x2b1e
++#define mmTC_CFG_L2_STORE_POLICY0                                               0x2b1f
++#define mmTC_CFG_L2_STORE_POLICY1                                               0x2b20
++#define mmTC_CFG_L2_ATOMIC_POLICY                                               0x2b21
++#define mmTC_CFG_L1_VOLATILE                                                    0x2b22
++#define mmTC_CFG_L2_VOLATILE                                                    0x2b23
++#define mmTCP_WATCH0_ADDR_H                                                     0x32a0
++#define mmTCP_WATCH1_ADDR_H                                                     0x32a3
++#define mmTCP_WATCH2_ADDR_H                                                     0x32a6
++#define mmTCP_WATCH3_ADDR_H                                                     0x32a9
++#define mmTCP_WATCH0_ADDR_L                                                     0x32a1
++#define mmTCP_WATCH1_ADDR_L                                                     0x32a4
++#define mmTCP_WATCH2_ADDR_L                                                     0x32a7
++#define mmTCP_WATCH3_ADDR_L                                                     0x32aa
++#define mmTCP_WATCH0_CNTL                                                       0x32a2
++#define mmTCP_WATCH1_CNTL                                                       0x32a5
++#define mmTCP_WATCH2_CNTL                                                       0x32a8
++#define mmTCP_WATCH3_CNTL                                                       0x32ab
++#define mmTCP_GATCL1_CNTL                                                       0x32b0
++#define mmTCP_ATC_EDC_GATCL1_CNT                                                0x32b1
++#define mmTCP_GATCL1_DSM_CNTL                                                   0x32b2
++#define mmTCP_DSM_CNTL                                                          0x32b3
++#define mmTCP_CNTL2                                                             0x32b4
++#define mmTD_CGTT_CTRL                                                          0xf09c
++#define mmTA_CGTT_CTRL                                                          0xf09d
++#define mmCGTT_TCP_CLK_CTRL                                                     0xf09e
++#define mmCGTT_TCI_CLK_CTRL                                                     0xf09f
++#define mmTCI_STATUS                                                            0x2b61
++#define mmTCI_CNTL_1                                                            0x2b62
++#define mmTCI_CNTL_2                                                            0x2b63
++#define mmGDS_CONFIG                                                            0x25c0
++#define mmGDS_CNTL_STATUS                                                       0x25c1
++#define mmGDS_ENHANCE2                                                          0x25c2
++#define mmGDS_PROTECTION_FAULT                                                  0x25c3
++#define mmGDS_VM_PROTECTION_FAULT                                               0x25c4
++#define mmGDS_EDC_CNT                                                           0x25c5
++#define mmGDS_EDC_GRBM_CNT                                                      0x25c6
++#define mmGDS_EDC_OA_DED                                                        0x25c7
++#define mmGDS_DEBUG_CNTL                                                        0x25c8
++#define mmGDS_DEBUG_DATA                                                        0x25c9
++#define mmGDS_DSM_CNTL                                                          0x25ca
++#define mmCGTT_GDS_CLK_CTRL                                                     0xf0a0
++#define mmGDS_RD_ADDR                                                           0xc400
++#define mmGDS_RD_DATA                                                           0xc401
++#define mmGDS_RD_BURST_ADDR                                                     0xc402
++#define mmGDS_RD_BURST_COUNT                                                    0xc403
++#define mmGDS_RD_BURST_DATA                                                     0xc404
++#define mmGDS_WR_ADDR                                                           0xc405
++#define mmGDS_WR_DATA                                                           0xc406
++#define mmGDS_WR_BURST_ADDR                                                     0xc407
++#define mmGDS_WR_BURST_DATA                                                     0xc408
++#define mmGDS_WRITE_COMPLETE                                                    0xc409
++#define mmGDS_ATOM_CNTL                                                         0xc40a
++#define mmGDS_ATOM_COMPLETE                                                     0xc40b
++#define mmGDS_ATOM_BASE                                                         0xc40c
++#define mmGDS_ATOM_SIZE                                                         0xc40d
++#define mmGDS_ATOM_OFFSET0                                                      0xc40e
++#define mmGDS_ATOM_OFFSET1                                                      0xc40f
++#define mmGDS_ATOM_DST                                                          0xc410
++#define mmGDS_ATOM_OP                                                           0xc411
++#define mmGDS_ATOM_SRC0                                                         0xc412
++#define mmGDS_ATOM_SRC0_U                                                       0xc413
++#define mmGDS_ATOM_SRC1                                                         0xc414
++#define mmGDS_ATOM_SRC1_U                                                       0xc415
++#define mmGDS_ATOM_READ0                                                        0xc416
++#define mmGDS_ATOM_READ0_U                                                      0xc417
++#define mmGDS_ATOM_READ1                                                        0xc418
++#define mmGDS_ATOM_READ1_U                                                      0xc419
++#define mmGDS_GWS_RESOURCE_CNTL                                                 0xc41a
++#define mmGDS_GWS_RESOURCE                                                      0xc41b
++#define mmGDS_GWS_RESOURCE_CNT                                                  0xc41c
++#define mmGDS_OA_CNTL                                                           0xc41d
++#define mmGDS_OA_COUNTER                                                        0xc41e
++#define mmGDS_OA_ADDRESS                                                        0xc41f
++#define mmGDS_OA_INCDEC                                                         0xc420
++#define mmGDS_OA_RING_SIZE                                                      0xc421
++#define ixGDS_DEBUG_REG0                                                        0x0
++#define ixGDS_DEBUG_REG1                                                        0x1
++#define ixGDS_DEBUG_REG2                                                        0x2
++#define ixGDS_DEBUG_REG3                                                        0x3
++#define ixGDS_DEBUG_REG4                                                        0x4
++#define ixGDS_DEBUG_REG5                                                        0x5
++#define ixGDS_DEBUG_REG6                                                        0x6
++#define mmGDS_PERFCOUNTER0_SELECT                                               0xda80
++#define mmGDS_PERFCOUNTER1_SELECT                                               0xda81
++#define mmGDS_PERFCOUNTER2_SELECT                                               0xda82
++#define mmGDS_PERFCOUNTER3_SELECT                                               0xda83
++#define mmGDS_PERFCOUNTER0_LO                                                   0xd280
++#define mmGDS_PERFCOUNTER1_LO                                                   0xd282
++#define mmGDS_PERFCOUNTER2_LO                                                   0xd284
++#define mmGDS_PERFCOUNTER3_LO                                                   0xd286
++#define mmGDS_PERFCOUNTER0_HI                                                   0xd281
++#define mmGDS_PERFCOUNTER1_HI                                                   0xd283
++#define mmGDS_PERFCOUNTER2_HI                                                   0xd285
++#define mmGDS_PERFCOUNTER3_HI                                                   0xd287
++#define mmGDS_PERFCOUNTER0_SELECT1                                              0xda84
++#define mmGDS_VMID0_BASE                                                        0x3300
++#define mmGDS_VMID1_BASE                                                        0x3302
++#define mmGDS_VMID2_BASE                                                        0x3304
++#define mmGDS_VMID3_BASE                                                        0x3306
++#define mmGDS_VMID4_BASE                                                        0x3308
++#define mmGDS_VMID5_BASE                                                        0x330a
++#define mmGDS_VMID6_BASE                                                        0x330c
++#define mmGDS_VMID7_BASE                                                        0x330e
++#define mmGDS_VMID8_BASE                                                        0x3310
++#define mmGDS_VMID9_BASE                                                        0x3312
++#define mmGDS_VMID10_BASE                                                       0x3314
++#define mmGDS_VMID11_BASE                                                       0x3316
++#define mmGDS_VMID12_BASE                                                       0x3318
++#define mmGDS_VMID13_BASE                                                       0x331a
++#define mmGDS_VMID14_BASE                                                       0x331c
++#define mmGDS_VMID15_BASE                                                       0x331e
++#define mmGDS_VMID0_SIZE                                                        0x3301
++#define mmGDS_VMID1_SIZE                                                        0x3303
++#define mmGDS_VMID2_SIZE                                                        0x3305
++#define mmGDS_VMID3_SIZE                                                        0x3307
++#define mmGDS_VMID4_SIZE                                                        0x3309
++#define mmGDS_VMID5_SIZE                                                        0x330b
++#define mmGDS_VMID6_SIZE                                                        0x330d
++#define mmGDS_VMID7_SIZE                                                        0x330f
++#define mmGDS_VMID8_SIZE                                                        0x3311
++#define mmGDS_VMID9_SIZE                                                        0x3313
++#define mmGDS_VMID10_SIZE                                                       0x3315
++#define mmGDS_VMID11_SIZE                                                       0x3317
++#define mmGDS_VMID12_SIZE                                                       0x3319
++#define mmGDS_VMID13_SIZE                                                       0x331b
++#define mmGDS_VMID14_SIZE                                                       0x331d
++#define mmGDS_VMID15_SIZE                                                       0x331f
++#define mmGDS_GWS_VMID0                                                         0x3320
++#define mmGDS_GWS_VMID1                                                         0x3321
++#define mmGDS_GWS_VMID2                                                         0x3322
++#define mmGDS_GWS_VMID3                                                         0x3323
++#define mmGDS_GWS_VMID4                                                         0x3324
++#define mmGDS_GWS_VMID5                                                         0x3325
++#define mmGDS_GWS_VMID6                                                         0x3326
++#define mmGDS_GWS_VMID7                                                         0x3327
++#define mmGDS_GWS_VMID8                                                         0x3328
++#define mmGDS_GWS_VMID9                                                         0x3329
++#define mmGDS_GWS_VMID10                                                        0x332a
++#define mmGDS_GWS_VMID11                                                        0x332b
++#define mmGDS_GWS_VMID12                                                        0x332c
++#define mmGDS_GWS_VMID13                                                        0x332d
++#define mmGDS_GWS_VMID14                                                        0x332e
++#define mmGDS_GWS_VMID15                                                        0x332f
++#define mmGDS_OA_VMID0                                                          0x3330
++#define mmGDS_OA_VMID1                                                          0x3331
++#define mmGDS_OA_VMID2                                                          0x3332
++#define mmGDS_OA_VMID3                                                          0x3333
++#define mmGDS_OA_VMID4                                                          0x3334
++#define mmGDS_OA_VMID5                                                          0x3335
++#define mmGDS_OA_VMID6                                                          0x3336
++#define mmGDS_OA_VMID7                                                          0x3337
++#define mmGDS_OA_VMID8                                                          0x3338
++#define mmGDS_OA_VMID9                                                          0x3339
++#define mmGDS_OA_VMID10                                                         0x333a
++#define mmGDS_OA_VMID11                                                         0x333b
++#define mmGDS_OA_VMID12                                                         0x333c
++#define mmGDS_OA_VMID13                                                         0x333d
++#define mmGDS_OA_VMID14                                                         0x333e
++#define mmGDS_OA_VMID15                                                         0x333f
++#define mmGDS_GWS_RESET0                                                        0x3344
++#define mmGDS_GWS_RESET1                                                        0x3345
++#define mmGDS_GWS_RESOURCE_RESET                                                0x3346
++#define mmGDS_COMPUTE_MAX_WAVE_ID                                               0x3348
++#define mmGDS_OA_RESET_MASK                                                     0x3349
++#define mmGDS_OA_RESET                                                          0x334a
++#define mmGDS_ENHANCE                                                           0x334b
++#define mmGDS_OA_CGPG_RESTORE                                                   0x334c
++#define mmGDS_CS_CTXSW_STATUS                                                   0x334d
++#define mmGDS_CS_CTXSW_CNT0                                                     0x334e
++#define mmGDS_CS_CTXSW_CNT1                                                     0x334f
++#define mmGDS_CS_CTXSW_CNT2                                                     0x3350
++#define mmGDS_CS_CTXSW_CNT3                                                     0x3351
++#define mmGDS_GFX_CTXSW_STATUS                                                  0x3352
++#define mmGDS_VS_CTXSW_CNT0                                                     0x3353
++#define mmGDS_VS_CTXSW_CNT1                                                     0x3354
++#define mmGDS_VS_CTXSW_CNT2                                                     0x3355
++#define mmGDS_VS_CTXSW_CNT3                                                     0x3356
++#define mmGDS_PS0_CTXSW_CNT0                                                    0x3357
++#define mmGDS_PS1_CTXSW_CNT0                                                    0x335b
++#define mmGDS_PS2_CTXSW_CNT0                                                    0x335f
++#define mmGDS_PS3_CTXSW_CNT0                                                    0x3363
++#define mmGDS_PS4_CTXSW_CNT0                                                    0x3367
++#define mmGDS_PS5_CTXSW_CNT0                                                    0x336b
++#define mmGDS_PS6_CTXSW_CNT0                                                    0x336f
++#define mmGDS_PS7_CTXSW_CNT0                                                    0x3373
++#define mmGDS_PS0_CTXSW_CNT1                                                    0x3358
++#define mmGDS_PS1_CTXSW_CNT1                                                    0x335c
++#define mmGDS_PS2_CTXSW_CNT1                                                    0x3360
++#define mmGDS_PS3_CTXSW_CNT1                                                    0x3364
++#define mmGDS_PS4_CTXSW_CNT1                                                    0x3368
++#define mmGDS_PS5_CTXSW_CNT1                                                    0x336c
++#define mmGDS_PS6_CTXSW_CNT1                                                    0x3370
++#define mmGDS_PS7_CTXSW_CNT1                                                    0x3374
++#define mmGDS_PS0_CTXSW_CNT2                                                    0x3359
++#define mmGDS_PS1_CTXSW_CNT2                                                    0x335d
++#define mmGDS_PS2_CTXSW_CNT2                                                    0x3361
++#define mmGDS_PS3_CTXSW_CNT2                                                    0x3365
++#define mmGDS_PS4_CTXSW_CNT2                                                    0x3369
++#define mmGDS_PS5_CTXSW_CNT2                                                    0x336d
++#define mmGDS_PS6_CTXSW_CNT2                                                    0x3371
++#define mmGDS_PS7_CTXSW_CNT2                                                    0x3375
++#define mmGDS_PS0_CTXSW_CNT3                                                    0x335a
++#define mmGDS_PS1_CTXSW_CNT3                                                    0x335e
++#define mmGDS_PS2_CTXSW_CNT3                                                    0x3362
++#define mmGDS_PS3_CTXSW_CNT3                                                    0x3366
++#define mmGDS_PS4_CTXSW_CNT3                                                    0x336a
++#define mmGDS_PS5_CTXSW_CNT3                                                    0x336e
++#define mmGDS_PS6_CTXSW_CNT3                                                    0x3372
++#define mmGDS_PS7_CTXSW_CNT3                                                    0x3376
++#define mmCS_COPY_STATE                                                         0xa1f3
++#define mmGFX_COPY_STATE                                                        0xa1f4
++#define mmVGT_DRAW_INITIATOR                                                    0xa1fc
++#define mmVGT_EVENT_INITIATOR                                                   0xa2a4
++#define mmVGT_EVENT_ADDRESS_REG                                                 0xa1fe
++#define mmVGT_DMA_BASE_HI                                                       0xa1f9
++#define mmVGT_DMA_BASE                                                          0xa1fa
++#define mmVGT_DMA_INDEX_TYPE                                                    0xa29f
++#define mmVGT_DMA_NUM_INSTANCES                                                 0xa2a2
++#define mmIA_ENHANCE                                                            0xa29c
++#define mmVGT_DMA_SIZE                                                          0xa29d
++#define mmVGT_DMA_MAX_SIZE                                                      0xa29e
++#define mmVGT_DMA_PRIMITIVE_TYPE                                                0x2271
++#define mmVGT_DMA_CONTROL                                                       0x2272
++#define mmVGT_IMMED_DATA                                                        0xa1fd
++#define mmVGT_INDEX_TYPE                                                        0xc243
++#define mmVGT_NUM_INDICES                                                       0xc24c
++#define mmVGT_NUM_INSTANCES                                                     0xc24d
++#define mmVGT_PRIMITIVE_TYPE                                                    0xc242
++#define mmVGT_PRIMITIVEID_EN                                                    0xa2a1
++#define mmVGT_PRIMITIVEID_RESET                                                 0xa2a3
++#define mmVGT_VTX_CNT_EN                                                        0xa2ae
++#define mmVGT_REUSE_OFF                                                         0xa2ad
++#define mmVGT_INSTANCE_STEP_RATE_0                                              0xa2a8
++#define mmVGT_INSTANCE_STEP_RATE_1                                              0xa2a9
++#define mmVGT_MAX_VTX_INDX                                                      0xa100
++#define mmVGT_MIN_VTX_INDX                                                      0xa101
++#define mmVGT_INDX_OFFSET                                                       0xa102
++#define mmVGT_VERTEX_REUSE_BLOCK_CNTL                                           0xa316
++#define mmVGT_OUT_DEALLOC_CNTL                                                  0xa317
++#define mmVGT_MULTI_PRIM_IB_RESET_INDX                                          0xa103
++#define mmVGT_MULTI_PRIM_IB_RESET_EN                                            0xa2a5
++#define mmVGT_ENHANCE                                                           0xa294
++#define mmVGT_OUTPUT_PATH_CNTL                                                  0xa284
++#define mmVGT_HOS_CNTL                                                          0xa285
++#define mmVGT_HOS_MAX_TESS_LEVEL                                                0xa286
++#define mmVGT_HOS_MIN_TESS_LEVEL                                                0xa287
++#define mmVGT_HOS_REUSE_DEPTH                                                   0xa288
++#define mmVGT_GROUP_PRIM_TYPE                                                   0xa289
++#define mmVGT_GROUP_FIRST_DECR                                                  0xa28a
++#define mmVGT_GROUP_DECR                                                        0xa28b
++#define mmVGT_GROUP_VECT_0_CNTL                                                 0xa28c
++#define mmVGT_GROUP_VECT_1_CNTL                                                 0xa28d
++#define mmVGT_GROUP_VECT_0_FMT_CNTL                                             0xa28e
++#define mmVGT_GROUP_VECT_1_FMT_CNTL                                             0xa28f
++#define mmVGT_VTX_VECT_EJECT_REG                                                0x222c
++#define mmVGT_DMA_DATA_FIFO_DEPTH                                               0x222d
++#define mmVGT_DMA_REQ_FIFO_DEPTH                                                0x222e
++#define mmVGT_DRAW_INIT_FIFO_DEPTH                                              0x222f
++#define mmVGT_LAST_COPY_STATE                                                   0x2230
++#define mmCC_GC_SHADER_ARRAY_CONFIG                                             0x226f
++#define mmGC_USER_SHADER_ARRAY_CONFIG                                           0x2270
++#define mmVGT_GS_MODE                                                           0xa290
++#define mmVGT_GS_ONCHIP_CNTL                                                    0xa291
++#define mmVGT_GS_OUT_PRIM_TYPE                                                  0xa29b
++#define mmVGT_CACHE_INVALIDATION                                                0x2231
++#define mmVGT_RESET_DEBUG                                                       0x2232
++#define mmVGT_STRMOUT_DELAY                                                     0x2233
++#define mmVGT_FIFO_DEPTHS                                                       0x2234
++#define mmVGT_GS_PER_ES                                                         0xa295
++#define mmVGT_ES_PER_GS                                                         0xa296
++#define mmVGT_GS_PER_VS                                                         0xa297
++#define mmVGT_GS_VERTEX_REUSE                                                   0x2235
++#define mmVGT_MC_LAT_CNTL                                                       0x2236
++#define mmIA_CNTL_STATUS                                                        0x2237
++#define mmVGT_STRMOUT_CONFIG                                                    0xa2e5
++#define mmVGT_STRMOUT_BUFFER_SIZE_0                                             0xa2b4
++#define mmVGT_STRMOUT_BUFFER_SIZE_1                                             0xa2b8
++#define mmVGT_STRMOUT_BUFFER_SIZE_2                                             0xa2bc
++#define mmVGT_STRMOUT_BUFFER_SIZE_3                                             0xa2c0
++#define mmVGT_STRMOUT_BUFFER_OFFSET_0                                           0xa2b7
++#define mmVGT_STRMOUT_BUFFER_OFFSET_1                                           0xa2bb
++#define mmVGT_STRMOUT_BUFFER_OFFSET_2                                           0xa2bf
++#define mmVGT_STRMOUT_BUFFER_OFFSET_3                                           0xa2c3
++#define mmVGT_STRMOUT_VTX_STRIDE_0                                              0xa2b5
++#define mmVGT_STRMOUT_VTX_STRIDE_1                                              0xa2b9
++#define mmVGT_STRMOUT_VTX_STRIDE_2                                              0xa2bd
++#define mmVGT_STRMOUT_VTX_STRIDE_3                                              0xa2c1
++#define mmVGT_STRMOUT_BUFFER_CONFIG                                             0xa2e6
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                                      0xc244
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                                      0xc245
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                                      0xc246
++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                                      0xc247
++#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                        0xa2ca
++#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                            0xa2cb
++#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                 0xa2cc
++#define mmVGT_GS_MAX_VERT_OUT                                                   0xa2ce
++#define mmVGT_SHADER_STAGES_EN                                                  0xa2d5
++#define mmVGT_DISPATCH_DRAW_INDEX                                               0xa2dd
++#define mmVGT_LS_HS_CONFIG                                                      0xa2d6
++#define mmVGT_DMA_LS_HS_CONFIG                                                  0x2273
++#define mmVGT_TF_PARAM                                                          0xa2db
++#define mmVGT_TESS_DISTRIBUTION                                                 0xa2d4
++#define mmVGT_TF_RING_SIZE                                                      0xc24e
++#define mmVGT_SYS_CONFIG                                                        0x2263
++#define mmVGT_HS_OFFCHIP_PARAM                                                  0xc24f
++#define mmVGT_TF_MEMORY_BASE                                                    0xc250
++#define mmVGT_GS_INSTANCE_CNT                                                   0xa2e4
++#define mmIA_MULTI_VGT_PARAM                                                    0xa2aa
++#define mmVGT_VS_MAX_WAVE_ID                                                    0x2268
++#define mmVGT_ESGS_RING_SIZE                                                    0xc240
++#define mmVGT_GSVS_RING_SIZE                                                    0xc241
++#define mmVGT_GSVS_RING_OFFSET_1                                                0xa298
++#define mmVGT_GSVS_RING_OFFSET_2                                                0xa299
++#define mmVGT_GSVS_RING_OFFSET_3                                                0xa29a
++#define mmVGT_ESGS_RING_ITEMSIZE                                                0xa2ab
++#define mmVGT_GSVS_RING_ITEMSIZE                                                0xa2ac
++#define mmVGT_GS_VERT_ITEMSIZE                                                  0xa2d7
++#define mmVGT_GS_VERT_ITEMSIZE_1                                                0xa2d8
++#define mmVGT_GS_VERT_ITEMSIZE_2                                                0xa2d9
++#define mmVGT_GS_VERT_ITEMSIZE_3                                                0xa2da
++#define mmWD_CNTL_STATUS                                                        0x223f
++#define mmWD_ENHANCE                                                            0xa2a0
++#define mmGFX_PIPE_CONTROL                                                      0x226d
++#define mmGFX_PIPE_PRIORITY                                                     0xf87f
++#define mmCGTT_VGT_CLK_CTRL                                                     0xf084
++#define mmCGTT_IA_CLK_CTRL                                                      0xf085
++#define mmCGTT_WD_CLK_CTRL                                                      0xf086
++#define mmVGT_DEBUG_CNTL                                                        0x2238
++#define mmVGT_DEBUG_DATA                                                        0x2239
++#define mmIA_DEBUG_CNTL                                                         0x223a
++#define mmIA_DEBUG_DATA                                                         0x223b
++#define mmVGT_CNTL_STATUS                                                       0x223c
++#define mmWD_DEBUG_CNTL                                                         0x223d
++#define mmWD_DEBUG_DATA                                                         0x223e
++#define mmWD_QOS                                                                0x2242
++#define mmCC_GC_PRIM_CONFIG                                                     0x2240
++#define mmGC_USER_PRIM_CONFIG                                                   0x2241
++#define ixWD_DEBUG_REG0                                                         0x0
++#define ixWD_DEBUG_REG1                                                         0x1
++#define ixWD_DEBUG_REG2                                                         0x2
++#define ixWD_DEBUG_REG3                                                         0x3
++#define ixWD_DEBUG_REG4                                                         0x4
++#define ixWD_DEBUG_REG5                                                         0x5
++#define ixWD_DEBUG_REG6                                                         0x6
++#define ixWD_DEBUG_REG7                                                         0x7
++#define ixWD_DEBUG_REG8                                                         0x8
++#define ixWD_DEBUG_REG9                                                         0x9
++#define ixWD_DEBUG_REG10                                                        0xa
++#define ixIA_DEBUG_REG0                                                         0x0
++#define ixIA_DEBUG_REG1                                                         0x1
++#define ixIA_DEBUG_REG2                                                         0x2
++#define ixIA_DEBUG_REG3                                                         0x3
++#define ixIA_DEBUG_REG4                                                         0x4
++#define ixIA_DEBUG_REG5                                                         0x5
++#define ixIA_DEBUG_REG6                                                         0x6
++#define ixIA_DEBUG_REG7                                                         0x7
++#define ixIA_DEBUG_REG8                                                         0x8
++#define ixIA_DEBUG_REG9                                                         0x9
++#define ixVGT_DEBUG_REG0                                                        0x0
++#define ixVGT_DEBUG_REG1                                                        0x1
++#define ixVGT_DEBUG_REG2                                                        0x1e
++#define ixVGT_DEBUG_REG3                                                        0x1f
++#define ixVGT_DEBUG_REG4                                                        0x20
++#define ixVGT_DEBUG_REG5                                                        0x21
++#define ixVGT_DEBUG_REG6                                                        0x22
++#define ixVGT_DEBUG_REG7                                                        0x23
++#define ixVGT_DEBUG_REG8                                                        0x8
++#define ixVGT_DEBUG_REG9                                                        0x9
++#define ixVGT_DEBUG_REG10                                                       0xa
++#define ixVGT_DEBUG_REG11                                                       0xb
++#define ixVGT_DEBUG_REG12                                                       0xc
++#define ixVGT_DEBUG_REG13                                                       0xd
++#define ixVGT_DEBUG_REG14                                                       0xe
++#define ixVGT_DEBUG_REG15                                                       0xf
++#define ixVGT_DEBUG_REG16                                                       0x10
++#define ixVGT_DEBUG_REG17                                                       0x11
++#define ixVGT_DEBUG_REG18                                                       0x7
++#define ixVGT_DEBUG_REG19                                                       0x13
++#define ixVGT_DEBUG_REG20                                                       0x14
++#define ixVGT_DEBUG_REG21                                                       0x15
++#define ixVGT_DEBUG_REG22                                                       0x16
++#define ixVGT_DEBUG_REG23                                                       0x17
++#define ixVGT_DEBUG_REG24                                                       0x18
++#define ixVGT_DEBUG_REG25                                                       0x19
++#define ixVGT_DEBUG_REG26                                                       0x24
++#define ixVGT_DEBUG_REG27                                                       0x1b
++#define ixVGT_DEBUG_REG28                                                       0x1c
++#define ixVGT_DEBUG_REG29                                                       0x1d
++#define ixVGT_DEBUG_REG31                                                       0x26
++#define ixVGT_DEBUG_REG32                                                       0x27
++#define ixVGT_DEBUG_REG33                                                       0x28
++#define ixVGT_DEBUG_REG34                                                       0x29
++#define ixVGT_DEBUG_REG36                                                       0x2b
++#define mmVGT_PERFCOUNTER_SEID_MASK                                             0xd894
++#define mmVGT_PERFCOUNTER0_SELECT                                               0xd88c
++#define mmVGT_PERFCOUNTER1_SELECT                                               0xd88d
++#define mmVGT_PERFCOUNTER2_SELECT                                               0xd88e
++#define mmVGT_PERFCOUNTER3_SELECT                                               0xd88f
++#define mmVGT_PERFCOUNTER0_SELECT1                                              0xd890
++#define mmVGT_PERFCOUNTER1_SELECT1                                              0xd891
++#define mmVGT_PERFCOUNTER0_LO                                                   0xd090
++#define mmVGT_PERFCOUNTER1_LO                                                   0xd092
++#define mmVGT_PERFCOUNTER2_LO                                                   0xd094
++#define mmVGT_PERFCOUNTER3_LO                                                   0xd096
++#define mmVGT_PERFCOUNTER0_HI                                                   0xd091
++#define mmVGT_PERFCOUNTER1_HI                                                   0xd093
++#define mmVGT_PERFCOUNTER2_HI                                                   0xd095
++#define mmVGT_PERFCOUNTER3_HI                                                   0xd097
++#define mmIA_PERFCOUNTER0_SELECT                                                0xd884
++#define mmIA_PERFCOUNTER1_SELECT                                                0xd885
++#define mmIA_PERFCOUNTER2_SELECT                                                0xd886
++#define mmIA_PERFCOUNTER3_SELECT                                                0xd887
++#define mmIA_PERFCOUNTER0_SELECT1                                               0xd888
++#define mmIA_PERFCOUNTER0_LO                                                    0xd088
++#define mmIA_PERFCOUNTER1_LO                                                    0xd08a
++#define mmIA_PERFCOUNTER2_LO                                                    0xd08c
++#define mmIA_PERFCOUNTER3_LO                                                    0xd08e
++#define mmIA_PERFCOUNTER0_HI                                                    0xd089
++#define mmIA_PERFCOUNTER1_HI                                                    0xd08b
++#define mmIA_PERFCOUNTER2_HI                                                    0xd08d
++#define mmIA_PERFCOUNTER3_HI                                                    0xd08f
++#define mmWD_PERFCOUNTER0_SELECT                                                0xd880
++#define mmWD_PERFCOUNTER1_SELECT                                                0xd881
++#define mmWD_PERFCOUNTER2_SELECT                                                0xd882
++#define mmWD_PERFCOUNTER3_SELECT                                                0xd883
++#define mmWD_PERFCOUNTER0_LO                                                    0xd080
++#define mmWD_PERFCOUNTER1_LO                                                    0xd082
++#define mmWD_PERFCOUNTER2_LO                                                    0xd084
++#define mmWD_PERFCOUNTER3_LO                                                    0xd086
++#define mmWD_PERFCOUNTER0_HI                                                    0xd081
++#define mmWD_PERFCOUNTER1_HI                                                    0xd083
++#define mmWD_PERFCOUNTER2_HI                                                    0xd085
++#define mmWD_PERFCOUNTER3_HI                                                    0xd087
++#define mmDIDT_IND_INDEX                                                        0x3280
++#define mmDIDT_IND_DATA                                                         0x3281
++#define ixDIDT_SQ_CTRL0                                                         0x0
++#define ixDIDT_SQ_CTRL1                                                         0x1
++#define ixDIDT_SQ_CTRL2                                                         0x2
++#define ixDIDT_SQ_CTRL_OCP                                                      0x3
++#define ixDIDT_SQ_WEIGHT0_3                                                     0x10
++#define ixDIDT_SQ_WEIGHT4_7                                                     0x11
++#define ixDIDT_SQ_WEIGHT8_11                                                    0x12
++#define ixDIDT_DB_CTRL0                                                         0x20
++#define ixDIDT_DB_CTRL1                                                         0x21
++#define ixDIDT_DB_CTRL2                                                         0x22
++#define ixDIDT_DB_CTRL_OCP                                                      0x23
++#define ixDIDT_DB_WEIGHT0_3                                                     0x30
++#define ixDIDT_DB_WEIGHT4_7                                                     0x31
++#define ixDIDT_DB_WEIGHT8_11                                                    0x32
++#define ixDIDT_TD_CTRL0                                                         0x40
++#define ixDIDT_TD_CTRL1                                                         0x41
++#define ixDIDT_TD_CTRL2                                                         0x42
++#define ixDIDT_TD_CTRL_OCP                                                      0x43
++#define ixDIDT_TD_WEIGHT0_3                                                     0x50
++#define ixDIDT_TD_WEIGHT4_7                                                     0x51
++#define ixDIDT_TD_WEIGHT8_11                                                    0x52
++#define ixDIDT_TCP_CTRL0                                                        0x60
++#define ixDIDT_TCP_CTRL1                                                        0x61
++#define ixDIDT_TCP_CTRL2                                                        0x62
++#define ixDIDT_TCP_CTRL_OCP                                                     0x63
++#define ixDIDT_TCP_WEIGHT0_3                                                    0x70
++#define ixDIDT_TCP_WEIGHT4_7                                                    0x71
++#define ixDIDT_TCP_WEIGHT8_11                                                   0x72
++#define ixDIDT_DBR_CTRL0                                                        0x80
++#define ixDIDT_DBR_CTRL1                                                        0x81
++#define ixDIDT_DBR_CTRL2                                                        0x82
++#define ixDIDT_DBR_CTRL_OCP                                                     0x83
++#define ixDIDT_DBR_WEIGHT0_3                                                    0x90
++#define ixDIDT_DBR_WEIGHT4_7                                                    0x91
++#define ixDIDT_DBR_WEIGHT8_11                                                   0x92
++
++#endif /* GFX_8_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h
+new file mode 100644
+index 0000000..43386c2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h
+@@ -0,0 +1,6858 @@
++/*
++ * GFX_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_8_0_ENUM_H
++#define GFX_8_0_ENUM_H
++
++typedef enum SurfaceNumber {
++	NUMBER_UNORM                                     = 0x0,
++	NUMBER_SNORM                                     = 0x1,
++	NUMBER_USCALED                                   = 0x2,
++	NUMBER_SSCALED                                   = 0x3,
++	NUMBER_UINT                                      = 0x4,
++	NUMBER_SINT                                      = 0x5,
++	NUMBER_SRGB                                      = 0x6,
++	NUMBER_FLOAT                                     = 0x7,
++} SurfaceNumber;
++typedef enum SurfaceSwap {
++	SWAP_STD                                         = 0x0,
++	SWAP_ALT                                         = 0x1,
++	SWAP_STD_REV                                     = 0x2,
++	SWAP_ALT_REV                                     = 0x3,
++} SurfaceSwap;
++typedef enum CBMode {
++	CB_DISABLE                                       = 0x0,
++	CB_NORMAL                                        = 0x1,
++	CB_ELIMINATE_FAST_CLEAR                          = 0x2,
++	CB_RESOLVE                                       = 0x3,
++	CB_DECOMPRESS                                    = 0x4,
++	CB_FMASK_DECOMPRESS                              = 0x5,
++	CB_DCC_DECOMPRESS                                = 0x6,
++} CBMode;
++typedef enum RoundMode {
++	ROUND_BY_HALF                                    = 0x0,
++	ROUND_TRUNCATE                                   = 0x1,
++} RoundMode;
++typedef enum SourceFormat {
++	EXPORT_4C_32BPC                                  = 0x0,
++	EXPORT_4C_16BPC                                  = 0x1,
++	EXPORT_2C_32BPC_GR                               = 0x2,
++	EXPORT_2C_32BPC_AR                               = 0x3,
++} SourceFormat;
++typedef enum BlendOp {
++	BLEND_ZERO                                       = 0x0,
++	BLEND_ONE                                        = 0x1,
++	BLEND_SRC_COLOR                                  = 0x2,
++	BLEND_ONE_MINUS_SRC_COLOR                        = 0x3,
++	BLEND_SRC_ALPHA                                  = 0x4,
++	BLEND_ONE_MINUS_SRC_ALPHA                        = 0x5,
++	BLEND_DST_ALPHA                                  = 0x6,
++	BLEND_ONE_MINUS_DST_ALPHA                        = 0x7,
++	BLEND_DST_COLOR                                  = 0x8,
++	BLEND_ONE_MINUS_DST_COLOR                        = 0x9,
++	BLEND_SRC_ALPHA_SATURATE                         = 0xa,
++	BLEND_BOTH_SRC_ALPHA                             = 0xb,
++	BLEND_BOTH_INV_SRC_ALPHA                         = 0xc,
++	BLEND_CONSTANT_COLOR                             = 0xd,
++	BLEND_ONE_MINUS_CONSTANT_COLOR                   = 0xe,
++	BLEND_SRC1_COLOR                                 = 0xf,
++	BLEND_INV_SRC1_COLOR                             = 0x10,
++	BLEND_SRC1_ALPHA                                 = 0x11,
++	BLEND_INV_SRC1_ALPHA                             = 0x12,
++	BLEND_CONSTANT_ALPHA                             = 0x13,
++	BLEND_ONE_MINUS_CONSTANT_ALPHA                   = 0x14,
++} BlendOp;
++typedef enum CombFunc {
++	COMB_DST_PLUS_SRC                                = 0x0,
++	COMB_SRC_MINUS_DST                               = 0x1,
++	COMB_MIN_DST_SRC                                 = 0x2,
++	COMB_MAX_DST_SRC                                 = 0x3,
++	COMB_DST_MINUS_SRC                               = 0x4,
++} CombFunc;
++typedef enum BlendOpt {
++	FORCE_OPT_AUTO                                   = 0x0,
++	FORCE_OPT_DISABLE                                = 0x1,
++	FORCE_OPT_ENABLE_IF_SRC_A_0                      = 0x2,
++	FORCE_OPT_ENABLE_IF_SRC_RGB_0                    = 0x3,
++	FORCE_OPT_ENABLE_IF_SRC_ARGB_0                   = 0x4,
++	FORCE_OPT_ENABLE_IF_SRC_A_1                      = 0x5,
++	FORCE_OPT_ENABLE_IF_SRC_RGB_1                    = 0x6,
++	FORCE_OPT_ENABLE_IF_SRC_ARGB_1                   = 0x7,
++} BlendOpt;
++typedef enum CmaskCode {
++	CMASK_CLR00_F0                                   = 0x0,
++	CMASK_CLR00_F1                                   = 0x1,
++	CMASK_CLR00_F2                                   = 0x2,
++	CMASK_CLR00_FX                                   = 0x3,
++	CMASK_CLR01_F0                                   = 0x4,
++	CMASK_CLR01_F1                                   = 0x5,
++	CMASK_CLR01_F2                                   = 0x6,
++	CMASK_CLR01_FX                                   = 0x7,
++	CMASK_CLR10_F0                                   = 0x8,
++	CMASK_CLR10_F1                                   = 0x9,
++	CMASK_CLR10_F2                                   = 0xa,
++	CMASK_CLR10_FX                                   = 0xb,
++	CMASK_CLR11_F0                                   = 0xc,
++	CMASK_CLR11_F1                                   = 0xd,
++	CMASK_CLR11_F2                                   = 0xe,
++	CMASK_CLR11_FX                                   = 0xf,
++} CmaskCode;
++typedef enum CmaskAddr {
++	CMASK_ADDR_TILED                                 = 0x0,
++	CMASK_ADDR_LINEAR                                = 0x1,
++	CMASK_ADDR_COMPATIBLE                            = 0x2,
++} CmaskAddr;
++typedef enum CBPerfSel {
++	CB_PERF_SEL_NONE                                 = 0x0,
++	CB_PERF_SEL_BUSY                                 = 0x1,
++	CB_PERF_SEL_CORE_SCLK_VLD                        = 0x2,
++	CB_PERF_SEL_REG_SCLK0_VLD                        = 0x3,
++	CB_PERF_SEL_REG_SCLK1_VLD                        = 0x4,
++	CB_PERF_SEL_DRAWN_QUAD                           = 0x5,
++	CB_PERF_SEL_DRAWN_PIXEL                          = 0x6,
++	CB_PERF_SEL_DRAWN_QUAD_FRAGMENT                  = 0x7,
++	CB_PERF_SEL_DRAWN_TILE                           = 0x8,
++	CB_PERF_SEL_DB_CB_TILE_VALID_READY               = 0x9,
++	CB_PERF_SEL_DB_CB_TILE_VALID_READYB              = 0xa,
++	CB_PERF_SEL_DB_CB_TILE_VALIDB_READY              = 0xb,
++	CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB             = 0xc,
++	CB_PERF_SEL_CM_FC_TILE_VALID_READY               = 0xd,
++	CB_PERF_SEL_CM_FC_TILE_VALID_READYB              = 0xe,
++	CB_PERF_SEL_CM_FC_TILE_VALIDB_READY              = 0xf,
++	CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB             = 0x10,
++	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY          = 0x11,
++	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB         = 0x12,
++	CB_PERF_SEL_DB_CB_LQUAD_VALID_READY              = 0x13,
++	CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB             = 0x14,
++	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY             = 0x15,
++	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB            = 0x16,
++	CB_PERF_SEL_LQUAD_NO_TILE                        = 0x17,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R          = 0x18,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR         = 0x19,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR         = 0x1a,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR       = 0x1b,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR     = 0x1c,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
++	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
++	CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT    = 0x1f,
++	CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID         = 0x20,
++	CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
++	CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK      = 0x22,
++	CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL         = 0x23,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY            = 0x24,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB           = 0x25,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY           = 0x26,
++	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB          = 0x27,
++	CB_PERF_SEL_FOP_IN_VALID_READY                   = 0x28,
++	CB_PERF_SEL_FOP_IN_VALID_READYB                  = 0x29,
++	CB_PERF_SEL_FOP_IN_VALIDB_READY                  = 0x2a,
++	CB_PERF_SEL_FOP_IN_VALIDB_READYB                 = 0x2b,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY           = 0x2c,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB          = 0x2d,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY          = 0x2e,
++	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB         = 0x2f,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY            = 0x30,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB           = 0x31,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY           = 0x32,
++	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB          = 0x33,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY            = 0x34,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB           = 0x35,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY           = 0x36,
++	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB          = 0x37,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY        = 0x38,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB       = 0x39,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY       = 0x3a,
++	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB      = 0x3b,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY         = 0x3c,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB        = 0x3d,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY        = 0x3e,
++	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB       = 0x3f,
++	CB_PERF_SEL_CC_BC_CS_FRAG_VALID                  = 0x40,
++	CB_PERF_SEL_CM_CACHE_HIT                         = 0x41,
++	CB_PERF_SEL_CM_CACHE_TAG_MISS                    = 0x42,
++	CB_PERF_SEL_CM_CACHE_SECTOR_MISS                 = 0x43,
++	CB_PERF_SEL_CM_CACHE_REEVICTION_STALL            = 0x44,
++	CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
++	CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
++	CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
++	CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL           = 0x48,
++	CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL          = 0x49,
++	CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL            = 0x4a,
++	CB_PERF_SEL_CM_CACHE_STALL                       = 0x4b,
++	CB_PERF_SEL_CM_CACHE_FLUSH                       = 0x4c,
++	CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED                = 0x4d,
++	CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED             = 0x4e,
++	CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED       = 0x4f,
++	CB_PERF_SEL_FC_CACHE_HIT                         = 0x50,
++	CB_PERF_SEL_FC_CACHE_TAG_MISS                    = 0x51,
++	CB_PERF_SEL_FC_CACHE_SECTOR_MISS                 = 0x52,
++	CB_PERF_SEL_FC_CACHE_REEVICTION_STALL            = 0x53,
++	CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
++	CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
++	CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
++	CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL           = 0x57,
++	CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL          = 0x58,
++	CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL            = 0x59,
++	CB_PERF_SEL_FC_CACHE_STALL                       = 0x5a,
++	CB_PERF_SEL_FC_CACHE_FLUSH                       = 0x5b,
++	CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED                = 0x5c,
++	CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED             = 0x5d,
++	CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x5e,
++	CB_PERF_SEL_CC_CACHE_HIT                         = 0x5f,
++	CB_PERF_SEL_CC_CACHE_TAG_MISS                    = 0x60,
++	CB_PERF_SEL_CC_CACHE_SECTOR_MISS                 = 0x61,
++	CB_PERF_SEL_CC_CACHE_REEVICTION_STALL            = 0x62,
++	CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
++	CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
++	CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
++	CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL           = 0x66,
++	CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL          = 0x67,
++	CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL            = 0x68,
++	CB_PERF_SEL_CC_CACHE_STALL                       = 0x69,
++	CB_PERF_SEL_CC_CACHE_FLUSH                       = 0x6a,
++	CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED                = 0x6b,
++	CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED             = 0x6c,
++	CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x6d,
++	CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION        = 0x6e,
++	CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC      = 0x6f,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY             = 0x70,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB            = 0x71,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY            = 0x72,
++	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB           = 0x73,
++	CB_PERF_SEL_CM_MC_WRITE_REQUEST                  = 0x74,
++	CB_PERF_SEL_FC_MC_WRITE_REQUEST                  = 0x75,
++	CB_PERF_SEL_CC_MC_WRITE_REQUEST                  = 0x76,
++	CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x77,
++	CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x78,
++	CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x79,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY             = 0x7a,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB            = 0x7b,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY            = 0x7c,
++	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB           = 0x7d,
++	CB_PERF_SEL_CM_MC_READ_REQUEST                   = 0x7e,
++	CB_PERF_SEL_FC_MC_READ_REQUEST                   = 0x7f,
++	CB_PERF_SEL_CC_MC_READ_REQUEST                   = 0x80,
++	CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT        = 0x81,
++	CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT        = 0x82,
++	CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT        = 0x83,
++	CB_PERF_SEL_CM_TQ_FULL                           = 0x84,
++	CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL      = 0x85,
++	CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL              = 0x86,
++	CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL              = 0x87,
++	CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL   = 0x88,
++	CB_PERF_SEL_FOP_FMASK_RAW_STALL                  = 0x89,
++	CB_PERF_SEL_FOP_FMASK_BYPASS_STALL               = 0x8a,
++	CB_PERF_SEL_CC_SF_FULL                           = 0x8b,
++	CB_PERF_SEL_CC_RB_FULL                           = 0x8c,
++	CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL     = 0x8d,
++	CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL      = 0x8e,
++	CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL             = 0x8f,
++	CB_PERF_SEL_EVENT                                = 0x90,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH_TS                 = 0x91,
++	CB_PERF_SEL_EVENT_CONTEXT_DONE                   = 0x92,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH                    = 0x93,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT   = 0x94,
++	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT      = 0x95,
++	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS       = 0x96,
++	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META          = 0x97,
++	CB_PERF_SEL_CC_SURFACE_SYNC                      = 0x98,
++	CB_PERF_SEL_CMASK_READ_DATA_0xC                  = 0x99,
++	CB_PERF_SEL_CMASK_READ_DATA_0xD                  = 0x9a,
++	CB_PERF_SEL_CMASK_READ_DATA_0xE                  = 0x9b,
++	CB_PERF_SEL_CMASK_READ_DATA_0xF                  = 0x9c,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xC                 = 0x9d,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xD                 = 0x9e,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xE                 = 0x9f,
++	CB_PERF_SEL_CMASK_WRITE_DATA_0xF                 = 0xa0,
++	CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT              = 0xa1,
++	CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT         = 0xa2,
++	CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT      = 0xa3,
++	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE    = 0xa4,
++	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE   = 0xa5,
++	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE   = 0xa6,
++	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE   = 0xa7,
++	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE   = 0xa8,
++	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE   = 0xa9,
++	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE   = 0xaa,
++	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE   = 0xab,
++	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE     = 0xac,
++	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE    = 0xad,
++	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE    = 0xae,
++	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE    = 0xaf,
++	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE    = 0xb0,
++	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE    = 0xb1,
++	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE    = 0xb2,
++	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE    = 0xb3,
++	CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT                = 0xb4,
++	CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS               = 0xb5,
++	CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS               = 0xb6,
++	CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS               = 0xb7,
++	CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS               = 0xb8,
++	CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS               = 0xb9,
++	CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS               = 0xba,
++	CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT              = 0xbb,
++	CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS             = 0xbc,
++	CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS             = 0xbd,
++	CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS             = 0xbe,
++	CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS             = 0xbf,
++	CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS             = 0xc0,
++	CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS             = 0xc1,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_0                = 0xc2,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_1                = 0xc3,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_2                = 0xc4,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_3                = 0xc5,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_4                = 0xc6,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_5                = 0xc7,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_6                = 0xc8,
++	CB_PERF_SEL_QUAD_READS_FRAGMENT_7                = 0xc9,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0               = 0xca,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1               = 0xcb,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2               = 0xcc,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3               = 0xcd,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4               = 0xce,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5               = 0xcf,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6               = 0xd0,
++	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7               = 0xd1,
++	CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST         = 0xd2,
++	CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS          = 0xd3,
++	CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS        = 0xd4,
++	CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
++	CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
++	CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED       = 0xd7,
++	CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST      = 0xd8,
++	CB_PERF_SEL_DRAWN_BUSY                           = 0xd9,
++	CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY              = 0xda,
++	CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY               = 0xdb,
++	CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY               = 0xdc,
++	CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY               = 0xdd,
++	CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
++	CB_PERF_SEL_FC_SEQUENCER_CLEAR                   = 0xdf,
++	CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR    = 0xe0,
++	CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS        = 0xe1,
++	CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
++	CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL             = 0xe3,
++	CB_PERF_SEL_FC_DOC_IS_STALLED                    = 0xe4,
++	CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED             = 0xe5,
++	CB_PERF_SEL_FC_DOC_MRTS_COMBINED                 = 0xe6,
++	CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS                = 0xe7,
++	CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT                 = 0xe8,
++	CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS                = 0xe9,
++	CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT                 = 0xea,
++	CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL         = 0xeb,
++	CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR            = 0xec,
++	CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS           = 0xed,
++	CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS           = 0xee,
++	CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS           = 0xef,
++	CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS     = 0xf0,
++	CB_PERF_SEL_FC_DCC_CACHE_HIT                     = 0xf1,
++	CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS                = 0xf2,
++	CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS             = 0xf3,
++	CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL        = 0xf4,
++	CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
++	CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
++	CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
++	CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL       = 0xf8,
++	CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL      = 0xf9,
++	CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL        = 0xfa,
++	CB_PERF_SEL_FC_DCC_CACHE_STALL                   = 0xfb,
++	CB_PERF_SEL_FC_DCC_CACHE_FLUSH                   = 0xfc,
++	CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED            = 0xfd,
++	CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED         = 0xfe,
++	CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED   = 0xff,
++	CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT             = 0x100,
++	CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST              = 0x101,
++	CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT   = 0x102,
++	CB_PERF_SEL_FC_MC_DCC_READ_REQUEST               = 0x103,
++	CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT    = 0x104,
++	CB_PERF_SEL_CC_DCC_RDREQ_STALL                   = 0x105,
++	CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN            = 0x106,
++	CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT           = 0x107,
++	CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN              = 0x108,
++	CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT             = 0x109,
++	CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR              = 0x10a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1     = 0x10b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1       = 0x11a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2       = 0x11f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3       = 0x124,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x15c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x15d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x163,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x164,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x16b,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x16c,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x172,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x173,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1        = 0x174,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2        = 0x175,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3        = 0x176,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4        = 0x177,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5        = 0x178,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6        = 0x179,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7        = 0x17a,
++	CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED       = 0x17b,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1           = 0x17c,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1           = 0x17d,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2           = 0x17e,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3           = 0x17f,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1           = 0x180,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2           = 0x181,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3           = 0x182,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4           = 0x183,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5           = 0x184,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1           = 0x185,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2           = 0x186,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3           = 0x187,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4           = 0x188,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5           = 0x189,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6           = 0x18a,
++	CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7           = 0x18b,
++} CBPerfSel;
++typedef enum CBPerfOpFilterSel {
++	CB_PERF_OP_FILTER_SEL_WRITE_ONLY                 = 0x0,
++	CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION          = 0x1,
++	CB_PERF_OP_FILTER_SEL_RESOLVE                    = 0x2,
++	CB_PERF_OP_FILTER_SEL_DECOMPRESS                 = 0x3,
++	CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS           = 0x4,
++	CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR       = 0x5,
++} CBPerfOpFilterSel;
++typedef enum CBPerfClearFilterSel {
++	CB_PERF_CLEAR_FILTER_SEL_NONCLEAR                = 0x0,
++	CB_PERF_CLEAR_FILTER_SEL_CLEAR                   = 0x1,
++} CBPerfClearFilterSel;
++typedef enum CP_RING_ID {
++	RINGID0                                          = 0x0,
++	RINGID1                                          = 0x1,
++	RINGID2                                          = 0x2,
++	RINGID3                                          = 0x3,
++} CP_RING_ID;
++typedef enum CP_PIPE_ID {
++	PIPE_ID0                                         = 0x0,
++	PIPE_ID1                                         = 0x1,
++	PIPE_ID2                                         = 0x2,
++	PIPE_ID3                                         = 0x3,
++} CP_PIPE_ID;
++typedef enum CP_ME_ID {
++	ME_ID0                                           = 0x0,
++	ME_ID1                                           = 0x1,
++	ME_ID2                                           = 0x2,
++	ME_ID3                                           = 0x3,
++} CP_ME_ID;
++typedef enum SPM_PERFMON_STATE {
++	STRM_PERFMON_STATE_DISABLE_AND_RESET             = 0x0,
++	STRM_PERFMON_STATE_START_COUNTING                = 0x1,
++	STRM_PERFMON_STATE_STOP_COUNTING                 = 0x2,
++	STRM_PERFMON_STATE_RESERVED_3                    = 0x3,
++	STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM     = 0x4,
++	STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM        = 0x5,
++} SPM_PERFMON_STATE;
++typedef enum CP_PERFMON_STATE {
++	CP_PERFMON_STATE_DISABLE_AND_RESET               = 0x0,
++	CP_PERFMON_STATE_START_COUNTING                  = 0x1,
++	CP_PERFMON_STATE_STOP_COUNTING                   = 0x2,
++	CP_PERFMON_STATE_RESERVED_3                      = 0x3,
++	CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM       = 0x4,
++	CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM          = 0x5,
++} CP_PERFMON_STATE;
++typedef enum CP_PERFMON_ENABLE_MODE {
++	CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT              = 0x0,
++	CP_PERFMON_ENABLE_MODE_RESERVED_1                = 0x1,
++	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE        = 0x2,
++	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE       = 0x3,
++} CP_PERFMON_ENABLE_MODE;
++typedef enum CPG_PERFCOUNT_SEL {
++	CPG_PERF_SEL_ALWAYS_COUNT                        = 0x0,
++	CPG_PERF_SEL_RBIU_FIFO_FULL                      = 0x1,
++	CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR             = 0x2,
++	CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL          = 0x3,
++	CPG_PERF_SEL_CP_GRBM_DWORDS_SENT                 = 0x4,
++	CPG_PERF_SEL_ME_PARSER_BUSY                      = 0x5,
++	CPG_PERF_SEL_COUNT_TYPE0_PACKETS                 = 0x6,
++	CPG_PERF_SEL_COUNT_TYPE3_PACKETS                 = 0x7,
++	CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0x8,
++	CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS              = 0x9,
++	CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS          = 0xa,
++	CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS          = 0xb,
++	CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ             = 0xc,
++	CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ            = 0xd,
++	CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX          = 0xe,
++	CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS        = 0xf,
++	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE        = 0x10,
++	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM   = 0x11,
++	CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY            = 0x12,
++	CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY            = 0x13,
++	CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY           = 0x14,
++	CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ       = 0x15,
++	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP        = 0x16,
++	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ        = 0x17,
++	CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX     = 0x18,
++	CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU          = 0x19,
++	CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS        = 0x1a,
++	CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH         = 0x1b,
++	CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER               = 0x1c,
++	CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER             = 0x1d,
++	CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS     = 0x1e,
++	CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY       = 0x1f,
++	CPG_PERF_SEL_DYNAMIC_CLK_VALID                   = 0x20,
++	CPG_PERF_SEL_REGISTER_CLK_VALID                  = 0x21,
++	CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT              = 0x22,
++	CPG_PERF_SEL_MIU_READ_REQUEST_SENT               = 0x23,
++	CPG_PERF_SEL_CE_STALL_RAM_DUMP                   = 0x24,
++	CPG_PERF_SEL_CE_STALL_RAM_WRITE                  = 0x25,
++	CPG_PERF_SEL_CE_STALL_ON_INC_FIFO                = 0x26,
++	CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO             = 0x27,
++	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU           = 0x28,
++	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ           = 0x29,
++	CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG          = 0x2a,
++	CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER              = 0x2b,
++	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x2c,
++	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS             = 0x2d,
++	CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x2e,
++	CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x2f,
++	CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x30,
++} CPG_PERFCOUNT_SEL;
++typedef enum CPF_PERFCOUNT_SEL {
++	CPF_PERF_SEL_ALWAYS_COUNT                        = 0x0,
++	CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE      = 0x1,
++	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE        = 0x2,
++	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS        = 0x3,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING          = 0x4,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1           = 0x5,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2           = 0x6,
++	CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE         = 0x7,
++	CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS       = 0x8,
++	CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR                 = 0x9,
++	CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR              = 0xa,
++	CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0xb,
++	CPF_PERF_SEL_GRBM_DWORDS_SENT                    = 0xc,
++	CPF_PERF_SEL_DYNAMIC_CLOCK_VALID                 = 0xd,
++	CPF_PERF_SEL_REGISTER_CLOCK_VALID                = 0xe,
++	CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND              = 0xf,
++	CPF_PERF_SEL_MIU_READ_REQUEST_SEND               = 0x10,
++	CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x11,
++	CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x12,
++	CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x13,
++} CPF_PERFCOUNT_SEL;
++typedef enum CPC_PERFCOUNT_SEL {
++	CPC_PERF_SEL_ALWAYS_COUNT                        = 0x0,
++	CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE             = 0x1,
++	CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION           = 0x2,
++	CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE             = 0x3,
++	CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE             = 0x4,
++	CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x5,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY        = 0x6,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF   = 0x7,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ         = 0x8,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ          = 0x9,
++	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE         = 0xa,
++	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ          = 0xb,
++	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF     = 0xc,
++	CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE          = 0xd,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY        = 0xe,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF   = 0xf,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ         = 0x10,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ          = 0x11,
++	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE         = 0x12,
++	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ          = 0x13,
++	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF     = 0x14,
++	CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE          = 0x15,
++	CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x16,
++	CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x17,
++	CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x18,
++} CPC_PERFCOUNT_SEL;
++typedef enum CP_ALPHA_TAG_RAM_SEL {
++	CPG_TAG_RAM                                      = 0x0,
++	CPC_TAG_RAM                                      = 0x1,
++	CPF_TAG_RAM                                      = 0x2,
++	RSV_TAG_RAM                                      = 0x3,
++} CP_ALPHA_TAG_RAM_SEL;
++#define SEM_ECC_ERROR                             0x0
++#define SEM_RESERVED                              0x1
++#define SEM_FAILED                                0x2
++#define SEM_PASSED                                0x3
++#define IQ_QUEUE_SLEEP                            0x0
++#define IQ_OFFLOAD_RETRY                          0x1
++#define IQ_SCH_WAVE_MSG                           0x2
++#define IQ_SEM_REARM                              0x3
++#define IQ_DEQUEUE_RETRY                          0x4
++#define IQ_INTR_TYPE_PQ                           0x0
++#define IQ_INTR_TYPE_IB                           0x1
++#define IQ_INTR_TYPE_MQD                          0x2
++#define VMID_SZ                                   0x4
++#define CONFIG_SPACE_START                        0x2000
++#define CONFIG_SPACE_END                          0x9fff
++#define CONFIG_SPACE1_START                       0x2000
++#define CONFIG_SPACE1_END                         0x2bff
++#define CONFIG_SPACE2_START                       0x3000
++#define CONFIG_SPACE2_END                         0x9fff
++#define UCONFIG_SPACE_START                       0xc000
++#define UCONFIG_SPACE_END                         0xffff
++#define PERSISTENT_SPACE_START                    0x2c00
++#define PERSISTENT_SPACE_END                      0x2fff
++#define CONTEXT_SPACE_START                       0xa000
++#define CONTEXT_SPACE_END                         0xbfff
++typedef enum ForceControl {
++	FORCE_OFF                                        = 0x0,
++	FORCE_ENABLE                                     = 0x1,
++	FORCE_DISABLE                                    = 0x2,
++	FORCE_RESERVED                                   = 0x3,
++} ForceControl;
++typedef enum ZSamplePosition {
++	Z_SAMPLE_CENTER                                  = 0x0,
++	Z_SAMPLE_CENTROID                                = 0x1,
++} ZSamplePosition;
++typedef enum ZOrder {
++	LATE_Z                                           = 0x0,
++	EARLY_Z_THEN_LATE_Z                              = 0x1,
++	RE_Z                                             = 0x2,
++	EARLY_Z_THEN_RE_Z                                = 0x3,
++} ZOrder;
++typedef enum ZpassControl {
++	ZPASS_DISABLE                                    = 0x0,
++	ZPASS_SAMPLES                                    = 0x1,
++	ZPASS_PIXELS                                     = 0x2,
++} ZpassControl;
++typedef enum ZModeForce {
++	NO_FORCE                                         = 0x0,
++	FORCE_EARLY_Z                                    = 0x1,
++	FORCE_LATE_Z                                     = 0x2,
++	FORCE_RE_Z                                       = 0x3,
++} ZModeForce;
++typedef enum ZLimitSumm {
++	FORCE_SUMM_OFF                                   = 0x0,
++	FORCE_SUMM_MINZ                                  = 0x1,
++	FORCE_SUMM_MAXZ                                  = 0x2,
++	FORCE_SUMM_BOTH                                  = 0x3,
++} ZLimitSumm;
++typedef enum CompareFrag {
++	FRAG_NEVER                                       = 0x0,
++	FRAG_LESS                                        = 0x1,
++	FRAG_EQUAL                                       = 0x2,
++	FRAG_LEQUAL                                      = 0x3,
++	FRAG_GREATER                                     = 0x4,
++	FRAG_NOTEQUAL                                    = 0x5,
++	FRAG_GEQUAL                                      = 0x6,
++	FRAG_ALWAYS                                      = 0x7,
++} CompareFrag;
++typedef enum StencilOp {
++	STENCIL_KEEP                                     = 0x0,
++	STENCIL_ZERO                                     = 0x1,
++	STENCIL_ONES                                     = 0x2,
++	STENCIL_REPLACE_TEST                             = 0x3,
++	STENCIL_REPLACE_OP                               = 0x4,
++	STENCIL_ADD_CLAMP                                = 0x5,
++	STENCIL_SUB_CLAMP                                = 0x6,
++	STENCIL_INVERT                                   = 0x7,
++	STENCIL_ADD_WRAP                                 = 0x8,
++	STENCIL_SUB_WRAP                                 = 0x9,
++	STENCIL_AND                                      = 0xa,
++	STENCIL_OR                                       = 0xb,
++	STENCIL_XOR                                      = 0xc,
++	STENCIL_NAND                                     = 0xd,
++	STENCIL_NOR                                      = 0xe,
++	STENCIL_XNOR                                     = 0xf,
++} StencilOp;
++typedef enum ConservativeZExport {
++	EXPORT_ANY_Z                                     = 0x0,
++	EXPORT_LESS_THAN_Z                               = 0x1,
++	EXPORT_GREATER_THAN_Z                            = 0x2,
++	EXPORT_RESERVED                                  = 0x3,
++} ConservativeZExport;
++typedef enum DbPSLControl {
++	PSLC_AUTO                                        = 0x0,
++	PSLC_ON_HANG_ONLY                                = 0x1,
++	PSLC_ASAP                                        = 0x2,
++	PSLC_COUNTDOWN                                   = 0x3,
++} DbPSLControl;
++typedef enum PerfCounter_Vals {
++	DB_PERF_SEL_SC_DB_tile_sends                     = 0x0,
++	DB_PERF_SEL_SC_DB_tile_busy                      = 0x1,
++	DB_PERF_SEL_SC_DB_tile_stalls                    = 0x2,
++	DB_PERF_SEL_SC_DB_tile_events                    = 0x3,
++	DB_PERF_SEL_SC_DB_tile_tiles                     = 0x4,
++	DB_PERF_SEL_SC_DB_tile_covered                   = 0x5,
++	DB_PERF_SEL_hiz_tc_read_starved                  = 0x6,
++	DB_PERF_SEL_hiz_tc_write_stall                   = 0x7,
++	DB_PERF_SEL_hiz_qtiles_culled                    = 0x8,
++	DB_PERF_SEL_his_qtiles_culled                    = 0x9,
++	DB_PERF_SEL_DB_SC_tile_sends                     = 0xa,
++	DB_PERF_SEL_DB_SC_tile_busy                      = 0xb,
++	DB_PERF_SEL_DB_SC_tile_stalls                    = 0xc,
++	DB_PERF_SEL_DB_SC_tile_df_stalls                 = 0xd,
++	DB_PERF_SEL_DB_SC_tile_tiles                     = 0xe,
++	DB_PERF_SEL_DB_SC_tile_culled                    = 0xf,
++	DB_PERF_SEL_DB_SC_tile_hier_kill                 = 0x10,
++	DB_PERF_SEL_DB_SC_tile_fast_ops                  = 0x11,
++	DB_PERF_SEL_DB_SC_tile_no_ops                    = 0x12,
++	DB_PERF_SEL_DB_SC_tile_tile_rate                 = 0x13,
++	DB_PERF_SEL_DB_SC_tile_ssaa_kill                 = 0x14,
++	DB_PERF_SEL_DB_SC_tile_fast_z_ops                = 0x15,
++	DB_PERF_SEL_DB_SC_tile_fast_stencil_ops          = 0x16,
++	DB_PERF_SEL_SC_DB_quad_sends                     = 0x17,
++	DB_PERF_SEL_SC_DB_quad_busy                      = 0x18,
++	DB_PERF_SEL_SC_DB_quad_squads                    = 0x19,
++	DB_PERF_SEL_SC_DB_quad_tiles                     = 0x1a,
++	DB_PERF_SEL_SC_DB_quad_pixels                    = 0x1b,
++	DB_PERF_SEL_SC_DB_quad_killed_tiles              = 0x1c,
++	DB_PERF_SEL_DB_SC_quad_sends                     = 0x1d,
++	DB_PERF_SEL_DB_SC_quad_busy                      = 0x1e,
++	DB_PERF_SEL_DB_SC_quad_stalls                    = 0x1f,
++	DB_PERF_SEL_DB_SC_quad_tiles                     = 0x20,
++	DB_PERF_SEL_DB_SC_quad_lit_quad                  = 0x21,
++	DB_PERF_SEL_DB_CB_tile_sends                     = 0x22,
++	DB_PERF_SEL_DB_CB_tile_busy                      = 0x23,
++	DB_PERF_SEL_DB_CB_tile_stalls                    = 0x24,
++	DB_PERF_SEL_SX_DB_quad_sends                     = 0x25,
++	DB_PERF_SEL_SX_DB_quad_busy                      = 0x26,
++	DB_PERF_SEL_SX_DB_quad_stalls                    = 0x27,
++	DB_PERF_SEL_SX_DB_quad_quads                     = 0x28,
++	DB_PERF_SEL_SX_DB_quad_pixels                    = 0x29,
++	DB_PERF_SEL_SX_DB_quad_exports                   = 0x2a,
++	DB_PERF_SEL_SH_quads_outstanding_sum             = 0x2b,
++	DB_PERF_SEL_DB_CB_lquad_sends                    = 0x2c,
++	DB_PERF_SEL_DB_CB_lquad_busy                     = 0x2d,
++	DB_PERF_SEL_DB_CB_lquad_stalls                   = 0x2e,
++	DB_PERF_SEL_DB_CB_lquad_quads                    = 0x2f,
++	DB_PERF_SEL_tile_rd_sends                        = 0x30,
++	DB_PERF_SEL_mi_tile_rd_outstanding_sum           = 0x31,
++	DB_PERF_SEL_quad_rd_sends                        = 0x32,
++	DB_PERF_SEL_quad_rd_busy                         = 0x33,
++	DB_PERF_SEL_quad_rd_mi_stall                     = 0x34,
++	DB_PERF_SEL_quad_rd_rw_collision                 = 0x35,
++	DB_PERF_SEL_quad_rd_tag_stall                    = 0x36,
++	DB_PERF_SEL_quad_rd_32byte_reqs                  = 0x37,
++	DB_PERF_SEL_quad_rd_panic                        = 0x38,
++	DB_PERF_SEL_mi_quad_rd_outstanding_sum           = 0x39,
++	DB_PERF_SEL_quad_rdret_sends                     = 0x3a,
++	DB_PERF_SEL_quad_rdret_busy                      = 0x3b,
++	DB_PERF_SEL_tile_wr_sends                        = 0x3c,
++	DB_PERF_SEL_tile_wr_acks                         = 0x3d,
++	DB_PERF_SEL_mi_tile_wr_outstanding_sum           = 0x3e,
++	DB_PERF_SEL_quad_wr_sends                        = 0x3f,
++	DB_PERF_SEL_quad_wr_busy                         = 0x40,
++	DB_PERF_SEL_quad_wr_mi_stall                     = 0x41,
++	DB_PERF_SEL_quad_wr_coherency_stall              = 0x42,
++	DB_PERF_SEL_quad_wr_acks                         = 0x43,
++	DB_PERF_SEL_mi_quad_wr_outstanding_sum           = 0x44,
++	DB_PERF_SEL_Tile_Cache_misses                    = 0x45,
++	DB_PERF_SEL_Tile_Cache_hits                      = 0x46,
++	DB_PERF_SEL_Tile_Cache_flushes                   = 0x47,
++	DB_PERF_SEL_Tile_Cache_surface_stall             = 0x48,
++	DB_PERF_SEL_Tile_Cache_starves                   = 0x49,
++	DB_PERF_SEL_Tile_Cache_mem_return_starve         = 0x4a,
++	DB_PERF_SEL_tcp_dispatcher_reads                 = 0x4b,
++	DB_PERF_SEL_tcp_prefetcher_reads                 = 0x4c,
++	DB_PERF_SEL_tcp_preloader_reads                  = 0x4d,
++	DB_PERF_SEL_tcp_dispatcher_flushes               = 0x4e,
++	DB_PERF_SEL_tcp_prefetcher_flushes               = 0x4f,
++	DB_PERF_SEL_tcp_preloader_flushes                = 0x50,
++	DB_PERF_SEL_Depth_Tile_Cache_sends               = 0x51,
++	DB_PERF_SEL_Depth_Tile_Cache_busy                = 0x52,
++	DB_PERF_SEL_Depth_Tile_Cache_starves             = 0x53,
++	DB_PERF_SEL_Depth_Tile_Cache_dtile_locked        = 0x54,
++	DB_PERF_SEL_Depth_Tile_Cache_alloc_stall         = 0x55,
++	DB_PERF_SEL_Depth_Tile_Cache_misses              = 0x56,
++	DB_PERF_SEL_Depth_Tile_Cache_hits                = 0x57,
++	DB_PERF_SEL_Depth_Tile_Cache_flushes             = 0x58,
++	DB_PERF_SEL_Depth_Tile_Cache_noop_tile           = 0x59,
++	DB_PERF_SEL_Depth_Tile_Cache_detailed_noop       = 0x5a,
++	DB_PERF_SEL_Depth_Tile_Cache_event               = 0x5b,
++	DB_PERF_SEL_Depth_Tile_Cache_tile_frees          = 0x5c,
++	DB_PERF_SEL_Depth_Tile_Cache_data_frees          = 0x5d,
++	DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve   = 0x5e,
++	DB_PERF_SEL_Stencil_Cache_misses                 = 0x5f,
++	DB_PERF_SEL_Stencil_Cache_hits                   = 0x60,
++	DB_PERF_SEL_Stencil_Cache_flushes                = 0x61,
++	DB_PERF_SEL_Stencil_Cache_starves                = 0x62,
++	DB_PERF_SEL_Stencil_Cache_frees                  = 0x63,
++	DB_PERF_SEL_Z_Cache_separate_Z_misses            = 0x64,
++	DB_PERF_SEL_Z_Cache_separate_Z_hits              = 0x65,
++	DB_PERF_SEL_Z_Cache_separate_Z_flushes           = 0x66,
++	DB_PERF_SEL_Z_Cache_separate_Z_starves           = 0x67,
++	DB_PERF_SEL_Z_Cache_pmask_misses                 = 0x68,
++	DB_PERF_SEL_Z_Cache_pmask_hits                   = 0x69,
++	DB_PERF_SEL_Z_Cache_pmask_flushes                = 0x6a,
++	DB_PERF_SEL_Z_Cache_pmask_starves                = 0x6b,
++	DB_PERF_SEL_Z_Cache_frees                        = 0x6c,
++	DB_PERF_SEL_Plane_Cache_misses                   = 0x6d,
++	DB_PERF_SEL_Plane_Cache_hits                     = 0x6e,
++	DB_PERF_SEL_Plane_Cache_flushes                  = 0x6f,
++	DB_PERF_SEL_Plane_Cache_starves                  = 0x70,
++	DB_PERF_SEL_Plane_Cache_frees                    = 0x71,
++	DB_PERF_SEL_flush_expanded_stencil               = 0x72,
++	DB_PERF_SEL_flush_compressed_stencil             = 0x73,
++	DB_PERF_SEL_flush_single_stencil                 = 0x74,
++	DB_PERF_SEL_planes_flushed                       = 0x75,
++	DB_PERF_SEL_flush_1plane                         = 0x76,
++	DB_PERF_SEL_flush_2plane                         = 0x77,
++	DB_PERF_SEL_flush_3plane                         = 0x78,
++	DB_PERF_SEL_flush_4plane                         = 0x79,
++	DB_PERF_SEL_flush_5plane                         = 0x7a,
++	DB_PERF_SEL_flush_6plane                         = 0x7b,
++	DB_PERF_SEL_flush_7plane                         = 0x7c,
++	DB_PERF_SEL_flush_8plane                         = 0x7d,
++	DB_PERF_SEL_flush_9plane                         = 0x7e,
++	DB_PERF_SEL_flush_10plane                        = 0x7f,
++	DB_PERF_SEL_flush_11plane                        = 0x80,
++	DB_PERF_SEL_flush_12plane                        = 0x81,
++	DB_PERF_SEL_flush_13plane                        = 0x82,
++	DB_PERF_SEL_flush_14plane                        = 0x83,
++	DB_PERF_SEL_flush_15plane                        = 0x84,
++	DB_PERF_SEL_flush_16plane                        = 0x85,
++	DB_PERF_SEL_flush_expanded_z                     = 0x86,
++	DB_PERF_SEL_earlyZ_waiting_for_postZ_done        = 0x87,
++	DB_PERF_SEL_reZ_waiting_for_postZ_done           = 0x88,
++	DB_PERF_SEL_dk_tile_sends                        = 0x89,
++	DB_PERF_SEL_dk_tile_busy                         = 0x8a,
++	DB_PERF_SEL_dk_tile_quad_starves                 = 0x8b,
++	DB_PERF_SEL_dk_tile_stalls                       = 0x8c,
++	DB_PERF_SEL_dk_squad_sends                       = 0x8d,
++	DB_PERF_SEL_dk_squad_busy                        = 0x8e,
++	DB_PERF_SEL_dk_squad_stalls                      = 0x8f,
++	DB_PERF_SEL_Op_Pipe_Busy                         = 0x90,
++	DB_PERF_SEL_Op_Pipe_MC_Read_stall                = 0x91,
++	DB_PERF_SEL_qc_busy                              = 0x92,
++	DB_PERF_SEL_qc_xfc                               = 0x93,
++	DB_PERF_SEL_qc_conflicts                         = 0x94,
++	DB_PERF_SEL_qc_full_stall                        = 0x95,
++	DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ         = 0x96,
++	DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ         = 0x97,
++	DB_PERF_SEL_tsc_insert_summarize_stall           = 0x98,
++	DB_PERF_SEL_tl_busy                              = 0x99,
++	DB_PERF_SEL_tl_dtc_read_starved                  = 0x9a,
++	DB_PERF_SEL_tl_z_fetch_stall                     = 0x9b,
++	DB_PERF_SEL_tl_stencil_stall                     = 0x9c,
++	DB_PERF_SEL_tl_z_decompress_stall                = 0x9d,
++	DB_PERF_SEL_tl_stencil_locked_stall              = 0x9e,
++	DB_PERF_SEL_tl_events                            = 0x9f,
++	DB_PERF_SEL_tl_summarize_squads                  = 0xa0,
++	DB_PERF_SEL_tl_flush_expand_squads               = 0xa1,
++	DB_PERF_SEL_tl_expand_squads                     = 0xa2,
++	DB_PERF_SEL_tl_preZ_squads                       = 0xa3,
++	DB_PERF_SEL_tl_postZ_squads                      = 0xa4,
++	DB_PERF_SEL_tl_preZ_noop_squads                  = 0xa5,
++	DB_PERF_SEL_tl_postZ_noop_squads                 = 0xa6,
++	DB_PERF_SEL_tl_tile_ops                          = 0xa7,
++	DB_PERF_SEL_tl_in_xfc                            = 0xa8,
++	DB_PERF_SEL_tl_in_single_stencil_expand_stall    = 0xa9,
++	DB_PERF_SEL_tl_in_fast_z_stall                   = 0xaa,
++	DB_PERF_SEL_tl_out_xfc                           = 0xab,
++	DB_PERF_SEL_tl_out_squads                        = 0xac,
++	DB_PERF_SEL_zf_plane_multicycle                  = 0xad,
++	DB_PERF_SEL_PostZ_Samples_passing_Z              = 0xae,
++	DB_PERF_SEL_PostZ_Samples_failing_Z              = 0xaf,
++	DB_PERF_SEL_PostZ_Samples_failing_S              = 0xb0,
++	DB_PERF_SEL_PreZ_Samples_passing_Z               = 0xb1,
++	DB_PERF_SEL_PreZ_Samples_failing_Z               = 0xb2,
++	DB_PERF_SEL_PreZ_Samples_failing_S               = 0xb3,
++	DB_PERF_SEL_ts_tc_update_stall                   = 0xb4,
++	DB_PERF_SEL_sc_kick_start                        = 0xb5,
++	DB_PERF_SEL_sc_kick_end                          = 0xb6,
++	DB_PERF_SEL_clock_reg_active                     = 0xb7,
++	DB_PERF_SEL_clock_main_active                    = 0xb8,
++	DB_PERF_SEL_clock_mem_export_active              = 0xb9,
++	DB_PERF_SEL_esr_ps_out_busy                      = 0xba,
++	DB_PERF_SEL_esr_ps_lqf_busy                      = 0xbb,
++	DB_PERF_SEL_esr_ps_lqf_stall                     = 0xbc,
++	DB_PERF_SEL_etr_out_send                         = 0xbd,
++	DB_PERF_SEL_etr_out_busy                         = 0xbe,
++	DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0xbf,
++	DB_PERF_SEL_etr_out_cb_tile_stall                = 0xc0,
++	DB_PERF_SEL_etr_out_esr_stall                    = 0xc1,
++	DB_PERF_SEL_esr_ps_sqq_busy                      = 0xc2,
++	DB_PERF_SEL_esr_ps_sqq_stall                     = 0xc3,
++	DB_PERF_SEL_esr_eot_fwd_busy                     = 0xc4,
++	DB_PERF_SEL_esr_eot_fwd_holding_squad            = 0xc5,
++	DB_PERF_SEL_esr_eot_fwd_forward                  = 0xc6,
++	DB_PERF_SEL_esr_sqq_zi_busy                      = 0xc7,
++	DB_PERF_SEL_esr_sqq_zi_stall                     = 0xc8,
++	DB_PERF_SEL_postzl_sq_pt_busy                    = 0xc9,
++	DB_PERF_SEL_postzl_sq_pt_stall                   = 0xca,
++	DB_PERF_SEL_postzl_se_busy                       = 0xcb,
++	DB_PERF_SEL_postzl_se_stall                      = 0xcc,
++	DB_PERF_SEL_postzl_partial_launch                = 0xcd,
++	DB_PERF_SEL_postzl_full_launch                   = 0xce,
++	DB_PERF_SEL_postzl_partial_waiting               = 0xcf,
++	DB_PERF_SEL_postzl_tile_mem_stall                = 0xd0,
++	DB_PERF_SEL_postzl_tile_init_stall               = 0xd1,
++	DB_PEFF_SEL_prezl_tile_mem_stall                 = 0xd2,
++	DB_PERF_SEL_prezl_tile_init_stall                = 0xd3,
++	DB_PERF_SEL_dtt_sm_clash_stall                   = 0xd4,
++	DB_PERF_SEL_dtt_sm_slot_stall                    = 0xd5,
++	DB_PERF_SEL_dtt_sm_miss_stall                    = 0xd6,
++	DB_PERF_SEL_mi_rdreq_busy                        = 0xd7,
++	DB_PERF_SEL_mi_rdreq_stall                       = 0xd8,
++	DB_PERF_SEL_mi_wrreq_busy                        = 0xd9,
++	DB_PERF_SEL_mi_wrreq_stall                       = 0xda,
++	DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop     = 0xdb,
++	DB_PERF_SEL_dkg_tile_rate_tile                   = 0xdc,
++	DB_PERF_SEL_prezl_src_in_sends                   = 0xdd,
++	DB_PERF_SEL_prezl_src_in_stall                   = 0xde,
++	DB_PERF_SEL_prezl_src_in_squads                  = 0xdf,
++	DB_PERF_SEL_prezl_src_in_squads_unrolled         = 0xe0,
++	DB_PERF_SEL_prezl_src_in_tile_rate               = 0xe1,
++	DB_PERF_SEL_prezl_src_in_tile_rate_unrolled      = 0xe2,
++	DB_PERF_SEL_prezl_src_out_stall                  = 0xe3,
++	DB_PERF_SEL_postzl_src_in_sends                  = 0xe4,
++	DB_PERF_SEL_postzl_src_in_stall                  = 0xe5,
++	DB_PERF_SEL_postzl_src_in_squads                 = 0xe6,
++	DB_PERF_SEL_postzl_src_in_squads_unrolled        = 0xe7,
++	DB_PERF_SEL_postzl_src_in_tile_rate              = 0xe8,
++	DB_PERF_SEL_postzl_src_in_tile_rate_unrolled     = 0xe9,
++	DB_PERF_SEL_postzl_src_out_stall                 = 0xea,
++	DB_PERF_SEL_esr_ps_src_in_sends                  = 0xeb,
++	DB_PERF_SEL_esr_ps_src_in_stall                  = 0xec,
++	DB_PERF_SEL_esr_ps_src_in_squads                 = 0xed,
++	DB_PERF_SEL_esr_ps_src_in_squads_unrolled        = 0xee,
++	DB_PERF_SEL_esr_ps_src_in_tile_rate              = 0xef,
++	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled     = 0xf0,
++	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
++	DB_PERF_SEL_esr_ps_src_out_stall                 = 0xf2,
++	DB_PERF_SEL_depth_bounds_qtiles_culled           = 0xf3,
++	DB_PERF_SEL_PreZ_Samples_failing_DB              = 0xf4,
++	DB_PERF_SEL_PostZ_Samples_failing_DB             = 0xf5,
++	DB_PERF_SEL_flush_compressed                     = 0xf6,
++	DB_PERF_SEL_flush_plane_le4                      = 0xf7,
++	DB_PERF_SEL_tiles_z_fully_summarized             = 0xf8,
++	DB_PERF_SEL_tiles_stencil_fully_summarized       = 0xf9,
++	DB_PERF_SEL_tiles_z_clear_on_expclear            = 0xfa,
++	DB_PERF_SEL_tiles_s_clear_on_expclear            = 0xfb,
++	DB_PERF_SEL_tiles_decomp_on_expclear             = 0xfc,
++	DB_PERF_SEL_tiles_compressed_to_decompressed     = 0xfd,
++	DB_PERF_SEL_Op_Pipe_Prez_Busy                    = 0xfe,
++	DB_PERF_SEL_Op_Pipe_Postz_Busy                   = 0xff,
++	DB_PERF_SEL_di_dt_stall                          = 0x100,
++} PerfCounter_Vals;
++typedef enum RingCounterControl {
++	COUNTER_RING_SPLIT                               = 0x0,
++	COUNTER_RING_0                                   = 0x1,
++	COUNTER_RING_1                                   = 0x2,
++} RingCounterControl;
++typedef enum PixelPipeCounterId {
++	PIXEL_PIPE_OCCLUSION_COUNT_0                     = 0x0,
++	PIXEL_PIPE_OCCLUSION_COUNT_1                     = 0x1,
++	PIXEL_PIPE_OCCLUSION_COUNT_2                     = 0x2,
++	PIXEL_PIPE_OCCLUSION_COUNT_3                     = 0x3,
++	PIXEL_PIPE_SCREEN_MIN_EXTENTS_0                  = 0x4,
++	PIXEL_PIPE_SCREEN_MAX_EXTENTS_0                  = 0x5,
++	PIXEL_PIPE_SCREEN_MIN_EXTENTS_1                  = 0x6,
++	PIXEL_PIPE_SCREEN_MAX_EXTENTS_1                  = 0x7,
++} PixelPipeCounterId;
++typedef enum PixelPipeStride {
++	PIXEL_PIPE_STRIDE_32_BITS                        = 0x0,
++	PIXEL_PIPE_STRIDE_64_BITS                        = 0x1,
++	PIXEL_PIPE_STRIDE_128_BITS                       = 0x2,
++	PIXEL_PIPE_STRIDE_256_BITS                       = 0x3,
++} PixelPipeStride;
++typedef enum GB_EDC_DED_MODE {
++	GB_EDC_DED_MODE_LOG                              = 0x0,
++	GB_EDC_DED_MODE_HALT                             = 0x1,
++	GB_EDC_DED_MODE_INT_HALT                         = 0x2,
++} GB_EDC_DED_MODE;
++#define GB_TILING_CONFIG_TABLE_SIZE               0x20
++#define GB_TILING_CONFIG_MACROTABLE_SIZE          0x10
++typedef enum GRBM_PERF_SEL {
++	GRBM_PERF_SEL_COUNT                              = 0x0,
++	GRBM_PERF_SEL_USER_DEFINED                       = 0x1,
++	GRBM_PERF_SEL_GUI_ACTIVE                         = 0x2,
++	GRBM_PERF_SEL_CP_BUSY                            = 0x3,
++	GRBM_PERF_SEL_CP_COHER_BUSY                      = 0x4,
++	GRBM_PERF_SEL_CP_DMA_BUSY                        = 0x5,
++	GRBM_PERF_SEL_CB_BUSY                            = 0x6,
++	GRBM_PERF_SEL_DB_BUSY                            = 0x7,
++	GRBM_PERF_SEL_PA_BUSY                            = 0x8,
++	GRBM_PERF_SEL_SC_BUSY                            = 0x9,
++	GRBM_PERF_SEL_RESERVED_6                         = 0xa,
++	GRBM_PERF_SEL_SPI_BUSY                           = 0xb,
++	GRBM_PERF_SEL_SX_BUSY                            = 0xc,
++	GRBM_PERF_SEL_TA_BUSY                            = 0xd,
++	GRBM_PERF_SEL_CB_CLEAN                           = 0xe,
++	GRBM_PERF_SEL_DB_CLEAN                           = 0xf,
++	GRBM_PERF_SEL_RESERVED_5                         = 0x10,
++	GRBM_PERF_SEL_VGT_BUSY                           = 0x11,
++	GRBM_PERF_SEL_RESERVED_4                         = 0x12,
++	GRBM_PERF_SEL_RESERVED_3                         = 0x13,
++	GRBM_PERF_SEL_RESERVED_2                         = 0x14,
++	GRBM_PERF_SEL_RESERVED_1                         = 0x15,
++	GRBM_PERF_SEL_RESERVED_0                         = 0x16,
++	GRBM_PERF_SEL_IA_BUSY                            = 0x17,
++	GRBM_PERF_SEL_IA_NO_DMA_BUSY                     = 0x18,
++	GRBM_PERF_SEL_GDS_BUSY                           = 0x19,
++	GRBM_PERF_SEL_BCI_BUSY                           = 0x1a,
++	GRBM_PERF_SEL_RLC_BUSY                           = 0x1b,
++	GRBM_PERF_SEL_TC_BUSY                            = 0x1c,
++	GRBM_PERF_SEL_CPG_BUSY                           = 0x1d,
++	GRBM_PERF_SEL_CPC_BUSY                           = 0x1e,
++	GRBM_PERF_SEL_CPF_BUSY                           = 0x1f,
++	GRBM_PERF_SEL_WD_BUSY                            = 0x20,
++	GRBM_PERF_SEL_WD_NO_DMA_BUSY                     = 0x21,
++} GRBM_PERF_SEL;
++typedef enum GRBM_SE0_PERF_SEL {
++	GRBM_SE0_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE0_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE0_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE0_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE0_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE0_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE0_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE0_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE0_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE0_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE0_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE0_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE0_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE0_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE0_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE0_PERF_SEL;
++typedef enum GRBM_SE1_PERF_SEL {
++	GRBM_SE1_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE1_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE1_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE1_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE1_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE1_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE1_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE1_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE1_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE1_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE1_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE1_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE1_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE1_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE1_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE1_PERF_SEL;
++typedef enum GRBM_SE2_PERF_SEL {
++	GRBM_SE2_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE2_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE2_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE2_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE2_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE2_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE2_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE2_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE2_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE2_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE2_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE2_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE2_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE2_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE2_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE2_PERF_SEL;
++typedef enum GRBM_SE3_PERF_SEL {
++	GRBM_SE3_PERF_SEL_COUNT                          = 0x0,
++	GRBM_SE3_PERF_SEL_USER_DEFINED                   = 0x1,
++	GRBM_SE3_PERF_SEL_CB_BUSY                        = 0x2,
++	GRBM_SE3_PERF_SEL_DB_BUSY                        = 0x3,
++	GRBM_SE3_PERF_SEL_SC_BUSY                        = 0x4,
++	GRBM_SE3_PERF_SEL_RESERVED_1                     = 0x5,
++	GRBM_SE3_PERF_SEL_SPI_BUSY                       = 0x6,
++	GRBM_SE3_PERF_SEL_SX_BUSY                        = 0x7,
++	GRBM_SE3_PERF_SEL_TA_BUSY                        = 0x8,
++	GRBM_SE3_PERF_SEL_CB_CLEAN                       = 0x9,
++	GRBM_SE3_PERF_SEL_DB_CLEAN                       = 0xa,
++	GRBM_SE3_PERF_SEL_RESERVED_0                     = 0xb,
++	GRBM_SE3_PERF_SEL_PA_BUSY                        = 0xc,
++	GRBM_SE3_PERF_SEL_VGT_BUSY                       = 0xd,
++	GRBM_SE3_PERF_SEL_BCI_BUSY                       = 0xe,
++} GRBM_SE3_PERF_SEL;
++typedef enum SU_PERFCNT_SEL {
++	PERF_PAPC_PASX_REQ                               = 0x0,
++	PERF_PAPC_PASX_DISABLE_PIPE                      = 0x1,
++	PERF_PAPC_PASX_FIRST_VECTOR                      = 0x2,
++	PERF_PAPC_PASX_SECOND_VECTOR                     = 0x3,
++	PERF_PAPC_PASX_FIRST_DEAD                        = 0x4,
++	PERF_PAPC_PASX_SECOND_DEAD                       = 0x5,
++	PERF_PAPC_PASX_VTX_KILL_DISCARD                  = 0x6,
++	PERF_PAPC_PASX_VTX_NAN_DISCARD                   = 0x7,
++	PERF_PAPC_PA_INPUT_PRIM                          = 0x8,
++	PERF_PAPC_PA_INPUT_NULL_PRIM                     = 0x9,
++	PERF_PAPC_PA_INPUT_EVENT_FLAG                    = 0xa,
++	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT               = 0xb,
++	PERF_PAPC_PA_INPUT_END_OF_PACKET                 = 0xc,
++	PERF_PAPC_PA_INPUT_EXTENDED_EVENT                = 0xd,
++	PERF_PAPC_CLPR_CULL_PRIM                         = 0xe,
++	PERF_PAPC_CLPR_VVUCP_CULL_PRIM                   = 0xf,
++	PERF_PAPC_CLPR_VV_CULL_PRIM                      = 0x10,
++	PERF_PAPC_CLPR_UCP_CULL_PRIM                     = 0x11,
++	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM                = 0x12,
++	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM                 = 0x13,
++	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM                 = 0x14,
++	PERF_PAPC_CLPR_VVUCP_CLIP_PRIM                   = 0x15,
++	PERF_PAPC_CLPR_VV_CLIP_PRIM                      = 0x16,
++	PERF_PAPC_CLPR_UCP_CLIP_PRIM                     = 0x17,
++	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE              = 0x18,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1                  = 0x19,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2                  = 0x1a,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3                  = 0x1b,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4                  = 0x1c,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8                = 0x1d,
++	PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12               = 0x1e,
++	PERF_PAPC_CLPR_CLIP_PLANE_NEAR                   = 0x1f,
++	PERF_PAPC_CLPR_CLIP_PLANE_FAR                    = 0x20,
++	PERF_PAPC_CLPR_CLIP_PLANE_LEFT                   = 0x21,
++	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT                  = 0x22,
++	PERF_PAPC_CLPR_CLIP_PLANE_TOP                    = 0x23,
++	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM                 = 0x24,
++	PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM                = 0x25,
++	PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM             = 0x26,
++	PERF_PAPC_CLSM_NULL_PRIM                         = 0x27,
++	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM              = 0x28,
++	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM                 = 0x29,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_1                    = 0x2a,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_2                    = 0x2b,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_3                    = 0x2c,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_4                    = 0x2d,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8                  = 0x2e,
++	PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13                 = 0x2f,
++	PERF_PAPC_CLIPGA_VTE_KILL_PRIM                   = 0x30,
++	PERF_PAPC_SU_INPUT_PRIM                          = 0x31,
++	PERF_PAPC_SU_INPUT_CLIP_PRIM                     = 0x32,
++	PERF_PAPC_SU_INPUT_NULL_PRIM                     = 0x33,
++	PERF_PAPC_SU_INPUT_PRIM_DUAL                     = 0x34,
++	PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL                = 0x35,
++	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM                 = 0x36,
++	PERF_PAPC_SU_BACK_FACE_CULL_PRIM                 = 0x37,
++	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM                = 0x38,
++	PERF_PAPC_SU_POLYMODE_FACE_CULL                  = 0x39,
++	PERF_PAPC_SU_POLYMODE_BACK_CULL                  = 0x3a,
++	PERF_PAPC_SU_POLYMODE_FRONT_CULL                 = 0x3b,
++	PERF_PAPC_SU_POLYMODE_INVALID_FILL               = 0x3c,
++	PERF_PAPC_SU_OUTPUT_PRIM                         = 0x3d,
++	PERF_PAPC_SU_OUTPUT_CLIP_PRIM                    = 0x3e,
++	PERF_PAPC_SU_OUTPUT_NULL_PRIM                    = 0x3f,
++	PERF_PAPC_SU_OUTPUT_EVENT_FLAG                   = 0x40,
++	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT              = 0x41,
++	PERF_PAPC_SU_OUTPUT_END_OF_PACKET                = 0x42,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE                = 0x43,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK                = 0x44,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT               = 0x45,
++	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE              = 0x46,
++	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK              = 0x47,
++	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT             = 0x48,
++	PERF_PAPC_SU_OUTPUT_PRIM_DUAL                    = 0x49,
++	PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL               = 0x4a,
++	PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL                = 0x4b,
++	PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL           = 0x4c,
++	PERF_PAPC_PASX_REQ_IDLE                          = 0x4d,
++	PERF_PAPC_PASX_REQ_BUSY                          = 0x4e,
++	PERF_PAPC_PASX_REQ_STALLED                       = 0x4f,
++	PERF_PAPC_PASX_REC_IDLE                          = 0x50,
++	PERF_PAPC_PASX_REC_BUSY                          = 0x51,
++	PERF_PAPC_PASX_REC_STARVED_SX                    = 0x52,
++	PERF_PAPC_PASX_REC_STALLED                       = 0x53,
++	PERF_PAPC_PASX_REC_STALLED_POS_MEM               = 0x54,
++	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN              = 0x55,
++	PERF_PAPC_CCGSM_IDLE                             = 0x56,
++	PERF_PAPC_CCGSM_BUSY                             = 0x57,
++	PERF_PAPC_CCGSM_STALLED                          = 0x58,
++	PERF_PAPC_CLPRIM_IDLE                            = 0x59,
++	PERF_PAPC_CLPRIM_BUSY                            = 0x5a,
++	PERF_PAPC_CLPRIM_STALLED                         = 0x5b,
++	PERF_PAPC_CLPRIM_STARVED_CCGSM                   = 0x5c,
++	PERF_PAPC_CLIPSM_IDLE                            = 0x5d,
++	PERF_PAPC_CLIPSM_BUSY                            = 0x5e,
++	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH             = 0x5f,
++	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ               = 0x60,
++	PERF_PAPC_CLIPSM_WAIT_CLIPGA                     = 0x61,
++	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP             = 0x62,
++	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM                 = 0x63,
++	PERF_PAPC_CLIPGA_IDLE                            = 0x64,
++	PERF_PAPC_CLIPGA_BUSY                            = 0x65,
++	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP                = 0x66,
++	PERF_PAPC_CLIPGA_STALLED                         = 0x67,
++	PERF_PAPC_CLIP_IDLE                              = 0x68,
++	PERF_PAPC_CLIP_BUSY                              = 0x69,
++	PERF_PAPC_SU_IDLE                                = 0x6a,
++	PERF_PAPC_SU_BUSY                                = 0x6b,
++	PERF_PAPC_SU_STARVED_CLIP                        = 0x6c,
++	PERF_PAPC_SU_STALLED_SC                          = 0x6d,
++	PERF_PAPC_CL_DYN_SCLK_VLD                        = 0x6e,
++	PERF_PAPC_SU_DYN_SCLK_VLD                        = 0x6f,
++	PERF_PAPC_PA_REG_SCLK_VLD                        = 0x70,
++	PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL          = 0x71,
++	PERF_PAPC_PASX_SE0_REQ                           = 0x72,
++	PERF_PAPC_PASX_SE1_REQ                           = 0x73,
++	PERF_PAPC_PASX_SE0_FIRST_VECTOR                  = 0x74,
++	PERF_PAPC_PASX_SE0_SECOND_VECTOR                 = 0x75,
++	PERF_PAPC_PASX_SE1_FIRST_VECTOR                  = 0x76,
++	PERF_PAPC_PASX_SE1_SECOND_VECTOR                 = 0x77,
++	PERF_PAPC_SU_SE0_PRIM_FILTER_CULL                = 0x78,
++	PERF_PAPC_SU_SE1_PRIM_FILTER_CULL                = 0x79,
++	PERF_PAPC_SU_SE01_PRIM_FILTER_CULL               = 0x7a,
++	PERF_PAPC_SU_SE0_OUTPUT_PRIM                     = 0x7b,
++	PERF_PAPC_SU_SE1_OUTPUT_PRIM                     = 0x7c,
++	PERF_PAPC_SU_SE01_OUTPUT_PRIM                    = 0x7d,
++	PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM                = 0x7e,
++	PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM                = 0x7f,
++	PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM               = 0x80,
++	PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT          = 0x81,
++	PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT          = 0x82,
++	PERF_PAPC_SU_SE0_STALLED_SC                      = 0x83,
++	PERF_PAPC_SU_SE1_STALLED_SC                      = 0x84,
++	PERF_PAPC_SU_SE01_STALLED_SC                     = 0x85,
++	PERF_PAPC_CLSM_CLIPPING_PRIM                     = 0x86,
++	PERF_PAPC_SU_CULLED_PRIM                         = 0x87,
++	PERF_PAPC_SU_OUTPUT_EOPG                         = 0x88,
++	PERF_PAPC_SU_SE2_PRIM_FILTER_CULL                = 0x89,
++	PERF_PAPC_SU_SE3_PRIM_FILTER_CULL                = 0x8a,
++	PERF_PAPC_SU_SE2_OUTPUT_PRIM                     = 0x8b,
++	PERF_PAPC_SU_SE3_OUTPUT_PRIM                     = 0x8c,
++	PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM                = 0x8d,
++	PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM                = 0x8e,
++	PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET            = 0x8f,
++	PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET            = 0x90,
++	PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET            = 0x91,
++	PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET            = 0x92,
++	PERF_PAPC_SU_SE0_OUTPUT_EOPG                     = 0x93,
++	PERF_PAPC_SU_SE1_OUTPUT_EOPG                     = 0x94,
++	PERF_PAPC_SU_SE2_OUTPUT_EOPG                     = 0x95,
++	PERF_PAPC_SU_SE3_OUTPUT_EOPG                     = 0x96,
++	PERF_PAPC_SU_SE2_STALLED_SC                      = 0x97,
++	PERF_PAPC_SU_SE3_STALLED_SC                      = 0x98,
++} SU_PERFCNT_SEL;
++typedef enum SC_PERFCNT_SEL {
++	SC_SRPS_WINDOW_VALID                             = 0x0,
++	SC_PSSW_WINDOW_VALID                             = 0x1,
++	SC_TPQZ_WINDOW_VALID                             = 0x2,
++	SC_QZQP_WINDOW_VALID                             = 0x3,
++	SC_TRPK_WINDOW_VALID                             = 0x4,
++	SC_SRPS_WINDOW_VALID_BUSY                        = 0x5,
++	SC_PSSW_WINDOW_VALID_BUSY                        = 0x6,
++	SC_TPQZ_WINDOW_VALID_BUSY                        = 0x7,
++	SC_QZQP_WINDOW_VALID_BUSY                        = 0x8,
++	SC_TRPK_WINDOW_VALID_BUSY                        = 0x9,
++	SC_STARVED_BY_PA                                 = 0xa,
++	SC_STALLED_BY_PRIMFIFO                           = 0xb,
++	SC_STALLED_BY_DB_TILE                            = 0xc,
++	SC_STARVED_BY_DB_TILE                            = 0xd,
++	SC_STALLED_BY_TILEORDERFIFO                      = 0xe,
++	SC_STALLED_BY_TILEFIFO                           = 0xf,
++	SC_STALLED_BY_DB_QUAD                            = 0x10,
++	SC_STARVED_BY_DB_QUAD                            = 0x11,
++	SC_STALLED_BY_QUADFIFO                           = 0x12,
++	SC_STALLED_BY_BCI                                = 0x13,
++	SC_STALLED_BY_SPI                                = 0x14,
++	SC_SCISSOR_DISCARD                               = 0x15,
++	SC_BB_DISCARD                                    = 0x16,
++	SC_SUPERTILE_COUNT                               = 0x17,
++	SC_SUPERTILE_PER_PRIM_H0                         = 0x18,
++	SC_SUPERTILE_PER_PRIM_H1                         = 0x19,
++	SC_SUPERTILE_PER_PRIM_H2                         = 0x1a,
++	SC_SUPERTILE_PER_PRIM_H3                         = 0x1b,
++	SC_SUPERTILE_PER_PRIM_H4                         = 0x1c,
++	SC_SUPERTILE_PER_PRIM_H5                         = 0x1d,
++	SC_SUPERTILE_PER_PRIM_H6                         = 0x1e,
++	SC_SUPERTILE_PER_PRIM_H7                         = 0x1f,
++	SC_SUPERTILE_PER_PRIM_H8                         = 0x20,
++	SC_SUPERTILE_PER_PRIM_H9                         = 0x21,
++	SC_SUPERTILE_PER_PRIM_H10                        = 0x22,
++	SC_SUPERTILE_PER_PRIM_H11                        = 0x23,
++	SC_SUPERTILE_PER_PRIM_H12                        = 0x24,
++	SC_SUPERTILE_PER_PRIM_H13                        = 0x25,
++	SC_SUPERTILE_PER_PRIM_H14                        = 0x26,
++	SC_SUPERTILE_PER_PRIM_H15                        = 0x27,
++	SC_SUPERTILE_PER_PRIM_H16                        = 0x28,
++	SC_TILE_PER_PRIM_H0                              = 0x29,
++	SC_TILE_PER_PRIM_H1                              = 0x2a,
++	SC_TILE_PER_PRIM_H2                              = 0x2b,
++	SC_TILE_PER_PRIM_H3                              = 0x2c,
++	SC_TILE_PER_PRIM_H4                              = 0x2d,
++	SC_TILE_PER_PRIM_H5                              = 0x2e,
++	SC_TILE_PER_PRIM_H6                              = 0x2f,
++	SC_TILE_PER_PRIM_H7                              = 0x30,
++	SC_TILE_PER_PRIM_H8                              = 0x31,
++	SC_TILE_PER_PRIM_H9                              = 0x32,
++	SC_TILE_PER_PRIM_H10                             = 0x33,
++	SC_TILE_PER_PRIM_H11                             = 0x34,
++	SC_TILE_PER_PRIM_H12                             = 0x35,
++	SC_TILE_PER_PRIM_H13                             = 0x36,
++	SC_TILE_PER_PRIM_H14                             = 0x37,
++	SC_TILE_PER_PRIM_H15                             = 0x38,
++	SC_TILE_PER_PRIM_H16                             = 0x39,
++	SC_TILE_PER_SUPERTILE_H0                         = 0x3a,
++	SC_TILE_PER_SUPERTILE_H1                         = 0x3b,
++	SC_TILE_PER_SUPERTILE_H2                         = 0x3c,
++	SC_TILE_PER_SUPERTILE_H3                         = 0x3d,
++	SC_TILE_PER_SUPERTILE_H4                         = 0x3e,
++	SC_TILE_PER_SUPERTILE_H5                         = 0x3f,
++	SC_TILE_PER_SUPERTILE_H6                         = 0x40,
++	SC_TILE_PER_SUPERTILE_H7                         = 0x41,
++	SC_TILE_PER_SUPERTILE_H8                         = 0x42,
++	SC_TILE_PER_SUPERTILE_H9                         = 0x43,
++	SC_TILE_PER_SUPERTILE_H10                        = 0x44,
++	SC_TILE_PER_SUPERTILE_H11                        = 0x45,
++	SC_TILE_PER_SUPERTILE_H12                        = 0x46,
++	SC_TILE_PER_SUPERTILE_H13                        = 0x47,
++	SC_TILE_PER_SUPERTILE_H14                        = 0x48,
++	SC_TILE_PER_SUPERTILE_H15                        = 0x49,
++	SC_TILE_PER_SUPERTILE_H16                        = 0x4a,
++	SC_TILE_PICKED_H1                                = 0x4b,
++	SC_TILE_PICKED_H2                                = 0x4c,
++	SC_TILE_PICKED_H3                                = 0x4d,
++	SC_TILE_PICKED_H4                                = 0x4e,
++	SC_QZ0_MULTI_GPU_TILE_DISCARD                    = 0x4f,
++	SC_QZ1_MULTI_GPU_TILE_DISCARD                    = 0x50,
++	SC_QZ2_MULTI_GPU_TILE_DISCARD                    = 0x51,
++	SC_QZ3_MULTI_GPU_TILE_DISCARD                    = 0x52,
++	SC_QZ0_TILE_COUNT                                = 0x53,
++	SC_QZ1_TILE_COUNT                                = 0x54,
++	SC_QZ2_TILE_COUNT                                = 0x55,
++	SC_QZ3_TILE_COUNT                                = 0x56,
++	SC_QZ0_TILE_COVERED_COUNT                        = 0x57,
++	SC_QZ1_TILE_COVERED_COUNT                        = 0x58,
++	SC_QZ2_TILE_COVERED_COUNT                        = 0x59,
++	SC_QZ3_TILE_COVERED_COUNT                        = 0x5a,
++	SC_QZ0_TILE_NOT_COVERED_COUNT                    = 0x5b,
++	SC_QZ1_TILE_NOT_COVERED_COUNT                    = 0x5c,
++	SC_QZ2_TILE_NOT_COVERED_COUNT                    = 0x5d,
++	SC_QZ3_TILE_NOT_COVERED_COUNT                    = 0x5e,
++	SC_QZ0_QUAD_PER_TILE_H0                          = 0x5f,
++	SC_QZ0_QUAD_PER_TILE_H1                          = 0x60,
++	SC_QZ0_QUAD_PER_TILE_H2                          = 0x61,
++	SC_QZ0_QUAD_PER_TILE_H3                          = 0x62,
++	SC_QZ0_QUAD_PER_TILE_H4                          = 0x63,
++	SC_QZ0_QUAD_PER_TILE_H5                          = 0x64,
++	SC_QZ0_QUAD_PER_TILE_H6                          = 0x65,
++	SC_QZ0_QUAD_PER_TILE_H7                          = 0x66,
++	SC_QZ0_QUAD_PER_TILE_H8                          = 0x67,
++	SC_QZ0_QUAD_PER_TILE_H9                          = 0x68,
++	SC_QZ0_QUAD_PER_TILE_H10                         = 0x69,
++	SC_QZ0_QUAD_PER_TILE_H11                         = 0x6a,
++	SC_QZ0_QUAD_PER_TILE_H12                         = 0x6b,
++	SC_QZ0_QUAD_PER_TILE_H13                         = 0x6c,
++	SC_QZ0_QUAD_PER_TILE_H14                         = 0x6d,
++	SC_QZ0_QUAD_PER_TILE_H15                         = 0x6e,
++	SC_QZ0_QUAD_PER_TILE_H16                         = 0x6f,
++	SC_QZ1_QUAD_PER_TILE_H0                          = 0x70,
++	SC_QZ1_QUAD_PER_TILE_H1                          = 0x71,
++	SC_QZ1_QUAD_PER_TILE_H2                          = 0x72,
++	SC_QZ1_QUAD_PER_TILE_H3                          = 0x73,
++	SC_QZ1_QUAD_PER_TILE_H4                          = 0x74,
++	SC_QZ1_QUAD_PER_TILE_H5                          = 0x75,
++	SC_QZ1_QUAD_PER_TILE_H6                          = 0x76,
++	SC_QZ1_QUAD_PER_TILE_H7                          = 0x77,
++	SC_QZ1_QUAD_PER_TILE_H8                          = 0x78,
++	SC_QZ1_QUAD_PER_TILE_H9                          = 0x79,
++	SC_QZ1_QUAD_PER_TILE_H10                         = 0x7a,
++	SC_QZ1_QUAD_PER_TILE_H11                         = 0x7b,
++	SC_QZ1_QUAD_PER_TILE_H12                         = 0x7c,
++	SC_QZ1_QUAD_PER_TILE_H13                         = 0x7d,
++	SC_QZ1_QUAD_PER_TILE_H14                         = 0x7e,
++	SC_QZ1_QUAD_PER_TILE_H15                         = 0x7f,
++	SC_QZ1_QUAD_PER_TILE_H16                         = 0x80,
++	SC_QZ2_QUAD_PER_TILE_H0                          = 0x81,
++	SC_QZ2_QUAD_PER_TILE_H1                          = 0x82,
++	SC_QZ2_QUAD_PER_TILE_H2                          = 0x83,
++	SC_QZ2_QUAD_PER_TILE_H3                          = 0x84,
++	SC_QZ2_QUAD_PER_TILE_H4                          = 0x85,
++	SC_QZ2_QUAD_PER_TILE_H5                          = 0x86,
++	SC_QZ2_QUAD_PER_TILE_H6                          = 0x87,
++	SC_QZ2_QUAD_PER_TILE_H7                          = 0x88,
++	SC_QZ2_QUAD_PER_TILE_H8                          = 0x89,
++	SC_QZ2_QUAD_PER_TILE_H9                          = 0x8a,
++	SC_QZ2_QUAD_PER_TILE_H10                         = 0x8b,
++	SC_QZ2_QUAD_PER_TILE_H11                         = 0x8c,
++	SC_QZ2_QUAD_PER_TILE_H12                         = 0x8d,
++	SC_QZ2_QUAD_PER_TILE_H13                         = 0x8e,
++	SC_QZ2_QUAD_PER_TILE_H14                         = 0x8f,
++	SC_QZ2_QUAD_PER_TILE_H15                         = 0x90,
++	SC_QZ2_QUAD_PER_TILE_H16                         = 0x91,
++	SC_QZ3_QUAD_PER_TILE_H0                          = 0x92,
++	SC_QZ3_QUAD_PER_TILE_H1                          = 0x93,
++	SC_QZ3_QUAD_PER_TILE_H2                          = 0x94,
++	SC_QZ3_QUAD_PER_TILE_H3                          = 0x95,
++	SC_QZ3_QUAD_PER_TILE_H4                          = 0x96,
++	SC_QZ3_QUAD_PER_TILE_H5                          = 0x97,
++	SC_QZ3_QUAD_PER_TILE_H6                          = 0x98,
++	SC_QZ3_QUAD_PER_TILE_H7                          = 0x99,
++	SC_QZ3_QUAD_PER_TILE_H8                          = 0x9a,
++	SC_QZ3_QUAD_PER_TILE_H9                          = 0x9b,
++	SC_QZ3_QUAD_PER_TILE_H10                         = 0x9c,
++	SC_QZ3_QUAD_PER_TILE_H11                         = 0x9d,
++	SC_QZ3_QUAD_PER_TILE_H12                         = 0x9e,
++	SC_QZ3_QUAD_PER_TILE_H13                         = 0x9f,
++	SC_QZ3_QUAD_PER_TILE_H14                         = 0xa0,
++	SC_QZ3_QUAD_PER_TILE_H15                         = 0xa1,
++	SC_QZ3_QUAD_PER_TILE_H16                         = 0xa2,
++	SC_QZ0_QUAD_COUNT                                = 0xa3,
++	SC_QZ1_QUAD_COUNT                                = 0xa4,
++	SC_QZ2_QUAD_COUNT                                = 0xa5,
++	SC_QZ3_QUAD_COUNT                                = 0xa6,
++	SC_P0_HIZ_TILE_COUNT                             = 0xa7,
++	SC_P1_HIZ_TILE_COUNT                             = 0xa8,
++	SC_P2_HIZ_TILE_COUNT                             = 0xa9,
++	SC_P3_HIZ_TILE_COUNT                             = 0xaa,
++	SC_P0_HIZ_QUAD_PER_TILE_H0                       = 0xab,
++	SC_P0_HIZ_QUAD_PER_TILE_H1                       = 0xac,
++	SC_P0_HIZ_QUAD_PER_TILE_H2                       = 0xad,
++	SC_P0_HIZ_QUAD_PER_TILE_H3                       = 0xae,
++	SC_P0_HIZ_QUAD_PER_TILE_H4                       = 0xaf,
++	SC_P0_HIZ_QUAD_PER_TILE_H5                       = 0xb0,
++	SC_P0_HIZ_QUAD_PER_TILE_H6                       = 0xb1,
++	SC_P0_HIZ_QUAD_PER_TILE_H7                       = 0xb2,
++	SC_P0_HIZ_QUAD_PER_TILE_H8                       = 0xb3,
++	SC_P0_HIZ_QUAD_PER_TILE_H9                       = 0xb4,
++	SC_P0_HIZ_QUAD_PER_TILE_H10                      = 0xb5,
++	SC_P0_HIZ_QUAD_PER_TILE_H11                      = 0xb6,
++	SC_P0_HIZ_QUAD_PER_TILE_H12                      = 0xb7,
++	SC_P0_HIZ_QUAD_PER_TILE_H13                      = 0xb8,
++	SC_P0_HIZ_QUAD_PER_TILE_H14                      = 0xb9,
++	SC_P0_HIZ_QUAD_PER_TILE_H15                      = 0xba,
++	SC_P0_HIZ_QUAD_PER_TILE_H16                      = 0xbb,
++	SC_P1_HIZ_QUAD_PER_TILE_H0                       = 0xbc,
++	SC_P1_HIZ_QUAD_PER_TILE_H1                       = 0xbd,
++	SC_P1_HIZ_QUAD_PER_TILE_H2                       = 0xbe,
++	SC_P1_HIZ_QUAD_PER_TILE_H3                       = 0xbf,
++	SC_P1_HIZ_QUAD_PER_TILE_H4                       = 0xc0,
++	SC_P1_HIZ_QUAD_PER_TILE_H5                       = 0xc1,
++	SC_P1_HIZ_QUAD_PER_TILE_H6                       = 0xc2,
++	SC_P1_HIZ_QUAD_PER_TILE_H7                       = 0xc3,
++	SC_P1_HIZ_QUAD_PER_TILE_H8                       = 0xc4,
++	SC_P1_HIZ_QUAD_PER_TILE_H9                       = 0xc5,
++	SC_P1_HIZ_QUAD_PER_TILE_H10                      = 0xc6,
++	SC_P1_HIZ_QUAD_PER_TILE_H11                      = 0xc7,
++	SC_P1_HIZ_QUAD_PER_TILE_H12                      = 0xc8,
++	SC_P1_HIZ_QUAD_PER_TILE_H13                      = 0xc9,
++	SC_P1_HIZ_QUAD_PER_TILE_H14                      = 0xca,
++	SC_P1_HIZ_QUAD_PER_TILE_H15                      = 0xcb,
++	SC_P1_HIZ_QUAD_PER_TILE_H16                      = 0xcc,
++	SC_P2_HIZ_QUAD_PER_TILE_H0                       = 0xcd,
++	SC_P2_HIZ_QUAD_PER_TILE_H1                       = 0xce,
++	SC_P2_HIZ_QUAD_PER_TILE_H2                       = 0xcf,
++	SC_P2_HIZ_QUAD_PER_TILE_H3                       = 0xd0,
++	SC_P2_HIZ_QUAD_PER_TILE_H4                       = 0xd1,
++	SC_P2_HIZ_QUAD_PER_TILE_H5                       = 0xd2,
++	SC_P2_HIZ_QUAD_PER_TILE_H6                       = 0xd3,
++	SC_P2_HIZ_QUAD_PER_TILE_H7                       = 0xd4,
++	SC_P2_HIZ_QUAD_PER_TILE_H8                       = 0xd5,
++	SC_P2_HIZ_QUAD_PER_TILE_H9                       = 0xd6,
++	SC_P2_HIZ_QUAD_PER_TILE_H10                      = 0xd7,
++	SC_P2_HIZ_QUAD_PER_TILE_H11                      = 0xd8,
++	SC_P2_HIZ_QUAD_PER_TILE_H12                      = 0xd9,
++	SC_P2_HIZ_QUAD_PER_TILE_H13                      = 0xda,
++	SC_P2_HIZ_QUAD_PER_TILE_H14                      = 0xdb,
++	SC_P2_HIZ_QUAD_PER_TILE_H15                      = 0xdc,
++	SC_P2_HIZ_QUAD_PER_TILE_H16                      = 0xdd,
++	SC_P3_HIZ_QUAD_PER_TILE_H0                       = 0xde,
++	SC_P3_HIZ_QUAD_PER_TILE_H1                       = 0xdf,
++	SC_P3_HIZ_QUAD_PER_TILE_H2                       = 0xe0,
++	SC_P3_HIZ_QUAD_PER_TILE_H3                       = 0xe1,
++	SC_P3_HIZ_QUAD_PER_TILE_H4                       = 0xe2,
++	SC_P3_HIZ_QUAD_PER_TILE_H5                       = 0xe3,
++	SC_P3_HIZ_QUAD_PER_TILE_H6                       = 0xe4,
++	SC_P3_HIZ_QUAD_PER_TILE_H7                       = 0xe5,
++	SC_P3_HIZ_QUAD_PER_TILE_H8                       = 0xe6,
++	SC_P3_HIZ_QUAD_PER_TILE_H9                       = 0xe7,
++	SC_P3_HIZ_QUAD_PER_TILE_H10                      = 0xe8,
++	SC_P3_HIZ_QUAD_PER_TILE_H11                      = 0xe9,
++	SC_P3_HIZ_QUAD_PER_TILE_H12                      = 0xea,
++	SC_P3_HIZ_QUAD_PER_TILE_H13                      = 0xeb,
++	SC_P3_HIZ_QUAD_PER_TILE_H14                      = 0xec,
++	SC_P3_HIZ_QUAD_PER_TILE_H15                      = 0xed,
++	SC_P3_HIZ_QUAD_PER_TILE_H16                      = 0xee,
++	SC_P0_HIZ_QUAD_COUNT                             = 0xef,
++	SC_P1_HIZ_QUAD_COUNT                             = 0xf0,
++	SC_P2_HIZ_QUAD_COUNT                             = 0xf1,
++	SC_P3_HIZ_QUAD_COUNT                             = 0xf2,
++	SC_P0_DETAIL_QUAD_COUNT                          = 0xf3,
++	SC_P1_DETAIL_QUAD_COUNT                          = 0xf4,
++	SC_P2_DETAIL_QUAD_COUNT                          = 0xf5,
++	SC_P3_DETAIL_QUAD_COUNT                          = 0xf6,
++	SC_P0_DETAIL_QUAD_WITH_1_PIX                     = 0xf7,
++	SC_P0_DETAIL_QUAD_WITH_2_PIX                     = 0xf8,
++	SC_P0_DETAIL_QUAD_WITH_3_PIX                     = 0xf9,
++	SC_P0_DETAIL_QUAD_WITH_4_PIX                     = 0xfa,
++	SC_P1_DETAIL_QUAD_WITH_1_PIX                     = 0xfb,
++	SC_P1_DETAIL_QUAD_WITH_2_PIX                     = 0xfc,
++	SC_P1_DETAIL_QUAD_WITH_3_PIX                     = 0xfd,
++	SC_P1_DETAIL_QUAD_WITH_4_PIX                     = 0xfe,
++	SC_P2_DETAIL_QUAD_WITH_1_PIX                     = 0xff,
++	SC_P2_DETAIL_QUAD_WITH_2_PIX                     = 0x100,
++	SC_P2_DETAIL_QUAD_WITH_3_PIX                     = 0x101,
++	SC_P2_DETAIL_QUAD_WITH_4_PIX                     = 0x102,
++	SC_P3_DETAIL_QUAD_WITH_1_PIX                     = 0x103,
++	SC_P3_DETAIL_QUAD_WITH_2_PIX                     = 0x104,
++	SC_P3_DETAIL_QUAD_WITH_3_PIX                     = 0x105,
++	SC_P3_DETAIL_QUAD_WITH_4_PIX                     = 0x106,
++	SC_EARLYZ_QUAD_COUNT                             = 0x107,
++	SC_EARLYZ_QUAD_WITH_1_PIX                        = 0x108,
++	SC_EARLYZ_QUAD_WITH_2_PIX                        = 0x109,
++	SC_EARLYZ_QUAD_WITH_3_PIX                        = 0x10a,
++	SC_EARLYZ_QUAD_WITH_4_PIX                        = 0x10b,
++	SC_PKR_QUAD_PER_ROW_H1                           = 0x10c,
++	SC_PKR_QUAD_PER_ROW_H2                           = 0x10d,
++	SC_PKR_QUAD_PER_ROW_H3                           = 0x10e,
++	SC_PKR_QUAD_PER_ROW_H4                           = 0x10f,
++	SC_PKR_END_OF_VECTOR                             = 0x110,
++	SC_PKR_CONTROL_XFER                              = 0x111,
++	SC_PKR_DBHANG_FORCE_EOV                          = 0x112,
++	SC_REG_SCLK_BUSY                                 = 0x113,
++	SC_GRP0_DYN_SCLK_BUSY                            = 0x114,
++	SC_GRP1_DYN_SCLK_BUSY                            = 0x115,
++	SC_GRP2_DYN_SCLK_BUSY                            = 0x116,
++	SC_GRP3_DYN_SCLK_BUSY                            = 0x117,
++	SC_GRP4_DYN_SCLK_BUSY                            = 0x118,
++	SC_PA0_SC_DATA_FIFO_RD                           = 0x119,
++	SC_PA0_SC_DATA_FIFO_WE                           = 0x11a,
++	SC_PA1_SC_DATA_FIFO_RD                           = 0x11b,
++	SC_PA1_SC_DATA_FIFO_WE                           = 0x11c,
++	SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES           = 0x11d,
++	SC_PS_ARB_XFC_ONLY_PRIM_CYCLES                   = 0x11e,
++	SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM              = 0x11f,
++	SC_PS_ARB_STALLED_FROM_BELOW                     = 0x120,
++	SC_PS_ARB_STARVED_FROM_ABOVE                     = 0x121,
++	SC_PS_ARB_SC_BUSY                                = 0x122,
++	SC_PS_ARB_PA_SC_BUSY                             = 0x123,
++	SC_PA2_SC_DATA_FIFO_RD                           = 0x124,
++	SC_PA2_SC_DATA_FIFO_WE                           = 0x125,
++	SC_PA3_SC_DATA_FIFO_RD                           = 0x126,
++	SC_PA3_SC_DATA_FIFO_WE                           = 0x127,
++	SC_PA_SC_DEALLOC_0_0_WE                          = 0x128,
++	SC_PA_SC_DEALLOC_0_1_WE                          = 0x129,
++	SC_PA_SC_DEALLOC_1_0_WE                          = 0x12a,
++	SC_PA_SC_DEALLOC_1_1_WE                          = 0x12b,
++	SC_PA_SC_DEALLOC_2_0_WE                          = 0x12c,
++	SC_PA_SC_DEALLOC_2_1_WE                          = 0x12d,
++	SC_PA_SC_DEALLOC_3_0_WE                          = 0x12e,
++	SC_PA_SC_DEALLOC_3_1_WE                          = 0x12f,
++	SC_PA0_SC_EOP_WE                                 = 0x130,
++	SC_PA0_SC_EOPG_WE                                = 0x131,
++	SC_PA0_SC_EVENT_WE                               = 0x132,
++	SC_PA1_SC_EOP_WE                                 = 0x133,
++	SC_PA1_SC_EOPG_WE                                = 0x134,
++	SC_PA1_SC_EVENT_WE                               = 0x135,
++	SC_PA2_SC_EOP_WE                                 = 0x136,
++	SC_PA2_SC_EOPG_WE                                = 0x137,
++	SC_PA2_SC_EVENT_WE                               = 0x138,
++	SC_PA3_SC_EOP_WE                                 = 0x139,
++	SC_PA3_SC_EOPG_WE                                = 0x13a,
++	SC_PA3_SC_EVENT_WE                               = 0x13b,
++	SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO   = 0x13c,
++	SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH                  = 0x13d,
++	SC_PS_ARB_NULL_PRIM_BUBBLE_POP                   = 0x13e,
++	SC_PS_ARB_EOP_POP_SYNC_POP                       = 0x13f,
++	SC_PS_ARB_EVENT_SYNC_POP                         = 0x140,
++	SC_SC_PS_ENG_MULTICYCLE_BUBBLE                   = 0x141,
++	SC_PA0_SC_FPOV_WE                                = 0x142,
++	SC_PA1_SC_FPOV_WE                                = 0x143,
++	SC_PA2_SC_FPOV_WE                                = 0x144,
++	SC_PA3_SC_FPOV_WE                                = 0x145,
++	SC_PA0_SC_LPOV_WE                                = 0x146,
++	SC_PA1_SC_LPOV_WE                                = 0x147,
++	SC_PA2_SC_LPOV_WE                                = 0x148,
++	SC_PA3_SC_LPOV_WE                                = 0x149,
++	SC_SC_SPI_DEALLOC_0_0                            = 0x14a,
++	SC_SC_SPI_DEALLOC_0_1                            = 0x14b,
++	SC_SC_SPI_DEALLOC_0_2                            = 0x14c,
++	SC_SC_SPI_DEALLOC_1_0                            = 0x14d,
++	SC_SC_SPI_DEALLOC_1_1                            = 0x14e,
++	SC_SC_SPI_DEALLOC_1_2                            = 0x14f,
++	SC_SC_SPI_DEALLOC_2_0                            = 0x150,
++	SC_SC_SPI_DEALLOC_2_1                            = 0x151,
++	SC_SC_SPI_DEALLOC_2_2                            = 0x152,
++	SC_SC_SPI_DEALLOC_3_0                            = 0x153,
++	SC_SC_SPI_DEALLOC_3_1                            = 0x154,
++	SC_SC_SPI_DEALLOC_3_2                            = 0x155,
++	SC_SC_SPI_FPOV_0                                 = 0x156,
++	SC_SC_SPI_FPOV_1                                 = 0x157,
++	SC_SC_SPI_FPOV_2                                 = 0x158,
++	SC_SC_SPI_FPOV_3                                 = 0x159,
++	SC_SC_SPI_EVENT                                  = 0x15a,
++	SC_PS_TS_EVENT_FIFO_PUSH                         = 0x15b,
++	SC_PS_TS_EVENT_FIFO_POP                          = 0x15c,
++	SC_PS_CTX_DONE_FIFO_PUSH                         = 0x15d,
++	SC_PS_CTX_DONE_FIFO_POP                          = 0x15e,
++	SC_MULTICYCLE_BUBBLE_FREEZE                      = 0x15f,
++	SC_EOP_SYNC_WINDOW                               = 0x160,
++	SC_PA0_SC_NULL_WE                                = 0x161,
++	SC_PA0_SC_NULL_DEALLOC_WE                        = 0x162,
++	SC_PA0_SC_DATA_FIFO_EOPG_RD                      = 0x163,
++	SC_PA0_SC_DATA_FIFO_EOP_RD                       = 0x164,
++	SC_PA0_SC_DEALLOC_0_RD                           = 0x165,
++	SC_PA0_SC_DEALLOC_1_RD                           = 0x166,
++	SC_PA1_SC_DATA_FIFO_EOPG_RD                      = 0x167,
++	SC_PA1_SC_DATA_FIFO_EOP_RD                       = 0x168,
++	SC_PA1_SC_DEALLOC_0_RD                           = 0x169,
++	SC_PA1_SC_DEALLOC_1_RD                           = 0x16a,
++	SC_PA1_SC_NULL_WE                                = 0x16b,
++	SC_PA1_SC_NULL_DEALLOC_WE                        = 0x16c,
++	SC_PA2_SC_DATA_FIFO_EOPG_RD                      = 0x16d,
++	SC_PA2_SC_DATA_FIFO_EOP_RD                       = 0x16e,
++	SC_PA2_SC_DEALLOC_0_RD                           = 0x16f,
++	SC_PA2_SC_DEALLOC_1_RD                           = 0x170,
++	SC_PA2_SC_NULL_WE                                = 0x171,
++	SC_PA2_SC_NULL_DEALLOC_WE                        = 0x172,
++	SC_PA3_SC_DATA_FIFO_EOPG_RD                      = 0x173,
++	SC_PA3_SC_DATA_FIFO_EOP_RD                       = 0x174,
++	SC_PA3_SC_DEALLOC_0_RD                           = 0x175,
++	SC_PA3_SC_DEALLOC_1_RD                           = 0x176,
++	SC_PA3_SC_NULL_WE                                = 0x177,
++	SC_PA3_SC_NULL_DEALLOC_WE                        = 0x178,
++	SC_PS_PA0_SC_FIFO_EMPTY                          = 0x179,
++	SC_PS_PA0_SC_FIFO_FULL                           = 0x17a,
++	SC_PA0_PS_DATA_SEND                              = 0x17b,
++	SC_PS_PA1_SC_FIFO_EMPTY                          = 0x17c,
++	SC_PS_PA1_SC_FIFO_FULL                           = 0x17d,
++	SC_PA1_PS_DATA_SEND                              = 0x17e,
++	SC_PS_PA2_SC_FIFO_EMPTY                          = 0x17f,
++	SC_PS_PA2_SC_FIFO_FULL                           = 0x180,
++	SC_PA2_PS_DATA_SEND                              = 0x181,
++	SC_PS_PA3_SC_FIFO_EMPTY                          = 0x182,
++	SC_PS_PA3_SC_FIFO_FULL                           = 0x183,
++	SC_PA3_PS_DATA_SEND                              = 0x184,
++	SC_BUSY_PROCESSING_MULTICYCLE_PRIM               = 0x185,
++	SC_BUSY_CNT_NOT_ZERO                             = 0x186,
++	SC_BM_BUSY                                       = 0x187,
++	SC_BACKEND_BUSY                                  = 0x188,
++	SC_SCF_SCB_INTERFACE_BUSY                        = 0x189,
++	SC_SCB_BUSY                                      = 0x18a,
++	SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY    = 0x18b,
++	SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL         = 0x18c,
++} SC_PERFCNT_SEL;
++typedef enum SePairXsel {
++	RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE           = 0x0,
++	RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE          = 0x1,
++	RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE          = 0x2,
++	RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE          = 0x3,
++} SePairXsel;
++typedef enum SePairYsel {
++	RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE           = 0x0,
++	RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE          = 0x1,
++	RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE          = 0x2,
++	RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE          = 0x3,
++} SePairYsel;
++typedef enum SePairMap {
++	RASTER_CONFIG_SE_PAIR_MAP_0                      = 0x0,
++	RASTER_CONFIG_SE_PAIR_MAP_1                      = 0x1,
++	RASTER_CONFIG_SE_PAIR_MAP_2                      = 0x2,
++	RASTER_CONFIG_SE_PAIR_MAP_3                      = 0x3,
++} SePairMap;
++typedef enum SeXsel {
++	RASTER_CONFIG_SE_XSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SE_XSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SE_XSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SE_XSEL_64_WIDE_TILE               = 0x3,
++} SeXsel;
++typedef enum SeYsel {
++	RASTER_CONFIG_SE_YSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SE_YSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SE_YSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SE_YSEL_64_WIDE_TILE               = 0x3,
++} SeYsel;
++typedef enum SeMap {
++	RASTER_CONFIG_SE_MAP_0                           = 0x0,
++	RASTER_CONFIG_SE_MAP_1                           = 0x1,
++	RASTER_CONFIG_SE_MAP_2                           = 0x2,
++	RASTER_CONFIG_SE_MAP_3                           = 0x3,
++} SeMap;
++typedef enum ScXsel {
++	RASTER_CONFIG_SC_XSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SC_XSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SC_XSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SC_XSEL_64_WIDE_TILE               = 0x3,
++} ScXsel;
++typedef enum ScYsel {
++	RASTER_CONFIG_SC_YSEL_8_WIDE_TILE                = 0x0,
++	RASTER_CONFIG_SC_YSEL_16_WIDE_TILE               = 0x1,
++	RASTER_CONFIG_SC_YSEL_32_WIDE_TILE               = 0x2,
++	RASTER_CONFIG_SC_YSEL_64_WIDE_TILE               = 0x3,
++} ScYsel;
++typedef enum ScMap {
++	RASTER_CONFIG_SC_MAP_0                           = 0x0,
++	RASTER_CONFIG_SC_MAP_1                           = 0x1,
++	RASTER_CONFIG_SC_MAP_2                           = 0x2,
++	RASTER_CONFIG_SC_MAP_3                           = 0x3,
++} ScMap;
++typedef enum PkrXsel2 {
++	RASTER_CONFIG_PKR_XSEL2_0                        = 0x0,
++	RASTER_CONFIG_PKR_XSEL2_1                        = 0x1,
++	RASTER_CONFIG_PKR_XSEL2_2                        = 0x2,
++	RASTER_CONFIG_PKR_XSEL2_3                        = 0x3,
++} PkrXsel2;
++typedef enum PkrXsel {
++	RASTER_CONFIG_PKR_XSEL_0                         = 0x0,
++	RASTER_CONFIG_PKR_XSEL_1                         = 0x1,
++	RASTER_CONFIG_PKR_XSEL_2                         = 0x2,
++	RASTER_CONFIG_PKR_XSEL_3                         = 0x3,
++} PkrXsel;
++typedef enum PkrYsel {
++	RASTER_CONFIG_PKR_YSEL_0                         = 0x0,
++	RASTER_CONFIG_PKR_YSEL_1                         = 0x1,
++	RASTER_CONFIG_PKR_YSEL_2                         = 0x2,
++	RASTER_CONFIG_PKR_YSEL_3                         = 0x3,
++} PkrYsel;
++typedef enum PkrMap {
++	RASTER_CONFIG_PKR_MAP_0                          = 0x0,
++	RASTER_CONFIG_PKR_MAP_1                          = 0x1,
++	RASTER_CONFIG_PKR_MAP_2                          = 0x2,
++	RASTER_CONFIG_PKR_MAP_3                          = 0x3,
++} PkrMap;
++typedef enum RbXsel {
++	RASTER_CONFIG_RB_XSEL_0                          = 0x0,
++	RASTER_CONFIG_RB_XSEL_1                          = 0x1,
++} RbXsel;
++typedef enum RbYsel {
++	RASTER_CONFIG_RB_YSEL_0                          = 0x0,
++	RASTER_CONFIG_RB_YSEL_1                          = 0x1,
++} RbYsel;
++typedef enum RbXsel2 {
++	RASTER_CONFIG_RB_XSEL2_0                         = 0x0,
++	RASTER_CONFIG_RB_XSEL2_1                         = 0x1,
++	RASTER_CONFIG_RB_XSEL2_2                         = 0x2,
++	RASTER_CONFIG_RB_XSEL2_3                         = 0x3,
++} RbXsel2;
++typedef enum RbMap {
++	RASTER_CONFIG_RB_MAP_0                           = 0x0,
++	RASTER_CONFIG_RB_MAP_1                           = 0x1,
++	RASTER_CONFIG_RB_MAP_2                           = 0x2,
++	RASTER_CONFIG_RB_MAP_3                           = 0x3,
++} RbMap;
++typedef enum CSDATA_TYPE {
++	CSDATA_TYPE_TG                                   = 0x0,
++	CSDATA_TYPE_STATE                                = 0x1,
++	CSDATA_TYPE_EVENT                                = 0x2,
++	CSDATA_TYPE_PRIVATE                              = 0x3,
++} CSDATA_TYPE;
++#define CSDATA_TYPE_WIDTH                         0x2
++#define CSDATA_ADDR_WIDTH                         0x7
++#define CSDATA_DATA_WIDTH                         0x20
++typedef enum SPI_SAMPLE_CNTL {
++	CENTROIDS_ONLY                                   = 0x0,
++	CENTERS_ONLY                                     = 0x1,
++	CENTROIDS_AND_CENTERS                            = 0x2,
++	UNDEF                                            = 0x3,
++} SPI_SAMPLE_CNTL;
++typedef enum SPI_FOG_MODE {
++	SPI_FOG_NONE                                     = 0x0,
++	SPI_FOG_EXP                                      = 0x1,
++	SPI_FOG_EXP2                                     = 0x2,
++	SPI_FOG_LINEAR                                   = 0x3,
++} SPI_FOG_MODE;
++typedef enum SPI_PNT_SPRITE_OVERRIDE {
++	SPI_PNT_SPRITE_SEL_0                             = 0x0,
++	SPI_PNT_SPRITE_SEL_1                             = 0x1,
++	SPI_PNT_SPRITE_SEL_S                             = 0x2,
++	SPI_PNT_SPRITE_SEL_T                             = 0x3,
++	SPI_PNT_SPRITE_SEL_NONE                          = 0x4,
++} SPI_PNT_SPRITE_OVERRIDE;
++typedef enum SPI_PERFCNT_SEL {
++	SPI_PERF_VS_WINDOW_VALID                         = 0x0,
++	SPI_PERF_VS_BUSY                                 = 0x1,
++	SPI_PERF_VS_FIRST_WAVE                           = 0x2,
++	SPI_PERF_VS_LAST_WAVE                            = 0x3,
++	SPI_PERF_VS_LSHS_DEALLOC                         = 0x4,
++	SPI_PERF_VS_PC_STALL                             = 0x5,
++	SPI_PERF_VS_POS0_STALL                           = 0x6,
++	SPI_PERF_VS_POS1_STALL                           = 0x7,
++	SPI_PERF_VS_CRAWLER_STALL                        = 0x8,
++	SPI_PERF_VS_EVENT_WAVE                           = 0x9,
++	SPI_PERF_VS_WAVE                                 = 0xa,
++	SPI_PERF_VS_PERS_UPD_FULL0                       = 0xb,
++	SPI_PERF_VS_PERS_UPD_FULL1                       = 0xc,
++	SPI_PERF_VS_LATE_ALLOC_FULL                      = 0xd,
++	SPI_PERF_VS_FIRST_SUBGRP                         = 0xe,
++	SPI_PERF_VS_LAST_SUBGRP                          = 0xf,
++	SPI_PERF_GS_WINDOW_VALID                         = 0x10,
++	SPI_PERF_GS_BUSY                                 = 0x11,
++	SPI_PERF_GS_CRAWLER_STALL                        = 0x12,
++	SPI_PERF_GS_EVENT_WAVE                           = 0x13,
++	SPI_PERF_GS_WAVE                                 = 0x14,
++	SPI_PERF_GS_PERS_UPD_FULL0                       = 0x15,
++	SPI_PERF_GS_PERS_UPD_FULL1                       = 0x16,
++	SPI_PERF_GS_FIRST_SUBGRP                         = 0x17,
++	SPI_PERF_GS_LAST_SUBGRP                          = 0x18,
++	SPI_PERF_ES_WINDOW_VALID                         = 0x19,
++	SPI_PERF_ES_BUSY                                 = 0x1a,
++	SPI_PERF_ES_CRAWLER_STALL                        = 0x1b,
++	SPI_PERF_ES_FIRST_WAVE                           = 0x1c,
++	SPI_PERF_ES_LAST_WAVE                            = 0x1d,
++	SPI_PERF_ES_LSHS_DEALLOC                         = 0x1e,
++	SPI_PERF_ES_EVENT_WAVE                           = 0x1f,
++	SPI_PERF_ES_WAVE                                 = 0x20,
++	SPI_PERF_ES_PERS_UPD_FULL0                       = 0x21,
++	SPI_PERF_ES_PERS_UPD_FULL1                       = 0x22,
++	SPI_PERF_ES_FIRST_SUBGRP                         = 0x23,
++	SPI_PERF_ES_LAST_SUBGRP                          = 0x24,
++	SPI_PERF_HS_WINDOW_VALID                         = 0x25,
++	SPI_PERF_HS_BUSY                                 = 0x26,
++	SPI_PERF_HS_CRAWLER_STALL                        = 0x27,
++	SPI_PERF_HS_FIRST_WAVE                           = 0x28,
++	SPI_PERF_HS_LAST_WAVE                            = 0x29,
++	SPI_PERF_HS_LSHS_DEALLOC                         = 0x2a,
++	SPI_PERF_HS_EVENT_WAVE                           = 0x2b,
++	SPI_PERF_HS_WAVE                                 = 0x2c,
++	SPI_PERF_HS_PERS_UPD_FULL0                       = 0x2d,
++	SPI_PERF_HS_PERS_UPD_FULL1                       = 0x2e,
++	SPI_PERF_LS_WINDOW_VALID                         = 0x2f,
++	SPI_PERF_LS_BUSY                                 = 0x30,
++	SPI_PERF_LS_CRAWLER_STALL                        = 0x31,
++	SPI_PERF_LS_FIRST_WAVE                           = 0x32,
++	SPI_PERF_LS_LAST_WAVE                            = 0x33,
++	SPI_PERF_OFFCHIP_LDS_STALL_LS                    = 0x34,
++	SPI_PERF_LS_EVENT_WAVE                           = 0x35,
++	SPI_PERF_LS_WAVE                                 = 0x36,
++	SPI_PERF_LS_PERS_UPD_FULL0                       = 0x37,
++	SPI_PERF_LS_PERS_UPD_FULL1                       = 0x38,
++	SPI_PERF_CSG_WINDOW_VALID                        = 0x39,
++	SPI_PERF_CSG_BUSY                                = 0x3a,
++	SPI_PERF_CSG_NUM_THREADGROUPS                    = 0x3b,
++	SPI_PERF_CSG_CRAWLER_STALL                       = 0x3c,
++	SPI_PERF_CSG_EVENT_WAVE                          = 0x3d,
++	SPI_PERF_CSG_WAVE                                = 0x3e,
++	SPI_PERF_CSN_WINDOW_VALID                        = 0x3f,
++	SPI_PERF_CSN_BUSY                                = 0x40,
++	SPI_PERF_CSN_NUM_THREADGROUPS                    = 0x41,
++	SPI_PERF_CSN_CRAWLER_STALL                       = 0x42,
++	SPI_PERF_CSN_EVENT_WAVE                          = 0x43,
++	SPI_PERF_CSN_WAVE                                = 0x44,
++	SPI_PERF_PS_CTL_WINDOW_VALID                     = 0x45,
++	SPI_PERF_PS_CTL_BUSY                             = 0x46,
++	SPI_PERF_PS_CTL_ACTIVE                           = 0x47,
++	SPI_PERF_PS_CTL_DEALLOC_BIN0                     = 0x48,
++	SPI_PERF_PS_CTL_FPOS_BIN1_STALL                  = 0x49,
++	SPI_PERF_PS_CTL_EVENT_WAVE                       = 0x4a,
++	SPI_PERF_PS_CTL_WAVE                             = 0x4b,
++	SPI_PERF_PS_CTL_OPT_WAVE                         = 0x4c,
++	SPI_PERF_PS_CTL_PASS_BIN0                        = 0x4d,
++	SPI_PERF_PS_CTL_PASS_BIN1                        = 0x4e,
++	SPI_PERF_PS_CTL_FPOS_BIN2                        = 0x4f,
++	SPI_PERF_PS_CTL_PRIM_BIN0                        = 0x50,
++	SPI_PERF_PS_CTL_PRIM_BIN1                        = 0x51,
++	SPI_PERF_PS_CTL_CNF_BIN2                         = 0x52,
++	SPI_PERF_PS_CTL_CNF_BIN3                         = 0x53,
++	SPI_PERF_PS_CTL_CRAWLER_STALL                    = 0x54,
++	SPI_PERF_PS_CTL_LDS_RES_FULL                     = 0x55,
++	SPI_PERF_PS_PERS_UPD_FULL0                       = 0x56,
++	SPI_PERF_PS_PERS_UPD_FULL1                       = 0x57,
++	SPI_PERF_PIX_ALLOC_PEND_CNT                      = 0x58,
++	SPI_PERF_PIX_ALLOC_SCB_STALL                     = 0x59,
++	SPI_PERF_PIX_ALLOC_DB0_STALL                     = 0x5a,
++	SPI_PERF_PIX_ALLOC_DB1_STALL                     = 0x5b,
++	SPI_PERF_PIX_ALLOC_DB2_STALL                     = 0x5c,
++	SPI_PERF_PIX_ALLOC_DB3_STALL                     = 0x5d,
++	SPI_PERF_LDS0_PC_VALID                           = 0x5e,
++	SPI_PERF_LDS1_PC_VALID                           = 0x5f,
++	SPI_PERF_RA_PIPE_REQ_BIN2                        = 0x60,
++	SPI_PERF_RA_TASK_REQ_BIN3                        = 0x61,
++	SPI_PERF_RA_WR_CTL_FULL                          = 0x62,
++	SPI_PERF_RA_REQ_NO_ALLOC                         = 0x63,
++	SPI_PERF_RA_REQ_NO_ALLOC_PS                      = 0x64,
++	SPI_PERF_RA_REQ_NO_ALLOC_VS                      = 0x65,
++	SPI_PERF_RA_REQ_NO_ALLOC_GS                      = 0x66,
++	SPI_PERF_RA_REQ_NO_ALLOC_ES                      = 0x67,
++	SPI_PERF_RA_REQ_NO_ALLOC_HS                      = 0x68,
++	SPI_PERF_RA_REQ_NO_ALLOC_LS                      = 0x69,
++	SPI_PERF_RA_REQ_NO_ALLOC_CSG                     = 0x6a,
++	SPI_PERF_RA_REQ_NO_ALLOC_CSN                     = 0x6b,
++	SPI_PERF_RA_RES_STALL_PS                         = 0x6c,
++	SPI_PERF_RA_RES_STALL_VS                         = 0x6d,
++	SPI_PERF_RA_RES_STALL_GS                         = 0x6e,
++	SPI_PERF_RA_RES_STALL_ES                         = 0x6f,
++	SPI_PERF_RA_RES_STALL_HS                         = 0x70,
++	SPI_PERF_RA_RES_STALL_LS                         = 0x71,
++	SPI_PERF_RA_RES_STALL_CSG                        = 0x72,
++	SPI_PERF_RA_RES_STALL_CSN                        = 0x73,
++	SPI_PERF_RA_TMP_STALL_PS                         = 0x74,
++	SPI_PERF_RA_TMP_STALL_VS                         = 0x75,
++	SPI_PERF_RA_TMP_STALL_GS                         = 0x76,
++	SPI_PERF_RA_TMP_STALL_ES                         = 0x77,
++	SPI_PERF_RA_TMP_STALL_HS                         = 0x78,
++	SPI_PERF_RA_TMP_STALL_LS                         = 0x79,
++	SPI_PERF_RA_TMP_STALL_CSG                        = 0x7a,
++	SPI_PERF_RA_TMP_STALL_CSN                        = 0x7b,
++	SPI_PERF_RA_WAVE_SIMD_FULL_PS                    = 0x7c,
++	SPI_PERF_RA_WAVE_SIMD_FULL_VS                    = 0x7d,
++	SPI_PERF_RA_WAVE_SIMD_FULL_GS                    = 0x7e,
++	SPI_PERF_RA_WAVE_SIMD_FULL_ES                    = 0x7f,
++	SPI_PERF_RA_WAVE_SIMD_FULL_HS                    = 0x80,
++	SPI_PERF_RA_WAVE_SIMD_FULL_LS                    = 0x81,
++	SPI_PERF_RA_WAVE_SIMD_FULL_CSG                   = 0x82,
++	SPI_PERF_RA_WAVE_SIMD_FULL_CSN                   = 0x83,
++	SPI_PERF_RA_VGPR_SIMD_FULL_PS                    = 0x84,
++	SPI_PERF_RA_VGPR_SIMD_FULL_VS                    = 0x85,
++	SPI_PERF_RA_VGPR_SIMD_FULL_GS                    = 0x86,
++	SPI_PERF_RA_VGPR_SIMD_FULL_ES                    = 0x87,
++	SPI_PERF_RA_VGPR_SIMD_FULL_HS                    = 0x88,
++	SPI_PERF_RA_VGPR_SIMD_FULL_LS                    = 0x89,
++	SPI_PERF_RA_VGPR_SIMD_FULL_CSG                   = 0x8a,
++	SPI_PERF_RA_VGPR_SIMD_FULL_CSN                   = 0x8b,
++	SPI_PERF_RA_SGPR_SIMD_FULL_PS                    = 0x8c,
++	SPI_PERF_RA_SGPR_SIMD_FULL_VS                    = 0x8d,
++	SPI_PERF_RA_SGPR_SIMD_FULL_GS                    = 0x8e,
++	SPI_PERF_RA_SGPR_SIMD_FULL_ES                    = 0x8f,
++	SPI_PERF_RA_SGPR_SIMD_FULL_HS                    = 0x90,
++	SPI_PERF_RA_SGPR_SIMD_FULL_LS                    = 0x91,
++	SPI_PERF_RA_SGPR_SIMD_FULL_CSG                   = 0x92,
++	SPI_PERF_RA_SGPR_SIMD_FULL_CSN                   = 0x93,
++	SPI_PERF_RA_LDS_CU_FULL_PS                       = 0x94,
++	SPI_PERF_RA_LDS_CU_FULL_LS                       = 0x95,
++	SPI_PERF_RA_LDS_CU_FULL_ES                       = 0x96,
++	SPI_PERF_RA_LDS_CU_FULL_CSG                      = 0x97,
++	SPI_PERF_RA_LDS_CU_FULL_CSN                      = 0x98,
++	SPI_PERF_RA_BAR_CU_FULL_HS                       = 0x99,
++	SPI_PERF_RA_BAR_CU_FULL_CSG                      = 0x9a,
++	SPI_PERF_RA_BAR_CU_FULL_CSN                      = 0x9b,
++	SPI_PERF_RA_BULKY_CU_FULL_CSG                    = 0x9c,
++	SPI_PERF_RA_BULKY_CU_FULL_CSN                    = 0x9d,
++	SPI_PERF_RA_TGLIM_CU_FULL_CSG                    = 0x9e,
++	SPI_PERF_RA_TGLIM_CU_FULL_CSN                    = 0x9f,
++	SPI_PERF_RA_WVLIM_STALL_PS                       = 0xa0,
++	SPI_PERF_RA_WVLIM_STALL_VS                       = 0xa1,
++	SPI_PERF_RA_WVLIM_STALL_GS                       = 0xa2,
++	SPI_PERF_RA_WVLIM_STALL_ES                       = 0xa3,
++	SPI_PERF_RA_WVLIM_STALL_HS                       = 0xa4,
++	SPI_PERF_RA_WVLIM_STALL_LS                       = 0xa5,
++	SPI_PERF_RA_WVLIM_STALL_CSG                      = 0xa6,
++	SPI_PERF_RA_WVLIM_STALL_CSN                      = 0xa7,
++	SPI_PERF_RA_PS_LOCK_NA                           = 0xa8,
++	SPI_PERF_RA_VS_LOCK                              = 0xa9,
++	SPI_PERF_RA_GS_LOCK                              = 0xaa,
++	SPI_PERF_RA_ES_LOCK                              = 0xab,
++	SPI_PERF_RA_HS_LOCK                              = 0xac,
++	SPI_PERF_RA_LS_LOCK                              = 0xad,
++	SPI_PERF_RA_CSG_LOCK                             = 0xae,
++	SPI_PERF_RA_CSN_LOCK                             = 0xaf,
++	SPI_PERF_RA_RSV_UPD                              = 0xb0,
++	SPI_PERF_EXP_ARB_COL_CNT                         = 0xb1,
++	SPI_PERF_EXP_ARB_PAR_CNT                         = 0xb2,
++	SPI_PERF_EXP_ARB_POS_CNT                         = 0xb3,
++	SPI_PERF_EXP_ARB_GDS_CNT                         = 0xb4,
++	SPI_PERF_CLKGATE_BUSY_STALL                      = 0xb5,
++	SPI_PERF_CLKGATE_ACTIVE_STALL                    = 0xb6,
++	SPI_PERF_CLKGATE_ALL_CLOCKS_ON                   = 0xb7,
++	SPI_PERF_CLKGATE_CGTT_DYN_ON                     = 0xb8,
++	SPI_PERF_CLKGATE_CGTT_REG_ON                     = 0xb9,
++	SPI_PERF_NUM_VS_POS_EXPORTS                      = 0xba,
++	SPI_PERF_NUM_VS_PARAM_EXPORTS                    = 0xbb,
++	SPI_PERF_NUM_PS_COL_EXPORTS                      = 0xbc,
++	SPI_PERF_ES_GRP_FIFO_FULL                        = 0xbd,
++	SPI_PERF_GS_GRP_FIFO_FULL                        = 0xbe,
++	SPI_PERF_HS_GRP_FIFO_FULL                        = 0xbf,
++	SPI_PERF_LS_GRP_FIFO_FULL                        = 0xc0,
++	SPI_PERF_VS_ALLOC_CNT                            = 0xc1,
++	SPI_PERF_VS_LATE_ALLOC_ACCUM                     = 0xc2,
++	SPI_PERF_PC_ALLOC_CNT                            = 0xc3,
++	SPI_PERF_PC_ALLOC_ACCUM                          = 0xc4,
++} SPI_PERFCNT_SEL;
++typedef enum SPI_SHADER_FORMAT {
++	SPI_SHADER_NONE                                  = 0x0,
++	SPI_SHADER_1COMP                                 = 0x1,
++	SPI_SHADER_2COMP                                 = 0x2,
++	SPI_SHADER_4COMPRESS                             = 0x3,
++	SPI_SHADER_4COMP                                 = 0x4,
++} SPI_SHADER_FORMAT;
++typedef enum SPI_SHADER_EX_FORMAT {
++	SPI_SHADER_ZERO                                  = 0x0,
++	SPI_SHADER_32_R                                  = 0x1,
++	SPI_SHADER_32_GR                                 = 0x2,
++	SPI_SHADER_32_AR                                 = 0x3,
++	SPI_SHADER_FP16_ABGR                             = 0x4,
++	SPI_SHADER_UNORM16_ABGR                          = 0x5,
++	SPI_SHADER_SNORM16_ABGR                          = 0x6,
++	SPI_SHADER_UINT16_ABGR                           = 0x7,
++	SPI_SHADER_SINT16_ABGR                           = 0x8,
++	SPI_SHADER_32_ABGR                               = 0x9,
++} SPI_SHADER_EX_FORMAT;
++typedef enum CLKGATE_SM_MODE {
++	ON_SEQ                                           = 0x0,
++	OFF_SEQ                                          = 0x1,
++	PROG_SEQ                                         = 0x2,
++	READ_SEQ                                         = 0x3,
++	SM_MODE_RESERVED                                 = 0x4,
++} CLKGATE_SM_MODE;
++typedef enum CLKGATE_BASE_MODE {
++	MULT_8                                           = 0x0,
++	MULT_16                                          = 0x1,
++} CLKGATE_BASE_MODE;
++typedef enum SQ_TEX_CLAMP {
++	SQ_TEX_WRAP                                      = 0x0,
++	SQ_TEX_MIRROR                                    = 0x1,
++	SQ_TEX_CLAMP_LAST_TEXEL                          = 0x2,
++	SQ_TEX_MIRROR_ONCE_LAST_TEXEL                    = 0x3,
++	SQ_TEX_CLAMP_HALF_BORDER                         = 0x4,
++	SQ_TEX_MIRROR_ONCE_HALF_BORDER                   = 0x5,
++	SQ_TEX_CLAMP_BORDER                              = 0x6,
++	SQ_TEX_MIRROR_ONCE_BORDER                        = 0x7,
++} SQ_TEX_CLAMP;
++typedef enum SQ_TEX_XY_FILTER {
++	SQ_TEX_XY_FILTER_POINT                           = 0x0,
++	SQ_TEX_XY_FILTER_BILINEAR                        = 0x1,
++	SQ_TEX_XY_FILTER_ANISO_POINT                     = 0x2,
++	SQ_TEX_XY_FILTER_ANISO_BILINEAR                  = 0x3,
++} SQ_TEX_XY_FILTER;
++typedef enum SQ_TEX_Z_FILTER {
++	SQ_TEX_Z_FILTER_NONE                             = 0x0,
++	SQ_TEX_Z_FILTER_POINT                            = 0x1,
++	SQ_TEX_Z_FILTER_LINEAR                           = 0x2,
++} SQ_TEX_Z_FILTER;
++typedef enum SQ_TEX_MIP_FILTER {
++	SQ_TEX_MIP_FILTER_NONE                           = 0x0,
++	SQ_TEX_MIP_FILTER_POINT                          = 0x1,
++	SQ_TEX_MIP_FILTER_LINEAR                         = 0x2,
++	SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ                = 0x3,
++} SQ_TEX_MIP_FILTER;
++typedef enum SQ_TEX_ANISO_RATIO {
++	SQ_TEX_ANISO_RATIO_1                             = 0x0,
++	SQ_TEX_ANISO_RATIO_2                             = 0x1,
++	SQ_TEX_ANISO_RATIO_4                             = 0x2,
++	SQ_TEX_ANISO_RATIO_8                             = 0x3,
++	SQ_TEX_ANISO_RATIO_16                            = 0x4,
++} SQ_TEX_ANISO_RATIO;
++typedef enum SQ_TEX_DEPTH_COMPARE {
++	SQ_TEX_DEPTH_COMPARE_NEVER                       = 0x0,
++	SQ_TEX_DEPTH_COMPARE_LESS                        = 0x1,
++	SQ_TEX_DEPTH_COMPARE_EQUAL                       = 0x2,
++	SQ_TEX_DEPTH_COMPARE_LESSEQUAL                   = 0x3,
++	SQ_TEX_DEPTH_COMPARE_GREATER                     = 0x4,
++	SQ_TEX_DEPTH_COMPARE_NOTEQUAL                    = 0x5,
++	SQ_TEX_DEPTH_COMPARE_GREATEREQUAL                = 0x6,
++	SQ_TEX_DEPTH_COMPARE_ALWAYS                      = 0x7,
++} SQ_TEX_DEPTH_COMPARE;
++typedef enum SQ_TEX_BORDER_COLOR {
++	SQ_TEX_BORDER_COLOR_TRANS_BLACK                  = 0x0,
++	SQ_TEX_BORDER_COLOR_OPAQUE_BLACK                 = 0x1,
++	SQ_TEX_BORDER_COLOR_OPAQUE_WHITE                 = 0x2,
++	SQ_TEX_BORDER_COLOR_REGISTER                     = 0x3,
++} SQ_TEX_BORDER_COLOR;
++typedef enum SQ_RSRC_BUF_TYPE {
++	SQ_RSRC_BUF                                      = 0x0,
++	SQ_RSRC_BUF_RSVD_1                               = 0x1,
++	SQ_RSRC_BUF_RSVD_2                               = 0x2,
++	SQ_RSRC_BUF_RSVD_3                               = 0x3,
++} SQ_RSRC_BUF_TYPE;
++typedef enum SQ_RSRC_IMG_TYPE {
++	SQ_RSRC_IMG_RSVD_0                               = 0x0,
++	SQ_RSRC_IMG_RSVD_1                               = 0x1,
++	SQ_RSRC_IMG_RSVD_2                               = 0x2,
++	SQ_RSRC_IMG_RSVD_3                               = 0x3,
++	SQ_RSRC_IMG_RSVD_4                               = 0x4,
++	SQ_RSRC_IMG_RSVD_5                               = 0x5,
++	SQ_RSRC_IMG_RSVD_6                               = 0x6,
++	SQ_RSRC_IMG_RSVD_7                               = 0x7,
++	SQ_RSRC_IMG_1D                                   = 0x8,
++	SQ_RSRC_IMG_2D                                   = 0x9,
++	SQ_RSRC_IMG_3D                                   = 0xa,
++	SQ_RSRC_IMG_CUBE                                 = 0xb,
++	SQ_RSRC_IMG_1D_ARRAY                             = 0xc,
++	SQ_RSRC_IMG_2D_ARRAY                             = 0xd,
++	SQ_RSRC_IMG_2D_MSAA                              = 0xe,
++	SQ_RSRC_IMG_2D_MSAA_ARRAY                        = 0xf,
++} SQ_RSRC_IMG_TYPE;
++typedef enum SQ_RSRC_FLAT_TYPE {
++	SQ_RSRC_FLAT_RSVD_0                              = 0x0,
++	SQ_RSRC_FLAT                                     = 0x1,
++	SQ_RSRC_FLAT_RSVD_2                              = 0x2,
++	SQ_RSRC_FLAT_RSVD_3                              = 0x3,
++} SQ_RSRC_FLAT_TYPE;
++typedef enum SQ_IMG_FILTER_TYPE {
++	SQ_IMG_FILTER_MODE_BLEND                         = 0x0,
++	SQ_IMG_FILTER_MODE_MIN                           = 0x1,
++	SQ_IMG_FILTER_MODE_MAX                           = 0x2,
++} SQ_IMG_FILTER_TYPE;
++typedef enum SQ_SEL_XYZW01 {
++	SQ_SEL_0                                         = 0x0,
++	SQ_SEL_1                                         = 0x1,
++	SQ_SEL_RESERVED_0                                = 0x2,
++	SQ_SEL_RESERVED_1                                = 0x3,
++	SQ_SEL_X                                         = 0x4,
++	SQ_SEL_Y                                         = 0x5,
++	SQ_SEL_Z                                         = 0x6,
++	SQ_SEL_W                                         = 0x7,
++} SQ_SEL_XYZW01;
++typedef enum SQ_WAVE_TYPE {
++	SQ_WAVE_TYPE_PS                                  = 0x0,
++	SQ_WAVE_TYPE_VS                                  = 0x1,
++	SQ_WAVE_TYPE_GS                                  = 0x2,
++	SQ_WAVE_TYPE_ES                                  = 0x3,
++	SQ_WAVE_TYPE_HS                                  = 0x4,
++	SQ_WAVE_TYPE_LS                                  = 0x5,
++	SQ_WAVE_TYPE_CS                                  = 0x6,
++	SQ_WAVE_TYPE_PS1                                 = 0x7,
++} SQ_WAVE_TYPE;
++typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
++	SQ_THREAD_TRACE_TOKEN_MISC                       = 0x0,
++	SQ_THREAD_TRACE_TOKEN_TIMESTAMP                  = 0x1,
++	SQ_THREAD_TRACE_TOKEN_REG                        = 0x2,
++	SQ_THREAD_TRACE_TOKEN_WAVE_START                 = 0x3,
++	SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC                 = 0x4,
++	SQ_THREAD_TRACE_TOKEN_REG_CSPRIV                 = 0x5,
++	SQ_THREAD_TRACE_TOKEN_WAVE_END                   = 0x6,
++	SQ_THREAD_TRACE_TOKEN_EVENT                      = 0x7,
++	SQ_THREAD_TRACE_TOKEN_EVENT_CS                   = 0x8,
++	SQ_THREAD_TRACE_TOKEN_EVENT_GFX1                 = 0x9,
++	SQ_THREAD_TRACE_TOKEN_INST                       = 0xa,
++	SQ_THREAD_TRACE_TOKEN_INST_PC                    = 0xb,
++	SQ_THREAD_TRACE_TOKEN_INST_USERDATA              = 0xc,
++	SQ_THREAD_TRACE_TOKEN_ISSUE                      = 0xd,
++	SQ_THREAD_TRACE_TOKEN_PERF                       = 0xe,
++	SQ_THREAD_TRACE_TOKEN_REG_CS                     = 0xf,
++} SQ_THREAD_TRACE_TOKEN_TYPE;
++typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
++	SQ_THREAD_TRACE_MISC_TOKEN_TIME                  = 0x0,
++	SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET            = 0x1,
++	SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST           = 0x2,
++	SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC             = 0x3,
++	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN    = 0x4,
++	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END      = 0x5,
++	SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX               = 0x6,
++	SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN            = 0x7,
++} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
++typedef enum SQ_THREAD_TRACE_INST_TYPE {
++	SQ_THREAD_TRACE_INST_TYPE_SMEM_RD                = 0x0,
++	SQ_THREAD_TRACE_INST_TYPE_SALU_32                = 0x1,
++	SQ_THREAD_TRACE_INST_TYPE_VMEM_RD                = 0x2,
++	SQ_THREAD_TRACE_INST_TYPE_VMEM_WR                = 0x3,
++	SQ_THREAD_TRACE_INST_TYPE_FLAT_WR                = 0x4,
++	SQ_THREAD_TRACE_INST_TYPE_VALU_32                = 0x5,
++	SQ_THREAD_TRACE_INST_TYPE_LDS                    = 0x6,
++	SQ_THREAD_TRACE_INST_TYPE_PC                     = 0x7,
++	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS             = 0x8,
++	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX             = 0x9,
++	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL         = 0xa,
++	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS         = 0xb,
++	SQ_THREAD_TRACE_INST_TYPE_JUMP                   = 0xc,
++	SQ_THREAD_TRACE_INST_TYPE_NEXT                   = 0xd,
++	SQ_THREAD_TRACE_INST_TYPE_FLAT_RD                = 0xe,
++	SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG              = 0xf,
++	SQ_THREAD_TRACE_INST_TYPE_SMEM_WR                = 0x10,
++	SQ_THREAD_TRACE_INST_TYPE_SALU_64                = 0x11,
++	SQ_THREAD_TRACE_INST_TYPE_VALU_64                = 0x12,
++	SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY         = 0x13,
++	SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY         = 0x14,
++	SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY         = 0x15,
++	SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY         = 0x16,
++	SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY         = 0x17,
++	SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY         = 0x18,
++} SQ_THREAD_TRACE_INST_TYPE;
++typedef enum SQ_THREAD_TRACE_REG_TYPE {
++	SQ_THREAD_TRACE_REG_TYPE_EVENT                   = 0x0,
++	SQ_THREAD_TRACE_REG_TYPE_DRAW                    = 0x1,
++	SQ_THREAD_TRACE_REG_TYPE_DISPATCH                = 0x2,
++	SQ_THREAD_TRACE_REG_TYPE_USERDATA                = 0x3,
++	SQ_THREAD_TRACE_REG_TYPE_MARKER                  = 0x4,
++	SQ_THREAD_TRACE_REG_TYPE_GFXDEC                  = 0x5,
++	SQ_THREAD_TRACE_REG_TYPE_SHDEC                   = 0x6,
++	SQ_THREAD_TRACE_REG_TYPE_OTHER                   = 0x7,
++} SQ_THREAD_TRACE_REG_TYPE;
++typedef enum SQ_THREAD_TRACE_REG_OP {
++	SQ_THREAD_TRACE_REG_OP_READ                      = 0x0,
++	SQ_THREAD_TRACE_REG_OP_WRITE                     = 0x1,
++} SQ_THREAD_TRACE_REG_OP;
++typedef enum SQ_THREAD_TRACE_MODE_SEL {
++	SQ_THREAD_TRACE_MODE_OFF                         = 0x0,
++	SQ_THREAD_TRACE_MODE_ON                          = 0x1,
++} SQ_THREAD_TRACE_MODE_SEL;
++typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
++	SQ_THREAD_TRACE_CAPTURE_MODE_ALL                 = 0x0,
++	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT              = 0x1,
++	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL       = 0x2,
++} SQ_THREAD_TRACE_CAPTURE_MODE;
++typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
++	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE                = 0x0,
++	SQ_THREAD_TRACE_VM_ID_MASK_ALL                   = 0x1,
++	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL         = 0x2,
++} SQ_THREAD_TRACE_VM_ID_MASK;
++typedef enum SQ_THREAD_TRACE_WAVE_MASK {
++	SQ_THREAD_TRACE_WAVE_MASK_NONE                   = 0x0,
++	SQ_THREAD_TRACE_WAVE_MASK_ALL                    = 0x1,
++} SQ_THREAD_TRACE_WAVE_MASK;
++typedef enum SQ_THREAD_TRACE_ISSUE {
++	SQ_THREAD_TRACE_ISSUE_NULL                       = 0x0,
++	SQ_THREAD_TRACE_ISSUE_STALL                      = 0x1,
++	SQ_THREAD_TRACE_ISSUE_INST                       = 0x2,
++	SQ_THREAD_TRACE_ISSUE_IMMED                      = 0x3,
++} SQ_THREAD_TRACE_ISSUE;
++typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
++	SQ_THREAD_TRACE_ISSUE_MASK_ALL                   = 0x0,
++	SQ_THREAD_TRACE_ISSUE_MASK_STALLED               = 0x1,
++	SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED     = 0x2,
++	SQ_THREAD_TRACE_ISSUE_MASK_IMMED                 = 0x3,
++} SQ_THREAD_TRACE_ISSUE_MASK;
++typedef enum SQ_PERF_SEL {
++	SQ_PERF_SEL_NONE                                 = 0x0,
++	SQ_PERF_SEL_ACCUM_PREV                           = 0x1,
++	SQ_PERF_SEL_CYCLES                               = 0x2,
++	SQ_PERF_SEL_BUSY_CYCLES                          = 0x3,
++	SQ_PERF_SEL_WAVES                                = 0x4,
++	SQ_PERF_SEL_LEVEL_WAVES                          = 0x5,
++	SQ_PERF_SEL_WAVES_EQ_64                          = 0x6,
++	SQ_PERF_SEL_WAVES_LT_64                          = 0x7,
++	SQ_PERF_SEL_WAVES_LT_48                          = 0x8,
++	SQ_PERF_SEL_WAVES_LT_32                          = 0x9,
++	SQ_PERF_SEL_WAVES_LT_16                          = 0xa,
++	SQ_PERF_SEL_WAVES_CU                             = 0xb,
++	SQ_PERF_SEL_LEVEL_WAVES_CU                       = 0xc,
++	SQ_PERF_SEL_BUSY_CU_CYCLES                       = 0xd,
++	SQ_PERF_SEL_ITEMS                                = 0xe,
++	SQ_PERF_SEL_QUADS                                = 0xf,
++	SQ_PERF_SEL_EVENTS                               = 0x10,
++	SQ_PERF_SEL_SURF_SYNCS                           = 0x11,
++	SQ_PERF_SEL_TTRACE_REQS                          = 0x12,
++	SQ_PERF_SEL_TTRACE_INFLIGHT_REQS                 = 0x13,
++	SQ_PERF_SEL_TTRACE_STALL                         = 0x14,
++	SQ_PERF_SEL_MSG_CNTR                             = 0x15,
++	SQ_PERF_SEL_MSG_PERF                             = 0x16,
++	SQ_PERF_SEL_MSG_GSCNT                            = 0x17,
++	SQ_PERF_SEL_MSG_INTERRUPT                        = 0x18,
++	SQ_PERF_SEL_INSTS                                = 0x19,
++	SQ_PERF_SEL_INSTS_VALU                           = 0x1a,
++	SQ_PERF_SEL_INSTS_VMEM_WR                        = 0x1b,
++	SQ_PERF_SEL_INSTS_VMEM_RD                        = 0x1c,
++	SQ_PERF_SEL_INSTS_VMEM                           = 0x1d,
++	SQ_PERF_SEL_INSTS_SALU                           = 0x1e,
++	SQ_PERF_SEL_INSTS_SMEM                           = 0x1f,
++	SQ_PERF_SEL_INSTS_FLAT                           = 0x20,
++	SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY                  = 0x21,
++	SQ_PERF_SEL_INSTS_LDS                            = 0x22,
++	SQ_PERF_SEL_INSTS_GDS                            = 0x23,
++	SQ_PERF_SEL_INSTS_EXP                            = 0x24,
++	SQ_PERF_SEL_INSTS_EXP_GDS                        = 0x25,
++	SQ_PERF_SEL_INSTS_BRANCH                         = 0x26,
++	SQ_PERF_SEL_INSTS_SENDMSG                        = 0x27,
++	SQ_PERF_SEL_INSTS_VSKIPPED                       = 0x28,
++	SQ_PERF_SEL_INST_LEVEL_VMEM                      = 0x29,
++	SQ_PERF_SEL_INST_LEVEL_SMEM                      = 0x2a,
++	SQ_PERF_SEL_INST_LEVEL_LDS                       = 0x2b,
++	SQ_PERF_SEL_INST_LEVEL_GDS                       = 0x2c,
++	SQ_PERF_SEL_INST_LEVEL_EXP                       = 0x2d,
++	SQ_PERF_SEL_WAVE_CYCLES                          = 0x2e,
++	SQ_PERF_SEL_WAVE_READY                           = 0x2f,
++	SQ_PERF_SEL_WAIT_CNT_VM                          = 0x30,
++	SQ_PERF_SEL_WAIT_CNT_LGKM                        = 0x31,
++	SQ_PERF_SEL_WAIT_CNT_EXP                         = 0x32,
++	SQ_PERF_SEL_WAIT_CNT_ANY                         = 0x33,
++	SQ_PERF_SEL_WAIT_BARRIER                         = 0x34,
++	SQ_PERF_SEL_WAIT_EXP_ALLOC                       = 0x35,
++	SQ_PERF_SEL_WAIT_SLEEP                           = 0x36,
++	SQ_PERF_SEL_WAIT_OTHER                           = 0x37,
++	SQ_PERF_SEL_WAIT_ANY                             = 0x38,
++	SQ_PERF_SEL_WAIT_TTRACE                          = 0x39,
++	SQ_PERF_SEL_WAIT_IFETCH                          = 0x3a,
++	SQ_PERF_SEL_WAIT_INST_VMEM                       = 0x3b,
++	SQ_PERF_SEL_WAIT_INST_SCA                        = 0x3c,
++	SQ_PERF_SEL_WAIT_INST_LDS                        = 0x3d,
++	SQ_PERF_SEL_WAIT_INST_VALU                       = 0x3e,
++	SQ_PERF_SEL_WAIT_INST_EXP_GDS                    = 0x3f,
++	SQ_PERF_SEL_WAIT_INST_MISC                       = 0x40,
++	SQ_PERF_SEL_WAIT_INST_FLAT                       = 0x41,
++	SQ_PERF_SEL_ACTIVE_INST_ANY                      = 0x42,
++	SQ_PERF_SEL_ACTIVE_INST_VMEM                     = 0x43,
++	SQ_PERF_SEL_ACTIVE_INST_LDS                      = 0x44,
++	SQ_PERF_SEL_ACTIVE_INST_VALU                     = 0x45,
++	SQ_PERF_SEL_ACTIVE_INST_SCA                      = 0x46,
++	SQ_PERF_SEL_ACTIVE_INST_EXP_GDS                  = 0x47,
++	SQ_PERF_SEL_ACTIVE_INST_MISC                     = 0x48,
++	SQ_PERF_SEL_ACTIVE_INST_FLAT                     = 0x49,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_WR                  = 0x4a,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_RD                  = 0x4b,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR                = 0x4c,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_DATA                = 0x4d,
++	SQ_PERF_SEL_INST_CYCLES_VMEM_CMD                 = 0x4e,
++	SQ_PERF_SEL_INST_CYCLES_VMEM                     = 0x4f,
++	SQ_PERF_SEL_INST_CYCLES_LDS                      = 0x50,
++	SQ_PERF_SEL_INST_CYCLES_VALU                     = 0x51,
++	SQ_PERF_SEL_INST_CYCLES_EXP                      = 0x52,
++	SQ_PERF_SEL_INST_CYCLES_GDS                      = 0x53,
++	SQ_PERF_SEL_INST_CYCLES_SCA                      = 0x54,
++	SQ_PERF_SEL_INST_CYCLES_SMEM                     = 0x55,
++	SQ_PERF_SEL_INST_CYCLES_SALU                     = 0x56,
++	SQ_PERF_SEL_INST_CYCLES_EXP_GDS                  = 0x57,
++	SQ_PERF_SEL_INST_CYCLES_MISC                     = 0x58,
++	SQ_PERF_SEL_THREAD_CYCLES_VALU                   = 0x59,
++	SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX               = 0x5a,
++	SQ_PERF_SEL_IFETCH                               = 0x5b,
++	SQ_PERF_SEL_IFETCH_LEVEL                         = 0x5c,
++	SQ_PERF_SEL_CBRANCH_FORK                         = 0x5d,
++	SQ_PERF_SEL_CBRANCH_FORK_SPLIT                   = 0x5e,
++	SQ_PERF_SEL_VALU_LDS_DIRECT_RD                   = 0x5f,
++	SQ_PERF_SEL_VALU_LDS_INTERP_OP                   = 0x60,
++	SQ_PERF_SEL_LDS_BANK_CONFLICT                    = 0x61,
++	SQ_PERF_SEL_LDS_ADDR_CONFLICT                    = 0x62,
++	SQ_PERF_SEL_LDS_UNALIGNED_STALL                  = 0x63,
++	SQ_PERF_SEL_LDS_MEM_VIOLATIONS                   = 0x64,
++	SQ_PERF_SEL_LDS_ATOMIC_RETURN                    = 0x65,
++	SQ_PERF_SEL_LDS_IDX_ACTIVE                       = 0x66,
++	SQ_PERF_SEL_VALU_DEP_STALL                       = 0x67,
++	SQ_PERF_SEL_VALU_STARVE                          = 0x68,
++	SQ_PERF_SEL_EXP_REQ_FIFO_FULL                    = 0x69,
++	SQ_PERF_SEL_LDS_BACK2BACK_STALL                  = 0x6a,
++	SQ_PERF_SEL_LDS_DATA_FIFO_FULL                   = 0x6b,
++	SQ_PERF_SEL_LDS_CMD_FIFO_FULL                    = 0x6c,
++	SQ_PERF_SEL_VMEM_BACK2BACK_STALL                 = 0x6d,
++	SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL               = 0x6e,
++	SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL                = 0x6f,
++	SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY                = 0x70,
++	SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL              = 0x71,
++	SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL            = 0x72,
++	SQ_PERF_SEL_VALU_SRC_C_CONFLICT                  = 0x73,
++	SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT              = 0x74,
++	SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT              = 0x75,
++	SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT                 = 0x76,
++	SQ_PERF_SEL_LDS_SRC_CD_CONFLICT                  = 0x77,
++	SQ_PERF_SEL_SRC_CD_BUSY                          = 0x78,
++	SQ_PERF_SEL_PT_POWER_STALL                       = 0x79,
++	SQ_PERF_SEL_USER0                                = 0x7a,
++	SQ_PERF_SEL_USER1                                = 0x7b,
++	SQ_PERF_SEL_USER2                                = 0x7c,
++	SQ_PERF_SEL_USER3                                = 0x7d,
++	SQ_PERF_SEL_USER4                                = 0x7e,
++	SQ_PERF_SEL_USER5                                = 0x7f,
++	SQ_PERF_SEL_USER6                                = 0x80,
++	SQ_PERF_SEL_USER7                                = 0x81,
++	SQ_PERF_SEL_USER8                                = 0x82,
++	SQ_PERF_SEL_USER9                                = 0x83,
++	SQ_PERF_SEL_USER10                               = 0x84,
++	SQ_PERF_SEL_USER11                               = 0x85,
++	SQ_PERF_SEL_USER12                               = 0x86,
++	SQ_PERF_SEL_USER13                               = 0x87,
++	SQ_PERF_SEL_USER14                               = 0x88,
++	SQ_PERF_SEL_USER15                               = 0x89,
++	SQ_PERF_SEL_USER_LEVEL0                          = 0x8a,
++	SQ_PERF_SEL_USER_LEVEL1                          = 0x8b,
++	SQ_PERF_SEL_USER_LEVEL2                          = 0x8c,
++	SQ_PERF_SEL_USER_LEVEL3                          = 0x8d,
++	SQ_PERF_SEL_USER_LEVEL4                          = 0x8e,
++	SQ_PERF_SEL_USER_LEVEL5                          = 0x8f,
++	SQ_PERF_SEL_USER_LEVEL6                          = 0x90,
++	SQ_PERF_SEL_USER_LEVEL7                          = 0x91,
++	SQ_PERF_SEL_USER_LEVEL8                          = 0x92,
++	SQ_PERF_SEL_USER_LEVEL9                          = 0x93,
++	SQ_PERF_SEL_USER_LEVEL10                         = 0x94,
++	SQ_PERF_SEL_USER_LEVEL11                         = 0x95,
++	SQ_PERF_SEL_USER_LEVEL12                         = 0x96,
++	SQ_PERF_SEL_USER_LEVEL13                         = 0x97,
++	SQ_PERF_SEL_USER_LEVEL14                         = 0x98,
++	SQ_PERF_SEL_USER_LEVEL15                         = 0x99,
++	SQ_PERF_SEL_POWER_VALU                           = 0x9a,
++	SQ_PERF_SEL_POWER_VALU0                          = 0x9b,
++	SQ_PERF_SEL_POWER_VALU1                          = 0x9c,
++	SQ_PERF_SEL_POWER_VALU2                          = 0x9d,
++	SQ_PERF_SEL_POWER_GPR_RD                         = 0x9e,
++	SQ_PERF_SEL_POWER_GPR_WR                         = 0x9f,
++	SQ_PERF_SEL_POWER_LDS_BUSY                       = 0xa0,
++	SQ_PERF_SEL_POWER_ALU_BUSY                       = 0xa1,
++	SQ_PERF_SEL_POWER_TEX_BUSY                       = 0xa2,
++	SQ_PERF_SEL_ACCUM_PREV_HIRES                     = 0xa3,
++	SQ_PERF_SEL_WAVES_RESTORED                       = 0xa4,
++	SQ_PERF_SEL_WAVES_SAVED                          = 0xa5,
++	SQ_PERF_SEL_DUMMY_LAST                           = 0xa7,
++	SQC_PERF_SEL_ICACHE_INPUT_VALID_READY            = 0xa8,
++	SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB           = 0xa9,
++	SQC_PERF_SEL_ICACHE_INPUT_VALIDB                 = 0xaa,
++	SQC_PERF_SEL_DCACHE_INPUT_VALID_READY            = 0xab,
++	SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB           = 0xac,
++	SQC_PERF_SEL_DCACHE_INPUT_VALIDB                 = 0xad,
++	SQC_PERF_SEL_TC_REQ                              = 0xae,
++	SQC_PERF_SEL_TC_INST_REQ                         = 0xaf,
++	SQC_PERF_SEL_TC_DATA_READ_REQ                    = 0xb0,
++	SQC_PERF_SEL_TC_DATA_WRITE_REQ                   = 0xb1,
++	SQC_PERF_SEL_TC_DATA_ATOMIC_REQ                  = 0xb2,
++	SQC_PERF_SEL_TC_STALL                            = 0xb3,
++	SQC_PERF_SEL_TC_STARVE                           = 0xb4,
++	SQC_PERF_SEL_ICACHE_BUSY_CYCLES                  = 0xb5,
++	SQC_PERF_SEL_ICACHE_REQ                          = 0xb6,
++	SQC_PERF_SEL_ICACHE_HITS                         = 0xb7,
++	SQC_PERF_SEL_ICACHE_MISSES                       = 0xb8,
++	SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE             = 0xb9,
++	SQC_PERF_SEL_ICACHE_INVAL_INST                   = 0xba,
++	SQC_PERF_SEL_ICACHE_INVAL_ASYNC                  = 0xbb,
++	SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT     = 0xbc,
++	SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB      = 0xbd,
++	SQC_PERF_SEL_ICACHE_CACHE_STALLED                = 0xbe,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX     = 0xc0,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT           = 0xc1,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xc3,
++	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xc4,
++	SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xc5,
++	SQC_PERF_SEL_DCACHE_BUSY_CYCLES                  = 0xc6,
++	SQC_PERF_SEL_DCACHE_REQ                          = 0xc7,
++	SQC_PERF_SEL_DCACHE_HITS                         = 0xc8,
++	SQC_PERF_SEL_DCACHE_MISSES                       = 0xc9,
++	SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE             = 0xca,
++	SQC_PERF_SEL_DCACHE_HIT_LRU_READ                 = 0xcb,
++	SQC_PERF_SEL_DCACHE_MISS_EVICT_READ              = 0xcc,
++	SQC_PERF_SEL_DCACHE_WC_LRU_WRITE                 = 0xcd,
++	SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE               = 0xce,
++	SQC_PERF_SEL_DCACHE_ATOMIC                       = 0xcf,
++	SQC_PERF_SEL_DCACHE_VOLATILE                     = 0xd0,
++	SQC_PERF_SEL_DCACHE_INVAL_INST                   = 0xd1,
++	SQC_PERF_SEL_DCACHE_INVAL_ASYNC                  = 0xd2,
++	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST          = 0xd3,
++	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC         = 0xd4,
++	SQC_PERF_SEL_DCACHE_WB_INST                      = 0xd5,
++	SQC_PERF_SEL_DCACHE_WB_ASYNC                     = 0xd6,
++	SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST             = 0xd7,
++	SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC            = 0xd8,
++	SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT     = 0xd9,
++	SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB      = 0xda,
++	SQC_PERF_SEL_DCACHE_CACHE_STALLED                = 0xdb,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX     = 0xdc,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT           = 0xdd,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT            = 0xde,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED        = 0xdf,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT      = 0xe1,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH      = 0xe2,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE       = 0xe3,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xe5,
++	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xe6,
++	SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xe7,
++	SQC_PERF_SEL_DCACHE_REQ_READ_1                   = 0xe8,
++	SQC_PERF_SEL_DCACHE_REQ_READ_2                   = 0xe9,
++	SQC_PERF_SEL_DCACHE_REQ_READ_4                   = 0xea,
++	SQC_PERF_SEL_DCACHE_REQ_READ_8                   = 0xeb,
++	SQC_PERF_SEL_DCACHE_REQ_READ_16                  = 0xec,
++	SQC_PERF_SEL_DCACHE_REQ_TIME                     = 0xed,
++	SQC_PERF_SEL_DCACHE_REQ_WRITE_1                  = 0xee,
++	SQC_PERF_SEL_DCACHE_REQ_WRITE_2                  = 0xef,
++	SQC_PERF_SEL_DCACHE_REQ_WRITE_4                  = 0xf0,
++	SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE                = 0xf1,
++	SQC_PERF_SEL_SQ_DCACHE_REQS                      = 0xf2,
++	SQC_PERF_SEL_DCACHE_FLAT_REQ                     = 0xf3,
++	SQC_PERF_SEL_DCACHE_NONFLAT_REQ                  = 0xf4,
++	SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL               = 0xf5,
++	SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL               = 0xf6,
++	SQC_PERF_SEL_TC_INFLIGHT_LEVEL                   = 0xf7,
++	SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL            = 0xf8,
++	SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL            = 0xf9,
++	SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS      = 0xfa,
++	SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS       = 0xfb,
++	SQC_PERF_SEL_ICACHE_GATCL1_REQUEST               = 0xfc,
++	SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX    = 0xfd,
++	SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT    = 0xfe,
++	SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL            = 0xff,
++	SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES   = 0x100,
++	SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101,
++	SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT        = 0x102,
++	SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL   = 0x103,
++	SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS      = 0x104,
++	SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS       = 0x105,
++	SQC_PERF_SEL_DCACHE_GATCL1_REQUEST               = 0x106,
++	SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX    = 0x107,
++	SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT    = 0x108,
++	SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL            = 0x109,
++	SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES   = 0x10a,
++	SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b,
++	SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT        = 0x10c,
++	SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL   = 0x10d,
++	SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS      = 0x10e,
++	SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL         = 0x10f,
++	SQC_PERF_SEL_DUMMY_LAST                          = 0x110,
++	SQ_PERF_SEL_INSTS_SMEM_NORM                      = 0x111,
++	SQ_PERF_SEL_ATC_INSTS_VMEM                       = 0x112,
++	SQ_PERF_SEL_ATC_INST_LEVEL_VMEM                  = 0x113,
++	SQ_PERF_SEL_ATC_XNACK_FIRST                      = 0x114,
++	SQ_PERF_SEL_ATC_XNACK_ALL                        = 0x115,
++	SQ_PERF_SEL_ATC_XNACK_FIFO_FULL                  = 0x116,
++	SQ_PERF_SEL_ATC_INSTS_SMEM                       = 0x117,
++	SQ_PERF_SEL_ATC_INST_LEVEL_SMEM                  = 0x118,
++	SQ_PERF_SEL_IFETCH_XNACK                         = 0x119,
++	SQ_PERF_SEL_TLB_SHOOTDOWN                        = 0x11a,
++	SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES                 = 0x11b,
++	SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY                 = 0x11c,
++	SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY                 = 0x11d,
++	SQ_PERF_SEL_INSTS_VMEM_REPLAY                    = 0x11e,
++	SQ_PERF_SEL_INSTS_SMEM_REPLAY                    = 0x11f,
++	SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY               = 0x120,
++	SQ_PERF_SEL_INSTS_FLAT_REPLAY                    = 0x121,
++	SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY                = 0x122,
++	SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY                = 0x123,
++	SQ_PERF_SEL_DUMMY_LAST1                          = 0x12a,
++} SQ_PERF_SEL;
++typedef enum SQ_CAC_POWER_SEL {
++	SQ_CAC_POWER_VALU                                = 0x0,
++	SQ_CAC_POWER_VALU0                               = 0x1,
++	SQ_CAC_POWER_VALU1                               = 0x2,
++	SQ_CAC_POWER_VALU2                               = 0x3,
++	SQ_CAC_POWER_GPR_RD                              = 0x4,
++	SQ_CAC_POWER_GPR_WR                              = 0x5,
++	SQ_CAC_POWER_LDS_BUSY                            = 0x6,
++	SQ_CAC_POWER_ALU_BUSY                            = 0x7,
++	SQ_CAC_POWER_TEX_BUSY                            = 0x8,
++} SQ_CAC_POWER_SEL;
++typedef enum SQ_IND_CMD_CMD {
++	SQ_IND_CMD_CMD_NULL                              = 0x0,
++	SQ_IND_CMD_CMD_SETHALT                           = 0x1,
++	SQ_IND_CMD_CMD_SAVECTX                           = 0x2,
++	SQ_IND_CMD_CMD_KILL                              = 0x3,
++	SQ_IND_CMD_CMD_DEBUG                             = 0x4,
++	SQ_IND_CMD_CMD_TRAP                              = 0x5,
++	SQ_IND_CMD_CMD_SET_SPI_PRIO                      = 0x6,
++} SQ_IND_CMD_CMD;
++typedef enum SQ_IND_CMD_MODE {
++	SQ_IND_CMD_MODE_SINGLE                           = 0x0,
++	SQ_IND_CMD_MODE_BROADCAST                        = 0x1,
++	SQ_IND_CMD_MODE_BROADCAST_QUEUE                  = 0x2,
++	SQ_IND_CMD_MODE_BROADCAST_PIPE                   = 0x3,
++	SQ_IND_CMD_MODE_BROADCAST_ME                     = 0x4,
++} SQ_IND_CMD_MODE;
++typedef enum SQ_EDC_INFO_SOURCE {
++	SQ_EDC_INFO_SOURCE_INVALID                       = 0x0,
++	SQ_EDC_INFO_SOURCE_INST                          = 0x1,
++	SQ_EDC_INFO_SOURCE_SGPR                          = 0x2,
++	SQ_EDC_INFO_SOURCE_VGPR                          = 0x3,
++	SQ_EDC_INFO_SOURCE_LDS                           = 0x4,
++	SQ_EDC_INFO_SOURCE_GDS                           = 0x5,
++	SQ_EDC_INFO_SOURCE_TA                            = 0x6,
++} SQ_EDC_INFO_SOURCE;
++typedef enum SQ_ROUND_MODE {
++	SQ_ROUND_NEAREST_EVEN                            = 0x0,
++	SQ_ROUND_PLUS_INFINITY                           = 0x1,
++	SQ_ROUND_MINUS_INFINITY                          = 0x2,
++	SQ_ROUND_TO_ZERO                                 = 0x3,
++} SQ_ROUND_MODE;
++typedef enum SQ_INTERRUPT_WORD_ENCODING {
++	SQ_INTERRUPT_WORD_ENCODING_AUTO                  = 0x0,
++	SQ_INTERRUPT_WORD_ENCODING_INST                  = 0x1,
++	SQ_INTERRUPT_WORD_ENCODING_ERROR                 = 0x2,
++} SQ_INTERRUPT_WORD_ENCODING;
++typedef enum ENUM_SQ_EXPORT_RAT_INST {
++	SQ_EXPORT_RAT_INST_NOP                           = 0x0,
++	SQ_EXPORT_RAT_INST_STORE_TYPED                   = 0x1,
++	SQ_EXPORT_RAT_INST_STORE_RAW                     = 0x2,
++	SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM             = 0x3,
++	SQ_EXPORT_RAT_INST_CMPXCHG_INT                   = 0x4,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FLT                   = 0x5,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM               = 0x6,
++	SQ_EXPORT_RAT_INST_ADD                           = 0x7,
++	SQ_EXPORT_RAT_INST_SUB                           = 0x8,
++	SQ_EXPORT_RAT_INST_RSUB                          = 0x9,
++	SQ_EXPORT_RAT_INST_MIN_INT                       = 0xa,
++	SQ_EXPORT_RAT_INST_MIN_UINT                      = 0xb,
++	SQ_EXPORT_RAT_INST_MAX_INT                       = 0xc,
++	SQ_EXPORT_RAT_INST_MAX_UINT                      = 0xd,
++	SQ_EXPORT_RAT_INST_AND                           = 0xe,
++	SQ_EXPORT_RAT_INST_OR                            = 0xf,
++	SQ_EXPORT_RAT_INST_XOR                           = 0x10,
++	SQ_EXPORT_RAT_INST_MSKOR                         = 0x11,
++	SQ_EXPORT_RAT_INST_INC_UINT                      = 0x12,
++	SQ_EXPORT_RAT_INST_DEC_UINT                      = 0x13,
++	SQ_EXPORT_RAT_INST_STORE_DWORD                   = 0x14,
++	SQ_EXPORT_RAT_INST_STORE_SHORT                   = 0x15,
++	SQ_EXPORT_RAT_INST_STORE_BYTE                    = 0x16,
++	SQ_EXPORT_RAT_INST_NOP_RTN                       = 0x20,
++	SQ_EXPORT_RAT_INST_XCHG_RTN                      = 0x22,
++	SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN              = 0x23,
++	SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN               = 0x24,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN               = 0x25,
++	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN           = 0x26,
++	SQ_EXPORT_RAT_INST_ADD_RTN                       = 0x27,
++	SQ_EXPORT_RAT_INST_SUB_RTN                       = 0x28,
++	SQ_EXPORT_RAT_INST_RSUB_RTN                      = 0x29,
++	SQ_EXPORT_RAT_INST_MIN_INT_RTN                   = 0x2a,
++	SQ_EXPORT_RAT_INST_MIN_UINT_RTN                  = 0x2b,
++	SQ_EXPORT_RAT_INST_MAX_INT_RTN                   = 0x2c,
++	SQ_EXPORT_RAT_INST_MAX_UINT_RTN                  = 0x2d,
++	SQ_EXPORT_RAT_INST_AND_RTN                       = 0x2e,
++	SQ_EXPORT_RAT_INST_OR_RTN                        = 0x2f,
++	SQ_EXPORT_RAT_INST_XOR_RTN                       = 0x30,
++	SQ_EXPORT_RAT_INST_MSKOR_RTN                     = 0x31,
++	SQ_EXPORT_RAT_INST_INC_UINT_RTN                  = 0x32,
++	SQ_EXPORT_RAT_INST_DEC_UINT_RTN                  = 0x33,
++} ENUM_SQ_EXPORT_RAT_INST;
++typedef enum SQ_IBUF_ST {
++	SQ_IBUF_IB_IDLE                                  = 0x0,
++	SQ_IBUF_IB_INI_WAIT_GNT                          = 0x1,
++	SQ_IBUF_IB_INI_WAIT_DRET                         = 0x2,
++	SQ_IBUF_IB_LE_4DW                                = 0x3,
++	SQ_IBUF_IB_WAIT_DRET                             = 0x4,
++	SQ_IBUF_IB_EMPTY_WAIT_DRET                       = 0x5,
++	SQ_IBUF_IB_DRET                                  = 0x6,
++	SQ_IBUF_IB_EMPTY_WAIT_GNT                        = 0x7,
++} SQ_IBUF_ST;
++typedef enum SQ_INST_STR_ST {
++	SQ_INST_STR_IB_WAVE_NORML                        = 0x0,
++	SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV            = 0x1,
++	SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV             = 0x2,
++	SQ_INST_STR_IB_WAVE_INST_SKIP_AV                 = 0x3,
++	SQ_INST_STR_IB_WAVE_SETVSKIP_ST0                 = 0x4,
++	SQ_INST_STR_IB_WAVE_SETVSKIP_ST1                 = 0x5,
++	SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT               = 0x6,
++	SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT        = 0x7,
++} SQ_INST_STR_ST;
++typedef enum SQ_WAVE_IB_ECC_ST {
++	SQ_WAVE_IB_ECC_CLEAN                             = 0x0,
++	SQ_WAVE_IB_ECC_ERR_CONTINUE                      = 0x1,
++	SQ_WAVE_IB_ECC_ERR_HALT                          = 0x2,
++	SQ_WAVE_IB_ECC_WITH_ERR_MSG                      = 0x3,
++} SQ_WAVE_IB_ECC_ST;
++typedef enum SH_MEM_ADDRESS_MODE {
++	SH_MEM_ADDRESS_MODE_GPUVM64                      = 0x0,
++	SH_MEM_ADDRESS_MODE_GPUVM32                      = 0x1,
++	SH_MEM_ADDRESS_MODE_HSA64                        = 0x2,
++	SH_MEM_ADDRESS_MODE_HSA32                        = 0x3,
++} SH_MEM_ADDRESS_MODE;
++typedef enum SH_MEM_ALIGNMENT_MODE {
++	SH_MEM_ALIGNMENT_MODE_DWORD                      = 0x0,
++	SH_MEM_ALIGNMENT_MODE_DWORD_STRICT               = 0x1,
++	SH_MEM_ALIGNMENT_MODE_STRICT                     = 0x2,
++	SH_MEM_ALIGNMENT_MODE_UNALIGNED                  = 0x3,
++} SH_MEM_ALIGNMENT_MODE;
++typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
++	SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC   = 0x18,
++	SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE  = 0x19,
++} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
++#define SQ_WAVE_TYPE_PS0                          0x0
++#define SQIND_GLOBAL_REGS_OFFSET                  0x0
++#define SQIND_GLOBAL_REGS_SIZE                    0x8
++#define SQIND_LOCAL_REGS_OFFSET                   0x8
++#define SQIND_LOCAL_REGS_SIZE                     0x8
++#define SQIND_WAVE_HWREGS_OFFSET                  0x10
++#define SQIND_WAVE_HWREGS_SIZE                    0x1f0
++#define SQIND_WAVE_SGPRS_OFFSET                   0x200
++#define SQIND_WAVE_SGPRS_SIZE                     0x200
++#define SQ_GFXDEC_BEGIN                           0xa000
++#define SQ_GFXDEC_END                             0xc000
++#define SQ_GFXDEC_STATE_ID_SHIFT                  0xa
++#define SQDEC_BEGIN                               0x2300
++#define SQDEC_END                                 0x23ff
++#define SQPERFSDEC_BEGIN                          0xd9c0
++#define SQPERFSDEC_END                            0xda40
++#define SQPERFDDEC_BEGIN                          0xd1c0
++#define SQPERFDDEC_END                            0xd240
++#define SQGFXUDEC_BEGIN                           0xc330
++#define SQGFXUDEC_END                             0xc380
++#define SQPWRDEC_BEGIN                            0xf08c
++#define SQPWRDEC_END                              0xf094
++#define SQ_DISPATCHER_GFX_MIN                     0x10
++#define SQ_DISPATCHER_GFX_CNT_PER_RING            0x8
++#define SQ_MAX_PGM_SGPRS                          0x68
++#define SQ_MAX_PGM_VGPRS                          0x100
++#define SQ_THREAD_TRACE_TIME_UNIT                 0x4
++#define SQ_EX_MODE_EXCP_VALU_BASE                 0x0
++#define SQ_EX_MODE_EXCP_VALU_SIZE                 0x7
++#define SQ_EX_MODE_EXCP_INVALID                   0x0
++#define SQ_EX_MODE_EXCP_INPUT_DENORM              0x1
++#define SQ_EX_MODE_EXCP_DIV0                      0x2
++#define SQ_EX_MODE_EXCP_OVERFLOW                  0x3
++#define SQ_EX_MODE_EXCP_UNDERFLOW                 0x4
++#define SQ_EX_MODE_EXCP_INEXACT                   0x5
++#define SQ_EX_MODE_EXCP_INT_DIV0                  0x6
++#define SQ_EX_MODE_EXCP_ADDR_WATCH                0x7
++#define SQ_EX_MODE_EXCP_MEM_VIOL                  0x8
++#define INST_ID_PRIV_START                        0x80000000
++#define INST_ID_ECC_INTERRUPT_MSG                 0xfffffff0
++#define INST_ID_TTRACE_NEW_PC_MSG                 0xfffffff1
++#define INST_ID_HW_TRAP                           0xfffffff2
++#define INST_ID_KILL_SEQ                          0xfffffff3
++#define INST_ID_SPI_WREXEC                        0xfffffff4
++#define INST_ID_HOST_REG_TRAP_MSG                 0xfffffffe
++#define SQ_ENC_SOP1_BITS                          0xbe800000
++#define SQ_ENC_SOP1_MASK                          0xff800000
++#define SQ_ENC_SOP1_FIELD                         0x17d
++#define SQ_ENC_SOPC_BITS                          0xbf000000
++#define SQ_ENC_SOPC_MASK                          0xff800000
++#define SQ_ENC_SOPC_FIELD                         0x17e
++#define SQ_ENC_SOPP_BITS                          0xbf800000
++#define SQ_ENC_SOPP_MASK                          0xff800000
++#define SQ_ENC_SOPP_FIELD                         0x17f
++#define SQ_ENC_SOPK_BITS                          0xb0000000
++#define SQ_ENC_SOPK_MASK                          0xf0000000
++#define SQ_ENC_SOPK_FIELD                         0xb
++#define SQ_ENC_SOP2_BITS                          0x80000000
++#define SQ_ENC_SOP2_MASK                          0xc0000000
++#define SQ_ENC_SOP2_FIELD                         0x2
++#define SQ_ENC_SMEM_BITS                          0xc0000000
++#define SQ_ENC_SMEM_MASK                          0xfc000000
++#define SQ_ENC_SMEM_FIELD                         0x30
++#define SQ_ENC_VOP1_BITS                          0x7e000000
++#define SQ_ENC_VOP1_MASK                          0xfe000000
++#define SQ_ENC_VOP1_FIELD                         0x3f
++#define SQ_ENC_VOPC_BITS                          0x7c000000
++#define SQ_ENC_VOPC_MASK                          0xfe000000
++#define SQ_ENC_VOPC_FIELD                         0x3e
++#define SQ_ENC_VOP2_BITS                          0x0
++#define SQ_ENC_VOP2_MASK                          0x80000000
++#define SQ_ENC_VOP2_FIELD                         0x0
++#define SQ_ENC_VINTRP_BITS                        0xd4000000
++#define SQ_ENC_VINTRP_MASK                        0xfc000000
++#define SQ_ENC_VINTRP_FIELD                       0x35
++#define SQ_ENC_VOP3_BITS                          0xd0000000
++#define SQ_ENC_VOP3_MASK                          0xfc000000
++#define SQ_ENC_VOP3_FIELD                         0x34
++#define SQ_ENC_DS_BITS                            0xd8000000
++#define SQ_ENC_DS_MASK                            0xfc000000
++#define SQ_ENC_DS_FIELD                           0x36
++#define SQ_ENC_MUBUF_BITS                         0xe0000000
++#define SQ_ENC_MUBUF_MASK                         0xfc000000
++#define SQ_ENC_MUBUF_FIELD                        0x38
++#define SQ_ENC_MTBUF_BITS                         0xe8000000
++#define SQ_ENC_MTBUF_MASK                         0xfc000000
++#define SQ_ENC_MTBUF_FIELD                        0x3a
++#define SQ_ENC_MIMG_BITS                          0xf0000000
++#define SQ_ENC_MIMG_MASK                          0xfc000000
++#define SQ_ENC_MIMG_FIELD                         0x3c
++#define SQ_ENC_EXP_BITS                           0xc4000000
++#define SQ_ENC_EXP_MASK                           0xfc000000
++#define SQ_ENC_EXP_FIELD                          0x31
++#define SQ_ENC_FLAT_BITS                          0xdc000000
++#define SQ_ENC_FLAT_MASK                          0xfc000000
++#define SQ_ENC_FLAT_FIELD                         0x37
++#define SQ_V_OP3_INTRP_OFFSET                     0x274
++#define SQ_WAITCNT_VM_SHIFT                       0x0
++#define SQ_SENDMSG_STREAMID_SIZE                  0x2
++#define SQ_V_OPC_COUNT                            0x100
++#define SQ_V_OP3_INTRP_COUNT                      0xc
++#define SQ_XLATE_VOP3_TO_VOP2_OFFSET              0x100
++#define SQ_HWREG_OFFSET_SIZE                      0x5
++#define SQ_HWREG_OFFSET_SHIFT                     0x6
++#define SQ_V_OP3_3IN_OFFSET                       0x1c0
++#define SQ_NUM_ATTR                               0x21
++#define SQ_NUM_VGPR                               0x100
++#define SQ_XLATE_VOP3_TO_VINTRP_COUNT             0x4
++#define SQ_SENDMSG_MSG_SIZE                       0x4
++#define SQ_NUM_TTMP                               0xc
++#define SQ_HWREG_ID_SIZE                          0x6
++#define SQ_SENDMSG_GSOP_SIZE                      0x2
++#define SQ_NUM_SGPR                               0x66
++#define SQ_EXP_NUM_MRT                            0x8
++#define SQ_SENDMSG_SYSTEM_SIZE                    0x3
++#define SQ_WAITCNT_LGKM_SHIFT                     0x8
++#define SQ_XLATE_VOP3_TO_VOP2_COUNT               0x40
++#define SQ_V_OP3_3IN_COUNT                        0xb0
++#define SQ_V_INTRP_COUNT                          0x4
++#define SQ_WAITCNT_EXP_SIZE                       0x3
++#define SQ_SENDMSG_SYSTEM_SHIFT                   0x4
++#define SQ_EXP_NUM_GDS                            0x5
++#define SQ_HWREG_SIZE_SHIFT                       0xb
++#define SQ_XLATE_VOP3_TO_VOPC_OFFSET              0x0
++#define SQ_V_OP3_2IN_COUNT                        0x80
++#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET            0x270
++#define SQ_SENDMSG_MSG_SHIFT                      0x0
++#define SQ_WAITCNT_EXP_SHIFT                      0x4
++#define SQ_WAITCNT_VM_SIZE                        0x4
++#define SQ_XLATE_VOP3_TO_VOP1_OFFSET              0x140
++#define SQ_SENDMSG_GSOP_SHIFT                     0x4
++#define SQ_XLATE_VOP3_TO_VOP1_COUNT               0x80
++#define SQ_SRC_VGPR_BIT                           0x100
++#define SQ_V_OP2_COUNT                            0x40
++#define SQ_EXP_NUM_PARAM                          0x20
++#define SQ_V_OP1_COUNT                            0x80
++#define SQ_SENDMSG_STREAMID_SHIFT                 0x8
++#define SQ_V_OP3_2IN_OFFSET                       0x280
++#define SQ_WAITCNT_LGKM_SIZE                      0x4
++#define SQ_XLATE_VOP3_TO_VOPC_COUNT               0x100
++#define SQ_EXP_NUM_POS                            0x4
++#define SQ_HWREG_SIZE_SIZE                        0x5
++#define SQ_HWREG_ID_SHIFT                         0x0
++#define SQ_S_MOV_B32                              0x0
++#define SQ_S_MOV_B64                              0x1
++#define SQ_S_CMOV_B32                             0x2
++#define SQ_S_CMOV_B64                             0x3
++#define SQ_S_NOT_B32                              0x4
++#define SQ_S_NOT_B64                              0x5
++#define SQ_S_WQM_B32                              0x6
++#define SQ_S_WQM_B64                              0x7
++#define SQ_S_BREV_B32                             0x8
++#define SQ_S_BREV_B64                             0x9
++#define SQ_S_BCNT0_I32_B32                        0xa
++#define SQ_S_BCNT0_I32_B64                        0xb
++#define SQ_S_BCNT1_I32_B32                        0xc
++#define SQ_S_BCNT1_I32_B64                        0xd
++#define SQ_S_FF0_I32_B32                          0xe
++#define SQ_S_FF0_I32_B64                          0xf
++#define SQ_S_FF1_I32_B32                          0x10
++#define SQ_S_FF1_I32_B64                          0x11
++#define SQ_S_FLBIT_I32_B32                        0x12
++#define SQ_S_FLBIT_I32_B64                        0x13
++#define SQ_S_FLBIT_I32                            0x14
++#define SQ_S_FLBIT_I32_I64                        0x15
++#define SQ_S_SEXT_I32_I8                          0x16
++#define SQ_S_SEXT_I32_I16                         0x17
++#define SQ_S_BITSET0_B32                          0x18
++#define SQ_S_BITSET0_B64                          0x19
++#define SQ_S_BITSET1_B32                          0x1a
++#define SQ_S_BITSET1_B64                          0x1b
++#define SQ_S_GETPC_B64                            0x1c
++#define SQ_S_SETPC_B64                            0x1d
++#define SQ_S_SWAPPC_B64                           0x1e
++#define SQ_S_RFE_B64                              0x1f
++#define SQ_S_AND_SAVEEXEC_B64                     0x20
++#define SQ_S_OR_SAVEEXEC_B64                      0x21
++#define SQ_S_XOR_SAVEEXEC_B64                     0x22
++#define SQ_S_ANDN2_SAVEEXEC_B64                   0x23
++#define SQ_S_ORN2_SAVEEXEC_B64                    0x24
++#define SQ_S_NAND_SAVEEXEC_B64                    0x25
++#define SQ_S_NOR_SAVEEXEC_B64                     0x26
++#define SQ_S_XNOR_SAVEEXEC_B64                    0x27
++#define SQ_S_QUADMASK_B32                         0x28
++#define SQ_S_QUADMASK_B64                         0x29
++#define SQ_S_MOVRELS_B32                          0x2a
++#define SQ_S_MOVRELS_B64                          0x2b
++#define SQ_S_MOVRELD_B32                          0x2c
++#define SQ_S_MOVRELD_B64                          0x2d
++#define SQ_S_CBRANCH_JOIN                         0x2e
++#define SQ_S_MOV_REGRD_B32                        0x2f
++#define SQ_S_ABS_I32                              0x30
++#define SQ_S_MOV_FED_B32                          0x31
++#define SQ_S_SET_GPR_IDX_IDX                      0x32
++#define SQ_ATTR0                                  0x0
++#define SQ_S_MOVK_I32                             0x0
++#define SQ_S_CMOVK_I32                            0x1
++#define SQ_S_CMPK_EQ_I32                          0x2
++#define SQ_S_CMPK_LG_I32                          0x3
++#define SQ_S_CMPK_GT_I32                          0x4
++#define SQ_S_CMPK_GE_I32                          0x5
++#define SQ_S_CMPK_LT_I32                          0x6
++#define SQ_S_CMPK_LE_I32                          0x7
++#define SQ_S_CMPK_EQ_U32                          0x8
++#define SQ_S_CMPK_LG_U32                          0x9
++#define SQ_S_CMPK_GT_U32                          0xa
++#define SQ_S_CMPK_GE_U32                          0xb
++#define SQ_S_CMPK_LT_U32                          0xc
++#define SQ_S_CMPK_LE_U32                          0xd
++#define SQ_S_ADDK_I32                             0xe
++#define SQ_S_MULK_I32                             0xf
++#define SQ_S_CBRANCH_I_FORK                       0x10
++#define SQ_S_GETREG_B32                           0x11
++#define SQ_S_SETREG_B32                           0x12
++#define SQ_S_GETREG_REGRD_B32                     0x13
++#define SQ_S_SETREG_IMM32_B32                     0x14
++#define SQ_TBA_LO                                 0x6c
++#define SQ_TBA_HI                                 0x6d
++#define SQ_TMA_LO                                 0x6e
++#define SQ_TMA_HI                                 0x6f
++#define SQ_TTMP0                                  0x70
++#define SQ_TTMP1                                  0x71
++#define SQ_TTMP2                                  0x72
++#define SQ_TTMP3                                  0x73
++#define SQ_TTMP4                                  0x74
++#define SQ_TTMP5                                  0x75
++#define SQ_TTMP6                                  0x76
++#define SQ_TTMP7                                  0x77
++#define SQ_TTMP8                                  0x78
++#define SQ_TTMP9                                  0x79
++#define SQ_TTMP10                                 0x7a
++#define SQ_TTMP11                                 0x7b
++#define SQ_VGPR0                                  0x0
++#define SQ_EXP                                    0x0
++#define SQ_EXP_MRT0                               0x0
++#define SQ_EXP_MRTZ                               0x8
++#define SQ_EXP_NULL                               0x9
++#define SQ_EXP_POS0                               0xc
++#define SQ_EXP_PARAM0                             0x20
++#define SQ_CNT1                                   0x0
++#define SQ_CNT2                                   0x1
++#define SQ_CNT3                                   0x2
++#define SQ_CNT4                                   0x3
++#define SQ_S_LOAD_DWORD                           0x0
++#define SQ_S_LOAD_DWORDX2                         0x1
++#define SQ_S_LOAD_DWORDX4                         0x2
++#define SQ_S_LOAD_DWORDX8                         0x3
++#define SQ_S_LOAD_DWORDX16                        0x4
++#define SQ_S_BUFFER_LOAD_DWORD                    0x8
++#define SQ_S_BUFFER_LOAD_DWORDX2                  0x9
++#define SQ_S_BUFFER_LOAD_DWORDX4                  0xa
++#define SQ_S_BUFFER_LOAD_DWORDX8                  0xb
++#define SQ_S_BUFFER_LOAD_DWORDX16                 0xc
++#define SQ_S_STORE_DWORD                          0x10
++#define SQ_S_STORE_DWORDX2                        0x11
++#define SQ_S_STORE_DWORDX4                        0x12
++#define SQ_S_BUFFER_STORE_DWORD                   0x18
++#define SQ_S_BUFFER_STORE_DWORDX2                 0x19
++#define SQ_S_BUFFER_STORE_DWORDX4                 0x1a
++#define SQ_S_DCACHE_INV                           0x20
++#define SQ_S_DCACHE_WB                            0x21
++#define SQ_S_DCACHE_INV_VOL                       0x22
++#define SQ_S_DCACHE_WB_VOL                        0x23
++#define SQ_S_MEMTIME                              0x24
++#define SQ_S_MEMREALTIME                          0x25
++#define SQ_S_ATC_PROBE                            0x26
++#define SQ_S_ATC_PROBE_BUFFER                     0x27
++#define SQ_S_BUFFER_ATOMIC_SWAP                   0x40
++#define SQ_S_BUFFER_ATOMIC_CMPSWAP                0x41
++#define SQ_S_BUFFER_ATOMIC_ADD                    0x42
++#define SQ_S_BUFFER_ATOMIC_SUB                    0x43
++#define SQ_S_BUFFER_ATOMIC_SMIN                   0x44
++#define SQ_S_BUFFER_ATOMIC_UMIN                   0x45
++#define SQ_S_BUFFER_ATOMIC_SMAX                   0x46
++#define SQ_S_BUFFER_ATOMIC_UMAX                   0x47
++#define SQ_S_BUFFER_ATOMIC_AND                    0x48
++#define SQ_S_BUFFER_ATOMIC_OR                     0x49
++#define SQ_S_BUFFER_ATOMIC_XOR                    0x4a
++#define SQ_S_BUFFER_ATOMIC_INC                    0x4b
++#define SQ_S_BUFFER_ATOMIC_DEC                    0x4c
++#define SQ_S_BUFFER_ATOMIC_SWAP_X2                0x60
++#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2             0x61
++#define SQ_S_BUFFER_ATOMIC_ADD_X2                 0x62
++#define SQ_S_BUFFER_ATOMIC_SUB_X2                 0x63
++#define SQ_S_BUFFER_ATOMIC_SMIN_X2                0x64
++#define SQ_S_BUFFER_ATOMIC_UMIN_X2                0x65
++#define SQ_S_BUFFER_ATOMIC_SMAX_X2                0x66
++#define SQ_S_BUFFER_ATOMIC_UMAX_X2                0x67
++#define SQ_S_BUFFER_ATOMIC_AND_X2                 0x68
++#define SQ_S_BUFFER_ATOMIC_OR_X2                  0x69
++#define SQ_S_BUFFER_ATOMIC_XOR_X2                 0x6a
++#define SQ_S_BUFFER_ATOMIC_INC_X2                 0x6b
++#define SQ_S_BUFFER_ATOMIC_DEC_X2                 0x6c
++#define SQ_F                                      0x0
++#define SQ_LT                                     0x1
++#define SQ_EQ                                     0x2
++#define SQ_LE                                     0x3
++#define SQ_GT                                     0x4
++#define SQ_LG                                     0x5
++#define SQ_GE                                     0x6
++#define SQ_O                                      0x7
++#define SQ_U                                      0x8
++#define SQ_NGE                                    0x9
++#define SQ_NLG                                    0xa
++#define SQ_NGT                                    0xb
++#define SQ_NLE                                    0xc
++#define SQ_NEQ                                    0xd
++#define SQ_NLT                                    0xe
++#define SQ_TRU                                    0xf
++#define SQ_V_CMP_CLASS_F32                        0x10
++#define SQ_V_CMPX_CLASS_F32                       0x11
++#define SQ_V_CMP_CLASS_F64                        0x12
++#define SQ_V_CMPX_CLASS_F64                       0x13
++#define SQ_V_CMP_CLASS_F16                        0x14
++#define SQ_V_CMPX_CLASS_F16                       0x15
++#define SQ_V_CMP_F_F16                            0x20
++#define SQ_V_CMP_LT_F16                           0x21
++#define SQ_V_CMP_EQ_F16                           0x22
++#define SQ_V_CMP_LE_F16                           0x23
++#define SQ_V_CMP_GT_F16                           0x24
++#define SQ_V_CMP_LG_F16                           0x25
++#define SQ_V_CMP_GE_F16                           0x26
++#define SQ_V_CMP_O_F16                            0x27
++#define SQ_V_CMP_U_F16                            0x28
++#define SQ_V_CMP_NGE_F16                          0x29
++#define SQ_V_CMP_NLG_F16                          0x2a
++#define SQ_V_CMP_NGT_F16                          0x2b
++#define SQ_V_CMP_NLE_F16                          0x2c
++#define SQ_V_CMP_NEQ_F16                          0x2d
++#define SQ_V_CMP_NLT_F16                          0x2e
++#define SQ_V_CMP_TRU_F16                          0x2f
++#define SQ_V_CMPX_F_F16                           0x30
++#define SQ_V_CMPX_LT_F16                          0x31
++#define SQ_V_CMPX_EQ_F16                          0x32
++#define SQ_V_CMPX_LE_F16                          0x33
++#define SQ_V_CMPX_GT_F16                          0x34
++#define SQ_V_CMPX_LG_F16                          0x35
++#define SQ_V_CMPX_GE_F16                          0x36
++#define SQ_V_CMPX_O_F16                           0x37
++#define SQ_V_CMPX_U_F16                           0x38
++#define SQ_V_CMPX_NGE_F16                         0x39
++#define SQ_V_CMPX_NLG_F16                         0x3a
++#define SQ_V_CMPX_NGT_F16                         0x3b
++#define SQ_V_CMPX_NLE_F16                         0x3c
++#define SQ_V_CMPX_NEQ_F16                         0x3d
++#define SQ_V_CMPX_NLT_F16                         0x3e
++#define SQ_V_CMPX_TRU_F16                         0x3f
++#define SQ_V_CMP_F_F32                            0x40
++#define SQ_V_CMP_LT_F32                           0x41
++#define SQ_V_CMP_EQ_F32                           0x42
++#define SQ_V_CMP_LE_F32                           0x43
++#define SQ_V_CMP_GT_F32                           0x44
++#define SQ_V_CMP_LG_F32                           0x45
++#define SQ_V_CMP_GE_F32                           0x46
++#define SQ_V_CMP_O_F32                            0x47
++#define SQ_V_CMP_U_F32                            0x48
++#define SQ_V_CMP_NGE_F32                          0x49
++#define SQ_V_CMP_NLG_F32                          0x4a
++#define SQ_V_CMP_NGT_F32                          0x4b
++#define SQ_V_CMP_NLE_F32                          0x4c
++#define SQ_V_CMP_NEQ_F32                          0x4d
++#define SQ_V_CMP_NLT_F32                          0x4e
++#define SQ_V_CMP_TRU_F32                          0x4f
++#define SQ_V_CMPX_F_F32                           0x50
++#define SQ_V_CMPX_LT_F32                          0x51
++#define SQ_V_CMPX_EQ_F32                          0x52
++#define SQ_V_CMPX_LE_F32                          0x53
++#define SQ_V_CMPX_GT_F32                          0x54
++#define SQ_V_CMPX_LG_F32                          0x55
++#define SQ_V_CMPX_GE_F32                          0x56
++#define SQ_V_CMPX_O_F32                           0x57
++#define SQ_V_CMPX_U_F32                           0x58
++#define SQ_V_CMPX_NGE_F32                         0x59
++#define SQ_V_CMPX_NLG_F32                         0x5a
++#define SQ_V_CMPX_NGT_F32                         0x5b
++#define SQ_V_CMPX_NLE_F32                         0x5c
++#define SQ_V_CMPX_NEQ_F32                         0x5d
++#define SQ_V_CMPX_NLT_F32                         0x5e
++#define SQ_V_CMPX_TRU_F32                         0x5f
++#define SQ_V_CMP_F_F64                            0x60
++#define SQ_V_CMP_LT_F64                           0x61
++#define SQ_V_CMP_EQ_F64                           0x62
++#define SQ_V_CMP_LE_F64                           0x63
++#define SQ_V_CMP_GT_F64                           0x64
++#define SQ_V_CMP_LG_F64                           0x65
++#define SQ_V_CMP_GE_F64                           0x66
++#define SQ_V_CMP_O_F64                            0x67
++#define SQ_V_CMP_U_F64                            0x68
++#define SQ_V_CMP_NGE_F64                          0x69
++#define SQ_V_CMP_NLG_F64                          0x6a
++#define SQ_V_CMP_NGT_F64                          0x6b
++#define SQ_V_CMP_NLE_F64                          0x6c
++#define SQ_V_CMP_NEQ_F64                          0x6d
++#define SQ_V_CMP_NLT_F64                          0x6e
++#define SQ_V_CMP_TRU_F64                          0x6f
++#define SQ_V_CMPX_F_F64                           0x70
++#define SQ_V_CMPX_LT_F64                          0x71
++#define SQ_V_CMPX_EQ_F64                          0x72
++#define SQ_V_CMPX_LE_F64                          0x73
++#define SQ_V_CMPX_GT_F64                          0x74
++#define SQ_V_CMPX_LG_F64                          0x75
++#define SQ_V_CMPX_GE_F64                          0x76
++#define SQ_V_CMPX_O_F64                           0x77
++#define SQ_V_CMPX_U_F64                           0x78
++#define SQ_V_CMPX_NGE_F64                         0x79
++#define SQ_V_CMPX_NLG_F64                         0x7a
++#define SQ_V_CMPX_NGT_F64                         0x7b
++#define SQ_V_CMPX_NLE_F64                         0x7c
++#define SQ_V_CMPX_NEQ_F64                         0x7d
++#define SQ_V_CMPX_NLT_F64                         0x7e
++#define SQ_V_CMPX_TRU_F64                         0x7f
++#define SQ_V_CMP_F_I16                            0xa0
++#define SQ_V_CMP_LT_I16                           0xa1
++#define SQ_V_CMP_EQ_I16                           0xa2
++#define SQ_V_CMP_LE_I16                           0xa3
++#define SQ_V_CMP_GT_I16                           0xa4
++#define SQ_V_CMP_NE_I16                           0xa5
++#define SQ_V_CMP_GE_I16                           0xa6
++#define SQ_V_CMP_T_I16                            0xa7
++#define SQ_V_CMP_F_U16                            0xa8
++#define SQ_V_CMP_LT_U16                           0xa9
++#define SQ_V_CMP_EQ_U16                           0xaa
++#define SQ_V_CMP_LE_U16                           0xab
++#define SQ_V_CMP_GT_U16                           0xac
++#define SQ_V_CMP_NE_U16                           0xad
++#define SQ_V_CMP_GE_U16                           0xae
++#define SQ_V_CMP_T_U16                            0xaf
++#define SQ_V_CMPX_F_I16                           0xb0
++#define SQ_V_CMPX_LT_I16                          0xb1
++#define SQ_V_CMPX_EQ_I16                          0xb2
++#define SQ_V_CMPX_LE_I16                          0xb3
++#define SQ_V_CMPX_GT_I16                          0xb4
++#define SQ_V_CMPX_NE_I16                          0xb5
++#define SQ_V_CMPX_GE_I16                          0xb6
++#define SQ_V_CMPX_T_I16                           0xb7
++#define SQ_V_CMPX_F_U16                           0xb8
++#define SQ_V_CMPX_LT_U16                          0xb9
++#define SQ_V_CMPX_EQ_U16                          0xba
++#define SQ_V_CMPX_LE_U16                          0xbb
++#define SQ_V_CMPX_GT_U16                          0xbc
++#define SQ_V_CMPX_NE_U16                          0xbd
++#define SQ_V_CMPX_GE_U16                          0xbe
++#define SQ_V_CMPX_T_U16                           0xbf
++#define SQ_V_CMP_F_I32                            0xc0
++#define SQ_V_CMP_LT_I32                           0xc1
++#define SQ_V_CMP_EQ_I32                           0xc2
++#define SQ_V_CMP_LE_I32                           0xc3
++#define SQ_V_CMP_GT_I32                           0xc4
++#define SQ_V_CMP_NE_I32                           0xc5
++#define SQ_V_CMP_GE_I32                           0xc6
++#define SQ_V_CMP_T_I32                            0xc7
++#define SQ_V_CMP_F_U32                            0xc8
++#define SQ_V_CMP_LT_U32                           0xc9
++#define SQ_V_CMP_EQ_U32                           0xca
++#define SQ_V_CMP_LE_U32                           0xcb
++#define SQ_V_CMP_GT_U32                           0xcc
++#define SQ_V_CMP_NE_U32                           0xcd
++#define SQ_V_CMP_GE_U32                           0xce
++#define SQ_V_CMP_T_U32                            0xcf
++#define SQ_V_CMPX_F_I32                           0xd0
++#define SQ_V_CMPX_LT_I32                          0xd1
++#define SQ_V_CMPX_EQ_I32                          0xd2
++#define SQ_V_CMPX_LE_I32                          0xd3
++#define SQ_V_CMPX_GT_I32                          0xd4
++#define SQ_V_CMPX_NE_I32                          0xd5
++#define SQ_V_CMPX_GE_I32                          0xd6
++#define SQ_V_CMPX_T_I32                           0xd7
++#define SQ_V_CMPX_F_U32                           0xd8
++#define SQ_V_CMPX_LT_U32                          0xd9
++#define SQ_V_CMPX_EQ_U32                          0xda
++#define SQ_V_CMPX_LE_U32                          0xdb
++#define SQ_V_CMPX_GT_U32                          0xdc
++#define SQ_V_CMPX_NE_U32                          0xdd
++#define SQ_V_CMPX_GE_U32                          0xde
++#define SQ_V_CMPX_T_U32                           0xdf
++#define SQ_V_CMP_F_I64                            0xe0
++#define SQ_V_CMP_LT_I64                           0xe1
++#define SQ_V_CMP_EQ_I64                           0xe2
++#define SQ_V_CMP_LE_I64                           0xe3
++#define SQ_V_CMP_GT_I64                           0xe4
++#define SQ_V_CMP_NE_I64                           0xe5
++#define SQ_V_CMP_GE_I64                           0xe6
++#define SQ_V_CMP_T_I64                            0xe7
++#define SQ_V_CMP_F_U64                            0xe8
++#define SQ_V_CMP_LT_U64                           0xe9
++#define SQ_V_CMP_EQ_U64                           0xea
++#define SQ_V_CMP_LE_U64                           0xeb
++#define SQ_V_CMP_GT_U64                           0xec
++#define SQ_V_CMP_NE_U64                           0xed
++#define SQ_V_CMP_GE_U64                           0xee
++#define SQ_V_CMP_T_U64                            0xef
++#define SQ_V_CMPX_F_I64                           0xf0
++#define SQ_V_CMPX_LT_I64                          0xf1
++#define SQ_V_CMPX_EQ_I64                          0xf2
++#define SQ_V_CMPX_LE_I64                          0xf3
++#define SQ_V_CMPX_GT_I64                          0xf4
++#define SQ_V_CMPX_NE_I64                          0xf5
++#define SQ_V_CMPX_GE_I64                          0xf6
++#define SQ_V_CMPX_T_I64                           0xf7
++#define SQ_V_CMPX_F_U64                           0xf8
++#define SQ_V_CMPX_LT_U64                          0xf9
++#define SQ_V_CMPX_EQ_U64                          0xfa
++#define SQ_V_CMPX_LE_U64                          0xfb
++#define SQ_V_CMPX_GT_U64                          0xfc
++#define SQ_V_CMPX_NE_U64                          0xfd
++#define SQ_V_CMPX_GE_U64                          0xfe
++#define SQ_V_CMPX_T_U64                           0xff
++#define SQ_L1                                     0x1
++#define SQ_L2                                     0x2
++#define SQ_L3                                     0x3
++#define SQ_L4                                     0x4
++#define SQ_L5                                     0x5
++#define SQ_L6                                     0x6
++#define SQ_L7                                     0x7
++#define SQ_L8                                     0x8
++#define SQ_L9                                     0x9
++#define SQ_L10                                    0xa
++#define SQ_L11                                    0xb
++#define SQ_L12                                    0xc
++#define SQ_L13                                    0xd
++#define SQ_L14                                    0xe
++#define SQ_L15                                    0xf
++#define SQ_SGPR0                                  0x0
++#define SQ_SDWA_UNUSED_PAD                        0x0
++#define SQ_SDWA_UNUSED_SEXT                       0x1
++#define SQ_SDWA_UNUSED_PRESERVE                   0x2
++#define SQ_F                                      0x0
++#define SQ_LT                                     0x1
++#define SQ_EQ                                     0x2
++#define SQ_LE                                     0x3
++#define SQ_GT                                     0x4
++#define SQ_NE                                     0x5
++#define SQ_GE                                     0x6
++#define SQ_T                                      0x7
++#define SQ_SRC_64_INT                             0xc0
++#define SQ_SRC_M_1_INT                            0xc1
++#define SQ_SRC_M_2_INT                            0xc2
++#define SQ_SRC_M_3_INT                            0xc3
++#define SQ_SRC_M_4_INT                            0xc4
++#define SQ_SRC_M_5_INT                            0xc5
++#define SQ_SRC_M_6_INT                            0xc6
++#define SQ_SRC_M_7_INT                            0xc7
++#define SQ_SRC_M_8_INT                            0xc8
++#define SQ_SRC_M_9_INT                            0xc9
++#define SQ_SRC_M_10_INT                           0xca
++#define SQ_SRC_M_11_INT                           0xcb
++#define SQ_SRC_M_12_INT                           0xcc
++#define SQ_SRC_M_13_INT                           0xcd
++#define SQ_SRC_M_14_INT                           0xce
++#define SQ_SRC_M_15_INT                           0xcf
++#define SQ_SRC_M_16_INT                           0xd0
++#define SQ_SRC_0_5                                0xf0
++#define SQ_SRC_M_0_5                              0xf1
++#define SQ_SRC_1                                  0xf2
++#define SQ_SRC_M_1                                0xf3
++#define SQ_SRC_2                                  0xf4
++#define SQ_SRC_M_2                                0xf5
++#define SQ_SRC_4                                  0xf6
++#define SQ_SRC_M_4                                0xf7
++#define SQ_SRC_INV_2PI                            0xf8
++#define SQ_SRC_0                                  0x80
++#define SQ_SRC_1_INT                              0x81
++#define SQ_SRC_2_INT                              0x82
++#define SQ_SRC_3_INT                              0x83
++#define SQ_SRC_4_INT                              0x84
++#define SQ_SRC_5_INT                              0x85
++#define SQ_SRC_6_INT                              0x86
++#define SQ_SRC_7_INT                              0x87
++#define SQ_SRC_8_INT                              0x88
++#define SQ_SRC_9_INT                              0x89
++#define SQ_SRC_10_INT                             0x8a
++#define SQ_SRC_11_INT                             0x8b
++#define SQ_SRC_12_INT                             0x8c
++#define SQ_SRC_13_INT                             0x8d
++#define SQ_SRC_14_INT                             0x8e
++#define SQ_SRC_15_INT                             0x8f
++#define SQ_SRC_16_INT                             0x90
++#define SQ_SRC_17_INT                             0x91
++#define SQ_SRC_18_INT                             0x92
++#define SQ_SRC_19_INT                             0x93
++#define SQ_SRC_20_INT                             0x94
++#define SQ_SRC_21_INT                             0x95
++#define SQ_SRC_22_INT                             0x96
++#define SQ_SRC_23_INT                             0x97
++#define SQ_SRC_24_INT                             0x98
++#define SQ_SRC_25_INT                             0x99
++#define SQ_SRC_26_INT                             0x9a
++#define SQ_SRC_27_INT                             0x9b
++#define SQ_SRC_28_INT                             0x9c
++#define SQ_SRC_29_INT                             0x9d
++#define SQ_SRC_30_INT                             0x9e
++#define SQ_SRC_31_INT                             0x9f
++#define SQ_SRC_32_INT                             0xa0
++#define SQ_SRC_33_INT                             0xa1
++#define SQ_SRC_34_INT                             0xa2
++#define SQ_SRC_35_INT                             0xa3
++#define SQ_SRC_36_INT                             0xa4
++#define SQ_SRC_37_INT                             0xa5
++#define SQ_SRC_38_INT                             0xa6
++#define SQ_SRC_39_INT                             0xa7
++#define SQ_SRC_40_INT                             0xa8
++#define SQ_SRC_41_INT                             0xa9
++#define SQ_SRC_42_INT                             0xaa
++#define SQ_SRC_43_INT                             0xab
++#define SQ_SRC_44_INT                             0xac
++#define SQ_SRC_45_INT                             0xad
++#define SQ_SRC_46_INT                             0xae
++#define SQ_SRC_47_INT                             0xaf
++#define SQ_SRC_48_INT                             0xb0
++#define SQ_SRC_49_INT                             0xb1
++#define SQ_SRC_50_INT                             0xb2
++#define SQ_SRC_51_INT                             0xb3
++#define SQ_SRC_52_INT                             0xb4
++#define SQ_SRC_53_INT                             0xb5
++#define SQ_SRC_54_INT                             0xb6
++#define SQ_SRC_55_INT                             0xb7
++#define SQ_SRC_56_INT                             0xb8
++#define SQ_SRC_57_INT                             0xb9
++#define SQ_SRC_58_INT                             0xba
++#define SQ_SRC_59_INT                             0xbb
++#define SQ_SRC_60_INT                             0xbc
++#define SQ_SRC_61_INT                             0xbd
++#define SQ_SRC_62_INT                             0xbe
++#define SQ_SRC_63_INT                             0xbf
++#define SQ_DS_ADD_U32                             0x0
++#define SQ_DS_SUB_U32                             0x1
++#define SQ_DS_RSUB_U32                            0x2
++#define SQ_DS_INC_U32                             0x3
++#define SQ_DS_DEC_U32                             0x4
++#define SQ_DS_MIN_I32                             0x5
++#define SQ_DS_MAX_I32                             0x6
++#define SQ_DS_MIN_U32                             0x7
++#define SQ_DS_MAX_U32                             0x8
++#define SQ_DS_AND_B32                             0x9
++#define SQ_DS_OR_B32                              0xa
++#define SQ_DS_XOR_B32                             0xb
++#define SQ_DS_MSKOR_B32                           0xc
++#define SQ_DS_WRITE_B32                           0xd
++#define SQ_DS_WRITE2_B32                          0xe
++#define SQ_DS_WRITE2ST64_B32                      0xf
++#define SQ_DS_CMPST_B32                           0x10
++#define SQ_DS_CMPST_F32                           0x11
++#define SQ_DS_MIN_F32                             0x12
++#define SQ_DS_MAX_F32                             0x13
++#define SQ_DS_NOP                                 0x14
++#define SQ_DS_ADD_F32                             0x15
++#define SQ_DS_WRITE_B8                            0x1e
++#define SQ_DS_WRITE_B16                           0x1f
++#define SQ_DS_ADD_RTN_U32                         0x20
++#define SQ_DS_SUB_RTN_U32                         0x21
++#define SQ_DS_RSUB_RTN_U32                        0x22
++#define SQ_DS_INC_RTN_U32                         0x23
++#define SQ_DS_DEC_RTN_U32                         0x24
++#define SQ_DS_MIN_RTN_I32                         0x25
++#define SQ_DS_MAX_RTN_I32                         0x26
++#define SQ_DS_MIN_RTN_U32                         0x27
++#define SQ_DS_MAX_RTN_U32                         0x28
++#define SQ_DS_AND_RTN_B32                         0x29
++#define SQ_DS_OR_RTN_B32                          0x2a
++#define SQ_DS_XOR_RTN_B32                         0x2b
++#define SQ_DS_MSKOR_RTN_B32                       0x2c
++#define SQ_DS_WRXCHG_RTN_B32                      0x2d
++#define SQ_DS_WRXCHG2_RTN_B32                     0x2e
++#define SQ_DS_WRXCHG2ST64_RTN_B32                 0x2f
++#define SQ_DS_CMPST_RTN_B32                       0x30
++#define SQ_DS_CMPST_RTN_F32                       0x31
++#define SQ_DS_MIN_RTN_F32                         0x32
++#define SQ_DS_MAX_RTN_F32                         0x33
++#define SQ_DS_WRAP_RTN_B32                        0x34
++#define SQ_DS_ADD_RTN_F32                         0x35
++#define SQ_DS_READ_B32                            0x36
++#define SQ_DS_READ2_B32                           0x37
++#define SQ_DS_READ2ST64_B32                       0x38
++#define SQ_DS_READ_I8                             0x39
++#define SQ_DS_READ_U8                             0x3a
++#define SQ_DS_READ_I16                            0x3b
++#define SQ_DS_READ_U16                            0x3c
++#define SQ_DS_SWIZZLE_B32                         0x3d
++#define SQ_DS_PERMUTE_B32                         0x3e
++#define SQ_DS_BPERMUTE_B32                        0x3f
++#define SQ_DS_ADD_U64                             0x40
++#define SQ_DS_SUB_U64                             0x41
++#define SQ_DS_RSUB_U64                            0x42
++#define SQ_DS_INC_U64                             0x43
++#define SQ_DS_DEC_U64                             0x44
++#define SQ_DS_MIN_I64                             0x45
++#define SQ_DS_MAX_I64                             0x46
++#define SQ_DS_MIN_U64                             0x47
++#define SQ_DS_MAX_U64                             0x48
++#define SQ_DS_AND_B64                             0x49
++#define SQ_DS_OR_B64                              0x4a
++#define SQ_DS_XOR_B64                             0x4b
++#define SQ_DS_MSKOR_B64                           0x4c
++#define SQ_DS_WRITE_B64                           0x4d
++#define SQ_DS_WRITE2_B64                          0x4e
++#define SQ_DS_WRITE2ST64_B64                      0x4f
++#define SQ_DS_CMPST_B64                           0x50
++#define SQ_DS_CMPST_F64                           0x51
++#define SQ_DS_MIN_F64                             0x52
++#define SQ_DS_MAX_F64                             0x53
++#define SQ_DS_ADD_RTN_U64                         0x60
++#define SQ_DS_SUB_RTN_U64                         0x61
++#define SQ_DS_RSUB_RTN_U64                        0x62
++#define SQ_DS_INC_RTN_U64                         0x63
++#define SQ_DS_DEC_RTN_U64                         0x64
++#define SQ_DS_MIN_RTN_I64                         0x65
++#define SQ_DS_MAX_RTN_I64                         0x66
++#define SQ_DS_MIN_RTN_U64                         0x67
++#define SQ_DS_MAX_RTN_U64                         0x68
++#define SQ_DS_AND_RTN_B64                         0x69
++#define SQ_DS_OR_RTN_B64                          0x6a
++#define SQ_DS_XOR_RTN_B64                         0x6b
++#define SQ_DS_MSKOR_RTN_B64                       0x6c
++#define SQ_DS_WRXCHG_RTN_B64                      0x6d
++#define SQ_DS_WRXCHG2_RTN_B64                     0x6e
++#define SQ_DS_WRXCHG2ST64_RTN_B64                 0x6f
++#define SQ_DS_CMPST_RTN_B64                       0x70
++#define SQ_DS_CMPST_RTN_F64                       0x71
++#define SQ_DS_MIN_RTN_F64                         0x72
++#define SQ_DS_MAX_RTN_F64                         0x73
++#define SQ_DS_READ_B64                            0x76
++#define SQ_DS_READ2_B64                           0x77
++#define SQ_DS_READ2ST64_B64                       0x78
++#define SQ_DS_CONDXCHG32_RTN_B64                  0x7e
++#define SQ_DS_ADD_SRC2_U32                        0x80
++#define SQ_DS_SUB_SRC2_U32                        0x81
++#define SQ_DS_RSUB_SRC2_U32                       0x82
++#define SQ_DS_INC_SRC2_U32                        0x83
++#define SQ_DS_DEC_SRC2_U32                        0x84
++#define SQ_DS_MIN_SRC2_I32                        0x85
++#define SQ_DS_MAX_SRC2_I32                        0x86
++#define SQ_DS_MIN_SRC2_U32                        0x87
++#define SQ_DS_MAX_SRC2_U32                        0x88
++#define SQ_DS_AND_SRC2_B32                        0x89
++#define SQ_DS_OR_SRC2_B32                         0x8a
++#define SQ_DS_XOR_SRC2_B32                        0x8b
++#define SQ_DS_WRITE_SRC2_B32                      0x8d
++#define SQ_DS_MIN_SRC2_F32                        0x92
++#define SQ_DS_MAX_SRC2_F32                        0x93
++#define SQ_DS_ADD_SRC2_F32                        0x95
++#define SQ_DS_GWS_SEMA_RELEASE_ALL                0x98
++#define SQ_DS_GWS_INIT                            0x99
++#define SQ_DS_GWS_SEMA_V                          0x9a
++#define SQ_DS_GWS_SEMA_BR                         0x9b
++#define SQ_DS_GWS_SEMA_P                          0x9c
++#define SQ_DS_GWS_BARRIER                         0x9d
++#define SQ_DS_CONSUME                             0xbd
++#define SQ_DS_APPEND                              0xbe
++#define SQ_DS_ORDERED_COUNT                       0xbf
++#define SQ_DS_ADD_SRC2_U64                        0xc0
++#define SQ_DS_SUB_SRC2_U64                        0xc1
++#define SQ_DS_RSUB_SRC2_U64                       0xc2
++#define SQ_DS_INC_SRC2_U64                        0xc3
++#define SQ_DS_DEC_SRC2_U64                        0xc4
++#define SQ_DS_MIN_SRC2_I64                        0xc5
++#define SQ_DS_MAX_SRC2_I64                        0xc6
++#define SQ_DS_MIN_SRC2_U64                        0xc7
++#define SQ_DS_MAX_SRC2_U64                        0xc8
++#define SQ_DS_AND_SRC2_B64                        0xc9
++#define SQ_DS_OR_SRC2_B64                         0xca
++#define SQ_DS_XOR_SRC2_B64                        0xcb
++#define SQ_DS_WRITE_SRC2_B64                      0xcd
++#define SQ_DS_MIN_SRC2_F64                        0xd2
++#define SQ_DS_MAX_SRC2_F64                        0xd3
++#define SQ_DS_WRITE_B96                           0xde
++#define SQ_DS_WRITE_B128                          0xdf
++#define SQ_DS_CONDXCHG32_RTN_B128                 0xfd
++#define SQ_DS_READ_B96                            0xfe
++#define SQ_DS_READ_B128                           0xff
++#define SQ_BUFFER_LOAD_FORMAT_X                   0x0
++#define SQ_BUFFER_LOAD_FORMAT_XY                  0x1
++#define SQ_BUFFER_LOAD_FORMAT_XYZ                 0x2
++#define SQ_BUFFER_LOAD_FORMAT_XYZW                0x3
++#define SQ_BUFFER_STORE_FORMAT_X                  0x4
++#define SQ_BUFFER_STORE_FORMAT_XY                 0x5
++#define SQ_BUFFER_STORE_FORMAT_XYZ                0x6
++#define SQ_BUFFER_STORE_FORMAT_XYZW               0x7
++#define SQ_BUFFER_LOAD_FORMAT_D16_X               0x8
++#define SQ_BUFFER_LOAD_FORMAT_D16_XY              0x9
++#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ             0xa
++#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW            0xb
++#define SQ_BUFFER_STORE_FORMAT_D16_X              0xc
++#define SQ_BUFFER_STORE_FORMAT_D16_XY             0xd
++#define SQ_BUFFER_STORE_FORMAT_D16_XYZ            0xe
++#define SQ_BUFFER_STORE_FORMAT_D16_XYZW           0xf
++#define SQ_BUFFER_LOAD_UBYTE                      0x10
++#define SQ_BUFFER_LOAD_SBYTE                      0x11
++#define SQ_BUFFER_LOAD_USHORT                     0x12
++#define SQ_BUFFER_LOAD_SSHORT                     0x13
++#define SQ_BUFFER_LOAD_DWORD                      0x14
++#define SQ_BUFFER_LOAD_DWORDX2                    0x15
++#define SQ_BUFFER_LOAD_DWORDX3                    0x16
++#define SQ_BUFFER_LOAD_DWORDX4                    0x17
++#define SQ_BUFFER_STORE_BYTE                      0x18
++#define SQ_BUFFER_STORE_SHORT                     0x1a
++#define SQ_BUFFER_STORE_DWORD                     0x1c
++#define SQ_BUFFER_STORE_DWORDX2                   0x1d
++#define SQ_BUFFER_STORE_DWORDX3                   0x1e
++#define SQ_BUFFER_STORE_DWORDX4                   0x1f
++#define SQ_BUFFER_STORE_LDS_DWORD                 0x3d
++#define SQ_BUFFER_WBINVL1                         0x3e
++#define SQ_BUFFER_WBINVL1_VOL                     0x3f
++#define SQ_BUFFER_ATOMIC_SWAP                     0x40
++#define SQ_BUFFER_ATOMIC_CMPSWAP                  0x41
++#define SQ_BUFFER_ATOMIC_ADD                      0x42
++#define SQ_BUFFER_ATOMIC_SUB                      0x43
++#define SQ_BUFFER_ATOMIC_SMIN                     0x44
++#define SQ_BUFFER_ATOMIC_UMIN                     0x45
++#define SQ_BUFFER_ATOMIC_SMAX                     0x46
++#define SQ_BUFFER_ATOMIC_UMAX                     0x47
++#define SQ_BUFFER_ATOMIC_AND                      0x48
++#define SQ_BUFFER_ATOMIC_OR                       0x49
++#define SQ_BUFFER_ATOMIC_XOR                      0x4a
++#define SQ_BUFFER_ATOMIC_INC                      0x4b
++#define SQ_BUFFER_ATOMIC_DEC                      0x4c
++#define SQ_BUFFER_ATOMIC_SWAP_X2                  0x60
++#define SQ_BUFFER_ATOMIC_CMPSWAP_X2               0x61
++#define SQ_BUFFER_ATOMIC_ADD_X2                   0x62
++#define SQ_BUFFER_ATOMIC_SUB_X2                   0x63
++#define SQ_BUFFER_ATOMIC_SMIN_X2                  0x64
++#define SQ_BUFFER_ATOMIC_UMIN_X2                  0x65
++#define SQ_BUFFER_ATOMIC_SMAX_X2                  0x66
++#define SQ_BUFFER_ATOMIC_UMAX_X2                  0x67
++#define SQ_BUFFER_ATOMIC_AND_X2                   0x68
++#define SQ_BUFFER_ATOMIC_OR_X2                    0x69
++#define SQ_BUFFER_ATOMIC_XOR_X2                   0x6a
++#define SQ_BUFFER_ATOMIC_INC_X2                   0x6b
++#define SQ_BUFFER_ATOMIC_DEC_X2                   0x6c
++#define SQ_EXEC_LO                                0x7e
++#define SQ_EXEC_HI                                0x7f
++#define SQ_SRC_SCC                                0xfd
++#define SQ_OMOD_OFF                               0x0
++#define SQ_OMOD_M2                                0x1
++#define SQ_OMOD_M4                                0x2
++#define SQ_OMOD_D2                                0x3
++#define SQ_DPP_QUAD_PERM                          0x0
++#define SQ_DPP_ROW_SL1                            0x101
++#define SQ_DPP_ROW_SL2                            0x102
++#define SQ_DPP_ROW_SL3                            0x103
++#define SQ_DPP_ROW_SL4                            0x104
++#define SQ_DPP_ROW_SL5                            0x105
++#define SQ_DPP_ROW_SL6                            0x106
++#define SQ_DPP_ROW_SL7                            0x107
++#define SQ_DPP_ROW_SL8                            0x108
++#define SQ_DPP_ROW_SL9                            0x109
++#define SQ_DPP_ROW_SL10                           0x10a
++#define SQ_DPP_ROW_SL11                           0x10b
++#define SQ_DPP_ROW_SL12                           0x10c
++#define SQ_DPP_ROW_SL13                           0x10d
++#define SQ_DPP_ROW_SL14                           0x10e
++#define SQ_DPP_ROW_SL15                           0x10f
++#define SQ_DPP_ROW_SR1                            0x111
++#define SQ_DPP_ROW_SR2                            0x112
++#define SQ_DPP_ROW_SR3                            0x113
++#define SQ_DPP_ROW_SR4                            0x114
++#define SQ_DPP_ROW_SR5                            0x115
++#define SQ_DPP_ROW_SR6                            0x116
++#define SQ_DPP_ROW_SR7                            0x117
++#define SQ_DPP_ROW_SR8                            0x118
++#define SQ_DPP_ROW_SR9                            0x119
++#define SQ_DPP_ROW_SR10                           0x11a
++#define SQ_DPP_ROW_SR11                           0x11b
++#define SQ_DPP_ROW_SR12                           0x11c
++#define SQ_DPP_ROW_SR13                           0x11d
++#define SQ_DPP_ROW_SR14                           0x11e
++#define SQ_DPP_ROW_SR15                           0x11f
++#define SQ_DPP_ROW_RR1                            0x121
++#define SQ_DPP_ROW_RR2                            0x122
++#define SQ_DPP_ROW_RR3                            0x123
++#define SQ_DPP_ROW_RR4                            0x124
++#define SQ_DPP_ROW_RR5                            0x125
++#define SQ_DPP_ROW_RR6                            0x126
++#define SQ_DPP_ROW_RR7                            0x127
++#define SQ_DPP_ROW_RR8                            0x128
++#define SQ_DPP_ROW_RR9                            0x129
++#define SQ_DPP_ROW_RR10                           0x12a
++#define SQ_DPP_ROW_RR11                           0x12b
++#define SQ_DPP_ROW_RR12                           0x12c
++#define SQ_DPP_ROW_RR13                           0x12d
++#define SQ_DPP_ROW_RR14                           0x12e
++#define SQ_DPP_ROW_RR15                           0x12f
++#define SQ_DPP_WF_SL1                             0x130
++#define SQ_DPP_WF_RL1                             0x134
++#define SQ_DPP_WF_SR1                             0x138
++#define SQ_DPP_WF_RR1                             0x13c
++#define SQ_DPP_ROW_MIRROR                         0x140
++#define SQ_DPP_ROW_HALF_MIRROR                    0x141
++#define SQ_DPP_ROW_BCAST15                        0x142
++#define SQ_DPP_ROW_BCAST31                        0x143
++#define SQ_EXP_GDS0                               0x18
++#define SQ_GS_OP_NOP                              0x0
++#define SQ_GS_OP_CUT                              0x1
++#define SQ_GS_OP_EMIT                             0x2
++#define SQ_GS_OP_EMIT_CUT                         0x3
++#define SQ_IMAGE_LOAD                             0x0
++#define SQ_IMAGE_LOAD_MIP                         0x1
++#define SQ_IMAGE_LOAD_PCK                         0x2
++#define SQ_IMAGE_LOAD_PCK_SGN                     0x3
++#define SQ_IMAGE_LOAD_MIP_PCK                     0x4
++#define SQ_IMAGE_LOAD_MIP_PCK_SGN                 0x5
++#define SQ_IMAGE_STORE                            0x8
++#define SQ_IMAGE_STORE_MIP                        0x9
++#define SQ_IMAGE_STORE_PCK                        0xa
++#define SQ_IMAGE_STORE_MIP_PCK                    0xb
++#define SQ_IMAGE_GET_RESINFO                      0xe
++#define SQ_IMAGE_ATOMIC_SWAP                      0x10
++#define SQ_IMAGE_ATOMIC_CMPSWAP                   0x11
++#define SQ_IMAGE_ATOMIC_ADD                       0x12
++#define SQ_IMAGE_ATOMIC_SUB                       0x13
++#define SQ_IMAGE_ATOMIC_SMIN                      0x14
++#define SQ_IMAGE_ATOMIC_UMIN                      0x15
++#define SQ_IMAGE_ATOMIC_SMAX                      0x16
++#define SQ_IMAGE_ATOMIC_UMAX                      0x17
++#define SQ_IMAGE_ATOMIC_AND                       0x18
++#define SQ_IMAGE_ATOMIC_OR                        0x19
++#define SQ_IMAGE_ATOMIC_XOR                       0x1a
++#define SQ_IMAGE_ATOMIC_INC                       0x1b
++#define SQ_IMAGE_ATOMIC_DEC                       0x1c
++#define SQ_IMAGE_SAMPLE                           0x20
++#define SQ_IMAGE_SAMPLE_CL                        0x21
++#define SQ_IMAGE_SAMPLE_D                         0x22
++#define SQ_IMAGE_SAMPLE_D_CL                      0x23
++#define SQ_IMAGE_SAMPLE_L                         0x24
++#define SQ_IMAGE_SAMPLE_B                         0x25
++#define SQ_IMAGE_SAMPLE_B_CL                      0x26
++#define SQ_IMAGE_SAMPLE_LZ                        0x27
++#define SQ_IMAGE_SAMPLE_C                         0x28
++#define SQ_IMAGE_SAMPLE_C_CL                      0x29
++#define SQ_IMAGE_SAMPLE_C_D                       0x2a
++#define SQ_IMAGE_SAMPLE_C_D_CL                    0x2b
++#define SQ_IMAGE_SAMPLE_C_L                       0x2c
++#define SQ_IMAGE_SAMPLE_C_B                       0x2d
++#define SQ_IMAGE_SAMPLE_C_B_CL                    0x2e
++#define SQ_IMAGE_SAMPLE_C_LZ                      0x2f
++#define SQ_IMAGE_SAMPLE_O                         0x30
++#define SQ_IMAGE_SAMPLE_CL_O                      0x31
++#define SQ_IMAGE_SAMPLE_D_O                       0x32
++#define SQ_IMAGE_SAMPLE_D_CL_O                    0x33
++#define SQ_IMAGE_SAMPLE_L_O                       0x34
++#define SQ_IMAGE_SAMPLE_B_O                       0x35
++#define SQ_IMAGE_SAMPLE_B_CL_O                    0x36
++#define SQ_IMAGE_SAMPLE_LZ_O                      0x37
++#define SQ_IMAGE_SAMPLE_C_O                       0x38
++#define SQ_IMAGE_SAMPLE_C_CL_O                    0x39
++#define SQ_IMAGE_SAMPLE_C_D_O                     0x3a
++#define SQ_IMAGE_SAMPLE_C_D_CL_O                  0x3b
++#define SQ_IMAGE_SAMPLE_C_L_O                     0x3c
++#define SQ_IMAGE_SAMPLE_C_B_O                     0x3d
++#define SQ_IMAGE_SAMPLE_C_B_CL_O                  0x3e
++#define SQ_IMAGE_SAMPLE_C_LZ_O                    0x3f
++#define SQ_IMAGE_GATHER4                          0x40
++#define SQ_IMAGE_GATHER4_CL                       0x41
++#define SQ_IMAGE_GATHER4_L                        0x44
++#define SQ_IMAGE_GATHER4_B                        0x45
++#define SQ_IMAGE_GATHER4_B_CL                     0x46
++#define SQ_IMAGE_GATHER4_LZ                       0x47
++#define SQ_IMAGE_GATHER4_C                        0x48
++#define SQ_IMAGE_GATHER4_C_CL                     0x49
++#define SQ_IMAGE_GATHER4_C_L                      0x4c
++#define SQ_IMAGE_GATHER4_C_B                      0x4d
++#define SQ_IMAGE_GATHER4_C_B_CL                   0x4e
++#define SQ_IMAGE_GATHER4_C_LZ                     0x4f
++#define SQ_IMAGE_GATHER4_O                        0x50
++#define SQ_IMAGE_GATHER4_CL_O                     0x51
++#define SQ_IMAGE_GATHER4_L_O                      0x54
++#define SQ_IMAGE_GATHER4_B_O                      0x55
++#define SQ_IMAGE_GATHER4_B_CL_O                   0x56
++#define SQ_IMAGE_GATHER4_LZ_O                     0x57
++#define SQ_IMAGE_GATHER4_C_O                      0x58
++#define SQ_IMAGE_GATHER4_C_CL_O                   0x59
++#define SQ_IMAGE_GATHER4_C_L_O                    0x5c
++#define SQ_IMAGE_GATHER4_C_B_O                    0x5d
++#define SQ_IMAGE_GATHER4_C_B_CL_O                 0x5e
++#define SQ_IMAGE_GATHER4_C_LZ_O                   0x5f
++#define SQ_IMAGE_GET_LOD                          0x60
++#define SQ_IMAGE_SAMPLE_CD                        0x68
++#define SQ_IMAGE_SAMPLE_CD_CL                     0x69
++#define SQ_IMAGE_SAMPLE_C_CD                      0x6a
++#define SQ_IMAGE_SAMPLE_C_CD_CL                   0x6b
++#define SQ_IMAGE_SAMPLE_CD_O                      0x6c
++#define SQ_IMAGE_SAMPLE_CD_CL_O                   0x6d
++#define SQ_IMAGE_SAMPLE_C_CD_O                    0x6e
++#define SQ_IMAGE_SAMPLE_C_CD_CL_O                 0x6f
++#define SQ_IMAGE_RSRC256                          0x7e
++#define SQ_IMAGE_SAMPLER                          0x7f
++#define SQ_SRC_VCCZ                               0xfb
++#define SQ_SRC_VGPR0                              0x100
++#define SQ_SDWA_BYTE_0                            0x0
++#define SQ_SDWA_BYTE_1                            0x1
++#define SQ_SDWA_BYTE_2                            0x2
++#define SQ_SDWA_BYTE_3                            0x3
++#define SQ_SDWA_WORD_0                            0x4
++#define SQ_SDWA_WORD_1                            0x5
++#define SQ_SDWA_DWORD                             0x6
++#define SQ_XNACK_MASK_LO                          0x68
++#define SQ_XNACK_MASK_HI                          0x69
++#define SQ_TBUFFER_LOAD_FORMAT_X                  0x0
++#define SQ_TBUFFER_LOAD_FORMAT_XY                 0x1
++#define SQ_TBUFFER_LOAD_FORMAT_XYZ                0x2
++#define SQ_TBUFFER_LOAD_FORMAT_XYZW               0x3
++#define SQ_TBUFFER_STORE_FORMAT_X                 0x4
++#define SQ_TBUFFER_STORE_FORMAT_XY                0x5
++#define SQ_TBUFFER_STORE_FORMAT_XYZ               0x6
++#define SQ_TBUFFER_STORE_FORMAT_XYZW              0x7
++#define SQ_TBUFFER_LOAD_FORMAT_D16_X              0x8
++#define SQ_TBUFFER_LOAD_FORMAT_D16_XY             0x9
++#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ            0xa
++#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW           0xb
++#define SQ_TBUFFER_STORE_FORMAT_D16_X             0xc
++#define SQ_TBUFFER_STORE_FORMAT_D16_XY            0xd
++#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ           0xe
++#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW          0xf
++#define SQ_CHAN_X                                 0x0
++#define SQ_CHAN_Y                                 0x1
++#define SQ_CHAN_Z                                 0x2
++#define SQ_CHAN_W                                 0x3
++#define SQ_V_NOP                                  0x0
++#define SQ_V_MOV_B32                              0x1
++#define SQ_V_READFIRSTLANE_B32                    0x2
++#define SQ_V_CVT_I32_F64                          0x3
++#define SQ_V_CVT_F64_I32                          0x4
++#define SQ_V_CVT_F32_I32                          0x5
++#define SQ_V_CVT_F32_U32                          0x6
++#define SQ_V_CVT_U32_F32                          0x7
++#define SQ_V_CVT_I32_F32                          0x8
++#define SQ_V_MOV_FED_B32                          0x9
++#define SQ_V_CVT_F16_F32                          0xa
++#define SQ_V_CVT_F32_F16                          0xb
++#define SQ_V_CVT_RPI_I32_F32                      0xc
++#define SQ_V_CVT_FLR_I32_F32                      0xd
++#define SQ_V_CVT_OFF_F32_I4                       0xe
++#define SQ_V_CVT_F32_F64                          0xf
++#define SQ_V_CVT_F64_F32                          0x10
++#define SQ_V_CVT_F32_UBYTE0                       0x11
++#define SQ_V_CVT_F32_UBYTE1                       0x12
++#define SQ_V_CVT_F32_UBYTE2                       0x13
++#define SQ_V_CVT_F32_UBYTE3                       0x14
++#define SQ_V_CVT_U32_F64                          0x15
++#define SQ_V_CVT_F64_U32                          0x16
++#define SQ_V_TRUNC_F64                            0x17
++#define SQ_V_CEIL_F64                             0x18
++#define SQ_V_RNDNE_F64                            0x19
++#define SQ_V_FLOOR_F64                            0x1a
++#define SQ_V_FRACT_F32                            0x1b
++#define SQ_V_TRUNC_F32                            0x1c
++#define SQ_V_CEIL_F32                             0x1d
++#define SQ_V_RNDNE_F32                            0x1e
++#define SQ_V_FLOOR_F32                            0x1f
++#define SQ_V_EXP_F32                              0x20
++#define SQ_V_LOG_F32                              0x21
++#define SQ_V_RCP_F32                              0x22
++#define SQ_V_RCP_IFLAG_F32                        0x23
++#define SQ_V_RSQ_F32                              0x24
++#define SQ_V_RCP_F64                              0x25
++#define SQ_V_RSQ_F64                              0x26
++#define SQ_V_SQRT_F32                             0x27
++#define SQ_V_SQRT_F64                             0x28
++#define SQ_V_SIN_F32                              0x29
++#define SQ_V_COS_F32                              0x2a
++#define SQ_V_NOT_B32                              0x2b
++#define SQ_V_BFREV_B32                            0x2c
++#define SQ_V_FFBH_U32                             0x2d
++#define SQ_V_FFBL_B32                             0x2e
++#define SQ_V_FFBH_I32                             0x2f
++#define SQ_V_FREXP_EXP_I32_F64                    0x30
++#define SQ_V_FREXP_MANT_F64                       0x31
++#define SQ_V_FRACT_F64                            0x32
++#define SQ_V_FREXP_EXP_I32_F32                    0x33
++#define SQ_V_FREXP_MANT_F32                       0x34
++#define SQ_V_CLREXCP                              0x35
++#define SQ_V_MOVRELD_B32                          0x36
++#define SQ_V_MOVRELS_B32                          0x37
++#define SQ_V_MOVRELSD_B32                         0x38
++#define SQ_V_CVT_F16_U16                          0x39
++#define SQ_V_CVT_F16_I16                          0x3a
++#define SQ_V_CVT_U16_F16                          0x3b
++#define SQ_V_CVT_I16_F16                          0x3c
++#define SQ_V_RCP_F16                              0x3d
++#define SQ_V_SQRT_F16                             0x3e
++#define SQ_V_RSQ_F16                              0x3f
++#define SQ_V_LOG_F16                              0x40
++#define SQ_V_EXP_F16                              0x41
++#define SQ_V_FREXP_MANT_F16                       0x42
++#define SQ_V_FREXP_EXP_I16_F16                    0x43
++#define SQ_V_FLOOR_F16                            0x44
++#define SQ_V_CEIL_F16                             0x45
++#define SQ_V_TRUNC_F16                            0x46
++#define SQ_V_RNDNE_F16                            0x47
++#define SQ_V_FRACT_F16                            0x48
++#define SQ_V_SIN_F16                              0x49
++#define SQ_V_COS_F16                              0x4a
++#define SQ_V_EXP_LEGACY_F32                       0x4b
++#define SQ_V_LOG_LEGACY_F32                       0x4c
++#define SQ_SRC_SDWA                               0xf9
++#define SQ_V_OPC_OFFSET                           0x0
++#define SQ_V_OP2_OFFSET                           0x100
++#define SQ_V_OP1_OFFSET                           0x140
++#define SQ_V_INTRP_OFFSET                         0x270
++#define SQ_V_INTERP_P1_F32                        0x0
++#define SQ_V_INTERP_P2_F32                        0x1
++#define SQ_V_INTERP_MOV_F32                       0x2
++#define SQ_S_NOP                                  0x0
++#define SQ_S_ENDPGM                               0x1
++#define SQ_S_BRANCH                               0x2
++#define SQ_S_WAKEUP                               0x3
++#define SQ_S_CBRANCH_SCC0                         0x4
++#define SQ_S_CBRANCH_SCC1                         0x5
++#define SQ_S_CBRANCH_VCCZ                         0x6
++#define SQ_S_CBRANCH_VCCNZ                        0x7
++#define SQ_S_CBRANCH_EXECZ                        0x8
++#define SQ_S_CBRANCH_EXECNZ                       0x9
++#define SQ_S_BARRIER                              0xa
++#define SQ_S_SETKILL                              0xb
++#define SQ_S_WAITCNT                              0xc
++#define SQ_S_SETHALT                              0xd
++#define SQ_S_SLEEP                                0xe
++#define SQ_S_SETPRIO                              0xf
++#define SQ_S_SENDMSG                              0x10
++#define SQ_S_SENDMSGHALT                          0x11
++#define SQ_S_TRAP                                 0x12
++#define SQ_S_ICACHE_INV                           0x13
++#define SQ_S_INCPERFLEVEL                         0x14
++#define SQ_S_DECPERFLEVEL                         0x15
++#define SQ_S_TTRACEDATA                           0x16
++#define SQ_S_CBRANCH_CDBGSYS                      0x17
++#define SQ_S_CBRANCH_CDBGUSER                     0x18
++#define SQ_S_CBRANCH_CDBGSYS_OR_USER              0x19
++#define SQ_S_CBRANCH_CDBGSYS_AND_USER             0x1a
++#define SQ_S_ENDPGM_SAVED                         0x1b
++#define SQ_S_SET_GPR_IDX_OFF                      0x1c
++#define SQ_S_SET_GPR_IDX_MODE                     0x1d
++#define SQ_SRC_DPP                                0xfa
++#define SQ_SRC_LITERAL                            0xff
++#define SQ_VCC_LO                                 0x6a
++#define SQ_VCC_HI                                 0x6b
++#define SQ_PARAM_P10                              0x0
++#define SQ_PARAM_P20                              0x1
++#define SQ_PARAM_P0                               0x2
++#define SQ_SRC_LDS_DIRECT                         0xfe
++#define SQ_V_CNDMASK_B32                          0x0
++#define SQ_V_ADD_F32                              0x1
++#define SQ_V_SUB_F32                              0x2
++#define SQ_V_SUBREV_F32                           0x3
++#define SQ_V_MUL_LEGACY_F32                       0x4
++#define SQ_V_MUL_F32                              0x5
++#define SQ_V_MUL_I32_I24                          0x6
++#define SQ_V_MUL_HI_I32_I24                       0x7
++#define SQ_V_MUL_U32_U24                          0x8
++#define SQ_V_MUL_HI_U32_U24                       0x9
++#define SQ_V_MIN_F32                              0xa
++#define SQ_V_MAX_F32                              0xb
++#define SQ_V_MIN_I32                              0xc
++#define SQ_V_MAX_I32                              0xd
++#define SQ_V_MIN_U32                              0xe
++#define SQ_V_MAX_U32                              0xf
++#define SQ_V_LSHRREV_B32                          0x10
++#define SQ_V_ASHRREV_I32                          0x11
++#define SQ_V_LSHLREV_B32                          0x12
++#define SQ_V_AND_B32                              0x13
++#define SQ_V_OR_B32                               0x14
++#define SQ_V_XOR_B32                              0x15
++#define SQ_V_MAC_F32                              0x16
++#define SQ_V_MADMK_F32                            0x17
++#define SQ_V_MADAK_F32                            0x18
++#define SQ_V_ADD_U32                              0x19
++#define SQ_V_SUB_U32                              0x1a
++#define SQ_V_SUBREV_U32                           0x1b
++#define SQ_V_ADDC_U32                             0x1c
++#define SQ_V_SUBB_U32                             0x1d
++#define SQ_V_SUBBREV_U32                          0x1e
++#define SQ_V_ADD_F16                              0x1f
++#define SQ_V_SUB_F16                              0x20
++#define SQ_V_SUBREV_F16                           0x21
++#define SQ_V_MUL_F16                              0x22
++#define SQ_V_MAC_F16                              0x23
++#define SQ_V_MADMK_F16                            0x24
++#define SQ_V_MADAK_F16                            0x25
++#define SQ_V_ADD_U16                              0x26
++#define SQ_V_SUB_U16                              0x27
++#define SQ_V_SUBREV_U16                           0x28
++#define SQ_V_MUL_LO_U16                           0x29
++#define SQ_V_LSHLREV_B16                          0x2a
++#define SQ_V_LSHRREV_B16                          0x2b
++#define SQ_V_ASHRREV_I16                          0x2c
++#define SQ_V_MAX_F16                              0x2d
++#define SQ_V_MIN_F16                              0x2e
++#define SQ_V_MAX_U16                              0x2f
++#define SQ_V_MAX_I16                              0x30
++#define SQ_V_MIN_U16                              0x31
++#define SQ_V_MIN_I16                              0x32
++#define SQ_V_LDEXP_F16                            0x33
++#define SQ_FLAT_LOAD_UBYTE                        0x10
++#define SQ_FLAT_LOAD_SBYTE                        0x11
++#define SQ_FLAT_LOAD_USHORT                       0x12
++#define SQ_FLAT_LOAD_SSHORT                       0x13
++#define SQ_FLAT_LOAD_DWORD                        0x14
++#define SQ_FLAT_LOAD_DWORDX2                      0x15
++#define SQ_FLAT_LOAD_DWORDX3                      0x16
++#define SQ_FLAT_LOAD_DWORDX4                      0x17
++#define SQ_FLAT_STORE_BYTE                        0x18
++#define SQ_FLAT_STORE_SHORT                       0x1a
++#define SQ_FLAT_STORE_DWORD                       0x1c
++#define SQ_FLAT_STORE_DWORDX2                     0x1d
++#define SQ_FLAT_STORE_DWORDX3                     0x1e
++#define SQ_FLAT_STORE_DWORDX4                     0x1f
++#define SQ_FLAT_ATOMIC_SWAP                       0x40
++#define SQ_FLAT_ATOMIC_CMPSWAP                    0x41
++#define SQ_FLAT_ATOMIC_ADD                        0x42
++#define SQ_FLAT_ATOMIC_SUB                        0x43
++#define SQ_FLAT_ATOMIC_SMIN                       0x44
++#define SQ_FLAT_ATOMIC_UMIN                       0x45
++#define SQ_FLAT_ATOMIC_SMAX                       0x46
++#define SQ_FLAT_ATOMIC_UMAX                       0x47
++#define SQ_FLAT_ATOMIC_AND                        0x48
++#define SQ_FLAT_ATOMIC_OR                         0x49
++#define SQ_FLAT_ATOMIC_XOR                        0x4a
++#define SQ_FLAT_ATOMIC_INC                        0x4b
++#define SQ_FLAT_ATOMIC_DEC                        0x4c
++#define SQ_FLAT_ATOMIC_SWAP_X2                    0x60
++#define SQ_FLAT_ATOMIC_CMPSWAP_X2                 0x61
++#define SQ_FLAT_ATOMIC_ADD_X2                     0x62
++#define SQ_FLAT_ATOMIC_SUB_X2                     0x63
++#define SQ_FLAT_ATOMIC_SMIN_X2                    0x64
++#define SQ_FLAT_ATOMIC_UMIN_X2                    0x65
++#define SQ_FLAT_ATOMIC_SMAX_X2                    0x66
++#define SQ_FLAT_ATOMIC_UMAX_X2                    0x67
++#define SQ_FLAT_ATOMIC_AND_X2                     0x68
++#define SQ_FLAT_ATOMIC_OR_X2                      0x69
++#define SQ_FLAT_ATOMIC_XOR_X2                     0x6a
++#define SQ_FLAT_ATOMIC_INC_X2                     0x6b
++#define SQ_FLAT_ATOMIC_DEC_X2                     0x6c
++#define SQ_S_CMP_EQ_I32                           0x0
++#define SQ_S_CMP_LG_I32                           0x1
++#define SQ_S_CMP_GT_I32                           0x2
++#define SQ_S_CMP_GE_I32                           0x3
++#define SQ_S_CMP_LT_I32                           0x4
++#define SQ_S_CMP_LE_I32                           0x5
++#define SQ_S_CMP_EQ_U32                           0x6
++#define SQ_S_CMP_LG_U32                           0x7
++#define SQ_S_CMP_GT_U32                           0x8
++#define SQ_S_CMP_GE_U32                           0x9
++#define SQ_S_CMP_LT_U32                           0xa
++#define SQ_S_CMP_LE_U32                           0xb
++#define SQ_S_BITCMP0_B32                          0xc
++#define SQ_S_BITCMP1_B32                          0xd
++#define SQ_S_BITCMP0_B64                          0xe
++#define SQ_S_BITCMP1_B64                          0xf
++#define SQ_S_SETVSKIP                             0x10
++#define SQ_S_SET_GPR_IDX_ON                       0x11
++#define SQ_S_CMP_EQ_U64                           0x12
++#define SQ_S_CMP_LG_U64                           0x13
++#define SQ_M0                                     0x7c
++#define SQ_V_MAD_LEGACY_F32                       0x1c0
++#define SQ_V_MAD_F32                              0x1c1
++#define SQ_V_MAD_I32_I24                          0x1c2
++#define SQ_V_MAD_U32_U24                          0x1c3
++#define SQ_V_CUBEID_F32                           0x1c4
++#define SQ_V_CUBESC_F32                           0x1c5
++#define SQ_V_CUBETC_F32                           0x1c6
++#define SQ_V_CUBEMA_F32                           0x1c7
++#define SQ_V_BFE_U32                              0x1c8
++#define SQ_V_BFE_I32                              0x1c9
++#define SQ_V_BFI_B32                              0x1ca
++#define SQ_V_FMA_F32                              0x1cb
++#define SQ_V_FMA_F64                              0x1cc
++#define SQ_V_LERP_U8                              0x1cd
++#define SQ_V_ALIGNBIT_B32                         0x1ce
++#define SQ_V_ALIGNBYTE_B32                        0x1cf
++#define SQ_V_MIN3_F32                             0x1d0
++#define SQ_V_MIN3_I32                             0x1d1
++#define SQ_V_MIN3_U32                             0x1d2
++#define SQ_V_MAX3_F32                             0x1d3
++#define SQ_V_MAX3_I32                             0x1d4
++#define SQ_V_MAX3_U32                             0x1d5
++#define SQ_V_MED3_F32                             0x1d6
++#define SQ_V_MED3_I32                             0x1d7
++#define SQ_V_MED3_U32                             0x1d8
++#define SQ_V_SAD_U8                               0x1d9
++#define SQ_V_SAD_HI_U8                            0x1da
++#define SQ_V_SAD_U16                              0x1db
++#define SQ_V_SAD_U32                              0x1dc
++#define SQ_V_CVT_PK_U8_F32                        0x1dd
++#define SQ_V_DIV_FIXUP_F32                        0x1de
++#define SQ_V_DIV_FIXUP_F64                        0x1df
++#define SQ_V_DIV_SCALE_F32                        0x1e0
++#define SQ_V_DIV_SCALE_F64                        0x1e1
++#define SQ_V_DIV_FMAS_F32                         0x1e2
++#define SQ_V_DIV_FMAS_F64                         0x1e3
++#define SQ_V_MSAD_U8                              0x1e4
++#define SQ_V_QSAD_PK_U16_U8                       0x1e5
++#define SQ_V_MQSAD_PK_U16_U8                      0x1e6
++#define SQ_V_MQSAD_U32_U8                         0x1e7
++#define SQ_V_MAD_U64_U32                          0x1e8
++#define SQ_V_MAD_I64_I32                          0x1e9
++#define SQ_V_MAD_F16                              0x1ea
++#define SQ_V_MAD_U16                              0x1eb
++#define SQ_V_MAD_I16                              0x1ec
++#define SQ_V_PERM_B32                             0x1ed
++#define SQ_V_FMA_F16                              0x1ee
++#define SQ_V_DIV_FIXUP_F16                        0x1ef
++#define SQ_V_CVT_PKACCUM_U8_F32                   0x1f0
++#define SQ_V_INTERP_P1LL_F16                      0x274
++#define SQ_V_INTERP_P1LV_F16                      0x275
++#define SQ_V_INTERP_P2_F16                        0x276
++#define SQ_V_ADD_F64                              0x280
++#define SQ_V_MUL_F64                              0x281
++#define SQ_V_MIN_F64                              0x282
++#define SQ_V_MAX_F64                              0x283
++#define SQ_V_LDEXP_F64                            0x284
++#define SQ_V_MUL_LO_U32                           0x285
++#define SQ_V_MUL_HI_U32                           0x286
++#define SQ_V_MUL_HI_I32                           0x287
++#define SQ_V_LDEXP_F32                            0x288
++#define SQ_V_READLANE_B32                         0x289
++#define SQ_V_WRITELANE_B32                        0x28a
++#define SQ_V_BCNT_U32_B32                         0x28b
++#define SQ_V_MBCNT_LO_U32_B32                     0x28c
++#define SQ_V_MBCNT_HI_U32_B32                     0x28d
++#define SQ_V_MAC_LEGACY_F32                       0x28e
++#define SQ_V_LSHLREV_B64                          0x28f
++#define SQ_V_LSHRREV_B64                          0x290
++#define SQ_V_ASHRREV_I64                          0x291
++#define SQ_V_TRIG_PREOP_F64                       0x292
++#define SQ_V_BFM_B32                              0x293
++#define SQ_V_CVT_PKNORM_I16_F32                   0x294
++#define SQ_V_CVT_PKNORM_U16_F32                   0x295
++#define SQ_V_CVT_PKRTZ_F16_F32                    0x296
++#define SQ_V_CVT_PK_U16_U32                       0x297
++#define SQ_V_CVT_PK_I16_I32                       0x298
++#define SQ_VCC_ALL                                0x0
++#define SQ_SRC_EXECZ                              0xfc
++#define SQ_FLAT_SCRATCH_LO                        0x66
++#define SQ_FLAT_SCRATCH_HI                        0x67
++#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT            0x1
++#define SQ_SYSMSG_OP_REG_RD                       0x2
++#define SQ_SYSMSG_OP_HOST_TRAP_ACK                0x3
++#define SQ_SYSMSG_OP_TTRACE_PC                    0x4
++#define SQ_HW_REG_MODE                            0x1
++#define SQ_HW_REG_STATUS                          0x2
++#define SQ_HW_REG_TRAPSTS                         0x3
++#define SQ_HW_REG_HW_ID                           0x4
++#define SQ_HW_REG_GPR_ALLOC                       0x5
++#define SQ_HW_REG_LDS_ALLOC                       0x6
++#define SQ_HW_REG_IB_STS                          0x7
++#define SQ_HW_REG_PC_LO                           0x8
++#define SQ_HW_REG_PC_HI                           0x9
++#define SQ_HW_REG_INST_DW0                        0xa
++#define SQ_HW_REG_INST_DW1                        0xb
++#define SQ_HW_REG_IB_DBG0                         0xc
++#define SQ_HW_REG_IB_DBG1                         0xd
++#define SQ_DPP_BOUND_OFF                          0x0
++#define SQ_DPP_BOUND_ZERO                         0x1
++#define SQ_R1                                     0x1
++#define SQ_R2                                     0x2
++#define SQ_R3                                     0x3
++#define SQ_R4                                     0x4
++#define SQ_R5                                     0x5
++#define SQ_R6                                     0x6
++#define SQ_R7                                     0x7
++#define SQ_R8                                     0x8
++#define SQ_R9                                     0x9
++#define SQ_R10                                    0xa
++#define SQ_R11                                    0xb
++#define SQ_R12                                    0xc
++#define SQ_R13                                    0xd
++#define SQ_R14                                    0xe
++#define SQ_R15                                    0xf
++#define SQ_S_ADD_U32                              0x0
++#define SQ_S_SUB_U32                              0x1
++#define SQ_S_ADD_I32                              0x2
++#define SQ_S_SUB_I32                              0x3
++#define SQ_S_ADDC_U32                             0x4
++#define SQ_S_SUBB_U32                             0x5
++#define SQ_S_MIN_I32                              0x6
++#define SQ_S_MIN_U32                              0x7
++#define SQ_S_MAX_I32                              0x8
++#define SQ_S_MAX_U32                              0x9
++#define SQ_S_CSELECT_B32                          0xa
++#define SQ_S_CSELECT_B64                          0xb
++#define SQ_S_AND_B32                              0xc
++#define SQ_S_AND_B64                              0xd
++#define SQ_S_OR_B32                               0xe
++#define SQ_S_OR_B64                               0xf
++#define SQ_S_XOR_B32                              0x10
++#define SQ_S_XOR_B64                              0x11
++#define SQ_S_ANDN2_B32                            0x12
++#define SQ_S_ANDN2_B64                            0x13
++#define SQ_S_ORN2_B32                             0x14
++#define SQ_S_ORN2_B64                             0x15
++#define SQ_S_NAND_B32                             0x16
++#define SQ_S_NAND_B64                             0x17
++#define SQ_S_NOR_B32                              0x18
++#define SQ_S_NOR_B64                              0x19
++#define SQ_S_XNOR_B32                             0x1a
++#define SQ_S_XNOR_B64                             0x1b
++#define SQ_S_LSHL_B32                             0x1c
++#define SQ_S_LSHL_B64                             0x1d
++#define SQ_S_LSHR_B32                             0x1e
++#define SQ_S_LSHR_B64                             0x1f
++#define SQ_S_ASHR_I32                             0x20
++#define SQ_S_ASHR_I64                             0x21
++#define SQ_S_BFM_B32                              0x22
++#define SQ_S_BFM_B64                              0x23
++#define SQ_S_MUL_I32                              0x24
++#define SQ_S_BFE_U32                              0x25
++#define SQ_S_BFE_I32                              0x26
++#define SQ_S_BFE_U64                              0x27
++#define SQ_S_BFE_I64                              0x28
++#define SQ_S_CBRANCH_G_FORK                       0x29
++#define SQ_S_ABSDIFF_I32                          0x2a
++#define SQ_S_RFE_RESTORE_B64                      0x2b
++#define SQ_MSG_INTERRUPT                          0x1
++#define SQ_MSG_GS                                 0x2
++#define SQ_MSG_GS_DONE                            0x3
++#define SQ_MSG_SAVEWAVE                           0x4
++#define SQ_MSG_SYSMSG                             0xf
++typedef enum TEX_BORDER_COLOR_TYPE {
++	TEX_BorderColor_TransparentBlack                 = 0x0,
++	TEX_BorderColor_OpaqueBlack                      = 0x1,
++	TEX_BorderColor_OpaqueWhite                      = 0x2,
++	TEX_BorderColor_Register                         = 0x3,
++} TEX_BORDER_COLOR_TYPE;
++typedef enum TEX_CHROMA_KEY {
++	TEX_ChromaKey_Disabled                           = 0x0,
++	TEX_ChromaKey_Kill                               = 0x1,
++	TEX_ChromaKey_Blend                              = 0x2,
++	TEX_ChromaKey_RESERVED_3                         = 0x3,
++} TEX_CHROMA_KEY;
++typedef enum TEX_CLAMP {
++	TEX_Clamp_Repeat                                 = 0x0,
++	TEX_Clamp_Mirror                                 = 0x1,
++	TEX_Clamp_ClampToLast                            = 0x2,
++	TEX_Clamp_MirrorOnceToLast                       = 0x3,
++	TEX_Clamp_ClampHalfToBorder                      = 0x4,
++	TEX_Clamp_MirrorOnceHalfToBorder                 = 0x5,
++	TEX_Clamp_ClampToBorder                          = 0x6,
++	TEX_Clamp_MirrorOnceToBorder                     = 0x7,
++} TEX_CLAMP;
++typedef enum TEX_COORD_TYPE {
++	TEX_CoordType_Unnormalized                       = 0x0,
++	TEX_CoordType_Normalized                         = 0x1,
++} TEX_COORD_TYPE;
++typedef enum TEX_DEPTH_COMPARE_FUNCTION {
++	TEX_DepthCompareFunction_Never                   = 0x0,
++	TEX_DepthCompareFunction_Less                    = 0x1,
++	TEX_DepthCompareFunction_Equal                   = 0x2,
++	TEX_DepthCompareFunction_LessEqual               = 0x3,
++	TEX_DepthCompareFunction_Greater                 = 0x4,
++	TEX_DepthCompareFunction_NotEqual                = 0x5,
++	TEX_DepthCompareFunction_GreaterEqual            = 0x6,
++	TEX_DepthCompareFunction_Always                  = 0x7,
++} TEX_DEPTH_COMPARE_FUNCTION;
++typedef enum TEX_DIM {
++	TEX_Dim_1D                                       = 0x0,
++	TEX_Dim_2D                                       = 0x1,
++	TEX_Dim_3D                                       = 0x2,
++	TEX_Dim_CubeMap                                  = 0x3,
++	TEX_Dim_1DArray                                  = 0x4,
++	TEX_Dim_2DArray                                  = 0x5,
++	TEX_Dim_2D_MSAA                                  = 0x6,
++	TEX_Dim_2DArray_MSAA                             = 0x7,
++} TEX_DIM;
++typedef enum TEX_FORMAT_COMP {
++	TEX_FormatComp_Unsigned                          = 0x0,
++	TEX_FormatComp_Signed                            = 0x1,
++	TEX_FormatComp_UnsignedBiased                    = 0x2,
++	TEX_FormatComp_RESERVED_3                        = 0x3,
++} TEX_FORMAT_COMP;
++typedef enum TEX_MAX_ANISO_RATIO {
++	TEX_MaxAnisoRatio_1to1                           = 0x0,
++	TEX_MaxAnisoRatio_2to1                           = 0x1,
++	TEX_MaxAnisoRatio_4to1                           = 0x2,
++	TEX_MaxAnisoRatio_8to1                           = 0x3,
++	TEX_MaxAnisoRatio_16to1                          = 0x4,
++	TEX_MaxAnisoRatio_RESERVED_5                     = 0x5,
++	TEX_MaxAnisoRatio_RESERVED_6                     = 0x6,
++	TEX_MaxAnisoRatio_RESERVED_7                     = 0x7,
++} TEX_MAX_ANISO_RATIO;
++typedef enum TEX_MIP_FILTER {
++	TEX_MipFilter_None                               = 0x0,
++	TEX_MipFilter_Point                              = 0x1,
++	TEX_MipFilter_Linear                             = 0x2,
++	TEX_MipFilter_Point_Aniso_Adj                    = 0x3,
++} TEX_MIP_FILTER;
++typedef enum TEX_REQUEST_SIZE {
++	TEX_RequestSize_32B                              = 0x0,
++	TEX_RequestSize_64B                              = 0x1,
++	TEX_RequestSize_128B                             = 0x2,
++	TEX_RequestSize_2X64B                            = 0x3,
++} TEX_REQUEST_SIZE;
++typedef enum TEX_SAMPLER_TYPE {
++	TEX_SamplerType_Invalid                          = 0x0,
++	TEX_SamplerType_Valid                            = 0x1,
++} TEX_SAMPLER_TYPE;
++typedef enum TEX_XY_FILTER {
++	TEX_XYFilter_Point                               = 0x0,
++	TEX_XYFilter_Linear                              = 0x1,
++	TEX_XYFilter_AnisoPoint                          = 0x2,
++	TEX_XYFilter_AnisoLinear                         = 0x3,
++} TEX_XY_FILTER;
++typedef enum TEX_Z_FILTER {
++	TEX_ZFilter_None                                 = 0x0,
++	TEX_ZFilter_Point                                = 0x1,
++	TEX_ZFilter_Linear                               = 0x2,
++	TEX_ZFilter_RESERVED_3                           = 0x3,
++} TEX_Z_FILTER;
++typedef enum VTX_CLAMP {
++	VTX_Clamp_ClampToZero                            = 0x0,
++	VTX_Clamp_ClampToNAN                             = 0x1,
++} VTX_CLAMP;
++typedef enum VTX_FETCH_TYPE {
++	VTX_FetchType_VertexData                         = 0x0,
++	VTX_FetchType_InstanceData                       = 0x1,
++	VTX_FetchType_NoIndexOffset                      = 0x2,
++	VTX_FetchType_RESERVED_3                         = 0x3,
++} VTX_FETCH_TYPE;
++typedef enum VTX_FORMAT_COMP_ALL {
++	VTX_FormatCompAll_Unsigned                       = 0x0,
++	VTX_FormatCompAll_Signed                         = 0x1,
++} VTX_FORMAT_COMP_ALL;
++typedef enum VTX_MEM_REQUEST_SIZE {
++	VTX_MemRequestSize_32B                           = 0x0,
++	VTX_MemRequestSize_64B                           = 0x1,
++} VTX_MEM_REQUEST_SIZE;
++typedef enum TVX_DATA_FORMAT {
++	TVX_FMT_INVALID                                  = 0x0,
++	TVX_FMT_8                                        = 0x1,
++	TVX_FMT_4_4                                      = 0x2,
++	TVX_FMT_3_3_2                                    = 0x3,
++	TVX_FMT_RESERVED_4                               = 0x4,
++	TVX_FMT_16                                       = 0x5,
++	TVX_FMT_16_FLOAT                                 = 0x6,
++	TVX_FMT_8_8                                      = 0x7,
++	TVX_FMT_5_6_5                                    = 0x8,
++	TVX_FMT_6_5_5                                    = 0x9,
++	TVX_FMT_1_5_5_5                                  = 0xa,
++	TVX_FMT_4_4_4_4                                  = 0xb,
++	TVX_FMT_5_5_5_1                                  = 0xc,
++	TVX_FMT_32                                       = 0xd,
++	TVX_FMT_32_FLOAT                                 = 0xe,
++	TVX_FMT_16_16                                    = 0xf,
++	TVX_FMT_16_16_FLOAT                              = 0x10,
++	TVX_FMT_8_24                                     = 0x11,
++	TVX_FMT_8_24_FLOAT                               = 0x12,
++	TVX_FMT_24_8                                     = 0x13,
++	TVX_FMT_24_8_FLOAT                               = 0x14,
++	TVX_FMT_10_11_11                                 = 0x15,
++	TVX_FMT_10_11_11_FLOAT                           = 0x16,
++	TVX_FMT_11_11_10                                 = 0x17,
++	TVX_FMT_11_11_10_FLOAT                           = 0x18,
++	TVX_FMT_2_10_10_10                               = 0x19,
++	TVX_FMT_8_8_8_8                                  = 0x1a,
++	TVX_FMT_10_10_10_2                               = 0x1b,
++	TVX_FMT_X24_8_32_FLOAT                           = 0x1c,
++	TVX_FMT_32_32                                    = 0x1d,
++	TVX_FMT_32_32_FLOAT                              = 0x1e,
++	TVX_FMT_16_16_16_16                              = 0x1f,
++	TVX_FMT_16_16_16_16_FLOAT                        = 0x20,
++	TVX_FMT_RESERVED_33                              = 0x21,
++	TVX_FMT_32_32_32_32                              = 0x22,
++	TVX_FMT_32_32_32_32_FLOAT                        = 0x23,
++	TVX_FMT_RESERVED_36                              = 0x24,
++	TVX_FMT_1                                        = 0x25,
++	TVX_FMT_1_REVERSED                               = 0x26,
++	TVX_FMT_GB_GR                                    = 0x27,
++	TVX_FMT_BG_RG                                    = 0x28,
++	TVX_FMT_32_AS_8                                  = 0x29,
++	TVX_FMT_32_AS_8_8                                = 0x2a,
++	TVX_FMT_5_9_9_9_SHAREDEXP                        = 0x2b,
++	TVX_FMT_8_8_8                                    = 0x2c,
++	TVX_FMT_16_16_16                                 = 0x2d,
++	TVX_FMT_16_16_16_FLOAT                           = 0x2e,
++	TVX_FMT_32_32_32                                 = 0x2f,
++	TVX_FMT_32_32_32_FLOAT                           = 0x30,
++	TVX_FMT_BC1                                      = 0x31,
++	TVX_FMT_BC2                                      = 0x32,
++	TVX_FMT_BC3                                      = 0x33,
++	TVX_FMT_BC4                                      = 0x34,
++	TVX_FMT_BC5                                      = 0x35,
++	TVX_FMT_APC0                                     = 0x36,
++	TVX_FMT_APC1                                     = 0x37,
++	TVX_FMT_APC2                                     = 0x38,
++	TVX_FMT_APC3                                     = 0x39,
++	TVX_FMT_APC4                                     = 0x3a,
++	TVX_FMT_APC5                                     = 0x3b,
++	TVX_FMT_APC6                                     = 0x3c,
++	TVX_FMT_APC7                                     = 0x3d,
++	TVX_FMT_CTX1                                     = 0x3e,
++	TVX_FMT_RESERVED_63                              = 0x3f,
++} TVX_DATA_FORMAT;
++typedef enum TVX_DST_SEL {
++	TVX_DstSel_X                                     = 0x0,
++	TVX_DstSel_Y                                     = 0x1,
++	TVX_DstSel_Z                                     = 0x2,
++	TVX_DstSel_W                                     = 0x3,
++	TVX_DstSel_0f                                    = 0x4,
++	TVX_DstSel_1f                                    = 0x5,
++	TVX_DstSel_RESERVED_6                            = 0x6,
++	TVX_DstSel_Mask                                  = 0x7,
++} TVX_DST_SEL;
++typedef enum TVX_ENDIAN_SWAP {
++	TVX_EndianSwap_None                              = 0x0,
++	TVX_EndianSwap_8in16                             = 0x1,
++	TVX_EndianSwap_8in32                             = 0x2,
++	TVX_EndianSwap_8in64                             = 0x3,
++} TVX_ENDIAN_SWAP;
++typedef enum TVX_INST {
++	TVX_Inst_NormalVertexFetch                       = 0x0,
++	TVX_Inst_SemanticVertexFetch                     = 0x1,
++	TVX_Inst_RESERVED_2                              = 0x2,
++	TVX_Inst_LD                                      = 0x3,
++	TVX_Inst_GetTextureResInfo                       = 0x4,
++	TVX_Inst_GetNumberOfSamples                      = 0x5,
++	TVX_Inst_GetLOD                                  = 0x6,
++	TVX_Inst_GetGradientsH                           = 0x7,
++	TVX_Inst_GetGradientsV                           = 0x8,
++	TVX_Inst_SetTextureOffsets                       = 0x9,
++	TVX_Inst_KeepGradients                           = 0xa,
++	TVX_Inst_SetGradientsH                           = 0xb,
++	TVX_Inst_SetGradientsV                           = 0xc,
++	TVX_Inst_Pass                                    = 0xd,
++	TVX_Inst_GetBufferResInfo                        = 0xe,
++	TVX_Inst_RESERVED_15                             = 0xf,
++	TVX_Inst_Sample                                  = 0x10,
++	TVX_Inst_Sample_L                                = 0x11,
++	TVX_Inst_Sample_LB                               = 0x12,
++	TVX_Inst_Sample_LZ                               = 0x13,
++	TVX_Inst_Sample_G                                = 0x14,
++	TVX_Inst_Gather4                                 = 0x15,
++	TVX_Inst_Sample_G_LB                             = 0x16,
++	TVX_Inst_Gather4_O                               = 0x17,
++	TVX_Inst_Sample_C                                = 0x18,
++	TVX_Inst_Sample_C_L                              = 0x19,
++	TVX_Inst_Sample_C_LB                             = 0x1a,
++	TVX_Inst_Sample_C_LZ                             = 0x1b,
++	TVX_Inst_Sample_C_G                              = 0x1c,
++	TVX_Inst_Gather4_C                               = 0x1d,
++	TVX_Inst_Sample_C_G_LB                           = 0x1e,
++	TVX_Inst_Gather4_C_O                             = 0x1f,
++} TVX_INST;
++typedef enum TVX_NUM_FORMAT_ALL {
++	TVX_NumFormatAll_Norm                            = 0x0,
++	TVX_NumFormatAll_Int                             = 0x1,
++	TVX_NumFormatAll_Scaled                          = 0x2,
++	TVX_NumFormatAll_RESERVED_3                      = 0x3,
++} TVX_NUM_FORMAT_ALL;
++typedef enum TVX_SRC_SEL {
++	TVX_SrcSel_X                                     = 0x0,
++	TVX_SrcSel_Y                                     = 0x1,
++	TVX_SrcSel_Z                                     = 0x2,
++	TVX_SrcSel_W                                     = 0x3,
++	TVX_SrcSel_0f                                    = 0x4,
++	TVX_SrcSel_1f                                    = 0x5,
++} TVX_SRC_SEL;
++typedef enum TVX_SRF_MODE_ALL {
++	TVX_SRFModeAll_ZCMO                              = 0x0,
++	TVX_SRFModeAll_NZ                                = 0x1,
++} TVX_SRF_MODE_ALL;
++typedef enum TVX_TYPE {
++	TVX_Type_InvalidTextureResource                  = 0x0,
++	TVX_Type_InvalidVertexBuffer                     = 0x1,
++	TVX_Type_ValidTextureResource                    = 0x2,
++	TVX_Type_ValidVertexBuffer                       = 0x3,
++} TVX_TYPE;
++typedef enum TC_OP_MASKS {
++	TC_OP_MASK_FLUSH_DENROM                          = 0x8,
++	TC_OP_MASK_64                                    = 0x20,
++	TC_OP_MASK_NO_RTN                                = 0x40,
++} TC_OP_MASKS;
++typedef enum TC_OP {
++	TC_OP_READ                                       = 0x0,
++	TC_OP_ATOMIC_FCMPSWAP_RTN_32                     = 0x1,
++	TC_OP_ATOMIC_FMIN_RTN_32                         = 0x2,
++	TC_OP_ATOMIC_FMAX_RTN_32                         = 0x3,
++	TC_OP_RESERVED_FOP_RTN_32_0                      = 0x4,
++	TC_OP_RESERVED_FOP_RTN_32_1                      = 0x5,
++	TC_OP_RESERVED_FOP_RTN_32_2                      = 0x6,
++	TC_OP_ATOMIC_SWAP_RTN_32                         = 0x7,
++	TC_OP_ATOMIC_CMPSWAP_RTN_32                      = 0x8,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32        = 0x9,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32            = 0xa,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32            = 0xb,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0         = 0xc,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1         = 0xd,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2         = 0xe,
++	TC_OP_ATOMIC_ADD_RTN_32                          = 0xf,
++	TC_OP_ATOMIC_SUB_RTN_32                          = 0x10,
++	TC_OP_ATOMIC_SMIN_RTN_32                         = 0x11,
++	TC_OP_ATOMIC_UMIN_RTN_32                         = 0x12,
++	TC_OP_ATOMIC_SMAX_RTN_32                         = 0x13,
++	TC_OP_ATOMIC_UMAX_RTN_32                         = 0x14,
++	TC_OP_ATOMIC_AND_RTN_32                          = 0x15,
++	TC_OP_ATOMIC_OR_RTN_32                           = 0x16,
++	TC_OP_ATOMIC_XOR_RTN_32                          = 0x17,
++	TC_OP_ATOMIC_INC_RTN_32                          = 0x18,
++	TC_OP_ATOMIC_DEC_RTN_32                          = 0x19,
++	TC_OP_WBINVL1_VOL                                = 0x1a,
++	TC_OP_WBINVL1_SD                                 = 0x1b,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_0                = 0x1c,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_1                = 0x1d,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_2                = 0x1e,
++	TC_OP_RESERVED_NON_FLOAT_RTN_32_3                = 0x1f,
++	TC_OP_WRITE                                      = 0x20,
++	TC_OP_ATOMIC_FCMPSWAP_RTN_64                     = 0x21,
++	TC_OP_ATOMIC_FMIN_RTN_64                         = 0x22,
++	TC_OP_ATOMIC_FMAX_RTN_64                         = 0x23,
++	TC_OP_RESERVED_FOP_RTN_64_0                      = 0x24,
++	TC_OP_RESERVED_FOP_RTN_64_1                      = 0x25,
++	TC_OP_RESERVED_FOP_RTN_64_2                      = 0x26,
++	TC_OP_ATOMIC_SWAP_RTN_64                         = 0x27,
++	TC_OP_ATOMIC_CMPSWAP_RTN_64                      = 0x28,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64        = 0x29,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64            = 0x2a,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64            = 0x2b,
++	TC_OP_WBINVL2_SD                                 = 0x2c,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0         = 0x2d,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1         = 0x2e,
++	TC_OP_ATOMIC_ADD_RTN_64                          = 0x2f,
++	TC_OP_ATOMIC_SUB_RTN_64                          = 0x30,
++	TC_OP_ATOMIC_SMIN_RTN_64                         = 0x31,
++	TC_OP_ATOMIC_UMIN_RTN_64                         = 0x32,
++	TC_OP_ATOMIC_SMAX_RTN_64                         = 0x33,
++	TC_OP_ATOMIC_UMAX_RTN_64                         = 0x34,
++	TC_OP_ATOMIC_AND_RTN_64                          = 0x35,
++	TC_OP_ATOMIC_OR_RTN_64                           = 0x36,
++	TC_OP_ATOMIC_XOR_RTN_64                          = 0x37,
++	TC_OP_ATOMIC_INC_RTN_64                          = 0x38,
++	TC_OP_ATOMIC_DEC_RTN_64                          = 0x39,
++	TC_OP_WBL2_NC                                    = 0x3a,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_0                = 0x3b,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_1                = 0x3c,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_2                = 0x3d,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_3                = 0x3e,
++	TC_OP_RESERVED_NON_FLOAT_RTN_64_4                = 0x3f,
++	TC_OP_WBINVL1                                    = 0x40,
++	TC_OP_ATOMIC_FCMPSWAP_32                         = 0x41,
++	TC_OP_ATOMIC_FMIN_32                             = 0x42,
++	TC_OP_ATOMIC_FMAX_32                             = 0x43,
++	TC_OP_RESERVED_FOP_32_0                          = 0x44,
++	TC_OP_RESERVED_FOP_32_1                          = 0x45,
++	TC_OP_RESERVED_FOP_32_2                          = 0x46,
++	TC_OP_ATOMIC_SWAP_32                             = 0x47,
++	TC_OP_ATOMIC_CMPSWAP_32                          = 0x48,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32            = 0x49,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32                = 0x4a,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32                = 0x4b,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0             = 0x4c,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1             = 0x4d,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2             = 0x4e,
++	TC_OP_ATOMIC_ADD_32                              = 0x4f,
++	TC_OP_ATOMIC_SUB_32                              = 0x50,
++	TC_OP_ATOMIC_SMIN_32                             = 0x51,
++	TC_OP_ATOMIC_UMIN_32                             = 0x52,
++	TC_OP_ATOMIC_SMAX_32                             = 0x53,
++	TC_OP_ATOMIC_UMAX_32                             = 0x54,
++	TC_OP_ATOMIC_AND_32                              = 0x55,
++	TC_OP_ATOMIC_OR_32                               = 0x56,
++	TC_OP_ATOMIC_XOR_32                              = 0x57,
++	TC_OP_ATOMIC_INC_32                              = 0x58,
++	TC_OP_ATOMIC_DEC_32                              = 0x59,
++	TC_OP_INVL2_NC                                   = 0x5a,
++	TC_OP_RESERVED_NON_FLOAT_32_0                    = 0x5b,
++	TC_OP_RESERVED_NON_FLOAT_32_1                    = 0x5c,
++	TC_OP_RESERVED_NON_FLOAT_32_2                    = 0x5d,
++	TC_OP_RESERVED_NON_FLOAT_32_3                    = 0x5e,
++	TC_OP_RESERVED_NON_FLOAT_32_4                    = 0x5f,
++	TC_OP_WBINVL2                                    = 0x60,
++	TC_OP_ATOMIC_FCMPSWAP_64                         = 0x61,
++	TC_OP_ATOMIC_FMIN_64                             = 0x62,
++	TC_OP_ATOMIC_FMAX_64                             = 0x63,
++	TC_OP_RESERVED_FOP_64_0                          = 0x64,
++	TC_OP_RESERVED_FOP_64_1                          = 0x65,
++	TC_OP_RESERVED_FOP_64_2                          = 0x66,
++	TC_OP_ATOMIC_SWAP_64                             = 0x67,
++	TC_OP_ATOMIC_CMPSWAP_64                          = 0x68,
++	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64            = 0x69,
++	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64                = 0x6a,
++	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64                = 0x6b,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0             = 0x6c,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1             = 0x6d,
++	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2             = 0x6e,
++	TC_OP_ATOMIC_ADD_64                              = 0x6f,
++	TC_OP_ATOMIC_SUB_64                              = 0x70,
++	TC_OP_ATOMIC_SMIN_64                             = 0x71,
++	TC_OP_ATOMIC_UMIN_64                             = 0x72,
++	TC_OP_ATOMIC_SMAX_64                             = 0x73,
++	TC_OP_ATOMIC_UMAX_64                             = 0x74,
++	TC_OP_ATOMIC_AND_64                              = 0x75,
++	TC_OP_ATOMIC_OR_64                               = 0x76,
++	TC_OP_ATOMIC_XOR_64                              = 0x77,
++	TC_OP_ATOMIC_INC_64                              = 0x78,
++	TC_OP_ATOMIC_DEC_64                              = 0x79,
++	TC_OP_WBINVL2_NC                                 = 0x7a,
++	TC_OP_RESERVED_NON_FLOAT_64_0                    = 0x7b,
++	TC_OP_RESERVED_NON_FLOAT_64_1                    = 0x7c,
++	TC_OP_RESERVED_NON_FLOAT_64_2                    = 0x7d,
++	TC_OP_RESERVED_NON_FLOAT_64_3                    = 0x7e,
++	TC_OP_RESERVED_NON_FLOAT_64_4                    = 0x7f,
++} TC_OP;
++typedef enum TC_CHUB_REQ_CREDITS_ENUM {
++	TC_CHUB_REQ_CREDITS                              = 0x10,
++} TC_CHUB_REQ_CREDITS_ENUM;
++typedef enum CHUB_TC_RET_CREDITS_ENUM {
++	CHUB_TC_RET_CREDITS                              = 0x20,
++} CHUB_TC_RET_CREDITS_ENUM;
++typedef enum TC_NACKS {
++	TC_NACK_NO_FAULT                                 = 0x0,
++	TC_NACK_PAGE_FAULT                               = 0x1,
++	TC_NACK_PROTECTION_FAULT                         = 0x2,
++	TC_NACK_DATA_ERROR                               = 0x3,
++} TC_NACKS;
++typedef enum TCC_PERF_SEL {
++	TCC_PERF_SEL_NONE                                = 0x0,
++	TCC_PERF_SEL_CYCLE                               = 0x1,
++	TCC_PERF_SEL_BUSY                                = 0x2,
++	TCC_PERF_SEL_REQ                                 = 0x3,
++	TCC_PERF_SEL_STREAMING_REQ                       = 0x4,
++	TCC_PERF_SEL_EXE_REQ                             = 0x5,
++	TCC_PERF_SEL_COMPRESSED_REQ                      = 0x6,
++	TCC_PERF_SEL_COMPRESSED_0_REQ                    = 0x7,
++	TCC_PERF_SEL_METADATA_REQ                        = 0x8,
++	TCC_PERF_SEL_NC_VIRTUAL_REQ                      = 0x9,
++	TCC_PERF_SEL_NC_PHYSICAL_REQ                     = 0xa,
++	TCC_PERF_SEL_UC_VIRTUAL_REQ                      = 0xb,
++	TCC_PERF_SEL_UC_PHYSICAL_REQ                     = 0xc,
++	TCC_PERF_SEL_CC_PHYSICAL_REQ                     = 0xd,
++	TCC_PERF_SEL_PROBE                               = 0xe,
++	TCC_PERF_SEL_READ                                = 0xf,
++	TCC_PERF_SEL_WRITE                               = 0x10,
++	TCC_PERF_SEL_ATOMIC                              = 0x11,
++	TCC_PERF_SEL_HIT                                 = 0x12,
++	TCC_PERF_SEL_MISS                                = 0x13,
++	TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT                = 0x14,
++	TCC_PERF_SEL_FULLY_WRITTEN_HIT                   = 0x15,
++	TCC_PERF_SEL_WRITEBACK                           = 0x16,
++	TCC_PERF_SEL_LATENCY_FIFO_FULL                   = 0x17,
++	TCC_PERF_SEL_SRC_FIFO_FULL                       = 0x18,
++	TCC_PERF_SEL_HOLE_FIFO_FULL                      = 0x19,
++	TCC_PERF_SEL_MC_WRREQ                            = 0x1a,
++	TCC_PERF_SEL_MC_WRREQ_UNCACHED                   = 0x1b,
++	TCC_PERF_SEL_MC_WRREQ_STALL                      = 0x1c,
++	TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL               = 0x1d,
++	TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL              = 0x1e,
++	TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL            = 0x1f,
++	TCC_PERF_SEL_MC_WRREQ_LEVEL                      = 0x20,
++	TCC_PERF_SEL_MC_ATOMIC                           = 0x21,
++	TCC_PERF_SEL_MC_ATOMIC_LEVEL                     = 0x22,
++	TCC_PERF_SEL_MC_RDREQ                            = 0x23,
++	TCC_PERF_SEL_MC_RDREQ_UNCACHED                   = 0x24,
++	TCC_PERF_SEL_MC_RDREQ_MDC                        = 0x25,
++	TCC_PERF_SEL_MC_RDREQ_COMPRESSED                 = 0x26,
++	TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL               = 0x27,
++	TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL              = 0x28,
++	TCC_PERF_SEL_MC_RDREQ_LEVEL                      = 0x29,
++	TCC_PERF_SEL_TAG_STALL                           = 0x2a,
++	TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL       = 0x2b,
++	TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x2c,
++	TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d,
++	TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e,
++	TCC_PERF_SEL_TAG_PROBE_STALL                     = 0x2f,
++	TCC_PERF_SEL_TAG_PROBE_FILTER_STALL              = 0x30,
++	TCC_PERF_SEL_READ_RETURN_TIMEOUT                 = 0x31,
++	TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT              = 0x32,
++	TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE             = 0x33,
++	TCC_PERF_SEL_BUBBLE                              = 0x34,
++	TCC_PERF_SEL_RETURN_ACK                          = 0x35,
++	TCC_PERF_SEL_RETURN_DATA                         = 0x36,
++	TCC_PERF_SEL_RETURN_HOLE                         = 0x37,
++	TCC_PERF_SEL_RETURN_ACK_HOLE                     = 0x38,
++	TCC_PERF_SEL_IB_REQ                              = 0x39,
++	TCC_PERF_SEL_IB_STALL                            = 0x3a,
++	TCC_PERF_SEL_IB_TAG_STALL                        = 0x3b,
++	TCC_PERF_SEL_IB_MDC_STALL                        = 0x3c,
++	TCC_PERF_SEL_TCA_LEVEL                           = 0x3d,
++	TCC_PERF_SEL_HOLE_LEVEL                          = 0x3e,
++	TCC_PERF_SEL_MC_RDRET_NACK                       = 0x3f,
++	TCC_PERF_SEL_MC_WRRET_NACK                       = 0x40,
++	TCC_PERF_SEL_NORMAL_WRITEBACK                    = 0x41,
++	TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK             = 0x42,
++	TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK             = 0x43,
++	TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK          = 0x44,
++	TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK          = 0x45,
++	TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK              = 0x46,
++	TCC_PERF_SEL_NORMAL_EVICT                        = 0x47,
++	TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT                 = 0x48,
++	TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT                = 0x49,
++	TCC_PERF_SEL_TC_OP_WBINVL2_EVICT                 = 0x4a,
++	TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT              = 0x4b,
++	TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT              = 0x4c,
++	TCC_PERF_SEL_ALL_TC_OP_INV_EVICT                 = 0x4d,
++	TCC_PERF_SEL_PROBE_EVICT                         = 0x4e,
++	TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE                 = 0x4f,
++	TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE                = 0x50,
++	TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE                 = 0x51,
++	TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE              = 0x52,
++	TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE              = 0x53,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE           = 0x54,
++	TCC_PERF_SEL_TC_OP_WBL2_NC_START                 = 0x55,
++	TCC_PERF_SEL_TC_OP_INVL2_NC_START                = 0x56,
++	TCC_PERF_SEL_TC_OP_WBINVL2_START                 = 0x57,
++	TCC_PERF_SEL_TC_OP_WBINVL2_NC_START              = 0x58,
++	TCC_PERF_SEL_TC_OP_WBINVL2_SD_START              = 0x59,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START           = 0x5a,
++	TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH                = 0x5b,
++	TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH               = 0x5c,
++	TCC_PERF_SEL_TC_OP_WBINVL2_FINISH                = 0x5d,
++	TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH             = 0x5e,
++	TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH             = 0x5f,
++	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH          = 0x60,
++	TCC_PERF_SEL_MDC_REQ                             = 0x61,
++	TCC_PERF_SEL_MDC_LEVEL                           = 0x62,
++	TCC_PERF_SEL_MDC_TAG_HIT                         = 0x63,
++	TCC_PERF_SEL_MDC_SECTOR_HIT                      = 0x64,
++	TCC_PERF_SEL_MDC_SECTOR_MISS                     = 0x65,
++	TCC_PERF_SEL_MDC_TAG_STALL                       = 0x66,
++	TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67,
++	TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68,
++	TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69,
++	TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION     = 0x6a,
++	TCC_PERF_SEL_PROBE_FILTER_DISABLED               = 0x6b,
++	TCC_PERF_SEL_CLIENT0_REQ                         = 0x80,
++	TCC_PERF_SEL_CLIENT1_REQ                         = 0x81,
++	TCC_PERF_SEL_CLIENT2_REQ                         = 0x82,
++	TCC_PERF_SEL_CLIENT3_REQ                         = 0x83,
++	TCC_PERF_SEL_CLIENT4_REQ                         = 0x84,
++	TCC_PERF_SEL_CLIENT5_REQ                         = 0x85,
++	TCC_PERF_SEL_CLIENT6_REQ                         = 0x86,
++	TCC_PERF_SEL_CLIENT7_REQ                         = 0x87,
++	TCC_PERF_SEL_CLIENT8_REQ                         = 0x88,
++	TCC_PERF_SEL_CLIENT9_REQ                         = 0x89,
++	TCC_PERF_SEL_CLIENT10_REQ                        = 0x8a,
++	TCC_PERF_SEL_CLIENT11_REQ                        = 0x8b,
++	TCC_PERF_SEL_CLIENT12_REQ                        = 0x8c,
++	TCC_PERF_SEL_CLIENT13_REQ                        = 0x8d,
++	TCC_PERF_SEL_CLIENT14_REQ                        = 0x8e,
++	TCC_PERF_SEL_CLIENT15_REQ                        = 0x8f,
++	TCC_PERF_SEL_CLIENT16_REQ                        = 0x90,
++	TCC_PERF_SEL_CLIENT17_REQ                        = 0x91,
++	TCC_PERF_SEL_CLIENT18_REQ                        = 0x92,
++	TCC_PERF_SEL_CLIENT19_REQ                        = 0x93,
++	TCC_PERF_SEL_CLIENT20_REQ                        = 0x94,
++	TCC_PERF_SEL_CLIENT21_REQ                        = 0x95,
++	TCC_PERF_SEL_CLIENT22_REQ                        = 0x96,
++	TCC_PERF_SEL_CLIENT23_REQ                        = 0x97,
++	TCC_PERF_SEL_CLIENT24_REQ                        = 0x98,
++	TCC_PERF_SEL_CLIENT25_REQ                        = 0x99,
++	TCC_PERF_SEL_CLIENT26_REQ                        = 0x9a,
++	TCC_PERF_SEL_CLIENT27_REQ                        = 0x9b,
++	TCC_PERF_SEL_CLIENT28_REQ                        = 0x9c,
++	TCC_PERF_SEL_CLIENT29_REQ                        = 0x9d,
++	TCC_PERF_SEL_CLIENT30_REQ                        = 0x9e,
++	TCC_PERF_SEL_CLIENT31_REQ                        = 0x9f,
++	TCC_PERF_SEL_CLIENT32_REQ                        = 0xa0,
++	TCC_PERF_SEL_CLIENT33_REQ                        = 0xa1,
++	TCC_PERF_SEL_CLIENT34_REQ                        = 0xa2,
++	TCC_PERF_SEL_CLIENT35_REQ                        = 0xa3,
++	TCC_PERF_SEL_CLIENT36_REQ                        = 0xa4,
++	TCC_PERF_SEL_CLIENT37_REQ                        = 0xa5,
++	TCC_PERF_SEL_CLIENT38_REQ                        = 0xa6,
++	TCC_PERF_SEL_CLIENT39_REQ                        = 0xa7,
++	TCC_PERF_SEL_CLIENT40_REQ                        = 0xa8,
++	TCC_PERF_SEL_CLIENT41_REQ                        = 0xa9,
++	TCC_PERF_SEL_CLIENT42_REQ                        = 0xaa,
++	TCC_PERF_SEL_CLIENT43_REQ                        = 0xab,
++	TCC_PERF_SEL_CLIENT44_REQ                        = 0xac,
++	TCC_PERF_SEL_CLIENT45_REQ                        = 0xad,
++	TCC_PERF_SEL_CLIENT46_REQ                        = 0xae,
++	TCC_PERF_SEL_CLIENT47_REQ                        = 0xaf,
++	TCC_PERF_SEL_CLIENT48_REQ                        = 0xb0,
++	TCC_PERF_SEL_CLIENT49_REQ                        = 0xb1,
++	TCC_PERF_SEL_CLIENT50_REQ                        = 0xb2,
++	TCC_PERF_SEL_CLIENT51_REQ                        = 0xb3,
++	TCC_PERF_SEL_CLIENT52_REQ                        = 0xb4,
++	TCC_PERF_SEL_CLIENT53_REQ                        = 0xb5,
++	TCC_PERF_SEL_CLIENT54_REQ                        = 0xb6,
++	TCC_PERF_SEL_CLIENT55_REQ                        = 0xb7,
++	TCC_PERF_SEL_CLIENT56_REQ                        = 0xb8,
++	TCC_PERF_SEL_CLIENT57_REQ                        = 0xb9,
++	TCC_PERF_SEL_CLIENT58_REQ                        = 0xba,
++	TCC_PERF_SEL_CLIENT59_REQ                        = 0xbb,
++	TCC_PERF_SEL_CLIENT60_REQ                        = 0xbc,
++	TCC_PERF_SEL_CLIENT61_REQ                        = 0xbd,
++	TCC_PERF_SEL_CLIENT62_REQ                        = 0xbe,
++	TCC_PERF_SEL_CLIENT63_REQ                        = 0xbf,
++	TCC_PERF_SEL_CLIENT64_REQ                        = 0xc0,
++	TCC_PERF_SEL_CLIENT65_REQ                        = 0xc1,
++	TCC_PERF_SEL_CLIENT66_REQ                        = 0xc2,
++	TCC_PERF_SEL_CLIENT67_REQ                        = 0xc3,
++	TCC_PERF_SEL_CLIENT68_REQ                        = 0xc4,
++	TCC_PERF_SEL_CLIENT69_REQ                        = 0xc5,
++	TCC_PERF_SEL_CLIENT70_REQ                        = 0xc6,
++	TCC_PERF_SEL_CLIENT71_REQ                        = 0xc7,
++	TCC_PERF_SEL_CLIENT72_REQ                        = 0xc8,
++	TCC_PERF_SEL_CLIENT73_REQ                        = 0xc9,
++	TCC_PERF_SEL_CLIENT74_REQ                        = 0xca,
++	TCC_PERF_SEL_CLIENT75_REQ                        = 0xcb,
++	TCC_PERF_SEL_CLIENT76_REQ                        = 0xcc,
++	TCC_PERF_SEL_CLIENT77_REQ                        = 0xcd,
++	TCC_PERF_SEL_CLIENT78_REQ                        = 0xce,
++	TCC_PERF_SEL_CLIENT79_REQ                        = 0xcf,
++	TCC_PERF_SEL_CLIENT80_REQ                        = 0xd0,
++	TCC_PERF_SEL_CLIENT81_REQ                        = 0xd1,
++	TCC_PERF_SEL_CLIENT82_REQ                        = 0xd2,
++	TCC_PERF_SEL_CLIENT83_REQ                        = 0xd3,
++	TCC_PERF_SEL_CLIENT84_REQ                        = 0xd4,
++	TCC_PERF_SEL_CLIENT85_REQ                        = 0xd5,
++	TCC_PERF_SEL_CLIENT86_REQ                        = 0xd6,
++	TCC_PERF_SEL_CLIENT87_REQ                        = 0xd7,
++	TCC_PERF_SEL_CLIENT88_REQ                        = 0xd8,
++	TCC_PERF_SEL_CLIENT89_REQ                        = 0xd9,
++	TCC_PERF_SEL_CLIENT90_REQ                        = 0xda,
++	TCC_PERF_SEL_CLIENT91_REQ                        = 0xdb,
++	TCC_PERF_SEL_CLIENT92_REQ                        = 0xdc,
++	TCC_PERF_SEL_CLIENT93_REQ                        = 0xdd,
++	TCC_PERF_SEL_CLIENT94_REQ                        = 0xde,
++	TCC_PERF_SEL_CLIENT95_REQ                        = 0xdf,
++	TCC_PERF_SEL_CLIENT96_REQ                        = 0xe0,
++	TCC_PERF_SEL_CLIENT97_REQ                        = 0xe1,
++	TCC_PERF_SEL_CLIENT98_REQ                        = 0xe2,
++	TCC_PERF_SEL_CLIENT99_REQ                        = 0xe3,
++	TCC_PERF_SEL_CLIENT100_REQ                       = 0xe4,
++	TCC_PERF_SEL_CLIENT101_REQ                       = 0xe5,
++	TCC_PERF_SEL_CLIENT102_REQ                       = 0xe6,
++	TCC_PERF_SEL_CLIENT103_REQ                       = 0xe7,
++	TCC_PERF_SEL_CLIENT104_REQ                       = 0xe8,
++	TCC_PERF_SEL_CLIENT105_REQ                       = 0xe9,
++	TCC_PERF_SEL_CLIENT106_REQ                       = 0xea,
++	TCC_PERF_SEL_CLIENT107_REQ                       = 0xeb,
++	TCC_PERF_SEL_CLIENT108_REQ                       = 0xec,
++	TCC_PERF_SEL_CLIENT109_REQ                       = 0xed,
++	TCC_PERF_SEL_CLIENT110_REQ                       = 0xee,
++	TCC_PERF_SEL_CLIENT111_REQ                       = 0xef,
++	TCC_PERF_SEL_CLIENT112_REQ                       = 0xf0,
++	TCC_PERF_SEL_CLIENT113_REQ                       = 0xf1,
++	TCC_PERF_SEL_CLIENT114_REQ                       = 0xf2,
++	TCC_PERF_SEL_CLIENT115_REQ                       = 0xf3,
++	TCC_PERF_SEL_CLIENT116_REQ                       = 0xf4,
++	TCC_PERF_SEL_CLIENT117_REQ                       = 0xf5,
++	TCC_PERF_SEL_CLIENT118_REQ                       = 0xf6,
++	TCC_PERF_SEL_CLIENT119_REQ                       = 0xf7,
++	TCC_PERF_SEL_CLIENT120_REQ                       = 0xf8,
++	TCC_PERF_SEL_CLIENT121_REQ                       = 0xf9,
++	TCC_PERF_SEL_CLIENT122_REQ                       = 0xfa,
++	TCC_PERF_SEL_CLIENT123_REQ                       = 0xfb,
++	TCC_PERF_SEL_CLIENT124_REQ                       = 0xfc,
++	TCC_PERF_SEL_CLIENT125_REQ                       = 0xfd,
++	TCC_PERF_SEL_CLIENT126_REQ                       = 0xfe,
++	TCC_PERF_SEL_CLIENT127_REQ                       = 0xff,
++} TCC_PERF_SEL;
++typedef enum TCA_PERF_SEL {
++	TCA_PERF_SEL_NONE                                = 0x0,
++	TCA_PERF_SEL_CYCLE                               = 0x1,
++	TCA_PERF_SEL_BUSY                                = 0x2,
++	TCA_PERF_SEL_FORCED_HOLE_TCC0                    = 0x3,
++	TCA_PERF_SEL_FORCED_HOLE_TCC1                    = 0x4,
++	TCA_PERF_SEL_FORCED_HOLE_TCC2                    = 0x5,
++	TCA_PERF_SEL_FORCED_HOLE_TCC3                    = 0x6,
++	TCA_PERF_SEL_FORCED_HOLE_TCC4                    = 0x7,
++	TCA_PERF_SEL_FORCED_HOLE_TCC5                    = 0x8,
++	TCA_PERF_SEL_FORCED_HOLE_TCC6                    = 0x9,
++	TCA_PERF_SEL_FORCED_HOLE_TCC7                    = 0xa,
++	TCA_PERF_SEL_REQ_TCC0                            = 0xb,
++	TCA_PERF_SEL_REQ_TCC1                            = 0xc,
++	TCA_PERF_SEL_REQ_TCC2                            = 0xd,
++	TCA_PERF_SEL_REQ_TCC3                            = 0xe,
++	TCA_PERF_SEL_REQ_TCC4                            = 0xf,
++	TCA_PERF_SEL_REQ_TCC5                            = 0x10,
++	TCA_PERF_SEL_REQ_TCC6                            = 0x11,
++	TCA_PERF_SEL_REQ_TCC7                            = 0x12,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0            = 0x13,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1            = 0x14,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2            = 0x15,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3            = 0x16,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4            = 0x17,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5            = 0x18,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6            = 0x19,
++	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7            = 0x1a,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC0                 = 0x1b,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC1                 = 0x1c,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC2                 = 0x1d,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC3                 = 0x1e,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC4                 = 0x1f,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC5                 = 0x20,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC6                 = 0x21,
++	TCA_PERF_SEL_CROSSBAR_STALL_TCC7                 = 0x22,
++} TCA_PERF_SEL;
++typedef enum TA_TC_ADDR_MODES {
++	TA_TC_ADDR_MODE_DEFAULT                          = 0x0,
++	TA_TC_ADDR_MODE_COMP0                            = 0x1,
++	TA_TC_ADDR_MODE_COMP1                            = 0x2,
++	TA_TC_ADDR_MODE_COMP2                            = 0x3,
++	TA_TC_ADDR_MODE_COMP3                            = 0x4,
++	TA_TC_ADDR_MODE_UNALIGNED                        = 0x5,
++	TA_TC_ADDR_MODE_BORDER_COLOR                     = 0x6,
++} TA_TC_ADDR_MODES;
++typedef enum TA_PERFCOUNT_SEL {
++	TA_PERF_SEL_NULL                                 = 0x0,
++	TA_PERF_SEL_sh_fifo_busy                         = 0x1,
++	TA_PERF_SEL_sh_fifo_cmd_busy                     = 0x2,
++	TA_PERF_SEL_sh_fifo_addr_busy                    = 0x3,
++	TA_PERF_SEL_sh_fifo_data_busy                    = 0x4,
++	TA_PERF_SEL_sh_fifo_data_sfifo_busy              = 0x5,
++	TA_PERF_SEL_sh_fifo_data_tfifo_busy              = 0x6,
++	TA_PERF_SEL_gradient_busy                        = 0x7,
++	TA_PERF_SEL_gradient_fifo_busy                   = 0x8,
++	TA_PERF_SEL_lod_busy                             = 0x9,
++	TA_PERF_SEL_lod_fifo_busy                        = 0xa,
++	TA_PERF_SEL_addresser_busy                       = 0xb,
++	TA_PERF_SEL_addresser_fifo_busy                  = 0xc,
++	TA_PERF_SEL_aligner_busy                         = 0xd,
++	TA_PERF_SEL_write_path_busy                      = 0xe,
++	TA_PERF_SEL_ta_busy                              = 0xf,
++	TA_PERF_SEL_sq_ta_cmd_cycles                     = 0x10,
++	TA_PERF_SEL_sp_ta_addr_cycles                    = 0x11,
++	TA_PERF_SEL_sp_ta_data_cycles                    = 0x12,
++	TA_PERF_SEL_ta_fa_data_state_cycles              = 0x13,
++	TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles   = 0x14,
++	TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles   = 0x15,
++	TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
++	TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
++	TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
++	TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
++	TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
++	TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
++	TA_PERF_SEL_RESERVED_28                          = 0x1c,
++	TA_PERF_SEL_RESERVED_29                          = 0x1d,
++	TA_PERF_SEL_sh_fifo_addr_cycles                  = 0x1e,
++	TA_PERF_SEL_sh_fifo_data_cycles                  = 0x1f,
++	TA_PERF_SEL_total_wavefronts                     = 0x20,
++	TA_PERF_SEL_gradient_cycles                      = 0x21,
++	TA_PERF_SEL_walker_cycles                        = 0x22,
++	TA_PERF_SEL_aligner_cycles                       = 0x23,
++	TA_PERF_SEL_image_wavefronts                     = 0x24,
++	TA_PERF_SEL_image_read_wavefronts                = 0x25,
++	TA_PERF_SEL_image_write_wavefronts               = 0x26,
++	TA_PERF_SEL_image_atomic_wavefronts              = 0x27,
++	TA_PERF_SEL_image_total_cycles                   = 0x28,
++	TA_PERF_SEL_RESERVED_41                          = 0x29,
++	TA_PERF_SEL_RESERVED_42                          = 0x2a,
++	TA_PERF_SEL_RESERVED_43                          = 0x2b,
++	TA_PERF_SEL_buffer_wavefronts                    = 0x2c,
++	TA_PERF_SEL_buffer_read_wavefronts               = 0x2d,
++	TA_PERF_SEL_buffer_write_wavefronts              = 0x2e,
++	TA_PERF_SEL_buffer_atomic_wavefronts             = 0x2f,
++	TA_PERF_SEL_buffer_coalescable_wavefronts        = 0x30,
++	TA_PERF_SEL_buffer_total_cycles                  = 0x31,
++	TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
++	TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
++	TA_PERF_SEL_buffer_coalesced_read_cycles         = 0x34,
++	TA_PERF_SEL_buffer_coalesced_write_cycles        = 0x35,
++	TA_PERF_SEL_addr_stalled_by_tc_cycles            = 0x36,
++	TA_PERF_SEL_addr_stalled_by_td_cycles            = 0x37,
++	TA_PERF_SEL_data_stalled_by_tc_cycles            = 0x38,
++	TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
++	TA_PERF_SEL_addresser_stalled_cycles             = 0x3a,
++	TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
++	TA_PERF_SEL_aniso_stalled_cycles                 = 0x3c,
++	TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles   = 0x3d,
++	TA_PERF_SEL_deriv_stalled_cycles                 = 0x3e,
++	TA_PERF_SEL_aniso_gt1_cycle_quads                = 0x3f,
++	TA_PERF_SEL_color_1_cycle_pixels                 = 0x40,
++	TA_PERF_SEL_color_2_cycle_pixels                 = 0x41,
++	TA_PERF_SEL_color_3_cycle_pixels                 = 0x42,
++	TA_PERF_SEL_color_4_cycle_pixels                 = 0x43,
++	TA_PERF_SEL_mip_1_cycle_pixels                   = 0x44,
++	TA_PERF_SEL_mip_2_cycle_pixels                   = 0x45,
++	TA_PERF_SEL_vol_1_cycle_pixels                   = 0x46,
++	TA_PERF_SEL_vol_2_cycle_pixels                   = 0x47,
++	TA_PERF_SEL_bilin_point_1_cycle_pixels           = 0x48,
++	TA_PERF_SEL_mipmap_lod_0_samples                 = 0x49,
++	TA_PERF_SEL_mipmap_lod_1_samples                 = 0x4a,
++	TA_PERF_SEL_mipmap_lod_2_samples                 = 0x4b,
++	TA_PERF_SEL_mipmap_lod_3_samples                 = 0x4c,
++	TA_PERF_SEL_mipmap_lod_4_samples                 = 0x4d,
++	TA_PERF_SEL_mipmap_lod_5_samples                 = 0x4e,
++	TA_PERF_SEL_mipmap_lod_6_samples                 = 0x4f,
++	TA_PERF_SEL_mipmap_lod_7_samples                 = 0x50,
++	TA_PERF_SEL_mipmap_lod_8_samples                 = 0x51,
++	TA_PERF_SEL_mipmap_lod_9_samples                 = 0x52,
++	TA_PERF_SEL_mipmap_lod_10_samples                = 0x53,
++	TA_PERF_SEL_mipmap_lod_11_samples                = 0x54,
++	TA_PERF_SEL_mipmap_lod_12_samples                = 0x55,
++	TA_PERF_SEL_mipmap_lod_13_samples                = 0x56,
++	TA_PERF_SEL_mipmap_lod_14_samples                = 0x57,
++	TA_PERF_SEL_mipmap_invalid_samples               = 0x58,
++	TA_PERF_SEL_aniso_1_cycle_quads                  = 0x59,
++	TA_PERF_SEL_aniso_2_cycle_quads                  = 0x5a,
++	TA_PERF_SEL_aniso_4_cycle_quads                  = 0x5b,
++	TA_PERF_SEL_aniso_6_cycle_quads                  = 0x5c,
++	TA_PERF_SEL_aniso_8_cycle_quads                  = 0x5d,
++	TA_PERF_SEL_aniso_10_cycle_quads                 = 0x5e,
++	TA_PERF_SEL_aniso_12_cycle_quads                 = 0x5f,
++	TA_PERF_SEL_aniso_14_cycle_quads                 = 0x60,
++	TA_PERF_SEL_aniso_16_cycle_quads                 = 0x61,
++	TA_PERF_SEL_write_path_input_cycles              = 0x62,
++	TA_PERF_SEL_write_path_output_cycles             = 0x63,
++	TA_PERF_SEL_flat_wavefronts                      = 0x64,
++	TA_PERF_SEL_flat_read_wavefronts                 = 0x65,
++	TA_PERF_SEL_flat_write_wavefronts                = 0x66,
++	TA_PERF_SEL_flat_atomic_wavefronts               = 0x67,
++	TA_PERF_SEL_flat_coalesceable_wavefronts         = 0x68,
++	TA_PERF_SEL_reg_sclk_vld                         = 0x69,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6a,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x6b,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en       = 0x6c,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x6d,
++	TA_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x6e,
++	TA_PERF_SEL_xnack_on_phase0                      = 0x6f,
++	TA_PERF_SEL_xnack_on_phase1                      = 0x70,
++	TA_PERF_SEL_xnack_on_phase2                      = 0x71,
++	TA_PERF_SEL_xnack_on_phase3                      = 0x72,
++	TA_PERF_SEL_first_xnack_on_phase0                = 0x73,
++	TA_PERF_SEL_first_xnack_on_phase1                = 0x74,
++	TA_PERF_SEL_first_xnack_on_phase2                = 0x75,
++	TA_PERF_SEL_first_xnack_on_phase3                = 0x76,
++} TA_PERFCOUNT_SEL;
++typedef enum TD_PERFCOUNT_SEL {
++	TD_PERF_SEL_none                                 = 0x0,
++	TD_PERF_SEL_td_busy                              = 0x1,
++	TD_PERF_SEL_input_busy                           = 0x2,
++	TD_PERF_SEL_output_busy                          = 0x3,
++	TD_PERF_SEL_lerp_busy                            = 0x4,
++	TD_PERF_SEL_reg_sclk_vld                         = 0x5,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x7,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x8,
++	TD_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x9,
++	TD_PERF_SEL_tc_td_fifo_full                      = 0xa,
++	TD_PERF_SEL_constant_state_full                  = 0xb,
++	TD_PERF_SEL_sample_state_full                    = 0xc,
++	TD_PERF_SEL_output_fifo_full                     = 0xd,
++	TD_PERF_SEL_RESERVED_14                          = 0xe,
++	TD_PERF_SEL_tc_stall                             = 0xf,
++	TD_PERF_SEL_pc_stall                             = 0x10,
++	TD_PERF_SEL_gds_stall                            = 0x11,
++	TD_PERF_SEL_RESERVED_18                          = 0x12,
++	TD_PERF_SEL_RESERVED_19                          = 0x13,
++	TD_PERF_SEL_gather4_wavefront                    = 0x14,
++	TD_PERF_SEL_sample_c_wavefront                   = 0x15,
++	TD_PERF_SEL_load_wavefront                       = 0x16,
++	TD_PERF_SEL_atomic_wavefront                     = 0x17,
++	TD_PERF_SEL_store_wavefront                      = 0x18,
++	TD_PERF_SEL_ldfptr_wavefront                     = 0x19,
++	TD_PERF_SEL_RESERVED_26                          = 0x1a,
++	TD_PERF_SEL_RESERVED_27                          = 0x1b,
++	TD_PERF_SEL_d16_en_wavefront                     = 0x1c,
++	TD_PERF_SEL_bicubic_filter_wavefront             = 0x1d,
++	TD_PERF_SEL_bypass_filter_wavefront              = 0x1e,
++	TD_PERF_SEL_min_max_filter_wavefront             = 0x1f,
++	TD_PERF_SEL_coalescable_wavefront                = 0x20,
++	TD_PERF_SEL_coalesced_phase                      = 0x21,
++	TD_PERF_SEL_four_phase_wavefront                 = 0x22,
++	TD_PERF_SEL_eight_phase_wavefront                = 0x23,
++	TD_PERF_SEL_sixteen_phase_wavefront              = 0x24,
++	TD_PERF_SEL_four_phase_forward_wavefront         = 0x25,
++	TD_PERF_SEL_write_ack_wavefront                  = 0x26,
++	TD_PERF_SEL_RESERVED_39                          = 0x27,
++	TD_PERF_SEL_user_defined_border                  = 0x28,
++	TD_PERF_SEL_white_border                         = 0x29,
++	TD_PERF_SEL_opaque_black_border                  = 0x2a,
++	TD_PERF_SEL_RESERVED_43                          = 0x2b,
++	TD_PERF_SEL_RESERVED_44                          = 0x2c,
++	TD_PERF_SEL_nack                                 = 0x2d,
++	TD_PERF_SEL_td_sp_traffic                        = 0x2e,
++	TD_PERF_SEL_consume_gds_traffic                  = 0x2f,
++	TD_PERF_SEL_addresscmd_poison                    = 0x30,
++	TD_PERF_SEL_data_poison                          = 0x31,
++	TD_PERF_SEL_start_cycle_0                        = 0x32,
++	TD_PERF_SEL_start_cycle_1                        = 0x33,
++	TD_PERF_SEL_start_cycle_2                        = 0x34,
++	TD_PERF_SEL_start_cycle_3                        = 0x35,
++	TD_PERF_SEL_null_cycle_output                    = 0x36,
++} TD_PERFCOUNT_SEL;
++typedef enum TCP_PERFCOUNT_SELECT {
++	TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES           = 0x0,
++	TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES           = 0x1,
++	TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES            = 0x2,
++	TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES            = 0x3,
++	TCP_PERF_SEL_TD_TCP_STALL_CYCLES                 = 0x4,
++	TCP_PERF_SEL_TCR_TCP_STALL_CYCLES                = 0x5,
++	TCP_PERF_SEL_LOD_STALL_CYCLES                    = 0x6,
++	TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES       = 0x7,
++	TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES      = 0x8,
++	TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES     = 0x9,
++	TCP_PERF_SEL_ALLOC_STALL_CYCLES                  = 0xa,
++	TCP_PERF_SEL_LFIFO_STALL_CYCLES                  = 0xb,
++	TCP_PERF_SEL_RFIFO_STALL_CYCLES                  = 0xc,
++	TCP_PERF_SEL_TCR_RDRET_STALL                     = 0xd,
++	TCP_PERF_SEL_WRITE_CONFLICT_STALL                = 0xe,
++	TCP_PERF_SEL_HOLE_READ_STALL                     = 0xf,
++	TCP_PERF_SEL_READCONFLICT_STALL_CYCLES           = 0x10,
++	TCP_PERF_SEL_PENDING_STALL_CYCLES                = 0x11,
++	TCP_PERF_SEL_READFIFO_STALL_CYCLES               = 0x12,
++	TCP_PERF_SEL_TCP_LATENCY                         = 0x13,
++	TCP_PERF_SEL_TCC_READ_REQ_LATENCY                = 0x14,
++	TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY               = 0x15,
++	TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY          = 0x16,
++	TCP_PERF_SEL_TCC_READ_REQ                        = 0x17,
++	TCP_PERF_SEL_TCC_WRITE_REQ                       = 0x18,
++	TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ             = 0x19,
++	TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ          = 0x1a,
++	TCP_PERF_SEL_TOTAL_LOCAL_READ                    = 0x1b,
++	TCP_PERF_SEL_TOTAL_GLOBAL_READ                   = 0x1c,
++	TCP_PERF_SEL_TOTAL_LOCAL_WRITE                   = 0x1d,
++	TCP_PERF_SEL_TOTAL_GLOBAL_WRITE                  = 0x1e,
++	TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET               = 0x1f,
++	TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET            = 0x20,
++	TCP_PERF_SEL_TOTAL_WBINVL1                       = 0x21,
++	TCP_PERF_SEL_IMG_READ_FMT_1                      = 0x22,
++	TCP_PERF_SEL_IMG_READ_FMT_8                      = 0x23,
++	TCP_PERF_SEL_IMG_READ_FMT_16                     = 0x24,
++	TCP_PERF_SEL_IMG_READ_FMT_32                     = 0x25,
++	TCP_PERF_SEL_IMG_READ_FMT_32_AS_8                = 0x26,
++	TCP_PERF_SEL_IMG_READ_FMT_32_AS_16               = 0x27,
++	TCP_PERF_SEL_IMG_READ_FMT_32_AS_128              = 0x28,
++	TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE             = 0x29,
++	TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE             = 0x2a,
++	TCP_PERF_SEL_IMG_READ_FMT_96                     = 0x2b,
++	TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE            = 0x2c,
++	TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE            = 0x2d,
++	TCP_PERF_SEL_IMG_READ_FMT_BC1                    = 0x2e,
++	TCP_PERF_SEL_IMG_READ_FMT_BC2                    = 0x2f,
++	TCP_PERF_SEL_IMG_READ_FMT_BC3                    = 0x30,
++	TCP_PERF_SEL_IMG_READ_FMT_BC4                    = 0x31,
++	TCP_PERF_SEL_IMG_READ_FMT_BC5                    = 0x32,
++	TCP_PERF_SEL_IMG_READ_FMT_BC6                    = 0x33,
++	TCP_PERF_SEL_IMG_READ_FMT_BC7                    = 0x34,
++	TCP_PERF_SEL_IMG_READ_FMT_I8                     = 0x35,
++	TCP_PERF_SEL_IMG_READ_FMT_I16                    = 0x36,
++	TCP_PERF_SEL_IMG_READ_FMT_I32                    = 0x37,
++	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8               = 0x38,
++	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16              = 0x39,
++	TCP_PERF_SEL_IMG_READ_FMT_D8                     = 0x3a,
++	TCP_PERF_SEL_IMG_READ_FMT_D16                    = 0x3b,
++	TCP_PERF_SEL_IMG_READ_FMT_D32                    = 0x3c,
++	TCP_PERF_SEL_IMG_WRITE_FMT_8                     = 0x3d,
++	TCP_PERF_SEL_IMG_WRITE_FMT_16                    = 0x3e,
++	TCP_PERF_SEL_IMG_WRITE_FMT_32                    = 0x3f,
++	TCP_PERF_SEL_IMG_WRITE_FMT_64                    = 0x40,
++	TCP_PERF_SEL_IMG_WRITE_FMT_128                   = 0x41,
++	TCP_PERF_SEL_IMG_WRITE_FMT_D8                    = 0x42,
++	TCP_PERF_SEL_IMG_WRITE_FMT_D16                   = 0x43,
++	TCP_PERF_SEL_IMG_WRITE_FMT_D32                   = 0x44,
++	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32          = 0x45,
++	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32       = 0x46,
++	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64          = 0x47,
++	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64       = 0x48,
++	TCP_PERF_SEL_BUF_READ_FMT_8                      = 0x49,
++	TCP_PERF_SEL_BUF_READ_FMT_16                     = 0x4a,
++	TCP_PERF_SEL_BUF_READ_FMT_32                     = 0x4b,
++	TCP_PERF_SEL_BUF_WRITE_FMT_8                     = 0x4c,
++	TCP_PERF_SEL_BUF_WRITE_FMT_16                    = 0x4d,
++	TCP_PERF_SEL_BUF_WRITE_FMT_32                    = 0x4e,
++	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32          = 0x4f,
++	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32       = 0x50,
++	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64          = 0x51,
++	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64       = 0x52,
++	TCP_PERF_SEL_ARR_LINEAR_GENERAL                  = 0x53,
++	TCP_PERF_SEL_ARR_LINEAR_ALIGNED                  = 0x54,
++	TCP_PERF_SEL_ARR_1D_THIN1                        = 0x55,
++	TCP_PERF_SEL_ARR_1D_THICK                        = 0x56,
++	TCP_PERF_SEL_ARR_2D_THIN1                        = 0x57,
++	TCP_PERF_SEL_ARR_2D_THICK                        = 0x58,
++	TCP_PERF_SEL_ARR_2D_XTHICK                       = 0x59,
++	TCP_PERF_SEL_ARR_3D_THIN1                        = 0x5a,
++	TCP_PERF_SEL_ARR_3D_THICK                        = 0x5b,
++	TCP_PERF_SEL_ARR_3D_XTHICK                       = 0x5c,
++	TCP_PERF_SEL_DIM_1D                              = 0x5d,
++	TCP_PERF_SEL_DIM_2D                              = 0x5e,
++	TCP_PERF_SEL_DIM_3D                              = 0x5f,
++	TCP_PERF_SEL_DIM_1D_ARRAY                        = 0x60,
++	TCP_PERF_SEL_DIM_2D_ARRAY                        = 0x61,
++	TCP_PERF_SEL_DIM_2D_MSAA                         = 0x62,
++	TCP_PERF_SEL_DIM_2D_ARRAY_MSAA                   = 0x63,
++	TCP_PERF_SEL_DIM_CUBE_ARRAY                      = 0x64,
++	TCP_PERF_SEL_CP_TCP_INVALIDATE                   = 0x65,
++	TCP_PERF_SEL_TA_TCP_STATE_READ                   = 0x66,
++	TCP_PERF_SEL_TAGRAM0_REQ                         = 0x67,
++	TCP_PERF_SEL_TAGRAM1_REQ                         = 0x68,
++	TCP_PERF_SEL_TAGRAM2_REQ                         = 0x69,
++	TCP_PERF_SEL_TAGRAM3_REQ                         = 0x6a,
++	TCP_PERF_SEL_GATE_EN1                            = 0x6b,
++	TCP_PERF_SEL_GATE_EN2                            = 0x6c,
++	TCP_PERF_SEL_CORE_REG_SCLK_VLD                   = 0x6d,
++	TCP_PERF_SEL_TCC_REQ                             = 0x6e,
++	TCP_PERF_SEL_TCC_NON_READ_REQ                    = 0x6f,
++	TCP_PERF_SEL_TCC_BYPASS_READ_REQ                 = 0x70,
++	TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ             = 0x71,
++	TCP_PERF_SEL_TCC_VOLATILE_READ_REQ               = 0x72,
++	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ        = 0x73,
++	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ    = 0x74,
++	TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ                = 0x75,
++	TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ            = 0x76,
++	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ       = 0x77,
++	TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ              = 0x78,
++	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ   = 0x79,
++	TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ               = 0x7a,
++	TCP_PERF_SEL_TCC_ATOMIC_REQ                      = 0x7b,
++	TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ             = 0x7c,
++	TCP_PERF_SEL_TCC_DATA_BUS_BUSY                   = 0x7d,
++	TCP_PERF_SEL_TOTAL_ACCESSES                      = 0x7e,
++	TCP_PERF_SEL_TOTAL_READ                          = 0x7f,
++	TCP_PERF_SEL_TOTAL_HIT_LRU_READ                  = 0x80,
++	TCP_PERF_SEL_TOTAL_HIT_EVICT_READ                = 0x81,
++	TCP_PERF_SEL_TOTAL_MISS_LRU_READ                 = 0x82,
++	TCP_PERF_SEL_TOTAL_MISS_EVICT_READ               = 0x83,
++	TCP_PERF_SEL_TOTAL_NON_READ                      = 0x84,
++	TCP_PERF_SEL_TOTAL_WRITE                         = 0x85,
++	TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE                = 0x86,
++	TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE              = 0x87,
++	TCP_PERF_SEL_TOTAL_WBINVL1_VOL                   = 0x88,
++	TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES         = 0x89,
++	TCP_PERF_SEL_DISPLAY_MICROTILING                 = 0x8a,
++	TCP_PERF_SEL_THIN_MICROTILING                    = 0x8b,
++	TCP_PERF_SEL_DEPTH_MICROTILING                   = 0x8c,
++	TCP_PERF_SEL_ARR_PRT_THIN1                       = 0x8d,
++	TCP_PERF_SEL_ARR_PRT_2D_THIN1                    = 0x8e,
++	TCP_PERF_SEL_ARR_PRT_3D_THIN1                    = 0x8f,
++	TCP_PERF_SEL_ARR_PRT_THICK                       = 0x90,
++	TCP_PERF_SEL_ARR_PRT_2D_THICK                    = 0x91,
++	TCP_PERF_SEL_ARR_PRT_3D_THICK                    = 0x92,
++	TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL               = 0x93,
++	TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL               = 0x94,
++	TCP_PERF_SEL_UNALIGNED                           = 0x95,
++	TCP_PERF_SEL_ROTATED_MICROTILING                 = 0x96,
++	TCP_PERF_SEL_THICK_MICROTILING                   = 0x97,
++	TCP_PERF_SEL_ATC                                 = 0x98,
++	TCP_PERF_SEL_POWER_STALL                         = 0x99,
++	TCP_PERF_SEL_RESERVED_154                        = 0x9a,
++	TCP_PERF_SEL_TCC_LRU_REQ                         = 0x9b,
++	TCP_PERF_SEL_TCC_STREAM_REQ                      = 0x9c,
++	TCP_PERF_SEL_TCC_NC_READ_REQ                     = 0x9d,
++	TCP_PERF_SEL_TCC_NC_WRITE_REQ                    = 0x9e,
++	TCP_PERF_SEL_TCC_NC_ATOMIC_REQ                   = 0x9f,
++	TCP_PERF_SEL_TCC_UC_READ_REQ                     = 0xa0,
++	TCP_PERF_SEL_TCC_UC_WRITE_REQ                    = 0xa1,
++	TCP_PERF_SEL_TCC_UC_ATOMIC_REQ                   = 0xa2,
++	TCP_PERF_SEL_TCC_CC_READ_REQ                     = 0xa3,
++	TCP_PERF_SEL_TCC_CC_WRITE_REQ                    = 0xa4,
++	TCP_PERF_SEL_TCC_CC_ATOMIC_REQ                   = 0xa5,
++	TCP_PERF_SEL_TCC_DCC_REQ                         = 0xa6,
++	TCP_PERF_SEL_TCC_PHYSICAL_REQ                    = 0xa7,
++	TCP_PERF_SEL_UNORDERED_MTYPE_STALL               = 0xa8,
++	TCP_PERF_SEL_VOLATILE                            = 0xa9,
++	TCP_PERF_SEL_TC_TA_XNACK_STALL                   = 0xaa,
++	TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL           = 0xab,
++	TCP_PERF_SEL_SHOOTDOWN                           = 0xac,
++	TCP_PERF_SEL_GATCL1_TRANSLATION_MISS             = 0xad,
++	TCP_PERF_SEL_GATCL1_PERMISSION_MISS              = 0xae,
++	TCP_PERF_SEL_GATCL1_REQUEST                      = 0xaf,
++	TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX           = 0xb0,
++	TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT           = 0xb1,
++	TCP_PERF_SEL_GATCL1_LFIFO_FULL                   = 0xb2,
++	TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES          = 0xb3,
++	TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4,
++	TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT               = 0xb5,
++	TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL          = 0xb6,
++} TCP_PERFCOUNT_SELECT;
++typedef enum TCP_CACHE_POLICIES {
++	TCP_CACHE_POLICY_MISS_LRU                        = 0x0,
++	TCP_CACHE_POLICY_MISS_EVICT                      = 0x1,
++	TCP_CACHE_POLICY_HIT_LRU                         = 0x2,
++	TCP_CACHE_POLICY_HIT_EVICT                       = 0x3,
++} TCP_CACHE_POLICIES;
++typedef enum TCP_CACHE_STORE_POLICIES {
++	TCP_CACHE_STORE_POLICY_WT_LRU                    = 0x0,
++	TCP_CACHE_STORE_POLICY_WT_EVICT                  = 0x1,
++} TCP_CACHE_STORE_POLICIES;
++typedef enum TCP_WATCH_MODES {
++	TCP_WATCH_MODE_READ                              = 0x0,
++	TCP_WATCH_MODE_NONREAD                           = 0x1,
++	TCP_WATCH_MODE_ATOMIC                            = 0x2,
++	TCP_WATCH_MODE_ALL                               = 0x3,
++} TCP_WATCH_MODES;
++typedef enum TCP_DSM_DATA_SEL {
++	TCP_DSM_DISABLE                                  = 0x0,
++	TCP_DSM_SEL0                                     = 0x1,
++	TCP_DSM_SEL1                                     = 0x2,
++	TCP_DSM_SEL_BOTH                                 = 0x3,
++} TCP_DSM_DATA_SEL;
++typedef enum TCP_DSM_SINGLE_WRITE {
++	TCP_DSM_SINGLE_WRITE_EN                          = 0x1,
++} TCP_DSM_SINGLE_WRITE;
++typedef enum VGT_OUT_PRIM_TYPE {
++	VGT_OUT_POINT                                    = 0x0,
++	VGT_OUT_LINE                                     = 0x1,
++	VGT_OUT_TRI                                      = 0x2,
++	VGT_OUT_RECT_V0                                  = 0x3,
++	VGT_OUT_RECT_V1                                  = 0x4,
++	VGT_OUT_RECT_V2                                  = 0x5,
++	VGT_OUT_RECT_V3                                  = 0x6,
++	VGT_OUT_RESERVED                                 = 0x7,
++	VGT_TE_QUAD                                      = 0x8,
++	VGT_TE_PRIM_INDEX_LINE                           = 0x9,
++	VGT_TE_PRIM_INDEX_TRI                            = 0xa,
++	VGT_TE_PRIM_INDEX_QUAD                           = 0xb,
++	VGT_OUT_LINE_ADJ                                 = 0xc,
++	VGT_OUT_TRI_ADJ                                  = 0xd,
++	VGT_OUT_PATCH                                    = 0xe,
++} VGT_OUT_PRIM_TYPE;
++typedef enum VGT_DI_PRIM_TYPE {
++	DI_PT_NONE                                       = 0x0,
++	DI_PT_POINTLIST                                  = 0x1,
++	DI_PT_LINELIST                                   = 0x2,
++	DI_PT_LINESTRIP                                  = 0x3,
++	DI_PT_TRILIST                                    = 0x4,
++	DI_PT_TRIFAN                                     = 0x5,
++	DI_PT_TRISTRIP                                   = 0x6,
++	DI_PT_UNUSED_0                                   = 0x7,
++	DI_PT_UNUSED_1                                   = 0x8,
++	DI_PT_PATCH                                      = 0x9,
++	DI_PT_LINELIST_ADJ                               = 0xa,
++	DI_PT_LINESTRIP_ADJ                              = 0xb,
++	DI_PT_TRILIST_ADJ                                = 0xc,
++	DI_PT_TRISTRIP_ADJ                               = 0xd,
++	DI_PT_UNUSED_3                                   = 0xe,
++	DI_PT_UNUSED_4                                   = 0xf,
++	DI_PT_TRI_WITH_WFLAGS                            = 0x10,
++	DI_PT_RECTLIST                                   = 0x11,
++	DI_PT_LINELOOP                                   = 0x12,
++	DI_PT_QUADLIST                                   = 0x13,
++	DI_PT_QUADSTRIP                                  = 0x14,
++	DI_PT_POLYGON                                    = 0x15,
++	DI_PT_2D_COPY_RECT_LIST_V0                       = 0x16,
++	DI_PT_2D_COPY_RECT_LIST_V1                       = 0x17,
++	DI_PT_2D_COPY_RECT_LIST_V2                       = 0x18,
++	DI_PT_2D_COPY_RECT_LIST_V3                       = 0x19,
++	DI_PT_2D_FILL_RECT_LIST                          = 0x1a,
++	DI_PT_2D_LINE_STRIP                              = 0x1b,
++	DI_PT_2D_TRI_STRIP                               = 0x1c,
++} VGT_DI_PRIM_TYPE;
++typedef enum VGT_DI_SOURCE_SELECT {
++	DI_SRC_SEL_DMA                                   = 0x0,
++	DI_SRC_SEL_IMMEDIATE                             = 0x1,
++	DI_SRC_SEL_AUTO_INDEX                            = 0x2,
++	DI_SRC_SEL_RESERVED                              = 0x3,
++} VGT_DI_SOURCE_SELECT;
++typedef enum VGT_DI_MAJOR_MODE_SELECT {
++	DI_MAJOR_MODE_0                                  = 0x0,
++	DI_MAJOR_MODE_1                                  = 0x1,
++} VGT_DI_MAJOR_MODE_SELECT;
++typedef enum VGT_DI_INDEX_SIZE {
++	DI_INDEX_SIZE_16_BIT                             = 0x0,
++	DI_INDEX_SIZE_32_BIT                             = 0x1,
++	DI_INDEX_SIZE_8_BIT                              = 0x2,
++} VGT_DI_INDEX_SIZE;
++typedef enum VGT_EVENT_TYPE {
++	Reserved_0x00                                    = 0x0,
++	SAMPLE_STREAMOUTSTATS1                           = 0x1,
++	SAMPLE_STREAMOUTSTATS2                           = 0x2,
++	SAMPLE_STREAMOUTSTATS3                           = 0x3,
++	CACHE_FLUSH_TS                                   = 0x4,
++	CONTEXT_DONE                                     = 0x5,
++	CACHE_FLUSH                                      = 0x6,
++	CS_PARTIAL_FLUSH                                 = 0x7,
++	VGT_STREAMOUT_SYNC                               = 0x8,
++	Reserved_0x09                                    = 0x9,
++	VGT_STREAMOUT_RESET                              = 0xa,
++	END_OF_PIPE_INCR_DE                              = 0xb,
++	END_OF_PIPE_IB_END                               = 0xc,
++	RST_PIX_CNT                                      = 0xd,
++	Reserved_0x0E                                    = 0xe,
++	VS_PARTIAL_FLUSH                                 = 0xf,
++	PS_PARTIAL_FLUSH                                 = 0x10,
++	FLUSH_HS_OUTPUT                                  = 0x11,
++	FLUSH_LS_OUTPUT                                  = 0x12,
++	Reserved_0x13                                    = 0x13,
++	CACHE_FLUSH_AND_INV_TS_EVENT                     = 0x14,
++	ZPASS_DONE                                       = 0x15,
++	CACHE_FLUSH_AND_INV_EVENT                        = 0x16,
++	PERFCOUNTER_START                                = 0x17,
++	PERFCOUNTER_STOP                                 = 0x18,
++	PIPELINESTAT_START                               = 0x19,
++	PIPELINESTAT_STOP                                = 0x1a,
++	PERFCOUNTER_SAMPLE                               = 0x1b,
++	FLUSH_ES_OUTPUT                                  = 0x1c,
++	FLUSH_GS_OUTPUT                                  = 0x1d,
++	SAMPLE_PIPELINESTAT                              = 0x1e,
++	SO_VGTSTREAMOUT_FLUSH                            = 0x1f,
++	SAMPLE_STREAMOUTSTATS                            = 0x20,
++	RESET_VTX_CNT                                    = 0x21,
++	BLOCK_CONTEXT_DONE                               = 0x22,
++	CS_CONTEXT_DONE                                  = 0x23,
++	VGT_FLUSH                                        = 0x24,
++	TGID_ROLLOVER                                    = 0x25,
++	SQ_NON_EVENT                                     = 0x26,
++	SC_SEND_DB_VPZ                                   = 0x27,
++	BOTTOM_OF_PIPE_TS                                = 0x28,
++	FLUSH_SX_TS                                      = 0x29,
++	DB_CACHE_FLUSH_AND_INV                           = 0x2a,
++	FLUSH_AND_INV_DB_DATA_TS                         = 0x2b,
++	FLUSH_AND_INV_DB_META                            = 0x2c,
++	FLUSH_AND_INV_CB_DATA_TS                         = 0x2d,
++	FLUSH_AND_INV_CB_META                            = 0x2e,
++	CS_DONE                                          = 0x2f,
++	PS_DONE                                          = 0x30,
++	FLUSH_AND_INV_CB_PIXEL_DATA                      = 0x31,
++	SX_CB_RAT_ACK_REQUEST                            = 0x32,
++	THREAD_TRACE_START                               = 0x33,
++	THREAD_TRACE_STOP                                = 0x34,
++	THREAD_TRACE_MARKER                              = 0x35,
++	THREAD_TRACE_FLUSH                               = 0x36,
++	THREAD_TRACE_FINISH                              = 0x37,
++	PIXEL_PIPE_STAT_CONTROL                          = 0x38,
++	PIXEL_PIPE_STAT_DUMP                             = 0x39,
++	PIXEL_PIPE_STAT_RESET                            = 0x3a,
++	CONTEXT_SUSPEND                                  = 0x3b,
++	OFFCHIP_HS_DEALLOC                               = 0x3c,
++} VGT_EVENT_TYPE;
++typedef enum VGT_DMA_SWAP_MODE {
++	VGT_DMA_SWAP_NONE                                = 0x0,
++	VGT_DMA_SWAP_16_BIT                              = 0x1,
++	VGT_DMA_SWAP_32_BIT                              = 0x2,
++	VGT_DMA_SWAP_WORD                                = 0x3,
++} VGT_DMA_SWAP_MODE;
++typedef enum VGT_INDEX_TYPE_MODE {
++	VGT_INDEX_16                                     = 0x0,
++	VGT_INDEX_32                                     = 0x1,
++	VGT_INDEX_8                                      = 0x2,
++} VGT_INDEX_TYPE_MODE;
++typedef enum VGT_DMA_BUF_TYPE {
++	VGT_DMA_BUF_MEM                                  = 0x0,
++	VGT_DMA_BUF_RING                                 = 0x1,
++	VGT_DMA_BUF_SETUP                                = 0x2,
++	VGT_DMA_PTR_UPDATE                               = 0x3,
++} VGT_DMA_BUF_TYPE;
++typedef enum VGT_OUTPATH_SELECT {
++	VGT_OUTPATH_VTX_REUSE                            = 0x0,
++	VGT_OUTPATH_TESS_EN                              = 0x1,
++	VGT_OUTPATH_PASSTHRU                             = 0x2,
++	VGT_OUTPATH_GS_BLOCK                             = 0x3,
++	VGT_OUTPATH_HS_BLOCK                             = 0x4,
++} VGT_OUTPATH_SELECT;
++typedef enum VGT_GRP_PRIM_TYPE {
++	VGT_GRP_3D_POINT                                 = 0x0,
++	VGT_GRP_3D_LINE                                  = 0x1,
++	VGT_GRP_3D_TRI                                   = 0x2,
++	VGT_GRP_3D_RECT                                  = 0x3,
++	VGT_GRP_3D_QUAD                                  = 0x4,
++	VGT_GRP_2D_COPY_RECT_V0                          = 0x5,
++	VGT_GRP_2D_COPY_RECT_V1                          = 0x6,
++	VGT_GRP_2D_COPY_RECT_V2                          = 0x7,
++	VGT_GRP_2D_COPY_RECT_V3                          = 0x8,
++	VGT_GRP_2D_FILL_RECT                             = 0x9,
++	VGT_GRP_2D_LINE                                  = 0xa,
++	VGT_GRP_2D_TRI                                   = 0xb,
++	VGT_GRP_PRIM_INDEX_LINE                          = 0xc,
++	VGT_GRP_PRIM_INDEX_TRI                           = 0xd,
++	VGT_GRP_PRIM_INDEX_QUAD                          = 0xe,
++	VGT_GRP_3D_LINE_ADJ                              = 0xf,
++	VGT_GRP_3D_TRI_ADJ                               = 0x10,
++	VGT_GRP_3D_PATCH                                 = 0x11,
++} VGT_GRP_PRIM_TYPE;
++typedef enum VGT_GRP_PRIM_ORDER {
++	VGT_GRP_LIST                                     = 0x0,
++	VGT_GRP_STRIP                                    = 0x1,
++	VGT_GRP_FAN                                      = 0x2,
++	VGT_GRP_LOOP                                     = 0x3,
++	VGT_GRP_POLYGON                                  = 0x4,
++} VGT_GRP_PRIM_ORDER;
++typedef enum VGT_GROUP_CONV_SEL {
++	VGT_GRP_INDEX_16                                 = 0x0,
++	VGT_GRP_INDEX_32                                 = 0x1,
++	VGT_GRP_UINT_16                                  = 0x2,
++	VGT_GRP_UINT_32                                  = 0x3,
++	VGT_GRP_SINT_16                                  = 0x4,
++	VGT_GRP_SINT_32                                  = 0x5,
++	VGT_GRP_FLOAT_32                                 = 0x6,
++	VGT_GRP_AUTO_PRIM                                = 0x7,
++	VGT_GRP_FIX_1_23_TO_FLOAT                        = 0x8,
++} VGT_GROUP_CONV_SEL;
++typedef enum VGT_GS_MODE_TYPE {
++	GS_OFF                                           = 0x0,
++	GS_SCENARIO_A                                    = 0x1,
++	GS_SCENARIO_B                                    = 0x2,
++	GS_SCENARIO_G                                    = 0x3,
++	GS_SCENARIO_C                                    = 0x4,
++	SPRITE_EN                                        = 0x5,
++} VGT_GS_MODE_TYPE;
++typedef enum VGT_GS_CUT_MODE {
++	GS_CUT_1024                                      = 0x0,
++	GS_CUT_512                                       = 0x1,
++	GS_CUT_256                                       = 0x2,
++	GS_CUT_128                                       = 0x3,
++} VGT_GS_CUT_MODE;
++typedef enum VGT_GS_OUTPRIM_TYPE {
++	POINTLIST                                        = 0x0,
++	LINESTRIP                                        = 0x1,
++	TRISTRIP                                         = 0x2,
++} VGT_GS_OUTPRIM_TYPE;
++typedef enum VGT_CACHE_INVALID_MODE {
++	VC_ONLY                                          = 0x0,
++	TC_ONLY                                          = 0x1,
++	VC_AND_TC                                        = 0x2,
++} VGT_CACHE_INVALID_MODE;
++typedef enum VGT_TESS_TYPE {
++	TESS_ISOLINE                                     = 0x0,
++	TESS_TRIANGLE                                    = 0x1,
++	TESS_QUAD                                        = 0x2,
++} VGT_TESS_TYPE;
++typedef enum VGT_TESS_PARTITION {
++	PART_INTEGER                                     = 0x0,
++	PART_POW2                                        = 0x1,
++	PART_FRAC_ODD                                    = 0x2,
++	PART_FRAC_EVEN                                   = 0x3,
++} VGT_TESS_PARTITION;
++typedef enum VGT_TESS_TOPOLOGY {
++	OUTPUT_POINT                                     = 0x0,
++	OUTPUT_LINE                                      = 0x1,
++	OUTPUT_TRIANGLE_CW                               = 0x2,
++	OUTPUT_TRIANGLE_CCW                              = 0x3,
++} VGT_TESS_TOPOLOGY;
++typedef enum VGT_RDREQ_POLICY {
++	VGT_POLICY_LRU                                   = 0x0,
++	VGT_POLICY_STREAM                                = 0x1,
++} VGT_RDREQ_POLICY;
++typedef enum VGT_DIST_MODE {
++	NO_DIST                                          = 0x0,
++	PATCHES                                          = 0x1,
++	DONUTS                                           = 0x2,
++} VGT_DIST_MODE;
++typedef enum VGT_STAGES_LS_EN {
++	LS_STAGE_OFF                                     = 0x0,
++	LS_STAGE_ON                                      = 0x1,
++	CS_STAGE_ON                                      = 0x2,
++	RESERVED_LS                                      = 0x3,
++} VGT_STAGES_LS_EN;
++typedef enum VGT_STAGES_HS_EN {
++	HS_STAGE_OFF                                     = 0x0,
++	HS_STAGE_ON                                      = 0x1,
++} VGT_STAGES_HS_EN;
++typedef enum VGT_STAGES_ES_EN {
++	ES_STAGE_OFF                                     = 0x0,
++	ES_STAGE_DS                                      = 0x1,
++	ES_STAGE_REAL                                    = 0x2,
++	RESERVED_ES                                      = 0x3,
++} VGT_STAGES_ES_EN;
++typedef enum VGT_STAGES_GS_EN {
++	GS_STAGE_OFF                                     = 0x0,
++	GS_STAGE_ON                                      = 0x1,
++} VGT_STAGES_GS_EN;
++typedef enum VGT_STAGES_VS_EN {
++	VS_STAGE_REAL                                    = 0x0,
++	VS_STAGE_DS                                      = 0x1,
++	VS_STAGE_COPY_SHADER                             = 0x2,
++	RESERVED_VS                                      = 0x3,
++} VGT_STAGES_VS_EN;
++typedef enum VGT_PERFCOUNT_SELECT {
++	vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE    = 0x0,
++	vgt_perf_VGT_SPI_ESVERT_VALID                    = 0x1,
++	vgt_perf_VGT_SPI_ESVERT_EOV                      = 0x2,
++	vgt_perf_VGT_SPI_ESVERT_STALLED                  = 0x3,
++	vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY             = 0x4,
++	vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE             = 0x5,
++	vgt_perf_VGT_SPI_ESVERT_STATIC                   = 0x6,
++	vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT               = 0x7,
++	vgt_perf_VGT_SPI_ESTHREAD_SEND                   = 0x8,
++	vgt_perf_VGT_SPI_GSPRIM_VALID                    = 0x9,
++	vgt_perf_VGT_SPI_GSPRIM_EOV                      = 0xa,
++	vgt_perf_VGT_SPI_GSPRIM_CONT                     = 0xb,
++	vgt_perf_VGT_SPI_GSPRIM_STALLED                  = 0xc,
++	vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY             = 0xd,
++	vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE             = 0xe,
++	vgt_perf_VGT_SPI_GSPRIM_STATIC                   = 0xf,
++	vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE    = 0x10,
++	vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT               = 0x11,
++	vgt_perf_VGT_SPI_GSTHREAD_SEND                   = 0x12,
++	vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE    = 0x13,
++	vgt_perf_VGT_SPI_VSVERT_SEND                     = 0x14,
++	vgt_perf_VGT_SPI_VSVERT_EOV                      = 0x15,
++	vgt_perf_VGT_SPI_VSVERT_STALLED                  = 0x16,
++	vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY             = 0x17,
++	vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE             = 0x18,
++	vgt_perf_VGT_SPI_VSVERT_STATIC                   = 0x19,
++	vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT               = 0x1a,
++	vgt_perf_VGT_SPI_VSTHREAD_SEND                   = 0x1b,
++	vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE              = 0x1c,
++	vgt_perf_VGT_PA_CLIPV_SEND                       = 0x1d,
++	vgt_perf_VGT_PA_CLIPV_FIRSTVERT                  = 0x1e,
++	vgt_perf_VGT_PA_CLIPV_STALLED                    = 0x1f,
++	vgt_perf_VGT_PA_CLIPV_STARVED_BUSY               = 0x20,
++	vgt_perf_VGT_PA_CLIPV_STARVED_IDLE               = 0x21,
++	vgt_perf_VGT_PA_CLIPV_STATIC                     = 0x22,
++	vgt_perf_VGT_PA_CLIPP_SEND                       = 0x23,
++	vgt_perf_VGT_PA_CLIPP_EOP                        = 0x24,
++	vgt_perf_VGT_PA_CLIPP_IS_EVENT                   = 0x25,
++	vgt_perf_VGT_PA_CLIPP_NULL_PRIM                  = 0x26,
++	vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT               = 0x27,
++	vgt_perf_VGT_PA_CLIPP_STALLED                    = 0x28,
++	vgt_perf_VGT_PA_CLIPP_STARVED_BUSY               = 0x29,
++	vgt_perf_VGT_PA_CLIPP_STARVED_IDLE               = 0x2a,
++	vgt_perf_VGT_PA_CLIPP_STATIC                     = 0x2b,
++	vgt_perf_VGT_PA_CLIPS_SEND                       = 0x2c,
++	vgt_perf_VGT_PA_CLIPS_STALLED                    = 0x2d,
++	vgt_perf_VGT_PA_CLIPS_STARVED_BUSY               = 0x2e,
++	vgt_perf_VGT_PA_CLIPS_STARVED_IDLE               = 0x2f,
++	vgt_perf_VGT_PA_CLIPS_STATIC                     = 0x30,
++	vgt_perf_vsvert_ds_send                          = 0x31,
++	vgt_perf_vsvert_api_send                         = 0x32,
++	vgt_perf_hs_tif_stall                            = 0x33,
++	vgt_perf_hs_input_stall                          = 0x34,
++	vgt_perf_hs_interface_stall                      = 0x35,
++	vgt_perf_hs_tfm_stall                            = 0x36,
++	vgt_perf_te11_starved                            = 0x37,
++	vgt_perf_gs_event_stall                          = 0x38,
++	vgt_perf_vgt_pa_clipp_send_not_event             = 0x39,
++	vgt_perf_vgt_pa_clipp_valid_prim                 = 0x3a,
++	vgt_perf_reused_es_indices                       = 0x3b,
++	vgt_perf_vs_cache_hits                           = 0x3c,
++	vgt_perf_gs_cache_hits                           = 0x3d,
++	vgt_perf_ds_cache_hits                           = 0x3e,
++	vgt_perf_total_cache_hits                        = 0x3f,
++	vgt_perf_vgt_busy                                = 0x40,
++	vgt_perf_vgt_gs_busy                             = 0x41,
++	vgt_perf_esvert_stalled_es_tbl                   = 0x42,
++	vgt_perf_esvert_stalled_gs_tbl                   = 0x43,
++	vgt_perf_esvert_stalled_gs_event                 = 0x44,
++	vgt_perf_esvert_stalled_gsprim                   = 0x45,
++	vgt_perf_gsprim_stalled_es_tbl                   = 0x46,
++	vgt_perf_gsprim_stalled_gs_tbl                   = 0x47,
++	vgt_perf_gsprim_stalled_gs_event                 = 0x48,
++	vgt_perf_gsprim_stalled_esvert                   = 0x49,
++	vgt_perf_esthread_stalled_es_rb_full             = 0x4a,
++	vgt_perf_esthread_stalled_spi_bp                 = 0x4b,
++	vgt_perf_counters_avail_stalled                  = 0x4c,
++	vgt_perf_gs_rb_space_avail_stalled               = 0x4d,
++	vgt_perf_gs_issue_rtr_stalled                    = 0x4e,
++	vgt_perf_gsthread_stalled                        = 0x4f,
++	vgt_perf_strmout_stalled                         = 0x50,
++	vgt_perf_wait_for_es_done_stalled                = 0x51,
++	vgt_perf_cm_stalled_by_gog                       = 0x52,
++	vgt_perf_cm_reading_stalled                      = 0x53,
++	vgt_perf_cm_stalled_by_gsfetch_done              = 0x54,
++	vgt_perf_gog_vs_tbl_stalled                      = 0x55,
++	vgt_perf_gog_out_indx_stalled                    = 0x56,
++	vgt_perf_gog_out_prim_stalled                    = 0x57,
++	vgt_perf_waveid_stalled                          = 0x58,
++	vgt_perf_gog_busy                                = 0x59,
++	vgt_perf_reused_vs_indices                       = 0x5a,
++	vgt_perf_sclk_reg_vld_event                      = 0x5b,
++	vgt_perf_vs_conflicting_indices                  = 0x5c,
++	vgt_perf_sclk_core_vld_event                     = 0x5d,
++	vgt_perf_hswave_stalled                          = 0x5e,
++	vgt_perf_sclk_gs_vld_event                       = 0x5f,
++	vgt_perf_VGT_SPI_LSVERT_VALID                    = 0x60,
++	vgt_perf_VGT_SPI_LSVERT_EOV                      = 0x61,
++	vgt_perf_VGT_SPI_LSVERT_STALLED                  = 0x62,
++	vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY             = 0x63,
++	vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE             = 0x64,
++	vgt_perf_VGT_SPI_LSVERT_STATIC                   = 0x65,
++	vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE      = 0x66,
++	vgt_perf_VGT_SPI_LSWAVE_IS_EVENT                 = 0x67,
++	vgt_perf_VGT_SPI_LSWAVE_SEND                     = 0x68,
++	vgt_perf_VGT_SPI_HSVERT_VALID                    = 0x69,
++	vgt_perf_VGT_SPI_HSVERT_EOV                      = 0x6a,
++	vgt_perf_VGT_SPI_HSVERT_STALLED                  = 0x6b,
++	vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY             = 0x6c,
++	vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE             = 0x6d,
++	vgt_perf_VGT_SPI_HSVERT_STATIC                   = 0x6e,
++	vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE      = 0x6f,
++	vgt_perf_VGT_SPI_HSWAVE_IS_EVENT                 = 0x70,
++	vgt_perf_VGT_SPI_HSWAVE_SEND                     = 0x71,
++	vgt_perf_ds_prims                                = 0x72,
++	vgt_perf_ls_thread_groups                        = 0x73,
++	vgt_perf_hs_thread_groups                        = 0x74,
++	vgt_perf_es_thread_groups                        = 0x75,
++	vgt_perf_vs_thread_groups                        = 0x76,
++	vgt_perf_ls_done_latency                         = 0x77,
++	vgt_perf_hs_done_latency                         = 0x78,
++	vgt_perf_es_done_latency                         = 0x79,
++	vgt_perf_gs_done_latency                         = 0x7a,
++	vgt_perf_vgt_hs_busy                             = 0x7b,
++	vgt_perf_vgt_te11_busy                           = 0x7c,
++	vgt_perf_ls_flush                                = 0x7d,
++	vgt_perf_hs_flush                                = 0x7e,
++	vgt_perf_es_flush                                = 0x7f,
++	vgt_perf_vgt_pa_clipp_eopg                       = 0x80,
++	vgt_perf_ls_done                                 = 0x81,
++	vgt_perf_hs_done                                 = 0x82,
++	vgt_perf_es_done                                 = 0x83,
++	vgt_perf_gs_done                                 = 0x84,
++	vgt_perf_vsfetch_done                            = 0x85,
++	vgt_perf_gs_done_received                        = 0x86,
++	vgt_perf_es_ring_high_water_mark                 = 0x87,
++	vgt_perf_gs_ring_high_water_mark                 = 0x88,
++	vgt_perf_vs_table_high_water_mark                = 0x89,
++	vgt_perf_hs_tgs_active_high_water_mark           = 0x8a,
++	vgt_perf_pa_clipp_dealloc                        = 0x8b,
++	vgt_perf_cut_mem_flush_stalled                   = 0x8c,
++	vgt_perf_vsvert_work_received                    = 0x8d,
++	vgt_perf_vgt_pa_clipp_starved_after_work         = 0x8e,
++	vgt_perf_te11_con_starved_after_work             = 0x8f,
++	vgt_perf_hs_waiting_on_ls_done_stall             = 0x90,
++	vgt_spi_vsvert_valid                             = 0x91,
++} VGT_PERFCOUNT_SELECT;
++typedef enum IA_PERFCOUNT_SELECT {
++	ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE            = 0x0,
++	ia_perf_dma_data_fifo_full                       = 0x1,
++	ia_perf_RESERVED1                                = 0x2,
++	ia_perf_RESERVED2                                = 0x3,
++	ia_perf_RESERVED3                                = 0x4,
++	ia_perf_RESERVED4                                = 0x5,
++	ia_perf_RESERVED5                                = 0x6,
++	ia_perf_MC_LAT_BIN_0                             = 0x7,
++	ia_perf_MC_LAT_BIN_1                             = 0x8,
++	ia_perf_MC_LAT_BIN_2                             = 0x9,
++	ia_perf_MC_LAT_BIN_3                             = 0xa,
++	ia_perf_MC_LAT_BIN_4                             = 0xb,
++	ia_perf_MC_LAT_BIN_5                             = 0xc,
++	ia_perf_MC_LAT_BIN_6                             = 0xd,
++	ia_perf_MC_LAT_BIN_7                             = 0xe,
++	ia_perf_ia_busy                                  = 0xf,
++	ia_perf_ia_sclk_reg_vld_event                    = 0x10,
++	ia_perf_RESERVED6                                = 0x11,
++	ia_perf_ia_sclk_core_vld_event                   = 0x12,
++	ia_perf_RESERVED7                                = 0x13,
++	ia_perf_ia_dma_return                            = 0x14,
++	ia_perf_ia_stalled                               = 0x15,
++	ia_perf_shift_starved_pipe0_event                = 0x16,
++	ia_perf_shift_starved_pipe1_event                = 0x17,
++} IA_PERFCOUNT_SELECT;
++typedef enum WD_PERFCOUNT_SELECT {
++	wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE           = 0x0,
++	wd_perf_RBIU_DR_FIFO_STARVED                     = 0x1,
++	wd_perf_RBIU_DR_FIFO_STALLED                     = 0x2,
++	wd_perf_RBIU_DI_FIFO_STARVED                     = 0x3,
++	wd_perf_RBIU_DI_FIFO_STALLED                     = 0x4,
++	wd_perf_wd_busy                                  = 0x5,
++	wd_perf_wd_sclk_reg_vld_event                    = 0x6,
++	wd_perf_wd_sclk_input_vld_event                  = 0x7,
++	wd_perf_wd_sclk_core_vld_event                   = 0x8,
++	wd_perf_wd_stalled                               = 0x9,
++	wd_perf_inside_tf_bin_0                          = 0xa,
++	wd_perf_inside_tf_bin_1                          = 0xb,
++	wd_perf_inside_tf_bin_2                          = 0xc,
++	wd_perf_inside_tf_bin_3                          = 0xd,
++	wd_perf_inside_tf_bin_4                          = 0xe,
++	wd_perf_inside_tf_bin_5                          = 0xf,
++	wd_perf_inside_tf_bin_6                          = 0x10,
++	wd_perf_inside_tf_bin_7                          = 0x11,
++	wd_perf_inside_tf_bin_8                          = 0x12,
++	wd_perf_tfreq_lat_bin_0                          = 0x13,
++	wd_perf_tfreq_lat_bin_1                          = 0x14,
++	wd_perf_tfreq_lat_bin_2                          = 0x15,
++	wd_perf_tfreq_lat_bin_3                          = 0x16,
++	wd_perf_tfreq_lat_bin_4                          = 0x17,
++	wd_perf_tfreq_lat_bin_5                          = 0x18,
++	wd_perf_tfreq_lat_bin_6                          = 0x19,
++	wd_perf_tfreq_lat_bin_7                          = 0x1a,
++	wd_starved_on_hs_done                            = 0x1b,
++	wd_perf_se0_hs_done_latency                      = 0x1c,
++	wd_perf_se1_hs_done_latency                      = 0x1d,
++	wd_perf_se2_hs_done_latency                      = 0x1e,
++	wd_perf_se3_hs_done_latency                      = 0x1f,
++	wd_perf_hs_done_se0                              = 0x20,
++	wd_perf_hs_done_se1                              = 0x21,
++	wd_perf_hs_done_se2                              = 0x22,
++	wd_perf_hs_done_se3                              = 0x23,
++	wd_perf_null_patches                             = 0x24,
++} WD_PERFCOUNT_SELECT;
++typedef enum WD_IA_DRAW_TYPE {
++	WD_IA_DRAW_TYPE_DI_MM0                           = 0x0,
++	WD_IA_DRAW_TYPE_DI_MM1                           = 0x1,
++	WD_IA_DRAW_TYPE_EVENT_INIT                       = 0x2,
++	WD_IA_DRAW_TYPE_EVENT_ADDR                       = 0x3,
++	WD_IA_DRAW_TYPE_MIN_INDX                         = 0x4,
++	WD_IA_DRAW_TYPE_MAX_INDX                         = 0x5,
++	WD_IA_DRAW_TYPE_INDX_OFF                         = 0x6,
++	WD_IA_DRAW_TYPE_IMM_DATA                         = 0x7,
++} WD_IA_DRAW_TYPE;
++typedef enum WD_IA_DRAW_SOURCE {
++	WD_IA_DRAW_SOURCE_DMA                            = 0x0,
++	WD_IA_DRAW_SOURCE_IMMD                           = 0x1,
++	WD_IA_DRAW_SOURCE_AUTO                           = 0x2,
++	WD_IA_DRAW_SOURCE_OPAQ                           = 0x3,
++} WD_IA_DRAW_SOURCE;
++#define GSTHREADID_SIZE                           0x2
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
++	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
++	DBG_CLIENT_BLKID_bci0                            = 0xe,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
++	DBG_CLIENT_BLKID_cb100                           = 0x10,
++	DBG_CLIENT_BLKID_cb001                           = 0x11,
++	DBG_CLIENT_BLKID_mcd4                            = 0x12,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
++	DBG_CLIENT_BLKID_cb101                           = 0x14,
++	DBG_CLIENT_BLKID_sx10                            = 0x15,
++	DBG_CLIENT_BLKID_cb301                           = 0x16,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
++	DBG_CLIENT_BLKID_scf1                            = 0x1c,
++	DBG_CLIENT_BLKID_sx20                            = 0x1d,
++	DBG_CLIENT_BLKID_spim1                           = 0x1e,
++	DBG_CLIENT_BLKID_pa10                            = 0x1f,
++	DBG_CLIENT_BLKID_pa00                            = 0x20,
++	DBG_CLIENT_BLKID_gmcon                           = 0x21,
++	DBG_CLIENT_BLKID_mcb                             = 0x22,
++	DBG_CLIENT_BLKID_vgt0                            = 0x23,
++	DBG_CLIENT_BLKID_pc0                             = 0x24,
++	DBG_CLIENT_BLKID_bci2                            = 0x25,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
++	DBG_CLIENT_BLKID_spim3                           = 0x27,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
++	DBG_CLIENT_BLKID_cb000                           = 0x2e,
++	DBG_CLIENT_BLKID_spim0                           = 0x2f,
++	DBG_CLIENT_BLKID_mcc2                            = 0x30,
++	DBG_CLIENT_BLKID_ds0                             = 0x31,
++	DBG_CLIENT_BLKID_srbm                            = 0x32,
++	DBG_CLIENT_BLKID_ih                              = 0x33,
++	DBG_CLIENT_BLKID_sem                             = 0x34,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
++	DBG_CLIENT_BLKID_hdp                             = 0x37,
++	DBG_CLIENT_BLKID_acp_0                           = 0x38,
++	DBG_CLIENT_BLKID_acp_1                           = 0x39,
++	DBG_CLIENT_BLKID_cb200                           = 0x3a,
++	DBG_CLIENT_BLKID_scf3                            = 0x3b,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
++	DBG_CLIENT_BLKID_bci3                            = 0x41,
++	DBG_CLIENT_BLKID_mcd0                            = 0x42,
++	DBG_CLIENT_BLKID_pa11                            = 0x43,
++	DBG_CLIENT_BLKID_pa01                            = 0x44,
++	DBG_CLIENT_BLKID_cb201                           = 0x45,
++	DBG_CLIENT_BLKID_spim2                           = 0x46,
++	DBG_CLIENT_BLKID_vgt2                            = 0x47,
++	DBG_CLIENT_BLKID_pc2                             = 0x48,
++	DBG_CLIENT_BLKID_smu_0                           = 0x49,
++	DBG_CLIENT_BLKID_smu_1                           = 0x4a,
++	DBG_CLIENT_BLKID_smu_2                           = 0x4b,
++	DBG_CLIENT_BLKID_cb1                             = 0x4c,
++	DBG_CLIENT_BLKID_ia0                             = 0x4d,
++	DBG_CLIENT_BLKID_wd                              = 0x4e,
++	DBG_CLIENT_BLKID_ia1                             = 0x4f,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
++	DBG_CLIENT_BLKID_scf0                            = 0x51,
++	DBG_CLIENT_BLKID_vgt1                            = 0x52,
++	DBG_CLIENT_BLKID_pc1                             = 0x53,
++	DBG_CLIENT_BLKID_cb0                             = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
++	DBG_CLIENT_BLKID_vgt3                            = 0x7a,
++	DBG_CLIENT_BLKID_pc3                             = 0x7b,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
++	DBG_CLIENT_BLKID_cb300                           = 0x84,
++	DBG_CLIENT_BLKID_mcd1                            = 0x85,
++	DBG_CLIENT_BLKID_sx00                            = 0x86,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
++	DBG_CLIENT_BLKID_mcc3                            = 0x89,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
++	DBG_CLIENT_BLKID_gck                             = 0x8c,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8d,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
++	DBG_CLIENT_BLKID_rlc                             = 0x90,
++	DBG_CLIENT_BLKID_grbm                            = 0x91,
++	DBG_CLIENT_BLKID_sammsp                          = 0x92,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x93,
++	DBG_CLIENT_BLKID_dci_0                           = 0x94,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* GFX_8_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
+new file mode 100644
+index 0000000..7d72245
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
+@@ -0,0 +1,20776 @@
++/*
++ * GFX_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GFX_8_0_SH_MASK_H
++#define GFX_8_0_SH_MASK_H
++
++#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
++#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
++#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
++#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
++#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
++#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
++#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
++#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
++#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
++#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
++#define CB_COLOR_CONTROL__MODE_MASK 0x70
++#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
++#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
++#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
++#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
++#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
++#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
++#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
++#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
++#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
++#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
++#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
++#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
++#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
++#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
++#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
++#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
++#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
++#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
++#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
++#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
++#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
++#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
++#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
++#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
++#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
++#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
++#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
++#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
++#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
++#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
++#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
++#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
++#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
++#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
++#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
++#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
++#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
++#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
++#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
++#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
++#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
++#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
++#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
++#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
++#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
++#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
++#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
++#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
++#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
++#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
++#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
++#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
++#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
++#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
++#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
++#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
++#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
++#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
++#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
++#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
++#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
++#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
++#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
++#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
++#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
++#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
++#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
++#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
++#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
++#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
++#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
++#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
++#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
++#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
++#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
++#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
++#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
++#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
++#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
++#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
++#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
++#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
++#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
++#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
++#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
++#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
++#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
++#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
++#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
++#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
++#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
++#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
++#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
++#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
++#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
++#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
++#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
++#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
++#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
++#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
++#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
++#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
++#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
++#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
++#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
++#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
++#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
++#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
++#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
++#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
++#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
++#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
++#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
++#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
++#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
++#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
++#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
++#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
++#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
++#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
++#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
++#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
++#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
++#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
++#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
++#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
++#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
++#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
++#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
++#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
++#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
++#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
++#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
++#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
++#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
++#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
++#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
++#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
++#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
++#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
++#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
++#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
++#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
++#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
++#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
++#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
++#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
++#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
++#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
++#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
++#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
++#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
++#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
++#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
++#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
++#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
++#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
++#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
++#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
++#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
++#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
++#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
++#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
++#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
++#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
++#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
++#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
++#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
++#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
++#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
++#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
++#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
++#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
++#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
++#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
++#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
++#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
++#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
++#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
++#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
++#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
++#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
++#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
++#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
++#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
++#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
++#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
++#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
++#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
++#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
++#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
++#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
++#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
++#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
++#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
++#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
++#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
++#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
++#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
++#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
++#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
++#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
++#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
++#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
++#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
++#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
++#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
++#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
++#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
++#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
++#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
++#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
++#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
++#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
++#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
++#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
++#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
++#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
++#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
++#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
++#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
++#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
++#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
++#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
++#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
++#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
++#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
++#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
++#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
++#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
++#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
++#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
++#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
++#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
++#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
++#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
++#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
++#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
++#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
++#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
++#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
++#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
++#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
++#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
++#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
++#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
++#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
++#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
++#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
++#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
++#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
++#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
++#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
++#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
++#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
++#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
++#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
++#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
++#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
++#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
++#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
++#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
++#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
++#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
++#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
++#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
++#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
++#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
++#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
++#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
++#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
++#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
++#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
++#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
++#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
++#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
++#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
++#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
++#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
++#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
++#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
++#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
++#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
++#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
++#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
++#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
++#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
++#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
++#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
++#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
++#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
++#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
++#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
++#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
++#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
++#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
++#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
++#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
++#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
++#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
++#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
++#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
++#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
++#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
++#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
++#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
++#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
++#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
++#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
++#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
++#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
++#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
++#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
++#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
++#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
++#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
++#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
++#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
++#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
++#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
++#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
++#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
++#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
++#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
++#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
++#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
++#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
++#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
++#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
++#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
++#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
++#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
++#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
++#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
++#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
++#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
++#define CP_DFY_CNTL__POLICY_MASK 0x1
++#define CP_DFY_CNTL__POLICY__SHIFT 0x0
++#define CP_DFY_CNTL__MTYPE_MASK 0xc
++#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
++#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
++#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
++#define CP_DFY_CNTL__MODE_MASK 0x60000000
++#define CP_DFY_CNTL__MODE__SHIFT 0x1d
++#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
++#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
++#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
++#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
++#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
++#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
++#define CP_DFY_STAT__BUSY_MASK 0x80000000
++#define CP_DFY_STAT__BUSY__SHIFT 0x1f
++#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
++#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
++#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
++#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_0__DATA__SHIFT 0x0
++#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_1__DATA__SHIFT 0x0
++#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_2__DATA__SHIFT 0x0
++#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_3__DATA__SHIFT 0x0
++#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_4__DATA__SHIFT 0x0
++#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_5__DATA__SHIFT 0x0
++#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_6__DATA__SHIFT 0x0
++#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_7__DATA__SHIFT 0x0
++#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_8__DATA__SHIFT 0x0
++#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_9__DATA__SHIFT 0x0
++#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_10__DATA__SHIFT 0x0
++#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_11__DATA__SHIFT 0x0
++#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_12__DATA__SHIFT 0x0
++#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_13__DATA__SHIFT 0x0
++#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_14__DATA__SHIFT 0x0
++#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
++#define CP_DFY_DATA_15__DATA__SHIFT 0x0
++#define CP_DFY_CMD__OFFSET_MASK 0x1ff
++#define CP_DFY_CMD__OFFSET__SHIFT 0x0
++#define CP_DFY_CMD__SIZE_MASK 0xffff0000
++#define CP_DFY_CMD__SIZE__SHIFT 0x10
++#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
++#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
++#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
++#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
++#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
++#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
++#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
++#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
++#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB0_CNTL__MTYPE_MASK 0x18000
++#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
++#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
++#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
++#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
++#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB_CNTL__MTYPE_MASK 0x18000
++#define CP_RB_CNTL__MTYPE__SHIFT 0xf
++#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
++#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
++#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
++#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB1_CNTL__MTYPE_MASK 0x18000
++#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
++#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
++#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
++#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
++#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
++#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
++#define CP_RB2_CNTL__MTYPE_MASK 0x18000
++#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
++#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
++#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
++#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
++#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
++#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
++#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
++#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
++#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
++#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
++#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
++#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
++#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
++#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
++#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
++#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
++#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
++#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
++#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
++#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
++#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
++#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
++#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
++#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
++#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
++#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
++#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
++#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
++#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
++#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
++#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
++#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
++#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
++#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
++#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
++#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
++#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
++#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
++#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
++#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
++#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
++#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
++#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
++#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
++#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
++#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
++#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
++#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
++#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
++#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
++#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
++#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
++#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
++#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
++#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
++#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
++#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
++#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
++#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
++#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
++#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
++#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
++#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
++#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
++#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
++#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
++#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
++#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
++#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
++#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
++#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
++#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
++#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
++#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
++#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
++#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
++#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
++#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
++#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
++#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
++#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
++#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
++#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
++#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
++#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
++#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
++#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
++#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
++#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
++#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
++#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
++#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
++#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
++#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
++#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
++#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
++#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
++#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
++#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
++#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
++#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
++#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
++#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
++#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
++#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
++#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
++#define CP_RB_VMID__RB0_VMID_MASK 0xf
++#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
++#define CP_RB_VMID__RB1_VMID_MASK 0xf00
++#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
++#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
++#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
++#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
++#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
++#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
++#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
++#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
++#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
++#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
++#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
++#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
++#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
++#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
++#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
++#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
++#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
++#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
++#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
++#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
++#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
++#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
++#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
++#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
++#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
++#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
++#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
++#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
++#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
++#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
++#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
++#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
++#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
++#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
++#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
++#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
++#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
++#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
++#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
++#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
++#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
++#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
++#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
++#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
++#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
++#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
++#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
++#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
++#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
++#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
++#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
++#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
++#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
++#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
++#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
++#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
++#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
++#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
++#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
++#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
++#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
++#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
++#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
++#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
++#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
++#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
++#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
++#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
++#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
++#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
++#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
++#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
++#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
++#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
++#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
++#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
++#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
++#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
++#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
++#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
++#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
++#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
++#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
++#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
++#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
++#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
++#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
++#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
++#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
++#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
++#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
++#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
++#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
++#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
++#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
++#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
++#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
++#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
++#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
++#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
++#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
++#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
++#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
++#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
++#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
++#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
++#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
++#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
++#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
++#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
++#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
++#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
++#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
++#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
++#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
++#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
++#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
++#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
++#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
++#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
++#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
++#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
++#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
++#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
++#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
++#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
++#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
++#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
++#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
++#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
++#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
++#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
++#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
++#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
++#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
++#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
++#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
++#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
++#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
++#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
++#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
++#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
++#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
++#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
++#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
++#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
++#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
++#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
++#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
++#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
++#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
++#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
++#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
++#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
++#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
++#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
++#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
++#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
++#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
++#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
++#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
++#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
++#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
++#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
++#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
++#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
++#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
++#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
++#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
++#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
++#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
++#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
++#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
++#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
++#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
++#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
++#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
++#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
++#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
++#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
++#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
++#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
++#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
++#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
++#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
++#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
++#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
++#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
++#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
++#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
++#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
++#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
++#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
++#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
++#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
++#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
++#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
++#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
++#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
++#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
++#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
++#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
++#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
++#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
++#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
++#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
++#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
++#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
++#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
++#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
++#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
++#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
++#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
++#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
++#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
++#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
++#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
++#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
++#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
++#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
++#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
++#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
++#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
++#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
++#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
++#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
++#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
++#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
++#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
++#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
++#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
++#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
++#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
++#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
++#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
++#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
++#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
++#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
++#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
++#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
++#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
++#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
++#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
++#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
++#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
++#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
++#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
++#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
++#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
++#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
++#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
++#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
++#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
++#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
++#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
++#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
++#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
++#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
++#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
++#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
++#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
++#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
++#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
++#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
++#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
++#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
++#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
++#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
++#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
++#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
++#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
++#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
++#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
++#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
++#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
++#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
++#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
++#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
++#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
++#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
++#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
++#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
++#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
++#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
++#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
++#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
++#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
++#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
++#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
++#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
++#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
++#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
++#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
++#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
++#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
++#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
++#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
++#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
++#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
++#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
++#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
++#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
++#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
++#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
++#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
++#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
++#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
++#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
++#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
++#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
++#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
++#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
++#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
++#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
++#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
++#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
++#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
++#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
++#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
++#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
++#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
++#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
++#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
++#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
++#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
++#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
++#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
++#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
++#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
++#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
++#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
++#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
++#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
++#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
++#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
++#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
++#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
++#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
++#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
++#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
++#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
++#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
++#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
++#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
++#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
++#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
++#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
++#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
++#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
++#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
++#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
++#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
++#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
++#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
++#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
++#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
++#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
++#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
++#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
++#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
++#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
++#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
++#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
++#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
++#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
++#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
++#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
++#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
++#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
++#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
++#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
++#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
++#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
++#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
++#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
++#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
++#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
++#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
++#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
++#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
++#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
++#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
++#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
++#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
++#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
++#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
++#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
++#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
++#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
++#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
++#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
++#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
++#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
++#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
++#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
++#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
++#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
++#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
++#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
++#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
++#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
++#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
++#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
++#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
++#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
++#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
++#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
++#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
++#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
++#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
++#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
++#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
++#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
++#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
++#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
++#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
++#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
++#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
++#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
++#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
++#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
++#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
++#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
++#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
++#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
++#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
++#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
++#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
++#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
++#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
++#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
++#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
++#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
++#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
++#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
++#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
++#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
++#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
++#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
++#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
++#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
++#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
++#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
++#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
++#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
++#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
++#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
++#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
++#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
++#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
++#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
++#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
++#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
++#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
++#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
++#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
++#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
++#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
++#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
++#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
++#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
++#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
++#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
++#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
++#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
++#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
++#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
++#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
++#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
++#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
++#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
++#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
++#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
++#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
++#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
++#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
++#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
++#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
++#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
++#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
++#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
++#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
++#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
++#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
++#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
++#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
++#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
++#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
++#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
++#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
++#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
++#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
++#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
++#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
++#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
++#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
++#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
++#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
++#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
++#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
++#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
++#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
++#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
++#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
++#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
++#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
++#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
++#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
++#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
++#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
++#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
++#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
++#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
++#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
++#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
++#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
++#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
++#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
++#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
++#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
++#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
++#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
++#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
++#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
++#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
++#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
++#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
++#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
++#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
++#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
++#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
++#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
++#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
++#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
++#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
++#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
++#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
++#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
++#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
++#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
++#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
++#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
++#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
++#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
++#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
++#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
++#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
++#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
++#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
++#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
++#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
++#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
++#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
++#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
++#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
++#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
++#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
++#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
++#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
++#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
++#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
++#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
++#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
++#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
++#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
++#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
++#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
++#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
++#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
++#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
++#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
++#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
++#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
++#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
++#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
++#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
++#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
++#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
++#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
++#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
++#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
++#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
++#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
++#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
++#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
++#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
++#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
++#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
++#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
++#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
++#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
++#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
++#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
++#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
++#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
++#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
++#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
++#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
++#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
++#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
++#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
++#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
++#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
++#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
++#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
++#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
++#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
++#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
++#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
++#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
++#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
++#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
++#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
++#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
++#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
++#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
++#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
++#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
++#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
++#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
++#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
++#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
++#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
++#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
++#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
++#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
++#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
++#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
++#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
++#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
++#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
++#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
++#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
++#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
++#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
++#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
++#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
++#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
++#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
++#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
++#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
++#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
++#define CP_APPEND_DATA__DATA_MASK 0xffffffff
++#define CP_APPEND_DATA__DATA__SHIFT 0x0
++#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
++#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
++#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
++#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
++#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
++#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
++#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
++#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
++#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
++#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
++#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
++#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
++#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
++#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
++#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
++#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
++#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
++#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
++#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
++#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
++#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
++#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
++#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
++#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
++#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
++#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
++#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
++#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
++#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
++#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
++#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
++#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
++#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
++#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
++#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
++#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
++#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
++#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
++#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
++#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
++#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
++#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
++#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
++#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
++#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
++#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
++#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
++#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
++#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
++#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
++#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
++#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
++#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
++#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
++#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
++#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
++#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
++#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
++#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
++#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
++#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
++#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
++#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
++#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
++#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
++#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
++#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
++#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
++#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
++#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
++#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
++#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
++#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
++#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
++#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
++#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
++#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
++#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
++#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
++#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
++#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
++#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
++#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
++#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
++#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
++#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
++#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
++#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
++#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
++#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
++#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
++#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
++#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
++#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
++#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
++#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
++#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
++#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
++#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
++#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
++#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
++#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
++#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
++#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
++#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
++#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
++#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
++#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
++#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
++#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
++#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
++#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
++#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
++#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
++#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
++#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
++#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
++#define CP_COHER_STATUS__MEID_MASK 0x3000000
++#define CP_COHER_STATUS__MEID__SHIFT 0x18
++#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
++#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
++#define CP_COHER_STATUS__STATUS_MASK 0x80000000
++#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
++#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
++#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
++#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
++#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
++#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
++#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
++#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
++#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
++#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
++#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
++#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
++#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
++#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
++#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
++#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
++#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
++#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
++#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
++#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
++#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
++#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
++#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
++#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
++#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
++#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
++#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
++#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
++#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
++#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
++#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
++#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
++#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
++#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
++#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
++#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
++#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
++#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
++#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
++#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
++#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
++#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
++#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
++#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
++#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
++#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
++#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
++#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
++#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
++#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
++#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
++#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
++#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
++#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
++#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
++#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
++#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
++#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
++#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
++#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
++#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
++#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
++#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
++#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
++#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
++#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
++#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
++#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
++#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
++#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
++#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
++#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
++#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
++#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
++#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
++#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
++#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
++#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
++#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
++#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
++#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
++#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
++#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
++#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
++#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
++#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
++#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
++#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
++#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
++#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
++#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
++#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
++#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
++#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
++#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
++#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
++#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
++#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
++#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
++#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
++#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
++#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
++#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
++#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
++#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
++#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
++#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
++#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
++#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
++#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
++#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
++#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
++#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
++#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
++#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
++#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
++#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
++#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
++#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
++#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
++#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
++#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
++#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
++#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
++#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
++#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
++#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
++#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
++#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
++#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
++#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
++#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
++#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
++#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
++#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
++#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
++#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
++#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
++#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
++#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
++#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
++#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
++#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
++#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
++#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
++#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
++#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
++#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
++#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
++#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
++#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
++#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
++#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
++#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
++#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
++#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
++#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
++#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
++#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
++#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
++#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
++#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
++#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
++#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
++#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
++#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
++#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
++#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
++#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
++#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
++#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
++#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
++#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
++#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
++#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
++#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
++#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
++#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
++#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
++#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
++#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
++#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
++#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
++#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
++#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
++#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
++#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
++#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
++#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
++#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
++#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
++#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
++#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
++#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
++#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
++#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
++#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
++#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
++#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
++#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
++#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
++#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
++#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
++#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
++#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
++#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
++#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
++#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
++#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
++#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
++#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
++#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
++#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
++#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
++#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
++#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
++#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
++#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
++#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
++#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
++#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
++#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
++#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
++#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
++#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
++#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
++#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
++#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
++#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
++#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
++#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
++#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
++#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
++#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
++#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
++#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
++#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
++#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
++#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
++#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
++#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
++#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
++#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
++#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
++#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
++#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
++#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
++#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
++#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
++#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
++#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
++#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
++#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
++#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
++#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
++#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
++#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
++#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
++#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
++#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
++#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
++#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
++#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
++#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
++#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
++#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
++#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
++#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
++#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
++#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
++#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
++#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
++#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
++#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
++#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
++#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
++#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
++#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
++#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
++#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
++#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
++#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
++#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
++#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
++#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
++#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
++#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
++#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
++#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
++#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
++#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
++#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
++#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
++#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
++#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
++#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
++#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
++#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
++#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
++#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
++#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
++#define CP_STAT__DC_BUSY_MASK 0x2000
++#define CP_STAT__DC_BUSY__SHIFT 0xd
++#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
++#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
++#define CP_STAT__PFP_BUSY_MASK 0x8000
++#define CP_STAT__PFP_BUSY__SHIFT 0xf
++#define CP_STAT__MEQ_BUSY_MASK 0x10000
++#define CP_STAT__MEQ_BUSY__SHIFT 0x10
++#define CP_STAT__ME_BUSY_MASK 0x20000
++#define CP_STAT__ME_BUSY__SHIFT 0x11
++#define CP_STAT__QUERY_BUSY_MASK 0x40000
++#define CP_STAT__QUERY_BUSY__SHIFT 0x12
++#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
++#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
++#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
++#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
++#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
++#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
++#define CP_STAT__DMA_BUSY_MASK 0x400000
++#define CP_STAT__DMA_BUSY__SHIFT 0x16
++#define CP_STAT__RCIU_BUSY_MASK 0x800000
++#define CP_STAT__RCIU_BUSY__SHIFT 0x17
++#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
++#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
++#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
++#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
++#define CP_STAT__CE_BUSY_MASK 0x4000000
++#define CP_STAT__CE_BUSY__SHIFT 0x1a
++#define CP_STAT__TCIU_BUSY_MASK 0x8000000
++#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
++#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
++#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
++#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
++#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
++#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
++#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
++#define CP_STAT__CP_BUSY_MASK 0x80000000
++#define CP_STAT__CP_BUSY__SHIFT 0x1f
++#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
++#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
++#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
++#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
++#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
++#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
++#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
++#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
++#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
++#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
++#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
++#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
++#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
++#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
++#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
++#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
++#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
++#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
++#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
++#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
++#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
++#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
++#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
++#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
++#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
++#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
++#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
++#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
++#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
++#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
++#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
++#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
++#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
++#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
++#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
++#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
++#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
++#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
++#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
++#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
++#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
++#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
++#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
++#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
++#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
++#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
++#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
++#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
++#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
++#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
++#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
++#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
++#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
++#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
++#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
++#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
++#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
++#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
++#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
++#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
++#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
++#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
++#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
++#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
++#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
++#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
++#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
++#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
++#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
++#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
++#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
++#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
++#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
++#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
++#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
++#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
++#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
++#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
++#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
++#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
++#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
++#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
++#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
++#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
++#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
++#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
++#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
++#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
++#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
++#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
++#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
++#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
++#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
++#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
++#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
++#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
++#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
++#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
++#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
++#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
++#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
++#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
++#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
++#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
++#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
++#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
++#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
++#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
++#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
++#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
++#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
++#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
++#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
++#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
++#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
++#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
++#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
++#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
++#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
++#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
++#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
++#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
++#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
++#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
++#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
++#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
++#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
++#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
++#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
++#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
++#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
++#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
++#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
++#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
++#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
++#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
++#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
++#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
++#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
++#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
++#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
++#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
++#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
++#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
++#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
++#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
++#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
++#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
++#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
++#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
++#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
++#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
++#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
++#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
++#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
++#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
++#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
++#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
++#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
++#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
++#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
++#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
++#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
++#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
++#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
++#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
++#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
++#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
++#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
++#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
++#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
++#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
++#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
++#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
++#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
++#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
++#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
++#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
++#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
++#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
++#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
++#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
++#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
++#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
++#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
++#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
++#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
++#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
++#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
++#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
++#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
++#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
++#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
++#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
++#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
++#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
++#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
++#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
++#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
++#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
++#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
++#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
++#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
++#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
++#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
++#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
++#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
++#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
++#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
++#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
++#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
++#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
++#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
++#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
++#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
++#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
++#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
++#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
++#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
++#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
++#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
++#define CP_RINGID__RINGID_MASK 0x3
++#define CP_RINGID__RINGID__SHIFT 0x0
++#define CP_PIPEID__PIPE_ID_MASK 0x3
++#define CP_PIPEID__PIPE_ID__SHIFT 0x0
++#define CP_VMID__VMID_MASK 0xf
++#define CP_VMID__VMID__SHIFT 0x0
++#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
++#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
++#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
++#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
++#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
++#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
++#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
++#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
++#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
++#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
++#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
++#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
++#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
++#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
++#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
++#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
++#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
++#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
++#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
++#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
++#define CP_HQD_VMID__VMID_MASK 0xf
++#define CP_HQD_VMID__VMID__SHIFT 0x0
++#define CP_HQD_VMID__IB_VMID_MASK 0xf00
++#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
++#define CP_HQD_VMID__VQID_MASK 0x3ff0000
++#define CP_HQD_VMID__VQID__SHIFT 0x10
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
++#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
++#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
++#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
++#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
++#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
++#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
++#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
++#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
++#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
++#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
++#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
++#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
++#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
++#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
++#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
++#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
++#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
++#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
++#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
++#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
++#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
++#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
++#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
++#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
++#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
++#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
++#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
++#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
++#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
++#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
++#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
++#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
++#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
++#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
++#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
++#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
++#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
++#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
++#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
++#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
++#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
++#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
++#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
++#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
++#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
++#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
++#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
++#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
++#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
++#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
++#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
++#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
++#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
++#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
++#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
++#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
++#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
++#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
++#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
++#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
++#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
++#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
++#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
++#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
++#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
++#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
++#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
++#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
++#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
++#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
++#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
++#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
++#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
++#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
++#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
++#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
++#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
++#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
++#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
++#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
++#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
++#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
++#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
++#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
++#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
++#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
++#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
++#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
++#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
++#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
++#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
++#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
++#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
++#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
++#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
++#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
++#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
++#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
++#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
++#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
++#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
++#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
++#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
++#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
++#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
++#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
++#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
++#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
++#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
++#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
++#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
++#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
++#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
++#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
++#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
++#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
++#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
++#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
++#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
++#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
++#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
++#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
++#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
++#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
++#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
++#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
++#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
++#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
++#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
++#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
++#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
++#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
++#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
++#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
++#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
++#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
++#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
++#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
++#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
++#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
++#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
++#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
++#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
++#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
++#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
++#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
++#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
++#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
++#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
++#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
++#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
++#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
++#define CP_MQD_CONTROL__VMID_MASK 0xf
++#define CP_MQD_CONTROL__VMID__SHIFT 0x0
++#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
++#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
++#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
++#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
++#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
++#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
++#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
++#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
++#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
++#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
++#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
++#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
++#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
++#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
++#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
++#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
++#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
++#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
++#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
++#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
++#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
++#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
++#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
++#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
++#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
++#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
++#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
++#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
++#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
++#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
++#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
++#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
++#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
++#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
++#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
++#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
++#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
++#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
++#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
++#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
++#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
++#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
++#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
++#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
++#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
++#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
++#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
++#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
++#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
++#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
++#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
++#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
++#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
++#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
++#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
++#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
++#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
++#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
++#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
++#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
++#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
++#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
++#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
++#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
++#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
++#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
++#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
++#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
++#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
++#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
++#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
++#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
++#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
++#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
++#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
++#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
++#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
++#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
++#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
++#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
++#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
++#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
++#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
++#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
++#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
++#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
++#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
++#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
++#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
++#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
++#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
++#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
++#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
++#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
++#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
++#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
++#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
++#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
++#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
++#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
++#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
++#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
++#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
++#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
++#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
++#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
++#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
++#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
++#define DB_Z_INFO__FORMAT_MASK 0x3
++#define DB_Z_INFO__FORMAT__SHIFT 0x0
++#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
++#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
++#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
++#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
++#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
++#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
++#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
++#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
++#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
++#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
++#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
++#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
++#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
++#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
++#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
++#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
++#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
++#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
++#define DB_STENCIL_INFO__FORMAT_MASK 0x1
++#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
++#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
++#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
++#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
++#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
++#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
++#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
++#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
++#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
++#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
++#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
++#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
++#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
++#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
++#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
++#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
++#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
++#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
++#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
++#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
++#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
++#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
++#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
++#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
++#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
++#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
++#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
++#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
++#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
++#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
++#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
++#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
++#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
++#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
++#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
++#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
++#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
++#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
++#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
++#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
++#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
++#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
++#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
++#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
++#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
++#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
++#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
++#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
++#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
++#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
++#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
++#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
++#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
++#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
++#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
++#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
++#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
++#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
++#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
++#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
++#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
++#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
++#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
++#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
++#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
++#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
++#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
++#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
++#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
++#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
++#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
++#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
++#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
++#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
++#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
++#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
++#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
++#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
++#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
++#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
++#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
++#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
++#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
++#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
++#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
++#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
++#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
++#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
++#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
++#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
++#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
++#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
++#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
++#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
++#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
++#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
++#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
++#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
++#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
++#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
++#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
++#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
++#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
++#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
++#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
++#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
++#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
++#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
++#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
++#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
++#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
++#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
++#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
++#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
++#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
++#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
++#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
++#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
++#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
++#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
++#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
++#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
++#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
++#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
++#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
++#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
++#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
++#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
++#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
++#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
++#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
++#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
++#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
++#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
++#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
++#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
++#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
++#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
++#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
++#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
++#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
++#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
++#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
++#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
++#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
++#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
++#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
++#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
++#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
++#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
++#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
++#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
++#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
++#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
++#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
++#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
++#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
++#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
++#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
++#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
++#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
++#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
++#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
++#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
++#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
++#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
++#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
++#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
++#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
++#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
++#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
++#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
++#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
++#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
++#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
++#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
++#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
++#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
++#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
++#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
++#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
++#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
++#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
++#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
++#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
++#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
++#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
++#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
++#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
++#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
++#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
++#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
++#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
++#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
++#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
++#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
++#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
++#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
++#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
++#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
++#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
++#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
++#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
++#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
++#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
++#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
++#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
++#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
++#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
++#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
++#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
++#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
++#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
++#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
++#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
++#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
++#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
++#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
++#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
++#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
++#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
++#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
++#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
++#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
++#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
++#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
++#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
++#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
++#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
++#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
++#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
++#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
++#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
++#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
++#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
++#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
++#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
++#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
++#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
++#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
++#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
++#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
++#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
++#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
++#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
++#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
++#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
++#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
++#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
++#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
++#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
++#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
++#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
++#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
++#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
++#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
++#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
++#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
++#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
++#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
++#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
++#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
++#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
++#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
++#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
++#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
++#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
++#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
++#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
++#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
++#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
++#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
++#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
++#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
++#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
++#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
++#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
++#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
++#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
++#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
++#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
++#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
++#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
++#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
++#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
++#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
++#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
++#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
++#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
++#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
++#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
++#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
++#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
++#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
++#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
++#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
++#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
++#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
++#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
++#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
++#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
++#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
++#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
++#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
++#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
++#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
++#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
++#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
++#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
++#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
++#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
++#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
++#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
++#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
++#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
++#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
++#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
++#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
++#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
++#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
++#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
++#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
++#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
++#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
++#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
++#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
++#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
++#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
++#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
++#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
++#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
++#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
++#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
++#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
++#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
++#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
++#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
++#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
++#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
++#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
++#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
++#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
++#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
++#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
++#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
++#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
++#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
++#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
++#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
++#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
++#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
++#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
++#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
++#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
++#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
++#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
++#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
++#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
++#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
++#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
++#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
++#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
++#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
++#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
++#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
++#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
++#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
++#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
++#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
++#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
++#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
++#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
++#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
++#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
++#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
++#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
++#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
++#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
++#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
++#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
++#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
++#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
++#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
++#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
++#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
++#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
++#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
++#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
++#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
++#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
++#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
++#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
++#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
++#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
++#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
++#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
++#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
++#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
++#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
++#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
++#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
++#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
++#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
++#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
++#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
++#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
++#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
++#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
++#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
++#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
++#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
++#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
++#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
++#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
++#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
++#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
++#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
++#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
++#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
++#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
++#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
++#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
++#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
++#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
++#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
++#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
++#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
++#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
++#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
++#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
++#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
++#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
++#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
++#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
++#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
++#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
++#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
++#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
++#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
++#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
++#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
++#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
++#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
++#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
++#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
++#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
++#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
++#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
++#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
++#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
++#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
++#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
++#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
++#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
++#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
++#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
++#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
++#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
++#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
++#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
++#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
++#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
++#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
++#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
++#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
++#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
++#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
++#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
++#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
++#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
++#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
++#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
++#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
++#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
++#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
++#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
++#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
++#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
++#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
++#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
++#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
++#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
++#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
++#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
++#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
++#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
++#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
++#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
++#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
++#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
++#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
++#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
++#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
++#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
++#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
++#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
++#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
++#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
++#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
++#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
++#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
++#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
++#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
++#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
++#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
++#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
++#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
++#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
++#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
++#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
++#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
++#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
++#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
++#define GB_GPU_ID__GPU_ID_MASK 0xf
++#define GB_GPU_ID__GPU_ID__SHIFT 0x0
++#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
++#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
++#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
++#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
++#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
++#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
++#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
++#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
++#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
++#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
++#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
++#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
++#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
++#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
++#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
++#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
++#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
++#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
++#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
++#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
++#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
++#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
++#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
++#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
++#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
++#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
++#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
++#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
++#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
++#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
++#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
++#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
++#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
++#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
++#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
++#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
++#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
++#define GB_EDC_MODE__DED_MODE_MASK 0x300000
++#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
++#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
++#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
++#define GB_EDC_MODE__BYPASS_MASK 0x80000000
++#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
++#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
++#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
++#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
++#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
++#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
++#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
++#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
++#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
++#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
++#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
++#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
++#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
++#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
++#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
++#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
++#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
++#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
++#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
++#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
++#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
++#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
++#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
++#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
++#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
++#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
++#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
++#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
++#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
++#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
++#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
++#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
++#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
++#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
++#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
++#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
++#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
++#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
++#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
++#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
++#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
++#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
++#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
++#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
++#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
++#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
++#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
++#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
++#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
++#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
++#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
++#define GRBM_STATUS__TA_BUSY_MASK 0x4000
++#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
++#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
++#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
++#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
++#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
++#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
++#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
++#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
++#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
++#define GRBM_STATUS__IA_BUSY_MASK 0x80000
++#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
++#define GRBM_STATUS__SX_BUSY_MASK 0x100000
++#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
++#define GRBM_STATUS__WD_BUSY_MASK 0x200000
++#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
++#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
++#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
++#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
++#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
++#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
++#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
++#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
++#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
++#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
++#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
++#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
++#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
++#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
++#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
++#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
++#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
++#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
++#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
++#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
++#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
++#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
++#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
++#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
++#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
++#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
++#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
++#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
++#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
++#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
++#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
++#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
++#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
++#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
++#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
++#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
++#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
++#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
++#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
++#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
++#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
++#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
++#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
++#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
++#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
++#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
++#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
++#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
++#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
++#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
++#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
++#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
++#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
++#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
++#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
++#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
++#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
++#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
++#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
++#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
++#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
++#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
++#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
++#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
++#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
++#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
++#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
++#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
++#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
++#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
++#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
++#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
++#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
++#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
++#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
++#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
++#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
++#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
++#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
++#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
++#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
++#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
++#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
++#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
++#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
++#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
++#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
++#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
++#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
++#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
++#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
++#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
++#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
++#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
++#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
++#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
++#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
++#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
++#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
++#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
++#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
++#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
++#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
++#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
++#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
++#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
++#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
++#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
++#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
++#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
++#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
++#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
++#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
++#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
++#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
++#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
++#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
++#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
++#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
++#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
++#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
++#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
++#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
++#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
++#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
++#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
++#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
++#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
++#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
++#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
++#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
++#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
++#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
++#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
++#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
++#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
++#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
++#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
++#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
++#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
++#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
++#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
++#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
++#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
++#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
++#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
++#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
++#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
++#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
++#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
++#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
++#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
++#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
++#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
++#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
++#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
++#define GRBM_TRAP_OP__RW_MASK 0x1
++#define GRBM_TRAP_OP__RW__SHIFT 0x0
++#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
++#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
++#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
++#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
++#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
++#define GRBM_TRAP_WD__DATA__SHIFT 0x0
++#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
++#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
++#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
++#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
++#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
++#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
++#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
++#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
++#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
++#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
++#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
++#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
++#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
++#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
++#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
++#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
++#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
++#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
++#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
++#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
++#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
++#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
++#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
++#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
++#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
++#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
++#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
++#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
++#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
++#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
++#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
++#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
++#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
++#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
++#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
++#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
++#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
++#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
++#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
++#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
++#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
++#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
++#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
++#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
++#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
++#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
++#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
++#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
++#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
++#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
++#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
++#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
++#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
++#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
++#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
++#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
++#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
++#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
++#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
++#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
++#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
++#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
++#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
++#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
++#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
++#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
++#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
++#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
++#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
++#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
++#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
++#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
++#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
++#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
++#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
++#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
++#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
++#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
++#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
++#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
++#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
++#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
++#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
++#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
++#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
++#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
++#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
++#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
++#define GRBM_NOWHERE__DATA_MASK 0xffffffff
++#define GRBM_NOWHERE__DATA__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
++#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
++#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
++#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
++#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
++#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
++#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
++#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
++#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
++#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
++#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
++#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
++#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
++#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
++#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
++#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
++#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
++#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
++#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
++#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
++#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
++#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
++#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
++#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
++#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
++#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
++#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
++#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
++#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
++#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
++#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
++#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
++#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
++#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
++#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
++#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
++#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
++#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
++#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
++#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
++#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
++#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
++#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
++#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
++#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
++#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
++#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
++#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
++#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
++#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
++#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
++#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
++#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
++#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
++#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
++#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
++#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
++#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
++#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
++#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
++#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
++#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
++#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
++#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
++#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
++#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
++#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
++#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
++#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
++#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
++#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
++#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
++#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
++#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
++#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
++#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
++#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
++#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
++#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
++#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
++#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
++#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
++#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
++#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
++#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
++#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
++#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
++#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
++#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
++#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
++#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
++#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
++#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
++#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
++#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
++#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
++#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
++#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
++#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
++#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
++#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
++#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
++#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
++#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
++#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
++#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
++#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
++#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
++#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
++#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
++#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
++#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
++#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
++#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
++#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
++#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
++#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
++#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
++#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
++#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
++#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
++#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
++#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
++#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
++#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
++#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
++#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
++#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
++#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
++#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
++#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
++#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
++#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
++#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
++#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
++#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
++#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
++#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
++#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
++#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
++#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
++#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
++#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
++#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
++#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
++#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
++#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
++#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
++#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
++#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
++#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
++#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
++#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
++#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
++#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
++#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
++#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
++#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
++#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
++#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
++#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
++#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
++#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
++#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
++#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
++#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
++#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
++#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
++#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
++#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
++#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
++#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
++#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
++#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
++#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
++#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
++#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
++#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
++#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
++#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
++#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
++#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
++#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
++#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
++#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
++#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
++#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
++#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
++#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
++#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
++#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
++#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
++#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
++#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
++#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
++#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
++#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
++#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
++#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
++#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
++#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
++#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
++#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
++#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
++#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
++#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
++#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
++#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
++#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
++#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
++#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
++#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
++#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
++#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
++#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
++#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
++#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
++#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
++#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
++#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
++#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
++#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
++#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
++#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
++#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
++#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
++#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
++#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
++#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
++#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
++#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
++#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
++#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
++#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
++#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
++#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
++#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
++#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
++#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
++#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
++#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
++#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
++#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
++#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
++#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
++#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
++#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
++#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
++#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
++#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
++#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
++#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
++#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
++#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
++#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
++#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
++#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
++#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
++#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
++#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
++#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
++#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
++#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
++#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
++#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
++#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
++#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
++#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
++#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
++#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
++#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
++#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
++#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
++#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
++#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
++#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
++#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
++#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
++#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
++#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
++#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
++#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
++#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
++#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
++#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
++#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
++#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
++#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
++#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
++#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
++#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
++#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
++#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
++#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
++#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
++#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
++#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
++#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
++#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
++#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
++#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
++#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
++#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
++#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
++#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
++#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
++#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
++#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
++#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
++#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
++#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
++#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
++#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
++#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
++#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
++#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
++#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
++#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
++#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
++#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
++#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
++#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
++#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
++#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
++#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
++#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
++#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
++#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
++#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
++#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
++#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
++#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
++#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
++#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
++#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
++#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
++#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
++#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
++#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
++#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
++#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
++#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
++#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
++#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
++#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
++#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
++#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
++#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
++#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
++#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
++#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
++#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
++#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
++#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
++#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
++#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
++#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
++#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
++#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
++#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
++#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
++#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
++#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
++#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
++#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
++#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
++#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
++#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
++#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
++#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
++#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
++#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
++#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
++#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
++#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
++#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
++#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
++#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
++#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
++#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
++#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
++#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
++#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
++#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
++#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
++#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
++#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
++#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
++#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
++#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
++#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
++#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
++#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
++#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
++#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
++#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
++#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
++#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
++#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
++#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
++#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
++#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
++#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
++#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
++#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
++#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
++#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
++#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
++#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
++#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
++#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
++#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
++#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
++#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
++#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
++#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
++#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
++#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
++#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
++#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
++#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
++#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
++#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
++#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
++#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
++#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
++#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
++#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
++#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
++#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
++#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
++#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
++#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
++#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
++#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
++#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
++#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
++#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
++#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
++#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
++#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
++#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
++#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
++#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
++#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
++#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
++#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
++#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
++#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
++#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
++#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
++#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
++#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
++#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
++#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
++#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
++#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
++#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
++#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
++#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
++#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
++#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
++#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
++#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
++#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
++#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
++#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
++#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
++#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
++#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
++#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
++#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
++#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
++#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
++#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
++#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
++#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
++#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
++#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
++#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
++#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
++#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
++#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
++#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
++#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
++#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
++#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
++#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
++#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
++#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
++#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
++#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
++#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
++#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
++#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
++#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
++#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
++#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
++#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
++#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
++#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
++#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
++#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
++#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
++#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
++#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
++#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
++#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
++#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
++#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
++#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
++#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
++#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
++#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
++#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
++#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
++#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
++#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
++#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
++#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
++#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
++#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
++#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
++#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
++#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
++#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
++#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
++#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
++#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
++#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
++#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
++#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
++#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
++#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
++#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
++#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
++#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
++#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
++#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
++#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
++#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
++#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
++#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
++#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
++#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
++#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
++#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
++#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
++#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
++#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
++#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
++#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
++#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
++#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
++#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
++#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
++#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
++#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
++#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
++#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
++#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
++#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
++#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
++#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
++#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
++#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
++#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
++#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
++#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
++#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
++#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
++#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
++#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
++#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
++#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
++#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
++#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
++#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
++#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
++#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
++#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
++#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
++#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
++#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
++#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
++#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
++#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
++#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
++#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
++#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
++#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
++#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
++#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
++#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
++#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
++#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
++#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
++#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
++#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
++#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
++#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
++#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
++#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
++#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
++#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
++#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
++#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
++#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
++#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
++#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
++#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
++#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
++#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
++#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
++#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
++#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
++#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
++#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
++#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
++#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
++#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
++#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
++#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
++#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
++#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
++#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
++#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
++#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
++#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
++#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
++#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
++#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
++#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
++#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
++#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
++#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
++#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
++#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
++#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
++#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
++#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
++#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
++#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
++#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
++#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
++#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
++#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
++#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
++#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
++#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
++#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
++#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
++#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
++#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
++#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
++#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
++#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
++#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
++#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
++#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
++#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
++#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
++#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
++#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
++#define COMPUTE_START_X__START_MASK 0xffffffff
++#define COMPUTE_START_X__START__SHIFT 0x0
++#define COMPUTE_START_Y__START_MASK 0xffffffff
++#define COMPUTE_START_Y__START__SHIFT 0x0
++#define COMPUTE_START_Z__START_MASK 0xffffffff
++#define COMPUTE_START_Z__START__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
++#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
++#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
++#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
++#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
++#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
++#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
++#define COMPUTE_PGM_HI__DATA_MASK 0xff
++#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
++#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
++#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
++#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
++#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
++#define COMPUTE_TBA_HI__DATA_MASK 0xff
++#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
++#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
++#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
++#define COMPUTE_TMA_HI__DATA_MASK 0xff
++#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
++#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
++#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
++#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
++#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
++#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
++#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
++#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
++#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
++#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
++#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
++#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
++#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
++#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
++#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
++#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
++#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
++#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
++#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
++#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
++#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
++#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
++#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
++#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
++#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
++#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
++#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
++#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
++#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
++#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
++#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
++#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
++#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
++#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
++#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
++#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
++#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
++#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
++#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
++#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
++#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
++#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
++#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
++#define COMPUTE_VMID__DATA_MASK 0xf
++#define COMPUTE_VMID__DATA__SHIFT 0x0
++#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
++#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
++#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
++#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
++#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
++#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
++#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
++#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
++#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
++#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
++#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
++#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
++#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
++#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
++#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
++#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
++#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
++#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
++#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
++#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
++#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
++#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
++#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
++#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
++#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
++#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
++#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
++#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
++#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
++#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
++#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
++#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
++#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
++#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
++#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
++#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
++#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
++#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
++#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
++#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
++#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
++#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
++#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
++#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
++#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
++#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
++#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
++#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
++#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
++#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
++#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
++#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
++#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
++#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
++#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
++#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
++#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
++#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
++#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
++#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
++#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
++#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
++#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
++#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
++#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
++#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
++#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
++#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
++#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
++#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
++#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
++#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
++#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
++#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
++#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
++#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
++#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
++#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
++#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
++#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
++#define RLC_CNTL__FORCE_RETRY_MASK 0x2
++#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
++#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
++#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
++#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
++#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
++#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
++#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
++#define RLC_CNTL__RESERVED_MASK 0xffffff00
++#define RLC_CNTL__RESERVED__SHIFT 0x8
++#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
++#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
++#define RLC_DEBUG__DATA_MASK 0xffffffff
++#define RLC_DEBUG__DATA__SHIFT 0x0
++#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
++#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
++#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
++#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
++#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
++#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
++#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
++#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
++#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
++#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
++#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
++#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
++#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
++#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
++#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
++#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
++#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
++#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
++#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
++#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
++#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
++#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
++#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
++#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
++#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
++#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
++#define RLC_STAT__RLC_BUSY_MASK 0x1
++#define RLC_STAT__RLC_BUSY__SHIFT 0x0
++#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
++#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
++#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
++#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
++#define RLC_STAT__RESERVED_MASK 0xfffffff8
++#define RLC_STAT__RESERVED__SHIFT 0x3
++#define RLC_SAFE_MODE__CMD_MASK 0x1
++#define RLC_SAFE_MODE__CMD__SHIFT 0x0
++#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
++#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
++#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
++#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
++#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
++#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
++#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
++#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
++#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
++#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
++#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
++#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
++#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
++#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
++#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
++#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
++#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
++#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
++#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
++#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
++#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
++#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
++#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
++#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
++#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
++#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
++#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
++#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
++#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
++#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
++#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
++#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
++#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
++#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
++#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
++#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
++#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
++#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
++#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
++#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
++#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
++#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
++#define RLC_RLCV_COMMAND__CMD_MASK 0xf
++#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
++#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
++#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
++#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
++#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
++#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
++#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
++#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
++#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
++#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
++#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
++#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
++#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
++#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
++#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
++#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
++#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
++#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
++#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
++#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
++#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
++#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
++#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
++#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
++#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
++#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
++#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
++#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
++#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
++#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
++#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
++#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
++#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
++#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
++#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
++#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
++#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
++#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
++#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
++#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
++#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
++#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
++#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
++#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
++#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
++#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
++#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
++#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
++#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
++#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
++#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
++#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
++#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
++#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
++#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
++#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
++#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
++#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
++#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
++#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
++#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
++#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
++#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
++#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
++#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
++#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
++#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
++#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
++#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
++#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
++#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
++#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
++#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
++#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
++#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
++#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
++#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
++#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
++#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
++#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
++#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
++#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
++#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
++#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
++#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
++#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
++#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
++#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
++#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
++#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
++#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
++#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
++#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
++#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
++#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
++#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
++#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
++#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
++#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
++#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
++#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
++#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
++#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
++#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
++#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
++#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
++#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
++#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
++#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
++#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
++#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
++#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
++#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
++#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
++#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000
++#define RLC_GPM_STAT__RESERVED__SHIFT 0x12
++#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
++#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
++#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
++#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
++#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
++#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
++#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
++#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
++#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
++#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
++#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
++#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
++#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
++#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
++#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
++#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
++#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
++#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
++#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
++#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
++#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
++#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
++#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
++#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
++#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
++#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
++#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
++#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
++#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000
++#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
++#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
++#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
++#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
++#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
++#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
++#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
++#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
++#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
++#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
++#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
++#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
++#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
++#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
++#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
++#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
++#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
++#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
++#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
++#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
++#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
++#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
++#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
++#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
++#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
++#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
++#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
++#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
++#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
++#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
++#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
++#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
++#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
++#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
++#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
++#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
++#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
++#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
++#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
++#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
++#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
++#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
++#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
++#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
++#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
++#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
++#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
++#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
++#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
++#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
++#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
++#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
++#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
++#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
++#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
++#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
++#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
++#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
++#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
++#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
++#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
++#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
++#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
++#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
++#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
++#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
++#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
++#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
++#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
++#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
++#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
++#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
++#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
++#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
++#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
++#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
++#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
++#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
++#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
++#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
++#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
++#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
++#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
++#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
++#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
++#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
++#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
++#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
++#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
++#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
++#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
++#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
++#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
++#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
++#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
++#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
++#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
++#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
++#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
++#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
++#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
++#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
++#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
++#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
++#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
++#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
++#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
++#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
++#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
++#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
++#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
++#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
++#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
++#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
++#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
++#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
++#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
++#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
++#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
++#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
++#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
++#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
++#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
++#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
++#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
++#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
++#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
++#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
++#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
++#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
++#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
++#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
++#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
++#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
++#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
++#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
++#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
++#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
++#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
++#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
++#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
++#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
++#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
++#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
++#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
++#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
++#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
++#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
++#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
++#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
++#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
++#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
++#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
++#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
++#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
++#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
++#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
++#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
++#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
++#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
++#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
++#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
++#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
++#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
++#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
++#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
++#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
++#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
++#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
++#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
++#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
++#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
++#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
++#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
++#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
++#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
++#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
++#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
++#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
++#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
++#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
++#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
++#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
++#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
++#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
++#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
++#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
++#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
++#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
++#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
++#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
++#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
++#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
++#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
++#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
++#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
++#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
++#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
++#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
++#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
++#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
++#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
++#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
++#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
++#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
++#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
++#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
++#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
++#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
++#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
++#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
++#define RLC_GPR_REG1__DATA_MASK 0xffffffff
++#define RLC_GPR_REG1__DATA__SHIFT 0x0
++#define RLC_GPR_REG2__DATA_MASK 0xffffffff
++#define RLC_GPR_REG2__DATA__SHIFT 0x0
++#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
++#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
++#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
++#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
++#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
++#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
++#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
++#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
++#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
++#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
++#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
++#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf
++#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
++#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
++#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
++#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
++#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
++#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
++#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
++#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
++#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
++#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
++#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
++#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
++#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
++#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
++#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
++#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
++#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
++#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
++#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
++#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
++#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
++#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
++#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
++#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
++#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
++#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
++#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
++#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
++#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
++#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
++#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
++#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
++#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
++#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
++#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
++#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
++#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
++#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00
++#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
++#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
++#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
++#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
++#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
++#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
++#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
++#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
++#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
++#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
++#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
++#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
++#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
++#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
++#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
++#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
++#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
++#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
++#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
++#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
++#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
++#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff
++#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
++#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00
++#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa
++#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
++#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
++#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff
++#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
++#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
++#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
++#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
++#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
++#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
++#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
++#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
++#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
++#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
++#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
++#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
++#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
++#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
++#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
++#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
++#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
++#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
++#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
++#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
++#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
++#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
++#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
++#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
++#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
++#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
++#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
++#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
++#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
++#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
++#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
++#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
++#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
++#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
++#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
++#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
++#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
++#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
++#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
++#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
++#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
++#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
++#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
++#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
++#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
++#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
++#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
++#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
++#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
++#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
++#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
++#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
++#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
++#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
++#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
++#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
++#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
++#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
++#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
++#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
++#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
++#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
++#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
++#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
++#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
++#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
++#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
++#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
++#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
++#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
++#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
++#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
++#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
++#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
++#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
++#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
++#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
++#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
++#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
++#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
++#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
++#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
++#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
++#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
++#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
++#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
++#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
++#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
++#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
++#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
++#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
++#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
++#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
++#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
++#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
++#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
++#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
++#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
++#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
++#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
++#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf
++#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10
++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20
++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
++#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0
++#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
++#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00
++#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000
++#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000
++#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
++#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf
++#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0
++#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
++#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f
++#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80
++#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
++#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300
++#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00
++#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
++#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff
++#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff
++#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00
++#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000
++#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc
++#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff
++#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000
++#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff
++#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000
++#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000
++#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000
++#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000
++#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18
++#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
++#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
++#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
++#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
++#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
++#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
++#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf
++#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0
++#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0
++#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4
++#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700
++#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8
++#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800
++#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb
++#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
++#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
++#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000
++#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
++#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
++#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
++#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff
++#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
++#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
++#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
++#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff
++#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
++#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1
++#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
++#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe
++#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
++#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1
++#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
++#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe
++#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
++#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1
++#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe
++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
++#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100
++#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00
++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
++#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000
++#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000
++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
++#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1
++#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe
++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
++#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100
++#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00
++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
++#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000
++#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000
++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
++#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff
++#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
++#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff
++#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
++#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000
++#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
++#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000
++#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
++#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
++#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
++#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff
++#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
++#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff
++#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
++#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
++#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
++#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
++#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
++#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff
++#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0
++#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff
++#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
++#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff
++#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
++#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff
++#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0
++#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff
++#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
++#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
++#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
++#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
++#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
++#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
++#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
++#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
++#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
++#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
++#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
++#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
++#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
++#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
++#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
++#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
++#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
++#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
++#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
++#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
++#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
++#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
++#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
++#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
++#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
++#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
++#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
++#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
++#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
++#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
++#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
++#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
++#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
++#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
++#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
++#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
++#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
++#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
++#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
++#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
++#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
++#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
++#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
++#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
++#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
++#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
++#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
++#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
++#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
++#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
++#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
++#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
++#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
++#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
++#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
++#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
++#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
++#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
++#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
++#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
++#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
++#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
++#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
++#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
++#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
++#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
++#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
++#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
++#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
++#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
++#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
++#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
++#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
++#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
++#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
++#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
++#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
++#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
++#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
++#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
++#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
++#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
++#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
++#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
++#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
++#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
++#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
++#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
++#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
++#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
++#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
++#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
++#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
++#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
++#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
++#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
++#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
++#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
++#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
++#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
++#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
++#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
++#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
++#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
++#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
++#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
++#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
++#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
++#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
++#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
++#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
++#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
++#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
++#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
++#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
++#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
++#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
++#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
++#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
++#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
++#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
++#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
++#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
++#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
++#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
++#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
++#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
++#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
++#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
++#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
++#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
++#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
++#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
++#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
++#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
++#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
++#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
++#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
++#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
++#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
++#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
++#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
++#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
++#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
++#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
++#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
++#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
++#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
++#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
++#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
++#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
++#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
++#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
++#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
++#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
++#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
++#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
++#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
++#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
++#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
++#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
++#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
++#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
++#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
++#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
++#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
++#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
++#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
++#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
++#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
++#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
++#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
++#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
++#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
++#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
++#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
++#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
++#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
++#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
++#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
++#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
++#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
++#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
++#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
++#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
++#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
++#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
++#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
++#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
++#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
++#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
++#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
++#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
++#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
++#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
++#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
++#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
++#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
++#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
++#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
++#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
++#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
++#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
++#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
++#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
++#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
++#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
++#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
++#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
++#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
++#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
++#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
++#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
++#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
++#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
++#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
++#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
++#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
++#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
++#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
++#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
++#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
++#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
++#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
++#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
++#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
++#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
++#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
++#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
++#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
++#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
++#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
++#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
++#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
++#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
++#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
++#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
++#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
++#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe
++#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
++#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000
++#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
++#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000
++#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
++#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1
++#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2
++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
++#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4
++#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000
++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
++#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000
++#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
++#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
++#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
++#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3
++#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
++#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc
++#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
++#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30
++#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
++#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1
++#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
++#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
++#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
++#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
++#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
++#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
++#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
++#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
++#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
++#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
++#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
++#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
++#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
++#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
++#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
++#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
++#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
++#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
++#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
++#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
++#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
++#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
++#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
++#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
++#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
++#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
++#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
++#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
++#define SPI_DEBUG_READ__DATA_MASK 0xffffff
++#define SPI_DEBUG_READ__DATA__SHIFT 0x0
++#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1
++#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0
++#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2
++#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1
++#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4
++#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2
++#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8
++#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
++#define SPI_EDC_CNT__SED_MASK 0xff
++#define SPI_EDC_CNT__SED__SHIFT 0x0
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
++#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
++#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
++#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
++#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
++#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
++#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
++#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
++#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
++#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
++#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
++#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
++#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
++#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
++#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
++#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
++#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
++#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
++#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
++#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
++#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
++#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
++#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
++#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
++#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
++#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
++#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
++#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
++#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
++#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
++#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
++#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
++#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
++#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
++#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
++#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
++#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
++#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
++#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
++#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
++#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
++#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
++#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
++#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
++#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
++#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
++#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
++#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
++#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
++#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
++#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
++#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
++#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
++#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
++#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
++#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
++#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
++#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
++#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
++#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
++#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
++#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
++#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
++#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
++#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
++#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
++#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
++#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
++#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
++#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
++#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
++#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
++#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
++#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
++#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
++#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf
++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0
++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
++#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
++#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
++#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
++#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
++#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
++#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
++#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
++#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
++#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
++#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
++#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
++#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
++#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
++#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
++#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
++#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
++#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
++#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
++#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
++#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
++#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
++#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
++#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
++#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
++#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
++#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
++#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
++#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
++#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
++#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
++#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
++#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
++#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
++#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
++#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
++#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
++#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
++#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
++#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
++#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
++#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
++#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
++#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
++#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
++#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
++#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
++#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
++#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
++#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
++#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
++#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
++#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
++#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
++#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
++#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
++#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
++#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
++#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
++#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
++#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
++#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
++#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
++#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
++#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
++#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
++#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
++#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
++#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
++#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
++#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
++#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
++#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
++#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
++#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
++#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
++#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
++#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
++#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
++#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
++#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
++#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
++#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
++#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
++#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
++#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
++#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
++#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
++#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
++#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
++#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
++#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
++#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
++#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
++#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
++#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
++#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
++#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
++#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
++#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
++#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
++#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
++#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
++#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
++#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
++#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
++#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
++#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
++#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
++#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
++#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
++#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
++#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000
++#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16
++#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
++#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
++#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
++#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
++#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
++#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
++#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
++#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
++#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
++#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
++#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
++#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
++#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
++#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
++#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
++#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
++#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
++#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
++#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
++#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
++#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
++#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
++#define BCI_DEBUG_READ__DATA_MASK 0xffffff
++#define BCI_DEBUG_READ__DATA__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
++#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
++#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
++#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
++#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
++#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
++#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
++#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
++#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
++#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
++#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
++#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
++#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
++#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
++#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
++#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
++#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
++#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
++#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
++#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
++#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
++#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
++#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
++#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
++#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
++#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
++#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000
++#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
++#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
++#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
++#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
++#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
++#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
++#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
++#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
++#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000
++#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
++#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
++#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
++#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
++#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
++#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
++#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
++#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
++#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
++#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
++#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
++#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
++#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
++#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000
++#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
++#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
++#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
++#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
++#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
++#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
++#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
++#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
++#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
++#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00
++#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
++#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
++#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
++#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
++#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
++#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
++#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
++#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
++#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
++#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
++#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
++#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
++#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
++#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
++#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
++#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
++#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
++#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
++#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
++#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
++#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
++#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
++#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
++#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
++#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
++#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
++#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
++#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
++#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
++#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
++#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
++#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
++#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
++#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
++#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
++#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
++#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000
++#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
++#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
++#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
++#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
++#define SQ_CONFIG__UNUSED_MASK 0xff
++#define SQ_CONFIG__UNUSED__SHIFT 0x0
++#define SQ_CONFIG__DEBUG_EN_MASK 0x100
++#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
++#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200
++#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
++#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400
++#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
++#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
++#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
++#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
++#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
++#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
++#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
++#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
++#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
++#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000
++#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
++#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000
++#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
++#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000
++#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
++#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000
++#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
++#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000
++#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
++#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
++#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
++#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
++#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
++#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
++#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
++#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
++#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
++#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
++#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
++#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
++#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
++#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
++#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
++#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
++#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
++#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
++#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
++#define SQC_CONFIG__EVICT_LRU_MASK 0x3000
++#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
++#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000
++#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
++#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000
++#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
++#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000
++#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
++#define SQC_CACHES__TARGET_INST_MASK 0x1
++#define SQC_CACHES__TARGET_INST__SHIFT 0x0
++#define SQC_CACHES__TARGET_DATA_MASK 0x2
++#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
++#define SQC_CACHES__INVALIDATE_MASK 0x4
++#define SQC_CACHES__INVALIDATE__SHIFT 0x2
++#define SQC_CACHES__WRITEBACK_MASK 0x8
++#define SQC_CACHES__WRITEBACK__SHIFT 0x3
++#define SQC_CACHES__VOL_MASK 0x10
++#define SQC_CACHES__VOL__SHIFT 0x4
++#define SQC_CACHES__COMPLETE_MASK 0x10000
++#define SQC_CACHES__COMPLETE__SHIFT 0x10
++#define SQC_WRITEBACK__DWB_MASK 0x1
++#define SQC_WRITEBACK__DWB__SHIFT 0x0
++#define SQC_WRITEBACK__DIRTY_MASK 0x2
++#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000
++#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000
++#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000
++#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000
++#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d
++#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
++#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
++#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
++#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
++#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
++#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
++#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
++#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
++#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
++#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
++#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
++#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
++#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
++#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
++#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
++#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
++#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
++#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
++#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
++#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
++#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
++#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
++#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
++#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
++#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
++#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
++#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1
++#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
++#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2
++#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4
++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8
++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100
++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200
++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
++#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400
++#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000
++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000
++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000
++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000
++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000
++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
++#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000
++#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
++#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
++#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
++#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
++#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
++#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
++#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
++#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
++#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
++#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
++#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
++#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
++#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
++#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
++#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
++#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
++#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
++#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
++#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
++#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
++#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
++#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
++#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
++#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
++#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
++#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
++#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
++#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
++#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
++#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
++#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
++#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
++#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
++#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
++#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
++#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
++#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
++#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
++#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
++#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
++#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
++#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
++#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
++#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
++#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
++#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
++#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
++#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
++#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
++#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
++#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
++#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
++#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
++#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
++#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
++#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
++#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
++#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff
++#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
++#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
++#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
++#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
++#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
++#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
++#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
++#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
++#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
++#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
++#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
++#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
++#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
++#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000
++#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
++#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
++#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
++#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
++#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
++#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
++#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
++#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
++#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
++#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
++#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
++#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
++#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
++#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
++#define SQ_TIME_HI__TIME_MASK 0xffffffff
++#define SQ_TIME_HI__TIME__SHIFT 0x0
++#define SQ_TIME_LO__TIME_MASK 0xffffffff
++#define SQ_TIME_LO__TIME__SHIFT 0x0
++#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
++#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
++#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
++#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
++#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
++#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
++#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
++#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
++#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
++#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
++#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
++#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
++#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
++#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
++#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
++#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
++#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
++#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
++#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
++#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
++#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
++#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
++#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
++#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
++#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
++#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
++#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
++#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
++#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
++#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
++#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
++#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
++#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
++#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
++#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
++#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
++#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
++#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
++#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
++#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
++#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
++#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
++#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
++#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
++#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
++#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
++#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
++#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
++#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
++#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
++#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
++#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
++#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
++#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff
++#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
++#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
++#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
++#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
++#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
++#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
++#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
++#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
++#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
++#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
++#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
++#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
++#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
++#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
++#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
++#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
++#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
++#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
++#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
++#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
++#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
++#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
++#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
++#define SQ_LB_CTR_CTRL__START_MASK 0x1
++#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
++#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
++#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
++#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
++#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
++#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
++#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
++#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
++#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
++#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
++#define SQC_EDC_CNT__INST_SEC_MASK 0xff
++#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0
++#define SQC_EDC_CNT__INST_DED_MASK 0xff00
++#define SQC_EDC_CNT__INST_DED__SHIFT 0x8
++#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000
++#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10
++#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000
++#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18
++#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff
++#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
++#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00
++#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
++#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000
++#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
++#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff
++#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
++#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00
++#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
++#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000
++#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
++#define SQ_EDC_INFO__WAVE_ID_MASK 0xf
++#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
++#define SQ_EDC_INFO__SIMD_ID_MASK 0x30
++#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
++#define SQ_EDC_INFO__SOURCE_MASK 0x1c0
++#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
++#define SQ_EDC_INFO__VM_ID_MASK 0x1e00
++#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
++#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
++#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
++#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
++#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
++#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
++#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
++#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
++#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
++#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
++#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
++#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
++#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
++#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
++#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
++#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
++#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
++#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
++#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
++#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
++#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
++#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
++#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
++#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
++#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
++#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
++#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
++#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
++#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
++#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
++#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
++#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
++#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
++#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
++#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
++#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
++#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
++#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
++#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
++#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
++#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
++#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
++#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
++#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
++#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
++#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
++#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
++#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
++#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
++#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
++#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
++#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
++#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
++#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
++#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
++#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
++#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
++#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
++#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
++#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
++#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
++#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
++#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
++#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
++#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
++#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
++#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
++#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
++#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
++#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
++#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
++#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
++#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
++#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
++#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
++#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
++#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
++#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
++#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
++#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
++#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
++#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
++#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
++#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000
++#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
++#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000
++#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
++#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000
++#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
++#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000
++#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
++#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000
++#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
++#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff
++#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
++#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
++#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
++#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
++#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
++#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
++#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
++#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
++#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
++#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
++#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
++#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
++#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
++#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
++#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
++#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
++#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
++#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
++#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
++#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
++#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
++#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
++#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
++#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
++#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
++#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000
++#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
++#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
++#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
++#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
++#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
++#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
++#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
++#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
++#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
++#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
++#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
++#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
++#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
++#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
++#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
++#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
++#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
++#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
++#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
++#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
++#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
++#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
++#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000
++#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
++#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
++#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
++#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
++#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
++#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff
++#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
++#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000
++#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
++#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000
++#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
++#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000
++#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
++#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000
++#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
++#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
++#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
++#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
++#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
++#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
++#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
++#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
++#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
++#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
++#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
++#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
++#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
++#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
++#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
++#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
++#define SQ_IND_INDEX__INDEX__SHIFT 0x10
++#define SQ_CMD__CMD_MASK 0x7
++#define SQ_CMD__CMD__SHIFT 0x0
++#define SQ_CMD__MODE_MASK 0x70
++#define SQ_CMD__MODE__SHIFT 0x4
++#define SQ_CMD__CHECK_VMID_MASK 0x80
++#define SQ_CMD__CHECK_VMID__SHIFT 0x7
++#define SQ_CMD__DATA_MASK 0x700
++#define SQ_CMD__DATA__SHIFT 0x8
++#define SQ_CMD__WAVE_ID_MASK 0xf0000
++#define SQ_CMD__WAVE_ID__SHIFT 0x10
++#define SQ_CMD__SIMD_ID_MASK 0x300000
++#define SQ_CMD__SIMD_ID__SHIFT 0x14
++#define SQ_CMD__QUEUE_ID_MASK 0x7000000
++#define SQ_CMD__QUEUE_ID__SHIFT 0x18
++#define SQ_CMD__VM_ID_MASK 0xf0000000
++#define SQ_CMD__VM_ID__SHIFT 0x1c
++#define SQ_IND_DATA__DATA_MASK 0xffffffff
++#define SQ_IND_DATA__DATA__SHIFT 0x0
++#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
++#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
++#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
++#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
++#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
++#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
++#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
++#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
++#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
++#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
++#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
++#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
++#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
++#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
++#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
++#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
++#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
++#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
++#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
++#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
++#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
++#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
++#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
++#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
++#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
++#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
++#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000
++#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
++#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000
++#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
++#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000
++#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
++#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000
++#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
++#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000
++#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
++#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000
++#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
++#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000
++#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
++#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1
++#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
++#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2
++#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
++#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4
++#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
++#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0
++#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
++#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00
++#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8
++#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
++#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
++#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
++#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
++#define SQ_WAVE_STATUS__SCC_MASK 0x1
++#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
++#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
++#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
++#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18
++#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
++#define SQ_WAVE_STATUS__PRIV_MASK 0x20
++#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
++#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
++#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
++#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
++#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
++#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
++#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
++#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
++#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
++#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
++#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
++#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
++#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
++#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
++#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
++#define SQ_WAVE_STATUS__HALT_MASK 0x2000
++#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
++#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
++#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
++#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
++#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
++#define SQ_WAVE_STATUS__VALID_MASK 0x10000
++#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
++#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
++#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
++#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
++#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
++#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
++#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
++#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
++#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
++#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
++#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
++#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000
++#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
++#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
++#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
++#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
++#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
++#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
++#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
++#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
++#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
++#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
++#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
++#define SQ_WAVE_MODE__IEEE_MASK 0x200
++#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
++#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
++#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
++#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
++#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
++#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
++#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
++#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000
++#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
++#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
++#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
++#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
++#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
++#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
++#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
++#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400
++#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
++#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
++#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
++#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
++#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
++#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
++#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
++#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
++#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
++#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
++#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
++#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
++#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
++#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
++#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
++#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
++#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
++#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
++#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
++#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
++#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
++#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
++#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
++#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
++#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
++#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
++#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
++#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
++#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
++#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
++#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
++#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
++#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
++#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
++#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
++#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
++#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
++#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
++#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
++#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
++#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
++#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
++#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
++#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
++#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
++#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
++#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
++#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000
++#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
++#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000
++#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
++#define SQ_WAVE_M0__M0_MASK 0xffffffff
++#define SQ_WAVE_M0__M0__SHIFT 0x0
++#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
++#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
++#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
++#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
++#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
++#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
++#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
++#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
++#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
++#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
++#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
++#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
++#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
++#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
++#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0
++#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
++#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
++#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
++#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
++#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
++#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
++#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
++#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
++#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
++#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
++#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
++#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
++#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
++#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
++#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
++#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3
++#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
++#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4
++#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2
++#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18
++#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
++#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0
++#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5
++#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700
++#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8
++#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800
++#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb
++#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
++#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
++#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800
++#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
++#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
++#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
++#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
++#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
++#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
++#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
++#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
++#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
++#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
++#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
++#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
++#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
++#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
++#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
++#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff
++#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
++#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff
++#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
++#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000
++#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
++#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000
++#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
++#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000
++#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
++#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000
++#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
++#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff
++#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0
++#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000
++#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12
++#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000
++#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13
++#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000
++#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
++#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000
++#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15
++#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000
++#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17
++#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000
++#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19
++#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000
++#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a
++#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000
++#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b
++#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
++#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
++#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
++#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
++#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff
++#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0
++#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000
++#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10
++#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
++#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
++#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
++#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
++#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
++#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
++#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
++#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
++#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
++#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
++#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
++#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
++#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
++#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
++#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
++#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
++#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
++#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
++#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
++#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
++#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
++#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
++#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
++#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
++#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
++#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
++#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
++#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
++#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
++#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
++#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
++#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
++#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
++#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
++#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
++#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
++#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
++#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
++#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
++#define SQ_SOP2__SSRC0_MASK 0xff
++#define SQ_SOP2__SSRC0__SHIFT 0x0
++#define SQ_SOP2__SSRC1_MASK 0xff00
++#define SQ_SOP2__SSRC1__SHIFT 0x8
++#define SQ_SOP2__SDST_MASK 0x7f0000
++#define SQ_SOP2__SDST__SHIFT 0x10
++#define SQ_SOP2__OP_MASK 0x3f800000
++#define SQ_SOP2__OP__SHIFT 0x17
++#define SQ_SOP2__ENCODING_MASK 0xc0000000
++#define SQ_SOP2__ENCODING__SHIFT 0x1e
++#define SQ_VOP1__SRC0_MASK 0x1ff
++#define SQ_VOP1__SRC0__SHIFT 0x0
++#define SQ_VOP1__OP_MASK 0x1fe00
++#define SQ_VOP1__OP__SHIFT 0x9
++#define SQ_VOP1__VDST_MASK 0x1fe0000
++#define SQ_VOP1__VDST__SHIFT 0x11
++#define SQ_VOP1__ENCODING_MASK 0xfe000000
++#define SQ_VOP1__ENCODING__SHIFT 0x19
++#define SQ_MTBUF_1__VADDR_MASK 0xff
++#define SQ_MTBUF_1__VADDR__SHIFT 0x0
++#define SQ_MTBUF_1__VDATA_MASK 0xff00
++#define SQ_MTBUF_1__VDATA__SHIFT 0x8
++#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
++#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
++#define SQ_MTBUF_1__SLC_MASK 0x400000
++#define SQ_MTBUF_1__SLC__SHIFT 0x16
++#define SQ_MTBUF_1__TFE_MASK 0x800000
++#define SQ_MTBUF_1__TFE__SHIFT 0x17
++#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
++#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
++#define SQ_EXP_1__VSRC0_MASK 0xff
++#define SQ_EXP_1__VSRC0__SHIFT 0x0
++#define SQ_EXP_1__VSRC1_MASK 0xff00
++#define SQ_EXP_1__VSRC1__SHIFT 0x8
++#define SQ_EXP_1__VSRC2_MASK 0xff0000
++#define SQ_EXP_1__VSRC2__SHIFT 0x10
++#define SQ_EXP_1__VSRC3_MASK 0xff000000
++#define SQ_EXP_1__VSRC3__SHIFT 0x18
++#define SQ_MUBUF_1__VADDR_MASK 0xff
++#define SQ_MUBUF_1__VADDR__SHIFT 0x0
++#define SQ_MUBUF_1__VDATA_MASK 0xff00
++#define SQ_MUBUF_1__VDATA__SHIFT 0x8
++#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
++#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
++#define SQ_MUBUF_1__TFE_MASK 0x800000
++#define SQ_MUBUF_1__TFE__SHIFT 0x17
++#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
++#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
++#define SQ_SMEM_1__OFFSET_MASK 0xfffff
++#define SQ_SMEM_1__OFFSET__SHIFT 0x0
++#define SQ_INST__ENCODING_MASK 0xffffffff
++#define SQ_INST__ENCODING__SHIFT 0x0
++#define SQ_EXP_0__EN_MASK 0xf
++#define SQ_EXP_0__EN__SHIFT 0x0
++#define SQ_EXP_0__TGT_MASK 0x3f0
++#define SQ_EXP_0__TGT__SHIFT 0x4
++#define SQ_EXP_0__COMPR_MASK 0x400
++#define SQ_EXP_0__COMPR__SHIFT 0xa
++#define SQ_EXP_0__DONE_MASK 0x800
++#define SQ_EXP_0__DONE__SHIFT 0xb
++#define SQ_EXP_0__VM_MASK 0x1000
++#define SQ_EXP_0__VM__SHIFT 0xc
++#define SQ_EXP_0__ENCODING_MASK 0xfc000000
++#define SQ_EXP_0__ENCODING__SHIFT 0x1a
++#define SQ_MUBUF_0__OFFSET_MASK 0xfff
++#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
++#define SQ_MUBUF_0__OFFEN_MASK 0x1000
++#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
++#define SQ_MUBUF_0__IDXEN_MASK 0x2000
++#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
++#define SQ_MUBUF_0__GLC_MASK 0x4000
++#define SQ_MUBUF_0__GLC__SHIFT 0xe
++#define SQ_MUBUF_0__LDS_MASK 0x10000
++#define SQ_MUBUF_0__LDS__SHIFT 0x10
++#define SQ_MUBUF_0__SLC_MASK 0x20000
++#define SQ_MUBUF_0__SLC__SHIFT 0x11
++#define SQ_MUBUF_0__OP_MASK 0x1fc0000
++#define SQ_MUBUF_0__OP__SHIFT 0x12
++#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
++#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP_SDWA__SRC0_MASK 0xff
++#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
++#define SQ_VOP_SDWA__DST_SEL_MASK 0x700
++#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
++#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800
++#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
++#define SQ_VOP_SDWA__CLAMP_MASK 0x2000
++#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
++#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000
++#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
++#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000
++#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
++#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000
++#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
++#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000
++#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
++#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000
++#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
++#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000
++#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
++#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000
++#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
++#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000
++#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
++#define SQ_VOP3_0__VDST_MASK 0xff
++#define SQ_VOP3_0__VDST__SHIFT 0x0
++#define SQ_VOP3_0__ABS_MASK 0x700
++#define SQ_VOP3_0__ABS__SHIFT 0x8
++#define SQ_VOP3_0__CLAMP_MASK 0x8000
++#define SQ_VOP3_0__CLAMP__SHIFT 0xf
++#define SQ_VOP3_0__OP_MASK 0x3ff0000
++#define SQ_VOP3_0__OP__SHIFT 0x10
++#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
++#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP2__SRC0_MASK 0x1ff
++#define SQ_VOP2__SRC0__SHIFT 0x0
++#define SQ_VOP2__VSRC1_MASK 0x1fe00
++#define SQ_VOP2__VSRC1__SHIFT 0x9
++#define SQ_VOP2__VDST_MASK 0x1fe0000
++#define SQ_VOP2__VDST__SHIFT 0x11
++#define SQ_VOP2__OP_MASK 0x7e000000
++#define SQ_VOP2__OP__SHIFT 0x19
++#define SQ_VOP2__ENCODING_MASK 0x80000000
++#define SQ_VOP2__ENCODING__SHIFT 0x1f
++#define SQ_MTBUF_0__OFFSET_MASK 0xfff
++#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
++#define SQ_MTBUF_0__OFFEN_MASK 0x1000
++#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
++#define SQ_MTBUF_0__IDXEN_MASK 0x2000
++#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
++#define SQ_MTBUF_0__GLC_MASK 0x4000
++#define SQ_MTBUF_0__GLC__SHIFT 0xe
++#define SQ_MTBUF_0__OP_MASK 0x78000
++#define SQ_MTBUF_0__OP__SHIFT 0xf
++#define SQ_MTBUF_0__DFMT_MASK 0x780000
++#define SQ_MTBUF_0__DFMT__SHIFT 0x13
++#define SQ_MTBUF_0__NFMT_MASK 0x3800000
++#define SQ_MTBUF_0__NFMT__SHIFT 0x17
++#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
++#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
++#define SQ_SOPP__SIMM16_MASK 0xffff
++#define SQ_SOPP__SIMM16__SHIFT 0x0
++#define SQ_SOPP__OP_MASK 0x7f0000
++#define SQ_SOPP__OP__SHIFT 0x10
++#define SQ_SOPP__ENCODING_MASK 0xff800000
++#define SQ_SOPP__ENCODING__SHIFT 0x17
++#define SQ_FLAT_0__GLC_MASK 0x10000
++#define SQ_FLAT_0__GLC__SHIFT 0x10
++#define SQ_FLAT_0__SLC_MASK 0x20000
++#define SQ_FLAT_0__SLC__SHIFT 0x11
++#define SQ_FLAT_0__OP_MASK 0x1fc0000
++#define SQ_FLAT_0__OP__SHIFT 0x12
++#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
++#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
++#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
++#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
++#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
++#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000
++#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
++#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000
++#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
++#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
++#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
++#define SQ_MIMG_1__VADDR_MASK 0xff
++#define SQ_MIMG_1__VADDR__SHIFT 0x0
++#define SQ_MIMG_1__VDATA_MASK 0xff00
++#define SQ_MIMG_1__VDATA__SHIFT 0x8
++#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
++#define SQ_MIMG_1__SRSRC__SHIFT 0x10
++#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
++#define SQ_MIMG_1__SSAMP__SHIFT 0x15
++#define SQ_MIMG_1__D16_MASK 0x80000000
++#define SQ_MIMG_1__D16__SHIFT 0x1f
++#define SQ_SOP1__SSRC0_MASK 0xff
++#define SQ_SOP1__SSRC0__SHIFT 0x0
++#define SQ_SOP1__OP_MASK 0xff00
++#define SQ_SOP1__OP__SHIFT 0x8
++#define SQ_SOP1__SDST_MASK 0x7f0000
++#define SQ_SOP1__SDST__SHIFT 0x10
++#define SQ_SOP1__ENCODING_MASK 0xff800000
++#define SQ_SOP1__ENCODING__SHIFT 0x17
++#define SQ_SOPC__SSRC0_MASK 0xff
++#define SQ_SOPC__SSRC0__SHIFT 0x0
++#define SQ_SOPC__SSRC1_MASK 0xff00
++#define SQ_SOPC__SSRC1__SHIFT 0x8
++#define SQ_SOPC__OP_MASK 0x7f0000
++#define SQ_SOPC__OP__SHIFT 0x10
++#define SQ_SOPC__ENCODING_MASK 0xff800000
++#define SQ_SOPC__ENCODING__SHIFT 0x17
++#define SQ_FLAT_1__ADDR_MASK 0xff
++#define SQ_FLAT_1__ADDR__SHIFT 0x0
++#define SQ_FLAT_1__DATA_MASK 0xff00
++#define SQ_FLAT_1__DATA__SHIFT 0x8
++#define SQ_FLAT_1__TFE_MASK 0x800000
++#define SQ_FLAT_1__TFE__SHIFT 0x17
++#define SQ_FLAT_1__VDST_MASK 0xff000000
++#define SQ_FLAT_1__VDST__SHIFT 0x18
++#define SQ_DS_1__ADDR_MASK 0xff
++#define SQ_DS_1__ADDR__SHIFT 0x0
++#define SQ_DS_1__DATA0_MASK 0xff00
++#define SQ_DS_1__DATA0__SHIFT 0x8
++#define SQ_DS_1__DATA1_MASK 0xff0000
++#define SQ_DS_1__DATA1__SHIFT 0x10
++#define SQ_DS_1__VDST_MASK 0xff000000
++#define SQ_DS_1__VDST__SHIFT 0x18
++#define SQ_VOP3_1__SRC0_MASK 0x1ff
++#define SQ_VOP3_1__SRC0__SHIFT 0x0
++#define SQ_VOP3_1__SRC1_MASK 0x3fe00
++#define SQ_VOP3_1__SRC1__SHIFT 0x9
++#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
++#define SQ_VOP3_1__SRC2__SHIFT 0x12
++#define SQ_VOP3_1__OMOD_MASK 0x18000000
++#define SQ_VOP3_1__OMOD__SHIFT 0x1b
++#define SQ_VOP3_1__NEG_MASK 0xe0000000
++#define SQ_VOP3_1__NEG__SHIFT 0x1d
++#define SQ_SMEM_0__SBASE_MASK 0x3f
++#define SQ_SMEM_0__SBASE__SHIFT 0x0
++#define SQ_SMEM_0__SDATA_MASK 0x1fc0
++#define SQ_SMEM_0__SDATA__SHIFT 0x6
++#define SQ_SMEM_0__GLC_MASK 0x10000
++#define SQ_SMEM_0__GLC__SHIFT 0x10
++#define SQ_SMEM_0__IMM_MASK 0x20000
++#define SQ_SMEM_0__IMM__SHIFT 0x11
++#define SQ_SMEM_0__OP_MASK 0x3fc0000
++#define SQ_SMEM_0__OP__SHIFT 0x12
++#define SQ_SMEM_0__ENCODING_MASK 0xfc000000
++#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
++#define SQ_MIMG_0__DMASK_MASK 0xf00
++#define SQ_MIMG_0__DMASK__SHIFT 0x8
++#define SQ_MIMG_0__UNORM_MASK 0x1000
++#define SQ_MIMG_0__UNORM__SHIFT 0xc
++#define SQ_MIMG_0__GLC_MASK 0x2000
++#define SQ_MIMG_0__GLC__SHIFT 0xd
++#define SQ_MIMG_0__DA_MASK 0x4000
++#define SQ_MIMG_0__DA__SHIFT 0xe
++#define SQ_MIMG_0__R128_MASK 0x8000
++#define SQ_MIMG_0__R128__SHIFT 0xf
++#define SQ_MIMG_0__TFE_MASK 0x10000
++#define SQ_MIMG_0__TFE__SHIFT 0x10
++#define SQ_MIMG_0__LWE_MASK 0x20000
++#define SQ_MIMG_0__LWE__SHIFT 0x11
++#define SQ_MIMG_0__OP_MASK 0x1fc0000
++#define SQ_MIMG_0__OP__SHIFT 0x12
++#define SQ_MIMG_0__SLC_MASK 0x2000000
++#define SQ_MIMG_0__SLC__SHIFT 0x19
++#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
++#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
++#define SQ_SOPK__SIMM16_MASK 0xffff
++#define SQ_SOPK__SIMM16__SHIFT 0x0
++#define SQ_SOPK__SDST_MASK 0x7f0000
++#define SQ_SOPK__SDST__SHIFT 0x10
++#define SQ_SOPK__OP_MASK 0xf800000
++#define SQ_SOPK__OP__SHIFT 0x17
++#define SQ_SOPK__ENCODING_MASK 0xf0000000
++#define SQ_SOPK__ENCODING__SHIFT 0x1c
++#define SQ_DS_0__OFFSET0_MASK 0xff
++#define SQ_DS_0__OFFSET0__SHIFT 0x0
++#define SQ_DS_0__OFFSET1_MASK 0xff00
++#define SQ_DS_0__OFFSET1__SHIFT 0x8
++#define SQ_DS_0__GDS_MASK 0x10000
++#define SQ_DS_0__GDS__SHIFT 0x10
++#define SQ_DS_0__OP_MASK 0x1fe0000
++#define SQ_DS_0__OP__SHIFT 0x11
++#define SQ_DS_0__ENCODING_MASK 0xfc000000
++#define SQ_DS_0__ENCODING__SHIFT 0x1a
++#define SQ_VOP_DPP__SRC0_MASK 0xff
++#define SQ_VOP_DPP__SRC0__SHIFT 0x0
++#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00
++#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
++#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000
++#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
++#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000
++#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
++#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000
++#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
++#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000
++#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
++#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000
++#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
++#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000
++#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
++#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000
++#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
++#define SQ_VOPC__SRC0_MASK 0x1ff
++#define SQ_VOPC__SRC0__SHIFT 0x0
++#define SQ_VOPC__VSRC1_MASK 0x1fe00
++#define SQ_VOPC__VSRC1__SHIFT 0x9
++#define SQ_VOPC__OP_MASK 0x1fe0000
++#define SQ_VOPC__OP__SHIFT 0x11
++#define SQ_VOPC__ENCODING_MASK 0xfe000000
++#define SQ_VOPC__ENCODING__SHIFT 0x19
++#define SQ_VINTRP__VSRC_MASK 0xff
++#define SQ_VINTRP__VSRC__SHIFT 0x0
++#define SQ_VINTRP__ATTRCHAN_MASK 0x300
++#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
++#define SQ_VINTRP__ATTR_MASK 0xfc00
++#define SQ_VINTRP__ATTR__SHIFT 0xa
++#define SQ_VINTRP__OP_MASK 0x30000
++#define SQ_VINTRP__OP__SHIFT 0x10
++#define SQ_VINTRP__VDST_MASK 0x3fc0000
++#define SQ_VINTRP__VDST__SHIFT 0x12
++#define SQ_VINTRP__ENCODING_MASK 0xfc000000
++#define SQ_VINTRP__ENCODING__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
++#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
++#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
++#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
++#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
++#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
++#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
++#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
++#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
++#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
++#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
++#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
++#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
++#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
++#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
++#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
++#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
++#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
++#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
++#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
++#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
++#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
++#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
++#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
++#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
++#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
++#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
++#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
++#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
++#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
++#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
++#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
++#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
++#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
++#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
++#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
++#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
++#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
++#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
++#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
++#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
++#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
++#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
++#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
++#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
++#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
++#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
++#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
++#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
++#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
++#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
++#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
++#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
++#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
++#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
++#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
++#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
++#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
++#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
++#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
++#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
++#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
++#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
++#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
++#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
++#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
++#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
++#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
++#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
++#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
++#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
++#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
++#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
++#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
++#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
++#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
++#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
++#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
++#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
++#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
++#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
++#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
++#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
++#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
++#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
++#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_CTRL__CACHE_SIZE_MASK 0x3
++#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
++#define TCC_CTRL__RATE_MASK 0xc
++#define TCC_CTRL__RATE__SHIFT 0x2
++#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
++#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
++#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00
++#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
++#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
++#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
++#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
++#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
++#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
++#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
++#define TCC_CTRL__MDC_SIZE_MASK 0x3000000
++#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
++#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000
++#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
++#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000
++#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
++#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff
++#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0
++#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000
++#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10
++#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
++#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
++#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
++#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
++#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2
++#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
++#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
++#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
++#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
++#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
++#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
++#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
++#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
++#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
++#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
++#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
++#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
++#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
++#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
++#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
++#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
++#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
++#define TD_CNTL__PAD_STALL_EN_MASK 0x100
++#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
++#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
++#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
++#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
++#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
++#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
++#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
++#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
++#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
++#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
++#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
++#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
++#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
++#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
++#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
++#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000
++#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
++#define TD_STATUS__BUSY_MASK 0x80000000
++#define TD_STATUS__BUSY__SHIFT 0x1f
++#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
++#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
++#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
++#define TD_DEBUG_DATA__DATA__SHIFT 0x0
++#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1
++#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0
++#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2
++#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1
++#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4
++#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
++#define TD_SCRATCH__SCRATCH__SHIFT 0x0
++#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
++#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
++#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
++#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
++#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
++#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
++#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
++#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
++#define TA_CNTL_AUX__RESERVED_MASK 0xe
++#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
++#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
++#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
++#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000
++#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
++#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000
++#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
++#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000
++#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
++#define TA_RESERVED_010C__Unused_MASK 0xffffffff
++#define TA_RESERVED_010C__Unused__SHIFT 0x0
++#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
++#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
++#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
++#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
++#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
++#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
++#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
++#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
++#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
++#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
++#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
++#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
++#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
++#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
++#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
++#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
++#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
++#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
++#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
++#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
++#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
++#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
++#define TA_STATUS__IN_BUSY_MASK 0x1000000
++#define TA_STATUS__IN_BUSY__SHIFT 0x18
++#define TA_STATUS__FG_BUSY_MASK 0x2000000
++#define TA_STATUS__FG_BUSY__SHIFT 0x19
++#define TA_STATUS__LA_BUSY_MASK 0x4000000
++#define TA_STATUS__LA_BUSY__SHIFT 0x1a
++#define TA_STATUS__FL_BUSY_MASK 0x8000000
++#define TA_STATUS__FL_BUSY__SHIFT 0x1b
++#define TA_STATUS__TA_BUSY_MASK 0x10000000
++#define TA_STATUS__TA_BUSY__SHIFT 0x1c
++#define TA_STATUS__FA_BUSY_MASK 0x20000000
++#define TA_STATUS__FA_BUSY__SHIFT 0x1d
++#define TA_STATUS__AL_BUSY_MASK 0x40000000
++#define TA_STATUS__AL_BUSY__SHIFT 0x1e
++#define TA_STATUS__BUSY_MASK 0x80000000
++#define TA_STATUS__BUSY__SHIFT 0x1f
++#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
++#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
++#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
++#define TA_DEBUG_DATA__DATA__SHIFT 0x0
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
++#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
++#define TA_SCRATCH__SCRATCH__SHIFT 0x0
++#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
++#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
++#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
++#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
++#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
++#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
++#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
++#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
++#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
++#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
++#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
++#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
++#define TCP_INVALIDATE__START_MASK 0x1
++#define TCP_INVALIDATE__START__SHIFT 0x0
++#define TCP_STATUS__TCP_BUSY_MASK 0x1
++#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
++#define TCP_STATUS__INPUT_BUSY_MASK 0x2
++#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
++#define TCP_STATUS__ADRS_BUSY_MASK 0x4
++#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
++#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8
++#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
++#define TCP_STATUS__CNTRL_BUSY_MASK 0x10
++#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
++#define TCP_STATUS__LFIFO_BUSY_MASK 0x20
++#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
++#define TCP_STATUS__READ_BUSY_MASK 0x40
++#define TCP_STATUS__READ_BUSY__SHIFT 0x6
++#define TCP_STATUS__FORMAT_BUSY_MASK 0x80
++#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
++#define TCP_CNTL__FORCE_HIT_MASK 0x1
++#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
++#define TCP_CNTL__FORCE_MISS_MASK 0x2
++#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
++#define TCP_CNTL__L1_SIZE_MASK 0xc
++#define TCP_CNTL__L1_SIZE__SHIFT 0x2
++#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
++#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
++#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
++#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
++#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
++#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
++#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
++#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
++#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
++#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
++#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
++#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
++#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
++#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
++#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
++#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
++#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
++#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
++#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
++#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
++#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
++#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
++#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
++#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
++#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
++#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
++#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
++#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
++#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
++#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
++#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
++#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
++#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
++#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
++#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
++#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
++#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
++#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
++#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
++#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
++#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
++#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
++#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
++#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
++#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
++#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
++#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
++#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
++#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
++#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
++#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
++#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
++#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
++#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
++#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
++#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
++#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
++#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
++#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
++#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff
++#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
++#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00
++#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
++#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000
++#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
++#define TCP_EDC_CNT__UNUSED_MASK 0xff000000
++#define TCP_EDC_CNT__UNUSED__SHIFT 0x18
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
++#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
++#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
++#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
++#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
++#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
++#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
++#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
++#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
++#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
++#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
++#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
++#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
++#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
++#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
++#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
++#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
++#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
++#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
++#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
++#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
++#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
++#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
++#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
++#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
++#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
++#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
++#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
++#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
++#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
++#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
++#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
++#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
++#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
++#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
++#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
++#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
++#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
++#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
++#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
++#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
++#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
++#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
++#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
++#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
++#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
++#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
++#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
++#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
++#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
++#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
++#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
++#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
++#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
++#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
++#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
++#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
++#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
++#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
++#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
++#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
++#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
++#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
++#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
++#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
++#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
++#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
++#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
++#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
++#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
++#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
++#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
++#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
++#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
++#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
++#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
++#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
++#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
++#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
++#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
++#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
++#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
++#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
++#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
++#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
++#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
++#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
++#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
++#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
++#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
++#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
++#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
++#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
++#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
++#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
++#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
++#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
++#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
++#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
++#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
++#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
++#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
++#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
++#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
++#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
++#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
++#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
++#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
++#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
++#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
++#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
++#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
++#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
++#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
++#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
++#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
++#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
++#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
++#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
++#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
++#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
++#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000
++#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
++#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000
++#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
++#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000
++#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
++#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
++#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
++#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
++#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
++#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff
++#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1
++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2
++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
++#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4
++#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
++#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
++#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
++#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
++#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
++#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18
++#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
++#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20
++#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
++#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff
++#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
++#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
++#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
++#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
++#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
++#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define TCI_STATUS__TCI_BUSY_MASK 0x1
++#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
++#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
++#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
++#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
++#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
++#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
++#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
++#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
++#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
++#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
++#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
++#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
++#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
++#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
++#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
++#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
++#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
++#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
++#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
++#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
++#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
++#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
++#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
++#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
++#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
++#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
++#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
++#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
++#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
++#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
++#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
++#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
++#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
++#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80
++#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
++#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100
++#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
++#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200
++#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
++#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400
++#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
++#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800
++#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
++#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000
++#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
++#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000
++#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
++#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000
++#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
++#define GDS_ENHANCE2__MISC_MASK 0xffff
++#define GDS_ENHANCE2__MISC__SHIFT 0x0
++#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
++#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
++#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
++#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
++#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
++#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
++#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
++#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
++#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
++#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
++#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
++#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
++#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
++#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
++#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
++#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
++#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
++#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
++#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
++#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
++#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
++#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
++#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
++#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
++#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
++#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
++#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
++#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
++#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
++#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
++#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
++#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
++#define GDS_EDC_CNT__DED_MASK 0xff
++#define GDS_EDC_CNT__DED__SHIFT 0x0
++#define GDS_EDC_CNT__SED_MASK 0xff00
++#define GDS_EDC_CNT__SED__SHIFT 0x8
++#define GDS_EDC_CNT__SEC_MASK 0xff0000
++#define GDS_EDC_CNT__SEC__SHIFT 0x10
++#define GDS_EDC_GRBM_CNT__DED_MASK 0xff
++#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
++#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000
++#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10
++#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
++#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
++#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
++#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
++#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4
++#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
++#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8
++#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3
++#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10
++#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
++#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20
++#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
++#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40
++#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
++#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80
++#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
++#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100
++#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
++#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200
++#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
++#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400
++#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
++#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800
++#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
++#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000
++#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
++#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
++#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
++#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
++#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
++#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
++#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1
++#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4
++#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10
++#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4
++#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20
++#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5
++#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0
++#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6
++#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
++#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
++#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
++#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
++#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
++#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
++#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
++#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
++#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
++#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
++#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
++#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
++#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
++#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
++#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
++#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
++#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
++#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
++#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
++#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
++#define GDS_ATOM_CNTL__AINC_MASK 0x3f
++#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
++#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
++#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
++#define GDS_ATOM_CNTL__DMODE_MASK 0x300
++#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
++#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00
++#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
++#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
++#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
++#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
++#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
++#define GDS_ATOM_BASE__BASE_MASK 0xffff
++#define GDS_ATOM_BASE__BASE__SHIFT 0x0
++#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
++#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
++#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
++#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
++#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
++#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
++#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
++#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
++#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
++#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
++#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
++#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
++#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
++#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
++#define GDS_ATOM_DST__DST_MASK 0xffffffff
++#define GDS_ATOM_DST__DST__SHIFT 0x0
++#define GDS_ATOM_OP__OP_MASK 0xff
++#define GDS_ATOM_OP__OP__SHIFT 0x0
++#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
++#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
++#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
++#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
++#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
++#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
++#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ0__DATA__SHIFT 0x0
++#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
++#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ1__DATA__SHIFT 0x0
++#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
++#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
++#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
++#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
++#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
++#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
++#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
++#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
++#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
++#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
++#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
++#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
++#define GDS_GWS_RESOURCE__DED_MASK 0x4000
++#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
++#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
++#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
++#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
++#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
++#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
++#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
++#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
++#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
++#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
++#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
++#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
++#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
++#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
++#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
++#define GDS_OA_CNTL__INDEX_MASK 0xf
++#define GDS_OA_CNTL__INDEX__SHIFT 0x0
++#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
++#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
++#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
++#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
++#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
++#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
++#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000
++#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
++#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000
++#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
++#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000
++#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
++#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
++#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
++#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
++#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
++#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
++#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
++#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
++#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
++#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
++#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
++#define GDS_DEBUG_REG0__spare1_MASK 0x3f
++#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
++#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
++#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
++#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
++#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
++#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
++#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
++#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
++#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
++#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
++#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
++#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
++#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
++#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
++#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
++#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
++#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
++#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
++#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
++#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
++#define GDS_DEBUG_REG0__spare__SHIFT 0x16
++#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
++#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
++#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
++#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
++#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
++#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
++#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
++#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
++#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
++#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
++#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
++#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
++#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
++#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
++#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
++#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
++#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
++#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
++#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
++#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
++#define GDS_DEBUG_REG1__spare_MASK 0xff000000
++#define GDS_DEBUG_REG1__spare__SHIFT 0x18
++#define GDS_DEBUG_REG2__ds_full_MASK 0x1
++#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
++#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
++#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
++#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
++#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
++#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
++#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
++#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
++#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
++#define GDS_DEBUG_REG2__req_MASK 0x7fff00
++#define GDS_DEBUG_REG2__req__SHIFT 0x8
++#define GDS_DEBUG_REG2__spare_MASK 0xff800000
++#define GDS_DEBUG_REG2__spare__SHIFT 0x17
++#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
++#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
++#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
++#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
++#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
++#define GDS_DEBUG_REG3__spare__SHIFT 0xf
++#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
++#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
++#define GDS_DEBUG_REG4__gws_req_MASK 0x2
++#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
++#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
++#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
++#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
++#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
++#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
++#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
++#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
++#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
++#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
++#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
++#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
++#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
++#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
++#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
++#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
++#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
++#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
++#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
++#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
++#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
++#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
++#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
++#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
++#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
++#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
++#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
++#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
++#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
++#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
++#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
++#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
++#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
++#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
++#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
++#define GDS_DEBUG_REG4__spare_MASK 0xff000000
++#define GDS_DEBUG_REG4__spare__SHIFT 0x18
++#define GDS_DEBUG_REG5__write_dis_MASK 0x1
++#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
++#define GDS_DEBUG_REG5__dec_error_MASK 0x2
++#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
++#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
++#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
++#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
++#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
++#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
++#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
++#define GDS_DEBUG_REG5__spare_MASK 0xe0
++#define GDS_DEBUG_REG5__spare__SHIFT 0x5
++#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
++#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
++#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
++#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
++#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
++#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
++#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
++#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
++#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
++#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
++#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
++#define GDS_DEBUG_REG6__spare__SHIFT 0x15
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
++#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
++#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
++#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
++#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
++#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
++#define GDS_VMID0_BASE__BASE_MASK 0xffff
++#define GDS_VMID0_BASE__BASE__SHIFT 0x0
++#define GDS_VMID1_BASE__BASE_MASK 0xffff
++#define GDS_VMID1_BASE__BASE__SHIFT 0x0
++#define GDS_VMID2_BASE__BASE_MASK 0xffff
++#define GDS_VMID2_BASE__BASE__SHIFT 0x0
++#define GDS_VMID3_BASE__BASE_MASK 0xffff
++#define GDS_VMID3_BASE__BASE__SHIFT 0x0
++#define GDS_VMID4_BASE__BASE_MASK 0xffff
++#define GDS_VMID4_BASE__BASE__SHIFT 0x0
++#define GDS_VMID5_BASE__BASE_MASK 0xffff
++#define GDS_VMID5_BASE__BASE__SHIFT 0x0
++#define GDS_VMID6_BASE__BASE_MASK 0xffff
++#define GDS_VMID6_BASE__BASE__SHIFT 0x0
++#define GDS_VMID7_BASE__BASE_MASK 0xffff
++#define GDS_VMID7_BASE__BASE__SHIFT 0x0
++#define GDS_VMID8_BASE__BASE_MASK 0xffff
++#define GDS_VMID8_BASE__BASE__SHIFT 0x0
++#define GDS_VMID9_BASE__BASE_MASK 0xffff
++#define GDS_VMID9_BASE__BASE__SHIFT 0x0
++#define GDS_VMID10_BASE__BASE_MASK 0xffff
++#define GDS_VMID10_BASE__BASE__SHIFT 0x0
++#define GDS_VMID11_BASE__BASE_MASK 0xffff
++#define GDS_VMID11_BASE__BASE__SHIFT 0x0
++#define GDS_VMID12_BASE__BASE_MASK 0xffff
++#define GDS_VMID12_BASE__BASE__SHIFT 0x0
++#define GDS_VMID13_BASE__BASE_MASK 0xffff
++#define GDS_VMID13_BASE__BASE__SHIFT 0x0
++#define GDS_VMID14_BASE__BASE_MASK 0xffff
++#define GDS_VMID14_BASE__BASE__SHIFT 0x0
++#define GDS_VMID15_BASE__BASE_MASK 0xffff
++#define GDS_VMID15_BASE__BASE__SHIFT 0x0
++#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
++#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
++#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
++#define GDS_GWS_VMID0__BASE_MASK 0x3f
++#define GDS_GWS_VMID0__BASE__SHIFT 0x0
++#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID1__BASE_MASK 0x3f
++#define GDS_GWS_VMID1__BASE__SHIFT 0x0
++#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID2__BASE_MASK 0x3f
++#define GDS_GWS_VMID2__BASE__SHIFT 0x0
++#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID3__BASE_MASK 0x3f
++#define GDS_GWS_VMID3__BASE__SHIFT 0x0
++#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID4__BASE_MASK 0x3f
++#define GDS_GWS_VMID4__BASE__SHIFT 0x0
++#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID5__BASE_MASK 0x3f
++#define GDS_GWS_VMID5__BASE__SHIFT 0x0
++#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID6__BASE_MASK 0x3f
++#define GDS_GWS_VMID6__BASE__SHIFT 0x0
++#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID7__BASE_MASK 0x3f
++#define GDS_GWS_VMID7__BASE__SHIFT 0x0
++#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID8__BASE_MASK 0x3f
++#define GDS_GWS_VMID8__BASE__SHIFT 0x0
++#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID9__BASE_MASK 0x3f
++#define GDS_GWS_VMID9__BASE__SHIFT 0x0
++#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID10__BASE_MASK 0x3f
++#define GDS_GWS_VMID10__BASE__SHIFT 0x0
++#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID11__BASE_MASK 0x3f
++#define GDS_GWS_VMID11__BASE__SHIFT 0x0
++#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID12__BASE_MASK 0x3f
++#define GDS_GWS_VMID12__BASE__SHIFT 0x0
++#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID13__BASE_MASK 0x3f
++#define GDS_GWS_VMID13__BASE__SHIFT 0x0
++#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID14__BASE_MASK 0x3f
++#define GDS_GWS_VMID14__BASE__SHIFT 0x0
++#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
++#define GDS_GWS_VMID15__BASE_MASK 0x3f
++#define GDS_GWS_VMID15__BASE__SHIFT 0x0
++#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
++#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
++#define GDS_OA_VMID0__MASK_MASK 0xffff
++#define GDS_OA_VMID0__MASK__SHIFT 0x0
++#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID1__MASK_MASK 0xffff
++#define GDS_OA_VMID1__MASK__SHIFT 0x0
++#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID2__MASK_MASK 0xffff
++#define GDS_OA_VMID2__MASK__SHIFT 0x0
++#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID3__MASK_MASK 0xffff
++#define GDS_OA_VMID3__MASK__SHIFT 0x0
++#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID4__MASK_MASK 0xffff
++#define GDS_OA_VMID4__MASK__SHIFT 0x0
++#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID5__MASK_MASK 0xffff
++#define GDS_OA_VMID5__MASK__SHIFT 0x0
++#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID6__MASK_MASK 0xffff
++#define GDS_OA_VMID6__MASK__SHIFT 0x0
++#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID7__MASK_MASK 0xffff
++#define GDS_OA_VMID7__MASK__SHIFT 0x0
++#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID8__MASK_MASK 0xffff
++#define GDS_OA_VMID8__MASK__SHIFT 0x0
++#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID9__MASK_MASK 0xffff
++#define GDS_OA_VMID9__MASK__SHIFT 0x0
++#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID10__MASK_MASK 0xffff
++#define GDS_OA_VMID10__MASK__SHIFT 0x0
++#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID11__MASK_MASK 0xffff
++#define GDS_OA_VMID11__MASK__SHIFT 0x0
++#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID12__MASK_MASK 0xffff
++#define GDS_OA_VMID12__MASK__SHIFT 0x0
++#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID13__MASK_MASK 0xffff
++#define GDS_OA_VMID13__MASK__SHIFT 0x0
++#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID14__MASK_MASK 0xffff
++#define GDS_OA_VMID14__MASK__SHIFT 0x0
++#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
++#define GDS_OA_VMID15__MASK_MASK 0xffff
++#define GDS_OA_VMID15__MASK__SHIFT 0x0
++#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
++#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
++#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
++#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
++#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
++#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
++#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
++#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
++#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
++#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
++#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
++#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
++#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
++#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
++#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
++#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
++#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
++#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
++#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
++#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
++#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
++#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
++#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
++#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
++#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
++#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
++#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
++#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
++#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
++#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
++#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
++#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
++#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
++#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
++#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
++#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
++#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
++#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
++#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
++#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
++#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
++#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
++#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
++#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
++#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
++#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
++#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
++#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
++#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
++#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
++#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
++#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
++#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
++#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
++#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
++#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
++#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
++#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
++#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
++#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
++#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
++#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
++#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
++#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
++#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
++#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
++#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
++#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
++#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
++#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
++#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
++#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
++#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
++#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
++#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
++#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
++#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
++#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
++#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
++#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
++#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
++#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
++#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
++#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
++#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
++#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
++#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
++#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
++#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
++#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
++#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
++#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
++#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
++#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
++#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
++#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
++#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
++#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
++#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
++#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
++#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
++#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
++#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
++#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
++#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
++#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
++#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
++#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
++#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
++#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
++#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
++#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
++#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
++#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
++#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
++#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
++#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
++#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
++#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
++#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
++#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
++#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
++#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
++#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
++#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
++#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
++#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
++#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
++#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
++#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
++#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
++#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
++#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
++#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
++#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
++#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
++#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
++#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
++#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
++#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
++#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
++#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
++#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
++#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
++#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
++#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
++#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
++#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
++#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
++#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
++#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
++#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
++#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
++#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
++#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
++#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
++#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
++#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
++#define GDS_OA_RESET__RESET_MASK 0x1
++#define GDS_OA_RESET__RESET__SHIFT 0x0
++#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
++#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
++#define GDS_ENHANCE__MISC_MASK 0xffff
++#define GDS_ENHANCE__MISC__SHIFT 0x0
++#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
++#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
++#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
++#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
++#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
++#define GDS_ENHANCE__UNUSED__SHIFT 0x12
++#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
++#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
++#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
++#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
++#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
++#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
++#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000
++#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
++#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000
++#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
++#define GDS_CS_CTXSW_STATUS__R_MASK 0x1
++#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
++#define GDS_CS_CTXSW_STATUS__W_MASK 0x2
++#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
++#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
++#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
++#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1
++#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
++#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2
++#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
++#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
++#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
++#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff
++#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
++#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000
++#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
++#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff
++#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
++#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000
++#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
++#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff
++#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
++#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000
++#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
++#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
++#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff
++#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
++#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000
++#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
++#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
++#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
++#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
++#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
++#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
++#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
++#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
++#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
++#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
++#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
++#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
++#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
++#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
++#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
++#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
++#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
++#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
++#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
++#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
++#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
++#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
++#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
++#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
++#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
++#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
++#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
++#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
++#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
++#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
++#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
++#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
++#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
++#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40
++#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
++#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
++#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
++#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
++#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
++#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800
++#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
++#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
++#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
++#define IA_ENHANCE__MISC_MASK 0xffffffff
++#define IA_ENHANCE__MISC__SHIFT 0x0
++#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
++#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
++#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
++#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
++#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
++#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
++#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
++#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
++#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
++#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
++#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
++#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
++#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
++#define VGT_IMMED_DATA__DATA__SHIFT 0x0
++#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
++#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
++#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
++#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
++#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
++#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
++#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
++#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
++#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
++#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
++#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
++#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
++#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
++#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
++#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
++#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
++#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
++#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
++#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
++#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
++#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
++#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
++#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
++#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
++#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
++#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
++#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
++#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
++#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
++#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
++#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
++#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
++#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
++#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
++#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
++#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
++#define VGT_ENHANCE__MISC_MASK 0xffffffff
++#define VGT_ENHANCE__MISC__SHIFT 0x0
++#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
++#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
++#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
++#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
++#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
++#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
++#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
++#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
++#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
++#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
++#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
++#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
++#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
++#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
++#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
++#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
++#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
++#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
++#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
++#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
++#define VGT_GROUP_DECR__DECR_MASK 0xf
++#define VGT_GROUP_DECR__DECR__SHIFT 0x0
++#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
++#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
++#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
++#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
++#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
++#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
++#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
++#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
++#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
++#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
++#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
++#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
++#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
++#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
++#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
++#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
++#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
++#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
++#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
++#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
++#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
++#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
++#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
++#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
++#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
++#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
++#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
++#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
++#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
++#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
++#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
++#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
++#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
++#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
++#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
++#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
++#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
++#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
++#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
++#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
++#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
++#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
++#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
++#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
++#define VGT_GS_MODE__MODE_MASK 0x7
++#define VGT_GS_MODE__MODE__SHIFT 0x0
++#define VGT_GS_MODE__RESERVED_0_MASK 0x8
++#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
++#define VGT_GS_MODE__CUT_MODE_MASK 0x30
++#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
++#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
++#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
++#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
++#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
++#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
++#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
++#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
++#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
++#define VGT_GS_MODE__RESERVED_3_MASK 0x4000
++#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
++#define VGT_GS_MODE__RESERVED_4_MASK 0x8000
++#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
++#define VGT_GS_MODE__RESERVED_5_MASK 0x10000
++#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
++#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
++#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
++#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
++#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
++#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
++#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
++#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
++#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
++#define VGT_GS_MODE__ONCHIP_MASK 0x600000
++#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
++#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
++#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
++#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
++#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
++#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
++#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
++#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
++#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
++#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10
++#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
++#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
++#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
++#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
++#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
++#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
++#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
++#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
++#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
++#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
++#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
++#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
++#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
++#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
++#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
++#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
++#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
++#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
++#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
++#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
++#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
++#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
++#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
++#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
++#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
++#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
++#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
++#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
++#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
++#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
++#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
++#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
++#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
++#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
++#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
++#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
++#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
++#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000
++#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
++#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
++#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
++#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
++#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
++#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
++#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
++#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
++#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
++#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
++#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
++#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
++#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
++#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
++#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
++#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
++#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
++#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
++#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
++#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
++#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
++#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
++#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
++#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
++#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
++#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
++#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
++#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
++#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
++#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
++#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
++#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
++#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
++#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
++#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
++#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
++#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
++#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
++#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
++#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
++#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
++#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
++#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
++#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
++#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
++#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
++#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
++#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
++#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
++#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
++#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
++#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
++#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
++#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200
++#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400
++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800
++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
++#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000
++#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
++#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
++#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
++#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
++#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
++#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
++#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
++#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
++#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
++#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
++#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
++#define VGT_TF_PARAM__TYPE_MASK 0x3
++#define VGT_TF_PARAM__TYPE__SHIFT 0x0
++#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
++#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
++#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
++#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
++#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
++#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
++#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
++#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
++#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
++#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
++#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
++#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
++#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000
++#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
++#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000
++#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
++#define VGT_TF_PARAM__MTYPE_MASK 0x180000
++#define VGT_TF_PARAM__MTYPE__SHIFT 0x13
++#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff
++#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
++#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00
++#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
++#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000
++#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
++#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000
++#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
++#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
++#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
++#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
++#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
++#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
++#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
++#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
++#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
++#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
++#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
++#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
++#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
++#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
++#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
++#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
++#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
++#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
++#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
++#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
++#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
++#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
++#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
++#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000
++#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c
++#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
++#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
++#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
++#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
++#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
++#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
++#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
++#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
++#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
++#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
++#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
++#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
++#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
++#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
++#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
++#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
++#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
++#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
++#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
++#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
++#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
++#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
++#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
++#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
++#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
++#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
++#define WD_ENHANCE__MISC_MASK 0xffffffff
++#define WD_ENHANCE__MISC__SHIFT 0x0
++#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
++#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
++#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
++#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
++#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
++#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
++#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
++#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
++#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
++#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
++#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
++#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
++#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
++#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
++#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
++#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
++#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
++#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
++#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
++#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
++#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
++#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
++#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
++#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
++#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
++#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
++#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
++#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
++#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
++#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
++#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
++#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
++#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
++#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
++#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
++#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
++#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
++#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
++#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
++#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
++#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
++#define IA_DEBUG_DATA__DATA__SHIFT 0x0
++#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
++#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
++#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
++#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
++#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
++#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
++#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
++#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
++#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
++#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
++#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
++#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
++#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
++#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
++#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
++#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
++#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
++#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
++#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
++#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
++#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
++#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
++#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
++#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
++#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
++#define WD_DEBUG_DATA__DATA__SHIFT 0x0
++#define WD_QOS__DRAW_STALL_MASK 0x1
++#define WD_QOS__DRAW_STALL__SHIFT 0x0
++#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
++#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
++#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
++#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
++#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
++#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
++#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
++#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
++#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
++#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
++#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
++#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
++#define WD_DEBUG_REG0__wd_busy_MASK 0x4
++#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
++#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
++#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
++#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
++#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
++#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
++#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
++#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
++#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
++#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
++#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
++#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
++#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
++#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
++#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
++#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
++#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
++#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
++#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
++#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
++#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
++#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
++#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
++#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
++#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
++#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
++#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
++#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
++#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
++#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
++#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
++#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
++#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
++#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
++#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
++#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
++#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
++#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
++#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
++#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
++#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
++#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
++#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
++#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
++#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
++#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
++#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
++#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
++#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
++#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
++#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
++#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
++#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
++#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
++#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
++#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
++#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
++#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
++#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
++#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
++#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
++#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
++#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
++#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
++#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
++#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
++#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
++#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
++#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
++#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
++#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
++#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
++#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
++#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
++#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
++#define WD_DEBUG_REG1__SPARE0_MASK 0x100
++#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
++#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
++#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
++#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
++#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
++#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
++#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
++#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
++#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
++#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
++#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
++#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
++#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
++#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
++#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
++#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
++#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
++#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
++#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
++#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
++#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
++#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
++#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
++#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
++#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
++#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
++#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
++#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
++#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
++#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
++#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
++#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
++#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
++#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
++#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
++#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
++#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
++#define WD_DEBUG_REG2__SPARE0_MASK 0x100
++#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
++#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
++#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
++#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
++#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
++#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
++#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
++#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
++#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
++#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
++#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
++#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
++#define WD_DEBUG_REG3__SPARE0_MASK 0x2
++#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
++#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
++#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
++#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
++#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
++#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
++#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
++#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
++#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
++#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
++#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
++#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
++#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
++#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
++#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
++#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
++#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
++#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
++#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
++#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
++#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
++#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
++#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
++#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
++#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
++#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
++#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
++#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
++#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
++#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
++#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
++#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
++#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
++#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
++#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
++#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
++#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
++#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
++#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
++#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
++#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
++#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
++#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
++#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
++#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
++#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
++#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
++#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
++#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
++#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
++#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
++#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
++#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
++#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
++#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
++#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
++#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
++#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
++#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
++#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
++#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
++#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
++#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
++#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
++#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
++#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
++#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
++#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
++#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
++#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
++#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
++#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
++#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
++#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
++#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
++#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
++#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
++#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
++#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
++#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
++#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
++#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
++#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
++#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
++#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
++#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
++#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
++#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
++#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
++#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
++#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
++#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
++#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
++#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
++#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
++#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
++#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
++#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
++#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
++#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
++#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
++#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
++#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
++#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
++#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
++#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
++#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
++#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
++#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
++#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
++#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
++#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
++#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
++#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
++#define WD_DEBUG_REG5__SPARE0_MASK 0x2
++#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
++#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
++#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
++#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
++#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
++#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
++#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
++#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
++#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
++#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
++#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
++#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
++#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
++#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
++#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
++#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
++#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
++#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
++#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
++#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
++#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
++#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
++#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
++#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
++#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
++#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
++#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
++#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
++#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
++#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
++#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
++#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
++#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
++#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
++#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
++#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
++#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
++#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
++#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
++#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
++#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
++#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
++#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
++#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
++#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
++#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
++#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
++#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
++#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff
++#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0
++#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1
++#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0
++#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2
++#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1
++#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4
++#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2
++#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8
++#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3
++#define WD_DEBUG_REG7__SPARE0_MASK 0xf0
++#define WD_DEBUG_REG7__SPARE0__SHIFT 0x4
++#define WD_DEBUG_REG7__SPARE1_MASK 0xf00
++#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8
++#define WD_DEBUG_REG7__SPARE2_MASK 0xf000
++#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc
++#define WD_DEBUG_REG7__SPARE3_MASK 0xf0000
++#define WD_DEBUG_REG7__SPARE3__SHIFT 0x10
++#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000
++#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
++#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000
++#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15
++#define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000
++#define WD_DEBUG_REG7__SPARE4__SHIFT 0x16
++#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000
++#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c
++#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000
++#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d
++#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000
++#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e
++#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000
++#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f
++#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1
++#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0
++#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2
++#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1
++#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4
++#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2
++#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8
++#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3
++#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10
++#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4
++#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20
++#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5
++#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40
++#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6
++#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80
++#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7
++#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100
++#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8
++#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200
++#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9
++#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400
++#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa
++#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800
++#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb
++#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000
++#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc
++#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000
++#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12
++#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000
++#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13
++#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000
++#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
++#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000
++#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b
++#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000
++#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c
++#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000
++#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d
++#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000
++#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e
++#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000
++#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f
++#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1
++#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0
++#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2
++#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1
++#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4
++#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2
++#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8
++#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3
++#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10
++#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4
++#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20
++#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5
++#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40
++#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6
++#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80
++#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7
++#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100
++#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8
++#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200
++#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9
++#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400
++#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa
++#define WD_DEBUG_REG9__SPARE0_MASK 0xf800
++#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb
++#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000
++#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10
++#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000
++#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13
++#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000
++#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
++#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000
++#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18
++#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000
++#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19
++#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000
++#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a
++#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000
++#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b
++#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000
++#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c
++#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000
++#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e
++#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000
++#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f
++#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1
++#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0
++#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2
++#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1
++#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4
++#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2
++#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8
++#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3
++#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10
++#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4
++#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20
++#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5
++#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40
++#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6
++#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80
++#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7
++#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100
++#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8
++#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200
++#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9
++#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400
++#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa
++#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800
++#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb
++#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000
++#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc
++#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000
++#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd
++#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000
++#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe
++#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000
++#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf
++#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000
++#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10
++#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000
++#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18
++#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000
++#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19
++#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000
++#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a
++#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000
++#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b
++#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000
++#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c
++#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000
++#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d
++#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000
++#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e
++#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000
++#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f
++#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
++#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
++#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
++#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
++#define IA_DEBUG_REG0__ia_busy_MASK 0x4
++#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
++#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
++#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
++#define IA_DEBUG_REG0__SPARE0_MASK 0x10
++#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
++#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
++#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
++#define IA_DEBUG_REG0__dma_busy_MASK 0x40
++#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
++#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
++#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
++#define IA_DEBUG_REG0__grp_busy_MASK 0x100
++#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
++#define IA_DEBUG_REG0__SPARE1_MASK 0x200
++#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
++#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
++#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
++#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
++#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
++#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
++#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
++#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
++#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
++#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
++#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
++#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
++#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
++#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
++#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
++#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
++#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
++#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
++#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
++#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
++#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
++#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
++#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
++#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
++#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
++#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
++#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
++#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
++#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
++#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
++#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
++#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
++#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
++#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
++#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
++#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
++#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
++#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
++#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
++#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
++#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
++#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
++#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
++#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
++#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
++#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
++#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
++#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
++#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
++#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
++#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
++#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
++#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
++#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
++#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
++#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
++#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
++#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
++#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
++#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
++#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
++#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
++#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
++#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
++#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
++#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
++#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
++#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
++#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
++#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
++#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
++#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
++#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
++#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
++#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
++#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
++#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
++#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
++#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
++#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
++#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
++#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
++#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
++#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
++#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
++#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
++#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
++#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
++#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
++#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
++#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
++#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
++#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
++#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
++#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
++#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
++#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
++#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
++#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
++#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
++#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
++#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
++#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
++#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
++#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
++#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
++#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
++#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
++#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
++#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
++#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
++#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
++#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
++#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
++#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
++#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
++#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
++#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
++#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
++#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
++#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
++#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
++#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
++#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
++#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
++#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
++#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
++#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
++#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
++#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
++#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
++#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
++#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
++#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
++#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
++#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
++#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
++#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
++#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
++#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
++#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
++#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
++#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
++#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
++#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
++#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
++#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
++#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
++#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
++#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
++#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
++#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
++#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
++#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
++#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
++#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
++#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
++#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
++#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
++#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
++#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
++#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
++#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
++#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
++#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
++#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
++#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
++#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
++#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
++#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
++#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
++#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
++#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
++#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
++#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
++#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
++#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
++#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
++#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
++#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
++#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
++#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
++#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
++#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
++#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
++#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
++#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
++#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
++#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
++#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
++#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
++#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
++#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
++#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
++#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
++#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
++#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
++#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
++#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
++#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
++#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
++#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
++#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
++#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
++#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
++#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
++#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
++#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
++#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
++#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
++#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
++#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
++#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
++#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
++#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
++#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
++#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
++#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
++#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
++#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
++#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
++#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
++#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
++#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
++#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
++#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
++#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
++#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
++#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
++#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
++#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
++#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
++#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
++#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
++#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
++#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
++#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
++#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
++#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
++#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
++#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
++#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
++#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
++#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
++#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
++#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
++#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
++#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
++#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
++#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
++#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
++#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
++#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
++#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
++#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
++#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
++#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
++#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
++#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
++#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
++#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
++#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
++#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
++#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
++#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
++#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
++#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
++#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
++#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
++#define IA_DEBUG_REG6__extract_group_MASK 0x800000
++#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
++#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
++#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
++#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
++#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
++#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
++#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
++#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
++#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
++#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
++#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
++#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
++#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
++#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
++#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
++#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
++#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
++#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
++#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
++#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
++#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
++#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
++#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
++#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
++#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
++#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
++#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
++#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
++#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
++#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
++#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
++#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
++#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
++#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
++#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
++#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
++#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
++#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
++#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
++#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
++#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
++#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
++#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
++#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
++#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
++#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
++#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
++#define IA_DEBUG_REG8__grp_continued_MASK 0x800
++#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
++#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
++#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
++#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
++#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
++#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
++#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
++#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
++#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
++#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
++#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
++#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
++#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
++#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
++#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
++#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
++#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
++#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
++#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
++#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
++#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
++#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
++#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
++#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
++#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
++#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
++#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
++#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
++#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
++#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
++#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
++#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
++#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
++#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
++#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
++#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
++#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
++#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
++#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
++#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
++#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
++#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
++#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
++#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
++#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
++#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
++#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
++#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
++#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
++#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
++#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
++#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
++#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
++#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
++#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
++#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
++#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
++#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
++#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
++#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
++#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
++#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
++#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
++#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
++#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
++#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
++#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
++#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
++#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
++#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
++#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
++#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
++#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
++#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
++#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
++#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
++#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
++#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
++#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
++#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
++#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
++#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
++#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
++#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
++#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
++#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
++#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
++#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
++#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
++#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
++#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
++#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
++#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
++#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
++#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
++#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
++#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
++#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
++#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
++#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
++#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
++#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
++#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
++#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
++#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
++#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
++#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
++#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
++#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
++#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
++#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
++#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
++#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
++#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
++#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
++#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
++#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
++#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
++#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
++#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
++#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
++#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
++#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
++#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
++#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
++#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
++#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
++#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
++#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
++#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
++#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
++#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
++#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
++#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
++#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
++#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
++#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
++#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
++#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
++#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
++#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
++#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
++#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
++#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
++#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
++#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
++#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
++#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
++#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
++#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
++#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
++#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
++#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
++#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
++#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
++#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
++#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
++#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
++#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
++#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
++#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
++#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
++#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
++#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
++#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
++#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
++#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
++#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
++#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
++#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
++#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
++#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
++#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
++#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
++#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
++#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
++#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
++#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
++#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
++#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
++#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
++#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
++#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
++#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
++#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
++#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
++#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
++#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
++#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
++#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
++#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
++#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
++#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
++#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
++#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
++#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
++#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
++#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
++#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
++#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
++#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
++#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
++#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
++#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
++#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
++#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
++#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
++#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
++#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
++#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
++#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
++#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
++#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
++#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
++#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
++#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
++#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
++#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
++#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
++#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
++#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
++#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
++#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
++#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
++#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
++#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
++#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
++#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
++#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
++#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
++#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
++#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
++#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
++#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
++#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
++#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
++#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
++#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
++#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
++#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
++#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
++#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
++#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
++#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
++#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
++#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
++#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
++#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
++#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
++#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
++#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
++#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
++#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
++#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
++#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
++#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
++#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
++#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
++#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
++#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
++#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
++#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
++#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
++#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
++#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
++#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
++#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
++#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
++#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
++#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
++#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
++#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
++#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
++#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
++#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
++#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
++#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
++#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
++#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
++#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
++#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
++#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
++#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
++#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
++#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
++#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
++#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
++#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
++#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
++#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
++#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
++#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
++#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
++#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
++#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
++#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
++#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
++#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
++#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
++#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
++#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
++#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
++#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
++#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
++#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
++#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
++#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
++#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
++#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
++#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
++#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
++#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
++#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
++#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
++#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
++#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
++#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
++#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
++#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
++#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
++#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
++#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
++#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
++#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
++#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
++#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
++#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
++#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
++#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
++#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
++#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
++#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
++#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
++#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
++#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
++#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
++#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
++#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
++#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
++#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
++#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
++#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
++#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
++#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
++#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
++#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
++#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
++#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
++#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
++#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
++#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
++#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
++#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
++#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
++#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
++#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
++#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
++#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
++#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
++#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
++#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
++#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
++#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
++#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
++#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
++#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
++#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
++#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
++#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
++#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
++#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
++#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
++#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
++#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
++#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
++#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
++#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
++#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
++#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
++#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
++#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
++#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
++#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
++#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
++#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
++#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
++#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
++#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
++#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
++#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
++#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
++#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
++#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
++#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
++#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
++#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
++#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
++#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
++#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
++#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
++#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
++#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
++#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
++#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
++#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
++#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
++#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
++#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
++#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
++#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
++#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
++#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
++#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
++#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
++#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
++#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
++#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
++#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
++#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
++#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
++#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
++#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
++#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
++#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
++#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
++#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
++#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
++#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
++#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
++#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
++#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
++#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
++#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
++#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
++#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
++#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
++#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
++#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
++#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
++#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
++#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
++#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
++#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
++#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
++#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
++#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
++#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
++#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
++#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
++#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
++#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
++#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
++#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
++#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
++#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
++#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
++#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
++#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
++#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
++#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
++#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
++#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
++#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
++#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
++#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
++#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
++#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
++#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
++#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
++#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
++#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
++#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
++#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
++#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
++#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
++#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
++#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
++#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
++#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
++#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
++#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
++#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
++#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
++#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
++#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
++#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
++#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
++#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
++#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
++#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
++#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
++#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
++#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
++#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
++#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
++#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
++#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
++#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
++#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
++#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
++#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
++#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
++#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
++#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
++#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
++#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
++#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
++#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
++#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
++#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
++#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
++#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
++#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
++#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
++#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
++#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
++#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
++#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
++#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
++#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
++#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
++#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
++#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
++#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
++#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
++#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
++#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
++#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
++#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
++#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
++#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
++#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
++#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
++#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
++#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
++#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
++#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
++#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
++#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
++#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
++#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
++#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
++#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
++#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
++#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
++#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
++#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
++#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
++#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
++#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
++#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
++#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
++#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
++#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
++#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
++#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
++#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
++#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
++#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
++#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
++#define VGT_DEBUG_REG15__counters_full_MASK 0x10
++#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
++#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
++#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
++#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
++#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
++#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
++#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
++#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
++#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
++#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
++#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
++#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
++#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
++#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
++#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
++#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
++#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
++#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
++#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
++#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
++#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
++#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
++#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
++#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
++#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
++#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
++#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
++#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
++#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
++#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
++#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
++#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
++#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
++#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
++#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
++#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
++#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
++#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
++#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
++#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
++#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
++#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
++#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
++#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
++#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
++#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
++#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
++#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
++#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
++#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
++#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
++#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
++#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
++#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
++#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
++#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
++#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
++#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
++#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
++#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
++#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
++#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
++#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
++#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
++#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
++#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
++#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
++#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
++#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
++#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
++#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
++#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
++#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
++#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
++#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
++#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
++#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
++#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
++#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
++#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
++#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
++#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
++#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
++#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
++#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
++#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
++#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
++#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
++#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
++#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
++#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
++#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
++#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
++#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
++#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
++#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
++#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
++#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
++#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
++#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
++#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
++#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
++#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
++#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
++#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
++#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
++#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
++#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
++#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
++#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
++#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
++#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
++#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
++#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
++#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
++#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
++#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
++#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
++#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
++#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
++#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
++#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
++#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
++#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
++#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
++#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
++#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
++#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
++#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
++#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
++#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
++#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
++#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
++#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
++#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
++#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
++#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
++#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
++#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
++#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
++#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
++#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
++#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
++#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
++#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
++#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
++#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
++#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
++#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
++#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
++#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
++#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
++#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
++#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
++#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
++#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
++#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
++#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
++#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
++#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
++#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
++#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
++#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
++#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
++#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
++#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
++#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
++#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
++#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
++#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
++#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
++#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
++#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
++#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
++#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
++#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
++#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
++#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
++#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
++#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
++#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
++#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
++#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
++#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
++#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
++#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
++#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
++#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
++#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
++#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
++#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
++#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
++#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
++#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
++#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
++#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
++#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
++#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
++#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
++#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
++#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
++#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
++#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
++#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
++#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
++#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
++#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
++#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
++#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
++#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
++#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
++#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
++#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
++#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
++#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
++#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
++#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
++#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
++#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
++#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
++#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
++#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
++#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
++#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
++#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
++#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
++#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
++#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
++#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
++#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
++#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
++#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
++#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
++#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
++#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
++#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
++#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
++#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
++#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
++#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
++#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
++#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
++#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
++#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
++#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
++#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
++#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
++#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
++#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
++#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
++#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
++#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
++#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
++#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
++#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
++#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
++#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
++#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
++#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
++#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
++#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
++#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
++#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
++#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
++#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
++#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
++#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
++#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
++#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
++#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
++#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
++#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
++#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
++#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
++#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
++#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
++#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
++#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
++#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
++#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
++#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
++#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
++#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
++#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
++#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
++#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
++#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
++#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
++#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
++#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
++#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
++#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
++#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
++#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
++#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
++#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
++#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
++#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
++#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
++#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
++#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
++#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
++#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
++#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
++#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
++#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
++#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
++#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
++#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
++#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
++#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
++#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
++#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
++#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
++#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
++#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
++#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
++#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
++#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
++#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
++#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
++#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
++#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
++#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
++#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
++#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
++#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
++#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
++#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
++#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
++#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
++#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
++#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
++#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
++#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
++#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
++#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
++#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
++#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
++#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
++#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
++#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
++#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
++#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
++#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
++#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
++#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
++#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
++#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
++#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
++#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
++#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
++#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
++#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
++#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
++#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
++#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
++#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
++#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
++#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
++#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
++#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
++#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
++#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
++#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
++#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
++#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
++#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
++#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
++#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
++#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
++#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
++#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
++#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
++#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
++#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
++#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
++#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
++#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
++#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
++#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
++#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
++#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
++#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
++#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
++#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
++#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
++#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
++#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
++#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
++#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
++#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
++#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
++#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
++#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
++#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
++#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
++#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
++#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
++#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
++#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
++#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
++#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
++#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
++#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
++#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
++#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
++#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
++#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
++#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
++#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
++#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
++#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
++#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
++#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
++#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
++#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
++#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
++#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
++#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
++#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
++#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
++#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
++#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
++#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
++#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
++#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
++#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
++#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
++#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
++#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
++#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
++#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
++#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
++#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
++#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
++#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
++#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
++#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
++#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
++#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
++#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
++#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
++#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
++#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
++#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
++#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
++#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
++#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
++#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
++#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
++#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
++#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
++#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
++#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
++#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
++#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
++#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
++#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
++#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
++#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
++#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
++#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
++#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
++#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
++#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
++#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
++#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
++#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
++#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
++#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
++#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
++#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
++#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
++#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
++#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
++#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
++#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
++#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
++#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
++#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
++#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
++#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
++#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
++#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
++#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
++#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
++#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
++#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
++#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
++#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
++#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
++#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
++#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
++#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
++#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
++#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
++#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
++#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
++#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
++#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
++#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
++#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
++#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
++#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
++#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
++#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
++#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
++#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
++#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
++#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
++#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
++#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
++#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
++#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
++#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
++#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
++#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
++#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
++#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
++#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
++#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
++#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
++#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
++#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
++#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
++#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
++#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
++#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
++#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
++#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
++#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
++#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
++#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
++#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
++#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
++#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
++#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
++#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
++#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
++#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
++#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
++#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
++#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
++#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
++#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
++#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
++#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
++#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
++#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
++#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
++#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
++#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
++#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
++#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
++#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
++#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
++#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
++#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
++#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
++#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
++#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
++#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
++#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
++#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
++#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
++#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
++#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
++#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
++#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
++#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
++#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
++#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
++#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
++#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
++#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
++#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
++#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
++#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
++#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
++#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
++#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
++#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
++#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
++#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
++#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
++#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
++#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
++#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
++#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
++#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
++#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
++#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
++#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
++#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
++#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
++#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
++#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
++#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
++#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
++#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
++#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
++#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
++#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
++#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
++#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
++#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
++#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
++#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
++#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
++#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
++#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
++#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
++#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
++#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
++#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
++#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
++#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
++#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
++#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
++#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
++#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
++#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
++#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
++#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
++#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
++#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
++#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
++#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
++#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
++#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
++#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
++#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
++#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
++#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
++#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
++#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
++#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
++#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
++#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
++#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
++#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
++#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
++#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
++#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
++#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
++#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
++#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
++#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
++#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
++#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
++#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
++#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
++#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
++#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
++#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
++#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
++#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
++#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
++#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
++#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
++#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
++#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
++#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
++#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
++#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
++#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
++#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
++#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
++#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
++#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
++#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
++#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
++#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
++#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
++#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
++#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff
++#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0
++#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
++#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
++#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
++#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
++#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
++#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
++#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
++#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
++#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
++#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
++#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
++#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
++#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
++#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
++#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
++#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
++#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
++#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
++#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
++#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0
++#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6
++#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000
++#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
++#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000
++#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
++#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000
++#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
++#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff
++#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0
++#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
++#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
++#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0
++#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6
++#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000
++#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
++#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000
++#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
++#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000
++#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
++#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff
++#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0
++#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
++#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
++#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0
++#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6
++#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000
++#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
++#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000
++#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
++#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000
++#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
++#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff
++#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0
++#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
++#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
++#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0
++#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6
++#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000
++#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
++#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000
++#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
++#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000
++#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
++#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff
++#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0
++#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
++#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
++#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1
++#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
++#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2
++#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1
++#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc
++#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2
++#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10
++#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
++#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
++#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
++#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0
++#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6
++#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff
++#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
++#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000
++#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
++#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
++#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
++#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000
++#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
++#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
++#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
++#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000
++#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
++#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
++#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
++#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000
++#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
++#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff
++#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0
++#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
++#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
++#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff
++#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
++#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00
++#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
++#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000
++#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
++#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000
++#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
++#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff
++#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
++#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00
++#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
++#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000
++#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
++#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000
++#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
++#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff
++#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
++#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00
++#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
++#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000
++#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
++#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000
++#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
++
++#endif /* GFX_8_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0010-yocto-amd-drm-amdgpu-add-ppsmc-hA.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0010-yocto-amd-drm-amdgpu-add-ppsmc-hA.patch
new file mode 100644
index 00000000..0ce97f7b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0010-yocto-amd-drm-amdgpu-add-ppsmc-hA.patch
@@ -0,0 +1,6799 @@
+From 9083e97732cba4e2f24edfa1299b7aef330b2686 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:22:19 -0400
+Subject: drm/amdgpu: add GMC 7.0 register headers
+
+These are register headers for the GMC (Graphics Memory Controller)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h
+new file mode 100644
+index 0000000..1940e7a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h
+@@ -0,0 +1,657 @@
++/*
++ * GMC_7_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_7_0_D_H
++#define GMC_7_0_D_H
++
++#define mmMC_CONFIG                                                             0x800
++#define mmMC_ARB_AGE_CNTL                                                       0x9bf
++#define mmMC_ARB_RET_CREDITS2                                                   0x9c0
++#define mmMC_ARB_FED_CNTL                                                       0x9c1
++#define mmMC_ARB_GECC2_STATUS                                                   0x9c2
++#define mmMC_ARB_GECC2_MISC                                                     0x9c3
++#define mmMC_ARB_GECC2_DEBUG                                                    0x9c4
++#define mmMC_ARB_GECC2_DEBUG2                                                   0x9c5
++#define mmMC_ARB_GECC2                                                          0x9c9
++#define mmMC_ARB_GECC2_CLI                                                      0x9ca
++#define mmMC_ARB_ADDR_SWIZ0                                                     0x9cb
++#define mmMC_ARB_ADDR_SWIZ1                                                     0x9cc
++#define mmMC_ARB_MISC3                                                          0x9cd
++#define mmMC_ARB_WCDR_2                                                         0x9ce
++#define mmMC_ARB_RTT_DATA                                                       0x9cf
++#define mmMC_ARB_RTT_CNTL0                                                      0x9d0
++#define mmMC_ARB_RTT_CNTL1                                                      0x9d1
++#define mmMC_ARB_RTT_CNTL2                                                      0x9d2
++#define mmMC_ARB_RTT_DEBUG                                                      0x9d3
++#define mmMC_ARB_CAC_CNTL                                                       0x9d4
++#define mmMC_ARB_MISC2                                                          0x9d5
++#define mmMC_ARB_MISC                                                           0x9d6
++#define mmMC_ARB_BANKMAP                                                        0x9d7
++#define mmMC_ARB_RAMCFG                                                         0x9d8
++#define mmMC_ARB_POP                                                            0x9d9
++#define mmMC_ARB_MINCLKS                                                        0x9da
++#define mmMC_ARB_SQM_CNTL                                                       0x9db
++#define mmMC_ARB_ADDR_HASH                                                      0x9dc
++#define mmMC_ARB_DRAM_TIMING                                                    0x9dd
++#define mmMC_ARB_DRAM_TIMING2                                                   0x9de
++#define mmMC_ARB_WTM_CNTL_RD                                                    0x9df
++#define mmMC_ARB_WTM_CNTL_WR                                                    0x9e0
++#define mmMC_ARB_WTM_GRPWT_RD                                                   0x9e1
++#define mmMC_ARB_WTM_GRPWT_WR                                                   0x9e2
++#define mmMC_ARB_TM_CNTL_RD                                                     0x9e3
++#define mmMC_ARB_TM_CNTL_WR                                                     0x9e4
++#define mmMC_ARB_LAZY0_RD                                                       0x9e5
++#define mmMC_ARB_LAZY0_WR                                                       0x9e6
++#define mmMC_ARB_LAZY1_RD                                                       0x9e7
++#define mmMC_ARB_LAZY1_WR                                                       0x9e8
++#define mmMC_ARB_AGE_RD                                                         0x9e9
++#define mmMC_ARB_AGE_WR                                                         0x9ea
++#define mmMC_ARB_RFSH_CNTL                                                      0x9eb
++#define mmMC_ARB_RFSH_RATE                                                      0x9ec
++#define mmMC_ARB_PM_CNTL                                                        0x9ed
++#define mmMC_ARB_GDEC_RD_CNTL                                                   0x9ee
++#define mmMC_ARB_GDEC_WR_CNTL                                                   0x9ef
++#define mmMC_ARB_LM_RD                                                          0x9f0
++#define mmMC_ARB_LM_WR                                                          0x9f1
++#define mmMC_ARB_REMREQ                                                         0x9f2
++#define mmMC_ARB_REPLAY                                                         0x9f3
++#define mmMC_ARB_RET_CREDITS_RD                                                 0x9f4
++#define mmMC_ARB_RET_CREDITS_WR                                                 0x9f5
++#define mmMC_ARB_MAX_LAT_CID                                                    0x9f6
++#define mmMC_ARB_MAX_LAT_RSLT0                                                  0x9f7
++#define mmMC_ARB_MAX_LAT_RSLT1                                                  0x9f8
++#define mmMC_ARB_SSM                                                            0x9f9
++#define mmMC_ARB_CG                                                             0x9fa
++#define mmMC_ARB_WCDR                                                           0x9fb
++#define mmMC_ARB_DRAM_TIMING_1                                                  0x9fc
++#define mmMC_ARB_BUSY_STATUS                                                    0x9fd
++#define mmMC_ARB_DRAM_TIMING2_1                                                 0x9ff
++#define mmMC_ARB_BURST_TIME                                                     0xa02
++#define mmMC_CITF_XTRA_ENABLE                                                   0x96d
++#define mmCC_MC_MAX_CHANNEL                                                     0x96e
++#define mmMC_CG_CONFIG                                                          0x96f
++#define mmMC_CITF_CNTL                                                          0x970
++#define mmMC_CITF_CREDITS_VM                                                    0x971
++#define mmMC_CITF_CREDITS_ARB_RD                                                0x972
++#define mmMC_CITF_CREDITS_ARB_WR                                                0x973
++#define mmMC_CITF_DAGB_CNTL                                                     0x974
++#define mmMC_CITF_INT_CREDITS                                                   0x975
++#define mmMC_CITF_RET_MODE                                                      0x976
++#define mmMC_CITF_DAGB_DLY                                                      0x977
++#define mmMC_RD_GRP_EXT                                                         0x978
++#define mmMC_WR_GRP_EXT                                                         0x979
++#define mmMC_CITF_REMREQ                                                        0x97a
++#define mmMC_WR_TC0                                                             0x97b
++#define mmMC_WR_TC1                                                             0x97c
++#define mmMC_CITF_INT_CREDITS_WR                                                0x97d
++#define mmMC_CITF_WTM_RD_CNTL                                                   0x97f
++#define mmMC_CITF_WTM_WR_CNTL                                                   0x980
++#define mmMC_RD_CB                                                              0x981
++#define mmMC_RD_DB                                                              0x982
++#define mmMC_RD_TC0                                                             0x983
++#define mmMC_RD_TC1                                                             0x984
++#define mmMC_RD_HUB                                                             0x985
++#define mmMC_WR_CB                                                              0x986
++#define mmMC_WR_DB                                                              0x987
++#define mmMC_WR_HUB                                                             0x988
++#define mmMC_CITF_CREDITS_XBAR                                                  0x989
++#define mmMC_RD_GRP_LCL                                                         0x98a
++#define mmMC_WR_GRP_LCL                                                         0x98b
++#define mmMC_CITF_PERF_MON_CNTL2                                                0x98e
++#define mmMC_CITF_PERF_MON_RSLT2                                                0x991
++#define mmMC_CITF_MISC_RD_CG                                                    0x992
++#define mmMC_CITF_MISC_WR_CG                                                    0x993
++#define mmMC_CITF_MISC_VM_CG                                                    0x994
++#define mmMC_HUB_MISC_POWER                                                     0x82d
++#define mmMC_HUB_MISC_HUB_CG                                                    0x82e
++#define mmMC_HUB_MISC_VM_CG                                                     0x82f
++#define mmMC_HUB_MISC_SIP_CG                                                    0x830
++#define mmMC_HUB_MISC_DBG                                                       0x831
++#define mmMC_HUB_MISC_STATUS                                                    0x832
++#define mmMC_HUB_MISC_OVERRIDE                                                  0x833
++#define mmMC_HUB_MISC_FRAMING                                                   0x834
++#define mmMC_HUB_WDP_CNTL                                                       0x835
++#define mmMC_HUB_WDP_ERR                                                        0x836
++#define mmMC_HUB_WDP_BP                                                         0x837
++#define mmMC_HUB_WDP_STATUS                                                     0x838
++#define mmMC_HUB_RDREQ_STATUS                                                   0x839
++#define mmMC_HUB_WRRET_STATUS                                                   0x83a
++#define mmMC_HUB_RDREQ_CNTL                                                     0x83b
++#define mmMC_HUB_WRRET_CNTL                                                     0x83c
++#define mmMC_HUB_RDREQ_WTM_CNTL                                                 0x83d
++#define mmMC_HUB_WDP_WTM_CNTL                                                   0x83e
++#define mmMC_HUB_WDP_CREDITS                                                    0x83f
++#define mmMC_HUB_WDP_MGPU2                                                      0x840
++#define mmMC_HUB_WDP_GBL0                                                       0x841
++#define mmMC_HUB_WDP_GBL1                                                       0x842
++#define mmMC_HUB_WDP_MGPU                                                       0x843
++#define mmMC_HUB_RDREQ_CREDITS                                                  0x844
++#define mmMC_HUB_RDREQ_CREDITS2                                                 0x845
++#define mmMC_HUB_SHARED_DAGB_DLY                                                0x846
++#define mmMC_HUB_MISC_IDLE_STATUS                                               0x847
++#define mmMC_HUB_RDREQ_DMIF_LIMIT                                               0x848
++#define mmMC_HUB_RDREQ_ACPG_LIMIT                                               0x849
++#define mmMC_HUB_WDP_SH2                                                        0x84d
++#define mmMC_HUB_WDP_SH3                                                        0x84e
++#define mmMC_HUB_RDREQ_IA0                                                      0x84f
++#define mmMC_HUB_RDREQ_IA1                                                      0x850
++#define mmMC_HUB_RDREQ_MCDW                                                     0x851
++#define mmMC_HUB_RDREQ_MCDX                                                     0x852
++#define mmMC_HUB_RDREQ_MCDY                                                     0x853
++#define mmMC_HUB_RDREQ_MCDZ                                                     0x854
++#define mmMC_HUB_RDREQ_SIP                                                      0x855
++#define mmMC_HUB_RDREQ_GBL0                                                     0x856
++#define mmMC_HUB_RDREQ_GBL1                                                     0x857
++#define mmMC_HUB_RDREQ_SMU                                                      0x858
++#define mmMC_HUB_RDREQ_CPG                                                      0x859
++#define mmMC_HUB_RDREQ_SDMA0                                                    0x85a
++#define mmMC_HUB_RDREQ_HDP                                                      0x85b
++#define mmMC_HUB_RDREQ_SDMA1                                                    0x85c
++#define mmMC_HUB_RDREQ_RLC                                                      0x85d
++#define mmMC_HUB_RDREQ_SEM                                                      0x85e
++#define mmMC_HUB_RDREQ_VCE                                                      0x85f
++#define mmMC_HUB_RDREQ_UMC                                                      0x860
++#define mmMC_HUB_RDREQ_UVD                                                      0x861
++#define mmMC_HUB_RDREQ_IA                                                       0x862
++#define mmMC_HUB_RDREQ_DMIF                                                     0x863
++#define mmMC_HUB_RDREQ_MCIF                                                     0x864
++#define mmMC_HUB_RDREQ_VMC                                                      0x865
++#define mmMC_HUB_RDREQ_VCEU                                                     0x866
++#define mmMC_HUB_WDP_MCDW                                                       0x867
++#define mmMC_HUB_WDP_MCDX                                                       0x868
++#define mmMC_HUB_WDP_MCDY                                                       0x869
++#define mmMC_HUB_WDP_MCDZ                                                       0x86a
++#define mmMC_HUB_WDP_SIP                                                        0x86b
++#define mmMC_HUB_WDP_CPG                                                        0x86c
++#define mmMC_HUB_WDP_SDMA1                                                      0x86d
++#define mmMC_HUB_WDP_SH0                                                        0x86e
++#define mmMC_HUB_WDP_MCIF                                                       0x86f
++#define mmMC_HUB_WDP_VCE                                                        0x870
++#define mmMC_HUB_WDP_XDP                                                        0x871
++#define mmMC_HUB_WDP_IH                                                         0x872
++#define mmMC_HUB_WDP_RLC                                                        0x873
++#define mmMC_HUB_WDP_SEM                                                        0x874
++#define mmMC_HUB_WDP_SMU                                                        0x875
++#define mmMC_HUB_WDP_SH1                                                        0x876
++#define mmMC_HUB_WDP_UMC                                                        0x877
++#define mmMC_HUB_WDP_UVD                                                        0x878
++#define mmMC_HUB_WDP_HDP                                                        0x879
++#define mmMC_HUB_WDP_SDMA0                                                      0x87a
++#define mmMC_HUB_WRRET_MCDW                                                     0x87b
++#define mmMC_HUB_WRRET_MCDX                                                     0x87c
++#define mmMC_HUB_WRRET_MCDY                                                     0x87d
++#define mmMC_HUB_WRRET_MCDZ                                                     0x87e
++#define mmMC_HUB_WDP_VCEU                                                       0x87f
++#define mmMC_HUB_WDP_XDMAM                                                      0x880
++#define mmMC_HUB_WDP_XDMA                                                       0x881
++#define mmMC_HUB_RDREQ_XDMAM                                                    0x882
++#define mmMC_HUB_RDREQ_ACPG                                                     0x883
++#define mmMC_HUB_RDREQ_ACPO                                                     0x884
++#define mmMC_HUB_RDREQ_SAM                                                      0x885
++#define mmMC_HUB_WDP_ACPG                                                       0x886
++#define mmMC_HUB_WDP_ACPO                                                       0x887
++#define mmMC_HUB_WDP_SAM                                                        0x888
++#define mmMC_HUB_RDREQ_CPC                                                      0x889
++#define mmMC_HUB_RDREQ_CPF                                                      0x88a
++#define mmMC_HUB_WDP_CPC                                                        0x88b
++#define mmMC_HUB_WDP_CPF                                                        0x88c
++#define mmMC_RPB_CONF                                                           0x94d
++#define mmMC_RPB_IF_CONF                                                        0x94e
++#define mmMC_RPB_DBG1                                                           0x94f
++#define mmMC_RPB_EFF_CNTL                                                       0x950
++#define mmMC_RPB_ARB_CNTL                                                       0x951
++#define mmMC_RPB_BIF_CNTL                                                       0x952
++#define mmMC_RPB_WR_SWITCH_CNTL                                                 0x953
++#define mmMC_RPB_WR_COMBINE_CNTL                                                0x954
++#define mmMC_RPB_RD_SWITCH_CNTL                                                 0x955
++#define mmMC_RPB_CID_QUEUE_WR                                                   0x956
++#define mmMC_RPB_CID_QUEUE_RD                                                   0x957
++#define mmMC_RPB_PERF_COUNTER_CNTL                                              0x958
++#define mmMC_RPB_PERF_COUNTER_STATUS                                            0x959
++#define mmMC_RPB_CID_QUEUE_EX                                                   0x95a
++#define mmMC_RPB_CID_QUEUE_EX_DATA                                              0x95b
++#define mmMC_SHARED_CHMAP                                                       0x801
++#define mmMC_SHARED_CHREMAP                                                     0x802
++#define mmMC_RD_GRP_GFX                                                         0x803
++#define mmMC_WR_GRP_GFX                                                         0x804
++#define mmMC_RD_GRP_SYS                                                         0x805
++#define mmMC_WR_GRP_SYS                                                         0x806
++#define mmMC_RD_GRP_OTH                                                         0x807
++#define mmMC_WR_GRP_OTH                                                         0x808
++#define mmMC_VM_FB_LOCATION                                                     0x809
++#define mmMC_VM_AGP_TOP                                                         0x80a
++#define mmMC_VM_AGP_BOT                                                         0x80b
++#define mmMC_VM_AGP_BASE                                                        0x80c
++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR                                        0x80d
++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                       0x80e
++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR                                    0x80f
++#define mmMC_VM_DC_WRITE_CNTL                                                   0x810
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR                                  0x811
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR                                  0x812
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR                                  0x813
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR                                  0x814
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR                                 0x815
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR                                 0x816
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR                                 0x817
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR                                 0x818
++#define mmMC_VM_MX_L1_TLB_CNTL                                                  0x819
++#define mmMC_VM_FB_OFFSET                                                       0x81a
++#define mmMC_VM_STEERING                                                        0x81b
++#define mmMC_CONFIG_MCD                                                         0x828
++#define mmMC_CG_CONFIG_MCD                                                      0x829
++#define mmMC_MEM_POWER_LS                                                       0x82a
++#define mmMC_SHARED_BLACKOUT_CNTL                                               0x82b
++#define mmMC_VM_MB_L1_TLB0_DEBUG                                                0x891
++#define mmMC_VM_MB_L1_TLB2_DEBUG                                                0x893
++#define mmMC_VM_MB_L1_TLB0_STATUS                                               0x895
++#define mmMC_VM_MB_L1_TLB1_STATUS                                               0x896
++#define mmMC_VM_MB_L1_TLB2_STATUS                                               0x897
++#define mmMC_VM_MB_L2ARBITER_L2_CREDITS                                         0x8a1
++#define mmMC_VM_MB_L1_TLB3_DEBUG                                                0x8a5
++#define mmMC_VM_MB_L1_TLB3_STATUS                                               0x8a6
++#define mmMC_VM_MD_L1_TLB0_DEBUG                                                0x998
++#define mmMC_VM_MD_L1_TLB1_DEBUG                                                0x999
++#define mmMC_VM_MD_L1_TLB2_DEBUG                                                0x99a
++#define mmMC_VM_MD_L1_TLB0_STATUS                                               0x99b
++#define mmMC_VM_MD_L1_TLB1_STATUS                                               0x99c
++#define mmMC_VM_MD_L1_TLB2_STATUS                                               0x99d
++#define mmMC_VM_MD_L2ARBITER_L2_CREDITS                                         0x9a4
++#define mmMC_VM_MD_L1_TLB3_DEBUG                                                0x9a7
++#define mmMC_VM_MD_L1_TLB3_STATUS                                               0x9a8
++#define mmMC_XPB_RTR_SRC_APRTR0                                                 0x8cd
++#define mmMC_XPB_RTR_SRC_APRTR1                                                 0x8ce
++#define mmMC_XPB_RTR_SRC_APRTR2                                                 0x8cf
++#define mmMC_XPB_RTR_SRC_APRTR3                                                 0x8d0
++#define mmMC_XPB_RTR_SRC_APRTR4                                                 0x8d1
++#define mmMC_XPB_RTR_SRC_APRTR5                                                 0x8d2
++#define mmMC_XPB_RTR_SRC_APRTR6                                                 0x8d3
++#define mmMC_XPB_RTR_SRC_APRTR7                                                 0x8d4
++#define mmMC_XPB_RTR_SRC_APRTR8                                                 0x8d5
++#define mmMC_XPB_RTR_SRC_APRTR9                                                 0x8d6
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR0                                            0x8d7
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR1                                            0x8d8
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR2                                            0x8d9
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR3                                            0x8da
++#define mmMC_XPB_RTR_DEST_MAP0                                                  0x8db
++#define mmMC_XPB_RTR_DEST_MAP1                                                  0x8dc
++#define mmMC_XPB_RTR_DEST_MAP2                                                  0x8dd
++#define mmMC_XPB_RTR_DEST_MAP3                                                  0x8de
++#define mmMC_XPB_RTR_DEST_MAP4                                                  0x8df
++#define mmMC_XPB_RTR_DEST_MAP5                                                  0x8e0
++#define mmMC_XPB_RTR_DEST_MAP6                                                  0x8e1
++#define mmMC_XPB_RTR_DEST_MAP7                                                  0x8e2
++#define mmMC_XPB_RTR_DEST_MAP8                                                  0x8e3
++#define mmMC_XPB_RTR_DEST_MAP9                                                  0x8e4
++#define mmMC_XPB_XDMA_RTR_DEST_MAP0                                             0x8e5
++#define mmMC_XPB_XDMA_RTR_DEST_MAP1                                             0x8e6
++#define mmMC_XPB_XDMA_RTR_DEST_MAP2                                             0x8e7
++#define mmMC_XPB_XDMA_RTR_DEST_MAP3                                             0x8e8
++#define mmMC_XPB_CLG_CFG0                                                       0x8e9
++#define mmMC_XPB_CLG_CFG1                                                       0x8ea
++#define mmMC_XPB_CLG_CFG2                                                       0x8eb
++#define mmMC_XPB_CLG_CFG3                                                       0x8ec
++#define mmMC_XPB_CLG_CFG4                                                       0x8ed
++#define mmMC_XPB_CLG_CFG5                                                       0x8ee
++#define mmMC_XPB_CLG_CFG6                                                       0x8ef
++#define mmMC_XPB_CLG_CFG7                                                       0x8f0
++#define mmMC_XPB_CLG_CFG8                                                       0x8f1
++#define mmMC_XPB_CLG_CFG9                                                       0x8f2
++#define mmMC_XPB_CLG_CFG10                                                      0x8f3
++#define mmMC_XPB_CLG_CFG11                                                      0x8f4
++#define mmMC_XPB_CLG_CFG12                                                      0x8f5
++#define mmMC_XPB_CLG_CFG13                                                      0x8f6
++#define mmMC_XPB_CLG_CFG14                                                      0x8f7
++#define mmMC_XPB_CLG_CFG15                                                      0x8f8
++#define mmMC_XPB_CLG_CFG16                                                      0x8f9
++#define mmMC_XPB_CLG_CFG17                                                      0x8fa
++#define mmMC_XPB_CLG_CFG18                                                      0x8fb
++#define mmMC_XPB_CLG_CFG19                                                      0x8fc
++#define mmMC_XPB_CLG_EXTRA                                                      0x8fd
++#define mmMC_XPB_LB_ADDR                                                        0x8fe
++#define mmMC_XPB_UNC_THRESH_HST                                                 0x8ff
++#define mmMC_XPB_UNC_THRESH_SID                                                 0x900
++#define mmMC_XPB_WCB_STS                                                        0x901
++#define mmMC_XPB_WCB_CFG                                                        0x902
++#define mmMC_XPB_P2P_BAR_CFG                                                    0x903
++#define mmMC_XPB_P2P_BAR0                                                       0x904
++#define mmMC_XPB_P2P_BAR1                                                       0x905
++#define mmMC_XPB_P2P_BAR2                                                       0x906
++#define mmMC_XPB_P2P_BAR3                                                       0x907
++#define mmMC_XPB_P2P_BAR4                                                       0x908
++#define mmMC_XPB_P2P_BAR5                                                       0x909
++#define mmMC_XPB_P2P_BAR6                                                       0x90a
++#define mmMC_XPB_P2P_BAR7                                                       0x90b
++#define mmMC_XPB_P2P_BAR_SETUP                                                  0x90c
++#define mmMC_XPB_P2P_BAR_DEBUG                                                  0x90d
++#define mmMC_XPB_P2P_BAR_DELTA_ABOVE                                            0x90e
++#define mmMC_XPB_P2P_BAR_DELTA_BELOW                                            0x90f
++#define mmMC_XPB_PEER_SYS_BAR0                                                  0x910
++#define mmMC_XPB_PEER_SYS_BAR1                                                  0x911
++#define mmMC_XPB_PEER_SYS_BAR2                                                  0x912
++#define mmMC_XPB_PEER_SYS_BAR3                                                  0x913
++#define mmMC_XPB_PEER_SYS_BAR4                                                  0x914
++#define mmMC_XPB_PEER_SYS_BAR5                                                  0x915
++#define mmMC_XPB_PEER_SYS_BAR6                                                  0x916
++#define mmMC_XPB_PEER_SYS_BAR7                                                  0x917
++#define mmMC_XPB_PEER_SYS_BAR8                                                  0x918
++#define mmMC_XPB_PEER_SYS_BAR9                                                  0x919
++#define mmMC_XPB_XDMA_PEER_SYS_BAR0                                             0x91a
++#define mmMC_XPB_XDMA_PEER_SYS_BAR1                                             0x91b
++#define mmMC_XPB_XDMA_PEER_SYS_BAR2                                             0x91c
++#define mmMC_XPB_XDMA_PEER_SYS_BAR3                                             0x91d
++#define mmMC_XPB_CLK_GAT                                                        0x91e
++#define mmMC_XPB_INTF_CFG                                                       0x91f
++#define mmMC_XPB_INTF_STS                                                       0x920
++#define mmMC_XPB_PIPE_STS                                                       0x921
++#define mmMC_XPB_SUB_CTRL                                                       0x922
++#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB                                       0x923
++#define mmMC_XPB_PERF_KNOBS                                                     0x924
++#define mmMC_XPB_STICKY                                                         0x925
++#define mmMC_XPB_STICKY_W1C                                                     0x926
++#define mmMC_XPB_MISC_CFG                                                       0x927
++#define mmMC_XPB_CLG_CFG20                                                      0x928
++#define mmMC_XPB_CLG_CFG21                                                      0x929
++#define mmMC_XPB_CLG_CFG22                                                      0x92a
++#define mmMC_XPB_CLG_CFG23                                                      0x92b
++#define mmMC_XPB_CLG_CFG24                                                      0x92c
++#define mmMC_XPB_CLG_CFG25                                                      0x92d
++#define mmMC_XPB_CLG_CFG26                                                      0x92e
++#define mmMC_XPB_CLG_CFG27                                                      0x92f
++#define mmMC_XPB_CLG_CFG28                                                      0x930
++#define mmMC_XPB_CLG_CFG29                                                      0x931
++#define mmMC_XPB_CLG_CFG30                                                      0x932
++#define mmMC_XPB_CLG_CFG31                                                      0x933
++#define mmMC_XPB_INTF_CFG2                                                      0x934
++#define mmMC_XPB_CLG_EXTRA_RD                                                   0x935
++#define mmMC_XPB_CLG_CFG32                                                      0x936
++#define mmMC_XPB_CLG_CFG33                                                      0x937
++#define mmMC_XPB_CLG_CFG34                                                      0x938
++#define mmMC_XPB_CLG_CFG35                                                      0x939
++#define mmMC_XPB_CLG_CFG36                                                      0x93a
++#define mmMC_XBAR_ADDR_DEC                                                      0xc80
++#define mmMC_XBAR_REMOTE                                                        0xc81
++#define mmMC_XBAR_WRREQ_CREDIT                                                  0xc82
++#define mmMC_XBAR_RDREQ_CREDIT                                                  0xc83
++#define mmMC_XBAR_RDREQ_PRI_CREDIT                                              0xc84
++#define mmMC_XBAR_WRRET_CREDIT1                                                 0xc85
++#define mmMC_XBAR_WRRET_CREDIT2                                                 0xc86
++#define mmMC_XBAR_RDRET_CREDIT1                                                 0xc87
++#define mmMC_XBAR_RDRET_CREDIT2                                                 0xc88
++#define mmMC_XBAR_RDRET_PRI_CREDIT1                                             0xc89
++#define mmMC_XBAR_RDRET_PRI_CREDIT2                                             0xc8a
++#define mmMC_XBAR_CHTRIREMAP                                                    0xc8b
++#define mmMC_XBAR_TWOCHAN                                                       0xc8c
++#define mmMC_XBAR_ARB                                                           0xc8d
++#define mmMC_XBAR_ARB_MAX_BURST                                                 0xc8e
++#define mmMC_XBAR_PERF_MON_CNTL0                                                0xc8f
++#define mmMC_XBAR_PERF_MON_CNTL1                                                0xc90
++#define mmMC_XBAR_PERF_MON_CNTL2                                                0xc91
++#define mmMC_XBAR_PERF_MON_RSLT0                                                0xc92
++#define mmMC_XBAR_PERF_MON_RSLT1                                                0xc93
++#define mmMC_XBAR_PERF_MON_RSLT2                                                0xc94
++#define mmMC_XBAR_PERF_MON_RSLT3                                                0xc95
++#define mmMC_XBAR_PERF_MON_MAX_THSH                                             0xc96
++#define mmMC_XBAR_SPARE0                                                        0xc97
++#define mmMC_XBAR_SPARE1                                                        0xc98
++#define mmMC_CITF_PERFCOUNTER_LO                                                0x7a0
++#define mmMC_HUB_PERFCOUNTER_LO                                                 0x7a1
++#define mmMC_RPB_PERFCOUNTER_LO                                                 0x7a2
++#define mmMC_MCBVM_PERFCOUNTER_LO                                               0x7a3
++#define mmMC_MCDVM_PERFCOUNTER_LO                                               0x7a4
++#define mmMC_VM_L2_PERFCOUNTER_LO                                               0x7a5
++#define mmMC_ARB_PERFCOUNTER_LO                                                 0x7a6
++#define mmATC_PERFCOUNTER_LO                                                    0x7a7
++#define mmMC_CITF_PERFCOUNTER_HI                                                0x7a8
++#define mmMC_HUB_PERFCOUNTER_HI                                                 0x7a9
++#define mmMC_MCBVM_PERFCOUNTER_HI                                               0x7aa
++#define mmMC_MCDVM_PERFCOUNTER_HI                                               0x7ab
++#define mmMC_RPB_PERFCOUNTER_HI                                                 0x7ac
++#define mmMC_VM_L2_PERFCOUNTER_HI                                               0x7ad
++#define mmMC_ARB_PERFCOUNTER_HI                                                 0x7ae
++#define mmATC_PERFCOUNTER_HI                                                    0x7af
++#define mmMC_CITF_PERFCOUNTER0_CFG                                              0x7b0
++#define mmMC_CITF_PERFCOUNTER1_CFG                                              0x7b1
++#define mmMC_CITF_PERFCOUNTER2_CFG                                              0x7b2
++#define mmMC_CITF_PERFCOUNTER3_CFG                                              0x7b3
++#define mmMC_HUB_PERFCOUNTER0_CFG                                               0x7b4
++#define mmMC_HUB_PERFCOUNTER1_CFG                                               0x7b5
++#define mmMC_HUB_PERFCOUNTER2_CFG                                               0x7b6
++#define mmMC_HUB_PERFCOUNTER3_CFG                                               0x7b7
++#define mmMC_RPB_PERFCOUNTER0_CFG                                               0x7b8
++#define mmMC_RPB_PERFCOUNTER1_CFG                                               0x7b9
++#define mmMC_RPB_PERFCOUNTER2_CFG                                               0x7ba
++#define mmMC_RPB_PERFCOUNTER3_CFG                                               0x7bb
++#define mmMC_ARB_PERFCOUNTER0_CFG                                               0x7bc
++#define mmMC_ARB_PERFCOUNTER1_CFG                                               0x7bd
++#define mmMC_ARB_PERFCOUNTER2_CFG                                               0x7be
++#define mmMC_ARB_PERFCOUNTER3_CFG                                               0x7bf
++#define mmMC_MCBVM_PERFCOUNTER0_CFG                                             0x7c0
++#define mmMC_MCBVM_PERFCOUNTER1_CFG                                             0x7c1
++#define mmMC_MCBVM_PERFCOUNTER2_CFG                                             0x7c2
++#define mmMC_MCBVM_PERFCOUNTER3_CFG                                             0x7c3
++#define mmMC_MCDVM_PERFCOUNTER0_CFG                                             0x7c4
++#define mmMC_MCDVM_PERFCOUNTER1_CFG                                             0x7c5
++#define mmMC_MCDVM_PERFCOUNTER2_CFG                                             0x7c6
++#define mmMC_MCDVM_PERFCOUNTER3_CFG                                             0x7c7
++#define mmATC_PERFCOUNTER0_CFG                                                  0x7c8
++#define mmATC_PERFCOUNTER1_CFG                                                  0x7c9
++#define mmATC_PERFCOUNTER2_CFG                                                  0x7ca
++#define mmATC_PERFCOUNTER3_CFG                                                  0x7cb
++#define mmMC_VM_L2_PERFCOUNTER0_CFG                                             0x7cc
++#define mmMC_VM_L2_PERFCOUNTER1_CFG                                             0x7cd
++#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL                                         0x7ce
++#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL                                          0x7cf
++#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL                                          0x7d0
++#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL                                        0x7d1
++#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL                                        0x7d2
++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                        0x7d3
++#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL                                          0x7d4
++#define mmATC_PERFCOUNTER_RSLT_CNTL                                             0x7d5
++#define mmCHUB_ATC_PERFCOUNTER_LO                                               0x7d6
++#define mmCHUB_ATC_PERFCOUNTER_HI                                               0x7d7
++#define mmCHUB_ATC_PERFCOUNTER0_CFG                                             0x7d8
++#define mmCHUB_ATC_PERFCOUNTER1_CFG                                             0x7d9
++#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL                                        0x7da
++#define mmMC_ARB_PERF_MON_CNTL0_ECC                                             0x7db
++#define mmATC_VM_APERTURE0_LOW_ADDR                                             0xcc0
++#define mmATC_VM_APERTURE1_LOW_ADDR                                             0xcc1
++#define mmATC_VM_APERTURE0_HIGH_ADDR                                            0xcc2
++#define mmATC_VM_APERTURE1_HIGH_ADDR                                            0xcc3
++#define mmATC_VM_APERTURE0_CNTL                                                 0xcc4
++#define mmATC_VM_APERTURE1_CNTL                                                 0xcc5
++#define mmATC_VM_APERTURE0_CNTL2                                                0xcc6
++#define mmATC_VM_APERTURE1_CNTL2                                                0xcc7
++#define mmATC_ATS_CNTL                                                          0xcc9
++#define mmATC_ATS_DEBUG                                                         0xcca
++#define mmATC_ATS_FAULT_DEBUG                                                   0xccb
++#define mmATC_ATS_STATUS                                                        0xccc
++#define mmATC_ATS_FAULT_CNTL                                                    0xccd
++#define mmATC_ATS_FAULT_STATUS_INFO                                             0xcce
++#define mmATC_ATS_FAULT_STATUS_ADDR                                             0xccf
++#define mmATC_ATS_DEFAULT_PAGE_LOW                                              0xcd0
++#define mmATC_ATS_DEFAULT_PAGE_CNTL                                             0xcd1
++#define mmATC_MISC_CG                                                           0xcd4
++#define mmATC_L2_CNTL                                                           0xcd5
++#define mmATC_L2_CNTL2                                                          0xcd6
++#define mmATC_L2_DEBUG                                                          0xcd7
++#define mmATC_L2_DEBUG2                                                         0xcd8
++#define mmATC_L1_CNTL                                                           0xcdc
++#define mmATC_L1_ADDRESS_OFFSET                                                 0xcdd
++#define mmATC_L1RD_DEBUG_TLB                                                    0xcde
++#define mmATC_L1WR_DEBUG_TLB                                                    0xcdf
++#define mmATC_L1RD_STATUS                                                       0xce0
++#define mmATC_L1WR_STATUS                                                       0xce1
++#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS                                  0xce6
++#define mmATC_VMID0_PASID_MAPPING                                               0xce7
++#define mmATC_VMID1_PASID_MAPPING                                               0xce8
++#define mmATC_VMID2_PASID_MAPPING                                               0xce9
++#define mmATC_VMID3_PASID_MAPPING                                               0xcea
++#define mmATC_VMID4_PASID_MAPPING                                               0xceb
++#define mmATC_VMID5_PASID_MAPPING                                               0xcec
++#define mmATC_VMID6_PASID_MAPPING                                               0xced
++#define mmATC_VMID7_PASID_MAPPING                                               0xcee
++#define mmATC_VMID8_PASID_MAPPING                                               0xcef
++#define mmATC_VMID9_PASID_MAPPING                                               0xcf0
++#define mmATC_VMID10_PASID_MAPPING                                              0xcf1
++#define mmATC_VMID11_PASID_MAPPING                                              0xcf2
++#define mmATC_VMID12_PASID_MAPPING                                              0xcf3
++#define mmATC_VMID13_PASID_MAPPING                                              0xcf4
++#define mmATC_VMID14_PASID_MAPPING                                              0xcf5
++#define mmATC_VMID15_PASID_MAPPING                                              0xcf6
++#define mmGMCON_RENG_RAM_INDEX                                                  0xd40
++#define mmGMCON_RENG_RAM_DATA                                                   0xd41
++#define mmGMCON_RENG_EXECUTE                                                    0xd42
++#define mmGMCON_MISC                                                            0xd43
++#define mmGMCON_MISC2                                                           0xd44
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0                                     0xd45
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1                                     0xd46
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2                                     0xd47
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0                                  0xd48
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1                                  0xd49
++#define mmGMCON_PERF_MON_CNTL0                                                  0xd4a
++#define mmGMCON_PERF_MON_CNTL1                                                  0xd4b
++#define mmGMCON_PERF_MON_RSLT0                                                  0xd4c
++#define mmGMCON_PERF_MON_RSLT1                                                  0xd4d
++#define mmGMCON_PGFSM_CONFIG                                                    0xd4e
++#define mmGMCON_PGFSM_WRITE                                                     0xd4f
++#define mmGMCON_PGFSM_READ                                                      0xd50
++#define mmGMCON_MISC3                                                           0xd51
++#define mmGMCON_MASK                                                            0xd52
++#define mmGMCON_DEBUG                                                           0xd5f
++#define mmVM_L2_CNTL                                                            0x500
++#define mmVM_L2_CNTL2                                                           0x501
++#define mmVM_L2_CNTL3                                                           0x502
++#define mmVM_L2_STATUS                                                          0x503
++#define mmVM_CONTEXT0_CNTL                                                      0x504
++#define mmVM_CONTEXT1_CNTL                                                      0x505
++#define mmVM_DUMMY_PAGE_FAULT_CNTL                                              0x506
++#define mmVM_DUMMY_PAGE_FAULT_ADDR                                              0x507
++#define mmVM_CONTEXT0_CNTL2                                                     0x50c
++#define mmVM_CONTEXT1_CNTL2                                                     0x50d
++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR                                      0x50e
++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR                                      0x50f
++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR                                     0x510
++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR                                     0x511
++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR                                     0x512
++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR                                     0x513
++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR                                     0x514
++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR                                     0x515
++#define mmVM_INVALIDATE_REQUEST                                                 0x51e
++#define mmVM_INVALIDATE_RESPONSE                                                0x51f
++#define mmVM_PRT_APERTURE0_LOW_ADDR                                             0x52c
++#define mmVM_PRT_APERTURE1_LOW_ADDR                                             0x52d
++#define mmVM_PRT_APERTURE2_LOW_ADDR                                             0x52e
++#define mmVM_PRT_APERTURE3_LOW_ADDR                                             0x52f
++#define mmVM_PRT_APERTURE0_HIGH_ADDR                                            0x530
++#define mmVM_PRT_APERTURE1_HIGH_ADDR                                            0x531
++#define mmVM_PRT_APERTURE2_HIGH_ADDR                                            0x532
++#define mmVM_PRT_APERTURE3_HIGH_ADDR                                            0x533
++#define mmVM_PRT_CNTL                                                           0x534
++#define mmVM_CONTEXTS_DISABLE                                                   0x535
++#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS                                   0x536
++#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS                                   0x537
++#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT                                 0x538
++#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT                                 0x539
++#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR                                     0x53e
++#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR                                     0x53f
++#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR                             0x546
++#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR                             0x547
++#define mmVM_FAULT_CLIENT_ID                                                    0x54e
++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR                                      0x54f
++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR                                      0x550
++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR                                      0x551
++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR                                      0x552
++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR                                      0x553
++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR                                      0x554
++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR                                      0x555
++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR                                      0x556
++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR                                     0x557
++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR                                     0x558
++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR                                       0x55f
++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR                                       0x560
++#define mmVM_DEBUG                                                              0x56f
++#define mmVM_L2_CG                                                              0x570
++#define mmVM_L2_BANK_SELECT_MASKA                                               0x572
++#define mmVM_L2_BANK_SELECT_MASKB                                               0x573
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR                             0x575
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR                            0x576
++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET                                0x577
++#define mmMC_ARB_HARSH_EN_RD                                                    0xdc0
++#define mmMC_ARB_HARSH_EN_WR                                                    0xdc1
++#define mmMC_ARB_HARSH_TX_HI0_RD                                                0xdc2
++#define mmMC_ARB_HARSH_TX_HI0_WR                                                0xdc3
++#define mmMC_ARB_HARSH_TX_HI1_RD                                                0xdc4
++#define mmMC_ARB_HARSH_TX_HI1_WR                                                0xdc5
++#define mmMC_ARB_HARSH_TX_LO0_RD                                                0xdc6
++#define mmMC_ARB_HARSH_TX_LO0_WR                                                0xdc7
++#define mmMC_ARB_HARSH_TX_LO1_RD                                                0xdc8
++#define mmMC_ARB_HARSH_TX_LO1_WR                                                0xdc9
++#define mmMC_ARB_HARSH_BWPERIOD0_RD                                             0xdca
++#define mmMC_ARB_HARSH_BWPERIOD0_WR                                             0xdcb
++#define mmMC_ARB_HARSH_BWPERIOD1_RD                                             0xdcc
++#define mmMC_ARB_HARSH_BWPERIOD1_WR                                             0xdcd
++#define mmMC_ARB_HARSH_BWCNT0_RD                                                0xdce
++#define mmMC_ARB_HARSH_BWCNT0_WR                                                0xdcf
++#define mmMC_ARB_HARSH_BWCNT1_RD                                                0xdd0
++#define mmMC_ARB_HARSH_BWCNT1_WR                                                0xdd1
++#define mmMC_ARB_HARSH_SAT0_RD                                                  0xdd2
++#define mmMC_ARB_HARSH_SAT0_WR                                                  0xdd3
++#define mmMC_ARB_HARSH_SAT1_RD                                                  0xdd4
++#define mmMC_ARB_HARSH_SAT1_WR                                                  0xdd5
++#define mmMC_ARB_HARSH_CTL_RD                                                   0xdd6
++#define mmMC_ARB_HARSH_CTL_WR                                                   0xdd7
++#define mmMC_FUS_DRAM0_CS0_BASE                                                 0xa05
++#define mmMC_FUS_DRAM1_CS0_BASE                                                 0xa06
++#define mmMC_FUS_DRAM0_CS1_BASE                                                 0xa07
++#define mmMC_FUS_DRAM1_CS1_BASE                                                 0xa08
++#define mmMC_FUS_DRAM0_CS2_BASE                                                 0xa09
++#define mmMC_FUS_DRAM1_CS2_BASE                                                 0xa0a
++#define mmMC_FUS_DRAM0_CS3_BASE                                                 0xa0b
++#define mmMC_FUS_DRAM1_CS3_BASE                                                 0xa0c
++#define mmMC_FUS_DRAM0_CS01_MASK                                                0xa0d
++#define mmMC_FUS_DRAM1_CS01_MASK                                                0xa0e
++#define mmMC_FUS_DRAM0_CS23_MASK                                                0xa0f
++#define mmMC_FUS_DRAM1_CS23_MASK                                                0xa10
++#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING                                        0xa11
++#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING                                        0xa12
++#define mmMC_FUS_DRAM0_CTL_BASE                                                 0xa13
++#define mmMC_FUS_DRAM1_CTL_BASE                                                 0xa14
++#define mmMC_FUS_DRAM0_CTL_LIMIT                                                0xa15
++#define mmMC_FUS_DRAM1_CTL_LIMIT                                                0xa16
++#define mmMC_FUS_DRAM_CTL_HIGH_01                                               0xa17
++#define mmMC_FUS_DRAM_CTL_HIGH_23                                               0xa18
++#define mmMC_FUS_DRAM_MODE                                                      0xa19
++#define mmMC_FUS_DRAM_APER_BASE                                                 0xa1a
++#define mmMC_FUS_DRAM_APER_TOP                                                  0xa1b
++#define mmMC_FUS_DRAM_C6SAVE_APER_BASE                                          0xa1c
++#define mmMC_FUS_DRAM_C6SAVE_APER_TOP                                           0xa1d
++#define mmMC_FUS_DRAM_APER_DEF                                                  0xa1e
++#define mmMC_FUS_ARB_GARLIC_ISOC_PRI                                            0xa1f
++#define mmMC_FUS_ARB_GARLIC_CNTL                                                0xa20
++#define mmMC_FUS_ARB_GARLIC_WR_PRI                                              0xa21
++#define mmMC_FUS_ARB_GARLIC_WR_PRI2                                             0xa22
++#define mmMC_CG_DATAPORT                                                        0xa32
++#define mmCHUB_ATC_L1_DEBUG_TLB                                                 0x8c00
++#define mmCHUB_ATC_L1_STATUS                                                    0x8c01
++
++#endif /* GMC_7_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h
+new file mode 100644
+index 0000000..64d3c23
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h
+@@ -0,0 +1,6116 @@
++/*
++ * GMC_7_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_7_0_SH_MASK_H
++#define GMC_7_0_SH_MASK_H
++
++#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
++#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
++#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
++#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
++#define MC_ARB_FED_CNTL__MODE_MASK 0x3
++#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
++#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
++#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
++#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
++#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
++#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
++#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
++#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
++#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
++#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
++#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
++#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
++#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
++#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
++#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
++#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
++#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
++#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
++#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
++#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
++#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
++#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
++#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
++#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
++#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
++#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
++#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
++#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
++#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
++#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
++#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffff80
++#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0x7
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
++#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
++#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
++#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
++#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
++#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
++#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
++#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
++#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
++#define MC_ARB_GECC2__ENABLE_MASK 0x1
++#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
++#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
++#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
++#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
++#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
++#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
++#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
++#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
++#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
++#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
++#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
++#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
++#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
++#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
++#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
++#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
++#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
++#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
++#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
++#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
++#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
++#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
++#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
++#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
++#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
++#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
++#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
++#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffffe
++#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x1
++#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
++#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
++#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
++#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
++#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
++#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
++#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
++#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
++#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
++#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
++#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
++#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
++#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
++#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
++#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
++#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
++#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
++#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
++#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
++#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
++#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
++#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
++#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
++#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
++#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
++#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
++#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
++#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
++#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
++#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
++#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
++#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
++#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
++#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
++#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
++#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
++#define MC_ARB_MISC2__GECC_MASK 0x40000
++#define MC_ARB_MISC2__GECC__SHIFT 0x12
++#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
++#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
++#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
++#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
++#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
++#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
++#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
++#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
++#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
++#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
++#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
++#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
++#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
++#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
++#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
++#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
++#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
++#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
++#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
++#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
++#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
++#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
++#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
++#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
++#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
++#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
++#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
++#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
++#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
++#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
++#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
++#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
++#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
++#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
++#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
++#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
++#define MC_ARB_BANKMAP__BANK0_MASK 0xf
++#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
++#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
++#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
++#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
++#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
++#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
++#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
++#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
++#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
++#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
++#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
++#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
++#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
++#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
++#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
++#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
++#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
++#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
++#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
++#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
++#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
++#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
++#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
++#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
++#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
++#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
++#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
++#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
++#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
++#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
++#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
++#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
++#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
++#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
++#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
++#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
++#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
++#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
++#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
++#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
++#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
++#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
++#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
++#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
++#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
++#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
++#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
++#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
++#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
++#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
++#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
++#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
++#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
++#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
++#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
++#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
++#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
++#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
++#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
++#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
++#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
++#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
++#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
++#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
++#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
++#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
++#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
++#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
++#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
++#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
++#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
++#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
++#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
++#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
++#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
++#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
++#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
++#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
++#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
++#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
++#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
++#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
++#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
++#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
++#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
++#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
++#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
++#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
++#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
++#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
++#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
++#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
++#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
++#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
++#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
++#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
++#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
++#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
++#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
++#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
++#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
++#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
++#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
++#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
++#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
++#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
++#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
++#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
++#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
++#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
++#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
++#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
++#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
++#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
++#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
++#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
++#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
++#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
++#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
++#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
++#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
++#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_SSM__FORMAT_MASK 0x1f
++#define MC_ARB_SSM__FORMAT__SHIFT 0x0
++#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
++#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
++#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
++#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
++#define MC_ARB_CG__RSV_0_MASK 0xff0000
++#define MC_ARB_CG__RSV_0__SHIFT 0x10
++#define MC_ARB_CG__RSV_1_MASK 0xff000000
++#define MC_ARB_CG__RSV_1__SHIFT 0x18
++#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
++#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
++#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
++#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
++#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
++#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
++#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
++#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
++#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
++#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
++#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
++#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
++#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
++#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
++#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
++#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
++#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
++#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
++#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
++#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
++#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
++#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
++#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
++#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
++#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
++#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
++#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
++#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
++#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
++#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
++#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
++#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
++#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
++#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
++#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
++#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
++#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
++#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
++#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
++#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
++#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
++#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
++#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
++#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
++#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
++#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
++#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
++#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
++#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
++#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
++#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
++#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
++#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
++#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
++#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
++#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
++#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
++#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
++#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
++#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
++#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
++#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
++#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
++#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
++#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
++#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
++#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
++#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
++#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
++#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
++#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
++#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
++#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
++#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
++#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
++#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
++#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
++#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
++#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
++#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
++#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
++#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
++#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
++#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
++#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
++#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
++#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
++#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
++#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
++#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
++#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
++#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
++#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
++#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
++#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
++#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
++#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
++#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
++#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
++#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
++#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
++#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
++#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
++#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
++#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
++#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
++#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
++#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
++#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
++#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
++#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
++#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
++#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
++#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
++#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
++#define MC_CG_CONFIG__INDEX__SHIFT 0x6
++#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
++#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
++#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
++#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x80
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x100
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x8
++#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
++#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
++#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
++#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x10000
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x20000
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x11
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
++#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
++#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
++#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
++#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
++#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
++#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
++#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
++#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
++#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
++#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
++#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
++#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
++#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
++#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
++#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
++#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_CITF_DAGB_DLY__CLI_MASK 0x1f0000
++#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
++#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
++#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_RD_GRP_EXT__TC0_MASK 0xf0
++#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
++#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_WR_GRP_EXT__TC0_MASK 0xf0
++#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
++#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
++#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
++#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
++#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
++#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
++#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
++#define MC_WR_TC0__ENABLE_MASK 0x1
++#define MC_WR_TC0__ENABLE__SHIFT 0x0
++#define MC_WR_TC0__PRESCALE_MASK 0x6
++#define MC_WR_TC0__PRESCALE__SHIFT 0x1
++#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC0__STALL_MODE_MASK 0x30
++#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC0__MAX_BURST_MASK 0x780
++#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_TC1__ENABLE_MASK 0x1
++#define MC_WR_TC1__ENABLE__SHIFT 0x0
++#define MC_WR_TC1__PRESCALE_MASK 0x6
++#define MC_WR_TC1__PRESCALE__SHIFT 0x1
++#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC1__STALL_MODE_MASK 0x30
++#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC1__MAX_BURST_MASK 0x780
++#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_RD_CB__ENABLE_MASK 0x1
++#define MC_RD_CB__ENABLE__SHIFT 0x0
++#define MC_RD_CB__PRESCALE_MASK 0x6
++#define MC_RD_CB__PRESCALE__SHIFT 0x1
++#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_CB__STALL_MODE_MASK 0x30
++#define MC_RD_CB__STALL_MODE__SHIFT 0x4
++#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_CB__MAX_BURST_MASK 0x780
++#define MC_RD_CB__MAX_BURST__SHIFT 0x7
++#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_DB__ENABLE_MASK 0x1
++#define MC_RD_DB__ENABLE__SHIFT 0x0
++#define MC_RD_DB__PRESCALE_MASK 0x6
++#define MC_RD_DB__PRESCALE__SHIFT 0x1
++#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_DB__STALL_MODE_MASK 0x30
++#define MC_RD_DB__STALL_MODE__SHIFT 0x4
++#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_DB__MAX_BURST_MASK 0x780
++#define MC_RD_DB__MAX_BURST__SHIFT 0x7
++#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC0__ENABLE_MASK 0x1
++#define MC_RD_TC0__ENABLE__SHIFT 0x0
++#define MC_RD_TC0__PRESCALE_MASK 0x6
++#define MC_RD_TC0__PRESCALE__SHIFT 0x1
++#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC0__STALL_MODE_MASK 0x30
++#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC0__MAX_BURST_MASK 0x780
++#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC1__ENABLE_MASK 0x1
++#define MC_RD_TC1__ENABLE__SHIFT 0x0
++#define MC_RD_TC1__PRESCALE_MASK 0x6
++#define MC_RD_TC1__PRESCALE__SHIFT 0x1
++#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC1__STALL_MODE_MASK 0x30
++#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC1__MAX_BURST_MASK 0x780
++#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_HUB__ENABLE_MASK 0x1
++#define MC_RD_HUB__ENABLE__SHIFT 0x0
++#define MC_RD_HUB__PRESCALE_MASK 0x6
++#define MC_RD_HUB__PRESCALE__SHIFT 0x1
++#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_HUB__STALL_MODE_MASK 0x30
++#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
++#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_HUB__MAX_BURST_MASK 0x780
++#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
++#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_CB__ENABLE_MASK 0x1
++#define MC_WR_CB__ENABLE__SHIFT 0x0
++#define MC_WR_CB__PRESCALE_MASK 0x6
++#define MC_WR_CB__PRESCALE__SHIFT 0x1
++#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_CB__STALL_MODE_MASK 0x30
++#define MC_WR_CB__STALL_MODE__SHIFT 0x4
++#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_CB__MAX_BURST_MASK 0x780
++#define MC_WR_CB__MAX_BURST__SHIFT 0x7
++#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_DB__ENABLE_MASK 0x1
++#define MC_WR_DB__ENABLE__SHIFT 0x0
++#define MC_WR_DB__PRESCALE_MASK 0x6
++#define MC_WR_DB__PRESCALE__SHIFT 0x1
++#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_DB__STALL_MODE_MASK 0x30
++#define MC_WR_DB__STALL_MODE__SHIFT 0x4
++#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_DB__MAX_BURST_MASK 0x780
++#define MC_WR_DB__MAX_BURST__SHIFT 0x7
++#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_HUB__ENABLE_MASK 0x1
++#define MC_WR_HUB__ENABLE__SHIFT 0x0
++#define MC_WR_HUB__PRESCALE_MASK 0x6
++#define MC_WR_HUB__PRESCALE__SHIFT 0x1
++#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_HUB__STALL_MODE_MASK 0x30
++#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
++#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_HUB__MAX_BURST_MASK 0x780
++#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
++#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
++#define MC_RD_GRP_LCL__CB0_MASK 0xf000
++#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
++#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
++#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
++#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
++#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
++#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
++#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
++#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
++#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
++#define MC_WR_GRP_LCL__CB0_MASK 0xf
++#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
++#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
++#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
++#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
++#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
++#define MC_WR_GRP_LCL__DB0_MASK 0xf000
++#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
++#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
++#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
++#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
++#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
++#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
++#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
++#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
++#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
++#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_DBG__SELECT0_MASK 0xf
++#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x0
++#define MC_HUB_MISC_DBG__SELECT1_MASK 0xf0
++#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x4
++#define MC_HUB_MISC_DBG__CTRL0_MASK 0x1f00
++#define MC_HUB_MISC_DBG__CTRL0__SHIFT 0x8
++#define MC_HUB_MISC_DBG__CTRL1_MASK 0x3e000
++#define MC_HUB_MISC_DBG__CTRL1__SHIFT 0xd
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
++#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
++#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
++#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
++#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
++#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
++#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
++#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
++#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
++#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
++#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
++#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
++#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
++#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x5
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x6
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x8
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x9
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x20
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x5
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x40
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x6
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x100
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x8
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x200
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x9
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x800
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xb
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x200
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x9
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc00
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xa
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x20000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x11
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x40000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x12
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x80000
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x13
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x100000
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x14
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
++#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
++#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
++#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
++#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
++#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
++#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
++#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_WDP_MGPU2__CID2_MASK 0xff
++#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x0
++#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_MGPU__STOR_MASK 0xff
++#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x0
++#define MC_HUB_WDP_MGPU__CID_MASK 0xff00
++#define MC_HUB_WDP_MGPU__CID__SHIFT 0x8
++#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x7f0000
++#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x10
++#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x800000
++#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x17
++#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x0
++#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
++#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x1f0000
++#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
++#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
++#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
++#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
++#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
++#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
++#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
++#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
++#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
++#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
++#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
++#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
++#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
++#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
++#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
++#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
++#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
++#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
++#define MC_SHARED_CHREMAP__CHAN0_MASK 0x7
++#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHREMAP__CHAN1_MASK 0x38
++#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x3
++#define MC_SHARED_CHREMAP__CHAN2_MASK 0x1c0
++#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x6
++#define MC_SHARED_CHREMAP__CHAN3_MASK 0xe00
++#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x9
++#define MC_SHARED_CHREMAP__CHAN4_MASK 0x7000
++#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0xc
++#define MC_SHARED_CHREMAP__CHAN5_MASK 0x38000
++#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0xf
++#define MC_SHARED_CHREMAP__CHAN6_MASK 0x1c0000
++#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x12
++#define MC_SHARED_CHREMAP__CHAN7_MASK 0xe00000
++#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x15
++#define MC_RD_GRP_GFX__CP_MASK 0xf
++#define MC_RD_GRP_GFX__CP__SHIFT 0x0
++#define MC_RD_GRP_GFX__SH_MASK 0xf0
++#define MC_RD_GRP_GFX__SH__SHIFT 0x4
++#define MC_RD_GRP_GFX__IA_MASK 0xf00
++#define MC_RD_GRP_GFX__IA__SHIFT 0x8
++#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
++#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
++#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
++#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
++#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
++#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
++#define MC_WR_GRP_GFX__CP_MASK 0xf
++#define MC_WR_GRP_GFX__CP__SHIFT 0x0
++#define MC_WR_GRP_GFX__SH_MASK 0xf0
++#define MC_WR_GRP_GFX__SH__SHIFT 0x4
++#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
++#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
++#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
++#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
++#define MC_WR_GRP_GFX__XDMA_MASK 0xf0000
++#define MC_WR_GRP_GFX__XDMA__SHIFT 0x10
++#define MC_WR_GRP_GFX__XDMAM_MASK 0xf00000
++#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x14
++#define MC_RD_GRP_SYS__RLC_MASK 0xf
++#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
++#define MC_RD_GRP_SYS__VMC_MASK 0xf0
++#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
++#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
++#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
++#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
++#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
++#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
++#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
++#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
++#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
++#define MC_RD_GRP_SYS__VCE_MASK 0xf000000
++#define MC_RD_GRP_SYS__VCE__SHIFT 0x18
++#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
++#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
++#define MC_WR_GRP_SYS__IH_MASK 0xf
++#define MC_WR_GRP_SYS__IH__SHIFT 0x0
++#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
++#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
++#define MC_WR_GRP_SYS__RLC_MASK 0xf00
++#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
++#define MC_WR_GRP_SYS__SAM_MASK 0xf000
++#define MC_WR_GRP_SYS__SAM__SHIFT 0xc
++#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
++#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
++#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
++#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
++#define MC_WR_GRP_SYS__VCE_MASK 0xf000000
++#define MC_WR_GRP_SYS__VCE__SHIFT 0x18
++#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
++#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
++#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_RD_GRP_OTH__HDP_MASK 0xf00
++#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
++#define MC_RD_GRP_OTH__SEM_MASK 0xf000
++#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
++#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
++#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
++#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
++#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
++#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
++#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
++#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
++#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
++#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_WR_GRP_OTH__HDP_MASK 0xf00
++#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
++#define MC_WR_GRP_OTH__SEM_MASK 0xf000
++#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
++#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
++#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
++#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
++#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
++#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
++#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
++#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
++#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
++#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
++#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
++#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
++#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
++#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
++#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
++#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
++#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
++#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
++#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
++#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
++#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
++#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
++#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
++#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
++#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
++#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
++#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
++#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
++#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
++#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
++#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
++#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
++#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
++#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
++#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
++#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
++#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
++#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
++#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
++#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
++#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
++#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
++#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
++#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
++#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
++#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
++#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
++#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
++#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
++#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
++#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
++#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
++#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
++#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
++#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
++#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
++#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
++#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
++#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
++#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
++#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
++#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
++#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
++#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
++#define MC_XPB_STICKY__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY__BITS__SHIFT 0x0
++#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
++#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
++#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
++#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
++#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
++#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
++#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
++#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
++#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
++#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
++#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
++#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
++#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
++#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
++#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
++#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
++#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
++#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
++#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
++#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
++#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
++#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
++#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
++#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
++#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
++#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
++#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
++#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
++#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
++#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
++#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00
++#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
++#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
++#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
++#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff
++#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0
++#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00
++#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8
++#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000
++#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10
++#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000
++#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18
++#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff
++#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0
++#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00
++#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8
++#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000
++#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10
++#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000
++#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18
++#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
++#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1
++#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
++#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
++#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
++#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
++#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
++#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
++#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
++#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
++#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
++#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
++#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
++#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
++#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
++#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
++#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
++#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
++#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
++#define ATC_ATS_STATUS__BUSY_MASK 0x1
++#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
++#define ATC_ATS_STATUS__CRASHED_MASK 0x2
++#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
++#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c
++#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2
++#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
++#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
++#define ATC_MISC_CG__ENABLE_MASK 0x40000
++#define ATC_MISC_CG__ENABLE__SHIFT 0x12
++#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
++#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
++#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
++#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
++#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
++#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
++#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x400
++#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0xa
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
++#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
++#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1RD_STATUS__BUSY_MASK 0x1
++#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_L1WR_STATUS__BUSY_MASK 0x1
++#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
++#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
++#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
++#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
++#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
++#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
++#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x7
++#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x0
++#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x38
++#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x3
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
++#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x1ffe0000
++#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x11
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
++#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
++#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
++#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
++#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0xfc0000
++#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
++#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000
++#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x18
++#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
++#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
++#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
++#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
++#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
++#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
++#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
++#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
++#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x3f
++#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
++#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xfc0
++#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x6
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff000
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xc
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x1000000
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x18
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x2000000
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x19
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x4000000
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1a
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0x3f0
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
++#define GMCON_DEBUG__GFX_STALL_MASK 0x1
++#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
++#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
++#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
++#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc
++#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2
++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
++#define VM_L2_STATUS__L2_BUSY_MASK 0x1
++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
++#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
++#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_DEBUG__FLAGS_MASK 0xffffffff
++#define VM_DEBUG__FLAGS__SHIFT 0x0
++#define VM_L2_CG__OFFDLY_MASK 0xfc0
++#define VM_L2_CG__OFFDLY__SHIFT 0x6
++#define VM_L2_CG__ENABLE_MASK 0x40000
++#define VM_L2_CG__ENABLE__SHIFT 0x12
++#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
++#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
++#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
++#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7
++#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0
++#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78
++#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3
++#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
++#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7
++#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
++#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
++#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7
++#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0
++#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78
++#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3
++#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
++#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7
++#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
++#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
++#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
++#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
++#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
++#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
++#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
++#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
++#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
++#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc
++#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7
++#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0
++#define MC_FUS_DRAM_MODE__GDDR5EN_MASK 0x8
++#define MC_FUS_DRAM_MODE__GDDR5EN__SHIFT 0x3
++#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x1ff0
++#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x4
++#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff
++#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0
++#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff
++#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0
++#define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE_MASK 0xfffff
++#define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE__SHIFT 0x0
++#define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP_MASK 0xfffff
++#define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP__SHIFT 0x0
++#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff
++#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0
++#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000
++#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d
++#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff
++#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00
++#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8
++#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000
++#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf
++#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000
++#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a
++#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3
++#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc
++#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2
++#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30
++#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4
++#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0
++#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6
++#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300
++#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8
++#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00
++#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa
++#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000
++#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc
++#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000
++#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe
++#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000
++#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10
++#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000
++#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12
++#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000
++#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14
++#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000
++#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16
++#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18
++#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2
++#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30
++#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4
++#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
++#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
++#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS_MASK 0x80000000
++#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS__SHIFT 0x1f
++#define CHUB_ATC_L1_STATUS__BUSY_MASK 0x1
++#define CHUB_ATC_L1_STATUS__BUSY__SHIFT 0x0
++#define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define CHUB_ATC_L1_STATUS__BAD_NEED_ATS_MASK 0x100
++#define CHUB_ATC_L1_STATUS__BAD_NEED_ATS__SHIFT 0x8
++
++#endif /* GMC_7_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0011-yocto-amd-drm-amdgpu-add-clearstate_defs-h.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0011-yocto-amd-drm-amdgpu-add-clearstate_defs-h.patch
new file mode 100644
index 00000000..10ca6ec7
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0011-yocto-amd-drm-amdgpu-add-clearstate_defs-h.patch
@@ -0,0 +1,15906 @@
+From e99fb5762c8ec7b1b6c56974527b0b0a8c762ba5 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:23:29 -0400
+Subject: drm/amdgpu: add GMC 7.1 register headers
+
+These are register headers for the GMC (Graphics Memory Controller)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
+new file mode 100644
+index 0000000..9da033d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
+@@ -0,0 +1,1464 @@
++/*
++ * GMC_7_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_7_1_D_H
++#define GMC_7_1_D_H
++
++#define mmMC_CONFIG                                                             0x800
++#define mmMC_ARB_AGE_CNTL                                                       0x9bf
++#define mmMC_ARB_RET_CREDITS2                                                   0x9c0
++#define mmMC_ARB_FED_CNTL                                                       0x9c1
++#define mmMC_ARB_GECC2_STATUS                                                   0x9c2
++#define mmMC_ARB_GECC2_MISC                                                     0x9c3
++#define mmMC_ARB_GECC2_DEBUG                                                    0x9c4
++#define mmMC_ARB_GECC2_DEBUG2                                                   0x9c5
++#define mmMC_ARB_PERF_CID                                                       0x9c6
++#define mmMC_ARB_GECC2                                                          0x9c9
++#define mmMC_ARB_GECC2_CLI                                                      0x9ca
++#define mmMC_ARB_ADDR_SWIZ0                                                     0x9cb
++#define mmMC_ARB_ADDR_SWIZ1                                                     0x9cc
++#define mmMC_ARB_MISC3                                                          0x9cd
++#define mmMC_ARB_WCDR_2                                                         0x9ce
++#define mmMC_ARB_RTT_DATA                                                       0x9cf
++#define mmMC_ARB_RTT_CNTL0                                                      0x9d0
++#define mmMC_ARB_RTT_CNTL1                                                      0x9d1
++#define mmMC_ARB_RTT_CNTL2                                                      0x9d2
++#define mmMC_ARB_RTT_DEBUG                                                      0x9d3
++#define mmMC_ARB_CAC_CNTL                                                       0x9d4
++#define mmMC_ARB_MISC2                                                          0x9d5
++#define mmMC_ARB_MISC                                                           0x9d6
++#define mmMC_ARB_BANKMAP                                                        0x9d7
++#define mmMC_ARB_RAMCFG                                                         0x9d8
++#define mmMC_ARB_POP                                                            0x9d9
++#define mmMC_ARB_MINCLKS                                                        0x9da
++#define mmMC_ARB_SQM_CNTL                                                       0x9db
++#define mmMC_ARB_ADDR_HASH                                                      0x9dc
++#define mmMC_ARB_DRAM_TIMING                                                    0x9dd
++#define mmMC_ARB_DRAM_TIMING2                                                   0x9de
++#define mmMC_ARB_WTM_CNTL_RD                                                    0x9df
++#define mmMC_ARB_WTM_CNTL_WR                                                    0x9e0
++#define mmMC_ARB_WTM_GRPWT_RD                                                   0x9e1
++#define mmMC_ARB_WTM_GRPWT_WR                                                   0x9e2
++#define mmMC_ARB_TM_CNTL_RD                                                     0x9e3
++#define mmMC_ARB_TM_CNTL_WR                                                     0x9e4
++#define mmMC_ARB_LAZY0_RD                                                       0x9e5
++#define mmMC_ARB_LAZY0_WR                                                       0x9e6
++#define mmMC_ARB_LAZY1_RD                                                       0x9e7
++#define mmMC_ARB_LAZY1_WR                                                       0x9e8
++#define mmMC_ARB_AGE_RD                                                         0x9e9
++#define mmMC_ARB_AGE_WR                                                         0x9ea
++#define mmMC_ARB_RFSH_CNTL                                                      0x9eb
++#define mmMC_ARB_RFSH_RATE                                                      0x9ec
++#define mmMC_ARB_PM_CNTL                                                        0x9ed
++#define mmMC_ARB_GDEC_RD_CNTL                                                   0x9ee
++#define mmMC_ARB_GDEC_WR_CNTL                                                   0x9ef
++#define mmMC_ARB_LM_RD                                                          0x9f0
++#define mmMC_ARB_LM_WR                                                          0x9f1
++#define mmMC_ARB_REMREQ                                                         0x9f2
++#define mmMC_ARB_REPLAY                                                         0x9f3
++#define mmMC_ARB_RET_CREDITS_RD                                                 0x9f4
++#define mmMC_ARB_RET_CREDITS_WR                                                 0x9f5
++#define mmMC_ARB_MAX_LAT_CID                                                    0x9f6
++#define mmMC_ARB_MAX_LAT_RSLT0                                                  0x9f7
++#define mmMC_ARB_MAX_LAT_RSLT1                                                  0x9f8
++#define mmMC_ARB_SSM                                                            0x9f9
++#define mmMC_ARB_CG                                                             0x9fa
++#define mmMC_ARB_WCDR                                                           0x9fb
++#define mmMC_ARB_DRAM_TIMING_1                                                  0x9fc
++#define mmMC_ARB_BUSY_STATUS                                                    0x9fd
++#define mmMC_ARB_DRAM_TIMING2_1                                                 0x9ff
++#define mmMC_ARB_BURST_TIME                                                     0xa02
++#define mmMC_CITF_XTRA_ENABLE                                                   0x96d
++#define mmCC_MC_MAX_CHANNEL                                                     0x96e
++#define mmMC_CG_CONFIG                                                          0x96f
++#define mmMC_CITF_CNTL                                                          0x970
++#define mmMC_CITF_CREDITS_VM                                                    0x971
++#define mmMC_CITF_CREDITS_ARB_RD                                                0x972
++#define mmMC_CITF_CREDITS_ARB_WR                                                0x973
++#define mmMC_CITF_DAGB_CNTL                                                     0x974
++#define mmMC_CITF_INT_CREDITS                                                   0x975
++#define mmMC_CITF_RET_MODE                                                      0x976
++#define mmMC_CITF_DAGB_DLY                                                      0x977
++#define mmMC_RD_GRP_EXT                                                         0x978
++#define mmMC_WR_GRP_EXT                                                         0x979
++#define mmMC_CITF_REMREQ                                                        0x97a
++#define mmMC_WR_TC0                                                             0x97b
++#define mmMC_WR_TC1                                                             0x97c
++#define mmMC_CITF_INT_CREDITS_WR                                                0x97d
++#define mmMC_CITF_WTM_RD_CNTL                                                   0x97f
++#define mmMC_CITF_WTM_WR_CNTL                                                   0x980
++#define mmMC_RD_CB                                                              0x981
++#define mmMC_RD_DB                                                              0x982
++#define mmMC_RD_TC0                                                             0x983
++#define mmMC_RD_TC1                                                             0x984
++#define mmMC_RD_HUB                                                             0x985
++#define mmMC_WR_CB                                                              0x986
++#define mmMC_WR_DB                                                              0x987
++#define mmMC_WR_HUB                                                             0x988
++#define mmMC_CITF_CREDITS_XBAR                                                  0x989
++#define mmMC_RD_GRP_LCL                                                         0x98a
++#define mmMC_WR_GRP_LCL                                                         0x98b
++#define mmMC_CITF_PERF_MON_CNTL2                                                0x98e
++#define mmMC_CITF_PERF_MON_RSLT2                                                0x991
++#define mmMC_CITF_MISC_RD_CG                                                    0x992
++#define mmMC_CITF_MISC_WR_CG                                                    0x993
++#define mmMC_CITF_MISC_VM_CG                                                    0x994
++#define mmMC_HUB_MISC_POWER                                                     0x82d
++#define mmMC_HUB_MISC_HUB_CG                                                    0x82e
++#define mmMC_HUB_MISC_VM_CG                                                     0x82f
++#define mmMC_HUB_MISC_SIP_CG                                                    0x830
++#define mmMC_HUB_MISC_STATUS                                                    0x832
++#define mmMC_HUB_MISC_OVERRIDE                                                  0x833
++#define mmMC_HUB_MISC_FRAMING                                                   0x834
++#define mmMC_HUB_WDP_CNTL                                                       0x835
++#define mmMC_HUB_WDP_ERR                                                        0x836
++#define mmMC_HUB_WDP_BP                                                         0x837
++#define mmMC_HUB_WDP_STATUS                                                     0x838
++#define mmMC_HUB_RDREQ_STATUS                                                   0x839
++#define mmMC_HUB_WRRET_STATUS                                                   0x83a
++#define mmMC_HUB_RDREQ_CNTL                                                     0x83b
++#define mmMC_HUB_WRRET_CNTL                                                     0x83c
++#define mmMC_HUB_RDREQ_WTM_CNTL                                                 0x83d
++#define mmMC_HUB_WDP_WTM_CNTL                                                   0x83e
++#define mmMC_HUB_WDP_CREDITS                                                    0x83f
++#define mmMC_HUB_WDP_CREDITS2                                                   0x840
++#define mmMC_HUB_WDP_GBL0                                                       0x841
++#define mmMC_HUB_WDP_GBL1                                                       0x842
++#define mmMC_HUB_RDREQ_CREDITS                                                  0x844
++#define mmMC_HUB_RDREQ_CREDITS2                                                 0x845
++#define mmMC_HUB_SHARED_DAGB_DLY                                                0x846
++#define mmMC_HUB_MISC_IDLE_STATUS                                               0x847
++#define mmMC_HUB_RDREQ_DMIF_LIMIT                                               0x848
++#define mmMC_HUB_RDREQ_ACPG_LIMIT                                               0x849
++#define mmMC_HUB_WDP_BYPASS_GBL0                                                0x84a
++#define mmMC_HUB_WDP_BYPASS_GBL1                                                0x84b
++#define mmMC_HUB_RDREQ_BYPASS_GBL0                                              0x84c
++#define mmMC_HUB_WDP_SH2                                                        0x84d
++#define mmMC_HUB_WDP_SH3                                                        0x84e
++#define mmMC_HUB_RDREQ_IA0                                                      0x84f
++#define mmMC_HUB_RDREQ_IA1                                                      0x850
++#define mmMC_HUB_RDREQ_MCDW                                                     0x851
++#define mmMC_HUB_RDREQ_MCDX                                                     0x852
++#define mmMC_HUB_RDREQ_MCDY                                                     0x853
++#define mmMC_HUB_RDREQ_MCDZ                                                     0x854
++#define mmMC_HUB_RDREQ_SIP                                                      0x855
++#define mmMC_HUB_RDREQ_GBL0                                                     0x856
++#define mmMC_HUB_RDREQ_GBL1                                                     0x857
++#define mmMC_HUB_RDREQ_SMU                                                      0x858
++#define mmMC_HUB_RDREQ_CPG                                                      0x859
++#define mmMC_HUB_RDREQ_SDMA0                                                    0x85a
++#define mmMC_HUB_RDREQ_HDP                                                      0x85b
++#define mmMC_HUB_RDREQ_SDMA1                                                    0x85c
++#define mmMC_HUB_RDREQ_RLC                                                      0x85d
++#define mmMC_HUB_RDREQ_SEM                                                      0x85e
++#define mmMC_HUB_RDREQ_VCE                                                      0x85f
++#define mmMC_HUB_RDREQ_UMC                                                      0x860
++#define mmMC_HUB_RDREQ_UVD                                                      0x861
++#define mmMC_HUB_RDREQ_IA                                                       0x862
++#define mmMC_HUB_RDREQ_DMIF                                                     0x863
++#define mmMC_HUB_RDREQ_MCIF                                                     0x864
++#define mmMC_HUB_RDREQ_VMC                                                      0x865
++#define mmMC_HUB_RDREQ_VCEU                                                     0x866
++#define mmMC_HUB_WDP_MCDW                                                       0x867
++#define mmMC_HUB_WDP_MCDX                                                       0x868
++#define mmMC_HUB_WDP_MCDY                                                       0x869
++#define mmMC_HUB_WDP_MCDZ                                                       0x86a
++#define mmMC_HUB_WDP_SIP                                                        0x86b
++#define mmMC_HUB_WDP_CPG                                                        0x86c
++#define mmMC_HUB_WDP_SDMA1                                                      0x86d
++#define mmMC_HUB_WDP_SH0                                                        0x86e
++#define mmMC_HUB_WDP_MCIF                                                       0x86f
++#define mmMC_HUB_WDP_VCE                                                        0x870
++#define mmMC_HUB_WDP_XDP                                                        0x871
++#define mmMC_HUB_WDP_IH                                                         0x872
++#define mmMC_HUB_WDP_RLC                                                        0x873
++#define mmMC_HUB_WDP_SEM                                                        0x874
++#define mmMC_HUB_WDP_SMU                                                        0x875
++#define mmMC_HUB_WDP_SH1                                                        0x876
++#define mmMC_HUB_WDP_UMC                                                        0x877
++#define mmMC_HUB_WDP_UVD                                                        0x878
++#define mmMC_HUB_WDP_HDP                                                        0x879
++#define mmMC_HUB_WDP_SDMA0                                                      0x87a
++#define mmMC_HUB_WRRET_MCDW                                                     0x87b
++#define mmMC_HUB_WRRET_MCDX                                                     0x87c
++#define mmMC_HUB_WRRET_MCDY                                                     0x87d
++#define mmMC_HUB_WRRET_MCDZ                                                     0x87e
++#define mmMC_HUB_WDP_VCEU                                                       0x87f
++#define mmMC_HUB_WDP_XDMAM                                                      0x880
++#define mmMC_HUB_WDP_XDMA                                                       0x881
++#define mmMC_HUB_RDREQ_XDMAM                                                    0x882
++#define mmMC_HUB_RDREQ_ACPG                                                     0x883
++#define mmMC_HUB_RDREQ_ACPO                                                     0x884
++#define mmMC_HUB_RDREQ_SAM                                                      0x885
++#define mmMC_HUB_WDP_ACPG                                                       0x886
++#define mmMC_HUB_WDP_ACPO                                                       0x887
++#define mmMC_HUB_WDP_SAM                                                        0x888
++#define mmMC_HUB_RDREQ_CPC                                                      0x889
++#define mmMC_HUB_RDREQ_CPF                                                      0x88a
++#define mmMC_HUB_WDP_CPC                                                        0x88b
++#define mmMC_HUB_WDP_CPF                                                        0x88c
++#define mmMC_HUB_RDREQ_ISP_SPM                                                  0xde0
++#define mmMC_HUB_RDREQ_ISP_MPM                                                  0xde1
++#define mmMC_HUB_RDREQ_ISP_CCPU                                                 0xde2
++#define mmMC_HUB_WDP_ISP_SPM                                                    0xde3
++#define mmMC_HUB_WDP_ISP_MPS                                                    0xde4
++#define mmMC_HUB_WDP_ISP_MPM                                                    0xde5
++#define mmMC_HUB_WDP_ISP_CCPU                                                   0xde6
++#define mmMC_HUB_RDREQ_MCDS                                                     0xde7
++#define mmMC_HUB_RDREQ_MCDT                                                     0xde8
++#define mmMC_HUB_RDREQ_MCDU                                                     0xde9
++#define mmMC_HUB_RDREQ_MCDV                                                     0xdea
++#define mmMC_HUB_WDP_MCDS                                                       0xdeb
++#define mmMC_HUB_WDP_MCDT                                                       0xdec
++#define mmMC_HUB_WDP_MCDU                                                       0xded
++#define mmMC_HUB_WDP_MCDV                                                       0xdee
++#define mmMC_HUB_WRRET_MCDS                                                     0xdef
++#define mmMC_HUB_WRRET_MCDT                                                     0xdf0
++#define mmMC_HUB_WRRET_MCDU                                                     0xdf1
++#define mmMC_HUB_WRRET_MCDV                                                     0xdf2
++#define mmMC_HUB_WDP_CREDITS_MCDW                                               0xdf3
++#define mmMC_HUB_WDP_CREDITS_MCDX                                               0xdf4
++#define mmMC_HUB_WDP_CREDITS_MCDY                                               0xdf5
++#define mmMC_HUB_WDP_CREDITS_MCDZ                                               0xdf6
++#define mmMC_HUB_WDP_CREDITS_MCDS                                               0xdf7
++#define mmMC_HUB_WDP_CREDITS_MCDT                                               0xdf8
++#define mmMC_HUB_WDP_CREDITS_MCDU                                               0xdf9
++#define mmMC_HUB_WDP_CREDITS_MCDV                                               0xdfa
++#define mmMC_HUB_WDP_BP2                                                        0xdfb
++#define mmMC_RPB_CONF                                                           0x94d
++#define mmMC_RPB_IF_CONF                                                        0x94e
++#define mmMC_RPB_DBG1                                                           0x94f
++#define mmMC_RPB_EFF_CNTL                                                       0x950
++#define mmMC_RPB_ARB_CNTL                                                       0x951
++#define mmMC_RPB_BIF_CNTL                                                       0x952
++#define mmMC_RPB_WR_SWITCH_CNTL                                                 0x953
++#define mmMC_RPB_WR_COMBINE_CNTL                                                0x954
++#define mmMC_RPB_RD_SWITCH_CNTL                                                 0x955
++#define mmMC_RPB_CID_QUEUE_WR                                                   0x956
++#define mmMC_RPB_CID_QUEUE_RD                                                   0x957
++#define mmMC_RPB_PERF_COUNTER_CNTL                                              0x958
++#define mmMC_RPB_PERF_COUNTER_STATUS                                            0x959
++#define mmMC_RPB_CID_QUEUE_EX                                                   0x95a
++#define mmMC_RPB_CID_QUEUE_EX_DATA                                              0x95b
++#define mmMC_RPB_TCI_CNTL                                                       0x95c
++#define mmMC_SHARED_CHMAP                                                       0x801
++#define mmMC_SHARED_CHREMAP                                                     0x802
++#define mmMC_RD_GRP_GFX                                                         0x803
++#define mmMC_WR_GRP_GFX                                                         0x804
++#define mmMC_RD_GRP_SYS                                                         0x805
++#define mmMC_WR_GRP_SYS                                                         0x806
++#define mmMC_RD_GRP_OTH                                                         0x807
++#define mmMC_WR_GRP_OTH                                                         0x808
++#define mmMC_VM_FB_LOCATION                                                     0x809
++#define mmMC_VM_AGP_TOP                                                         0x80a
++#define mmMC_VM_AGP_BOT                                                         0x80b
++#define mmMC_VM_AGP_BASE                                                        0x80c
++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR                                        0x80d
++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                       0x80e
++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR                                    0x80f
++#define mmMC_VM_DC_WRITE_CNTL                                                   0x810
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR                                  0x811
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR                                  0x812
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR                                  0x813
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR                                  0x814
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR                                 0x815
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR                                 0x816
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR                                 0x817
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR                                 0x818
++#define mmMC_VM_MX_L1_TLB_CNTL                                                  0x819
++#define mmMC_VM_FB_OFFSET                                                       0x81a
++#define mmMC_VM_STEERING                                                        0x81b
++#define mmMC_SHARED_CHREMAP2                                                    0x81c
++#define mmMC_CONFIG_MCD                                                         0x828
++#define mmMC_CG_CONFIG_MCD                                                      0x829
++#define mmMC_MEM_POWER_LS                                                       0x82a
++#define mmMC_SHARED_BLACKOUT_CNTL                                               0x82b
++#define mmMC_VM_MB_L1_TLB0_DEBUG                                                0x891
++#define mmMC_VM_MB_L1_TLB2_DEBUG                                                0x893
++#define mmMC_VM_MB_L1_TLB0_STATUS                                               0x895
++#define mmMC_VM_MB_L1_TLB1_STATUS                                               0x896
++#define mmMC_VM_MB_L1_TLB2_STATUS                                               0x897
++#define mmMC_VM_MB_L2ARBITER_L2_CREDITS                                         0x8a1
++#define mmMC_VM_MB_L1_TLB3_DEBUG                                                0x8a5
++#define mmMC_VM_MB_L1_TLB3_STATUS                                               0x8a6
++#define mmMC_VM_MD_L1_TLB0_DEBUG                                                0x998
++#define mmMC_VM_MD_L1_TLB1_DEBUG                                                0x999
++#define mmMC_VM_MD_L1_TLB2_DEBUG                                                0x99a
++#define mmMC_VM_MD_L1_TLB0_STATUS                                               0x99b
++#define mmMC_VM_MD_L1_TLB1_STATUS                                               0x99c
++#define mmMC_VM_MD_L1_TLB2_STATUS                                               0x99d
++#define mmMC_VM_MD_L2ARBITER_L2_CREDITS                                         0x9a4
++#define mmMC_VM_MD_L1_TLB3_DEBUG                                                0x9a7
++#define mmMC_VM_MD_L1_TLB3_STATUS                                               0x9a8
++#define mmMC_XPB_RTR_SRC_APRTR0                                                 0x8cd
++#define mmMC_XPB_RTR_SRC_APRTR1                                                 0x8ce
++#define mmMC_XPB_RTR_SRC_APRTR2                                                 0x8cf
++#define mmMC_XPB_RTR_SRC_APRTR3                                                 0x8d0
++#define mmMC_XPB_RTR_SRC_APRTR4                                                 0x8d1
++#define mmMC_XPB_RTR_SRC_APRTR5                                                 0x8d2
++#define mmMC_XPB_RTR_SRC_APRTR6                                                 0x8d3
++#define mmMC_XPB_RTR_SRC_APRTR7                                                 0x8d4
++#define mmMC_XPB_RTR_SRC_APRTR8                                                 0x8d5
++#define mmMC_XPB_RTR_SRC_APRTR9                                                 0x8d6
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR0                                            0x8d7
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR1                                            0x8d8
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR2                                            0x8d9
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR3                                            0x8da
++#define mmMC_XPB_RTR_DEST_MAP0                                                  0x8db
++#define mmMC_XPB_RTR_DEST_MAP1                                                  0x8dc
++#define mmMC_XPB_RTR_DEST_MAP2                                                  0x8dd
++#define mmMC_XPB_RTR_DEST_MAP3                                                  0x8de
++#define mmMC_XPB_RTR_DEST_MAP4                                                  0x8df
++#define mmMC_XPB_RTR_DEST_MAP5                                                  0x8e0
++#define mmMC_XPB_RTR_DEST_MAP6                                                  0x8e1
++#define mmMC_XPB_RTR_DEST_MAP7                                                  0x8e2
++#define mmMC_XPB_RTR_DEST_MAP8                                                  0x8e3
++#define mmMC_XPB_RTR_DEST_MAP9                                                  0x8e4
++#define mmMC_XPB_XDMA_RTR_DEST_MAP0                                             0x8e5
++#define mmMC_XPB_XDMA_RTR_DEST_MAP1                                             0x8e6
++#define mmMC_XPB_XDMA_RTR_DEST_MAP2                                             0x8e7
++#define mmMC_XPB_XDMA_RTR_DEST_MAP3                                             0x8e8
++#define mmMC_XPB_CLG_CFG0                                                       0x8e9
++#define mmMC_XPB_CLG_CFG1                                                       0x8ea
++#define mmMC_XPB_CLG_CFG2                                                       0x8eb
++#define mmMC_XPB_CLG_CFG3                                                       0x8ec
++#define mmMC_XPB_CLG_CFG4                                                       0x8ed
++#define mmMC_XPB_CLG_CFG5                                                       0x8ee
++#define mmMC_XPB_CLG_CFG6                                                       0x8ef
++#define mmMC_XPB_CLG_CFG7                                                       0x8f0
++#define mmMC_XPB_CLG_CFG8                                                       0x8f1
++#define mmMC_XPB_CLG_CFG9                                                       0x8f2
++#define mmMC_XPB_CLG_CFG10                                                      0x8f3
++#define mmMC_XPB_CLG_CFG11                                                      0x8f4
++#define mmMC_XPB_CLG_CFG12                                                      0x8f5
++#define mmMC_XPB_CLG_CFG13                                                      0x8f6
++#define mmMC_XPB_CLG_CFG14                                                      0x8f7
++#define mmMC_XPB_CLG_CFG15                                                      0x8f8
++#define mmMC_XPB_CLG_CFG16                                                      0x8f9
++#define mmMC_XPB_CLG_CFG17                                                      0x8fa
++#define mmMC_XPB_CLG_CFG18                                                      0x8fb
++#define mmMC_XPB_CLG_CFG19                                                      0x8fc
++#define mmMC_XPB_CLG_EXTRA                                                      0x8fd
++#define mmMC_XPB_LB_ADDR                                                        0x8fe
++#define mmMC_XPB_UNC_THRESH_HST                                                 0x8ff
++#define mmMC_XPB_UNC_THRESH_SID                                                 0x900
++#define mmMC_XPB_WCB_STS                                                        0x901
++#define mmMC_XPB_WCB_CFG                                                        0x902
++#define mmMC_XPB_P2P_BAR_CFG                                                    0x903
++#define mmMC_XPB_P2P_BAR0                                                       0x904
++#define mmMC_XPB_P2P_BAR1                                                       0x905
++#define mmMC_XPB_P2P_BAR2                                                       0x906
++#define mmMC_XPB_P2P_BAR3                                                       0x907
++#define mmMC_XPB_P2P_BAR4                                                       0x908
++#define mmMC_XPB_P2P_BAR5                                                       0x909
++#define mmMC_XPB_P2P_BAR6                                                       0x90a
++#define mmMC_XPB_P2P_BAR7                                                       0x90b
++#define mmMC_XPB_P2P_BAR_SETUP                                                  0x90c
++#define mmMC_XPB_P2P_BAR_DEBUG                                                  0x90d
++#define mmMC_XPB_P2P_BAR_DELTA_ABOVE                                            0x90e
++#define mmMC_XPB_P2P_BAR_DELTA_BELOW                                            0x90f
++#define mmMC_XPB_PEER_SYS_BAR0                                                  0x910
++#define mmMC_XPB_PEER_SYS_BAR1                                                  0x911
++#define mmMC_XPB_PEER_SYS_BAR2                                                  0x912
++#define mmMC_XPB_PEER_SYS_BAR3                                                  0x913
++#define mmMC_XPB_PEER_SYS_BAR4                                                  0x914
++#define mmMC_XPB_PEER_SYS_BAR5                                                  0x915
++#define mmMC_XPB_PEER_SYS_BAR6                                                  0x916
++#define mmMC_XPB_PEER_SYS_BAR7                                                  0x917
++#define mmMC_XPB_PEER_SYS_BAR8                                                  0x918
++#define mmMC_XPB_PEER_SYS_BAR9                                                  0x919
++#define mmMC_XPB_XDMA_PEER_SYS_BAR0                                             0x91a
++#define mmMC_XPB_XDMA_PEER_SYS_BAR1                                             0x91b
++#define mmMC_XPB_XDMA_PEER_SYS_BAR2                                             0x91c
++#define mmMC_XPB_XDMA_PEER_SYS_BAR3                                             0x91d
++#define mmMC_XPB_CLK_GAT                                                        0x91e
++#define mmMC_XPB_INTF_CFG                                                       0x91f
++#define mmMC_XPB_INTF_STS                                                       0x920
++#define mmMC_XPB_PIPE_STS                                                       0x921
++#define mmMC_XPB_SUB_CTRL                                                       0x922
++#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB                                       0x923
++#define mmMC_XPB_PERF_KNOBS                                                     0x924
++#define mmMC_XPB_STICKY                                                         0x925
++#define mmMC_XPB_STICKY_W1C                                                     0x926
++#define mmMC_XPB_MISC_CFG                                                       0x927
++#define mmMC_XPB_CLG_CFG20                                                      0x928
++#define mmMC_XPB_CLG_CFG21                                                      0x929
++#define mmMC_XPB_CLG_CFG22                                                      0x92a
++#define mmMC_XPB_CLG_CFG23                                                      0x92b
++#define mmMC_XPB_CLG_CFG24                                                      0x92c
++#define mmMC_XPB_CLG_CFG25                                                      0x92d
++#define mmMC_XPB_CLG_CFG26                                                      0x92e
++#define mmMC_XPB_CLG_CFG27                                                      0x92f
++#define mmMC_XPB_CLG_CFG28                                                      0x930
++#define mmMC_XPB_CLG_CFG29                                                      0x931
++#define mmMC_XPB_CLG_CFG30                                                      0x932
++#define mmMC_XPB_CLG_CFG31                                                      0x933
++#define mmMC_XPB_INTF_CFG2                                                      0x934
++#define mmMC_XPB_CLG_EXTRA_RD                                                   0x935
++#define mmMC_XPB_CLG_CFG32                                                      0x936
++#define mmMC_XPB_CLG_CFG33                                                      0x937
++#define mmMC_XPB_CLG_CFG34                                                      0x938
++#define mmMC_XPB_CLG_CFG35                                                      0x939
++#define mmMC_XPB_CLG_CFG36                                                      0x93a
++#define mmMC_XBAR_ADDR_DEC                                                      0xc80
++#define mmMC_XBAR_REMOTE                                                        0xc81
++#define mmMC_XBAR_WRREQ_CREDIT                                                  0xc82
++#define mmMC_XBAR_RDREQ_CREDIT                                                  0xc83
++#define mmMC_XBAR_RDREQ_PRI_CREDIT                                              0xc84
++#define mmMC_XBAR_WRRET_CREDIT1                                                 0xc85
++#define mmMC_XBAR_WRRET_CREDIT2                                                 0xc86
++#define mmMC_XBAR_RDRET_CREDIT1                                                 0xc87
++#define mmMC_XBAR_RDRET_CREDIT2                                                 0xc88
++#define mmMC_XBAR_RDRET_PRI_CREDIT1                                             0xc89
++#define mmMC_XBAR_RDRET_PRI_CREDIT2                                             0xc8a
++#define mmMC_XBAR_CHTRIREMAP                                                    0xc8b
++#define mmMC_XBAR_TWOCHAN                                                       0xc8c
++#define mmMC_XBAR_ARB                                                           0xc8d
++#define mmMC_XBAR_ARB_MAX_BURST                                                 0xc8e
++#define mmMC_XBAR_PERF_MON_CNTL0                                                0xc8f
++#define mmMC_XBAR_PERF_MON_CNTL1                                                0xc90
++#define mmMC_XBAR_PERF_MON_CNTL2                                                0xc91
++#define mmMC_XBAR_PERF_MON_RSLT0                                                0xc92
++#define mmMC_XBAR_PERF_MON_RSLT1                                                0xc93
++#define mmMC_XBAR_PERF_MON_RSLT2                                                0xc94
++#define mmMC_XBAR_PERF_MON_RSLT3                                                0xc95
++#define mmMC_XBAR_PERF_MON_MAX_THSH                                             0xc96
++#define mmMC_XBAR_SPARE0                                                        0xc97
++#define mmMC_XBAR_SPARE1                                                        0xc98
++#define mmMC_CITF_PERFCOUNTER_LO                                                0x7a0
++#define mmMC_HUB_PERFCOUNTER_LO                                                 0x7a1
++#define mmMC_RPB_PERFCOUNTER_LO                                                 0x7a2
++#define mmMC_MCBVM_PERFCOUNTER_LO                                               0x7a3
++#define mmMC_MCDVM_PERFCOUNTER_LO                                               0x7a4
++#define mmMC_VM_L2_PERFCOUNTER_LO                                               0x7a5
++#define mmMC_ARB_PERFCOUNTER_LO                                                 0x7a6
++#define mmATC_PERFCOUNTER_LO                                                    0x7a7
++#define mmMC_CITF_PERFCOUNTER_HI                                                0x7a8
++#define mmMC_HUB_PERFCOUNTER_HI                                                 0x7a9
++#define mmMC_MCBVM_PERFCOUNTER_HI                                               0x7aa
++#define mmMC_MCDVM_PERFCOUNTER_HI                                               0x7ab
++#define mmMC_RPB_PERFCOUNTER_HI                                                 0x7ac
++#define mmMC_VM_L2_PERFCOUNTER_HI                                               0x7ad
++#define mmMC_ARB_PERFCOUNTER_HI                                                 0x7ae
++#define mmATC_PERFCOUNTER_HI                                                    0x7af
++#define mmMC_CITF_PERFCOUNTER0_CFG                                              0x7b0
++#define mmMC_CITF_PERFCOUNTER1_CFG                                              0x7b1
++#define mmMC_CITF_PERFCOUNTER2_CFG                                              0x7b2
++#define mmMC_CITF_PERFCOUNTER3_CFG                                              0x7b3
++#define mmMC_HUB_PERFCOUNTER0_CFG                                               0x7b4
++#define mmMC_HUB_PERFCOUNTER1_CFG                                               0x7b5
++#define mmMC_HUB_PERFCOUNTER2_CFG                                               0x7b6
++#define mmMC_HUB_PERFCOUNTER3_CFG                                               0x7b7
++#define mmMC_RPB_PERFCOUNTER0_CFG                                               0x7b8
++#define mmMC_RPB_PERFCOUNTER1_CFG                                               0x7b9
++#define mmMC_RPB_PERFCOUNTER2_CFG                                               0x7ba
++#define mmMC_RPB_PERFCOUNTER3_CFG                                               0x7bb
++#define mmMC_ARB_PERFCOUNTER0_CFG                                               0x7bc
++#define mmMC_ARB_PERFCOUNTER1_CFG                                               0x7bd
++#define mmMC_ARB_PERFCOUNTER2_CFG                                               0x7be
++#define mmMC_ARB_PERFCOUNTER3_CFG                                               0x7bf
++#define mmMC_MCBVM_PERFCOUNTER0_CFG                                             0x7c0
++#define mmMC_MCBVM_PERFCOUNTER1_CFG                                             0x7c1
++#define mmMC_MCBVM_PERFCOUNTER2_CFG                                             0x7c2
++#define mmMC_MCBVM_PERFCOUNTER3_CFG                                             0x7c3
++#define mmMC_MCDVM_PERFCOUNTER0_CFG                                             0x7c4
++#define mmMC_MCDVM_PERFCOUNTER1_CFG                                             0x7c5
++#define mmMC_MCDVM_PERFCOUNTER2_CFG                                             0x7c6
++#define mmMC_MCDVM_PERFCOUNTER3_CFG                                             0x7c7
++#define mmATC_PERFCOUNTER0_CFG                                                  0x7c8
++#define mmATC_PERFCOUNTER1_CFG                                                  0x7c9
++#define mmATC_PERFCOUNTER2_CFG                                                  0x7ca
++#define mmATC_PERFCOUNTER3_CFG                                                  0x7cb
++#define mmMC_VM_L2_PERFCOUNTER0_CFG                                             0x7cc
++#define mmMC_VM_L2_PERFCOUNTER1_CFG                                             0x7cd
++#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL                                         0x7ce
++#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL                                          0x7cf
++#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL                                          0x7d0
++#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL                                        0x7d1
++#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL                                        0x7d2
++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                        0x7d3
++#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL                                          0x7d4
++#define mmATC_PERFCOUNTER_RSLT_CNTL                                             0x7d5
++#define mmCHUB_ATC_PERFCOUNTER_LO                                               0x7d6
++#define mmCHUB_ATC_PERFCOUNTER_HI                                               0x7d7
++#define mmCHUB_ATC_PERFCOUNTER0_CFG                                             0x7d8
++#define mmCHUB_ATC_PERFCOUNTER1_CFG                                             0x7d9
++#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL                                        0x7da
++#define mmMC_ARB_PERF_MON_CNTL0_ECC                                             0x7db
++#define mmATC_VM_APERTURE0_LOW_ADDR                                             0xcc0
++#define mmATC_VM_APERTURE1_LOW_ADDR                                             0xcc1
++#define mmATC_VM_APERTURE0_HIGH_ADDR                                            0xcc2
++#define mmATC_VM_APERTURE1_HIGH_ADDR                                            0xcc3
++#define mmATC_VM_APERTURE0_CNTL                                                 0xcc4
++#define mmATC_VM_APERTURE1_CNTL                                                 0xcc5
++#define mmATC_VM_APERTURE0_CNTL2                                                0xcc6
++#define mmATC_VM_APERTURE1_CNTL2                                                0xcc7
++#define mmATC_ATS_CNTL                                                          0xcc9
++#define mmATC_ATS_DEBUG                                                         0xcca
++#define mmATC_ATS_FAULT_DEBUG                                                   0xccb
++#define mmATC_ATS_STATUS                                                        0xccc
++#define mmATC_ATS_FAULT_CNTL                                                    0xccd
++#define mmATC_ATS_FAULT_STATUS_INFO                                             0xcce
++#define mmATC_ATS_FAULT_STATUS_ADDR                                             0xccf
++#define mmATC_ATS_DEFAULT_PAGE_LOW                                              0xcd0
++#define mmATC_ATS_DEFAULT_PAGE_CNTL                                             0xcd1
++#define mmATC_MISC_CG                                                           0xcd4
++#define mmATC_L2_CNTL                                                           0xcd5
++#define mmATC_L2_CNTL2                                                          0xcd6
++#define mmATC_L2_DEBUG                                                          0xcd7
++#define mmATC_L2_DEBUG2                                                         0xcd8
++#define mmATC_L1_CNTL                                                           0xcdc
++#define mmATC_L1_ADDRESS_OFFSET                                                 0xcdd
++#define mmATC_L1RD_DEBUG_TLB                                                    0xcde
++#define mmATC_L1WR_DEBUG_TLB                                                    0xcdf
++#define mmATC_L1RD_STATUS                                                       0xce0
++#define mmATC_L1WR_STATUS                                                       0xce1
++#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS                                  0xce6
++#define mmATC_VMID0_PASID_MAPPING                                               0xce7
++#define mmATC_VMID1_PASID_MAPPING                                               0xce8
++#define mmATC_VMID2_PASID_MAPPING                                               0xce9
++#define mmATC_VMID3_PASID_MAPPING                                               0xcea
++#define mmATC_VMID4_PASID_MAPPING                                               0xceb
++#define mmATC_VMID5_PASID_MAPPING                                               0xcec
++#define mmATC_VMID6_PASID_MAPPING                                               0xced
++#define mmATC_VMID7_PASID_MAPPING                                               0xcee
++#define mmATC_VMID8_PASID_MAPPING                                               0xcef
++#define mmATC_VMID9_PASID_MAPPING                                               0xcf0
++#define mmATC_VMID10_PASID_MAPPING                                              0xcf1
++#define mmATC_VMID11_PASID_MAPPING                                              0xcf2
++#define mmATC_VMID12_PASID_MAPPING                                              0xcf3
++#define mmATC_VMID13_PASID_MAPPING                                              0xcf4
++#define mmATC_VMID14_PASID_MAPPING                                              0xcf5
++#define mmATC_VMID15_PASID_MAPPING                                              0xcf6
++#define mmGMCON_RENG_RAM_INDEX                                                  0xd40
++#define mmGMCON_RENG_RAM_DATA                                                   0xd41
++#define mmGMCON_RENG_EXECUTE                                                    0xd42
++#define mmGMCON_MISC                                                            0xd43
++#define mmGMCON_MISC2                                                           0xd44
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0                                     0xd45
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1                                     0xd46
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2                                     0xd47
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0                                  0xd48
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1                                  0xd49
++#define mmGMCON_PERF_MON_CNTL0                                                  0xd4a
++#define mmGMCON_PERF_MON_CNTL1                                                  0xd4b
++#define mmGMCON_PERF_MON_RSLT0                                                  0xd4c
++#define mmGMCON_PERF_MON_RSLT1                                                  0xd4d
++#define mmGMCON_PGFSM_CONFIG                                                    0xd4e
++#define mmGMCON_PGFSM_WRITE                                                     0xd4f
++#define mmGMCON_PGFSM_READ                                                      0xd50
++#define mmGMCON_MISC3                                                           0xd51
++#define mmGMCON_MASK                                                            0xd52
++#define mmGMCON_LPT_TARGET                                                      0xd53
++#define mmGMCON_DEBUG                                                           0xd5f
++#define mmVM_L2_CNTL                                                            0x500
++#define mmVM_L2_CNTL2                                                           0x501
++#define mmVM_L2_CNTL3                                                           0x502
++#define mmVM_L2_STATUS                                                          0x503
++#define mmVM_CONTEXT0_CNTL                                                      0x504
++#define mmVM_CONTEXT1_CNTL                                                      0x505
++#define mmVM_DUMMY_PAGE_FAULT_CNTL                                              0x506
++#define mmVM_DUMMY_PAGE_FAULT_ADDR                                              0x507
++#define mmVM_CONTEXT0_CNTL2                                                     0x50c
++#define mmVM_CONTEXT1_CNTL2                                                     0x50d
++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR                                      0x50e
++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR                                      0x50f
++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR                                     0x510
++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR                                     0x511
++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR                                     0x512
++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR                                     0x513
++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR                                     0x514
++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR                                     0x515
++#define mmVM_INVALIDATE_REQUEST                                                 0x51e
++#define mmVM_INVALIDATE_RESPONSE                                                0x51f
++#define mmVM_PRT_APERTURE0_LOW_ADDR                                             0x52c
++#define mmVM_PRT_APERTURE1_LOW_ADDR                                             0x52d
++#define mmVM_PRT_APERTURE2_LOW_ADDR                                             0x52e
++#define mmVM_PRT_APERTURE3_LOW_ADDR                                             0x52f
++#define mmVM_PRT_APERTURE0_HIGH_ADDR                                            0x530
++#define mmVM_PRT_APERTURE1_HIGH_ADDR                                            0x531
++#define mmVM_PRT_APERTURE2_HIGH_ADDR                                            0x532
++#define mmVM_PRT_APERTURE3_HIGH_ADDR                                            0x533
++#define mmVM_PRT_CNTL                                                           0x534
++#define mmVM_CONTEXTS_DISABLE                                                   0x535
++#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS                                   0x536
++#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS                                   0x537
++#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT                                 0x538
++#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT                                 0x539
++#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR                                     0x53e
++#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR                                     0x53f
++#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR                             0x546
++#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR                             0x547
++#define mmVM_FAULT_CLIENT_ID                                                    0x54e
++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR                                      0x54f
++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR                                      0x550
++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR                                      0x551
++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR                                      0x552
++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR                                      0x553
++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR                                      0x554
++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR                                      0x555
++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR                                      0x556
++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR                                     0x557
++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR                                     0x558
++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR                                       0x55f
++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR                                       0x560
++#define mmVM_DEBUG                                                              0x56f
++#define mmVM_L2_CG                                                              0x570
++#define mmVM_L2_BANK_SELECT_MASKA                                               0x572
++#define mmVM_L2_BANK_SELECT_MASKB                                               0x573
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR                             0x575
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR                            0x576
++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET                                0x577
++#define mmMC_SEQ_CNTL                                                           0xa25
++#define mmMC_SEQ_CNTL_2                                                         0xad4
++#define mmMC_SEQ_DRAM                                                           0xa26
++#define mmMC_SEQ_DRAM_2                                                         0xa27
++#define mmMC_SEQ_RAS_TIMING                                                     0xa28
++#define mmMC_SEQ_CAS_TIMING                                                     0xa29
++#define mmMC_SEQ_MISC_TIMING                                                    0xa2a
++#define mmMC_SEQ_MISC_TIMING2                                                   0xa2b
++#define mmMC_SEQ_PMG_TIMING                                                     0xa2c
++#define mmMC_SEQ_RD_CTL_D0                                                      0xa2d
++#define mmMC_SEQ_RD_CTL_D1                                                      0xa2e
++#define mmMC_SEQ_WR_CTL_D0                                                      0xa2f
++#define mmMC_SEQ_WR_CTL_D1                                                      0xa30
++#define mmMC_SEQ_WR_CTL_2                                                       0xad5
++#define mmMC_SEQ_CMD                                                            0xa31
++#define mmMC_PMG_CMD_EMRS                                                       0xa83
++#define mmMC_PMG_CMD_MRS                                                        0xaab
++#define mmMC_PMG_CMD_MRS1                                                       0xad1
++#define mmMC_PMG_CMD_MRS2                                                       0xad7
++#define mmMC_PMG_CFG                                                            0xa84
++#define mmMC_PMG_AUTO_CMD                                                       0xa34
++#define mmMC_PMG_AUTO_CFG                                                       0xa35
++#define mmMC_IMP_CNTL                                                           0xa36
++#define mmMC_IMP_DEBUG                                                          0xa37
++#define mmMC_IMP_STATUS                                                         0xa38
++#define mmMC_IMP_DQ_STATUS                                                      0xabc
++#define mmMC_SEQ_WCDR_CTRL                                                      0xa39
++#define mmMC_SEQ_TRAIN_WAKEUP_CNTL                                              0xa3a
++#define mmMC_SEQ_TRAIN_EDC_THRESHOLD                                            0xa3b
++#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2                                           0xafe
++#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3                                           0xaff
++#define mmMC_SEQ_TRAIN_WAKEUP_EDGE                                              0xa3c
++#define mmMC_SEQ_TRAIN_WAKEUP_MASK                                              0xa3d
++#define mmMC_SEQ_TRAIN_CAPTURE                                                  0xa3e
++#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR                                             0xa3f
++#define mmMC_SEQ_TRAIN_TIMING                                                   0xa40
++#define mmMC_TRAIN_EDCCDR_R_D0                                                  0xa41
++#define mmMC_TRAIN_EDCCDR_R_D1                                                  0xa42
++#define mmMC_TRAIN_PRBSERR_0_D0                                                 0xa43
++#define mmMC_TRAIN_PRBSERR_1_D0                                                 0xa44
++#define mmMC_TRAIN_PRBSERR_2_D0                                                 0xafb
++#define mmMC_TRAIN_EDC_STATUS_D0                                                0xa45
++#define mmMC_TRAIN_PRBSERR_0_D1                                                 0xa46
++#define mmMC_TRAIN_PRBSERR_1_D1                                                 0xa47
++#define mmMC_TRAIN_PRBSERR_2_D1                                                 0xafc
++#define mmMC_TRAIN_EDC_STATUS_D1                                                0xa48
++#define mmMC_IO_TXCNTL_DPHY0_D0                                                 0xa49
++#define mmMC_IO_TXCNTL_DPHY1_D0                                                 0xa4a
++#define mmMC_IO_TXCNTL_APHY_D0                                                  0xa4b
++#define mmMC_IO_RXCNTL_DPHY0_D0                                                 0xa4c
++#define mmMC_IO_RXCNTL1_DPHY0_D0                                                0xadf
++#define mmMC_IO_RXCNTL_DPHY1_D0                                                 0xa4d
++#define mmMC_IO_RXCNTL1_DPHY1_D0                                                0xae0
++#define mmMC_IO_DPHY_STR_CNTL_D0                                                0xa4e
++#define mmMC_IO_APHY_STR_CNTL_D0                                                0xa97
++#define mmMC_IO_TXCNTL_DPHY0_D1                                                 0xa4f
++#define mmMC_IO_TXCNTL_DPHY1_D1                                                 0xa50
++#define mmMC_IO_TXCNTL_APHY_D1                                                  0xa51
++#define mmMC_IO_RXCNTL_DPHY0_D1                                                 0xa52
++#define mmMC_IO_RXCNTL1_DPHY0_D1                                                0xae1
++#define mmMC_IO_RXCNTL_DPHY1_D1                                                 0xa53
++#define mmMC_IO_RXCNTL1_DPHY1_D1                                                0xae2
++#define mmMC_IO_DPHY_STR_CNTL_D1                                                0xa54
++#define mmMC_IO_APHY_STR_CNTL_D1                                                0xa98
++#define mmMC_IO_CDRCNTL_D0                                                      0xa55
++#define mmMC_IO_CDRCNTL1_D0                                                     0xadd
++#define mmMC_IO_CDRCNTL2_D0                                                     0xae4
++#define mmMC_IO_CDRCNTL_D1                                                      0xa56
++#define mmMC_IO_CDRCNTL1_D1                                                     0xade
++#define mmMC_IO_CDRCNTL2_D1                                                     0xae5
++#define mmMC_SEQ_FIFO_CTL                                                       0xa57
++#define mmMC_SEQ_TXFRAMING_BYTE0_D0                                             0xa58
++#define mmMC_SEQ_TXFRAMING_BYTE1_D0                                             0xa59
++#define mmMC_SEQ_TXFRAMING_BYTE2_D0                                             0xa5a
++#define mmMC_SEQ_TXFRAMING_BYTE3_D0                                             0xa5b
++#define mmMC_SEQ_TXFRAMING_DBI_D0                                               0xa5c
++#define mmMC_SEQ_TXFRAMING_EDC_D0                                               0xa5d
++#define mmMC_SEQ_TXFRAMING_FCK_D0                                               0xa5e
++#define mmMC_SEQ_TXFRAMING_BYTE0_D1                                             0xa60
++#define mmMC_SEQ_TXFRAMING_BYTE1_D1                                             0xa61
++#define mmMC_SEQ_TXFRAMING_BYTE2_D1                                             0xa62
++#define mmMC_SEQ_TXFRAMING_BYTE3_D1                                             0xa63
++#define mmMC_SEQ_TXFRAMING_DBI_D1                                               0xa64
++#define mmMC_SEQ_TXFRAMING_EDC_D1                                               0xa65
++#define mmMC_SEQ_TXFRAMING_FCK_D1                                               0xa66
++#define mmMC_SEQ_RXFRAMING_BYTE0_D0                                             0xa67
++#define mmMC_SEQ_RXFRAMING_BYTE1_D0                                             0xa68
++#define mmMC_SEQ_RXFRAMING_BYTE2_D0                                             0xa69
++#define mmMC_SEQ_RXFRAMING_BYTE3_D0                                             0xa6a
++#define mmMC_SEQ_RXFRAMING_DBI_D0                                               0xa6b
++#define mmMC_SEQ_RXFRAMING_EDC_D0                                               0xa6c
++#define mmMC_SEQ_RXFRAMING_BYTE0_D1                                             0xa6d
++#define mmMC_SEQ_RXFRAMING_BYTE1_D1                                             0xa6e
++#define mmMC_SEQ_RXFRAMING_BYTE2_D1                                             0xa6f
++#define mmMC_SEQ_RXFRAMING_BYTE3_D1                                             0xa70
++#define mmMC_SEQ_RXFRAMING_DBI_D1                                               0xa71
++#define mmMC_SEQ_RXFRAMING_EDC_D1                                               0xa72
++#define mmMC_IO_PAD_CNTL                                                        0xa73
++#define mmMC_IO_PAD_CNTL_D0                                                     0xa74
++#define mmMC_IO_PAD_CNTL_D1                                                     0xa75
++#define mmMC_NPL_STATUS                                                         0xa76
++#define mmMC_BIST_CMD_CNTL                                                      0xa8e
++#define mmMC_BIST_CNTL                                                          0xa05
++#define mmMC_BIST_AUTO_CNTL                                                     0xa06
++#define mmMC_BIST_DIR_CNTL                                                      0xa07
++#define mmMC_BIST_SADDR                                                         0xa08
++#define mmMC_BIST_EADDR                                                         0xa09
++#define mmMC_BIST_CMP_CNTL                                                      0xa8d
++#define mmMC_BIST_CMP_CNTL_2                                                    0xab6
++#define mmMC_BIST_DATA_WORD0                                                    0xa0a
++#define mmMC_BIST_DATA_WORD1                                                    0xa0b
++#define mmMC_BIST_DATA_WORD2                                                    0xa0c
++#define mmMC_BIST_DATA_WORD3                                                    0xa0d
++#define mmMC_BIST_DATA_WORD4                                                    0xa0e
++#define mmMC_BIST_DATA_WORD5                                                    0xa0f
++#define mmMC_BIST_DATA_WORD6                                                    0xa10
++#define mmMC_BIST_DATA_WORD7                                                    0xa11
++#define mmMC_BIST_DATA_MASK                                                     0xa12
++#define mmMC_BIST_MISMATCH_ADDR                                                 0xa13
++#define mmMC_BIST_RDATA_WORD0                                                   0xa14
++#define mmMC_BIST_RDATA_WORD1                                                   0xa15
++#define mmMC_BIST_RDATA_WORD2                                                   0xa16
++#define mmMC_BIST_RDATA_WORD3                                                   0xa17
++#define mmMC_BIST_RDATA_WORD4                                                   0xa18
++#define mmMC_BIST_RDATA_WORD5                                                   0xa19
++#define mmMC_BIST_RDATA_WORD6                                                   0xa1a
++#define mmMC_BIST_RDATA_WORD7                                                   0xa1b
++#define mmMC_BIST_RDATA_MASK                                                    0xa1c
++#define mmMC_BIST_RDATA_EDC                                                     0xa1d
++#define mmMC_SEQ_PERF_CNTL                                                      0xa77
++#define mmMC_SEQ_PERF_CNTL_1                                                    0xafd
++#define mmMC_SEQ_PERF_SEQ_CTL                                                   0xa78
++#define mmMC_SEQ_PERF_SEQ_CNT_A_I0                                              0xa79
++#define mmMC_SEQ_PERF_SEQ_CNT_A_I1                                              0xa7a
++#define mmMC_SEQ_PERF_SEQ_CNT_B_I0                                              0xa7b
++#define mmMC_SEQ_PERF_SEQ_CNT_B_I1                                              0xa7c
++#define mmMC_SEQ_PERF_SEQ_CNT_C_I0                                              0xad9
++#define mmMC_SEQ_PERF_SEQ_CNT_C_I1                                              0xada
++#define mmMC_SEQ_PERF_SEQ_CNT_D_I0                                              0xadb
++#define mmMC_SEQ_PERF_SEQ_CNT_D_I1                                              0xadc
++#define mmMC_SEQ_STATUS_M                                                       0xa7d
++#define mmMC_SEQ_STATUS_S                                                       0xa20
++#define mmMC_CG_DATAPORT                                                        0xa21
++#define mmMC_SEQ_VENDOR_ID_I0                                                   0xa7e
++#define mmMC_SEQ_VENDOR_ID_I1                                                   0xa7f
++#define mmMC_SEQ_MISC0                                                          0xa80
++#define mmMC_SEQ_MISC1                                                          0xa81
++#define mmMC_SEQ_RESERVE_0_S                                                    0xa1e
++#define mmMC_SEQ_RESERVE_1_S                                                    0xa1f
++#define mmMC_SEQ_RESERVE_M                                                      0xa82
++#define mmMC_SEQ_IO_RESERVE_D0                                                  0xab7
++#define mmMC_SEQ_IO_RESERVE_D1                                                  0xab8
++#define mmMC_SEQ_SUP_CNTL                                                       0xa32
++#define mmMC_SEQ_SUP_PGM                                                        0xa33
++#define mmMC_SEQ_SUP_GP0_STAT                                                   0xa8f
++#define mmMC_SEQ_SUP_GP1_STAT                                                   0xa90
++#define mmMC_SEQ_SUP_GP2_STAT                                                   0xa85
++#define mmMC_SEQ_SUP_GP3_STAT                                                   0xa86
++#define mmMC_SEQ_SUP_IR_STAT                                                    0xa87
++#define mmMC_SEQ_SUP_DEC_STAT                                                   0xa88
++#define mmMC_SEQ_SUP_PGM_STAT                                                   0xa89
++#define mmMC_SEQ_SUP_R_PGM                                                      0xa8a
++#define mmMC_SEQ_MISC3                                                          0xa8b
++#define mmMC_SEQ_MISC4                                                          0xa8c
++#define mmMC_SEQ_MISC5                                                          0xa95
++#define mmMC_SEQ_MISC6                                                          0xa96
++#define mmMC_SEQ_MISC7                                                          0xa99
++#define mmMC_SEQ_MISC8                                                          0xa5f
++#define mmMC_SEQ_MISC9                                                          0xae7
++#define mmMC_SEQ_CG                                                             0xa9a
++#define mmMC_SEQ_BYTE_REMAP_D0                                                  0xa93
++#define mmMC_SEQ_BYTE_REMAP_D1                                                  0xa94
++#define mmMC_SEQ_BIT_REMAP_B0_D0                                                0xaa3
++#define mmMC_SEQ_BIT_REMAP_B1_D0                                                0xaa4
++#define mmMC_SEQ_BIT_REMAP_B2_D0                                                0xaa5
++#define mmMC_SEQ_BIT_REMAP_B3_D0                                                0xaa6
++#define mmMC_SEQ_BIT_REMAP_B0_D1                                                0xaa7
++#define mmMC_SEQ_BIT_REMAP_B1_D1                                                0xaa8
++#define mmMC_SEQ_BIT_REMAP_B2_D1                                                0xaa9
++#define mmMC_SEQ_BIT_REMAP_B3_D1                                                0xaaa
++#define mmMC_SEQ_RAS_TIMING_LP                                                  0xa9b
++#define mmMC_SEQ_CAS_TIMING_LP                                                  0xa9c
++#define mmMC_SEQ_MISC_TIMING_LP                                                 0xa9d
++#define mmMC_SEQ_MISC_TIMING2_LP                                                0xa9e
++#define mmMC_SEQ_RD_CTL_D0_LP                                                   0xac7
++#define mmMC_SEQ_RD_CTL_D1_LP                                                   0xac8
++#define mmMC_SEQ_WR_CTL_D0_LP                                                   0xa9f
++#define mmMC_SEQ_WR_CTL_D1_LP                                                   0xaa0
++#define mmMC_SEQ_WR_CTL_2_LP                                                    0xad6
++#define mmMC_SEQ_PMG_CMD_EMRS_LP                                                0xaa1
++#define mmMC_SEQ_PMG_CMD_MRS_LP                                                 0xaa2
++#define mmMC_SEQ_PMG_CMD_MRS1_LP                                                0xad2
++#define mmMC_SEQ_PMG_CMD_MRS2_LP                                                0xad8
++#define mmMC_SEQ_PMG_TIMING_LP                                                  0xad3
++#define mmMC_SEQ_IO_RWORD0                                                      0xaac
++#define mmMC_SEQ_IO_RWORD1                                                      0xaad
++#define mmMC_SEQ_IO_RWORD2                                                      0xaae
++#define mmMC_SEQ_IO_RWORD3                                                      0xaaf
++#define mmMC_SEQ_IO_RWORD4                                                      0xab0
++#define mmMC_SEQ_IO_RWORD5                                                      0xab1
++#define mmMC_SEQ_IO_RWORD6                                                      0xab2
++#define mmMC_SEQ_IO_RWORD7                                                      0xab3
++#define mmMC_SEQ_IO_RDBI                                                        0xab4
++#define mmMC_SEQ_IO_REDC                                                        0xab5
++#define mmMC_SEQ_TCG_CNTL                                                       0xabd
++#define mmMC_SEQ_TSM_CTRL                                                       0xabe
++#define mmMC_SEQ_TSM_GCNT                                                       0xabf
++#define mmMC_SEQ_TSM_OCNT                                                       0xac0
++#define mmMC_SEQ_TSM_NCNT                                                       0xac1
++#define mmMC_SEQ_TSM_BCNT                                                       0xac2
++#define mmMC_SEQ_TSM_FLAG                                                       0xac3
++#define mmMC_SEQ_TSM_UPDATE                                                     0xac4
++#define mmMC_SEQ_TSM_EDC                                                        0xac5
++#define mmMC_SEQ_TSM_DBI                                                        0xac6
++#define mmMC_SEQ_TSM_WCDR                                                       0xae3
++#define mmMC_SEQ_TSM_MISC                                                       0xae6
++#define mmMC_SEQ_TIMER_WR                                                       0xac9
++#define mmMC_SEQ_TIMER_RD                                                       0xaca
++#define mmMC_SEQ_DRAM_ERROR_INSERTION                                           0xacb
++#define mmMC_PHY_TIMING_D0                                                      0xacc
++#define mmMC_PHY_TIMING_D1                                                      0xacd
++#define mmMC_PHY_TIMING_2                                                       0xace
++#define mmMC_SEQ_MPLL_OVERRIDE                                                  0xa22
++#define mmMCLK_PWRMGT_CNTL                                                      0xae8
++#define mmDLL_CNTL                                                              0xae9
++#define mmMPLL_SEQ_UCODE_1                                                      0xaea
++#define mmMPLL_SEQ_UCODE_2                                                      0xaeb
++#define mmMPLL_CNTL_MODE                                                        0xaec
++#define mmMPLL_FUNC_CNTL                                                        0xaed
++#define mmMPLL_FUNC_CNTL_1                                                      0xaee
++#define mmMPLL_FUNC_CNTL_2                                                      0xaef
++#define mmMPLL_AD_FUNC_CNTL                                                     0xaf0
++#define mmMPLL_DQ_FUNC_CNTL                                                     0xaf1
++#define mmMPLL_TIME                                                             0xaf2
++#define mmMPLL_SS1                                                              0xaf3
++#define mmMPLL_SS2                                                              0xaf4
++#define mmMPLL_CONTROL                                                          0xaf5
++#define mmMPLL_AD_STATUS                                                        0xaf6
++#define mmMPLL_DQ_0_0_STATUS                                                    0xaf7
++#define mmMPLL_DQ_0_1_STATUS                                                    0xaf8
++#define mmMPLL_DQ_1_0_STATUS                                                    0xaf9
++#define mmMPLL_DQ_1_1_STATUS                                                    0xafa
++#define mmMC_SEQ_PMG_PG_HWCNTL                                                  0xab9
++#define mmMC_SEQ_PMG_PG_SWCNTL_0                                                0xaba
++#define mmMC_SEQ_PMG_PG_SWCNTL_1                                                0xabb
++#define mmMC_SEQ_TSM_DEBUG_INDEX                                                0xacf
++#define mmMC_SEQ_TSM_DEBUG_DATA                                                 0xad0
++#define ixMC_TSM_DEBUG_GCNT                                                     0x0
++#define ixMC_TSM_DEBUG_FLAG                                                     0x1
++#define ixMC_TSM_DEBUG_MISC                                                     0x2
++#define ixMC_TSM_DEBUG_BCNT0                                                    0x3
++#define ixMC_TSM_DEBUG_BCNT1                                                    0x4
++#define ixMC_TSM_DEBUG_BCNT2                                                    0x5
++#define ixMC_TSM_DEBUG_BCNT3                                                    0x6
++#define ixMC_TSM_DEBUG_BCNT4                                                    0x7
++#define ixMC_TSM_DEBUG_BCNT5                                                    0x8
++#define ixMC_TSM_DEBUG_BCNT6                                                    0x9
++#define ixMC_TSM_DEBUG_BCNT7                                                    0xa
++#define ixMC_TSM_DEBUG_BCNT8                                                    0xb
++#define ixMC_TSM_DEBUG_BCNT9                                                    0xc
++#define ixMC_TSM_DEBUG_BCNT10                                                   0xd
++#define ixMC_TSM_DEBUG_ST01                                                     0x10
++#define ixMC_TSM_DEBUG_ST23                                                     0x11
++#define ixMC_TSM_DEBUG_ST45                                                     0x12
++#define ixMC_TSM_DEBUG_BKPT                                                     0x13
++#define mmMC_SEQ_IO_DEBUG_INDEX                                                 0xa91
++#define mmMC_SEQ_IO_DEBUG_DATA                                                  0xa92
++#define ixMC_IO_DEBUG_UP_0                                                      0x0
++#define ixMC_IO_DEBUG_UP_1                                                      0x1
++#define ixMC_IO_DEBUG_UP_2                                                      0x2
++#define ixMC_IO_DEBUG_UP_3                                                      0x3
++#define ixMC_IO_DEBUG_UP_4                                                      0x4
++#define ixMC_IO_DEBUG_UP_5                                                      0x5
++#define ixMC_IO_DEBUG_UP_6                                                      0x6
++#define ixMC_IO_DEBUG_UP_7                                                      0x7
++#define ixMC_IO_DEBUG_UP_8                                                      0x8
++#define ixMC_IO_DEBUG_UP_9                                                      0x9
++#define ixMC_IO_DEBUG_UP_10                                                     0xa
++#define ixMC_IO_DEBUG_UP_11                                                     0xb
++#define ixMC_IO_DEBUG_UP_12                                                     0xc
++#define ixMC_IO_DEBUG_UP_13                                                     0xd
++#define ixMC_IO_DEBUG_UP_14                                                     0xe
++#define ixMC_IO_DEBUG_UP_15                                                     0xf
++#define ixMC_IO_DEBUG_UP_16                                                     0x10
++#define ixMC_IO_DEBUG_UP_17                                                     0x11
++#define ixMC_IO_DEBUG_UP_18                                                     0x12
++#define ixMC_IO_DEBUG_UP_19                                                     0x13
++#define ixMC_IO_DEBUG_UP_20                                                     0x14
++#define ixMC_IO_DEBUG_UP_21                                                     0x15
++#define ixMC_IO_DEBUG_UP_22                                                     0x16
++#define ixMC_IO_DEBUG_UP_23                                                     0x17
++#define ixMC_IO_DEBUG_UP_24                                                     0x18
++#define ixMC_IO_DEBUG_UP_25                                                     0x19
++#define ixMC_IO_DEBUG_UP_26                                                     0x1a
++#define ixMC_IO_DEBUG_UP_27                                                     0x1b
++#define ixMC_IO_DEBUG_UP_28                                                     0x1c
++#define ixMC_IO_DEBUG_UP_29                                                     0x1d
++#define ixMC_IO_DEBUG_UP_30                                                     0x1e
++#define ixMC_IO_DEBUG_UP_31                                                     0x1f
++#define ixMC_IO_DEBUG_UP_32                                                     0x20
++#define ixMC_IO_DEBUG_UP_33                                                     0x21
++#define ixMC_IO_DEBUG_UP_34                                                     0x22
++#define ixMC_IO_DEBUG_UP_35                                                     0x23
++#define ixMC_IO_DEBUG_UP_36                                                     0x24
++#define ixMC_IO_DEBUG_UP_37                                                     0x25
++#define ixMC_IO_DEBUG_UP_38                                                     0x26
++#define ixMC_IO_DEBUG_UP_39                                                     0x27
++#define ixMC_IO_DEBUG_UP_40                                                     0x28
++#define ixMC_IO_DEBUG_UP_41                                                     0x29
++#define ixMC_IO_DEBUG_UP_42                                                     0x2a
++#define ixMC_IO_DEBUG_UP_43                                                     0x2b
++#define ixMC_IO_DEBUG_UP_44                                                     0x2c
++#define ixMC_IO_DEBUG_UP_45                                                     0x2d
++#define ixMC_IO_DEBUG_UP_46                                                     0x2e
++#define ixMC_IO_DEBUG_UP_47                                                     0x2f
++#define ixMC_IO_DEBUG_UP_48                                                     0x30
++#define ixMC_IO_DEBUG_UP_49                                                     0x31
++#define ixMC_IO_DEBUG_UP_50                                                     0x32
++#define ixMC_IO_DEBUG_UP_51                                                     0x33
++#define ixMC_IO_DEBUG_UP_52                                                     0x34
++#define ixMC_IO_DEBUG_UP_53                                                     0x35
++#define ixMC_IO_DEBUG_UP_54                                                     0x36
++#define ixMC_IO_DEBUG_UP_55                                                     0x37
++#define ixMC_IO_DEBUG_UP_56                                                     0x38
++#define ixMC_IO_DEBUG_UP_57                                                     0x39
++#define ixMC_IO_DEBUG_UP_58                                                     0x3a
++#define ixMC_IO_DEBUG_UP_59                                                     0x3b
++#define ixMC_IO_DEBUG_UP_60                                                     0x3c
++#define ixMC_IO_DEBUG_UP_61                                                     0x3d
++#define ixMC_IO_DEBUG_UP_62                                                     0x3e
++#define ixMC_IO_DEBUG_UP_63                                                     0x3f
++#define ixMC_IO_DEBUG_UP_64                                                     0x40
++#define ixMC_IO_DEBUG_UP_65                                                     0x41
++#define ixMC_IO_DEBUG_UP_66                                                     0x42
++#define ixMC_IO_DEBUG_UP_67                                                     0x43
++#define ixMC_IO_DEBUG_UP_68                                                     0x44
++#define ixMC_IO_DEBUG_UP_69                                                     0x45
++#define ixMC_IO_DEBUG_UP_70                                                     0x46
++#define ixMC_IO_DEBUG_UP_71                                                     0x47
++#define ixMC_IO_DEBUG_UP_72                                                     0x48
++#define ixMC_IO_DEBUG_UP_73                                                     0x49
++#define ixMC_IO_DEBUG_UP_74                                                     0x4a
++#define ixMC_IO_DEBUG_UP_75                                                     0x4b
++#define ixMC_IO_DEBUG_UP_76                                                     0x4c
++#define ixMC_IO_DEBUG_UP_77                                                     0x4d
++#define ixMC_IO_DEBUG_UP_78                                                     0x4e
++#define ixMC_IO_DEBUG_UP_79                                                     0x4f
++#define ixMC_IO_DEBUG_UP_80                                                     0x50
++#define ixMC_IO_DEBUG_UP_81                                                     0x51
++#define ixMC_IO_DEBUG_UP_82                                                     0x52
++#define ixMC_IO_DEBUG_UP_83                                                     0x53
++#define ixMC_IO_DEBUG_UP_84                                                     0x54
++#define ixMC_IO_DEBUG_UP_85                                                     0x55
++#define ixMC_IO_DEBUG_UP_86                                                     0x56
++#define ixMC_IO_DEBUG_UP_87                                                     0x57
++#define ixMC_IO_DEBUG_UP_88                                                     0x58
++#define ixMC_IO_DEBUG_UP_89                                                     0x59
++#define ixMC_IO_DEBUG_UP_90                                                     0x5a
++#define ixMC_IO_DEBUG_UP_91                                                     0x5b
++#define ixMC_IO_DEBUG_UP_92                                                     0x5c
++#define ixMC_IO_DEBUG_UP_93                                                     0x5d
++#define ixMC_IO_DEBUG_UP_94                                                     0x5e
++#define ixMC_IO_DEBUG_UP_95                                                     0x5f
++#define ixMC_IO_DEBUG_UP_96                                                     0x60
++#define ixMC_IO_DEBUG_UP_97                                                     0x61
++#define ixMC_IO_DEBUG_UP_98                                                     0x62
++#define ixMC_IO_DEBUG_UP_99                                                     0x63
++#define ixMC_IO_DEBUG_UP_100                                                    0x64
++#define ixMC_IO_DEBUG_UP_101                                                    0x65
++#define ixMC_IO_DEBUG_UP_102                                                    0x66
++#define ixMC_IO_DEBUG_UP_103                                                    0x67
++#define ixMC_IO_DEBUG_UP_104                                                    0x68
++#define ixMC_IO_DEBUG_UP_105                                                    0x69
++#define ixMC_IO_DEBUG_UP_106                                                    0x6a
++#define ixMC_IO_DEBUG_UP_107                                                    0x6b
++#define ixMC_IO_DEBUG_UP_108                                                    0x6c
++#define ixMC_IO_DEBUG_UP_109                                                    0x6d
++#define ixMC_IO_DEBUG_UP_110                                                    0x6e
++#define ixMC_IO_DEBUG_UP_111                                                    0x6f
++#define ixMC_IO_DEBUG_UP_112                                                    0x70
++#define ixMC_IO_DEBUG_UP_113                                                    0x71
++#define ixMC_IO_DEBUG_UP_114                                                    0x72
++#define ixMC_IO_DEBUG_UP_115                                                    0x73
++#define ixMC_IO_DEBUG_UP_116                                                    0x74
++#define ixMC_IO_DEBUG_UP_117                                                    0x75
++#define ixMC_IO_DEBUG_UP_118                                                    0x76
++#define ixMC_IO_DEBUG_UP_119                                                    0x77
++#define ixMC_IO_DEBUG_UP_120                                                    0x78
++#define ixMC_IO_DEBUG_UP_121                                                    0x79
++#define ixMC_IO_DEBUG_UP_122                                                    0x7a
++#define ixMC_IO_DEBUG_UP_123                                                    0x7b
++#define ixMC_IO_DEBUG_UP_124                                                    0x7c
++#define ixMC_IO_DEBUG_UP_125                                                    0x7d
++#define ixMC_IO_DEBUG_UP_126                                                    0x7e
++#define ixMC_IO_DEBUG_UP_127                                                    0x7f
++#define ixMC_IO_DEBUG_UP_128                                                    0x80
++#define ixMC_IO_DEBUG_UP_129                                                    0x81
++#define ixMC_IO_DEBUG_UP_130                                                    0x82
++#define ixMC_IO_DEBUG_UP_131                                                    0x83
++#define ixMC_IO_DEBUG_UP_132                                                    0x84
++#define ixMC_IO_DEBUG_UP_133                                                    0x85
++#define ixMC_IO_DEBUG_UP_134                                                    0x86
++#define ixMC_IO_DEBUG_UP_135                                                    0x87
++#define ixMC_IO_DEBUG_UP_136                                                    0x88
++#define ixMC_IO_DEBUG_UP_137                                                    0x89
++#define ixMC_IO_DEBUG_UP_138                                                    0x8a
++#define ixMC_IO_DEBUG_UP_139                                                    0x8b
++#define ixMC_IO_DEBUG_UP_140                                                    0x8c
++#define ixMC_IO_DEBUG_UP_141                                                    0x8d
++#define ixMC_IO_DEBUG_UP_142                                                    0x8e
++#define ixMC_IO_DEBUG_UP_143                                                    0x8f
++#define ixMC_IO_DEBUG_UP_144                                                    0x90
++#define ixMC_IO_DEBUG_UP_145                                                    0x91
++#define ixMC_IO_DEBUG_UP_146                                                    0x92
++#define ixMC_IO_DEBUG_UP_147                                                    0x93
++#define ixMC_IO_DEBUG_UP_148                                                    0x94
++#define ixMC_IO_DEBUG_UP_149                                                    0x95
++#define ixMC_IO_DEBUG_UP_150                                                    0x96
++#define ixMC_IO_DEBUG_UP_151                                                    0x97
++#define ixMC_IO_DEBUG_UP_152                                                    0x98
++#define ixMC_IO_DEBUG_UP_153                                                    0x99
++#define ixMC_IO_DEBUG_UP_154                                                    0x9a
++#define ixMC_IO_DEBUG_UP_155                                                    0x9b
++#define ixMC_IO_DEBUG_UP_156                                                    0x9c
++#define ixMC_IO_DEBUG_UP_157                                                    0x9d
++#define ixMC_IO_DEBUG_UP_158                                                    0x9e
++#define ixMC_IO_DEBUG_UP_159                                                    0x9f
++#define ixMC_IO_DEBUG_DQB0L_MISC_D0                                             0xa0
++#define ixMC_IO_DEBUG_DQB0H_MISC_D0                                             0xa1
++#define ixMC_IO_DEBUG_DQB1L_MISC_D0                                             0xa2
++#define ixMC_IO_DEBUG_DQB1H_MISC_D0                                             0xa3
++#define ixMC_IO_DEBUG_DQB2L_MISC_D0                                             0xa4
++#define ixMC_IO_DEBUG_DQB2H_MISC_D0                                             0xa5
++#define ixMC_IO_DEBUG_DQB3L_MISC_D0                                             0xa6
++#define ixMC_IO_DEBUG_DQB3H_MISC_D0                                             0xa7
++#define ixMC_IO_DEBUG_DBI_MISC_D0                                               0xa8
++#define ixMC_IO_DEBUG_EDC_MISC_D0                                               0xa9
++#define ixMC_IO_DEBUG_WCK_MISC_D0                                               0xaa
++#define ixMC_IO_DEBUG_CK_MISC_D0                                                0xab
++#define ixMC_IO_DEBUG_ADDRL_MISC_D0                                             0xac
++#define ixMC_IO_DEBUG_ADDRH_MISC_D0                                             0xad
++#define ixMC_IO_DEBUG_ACMD_MISC_D0                                              0xae
++#define ixMC_IO_DEBUG_CMD_MISC_D0                                               0xaf
++#define ixMC_IO_DEBUG_DQB0L_MISC_D1                                             0xb0
++#define ixMC_IO_DEBUG_DQB0H_MISC_D1                                             0xb1
++#define ixMC_IO_DEBUG_DQB1L_MISC_D1                                             0xb2
++#define ixMC_IO_DEBUG_DQB1H_MISC_D1                                             0xb3
++#define ixMC_IO_DEBUG_DQB2L_MISC_D1                                             0xb4
++#define ixMC_IO_DEBUG_DQB2H_MISC_D1                                             0xb5
++#define ixMC_IO_DEBUG_DQB3L_MISC_D1                                             0xb6
++#define ixMC_IO_DEBUG_DQB3H_MISC_D1                                             0xb7
++#define ixMC_IO_DEBUG_DBI_MISC_D1                                               0xb8
++#define ixMC_IO_DEBUG_EDC_MISC_D1                                               0xb9
++#define ixMC_IO_DEBUG_WCK_MISC_D1                                               0xba
++#define ixMC_IO_DEBUG_CK_MISC_D1                                                0xbb
++#define ixMC_IO_DEBUG_ADDRL_MISC_D1                                             0xbc
++#define ixMC_IO_DEBUG_ADDRH_MISC_D1                                             0xbd
++#define ixMC_IO_DEBUG_ACMD_MISC_D1                                              0xbe
++#define ixMC_IO_DEBUG_CMD_MISC_D1                                               0xbf
++#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0                                           0xc0
++#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0                                           0xc1
++#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0                                           0xc2
++#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0                                           0xc3
++#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0                                           0xc4
++#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0                                           0xc5
++#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0                                           0xc6
++#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0                                           0xc7
++#define ixMC_IO_DEBUG_DBI_CLKSEL_D0                                             0xc8
++#define ixMC_IO_DEBUG_EDC_CLKSEL_D0                                             0xc9
++#define ixMC_IO_DEBUG_WCK_CLKSEL_D0                                             0xca
++#define ixMC_IO_DEBUG_CK_CLKSEL_D0                                              0xcb
++#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0                                           0xcc
++#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0                                           0xcd
++#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0                                            0xce
++#define ixMC_IO_DEBUG_CMD_CLKSEL_D0                                             0xcf
++#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1                                           0xd0
++#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1                                           0xd1
++#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1                                           0xd2
++#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1                                           0xd3
++#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1                                           0xd4
++#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1                                           0xd5
++#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1                                           0xd6
++#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1                                           0xd7
++#define ixMC_IO_DEBUG_DBI_CLKSEL_D1                                             0xd8
++#define ixMC_IO_DEBUG_EDC_CLKSEL_D1                                             0xd9
++#define ixMC_IO_DEBUG_WCK_CLKSEL_D1                                             0xda
++#define ixMC_IO_DEBUG_CK_CLKSEL_D1                                              0xdb
++#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1                                           0xdc
++#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1                                           0xdd
++#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1                                            0xde
++#define ixMC_IO_DEBUG_CMD_CLKSEL_D1                                             0xdf
++#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0                                           0xe0
++#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0                                           0xe1
++#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0                                           0xe2
++#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0                                           0xe3
++#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0                                           0xe4
++#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0                                           0xe5
++#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0                                           0xe6
++#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0                                           0xe7
++#define ixMC_IO_DEBUG_DBI_OFSCAL_D0                                             0xe8
++#define ixMC_IO_DEBUG_EDC_OFSCAL_D0                                             0xe9
++#define ixMC_IO_DEBUG_WCK_OFSCAL_D0                                             0xea
++#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0                                           0xeb
++#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0                                          0xec
++#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0                                         0xed
++#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0                                            0xee
++#define ixMC_IO_DEBUG_CMD_OFSCAL_D0                                             0xef
++#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1                                           0xf0
++#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1                                           0xf1
++#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1                                           0xf2
++#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1                                           0xf3
++#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1                                           0xf4
++#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1                                           0xf5
++#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1                                           0xf6
++#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1                                           0xf7
++#define ixMC_IO_DEBUG_DBI_OFSCAL_D1                                             0xf8
++#define ixMC_IO_DEBUG_EDC_OFSCAL_D1                                             0xf9
++#define ixMC_IO_DEBUG_WCK_OFSCAL_D1                                             0xfa
++#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1                                           0xfb
++#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1                                          0xfc
++#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1                                         0xfd
++#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1                                            0xfe
++#define ixMC_IO_DEBUG_CMD_OFSCAL_D1                                             0xff
++#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0                                          0x100
++#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0                                          0x101
++#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0                                          0x102
++#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0                                          0x103
++#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0                                          0x104
++#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0                                          0x105
++#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0                                          0x106
++#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0                                          0x107
++#define ixMC_IO_DEBUG_DBI_RXPHASE_D0                                            0x108
++#define ixMC_IO_DEBUG_EDC_RXPHASE_D0                                            0x109
++#define ixMC_IO_DEBUG_WCK_RXPHASE_D0                                            0x10a
++#define ixMC_IO_DEBUG_CK_RXPHASE_D0                                             0x10b
++#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0                                          0x10c
++#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0                                          0x10d
++#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0                                           0x10e
++#define ixMC_IO_DEBUG_CMD_RXPHASE_D0                                            0x10f
++#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1                                          0x110
++#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1                                          0x111
++#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1                                          0x112
++#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1                                          0x113
++#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1                                          0x114
++#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1                                          0x115
++#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1                                          0x116
++#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1                                          0x117
++#define ixMC_IO_DEBUG_DBI_RXPHASE_D1                                            0x118
++#define ixMC_IO_DEBUG_EDC_RXPHASE_D1                                            0x119
++#define ixMC_IO_DEBUG_WCK_RXPHASE_D1                                            0x11a
++#define ixMC_IO_DEBUG_CK_RXPHASE_D1                                             0x11b
++#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1                                          0x11c
++#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1                                          0x11d
++#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1                                           0x11e
++#define ixMC_IO_DEBUG_CMD_RXPHASE_D1                                            0x11f
++#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0                                          0x120
++#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0                                          0x121
++#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0                                          0x122
++#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0                                          0x123
++#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0                                          0x124
++#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0                                          0x125
++#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0                                          0x126
++#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0                                          0x127
++#define ixMC_IO_DEBUG_DBI_TXPHASE_D0                                            0x128
++#define ixMC_IO_DEBUG_EDC_TXPHASE_D0                                            0x129
++#define ixMC_IO_DEBUG_WCK_TXPHASE_D0                                            0x12a
++#define ixMC_IO_DEBUG_CK_TXPHASE_D0                                             0x12b
++#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0                                          0x12c
++#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0                                          0x12d
++#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0                                           0x12e
++#define ixMC_IO_DEBUG_CMD_TXPHASE_D0                                            0x12f
++#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1                                          0x130
++#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1                                          0x131
++#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1                                          0x132
++#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1                                          0x133
++#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1                                          0x134
++#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1                                          0x135
++#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1                                          0x136
++#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1                                          0x137
++#define ixMC_IO_DEBUG_DBI_TXPHASE_D1                                            0x138
++#define ixMC_IO_DEBUG_EDC_TXPHASE_D1                                            0x139
++#define ixMC_IO_DEBUG_WCK_TXPHASE_D1                                            0x13a
++#define ixMC_IO_DEBUG_CK_TXPHASE_D1                                             0x13b
++#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1                                          0x13c
++#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1                                          0x13d
++#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1                                           0x13e
++#define ixMC_IO_DEBUG_CMD_TXPHASE_D1                                            0x13f
++#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0                                      0x140
++#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0                                      0x141
++#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0                                      0x142
++#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0                                      0x143
++#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0                                      0x144
++#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0                                      0x145
++#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0                                      0x146
++#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0                                      0x147
++#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0                                        0x148
++#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0                                        0x149
++#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0                                        0x14a
++#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0                                        0x14b
++#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0                                        0x14c
++#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0                                        0x14d
++#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0                                        0x14e
++#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0                                         0x14f
++#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1                                      0x150
++#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1                                      0x151
++#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1                                      0x152
++#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1                                      0x153
++#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1                                      0x154
++#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1                                      0x155
++#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1                                      0x156
++#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1                                      0x157
++#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1                                        0x158
++#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1                                        0x159
++#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1                                        0x15a
++#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1                                        0x15b
++#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1                                        0x15c
++#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1                                        0x15d
++#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1                                        0x15e
++#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1                                         0x15f
++#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0                                            0x160
++#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0                                            0x161
++#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0                                            0x162
++#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0                                            0x163
++#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0                                            0x164
++#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0                                            0x165
++#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0                                            0x166
++#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0                                            0x167
++#define ixMC_IO_DEBUG_DBI_TXSLF_D0                                              0x168
++#define ixMC_IO_DEBUG_EDC_TXSLF_D0                                              0x169
++#define ixMC_IO_DEBUG_WCK_TXSLF_D0                                              0x16a
++#define ixMC_IO_DEBUG_CK_TXSLF_D0                                               0x16b
++#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0                                            0x16c
++#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0                                            0x16d
++#define ixMC_IO_DEBUG_ACMD_TXSLF_D0                                             0x16e
++#define ixMC_IO_DEBUG_CMD_TXSLF_D0                                              0x16f
++#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1                                            0x170
++#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1                                            0x171
++#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1                                            0x172
++#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1                                            0x173
++#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1                                            0x174
++#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1                                            0x175
++#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1                                            0x176
++#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1                                            0x177
++#define ixMC_IO_DEBUG_DBI_TXSLF_D1                                              0x178
++#define ixMC_IO_DEBUG_EDC_TXSLF_D1                                              0x179
++#define ixMC_IO_DEBUG_WCK_TXSLF_D1                                              0x17a
++#define ixMC_IO_DEBUG_CK_TXSLF_D1                                               0x17b
++#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1                                            0x17c
++#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1                                            0x17d
++#define ixMC_IO_DEBUG_ACMD_TXSLF_D1                                             0x17e
++#define ixMC_IO_DEBUG_CMD_TXSLF_D1                                              0x17f
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0                                         0x180
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0                                         0x181
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0                                         0x182
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0                                         0x183
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0                                         0x184
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0                                         0x185
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0                                         0x186
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0                                         0x187
++#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0                                           0x188
++#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0                                           0x189
++#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0                                           0x18a
++#define ixMC_IO_DEBUG_CK_TXBST_PD_D0                                            0x18b
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0                                         0x18c
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0                                         0x18d
++#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0                                          0x18e
++#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0                                           0x18f
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1                                         0x190
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1                                         0x191
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1                                         0x192
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1                                         0x193
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1                                         0x194
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1                                         0x195
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1                                         0x196
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1                                         0x197
++#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1                                           0x198
++#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1                                           0x199
++#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1                                           0x19a
++#define ixMC_IO_DEBUG_CK_TXBST_PD_D1                                            0x19b
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1                                         0x19c
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1                                         0x19d
++#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1                                          0x19e
++#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1                                           0x19f
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0                                         0x1a0
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0                                         0x1a1
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0                                         0x1a2
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0                                         0x1a3
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0                                         0x1a4
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0                                         0x1a5
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0                                         0x1a6
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0                                         0x1a7
++#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0                                           0x1a8
++#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0                                           0x1a9
++#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0                                           0x1aa
++#define ixMC_IO_DEBUG_CK_TXBST_PU_D0                                            0x1ab
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0                                         0x1ac
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0                                         0x1ad
++#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0                                          0x1ae
++#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0                                           0x1af
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1                                         0x1b0
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1                                         0x1b1
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1                                         0x1b2
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1                                         0x1b3
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1                                         0x1b4
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1                                         0x1b5
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1                                         0x1b6
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1                                         0x1b7
++#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1                                           0x1b8
++#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1                                           0x1b9
++#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1                                           0x1ba
++#define ixMC_IO_DEBUG_CK_TXBST_PU_D1                                            0x1bb
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1                                         0x1bc
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1                                         0x1bd
++#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1                                          0x1be
++#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1                                           0x1bf
++#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0                                            0x1c0
++#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0                                            0x1c1
++#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0                                            0x1c2
++#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0                                            0x1c3
++#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0                                            0x1c4
++#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0                                            0x1c5
++#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0                                            0x1c6
++#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0                                            0x1c7
++#define ixMC_IO_DEBUG_DBI_RX_EQ_D0                                              0x1c8
++#define ixMC_IO_DEBUG_EDC_RX_EQ_D0                                              0x1c9
++#define ixMC_IO_DEBUG_WCK_RX_EQ_D0                                              0x1ca
++#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0                                           0x1cb
++#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0                                           0x1cc
++#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0                                          0x1cd
++#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0                                          0x1ce
++#define ixMC_IO_DEBUG_CMD_RX_EQ_D0                                              0x1cf
++#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1                                            0x1d0
++#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1                                            0x1d1
++#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1                                            0x1d2
++#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1                                            0x1d3
++#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1                                            0x1d4
++#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1                                            0x1d5
++#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1                                            0x1d6
++#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1                                            0x1d7
++#define ixMC_IO_DEBUG_DBI_RX_EQ_D1                                              0x1d8
++#define ixMC_IO_DEBUG_EDC_RX_EQ_D1                                              0x1d9
++#define ixMC_IO_DEBUG_WCK_RX_EQ_D1                                              0x1da
++#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1                                           0x1db
++#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1                                           0x1dc
++#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1                                          0x1dd
++#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1                                          0x1de
++#define ixMC_IO_DEBUG_CMD_RX_EQ_D1                                              0x1df
++#define ixMC_IO_DEBUG_WCDR_MISC_D0                                              0x1e0
++#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0                                            0x1e1
++#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0                                            0x1e2
++#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0                                           0x1e3
++#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0                                           0x1e4
++#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0                                       0x1e5
++#define ixMC_IO_DEBUG_WCDR_TXSLF_D0                                             0x1e6
++#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0                                          0x1e7
++#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0                                          0x1e8
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0                                             0x1e9
++#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0                                        0x1ea
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0                                          0x1eb
++#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0                                         0x1ec
++#define ixMC_IO_DEBUG_WCDR_MISC_D1                                              0x1f0
++#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1                                            0x1f1
++#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1                                            0x1f2
++#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1                                           0x1f3
++#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1                                           0x1f4
++#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1                                       0x1f5
++#define ixMC_IO_DEBUG_WCDR_TXSLF_D1                                             0x1f6
++#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1                                          0x1f7
++#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1                                          0x1f8
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1                                             0x1f9
++#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1                                        0x1fa
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1                                          0x1fb
++#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1                                         0x1fc
++#define mmMC_SEQ_CNTL_3                                                         0xd80
++#define mmMC_SEQ_G5PDX_CTRL                                                     0xd81
++#define mmMC_SEQ_G5PDX_CTRL_LP                                                  0xd82
++#define mmMC_SEQ_G5PDX_CMD0                                                     0xd83
++#define mmMC_SEQ_G5PDX_CMD0_LP                                                  0xd84
++#define mmMC_SEQ_G5PDX_CMD1                                                     0xd85
++#define mmMC_SEQ_G5PDX_CMD1_LP                                                  0xd86
++#define mmMC_SEQ_SREG_READ                                                      0xd87
++#define mmMC_SEQ_SREG_STATUS                                                    0xd88
++#define mmMC_SEQ_PHYREG_BCAST                                                   0xd89
++#define mmMC_SEQ_PMG_DVS_CTL                                                    0xd8a
++#define mmMC_SEQ_PMG_DVS_CTL_LP                                                 0xd8b
++#define mmMC_SEQ_PMG_DVS_CMD                                                    0xd8c
++#define mmMC_SEQ_PMG_DVS_CMD_LP                                                 0xd8d
++#define mmMC_SEQ_DLL_STBY                                                       0xd8e
++#define mmMC_SEQ_DLL_STBY_LP                                                    0xd8f
++#define mmMC_DLB_MISCCTRL0                                                      0xd90
++#define mmMC_DLB_MISCCTRL1                                                      0xd91
++#define mmMC_DLB_MISCCTRL2                                                      0xd92
++#define mmMC_DLB_CONFIG0                                                        0xd93
++#define mmMC_DLB_CONFIG1                                                        0xd94
++#define mmMC_DLB_SETUP                                                          0xd95
++#define mmMC_DLB_SETUPSWEEP                                                     0xd96
++#define mmMC_DLB_SETUPFIFO                                                      0xd97
++#define mmMC_DLB_WRITE_MASK                                                     0xd98
++#define mmMC_DLB_STATUS                                                         0xd99
++#define mmMC_DLB_STATUS_MISC0                                                   0xd9a
++#define mmMC_DLB_STATUS_MISC1                                                   0xd9b
++#define mmMC_DLB_STATUS_MISC2                                                   0xd9c
++#define mmMC_DLB_STATUS_MISC3                                                   0xd9d
++#define mmMC_DLB_STATUS_MISC4                                                   0xd9e
++#define mmMC_DLB_STATUS_MISC5                                                   0xd9f
++#define mmMC_DLB_STATUS_MISC6                                                   0xda0
++#define mmMC_DLB_STATUS_MISC7                                                   0xda1
++#define mmMC_ARB_HARSH_EN_RD                                                    0xdc0
++#define mmMC_ARB_HARSH_EN_WR                                                    0xdc1
++#define mmMC_ARB_HARSH_TX_HI0_RD                                                0xdc2
++#define mmMC_ARB_HARSH_TX_HI0_WR                                                0xdc3
++#define mmMC_ARB_HARSH_TX_HI1_RD                                                0xdc4
++#define mmMC_ARB_HARSH_TX_HI1_WR                                                0xdc5
++#define mmMC_ARB_HARSH_TX_LO0_RD                                                0xdc6
++#define mmMC_ARB_HARSH_TX_LO0_WR                                                0xdc7
++#define mmMC_ARB_HARSH_TX_LO1_RD                                                0xdc8
++#define mmMC_ARB_HARSH_TX_LO1_WR                                                0xdc9
++#define mmMC_ARB_HARSH_BWPERIOD0_RD                                             0xdca
++#define mmMC_ARB_HARSH_BWPERIOD0_WR                                             0xdcb
++#define mmMC_ARB_HARSH_BWPERIOD1_RD                                             0xdcc
++#define mmMC_ARB_HARSH_BWPERIOD1_WR                                             0xdcd
++#define mmMC_ARB_HARSH_BWCNT0_RD                                                0xdce
++#define mmMC_ARB_HARSH_BWCNT0_WR                                                0xdcf
++#define mmMC_ARB_HARSH_BWCNT1_RD                                                0xdd0
++#define mmMC_ARB_HARSH_BWCNT1_WR                                                0xdd1
++#define mmMC_ARB_HARSH_SAT0_RD                                                  0xdd2
++#define mmMC_ARB_HARSH_SAT0_WR                                                  0xdd3
++#define mmMC_ARB_HARSH_SAT1_RD                                                  0xdd4
++#define mmMC_ARB_HARSH_SAT1_WR                                                  0xdd5
++#define mmMC_ARB_HARSH_CTL_RD                                                   0xdd6
++#define mmMC_ARB_HARSH_CTL_WR                                                   0xdd7
++
++#endif /* GMC_7_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h
+new file mode 100644
+index 0000000..3a202b6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h
+@@ -0,0 +1,14416 @@
++/*
++ * GMC_7_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_7_1_SH_MASK_H
++#define GMC_7_1_SH_MASK_H
++
++#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
++#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
++#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
++#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
++#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
++#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
++#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
++#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
++#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
++#define MC_ARB_FED_CNTL__MODE_MASK 0x3
++#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
++#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
++#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
++#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
++#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
++#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
++#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
++#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
++#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
++#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
++#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
++#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
++#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
++#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
++#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
++#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
++#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
++#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
++#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
++#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
++#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
++#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
++#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
++#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
++#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
++#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
++#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
++#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
++#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
++#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
++#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
++#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
++#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
++#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
++#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
++#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
++#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
++#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
++#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
++#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
++#define MC_ARB_PERF_CID__CH0_MASK 0xff
++#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
++#define MC_ARB_PERF_CID__CH1_MASK 0xff00
++#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
++#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
++#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
++#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
++#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
++#define MC_ARB_GECC2__ENABLE_MASK 0x1
++#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
++#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
++#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
++#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
++#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
++#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
++#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
++#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
++#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
++#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
++#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
++#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
++#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
++#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
++#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
++#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
++#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
++#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
++#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
++#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
++#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
++#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
++#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
++#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
++#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
++#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
++#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
++#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
++#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
++#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
++#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
++#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffff8
++#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x3
++#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
++#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
++#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
++#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
++#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
++#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
++#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
++#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
++#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
++#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
++#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
++#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
++#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
++#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
++#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
++#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
++#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
++#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
++#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
++#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
++#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
++#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
++#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
++#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
++#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
++#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
++#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
++#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
++#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
++#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
++#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
++#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
++#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
++#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
++#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
++#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
++#define MC_ARB_MISC2__GECC_MASK 0x40000
++#define MC_ARB_MISC2__GECC__SHIFT 0x12
++#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
++#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
++#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
++#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
++#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
++#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
++#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
++#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
++#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
++#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
++#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
++#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
++#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
++#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
++#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
++#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
++#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
++#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
++#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
++#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
++#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
++#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
++#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
++#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
++#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
++#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
++#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
++#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
++#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
++#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
++#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
++#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
++#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
++#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
++#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
++#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
++#define MC_ARB_BANKMAP__BANK0_MASK 0xf
++#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
++#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
++#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
++#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
++#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
++#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
++#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
++#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
++#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
++#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
++#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
++#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
++#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
++#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
++#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
++#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
++#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
++#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
++#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
++#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
++#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
++#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
++#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
++#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
++#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
++#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
++#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
++#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
++#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
++#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
++#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
++#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
++#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
++#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
++#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
++#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
++#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
++#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
++#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
++#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
++#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
++#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
++#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
++#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
++#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
++#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
++#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
++#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
++#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
++#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
++#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
++#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
++#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
++#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
++#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
++#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
++#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
++#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
++#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
++#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
++#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
++#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
++#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
++#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
++#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
++#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
++#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
++#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
++#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
++#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
++#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
++#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
++#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
++#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
++#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
++#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
++#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
++#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
++#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
++#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
++#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
++#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
++#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
++#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
++#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
++#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
++#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
++#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
++#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
++#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
++#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
++#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
++#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
++#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
++#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
++#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
++#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
++#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
++#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
++#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
++#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
++#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
++#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
++#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
++#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
++#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
++#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
++#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
++#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
++#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
++#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
++#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
++#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
++#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
++#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
++#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
++#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
++#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
++#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
++#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
++#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
++#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
++#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
++#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
++#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
++#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_SSM__FORMAT_MASK 0x1f
++#define MC_ARB_SSM__FORMAT__SHIFT 0x0
++#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
++#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
++#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
++#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
++#define MC_ARB_CG__RSV_0_MASK 0xff0000
++#define MC_ARB_CG__RSV_0__SHIFT 0x10
++#define MC_ARB_CG__RSV_1_MASK 0xff000000
++#define MC_ARB_CG__RSV_1__SHIFT 0x18
++#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
++#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
++#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
++#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
++#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
++#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
++#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
++#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
++#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
++#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
++#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
++#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
++#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
++#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
++#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
++#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
++#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
++#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
++#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
++#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
++#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
++#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
++#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
++#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
++#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
++#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
++#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
++#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
++#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
++#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
++#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
++#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
++#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
++#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
++#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
++#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
++#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
++#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
++#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
++#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
++#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
++#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
++#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
++#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
++#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
++#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
++#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
++#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
++#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
++#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
++#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
++#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
++#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
++#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
++#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
++#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
++#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
++#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
++#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
++#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
++#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
++#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
++#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
++#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
++#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
++#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
++#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
++#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
++#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
++#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
++#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
++#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
++#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
++#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
++#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
++#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
++#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
++#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
++#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
++#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
++#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
++#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
++#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
++#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
++#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
++#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
++#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
++#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
++#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
++#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
++#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
++#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
++#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
++#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
++#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
++#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
++#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
++#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
++#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
++#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
++#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
++#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
++#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
++#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
++#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
++#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
++#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
++#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
++#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
++#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
++#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
++#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
++#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
++#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
++#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
++#define MC_CG_CONFIG__INDEX__SHIFT 0x6
++#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
++#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
++#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
++#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
++#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
++#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
++#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
++#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
++#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
++#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
++#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
++#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
++#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
++#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
++#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
++#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
++#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
++#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
++#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
++#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
++#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
++#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
++#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
++#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
++#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
++#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
++#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
++#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
++#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_RD_GRP_EXT__TC0_MASK 0xf0
++#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
++#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_WR_GRP_EXT__TC0_MASK 0xf0
++#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
++#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
++#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
++#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
++#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
++#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
++#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
++#define MC_WR_TC0__ENABLE_MASK 0x1
++#define MC_WR_TC0__ENABLE__SHIFT 0x0
++#define MC_WR_TC0__PRESCALE_MASK 0x6
++#define MC_WR_TC0__PRESCALE__SHIFT 0x1
++#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC0__STALL_MODE_MASK 0x30
++#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC0__MAX_BURST_MASK 0x780
++#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_TC1__ENABLE_MASK 0x1
++#define MC_WR_TC1__ENABLE__SHIFT 0x0
++#define MC_WR_TC1__PRESCALE_MASK 0x6
++#define MC_WR_TC1__PRESCALE__SHIFT 0x1
++#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC1__STALL_MODE_MASK 0x30
++#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC1__MAX_BURST_MASK 0x780
++#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_RD_CB__ENABLE_MASK 0x1
++#define MC_RD_CB__ENABLE__SHIFT 0x0
++#define MC_RD_CB__PRESCALE_MASK 0x6
++#define MC_RD_CB__PRESCALE__SHIFT 0x1
++#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_CB__STALL_MODE_MASK 0x30
++#define MC_RD_CB__STALL_MODE__SHIFT 0x4
++#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_CB__MAX_BURST_MASK 0x780
++#define MC_RD_CB__MAX_BURST__SHIFT 0x7
++#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_DB__ENABLE_MASK 0x1
++#define MC_RD_DB__ENABLE__SHIFT 0x0
++#define MC_RD_DB__PRESCALE_MASK 0x6
++#define MC_RD_DB__PRESCALE__SHIFT 0x1
++#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_DB__STALL_MODE_MASK 0x30
++#define MC_RD_DB__STALL_MODE__SHIFT 0x4
++#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_DB__MAX_BURST_MASK 0x780
++#define MC_RD_DB__MAX_BURST__SHIFT 0x7
++#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC0__ENABLE_MASK 0x1
++#define MC_RD_TC0__ENABLE__SHIFT 0x0
++#define MC_RD_TC0__PRESCALE_MASK 0x6
++#define MC_RD_TC0__PRESCALE__SHIFT 0x1
++#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC0__STALL_MODE_MASK 0x30
++#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC0__MAX_BURST_MASK 0x780
++#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC1__ENABLE_MASK 0x1
++#define MC_RD_TC1__ENABLE__SHIFT 0x0
++#define MC_RD_TC1__PRESCALE_MASK 0x6
++#define MC_RD_TC1__PRESCALE__SHIFT 0x1
++#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC1__STALL_MODE_MASK 0x30
++#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC1__MAX_BURST_MASK 0x780
++#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_HUB__ENABLE_MASK 0x1
++#define MC_RD_HUB__ENABLE__SHIFT 0x0
++#define MC_RD_HUB__PRESCALE_MASK 0x6
++#define MC_RD_HUB__PRESCALE__SHIFT 0x1
++#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_HUB__STALL_MODE_MASK 0x30
++#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
++#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_HUB__MAX_BURST_MASK 0x780
++#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
++#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_CB__ENABLE_MASK 0x1
++#define MC_WR_CB__ENABLE__SHIFT 0x0
++#define MC_WR_CB__PRESCALE_MASK 0x6
++#define MC_WR_CB__PRESCALE__SHIFT 0x1
++#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_CB__STALL_MODE_MASK 0x30
++#define MC_WR_CB__STALL_MODE__SHIFT 0x4
++#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_CB__MAX_BURST_MASK 0x780
++#define MC_WR_CB__MAX_BURST__SHIFT 0x7
++#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_DB__ENABLE_MASK 0x1
++#define MC_WR_DB__ENABLE__SHIFT 0x0
++#define MC_WR_DB__PRESCALE_MASK 0x6
++#define MC_WR_DB__PRESCALE__SHIFT 0x1
++#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_DB__STALL_MODE_MASK 0x30
++#define MC_WR_DB__STALL_MODE__SHIFT 0x4
++#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_DB__MAX_BURST_MASK 0x780
++#define MC_WR_DB__MAX_BURST__SHIFT 0x7
++#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_HUB__ENABLE_MASK 0x1
++#define MC_WR_HUB__ENABLE__SHIFT 0x0
++#define MC_WR_HUB__PRESCALE_MASK 0x6
++#define MC_WR_HUB__PRESCALE__SHIFT 0x1
++#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_HUB__STALL_MODE_MASK 0x30
++#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
++#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_HUB__MAX_BURST_MASK 0x780
++#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
++#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
++#define MC_RD_GRP_LCL__CB0_MASK 0xf000
++#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
++#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
++#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
++#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
++#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
++#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
++#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
++#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
++#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
++#define MC_WR_GRP_LCL__CB0_MASK 0xf
++#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
++#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
++#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
++#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
++#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
++#define MC_WR_GRP_LCL__DB0_MASK 0xf000
++#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
++#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
++#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
++#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
++#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
++#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
++#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
++#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
++#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
++#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
++#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
++#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
++#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
++#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
++#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
++#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
++#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
++#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
++#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
++#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
++#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
++#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
++#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
++#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
++#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
++#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
++#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
++#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
++#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
++#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
++#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
++#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
++#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
++#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
++#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
++#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
++#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
++#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
++#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x40000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1e
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x80000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1f
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
++#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
++#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
++#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
++#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
++#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
++#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
++#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
++#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
++#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
++#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCE__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_VCE__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
++#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
++#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
++#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
++#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCE__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_VCE__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
++#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
++#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
++#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
++#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
++#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
++#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
++#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
++#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
++#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
++#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
++#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
++#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
++#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
++#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
++#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
++#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
++#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
++#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
++#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
++#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
++#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
++#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
++#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
++#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
++#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
++#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
++#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
++#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
++#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
++#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
++#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
++#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
++#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
++#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
++#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
++#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
++#define MC_RD_GRP_GFX__CP_MASK 0xf
++#define MC_RD_GRP_GFX__CP__SHIFT 0x0
++#define MC_RD_GRP_GFX__SH_MASK 0xf0
++#define MC_RD_GRP_GFX__SH__SHIFT 0x4
++#define MC_RD_GRP_GFX__IA_MASK 0xf00
++#define MC_RD_GRP_GFX__IA__SHIFT 0x8
++#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
++#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
++#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
++#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
++#define MC_RD_GRP_GFX__ISP_MASK 0xf00000
++#define MC_RD_GRP_GFX__ISP__SHIFT 0x14
++#define MC_RD_GRP_GFX__XDMAM_MASK 0xf000000
++#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x18
++#define MC_WR_GRP_GFX__CP_MASK 0xf
++#define MC_WR_GRP_GFX__CP__SHIFT 0x0
++#define MC_WR_GRP_GFX__SH_MASK 0xf0
++#define MC_WR_GRP_GFX__SH__SHIFT 0x4
++#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
++#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
++#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
++#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
++#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
++#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
++#define MC_WR_GRP_GFX__XDMA_MASK 0xf00000
++#define MC_WR_GRP_GFX__XDMA__SHIFT 0x14
++#define MC_WR_GRP_GFX__XDMAM_MASK 0xf000000
++#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x18
++#define MC_RD_GRP_SYS__RLC_MASK 0xf
++#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
++#define MC_RD_GRP_SYS__VMC_MASK 0xf0
++#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
++#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
++#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
++#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
++#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
++#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
++#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
++#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
++#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
++#define MC_RD_GRP_SYS__VCE_MASK 0xf000000
++#define MC_RD_GRP_SYS__VCE__SHIFT 0x18
++#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
++#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
++#define MC_WR_GRP_SYS__IH_MASK 0xf
++#define MC_WR_GRP_SYS__IH__SHIFT 0x0
++#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
++#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
++#define MC_WR_GRP_SYS__RLC_MASK 0xf00
++#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
++#define MC_WR_GRP_SYS__SAM_MASK 0xf000
++#define MC_WR_GRP_SYS__SAM__SHIFT 0xc
++#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
++#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
++#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
++#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
++#define MC_WR_GRP_SYS__VCE_MASK 0xf000000
++#define MC_WR_GRP_SYS__VCE__SHIFT 0x18
++#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
++#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
++#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_RD_GRP_OTH__HDP_MASK 0xf00
++#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
++#define MC_RD_GRP_OTH__SEM_MASK 0xf000
++#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
++#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
++#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
++#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
++#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
++#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
++#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
++#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
++#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
++#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_WR_GRP_OTH__HDP_MASK 0xf00
++#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
++#define MC_WR_GRP_OTH__SEM_MASK 0xf000
++#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
++#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
++#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
++#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
++#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
++#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
++#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
++#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
++#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
++#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
++#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
++#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
++#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
++#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
++#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
++#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
++#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
++#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
++#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
++#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
++#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
++#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
++#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
++#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
++#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
++#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
++#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
++#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
++#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
++#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
++#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
++#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
++#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
++#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
++#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
++#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
++#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
++#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
++#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
++#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
++#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
++#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
++#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
++#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
++#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
++#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
++#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
++#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
++#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
++#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
++#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
++#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
++#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
++#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
++#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
++#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
++#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
++#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
++#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
++#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
++#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
++#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
++#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
++#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
++#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
++#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
++#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
++#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
++#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
++#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
++#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
++#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
++#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
++#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
++#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
++#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
++#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
++#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
++#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
++#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
++#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
++#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
++#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
++#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
++#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
++#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
++#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
++#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
++#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
++#define MC_XPB_STICKY__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY__BITS__SHIFT 0x0
++#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
++#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
++#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
++#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
++#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
++#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
++#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
++#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
++#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
++#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
++#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
++#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
++#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
++#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
++#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
++#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
++#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
++#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
++#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
++#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
++#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
++#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
++#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
++#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
++#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
++#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
++#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
++#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
++#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
++#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
++#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00
++#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
++#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
++#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
++#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff
++#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0
++#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00
++#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8
++#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000
++#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10
++#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000
++#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18
++#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff
++#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0
++#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff
++#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0
++#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00
++#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8
++#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000
++#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10
++#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000
++#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18
++#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
++#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1
++#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
++#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
++#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
++#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
++#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
++#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
++#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
++#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
++#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
++#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
++#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
++#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
++#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
++#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
++#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
++#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
++#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
++#define ATC_ATS_STATUS__BUSY_MASK 0x1
++#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
++#define ATC_ATS_STATUS__CRASHED_MASK 0x2
++#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
++#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c
++#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2
++#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
++#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
++#define ATC_MISC_CG__ENABLE_MASK 0x40000
++#define ATC_MISC_CG__ENABLE__SHIFT 0x12
++#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
++#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
++#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
++#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
++#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
++#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
++#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
++#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1RD_STATUS__BUSY_MASK 0x1
++#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_L1WR_STATUS__BUSY_MASK 0x1
++#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
++#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
++#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
++#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
++#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
++#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
++#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
++#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
++#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
++#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
++#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
++#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
++#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
++#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
++#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
++#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
++#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
++#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
++#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
++#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
++#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
++#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
++#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
++#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
++#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
++#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
++#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
++#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
++#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
++#define GMCON_DEBUG__GFX_STALL_MASK 0x1
++#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
++#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
++#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
++#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc
++#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2
++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
++#define VM_L2_STATUS__L2_BUSY_MASK 0x1
++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
++#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
++#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_DEBUG__FLAGS_MASK 0xffffffff
++#define VM_DEBUG__FLAGS__SHIFT 0x0
++#define VM_L2_CG__OFFDLY_MASK 0xfc0
++#define VM_L2_CG__OFFDLY__SHIFT 0x6
++#define VM_L2_CG__ENABLE_MASK 0x40000
++#define VM_L2_CG__ENABLE__SHIFT 0x12
++#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
++#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x1ff
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2
++#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30
++#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4
++#define MC_SEQ_CNTL__DAT_INV_MASK 0x40
++#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6
++#define MC_SEQ_CNTL__MSK_DF1_MASK 0x80
++#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7
++#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300
++#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8
++#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000
++#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe
++#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000
++#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf
++#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000
++#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10
++#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000
++#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11
++#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000
++#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12
++#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000
++#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13
++#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000
++#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14
++#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000
++#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18
++#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000
++#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c
++#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf
++#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0
++#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
++#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4
++#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20
++#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5
++#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300
++#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8
++#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00
++#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa
++#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000
++#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c
++#define MC_SEQ_DRAM__ADR_2CK_MASK 0x1
++#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0
++#define MC_SEQ_DRAM__ADR_MUX_MASK 0x2
++#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1
++#define MC_SEQ_DRAM__ADR_DF1_MASK 0x4
++#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2
++#define MC_SEQ_DRAM__AP8_MASK 0x8
++#define MC_SEQ_DRAM__AP8__SHIFT 0x3
++#define MC_SEQ_DRAM__DAT_DF1_MASK 0x10
++#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4
++#define MC_SEQ_DRAM__DQS_DF1_MASK 0x20
++#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5
++#define MC_SEQ_DRAM__DQM_DF1_MASK 0x40
++#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6
++#define MC_SEQ_DRAM__DQM_ACT_MASK 0x80
++#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7
++#define MC_SEQ_DRAM__STB_CNT_MASK 0xf00
++#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8
++#define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000
++#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc
++#define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000
++#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd
++#define MC_SEQ_DRAM__BO4_MASK 0x4000
++#define MC_SEQ_DRAM__BO4__SHIFT 0xe
++#define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000
++#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf
++#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000
++#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10
++#define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000
++#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18
++#define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000
++#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19
++#define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000
++#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a
++#define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000
++#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b
++#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000
++#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c
++#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000
++#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d
++#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000
++#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e
++#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000
++#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f
++#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1
++#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0
++#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2
++#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1
++#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4
++#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2
++#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8
++#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3
++#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10
++#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4
++#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20
++#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5
++#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40
++#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6
++#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80
++#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7
++#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100
++#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8
++#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200
++#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9
++#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400
++#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa
++#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800
++#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb
++#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000
++#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc
++#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000
++#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd
++#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000
++#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe
++#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000
++#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf
++#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000
++#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10
++#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000
++#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18
++#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000
++#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19
++#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000
++#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a
++#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000
++#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b
++#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000
++#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c
++#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000
++#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d
++#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000
++#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e
++#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000
++#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f
++#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f
++#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0
++#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0
++#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5
++#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00
++#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa
++#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000
++#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf
++#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000
++#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14
++#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000
++#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18
++#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3
++#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0
++#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc
++#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2
++#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0
++#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4
++#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00
++#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9
++#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000
++#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc
++#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000
++#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10
++#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000
++#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18
++#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f
++#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00
++#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000
++#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
++#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000
++#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
++#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7
++#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70
++#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4
++#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00
++#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000
++#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd
++#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000
++#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10
++#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000
++#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15
++#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000
++#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c
++#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7
++#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0
++#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70
++#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8
++#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000
++#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18
++#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5
++#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40
++#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6
++#define MC_SEQ_CMD__ADR_MASK 0xffff
++#define MC_SEQ_CMD__ADR__SHIFT 0x0
++#define MC_SEQ_CMD__MOP_MASK 0xf0000
++#define MC_SEQ_CMD__MOP__SHIFT 0x10
++#define MC_SEQ_CMD__END_MASK 0x100000
++#define MC_SEQ_CMD__END__SHIFT 0x14
++#define MC_SEQ_CMD__CSB_MASK 0x600000
++#define MC_SEQ_CMD__CSB__SHIFT 0x15
++#define MC_SEQ_CMD__CHAN0_MASK 0x1000000
++#define MC_SEQ_CMD__CHAN0__SHIFT 0x18
++#define MC_SEQ_CMD__CHAN1_MASK 0x2000000
++#define MC_SEQ_CMD__CHAN1__SHIFT 0x19
++#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff
++#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0
++#define MC_PMG_CMD_EMRS__MOP_MASK 0x70000
++#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10
++#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_EMRS__END_MASK 0x100000
++#define MC_PMG_CMD_EMRS__END__SHIFT 0x14
++#define MC_PMG_CMD_EMRS__CSB_MASK 0x600000
++#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15
++#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_MRS__ADR_MASK 0xffff
++#define MC_PMG_CMD_MRS__ADR__SHIFT 0x0
++#define MC_PMG_CMD_MRS__MOP_MASK 0x70000
++#define MC_PMG_CMD_MRS__MOP__SHIFT 0x10
++#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_MRS__END_MASK 0x100000
++#define MC_PMG_CMD_MRS__END__SHIFT 0x14
++#define MC_PMG_CMD_MRS__CSB_MASK 0x600000
++#define MC_PMG_CMD_MRS__CSB__SHIFT 0x15
++#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff
++#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0
++#define MC_PMG_CMD_MRS1__MOP_MASK 0x70000
++#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10
++#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_MRS1__END_MASK 0x100000
++#define MC_PMG_CMD_MRS1__END__SHIFT 0x14
++#define MC_PMG_CMD_MRS1__CSB_MASK 0x600000
++#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15
++#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff
++#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0
++#define MC_PMG_CMD_MRS2__MOP_MASK 0x70000
++#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10
++#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_MRS2__END_MASK 0x100000
++#define MC_PMG_CMD_MRS2__END__SHIFT 0x14
++#define MC_PMG_CMD_MRS2__CSB_MASK 0x600000
++#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15
++#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CFG__SYC_CLK_MASK 0x1
++#define MC_PMG_CFG__SYC_CLK__SHIFT 0x0
++#define MC_PMG_CFG__RST_MRS_MASK 0x2
++#define MC_PMG_CFG__RST_MRS__SHIFT 0x1
++#define MC_PMG_CFG__RST_EMRS_MASK 0x4
++#define MC_PMG_CFG__RST_EMRS__SHIFT 0x2
++#define MC_PMG_CFG__TRI_MIO_MASK 0x8
++#define MC_PMG_CFG__TRI_MIO__SHIFT 0x3
++#define MC_PMG_CFG__XSR_TMR_MASK 0xf0
++#define MC_PMG_CFG__XSR_TMR__SHIFT 0x4
++#define MC_PMG_CFG__RST_MRS1_MASK 0x100
++#define MC_PMG_CFG__RST_MRS1__SHIFT 0x8
++#define MC_PMG_CFG__RST_MRS2_MASK 0x200
++#define MC_PMG_CFG__RST_MRS2__SHIFT 0x9
++#define MC_PMG_CFG__DPM_WAKE_MASK 0x400
++#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa
++#define MC_PMG_CFG__RFS_SRX_MASK 0x1000
++#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc
++#define MC_PMG_CFG__PREA_SRX_MASK 0x2000
++#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd
++#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000
++#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10
++#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000
++#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
++#define MC_PMG_CFG__YCLK_ON_MASK 0x200000
++#define MC_PMG_CFG__YCLK_ON__SHIFT 0x15
++#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000
++#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16
++#define MC_PMG_CFG__RXPDNB_MASK 0x2000000
++#define MC_PMG_CFG__RXPDNB__SHIFT 0x19
++#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000
++#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a
++#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff
++#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0
++#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1
++#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0
++#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2
++#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1
++#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4
++#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2
++#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0
++#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4
++#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100
++#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8
++#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200
++#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9
++#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400
++#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa
++#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800
++#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb
++#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000
++#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc
++#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000
++#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd
++#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000
++#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf
++#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000
++#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10
++#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000
++#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
++#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000
++#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15
++#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000
++#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17
++#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000
++#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18
++#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f
++#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0
++#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20
++#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5
++#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40
++#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6
++#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100
++#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8
++#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200
++#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9
++#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000
++#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd
++#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000
++#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10
++#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000
++#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d
++#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000
++#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e
++#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000
++#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f
++#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff
++#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0
++#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00
++#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8
++#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000
++#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10
++#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000
++#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c
++#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000
++#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d
++#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000
++#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e
++#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000
++#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f
++#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff
++#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0
++#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00
++#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8
++#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000
++#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10
++#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000
++#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18
++#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff
++#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0
++#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00
++#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
++#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000
++#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10
++#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000
++#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18
++#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff
++#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0
++#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
++#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8
++#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000
++#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc
++#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000
++#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd
++#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000
++#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe
++#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000
++#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf
++#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000
++#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10
++#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000
++#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14
++#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000
++#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15
++#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000
++#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18
++#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000
++#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10
++#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff
++#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f
++#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0
++#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0
++#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5
++#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00
++#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa
++#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000
++#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf
++#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff
++#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0
++#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00
++#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8
++#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000
++#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
++#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000
++#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18
++#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff
++#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0
++#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00
++#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
++#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000
++#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10
++#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000
++#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
++#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff
++#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf
++#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0
++#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00
++#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000
++#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc
++#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c
++#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000
++#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d
++#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000
++#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e
++#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1
++#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2
++#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1
++#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30
++#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100
++#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200
++#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9
++#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400
++#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa
++#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800
++#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb
++#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000
++#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10
++#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c
++#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff
++#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0
++#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000
++#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10
++#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff
++#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf
++#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0
++#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00
++#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000
++#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc
++#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c
++#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000
++#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d
++#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000
++#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e
++#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1
++#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2
++#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1
++#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30
++#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100
++#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200
++#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9
++#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400
++#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa
++#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800
++#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb
++#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000
++#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10
++#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c
++#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff
++#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
++#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000
++#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20
++#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000
++#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc
++#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000
++#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd
++#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000
++#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000
++#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17
++#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000
++#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b
++#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000
++#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e
++#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000
++#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f
++#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12
++#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000
++#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18
++#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000
++#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19
++#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
++#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d
++#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000
++#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0
++#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0
++#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc
++#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000
++#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18
++#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000
++#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19
++#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
++#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d
++#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20
++#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000
++#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc
++#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000
++#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd
++#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000
++#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000
++#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17
++#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000
++#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b
++#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000
++#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e
++#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000
++#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f
++#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12
++#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000
++#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18
++#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000
++#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19
++#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
++#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d
++#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000
++#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0
++#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0
++#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc
++#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000
++#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18
++#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000
++#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19
++#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
++#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d
++#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf
++#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0
++#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0
++#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4
++#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100
++#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8
++#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200
++#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19
++#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000
++#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a
++#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000
++#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7
++#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00
++#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8
++#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000
++#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc
++#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000
++#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10
++#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf
++#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0
++#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0
++#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4
++#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100
++#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8
++#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200
++#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19
++#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000
++#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a
++#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000
++#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7
++#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00
++#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8
++#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000
++#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc
++#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000
++#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0
++#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
++#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
++#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30
++#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4
++#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
++#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
++#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100
++#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8
++#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200
++#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa
++#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000
++#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc
++#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000
++#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10
++#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000
++#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12
++#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000
++#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14
++#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
++#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18
++#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000
++#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8
++#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000
++#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10
++#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000
++#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13
++#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000
++#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14
++#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000
++#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18
++#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000
++#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e
++#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000
++#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f
++#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4
++#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2
++#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8
++#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3
++#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10
++#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9
++#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400
++#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa
++#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800
++#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb
++#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000
++#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc
++#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000
++#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd
++#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000
++#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe
++#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000
++#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf
++#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000
++#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b
++#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000
++#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c
++#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000
++#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d
++#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000
++#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f
++#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1
++#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0
++#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2
++#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1
++#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4
++#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2
++#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8
++#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3
++#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10
++#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9
++#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400
++#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa
++#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800
++#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb
++#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000
++#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc
++#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000
++#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd
++#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000
++#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe
++#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000
++#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf
++#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000
++#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b
++#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000
++#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c
++#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000
++#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d
++#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000
++#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f
++#define MC_NPL_STATUS__D0_PDELAY_MASK 0x3
++#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0
++#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc
++#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2
++#define MC_NPL_STATUS__D0_PEARLY_MASK 0x10
++#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4
++#define MC_NPL_STATUS__D0_NEARLY_MASK 0x20
++#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5
++#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0
++#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6
++#define MC_NPL_STATUS__D1_NDELAY_MASK 0x300
++#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8
++#define MC_NPL_STATUS__D1_PEARLY_MASK 0x400
++#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa
++#define MC_NPL_STATUS__D1_NEARLY_MASK 0x800
++#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb
++#define MC_BIST_CMD_CNTL__RESET_MASK 0x1
++#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2
++#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8
++#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3
++#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0
++#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11
++#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000
++#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12
++#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000
++#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c
++#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000
++#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d
++#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000
++#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e
++#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000
++#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f
++#define MC_BIST_CNTL__RESET_MASK 0x1
++#define MC_BIST_CNTL__RESET__SHIFT 0x0
++#define MC_BIST_CNTL__RUN_MASK 0x2
++#define MC_BIST_CNTL__RUN__SHIFT 0x1
++#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4
++#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2
++#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8
++#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3
++#define MC_BIST_CNTL__MOP_MODE_MASK 0x10
++#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4
++#define MC_BIST_CNTL__ADR_MODE_MASK 0x20
++#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5
++#define MC_BIST_CNTL__DAT_MODE_MASK 0x40
++#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6
++#define MC_BIST_CNTL__LOOP_MASK 0xc00
++#define MC_BIST_CNTL__LOOP__SHIFT 0xa
++#define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000
++#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc
++#define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000
++#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd
++#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000
++#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe
++#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000
++#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10
++#define MC_BIST_CNTL__DONE_MASK 0x40000000
++#define MC_BIST_CNTL__DONE__SHIFT 0x1e
++#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000
++#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f
++#define MC_BIST_AUTO_CNTL__MOP_MASK 0x3
++#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0
++#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0
++#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4
++#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00
++#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8
++#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000
++#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18
++#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000
++#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19
++#define MC_BIST_DIR_CNTL__MOP_MASK 0x7
++#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0
++#define MC_BIST_DIR_CNTL__EOB_MASK 0x8
++#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3
++#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10
++#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4
++#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20
++#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5
++#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40
++#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6
++#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80
++#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7
++#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100
++#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8
++#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200
++#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9
++#define MC_BIST_DIR_CNTL__MOP3_MASK 0x400
++#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa
++#define MC_BIST_SADDR__COL_MASK 0x3ff
++#define MC_BIST_SADDR__COL__SHIFT 0x0
++#define MC_BIST_SADDR__ROW_MASK 0xfffc00
++#define MC_BIST_SADDR__ROW__SHIFT 0xa
++#define MC_BIST_SADDR__BANK_MASK 0xf000000
++#define MC_BIST_SADDR__BANK__SHIFT 0x18
++#define MC_BIST_SADDR__RANK_MASK 0x10000000
++#define MC_BIST_SADDR__RANK__SHIFT 0x1c
++#define MC_BIST_SADDR__COLH_MASK 0x20000000
++#define MC_BIST_SADDR__COLH__SHIFT 0x1d
++#define MC_BIST_SADDR__ROWH_MASK 0xc0000000
++#define MC_BIST_SADDR__ROWH__SHIFT 0x1e
++#define MC_BIST_EADDR__COL_MASK 0x3ff
++#define MC_BIST_EADDR__COL__SHIFT 0x0
++#define MC_BIST_EADDR__ROW_MASK 0xfffc00
++#define MC_BIST_EADDR__ROW__SHIFT 0xa
++#define MC_BIST_EADDR__BANK_MASK 0xf000000
++#define MC_BIST_EADDR__BANK__SHIFT 0x18
++#define MC_BIST_EADDR__RANK_MASK 0x10000000
++#define MC_BIST_EADDR__RANK__SHIFT 0x1c
++#define MC_BIST_EADDR__COLH_MASK 0x20000000
++#define MC_BIST_EADDR__COLH__SHIFT 0x1d
++#define MC_BIST_EADDR__ROWH_MASK 0xc0000000
++#define MC_BIST_EADDR__ROWH__SHIFT 0x1e
++#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf
++#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0
++#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0
++#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4
++#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000
++#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc
++#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000
++#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd
++#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000
++#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe
++#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000
++#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf
++#define MC_BIST_CMP_CNTL__CMP_MASK 0x30000
++#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10
++#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000
++#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12
++#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000
++#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13
++#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000
++#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14
++#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000
++#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14
++#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0
++#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff
++#define MC_BIST_DATA_MASK__MASK__SHIFT 0x0
++#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff
++#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0
++#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00
++#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa
++#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000
++#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18
++#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000
++#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c
++#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000
++#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d
++#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000
++#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e
++#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff
++#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0
++#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff
++#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0
++#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff
++#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0
++#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000
++#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e
++#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1
++#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0
++#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100
++#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8
++#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200
++#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf
++#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf
++#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0
++#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c
++#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1
++#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4
++#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
++#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8
++#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3
++#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10
++#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4
++#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20
++#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5
++#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40
++#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
++#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80
++#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
++#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100
++#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8
++#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200
++#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9
++#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000
++#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc
++#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000
++#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd
++#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000
++#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe
++#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000
++#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf
++#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000
++#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10
++#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000
++#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14
++#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000
++#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19
++#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000
++#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a
++#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000
++#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b
++#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000
++#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c
++#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1
++#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0
++#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2
++#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1
++#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10
++#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4
++#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20
++#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5
++#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100
++#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8
++#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200
++#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9
++#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
++#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
++#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC0__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC1__VALUE__SHIFT 0x0
++#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL_MASK 0x1
++#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL__SHIFT 0x0
++#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xfffffffe
++#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x1
++#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff
++#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0
++#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff
++#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0
++#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff
++#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0
++#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000
++#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc
++#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000
++#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18
++#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff
++#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0
++#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000
++#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
++#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000
++#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18
++#define MC_SEQ_SUP_CNTL__RUN_MASK 0x1
++#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0
++#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2
++#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1
++#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4
++#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2
++#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8
++#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3
++#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10
++#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4
++#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20
++#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5
++#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40
++#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6
++#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80
++#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7
++#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000
++#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17
++#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff
++#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0
++#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff
++#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0
++#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC3__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC4__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC5__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC6__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC7__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC8__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC9__VALUE__SHIFT 0x0
++#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff
++#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0
++#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00
++#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8
++#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000
++#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10
++#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000
++#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18
++#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3
++#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0
++#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc
++#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2
++#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30
++#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4
++#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0
++#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6
++#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3
++#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0
++#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc
++#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2
++#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30
++#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4
++#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0
++#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
++#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0
++#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
++#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5
++#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
++#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa
++#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
++#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf
++#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
++#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14
++#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
++#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18
++#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
++#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0
++#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
++#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2
++#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
++#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4
++#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
++#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9
++#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000
++#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
++#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000
++#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
++#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000
++#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
++#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
++#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
++#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
++#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
++#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
++#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
++#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7
++#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70
++#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4
++#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00
++#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000
++#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd
++#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000
++#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10
++#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000
++#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15
++#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000
++#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18
++#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000
++#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c
++#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5
++#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40
++#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7
++#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0
++#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70
++#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8
++#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000
++#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18
++#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff
++#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0
++#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff
++#define MC_SEQ_IO_REDC__EDC__SHIFT 0x0
++#define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
++#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0
++#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2
++#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1
++#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
++#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2
++#define MC_SEQ_TCG_CNTL__START_MASK 0x8
++#define MC_SEQ_TCG_CNTL__START__SHIFT 0x3
++#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70
++#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4
++#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80
++#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7
++#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00
++#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8
++#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000
++#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc
++#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000
++#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10
++#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000
++#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11
++#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000
++#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12
++#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000
++#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13
++#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000
++#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16
++#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000
++#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17
++#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000
++#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18
++#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000
++#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19
++#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000
++#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d
++#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000
++#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f
++#define MC_SEQ_TSM_CTRL__START_MASK 0x1
++#define MC_SEQ_TSM_CTRL__START__SHIFT 0x0
++#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2
++#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1
++#define MC_SEQ_TSM_CTRL__DONE_MASK 0x4
++#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2
++#define MC_SEQ_TSM_CTRL__ERR_MASK 0x8
++#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3
++#define MC_SEQ_TSM_CTRL__STEP_MASK 0x10
++#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4
++#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20
++#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5
++#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40
++#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6
++#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80
++#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7
++#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300
++#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8
++#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400
++#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa
++#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800
++#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb
++#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000
++#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc
++#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000
++#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd
++#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000
++#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10
++#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00
++#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000
++#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10
++#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00
++#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000
++#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10
++#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00
++#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000
++#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10
++#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000
++#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14
++#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000
++#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18
++#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00
++#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000
++#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10
++#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000
++#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18
++#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00
++#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000
++#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10
++#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000
++#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18
++#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00
++#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
++#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10
++#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000
++#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18
++#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff
++#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0
++#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff
++#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0
++#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff
++#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0
++#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff
++#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0
++#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000
++#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10
++#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000
++#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14
++#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000
++#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a
++#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff
++#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0
++#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff
++#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0
++#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff
++#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0
++#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000
++#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10
++#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf
++#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0
++#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0
++#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4
++#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00
++#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8
++#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000
++#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc
++#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000
++#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10
++#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000
++#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14
++#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000
++#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18
++#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000
++#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c
++#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf
++#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0
++#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0
++#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4
++#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00
++#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8
++#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000
++#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc
++#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
++#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10
++#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000
++#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14
++#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000
++#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18
++#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000
++#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c
++#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f
++#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0
++#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100
++#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8
++#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200
++#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9
++#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400
++#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa
++#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800
++#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb
++#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000
++#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc
++#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000
++#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd
++#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000
++#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe
++#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000
++#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf
++#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000
++#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10
++#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000
++#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11
++#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000
++#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12
++#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000
++#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13
++#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000
++#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14
++#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000
++#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18
++#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000
++#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19
++#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1
++#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4
++#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20
++#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7
++#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f
++#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0
++#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40
++#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6
++#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80
++#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7
++#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100
++#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8
++#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200
++#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9
++#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000
++#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10
++#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000
++#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11
++#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000
++#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18
++#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff
++#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0
++#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000
++#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc
++#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000
++#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18
++#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000
++#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19
++#define DLL_CNTL__PWR2_MODE_MASK 0x4000000
++#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a
++#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf
++#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0
++#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0
++#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4
++#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00
++#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8
++#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000
++#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc
++#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000
++#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
++#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000
++#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
++#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000
++#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18
++#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000
++#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c
++#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf
++#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0
++#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0
++#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4
++#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00
++#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8
++#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000
++#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc
++#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000
++#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10
++#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000
++#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14
++#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000
++#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18
++#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000
++#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c
++#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff
++#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0
++#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100
++#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8
++#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800
++#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb
++#define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000
++#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc
++#define MPLL_CNTL_MODE__QDR_MASK 0x2000
++#define MPLL_CNTL_MODE__QDR__SHIFT 0xd
++#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000
++#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe
++#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000
++#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10
++#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000
++#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11
++#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000
++#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14
++#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000
++#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15
++#define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000
++#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17
++#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000
++#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18
++#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000
++#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a
++#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000
++#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b
++#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000
++#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c
++#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000
++#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f
++#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20
++#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5
++#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00
++#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8
++#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000
++#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10
++#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000
++#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14
++#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000
++#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e
++#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3
++#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0
++#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc
++#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2
++#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0
++#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4
++#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000
++#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10
++#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000
++#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c
++#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1
++#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1
++#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4
++#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5
++#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40
++#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6
++#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80
++#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9
++#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00
++#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa
++#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000
++#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc
++#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000
++#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe
++#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000
++#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf
++#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000
++#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10
++#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000
++#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11
++#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000
++#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14
++#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000
++#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b
++#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
++#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
++#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8
++#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3
++#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
++#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
++#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8
++#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3
++#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10
++#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4
++#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0
++#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5
++#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff
++#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0
++#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000
++#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10
++#define MPLL_SS1__CLKV_MASK 0x3ffffff
++#define MPLL_SS1__CLKV__SHIFT 0x0
++#define MPLL_SS1__SPARE_MASK 0xfc000000
++#define MPLL_SS1__SPARE__SHIFT 0x1a
++#define MPLL_SS2__CLKS_MASK 0xfff
++#define MPLL_SS2__CLKS__SHIFT 0x0
++#define MPLL_SS2__SPARE_MASK 0xfffff000
++#define MPLL_SS2__SPARE__SHIFT 0xc
++#define MPLL_CONTROL__GDDR_PWRON_MASK 0x1
++#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0
++#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2
++#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1
++#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4
++#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2
++#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000
++#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc
++#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000
++#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd
++#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000
++#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe
++#define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000
++#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf
++#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000
++#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
++#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000
++#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11
++#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000
++#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12
++#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000
++#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13
++#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000
++#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14
++#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000
++#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
++#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000
++#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
++#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000
++#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17
++#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000
++#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18
++#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000
++#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
++#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000
++#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
++#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000
++#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b
++#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000
++#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c
++#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000
++#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d
++#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000
++#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
++#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000
++#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f
++#define MPLL_AD_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1
++#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0
++#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2
++#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1
++#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c
++#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2
++#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0
++#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6
++#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300
++#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8
++#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00
++#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa
++#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000
++#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10
++#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000
++#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11
++#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000
++#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000
++#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000
++#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f
++#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f
++#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0
++#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff
++#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff
++#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0
++#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00
++#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8
++#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000
++#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc
++#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0
++#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff
++#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0
++#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff
++#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0
++#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9
++#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000
++#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc
++#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000
++#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd
++#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000
++#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10
++#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000
++#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14
++#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000
++#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15
++#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000
++#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16
++#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000
++#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17
++#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000
++#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18
++#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000
++#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e
++#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000
++#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f
++#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
++#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0
++#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2
++#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3
++#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0
++#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4
++#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
++#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc
++#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000
++#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10
++#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000
++#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14
++#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1
++#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0
++#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2
++#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3
++#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0
++#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4
++#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000
++#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc
++#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000
++#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10
++#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000
++#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14
++#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0
++#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0
++#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0
++#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0
++#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff
++#define MC_SEQ_SREG_READ__DATA__SHIFT 0x0
++#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf
++#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0
++#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00
++#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8
++#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000
++#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc
++#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1
++#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0
++#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2
++#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1
++#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80
++#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7
++#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100
++#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8
++#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200
++#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9
++#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400
++#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa
++#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800
++#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb
++#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000
++#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc
++#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000
++#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd
++#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000
++#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe
++#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000
++#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf
++#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1
++#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e
++#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1
++#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1
++#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e
++#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1
++#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff
++#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000
++#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000
++#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14
++#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000
++#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18
++#define MC_SEQ_DLL_STBY__EN_MASK 0x1
++#define MC_SEQ_DLL_STBY__EN__SHIFT 0x0
++#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2
++#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1
++#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4
++#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2
++#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8
++#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3
++#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10
++#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4
++#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0
++#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5
++#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00
++#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8
++#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000
++#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc
++#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000
++#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10
++#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000
++#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18
++#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1
++#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4
++#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0
++#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5
++#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00
++#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8
++#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000
++#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc
++#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000
++#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10
++#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000
++#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18
++#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1
++#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0
++#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2
++#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1
++#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4
++#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2
++#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8
++#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3
++#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0
++#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4
++#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00
++#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8
++#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000
++#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10
++#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff
++#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0
++#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff
++#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0
++#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000
++#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11
++#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000
++#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12
++#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000
++#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13
++#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000
++#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14
++#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000
++#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15
++#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000
++#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18
++#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000
++#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a
++#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000
++#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c
++#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000
++#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d
++#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
++#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e
++#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1
++#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0
++#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2
++#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1
++#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4
++#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2
++#define MC_DLB_CONFIG0__MASK_MASK 0xf0
++#define MC_DLB_CONFIG0__MASK__SHIFT 0x4
++#define MC_DLB_CONFIG0__PTR_MASK 0x3ff00
++#define MC_DLB_CONFIG0__PTR__SHIFT 0x8
++#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff
++#define MC_DLB_CONFIG1__DATA__SHIFT 0x0
++#define MC_DLB_SETUP__DLB_EN_MASK 0x1
++#define MC_DLB_SETUP__DLB_EN__SHIFT 0x0
++#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2
++#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1
++#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4
++#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2
++#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8
++#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3
++#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10
++#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4
++#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20
++#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5
++#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40
++#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6
++#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80
++#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7
++#define MC_DLB_SETUP__QDR_MODE_MASK 0x100
++#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8
++#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000
++#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10
++#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000
++#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18
++#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000
++#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f
++#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1
++#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0
++#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2
++#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1
++#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4
++#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2
++#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0
++#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4
++#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00
++#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8
++#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1
++#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0
++#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2
++#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1
++#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4
++#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2
++#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8
++#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3
++#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30
++#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4
++#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40
++#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6
++#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300
++#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8
++#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00
++#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa
++#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000
++#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10
++#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff
++#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0
++#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000
++#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18
++#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf
++#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0
++#define MC_DLB_STATUS__LOCK_MASK 0xf0
++#define MC_DLB_STATUS__LOCK__SHIFT 0x4
++#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00
++#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8
++#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
++
++#endif /* GMC_7_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0012-yocto-amd-drm-amdgpu-add-atombios-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0012-yocto-amd-drm-amdgpu-add-atombios-headers.patch
new file mode 100644
index 00000000..3d4a9906
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0012-yocto-amd-drm-amdgpu-add-atombios-headers.patch
@@ -0,0 +1,18620 @@
+From ae0942d5e635b98a9dc437ca90c2984772e9211c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:24:04 -0400
+Subject: drm/amdgpu: add GMC 8.1 register headers
+
+These are register headers for the GMC (Graphics Memory Controller)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h
+new file mode 100644
+index 0000000..8c2412e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h
+@@ -0,0 +1,1708 @@
++/*
++ * GMC_8_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_8_1_D_H
++#define GMC_8_1_D_H
++
++#define mmMC_CONFIG                                                             0x800
++#define mmMC_ARB_ATOMIC                                                         0x9be
++#define mmMC_ARB_AGE_CNTL                                                       0x9bf
++#define mmMC_ARB_RET_CREDITS2                                                   0x9c0
++#define mmMC_ARB_FED_CNTL                                                       0x9c1
++#define mmMC_ARB_GECC2_STATUS                                                   0x9c2
++#define mmMC_ARB_GECC2_MISC                                                     0x9c3
++#define mmMC_ARB_GECC2_DEBUG                                                    0x9c4
++#define mmMC_ARB_GECC2_DEBUG2                                                   0x9c5
++#define mmMC_ARB_PERF_CID                                                       0x9c6
++#define mmMC_ARB_SNOOP                                                          0x9c7
++#define mmMC_ARB_GRUB                                                           0x9c8
++#define mmMC_ARB_GECC2                                                          0x9c9
++#define mmMC_ARB_GECC2_CLI                                                      0x9ca
++#define mmMC_ARB_ADDR_SWIZ0                                                     0x9cb
++#define mmMC_ARB_ADDR_SWIZ1                                                     0x9cc
++#define mmMC_ARB_MISC3                                                          0x9cd
++#define mmMC_ARB_GRUB_PROMOTE                                                   0x9ce
++#define mmMC_ARB_RTT_DATA                                                       0x9cf
++#define mmMC_ARB_RTT_CNTL0                                                      0x9d0
++#define mmMC_ARB_RTT_CNTL1                                                      0x9d1
++#define mmMC_ARB_RTT_CNTL2                                                      0x9d2
++#define mmMC_ARB_RTT_DEBUG                                                      0x9d3
++#define mmMC_ARB_CAC_CNTL                                                       0x9d4
++#define mmMC_ARB_MISC2                                                          0x9d5
++#define mmMC_ARB_MISC                                                           0x9d6
++#define mmMC_ARB_BANKMAP                                                        0x9d7
++#define mmMC_ARB_RAMCFG                                                         0x9d8
++#define mmMC_ARB_POP                                                            0x9d9
++#define mmMC_ARB_MINCLKS                                                        0x9da
++#define mmMC_ARB_SQM_CNTL                                                       0x9db
++#define mmMC_ARB_ADDR_HASH                                                      0x9dc
++#define mmMC_ARB_DRAM_TIMING                                                    0x9dd
++#define mmMC_ARB_DRAM_TIMING2                                                   0x9de
++#define mmMC_ARB_WTM_CNTL_RD                                                    0x9df
++#define mmMC_ARB_WTM_CNTL_WR                                                    0x9e0
++#define mmMC_ARB_WTM_GRPWT_RD                                                   0x9e1
++#define mmMC_ARB_WTM_GRPWT_WR                                                   0x9e2
++#define mmMC_ARB_TM_CNTL_RD                                                     0x9e3
++#define mmMC_ARB_TM_CNTL_WR                                                     0x9e4
++#define mmMC_ARB_LAZY0_RD                                                       0x9e5
++#define mmMC_ARB_LAZY0_WR                                                       0x9e6
++#define mmMC_ARB_LAZY1_RD                                                       0x9e7
++#define mmMC_ARB_LAZY1_WR                                                       0x9e8
++#define mmMC_ARB_AGE_RD                                                         0x9e9
++#define mmMC_ARB_AGE_WR                                                         0x9ea
++#define mmMC_ARB_RFSH_CNTL                                                      0x9eb
++#define mmMC_ARB_RFSH_RATE                                                      0x9ec
++#define mmMC_ARB_PM_CNTL                                                        0x9ed
++#define mmMC_ARB_GDEC_RD_CNTL                                                   0x9ee
++#define mmMC_ARB_GDEC_WR_CNTL                                                   0x9ef
++#define mmMC_ARB_LM_RD                                                          0x9f0
++#define mmMC_ARB_LM_WR                                                          0x9f1
++#define mmMC_ARB_REMREQ                                                         0x9f2
++#define mmMC_ARB_REPLAY                                                         0x9f3
++#define mmMC_ARB_RET_CREDITS_RD                                                 0x9f4
++#define mmMC_ARB_RET_CREDITS_WR                                                 0x9f5
++#define mmMC_ARB_MAX_LAT_CID                                                    0x9f6
++#define mmMC_ARB_MAX_LAT_RSLT0                                                  0x9f7
++#define mmMC_ARB_MAX_LAT_RSLT1                                                  0x9f8
++#define mmMC_ARB_GRUB_REALTIME_RD                                               0x9f9
++#define mmMC_ARB_CG                                                             0x9fa
++#define mmMC_ARB_GRUB_REALTIME_WR                                               0x9fb
++#define mmMC_ARB_DRAM_TIMING_1                                                  0x9fc
++#define mmMC_ARB_BUSY_STATUS                                                    0x9fd
++#define mmMC_ARB_DRAM_TIMING2_1                                                 0x9ff
++#define mmMC_ARB_GRUB2                                                          0xa01
++#define mmMC_ARB_BURST_TIME                                                     0xa02
++#define mmMC_CITF_XTRA_ENABLE                                                   0x96d
++#define mmCC_MC_MAX_CHANNEL                                                     0x96e
++#define mmMC_CG_CONFIG                                                          0x96f
++#define mmMC_CITF_CNTL                                                          0x970
++#define mmMC_CITF_CREDITS_VM                                                    0x971
++#define mmMC_CITF_CREDITS_ARB_RD                                                0x972
++#define mmMC_CITF_CREDITS_ARB_WR                                                0x973
++#define mmMC_CITF_DAGB_CNTL                                                     0x974
++#define mmMC_CITF_INT_CREDITS                                                   0x975
++#define mmMC_CITF_RET_MODE                                                      0x976
++#define mmMC_CITF_DAGB_DLY                                                      0x977
++#define mmMC_RD_GRP_EXT                                                         0x978
++#define mmMC_WR_GRP_EXT                                                         0x979
++#define mmMC_CITF_REMREQ                                                        0x97a
++#define mmMC_WR_TC0                                                             0x97b
++#define mmMC_WR_TC1                                                             0x97c
++#define mmMC_CITF_INT_CREDITS_WR                                                0x97d
++#define mmMC_CITF_CREDITS_ARB_RD2                                               0x97e
++#define mmMC_CITF_WTM_RD_CNTL                                                   0x97f
++#define mmMC_CITF_WTM_WR_CNTL                                                   0x980
++#define mmMC_RD_CB                                                              0x981
++#define mmMC_RD_DB                                                              0x982
++#define mmMC_RD_TC0                                                             0x983
++#define mmMC_RD_TC1                                                             0x984
++#define mmMC_RD_HUB                                                             0x985
++#define mmMC_WR_CB                                                              0x986
++#define mmMC_WR_DB                                                              0x987
++#define mmMC_WR_HUB                                                             0x988
++#define mmMC_CITF_CREDITS_XBAR                                                  0x989
++#define mmMC_RD_GRP_LCL                                                         0x98a
++#define mmMC_WR_GRP_LCL                                                         0x98b
++#define mmMC_CITF_PERF_MON_CNTL2                                                0x98e
++#define mmMC_CITF_PERF_MON_RSLT2                                                0x991
++#define mmMC_CITF_MISC_RD_CG                                                    0x992
++#define mmMC_CITF_MISC_WR_CG                                                    0x993
++#define mmMC_CITF_MISC_VM_CG                                                    0x994
++#define mmMC_HUB_MISC_POWER                                                     0x82d
++#define mmMC_HUB_MISC_HUB_CG                                                    0x82e
++#define mmMC_HUB_MISC_VM_CG                                                     0x82f
++#define mmMC_HUB_MISC_SIP_CG                                                    0x830
++#define mmMC_HUB_MISC_STATUS                                                    0x832
++#define mmMC_HUB_MISC_OVERRIDE                                                  0x833
++#define mmMC_HUB_MISC_FRAMING                                                   0x834
++#define mmMC_HUB_WDP_CNTL                                                       0x835
++#define mmMC_HUB_WDP_ERR                                                        0x836
++#define mmMC_HUB_WDP_BP                                                         0x837
++#define mmMC_HUB_WDP_STATUS                                                     0x838
++#define mmMC_HUB_RDREQ_STATUS                                                   0x839
++#define mmMC_HUB_WRRET_STATUS                                                   0x83a
++#define mmMC_HUB_RDREQ_CNTL                                                     0x83b
++#define mmMC_HUB_WRRET_CNTL                                                     0x83c
++#define mmMC_HUB_RDREQ_WTM_CNTL                                                 0x83d
++#define mmMC_HUB_WDP_WTM_CNTL                                                   0x83e
++#define mmMC_HUB_WDP_CREDITS                                                    0x83f
++#define mmMC_HUB_WDP_CREDITS2                                                   0x840
++#define mmMC_HUB_WDP_GBL0                                                       0x841
++#define mmMC_HUB_WDP_GBL1                                                       0x842
++#define mmMC_HUB_WDP_CREDITS3                                                   0x843
++#define mmMC_HUB_RDREQ_CREDITS                                                  0x844
++#define mmMC_HUB_RDREQ_CREDITS2                                                 0x845
++#define mmMC_HUB_SHARED_DAGB_DLY                                                0x846
++#define mmMC_HUB_MISC_IDLE_STATUS                                               0x847
++#define mmMC_HUB_RDREQ_DMIF_LIMIT                                               0x848
++#define mmMC_HUB_RDREQ_ACPG_LIMIT                                               0x849
++#define mmMC_HUB_WDP_BYPASS_GBL0                                                0x84a
++#define mmMC_HUB_WDP_BYPASS_GBL1                                                0x84b
++#define mmMC_HUB_RDREQ_BYPASS_GBL0                                              0x84c
++#define mmMC_HUB_WDP_SH2                                                        0x84d
++#define mmMC_HUB_WDP_SH3                                                        0x84e
++#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS                                        0x84f
++#define mmMC_HUB_WDP_VIN0                                                       0x850
++#define mmMC_HUB_RDREQ_MCDW                                                     0x851
++#define mmMC_HUB_RDREQ_MCDX                                                     0x852
++#define mmMC_HUB_RDREQ_MCDY                                                     0x853
++#define mmMC_HUB_RDREQ_MCDZ                                                     0x854
++#define mmMC_HUB_RDREQ_SIP                                                      0x855
++#define mmMC_HUB_RDREQ_GBL0                                                     0x856
++#define mmMC_HUB_RDREQ_GBL1                                                     0x857
++#define mmMC_HUB_RDREQ_SMU                                                      0x858
++#define mmMC_HUB_RDREQ_SDMA0                                                    0x859
++#define mmMC_HUB_RDREQ_HDP                                                      0x85a
++#define mmMC_HUB_RDREQ_SDMA1                                                    0x85b
++#define mmMC_HUB_RDREQ_RLC                                                      0x85c
++#define mmMC_HUB_RDREQ_SEM                                                      0x85d
++#define mmMC_HUB_RDREQ_VCE0                                                     0x85e
++#define mmMC_HUB_RDREQ_UMC                                                      0x85f
++#define mmMC_HUB_RDREQ_UVD                                                      0x860
++#define mmMC_HUB_RDREQ_TLS                                                      0x861
++#define mmMC_HUB_RDREQ_DMIF                                                     0x862
++#define mmMC_HUB_RDREQ_MCIF                                                     0x863
++#define mmMC_HUB_RDREQ_VMC                                                      0x864
++#define mmMC_HUB_RDREQ_VCEU0                                                    0x865
++#define mmMC_HUB_WDP_MCDW                                                       0x866
++#define mmMC_HUB_WDP_MCDX                                                       0x867
++#define mmMC_HUB_WDP_MCDY                                                       0x868
++#define mmMC_HUB_WDP_MCDZ                                                       0x869
++#define mmMC_HUB_WDP_SIP                                                        0x86a
++#define mmMC_HUB_WDP_SDMA1                                                      0x86b
++#define mmMC_HUB_WDP_SH0                                                        0x86c
++#define mmMC_HUB_WDP_MCIF                                                       0x86d
++#define mmMC_HUB_WDP_VCE0                                                       0x86e
++#define mmMC_HUB_WDP_XDP                                                        0x86f
++#define mmMC_HUB_WDP_IH                                                         0x870
++#define mmMC_HUB_WDP_RLC                                                        0x871
++#define mmMC_HUB_WDP_SEM                                                        0x872
++#define mmMC_HUB_WDP_SMU                                                        0x873
++#define mmMC_HUB_WDP_SH1                                                        0x874
++#define mmMC_HUB_WDP_UMC                                                        0x875
++#define mmMC_HUB_WDP_UVD                                                        0x876
++#define mmMC_HUB_WDP_HDP                                                        0x877
++#define mmMC_HUB_WDP_SDMA0                                                      0x878
++#define mmMC_HUB_WRRET_MCDW                                                     0x879
++#define mmMC_HUB_WRRET_MCDX                                                     0x87a
++#define mmMC_HUB_WRRET_MCDY                                                     0x87b
++#define mmMC_HUB_WRRET_MCDZ                                                     0x87c
++#define mmMC_HUB_WDP_VCEU0                                                      0x87d
++#define mmMC_HUB_WDP_XDMAM                                                      0x87e
++#define mmMC_HUB_WDP_XDMA                                                       0x87f
++#define mmMC_HUB_RDREQ_XDMAM                                                    0x880
++#define mmMC_HUB_RDREQ_ACPG                                                     0x881
++#define mmMC_HUB_RDREQ_ACPO                                                     0x882
++#define mmMC_HUB_RDREQ_SAMMSP                                                   0x883
++#define mmMC_HUB_RDREQ_VP8                                                      0x884
++#define mmMC_HUB_RDREQ_VP8U                                                     0x885
++#define mmMC_HUB_WDP_ACPG                                                       0x886
++#define mmMC_HUB_WDP_ACPO                                                       0x887
++#define mmMC_HUB_WDP_SAMMSP                                                     0x888
++#define mmMC_HUB_WDP_VP8                                                        0x889
++#define mmMC_HUB_WDP_VP8U                                                       0x88a
++#define mmMC_HUB_RDREQ_ISP_SPM                                                  0xde0
++#define mmMC_HUB_RDREQ_ISP_MPM                                                  0xde1
++#define mmMC_HUB_RDREQ_ISP_CCPU                                                 0xde2
++#define mmMC_HUB_WDP_ISP_SPM                                                    0xde3
++#define mmMC_HUB_WDP_ISP_MPS                                                    0xde4
++#define mmMC_HUB_WDP_ISP_MPM                                                    0xde5
++#define mmMC_HUB_WDP_ISP_CCPU                                                   0xde6
++#define mmMC_HUB_RDREQ_MCDS                                                     0xde7
++#define mmMC_HUB_RDREQ_MCDT                                                     0xde8
++#define mmMC_HUB_RDREQ_MCDU                                                     0xde9
++#define mmMC_HUB_RDREQ_MCDV                                                     0xdea
++#define mmMC_HUB_WDP_MCDS                                                       0xdeb
++#define mmMC_HUB_WDP_MCDT                                                       0xdec
++#define mmMC_HUB_WDP_MCDU                                                       0xded
++#define mmMC_HUB_WDP_MCDV                                                       0xdee
++#define mmMC_HUB_WRRET_MCDS                                                     0xdef
++#define mmMC_HUB_WRRET_MCDT                                                     0xdf0
++#define mmMC_HUB_WRRET_MCDU                                                     0xdf1
++#define mmMC_HUB_WRRET_MCDV                                                     0xdf2
++#define mmMC_HUB_WDP_CREDITS_MCDW                                               0xdf3
++#define mmMC_HUB_WDP_CREDITS_MCDX                                               0xdf4
++#define mmMC_HUB_WDP_CREDITS_MCDY                                               0xdf5
++#define mmMC_HUB_WDP_CREDITS_MCDZ                                               0xdf6
++#define mmMC_HUB_WDP_CREDITS_MCDS                                               0xdf7
++#define mmMC_HUB_WDP_CREDITS_MCDT                                               0xdf8
++#define mmMC_HUB_WDP_CREDITS_MCDU                                               0xdf9
++#define mmMC_HUB_WDP_CREDITS_MCDV                                               0xdfa
++#define mmMC_HUB_WDP_BP2                                                        0xdfb
++#define mmMC_HUB_RDREQ_VCE1                                                     0xdfc
++#define mmMC_HUB_RDREQ_VCEU1                                                    0xdfd
++#define mmMC_HUB_WDP_VCE1                                                       0xdfe
++#define mmMC_HUB_WDP_VCEU1                                                      0xdff
++#define mmMC_RPB_CONF                                                           0x94d
++#define mmMC_RPB_IF_CONF                                                        0x94e
++#define mmMC_RPB_DBG1                                                           0x94f
++#define mmMC_RPB_EFF_CNTL                                                       0x950
++#define mmMC_RPB_ARB_CNTL                                                       0x951
++#define mmMC_RPB_BIF_CNTL                                                       0x952
++#define mmMC_RPB_WR_SWITCH_CNTL                                                 0x953
++#define mmMC_RPB_WR_COMBINE_CNTL                                                0x954
++#define mmMC_RPB_RD_SWITCH_CNTL                                                 0x955
++#define mmMC_RPB_CID_QUEUE_WR                                                   0x956
++#define mmMC_RPB_CID_QUEUE_RD                                                   0x957
++#define mmMC_RPB_PERF_COUNTER_CNTL                                              0x958
++#define mmMC_RPB_PERF_COUNTER_STATUS                                            0x959
++#define mmMC_RPB_CID_QUEUE_EX                                                   0x95a
++#define mmMC_RPB_CID_QUEUE_EX_DATA                                              0x95b
++#define mmMC_RPB_TCI_CNTL                                                       0x95c
++#define mmMC_RPB_TCI_CNTL2                                                      0x95d
++#define mmMC_SHARED_CHMAP                                                       0x801
++#define mmMC_SHARED_CHREMAP                                                     0x802
++#define mmMC_RD_GRP_GFX                                                         0x803
++#define mmMC_WR_GRP_GFX                                                         0x804
++#define mmMC_RD_GRP_SYS                                                         0x805
++#define mmMC_WR_GRP_SYS                                                         0x806
++#define mmMC_RD_GRP_OTH                                                         0x807
++#define mmMC_WR_GRP_OTH                                                         0x808
++#define mmMC_VM_FB_LOCATION                                                     0x809
++#define mmMC_VM_AGP_TOP                                                         0x80a
++#define mmMC_VM_AGP_BOT                                                         0x80b
++#define mmMC_VM_AGP_BASE                                                        0x80c
++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR                                        0x80d
++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                       0x80e
++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR                                    0x80f
++#define mmMC_VM_DC_WRITE_CNTL                                                   0x810
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR                                  0x811
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR                                  0x812
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR                                  0x813
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR                                  0x814
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR                                 0x815
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR                                 0x816
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR                                 0x817
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR                                 0x818
++#define mmMC_VM_MX_L1_TLB_CNTL                                                  0x819
++#define mmMC_VM_FB_OFFSET                                                       0x81a
++#define mmMC_VM_STEERING                                                        0x81b
++#define mmMC_SHARED_CHREMAP2                                                    0x81c
++#define mmMC_SHARED_VF_ENABLE                                                   0x81d
++#define mmMC_SHARED_VIRT_RESET_REQ                                              0x81e
++#define mmMC_SHARED_ACTIVE_FCN_ID                                               0x81f
++#define mmMC_CONFIG_MCD                                                         0x828
++#define mmMC_CG_CONFIG_MCD                                                      0x829
++#define mmMC_MEM_POWER_LS                                                       0x82a
++#define mmMC_SHARED_BLACKOUT_CNTL                                               0x82b
++#define mmMC_VM_MB_L1_TLB0_DEBUG                                                0x891
++#define mmMC_VM_MB_L1_TLB1_DEBUG                                                0x892
++#define mmMC_VM_MB_L1_TLB2_DEBUG                                                0x893
++#define mmMC_VM_MB_L1_TLB0_STATUS                                               0x895
++#define mmMC_VM_MB_L1_TLB1_STATUS                                               0x896
++#define mmMC_VM_MB_L1_TLB2_STATUS                                               0x897
++#define mmMC_VM_MB_L2ARBITER_L2_CREDITS                                         0x8a1
++#define mmMC_VM_MB_L1_TLB3_DEBUG                                                0x8a5
++#define mmMC_VM_MB_L1_TLB3_STATUS                                               0x8a6
++#define mmMC_VM_MD_L1_TLB0_DEBUG                                                0x998
++#define mmMC_VM_MD_L1_TLB1_DEBUG                                                0x999
++#define mmMC_VM_MD_L1_TLB2_DEBUG                                                0x99a
++#define mmMC_VM_MD_L1_TLB0_STATUS                                               0x99b
++#define mmMC_VM_MD_L1_TLB1_STATUS                                               0x99c
++#define mmMC_VM_MD_L1_TLB2_STATUS                                               0x99d
++#define mmMC_VM_MD_L2ARBITER_L2_CREDITS                                         0x9a4
++#define mmMC_VM_MD_L1_TLB3_DEBUG                                                0x9a7
++#define mmMC_VM_MD_L1_TLB3_STATUS                                               0x9a8
++#define mmMC_XPB_RTR_SRC_APRTR0                                                 0x8cd
++#define mmMC_XPB_RTR_SRC_APRTR1                                                 0x8ce
++#define mmMC_XPB_RTR_SRC_APRTR2                                                 0x8cf
++#define mmMC_XPB_RTR_SRC_APRTR3                                                 0x8d0
++#define mmMC_XPB_RTR_SRC_APRTR4                                                 0x8d1
++#define mmMC_XPB_RTR_SRC_APRTR5                                                 0x8d2
++#define mmMC_XPB_RTR_SRC_APRTR6                                                 0x8d3
++#define mmMC_XPB_RTR_SRC_APRTR7                                                 0x8d4
++#define mmMC_XPB_RTR_SRC_APRTR8                                                 0x8d5
++#define mmMC_XPB_RTR_SRC_APRTR9                                                 0x8d6
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR0                                            0x8d7
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR1                                            0x8d8
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR2                                            0x8d9
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR3                                            0x8da
++#define mmMC_XPB_RTR_DEST_MAP0                                                  0x8db
++#define mmMC_XPB_RTR_DEST_MAP1                                                  0x8dc
++#define mmMC_XPB_RTR_DEST_MAP2                                                  0x8dd
++#define mmMC_XPB_RTR_DEST_MAP3                                                  0x8de
++#define mmMC_XPB_RTR_DEST_MAP4                                                  0x8df
++#define mmMC_XPB_RTR_DEST_MAP5                                                  0x8e0
++#define mmMC_XPB_RTR_DEST_MAP6                                                  0x8e1
++#define mmMC_XPB_RTR_DEST_MAP7                                                  0x8e2
++#define mmMC_XPB_RTR_DEST_MAP8                                                  0x8e3
++#define mmMC_XPB_RTR_DEST_MAP9                                                  0x8e4
++#define mmMC_XPB_XDMA_RTR_DEST_MAP0                                             0x8e5
++#define mmMC_XPB_XDMA_RTR_DEST_MAP1                                             0x8e6
++#define mmMC_XPB_XDMA_RTR_DEST_MAP2                                             0x8e7
++#define mmMC_XPB_XDMA_RTR_DEST_MAP3                                             0x8e8
++#define mmMC_XPB_CLG_CFG0                                                       0x8e9
++#define mmMC_XPB_CLG_CFG1                                                       0x8ea
++#define mmMC_XPB_CLG_CFG2                                                       0x8eb
++#define mmMC_XPB_CLG_CFG3                                                       0x8ec
++#define mmMC_XPB_CLG_CFG4                                                       0x8ed
++#define mmMC_XPB_CLG_CFG5                                                       0x8ee
++#define mmMC_XPB_CLG_CFG6                                                       0x8ef
++#define mmMC_XPB_CLG_CFG7                                                       0x8f0
++#define mmMC_XPB_CLG_CFG8                                                       0x8f1
++#define mmMC_XPB_CLG_CFG9                                                       0x8f2
++#define mmMC_XPB_CLG_CFG10                                                      0x8f3
++#define mmMC_XPB_CLG_CFG11                                                      0x8f4
++#define mmMC_XPB_CLG_CFG12                                                      0x8f5
++#define mmMC_XPB_CLG_CFG13                                                      0x8f6
++#define mmMC_XPB_CLG_CFG14                                                      0x8f7
++#define mmMC_XPB_CLG_CFG15                                                      0x8f8
++#define mmMC_XPB_CLG_CFG16                                                      0x8f9
++#define mmMC_XPB_CLG_CFG17                                                      0x8fa
++#define mmMC_XPB_CLG_CFG18                                                      0x8fb
++#define mmMC_XPB_CLG_CFG19                                                      0x8fc
++#define mmMC_XPB_CLG_EXTRA                                                      0x8fd
++#define mmMC_XPB_LB_ADDR                                                        0x8fe
++#define mmMC_XPB_UNC_THRESH_HST                                                 0x8ff
++#define mmMC_XPB_UNC_THRESH_SID                                                 0x900
++#define mmMC_XPB_WCB_STS                                                        0x901
++#define mmMC_XPB_WCB_CFG                                                        0x902
++#define mmMC_XPB_P2P_BAR_CFG                                                    0x903
++#define mmMC_XPB_P2P_BAR0                                                       0x904
++#define mmMC_XPB_P2P_BAR1                                                       0x905
++#define mmMC_XPB_P2P_BAR2                                                       0x906
++#define mmMC_XPB_P2P_BAR3                                                       0x907
++#define mmMC_XPB_P2P_BAR4                                                       0x908
++#define mmMC_XPB_P2P_BAR5                                                       0x909
++#define mmMC_XPB_P2P_BAR6                                                       0x90a
++#define mmMC_XPB_P2P_BAR7                                                       0x90b
++#define mmMC_XPB_P2P_BAR_SETUP                                                  0x90c
++#define mmMC_XPB_P2P_BAR_DEBUG                                                  0x90d
++#define mmMC_XPB_P2P_BAR_DELTA_ABOVE                                            0x90e
++#define mmMC_XPB_P2P_BAR_DELTA_BELOW                                            0x90f
++#define mmMC_XPB_PEER_SYS_BAR0                                                  0x910
++#define mmMC_XPB_PEER_SYS_BAR1                                                  0x911
++#define mmMC_XPB_PEER_SYS_BAR2                                                  0x912
++#define mmMC_XPB_PEER_SYS_BAR3                                                  0x913
++#define mmMC_XPB_PEER_SYS_BAR4                                                  0x914
++#define mmMC_XPB_PEER_SYS_BAR5                                                  0x915
++#define mmMC_XPB_PEER_SYS_BAR6                                                  0x916
++#define mmMC_XPB_PEER_SYS_BAR7                                                  0x917
++#define mmMC_XPB_PEER_SYS_BAR8                                                  0x918
++#define mmMC_XPB_PEER_SYS_BAR9                                                  0x919
++#define mmMC_XPB_XDMA_PEER_SYS_BAR0                                             0x91a
++#define mmMC_XPB_XDMA_PEER_SYS_BAR1                                             0x91b
++#define mmMC_XPB_XDMA_PEER_SYS_BAR2                                             0x91c
++#define mmMC_XPB_XDMA_PEER_SYS_BAR3                                             0x91d
++#define mmMC_XPB_CLK_GAT                                                        0x91e
++#define mmMC_XPB_INTF_CFG                                                       0x91f
++#define mmMC_XPB_INTF_STS                                                       0x920
++#define mmMC_XPB_PIPE_STS                                                       0x921
++#define mmMC_XPB_SUB_CTRL                                                       0x922
++#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB                                       0x923
++#define mmMC_XPB_PERF_KNOBS                                                     0x924
++#define mmMC_XPB_STICKY                                                         0x925
++#define mmMC_XPB_STICKY_W1C                                                     0x926
++#define mmMC_XPB_MISC_CFG                                                       0x927
++#define mmMC_XPB_CLG_CFG20                                                      0x928
++#define mmMC_XPB_CLG_CFG21                                                      0x929
++#define mmMC_XPB_CLG_CFG22                                                      0x92a
++#define mmMC_XPB_CLG_CFG23                                                      0x92b
++#define mmMC_XPB_CLG_CFG24                                                      0x92c
++#define mmMC_XPB_CLG_CFG25                                                      0x92d
++#define mmMC_XPB_CLG_CFG26                                                      0x92e
++#define mmMC_XPB_CLG_CFG27                                                      0x92f
++#define mmMC_XPB_CLG_CFG28                                                      0x930
++#define mmMC_XPB_CLG_CFG29                                                      0x931
++#define mmMC_XPB_CLG_CFG30                                                      0x932
++#define mmMC_XPB_CLG_CFG31                                                      0x933
++#define mmMC_XPB_INTF_CFG2                                                      0x934
++#define mmMC_XPB_CLG_EXTRA_RD                                                   0x935
++#define mmMC_XPB_CLG_CFG32                                                      0x936
++#define mmMC_XPB_CLG_CFG33                                                      0x937
++#define mmMC_XPB_CLG_CFG34                                                      0x938
++#define mmMC_XPB_CLG_CFG35                                                      0x939
++#define mmMC_XPB_CLG_CFG36                                                      0x93a
++#define mmMC_XBAR_ADDR_DEC                                                      0xc80
++#define mmMC_XBAR_REMOTE                                                        0xc81
++#define mmMC_XBAR_WRREQ_CREDIT                                                  0xc82
++#define mmMC_XBAR_RDREQ_CREDIT                                                  0xc83
++#define mmMC_XBAR_RDREQ_PRI_CREDIT                                              0xc84
++#define mmMC_XBAR_WRRET_CREDIT1                                                 0xc85
++#define mmMC_XBAR_WRRET_CREDIT2                                                 0xc86
++#define mmMC_XBAR_RDRET_CREDIT1                                                 0xc87
++#define mmMC_XBAR_RDRET_CREDIT2                                                 0xc88
++#define mmMC_XBAR_RDRET_PRI_CREDIT1                                             0xc89
++#define mmMC_XBAR_RDRET_PRI_CREDIT2                                             0xc8a
++#define mmMC_XBAR_CHTRIREMAP                                                    0xc8b
++#define mmMC_XBAR_TWOCHAN                                                       0xc8c
++#define mmMC_XBAR_ARB                                                           0xc8d
++#define mmMC_XBAR_ARB_MAX_BURST                                                 0xc8e
++#define mmMC_XBAR_FIFO_MON_CNTL0                                                0xc8f
++#define mmMC_XBAR_FIFO_MON_CNTL1                                                0xc90
++#define mmMC_XBAR_FIFO_MON_CNTL2                                                0xc91
++#define mmMC_XBAR_FIFO_MON_RSLT0                                                0xc92
++#define mmMC_XBAR_FIFO_MON_RSLT1                                                0xc93
++#define mmMC_XBAR_FIFO_MON_RSLT2                                                0xc94
++#define mmMC_XBAR_FIFO_MON_RSLT3                                                0xc95
++#define mmMC_XBAR_FIFO_MON_MAX_THSH                                             0xc96
++#define mmMC_XBAR_SPARE0                                                        0xc97
++#define mmMC_XBAR_SPARE1                                                        0xc98
++#define mmMC_CITF_PERFCOUNTER_LO                                                0x7a0
++#define mmMC_HUB_PERFCOUNTER_LO                                                 0x7a1
++#define mmMC_RPB_PERFCOUNTER_LO                                                 0x7a2
++#define mmMC_MCBVM_PERFCOUNTER_LO                                               0x7a3
++#define mmMC_MCDVM_PERFCOUNTER_LO                                               0x7a4
++#define mmMC_VM_L2_PERFCOUNTER_LO                                               0x7a5
++#define mmMC_ARB_PERFCOUNTER_LO                                                 0x7a6
++#define mmATC_PERFCOUNTER_LO                                                    0x7a7
++#define mmMC_CITF_PERFCOUNTER_HI                                                0x7a8
++#define mmMC_HUB_PERFCOUNTER_HI                                                 0x7a9
++#define mmMC_MCBVM_PERFCOUNTER_HI                                               0x7aa
++#define mmMC_MCDVM_PERFCOUNTER_HI                                               0x7ab
++#define mmMC_RPB_PERFCOUNTER_HI                                                 0x7ac
++#define mmMC_VM_L2_PERFCOUNTER_HI                                               0x7ad
++#define mmMC_ARB_PERFCOUNTER_HI                                                 0x7ae
++#define mmATC_PERFCOUNTER_HI                                                    0x7af
++#define mmMC_CITF_PERFCOUNTER0_CFG                                              0x7b0
++#define mmMC_CITF_PERFCOUNTER1_CFG                                              0x7b1
++#define mmMC_CITF_PERFCOUNTER2_CFG                                              0x7b2
++#define mmMC_CITF_PERFCOUNTER3_CFG                                              0x7b3
++#define mmMC_HUB_PERFCOUNTER0_CFG                                               0x7b4
++#define mmMC_HUB_PERFCOUNTER1_CFG                                               0x7b5
++#define mmMC_HUB_PERFCOUNTER2_CFG                                               0x7b6
++#define mmMC_HUB_PERFCOUNTER3_CFG                                               0x7b7
++#define mmMC_RPB_PERFCOUNTER0_CFG                                               0x7b8
++#define mmMC_RPB_PERFCOUNTER1_CFG                                               0x7b9
++#define mmMC_RPB_PERFCOUNTER2_CFG                                               0x7ba
++#define mmMC_RPB_PERFCOUNTER3_CFG                                               0x7bb
++#define mmMC_ARB_PERFCOUNTER0_CFG                                               0x7bc
++#define mmMC_ARB_PERFCOUNTER1_CFG                                               0x7bd
++#define mmMC_ARB_PERFCOUNTER2_CFG                                               0x7be
++#define mmMC_ARB_PERFCOUNTER3_CFG                                               0x7bf
++#define mmMC_MCBVM_PERFCOUNTER0_CFG                                             0x7c0
++#define mmMC_MCBVM_PERFCOUNTER1_CFG                                             0x7c1
++#define mmMC_MCBVM_PERFCOUNTER2_CFG                                             0x7c2
++#define mmMC_MCBVM_PERFCOUNTER3_CFG                                             0x7c3
++#define mmMC_MCDVM_PERFCOUNTER0_CFG                                             0x7c4
++#define mmMC_MCDVM_PERFCOUNTER1_CFG                                             0x7c5
++#define mmMC_MCDVM_PERFCOUNTER2_CFG                                             0x7c6
++#define mmMC_MCDVM_PERFCOUNTER3_CFG                                             0x7c7
++#define mmATC_PERFCOUNTER0_CFG                                                  0x7c8
++#define mmATC_PERFCOUNTER1_CFG                                                  0x7c9
++#define mmATC_PERFCOUNTER2_CFG                                                  0x7ca
++#define mmATC_PERFCOUNTER3_CFG                                                  0x7cb
++#define mmMC_VM_L2_PERFCOUNTER0_CFG                                             0x7cc
++#define mmMC_VM_L2_PERFCOUNTER1_CFG                                             0x7cd
++#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL                                         0x7ce
++#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL                                          0x7cf
++#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL                                          0x7d0
++#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL                                        0x7d1
++#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL                                        0x7d2
++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                        0x7d3
++#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL                                          0x7d4
++#define mmATC_PERFCOUNTER_RSLT_CNTL                                             0x7d5
++#define mmCHUB_ATC_PERFCOUNTER_LO                                               0x7d6
++#define mmCHUB_ATC_PERFCOUNTER_HI                                               0x7d7
++#define mmCHUB_ATC_PERFCOUNTER0_CFG                                             0x7d8
++#define mmCHUB_ATC_PERFCOUNTER1_CFG                                             0x7d9
++#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL                                        0x7da
++#define mmATC_VM_APERTURE0_LOW_ADDR                                             0xcc0
++#define mmATC_VM_APERTURE1_LOW_ADDR                                             0xcc1
++#define mmATC_VM_APERTURE0_HIGH_ADDR                                            0xcc2
++#define mmATC_VM_APERTURE1_HIGH_ADDR                                            0xcc3
++#define mmATC_VM_APERTURE0_CNTL                                                 0xcc4
++#define mmATC_VM_APERTURE1_CNTL                                                 0xcc5
++#define mmATC_VM_APERTURE0_CNTL2                                                0xcc6
++#define mmATC_VM_APERTURE1_CNTL2                                                0xcc7
++#define mmATC_ATS_CNTL                                                          0xcc9
++#define mmATC_ATS_DEBUG                                                         0xcca
++#define mmATC_ATS_FAULT_DEBUG                                                   0xccb
++#define mmATC_ATS_STATUS                                                        0xccc
++#define mmATC_ATS_FAULT_CNTL                                                    0xccd
++#define mmATC_ATS_FAULT_STATUS_INFO                                             0xcce
++#define mmATC_ATS_FAULT_STATUS_ADDR                                             0xccf
++#define mmATC_ATS_DEFAULT_PAGE_LOW                                              0xcd0
++#define mmATC_ATS_DEFAULT_PAGE_CNTL                                             0xcd1
++#define mmATC_ATS_FAULT_STATUS_INFO2                                            0xcd2
++#define mmATC_MISC_CG                                                           0xcd4
++#define mmATC_L2_CNTL                                                           0xcd5
++#define mmATC_L2_CNTL2                                                          0xcd6
++#define mmATC_L2_DEBUG                                                          0xcd7
++#define mmATC_L2_DEBUG2                                                         0xcd8
++#define mmATC_L2_CACHE_DATA0                                                    0xcd9
++#define mmATC_L2_CACHE_DATA1                                                    0xcda
++#define mmATC_L2_CACHE_DATA2                                                    0xcdb
++#define mmATC_L1_CNTL                                                           0xcdc
++#define mmATC_L1_ADDRESS_OFFSET                                                 0xcdd
++#define mmATC_L1RD_DEBUG_TLB                                                    0xcde
++#define mmATC_L1WR_DEBUG_TLB                                                    0xcdf
++#define mmATC_L1RD_STATUS                                                       0xce0
++#define mmATC_L1WR_STATUS                                                       0xce1
++#define mmATC_L1RD_DEBUG2_TLB                                                   0xce2
++#define mmATC_L1WR_DEBUG2_TLB                                                   0xce3
++#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS                                  0xce6
++#define mmATC_VMID0_PASID_MAPPING                                               0xce7
++#define mmATC_VMID1_PASID_MAPPING                                               0xce8
++#define mmATC_VMID2_PASID_MAPPING                                               0xce9
++#define mmATC_VMID3_PASID_MAPPING                                               0xcea
++#define mmATC_VMID4_PASID_MAPPING                                               0xceb
++#define mmATC_VMID5_PASID_MAPPING                                               0xcec
++#define mmATC_VMID6_PASID_MAPPING                                               0xced
++#define mmATC_VMID7_PASID_MAPPING                                               0xcee
++#define mmATC_VMID8_PASID_MAPPING                                               0xcef
++#define mmATC_VMID9_PASID_MAPPING                                               0xcf0
++#define mmATC_VMID10_PASID_MAPPING                                              0xcf1
++#define mmATC_VMID11_PASID_MAPPING                                              0xcf2
++#define mmATC_VMID12_PASID_MAPPING                                              0xcf3
++#define mmATC_VMID13_PASID_MAPPING                                              0xcf4
++#define mmATC_VMID14_PASID_MAPPING                                              0xcf5
++#define mmATC_VMID15_PASID_MAPPING                                              0xcf6
++#define mmATC_ATS_VMID_STATUS                                                   0xd07
++#define mmATC_ATS_SMU_STATUS                                                    0xd08
++#define mmATC_L2_CNTL3                                                          0xd09
++#define mmATC_L2_STATUS                                                         0xd0a
++#define mmATC_L2_STATUS2                                                        0xd0b
++#define mmGMCON_RENG_RAM_INDEX                                                  0xd40
++#define mmGMCON_RENG_RAM_DATA                                                   0xd41
++#define mmGMCON_RENG_EXECUTE                                                    0xd42
++#define mmGMCON_MISC                                                            0xd43
++#define mmGMCON_MISC2                                                           0xd44
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0                                     0xd45
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1                                     0xd46
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2                                     0xd47
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0                                  0xd48
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1                                  0xd49
++#define mmGMCON_PERF_MON_CNTL0                                                  0xd4a
++#define mmGMCON_PERF_MON_CNTL1                                                  0xd4b
++#define mmGMCON_PERF_MON_RSLT0                                                  0xd4c
++#define mmGMCON_PERF_MON_RSLT1                                                  0xd4d
++#define mmGMCON_PGFSM_CONFIG                                                    0xd4e
++#define mmGMCON_PGFSM_WRITE                                                     0xd4f
++#define mmGMCON_PGFSM_READ                                                      0xd50
++#define mmGMCON_MISC3                                                           0xd51
++#define mmGMCON_MASK                                                            0xd52
++#define mmGMCON_LPT_TARGET                                                      0xd53
++#define mmGMCON_DEBUG                                                           0xd5f
++#define mmVM_L2_CNTL                                                            0x500
++#define mmVM_L2_CNTL2                                                           0x501
++#define mmVM_L2_CNTL3                                                           0x502
++#define mmVM_L2_STATUS                                                          0x503
++#define mmVM_CONTEXT0_CNTL                                                      0x504
++#define mmVM_CONTEXT1_CNTL                                                      0x505
++#define mmVM_DUMMY_PAGE_FAULT_CNTL                                              0x506
++#define mmVM_DUMMY_PAGE_FAULT_ADDR                                              0x507
++#define mmVM_CONTEXT0_CNTL2                                                     0x50c
++#define mmVM_CONTEXT1_CNTL2                                                     0x50d
++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR                                      0x50e
++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR                                      0x50f
++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR                                     0x510
++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR                                     0x511
++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR                                     0x512
++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR                                     0x513
++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR                                     0x514
++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR                                     0x515
++#define mmVM_INVALIDATE_REQUEST                                                 0x51e
++#define mmVM_INVALIDATE_RESPONSE                                                0x51f
++#define mmVM_PRT_APERTURE0_LOW_ADDR                                             0x52c
++#define mmVM_PRT_APERTURE1_LOW_ADDR                                             0x52d
++#define mmVM_PRT_APERTURE2_LOW_ADDR                                             0x52e
++#define mmVM_PRT_APERTURE3_LOW_ADDR                                             0x52f
++#define mmVM_PRT_APERTURE0_HIGH_ADDR                                            0x530
++#define mmVM_PRT_APERTURE1_HIGH_ADDR                                            0x531
++#define mmVM_PRT_APERTURE2_HIGH_ADDR                                            0x532
++#define mmVM_PRT_APERTURE3_HIGH_ADDR                                            0x533
++#define mmVM_PRT_CNTL                                                           0x534
++#define mmVM_CONTEXTS_DISABLE                                                   0x535
++#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS                                   0x536
++#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS                                   0x537
++#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT                                 0x538
++#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT                                 0x539
++#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR                                     0x53e
++#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR                                     0x53f
++#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR                             0x546
++#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR                             0x547
++#define mmVM_FAULT_CLIENT_ID                                                    0x54e
++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR                                      0x54f
++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR                                      0x550
++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR                                      0x551
++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR                                      0x552
++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR                                      0x553
++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR                                      0x554
++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR                                      0x555
++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR                                      0x556
++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR                                     0x557
++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR                                     0x558
++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR                                       0x55f
++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR                                       0x560
++#define mmVM_DEBUG                                                              0x56f
++#define mmVM_L2_CG                                                              0x570
++#define mmVM_L2_BANK_SELECT_MASKA                                               0x572
++#define mmVM_L2_BANK_SELECT_MASKB                                               0x573
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR                             0x575
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR                            0x576
++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET                                0x577
++#define mmVM_L2_CNTL4                                                           0x578
++#define mmVM_L2_BANK_SELECT_RESERVED_CID                                        0x579
++#define mmVM_L2_BANK_SELECT_RESERVED_CID2                                       0x57a
++#define mmMC_VM_FB_SIZE_OFFSET_VF0                                              0xf980
++#define mmMC_VM_FB_SIZE_OFFSET_VF1                                              0xf981
++#define mmMC_VM_FB_SIZE_OFFSET_VF2                                              0xf982
++#define mmMC_VM_FB_SIZE_OFFSET_VF3                                              0xf983
++#define mmMC_VM_FB_SIZE_OFFSET_VF4                                              0xf984
++#define mmMC_VM_FB_SIZE_OFFSET_VF5                                              0xf985
++#define mmMC_VM_FB_SIZE_OFFSET_VF6                                              0xf986
++#define mmMC_VM_FB_SIZE_OFFSET_VF7                                              0xf987
++#define mmMC_VM_FB_SIZE_OFFSET_VF8                                              0xf988
++#define mmMC_VM_FB_SIZE_OFFSET_VF9                                              0xf989
++#define mmMC_VM_FB_SIZE_OFFSET_VF10                                             0xf98a
++#define mmMC_VM_FB_SIZE_OFFSET_VF11                                             0xf98b
++#define mmMC_VM_FB_SIZE_OFFSET_VF12                                             0xf98c
++#define mmMC_VM_FB_SIZE_OFFSET_VF13                                             0xf98d
++#define mmMC_VM_FB_SIZE_OFFSET_VF14                                             0xf98e
++#define mmMC_VM_FB_SIZE_OFFSET_VF15                                             0xf98f
++#define mmMC_VM_NB_MMIOBASE                                                     0xf990
++#define mmMC_VM_NB_MMIOLIMIT                                                    0xf991
++#define mmMC_VM_NB_PCI_CTRL                                                     0xf992
++#define mmMC_VM_NB_PCI_ARB                                                      0xf993
++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1                                            0xf994
++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2                                           0xf995
++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2                                           0xf996
++#define mmMC_VM_NB_TOP_OF_DRAM3                                                 0xf997
++#define mmMC_VM_MARC_BASE_LO_0                                                  0xf998
++#define mmMC_VM_MARC_BASE_LO_1                                                  0xf99e
++#define mmMC_VM_MARC_BASE_LO_2                                                  0xf9a4
++#define mmMC_VM_MARC_BASE_LO_3                                                  0xf9aa
++#define mmMC_VM_MARC_BASE_HI_0                                                  0xf999
++#define mmMC_VM_MARC_BASE_HI_1                                                  0xf99f
++#define mmMC_VM_MARC_BASE_HI_2                                                  0xf9a5
++#define mmMC_VM_MARC_BASE_HI_3                                                  0xf9ab
++#define mmMC_VM_MARC_RELOC_LO_0                                                 0xf99a
++#define mmMC_VM_MARC_RELOC_LO_1                                                 0xf9a0
++#define mmMC_VM_MARC_RELOC_LO_2                                                 0xf9a6
++#define mmMC_VM_MARC_RELOC_LO_3                                                 0xf9ac
++#define mmMC_VM_MARC_RELOC_HI_0                                                 0xf99b
++#define mmMC_VM_MARC_RELOC_HI_1                                                 0xf9a1
++#define mmMC_VM_MARC_RELOC_HI_2                                                 0xf9a7
++#define mmMC_VM_MARC_RELOC_HI_3                                                 0xf9ad
++#define mmMC_VM_MARC_LEN_LO_0                                                   0xf99c
++#define mmMC_VM_MARC_LEN_LO_1                                                   0xf9a2
++#define mmMC_VM_MARC_LEN_LO_2                                                   0xf9a8
++#define mmMC_VM_MARC_LEN_LO_3                                                   0xf9ae
++#define mmMC_VM_MARC_LEN_HI_0                                                   0xf99d
++#define mmMC_VM_MARC_LEN_HI_1                                                   0xf9a3
++#define mmMC_VM_MARC_LEN_HI_2                                                   0xf9a9
++#define mmMC_VM_MARC_LEN_HI_3                                                   0xf9af
++#define mmMC_VM_MARC_CNTL                                                       0xf9b0
++#define mmMC_VM_MB_L1_TLS0_CNTL0                                                0xf9b1
++#define mmMC_VM_MB_L1_TLS0_CNTL1                                                0xf9b4
++#define mmMC_VM_MB_L1_TLS0_CNTL2                                                0xf9b7
++#define mmMC_VM_MB_L1_TLS0_CNTL3                                                0xf9ba
++#define mmMC_VM_MB_L1_TLS0_CNTL4                                                0xf9bd
++#define mmMC_VM_MB_L1_TLS0_CNTL5                                                0xf9c0
++#define mmMC_VM_MB_L1_TLS0_CNTL6                                                0xf9c3
++#define mmMC_VM_MB_L1_TLS0_CNTL7                                                0xf9c6
++#define mmMC_VM_MB_L1_TLS0_CNTL8                                                0xf9c9
++#define mmMC_VM_MB_L1_TLS0_START_ADDR0                                          0xf9b2
++#define mmMC_VM_MB_L1_TLS0_START_ADDR1                                          0xf9b5
++#define mmMC_VM_MB_L1_TLS0_START_ADDR2                                          0xf9b8
++#define mmMC_VM_MB_L1_TLS0_START_ADDR3                                          0xf9bb
++#define mmMC_VM_MB_L1_TLS0_START_ADDR4                                          0xf9be
++#define mmMC_VM_MB_L1_TLS0_START_ADDR5                                          0xf9c1
++#define mmMC_VM_MB_L1_TLS0_START_ADDR6                                          0xf9c4
++#define mmMC_VM_MB_L1_TLS0_START_ADDR7                                          0xf9c7
++#define mmMC_VM_MB_L1_TLS0_START_ADDR8                                          0xf9ca
++#define mmMC_VM_MB_L1_TLS0_END_ADDR0                                            0xf9b3
++#define mmMC_VM_MB_L1_TLS0_END_ADDR1                                            0xf9b6
++#define mmMC_VM_MB_L1_TLS0_END_ADDR2                                            0xf9b9
++#define mmMC_VM_MB_L1_TLS0_END_ADDR3                                            0xf9bc
++#define mmMC_VM_MB_L1_TLS0_END_ADDR4                                            0xf9bf
++#define mmMC_VM_MB_L1_TLS0_END_ADDR5                                            0xf9c2
++#define mmMC_VM_MB_L1_TLS0_END_ADDR6                                            0xf9c5
++#define mmMC_VM_MB_L1_TLS0_END_ADDR7                                            0xf9c8
++#define mmMC_VM_MB_L1_TLS0_END_ADDR8                                            0xf9cb
++#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS                              0xf9cc
++#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR                                0xf9cd
++#define mmMC_SEQ_CNTL                                                           0xa25
++#define mmMC_SEQ_CNTL_2                                                         0xad4
++#define mmMC_SEQ_DRAM                                                           0xa26
++#define mmMC_SEQ_DRAM_2                                                         0xa27
++#define mmMC_SEQ_RAS_TIMING                                                     0xa28
++#define mmMC_SEQ_CAS_TIMING                                                     0xa29
++#define mmMC_SEQ_MISC_TIMING                                                    0xa2a
++#define mmMC_SEQ_MISC_TIMING2                                                   0xa2b
++#define mmMC_SEQ_PMG_TIMING                                                     0xa2c
++#define mmMC_SEQ_RD_CTL_D0                                                      0xa2d
++#define mmMC_SEQ_RD_CTL_D1                                                      0xa2e
++#define mmMC_SEQ_WR_CTL_D0                                                      0xa2f
++#define mmMC_SEQ_WR_CTL_D1                                                      0xa30
++#define mmMC_SEQ_WR_CTL_2                                                       0xad5
++#define mmMC_SEQ_CMD                                                            0xa31
++#define mmMC_PMG_CMD_EMRS                                                       0xa83
++#define mmMC_PMG_CMD_MRS                                                        0xaab
++#define mmMC_PMG_CMD_MRS1                                                       0xad1
++#define mmMC_PMG_CMD_MRS2                                                       0xad7
++#define mmMC_PMG_CFG                                                            0xa84
++#define mmMC_PMG_AUTO_CMD                                                       0xa34
++#define mmMC_PMG_AUTO_CFG                                                       0xa35
++#define mmMC_IMP_CNTL                                                           0xa36
++#define mmMC_IMP_DEBUG                                                          0xa37
++#define mmMC_IMP_STATUS                                                         0xa38
++#define mmMC_IMP_DQ_STATUS                                                      0xabc
++#define mmMC_SEQ_WCDR_CTRL                                                      0xa39
++#define mmMC_SEQ_TRAIN_WAKEUP_CNTL                                              0xa3a
++#define mmMC_SEQ_TRAIN_EDC_THRESHOLD                                            0xa3b
++#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2                                           0xafe
++#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3                                           0xaff
++#define mmMC_SEQ_TRAIN_WAKEUP_EDGE                                              0xa3c
++#define mmMC_SEQ_TRAIN_WAKEUP_MASK                                              0xa3d
++#define mmMC_SEQ_TRAIN_CAPTURE                                                  0xa3e
++#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR                                             0xa3f
++#define mmMC_SEQ_TRAIN_TIMING                                                   0xa40
++#define mmMC_TRAIN_EDCCDR_R_D0                                                  0xa41
++#define mmMC_TRAIN_EDCCDR_R_D1                                                  0xa42
++#define mmMC_TRAIN_PRBSERR_0_D0                                                 0xa43
++#define mmMC_TRAIN_PRBSERR_1_D0                                                 0xa44
++#define mmMC_TRAIN_PRBSERR_2_D0                                                 0xafb
++#define mmMC_TRAIN_EDC_STATUS_D0                                                0xa45
++#define mmMC_TRAIN_PRBSERR_0_D1                                                 0xa46
++#define mmMC_TRAIN_PRBSERR_1_D1                                                 0xa47
++#define mmMC_TRAIN_PRBSERR_2_D1                                                 0xafc
++#define mmMC_TRAIN_EDC_STATUS_D1                                                0xa48
++#define mmMC_IO_TXCNTL_DPHY0_D0                                                 0xa49
++#define mmMC_IO_TXCNTL_DPHY1_D0                                                 0xa4a
++#define mmMC_IO_TXCNTL_APHY_D0                                                  0xa4b
++#define mmMC_IO_RXCNTL_DPHY0_D0                                                 0xa4c
++#define mmMC_IO_RXCNTL1_DPHY0_D0                                                0xadf
++#define mmMC_IO_RXCNTL_DPHY1_D0                                                 0xa4d
++#define mmMC_IO_RXCNTL1_DPHY1_D0                                                0xae0
++#define mmMC_IO_DPHY_STR_CNTL_D0                                                0xa4e
++#define mmMC_IO_APHY_STR_CNTL_D0                                                0xa97
++#define mmMC_IO_TXCNTL_DPHY0_D1                                                 0xa4f
++#define mmMC_IO_TXCNTL_DPHY1_D1                                                 0xa50
++#define mmMC_IO_TXCNTL_APHY_D1                                                  0xa51
++#define mmMC_IO_RXCNTL_DPHY0_D1                                                 0xa52
++#define mmMC_IO_RXCNTL1_DPHY0_D1                                                0xae1
++#define mmMC_IO_RXCNTL_DPHY1_D1                                                 0xa53
++#define mmMC_IO_RXCNTL1_DPHY1_D1                                                0xae2
++#define mmMC_IO_DPHY_STR_CNTL_D1                                                0xa54
++#define mmMC_IO_APHY_STR_CNTL_D1                                                0xa98
++#define mmMC_IO_CDRCNTL_D0                                                      0xa55
++#define mmMC_IO_CDRCNTL1_D0                                                     0xadd
++#define mmMC_IO_CDRCNTL2_D0                                                     0xae4
++#define mmMC_IO_CDRCNTL_D1                                                      0xa56
++#define mmMC_IO_CDRCNTL1_D1                                                     0xade
++#define mmMC_IO_CDRCNTL2_D1                                                     0xae5
++#define mmMC_SEQ_FIFO_CTL                                                       0xa57
++#define mmMC_SEQ_TXFRAMING_BYTE0_D0                                             0xa58
++#define mmMC_SEQ_TXFRAMING_BYTE1_D0                                             0xa59
++#define mmMC_SEQ_TXFRAMING_BYTE2_D0                                             0xa5a
++#define mmMC_SEQ_TXFRAMING_BYTE3_D0                                             0xa5b
++#define mmMC_SEQ_TXFRAMING_DBI_D0                                               0xa5c
++#define mmMC_SEQ_TXFRAMING_EDC_D0                                               0xa5d
++#define mmMC_SEQ_TXFRAMING_FCK_D0                                               0xa5e
++#define mmMC_SEQ_TXFRAMING_BYTE0_D1                                             0xa60
++#define mmMC_SEQ_TXFRAMING_BYTE1_D1                                             0xa61
++#define mmMC_SEQ_TXFRAMING_BYTE2_D1                                             0xa62
++#define mmMC_SEQ_TXFRAMING_BYTE3_D1                                             0xa63
++#define mmMC_SEQ_TXFRAMING_DBI_D1                                               0xa64
++#define mmMC_SEQ_TXFRAMING_EDC_D1                                               0xa65
++#define mmMC_SEQ_TXFRAMING_FCK_D1                                               0xa66
++#define mmMC_SEQ_RXFRAMING_BYTE0_D0                                             0xa67
++#define mmMC_SEQ_RXFRAMING_BYTE1_D0                                             0xa68
++#define mmMC_SEQ_RXFRAMING_BYTE2_D0                                             0xa69
++#define mmMC_SEQ_RXFRAMING_BYTE3_D0                                             0xa6a
++#define mmMC_SEQ_RXFRAMING_DBI_D0                                               0xa6b
++#define mmMC_SEQ_RXFRAMING_EDC_D0                                               0xa6c
++#define mmMC_SEQ_RXFRAMING_BYTE0_D1                                             0xa6d
++#define mmMC_SEQ_RXFRAMING_BYTE1_D1                                             0xa6e
++#define mmMC_SEQ_RXFRAMING_BYTE2_D1                                             0xa6f
++#define mmMC_SEQ_RXFRAMING_BYTE3_D1                                             0xa70
++#define mmMC_SEQ_RXFRAMING_DBI_D1                                               0xa71
++#define mmMC_SEQ_RXFRAMING_EDC_D1                                               0xa72
++#define mmMC_IO_PAD_CNTL                                                        0xa73
++#define mmMC_IO_PAD_CNTL_D0                                                     0xa74
++#define mmMC_IO_PAD_CNTL_D1                                                     0xa75
++#define mmMC_NPL_STATUS                                                         0xa76
++#define mmMC_BIST_CMD_CNTL                                                      0xa8e
++#define mmMC_BIST_CNTL                                                          0xa05
++#define mmMC_BIST_AUTO_CNTL                                                     0xa06
++#define mmMC_BIST_DIR_CNTL                                                      0xa07
++#define mmMC_BIST_SADDR                                                         0xa08
++#define mmMC_BIST_EADDR                                                         0xa09
++#define mmMC_BIST_CMP_CNTL                                                      0xa8d
++#define mmMC_BIST_CMP_CNTL_2                                                    0xab6
++#define mmMC_BIST_DATA_WORD0                                                    0xa0a
++#define mmMC_BIST_DATA_WORD1                                                    0xa0b
++#define mmMC_BIST_DATA_WORD2                                                    0xa0c
++#define mmMC_BIST_DATA_WORD3                                                    0xa0d
++#define mmMC_BIST_DATA_WORD4                                                    0xa0e
++#define mmMC_BIST_DATA_WORD5                                                    0xa0f
++#define mmMC_BIST_DATA_WORD6                                                    0xa10
++#define mmMC_BIST_DATA_WORD7                                                    0xa11
++#define mmMC_BIST_DATA_MASK                                                     0xa12
++#define mmMC_BIST_MISMATCH_ADDR                                                 0xa13
++#define mmMC_BIST_RDATA_WORD0                                                   0xa14
++#define mmMC_BIST_RDATA_WORD1                                                   0xa15
++#define mmMC_BIST_RDATA_WORD2                                                   0xa16
++#define mmMC_BIST_RDATA_WORD3                                                   0xa17
++#define mmMC_BIST_RDATA_WORD4                                                   0xa18
++#define mmMC_BIST_RDATA_WORD5                                                   0xa19
++#define mmMC_BIST_RDATA_WORD6                                                   0xa1a
++#define mmMC_BIST_RDATA_WORD7                                                   0xa1b
++#define mmMC_BIST_RDATA_MASK                                                    0xa1c
++#define mmMC_BIST_RDATA_EDC                                                     0xa1d
++#define mmMC_SEQ_PERF_CNTL                                                      0xa77
++#define mmMC_SEQ_PERF_CNTL_1                                                    0xafd
++#define mmMC_SEQ_PERF_SEQ_CTL                                                   0xa78
++#define mmMC_SEQ_PERF_SEQ_CNT_A_I0                                              0xa79
++#define mmMC_SEQ_PERF_SEQ_CNT_A_I1                                              0xa7a
++#define mmMC_SEQ_PERF_SEQ_CNT_B_I0                                              0xa7b
++#define mmMC_SEQ_PERF_SEQ_CNT_B_I1                                              0xa7c
++#define mmMC_SEQ_PERF_SEQ_CNT_C_I0                                              0xad9
++#define mmMC_SEQ_PERF_SEQ_CNT_C_I1                                              0xada
++#define mmMC_SEQ_PERF_SEQ_CNT_D_I0                                              0xadb
++#define mmMC_SEQ_PERF_SEQ_CNT_D_I1                                              0xadc
++#define mmMC_SEQ_STATUS_M                                                       0xa7d
++#define mmMC_SEQ_STATUS_S                                                       0xa20
++#define mmMC_CG_DATAPORT                                                        0xa21
++#define mmMC_SEQ_VENDOR_ID_I0                                                   0xa7e
++#define mmMC_SEQ_VENDOR_ID_I1                                                   0xa7f
++#define mmMC_SEQ_MISC0                                                          0xa80
++#define mmMC_SEQ_MISC1                                                          0xa81
++#define mmMC_SEQ_RESERVE_0_S                                                    0xa1e
++#define mmMC_SEQ_RESERVE_1_S                                                    0xa1f
++#define mmMC_SEQ_RESERVE_M                                                      0xa82
++#define mmMC_SEQ_IO_RESERVE_D0                                                  0xab7
++#define mmMC_SEQ_IO_RESERVE_D1                                                  0xab8
++#define mmMC_SEQ_SUP_CNTL                                                       0xa32
++#define mmMC_SEQ_SUP_PGM                                                        0xa33
++#define mmMC_SEQ_SUP_GP0_STAT                                                   0xa8f
++#define mmMC_SEQ_SUP_GP1_STAT                                                   0xa90
++#define mmMC_SEQ_SUP_GP2_STAT                                                   0xa85
++#define mmMC_SEQ_SUP_GP3_STAT                                                   0xa86
++#define mmMC_SEQ_SUP_IR_STAT                                                    0xa87
++#define mmMC_SEQ_SUP_DEC_STAT                                                   0xa88
++#define mmMC_SEQ_SUP_PGM_STAT                                                   0xa89
++#define mmMC_SEQ_SUP_R_PGM                                                      0xa8a
++#define mmMC_SEQ_MISC3                                                          0xa8b
++#define mmMC_SEQ_MISC4                                                          0xa8c
++#define mmMC_SEQ_MISC5                                                          0xa95
++#define mmMC_SEQ_MISC6                                                          0xa96
++#define mmMC_SEQ_MISC7                                                          0xa99
++#define mmMC_SEQ_MISC8                                                          0xa5f
++#define mmMC_SEQ_MISC9                                                          0xae7
++#define mmMC_SEQ_CG                                                             0xa9a
++#define mmMC_SEQ_BYTE_REMAP_D0                                                  0xa93
++#define mmMC_SEQ_BYTE_REMAP_D1                                                  0xa94
++#define mmMC_SEQ_BIT_REMAP_B0_D0                                                0xaa3
++#define mmMC_SEQ_BIT_REMAP_B1_D0                                                0xaa4
++#define mmMC_SEQ_BIT_REMAP_B2_D0                                                0xaa5
++#define mmMC_SEQ_BIT_REMAP_B3_D0                                                0xaa6
++#define mmMC_SEQ_BIT_REMAP_B0_D1                                                0xaa7
++#define mmMC_SEQ_BIT_REMAP_B1_D1                                                0xaa8
++#define mmMC_SEQ_BIT_REMAP_B2_D1                                                0xaa9
++#define mmMC_SEQ_BIT_REMAP_B3_D1                                                0xaaa
++#define mmMC_SEQ_RAS_TIMING_LP                                                  0xa9b
++#define mmMC_SEQ_CAS_TIMING_LP                                                  0xa9c
++#define mmMC_SEQ_MISC_TIMING_LP                                                 0xa9d
++#define mmMC_SEQ_MISC_TIMING2_LP                                                0xa9e
++#define mmMC_SEQ_RD_CTL_D0_LP                                                   0xac7
++#define mmMC_SEQ_RD_CTL_D1_LP                                                   0xac8
++#define mmMC_SEQ_WR_CTL_D0_LP                                                   0xa9f
++#define mmMC_SEQ_WR_CTL_D1_LP                                                   0xaa0
++#define mmMC_SEQ_WR_CTL_2_LP                                                    0xad6
++#define mmMC_SEQ_PMG_CMD_EMRS_LP                                                0xaa1
++#define mmMC_SEQ_PMG_CMD_MRS_LP                                                 0xaa2
++#define mmMC_SEQ_PMG_CMD_MRS1_LP                                                0xad2
++#define mmMC_SEQ_PMG_CMD_MRS2_LP                                                0xad8
++#define mmMC_SEQ_PMG_TIMING_LP                                                  0xad3
++#define mmMC_SEQ_IO_RWORD0                                                      0xaac
++#define mmMC_SEQ_IO_RWORD1                                                      0xaad
++#define mmMC_SEQ_IO_RWORD2                                                      0xaae
++#define mmMC_SEQ_IO_RWORD3                                                      0xaaf
++#define mmMC_SEQ_IO_RWORD4                                                      0xab0
++#define mmMC_SEQ_IO_RWORD5                                                      0xab1
++#define mmMC_SEQ_IO_RWORD6                                                      0xab2
++#define mmMC_SEQ_IO_RWORD7                                                      0xab3
++#define mmMC_SEQ_IO_RDBI                                                        0xab4
++#define mmMC_SEQ_IO_REDC                                                        0xab5
++#define mmMC_SEQ_TCG_CNTL                                                       0xabd
++#define mmMC_SEQ_TSM_CTRL                                                       0xabe
++#define mmMC_SEQ_TSM_GCNT                                                       0xabf
++#define mmMC_SEQ_TSM_OCNT                                                       0xac0
++#define mmMC_SEQ_TSM_NCNT                                                       0xac1
++#define mmMC_SEQ_TSM_BCNT                                                       0xac2
++#define mmMC_SEQ_TSM_FLAG                                                       0xac3
++#define mmMC_SEQ_TSM_UPDATE                                                     0xac4
++#define mmMC_SEQ_TSM_EDC                                                        0xac5
++#define mmMC_SEQ_TSM_DBI                                                        0xac6
++#define mmMC_SEQ_TSM_WCDR                                                       0xae3
++#define mmMC_SEQ_TSM_MISC                                                       0xae6
++#define mmMC_SEQ_TIMER_WR                                                       0xac9
++#define mmMC_SEQ_TIMER_RD                                                       0xaca
++#define mmMC_SEQ_DRAM_ERROR_INSERTION                                           0xacb
++#define mmMC_PHY_TIMING_D0                                                      0xacc
++#define mmMC_PHY_TIMING_D1                                                      0xacd
++#define mmMC_PHY_TIMING_2                                                       0xace
++#define mmMC_SEQ_MPLL_OVERRIDE                                                  0xa22
++#define mmMCLK_PWRMGT_CNTL                                                      0xae8
++#define mmDLL_CNTL                                                              0xae9
++#define mmMPLL_SEQ_UCODE_1                                                      0xaea
++#define mmMPLL_SEQ_UCODE_2                                                      0xaeb
++#define mmMPLL_CNTL_MODE                                                        0xaec
++#define mmMPLL_FUNC_CNTL                                                        0xaed
++#define mmMPLL_FUNC_CNTL_1                                                      0xaee
++#define mmMPLL_FUNC_CNTL_2                                                      0xaef
++#define mmMPLL_AD_FUNC_CNTL                                                     0xaf0
++#define mmMPLL_DQ_FUNC_CNTL                                                     0xaf1
++#define mmMPLL_TIME                                                             0xaf2
++#define mmMPLL_SS1                                                              0xaf3
++#define mmMPLL_SS2                                                              0xaf4
++#define mmMPLL_CONTROL                                                          0xaf5
++#define mmMPLL_AD_STATUS                                                        0xaf6
++#define mmMPLL_DQ_0_0_STATUS                                                    0xaf7
++#define mmMPLL_DQ_0_1_STATUS                                                    0xaf8
++#define mmMPLL_DQ_1_0_STATUS                                                    0xaf9
++#define mmMPLL_DQ_1_1_STATUS                                                    0xafa
++#define mmMC_SEQ_PMG_PG_HWCNTL                                                  0xab9
++#define mmMC_SEQ_PMG_PG_SWCNTL_0                                                0xaba
++#define mmMC_SEQ_PMG_PG_SWCNTL_1                                                0xabb
++#define mmMC_SEQ_TSM_DEBUG_INDEX                                                0xacf
++#define mmMC_SEQ_TSM_DEBUG_DATA                                                 0xad0
++#define ixMC_TSM_DEBUG_GCNT                                                     0x0
++#define ixMC_TSM_DEBUG_FLAG                                                     0x1
++#define ixMC_TSM_DEBUG_MISC                                                     0x2
++#define ixMC_TSM_DEBUG_BCNT0                                                    0x3
++#define ixMC_TSM_DEBUG_BCNT1                                                    0x4
++#define ixMC_TSM_DEBUG_BCNT2                                                    0x5
++#define ixMC_TSM_DEBUG_BCNT3                                                    0x6
++#define ixMC_TSM_DEBUG_BCNT4                                                    0x7
++#define ixMC_TSM_DEBUG_BCNT5                                                    0x8
++#define ixMC_TSM_DEBUG_BCNT6                                                    0x9
++#define ixMC_TSM_DEBUG_BCNT7                                                    0xa
++#define ixMC_TSM_DEBUG_BCNT8                                                    0xb
++#define ixMC_TSM_DEBUG_BCNT9                                                    0xc
++#define ixMC_TSM_DEBUG_BCNT10                                                   0xd
++#define ixMC_TSM_DEBUG_ST01                                                     0x10
++#define ixMC_TSM_DEBUG_ST23                                                     0x11
++#define ixMC_TSM_DEBUG_ST45                                                     0x12
++#define ixMC_TSM_DEBUG_BKPT                                                     0x13
++#define mmMC_SEQ_IO_DEBUG_INDEX                                                 0xa91
++#define mmMC_SEQ_IO_DEBUG_DATA                                                  0xa92
++#define ixMC_IO_DEBUG_UP_0                                                      0x0
++#define ixMC_IO_DEBUG_UP_1                                                      0x1
++#define ixMC_IO_DEBUG_UP_2                                                      0x2
++#define ixMC_IO_DEBUG_UP_3                                                      0x3
++#define ixMC_IO_DEBUG_UP_4                                                      0x4
++#define ixMC_IO_DEBUG_UP_5                                                      0x5
++#define ixMC_IO_DEBUG_UP_6                                                      0x6
++#define ixMC_IO_DEBUG_UP_7                                                      0x7
++#define ixMC_IO_DEBUG_UP_8                                                      0x8
++#define ixMC_IO_DEBUG_UP_9                                                      0x9
++#define ixMC_IO_DEBUG_UP_10                                                     0xa
++#define ixMC_IO_DEBUG_UP_11                                                     0xb
++#define ixMC_IO_DEBUG_UP_12                                                     0xc
++#define ixMC_IO_DEBUG_UP_13                                                     0xd
++#define ixMC_IO_DEBUG_UP_14                                                     0xe
++#define ixMC_IO_DEBUG_UP_15                                                     0xf
++#define ixMC_IO_DEBUG_UP_16                                                     0x10
++#define ixMC_IO_DEBUG_UP_17                                                     0x11
++#define ixMC_IO_DEBUG_UP_18                                                     0x12
++#define ixMC_IO_DEBUG_UP_19                                                     0x13
++#define ixMC_IO_DEBUG_UP_20                                                     0x14
++#define ixMC_IO_DEBUG_UP_21                                                     0x15
++#define ixMC_IO_DEBUG_UP_22                                                     0x16
++#define ixMC_IO_DEBUG_UP_23                                                     0x17
++#define ixMC_IO_DEBUG_UP_24                                                     0x18
++#define ixMC_IO_DEBUG_UP_25                                                     0x19
++#define ixMC_IO_DEBUG_UP_26                                                     0x1a
++#define ixMC_IO_DEBUG_UP_27                                                     0x1b
++#define ixMC_IO_DEBUG_UP_28                                                     0x1c
++#define ixMC_IO_DEBUG_UP_29                                                     0x1d
++#define ixMC_IO_DEBUG_UP_30                                                     0x1e
++#define ixMC_IO_DEBUG_UP_31                                                     0x1f
++#define ixMC_IO_DEBUG_UP_32                                                     0x20
++#define ixMC_IO_DEBUG_UP_33                                                     0x21
++#define ixMC_IO_DEBUG_UP_34                                                     0x22
++#define ixMC_IO_DEBUG_UP_35                                                     0x23
++#define ixMC_IO_DEBUG_UP_36                                                     0x24
++#define ixMC_IO_DEBUG_UP_37                                                     0x25
++#define ixMC_IO_DEBUG_UP_38                                                     0x26
++#define ixMC_IO_DEBUG_UP_39                                                     0x27
++#define ixMC_IO_DEBUG_UP_40                                                     0x28
++#define ixMC_IO_DEBUG_UP_41                                                     0x29
++#define ixMC_IO_DEBUG_UP_42                                                     0x2a
++#define ixMC_IO_DEBUG_UP_43                                                     0x2b
++#define ixMC_IO_DEBUG_UP_44                                                     0x2c
++#define ixMC_IO_DEBUG_UP_45                                                     0x2d
++#define ixMC_IO_DEBUG_UP_46                                                     0x2e
++#define ixMC_IO_DEBUG_UP_47                                                     0x2f
++#define ixMC_IO_DEBUG_UP_48                                                     0x30
++#define ixMC_IO_DEBUG_UP_49                                                     0x31
++#define ixMC_IO_DEBUG_UP_50                                                     0x32
++#define ixMC_IO_DEBUG_UP_51                                                     0x33
++#define ixMC_IO_DEBUG_UP_52                                                     0x34
++#define ixMC_IO_DEBUG_UP_53                                                     0x35
++#define ixMC_IO_DEBUG_UP_54                                                     0x36
++#define ixMC_IO_DEBUG_UP_55                                                     0x37
++#define ixMC_IO_DEBUG_UP_56                                                     0x38
++#define ixMC_IO_DEBUG_UP_57                                                     0x39
++#define ixMC_IO_DEBUG_UP_58                                                     0x3a
++#define ixMC_IO_DEBUG_UP_59                                                     0x3b
++#define ixMC_IO_DEBUG_UP_60                                                     0x3c
++#define ixMC_IO_DEBUG_UP_61                                                     0x3d
++#define ixMC_IO_DEBUG_UP_62                                                     0x3e
++#define ixMC_IO_DEBUG_UP_63                                                     0x3f
++#define ixMC_IO_DEBUG_UP_64                                                     0x40
++#define ixMC_IO_DEBUG_UP_65                                                     0x41
++#define ixMC_IO_DEBUG_UP_66                                                     0x42
++#define ixMC_IO_DEBUG_UP_67                                                     0x43
++#define ixMC_IO_DEBUG_UP_68                                                     0x44
++#define ixMC_IO_DEBUG_UP_69                                                     0x45
++#define ixMC_IO_DEBUG_UP_70                                                     0x46
++#define ixMC_IO_DEBUG_UP_71                                                     0x47
++#define ixMC_IO_DEBUG_UP_72                                                     0x48
++#define ixMC_IO_DEBUG_UP_73                                                     0x49
++#define ixMC_IO_DEBUG_UP_74                                                     0x4a
++#define ixMC_IO_DEBUG_UP_75                                                     0x4b
++#define ixMC_IO_DEBUG_UP_76                                                     0x4c
++#define ixMC_IO_DEBUG_UP_77                                                     0x4d
++#define ixMC_IO_DEBUG_UP_78                                                     0x4e
++#define ixMC_IO_DEBUG_UP_79                                                     0x4f
++#define ixMC_IO_DEBUG_UP_80                                                     0x50
++#define ixMC_IO_DEBUG_UP_81                                                     0x51
++#define ixMC_IO_DEBUG_UP_82                                                     0x52
++#define ixMC_IO_DEBUG_UP_83                                                     0x53
++#define ixMC_IO_DEBUG_UP_84                                                     0x54
++#define ixMC_IO_DEBUG_UP_85                                                     0x55
++#define ixMC_IO_DEBUG_UP_86                                                     0x56
++#define ixMC_IO_DEBUG_UP_87                                                     0x57
++#define ixMC_IO_DEBUG_UP_88                                                     0x58
++#define ixMC_IO_DEBUG_UP_89                                                     0x59
++#define ixMC_IO_DEBUG_UP_90                                                     0x5a
++#define ixMC_IO_DEBUG_UP_91                                                     0x5b
++#define ixMC_IO_DEBUG_UP_92                                                     0x5c
++#define ixMC_IO_DEBUG_UP_93                                                     0x5d
++#define ixMC_IO_DEBUG_UP_94                                                     0x5e
++#define ixMC_IO_DEBUG_UP_95                                                     0x5f
++#define ixMC_IO_DEBUG_UP_96                                                     0x60
++#define ixMC_IO_DEBUG_UP_97                                                     0x61
++#define ixMC_IO_DEBUG_UP_98                                                     0x62
++#define ixMC_IO_DEBUG_UP_99                                                     0x63
++#define ixMC_IO_DEBUG_UP_100                                                    0x64
++#define ixMC_IO_DEBUG_UP_101                                                    0x65
++#define ixMC_IO_DEBUG_UP_102                                                    0x66
++#define ixMC_IO_DEBUG_UP_103                                                    0x67
++#define ixMC_IO_DEBUG_UP_104                                                    0x68
++#define ixMC_IO_DEBUG_UP_105                                                    0x69
++#define ixMC_IO_DEBUG_UP_106                                                    0x6a
++#define ixMC_IO_DEBUG_UP_107                                                    0x6b
++#define ixMC_IO_DEBUG_UP_108                                                    0x6c
++#define ixMC_IO_DEBUG_UP_109                                                    0x6d
++#define ixMC_IO_DEBUG_UP_110                                                    0x6e
++#define ixMC_IO_DEBUG_UP_111                                                    0x6f
++#define ixMC_IO_DEBUG_UP_112                                                    0x70
++#define ixMC_IO_DEBUG_UP_113                                                    0x71
++#define ixMC_IO_DEBUG_UP_114                                                    0x72
++#define ixMC_IO_DEBUG_UP_115                                                    0x73
++#define ixMC_IO_DEBUG_UP_116                                                    0x74
++#define ixMC_IO_DEBUG_UP_117                                                    0x75
++#define ixMC_IO_DEBUG_UP_118                                                    0x76
++#define ixMC_IO_DEBUG_UP_119                                                    0x77
++#define ixMC_IO_DEBUG_UP_120                                                    0x78
++#define ixMC_IO_DEBUG_UP_121                                                    0x79
++#define ixMC_IO_DEBUG_UP_122                                                    0x7a
++#define ixMC_IO_DEBUG_UP_123                                                    0x7b
++#define ixMC_IO_DEBUG_UP_124                                                    0x7c
++#define ixMC_IO_DEBUG_UP_125                                                    0x7d
++#define ixMC_IO_DEBUG_UP_126                                                    0x7e
++#define ixMC_IO_DEBUG_UP_127                                                    0x7f
++#define ixMC_IO_DEBUG_UP_128                                                    0x80
++#define ixMC_IO_DEBUG_UP_129                                                    0x81
++#define ixMC_IO_DEBUG_UP_130                                                    0x82
++#define ixMC_IO_DEBUG_UP_131                                                    0x83
++#define ixMC_IO_DEBUG_UP_132                                                    0x84
++#define ixMC_IO_DEBUG_UP_133                                                    0x85
++#define ixMC_IO_DEBUG_UP_134                                                    0x86
++#define ixMC_IO_DEBUG_UP_135                                                    0x87
++#define ixMC_IO_DEBUG_UP_136                                                    0x88
++#define ixMC_IO_DEBUG_UP_137                                                    0x89
++#define ixMC_IO_DEBUG_UP_138                                                    0x8a
++#define ixMC_IO_DEBUG_UP_139                                                    0x8b
++#define ixMC_IO_DEBUG_UP_140                                                    0x8c
++#define ixMC_IO_DEBUG_UP_141                                                    0x8d
++#define ixMC_IO_DEBUG_UP_142                                                    0x8e
++#define ixMC_IO_DEBUG_UP_143                                                    0x8f
++#define ixMC_IO_DEBUG_UP_144                                                    0x90
++#define ixMC_IO_DEBUG_UP_145                                                    0x91
++#define ixMC_IO_DEBUG_UP_146                                                    0x92
++#define ixMC_IO_DEBUG_UP_147                                                    0x93
++#define ixMC_IO_DEBUG_UP_148                                                    0x94
++#define ixMC_IO_DEBUG_UP_149                                                    0x95
++#define ixMC_IO_DEBUG_UP_150                                                    0x96
++#define ixMC_IO_DEBUG_UP_151                                                    0x97
++#define ixMC_IO_DEBUG_UP_152                                                    0x98
++#define ixMC_IO_DEBUG_UP_153                                                    0x99
++#define ixMC_IO_DEBUG_UP_154                                                    0x9a
++#define ixMC_IO_DEBUG_UP_155                                                    0x9b
++#define ixMC_IO_DEBUG_UP_156                                                    0x9c
++#define ixMC_IO_DEBUG_UP_157                                                    0x9d
++#define ixMC_IO_DEBUG_UP_158                                                    0x9e
++#define ixMC_IO_DEBUG_UP_159                                                    0x9f
++#define ixMC_IO_DEBUG_DQB0L_MISC_D0                                             0xa0
++#define ixMC_IO_DEBUG_DQB0H_MISC_D0                                             0xa1
++#define ixMC_IO_DEBUG_DQB1L_MISC_D0                                             0xa2
++#define ixMC_IO_DEBUG_DQB1H_MISC_D0                                             0xa3
++#define ixMC_IO_DEBUG_DQB2L_MISC_D0                                             0xa4
++#define ixMC_IO_DEBUG_DQB2H_MISC_D0                                             0xa5
++#define ixMC_IO_DEBUG_DQB3L_MISC_D0                                             0xa6
++#define ixMC_IO_DEBUG_DQB3H_MISC_D0                                             0xa7
++#define ixMC_IO_DEBUG_DBI_MISC_D0                                               0xa8
++#define ixMC_IO_DEBUG_EDC_MISC_D0                                               0xa9
++#define ixMC_IO_DEBUG_WCK_MISC_D0                                               0xaa
++#define ixMC_IO_DEBUG_CK_MISC_D0                                                0xab
++#define ixMC_IO_DEBUG_ADDRL_MISC_D0                                             0xac
++#define ixMC_IO_DEBUG_ADDRH_MISC_D0                                             0xad
++#define ixMC_IO_DEBUG_ACMD_MISC_D0                                              0xae
++#define ixMC_IO_DEBUG_CMD_MISC_D0                                               0xaf
++#define ixMC_IO_DEBUG_DQB0L_MISC_D1                                             0xb0
++#define ixMC_IO_DEBUG_DQB0H_MISC_D1                                             0xb1
++#define ixMC_IO_DEBUG_DQB1L_MISC_D1                                             0xb2
++#define ixMC_IO_DEBUG_DQB1H_MISC_D1                                             0xb3
++#define ixMC_IO_DEBUG_DQB2L_MISC_D1                                             0xb4
++#define ixMC_IO_DEBUG_DQB2H_MISC_D1                                             0xb5
++#define ixMC_IO_DEBUG_DQB3L_MISC_D1                                             0xb6
++#define ixMC_IO_DEBUG_DQB3H_MISC_D1                                             0xb7
++#define ixMC_IO_DEBUG_DBI_MISC_D1                                               0xb8
++#define ixMC_IO_DEBUG_EDC_MISC_D1                                               0xb9
++#define ixMC_IO_DEBUG_WCK_MISC_D1                                               0xba
++#define ixMC_IO_DEBUG_CK_MISC_D1                                                0xbb
++#define ixMC_IO_DEBUG_ADDRL_MISC_D1                                             0xbc
++#define ixMC_IO_DEBUG_ADDRH_MISC_D1                                             0xbd
++#define ixMC_IO_DEBUG_ACMD_MISC_D1                                              0xbe
++#define ixMC_IO_DEBUG_CMD_MISC_D1                                               0xbf
++#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0                                           0xc0
++#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0                                           0xc1
++#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0                                           0xc2
++#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0                                           0xc3
++#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0                                           0xc4
++#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0                                           0xc5
++#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0                                           0xc6
++#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0                                           0xc7
++#define ixMC_IO_DEBUG_DBI_CLKSEL_D0                                             0xc8
++#define ixMC_IO_DEBUG_EDC_CLKSEL_D0                                             0xc9
++#define ixMC_IO_DEBUG_WCK_CLKSEL_D0                                             0xca
++#define ixMC_IO_DEBUG_CK_CLKSEL_D0                                              0xcb
++#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0                                           0xcc
++#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0                                           0xcd
++#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0                                            0xce
++#define ixMC_IO_DEBUG_CMD_CLKSEL_D0                                             0xcf
++#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1                                           0xd0
++#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1                                           0xd1
++#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1                                           0xd2
++#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1                                           0xd3
++#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1                                           0xd4
++#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1                                           0xd5
++#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1                                           0xd6
++#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1                                           0xd7
++#define ixMC_IO_DEBUG_DBI_CLKSEL_D1                                             0xd8
++#define ixMC_IO_DEBUG_EDC_CLKSEL_D1                                             0xd9
++#define ixMC_IO_DEBUG_WCK_CLKSEL_D1                                             0xda
++#define ixMC_IO_DEBUG_CK_CLKSEL_D1                                              0xdb
++#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1                                           0xdc
++#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1                                           0xdd
++#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1                                            0xde
++#define ixMC_IO_DEBUG_CMD_CLKSEL_D1                                             0xdf
++#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0                                           0xe0
++#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0                                           0xe1
++#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0                                           0xe2
++#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0                                           0xe3
++#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0                                           0xe4
++#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0                                           0xe5
++#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0                                           0xe6
++#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0                                           0xe7
++#define ixMC_IO_DEBUG_DBI_OFSCAL_D0                                             0xe8
++#define ixMC_IO_DEBUG_EDC_OFSCAL_D0                                             0xe9
++#define ixMC_IO_DEBUG_WCK_OFSCAL_D0                                             0xea
++#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0                                           0xeb
++#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0                                          0xec
++#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0                                         0xed
++#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0                                            0xee
++#define ixMC_IO_DEBUG_CMD_OFSCAL_D0                                             0xef
++#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1                                           0xf0
++#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1                                           0xf1
++#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1                                           0xf2
++#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1                                           0xf3
++#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1                                           0xf4
++#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1                                           0xf5
++#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1                                           0xf6
++#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1                                           0xf7
++#define ixMC_IO_DEBUG_DBI_OFSCAL_D1                                             0xf8
++#define ixMC_IO_DEBUG_EDC_OFSCAL_D1                                             0xf9
++#define ixMC_IO_DEBUG_WCK_OFSCAL_D1                                             0xfa
++#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1                                           0xfb
++#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1                                          0xfc
++#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1                                         0xfd
++#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1                                            0xfe
++#define ixMC_IO_DEBUG_CMD_OFSCAL_D1                                             0xff
++#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0                                          0x100
++#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0                                          0x101
++#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0                                          0x102
++#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0                                          0x103
++#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0                                          0x104
++#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0                                          0x105
++#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0                                          0x106
++#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0                                          0x107
++#define ixMC_IO_DEBUG_DBI_RXPHASE_D0                                            0x108
++#define ixMC_IO_DEBUG_EDC_RXPHASE_D0                                            0x109
++#define ixMC_IO_DEBUG_WCK_RXPHASE_D0                                            0x10a
++#define ixMC_IO_DEBUG_CK_RXPHASE_D0                                             0x10b
++#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0                                          0x10c
++#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0                                          0x10d
++#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0                                           0x10e
++#define ixMC_IO_DEBUG_CMD_RXPHASE_D0                                            0x10f
++#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1                                          0x110
++#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1                                          0x111
++#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1                                          0x112
++#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1                                          0x113
++#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1                                          0x114
++#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1                                          0x115
++#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1                                          0x116
++#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1                                          0x117
++#define ixMC_IO_DEBUG_DBI_RXPHASE_D1                                            0x118
++#define ixMC_IO_DEBUG_EDC_RXPHASE_D1                                            0x119
++#define ixMC_IO_DEBUG_WCK_RXPHASE_D1                                            0x11a
++#define ixMC_IO_DEBUG_CK_RXPHASE_D1                                             0x11b
++#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1                                          0x11c
++#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1                                          0x11d
++#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1                                           0x11e
++#define ixMC_IO_DEBUG_CMD_RXPHASE_D1                                            0x11f
++#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0                                          0x120
++#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0                                          0x121
++#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0                                          0x122
++#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0                                          0x123
++#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0                                          0x124
++#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0                                          0x125
++#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0                                          0x126
++#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0                                          0x127
++#define ixMC_IO_DEBUG_DBI_TXPHASE_D0                                            0x128
++#define ixMC_IO_DEBUG_EDC_TXPHASE_D0                                            0x129
++#define ixMC_IO_DEBUG_WCK_TXPHASE_D0                                            0x12a
++#define ixMC_IO_DEBUG_CK_TXPHASE_D0                                             0x12b
++#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0                                          0x12c
++#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0                                          0x12d
++#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0                                           0x12e
++#define ixMC_IO_DEBUG_CMD_TXPHASE_D0                                            0x12f
++#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1                                          0x130
++#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1                                          0x131
++#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1                                          0x132
++#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1                                          0x133
++#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1                                          0x134
++#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1                                          0x135
++#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1                                          0x136
++#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1                                          0x137
++#define ixMC_IO_DEBUG_DBI_TXPHASE_D1                                            0x138
++#define ixMC_IO_DEBUG_EDC_TXPHASE_D1                                            0x139
++#define ixMC_IO_DEBUG_WCK_TXPHASE_D1                                            0x13a
++#define ixMC_IO_DEBUG_CK_TXPHASE_D1                                             0x13b
++#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1                                          0x13c
++#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1                                          0x13d
++#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1                                           0x13e
++#define ixMC_IO_DEBUG_CMD_TXPHASE_D1                                            0x13f
++#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0                                      0x140
++#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0                                      0x141
++#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0                                      0x142
++#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0                                      0x143
++#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0                                      0x144
++#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0                                      0x145
++#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0                                      0x146
++#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0                                      0x147
++#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0                                        0x148
++#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0                                        0x149
++#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0                                        0x14a
++#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0                                        0x14b
++#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0                                        0x14c
++#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0                                        0x14d
++#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0                                        0x14e
++#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0                                         0x14f
++#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1                                      0x150
++#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1                                      0x151
++#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1                                      0x152
++#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1                                      0x153
++#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1                                      0x154
++#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1                                      0x155
++#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1                                      0x156
++#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1                                      0x157
++#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1                                        0x158
++#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1                                        0x159
++#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1                                        0x15a
++#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1                                        0x15b
++#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1                                        0x15c
++#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1                                        0x15d
++#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1                                        0x15e
++#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1                                         0x15f
++#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0                                            0x160
++#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0                                            0x161
++#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0                                            0x162
++#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0                                            0x163
++#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0                                            0x164
++#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0                                            0x165
++#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0                                            0x166
++#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0                                            0x167
++#define ixMC_IO_DEBUG_DBI_TXSLF_D0                                              0x168
++#define ixMC_IO_DEBUG_EDC_TXSLF_D0                                              0x169
++#define ixMC_IO_DEBUG_WCK_TXSLF_D0                                              0x16a
++#define ixMC_IO_DEBUG_CK_TXSLF_D0                                               0x16b
++#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0                                            0x16c
++#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0                                            0x16d
++#define ixMC_IO_DEBUG_ACMD_TXSLF_D0                                             0x16e
++#define ixMC_IO_DEBUG_CMD_TXSLF_D0                                              0x16f
++#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1                                            0x170
++#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1                                            0x171
++#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1                                            0x172
++#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1                                            0x173
++#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1                                            0x174
++#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1                                            0x175
++#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1                                            0x176
++#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1                                            0x177
++#define ixMC_IO_DEBUG_DBI_TXSLF_D1                                              0x178
++#define ixMC_IO_DEBUG_EDC_TXSLF_D1                                              0x179
++#define ixMC_IO_DEBUG_WCK_TXSLF_D1                                              0x17a
++#define ixMC_IO_DEBUG_CK_TXSLF_D1                                               0x17b
++#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1                                            0x17c
++#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1                                            0x17d
++#define ixMC_IO_DEBUG_ACMD_TXSLF_D1                                             0x17e
++#define ixMC_IO_DEBUG_CMD_TXSLF_D1                                              0x17f
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0                                         0x180
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0                                         0x181
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0                                         0x182
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0                                         0x183
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0                                         0x184
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0                                         0x185
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0                                         0x186
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0                                         0x187
++#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0                                           0x188
++#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0                                           0x189
++#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0                                           0x18a
++#define ixMC_IO_DEBUG_CK_TXBST_PD_D0                                            0x18b
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0                                         0x18c
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0                                         0x18d
++#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0                                          0x18e
++#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0                                           0x18f
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1                                         0x190
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1                                         0x191
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1                                         0x192
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1                                         0x193
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1                                         0x194
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1                                         0x195
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1                                         0x196
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1                                         0x197
++#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1                                           0x198
++#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1                                           0x199
++#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1                                           0x19a
++#define ixMC_IO_DEBUG_CK_TXBST_PD_D1                                            0x19b
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1                                         0x19c
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1                                         0x19d
++#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1                                          0x19e
++#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1                                           0x19f
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0                                         0x1a0
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0                                         0x1a1
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0                                         0x1a2
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0                                         0x1a3
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0                                         0x1a4
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0                                         0x1a5
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0                                         0x1a6
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0                                         0x1a7
++#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0                                           0x1a8
++#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0                                           0x1a9
++#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0                                           0x1aa
++#define ixMC_IO_DEBUG_CK_TXBST_PU_D0                                            0x1ab
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0                                         0x1ac
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0                                         0x1ad
++#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0                                          0x1ae
++#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0                                           0x1af
++#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1                                         0x1b0
++#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1                                         0x1b1
++#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1                                         0x1b2
++#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1                                         0x1b3
++#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1                                         0x1b4
++#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1                                         0x1b5
++#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1                                         0x1b6
++#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1                                         0x1b7
++#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1                                           0x1b8
++#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1                                           0x1b9
++#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1                                           0x1ba
++#define ixMC_IO_DEBUG_CK_TXBST_PU_D1                                            0x1bb
++#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1                                         0x1bc
++#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1                                         0x1bd
++#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1                                          0x1be
++#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1                                           0x1bf
++#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0                                            0x1c0
++#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0                                            0x1c1
++#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0                                            0x1c2
++#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0                                            0x1c3
++#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0                                            0x1c4
++#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0                                            0x1c5
++#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0                                            0x1c6
++#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0                                            0x1c7
++#define ixMC_IO_DEBUG_DBI_RX_EQ_D0                                              0x1c8
++#define ixMC_IO_DEBUG_EDC_RX_EQ_D0                                              0x1c9
++#define ixMC_IO_DEBUG_WCK_RX_EQ_D0                                              0x1ca
++#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0                                           0x1cb
++#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0                                           0x1cc
++#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0                                          0x1cd
++#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0                                          0x1ce
++#define ixMC_IO_DEBUG_CMD_RX_EQ_D0                                              0x1cf
++#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1                                            0x1d0
++#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1                                            0x1d1
++#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1                                            0x1d2
++#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1                                            0x1d3
++#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1                                            0x1d4
++#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1                                            0x1d5
++#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1                                            0x1d6
++#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1                                            0x1d7
++#define ixMC_IO_DEBUG_DBI_RX_EQ_D1                                              0x1d8
++#define ixMC_IO_DEBUG_EDC_RX_EQ_D1                                              0x1d9
++#define ixMC_IO_DEBUG_WCK_RX_EQ_D1                                              0x1da
++#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1                                           0x1db
++#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1                                           0x1dc
++#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1                                          0x1dd
++#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1                                          0x1de
++#define ixMC_IO_DEBUG_CMD_RX_EQ_D1                                              0x1df
++#define ixMC_IO_DEBUG_WCDR_MISC_D0                                              0x1e0
++#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0                                            0x1e1
++#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0                                            0x1e2
++#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0                                           0x1e3
++#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0                                           0x1e4
++#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0                                       0x1e5
++#define ixMC_IO_DEBUG_WCDR_TXSLF_D0                                             0x1e6
++#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0                                          0x1e7
++#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0                                          0x1e8
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0                                             0x1e9
++#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0                                        0x1ea
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0                                          0x1eb
++#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0                                         0x1ec
++#define ixMC_IO_DEBUG_WCDR_MISC_D1                                              0x1f0
++#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1                                            0x1f1
++#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1                                            0x1f2
++#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1                                           0x1f3
++#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1                                           0x1f4
++#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1                                       0x1f5
++#define ixMC_IO_DEBUG_WCDR_TXSLF_D1                                             0x1f6
++#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1                                          0x1f7
++#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1                                          0x1f8
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1                                             0x1f9
++#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1                                        0x1fa
++#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1                                          0x1fb
++#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1                                         0x1fc
++#define mmMC_SEQ_CNTL_3                                                         0xd80
++#define mmMC_SEQ_G5PDX_CTRL                                                     0xd81
++#define mmMC_SEQ_G5PDX_CTRL_LP                                                  0xd82
++#define mmMC_SEQ_G5PDX_CMD0                                                     0xd83
++#define mmMC_SEQ_G5PDX_CMD0_LP                                                  0xd84
++#define mmMC_SEQ_G5PDX_CMD1                                                     0xd85
++#define mmMC_SEQ_G5PDX_CMD1_LP                                                  0xd86
++#define mmMC_SEQ_SREG_READ                                                      0xd87
++#define mmMC_SEQ_SREG_STATUS                                                    0xd88
++#define mmMC_SEQ_PHYREG_BCAST                                                   0xd89
++#define mmMC_SEQ_PMG_DVS_CTL                                                    0xd8a
++#define mmMC_SEQ_PMG_DVS_CTL_LP                                                 0xd8b
++#define mmMC_SEQ_PMG_DVS_CMD                                                    0xd8c
++#define mmMC_SEQ_PMG_DVS_CMD_LP                                                 0xd8d
++#define mmMC_SEQ_DLL_STBY                                                       0xd8e
++#define mmMC_SEQ_DLL_STBY_LP                                                    0xd8f
++#define mmMC_DLB_MISCCTRL0                                                      0xd90
++#define mmMC_DLB_MISCCTRL1                                                      0xd91
++#define mmMC_DLB_MISCCTRL2                                                      0xd92
++#define mmMC_DLB_CONFIG0                                                        0xd93
++#define mmMC_DLB_CONFIG1                                                        0xd94
++#define mmMC_DLB_SETUP                                                          0xd95
++#define mmMC_DLB_SETUPSWEEP                                                     0xd96
++#define mmMC_DLB_SETUPFIFO                                                      0xd97
++#define mmMC_DLB_WRITE_MASK                                                     0xd98
++#define mmMC_DLB_STATUS                                                         0xd99
++#define mmMC_DLB_STATUS_MISC0                                                   0xd9a
++#define mmMC_DLB_STATUS_MISC1                                                   0xd9b
++#define mmMC_DLB_STATUS_MISC2                                                   0xd9c
++#define mmMC_DLB_STATUS_MISC3                                                   0xd9d
++#define mmMC_DLB_STATUS_MISC4                                                   0xd9e
++#define mmMC_DLB_STATUS_MISC5                                                   0xd9f
++#define mmMC_DLB_STATUS_MISC6                                                   0xda0
++#define mmMC_DLB_STATUS_MISC7                                                   0xda1
++#define mmMC_ARB_HARSH_EN_RD                                                    0xdc0
++#define mmMC_ARB_HARSH_EN_WR                                                    0xdc1
++#define mmMC_ARB_HARSH_TX_HI0_RD                                                0xdc2
++#define mmMC_ARB_HARSH_TX_HI0_WR                                                0xdc3
++#define mmMC_ARB_HARSH_TX_HI1_RD                                                0xdc4
++#define mmMC_ARB_HARSH_TX_HI1_WR                                                0xdc5
++#define mmMC_ARB_HARSH_TX_LO0_RD                                                0xdc6
++#define mmMC_ARB_HARSH_TX_LO0_WR                                                0xdc7
++#define mmMC_ARB_HARSH_TX_LO1_RD                                                0xdc8
++#define mmMC_ARB_HARSH_TX_LO1_WR                                                0xdc9
++#define mmMC_ARB_HARSH_BWPERIOD0_RD                                             0xdca
++#define mmMC_ARB_HARSH_BWPERIOD0_WR                                             0xdcb
++#define mmMC_ARB_HARSH_BWPERIOD1_RD                                             0xdcc
++#define mmMC_ARB_HARSH_BWPERIOD1_WR                                             0xdcd
++#define mmMC_ARB_HARSH_BWCNT0_RD                                                0xdce
++#define mmMC_ARB_HARSH_BWCNT0_WR                                                0xdcf
++#define mmMC_ARB_HARSH_BWCNT1_RD                                                0xdd0
++#define mmMC_ARB_HARSH_BWCNT1_WR                                                0xdd1
++#define mmMC_ARB_HARSH_SAT0_RD                                                  0xdd2
++#define mmMC_ARB_HARSH_SAT0_WR                                                  0xdd3
++#define mmMC_ARB_HARSH_SAT1_RD                                                  0xdd4
++#define mmMC_ARB_HARSH_SAT1_WR                                                  0xdd5
++#define mmMC_ARB_HARSH_CTL_RD                                                   0xdd6
++#define mmMC_ARB_HARSH_CTL_WR                                                   0xdd7
++#define mmMC_ARB_GRUB_PRIORITY1_RD                                              0xdd8
++#define mmMC_ARB_GRUB_PRIORITY1_WR                                              0xdd9
++#define mmMC_ARB_GRUB_PRIORITY2_RD                                              0xdda
++#define mmMC_ARB_GRUB_PRIORITY2_WR                                              0xddb
++#define mmMCIF_WB_BUFMGR_SW_CONTROL                                             0x5e78
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5e78
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5eb8
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5ef8
++#define mmMCIF_WB_BUFMGR_CUR_LINE_R                                             0x5e79
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                                    0x5e79
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                                    0x5eb9
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                                    0x5ef9
++#define mmMCIF_WB_BUFMGR_STATUS                                                 0x5e7a
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                                        0x5e7a
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                                        0x5eba
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                                        0x5efa
++#define mmMCIF_WB_BUF_PITCH                                                     0x5e7b
++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH                                            0x5e7b
++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH                                            0x5ebb
++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH                                            0x5efb
++#define mmMCIF_WB_BUF_1_STATUS                                                  0x5e7c
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                                         0x5e7c
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                                         0x5ebc
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                                         0x5efc
++#define mmMCIF_WB_BUF_1_STATUS2                                                 0x5e7d
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                                        0x5e7d
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                                        0x5ebd
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                                        0x5efd
++#define mmMCIF_WB_BUF_2_STATUS                                                  0x5e7e
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                                         0x5e7e
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                                         0x5ebe
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                                         0x5efe
++#define mmMCIF_WB_BUF_2_STATUS2                                                 0x5e7f
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                                        0x5e7f
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                                        0x5ebf
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                                        0x5eff
++#define mmMCIF_WB_BUF_3_STATUS                                                  0x5e80
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                                         0x5e80
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                                         0x5ec0
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                                         0x5f00
++#define mmMCIF_WB_BUF_3_STATUS2                                                 0x5e81
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                                        0x5e81
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                                        0x5ec1
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                                        0x5f01
++#define mmMCIF_WB_BUF_4_STATUS                                                  0x5e82
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                                         0x5e82
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                                         0x5ec2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                                         0x5f02
++#define mmMCIF_WB_BUF_4_STATUS2                                                 0x5e83
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                                        0x5e83
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                                        0x5ec3
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                                        0x5f03
++#define mmMCIF_WB_ARBITRATION_CONTROL                                           0x5e84
++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                                  0x5e84
++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                                  0x5ec4
++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                                  0x5f04
++#define mmMCIF_WB_URGENCY_WATERMARK                                             0x5e85
++#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK                                    0x5e85
++#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK                                    0x5ec5
++#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK                                    0x5f05
++#define mmMCIF_WB_TEST_DEBUG_INDEX                                              0x5e86
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                                     0x5e86
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                                     0x5ec6
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                                     0x5f06
++#define mmMCIF_WB_TEST_DEBUG_DATA                                               0x5e87
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                                      0x5e87
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                                      0x5ec7
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                                      0x5f07
++#define mmMCIF_WB_BUF_1_ADDR_Y                                                  0x5e88
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                                         0x5e88
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                                         0x5ec8
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                                         0x5f08
++#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET                                           0x5e89
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                  0x5e89
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                  0x5ec9
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                  0x5f09
++#define mmMCIF_WB_BUF_1_ADDR_C                                                  0x5e8a
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                                         0x5e8a
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                                         0x5eca
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                                         0x5f0a
++#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET                                           0x5e8b
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                                  0x5e8b
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                                  0x5ecb
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                                  0x5f0b
++#define mmMCIF_WB_BUF_2_ADDR_Y                                                  0x5e8c
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                                         0x5e8c
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                                         0x5ecc
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                                         0x5f0c
++#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET                                           0x5e8d
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                  0x5e8d
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                  0x5ecd
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                  0x5f0d
++#define mmMCIF_WB_BUF_2_ADDR_C                                                  0x5e8e
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                                         0x5e8e
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                                         0x5ece
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                                         0x5f0e
++#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET                                           0x5e8f
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                                  0x5e8f
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                                  0x5ecf
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                                  0x5f0f
++#define mmMCIF_WB_BUF_3_ADDR_Y                                                  0x5e90
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                                         0x5e90
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                                         0x5ed0
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                                         0x5f10
++#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET                                           0x5e91
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                  0x5e91
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                  0x5ed1
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                  0x5f11
++#define mmMCIF_WB_BUF_3_ADDR_C                                                  0x5e92
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                                         0x5e92
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                                         0x5ed2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                                         0x5f12
++#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET                                           0x5e93
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                                  0x5e93
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                                  0x5ed3
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                                  0x5f13
++#define mmMCIF_WB_BUF_4_ADDR_Y                                                  0x5e94
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                                         0x5e94
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                                         0x5ed4
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                                         0x5f14
++#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET                                           0x5e95
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                  0x5e95
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                  0x5ed5
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                  0x5f15
++#define mmMCIF_WB_BUF_4_ADDR_C                                                  0x5e96
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                                         0x5e96
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                                         0x5ed6
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                                         0x5f16
++#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET                                           0x5e97
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                                  0x5e97
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                                  0x5ed7
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                                  0x5f17
++#define mmMCIF_WB_BUFMGR_VCE_CONTROL                                            0x5e98
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                                   0x5e98
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                                   0x5ed8
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                                   0x5f18
++#define mmMCIF_WB_HVVMID_CONTROL                                                0x5e99
++#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL                                       0x5e99
++#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL                                       0x5ed9
++#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL                                       0x5f19
++
++#endif /* GMC_8_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
+new file mode 100644
+index 0000000..05b80f2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
+@@ -0,0 +1,1198 @@
++/*
++ * GMC_8_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_8_1_ENUM_H
++#define GMC_8_1_ENUM_H
++
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
++	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
++	DBG_CLIENT_BLKID_bci0                            = 0xe,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
++	DBG_CLIENT_BLKID_cb100                           = 0x10,
++	DBG_CLIENT_BLKID_cb001                           = 0x11,
++	DBG_CLIENT_BLKID_mcd4                            = 0x12,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
++	DBG_CLIENT_BLKID_cb101                           = 0x14,
++	DBG_CLIENT_BLKID_sx10                            = 0x15,
++	DBG_CLIENT_BLKID_cb301                           = 0x16,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
++	DBG_CLIENT_BLKID_scf1                            = 0x1c,
++	DBG_CLIENT_BLKID_sx20                            = 0x1d,
++	DBG_CLIENT_BLKID_spim1                           = 0x1e,
++	DBG_CLIENT_BLKID_pa10                            = 0x1f,
++	DBG_CLIENT_BLKID_pa00                            = 0x20,
++	DBG_CLIENT_BLKID_gmcon                           = 0x21,
++	DBG_CLIENT_BLKID_mcb                             = 0x22,
++	DBG_CLIENT_BLKID_vgt0                            = 0x23,
++	DBG_CLIENT_BLKID_pc0                             = 0x24,
++	DBG_CLIENT_BLKID_bci2                            = 0x25,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
++	DBG_CLIENT_BLKID_spim3                           = 0x27,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
++	DBG_CLIENT_BLKID_cb000                           = 0x2e,
++	DBG_CLIENT_BLKID_spim0                           = 0x2f,
++	DBG_CLIENT_BLKID_mcc2                            = 0x30,
++	DBG_CLIENT_BLKID_ds0                             = 0x31,
++	DBG_CLIENT_BLKID_srbm                            = 0x32,
++	DBG_CLIENT_BLKID_ih                              = 0x33,
++	DBG_CLIENT_BLKID_sem                             = 0x34,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
++	DBG_CLIENT_BLKID_hdp                             = 0x37,
++	DBG_CLIENT_BLKID_acp_0                           = 0x38,
++	DBG_CLIENT_BLKID_acp_1                           = 0x39,
++	DBG_CLIENT_BLKID_cb200                           = 0x3a,
++	DBG_CLIENT_BLKID_scf3                            = 0x3b,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
++	DBG_CLIENT_BLKID_bci3                            = 0x41,
++	DBG_CLIENT_BLKID_mcd0                            = 0x42,
++	DBG_CLIENT_BLKID_pa11                            = 0x43,
++	DBG_CLIENT_BLKID_pa01                            = 0x44,
++	DBG_CLIENT_BLKID_cb201                           = 0x45,
++	DBG_CLIENT_BLKID_spim2                           = 0x46,
++	DBG_CLIENT_BLKID_vgt2                            = 0x47,
++	DBG_CLIENT_BLKID_pc2                             = 0x48,
++	DBG_CLIENT_BLKID_smu_0                           = 0x49,
++	DBG_CLIENT_BLKID_smu_1                           = 0x4a,
++	DBG_CLIENT_BLKID_smu_2                           = 0x4b,
++	DBG_CLIENT_BLKID_cb1                             = 0x4c,
++	DBG_CLIENT_BLKID_ia0                             = 0x4d,
++	DBG_CLIENT_BLKID_wd                              = 0x4e,
++	DBG_CLIENT_BLKID_ia1                             = 0x4f,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
++	DBG_CLIENT_BLKID_scf0                            = 0x51,
++	DBG_CLIENT_BLKID_vgt1                            = 0x52,
++	DBG_CLIENT_BLKID_pc1                             = 0x53,
++	DBG_CLIENT_BLKID_cb0                             = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
++	DBG_CLIENT_BLKID_vgt3                            = 0x7a,
++	DBG_CLIENT_BLKID_pc3                             = 0x7b,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
++	DBG_CLIENT_BLKID_cb300                           = 0x84,
++	DBG_CLIENT_BLKID_mcd1                            = 0x85,
++	DBG_CLIENT_BLKID_sx00                            = 0x86,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
++	DBG_CLIENT_BLKID_mcc3                            = 0x89,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
++	DBG_CLIENT_BLKID_gck                             = 0x8c,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8d,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
++	DBG_CLIENT_BLKID_rlc                             = 0x90,
++	DBG_CLIENT_BLKID_grbm                            = 0x91,
++	DBG_CLIENT_BLKID_sammsp                          = 0x92,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x93,
++	DBG_CLIENT_BLKID_dci_0                           = 0x94,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* GMC_8_1_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h
+new file mode 100644
+index 0000000..7d3963f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h
+@@ -0,0 +1,15682 @@
++/*
++ * GMC_8_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_8_1_SH_MASK_H
++#define GMC_8_1_SH_MASK_H
++
++#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
++#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
++#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
++#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
++#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
++#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
++#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7
++#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0
++#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
++#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3
++#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70
++#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4
++#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80
++#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7
++#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00
++#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
++#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000
++#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
++#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
++#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
++#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000
++#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
++#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000
++#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf
++#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000
++#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
++#define MC_ARB_FED_CNTL__MODE_MASK 0x3
++#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
++#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
++#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
++#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
++#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
++#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
++#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
++#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
++#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
++#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
++#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
++#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
++#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
++#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
++#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
++#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
++#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
++#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
++#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
++#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
++#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
++#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
++#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
++#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
++#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
++#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
++#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
++#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
++#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
++#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
++#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
++#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
++#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
++#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
++#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
++#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
++#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
++#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
++#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
++#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
++#define MC_ARB_PERF_CID__CH0_MASK 0xff
++#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
++#define MC_ARB_PERF_CID__CH1_MASK 0xff00
++#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
++#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
++#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
++#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
++#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
++#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7
++#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0
++#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8
++#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3
++#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70
++#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4
++#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80
++#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7
++#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700
++#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8
++#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800
++#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb
++#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000
++#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc
++#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000
++#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf
++#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000
++#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10
++#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000
++#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18
++#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff
++#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0
++#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00
++#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8
++#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000
++#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10
++#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000
++#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18
++#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000
++#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a
++#define MC_ARB_GECC2__ENABLE_MASK 0x1
++#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
++#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
++#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
++#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
++#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
++#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
++#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
++#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
++#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
++#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
++#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
++#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
++#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
++#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
++#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
++#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
++#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
++#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
++#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
++#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
++#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
++#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
++#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
++#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
++#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
++#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
++#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
++#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
++#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
++#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
++#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
++#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8
++#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3
++#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10
++#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4
++#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0
++#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5
++#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff
++#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0
++#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00
++#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18
++#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
++#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
++#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
++#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
++#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
++#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
++#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
++#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
++#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
++#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
++#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
++#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
++#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
++#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
++#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
++#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
++#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
++#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
++#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
++#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
++#define MC_ARB_MISC2__GECC_MASK 0x40000
++#define MC_ARB_MISC2__GECC__SHIFT 0x12
++#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
++#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
++#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
++#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
++#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
++#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
++#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
++#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
++#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
++#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
++#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
++#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
++#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
++#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
++#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
++#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
++#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
++#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
++#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
++#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
++#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
++#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
++#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
++#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
++#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
++#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
++#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
++#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
++#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
++#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
++#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
++#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
++#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
++#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
++#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
++#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
++#define MC_ARB_BANKMAP__BANK0_MASK 0xf
++#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
++#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
++#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
++#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
++#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
++#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
++#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
++#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
++#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
++#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
++#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
++#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
++#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
++#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
++#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
++#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
++#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
++#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
++#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
++#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
++#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
++#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
++#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
++#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
++#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
++#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
++#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
++#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
++#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
++#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
++#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
++#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
++#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
++#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
++#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
++#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
++#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
++#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
++#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
++#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
++#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
++#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
++#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
++#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
++#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
++#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
++#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
++#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
++#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
++#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
++#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
++#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
++#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
++#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
++#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
++#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
++#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
++#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
++#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
++#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
++#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
++#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
++#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
++#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
++#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
++#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
++#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
++#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
++#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
++#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
++#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
++#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
++#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE_MASK 0x20000
++#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE__SHIFT 0x11
++#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
++#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
++#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
++#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
++#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
++#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
++#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
++#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
++#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
++#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
++#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
++#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
++#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
++#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
++#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000
++#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10
++#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000
++#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11
++#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
++#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
++#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
++#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
++#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
++#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
++#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000
++#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18
++#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000
++#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
++#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
++#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000
++#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19
++#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000
++#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a
++#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
++#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
++#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
++#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
++#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
++#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
++#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
++#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
++#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
++#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
++#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
++#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
++#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
++#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
++#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
++#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
++#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
++#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
++#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
++#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
++#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
++#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
++#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
++#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
++#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
++#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
++#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1
++#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2
++#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1
++#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4
++#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8
++#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3
++#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10
++#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4
++#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20
++#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5
++#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40
++#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6
++#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80
++#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7
++#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100
++#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8
++#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200
++#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400
++#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd
++#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000
++#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe
++#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000
++#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf
++#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000
++#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10
++#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000
++#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11
++#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000
++#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12
++#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000
++#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13
++#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000
++#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14
++#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000
++#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15
++#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000
++#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16
++#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000
++#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17
++#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000
++#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18
++#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000
++#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b
++#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000
++#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c
++#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000
++#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
++#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000
++#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e
++#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000
++#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f
++#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
++#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
++#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
++#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
++#define MC_ARB_CG__RSV_0_MASK 0xff0000
++#define MC_ARB_CG__RSV_0__SHIFT 0x10
++#define MC_ARB_CG__RSV_1_MASK 0xff000000
++#define MC_ARB_CG__RSV_1__SHIFT 0x18
++#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1
++#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2
++#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1
++#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4
++#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8
++#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3
++#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10
++#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4
++#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20
++#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5
++#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40
++#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6
++#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80
++#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7
++#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100
++#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8
++#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200
++#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9
++#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400
++#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa
++#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800
++#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb
++#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000
++#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc
++#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000
++#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd
++#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000
++#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe
++#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000
++#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf
++#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000
++#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10
++#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000
++#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11
++#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000
++#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12
++#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000
++#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13
++#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000
++#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14
++#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000
++#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15
++#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000
++#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16
++#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000
++#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19
++#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000
++#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a
++#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000
++#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b
++#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000
++#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c
++#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000
++#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
++#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000
++#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e
++#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000
++#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f
++#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
++#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
++#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
++#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
++#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
++#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
++#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
++#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
++#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
++#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
++#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
++#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
++#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
++#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
++#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
++#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
++#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
++#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
++#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
++#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
++#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
++#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
++#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
++#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
++#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
++#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
++#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
++#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
++#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
++#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
++#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
++#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
++#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
++#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
++#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
++#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
++#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
++#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
++#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
++#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
++#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
++#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
++#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
++#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
++#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
++#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
++#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
++#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
++#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000
++#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000
++#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19
++#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
++#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
++#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
++#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
++#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
++#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
++#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
++#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
++#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
++#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
++#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
++#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
++#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff
++#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0
++#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00
++#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8
++#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000
++#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10
++#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000
++#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11
++#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000
++#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12
++#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000
++#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13
++#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000
++#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14
++#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000
++#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15
++#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000
++#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16
++#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000
++#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17
++#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000
++#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c
++#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
++#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
++#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
++#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
++#define MC_ARB_BURST_TIME__TRRDS0_MASK 0x7c00
++#define MC_ARB_BURST_TIME__TRRDS0__SHIFT 0xa
++#define MC_ARB_BURST_TIME__TRRDS1_MASK 0xf8000
++#define MC_ARB_BURST_TIME__TRRDS1__SHIFT 0xf
++#define MC_ARB_BURST_TIME__TRRDL0_MASK 0x1f00000
++#define MC_ARB_BURST_TIME__TRRDL0__SHIFT 0x14
++#define MC_ARB_BURST_TIME__TRRDL1_MASK 0x3e000000
++#define MC_ARB_BURST_TIME__TRRDL1__SHIFT 0x19
++#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
++#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
++#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
++#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
++#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
++#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
++#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
++#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
++#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
++#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
++#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
++#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
++#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
++#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
++#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
++#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
++#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
++#define MC_CG_CONFIG__INDEX__SHIFT 0x6
++#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
++#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
++#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
++#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
++#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
++#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
++#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
++#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
++#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
++#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
++#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
++#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
++#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
++#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
++#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
++#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
++#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
++#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
++#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
++#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
++#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
++#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
++#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
++#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
++#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
++#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
++#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000
++#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
++#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_RD_GRP_EXT__TC0_MASK 0xf0
++#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
++#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_WR_GRP_EXT__TC0_MASK 0xf0
++#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
++#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
++#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
++#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
++#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
++#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
++#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
++#define MC_WR_TC0__ENABLE_MASK 0x1
++#define MC_WR_TC0__ENABLE__SHIFT 0x0
++#define MC_WR_TC0__PRESCALE_MASK 0x6
++#define MC_WR_TC0__PRESCALE__SHIFT 0x1
++#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC0__STALL_MODE_MASK 0x30
++#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC0__MAX_BURST_MASK 0x780
++#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_TC1__ENABLE_MASK 0x1
++#define MC_WR_TC1__ENABLE__SHIFT 0x0
++#define MC_WR_TC1__PRESCALE_MASK 0x6
++#define MC_WR_TC1__PRESCALE__SHIFT 0x1
++#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC1__STALL_MODE_MASK 0x30
++#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC1__MAX_BURST_MASK 0x780
++#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
++#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff
++#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_RD_CB__ENABLE_MASK 0x1
++#define MC_RD_CB__ENABLE__SHIFT 0x0
++#define MC_RD_CB__PRESCALE_MASK 0x6
++#define MC_RD_CB__PRESCALE__SHIFT 0x1
++#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_CB__STALL_MODE_MASK 0x30
++#define MC_RD_CB__STALL_MODE__SHIFT 0x4
++#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_CB__MAX_BURST_MASK 0x780
++#define MC_RD_CB__MAX_BURST__SHIFT 0x7
++#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_DB__ENABLE_MASK 0x1
++#define MC_RD_DB__ENABLE__SHIFT 0x0
++#define MC_RD_DB__PRESCALE_MASK 0x6
++#define MC_RD_DB__PRESCALE__SHIFT 0x1
++#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_DB__STALL_MODE_MASK 0x30
++#define MC_RD_DB__STALL_MODE__SHIFT 0x4
++#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_DB__MAX_BURST_MASK 0x780
++#define MC_RD_DB__MAX_BURST__SHIFT 0x7
++#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC0__ENABLE_MASK 0x1
++#define MC_RD_TC0__ENABLE__SHIFT 0x0
++#define MC_RD_TC0__PRESCALE_MASK 0x6
++#define MC_RD_TC0__PRESCALE__SHIFT 0x1
++#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC0__STALL_MODE_MASK 0x30
++#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC0__MAX_BURST_MASK 0x780
++#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC1__ENABLE_MASK 0x1
++#define MC_RD_TC1__ENABLE__SHIFT 0x0
++#define MC_RD_TC1__PRESCALE_MASK 0x6
++#define MC_RD_TC1__PRESCALE__SHIFT 0x1
++#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC1__STALL_MODE_MASK 0x30
++#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC1__MAX_BURST_MASK 0x780
++#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_HUB__ENABLE_MASK 0x1
++#define MC_RD_HUB__ENABLE__SHIFT 0x0
++#define MC_RD_HUB__PRESCALE_MASK 0x6
++#define MC_RD_HUB__PRESCALE__SHIFT 0x1
++#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_HUB__STALL_MODE_MASK 0x30
++#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
++#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_HUB__MAX_BURST_MASK 0x780
++#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
++#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_CB__ENABLE_MASK 0x1
++#define MC_WR_CB__ENABLE__SHIFT 0x0
++#define MC_WR_CB__PRESCALE_MASK 0x6
++#define MC_WR_CB__PRESCALE__SHIFT 0x1
++#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_CB__STALL_MODE_MASK 0x30
++#define MC_WR_CB__STALL_MODE__SHIFT 0x4
++#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_CB__MAX_BURST_MASK 0x780
++#define MC_WR_CB__MAX_BURST__SHIFT 0x7
++#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_DB__ENABLE_MASK 0x1
++#define MC_WR_DB__ENABLE__SHIFT 0x0
++#define MC_WR_DB__PRESCALE_MASK 0x6
++#define MC_WR_DB__PRESCALE__SHIFT 0x1
++#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_DB__STALL_MODE_MASK 0x30
++#define MC_WR_DB__STALL_MODE__SHIFT 0x4
++#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_DB__MAX_BURST_MASK 0x780
++#define MC_WR_DB__MAX_BURST__SHIFT 0x7
++#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_HUB__ENABLE_MASK 0x1
++#define MC_WR_HUB__ENABLE__SHIFT 0x0
++#define MC_WR_HUB__PRESCALE_MASK 0x6
++#define MC_WR_HUB__PRESCALE__SHIFT 0x1
++#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_HUB__STALL_MODE_MASK 0x30
++#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
++#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_HUB__MAX_BURST_MASK 0x780
++#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
++#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
++#define MC_RD_GRP_LCL__CB0_MASK 0xf000
++#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
++#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
++#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
++#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
++#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
++#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
++#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
++#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
++#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
++#define MC_WR_GRP_LCL__CB0_MASK 0xf
++#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
++#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
++#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
++#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
++#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
++#define MC_WR_GRP_LCL__DB0_MASK 0xf000
++#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
++#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
++#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
++#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
++#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
++#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
++#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
++#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
++#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd
++#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000
++#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe
++#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000
++#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf
++#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000
++#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10
++#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000
++#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11
++#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000
++#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
++#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe
++#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000
++#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11
++#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000
++#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12
++#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000
++#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13
++#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
++#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
++#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
++#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
++#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
++#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000
++#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
++#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
++#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
++#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
++#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
++#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000
++#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a
++#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000
++#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
++#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
++#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
++#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
++#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
++#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
++#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
++#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
++#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
++#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
++#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000
++#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10
++#define MC_HUB_WDP_CREDITS2__VM3_MASK 0xff000000
++#define MC_HUB_WDP_CREDITS2__VM3__SHIFT 0x18
++#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG_MASK 0xfe000000
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG__SHIFT 0x19
++#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG_MASK 0xfe000000
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG__SHIFT 0x19
++#define MC_HUB_WDP_CREDITS3__STOR0_URG_MASK 0xff
++#define MC_HUB_WDP_CREDITS3__STOR0_URG__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS3__STOR1_URG_MASK 0xff00
++#define MC_HUB_WDP_CREDITS3__STOR1_URG__SHIFT 0x8
++#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
++#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
++#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
++#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
++#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
++#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
++#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
++#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
++#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
++#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
++#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
++#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ_MASK 0x10000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ__SHIFT 0x10
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE_MASK 0x20000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE__SHIFT 0x11
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC_MASK 0x40000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC__SHIFT 0x12
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ_MASK 0x80000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ__SHIFT 0x13
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE_MASK 0x100000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE__SHIFT 0x14
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC_MASK 0x200000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC__SHIFT 0x15
++#define MC_HUB_WDP_VIN0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VIN0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VIN0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VIN0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VIN0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VIN0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VIN0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VIN0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VIN0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VIN0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VIN0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
++#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80
++#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
++#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_TLS__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_TLS__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_TLS__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_TLS__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_TLS__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_TLS__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_TLS__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_TLS__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_TLS__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_TLS__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
++#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
++#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
++#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
++#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
++#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
++#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
++#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
++#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x80000
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x13
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x3f00000
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x14
++#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x80000
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x13
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x3f00000
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x14
++#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x80000
++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x13
++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x3f00000
++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x14
++#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x80000
++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x13
++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x3f00000
++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x14
++#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x80000
++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x13
++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x3f00000
++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x14
++#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x80000
++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x13
++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x3f00000
++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x14
++#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDS__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDS__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDT__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDT__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDU__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDU__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDV__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDV__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDW__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDX__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDY__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDS__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDT__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDU__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_MASK 0x1fc000
++#define MC_HUB_WDP_CREDITS_MCDV__WR_URG__SHIFT 0xe
++#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
++#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD__SHIFT 0x15
++#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
++#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
++#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
++#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
++#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
++#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
++#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
++#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
++#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
++#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
++#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
++#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
++#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
++#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
++#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
++#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
++#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
++#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
++#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
++#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
++#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1
++#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0
++#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6
++#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1
++#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8
++#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3
++#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10
++#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4
++#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20
++#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5
++#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40
++#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6
++#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
++#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
++#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
++#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
++#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
++#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
++#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
++#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
++#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
++#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
++#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
++#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
++#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
++#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
++#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
++#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
++#define MC_RD_GRP_GFX__CP_MASK 0xf
++#define MC_RD_GRP_GFX__CP__SHIFT 0x0
++#define MC_RD_GRP_GFX__SH_MASK 0xf0
++#define MC_RD_GRP_GFX__SH__SHIFT 0x4
++#define MC_RD_GRP_GFX__TLS_MASK 0xf00
++#define MC_RD_GRP_GFX__TLS__SHIFT 0x8
++#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
++#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
++#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
++#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
++#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
++#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
++#define MC_RD_GRP_GFX__ISP_MASK 0xf000000
++#define MC_RD_GRP_GFX__ISP__SHIFT 0x18
++#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000
++#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c
++#define MC_WR_GRP_GFX__VIN0_MASK 0xf
++#define MC_WR_GRP_GFX__VIN0__SHIFT 0x0
++#define MC_WR_GRP_GFX__SH_MASK 0xf0
++#define MC_WR_GRP_GFX__SH__SHIFT 0x4
++#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
++#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
++#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
++#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
++#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
++#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
++#define MC_WR_GRP_GFX__VP8_MASK 0xf00000
++#define MC_WR_GRP_GFX__VP8__SHIFT 0x14
++#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000
++#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18
++#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000
++#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c
++#define MC_RD_GRP_SYS__RLC_MASK 0xf
++#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
++#define MC_RD_GRP_SYS__VMC_MASK 0xf0
++#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
++#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
++#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
++#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
++#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
++#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
++#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
++#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
++#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
++#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000
++#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18
++#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000
++#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c
++#define MC_WR_GRP_SYS__IH_MASK 0xf
++#define MC_WR_GRP_SYS__IH__SHIFT 0x0
++#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
++#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
++#define MC_WR_GRP_SYS__RLC_MASK 0xf00
++#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
++#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000
++#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc
++#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
++#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
++#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
++#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
++#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000
++#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18
++#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000
++#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c
++#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_RD_GRP_OTH__HDP_MASK 0xf00
++#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
++#define MC_RD_GRP_OTH__SEM_MASK 0xf000
++#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
++#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
++#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
++#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
++#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
++#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
++#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
++#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000
++#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c
++#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_WR_GRP_OTH__HDP_MASK 0xf00
++#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
++#define MC_WR_GRP_OTH__SEM_MASK 0xf000
++#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
++#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
++#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
++#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
++#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
++#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
++#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
++#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
++#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
++#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
++#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
++#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
++#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
++#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
++#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
++#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
++#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
++#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
++#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
++#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
++#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
++#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
++#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
++#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
++#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
++#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
++#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
++#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
++#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
++#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff
++#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
++#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
++#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
++#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
++#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
++#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
++#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
++#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
++#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
++#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
++#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4
++#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000
++#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc
++#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000
++#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
++#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
++#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
++#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
++#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
++#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
++#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
++#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
++#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
++#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
++#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
++#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
++#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
++#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
++#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
++#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
++#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
++#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
++#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
++#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
++#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
++#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
++#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
++#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
++#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
++#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
++#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
++#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
++#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
++#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
++#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
++#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
++#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
++#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
++#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
++#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
++#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
++#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
++#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
++#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
++#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
++#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
++#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
++#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
++#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
++#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
++#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
++#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
++#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
++#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
++#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
++#define MC_XPB_STICKY__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY__BITS__SHIFT 0x0
++#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
++#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
++#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
++#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
++#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
++#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
++#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
++#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
++#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
++#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
++#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
++#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
++#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
++#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
++#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
++#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
++#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
++#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
++#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
++#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
++#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
++#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
++#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
++#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
++#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
++#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
++#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8
++#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3
++#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10
++#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4
++#define MC_XBAR_ARB__BREAK_BURST_BY_URG_MASK 0x20
++#define MC_XBAR_ARB__BREAK_BURST_BY_URG__SHIFT 0x5
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
++#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff
++#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000
++#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
++#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00
++#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
++#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
++#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
++#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff
++#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00
++#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8
++#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000
++#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10
++#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000
++#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18
++#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18
++#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
++#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
++#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
++#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
++#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
++#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
++#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
++#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
++#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
++#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
++#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
++#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
++#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
++#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
++#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
++#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
++#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
++#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
++#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000
++#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14
++#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000
++#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
++#define ATC_ATS_STATUS__BUSY_MASK 0x1
++#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
++#define ATC_ATS_STATUS__CRASHED_MASK 0x2
++#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
++#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1
++#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e
++#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
++#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00
++#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9
++#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
++#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
++#define ATC_MISC_CG__ENABLE_MASK 0x40000
++#define ATC_MISC_CG__ENABLE__SHIFT 0x12
++#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
++#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
++#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
++#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
++#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80
++#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7
++#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00
++#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8
++#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000
++#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18
++#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000
++#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19
++#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000
++#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b
++#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000
++#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d
++#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000
++#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e
++#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000
++#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
++#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
++#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
++#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400
++#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
++#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
++#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
++#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000
++#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13
++#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000
++#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17
++#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000
++#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f
++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1
++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2
++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc
++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000
++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19
++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff
++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff
++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1RD_STATUS__BUSY_MASK 0x1
++#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
++#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
++#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000
++#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11
++#define ATC_L1WR_STATUS__BUSY_MASK 0x1
++#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
++#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
++#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000
++#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
++#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
++#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
++#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
++#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
++#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
++#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
++#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
++#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
++#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
++#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
++#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
++#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
++#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
++#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
++#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
++#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
++#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1
++#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
++#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2
++#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
++#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4
++#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
++#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8
++#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
++#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10
++#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
++#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20
++#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
++#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40
++#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
++#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80
++#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
++#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100
++#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
++#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200
++#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
++#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400
++#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
++#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800
++#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
++#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000
++#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
++#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000
++#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
++#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000
++#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
++#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000
++#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
++#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1
++#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0
++#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f
++#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0
++#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80
++#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7
++#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00
++#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8
++#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000
++#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd
++#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000
++#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe
++#define ATC_L2_STATUS__BUSY_MASK 0x1
++#define ATC_L2_STATUS__BUSY__SHIFT 0x0
++#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe
++#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
++#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7
++#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0
++#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8
++#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
++#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
++#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
++#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
++#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
++#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
++#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
++#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
++#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
++#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
++#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
++#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
++#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
++#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
++#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
++#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
++#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
++#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
++#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
++#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
++#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
++#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
++#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
++#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
++#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
++#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
++#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
++#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
++#define GMCON_DEBUG__GFX_STALL_MASK 0x1
++#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
++#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
++#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
++#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4
++#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2
++#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8
++#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3
++#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0
++#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4
++#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00
++#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8
++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
++#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000
++#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
++#define VM_L2_STATUS__L2_BUSY_MASK 0x1
++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
++#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
++#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_DEBUG__FLAGS_MASK 0xffffffff
++#define VM_DEBUG__FLAGS__SHIFT 0x0
++#define VM_L2_CG__OFFDLY_MASK 0xfc0
++#define VM_L2_CG__OFFDLY__SHIFT 0x6
++#define VM_L2_CG__ENABLE_MASK 0x40000
++#define VM_L2_CG__ENABLE__SHIFT 0x12
++#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
++#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define VM_L2_CG__OVERRIDE_MASK 0x100000
++#define VM_L2_CG__OVERRIDE__SHIFT 0x14
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f
++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11
++#define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x40000
++#define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000
++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x1ff
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
++#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x100000
++#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff
++#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff
++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
++#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000
++#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
++#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8
++#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000
++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff
++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f
++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
++#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1
++#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL0__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL0__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL1__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL1__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL2__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL2__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL3__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL3__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL4__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL4__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL5__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL5__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL6__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL6__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL7__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL7__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x1ff
++#define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_CNTL8__EN_MASK 0x1000
++#define MC_VM_MB_L1_TLS0_CNTL8__EN__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x2000
++#define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd
++#define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc
++#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2
++#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30
++#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4
++#define MC_SEQ_CNTL__DAT_INV_MASK 0x40
++#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6
++#define MC_SEQ_CNTL__MSK_DF1_MASK 0x80
++#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7
++#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300
++#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8
++#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000
++#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe
++#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000
++#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf
++#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000
++#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10
++#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000
++#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11
++#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000
++#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12
++#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000
++#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13
++#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000
++#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14
++#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000
++#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18
++#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000
++#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c
++#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf
++#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0
++#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
++#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4
++#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20
++#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5
++#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300
++#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8
++#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00
++#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa
++#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000
++#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000
++#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000
++#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c
++#define MC_SEQ_DRAM__ADR_2CK_MASK 0x1
++#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0
++#define MC_SEQ_DRAM__ADR_MUX_MASK 0x2
++#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1
++#define MC_SEQ_DRAM__ADR_DF1_MASK 0x4
++#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2
++#define MC_SEQ_DRAM__AP8_MASK 0x8
++#define MC_SEQ_DRAM__AP8__SHIFT 0x3
++#define MC_SEQ_DRAM__DAT_DF1_MASK 0x10
++#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4
++#define MC_SEQ_DRAM__DQS_DF1_MASK 0x20
++#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5
++#define MC_SEQ_DRAM__DQM_DF1_MASK 0x40
++#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6
++#define MC_SEQ_DRAM__DQM_ACT_MASK 0x80
++#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7
++#define MC_SEQ_DRAM__STB_CNT_MASK 0xf00
++#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8
++#define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000
++#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc
++#define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000
++#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd
++#define MC_SEQ_DRAM__BO4_MASK 0x4000
++#define MC_SEQ_DRAM__BO4__SHIFT 0xe
++#define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000
++#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf
++#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000
++#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10
++#define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000
++#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18
++#define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000
++#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19
++#define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000
++#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a
++#define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000
++#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b
++#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000
++#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c
++#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000
++#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d
++#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000
++#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e
++#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000
++#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f
++#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1
++#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0
++#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2
++#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1
++#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4
++#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2
++#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8
++#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3
++#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10
++#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4
++#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20
++#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5
++#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40
++#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6
++#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80
++#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7
++#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100
++#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8
++#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200
++#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9
++#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400
++#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa
++#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800
++#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb
++#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000
++#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc
++#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000
++#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd
++#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000
++#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe
++#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000
++#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf
++#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000
++#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10
++#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000
++#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18
++#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000
++#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19
++#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000
++#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a
++#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000
++#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b
++#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000
++#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c
++#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000
++#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d
++#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000
++#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e
++#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000
++#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f
++#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f
++#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0
++#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0
++#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5
++#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00
++#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa
++#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000
++#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf
++#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000
++#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14
++#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000
++#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18
++#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3
++#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0
++#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc
++#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2
++#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0
++#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4
++#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00
++#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9
++#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000
++#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc
++#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000
++#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10
++#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000
++#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18
++#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f
++#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00
++#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000
++#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
++#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000
++#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
++#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7
++#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70
++#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4
++#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00
++#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000
++#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd
++#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000
++#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10
++#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000
++#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15
++#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000
++#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c
++#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7
++#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0
++#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70
++#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8
++#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000
++#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000
++#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000
++#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18
++#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8
++#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10
++#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20
++#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5
++#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40
++#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6
++#define MC_SEQ_CMD__ADR_MASK 0xffff
++#define MC_SEQ_CMD__ADR__SHIFT 0x0
++#define MC_SEQ_CMD__MOP_MASK 0xf0000
++#define MC_SEQ_CMD__MOP__SHIFT 0x10
++#define MC_SEQ_CMD__END_MASK 0x100000
++#define MC_SEQ_CMD__END__SHIFT 0x14
++#define MC_SEQ_CMD__CSB_MASK 0x600000
++#define MC_SEQ_CMD__CSB__SHIFT 0x15
++#define MC_SEQ_CMD__CHAN0_MASK 0x1000000
++#define MC_SEQ_CMD__CHAN0__SHIFT 0x18
++#define MC_SEQ_CMD__CHAN1_MASK 0x2000000
++#define MC_SEQ_CMD__CHAN1__SHIFT 0x19
++#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff
++#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0
++#define MC_PMG_CMD_EMRS__MOP_MASK 0x70000
++#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10
++#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_EMRS__END_MASK 0x100000
++#define MC_PMG_CMD_EMRS__END__SHIFT 0x14
++#define MC_PMG_CMD_EMRS__CSB_MASK 0x600000
++#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15
++#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_MRS__ADR_MASK 0xffff
++#define MC_PMG_CMD_MRS__ADR__SHIFT 0x0
++#define MC_PMG_CMD_MRS__MOP_MASK 0x70000
++#define MC_PMG_CMD_MRS__MOP__SHIFT 0x10
++#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_MRS__END_MASK 0x100000
++#define MC_PMG_CMD_MRS__END__SHIFT 0x14
++#define MC_PMG_CMD_MRS__CSB_MASK 0x600000
++#define MC_PMG_CMD_MRS__CSB__SHIFT 0x15
++#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff
++#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0
++#define MC_PMG_CMD_MRS1__MOP_MASK 0x70000
++#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10
++#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_MRS1__END_MASK 0x100000
++#define MC_PMG_CMD_MRS1__END__SHIFT 0x14
++#define MC_PMG_CMD_MRS1__CSB_MASK 0x600000
++#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15
++#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff
++#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0
++#define MC_PMG_CMD_MRS2__MOP_MASK 0x70000
++#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10
++#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000
++#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13
++#define MC_PMG_CMD_MRS2__END_MASK 0x100000
++#define MC_PMG_CMD_MRS2__END__SHIFT 0x14
++#define MC_PMG_CMD_MRS2__CSB_MASK 0x600000
++#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15
++#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_CFG__SYC_CLK_MASK 0x1
++#define MC_PMG_CFG__SYC_CLK__SHIFT 0x0
++#define MC_PMG_CFG__RST_MRS_MASK 0x2
++#define MC_PMG_CFG__RST_MRS__SHIFT 0x1
++#define MC_PMG_CFG__RST_EMRS_MASK 0x4
++#define MC_PMG_CFG__RST_EMRS__SHIFT 0x2
++#define MC_PMG_CFG__TRI_MIO_MASK 0x8
++#define MC_PMG_CFG__TRI_MIO__SHIFT 0x3
++#define MC_PMG_CFG__XSR_TMR_MASK 0xf0
++#define MC_PMG_CFG__XSR_TMR__SHIFT 0x4
++#define MC_PMG_CFG__RST_MRS1_MASK 0x100
++#define MC_PMG_CFG__RST_MRS1__SHIFT 0x8
++#define MC_PMG_CFG__RST_MRS2_MASK 0x200
++#define MC_PMG_CFG__RST_MRS2__SHIFT 0x9
++#define MC_PMG_CFG__DPM_WAKE_MASK 0x400
++#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa
++#define MC_PMG_CFG__RFS_SRX_MASK 0x1000
++#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc
++#define MC_PMG_CFG__PREA_SRX_MASK 0x2000
++#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd
++#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000
++#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10
++#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000
++#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
++#define MC_PMG_CFG__YCLK_ON_MASK 0x200000
++#define MC_PMG_CFG__YCLK_ON__SHIFT 0x15
++#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000
++#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16
++#define MC_PMG_CFG__RXPDNB_MASK 0x2000000
++#define MC_PMG_CFG__RXPDNB__SHIFT 0x19
++#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000
++#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a
++#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff
++#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0
++#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000
++#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c
++#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000
++#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d
++#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1
++#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0
++#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2
++#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1
++#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4
++#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2
++#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0
++#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4
++#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100
++#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8
++#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200
++#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9
++#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400
++#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa
++#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800
++#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb
++#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000
++#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc
++#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000
++#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd
++#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000
++#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf
++#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000
++#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10
++#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000
++#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
++#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000
++#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15
++#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000
++#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000
++#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17
++#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000
++#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18
++#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f
++#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0
++#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20
++#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5
++#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40
++#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6
++#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100
++#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8
++#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200
++#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9
++#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000
++#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd
++#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000
++#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10
++#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000
++#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d
++#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000
++#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e
++#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000
++#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f
++#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff
++#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0
++#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00
++#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8
++#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000
++#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10
++#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000
++#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c
++#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000
++#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d
++#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000
++#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e
++#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000
++#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f
++#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff
++#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0
++#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00
++#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8
++#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000
++#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10
++#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000
++#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18
++#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff
++#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0
++#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00
++#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
++#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000
++#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10
++#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000
++#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18
++#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff
++#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0
++#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
++#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8
++#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000
++#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc
++#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000
++#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd
++#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000
++#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe
++#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000
++#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf
++#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000
++#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10
++#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000
++#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14
++#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000
++#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15
++#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000
++#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18
++#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000
++#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000
++#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000
++#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10
++#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff
++#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200
++#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000
++#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b
++#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f
++#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0
++#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0
++#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5
++#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00
++#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa
++#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000
++#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf
++#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff
++#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0
++#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00
++#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8
++#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000
++#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
++#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000
++#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18
++#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff
++#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0
++#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00
++#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
++#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000
++#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10
++#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000
++#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
++#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff
++#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf
++#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0
++#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00
++#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000
++#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc
++#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c
++#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000
++#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d
++#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000
++#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e
++#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1
++#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2
++#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1
++#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30
++#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100
++#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200
++#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9
++#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400
++#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa
++#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800
++#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb
++#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000
++#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10
++#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c
++#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff
++#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0
++#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000
++#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10
++#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff
++#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf
++#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0
++#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00
++#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000
++#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc
++#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c
++#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000
++#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d
++#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000
++#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e
++#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1
++#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0
++#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2
++#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1
++#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30
++#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4
++#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100
++#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8
++#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200
++#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9
++#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400
++#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa
++#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800
++#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb
++#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000
++#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10
++#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000
++#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c
++#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff
++#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
++#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000
++#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20
++#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000
++#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc
++#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000
++#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd
++#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000
++#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000
++#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17
++#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000
++#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000
++#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b
++#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000
++#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e
++#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000
++#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f
++#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000
++#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000
++#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12
++#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000
++#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18
++#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000
++#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19
++#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
++#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000
++#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d
++#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000
++#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0
++#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0
++#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000
++#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc
++#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000
++#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18
++#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000
++#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19
++#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
++#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000
++#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d
++#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20
++#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000
++#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc
++#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000
++#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
++#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000
++#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000
++#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c
++#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3
++#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0
++#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc
++#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2
++#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10
++#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4
++#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20
++#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5
++#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40
++#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6
++#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80
++#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7
++#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00
++#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8
++#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000
++#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc
++#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000
++#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd
++#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000
++#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10
++#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000
++#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14
++#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000
++#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17
++#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000
++#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18
++#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000
++#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000
++#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b
++#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000
++#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e
++#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000
++#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f
++#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3
++#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0
++#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4
++#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2
++#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8
++#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3
++#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30
++#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4
++#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40
++#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6
++#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80
++#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000
++#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc
++#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000
++#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10
++#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000
++#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c
++#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000
++#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000
++#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000
++#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000
++#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17
++#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000
++#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000
++#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000
++#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000
++#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12
++#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000
++#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18
++#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000
++#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19
++#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
++#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000
++#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d
++#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000
++#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0
++#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0
++#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000
++#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc
++#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000
++#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18
++#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000
++#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19
++#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
++#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000
++#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d
++#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf
++#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0
++#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0
++#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4
++#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100
++#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8
++#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200
++#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800
++#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000
++#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000
++#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000
++#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000
++#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19
++#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000
++#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a
++#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000
++#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000
++#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000
++#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00
++#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000
++#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2
++#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8
++#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20
++#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80
++#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7
++#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00
++#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8
++#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000
++#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc
++#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000
++#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10
++#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf
++#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0
++#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0
++#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4
++#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100
++#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8
++#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200
++#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800
++#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000
++#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000
++#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000
++#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000
++#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19
++#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000
++#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a
++#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000
++#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000
++#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000
++#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00
++#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000
++#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2
++#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8
++#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20
++#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80
++#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7
++#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00
++#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8
++#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000
++#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc
++#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000
++#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0
++#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
++#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
++#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30
++#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4
++#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
++#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
++#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100
++#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8
++#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200
++#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00
++#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa
++#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000
++#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc
++#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000
++#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10
++#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000
++#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12
++#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000
++#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14
++#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
++#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18
++#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000
++#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
++#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000
++#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000
++#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
++#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00
++#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8
++#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000
++#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10
++#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000
++#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000
++#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13
++#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000
++#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14
++#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000
++#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18
++#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000
++#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e
++#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000
++#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f
++#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4
++#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2
++#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8
++#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3
++#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10
++#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200
++#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9
++#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400
++#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa
++#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800
++#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb
++#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000
++#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc
++#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000
++#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd
++#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000
++#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe
++#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000
++#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf
++#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000
++#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000
++#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b
++#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000
++#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c
++#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000
++#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d
++#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000
++#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000
++#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f
++#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1
++#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0
++#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2
++#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1
++#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4
++#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2
++#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8
++#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3
++#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10
++#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200
++#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9
++#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400
++#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa
++#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800
++#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb
++#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000
++#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc
++#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000
++#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd
++#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000
++#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe
++#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000
++#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf
++#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000
++#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000
++#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b
++#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000
++#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c
++#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000
++#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d
++#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000
++#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000
++#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f
++#define MC_NPL_STATUS__D0_PDELAY_MASK 0x3
++#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0
++#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc
++#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2
++#define MC_NPL_STATUS__D0_PEARLY_MASK 0x10
++#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4
++#define MC_NPL_STATUS__D0_NEARLY_MASK 0x20
++#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5
++#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0
++#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6
++#define MC_NPL_STATUS__D1_NDELAY_MASK 0x300
++#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8
++#define MC_NPL_STATUS__D1_PEARLY_MASK 0x400
++#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa
++#define MC_NPL_STATUS__D1_NEARLY_MASK 0x800
++#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb
++#define MC_BIST_CMD_CNTL__RESET_MASK 0x1
++#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2
++#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8
++#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3
++#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0
++#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000
++#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11
++#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000
++#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12
++#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000
++#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c
++#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000
++#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d
++#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000
++#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e
++#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000
++#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f
++#define MC_BIST_CNTL__RESET_MASK 0x1
++#define MC_BIST_CNTL__RESET__SHIFT 0x0
++#define MC_BIST_CNTL__RUN_MASK 0x2
++#define MC_BIST_CNTL__RUN__SHIFT 0x1
++#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4
++#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2
++#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8
++#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3
++#define MC_BIST_CNTL__MOP_MODE_MASK 0x10
++#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4
++#define MC_BIST_CNTL__ADR_MODE_MASK 0x20
++#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5
++#define MC_BIST_CNTL__DAT_MODE_MASK 0x40
++#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6
++#define MC_BIST_CNTL__LOOP_MASK 0xc00
++#define MC_BIST_CNTL__LOOP__SHIFT 0xa
++#define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000
++#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc
++#define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000
++#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd
++#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000
++#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe
++#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000
++#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10
++#define MC_BIST_CNTL__DONE_MASK 0x40000000
++#define MC_BIST_CNTL__DONE__SHIFT 0x1e
++#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000
++#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f
++#define MC_BIST_AUTO_CNTL__MOP_MASK 0x3
++#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0
++#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0
++#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4
++#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00
++#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8
++#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000
++#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18
++#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000
++#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19
++#define MC_BIST_DIR_CNTL__MOP_MASK 0x7
++#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0
++#define MC_BIST_DIR_CNTL__EOB_MASK 0x8
++#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3
++#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10
++#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4
++#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20
++#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5
++#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40
++#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6
++#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80
++#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7
++#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100
++#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8
++#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200
++#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9
++#define MC_BIST_DIR_CNTL__MOP3_MASK 0x400
++#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa
++#define MC_BIST_SADDR__COL_MASK 0x3ff
++#define MC_BIST_SADDR__COL__SHIFT 0x0
++#define MC_BIST_SADDR__ROW_MASK 0xfffc00
++#define MC_BIST_SADDR__ROW__SHIFT 0xa
++#define MC_BIST_SADDR__BANK_MASK 0xf000000
++#define MC_BIST_SADDR__BANK__SHIFT 0x18
++#define MC_BIST_SADDR__RANK_MASK 0x10000000
++#define MC_BIST_SADDR__RANK__SHIFT 0x1c
++#define MC_BIST_SADDR__COLH_MASK 0x20000000
++#define MC_BIST_SADDR__COLH__SHIFT 0x1d
++#define MC_BIST_SADDR__ROWH_MASK 0xc0000000
++#define MC_BIST_SADDR__ROWH__SHIFT 0x1e
++#define MC_BIST_EADDR__COL_MASK 0x3ff
++#define MC_BIST_EADDR__COL__SHIFT 0x0
++#define MC_BIST_EADDR__ROW_MASK 0xfffc00
++#define MC_BIST_EADDR__ROW__SHIFT 0xa
++#define MC_BIST_EADDR__BANK_MASK 0xf000000
++#define MC_BIST_EADDR__BANK__SHIFT 0x18
++#define MC_BIST_EADDR__RANK_MASK 0x10000000
++#define MC_BIST_EADDR__RANK__SHIFT 0x1c
++#define MC_BIST_EADDR__COLH_MASK 0x20000000
++#define MC_BIST_EADDR__COLH__SHIFT 0x1d
++#define MC_BIST_EADDR__ROWH_MASK 0xc0000000
++#define MC_BIST_EADDR__ROWH__SHIFT 0x1e
++#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf
++#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0
++#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0
++#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4
++#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000
++#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc
++#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000
++#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd
++#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000
++#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe
++#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000
++#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf
++#define MC_BIST_CMP_CNTL__CMP_MASK 0x30000
++#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10
++#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000
++#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12
++#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000
++#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13
++#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000
++#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14
++#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000
++#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100
++#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000
++#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14
++#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0
++#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff
++#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0
++#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff
++#define MC_BIST_DATA_MASK__MASK__SHIFT 0x0
++#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff
++#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0
++#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00
++#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa
++#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000
++#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18
++#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000
++#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c
++#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000
++#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d
++#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000
++#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e
++#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff
++#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0
++#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff
++#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0
++#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff
++#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0
++#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff
++#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0
++#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000
++#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e
++#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1
++#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0
++#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100
++#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8
++#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200
++#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800
++#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000
++#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf
++#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf
++#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0
++#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000
++#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c
++#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2
++#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1
++#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4
++#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
++#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8
++#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3
++#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10
++#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4
++#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20
++#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5
++#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40
++#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
++#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80
++#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
++#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100
++#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8
++#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200
++#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9
++#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000
++#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc
++#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000
++#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd
++#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000
++#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe
++#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000
++#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf
++#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000
++#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10
++#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000
++#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14
++#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000
++#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19
++#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000
++#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a
++#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000
++#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b
++#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000
++#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c
++#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1
++#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0
++#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2
++#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1
++#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10
++#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4
++#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20
++#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5
++#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100
++#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8
++#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200
++#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9
++#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
++#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
++#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff
++#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0
++#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff
++#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC0__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC1__VALUE__SHIFT 0x0
++#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffff
++#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x0
++#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff
++#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0
++#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff
++#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0
++#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff
++#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0
++#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000
++#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc
++#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000
++#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18
++#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff
++#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0
++#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000
++#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
++#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000
++#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18
++#define MC_SEQ_SUP_CNTL__RUN_MASK 0x1
++#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0
++#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2
++#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1
++#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4
++#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2
++#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8
++#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3
++#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10
++#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4
++#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20
++#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5
++#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40
++#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6
++#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80
++#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7
++#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000
++#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17
++#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff
++#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0
++#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff
++#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0
++#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff
++#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0
++#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC3__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC4__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC5__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC6__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC7__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC8__VALUE__SHIFT 0x0
++#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff
++#define MC_SEQ_MISC9__VALUE__SHIFT 0x0
++#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff
++#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0
++#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00
++#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8
++#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000
++#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10
++#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000
++#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18
++#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3
++#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0
++#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc
++#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2
++#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30
++#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4
++#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0
++#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6
++#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3
++#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0
++#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc
++#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2
++#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30
++#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4
++#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0
++#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000
++#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15
++#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
++#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0
++#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
++#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5
++#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
++#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa
++#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
++#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf
++#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
++#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14
++#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
++#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18
++#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
++#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0
++#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
++#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2
++#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
++#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4
++#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
++#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9
++#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000
++#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
++#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000
++#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
++#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000
++#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
++#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
++#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
++#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
++#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
++#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
++#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
++#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7
++#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0
++#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70
++#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4
++#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00
++#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8
++#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000
++#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd
++#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000
++#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10
++#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000
++#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15
++#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000
++#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18
++#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000
++#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c
++#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7
++#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0
++#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8
++#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3
++#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300
++#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8
++#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00
++#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa
++#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000
++#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc
++#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000
++#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10
++#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000
++#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11
++#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000
++#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14
++#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000
++#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19
++#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf
++#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0
++#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0
++#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4
++#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100
++#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8
++#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200
++#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9
++#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400
++#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa
++#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800
++#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb
++#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000
++#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc
++#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000
++#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10
++#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000
++#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14
++#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000
++#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18
++#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000
++#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c
++#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000
++#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d
++#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000
++#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8
++#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10
++#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20
++#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5
++#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40
++#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000
++#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d
++#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7
++#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0
++#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70
++#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8
++#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000
++#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000
++#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000
++#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18
++#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff
++#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0
++#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff
++#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0
++#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff
++#define MC_SEQ_IO_REDC__EDC__SHIFT 0x0
++#define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
++#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0
++#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2
++#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1
++#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
++#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2
++#define MC_SEQ_TCG_CNTL__START_MASK 0x8
++#define MC_SEQ_TCG_CNTL__START__SHIFT 0x3
++#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70
++#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4
++#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80
++#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7
++#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00
++#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8
++#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000
++#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc
++#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000
++#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10
++#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000
++#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11
++#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000
++#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12
++#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000
++#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13
++#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000
++#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16
++#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000
++#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17
++#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000
++#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18
++#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000
++#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19
++#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000
++#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000
++#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d
++#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000
++#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f
++#define MC_SEQ_TSM_CTRL__START_MASK 0x1
++#define MC_SEQ_TSM_CTRL__START__SHIFT 0x0
++#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2
++#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1
++#define MC_SEQ_TSM_CTRL__DONE_MASK 0x4
++#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2
++#define MC_SEQ_TSM_CTRL__ERR_MASK 0x8
++#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3
++#define MC_SEQ_TSM_CTRL__STEP_MASK 0x10
++#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4
++#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20
++#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5
++#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40
++#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6
++#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80
++#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7
++#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300
++#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8
++#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400
++#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa
++#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800
++#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb
++#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000
++#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc
++#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000
++#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd
++#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000
++#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10
++#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00
++#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000
++#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10
++#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00
++#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000
++#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10
++#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00
++#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000
++#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10
++#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000
++#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14
++#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000
++#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18
++#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00
++#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000
++#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10
++#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000
++#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18
++#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00
++#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000
++#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10
++#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000
++#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18
++#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf
++#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0
++#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0
++#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4
++#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00
++#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8
++#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
++#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10
++#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000
++#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18
++#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff
++#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0
++#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff
++#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0
++#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff
++#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0
++#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff
++#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0
++#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000
++#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10
++#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000
++#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14
++#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000
++#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a
++#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff
++#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0
++#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff
++#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0
++#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff
++#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0
++#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000
++#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10
++#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf
++#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0
++#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0
++#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4
++#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00
++#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8
++#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000
++#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc
++#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000
++#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10
++#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000
++#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14
++#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000
++#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18
++#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000
++#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c
++#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf
++#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0
++#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0
++#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4
++#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00
++#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8
++#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000
++#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc
++#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
++#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10
++#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000
++#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14
++#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000
++#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18
++#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000
++#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c
++#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f
++#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0
++#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100
++#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8
++#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200
++#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9
++#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400
++#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa
++#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800
++#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb
++#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000
++#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc
++#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000
++#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd
++#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000
++#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe
++#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000
++#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf
++#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000
++#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10
++#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000
++#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11
++#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000
++#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12
++#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000
++#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13
++#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000
++#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14
++#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000
++#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18
++#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000
++#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19
++#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1
++#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4
++#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10
++#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4
++#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20
++#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80
++#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7
++#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f
++#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0
++#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40
++#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6
++#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80
++#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7
++#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100
++#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8
++#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200
++#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9
++#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000
++#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10
++#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000
++#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11
++#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000
++#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18
++#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff
++#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0
++#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000
++#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc
++#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000
++#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18
++#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000
++#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19
++#define DLL_CNTL__PWR2_MODE_MASK 0x4000000
++#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a
++#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf
++#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0
++#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0
++#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4
++#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00
++#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8
++#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000
++#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc
++#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000
++#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
++#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000
++#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
++#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000
++#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18
++#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000
++#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c
++#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf
++#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0
++#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0
++#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4
++#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00
++#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8
++#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000
++#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc
++#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000
++#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10
++#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000
++#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14
++#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000
++#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18
++#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000
++#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c
++#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff
++#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0
++#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100
++#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8
++#define MPLL_CNTL_MODE__GDDR_PWRON_OVR_MASK 0x200
++#define MPLL_CNTL_MODE__GDDR_PWRON_OVR__SHIFT 0x9
++#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800
++#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb
++#define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000
++#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc
++#define MPLL_CNTL_MODE__QDR_MASK 0x2000
++#define MPLL_CNTL_MODE__QDR__SHIFT 0xd
++#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000
++#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe
++#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000
++#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10
++#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000
++#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11
++#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000
++#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14
++#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000
++#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15
++#define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000
++#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17
++#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000
++#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18
++#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000
++#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a
++#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000
++#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b
++#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000
++#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c
++#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000
++#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f
++#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20
++#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5
++#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00
++#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8
++#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000
++#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10
++#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000
++#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14
++#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000
++#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e
++#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3
++#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0
++#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc
++#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2
++#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0
++#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4
++#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000
++#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10
++#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000
++#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c
++#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1
++#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1
++#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4
++#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10
++#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5
++#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40
++#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6
++#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80
++#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100
++#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200
++#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9
++#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00
++#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa
++#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000
++#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc
++#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000
++#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe
++#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000
++#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf
++#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000
++#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10
++#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000
++#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11
++#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000
++#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14
++#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000
++#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b
++#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
++#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
++#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8
++#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3
++#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
++#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
++#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8
++#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3
++#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10
++#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4
++#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0
++#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5
++#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff
++#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0
++#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000
++#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10
++#define MPLL_SS1__CLKV_MASK 0x3ffffff
++#define MPLL_SS1__CLKV__SHIFT 0x0
++#define MPLL_SS1__SPARE_MASK 0xfc000000
++#define MPLL_SS1__SPARE__SHIFT 0x1a
++#define MPLL_SS2__CLKS_MASK 0xfff
++#define MPLL_SS2__CLKS__SHIFT 0x0
++#define MPLL_SS2__SPARE_MASK 0xfffff000
++#define MPLL_SS2__SPARE__SHIFT 0xc
++#define MPLL_CONTROL__GDDR_PWRON_MASK 0x1
++#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0
++#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2
++#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1
++#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4
++#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2
++#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000
++#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc
++#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000
++#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd
++#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000
++#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe
++#define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000
++#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf
++#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000
++#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
++#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000
++#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11
++#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000
++#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12
++#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000
++#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13
++#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000
++#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14
++#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000
++#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
++#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000
++#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
++#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000
++#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17
++#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000
++#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18
++#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000
++#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
++#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000
++#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
++#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000
++#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b
++#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000
++#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c
++#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000
++#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d
++#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000
++#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
++#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000
++#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f
++#define MPLL_AD_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
++#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
++#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
++#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000
++#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11
++#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000
++#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12
++#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
++#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
++#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1
++#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0
++#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2
++#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1
++#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c
++#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2
++#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0
++#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6
++#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300
++#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8
++#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00
++#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa
++#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000
++#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10
++#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000
++#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11
++#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000
++#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000
++#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000
++#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000
++#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10
++#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000
++#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f
++#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f
++#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0
++#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff
++#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff
++#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0
++#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00
++#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8
++#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000
++#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc
++#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff
++#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0
++#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00
++#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8
++#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000
++#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10
++#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000
++#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18
++#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0
++#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff
++#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0
++#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff
++#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0
++#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff
++#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0
++#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
++#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0
++#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00
++#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9
++#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000
++#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc
++#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000
++#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd
++#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000
++#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10
++#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000
++#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14
++#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000
++#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15
++#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000
++#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16
++#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000
++#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17
++#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000
++#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18
++#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000
++#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e
++#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000
++#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f
++#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
++#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0
++#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2
++#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8
++#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3
++#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0
++#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4
++#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
++#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc
++#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000
++#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10
++#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000
++#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14
++#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1
++#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0
++#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2
++#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8
++#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3
++#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0
++#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4
++#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000
++#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc
++#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000
++#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10
++#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000
++#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14
++#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0
++#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0
++#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0
++#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff
++#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0
++#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff
++#define MC_SEQ_SREG_READ__DATA__SHIFT 0x0
++#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf
++#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0
++#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00
++#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8
++#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000
++#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc
++#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1
++#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0
++#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2
++#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1
++#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80
++#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7
++#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100
++#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8
++#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200
++#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9
++#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400
++#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa
++#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800
++#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb
++#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000
++#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc
++#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000
++#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd
++#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000
++#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe
++#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000
++#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf
++#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1
++#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e
++#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1
++#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1
++#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e
++#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1
++#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff
++#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000
++#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000
++#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14
++#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000
++#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000
++#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0
++#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000
++#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10
++#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000
++#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13
++#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000
++#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14
++#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000
++#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000
++#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18
++#define MC_SEQ_DLL_STBY__EN_MASK 0x1
++#define MC_SEQ_DLL_STBY__EN__SHIFT 0x0
++#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2
++#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1
++#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4
++#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2
++#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8
++#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3
++#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10
++#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4
++#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0
++#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5
++#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00
++#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8
++#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000
++#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc
++#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000
++#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10
++#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000
++#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18
++#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1
++#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4
++#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10
++#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4
++#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0
++#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5
++#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00
++#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8
++#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000
++#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc
++#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000
++#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10
++#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000
++#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18
++#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1
++#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0
++#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2
++#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1
++#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4
++#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2
++#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8
++#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3
++#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0
++#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4
++#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00
++#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8
++#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000
++#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10
++#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff
++#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0
++#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff
++#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0
++#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000
++#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11
++#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000
++#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12
++#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000
++#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13
++#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000
++#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14
++#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000
++#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15
++#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000
++#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18
++#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000
++#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a
++#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000
++#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c
++#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000
++#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d
++#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
++#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e
++#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1
++#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0
++#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2
++#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1
++#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4
++#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2
++#define MC_DLB_CONFIG0__MASK_MASK 0xf0
++#define MC_DLB_CONFIG0__MASK__SHIFT 0x4
++#define MC_DLB_CONFIG0__PTR_MASK 0x3ff00
++#define MC_DLB_CONFIG0__PTR__SHIFT 0x8
++#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff
++#define MC_DLB_CONFIG1__DATA__SHIFT 0x0
++#define MC_DLB_SETUP__DLB_EN_MASK 0x1
++#define MC_DLB_SETUP__DLB_EN__SHIFT 0x0
++#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2
++#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1
++#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4
++#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2
++#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8
++#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3
++#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10
++#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4
++#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20
++#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5
++#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40
++#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6
++#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80
++#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7
++#define MC_DLB_SETUP__QDR_MODE_MASK 0x100
++#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8
++#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000
++#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10
++#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000
++#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18
++#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000
++#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f
++#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1
++#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0
++#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2
++#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1
++#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4
++#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2
++#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0
++#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4
++#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00
++#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8
++#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1
++#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0
++#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2
++#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1
++#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4
++#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2
++#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8
++#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3
++#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30
++#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4
++#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40
++#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6
++#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300
++#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8
++#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00
++#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa
++#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000
++#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10
++#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff
++#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0
++#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000
++#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18
++#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf
++#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0
++#define MC_DLB_STATUS__LOCK_MASK 0xf0
++#define MC_DLB_STATUS__LOCK__SHIFT 0x4
++#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00
++#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8
++#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0
++#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff
++#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e
++#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e
++#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
++#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10
++
++#endif /* GMC_8_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch
new file mode 100644
index 00000000..7909ea24
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch
@@ -0,0 +1,9860 @@
+From 3d1676c0d334981b60e7ae14a1d968e64ae73711 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:24:40 -0400
+Subject: drm/amdgpu: add GMC 8.2 register headers
+
+These are register headers for the GMC (Graphics Memory Controller)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h
+new file mode 100644
+index 0000000..06ef7d9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h
+@@ -0,0 +1,910 @@
++/*
++ * GMC_8_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_8_2_D_H
++#define GMC_8_2_D_H
++
++#define mmMC_CONFIG                                                             0x800
++#define mmMC_ARB_ATOMIC                                                         0x9be
++#define mmMC_ARB_AGE_CNTL                                                       0x9bf
++#define mmMC_ARB_RET_CREDITS2                                                   0x9c0
++#define mmMC_ARB_FED_CNTL                                                       0x9c1
++#define mmMC_ARB_GECC2_STATUS                                                   0x9c2
++#define mmMC_ARB_GECC2_MISC                                                     0x9c3
++#define mmMC_ARB_GECC2_DEBUG                                                    0x9c4
++#define mmMC_ARB_GECC2_DEBUG2                                                   0x9c5
++#define mmMC_ARB_PERF_CID                                                       0x9c6
++#define mmMC_ARB_SNOOP                                                          0x9c7
++#define mmMC_ARB_GRUB                                                           0x9c8
++#define mmMC_ARB_GECC2                                                          0x9c9
++#define mmMC_ARB_GECC2_CLI                                                      0x9ca
++#define mmMC_ARB_ADDR_SWIZ0                                                     0x9cb
++#define mmMC_ARB_ADDR_SWIZ1                                                     0x9cc
++#define mmMC_ARB_MISC3                                                          0x9cd
++#define mmMC_ARB_GRUB_PROMOTE                                                   0x9ce
++#define mmMC_ARB_RTT_DATA                                                       0x9cf
++#define mmMC_ARB_RTT_CNTL0                                                      0x9d0
++#define mmMC_ARB_RTT_CNTL1                                                      0x9d1
++#define mmMC_ARB_RTT_CNTL2                                                      0x9d2
++#define mmMC_ARB_RTT_DEBUG                                                      0x9d3
++#define mmMC_ARB_CAC_CNTL                                                       0x9d4
++#define mmMC_ARB_MISC2                                                          0x9d5
++#define mmMC_ARB_MISC                                                           0x9d6
++#define mmMC_ARB_BANKMAP                                                        0x9d7
++#define mmMC_ARB_RAMCFG                                                         0x9d8
++#define mmMC_ARB_POP                                                            0x9d9
++#define mmMC_ARB_MINCLKS                                                        0x9da
++#define mmMC_ARB_SQM_CNTL                                                       0x9db
++#define mmMC_ARB_ADDR_HASH                                                      0x9dc
++#define mmMC_ARB_DRAM_TIMING                                                    0x9dd
++#define mmMC_ARB_DRAM_TIMING2                                                   0x9de
++#define mmMC_ARB_WTM_CNTL_RD                                                    0x9df
++#define mmMC_ARB_WTM_CNTL_WR                                                    0x9e0
++#define mmMC_ARB_WTM_GRPWT_RD                                                   0x9e1
++#define mmMC_ARB_WTM_GRPWT_WR                                                   0x9e2
++#define mmMC_ARB_TM_CNTL_RD                                                     0x9e3
++#define mmMC_ARB_TM_CNTL_WR                                                     0x9e4
++#define mmMC_ARB_LAZY0_RD                                                       0x9e5
++#define mmMC_ARB_LAZY0_WR                                                       0x9e6
++#define mmMC_ARB_LAZY1_RD                                                       0x9e7
++#define mmMC_ARB_LAZY1_WR                                                       0x9e8
++#define mmMC_ARB_AGE_RD                                                         0x9e9
++#define mmMC_ARB_AGE_WR                                                         0x9ea
++#define mmMC_ARB_RFSH_CNTL                                                      0x9eb
++#define mmMC_ARB_RFSH_RATE                                                      0x9ec
++#define mmMC_ARB_PM_CNTL                                                        0x9ed
++#define mmMC_ARB_GDEC_RD_CNTL                                                   0x9ee
++#define mmMC_ARB_GDEC_WR_CNTL                                                   0x9ef
++#define mmMC_ARB_LM_RD                                                          0x9f0
++#define mmMC_ARB_LM_WR                                                          0x9f1
++#define mmMC_ARB_REMREQ                                                         0x9f2
++#define mmMC_ARB_REPLAY                                                         0x9f3
++#define mmMC_ARB_RET_CREDITS_RD                                                 0x9f4
++#define mmMC_ARB_RET_CREDITS_WR                                                 0x9f5
++#define mmMC_ARB_MAX_LAT_CID                                                    0x9f6
++#define mmMC_ARB_MAX_LAT_RSLT0                                                  0x9f7
++#define mmMC_ARB_MAX_LAT_RSLT1                                                  0x9f8
++#define mmMC_ARB_GRUB_REALTIME_RD                                               0x9f9
++#define mmMC_ARB_CG                                                             0x9fa
++#define mmMC_ARB_GRUB_REALTIME_WR                                               0x9fb
++#define mmMC_ARB_DRAM_TIMING_1                                                  0x9fc
++#define mmMC_ARB_BUSY_STATUS                                                    0x9fd
++#define mmMC_ARB_DRAM_TIMING2_1                                                 0x9ff
++#define mmMC_ARB_GRUB2                                                          0xa01
++#define mmMC_ARB_BURST_TIME                                                     0xa02
++#define mmMC_CITF_XTRA_ENABLE                                                   0x96d
++#define mmCC_MC_MAX_CHANNEL                                                     0x96e
++#define mmMC_CG_CONFIG                                                          0x96f
++#define mmMC_CITF_CNTL                                                          0x970
++#define mmMC_CITF_CREDITS_VM                                                    0x971
++#define mmMC_CITF_CREDITS_ARB_RD                                                0x972
++#define mmMC_CITF_CREDITS_ARB_WR                                                0x973
++#define mmMC_CITF_DAGB_CNTL                                                     0x974
++#define mmMC_CITF_INT_CREDITS                                                   0x975
++#define mmMC_CITF_RET_MODE                                                      0x976
++#define mmMC_CITF_DAGB_DLY                                                      0x977
++#define mmMC_RD_GRP_EXT                                                         0x978
++#define mmMC_WR_GRP_EXT                                                         0x979
++#define mmMC_CITF_REMREQ                                                        0x97a
++#define mmMC_WR_TC0                                                             0x97b
++#define mmMC_WR_TC1                                                             0x97c
++#define mmMC_CITF_INT_CREDITS_WR                                                0x97d
++#define mmMC_CITF_CREDITS_ARB_RD2                                               0x97e
++#define mmMC_CITF_WTM_RD_CNTL                                                   0x97f
++#define mmMC_CITF_WTM_WR_CNTL                                                   0x980
++#define mmMC_RD_CB                                                              0x981
++#define mmMC_RD_DB                                                              0x982
++#define mmMC_RD_TC0                                                             0x983
++#define mmMC_RD_TC1                                                             0x984
++#define mmMC_RD_HUB                                                             0x985
++#define mmMC_WR_CB                                                              0x986
++#define mmMC_WR_DB                                                              0x987
++#define mmMC_WR_HUB                                                             0x988
++#define mmMC_CITF_CREDITS_XBAR                                                  0x989
++#define mmMC_RD_GRP_LCL                                                         0x98a
++#define mmMC_WR_GRP_LCL                                                         0x98b
++#define mmMC_CITF_PERF_MON_CNTL2                                                0x98e
++#define mmMC_CITF_PERF_MON_RSLT2                                                0x991
++#define mmMC_CITF_MISC_RD_CG                                                    0x992
++#define mmMC_CITF_MISC_WR_CG                                                    0x993
++#define mmMC_CITF_MISC_VM_CG                                                    0x994
++#define mmMC_HUB_MISC_POWER                                                     0x82d
++#define mmMC_HUB_MISC_HUB_CG                                                    0x82e
++#define mmMC_HUB_MISC_VM_CG                                                     0x82f
++#define mmMC_HUB_MISC_SIP_CG                                                    0x830
++#define mmMC_HUB_MISC_STATUS                                                    0x832
++#define mmMC_HUB_MISC_OVERRIDE                                                  0x833
++#define mmMC_HUB_MISC_FRAMING                                                   0x834
++#define mmMC_HUB_WDP_CNTL                                                       0x835
++#define mmMC_HUB_WDP_ERR                                                        0x836
++#define mmMC_HUB_WDP_BP                                                         0x837
++#define mmMC_HUB_WDP_STATUS                                                     0x838
++#define mmMC_HUB_RDREQ_STATUS                                                   0x839
++#define mmMC_HUB_WRRET_STATUS                                                   0x83a
++#define mmMC_HUB_RDREQ_CNTL                                                     0x83b
++#define mmMC_HUB_WRRET_CNTL                                                     0x83c
++#define mmMC_HUB_RDREQ_WTM_CNTL                                                 0x83d
++#define mmMC_HUB_WDP_WTM_CNTL                                                   0x83e
++#define mmMC_HUB_WDP_CREDITS                                                    0x83f
++#define mmMC_HUB_WDP_CREDITS2                                                   0x840
++#define mmMC_HUB_WDP_GBL0                                                       0x841
++#define mmMC_HUB_WDP_GBL1                                                       0x842
++#define mmMC_HUB_RDREQ_CREDITS                                                  0x844
++#define mmMC_HUB_RDREQ_CREDITS2                                                 0x845
++#define mmMC_HUB_SHARED_DAGB_DLY                                                0x846
++#define mmMC_HUB_MISC_IDLE_STATUS                                               0x847
++#define mmMC_HUB_RDREQ_DMIF_LIMIT                                               0x848
++#define mmMC_HUB_RDREQ_ACPG_LIMIT                                               0x849
++#define mmMC_HUB_WDP_BYPASS_GBL0                                                0x84a
++#define mmMC_HUB_WDP_BYPASS_GBL1                                                0x84b
++#define mmMC_HUB_RDREQ_BYPASS_GBL0                                              0x84c
++#define mmMC_HUB_WDP_SH2                                                        0x84d
++#define mmMC_HUB_WDP_SH3                                                        0x84e
++#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS                                        0x84f
++#define mmMC_HUB_RDREQ_MCDW                                                     0x851
++#define mmMC_HUB_RDREQ_MCDX                                                     0x852
++#define mmMC_HUB_RDREQ_MCDY                                                     0x853
++#define mmMC_HUB_RDREQ_MCDZ                                                     0x854
++#define mmMC_HUB_RDREQ_SIP                                                      0x855
++#define mmMC_HUB_RDREQ_GBL0                                                     0x856
++#define mmMC_HUB_RDREQ_GBL1                                                     0x857
++#define mmMC_HUB_RDREQ_SMU                                                      0x858
++#define mmMC_HUB_RDREQ_SDMA0                                                    0x859
++#define mmMC_HUB_RDREQ_HDP                                                      0x85a
++#define mmMC_HUB_RDREQ_SDMA1                                                    0x85b
++#define mmMC_HUB_RDREQ_RLC                                                      0x85c
++#define mmMC_HUB_RDREQ_SEM                                                      0x85d
++#define mmMC_HUB_RDREQ_VCE0                                                     0x85e
++#define mmMC_HUB_RDREQ_UMC                                                      0x85f
++#define mmMC_HUB_RDREQ_UVD                                                      0x860
++#define mmMC_HUB_RDREQ_DMIF                                                     0x862
++#define mmMC_HUB_RDREQ_MCIF                                                     0x863
++#define mmMC_HUB_RDREQ_VMC                                                      0x864
++#define mmMC_HUB_RDREQ_VCEU0                                                    0x865
++#define mmMC_HUB_WDP_MCDW                                                       0x866
++#define mmMC_HUB_WDP_MCDX                                                       0x867
++#define mmMC_HUB_WDP_MCDY                                                       0x868
++#define mmMC_HUB_WDP_MCDZ                                                       0x869
++#define mmMC_HUB_WDP_SIP                                                        0x86a
++#define mmMC_HUB_WDP_SDMA1                                                      0x86b
++#define mmMC_HUB_WDP_SH0                                                        0x86c
++#define mmMC_HUB_WDP_MCIF                                                       0x86d
++#define mmMC_HUB_WDP_VCE0                                                       0x86e
++#define mmMC_HUB_WDP_XDP                                                        0x86f
++#define mmMC_HUB_WDP_IH                                                         0x870
++#define mmMC_HUB_WDP_RLC                                                        0x871
++#define mmMC_HUB_WDP_SEM                                                        0x872
++#define mmMC_HUB_WDP_SMU                                                        0x873
++#define mmMC_HUB_WDP_SH1                                                        0x874
++#define mmMC_HUB_WDP_UMC                                                        0x875
++#define mmMC_HUB_WDP_UVD                                                        0x876
++#define mmMC_HUB_WDP_HDP                                                        0x877
++#define mmMC_HUB_WDP_SDMA0                                                      0x878
++#define mmMC_HUB_WRRET_MCDW                                                     0x879
++#define mmMC_HUB_WRRET_MCDX                                                     0x87a
++#define mmMC_HUB_WRRET_MCDY                                                     0x87b
++#define mmMC_HUB_WRRET_MCDZ                                                     0x87c
++#define mmMC_HUB_WDP_VCEU0                                                      0x87d
++#define mmMC_HUB_WDP_XDMAM                                                      0x87e
++#define mmMC_HUB_WDP_XDMA                                                       0x87f
++#define mmMC_HUB_RDREQ_XDMAM                                                    0x880
++#define mmMC_HUB_RDREQ_ACPG                                                     0x881
++#define mmMC_HUB_RDREQ_ACPO                                                     0x882
++#define mmMC_HUB_RDREQ_SAMMSP                                                   0x883
++#define mmMC_HUB_RDREQ_VP8                                                      0x884
++#define mmMC_HUB_RDREQ_VP8U                                                     0x885
++#define mmMC_HUB_WDP_ACPG                                                       0x886
++#define mmMC_HUB_WDP_ACPO                                                       0x887
++#define mmMC_HUB_WDP_SAMMSP                                                     0x888
++#define mmMC_HUB_WDP_VP8                                                        0x889
++#define mmMC_HUB_WDP_VP8U                                                       0x88a
++#define mmMC_HUB_RDREQ_ISP_SPM                                                  0xde0
++#define mmMC_HUB_RDREQ_ISP_MPM                                                  0xde1
++#define mmMC_HUB_RDREQ_ISP_CCPU                                                 0xde2
++#define mmMC_HUB_WDP_ISP_SPM                                                    0xde3
++#define mmMC_HUB_WDP_ISP_MPS                                                    0xde4
++#define mmMC_HUB_WDP_ISP_MPM                                                    0xde5
++#define mmMC_HUB_WDP_ISP_CCPU                                                   0xde6
++#define mmMC_HUB_RDREQ_MCDS                                                     0xde7
++#define mmMC_HUB_RDREQ_MCDT                                                     0xde8
++#define mmMC_HUB_RDREQ_MCDU                                                     0xde9
++#define mmMC_HUB_RDREQ_MCDV                                                     0xdea
++#define mmMC_HUB_WDP_MCDS                                                       0xdeb
++#define mmMC_HUB_WDP_MCDT                                                       0xdec
++#define mmMC_HUB_WDP_MCDU                                                       0xded
++#define mmMC_HUB_WDP_MCDV                                                       0xdee
++#define mmMC_HUB_WRRET_MCDS                                                     0xdef
++#define mmMC_HUB_WRRET_MCDT                                                     0xdf0
++#define mmMC_HUB_WRRET_MCDU                                                     0xdf1
++#define mmMC_HUB_WRRET_MCDV                                                     0xdf2
++#define mmMC_HUB_WDP_CREDITS_MCDW                                               0xdf3
++#define mmMC_HUB_WDP_CREDITS_MCDX                                               0xdf4
++#define mmMC_HUB_WDP_CREDITS_MCDY                                               0xdf5
++#define mmMC_HUB_WDP_CREDITS_MCDZ                                               0xdf6
++#define mmMC_HUB_WDP_CREDITS_MCDS                                               0xdf7
++#define mmMC_HUB_WDP_CREDITS_MCDT                                               0xdf8
++#define mmMC_HUB_WDP_CREDITS_MCDU                                               0xdf9
++#define mmMC_HUB_WDP_CREDITS_MCDV                                               0xdfa
++#define mmMC_HUB_WDP_BP2                                                        0xdfb
++#define mmMC_HUB_RDREQ_VCE1                                                     0xdfc
++#define mmMC_HUB_RDREQ_VCEU1                                                    0xdfd
++#define mmMC_HUB_WDP_VCE1                                                       0xdfe
++#define mmMC_HUB_WDP_VCEU1                                                      0xdff
++#define mmMC_RPB_CONF                                                           0x94d
++#define mmMC_RPB_IF_CONF                                                        0x94e
++#define mmMC_RPB_DBG1                                                           0x94f
++#define mmMC_RPB_EFF_CNTL                                                       0x950
++#define mmMC_RPB_ARB_CNTL                                                       0x951
++#define mmMC_RPB_BIF_CNTL                                                       0x952
++#define mmMC_RPB_WR_SWITCH_CNTL                                                 0x953
++#define mmMC_RPB_WR_COMBINE_CNTL                                                0x954
++#define mmMC_RPB_RD_SWITCH_CNTL                                                 0x955
++#define mmMC_RPB_CID_QUEUE_WR                                                   0x956
++#define mmMC_RPB_CID_QUEUE_RD                                                   0x957
++#define mmMC_RPB_PERF_COUNTER_CNTL                                              0x958
++#define mmMC_RPB_PERF_COUNTER_STATUS                                            0x959
++#define mmMC_RPB_CID_QUEUE_EX                                                   0x95a
++#define mmMC_RPB_CID_QUEUE_EX_DATA                                              0x95b
++#define mmMC_RPB_TCI_CNTL                                                       0x95c
++#define mmMC_RPB_TCI_CNTL2                                                      0x95d
++#define mmMC_SHARED_CHMAP                                                       0x801
++#define mmMC_SHARED_CHREMAP                                                     0x802
++#define mmMC_RD_GRP_GFX                                                         0x803
++#define mmMC_WR_GRP_GFX                                                         0x804
++#define mmMC_RD_GRP_SYS                                                         0x805
++#define mmMC_WR_GRP_SYS                                                         0x806
++#define mmMC_RD_GRP_OTH                                                         0x807
++#define mmMC_WR_GRP_OTH                                                         0x808
++#define mmMC_VM_FB_LOCATION                                                     0x809
++#define mmMC_VM_AGP_TOP                                                         0x80a
++#define mmMC_VM_AGP_BOT                                                         0x80b
++#define mmMC_VM_AGP_BASE                                                        0x80c
++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR                                        0x80d
++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                       0x80e
++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR                                    0x80f
++#define mmMC_VM_DC_WRITE_CNTL                                                   0x810
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR                                  0x811
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR                                  0x812
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR                                  0x813
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR                                  0x814
++#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR                                 0x815
++#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR                                 0x816
++#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR                                 0x817
++#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR                                 0x818
++#define mmMC_VM_MX_L1_TLB_CNTL                                                  0x819
++#define mmMC_VM_FB_OFFSET                                                       0x81a
++#define mmMC_VM_STEERING                                                        0x81b
++#define mmMC_SHARED_CHREMAP2                                                    0x81c
++#define mmMC_SHARED_VF_ENABLE                                                   0x81d
++#define mmMC_SHARED_VIRT_RESET_REQ                                              0x81e
++#define mmMC_SHARED_ACTIVE_FCN_ID                                               0x81f
++#define mmMC_CONFIG_MCD                                                         0x828
++#define mmMC_CG_CONFIG_MCD                                                      0x829
++#define mmMC_MEM_POWER_LS                                                       0x82a
++#define mmMC_SHARED_BLACKOUT_CNTL                                               0x82b
++#define mmMC_VM_MB_L1_TLB0_DEBUG                                                0x891
++#define mmMC_VM_MB_L1_TLB1_DEBUG                                                0x892
++#define mmMC_VM_MB_L1_TLB2_DEBUG                                                0x893
++#define mmMC_VM_MB_L1_TLB0_STATUS                                               0x895
++#define mmMC_VM_MB_L1_TLB1_STATUS                                               0x896
++#define mmMC_VM_MB_L1_TLB2_STATUS                                               0x897
++#define mmMC_VM_MB_L2ARBITER_L2_CREDITS                                         0x8a1
++#define mmMC_VM_MB_L1_TLB3_DEBUG                                                0x8a5
++#define mmMC_VM_MB_L1_TLB3_STATUS                                               0x8a6
++#define mmMC_VM_MD_L1_TLB0_DEBUG                                                0x998
++#define mmMC_VM_MD_L1_TLB1_DEBUG                                                0x999
++#define mmMC_VM_MD_L1_TLB2_DEBUG                                                0x99a
++#define mmMC_VM_MD_L1_TLB0_STATUS                                               0x99b
++#define mmMC_VM_MD_L1_TLB1_STATUS                                               0x99c
++#define mmMC_VM_MD_L1_TLB2_STATUS                                               0x99d
++#define mmMC_VM_MD_L2ARBITER_L2_CREDITS                                         0x9a4
++#define mmMC_VM_MD_L1_TLB3_DEBUG                                                0x9a7
++#define mmMC_VM_MD_L1_TLB3_STATUS                                               0x9a8
++#define mmMC_XPB_RTR_SRC_APRTR0                                                 0x8cd
++#define mmMC_XPB_RTR_SRC_APRTR1                                                 0x8ce
++#define mmMC_XPB_RTR_SRC_APRTR2                                                 0x8cf
++#define mmMC_XPB_RTR_SRC_APRTR3                                                 0x8d0
++#define mmMC_XPB_RTR_SRC_APRTR4                                                 0x8d1
++#define mmMC_XPB_RTR_SRC_APRTR5                                                 0x8d2
++#define mmMC_XPB_RTR_SRC_APRTR6                                                 0x8d3
++#define mmMC_XPB_RTR_SRC_APRTR7                                                 0x8d4
++#define mmMC_XPB_RTR_SRC_APRTR8                                                 0x8d5
++#define mmMC_XPB_RTR_SRC_APRTR9                                                 0x8d6
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR0                                            0x8d7
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR1                                            0x8d8
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR2                                            0x8d9
++#define mmMC_XPB_XDMA_RTR_SRC_APRTR3                                            0x8da
++#define mmMC_XPB_RTR_DEST_MAP0                                                  0x8db
++#define mmMC_XPB_RTR_DEST_MAP1                                                  0x8dc
++#define mmMC_XPB_RTR_DEST_MAP2                                                  0x8dd
++#define mmMC_XPB_RTR_DEST_MAP3                                                  0x8de
++#define mmMC_XPB_RTR_DEST_MAP4                                                  0x8df
++#define mmMC_XPB_RTR_DEST_MAP5                                                  0x8e0
++#define mmMC_XPB_RTR_DEST_MAP6                                                  0x8e1
++#define mmMC_XPB_RTR_DEST_MAP7                                                  0x8e2
++#define mmMC_XPB_RTR_DEST_MAP8                                                  0x8e3
++#define mmMC_XPB_RTR_DEST_MAP9                                                  0x8e4
++#define mmMC_XPB_XDMA_RTR_DEST_MAP0                                             0x8e5
++#define mmMC_XPB_XDMA_RTR_DEST_MAP1                                             0x8e6
++#define mmMC_XPB_XDMA_RTR_DEST_MAP2                                             0x8e7
++#define mmMC_XPB_XDMA_RTR_DEST_MAP3                                             0x8e8
++#define mmMC_XPB_CLG_CFG0                                                       0x8e9
++#define mmMC_XPB_CLG_CFG1                                                       0x8ea
++#define mmMC_XPB_CLG_CFG2                                                       0x8eb
++#define mmMC_XPB_CLG_CFG3                                                       0x8ec
++#define mmMC_XPB_CLG_CFG4                                                       0x8ed
++#define mmMC_XPB_CLG_CFG5                                                       0x8ee
++#define mmMC_XPB_CLG_CFG6                                                       0x8ef
++#define mmMC_XPB_CLG_CFG7                                                       0x8f0
++#define mmMC_XPB_CLG_CFG8                                                       0x8f1
++#define mmMC_XPB_CLG_CFG9                                                       0x8f2
++#define mmMC_XPB_CLG_CFG10                                                      0x8f3
++#define mmMC_XPB_CLG_CFG11                                                      0x8f4
++#define mmMC_XPB_CLG_CFG12                                                      0x8f5
++#define mmMC_XPB_CLG_CFG13                                                      0x8f6
++#define mmMC_XPB_CLG_CFG14                                                      0x8f7
++#define mmMC_XPB_CLG_CFG15                                                      0x8f8
++#define mmMC_XPB_CLG_CFG16                                                      0x8f9
++#define mmMC_XPB_CLG_CFG17                                                      0x8fa
++#define mmMC_XPB_CLG_CFG18                                                      0x8fb
++#define mmMC_XPB_CLG_CFG19                                                      0x8fc
++#define mmMC_XPB_CLG_EXTRA                                                      0x8fd
++#define mmMC_XPB_LB_ADDR                                                        0x8fe
++#define mmMC_XPB_UNC_THRESH_HST                                                 0x8ff
++#define mmMC_XPB_UNC_THRESH_SID                                                 0x900
++#define mmMC_XPB_WCB_STS                                                        0x901
++#define mmMC_XPB_WCB_CFG                                                        0x902
++#define mmMC_XPB_P2P_BAR_CFG                                                    0x903
++#define mmMC_XPB_P2P_BAR0                                                       0x904
++#define mmMC_XPB_P2P_BAR1                                                       0x905
++#define mmMC_XPB_P2P_BAR2                                                       0x906
++#define mmMC_XPB_P2P_BAR3                                                       0x907
++#define mmMC_XPB_P2P_BAR4                                                       0x908
++#define mmMC_XPB_P2P_BAR5                                                       0x909
++#define mmMC_XPB_P2P_BAR6                                                       0x90a
++#define mmMC_XPB_P2P_BAR7                                                       0x90b
++#define mmMC_XPB_P2P_BAR_SETUP                                                  0x90c
++#define mmMC_XPB_P2P_BAR_DEBUG                                                  0x90d
++#define mmMC_XPB_P2P_BAR_DELTA_ABOVE                                            0x90e
++#define mmMC_XPB_P2P_BAR_DELTA_BELOW                                            0x90f
++#define mmMC_XPB_PEER_SYS_BAR0                                                  0x910
++#define mmMC_XPB_PEER_SYS_BAR1                                                  0x911
++#define mmMC_XPB_PEER_SYS_BAR2                                                  0x912
++#define mmMC_XPB_PEER_SYS_BAR3                                                  0x913
++#define mmMC_XPB_PEER_SYS_BAR4                                                  0x914
++#define mmMC_XPB_PEER_SYS_BAR5                                                  0x915
++#define mmMC_XPB_PEER_SYS_BAR6                                                  0x916
++#define mmMC_XPB_PEER_SYS_BAR7                                                  0x917
++#define mmMC_XPB_PEER_SYS_BAR8                                                  0x918
++#define mmMC_XPB_PEER_SYS_BAR9                                                  0x919
++#define mmMC_XPB_XDMA_PEER_SYS_BAR0                                             0x91a
++#define mmMC_XPB_XDMA_PEER_SYS_BAR1                                             0x91b
++#define mmMC_XPB_XDMA_PEER_SYS_BAR2                                             0x91c
++#define mmMC_XPB_XDMA_PEER_SYS_BAR3                                             0x91d
++#define mmMC_XPB_CLK_GAT                                                        0x91e
++#define mmMC_XPB_INTF_CFG                                                       0x91f
++#define mmMC_XPB_INTF_STS                                                       0x920
++#define mmMC_XPB_PIPE_STS                                                       0x921
++#define mmMC_XPB_SUB_CTRL                                                       0x922
++#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB                                       0x923
++#define mmMC_XPB_PERF_KNOBS                                                     0x924
++#define mmMC_XPB_STICKY                                                         0x925
++#define mmMC_XPB_STICKY_W1C                                                     0x926
++#define mmMC_XPB_MISC_CFG                                                       0x927
++#define mmMC_XPB_CLG_CFG20                                                      0x928
++#define mmMC_XPB_CLG_CFG21                                                      0x929
++#define mmMC_XPB_CLG_CFG22                                                      0x92a
++#define mmMC_XPB_CLG_CFG23                                                      0x92b
++#define mmMC_XPB_CLG_CFG24                                                      0x92c
++#define mmMC_XPB_CLG_CFG25                                                      0x92d
++#define mmMC_XPB_CLG_CFG26                                                      0x92e
++#define mmMC_XPB_CLG_CFG27                                                      0x92f
++#define mmMC_XPB_CLG_CFG28                                                      0x930
++#define mmMC_XPB_CLG_CFG29                                                      0x931
++#define mmMC_XPB_CLG_CFG30                                                      0x932
++#define mmMC_XPB_CLG_CFG31                                                      0x933
++#define mmMC_XPB_INTF_CFG2                                                      0x934
++#define mmMC_XPB_CLG_EXTRA_RD                                                   0x935
++#define mmMC_XPB_CLG_CFG32                                                      0x936
++#define mmMC_XPB_CLG_CFG33                                                      0x937
++#define mmMC_XPB_CLG_CFG34                                                      0x938
++#define mmMC_XPB_CLG_CFG35                                                      0x939
++#define mmMC_XPB_CLG_CFG36                                                      0x93a
++#define mmMC_XBAR_ADDR_DEC                                                      0xc80
++#define mmMC_XBAR_REMOTE                                                        0xc81
++#define mmMC_XBAR_WRREQ_CREDIT                                                  0xc82
++#define mmMC_XBAR_RDREQ_CREDIT                                                  0xc83
++#define mmMC_XBAR_RDREQ_PRI_CREDIT                                              0xc84
++#define mmMC_XBAR_WRRET_CREDIT1                                                 0xc85
++#define mmMC_XBAR_WRRET_CREDIT2                                                 0xc86
++#define mmMC_XBAR_RDRET_CREDIT1                                                 0xc87
++#define mmMC_XBAR_RDRET_CREDIT2                                                 0xc88
++#define mmMC_XBAR_RDRET_PRI_CREDIT1                                             0xc89
++#define mmMC_XBAR_RDRET_PRI_CREDIT2                                             0xc8a
++#define mmMC_XBAR_CHTRIREMAP                                                    0xc8b
++#define mmMC_XBAR_TWOCHAN                                                       0xc8c
++#define mmMC_XBAR_ARB                                                           0xc8d
++#define mmMC_XBAR_ARB_MAX_BURST                                                 0xc8e
++#define mmMC_XBAR_FIFO_MON_CNTL0                                                0xc8f
++#define mmMC_XBAR_FIFO_MON_CNTL1                                                0xc90
++#define mmMC_XBAR_FIFO_MON_CNTL2                                                0xc91
++#define mmMC_XBAR_FIFO_MON_RSLT0                                                0xc92
++#define mmMC_XBAR_FIFO_MON_RSLT1                                                0xc93
++#define mmMC_XBAR_FIFO_MON_RSLT2                                                0xc94
++#define mmMC_XBAR_FIFO_MON_RSLT3                                                0xc95
++#define mmMC_XBAR_FIFO_MON_MAX_THSH                                             0xc96
++#define mmMC_XBAR_SPARE0                                                        0xc97
++#define mmMC_XBAR_SPARE1                                                        0xc98
++#define mmMC_CITF_PERFCOUNTER_LO                                                0x7a0
++#define mmMC_HUB_PERFCOUNTER_LO                                                 0x7a1
++#define mmMC_RPB_PERFCOUNTER_LO                                                 0x7a2
++#define mmMC_MCBVM_PERFCOUNTER_LO                                               0x7a3
++#define mmMC_MCDVM_PERFCOUNTER_LO                                               0x7a4
++#define mmMC_VM_L2_PERFCOUNTER_LO                                               0x7a5
++#define mmMC_ARB_PERFCOUNTER_LO                                                 0x7a6
++#define mmATC_PERFCOUNTER_LO                                                    0x7a7
++#define mmMC_CITF_PERFCOUNTER_HI                                                0x7a8
++#define mmMC_HUB_PERFCOUNTER_HI                                                 0x7a9
++#define mmMC_MCBVM_PERFCOUNTER_HI                                               0x7aa
++#define mmMC_MCDVM_PERFCOUNTER_HI                                               0x7ab
++#define mmMC_RPB_PERFCOUNTER_HI                                                 0x7ac
++#define mmMC_VM_L2_PERFCOUNTER_HI                                               0x7ad
++#define mmMC_ARB_PERFCOUNTER_HI                                                 0x7ae
++#define mmATC_PERFCOUNTER_HI                                                    0x7af
++#define mmMC_CITF_PERFCOUNTER0_CFG                                              0x7b0
++#define mmMC_CITF_PERFCOUNTER1_CFG                                              0x7b1
++#define mmMC_CITF_PERFCOUNTER2_CFG                                              0x7b2
++#define mmMC_CITF_PERFCOUNTER3_CFG                                              0x7b3
++#define mmMC_HUB_PERFCOUNTER0_CFG                                               0x7b4
++#define mmMC_HUB_PERFCOUNTER1_CFG                                               0x7b5
++#define mmMC_HUB_PERFCOUNTER2_CFG                                               0x7b6
++#define mmMC_HUB_PERFCOUNTER3_CFG                                               0x7b7
++#define mmMC_RPB_PERFCOUNTER0_CFG                                               0x7b8
++#define mmMC_RPB_PERFCOUNTER1_CFG                                               0x7b9
++#define mmMC_RPB_PERFCOUNTER2_CFG                                               0x7ba
++#define mmMC_RPB_PERFCOUNTER3_CFG                                               0x7bb
++#define mmMC_ARB_PERFCOUNTER0_CFG                                               0x7bc
++#define mmMC_ARB_PERFCOUNTER1_CFG                                               0x7bd
++#define mmMC_ARB_PERFCOUNTER2_CFG                                               0x7be
++#define mmMC_ARB_PERFCOUNTER3_CFG                                               0x7bf
++#define mmMC_MCBVM_PERFCOUNTER0_CFG                                             0x7c0
++#define mmMC_MCBVM_PERFCOUNTER1_CFG                                             0x7c1
++#define mmMC_MCBVM_PERFCOUNTER2_CFG                                             0x7c2
++#define mmMC_MCBVM_PERFCOUNTER3_CFG                                             0x7c3
++#define mmMC_MCDVM_PERFCOUNTER0_CFG                                             0x7c4
++#define mmMC_MCDVM_PERFCOUNTER1_CFG                                             0x7c5
++#define mmMC_MCDVM_PERFCOUNTER2_CFG                                             0x7c6
++#define mmMC_MCDVM_PERFCOUNTER3_CFG                                             0x7c7
++#define mmATC_PERFCOUNTER0_CFG                                                  0x7c8
++#define mmATC_PERFCOUNTER1_CFG                                                  0x7c9
++#define mmATC_PERFCOUNTER2_CFG                                                  0x7ca
++#define mmATC_PERFCOUNTER3_CFG                                                  0x7cb
++#define mmMC_VM_L2_PERFCOUNTER0_CFG                                             0x7cc
++#define mmMC_VM_L2_PERFCOUNTER1_CFG                                             0x7cd
++#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL                                         0x7ce
++#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL                                          0x7cf
++#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL                                          0x7d0
++#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL                                        0x7d1
++#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL                                        0x7d2
++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                        0x7d3
++#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL                                          0x7d4
++#define mmATC_PERFCOUNTER_RSLT_CNTL                                             0x7d5
++#define mmCHUB_ATC_PERFCOUNTER_LO                                               0x7d6
++#define mmCHUB_ATC_PERFCOUNTER_HI                                               0x7d7
++#define mmCHUB_ATC_PERFCOUNTER0_CFG                                             0x7d8
++#define mmCHUB_ATC_PERFCOUNTER1_CFG                                             0x7d9
++#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL                                        0x7da
++#define mmMC_GRUB_PERFCOUNTER_LO                                                0x7e4
++#define mmMC_GRUB_PERFCOUNTER_HI                                                0x7e5
++#define mmMC_GRUB_PERFCOUNTER0_CFG                                              0x7e6
++#define mmMC_GRUB_PERFCOUNTER1_CFG                                              0x7e7
++#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL                                         0x7e8
++#define mmATC_VM_APERTURE0_LOW_ADDR                                             0xcc0
++#define mmATC_VM_APERTURE1_LOW_ADDR                                             0xcc1
++#define mmATC_VM_APERTURE0_HIGH_ADDR                                            0xcc2
++#define mmATC_VM_APERTURE1_HIGH_ADDR                                            0xcc3
++#define mmATC_VM_APERTURE0_CNTL                                                 0xcc4
++#define mmATC_VM_APERTURE1_CNTL                                                 0xcc5
++#define mmATC_VM_APERTURE0_CNTL2                                                0xcc6
++#define mmATC_VM_APERTURE1_CNTL2                                                0xcc7
++#define mmATC_ATS_CNTL                                                          0xcc9
++#define mmATC_ATS_DEBUG                                                         0xcca
++#define mmATC_ATS_FAULT_DEBUG                                                   0xccb
++#define mmATC_ATS_STATUS                                                        0xccc
++#define mmATC_ATS_FAULT_CNTL                                                    0xccd
++#define mmATC_ATS_FAULT_STATUS_INFO                                             0xcce
++#define mmATC_ATS_FAULT_STATUS_ADDR                                             0xccf
++#define mmATC_ATS_DEFAULT_PAGE_LOW                                              0xcd0
++#define mmATC_ATS_DEFAULT_PAGE_CNTL                                             0xcd1
++#define mmATC_ATS_FAULT_STATUS_INFO2                                            0xcd2
++#define mmATC_MISC_CG                                                           0xcd4
++#define mmATC_L2_CNTL                                                           0xcd5
++#define mmATC_L2_CNTL2                                                          0xcd6
++#define mmATC_L2_DEBUG                                                          0xcd7
++#define mmATC_L2_DEBUG2                                                         0xcd8
++#define mmATC_L2_CACHE_DATA0                                                    0xcd9
++#define mmATC_L2_CACHE_DATA1                                                    0xcda
++#define mmATC_L2_CACHE_DATA2                                                    0xcdb
++#define mmATC_L1_CNTL                                                           0xcdc
++#define mmATC_L1_ADDRESS_OFFSET                                                 0xcdd
++#define mmATC_L1RD_DEBUG_TLB                                                    0xcde
++#define mmATC_L1WR_DEBUG_TLB                                                    0xcdf
++#define mmATC_L1RD_STATUS                                                       0xce0
++#define mmATC_L1WR_STATUS                                                       0xce1
++#define mmATC_L1RD_DEBUG2_TLB                                                   0xce2
++#define mmATC_L1WR_DEBUG2_TLB                                                   0xce3
++#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS                                  0xce6
++#define mmATC_VMID0_PASID_MAPPING                                               0xce7
++#define mmATC_VMID1_PASID_MAPPING                                               0xce8
++#define mmATC_VMID2_PASID_MAPPING                                               0xce9
++#define mmATC_VMID3_PASID_MAPPING                                               0xcea
++#define mmATC_VMID4_PASID_MAPPING                                               0xceb
++#define mmATC_VMID5_PASID_MAPPING                                               0xcec
++#define mmATC_VMID6_PASID_MAPPING                                               0xced
++#define mmATC_VMID7_PASID_MAPPING                                               0xcee
++#define mmATC_VMID8_PASID_MAPPING                                               0xcef
++#define mmATC_VMID9_PASID_MAPPING                                               0xcf0
++#define mmATC_VMID10_PASID_MAPPING                                              0xcf1
++#define mmATC_VMID11_PASID_MAPPING                                              0xcf2
++#define mmATC_VMID12_PASID_MAPPING                                              0xcf3
++#define mmATC_VMID13_PASID_MAPPING                                              0xcf4
++#define mmATC_VMID14_PASID_MAPPING                                              0xcf5
++#define mmATC_VMID15_PASID_MAPPING                                              0xcf6
++#define mmATC_ATS_VMID_STATUS                                                   0xd07
++#define mmATC_ATS_SMU_STATUS                                                    0xd08
++#define mmATC_L2_CNTL3                                                          0xd09
++#define mmATC_L2_STATUS                                                         0xd0a
++#define mmATC_L2_STATUS2                                                        0xd0b
++#define mmGMCON_RENG_RAM_INDEX                                                  0xd40
++#define mmGMCON_RENG_RAM_DATA                                                   0xd41
++#define mmGMCON_RENG_EXECUTE                                                    0xd42
++#define mmGMCON_MISC                                                            0xd43
++#define mmGMCON_MISC2                                                           0xd44
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0                                     0xd45
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1                                     0xd46
++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2                                     0xd47
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0                                  0xd48
++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1                                  0xd49
++#define mmGMCON_PERF_MON_CNTL0                                                  0xd4a
++#define mmGMCON_PERF_MON_CNTL1                                                  0xd4b
++#define mmGMCON_PERF_MON_RSLT0                                                  0xd4c
++#define mmGMCON_PERF_MON_RSLT1                                                  0xd4d
++#define mmGMCON_PGFSM_CONFIG                                                    0xd4e
++#define mmGMCON_PGFSM_WRITE                                                     0xd4f
++#define mmGMCON_PGFSM_READ                                                      0xd50
++#define mmGMCON_MISC3                                                           0xd51
++#define mmGMCON_MASK                                                            0xd52
++#define mmGMCON_LPT_TARGET                                                      0xd53
++#define mmGMCON_DEBUG                                                           0xd5f
++#define mmVM_L2_CNTL                                                            0x500
++#define mmVM_L2_CNTL2                                                           0x501
++#define mmVM_L2_CNTL3                                                           0x502
++#define mmVM_L2_STATUS                                                          0x503
++#define mmVM_CONTEXT0_CNTL                                                      0x504
++#define mmVM_CONTEXT1_CNTL                                                      0x505
++#define mmVM_DUMMY_PAGE_FAULT_CNTL                                              0x506
++#define mmVM_DUMMY_PAGE_FAULT_ADDR                                              0x507
++#define mmVM_CONTEXT0_CNTL2                                                     0x50c
++#define mmVM_CONTEXT1_CNTL2                                                     0x50d
++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR                                      0x50e
++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR                                      0x50f
++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR                                     0x510
++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR                                     0x511
++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR                                     0x512
++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR                                     0x513
++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR                                     0x514
++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR                                     0x515
++#define mmVM_INVALIDATE_REQUEST                                                 0x51e
++#define mmVM_INVALIDATE_RESPONSE                                                0x51f
++#define mmVM_PRT_APERTURE0_LOW_ADDR                                             0x52c
++#define mmVM_PRT_APERTURE1_LOW_ADDR                                             0x52d
++#define mmVM_PRT_APERTURE2_LOW_ADDR                                             0x52e
++#define mmVM_PRT_APERTURE3_LOW_ADDR                                             0x52f
++#define mmVM_PRT_APERTURE0_HIGH_ADDR                                            0x530
++#define mmVM_PRT_APERTURE1_HIGH_ADDR                                            0x531
++#define mmVM_PRT_APERTURE2_HIGH_ADDR                                            0x532
++#define mmVM_PRT_APERTURE3_HIGH_ADDR                                            0x533
++#define mmVM_PRT_CNTL                                                           0x534
++#define mmVM_CONTEXTS_DISABLE                                                   0x535
++#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS                                   0x536
++#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS                                   0x537
++#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT                                 0x538
++#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT                                 0x539
++#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR                                     0x53e
++#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR                                     0x53f
++#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR                             0x546
++#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR                             0x547
++#define mmVM_FAULT_CLIENT_ID                                                    0x54e
++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR                                      0x54f
++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR                                      0x550
++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR                                      0x551
++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR                                      0x552
++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR                                      0x553
++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR                                      0x554
++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR                                      0x555
++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR                                      0x556
++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR                                     0x557
++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR                                     0x558
++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR                                       0x55f
++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR                                       0x560
++#define mmVM_DEBUG                                                              0x56f
++#define mmVM_L2_CG                                                              0x570
++#define mmVM_L2_BANK_SELECT_MASKA                                               0x572
++#define mmVM_L2_BANK_SELECT_MASKB                                               0x573
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR                             0x575
++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR                            0x576
++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET                                0x577
++#define mmVM_L2_CNTL4                                                           0x578
++#define mmVM_L2_BANK_SELECT_RESERVED_CID                                        0x579
++#define mmMC_VM_FB_SIZE_OFFSET_VF0                                              0xf980
++#define mmMC_VM_FB_SIZE_OFFSET_VF1                                              0xf981
++#define mmMC_VM_FB_SIZE_OFFSET_VF2                                              0xf982
++#define mmMC_VM_FB_SIZE_OFFSET_VF3                                              0xf983
++#define mmMC_VM_FB_SIZE_OFFSET_VF4                                              0xf984
++#define mmMC_VM_FB_SIZE_OFFSET_VF5                                              0xf985
++#define mmMC_VM_FB_SIZE_OFFSET_VF6                                              0xf986
++#define mmMC_VM_FB_SIZE_OFFSET_VF7                                              0xf987
++#define mmMC_VM_FB_SIZE_OFFSET_VF8                                              0xf988
++#define mmMC_VM_FB_SIZE_OFFSET_VF9                                              0xf989
++#define mmMC_VM_FB_SIZE_OFFSET_VF10                                             0xf98a
++#define mmMC_VM_FB_SIZE_OFFSET_VF11                                             0xf98b
++#define mmMC_VM_FB_SIZE_OFFSET_VF12                                             0xf98c
++#define mmMC_VM_FB_SIZE_OFFSET_VF13                                             0xf98d
++#define mmMC_VM_FB_SIZE_OFFSET_VF14                                             0xf98e
++#define mmMC_VM_FB_SIZE_OFFSET_VF15                                             0xf98f
++#define mmMC_VM_NB_MMIOBASE                                                     0xf990
++#define mmMC_VM_NB_MMIOLIMIT                                                    0xf991
++#define mmMC_VM_NB_PCI_CTRL                                                     0xf992
++#define mmMC_VM_NB_PCI_ARB                                                      0xf993
++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1                                            0xf994
++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2                                           0xf995
++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2                                           0xf996
++#define mmMC_VM_NB_TOP_OF_DRAM3                                                 0xf997
++#define mmMC_VM_MARC_BASE_LO_0                                                  0xf998
++#define mmMC_VM_MARC_BASE_LO_1                                                  0xf99e
++#define mmMC_VM_MARC_BASE_LO_2                                                  0xf9a4
++#define mmMC_VM_MARC_BASE_LO_3                                                  0xf9aa
++#define mmMC_VM_MARC_BASE_HI_0                                                  0xf999
++#define mmMC_VM_MARC_BASE_HI_1                                                  0xf99f
++#define mmMC_VM_MARC_BASE_HI_2                                                  0xf9a5
++#define mmMC_VM_MARC_BASE_HI_3                                                  0xf9ab
++#define mmMC_VM_MARC_RELOC_LO_0                                                 0xf99a
++#define mmMC_VM_MARC_RELOC_LO_1                                                 0xf9a0
++#define mmMC_VM_MARC_RELOC_LO_2                                                 0xf9a6
++#define mmMC_VM_MARC_RELOC_LO_3                                                 0xf9ac
++#define mmMC_VM_MARC_RELOC_HI_0                                                 0xf99b
++#define mmMC_VM_MARC_RELOC_HI_1                                                 0xf9a1
++#define mmMC_VM_MARC_RELOC_HI_2                                                 0xf9a7
++#define mmMC_VM_MARC_RELOC_HI_3                                                 0xf9ad
++#define mmMC_VM_MARC_LEN_LO_0                                                   0xf99c
++#define mmMC_VM_MARC_LEN_LO_1                                                   0xf9a2
++#define mmMC_VM_MARC_LEN_LO_2                                                   0xf9a8
++#define mmMC_VM_MARC_LEN_LO_3                                                   0xf9ae
++#define mmMC_VM_MARC_LEN_HI_0                                                   0xf99d
++#define mmMC_VM_MARC_LEN_HI_1                                                   0xf9a3
++#define mmMC_VM_MARC_LEN_HI_2                                                   0xf9a9
++#define mmMC_VM_MARC_LEN_HI_3                                                   0xf9af
++#define mmMC_VM_MARC_CNTL                                                       0xf9b0
++#define mmMC_ARB_HARSH_EN_RD                                                    0xdc0
++#define mmMC_ARB_HARSH_EN_WR                                                    0xdc1
++#define mmMC_ARB_HARSH_TX_HI0_RD                                                0xdc2
++#define mmMC_ARB_HARSH_TX_HI0_WR                                                0xdc3
++#define mmMC_ARB_HARSH_TX_HI1_RD                                                0xdc4
++#define mmMC_ARB_HARSH_TX_HI1_WR                                                0xdc5
++#define mmMC_ARB_HARSH_TX_LO0_RD                                                0xdc6
++#define mmMC_ARB_HARSH_TX_LO0_WR                                                0xdc7
++#define mmMC_ARB_HARSH_TX_LO1_RD                                                0xdc8
++#define mmMC_ARB_HARSH_TX_LO1_WR                                                0xdc9
++#define mmMC_ARB_HARSH_BWPERIOD0_RD                                             0xdca
++#define mmMC_ARB_HARSH_BWPERIOD0_WR                                             0xdcb
++#define mmMC_ARB_HARSH_BWPERIOD1_RD                                             0xdcc
++#define mmMC_ARB_HARSH_BWPERIOD1_WR                                             0xdcd
++#define mmMC_ARB_HARSH_BWCNT0_RD                                                0xdce
++#define mmMC_ARB_HARSH_BWCNT0_WR                                                0xdcf
++#define mmMC_ARB_HARSH_BWCNT1_RD                                                0xdd0
++#define mmMC_ARB_HARSH_BWCNT1_WR                                                0xdd1
++#define mmMC_ARB_HARSH_SAT0_RD                                                  0xdd2
++#define mmMC_ARB_HARSH_SAT0_WR                                                  0xdd3
++#define mmMC_ARB_HARSH_SAT1_RD                                                  0xdd4
++#define mmMC_ARB_HARSH_SAT1_WR                                                  0xdd5
++#define mmMC_ARB_HARSH_CTL_RD                                                   0xdd6
++#define mmMC_ARB_HARSH_CTL_WR                                                   0xdd7
++#define mmMC_ARB_GRUB_PRIORITY1_RD                                              0xdd8
++#define mmMC_ARB_GRUB_PRIORITY1_WR                                              0xdd9
++#define mmMC_ARB_GRUB_PRIORITY2_RD                                              0xdda
++#define mmMC_ARB_GRUB_PRIORITY2_WR                                              0xddb
++#define mmMC_FUS_DRAM0_CS0_BASE                                                 0xa05
++#define mmMC_FUS_DRAM1_CS0_BASE                                                 0xa06
++#define mmMC_FUS_DRAM0_CS1_BASE                                                 0xa07
++#define mmMC_FUS_DRAM1_CS1_BASE                                                 0xa08
++#define mmMC_FUS_DRAM0_CS2_BASE                                                 0xa09
++#define mmMC_FUS_DRAM1_CS2_BASE                                                 0xa0a
++#define mmMC_FUS_DRAM0_CS3_BASE                                                 0xa0b
++#define mmMC_FUS_DRAM1_CS3_BASE                                                 0xa0c
++#define mmMC_FUS_DRAM0_CS01_MASK                                                0xa0d
++#define mmMC_FUS_DRAM1_CS01_MASK                                                0xa0e
++#define mmMC_FUS_DRAM0_CS23_MASK                                                0xa0f
++#define mmMC_FUS_DRAM1_CS23_MASK                                                0xa10
++#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING                                        0xa11
++#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING                                        0xa12
++#define mmMC_FUS_DRAM0_CTL_BASE                                                 0xa13
++#define mmMC_FUS_DRAM1_CTL_BASE                                                 0xa14
++#define mmMC_FUS_DRAM0_CTL_LIMIT                                                0xa15
++#define mmMC_FUS_DRAM1_CTL_LIMIT                                                0xa16
++#define mmMC_FUS_DRAM_CTL_HIGH_01                                               0xa17
++#define mmMC_FUS_DRAM_CTL_HIGH_23                                               0xa18
++#define mmMC_FUS_DRAM_MODE                                                      0xa19
++#define mmMC_FUS_DRAM_APER_BASE                                                 0xa1a
++#define mmMC_FUS_DRAM_APER_TOP                                                  0xa1b
++#define mmMC_FUS_DRAM_APER_DEF                                                  0xa1e
++#define mmMC_FUS_ARB_GARLIC_ISOC_PRI                                            0xa1f
++#define mmMC_FUS_ARB_GARLIC_CNTL                                                0xa20
++#define mmMC_FUS_ARB_GARLIC_WR_PRI                                              0xa21
++#define mmMC_FUS_ARB_GARLIC_WR_PRI2                                             0xa22
++#define mmMC_CG_DATAPORT                                                        0xa32
++#define mmMC_GRUB_PROBE_MAP                                                     0xa33
++#define mmMC_GRUB_POST_PROBE_DELAY                                              0xa34
++#define mmMC_GRUB_PROBE_CREDITS                                                 0xa35
++#define mmMC_GRUB_FEATURES                                                      0xa36
++#define mmMC_GRUB_TX_CREDITS                                                    0xa37
++#define mmMC_GRUB_TCB_INDEX                                                     0xa38
++#define mmMC_GRUB_TCB_DATA_LO                                                   0xa39
++#define mmMC_GRUB_TCB_DATA_HI                                                   0xa3a
++#define mmMCIF_WB_BUFMGR_SW_CONTROL                                             0x5e78
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5e78
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5eb8
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                                    0x5ef8
++#define mmMCIF_WB_BUFMGR_CUR_LINE_R                                             0x5e79
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                                    0x5e79
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                                    0x5eb9
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                                    0x5ef9
++#define mmMCIF_WB_BUFMGR_STATUS                                                 0x5e7a
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                                        0x5e7a
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                                        0x5eba
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                                        0x5efa
++#define mmMCIF_WB_BUF_PITCH                                                     0x5e7b
++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH                                            0x5e7b
++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH                                            0x5ebb
++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH                                            0x5efb
++#define mmMCIF_WB_BUF_1_STATUS                                                  0x5e7c
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                                         0x5e7c
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                                         0x5ebc
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                                         0x5efc
++#define mmMCIF_WB_BUF_1_STATUS2                                                 0x5e7d
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                                        0x5e7d
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                                        0x5ebd
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                                        0x5efd
++#define mmMCIF_WB_BUF_2_STATUS                                                  0x5e7e
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                                         0x5e7e
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                                         0x5ebe
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                                         0x5efe
++#define mmMCIF_WB_BUF_2_STATUS2                                                 0x5e7f
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                                        0x5e7f
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                                        0x5ebf
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                                        0x5eff
++#define mmMCIF_WB_BUF_3_STATUS                                                  0x5e80
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                                         0x5e80
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                                         0x5ec0
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                                         0x5f00
++#define mmMCIF_WB_BUF_3_STATUS2                                                 0x5e81
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                                        0x5e81
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                                        0x5ec1
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                                        0x5f01
++#define mmMCIF_WB_BUF_4_STATUS                                                  0x5e82
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                                         0x5e82
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                                         0x5ec2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                                         0x5f02
++#define mmMCIF_WB_BUF_4_STATUS2                                                 0x5e83
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                                        0x5e83
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                                        0x5ec3
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                                        0x5f03
++#define mmMCIF_WB_ARBITRATION_CONTROL                                           0x5e84
++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                                  0x5e84
++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                                  0x5ec4
++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                                  0x5f04
++#define mmMCIF_WB_URGENCY_WATERMARK                                             0x5e85
++#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK                                    0x5e85
++#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK                                    0x5ec5
++#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK                                    0x5f05
++#define mmMCIF_WB_TEST_DEBUG_INDEX                                              0x5e86
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                                     0x5e86
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                                     0x5ec6
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                                     0x5f06
++#define mmMCIF_WB_TEST_DEBUG_DATA                                               0x5e87
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                                      0x5e87
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                                      0x5ec7
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                                      0x5f07
++#define mmMCIF_WB_BUF_1_ADDR_Y                                                  0x5e88
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                                         0x5e88
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                                         0x5ec8
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                                         0x5f08
++#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET                                           0x5e89
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                  0x5e89
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                  0x5ec9
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                  0x5f09
++#define mmMCIF_WB_BUF_1_ADDR_C                                                  0x5e8a
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                                         0x5e8a
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                                         0x5eca
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                                         0x5f0a
++#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET                                           0x5e8b
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                                  0x5e8b
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                                  0x5ecb
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                                  0x5f0b
++#define mmMCIF_WB_BUF_2_ADDR_Y                                                  0x5e8c
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                                         0x5e8c
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                                         0x5ecc
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                                         0x5f0c
++#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET                                           0x5e8d
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                  0x5e8d
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                  0x5ecd
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                  0x5f0d
++#define mmMCIF_WB_BUF_2_ADDR_C                                                  0x5e8e
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                                         0x5e8e
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                                         0x5ece
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                                         0x5f0e
++#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET                                           0x5e8f
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                                  0x5e8f
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                                  0x5ecf
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                                  0x5f0f
++#define mmMCIF_WB_BUF_3_ADDR_Y                                                  0x5e90
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                                         0x5e90
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                                         0x5ed0
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                                         0x5f10
++#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET                                           0x5e91
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                  0x5e91
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                  0x5ed1
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                  0x5f11
++#define mmMCIF_WB_BUF_3_ADDR_C                                                  0x5e92
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                                         0x5e92
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                                         0x5ed2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                                         0x5f12
++#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET                                           0x5e93
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                                  0x5e93
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                                  0x5ed3
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                                  0x5f13
++#define mmMCIF_WB_BUF_4_ADDR_Y                                                  0x5e94
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                                         0x5e94
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                                         0x5ed4
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                                         0x5f14
++#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET                                           0x5e95
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                  0x5e95
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                  0x5ed5
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                  0x5f15
++#define mmMCIF_WB_BUF_4_ADDR_C                                                  0x5e96
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                                         0x5e96
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                                         0x5ed6
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                                         0x5f16
++#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET                                           0x5e97
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                                  0x5e97
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                                  0x5ed7
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                                  0x5f17
++#define mmMCIF_WB_BUFMGR_VCE_CONTROL                                            0x5e98
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                                   0x5e98
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                                   0x5ed8
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                                   0x5f18
++#define mmMCIF_WB_HVVMID_CONTROL                                                0x5e99
++#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL                                       0x5e99
++#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL                                       0x5ed9
++#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL                                       0x5f19
++
++#endif /* GMC_8_2_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
+new file mode 100644
+index 0000000..bc18e4d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
+@@ -0,0 +1,1068 @@
++/*
++ * GMC_8_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_8_2_ENUM_H
++#define GMC_8_2_ENUM_H
++
++typedef enum DebugBlockId {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_UVDU                                = 0xd,
++	DBG_BLOCK_ID_SQA                                 = 0xe,
++	DBG_BLOCK_ID_SDMA0                               = 0xf,
++	DBG_BLOCK_ID_SDMA1                               = 0x10,
++	DBG_BLOCK_ID_SPIM                                = 0x11,
++	DBG_BLOCK_ID_GDS                                 = 0x12,
++	DBG_BLOCK_ID_VC0                                 = 0x13,
++	DBG_BLOCK_ID_VC1                                 = 0x14,
++	DBG_BLOCK_ID_PA0                                 = 0x15,
++	DBG_BLOCK_ID_PA1                                 = 0x16,
++	DBG_BLOCK_ID_CP0                                 = 0x17,
++	DBG_BLOCK_ID_CP1                                 = 0x18,
++	DBG_BLOCK_ID_CP2                                 = 0x19,
++	DBG_BLOCK_ID_XBR                                 = 0x1a,
++	DBG_BLOCK_ID_UVDM                                = 0x1b,
++	DBG_BLOCK_ID_VGT0                                = 0x1c,
++	DBG_BLOCK_ID_VGT1                                = 0x1d,
++	DBG_BLOCK_ID_IA                                  = 0x1e,
++	DBG_BLOCK_ID_SXM0                                = 0x1f,
++	DBG_BLOCK_ID_SXM1                                = 0x20,
++	DBG_BLOCK_ID_SCT0                                = 0x21,
++	DBG_BLOCK_ID_SCT1                                = 0x22,
++	DBG_BLOCK_ID_SPM0                                = 0x23,
++	DBG_BLOCK_ID_SPM1                                = 0x24,
++	DBG_BLOCK_ID_UNUSED0                             = 0x25,
++	DBG_BLOCK_ID_UNUSED1                             = 0x26,
++	DBG_BLOCK_ID_TCAA                                = 0x27,
++	DBG_BLOCK_ID_TCAB                                = 0x28,
++	DBG_BLOCK_ID_TCCA                                = 0x29,
++	DBG_BLOCK_ID_TCCB                                = 0x2a,
++	DBG_BLOCK_ID_MCC0                                = 0x2b,
++	DBG_BLOCK_ID_MCC1                                = 0x2c,
++	DBG_BLOCK_ID_MCC2                                = 0x2d,
++	DBG_BLOCK_ID_MCC3                                = 0x2e,
++	DBG_BLOCK_ID_SXS0                                = 0x2f,
++	DBG_BLOCK_ID_SXS1                                = 0x30,
++	DBG_BLOCK_ID_SXS2                                = 0x31,
++	DBG_BLOCK_ID_SXS3                                = 0x32,
++	DBG_BLOCK_ID_SXS4                                = 0x33,
++	DBG_BLOCK_ID_SXS5                                = 0x34,
++	DBG_BLOCK_ID_SXS6                                = 0x35,
++	DBG_BLOCK_ID_SXS7                                = 0x36,
++	DBG_BLOCK_ID_SXS8                                = 0x37,
++	DBG_BLOCK_ID_SXS9                                = 0x38,
++	DBG_BLOCK_ID_BCI0                                = 0x39,
++	DBG_BLOCK_ID_BCI1                                = 0x3a,
++	DBG_BLOCK_ID_BCI2                                = 0x3b,
++	DBG_BLOCK_ID_BCI3                                = 0x3c,
++	DBG_BLOCK_ID_MCB                                 = 0x3d,
++	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
++	DBG_BLOCK_ID_SQA00                               = 0x3f,
++	DBG_BLOCK_ID_SQA01                               = 0x40,
++	DBG_BLOCK_ID_SQA02                               = 0x41,
++	DBG_BLOCK_ID_SQA10                               = 0x42,
++	DBG_BLOCK_ID_SQA11                               = 0x43,
++	DBG_BLOCK_ID_SQA12                               = 0x44,
++	DBG_BLOCK_ID_UNUSED7                             = 0x45,
++	DBG_BLOCK_ID_UNUSED8                             = 0x46,
++	DBG_BLOCK_ID_SQB00                               = 0x47,
++	DBG_BLOCK_ID_SQB01                               = 0x48,
++	DBG_BLOCK_ID_SQB10                               = 0x49,
++	DBG_BLOCK_ID_SQB11                               = 0x4a,
++	DBG_BLOCK_ID_SQ00                                = 0x4b,
++	DBG_BLOCK_ID_SQ01                                = 0x4c,
++	DBG_BLOCK_ID_SQ10                                = 0x4d,
++	DBG_BLOCK_ID_SQ11                                = 0x4e,
++	DBG_BLOCK_ID_CB00                                = 0x4f,
++	DBG_BLOCK_ID_CB01                                = 0x50,
++	DBG_BLOCK_ID_CB02                                = 0x51,
++	DBG_BLOCK_ID_CB03                                = 0x52,
++	DBG_BLOCK_ID_CB04                                = 0x53,
++	DBG_BLOCK_ID_UNUSED9                             = 0x54,
++	DBG_BLOCK_ID_UNUSED10                            = 0x55,
++	DBG_BLOCK_ID_UNUSED11                            = 0x56,
++	DBG_BLOCK_ID_CB10                                = 0x57,
++	DBG_BLOCK_ID_CB11                                = 0x58,
++	DBG_BLOCK_ID_CB12                                = 0x59,
++	DBG_BLOCK_ID_CB13                                = 0x5a,
++	DBG_BLOCK_ID_CB14                                = 0x5b,
++	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
++	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
++	DBG_BLOCK_ID_TCP0                                = 0x5f,
++	DBG_BLOCK_ID_TCP1                                = 0x60,
++	DBG_BLOCK_ID_TCP2                                = 0x61,
++	DBG_BLOCK_ID_TCP3                                = 0x62,
++	DBG_BLOCK_ID_TCP4                                = 0x63,
++	DBG_BLOCK_ID_TCP5                                = 0x64,
++	DBG_BLOCK_ID_TCP6                                = 0x65,
++	DBG_BLOCK_ID_TCP7                                = 0x66,
++	DBG_BLOCK_ID_TCP8                                = 0x67,
++	DBG_BLOCK_ID_TCP9                                = 0x68,
++	DBG_BLOCK_ID_TCP10                               = 0x69,
++	DBG_BLOCK_ID_TCP11                               = 0x6a,
++	DBG_BLOCK_ID_TCP12                               = 0x6b,
++	DBG_BLOCK_ID_TCP13                               = 0x6c,
++	DBG_BLOCK_ID_TCP14                               = 0x6d,
++	DBG_BLOCK_ID_TCP15                               = 0x6e,
++	DBG_BLOCK_ID_TCP16                               = 0x6f,
++	DBG_BLOCK_ID_TCP17                               = 0x70,
++	DBG_BLOCK_ID_TCP18                               = 0x71,
++	DBG_BLOCK_ID_TCP19                               = 0x72,
++	DBG_BLOCK_ID_TCP20                               = 0x73,
++	DBG_BLOCK_ID_TCP21                               = 0x74,
++	DBG_BLOCK_ID_TCP22                               = 0x75,
++	DBG_BLOCK_ID_TCP23                               = 0x76,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
++	DBG_BLOCK_ID_DB00                                = 0x7f,
++	DBG_BLOCK_ID_DB01                                = 0x80,
++	DBG_BLOCK_ID_DB02                                = 0x81,
++	DBG_BLOCK_ID_DB03                                = 0x82,
++	DBG_BLOCK_ID_DB04                                = 0x83,
++	DBG_BLOCK_ID_UNUSED15                            = 0x84,
++	DBG_BLOCK_ID_UNUSED16                            = 0x85,
++	DBG_BLOCK_ID_UNUSED17                            = 0x86,
++	DBG_BLOCK_ID_DB10                                = 0x87,
++	DBG_BLOCK_ID_DB11                                = 0x88,
++	DBG_BLOCK_ID_DB12                                = 0x89,
++	DBG_BLOCK_ID_DB13                                = 0x8a,
++	DBG_BLOCK_ID_DB14                                = 0x8b,
++	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
++	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
++	DBG_BLOCK_ID_TCC0                                = 0x8f,
++	DBG_BLOCK_ID_TCC1                                = 0x90,
++	DBG_BLOCK_ID_TCC2                                = 0x91,
++	DBG_BLOCK_ID_TCC3                                = 0x92,
++	DBG_BLOCK_ID_TCC4                                = 0x93,
++	DBG_BLOCK_ID_TCC5                                = 0x94,
++	DBG_BLOCK_ID_TCC6                                = 0x95,
++	DBG_BLOCK_ID_TCC7                                = 0x96,
++	DBG_BLOCK_ID_SPS00                               = 0x97,
++	DBG_BLOCK_ID_SPS01                               = 0x98,
++	DBG_BLOCK_ID_SPS02                               = 0x99,
++	DBG_BLOCK_ID_SPS10                               = 0x9a,
++	DBG_BLOCK_ID_SPS11                               = 0x9b,
++	DBG_BLOCK_ID_SPS12                               = 0x9c,
++	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
++	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
++	DBG_BLOCK_ID_TA00                                = 0x9f,
++	DBG_BLOCK_ID_TA01                                = 0xa0,
++	DBG_BLOCK_ID_TA02                                = 0xa1,
++	DBG_BLOCK_ID_TA03                                = 0xa2,
++	DBG_BLOCK_ID_TA04                                = 0xa3,
++	DBG_BLOCK_ID_TA05                                = 0xa4,
++	DBG_BLOCK_ID_TA06                                = 0xa5,
++	DBG_BLOCK_ID_TA07                                = 0xa6,
++	DBG_BLOCK_ID_TA08                                = 0xa7,
++	DBG_BLOCK_ID_TA09                                = 0xa8,
++	DBG_BLOCK_ID_TA0A                                = 0xa9,
++	DBG_BLOCK_ID_TA0B                                = 0xaa,
++	DBG_BLOCK_ID_UNUSED23                            = 0xab,
++	DBG_BLOCK_ID_UNUSED24                            = 0xac,
++	DBG_BLOCK_ID_UNUSED25                            = 0xad,
++	DBG_BLOCK_ID_UNUSED26                            = 0xae,
++	DBG_BLOCK_ID_TA10                                = 0xaf,
++	DBG_BLOCK_ID_TA11                                = 0xb0,
++	DBG_BLOCK_ID_TA12                                = 0xb1,
++	DBG_BLOCK_ID_TA13                                = 0xb2,
++	DBG_BLOCK_ID_TA14                                = 0xb3,
++	DBG_BLOCK_ID_TA15                                = 0xb4,
++	DBG_BLOCK_ID_TA16                                = 0xb5,
++	DBG_BLOCK_ID_TA17                                = 0xb6,
++	DBG_BLOCK_ID_TA18                                = 0xb7,
++	DBG_BLOCK_ID_TA19                                = 0xb8,
++	DBG_BLOCK_ID_TA1A                                = 0xb9,
++	DBG_BLOCK_ID_TA1B                                = 0xba,
++	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
++	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
++	DBG_BLOCK_ID_TD00                                = 0xbf,
++	DBG_BLOCK_ID_TD01                                = 0xc0,
++	DBG_BLOCK_ID_TD02                                = 0xc1,
++	DBG_BLOCK_ID_TD03                                = 0xc2,
++	DBG_BLOCK_ID_TD04                                = 0xc3,
++	DBG_BLOCK_ID_TD05                                = 0xc4,
++	DBG_BLOCK_ID_TD06                                = 0xc5,
++	DBG_BLOCK_ID_TD07                                = 0xc6,
++	DBG_BLOCK_ID_TD08                                = 0xc7,
++	DBG_BLOCK_ID_TD09                                = 0xc8,
++	DBG_BLOCK_ID_TD0A                                = 0xc9,
++	DBG_BLOCK_ID_TD0B                                = 0xca,
++	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
++	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED34                            = 0xce,
++	DBG_BLOCK_ID_TD10                                = 0xcf,
++	DBG_BLOCK_ID_TD11                                = 0xd0,
++	DBG_BLOCK_ID_TD12                                = 0xd1,
++	DBG_BLOCK_ID_TD13                                = 0xd2,
++	DBG_BLOCK_ID_TD14                                = 0xd3,
++	DBG_BLOCK_ID_TD15                                = 0xd4,
++	DBG_BLOCK_ID_TD16                                = 0xd5,
++	DBG_BLOCK_ID_TD17                                = 0xd6,
++	DBG_BLOCK_ID_TD18                                = 0xd7,
++	DBG_BLOCK_ID_TD19                                = 0xd8,
++	DBG_BLOCK_ID_TD1A                                = 0xd9,
++	DBG_BLOCK_ID_TD1B                                = 0xda,
++	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
++	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED38                            = 0xde,
++	DBG_BLOCK_ID_LDS00                               = 0xdf,
++	DBG_BLOCK_ID_LDS01                               = 0xe0,
++	DBG_BLOCK_ID_LDS02                               = 0xe1,
++	DBG_BLOCK_ID_LDS03                               = 0xe2,
++	DBG_BLOCK_ID_LDS04                               = 0xe3,
++	DBG_BLOCK_ID_LDS05                               = 0xe4,
++	DBG_BLOCK_ID_LDS06                               = 0xe5,
++	DBG_BLOCK_ID_LDS07                               = 0xe6,
++	DBG_BLOCK_ID_LDS08                               = 0xe7,
++	DBG_BLOCK_ID_LDS09                               = 0xe8,
++	DBG_BLOCK_ID_LDS0A                               = 0xe9,
++	DBG_BLOCK_ID_LDS0B                               = 0xea,
++	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
++	DBG_BLOCK_ID_UNUSED40                            = 0xec,
++	DBG_BLOCK_ID_UNUSED41                            = 0xed,
++	DBG_BLOCK_ID_UNUSED42                            = 0xee,
++	DBG_BLOCK_ID_LDS10                               = 0xef,
++	DBG_BLOCK_ID_LDS11                               = 0xf0,
++	DBG_BLOCK_ID_LDS12                               = 0xf1,
++	DBG_BLOCK_ID_LDS13                               = 0xf2,
++	DBG_BLOCK_ID_LDS14                               = 0xf3,
++	DBG_BLOCK_ID_LDS15                               = 0xf4,
++	DBG_BLOCK_ID_LDS16                               = 0xf5,
++	DBG_BLOCK_ID_LDS17                               = 0xf6,
++	DBG_BLOCK_ID_LDS18                               = 0xf7,
++	DBG_BLOCK_ID_LDS19                               = 0xf8,
++	DBG_BLOCK_ID_LDS1A                               = 0xf9,
++	DBG_BLOCK_ID_LDS1B                               = 0xfa,
++	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
++	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
++	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
++	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
++} DebugBlockId;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
++	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
++	DBG_BLOCK_ID_PA_BY2                              = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
++	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
++	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
++	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
++	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
++	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
++	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
++	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
++	DBG_BLOCK_ID_CB_BY2                              = 0x24,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
++	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
++	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
++	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
++	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
++	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
++	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
++	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
++	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
++	DBG_BLOCK_ID_TA_BY2                              = 0x48,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
++	DBG_BLOCK_ID_TD_BY2                              = 0x58,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
++	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
++	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
++	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
++	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
++	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
++	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
++	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
++	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
++	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
++	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
++	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
++	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
++	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
++	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
++	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
++	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
++	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
++	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
++	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
++	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
++	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
++	DBG_BLOCK_ID_CB_BY4                              = 0x12,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
++	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
++	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
++	DBG_BLOCK_ID_DB_BY4                              = 0x16,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
++	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
++	DBG_BLOCK_ID_TA_BY4                              = 0x24,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
++	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
++	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
++	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
++	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
++	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
++	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
++	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
++	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
++	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
++	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
++	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
++	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
++	DBG_BLOCK_ID_CB_BY8                              = 0x9,
++	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
++	DBG_BLOCK_ID_DB_BY8                              = 0xb,
++	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
++	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
++	DBG_BLOCK_ID_TA_BY8                              = 0x12,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
++	DBG_BLOCK_ID_TD_BY8                              = 0x16,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
++	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
++	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
++	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
++	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
++	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
++	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
++	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
++	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
++	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
++	DBG_BLOCK_ID_TA_BY16                             = 0x9,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
++	DBG_BLOCK_ID_TD_BY16                             = 0xb,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
++	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
++	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
++} DebugBlockId_BY16;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* GMC_8_2_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h
+new file mode 100644
+index 0000000..c5dd8ec
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h
+@@ -0,0 +1,7850 @@
++/*
++ * GMC_8_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef GMC_8_2_SH_MASK_H
++#define GMC_8_2_SH_MASK_H
++
++#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
++#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
++#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
++#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
++#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
++#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
++#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7
++#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0
++#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
++#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3
++#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70
++#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4
++#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80
++#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7
++#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00
++#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
++#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000
++#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
++#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
++#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
++#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000
++#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
++#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000
++#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf
++#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000
++#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
++#define MC_ARB_FED_CNTL__MODE_MASK 0x3
++#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
++#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
++#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
++#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
++#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
++#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
++#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
++#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
++#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
++#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
++#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
++#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
++#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
++#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
++#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
++#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
++#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
++#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
++#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
++#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
++#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
++#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
++#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
++#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
++#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
++#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
++#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
++#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
++#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
++#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
++#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
++#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
++#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
++#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
++#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
++#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
++#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
++#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
++#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
++#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
++#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
++#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
++#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
++#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
++#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
++#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
++#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
++#define MC_ARB_PERF_CID__CH0_MASK 0xff
++#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
++#define MC_ARB_PERF_CID__CH1_MASK 0xff00
++#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
++#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
++#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
++#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
++#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
++#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7
++#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0
++#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8
++#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3
++#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70
++#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4
++#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80
++#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7
++#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700
++#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8
++#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800
++#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb
++#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000
++#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc
++#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000
++#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf
++#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000
++#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10
++#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000
++#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18
++#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff
++#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0
++#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00
++#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8
++#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000
++#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10
++#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000
++#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18
++#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000
++#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a
++#define MC_ARB_GECC2__ENABLE_MASK 0x1
++#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
++#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
++#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
++#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
++#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
++#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
++#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
++#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
++#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
++#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
++#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
++#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
++#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
++#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
++#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
++#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
++#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
++#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
++#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
++#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
++#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
++#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
++#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
++#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
++#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
++#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
++#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
++#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
++#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
++#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
++#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
++#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
++#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
++#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
++#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
++#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
++#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
++#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
++#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
++#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8
++#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3
++#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10
++#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4
++#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0
++#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5
++#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff
++#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0
++#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00
++#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000
++#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18
++#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
++#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
++#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
++#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
++#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
++#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
++#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
++#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
++#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
++#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
++#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
++#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
++#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
++#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
++#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
++#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
++#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
++#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
++#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
++#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
++#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
++#define MC_ARB_MISC2__GECC_MASK 0x40000
++#define MC_ARB_MISC2__GECC__SHIFT 0x12
++#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
++#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
++#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
++#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
++#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
++#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
++#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
++#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
++#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
++#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
++#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
++#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
++#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
++#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
++#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
++#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
++#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
++#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
++#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
++#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
++#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
++#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
++#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
++#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
++#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
++#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
++#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
++#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
++#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
++#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
++#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
++#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
++#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
++#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
++#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
++#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
++#define MC_ARB_BANKMAP__BANK0_MASK 0xf
++#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
++#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
++#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
++#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
++#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
++#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
++#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
++#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
++#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
++#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
++#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
++#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
++#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
++#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
++#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
++#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
++#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
++#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
++#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
++#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
++#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
++#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
++#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
++#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
++#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
++#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
++#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
++#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
++#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
++#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
++#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
++#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
++#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
++#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
++#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
++#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
++#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
++#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
++#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
++#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
++#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
++#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
++#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
++#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
++#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
++#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
++#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
++#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
++#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
++#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
++#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
++#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
++#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
++#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
++#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
++#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
++#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
++#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
++#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
++#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
++#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
++#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
++#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
++#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
++#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
++#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
++#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
++#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
++#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
++#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
++#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
++#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
++#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
++#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
++#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
++#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
++#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
++#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
++#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
++#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
++#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
++#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
++#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
++#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
++#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
++#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
++#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
++#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
++#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
++#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
++#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
++#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
++#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
++#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
++#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
++#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
++#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
++#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
++#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
++#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
++#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
++#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
++#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
++#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
++#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
++#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
++#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
++#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
++#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
++#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
++#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
++#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
++#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
++#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
++#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
++#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
++#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
++#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
++#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
++#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
++#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
++#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
++#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
++#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
++#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
++#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
++#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
++#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
++#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
++#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
++#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
++#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
++#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
++#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
++#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
++#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
++#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
++#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
++#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
++#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
++#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
++#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
++#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
++#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
++#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
++#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
++#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
++#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
++#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
++#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000
++#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10
++#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000
++#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11
++#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
++#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
++#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
++#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
++#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
++#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
++#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000
++#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18
++#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000
++#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
++#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
++#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
++#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
++#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
++#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
++#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
++#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
++#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
++#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
++#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
++#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
++#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000
++#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19
++#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000
++#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a
++#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
++#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
++#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
++#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
++#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
++#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
++#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
++#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
++#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
++#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
++#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
++#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
++#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
++#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
++#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
++#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
++#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
++#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
++#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
++#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
++#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
++#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
++#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
++#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
++#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
++#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
++#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
++#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
++#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
++#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
++#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
++#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
++#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
++#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1
++#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2
++#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1
++#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4
++#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8
++#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3
++#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10
++#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4
++#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20
++#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5
++#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40
++#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6
++#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80
++#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7
++#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100
++#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8
++#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200
++#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400
++#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000
++#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd
++#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000
++#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe
++#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000
++#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf
++#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000
++#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10
++#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000
++#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11
++#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000
++#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12
++#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000
++#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13
++#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000
++#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14
++#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000
++#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15
++#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000
++#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16
++#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000
++#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17
++#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000
++#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18
++#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000
++#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000
++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b
++#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000
++#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c
++#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000
++#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
++#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000
++#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e
++#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000
++#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f
++#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
++#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
++#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
++#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
++#define MC_ARB_CG__RSV_0_MASK 0xff0000
++#define MC_ARB_CG__RSV_0__SHIFT 0x10
++#define MC_ARB_CG__RSV_1_MASK 0xff000000
++#define MC_ARB_CG__RSV_1__SHIFT 0x18
++#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1
++#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2
++#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1
++#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4
++#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8
++#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3
++#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10
++#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4
++#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20
++#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5
++#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40
++#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6
++#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80
++#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7
++#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100
++#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8
++#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200
++#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9
++#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400
++#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa
++#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800
++#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb
++#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000
++#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc
++#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000
++#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd
++#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000
++#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe
++#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000
++#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf
++#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000
++#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10
++#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000
++#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11
++#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000
++#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12
++#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000
++#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13
++#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000
++#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14
++#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000
++#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15
++#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000
++#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16
++#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000
++#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000
++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19
++#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000
++#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a
++#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000
++#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b
++#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000
++#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c
++#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000
++#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
++#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000
++#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e
++#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000
++#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f
++#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
++#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
++#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
++#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
++#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
++#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
++#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
++#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
++#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
++#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
++#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
++#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
++#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
++#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
++#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
++#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
++#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
++#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
++#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
++#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
++#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
++#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
++#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
++#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
++#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
++#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
++#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
++#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
++#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
++#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
++#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
++#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
++#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
++#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
++#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
++#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
++#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
++#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
++#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
++#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
++#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
++#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
++#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
++#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
++#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
++#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
++#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
++#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
++#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
++#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
++#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
++#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000
++#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18
++#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000
++#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19
++#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
++#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
++#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
++#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
++#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
++#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
++#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
++#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
++#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
++#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
++#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
++#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
++#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
++#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
++#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff
++#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0
++#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00
++#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8
++#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000
++#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10
++#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000
++#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11
++#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000
++#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12
++#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000
++#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13
++#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000
++#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14
++#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000
++#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15
++#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000
++#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16
++#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000
++#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17
++#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000
++#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000
++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000
++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c
++#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
++#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
++#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
++#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
++#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
++#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
++#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
++#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
++#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
++#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
++#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
++#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
++#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
++#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
++#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
++#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
++#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
++#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
++#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
++#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
++#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
++#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
++#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
++#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
++#define MC_CG_CONFIG__INDEX__SHIFT 0x6
++#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
++#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
++#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
++#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
++#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
++#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
++#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
++#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
++#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
++#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
++#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
++#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
++#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
++#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
++#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
++#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
++#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
++#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
++#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
++#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
++#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
++#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
++#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
++#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
++#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
++#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
++#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
++#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000
++#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
++#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_RD_GRP_EXT__TC0_MASK 0xf0
++#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
++#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
++#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
++#define MC_WR_GRP_EXT__TC0_MASK 0xf0
++#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
++#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
++#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
++#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
++#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
++#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
++#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
++#define MC_WR_TC0__ENABLE_MASK 0x1
++#define MC_WR_TC0__ENABLE__SHIFT 0x0
++#define MC_WR_TC0__PRESCALE_MASK 0x6
++#define MC_WR_TC0__PRESCALE__SHIFT 0x1
++#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC0__STALL_MODE_MASK 0x30
++#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC0__MAX_BURST_MASK 0x780
++#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_TC1__ENABLE_MASK 0x1
++#define MC_WR_TC1__ENABLE__SHIFT 0x0
++#define MC_WR_TC1__PRESCALE_MASK 0x6
++#define MC_WR_TC1__PRESCALE__SHIFT 0x1
++#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_TC1__STALL_MODE_MASK 0x30
++#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
++#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_TC1__MAX_BURST_MASK 0x780
++#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
++#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
++#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff
++#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
++#define MC_RD_CB__ENABLE_MASK 0x1
++#define MC_RD_CB__ENABLE__SHIFT 0x0
++#define MC_RD_CB__PRESCALE_MASK 0x6
++#define MC_RD_CB__PRESCALE__SHIFT 0x1
++#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_CB__STALL_MODE_MASK 0x30
++#define MC_RD_CB__STALL_MODE__SHIFT 0x4
++#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_CB__MAX_BURST_MASK 0x780
++#define MC_RD_CB__MAX_BURST__SHIFT 0x7
++#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_DB__ENABLE_MASK 0x1
++#define MC_RD_DB__ENABLE__SHIFT 0x0
++#define MC_RD_DB__PRESCALE_MASK 0x6
++#define MC_RD_DB__PRESCALE__SHIFT 0x1
++#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_DB__STALL_MODE_MASK 0x30
++#define MC_RD_DB__STALL_MODE__SHIFT 0x4
++#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_DB__MAX_BURST_MASK 0x780
++#define MC_RD_DB__MAX_BURST__SHIFT 0x7
++#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC0__ENABLE_MASK 0x1
++#define MC_RD_TC0__ENABLE__SHIFT 0x0
++#define MC_RD_TC0__PRESCALE_MASK 0x6
++#define MC_RD_TC0__PRESCALE__SHIFT 0x1
++#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC0__STALL_MODE_MASK 0x30
++#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC0__MAX_BURST_MASK 0x780
++#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_TC1__ENABLE_MASK 0x1
++#define MC_RD_TC1__ENABLE__SHIFT 0x0
++#define MC_RD_TC1__PRESCALE_MASK 0x6
++#define MC_RD_TC1__PRESCALE__SHIFT 0x1
++#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_TC1__STALL_MODE_MASK 0x30
++#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
++#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_TC1__MAX_BURST_MASK 0x780
++#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
++#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
++#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_RD_HUB__ENABLE_MASK 0x1
++#define MC_RD_HUB__ENABLE__SHIFT 0x0
++#define MC_RD_HUB__PRESCALE_MASK 0x6
++#define MC_RD_HUB__PRESCALE__SHIFT 0x1
++#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_RD_HUB__STALL_MODE_MASK 0x30
++#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
++#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_RD_HUB__MAX_BURST_MASK 0x780
++#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
++#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_CB__ENABLE_MASK 0x1
++#define MC_WR_CB__ENABLE__SHIFT 0x0
++#define MC_WR_CB__PRESCALE_MASK 0x6
++#define MC_WR_CB__PRESCALE__SHIFT 0x1
++#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_CB__STALL_MODE_MASK 0x30
++#define MC_WR_CB__STALL_MODE__SHIFT 0x4
++#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_CB__MAX_BURST_MASK 0x780
++#define MC_WR_CB__MAX_BURST__SHIFT 0x7
++#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_DB__ENABLE_MASK 0x1
++#define MC_WR_DB__ENABLE__SHIFT 0x0
++#define MC_WR_DB__PRESCALE_MASK 0x6
++#define MC_WR_DB__PRESCALE__SHIFT 0x1
++#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_DB__STALL_MODE_MASK 0x30
++#define MC_WR_DB__STALL_MODE__SHIFT 0x4
++#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_DB__MAX_BURST_MASK 0x780
++#define MC_WR_DB__MAX_BURST__SHIFT 0x7
++#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_WR_HUB__ENABLE_MASK 0x1
++#define MC_WR_HUB__ENABLE__SHIFT 0x0
++#define MC_WR_HUB__PRESCALE_MASK 0x6
++#define MC_WR_HUB__PRESCALE__SHIFT 0x1
++#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_WR_HUB__STALL_MODE_MASK 0x30
++#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
++#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
++#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
++#define MC_WR_HUB__MAX_BURST_MASK 0x780
++#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
++#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
++#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
++#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
++#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
++#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
++#define MC_RD_GRP_LCL__CB0_MASK 0xf000
++#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
++#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
++#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
++#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
++#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
++#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
++#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
++#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
++#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
++#define MC_WR_GRP_LCL__CB0_MASK 0xf
++#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
++#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
++#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
++#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
++#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
++#define MC_WR_GRP_LCL__DB0_MASK 0xf000
++#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
++#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
++#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
++#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
++#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
++#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
++#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
++#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
++#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2
++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4
++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8
++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10
++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20
++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40
++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80
++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100
++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200
++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400
++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800
++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000
++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000
++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd
++#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000
++#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe
++#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000
++#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf
++#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000
++#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10
++#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000
++#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11
++#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000
++#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
++#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
++#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
++#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
++#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
++#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
++#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
++#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
++#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100
++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800
++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000
++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe
++#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000
++#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000
++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000
++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11
++#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000
++#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12
++#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000
++#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13
++#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
++#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
++#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
++#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
++#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
++#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
++#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000
++#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
++#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
++#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
++#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
++#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
++#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
++#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000
++#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a
++#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000
++#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
++#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
++#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
++#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
++#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
++#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
++#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
++#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
++#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
++#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
++#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
++#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
++#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000
++#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10
++#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
++#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
++#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
++#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
++#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
++#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
++#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
++#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
++#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
++#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
++#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
++#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
++#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
++#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
++#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
++#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
++#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000
++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
++#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
++#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
++#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
++#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
++#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
++#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
++#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000
++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf
++#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
++#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
++#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80
++#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
++#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
++#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
++#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
++#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
++#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
++#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
++#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1
++#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
++#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
++#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
++#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
++#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
++#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000
++#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19
++#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
++#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
++#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
++#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
++#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
++#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
++#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
++#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
++#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
++#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
++#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
++#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
++#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000
++#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1
++#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0
++#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6
++#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1
++#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30
++#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780
++#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7
++#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000
++#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10
++#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
++#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
++#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1
++#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0
++#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6
++#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1
++#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
++#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
++#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30
++#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6
++#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780
++#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7
++#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800
++#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
++#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
++#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
++#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
++#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
++#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
++#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
++#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
++#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
++#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
++#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
++#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
++#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
++#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
++#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
++#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
++#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
++#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
++#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
++#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
++#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
++#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1
++#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0
++#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6
++#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1
++#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8
++#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3
++#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10
++#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4
++#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20
++#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5
++#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40
++#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6
++#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
++#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
++#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
++#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
++#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
++#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
++#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
++#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
++#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
++#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
++#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
++#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
++#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
++#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
++#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
++#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
++#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
++#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
++#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
++#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
++#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
++#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
++#define MC_RD_GRP_GFX__CP_MASK 0xf
++#define MC_RD_GRP_GFX__CP__SHIFT 0x0
++#define MC_RD_GRP_GFX__SH_MASK 0xf0
++#define MC_RD_GRP_GFX__SH__SHIFT 0x4
++#define MC_RD_GRP_GFX__IA_MASK 0xf00
++#define MC_RD_GRP_GFX__IA__SHIFT 0x8
++#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
++#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
++#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
++#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
++#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
++#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
++#define MC_RD_GRP_GFX__ISP_MASK 0xf000000
++#define MC_RD_GRP_GFX__ISP__SHIFT 0x18
++#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000
++#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c
++#define MC_WR_GRP_GFX__CP_MASK 0xf
++#define MC_WR_GRP_GFX__CP__SHIFT 0x0
++#define MC_WR_GRP_GFX__SH_MASK 0xf0
++#define MC_WR_GRP_GFX__SH__SHIFT 0x4
++#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
++#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
++#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
++#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
++#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
++#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
++#define MC_WR_GRP_GFX__VP8_MASK 0xf00000
++#define MC_WR_GRP_GFX__VP8__SHIFT 0x14
++#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000
++#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18
++#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000
++#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c
++#define MC_RD_GRP_SYS__RLC_MASK 0xf
++#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
++#define MC_RD_GRP_SYS__VMC_MASK 0xf0
++#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
++#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
++#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
++#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
++#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
++#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
++#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
++#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
++#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
++#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000
++#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18
++#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000
++#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c
++#define MC_WR_GRP_SYS__IH_MASK 0xf
++#define MC_WR_GRP_SYS__IH__SHIFT 0x0
++#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
++#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
++#define MC_WR_GRP_SYS__RLC_MASK 0xf00
++#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
++#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000
++#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc
++#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
++#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
++#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
++#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
++#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000
++#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18
++#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000
++#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c
++#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_RD_GRP_OTH__HDP_MASK 0xf00
++#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
++#define MC_RD_GRP_OTH__SEM_MASK 0xf000
++#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
++#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
++#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
++#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
++#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
++#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
++#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
++#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000
++#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c
++#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
++#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
++#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
++#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
++#define MC_WR_GRP_OTH__HDP_MASK 0xf00
++#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
++#define MC_WR_GRP_OTH__SEM_MASK 0xf000
++#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
++#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
++#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
++#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
++#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
++#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
++#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
++#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
++#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
++#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
++#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
++#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
++#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
++#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
++#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
++#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
++#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
++#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
++#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
++#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
++#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
++#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
++#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
++#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
++#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
++#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
++#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
++#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
++#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
++#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff
++#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
++#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
++#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
++#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
++#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
++#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
++#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
++#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
++#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
++#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
++#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0
++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4
++#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000
++#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc
++#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000
++#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
++#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
++#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
++#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
++#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
++#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
++#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
++#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
++#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
++#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
++#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
++#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
++#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
++#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
++#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
++#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
++#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
++#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
++#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
++#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
++#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
++#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
++#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
++#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
++#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
++#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
++#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
++#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
++#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
++#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
++#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
++#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
++#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
++#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
++#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
++#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
++#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
++#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
++#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
++#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
++#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
++#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
++#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
++#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
++#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
++#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
++#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
++#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
++#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
++#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
++#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
++#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
++#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
++#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
++#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
++#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
++#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
++#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
++#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
++#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
++#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
++#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
++#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
++#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
++#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
++#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
++#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
++#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
++#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
++#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
++#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
++#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
++#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
++#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
++#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
++#define MC_XPB_STICKY__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY__BITS__SHIFT 0x0
++#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
++#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
++#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
++#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
++#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
++#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
++#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
++#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
++#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
++#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
++#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
++#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
++#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
++#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
++#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
++#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
++#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
++#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
++#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
++#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
++#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
++#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
++#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
++#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
++#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
++#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
++#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
++#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
++#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
++#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
++#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
++#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
++#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
++#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
++#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
++#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
++#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
++#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
++#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
++#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
++#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
++#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
++#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
++#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
++#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
++#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
++#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
++#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8
++#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3
++#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10
++#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
++#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff
++#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000
++#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
++#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00
++#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
++#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
++#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
++#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff
++#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00
++#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8
++#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000
++#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10
++#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000
++#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18
++#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff
++#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000
++#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18
++#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
++#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
++#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
++#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
++#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
++#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
++#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
++#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
++#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
++#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
++#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
++#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
++#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
++#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
++#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
++#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
++#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
++#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
++#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
++#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
++#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
++#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
++#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
++#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
++#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
++#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
++#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
++#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
++#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
++#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
++#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
++#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
++#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
++#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
++#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
++#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
++#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
++#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
++#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
++#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000
++#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000
++#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14
++#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000
++#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
++#define ATC_ATS_STATUS__BUSY_MASK 0x1
++#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
++#define ATC_ATS_STATUS__CRASHED_MASK 0x2
++#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
++#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff
++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00
++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000
++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff
++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
++#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
++#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff
++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1
++#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
++#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e
++#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
++#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00
++#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9
++#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
++#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
++#define ATC_MISC_CG__ENABLE_MASK 0x40000
++#define ATC_MISC_CG__ENABLE__SHIFT 0x12
++#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
++#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
++#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
++#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
++#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80
++#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7
++#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00
++#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8
++#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000
++#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18
++#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000
++#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19
++#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000
++#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b
++#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000
++#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d
++#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000
++#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e
++#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000
++#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
++#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
++#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
++#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400
++#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800
++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
++#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
++#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
++#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000
++#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13
++#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000
++#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17
++#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000
++#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f
++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1
++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2
++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc
++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000
++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19
++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff
++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff
++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
++#define ATC_L1RD_STATUS__BUSY_MASK 0x1
++#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
++#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
++#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000
++#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11
++#define ATC_L1WR_STATUS__BUSY_MASK 0x1
++#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
++#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
++#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
++#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
++#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
++#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000
++#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
++#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
++#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
++#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
++#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
++#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
++#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
++#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
++#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
++#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
++#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
++#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
++#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
++#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
++#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
++#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
++#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
++#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
++#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
++#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
++#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
++#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
++#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
++#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1
++#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
++#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2
++#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
++#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4
++#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
++#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8
++#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
++#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10
++#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
++#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20
++#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
++#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40
++#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
++#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80
++#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
++#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100
++#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
++#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200
++#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
++#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400
++#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
++#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800
++#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
++#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000
++#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
++#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000
++#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
++#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000
++#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
++#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000
++#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
++#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1
++#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0
++#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f
++#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0
++#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80
++#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7
++#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00
++#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8
++#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000
++#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd
++#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000
++#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe
++#define ATC_L2_STATUS__BUSY_MASK 0x1
++#define ATC_L2_STATUS__BUSY__SHIFT 0x0
++#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe
++#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
++#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7
++#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0
++#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8
++#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
++#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
++#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
++#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
++#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
++#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
++#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
++#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
++#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
++#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
++#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
++#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
++#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
++#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
++#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
++#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
++#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
++#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
++#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
++#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
++#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
++#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
++#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
++#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
++#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
++#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
++#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
++#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
++#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
++#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
++#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
++#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
++#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
++#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
++#define GMCON_DEBUG__GFX_STALL_MASK 0x1
++#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
++#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
++#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
++#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4
++#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2
++#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8
++#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3
++#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0
++#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4
++#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00
++#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8
++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
++#define VM_L2_STATUS__L2_BUSY_MASK 0x1
++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
++#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
++#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000
++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_DEBUG__FLAGS_MASK 0xffffffff
++#define VM_DEBUG__FLAGS__SHIFT 0x0
++#define VM_L2_CG__OFFDLY_MASK 0xfc0
++#define VM_L2_CG__OFFDLY__SHIFT 0x6
++#define VM_L2_CG__ENABLE_MASK 0x40000
++#define VM_L2_CG__ENABLE__SHIFT 0x12
++#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
++#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
++#define VM_L2_CG__OVERRIDE_MASK 0x100000
++#define VM_L2_CG__OVERRIDE__SHIFT 0x14
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x7f
++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f
++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000
++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000
++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000
++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
++#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff
++#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff
++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
++#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000
++#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
++#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8
++#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000
++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000
++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff
++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000
++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f
++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000
++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff
++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1
++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2
++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000
++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff
++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000
++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff
++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
++#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1
++#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
++#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
++#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
++#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
++#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
++#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
++#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
++#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
++#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
++#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
++#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
++#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
++#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
++#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
++#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
++#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
++#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
++#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
++#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
++#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
++#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
++#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
++#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
++#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
++#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e
++#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e
++#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3
++#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0
++#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc
++#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0
++#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6
++#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300
++#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8
++#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00
++#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa
++#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000
++#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000
++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12
++#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000
++#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14
++#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000
++#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16
++#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000
++#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18
++#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000
++#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a
++#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000
++#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c
++#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000
++#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e
++#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1
++#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
++#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7
++#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0
++#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78
++#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3
++#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
++#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7
++#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
++#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
++#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7
++#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0
++#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78
++#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3
++#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
++#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7
++#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
++#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
++#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
++#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
++#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
++#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
++#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
++#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
++#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
++#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000
++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000
++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc
++#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7
++#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0
++#define MC_FUS_DRAM_MODE__DRAMTYPE_MASK 0x38
++#define MC_FUS_DRAM_MODE__DRAMTYPE__SHIFT 0x3
++#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x7fc0
++#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x6
++#define MC_FUS_DRAM_MODE__DDR3LPX32_MASK 0x8000
++#define MC_FUS_DRAM_MODE__DDR3LPX32__SHIFT 0xf
++#define MC_FUS_DRAM_MODE__BANKGROUPSWAP_MASK 0x10000
++#define MC_FUS_DRAM_MODE__BANKGROUPSWAP__SHIFT 0x10
++#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff
++#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0
++#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff
++#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0
++#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff
++#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0
++#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000
++#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000
++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d
++#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff
++#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00
++#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8
++#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000
++#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf
++#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000
++#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000
++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a
++#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3
++#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc
++#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2
++#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30
++#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4
++#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0
++#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6
++#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300
++#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8
++#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00
++#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa
++#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000
++#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc
++#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000
++#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe
++#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000
++#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10
++#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000
++#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12
++#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000
++#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14
++#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000
++#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16
++#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18
++#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000
++#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc
++#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2
++#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30
++#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4
++#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
++#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
++#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP_MASK 0x3
++#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP__SHIFT 0x0
++#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP_MASK 0xc
++#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP__SHIFT 0x2
++#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP_MASK 0x30
++#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP__SHIFT 0x4
++#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP_MASK 0xc0
++#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP__SHIFT 0x6
++#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP_MASK 0x100
++#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP__SHIFT 0x8
++#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP_MASK 0x200
++#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP__SHIFT 0x9
++#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP_MASK 0x400
++#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP__SHIFT 0xa
++#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP_MASK 0x800
++#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP__SHIFT 0xb
++#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY_MASK 0x1f
++#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY__SHIFT 0x0
++#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY_MASK 0x1f00
++#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY__SHIFT 0x8
++#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY_MASK 0x1f0000
++#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY__SHIFT 0x10
++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO_MASK 0x3f
++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO__SHIFT 0x0
++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI_MASK 0x3f00
++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI__SHIFT 0x8
++#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL_MASK 0x8000
++#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL__SHIFT 0xf
++#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH_MASK 0x70000
++#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH__SHIFT 0x10
++#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH_MASK 0x700000
++#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH__SHIFT 0x14
++#define MC_GRUB_FEATURES__WR_COMBINE_OFF_MASK 0x1
++#define MC_GRUB_FEATURES__WR_COMBINE_OFF__SHIFT 0x0
++#define MC_GRUB_FEATURES__SCLK_CG_DISABLE_MASK 0x2
++#define MC_GRUB_FEATURES__SCLK_CG_DISABLE__SHIFT 0x1
++#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE_MASK 0x4
++#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE__SHIFT 0x2
++#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE_MASK 0x8
++#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE__SHIFT 0x3
++#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY_MASK 0x10
++#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY__SHIFT 0x4
++#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE_MASK 0x20
++#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE__SHIFT 0x5
++#define MC_GRUB_FEATURES__RT_BYPASS_OFF_MASK 0x40
++#define MC_GRUB_FEATURES__RT_BYPASS_OFF__SHIFT 0x6
++#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE_MASK 0x80
++#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE__SHIFT 0x7
++#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE_MASK 0x100
++#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE__SHIFT 0x8
++#define MC_GRUB_FEATURES__ARB_STALL_EN_MASK 0x400
++#define MC_GRUB_FEATURES__ARB_STALL_EN__SHIFT 0xa
++#define MC_GRUB_FEATURES__CREDIT_STALL_EN_MASK 0x800
++#define MC_GRUB_FEATURES__CREDIT_STALL_EN__SHIFT 0xb
++#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL_MASK 0x3000
++#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL__SHIFT 0xc
++#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL_MASK 0xc000
++#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL__SHIFT 0xe
++#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL_MASK 0x30000
++#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL__SHIFT 0x10
++#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL_MASK 0xc0000
++#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL__SHIFT 0x12
++#define MC_GRUB_FEATURES__WR_REORDER_OFF_MASK 0x100000
++#define MC_GRUB_FEATURES__WR_REORDER_OFF__SHIFT 0x14
++#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT_MASK 0x3f
++#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT__SHIFT 0x0
++#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE_MASK 0xf00
++#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE__SHIFT 0x8
++#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE_MASK 0xf000
++#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE__SHIFT 0xc
++#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE_MASK 0xf0000
++#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE__SHIFT 0x10
++#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH_MASK 0x1f00000
++#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH__SHIFT 0x14
++#define MC_GRUB_TCB_INDEX__INDEX_MASK 0x7f
++#define MC_GRUB_TCB_INDEX__INDEX__SHIFT 0x0
++#define MC_GRUB_TCB_INDEX__TCB0_WR_EN_MASK 0x100
++#define MC_GRUB_TCB_INDEX__TCB0_WR_EN__SHIFT 0x8
++#define MC_GRUB_TCB_INDEX__TCB1_WR_EN_MASK 0x200
++#define MC_GRUB_TCB_INDEX__TCB1_WR_EN__SHIFT 0x9
++#define MC_GRUB_TCB_INDEX__RD_EN_MASK 0x400
++#define MC_GRUB_TCB_INDEX__RD_EN__SHIFT 0xa
++#define MC_GRUB_TCB_INDEX__TCB_SEL_MASK 0x800
++#define MC_GRUB_TCB_INDEX__TCB_SEL__SHIFT 0xb
++#define MC_GRUB_TCB_DATA_LO__DATA_MASK 0xffffffff
++#define MC_GRUB_TCB_DATA_LO__DATA__SHIFT 0x0
++#define MC_GRUB_TCB_DATA_HI__DATA_MASK 0xffffffff
++#define MC_GRUB_TCB_DATA_HI__DATA__SHIFT 0x0
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000
++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
++#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000
++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000
++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000
++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000
++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000
++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff
++#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff
++#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff
++#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
++#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff
++#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000
++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000
++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10
++
++#endif /* GMC_8_2_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0014-yocto-amd-drm-amdgpu-add-VCE-3-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0014-yocto-amd-drm-amdgpu-add-VCE-3-0-register-headers.patch
new file mode 100644
index 00000000..2c195a07
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0014-yocto-amd-drm-amdgpu-add-VCE-3-0-register-headers.patch
@@ -0,0 +1,3144 @@
+From 894dfbcf57920ea0bbe479241adab3382371f41a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:25:48 -0400
+Subject: drm/amdgpu: add OSS 2.0 register headers
+
+These are register headers for the OSS (OS Services)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h
+new file mode 100644
+index 0000000..34ab258
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h
+@@ -0,0 +1,642 @@
++/*
++ * OSS_2_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_2_0_D_H
++#define OSS_2_0_D_H
++
++#define mmIH_VMID_0_LUT                                                         0xf50
++#define mmIH_VMID_1_LUT                                                         0xf51
++#define mmIH_VMID_2_LUT                                                         0xf52
++#define mmIH_VMID_3_LUT                                                         0xf53
++#define mmIH_VMID_4_LUT                                                         0xf54
++#define mmIH_VMID_5_LUT                                                         0xf55
++#define mmIH_VMID_6_LUT                                                         0xf56
++#define mmIH_VMID_7_LUT                                                         0xf57
++#define mmIH_VMID_8_LUT                                                         0xf58
++#define mmIH_VMID_9_LUT                                                         0xf59
++#define mmIH_VMID_10_LUT                                                        0xf5a
++#define mmIH_VMID_11_LUT                                                        0xf5b
++#define mmIH_VMID_12_LUT                                                        0xf5c
++#define mmIH_VMID_13_LUT                                                        0xf5d
++#define mmIH_VMID_14_LUT                                                        0xf5e
++#define mmIH_VMID_15_LUT                                                        0xf5f
++#define mmIH_RB_CNTL                                                            0xf80
++#define mmIH_RB_BASE                                                            0xf81
++#define mmIH_RB_RPTR                                                            0xf82
++#define mmIH_RB_WPTR                                                            0xf83
++#define mmIH_RB_WPTR_ADDR_HI                                                    0xf84
++#define mmIH_RB_WPTR_ADDR_LO                                                    0xf85
++#define mmIH_CNTL                                                               0xf86
++#define mmIH_LEVEL_STATUS                                                       0xf87
++#define mmIH_STATUS                                                             0xf88
++#define mmIH_PERFMON_CNTL                                                       0xf89
++#define mmIH_PERFCOUNTER0_RESULT                                                0xf8a
++#define mmIH_PERFCOUNTER1_RESULT                                                0xf8b
++#define mmIH_ADVFAULT_CNTL                                                      0xf8c
++#define mmSEM_MCIF_CONFIG                                                       0xf90
++#define mmSDMA_CONFIG                                                           0xf91
++#define mmSDMA1_CONFIG                                                          0xf92
++#define mmUVD_CONFIG                                                            0xf93
++#define mmVCE_CONFIG                                                            0xf94
++#define mmACP_CONFIG                                                            0xf95
++#define mmCPG_CONFIG                                                            0xf96
++#define mmCPC1_CONFIG                                                           0xf97
++#define mmCPC2_CONFIG                                                           0xf98
++#define mmSEM_STATUS                                                            0xf99
++#define mmSEM_EDC_CONFIG                                                        0xf9a
++#define mmSEM_MAILBOX_CLIENTCONFIG                                              0xf9b
++#define mmSEM_MAILBOX                                                           0xf9c
++#define mmSEM_MAILBOX_CONTROL                                                   0xf9d
++#define mmSEM_CHICKEN_BITS                                                      0xf9e
++#define mmSRBM_CNTL                                                             0x390
++#define mmSRBM_GFX_CNTL                                                         0x391
++#define mmSRBM_STATUS2                                                          0x393
++#define mmSRBM_STATUS                                                           0x394
++#define mmSRBM_CAM_INDEX                                                        0x396
++#define mmSRBM_CAM_DATA                                                         0x397
++#define mmSRBM_SOFT_RESET                                                       0x398
++#define mmSRBM_DEBUG_CNTL                                                       0x399
++#define mmSRBM_DEBUG_DATA                                                       0x39a
++#define mmSRBM_CHIP_REVISION                                                    0x39b
++#define mmCC_SYS_RB_REDUNDANCY                                                  0x39f
++#define mmCC_SYS_RB_BACKEND_DISABLE                                             0x3a0
++#define mmGC_USER_SYS_RB_BACKEND_DISABLE                                        0x3a1
++#define mmSRBM_MC_CLKEN_CNTL                                                    0x3b3
++#define mmSRBM_SYS_CLKEN_CNTL                                                   0x3b4
++#define mmSRBM_VCE_CLKEN_CNTL                                                   0x3b5
++#define mmSRBM_UVD_CLKEN_CNTL                                                   0x3b6
++#define mmSRBM_SDMA_CLKEN_CNTL                                                  0x3b7
++#define mmSRBM_SAM_CLKEN_CNTL                                                   0x3b8
++#define mmSRBM_DEBUG                                                            0x3a4
++#define mmSRBM_DEBUG_SNAPSHOT                                                   0x3a5
++#define mmSRBM_READ_ERROR                                                       0x3a6
++#define mmSRBM_INT_CNTL                                                         0x3a8
++#define mmSRBM_INT_STATUS                                                       0x3a9
++#define mmSRBM_INT_ACK                                                          0x3aa
++#define mmSRBM_PERFMON_CNTL                                                     0x700
++#define mmSRBM_PERFCOUNTER0_SELECT                                              0x701
++#define mmSRBM_PERFCOUNTER1_SELECT                                              0x702
++#define mmSRBM_PERFCOUNTER0_LO                                                  0x703
++#define mmSRBM_PERFCOUNTER0_HI                                                  0x704
++#define mmSRBM_PERFCOUNTER1_LO                                                  0x705
++#define mmSRBM_PERFCOUNTER1_HI                                                  0x706
++#define mmCC_DRM_ID_STRAPS                                                      0x1559
++#define mmCGTT_DRM_CLK_CTRL0                                                    0x1579
++#define ixDH_TEST                                                               0x0
++#define ixKHFS0                                                                 0x4
++#define ixKHFS1                                                                 0x8
++#define ixKHFS2                                                                 0xc
++#define ixKHFS3                                                                 0x10
++#define ixKSESSION0                                                             0x14
++#define ixKSESSION1                                                             0x18
++#define ixKSESSION2                                                             0x1c
++#define ixKSESSION3                                                             0x20
++#define ixKSIG0                                                                 0x24
++#define ixKSIG1                                                                 0x28
++#define ixKSIG2                                                                 0x2c
++#define ixKSIG3                                                                 0x30
++#define ixEXP0                                                                  0x34
++#define ixEXP1                                                                  0x38
++#define ixEXP2                                                                  0x3c
++#define ixEXP3                                                                  0x40
++#define ixEXP4                                                                  0x44
++#define ixEXP5                                                                  0x48
++#define ixEXP6                                                                  0x4c
++#define ixEXP7                                                                  0x50
++#define ixLX0                                                                   0x54
++#define ixLX1                                                                   0x58
++#define ixLX2                                                                   0x5c
++#define ixLX3                                                                   0x60
++#define ixCLIENT2_K0                                                            0x1b4
++#define ixCLIENT2_K1                                                            0x1b8
++#define ixCLIENT2_K2                                                            0x1bc
++#define ixCLIENT2_K3                                                            0x1c0
++#define ixCLIENT2_CK0                                                           0x1c4
++#define ixCLIENT2_CK1                                                           0x1c8
++#define ixCLIENT2_CK2                                                           0x1cc
++#define ixCLIENT2_CK3                                                           0x1d0
++#define ixCLIENT2_CD0                                                           0x1d4
++#define ixCLIENT2_CD1                                                           0x1d8
++#define ixCLIENT2_CD2                                                           0x1dc
++#define ixCLIENT2_CD3                                                           0x1e0
++#define ixCLIENT2_BM                                                            0x1e4
++#define ixCLIENT2_OFFSET                                                        0x1e8
++#define ixCLIENT2_STATUS                                                        0x1ec
++#define ixCLIENT0_K0                                                            0x1f0
++#define ixCLIENT0_K1                                                            0x1f4
++#define ixCLIENT0_K2                                                            0x1f8
++#define ixCLIENT0_K3                                                            0x1fc
++#define ixCLIENT0_CK0                                                           0x200
++#define ixCLIENT0_CK1                                                           0x204
++#define ixCLIENT0_CK2                                                           0x208
++#define ixCLIENT0_CK3                                                           0x20c
++#define ixCLIENT0_CD0                                                           0x210
++#define ixCLIENT0_CD1                                                           0x214
++#define ixCLIENT0_CD2                                                           0x218
++#define ixCLIENT0_CD3                                                           0x21c
++#define ixCLIENT0_BM                                                            0x220
++#define ixCLIENT0_OFFSET                                                        0x224
++#define ixCLIENT0_STATUS                                                        0x228
++#define ixCLIENT1_K0                                                            0x22c
++#define ixCLIENT1_K1                                                            0x230
++#define ixCLIENT1_K2                                                            0x234
++#define ixCLIENT1_K3                                                            0x238
++#define ixCLIENT1_CK0                                                           0x23c
++#define ixCLIENT1_CK1                                                           0x240
++#define ixCLIENT1_CK2                                                           0x244
++#define ixCLIENT1_CK3                                                           0x248
++#define ixCLIENT1_CD0                                                           0x24c
++#define ixCLIENT1_CD1                                                           0x250
++#define ixCLIENT1_CD2                                                           0x254
++#define ixCLIENT1_CD3                                                           0x258
++#define ixCLIENT1_BM                                                            0x25c
++#define ixCLIENT1_OFFSET                                                        0x260
++#define ixCLIENT1_PORT_STATUS                                                   0x264
++#define ixKEFUSE0                                                               0x268
++#define ixKEFUSE1                                                               0x26c
++#define ixKEFUSE2                                                               0x270
++#define ixKEFUSE3                                                               0x274
++#define ixHFS_SEED0                                                             0x278
++#define ixHFS_SEED1                                                             0x27c
++#define ixHFS_SEED2                                                             0x280
++#define ixHFS_SEED3                                                             0x284
++#define ixRINGOSC_MASK                                                          0x288
++#define ixCLIENT0_OFFSET_HI                                                     0x290
++#define ixCLIENT1_OFFSET_HI                                                     0x294
++#define ixCLIENT2_OFFSET_HI                                                     0x298
++#define ixSPU_PORT_STATUS                                                       0x29c
++#define ixCLIENT3_OFFSET_HI                                                     0x2a0
++#define ixCLIENT3_K0                                                            0x2a4
++#define ixCLIENT3_K1                                                            0x2a8
++#define ixCLIENT3_K2                                                            0x2ac
++#define ixCLIENT3_K3                                                            0x2b0
++#define ixCLIENT3_CK0                                                           0x2b4
++#define ixCLIENT3_CK1                                                           0x2b8
++#define ixCLIENT3_CK2                                                           0x2bc
++#define ixCLIENT3_CK3                                                           0x2c0
++#define ixCLIENT3_CD0                                                           0x2c4
++#define ixCLIENT3_CD1                                                           0x2c8
++#define ixCLIENT3_CD2                                                           0x2cc
++#define ixCLIENT3_CD3                                                           0x2d0
++#define ixCLIENT3_BM                                                            0x2d4
++#define ixCLIENT3_OFFSET                                                        0x2d8
++#define ixCLIENT3_STATUS                                                        0x2dc
++#define mmDC_TEST_DEBUG_INDEX                                                   0x157c
++#define mmDC_TEST_DEBUG_DATA                                                    0x157d
++#define mmXDMA_SLV_CNTL                                                         0x460
++#define mmXDMA_SLV_MEM_CLIENT_CONFIG                                            0x461
++#define mmXDMA_SLV_SLS_PITCH                                                    0x462
++#define mmXDMA_SLV_READ_URGENT_CNTL                                             0x463
++#define mmXDMA_SLV_WRITE_URGENT_CNTL                                            0x464
++#define mmXDMA_SLV_WB_RATE_CNTL                                                 0x465
++#define mmXDMA_SLV_READ_LATENCY_MINMAX                                          0x466
++#define mmXDMA_SLV_READ_LATENCY_AVE                                             0x467
++#define mmXDMA_SLV_PCIE_NACK_STATUS                                             0x468
++#define mmXDMA_SLV_MEM_NACK_STATUS                                              0x469
++#define mmXDMA_SLV_RDRET_BUF_STATUS                                             0x46a
++#define mmXDMA_SLV_READ_LATENCY_TIMER                                           0x46b
++#define mmXDMA_SLV_FLIP_PENDING                                                 0x46c
++#define mmSDMA0_UCODE_ADDR                                                      0x3400
++#define mmSDMA0_UCODE_DATA                                                      0x3401
++#define mmSDMA0_POWER_CNTL                                                      0x3402
++#define mmSDMA0_CLK_CTRL                                                        0x3403
++#define mmSDMA0_CNTL                                                            0x3404
++#define mmSDMA0_CHICKEN_BITS                                                    0x3405
++#define mmSDMA0_TILING_CONFIG                                                   0x3406
++#define mmSDMA0_HASH                                                            0x3407
++#define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL                                       0x3408
++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3409
++#define mmSDMA0_RB_RPTR_FETCH                                                   0x340a
++#define mmSDMA0_IB_OFFSET_FETCH                                                 0x340b
++#define mmSDMA0_PROGRAM                                                         0x340c
++#define mmSDMA0_STATUS_REG                                                      0x340d
++#define mmSDMA0_STATUS1_REG                                                     0x340e
++#define mmSDMA0_PERFMON_CNTL                                                    0x340f
++#define mmSDMA0_PERFCOUNTER0_RESULT                                             0x3410
++#define mmSDMA0_PERFCOUNTER1_RESULT                                             0x3411
++#define mmSDMA0_F32_CNTL                                                        0x3412
++#define mmSDMA0_FREEZE                                                          0x3413
++#define mmSDMA0_PHASE0_QUANTUM                                                  0x3414
++#define mmSDMA0_PHASE1_QUANTUM                                                  0x3415
++#define mmSDMA_POWER_GATING                                                     0x3416
++#define mmSDMA_PGFSM_CONFIG                                                     0x3417
++#define mmSDMA_PGFSM_WRITE                                                      0x3418
++#define mmSDMA_PGFSM_READ                                                       0x3419
++#define mmSDMA0_EDC_CONFIG                                                      0x341a
++#define mmSDMA0_GFX_RB_CNTL                                                     0x3480
++#define mmSDMA0_GFX_RB_BASE                                                     0x3481
++#define mmSDMA0_GFX_RB_BASE_HI                                                  0x3482
++#define mmSDMA0_GFX_RB_RPTR                                                     0x3483
++#define mmSDMA0_GFX_RB_WPTR                                                     0x3484
++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                           0x3485
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3486
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3487
++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                             0x3488
++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                             0x3489
++#define mmSDMA0_GFX_IB_CNTL                                                     0x348a
++#define mmSDMA0_GFX_IB_RPTR                                                     0x348b
++#define mmSDMA0_GFX_IB_OFFSET                                                   0x348c
++#define mmSDMA0_GFX_IB_BASE_LO                                                  0x348d
++#define mmSDMA0_GFX_IB_BASE_HI                                                  0x348e
++#define mmSDMA0_GFX_IB_SIZE                                                     0x348f
++#define mmSDMA0_GFX_SKIP_CNTL                                                   0x3490
++#define mmSDMA0_GFX_CONTEXT_STATUS                                              0x3491
++#define mmSDMA0_GFX_CONTEXT_CNTL                                                0x3493
++#define mmSDMA0_GFX_VIRTUAL_ADDR                                                0x34a7
++#define mmSDMA0_GFX_APE1_CNTL                                                   0x34a8
++#define mmSDMA0_GFX_WATERMARK                                                   0x34aa
++#define mmSDMA0_RLC0_RB_CNTL                                                    0x3500
++#define mmSDMA0_RLC0_RB_BASE                                                    0x3501
++#define mmSDMA0_RLC0_RB_BASE_HI                                                 0x3502
++#define mmSDMA0_RLC0_RB_RPTR                                                    0x3503
++#define mmSDMA0_RLC0_RB_WPTR                                                    0x3504
++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                          0x3505
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3506
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3507
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                            0x3508
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                            0x3509
++#define mmSDMA0_RLC0_IB_CNTL                                                    0x350a
++#define mmSDMA0_RLC0_IB_RPTR                                                    0x350b
++#define mmSDMA0_RLC0_IB_OFFSET                                                  0x350c
++#define mmSDMA0_RLC0_IB_BASE_LO                                                 0x350d
++#define mmSDMA0_RLC0_IB_BASE_HI                                                 0x350e
++#define mmSDMA0_RLC0_IB_SIZE                                                    0x350f
++#define mmSDMA0_RLC0_SKIP_CNTL                                                  0x3510
++#define mmSDMA0_RLC0_CONTEXT_STATUS                                             0x3511
++#define mmSDMA0_RLC0_DOORBELL                                                   0x3512
++#define mmSDMA0_RLC0_VIRTUAL_ADDR                                               0x3527
++#define mmSDMA0_RLC0_APE1_CNTL                                                  0x3528
++#define mmSDMA0_RLC0_DOORBELL_LOG                                               0x3529
++#define mmSDMA0_RLC0_WATERMARK                                                  0x352a
++#define mmSDMA0_RLC1_RB_CNTL                                                    0x3580
++#define mmSDMA0_RLC1_RB_BASE                                                    0x3581
++#define mmSDMA0_RLC1_RB_BASE_HI                                                 0x3582
++#define mmSDMA0_RLC1_RB_RPTR                                                    0x3583
++#define mmSDMA0_RLC1_RB_WPTR                                                    0x3584
++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                          0x3585
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3586
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3587
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                            0x3588
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                            0x3589
++#define mmSDMA0_RLC1_IB_CNTL                                                    0x358a
++#define mmSDMA0_RLC1_IB_RPTR                                                    0x358b
++#define mmSDMA0_RLC1_IB_OFFSET                                                  0x358c
++#define mmSDMA0_RLC1_IB_BASE_LO                                                 0x358d
++#define mmSDMA0_RLC1_IB_BASE_HI                                                 0x358e
++#define mmSDMA0_RLC1_IB_SIZE                                                    0x358f
++#define mmSDMA0_RLC1_SKIP_CNTL                                                  0x3590
++#define mmSDMA0_RLC1_CONTEXT_STATUS                                             0x3591
++#define mmSDMA0_RLC1_DOORBELL                                                   0x3592
++#define mmSDMA0_RLC1_VIRTUAL_ADDR                                               0x35a7
++#define mmSDMA0_RLC1_APE1_CNTL                                                  0x35a8
++#define mmSDMA0_RLC1_DOORBELL_LOG                                               0x35a9
++#define mmSDMA0_RLC1_WATERMARK                                                  0x35aa
++#define mmSDMA1_UCODE_ADDR                                                      0x3600
++#define mmSDMA1_UCODE_DATA                                                      0x3601
++#define mmSDMA1_POWER_CNTL                                                      0x3602
++#define mmSDMA1_CLK_CTRL                                                        0x3603
++#define mmSDMA1_CNTL                                                            0x3604
++#define mmSDMA1_CHICKEN_BITS                                                    0x3605
++#define mmSDMA1_TILING_CONFIG                                                   0x3606
++#define mmSDMA1_HASH                                                            0x3607
++#define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL                                       0x3608
++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3609
++#define mmSDMA1_RB_RPTR_FETCH                                                   0x360a
++#define mmSDMA1_IB_OFFSET_FETCH                                                 0x360b
++#define mmSDMA1_PROGRAM                                                         0x360c
++#define mmSDMA1_STATUS_REG                                                      0x360d
++#define mmSDMA1_STATUS1_REG                                                     0x360e
++#define mmSDMA1_PERFMON_CNTL                                                    0x360f
++#define mmSDMA1_PERFCOUNTER0_RESULT                                             0x3610
++#define mmSDMA1_PERFCOUNTER1_RESULT                                             0x3611
++#define mmSDMA1_F32_CNTL                                                        0x3612
++#define mmSDMA1_FREEZE                                                          0x3613
++#define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
++#define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
++#define mmSDMA1_EDC_CONFIG                                                      0x361a
++#define mmSDMA1_GFX_RB_CNTL                                                     0x3680
++#define mmSDMA1_GFX_RB_BASE                                                     0x3681
++#define mmSDMA1_GFX_RB_BASE_HI                                                  0x3682
++#define mmSDMA1_GFX_RB_RPTR                                                     0x3683
++#define mmSDMA1_GFX_RB_WPTR                                                     0x3684
++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3686
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3687
++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                             0x3688
++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                             0x3689
++#define mmSDMA1_GFX_IB_CNTL                                                     0x368a
++#define mmSDMA1_GFX_IB_RPTR                                                     0x368b
++#define mmSDMA1_GFX_IB_OFFSET                                                   0x368c
++#define mmSDMA1_GFX_IB_BASE_LO                                                  0x368d
++#define mmSDMA1_GFX_IB_BASE_HI                                                  0x368e
++#define mmSDMA1_GFX_IB_SIZE                                                     0x368f
++#define mmSDMA1_GFX_SKIP_CNTL                                                   0x3690
++#define mmSDMA1_GFX_CONTEXT_STATUS                                              0x3691
++#define mmSDMA1_GFX_CONTEXT_CNTL                                                0x3693
++#define mmSDMA1_GFX_VIRTUAL_ADDR                                                0x36a7
++#define mmSDMA1_GFX_APE1_CNTL                                                   0x36a8
++#define mmSDMA1_GFX_WATERMARK                                                   0x36aa
++#define mmSDMA1_RLC0_RB_CNTL                                                    0x3700
++#define mmSDMA1_RLC0_RB_BASE                                                    0x3701
++#define mmSDMA1_RLC0_RB_BASE_HI                                                 0x3702
++#define mmSDMA1_RLC0_RB_RPTR                                                    0x3703
++#define mmSDMA1_RLC0_RB_WPTR                                                    0x3704
++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                          0x3705
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3706
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3707
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                            0x3708
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                            0x3709
++#define mmSDMA1_RLC0_IB_CNTL                                                    0x370a
++#define mmSDMA1_RLC0_IB_RPTR                                                    0x370b
++#define mmSDMA1_RLC0_IB_OFFSET                                                  0x370c
++#define mmSDMA1_RLC0_IB_BASE_LO                                                 0x370d
++#define mmSDMA1_RLC0_IB_BASE_HI                                                 0x370e
++#define mmSDMA1_RLC0_IB_SIZE                                                    0x370f
++#define mmSDMA1_RLC0_SKIP_CNTL                                                  0x3710
++#define mmSDMA1_RLC0_CONTEXT_STATUS                                             0x3711
++#define mmSDMA1_RLC0_DOORBELL                                                   0x3712
++#define mmSDMA1_RLC0_VIRTUAL_ADDR                                               0x3727
++#define mmSDMA1_RLC0_APE1_CNTL                                                  0x3728
++#define mmSDMA1_RLC0_DOORBELL_LOG                                               0x3729
++#define mmSDMA1_RLC0_WATERMARK                                                  0x372a
++#define mmSDMA1_RLC1_RB_CNTL                                                    0x3780
++#define mmSDMA1_RLC1_RB_BASE                                                    0x3781
++#define mmSDMA1_RLC1_RB_BASE_HI                                                 0x3782
++#define mmSDMA1_RLC1_RB_RPTR                                                    0x3783
++#define mmSDMA1_RLC1_RB_WPTR                                                    0x3784
++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                          0x3785
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3786
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3787
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                            0x3788
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                            0x3789
++#define mmSDMA1_RLC1_IB_CNTL                                                    0x378a
++#define mmSDMA1_RLC1_IB_RPTR                                                    0x378b
++#define mmSDMA1_RLC1_IB_OFFSET                                                  0x378c
++#define mmSDMA1_RLC1_IB_BASE_LO                                                 0x378d
++#define mmSDMA1_RLC1_IB_BASE_HI                                                 0x378e
++#define mmSDMA1_RLC1_IB_SIZE                                                    0x378f
++#define mmSDMA1_RLC1_SKIP_CNTL                                                  0x3790
++#define mmSDMA1_RLC1_CONTEXT_STATUS                                             0x3791
++#define mmSDMA1_RLC1_DOORBELL                                                   0x3792
++#define mmSDMA1_RLC1_VIRTUAL_ADDR                                               0x37a7
++#define mmSDMA1_RLC1_APE1_CNTL                                                  0x37a8
++#define mmSDMA1_RLC1_DOORBELL_LOG                                               0x37a9
++#define mmSDMA1_RLC1_WATERMARK                                                  0x37aa
++#define mmXDMA_SLV_CHANNEL_CNTL                                                 0x470
++#define mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL                                   0x470
++#define mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL                                   0x478
++#define mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL                                   0x480
++#define mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL                                   0x488
++#define mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL                                   0x490
++#define mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL                                   0x498
++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS                                           0x471
++#define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS                             0x471
++#define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS                             0x479
++#define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS                             0x481
++#define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS                             0x489
++#define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS                             0x491
++#define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS                             0x499
++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                                      0x472
++#define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                        0x472
++#define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                        0x47a
++#define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                        0x482
++#define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                        0x48a
++#define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                        0x492
++#define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                        0x49a
++#define mmXDMA_MSTR_PIPE_CNTL                                                   0x400
++#define mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL                                        0x400
++#define mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL                                        0x410
++#define mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL                                        0x420
++#define mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL                                        0x430
++#define mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL                                        0x440
++#define mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL                                        0x450
++#define mmXDMA_MSTR_READ_COMMAND                                                0x401
++#define mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND                                     0x401
++#define mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND                                     0x411
++#define mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND                                     0x421
++#define mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND                                     0x431
++#define mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND                                     0x441
++#define mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND                                     0x451
++#define mmXDMA_MSTR_CHANNEL_DIM                                                 0x402
++#define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM                                      0x402
++#define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM                                      0x412
++#define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM                                      0x422
++#define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM                                      0x432
++#define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM                                      0x442
++#define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM                                      0x452
++#define mmXDMA_MSTR_HEIGHT                                                      0x403
++#define mmMDMA_PIPE0_XDMA_MSTR_HEIGHT                                           0x403
++#define mmMDMA_PIPE1_XDMA_MSTR_HEIGHT                                           0x413
++#define mmMDMA_PIPE2_XDMA_MSTR_HEIGHT                                           0x423
++#define mmMDMA_PIPE3_XDMA_MSTR_HEIGHT                                           0x433
++#define mmMDMA_PIPE4_XDMA_MSTR_HEIGHT                                           0x443
++#define mmMDMA_PIPE5_XDMA_MSTR_HEIGHT                                           0x453
++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE                                         0x404
++#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE                              0x404
++#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE                              0x414
++#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE                              0x424
++#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE                              0x434
++#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE                              0x444
++#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE                              0x454
++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                                    0x405
++#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                         0x405
++#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                         0x415
++#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                         0x425
++#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                         0x435
++#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                         0x445
++#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                         0x455
++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS                                          0x406
++#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS                               0x406
++#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS                               0x416
++#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS                               0x426
++#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS                               0x436
++#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS                               0x446
++#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS                               0x456
++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                                     0x407
++#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                          0x407
++#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                          0x417
++#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                          0x427
++#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                          0x437
++#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                          0x447
++#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                          0x457
++#define mmXDMA_MSTR_CACHE_BASE_ADDR                                             0x408
++#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR                                  0x408
++#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR                                  0x418
++#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR                                  0x428
++#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR                                  0x438
++#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR                                  0x448
++#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR                                  0x458
++#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH                                        0x409
++#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                             0x409
++#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                             0x419
++#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                             0x429
++#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                             0x439
++#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                             0x449
++#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                             0x459
++#define mmXDMA_MSTR_CACHE_PITCH                                                 0x40a
++#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH                                      0x40a
++#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH                                      0x41a
++#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH                                      0x42a
++#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH                                      0x43a
++#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH                                      0x44a
++#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH                                      0x45a
++#define mmXDMA_MSTR_CHANNEL_START                                               0x40b
++#define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START                                    0x40b
++#define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START                                    0x41b
++#define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START                                    0x42b
++#define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START                                    0x43b
++#define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START                                    0x44b
++#define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START                                    0x45b
++#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL                                           0x40c
++#define mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL                                0x40c
++#define mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL                                0x41c
++#define mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL                                0x42c
++#define mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL                                0x43c
++#define mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL                                0x44c
++#define mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL                                0x45c
++#define mmXDMA_MSTR_MEM_UNDERFLOW_CNTL                                          0x40d
++#define mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL                               0x40d
++#define mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL                               0x41d
++#define mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL                               0x42d
++#define mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL                               0x43d
++#define mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL                               0x44d
++#define mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL                               0x45d
++#define mmXDMA_MSTR_PERFMEAS_STATUS                                             0x40e
++#define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS                                  0x40e
++#define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS                                  0x41e
++#define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS                                  0x42e
++#define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS                                  0x43e
++#define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS                                  0x44e
++#define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS                                  0x45e
++#define mmXDMA_MSTR_PERFMEAS_CNTL                                               0x40f
++#define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL                                    0x40f
++#define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL                                    0x41f
++#define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL                                    0x42f
++#define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL                                    0x43f
++#define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL                                    0x44f
++#define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL                                    0x45f
++#define mmXDMA_MSTR_CNTL                                                        0x3ec
++#define mmXDMA_MSTR_STATUS                                                      0x3ed
++#define mmXDMA_MSTR_MEM_CLIENT_CONFIG                                           0x3ee
++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR                                     0x3ef
++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH                                0x3f0
++#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH                                         0x3f1
++#define mmXDMA_MSTR_CMD_URGENT_CNTL                                             0x3f2
++#define mmXDMA_MSTR_MEM_URGENT_CNTL                                             0x3f3
++#define mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG                                        0x3f4
++#define mmXDMA_MSTR_PCIE_NACK_STATUS                                            0x3f5
++#define mmXDMA_MSTR_MEM_NACK_STATUS                                             0x3f6
++#define mmXDMA_MSTR_VSYNC_GSL_CHECK                                             0x3f7
++#define mmHDP_HOST_PATH_CNTL                                                    0xb00
++#define mmHDP_NONSURFACE_BASE                                                   0xb01
++#define mmHDP_NONSURFACE_INFO                                                   0xb02
++#define mmHDP_NONSURFACE_SIZE                                                   0xb03
++#define mmHDP_NONSURF_FLAGS                                                     0xbc9
++#define mmHDP_NONSURF_FLAGS_CLR                                                 0xbca
++#define mmHDP_SW_SEMAPHORE                                                      0xbcb
++#define mmHDP_DEBUG0                                                            0xbcc
++#define mmHDP_DEBUG1                                                            0xbcd
++#define mmHDP_LAST_SURFACE_HIT                                                  0xbce
++#define mmHDP_TILING_CONFIG                                                     0xbcf
++#define mmHDP_SC_MULTI_CHIP_CNTL                                                0xbd0
++#define mmHDP_OUTSTANDING_REQ                                                   0xbd1
++#define mmHDP_ADDR_CONFIG                                                       0xbd2
++#define mmHDP_MISC_CNTL                                                         0xbd3
++#define mmHDP_MEM_POWER_LS                                                      0xbd4
++#define mmHDP_NONSURFACE_PREFETCH                                               0xbd5
++#define mmHDP_MEMIO_CNTL                                                        0xbf6
++#define mmHDP_MEMIO_ADDR                                                        0xbf7
++#define mmHDP_MEMIO_STATUS                                                      0xbf8
++#define mmHDP_MEMIO_WR_DATA                                                     0xbf9
++#define mmHDP_MEMIO_RD_DATA                                                     0xbfa
++#define mmHDP_XDP_DIRECT2HDP_FIRST                                              0xc00
++#define mmHDP_XDP_D2H_FLUSH                                                     0xc01
++#define mmHDP_XDP_D2H_BAR_UPDATE                                                0xc02
++#define mmHDP_XDP_D2H_RSVD_3                                                    0xc03
++#define mmHDP_XDP_D2H_RSVD_4                                                    0xc04
++#define mmHDP_XDP_D2H_RSVD_5                                                    0xc05
++#define mmHDP_XDP_D2H_RSVD_6                                                    0xc06
++#define mmHDP_XDP_D2H_RSVD_7                                                    0xc07
++#define mmHDP_XDP_D2H_RSVD_8                                                    0xc08
++#define mmHDP_XDP_D2H_RSVD_9                                                    0xc09
++#define mmHDP_XDP_D2H_RSVD_10                                                   0xc0a
++#define mmHDP_XDP_D2H_RSVD_11                                                   0xc0b
++#define mmHDP_XDP_D2H_RSVD_12                                                   0xc0c
++#define mmHDP_XDP_D2H_RSVD_13                                                   0xc0d
++#define mmHDP_XDP_D2H_RSVD_14                                                   0xc0e
++#define mmHDP_XDP_D2H_RSVD_15                                                   0xc0f
++#define mmHDP_XDP_D2H_RSVD_16                                                   0xc10
++#define mmHDP_XDP_D2H_RSVD_17                                                   0xc11
++#define mmHDP_XDP_D2H_RSVD_18                                                   0xc12
++#define mmHDP_XDP_D2H_RSVD_19                                                   0xc13
++#define mmHDP_XDP_D2H_RSVD_20                                                   0xc14
++#define mmHDP_XDP_D2H_RSVD_21                                                   0xc15
++#define mmHDP_XDP_D2H_RSVD_22                                                   0xc16
++#define mmHDP_XDP_D2H_RSVD_23                                                   0xc17
++#define mmHDP_XDP_D2H_RSVD_24                                                   0xc18
++#define mmHDP_XDP_D2H_RSVD_25                                                   0xc19
++#define mmHDP_XDP_D2H_RSVD_26                                                   0xc1a
++#define mmHDP_XDP_D2H_RSVD_27                                                   0xc1b
++#define mmHDP_XDP_D2H_RSVD_28                                                   0xc1c
++#define mmHDP_XDP_D2H_RSVD_29                                                   0xc1d
++#define mmHDP_XDP_D2H_RSVD_30                                                   0xc1e
++#define mmHDP_XDP_D2H_RSVD_31                                                   0xc1f
++#define mmHDP_XDP_D2H_RSVD_32                                                   0xc20
++#define mmHDP_XDP_D2H_RSVD_33                                                   0xc21
++#define mmHDP_XDP_D2H_RSVD_34                                                   0xc22
++#define mmHDP_XDP_DIRECT2HDP_LAST                                               0xc23
++#define mmHDP_XDP_P2P_BAR_CFG                                                   0xc24
++#define mmHDP_XDP_P2P_MBX_OFFSET                                                0xc25
++#define mmHDP_XDP_P2P_MBX_ADDR0                                                 0xc26
++#define mmHDP_XDP_P2P_MBX_ADDR1                                                 0xc27
++#define mmHDP_XDP_P2P_MBX_ADDR2                                                 0xc28
++#define mmHDP_XDP_P2P_MBX_ADDR3                                                 0xc29
++#define mmHDP_XDP_P2P_MBX_ADDR4                                                 0xc2a
++#define mmHDP_XDP_P2P_MBX_ADDR5                                                 0xc2b
++#define mmHDP_XDP_P2P_MBX_ADDR6                                                 0xc2c
++#define mmHDP_XDP_HDP_MBX_MC_CFG                                                0xc2d
++#define mmHDP_XDP_HDP_MC_CFG                                                    0xc2e
++#define mmHDP_XDP_HST_CFG                                                       0xc2f
++#define mmHDP_XDP_SID_CFG                                                       0xc30
++#define mmHDP_XDP_HDP_IPH_CFG                                                   0xc31
++#define mmHDP_XDP_SRBM_CFG                                                      0xc32
++#define mmHDP_XDP_CGTT_BLK_CTRL                                                 0xc33
++#define mmHDP_XDP_P2P_BAR0                                                      0xc34
++#define mmHDP_XDP_P2P_BAR1                                                      0xc35
++#define mmHDP_XDP_P2P_BAR2                                                      0xc36
++#define mmHDP_XDP_P2P_BAR3                                                      0xc37
++#define mmHDP_XDP_P2P_BAR4                                                      0xc38
++#define mmHDP_XDP_P2P_BAR5                                                      0xc39
++#define mmHDP_XDP_P2P_BAR6                                                      0xc3a
++#define mmHDP_XDP_P2P_BAR7                                                      0xc3b
++#define mmHDP_XDP_FLUSH_ARMED_STS                                               0xc3c
++#define mmHDP_XDP_FLUSH_CNTR0_STS                                               0xc3d
++#define mmHDP_XDP_BUSY_STS                                                      0xc3e
++#define mmHDP_XDP_STICKY                                                        0xc3f
++#define mmHDP_XDP_CHKN                                                          0xc40
++#define mmHDP_XDP_DBG_ADDR                                                      0xc41
++#define mmHDP_XDP_DBG_DATA                                                      0xc42
++#define mmHDP_XDP_DBG_MASK                                                      0xc43
++#define mmHDP_XDP_BARS_ADDR_39_36                                               0xc44
++
++#endif /* OSS_2_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h
+new file mode 100644
+index 0000000..99e0b2d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h
+@@ -0,0 +1,2476 @@
++/*
++ * OSS_2_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_2_0_SH_MASK_H
++#define OSS_2_0_SH_MASK_H
++
++#define IH_VMID_0_LUT__PASID_MASK 0xffff
++#define IH_VMID_0_LUT__PASID__SHIFT 0x0
++#define IH_VMID_1_LUT__PASID_MASK 0xffff
++#define IH_VMID_1_LUT__PASID__SHIFT 0x0
++#define IH_VMID_2_LUT__PASID_MASK 0xffff
++#define IH_VMID_2_LUT__PASID__SHIFT 0x0
++#define IH_VMID_3_LUT__PASID_MASK 0xffff
++#define IH_VMID_3_LUT__PASID__SHIFT 0x0
++#define IH_VMID_4_LUT__PASID_MASK 0xffff
++#define IH_VMID_4_LUT__PASID__SHIFT 0x0
++#define IH_VMID_5_LUT__PASID_MASK 0xffff
++#define IH_VMID_5_LUT__PASID__SHIFT 0x0
++#define IH_VMID_6_LUT__PASID_MASK 0xffff
++#define IH_VMID_6_LUT__PASID__SHIFT 0x0
++#define IH_VMID_7_LUT__PASID_MASK 0xffff
++#define IH_VMID_7_LUT__PASID__SHIFT 0x0
++#define IH_VMID_8_LUT__PASID_MASK 0xffff
++#define IH_VMID_8_LUT__PASID__SHIFT 0x0
++#define IH_VMID_9_LUT__PASID_MASK 0xffff
++#define IH_VMID_9_LUT__PASID__SHIFT 0x0
++#define IH_VMID_10_LUT__PASID_MASK 0xffff
++#define IH_VMID_10_LUT__PASID__SHIFT 0x0
++#define IH_VMID_11_LUT__PASID_MASK 0xffff
++#define IH_VMID_11_LUT__PASID__SHIFT 0x0
++#define IH_VMID_12_LUT__PASID_MASK 0xffff
++#define IH_VMID_12_LUT__PASID__SHIFT 0x0
++#define IH_VMID_13_LUT__PASID_MASK 0xffff
++#define IH_VMID_13_LUT__PASID__SHIFT 0x0
++#define IH_VMID_14_LUT__PASID_MASK 0xffff
++#define IH_VMID_14_LUT__PASID__SHIFT 0x0
++#define IH_VMID_15_LUT__PASID_MASK 0xffff
++#define IH_VMID_15_LUT__PASID__SHIFT 0x0
++#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
++#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define IH_RB_BASE__ADDR_MASK 0xffffffff
++#define IH_RB_BASE__ADDR__SHIFT 0x0
++#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_RPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
++#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_WPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define IH_CNTL__ENABLE_INTR_MASK 0x1
++#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
++#define IH_CNTL__MC_SWAP_MASK 0x6
++#define IH_CNTL__MC_SWAP__SHIFT 0x1
++#define IH_CNTL__MC_TRAN_MASK 0x8
++#define IH_CNTL__MC_TRAN__SHIFT 0x3
++#define IH_CNTL__RPTR_REARM_MASK 0x10
++#define IH_CNTL__RPTR_REARM__SHIFT 0x4
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
++#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
++#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
++#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
++#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
++#define IH_CNTL__MC_VMID_MASK 0x1e000000
++#define IH_CNTL__MC_VMID__SHIFT 0x19
++#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
++#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
++#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
++#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
++#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
++#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
++#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
++#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
++#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
++#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
++#define IH_STATUS__IDLE_MASK 0x1
++#define IH_STATUS__IDLE__SHIFT 0x0
++#define IH_STATUS__INPUT_IDLE_MASK 0x2
++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
++#define IH_STATUS__RB_IDLE_MASK 0x4
++#define IH_STATUS__RB_IDLE__SHIFT 0x2
++#define IH_STATUS__RB_FULL_MASK 0x8
++#define IH_STATUS__RB_FULL__SHIFT 0x3
++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
++#define IH_STATUS__RB_OVERFLOW_MASK 0x20
++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
++#define IH_STATUS__MC_WR_IDLE_MASK 0x40
++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
++#define IH_STATUS__MC_WR_STALL_MASK 0x80
++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x7
++#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x0
++#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x8
++#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x3
++#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x10
++#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x4
++#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0xff00
++#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x8
++#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000
++#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x10
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
++#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
++#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
++#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
++#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
++#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
++#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
++#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
++#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
++#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
++#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
++#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
++#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
++#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
++#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
++#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
++#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
++#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00
++#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8
++#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000
++#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10
++#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00
++#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8
++#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000
++#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10
++#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00
++#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8
++#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000
++#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10
++#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00
++#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8
++#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000
++#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10
++#define SEM_STATUS__SEM_IDLE_MASK 0x1
++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
++#define SEM_MAILBOX__SIDEPORT_MASK 0xff
++#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
++#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
++#define SRBM_CNTL__READ_TIMEOUT_MASK 0x1fff
++#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
++#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
++#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
++#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
++#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
++#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL__MEID_MASK 0xc
++#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
++#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
++#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
++#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS2__XSP_BUSY_MASK 0x10
++#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4
++#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
++#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
++#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
++#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
++#define SRBM_STATUS2__VCE_BUSY_MASK 0x80
++#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x7
++#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
++#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
++#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
++#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
++#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS__SAM_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS__SAM_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
++#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
++#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
++#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
++#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
++#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
++#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x80
++#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x7
++#define SRBM_STATUS__VMC_BUSY_MASK 0x100
++#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
++#define SRBM_STATUS__MCB_BUSY_MASK 0x200
++#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
++#define SRBM_STATUS__MCC_BUSY_MASK 0x800
++#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
++#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
++#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
++#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
++#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
++#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
++#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
++#define SRBM_STATUS__IH_BUSY_MASK 0x20000
++#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
++#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
++#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
++#define SRBM_STATUS__SAM_BUSY_MASK 0x100000
++#define SRBM_STATUS__SAM_BUSY__SHIFT 0x14
++#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
++#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
++#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
++#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
++#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
++#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
++#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
++#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
++#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
++#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000
++#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
++#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
++#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
++#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000
++#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x1000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x18
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
++#define SRBM_SOFT_RESET__SOFT_RESET_SAM_MASK 0x8000000
++#define SRBM_SOFT_RESET__SOFT_RESET_SAM__SHIFT 0x1b
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
++#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
++#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
++#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
++#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
++#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
++#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
++#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
++#define SRBM_DEBUG_SNAPSHOT__SAM_RDY_MASK 0x8
++#define SRBM_DEBUG_SNAPSHOT__SAM_RDY__SHIFT 0x3
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
++#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400
++#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
++#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000
++#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
++#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000
++#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x1d
++#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
++#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x100000
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x14
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
++#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
++#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
++#define SRBM_READ_ERROR__READ_REQUESTER_SAM_MASK 0x800000
++#define SRBM_READ_ERROR__READ_REQUESTER_SAM__SHIFT 0x17
++#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
++#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
++#define SRBM_READ_ERROR__READ_REQUESTER_ACP_MASK 0x8000000
++#define SRBM_READ_ERROR__READ_REQUESTER_ACP__SHIFT 0x1b
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
++#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
++#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
++#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
++#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
++#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
++#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
++#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
++#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
++#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
++#define DH_TEST__DH_TEST_MASK 0x1
++#define DH_TEST__DH_TEST__SHIFT 0x0
++#define KHFS0__RESERVED_MASK 0xffffffff
++#define KHFS0__RESERVED__SHIFT 0x0
++#define KHFS1__RESERVED_MASK 0xffffffff
++#define KHFS1__RESERVED__SHIFT 0x0
++#define KHFS2__RESERVED_MASK 0xffffffff
++#define KHFS2__RESERVED__SHIFT 0x0
++#define KHFS3__RESERVED_MASK 0xffffffff
++#define KHFS3__RESERVED__SHIFT 0x0
++#define KSESSION0__RESERVED_MASK 0xffffffff
++#define KSESSION0__RESERVED__SHIFT 0x0
++#define KSESSION1__RESERVED_MASK 0xffffffff
++#define KSESSION1__RESERVED__SHIFT 0x0
++#define KSESSION2__RESERVED_MASK 0xffffffff
++#define KSESSION2__RESERVED__SHIFT 0x0
++#define KSESSION3__RESERVED_MASK 0xffffffff
++#define KSESSION3__RESERVED__SHIFT 0x0
++#define KSIG0__RESERVED_MASK 0xffffffff
++#define KSIG0__RESERVED__SHIFT 0x0
++#define KSIG1__RESERVED_MASK 0xffffffff
++#define KSIG1__RESERVED__SHIFT 0x0
++#define KSIG2__RESERVED_MASK 0xffffffff
++#define KSIG2__RESERVED__SHIFT 0x0
++#define KSIG3__RESERVED_MASK 0xffffffff
++#define KSIG3__RESERVED__SHIFT 0x0
++#define EXP0__RESERVED_MASK 0xffffffff
++#define EXP0__RESERVED__SHIFT 0x0
++#define EXP1__RESERVED_MASK 0xffffffff
++#define EXP1__RESERVED__SHIFT 0x0
++#define EXP2__RESERVED_MASK 0xffffffff
++#define EXP2__RESERVED__SHIFT 0x0
++#define EXP3__RESERVED_MASK 0xffffffff
++#define EXP3__RESERVED__SHIFT 0x0
++#define EXP4__RESERVED_MASK 0xffffffff
++#define EXP4__RESERVED__SHIFT 0x0
++#define EXP5__RESERVED_MASK 0xffffffff
++#define EXP5__RESERVED__SHIFT 0x0
++#define EXP6__RESERVED_MASK 0xffffffff
++#define EXP6__RESERVED__SHIFT 0x0
++#define EXP7__RESERVED_MASK 0xffffffff
++#define EXP7__RESERVED__SHIFT 0x0
++#define LX0__RESERVED_MASK 0xffffffff
++#define LX0__RESERVED__SHIFT 0x0
++#define LX1__RESERVED_MASK 0xffffffff
++#define LX1__RESERVED__SHIFT 0x0
++#define LX2__RESERVED_MASK 0xffffffff
++#define LX2__RESERVED__SHIFT 0x0
++#define LX3__RESERVED_MASK 0xffffffff
++#define LX3__RESERVED__SHIFT 0x0
++#define CLIENT2_K0__RESERVED_MASK 0xffffffff
++#define CLIENT2_K0__RESERVED__SHIFT 0x0
++#define CLIENT2_K1__RESERVED_MASK 0xffffffff
++#define CLIENT2_K1__RESERVED__SHIFT 0x0
++#define CLIENT2_K2__RESERVED_MASK 0xffffffff
++#define CLIENT2_K2__RESERVED__SHIFT 0x0
++#define CLIENT2_K3__RESERVED_MASK 0xffffffff
++#define CLIENT2_K3__RESERVED__SHIFT 0x0
++#define CLIENT2_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK0__RESERVED__SHIFT 0x0
++#define CLIENT2_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK1__RESERVED__SHIFT 0x0
++#define CLIENT2_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK2__RESERVED__SHIFT 0x0
++#define CLIENT2_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK3__RESERVED__SHIFT 0x0
++#define CLIENT2_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD0__RESERVED__SHIFT 0x0
++#define CLIENT2_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD1__RESERVED__SHIFT 0x0
++#define CLIENT2_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD2__RESERVED__SHIFT 0x0
++#define CLIENT2_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD3__RESERVED__SHIFT 0x0
++#define CLIENT2_BM__RESERVED_MASK 0xffffffff
++#define CLIENT2_BM__RESERVED__SHIFT 0x0
++#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT2_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT0_K0__RESERVED_MASK 0xffffffff
++#define CLIENT0_K0__RESERVED__SHIFT 0x0
++#define CLIENT0_K1__RESERVED_MASK 0xffffffff
++#define CLIENT0_K1__RESERVED__SHIFT 0x0
++#define CLIENT0_K2__RESERVED_MASK 0xffffffff
++#define CLIENT0_K2__RESERVED__SHIFT 0x0
++#define CLIENT0_K3__RESERVED_MASK 0xffffffff
++#define CLIENT0_K3__RESERVED__SHIFT 0x0
++#define CLIENT0_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK0__RESERVED__SHIFT 0x0
++#define CLIENT0_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK1__RESERVED__SHIFT 0x0
++#define CLIENT0_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK2__RESERVED__SHIFT 0x0
++#define CLIENT0_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK3__RESERVED__SHIFT 0x0
++#define CLIENT0_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD0__RESERVED__SHIFT 0x0
++#define CLIENT0_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD1__RESERVED__SHIFT 0x0
++#define CLIENT0_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD2__RESERVED__SHIFT 0x0
++#define CLIENT0_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD3__RESERVED__SHIFT 0x0
++#define CLIENT0_BM__RESERVED_MASK 0xffffffff
++#define CLIENT0_BM__RESERVED__SHIFT 0x0
++#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT0_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT1_K0__RESERVED_MASK 0xffffffff
++#define CLIENT1_K0__RESERVED__SHIFT 0x0
++#define CLIENT1_K1__RESERVED_MASK 0xffffffff
++#define CLIENT1_K1__RESERVED__SHIFT 0x0
++#define CLIENT1_K2__RESERVED_MASK 0xffffffff
++#define CLIENT1_K2__RESERVED__SHIFT 0x0
++#define CLIENT1_K3__RESERVED_MASK 0xffffffff
++#define CLIENT1_K3__RESERVED__SHIFT 0x0
++#define CLIENT1_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK0__RESERVED__SHIFT 0x0
++#define CLIENT1_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK1__RESERVED__SHIFT 0x0
++#define CLIENT1_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK2__RESERVED__SHIFT 0x0
++#define CLIENT1_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK3__RESERVED__SHIFT 0x0
++#define CLIENT1_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD0__RESERVED__SHIFT 0x0
++#define CLIENT1_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD1__RESERVED__SHIFT 0x0
++#define CLIENT1_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD2__RESERVED__SHIFT 0x0
++#define CLIENT1_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD3__RESERVED__SHIFT 0x0
++#define CLIENT1_BM__RESERVED_MASK 0xffffffff
++#define CLIENT1_BM__RESERVED__SHIFT 0x0
++#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0
++#define KEFUSE0__RESERVED_MASK 0xffffffff
++#define KEFUSE0__RESERVED__SHIFT 0x0
++#define KEFUSE1__RESERVED_MASK 0xffffffff
++#define KEFUSE1__RESERVED__SHIFT 0x0
++#define KEFUSE2__RESERVED_MASK 0xffffffff
++#define KEFUSE2__RESERVED__SHIFT 0x0
++#define KEFUSE3__RESERVED_MASK 0xffffffff
++#define KEFUSE3__RESERVED__SHIFT 0x0
++#define HFS_SEED0__RESERVED_MASK 0xffffffff
++#define HFS_SEED0__RESERVED__SHIFT 0x0
++#define HFS_SEED1__RESERVED_MASK 0xffffffff
++#define HFS_SEED1__RESERVED__SHIFT 0x0
++#define HFS_SEED2__RESERVED_MASK 0xffffffff
++#define HFS_SEED2__RESERVED__SHIFT 0x0
++#define HFS_SEED3__RESERVED_MASK 0xffffffff
++#define HFS_SEED3__RESERVED__SHIFT 0x0
++#define RINGOSC_MASK__MASK_MASK 0xffff
++#define RINGOSC_MASK__MASK__SHIFT 0x0
++#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0
++#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff
++#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT3_K0__RESERVED_MASK 0xffffffff
++#define CLIENT3_K0__RESERVED__SHIFT 0x0
++#define CLIENT3_K1__RESERVED_MASK 0xffffffff
++#define CLIENT3_K1__RESERVED__SHIFT 0x0
++#define CLIENT3_K2__RESERVED_MASK 0xffffffff
++#define CLIENT3_K2__RESERVED__SHIFT 0x0
++#define CLIENT3_K3__RESERVED_MASK 0xffffffff
++#define CLIENT3_K3__RESERVED__SHIFT 0x0
++#define CLIENT3_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK0__RESERVED__SHIFT 0x0
++#define CLIENT3_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK1__RESERVED__SHIFT 0x0
++#define CLIENT3_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK2__RESERVED__SHIFT 0x0
++#define CLIENT3_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK3__RESERVED__SHIFT 0x0
++#define CLIENT3_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD0__RESERVED__SHIFT 0x0
++#define CLIENT3_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD1__RESERVED__SHIFT 0x0
++#define CLIENT3_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD2__RESERVED__SHIFT 0x0
++#define CLIENT3_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD3__RESERVED__SHIFT 0x0
++#define CLIENT3_BM__RESERVED_MASK 0xffffffff
++#define CLIENT3_BM__RESERVED__SHIFT 0x0
++#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT3_STATUS__RESERVED__SHIFT 0x0
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
++#define SDMA0_UCODE_ADDR__VALUE_MASK 0x7ff
++#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
++#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA0_HASH__BANK_BITS_MASK 0x70
++#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff
++#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA0_STATUS_REG__IDLE_MASK 0x1
++#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
++#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_F32_CNTL__HALT_MASK 0x1
++#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA0_F32_CNTL__STEP_MASK 0x2
++#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA0_FREEZE__FREEZE_MASK 0x10
++#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA0_FREEZE__FROZEN_MASK 0x20
++#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
++#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
++#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
++#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
++#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
++#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
++#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
++#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
++#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
++#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
++#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
++#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
++#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
++#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
++#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_UCODE_ADDR__VALUE_MASK 0x7ff
++#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
++#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA1_HASH__BANK_BITS_MASK 0x70
++#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff
++#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA1_STATUS_REG__IDLE_MASK 0x1
++#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
++#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_F32_CNTL__HALT_MASK 0x1
++#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA1_F32_CNTL__STEP_MASK 0x2
++#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA1_FREEZE__FREEZE_MASK 0x10
++#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA1_FREEZE__FROZEN_MASK 0x20
++#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
++#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
++#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0xffff
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x0
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x10
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE_MASK 0x40000000
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE__SHIFT 0x1e
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000
++#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x1f
++#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT_MASK 0xffff
++#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT__SHIFT 0x0
++#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD_MASK 0x3fff0000
++#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD__SHIFT 0x10
++#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE_MASK 0x80000000
++#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE__SHIFT 0x1f
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
++#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x80000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x13
++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
++#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT_MASK 0xffff
++#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT__SHIFT 0x0
++#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER_MASK 0xffff0000
++#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER__SHIFT 0x10
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
++#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
++#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
++#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
++#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
++#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
++#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
++#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
++#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
++#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
++#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
++#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
++#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
++#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
++#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
++#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
++#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
++#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
++#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
++#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
++#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
++#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
++#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
++#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
++#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
++#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
++#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
++#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
++#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
++#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
++#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
++#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
++#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
++#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
++#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
++#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
++#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
++#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
++#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
++#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
++#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
++#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
++#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
++#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
++#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
++#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
++#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
++#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
++#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
++#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
++#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
++#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
++#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
++#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
++#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
++#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
++
++#endif /* OSS_2_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0015-yocto-amd-drm-amdgpu-add-VCE-2-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0015-yocto-amd-drm-amdgpu-add-VCE-2-0-register-headers.patch
new file mode 100644
index 00000000..27009fd2
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0015-yocto-amd-drm-amdgpu-add-VCE-2-0-register-headers.patch
@@ -0,0 +1,4387 @@
+From 756eef480dbefca90df2c63de7000a94b53ba9ca Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:26:30 -0400
+Subject: drm/amdgpu: add OSS 2.4 register headers
+
+These are register headers for the OSS (OS Services)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h
+new file mode 100644
+index 0000000..ca833d3
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h
+@@ -0,0 +1,471 @@
++/*
++ * OSS_2_4 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_2_4_D_H
++#define OSS_2_4_D_H
++
++#define mmIH_VMID_0_LUT                                                         0xe00
++#define mmIH_VMID_1_LUT                                                         0xe01
++#define mmIH_VMID_2_LUT                                                         0xe02
++#define mmIH_VMID_3_LUT                                                         0xe03
++#define mmIH_VMID_4_LUT                                                         0xe04
++#define mmIH_VMID_5_LUT                                                         0xe05
++#define mmIH_VMID_6_LUT                                                         0xe06
++#define mmIH_VMID_7_LUT                                                         0xe07
++#define mmIH_VMID_8_LUT                                                         0xe08
++#define mmIH_VMID_9_LUT                                                         0xe09
++#define mmIH_VMID_10_LUT                                                        0xe0a
++#define mmIH_VMID_11_LUT                                                        0xe0b
++#define mmIH_VMID_12_LUT                                                        0xe0c
++#define mmIH_VMID_13_LUT                                                        0xe0d
++#define mmIH_VMID_14_LUT                                                        0xe0e
++#define mmIH_VMID_15_LUT                                                        0xe0f
++#define mmIH_RB_CNTL                                                            0xe30
++#define mmIH_RB_BASE                                                            0xe31
++#define mmIH_RB_RPTR                                                            0xe32
++#define mmIH_RB_WPTR                                                            0xe33
++#define mmIH_RB_WPTR_ADDR_HI                                                    0xe34
++#define mmIH_RB_WPTR_ADDR_LO                                                    0xe35
++#define mmIH_CNTL                                                               0xe36
++#define mmIH_LEVEL_STATUS                                                       0xe37
++#define mmIH_STATUS                                                             0xe38
++#define mmIH_PERFMON_CNTL                                                       0xe39
++#define mmIH_PERFCOUNTER0_RESULT                                                0xe3a
++#define mmIH_PERFCOUNTER1_RESULT                                                0xe3b
++#define mmIH_DSM_MATCH_VALUE_BIT_31_0                                           0xe3d
++#define mmIH_DSM_MATCH_VALUE_BIT_63_32                                          0xe3e
++#define mmIH_DSM_MATCH_VALUE_BIT_95_64                                          0xe3f
++#define mmIH_DSM_MATCH_FIELD_CONTROL                                            0xe40
++#define mmIH_DSM_MATCH_DATA_CONTROL                                             0xe41
++#define mmIH_VERSION                                                            0xe42
++#define mmSEM_MCIF_CONFIG                                                       0xf90
++#define mmSDMA_CONFIG                                                           0xf91
++#define mmSDMA1_CONFIG                                                          0xf92
++#define mmUVD_CONFIG                                                            0xf93
++#define mmVCE_CONFIG                                                            0xf94
++#define mmACP_CONFIG                                                            0xf95
++#define mmCPG_CONFIG                                                            0xf96
++#define mmCPC1_CONFIG                                                           0xf97
++#define mmCPC2_CONFIG                                                           0xf98
++#define mmSEM_STATUS                                                            0xf99
++#define mmSEM_EDC_CONFIG                                                        0xf9a
++#define mmSEM_MAILBOX_CLIENTCONFIG                                              0xf9b
++#define mmSEM_MAILBOX                                                           0xf9c
++#define mmSEM_MAILBOX_CONTROL                                                   0xf9d
++#define mmSEM_CHICKEN_BITS                                                      0xf9e
++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA                                        0xf9f
++#define mmSRBM_CNTL                                                             0x390
++#define mmSRBM_GFX_CNTL                                                         0x391
++#define mmSRBM_READ_CNTL                                                        0x392
++#define mmSRBM_STATUS2                                                          0x393
++#define mmSRBM_STATUS                                                           0x394
++#define mmSRBM_STATUS3                                                          0x395
++#define mmSRBM_SOFT_RESET                                                       0x398
++#define mmSRBM_DEBUG_CNTL                                                       0x399
++#define mmSRBM_DEBUG_DATA                                                       0x39a
++#define mmSRBM_CHIP_REVISION                                                    0x39b
++#define mmCC_SYS_RB_REDUNDANCY                                                  0x39f
++#define mmCC_SYS_RB_BACKEND_DISABLE                                             0x3a0
++#define mmGC_USER_SYS_RB_BACKEND_DISABLE                                        0x3a1
++#define mmSRBM_MC_CLKEN_CNTL                                                    0x3b3
++#define mmSRBM_SYS_CLKEN_CNTL                                                   0x3b4
++#define mmSRBM_VCE_CLKEN_CNTL                                                   0x3b5
++#define mmSRBM_UVD_CLKEN_CNTL                                                   0x3b6
++#define mmSRBM_SDMA_CLKEN_CNTL                                                  0x3b7
++#define mmSRBM_SAM_CLKEN_CNTL                                                   0x3b8
++#define mmSRBM_ISP_CLKEN_CNTL                                                   0x3b9
++#define mmSRBM_DEBUG                                                            0x3a4
++#define mmSRBM_DEBUG_SNAPSHOT                                                   0x3a5
++#define mmSRBM_DEBUG_SNAPSHOT2                                                  0x3ad
++#define mmSRBM_READ_ERROR                                                       0x3a6
++#define mmSRBM_READ_ERROR2                                                      0x3ae
++#define mmSRBM_INT_CNTL                                                         0x3a8
++#define mmSRBM_INT_STATUS                                                       0x3a9
++#define mmSRBM_INT_ACK                                                          0x3aa
++#define mmSRBM_FIREWALL_ERROR_SRC                                               0x3ab
++#define mmSRBM_FIREWALL_ERROR_ADDR                                              0x3ac
++#define mmSRBM_DSM_TRIG_CNTL0                                                   0x3af
++#define mmSRBM_DSM_TRIG_CNTL1                                                   0x3b0
++#define mmSRBM_DSM_TRIG_MASK0                                                   0x3b1
++#define mmSRBM_DSM_TRIG_MASK1                                                   0x3b2
++#define mmSRBM_PERFMON_CNTL                                                     0x7c00
++#define mmSRBM_PERFCOUNTER0_SELECT                                              0x7c01
++#define mmSRBM_PERFCOUNTER1_SELECT                                              0x7c02
++#define mmSRBM_PERFCOUNTER0_LO                                                  0x7c03
++#define mmSRBM_PERFCOUNTER0_HI                                                  0x7c04
++#define mmSRBM_PERFCOUNTER1_LO                                                  0x7c05
++#define mmSRBM_PERFCOUNTER1_HI                                                  0x7c06
++#define mmSRBM_CAM_INDEX                                                        0xfe34
++#define mmSRBM_CAM_DATA                                                         0xfe35
++#define mmSRBM_MC_DOMAIN_ADDR0                                                  0xfa00
++#define mmSRBM_MC_DOMAIN_ADDR1                                                  0xfa01
++#define mmSRBM_MC_DOMAIN_ADDR2                                                  0xfa02
++#define mmSRBM_MC_DOMAIN_ADDR3                                                  0xfa03
++#define mmSRBM_MC_DOMAIN_ADDR4                                                  0xfa04
++#define mmSRBM_MC_DOMAIN_ADDR5                                                  0xfa05
++#define mmSRBM_MC_DOMAIN_ADDR6                                                  0xfa06
++#define mmSRBM_SYS_DOMAIN_ADDR0                                                 0xfa08
++#define mmSRBM_SYS_DOMAIN_ADDR1                                                 0xfa09
++#define mmSRBM_SYS_DOMAIN_ADDR2                                                 0xfa0a
++#define mmSRBM_SYS_DOMAIN_ADDR3                                                 0xfa0b
++#define mmSRBM_SYS_DOMAIN_ADDR4                                                 0xfa0c
++#define mmSRBM_SYS_DOMAIN_ADDR5                                                 0xfa0d
++#define mmSRBM_SYS_DOMAIN_ADDR6                                                 0xfa0e
++#define mmSRBM_SDMA_DOMAIN_ADDR0                                                0xfa10
++#define mmSRBM_SDMA_DOMAIN_ADDR1                                                0xfa11
++#define mmSRBM_SDMA_DOMAIN_ADDR2                                                0xfa12
++#define mmSRBM_SDMA_DOMAIN_ADDR3                                                0xfa13
++#define mmSRBM_UVD_DOMAIN_ADDR0                                                 0xfa14
++#define mmSRBM_UVD_DOMAIN_ADDR1                                                 0xfa15
++#define mmSRBM_UVD_DOMAIN_ADDR2                                                 0xfa16
++#define mmSRBM_VCE_DOMAIN_ADDR0                                                 0xfa18
++#define mmSRBM_VCE_DOMAIN_ADDR1                                                 0xfa19
++#define mmSRBM_VCE_DOMAIN_ADDR2                                                 0xfa1a
++#define mmSRBM_SAM_DOMAIN_ADDR0                                                 0xfa1c
++#define mmSRBM_SAM_DOMAIN_ADDR1                                                 0xfa1d
++#define mmSRBM_SAM_DOMAIN_ADDR2                                                 0xfa1e
++#define mmSRBM_ISP_DOMAIN_ADDR0                                                 0xfa20
++#define mmSRBM_ISP_DOMAIN_ADDR1                                                 0xfa21
++#define mmSRBM_ISP_DOMAIN_ADDR2                                                 0xfa22
++#define mmSYS_GRBM_GFX_INDEX_SELECT                                             0xfa2c
++#define mmSYS_GRBM_GFX_INDEX_DATA                                               0xfa2d
++#define mmSRBM_GFX_CNTL_SELECT                                                  0xfa2e
++#define mmSRBM_GFX_CNTL_DATA                                                    0xfa2f
++#define mmSRBM_VF_ENABLE                                                        0xfa30
++#define mmSRBM_VIRT_CNTL                                                        0xfa31
++#define mmSRBM_VIRT_RESET_REQ                                                   0xfa32
++#define mmSDMA0_UCODE_ADDR                                                      0x3400
++#define mmSDMA0_UCODE_DATA                                                      0x3401
++#define mmSDMA0_POWER_CNTL                                                      0x3402
++#define mmSDMA0_CLK_CTRL                                                        0x3403
++#define mmSDMA0_CNTL                                                            0x3404
++#define mmSDMA0_CHICKEN_BITS                                                    0x3405
++#define mmSDMA0_TILING_CONFIG                                                   0x3406
++#define mmSDMA0_HASH                                                            0x3407
++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3409
++#define mmSDMA0_RB_RPTR_FETCH                                                   0x340a
++#define mmSDMA0_IB_OFFSET_FETCH                                                 0x340b
++#define mmSDMA0_PROGRAM                                                         0x340c
++#define mmSDMA0_STATUS_REG                                                      0x340d
++#define mmSDMA0_STATUS1_REG                                                     0x340e
++#define mmSDMA0_PERFMON_CNTL                                                    0x9000
++#define mmSDMA0_PERFCOUNTER0_RESULT                                             0x9001
++#define mmSDMA0_PERFCOUNTER1_RESULT                                             0x9002
++#define mmSDMA0_F32_CNTL                                                        0x3412
++#define mmSDMA0_FREEZE                                                          0x3413
++#define mmSDMA0_PHASE0_QUANTUM                                                  0x3414
++#define mmSDMA0_PHASE1_QUANTUM                                                  0x3415
++#define mmSDMA_POWER_GATING                                                     0x3416
++#define mmSDMA_PGFSM_CONFIG                                                     0x3417
++#define mmSDMA_PGFSM_WRITE                                                      0x3418
++#define mmSDMA_PGFSM_READ                                                       0x3419
++#define mmSDMA0_EDC_CONFIG                                                      0x341a
++#define mmSDMA0_BA_THRESHOLD                                                    0x341b
++#define mmSDMA0_ID                                                              0x341c
++#define mmSDMA0_VERSION                                                         0x341d
++#define mmSDMA0_STATUS2_REG                                                     0x341e
++#define mmSDMA0_GFX_RB_CNTL                                                     0x3480
++#define mmSDMA0_GFX_RB_BASE                                                     0x3481
++#define mmSDMA0_GFX_RB_BASE_HI                                                  0x3482
++#define mmSDMA0_GFX_RB_RPTR                                                     0x3483
++#define mmSDMA0_GFX_RB_WPTR                                                     0x3484
++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                           0x3485
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3486
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3487
++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                             0x3488
++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                             0x3489
++#define mmSDMA0_GFX_IB_CNTL                                                     0x348a
++#define mmSDMA0_GFX_IB_RPTR                                                     0x348b
++#define mmSDMA0_GFX_IB_OFFSET                                                   0x348c
++#define mmSDMA0_GFX_IB_BASE_LO                                                  0x348d
++#define mmSDMA0_GFX_IB_BASE_HI                                                  0x348e
++#define mmSDMA0_GFX_IB_SIZE                                                     0x348f
++#define mmSDMA0_GFX_SKIP_CNTL                                                   0x3490
++#define mmSDMA0_GFX_CONTEXT_STATUS                                              0x3491
++#define mmSDMA0_GFX_CONTEXT_CNTL                                                0x3493
++#define mmSDMA0_GFX_VIRTUAL_ADDR                                                0x34a7
++#define mmSDMA0_GFX_APE1_CNTL                                                   0x34a8
++#define mmSDMA0_GFX_WATERMARK                                                   0x34aa
++#define mmSDMA0_GFX_CSA_ADDR_LO                                                 0x34ac
++#define mmSDMA0_GFX_CSA_ADDR_HI                                                 0x34ad
++#define mmSDMA0_GFX_DUMMY_REG                                                   0x34ae
++#define mmSDMA0_GFX_IB_SUB_REMAIN                                               0x34af
++#define mmSDMA0_GFX_PREEMPT                                                     0x34b0
++#define mmSDMA0_RLC0_RB_CNTL                                                    0x3500
++#define mmSDMA0_RLC0_RB_BASE                                                    0x3501
++#define mmSDMA0_RLC0_RB_BASE_HI                                                 0x3502
++#define mmSDMA0_RLC0_RB_RPTR                                                    0x3503
++#define mmSDMA0_RLC0_RB_WPTR                                                    0x3504
++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                          0x3505
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3506
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3507
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                            0x3508
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                            0x3509
++#define mmSDMA0_RLC0_IB_CNTL                                                    0x350a
++#define mmSDMA0_RLC0_IB_RPTR                                                    0x350b
++#define mmSDMA0_RLC0_IB_OFFSET                                                  0x350c
++#define mmSDMA0_RLC0_IB_BASE_LO                                                 0x350d
++#define mmSDMA0_RLC0_IB_BASE_HI                                                 0x350e
++#define mmSDMA0_RLC0_IB_SIZE                                                    0x350f
++#define mmSDMA0_RLC0_SKIP_CNTL                                                  0x3510
++#define mmSDMA0_RLC0_CONTEXT_STATUS                                             0x3511
++#define mmSDMA0_RLC0_DOORBELL                                                   0x3512
++#define mmSDMA0_RLC0_VIRTUAL_ADDR                                               0x3527
++#define mmSDMA0_RLC0_APE1_CNTL                                                  0x3528
++#define mmSDMA0_RLC0_DOORBELL_LOG                                               0x3529
++#define mmSDMA0_RLC0_WATERMARK                                                  0x352a
++#define mmSDMA0_RLC0_CSA_ADDR_LO                                                0x352c
++#define mmSDMA0_RLC0_CSA_ADDR_HI                                                0x352d
++#define mmSDMA0_RLC0_DUMMY_REG                                                  0x352e
++#define mmSDMA0_RLC0_IB_SUB_REMAIN                                              0x352f
++#define mmSDMA0_RLC0_PREEMPT                                                    0x3530
++#define mmSDMA0_RLC1_RB_CNTL                                                    0x3580
++#define mmSDMA0_RLC1_RB_BASE                                                    0x3581
++#define mmSDMA0_RLC1_RB_BASE_HI                                                 0x3582
++#define mmSDMA0_RLC1_RB_RPTR                                                    0x3583
++#define mmSDMA0_RLC1_RB_WPTR                                                    0x3584
++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                          0x3585
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3586
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3587
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                            0x3588
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                            0x3589
++#define mmSDMA0_RLC1_IB_CNTL                                                    0x358a
++#define mmSDMA0_RLC1_IB_RPTR                                                    0x358b
++#define mmSDMA0_RLC1_IB_OFFSET                                                  0x358c
++#define mmSDMA0_RLC1_IB_BASE_LO                                                 0x358d
++#define mmSDMA0_RLC1_IB_BASE_HI                                                 0x358e
++#define mmSDMA0_RLC1_IB_SIZE                                                    0x358f
++#define mmSDMA0_RLC1_SKIP_CNTL                                                  0x3590
++#define mmSDMA0_RLC1_CONTEXT_STATUS                                             0x3591
++#define mmSDMA0_RLC1_DOORBELL                                                   0x3592
++#define mmSDMA0_RLC1_VIRTUAL_ADDR                                               0x35a7
++#define mmSDMA0_RLC1_APE1_CNTL                                                  0x35a8
++#define mmSDMA0_RLC1_DOORBELL_LOG                                               0x35a9
++#define mmSDMA0_RLC1_WATERMARK                                                  0x35aa
++#define mmSDMA0_RLC1_CSA_ADDR_LO                                                0x35ac
++#define mmSDMA0_RLC1_CSA_ADDR_HI                                                0x35ad
++#define mmSDMA0_RLC1_DUMMY_REG                                                  0x35ae
++#define mmSDMA0_RLC1_IB_SUB_REMAIN                                              0x35af
++#define mmSDMA0_RLC1_PREEMPT                                                    0x35b0
++#define mmSDMA1_UCODE_ADDR                                                      0x3600
++#define mmSDMA1_UCODE_DATA                                                      0x3601
++#define mmSDMA1_POWER_CNTL                                                      0x3602
++#define mmSDMA1_CLK_CTRL                                                        0x3603
++#define mmSDMA1_CNTL                                                            0x3604
++#define mmSDMA1_CHICKEN_BITS                                                    0x3605
++#define mmSDMA1_TILING_CONFIG                                                   0x3606
++#define mmSDMA1_HASH                                                            0x3607
++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3609
++#define mmSDMA1_RB_RPTR_FETCH                                                   0x360a
++#define mmSDMA1_IB_OFFSET_FETCH                                                 0x360b
++#define mmSDMA1_PROGRAM                                                         0x360c
++#define mmSDMA1_STATUS_REG                                                      0x360d
++#define mmSDMA1_STATUS1_REG                                                     0x360e
++#define mmSDMA1_PERFMON_CNTL                                                    0x9010
++#define mmSDMA1_PERFCOUNTER0_RESULT                                             0x9011
++#define mmSDMA1_PERFCOUNTER1_RESULT                                             0x9012
++#define mmSDMA1_F32_CNTL                                                        0x3612
++#define mmSDMA1_FREEZE                                                          0x3613
++#define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
++#define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
++#define mmSDMA1_EDC_CONFIG                                                      0x361a
++#define mmSDMA1_BA_THRESHOLD                                                    0x361b
++#define mmSDMA1_ID                                                              0x361c
++#define mmSDMA1_VERSION                                                         0x361d
++#define mmSDMA1_STATUS2_REG                                                     0x361e
++#define mmSDMA1_GFX_RB_CNTL                                                     0x3680
++#define mmSDMA1_GFX_RB_BASE                                                     0x3681
++#define mmSDMA1_GFX_RB_BASE_HI                                                  0x3682
++#define mmSDMA1_GFX_RB_RPTR                                                     0x3683
++#define mmSDMA1_GFX_RB_WPTR                                                     0x3684
++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3686
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3687
++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                             0x3688
++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                             0x3689
++#define mmSDMA1_GFX_IB_CNTL                                                     0x368a
++#define mmSDMA1_GFX_IB_RPTR                                                     0x368b
++#define mmSDMA1_GFX_IB_OFFSET                                                   0x368c
++#define mmSDMA1_GFX_IB_BASE_LO                                                  0x368d
++#define mmSDMA1_GFX_IB_BASE_HI                                                  0x368e
++#define mmSDMA1_GFX_IB_SIZE                                                     0x368f
++#define mmSDMA1_GFX_SKIP_CNTL                                                   0x3690
++#define mmSDMA1_GFX_CONTEXT_STATUS                                              0x3691
++#define mmSDMA1_GFX_CONTEXT_CNTL                                                0x3693
++#define mmSDMA1_GFX_VIRTUAL_ADDR                                                0x36a7
++#define mmSDMA1_GFX_APE1_CNTL                                                   0x36a8
++#define mmSDMA1_GFX_WATERMARK                                                   0x36aa
++#define mmSDMA1_GFX_CSA_ADDR_LO                                                 0x36ac
++#define mmSDMA1_GFX_CSA_ADDR_HI                                                 0x36ad
++#define mmSDMA1_GFX_DUMMY_REG                                                   0x36ae
++#define mmSDMA1_GFX_IB_SUB_REMAIN                                               0x36af
++#define mmSDMA1_GFX_PREEMPT                                                     0x36b0
++#define mmSDMA1_RLC0_RB_CNTL                                                    0x3700
++#define mmSDMA1_RLC0_RB_BASE                                                    0x3701
++#define mmSDMA1_RLC0_RB_BASE_HI                                                 0x3702
++#define mmSDMA1_RLC0_RB_RPTR                                                    0x3703
++#define mmSDMA1_RLC0_RB_WPTR                                                    0x3704
++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                          0x3705
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3706
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3707
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                            0x3708
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                            0x3709
++#define mmSDMA1_RLC0_IB_CNTL                                                    0x370a
++#define mmSDMA1_RLC0_IB_RPTR                                                    0x370b
++#define mmSDMA1_RLC0_IB_OFFSET                                                  0x370c
++#define mmSDMA1_RLC0_IB_BASE_LO                                                 0x370d
++#define mmSDMA1_RLC0_IB_BASE_HI                                                 0x370e
++#define mmSDMA1_RLC0_IB_SIZE                                                    0x370f
++#define mmSDMA1_RLC0_SKIP_CNTL                                                  0x3710
++#define mmSDMA1_RLC0_CONTEXT_STATUS                                             0x3711
++#define mmSDMA1_RLC0_DOORBELL                                                   0x3712
++#define mmSDMA1_RLC0_VIRTUAL_ADDR                                               0x3727
++#define mmSDMA1_RLC0_APE1_CNTL                                                  0x3728
++#define mmSDMA1_RLC0_DOORBELL_LOG                                               0x3729
++#define mmSDMA1_RLC0_WATERMARK                                                  0x372a
++#define mmSDMA1_RLC0_CSA_ADDR_LO                                                0x372c
++#define mmSDMA1_RLC0_CSA_ADDR_HI                                                0x372d
++#define mmSDMA1_RLC0_DUMMY_REG                                                  0x372e
++#define mmSDMA1_RLC0_IB_SUB_REMAIN                                              0x372f
++#define mmSDMA1_RLC0_PREEMPT                                                    0x3730
++#define mmSDMA1_RLC1_RB_CNTL                                                    0x3780
++#define mmSDMA1_RLC1_RB_BASE                                                    0x3781
++#define mmSDMA1_RLC1_RB_BASE_HI                                                 0x3782
++#define mmSDMA1_RLC1_RB_RPTR                                                    0x3783
++#define mmSDMA1_RLC1_RB_WPTR                                                    0x3784
++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                          0x3785
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3786
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3787
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                            0x3788
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                            0x3789
++#define mmSDMA1_RLC1_IB_CNTL                                                    0x378a
++#define mmSDMA1_RLC1_IB_RPTR                                                    0x378b
++#define mmSDMA1_RLC1_IB_OFFSET                                                  0x378c
++#define mmSDMA1_RLC1_IB_BASE_LO                                                 0x378d
++#define mmSDMA1_RLC1_IB_BASE_HI                                                 0x378e
++#define mmSDMA1_RLC1_IB_SIZE                                                    0x378f
++#define mmSDMA1_RLC1_SKIP_CNTL                                                  0x3790
++#define mmSDMA1_RLC1_CONTEXT_STATUS                                             0x3791
++#define mmSDMA1_RLC1_DOORBELL                                                   0x3792
++#define mmSDMA1_RLC1_VIRTUAL_ADDR                                               0x37a7
++#define mmSDMA1_RLC1_APE1_CNTL                                                  0x37a8
++#define mmSDMA1_RLC1_DOORBELL_LOG                                               0x37a9
++#define mmSDMA1_RLC1_WATERMARK                                                  0x37aa
++#define mmSDMA1_RLC1_CSA_ADDR_LO                                                0x37ac
++#define mmSDMA1_RLC1_CSA_ADDR_HI                                                0x37ad
++#define mmSDMA1_RLC1_DUMMY_REG                                                  0x37ae
++#define mmSDMA1_RLC1_IB_SUB_REMAIN                                              0x37af
++#define mmSDMA1_RLC1_PREEMPT                                                    0x37b0
++#define mmHDP_HOST_PATH_CNTL                                                    0xb00
++#define mmHDP_NONSURFACE_BASE                                                   0xb01
++#define mmHDP_NONSURFACE_INFO                                                   0xb02
++#define mmHDP_NONSURFACE_SIZE                                                   0xb03
++#define mmHDP_NONSURF_FLAGS                                                     0xbc9
++#define mmHDP_NONSURF_FLAGS_CLR                                                 0xbca
++#define mmHDP_SW_SEMAPHORE                                                      0xbcb
++#define mmHDP_DEBUG0                                                            0xbcc
++#define mmHDP_DEBUG1                                                            0xbcd
++#define mmHDP_LAST_SURFACE_HIT                                                  0xbce
++#define mmHDP_TILING_CONFIG                                                     0xbcf
++#define mmHDP_SC_MULTI_CHIP_CNTL                                                0xbd0
++#define mmHDP_OUTSTANDING_REQ                                                   0xbd1
++#define mmHDP_ADDR_CONFIG                                                       0xbd2
++#define mmHDP_MISC_CNTL                                                         0xbd3
++#define mmHDP_MEM_POWER_LS                                                      0xbd4
++#define mmHDP_NONSURFACE_PREFETCH                                               0xbd5
++#define mmHDP_MEMIO_CNTL                                                        0xbf6
++#define mmHDP_MEMIO_ADDR                                                        0xbf7
++#define mmHDP_MEMIO_STATUS                                                      0xbf8
++#define mmHDP_MEMIO_WR_DATA                                                     0xbf9
++#define mmHDP_MEMIO_RD_DATA                                                     0xbfa
++#define mmHDP_XDP_DIRECT2HDP_FIRST                                              0xc00
++#define mmHDP_XDP_D2H_FLUSH                                                     0xc01
++#define mmHDP_XDP_D2H_BAR_UPDATE                                                0xc02
++#define mmHDP_XDP_D2H_RSVD_3                                                    0xc03
++#define mmHDP_XDP_D2H_RSVD_4                                                    0xc04
++#define mmHDP_XDP_D2H_RSVD_5                                                    0xc05
++#define mmHDP_XDP_D2H_RSVD_6                                                    0xc06
++#define mmHDP_XDP_D2H_RSVD_7                                                    0xc07
++#define mmHDP_XDP_D2H_RSVD_8                                                    0xc08
++#define mmHDP_XDP_D2H_RSVD_9                                                    0xc09
++#define mmHDP_XDP_D2H_RSVD_10                                                   0xc0a
++#define mmHDP_XDP_D2H_RSVD_11                                                   0xc0b
++#define mmHDP_XDP_D2H_RSVD_12                                                   0xc0c
++#define mmHDP_XDP_D2H_RSVD_13                                                   0xc0d
++#define mmHDP_XDP_D2H_RSVD_14                                                   0xc0e
++#define mmHDP_XDP_D2H_RSVD_15                                                   0xc0f
++#define mmHDP_XDP_D2H_RSVD_16                                                   0xc10
++#define mmHDP_XDP_D2H_RSVD_17                                                   0xc11
++#define mmHDP_XDP_D2H_RSVD_18                                                   0xc12
++#define mmHDP_XDP_D2H_RSVD_19                                                   0xc13
++#define mmHDP_XDP_D2H_RSVD_20                                                   0xc14
++#define mmHDP_XDP_D2H_RSVD_21                                                   0xc15
++#define mmHDP_XDP_D2H_RSVD_22                                                   0xc16
++#define mmHDP_XDP_D2H_RSVD_23                                                   0xc17
++#define mmHDP_XDP_D2H_RSVD_24                                                   0xc18
++#define mmHDP_XDP_D2H_RSVD_25                                                   0xc19
++#define mmHDP_XDP_D2H_RSVD_26                                                   0xc1a
++#define mmHDP_XDP_D2H_RSVD_27                                                   0xc1b
++#define mmHDP_XDP_D2H_RSVD_28                                                   0xc1c
++#define mmHDP_XDP_D2H_RSVD_29                                                   0xc1d
++#define mmHDP_XDP_D2H_RSVD_30                                                   0xc1e
++#define mmHDP_XDP_D2H_RSVD_31                                                   0xc1f
++#define mmHDP_XDP_D2H_RSVD_32                                                   0xc20
++#define mmHDP_XDP_D2H_RSVD_33                                                   0xc21
++#define mmHDP_XDP_D2H_RSVD_34                                                   0xc22
++#define mmHDP_XDP_DIRECT2HDP_LAST                                               0xc23
++#define mmHDP_XDP_P2P_BAR_CFG                                                   0xc24
++#define mmHDP_XDP_P2P_MBX_OFFSET                                                0xc25
++#define mmHDP_XDP_P2P_MBX_ADDR0                                                 0xc26
++#define mmHDP_XDP_P2P_MBX_ADDR1                                                 0xc27
++#define mmHDP_XDP_P2P_MBX_ADDR2                                                 0xc28
++#define mmHDP_XDP_P2P_MBX_ADDR3                                                 0xc29
++#define mmHDP_XDP_P2P_MBX_ADDR4                                                 0xc2a
++#define mmHDP_XDP_P2P_MBX_ADDR5                                                 0xc2b
++#define mmHDP_XDP_P2P_MBX_ADDR6                                                 0xc2c
++#define mmHDP_XDP_HDP_MBX_MC_CFG                                                0xc2d
++#define mmHDP_XDP_HDP_MC_CFG                                                    0xc2e
++#define mmHDP_XDP_HST_CFG                                                       0xc2f
++#define mmHDP_XDP_SID_CFG                                                       0xc30
++#define mmHDP_XDP_HDP_IPH_CFG                                                   0xc31
++#define mmHDP_XDP_SRBM_CFG                                                      0xc32
++#define mmHDP_XDP_CGTT_BLK_CTRL                                                 0xc33
++#define mmHDP_XDP_P2P_BAR0                                                      0xc34
++#define mmHDP_XDP_P2P_BAR1                                                      0xc35
++#define mmHDP_XDP_P2P_BAR2                                                      0xc36
++#define mmHDP_XDP_P2P_BAR3                                                      0xc37
++#define mmHDP_XDP_P2P_BAR4                                                      0xc38
++#define mmHDP_XDP_P2P_BAR5                                                      0xc39
++#define mmHDP_XDP_P2P_BAR6                                                      0xc3a
++#define mmHDP_XDP_P2P_BAR7                                                      0xc3b
++#define mmHDP_XDP_FLUSH_ARMED_STS                                               0xc3c
++#define mmHDP_XDP_FLUSH_CNTR0_STS                                               0xc3d
++#define mmHDP_XDP_BUSY_STS                                                      0xc3e
++#define mmHDP_XDP_STICKY                                                        0xc3f
++#define mmHDP_XDP_CHKN                                                          0xc40
++#define mmHDP_XDP_DBG_ADDR                                                      0xc41
++#define mmHDP_XDP_DBG_DATA                                                      0xc42
++#define mmHDP_XDP_DBG_MASK                                                      0xc43
++#define mmHDP_XDP_BARS_ADDR_39_36                                               0xc44
++
++#endif /* OSS_2_4_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
+new file mode 100644
+index 0000000..37adf0d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
+@@ -0,0 +1,1340 @@
++/*
++ * OSS_2_4 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_2_4_ENUM_H
++#define OSS_2_4_ENUM_H
++
++typedef enum IH_CLIENT_ID {
++	DC_IH_SRC_ID_START                               = 0x1,
++	DC_IH_SRC_ID_END                                 = 0x1f,
++	VGA_IH_SRC_ID_START                              = 0x20,
++	VGA_IH_SRC_ID_END                                = 0x27,
++	CAP_IH_SRC_ID_START                              = 0x28,
++	CAP_IH_SRC_ID_END                                = 0x2f,
++	VIP_IH_SRC_ID_START                              = 0x30,
++	VIP_IH_SRC_ID_END                                = 0x3f,
++	ROM_IH_SRC_ID_START                              = 0x40,
++	ROM_IH_SRC_ID_END                                = 0x5d,
++	BIF_IH_SRC_ID_START                              = 0x5e,
++	SAM_IH_SRC_ID_START                              = 0x5f,
++	SRBM_IH_SRC_ID_START                             = 0x60,
++	SRBM_IH_SRC_ID_END                               = 0x67,
++	UVD_IH_SRC_ID_START                              = 0x72,
++	UVD_IH_SRC_ID_END                                = 0x85,
++	VMC_IH_SRC_ID_START                              = 0x86,
++	VMC_IH_SRC_ID_END                                = 0x8f,
++	RLC_IH_SRC_ID_START                              = 0x90,
++	RLC_IH_SRC_ID_END                                = 0xf3,
++	PDMA_IH_SRC_ID_START                             = 0xf4,
++	PDMA_IH_SRC_ID_END                               = 0xf7,
++	CG_IH_SRC_ID_START                               = 0xf8,
++	CG_IH_SRC_ID_END                                 = 0xff,
++} IH_CLIENT_ID;
++typedef enum IH_PERF_SEL {
++	IH_PERF_SEL_CYCLE                                = 0x0,
++	IH_PERF_SEL_IDLE                                 = 0x1,
++	IH_PERF_SEL_INPUT_IDLE                           = 0x2,
++	IH_PERF_SEL_CLIENT0_IH_STALL                     = 0x3,
++	IH_PERF_SEL_CLIENT1_IH_STALL                     = 0x4,
++	IH_PERF_SEL_CLIENT2_IH_STALL                     = 0x5,
++	IH_PERF_SEL_CLIENT3_IH_STALL                     = 0x6,
++	IH_PERF_SEL_CLIENT4_IH_STALL                     = 0x7,
++	IH_PERF_SEL_CLIENT5_IH_STALL                     = 0x8,
++	IH_PERF_SEL_CLIENT6_IH_STALL                     = 0x9,
++	IH_PERF_SEL_CLIENT7_IH_STALL                     = 0xa,
++	IH_PERF_SEL_RB_IDLE                              = 0xb,
++	IH_PERF_SEL_RB_FULL                              = 0xc,
++	IH_PERF_SEL_RB_OVERFLOW                          = 0xd,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK                    = 0xe,
++	IH_PERF_SEL_RB_WPTR_WRAP                         = 0xf,
++	IH_PERF_SEL_RB_RPTR_WRAP                         = 0x10,
++	IH_PERF_SEL_MC_WR_IDLE                           = 0x11,
++	IH_PERF_SEL_MC_WR_COUNT                          = 0x12,
++	IH_PERF_SEL_MC_WR_STALL                          = 0x13,
++	IH_PERF_SEL_MC_WR_CLEAN_PENDING                  = 0x14,
++	IH_PERF_SEL_MC_WR_CLEAN_STALL                    = 0x15,
++	IH_PERF_SEL_BIF_RISING                           = 0x16,
++	IH_PERF_SEL_BIF_FALLING                          = 0x17,
++	IH_PERF_SEL_CLIENT8_IH_STALL                     = 0x18,
++	IH_PERF_SEL_CLIENT9_IH_STALL                     = 0x19,
++	IH_PERF_SEL_CLIENT10_IH_STALL                    = 0x1a,
++	IH_PERF_SEL_CLIENT11_IH_STALL                    = 0x1b,
++	IH_PERF_SEL_CLIENT12_IH_STALL                    = 0x1c,
++	IH_PERF_SEL_CLIENT13_IH_STALL                    = 0x1d,
++	IH_PERF_SEL_CLIENT14_IH_STALL                    = 0x1e,
++	IH_PERF_SEL_CLIENT15_IH_STALL                    = 0x1f,
++	IH_PERF_SEL_CLIENT16_IH_STALL                    = 0x20,
++	IH_PERF_SEL_CLIENT17_IH_STALL                    = 0x21,
++	IH_PERF_SEL_CLIENT18_IH_STALL                    = 0x22,
++	IH_PERF_SEL_CLIENT19_IH_STALL                    = 0x23,
++	IH_PERF_SEL_CLIENT20_IH_STALL                    = 0x24,
++	IH_PERF_SEL_CLIENT21_IH_STALL                    = 0x25,
++} IH_PERF_SEL;
++typedef enum SRBM_PERFCOUNT1_SEL {
++	SRBM_PERF_SEL_COUNT                              = 0x0,
++	SRBM_PERF_SEL_BIF_BUSY                           = 0x1,
++	SRBM_PERF_SEL_SDMA0_BUSY                         = 0x3,
++	SRBM_PERF_SEL_IH_BUSY                            = 0x4,
++	SRBM_PERF_SEL_MCB_BUSY                           = 0x5,
++	SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY               = 0x6,
++	SRBM_PERF_SEL_MCC_BUSY                           = 0x7,
++	SRBM_PERF_SEL_MCD_BUSY                           = 0x8,
++	SRBM_PERF_SEL_CHUB_BUSY                          = 0x9,
++	SRBM_PERF_SEL_SEM_BUSY                           = 0xa,
++	SRBM_PERF_SEL_UVD_BUSY                           = 0xb,
++	SRBM_PERF_SEL_VMC_BUSY                           = 0xc,
++	SRBM_PERF_SEL_XSP_BUSY                           = 0xd,
++	SRBM_PERF_SEL_SDMA1_BUSY                         = 0xe,
++	SRBM_PERF_SEL_SAMMSP_BUSY                        = 0xf,
++	SRBM_PERF_SEL_VCE0_BUSY                          = 0x10,
++	SRBM_PERF_SEL_XDMA_BUSY                          = 0x11,
++	SRBM_PERF_SEL_ACP_BUSY                           = 0x12,
++	SRBM_PERF_SEL_SDMA2_BUSY                         = 0x13,
++	SRBM_PERF_SEL_SDMA3_BUSY                         = 0x14,
++	SRBM_PERF_SEL_SAMSCP_BUSY                        = 0x15,
++	SRBM_PERF_SEL_VMC1_BUSY                          = 0x16,
++	SRBM_PERF_SEL_ISP_BUSY                           = 0x17,
++	SRBM_PERF_SEL_VCE1_BUSY                          = 0x18,
++	SRBM_PERF_SEL_GCATCL2_BUSY                       = 0x19,
++	SRBM_PERF_SEL_OSATCL2_BUSY                       = 0x1a,
++} SRBM_PERFCOUNT1_SEL;
++typedef enum SYS_GRBM_GFX_INDEX_SEL {
++	GRBM_GFX_INDEX_BIF                               = 0x0,
++	GRBM_GFX_INDEX_SDMA0                             = 0x1,
++	GRBM_GFX_INDEX_SDMA1                             = 0x2,
++	RESEVERED0                                       = 0x3,
++	GRBM_GFX_INDEX_UVD                               = 0x4,
++	GRBM_GFX_INDEX_VCE0                              = 0x5,
++	GRBM_GFX_INDEX_VCE1                              = 0x6,
++	GRBM_GFX_INDEX_ACP                               = 0x7,
++	GRBM_GFX_INDEX_SMU                               = 0x8,
++	GRBM_GFX_INDEX_SAMMSP                            = 0x9,
++	GRBM_GFX_INDEX_SAMSCP                            = 0xa,
++	GRBM_GFX_INDEX_ISP                               = 0xb,
++	GRBM_GFX_INDEX_TST                               = 0xc,
++	GRBM_GFX_INDEX_SDMA2                             = 0xd,
++	GRBM_GFX_INDEX_SDMA3                             = 0xe,
++} SYS_GRBM_GFX_INDEX_SEL;
++typedef enum SRBM_GFX_CNTL_SEL {
++	SRBM_GFX_CNTL_BIF                                = 0x0,
++	SRBM_GFX_CNTL_SDMA0                              = 0x1,
++	SRBM_GFX_CNTL_SDMA1                              = 0x2,
++	SRBM_GFX_CNTL_GRBM                               = 0x3,
++	SRBM_GFX_CNTL_UVD                                = 0x4,
++	SRBM_GFX_CNTL_VCE0                               = 0x5,
++	SRBM_GFX_CNTL_VCE1                               = 0x6,
++	SRBM_GFX_CNTL_ACP                                = 0x7,
++	SRBM_GFX_CNTL_SMU                                = 0x8,
++	SRBM_GFX_CNTL_SAMMSP                             = 0x9,
++	SRBM_GFX_CNTL_SAMSCP                             = 0xa,
++	SRBM_GFX_CNTL_ISP                                = 0xb,
++	SRBM_GFX_CNTL_TST                                = 0xc,
++	SRBM_GFX_CNTL_SDMA2                              = 0xd,
++	SRBM_GFX_CNTL_SDMA3                              = 0xe,
++} SRBM_GFX_CNTL_SEL;
++typedef enum SDMA_PERF_SEL {
++	SDMA_PERF_SEL_CYCLE                              = 0x0,
++	SDMA_PERF_SEL_IDLE                               = 0x1,
++	SDMA_PERF_SEL_REG_IDLE                           = 0x2,
++	SDMA_PERF_SEL_RB_EMPTY                           = 0x3,
++	SDMA_PERF_SEL_RB_FULL                            = 0x4,
++	SDMA_PERF_SEL_RB_WPTR_WRAP                       = 0x5,
++	SDMA_PERF_SEL_RB_RPTR_WRAP                       = 0x6,
++	SDMA_PERF_SEL_RB_WPTR_POLL_READ                  = 0x7,
++	SDMA_PERF_SEL_RB_RPTR_WB                         = 0x8,
++	SDMA_PERF_SEL_RB_CMD_IDLE                        = 0x9,
++	SDMA_PERF_SEL_RB_CMD_FULL                        = 0xa,
++	SDMA_PERF_SEL_IB_CMD_IDLE                        = 0xb,
++	SDMA_PERF_SEL_IB_CMD_FULL                        = 0xc,
++	SDMA_PERF_SEL_EX_IDLE                            = 0xd,
++	SDMA_PERF_SEL_SRBM_REG_SEND                      = 0xe,
++	SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE          = 0xf,
++	SDMA_PERF_SEL_MC_WR_IDLE                         = 0x10,
++	SDMA_PERF_SEL_MC_WR_COUNT                        = 0x11,
++	SDMA_PERF_SEL_MC_RD_IDLE                         = 0x12,
++	SDMA_PERF_SEL_MC_RD_COUNT                        = 0x13,
++	SDMA_PERF_SEL_MC_RD_RET_STALL                    = 0x14,
++	SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE                 = 0x15,
++	SDMA_PERF_SEL_SEM_IDLE                           = 0x18,
++	SDMA_PERF_SEL_SEM_REQ_STALL                      = 0x19,
++	SDMA_PERF_SEL_SEM_REQ_COUNT                      = 0x1a,
++	SDMA_PERF_SEL_SEM_RESP_INCOMPLETE                = 0x1b,
++	SDMA_PERF_SEL_SEM_RESP_FAIL                      = 0x1c,
++	SDMA_PERF_SEL_SEM_RESP_PASS                      = 0x1d,
++	SDMA_PERF_SEL_INT_IDLE                           = 0x1e,
++	SDMA_PERF_SEL_INT_REQ_STALL                      = 0x1f,
++	SDMA_PERF_SEL_INT_REQ_COUNT                      = 0x20,
++	SDMA_PERF_SEL_INT_RESP_ACCEPTED                  = 0x21,
++	SDMA_PERF_SEL_INT_RESP_RETRY                     = 0x22,
++	SDMA_PERF_SEL_NUM_PACKET                         = 0x23,
++	SDMA_PERF_SEL_CE_WREQ_IDLE                       = 0x25,
++	SDMA_PERF_SEL_CE_WR_IDLE                         = 0x26,
++	SDMA_PERF_SEL_CE_SPLIT_IDLE                      = 0x27,
++	SDMA_PERF_SEL_CE_RREQ_IDLE                       = 0x28,
++	SDMA_PERF_SEL_CE_OUT_IDLE                        = 0x29,
++	SDMA_PERF_SEL_CE_IN_IDLE                         = 0x2a,
++	SDMA_PERF_SEL_CE_DST_IDLE                        = 0x2b,
++	SDMA_PERF_SEL_CE_AFIFO_FULL                      = 0x2e,
++	SDMA_PERF_SEL_CE_INFO_FULL                       = 0x31,
++	SDMA_PERF_SEL_CE_INFO1_FULL                      = 0x32,
++	SDMA_PERF_SEL_CE_RD_STALL                        = 0x33,
++	SDMA_PERF_SEL_CE_WR_STALL                        = 0x34,
++	SDMA_PERF_SEL_GFX_SELECT                         = 0x35,
++	SDMA_PERF_SEL_RLC0_SELECT                        = 0x36,
++	SDMA_PERF_SEL_RLC1_SELECT                        = 0x37,
++	SDMA_PERF_SEL_CTX_CHANGE                         = 0x38,
++	SDMA_PERF_SEL_CTX_CHANGE_EXPIRED                 = 0x39,
++	SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION               = 0x3a,
++	SDMA_PERF_SEL_DOORBELL                           = 0x3b,
++	SDMA_PERF_SEL_RD_BA_RTR                          = 0x3c,
++	SDMA_PERF_SEL_WR_BA_RTR                          = 0x3d,
++} SDMA_PERF_SEL;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x2,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x3,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x4,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x5,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x6,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x7,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x8,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x9,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xc,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xd,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0xe,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0xf,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x10,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x11,
++	DBG_CLIENT_BLKID_vcea_0                          = 0x12,
++	DBG_CLIENT_BLKID_vcea_1                          = 0x13,
++	DBG_CLIENT_BLKID_vcea_2                          = 0x14,
++	DBG_CLIENT_BLKID_vcea_3                          = 0x15,
++	DBG_CLIENT_BLKID_vceb_0                          = 0x16,
++	DBG_CLIENT_BLKID_vcec_0                          = 0x17,
++	DBG_CLIENT_BLKID_dco                             = 0x18,
++	DBG_CLIENT_BLKID_xdma                            = 0x19,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x1a,
++	DBG_CLIENT_BLKID_smu_0                           = 0x1b,
++	DBG_CLIENT_BLKID_smu_1                           = 0x1c,
++	DBG_CLIENT_BLKID_smu_2                           = 0x1d,
++	DBG_CLIENT_BLKID_gck                             = 0x1e,
++	DBG_CLIENT_BLKID_tmonw0                          = 0x1f,
++	DBG_CLIENT_BLKID_tmonw1                          = 0x20,
++	DBG_CLIENT_BLKID_grbm                            = 0x21,
++	DBG_CLIENT_BLKID_rlc                             = 0x22,
++	DBG_CLIENT_BLKID_ds0                             = 0x23,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x24,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x25,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x26,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x27,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x29,
++	DBG_CLIENT_BLKID_scf0                            = 0x2a,
++	DBG_CLIENT_BLKID_scf1                            = 0x2b,
++	DBG_CLIENT_BLKID_scf2                            = 0x2c,
++	DBG_CLIENT_BLKID_scf3                            = 0x2d,
++	DBG_CLIENT_BLKID_pc0                             = 0x2e,
++	DBG_CLIENT_BLKID_pc1                             = 0x2f,
++	DBG_CLIENT_BLKID_pc2                             = 0x30,
++	DBG_CLIENT_BLKID_pc3                             = 0x31,
++	DBG_CLIENT_BLKID_vgt0                            = 0x32,
++	DBG_CLIENT_BLKID_vgt1                            = 0x33,
++	DBG_CLIENT_BLKID_vgt2                            = 0x34,
++	DBG_CLIENT_BLKID_vgt3                            = 0x35,
++	DBG_CLIENT_BLKID_sx00                            = 0x36,
++	DBG_CLIENT_BLKID_sx10                            = 0x37,
++	DBG_CLIENT_BLKID_sx20                            = 0x38,
++	DBG_CLIENT_BLKID_sx30                            = 0x39,
++	DBG_CLIENT_BLKID_cb001                           = 0x3a,
++	DBG_CLIENT_BLKID_cb200                           = 0x3b,
++	DBG_CLIENT_BLKID_cb201                           = 0x3c,
++	DBG_CLIENT_BLKID_cbr0                            = 0x3d,
++	DBG_CLIENT_BLKID_cb000                           = 0x3e,
++	DBG_CLIENT_BLKID_cb101                           = 0x3f,
++	DBG_CLIENT_BLKID_cb300                           = 0x40,
++	DBG_CLIENT_BLKID_cb301                           = 0x41,
++	DBG_CLIENT_BLKID_cbr1                            = 0x42,
++	DBG_CLIENT_BLKID_cb100                           = 0x43,
++	DBG_CLIENT_BLKID_ia0                             = 0x44,
++	DBG_CLIENT_BLKID_ia1                             = 0x45,
++	DBG_CLIENT_BLKID_bci0                            = 0x46,
++	DBG_CLIENT_BLKID_bci1                            = 0x47,
++	DBG_CLIENT_BLKID_bci2                            = 0x48,
++	DBG_CLIENT_BLKID_bci3                            = 0x49,
++	DBG_CLIENT_BLKID_pa0                             = 0x4a,
++	DBG_CLIENT_BLKID_pa1                             = 0x4b,
++	DBG_CLIENT_BLKID_spim0                           = 0x4c,
++	DBG_CLIENT_BLKID_spim1                           = 0x4d,
++	DBG_CLIENT_BLKID_spim2                           = 0x4e,
++	DBG_CLIENT_BLKID_spim3                           = 0x4f,
++	DBG_CLIENT_BLKID_sdma                            = 0x50,
++	DBG_CLIENT_BLKID_ih                              = 0x51,
++	DBG_CLIENT_BLKID_sem                             = 0x52,
++	DBG_CLIENT_BLKID_srbm                            = 0x53,
++	DBG_CLIENT_BLKID_hdp                             = 0x54,
++	DBG_CLIENT_BLKID_acp_0                           = 0x55,
++	DBG_CLIENT_BLKID_acp_1                           = 0x56,
++	DBG_CLIENT_BLKID_sam                             = 0x57,
++	DBG_CLIENT_BLKID_mcc0                            = 0x58,
++	DBG_CLIENT_BLKID_mcc1                            = 0x59,
++	DBG_CLIENT_BLKID_mcc2                            = 0x5a,
++	DBG_CLIENT_BLKID_mcc3                            = 0x5b,
++	DBG_CLIENT_BLKID_mcd0                            = 0x5c,
++	DBG_CLIENT_BLKID_mcd1                            = 0x5d,
++	DBG_CLIENT_BLKID_mcd2                            = 0x5e,
++	DBG_CLIENT_BLKID_mcd3                            = 0x5f,
++	DBG_CLIENT_BLKID_mcb                             = 0x60,
++	DBG_CLIENT_BLKID_vmc                             = 0x61,
++	DBG_CLIENT_BLKID_gmcon                           = 0x62,
++	DBG_CLIENT_BLKID_gdc_0                           = 0x63,
++	DBG_CLIENT_BLKID_gdc_1                           = 0x64,
++	DBG_CLIENT_BLKID_gdc_2                           = 0x65,
++	DBG_CLIENT_BLKID_gdc_3                           = 0x66,
++	DBG_CLIENT_BLKID_gdc_4                           = 0x67,
++	DBG_CLIENT_BLKID_gdc_5                           = 0x68,
++	DBG_CLIENT_BLKID_gdc_6                           = 0x69,
++	DBG_CLIENT_BLKID_gdc_7                           = 0x6a,
++	DBG_CLIENT_BLKID_gdc_8                           = 0x6b,
++	DBG_CLIENT_BLKID_gdc_9                           = 0x6c,
++	DBG_CLIENT_BLKID_gdc_10                          = 0x6d,
++	DBG_CLIENT_BLKID_gdc_11                          = 0x6e,
++	DBG_CLIENT_BLKID_gdc_12                          = 0x6f,
++	DBG_CLIENT_BLKID_gdc_13                          = 0x70,
++	DBG_CLIENT_BLKID_gdc_14                          = 0x71,
++	DBG_CLIENT_BLKID_gdc_15                          = 0x72,
++	DBG_CLIENT_BLKID_gdc_16                          = 0x73,
++	DBG_CLIENT_BLKID_gdc_17                          = 0x74,
++	DBG_CLIENT_BLKID_gdc_18                          = 0x75,
++	DBG_CLIENT_BLKID_gdc_19                          = 0x76,
++	DBG_CLIENT_BLKID_gdc_20                          = 0x77,
++	DBG_CLIENT_BLKID_gdc_21                          = 0x78,
++	DBG_CLIENT_BLKID_gdc_22                          = 0x79,
++	DBG_CLIENT_BLKID_gdc_23                          = 0x7a,
++	DBG_CLIENT_BLKID_gdc_24                          = 0x7b,
++	DBG_CLIENT_BLKID_gdc_25                          = 0x7c,
++	DBG_CLIENT_BLKID_gdc_26                          = 0x7d,
++	DBG_CLIENT_BLKID_gdc_27                          = 0x7e,
++	DBG_CLIENT_BLKID_gdc_28                          = 0x7f,
++	DBG_CLIENT_BLKID_wd                              = 0x80,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x81,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x82,
++	DBG_CLIENT_BLKID_sammsp                          = 0x83,
++	DBG_CLIENT_BLKID_dci_0                           = 0x84,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x85,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x86,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x87,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x88,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x89,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++
++#endif /* OSS_2_4_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h
+new file mode 100644
+index 0000000..413af7d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h
+@@ -0,0 +1,2544 @@
++/*
++ * OSS_2_4 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_2_4_SH_MASK_H
++#define OSS_2_4_SH_MASK_H
++
++#define IH_VMID_0_LUT__PASID_MASK 0xffff
++#define IH_VMID_0_LUT__PASID__SHIFT 0x0
++#define IH_VMID_1_LUT__PASID_MASK 0xffff
++#define IH_VMID_1_LUT__PASID__SHIFT 0x0
++#define IH_VMID_2_LUT__PASID_MASK 0xffff
++#define IH_VMID_2_LUT__PASID__SHIFT 0x0
++#define IH_VMID_3_LUT__PASID_MASK 0xffff
++#define IH_VMID_3_LUT__PASID__SHIFT 0x0
++#define IH_VMID_4_LUT__PASID_MASK 0xffff
++#define IH_VMID_4_LUT__PASID__SHIFT 0x0
++#define IH_VMID_5_LUT__PASID_MASK 0xffff
++#define IH_VMID_5_LUT__PASID__SHIFT 0x0
++#define IH_VMID_6_LUT__PASID_MASK 0xffff
++#define IH_VMID_6_LUT__PASID__SHIFT 0x0
++#define IH_VMID_7_LUT__PASID_MASK 0xffff
++#define IH_VMID_7_LUT__PASID__SHIFT 0x0
++#define IH_VMID_8_LUT__PASID_MASK 0xffff
++#define IH_VMID_8_LUT__PASID__SHIFT 0x0
++#define IH_VMID_9_LUT__PASID_MASK 0xffff
++#define IH_VMID_9_LUT__PASID__SHIFT 0x0
++#define IH_VMID_10_LUT__PASID_MASK 0xffff
++#define IH_VMID_10_LUT__PASID__SHIFT 0x0
++#define IH_VMID_11_LUT__PASID_MASK 0xffff
++#define IH_VMID_11_LUT__PASID__SHIFT 0x0
++#define IH_VMID_12_LUT__PASID_MASK 0xffff
++#define IH_VMID_12_LUT__PASID__SHIFT 0x0
++#define IH_VMID_13_LUT__PASID_MASK 0xffff
++#define IH_VMID_13_LUT__PASID__SHIFT 0x0
++#define IH_VMID_14_LUT__PASID_MASK 0xffff
++#define IH_VMID_14_LUT__PASID__SHIFT 0x0
++#define IH_VMID_15_LUT__PASID_MASK 0xffff
++#define IH_VMID_15_LUT__PASID__SHIFT 0x0
++#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
++#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define IH_RB_BASE__ADDR_MASK 0xffffffff
++#define IH_RB_BASE__ADDR__SHIFT 0x0
++#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_RPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
++#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_WPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
++#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
++#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
++#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define IH_CNTL__ENABLE_INTR_MASK 0x1
++#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
++#define IH_CNTL__MC_SWAP_MASK 0x6
++#define IH_CNTL__MC_SWAP__SHIFT 0x1
++#define IH_CNTL__RPTR_REARM_MASK 0x10
++#define IH_CNTL__RPTR_REARM__SHIFT 0x4
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
++#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
++#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
++#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
++#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
++#define IH_CNTL__MC_VMID_MASK 0x1e000000
++#define IH_CNTL__MC_VMID__SHIFT 0x19
++#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
++#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
++#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
++#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
++#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
++#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
++#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
++#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
++#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
++#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
++#define IH_STATUS__IDLE_MASK 0x1
++#define IH_STATUS__IDLE__SHIFT 0x0
++#define IH_STATUS__INPUT_IDLE_MASK 0x2
++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
++#define IH_STATUS__RB_IDLE_MASK 0x4
++#define IH_STATUS__RB_IDLE__SHIFT 0x2
++#define IH_STATUS__RB_FULL_MASK 0x8
++#define IH_STATUS__RB_FULL__SHIFT 0x3
++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
++#define IH_STATUS__RB_OVERFLOW_MASK 0x20
++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
++#define IH_STATUS__MC_WR_IDLE_MASK 0x40
++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
++#define IH_STATUS__MC_WR_STALL_MASK 0x80
++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
++#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
++#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
++#define IH_VERSION__VALUE_MASK 0xfff
++#define IH_VERSION__VALUE__SHIFT 0x0
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
++#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
++#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
++#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
++#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
++#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
++#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
++#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
++#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
++#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
++#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
++#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
++#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
++#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
++#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
++#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
++#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
++#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00
++#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8
++#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000
++#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10
++#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00
++#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8
++#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000
++#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10
++#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00
++#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8
++#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000
++#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10
++#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00
++#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8
++#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000
++#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10
++#define SEM_STATUS__SEM_IDLE_MASK 0x1
++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
++#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
++#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
++#define SEM_MAILBOX__SIDEPORT_MASK 0xff
++#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
++#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
++#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
++#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
++#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
++#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
++#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
++#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
++#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
++#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
++#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
++#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
++#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL__MEID_MASK 0xc
++#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
++#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
++#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
++#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
++#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
++#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS2__XSP_BUSY_MASK 0x10
++#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4
++#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
++#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
++#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
++#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
++#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
++#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
++#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
++#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
++#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
++#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
++#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
++#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
++#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
++#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
++#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000
++#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc
++#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
++#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
++#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
++#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
++#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
++#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
++#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
++#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
++#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000
++#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12
++#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
++#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
++#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
++#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
++#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
++#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
++#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
++#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
++#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
++#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
++#define SRBM_STATUS__VMC_BUSY_MASK 0x100
++#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
++#define SRBM_STATUS__MCB_BUSY_MASK 0x200
++#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
++#define SRBM_STATUS__MCC_BUSY_MASK 0x800
++#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
++#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
++#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
++#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
++#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
++#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
++#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
++#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
++#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
++#define SRBM_STATUS__IH_BUSY_MASK 0x20000
++#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
++#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
++#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
++#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
++#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
++#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
++#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
++#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
++#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
++#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
++#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
++#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
++#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
++#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
++#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
++#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
++#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
++#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
++#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
++#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
++#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
++#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
++#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
++#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
++#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
++#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
++#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
++#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
++#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
++#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
++#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
++#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
++#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
++#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
++#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
++#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
++#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
++#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
++#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
++#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
++#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
++#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
++#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
++#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
++#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
++#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
++#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
++#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
++#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
++#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000
++#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
++#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
++#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
++#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000
++#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c
++#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
++#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
++#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
++#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
++#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
++#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
++#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
++#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
++#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
++#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
++#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400
++#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
++#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000
++#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
++#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000
++#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e
++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
++#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
++#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
++#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
++#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
++#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
++#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
++#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
++#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
++#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
++#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
++#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
++#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
++#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
++#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
++#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
++#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
++#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
++#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
++#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
++#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
++#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
++#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
++#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
++#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
++#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
++#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
++#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SDMA0_UCODE_ADDR__VALUE_MASK 0xfff
++#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA0_HASH__BANK_BITS_MASK 0x70
++#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA0_STATUS_REG__IDLE_MASK 0x1
++#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
++#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
++#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_F32_CNTL__HALT_MASK 0x1
++#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA0_F32_CNTL__STEP_MASK 0x2
++#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
++#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
++#define SDMA0_FREEZE__FREEZE_MASK 0x10
++#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA0_FREEZE__FROZEN_MASK 0x20
++#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
++#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
++#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
++#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
++#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
++#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
++#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
++#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
++#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
++#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
++#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
++#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
++#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
++#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
++#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
++#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
++#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
++#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
++#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
++#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
++#define SDMA0_ID__DEVICE_ID_MASK 0xff
++#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
++#define SDMA0_VERSION__VALUE_MASK 0xffff
++#define SDMA0_VERSION__VALUE__SHIFT 0x0
++#define SDMA0_STATUS2_REG__ID_MASK 0x3
++#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
++#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
++#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
++#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
++#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_UCODE_ADDR__VALUE_MASK 0xfff
++#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA1_HASH__BANK_BITS_MASK 0x70
++#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA1_STATUS_REG__IDLE_MASK 0x1
++#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
++#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
++#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_F32_CNTL__HALT_MASK 0x1
++#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA1_F32_CNTL__STEP_MASK 0x2
++#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
++#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
++#define SDMA1_FREEZE__FREEZE_MASK 0x10
++#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA1_FREEZE__FROZEN_MASK 0x20
++#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
++#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
++#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
++#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
++#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
++#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
++#define SDMA1_ID__DEVICE_ID_MASK 0xff
++#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
++#define SDMA1_VERSION__VALUE_MASK 0xffff
++#define SDMA1_VERSION__VALUE__SHIFT 0x0
++#define SDMA1_STATUS2_REG__ID_MASK 0x3
++#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
++#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
++#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
++#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
++#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
++#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
++#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
++#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
++#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
++#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
++#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
++#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
++#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
++#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
++#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
++#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
++#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
++#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
++#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
++#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
++#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
++#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
++#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
++#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
++#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
++#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
++#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
++#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
++#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
++#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
++#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
++#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
++#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
++#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
++#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
++#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
++#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
++#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
++#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
++#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
++#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
++#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
++#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
++#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
++#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
++#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
++#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
++#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
++#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
++#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
++#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
++#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
++#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
++#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
++#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
++#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
++#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
++#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
++#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
++#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
++
++#endif /* OSS_2_4_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch
new file mode 100644
index 00000000..f793147c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch
@@ -0,0 +1,5877 @@
+From fe8e4443319e4c3f6fdefe2c9c3da2e4cd38867d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:27:33 -0400
+Subject: drm/amdgpu: add OSS 3.0 register headers
+
+These are register headers for the OSS (OS Services)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h
+new file mode 100644
+index 0000000..f56c68b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h
+@@ -0,0 +1,688 @@
++/*
++ * OSS_3_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_3_0_D_H
++#define OSS_3_0_D_H
++
++#define mmIH_VMID_0_LUT                                                         0xe00
++#define mmIH_VMID_1_LUT                                                         0xe01
++#define mmIH_VMID_2_LUT                                                         0xe02
++#define mmIH_VMID_3_LUT                                                         0xe03
++#define mmIH_VMID_4_LUT                                                         0xe04
++#define mmIH_VMID_5_LUT                                                         0xe05
++#define mmIH_VMID_6_LUT                                                         0xe06
++#define mmIH_VMID_7_LUT                                                         0xe07
++#define mmIH_VMID_8_LUT                                                         0xe08
++#define mmIH_VMID_9_LUT                                                         0xe09
++#define mmIH_VMID_10_LUT                                                        0xe0a
++#define mmIH_VMID_11_LUT                                                        0xe0b
++#define mmIH_VMID_12_LUT                                                        0xe0c
++#define mmIH_VMID_13_LUT                                                        0xe0d
++#define mmIH_VMID_14_LUT                                                        0xe0e
++#define mmIH_VMID_15_LUT                                                        0xe0f
++#define mmIH_RB_CNTL                                                            0xe30
++#define mmIH_RB_BASE                                                            0xe31
++#define mmIH_RB_RPTR                                                            0xe32
++#define mmIH_RB_WPTR                                                            0xe33
++#define mmIH_RB_WPTR_ADDR_HI                                                    0xe34
++#define mmIH_RB_WPTR_ADDR_LO                                                    0xe35
++#define mmIH_CNTL                                                               0xe36
++#define mmIH_LEVEL_STATUS                                                       0xe37
++#define mmIH_STATUS                                                             0xe38
++#define mmIH_PERFMON_CNTL                                                       0xe39
++#define mmIH_PERFCOUNTER0_RESULT                                                0xe3a
++#define mmIH_PERFCOUNTER1_RESULT                                                0xe3b
++#define mmIH_DEBUG                                                              0xe3c
++#define mmIH_DSM_MATCH_VALUE_BIT_31_0                                           0xe3d
++#define mmIH_DSM_MATCH_VALUE_BIT_63_32                                          0xe3e
++#define mmIH_DSM_MATCH_VALUE_BIT_95_64                                          0xe3f
++#define mmIH_DSM_MATCH_FIELD_CONTROL                                            0xe40
++#define mmIH_DSM_MATCH_DATA_CONTROL                                             0xe41
++#define mmIH_DOORBELL_RPTR                                                      0xe42
++#define mmIH_ACTIVE_FCN_ID                                                      0xe43
++#define mmIH_VF_RB_STATUS                                                       0xe44
++#define mmIH_VF_ENABLE                                                          0xe45
++#define mmIH_VIRT_RESET_REQ                                                     0xe46
++#define mmIH_VF_RB_BIF_STATUS                                                   0xe47
++#define mmIH_VERSION                                                            0xe48
++#define mmIH_LEVEL_INTR_MASK                                                    0xe49
++#define mmIH_RESET_INCOMPLETE_INT_CNTL                                          0xe4a
++#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT                                     0xe4b
++#define mmSEM_MCIF_CONFIG                                                       0xf90
++#define mmSDMA_CONFIG                                                           0xf91
++#define mmSDMA1_CONFIG                                                          0xf92
++#define mmUVD_CONFIG                                                            0xf93
++#define mmVCE_CONFIG                                                            0xf94
++#define mmSEM_VF_ENABLE                                                         0xf95
++#define mmCP_CONFIG                                                             0xf96
++#define mmSEM_ACTIVE_FCN_ID                                                     0xf97
++#define mmSEM_VIRT_RESET_REQ                                                    0xf98
++#define mmSEM_STATUS                                                            0xf99
++#define mmSEM_EDC_CONFIG                                                        0xf9a
++#define mmSEM_MAILBOX_CLIENTCONFIG                                              0xf9b
++#define mmSEM_MAILBOX                                                           0xf9c
++#define mmSEM_MAILBOX_CONTROL                                                   0xf9d
++#define mmSEM_CHICKEN_BITS                                                      0xf9e
++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA                                        0xf9f
++#define mmSRBM_CNTL                                                             0x390
++#define mmSRBM_GFX_CNTL                                                         0x391
++#define mmSRBM_READ_CNTL                                                        0x392
++#define mmSRBM_STATUS2                                                          0x393
++#define mmSRBM_STATUS                                                           0x394
++#define mmSRBM_STATUS3                                                          0x395
++#define mmSRBM_SOFT_RESET                                                       0x398
++#define mmSRBM_DEBUG_CNTL                                                       0x399
++#define mmSRBM_DEBUG_DATA                                                       0x39a
++#define mmSRBM_CHIP_REVISION                                                    0x39b
++#define mmSRBM_CREDIT_RECOVER_CNTL                                              0x39c
++#define mmSRBM_CREDIT_RECOVER                                                   0x39d
++#define mmSRBM_CREDIT_RESET                                                     0x39e
++#define mmCC_SYS_RB_REDUNDANCY                                                  0x39f
++#define mmCC_SYS_RB_BACKEND_DISABLE                                             0x3a0
++#define mmGC_USER_SYS_RB_BACKEND_DISABLE                                        0x3a1
++#define mmSRBM_MC_CLKEN_CNTL                                                    0x3b3
++#define mmSRBM_SYS_CLKEN_CNTL                                                   0x3b4
++#define mmSRBM_VCE_CLKEN_CNTL                                                   0x3b5
++#define mmSRBM_UVD_CLKEN_CNTL                                                   0x3b6
++#define mmSRBM_SDMA_CLKEN_CNTL                                                  0x3b7
++#define mmSRBM_SAM_CLKEN_CNTL                                                   0x3b8
++#define mmSRBM_ISP_CLKEN_CNTL                                                   0x3b9
++#define mmSRBM_VP8_CLKEN_CNTL                                                   0x3ba
++#define mmSRBM_DEBUG                                                            0x3a4
++#define mmSRBM_DEBUG_SNAPSHOT                                                   0x3a5
++#define mmSRBM_DEBUG_SNAPSHOT2                                                  0x3ad
++#define mmSRBM_READ_ERROR                                                       0x3a6
++#define mmSRBM_READ_ERROR2                                                      0x3ae
++#define mmSRBM_INT_CNTL                                                         0x3a8
++#define mmSRBM_INT_STATUS                                                       0x3a9
++#define mmSRBM_INT_ACK                                                          0x3aa
++#define mmSRBM_FIREWALL_ERROR_SRC                                               0x3ab
++#define mmSRBM_FIREWALL_ERROR_ADDR                                              0x3ac
++#define mmSRBM_DSM_TRIG_CNTL0                                                   0x3af
++#define mmSRBM_DSM_TRIG_CNTL1                                                   0x3b0
++#define mmSRBM_DSM_TRIG_MASK0                                                   0x3b1
++#define mmSRBM_DSM_TRIG_MASK1                                                   0x3b2
++#define mmSRBM_PERFMON_CNTL                                                     0x7c00
++#define mmSRBM_PERFCOUNTER0_SELECT                                              0x7c01
++#define mmSRBM_PERFCOUNTER1_SELECT                                              0x7c02
++#define mmSRBM_PERFCOUNTER0_LO                                                  0x7c03
++#define mmSRBM_PERFCOUNTER0_HI                                                  0x7c04
++#define mmSRBM_PERFCOUNTER1_LO                                                  0x7c05
++#define mmSRBM_PERFCOUNTER1_HI                                                  0x7c06
++#define mmSRBM_CAM_INDEX                                                        0xfe34
++#define mmSRBM_CAM_DATA                                                         0xfe35
++#define mmSRBM_MC_DOMAIN_ADDR0                                                  0xfa00
++#define mmSRBM_MC_DOMAIN_ADDR1                                                  0xfa01
++#define mmSRBM_MC_DOMAIN_ADDR2                                                  0xfa02
++#define mmSRBM_MC_DOMAIN_ADDR3                                                  0xfa03
++#define mmSRBM_MC_DOMAIN_ADDR4                                                  0xfa04
++#define mmSRBM_MC_DOMAIN_ADDR5                                                  0xfa05
++#define mmSRBM_MC_DOMAIN_ADDR6                                                  0xfa06
++#define mmSRBM_SYS_DOMAIN_ADDR0                                                 0xfa08
++#define mmSRBM_SYS_DOMAIN_ADDR1                                                 0xfa09
++#define mmSRBM_SYS_DOMAIN_ADDR2                                                 0xfa0a
++#define mmSRBM_SYS_DOMAIN_ADDR3                                                 0xfa0b
++#define mmSRBM_SYS_DOMAIN_ADDR4                                                 0xfa0c
++#define mmSRBM_SYS_DOMAIN_ADDR5                                                 0xfa0d
++#define mmSRBM_SYS_DOMAIN_ADDR6                                                 0xfa0e
++#define mmSRBM_SDMA_DOMAIN_ADDR0                                                0xfa10
++#define mmSRBM_SDMA_DOMAIN_ADDR1                                                0xfa11
++#define mmSRBM_SDMA_DOMAIN_ADDR2                                                0xfa12
++#define mmSRBM_SDMA_DOMAIN_ADDR3                                                0xfa13
++#define mmSRBM_UVD_DOMAIN_ADDR0                                                 0xfa14
++#define mmSRBM_UVD_DOMAIN_ADDR1                                                 0xfa15
++#define mmSRBM_UVD_DOMAIN_ADDR2                                                 0xfa16
++#define mmSRBM_VCE_DOMAIN_ADDR0                                                 0xfa18
++#define mmSRBM_VCE_DOMAIN_ADDR1                                                 0xfa19
++#define mmSRBM_VCE_DOMAIN_ADDR2                                                 0xfa1a
++#define mmSRBM_SAM_DOMAIN_ADDR0                                                 0xfa1c
++#define mmSRBM_SAM_DOMAIN_ADDR1                                                 0xfa1d
++#define mmSRBM_SAM_DOMAIN_ADDR2                                                 0xfa1e
++#define mmSRBM_ISP_DOMAIN_ADDR0                                                 0xfa20
++#define mmSRBM_ISP_DOMAIN_ADDR1                                                 0xfa21
++#define mmSRBM_ISP_DOMAIN_ADDR2                                                 0xfa22
++#define mmSRBM_VP8_DOMAIN_ADDR0                                                 0xfa24
++#define mmSYS_GRBM_GFX_INDEX_SELECT                                             0xfa2c
++#define mmSYS_GRBM_GFX_INDEX_DATA                                               0xfa2d
++#define mmSRBM_GFX_CNTL_SELECT                                                  0xfa2e
++#define mmSRBM_GFX_CNTL_DATA                                                    0xfa2f
++#define mmSRBM_VF_ENABLE                                                        0xfa30
++#define mmSRBM_VIRT_CNTL                                                        0xfa31
++#define mmSRBM_VIRT_RESET_REQ                                                   0xfa32
++#define mmCC_DRM_ID_STRAPS                                                      0x1559
++#define mmCGTT_DRM_CLK_CTRL0                                                    0x1579
++#define ixDH_TEST                                                               0x0
++#define ixKHFS0                                                                 0x4
++#define ixKHFS1                                                                 0x8
++#define ixKHFS2                                                                 0xc
++#define ixKHFS3                                                                 0x10
++#define ixKSESSION0                                                             0x14
++#define ixKSESSION1                                                             0x18
++#define ixKSESSION2                                                             0x1c
++#define ixKSESSION3                                                             0x20
++#define ixKSIG0                                                                 0x24
++#define ixKSIG1                                                                 0x28
++#define ixKSIG2                                                                 0x2c
++#define ixKSIG3                                                                 0x30
++#define ixEXP0                                                                  0x34
++#define ixEXP1                                                                  0x38
++#define ixEXP2                                                                  0x3c
++#define ixEXP3                                                                  0x40
++#define ixEXP4                                                                  0x44
++#define ixEXP5                                                                  0x48
++#define ixEXP6                                                                  0x4c
++#define ixEXP7                                                                  0x50
++#define ixLX0                                                                   0x54
++#define ixLX1                                                                   0x58
++#define ixLX2                                                                   0x5c
++#define ixLX3                                                                   0x60
++#define ixCLIENT2_K0                                                            0x1b4
++#define ixCLIENT2_K1                                                            0x1b8
++#define ixCLIENT2_K2                                                            0x1bc
++#define ixCLIENT2_K3                                                            0x1c0
++#define ixCLIENT2_CK0                                                           0x1c4
++#define ixCLIENT2_CK1                                                           0x1c8
++#define ixCLIENT2_CK2                                                           0x1cc
++#define ixCLIENT2_CK3                                                           0x1d0
++#define ixCLIENT2_CD0                                                           0x1d4
++#define ixCLIENT2_CD1                                                           0x1d8
++#define ixCLIENT2_CD2                                                           0x1dc
++#define ixCLIENT2_CD3                                                           0x1e0
++#define ixCLIENT2_BM                                                            0x1e4
++#define ixCLIENT2_OFFSET                                                        0x1e8
++#define ixCLIENT2_STATUS                                                        0x1ec
++#define ixCLIENT0_K0                                                            0x1f0
++#define ixCLIENT0_K1                                                            0x1f4
++#define ixCLIENT0_K2                                                            0x1f8
++#define ixCLIENT0_K3                                                            0x1fc
++#define ixCLIENT0_CK0                                                           0x200
++#define ixCLIENT0_CK1                                                           0x204
++#define ixCLIENT0_CK2                                                           0x208
++#define ixCLIENT0_CK3                                                           0x20c
++#define ixCLIENT0_CD0                                                           0x210
++#define ixCLIENT0_CD1                                                           0x214
++#define ixCLIENT0_CD2                                                           0x218
++#define ixCLIENT0_CD3                                                           0x21c
++#define ixCLIENT0_BM                                                            0x220
++#define ixCLIENT0_OFFSET                                                        0x224
++#define ixCLIENT0_STATUS                                                        0x228
++#define ixCLIENT1_K0                                                            0x22c
++#define ixCLIENT1_K1                                                            0x230
++#define ixCLIENT1_K2                                                            0x234
++#define ixCLIENT1_K3                                                            0x238
++#define ixCLIENT1_CK0                                                           0x23c
++#define ixCLIENT1_CK1                                                           0x240
++#define ixCLIENT1_CK2                                                           0x244
++#define ixCLIENT1_CK3                                                           0x248
++#define ixCLIENT1_CD0                                                           0x24c
++#define ixCLIENT1_CD1                                                           0x250
++#define ixCLIENT1_CD2                                                           0x254
++#define ixCLIENT1_CD3                                                           0x258
++#define ixCLIENT1_BM                                                            0x25c
++#define ixCLIENT1_OFFSET                                                        0x260
++#define ixCLIENT1_PORT_STATUS                                                   0x264
++#define ixKEFUSE0                                                               0x268
++#define ixKEFUSE1                                                               0x26c
++#define ixKEFUSE2                                                               0x270
++#define ixKEFUSE3                                                               0x274
++#define ixHFS_SEED0                                                             0x278
++#define ixHFS_SEED1                                                             0x27c
++#define ixHFS_SEED2                                                             0x280
++#define ixHFS_SEED3                                                             0x284
++#define ixRINGOSC_MASK                                                          0x288
++#define ixCLIENT0_OFFSET_HI                                                     0x290
++#define ixCLIENT1_OFFSET_HI                                                     0x294
++#define ixCLIENT2_OFFSET_HI                                                     0x298
++#define ixSPU_PORT_STATUS                                                       0x29c
++#define ixCLIENT3_OFFSET_HI                                                     0x2a0
++#define ixCLIENT3_K0                                                            0x2a4
++#define ixCLIENT3_K1                                                            0x2a8
++#define ixCLIENT3_K2                                                            0x2ac
++#define ixCLIENT3_K3                                                            0x2b0
++#define ixCLIENT3_CK0                                                           0x2b4
++#define ixCLIENT3_CK1                                                           0x2b8
++#define ixCLIENT3_CK2                                                           0x2bc
++#define ixCLIENT3_CK3                                                           0x2c0
++#define ixCLIENT3_CD0                                                           0x2c4
++#define ixCLIENT3_CD1                                                           0x2c8
++#define ixCLIENT3_CD2                                                           0x2cc
++#define ixCLIENT3_CD3                                                           0x2d0
++#define ixCLIENT3_BM                                                            0x2d4
++#define ixCLIENT3_OFFSET                                                        0x2d8
++#define ixCLIENT3_STATUS                                                        0x2dc
++#define ixCLIENT4_OFFSET_HI                                                     0x2e0
++#define ixCLIENT4_K0                                                            0x2e4
++#define ixCLIENT4_K1                                                            0x2e8
++#define ixCLIENT4_K2                                                            0x2ec
++#define ixCLIENT4_K3                                                            0x2f0
++#define ixCLIENT4_CK0                                                           0x2f4
++#define ixCLIENT4_CK1                                                           0x2f8
++#define ixCLIENT4_CK2                                                           0x2fc
++#define ixCLIENT4_CK3                                                           0x300
++#define ixCLIENT4_CD0                                                           0x304
++#define ixCLIENT4_CD1                                                           0x308
++#define ixCLIENT4_CD2                                                           0x30c
++#define ixCLIENT4_CD3                                                           0x310
++#define ixCLIENT4_BM                                                            0x314
++#define ixCLIENT4_OFFSET                                                        0x318
++#define ixCLIENT4_STATUS                                                        0x31c
++#define mmDC_TEST_DEBUG_INDEX                                                   0x157c
++#define mmDC_TEST_DEBUG_DATA                                                    0x157d
++#define mmSDMA0_UCODE_ADDR                                                      0x3400
++#define mmSDMA0_UCODE_DATA                                                      0x3401
++#define mmSDMA0_POWER_CNTL                                                      0x3402
++#define mmSDMA0_CLK_CTRL                                                        0x3403
++#define mmSDMA0_CNTL                                                            0x3404
++#define mmSDMA0_CHICKEN_BITS                                                    0x3405
++#define mmSDMA0_TILING_CONFIG                                                   0x3406
++#define mmSDMA0_HASH                                                            0x3407
++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3409
++#define mmSDMA0_RB_RPTR_FETCH                                                   0x340a
++#define mmSDMA0_IB_OFFSET_FETCH                                                 0x340b
++#define mmSDMA0_PROGRAM                                                         0x340c
++#define mmSDMA0_STATUS_REG                                                      0x340d
++#define mmSDMA0_STATUS1_REG                                                     0x340e
++#define mmSDMA0_RD_BURST_CNTL                                                   0x340f
++#define mmSDMA0_PERFMON_CNTL                                                    0x9000
++#define mmSDMA0_PERFCOUNTER0_RESULT                                             0x9001
++#define mmSDMA0_PERFCOUNTER1_RESULT                                             0x9002
++#define mmSDMA0_F32_CNTL                                                        0x3412
++#define mmSDMA0_FREEZE                                                          0x3413
++#define mmSDMA0_PHASE0_QUANTUM                                                  0x3414
++#define mmSDMA0_PHASE1_QUANTUM                                                  0x3415
++#define mmSDMA_POWER_GATING                                                     0x3416
++#define mmSDMA_PGFSM_CONFIG                                                     0x3417
++#define mmSDMA_PGFSM_WRITE                                                      0x3418
++#define mmSDMA_PGFSM_READ                                                       0x3419
++#define mmSDMA0_EDC_CONFIG                                                      0x341a
++#define mmSDMA0_VM_CNTL                                                         0x3420
++#define mmSDMA0_VM_CTX_LO                                                       0x3421
++#define mmSDMA0_VM_CTX_HI                                                       0x3422
++#define mmSDMA0_STATUS2_REG                                                     0x3423
++#define mmSDMA0_ACTIVE_FCN_ID                                                   0x3424
++#define mmSDMA0_VM_CTX_CNTL                                                     0x3425
++#define mmSDMA0_VIRT_RESET_REQ                                                  0x3426
++#define mmSDMA0_VF_ENABLE                                                       0x3427
++#define mmSDMA0_BA_THRESHOLD                                                    0x341b
++#define mmSDMA0_ID                                                              0x341c
++#define mmSDMA0_VERSION                                                         0x341d
++#define mmSDMA0_ATOMIC_CNTL                                                     0x3428
++#define mmSDMA0_ATOMIC_PREOP_LO                                                 0x3429
++#define mmSDMA0_ATOMIC_PREOP_HI                                                 0x342a
++#define mmSDMA0_POWER_CNTL_IDLE                                                 0x342c
++#define mmSDMA0_PERF_REG_TYPE0                                                  0x3477
++#define mmSDMA0_CONTEXT_REG_TYPE0                                               0x3478
++#define mmSDMA0_CONTEXT_REG_TYPE1                                               0x3479
++#define mmSDMA0_CONTEXT_REG_TYPE2                                               0x347a
++#define mmSDMA0_PUB_REG_TYPE0                                                   0x347c
++#define mmSDMA0_PUB_REG_TYPE1                                                   0x347d
++#define mmSDMA0_GFX_RB_CNTL                                                     0x3480
++#define mmSDMA0_GFX_RB_BASE                                                     0x3481
++#define mmSDMA0_GFX_RB_BASE_HI                                                  0x3482
++#define mmSDMA0_GFX_RB_RPTR                                                     0x3483
++#define mmSDMA0_GFX_RB_WPTR                                                     0x3484
++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                           0x3485
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3486
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3487
++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                             0x3488
++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                             0x3489
++#define mmSDMA0_GFX_IB_CNTL                                                     0x348a
++#define mmSDMA0_GFX_IB_RPTR                                                     0x348b
++#define mmSDMA0_GFX_IB_OFFSET                                                   0x348c
++#define mmSDMA0_GFX_IB_BASE_LO                                                  0x348d
++#define mmSDMA0_GFX_IB_BASE_HI                                                  0x348e
++#define mmSDMA0_GFX_IB_SIZE                                                     0x348f
++#define mmSDMA0_GFX_SKIP_CNTL                                                   0x3490
++#define mmSDMA0_GFX_CONTEXT_STATUS                                              0x3491
++#define mmSDMA0_GFX_DOORBELL                                                    0x3492
++#define mmSDMA0_GFX_CONTEXT_CNTL                                                0x3493
++#define mmSDMA0_GFX_VIRTUAL_ADDR                                                0x34a7
++#define mmSDMA0_GFX_APE1_CNTL                                                   0x34a8
++#define mmSDMA0_GFX_DOORBELL_LOG                                                0x34a9
++#define mmSDMA0_GFX_WATERMARK                                                   0x34aa
++#define mmSDMA0_GFX_CSA_ADDR_LO                                                 0x34ac
++#define mmSDMA0_GFX_CSA_ADDR_HI                                                 0x34ad
++#define mmSDMA0_GFX_IB_SUB_REMAIN                                               0x34af
++#define mmSDMA0_GFX_PREEMPT                                                     0x34b0
++#define mmSDMA0_GFX_DUMMY_REG                                                   0x34b1
++#define mmSDMA0_GFX_MIDCMD_DATA0                                                0x34c1
++#define mmSDMA0_GFX_MIDCMD_DATA1                                                0x34c2
++#define mmSDMA0_GFX_MIDCMD_DATA2                                                0x34c3
++#define mmSDMA0_GFX_MIDCMD_DATA3                                                0x34c4
++#define mmSDMA0_GFX_MIDCMD_DATA4                                                0x34c5
++#define mmSDMA0_GFX_MIDCMD_DATA5                                                0x34c6
++#define mmSDMA0_GFX_MIDCMD_CNTL                                                 0x34c7
++#define mmSDMA0_RLC0_RB_CNTL                                                    0x3500
++#define mmSDMA0_RLC0_RB_BASE                                                    0x3501
++#define mmSDMA0_RLC0_RB_BASE_HI                                                 0x3502
++#define mmSDMA0_RLC0_RB_RPTR                                                    0x3503
++#define mmSDMA0_RLC0_RB_WPTR                                                    0x3504
++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                          0x3505
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3506
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3507
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                            0x3508
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                            0x3509
++#define mmSDMA0_RLC0_IB_CNTL                                                    0x350a
++#define mmSDMA0_RLC0_IB_RPTR                                                    0x350b
++#define mmSDMA0_RLC0_IB_OFFSET                                                  0x350c
++#define mmSDMA0_RLC0_IB_BASE_LO                                                 0x350d
++#define mmSDMA0_RLC0_IB_BASE_HI                                                 0x350e
++#define mmSDMA0_RLC0_IB_SIZE                                                    0x350f
++#define mmSDMA0_RLC0_SKIP_CNTL                                                  0x3510
++#define mmSDMA0_RLC0_CONTEXT_STATUS                                             0x3511
++#define mmSDMA0_RLC0_DOORBELL                                                   0x3512
++#define mmSDMA0_RLC0_VIRTUAL_ADDR                                               0x3527
++#define mmSDMA0_RLC0_APE1_CNTL                                                  0x3528
++#define mmSDMA0_RLC0_DOORBELL_LOG                                               0x3529
++#define mmSDMA0_RLC0_WATERMARK                                                  0x352a
++#define mmSDMA0_RLC0_CSA_ADDR_LO                                                0x352c
++#define mmSDMA0_RLC0_CSA_ADDR_HI                                                0x352d
++#define mmSDMA0_RLC0_IB_SUB_REMAIN                                              0x352f
++#define mmSDMA0_RLC0_PREEMPT                                                    0x3530
++#define mmSDMA0_RLC0_DUMMY_REG                                                  0x3531
++#define mmSDMA0_RLC0_MIDCMD_DATA0                                               0x3541
++#define mmSDMA0_RLC0_MIDCMD_DATA1                                               0x3542
++#define mmSDMA0_RLC0_MIDCMD_DATA2                                               0x3543
++#define mmSDMA0_RLC0_MIDCMD_DATA3                                               0x3544
++#define mmSDMA0_RLC0_MIDCMD_DATA4                                               0x3545
++#define mmSDMA0_RLC0_MIDCMD_DATA5                                               0x3546
++#define mmSDMA0_RLC0_MIDCMD_CNTL                                                0x3547
++#define mmSDMA0_RLC1_RB_CNTL                                                    0x3580
++#define mmSDMA0_RLC1_RB_BASE                                                    0x3581
++#define mmSDMA0_RLC1_RB_BASE_HI                                                 0x3582
++#define mmSDMA0_RLC1_RB_RPTR                                                    0x3583
++#define mmSDMA0_RLC1_RB_WPTR                                                    0x3584
++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                          0x3585
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3586
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3587
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                            0x3588
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                            0x3589
++#define mmSDMA0_RLC1_IB_CNTL                                                    0x358a
++#define mmSDMA0_RLC1_IB_RPTR                                                    0x358b
++#define mmSDMA0_RLC1_IB_OFFSET                                                  0x358c
++#define mmSDMA0_RLC1_IB_BASE_LO                                                 0x358d
++#define mmSDMA0_RLC1_IB_BASE_HI                                                 0x358e
++#define mmSDMA0_RLC1_IB_SIZE                                                    0x358f
++#define mmSDMA0_RLC1_SKIP_CNTL                                                  0x3590
++#define mmSDMA0_RLC1_CONTEXT_STATUS                                             0x3591
++#define mmSDMA0_RLC1_DOORBELL                                                   0x3592
++#define mmSDMA0_RLC1_VIRTUAL_ADDR                                               0x35a7
++#define mmSDMA0_RLC1_APE1_CNTL                                                  0x35a8
++#define mmSDMA0_RLC1_DOORBELL_LOG                                               0x35a9
++#define mmSDMA0_RLC1_WATERMARK                                                  0x35aa
++#define mmSDMA0_RLC1_CSA_ADDR_LO                                                0x35ac
++#define mmSDMA0_RLC1_CSA_ADDR_HI                                                0x35ad
++#define mmSDMA0_RLC1_IB_SUB_REMAIN                                              0x35af
++#define mmSDMA0_RLC1_PREEMPT                                                    0x35b0
++#define mmSDMA0_RLC1_DUMMY_REG                                                  0x35b1
++#define mmSDMA0_RLC1_MIDCMD_DATA0                                               0x35c1
++#define mmSDMA0_RLC1_MIDCMD_DATA1                                               0x35c2
++#define mmSDMA0_RLC1_MIDCMD_DATA2                                               0x35c3
++#define mmSDMA0_RLC1_MIDCMD_DATA3                                               0x35c4
++#define mmSDMA0_RLC1_MIDCMD_DATA4                                               0x35c5
++#define mmSDMA0_RLC1_MIDCMD_DATA5                                               0x35c6
++#define mmSDMA0_RLC1_MIDCMD_CNTL                                                0x35c7
++#define mmSDMA1_UCODE_ADDR                                                      0x3600
++#define mmSDMA1_UCODE_DATA                                                      0x3601
++#define mmSDMA1_POWER_CNTL                                                      0x3602
++#define mmSDMA1_CLK_CTRL                                                        0x3603
++#define mmSDMA1_CNTL                                                            0x3604
++#define mmSDMA1_CHICKEN_BITS                                                    0x3605
++#define mmSDMA1_TILING_CONFIG                                                   0x3606
++#define mmSDMA1_HASH                                                            0x3607
++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3609
++#define mmSDMA1_RB_RPTR_FETCH                                                   0x360a
++#define mmSDMA1_IB_OFFSET_FETCH                                                 0x360b
++#define mmSDMA1_PROGRAM                                                         0x360c
++#define mmSDMA1_STATUS_REG                                                      0x360d
++#define mmSDMA1_STATUS1_REG                                                     0x360e
++#define mmSDMA1_RD_BURST_CNTL                                                   0x360f
++#define mmSDMA1_PERFMON_CNTL                                                    0x9010
++#define mmSDMA1_PERFCOUNTER0_RESULT                                             0x9011
++#define mmSDMA1_PERFCOUNTER1_RESULT                                             0x9012
++#define mmSDMA1_F32_CNTL                                                        0x3612
++#define mmSDMA1_FREEZE                                                          0x3613
++#define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
++#define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
++#define mmSDMA1_EDC_CONFIG                                                      0x361a
++#define mmSDMA1_VM_CNTL                                                         0x3620
++#define mmSDMA1_VM_CTX_LO                                                       0x3621
++#define mmSDMA1_VM_CTX_HI                                                       0x3622
++#define mmSDMA1_STATUS2_REG                                                     0x3623
++#define mmSDMA1_ACTIVE_FCN_ID                                                   0x3624
++#define mmSDMA1_VM_CTX_CNTL                                                     0x3625
++#define mmSDMA1_VIRT_RESET_REQ                                                  0x3626
++#define mmSDMA1_VF_ENABLE                                                       0x3627
++#define mmSDMA1_BA_THRESHOLD                                                    0x361b
++#define mmSDMA1_ID                                                              0x361c
++#define mmSDMA1_VERSION                                                         0x361d
++#define mmSDMA1_ATOMIC_CNTL                                                     0x3628
++#define mmSDMA1_ATOMIC_PREOP_LO                                                 0x3629
++#define mmSDMA1_ATOMIC_PREOP_HI                                                 0x362a
++#define mmSDMA1_POWER_CNTL_IDLE                                                 0x362c
++#define mmSDMA1_PERF_REG_TYPE0                                                  0x3677
++#define mmSDMA1_CONTEXT_REG_TYPE0                                               0x3678
++#define mmSDMA1_CONTEXT_REG_TYPE1                                               0x3679
++#define mmSDMA1_CONTEXT_REG_TYPE2                                               0x367a
++#define mmSDMA1_PUB_REG_TYPE0                                                   0x367c
++#define mmSDMA1_PUB_REG_TYPE1                                                   0x367d
++#define mmSDMA1_GFX_RB_CNTL                                                     0x3680
++#define mmSDMA1_GFX_RB_BASE                                                     0x3681
++#define mmSDMA1_GFX_RB_BASE_HI                                                  0x3682
++#define mmSDMA1_GFX_RB_RPTR                                                     0x3683
++#define mmSDMA1_GFX_RB_WPTR                                                     0x3684
++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3686
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3687
++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                             0x3688
++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                             0x3689
++#define mmSDMA1_GFX_IB_CNTL                                                     0x368a
++#define mmSDMA1_GFX_IB_RPTR                                                     0x368b
++#define mmSDMA1_GFX_IB_OFFSET                                                   0x368c
++#define mmSDMA1_GFX_IB_BASE_LO                                                  0x368d
++#define mmSDMA1_GFX_IB_BASE_HI                                                  0x368e
++#define mmSDMA1_GFX_IB_SIZE                                                     0x368f
++#define mmSDMA1_GFX_SKIP_CNTL                                                   0x3690
++#define mmSDMA1_GFX_CONTEXT_STATUS                                              0x3691
++#define mmSDMA1_GFX_DOORBELL                                                    0x3692
++#define mmSDMA1_GFX_CONTEXT_CNTL                                                0x3693
++#define mmSDMA1_GFX_VIRTUAL_ADDR                                                0x36a7
++#define mmSDMA1_GFX_APE1_CNTL                                                   0x36a8
++#define mmSDMA1_GFX_DOORBELL_LOG                                                0x36a9
++#define mmSDMA1_GFX_WATERMARK                                                   0x36aa
++#define mmSDMA1_GFX_CSA_ADDR_LO                                                 0x36ac
++#define mmSDMA1_GFX_CSA_ADDR_HI                                                 0x36ad
++#define mmSDMA1_GFX_IB_SUB_REMAIN                                               0x36af
++#define mmSDMA1_GFX_PREEMPT                                                     0x36b0
++#define mmSDMA1_GFX_DUMMY_REG                                                   0x36b1
++#define mmSDMA1_GFX_MIDCMD_DATA0                                                0x36c1
++#define mmSDMA1_GFX_MIDCMD_DATA1                                                0x36c2
++#define mmSDMA1_GFX_MIDCMD_DATA2                                                0x36c3
++#define mmSDMA1_GFX_MIDCMD_DATA3                                                0x36c4
++#define mmSDMA1_GFX_MIDCMD_DATA4                                                0x36c5
++#define mmSDMA1_GFX_MIDCMD_DATA5                                                0x36c6
++#define mmSDMA1_GFX_MIDCMD_CNTL                                                 0x36c7
++#define mmSDMA1_RLC0_RB_CNTL                                                    0x3700
++#define mmSDMA1_RLC0_RB_BASE                                                    0x3701
++#define mmSDMA1_RLC0_RB_BASE_HI                                                 0x3702
++#define mmSDMA1_RLC0_RB_RPTR                                                    0x3703
++#define mmSDMA1_RLC0_RB_WPTR                                                    0x3704
++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                          0x3705
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3706
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3707
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                            0x3708
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                            0x3709
++#define mmSDMA1_RLC0_IB_CNTL                                                    0x370a
++#define mmSDMA1_RLC0_IB_RPTR                                                    0x370b
++#define mmSDMA1_RLC0_IB_OFFSET                                                  0x370c
++#define mmSDMA1_RLC0_IB_BASE_LO                                                 0x370d
++#define mmSDMA1_RLC0_IB_BASE_HI                                                 0x370e
++#define mmSDMA1_RLC0_IB_SIZE                                                    0x370f
++#define mmSDMA1_RLC0_SKIP_CNTL                                                  0x3710
++#define mmSDMA1_RLC0_CONTEXT_STATUS                                             0x3711
++#define mmSDMA1_RLC0_DOORBELL                                                   0x3712
++#define mmSDMA1_RLC0_VIRTUAL_ADDR                                               0x3727
++#define mmSDMA1_RLC0_APE1_CNTL                                                  0x3728
++#define mmSDMA1_RLC0_DOORBELL_LOG                                               0x3729
++#define mmSDMA1_RLC0_WATERMARK                                                  0x372a
++#define mmSDMA1_RLC0_CSA_ADDR_LO                                                0x372c
++#define mmSDMA1_RLC0_CSA_ADDR_HI                                                0x372d
++#define mmSDMA1_RLC0_IB_SUB_REMAIN                                              0x372f
++#define mmSDMA1_RLC0_PREEMPT                                                    0x3730
++#define mmSDMA1_RLC0_DUMMY_REG                                                  0x3731
++#define mmSDMA1_RLC0_MIDCMD_DATA0                                               0x3741
++#define mmSDMA1_RLC0_MIDCMD_DATA1                                               0x3742
++#define mmSDMA1_RLC0_MIDCMD_DATA2                                               0x3743
++#define mmSDMA1_RLC0_MIDCMD_DATA3                                               0x3744
++#define mmSDMA1_RLC0_MIDCMD_DATA4                                               0x3745
++#define mmSDMA1_RLC0_MIDCMD_DATA5                                               0x3746
++#define mmSDMA1_RLC0_MIDCMD_CNTL                                                0x3747
++#define mmSDMA1_RLC1_RB_CNTL                                                    0x3780
++#define mmSDMA1_RLC1_RB_BASE                                                    0x3781
++#define mmSDMA1_RLC1_RB_BASE_HI                                                 0x3782
++#define mmSDMA1_RLC1_RB_RPTR                                                    0x3783
++#define mmSDMA1_RLC1_RB_WPTR                                                    0x3784
++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                          0x3785
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3786
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3787
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                            0x3788
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                            0x3789
++#define mmSDMA1_RLC1_IB_CNTL                                                    0x378a
++#define mmSDMA1_RLC1_IB_RPTR                                                    0x378b
++#define mmSDMA1_RLC1_IB_OFFSET                                                  0x378c
++#define mmSDMA1_RLC1_IB_BASE_LO                                                 0x378d
++#define mmSDMA1_RLC1_IB_BASE_HI                                                 0x378e
++#define mmSDMA1_RLC1_IB_SIZE                                                    0x378f
++#define mmSDMA1_RLC1_SKIP_CNTL                                                  0x3790
++#define mmSDMA1_RLC1_CONTEXT_STATUS                                             0x3791
++#define mmSDMA1_RLC1_DOORBELL                                                   0x3792
++#define mmSDMA1_RLC1_VIRTUAL_ADDR                                               0x37a7
++#define mmSDMA1_RLC1_APE1_CNTL                                                  0x37a8
++#define mmSDMA1_RLC1_DOORBELL_LOG                                               0x37a9
++#define mmSDMA1_RLC1_WATERMARK                                                  0x37aa
++#define mmSDMA1_RLC1_CSA_ADDR_LO                                                0x37ac
++#define mmSDMA1_RLC1_CSA_ADDR_HI                                                0x37ad
++#define mmSDMA1_RLC1_IB_SUB_REMAIN                                              0x37af
++#define mmSDMA1_RLC1_PREEMPT                                                    0x37b0
++#define mmSDMA1_RLC1_DUMMY_REG                                                  0x37b1
++#define mmSDMA1_RLC1_MIDCMD_DATA0                                               0x37c1
++#define mmSDMA1_RLC1_MIDCMD_DATA1                                               0x37c2
++#define mmSDMA1_RLC1_MIDCMD_DATA2                                               0x37c3
++#define mmSDMA1_RLC1_MIDCMD_DATA3                                               0x37c4
++#define mmSDMA1_RLC1_MIDCMD_DATA4                                               0x37c5
++#define mmSDMA1_RLC1_MIDCMD_DATA5                                               0x37c6
++#define mmSDMA1_RLC1_MIDCMD_CNTL                                                0x37c7
++#define mmHDP_HOST_PATH_CNTL                                                    0xb00
++#define mmHDP_NONSURFACE_BASE                                                   0xb01
++#define mmHDP_NONSURFACE_INFO                                                   0xb02
++#define mmHDP_NONSURFACE_SIZE                                                   0xb03
++#define mmHDP_NONSURF_FLAGS                                                     0xbc9
++#define mmHDP_NONSURF_FLAGS_CLR                                                 0xbca
++#define mmHDP_SW_SEMAPHORE                                                      0xbcb
++#define mmHDP_DEBUG0                                                            0xbcc
++#define mmHDP_DEBUG1                                                            0xbcd
++#define mmHDP_LAST_SURFACE_HIT                                                  0xbce
++#define mmHDP_TILING_CONFIG                                                     0xbcf
++#define mmHDP_SC_MULTI_CHIP_CNTL                                                0xbd0
++#define mmHDP_OUTSTANDING_REQ                                                   0xbd1
++#define mmHDP_ADDR_CONFIG                                                       0xbd2
++#define mmHDP_MISC_CNTL                                                         0xbd3
++#define mmHDP_MEM_POWER_LS                                                      0xbd4
++#define mmHDP_NONSURFACE_PREFETCH                                               0xbd5
++#define mmHDP_MEMIO_CNTL                                                        0xbf6
++#define mmHDP_MEMIO_ADDR                                                        0xbf7
++#define mmHDP_MEMIO_STATUS                                                      0xbf8
++#define mmHDP_MEMIO_WR_DATA                                                     0xbf9
++#define mmHDP_MEMIO_RD_DATA                                                     0xbfa
++#define mmHDP_VF_ENABLE                                                         0xbfb
++#define mmHDP_XDP_DIRECT2HDP_FIRST                                              0xc00
++#define mmHDP_XDP_D2H_FLUSH                                                     0xc01
++#define mmHDP_XDP_D2H_BAR_UPDATE                                                0xc02
++#define mmHDP_XDP_D2H_RSVD_3                                                    0xc03
++#define mmHDP_XDP_D2H_RSVD_4                                                    0xc04
++#define mmHDP_XDP_D2H_RSVD_5                                                    0xc05
++#define mmHDP_XDP_D2H_RSVD_6                                                    0xc06
++#define mmHDP_XDP_D2H_RSVD_7                                                    0xc07
++#define mmHDP_XDP_D2H_RSVD_8                                                    0xc08
++#define mmHDP_XDP_D2H_RSVD_9                                                    0xc09
++#define mmHDP_XDP_D2H_RSVD_10                                                   0xc0a
++#define mmHDP_XDP_D2H_RSVD_11                                                   0xc0b
++#define mmHDP_XDP_D2H_RSVD_12                                                   0xc0c
++#define mmHDP_XDP_D2H_RSVD_13                                                   0xc0d
++#define mmHDP_XDP_D2H_RSVD_14                                                   0xc0e
++#define mmHDP_XDP_D2H_RSVD_15                                                   0xc0f
++#define mmHDP_XDP_D2H_RSVD_16                                                   0xc10
++#define mmHDP_XDP_D2H_RSVD_17                                                   0xc11
++#define mmHDP_XDP_D2H_RSVD_18                                                   0xc12
++#define mmHDP_XDP_D2H_RSVD_19                                                   0xc13
++#define mmHDP_XDP_D2H_RSVD_20                                                   0xc14
++#define mmHDP_XDP_D2H_RSVD_21                                                   0xc15
++#define mmHDP_XDP_D2H_RSVD_22                                                   0xc16
++#define mmHDP_XDP_D2H_RSVD_23                                                   0xc17
++#define mmHDP_XDP_D2H_RSVD_24                                                   0xc18
++#define mmHDP_XDP_D2H_RSVD_25                                                   0xc19
++#define mmHDP_XDP_D2H_RSVD_26                                                   0xc1a
++#define mmHDP_XDP_D2H_RSVD_27                                                   0xc1b
++#define mmHDP_XDP_D2H_RSVD_28                                                   0xc1c
++#define mmHDP_XDP_D2H_RSVD_29                                                   0xc1d
++#define mmHDP_XDP_D2H_RSVD_30                                                   0xc1e
++#define mmHDP_XDP_D2H_RSVD_31                                                   0xc1f
++#define mmHDP_XDP_D2H_RSVD_32                                                   0xc20
++#define mmHDP_XDP_D2H_RSVD_33                                                   0xc21
++#define mmHDP_XDP_D2H_RSVD_34                                                   0xc22
++#define mmHDP_XDP_DIRECT2HDP_LAST                                               0xc23
++#define mmHDP_XDP_P2P_BAR_CFG                                                   0xc24
++#define mmHDP_XDP_P2P_MBX_OFFSET                                                0xc25
++#define mmHDP_XDP_P2P_MBX_ADDR0                                                 0xc26
++#define mmHDP_XDP_P2P_MBX_ADDR1                                                 0xc27
++#define mmHDP_XDP_P2P_MBX_ADDR2                                                 0xc28
++#define mmHDP_XDP_P2P_MBX_ADDR3                                                 0xc29
++#define mmHDP_XDP_P2P_MBX_ADDR4                                                 0xc2a
++#define mmHDP_XDP_P2P_MBX_ADDR5                                                 0xc2b
++#define mmHDP_XDP_P2P_MBX_ADDR6                                                 0xc2c
++#define mmHDP_XDP_HDP_MBX_MC_CFG                                                0xc2d
++#define mmHDP_XDP_HDP_MC_CFG                                                    0xc2e
++#define mmHDP_XDP_HST_CFG                                                       0xc2f
++#define mmHDP_XDP_SID_CFG                                                       0xc30
++#define mmHDP_XDP_HDP_IPH_CFG                                                   0xc31
++#define mmHDP_XDP_SRBM_CFG                                                      0xc32
++#define mmHDP_XDP_CGTT_BLK_CTRL                                                 0xc33
++#define mmHDP_XDP_P2P_BAR0                                                      0xc34
++#define mmHDP_XDP_P2P_BAR1                                                      0xc35
++#define mmHDP_XDP_P2P_BAR2                                                      0xc36
++#define mmHDP_XDP_P2P_BAR3                                                      0xc37
++#define mmHDP_XDP_P2P_BAR4                                                      0xc38
++#define mmHDP_XDP_P2P_BAR5                                                      0xc39
++#define mmHDP_XDP_P2P_BAR6                                                      0xc3a
++#define mmHDP_XDP_P2P_BAR7                                                      0xc3b
++#define mmHDP_XDP_FLUSH_ARMED_STS                                               0xc3c
++#define mmHDP_XDP_FLUSH_CNTR0_STS                                               0xc3d
++#define mmHDP_XDP_BUSY_STS                                                      0xc3e
++#define mmHDP_XDP_STICKY                                                        0xc3f
++#define mmHDP_XDP_CHKN                                                          0xc40
++#define mmHDP_XDP_DBG_ADDR                                                      0xc41
++#define mmHDP_XDP_DBG_DATA                                                      0xc42
++#define mmHDP_XDP_DBG_MASK                                                      0xc43
++#define mmHDP_XDP_BARS_ADDR_39_36                                               0xc44
++
++#endif /* OSS_3_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
+new file mode 100644
+index 0000000..09338d8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
+@@ -0,0 +1,1497 @@
++/*
++ * OSS_3_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_3_0_ENUM_H
++#define OSS_3_0_ENUM_H
++
++typedef enum IH_CLIENT_ID {
++	DC_IH_SRC_ID_START                               = 0x1,
++	DC_IH_SRC_ID_END                                 = 0x1f,
++	VGA_IH_SRC_ID_START                              = 0x20,
++	VGA_IH_SRC_ID_END                                = 0x27,
++	CAP_IH_SRC_ID_START                              = 0x28,
++	CAP_IH_SRC_ID_END                                = 0x2f,
++	VIP_IH_SRC_ID_START                              = 0x30,
++	VIP_IH_SRC_ID_END                                = 0x3f,
++	ROM_IH_SRC_ID_START                              = 0x40,
++	ROM_IH_SRC_ID_END                                = 0x5d,
++	BIF_IH_SRC_ID_START                              = 0x5e,
++	SAM_IH_SRC_ID_START                              = 0x5f,
++	SRBM_IH_SRC_ID_START                             = 0x60,
++	SRBM_IH_SRC_ID_END                               = 0x67,
++	UVD_IH_SRC_ID_START                              = 0x72,
++	UVD_IH_SRC_ID_END                                = 0x85,
++	VMC_IH_SRC_ID_START                              = 0x86,
++	VMC_IH_SRC_ID_END                                = 0x8f,
++	RLC_IH_SRC_ID_START                              = 0x90,
++	RLC_IH_SRC_ID_END                                = 0xf3,
++	PDMA_IH_SRC_ID_START                             = 0xf4,
++	PDMA_IH_SRC_ID_END                               = 0xf7,
++	CG_IH_SRC_ID_START                               = 0xf8,
++	CG_IH_SRC_ID_END                                 = 0xff,
++} IH_CLIENT_ID;
++typedef enum IH_PERF_SEL {
++	IH_PERF_SEL_CYCLE                                = 0x0,
++	IH_PERF_SEL_IDLE                                 = 0x1,
++	IH_PERF_SEL_INPUT_IDLE                           = 0x2,
++	IH_PERF_SEL_CLIENT0_IH_STALL                     = 0x3,
++	IH_PERF_SEL_CLIENT1_IH_STALL                     = 0x4,
++	IH_PERF_SEL_CLIENT2_IH_STALL                     = 0x5,
++	IH_PERF_SEL_CLIENT3_IH_STALL                     = 0x6,
++	IH_PERF_SEL_CLIENT4_IH_STALL                     = 0x7,
++	IH_PERF_SEL_CLIENT5_IH_STALL                     = 0x8,
++	IH_PERF_SEL_CLIENT6_IH_STALL                     = 0x9,
++	IH_PERF_SEL_CLIENT7_IH_STALL                     = 0xa,
++	IH_PERF_SEL_RB_IDLE                              = 0xb,
++	IH_PERF_SEL_RB_FULL                              = 0xc,
++	IH_PERF_SEL_RB_OVERFLOW                          = 0xd,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK                    = 0xe,
++	IH_PERF_SEL_RB_WPTR_WRAP                         = 0xf,
++	IH_PERF_SEL_RB_RPTR_WRAP                         = 0x10,
++	IH_PERF_SEL_MC_WR_IDLE                           = 0x11,
++	IH_PERF_SEL_MC_WR_COUNT                          = 0x12,
++	IH_PERF_SEL_MC_WR_STALL                          = 0x13,
++	IH_PERF_SEL_MC_WR_CLEAN_PENDING                  = 0x14,
++	IH_PERF_SEL_MC_WR_CLEAN_STALL                    = 0x15,
++	IH_PERF_SEL_BIF_RISING                           = 0x16,
++	IH_PERF_SEL_BIF_FALLING                          = 0x17,
++	IH_PERF_SEL_CLIENT8_IH_STALL                     = 0x18,
++	IH_PERF_SEL_CLIENT9_IH_STALL                     = 0x19,
++	IH_PERF_SEL_CLIENT10_IH_STALL                    = 0x1a,
++	IH_PERF_SEL_CLIENT11_IH_STALL                    = 0x1b,
++	IH_PERF_SEL_CLIENT12_IH_STALL                    = 0x1c,
++	IH_PERF_SEL_CLIENT13_IH_STALL                    = 0x1d,
++	IH_PERF_SEL_CLIENT14_IH_STALL                    = 0x1e,
++	IH_PERF_SEL_CLIENT15_IH_STALL                    = 0x1f,
++	IH_PERF_SEL_CLIENT16_IH_STALL                    = 0x20,
++	IH_PERF_SEL_CLIENT17_IH_STALL                    = 0x21,
++	IH_PERF_SEL_CLIENT18_IH_STALL                    = 0x22,
++	IH_PERF_SEL_CLIENT19_IH_STALL                    = 0x23,
++	IH_PERF_SEL_CLIENT20_IH_STALL                    = 0x24,
++	IH_PERF_SEL_CLIENT21_IH_STALL                    = 0x25,
++	IH_PERF_SEL_CLIENT22_IH_STALL                    = 0x26,
++	IH_PERF_SEL_RB_FULL_VF0                          = 0x27,
++	IH_PERF_SEL_RB_FULL_VF1                          = 0x28,
++	IH_PERF_SEL_RB_FULL_VF2                          = 0x29,
++	IH_PERF_SEL_RB_FULL_VF3                          = 0x2a,
++	IH_PERF_SEL_RB_FULL_VF4                          = 0x2b,
++	IH_PERF_SEL_RB_FULL_VF5                          = 0x2c,
++	IH_PERF_SEL_RB_FULL_VF6                          = 0x2d,
++	IH_PERF_SEL_RB_FULL_VF7                          = 0x2e,
++	IH_PERF_SEL_RB_FULL_VF8                          = 0x2f,
++	IH_PERF_SEL_RB_FULL_VF9                          = 0x30,
++	IH_PERF_SEL_RB_FULL_VF10                         = 0x31,
++	IH_PERF_SEL_RB_FULL_VF11                         = 0x32,
++	IH_PERF_SEL_RB_FULL_VF12                         = 0x33,
++	IH_PERF_SEL_RB_FULL_VF13                         = 0x34,
++	IH_PERF_SEL_RB_FULL_VF14                         = 0x35,
++	IH_PERF_SEL_RB_FULL_VF15                         = 0x36,
++	IH_PERF_SEL_RB_OVERFLOW_VF0                      = 0x37,
++	IH_PERF_SEL_RB_OVERFLOW_VF1                      = 0x38,
++	IH_PERF_SEL_RB_OVERFLOW_VF2                      = 0x39,
++	IH_PERF_SEL_RB_OVERFLOW_VF3                      = 0x3a,
++	IH_PERF_SEL_RB_OVERFLOW_VF4                      = 0x3b,
++	IH_PERF_SEL_RB_OVERFLOW_VF5                      = 0x3c,
++	IH_PERF_SEL_RB_OVERFLOW_VF6                      = 0x3d,
++	IH_PERF_SEL_RB_OVERFLOW_VF7                      = 0x3e,
++	IH_PERF_SEL_RB_OVERFLOW_VF8                      = 0x3f,
++	IH_PERF_SEL_RB_OVERFLOW_VF9                      = 0x40,
++	IH_PERF_SEL_RB_OVERFLOW_VF10                     = 0x41,
++	IH_PERF_SEL_RB_OVERFLOW_VF11                     = 0x42,
++	IH_PERF_SEL_RB_OVERFLOW_VF12                     = 0x43,
++	IH_PERF_SEL_RB_OVERFLOW_VF13                     = 0x44,
++	IH_PERF_SEL_RB_OVERFLOW_VF14                     = 0x45,
++	IH_PERF_SEL_RB_OVERFLOW_VF15                     = 0x46,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0                = 0x47,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1                = 0x48,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2                = 0x49,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3                = 0x4a,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4                = 0x4b,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5                = 0x4c,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6                = 0x4d,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7                = 0x4e,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8                = 0x4f,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9                = 0x50,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10               = 0x51,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11               = 0x52,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12               = 0x53,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13               = 0x54,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14               = 0x55,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15               = 0x56,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF0                     = 0x57,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF1                     = 0x58,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF2                     = 0x59,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF3                     = 0x5a,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF4                     = 0x5b,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF5                     = 0x5c,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF6                     = 0x5d,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF7                     = 0x5e,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF8                     = 0x5f,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF9                     = 0x60,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF10                    = 0x61,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF11                    = 0x62,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF12                    = 0x63,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF13                    = 0x64,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF14                    = 0x65,
++	IH_PERF_SEL_RB_WPTR_WRAP_VF15                    = 0x66,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF0                     = 0x67,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF1                     = 0x68,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF2                     = 0x69,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF3                     = 0x6a,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF4                     = 0x6b,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF5                     = 0x6c,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF6                     = 0x6d,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF7                     = 0x6e,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF8                     = 0x6f,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF9                     = 0x70,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF10                    = 0x71,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF11                    = 0x72,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF12                    = 0x73,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF13                    = 0x74,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF14                    = 0x75,
++	IH_PERF_SEL_RB_RPTR_WRAP_VF15                    = 0x76,
++	IH_PERF_SEL_BIF_RISING_VF0                       = 0x77,
++	IH_PERF_SEL_BIF_RISING_VF1                       = 0x78,
++	IH_PERF_SEL_BIF_RISING_VF2                       = 0x79,
++	IH_PERF_SEL_BIF_RISING_VF3                       = 0x7a,
++	IH_PERF_SEL_BIF_RISING_VF4                       = 0x7b,
++	IH_PERF_SEL_BIF_RISING_VF5                       = 0x7c,
++	IH_PERF_SEL_BIF_RISING_VF6                       = 0x7d,
++	IH_PERF_SEL_BIF_RISING_VF7                       = 0x7e,
++	IH_PERF_SEL_BIF_RISING_VF8                       = 0x7f,
++	IH_PERF_SEL_BIF_RISING_VF9                       = 0x80,
++	IH_PERF_SEL_BIF_RISING_VF10                      = 0x81,
++	IH_PERF_SEL_BIF_RISING_VF11                      = 0x82,
++	IH_PERF_SEL_BIF_RISING_VF12                      = 0x83,
++	IH_PERF_SEL_BIF_RISING_VF13                      = 0x84,
++	IH_PERF_SEL_BIF_RISING_VF14                      = 0x85,
++	IH_PERF_SEL_BIF_RISING_VF15                      = 0x86,
++	IH_PERF_SEL_BIF_FALLING_VF0                      = 0x87,
++	IH_PERF_SEL_BIF_FALLING_VF1                      = 0x88,
++	IH_PERF_SEL_BIF_FALLING_VF2                      = 0x89,
++	IH_PERF_SEL_BIF_FALLING_VF3                      = 0x8a,
++	IH_PERF_SEL_BIF_FALLING_VF4                      = 0x8b,
++	IH_PERF_SEL_BIF_FALLING_VF5                      = 0x8c,
++	IH_PERF_SEL_BIF_FALLING_VF6                      = 0x8d,
++	IH_PERF_SEL_BIF_FALLING_VF7                      = 0x8e,
++	IH_PERF_SEL_BIF_FALLING_VF8                      = 0x8f,
++	IH_PERF_SEL_BIF_FALLING_VF9                      = 0x90,
++	IH_PERF_SEL_BIF_FALLING_VF10                     = 0x91,
++	IH_PERF_SEL_BIF_FALLING_VF11                     = 0x92,
++	IH_PERF_SEL_BIF_FALLING_VF12                     = 0x93,
++	IH_PERF_SEL_BIF_FALLING_VF13                     = 0x94,
++	IH_PERF_SEL_BIF_FALLING_VF14                     = 0x95,
++	IH_PERF_SEL_BIF_FALLING_VF15                     = 0x96,
++} IH_PERF_SEL;
++typedef enum SRBM_PERFCOUNT1_SEL {
++	SRBM_PERF_SEL_COUNT                              = 0x0,
++	SRBM_PERF_SEL_BIF_BUSY                           = 0x1,
++	SRBM_PERF_SEL_SDMA0_BUSY                         = 0x3,
++	SRBM_PERF_SEL_IH_BUSY                            = 0x4,
++	SRBM_PERF_SEL_MCB_BUSY                           = 0x5,
++	SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY               = 0x6,
++	SRBM_PERF_SEL_MCC_BUSY                           = 0x7,
++	SRBM_PERF_SEL_MCD_BUSY                           = 0x8,
++	SRBM_PERF_SEL_CHUB_BUSY                          = 0x9,
++	SRBM_PERF_SEL_SEM_BUSY                           = 0xa,
++	SRBM_PERF_SEL_UVD_BUSY                           = 0xb,
++	SRBM_PERF_SEL_VMC_BUSY                           = 0xc,
++	SRBM_PERF_SEL_ODE_BUSY                           = 0xd,
++	SRBM_PERF_SEL_SDMA1_BUSY                         = 0xe,
++	SRBM_PERF_SEL_SAMMSP_BUSY                        = 0xf,
++	SRBM_PERF_SEL_VCE0_BUSY                          = 0x10,
++	SRBM_PERF_SEL_XDMA_BUSY                          = 0x11,
++	SRBM_PERF_SEL_ACP_BUSY                           = 0x12,
++	SRBM_PERF_SEL_SDMA2_BUSY                         = 0x13,
++	SRBM_PERF_SEL_SDMA3_BUSY                         = 0x14,
++	SRBM_PERF_SEL_SAMSCP_BUSY                        = 0x15,
++	SRBM_PERF_SEL_VMC1_BUSY                          = 0x16,
++	SRBM_PERF_SEL_ISP_BUSY                           = 0x17,
++	SRBM_PERF_SEL_VCE1_BUSY                          = 0x18,
++	SRBM_PERF_SEL_GCATCL2_BUSY                       = 0x19,
++	SRBM_PERF_SEL_OSATCL2_BUSY                       = 0x1a,
++	SRBM_PERF_SEL_VP8_BUSY                           = 0x1b,
++} SRBM_PERFCOUNT1_SEL;
++typedef enum SYS_GRBM_GFX_INDEX_SEL {
++	GRBM_GFX_INDEX_BIF                               = 0x0,
++	GRBM_GFX_INDEX_SDMA0                             = 0x1,
++	GRBM_GFX_INDEX_SDMA1                             = 0x2,
++	RESEVERED0                                       = 0x3,
++	GRBM_GFX_INDEX_UVD                               = 0x4,
++	GRBM_GFX_INDEX_VCE0                              = 0x5,
++	GRBM_GFX_INDEX_VCE1                              = 0x6,
++	GRBM_GFX_INDEX_ACP                               = 0x7,
++	GRBM_GFX_INDEX_SMU                               = 0x8,
++	GRBM_GFX_INDEX_SAMMSP                            = 0x9,
++	GRBM_GFX_INDEX_SAMSCP                            = 0xa,
++	GRBM_GFX_INDEX_ISP                               = 0xb,
++	GRBM_GFX_INDEX_TST                               = 0xc,
++	GRBM_GFX_INDEX_SDMA2                             = 0xd,
++	GRBM_GFX_INDEX_SDMA3                             = 0xe,
++} SYS_GRBM_GFX_INDEX_SEL;
++typedef enum SRBM_GFX_CNTL_SEL {
++	SRBM_GFX_CNTL_BIF                                = 0x0,
++	SRBM_GFX_CNTL_SDMA0                              = 0x1,
++	SRBM_GFX_CNTL_SDMA1                              = 0x2,
++	SRBM_GFX_CNTL_GRBM                               = 0x3,
++	SRBM_GFX_CNTL_UVD                                = 0x4,
++	SRBM_GFX_CNTL_VCE0                               = 0x5,
++	SRBM_GFX_CNTL_VCE1                               = 0x6,
++	SRBM_GFX_CNTL_ACP                                = 0x7,
++	SRBM_GFX_CNTL_SMU                                = 0x8,
++	SRBM_GFX_CNTL_SAMMSP                             = 0x9,
++	SRBM_GFX_CNTL_SAMSCP                             = 0xa,
++	SRBM_GFX_CNTL_ISP                                = 0xb,
++	SRBM_GFX_CNTL_TST                                = 0xc,
++	SRBM_GFX_CNTL_SDMA2                              = 0xd,
++	SRBM_GFX_CNTL_SDMA3                              = 0xe,
++} SRBM_GFX_CNTL_SEL;
++typedef enum SDMA_PERF_SEL {
++	SDMA_PERF_SEL_CYCLE                              = 0x0,
++	SDMA_PERF_SEL_IDLE                               = 0x1,
++	SDMA_PERF_SEL_REG_IDLE                           = 0x2,
++	SDMA_PERF_SEL_RB_EMPTY                           = 0x3,
++	SDMA_PERF_SEL_RB_FULL                            = 0x4,
++	SDMA_PERF_SEL_RB_WPTR_WRAP                       = 0x5,
++	SDMA_PERF_SEL_RB_RPTR_WRAP                       = 0x6,
++	SDMA_PERF_SEL_RB_WPTR_POLL_READ                  = 0x7,
++	SDMA_PERF_SEL_RB_RPTR_WB                         = 0x8,
++	SDMA_PERF_SEL_RB_CMD_IDLE                        = 0x9,
++	SDMA_PERF_SEL_RB_CMD_FULL                        = 0xa,
++	SDMA_PERF_SEL_IB_CMD_IDLE                        = 0xb,
++	SDMA_PERF_SEL_IB_CMD_FULL                        = 0xc,
++	SDMA_PERF_SEL_EX_IDLE                            = 0xd,
++	SDMA_PERF_SEL_SRBM_REG_SEND                      = 0xe,
++	SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE          = 0xf,
++	SDMA_PERF_SEL_MC_WR_IDLE                         = 0x10,
++	SDMA_PERF_SEL_MC_WR_COUNT                        = 0x11,
++	SDMA_PERF_SEL_MC_RD_IDLE                         = 0x12,
++	SDMA_PERF_SEL_MC_RD_COUNT                        = 0x13,
++	SDMA_PERF_SEL_MC_RD_RET_STALL                    = 0x14,
++	SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE                 = 0x15,
++	SDMA_PERF_SEL_SEM_IDLE                           = 0x18,
++	SDMA_PERF_SEL_SEM_REQ_STALL                      = 0x19,
++	SDMA_PERF_SEL_SEM_REQ_COUNT                      = 0x1a,
++	SDMA_PERF_SEL_SEM_RESP_INCOMPLETE                = 0x1b,
++	SDMA_PERF_SEL_SEM_RESP_FAIL                      = 0x1c,
++	SDMA_PERF_SEL_SEM_RESP_PASS                      = 0x1d,
++	SDMA_PERF_SEL_INT_IDLE                           = 0x1e,
++	SDMA_PERF_SEL_INT_REQ_STALL                      = 0x1f,
++	SDMA_PERF_SEL_INT_REQ_COUNT                      = 0x20,
++	SDMA_PERF_SEL_INT_RESP_ACCEPTED                  = 0x21,
++	SDMA_PERF_SEL_INT_RESP_RETRY                     = 0x22,
++	SDMA_PERF_SEL_NUM_PACKET                         = 0x23,
++	SDMA_PERF_SEL_CE_WREQ_IDLE                       = 0x25,
++	SDMA_PERF_SEL_CE_WR_IDLE                         = 0x26,
++	SDMA_PERF_SEL_CE_SPLIT_IDLE                      = 0x27,
++	SDMA_PERF_SEL_CE_RREQ_IDLE                       = 0x28,
++	SDMA_PERF_SEL_CE_OUT_IDLE                        = 0x29,
++	SDMA_PERF_SEL_CE_IN_IDLE                         = 0x2a,
++	SDMA_PERF_SEL_CE_DST_IDLE                        = 0x2b,
++	SDMA_PERF_SEL_CE_AFIFO_FULL                      = 0x2e,
++	SDMA_PERF_SEL_CE_INFO_FULL                       = 0x31,
++	SDMA_PERF_SEL_CE_INFO1_FULL                      = 0x32,
++	SDMA_PERF_SEL_CE_RD_STALL                        = 0x33,
++	SDMA_PERF_SEL_CE_WR_STALL                        = 0x34,
++	SDMA_PERF_SEL_GFX_SELECT                         = 0x35,
++	SDMA_PERF_SEL_RLC0_SELECT                        = 0x36,
++	SDMA_PERF_SEL_RLC1_SELECT                        = 0x37,
++	SDMA_PERF_SEL_CTX_CHANGE                         = 0x38,
++	SDMA_PERF_SEL_CTX_CHANGE_EXPIRED                 = 0x39,
++	SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION               = 0x3a,
++	SDMA_PERF_SEL_DOORBELL                           = 0x3b,
++	SDMA_PERF_SEL_RD_BA_RTR                          = 0x3c,
++	SDMA_PERF_SEL_WR_BA_RTR                          = 0x3d,
++} SDMA_PERF_SEL;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
++	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
++	DBG_CLIENT_BLKID_bci0                            = 0xe,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
++	DBG_CLIENT_BLKID_cb100                           = 0x10,
++	DBG_CLIENT_BLKID_cb001                           = 0x11,
++	DBG_CLIENT_BLKID_mcd4                            = 0x12,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
++	DBG_CLIENT_BLKID_cb101                           = 0x14,
++	DBG_CLIENT_BLKID_sx10                            = 0x15,
++	DBG_CLIENT_BLKID_cb301                           = 0x16,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
++	DBG_CLIENT_BLKID_scf1                            = 0x1c,
++	DBG_CLIENT_BLKID_sx20                            = 0x1d,
++	DBG_CLIENT_BLKID_spim1                           = 0x1e,
++	DBG_CLIENT_BLKID_pa10                            = 0x1f,
++	DBG_CLIENT_BLKID_pa00                            = 0x20,
++	DBG_CLIENT_BLKID_gmcon                           = 0x21,
++	DBG_CLIENT_BLKID_mcb                             = 0x22,
++	DBG_CLIENT_BLKID_vgt0                            = 0x23,
++	DBG_CLIENT_BLKID_pc0                             = 0x24,
++	DBG_CLIENT_BLKID_bci2                            = 0x25,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
++	DBG_CLIENT_BLKID_spim3                           = 0x27,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
++	DBG_CLIENT_BLKID_cb000                           = 0x2e,
++	DBG_CLIENT_BLKID_spim0                           = 0x2f,
++	DBG_CLIENT_BLKID_mcc2                            = 0x30,
++	DBG_CLIENT_BLKID_ds0                             = 0x31,
++	DBG_CLIENT_BLKID_srbm                            = 0x32,
++	DBG_CLIENT_BLKID_ih                              = 0x33,
++	DBG_CLIENT_BLKID_sem                             = 0x34,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
++	DBG_CLIENT_BLKID_hdp                             = 0x37,
++	DBG_CLIENT_BLKID_acp_0                           = 0x38,
++	DBG_CLIENT_BLKID_acp_1                           = 0x39,
++	DBG_CLIENT_BLKID_cb200                           = 0x3a,
++	DBG_CLIENT_BLKID_scf3                            = 0x3b,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
++	DBG_CLIENT_BLKID_bci3                            = 0x41,
++	DBG_CLIENT_BLKID_mcd0                            = 0x42,
++	DBG_CLIENT_BLKID_pa11                            = 0x43,
++	DBG_CLIENT_BLKID_pa01                            = 0x44,
++	DBG_CLIENT_BLKID_cb201                           = 0x45,
++	DBG_CLIENT_BLKID_spim2                           = 0x46,
++	DBG_CLIENT_BLKID_vgt2                            = 0x47,
++	DBG_CLIENT_BLKID_pc2                             = 0x48,
++	DBG_CLIENT_BLKID_smu_0                           = 0x49,
++	DBG_CLIENT_BLKID_smu_1                           = 0x4a,
++	DBG_CLIENT_BLKID_smu_2                           = 0x4b,
++	DBG_CLIENT_BLKID_cb1                             = 0x4c,
++	DBG_CLIENT_BLKID_ia0                             = 0x4d,
++	DBG_CLIENT_BLKID_wd                              = 0x4e,
++	DBG_CLIENT_BLKID_ia1                             = 0x4f,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
++	DBG_CLIENT_BLKID_scf0                            = 0x51,
++	DBG_CLIENT_BLKID_vgt1                            = 0x52,
++	DBG_CLIENT_BLKID_pc1                             = 0x53,
++	DBG_CLIENT_BLKID_cb0                             = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
++	DBG_CLIENT_BLKID_vgt3                            = 0x7a,
++	DBG_CLIENT_BLKID_pc3                             = 0x7b,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
++	DBG_CLIENT_BLKID_cb300                           = 0x84,
++	DBG_CLIENT_BLKID_mcd1                            = 0x85,
++	DBG_CLIENT_BLKID_sx00                            = 0x86,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
++	DBG_CLIENT_BLKID_mcc3                            = 0x89,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
++	DBG_CLIENT_BLKID_gck                             = 0x8c,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8d,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
++	DBG_CLIENT_BLKID_rlc                             = 0x90,
++	DBG_CLIENT_BLKID_grbm                            = 0x91,
++	DBG_CLIENT_BLKID_sammsp                          = 0x92,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x93,
++	DBG_CLIENT_BLKID_dci_0                           = 0x94,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* OSS_3_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h
+new file mode 100644
+index 0000000..7e2cca5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h
+@@ -0,0 +1,3660 @@
++/*
++ * OSS_3_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_3_0_SH_MASK_H
++#define OSS_3_0_SH_MASK_H
++
++#define IH_VMID_0_LUT__PASID_MASK 0xffff
++#define IH_VMID_0_LUT__PASID__SHIFT 0x0
++#define IH_VMID_1_LUT__PASID_MASK 0xffff
++#define IH_VMID_1_LUT__PASID__SHIFT 0x0
++#define IH_VMID_2_LUT__PASID_MASK 0xffff
++#define IH_VMID_2_LUT__PASID__SHIFT 0x0
++#define IH_VMID_3_LUT__PASID_MASK 0xffff
++#define IH_VMID_3_LUT__PASID__SHIFT 0x0
++#define IH_VMID_4_LUT__PASID_MASK 0xffff
++#define IH_VMID_4_LUT__PASID__SHIFT 0x0
++#define IH_VMID_5_LUT__PASID_MASK 0xffff
++#define IH_VMID_5_LUT__PASID__SHIFT 0x0
++#define IH_VMID_6_LUT__PASID_MASK 0xffff
++#define IH_VMID_6_LUT__PASID__SHIFT 0x0
++#define IH_VMID_7_LUT__PASID_MASK 0xffff
++#define IH_VMID_7_LUT__PASID__SHIFT 0x0
++#define IH_VMID_8_LUT__PASID_MASK 0xffff
++#define IH_VMID_8_LUT__PASID__SHIFT 0x0
++#define IH_VMID_9_LUT__PASID_MASK 0xffff
++#define IH_VMID_9_LUT__PASID__SHIFT 0x0
++#define IH_VMID_10_LUT__PASID_MASK 0xffff
++#define IH_VMID_10_LUT__PASID__SHIFT 0x0
++#define IH_VMID_11_LUT__PASID_MASK 0xffff
++#define IH_VMID_11_LUT__PASID__SHIFT 0x0
++#define IH_VMID_12_LUT__PASID_MASK 0xffff
++#define IH_VMID_12_LUT__PASID__SHIFT 0x0
++#define IH_VMID_13_LUT__PASID_MASK 0xffff
++#define IH_VMID_13_LUT__PASID__SHIFT 0x0
++#define IH_VMID_14_LUT__PASID_MASK 0xffff
++#define IH_VMID_14_LUT__PASID__SHIFT 0x0
++#define IH_VMID_15_LUT__PASID_MASK 0xffff
++#define IH_VMID_15_LUT__PASID__SHIFT 0x0
++#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define IH_RB_CNTL__ENABLE_INTR_MASK 0x20000
++#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11
++#define IH_RB_CNTL__MC_SWAP_MASK 0xc0000
++#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12
++#define IH_RB_CNTL__RPTR_REARM_MASK 0x200000
++#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15
++#define IH_RB_CNTL__MC_VMID_MASK 0xf000000
++#define IH_RB_CNTL__MC_VMID__SHIFT 0x18
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define IH_RB_BASE__ADDR_MASK 0xffffffff
++#define IH_RB_BASE__ADDR__SHIFT 0x0
++#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_RPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
++#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_WPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
++#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
++#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
++#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x1f
++#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
++#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
++#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
++#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
++#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
++#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
++#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
++#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
++#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
++#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
++#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
++#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
++#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
++#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
++#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
++#define IH_STATUS__IDLE_MASK 0x1
++#define IH_STATUS__IDLE__SHIFT 0x0
++#define IH_STATUS__INPUT_IDLE_MASK 0x2
++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
++#define IH_STATUS__RB_IDLE_MASK 0x4
++#define IH_STATUS__RB_IDLE__SHIFT 0x2
++#define IH_STATUS__RB_FULL_MASK 0x8
++#define IH_STATUS__RB_FULL__SHIFT 0x3
++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
++#define IH_STATUS__RB_OVERFLOW_MASK 0x20
++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
++#define IH_STATUS__MC_WR_IDLE_MASK 0x40
++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
++#define IH_STATUS__MC_WR_STALL_MASK 0x80
++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
++#define IH_STATUS__SWITCH_READY_MASK 0x800
++#define IH_STATUS__SWITCH_READY__SHIFT 0xb
++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x400
++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa
++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x800
++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0xb
++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1
++#define IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT 0x0
++#define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2
++#define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1
++#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK 0x4
++#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2
++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2
++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
++#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
++#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
++#define IH_DOORBELL_RPTR__OFFSET_MASK 0x1fffff
++#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0
++#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000
++#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c
++#define IH_DOORBELL_RPTR__CAPTURED_MASK 0x40000000
++#define IH_DOORBELL_RPTR__CAPTURED__SHIFT 0x1e
++#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0xf
++#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
++#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
++#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
++#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
++#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0xffff
++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
++#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000
++#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
++#define IH_VF_ENABLE__VALUE_MASK 0x1
++#define IH_VF_ENABLE__VALUE__SHIFT 0x0
++#define IH_VIRT_RESET_REQ__VF_MASK 0xffff
++#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK 0xffff
++#define IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT 0x0
++#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000
++#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT 0x10
++#define IH_VERSION__VALUE_MASK 0xfff
++#define IH_VERSION__VALUE__SHIFT 0x0
++#define IH_LEVEL_INTR_MASK__MASK_MASK 0x1
++#define IH_LEVEL_INTR_MASK__MASK__SHIFT 0x0
++#define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1
++#define IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT 0x0
++#define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2
++#define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1
++#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK 0x8
++#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT 0x3
++#define IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK 0x10
++#define IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT 0x4
++#define IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK 0x20
++#define IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT 0x5
++#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK 0x40
++#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT 0x6
++#define IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK 0x80
++#define IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT 0x7
++#define IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK 0x100
++#define IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT 0x8
++#define IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK 0x200
++#define IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT 0x9
++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK 0x400
++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa
++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK 0x800
++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT 0xb
++#define IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK 0x1000
++#define IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT 0xc
++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK 0x2000
++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT 0xd
++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK 0x4000
++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT 0xe
++#define IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK 0x8000
++#define IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT 0xf
++#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK 0x10000
++#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT 0x10
++#define IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK 0x20000
++#define IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT 0x11
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK 0x40000
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT 0x12
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK 0x80000
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT 0x13
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK 0x100000
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT 0x14
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK 0x200000
++#define IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT 0x15
++#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK 0x400000
++#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT 0x16
++#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK 0xf000000
++#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT 0x18
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT 0x0
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK 0x8
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT 0x3
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK 0x10
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT 0x4
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK 0x20
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT 0x5
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK 0x40
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT 0x6
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK 0x80
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT 0x7
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK 0x100
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT 0x8
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK 0x200
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT 0x9
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK 0x400
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK 0x800
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT 0xb
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK 0x1000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT 0xc
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK 0x2000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT 0xd
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK 0x4000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT 0xe
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK 0x8000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT 0xf
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK 0x10000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT 0x10
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK 0x20000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT 0x11
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK 0x40000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT 0x12
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK 0x80000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT 0x13
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK 0x100000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT 0x14
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK 0x200000
++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT 0x15
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
++#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
++#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
++#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
++#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
++#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
++#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
++#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
++#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
++#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
++#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
++#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
++#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
++#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
++#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
++#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
++#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
++#define SEM_VF_ENABLE__VALUE_MASK 0x1
++#define SEM_VF_ENABLE__VALUE__SHIFT 0x0
++#define CP_CONFIG__CP_RDREQ_URG_MASK 0xf00
++#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x8
++#define CP_CONFIG__CP_REQ_TRAN_MASK 0x10000
++#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x10
++#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SEM_STATUS__SEM_IDLE_MASK 0x1
++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
++#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
++#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
++#define SEM_STATUS__SWITCH_READY_MASK 0x80000000
++#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
++#define SEM_MAILBOX__SIDEPORT_MASK 0xff
++#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
++#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
++#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
++#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
++#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
++#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
++#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
++#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
++#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
++#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
++#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
++#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
++#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL__MEID_MASK 0xc
++#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
++#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
++#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
++#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
++#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
++#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS2__VP8_BUSY_MASK 0x10
++#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4
++#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
++#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
++#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
++#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
++#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
++#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
++#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
++#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
++#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
++#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
++#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
++#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
++#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
++#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
++#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000
++#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc
++#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
++#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
++#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
++#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
++#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000
++#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf
++#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
++#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
++#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
++#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
++#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000
++#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12
++#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
++#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
++#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
++#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
++#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
++#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
++#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
++#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
++#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
++#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
++#define SRBM_STATUS__VMC_BUSY_MASK 0x100
++#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
++#define SRBM_STATUS__MCB_BUSY_MASK 0x200
++#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
++#define SRBM_STATUS__MCC_BUSY_MASK 0x800
++#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
++#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
++#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
++#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
++#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
++#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
++#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
++#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
++#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
++#define SRBM_STATUS__IH_BUSY_MASK 0x20000
++#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
++#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
++#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
++#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
++#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
++#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
++#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
++#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
++#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
++#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
++#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
++#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
++#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
++#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
++#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
++#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
++#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
++#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
++#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
++#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
++#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
++#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
++#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
++#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
++#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
++#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
++#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
++#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
++#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
++#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
++#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
++#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
++#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
++#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
++#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
++#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
++#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
++#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
++#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
++#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
++#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
++#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
++#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
++#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
++#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
++#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
++#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
++#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
++#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
++#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000
++#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
++#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
++#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
++#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000
++#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c
++#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
++#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
++#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
++#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
++#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
++#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
++#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME_MASK 0xfff
++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME__SHIFT 0x0
++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE_MASK 0x80000000
++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE__SHIFT 0x1f
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF__SHIFT 0x0
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC_MASK 0x4
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB_MASK 0x8
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB__SHIFT 0x3
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP_MASK 0x10
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP__SHIFT 0x4
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA_MASK 0x20
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA__SHIFT 0x5
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE_MASK 0x40
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE__SHIFT 0x6
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB_MASK 0x80
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB__SHIFT 0x7
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8_MASK 0x100
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8__SHIFT 0x8
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM_MASK 0x200
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM__SHIFT 0x9
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD_MASK 0x400
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD__SHIFT 0xa
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0_MASK 0x800
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0__SHIFT 0xb
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1_MASK 0x1000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1__SHIFT 0xc
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP_MASK 0x2000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP__SHIFT 0xd
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM_MASK 0x4000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM__SHIFT 0xe
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB_MASK 0x8000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB__SHIFT 0xf
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0_MASK 0x10000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0__SHIFT 0x10
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1_MASK 0x20000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1__SHIFT 0x11
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2_MASK 0x40000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2__SHIFT 0x12
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3_MASK 0x80000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3__SHIFT 0x13
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4_MASK 0x100000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4__SHIFT 0x14
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5_MASK 0x200000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5__SHIFT 0x15
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6_MASK 0x400000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6__SHIFT 0x16
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7_MASK 0x800000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7__SHIFT 0x17
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0_MASK 0x1000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0__SHIFT 0x18
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1_MASK 0x2000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1__SHIFT 0x19
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2_MASK 0x4000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2__SHIFT 0x1a
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3_MASK 0x8000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3__SHIFT 0x1b
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4_MASK 0x10000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4__SHIFT 0x1c
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5_MASK 0x20000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5__SHIFT 0x1d
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6_MASK 0x40000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6__SHIFT 0x1e
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7_MASK 0x80000000
++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7__SHIFT 0x1f
++#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1
++#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF__SHIFT 0x0
++#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2
++#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1
++#define SRBM_CREDIT_RESET__CREDIT_RESET_DC_MASK 0x4
++#define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2
++#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB_MASK 0x8
++#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB__SHIFT 0x3
++#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP_MASK 0x10
++#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP__SHIFT 0x4
++#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA_MASK 0x20
++#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA__SHIFT 0x5
++#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE_MASK 0x40
++#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE__SHIFT 0x6
++#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB_MASK 0x80
++#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB__SHIFT 0x7
++#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8_MASK 0x100
++#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8__SHIFT 0x8
++#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM_MASK 0x200
++#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM__SHIFT 0x9
++#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD_MASK 0x400
++#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD__SHIFT 0xa
++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0_MASK 0x800
++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0__SHIFT 0xb
++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1_MASK 0x1000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1__SHIFT 0xc
++#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP_MASK 0x2000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP__SHIFT 0xd
++#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM_MASK 0x4000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM__SHIFT 0xe
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB_MASK 0x8000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB__SHIFT 0xf
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0_MASK 0x10000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0__SHIFT 0x10
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1_MASK 0x20000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1__SHIFT 0x11
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2_MASK 0x40000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2__SHIFT 0x12
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3_MASK 0x80000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3__SHIFT 0x13
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4_MASK 0x100000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4__SHIFT 0x14
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5_MASK 0x200000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5__SHIFT 0x15
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6_MASK 0x400000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6__SHIFT 0x16
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7_MASK 0x800000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7__SHIFT 0x17
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0_MASK 0x1000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0__SHIFT 0x18
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1_MASK 0x2000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1__SHIFT 0x19
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2_MASK 0x4000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2__SHIFT 0x1a
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3_MASK 0x8000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3__SHIFT 0x1b
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4_MASK 0x10000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4__SHIFT 0x1c
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5_MASK 0x20000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5__SHIFT 0x1d
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6_MASK 0x40000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6__SHIFT 0x1e
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7_MASK 0x80000000
++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7__SHIFT 0x1f
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
++#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
++#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800
++#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
++#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2
++#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
++#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400
++#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
++#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000
++#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
++#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000
++#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e
++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
++#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
++#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
++#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
++#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
++#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
++#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
++#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
++#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
++#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
++#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
++#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
++#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
++#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
++#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
++#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
++#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
++#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
++#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
++#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
++#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
++#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
++#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
++#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
++#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
++#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
++#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
++#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
++#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
++#define DH_TEST__DH_TEST_MASK 0x1
++#define DH_TEST__DH_TEST__SHIFT 0x0
++#define KHFS0__RESERVED_MASK 0xffffffff
++#define KHFS0__RESERVED__SHIFT 0x0
++#define KHFS1__RESERVED_MASK 0xffffffff
++#define KHFS1__RESERVED__SHIFT 0x0
++#define KHFS2__RESERVED_MASK 0xffffffff
++#define KHFS2__RESERVED__SHIFT 0x0
++#define KHFS3__RESERVED_MASK 0xffffffff
++#define KHFS3__RESERVED__SHIFT 0x0
++#define KSESSION0__RESERVED_MASK 0xffffffff
++#define KSESSION0__RESERVED__SHIFT 0x0
++#define KSESSION1__RESERVED_MASK 0xffffffff
++#define KSESSION1__RESERVED__SHIFT 0x0
++#define KSESSION2__RESERVED_MASK 0xffffffff
++#define KSESSION2__RESERVED__SHIFT 0x0
++#define KSESSION3__RESERVED_MASK 0xffffffff
++#define KSESSION3__RESERVED__SHIFT 0x0
++#define KSIG0__RESERVED_MASK 0xffffffff
++#define KSIG0__RESERVED__SHIFT 0x0
++#define KSIG1__RESERVED_MASK 0xffffffff
++#define KSIG1__RESERVED__SHIFT 0x0
++#define KSIG2__RESERVED_MASK 0xffffffff
++#define KSIG2__RESERVED__SHIFT 0x0
++#define KSIG3__RESERVED_MASK 0xffffffff
++#define KSIG3__RESERVED__SHIFT 0x0
++#define EXP0__RESERVED_MASK 0xffffffff
++#define EXP0__RESERVED__SHIFT 0x0
++#define EXP1__RESERVED_MASK 0xffffffff
++#define EXP1__RESERVED__SHIFT 0x0
++#define EXP2__RESERVED_MASK 0xffffffff
++#define EXP2__RESERVED__SHIFT 0x0
++#define EXP3__RESERVED_MASK 0xffffffff
++#define EXP3__RESERVED__SHIFT 0x0
++#define EXP4__RESERVED_MASK 0xffffffff
++#define EXP4__RESERVED__SHIFT 0x0
++#define EXP5__RESERVED_MASK 0xffffffff
++#define EXP5__RESERVED__SHIFT 0x0
++#define EXP6__RESERVED_MASK 0xffffffff
++#define EXP6__RESERVED__SHIFT 0x0
++#define EXP7__RESERVED_MASK 0xffffffff
++#define EXP7__RESERVED__SHIFT 0x0
++#define LX0__RESERVED_MASK 0xffffffff
++#define LX0__RESERVED__SHIFT 0x0
++#define LX1__RESERVED_MASK 0xffffffff
++#define LX1__RESERVED__SHIFT 0x0
++#define LX2__RESERVED_MASK 0xffffffff
++#define LX2__RESERVED__SHIFT 0x0
++#define LX3__RESERVED_MASK 0xffffffff
++#define LX3__RESERVED__SHIFT 0x0
++#define CLIENT2_K0__RESERVED_MASK 0xffffffff
++#define CLIENT2_K0__RESERVED__SHIFT 0x0
++#define CLIENT2_K1__RESERVED_MASK 0xffffffff
++#define CLIENT2_K1__RESERVED__SHIFT 0x0
++#define CLIENT2_K2__RESERVED_MASK 0xffffffff
++#define CLIENT2_K2__RESERVED__SHIFT 0x0
++#define CLIENT2_K3__RESERVED_MASK 0xffffffff
++#define CLIENT2_K3__RESERVED__SHIFT 0x0
++#define CLIENT2_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK0__RESERVED__SHIFT 0x0
++#define CLIENT2_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK1__RESERVED__SHIFT 0x0
++#define CLIENT2_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK2__RESERVED__SHIFT 0x0
++#define CLIENT2_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT2_CK3__RESERVED__SHIFT 0x0
++#define CLIENT2_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD0__RESERVED__SHIFT 0x0
++#define CLIENT2_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD1__RESERVED__SHIFT 0x0
++#define CLIENT2_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD2__RESERVED__SHIFT 0x0
++#define CLIENT2_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT2_CD3__RESERVED__SHIFT 0x0
++#define CLIENT2_BM__RESERVED_MASK 0xffffffff
++#define CLIENT2_BM__RESERVED__SHIFT 0x0
++#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT2_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT0_K0__RESERVED_MASK 0xffffffff
++#define CLIENT0_K0__RESERVED__SHIFT 0x0
++#define CLIENT0_K1__RESERVED_MASK 0xffffffff
++#define CLIENT0_K1__RESERVED__SHIFT 0x0
++#define CLIENT0_K2__RESERVED_MASK 0xffffffff
++#define CLIENT0_K2__RESERVED__SHIFT 0x0
++#define CLIENT0_K3__RESERVED_MASK 0xffffffff
++#define CLIENT0_K3__RESERVED__SHIFT 0x0
++#define CLIENT0_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK0__RESERVED__SHIFT 0x0
++#define CLIENT0_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK1__RESERVED__SHIFT 0x0
++#define CLIENT0_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK2__RESERVED__SHIFT 0x0
++#define CLIENT0_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT0_CK3__RESERVED__SHIFT 0x0
++#define CLIENT0_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD0__RESERVED__SHIFT 0x0
++#define CLIENT0_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD1__RESERVED__SHIFT 0x0
++#define CLIENT0_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD2__RESERVED__SHIFT 0x0
++#define CLIENT0_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT0_CD3__RESERVED__SHIFT 0x0
++#define CLIENT0_BM__RESERVED_MASK 0xffffffff
++#define CLIENT0_BM__RESERVED__SHIFT 0x0
++#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT0_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT1_K0__RESERVED_MASK 0xffffffff
++#define CLIENT1_K0__RESERVED__SHIFT 0x0
++#define CLIENT1_K1__RESERVED_MASK 0xffffffff
++#define CLIENT1_K1__RESERVED__SHIFT 0x0
++#define CLIENT1_K2__RESERVED_MASK 0xffffffff
++#define CLIENT1_K2__RESERVED__SHIFT 0x0
++#define CLIENT1_K3__RESERVED_MASK 0xffffffff
++#define CLIENT1_K3__RESERVED__SHIFT 0x0
++#define CLIENT1_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK0__RESERVED__SHIFT 0x0
++#define CLIENT1_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK1__RESERVED__SHIFT 0x0
++#define CLIENT1_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK2__RESERVED__SHIFT 0x0
++#define CLIENT1_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT1_CK3__RESERVED__SHIFT 0x0
++#define CLIENT1_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD0__RESERVED__SHIFT 0x0
++#define CLIENT1_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD1__RESERVED__SHIFT 0x0
++#define CLIENT1_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD2__RESERVED__SHIFT 0x0
++#define CLIENT1_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT1_CD3__RESERVED__SHIFT 0x0
++#define CLIENT1_BM__RESERVED_MASK 0xffffffff
++#define CLIENT1_BM__RESERVED__SHIFT 0x0
++#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0
++#define KEFUSE0__RESERVED_MASK 0xffffffff
++#define KEFUSE0__RESERVED__SHIFT 0x0
++#define KEFUSE1__RESERVED_MASK 0xffffffff
++#define KEFUSE1__RESERVED__SHIFT 0x0
++#define KEFUSE2__RESERVED_MASK 0xffffffff
++#define KEFUSE2__RESERVED__SHIFT 0x0
++#define KEFUSE3__RESERVED_MASK 0xffffffff
++#define KEFUSE3__RESERVED__SHIFT 0x0
++#define HFS_SEED0__RESERVED_MASK 0xffffffff
++#define HFS_SEED0__RESERVED__SHIFT 0x0
++#define HFS_SEED1__RESERVED_MASK 0xffffffff
++#define HFS_SEED1__RESERVED__SHIFT 0x0
++#define HFS_SEED2__RESERVED_MASK 0xffffffff
++#define HFS_SEED2__RESERVED__SHIFT 0x0
++#define HFS_SEED3__RESERVED_MASK 0xffffffff
++#define HFS_SEED3__RESERVED__SHIFT 0x0
++#define RINGOSC_MASK__MASK_MASK 0xffff
++#define RINGOSC_MASK__MASK__SHIFT 0x0
++#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0
++#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff
++#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT3_K0__RESERVED_MASK 0xffffffff
++#define CLIENT3_K0__RESERVED__SHIFT 0x0
++#define CLIENT3_K1__RESERVED_MASK 0xffffffff
++#define CLIENT3_K1__RESERVED__SHIFT 0x0
++#define CLIENT3_K2__RESERVED_MASK 0xffffffff
++#define CLIENT3_K2__RESERVED__SHIFT 0x0
++#define CLIENT3_K3__RESERVED_MASK 0xffffffff
++#define CLIENT3_K3__RESERVED__SHIFT 0x0
++#define CLIENT3_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK0__RESERVED__SHIFT 0x0
++#define CLIENT3_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK1__RESERVED__SHIFT 0x0
++#define CLIENT3_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK2__RESERVED__SHIFT 0x0
++#define CLIENT3_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT3_CK3__RESERVED__SHIFT 0x0
++#define CLIENT3_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD0__RESERVED__SHIFT 0x0
++#define CLIENT3_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD1__RESERVED__SHIFT 0x0
++#define CLIENT3_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD2__RESERVED__SHIFT 0x0
++#define CLIENT3_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT3_CD3__RESERVED__SHIFT 0x0
++#define CLIENT3_BM__RESERVED_MASK 0xffffffff
++#define CLIENT3_BM__RESERVED__SHIFT 0x0
++#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT3_STATUS__RESERVED__SHIFT 0x0
++#define CLIENT4_OFFSET_HI__RESERVED_MASK 0xffffffff
++#define CLIENT4_OFFSET_HI__RESERVED__SHIFT 0x0
++#define CLIENT4_K0__RESERVED_MASK 0xffffffff
++#define CLIENT4_K0__RESERVED__SHIFT 0x0
++#define CLIENT4_K1__RESERVED_MASK 0xffffffff
++#define CLIENT4_K1__RESERVED__SHIFT 0x0
++#define CLIENT4_K2__RESERVED_MASK 0xffffffff
++#define CLIENT4_K2__RESERVED__SHIFT 0x0
++#define CLIENT4_K3__RESERVED_MASK 0xffffffff
++#define CLIENT4_K3__RESERVED__SHIFT 0x0
++#define CLIENT4_CK0__RESERVED_MASK 0xffffffff
++#define CLIENT4_CK0__RESERVED__SHIFT 0x0
++#define CLIENT4_CK1__RESERVED_MASK 0xffffffff
++#define CLIENT4_CK1__RESERVED__SHIFT 0x0
++#define CLIENT4_CK2__RESERVED_MASK 0xffffffff
++#define CLIENT4_CK2__RESERVED__SHIFT 0x0
++#define CLIENT4_CK3__RESERVED_MASK 0xffffffff
++#define CLIENT4_CK3__RESERVED__SHIFT 0x0
++#define CLIENT4_CD0__RESERVED_MASK 0xffffffff
++#define CLIENT4_CD0__RESERVED__SHIFT 0x0
++#define CLIENT4_CD1__RESERVED_MASK 0xffffffff
++#define CLIENT4_CD1__RESERVED__SHIFT 0x0
++#define CLIENT4_CD2__RESERVED_MASK 0xffffffff
++#define CLIENT4_CD2__RESERVED__SHIFT 0x0
++#define CLIENT4_CD3__RESERVED_MASK 0xffffffff
++#define CLIENT4_CD3__RESERVED__SHIFT 0x0
++#define CLIENT4_BM__RESERVED_MASK 0xffffffff
++#define CLIENT4_BM__RESERVED__SHIFT 0x0
++#define CLIENT4_OFFSET__RESERVED_MASK 0xffffffff
++#define CLIENT4_OFFSET__RESERVED__SHIFT 0x0
++#define CLIENT4_STATUS__RESERVED_MASK 0xffffffff
++#define CLIENT4_STATUS__RESERVED__SHIFT 0x0
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100
++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
++#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff
++#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0
++#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff
++#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
++#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2
++#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
++#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA0_HASH__BANK_BITS_MASK 0x70
++#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA0_STATUS_REG__IDLE_MASK 0x1
++#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
++#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3
++#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
++#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_F32_CNTL__HALT_MASK 0x1
++#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA0_F32_CNTL__STEP_MASK 0x2
++#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
++#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
++#define SDMA0_FREEZE__FREEZE_MASK 0x10
++#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA0_FREEZE__FROZEN_MASK 0x20
++#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
++#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
++#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
++#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
++#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
++#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
++#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
++#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
++#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
++#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
++#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
++#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
++#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
++#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
++#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
++#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
++#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA0_VM_CNTL__CMD_MASK 0xf
++#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
++#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
++#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff
++#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
++#define SDMA0_STATUS2_REG__ID_MASK 0x3
++#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
++#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc
++#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
++#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000
++#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe
++#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
++#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
++#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1
++#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
++#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0
++#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
++#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
++#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
++#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
++#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
++#define SDMA0_ID__DEVICE_ID_MASK 0xff
++#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
++#define SDMA0_VERSION__VALUE_MASK 0xffff
++#define SDMA0_VERSION__VALUE__SHIFT 0x0
++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
++#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
++#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
++#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
++#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
++#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xffff
++#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0
++#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000
++#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2
++#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
++#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x40
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x6
++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80
++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4
++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5
++#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40
++#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6
++#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80
++#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7
++#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
++#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa
++#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800
++#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf
++#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
++#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
++#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
++#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
++#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12
++#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15
++#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000
++#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19
++#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a
++#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b
++#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c
++#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d
++#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
++#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2
++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8
++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa
++#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800
++#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xb
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff
++#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
++#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2
++#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
++#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA1_HASH__BANK_BITS_MASK 0x70
++#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA1_STATUS_REG__IDLE_MASK 0x1
++#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
++#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3
++#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
++#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_F32_CNTL__HALT_MASK 0x1
++#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA1_F32_CNTL__STEP_MASK 0x2
++#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
++#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
++#define SDMA1_FREEZE__FREEZE_MASK 0x10
++#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA1_FREEZE__FROZEN_MASK 0x20
++#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
++#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
++#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA1_VM_CNTL__CMD_MASK 0xf
++#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
++#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
++#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff
++#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
++#define SDMA1_STATUS2_REG__ID_MASK 0x3
++#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
++#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc
++#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
++#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000
++#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe
++#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
++#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
++#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1
++#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
++#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0
++#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
++#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
++#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
++#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
++#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
++#define SDMA1_ID__DEVICE_ID_MASK 0xff
++#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
++#define SDMA1_VERSION__VALUE_MASK 0xffff
++#define SDMA1_VERSION__VALUE__SHIFT 0x0
++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
++#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
++#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
++#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
++#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
++#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xffff
++#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0
++#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000
++#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2
++#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
++#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
++#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000
++#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x40
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x6
++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80
++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4
++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5
++#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40
++#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6
++#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80
++#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7
++#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
++#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa
++#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800
++#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf
++#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
++#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
++#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
++#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
++#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12
++#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15
++#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000
++#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16
++#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a
++#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b
++#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c
++#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d
++#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
++#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2
++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8
++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa
++#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800
++#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xb
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
++#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
++#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
++#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
++#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
++#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
++#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
++#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
++#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
++#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
++#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
++#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
++#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
++#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
++#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
++#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
++#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
++#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
++#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
++#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
++#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
++#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
++#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
++#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
++#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
++#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000
++#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16
++#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000
++#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17
++#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
++#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
++#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
++#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
++#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
++#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
++#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
++#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
++#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
++#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
++#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
++#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
++#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000
++#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
++#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000
++#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
++#define HDP_VF_ENABLE__VF_EN_MASK 0x1
++#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0
++#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000
++#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
++#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
++#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
++#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
++#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
++#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
++#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
++#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
++#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
++#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
++#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
++#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
++#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
++#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
++#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
++#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
++#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
++#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
++#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
++#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
++
++#endif /* OSS_3_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0017-yocto-amd-drm-amdgpu-add-UVD-5-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0017-yocto-amd-drm-amdgpu-add-UVD-5-0-register-headers.patch
new file mode 100644
index 00000000..834708d6
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0017-yocto-amd-drm-amdgpu-add-UVD-5-0-register-headers.patch
@@ -0,0 +1,5647 @@
+From 972ad9ae7da7f81a2822cbd39492775d146de111 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:27:02 -0400
+Subject: drm/amdgpu: add OSS 3.0.1 register headers
+
+These are register headers for the OSS (OS Services)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h
+new file mode 100644
+index 0000000..bdbb829
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h
+@@ -0,0 +1,593 @@
++/*
++ * OSS_3_0_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_3_0_1_D_H
++#define OSS_3_0_1_D_H
++
++#define mmIH_VMID_0_LUT                                                         0xe00
++#define mmIH_VMID_1_LUT                                                         0xe01
++#define mmIH_VMID_2_LUT                                                         0xe02
++#define mmIH_VMID_3_LUT                                                         0xe03
++#define mmIH_VMID_4_LUT                                                         0xe04
++#define mmIH_VMID_5_LUT                                                         0xe05
++#define mmIH_VMID_6_LUT                                                         0xe06
++#define mmIH_VMID_7_LUT                                                         0xe07
++#define mmIH_VMID_8_LUT                                                         0xe08
++#define mmIH_VMID_9_LUT                                                         0xe09
++#define mmIH_VMID_10_LUT                                                        0xe0a
++#define mmIH_VMID_11_LUT                                                        0xe0b
++#define mmIH_VMID_12_LUT                                                        0xe0c
++#define mmIH_VMID_13_LUT                                                        0xe0d
++#define mmIH_VMID_14_LUT                                                        0xe0e
++#define mmIH_VMID_15_LUT                                                        0xe0f
++#define mmIH_RB_CNTL                                                            0xe30
++#define mmIH_RB_BASE                                                            0xe31
++#define mmIH_RB_RPTR                                                            0xe32
++#define mmIH_RB_WPTR                                                            0xe33
++#define mmIH_RB_WPTR_ADDR_HI                                                    0xe34
++#define mmIH_RB_WPTR_ADDR_LO                                                    0xe35
++#define mmIH_CNTL                                                               0xe36
++#define mmIH_LEVEL_STATUS                                                       0xe37
++#define mmIH_STATUS                                                             0xe38
++#define mmIH_PERFMON_CNTL                                                       0xe39
++#define mmIH_PERFCOUNTER0_RESULT                                                0xe3a
++#define mmIH_PERFCOUNTER1_RESULT                                                0xe3b
++#define mmIH_DSM_MATCH_VALUE_BIT_31_0                                           0xe3d
++#define mmIH_DSM_MATCH_VALUE_BIT_63_32                                          0xe3e
++#define mmIH_DSM_MATCH_VALUE_BIT_95_64                                          0xe3f
++#define mmIH_DSM_MATCH_FIELD_CONTROL                                            0xe40
++#define mmIH_DSM_MATCH_DATA_CONTROL                                             0xe41
++#define mmIH_VERSION                                                            0xe48
++#define mmSEM_MCIF_CONFIG                                                       0xf90
++#define mmSEM_PERFMON_CNTL                                                      0xf91
++#define mmSEM_PERFCOUNTER0_RESULT                                               0xf92
++#define mmSEM_PERFCOUNTER1_RESULT                                               0xf93
++#define mmSEM_VF_ENABLE                                                         0xf95
++#define mmSEM_ACTIVE_FCN_ID                                                     0xf97
++#define mmSEM_VIRT_RESET_REQ                                                    0xf98
++#define mmSEM_STATUS                                                            0xf99
++#define mmSEM_EDC_CONFIG                                                        0xf9a
++#define mmSEM_MAILBOX_CLIENTCONFIG                                              0xf9b
++#define mmSEM_MAILBOX                                                           0xf9c
++#define mmSEM_MAILBOX_CONTROL                                                   0xf9d
++#define mmSEM_CHICKEN_BITS                                                      0xf9e
++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA                                        0xf9f
++#define mmSRBM_CNTL                                                             0x390
++#define mmSRBM_GFX_CNTL                                                         0x391
++#define mmSRBM_READ_CNTL                                                        0x392
++#define mmSRBM_STATUS2                                                          0x393
++#define mmSRBM_STATUS                                                           0x394
++#define mmSRBM_STATUS3                                                          0x395
++#define mmSRBM_SOFT_RESET                                                       0x398
++#define mmSRBM_DEBUG_CNTL                                                       0x399
++#define mmSRBM_DEBUG_DATA                                                       0x39a
++#define mmSRBM_CHIP_REVISION                                                    0x39b
++#define mmCC_SYS_RB_REDUNDANCY                                                  0x39f
++#define mmCC_SYS_RB_BACKEND_DISABLE                                             0x3a0
++#define mmGC_USER_SYS_RB_BACKEND_DISABLE                                        0x3a1
++#define mmSRBM_MC_CLKEN_CNTL                                                    0x3b3
++#define mmSRBM_SYS_CLKEN_CNTL                                                   0x3b4
++#define mmSRBM_VCE_CLKEN_CNTL                                                   0x3b5
++#define mmSRBM_UVD_CLKEN_CNTL                                                   0x3b6
++#define mmSRBM_SDMA_CLKEN_CNTL                                                  0x3b7
++#define mmSRBM_SAM_CLKEN_CNTL                                                   0x3b8
++#define mmSRBM_ISP_CLKEN_CNTL                                                   0x3b9
++#define mmSRBM_VP8_CLKEN_CNTL                                                   0x3ba
++#define mmSRBM_DEBUG                                                            0x3a4
++#define mmSRBM_DEBUG_SNAPSHOT                                                   0x3a5
++#define mmSRBM_DEBUG_SNAPSHOT2                                                  0x3ad
++#define mmSRBM_READ_ERROR                                                       0x3a6
++#define mmSRBM_READ_ERROR2                                                      0x3ae
++#define mmSRBM_INT_CNTL                                                         0x3a8
++#define mmSRBM_INT_STATUS                                                       0x3a9
++#define mmSRBM_INT_ACK                                                          0x3aa
++#define mmSRBM_FIREWALL_ERROR_SRC                                               0x3ab
++#define mmSRBM_FIREWALL_ERROR_ADDR                                              0x3ac
++#define mmSRBM_DSM_TRIG_CNTL0                                                   0x3af
++#define mmSRBM_DSM_TRIG_CNTL1                                                   0x3b0
++#define mmSRBM_DSM_TRIG_MASK0                                                   0x3b1
++#define mmSRBM_DSM_TRIG_MASK1                                                   0x3b2
++#define mmSRBM_PERFMON_CNTL                                                     0x7c00
++#define mmSRBM_PERFCOUNTER0_SELECT                                              0x7c01
++#define mmSRBM_PERFCOUNTER1_SELECT                                              0x7c02
++#define mmSRBM_PERFCOUNTER0_LO                                                  0x7c03
++#define mmSRBM_PERFCOUNTER0_HI                                                  0x7c04
++#define mmSRBM_PERFCOUNTER1_LO                                                  0x7c05
++#define mmSRBM_PERFCOUNTER1_HI                                                  0x7c06
++#define mmSRBM_CAM_INDEX                                                        0xfe34
++#define mmSRBM_CAM_DATA                                                         0xfe35
++#define mmSRBM_MC_DOMAIN_ADDR0                                                  0xfa00
++#define mmSRBM_MC_DOMAIN_ADDR1                                                  0xfa01
++#define mmSRBM_MC_DOMAIN_ADDR2                                                  0xfa02
++#define mmSRBM_MC_DOMAIN_ADDR3                                                  0xfa03
++#define mmSRBM_MC_DOMAIN_ADDR4                                                  0xfa04
++#define mmSRBM_MC_DOMAIN_ADDR5                                                  0xfa05
++#define mmSRBM_MC_DOMAIN_ADDR6                                                  0xfa06
++#define mmSRBM_SYS_DOMAIN_ADDR0                                                 0xfa08
++#define mmSRBM_SYS_DOMAIN_ADDR1                                                 0xfa09
++#define mmSRBM_SYS_DOMAIN_ADDR2                                                 0xfa0a
++#define mmSRBM_SYS_DOMAIN_ADDR3                                                 0xfa0b
++#define mmSRBM_SYS_DOMAIN_ADDR4                                                 0xfa0c
++#define mmSRBM_SYS_DOMAIN_ADDR5                                                 0xfa0d
++#define mmSRBM_SYS_DOMAIN_ADDR6                                                 0xfa0e
++#define mmSRBM_SDMA_DOMAIN_ADDR0                                                0xfa10
++#define mmSRBM_SDMA_DOMAIN_ADDR1                                                0xfa11
++#define mmSRBM_SDMA_DOMAIN_ADDR2                                                0xfa12
++#define mmSRBM_SDMA_DOMAIN_ADDR3                                                0xfa13
++#define mmSRBM_UVD_DOMAIN_ADDR0                                                 0xfa14
++#define mmSRBM_UVD_DOMAIN_ADDR1                                                 0xfa15
++#define mmSRBM_UVD_DOMAIN_ADDR2                                                 0xfa16
++#define mmSRBM_VCE_DOMAIN_ADDR0                                                 0xfa18
++#define mmSRBM_VCE_DOMAIN_ADDR1                                                 0xfa19
++#define mmSRBM_VCE_DOMAIN_ADDR2                                                 0xfa1a
++#define mmSRBM_ISP_DOMAIN_ADDR0                                                 0xfa20
++#define mmSRBM_ISP_DOMAIN_ADDR1                                                 0xfa21
++#define mmSRBM_ISP_DOMAIN_ADDR2                                                 0xfa22
++#define mmSRBM_VP8_DOMAIN_ADDR0                                                 0xfa24
++#define mmSYS_GRBM_GFX_INDEX_SELECT                                             0xfa2c
++#define mmSYS_GRBM_GFX_INDEX_DATA                                               0xfa2d
++#define mmSRBM_GFX_CNTL_SELECT                                                  0xfa2e
++#define mmSRBM_GFX_CNTL_DATA                                                    0xfa2f
++#define mmSRBM_VF_ENABLE                                                        0xfa30
++#define mmSRBM_VIRT_CNTL                                                        0xfa31
++#define mmSRBM_VIRT_RESET_REQ                                                   0xfa32
++#define mmSDMA0_UCODE_ADDR                                                      0x3400
++#define mmSDMA0_UCODE_DATA                                                      0x3401
++#define mmSDMA0_POWER_CNTL                                                      0x3402
++#define mmSDMA0_CLK_CTRL                                                        0x3403
++#define mmSDMA0_CNTL                                                            0x3404
++#define mmSDMA0_CHICKEN_BITS                                                    0x3405
++#define mmSDMA0_TILING_CONFIG                                                   0x3406
++#define mmSDMA0_HASH                                                            0x3407
++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3409
++#define mmSDMA0_RB_RPTR_FETCH                                                   0x340a
++#define mmSDMA0_IB_OFFSET_FETCH                                                 0x340b
++#define mmSDMA0_PROGRAM                                                         0x340c
++#define mmSDMA0_STATUS_REG                                                      0x340d
++#define mmSDMA0_STATUS1_REG                                                     0x340e
++#define mmSDMA0_RD_BURST_CNTL                                                   0x340f
++#define mmSDMA0_PERFMON_CNTL                                                    0x9000
++#define mmSDMA0_PERFCOUNTER0_RESULT                                             0x9001
++#define mmSDMA0_PERFCOUNTER1_RESULT                                             0x9002
++#define mmSDMA0_F32_CNTL                                                        0x3412
++#define mmSDMA0_FREEZE                                                          0x3413
++#define mmSDMA0_PHASE0_QUANTUM                                                  0x3414
++#define mmSDMA0_PHASE1_QUANTUM                                                  0x3415
++#define mmSDMA_POWER_GATING                                                     0x3416
++#define mmSDMA_PGFSM_CONFIG                                                     0x3417
++#define mmSDMA_PGFSM_WRITE                                                      0x3418
++#define mmSDMA_PGFSM_READ                                                       0x3419
++#define mmSDMA0_EDC_CONFIG                                                      0x341a
++#define mmSDMA0_BA_THRESHOLD                                                    0x341b
++#define mmSDMA0_ID                                                              0x341c
++#define mmSDMA0_VERSION                                                         0x341d
++#define mmSDMA0_VM_CNTL                                                         0x3420
++#define mmSDMA0_VM_CTX_LO                                                       0x3421
++#define mmSDMA0_VM_CTX_HI                                                       0x3422
++#define mmSDMA0_STATUS2_REG                                                     0x3423
++#define mmSDMA0_ACTIVE_FCN_ID                                                   0x3424
++#define mmSDMA0_VM_CTX_CNTL                                                     0x3425
++#define mmSDMA0_VIRT_RESET_REQ                                                  0x3426
++#define mmSDMA0_VF_ENABLE                                                       0x3427
++#define mmSDMA0_ATOMIC_CNTL                                                     0x3428
++#define mmSDMA0_ATOMIC_PREOP_LO                                                 0x3429
++#define mmSDMA0_ATOMIC_PREOP_HI                                                 0x342a
++#define mmSDMA0_ATCL1_CNTL                                                      0x342b
++#define mmSDMA0_ATCL1_WATERMK                                                   0x342c
++#define mmSDMA0_ATCL1_RD_STATUS                                                 0x342d
++#define mmSDMA0_ATCL1_WR_STATUS                                                 0x342e
++#define mmSDMA0_ATCL1_INV0                                                      0x342f
++#define mmSDMA0_ATCL1_INV1                                                      0x3430
++#define mmSDMA0_ATCL1_INV2                                                      0x3431
++#define mmSDMA0_ATCL1_RD_XNACK0                                                 0x3432
++#define mmSDMA0_ATCL1_RD_XNACK1                                                 0x3433
++#define mmSDMA0_ATCL1_WR_XNACK0                                                 0x3434
++#define mmSDMA0_ATCL1_WR_XNACK1                                                 0x3435
++#define mmSDMA0_ATCL1_TIMEOUT                                                   0x3436
++#define mmSDMA0_POWER_CNTL_IDLE                                                 0x3438
++#define mmSDMA0_PERF_REG_TYPE0                                                  0x3477
++#define mmSDMA0_CONTEXT_REG_TYPE0                                               0x3478
++#define mmSDMA0_CONTEXT_REG_TYPE1                                               0x3479
++#define mmSDMA0_CONTEXT_REG_TYPE2                                               0x347a
++#define mmSDMA0_PUB_REG_TYPE0                                                   0x347c
++#define mmSDMA0_PUB_REG_TYPE1                                                   0x347d
++#define mmSDMA0_GFX_RB_CNTL                                                     0x3480
++#define mmSDMA0_GFX_RB_BASE                                                     0x3481
++#define mmSDMA0_GFX_RB_BASE_HI                                                  0x3482
++#define mmSDMA0_GFX_RB_RPTR                                                     0x3483
++#define mmSDMA0_GFX_RB_WPTR                                                     0x3484
++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                           0x3485
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3486
++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3487
++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                             0x3488
++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                             0x3489
++#define mmSDMA0_GFX_IB_CNTL                                                     0x348a
++#define mmSDMA0_GFX_IB_RPTR                                                     0x348b
++#define mmSDMA0_GFX_IB_OFFSET                                                   0x348c
++#define mmSDMA0_GFX_IB_BASE_LO                                                  0x348d
++#define mmSDMA0_GFX_IB_BASE_HI                                                  0x348e
++#define mmSDMA0_GFX_IB_SIZE                                                     0x348f
++#define mmSDMA0_GFX_SKIP_CNTL                                                   0x3490
++#define mmSDMA0_GFX_CONTEXT_STATUS                                              0x3491
++#define mmSDMA0_GFX_DOORBELL                                                    0x3492
++#define mmSDMA0_GFX_CONTEXT_CNTL                                                0x3493
++#define mmSDMA0_GFX_VIRTUAL_ADDR                                                0x34a7
++#define mmSDMA0_GFX_APE1_CNTL                                                   0x34a8
++#define mmSDMA0_GFX_DOORBELL_LOG                                                0x34a9
++#define mmSDMA0_GFX_WATERMARK                                                   0x34aa
++#define mmSDMA0_GFX_CSA_ADDR_LO                                                 0x34ac
++#define mmSDMA0_GFX_CSA_ADDR_HI                                                 0x34ad
++#define mmSDMA0_GFX_IB_SUB_REMAIN                                               0x34af
++#define mmSDMA0_GFX_PREEMPT                                                     0x34b0
++#define mmSDMA0_GFX_DUMMY_REG                                                   0x34b1
++#define mmSDMA0_GFX_MIDCMD_DATA0                                                0x34c1
++#define mmSDMA0_GFX_MIDCMD_DATA1                                                0x34c2
++#define mmSDMA0_GFX_MIDCMD_DATA2                                                0x34c3
++#define mmSDMA0_GFX_MIDCMD_DATA3                                                0x34c4
++#define mmSDMA0_GFX_MIDCMD_DATA4                                                0x34c5
++#define mmSDMA0_GFX_MIDCMD_DATA5                                                0x34c6
++#define mmSDMA0_GFX_MIDCMD_DATA6                                                0x34c7
++#define mmSDMA0_GFX_MIDCMD_DATA7                                                0x34c8
++#define mmSDMA0_GFX_MIDCMD_DATA8                                                0x34c9
++#define mmSDMA0_GFX_MIDCMD_CNTL                                                 0x34ca
++#define mmSDMA0_RLC0_RB_CNTL                                                    0x3500
++#define mmSDMA0_RLC0_RB_BASE                                                    0x3501
++#define mmSDMA0_RLC0_RB_BASE_HI                                                 0x3502
++#define mmSDMA0_RLC0_RB_RPTR                                                    0x3503
++#define mmSDMA0_RLC0_RB_WPTR                                                    0x3504
++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                          0x3505
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3506
++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3507
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                            0x3508
++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                            0x3509
++#define mmSDMA0_RLC0_IB_CNTL                                                    0x350a
++#define mmSDMA0_RLC0_IB_RPTR                                                    0x350b
++#define mmSDMA0_RLC0_IB_OFFSET                                                  0x350c
++#define mmSDMA0_RLC0_IB_BASE_LO                                                 0x350d
++#define mmSDMA0_RLC0_IB_BASE_HI                                                 0x350e
++#define mmSDMA0_RLC0_IB_SIZE                                                    0x350f
++#define mmSDMA0_RLC0_SKIP_CNTL                                                  0x3510
++#define mmSDMA0_RLC0_CONTEXT_STATUS                                             0x3511
++#define mmSDMA0_RLC0_DOORBELL                                                   0x3512
++#define mmSDMA0_RLC0_VIRTUAL_ADDR                                               0x3527
++#define mmSDMA0_RLC0_APE1_CNTL                                                  0x3528
++#define mmSDMA0_RLC0_DOORBELL_LOG                                               0x3529
++#define mmSDMA0_RLC0_WATERMARK                                                  0x352a
++#define mmSDMA0_RLC0_CSA_ADDR_LO                                                0x352c
++#define mmSDMA0_RLC0_CSA_ADDR_HI                                                0x352d
++#define mmSDMA0_RLC0_IB_SUB_REMAIN                                              0x352f
++#define mmSDMA0_RLC0_PREEMPT                                                    0x3530
++#define mmSDMA0_RLC0_DUMMY_REG                                                  0x3531
++#define mmSDMA0_RLC0_MIDCMD_DATA0                                               0x3541
++#define mmSDMA0_RLC0_MIDCMD_DATA1                                               0x3542
++#define mmSDMA0_RLC0_MIDCMD_DATA2                                               0x3543
++#define mmSDMA0_RLC0_MIDCMD_DATA3                                               0x3544
++#define mmSDMA0_RLC0_MIDCMD_DATA4                                               0x3545
++#define mmSDMA0_RLC0_MIDCMD_DATA5                                               0x3546
++#define mmSDMA0_RLC0_MIDCMD_DATA6                                               0x3547
++#define mmSDMA0_RLC0_MIDCMD_DATA7                                               0x3548
++#define mmSDMA0_RLC0_MIDCMD_DATA8                                               0x3549
++#define mmSDMA0_RLC0_MIDCMD_CNTL                                                0x354a
++#define mmSDMA0_RLC1_RB_CNTL                                                    0x3580
++#define mmSDMA0_RLC1_RB_BASE                                                    0x3581
++#define mmSDMA0_RLC1_RB_BASE_HI                                                 0x3582
++#define mmSDMA0_RLC1_RB_RPTR                                                    0x3583
++#define mmSDMA0_RLC1_RB_WPTR                                                    0x3584
++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                          0x3585
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3586
++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3587
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                            0x3588
++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                            0x3589
++#define mmSDMA0_RLC1_IB_CNTL                                                    0x358a
++#define mmSDMA0_RLC1_IB_RPTR                                                    0x358b
++#define mmSDMA0_RLC1_IB_OFFSET                                                  0x358c
++#define mmSDMA0_RLC1_IB_BASE_LO                                                 0x358d
++#define mmSDMA0_RLC1_IB_BASE_HI                                                 0x358e
++#define mmSDMA0_RLC1_IB_SIZE                                                    0x358f
++#define mmSDMA0_RLC1_SKIP_CNTL                                                  0x3590
++#define mmSDMA0_RLC1_CONTEXT_STATUS                                             0x3591
++#define mmSDMA0_RLC1_DOORBELL                                                   0x3592
++#define mmSDMA0_RLC1_VIRTUAL_ADDR                                               0x35a7
++#define mmSDMA0_RLC1_APE1_CNTL                                                  0x35a8
++#define mmSDMA0_RLC1_DOORBELL_LOG                                               0x35a9
++#define mmSDMA0_RLC1_WATERMARK                                                  0x35aa
++#define mmSDMA0_RLC1_CSA_ADDR_LO                                                0x35ac
++#define mmSDMA0_RLC1_CSA_ADDR_HI                                                0x35ad
++#define mmSDMA0_RLC1_IB_SUB_REMAIN                                              0x35af
++#define mmSDMA0_RLC1_PREEMPT                                                    0x35b0
++#define mmSDMA0_RLC1_DUMMY_REG                                                  0x35b1
++#define mmSDMA0_RLC1_MIDCMD_DATA0                                               0x35c1
++#define mmSDMA0_RLC1_MIDCMD_DATA1                                               0x35c2
++#define mmSDMA0_RLC1_MIDCMD_DATA2                                               0x35c3
++#define mmSDMA0_RLC1_MIDCMD_DATA3                                               0x35c4
++#define mmSDMA0_RLC1_MIDCMD_DATA4                                               0x35c5
++#define mmSDMA0_RLC1_MIDCMD_DATA5                                               0x35c6
++#define mmSDMA0_RLC1_MIDCMD_DATA6                                               0x35c7
++#define mmSDMA0_RLC1_MIDCMD_DATA7                                               0x35c8
++#define mmSDMA0_RLC1_MIDCMD_DATA8                                               0x35c9
++#define mmSDMA0_RLC1_MIDCMD_CNTL                                                0x35ca
++#define mmSDMA1_UCODE_ADDR                                                      0x3600
++#define mmSDMA1_UCODE_DATA                                                      0x3601
++#define mmSDMA1_POWER_CNTL                                                      0x3602
++#define mmSDMA1_CLK_CTRL                                                        0x3603
++#define mmSDMA1_CNTL                                                            0x3604
++#define mmSDMA1_CHICKEN_BITS                                                    0x3605
++#define mmSDMA1_TILING_CONFIG                                                   0x3606
++#define mmSDMA1_HASH                                                            0x3607
++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                        0x3609
++#define mmSDMA1_RB_RPTR_FETCH                                                   0x360a
++#define mmSDMA1_IB_OFFSET_FETCH                                                 0x360b
++#define mmSDMA1_PROGRAM                                                         0x360c
++#define mmSDMA1_STATUS_REG                                                      0x360d
++#define mmSDMA1_STATUS1_REG                                                     0x360e
++#define mmSDMA1_RD_BURST_CNTL                                                   0x360f
++#define mmSDMA1_PERFMON_CNTL                                                    0x9010
++#define mmSDMA1_PERFCOUNTER0_RESULT                                             0x9011
++#define mmSDMA1_PERFCOUNTER1_RESULT                                             0x9012
++#define mmSDMA1_F32_CNTL                                                        0x3612
++#define mmSDMA1_FREEZE                                                          0x3613
++#define mmSDMA1_PHASE0_QUANTUM                                                  0x3614
++#define mmSDMA1_PHASE1_QUANTUM                                                  0x3615
++#define mmSDMA1_EDC_CONFIG                                                      0x361a
++#define mmSDMA1_BA_THRESHOLD                                                    0x361b
++#define mmSDMA1_ID                                                              0x361c
++#define mmSDMA1_VERSION                                                         0x361d
++#define mmSDMA1_VM_CNTL                                                         0x3620
++#define mmSDMA1_VM_CTX_LO                                                       0x3621
++#define mmSDMA1_VM_CTX_HI                                                       0x3622
++#define mmSDMA1_STATUS2_REG                                                     0x3623
++#define mmSDMA1_ACTIVE_FCN_ID                                                   0x3624
++#define mmSDMA1_VM_CTX_CNTL                                                     0x3625
++#define mmSDMA1_VIRT_RESET_REQ                                                  0x3626
++#define mmSDMA1_VF_ENABLE                                                       0x3627
++#define mmSDMA1_ATOMIC_CNTL                                                     0x3628
++#define mmSDMA1_ATOMIC_PREOP_LO                                                 0x3629
++#define mmSDMA1_ATOMIC_PREOP_HI                                                 0x362a
++#define mmSDMA1_ATCL1_CNTL                                                      0x362b
++#define mmSDMA1_ATCL1_WATERMK                                                   0x362c
++#define mmSDMA1_ATCL1_RD_STATUS                                                 0x362d
++#define mmSDMA1_ATCL1_WR_STATUS                                                 0x362e
++#define mmSDMA1_ATCL1_INV0                                                      0x362f
++#define mmSDMA1_ATCL1_INV1                                                      0x3630
++#define mmSDMA1_ATCL1_INV2                                                      0x3631
++#define mmSDMA1_ATCL1_RD_XNACK0                                                 0x3632
++#define mmSDMA1_ATCL1_RD_XNACK1                                                 0x3633
++#define mmSDMA1_ATCL1_WR_XNACK0                                                 0x3634
++#define mmSDMA1_ATCL1_WR_XNACK1                                                 0x3635
++#define mmSDMA1_ATCL1_TIMEOUT                                                   0x3636
++#define mmSDMA1_POWER_CNTL_IDLE                                                 0x3638
++#define mmSDMA1_PERF_REG_TYPE0                                                  0x3677
++#define mmSDMA1_CONTEXT_REG_TYPE0                                               0x3678
++#define mmSDMA1_CONTEXT_REG_TYPE1                                               0x3679
++#define mmSDMA1_CONTEXT_REG_TYPE2                                               0x367a
++#define mmSDMA1_PUB_REG_TYPE0                                                   0x367c
++#define mmSDMA1_PUB_REG_TYPE1                                                   0x367d
++#define mmSDMA1_GFX_RB_CNTL                                                     0x3680
++#define mmSDMA1_GFX_RB_BASE                                                     0x3681
++#define mmSDMA1_GFX_RB_BASE_HI                                                  0x3682
++#define mmSDMA1_GFX_RB_RPTR                                                     0x3683
++#define mmSDMA1_GFX_RB_WPTR                                                     0x3684
++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                           0x3685
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                        0x3686
++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                        0x3687
++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                             0x3688
++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                             0x3689
++#define mmSDMA1_GFX_IB_CNTL                                                     0x368a
++#define mmSDMA1_GFX_IB_RPTR                                                     0x368b
++#define mmSDMA1_GFX_IB_OFFSET                                                   0x368c
++#define mmSDMA1_GFX_IB_BASE_LO                                                  0x368d
++#define mmSDMA1_GFX_IB_BASE_HI                                                  0x368e
++#define mmSDMA1_GFX_IB_SIZE                                                     0x368f
++#define mmSDMA1_GFX_SKIP_CNTL                                                   0x3690
++#define mmSDMA1_GFX_CONTEXT_STATUS                                              0x3691
++#define mmSDMA1_GFX_DOORBELL                                                    0x3692
++#define mmSDMA1_GFX_CONTEXT_CNTL                                                0x3693
++#define mmSDMA1_GFX_VIRTUAL_ADDR                                                0x36a7
++#define mmSDMA1_GFX_APE1_CNTL                                                   0x36a8
++#define mmSDMA1_GFX_DOORBELL_LOG                                                0x36a9
++#define mmSDMA1_GFX_WATERMARK                                                   0x36aa
++#define mmSDMA1_GFX_CSA_ADDR_LO                                                 0x36ac
++#define mmSDMA1_GFX_CSA_ADDR_HI                                                 0x36ad
++#define mmSDMA1_GFX_IB_SUB_REMAIN                                               0x36af
++#define mmSDMA1_GFX_PREEMPT                                                     0x36b0
++#define mmSDMA1_GFX_DUMMY_REG                                                   0x36b1
++#define mmSDMA1_GFX_MIDCMD_DATA0                                                0x36c1
++#define mmSDMA1_GFX_MIDCMD_DATA1                                                0x36c2
++#define mmSDMA1_GFX_MIDCMD_DATA2                                                0x36c3
++#define mmSDMA1_GFX_MIDCMD_DATA3                                                0x36c4
++#define mmSDMA1_GFX_MIDCMD_DATA4                                                0x36c5
++#define mmSDMA1_GFX_MIDCMD_DATA5                                                0x36c6
++#define mmSDMA1_GFX_MIDCMD_DATA6                                                0x36c7
++#define mmSDMA1_GFX_MIDCMD_DATA7                                                0x36c8
++#define mmSDMA1_GFX_MIDCMD_DATA8                                                0x36c9
++#define mmSDMA1_GFX_MIDCMD_CNTL                                                 0x36ca
++#define mmSDMA1_RLC0_RB_CNTL                                                    0x3700
++#define mmSDMA1_RLC0_RB_BASE                                                    0x3701
++#define mmSDMA1_RLC0_RB_BASE_HI                                                 0x3702
++#define mmSDMA1_RLC0_RB_RPTR                                                    0x3703
++#define mmSDMA1_RLC0_RB_WPTR                                                    0x3704
++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                          0x3705
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                       0x3706
++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                       0x3707
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                            0x3708
++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                            0x3709
++#define mmSDMA1_RLC0_IB_CNTL                                                    0x370a
++#define mmSDMA1_RLC0_IB_RPTR                                                    0x370b
++#define mmSDMA1_RLC0_IB_OFFSET                                                  0x370c
++#define mmSDMA1_RLC0_IB_BASE_LO                                                 0x370d
++#define mmSDMA1_RLC0_IB_BASE_HI                                                 0x370e
++#define mmSDMA1_RLC0_IB_SIZE                                                    0x370f
++#define mmSDMA1_RLC0_SKIP_CNTL                                                  0x3710
++#define mmSDMA1_RLC0_CONTEXT_STATUS                                             0x3711
++#define mmSDMA1_RLC0_DOORBELL                                                   0x3712
++#define mmSDMA1_RLC0_VIRTUAL_ADDR                                               0x3727
++#define mmSDMA1_RLC0_APE1_CNTL                                                  0x3728
++#define mmSDMA1_RLC0_DOORBELL_LOG                                               0x3729
++#define mmSDMA1_RLC0_WATERMARK                                                  0x372a
++#define mmSDMA1_RLC0_CSA_ADDR_LO                                                0x372c
++#define mmSDMA1_RLC0_CSA_ADDR_HI                                                0x372d
++#define mmSDMA1_RLC0_IB_SUB_REMAIN                                              0x372f
++#define mmSDMA1_RLC0_PREEMPT                                                    0x3730
++#define mmSDMA1_RLC0_DUMMY_REG                                                  0x3731
++#define mmSDMA1_RLC0_MIDCMD_DATA0                                               0x3741
++#define mmSDMA1_RLC0_MIDCMD_DATA1                                               0x3742
++#define mmSDMA1_RLC0_MIDCMD_DATA2                                               0x3743
++#define mmSDMA1_RLC0_MIDCMD_DATA3                                               0x3744
++#define mmSDMA1_RLC0_MIDCMD_DATA4                                               0x3745
++#define mmSDMA1_RLC0_MIDCMD_DATA5                                               0x3746
++#define mmSDMA1_RLC0_MIDCMD_DATA6                                               0x3747
++#define mmSDMA1_RLC0_MIDCMD_DATA7                                               0x3748
++#define mmSDMA1_RLC0_MIDCMD_DATA8                                               0x3749
++#define mmSDMA1_RLC0_MIDCMD_CNTL                                                0x374a
++#define mmSDMA1_RLC1_RB_CNTL                                                    0x3780
++#define mmSDMA1_RLC1_RB_BASE                                                    0x3781
++#define mmSDMA1_RLC1_RB_BASE_HI                                                 0x3782
++#define mmSDMA1_RLC1_RB_RPTR                                                    0x3783
++#define mmSDMA1_RLC1_RB_WPTR                                                    0x3784
++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                          0x3785
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                       0x3786
++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                       0x3787
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                            0x3788
++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                            0x3789
++#define mmSDMA1_RLC1_IB_CNTL                                                    0x378a
++#define mmSDMA1_RLC1_IB_RPTR                                                    0x378b
++#define mmSDMA1_RLC1_IB_OFFSET                                                  0x378c
++#define mmSDMA1_RLC1_IB_BASE_LO                                                 0x378d
++#define mmSDMA1_RLC1_IB_BASE_HI                                                 0x378e
++#define mmSDMA1_RLC1_IB_SIZE                                                    0x378f
++#define mmSDMA1_RLC1_SKIP_CNTL                                                  0x3790
++#define mmSDMA1_RLC1_CONTEXT_STATUS                                             0x3791
++#define mmSDMA1_RLC1_DOORBELL                                                   0x3792
++#define mmSDMA1_RLC1_VIRTUAL_ADDR                                               0x37a7
++#define mmSDMA1_RLC1_APE1_CNTL                                                  0x37a8
++#define mmSDMA1_RLC1_DOORBELL_LOG                                               0x37a9
++#define mmSDMA1_RLC1_WATERMARK                                                  0x37aa
++#define mmSDMA1_RLC1_CSA_ADDR_LO                                                0x37ac
++#define mmSDMA1_RLC1_CSA_ADDR_HI                                                0x37ad
++#define mmSDMA1_RLC1_IB_SUB_REMAIN                                              0x37af
++#define mmSDMA1_RLC1_PREEMPT                                                    0x37b0
++#define mmSDMA1_RLC1_DUMMY_REG                                                  0x37b1
++#define mmSDMA1_RLC1_MIDCMD_DATA0                                               0x37c1
++#define mmSDMA1_RLC1_MIDCMD_DATA1                                               0x37c2
++#define mmSDMA1_RLC1_MIDCMD_DATA2                                               0x37c3
++#define mmSDMA1_RLC1_MIDCMD_DATA3                                               0x37c4
++#define mmSDMA1_RLC1_MIDCMD_DATA4                                               0x37c5
++#define mmSDMA1_RLC1_MIDCMD_DATA5                                               0x37c6
++#define mmSDMA1_RLC1_MIDCMD_DATA6                                               0x37c7
++#define mmSDMA1_RLC1_MIDCMD_DATA7                                               0x37c8
++#define mmSDMA1_RLC1_MIDCMD_DATA8                                               0x37c9
++#define mmSDMA1_RLC1_MIDCMD_CNTL                                                0x37ca
++#define mmHDP_HOST_PATH_CNTL                                                    0xb00
++#define mmHDP_NONSURFACE_BASE                                                   0xb01
++#define mmHDP_NONSURFACE_INFO                                                   0xb02
++#define mmHDP_NONSURFACE_SIZE                                                   0xb03
++#define mmHDP_NONSURF_FLAGS                                                     0xbc9
++#define mmHDP_NONSURF_FLAGS_CLR                                                 0xbca
++#define mmHDP_SW_SEMAPHORE                                                      0xbcb
++#define mmHDP_DEBUG0                                                            0xbcc
++#define mmHDP_DEBUG1                                                            0xbcd
++#define mmHDP_LAST_SURFACE_HIT                                                  0xbce
++#define mmHDP_TILING_CONFIG                                                     0xbcf
++#define mmHDP_SC_MULTI_CHIP_CNTL                                                0xbd0
++#define mmHDP_OUTSTANDING_REQ                                                   0xbd1
++#define mmHDP_ADDR_CONFIG                                                       0xbd2
++#define mmHDP_MISC_CNTL                                                         0xbd3
++#define mmHDP_MEM_POWER_LS                                                      0xbd4
++#define mmHDP_NONSURFACE_PREFETCH                                               0xbd5
++#define mmHDP_MEMIO_CNTL                                                        0xbf6
++#define mmHDP_MEMIO_ADDR                                                        0xbf7
++#define mmHDP_MEMIO_STATUS                                                      0xbf8
++#define mmHDP_MEMIO_WR_DATA                                                     0xbf9
++#define mmHDP_MEMIO_RD_DATA                                                     0xbfa
++#define mmHDP_VF_ENABLE                                                         0xbfb
++#define mmHDP_XDP_DIRECT2HDP_FIRST                                              0xc00
++#define mmHDP_XDP_D2H_FLUSH                                                     0xc01
++#define mmHDP_XDP_D2H_BAR_UPDATE                                                0xc02
++#define mmHDP_XDP_D2H_RSVD_3                                                    0xc03
++#define mmHDP_XDP_D2H_RSVD_4                                                    0xc04
++#define mmHDP_XDP_D2H_RSVD_5                                                    0xc05
++#define mmHDP_XDP_D2H_RSVD_6                                                    0xc06
++#define mmHDP_XDP_D2H_RSVD_7                                                    0xc07
++#define mmHDP_XDP_D2H_RSVD_8                                                    0xc08
++#define mmHDP_XDP_D2H_RSVD_9                                                    0xc09
++#define mmHDP_XDP_D2H_RSVD_10                                                   0xc0a
++#define mmHDP_XDP_D2H_RSVD_11                                                   0xc0b
++#define mmHDP_XDP_D2H_RSVD_12                                                   0xc0c
++#define mmHDP_XDP_D2H_RSVD_13                                                   0xc0d
++#define mmHDP_XDP_D2H_RSVD_14                                                   0xc0e
++#define mmHDP_XDP_D2H_RSVD_15                                                   0xc0f
++#define mmHDP_XDP_D2H_RSVD_16                                                   0xc10
++#define mmHDP_XDP_D2H_RSVD_17                                                   0xc11
++#define mmHDP_XDP_D2H_RSVD_18                                                   0xc12
++#define mmHDP_XDP_D2H_RSVD_19                                                   0xc13
++#define mmHDP_XDP_D2H_RSVD_20                                                   0xc14
++#define mmHDP_XDP_D2H_RSVD_21                                                   0xc15
++#define mmHDP_XDP_D2H_RSVD_22                                                   0xc16
++#define mmHDP_XDP_D2H_RSVD_23                                                   0xc17
++#define mmHDP_XDP_D2H_RSVD_24                                                   0xc18
++#define mmHDP_XDP_D2H_RSVD_25                                                   0xc19
++#define mmHDP_XDP_D2H_RSVD_26                                                   0xc1a
++#define mmHDP_XDP_D2H_RSVD_27                                                   0xc1b
++#define mmHDP_XDP_D2H_RSVD_28                                                   0xc1c
++#define mmHDP_XDP_D2H_RSVD_29                                                   0xc1d
++#define mmHDP_XDP_D2H_RSVD_30                                                   0xc1e
++#define mmHDP_XDP_D2H_RSVD_31                                                   0xc1f
++#define mmHDP_XDP_D2H_RSVD_32                                                   0xc20
++#define mmHDP_XDP_D2H_RSVD_33                                                   0xc21
++#define mmHDP_XDP_D2H_RSVD_34                                                   0xc22
++#define mmHDP_XDP_DIRECT2HDP_LAST                                               0xc23
++#define mmHDP_XDP_P2P_BAR_CFG                                                   0xc24
++#define mmHDP_XDP_P2P_MBX_OFFSET                                                0xc25
++#define mmHDP_XDP_P2P_MBX_ADDR0                                                 0xc26
++#define mmHDP_XDP_P2P_MBX_ADDR1                                                 0xc27
++#define mmHDP_XDP_P2P_MBX_ADDR2                                                 0xc28
++#define mmHDP_XDP_P2P_MBX_ADDR3                                                 0xc29
++#define mmHDP_XDP_P2P_MBX_ADDR4                                                 0xc2a
++#define mmHDP_XDP_P2P_MBX_ADDR5                                                 0xc2b
++#define mmHDP_XDP_P2P_MBX_ADDR6                                                 0xc2c
++#define mmHDP_XDP_HDP_MBX_MC_CFG                                                0xc2d
++#define mmHDP_XDP_HDP_MC_CFG                                                    0xc2e
++#define mmHDP_XDP_HST_CFG                                                       0xc2f
++#define mmHDP_XDP_SID_CFG                                                       0xc30
++#define mmHDP_XDP_HDP_IPH_CFG                                                   0xc31
++#define mmHDP_XDP_SRBM_CFG                                                      0xc32
++#define mmHDP_XDP_CGTT_BLK_CTRL                                                 0xc33
++#define mmHDP_XDP_P2P_BAR0                                                      0xc34
++#define mmHDP_XDP_P2P_BAR1                                                      0xc35
++#define mmHDP_XDP_P2P_BAR2                                                      0xc36
++#define mmHDP_XDP_P2P_BAR3                                                      0xc37
++#define mmHDP_XDP_P2P_BAR4                                                      0xc38
++#define mmHDP_XDP_P2P_BAR5                                                      0xc39
++#define mmHDP_XDP_P2P_BAR6                                                      0xc3a
++#define mmHDP_XDP_P2P_BAR7                                                      0xc3b
++#define mmHDP_XDP_FLUSH_ARMED_STS                                               0xc3c
++#define mmHDP_XDP_FLUSH_CNTR0_STS                                               0xc3d
++#define mmHDP_XDP_BUSY_STS                                                      0xc3e
++#define mmHDP_XDP_STICKY                                                        0xc3f
++#define mmHDP_XDP_CHKN                                                          0xc40
++#define mmHDP_XDP_DBG_ADDR                                                      0xc41
++#define mmHDP_XDP_DBG_DATA                                                      0xc42
++#define mmHDP_XDP_DBG_MASK                                                      0xc43
++#define mmHDP_XDP_BARS_ADDR_39_36                                               0xc44
++
++#endif /* OSS_3_0_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
+new file mode 100644
+index 0000000..627cff1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
+@@ -0,0 +1,1464 @@
++/*
++ * OSS_3_0_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_3_0_1_ENUM_H
++#define OSS_3_0_1_ENUM_H
++
++typedef enum IH_CLIENT_ID {
++	DC_IH_SRC_ID_START                               = 0x1,
++	DC_IH_SRC_ID_END                                 = 0x1f,
++	VGA_IH_SRC_ID_START                              = 0x20,
++	VGA_IH_SRC_ID_END                                = 0x27,
++	CAP_IH_SRC_ID_START                              = 0x28,
++	CAP_IH_SRC_ID_END                                = 0x2f,
++	VIP_IH_SRC_ID_START                              = 0x30,
++	VIP_IH_SRC_ID_END                                = 0x3f,
++	ROM_IH_SRC_ID_START                              = 0x40,
++	ROM_IH_SRC_ID_END                                = 0x5d,
++	BIF_IH_SRC_ID_START                              = 0x5e,
++	SAM_IH_SRC_ID_START                              = 0x5f,
++	SRBM_IH_SRC_ID_START                             = 0x60,
++	SRBM_IH_SRC_ID_END                               = 0x67,
++	UVD_IH_SRC_ID_START                              = 0x72,
++	UVD_IH_SRC_ID_END                                = 0x85,
++	VMC_IH_SRC_ID_START                              = 0x86,
++	VMC_IH_SRC_ID_END                                = 0x8f,
++	RLC_IH_SRC_ID_START                              = 0x90,
++	RLC_IH_SRC_ID_END                                = 0xf3,
++	PDMA_IH_SRC_ID_START                             = 0xf4,
++	PDMA_IH_SRC_ID_END                               = 0xf7,
++	CG_IH_SRC_ID_START                               = 0xf8,
++	CG_IH_SRC_ID_END                                 = 0xff,
++} IH_CLIENT_ID;
++typedef enum IH_PERF_SEL {
++	IH_PERF_SEL_CYCLE                                = 0x0,
++	IH_PERF_SEL_IDLE                                 = 0x1,
++	IH_PERF_SEL_INPUT_IDLE                           = 0x2,
++	IH_PERF_SEL_CLIENT0_IH_STALL                     = 0x3,
++	IH_PERF_SEL_CLIENT1_IH_STALL                     = 0x4,
++	IH_PERF_SEL_CLIENT2_IH_STALL                     = 0x5,
++	IH_PERF_SEL_CLIENT3_IH_STALL                     = 0x6,
++	IH_PERF_SEL_CLIENT4_IH_STALL                     = 0x7,
++	IH_PERF_SEL_CLIENT5_IH_STALL                     = 0x8,
++	IH_PERF_SEL_CLIENT6_IH_STALL                     = 0x9,
++	IH_PERF_SEL_CLIENT7_IH_STALL                     = 0xa,
++	IH_PERF_SEL_RB_IDLE                              = 0xb,
++	IH_PERF_SEL_RB_FULL                              = 0xc,
++	IH_PERF_SEL_RB_OVERFLOW                          = 0xd,
++	IH_PERF_SEL_RB_WPTR_WRITEBACK                    = 0xe,
++	IH_PERF_SEL_RB_WPTR_WRAP                         = 0xf,
++	IH_PERF_SEL_RB_RPTR_WRAP                         = 0x10,
++	IH_PERF_SEL_MC_WR_IDLE                           = 0x11,
++	IH_PERF_SEL_MC_WR_COUNT                          = 0x12,
++	IH_PERF_SEL_MC_WR_STALL                          = 0x13,
++	IH_PERF_SEL_MC_WR_CLEAN_PENDING                  = 0x14,
++	IH_PERF_SEL_MC_WR_CLEAN_STALL                    = 0x15,
++	IH_PERF_SEL_BIF_RISING                           = 0x16,
++	IH_PERF_SEL_BIF_FALLING                          = 0x17,
++	IH_PERF_SEL_CLIENT8_IH_STALL                     = 0x18,
++	IH_PERF_SEL_CLIENT9_IH_STALL                     = 0x19,
++	IH_PERF_SEL_CLIENT10_IH_STALL                    = 0x1a,
++	IH_PERF_SEL_CLIENT11_IH_STALL                    = 0x1b,
++	IH_PERF_SEL_CLIENT12_IH_STALL                    = 0x1c,
++	IH_PERF_SEL_CLIENT13_IH_STALL                    = 0x1d,
++	IH_PERF_SEL_CLIENT14_IH_STALL                    = 0x1e,
++	IH_PERF_SEL_CLIENT15_IH_STALL                    = 0x1f,
++	IH_PERF_SEL_CLIENT16_IH_STALL                    = 0x20,
++	IH_PERF_SEL_CLIENT17_IH_STALL                    = 0x21,
++	IH_PERF_SEL_CLIENT18_IH_STALL                    = 0x22,
++	IH_PERF_SEL_CLIENT19_IH_STALL                    = 0x23,
++	IH_PERF_SEL_CLIENT20_IH_STALL                    = 0x24,
++	IH_PERF_SEL_CLIENT21_IH_STALL                    = 0x25,
++	IH_PERF_SEL_CLIENT22_IH_STALL                    = 0x26,
++	IH_PERF_SEL_CLIENT23_IH_STALL                    = 0x27,
++} IH_PERF_SEL;
++typedef enum SEM_PERF_SEL {
++	SEM_PERF_SEL_CYCLE                               = 0x0,
++	SEM_PERF_SEL_IDLE                                = 0x1,
++	SEM_PERF_SEL_SDMA0_REQ_SIGNAL                    = 0x2,
++	SEM_PERF_SEL_SDMA1_REQ_SIGNAL                    = 0x3,
++	SEM_PERF_SEL_UVD_REQ_SIGNAL                      = 0x4,
++	SEM_PERF_SEL_VCE0_REQ_SIGNAL                     = 0x5,
++	SEM_PERF_SEL_ACP_REQ_SIGNAL                      = 0x6,
++	SEM_PERF_SEL_ISP_REQ_SIGNAL                      = 0x7,
++	SEM_PERF_SEL_VCE1_REQ_SIGNAL                     = 0x8,
++	SEM_PERF_SEL_VP8_REQ_SIGNAL                      = 0x9,
++	SEM_PERF_SEL_CPG_E0_REQ_SIGNAL                   = 0xa,
++	SEM_PERF_SEL_CPG_E1_REQ_SIGNAL                   = 0xb,
++	SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL             = 0xc,
++	SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL             = 0xd,
++	SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL             = 0xe,
++	SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL             = 0xf,
++	SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL             = 0x10,
++	SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL             = 0x11,
++	SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL             = 0x12,
++	SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL             = 0x13,
++	SEM_PERF_SEL_SDMA0_REQ_WAIT                      = 0x14,
++	SEM_PERF_SEL_SDMA1_REQ_WAIT                      = 0x15,
++	SEM_PERF_SEL_UVD_REQ_WAIT                        = 0x16,
++	SEM_PERF_SEL_VCE0_REQ_WAIT                       = 0x17,
++	SEM_PERF_SEL_ACP_REQ_WAIT                        = 0x18,
++	SEM_PERF_SEL_ISP_REQ_WAIT                        = 0x19,
++	SEM_PERF_SEL_VCE1_REQ_WAIT                       = 0x1a,
++	SEM_PERF_SEL_VP8_REQ_WAIT                        = 0x1b,
++	SEM_PERF_SEL_CPG_E0_REQ_WAIT                     = 0x1c,
++	SEM_PERF_SEL_CPG_E1_REQ_WAIT                     = 0x1d,
++	SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT               = 0x1e,
++	SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT               = 0x1f,
++	SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT               = 0x20,
++	SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT               = 0x21,
++	SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT               = 0x22,
++	SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT               = 0x23,
++	SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT               = 0x24,
++	SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT               = 0x25,
++	SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT               = 0x26,
++	SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT               = 0x27,
++	SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT               = 0x28,
++	SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT               = 0x29,
++	SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT               = 0x2a,
++	SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT               = 0x2b,
++	SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT               = 0x2c,
++	SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT               = 0x2d,
++	SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT               = 0x2e,
++	SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT               = 0x2f,
++	SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT              = 0x30,
++	SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT              = 0x31,
++	SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT              = 0x32,
++	SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT              = 0x33,
++	SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT              = 0x34,
++	SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT              = 0x35,
++	SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT              = 0x36,
++	SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT              = 0x37,
++	SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT              = 0x38,
++	SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT              = 0x39,
++	SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT              = 0x3a,
++	SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT              = 0x3b,
++	SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT              = 0x3c,
++	SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT              = 0x3d,
++	SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT              = 0x3e,
++	SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT              = 0x3f,
++	SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT              = 0x40,
++	SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT              = 0x41,
++	SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT              = 0x42,
++	SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT              = 0x43,
++	SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT              = 0x44,
++	SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT              = 0x45,
++	SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT               = 0x46,
++	SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT               = 0x47,
++	SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT               = 0x48,
++	SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT               = 0x49,
++	SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT               = 0x4a,
++	SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT               = 0x4b,
++	SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT               = 0x4c,
++	SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT               = 0x4d,
++	SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT               = 0x4e,
++	SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT               = 0x4f,
++	SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT              = 0x50,
++	SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT              = 0x51,
++	SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT              = 0x52,
++	SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT              = 0x53,
++	SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT              = 0x54,
++	SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT              = 0x55,
++	SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT              = 0x56,
++	SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT              = 0x57,
++	SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT              = 0x58,
++	SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT              = 0x59,
++	SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT              = 0x5a,
++	SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT              = 0x5b,
++	SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT              = 0x5c,
++	SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT              = 0x5d,
++	SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT              = 0x5e,
++	SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT              = 0x5f,
++	SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT              = 0x60,
++	SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT              = 0x61,
++	SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT              = 0x62,
++	SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT              = 0x63,
++	SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT              = 0x64,
++	SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT              = 0x65,
++	SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT              = 0x66,
++	SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT              = 0x67,
++	SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT              = 0x68,
++	SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT              = 0x69,
++	SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT              = 0x6a,
++	SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT              = 0x6b,
++	SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT              = 0x6c,
++	SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT              = 0x6d,
++	SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT              = 0x6e,
++	SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT              = 0x6f,
++	SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT             = 0x70,
++	SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT             = 0x71,
++	SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT             = 0x72,
++	SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT             = 0x73,
++	SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT             = 0x74,
++	SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT             = 0x75,
++	SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT             = 0x76,
++	SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT             = 0x77,
++	SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT             = 0x78,
++	SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT             = 0x79,
++	SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT             = 0x7a,
++	SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT             = 0x7b,
++	SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT             = 0x7c,
++	SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT             = 0x7d,
++	SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT             = 0x7e,
++	SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT             = 0x7f,
++	SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT             = 0x80,
++	SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT             = 0x81,
++	SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT             = 0x82,
++	SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT             = 0x83,
++	SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT             = 0x84,
++	SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT             = 0x85,
++	SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT              = 0x86,
++	SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT              = 0x87,
++	SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT              = 0x88,
++	SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT              = 0x89,
++	SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT              = 0x8a,
++	SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT              = 0x8b,
++	SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT              = 0x8c,
++	SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT              = 0x8d,
++	SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT              = 0x8e,
++	SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT              = 0x8f,
++	SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT             = 0x90,
++	SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT             = 0x91,
++	SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT             = 0x92,
++	SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT             = 0x93,
++	SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT             = 0x94,
++	SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT             = 0x95,
++	SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT             = 0x96,
++	SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT             = 0x97,
++	SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT             = 0x98,
++	SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT             = 0x99,
++	SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT             = 0x9a,
++	SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT             = 0x9b,
++	SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT             = 0x9c,
++	SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT             = 0x9d,
++	SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT             = 0x9e,
++	SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT             = 0x9f,
++	SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT             = 0xa0,
++	SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT             = 0xa1,
++	SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT             = 0xa2,
++	SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT             = 0xa3,
++	SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT             = 0xa4,
++	SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT             = 0xa5,
++	SEM_PERF_SEL_MC_RD_REQ                           = 0xa6,
++	SEM_PERF_SEL_MC_RD_RET                           = 0xa7,
++	SEM_PERF_SEL_MC_WR_REQ                           = 0xa8,
++	SEM_PERF_SEL_MC_WR_RET                           = 0xa9,
++	SEM_PERF_SEL_ATC_REQ                             = 0xaa,
++	SEM_PERF_SEL_ATC_RET                             = 0xab,
++	SEM_PERF_SEL_ATC_XNACK                           = 0xac,
++	SEM_PERF_SEL_ATC_INVALIDATION                    = 0xad,
++} SEM_PERF_SEL;
++typedef enum SRBM_PERFCOUNT1_SEL {
++	SRBM_PERF_SEL_COUNT                              = 0x0,
++	SRBM_PERF_SEL_BIF_BUSY                           = 0x1,
++	SRBM_PERF_SEL_SDMA0_BUSY                         = 0x3,
++	SRBM_PERF_SEL_IH_BUSY                            = 0x4,
++	SRBM_PERF_SEL_MCB_BUSY                           = 0x5,
++	SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY               = 0x6,
++	SRBM_PERF_SEL_MCC_BUSY                           = 0x7,
++	SRBM_PERF_SEL_MCD_BUSY                           = 0x8,
++	SRBM_PERF_SEL_CHUB_BUSY                          = 0x9,
++	SRBM_PERF_SEL_SEM_BUSY                           = 0xa,
++	SRBM_PERF_SEL_UVD_BUSY                           = 0xb,
++	SRBM_PERF_SEL_VMC_BUSY                           = 0xc,
++	SRBM_PERF_SEL_ODE_BUSY                           = 0xd,
++	SRBM_PERF_SEL_SDMA1_BUSY                         = 0xe,
++	SRBM_PERF_SEL_SAMMSP_BUSY                        = 0xf,
++	SRBM_PERF_SEL_VCE0_BUSY                          = 0x10,
++	SRBM_PERF_SEL_XDMA_BUSY                          = 0x11,
++	SRBM_PERF_SEL_ACP_BUSY                           = 0x12,
++	SRBM_PERF_SEL_SDMA2_BUSY                         = 0x13,
++	SRBM_PERF_SEL_SDMA3_BUSY                         = 0x14,
++	RESERVED0                                        = 0x15,
++	SRBM_PERF_SEL_VMC1_BUSY                          = 0x16,
++	SRBM_PERF_SEL_ISP_BUSY                           = 0x17,
++	SRBM_PERF_SEL_VCE1_BUSY                          = 0x18,
++	SRBM_PERF_SEL_GCATCL2_BUSY                       = 0x19,
++	SRBM_PERF_SEL_OSATCL2_BUSY                       = 0x1a,
++	SRBM_PERF_SEL_VP8_BUSY                           = 0x1b,
++} SRBM_PERFCOUNT1_SEL;
++typedef enum SYS_GRBM_GFX_INDEX_SEL {
++	GRBM_GFX_INDEX_BIF                               = 0x0,
++	GRBM_GFX_INDEX_SDMA0                             = 0x1,
++	GRBM_GFX_INDEX_SDMA1                             = 0x2,
++	RESEVERED0                                       = 0x3,
++	GRBM_GFX_INDEX_UVD                               = 0x4,
++	GRBM_GFX_INDEX_VCE0                              = 0x5,
++	GRBM_GFX_INDEX_VCE1                              = 0x6,
++	GRBM_GFX_INDEX_ACP                               = 0x7,
++	GRBM_GFX_INDEX_SMU                               = 0x8,
++	GRBM_GFX_INDEX_SAMMSP                            = 0x9,
++	GRBM_GFX_INDEX_VP8                               = 0xa,
++	GRBM_GFX_INDEX_ISP                               = 0xb,
++	GRBM_GFX_INDEX_TST                               = 0xc,
++	GRBM_GFX_INDEX_SDMA2                             = 0xd,
++	GRBM_GFX_INDEX_SDMA3                             = 0xe,
++} SYS_GRBM_GFX_INDEX_SEL;
++typedef enum SRBM_GFX_CNTL_SEL {
++	SRBM_GFX_CNTL_BIF                                = 0x0,
++	SRBM_GFX_CNTL_SDMA0                              = 0x1,
++	SRBM_GFX_CNTL_SDMA1                              = 0x2,
++	SRBM_GFX_CNTL_GRBM                               = 0x3,
++	SRBM_GFX_CNTL_UVD                                = 0x4,
++	SRBM_GFX_CNTL_VCE0                               = 0x5,
++	SRBM_GFX_CNTL_VCE1                               = 0x6,
++	SRBM_GFX_CNTL_ACP                                = 0x7,
++	SRBM_GFX_CNTL_SMU                                = 0x8,
++	SRBM_GFX_CNTL_SAMMSP                             = 0x9,
++	SRBM_GFX_CNTL_VP8                                = 0xa,
++	SRBM_GFX_CNTL_ISP                                = 0xb,
++	SRBM_GFX_CNTL_TST                                = 0xc,
++	SRBM_GFX_CNTL_SDMA2                              = 0xd,
++	SRBM_GFX_CNTL_SDMA3                              = 0xe,
++} SRBM_GFX_CNTL_SEL;
++typedef enum SDMA_PERF_SEL {
++	SDMA_PERF_SEL_CYCLE                              = 0x0,
++	SDMA_PERF_SEL_IDLE                               = 0x1,
++	SDMA_PERF_SEL_REG_IDLE                           = 0x2,
++	SDMA_PERF_SEL_RB_EMPTY                           = 0x3,
++	SDMA_PERF_SEL_RB_FULL                            = 0x4,
++	SDMA_PERF_SEL_RB_WPTR_WRAP                       = 0x5,
++	SDMA_PERF_SEL_RB_RPTR_WRAP                       = 0x6,
++	SDMA_PERF_SEL_RB_WPTR_POLL_READ                  = 0x7,
++	SDMA_PERF_SEL_RB_RPTR_WB                         = 0x8,
++	SDMA_PERF_SEL_RB_CMD_IDLE                        = 0x9,
++	SDMA_PERF_SEL_RB_CMD_FULL                        = 0xa,
++	SDMA_PERF_SEL_IB_CMD_IDLE                        = 0xb,
++	SDMA_PERF_SEL_IB_CMD_FULL                        = 0xc,
++	SDMA_PERF_SEL_EX_IDLE                            = 0xd,
++	SDMA_PERF_SEL_SRBM_REG_SEND                      = 0xe,
++	SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE          = 0xf,
++	SDMA_PERF_SEL_MC_WR_IDLE                         = 0x10,
++	SDMA_PERF_SEL_MC_WR_COUNT                        = 0x11,
++	SDMA_PERF_SEL_MC_RD_IDLE                         = 0x12,
++	SDMA_PERF_SEL_MC_RD_COUNT                        = 0x13,
++	SDMA_PERF_SEL_MC_RD_RET_STALL                    = 0x14,
++	SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE                 = 0x15,
++	SDMA_PERF_SEL_SEM_IDLE                           = 0x18,
++	SDMA_PERF_SEL_SEM_REQ_STALL                      = 0x19,
++	SDMA_PERF_SEL_SEM_REQ_COUNT                      = 0x1a,
++	SDMA_PERF_SEL_SEM_RESP_INCOMPLETE                = 0x1b,
++	SDMA_PERF_SEL_SEM_RESP_FAIL                      = 0x1c,
++	SDMA_PERF_SEL_SEM_RESP_PASS                      = 0x1d,
++	SDMA_PERF_SEL_INT_IDLE                           = 0x1e,
++	SDMA_PERF_SEL_INT_REQ_STALL                      = 0x1f,
++	SDMA_PERF_SEL_INT_REQ_COUNT                      = 0x20,
++	SDMA_PERF_SEL_INT_RESP_ACCEPTED                  = 0x21,
++	SDMA_PERF_SEL_INT_RESP_RETRY                     = 0x22,
++	SDMA_PERF_SEL_NUM_PACKET                         = 0x23,
++	SDMA_PERF_SEL_CE_WREQ_IDLE                       = 0x25,
++	SDMA_PERF_SEL_CE_WR_IDLE                         = 0x26,
++	SDMA_PERF_SEL_CE_SPLIT_IDLE                      = 0x27,
++	SDMA_PERF_SEL_CE_RREQ_IDLE                       = 0x28,
++	SDMA_PERF_SEL_CE_OUT_IDLE                        = 0x29,
++	SDMA_PERF_SEL_CE_IN_IDLE                         = 0x2a,
++	SDMA_PERF_SEL_CE_DST_IDLE                        = 0x2b,
++	SDMA_PERF_SEL_CE_AFIFO_FULL                      = 0x2e,
++	SDMA_PERF_SEL_CE_INFO_FULL                       = 0x31,
++	SDMA_PERF_SEL_CE_INFO1_FULL                      = 0x32,
++	SDMA_PERF_SEL_CE_RD_STALL                        = 0x33,
++	SDMA_PERF_SEL_CE_WR_STALL                        = 0x34,
++	SDMA_PERF_SEL_GFX_SELECT                         = 0x35,
++	SDMA_PERF_SEL_RLC0_SELECT                        = 0x36,
++	SDMA_PERF_SEL_RLC1_SELECT                        = 0x37,
++	SDMA_PERF_SEL_CTX_CHANGE                         = 0x38,
++	SDMA_PERF_SEL_CTX_CHANGE_EXPIRED                 = 0x39,
++	SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION               = 0x3a,
++	SDMA_PERF_SEL_DOORBELL                           = 0x3b,
++	SDMA_PERF_SEL_RD_BA_RTR                          = 0x3c,
++	SDMA_PERF_SEL_WR_BA_RTR                          = 0x3d,
++	SDMA_PERF_SEL_F32_L1_WR_VLD                      = 0x3e,
++	SDMA_PERF_SEL_CE_L1_WR_VLD                       = 0x3f,
++	SDMA_PERF_SEL_CE_L1_STALL                        = 0x40,
++	SDMA_PERF_SEL_SDMA_INVACK_NFLUSH                 = 0x41,
++	SDMA_PERF_SEL_SDMA_INVACK_FLUSH                  = 0x42,
++	SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH                = 0x43,
++	SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH                 = 0x44,
++	SDMA_PERF_SEL_ATCL2_RET_XNACK                    = 0x45,
++	SDMA_PERF_SEL_ATCL2_RET_ACK                      = 0x46,
++	SDMA_PERF_SEL_ATCL2_FREE                         = 0x47,
++	SDMA_PERF_SEL_SDMA_ATCL2_SEND                    = 0x48,
++	SDMA_PERF_SEL_DMA_L1_WR_SEND                     = 0x49,
++	SDMA_PERF_SEL_DMA_L1_RD_SEND                     = 0x4a,
++	SDMA_PERF_SEL_DMA_MC_WR_SEND                     = 0x4b,
++	SDMA_PERF_SEL_DMA_MC_RD_SEND                     = 0x4c,
++	SDMA_PERF_SEL_L1_WR_FIFO_IDLE                    = 0x4d,
++	SDMA_PERF_SEL_L1_RD_FIFO_IDLE                    = 0x4e,
++	SDMA_PERF_SEL_L1_WRL2_IDLE                       = 0x4f,
++	SDMA_PERF_SEL_L1_RDL2_IDLE                       = 0x50,
++	SDMA_PERF_SEL_L1_WRMC_IDLE                       = 0x51,
++	SDMA_PERF_SEL_L1_RDMC_IDLE                       = 0x52,
++	SDMA_PERF_SEL_L1_WR_INV_IDLE                     = 0x53,
++	SDMA_PERF_SEL_L1_RD_INV_IDLE                     = 0x54,
++	SDMA_PERF_SEL_L1_WR_INV_EN                       = 0x55,
++	SDMA_PERF_SEL_L1_RD_INV_EN                       = 0x56,
++	SDMA_PERF_SEL_L1_WR_WAIT_INVADR                  = 0x57,
++	SDMA_PERF_SEL_L1_RD_WAIT_INVADR                  = 0x58,
++	SDMA_PERF_SEL_IS_INVREQ_ADDR_WR                  = 0x59,
++	SDMA_PERF_SEL_IS_INVREQ_ADDR_RD                  = 0x5a,
++	SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT                = 0x5b,
++	SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT                = 0x5c,
++	SDMA_PERF_SEL_L1_INV_MIDDLE                      = 0x5d,
++} SDMA_PERF_SEL;
++typedef enum DebugBlockId {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_UVDU                                = 0xd,
++	DBG_BLOCK_ID_SQA                                 = 0xe,
++	DBG_BLOCK_ID_SDMA0                               = 0xf,
++	DBG_BLOCK_ID_SDMA1                               = 0x10,
++	DBG_BLOCK_ID_SPIM                                = 0x11,
++	DBG_BLOCK_ID_GDS                                 = 0x12,
++	DBG_BLOCK_ID_VC0                                 = 0x13,
++	DBG_BLOCK_ID_VC1                                 = 0x14,
++	DBG_BLOCK_ID_PA0                                 = 0x15,
++	DBG_BLOCK_ID_PA1                                 = 0x16,
++	DBG_BLOCK_ID_CP0                                 = 0x17,
++	DBG_BLOCK_ID_CP1                                 = 0x18,
++	DBG_BLOCK_ID_CP2                                 = 0x19,
++	DBG_BLOCK_ID_XBR                                 = 0x1a,
++	DBG_BLOCK_ID_UVDM                                = 0x1b,
++	DBG_BLOCK_ID_VGT0                                = 0x1c,
++	DBG_BLOCK_ID_VGT1                                = 0x1d,
++	DBG_BLOCK_ID_IA                                  = 0x1e,
++	DBG_BLOCK_ID_SXM0                                = 0x1f,
++	DBG_BLOCK_ID_SXM1                                = 0x20,
++	DBG_BLOCK_ID_SCT0                                = 0x21,
++	DBG_BLOCK_ID_SCT1                                = 0x22,
++	DBG_BLOCK_ID_SPM0                                = 0x23,
++	DBG_BLOCK_ID_SPM1                                = 0x24,
++	DBG_BLOCK_ID_UNUSED0                             = 0x25,
++	DBG_BLOCK_ID_UNUSED1                             = 0x26,
++	DBG_BLOCK_ID_TCAA                                = 0x27,
++	DBG_BLOCK_ID_TCAB                                = 0x28,
++	DBG_BLOCK_ID_TCCA                                = 0x29,
++	DBG_BLOCK_ID_TCCB                                = 0x2a,
++	DBG_BLOCK_ID_MCC0                                = 0x2b,
++	DBG_BLOCK_ID_MCC1                                = 0x2c,
++	DBG_BLOCK_ID_MCC2                                = 0x2d,
++	DBG_BLOCK_ID_MCC3                                = 0x2e,
++	DBG_BLOCK_ID_SXS0                                = 0x2f,
++	DBG_BLOCK_ID_SXS1                                = 0x30,
++	DBG_BLOCK_ID_SXS2                                = 0x31,
++	DBG_BLOCK_ID_SXS3                                = 0x32,
++	DBG_BLOCK_ID_SXS4                                = 0x33,
++	DBG_BLOCK_ID_SXS5                                = 0x34,
++	DBG_BLOCK_ID_SXS6                                = 0x35,
++	DBG_BLOCK_ID_SXS7                                = 0x36,
++	DBG_BLOCK_ID_SXS8                                = 0x37,
++	DBG_BLOCK_ID_SXS9                                = 0x38,
++	DBG_BLOCK_ID_BCI0                                = 0x39,
++	DBG_BLOCK_ID_BCI1                                = 0x3a,
++	DBG_BLOCK_ID_BCI2                                = 0x3b,
++	DBG_BLOCK_ID_BCI3                                = 0x3c,
++	DBG_BLOCK_ID_MCB                                 = 0x3d,
++	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
++	DBG_BLOCK_ID_SQA00                               = 0x3f,
++	DBG_BLOCK_ID_SQA01                               = 0x40,
++	DBG_BLOCK_ID_SQA02                               = 0x41,
++	DBG_BLOCK_ID_SQA10                               = 0x42,
++	DBG_BLOCK_ID_SQA11                               = 0x43,
++	DBG_BLOCK_ID_SQA12                               = 0x44,
++	DBG_BLOCK_ID_UNUSED7                             = 0x45,
++	DBG_BLOCK_ID_UNUSED8                             = 0x46,
++	DBG_BLOCK_ID_SQB00                               = 0x47,
++	DBG_BLOCK_ID_SQB01                               = 0x48,
++	DBG_BLOCK_ID_SQB10                               = 0x49,
++	DBG_BLOCK_ID_SQB11                               = 0x4a,
++	DBG_BLOCK_ID_SQ00                                = 0x4b,
++	DBG_BLOCK_ID_SQ01                                = 0x4c,
++	DBG_BLOCK_ID_SQ10                                = 0x4d,
++	DBG_BLOCK_ID_SQ11                                = 0x4e,
++	DBG_BLOCK_ID_CB00                                = 0x4f,
++	DBG_BLOCK_ID_CB01                                = 0x50,
++	DBG_BLOCK_ID_CB02                                = 0x51,
++	DBG_BLOCK_ID_CB03                                = 0x52,
++	DBG_BLOCK_ID_CB04                                = 0x53,
++	DBG_BLOCK_ID_UNUSED9                             = 0x54,
++	DBG_BLOCK_ID_UNUSED10                            = 0x55,
++	DBG_BLOCK_ID_UNUSED11                            = 0x56,
++	DBG_BLOCK_ID_CB10                                = 0x57,
++	DBG_BLOCK_ID_CB11                                = 0x58,
++	DBG_BLOCK_ID_CB12                                = 0x59,
++	DBG_BLOCK_ID_CB13                                = 0x5a,
++	DBG_BLOCK_ID_CB14                                = 0x5b,
++	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
++	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
++	DBG_BLOCK_ID_TCP0                                = 0x5f,
++	DBG_BLOCK_ID_TCP1                                = 0x60,
++	DBG_BLOCK_ID_TCP2                                = 0x61,
++	DBG_BLOCK_ID_TCP3                                = 0x62,
++	DBG_BLOCK_ID_TCP4                                = 0x63,
++	DBG_BLOCK_ID_TCP5                                = 0x64,
++	DBG_BLOCK_ID_TCP6                                = 0x65,
++	DBG_BLOCK_ID_TCP7                                = 0x66,
++	DBG_BLOCK_ID_TCP8                                = 0x67,
++	DBG_BLOCK_ID_TCP9                                = 0x68,
++	DBG_BLOCK_ID_TCP10                               = 0x69,
++	DBG_BLOCK_ID_TCP11                               = 0x6a,
++	DBG_BLOCK_ID_TCP12                               = 0x6b,
++	DBG_BLOCK_ID_TCP13                               = 0x6c,
++	DBG_BLOCK_ID_TCP14                               = 0x6d,
++	DBG_BLOCK_ID_TCP15                               = 0x6e,
++	DBG_BLOCK_ID_TCP16                               = 0x6f,
++	DBG_BLOCK_ID_TCP17                               = 0x70,
++	DBG_BLOCK_ID_TCP18                               = 0x71,
++	DBG_BLOCK_ID_TCP19                               = 0x72,
++	DBG_BLOCK_ID_TCP20                               = 0x73,
++	DBG_BLOCK_ID_TCP21                               = 0x74,
++	DBG_BLOCK_ID_TCP22                               = 0x75,
++	DBG_BLOCK_ID_TCP23                               = 0x76,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
++	DBG_BLOCK_ID_DB00                                = 0x7f,
++	DBG_BLOCK_ID_DB01                                = 0x80,
++	DBG_BLOCK_ID_DB02                                = 0x81,
++	DBG_BLOCK_ID_DB03                                = 0x82,
++	DBG_BLOCK_ID_DB04                                = 0x83,
++	DBG_BLOCK_ID_UNUSED15                            = 0x84,
++	DBG_BLOCK_ID_UNUSED16                            = 0x85,
++	DBG_BLOCK_ID_UNUSED17                            = 0x86,
++	DBG_BLOCK_ID_DB10                                = 0x87,
++	DBG_BLOCK_ID_DB11                                = 0x88,
++	DBG_BLOCK_ID_DB12                                = 0x89,
++	DBG_BLOCK_ID_DB13                                = 0x8a,
++	DBG_BLOCK_ID_DB14                                = 0x8b,
++	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
++	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
++	DBG_BLOCK_ID_TCC0                                = 0x8f,
++	DBG_BLOCK_ID_TCC1                                = 0x90,
++	DBG_BLOCK_ID_TCC2                                = 0x91,
++	DBG_BLOCK_ID_TCC3                                = 0x92,
++	DBG_BLOCK_ID_TCC4                                = 0x93,
++	DBG_BLOCK_ID_TCC5                                = 0x94,
++	DBG_BLOCK_ID_TCC6                                = 0x95,
++	DBG_BLOCK_ID_TCC7                                = 0x96,
++	DBG_BLOCK_ID_SPS00                               = 0x97,
++	DBG_BLOCK_ID_SPS01                               = 0x98,
++	DBG_BLOCK_ID_SPS02                               = 0x99,
++	DBG_BLOCK_ID_SPS10                               = 0x9a,
++	DBG_BLOCK_ID_SPS11                               = 0x9b,
++	DBG_BLOCK_ID_SPS12                               = 0x9c,
++	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
++	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
++	DBG_BLOCK_ID_TA00                                = 0x9f,
++	DBG_BLOCK_ID_TA01                                = 0xa0,
++	DBG_BLOCK_ID_TA02                                = 0xa1,
++	DBG_BLOCK_ID_TA03                                = 0xa2,
++	DBG_BLOCK_ID_TA04                                = 0xa3,
++	DBG_BLOCK_ID_TA05                                = 0xa4,
++	DBG_BLOCK_ID_TA06                                = 0xa5,
++	DBG_BLOCK_ID_TA07                                = 0xa6,
++	DBG_BLOCK_ID_TA08                                = 0xa7,
++	DBG_BLOCK_ID_TA09                                = 0xa8,
++	DBG_BLOCK_ID_TA0A                                = 0xa9,
++	DBG_BLOCK_ID_TA0B                                = 0xaa,
++	DBG_BLOCK_ID_UNUSED23                            = 0xab,
++	DBG_BLOCK_ID_UNUSED24                            = 0xac,
++	DBG_BLOCK_ID_UNUSED25                            = 0xad,
++	DBG_BLOCK_ID_UNUSED26                            = 0xae,
++	DBG_BLOCK_ID_TA10                                = 0xaf,
++	DBG_BLOCK_ID_TA11                                = 0xb0,
++	DBG_BLOCK_ID_TA12                                = 0xb1,
++	DBG_BLOCK_ID_TA13                                = 0xb2,
++	DBG_BLOCK_ID_TA14                                = 0xb3,
++	DBG_BLOCK_ID_TA15                                = 0xb4,
++	DBG_BLOCK_ID_TA16                                = 0xb5,
++	DBG_BLOCK_ID_TA17                                = 0xb6,
++	DBG_BLOCK_ID_TA18                                = 0xb7,
++	DBG_BLOCK_ID_TA19                                = 0xb8,
++	DBG_BLOCK_ID_TA1A                                = 0xb9,
++	DBG_BLOCK_ID_TA1B                                = 0xba,
++	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
++	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
++	DBG_BLOCK_ID_TD00                                = 0xbf,
++	DBG_BLOCK_ID_TD01                                = 0xc0,
++	DBG_BLOCK_ID_TD02                                = 0xc1,
++	DBG_BLOCK_ID_TD03                                = 0xc2,
++	DBG_BLOCK_ID_TD04                                = 0xc3,
++	DBG_BLOCK_ID_TD05                                = 0xc4,
++	DBG_BLOCK_ID_TD06                                = 0xc5,
++	DBG_BLOCK_ID_TD07                                = 0xc6,
++	DBG_BLOCK_ID_TD08                                = 0xc7,
++	DBG_BLOCK_ID_TD09                                = 0xc8,
++	DBG_BLOCK_ID_TD0A                                = 0xc9,
++	DBG_BLOCK_ID_TD0B                                = 0xca,
++	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
++	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED34                            = 0xce,
++	DBG_BLOCK_ID_TD10                                = 0xcf,
++	DBG_BLOCK_ID_TD11                                = 0xd0,
++	DBG_BLOCK_ID_TD12                                = 0xd1,
++	DBG_BLOCK_ID_TD13                                = 0xd2,
++	DBG_BLOCK_ID_TD14                                = 0xd3,
++	DBG_BLOCK_ID_TD15                                = 0xd4,
++	DBG_BLOCK_ID_TD16                                = 0xd5,
++	DBG_BLOCK_ID_TD17                                = 0xd6,
++	DBG_BLOCK_ID_TD18                                = 0xd7,
++	DBG_BLOCK_ID_TD19                                = 0xd8,
++	DBG_BLOCK_ID_TD1A                                = 0xd9,
++	DBG_BLOCK_ID_TD1B                                = 0xda,
++	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
++	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED38                            = 0xde,
++	DBG_BLOCK_ID_LDS00                               = 0xdf,
++	DBG_BLOCK_ID_LDS01                               = 0xe0,
++	DBG_BLOCK_ID_LDS02                               = 0xe1,
++	DBG_BLOCK_ID_LDS03                               = 0xe2,
++	DBG_BLOCK_ID_LDS04                               = 0xe3,
++	DBG_BLOCK_ID_LDS05                               = 0xe4,
++	DBG_BLOCK_ID_LDS06                               = 0xe5,
++	DBG_BLOCK_ID_LDS07                               = 0xe6,
++	DBG_BLOCK_ID_LDS08                               = 0xe7,
++	DBG_BLOCK_ID_LDS09                               = 0xe8,
++	DBG_BLOCK_ID_LDS0A                               = 0xe9,
++	DBG_BLOCK_ID_LDS0B                               = 0xea,
++	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
++	DBG_BLOCK_ID_UNUSED40                            = 0xec,
++	DBG_BLOCK_ID_UNUSED41                            = 0xed,
++	DBG_BLOCK_ID_UNUSED42                            = 0xee,
++	DBG_BLOCK_ID_LDS10                               = 0xef,
++	DBG_BLOCK_ID_LDS11                               = 0xf0,
++	DBG_BLOCK_ID_LDS12                               = 0xf1,
++	DBG_BLOCK_ID_LDS13                               = 0xf2,
++	DBG_BLOCK_ID_LDS14                               = 0xf3,
++	DBG_BLOCK_ID_LDS15                               = 0xf4,
++	DBG_BLOCK_ID_LDS16                               = 0xf5,
++	DBG_BLOCK_ID_LDS17                               = 0xf6,
++	DBG_BLOCK_ID_LDS18                               = 0xf7,
++	DBG_BLOCK_ID_LDS19                               = 0xf8,
++	DBG_BLOCK_ID_LDS1A                               = 0xf9,
++	DBG_BLOCK_ID_LDS1B                               = 0xfa,
++	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
++	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
++	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
++	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
++} DebugBlockId;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
++	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
++	DBG_BLOCK_ID_PA_BY2                              = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
++	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
++	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
++	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
++	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
++	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
++	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
++	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
++	DBG_BLOCK_ID_CB_BY2                              = 0x24,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
++	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
++	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
++	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
++	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
++	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
++	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
++	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
++	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
++	DBG_BLOCK_ID_TA_BY2                              = 0x48,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
++	DBG_BLOCK_ID_TD_BY2                              = 0x58,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
++	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
++	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
++	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
++	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
++	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
++	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
++	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
++	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
++	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
++	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
++	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
++	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
++	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
++	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
++	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
++	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
++	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
++	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
++	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
++	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
++	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
++	DBG_BLOCK_ID_CB_BY4                              = 0x12,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
++	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
++	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
++	DBG_BLOCK_ID_DB_BY4                              = 0x16,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
++	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
++	DBG_BLOCK_ID_TA_BY4                              = 0x24,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
++	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
++	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
++	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
++	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
++	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
++	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
++	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
++	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
++	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
++	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
++	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
++	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
++	DBG_BLOCK_ID_CB_BY8                              = 0x9,
++	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
++	DBG_BLOCK_ID_DB_BY8                              = 0xb,
++	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
++	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
++	DBG_BLOCK_ID_TA_BY8                              = 0x12,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
++	DBG_BLOCK_ID_TD_BY8                              = 0x16,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
++	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
++	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
++	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
++	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
++	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
++	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
++	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
++	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
++	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
++	DBG_BLOCK_ID_TA_BY16                             = 0x9,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
++	DBG_BLOCK_ID_TD_BY16                             = 0xb,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
++	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
++	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
++} DebugBlockId_BY16;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* OSS_3_0_1_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h
+new file mode 100644
+index 0000000..cfacd85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h
+@@ -0,0 +1,3558 @@
++/*
++ * OSS_3_0_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef OSS_3_0_1_SH_MASK_H
++#define OSS_3_0_1_SH_MASK_H
++
++#define IH_VMID_0_LUT__PASID_MASK 0xffff
++#define IH_VMID_0_LUT__PASID__SHIFT 0x0
++#define IH_VMID_1_LUT__PASID_MASK 0xffff
++#define IH_VMID_1_LUT__PASID__SHIFT 0x0
++#define IH_VMID_2_LUT__PASID_MASK 0xffff
++#define IH_VMID_2_LUT__PASID__SHIFT 0x0
++#define IH_VMID_3_LUT__PASID_MASK 0xffff
++#define IH_VMID_3_LUT__PASID__SHIFT 0x0
++#define IH_VMID_4_LUT__PASID_MASK 0xffff
++#define IH_VMID_4_LUT__PASID__SHIFT 0x0
++#define IH_VMID_5_LUT__PASID_MASK 0xffff
++#define IH_VMID_5_LUT__PASID__SHIFT 0x0
++#define IH_VMID_6_LUT__PASID_MASK 0xffff
++#define IH_VMID_6_LUT__PASID__SHIFT 0x0
++#define IH_VMID_7_LUT__PASID_MASK 0xffff
++#define IH_VMID_7_LUT__PASID__SHIFT 0x0
++#define IH_VMID_8_LUT__PASID_MASK 0xffff
++#define IH_VMID_8_LUT__PASID__SHIFT 0x0
++#define IH_VMID_9_LUT__PASID_MASK 0xffff
++#define IH_VMID_9_LUT__PASID__SHIFT 0x0
++#define IH_VMID_10_LUT__PASID_MASK 0xffff
++#define IH_VMID_10_LUT__PASID__SHIFT 0x0
++#define IH_VMID_11_LUT__PASID_MASK 0xffff
++#define IH_VMID_11_LUT__PASID__SHIFT 0x0
++#define IH_VMID_12_LUT__PASID_MASK 0xffff
++#define IH_VMID_12_LUT__PASID__SHIFT 0x0
++#define IH_VMID_13_LUT__PASID_MASK 0xffff
++#define IH_VMID_13_LUT__PASID__SHIFT 0x0
++#define IH_VMID_14_LUT__PASID_MASK 0xffff
++#define IH_VMID_14_LUT__PASID__SHIFT 0x0
++#define IH_VMID_15_LUT__PASID_MASK 0xffff
++#define IH_VMID_15_LUT__PASID__SHIFT 0x0
++#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
++#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
++#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
++#define IH_RB_BASE__ADDR_MASK 0xffffffff
++#define IH_RB_BASE__ADDR__SHIFT 0x0
++#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_RPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
++#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
++#define IH_RB_WPTR__OFFSET__SHIFT 0x2
++#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
++#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
++#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
++#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define IH_CNTL__ENABLE_INTR_MASK 0x1
++#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
++#define IH_CNTL__MC_SWAP_MASK 0x6
++#define IH_CNTL__MC_SWAP__SHIFT 0x1
++#define IH_CNTL__RPTR_REARM_MASK 0x10
++#define IH_CNTL__RPTR_REARM__SHIFT 0x4
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
++#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
++#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
++#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
++#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
++#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
++#define IH_CNTL__MC_VMID_MASK 0x1e000000
++#define IH_CNTL__MC_VMID__SHIFT 0x19
++#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
++#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
++#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
++#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
++#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
++#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
++#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
++#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
++#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
++#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
++#define IH_STATUS__IDLE_MASK 0x1
++#define IH_STATUS__IDLE__SHIFT 0x0
++#define IH_STATUS__INPUT_IDLE_MASK 0x2
++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
++#define IH_STATUS__RB_IDLE_MASK 0x4
++#define IH_STATUS__RB_IDLE__SHIFT 0x2
++#define IH_STATUS__RB_FULL_MASK 0x8
++#define IH_STATUS__RB_FULL__SHIFT 0x3
++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
++#define IH_STATUS__RB_OVERFLOW_MASK 0x20
++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
++#define IH_STATUS__MC_WR_IDLE_MASK 0x40
++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
++#define IH_STATUS__MC_WR_STALL_MASK 0x80
++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
++#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
++#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
++#define IH_VERSION__VALUE_MASK 0xfff
++#define IH_VERSION__VALUE__SHIFT 0x0
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
++#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
++#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400
++#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
++#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800
++#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
++#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
++#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
++#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SEM_VF_ENABLE__VALUE_MASK 0x1
++#define SEM_VF_ENABLE__VALUE__SHIFT 0x0
++#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SEM_STATUS__SEM_IDLE_MASK 0x1
++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
++#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
++#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
++#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x8000
++#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf
++#define SEM_STATUS__SWITCH_READY_MASK 0x80000000
++#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
++#define SEM_MAILBOX__SIDEPORT_MASK 0xff
++#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
++#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
++#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
++#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
++#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
++#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
++#define SEM_CHICKEN_BITS__SIGNAL_FAIL_MASK 0x20
++#define SEM_CHICKEN_BITS__SIGNAL_FAIL__SHIFT 0x5
++#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x40
++#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6
++#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x80
++#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7
++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
++#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x3000
++#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc
++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
++#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
++#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
++#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
++#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
++#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
++#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
++#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT_MASK 0x80000
++#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT__SHIFT 0x13
++#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL__MEID_MASK 0xc
++#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
++#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
++#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
++#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
++#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
++#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS2__VP8_BUSY_MASK 0x10
++#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4
++#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
++#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
++#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
++#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
++#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
++#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
++#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
++#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
++#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
++#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
++#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
++#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
++#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
++#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
++#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
++#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
++#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
++#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
++#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000
++#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf
++#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
++#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
++#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
++#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
++#define SRBM_STATUS2__VP8_RQ_PENDING_MASK 0x40000
++#define SRBM_STATUS2__VP8_RQ_PENDING__SHIFT 0x12
++#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
++#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
++#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
++#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
++#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
++#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
++#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
++#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
++#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
++#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
++#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
++#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
++#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
++#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
++#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
++#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
++#define SRBM_STATUS__VMC_BUSY_MASK 0x100
++#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
++#define SRBM_STATUS__MCB_BUSY_MASK 0x200
++#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
++#define SRBM_STATUS__MCC_BUSY_MASK 0x800
++#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
++#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
++#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
++#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
++#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
++#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
++#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
++#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
++#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
++#define SRBM_STATUS__IH_BUSY_MASK 0x20000
++#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
++#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
++#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
++#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
++#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
++#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
++#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
++#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
++#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
++#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
++#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
++#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
++#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
++#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
++#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
++#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
++#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
++#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
++#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
++#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
++#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
++#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
++#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
++#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
++#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
++#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
++#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
++#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
++#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
++#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
++#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
++#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
++#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
++#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
++#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
++#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
++#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
++#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
++#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
++#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
++#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
++#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
++#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
++#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4
++#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
++#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
++#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
++#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
++#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
++#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
++#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
++#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
++#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
++#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
++#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
++#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
++#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000
++#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
++#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
++#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
++#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000
++#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
++#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
++#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
++#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
++#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
++#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
++#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
++#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
++#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
++#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
++#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
++#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
++#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
++#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
++#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800
++#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
++#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2
++#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
++#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
++#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400
++#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
++#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000
++#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
++#define SRBM_DEBUG_SNAPSHOT__RESERVED_MASK 0x40000000
++#define SRBM_DEBUG_SNAPSHOT__RESERVED__SHIFT 0x1e
++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
++#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
++#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
++#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
++#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
++#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
++#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
++#define SRBM_READ_ERROR__READ_REQUESTER_VP8_MASK 0x8000000
++#define SRBM_READ_ERROR__READ_REQUESTER_VP8__SHIFT 0x1b
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
++#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
++#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
++#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
++#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
++#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
++#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
++#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
++#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
++#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
++#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
++#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
++#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
++#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
++#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
++#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
++#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
++#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8_MASK 0x4
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8__SHIFT 0x2
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
++#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
++#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
++#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
++#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
++#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
++#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
++#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
++#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
++#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
++#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
++#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
++#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
++#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
++#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
++#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
++#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff
++#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
++#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2
++#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
++#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA0_HASH__BANK_BITS_MASK 0x70
++#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA0_STATUS_REG__IDLE_MASK 0x1
++#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
++#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3
++#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
++#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400
++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800
++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
++#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
++#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA0_F32_CNTL__HALT_MASK 0x1
++#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA0_F32_CNTL__STEP_MASK 0x2
++#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
++#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
++#define SDMA0_FREEZE__FREEZE_MASK 0x10
++#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA0_FREEZE__FROZEN_MASK 0x20
++#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
++#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
++#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
++#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
++#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
++#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
++#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
++#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
++#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
++#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
++#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
++#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
++#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
++#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
++#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
++#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
++#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
++#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
++#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
++#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
++#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
++#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
++#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
++#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
++#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
++#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
++#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
++#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
++#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
++#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
++#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
++#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
++#define SDMA0_ID__DEVICE_ID_MASK 0xff
++#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
++#define SDMA0_VERSION__VALUE_MASK 0xffff
++#define SDMA0_VERSION__VALUE__SHIFT 0x0
++#define SDMA0_VM_CNTL__CMD_MASK 0xf
++#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
++#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
++#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff
++#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
++#define SDMA0_STATUS2_REG__ID_MASK 0x3
++#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
++#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
++#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
++#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
++#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
++#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1
++#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
++#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0
++#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
++#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
++#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
++#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
++#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
++#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
++#define SDMA0_ATCL1_CNTL__REDO_ENABLE_MASK 0x1
++#define SDMA0_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0
++#define SDMA0_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe
++#define SDMA0_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1
++#define SDMA0_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800
++#define SDMA0_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb
++#define SDMA0_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000
++#define SDMA0_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe
++#define SDMA0_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000
++#define SDMA0_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
++#define SDMA0_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000
++#define SDMA0_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c
++#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff
++#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
++#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00
++#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
++#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000
++#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
++#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000
++#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18
++#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
++#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
++#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
++#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
++#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
++#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
++#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
++#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
++#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
++#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
++#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
++#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
++#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
++#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
++#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
++#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
++#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
++#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
++#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
++#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
++#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
++#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
++#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
++#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
++#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
++#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
++#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
++#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
++#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
++#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000
++#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12
++#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000
++#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13
++#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000
++#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14
++#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000
++#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
++#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000
++#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
++#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000
++#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
++#define SDMA0_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000
++#define SDMA0_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d
++#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
++#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
++#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
++#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
++#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
++#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
++#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
++#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
++#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
++#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
++#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
++#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
++#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
++#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
++#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
++#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
++#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
++#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
++#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
++#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
++#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
++#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
++#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
++#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
++#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
++#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
++#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
++#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
++#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
++#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000
++#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12
++#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000
++#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13
++#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000
++#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14
++#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000
++#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
++#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000
++#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
++#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000
++#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a
++#define SDMA0_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000
++#define SDMA0_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d
++#define SDMA0_ATCL1_INV0__INV_MIDDLE_MASK 0x1
++#define SDMA0_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0
++#define SDMA0_ATCL1_INV0__RD_TIMEOUT_MASK 0x2
++#define SDMA0_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1
++#define SDMA0_ATCL1_INV0__WR_TIMEOUT_MASK 0x4
++#define SDMA0_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2
++#define SDMA0_ATCL1_INV0__RD_IN_INVADR_MASK 0x8
++#define SDMA0_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3
++#define SDMA0_ATCL1_INV0__WR_IN_INVADR_MASK 0x10
++#define SDMA0_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4
++#define SDMA0_ATCL1_INV0__RD_WT_INVADR_MASK 0x20
++#define SDMA0_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5
++#define SDMA0_ATCL1_INV0__WR_WT_INVADR_MASK 0x40
++#define SDMA0_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6
++#define SDMA0_ATCL1_INV0__RD_INV_EN_MASK 0x80
++#define SDMA0_ATCL1_INV0__RD_INV_EN__SHIFT 0x7
++#define SDMA0_ATCL1_INV0__WR_INV_EN_MASK 0x100
++#define SDMA0_ATCL1_INV0__WR_INV_EN__SHIFT 0x8
++#define SDMA0_ATCL1_INV0__RD_INV_IDLE_MASK 0x200
++#define SDMA0_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9
++#define SDMA0_ATCL1_INV0__WR_INV_IDLE_MASK 0x400
++#define SDMA0_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa
++#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800
++#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
++#define SDMA0_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000
++#define SDMA0_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc
++#define SDMA0_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000
++#define SDMA0_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
++#define SDMA0_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff
++#define SDMA0_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0
++#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff
++#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
++#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
++#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
++#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf
++#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
++#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0
++#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
++#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100
++#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8
++#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
++#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
++#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf
++#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
++#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0
++#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
++#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100
++#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8
++#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff
++#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
++#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000
++#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
++#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0xffff
++#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
++#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000
++#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
++#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000
++#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4
++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2
++#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
++#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000
++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000
++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000
++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x40
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x80
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x100
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x200
++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00
++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2
++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4
++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20
++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5
++#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40
++#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6
++#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80
++#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7
++#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
++#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa
++#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800
++#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf
++#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
++#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
++#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
++#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
++#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12
++#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15
++#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000
++#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000
++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19
++#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a
++#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b
++#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c
++#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000
++#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d
++#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
++#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2
++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8
++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80
++#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL_MASK 0x800
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL__SHIFT 0xb
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK_MASK 0x1000
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK__SHIFT 0xc
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT_MASK 0x2000
++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT__SHIFT 0xd
++#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000
++#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xe
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff
++#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff
++#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff
++#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff
++#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
++#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
++#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
++#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
++#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
++#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
++#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
++#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2
++#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
++#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
++#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
++#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
++#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
++#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
++#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
++#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
++#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
++#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
++#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
++#define SDMA1_HASH__BANK_BITS_MASK 0x70
++#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
++#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
++#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
++#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
++#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
++#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
++#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
++#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
++#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
++#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
++#define SDMA1_STATUS_REG__IDLE_MASK 0x1
++#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
++#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
++#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
++#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
++#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
++#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
++#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
++#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
++#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
++#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
++#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
++#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
++#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
++#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
++#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
++#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
++#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
++#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
++#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
++#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
++#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
++#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
++#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
++#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
++#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
++#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
++#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
++#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
++#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
++#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
++#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
++#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
++#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
++#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
++#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
++#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
++#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
++#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
++#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
++#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
++#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
++#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
++#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
++#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
++#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
++#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
++#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
++#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
++#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
++#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
++#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
++#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
++#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
++#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
++#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
++#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
++#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
++#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
++#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3
++#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
++#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
++#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400
++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800
++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
++#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
++#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
++#define SDMA1_F32_CNTL__HALT_MASK 0x1
++#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
++#define SDMA1_F32_CNTL__STEP_MASK 0x2
++#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
++#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
++#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
++#define SDMA1_FREEZE__FREEZE_MASK 0x10
++#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
++#define SDMA1_FREEZE__FROZEN_MASK 0x20
++#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
++#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
++#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
++#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
++#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
++#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
++#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
++#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
++#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
++#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
++#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
++#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
++#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
++#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
++#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
++#define SDMA1_ID__DEVICE_ID_MASK 0xff
++#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
++#define SDMA1_VERSION__VALUE_MASK 0xffff
++#define SDMA1_VERSION__VALUE__SHIFT 0x0
++#define SDMA1_VM_CNTL__CMD_MASK 0xf
++#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
++#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
++#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff
++#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
++#define SDMA1_STATUS2_REG__ID_MASK 0x3
++#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
++#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
++#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
++#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
++#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
++#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf
++#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
++#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000
++#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
++#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1
++#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
++#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0
++#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
++#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff
++#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1
++#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
++#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
++#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
++#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
++#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
++#define SDMA1_ATCL1_CNTL__REDO_ENABLE_MASK 0x1
++#define SDMA1_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0
++#define SDMA1_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe
++#define SDMA1_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1
++#define SDMA1_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800
++#define SDMA1_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb
++#define SDMA1_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000
++#define SDMA1_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe
++#define SDMA1_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000
++#define SDMA1_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
++#define SDMA1_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000
++#define SDMA1_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c
++#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff
++#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
++#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00
++#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
++#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000
++#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
++#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000
++#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18
++#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
++#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
++#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
++#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
++#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
++#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
++#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
++#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
++#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
++#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
++#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
++#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
++#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
++#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
++#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
++#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
++#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
++#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
++#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
++#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
++#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
++#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
++#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
++#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
++#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
++#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
++#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
++#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
++#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
++#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000
++#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12
++#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000
++#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13
++#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000
++#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14
++#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000
++#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
++#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000
++#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
++#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000
++#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
++#define SDMA1_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000
++#define SDMA1_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d
++#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
++#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
++#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
++#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
++#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
++#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
++#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
++#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
++#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
++#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
++#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
++#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
++#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
++#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
++#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
++#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
++#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
++#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
++#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
++#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
++#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
++#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
++#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
++#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
++#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
++#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
++#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
++#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
++#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
++#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000
++#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12
++#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000
++#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13
++#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000
++#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14
++#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000
++#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
++#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000
++#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
++#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000
++#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a
++#define SDMA1_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000
++#define SDMA1_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d
++#define SDMA1_ATCL1_INV0__INV_MIDDLE_MASK 0x1
++#define SDMA1_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0
++#define SDMA1_ATCL1_INV0__RD_TIMEOUT_MASK 0x2
++#define SDMA1_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1
++#define SDMA1_ATCL1_INV0__WR_TIMEOUT_MASK 0x4
++#define SDMA1_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2
++#define SDMA1_ATCL1_INV0__RD_IN_INVADR_MASK 0x8
++#define SDMA1_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3
++#define SDMA1_ATCL1_INV0__WR_IN_INVADR_MASK 0x10
++#define SDMA1_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4
++#define SDMA1_ATCL1_INV0__RD_WT_INVADR_MASK 0x20
++#define SDMA1_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5
++#define SDMA1_ATCL1_INV0__WR_WT_INVADR_MASK 0x40
++#define SDMA1_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6
++#define SDMA1_ATCL1_INV0__RD_INV_EN_MASK 0x80
++#define SDMA1_ATCL1_INV0__RD_INV_EN__SHIFT 0x7
++#define SDMA1_ATCL1_INV0__WR_INV_EN_MASK 0x100
++#define SDMA1_ATCL1_INV0__WR_INV_EN__SHIFT 0x8
++#define SDMA1_ATCL1_INV0__RD_INV_IDLE_MASK 0x200
++#define SDMA1_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9
++#define SDMA1_ATCL1_INV0__WR_INV_IDLE_MASK 0x400
++#define SDMA1_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa
++#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800
++#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
++#define SDMA1_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000
++#define SDMA1_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc
++#define SDMA1_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000
++#define SDMA1_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
++#define SDMA1_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff
++#define SDMA1_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0
++#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff
++#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
++#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
++#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
++#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf
++#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
++#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0
++#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
++#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100
++#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8
++#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
++#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
++#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf
++#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
++#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0
++#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
++#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100
++#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8
++#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff
++#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
++#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000
++#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
++#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0xffff
++#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
++#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000
++#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
++#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000
++#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4
++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2
++#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
++#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000
++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
++#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000
++#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000
++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000
++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x40
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x80
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x100
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x200
++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9
++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00
++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2
++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4
++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20
++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5
++#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40
++#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6
++#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80
++#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7
++#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
++#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa
++#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800
++#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf
++#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
++#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
++#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
++#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
++#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12
++#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15
++#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000
++#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16
++#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a
++#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b
++#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c
++#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000
++#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d
++#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
++#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2
++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8
++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80
++#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL_MASK 0x800
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL__SHIFT 0xb
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK_MASK 0x1000
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK__SHIFT 0xc
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT_MASK 0x2000
++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT__SHIFT 0xd
++#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000
++#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xe
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff
++#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff
++#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
++#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
++#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
++#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
++#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
++#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
++#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
++#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
++#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
++#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
++#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
++#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
++#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
++#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
++#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
++#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
++#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
++#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
++#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
++#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
++#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
++#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
++#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
++#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
++#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
++#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
++#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
++#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
++#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff
++#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
++#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
++#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
++#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
++#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
++#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
++#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
++#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
++#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
++#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
++#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
++#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
++#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
++#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
++#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
++#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
++#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
++#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
++#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
++#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
++#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
++#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
++#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
++#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
++#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
++#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
++#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
++#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000
++#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16
++#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000
++#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17
++#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
++#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
++#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
++#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
++#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
++#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
++#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
++#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
++#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
++#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
++#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
++#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
++#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000
++#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
++#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000
++#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
++#define HDP_VF_ENABLE__VF_EN_MASK 0x1
++#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0
++#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000
++#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
++#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
++#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
++#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
++#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
++#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
++#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
++#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
++#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
++#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
++#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
++#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
++#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
++#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
++#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
++#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
++#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
++#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
++#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
++#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
++#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
++#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
++#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
++#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
++#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
++#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
++#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
++#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
++#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
++#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
++#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
++#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
++
++#endif /* OSS_3_0_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0018-yocto-amd-drm-amdgpu-add-UVD-4-2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0018-yocto-amd-drm-amdgpu-add-UVD-4-2-register-headers.patch
new file mode 100644
index 00000000..1fa3486a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0018-yocto-amd-drm-amdgpu-add-UVD-4-2-register-headers.patch
@@ -0,0 +1,4608 @@
+From 4e2aa447f6f0e5e86ada9844bb6f7607d8ec77c0 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:28:58 -0400
+Subject: drm/amdgpu: add SMU 7.0.0 register headers
+
+These are register headers for the SMU (System Management Unit)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h
+new file mode 100644
+index 0000000..f67560b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h
+@@ -0,0 +1,741 @@
++/*
++ * SMU_7_0_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_0_0_D_H
++#define SMU_7_0_0_D_H
++
++#define mmGCK_SMC_IND_INDEX                                                     0x80
++#define mmGCK0_GCK_SMC_IND_INDEX                                                0x80
++#define mmGCK1_GCK_SMC_IND_INDEX                                                0x82
++#define mmGCK2_GCK_SMC_IND_INDEX                                                0x84
++#define mmGCK3_GCK_SMC_IND_INDEX                                                0x86
++#define mmGCK_SMC_IND_DATA                                                      0x81
++#define mmGCK0_GCK_SMC_IND_DATA                                                 0x81
++#define mmGCK1_GCK_SMC_IND_DATA                                                 0x83
++#define mmGCK2_GCK_SMC_IND_DATA                                                 0x85
++#define mmGCK3_GCK_SMC_IND_DATA                                                 0x87
++#define ixCG_DCLK_CNTL                                                          0xc050009c
++#define ixCG_DCLK_STATUS                                                        0xc05000a0
++#define ixCG_VCLK_CNTL                                                          0xc05000a4
++#define ixCG_VCLK_STATUS                                                        0xc05000a8
++#define ixCG_ECLK_CNTL                                                          0xc05000ac
++#define ixCG_ECLK_STATUS                                                        0xc05000b0
++#define ixCG_ACLK_CNTL                                                          0xc05000dc
++#define ixGCK_DFS_BYPASS_CNTL                                                   0xc0500118
++#define ixCG_SPLL_FUNC_CNTL                                                     0xc0500140
++#define ixCG_SPLL_FUNC_CNTL_2                                                   0xc0500144
++#define ixCG_SPLL_FUNC_CNTL_3                                                   0xc0500148
++#define ixCG_SPLL_FUNC_CNTL_4                                                   0xc050014c
++#define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
++#define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
++#define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixSPLL_CNTL_MODE                                                        0xc0500160
++#define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
++#define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
++#define ixMPLL_BYPASSCLK_SEL                                                    0xc050019c
++#define ixCG_CLKPIN_CNTL                                                        0xc05001a0
++#define ixCG_CLKPIN_CNTL_2                                                      0xc05001a4
++#define ixTHM_CLK_CNTL                                                          0xc05001a8
++#define ixMISC_CLK_CTRL                                                         0xc05001ac
++#define ixGCK_PLL_TEST_CNTL                                                     0xc05001c0
++#define ixGCK_PLL_TEST_CNTL_2                                                   0xc05001c4
++#define ixGCK_ADFS_CLK_BYPASS_CNTL1                                             0xc05001c8
++#define mmSMC_IND_INDEX                                                         0x80
++#define mmSMC0_SMC_IND_INDEX                                                    0x80
++#define mmSMC1_SMC_IND_INDEX                                                    0x82
++#define mmSMC2_SMC_IND_INDEX                                                    0x84
++#define mmSMC3_SMC_IND_INDEX                                                    0x86
++#define mmSMC_IND_DATA                                                          0x81
++#define mmSMC0_SMC_IND_DATA                                                     0x81
++#define mmSMC1_SMC_IND_DATA                                                     0x83
++#define mmSMC2_SMC_IND_DATA                                                     0x85
++#define mmSMC3_SMC_IND_DATA                                                     0x87
++#define mmSMC_IND_INDEX_0                                                       0x80
++#define mmSMC_IND_DATA_0                                                        0x81
++#define mmSMC_IND_INDEX_1                                                       0x82
++#define mmSMC_IND_DATA_1                                                        0x83
++#define mmSMC_IND_INDEX_2                                                       0x84
++#define mmSMC_IND_DATA_2                                                        0x85
++#define mmSMC_IND_INDEX_3                                                       0x86
++#define mmSMC_IND_DATA_3                                                        0x87
++#define mmSMC_IND_INDEX_4                                                       0x88
++#define mmSMC_IND_DATA_4                                                        0x89
++#define mmSMC_IND_INDEX_5                                                       0x8a
++#define mmSMC_IND_DATA_5                                                        0x8b
++#define mmSMC_IND_INDEX_6                                                       0x8c
++#define mmSMC_IND_DATA_6                                                        0x8d
++#define mmSMC_IND_INDEX_7                                                       0x8e
++#define mmSMC_IND_DATA_7                                                        0x8f
++#define mmSMC_IND_ACCESS_CNTL                                                   0x90
++#define mmSMC_MESSAGE_0                                                         0x94
++#define mmSMC_RESP_0                                                            0x95
++#define mmSMC_MESSAGE_1                                                         0x96
++#define mmSMC_RESP_1                                                            0x97
++#define mmSMC_MESSAGE_2                                                         0x98
++#define mmSMC_RESP_2                                                            0x99
++#define mmSMC_MESSAGE_3                                                         0x9a
++#define mmSMC_RESP_3                                                            0x9b
++#define mmSMC_MESSAGE_4                                                         0x9c
++#define mmSMC_RESP_4                                                            0x9d
++#define mmSMC_MESSAGE_5                                                         0x9e
++#define mmSMC_RESP_5                                                            0x9f
++#define mmSMC_MESSAGE_6                                                         0xa0
++#define mmSMC_RESP_6                                                            0xa1
++#define mmSMC_MESSAGE_7                                                         0xa2
++#define mmSMC_RESP_7                                                            0xa3
++#define mmSMC_MSG_ARG_0                                                         0xa4
++#define mmSMC_MSG_ARG_1                                                         0xa5
++#define mmSMC_MSG_ARG_2                                                         0xa6
++#define mmSMC_MSG_ARG_3                                                         0xa7
++#define mmSMC_MSG_ARG_4                                                         0xa8
++#define mmSMC_MSG_ARG_5                                                         0xa9
++#define mmSMC_MSG_ARG_6                                                         0xaa
++#define mmSMC_MSG_ARG_7                                                         0xab
++#define mmSMC_MESSAGE_8                                                         0xb5
++#define mmSMC_RESP_8                                                            0xb6
++#define mmSMC_MESSAGE_9                                                         0xb7
++#define mmSMC_RESP_9                                                            0xb8
++#define mmSMC_MESSAGE_10                                                        0xb9
++#define mmSMC_RESP_10                                                           0xba
++#define mmSMC_MESSAGE_11                                                        0xbb
++#define mmSMC_RESP_11                                                           0xbc
++#define mmSMC_MSG_ARG_8                                                         0xbd
++#define mmSMC_MSG_ARG_9                                                         0xbe
++#define mmSMC_MSG_ARG_10                                                        0xbf
++#define mmSMC_MSG_ARG_11                                                        0x91
++#define ixSMC_SYSCON_RESET_CNTL                                                 0x80000000
++#define ixSMC_SYSCON_CLOCK_CNTL_0                                               0x80000004
++#define ixSMC_SYSCON_CLOCK_CNTL_1                                               0x80000008
++#define ixSMC_SYSCON_CLOCK_CNTL_2                                               0x8000000c
++#define ixSMC_SYSCON_MISC_CNTL                                                  0x80000010
++#define ixSMC_SYSCON_MSG_ARG_0                                                  0x80000068
++#define ixSMC_PC_C                                                              0x80000370
++#define ixSMC_SCRATCH9                                                          0x80000424
++#define mmCG_FPS_CNT                                                            0x1a4
++#define mmSMU_SMC_IND_INDEX                                                     0x80
++#define mmSMU0_SMU_SMC_IND_INDEX                                                0x80
++#define mmSMU1_SMU_SMC_IND_INDEX                                                0x82
++#define mmSMU2_SMU_SMC_IND_INDEX                                                0x84
++#define mmSMU3_SMU_SMC_IND_INDEX                                                0x86
++#define mmSMU_SMC_IND_DATA                                                      0x81
++#define mmSMU0_SMU_SMC_IND_DATA                                                 0x81
++#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83
++#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85
++#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87
++#define ixRCU_UC_EVENTS                                                         0xc0000004
++#define ixRCU_MISC_CTRL                                                         0xc0000010
++#define ixCC_RCU_FUSES                                                          0xc00c0000
++#define ixCC_SMU_MISC_FUSES                                                     0xc00c0004
++#define ixCC_SCLK_VID_FUSES                                                     0xc00c0008
++#define ixCC_GIO_IOCCFG_FUSES                                                   0xc00c000c
++#define ixCC_GIO_IOC_FUSES                                                      0xc00c0010
++#define ixCC_SMU_TST_EFUSE1_MISC                                                0xc00c001c
++#define ixCC_TST_ID_STRAPS                                                      0xc00c0020
++#define ixCC_FCTRL_FUSES                                                        0xc00c0024
++#define ixSMU_MAIN_PLL_OP_FREQ                                                  0xe0003020
++#define ixSMU_STATUS                                                            0xe0003088
++#define ixSMU_FIRMWARE                                                          0xe00030a4
++#define ixSMU_INPUT_DATA                                                        0xe00030b8
++#define ixSMU_EFUSE_0                                                           0xc0100000
++#define ixDPM_TABLE_1                                                           0x3f000
++#define ixDPM_TABLE_2                                                           0x3f004
++#define ixDPM_TABLE_3                                                           0x3f008
++#define ixDPM_TABLE_4                                                           0x3f00c
++#define ixDPM_TABLE_5                                                           0x3f010
++#define ixDPM_TABLE_6                                                           0x3f014
++#define ixDPM_TABLE_7                                                           0x3f018
++#define ixDPM_TABLE_8                                                           0x3f01c
++#define ixDPM_TABLE_9                                                           0x3f020
++#define ixDPM_TABLE_10                                                          0x3f024
++#define ixDPM_TABLE_11                                                          0x3f028
++#define ixDPM_TABLE_12                                                          0x3f02c
++#define ixDPM_TABLE_13                                                          0x3f030
++#define ixDPM_TABLE_14                                                          0x3f034
++#define ixDPM_TABLE_15                                                          0x3f038
++#define ixDPM_TABLE_16                                                          0x3f03c
++#define ixDPM_TABLE_17                                                          0x3f040
++#define ixDPM_TABLE_18                                                          0x3f044
++#define ixDPM_TABLE_19                                                          0x3f048
++#define ixDPM_TABLE_20                                                          0x3f04c
++#define ixDPM_TABLE_21                                                          0x3f050
++#define ixDPM_TABLE_22                                                          0x3f054
++#define ixDPM_TABLE_23                                                          0x3f058
++#define ixDPM_TABLE_24                                                          0x3f05c
++#define ixDPM_TABLE_25                                                          0x3f060
++#define ixDPM_TABLE_26                                                          0x3f064
++#define ixDPM_TABLE_27                                                          0x3f068
++#define ixDPM_TABLE_28                                                          0x3f06c
++#define ixDPM_TABLE_29                                                          0x3f070
++#define ixDPM_TABLE_30                                                          0x3f074
++#define ixDPM_TABLE_31                                                          0x3f078
++#define ixDPM_TABLE_32                                                          0x3f07c
++#define ixDPM_TABLE_33                                                          0x3f080
++#define ixDPM_TABLE_34                                                          0x3f084
++#define ixDPM_TABLE_35                                                          0x3f088
++#define ixDPM_TABLE_36                                                          0x3f08c
++#define ixDPM_TABLE_37                                                          0x3f090
++#define ixDPM_TABLE_38                                                          0x3f094
++#define ixDPM_TABLE_39                                                          0x3f098
++#define ixDPM_TABLE_40                                                          0x3f09c
++#define ixDPM_TABLE_41                                                          0x3f0a0
++#define ixDPM_TABLE_42                                                          0x3f0a4
++#define ixDPM_TABLE_43                                                          0x3f0a8
++#define ixDPM_TABLE_44                                                          0x3f0ac
++#define ixDPM_TABLE_45                                                          0x3f0b0
++#define ixDPM_TABLE_46                                                          0x3f0b4
++#define ixDPM_TABLE_47                                                          0x3f0b8
++#define ixDPM_TABLE_48                                                          0x3f0bc
++#define ixDPM_TABLE_49                                                          0x3f0c0
++#define ixDPM_TABLE_50                                                          0x3f0c4
++#define ixDPM_TABLE_51                                                          0x3f0c8
++#define ixDPM_TABLE_52                                                          0x3f0cc
++#define ixDPM_TABLE_53                                                          0x3f0d0
++#define ixDPM_TABLE_54                                                          0x3f0d4
++#define ixDPM_TABLE_55                                                          0x3f0d8
++#define ixDPM_TABLE_56                                                          0x3f0dc
++#define ixDPM_TABLE_57                                                          0x3f0e0
++#define ixDPM_TABLE_58                                                          0x3f0e4
++#define ixDPM_TABLE_59                                                          0x3f0e8
++#define ixDPM_TABLE_60                                                          0x3f0ec
++#define ixDPM_TABLE_61                                                          0x3f0f0
++#define ixDPM_TABLE_62                                                          0x3f0f4
++#define ixDPM_TABLE_63                                                          0x3f0f8
++#define ixDPM_TABLE_64                                                          0x3f0fc
++#define ixDPM_TABLE_65                                                          0x3f100
++#define ixDPM_TABLE_66                                                          0x3f104
++#define ixDPM_TABLE_67                                                          0x3f108
++#define ixDPM_TABLE_68                                                          0x3f10c
++#define ixDPM_TABLE_69                                                          0x3f110
++#define ixDPM_TABLE_70                                                          0x3f114
++#define ixDPM_TABLE_71                                                          0x3f118
++#define ixDPM_TABLE_72                                                          0x3f11c
++#define ixDPM_TABLE_73                                                          0x3f120
++#define ixDPM_TABLE_74                                                          0x3f124
++#define ixDPM_TABLE_75                                                          0x3f128
++#define ixDPM_TABLE_76                                                          0x3f12c
++#define ixDPM_TABLE_77                                                          0x3f130
++#define ixDPM_TABLE_78                                                          0x3f134
++#define ixDPM_TABLE_79                                                          0x3f138
++#define ixDPM_TABLE_80                                                          0x3f13c
++#define ixDPM_TABLE_81                                                          0x3f140
++#define ixDPM_TABLE_82                                                          0x3f144
++#define ixDPM_TABLE_83                                                          0x3f148
++#define ixDPM_TABLE_84                                                          0x3f14c
++#define ixDPM_TABLE_85                                                          0x3f150
++#define ixDPM_TABLE_86                                                          0x3f154
++#define ixDPM_TABLE_87                                                          0x3f158
++#define ixDPM_TABLE_88                                                          0x3f15c
++#define ixDPM_TABLE_89                                                          0x3f160
++#define ixDPM_TABLE_90                                                          0x3f164
++#define ixDPM_TABLE_91                                                          0x3f168
++#define ixDPM_TABLE_92                                                          0x3f16c
++#define ixDPM_TABLE_93                                                          0x3f170
++#define ixDPM_TABLE_94                                                          0x3f174
++#define ixDPM_TABLE_95                                                          0x3f178
++#define ixDPM_TABLE_96                                                          0x3f17c
++#define ixDPM_TABLE_97                                                          0x3f180
++#define ixDPM_TABLE_98                                                          0x3f184
++#define ixDPM_TABLE_99                                                          0x3f188
++#define ixDPM_TABLE_100                                                         0x3f18c
++#define ixDPM_TABLE_101                                                         0x3f190
++#define ixDPM_TABLE_102                                                         0x3f194
++#define ixDPM_TABLE_103                                                         0x3f198
++#define ixDPM_TABLE_104                                                         0x3f19c
++#define ixDPM_TABLE_105                                                         0x3f1a0
++#define ixDPM_TABLE_106                                                         0x3f1a4
++#define ixDPM_TABLE_107                                                         0x3f1a8
++#define ixDPM_TABLE_108                                                         0x3f1ac
++#define ixDPM_TABLE_109                                                         0x3f1b0
++#define ixDPM_TABLE_110                                                         0x3f1b4
++#define ixDPM_TABLE_111                                                         0x3f1b8
++#define ixDPM_TABLE_112                                                         0x3f1bc
++#define ixDPM_TABLE_113                                                         0x3f1c0
++#define ixDPM_TABLE_114                                                         0x3f1c4
++#define ixDPM_TABLE_115                                                         0x3f1c8
++#define ixDPM_TABLE_116                                                         0x3f1cc
++#define ixDPM_TABLE_117                                                         0x3f1d0
++#define ixDPM_TABLE_118                                                         0x3f1d4
++#define ixDPM_TABLE_119                                                         0x3f1d8
++#define ixDPM_TABLE_120                                                         0x3f1dc
++#define ixDPM_TABLE_121                                                         0x3f1e0
++#define ixDPM_TABLE_122                                                         0x3f1e4
++#define ixDPM_TABLE_123                                                         0x3f1e8
++#define ixDPM_TABLE_124                                                         0x3f1ec
++#define ixDPM_TABLE_125                                                         0x3f1f0
++#define ixDPM_TABLE_126                                                         0x3f1f4
++#define ixDPM_TABLE_127                                                         0x3f1f8
++#define ixDPM_TABLE_128                                                         0x3f1fc
++#define ixDPM_TABLE_129                                                         0x3f200
++#define ixDPM_TABLE_130                                                         0x3f204
++#define ixDPM_TABLE_131                                                         0x3f208
++#define ixDPM_TABLE_132                                                         0x3f20c
++#define ixDPM_TABLE_133                                                         0x3f210
++#define ixDPM_TABLE_134                                                         0x3f214
++#define ixDPM_TABLE_135                                                         0x3f218
++#define ixDPM_TABLE_136                                                         0x3f21c
++#define ixDPM_TABLE_137                                                         0x3f220
++#define ixDPM_TABLE_138                                                         0x3f224
++#define ixDPM_TABLE_139                                                         0x3f228
++#define ixDPM_TABLE_140                                                         0x3f22c
++#define ixDPM_TABLE_141                                                         0x3f230
++#define ixDPM_TABLE_142                                                         0x3f234
++#define ixDPM_TABLE_143                                                         0x3f238
++#define ixDPM_TABLE_144                                                         0x3f23c
++#define ixDPM_TABLE_145                                                         0x3f240
++#define ixDPM_TABLE_146                                                         0x3f244
++#define ixDPM_TABLE_147                                                         0x3f248
++#define ixDPM_TABLE_148                                                         0x3f24c
++#define ixDPM_TABLE_149                                                         0x3f250
++#define ixDPM_TABLE_150                                                         0x3f254
++#define ixDPM_TABLE_151                                                         0x3f258
++#define ixDPM_TABLE_152                                                         0x3f25c
++#define ixDPM_TABLE_153                                                         0x3f260
++#define ixDPM_TABLE_154                                                         0x3f264
++#define ixDPM_TABLE_155                                                         0x3f268
++#define ixDPM_TABLE_156                                                         0x3f26c
++#define ixDPM_TABLE_157                                                         0x3f270
++#define ixDPM_TABLE_158                                                         0x3f274
++#define ixDPM_TABLE_159                                                         0x3f278
++#define ixDPM_TABLE_160                                                         0x3f27c
++#define ixDPM_TABLE_161                                                         0x3f280
++#define ixDPM_TABLE_162                                                         0x3f284
++#define ixDPM_TABLE_163                                                         0x3f288
++#define ixDPM_TABLE_164                                                         0x3f28c
++#define ixDPM_TABLE_165                                                         0x3f290
++#define ixDPM_TABLE_166                                                         0x3f294
++#define ixDPM_TABLE_167                                                         0x3f298
++#define ixDPM_TABLE_168                                                         0x3f29c
++#define ixDPM_TABLE_169                                                         0x3f2a0
++#define ixDPM_TABLE_170                                                         0x3f2a4
++#define ixDPM_TABLE_171                                                         0x3f2a8
++#define ixDPM_TABLE_172                                                         0x3f2ac
++#define ixDPM_TABLE_173                                                         0x3f2b0
++#define ixDPM_TABLE_174                                                         0x3f2b4
++#define ixDPM_TABLE_175                                                         0x3f2b8
++#define ixDPM_TABLE_176                                                         0x3f2bc
++#define ixDPM_TABLE_177                                                         0x3f2c0
++#define ixDPM_TABLE_178                                                         0x3f2c4
++#define ixDPM_TABLE_179                                                         0x3f2c8
++#define ixDPM_TABLE_180                                                         0x3f2cc
++#define ixDPM_TABLE_181                                                         0x3f2d0
++#define ixDPM_TABLE_182                                                         0x3f2d4
++#define ixDPM_TABLE_183                                                         0x3f2d8
++#define ixDPM_TABLE_184                                                         0x3f2dc
++#define ixDPM_TABLE_185                                                         0x3f2e0
++#define ixDPM_TABLE_186                                                         0x3f2e4
++#define ixDPM_TABLE_187                                                         0x3f2e8
++#define ixDPM_TABLE_188                                                         0x3f2ec
++#define ixDPM_TABLE_189                                                         0x3f2f0
++#define ixDPM_TABLE_190                                                         0x3f2f4
++#define ixDPM_TABLE_191                                                         0x3f2f8
++#define ixSOFT_REGISTERS_TABLE_1                                                0x3f900
++#define ixSOFT_REGISTERS_TABLE_2                                                0x3f904
++#define ixSOFT_REGISTERS_TABLE_3                                                0x3f908
++#define ixSOFT_REGISTERS_TABLE_4                                                0x3f90c
++#define ixSOFT_REGISTERS_TABLE_5                                                0x3f910
++#define ixSOFT_REGISTERS_TABLE_6                                                0x3f914
++#define ixSOFT_REGISTERS_TABLE_7                                                0x3f918
++#define ixSOFT_REGISTERS_TABLE_8                                                0x3f91c
++#define ixSOFT_REGISTERS_TABLE_9                                                0x3f920
++#define ixSOFT_REGISTERS_TABLE_10                                               0x3f924
++#define ixSOFT_REGISTERS_TABLE_11                                               0x3f928
++#define ixSOFT_REGISTERS_TABLE_12                                               0x3f92c
++#define ixSOFT_REGISTERS_TABLE_13                                               0x3f930
++#define ixSOFT_REGISTERS_TABLE_14                                               0x3f934
++#define ixSOFT_REGISTERS_TABLE_15                                               0x3f938
++#define ixSOFT_REGISTERS_TABLE_16                                               0x3f93c
++#define ixSOFT_REGISTERS_TABLE_17                                               0x3f940
++#define ixSOFT_REGISTERS_TABLE_18                                               0x3f944
++#define ixSOFT_REGISTERS_TABLE_19                                               0x3f948
++#define ixSOFT_REGISTERS_TABLE_20                                               0x3f94c
++#define ixSOFT_REGISTERS_TABLE_21                                               0x3f950
++#define ixSMU_LCLK_DPM_STATE_0_CNTL_0                                           0x3fd00
++#define ixSMU_LCLK_DPM_STATE_1_CNTL_0                                           0x3fd14
++#define ixSMU_LCLK_DPM_STATE_2_CNTL_0                                           0x3fd28
++#define ixSMU_LCLK_DPM_STATE_3_CNTL_0                                           0x3fd3c
++#define ixSMU_LCLK_DPM_STATE_4_CNTL_0                                           0x3fd50
++#define ixSMU_LCLK_DPM_STATE_5_CNTL_0                                           0x3fd64
++#define ixSMU_LCLK_DPM_STATE_6_CNTL_0                                           0x3fd78
++#define ixSMU_LCLK_DPM_STATE_7_CNTL_0                                           0x3fd8c
++#define ixSMU_LCLK_DPM_STATE_0_CNTL_1                                           0x3fd04
++#define ixSMU_LCLK_DPM_STATE_1_CNTL_1                                           0x3fd18
++#define ixSMU_LCLK_DPM_STATE_2_CNTL_1                                           0x3fd2c
++#define ixSMU_LCLK_DPM_STATE_3_CNTL_1                                           0x3fd40
++#define ixSMU_LCLK_DPM_STATE_4_CNTL_1                                           0x3fd54
++#define ixSMU_LCLK_DPM_STATE_5_CNTL_1                                           0x3fd68
++#define ixSMU_LCLK_DPM_STATE_6_CNTL_1                                           0x3fd7c
++#define ixSMU_LCLK_DPM_STATE_7_CNTL_1                                           0x3fd90
++#define ixSMU_LCLK_DPM_STATE_0_CNTL_2                                           0x3fd08
++#define ixSMU_LCLK_DPM_STATE_1_CNTL_2                                           0x3fd1c
++#define ixSMU_LCLK_DPM_STATE_2_CNTL_2                                           0x3fd30
++#define ixSMU_LCLK_DPM_STATE_3_CNTL_2                                           0x3fd44
++#define ixSMU_LCLK_DPM_STATE_4_CNTL_2                                           0x3fd58
++#define ixSMU_LCLK_DPM_STATE_5_CNTL_2                                           0x3fd6c
++#define ixSMU_LCLK_DPM_STATE_6_CNTL_2                                           0x3fd80
++#define ixSMU_LCLK_DPM_STATE_7_CNTL_2                                           0x3fd94
++#define ixSMU_LCLK_DPM_STATE_0_CNTL_3                                           0x3fd0c
++#define ixSMU_LCLK_DPM_STATE_1_CNTL_3                                           0x3fd20
++#define ixSMU_LCLK_DPM_STATE_2_CNTL_3                                           0x3fd34
++#define ixSMU_LCLK_DPM_STATE_3_CNTL_3                                           0x3fd48
++#define ixSMU_LCLK_DPM_STATE_4_CNTL_3                                           0x3fd5c
++#define ixSMU_LCLK_DPM_STATE_5_CNTL_3                                           0x3fd70
++#define ixSMU_LCLK_DPM_STATE_6_CNTL_3                                           0x3fd84
++#define ixSMU_LCLK_DPM_STATE_7_CNTL_3                                           0x3fd98
++#define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD                               0x3fd10
++#define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD                               0x3fd24
++#define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD                               0x3fd38
++#define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD                               0x3fd4c
++#define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD                               0x3fd60
++#define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD                               0x3fd74
++#define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD                               0x3fd88
++#define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD                               0x3fd9c
++#define ixGIO_PID_CONTROLLER_CNTL_0                                             0x3fda0
++#define ixGIO_PID_CONTROLLER_CNTL_1                                             0x3fda4
++#define ixGIO_PID_CONTROLLER_CNTL_2                                             0x3fda8
++#define ixGIO_PID_CONTROLLER_CNTL_3                                             0x3fdac
++#define ixGIO_PID_CONTROLLER_CNTL_4                                             0x3fdb0
++#define ixGIO_PID_CONTROLLER_CNTL_5                                             0x3fdb4
++#define ixGIO_PID_CONTROLLER_CNTL_6                                             0x3fdb8
++#define ixGIO_PID_CONTROLLER_CNTL_7                                             0x3fdbc
++#define ixGIO_PID_CONTROLLER_CNTL_8                                             0x3fdc0
++#define ixSMU_LCLK_DPM_LEVEL_COUNT                                              0x3fdc4
++#define ixSMU_LCLK_DPM_CNTL                                                     0x3fdc8
++#define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE                                 0x3fdcc
++#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL                                  0x3fdd0
++#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS                            0x3fdd4
++#define ixPM_FUSES_1                                                            0x3fa80
++#define ixPM_FUSES_2                                                            0x3fa84
++#define ixPM_FUSES_3                                                            0x3fa88
++#define ixPM_FUSES_4                                                            0x3fa8c
++#define ixPM_FUSES_5                                                            0x3fa90
++#define ixPM_FUSES_6                                                            0x3fa94
++#define ixPM_FUSES_7                                                            0x3fa98
++#define ixPM_FUSES_8                                                            0x3fa9c
++#define ixPM_FUSES_9                                                            0x3faa0
++#define ixPM_FUSES_10                                                           0x3faa4
++#define ixPM_FUSES_11                                                           0x3faa8
++#define ixPM_FUSES_12                                                           0x3faac
++#define ixPM_FUSES_13                                                           0x3fab0
++#define ixPM_FUSES_14                                                           0x3fab4
++#define ixPM_FUSES_15                                                           0x3fab8
++#define ixPM_FUSES_16                                                           0x3fabc
++#define ixPM_FUSES_17                                                           0x3fac0
++#define ixPM_FUSES_18                                                           0x3fac4
++#define ixPM_FUSES_19                                                           0x3fac8
++#define ixPM_FUSES_20                                                           0x3facc
++#define ixPM_FUSES_21                                                           0x3fad0
++#define ixPM_FUSES_22                                                           0x3fad4
++#define ixPM_FUSES_23                                                           0x3fad8
++#define ixPM_FUSES_24                                                           0x3fadc
++#define ixPM_FUSES_25                                                           0x3fae0
++#define ixPM_FUSES_26                                                           0x3fae4
++#define ixPM_FUSES_27                                                           0x3fae8
++#define ixPM_FUSES_28                                                           0x3faec
++#define ixPM_FUSES_29                                                           0x3faf0
++#define ixPM_FUSES_30                                                           0x3faf4
++#define ixPM_FUSES_31                                                           0x3faf8
++#define ixPM_FUSES_32                                                           0x3fafc
++#define ixPM_FUSES_33                                                           0x3fb00
++#define ixPM_FUSES_34                                                           0x3fb04
++#define ixPM_FUSES_35                                                           0x3fb08
++#define ixPM_FUSES_36                                                           0x3fb0c
++#define ixPM_FUSES_37                                                           0x3fb10
++#define ixPM_FUSES_38                                                           0x3fb14
++#define ixPM_FUSES_39                                                           0x3fb18
++#define ixPM_FUSES_40                                                           0x3fb1c
++#define ixPM_FUSES_41                                                           0x3fb20
++#define ixPM_FUSES_42                                                           0x3fb24
++#define ixPM_FUSES_43                                                           0x3fb28
++#define ixPM_FUSES_44                                                           0x3fb2c
++#define ixPM_FUSES_45                                                           0x3fb30
++#define ixPM_FUSES_46                                                           0x3fb34
++#define ixPM_FUSES_47                                                           0x3fb38
++#define ixPM_FUSES_48                                                           0x3fb3c
++#define ixPM_FUSES_49                                                           0x3fb40
++#define ixPM_FUSES_50                                                           0x3fb44
++#define ixPM_FUSES_51                                                           0x3fb48
++#define ixPM_FUSES_52                                                           0x3fb4c
++#define ixPM_FUSES_53                                                           0x3fb50
++#define ixPM_FUSES_54                                                           0x3fb54
++#define ixPM_FUSES_55                                                           0x3fb58
++#define ixPM_FUSES_56                                                           0x3fb5c
++#define ixPM_FUSES_57                                                           0x3fb60
++#define ixPM_FUSES_58                                                           0x3fb64
++#define ixPM_FUSES_59                                                           0x3fb68
++#define ixPM_FUSES_60                                                           0x3fb6c
++#define ixPM_FUSES_61                                                           0x3fb70
++#define ixPM_FUSES_62                                                           0x3fb74
++#define ixPM_FUSES_63                                                           0x3fb78
++#define ixPM_FUSES_64                                                           0x3fb7c
++#define ixPM_FUSES_65                                                           0x3fb80
++#define ixFIRMWARE_FLAGS                                                        0x3f800
++#define ixTEMPERATURE_READ_ADDR                                                 0x3f808
++#define ixCURRENT_GNB_TEMP                                                      0x3f810
++#define ixCURRENT_GLOBAL_TEMP                                                   0x3f814
++#define ixFEATURE_STATUS                                                        0x3f818
++#define ixPCIE_PLL_RECONF                                                       0x3f81c
++#define ixPM_INTERVAL_CNTL_0                                                    0x3f820
++#define ixPM_INTERVAL_CNTL_1                                                    0x3f824
++#define ixPM_INTERVAL_CNTL_2                                                    0x3f82c
++#define ixVPC_INTERVAL_CNTL                                                     0x3f830
++#define ixDISP_PHY_TDP_LIMIT                                                    0x3f834
++#define ixFCH_PWR_CREDIT                                                        0x3f838
++#define ixPKGPWR_MV_AVG                                                         0x3f83c
++#define ixPACKAGE_POWER                                                         0x3f840
++#define ixPKG_PWR_CNTL                                                          0x3f844
++#define ixPKG_PWR_STATUS                                                        0x3f848
++#define ixDISP_PHY_CONFIG                                                       0x3f84c
++#define ixGPU_TDP_LIMIT                                                         0x3f850
++#define ixEXT_API_IN_DATA_0_0                                                   0x3f858
++#define ixEXT_API_IN_DATA_0_1                                                   0x3f85c
++#define ixEXT_API_IN_DATA_0_2                                                   0x3f860
++#define ixEXT_API_IN_DATA_0_3                                                   0x3f864
++#define ixEXT_API_OUT_DATA_0_0                                                  0x3f868
++#define ixEXT_API_OUT_DATA_0_1                                                  0x3f86c
++#define ixEXT_API_OUT_DATA_0_2                                                  0x3f870
++#define ixEXT_API_OUT_DATA_0_3                                                  0x3f874
++#define ixBAPM_PARAMETERS                                                       0x3f984
++#define ixBAPM_PARAMETERS_2                                                     0x3f988
++#define ixBAPM_PARAMETERS_3                                                     0x3f98c
++#define ixBAPM_PARAMETERS_4                                                     0x3f990
++#define ixSMU_SVI_TELEMETRY                                                     0x3f994
++#define ixBAPM_STATUS                                                           0x3f998
++#define ixSMU_HTC_STATUS                                                        0x3f99c
++#define ixSMU_VPC_STATUS                                                        0x3f9a0
++#define ixENTITY_TEMPERATURES_1                                                 0x3f9a4
++#define ixENTITY_TEMPERATURES_2                                                 0x3f9a8
++#define ixENTITY_TEMPERATURES_3                                                 0x3f9ac
++#define ixCU_POWER                                                              0x3f9b0
++#define ixGPU_POWER                                                             0x3f9b4
++#define ixNTE_POWER                                                             0x3f9b8
++#define ixTDC_STATUS                                                            0x3f9d0
++#define ixTDC_MV_AVERAGE                                                        0x3f9d4
++#define ixPM_CONFIG                                                             0x3f9d8
++#define ixTE0_TEMPERATURE_READ_ADDR                                             0x3f9dc
++#define ixTE1_TEMPERATURE_READ_ADDR                                             0x3f9e0
++#define ixTE2_TEMPERATURE_READ_ADDR                                             0x3f9e4
++#define ixNB_DPM_CONFIG_1                                                       0x3f9e8
++#define ixNB_DPM_CONFIG_2                                                       0x3f9ec
++#define ixNB_DPM_CONFIG_3                                                       0x3f9f0
++#define ixSMU_IDD_OVERRIDE                                                      0x3f9fc
++#define ixAVS_CONFIG                                                            0x3fa00
++#define ixTDC_VRM_LIMIT                                                         0x3fa04
++#define ixCU0_PSM_CONFIG                                                        0x3fa08
++#define ixCU1_PSM_CONFIG                                                        0x3fa0c
++#define ixSPMI_CONFIG                                                           0x3fa10
++#define ixSPMI_SMC_CHAIN_ADDR                                                   0x3fa14
++#define ixSPMI_STATUS                                                           0x3fa30
++#define ixAVSNB_CONFIG                                                          0x3fa34
++#define ixHTC_CONFIG                                                            0x3fa38
++#define ixAVS_CU0_TEMPERATURE_SENSOR                                            0x3fa3c
++#define ixAVS_CU1_TEMPERATURE_SENSOR                                            0x3fa40
++#define ixAVS_GNB_TEMPERATURE_SENSOR                                            0x3fa44
++#define ixAVS_UNB_TEMPERATURE_SENSOR                                            0x3fa48
++#define ixSMU_MONITOR_PORT80_MMIO_ADDR                                          0x3fa4c
++#define ixSMU_MONITOR_PORT80_MEMBASE_HI                                         0x3fa50
++#define ixSMU_MONITOR_PORT80_MEMBASE_LO                                         0x3fa54
++#define ixSMU_MONITOR_PORT80_MEMSETUP                                           0x3fa58
++#define ixSMU_MONITOR_PORT80_CTRL                                               0x3fa5c
++#define ixSMU_TCEN_ALIVE                                                        0x3fa60
++#define ixPDM_STATUS                                                            0x3fa64
++#define ixPDM_CNTL_1                                                            0x3fa68
++#define ixPDM_CNTL_2                                                            0x3fa6c
++#define ixPDM_CNTL_3                                                            0x3fa70
++#define ixSMU_PM_STATUS_0                                                       0x3fe00
++#define ixSMU_PM_STATUS_1                                                       0x3fe04
++#define ixSMU_PM_STATUS_2                                                       0x3fe08
++#define ixSMU_PM_STATUS_3                                                       0x3fe0c
++#define ixSMU_PM_STATUS_4                                                       0x3fe10
++#define ixSMU_PM_STATUS_5                                                       0x3fe14
++#define ixSMU_PM_STATUS_6                                                       0x3fe18
++#define ixSMU_PM_STATUS_7                                                       0x3fe1c
++#define ixSMU_PM_STATUS_8                                                       0x3fe20
++#define ixSMU_PM_STATUS_9                                                       0x3fe24
++#define ixSMU_PM_STATUS_10                                                      0x3fe28
++#define ixSMU_PM_STATUS_11                                                      0x3fe2c
++#define ixSMU_PM_STATUS_12                                                      0x3fe30
++#define ixSMU_PM_STATUS_13                                                      0x3fe34
++#define ixSMU_PM_STATUS_14                                                      0x3fe38
++#define ixSMU_PM_STATUS_15                                                      0x3fe3c
++#define ixSMU_PM_STATUS_16                                                      0x3fe40
++#define ixSMU_PM_STATUS_17                                                      0x3fe44
++#define ixSMU_PM_STATUS_18                                                      0x3fe48
++#define ixSMU_PM_STATUS_19                                                      0x3fe4c
++#define ixSMU_PM_STATUS_20                                                      0x3fe50
++#define ixSMU_PM_STATUS_21                                                      0x3fe54
++#define ixSMU_PM_STATUS_22                                                      0x3fe58
++#define ixSMU_PM_STATUS_23                                                      0x3fe5c
++#define ixSMU_PM_STATUS_24                                                      0x3fe60
++#define ixSMU_PM_STATUS_25                                                      0x3fe64
++#define ixSMU_PM_STATUS_26                                                      0x3fe68
++#define ixSMU_PM_STATUS_27                                                      0x3fe6c
++#define ixSMU_PM_STATUS_28                                                      0x3fe70
++#define ixSMU_PM_STATUS_29                                                      0x3fe74
++#define ixSMU_PM_STATUS_30                                                      0x3fe78
++#define ixSMU_PM_STATUS_31                                                      0x3fe7c
++#define ixSMU_PM_STATUS_32                                                      0x3fe80
++#define ixSMU_PM_STATUS_33                                                      0x3fe84
++#define ixSMU_PM_STATUS_34                                                      0x3fe88
++#define ixSMU_PM_STATUS_35                                                      0x3fe8c
++#define ixSMU_PM_STATUS_36                                                      0x3fe90
++#define ixSMU_PM_STATUS_37                                                      0x3fe94
++#define ixSMU_PM_STATUS_38                                                      0x3fe98
++#define ixSMU_PM_STATUS_39                                                      0x3fe9c
++#define ixSMU_PM_STATUS_40                                                      0x3fea0
++#define ixSMU_PM_STATUS_41                                                      0x3fea4
++#define ixSMU_PM_STATUS_42                                                      0x3fea8
++#define ixSMU_PM_STATUS_43                                                      0x3feac
++#define ixSMU_PM_STATUS_44                                                      0x3feb0
++#define ixSMU_PM_STATUS_45                                                      0x3feb4
++#define ixSMU_PM_STATUS_46                                                      0x3feb8
++#define ixSMU_PM_STATUS_47                                                      0x3febc
++#define ixSMU_PM_STATUS_48                                                      0x3fec0
++#define ixSMU_PM_STATUS_49                                                      0x3fec4
++#define ixSMU_PM_STATUS_50                                                      0x3fec8
++#define ixSMU_PM_STATUS_51                                                      0x3fecc
++#define ixSMU_PM_STATUS_52                                                      0x3fed0
++#define ixSMU_PM_STATUS_53                                                      0x3fed4
++#define ixSMU_PM_STATUS_54                                                      0x3fed8
++#define ixSMU_PM_STATUS_55                                                      0x3fedc
++#define ixSMU_PM_STATUS_56                                                      0x3fee0
++#define ixSMU_PM_STATUS_57                                                      0x3fee4
++#define ixSMU_PM_STATUS_58                                                      0x3fee8
++#define ixSMU_PM_STATUS_59                                                      0x3feec
++#define ixSMU_PM_STATUS_60                                                      0x3fef0
++#define ixSMU_PM_STATUS_61                                                      0x3fef4
++#define ixSMU_PM_STATUS_62                                                      0x3fef8
++#define ixSMU_PM_STATUS_63                                                      0x3fefc
++#define ixSMU_PM_STATUS_64                                                      0x3ff00
++#define ixSMU_PM_STATUS_65                                                      0x3ff04
++#define ixSMU_PM_STATUS_66                                                      0x3ff08
++#define ixSMU_PM_STATUS_67                                                      0x3ff0c
++#define ixSMU_PM_STATUS_68                                                      0x3ff10
++#define ixSMU_PM_STATUS_69                                                      0x3ff14
++#define ixSMU_PM_STATUS_70                                                      0x3ff18
++#define ixSMU_PM_STATUS_71                                                      0x3ff1c
++#define ixSMU_PM_STATUS_72                                                      0x3ff20
++#define ixSMU_PM_STATUS_73                                                      0x3ff24
++#define ixSMU_PM_STATUS_74                                                      0x3ff28
++#define ixSMU_PM_STATUS_75                                                      0x3ff2c
++#define ixSMU_PM_STATUS_76                                                      0x3ff30
++#define ixSMU_PM_STATUS_77                                                      0x3ff34
++#define ixSMU_PM_STATUS_78                                                      0x3ff38
++#define ixSMU_PM_STATUS_79                                                      0x3ff3c
++#define ixSMU_PM_STATUS_80                                                      0x3ff40
++#define ixSMU_PM_STATUS_81                                                      0x3ff44
++#define ixSMU_PM_STATUS_82                                                      0x3ff48
++#define ixSMU_PM_STATUS_83                                                      0x3ff4c
++#define ixSMU_PM_STATUS_84                                                      0x3ff50
++#define ixSMU_PM_STATUS_85                                                      0x3ff54
++#define ixSMU_PM_STATUS_86                                                      0x3ff58
++#define ixSMU_PM_STATUS_87                                                      0x3ff5c
++#define ixSMU_PM_STATUS_88                                                      0x3ff60
++#define ixSMU_PM_STATUS_89                                                      0x3ff64
++#define ixSMU_PM_STATUS_90                                                      0x3ff68
++#define ixSMU_PM_STATUS_91                                                      0x3ff6c
++#define ixSMU_PM_STATUS_92                                                      0x3ff70
++#define ixSMU_PM_STATUS_93                                                      0x3ff74
++#define ixSMU_PM_STATUS_94                                                      0x3ff78
++#define ixSMU_PM_STATUS_95                                                      0x3ff7c
++#define ixSMU_PM_STATUS_96                                                      0x3ff80
++#define ixSMU_PM_STATUS_97                                                      0x3ff84
++#define ixSMU_PM_STATUS_98                                                      0x3ff88
++#define ixSMU_PM_STATUS_99                                                      0x3ff8c
++#define ixSMU_PM_STATUS_100                                                     0x3ff90
++#define ixSMU_PM_STATUS_101                                                     0x3ff94
++#define ixSMU_PM_STATUS_102                                                     0x3ff98
++#define ixSMU_PM_STATUS_103                                                     0x3ff9c
++#define ixSMU_PM_STATUS_104                                                     0x3ffa0
++#define ixSMU_PM_STATUS_105                                                     0x3ffa4
++#define ixSMU_PM_STATUS_106                                                     0x3ffa8
++#define ixSMU_PM_STATUS_107                                                     0x3ffac
++#define ixSMU_PM_STATUS_108                                                     0x3ffb0
++#define ixSMU_PM_STATUS_109                                                     0x3ffb4
++#define ixSMU_PM_STATUS_110                                                     0x3ffb8
++#define ixSMU_PM_STATUS_111                                                     0x3ffbc
++#define ixSMU_PM_STATUS_112                                                     0x3ffc0
++#define ixSMU_PM_STATUS_113                                                     0x3ffc4
++#define ixSMU_PM_STATUS_114                                                     0x3ffc8
++#define ixSMU_PM_STATUS_115                                                     0x3ffcc
++#define ixSMU_PM_STATUS_116                                                     0x3ffd0
++#define ixSMU_PM_STATUS_117                                                     0x3ffd4
++#define ixSMU_PM_STATUS_118                                                     0x3ffd8
++#define ixSMU_PM_STATUS_119                                                     0x3ffdc
++#define ixSMU_PM_STATUS_120                                                     0x3ffe0
++#define ixSMU_PM_STATUS_121                                                     0x3ffe4
++#define ixSMU_PM_STATUS_122                                                     0x3ffe8
++#define ixSMU_PM_STATUS_123                                                     0x3ffec
++#define ixSMU_PM_STATUS_124                                                     0x3fff0
++#define ixSMU_PM_STATUS_125                                                     0x3fff4
++#define ixSMU_PM_STATUS_126                                                     0x3fff8
++#define ixSMU_PM_STATUS_127                                                     0x3fffc
++#define ixCG_THERMAL_INT_ENA                                                    0xc2100024
++#define ixCG_THERMAL_INT_CTRL                                                   0xc2100028
++#define ixCG_THERMAL_INT_STATUS                                                 0xc210002c
++#define ixGENERAL_PWRMGT                                                        0xc0200000
++#define ixCNB_PWRMGT_CNTL                                                       0xc0200004
++#define ixSCLK_PWRMGT_CNTL                                                      0xc0200008
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xc0200014
++#define ixCG_FREQ_TRAN_VOTING_0                                                 0xc02001a8
++#define ixCG_FREQ_TRAN_VOTING_1                                                 0xc02001ac
++#define ixCG_FREQ_TRAN_VOTING_2                                                 0xc02001b0
++#define ixCG_FREQ_TRAN_VOTING_3                                                 0xc02001b4
++#define ixCG_FREQ_TRAN_VOTING_4                                                 0xc02001b8
++#define ixCG_FREQ_TRAN_VOTING_5                                                 0xc02001bc
++#define ixCG_FREQ_TRAN_VOTING_6                                                 0xc02001c0
++#define ixCG_FREQ_TRAN_VOTING_7                                                 0xc02001c4
++#define ixPLL_TEST_CNTL                                                         0xc020003c
++#define ixCG_STATIC_SCREEN_PARAMETER                                            0xc0200044
++#define ixCG_DISPLAY_GAP_CNTL                                                   0xc0200060
++#define ixCG_DISPLAY_GAP_CNTL2                                                  0xc0200230
++#define ixCG_ACPI_CNTL                                                          0xc0200064
++#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xc0200080
++#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xc0200084
++#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xc020009c
++#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xc0200088
++#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xc020008c
++#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xc0200310
++#define ixSMU_VOLTAGE_STATUS                                                    0xc0200094
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xc02000f0
++#define ixCG_ULV_PARAMETER                                                      0xc020015c
++#define ixSCLK_MIN_DIV                                                          0xc0200308
++#define ixLCAC_SX0_CNTL                                                         0xc0400d00
++#define ixLCAC_SX0_OVR_SEL                                                      0xc0400d04
++#define ixLCAC_SX0_OVR_VAL                                                      0xc0400d08
++#define ixLCAC_MC0_CNTL                                                         0xc0400d30
++#define ixLCAC_MC0_OVR_SEL                                                      0xc0400d34
++#define ixLCAC_MC0_OVR_VAL                                                      0xc0400d38
++#define ixLCAC_MC1_CNTL                                                         0xc0400d3c
++#define ixLCAC_MC1_OVR_SEL                                                      0xc0400d40
++#define ixLCAC_MC1_OVR_VAL                                                      0xc0400d44
++#define ixLCAC_MC2_CNTL                                                         0xc0400d48
++#define ixLCAC_MC2_OVR_SEL                                                      0xc0400d4c
++#define ixLCAC_MC2_OVR_VAL                                                      0xc0400d50
++#define ixLCAC_MC3_CNTL                                                         0xc0400d54
++#define ixLCAC_MC3_OVR_SEL                                                      0xc0400d58
++#define ixLCAC_MC3_OVR_VAL                                                      0xc0400d5c
++#define ixLCAC_CPL_CNTL                                                         0xc0400d80
++#define ixLCAC_CPL_OVR_SEL                                                      0xc0400d84
++#define ixLCAC_CPL_OVR_VAL                                                      0xc0400d88
++
++#endif /* SMU_7_0_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h
+new file mode 100644
+index 0000000..54e0e4c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h
+@@ -0,0 +1,3842 @@
++/*
++ * SMU_7_0_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_0_0_SH_MASK_H
++#define SMU_7_0_0_SH_MASK_H
++
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
++#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
++#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
++#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
++#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
++#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
++#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
++#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON_MASK 0x2000
++#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON__SHIFT 0xd
++#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK 0x3c000
++#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT 0xe
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x1fc0000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x12
++#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS_MASK 0xe000000
++#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN_MASK 0x200
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fc00
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0xa
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN_MASK 0x400
++#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT 0xa
++#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800
++#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
++#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
++#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
++#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
++#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
++#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
++#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
++#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
++#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
++#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
++#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
++#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
++#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
++#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
++#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
++#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
++#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
++#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
++#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
++#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
++#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
++#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_0__SMC_RESP_MASK 0xffff
++#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_1__SMC_RESP_MASK 0xffff
++#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_2__SMC_RESP_MASK 0xffff
++#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_3__SMC_RESP_MASK 0xffff
++#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_4__SMC_RESP_MASK 0xffff
++#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_5__SMC_RESP_MASK 0xffff
++#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_6__SMC_RESP_MASK 0xffff
++#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_7__SMC_RESP_MASK 0xffff
++#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_8__SMC_RESP_MASK 0xffff
++#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_9__SMC_RESP_MASK 0xffff
++#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_10__SMC_RESP_MASK 0xffff
++#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_11__SMC_RESP_MASK 0xffff
++#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
++#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
++#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
++#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
++#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
++#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
++#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
++#define SMC_PC_C__smc_pc_c__SHIFT 0x0
++#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
++#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
++#define CG_FPS_CNT__FPS_CNT_MASK 0xff
++#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
++#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
++#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
++#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
++#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
++#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
++#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
++#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
++#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
++#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
++#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
++#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
++#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
++#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
++#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
++#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
++#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
++#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
++#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
++#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
++#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
++#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
++#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
++#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
++#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
++#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
++#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
++#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
++#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
++#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
++#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
++#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
++#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
++#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
++#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
++#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
++#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
++#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
++#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
++#define CC_RCU_FUSES__RCU_SPARE_MASK 0x7e000000
++#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
++#define CC_RCU_FUSES__PSP_ENABLE_MASK 0x80000000
++#define CC_RCU_FUSES__PSP_ENABLE__SHIFT 0x1f
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
++#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
++#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
++#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
++#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
++#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
++#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
++#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
++#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
++#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
++#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
++#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
++#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
++#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
++#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
++#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
++#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
++#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3fffe
++#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
++#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
++#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
++#define SMU_STATUS__SMU_DONE_MASK 0x1
++#define SMU_STATUS__SMU_DONE__SHIFT 0x0
++#define SMU_STATUS__SMU_PASS_MASK 0x2
++#define SMU_STATUS__SMU_PASS__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
++#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
++#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
++#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
++#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
++#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
++#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
++#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
++#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
++#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
++#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
++#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
++#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
++#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
++#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
++#define DPM_TABLE_1__SystemFlags_MASK 0xffffffff
++#define DPM_TABLE_1__SystemFlags__SHIFT 0x0
++#define DPM_TABLE_2__GraphicsPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_2__GraphicsPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_5__GraphicsPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_5__GraphicsPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_6__GraphicsPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_6__GraphicsPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_7__GraphicsPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_7__GraphicsPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_8__GraphicsPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_8__GraphicsPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_10__GraphicsPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_10__GraphicsPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_11__GioPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_11__GioPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_14__GioPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_14__GioPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_15__GioPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_15__GioPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_16__GioPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_16__GioPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_17__GioPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_17__GioPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_18__GioPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_18__GioPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_19__GioPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_19__GioPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_20__VceLevelCount_MASK 0xff
++#define DPM_TABLE_20__VceLevelCount__SHIFT 0x0
++#define DPM_TABLE_20__UvdLevelCount_MASK 0xff00
++#define DPM_TABLE_20__UvdLevelCount__SHIFT 0x8
++#define DPM_TABLE_20__GIOLevelCount_MASK 0xff0000
++#define DPM_TABLE_20__GIOLevelCount__SHIFT 0x10
++#define DPM_TABLE_20__GraphicsDpmLevelCount_MASK 0xff000000
++#define DPM_TABLE_20__GraphicsDpmLevelCount__SHIFT 0x18
++#define DPM_TABLE_21__FpsHighThreshold_MASK 0xffff
++#define DPM_TABLE_21__FpsHighThreshold__SHIFT 0x0
++#define DPM_TABLE_21__SamuLevelCount_MASK 0xff0000
++#define DPM_TABLE_21__SamuLevelCount__SHIFT 0x10
++#define DPM_TABLE_21__AcpLevelCount_MASK 0xff000000
++#define DPM_TABLE_21__AcpLevelCount__SHIFT 0x18
++#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_24__GraphicsLevel_0_VidOffset_MASK 0xff0000
++#define DPM_TABLE_24__GraphicsLevel_0_VidOffset__SHIFT 0x10
++#define DPM_TABLE_24__GraphicsLevel_0_Vid_MASK 0xff000000
++#define DPM_TABLE_24__GraphicsLevel_0_Vid__SHIFT 0x18
++#define DPM_TABLE_25__GraphicsLevel_0_SclkDid_MASK 0xff
++#define DPM_TABLE_25__GraphicsLevel_0_SclkDid__SHIFT 0x0
++#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_26__GraphicsLevel_0_UpHyst_MASK 0xff
++#define DPM_TABLE_26__GraphicsLevel_0_UpHyst__SHIFT 0x0
++#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_27__GraphicsLevel_0_DownHyst_MASK 0xff000000
++#define DPM_TABLE_27__GraphicsLevel_0_DownHyst__SHIFT 0x18
++#define DPM_TABLE_28__GraphicsLevel_0_reserved_MASK 0xffffffff
++#define DPM_TABLE_28__GraphicsLevel_0_reserved__SHIFT 0x0
++#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_31__GraphicsLevel_1_VidOffset_MASK 0xff0000
++#define DPM_TABLE_31__GraphicsLevel_1_VidOffset__SHIFT 0x10
++#define DPM_TABLE_31__GraphicsLevel_1_Vid_MASK 0xff000000
++#define DPM_TABLE_31__GraphicsLevel_1_Vid__SHIFT 0x18
++#define DPM_TABLE_32__GraphicsLevel_1_SclkDid_MASK 0xff
++#define DPM_TABLE_32__GraphicsLevel_1_SclkDid__SHIFT 0x0
++#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_33__GraphicsLevel_1_UpHyst_MASK 0xff
++#define DPM_TABLE_33__GraphicsLevel_1_UpHyst__SHIFT 0x0
++#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_34__GraphicsLevel_1_DownHyst_MASK 0xff000000
++#define DPM_TABLE_34__GraphicsLevel_1_DownHyst__SHIFT 0x18
++#define DPM_TABLE_35__GraphicsLevel_1_reserved_MASK 0xffffffff
++#define DPM_TABLE_35__GraphicsLevel_1_reserved__SHIFT 0x0
++#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_38__GraphicsLevel_2_VidOffset_MASK 0xff0000
++#define DPM_TABLE_38__GraphicsLevel_2_VidOffset__SHIFT 0x10
++#define DPM_TABLE_38__GraphicsLevel_2_Vid_MASK 0xff000000
++#define DPM_TABLE_38__GraphicsLevel_2_Vid__SHIFT 0x18
++#define DPM_TABLE_39__GraphicsLevel_2_SclkDid_MASK 0xff
++#define DPM_TABLE_39__GraphicsLevel_2_SclkDid__SHIFT 0x0
++#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_40__GraphicsLevel_2_UpHyst_MASK 0xff
++#define DPM_TABLE_40__GraphicsLevel_2_UpHyst__SHIFT 0x0
++#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_41__GraphicsLevel_2_DownHyst_MASK 0xff000000
++#define DPM_TABLE_41__GraphicsLevel_2_DownHyst__SHIFT 0x18
++#define DPM_TABLE_42__GraphicsLevel_2_reserved_MASK 0xffffffff
++#define DPM_TABLE_42__GraphicsLevel_2_reserved__SHIFT 0x0
++#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_45__GraphicsLevel_3_VidOffset_MASK 0xff0000
++#define DPM_TABLE_45__GraphicsLevel_3_VidOffset__SHIFT 0x10
++#define DPM_TABLE_45__GraphicsLevel_3_Vid_MASK 0xff000000
++#define DPM_TABLE_45__GraphicsLevel_3_Vid__SHIFT 0x18
++#define DPM_TABLE_46__GraphicsLevel_3_SclkDid_MASK 0xff
++#define DPM_TABLE_46__GraphicsLevel_3_SclkDid__SHIFT 0x0
++#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_47__GraphicsLevel_3_UpHyst_MASK 0xff
++#define DPM_TABLE_47__GraphicsLevel_3_UpHyst__SHIFT 0x0
++#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_48__GraphicsLevel_3_DownHyst_MASK 0xff000000
++#define DPM_TABLE_48__GraphicsLevel_3_DownHyst__SHIFT 0x18
++#define DPM_TABLE_49__GraphicsLevel_3_reserved_MASK 0xffffffff
++#define DPM_TABLE_49__GraphicsLevel_3_reserved__SHIFT 0x0
++#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_52__GraphicsLevel_4_VidOffset_MASK 0xff0000
++#define DPM_TABLE_52__GraphicsLevel_4_VidOffset__SHIFT 0x10
++#define DPM_TABLE_52__GraphicsLevel_4_Vid_MASK 0xff000000
++#define DPM_TABLE_52__GraphicsLevel_4_Vid__SHIFT 0x18
++#define DPM_TABLE_53__GraphicsLevel_4_SclkDid_MASK 0xff
++#define DPM_TABLE_53__GraphicsLevel_4_SclkDid__SHIFT 0x0
++#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_54__GraphicsLevel_4_UpHyst_MASK 0xff
++#define DPM_TABLE_54__GraphicsLevel_4_UpHyst__SHIFT 0x0
++#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_55__GraphicsLevel_4_DownHyst_MASK 0xff000000
++#define DPM_TABLE_55__GraphicsLevel_4_DownHyst__SHIFT 0x18
++#define DPM_TABLE_56__GraphicsLevel_4_reserved_MASK 0xffffffff
++#define DPM_TABLE_56__GraphicsLevel_4_reserved__SHIFT 0x0
++#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_59__GraphicsLevel_5_VidOffset_MASK 0xff0000
++#define DPM_TABLE_59__GraphicsLevel_5_VidOffset__SHIFT 0x10
++#define DPM_TABLE_59__GraphicsLevel_5_Vid_MASK 0xff000000
++#define DPM_TABLE_59__GraphicsLevel_5_Vid__SHIFT 0x18
++#define DPM_TABLE_60__GraphicsLevel_5_SclkDid_MASK 0xff
++#define DPM_TABLE_60__GraphicsLevel_5_SclkDid__SHIFT 0x0
++#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_61__GraphicsLevel_5_UpHyst_MASK 0xff
++#define DPM_TABLE_61__GraphicsLevel_5_UpHyst__SHIFT 0x0
++#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_62__GraphicsLevel_5_DownHyst_MASK 0xff000000
++#define DPM_TABLE_62__GraphicsLevel_5_DownHyst__SHIFT 0x18
++#define DPM_TABLE_63__GraphicsLevel_5_reserved_MASK 0xffffffff
++#define DPM_TABLE_63__GraphicsLevel_5_reserved__SHIFT 0x0
++#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_66__GraphicsLevel_6_VidOffset_MASK 0xff0000
++#define DPM_TABLE_66__GraphicsLevel_6_VidOffset__SHIFT 0x10
++#define DPM_TABLE_66__GraphicsLevel_6_Vid_MASK 0xff000000
++#define DPM_TABLE_66__GraphicsLevel_6_Vid__SHIFT 0x18
++#define DPM_TABLE_67__GraphicsLevel_6_SclkDid_MASK 0xff
++#define DPM_TABLE_67__GraphicsLevel_6_SclkDid__SHIFT 0x0
++#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_68__GraphicsLevel_6_UpHyst_MASK 0xff
++#define DPM_TABLE_68__GraphicsLevel_6_UpHyst__SHIFT 0x0
++#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_69__GraphicsLevel_6_DownHyst_MASK 0xff000000
++#define DPM_TABLE_69__GraphicsLevel_6_DownHyst__SHIFT 0x18
++#define DPM_TABLE_70__GraphicsLevel_6_reserved_MASK 0xffffffff
++#define DPM_TABLE_70__GraphicsLevel_6_reserved__SHIFT 0x0
++#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_73__GraphicsLevel_7_VidOffset_MASK 0xff0000
++#define DPM_TABLE_73__GraphicsLevel_7_VidOffset__SHIFT 0x10
++#define DPM_TABLE_73__GraphicsLevel_7_Vid_MASK 0xff000000
++#define DPM_TABLE_73__GraphicsLevel_7_Vid__SHIFT 0x18
++#define DPM_TABLE_74__GraphicsLevel_7_SclkDid_MASK 0xff
++#define DPM_TABLE_74__GraphicsLevel_7_SclkDid__SHIFT 0x0
++#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle_MASK 0xff000000
++#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle__SHIFT 0x18
++#define DPM_TABLE_75__GraphicsLevel_7_UpHyst_MASK 0xff
++#define DPM_TABLE_75__GraphicsLevel_7_UpHyst__SHIFT 0x0
++#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity_MASK 0xff0000
++#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity__SHIFT 0x10
++#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark_MASK 0xff000000
++#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark__SHIFT 0x18
++#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst_MASK 0xff0000
++#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x10
++#define DPM_TABLE_76__GraphicsLevel_7_DownHyst_MASK 0xff000000
++#define DPM_TABLE_76__GraphicsLevel_7_DownHyst__SHIFT 0x18
++#define DPM_TABLE_77__GraphicsLevel_7_reserved_MASK 0xffffffff
++#define DPM_TABLE_77__GraphicsLevel_7_reserved__SHIFT 0x0
++#define DPM_TABLE_78__ACPILevel_Flags_MASK 0xffffffff
++#define DPM_TABLE_78__ACPILevel_Flags__SHIFT 0x0
++#define DPM_TABLE_79__ACPILevel_MinVddNb_MASK 0xffffffff
++#define DPM_TABLE_79__ACPILevel_MinVddNb__SHIFT 0x0
++#define DPM_TABLE_80__ACPILevel_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_80__ACPILevel_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_81__ACPILevel_DisplayWatermark_MASK 0xff
++#define DPM_TABLE_81__ACPILevel_DisplayWatermark__SHIFT 0x0
++#define DPM_TABLE_81__ACPILevel_ForceNbPs1_MASK 0xff00
++#define DPM_TABLE_81__ACPILevel_ForceNbPs1__SHIFT 0x8
++#define DPM_TABLE_81__ACPILevel_GnbSlow_MASK 0xff0000
++#define DPM_TABLE_81__ACPILevel_GnbSlow__SHIFT 0x10
++#define DPM_TABLE_81__ACPILevel_SclkDid_MASK 0xff000000
++#define DPM_TABLE_81__ACPILevel_SclkDid__SHIFT 0x18
++#define DPM_TABLE_82__ACPILevel_padding_2_MASK 0xff
++#define DPM_TABLE_82__ACPILevel_padding_2__SHIFT 0x0
++#define DPM_TABLE_82__ACPILevel_padding_1_MASK 0xff00
++#define DPM_TABLE_82__ACPILevel_padding_1__SHIFT 0x8
++#define DPM_TABLE_82__ACPILevel_padding_0_MASK 0xff0000
++#define DPM_TABLE_82__ACPILevel_padding_0__SHIFT 0x10
++#define DPM_TABLE_82__ACPILevel_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_82__ACPILevel_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_83__UvdLevel_0_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_83__UvdLevel_0_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_84__UvdLevel_0_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_84__UvdLevel_0_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_85__UvdLevel_0_DclkDivider_MASK 0xff
++#define DPM_TABLE_85__UvdLevel_0_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_85__UvdLevel_0_VclkDivider_MASK 0xff00
++#define DPM_TABLE_85__UvdLevel_0_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_85__UvdLevel_0_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_85__UvdLevel_0_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_86__UvdLevel_0_padding_1_MASK 0xff
++#define DPM_TABLE_86__UvdLevel_0_padding_1__SHIFT 0x0
++#define DPM_TABLE_86__UvdLevel_0_padding_0_MASK 0xff00
++#define DPM_TABLE_86__UvdLevel_0_padding_0__SHIFT 0x8
++#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_87__UvdLevel_1_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_87__UvdLevel_1_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_88__UvdLevel_1_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_88__UvdLevel_1_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_89__UvdLevel_1_DclkDivider_MASK 0xff
++#define DPM_TABLE_89__UvdLevel_1_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_89__UvdLevel_1_VclkDivider_MASK 0xff00
++#define DPM_TABLE_89__UvdLevel_1_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_89__UvdLevel_1_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_89__UvdLevel_1_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_90__UvdLevel_1_padding_1_MASK 0xff
++#define DPM_TABLE_90__UvdLevel_1_padding_1__SHIFT 0x0
++#define DPM_TABLE_90__UvdLevel_1_padding_0_MASK 0xff00
++#define DPM_TABLE_90__UvdLevel_1_padding_0__SHIFT 0x8
++#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_91__UvdLevel_2_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_91__UvdLevel_2_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_92__UvdLevel_2_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_92__UvdLevel_2_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_93__UvdLevel_2_DclkDivider_MASK 0xff
++#define DPM_TABLE_93__UvdLevel_2_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_93__UvdLevel_2_VclkDivider_MASK 0xff00
++#define DPM_TABLE_93__UvdLevel_2_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_93__UvdLevel_2_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_93__UvdLevel_2_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_94__UvdLevel_2_padding_1_MASK 0xff
++#define DPM_TABLE_94__UvdLevel_2_padding_1__SHIFT 0x0
++#define DPM_TABLE_94__UvdLevel_2_padding_0_MASK 0xff00
++#define DPM_TABLE_94__UvdLevel_2_padding_0__SHIFT 0x8
++#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_95__UvdLevel_3_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_95__UvdLevel_3_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_96__UvdLevel_3_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_96__UvdLevel_3_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_97__UvdLevel_3_DclkDivider_MASK 0xff
++#define DPM_TABLE_97__UvdLevel_3_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_97__UvdLevel_3_VclkDivider_MASK 0xff00
++#define DPM_TABLE_97__UvdLevel_3_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_97__UvdLevel_3_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_97__UvdLevel_3_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_98__UvdLevel_3_padding_1_MASK 0xff
++#define DPM_TABLE_98__UvdLevel_3_padding_1__SHIFT 0x0
++#define DPM_TABLE_98__UvdLevel_3_padding_0_MASK 0xff00
++#define DPM_TABLE_98__UvdLevel_3_padding_0__SHIFT 0x8
++#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_99__UvdLevel_4_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_99__UvdLevel_4_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_100__UvdLevel_4_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_100__UvdLevel_4_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_101__UvdLevel_4_DclkDivider_MASK 0xff
++#define DPM_TABLE_101__UvdLevel_4_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_101__UvdLevel_4_VclkDivider_MASK 0xff00
++#define DPM_TABLE_101__UvdLevel_4_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_101__UvdLevel_4_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_101__UvdLevel_4_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_102__UvdLevel_4_padding_1_MASK 0xff
++#define DPM_TABLE_102__UvdLevel_4_padding_1__SHIFT 0x0
++#define DPM_TABLE_102__UvdLevel_4_padding_0_MASK 0xff00
++#define DPM_TABLE_102__UvdLevel_4_padding_0__SHIFT 0x8
++#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_103__UvdLevel_5_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_103__UvdLevel_5_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_104__UvdLevel_5_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_104__UvdLevel_5_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_105__UvdLevel_5_DclkDivider_MASK 0xff
++#define DPM_TABLE_105__UvdLevel_5_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_105__UvdLevel_5_VclkDivider_MASK 0xff00
++#define DPM_TABLE_105__UvdLevel_5_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_105__UvdLevel_5_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_105__UvdLevel_5_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_106__UvdLevel_5_padding_1_MASK 0xff
++#define DPM_TABLE_106__UvdLevel_5_padding_1__SHIFT 0x0
++#define DPM_TABLE_106__UvdLevel_5_padding_0_MASK 0xff00
++#define DPM_TABLE_106__UvdLevel_5_padding_0__SHIFT 0x8
++#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_107__UvdLevel_6_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_107__UvdLevel_6_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_108__UvdLevel_6_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_108__UvdLevel_6_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_109__UvdLevel_6_DclkDivider_MASK 0xff
++#define DPM_TABLE_109__UvdLevel_6_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_109__UvdLevel_6_VclkDivider_MASK 0xff00
++#define DPM_TABLE_109__UvdLevel_6_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_109__UvdLevel_6_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_109__UvdLevel_6_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_110__UvdLevel_6_padding_1_MASK 0xff
++#define DPM_TABLE_110__UvdLevel_6_padding_1__SHIFT 0x0
++#define DPM_TABLE_110__UvdLevel_6_padding_0_MASK 0xff00
++#define DPM_TABLE_110__UvdLevel_6_padding_0__SHIFT 0x8
++#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_111__UvdLevel_7_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_111__UvdLevel_7_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_112__UvdLevel_7_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_112__UvdLevel_7_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_113__UvdLevel_7_DclkDivider_MASK 0xff
++#define DPM_TABLE_113__UvdLevel_7_DclkDivider__SHIFT 0x0
++#define DPM_TABLE_113__UvdLevel_7_VclkDivider_MASK 0xff00
++#define DPM_TABLE_113__UvdLevel_7_VclkDivider__SHIFT 0x8
++#define DPM_TABLE_113__UvdLevel_7_MinVddNb_MASK 0xffff0000
++#define DPM_TABLE_113__UvdLevel_7_MinVddNb__SHIFT 0x10
++#define DPM_TABLE_114__UvdLevel_7_padding_1_MASK 0xff
++#define DPM_TABLE_114__UvdLevel_7_padding_1__SHIFT 0x0
++#define DPM_TABLE_114__UvdLevel_7_padding_0_MASK 0xff00
++#define DPM_TABLE_114__UvdLevel_7_padding_0__SHIFT 0x8
++#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl_MASK 0xff0000
++#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl__SHIFT 0x10
++#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl_MASK 0xff000000
++#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl__SHIFT 0x18
++#define DPM_TABLE_115__VceLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_115__VceLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_116__VceLevel_0_Divider_MASK 0xff00
++#define DPM_TABLE_116__VceLevel_0_Divider__SHIFT 0x8
++#define DPM_TABLE_116__VceLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_116__VceLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_117__VceLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_117__VceLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_118__VceLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_118__VceLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_119__VceLevel_1_Divider_MASK 0xff00
++#define DPM_TABLE_119__VceLevel_1_Divider__SHIFT 0x8
++#define DPM_TABLE_119__VceLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_119__VceLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_120__VceLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_120__VceLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_121__VceLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_121__VceLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_122__VceLevel_2_Divider_MASK 0xff00
++#define DPM_TABLE_122__VceLevel_2_Divider__SHIFT 0x8
++#define DPM_TABLE_122__VceLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_122__VceLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_123__VceLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_123__VceLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_124__VceLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_124__VceLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_125__VceLevel_3_Divider_MASK 0xff00
++#define DPM_TABLE_125__VceLevel_3_Divider__SHIFT 0x8
++#define DPM_TABLE_125__VceLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_125__VceLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_126__VceLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_126__VceLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_127__VceLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_127__VceLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_128__VceLevel_4_Divider_MASK 0xff00
++#define DPM_TABLE_128__VceLevel_4_Divider__SHIFT 0x8
++#define DPM_TABLE_128__VceLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_128__VceLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_129__VceLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_129__VceLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_130__VceLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_130__VceLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_131__VceLevel_5_Divider_MASK 0xff00
++#define DPM_TABLE_131__VceLevel_5_Divider__SHIFT 0x8
++#define DPM_TABLE_131__VceLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_131__VceLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_132__VceLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_132__VceLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_133__VceLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_133__VceLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_134__VceLevel_6_Divider_MASK 0xff00
++#define DPM_TABLE_134__VceLevel_6_Divider__SHIFT 0x8
++#define DPM_TABLE_134__VceLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_134__VceLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_135__VceLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_135__VceLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_136__VceLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_136__VceLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_137__VceLevel_7_Divider_MASK 0xff00
++#define DPM_TABLE_137__VceLevel_7_Divider__SHIFT 0x8
++#define DPM_TABLE_137__VceLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_137__VceLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_138__VceLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_138__VceLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_139__AcpLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_139__AcpLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_140__AcpLevel_0_Divider_MASK 0xff00
++#define DPM_TABLE_140__AcpLevel_0_Divider__SHIFT 0x8
++#define DPM_TABLE_140__AcpLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_140__AcpLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_141__AcpLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_141__AcpLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_142__AcpLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_142__AcpLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_143__AcpLevel_1_Divider_MASK 0xff00
++#define DPM_TABLE_143__AcpLevel_1_Divider__SHIFT 0x8
++#define DPM_TABLE_143__AcpLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_143__AcpLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_144__AcpLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_144__AcpLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_145__AcpLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_145__AcpLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_146__AcpLevel_2_Divider_MASK 0xff00
++#define DPM_TABLE_146__AcpLevel_2_Divider__SHIFT 0x8
++#define DPM_TABLE_146__AcpLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_146__AcpLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_147__AcpLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_147__AcpLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_148__AcpLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_148__AcpLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_149__AcpLevel_3_Divider_MASK 0xff00
++#define DPM_TABLE_149__AcpLevel_3_Divider__SHIFT 0x8
++#define DPM_TABLE_149__AcpLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_149__AcpLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_150__AcpLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_150__AcpLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_151__AcpLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_151__AcpLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_152__AcpLevel_4_Divider_MASK 0xff00
++#define DPM_TABLE_152__AcpLevel_4_Divider__SHIFT 0x8
++#define DPM_TABLE_152__AcpLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_152__AcpLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_153__AcpLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_153__AcpLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_154__AcpLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_154__AcpLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_155__AcpLevel_5_Divider_MASK 0xff00
++#define DPM_TABLE_155__AcpLevel_5_Divider__SHIFT 0x8
++#define DPM_TABLE_155__AcpLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_155__AcpLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_156__AcpLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_156__AcpLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_157__AcpLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_157__AcpLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_158__AcpLevel_6_Divider_MASK 0xff00
++#define DPM_TABLE_158__AcpLevel_6_Divider__SHIFT 0x8
++#define DPM_TABLE_158__AcpLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_158__AcpLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_159__AcpLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_159__AcpLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_160__AcpLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_160__AcpLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_161__AcpLevel_7_Divider_MASK 0xff00
++#define DPM_TABLE_161__AcpLevel_7_Divider__SHIFT 0x8
++#define DPM_TABLE_161__AcpLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_161__AcpLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_162__AcpLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_162__AcpLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_163__SamuLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_163__SamuLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_164__SamuLevel_0_Divider_MASK 0xff00
++#define DPM_TABLE_164__SamuLevel_0_Divider__SHIFT 0x8
++#define DPM_TABLE_164__SamuLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_164__SamuLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_165__SamuLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_165__SamuLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_166__SamuLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_166__SamuLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_167__SamuLevel_1_Divider_MASK 0xff00
++#define DPM_TABLE_167__SamuLevel_1_Divider__SHIFT 0x8
++#define DPM_TABLE_167__SamuLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_167__SamuLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_168__SamuLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_168__SamuLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_169__SamuLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_169__SamuLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_170__SamuLevel_2_Divider_MASK 0xff00
++#define DPM_TABLE_170__SamuLevel_2_Divider__SHIFT 0x8
++#define DPM_TABLE_170__SamuLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_170__SamuLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_171__SamuLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_171__SamuLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_172__SamuLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_172__SamuLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_173__SamuLevel_3_Divider_MASK 0xff00
++#define DPM_TABLE_173__SamuLevel_3_Divider__SHIFT 0x8
++#define DPM_TABLE_173__SamuLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_173__SamuLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_174__SamuLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_174__SamuLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_175__SamuLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_175__SamuLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_176__SamuLevel_4_Divider_MASK 0xff00
++#define DPM_TABLE_176__SamuLevel_4_Divider__SHIFT 0x8
++#define DPM_TABLE_176__SamuLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_176__SamuLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_177__SamuLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_177__SamuLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_178__SamuLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_178__SamuLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_179__SamuLevel_5_Divider_MASK 0xff00
++#define DPM_TABLE_179__SamuLevel_5_Divider__SHIFT 0x8
++#define DPM_TABLE_179__SamuLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_179__SamuLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_180__SamuLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_180__SamuLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_181__SamuLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_181__SamuLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_182__SamuLevel_6_Divider_MASK 0xff00
++#define DPM_TABLE_182__SamuLevel_6_Divider__SHIFT 0x8
++#define DPM_TABLE_182__SamuLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_182__SamuLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_183__SamuLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_183__SamuLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_184__SamuLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_184__SamuLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl_MASK 0xff
++#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl__SHIFT 0x0
++#define DPM_TABLE_185__SamuLevel_7_Divider_MASK 0xff00
++#define DPM_TABLE_185__SamuLevel_7_Divider__SHIFT 0x8
++#define DPM_TABLE_185__SamuLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_185__SamuLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_186__SamuLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_186__SamuLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_187__SamuBootLevel_MASK 0xff
++#define DPM_TABLE_187__SamuBootLevel__SHIFT 0x0
++#define DPM_TABLE_187__AcpBootLevel_MASK 0xff00
++#define DPM_TABLE_187__AcpBootLevel__SHIFT 0x8
++#define DPM_TABLE_187__VceBootLevel_MASK 0xff0000
++#define DPM_TABLE_187__VceBootLevel__SHIFT 0x10
++#define DPM_TABLE_187__UvdBootLevel_MASK 0xff000000
++#define DPM_TABLE_187__UvdBootLevel__SHIFT 0x18
++#define DPM_TABLE_188__SAMUInterval_MASK 0xff
++#define DPM_TABLE_188__SAMUInterval__SHIFT 0x0
++#define DPM_TABLE_188__ACPInterval_MASK 0xff00
++#define DPM_TABLE_188__ACPInterval__SHIFT 0x8
++#define DPM_TABLE_188__VCEInterval_MASK 0xff0000
++#define DPM_TABLE_188__VCEInterval__SHIFT 0x10
++#define DPM_TABLE_188__UVDInterval_MASK 0xff000000
++#define DPM_TABLE_188__UVDInterval__SHIFT 0x18
++#define DPM_TABLE_189__GraphicsVoltageChangeEnable_MASK 0xff
++#define DPM_TABLE_189__GraphicsVoltageChangeEnable__SHIFT 0x0
++#define DPM_TABLE_189__GraphicsThermThrottleEnable_MASK 0xff00
++#define DPM_TABLE_189__GraphicsThermThrottleEnable__SHIFT 0x8
++#define DPM_TABLE_189__GraphicsInterval_MASK 0xff0000
++#define DPM_TABLE_189__GraphicsInterval__SHIFT 0x10
++#define DPM_TABLE_189__GraphicsBootLevel_MASK 0xff000000
++#define DPM_TABLE_189__GraphicsBootLevel__SHIFT 0x18
++#define DPM_TABLE_190__FpsLowThreshold_MASK 0xffff
++#define DPM_TABLE_190__FpsLowThreshold__SHIFT 0x0
++#define DPM_TABLE_190__GraphicsClkSlowDivider_MASK 0xff0000
++#define DPM_TABLE_190__GraphicsClkSlowDivider__SHIFT 0x10
++#define DPM_TABLE_190__GraphicsClkSlowEnable_MASK 0xff000000
++#define DPM_TABLE_190__GraphicsClkSlowEnable__SHIFT 0x18
++#define DPM_TABLE_191__DisplayCac_MASK 0xffffffff
++#define DPM_TABLE_191__DisplayCac__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_4__HandshakeDisables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_4__HandshakeDisables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_9__AverageGioActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_9__AverageGioActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_12__Reserved_0_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_12__Reserved_0__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_13__Reserved_1_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_13__Reserved_1__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__Reserved_2_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_14__Reserved_2__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_15__Reserved_3_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_15__Reserved_3__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_16__Reserved_4_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_16__Reserved_4__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_17__Reserved_5_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_17__Reserved_5__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_18__Reserved_6_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_18__Reserved_6__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__Reserved_7_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_19__Reserved_7__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_20__Reserved_8_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_20__Reserved_8__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_21__Reserved_9_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_21__Reserved_9__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
++#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
++#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
++#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
++#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
++#define GIO_PID_CONTROLLER_CNTL_0__K_I_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_0__K_I__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION__SHIFT 0x0
++#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT_MASK 0xffffffff
++#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT__SHIFT 0x0
++#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT_MASK 0xffffffff
++#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT__SHIFT 0x0
++#define SMU_LCLK_DPM_CNTL__RESERVED_MASK 0xff
++#define SMU_LCLK_DPM_CNTL__RESERVED__SHIFT 0x0
++#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE_MASK 0xff00
++#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE__SHIFT 0x8
++#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN_MASK 0xff0000
++#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN__SHIFT 0x10
++#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN_MASK 0xff000000
++#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN__SHIFT 0x18
++#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE_MASK 0xff
++#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE__SHIFT 0x0
++#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE_MASK 0xff00
++#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE__SHIFT 0x8
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN_MASK 0xff
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN__SHIFT 0x0
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL_MASK 0xff00
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL__SHIFT 0x8
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE_MASK 0xff0000
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE__SHIFT 0x10
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE_MASK 0xff000000
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE__SHIFT 0x18
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD_MASK 0xffff
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD__SHIFT 0x0
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD_MASK 0xffff0000
++#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD__SHIFT 0x10
++#define PM_FUSES_1__BapmPstateVid_3_MASK 0xff
++#define PM_FUSES_1__BapmPstateVid_3__SHIFT 0x0
++#define PM_FUSES_1__BapmPstateVid_2_MASK 0xff00
++#define PM_FUSES_1__BapmPstateVid_2__SHIFT 0x8
++#define PM_FUSES_1__BapmPstateVid_1_MASK 0xff0000
++#define PM_FUSES_1__BapmPstateVid_1__SHIFT 0x10
++#define PM_FUSES_1__BapmPstateVid_0_MASK 0xff000000
++#define PM_FUSES_1__BapmPstateVid_0__SHIFT 0x18
++#define PM_FUSES_2__BapmPstateVid_7_MASK 0xff
++#define PM_FUSES_2__BapmPstateVid_7__SHIFT 0x0
++#define PM_FUSES_2__BapmPstateVid_6_MASK 0xff00
++#define PM_FUSES_2__BapmPstateVid_6__SHIFT 0x8
++#define PM_FUSES_2__BapmPstateVid_5_MASK 0xff0000
++#define PM_FUSES_2__BapmPstateVid_5__SHIFT 0x10
++#define PM_FUSES_2__BapmPstateVid_4_MASK 0xff000000
++#define PM_FUSES_2__BapmPstateVid_4__SHIFT 0x18
++#define PM_FUSES_3__BapmVddNbVidHiSidd_3_MASK 0xff
++#define PM_FUSES_3__BapmVddNbVidHiSidd_3__SHIFT 0x0
++#define PM_FUSES_3__BapmVddNbVidHiSidd_2_MASK 0xff00
++#define PM_FUSES_3__BapmVddNbVidHiSidd_2__SHIFT 0x8
++#define PM_FUSES_3__BapmVddNbVidHiSidd_1_MASK 0xff0000
++#define PM_FUSES_3__BapmVddNbVidHiSidd_1__SHIFT 0x10
++#define PM_FUSES_3__BapmVddNbVidHiSidd_0_MASK 0xff000000
++#define PM_FUSES_3__BapmVddNbVidHiSidd_0__SHIFT 0x18
++#define PM_FUSES_4__BapmVddNbVidLoSidd_2_MASK 0xff
++#define PM_FUSES_4__BapmVddNbVidLoSidd_2__SHIFT 0x0
++#define PM_FUSES_4__BapmVddNbVidLoSidd_1_MASK 0xff00
++#define PM_FUSES_4__BapmVddNbVidLoSidd_1__SHIFT 0x8
++#define PM_FUSES_4__BapmVddNbVidLoSidd_0_MASK 0xff0000
++#define PM_FUSES_4__BapmVddNbVidLoSidd_0__SHIFT 0x10
++#define PM_FUSES_4__BapmVddNbVidHiSidd_4_MASK 0xff000000
++#define PM_FUSES_4__BapmVddNbVidHiSidd_4__SHIFT 0x18
++#define PM_FUSES_5__CpuIdModel_MASK 0xff
++#define PM_FUSES_5__CpuIdModel__SHIFT 0x0
++#define PM_FUSES_5__SviLoadLineEn_MASK 0xff00
++#define PM_FUSES_5__SviLoadLineEn__SHIFT 0x8
++#define PM_FUSES_5__BapmVddNbVidLoSidd_4_MASK 0xff0000
++#define PM_FUSES_5__BapmVddNbVidLoSidd_4__SHIFT 0x10
++#define PM_FUSES_5__BapmVddNbVidLoSidd_3_MASK 0xff000000
++#define PM_FUSES_5__BapmVddNbVidLoSidd_3__SHIFT 0x18
++#define PM_FUSES_6__SviLoadLineTrimVddNb_MASK 0xff
++#define PM_FUSES_6__SviLoadLineTrimVddNb__SHIFT 0x0
++#define PM_FUSES_6__SviLoadLineTrimVdd_MASK 0xff00
++#define PM_FUSES_6__SviLoadLineTrimVdd__SHIFT 0x8
++#define PM_FUSES_6__SviLoadLineVddNb_MASK 0xff0000
++#define PM_FUSES_6__SviLoadLineVddNb__SHIFT 0x10
++#define PM_FUSES_6__SviLoadLineVdd_MASK 0xff000000
++#define PM_FUSES_6__SviLoadLineVdd__SHIFT 0x18
++#define PM_FUSES_7__BAPMTI_TjOffset_0_MASK 0xffff
++#define PM_FUSES_7__BAPMTI_TjOffset_0__SHIFT 0x0
++#define PM_FUSES_7__SviLoadLineOffsetVddNb_MASK 0xff0000
++#define PM_FUSES_7__SviLoadLineOffsetVddNb__SHIFT 0x10
++#define PM_FUSES_7__SviLoadLineOffsetVdd_MASK 0xff000000
++#define PM_FUSES_7__SviLoadLineOffsetVdd__SHIFT 0x18
++#define PM_FUSES_8__BAPMTI_TjOffset_2_MASK 0xffff
++#define PM_FUSES_8__BAPMTI_TjOffset_2__SHIFT 0x0
++#define PM_FUSES_8__BAPMTI_TjOffset_1_MASK 0xffff0000
++#define PM_FUSES_8__BAPMTI_TjOffset_1__SHIFT 0x10
++#define PM_FUSES_9__BAPMTI_TjHyst_1_MASK 0xffff
++#define PM_FUSES_9__BAPMTI_TjHyst_1__SHIFT 0x0
++#define PM_FUSES_9__BAPMTI_TjHyst_0_MASK 0xffff0000
++#define PM_FUSES_9__BAPMTI_TjHyst_0__SHIFT 0x10
++#define PM_FUSES_10__BAPMTI_TjMax_1_MASK 0xff
++#define PM_FUSES_10__BAPMTI_TjMax_1__SHIFT 0x0
++#define PM_FUSES_10__BAPMTI_TjMax_0_MASK 0xff00
++#define PM_FUSES_10__BAPMTI_TjMax_0__SHIFT 0x8
++#define PM_FUSES_10__BAPMTI_GpuTjHyst_MASK 0xffff0000
++#define PM_FUSES_10__BAPMTI_GpuTjHyst__SHIFT 0x10
++#define PM_FUSES_11__LhtcTmpLmt_MASK 0xff
++#define PM_FUSES_11__LhtcTmpLmt__SHIFT 0x0
++#define PM_FUSES_11__LhtcPstateLimit_MASK 0xff00
++#define PM_FUSES_11__LhtcPstateLimit__SHIFT 0x8
++#define PM_FUSES_11__LhtcHystLmt_MASK 0xff0000
++#define PM_FUSES_11__LhtcHystLmt__SHIFT 0x10
++#define PM_FUSES_11__BAPMTI_GpuTjMax_MASK 0xff000000
++#define PM_FUSES_11__BAPMTI_GpuTjMax__SHIFT 0x18
++#define PM_FUSES_12__MaxPwrCpu_1_MASK 0xff
++#define PM_FUSES_12__MaxPwrCpu_1__SHIFT 0x0
++#define PM_FUSES_12__MaxPwrCpu_0_MASK 0xff00
++#define PM_FUSES_12__MaxPwrCpu_0__SHIFT 0x8
++#define PM_FUSES_12__NomPwrCpu_1_MASK 0xff0000
++#define PM_FUSES_12__NomPwrCpu_1__SHIFT 0x10
++#define PM_FUSES_12__NomPwrCpu_0_MASK 0xff000000
++#define PM_FUSES_12__NomPwrCpu_0__SHIFT 0x18
++#define PM_FUSES_13__NomPwrGpu_MASK 0xffff
++#define PM_FUSES_13__NomPwrGpu__SHIFT 0x0
++#define PM_FUSES_13__MidPwrCpu_1_MASK 0xff0000
++#define PM_FUSES_13__MidPwrCpu_1__SHIFT 0x10
++#define PM_FUSES_13__MidPwrCpu_0_MASK 0xff000000
++#define PM_FUSES_13__MidPwrCpu_0__SHIFT 0x18
++#define PM_FUSES_14__MinPwrGpu_MASK 0xffff
++#define PM_FUSES_14__MinPwrGpu__SHIFT 0x0
++#define PM_FUSES_14__MaxPwrGpu_MASK 0xffff0000
++#define PM_FUSES_14__MaxPwrGpu__SHIFT 0x10
++#define PM_FUSES_15__PCIe3PhyOffset_MASK 0xff
++#define PM_FUSES_15__PCIe3PhyOffset__SHIFT 0x0
++#define PM_FUSES_15__PCIe2PhyOffset_MASK 0xff00
++#define PM_FUSES_15__PCIe2PhyOffset__SHIFT 0x8
++#define PM_FUSES_15__PCIe1PhyOffset_MASK 0xff0000
++#define PM_FUSES_15__PCIe1PhyOffset__SHIFT 0x10
++#define PM_FUSES_15__MidPwrTempHyst_MASK 0xff000000
++#define PM_FUSES_15__MidPwrTempHyst__SHIFT 0x18
++#define PM_FUSES_16__TDC_VDD_PkgLimit_MASK 0xffff
++#define PM_FUSES_16__TDC_VDD_PkgLimit__SHIFT 0x0
++#define PM_FUSES_16__DCE2PhyOffset_MASK 0xff0000
++#define PM_FUSES_16__DCE2PhyOffset__SHIFT 0x10
++#define PM_FUSES_16__DCE1PhyOffset_MASK 0xff000000
++#define PM_FUSES_16__DCE1PhyOffset__SHIFT 0x18
++#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc_MASK 0xff
++#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc__SHIFT 0x0
++#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc_MASK 0xff00
++#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc__SHIFT 0x8
++#define PM_FUSES_17__TDC_VDDNB_PkgLimit_MASK 0xffff0000
++#define PM_FUSES_17__TDC_VDDNB_PkgLimit__SHIFT 0x10
++#define PM_FUSES_18__TdcWaterfallCtl_MASK 0xff
++#define PM_FUSES_18__TdcWaterfallCtl__SHIFT 0x0
++#define PM_FUSES_18__TdpAgeRate_MASK 0xff00
++#define PM_FUSES_18__TdpAgeRate__SHIFT 0x8
++#define PM_FUSES_18__TdpAgeValue_MASK 0xff0000
++#define PM_FUSES_18__TdpAgeValue__SHIFT 0x10
++#define PM_FUSES_18__TDC_MAWt_MASK 0xff000000
++#define PM_FUSES_18__TDC_MAWt__SHIFT 0x18
++#define PM_FUSES_19__BapmLhtcCap_MASK 0xff
++#define PM_FUSES_19__BapmLhtcCap__SHIFT 0x0
++#define PM_FUSES_19__BapmFuseOverride_MASK 0xff00
++#define PM_FUSES_19__BapmFuseOverride__SHIFT 0x8
++#define PM_FUSES_19__SmuCoolingIndex_MASK 0xff0000
++#define PM_FUSES_19__SmuCoolingIndex__SHIFT 0x10
++#define PM_FUSES_19__SmuSocIndex_MASK 0xff000000
++#define PM_FUSES_19__SmuSocIndex__SHIFT 0x18
++#define PM_FUSES_20__SamClkDid_3_MASK 0xff
++#define PM_FUSES_20__SamClkDid_3__SHIFT 0x0
++#define PM_FUSES_20__SamClkDid_2_MASK 0xff00
++#define PM_FUSES_20__SamClkDid_2__SHIFT 0x8
++#define PM_FUSES_20__SamClkDid_1_MASK 0xff0000
++#define PM_FUSES_20__SamClkDid_1__SHIFT 0x10
++#define PM_FUSES_20__SamClkDid_0_MASK 0xff000000
++#define PM_FUSES_20__SamClkDid_0__SHIFT 0x18
++#define PM_FUSES_21__AmbientTempBase_MASK 0xff
++#define PM_FUSES_21__AmbientTempBase__SHIFT 0x0
++#define PM_FUSES_21__LPMLTemperatureMax_MASK 0xff00
++#define PM_FUSES_21__LPMLTemperatureMax__SHIFT 0x8
++#define PM_FUSES_21__LPMLTemperatureMin_MASK 0xff0000
++#define PM_FUSES_21__LPMLTemperatureMin__SHIFT 0x10
++#define PM_FUSES_21__SamClkDid_4_MASK 0xff000000
++#define PM_FUSES_21__SamClkDid_4__SHIFT 0x18
++#define PM_FUSES_22__LPMLTemperatureScaler_3_MASK 0xff
++#define PM_FUSES_22__LPMLTemperatureScaler_3__SHIFT 0x0
++#define PM_FUSES_22__LPMLTemperatureScaler_2_MASK 0xff00
++#define PM_FUSES_22__LPMLTemperatureScaler_2__SHIFT 0x8
++#define PM_FUSES_22__LPMLTemperatureScaler_1_MASK 0xff0000
++#define PM_FUSES_22__LPMLTemperatureScaler_1__SHIFT 0x10
++#define PM_FUSES_22__LPMLTemperatureScaler_0_MASK 0xff000000
++#define PM_FUSES_22__LPMLTemperatureScaler_0__SHIFT 0x18
++#define PM_FUSES_23__LPMLTemperatureScaler_7_MASK 0xff
++#define PM_FUSES_23__LPMLTemperatureScaler_7__SHIFT 0x0
++#define PM_FUSES_23__LPMLTemperatureScaler_6_MASK 0xff00
++#define PM_FUSES_23__LPMLTemperatureScaler_6__SHIFT 0x8
++#define PM_FUSES_23__LPMLTemperatureScaler_5_MASK 0xff0000
++#define PM_FUSES_23__LPMLTemperatureScaler_5__SHIFT 0x10
++#define PM_FUSES_23__LPMLTemperatureScaler_4_MASK 0xff000000
++#define PM_FUSES_23__LPMLTemperatureScaler_4__SHIFT 0x18
++#define PM_FUSES_24__LPMLTemperatureScaler_11_MASK 0xff
++#define PM_FUSES_24__LPMLTemperatureScaler_11__SHIFT 0x0
++#define PM_FUSES_24__LPMLTemperatureScaler_10_MASK 0xff00
++#define PM_FUSES_24__LPMLTemperatureScaler_10__SHIFT 0x8
++#define PM_FUSES_24__LPMLTemperatureScaler_9_MASK 0xff0000
++#define PM_FUSES_24__LPMLTemperatureScaler_9__SHIFT 0x10
++#define PM_FUSES_24__LPMLTemperatureScaler_8_MASK 0xff000000
++#define PM_FUSES_24__LPMLTemperatureScaler_8__SHIFT 0x18
++#define PM_FUSES_25__LPMLTemperatureScaler_15_MASK 0xff
++#define PM_FUSES_25__LPMLTemperatureScaler_15__SHIFT 0x0
++#define PM_FUSES_25__LPMLTemperatureScaler_14_MASK 0xff00
++#define PM_FUSES_25__LPMLTemperatureScaler_14__SHIFT 0x8
++#define PM_FUSES_25__LPMLTemperatureScaler_13_MASK 0xff0000
++#define PM_FUSES_25__LPMLTemperatureScaler_13__SHIFT 0x10
++#define PM_FUSES_25__LPMLTemperatureScaler_12_MASK 0xff000000
++#define PM_FUSES_25__LPMLTemperatureScaler_12__SHIFT 0x18
++#define PM_FUSES_26__GnbLPML_3_MASK 0xff
++#define PM_FUSES_26__GnbLPML_3__SHIFT 0x0
++#define PM_FUSES_26__GnbLPML_2_MASK 0xff00
++#define PM_FUSES_26__GnbLPML_2__SHIFT 0x8
++#define PM_FUSES_26__GnbLPML_1_MASK 0xff0000
++#define PM_FUSES_26__GnbLPML_1__SHIFT 0x10
++#define PM_FUSES_26__GnbLPML_0_MASK 0xff000000
++#define PM_FUSES_26__GnbLPML_0__SHIFT 0x18
++#define PM_FUSES_27__GnbLPML_7_MASK 0xff
++#define PM_FUSES_27__GnbLPML_7__SHIFT 0x0
++#define PM_FUSES_27__GnbLPML_6_MASK 0xff00
++#define PM_FUSES_27__GnbLPML_6__SHIFT 0x8
++#define PM_FUSES_27__GnbLPML_5_MASK 0xff0000
++#define PM_FUSES_27__GnbLPML_5__SHIFT 0x10
++#define PM_FUSES_27__GnbLPML_4_MASK 0xff000000
++#define PM_FUSES_27__GnbLPML_4__SHIFT 0x18
++#define PM_FUSES_28__GnbLPML_11_MASK 0xff
++#define PM_FUSES_28__GnbLPML_11__SHIFT 0x0
++#define PM_FUSES_28__GnbLPML_10_MASK 0xff00
++#define PM_FUSES_28__GnbLPML_10__SHIFT 0x8
++#define PM_FUSES_28__GnbLPML_9_MASK 0xff0000
++#define PM_FUSES_28__GnbLPML_9__SHIFT 0x10
++#define PM_FUSES_28__GnbLPML_8_MASK 0xff000000
++#define PM_FUSES_28__GnbLPML_8__SHIFT 0x18
++#define PM_FUSES_29__GnbLPML_15_MASK 0xff
++#define PM_FUSES_29__GnbLPML_15__SHIFT 0x0
++#define PM_FUSES_29__GnbLPML_14_MASK 0xff00
++#define PM_FUSES_29__GnbLPML_14__SHIFT 0x8
++#define PM_FUSES_29__GnbLPML_13_MASK 0xff0000
++#define PM_FUSES_29__GnbLPML_13__SHIFT 0x10
++#define PM_FUSES_29__GnbLPML_12_MASK 0xff000000
++#define PM_FUSES_29__GnbLPML_12__SHIFT 0x18
++#define PM_FUSES_30__NbVid_3_MASK 0xff
++#define PM_FUSES_30__NbVid_3__SHIFT 0x0
++#define PM_FUSES_30__NbVid_2_MASK 0xff00
++#define PM_FUSES_30__NbVid_2__SHIFT 0x8
++#define PM_FUSES_30__NbVid_1_MASK 0xff0000
++#define PM_FUSES_30__NbVid_1__SHIFT 0x10
++#define PM_FUSES_30__NbVid_0_MASK 0xff000000
++#define PM_FUSES_30__NbVid_0__SHIFT 0x18
++#define PM_FUSES_31__CpuVid_3_MASK 0xff
++#define PM_FUSES_31__CpuVid_3__SHIFT 0x0
++#define PM_FUSES_31__CpuVid_2_MASK 0xff00
++#define PM_FUSES_31__CpuVid_2__SHIFT 0x8
++#define PM_FUSES_31__CpuVid_1_MASK 0xff0000
++#define PM_FUSES_31__CpuVid_1__SHIFT 0x10
++#define PM_FUSES_31__CpuVid_0_MASK 0xff000000
++#define PM_FUSES_31__CpuVid_0__SHIFT 0x18
++#define PM_FUSES_32__CpuVid_7_MASK 0xff
++#define PM_FUSES_32__CpuVid_7__SHIFT 0x0
++#define PM_FUSES_32__CpuVid_6_MASK 0xff00
++#define PM_FUSES_32__CpuVid_6__SHIFT 0x8
++#define PM_FUSES_32__CpuVid_5_MASK 0xff0000
++#define PM_FUSES_32__CpuVid_5__SHIFT 0x10
++#define PM_FUSES_32__CpuVid_4_MASK 0xff000000
++#define PM_FUSES_32__CpuVid_4__SHIFT 0x18
++#define PM_FUSES_33__Tdp2Watt_MASK 0xffff
++#define PM_FUSES_33__Tdp2Watt__SHIFT 0x0
++#define PM_FUSES_33__GnbLPMLMinVid_MASK 0xff0000
++#define PM_FUSES_33__GnbLPMLMinVid__SHIFT 0x10
++#define PM_FUSES_33__GnbLPMLMaxVid_MASK 0xff000000
++#define PM_FUSES_33__GnbLPMLMaxVid__SHIFT 0x18
++#define PM_FUSES_34__Lpml_3_MASK 0xff
++#define PM_FUSES_34__Lpml_3__SHIFT 0x0
++#define PM_FUSES_34__Lpml_2_MASK 0xff00
++#define PM_FUSES_34__Lpml_2__SHIFT 0x8
++#define PM_FUSES_34__Lpml_1_MASK 0xff0000
++#define PM_FUSES_34__Lpml_1__SHIFT 0x10
++#define PM_FUSES_34__Lpml_0_MASK 0xff000000
++#define PM_FUSES_34__Lpml_0__SHIFT 0x18
++#define PM_FUSES_35__Lpml_7_MASK 0xff
++#define PM_FUSES_35__Lpml_7__SHIFT 0x0
++#define PM_FUSES_35__Lpml_6_MASK 0xff00
++#define PM_FUSES_35__Lpml_6__SHIFT 0x8
++#define PM_FUSES_35__Lpml_5_MASK 0xff0000
++#define PM_FUSES_35__Lpml_5__SHIFT 0x10
++#define PM_FUSES_35__Lpml_4_MASK 0xff000000
++#define PM_FUSES_35__Lpml_4__SHIFT 0x18
++#define PM_FUSES_36__Lpmv_3_MASK 0xff
++#define PM_FUSES_36__Lpmv_3__SHIFT 0x0
++#define PM_FUSES_36__Lpmv_2_MASK 0xff00
++#define PM_FUSES_36__Lpmv_2__SHIFT 0x8
++#define PM_FUSES_36__Lpmv_1_MASK 0xff0000
++#define PM_FUSES_36__Lpmv_1__SHIFT 0x10
++#define PM_FUSES_36__Lpmv_0_MASK 0xff000000
++#define PM_FUSES_36__Lpmv_0__SHIFT 0x18
++#define PM_FUSES_37__Lpmv_7_MASK 0xff
++#define PM_FUSES_37__Lpmv_7__SHIFT 0x0
++#define PM_FUSES_37__Lpmv_6_MASK 0xff00
++#define PM_FUSES_37__Lpmv_6__SHIFT 0x8
++#define PM_FUSES_37__Lpmv_5_MASK 0xff0000
++#define PM_FUSES_37__Lpmv_5__SHIFT 0x10
++#define PM_FUSES_37__Lpmv_4_MASK 0xff000000
++#define PM_FUSES_37__Lpmv_4__SHIFT 0x18
++#define PM_FUSES_38__EClkDid_3_MASK 0xff
++#define PM_FUSES_38__EClkDid_3__SHIFT 0x0
++#define PM_FUSES_38__EClkDid_2_MASK 0xff00
++#define PM_FUSES_38__EClkDid_2__SHIFT 0x8
++#define PM_FUSES_38__EClkDid_1_MASK 0xff0000
++#define PM_FUSES_38__EClkDid_1__SHIFT 0x10
++#define PM_FUSES_38__EClkDid_0_MASK 0xff000000
++#define PM_FUSES_38__EClkDid_0__SHIFT 0x18
++#define PM_FUSES_39__CoreDis_MASK 0xff
++#define PM_FUSES_39__CoreDis__SHIFT 0x0
++#define PM_FUSES_39__C6CstatePower_MASK 0xff00
++#define PM_FUSES_39__C6CstatePower__SHIFT 0x8
++#define PM_FUSES_39__BoostLock_MASK 0xff0000
++#define PM_FUSES_39__BoostLock__SHIFT 0x10
++#define PM_FUSES_39__EClkDid_4_MASK 0xff000000
++#define PM_FUSES_39__EClkDid_4__SHIFT 0x18
++#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd_MASK 0xffff
++#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd__SHIFT 0x0
++#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd_MASK 0xffff0000
++#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd__SHIFT 0x10
++#define PM_FUSES_41__VddNbVid_3_MASK 0xff
++#define PM_FUSES_41__VddNbVid_3__SHIFT 0x0
++#define PM_FUSES_41__VddNbVid_2_MASK 0xff00
++#define PM_FUSES_41__VddNbVid_2__SHIFT 0x8
++#define PM_FUSES_41__VddNbVid_1_MASK 0xff0000
++#define PM_FUSES_41__VddNbVid_1__SHIFT 0x10
++#define PM_FUSES_41__VddNbVid_0_MASK 0xff000000
++#define PM_FUSES_41__VddNbVid_0__SHIFT 0x18
++#define PM_FUSES_42__VddNbVidOffset_2_MASK 0xff
++#define PM_FUSES_42__VddNbVidOffset_2__SHIFT 0x0
++#define PM_FUSES_42__VddNbVidOffset_1_MASK 0xff00
++#define PM_FUSES_42__VddNbVidOffset_1__SHIFT 0x8
++#define PM_FUSES_42__VddNbVidOffset_0_MASK 0xff0000
++#define PM_FUSES_42__VddNbVidOffset_0__SHIFT 0x10
++#define PM_FUSES_42__VddNbVid_4_MASK 0xff000000
++#define PM_FUSES_42__VddNbVid_4__SHIFT 0x18
++#define PM_FUSES_43__BapmDisable_MASK 0xff
++#define PM_FUSES_43__BapmDisable__SHIFT 0x0
++#define PM_FUSES_43__CoreTdpLimit0_MASK 0xff00
++#define PM_FUSES_43__CoreTdpLimit0__SHIFT 0x8
++#define PM_FUSES_43__VddNbVidOffset_4_MASK 0xff0000
++#define PM_FUSES_43__VddNbVidOffset_4__SHIFT 0x10
++#define PM_FUSES_43__VddNbVidOffset_3_MASK 0xff000000
++#define PM_FUSES_43__VddNbVidOffset_3__SHIFT 0x18
++#define PM_FUSES_44__LpmlL2_3_MASK 0xff
++#define PM_FUSES_44__LpmlL2_3__SHIFT 0x0
++#define PM_FUSES_44__LpmlL2_2_MASK 0xff00
++#define PM_FUSES_44__LpmlL2_2__SHIFT 0x8
++#define PM_FUSES_44__LpmlL2_1_MASK 0xff0000
++#define PM_FUSES_44__LpmlL2_1__SHIFT 0x10
++#define PM_FUSES_44__LpmlL2_0_MASK 0xff000000
++#define PM_FUSES_44__LpmlL2_0__SHIFT 0x18
++#define PM_FUSES_45__LpmlL2_7_MASK 0xff
++#define PM_FUSES_45__LpmlL2_7__SHIFT 0x0
++#define PM_FUSES_45__LpmlL2_6_MASK 0xff00
++#define PM_FUSES_45__LpmlL2_6__SHIFT 0x8
++#define PM_FUSES_45__LpmlL2_5_MASK 0xff0000
++#define PM_FUSES_45__LpmlL2_5__SHIFT 0x10
++#define PM_FUSES_45__LpmlL2_4_MASK 0xff000000
++#define PM_FUSES_45__LpmlL2_4__SHIFT 0x18
++#define PM_FUSES_46__CoolPdmTc_MASK 0xff
++#define PM_FUSES_46__CoolPdmTc__SHIFT 0x0
++#define PM_FUSES_46__BaseCpcTdpLimit2_MASK 0xff00
++#define PM_FUSES_46__BaseCpcTdpLimit2__SHIFT 0x8
++#define PM_FUSES_46__BaseCpcTdpLimit1_MASK 0xff0000
++#define PM_FUSES_46__BaseCpcTdpLimit1__SHIFT 0x10
++#define PM_FUSES_46__BaseCpcTdpLimit_MASK 0xff000000
++#define PM_FUSES_46__BaseCpcTdpLimit__SHIFT 0x18
++#define PM_FUSES_47__CoolPdmThr2_MASK 0xff
++#define PM_FUSES_47__CoolPdmThr2__SHIFT 0x0
++#define PM_FUSES_47__CoolPdmThr1_MASK 0xff00
++#define PM_FUSES_47__CoolPdmThr1__SHIFT 0x8
++#define PM_FUSES_47__GpuPdmTc_MASK 0xff0000
++#define PM_FUSES_47__GpuPdmTc__SHIFT 0x10
++#define PM_FUSES_47__HeatPdmTc_MASK 0xff000000
++#define PM_FUSES_47__HeatPdmTc__SHIFT 0x18
++#define PM_FUSES_48__PkgPwr_MAWt_MASK 0xff
++#define PM_FUSES_48__PkgPwr_MAWt__SHIFT 0x0
++#define PM_FUSES_48__GpuActThr_MASK 0xff00
++#define PM_FUSES_48__GpuActThr__SHIFT 0x8
++#define PM_FUSES_48__HeatPdmThr2_MASK 0xff0000
++#define PM_FUSES_48__HeatPdmThr2__SHIFT 0x10
++#define PM_FUSES_48__HeatPdmThr1_MASK 0xff000000
++#define PM_FUSES_48__HeatPdmThr1__SHIFT 0x18
++#define PM_FUSES_49__SocketTdp_MASK 0xffff
++#define PM_FUSES_49__SocketTdp__SHIFT 0x0
++#define PM_FUSES_49__GpuPdmMult_MASK 0xffff0000
++#define PM_FUSES_49__GpuPdmMult__SHIFT 0x10
++#define PM_FUSES_50__Reserved2_MASK 0xffff
++#define PM_FUSES_50__Reserved2__SHIFT 0x0
++#define PM_FUSES_50__Reserved1_MASK 0xff0000
++#define PM_FUSES_50__Reserved1__SHIFT 0x10
++#define PM_FUSES_50__NumBoostStates_MASK 0xff000000
++#define PM_FUSES_50__NumBoostStates__SHIFT 0x18
++#define PM_FUSES_51__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_51__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_52__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_52__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_53__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_53__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_54__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_54__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_55__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_55__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_56__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_56__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_57__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_57__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_58__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_58__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_59__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_59__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_60__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_60__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_61__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_61__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_62__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_62__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_63__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_63__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_64__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_64__FUSE_DATA__SHIFT 0x0
++#define PM_FUSES_65__FUSE_DATA_MASK 0xffffffff
++#define PM_FUSES_65__FUSE_DATA__SHIFT 0x0
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
++#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
++#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
++#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
++#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
++#define TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
++#define TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
++#define TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
++#define TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
++#define TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
++#define TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
++#define CURRENT_GNB_TEMP__TEMP_MASK 0x7ff
++#define CURRENT_GNB_TEMP__TEMP__SHIFT 0x0
++#define CURRENT_GLOBAL_TEMP__TEMP_MASK 0x7ff
++#define CURRENT_GLOBAL_TEMP__TEMP__SHIFT 0x0
++#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
++#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
++#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
++#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
++#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
++#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
++#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
++#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
++#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
++#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
++#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
++#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
++#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
++#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
++#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
++#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
++#define FEATURE_STATUS__BAPM_ON_MASK 0x100
++#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
++#define FEATURE_STATUS__LPMX_ON_MASK 0x200
++#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
++#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
++#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
++#define FEATURE_STATUS__LHTC_ON_MASK 0x800
++#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
++#define FEATURE_STATUS__VPC_ON_MASK 0x1000
++#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
++#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
++#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
++#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
++#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
++#define FEATURE_STATUS__AVS_ON_MASK 0x10000
++#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
++#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
++#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
++#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
++#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
++#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
++#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
++#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
++#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
++#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
++#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
++#define FEATURE_STATUS__CLK_MON_ON_MASK 0x400000
++#define FEATURE_STATUS__CLK_MON_ON__SHIFT 0x16
++#define FEATURE_STATUS__RESERVED_MASK 0xff800000
++#define FEATURE_STATUS__RESERVED__SHIFT 0x17
++#define PCIE_PLL_RECONF__RECONF_WAIT_MASK 0xff
++#define PCIE_PLL_RECONF__RECONF_WAIT__SHIFT 0x0
++#define PCIE_PLL_RECONF__RECONF_WRAPPER_MASK 0xff00
++#define PCIE_PLL_RECONF__RECONF_WRAPPER__SHIFT 0x8
++#define PCIE_PLL_RECONF__SB_RELOCATE_EN_MASK 0xff0000
++#define PCIE_PLL_RECONF__SB_RELOCATE_EN__SHIFT 0x10
++#define PCIE_PLL_RECONF__SB_NEW_PORT_MASK 0xff000000
++#define PCIE_PLL_RECONF__SB_NEW_PORT__SHIFT 0x18
++#define PM_INTERVAL_CNTL_0__LCLK_DPM_MASK 0xff
++#define PM_INTERVAL_CNTL_0__LCLK_DPM__SHIFT 0x0
++#define PM_INTERVAL_CNTL_0__THERMAL_CNTL_MASK 0xff00
++#define PM_INTERVAL_CNTL_0__THERMAL_CNTL__SHIFT 0x8
++#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL_MASK 0xff0000
++#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL__SHIFT 0x10
++#define PM_INTERVAL_CNTL_0__LOADLINE_MASK 0xff000000
++#define PM_INTERVAL_CNTL_0__LOADLINE__SHIFT 0x18
++#define PM_INTERVAL_CNTL_1__NB_DPM_MASK 0xff
++#define PM_INTERVAL_CNTL_1__NB_DPM__SHIFT 0x0
++#define PM_INTERVAL_CNTL_1__AVS_PERIOD_MASK 0xff00
++#define PM_INTERVAL_CNTL_1__AVS_PERIOD__SHIFT 0x8
++#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD_MASK 0xff0000
++#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD__SHIFT 0x10
++#define PM_INTERVAL_CNTL_1__TDP_CNTL_MASK 0xff000000
++#define PM_INTERVAL_CNTL_1__TDP_CNTL__SHIFT 0x18
++#define PM_INTERVAL_CNTL_2__BAPM_PERIOD_MASK 0xff
++#define PM_INTERVAL_CNTL_2__BAPM_PERIOD__SHIFT 0x0
++#define PM_INTERVAL_CNTL_2__HTC_PERIOD_MASK 0xff00
++#define PM_INTERVAL_CNTL_2__HTC_PERIOD__SHIFT 0x8
++#define PM_INTERVAL_CNTL_2__TDC_PERIOD_MASK 0xff0000
++#define PM_INTERVAL_CNTL_2__TDC_PERIOD__SHIFT 0x10
++#define PM_INTERVAL_CNTL_2__LPMX_PERIOD_MASK 0xff000000
++#define PM_INTERVAL_CNTL_2__LPMX_PERIOD__SHIFT 0x18
++#define VPC_INTERVAL_CNTL__VPC_PERIOD_MASK 0xffffffff
++#define VPC_INTERVAL_CNTL__VPC_PERIOD__SHIFT 0x0
++#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit_MASK 0xffffffff
++#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit__SHIFT 0x0
++#define FCH_PWR_CREDIT__FchPwrCredit_MASK 0xffffffff
++#define FCH_PWR_CREDIT__FchPwrCredit__SHIFT 0x0
++#define PKGPWR_MV_AVG__Avg_Pkg_Pwr_MASK 0xffffffff
++#define PKGPWR_MV_AVG__Avg_Pkg_Pwr__SHIFT 0x0
++#define PACKAGE_POWER__Pkg_power_MASK 0xffffffff
++#define PACKAGE_POWER__Pkg_power__SHIFT 0x0
++#define PKG_PWR_CNTL__CpcGpuPerfPri_MASK 0x1
++#define PKG_PWR_CNTL__CpcGpuPerfPri__SHIFT 0x0
++#define PKG_PWR_CNTL__PkgPwrLimit_MASK 0x1fffe
++#define PKG_PWR_CNTL__PkgPwrLimit__SHIFT 0x1
++#define PKG_PWR_CNTL__FchPwrCreditScale_MASK 0x7e0000
++#define PKG_PWR_CNTL__FchPwrCreditScale__SHIFT 0x11
++#define PKG_PWR_CNTL__PkgHystCoeff_MASK 0x1f800000
++#define PKG_PWR_CNTL__PkgHystCoeff__SHIFT 0x17
++#define PKG_PWR_CNTL__RESERVED_MASK 0xe0000000
++#define PKG_PWR_CNTL__RESERVED__SHIFT 0x1d
++#define PKG_PWR_STATUS__GnbMinLimitSetFlag_MASK 0x1
++#define PKG_PWR_STATUS__GnbMinLimitSetFlag__SHIFT 0x0
++#define PKG_PWR_STATUS__PstateLimitSetFlag_MASK 0x2
++#define PKG_PWR_STATUS__PstateLimitSetFlag__SHIFT 0x1
++#define PKG_PWR_STATUS__PkgPwrLimit_base_MASK 0x3fffc
++#define PKG_PWR_STATUS__PkgPwrLimit_base__SHIFT 0x2
++#define PKG_PWR_STATUS__RESERVED_MASK 0xfc0000
++#define PKG_PWR_STATUS__RESERVED__SHIFT 0x12
++#define PKG_PWR_STATUS__PkgPwr_MAWt_MASK 0xff000000
++#define PKG_PWR_STATUS__PkgPwr_MAWt__SHIFT 0x18
++#define DISP_PHY_CONFIG__Corner_MASK 0xff
++#define DISP_PHY_CONFIG__Corner__SHIFT 0x0
++#define DISP_PHY_CONFIG__DispPHYConfig_MASK 0xff00
++#define DISP_PHY_CONFIG__DispPHYConfig__SHIFT 0x8
++#define GPU_TDP_LIMIT__Gpu_Tdp_Limit_MASK 0xffff
++#define GPU_TDP_LIMIT__Gpu_Tdp_Limit__SHIFT 0x0
++#define GPU_TDP_LIMIT__Reserved_MASK 0xffff0000
++#define GPU_TDP_LIMIT__Reserved__SHIFT 0x10
++#define EXT_API_IN_DATA_0_0__byte0_MASK 0xff
++#define EXT_API_IN_DATA_0_0__byte0__SHIFT 0x0
++#define EXT_API_IN_DATA_0_0__byte1_MASK 0xff00
++#define EXT_API_IN_DATA_0_0__byte1__SHIFT 0x8
++#define EXT_API_IN_DATA_0_0__byte2_MASK 0xff0000
++#define EXT_API_IN_DATA_0_0__byte2__SHIFT 0x10
++#define EXT_API_IN_DATA_0_0__byte3_MASK 0xff000000
++#define EXT_API_IN_DATA_0_0__byte3__SHIFT 0x18
++#define EXT_API_IN_DATA_0_1__byte0_MASK 0xff
++#define EXT_API_IN_DATA_0_1__byte0__SHIFT 0x0
++#define EXT_API_IN_DATA_0_1__byte1_MASK 0xff00
++#define EXT_API_IN_DATA_0_1__byte1__SHIFT 0x8
++#define EXT_API_IN_DATA_0_1__byte2_MASK 0xff0000
++#define EXT_API_IN_DATA_0_1__byte2__SHIFT 0x10
++#define EXT_API_IN_DATA_0_1__byte3_MASK 0xff000000
++#define EXT_API_IN_DATA_0_1__byte3__SHIFT 0x18
++#define EXT_API_IN_DATA_0_2__byte0_MASK 0xff
++#define EXT_API_IN_DATA_0_2__byte0__SHIFT 0x0
++#define EXT_API_IN_DATA_0_2__byte1_MASK 0xff00
++#define EXT_API_IN_DATA_0_2__byte1__SHIFT 0x8
++#define EXT_API_IN_DATA_0_2__byte2_MASK 0xff0000
++#define EXT_API_IN_DATA_0_2__byte2__SHIFT 0x10
++#define EXT_API_IN_DATA_0_2__byte3_MASK 0xff000000
++#define EXT_API_IN_DATA_0_2__byte3__SHIFT 0x18
++#define EXT_API_IN_DATA_0_3__byte0_MASK 0xff
++#define EXT_API_IN_DATA_0_3__byte0__SHIFT 0x0
++#define EXT_API_IN_DATA_0_3__byte1_MASK 0xff00
++#define EXT_API_IN_DATA_0_3__byte1__SHIFT 0x8
++#define EXT_API_IN_DATA_0_3__byte2_MASK 0xff0000
++#define EXT_API_IN_DATA_0_3__byte2__SHIFT 0x10
++#define EXT_API_IN_DATA_0_3__byte3_MASK 0xff000000
++#define EXT_API_IN_DATA_0_3__byte3__SHIFT 0x18
++#define EXT_API_OUT_DATA_0_0__byte0_MASK 0xff
++#define EXT_API_OUT_DATA_0_0__byte0__SHIFT 0x0
++#define EXT_API_OUT_DATA_0_0__byte1_MASK 0xff00
++#define EXT_API_OUT_DATA_0_0__byte1__SHIFT 0x8
++#define EXT_API_OUT_DATA_0_0__byte2_MASK 0xff0000
++#define EXT_API_OUT_DATA_0_0__byte2__SHIFT 0x10
++#define EXT_API_OUT_DATA_0_0__byte3_MASK 0xff000000
++#define EXT_API_OUT_DATA_0_0__byte3__SHIFT 0x18
++#define EXT_API_OUT_DATA_0_1__byte0_MASK 0xff
++#define EXT_API_OUT_DATA_0_1__byte0__SHIFT 0x0
++#define EXT_API_OUT_DATA_0_1__byte1_MASK 0xff00
++#define EXT_API_OUT_DATA_0_1__byte1__SHIFT 0x8
++#define EXT_API_OUT_DATA_0_1__byte2_MASK 0xff0000
++#define EXT_API_OUT_DATA_0_1__byte2__SHIFT 0x10
++#define EXT_API_OUT_DATA_0_1__byte3_MASK 0xff000000
++#define EXT_API_OUT_DATA_0_1__byte3__SHIFT 0x18
++#define EXT_API_OUT_DATA_0_2__byte0_MASK 0xff
++#define EXT_API_OUT_DATA_0_2__byte0__SHIFT 0x0
++#define EXT_API_OUT_DATA_0_2__byte1_MASK 0xff00
++#define EXT_API_OUT_DATA_0_2__byte1__SHIFT 0x8
++#define EXT_API_OUT_DATA_0_2__byte2_MASK 0xff0000
++#define EXT_API_OUT_DATA_0_2__byte2__SHIFT 0x10
++#define EXT_API_OUT_DATA_0_2__byte3_MASK 0xff000000
++#define EXT_API_OUT_DATA_0_2__byte3__SHIFT 0x18
++#define EXT_API_OUT_DATA_0_3__byte0_MASK 0xff
++#define EXT_API_OUT_DATA_0_3__byte0__SHIFT 0x0
++#define EXT_API_OUT_DATA_0_3__byte1_MASK 0xff00
++#define EXT_API_OUT_DATA_0_3__byte1__SHIFT 0x8
++#define EXT_API_OUT_DATA_0_3__byte2_MASK 0xff0000
++#define EXT_API_OUT_DATA_0_3__byte2__SHIFT 0x10
++#define EXT_API_OUT_DATA_0_3__byte3_MASK 0xff000000
++#define EXT_API_OUT_DATA_0_3__byte3__SHIFT 0x18
++#define BAPM_PARAMETERS__MaxPwrCpu_1_MASK 0xff
++#define BAPM_PARAMETERS__MaxPwrCpu_1__SHIFT 0x0
++#define BAPM_PARAMETERS__NomPwrCpu_1_MASK 0xff00
++#define BAPM_PARAMETERS__NomPwrCpu_1__SHIFT 0x8
++#define BAPM_PARAMETERS__MaxPwrCpu_0_MASK 0xff0000
++#define BAPM_PARAMETERS__MaxPwrCpu_0__SHIFT 0x10
++#define BAPM_PARAMETERS__NomPwrCpu_0_MASK 0xff000000
++#define BAPM_PARAMETERS__NomPwrCpu_0__SHIFT 0x18
++#define BAPM_PARAMETERS_2__MaxPwrGpu_MASK 0xffff
++#define BAPM_PARAMETERS_2__MaxPwrGpu__SHIFT 0x0
++#define BAPM_PARAMETERS_2__NomPwrGpu_MASK 0xffff0000
++#define BAPM_PARAMETERS_2__NomPwrGpu__SHIFT 0x10
++#define BAPM_PARAMETERS_3__TjOffset_MASK 0xff
++#define BAPM_PARAMETERS_3__TjOffset__SHIFT 0x0
++#define BAPM_PARAMETERS_3__EnergyCntNorm_MASK 0x3ff00
++#define BAPM_PARAMETERS_3__EnergyCntNorm__SHIFT 0x8
++#define BAPM_PARAMETERS_3__Reserved_MASK 0xfffc0000
++#define BAPM_PARAMETERS_3__Reserved__SHIFT 0x12
++#define BAPM_PARAMETERS_4__MinPwrGpu_MASK 0xffff
++#define BAPM_PARAMETERS_4__MinPwrGpu__SHIFT 0x0
++#define BAPM_PARAMETERS_4__MidPwrCpu_1_MASK 0xff0000
++#define BAPM_PARAMETERS_4__MidPwrCpu_1__SHIFT 0x10
++#define BAPM_PARAMETERS_4__MidPwrCpu_0_MASK 0xff000000
++#define BAPM_PARAMETERS_4__MidPwrCpu_0__SHIFT 0x18
++#define SMU_SVI_TELEMETRY__Iddspike_OCP_MASK 0xffff
++#define SMU_SVI_TELEMETRY__Iddspike_OCP__SHIFT 0x0
++#define SMU_SVI_TELEMETRY__IddNbspike_OCP_MASK 0xffff0000
++#define SMU_SVI_TELEMETRY__IddNbspike_OCP__SHIFT 0x10
++#define BAPM_STATUS__THROTTLE_MASK 0xff
++#define BAPM_STATUS__THROTTLE__SHIFT 0x0
++#define BAPM_STATUS__THROTTLE_LAST_MASK 0xff00
++#define BAPM_STATUS__THROTTLE_LAST__SHIFT 0x8
++#define BAPM_STATUS__COUNT_CORE1_MASK 0xff0000
++#define BAPM_STATUS__COUNT_CORE1__SHIFT 0x10
++#define BAPM_STATUS__COUNT_CORE0_MASK 0xff000000
++#define BAPM_STATUS__COUNT_CORE0__SHIFT 0x18
++#define SMU_HTC_STATUS__HTC_ACTIVE_MASK 0x1
++#define SMU_HTC_STATUS__HTC_ACTIVE__SHIFT 0x0
++#define SMU_HTC_STATUS__Reserved_MASK 0xfffffffe
++#define SMU_HTC_STATUS__Reserved__SHIFT 0x1
++#define SMU_VPC_STATUS__AllCpuIdleLast_MASK 0x1
++#define SMU_VPC_STATUS__AllCpuIdleLast__SHIFT 0x0
++#define SMU_VPC_STATUS__Reserved_MASK 0xfffffffe
++#define SMU_VPC_STATUS__Reserved__SHIFT 0x1
++#define ENTITY_TEMPERATURES_1__CORE0_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_1__CORE0__SHIFT 0x0
++#define ENTITY_TEMPERATURES_2__CORE1_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_2__CORE1__SHIFT 0x0
++#define ENTITY_TEMPERATURES_3__GPU_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_3__GPU__SHIFT 0x0
++#define CU_POWER__CU0_POWER_MASK 0xffff
++#define CU_POWER__CU0_POWER__SHIFT 0x0
++#define CU_POWER__CU1_POWER_MASK 0xffff0000
++#define CU_POWER__CU1_POWER__SHIFT 0x10
++#define GPU_POWER__IGPU_POWER_MASK 0xffff
++#define GPU_POWER__IGPU_POWER__SHIFT 0x0
++#define GPU_POWER__DGPU_POWER_MASK 0xffff0000
++#define GPU_POWER__DGPU_POWER__SHIFT 0x10
++#define NTE_POWER__NTE0_POWER_MASK 0xffff
++#define NTE_POWER__NTE0_POWER__SHIFT 0x0
++#define NTE_POWER__NTE1_POWER_MASK 0xffff0000
++#define NTE_POWER__NTE1_POWER__SHIFT 0x10
++#define TDC_STATUS__VDD_Boost_MASK 0xff
++#define TDC_STATUS__VDD_Boost__SHIFT 0x0
++#define TDC_STATUS__VDD_Throttle_MASK 0xff00
++#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
++#define TDC_STATUS__VDDNB_Boost_MASK 0xff0000
++#define TDC_STATUS__VDDNB_Boost__SHIFT 0x10
++#define TDC_STATUS__VDDNB_Throttle_MASK 0xff000000
++#define TDC_STATUS__VDDNB_Throttle__SHIFT 0x18
++#define TDC_MV_AVERAGE__IDD_MASK 0xffff
++#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
++#define TDC_MV_AVERAGE__IDDNB_MASK 0xffff0000
++#define TDC_MV_AVERAGE__IDDNB__SHIFT 0x10
++#define PM_CONFIG__Enable_VPC_Accumulators_MASK 0x1
++#define PM_CONFIG__Enable_VPC_Accumulators__SHIFT 0x0
++#define PM_CONFIG__Enable_BAPM_MASK 0x2
++#define PM_CONFIG__Enable_BAPM__SHIFT 0x1
++#define PM_CONFIG__Enable_TDC_Limit_MASK 0x4
++#define PM_CONFIG__Enable_TDC_Limit__SHIFT 0x2
++#define PM_CONFIG__Enable_LPMx_MASK 0x8
++#define PM_CONFIG__Enable_LPMx__SHIFT 0x3
++#define PM_CONFIG__Enable_HTC_Limit_MASK 0x10
++#define PM_CONFIG__Enable_HTC_Limit__SHIFT 0x4
++#define PM_CONFIG__Enable_NBDPM_MASK 0x20
++#define PM_CONFIG__Enable_NBDPM__SHIFT 0x5
++#define PM_CONFIG__Enable_LoadLine_MASK 0x40
++#define PM_CONFIG__Enable_LoadLine__SHIFT 0x6
++#define PM_CONFIG__Reserved_MASK 0xff80
++#define PM_CONFIG__Reserved__SHIFT 0x7
++#define PM_CONFIG__Override_VPC_Current_MASK 0x10000
++#define PM_CONFIG__Override_VPC_Current__SHIFT 0x10
++#define PM_CONFIG__Reserved1_MASK 0x60000
++#define PM_CONFIG__Reserved1__SHIFT 0x11
++#define PM_CONFIG__Override_Calc_Temp_MASK 0x80000
++#define PM_CONFIG__Override_Calc_Temp__SHIFT 0x13
++#define PM_CONFIG__Enable_Hybrid_Boost_MASK 0x100000
++#define PM_CONFIG__Enable_Hybrid_Boost__SHIFT 0x14
++#define PM_CONFIG__Reserved2_MASK 0xe00000
++#define PM_CONFIG__Reserved2__SHIFT 0x15
++#define PM_CONFIG__PSTATE_AllCpusIdle_MASK 0x7000000
++#define PM_CONFIG__PSTATE_AllCpusIdle__SHIFT 0x18
++#define PM_CONFIG__NBPSTATE_AllCpusIdle_MASK 0x8000000
++#define PM_CONFIG__NBPSTATE_AllCpusIdle__SHIFT 0x1b
++#define PM_CONFIG__Reserved3_MASK 0x10000000
++#define PM_CONFIG__Reserved3__SHIFT 0x1c
++#define PM_CONFIG__SVI_Mode_MASK 0x20000000
++#define PM_CONFIG__SVI_Mode__SHIFT 0x1d
++#define PM_CONFIG__Enable_PDM_MASK 0x40000000
++#define PM_CONFIG__Enable_PDM__SHIFT 0x1e
++#define PM_CONFIG__Enable_PKG_PWR_LIMIT_MASK 0x80000000
++#define PM_CONFIG__Enable_PKG_PWR_LIMIT__SHIFT 0x1f
++#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
++#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
++#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
++#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
++#define TE0_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
++#define TE0_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
++#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
++#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
++#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
++#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
++#define TE1_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
++#define TE1_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
++#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
++#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
++#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
++#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
++#define TE2_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
++#define TE2_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
++#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK 0xff
++#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT 0x0
++#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK 0xff00
++#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT 0x8
++#define NB_DPM_CONFIG_1__DpmXNbPsLo_MASK 0xff0000
++#define NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT 0x10
++#define NB_DPM_CONFIG_1__DpmXNbPsHi_MASK 0xff000000
++#define NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT 0x18
++#define NB_DPM_CONFIG_2__Hysteresis_MASK 0xff
++#define NB_DPM_CONFIG_2__Hysteresis__SHIFT 0x0
++#define NB_DPM_CONFIG_2__SkipPG_MASK 0xff00
++#define NB_DPM_CONFIG_2__SkipPG__SHIFT 0x8
++#define NB_DPM_CONFIG_2__SkipDPM0_MASK 0xff0000
++#define NB_DPM_CONFIG_2__SkipDPM0__SHIFT 0x10
++#define NB_DPM_CONFIG_2__EnablePSI1_MASK 0xff000000
++#define NB_DPM_CONFIG_2__EnablePSI1__SHIFT 0x18
++#define NB_DPM_CONFIG_3__RESERVED_MASK 0xffffff
++#define NB_DPM_CONFIG_3__RESERVED__SHIFT 0x0
++#define NB_DPM_CONFIG_3__EnableDpmPstatePoll_MASK 0xff000000
++#define NB_DPM_CONFIG_3__EnableDpmPstatePoll__SHIFT 0x18
++#define SMU_IDD_OVERRIDE__IDD_MASK 0xffff
++#define SMU_IDD_OVERRIDE__IDD__SHIFT 0x0
++#define SMU_IDD_OVERRIDE__IDDNB_MASK 0xffff0000
++#define SMU_IDD_OVERRIDE__IDDNB__SHIFT 0x10
++#define AVS_CONFIG__AvsEnabledForPstates_MASK 0xff
++#define AVS_CONFIG__AvsEnabledForPstates__SHIFT 0x0
++#define AVS_CONFIG__AvsOverrideEnabled_MASK 0x100
++#define AVS_CONFIG__AvsOverrideEnabled__SHIFT 0x8
++#define AVS_CONFIG__AvsPsmTempCompensation_MASK 0x200
++#define AVS_CONFIG__AvsPsmTempCompensation__SHIFT 0x9
++#define AVS_CONFIG__RESERVED1_MASK 0xfc00
++#define AVS_CONFIG__RESERVED1__SHIFT 0xa
++#define AVS_CONFIG__AvsOverrideOffset_MASK 0xff0000
++#define AVS_CONFIG__AvsOverrideOffset__SHIFT 0x10
++#define AVS_CONFIG__RESERVED_MASK 0xff000000
++#define AVS_CONFIG__RESERVED__SHIFT 0x18
++#define TDC_VRM_LIMIT__IDD_MASK 0xffff
++#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
++#define TDC_VRM_LIMIT__IDDNB_MASK 0xffff0000
++#define TDC_VRM_LIMIT__IDDNB__SHIFT 0x10
++#define CU0_PSM_CONFIG__Psm4_MASK 0xff
++#define CU0_PSM_CONFIG__Psm4__SHIFT 0x0
++#define CU0_PSM_CONFIG__Psm3_MASK 0xff00
++#define CU0_PSM_CONFIG__Psm3__SHIFT 0x8
++#define CU0_PSM_CONFIG__Psm2_MASK 0xff0000
++#define CU0_PSM_CONFIG__Psm2__SHIFT 0x10
++#define CU0_PSM_CONFIG__Psm1_MASK 0xff000000
++#define CU0_PSM_CONFIG__Psm1__SHIFT 0x18
++#define CU1_PSM_CONFIG__Psm4_MASK 0xff
++#define CU1_PSM_CONFIG__Psm4__SHIFT 0x0
++#define CU1_PSM_CONFIG__Psm3_MASK 0xff00
++#define CU1_PSM_CONFIG__Psm3__SHIFT 0x8
++#define CU1_PSM_CONFIG__Psm2_MASK 0xff0000
++#define CU1_PSM_CONFIG__Psm2__SHIFT 0x10
++#define CU1_PSM_CONFIG__Psm1_MASK 0xff000000
++#define CU1_PSM_CONFIG__Psm1__SHIFT 0x18
++#define SPMI_CONFIG__SpmiTestCode_MASK 0xff
++#define SPMI_CONFIG__SpmiTestCode__SHIFT 0x0
++#define SPMI_CONFIG__SpmiTestData_MASK 0xff00
++#define SPMI_CONFIG__SpmiTestData__SHIFT 0x8
++#define SPMI_CONFIG__RESERVED_MASK 0xffff0000
++#define SPMI_CONFIG__RESERVED__SHIFT 0x10
++#define SPMI_SMC_CHAIN_ADDR__Addr_MASK 0xffffffff
++#define SPMI_SMC_CHAIN_ADDR__Addr__SHIFT 0x0
++#define SPMI_STATUS__OpDone_MASK 0xff
++#define SPMI_STATUS__OpDone__SHIFT 0x0
++#define SPMI_STATUS__OpFailed_MASK 0xff00
++#define SPMI_STATUS__OpFailed__SHIFT 0x8
++#define AVSNB_CONFIG__AvsEnabledForPstates_MASK 0xf
++#define AVSNB_CONFIG__AvsEnabledForPstates__SHIFT 0x0
++#define AVSNB_CONFIG__RESERVED0_MASK 0xf0
++#define AVSNB_CONFIG__RESERVED0__SHIFT 0x4
++#define AVSNB_CONFIG__AvsOverrideEnabled_MASK 0x100
++#define AVSNB_CONFIG__AvsOverrideEnabled__SHIFT 0x8
++#define AVSNB_CONFIG__AvsPsmTempCompensation_MASK 0x200
++#define AVSNB_CONFIG__AvsPsmTempCompensation__SHIFT 0x9
++#define AVSNB_CONFIG__RESERVED1_MASK 0xfc00
++#define AVSNB_CONFIG__RESERVED1__SHIFT 0xa
++#define AVSNB_CONFIG__AvsOverrideOffset_MASK 0xff0000
++#define AVSNB_CONFIG__AvsOverrideOffset__SHIFT 0x10
++#define AVSNB_CONFIG__RESERVED_MASK 0xff000000
++#define AVSNB_CONFIG__RESERVED__SHIFT 0x18
++#define HTC_CONFIG__CSR_ADDR_MASK 0x3f
++#define HTC_CONFIG__CSR_ADDR__SHIFT 0x0
++#define HTC_CONFIG__TCEN_ID_MASK 0x3c0
++#define HTC_CONFIG__TCEN_ID__SHIFT 0x6
++#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT_MASK 0xff0000
++#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT__SHIFT 0x10
++#define HTC_CONFIG__Reserved_MASK 0xff000000
++#define HTC_CONFIG__Reserved__SHIFT 0x18
++#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
++#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
++#define AVS_CU0_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
++#define AVS_CU0_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
++#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
++#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
++#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
++#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
++#define AVS_CU1_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
++#define AVS_CU1_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
++#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
++#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
++#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
++#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
++#define AVS_GNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
++#define AVS_GNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
++#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
++#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
++#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
++#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
++#define AVS_UNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
++#define AVS_UNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
++#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
++#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
++#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS_MASK 0xffffffff
++#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS__SHIFT 0x0
++#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI_MASK 0xffffffff
++#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI__SHIFT 0x0
++#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO_MASK 0xffffffff
++#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO__SHIFT 0x0
++#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION_MASK 0xffff
++#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION__SHIFT 0x0
++#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE_MASK 0xffff0000
++#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE__SHIFT 0x10
++#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW_MASK 0x1
++#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW__SHIFT 0x0
++#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW_MASK 0x2
++#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW__SHIFT 0x1
++#define SMU_MONITOR_PORT80_CTRL__RESERVED_MASK 0xfffc
++#define SMU_MONITOR_PORT80_CTRL__RESERVED__SHIFT 0x2
++#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL_MASK 0xffff0000
++#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL__SHIFT 0x10
++#define SMU_TCEN_ALIVE__CORE_TCEN_ID_MASK 0xff
++#define SMU_TCEN_ALIVE__CORE_TCEN_ID__SHIFT 0x0
++#define SMU_TCEN_ALIVE__GNB_TCEN_ID_MASK 0xff00
++#define SMU_TCEN_ALIVE__GNB_TCEN_ID__SHIFT 0x8
++#define SMU_TCEN_ALIVE__RESERVED_MASK 0xffff0000
++#define SMU_TCEN_ALIVE__RESERVED__SHIFT 0x10
++#define PDM_STATUS__PDM_ENABLED_MASK 0x1
++#define PDM_STATUS__PDM_ENABLED__SHIFT 0x0
++#define PDM_STATUS__NewCpcTdpLimit_MASK 0x1fffe
++#define PDM_STATUS__NewCpcTdpLimit__SHIFT 0x1
++#define PDM_STATUS__NoofConnectedCores_MASK 0x1e0000
++#define PDM_STATUS__NoofConnectedCores__SHIFT 0x11
++#define PDM_STATUS__Reserved_MASK 0xffe00000
++#define PDM_STATUS__Reserved__SHIFT 0x15
++#define PDM_CNTL_1__BaseCoreTdpLimit0_MASK 0xff
++#define PDM_CNTL_1__BaseCoreTdpLimit0__SHIFT 0x0
++#define PDM_CNTL_1__BaseCoreTdpLimit1_MASK 0xff00
++#define PDM_CNTL_1__BaseCoreTdpLimit1__SHIFT 0x8
++#define PDM_CNTL_1__BaseCoreTdpLimit2_MASK 0xff0000
++#define PDM_CNTL_1__BaseCoreTdpLimit2__SHIFT 0x10
++#define PDM_CNTL_1__GpuPdmMult_MASK 0xff000000
++#define PDM_CNTL_1__GpuPdmMult__SHIFT 0x18
++#define PDM_CNTL_2__HeatPdmTc_MASK 0xff
++#define PDM_CNTL_2__HeatPdmTc__SHIFT 0x0
++#define PDM_CNTL_2__CoolPdmTc_MASK 0xff00
++#define PDM_CNTL_2__CoolPdmTc__SHIFT 0x8
++#define PDM_CNTL_2__GpuPdmTc_MASK 0xff0000
++#define PDM_CNTL_2__GpuPdmTc__SHIFT 0x10
++#define PDM_CNTL_2__GpuActThr_MASK 0xff000000
++#define PDM_CNTL_2__GpuActThr__SHIFT 0x18
++#define PDM_CNTL_3__HeatPdmThr1_MASK 0xff
++#define PDM_CNTL_3__HeatPdmThr1__SHIFT 0x0
++#define PDM_CNTL_3__HeatPdmThr2_MASK 0xff00
++#define PDM_CNTL_3__HeatPdmThr2__SHIFT 0x8
++#define PDM_CNTL_3__CoolPdmThr1_MASK 0xff0000
++#define PDM_CNTL_3__CoolPdmThr1__SHIFT 0x10
++#define PDM_CNTL_3__CoolPdmThr2_MASK 0xff000000
++#define PDM_CNTL_3__CoolPdmThr2__SHIFT 0x18
++#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
++#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
++#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
++#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
++#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
++#define GENERAL_PWRMGT__SPARE11_MASK 0x800
++#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
++#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
++#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
++#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
++#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
++#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
++#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
++#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
++#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
++#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
++#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
++#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
++#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
++#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
++#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
++#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
++#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
++#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
++#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
++#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
++#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
++#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
++#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
++#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
++#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
++#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
++#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
++#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
++#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
++#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
++#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
++#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
++#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
++#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
++#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
++#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
++#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
++#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
++#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
++#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
++#define SCLK_MIN_DIV__FRACV_MASK 0xfff
++#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
++#define SCLK_MIN_DIV__INTV_MASK 0x7f000
++#define SCLK_MIN_DIV__INTV__SHIFT 0xc
++#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
++#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
++#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
++#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
++#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
++#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
++#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
++#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
++#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
++#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
++#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
++#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
++#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
++#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
++#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
++
++#endif /* SMU_7_0_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0019-yocto-amd-drm-amdgpu-add-SMU-8-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0019-yocto-amd-drm-amdgpu-add-SMU-8-0-register-headers.patch
new file mode 100644
index 00000000..991468c2
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0019-yocto-amd-drm-amdgpu-add-SMU-8-0-register-headers.patch
@@ -0,0 +1,6796 @@
+From e5581104ee144c8f812caa5a2e73c3a5054297d6 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:29:30 -0400
+Subject: drm/amdgpu: add SMU 7.0.1 register headers
+
+These are register headers for the SMU (System Management Unit)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+new file mode 100644
+index 0000000..f9fd2ea
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+@@ -0,0 +1,1314 @@
++/*
++ * SMU_7_0_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_0_1_D_H
++#define SMU_7_0_1_D_H
++
++#define mmGCK_SMC_IND_INDEX                                                     0x80
++#define mmGCK0_GCK_SMC_IND_INDEX                                                0x80
++#define mmGCK1_GCK_SMC_IND_INDEX                                                0x82
++#define mmGCK2_GCK_SMC_IND_INDEX                                                0x84
++#define mmGCK3_GCK_SMC_IND_INDEX                                                0x86
++#define mmGCK_SMC_IND_DATA                                                      0x81
++#define mmGCK0_GCK_SMC_IND_DATA                                                 0x81
++#define mmGCK1_GCK_SMC_IND_DATA                                                 0x83
++#define mmGCK2_GCK_SMC_IND_DATA                                                 0x85
++#define mmGCK3_GCK_SMC_IND_DATA                                                 0x87
++#define ixCG_DCLK_CNTL                                                          0xc050009c
++#define ixCG_DCLK_STATUS                                                        0xc05000a0
++#define ixCG_VCLK_CNTL                                                          0xc05000a4
++#define ixCG_VCLK_STATUS                                                        0xc05000a8
++#define ixCG_ECLK_CNTL                                                          0xc05000ac
++#define ixCG_ECLK_STATUS                                                        0xc05000b0
++#define ixCG_ACLK_CNTL                                                          0xc05000dc
++#define ixGCK_DFS_BYPASS_CNTL                                                   0xc0500118
++#define ixCG_SPLL_FUNC_CNTL                                                     0xc0500140
++#define ixCG_SPLL_FUNC_CNTL_2                                                   0xc0500144
++#define ixCG_SPLL_FUNC_CNTL_3                                                   0xc0500148
++#define ixCG_SPLL_FUNC_CNTL_4                                                   0xc050014c
++#define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
++#define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
++#define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixSPLL_CNTL_MODE                                                        0xc0500160
++#define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
++#define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
++#define ixMPLL_BYPASSCLK_SEL                                                    0xc050019c
++#define ixCG_CLKPIN_CNTL                                                        0xc05001a0
++#define ixCG_CLKPIN_CNTL_2                                                      0xc05001a4
++#define ixCG_CLKPIN_CNTL_DC                                                     0xc0500204
++#define ixTHM_CLK_CNTL                                                          0xc05001a8
++#define ixMISC_CLK_CTRL                                                         0xc05001ac
++#define ixGCK_PLL_TEST_CNTL                                                     0xc05001c0
++#define ixGCK_PLL_TEST_CNTL_2                                                   0xc05001c4
++#define ixGCK_ADFS_CLK_BYPASS_CNTL1                                             0xc05001c8
++#define mmSMC_IND_INDEX                                                         0x80
++#define mmSMC0_SMC_IND_INDEX                                                    0x80
++#define mmSMC1_SMC_IND_INDEX                                                    0x82
++#define mmSMC2_SMC_IND_INDEX                                                    0x84
++#define mmSMC3_SMC_IND_INDEX                                                    0x86
++#define mmSMC_IND_DATA                                                          0x81
++#define mmSMC0_SMC_IND_DATA                                                     0x81
++#define mmSMC1_SMC_IND_DATA                                                     0x83
++#define mmSMC2_SMC_IND_DATA                                                     0x85
++#define mmSMC3_SMC_IND_DATA                                                     0x87
++#define mmSMC_IND_INDEX_0                                                       0x80
++#define mmSMC_IND_DATA_0                                                        0x81
++#define mmSMC_IND_INDEX_1                                                       0x82
++#define mmSMC_IND_DATA_1                                                        0x83
++#define mmSMC_IND_INDEX_2                                                       0x84
++#define mmSMC_IND_DATA_2                                                        0x85
++#define mmSMC_IND_INDEX_3                                                       0x86
++#define mmSMC_IND_DATA_3                                                        0x87
++#define mmSMC_IND_INDEX_4                                                       0x88
++#define mmSMC_IND_DATA_4                                                        0x89
++#define mmSMC_IND_INDEX_5                                                       0x8a
++#define mmSMC_IND_DATA_5                                                        0x8b
++#define mmSMC_IND_INDEX_6                                                       0x8c
++#define mmSMC_IND_DATA_6                                                        0x8d
++#define mmSMC_IND_INDEX_7                                                       0x8e
++#define mmSMC_IND_DATA_7                                                        0x8f
++#define mmSMC_IND_ACCESS_CNTL                                                   0x90
++#define mmSMC_MESSAGE_0                                                         0x94
++#define mmSMC_RESP_0                                                            0x95
++#define mmSMC_MESSAGE_1                                                         0x96
++#define mmSMC_RESP_1                                                            0x97
++#define mmSMC_MESSAGE_2                                                         0x98
++#define mmSMC_RESP_2                                                            0x99
++#define mmSMC_MESSAGE_3                                                         0x9a
++#define mmSMC_RESP_3                                                            0x9b
++#define mmSMC_MESSAGE_4                                                         0x9c
++#define mmSMC_RESP_4                                                            0x9d
++#define mmSMC_MESSAGE_5                                                         0x9e
++#define mmSMC_RESP_5                                                            0x9f
++#define mmSMC_MESSAGE_6                                                         0xa0
++#define mmSMC_RESP_6                                                            0xa1
++#define mmSMC_MESSAGE_7                                                         0xa2
++#define mmSMC_RESP_7                                                            0xa3
++#define mmSMC_MSG_ARG_0                                                         0xa4
++#define mmSMC_MSG_ARG_1                                                         0xa5
++#define mmSMC_MSG_ARG_2                                                         0xa6
++#define mmSMC_MSG_ARG_3                                                         0xa7
++#define mmSMC_MSG_ARG_4                                                         0xa8
++#define mmSMC_MSG_ARG_5                                                         0xa9
++#define mmSMC_MSG_ARG_6                                                         0xaa
++#define mmSMC_MSG_ARG_7                                                         0xab
++#define mmSMC_MESSAGE_8                                                         0xb5
++#define mmSMC_RESP_8                                                            0xb6
++#define mmSMC_MESSAGE_9                                                         0xb7
++#define mmSMC_RESP_9                                                            0xb8
++#define mmSMC_MESSAGE_10                                                        0xb9
++#define mmSMC_RESP_10                                                           0xba
++#define mmSMC_MESSAGE_11                                                        0xbb
++#define mmSMC_RESP_11                                                           0xbc
++#define mmSMC_MSG_ARG_8                                                         0xbd
++#define mmSMC_MSG_ARG_9                                                         0xbe
++#define mmSMC_MSG_ARG_10                                                        0xbf
++#define mmSMC_MSG_ARG_11                                                        0x91
++#define ixSMC_SYSCON_RESET_CNTL                                                 0x80000000
++#define ixSMC_SYSCON_CLOCK_CNTL_0                                               0x80000004
++#define ixSMC_SYSCON_CLOCK_CNTL_1                                               0x80000008
++#define ixSMC_SYSCON_CLOCK_CNTL_2                                               0x8000000c
++#define ixSMC_SYSCON_MISC_CNTL                                                  0x80000010
++#define ixSMC_SYSCON_MSG_ARG_0                                                  0x80000068
++#define ixSMC_PC_C                                                              0x80000370
++#define ixSMC_SCRATCH9                                                          0x80000424
++#define mmGPIOPAD_SW_INT_STAT                                                   0x180
++#define mmGPIOPAD_STRENGTH                                                      0x181
++#define mmGPIOPAD_MASK                                                          0x182
++#define mmGPIOPAD_A                                                             0x183
++#define mmGPIOPAD_EN                                                            0x184
++#define mmGPIOPAD_Y                                                             0x185
++#define mmGPIOPAD_PINSTRAPS                                                     0x186
++#define mmGPIOPAD_INT_STAT_EN                                                   0x187
++#define mmGPIOPAD_INT_STAT                                                      0x188
++#define mmGPIOPAD_INT_STAT_AK                                                   0x189
++#define mmGPIOPAD_INT_EN                                                        0x18a
++#define mmGPIOPAD_INT_TYPE                                                      0x18b
++#define mmGPIOPAD_INT_POLARITY                                                  0x18c
++#define mmGPIOPAD_EXTERN_TRIG_CNTL                                              0x18d
++#define mmGPIOPAD_RCVR_SEL                                                      0x191
++#define mmGPIOPAD_PU_EN                                                         0x192
++#define mmGPIOPAD_PD_EN                                                         0x193
++#define mmCG_FPS_CNT                                                            0x1a4
++#define mmSMU_SMC_IND_INDEX                                                     0x80
++#define mmSMU0_SMU_SMC_IND_INDEX                                                0x80
++#define mmSMU1_SMU_SMC_IND_INDEX                                                0x82
++#define mmSMU2_SMU_SMC_IND_INDEX                                                0x84
++#define mmSMU3_SMU_SMC_IND_INDEX                                                0x86
++#define mmSMU_SMC_IND_DATA                                                      0x81
++#define mmSMU0_SMU_SMC_IND_DATA                                                 0x81
++#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83
++#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85
++#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87
++#define ixRCU_UC_EVENTS                                                         0xc0000004
++#define ixRCU_MISC_CTRL                                                         0xc0000010
++#define ixCC_RCU_FUSES                                                          0xc00c0000
++#define ixCC_SMU_MISC_FUSES                                                     0xc00c0004
++#define ixCC_SCLK_VID_FUSES                                                     0xc00c0008
++#define ixCC_GIO_IOCCFG_FUSES                                                   0xc00c000c
++#define ixCC_GIO_IOC_FUSES                                                      0xc00c0010
++#define ixCC_SMU_TST_EFUSE1_MISC                                                0xc00c001c
++#define ixCC_TST_ID_STRAPS                                                      0xc00c0020
++#define ixCC_FCTRL_FUSES                                                        0xc00c0024
++#define ixSMU_MAIN_PLL_OP_FREQ                                                  0xe0003020
++#define ixSMU_STATUS                                                            0xe0003088
++#define ixSMU_FIRMWARE                                                          0xe00030a4
++#define ixSMU_INPUT_DATA                                                        0xe00030b8
++#define ixSMU_EFUSE_0                                                           0xc0100000
++#define ixDPM_TABLE_1                                                           0x3f000
++#define ixDPM_TABLE_2                                                           0x3f004
++#define ixDPM_TABLE_3                                                           0x3f008
++#define ixDPM_TABLE_4                                                           0x3f00c
++#define ixDPM_TABLE_5                                                           0x3f010
++#define ixDPM_TABLE_6                                                           0x3f014
++#define ixDPM_TABLE_7                                                           0x3f018
++#define ixDPM_TABLE_8                                                           0x3f01c
++#define ixDPM_TABLE_9                                                           0x3f020
++#define ixDPM_TABLE_10                                                          0x3f024
++#define ixDPM_TABLE_11                                                          0x3f028
++#define ixDPM_TABLE_12                                                          0x3f02c
++#define ixDPM_TABLE_13                                                          0x3f030
++#define ixDPM_TABLE_14                                                          0x3f034
++#define ixDPM_TABLE_15                                                          0x3f038
++#define ixDPM_TABLE_16                                                          0x3f03c
++#define ixDPM_TABLE_17                                                          0x3f040
++#define ixDPM_TABLE_18                                                          0x3f044
++#define ixDPM_TABLE_19                                                          0x3f048
++#define ixDPM_TABLE_20                                                          0x3f04c
++#define ixDPM_TABLE_21                                                          0x3f050
++#define ixDPM_TABLE_22                                                          0x3f054
++#define ixDPM_TABLE_23                                                          0x3f058
++#define ixDPM_TABLE_24                                                          0x3f05c
++#define ixDPM_TABLE_25                                                          0x3f060
++#define ixDPM_TABLE_26                                                          0x3f064
++#define ixDPM_TABLE_27                                                          0x3f068
++#define ixDPM_TABLE_28                                                          0x3f06c
++#define ixDPM_TABLE_29                                                          0x3f070
++#define ixDPM_TABLE_30                                                          0x3f074
++#define ixDPM_TABLE_31                                                          0x3f078
++#define ixDPM_TABLE_32                                                          0x3f07c
++#define ixDPM_TABLE_33                                                          0x3f080
++#define ixDPM_TABLE_34                                                          0x3f084
++#define ixDPM_TABLE_35                                                          0x3f088
++#define ixDPM_TABLE_36                                                          0x3f08c
++#define ixDPM_TABLE_37                                                          0x3f090
++#define ixDPM_TABLE_38                                                          0x3f094
++#define ixDPM_TABLE_39                                                          0x3f098
++#define ixDPM_TABLE_40                                                          0x3f09c
++#define ixDPM_TABLE_41                                                          0x3f0a0
++#define ixDPM_TABLE_42                                                          0x3f0a4
++#define ixDPM_TABLE_43                                                          0x3f0a8
++#define ixDPM_TABLE_44                                                          0x3f0ac
++#define ixDPM_TABLE_45                                                          0x3f0b0
++#define ixDPM_TABLE_46                                                          0x3f0b4
++#define ixDPM_TABLE_47                                                          0x3f0b8
++#define ixDPM_TABLE_48                                                          0x3f0bc
++#define ixDPM_TABLE_49                                                          0x3f0c0
++#define ixDPM_TABLE_50                                                          0x3f0c4
++#define ixDPM_TABLE_51                                                          0x3f0c8
++#define ixDPM_TABLE_52                                                          0x3f0cc
++#define ixDPM_TABLE_53                                                          0x3f0d0
++#define ixDPM_TABLE_54                                                          0x3f0d4
++#define ixDPM_TABLE_55                                                          0x3f0d8
++#define ixDPM_TABLE_56                                                          0x3f0dc
++#define ixDPM_TABLE_57                                                          0x3f0e0
++#define ixDPM_TABLE_58                                                          0x3f0e4
++#define ixDPM_TABLE_59                                                          0x3f0e8
++#define ixDPM_TABLE_60                                                          0x3f0ec
++#define ixDPM_TABLE_61                                                          0x3f0f0
++#define ixDPM_TABLE_62                                                          0x3f0f4
++#define ixDPM_TABLE_63                                                          0x3f0f8
++#define ixDPM_TABLE_64                                                          0x3f0fc
++#define ixDPM_TABLE_65                                                          0x3f100
++#define ixDPM_TABLE_66                                                          0x3f104
++#define ixDPM_TABLE_67                                                          0x3f108
++#define ixDPM_TABLE_68                                                          0x3f10c
++#define ixDPM_TABLE_69                                                          0x3f110
++#define ixDPM_TABLE_70                                                          0x3f114
++#define ixDPM_TABLE_71                                                          0x3f118
++#define ixDPM_TABLE_72                                                          0x3f11c
++#define ixDPM_TABLE_73                                                          0x3f120
++#define ixDPM_TABLE_74                                                          0x3f124
++#define ixDPM_TABLE_75                                                          0x3f128
++#define ixDPM_TABLE_76                                                          0x3f12c
++#define ixDPM_TABLE_77                                                          0x3f130
++#define ixDPM_TABLE_78                                                          0x3f134
++#define ixDPM_TABLE_79                                                          0x3f138
++#define ixDPM_TABLE_80                                                          0x3f13c
++#define ixDPM_TABLE_81                                                          0x3f140
++#define ixDPM_TABLE_82                                                          0x3f144
++#define ixDPM_TABLE_83                                                          0x3f148
++#define ixDPM_TABLE_84                                                          0x3f14c
++#define ixDPM_TABLE_85                                                          0x3f150
++#define ixDPM_TABLE_86                                                          0x3f154
++#define ixDPM_TABLE_87                                                          0x3f158
++#define ixDPM_TABLE_88                                                          0x3f15c
++#define ixDPM_TABLE_89                                                          0x3f160
++#define ixDPM_TABLE_90                                                          0x3f164
++#define ixDPM_TABLE_91                                                          0x3f168
++#define ixDPM_TABLE_92                                                          0x3f16c
++#define ixDPM_TABLE_93                                                          0x3f170
++#define ixDPM_TABLE_94                                                          0x3f174
++#define ixDPM_TABLE_95                                                          0x3f178
++#define ixDPM_TABLE_96                                                          0x3f17c
++#define ixDPM_TABLE_97                                                          0x3f180
++#define ixDPM_TABLE_98                                                          0x3f184
++#define ixDPM_TABLE_99                                                          0x3f188
++#define ixDPM_TABLE_100                                                         0x3f18c
++#define ixDPM_TABLE_101                                                         0x3f190
++#define ixDPM_TABLE_102                                                         0x3f194
++#define ixDPM_TABLE_103                                                         0x3f198
++#define ixDPM_TABLE_104                                                         0x3f19c
++#define ixDPM_TABLE_105                                                         0x3f1a0
++#define ixDPM_TABLE_106                                                         0x3f1a4
++#define ixDPM_TABLE_107                                                         0x3f1a8
++#define ixDPM_TABLE_108                                                         0x3f1ac
++#define ixDPM_TABLE_109                                                         0x3f1b0
++#define ixDPM_TABLE_110                                                         0x3f1b4
++#define ixDPM_TABLE_111                                                         0x3f1b8
++#define ixDPM_TABLE_112                                                         0x3f1bc
++#define ixDPM_TABLE_113                                                         0x3f1c0
++#define ixDPM_TABLE_114                                                         0x3f1c4
++#define ixDPM_TABLE_115                                                         0x3f1c8
++#define ixDPM_TABLE_116                                                         0x3f1cc
++#define ixDPM_TABLE_117                                                         0x3f1d0
++#define ixDPM_TABLE_118                                                         0x3f1d4
++#define ixDPM_TABLE_119                                                         0x3f1d8
++#define ixDPM_TABLE_120                                                         0x3f1dc
++#define ixDPM_TABLE_121                                                         0x3f1e0
++#define ixDPM_TABLE_122                                                         0x3f1e4
++#define ixDPM_TABLE_123                                                         0x3f1e8
++#define ixDPM_TABLE_124                                                         0x3f1ec
++#define ixDPM_TABLE_125                                                         0x3f1f0
++#define ixDPM_TABLE_126                                                         0x3f1f4
++#define ixDPM_TABLE_127                                                         0x3f1f8
++#define ixDPM_TABLE_128                                                         0x3f1fc
++#define ixDPM_TABLE_129                                                         0x3f200
++#define ixDPM_TABLE_130                                                         0x3f204
++#define ixDPM_TABLE_131                                                         0x3f208
++#define ixDPM_TABLE_132                                                         0x3f20c
++#define ixDPM_TABLE_133                                                         0x3f210
++#define ixDPM_TABLE_134                                                         0x3f214
++#define ixDPM_TABLE_135                                                         0x3f218
++#define ixDPM_TABLE_136                                                         0x3f21c
++#define ixDPM_TABLE_137                                                         0x3f220
++#define ixDPM_TABLE_138                                                         0x3f224
++#define ixDPM_TABLE_139                                                         0x3f228
++#define ixDPM_TABLE_140                                                         0x3f22c
++#define ixDPM_TABLE_141                                                         0x3f230
++#define ixDPM_TABLE_142                                                         0x3f234
++#define ixDPM_TABLE_143                                                         0x3f238
++#define ixDPM_TABLE_144                                                         0x3f23c
++#define ixDPM_TABLE_145                                                         0x3f240
++#define ixDPM_TABLE_146                                                         0x3f244
++#define ixDPM_TABLE_147                                                         0x3f248
++#define ixDPM_TABLE_148                                                         0x3f24c
++#define ixDPM_TABLE_149                                                         0x3f250
++#define ixDPM_TABLE_150                                                         0x3f254
++#define ixDPM_TABLE_151                                                         0x3f258
++#define ixDPM_TABLE_152                                                         0x3f25c
++#define ixDPM_TABLE_153                                                         0x3f260
++#define ixDPM_TABLE_154                                                         0x3f264
++#define ixDPM_TABLE_155                                                         0x3f268
++#define ixDPM_TABLE_156                                                         0x3f26c
++#define ixDPM_TABLE_157                                                         0x3f270
++#define ixDPM_TABLE_158                                                         0x3f274
++#define ixDPM_TABLE_159                                                         0x3f278
++#define ixDPM_TABLE_160                                                         0x3f27c
++#define ixDPM_TABLE_161                                                         0x3f280
++#define ixDPM_TABLE_162                                                         0x3f284
++#define ixDPM_TABLE_163                                                         0x3f288
++#define ixDPM_TABLE_164                                                         0x3f28c
++#define ixDPM_TABLE_165                                                         0x3f290
++#define ixDPM_TABLE_166                                                         0x3f294
++#define ixDPM_TABLE_167                                                         0x3f298
++#define ixDPM_TABLE_168                                                         0x3f29c
++#define ixDPM_TABLE_169                                                         0x3f2a0
++#define ixDPM_TABLE_170                                                         0x3f2a4
++#define ixDPM_TABLE_171                                                         0x3f2a8
++#define ixDPM_TABLE_172                                                         0x3f2ac
++#define ixDPM_TABLE_173                                                         0x3f2b0
++#define ixDPM_TABLE_174                                                         0x3f2b4
++#define ixDPM_TABLE_175                                                         0x3f2b8
++#define ixDPM_TABLE_176                                                         0x3f2bc
++#define ixDPM_TABLE_177                                                         0x3f2c0
++#define ixDPM_TABLE_178                                                         0x3f2c4
++#define ixDPM_TABLE_179                                                         0x3f2c8
++#define ixDPM_TABLE_180                                                         0x3f2cc
++#define ixDPM_TABLE_181                                                         0x3f2d0
++#define ixDPM_TABLE_182                                                         0x3f2d4
++#define ixDPM_TABLE_183                                                         0x3f2d8
++#define ixDPM_TABLE_184                                                         0x3f2dc
++#define ixDPM_TABLE_185                                                         0x3f2e0
++#define ixDPM_TABLE_186                                                         0x3f2e4
++#define ixDPM_TABLE_187                                                         0x3f2e8
++#define ixDPM_TABLE_188                                                         0x3f2ec
++#define ixDPM_TABLE_189                                                         0x3f2f0
++#define ixDPM_TABLE_190                                                         0x3f2f4
++#define ixDPM_TABLE_191                                                         0x3f2f8
++#define ixDPM_TABLE_192                                                         0x3f2fc
++#define ixDPM_TABLE_193                                                         0x3f300
++#define ixDPM_TABLE_194                                                         0x3f304
++#define ixDPM_TABLE_195                                                         0x3f308
++#define ixDPM_TABLE_196                                                         0x3f30c
++#define ixDPM_TABLE_197                                                         0x3f310
++#define ixDPM_TABLE_198                                                         0x3f314
++#define ixDPM_TABLE_199                                                         0x3f318
++#define ixDPM_TABLE_200                                                         0x3f31c
++#define ixDPM_TABLE_201                                                         0x3f320
++#define ixDPM_TABLE_202                                                         0x3f324
++#define ixDPM_TABLE_203                                                         0x3f328
++#define ixDPM_TABLE_204                                                         0x3f32c
++#define ixDPM_TABLE_205                                                         0x3f330
++#define ixDPM_TABLE_206                                                         0x3f334
++#define ixDPM_TABLE_207                                                         0x3f338
++#define ixDPM_TABLE_208                                                         0x3f33c
++#define ixDPM_TABLE_209                                                         0x3f340
++#define ixDPM_TABLE_210                                                         0x3f344
++#define ixDPM_TABLE_211                                                         0x3f348
++#define ixDPM_TABLE_212                                                         0x3f34c
++#define ixDPM_TABLE_213                                                         0x3f350
++#define ixDPM_TABLE_214                                                         0x3f354
++#define ixDPM_TABLE_215                                                         0x3f358
++#define ixDPM_TABLE_216                                                         0x3f35c
++#define ixDPM_TABLE_217                                                         0x3f360
++#define ixDPM_TABLE_218                                                         0x3f364
++#define ixDPM_TABLE_219                                                         0x3f368
++#define ixDPM_TABLE_220                                                         0x3f36c
++#define ixDPM_TABLE_221                                                         0x3f370
++#define ixDPM_TABLE_222                                                         0x3f374
++#define ixDPM_TABLE_223                                                         0x3f378
++#define ixDPM_TABLE_224                                                         0x3f37c
++#define ixDPM_TABLE_225                                                         0x3f380
++#define ixDPM_TABLE_226                                                         0x3f384
++#define ixDPM_TABLE_227                                                         0x3f388
++#define ixDPM_TABLE_228                                                         0x3f38c
++#define ixDPM_TABLE_229                                                         0x3f390
++#define ixDPM_TABLE_230                                                         0x3f394
++#define ixDPM_TABLE_231                                                         0x3f398
++#define ixDPM_TABLE_232                                                         0x3f39c
++#define ixDPM_TABLE_233                                                         0x3f3a0
++#define ixDPM_TABLE_234                                                         0x3f3a4
++#define ixDPM_TABLE_235                                                         0x3f3a8
++#define ixDPM_TABLE_236                                                         0x3f3ac
++#define ixDPM_TABLE_237                                                         0x3f3b0
++#define ixDPM_TABLE_238                                                         0x3f3b4
++#define ixDPM_TABLE_239                                                         0x3f3b8
++#define ixDPM_TABLE_240                                                         0x3f3bc
++#define ixDPM_TABLE_241                                                         0x3f3c0
++#define ixDPM_TABLE_242                                                         0x3f3c4
++#define ixDPM_TABLE_243                                                         0x3f3c8
++#define ixDPM_TABLE_244                                                         0x3f3cc
++#define ixDPM_TABLE_245                                                         0x3f3d0
++#define ixDPM_TABLE_246                                                         0x3f3d4
++#define ixDPM_TABLE_247                                                         0x3f3d8
++#define ixDPM_TABLE_248                                                         0x3f3dc
++#define ixDPM_TABLE_249                                                         0x3f3e0
++#define ixDPM_TABLE_250                                                         0x3f3e4
++#define ixDPM_TABLE_251                                                         0x3f3e8
++#define ixDPM_TABLE_252                                                         0x3f3ec
++#define ixDPM_TABLE_253                                                         0x3f3f0
++#define ixDPM_TABLE_254                                                         0x3f3f4
++#define ixDPM_TABLE_255                                                         0x3f3f8
++#define ixDPM_TABLE_256                                                         0x3f3fc
++#define ixDPM_TABLE_257                                                         0x3f400
++#define ixDPM_TABLE_258                                                         0x3f404
++#define ixDPM_TABLE_259                                                         0x3f408
++#define ixDPM_TABLE_260                                                         0x3f40c
++#define ixDPM_TABLE_261                                                         0x3f410
++#define ixDPM_TABLE_262                                                         0x3f414
++#define ixDPM_TABLE_263                                                         0x3f418
++#define ixDPM_TABLE_264                                                         0x3f41c
++#define ixDPM_TABLE_265                                                         0x3f420
++#define ixDPM_TABLE_266                                                         0x3f424
++#define ixDPM_TABLE_267                                                         0x3f428
++#define ixDPM_TABLE_268                                                         0x3f42c
++#define ixDPM_TABLE_269                                                         0x3f430
++#define ixDPM_TABLE_270                                                         0x3f434
++#define ixDPM_TABLE_271                                                         0x3f438
++#define ixDPM_TABLE_272                                                         0x3f43c
++#define ixDPM_TABLE_273                                                         0x3f440
++#define ixDPM_TABLE_274                                                         0x3f444
++#define ixDPM_TABLE_275                                                         0x3f448
++#define ixDPM_TABLE_276                                                         0x3f44c
++#define ixDPM_TABLE_277                                                         0x3f450
++#define ixDPM_TABLE_278                                                         0x3f454
++#define ixDPM_TABLE_279                                                         0x3f458
++#define ixDPM_TABLE_280                                                         0x3f45c
++#define ixDPM_TABLE_281                                                         0x3f460
++#define ixDPM_TABLE_282                                                         0x3f464
++#define ixDPM_TABLE_283                                                         0x3f468
++#define ixDPM_TABLE_284                                                         0x3f46c
++#define ixDPM_TABLE_285                                                         0x3f470
++#define ixDPM_TABLE_286                                                         0x3f474
++#define ixDPM_TABLE_287                                                         0x3f478
++#define ixDPM_TABLE_288                                                         0x3f47c
++#define ixDPM_TABLE_289                                                         0x3f480
++#define ixDPM_TABLE_290                                                         0x3f484
++#define ixDPM_TABLE_291                                                         0x3f488
++#define ixDPM_TABLE_292                                                         0x3f48c
++#define ixDPM_TABLE_293                                                         0x3f490
++#define ixDPM_TABLE_294                                                         0x3f494
++#define ixDPM_TABLE_295                                                         0x3f498
++#define ixDPM_TABLE_296                                                         0x3f49c
++#define ixDPM_TABLE_297                                                         0x3f4a0
++#define ixDPM_TABLE_298                                                         0x3f4a4
++#define ixDPM_TABLE_299                                                         0x3f4a8
++#define ixDPM_TABLE_300                                                         0x3f4ac
++#define ixDPM_TABLE_301                                                         0x3f4b0
++#define ixDPM_TABLE_302                                                         0x3f4b4
++#define ixDPM_TABLE_303                                                         0x3f4b8
++#define ixDPM_TABLE_304                                                         0x3f4bc
++#define ixDPM_TABLE_305                                                         0x3f4c0
++#define ixDPM_TABLE_306                                                         0x3f4c4
++#define ixDPM_TABLE_307                                                         0x3f4c8
++#define ixDPM_TABLE_308                                                         0x3f4cc
++#define ixDPM_TABLE_309                                                         0x3f4d0
++#define ixDPM_TABLE_310                                                         0x3f4d4
++#define ixDPM_TABLE_311                                                         0x3f4d8
++#define ixDPM_TABLE_312                                                         0x3f4dc
++#define ixDPM_TABLE_313                                                         0x3f4e0
++#define ixDPM_TABLE_314                                                         0x3f4e4
++#define ixDPM_TABLE_315                                                         0x3f4e8
++#define ixDPM_TABLE_316                                                         0x3f4ec
++#define ixDPM_TABLE_317                                                         0x3f4f0
++#define ixDPM_TABLE_318                                                         0x3f4f4
++#define ixDPM_TABLE_319                                                         0x3f4f8
++#define ixDPM_TABLE_320                                                         0x3f4fc
++#define ixDPM_TABLE_321                                                         0x3f500
++#define ixDPM_TABLE_322                                                         0x3f504
++#define ixDPM_TABLE_323                                                         0x3f508
++#define ixDPM_TABLE_324                                                         0x3f50c
++#define ixDPM_TABLE_325                                                         0x3f510
++#define ixDPM_TABLE_326                                                         0x3f514
++#define ixDPM_TABLE_327                                                         0x3f518
++#define ixDPM_TABLE_328                                                         0x3f51c
++#define ixDPM_TABLE_329                                                         0x3f520
++#define ixDPM_TABLE_330                                                         0x3f524
++#define ixDPM_TABLE_331                                                         0x3f528
++#define ixDPM_TABLE_332                                                         0x3f52c
++#define ixDPM_TABLE_333                                                         0x3f530
++#define ixDPM_TABLE_334                                                         0x3f534
++#define ixDPM_TABLE_335                                                         0x3f538
++#define ixDPM_TABLE_336                                                         0x3f53c
++#define ixDPM_TABLE_337                                                         0x3f540
++#define ixDPM_TABLE_338                                                         0x3f544
++#define ixDPM_TABLE_339                                                         0x3f548
++#define ixDPM_TABLE_340                                                         0x3f54c
++#define ixDPM_TABLE_341                                                         0x3f550
++#define ixDPM_TABLE_342                                                         0x3f554
++#define ixDPM_TABLE_343                                                         0x3f558
++#define ixDPM_TABLE_344                                                         0x3f55c
++#define ixDPM_TABLE_345                                                         0x3f560
++#define ixDPM_TABLE_346                                                         0x3f564
++#define ixDPM_TABLE_347                                                         0x3f568
++#define ixDPM_TABLE_348                                                         0x3f56c
++#define ixDPM_TABLE_349                                                         0x3f570
++#define ixDPM_TABLE_350                                                         0x3f574
++#define ixDPM_TABLE_351                                                         0x3f578
++#define ixDPM_TABLE_352                                                         0x3f57c
++#define ixDPM_TABLE_353                                                         0x3f580
++#define ixDPM_TABLE_354                                                         0x3f584
++#define ixDPM_TABLE_355                                                         0x3f588
++#define ixDPM_TABLE_356                                                         0x3f58c
++#define ixDPM_TABLE_357                                                         0x3f590
++#define ixDPM_TABLE_358                                                         0x3f594
++#define ixDPM_TABLE_359                                                         0x3f598
++#define ixDPM_TABLE_360                                                         0x3f59c
++#define ixDPM_TABLE_361                                                         0x3f5a0
++#define ixDPM_TABLE_362                                                         0x3f5a4
++#define ixDPM_TABLE_363                                                         0x3f5a8
++#define ixDPM_TABLE_364                                                         0x3f5ac
++#define ixDPM_TABLE_365                                                         0x3f5b0
++#define ixDPM_TABLE_366                                                         0x3f5b4
++#define ixDPM_TABLE_367                                                         0x3f5b8
++#define ixDPM_TABLE_368                                                         0x3f5bc
++#define ixDPM_TABLE_369                                                         0x3f5c0
++#define ixDPM_TABLE_370                                                         0x3f5c4
++#define ixDPM_TABLE_371                                                         0x3f5c8
++#define ixDPM_TABLE_372                                                         0x3f5cc
++#define ixDPM_TABLE_373                                                         0x3f5d0
++#define ixDPM_TABLE_374                                                         0x3f5d4
++#define ixDPM_TABLE_375                                                         0x3f5d8
++#define ixDPM_TABLE_376                                                         0x3f5dc
++#define ixDPM_TABLE_377                                                         0x3f5e0
++#define ixDPM_TABLE_378                                                         0x3f5e4
++#define ixDPM_TABLE_379                                                         0x3f5e8
++#define ixDPM_TABLE_380                                                         0x3f5ec
++#define ixDPM_TABLE_381                                                         0x3f5f0
++#define ixDPM_TABLE_382                                                         0x3f5f4
++#define ixDPM_TABLE_383                                                         0x3f5f8
++#define ixDPM_TABLE_384                                                         0x3f5fc
++#define ixDPM_TABLE_385                                                         0x3f600
++#define ixDPM_TABLE_386                                                         0x3f604
++#define ixDPM_TABLE_387                                                         0x3f608
++#define ixDPM_TABLE_388                                                         0x3f60c
++#define ixDPM_TABLE_389                                                         0x3f610
++#define ixDPM_TABLE_390                                                         0x3f614
++#define ixDPM_TABLE_391                                                         0x3f618
++#define ixDPM_TABLE_392                                                         0x3f61c
++#define ixDPM_TABLE_393                                                         0x3f620
++#define ixDPM_TABLE_394                                                         0x3f624
++#define ixDPM_TABLE_395                                                         0x3f628
++#define ixDPM_TABLE_396                                                         0x3f62c
++#define ixDPM_TABLE_397                                                         0x3f630
++#define ixDPM_TABLE_398                                                         0x3f634
++#define ixDPM_TABLE_399                                                         0x3f638
++#define ixDPM_TABLE_400                                                         0x3f63c
++#define ixDPM_TABLE_401                                                         0x3f640
++#define ixDPM_TABLE_402                                                         0x3f644
++#define ixDPM_TABLE_403                                                         0x3f648
++#define ixDPM_TABLE_404                                                         0x3f64c
++#define ixDPM_TABLE_405                                                         0x3f650
++#define ixDPM_TABLE_406                                                         0x3f654
++#define ixDPM_TABLE_407                                                         0x3f658
++#define ixDPM_TABLE_408                                                         0x3f65c
++#define ixDPM_TABLE_409                                                         0x3f660
++#define ixDPM_TABLE_410                                                         0x3f664
++#define ixDPM_TABLE_411                                                         0x3f668
++#define ixDPM_TABLE_412                                                         0x3f66c
++#define ixDPM_TABLE_413                                                         0x3f670
++#define ixDPM_TABLE_414                                                         0x3f674
++#define ixDPM_TABLE_415                                                         0x3f678
++#define ixDPM_TABLE_416                                                         0x3f67c
++#define ixDPM_TABLE_417                                                         0x3f680
++#define ixDPM_TABLE_418                                                         0x3f684
++#define ixDPM_TABLE_419                                                         0x3f688
++#define ixDPM_TABLE_420                                                         0x3f68c
++#define ixDPM_TABLE_421                                                         0x3f690
++#define ixDPM_TABLE_422                                                         0x3f694
++#define ixDPM_TABLE_423                                                         0x3f698
++#define ixDPM_TABLE_424                                                         0x3f69c
++#define ixDPM_TABLE_425                                                         0x3f6a0
++#define ixDPM_TABLE_426                                                         0x3f6a4
++#define ixDPM_TABLE_427                                                         0x3f6a8
++#define ixDPM_TABLE_428                                                         0x3f6ac
++#define ixDPM_TABLE_429                                                         0x3f6b0
++#define ixDPM_TABLE_430                                                         0x3f6b4
++#define ixDPM_TABLE_431                                                         0x3f6b8
++#define ixDPM_TABLE_432                                                         0x3f6bc
++#define ixDPM_TABLE_433                                                         0x3f6c0
++#define ixDPM_TABLE_434                                                         0x3f6c4
++#define ixDPM_TABLE_435                                                         0x3f6c8
++#define ixDPM_TABLE_436                                                         0x3f6cc
++#define ixDPM_TABLE_437                                                         0x3f6d0
++#define ixDPM_TABLE_438                                                         0x3f6d4
++#define ixDPM_TABLE_439                                                         0x3f6d8
++#define ixDPM_TABLE_440                                                         0x3f6dc
++#define ixDPM_TABLE_441                                                         0x3f6e0
++#define ixDPM_TABLE_442                                                         0x3f6e4
++#define ixDPM_TABLE_443                                                         0x3f6e8
++#define ixDPM_TABLE_444                                                         0x3f6ec
++#define ixDPM_TABLE_445                                                         0x3f6f0
++#define ixDPM_TABLE_446                                                         0x3f6f4
++#define ixDPM_TABLE_447                                                         0x3f6f8
++#define ixDPM_TABLE_448                                                         0x3f6fc
++#define ixDPM_TABLE_449                                                         0x3f700
++#define ixDPM_TABLE_450                                                         0x3f704
++#define ixDPM_TABLE_451                                                         0x3f708
++#define ixDPM_TABLE_452                                                         0x3f70c
++#define ixDPM_TABLE_453                                                         0x3f710
++#define ixDPM_TABLE_454                                                         0x3f714
++#define ixDPM_TABLE_455                                                         0x3f718
++#define ixDPM_TABLE_456                                                         0x3f71c
++#define ixDPM_TABLE_457                                                         0x3f720
++#define ixDPM_TABLE_458                                                         0x3f724
++#define ixDPM_TABLE_459                                                         0x3f728
++#define ixDPM_TABLE_460                                                         0x3f72c
++#define ixDPM_TABLE_461                                                         0x3f730
++#define ixDPM_TABLE_462                                                         0x3f734
++#define ixDPM_TABLE_463                                                         0x3f738
++#define ixDPM_TABLE_464                                                         0x3f73c
++#define ixDPM_TABLE_465                                                         0x3f740
++#define ixDPM_TABLE_466                                                         0x3f744
++#define ixDPM_TABLE_467                                                         0x3f748
++#define ixDPM_TABLE_468                                                         0x3f74c
++#define ixDPM_TABLE_469                                                         0x3f750
++#define ixDPM_TABLE_470                                                         0x3f754
++#define ixDPM_TABLE_471                                                         0x3f758
++#define ixDPM_TABLE_472                                                         0x3f75c
++#define ixDPM_TABLE_473                                                         0x3f760
++#define ixDPM_TABLE_474                                                         0x3f764
++#define ixDPM_TABLE_475                                                         0x3f768
++#define ixDPM_TABLE_476                                                         0x3f76c
++#define ixDPM_TABLE_477                                                         0x3f770
++#define ixDPM_TABLE_478                                                         0x3f774
++#define ixDPM_TABLE_479                                                         0x3f778
++#define ixDPM_TABLE_480                                                         0x3f77c
++#define ixDPM_TABLE_481                                                         0x3f780
++#define ixDPM_TABLE_482                                                         0x3f784
++#define ixDPM_TABLE_483                                                         0x3f788
++#define ixDPM_TABLE_484                                                         0x3f78c
++#define ixDPM_TABLE_485                                                         0x3f790
++#define ixDPM_TABLE_486                                                         0x3f794
++#define ixDPM_TABLE_487                                                         0x3f798
++#define ixDPM_TABLE_488                                                         0x3f79c
++#define ixDPM_TABLE_489                                                         0x3f7a0
++#define ixDPM_TABLE_490                                                         0x3f7a4
++#define ixDPM_TABLE_491                                                         0x3f7a8
++#define ixDPM_TABLE_492                                                         0x3f7ac
++#define ixDPM_TABLE_493                                                         0x3f7b0
++#define ixDPM_TABLE_494                                                         0x3f7b4
++#define ixDPM_TABLE_495                                                         0x3f7b8
++#define ixDPM_TABLE_496                                                         0x3f7bc
++#define ixDPM_TABLE_497                                                         0x3f7c0
++#define ixDPM_TABLE_498                                                         0x3f7c4
++#define ixDPM_TABLE_499                                                         0x3f7c8
++#define ixDPM_TABLE_500                                                         0x3f7cc
++#define ixDPM_TABLE_501                                                         0x3f7d0
++#define ixDPM_TABLE_502                                                         0x3f7d4
++#define ixDPM_TABLE_503                                                         0x3f7d8
++#define ixDPM_TABLE_504                                                         0x3f7dc
++#define ixDPM_TABLE_505                                                         0x3f7e0
++#define ixDPM_TABLE_506                                                         0x3f7e4
++#define ixDPM_TABLE_507                                                         0x3f7e8
++#define ixDPM_TABLE_508                                                         0x3f7ec
++#define ixDPM_TABLE_509                                                         0x3f7f0
++#define ixDPM_TABLE_510                                                         0x3f7f4
++#define ixFIRMWARE_FLAGS                                                        0x3f800
++#define ixTDC_STATUS                                                            0x3f808
++#define ixTDC_MV_AVERAGE                                                        0x3f80c
++#define ixTDC_VRM_LIMIT                                                         0x3f810
++#define ixFEATURE_STATUS                                                        0x3f818
++#define ixENTITY_TEMPERATURES_1                                                 0x3f81c
++#define ixMCARB_DRAM_TIMING_TABLE_1                                             0x3f900
++#define ixMCARB_DRAM_TIMING_TABLE_2                                             0x3f904
++#define ixMCARB_DRAM_TIMING_TABLE_3                                             0x3f908
++#define ixMCARB_DRAM_TIMING_TABLE_4                                             0x3f90c
++#define ixMCARB_DRAM_TIMING_TABLE_5                                             0x3f910
++#define ixMCARB_DRAM_TIMING_TABLE_6                                             0x3f914
++#define ixMCARB_DRAM_TIMING_TABLE_7                                             0x3f918
++#define ixMCARB_DRAM_TIMING_TABLE_8                                             0x3f91c
++#define ixMCARB_DRAM_TIMING_TABLE_9                                             0x3f920
++#define ixMCARB_DRAM_TIMING_TABLE_10                                            0x3f924
++#define ixMCARB_DRAM_TIMING_TABLE_11                                            0x3f928
++#define ixMCARB_DRAM_TIMING_TABLE_12                                            0x3f92c
++#define ixMCARB_DRAM_TIMING_TABLE_13                                            0x3f930
++#define ixMCARB_DRAM_TIMING_TABLE_14                                            0x3f934
++#define ixMCARB_DRAM_TIMING_TABLE_15                                            0x3f938
++#define ixMCARB_DRAM_TIMING_TABLE_16                                            0x3f93c
++#define ixMCARB_DRAM_TIMING_TABLE_17                                            0x3f940
++#define ixMCARB_DRAM_TIMING_TABLE_18                                            0x3f944
++#define ixMCARB_DRAM_TIMING_TABLE_19                                            0x3f948
++#define ixMCARB_DRAM_TIMING_TABLE_20                                            0x3f94c
++#define ixMCARB_DRAM_TIMING_TABLE_21                                            0x3f950
++#define ixMCARB_DRAM_TIMING_TABLE_22                                            0x3f954
++#define ixMCARB_DRAM_TIMING_TABLE_23                                            0x3f958
++#define ixMCARB_DRAM_TIMING_TABLE_24                                            0x3f95c
++#define ixMCARB_DRAM_TIMING_TABLE_25                                            0x3f960
++#define ixMCARB_DRAM_TIMING_TABLE_26                                            0x3f964
++#define ixMCARB_DRAM_TIMING_TABLE_27                                            0x3f968
++#define ixMCARB_DRAM_TIMING_TABLE_28                                            0x3f96c
++#define ixMCARB_DRAM_TIMING_TABLE_29                                            0x3f970
++#define ixMCARB_DRAM_TIMING_TABLE_30                                            0x3f974
++#define ixMCARB_DRAM_TIMING_TABLE_31                                            0x3f978
++#define ixMCARB_DRAM_TIMING_TABLE_32                                            0x3f97c
++#define ixMCARB_DRAM_TIMING_TABLE_33                                            0x3f980
++#define ixMCARB_DRAM_TIMING_TABLE_34                                            0x3f984
++#define ixMCARB_DRAM_TIMING_TABLE_35                                            0x3f988
++#define ixMCARB_DRAM_TIMING_TABLE_36                                            0x3f98c
++#define ixMCARB_DRAM_TIMING_TABLE_37                                            0x3f990
++#define ixMCARB_DRAM_TIMING_TABLE_38                                            0x3f994
++#define ixMCARB_DRAM_TIMING_TABLE_39                                            0x3f998
++#define ixMCARB_DRAM_TIMING_TABLE_40                                            0x3f99c
++#define ixMCARB_DRAM_TIMING_TABLE_41                                            0x3f9a0
++#define ixMCARB_DRAM_TIMING_TABLE_42                                            0x3f9a4
++#define ixMCARB_DRAM_TIMING_TABLE_43                                            0x3f9a8
++#define ixMCARB_DRAM_TIMING_TABLE_44                                            0x3f9ac
++#define ixMCARB_DRAM_TIMING_TABLE_45                                            0x3f9b0
++#define ixMCARB_DRAM_TIMING_TABLE_46                                            0x3f9b4
++#define ixMCARB_DRAM_TIMING_TABLE_47                                            0x3f9b8
++#define ixMCARB_DRAM_TIMING_TABLE_48                                            0x3f9bc
++#define ixMCARB_DRAM_TIMING_TABLE_49                                            0x3f9c0
++#define ixMCARB_DRAM_TIMING_TABLE_50                                            0x3f9c4
++#define ixMCARB_DRAM_TIMING_TABLE_51                                            0x3f9c8
++#define ixMCARB_DRAM_TIMING_TABLE_52                                            0x3f9cc
++#define ixMCARB_DRAM_TIMING_TABLE_53                                            0x3f9d0
++#define ixMCARB_DRAM_TIMING_TABLE_54                                            0x3f9d4
++#define ixMCARB_DRAM_TIMING_TABLE_55                                            0x3f9d8
++#define ixMCARB_DRAM_TIMING_TABLE_56                                            0x3f9dc
++#define ixMCARB_DRAM_TIMING_TABLE_57                                            0x3f9e0
++#define ixMCARB_DRAM_TIMING_TABLE_58                                            0x3f9e4
++#define ixMCARB_DRAM_TIMING_TABLE_59                                            0x3f9e8
++#define ixMCARB_DRAM_TIMING_TABLE_60                                            0x3f9ec
++#define ixMCARB_DRAM_TIMING_TABLE_61                                            0x3f9f0
++#define ixMCARB_DRAM_TIMING_TABLE_62                                            0x3f9f4
++#define ixMCARB_DRAM_TIMING_TABLE_63                                            0x3f9f8
++#define ixMCARB_DRAM_TIMING_TABLE_64                                            0x3f9fc
++#define ixMCARB_DRAM_TIMING_TABLE_65                                            0x3fa00
++#define ixMCARB_DRAM_TIMING_TABLE_66                                            0x3fa04
++#define ixMCARB_DRAM_TIMING_TABLE_67                                            0x3fa08
++#define ixMCARB_DRAM_TIMING_TABLE_68                                            0x3fa0c
++#define ixMCARB_DRAM_TIMING_TABLE_69                                            0x3fa10
++#define ixMCARB_DRAM_TIMING_TABLE_70                                            0x3fa14
++#define ixMCARB_DRAM_TIMING_TABLE_71                                            0x3fa18
++#define ixMCARB_DRAM_TIMING_TABLE_72                                            0x3fa1c
++#define ixMCARB_DRAM_TIMING_TABLE_73                                            0x3fa20
++#define ixMCARB_DRAM_TIMING_TABLE_74                                            0x3fa24
++#define ixMCARB_DRAM_TIMING_TABLE_75                                            0x3fa28
++#define ixMCARB_DRAM_TIMING_TABLE_76                                            0x3fa2c
++#define ixMCARB_DRAM_TIMING_TABLE_77                                            0x3fa30
++#define ixMCARB_DRAM_TIMING_TABLE_78                                            0x3fa34
++#define ixMCARB_DRAM_TIMING_TABLE_79                                            0x3fa38
++#define ixMCARB_DRAM_TIMING_TABLE_80                                            0x3fa3c
++#define ixMCARB_DRAM_TIMING_TABLE_81                                            0x3fa40
++#define ixMCARB_DRAM_TIMING_TABLE_82                                            0x3fa44
++#define ixMCARB_DRAM_TIMING_TABLE_83                                            0x3fa48
++#define ixMCARB_DRAM_TIMING_TABLE_84                                            0x3fa4c
++#define ixMCARB_DRAM_TIMING_TABLE_85                                            0x3fa50
++#define ixMCARB_DRAM_TIMING_TABLE_86                                            0x3fa54
++#define ixMCARB_DRAM_TIMING_TABLE_87                                            0x3fa58
++#define ixMCARB_DRAM_TIMING_TABLE_88                                            0x3fa5c
++#define ixMCARB_DRAM_TIMING_TABLE_89                                            0x3fa60
++#define ixMCARB_DRAM_TIMING_TABLE_90                                            0x3fa64
++#define ixMCARB_DRAM_TIMING_TABLE_91                                            0x3fa68
++#define ixMCARB_DRAM_TIMING_TABLE_92                                            0x3fa6c
++#define ixMCARB_DRAM_TIMING_TABLE_93                                            0x3fa70
++#define ixMCARB_DRAM_TIMING_TABLE_94                                            0x3fa74
++#define ixMCARB_DRAM_TIMING_TABLE_95                                            0x3fa78
++#define ixMCARB_DRAM_TIMING_TABLE_96                                            0x3fa7c
++#define ixMCARB_DRAM_TIMING_TABLE_97                                            0x3fa80
++#define ixMCARB_DRAM_TIMING_TABLE_98                                            0x3fa84
++#define ixMCARB_DRAM_TIMING_TABLE_99                                            0x3fa88
++#define ixMCARB_DRAM_TIMING_TABLE_100                                           0x3fa8c
++#define ixMCARB_DRAM_TIMING_TABLE_101                                           0x3fa90
++#define ixMCARB_DRAM_TIMING_TABLE_102                                           0x3fa94
++#define ixMCARB_DRAM_TIMING_TABLE_103                                           0x3fa98
++#define ixMCARB_DRAM_TIMING_TABLE_104                                           0x3fa9c
++#define ixMCARB_DRAM_TIMING_TABLE_105                                           0x3faa0
++#define ixMCARB_DRAM_TIMING_TABLE_106                                           0x3faa4
++#define ixMCARB_DRAM_TIMING_TABLE_107                                           0x3faa8
++#define ixMCARB_DRAM_TIMING_TABLE_108                                           0x3faac
++#define ixMCARB_DRAM_TIMING_TABLE_109                                           0x3fab0
++#define ixMCARB_DRAM_TIMING_TABLE_110                                           0x3fab4
++#define ixMCARB_DRAM_TIMING_TABLE_111                                           0x3fab8
++#define ixMCARB_DRAM_TIMING_TABLE_112                                           0x3fabc
++#define ixMCARB_DRAM_TIMING_TABLE_113                                           0x3fac0
++#define ixMCARB_DRAM_TIMING_TABLE_114                                           0x3fac4
++#define ixMCARB_DRAM_TIMING_TABLE_115                                           0x3fac8
++#define ixMCARB_DRAM_TIMING_TABLE_116                                           0x3facc
++#define ixMCARB_DRAM_TIMING_TABLE_117                                           0x3fad0
++#define ixMCARB_DRAM_TIMING_TABLE_118                                           0x3fad4
++#define ixMCARB_DRAM_TIMING_TABLE_119                                           0x3fad8
++#define ixMCARB_DRAM_TIMING_TABLE_120                                           0x3fadc
++#define ixMCARB_DRAM_TIMING_TABLE_121                                           0x3fae0
++#define ixMCARB_DRAM_TIMING_TABLE_122                                           0x3fae4
++#define ixMCARB_DRAM_TIMING_TABLE_123                                           0x3fae8
++#define ixMCARB_DRAM_TIMING_TABLE_124                                           0x3faec
++#define ixMCARB_DRAM_TIMING_TABLE_125                                           0x3faf0
++#define ixMCARB_DRAM_TIMING_TABLE_126                                           0x3faf4
++#define ixMCARB_DRAM_TIMING_TABLE_127                                           0x3faf8
++#define ixMCARB_DRAM_TIMING_TABLE_128                                           0x3fafc
++#define ixMCARB_DRAM_TIMING_TABLE_129                                           0x3fb00
++#define ixMCARB_DRAM_TIMING_TABLE_130                                           0x3fb04
++#define ixMCARB_DRAM_TIMING_TABLE_131                                           0x3fb08
++#define ixMCARB_DRAM_TIMING_TABLE_132                                           0x3fb0c
++#define ixMCARB_DRAM_TIMING_TABLE_133                                           0x3fb10
++#define ixMCARB_DRAM_TIMING_TABLE_134                                           0x3fb14
++#define ixMCARB_DRAM_TIMING_TABLE_135                                           0x3fb18
++#define ixMCARB_DRAM_TIMING_TABLE_136                                           0x3fb1c
++#define ixMCARB_DRAM_TIMING_TABLE_137                                           0x3fb20
++#define ixMCARB_DRAM_TIMING_TABLE_138                                           0x3fb24
++#define ixMCARB_DRAM_TIMING_TABLE_139                                           0x3fb28
++#define ixMCARB_DRAM_TIMING_TABLE_140                                           0x3fb2c
++#define ixMCARB_DRAM_TIMING_TABLE_141                                           0x3fb30
++#define ixMCARB_DRAM_TIMING_TABLE_142                                           0x3fb34
++#define ixMCARB_DRAM_TIMING_TABLE_143                                           0x3fb38
++#define ixMCARB_DRAM_TIMING_TABLE_144                                           0x3fb3c
++#define ixMC_REGISTERS_TABLE_1                                                  0x3fb40
++#define ixMC_REGISTERS_TABLE_2                                                  0x3fb44
++#define ixMC_REGISTERS_TABLE_3                                                  0x3fb48
++#define ixMC_REGISTERS_TABLE_4                                                  0x3fb4c
++#define ixMC_REGISTERS_TABLE_5                                                  0x3fb50
++#define ixMC_REGISTERS_TABLE_6                                                  0x3fb54
++#define ixMC_REGISTERS_TABLE_7                                                  0x3fb58
++#define ixMC_REGISTERS_TABLE_8                                                  0x3fb5c
++#define ixMC_REGISTERS_TABLE_9                                                  0x3fb60
++#define ixMC_REGISTERS_TABLE_10                                                 0x3fb64
++#define ixMC_REGISTERS_TABLE_11                                                 0x3fb68
++#define ixMC_REGISTERS_TABLE_12                                                 0x3fb6c
++#define ixMC_REGISTERS_TABLE_13                                                 0x3fb70
++#define ixMC_REGISTERS_TABLE_14                                                 0x3fb74
++#define ixMC_REGISTERS_TABLE_15                                                 0x3fb78
++#define ixMC_REGISTERS_TABLE_16                                                 0x3fb7c
++#define ixMC_REGISTERS_TABLE_17                                                 0x3fb80
++#define ixMC_REGISTERS_TABLE_18                                                 0x3fb84
++#define ixMC_REGISTERS_TABLE_19                                                 0x3fb88
++#define ixMC_REGISTERS_TABLE_20                                                 0x3fb8c
++#define ixMC_REGISTERS_TABLE_21                                                 0x3fb90
++#define ixMC_REGISTERS_TABLE_22                                                 0x3fb94
++#define ixMC_REGISTERS_TABLE_23                                                 0x3fb98
++#define ixMC_REGISTERS_TABLE_24                                                 0x3fb9c
++#define ixMC_REGISTERS_TABLE_25                                                 0x3fba0
++#define ixMC_REGISTERS_TABLE_26                                                 0x3fba4
++#define ixMC_REGISTERS_TABLE_27                                                 0x3fba8
++#define ixMC_REGISTERS_TABLE_28                                                 0x3fbac
++#define ixMC_REGISTERS_TABLE_29                                                 0x3fbb0
++#define ixMC_REGISTERS_TABLE_30                                                 0x3fbb4
++#define ixMC_REGISTERS_TABLE_31                                                 0x3fbb8
++#define ixMC_REGISTERS_TABLE_32                                                 0x3fbbc
++#define ixMC_REGISTERS_TABLE_33                                                 0x3fbc0
++#define ixMC_REGISTERS_TABLE_34                                                 0x3fbc4
++#define ixMC_REGISTERS_TABLE_35                                                 0x3fbc8
++#define ixMC_REGISTERS_TABLE_36                                                 0x3fbcc
++#define ixMC_REGISTERS_TABLE_37                                                 0x3fbd0
++#define ixMC_REGISTERS_TABLE_38                                                 0x3fbd4
++#define ixMC_REGISTERS_TABLE_39                                                 0x3fbd8
++#define ixMC_REGISTERS_TABLE_40                                                 0x3fbdc
++#define ixMC_REGISTERS_TABLE_41                                                 0x3fbe0
++#define ixMC_REGISTERS_TABLE_42                                                 0x3fbe4
++#define ixMC_REGISTERS_TABLE_43                                                 0x3fbe8
++#define ixMC_REGISTERS_TABLE_44                                                 0x3fbec
++#define ixMC_REGISTERS_TABLE_45                                                 0x3fbf0
++#define ixMC_REGISTERS_TABLE_46                                                 0x3fbf4
++#define ixMC_REGISTERS_TABLE_47                                                 0x3fbf8
++#define ixMC_REGISTERS_TABLE_48                                                 0x3fbfc
++#define ixMC_REGISTERS_TABLE_49                                                 0x3fc00
++#define ixMC_REGISTERS_TABLE_50                                                 0x3fc04
++#define ixMC_REGISTERS_TABLE_51                                                 0x3fc08
++#define ixMC_REGISTERS_TABLE_52                                                 0x3fc0c
++#define ixMC_REGISTERS_TABLE_53                                                 0x3fc10
++#define ixMC_REGISTERS_TABLE_54                                                 0x3fc14
++#define ixMC_REGISTERS_TABLE_55                                                 0x3fc18
++#define ixMC_REGISTERS_TABLE_56                                                 0x3fc1c
++#define ixMC_REGISTERS_TABLE_57                                                 0x3fc20
++#define ixMC_REGISTERS_TABLE_58                                                 0x3fc24
++#define ixMC_REGISTERS_TABLE_59                                                 0x3fc28
++#define ixMC_REGISTERS_TABLE_60                                                 0x3fc2c
++#define ixMC_REGISTERS_TABLE_61                                                 0x3fc30
++#define ixMC_REGISTERS_TABLE_62                                                 0x3fc34
++#define ixMC_REGISTERS_TABLE_63                                                 0x3fc38
++#define ixMC_REGISTERS_TABLE_64                                                 0x3fc3c
++#define ixMC_REGISTERS_TABLE_65                                                 0x3fc40
++#define ixMC_REGISTERS_TABLE_66                                                 0x3fc44
++#define ixMC_REGISTERS_TABLE_67                                                 0x3fc48
++#define ixMC_REGISTERS_TABLE_68                                                 0x3fc4c
++#define ixMC_REGISTERS_TABLE_69                                                 0x3fc50
++#define ixMC_REGISTERS_TABLE_70                                                 0x3fc54
++#define ixMC_REGISTERS_TABLE_71                                                 0x3fc58
++#define ixMC_REGISTERS_TABLE_72                                                 0x3fc5c
++#define ixMC_REGISTERS_TABLE_73                                                 0x3fc60
++#define ixMC_REGISTERS_TABLE_74                                                 0x3fc64
++#define ixMC_REGISTERS_TABLE_75                                                 0x3fc68
++#define ixMC_REGISTERS_TABLE_76                                                 0x3fc6c
++#define ixMC_REGISTERS_TABLE_77                                                 0x3fc70
++#define ixMC_REGISTERS_TABLE_78                                                 0x3fc74
++#define ixMC_REGISTERS_TABLE_79                                                 0x3fc78
++#define ixMC_REGISTERS_TABLE_80                                                 0x3fc7c
++#define ixMC_REGISTERS_TABLE_81                                                 0x3fc80
++#define ixMC_REGISTERS_TABLE_82                                                 0x3fc84
++#define ixMC_REGISTERS_TABLE_83                                                 0x3fc88
++#define ixMC_REGISTERS_TABLE_84                                                 0x3fc8c
++#define ixMC_REGISTERS_TABLE_85                                                 0x3fc90
++#define ixMC_REGISTERS_TABLE_86                                                 0x3fc94
++#define ixMC_REGISTERS_TABLE_87                                                 0x3fc98
++#define ixMC_REGISTERS_TABLE_88                                                 0x3fc9c
++#define ixMC_REGISTERS_TABLE_89                                                 0x3fca0
++#define ixMC_REGISTERS_TABLE_90                                                 0x3fca4
++#define ixMC_REGISTERS_TABLE_91                                                 0x3fca8
++#define ixMC_REGISTERS_TABLE_92                                                 0x3fcac
++#define ixMC_REGISTERS_TABLE_93                                                 0x3fcb0
++#define ixMC_REGISTERS_TABLE_94                                                 0x3fcb4
++#define ixMC_REGISTERS_TABLE_95                                                 0x3fcb8
++#define ixMC_REGISTERS_TABLE_96                                                 0x3fcbc
++#define ixMC_REGISTERS_TABLE_97                                                 0x3fcc0
++#define ixMC_REGISTERS_TABLE_98                                                 0x3fcc4
++#define ixMC_REGISTERS_TABLE_99                                                 0x3fcc8
++#define ixMC_REGISTERS_TABLE_100                                                0x3fccc
++#define ixMC_REGISTERS_TABLE_101                                                0x3fcd0
++#define ixMC_REGISTERS_TABLE_102                                                0x3fcd4
++#define ixMC_REGISTERS_TABLE_103                                                0x3fcd8
++#define ixMC_REGISTERS_TABLE_104                                                0x3fcdc
++#define ixMC_REGISTERS_TABLE_105                                                0x3fce0
++#define ixMC_REGISTERS_TABLE_106                                                0x3fce4
++#define ixMC_REGISTERS_TABLE_107                                                0x3fce8
++#define ixMC_REGISTERS_TABLE_108                                                0x3fcec
++#define ixMC_REGISTERS_TABLE_109                                                0x3fcf0
++#define ixMC_REGISTERS_TABLE_110                                                0x3fcf4
++#define ixMC_REGISTERS_TABLE_111                                                0x3fcf8
++#define ixMC_REGISTERS_TABLE_112                                                0x3fcfc
++#define ixMC_REGISTERS_TABLE_113                                                0x3fd00
++#define ixFAN_TABLE_1                                                           0x3fd04
++#define ixFAN_TABLE_2                                                           0x3fd08
++#define ixFAN_TABLE_3                                                           0x3fd0c
++#define ixFAN_TABLE_4                                                           0x3fd10
++#define ixFAN_TABLE_5                                                           0x3fd14
++#define ixFAN_TABLE_6                                                           0x3fd18
++#define ixFAN_TABLE_7                                                           0x3fd1c
++#define ixFAN_TABLE_8                                                           0x3fd20
++#define ixFAN_TABLE_9                                                           0x3fd24
++#define ixSOFT_REGISTERS_TABLE_1                                                0x3fd28
++#define ixSOFT_REGISTERS_TABLE_2                                                0x3fd2c
++#define ixSOFT_REGISTERS_TABLE_3                                                0x3fd30
++#define ixSOFT_REGISTERS_TABLE_4                                                0x3fd34
++#define ixSOFT_REGISTERS_TABLE_5                                                0x3fd38
++#define ixSOFT_REGISTERS_TABLE_6                                                0x3fd3c
++#define ixSOFT_REGISTERS_TABLE_7                                                0x3fd40
++#define ixSOFT_REGISTERS_TABLE_8                                                0x3fd44
++#define ixSOFT_REGISTERS_TABLE_9                                                0x3fd48
++#define ixSOFT_REGISTERS_TABLE_10                                               0x3fd4c
++#define ixSOFT_REGISTERS_TABLE_11                                               0x3fd50
++#define ixSOFT_REGISTERS_TABLE_12                                               0x3fd54
++#define ixSOFT_REGISTERS_TABLE_13                                               0x3fd58
++#define ixSOFT_REGISTERS_TABLE_14                                               0x3fd5c
++#define ixSOFT_REGISTERS_TABLE_15                                               0x3fd60
++#define ixSOFT_REGISTERS_TABLE_16                                               0x3fd64
++#define ixSOFT_REGISTERS_TABLE_17                                               0x3fd68
++#define ixSOFT_REGISTERS_TABLE_18                                               0x3fd6c
++#define ixSOFT_REGISTERS_TABLE_19                                               0x3fd70
++#define ixSOFT_REGISTERS_TABLE_20                                               0x3fd74
++#define ixSOFT_REGISTERS_TABLE_21                                               0x3fd78
++#define ixSOFT_REGISTERS_TABLE_22                                               0x3fd7c
++#define ixSOFT_REGISTERS_TABLE_23                                               0x3fd80
++#define ixSOFT_REGISTERS_TABLE_24                                               0x3fd84
++#define ixSOFT_REGISTERS_TABLE_25                                               0x3fd88
++#define ixSOFT_REGISTERS_TABLE_26                                               0x3fd8c
++#define ixSOFT_REGISTERS_TABLE_27                                               0x3fd90
++#define ixSOFT_REGISTERS_TABLE_28                                               0x3fd94
++#define ixSOFT_REGISTERS_TABLE_29                                               0x3fd98
++#define ixSOFT_REGISTERS_TABLE_30                                               0x3fd9c
++#define ixPM_FUSES_1                                                            0x3fda0
++#define ixPM_FUSES_2                                                            0x3fda4
++#define ixPM_FUSES_3                                                            0x3fda8
++#define ixPM_FUSES_4                                                            0x3fdac
++#define ixPM_FUSES_5                                                            0x3fdb0
++#define ixPM_FUSES_6                                                            0x3fdb4
++#define ixPM_FUSES_7                                                            0x3fdb8
++#define ixPM_FUSES_8                                                            0x3fdbc
++#define ixPM_FUSES_9                                                            0x3fdc0
++#define ixPM_FUSES_10                                                           0x3fdc4
++#define ixPM_FUSES_11                                                           0x3fdc8
++#define ixPM_FUSES_12                                                           0x3fdcc
++#define ixPM_FUSES_13                                                           0x3fdd0
++#define ixPM_FUSES_14                                                           0x3fdd4
++#define ixPM_FUSES_15                                                           0x3fdd8
++#define ixPM_FUSES_16                                                           0x3fddc
++#define ixPM_FUSES_17                                                           0x3fde0
++#define ixPM_FUSES_18                                                           0x3fde4
++#define ixPM_FUSES_19                                                           0x3fde8
++#define ixSMU_PM_STATUS_0                                                       0x3fe00
++#define ixSMU_PM_STATUS_1                                                       0x3fe04
++#define ixSMU_PM_STATUS_2                                                       0x3fe08
++#define ixSMU_PM_STATUS_3                                                       0x3fe0c
++#define ixSMU_PM_STATUS_4                                                       0x3fe10
++#define ixSMU_PM_STATUS_5                                                       0x3fe14
++#define ixSMU_PM_STATUS_6                                                       0x3fe18
++#define ixSMU_PM_STATUS_7                                                       0x3fe1c
++#define ixSMU_PM_STATUS_8                                                       0x3fe20
++#define ixSMU_PM_STATUS_9                                                       0x3fe24
++#define ixSMU_PM_STATUS_10                                                      0x3fe28
++#define ixSMU_PM_STATUS_11                                                      0x3fe2c
++#define ixSMU_PM_STATUS_12                                                      0x3fe30
++#define ixSMU_PM_STATUS_13                                                      0x3fe34
++#define ixSMU_PM_STATUS_14                                                      0x3fe38
++#define ixSMU_PM_STATUS_15                                                      0x3fe3c
++#define ixSMU_PM_STATUS_16                                                      0x3fe40
++#define ixSMU_PM_STATUS_17                                                      0x3fe44
++#define ixSMU_PM_STATUS_18                                                      0x3fe48
++#define ixSMU_PM_STATUS_19                                                      0x3fe4c
++#define ixSMU_PM_STATUS_20                                                      0x3fe50
++#define ixSMU_PM_STATUS_21                                                      0x3fe54
++#define ixSMU_PM_STATUS_22                                                      0x3fe58
++#define ixSMU_PM_STATUS_23                                                      0x3fe5c
++#define ixSMU_PM_STATUS_24                                                      0x3fe60
++#define ixSMU_PM_STATUS_25                                                      0x3fe64
++#define ixSMU_PM_STATUS_26                                                      0x3fe68
++#define ixSMU_PM_STATUS_27                                                      0x3fe6c
++#define ixSMU_PM_STATUS_28                                                      0x3fe70
++#define ixSMU_PM_STATUS_29                                                      0x3fe74
++#define ixSMU_PM_STATUS_30                                                      0x3fe78
++#define ixSMU_PM_STATUS_31                                                      0x3fe7c
++#define ixSMU_PM_STATUS_32                                                      0x3fe80
++#define ixSMU_PM_STATUS_33                                                      0x3fe84
++#define ixSMU_PM_STATUS_34                                                      0x3fe88
++#define ixSMU_PM_STATUS_35                                                      0x3fe8c
++#define ixSMU_PM_STATUS_36                                                      0x3fe90
++#define ixSMU_PM_STATUS_37                                                      0x3fe94
++#define ixSMU_PM_STATUS_38                                                      0x3fe98
++#define ixSMU_PM_STATUS_39                                                      0x3fe9c
++#define ixSMU_PM_STATUS_40                                                      0x3fea0
++#define ixSMU_PM_STATUS_41                                                      0x3fea4
++#define ixSMU_PM_STATUS_42                                                      0x3fea8
++#define ixSMU_PM_STATUS_43                                                      0x3feac
++#define ixSMU_PM_STATUS_44                                                      0x3feb0
++#define ixSMU_PM_STATUS_45                                                      0x3feb4
++#define ixSMU_PM_STATUS_46                                                      0x3feb8
++#define ixSMU_PM_STATUS_47                                                      0x3febc
++#define ixSMU_PM_STATUS_48                                                      0x3fec0
++#define ixSMU_PM_STATUS_49                                                      0x3fec4
++#define ixSMU_PM_STATUS_50                                                      0x3fec8
++#define ixSMU_PM_STATUS_51                                                      0x3fecc
++#define ixSMU_PM_STATUS_52                                                      0x3fed0
++#define ixSMU_PM_STATUS_53                                                      0x3fed4
++#define ixSMU_PM_STATUS_54                                                      0x3fed8
++#define ixSMU_PM_STATUS_55                                                      0x3fedc
++#define ixSMU_PM_STATUS_56                                                      0x3fee0
++#define ixSMU_PM_STATUS_57                                                      0x3fee4
++#define ixSMU_PM_STATUS_58                                                      0x3fee8
++#define ixSMU_PM_STATUS_59                                                      0x3feec
++#define ixSMU_PM_STATUS_60                                                      0x3fef0
++#define ixSMU_PM_STATUS_61                                                      0x3fef4
++#define ixSMU_PM_STATUS_62                                                      0x3fef8
++#define ixSMU_PM_STATUS_63                                                      0x3fefc
++#define ixSMU_PM_STATUS_64                                                      0x3ff00
++#define ixSMU_PM_STATUS_65                                                      0x3ff04
++#define ixSMU_PM_STATUS_66                                                      0x3ff08
++#define ixSMU_PM_STATUS_67                                                      0x3ff0c
++#define ixSMU_PM_STATUS_68                                                      0x3ff10
++#define ixSMU_PM_STATUS_69                                                      0x3ff14
++#define ixSMU_PM_STATUS_70                                                      0x3ff18
++#define ixSMU_PM_STATUS_71                                                      0x3ff1c
++#define ixSMU_PM_STATUS_72                                                      0x3ff20
++#define ixSMU_PM_STATUS_73                                                      0x3ff24
++#define ixSMU_PM_STATUS_74                                                      0x3ff28
++#define ixSMU_PM_STATUS_75                                                      0x3ff2c
++#define ixSMU_PM_STATUS_76                                                      0x3ff30
++#define ixSMU_PM_STATUS_77                                                      0x3ff34
++#define ixSMU_PM_STATUS_78                                                      0x3ff38
++#define ixSMU_PM_STATUS_79                                                      0x3ff3c
++#define ixSMU_PM_STATUS_80                                                      0x3ff40
++#define ixSMU_PM_STATUS_81                                                      0x3ff44
++#define ixSMU_PM_STATUS_82                                                      0x3ff48
++#define ixSMU_PM_STATUS_83                                                      0x3ff4c
++#define ixSMU_PM_STATUS_84                                                      0x3ff50
++#define ixSMU_PM_STATUS_85                                                      0x3ff54
++#define ixSMU_PM_STATUS_86                                                      0x3ff58
++#define ixSMU_PM_STATUS_87                                                      0x3ff5c
++#define ixSMU_PM_STATUS_88                                                      0x3ff60
++#define ixSMU_PM_STATUS_89                                                      0x3ff64
++#define ixSMU_PM_STATUS_90                                                      0x3ff68
++#define ixSMU_PM_STATUS_91                                                      0x3ff6c
++#define ixSMU_PM_STATUS_92                                                      0x3ff70
++#define ixSMU_PM_STATUS_93                                                      0x3ff74
++#define ixSMU_PM_STATUS_94                                                      0x3ff78
++#define ixSMU_PM_STATUS_95                                                      0x3ff7c
++#define ixSMU_PM_STATUS_96                                                      0x3ff80
++#define ixSMU_PM_STATUS_97                                                      0x3ff84
++#define ixSMU_PM_STATUS_98                                                      0x3ff88
++#define ixSMU_PM_STATUS_99                                                      0x3ff8c
++#define ixSMU_PM_STATUS_100                                                     0x3ff90
++#define ixSMU_PM_STATUS_101                                                     0x3ff94
++#define ixSMU_PM_STATUS_102                                                     0x3ff98
++#define ixSMU_PM_STATUS_103                                                     0x3ff9c
++#define ixSMU_PM_STATUS_104                                                     0x3ffa0
++#define ixSMU_PM_STATUS_105                                                     0x3ffa4
++#define ixSMU_PM_STATUS_106                                                     0x3ffa8
++#define ixSMU_PM_STATUS_107                                                     0x3ffac
++#define ixSMU_PM_STATUS_108                                                     0x3ffb0
++#define ixSMU_PM_STATUS_109                                                     0x3ffb4
++#define ixSMU_PM_STATUS_110                                                     0x3ffb8
++#define ixSMU_PM_STATUS_111                                                     0x3ffbc
++#define ixSMU_PM_STATUS_112                                                     0x3ffc0
++#define ixSMU_PM_STATUS_113                                                     0x3ffc4
++#define ixSMU_PM_STATUS_114                                                     0x3ffc8
++#define ixSMU_PM_STATUS_115                                                     0x3ffcc
++#define ixSMU_PM_STATUS_116                                                     0x3ffd0
++#define ixSMU_PM_STATUS_117                                                     0x3ffd4
++#define ixSMU_PM_STATUS_118                                                     0x3ffd8
++#define ixSMU_PM_STATUS_119                                                     0x3ffdc
++#define ixSMU_PM_STATUS_120                                                     0x3ffe0
++#define ixSMU_PM_STATUS_121                                                     0x3ffe4
++#define ixSMU_PM_STATUS_122                                                     0x3ffe8
++#define ixSMU_PM_STATUS_123                                                     0x3ffec
++#define ixSMU_PM_STATUS_124                                                     0x3fff0
++#define ixSMU_PM_STATUS_125                                                     0x3fff4
++#define ixSMU_PM_STATUS_126                                                     0x3fff8
++#define ixSMU_PM_STATUS_127                                                     0x3fffc
++#define ixCG_THERMAL_INT_ENA                                                    0xc2100024
++#define ixCG_THERMAL_INT_CTRL                                                   0xc2100028
++#define ixCG_THERMAL_INT_STATUS                                                 0xc210002c
++#define ixCG_THERMAL_CTRL                                                       0xc0300004
++#define ixCG_THERMAL_STATUS                                                     0xc0300008
++#define ixCG_THERMAL_INT                                                        0xc030000c
++#define ixCG_MULT_THERMAL_CTRL                                                  0xc0300010
++#define ixCG_MULT_THERMAL_STATUS                                                0xc0300014
++#define ixCG_FDO_CTRL0                                                          0xc0300064
++#define ixCG_FDO_CTRL1                                                          0xc0300068
++#define ixCG_FDO_CTRL2                                                          0xc030006c
++#define ixCG_TACH_CTRL                                                          0xc0300070
++#define ixCG_TACH_STATUS                                                        0xc0300074
++#define ixCC_THM_STRAPS0                                                        0xc0300080
++#define ixTHM_TMON0_RDIL0_DATA                                                  0xc0300100
++#define ixTHM_TMON0_RDIL1_DATA                                                  0xc0300104
++#define ixTHM_TMON0_RDIL2_DATA                                                  0xc0300108
++#define ixTHM_TMON0_RDIL3_DATA                                                  0xc030010c
++#define ixTHM_TMON0_RDIL4_DATA                                                  0xc0300110
++#define ixTHM_TMON0_RDIL5_DATA                                                  0xc0300114
++#define ixTHM_TMON0_RDIL6_DATA                                                  0xc0300118
++#define ixTHM_TMON0_RDIL7_DATA                                                  0xc030011c
++#define ixTHM_TMON0_RDIL8_DATA                                                  0xc0300120
++#define ixTHM_TMON0_RDIL9_DATA                                                  0xc0300124
++#define ixTHM_TMON0_RDIL10_DATA                                                 0xc0300128
++#define ixTHM_TMON0_RDIL11_DATA                                                 0xc030012c
++#define ixTHM_TMON0_RDIL12_DATA                                                 0xc0300130
++#define ixTHM_TMON0_RDIL13_DATA                                                 0xc0300134
++#define ixTHM_TMON0_RDIL14_DATA                                                 0xc0300138
++#define ixTHM_TMON0_RDIL15_DATA                                                 0xc030013c
++#define ixTHM_TMON0_RDIR0_DATA                                                  0xc0300140
++#define ixTHM_TMON0_RDIR1_DATA                                                  0xc0300144
++#define ixTHM_TMON0_RDIR2_DATA                                                  0xc0300148
++#define ixTHM_TMON0_RDIR3_DATA                                                  0xc030014c
++#define ixTHM_TMON0_RDIR4_DATA                                                  0xc0300150
++#define ixTHM_TMON0_RDIR5_DATA                                                  0xc0300154
++#define ixTHM_TMON0_RDIR6_DATA                                                  0xc0300158
++#define ixTHM_TMON0_RDIR7_DATA                                                  0xc030015c
++#define ixTHM_TMON0_RDIR8_DATA                                                  0xc0300160
++#define ixTHM_TMON0_RDIR9_DATA                                                  0xc0300164
++#define ixTHM_TMON0_RDIR10_DATA                                                 0xc0300168
++#define ixTHM_TMON0_RDIR11_DATA                                                 0xc030016c
++#define ixTHM_TMON0_RDIR12_DATA                                                 0xc0300170
++#define ixTHM_TMON0_RDIR13_DATA                                                 0xc0300174
++#define ixTHM_TMON0_RDIR14_DATA                                                 0xc0300178
++#define ixTHM_TMON0_RDIR15_DATA                                                 0xc030017c
++#define ixTHM_TMON0_INT_DATA                                                    0xc0300300
++#define ixTHM_TMON0_DEBUG                                                       0xc0300310
++#define ixGENERAL_PWRMGT                                                        0xc0200000
++#define ixCNB_PWRMGT_CNTL                                                       0xc0200004
++#define ixSCLK_PWRMGT_CNTL                                                      0xc0200008
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xc0200014
++#define ixCG_FREQ_TRAN_VOTING_0                                                 0xc02001a8
++#define ixCG_FREQ_TRAN_VOTING_1                                                 0xc02001ac
++#define ixCG_FREQ_TRAN_VOTING_2                                                 0xc02001b0
++#define ixCG_FREQ_TRAN_VOTING_3                                                 0xc02001b4
++#define ixCG_FREQ_TRAN_VOTING_4                                                 0xc02001b8
++#define ixCG_FREQ_TRAN_VOTING_5                                                 0xc02001bc
++#define ixCG_FREQ_TRAN_VOTING_6                                                 0xc02001c0
++#define ixCG_FREQ_TRAN_VOTING_7                                                 0xc02001c4
++#define ixPLL_TEST_CNTL                                                         0xc020003c
++#define ixCG_STATIC_SCREEN_PARAMETER                                            0xc0200044
++#define ixCG_DISPLAY_GAP_CNTL                                                   0xc0200060
++#define ixCG_DISPLAY_GAP_CNTL2                                                  0xc0200230
++#define ixCG_ACPI_CNTL                                                          0xc0200064
++#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xc0200080
++#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xc0200084
++#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xc020009c
++#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xc0200088
++#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xc020008c
++#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xc0200310
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xc02000f0
++#define ixCG_ULV_PARAMETER                                                      0xc020015c
++#define ixSCLK_MIN_DIV                                                          0xc0200308
++#define ixLCAC_SX0_CNTL                                                         0xc0400d00
++#define ixLCAC_SX0_OVR_SEL                                                      0xc0400d04
++#define ixLCAC_SX0_OVR_VAL                                                      0xc0400d08
++#define ixLCAC_MC0_CNTL                                                         0xc0400d30
++#define ixLCAC_MC0_OVR_SEL                                                      0xc0400d34
++#define ixLCAC_MC0_OVR_VAL                                                      0xc0400d38
++#define ixLCAC_MC1_CNTL                                                         0xc0400d3c
++#define ixLCAC_MC1_OVR_SEL                                                      0xc0400d40
++#define ixLCAC_MC1_OVR_VAL                                                      0xc0400d44
++#define ixLCAC_MC2_CNTL                                                         0xc0400d48
++#define ixLCAC_MC2_OVR_SEL                                                      0xc0400d4c
++#define ixLCAC_MC2_OVR_VAL                                                      0xc0400d50
++#define ixLCAC_MC3_CNTL                                                         0xc0400d54
++#define ixLCAC_MC3_OVR_SEL                                                      0xc0400d58
++#define ixLCAC_MC3_OVR_VAL                                                      0xc0400d5c
++#define ixLCAC_CPL_CNTL                                                         0xc0400d80
++#define ixLCAC_CPL_OVR_SEL                                                      0xc0400d84
++#define ixLCAC_CPL_OVR_VAL                                                      0xc0400d88
++#define mmROM_SMC_IND_INDEX                                                     0x80
++#define mmROM0_ROM_SMC_IND_INDEX                                                0x80
++#define mmROM1_ROM_SMC_IND_INDEX                                                0x82
++#define mmROM2_ROM_SMC_IND_INDEX                                                0x84
++#define mmROM3_ROM_SMC_IND_INDEX                                                0x86
++#define mmROM_SMC_IND_DATA                                                      0x81
++#define mmROM0_ROM_SMC_IND_DATA                                                 0x81
++#define mmROM1_ROM_SMC_IND_DATA                                                 0x83
++#define mmROM2_ROM_SMC_IND_DATA                                                 0x85
++#define mmROM3_ROM_SMC_IND_DATA                                                 0x87
++#define ixROM_CNTL                                                              0xc0600000
++#define ixPAGE_MIRROR_CNTL                                                      0xc0600004
++#define ixROM_STATUS                                                            0xc0600008
++#define ixCGTT_ROM_CLK_CTRL0                                                    0xc060000c
++#define ixROM_INDEX                                                             0xc0600010
++#define ixROM_DATA                                                              0xc0600014
++#define ixROM_START                                                             0xc0600018
++#define ixROM_SW_CNTL                                                           0xc060001c
++#define ixROM_SW_STATUS                                                         0xc0600020
++#define ixROM_SW_COMMAND                                                        0xc0600024
++#define ixROM_SW_DATA_1                                                         0xc0600028
++#define ixROM_SW_DATA_2                                                         0xc060002c
++#define ixROM_SW_DATA_3                                                         0xc0600030
++#define ixROM_SW_DATA_4                                                         0xc0600034
++#define ixROM_SW_DATA_5                                                         0xc0600038
++#define ixROM_SW_DATA_6                                                         0xc060003c
++#define ixROM_SW_DATA_7                                                         0xc0600040
++#define ixROM_SW_DATA_8                                                         0xc0600044
++#define ixROM_SW_DATA_9                                                         0xc0600048
++#define ixROM_SW_DATA_10                                                        0xc060004c
++#define ixROM_SW_DATA_11                                                        0xc0600050
++#define ixROM_SW_DATA_12                                                        0xc0600054
++#define ixROM_SW_DATA_13                                                        0xc0600058
++#define ixROM_SW_DATA_14                                                        0xc060005c
++#define ixROM_SW_DATA_15                                                        0xc0600060
++#define ixROM_SW_DATA_16                                                        0xc0600064
++#define ixROM_SW_DATA_17                                                        0xc0600068
++#define ixROM_SW_DATA_18                                                        0xc060006c
++#define ixROM_SW_DATA_19                                                        0xc0600070
++#define ixROM_SW_DATA_20                                                        0xc0600074
++#define ixROM_SW_DATA_21                                                        0xc0600078
++#define ixROM_SW_DATA_22                                                        0xc060007c
++#define ixROM_SW_DATA_23                                                        0xc0600080
++#define ixROM_SW_DATA_24                                                        0xc0600084
++#define ixROM_SW_DATA_25                                                        0xc0600088
++#define ixROM_SW_DATA_26                                                        0xc060008c
++#define ixROM_SW_DATA_27                                                        0xc0600090
++#define ixROM_SW_DATA_28                                                        0xc0600094
++#define ixROM_SW_DATA_29                                                        0xc0600098
++#define ixROM_SW_DATA_30                                                        0xc060009c
++#define ixROM_SW_DATA_31                                                        0xc06000a0
++#define ixROM_SW_DATA_32                                                        0xc06000a4
++#define ixROM_SW_DATA_33                                                        0xc06000a8
++#define ixROM_SW_DATA_34                                                        0xc06000ac
++#define ixROM_SW_DATA_35                                                        0xc06000b0
++#define ixROM_SW_DATA_36                                                        0xc06000b4
++#define ixROM_SW_DATA_37                                                        0xc06000b8
++#define ixROM_SW_DATA_38                                                        0xc06000bc
++#define ixROM_SW_DATA_39                                                        0xc06000c0
++#define ixROM_SW_DATA_40                                                        0xc06000c4
++#define ixROM_SW_DATA_41                                                        0xc06000c8
++#define ixROM_SW_DATA_42                                                        0xc06000cc
++#define ixROM_SW_DATA_43                                                        0xc06000d0
++#define ixROM_SW_DATA_44                                                        0xc06000d4
++#define ixROM_SW_DATA_45                                                        0xc06000d8
++#define ixROM_SW_DATA_46                                                        0xc06000dc
++#define ixROM_SW_DATA_47                                                        0xc06000e0
++#define ixROM_SW_DATA_48                                                        0xc06000e4
++#define ixROM_SW_DATA_49                                                        0xc06000e8
++#define ixROM_SW_DATA_50                                                        0xc06000ec
++#define ixROM_SW_DATA_51                                                        0xc06000f0
++#define ixROM_SW_DATA_52                                                        0xc06000f4
++#define ixROM_SW_DATA_53                                                        0xc06000f8
++#define ixROM_SW_DATA_54                                                        0xc06000fc
++#define ixROM_SW_DATA_55                                                        0xc0600110
++#define ixROM_SW_DATA_56                                                        0xc0600114
++#define ixROM_SW_DATA_57                                                        0xc0600118
++#define ixROM_SW_DATA_58                                                        0xc060011c
++#define ixROM_SW_DATA_59                                                        0xc0600120
++#define ixROM_SW_DATA_60                                                        0xc0600124
++#define ixROM_SW_DATA_61                                                        0xc0600128
++#define ixROM_SW_DATA_62                                                        0xc060012c
++#define ixROM_SW_DATA_63                                                        0xc0600130
++#define ixROM_SW_DATA_64                                                        0xc0600134
++
++#endif /* SMU_7_0_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+new file mode 100644
+index 0000000..25882a4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+@@ -0,0 +1,5456 @@
++/*
++ * SMU_7_0_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_0_1_SH_MASK_H
++#define SMU_7_0_1_SH_MASK_H
++
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
++#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
++#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
++#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
++#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
++#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
++#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
++#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
++#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
++#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
++#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
++#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
++#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
++#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
++#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
++#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
++#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
++#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
++#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
++#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
++#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
++#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
++#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
++#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
++#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
++#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
++#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
++#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
++#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
++#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
++#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_0__SMC_RESP_MASK 0xffff
++#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_1__SMC_RESP_MASK 0xffff
++#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_2__SMC_RESP_MASK 0xffff
++#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_3__SMC_RESP_MASK 0xffff
++#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_4__SMC_RESP_MASK 0xffff
++#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_5__SMC_RESP_MASK 0xffff
++#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_6__SMC_RESP_MASK 0xffff
++#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_7__SMC_RESP_MASK 0xffff
++#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_8__SMC_RESP_MASK 0xffff
++#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_9__SMC_RESP_MASK 0xffff
++#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_10__SMC_RESP_MASK 0xffff
++#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_11__SMC_RESP_MASK 0xffff
++#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
++#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
++#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
++#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
++#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
++#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
++#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
++#define SMC_PC_C__smc_pc_c__SHIFT 0x0
++#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
++#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
++#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
++#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
++#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
++#define GPIOPAD_A__GPIO_A__SHIFT 0x0
++#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
++#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
++#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
++#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
++#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
++#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
++#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
++#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
++#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
++#define CG_FPS_CNT__FPS_CNT_MASK 0xff
++#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
++#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
++#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
++#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
++#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
++#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
++#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
++#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
++#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
++#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
++#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
++#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
++#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
++#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
++#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
++#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
++#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
++#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
++#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
++#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
++#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
++#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
++#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
++#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
++#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
++#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
++#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
++#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
++#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
++#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
++#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
++#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
++#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
++#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
++#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
++#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
++#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
++#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
++#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
++#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
++#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
++#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
++#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
++#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
++#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
++#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
++#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
++#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
++#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
++#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
++#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
++#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
++#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
++#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
++#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
++#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
++#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
++#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
++#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
++#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
++#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
++#define SMU_STATUS__SMU_DONE_MASK 0x1
++#define SMU_STATUS__SMU_DONE__SHIFT 0x0
++#define SMU_STATUS__SMU_PASS_MASK 0x2
++#define SMU_STATUS__SMU_PASS__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
++#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
++#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
++#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
++#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
++#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
++#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
++#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
++#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
++#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
++#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
++#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
++#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
++#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
++#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
++#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
++#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
++#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
++#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
++#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
++#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
++#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
++#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
++#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
++#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
++#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
++#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
++#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
++#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
++#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
++#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
++#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
++#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
++#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
++#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
++#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
++#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
++#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
++#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
++#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
++#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
++#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
++#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
++#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
++#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
++#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
++#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
++#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
++#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
++#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
++#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
++#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
++#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
++#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
++#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
++#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
++#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
++#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
++#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
++#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
++#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
++#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
++#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
++#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
++#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
++#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
++#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
++#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
++#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
++#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
++#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
++#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
++#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
++#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
++#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
++#define DPM_TABLE_69__padding2_MASK 0xff
++#define DPM_TABLE_69__padding2__SHIFT 0x0
++#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
++#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
++#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
++#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
++#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
++#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
++#define DPM_TABLE_70__Reserved_0_MASK 0xffffffff
++#define DPM_TABLE_70__Reserved_0__SHIFT 0x0
++#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
++#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
++#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
++#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
++#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
++#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
++#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
++#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
++#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
++#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
++#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
++#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_79__GraphicsLevel_0_padding1_1_MASK 0xff0000
++#define DPM_TABLE_79__GraphicsLevel_0_padding1_1__SHIFT 0x10
++#define DPM_TABLE_79__GraphicsLevel_0_padding1_0_MASK 0xff000000
++#define DPM_TABLE_79__GraphicsLevel_0_padding1_0__SHIFT 0x18
++#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
++#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
++#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
++#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
++#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
++#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
++#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_93__GraphicsLevel_1_padding1_1_MASK 0xff0000
++#define DPM_TABLE_93__GraphicsLevel_1_padding1_1__SHIFT 0x10
++#define DPM_TABLE_93__GraphicsLevel_1_padding1_0_MASK 0xff000000
++#define DPM_TABLE_93__GraphicsLevel_1_padding1_0__SHIFT 0x18
++#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
++#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
++#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
++#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
++#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
++#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
++#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_107__GraphicsLevel_2_padding1_1_MASK 0xff0000
++#define DPM_TABLE_107__GraphicsLevel_2_padding1_1__SHIFT 0x10
++#define DPM_TABLE_107__GraphicsLevel_2_padding1_0_MASK 0xff000000
++#define DPM_TABLE_107__GraphicsLevel_2_padding1_0__SHIFT 0x18
++#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
++#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
++#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
++#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
++#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
++#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
++#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_121__GraphicsLevel_3_padding1_1_MASK 0xff0000
++#define DPM_TABLE_121__GraphicsLevel_3_padding1_1__SHIFT 0x10
++#define DPM_TABLE_121__GraphicsLevel_3_padding1_0_MASK 0xff000000
++#define DPM_TABLE_121__GraphicsLevel_3_padding1_0__SHIFT 0x18
++#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
++#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
++#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
++#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
++#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
++#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
++#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_135__GraphicsLevel_4_padding1_1_MASK 0xff0000
++#define DPM_TABLE_135__GraphicsLevel_4_padding1_1__SHIFT 0x10
++#define DPM_TABLE_135__GraphicsLevel_4_padding1_0_MASK 0xff000000
++#define DPM_TABLE_135__GraphicsLevel_4_padding1_0__SHIFT 0x18
++#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
++#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
++#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
++#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
++#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
++#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
++#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
++#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
++#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
++#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
++#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_5_padding1_1_MASK 0xff0000
++#define DPM_TABLE_149__GraphicsLevel_5_padding1_1__SHIFT 0x10
++#define DPM_TABLE_149__GraphicsLevel_5_padding1_0_MASK 0xff000000
++#define DPM_TABLE_149__GraphicsLevel_5_padding1_0__SHIFT 0x18
++#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
++#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
++#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
++#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
++#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
++#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
++#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
++#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
++#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
++#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
++#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_6_padding1_1_MASK 0xff0000
++#define DPM_TABLE_163__GraphicsLevel_6_padding1_1__SHIFT 0x10
++#define DPM_TABLE_163__GraphicsLevel_6_padding1_0_MASK 0xff000000
++#define DPM_TABLE_163__GraphicsLevel_6_padding1_0__SHIFT 0x18
++#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
++#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
++#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
++#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
++#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
++#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
++#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
++#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
++#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
++#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
++#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_177__GraphicsLevel_7_padding1_1_MASK 0xff0000
++#define DPM_TABLE_177__GraphicsLevel_7_padding1_1__SHIFT 0x10
++#define DPM_TABLE_177__GraphicsLevel_7_padding1_0_MASK 0xff000000
++#define DPM_TABLE_177__GraphicsLevel_7_padding1_0__SHIFT 0x18
++#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
++#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
++#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
++#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
++#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
++#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
++#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
++#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
++#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
++#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
++#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
++#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
++#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
++#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
++#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
++#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
++#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
++#define DPM_TABLE_195__MemoryACPILevel_padding1_1_MASK 0xff
++#define DPM_TABLE_195__MemoryACPILevel_padding1_1__SHIFT 0x0
++#define DPM_TABLE_195__MemoryACPILevel_padding1_0_MASK 0xff00
++#define DPM_TABLE_195__MemoryACPILevel_padding1_0__SHIFT 0x8
++#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
++#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
++#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
++#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
++#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
++#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
++#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
++#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_213__MemoryLevel_0_padding1_1_MASK 0xff
++#define DPM_TABLE_213__MemoryLevel_0_padding1_1__SHIFT 0x0
++#define DPM_TABLE_213__MemoryLevel_0_padding1_0_MASK 0xff00
++#define DPM_TABLE_213__MemoryLevel_0_padding1_0__SHIFT 0x8
++#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
++#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
++#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
++#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
++#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
++#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
++#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
++#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_231__MemoryLevel_1_padding1_1_MASK 0xff
++#define DPM_TABLE_231__MemoryLevel_1_padding1_1__SHIFT 0x0
++#define DPM_TABLE_231__MemoryLevel_1_padding1_0_MASK 0xff00
++#define DPM_TABLE_231__MemoryLevel_1_padding1_0__SHIFT 0x8
++#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
++#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
++#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
++#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
++#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
++#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
++#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
++#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_249__MemoryLevel_2_padding1_1_MASK 0xff
++#define DPM_TABLE_249__MemoryLevel_2_padding1_1__SHIFT 0x0
++#define DPM_TABLE_249__MemoryLevel_2_padding1_0_MASK 0xff00
++#define DPM_TABLE_249__MemoryLevel_2_padding1_0__SHIFT 0x8
++#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
++#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
++#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
++#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
++#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
++#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
++#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
++#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_267__MemoryLevel_3_padding1_1_MASK 0xff
++#define DPM_TABLE_267__MemoryLevel_3_padding1_1__SHIFT 0x0
++#define DPM_TABLE_267__MemoryLevel_3_padding1_0_MASK 0xff00
++#define DPM_TABLE_267__MemoryLevel_3_padding1_0__SHIFT 0x8
++#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
++#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
++#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
++#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
++#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
++#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
++#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
++#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
++#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
++#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
++#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
++#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
++#define DPM_TABLE_285__MemoryLevel_4_padding1_1_MASK 0xff
++#define DPM_TABLE_285__MemoryLevel_4_padding1_1__SHIFT 0x0
++#define DPM_TABLE_285__MemoryLevel_4_padding1_0_MASK 0xff00
++#define DPM_TABLE_285__MemoryLevel_4_padding1_0__SHIFT 0x8
++#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
++#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
++#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
++#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
++#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
++#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
++#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
++#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
++#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
++#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
++#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
++#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
++#define DPM_TABLE_303__MemoryLevel_5_padding1_1_MASK 0xff
++#define DPM_TABLE_303__MemoryLevel_5_padding1_1__SHIFT 0x0
++#define DPM_TABLE_303__MemoryLevel_5_padding1_0_MASK 0xff00
++#define DPM_TABLE_303__MemoryLevel_5_padding1_0__SHIFT 0x8
++#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
++#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
++#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
++#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
++#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
++#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
++#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
++#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
++#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
++#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
++#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
++#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
++#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
++#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
++#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
++#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
++#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
++#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
++#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
++#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
++#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
++#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
++#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
++#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
++#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
++#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
++#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
++#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
++#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
++#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
++#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
++#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
++#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
++#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
++#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
++#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
++#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
++#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
++#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
++#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
++#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
++#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
++#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
++#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
++#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
++#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
++#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
++#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
++#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
++#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
++#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
++#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
++#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
++#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
++#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
++#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
++#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
++#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
++#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
++#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
++#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
++#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
++#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
++#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
++#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
++#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
++#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
++#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
++#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
++#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
++#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
++#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
++#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
++#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
++#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
++#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
++#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
++#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
++#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
++#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
++#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
++#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
++#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
++#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
++#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
++#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
++#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
++#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
++#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
++#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
++#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
++#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
++#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
++#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
++#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
++#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
++#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
++#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
++#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
++#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
++#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
++#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
++#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
++#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
++#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
++#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
++#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
++#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
++#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
++#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
++#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
++#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
++#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
++#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
++#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
++#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
++#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
++#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
++#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
++#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
++#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
++#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
++#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
++#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
++#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
++#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
++#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
++#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
++#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
++#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
++#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
++#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
++#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
++#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
++#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
++#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
++#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
++#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
++#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
++#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
++#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
++#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
++#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
++#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
++#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
++#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
++#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
++#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
++#define DPM_TABLE_443__Smio_0__SHIFT 0x0
++#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
++#define DPM_TABLE_444__Smio_1__SHIFT 0x0
++#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
++#define DPM_TABLE_445__Smio_2__SHIFT 0x0
++#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
++#define DPM_TABLE_446__Smio_3__SHIFT 0x0
++#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
++#define DPM_TABLE_447__Smio_4__SHIFT 0x0
++#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
++#define DPM_TABLE_448__Smio_5__SHIFT 0x0
++#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
++#define DPM_TABLE_449__Smio_6__SHIFT 0x0
++#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
++#define DPM_TABLE_450__Smio_7__SHIFT 0x0
++#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
++#define DPM_TABLE_451__Smio_8__SHIFT 0x0
++#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
++#define DPM_TABLE_452__Smio_9__SHIFT 0x0
++#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
++#define DPM_TABLE_453__Smio_10__SHIFT 0x0
++#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
++#define DPM_TABLE_454__Smio_11__SHIFT 0x0
++#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
++#define DPM_TABLE_455__Smio_12__SHIFT 0x0
++#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
++#define DPM_TABLE_456__Smio_13__SHIFT 0x0
++#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
++#define DPM_TABLE_457__Smio_14__SHIFT 0x0
++#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
++#define DPM_TABLE_458__Smio_15__SHIFT 0x0
++#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
++#define DPM_TABLE_459__Smio_16__SHIFT 0x0
++#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
++#define DPM_TABLE_460__Smio_17__SHIFT 0x0
++#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
++#define DPM_TABLE_461__Smio_18__SHIFT 0x0
++#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
++#define DPM_TABLE_462__Smio_19__SHIFT 0x0
++#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
++#define DPM_TABLE_463__Smio_20__SHIFT 0x0
++#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
++#define DPM_TABLE_464__Smio_21__SHIFT 0x0
++#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
++#define DPM_TABLE_465__Smio_22__SHIFT 0x0
++#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
++#define DPM_TABLE_466__Smio_23__SHIFT 0x0
++#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
++#define DPM_TABLE_467__Smio_24__SHIFT 0x0
++#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
++#define DPM_TABLE_468__Smio_25__SHIFT 0x0
++#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
++#define DPM_TABLE_469__Smio_26__SHIFT 0x0
++#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
++#define DPM_TABLE_470__Smio_27__SHIFT 0x0
++#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
++#define DPM_TABLE_471__Smio_28__SHIFT 0x0
++#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
++#define DPM_TABLE_472__Smio_29__SHIFT 0x0
++#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
++#define DPM_TABLE_473__Smio_30__SHIFT 0x0
++#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
++#define DPM_TABLE_474__Smio_31__SHIFT 0x0
++#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
++#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
++#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
++#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
++#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
++#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
++#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
++#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
++#define DPM_TABLE_476__SAMUInterval_MASK 0xff
++#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
++#define DPM_TABLE_476__ACPInterval_MASK 0xff00
++#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
++#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
++#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
++#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
++#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
++#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
++#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
++#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
++#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
++#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
++#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
++#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
++#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
++#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
++#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
++#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
++#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
++#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
++#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
++#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
++#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
++#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
++#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
++#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
++#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
++#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
++#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
++#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
++#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
++#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
++#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
++#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
++#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
++#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
++#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
++#define DPM_TABLE_482__DTEMode_MASK 0xff
++#define DPM_TABLE_482__DTEMode__SHIFT 0x0
++#define DPM_TABLE_482__DTEInterval_MASK 0xff00
++#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
++#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
++#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
++#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
++#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
++#define DPM_TABLE_483__ThermGpio_MASK 0xff
++#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
++#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
++#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
++#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
++#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
++#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
++#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
++#define DPM_TABLE_484__DisplayCac_MASK 0xffffffff
++#define DPM_TABLE_484__DisplayCac__SHIFT 0x0
++#define DPM_TABLE_485__NomPwr_MASK 0xffff
++#define DPM_TABLE_485__NomPwr__SHIFT 0x0
++#define DPM_TABLE_485__MaxPwr_MASK 0xffff0000
++#define DPM_TABLE_485__MaxPwr__SHIFT 0x10
++#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
++#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
++#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
++#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
++#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
++#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
++#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
++#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
++#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
++#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
++#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
++#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
++#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
++#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
++#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
++#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
++#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
++#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
++#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
++#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
++#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
++#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
++#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
++#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
++#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
++#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
++#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
++#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
++#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
++#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
++#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
++#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
++#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
++#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
++#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
++#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
++#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
++#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
++#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
++#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
++#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
++#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
++#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
++#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
++#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
++#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
++#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
++#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
++#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
++#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
++#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
++#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
++#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
++#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
++#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
++#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
++#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
++#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
++#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
++#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
++#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
++#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
++#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
++#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
++#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
++#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
++#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
++#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
++#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
++#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
++#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
++#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
++#define DPM_TABLE_503__BootVddci_MASK 0xffff
++#define DPM_TABLE_503__BootVddci__SHIFT 0x0
++#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
++#define DPM_TABLE_503__BootVddc__SHIFT 0x10
++#define DPM_TABLE_504__padding_MASK 0xffff
++#define DPM_TABLE_504__padding__SHIFT 0x0
++#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
++#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
++#define DPM_TABLE_505__DRAM_LOG_ADDR_H_MASK 0xffffffff
++#define DPM_TABLE_505__DRAM_LOG_ADDR_H__SHIFT 0x0
++#define DPM_TABLE_506__DRAM_LOG_ADDR_L_MASK 0xffffffff
++#define DPM_TABLE_506__DRAM_LOG_ADDR_L__SHIFT 0x0
++#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
++#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
++#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
++#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
++#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
++#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
++#define DPM_TABLE_510__BAPM_TEMP_GRADIENT_MASK 0xffffffff
++#define DPM_TABLE_510__BAPM_TEMP_GRADIENT__SHIFT 0x0
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
++#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
++#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
++#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
++#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
++#define TDC_STATUS__VDD_Boost_MASK 0xff
++#define TDC_STATUS__VDD_Boost__SHIFT 0x0
++#define TDC_STATUS__VDD_Throttle_MASK 0xff00
++#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
++#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
++#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
++#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
++#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
++#define TDC_MV_AVERAGE__IDD_MASK 0xffff
++#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
++#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
++#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
++#define TDC_VRM_LIMIT__IDD_MASK 0xffff
++#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
++#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
++#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
++#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
++#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
++#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
++#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
++#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
++#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
++#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
++#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
++#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
++#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
++#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
++#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
++#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
++#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
++#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
++#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
++#define FEATURE_STATUS__BAPM_ON_MASK 0x100
++#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
++#define FEATURE_STATUS__LPMX_ON_MASK 0x200
++#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
++#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
++#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
++#define FEATURE_STATUS__LHTC_ON_MASK 0x800
++#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
++#define FEATURE_STATUS__VPC_ON_MASK 0x1000
++#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
++#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
++#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
++#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
++#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
++#define FEATURE_STATUS__AVS_ON_MASK 0x10000
++#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
++#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
++#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
++#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
++#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
++#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
++#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
++#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
++#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
++#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
++#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
++#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
++#define FEATURE_STATUS__RESERVED__SHIFT 0x16
++#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18
++#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
++#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
++#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
++#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
++#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
++#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
++#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0
++#define FAN_TABLE_1__TempMin_MASK 0xffff
++#define FAN_TABLE_1__TempMin__SHIFT 0x0
++#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
++#define FAN_TABLE_1__FdoMode__SHIFT 0x10
++#define FAN_TABLE_2__TempMax_MASK 0xffff
++#define FAN_TABLE_2__TempMax__SHIFT 0x0
++#define FAN_TABLE_2__TempMed_MASK 0xffff0000
++#define FAN_TABLE_2__TempMed__SHIFT 0x10
++#define FAN_TABLE_3__Slope2_MASK 0xffff
++#define FAN_TABLE_3__Slope2__SHIFT 0x0
++#define FAN_TABLE_3__Slope1_MASK 0xffff0000
++#define FAN_TABLE_3__Slope1__SHIFT 0x10
++#define FAN_TABLE_4__HystUp_MASK 0xffff
++#define FAN_TABLE_4__HystUp__SHIFT 0x0
++#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
++#define FAN_TABLE_4__FdoMin__SHIFT 0x10
++#define FAN_TABLE_5__HystSlope_MASK 0xffff
++#define FAN_TABLE_5__HystSlope__SHIFT 0x0
++#define FAN_TABLE_5__HystDown_MASK 0xffff0000
++#define FAN_TABLE_5__HystDown__SHIFT 0x10
++#define FAN_TABLE_6__TempCurr_MASK 0xffff
++#define FAN_TABLE_6__TempCurr__SHIFT 0x0
++#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
++#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
++#define FAN_TABLE_7__PwmCurr_MASK 0xffff
++#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
++#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
++#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
++#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
++#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
++#define FAN_TABLE_9__Padding_MASK 0xff
++#define FAN_TABLE_9__Padding__SHIFT 0x0
++#define FAN_TABLE_9__TempSrc_MASK 0xff00
++#define FAN_TABLE_9__TempSrc__SHIFT 0x8
++#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
++#define FAN_TABLE_9__FdoMax__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_21__Reserved_0_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_21__Reserved_0__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_22__Reserved_1_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_22__Reserved_1__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_23__Reserved_2_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_23__Reserved_2__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_24__Reserved_3_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_24__Reserved_3__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_25__Reserved_4_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_25__Reserved_4__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_26__Reserved_5_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_26__Reserved_5__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_27__Reserved_6_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_27__Reserved_6__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_28__Reserved_7_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_28__Reserved_7__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_29__Reserved_8_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_29__Reserved_8__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_30__Reserved_9_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_30__Reserved_9__SHIFT 0x0
++#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
++#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
++#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
++#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
++#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
++#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
++#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
++#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
++#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
++#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
++#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
++#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
++#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
++#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
++#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
++#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
++#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
++#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
++#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
++#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
++#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
++#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
++#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
++#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
++#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
++#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
++#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
++#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
++#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
++#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
++#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
++#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
++#define PM_FUSES_5__VddCVid_3_MASK 0xff
++#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
++#define PM_FUSES_5__VddCVid_2_MASK 0xff00
++#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
++#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
++#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
++#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
++#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
++#define PM_FUSES_6__VddCVid_7_MASK 0xff
++#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
++#define PM_FUSES_6__VddCVid_6_MASK 0xff00
++#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
++#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
++#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
++#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
++#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
++#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
++#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
++#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
++#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
++#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
++#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
++#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
++#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
++#define PM_FUSES_8__TDC_MAWt_MASK 0xff
++#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
++#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
++#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
++#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
++#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
++#define PM_FUSES_9__Reserved_MASK 0xff
++#define PM_FUSES_9__Reserved__SHIFT 0x0
++#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
++#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
++#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
++#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
++#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
++#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
++#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff
++#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0
++#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00
++#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8
++#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000
++#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10
++#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000
++#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18
++#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff
++#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0
++#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00
++#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8
++#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000
++#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10
++#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000
++#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18
++#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff
++#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0
++#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00
++#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8
++#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000
++#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10
++#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000
++#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18
++#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff
++#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0
++#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00
++#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8
++#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000
++#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10
++#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000
++#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18
++#define PM_FUSES_14__GnbLPML_3_MASK 0xff
++#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0
++#define PM_FUSES_14__GnbLPML_2_MASK 0xff00
++#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8
++#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000
++#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10
++#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000
++#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18
++#define PM_FUSES_15__GnbLPML_7_MASK 0xff
++#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0
++#define PM_FUSES_15__GnbLPML_6_MASK 0xff00
++#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8
++#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000
++#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10
++#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000
++#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18
++#define PM_FUSES_16__GnbLPML_11_MASK 0xff
++#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0
++#define PM_FUSES_16__GnbLPML_10_MASK 0xff00
++#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8
++#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000
++#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10
++#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000
++#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18
++#define PM_FUSES_17__GnbLPML_15_MASK 0xff
++#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0
++#define PM_FUSES_17__GnbLPML_14_MASK 0xff00
++#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8
++#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000
++#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10
++#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000
++#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18
++#define PM_FUSES_18__Reserved1_1_MASK 0xff
++#define PM_FUSES_18__Reserved1_1__SHIFT 0x0
++#define PM_FUSES_18__Reserved1_0_MASK 0xff00
++#define PM_FUSES_18__Reserved1_0__SHIFT 0x8
++#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000
++#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10
++#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000
++#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18
++#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff
++#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
++#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
++#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
++#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
++#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
++#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
++#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
++#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
++#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
++#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
++#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
++#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
++#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
++#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
++#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
++#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
++#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
++#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
++#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
++#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
++#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
++#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
++#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
++#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
++#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
++#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
++#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
++#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
++#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
++#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
++#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
++#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
++#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
++#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
++#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
++#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL1__M_MASK 0xff0000
++#define CG_FDO_CTRL1__M__SHIFT 0x10
++#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
++#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
++#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
++#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
++#define CG_FDO_CTRL2__TMIN_MASK 0xff
++#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
++#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
++#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
++#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
++#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
++#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
++#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
++#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
++#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
++#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
++#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
++#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
++#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
++#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
++#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
++#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
++#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
++#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
++#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
++#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
++#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
++#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
++#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
++#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
++#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
++#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
++#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
++#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
++#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
++#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
++#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
++#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
++#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
++#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
++#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
++#define THM_TMON0_INT_DATA__VALID_MASK 0x800
++#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
++#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
++#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
++#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
++#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
++#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
++#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
++#define GENERAL_PWRMGT__SPARE11_MASK 0x800
++#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
++#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
++#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
++#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
++#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
++#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
++#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
++#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
++#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
++#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
++#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
++#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
++#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
++#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
++#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
++#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
++#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
++#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
++#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
++#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
++#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
++#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
++#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
++#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
++#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
++#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
++#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
++#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
++#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
++#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
++#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
++#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
++#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
++#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
++#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
++#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
++#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
++#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
++#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
++#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
++#define SCLK_MIN_DIV__FRACV_MASK 0xfff
++#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
++#define SCLK_MIN_DIV__INTV_MASK 0x7f000
++#define SCLK_MIN_DIV__INTV__SHIFT 0xc
++#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
++#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
++#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
++#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
++#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
++#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
++#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
++#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
++#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
++#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
++#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
++#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
++#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
++#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
++#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
++#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
++#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
++#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
++#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
++#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
++#define ROM_STATUS__ROM_BUSY_MASK 0x1
++#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
++#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
++#define ROM_DATA__ROM_DATA_MASK 0xffffffff
++#define ROM_DATA__ROM_DATA__SHIFT 0x0
++#define ROM_START__ROM_START_MASK 0xffffff
++#define ROM_START__ROM_START__SHIFT 0x0
++#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
++#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
++#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
++#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
++#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
++#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
++#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
++
++#endif /* SMU_7_0_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0020-yocto-amd-drm-amdgpu-add-SMU-7-1-2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0020-yocto-amd-drm-amdgpu-add-SMU-7-1-2-register-headers.patch
new file mode 100644
index 00000000..aa878c8d
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0020-yocto-amd-drm-amdgpu-add-SMU-7-1-2-register-headers.patch
@@ -0,0 +1,8215 @@
+From 7bfd998ac9a6e9af857b9540de4b30c320099e8a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:30:14 -0400
+Subject: drm/amdgpu: add SMU 7.1.0 register headers
+
+These are register headers for the SMU (System Management Unit)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
+new file mode 100644
+index 0000000..57588b1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
+@@ -0,0 +1,1344 @@
++/*
++ * SMU_7_1_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_0_D_H
++#define SMU_7_1_0_D_H
++
++#define mmGCK_SMC_IND_INDEX                                                     0x80
++#define mmGCK0_GCK_SMC_IND_INDEX                                                0x80
++#define mmGCK1_GCK_SMC_IND_INDEX                                                0x82
++#define mmGCK2_GCK_SMC_IND_INDEX                                                0x84
++#define mmGCK3_GCK_SMC_IND_INDEX                                                0x86
++#define mmGCK_SMC_IND_DATA                                                      0x81
++#define mmGCK0_GCK_SMC_IND_DATA                                                 0x81
++#define mmGCK1_GCK_SMC_IND_DATA                                                 0x83
++#define mmGCK2_GCK_SMC_IND_DATA                                                 0x85
++#define mmGCK3_GCK_SMC_IND_DATA                                                 0x87
++#define ixCG_DCLK_CNTL                                                          0xc050009c
++#define ixCG_DCLK_STATUS                                                        0xc05000a0
++#define ixCG_VCLK_CNTL                                                          0xc05000a4
++#define ixCG_VCLK_STATUS                                                        0xc05000a8
++#define ixCG_ECLK_CNTL                                                          0xc05000ac
++#define ixCG_ECLK_STATUS                                                        0xc05000b0
++#define ixCG_ACLK_CNTL                                                          0xc05000dc
++#define ixGCK_DFS_BYPASS_CNTL                                                   0xc0500118
++#define ixCG_SPLL_FUNC_CNTL                                                     0xc0500140
++#define ixCG_SPLL_FUNC_CNTL_2                                                   0xc0500144
++#define ixCG_SPLL_FUNC_CNTL_3                                                   0xc0500148
++#define ixCG_SPLL_FUNC_CNTL_4                                                   0xc050014c
++#define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
++#define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
++#define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixSPLL_CNTL_MODE                                                        0xc0500160
++#define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
++#define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
++#define ixMPLL_BYPASSCLK_SEL                                                    0xc050019c
++#define ixCG_CLKPIN_CNTL                                                        0xc05001a0
++#define ixCG_CLKPIN_CNTL_2                                                      0xc05001a4
++#define ixCG_CLKPIN_CNTL_DC                                                     0xc0500204
++#define ixTHM_CLK_CNTL                                                          0xc05001a8
++#define ixMISC_CLK_CTRL                                                         0xc05001ac
++#define ixGCK_PLL_TEST_CNTL                                                     0xc05001c0
++#define ixGCK_PLL_TEST_CNTL_2                                                   0xc05001c4
++#define ixGCK_ADFS_CLK_BYPASS_CNTL1                                             0xc05001c8
++#define mmSMC_IND_INDEX                                                         0x80
++#define mmSMC0_SMC_IND_INDEX                                                    0x80
++#define mmSMC1_SMC_IND_INDEX                                                    0x82
++#define mmSMC2_SMC_IND_INDEX                                                    0x84
++#define mmSMC3_SMC_IND_INDEX                                                    0x86
++#define mmSMC_IND_DATA                                                          0x81
++#define mmSMC0_SMC_IND_DATA                                                     0x81
++#define mmSMC1_SMC_IND_DATA                                                     0x83
++#define mmSMC2_SMC_IND_DATA                                                     0x85
++#define mmSMC3_SMC_IND_DATA                                                     0x87
++#define mmSMC_IND_INDEX_0                                                       0x80
++#define mmSMC_IND_DATA_0                                                        0x81
++#define mmSMC_IND_INDEX_1                                                       0x82
++#define mmSMC_IND_DATA_1                                                        0x83
++#define mmSMC_IND_INDEX_2                                                       0x84
++#define mmSMC_IND_DATA_2                                                        0x85
++#define mmSMC_IND_INDEX_3                                                       0x86
++#define mmSMC_IND_DATA_3                                                        0x87
++#define mmSMC_IND_INDEX_4                                                       0x88
++#define mmSMC_IND_DATA_4                                                        0x89
++#define mmSMC_IND_INDEX_5                                                       0x8a
++#define mmSMC_IND_DATA_5                                                        0x8b
++#define mmSMC_IND_INDEX_6                                                       0x8c
++#define mmSMC_IND_DATA_6                                                        0x8d
++#define mmSMC_IND_INDEX_7                                                       0x8e
++#define mmSMC_IND_DATA_7                                                        0x8f
++#define mmSMC_IND_ACCESS_CNTL                                                   0x90
++#define mmSMC_MESSAGE_0                                                         0x94
++#define mmSMC_RESP_0                                                            0x95
++#define mmSMC_MESSAGE_1                                                         0x96
++#define mmSMC_RESP_1                                                            0x97
++#define mmSMC_MESSAGE_2                                                         0x98
++#define mmSMC_RESP_2                                                            0x99
++#define mmSMC_MESSAGE_3                                                         0x9a
++#define mmSMC_RESP_3                                                            0x9b
++#define mmSMC_MESSAGE_4                                                         0x9c
++#define mmSMC_RESP_4                                                            0x9d
++#define mmSMC_MESSAGE_5                                                         0x9e
++#define mmSMC_RESP_5                                                            0x9f
++#define mmSMC_MESSAGE_6                                                         0xa0
++#define mmSMC_RESP_6                                                            0xa1
++#define mmSMC_MESSAGE_7                                                         0xa2
++#define mmSMC_RESP_7                                                            0xa3
++#define mmSMC_MSG_ARG_0                                                         0xa4
++#define mmSMC_MSG_ARG_1                                                         0xa5
++#define mmSMC_MSG_ARG_2                                                         0xa6
++#define mmSMC_MSG_ARG_3                                                         0xa7
++#define mmSMC_MSG_ARG_4                                                         0xa8
++#define mmSMC_MSG_ARG_5                                                         0xa9
++#define mmSMC_MSG_ARG_6                                                         0xaa
++#define mmSMC_MSG_ARG_7                                                         0xab
++#define mmSMC_MESSAGE_8                                                         0xb5
++#define mmSMC_RESP_8                                                            0xb6
++#define mmSMC_MESSAGE_9                                                         0xb7
++#define mmSMC_RESP_9                                                            0xb8
++#define mmSMC_MESSAGE_10                                                        0xb9
++#define mmSMC_RESP_10                                                           0xba
++#define mmSMC_MESSAGE_11                                                        0xbb
++#define mmSMC_RESP_11                                                           0xbc
++#define mmSMC_MSG_ARG_8                                                         0xbd
++#define mmSMC_MSG_ARG_9                                                         0xbe
++#define mmSMC_MSG_ARG_10                                                        0xbf
++#define mmSMC_MSG_ARG_11                                                        0x91
++#define ixSMC_SYSCON_RESET_CNTL                                                 0x80000000
++#define ixSMC_SYSCON_CLOCK_CNTL_0                                               0x80000004
++#define ixSMC_SYSCON_CLOCK_CNTL_1                                               0x80000008
++#define ixSMC_SYSCON_CLOCK_CNTL_2                                               0x8000000c
++#define ixSMC_SYSCON_MISC_CNTL                                                  0x80000010
++#define ixSMC_SYSCON_MSG_ARG_0                                                  0x80000068
++#define ixSMC_PC_C                                                              0x80000370
++#define ixSMC_SCRATCH9                                                          0x80000424
++#define mmGPIOPAD_SW_INT_STAT                                                   0x180
++#define mmGPIOPAD_STRENGTH                                                      0x181
++#define mmGPIOPAD_MASK                                                          0x182
++#define mmGPIOPAD_A                                                             0x183
++#define mmGPIOPAD_EN                                                            0x184
++#define mmGPIOPAD_Y                                                             0x185
++#define mmGPIOPAD_PINSTRAPS                                                     0x186
++#define mmGPIOPAD_INT_STAT_EN                                                   0x187
++#define mmGPIOPAD_INT_STAT                                                      0x188
++#define mmGPIOPAD_INT_STAT_AK                                                   0x189
++#define mmGPIOPAD_INT_EN                                                        0x18a
++#define mmGPIOPAD_INT_TYPE                                                      0x18b
++#define mmGPIOPAD_INT_POLARITY                                                  0x18c
++#define mmGPIOPAD_EXTERN_TRIG_CNTL                                              0x18d
++#define mmGPIOPAD_RCVR_SEL                                                      0x191
++#define mmGPIOPAD_PU_EN                                                         0x192
++#define mmGPIOPAD_PD_EN                                                         0x193
++#define mmCG_FPS_CNT                                                            0x1a4
++#define mmSMU_SMC_IND_INDEX                                                     0x80
++#define mmSMU0_SMU_SMC_IND_INDEX                                                0x80
++#define mmSMU1_SMU_SMC_IND_INDEX                                                0x82
++#define mmSMU2_SMU_SMC_IND_INDEX                                                0x84
++#define mmSMU3_SMU_SMC_IND_INDEX                                                0x86
++#define mmSMU_SMC_IND_DATA                                                      0x81
++#define mmSMU0_SMU_SMC_IND_DATA                                                 0x81
++#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83
++#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85
++#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87
++#define ixRCU_UC_EVENTS                                                         0xc0000004
++#define ixRCU_MISC_CTRL                                                         0xc0000010
++#define ixCC_RCU_FUSES                                                          0xc00c0000
++#define ixCC_SMU_MISC_FUSES                                                     0xc00c0004
++#define ixCC_SCLK_VID_FUSES                                                     0xc00c0008
++#define ixCC_GIO_IOCCFG_FUSES                                                   0xc00c000c
++#define ixCC_GIO_IOC_FUSES                                                      0xc00c0010
++#define ixCC_SMU_TST_EFUSE1_MISC                                                0xc00c001c
++#define ixCC_TST_ID_STRAPS                                                      0xc00c0020
++#define ixCC_FCTRL_FUSES                                                        0xc00c0024
++#define ixSMU_MAIN_PLL_OP_FREQ                                                  0xe0003020
++#define ixSMU_STATUS                                                            0xe0003088
++#define ixSMU_FIRMWARE                                                          0xe00030a4
++#define ixSMU_INPUT_DATA                                                        0xe00030b8
++#define ixSMU_EFUSE_0                                                           0xc0100000
++#define ixDPM_TABLE_1                                                           0x3f000
++#define ixDPM_TABLE_2                                                           0x3f004
++#define ixDPM_TABLE_3                                                           0x3f008
++#define ixDPM_TABLE_4                                                           0x3f00c
++#define ixDPM_TABLE_5                                                           0x3f010
++#define ixDPM_TABLE_6                                                           0x3f014
++#define ixDPM_TABLE_7                                                           0x3f018
++#define ixDPM_TABLE_8                                                           0x3f01c
++#define ixDPM_TABLE_9                                                           0x3f020
++#define ixDPM_TABLE_10                                                          0x3f024
++#define ixDPM_TABLE_11                                                          0x3f028
++#define ixDPM_TABLE_12                                                          0x3f02c
++#define ixDPM_TABLE_13                                                          0x3f030
++#define ixDPM_TABLE_14                                                          0x3f034
++#define ixDPM_TABLE_15                                                          0x3f038
++#define ixDPM_TABLE_16                                                          0x3f03c
++#define ixDPM_TABLE_17                                                          0x3f040
++#define ixDPM_TABLE_18                                                          0x3f044
++#define ixDPM_TABLE_19                                                          0x3f048
++#define ixDPM_TABLE_20                                                          0x3f04c
++#define ixDPM_TABLE_21                                                          0x3f050
++#define ixDPM_TABLE_22                                                          0x3f054
++#define ixDPM_TABLE_23                                                          0x3f058
++#define ixDPM_TABLE_24                                                          0x3f05c
++#define ixDPM_TABLE_25                                                          0x3f060
++#define ixDPM_TABLE_26                                                          0x3f064
++#define ixDPM_TABLE_27                                                          0x3f068
++#define ixDPM_TABLE_28                                                          0x3f06c
++#define ixDPM_TABLE_29                                                          0x3f070
++#define ixDPM_TABLE_30                                                          0x3f074
++#define ixDPM_TABLE_31                                                          0x3f078
++#define ixDPM_TABLE_32                                                          0x3f07c
++#define ixDPM_TABLE_33                                                          0x3f080
++#define ixDPM_TABLE_34                                                          0x3f084
++#define ixDPM_TABLE_35                                                          0x3f088
++#define ixDPM_TABLE_36                                                          0x3f08c
++#define ixDPM_TABLE_37                                                          0x3f090
++#define ixDPM_TABLE_38                                                          0x3f094
++#define ixDPM_TABLE_39                                                          0x3f098
++#define ixDPM_TABLE_40                                                          0x3f09c
++#define ixDPM_TABLE_41                                                          0x3f0a0
++#define ixDPM_TABLE_42                                                          0x3f0a4
++#define ixDPM_TABLE_43                                                          0x3f0a8
++#define ixDPM_TABLE_44                                                          0x3f0ac
++#define ixDPM_TABLE_45                                                          0x3f0b0
++#define ixDPM_TABLE_46                                                          0x3f0b4
++#define ixDPM_TABLE_47                                                          0x3f0b8
++#define ixDPM_TABLE_48                                                          0x3f0bc
++#define ixDPM_TABLE_49                                                          0x3f0c0
++#define ixDPM_TABLE_50                                                          0x3f0c4
++#define ixDPM_TABLE_51                                                          0x3f0c8
++#define ixDPM_TABLE_52                                                          0x3f0cc
++#define ixDPM_TABLE_53                                                          0x3f0d0
++#define ixDPM_TABLE_54                                                          0x3f0d4
++#define ixDPM_TABLE_55                                                          0x3f0d8
++#define ixDPM_TABLE_56                                                          0x3f0dc
++#define ixDPM_TABLE_57                                                          0x3f0e0
++#define ixDPM_TABLE_58                                                          0x3f0e4
++#define ixDPM_TABLE_59                                                          0x3f0e8
++#define ixDPM_TABLE_60                                                          0x3f0ec
++#define ixDPM_TABLE_61                                                          0x3f0f0
++#define ixDPM_TABLE_62                                                          0x3f0f4
++#define ixDPM_TABLE_63                                                          0x3f0f8
++#define ixDPM_TABLE_64                                                          0x3f0fc
++#define ixDPM_TABLE_65                                                          0x3f100
++#define ixDPM_TABLE_66                                                          0x3f104
++#define ixDPM_TABLE_67                                                          0x3f108
++#define ixDPM_TABLE_68                                                          0x3f10c
++#define ixDPM_TABLE_69                                                          0x3f110
++#define ixDPM_TABLE_70                                                          0x3f114
++#define ixDPM_TABLE_71                                                          0x3f118
++#define ixDPM_TABLE_72                                                          0x3f11c
++#define ixDPM_TABLE_73                                                          0x3f120
++#define ixDPM_TABLE_74                                                          0x3f124
++#define ixDPM_TABLE_75                                                          0x3f128
++#define ixDPM_TABLE_76                                                          0x3f12c
++#define ixDPM_TABLE_77                                                          0x3f130
++#define ixDPM_TABLE_78                                                          0x3f134
++#define ixDPM_TABLE_79                                                          0x3f138
++#define ixDPM_TABLE_80                                                          0x3f13c
++#define ixDPM_TABLE_81                                                          0x3f140
++#define ixDPM_TABLE_82                                                          0x3f144
++#define ixDPM_TABLE_83                                                          0x3f148
++#define ixDPM_TABLE_84                                                          0x3f14c
++#define ixDPM_TABLE_85                                                          0x3f150
++#define ixDPM_TABLE_86                                                          0x3f154
++#define ixDPM_TABLE_87                                                          0x3f158
++#define ixDPM_TABLE_88                                                          0x3f15c
++#define ixDPM_TABLE_89                                                          0x3f160
++#define ixDPM_TABLE_90                                                          0x3f164
++#define ixDPM_TABLE_91                                                          0x3f168
++#define ixDPM_TABLE_92                                                          0x3f16c
++#define ixDPM_TABLE_93                                                          0x3f170
++#define ixDPM_TABLE_94                                                          0x3f174
++#define ixDPM_TABLE_95                                                          0x3f178
++#define ixDPM_TABLE_96                                                          0x3f17c
++#define ixDPM_TABLE_97                                                          0x3f180
++#define ixDPM_TABLE_98                                                          0x3f184
++#define ixDPM_TABLE_99                                                          0x3f188
++#define ixDPM_TABLE_100                                                         0x3f18c
++#define ixDPM_TABLE_101                                                         0x3f190
++#define ixDPM_TABLE_102                                                         0x3f194
++#define ixDPM_TABLE_103                                                         0x3f198
++#define ixDPM_TABLE_104                                                         0x3f19c
++#define ixDPM_TABLE_105                                                         0x3f1a0
++#define ixDPM_TABLE_106                                                         0x3f1a4
++#define ixDPM_TABLE_107                                                         0x3f1a8
++#define ixDPM_TABLE_108                                                         0x3f1ac
++#define ixDPM_TABLE_109                                                         0x3f1b0
++#define ixDPM_TABLE_110                                                         0x3f1b4
++#define ixDPM_TABLE_111                                                         0x3f1b8
++#define ixDPM_TABLE_112                                                         0x3f1bc
++#define ixDPM_TABLE_113                                                         0x3f1c0
++#define ixDPM_TABLE_114                                                         0x3f1c4
++#define ixDPM_TABLE_115                                                         0x3f1c8
++#define ixDPM_TABLE_116                                                         0x3f1cc
++#define ixDPM_TABLE_117                                                         0x3f1d0
++#define ixDPM_TABLE_118                                                         0x3f1d4
++#define ixDPM_TABLE_119                                                         0x3f1d8
++#define ixDPM_TABLE_120                                                         0x3f1dc
++#define ixDPM_TABLE_121                                                         0x3f1e0
++#define ixDPM_TABLE_122                                                         0x3f1e4
++#define ixDPM_TABLE_123                                                         0x3f1e8
++#define ixDPM_TABLE_124                                                         0x3f1ec
++#define ixDPM_TABLE_125                                                         0x3f1f0
++#define ixDPM_TABLE_126                                                         0x3f1f4
++#define ixDPM_TABLE_127                                                         0x3f1f8
++#define ixDPM_TABLE_128                                                         0x3f1fc
++#define ixDPM_TABLE_129                                                         0x3f200
++#define ixDPM_TABLE_130                                                         0x3f204
++#define ixDPM_TABLE_131                                                         0x3f208
++#define ixDPM_TABLE_132                                                         0x3f20c
++#define ixDPM_TABLE_133                                                         0x3f210
++#define ixDPM_TABLE_134                                                         0x3f214
++#define ixDPM_TABLE_135                                                         0x3f218
++#define ixDPM_TABLE_136                                                         0x3f21c
++#define ixDPM_TABLE_137                                                         0x3f220
++#define ixDPM_TABLE_138                                                         0x3f224
++#define ixDPM_TABLE_139                                                         0x3f228
++#define ixDPM_TABLE_140                                                         0x3f22c
++#define ixDPM_TABLE_141                                                         0x3f230
++#define ixDPM_TABLE_142                                                         0x3f234
++#define ixDPM_TABLE_143                                                         0x3f238
++#define ixDPM_TABLE_144                                                         0x3f23c
++#define ixDPM_TABLE_145                                                         0x3f240
++#define ixDPM_TABLE_146                                                         0x3f244
++#define ixDPM_TABLE_147                                                         0x3f248
++#define ixDPM_TABLE_148                                                         0x3f24c
++#define ixDPM_TABLE_149                                                         0x3f250
++#define ixDPM_TABLE_150                                                         0x3f254
++#define ixDPM_TABLE_151                                                         0x3f258
++#define ixDPM_TABLE_152                                                         0x3f25c
++#define ixDPM_TABLE_153                                                         0x3f260
++#define ixDPM_TABLE_154                                                         0x3f264
++#define ixDPM_TABLE_155                                                         0x3f268
++#define ixDPM_TABLE_156                                                         0x3f26c
++#define ixDPM_TABLE_157                                                         0x3f270
++#define ixDPM_TABLE_158                                                         0x3f274
++#define ixDPM_TABLE_159                                                         0x3f278
++#define ixDPM_TABLE_160                                                         0x3f27c
++#define ixDPM_TABLE_161                                                         0x3f280
++#define ixDPM_TABLE_162                                                         0x3f284
++#define ixDPM_TABLE_163                                                         0x3f288
++#define ixDPM_TABLE_164                                                         0x3f28c
++#define ixDPM_TABLE_165                                                         0x3f290
++#define ixDPM_TABLE_166                                                         0x3f294
++#define ixDPM_TABLE_167                                                         0x3f298
++#define ixDPM_TABLE_168                                                         0x3f29c
++#define ixDPM_TABLE_169                                                         0x3f2a0
++#define ixDPM_TABLE_170                                                         0x3f2a4
++#define ixDPM_TABLE_171                                                         0x3f2a8
++#define ixDPM_TABLE_172                                                         0x3f2ac
++#define ixDPM_TABLE_173                                                         0x3f2b0
++#define ixDPM_TABLE_174                                                         0x3f2b4
++#define ixDPM_TABLE_175                                                         0x3f2b8
++#define ixDPM_TABLE_176                                                         0x3f2bc
++#define ixDPM_TABLE_177                                                         0x3f2c0
++#define ixDPM_TABLE_178                                                         0x3f2c4
++#define ixDPM_TABLE_179                                                         0x3f2c8
++#define ixDPM_TABLE_180                                                         0x3f2cc
++#define ixDPM_TABLE_181                                                         0x3f2d0
++#define ixDPM_TABLE_182                                                         0x3f2d4
++#define ixDPM_TABLE_183                                                         0x3f2d8
++#define ixDPM_TABLE_184                                                         0x3f2dc
++#define ixDPM_TABLE_185                                                         0x3f2e0
++#define ixDPM_TABLE_186                                                         0x3f2e4
++#define ixDPM_TABLE_187                                                         0x3f2e8
++#define ixDPM_TABLE_188                                                         0x3f2ec
++#define ixDPM_TABLE_189                                                         0x3f2f0
++#define ixDPM_TABLE_190                                                         0x3f2f4
++#define ixDPM_TABLE_191                                                         0x3f2f8
++#define ixDPM_TABLE_192                                                         0x3f2fc
++#define ixDPM_TABLE_193                                                         0x3f300
++#define ixDPM_TABLE_194                                                         0x3f304
++#define ixDPM_TABLE_195                                                         0x3f308
++#define ixDPM_TABLE_196                                                         0x3f30c
++#define ixDPM_TABLE_197                                                         0x3f310
++#define ixDPM_TABLE_198                                                         0x3f314
++#define ixDPM_TABLE_199                                                         0x3f318
++#define ixDPM_TABLE_200                                                         0x3f31c
++#define ixDPM_TABLE_201                                                         0x3f320
++#define ixDPM_TABLE_202                                                         0x3f324
++#define ixDPM_TABLE_203                                                         0x3f328
++#define ixDPM_TABLE_204                                                         0x3f32c
++#define ixDPM_TABLE_205                                                         0x3f330
++#define ixDPM_TABLE_206                                                         0x3f334
++#define ixDPM_TABLE_207                                                         0x3f338
++#define ixDPM_TABLE_208                                                         0x3f33c
++#define ixDPM_TABLE_209                                                         0x3f340
++#define ixDPM_TABLE_210                                                         0x3f344
++#define ixDPM_TABLE_211                                                         0x3f348
++#define ixDPM_TABLE_212                                                         0x3f34c
++#define ixDPM_TABLE_213                                                         0x3f350
++#define ixDPM_TABLE_214                                                         0x3f354
++#define ixDPM_TABLE_215                                                         0x3f358
++#define ixDPM_TABLE_216                                                         0x3f35c
++#define ixDPM_TABLE_217                                                         0x3f360
++#define ixDPM_TABLE_218                                                         0x3f364
++#define ixDPM_TABLE_219                                                         0x3f368
++#define ixDPM_TABLE_220                                                         0x3f36c
++#define ixDPM_TABLE_221                                                         0x3f370
++#define ixDPM_TABLE_222                                                         0x3f374
++#define ixDPM_TABLE_223                                                         0x3f378
++#define ixDPM_TABLE_224                                                         0x3f37c
++#define ixDPM_TABLE_225                                                         0x3f380
++#define ixDPM_TABLE_226                                                         0x3f384
++#define ixDPM_TABLE_227                                                         0x3f388
++#define ixDPM_TABLE_228                                                         0x3f38c
++#define ixDPM_TABLE_229                                                         0x3f390
++#define ixDPM_TABLE_230                                                         0x3f394
++#define ixDPM_TABLE_231                                                         0x3f398
++#define ixDPM_TABLE_232                                                         0x3f39c
++#define ixDPM_TABLE_233                                                         0x3f3a0
++#define ixDPM_TABLE_234                                                         0x3f3a4
++#define ixDPM_TABLE_235                                                         0x3f3a8
++#define ixDPM_TABLE_236                                                         0x3f3ac
++#define ixDPM_TABLE_237                                                         0x3f3b0
++#define ixDPM_TABLE_238                                                         0x3f3b4
++#define ixDPM_TABLE_239                                                         0x3f3b8
++#define ixDPM_TABLE_240                                                         0x3f3bc
++#define ixDPM_TABLE_241                                                         0x3f3c0
++#define ixDPM_TABLE_242                                                         0x3f3c4
++#define ixDPM_TABLE_243                                                         0x3f3c8
++#define ixDPM_TABLE_244                                                         0x3f3cc
++#define ixDPM_TABLE_245                                                         0x3f3d0
++#define ixDPM_TABLE_246                                                         0x3f3d4
++#define ixDPM_TABLE_247                                                         0x3f3d8
++#define ixDPM_TABLE_248                                                         0x3f3dc
++#define ixDPM_TABLE_249                                                         0x3f3e0
++#define ixDPM_TABLE_250                                                         0x3f3e4
++#define ixDPM_TABLE_251                                                         0x3f3e8
++#define ixDPM_TABLE_252                                                         0x3f3ec
++#define ixDPM_TABLE_253                                                         0x3f3f0
++#define ixDPM_TABLE_254                                                         0x3f3f4
++#define ixDPM_TABLE_255                                                         0x3f3f8
++#define ixDPM_TABLE_256                                                         0x3f3fc
++#define ixDPM_TABLE_257                                                         0x3f400
++#define ixDPM_TABLE_258                                                         0x3f404
++#define ixDPM_TABLE_259                                                         0x3f408
++#define ixDPM_TABLE_260                                                         0x3f40c
++#define ixDPM_TABLE_261                                                         0x3f410
++#define ixDPM_TABLE_262                                                         0x3f414
++#define ixDPM_TABLE_263                                                         0x3f418
++#define ixDPM_TABLE_264                                                         0x3f41c
++#define ixDPM_TABLE_265                                                         0x3f420
++#define ixDPM_TABLE_266                                                         0x3f424
++#define ixDPM_TABLE_267                                                         0x3f428
++#define ixDPM_TABLE_268                                                         0x3f42c
++#define ixDPM_TABLE_269                                                         0x3f430
++#define ixDPM_TABLE_270                                                         0x3f434
++#define ixDPM_TABLE_271                                                         0x3f438
++#define ixDPM_TABLE_272                                                         0x3f43c
++#define ixDPM_TABLE_273                                                         0x3f440
++#define ixDPM_TABLE_274                                                         0x3f444
++#define ixDPM_TABLE_275                                                         0x3f448
++#define ixDPM_TABLE_276                                                         0x3f44c
++#define ixDPM_TABLE_277                                                         0x3f450
++#define ixDPM_TABLE_278                                                         0x3f454
++#define ixDPM_TABLE_279                                                         0x3f458
++#define ixDPM_TABLE_280                                                         0x3f45c
++#define ixDPM_TABLE_281                                                         0x3f460
++#define ixDPM_TABLE_282                                                         0x3f464
++#define ixDPM_TABLE_283                                                         0x3f468
++#define ixDPM_TABLE_284                                                         0x3f46c
++#define ixDPM_TABLE_285                                                         0x3f470
++#define ixDPM_TABLE_286                                                         0x3f474
++#define ixDPM_TABLE_287                                                         0x3f478
++#define ixDPM_TABLE_288                                                         0x3f47c
++#define ixDPM_TABLE_289                                                         0x3f480
++#define ixDPM_TABLE_290                                                         0x3f484
++#define ixDPM_TABLE_291                                                         0x3f488
++#define ixDPM_TABLE_292                                                         0x3f48c
++#define ixDPM_TABLE_293                                                         0x3f490
++#define ixDPM_TABLE_294                                                         0x3f494
++#define ixDPM_TABLE_295                                                         0x3f498
++#define ixDPM_TABLE_296                                                         0x3f49c
++#define ixDPM_TABLE_297                                                         0x3f4a0
++#define ixDPM_TABLE_298                                                         0x3f4a4
++#define ixDPM_TABLE_299                                                         0x3f4a8
++#define ixDPM_TABLE_300                                                         0x3f4ac
++#define ixDPM_TABLE_301                                                         0x3f4b0
++#define ixDPM_TABLE_302                                                         0x3f4b4
++#define ixDPM_TABLE_303                                                         0x3f4b8
++#define ixDPM_TABLE_304                                                         0x3f4bc
++#define ixDPM_TABLE_305                                                         0x3f4c0
++#define ixDPM_TABLE_306                                                         0x3f4c4
++#define ixDPM_TABLE_307                                                         0x3f4c8
++#define ixDPM_TABLE_308                                                         0x3f4cc
++#define ixDPM_TABLE_309                                                         0x3f4d0
++#define ixDPM_TABLE_310                                                         0x3f4d4
++#define ixDPM_TABLE_311                                                         0x3f4d8
++#define ixDPM_TABLE_312                                                         0x3f4dc
++#define ixDPM_TABLE_313                                                         0x3f4e0
++#define ixDPM_TABLE_314                                                         0x3f4e4
++#define ixDPM_TABLE_315                                                         0x3f4e8
++#define ixDPM_TABLE_316                                                         0x3f4ec
++#define ixDPM_TABLE_317                                                         0x3f4f0
++#define ixDPM_TABLE_318                                                         0x3f4f4
++#define ixDPM_TABLE_319                                                         0x3f4f8
++#define ixDPM_TABLE_320                                                         0x3f4fc
++#define ixDPM_TABLE_321                                                         0x3f500
++#define ixDPM_TABLE_322                                                         0x3f504
++#define ixDPM_TABLE_323                                                         0x3f508
++#define ixDPM_TABLE_324                                                         0x3f50c
++#define ixDPM_TABLE_325                                                         0x3f510
++#define ixDPM_TABLE_326                                                         0x3f514
++#define ixDPM_TABLE_327                                                         0x3f518
++#define ixDPM_TABLE_328                                                         0x3f51c
++#define ixDPM_TABLE_329                                                         0x3f520
++#define ixDPM_TABLE_330                                                         0x3f524
++#define ixDPM_TABLE_331                                                         0x3f528
++#define ixDPM_TABLE_332                                                         0x3f52c
++#define ixDPM_TABLE_333                                                         0x3f530
++#define ixDPM_TABLE_334                                                         0x3f534
++#define ixDPM_TABLE_335                                                         0x3f538
++#define ixDPM_TABLE_336                                                         0x3f53c
++#define ixDPM_TABLE_337                                                         0x3f540
++#define ixDPM_TABLE_338                                                         0x3f544
++#define ixDPM_TABLE_339                                                         0x3f548
++#define ixDPM_TABLE_340                                                         0x3f54c
++#define ixDPM_TABLE_341                                                         0x3f550
++#define ixDPM_TABLE_342                                                         0x3f554
++#define ixDPM_TABLE_343                                                         0x3f558
++#define ixDPM_TABLE_344                                                         0x3f55c
++#define ixDPM_TABLE_345                                                         0x3f560
++#define ixDPM_TABLE_346                                                         0x3f564
++#define ixDPM_TABLE_347                                                         0x3f568
++#define ixDPM_TABLE_348                                                         0x3f56c
++#define ixDPM_TABLE_349                                                         0x3f570
++#define ixDPM_TABLE_350                                                         0x3f574
++#define ixDPM_TABLE_351                                                         0x3f578
++#define ixDPM_TABLE_352                                                         0x3f57c
++#define ixDPM_TABLE_353                                                         0x3f580
++#define ixDPM_TABLE_354                                                         0x3f584
++#define ixDPM_TABLE_355                                                         0x3f588
++#define ixDPM_TABLE_356                                                         0x3f58c
++#define ixDPM_TABLE_357                                                         0x3f590
++#define ixDPM_TABLE_358                                                         0x3f594
++#define ixDPM_TABLE_359                                                         0x3f598
++#define ixDPM_TABLE_360                                                         0x3f59c
++#define ixDPM_TABLE_361                                                         0x3f5a0
++#define ixDPM_TABLE_362                                                         0x3f5a4
++#define ixDPM_TABLE_363                                                         0x3f5a8
++#define ixDPM_TABLE_364                                                         0x3f5ac
++#define ixDPM_TABLE_365                                                         0x3f5b0
++#define ixDPM_TABLE_366                                                         0x3f5b4
++#define ixDPM_TABLE_367                                                         0x3f5b8
++#define ixDPM_TABLE_368                                                         0x3f5bc
++#define ixDPM_TABLE_369                                                         0x3f5c0
++#define ixDPM_TABLE_370                                                         0x3f5c4
++#define ixDPM_TABLE_371                                                         0x3f5c8
++#define ixDPM_TABLE_372                                                         0x3f5cc
++#define ixDPM_TABLE_373                                                         0x3f5d0
++#define ixDPM_TABLE_374                                                         0x3f5d4
++#define ixDPM_TABLE_375                                                         0x3f5d8
++#define ixDPM_TABLE_376                                                         0x3f5dc
++#define ixDPM_TABLE_377                                                         0x3f5e0
++#define ixDPM_TABLE_378                                                         0x3f5e4
++#define ixDPM_TABLE_379                                                         0x3f5e8
++#define ixDPM_TABLE_380                                                         0x3f5ec
++#define ixDPM_TABLE_381                                                         0x3f5f0
++#define ixDPM_TABLE_382                                                         0x3f5f4
++#define ixDPM_TABLE_383                                                         0x3f5f8
++#define ixDPM_TABLE_384                                                         0x3f5fc
++#define ixDPM_TABLE_385                                                         0x3f600
++#define ixDPM_TABLE_386                                                         0x3f604
++#define ixDPM_TABLE_387                                                         0x3f608
++#define ixDPM_TABLE_388                                                         0x3f60c
++#define ixDPM_TABLE_389                                                         0x3f610
++#define ixDPM_TABLE_390                                                         0x3f614
++#define ixDPM_TABLE_391                                                         0x3f618
++#define ixDPM_TABLE_392                                                         0x3f61c
++#define ixDPM_TABLE_393                                                         0x3f620
++#define ixDPM_TABLE_394                                                         0x3f624
++#define ixDPM_TABLE_395                                                         0x3f628
++#define ixDPM_TABLE_396                                                         0x3f62c
++#define ixDPM_TABLE_397                                                         0x3f630
++#define ixDPM_TABLE_398                                                         0x3f634
++#define ixDPM_TABLE_399                                                         0x3f638
++#define ixDPM_TABLE_400                                                         0x3f63c
++#define ixDPM_TABLE_401                                                         0x3f640
++#define ixDPM_TABLE_402                                                         0x3f644
++#define ixDPM_TABLE_403                                                         0x3f648
++#define ixDPM_TABLE_404                                                         0x3f64c
++#define ixDPM_TABLE_405                                                         0x3f650
++#define ixDPM_TABLE_406                                                         0x3f654
++#define ixDPM_TABLE_407                                                         0x3f658
++#define ixDPM_TABLE_408                                                         0x3f65c
++#define ixDPM_TABLE_409                                                         0x3f660
++#define ixDPM_TABLE_410                                                         0x3f664
++#define ixDPM_TABLE_411                                                         0x3f668
++#define ixDPM_TABLE_412                                                         0x3f66c
++#define ixDPM_TABLE_413                                                         0x3f670
++#define ixDPM_TABLE_414                                                         0x3f674
++#define ixDPM_TABLE_415                                                         0x3f678
++#define ixDPM_TABLE_416                                                         0x3f67c
++#define ixDPM_TABLE_417                                                         0x3f680
++#define ixDPM_TABLE_418                                                         0x3f684
++#define ixDPM_TABLE_419                                                         0x3f688
++#define ixDPM_TABLE_420                                                         0x3f68c
++#define ixDPM_TABLE_421                                                         0x3f690
++#define ixDPM_TABLE_422                                                         0x3f694
++#define ixDPM_TABLE_423                                                         0x3f698
++#define ixDPM_TABLE_424                                                         0x3f69c
++#define ixDPM_TABLE_425                                                         0x3f6a0
++#define ixDPM_TABLE_426                                                         0x3f6a4
++#define ixDPM_TABLE_427                                                         0x3f6a8
++#define ixDPM_TABLE_428                                                         0x3f6ac
++#define ixDPM_TABLE_429                                                         0x3f6b0
++#define ixDPM_TABLE_430                                                         0x3f6b4
++#define ixDPM_TABLE_431                                                         0x3f6b8
++#define ixDPM_TABLE_432                                                         0x3f6bc
++#define ixDPM_TABLE_433                                                         0x3f6c0
++#define ixDPM_TABLE_434                                                         0x3f6c4
++#define ixDPM_TABLE_435                                                         0x3f6c8
++#define ixDPM_TABLE_436                                                         0x3f6cc
++#define ixDPM_TABLE_437                                                         0x3f6d0
++#define ixDPM_TABLE_438                                                         0x3f6d4
++#define ixDPM_TABLE_439                                                         0x3f6d8
++#define ixDPM_TABLE_440                                                         0x3f6dc
++#define ixDPM_TABLE_441                                                         0x3f6e0
++#define ixDPM_TABLE_442                                                         0x3f6e4
++#define ixDPM_TABLE_443                                                         0x3f6e8
++#define ixDPM_TABLE_444                                                         0x3f6ec
++#define ixDPM_TABLE_445                                                         0x3f6f0
++#define ixDPM_TABLE_446                                                         0x3f6f4
++#define ixDPM_TABLE_447                                                         0x3f6f8
++#define ixDPM_TABLE_448                                                         0x3f6fc
++#define ixDPM_TABLE_449                                                         0x3f700
++#define ixDPM_TABLE_450                                                         0x3f704
++#define ixDPM_TABLE_451                                                         0x3f708
++#define ixDPM_TABLE_452                                                         0x3f70c
++#define ixDPM_TABLE_453                                                         0x3f710
++#define ixDPM_TABLE_454                                                         0x3f714
++#define ixDPM_TABLE_455                                                         0x3f718
++#define ixDPM_TABLE_456                                                         0x3f71c
++#define ixDPM_TABLE_457                                                         0x3f720
++#define ixDPM_TABLE_458                                                         0x3f724
++#define ixDPM_TABLE_459                                                         0x3f728
++#define ixDPM_TABLE_460                                                         0x3f72c
++#define ixDPM_TABLE_461                                                         0x3f730
++#define ixDPM_TABLE_462                                                         0x3f734
++#define ixDPM_TABLE_463                                                         0x3f738
++#define ixDPM_TABLE_464                                                         0x3f73c
++#define ixDPM_TABLE_465                                                         0x3f740
++#define ixDPM_TABLE_466                                                         0x3f744
++#define ixDPM_TABLE_467                                                         0x3f748
++#define ixDPM_TABLE_468                                                         0x3f74c
++#define ixDPM_TABLE_469                                                         0x3f750
++#define ixDPM_TABLE_470                                                         0x3f754
++#define ixDPM_TABLE_471                                                         0x3f758
++#define ixDPM_TABLE_472                                                         0x3f75c
++#define ixDPM_TABLE_473                                                         0x3f760
++#define ixDPM_TABLE_474                                                         0x3f764
++#define ixDPM_TABLE_475                                                         0x3f768
++#define ixDPM_TABLE_476                                                         0x3f76c
++#define ixDPM_TABLE_477                                                         0x3f770
++#define ixDPM_TABLE_478                                                         0x3f774
++#define ixDPM_TABLE_479                                                         0x3f778
++#define ixDPM_TABLE_480                                                         0x3f77c
++#define ixDPM_TABLE_481                                                         0x3f780
++#define ixDPM_TABLE_482                                                         0x3f784
++#define ixDPM_TABLE_483                                                         0x3f788
++#define ixDPM_TABLE_484                                                         0x3f78c
++#define ixDPM_TABLE_485                                                         0x3f790
++#define ixDPM_TABLE_486                                                         0x3f794
++#define ixDPM_TABLE_487                                                         0x3f798
++#define ixDPM_TABLE_488                                                         0x3f79c
++#define ixDPM_TABLE_489                                                         0x3f7a0
++#define ixDPM_TABLE_490                                                         0x3f7a4
++#define ixDPM_TABLE_491                                                         0x3f7a8
++#define ixDPM_TABLE_492                                                         0x3f7ac
++#define ixDPM_TABLE_493                                                         0x3f7b0
++#define ixDPM_TABLE_494                                                         0x3f7b4
++#define ixDPM_TABLE_495                                                         0x3f7b8
++#define ixDPM_TABLE_496                                                         0x3f7bc
++#define ixDPM_TABLE_497                                                         0x3f7c0
++#define ixDPM_TABLE_498                                                         0x3f7c4
++#define ixDPM_TABLE_499                                                         0x3f7c8
++#define ixDPM_TABLE_500                                                         0x3f7cc
++#define ixDPM_TABLE_501                                                         0x3f7d0
++#define ixDPM_TABLE_502                                                         0x3f7d4
++#define ixDPM_TABLE_503                                                         0x3f7d8
++#define ixDPM_TABLE_504                                                         0x3f7dc
++#define ixDPM_TABLE_505                                                         0x3f7e0
++#define ixDPM_TABLE_506                                                         0x3f7e4
++#define ixFIRMWARE_FLAGS                                                        0x3f800
++#define ixTDC_STATUS                                                            0x3f808
++#define ixTDC_MV_AVERAGE                                                        0x3f80c
++#define ixTDC_VRM_LIMIT                                                         0x3f810
++#define ixFEATURE_STATUS                                                        0x3f818
++#define ixENTITY_TEMPERATURES_1                                                 0x3f81c
++#define ixMCARB_DRAM_TIMING_TABLE_1                                             0x3f900
++#define ixMCARB_DRAM_TIMING_TABLE_2                                             0x3f904
++#define ixMCARB_DRAM_TIMING_TABLE_3                                             0x3f908
++#define ixMCARB_DRAM_TIMING_TABLE_4                                             0x3f90c
++#define ixMCARB_DRAM_TIMING_TABLE_5                                             0x3f910
++#define ixMCARB_DRAM_TIMING_TABLE_6                                             0x3f914
++#define ixMCARB_DRAM_TIMING_TABLE_7                                             0x3f918
++#define ixMCARB_DRAM_TIMING_TABLE_8                                             0x3f91c
++#define ixMCARB_DRAM_TIMING_TABLE_9                                             0x3f920
++#define ixMCARB_DRAM_TIMING_TABLE_10                                            0x3f924
++#define ixMCARB_DRAM_TIMING_TABLE_11                                            0x3f928
++#define ixMCARB_DRAM_TIMING_TABLE_12                                            0x3f92c
++#define ixMCARB_DRAM_TIMING_TABLE_13                                            0x3f930
++#define ixMCARB_DRAM_TIMING_TABLE_14                                            0x3f934
++#define ixMCARB_DRAM_TIMING_TABLE_15                                            0x3f938
++#define ixMCARB_DRAM_TIMING_TABLE_16                                            0x3f93c
++#define ixMCARB_DRAM_TIMING_TABLE_17                                            0x3f940
++#define ixMCARB_DRAM_TIMING_TABLE_18                                            0x3f944
++#define ixMCARB_DRAM_TIMING_TABLE_19                                            0x3f948
++#define ixMCARB_DRAM_TIMING_TABLE_20                                            0x3f94c
++#define ixMCARB_DRAM_TIMING_TABLE_21                                            0x3f950
++#define ixMCARB_DRAM_TIMING_TABLE_22                                            0x3f954
++#define ixMCARB_DRAM_TIMING_TABLE_23                                            0x3f958
++#define ixMCARB_DRAM_TIMING_TABLE_24                                            0x3f95c
++#define ixMCARB_DRAM_TIMING_TABLE_25                                            0x3f960
++#define ixMCARB_DRAM_TIMING_TABLE_26                                            0x3f964
++#define ixMCARB_DRAM_TIMING_TABLE_27                                            0x3f968
++#define ixMCARB_DRAM_TIMING_TABLE_28                                            0x3f96c
++#define ixMCARB_DRAM_TIMING_TABLE_29                                            0x3f970
++#define ixMCARB_DRAM_TIMING_TABLE_30                                            0x3f974
++#define ixMCARB_DRAM_TIMING_TABLE_31                                            0x3f978
++#define ixMCARB_DRAM_TIMING_TABLE_32                                            0x3f97c
++#define ixMCARB_DRAM_TIMING_TABLE_33                                            0x3f980
++#define ixMCARB_DRAM_TIMING_TABLE_34                                            0x3f984
++#define ixMCARB_DRAM_TIMING_TABLE_35                                            0x3f988
++#define ixMCARB_DRAM_TIMING_TABLE_36                                            0x3f98c
++#define ixMCARB_DRAM_TIMING_TABLE_37                                            0x3f990
++#define ixMCARB_DRAM_TIMING_TABLE_38                                            0x3f994
++#define ixMCARB_DRAM_TIMING_TABLE_39                                            0x3f998
++#define ixMCARB_DRAM_TIMING_TABLE_40                                            0x3f99c
++#define ixMCARB_DRAM_TIMING_TABLE_41                                            0x3f9a0
++#define ixMCARB_DRAM_TIMING_TABLE_42                                            0x3f9a4
++#define ixMCARB_DRAM_TIMING_TABLE_43                                            0x3f9a8
++#define ixMCARB_DRAM_TIMING_TABLE_44                                            0x3f9ac
++#define ixMCARB_DRAM_TIMING_TABLE_45                                            0x3f9b0
++#define ixMCARB_DRAM_TIMING_TABLE_46                                            0x3f9b4
++#define ixMCARB_DRAM_TIMING_TABLE_47                                            0x3f9b8
++#define ixMCARB_DRAM_TIMING_TABLE_48                                            0x3f9bc
++#define ixMCARB_DRAM_TIMING_TABLE_49                                            0x3f9c0
++#define ixMCARB_DRAM_TIMING_TABLE_50                                            0x3f9c4
++#define ixMCARB_DRAM_TIMING_TABLE_51                                            0x3f9c8
++#define ixMCARB_DRAM_TIMING_TABLE_52                                            0x3f9cc
++#define ixMCARB_DRAM_TIMING_TABLE_53                                            0x3f9d0
++#define ixMCARB_DRAM_TIMING_TABLE_54                                            0x3f9d4
++#define ixMCARB_DRAM_TIMING_TABLE_55                                            0x3f9d8
++#define ixMCARB_DRAM_TIMING_TABLE_56                                            0x3f9dc
++#define ixMCARB_DRAM_TIMING_TABLE_57                                            0x3f9e0
++#define ixMCARB_DRAM_TIMING_TABLE_58                                            0x3f9e4
++#define ixMCARB_DRAM_TIMING_TABLE_59                                            0x3f9e8
++#define ixMCARB_DRAM_TIMING_TABLE_60                                            0x3f9ec
++#define ixMCARB_DRAM_TIMING_TABLE_61                                            0x3f9f0
++#define ixMCARB_DRAM_TIMING_TABLE_62                                            0x3f9f4
++#define ixMCARB_DRAM_TIMING_TABLE_63                                            0x3f9f8
++#define ixMCARB_DRAM_TIMING_TABLE_64                                            0x3f9fc
++#define ixMCARB_DRAM_TIMING_TABLE_65                                            0x3fa00
++#define ixMCARB_DRAM_TIMING_TABLE_66                                            0x3fa04
++#define ixMCARB_DRAM_TIMING_TABLE_67                                            0x3fa08
++#define ixMCARB_DRAM_TIMING_TABLE_68                                            0x3fa0c
++#define ixMCARB_DRAM_TIMING_TABLE_69                                            0x3fa10
++#define ixMCARB_DRAM_TIMING_TABLE_70                                            0x3fa14
++#define ixMCARB_DRAM_TIMING_TABLE_71                                            0x3fa18
++#define ixMCARB_DRAM_TIMING_TABLE_72                                            0x3fa1c
++#define ixMCARB_DRAM_TIMING_TABLE_73                                            0x3fa20
++#define ixMCARB_DRAM_TIMING_TABLE_74                                            0x3fa24
++#define ixMCARB_DRAM_TIMING_TABLE_75                                            0x3fa28
++#define ixMCARB_DRAM_TIMING_TABLE_76                                            0x3fa2c
++#define ixMCARB_DRAM_TIMING_TABLE_77                                            0x3fa30
++#define ixMCARB_DRAM_TIMING_TABLE_78                                            0x3fa34
++#define ixMCARB_DRAM_TIMING_TABLE_79                                            0x3fa38
++#define ixMCARB_DRAM_TIMING_TABLE_80                                            0x3fa3c
++#define ixMCARB_DRAM_TIMING_TABLE_81                                            0x3fa40
++#define ixMCARB_DRAM_TIMING_TABLE_82                                            0x3fa44
++#define ixMCARB_DRAM_TIMING_TABLE_83                                            0x3fa48
++#define ixMCARB_DRAM_TIMING_TABLE_84                                            0x3fa4c
++#define ixMCARB_DRAM_TIMING_TABLE_85                                            0x3fa50
++#define ixMCARB_DRAM_TIMING_TABLE_86                                            0x3fa54
++#define ixMCARB_DRAM_TIMING_TABLE_87                                            0x3fa58
++#define ixMCARB_DRAM_TIMING_TABLE_88                                            0x3fa5c
++#define ixMCARB_DRAM_TIMING_TABLE_89                                            0x3fa60
++#define ixMCARB_DRAM_TIMING_TABLE_90                                            0x3fa64
++#define ixMCARB_DRAM_TIMING_TABLE_91                                            0x3fa68
++#define ixMCARB_DRAM_TIMING_TABLE_92                                            0x3fa6c
++#define ixMCARB_DRAM_TIMING_TABLE_93                                            0x3fa70
++#define ixMCARB_DRAM_TIMING_TABLE_94                                            0x3fa74
++#define ixMCARB_DRAM_TIMING_TABLE_95                                            0x3fa78
++#define ixMCARB_DRAM_TIMING_TABLE_96                                            0x3fa7c
++#define ixMCARB_DRAM_TIMING_TABLE_97                                            0x3fa80
++#define ixMCARB_DRAM_TIMING_TABLE_98                                            0x3fa84
++#define ixMCARB_DRAM_TIMING_TABLE_99                                            0x3fa88
++#define ixMCARB_DRAM_TIMING_TABLE_100                                           0x3fa8c
++#define ixMCARB_DRAM_TIMING_TABLE_101                                           0x3fa90
++#define ixMCARB_DRAM_TIMING_TABLE_102                                           0x3fa94
++#define ixMCARB_DRAM_TIMING_TABLE_103                                           0x3fa98
++#define ixMCARB_DRAM_TIMING_TABLE_104                                           0x3fa9c
++#define ixMCARB_DRAM_TIMING_TABLE_105                                           0x3faa0
++#define ixMCARB_DRAM_TIMING_TABLE_106                                           0x3faa4
++#define ixMCARB_DRAM_TIMING_TABLE_107                                           0x3faa8
++#define ixMCARB_DRAM_TIMING_TABLE_108                                           0x3faac
++#define ixMCARB_DRAM_TIMING_TABLE_109                                           0x3fab0
++#define ixMCARB_DRAM_TIMING_TABLE_110                                           0x3fab4
++#define ixMCARB_DRAM_TIMING_TABLE_111                                           0x3fab8
++#define ixMCARB_DRAM_TIMING_TABLE_112                                           0x3fabc
++#define ixMCARB_DRAM_TIMING_TABLE_113                                           0x3fac0
++#define ixMCARB_DRAM_TIMING_TABLE_114                                           0x3fac4
++#define ixMCARB_DRAM_TIMING_TABLE_115                                           0x3fac8
++#define ixMCARB_DRAM_TIMING_TABLE_116                                           0x3facc
++#define ixMCARB_DRAM_TIMING_TABLE_117                                           0x3fad0
++#define ixMCARB_DRAM_TIMING_TABLE_118                                           0x3fad4
++#define ixMCARB_DRAM_TIMING_TABLE_119                                           0x3fad8
++#define ixMCARB_DRAM_TIMING_TABLE_120                                           0x3fadc
++#define ixMCARB_DRAM_TIMING_TABLE_121                                           0x3fae0
++#define ixMCARB_DRAM_TIMING_TABLE_122                                           0x3fae4
++#define ixMCARB_DRAM_TIMING_TABLE_123                                           0x3fae8
++#define ixMCARB_DRAM_TIMING_TABLE_124                                           0x3faec
++#define ixMCARB_DRAM_TIMING_TABLE_125                                           0x3faf0
++#define ixMCARB_DRAM_TIMING_TABLE_126                                           0x3faf4
++#define ixMCARB_DRAM_TIMING_TABLE_127                                           0x3faf8
++#define ixMCARB_DRAM_TIMING_TABLE_128                                           0x3fafc
++#define ixMCARB_DRAM_TIMING_TABLE_129                                           0x3fb00
++#define ixMCARB_DRAM_TIMING_TABLE_130                                           0x3fb04
++#define ixMCARB_DRAM_TIMING_TABLE_131                                           0x3fb08
++#define ixMCARB_DRAM_TIMING_TABLE_132                                           0x3fb0c
++#define ixMCARB_DRAM_TIMING_TABLE_133                                           0x3fb10
++#define ixMCARB_DRAM_TIMING_TABLE_134                                           0x3fb14
++#define ixMCARB_DRAM_TIMING_TABLE_135                                           0x3fb18
++#define ixMCARB_DRAM_TIMING_TABLE_136                                           0x3fb1c
++#define ixMCARB_DRAM_TIMING_TABLE_137                                           0x3fb20
++#define ixMCARB_DRAM_TIMING_TABLE_138                                           0x3fb24
++#define ixMCARB_DRAM_TIMING_TABLE_139                                           0x3fb28
++#define ixMCARB_DRAM_TIMING_TABLE_140                                           0x3fb2c
++#define ixMCARB_DRAM_TIMING_TABLE_141                                           0x3fb30
++#define ixMCARB_DRAM_TIMING_TABLE_142                                           0x3fb34
++#define ixMCARB_DRAM_TIMING_TABLE_143                                           0x3fb38
++#define ixMCARB_DRAM_TIMING_TABLE_144                                           0x3fb3c
++#define ixMC_REGISTERS_TABLE_1                                                  0x3fb40
++#define ixMC_REGISTERS_TABLE_2                                                  0x3fb44
++#define ixMC_REGISTERS_TABLE_3                                                  0x3fb48
++#define ixMC_REGISTERS_TABLE_4                                                  0x3fb4c
++#define ixMC_REGISTERS_TABLE_5                                                  0x3fb50
++#define ixMC_REGISTERS_TABLE_6                                                  0x3fb54
++#define ixMC_REGISTERS_TABLE_7                                                  0x3fb58
++#define ixMC_REGISTERS_TABLE_8                                                  0x3fb5c
++#define ixMC_REGISTERS_TABLE_9                                                  0x3fb60
++#define ixMC_REGISTERS_TABLE_10                                                 0x3fb64
++#define ixMC_REGISTERS_TABLE_11                                                 0x3fb68
++#define ixMC_REGISTERS_TABLE_12                                                 0x3fb6c
++#define ixMC_REGISTERS_TABLE_13                                                 0x3fb70
++#define ixMC_REGISTERS_TABLE_14                                                 0x3fb74
++#define ixMC_REGISTERS_TABLE_15                                                 0x3fb78
++#define ixMC_REGISTERS_TABLE_16                                                 0x3fb7c
++#define ixMC_REGISTERS_TABLE_17                                                 0x3fb80
++#define ixMC_REGISTERS_TABLE_18                                                 0x3fb84
++#define ixMC_REGISTERS_TABLE_19                                                 0x3fb88
++#define ixMC_REGISTERS_TABLE_20                                                 0x3fb8c
++#define ixMC_REGISTERS_TABLE_21                                                 0x3fb90
++#define ixMC_REGISTERS_TABLE_22                                                 0x3fb94
++#define ixMC_REGISTERS_TABLE_23                                                 0x3fb98
++#define ixMC_REGISTERS_TABLE_24                                                 0x3fb9c
++#define ixMC_REGISTERS_TABLE_25                                                 0x3fba0
++#define ixMC_REGISTERS_TABLE_26                                                 0x3fba4
++#define ixMC_REGISTERS_TABLE_27                                                 0x3fba8
++#define ixMC_REGISTERS_TABLE_28                                                 0x3fbac
++#define ixMC_REGISTERS_TABLE_29                                                 0x3fbb0
++#define ixMC_REGISTERS_TABLE_30                                                 0x3fbb4
++#define ixMC_REGISTERS_TABLE_31                                                 0x3fbb8
++#define ixMC_REGISTERS_TABLE_32                                                 0x3fbbc
++#define ixMC_REGISTERS_TABLE_33                                                 0x3fbc0
++#define ixMC_REGISTERS_TABLE_34                                                 0x3fbc4
++#define ixMC_REGISTERS_TABLE_35                                                 0x3fbc8
++#define ixMC_REGISTERS_TABLE_36                                                 0x3fbcc
++#define ixMC_REGISTERS_TABLE_37                                                 0x3fbd0
++#define ixMC_REGISTERS_TABLE_38                                                 0x3fbd4
++#define ixMC_REGISTERS_TABLE_39                                                 0x3fbd8
++#define ixMC_REGISTERS_TABLE_40                                                 0x3fbdc
++#define ixMC_REGISTERS_TABLE_41                                                 0x3fbe0
++#define ixMC_REGISTERS_TABLE_42                                                 0x3fbe4
++#define ixMC_REGISTERS_TABLE_43                                                 0x3fbe8
++#define ixMC_REGISTERS_TABLE_44                                                 0x3fbec
++#define ixMC_REGISTERS_TABLE_45                                                 0x3fbf0
++#define ixMC_REGISTERS_TABLE_46                                                 0x3fbf4
++#define ixMC_REGISTERS_TABLE_47                                                 0x3fbf8
++#define ixMC_REGISTERS_TABLE_48                                                 0x3fbfc
++#define ixMC_REGISTERS_TABLE_49                                                 0x3fc00
++#define ixMC_REGISTERS_TABLE_50                                                 0x3fc04
++#define ixMC_REGISTERS_TABLE_51                                                 0x3fc08
++#define ixMC_REGISTERS_TABLE_52                                                 0x3fc0c
++#define ixMC_REGISTERS_TABLE_53                                                 0x3fc10
++#define ixMC_REGISTERS_TABLE_54                                                 0x3fc14
++#define ixMC_REGISTERS_TABLE_55                                                 0x3fc18
++#define ixMC_REGISTERS_TABLE_56                                                 0x3fc1c
++#define ixMC_REGISTERS_TABLE_57                                                 0x3fc20
++#define ixMC_REGISTERS_TABLE_58                                                 0x3fc24
++#define ixMC_REGISTERS_TABLE_59                                                 0x3fc28
++#define ixMC_REGISTERS_TABLE_60                                                 0x3fc2c
++#define ixMC_REGISTERS_TABLE_61                                                 0x3fc30
++#define ixMC_REGISTERS_TABLE_62                                                 0x3fc34
++#define ixMC_REGISTERS_TABLE_63                                                 0x3fc38
++#define ixMC_REGISTERS_TABLE_64                                                 0x3fc3c
++#define ixMC_REGISTERS_TABLE_65                                                 0x3fc40
++#define ixMC_REGISTERS_TABLE_66                                                 0x3fc44
++#define ixMC_REGISTERS_TABLE_67                                                 0x3fc48
++#define ixMC_REGISTERS_TABLE_68                                                 0x3fc4c
++#define ixMC_REGISTERS_TABLE_69                                                 0x3fc50
++#define ixMC_REGISTERS_TABLE_70                                                 0x3fc54
++#define ixMC_REGISTERS_TABLE_71                                                 0x3fc58
++#define ixMC_REGISTERS_TABLE_72                                                 0x3fc5c
++#define ixMC_REGISTERS_TABLE_73                                                 0x3fc60
++#define ixMC_REGISTERS_TABLE_74                                                 0x3fc64
++#define ixMC_REGISTERS_TABLE_75                                                 0x3fc68
++#define ixMC_REGISTERS_TABLE_76                                                 0x3fc6c
++#define ixMC_REGISTERS_TABLE_77                                                 0x3fc70
++#define ixMC_REGISTERS_TABLE_78                                                 0x3fc74
++#define ixMC_REGISTERS_TABLE_79                                                 0x3fc78
++#define ixMC_REGISTERS_TABLE_80                                                 0x3fc7c
++#define ixMC_REGISTERS_TABLE_81                                                 0x3fc80
++#define ixMC_REGISTERS_TABLE_82                                                 0x3fc84
++#define ixMC_REGISTERS_TABLE_83                                                 0x3fc88
++#define ixMC_REGISTERS_TABLE_84                                                 0x3fc8c
++#define ixMC_REGISTERS_TABLE_85                                                 0x3fc90
++#define ixMC_REGISTERS_TABLE_86                                                 0x3fc94
++#define ixMC_REGISTERS_TABLE_87                                                 0x3fc98
++#define ixMC_REGISTERS_TABLE_88                                                 0x3fc9c
++#define ixMC_REGISTERS_TABLE_89                                                 0x3fca0
++#define ixMC_REGISTERS_TABLE_90                                                 0x3fca4
++#define ixMC_REGISTERS_TABLE_91                                                 0x3fca8
++#define ixMC_REGISTERS_TABLE_92                                                 0x3fcac
++#define ixMC_REGISTERS_TABLE_93                                                 0x3fcb0
++#define ixMC_REGISTERS_TABLE_94                                                 0x3fcb4
++#define ixMC_REGISTERS_TABLE_95                                                 0x3fcb8
++#define ixMC_REGISTERS_TABLE_96                                                 0x3fcbc
++#define ixMC_REGISTERS_TABLE_97                                                 0x3fcc0
++#define ixMC_REGISTERS_TABLE_98                                                 0x3fcc4
++#define ixMC_REGISTERS_TABLE_99                                                 0x3fcc8
++#define ixMC_REGISTERS_TABLE_100                                                0x3fccc
++#define ixMC_REGISTERS_TABLE_101                                                0x3fcd0
++#define ixMC_REGISTERS_TABLE_102                                                0x3fcd4
++#define ixMC_REGISTERS_TABLE_103                                                0x3fcd8
++#define ixMC_REGISTERS_TABLE_104                                                0x3fcdc
++#define ixMC_REGISTERS_TABLE_105                                                0x3fce0
++#define ixMC_REGISTERS_TABLE_106                                                0x3fce4
++#define ixMC_REGISTERS_TABLE_107                                                0x3fce8
++#define ixMC_REGISTERS_TABLE_108                                                0x3fcec
++#define ixMC_REGISTERS_TABLE_109                                                0x3fcf0
++#define ixMC_REGISTERS_TABLE_110                                                0x3fcf4
++#define ixMC_REGISTERS_TABLE_111                                                0x3fcf8
++#define ixMC_REGISTERS_TABLE_112                                                0x3fcfc
++#define ixMC_REGISTERS_TABLE_113                                                0x3fd00
++#define ixFAN_TABLE_1                                                           0x3fd04
++#define ixFAN_TABLE_2                                                           0x3fd08
++#define ixFAN_TABLE_3                                                           0x3fd0c
++#define ixFAN_TABLE_4                                                           0x3fd10
++#define ixFAN_TABLE_5                                                           0x3fd14
++#define ixFAN_TABLE_6                                                           0x3fd18
++#define ixFAN_TABLE_7                                                           0x3fd1c
++#define ixFAN_TABLE_8                                                           0x3fd20
++#define ixFAN_TABLE_9                                                           0x3fd24
++#define ixSOFT_REGISTERS_TABLE_1                                                0x3fd28
++#define ixSOFT_REGISTERS_TABLE_2                                                0x3fd2c
++#define ixSOFT_REGISTERS_TABLE_3                                                0x3fd30
++#define ixSOFT_REGISTERS_TABLE_4                                                0x3fd34
++#define ixSOFT_REGISTERS_TABLE_5                                                0x3fd38
++#define ixSOFT_REGISTERS_TABLE_6                                                0x3fd3c
++#define ixSOFT_REGISTERS_TABLE_7                                                0x3fd40
++#define ixSOFT_REGISTERS_TABLE_8                                                0x3fd44
++#define ixSOFT_REGISTERS_TABLE_9                                                0x3fd48
++#define ixSOFT_REGISTERS_TABLE_10                                               0x3fd4c
++#define ixSOFT_REGISTERS_TABLE_11                                               0x3fd50
++#define ixSOFT_REGISTERS_TABLE_12                                               0x3fd54
++#define ixSOFT_REGISTERS_TABLE_13                                               0x3fd58
++#define ixSOFT_REGISTERS_TABLE_14                                               0x3fd5c
++#define ixSOFT_REGISTERS_TABLE_15                                               0x3fd60
++#define ixSOFT_REGISTERS_TABLE_16                                               0x3fd64
++#define ixSOFT_REGISTERS_TABLE_17                                               0x3fd68
++#define ixSOFT_REGISTERS_TABLE_18                                               0x3fd6c
++#define ixSOFT_REGISTERS_TABLE_19                                               0x3fd70
++#define ixSOFT_REGISTERS_TABLE_20                                               0x3fd74
++#define ixSOFT_REGISTERS_TABLE_21                                               0x3fd78
++#define ixSOFT_REGISTERS_TABLE_22                                               0x3fd7c
++#define ixSOFT_REGISTERS_TABLE_23                                               0x3fd80
++#define ixSOFT_REGISTERS_TABLE_24                                               0x3fd84
++#define ixSOFT_REGISTERS_TABLE_25                                               0x3fd88
++#define ixSOFT_REGISTERS_TABLE_26                                               0x3fd8c
++#define ixSOFT_REGISTERS_TABLE_27                                               0x3fd90
++#define ixSOFT_REGISTERS_TABLE_28                                               0x3fd94
++#define ixSOFT_REGISTERS_TABLE_29                                               0x3fd98
++#define ixSOFT_REGISTERS_TABLE_30                                               0x3fd9c
++#define ixPM_FUSES_1                                                            0x3fda0
++#define ixPM_FUSES_2                                                            0x3fda4
++#define ixPM_FUSES_3                                                            0x3fda8
++#define ixPM_FUSES_4                                                            0x3fdac
++#define ixPM_FUSES_5                                                            0x3fdb0
++#define ixPM_FUSES_6                                                            0x3fdb4
++#define ixPM_FUSES_7                                                            0x3fdb8
++#define ixPM_FUSES_8                                                            0x3fdbc
++#define ixPM_FUSES_9                                                            0x3fdc0
++#define ixPM_FUSES_10                                                           0x3fdc4
++#define ixPM_FUSES_11                                                           0x3fdc8
++#define ixPM_FUSES_12                                                           0x3fdcc
++#define ixPM_FUSES_13                                                           0x3fdd0
++#define ixPM_FUSES_14                                                           0x3fdd4
++#define ixPM_FUSES_15                                                           0x3fdd8
++#define ixPM_FUSES_16                                                           0x3fddc
++#define ixPM_FUSES_17                                                           0x3fde0
++#define ixPM_FUSES_18                                                           0x3fde4
++#define ixPM_FUSES_19                                                           0x3fde8
++#define ixSMU_PM_STATUS_0                                                       0x3fe00
++#define ixSMU_PM_STATUS_1                                                       0x3fe04
++#define ixSMU_PM_STATUS_2                                                       0x3fe08
++#define ixSMU_PM_STATUS_3                                                       0x3fe0c
++#define ixSMU_PM_STATUS_4                                                       0x3fe10
++#define ixSMU_PM_STATUS_5                                                       0x3fe14
++#define ixSMU_PM_STATUS_6                                                       0x3fe18
++#define ixSMU_PM_STATUS_7                                                       0x3fe1c
++#define ixSMU_PM_STATUS_8                                                       0x3fe20
++#define ixSMU_PM_STATUS_9                                                       0x3fe24
++#define ixSMU_PM_STATUS_10                                                      0x3fe28
++#define ixSMU_PM_STATUS_11                                                      0x3fe2c
++#define ixSMU_PM_STATUS_12                                                      0x3fe30
++#define ixSMU_PM_STATUS_13                                                      0x3fe34
++#define ixSMU_PM_STATUS_14                                                      0x3fe38
++#define ixSMU_PM_STATUS_15                                                      0x3fe3c
++#define ixSMU_PM_STATUS_16                                                      0x3fe40
++#define ixSMU_PM_STATUS_17                                                      0x3fe44
++#define ixSMU_PM_STATUS_18                                                      0x3fe48
++#define ixSMU_PM_STATUS_19                                                      0x3fe4c
++#define ixSMU_PM_STATUS_20                                                      0x3fe50
++#define ixSMU_PM_STATUS_21                                                      0x3fe54
++#define ixSMU_PM_STATUS_22                                                      0x3fe58
++#define ixSMU_PM_STATUS_23                                                      0x3fe5c
++#define ixSMU_PM_STATUS_24                                                      0x3fe60
++#define ixSMU_PM_STATUS_25                                                      0x3fe64
++#define ixSMU_PM_STATUS_26                                                      0x3fe68
++#define ixSMU_PM_STATUS_27                                                      0x3fe6c
++#define ixSMU_PM_STATUS_28                                                      0x3fe70
++#define ixSMU_PM_STATUS_29                                                      0x3fe74
++#define ixSMU_PM_STATUS_30                                                      0x3fe78
++#define ixSMU_PM_STATUS_31                                                      0x3fe7c
++#define ixSMU_PM_STATUS_32                                                      0x3fe80
++#define ixSMU_PM_STATUS_33                                                      0x3fe84
++#define ixSMU_PM_STATUS_34                                                      0x3fe88
++#define ixSMU_PM_STATUS_35                                                      0x3fe8c
++#define ixSMU_PM_STATUS_36                                                      0x3fe90
++#define ixSMU_PM_STATUS_37                                                      0x3fe94
++#define ixSMU_PM_STATUS_38                                                      0x3fe98
++#define ixSMU_PM_STATUS_39                                                      0x3fe9c
++#define ixSMU_PM_STATUS_40                                                      0x3fea0
++#define ixSMU_PM_STATUS_41                                                      0x3fea4
++#define ixSMU_PM_STATUS_42                                                      0x3fea8
++#define ixSMU_PM_STATUS_43                                                      0x3feac
++#define ixSMU_PM_STATUS_44                                                      0x3feb0
++#define ixSMU_PM_STATUS_45                                                      0x3feb4
++#define ixSMU_PM_STATUS_46                                                      0x3feb8
++#define ixSMU_PM_STATUS_47                                                      0x3febc
++#define ixSMU_PM_STATUS_48                                                      0x3fec0
++#define ixSMU_PM_STATUS_49                                                      0x3fec4
++#define ixSMU_PM_STATUS_50                                                      0x3fec8
++#define ixSMU_PM_STATUS_51                                                      0x3fecc
++#define ixSMU_PM_STATUS_52                                                      0x3fed0
++#define ixSMU_PM_STATUS_53                                                      0x3fed4
++#define ixSMU_PM_STATUS_54                                                      0x3fed8
++#define ixSMU_PM_STATUS_55                                                      0x3fedc
++#define ixSMU_PM_STATUS_56                                                      0x3fee0
++#define ixSMU_PM_STATUS_57                                                      0x3fee4
++#define ixSMU_PM_STATUS_58                                                      0x3fee8
++#define ixSMU_PM_STATUS_59                                                      0x3feec
++#define ixSMU_PM_STATUS_60                                                      0x3fef0
++#define ixSMU_PM_STATUS_61                                                      0x3fef4
++#define ixSMU_PM_STATUS_62                                                      0x3fef8
++#define ixSMU_PM_STATUS_63                                                      0x3fefc
++#define ixSMU_PM_STATUS_64                                                      0x3ff00
++#define ixSMU_PM_STATUS_65                                                      0x3ff04
++#define ixSMU_PM_STATUS_66                                                      0x3ff08
++#define ixSMU_PM_STATUS_67                                                      0x3ff0c
++#define ixSMU_PM_STATUS_68                                                      0x3ff10
++#define ixSMU_PM_STATUS_69                                                      0x3ff14
++#define ixSMU_PM_STATUS_70                                                      0x3ff18
++#define ixSMU_PM_STATUS_71                                                      0x3ff1c
++#define ixSMU_PM_STATUS_72                                                      0x3ff20
++#define ixSMU_PM_STATUS_73                                                      0x3ff24
++#define ixSMU_PM_STATUS_74                                                      0x3ff28
++#define ixSMU_PM_STATUS_75                                                      0x3ff2c
++#define ixSMU_PM_STATUS_76                                                      0x3ff30
++#define ixSMU_PM_STATUS_77                                                      0x3ff34
++#define ixSMU_PM_STATUS_78                                                      0x3ff38
++#define ixSMU_PM_STATUS_79                                                      0x3ff3c
++#define ixSMU_PM_STATUS_80                                                      0x3ff40
++#define ixSMU_PM_STATUS_81                                                      0x3ff44
++#define ixSMU_PM_STATUS_82                                                      0x3ff48
++#define ixSMU_PM_STATUS_83                                                      0x3ff4c
++#define ixSMU_PM_STATUS_84                                                      0x3ff50
++#define ixSMU_PM_STATUS_85                                                      0x3ff54
++#define ixSMU_PM_STATUS_86                                                      0x3ff58
++#define ixSMU_PM_STATUS_87                                                      0x3ff5c
++#define ixSMU_PM_STATUS_88                                                      0x3ff60
++#define ixSMU_PM_STATUS_89                                                      0x3ff64
++#define ixSMU_PM_STATUS_90                                                      0x3ff68
++#define ixSMU_PM_STATUS_91                                                      0x3ff6c
++#define ixSMU_PM_STATUS_92                                                      0x3ff70
++#define ixSMU_PM_STATUS_93                                                      0x3ff74
++#define ixSMU_PM_STATUS_94                                                      0x3ff78
++#define ixSMU_PM_STATUS_95                                                      0x3ff7c
++#define ixSMU_PM_STATUS_96                                                      0x3ff80
++#define ixSMU_PM_STATUS_97                                                      0x3ff84
++#define ixSMU_PM_STATUS_98                                                      0x3ff88
++#define ixSMU_PM_STATUS_99                                                      0x3ff8c
++#define ixSMU_PM_STATUS_100                                                     0x3ff90
++#define ixSMU_PM_STATUS_101                                                     0x3ff94
++#define ixSMU_PM_STATUS_102                                                     0x3ff98
++#define ixSMU_PM_STATUS_103                                                     0x3ff9c
++#define ixSMU_PM_STATUS_104                                                     0x3ffa0
++#define ixSMU_PM_STATUS_105                                                     0x3ffa4
++#define ixSMU_PM_STATUS_106                                                     0x3ffa8
++#define ixSMU_PM_STATUS_107                                                     0x3ffac
++#define ixSMU_PM_STATUS_108                                                     0x3ffb0
++#define ixSMU_PM_STATUS_109                                                     0x3ffb4
++#define ixSMU_PM_STATUS_110                                                     0x3ffb8
++#define ixSMU_PM_STATUS_111                                                     0x3ffbc
++#define ixSMU_PM_STATUS_112                                                     0x3ffc0
++#define ixSMU_PM_STATUS_113                                                     0x3ffc4
++#define ixSMU_PM_STATUS_114                                                     0x3ffc8
++#define ixSMU_PM_STATUS_115                                                     0x3ffcc
++#define ixSMU_PM_STATUS_116                                                     0x3ffd0
++#define ixSMU_PM_STATUS_117                                                     0x3ffd4
++#define ixSMU_PM_STATUS_118                                                     0x3ffd8
++#define ixSMU_PM_STATUS_119                                                     0x3ffdc
++#define ixSMU_PM_STATUS_120                                                     0x3ffe0
++#define ixSMU_PM_STATUS_121                                                     0x3ffe4
++#define ixSMU_PM_STATUS_122                                                     0x3ffe8
++#define ixSMU_PM_STATUS_123                                                     0x3ffec
++#define ixSMU_PM_STATUS_124                                                     0x3fff0
++#define ixSMU_PM_STATUS_125                                                     0x3fff4
++#define ixSMU_PM_STATUS_126                                                     0x3fff8
++#define ixSMU_PM_STATUS_127                                                     0x3fffc
++#define ixCG_THERMAL_INT_ENA                                                    0xc2100024
++#define ixCG_THERMAL_INT_CTRL                                                   0xc2100028
++#define ixCG_THERMAL_INT_STATUS                                                 0xc210002c
++#define ixCG_THERMAL_CTRL                                                       0xc0300004
++#define ixCG_THERMAL_STATUS                                                     0xc0300008
++#define ixCG_THERMAL_INT                                                        0xc030000c
++#define ixCG_MULT_THERMAL_CTRL                                                  0xc0300010
++#define ixCG_MULT_THERMAL_STATUS                                                0xc0300014
++#define ixCG_FDO_CTRL0                                                          0xc0300064
++#define ixCG_FDO_CTRL1                                                          0xc0300068
++#define ixCG_FDO_CTRL2                                                          0xc030006c
++#define ixCG_TACH_CTRL                                                          0xc0300070
++#define ixCG_TACH_STATUS                                                        0xc0300074
++#define ixCC_THM_STRAPS0                                                        0xc0300080
++#define ixTHM_TMON0_RDIL0_DATA                                                  0xc0300100
++#define ixTHM_TMON0_RDIL1_DATA                                                  0xc0300104
++#define ixTHM_TMON0_RDIL2_DATA                                                  0xc0300108
++#define ixTHM_TMON0_RDIL3_DATA                                                  0xc030010c
++#define ixTHM_TMON0_RDIL4_DATA                                                  0xc0300110
++#define ixTHM_TMON0_RDIL5_DATA                                                  0xc0300114
++#define ixTHM_TMON0_RDIL6_DATA                                                  0xc0300118
++#define ixTHM_TMON0_RDIL7_DATA                                                  0xc030011c
++#define ixTHM_TMON0_RDIL8_DATA                                                  0xc0300120
++#define ixTHM_TMON0_RDIL9_DATA                                                  0xc0300124
++#define ixTHM_TMON0_RDIL10_DATA                                                 0xc0300128
++#define ixTHM_TMON0_RDIL11_DATA                                                 0xc030012c
++#define ixTHM_TMON0_RDIL12_DATA                                                 0xc0300130
++#define ixTHM_TMON0_RDIL13_DATA                                                 0xc0300134
++#define ixTHM_TMON0_RDIL14_DATA                                                 0xc0300138
++#define ixTHM_TMON0_RDIL15_DATA                                                 0xc030013c
++#define ixTHM_TMON0_RDIR0_DATA                                                  0xc0300140
++#define ixTHM_TMON0_RDIR1_DATA                                                  0xc0300144
++#define ixTHM_TMON0_RDIR2_DATA                                                  0xc0300148
++#define ixTHM_TMON0_RDIR3_DATA                                                  0xc030014c
++#define ixTHM_TMON0_RDIR4_DATA                                                  0xc0300150
++#define ixTHM_TMON0_RDIR5_DATA                                                  0xc0300154
++#define ixTHM_TMON0_RDIR6_DATA                                                  0xc0300158
++#define ixTHM_TMON0_RDIR7_DATA                                                  0xc030015c
++#define ixTHM_TMON0_RDIR8_DATA                                                  0xc0300160
++#define ixTHM_TMON0_RDIR9_DATA                                                  0xc0300164
++#define ixTHM_TMON0_RDIR10_DATA                                                 0xc0300168
++#define ixTHM_TMON0_RDIR11_DATA                                                 0xc030016c
++#define ixTHM_TMON0_RDIR12_DATA                                                 0xc0300170
++#define ixTHM_TMON0_RDIR13_DATA                                                 0xc0300174
++#define ixTHM_TMON0_RDIR14_DATA                                                 0xc0300178
++#define ixTHM_TMON0_RDIR15_DATA                                                 0xc030017c
++#define ixTHM_TMON1_RDIL0_DATA                                                  0xc0300180
++#define ixTHM_TMON1_RDIL1_DATA                                                  0xc0300184
++#define ixTHM_TMON1_RDIL2_DATA                                                  0xc0300188
++#define ixTHM_TMON1_RDIL3_DATA                                                  0xc030018c
++#define ixTHM_TMON1_RDIL4_DATA                                                  0xc0300190
++#define ixTHM_TMON1_RDIL5_DATA                                                  0xc0300194
++#define ixTHM_TMON1_RDIL6_DATA                                                  0xc0300198
++#define ixTHM_TMON1_RDIL7_DATA                                                  0xc030019c
++#define ixTHM_TMON1_RDIL8_DATA                                                  0xc03001a0
++#define ixTHM_TMON1_RDIL9_DATA                                                  0xc03001a4
++#define ixTHM_TMON1_RDIL10_DATA                                                 0xc03001a8
++#define ixTHM_TMON1_RDIL11_DATA                                                 0xc03001ac
++#define ixTHM_TMON1_RDIL12_DATA                                                 0xc03001b0
++#define ixTHM_TMON1_RDIL13_DATA                                                 0xc03001b4
++#define ixTHM_TMON1_RDIL14_DATA                                                 0xc03001b8
++#define ixTHM_TMON1_RDIL15_DATA                                                 0xc03001bc
++#define ixTHM_TMON1_RDIR0_DATA                                                  0xc03001c0
++#define ixTHM_TMON1_RDIR1_DATA                                                  0xc03001c4
++#define ixTHM_TMON1_RDIR2_DATA                                                  0xc03001c8
++#define ixTHM_TMON1_RDIR3_DATA                                                  0xc03001cc
++#define ixTHM_TMON1_RDIR4_DATA                                                  0xc03001d0
++#define ixTHM_TMON1_RDIR5_DATA                                                  0xc03001d4
++#define ixTHM_TMON1_RDIR6_DATA                                                  0xc03001d8
++#define ixTHM_TMON1_RDIR7_DATA                                                  0xc03001dc
++#define ixTHM_TMON1_RDIR8_DATA                                                  0xc03001e0
++#define ixTHM_TMON1_RDIR9_DATA                                                  0xc03001e4
++#define ixTHM_TMON1_RDIR10_DATA                                                 0xc03001e8
++#define ixTHM_TMON1_RDIR11_DATA                                                 0xc03001ec
++#define ixTHM_TMON1_RDIR12_DATA                                                 0xc03001f0
++#define ixTHM_TMON1_RDIR13_DATA                                                 0xc03001f4
++#define ixTHM_TMON1_RDIR14_DATA                                                 0xc03001f8
++#define ixTHM_TMON1_RDIR15_DATA                                                 0xc03001fc
++#define ixTHM_TMON0_INT_DATA                                                    0xc0300300
++#define ixTHM_TMON1_INT_DATA                                                    0xc0300304
++#define ixTHM_TMON0_DEBUG                                                       0xc0300310
++#define ixTHM_TMON1_DEBUG                                                       0xc0300314
++#define ixGENERAL_PWRMGT                                                        0xc0200000
++#define ixCNB_PWRMGT_CNTL                                                       0xc0200004
++#define ixSCLK_PWRMGT_CNTL                                                      0xc0200008
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xc0200014
++#define ixCG_FREQ_TRAN_VOTING_0                                                 0xc02001a8
++#define ixCG_FREQ_TRAN_VOTING_1                                                 0xc02001ac
++#define ixCG_FREQ_TRAN_VOTING_2                                                 0xc02001b0
++#define ixCG_FREQ_TRAN_VOTING_3                                                 0xc02001b4
++#define ixCG_FREQ_TRAN_VOTING_4                                                 0xc02001b8
++#define ixCG_FREQ_TRAN_VOTING_5                                                 0xc02001bc
++#define ixCG_FREQ_TRAN_VOTING_6                                                 0xc02001c0
++#define ixCG_FREQ_TRAN_VOTING_7                                                 0xc02001c4
++#define ixPLL_TEST_CNTL                                                         0xc020003c
++#define ixCG_STATIC_SCREEN_PARAMETER                                            0xc0200044
++#define ixCG_DISPLAY_GAP_CNTL                                                   0xc0200060
++#define ixCG_DISPLAY_GAP_CNTL2                                                  0xc0200230
++#define ixCG_ACPI_CNTL                                                          0xc0200064
++#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xc0200080
++#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xc0200084
++#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xc020009c
++#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xc0200088
++#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xc020008c
++#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xc0200310
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xc02000f0
++#define ixCG_ULV_PARAMETER                                                      0xc020015c
++#define ixSCLK_MIN_DIV                                                          0xc0200308
++#define ixLCAC_SX0_CNTL                                                         0xc0400d00
++#define ixLCAC_SX0_OVR_SEL                                                      0xc0400d04
++#define ixLCAC_SX0_OVR_VAL                                                      0xc0400d08
++#define ixLCAC_MC0_CNTL                                                         0xc0400d30
++#define ixLCAC_MC0_OVR_SEL                                                      0xc0400d34
++#define ixLCAC_MC0_OVR_VAL                                                      0xc0400d38
++#define ixLCAC_MC1_CNTL                                                         0xc0400d3c
++#define ixLCAC_MC1_OVR_SEL                                                      0xc0400d40
++#define ixLCAC_MC1_OVR_VAL                                                      0xc0400d44
++#define ixLCAC_MC2_CNTL                                                         0xc0400d48
++#define ixLCAC_MC2_OVR_SEL                                                      0xc0400d4c
++#define ixLCAC_MC2_OVR_VAL                                                      0xc0400d50
++#define ixLCAC_MC3_CNTL                                                         0xc0400d54
++#define ixLCAC_MC3_OVR_SEL                                                      0xc0400d58
++#define ixLCAC_MC3_OVR_VAL                                                      0xc0400d5c
++#define ixLCAC_CPL_CNTL                                                         0xc0400d80
++#define ixLCAC_CPL_OVR_SEL                                                      0xc0400d84
++#define ixLCAC_CPL_OVR_VAL                                                      0xc0400d88
++#define mmROM_SMC_IND_INDEX                                                     0x80
++#define mmROM0_ROM_SMC_IND_INDEX                                                0x80
++#define mmROM1_ROM_SMC_IND_INDEX                                                0x82
++#define mmROM2_ROM_SMC_IND_INDEX                                                0x84
++#define mmROM3_ROM_SMC_IND_INDEX                                                0x86
++#define mmROM_SMC_IND_DATA                                                      0x81
++#define mmROM0_ROM_SMC_IND_DATA                                                 0x81
++#define mmROM1_ROM_SMC_IND_DATA                                                 0x83
++#define mmROM2_ROM_SMC_IND_DATA                                                 0x85
++#define mmROM3_ROM_SMC_IND_DATA                                                 0x87
++#define ixROM_CNTL                                                              0xc0600000
++#define ixPAGE_MIRROR_CNTL                                                      0xc0600004
++#define ixROM_STATUS                                                            0xc0600008
++#define ixCGTT_ROM_CLK_CTRL0                                                    0xc060000c
++#define ixROM_INDEX                                                             0xc0600010
++#define ixROM_DATA                                                              0xc0600014
++#define ixROM_START                                                             0xc0600018
++#define ixROM_SW_CNTL                                                           0xc060001c
++#define ixROM_SW_STATUS                                                         0xc0600020
++#define ixROM_SW_COMMAND                                                        0xc0600024
++#define ixROM_SW_DATA_1                                                         0xc0600028
++#define ixROM_SW_DATA_2                                                         0xc060002c
++#define ixROM_SW_DATA_3                                                         0xc0600030
++#define ixROM_SW_DATA_4                                                         0xc0600034
++#define ixROM_SW_DATA_5                                                         0xc0600038
++#define ixROM_SW_DATA_6                                                         0xc060003c
++#define ixROM_SW_DATA_7                                                         0xc0600040
++#define ixROM_SW_DATA_8                                                         0xc0600044
++#define ixROM_SW_DATA_9                                                         0xc0600048
++#define ixROM_SW_DATA_10                                                        0xc060004c
++#define ixROM_SW_DATA_11                                                        0xc0600050
++#define ixROM_SW_DATA_12                                                        0xc0600054
++#define ixROM_SW_DATA_13                                                        0xc0600058
++#define ixROM_SW_DATA_14                                                        0xc060005c
++#define ixROM_SW_DATA_15                                                        0xc0600060
++#define ixROM_SW_DATA_16                                                        0xc0600064
++#define ixROM_SW_DATA_17                                                        0xc0600068
++#define ixROM_SW_DATA_18                                                        0xc060006c
++#define ixROM_SW_DATA_19                                                        0xc0600070
++#define ixROM_SW_DATA_20                                                        0xc0600074
++#define ixROM_SW_DATA_21                                                        0xc0600078
++#define ixROM_SW_DATA_22                                                        0xc060007c
++#define ixROM_SW_DATA_23                                                        0xc0600080
++#define ixROM_SW_DATA_24                                                        0xc0600084
++#define ixROM_SW_DATA_25                                                        0xc0600088
++#define ixROM_SW_DATA_26                                                        0xc060008c
++#define ixROM_SW_DATA_27                                                        0xc0600090
++#define ixROM_SW_DATA_28                                                        0xc0600094
++#define ixROM_SW_DATA_29                                                        0xc0600098
++#define ixROM_SW_DATA_30                                                        0xc060009c
++#define ixROM_SW_DATA_31                                                        0xc06000a0
++#define ixROM_SW_DATA_32                                                        0xc06000a4
++#define ixROM_SW_DATA_33                                                        0xc06000a8
++#define ixROM_SW_DATA_34                                                        0xc06000ac
++#define ixROM_SW_DATA_35                                                        0xc06000b0
++#define ixROM_SW_DATA_36                                                        0xc06000b4
++#define ixROM_SW_DATA_37                                                        0xc06000b8
++#define ixROM_SW_DATA_38                                                        0xc06000bc
++#define ixROM_SW_DATA_39                                                        0xc06000c0
++#define ixROM_SW_DATA_40                                                        0xc06000c4
++#define ixROM_SW_DATA_41                                                        0xc06000c8
++#define ixROM_SW_DATA_42                                                        0xc06000cc
++#define ixROM_SW_DATA_43                                                        0xc06000d0
++#define ixROM_SW_DATA_44                                                        0xc06000d4
++#define ixROM_SW_DATA_45                                                        0xc06000d8
++#define ixROM_SW_DATA_46                                                        0xc06000dc
++#define ixROM_SW_DATA_47                                                        0xc06000e0
++#define ixROM_SW_DATA_48                                                        0xc06000e4
++#define ixROM_SW_DATA_49                                                        0xc06000e8
++#define ixROM_SW_DATA_50                                                        0xc06000ec
++#define ixROM_SW_DATA_51                                                        0xc06000f0
++#define ixROM_SW_DATA_52                                                        0xc06000f4
++#define ixROM_SW_DATA_53                                                        0xc06000f8
++#define ixROM_SW_DATA_54                                                        0xc06000fc
++#define ixROM_SW_DATA_55                                                        0xc0600100
++#define ixROM_SW_DATA_56                                                        0xc0600104
++#define ixROM_SW_DATA_57                                                        0xc0600108
++#define ixROM_SW_DATA_58                                                        0xc060010c
++#define ixROM_SW_DATA_59                                                        0xc0600110
++#define ixROM_SW_DATA_60                                                        0xc0600114
++#define ixROM_SW_DATA_61                                                        0xc0600118
++#define ixROM_SW_DATA_62                                                        0xc060011c
++#define ixROM_SW_DATA_63                                                        0xc0600120
++#define ixROM_SW_DATA_64                                                        0xc0600124
++
++#endif /* SMU_7_1_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
+new file mode 100644
+index 0000000..61face1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
+@@ -0,0 +1,1191 @@
++/*
++ * SMU_7_1_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_0_ENUM_H
++#define SMU_7_1_0_ENUM_H
++
++#define CG_SRBM_START_ADDR                        0x600
++#define CG_SRBM_END_ADDR                          0x8ff
++#define RCU_CCF_DWORDS0                           0x28
++#define RCU_CCF_BITS0                             0x500
++#define RCU_CCF_DWORDS1                           0x7f
++#define RCU_CCF_BITS1                             0x1000
++#define RCU_SAM_BYTES                             0x40
++#define RCU_SAM_RTL_BYTES                         0x40
++#define KEYS_CHAIN_ADR                            0x0
++#define SAMU_KEY_SADR                             0xa0
++#define SAMU_KEY_EADR                             0xdf
++#define RCU_SMU_BYTES                             0x11
++#define RCU_SMU_RTL_BYTES                         0x11
++#define SMC_MSG_TEST                              0x1
++#define SMC_MSG_PHY_LN_OFF                        0x2
++#define SMC_MSG_PHY_LN_ON                         0x3
++#define SMC_MSG_DDI_PHY_OFF                       0x4
++#define SMC_MSG_DDI_PHY_ON                        0x5
++#define SMC_MSG_CASCADE_PLL_OFF                   0x6
++#define SMC_MSG_CASCADE_PLL_ON                    0x7
++#define SMC_MSG_PWR_OFF_x16                       0x8
++#define SMC_MSG_CONFIG_LCLK_DPM                   0x9
++#define SMC_MSG_FLUSH_DATA_CACHE                  0xa
++#define SMC_MSG_FLUSH_INSTRUCTION_CACHE           0xb
++#define SMC_MSG_CONFIG_VPC_ACCUMULATOR            0xc
++#define SMC_MSG_CONFIG_BAPM                       0xd
++#define SMC_MSG_CONFIG_TDC_LIMIT                  0xe
++#define SMC_MSG_CONFIG_LPMx                       0xf
++#define SMC_MSG_CONFIG_HTC_LIMIT                  0x10
++#define SMC_MSG_CONFIG_THERMAL_CNTL               0x11
++#define SMC_MSG_CONFIG_VOLTAGE_CNTL               0x12
++#define SMC_MSG_CONFIG_TDP_CNTL                   0x13
++#define SMC_MSG_EN_PM_CNTL                        0x14
++#define SMC_MSG_DIS_PM_CNTL                       0x15
++#define SMC_MSG_CONFIG_NBDPM                      0x16
++#define SMC_MSG_CONFIG_LOADLINE                   0x17
++#define SMC_MSG_ADJUST_LOADLINE                   0x18
++#define SMC_MSG_RESET                             0x20
++#define SMC_MSG_VOLTAGE                           0x25
++#define SMC_VERSION_MAJOR                         0x7
++#define SMC_VERSION_MINOR                         0x0
++#define SMC_HEADER_SIZE                           0x40
++#define ROM_SIGNATURE                             0xaa55
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++	ADDR_CONFIG_16_PIPE                              = 0x4,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_dco0                            = 0x2,
++	DBG_CLIENT_BLKID_wd                              = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_scf2                            = 0x5,
++	DBG_CLIENT_BLKID_spim3                           = 0x6,
++	DBG_CLIENT_BLKID_cb3                             = 0x7,
++	DBG_CLIENT_BLKID_sx0                             = 0x8,
++	DBG_CLIENT_BLKID_cb2                             = 0x9,
++	DBG_CLIENT_BLKID_bci1                            = 0xa,
++	DBG_CLIENT_BLKID_xdma                            = 0xb,
++	DBG_CLIENT_BLKID_bci0                            = 0xc,
++	DBG_CLIENT_BLKID_spim0                           = 0xd,
++	DBG_CLIENT_BLKID_mcd0                            = 0xe,
++	DBG_CLIENT_BLKID_mcc0                            = 0xf,
++	DBG_CLIENT_BLKID_cb0                             = 0x10,
++	DBG_CLIENT_BLKID_cb1                             = 0x11,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x12,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x13,
++	DBG_CLIENT_BLKID_cpf                             = 0x14,
++	DBG_CLIENT_BLKID_rlc                             = 0x15,
++	DBG_CLIENT_BLKID_grbm                            = 0x16,
++	DBG_CLIENT_BLKID_bif                             = 0x17,
++	DBG_CLIENT_BLKID_scf1                            = 0x18,
++	DBG_CLIENT_BLKID_sam                             = 0x19,
++	DBG_CLIENT_BLKID_mcd4                            = 0x1a,
++	DBG_CLIENT_BLKID_mcc4                            = 0x1b,
++	DBG_CLIENT_BLKID_gmcon                           = 0x1c,
++	DBG_CLIENT_BLKID_mcb                             = 0x1d,
++	DBG_CLIENT_BLKID_vgt0                            = 0x1e,
++	DBG_CLIENT_BLKID_pc0                             = 0x1f,
++	DBG_CLIENT_BLKID_spim1                           = 0x20,
++	DBG_CLIENT_BLKID_bci2                            = 0x21,
++	DBG_CLIENT_BLKID_mcd6                            = 0x22,
++	DBG_CLIENT_BLKID_mcc6                            = 0x23,
++	DBG_CLIENT_BLKID_mcd3                            = 0x24,
++	DBG_CLIENT_BLKID_mcc3                            = 0x25,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x26,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x27,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x28,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x29,
++	DBG_CLIENT_BLKID_spim2                           = 0x2a,
++	DBG_CLIENT_BLKID_ds                              = 0x2b,
++	DBG_CLIENT_BLKID_srbm                            = 0x2c,
++	DBG_CLIENT_BLKID_ih                              = 0x2d,
++	DBG_CLIENT_BLKID_sem                             = 0x2e,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x2f,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x30,
++	DBG_CLIENT_BLKID_hdp                             = 0x31,
++	DBG_CLIENT_BLKID_acp_0                           = 0x32,
++	DBG_CLIENT_BLKID_acp_1                           = 0x33,
++	DBG_CLIENT_BLKID_vceb_0                          = 0x34,
++	DBG_CLIENT_BLKID_vceb_1                          = 0x35,
++	DBG_CLIENT_BLKID_vceb_2                          = 0x36,
++	DBG_CLIENT_BLKID_mcd2                            = 0x37,
++	DBG_CLIENT_BLKID_mcc2                            = 0x38,
++	DBG_CLIENT_BLKID_scf3                            = 0x39,
++	DBG_CLIENT_BLKID_bci3                            = 0x3a,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3b,
++	DBG_CLIENT_BLKID_mcc5                            = 0x3c,
++	DBG_CLIENT_BLKID_vgt2                            = 0x3d,
++	DBG_CLIENT_BLKID_pc2                             = 0x3e,
++	DBG_CLIENT_BLKID_smu_0                           = 0x3f,
++	DBG_CLIENT_BLKID_smu_1                           = 0x40,
++	DBG_CLIENT_BLKID_smu_2                           = 0x41,
++	DBG_CLIENT_BLKID_vcea_0                          = 0x42,
++	DBG_CLIENT_BLKID_vcea_1                          = 0x43,
++	DBG_CLIENT_BLKID_vcea_2                          = 0x44,
++	DBG_CLIENT_BLKID_vcea_3                          = 0x45,
++	DBG_CLIENT_BLKID_vcea_4                          = 0x46,
++	DBG_CLIENT_BLKID_vcea_5                          = 0x47,
++	DBG_CLIENT_BLKID_vcea_6                          = 0x48,
++	DBG_CLIENT_BLKID_scf0                            = 0x49,
++	DBG_CLIENT_BLKID_vgt1                            = 0x4a,
++	DBG_CLIENT_BLKID_pc1                             = 0x4b,
++	DBG_CLIENT_BLKID_gdc_0                           = 0x4c,
++	DBG_CLIENT_BLKID_gdc_1                           = 0x4d,
++	DBG_CLIENT_BLKID_gdc_2                           = 0x4e,
++	DBG_CLIENT_BLKID_gdc_3                           = 0x4f,
++	DBG_CLIENT_BLKID_gdc_4                           = 0x50,
++	DBG_CLIENT_BLKID_gdc_5                           = 0x51,
++	DBG_CLIENT_BLKID_gdc_6                           = 0x52,
++	DBG_CLIENT_BLKID_gdc_7                           = 0x53,
++	DBG_CLIENT_BLKID_gdc_8                           = 0x54,
++	DBG_CLIENT_BLKID_gdc_9                           = 0x55,
++	DBG_CLIENT_BLKID_gdc_10                          = 0x56,
++	DBG_CLIENT_BLKID_gdc_11                          = 0x57,
++	DBG_CLIENT_BLKID_gdc_12                          = 0x58,
++	DBG_CLIENT_BLKID_gdc_13                          = 0x59,
++	DBG_CLIENT_BLKID_gdc_14                          = 0x5a,
++	DBG_CLIENT_BLKID_gdc_15                          = 0x5b,
++	DBG_CLIENT_BLKID_gdc_16                          = 0x5c,
++	DBG_CLIENT_BLKID_gdc_17                          = 0x5d,
++	DBG_CLIENT_BLKID_gdc_18                          = 0x5e,
++	DBG_CLIENT_BLKID_gdc_19                          = 0x5f,
++	DBG_CLIENT_BLKID_gdc_20                          = 0x60,
++	DBG_CLIENT_BLKID_gdc_21                          = 0x61,
++	DBG_CLIENT_BLKID_gdc_22                          = 0x62,
++	DBG_CLIENT_BLKID_vgt3                            = 0x63,
++	DBG_CLIENT_BLKID_pc3                             = 0x64,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x65,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x66,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x67,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x68,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x69,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x6a,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x6b,
++	DBG_CLIENT_BLKID_mcd7                            = 0x6c,
++	DBG_CLIENT_BLKID_mcc7                            = 0x6d,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x6e,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x6f,
++	DBG_CLIENT_BLKID_gck                             = 0x70,
++	DBG_CLIENT_BLKID_mcd1                            = 0x71,
++	DBG_CLIENT_BLKID_mcc1                            = 0x72,
++	DBG_CLIENT_BLKID_cb101                           = 0x73,
++	DBG_CLIENT_BLKID_cb103                           = 0x74,
++	DBG_CLIENT_BLKID_sx10                            = 0x75,
++	DBG_CLIENT_BLKID_cb102                           = 0x76,
++	DBG_CLIENT_BLKID_cb002                           = 0x77,
++	DBG_CLIENT_BLKID_cb100                           = 0x78,
++	DBG_CLIENT_BLKID_cb000                           = 0x79,
++	DBG_CLIENT_BLKID_pa00                            = 0x7a,
++	DBG_CLIENT_BLKID_pa10                            = 0x7b,
++	DBG_CLIENT_BLKID_ia0                             = 0x7c,
++	DBG_CLIENT_BLKID_ia1                             = 0x7d,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x7e,
++	DBG_CLIENT_BLKID_cb001                           = 0x7f,
++	DBG_CLIENT_BLKID_cb003                           = 0x80,
++	DBG_CLIENT_BLKID_sx00                            = 0x81,
++	DBG_CLIENT_BLKID_sx20                            = 0x82,
++	DBG_CLIENT_BLKID_cb203                           = 0x83,
++	DBG_CLIENT_BLKID_cb201                           = 0x84,
++	DBG_CLIENT_BLKID_cb302                           = 0x85,
++	DBG_CLIENT_BLKID_cb202                           = 0x86,
++	DBG_CLIENT_BLKID_cb300                           = 0x87,
++	DBG_CLIENT_BLKID_cb200                           = 0x88,
++	DBG_CLIENT_BLKID_pa01                            = 0x89,
++	DBG_CLIENT_BLKID_pa11                            = 0x8a,
++	DBG_CLIENT_BLKID_sx30                            = 0x8b,
++	DBG_CLIENT_BLKID_cb303                           = 0x8c,
++	DBG_CLIENT_BLKID_cb301                           = 0x8d,
++	DBG_CLIENT_BLKID_dco                             = 0x8e,
++	DBG_CLIENT_BLKID_scb0                            = 0x8f,
++	DBG_CLIENT_BLKID_scb1                            = 0x90,
++	DBG_CLIENT_BLKID_scb2                            = 0x91,
++	DBG_CLIENT_BLKID_scb3                            = 0x92,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x93,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x94,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_SNORM_OGL                         = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_SNORM_OGL                         = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_UBNORM                            = 0xa,
++	IMG_NUM_FORMAT_UBNORM_OGL                        = 0xb,
++	IMG_NUM_FORMAT_UBINT                             = 0xc,
++	IMG_NUM_FORMAT_UBSCALED                          = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++	TCC_CACHE_POLICY_BYPASS                          = 0x2,
++} TCC_CACHE_POLICIES;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++
++#endif /* SMU_7_1_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
+new file mode 100644
+index 0000000..cd78930
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
+@@ -0,0 +1,5648 @@
++/*
++ * SMU_7_1_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_0_SH_MASK_H
++#define SMU_7_1_0_SH_MASK_H
++
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
++#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
++#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
++#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
++#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
++#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
++#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
++#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
++#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
++#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
++#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
++#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
++#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
++#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
++#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
++#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
++#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
++#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
++#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
++#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
++#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
++#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
++#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
++#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
++#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
++#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
++#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
++#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
++#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
++#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
++#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_0__SMC_RESP_MASK 0xffff
++#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_1__SMC_RESP_MASK 0xffff
++#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_2__SMC_RESP_MASK 0xffff
++#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_3__SMC_RESP_MASK 0xffff
++#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_4__SMC_RESP_MASK 0xffff
++#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_5__SMC_RESP_MASK 0xffff
++#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_6__SMC_RESP_MASK 0xffff
++#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_7__SMC_RESP_MASK 0xffff
++#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_8__SMC_RESP_MASK 0xffff
++#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_9__SMC_RESP_MASK 0xffff
++#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_10__SMC_RESP_MASK 0xffff
++#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_11__SMC_RESP_MASK 0xffff
++#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
++#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
++#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
++#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
++#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
++#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
++#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
++#define SMC_PC_C__smc_pc_c__SHIFT 0x0
++#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
++#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
++#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
++#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
++#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
++#define GPIOPAD_A__GPIO_A__SHIFT 0x0
++#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
++#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
++#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
++#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
++#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
++#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
++#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
++#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
++#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
++#define CG_FPS_CNT__FPS_CNT_MASK 0xff
++#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
++#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
++#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
++#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
++#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
++#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
++#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
++#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
++#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
++#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
++#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
++#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
++#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
++#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
++#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
++#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
++#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
++#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
++#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
++#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
++#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
++#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
++#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
++#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
++#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
++#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
++#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
++#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
++#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
++#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
++#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
++#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
++#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
++#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
++#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
++#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
++#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
++#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
++#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
++#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
++#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
++#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
++#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
++#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
++#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
++#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
++#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
++#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
++#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
++#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
++#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
++#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
++#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
++#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
++#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
++#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
++#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
++#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
++#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
++#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
++#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
++#define SMU_STATUS__SMU_DONE_MASK 0x1
++#define SMU_STATUS__SMU_DONE__SHIFT 0x0
++#define SMU_STATUS__SMU_PASS_MASK 0x2
++#define SMU_STATUS__SMU_PASS__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
++#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
++#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
++#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
++#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
++#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
++#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
++#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
++#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
++#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
++#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
++#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
++#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
++#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
++#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
++#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
++#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
++#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
++#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
++#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
++#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
++#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
++#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
++#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
++#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
++#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
++#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
++#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
++#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
++#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
++#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
++#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
++#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
++#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
++#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
++#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
++#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
++#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
++#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
++#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
++#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
++#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
++#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
++#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
++#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
++#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
++#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
++#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
++#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
++#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
++#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
++#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
++#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
++#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
++#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
++#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
++#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
++#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
++#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
++#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
++#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
++#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
++#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
++#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
++#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
++#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
++#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
++#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
++#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
++#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
++#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
++#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
++#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
++#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
++#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
++#define DPM_TABLE_69__MasterDeepSleepControl_MASK 0xff
++#define DPM_TABLE_69__MasterDeepSleepControl__SHIFT 0x0
++#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
++#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
++#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
++#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
++#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
++#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
++#define DPM_TABLE_70__DefaultTdp_MASK 0xffff
++#define DPM_TABLE_70__DefaultTdp__SHIFT 0x0
++#define DPM_TABLE_70__TargetTdp_MASK 0xffff0000
++#define DPM_TABLE_70__TargetTdp__SHIFT 0x10
++#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
++#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
++#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
++#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
++#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
++#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
++#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
++#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
++#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
++#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
++#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
++#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_79__GraphicsLevel_0_padding1_MASK 0xff0000
++#define DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT 0x10
++#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
++#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
++#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
++#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
++#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
++#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
++#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_93__GraphicsLevel_1_padding1_MASK 0xff0000
++#define DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT 0x10
++#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
++#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
++#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
++#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
++#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
++#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
++#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_107__GraphicsLevel_2_padding1_MASK 0xff0000
++#define DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT 0x10
++#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
++#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
++#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
++#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
++#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
++#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
++#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_121__GraphicsLevel_3_padding1_MASK 0xff0000
++#define DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT 0x10
++#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
++#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
++#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
++#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
++#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
++#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
++#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_135__GraphicsLevel_4_padding1_MASK 0xff0000
++#define DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT 0x10
++#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
++#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
++#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
++#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
++#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
++#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
++#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
++#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
++#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
++#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
++#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_5_padding1_MASK 0xff0000
++#define DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT 0x10
++#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
++#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
++#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
++#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
++#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
++#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
++#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
++#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
++#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
++#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
++#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_6_padding1_MASK 0xff0000
++#define DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT 0x10
++#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
++#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
++#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
++#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
++#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
++#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
++#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
++#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
++#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
++#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
++#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_177__GraphicsLevel_7_padding1_MASK 0xff0000
++#define DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT 0x10
++#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
++#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
++#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
++#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
++#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
++#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
++#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
++#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
++#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
++#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
++#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
++#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
++#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
++#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
++#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
++#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
++#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
++#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
++#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
++#define DPM_TABLE_195__MemoryACPILevel_padding1_MASK 0xff
++#define DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT 0x0
++#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
++#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
++#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
++#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
++#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
++#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
++#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
++#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_213__MemoryLevel_0_padding1_MASK 0xff
++#define DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT 0x0
++#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
++#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
++#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
++#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
++#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
++#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
++#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
++#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_231__MemoryLevel_1_padding1_MASK 0xff
++#define DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT 0x0
++#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
++#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
++#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
++#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
++#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
++#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
++#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
++#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_249__MemoryLevel_2_padding1_MASK 0xff
++#define DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT 0x0
++#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
++#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
++#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
++#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
++#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
++#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
++#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
++#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_267__MemoryLevel_3_padding1_MASK 0xff
++#define DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT 0x0
++#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
++#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
++#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
++#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
++#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
++#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
++#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
++#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
++#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
++#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
++#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
++#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
++#define DPM_TABLE_285__MemoryLevel_4_padding1_MASK 0xff
++#define DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT 0x0
++#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
++#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
++#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
++#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
++#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
++#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
++#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
++#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
++#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
++#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
++#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
++#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
++#define DPM_TABLE_303__MemoryLevel_5_padding1_MASK 0xff
++#define DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT 0x0
++#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
++#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
++#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
++#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
++#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
++#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
++#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
++#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
++#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
++#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
++#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
++#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
++#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
++#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
++#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
++#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
++#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
++#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
++#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
++#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
++#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
++#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
++#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
++#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
++#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
++#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
++#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
++#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
++#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
++#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
++#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
++#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
++#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
++#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
++#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
++#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
++#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
++#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
++#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
++#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
++#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
++#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
++#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
++#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
++#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
++#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
++#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
++#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
++#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
++#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
++#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
++#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
++#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
++#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
++#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
++#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
++#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
++#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
++#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
++#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
++#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
++#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
++#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
++#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
++#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
++#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
++#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
++#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
++#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
++#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
++#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
++#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
++#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
++#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
++#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
++#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
++#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
++#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
++#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
++#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
++#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
++#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
++#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
++#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
++#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
++#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
++#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
++#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
++#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
++#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
++#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
++#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
++#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
++#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
++#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
++#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
++#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
++#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
++#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
++#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
++#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
++#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
++#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
++#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
++#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
++#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
++#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
++#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
++#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
++#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
++#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
++#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
++#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
++#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
++#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
++#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
++#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
++#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
++#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
++#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
++#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
++#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
++#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
++#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
++#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
++#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
++#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
++#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
++#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
++#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
++#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
++#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
++#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
++#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
++#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
++#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
++#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
++#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
++#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
++#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
++#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
++#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
++#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
++#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
++#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
++#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
++#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
++#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
++#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
++#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
++#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
++#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
++#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
++#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
++#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
++#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
++#define DPM_TABLE_443__Smio_0__SHIFT 0x0
++#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
++#define DPM_TABLE_444__Smio_1__SHIFT 0x0
++#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
++#define DPM_TABLE_445__Smio_2__SHIFT 0x0
++#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
++#define DPM_TABLE_446__Smio_3__SHIFT 0x0
++#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
++#define DPM_TABLE_447__Smio_4__SHIFT 0x0
++#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
++#define DPM_TABLE_448__Smio_5__SHIFT 0x0
++#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
++#define DPM_TABLE_449__Smio_6__SHIFT 0x0
++#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
++#define DPM_TABLE_450__Smio_7__SHIFT 0x0
++#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
++#define DPM_TABLE_451__Smio_8__SHIFT 0x0
++#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
++#define DPM_TABLE_452__Smio_9__SHIFT 0x0
++#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
++#define DPM_TABLE_453__Smio_10__SHIFT 0x0
++#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
++#define DPM_TABLE_454__Smio_11__SHIFT 0x0
++#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
++#define DPM_TABLE_455__Smio_12__SHIFT 0x0
++#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
++#define DPM_TABLE_456__Smio_13__SHIFT 0x0
++#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
++#define DPM_TABLE_457__Smio_14__SHIFT 0x0
++#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
++#define DPM_TABLE_458__Smio_15__SHIFT 0x0
++#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
++#define DPM_TABLE_459__Smio_16__SHIFT 0x0
++#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
++#define DPM_TABLE_460__Smio_17__SHIFT 0x0
++#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
++#define DPM_TABLE_461__Smio_18__SHIFT 0x0
++#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
++#define DPM_TABLE_462__Smio_19__SHIFT 0x0
++#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
++#define DPM_TABLE_463__Smio_20__SHIFT 0x0
++#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
++#define DPM_TABLE_464__Smio_21__SHIFT 0x0
++#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
++#define DPM_TABLE_465__Smio_22__SHIFT 0x0
++#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
++#define DPM_TABLE_466__Smio_23__SHIFT 0x0
++#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
++#define DPM_TABLE_467__Smio_24__SHIFT 0x0
++#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
++#define DPM_TABLE_468__Smio_25__SHIFT 0x0
++#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
++#define DPM_TABLE_469__Smio_26__SHIFT 0x0
++#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
++#define DPM_TABLE_470__Smio_27__SHIFT 0x0
++#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
++#define DPM_TABLE_471__Smio_28__SHIFT 0x0
++#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
++#define DPM_TABLE_472__Smio_29__SHIFT 0x0
++#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
++#define DPM_TABLE_473__Smio_30__SHIFT 0x0
++#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
++#define DPM_TABLE_474__Smio_31__SHIFT 0x0
++#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
++#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
++#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
++#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
++#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
++#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
++#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
++#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
++#define DPM_TABLE_476__SAMUInterval_MASK 0xff
++#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
++#define DPM_TABLE_476__ACPInterval_MASK 0xff00
++#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
++#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
++#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
++#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
++#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
++#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
++#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
++#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
++#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
++#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
++#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
++#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
++#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
++#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
++#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
++#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
++#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
++#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
++#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
++#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
++#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
++#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
++#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
++#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
++#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
++#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
++#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
++#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
++#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
++#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
++#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
++#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
++#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
++#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
++#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
++#define DPM_TABLE_482__DTEMode_MASK 0xff
++#define DPM_TABLE_482__DTEMode__SHIFT 0x0
++#define DPM_TABLE_482__DTEInterval_MASK 0xff00
++#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
++#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
++#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
++#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
++#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
++#define DPM_TABLE_483__ThermGpio_MASK 0xff
++#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
++#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
++#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
++#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
++#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
++#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
++#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
++#define DPM_TABLE_484__PPM_TemperatureLimit_MASK 0xffff
++#define DPM_TABLE_484__PPM_TemperatureLimit__SHIFT 0x0
++#define DPM_TABLE_484__PPM_PkgPwrLimit_MASK 0xffff0000
++#define DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT 0x10
++#define DPM_TABLE_485__TargetTdp_MASK 0xffff
++#define DPM_TABLE_485__TargetTdp__SHIFT 0x0
++#define DPM_TABLE_485__DefaultTdp_MASK 0xffff0000
++#define DPM_TABLE_485__DefaultTdp__SHIFT 0x10
++#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
++#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
++#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
++#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
++#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
++#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
++#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
++#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
++#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
++#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
++#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
++#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
++#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
++#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
++#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
++#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
++#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
++#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
++#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
++#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
++#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
++#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
++#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
++#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
++#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
++#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
++#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
++#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
++#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
++#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
++#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
++#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
++#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
++#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
++#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
++#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
++#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
++#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
++#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
++#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
++#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
++#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
++#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
++#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
++#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
++#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
++#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
++#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
++#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
++#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
++#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
++#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
++#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
++#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
++#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
++#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
++#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
++#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
++#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
++#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
++#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
++#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
++#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
++#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
++#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
++#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
++#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
++#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
++#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
++#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
++#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
++#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
++#define DPM_TABLE_503__BootVddci_MASK 0xffff
++#define DPM_TABLE_503__BootVddci__SHIFT 0x0
++#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
++#define DPM_TABLE_503__BootVddc__SHIFT 0x10
++#define DPM_TABLE_504__padding_MASK 0xff
++#define DPM_TABLE_504__padding__SHIFT 0x0
++#define DPM_TABLE_504__PccGpio_MASK 0xff00
++#define DPM_TABLE_504__PccGpio__SHIFT 0x8
++#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
++#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
++#define DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK 0xffffffff
++#define DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT 0x0
++#define DPM_TABLE_506__LowSclkInterruptThreshold_MASK 0xffffffff
++#define DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT 0x0
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
++#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
++#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
++#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
++#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
++#define TDC_STATUS__VDD_Boost_MASK 0xff
++#define TDC_STATUS__VDD_Boost__SHIFT 0x0
++#define TDC_STATUS__VDD_Throttle_MASK 0xff00
++#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
++#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
++#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
++#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
++#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
++#define TDC_MV_AVERAGE__IDD_MASK 0xffff
++#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
++#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
++#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
++#define TDC_VRM_LIMIT__IDD_MASK 0xffff
++#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
++#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
++#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
++#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
++#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
++#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
++#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
++#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
++#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
++#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
++#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
++#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
++#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
++#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
++#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
++#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
++#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
++#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
++#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
++#define FEATURE_STATUS__BAPM_ON_MASK 0x100
++#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
++#define FEATURE_STATUS__LPMX_ON_MASK 0x200
++#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
++#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
++#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
++#define FEATURE_STATUS__LHTC_ON_MASK 0x800
++#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
++#define FEATURE_STATUS__VPC_ON_MASK 0x1000
++#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
++#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
++#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
++#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
++#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
++#define FEATURE_STATUS__AVS_ON_MASK 0x10000
++#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
++#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
++#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
++#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
++#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
++#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
++#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
++#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
++#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
++#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
++#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
++#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
++#define FEATURE_STATUS__RESERVED__SHIFT 0x16
++#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18
++#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
++#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
++#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
++#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
++#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
++#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
++#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0
++#define FAN_TABLE_1__TempMin_MASK 0xffff
++#define FAN_TABLE_1__TempMin__SHIFT 0x0
++#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
++#define FAN_TABLE_1__FdoMode__SHIFT 0x10
++#define FAN_TABLE_2__TempMax_MASK 0xffff
++#define FAN_TABLE_2__TempMax__SHIFT 0x0
++#define FAN_TABLE_2__TempMed_MASK 0xffff0000
++#define FAN_TABLE_2__TempMed__SHIFT 0x10
++#define FAN_TABLE_3__Slope2_MASK 0xffff
++#define FAN_TABLE_3__Slope2__SHIFT 0x0
++#define FAN_TABLE_3__Slope1_MASK 0xffff0000
++#define FAN_TABLE_3__Slope1__SHIFT 0x10
++#define FAN_TABLE_4__HystUp_MASK 0xffff
++#define FAN_TABLE_4__HystUp__SHIFT 0x0
++#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
++#define FAN_TABLE_4__FdoMin__SHIFT 0x10
++#define FAN_TABLE_5__HystSlope_MASK 0xffff
++#define FAN_TABLE_5__HystSlope__SHIFT 0x0
++#define FAN_TABLE_5__HystDown_MASK 0xffff0000
++#define FAN_TABLE_5__HystDown__SHIFT 0x10
++#define FAN_TABLE_6__TempCurr_MASK 0xffff
++#define FAN_TABLE_6__TempCurr__SHIFT 0x0
++#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
++#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
++#define FAN_TABLE_7__PwmCurr_MASK 0xffff
++#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
++#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
++#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
++#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
++#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
++#define FAN_TABLE_9__Padding_MASK 0xff
++#define FAN_TABLE_9__Padding__SHIFT 0x0
++#define FAN_TABLE_9__TempSrc_MASK 0xff00
++#define FAN_TABLE_9__TempSrc__SHIFT 0x8
++#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
++#define FAN_TABLE_9__FdoMax__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_30__Reserved_2_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_30__Reserved_2__SHIFT 0x0
++#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
++#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
++#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
++#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
++#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
++#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
++#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
++#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
++#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
++#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
++#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
++#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
++#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
++#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
++#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
++#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
++#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
++#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
++#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
++#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
++#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
++#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
++#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
++#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
++#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
++#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
++#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
++#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
++#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
++#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
++#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
++#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
++#define PM_FUSES_5__VddCVid_3_MASK 0xff
++#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
++#define PM_FUSES_5__VddCVid_2_MASK 0xff00
++#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
++#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
++#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
++#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
++#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
++#define PM_FUSES_6__VddCVid_7_MASK 0xff
++#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
++#define PM_FUSES_6__VddCVid_6_MASK 0xff00
++#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
++#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
++#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
++#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
++#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
++#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
++#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
++#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
++#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
++#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
++#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
++#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
++#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
++#define PM_FUSES_8__TDC_MAWt_MASK 0xff
++#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
++#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
++#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
++#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
++#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
++#define PM_FUSES_9__Reserved_MASK 0xff
++#define PM_FUSES_9__Reserved__SHIFT 0x0
++#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
++#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
++#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
++#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
++#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
++#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
++#define PM_FUSES_10__BapmVddCVidHiSidd2_3_MASK 0xff
++#define PM_FUSES_10__BapmVddCVidHiSidd2_3__SHIFT 0x0
++#define PM_FUSES_10__BapmVddCVidHiSidd2_2_MASK 0xff00
++#define PM_FUSES_10__BapmVddCVidHiSidd2_2__SHIFT 0x8
++#define PM_FUSES_10__BapmVddCVidHiSidd2_1_MASK 0xff0000
++#define PM_FUSES_10__BapmVddCVidHiSidd2_1__SHIFT 0x10
++#define PM_FUSES_10__BapmVddCVidHiSidd2_0_MASK 0xff000000
++#define PM_FUSES_10__BapmVddCVidHiSidd2_0__SHIFT 0x18
++#define PM_FUSES_11__BapmVddCVidHiSidd2_7_MASK 0xff
++#define PM_FUSES_11__BapmVddCVidHiSidd2_7__SHIFT 0x0
++#define PM_FUSES_11__BapmVddCVidHiSidd2_6_MASK 0xff00
++#define PM_FUSES_11__BapmVddCVidHiSidd2_6__SHIFT 0x8
++#define PM_FUSES_11__BapmVddCVidHiSidd2_5_MASK 0xff0000
++#define PM_FUSES_11__BapmVddCVidHiSidd2_5__SHIFT 0x10
++#define PM_FUSES_11__BapmVddCVidHiSidd2_4_MASK 0xff000000
++#define PM_FUSES_11__BapmVddCVidHiSidd2_4__SHIFT 0x18
++#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
++#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
++#define PM_FUSES_12__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
++#define PM_FUSES_12__FuzzyFan_ErrorSetDelta__SHIFT 0x10
++#define PM_FUSES_13__Reserved6_MASK 0xffff
++#define PM_FUSES_13__Reserved6__SHIFT 0x0
++#define PM_FUSES_13__FuzzyFan_PwmSetDelta_MASK 0xffff0000
++#define PM_FUSES_13__FuzzyFan_PwmSetDelta__SHIFT 0x10
++#define PM_FUSES_14__GnbLPML_3_MASK 0xff
++#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0
++#define PM_FUSES_14__GnbLPML_2_MASK 0xff00
++#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8
++#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000
++#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10
++#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000
++#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18
++#define PM_FUSES_15__GnbLPML_7_MASK 0xff
++#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0
++#define PM_FUSES_15__GnbLPML_6_MASK 0xff00
++#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8
++#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000
++#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10
++#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000
++#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18
++#define PM_FUSES_16__GnbLPML_11_MASK 0xff
++#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0
++#define PM_FUSES_16__GnbLPML_10_MASK 0xff00
++#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8
++#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000
++#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10
++#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000
++#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18
++#define PM_FUSES_17__GnbLPML_15_MASK 0xff
++#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0
++#define PM_FUSES_17__GnbLPML_14_MASK 0xff00
++#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8
++#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000
++#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10
++#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000
++#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18
++#define PM_FUSES_18__Reserved1_1_MASK 0xff
++#define PM_FUSES_18__Reserved1_1__SHIFT 0x0
++#define PM_FUSES_18__Reserved1_0_MASK 0xff00
++#define PM_FUSES_18__Reserved1_0__SHIFT 0x8
++#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000
++#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10
++#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000
++#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18
++#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff
++#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
++#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
++#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
++#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
++#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
++#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
++#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
++#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
++#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
++#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
++#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
++#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
++#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
++#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
++#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
++#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
++#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
++#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
++#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
++#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
++#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
++#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
++#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
++#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
++#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
++#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
++#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
++#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
++#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
++#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
++#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
++#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
++#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
++#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
++#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
++#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL1__M_MASK 0xff0000
++#define CG_FDO_CTRL1__M__SHIFT 0x10
++#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
++#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
++#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
++#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
++#define CG_FDO_CTRL2__TMIN_MASK 0xff
++#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
++#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
++#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
++#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
++#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
++#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
++#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
++#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
++#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
++#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
++#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
++#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
++#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
++#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
++#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
++#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
++#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
++#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
++#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
++#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
++#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
++#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
++#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
++#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
++#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
++#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
++#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
++#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
++#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
++#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
++#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
++#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
++#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
++#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
++#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
++#define THM_TMON0_INT_DATA__VALID_MASK 0x800
++#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_INT_DATA__Z_MASK 0x7ff
++#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
++#define THM_TMON1_INT_DATA__VALID_MASK 0x800
++#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
++#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
++#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
++#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f
++#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0
++#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
++#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
++#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
++#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
++#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
++#define GENERAL_PWRMGT__SPARE11_MASK 0x800
++#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
++#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
++#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
++#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
++#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
++#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
++#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
++#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
++#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
++#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
++#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
++#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
++#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
++#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
++#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
++#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
++#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
++#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
++#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
++#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
++#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
++#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
++#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
++#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
++#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
++#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
++#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
++#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
++#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
++#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
++#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
++#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
++#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
++#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
++#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
++#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
++#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
++#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
++#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
++#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
++#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
++#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
++#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
++#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
++#define SCLK_MIN_DIV__FRACV_MASK 0xfff
++#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
++#define SCLK_MIN_DIV__INTV_MASK 0x7f000
++#define SCLK_MIN_DIV__INTV__SHIFT 0xc
++#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
++#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
++#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
++#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
++#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
++#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
++#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
++#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
++#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
++#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
++#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
++#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
++#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
++#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
++#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
++#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
++#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
++#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
++#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
++#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
++#define ROM_STATUS__ROM_BUSY_MASK 0x1
++#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
++#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
++#define ROM_DATA__ROM_DATA_MASK 0xffffffff
++#define ROM_DATA__ROM_DATA__SHIFT 0x0
++#define ROM_START__ROM_START_MASK 0xffffff
++#define ROM_START__ROM_START__SHIFT 0x0
++#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
++#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
++#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
++#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
++#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
++#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
++#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
++
++#endif /* SMU_7_1_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0021-yocto-amd-drm-amdgpu-add-SMU-7-1-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0021-yocto-amd-drm-amdgpu-add-SMU-7-1-1-register-headers.patch
new file mode 100644
index 00000000..24136992
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0021-yocto-amd-drm-amdgpu-add-SMU-7-1-1-register-headers.patch
@@ -0,0 +1,7224 @@
+From 229ebf064b81f39d732e502c4ad9f954d1a4a5f4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:30:46 -0400
+Subject: drm/amdgpu: add SMU 7.1.1 register headers
+
+These are register headers for the SMU (System Management Unit)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
+new file mode 100644
+index 0000000..3014d4a5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
+@@ -0,0 +1,1123 @@
++/*
++ * SMU_7_1_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_1_D_H
++#define SMU_7_1_1_D_H
++
++#define mmGCK_SMC_IND_INDEX                                                     0x80
++#define mmGCK0_GCK_SMC_IND_INDEX                                                0x80
++#define mmGCK1_GCK_SMC_IND_INDEX                                                0x82
++#define mmGCK2_GCK_SMC_IND_INDEX                                                0x84
++#define mmGCK3_GCK_SMC_IND_INDEX                                                0x86
++#define mmGCK_SMC_IND_DATA                                                      0x81
++#define mmGCK0_GCK_SMC_IND_DATA                                                 0x81
++#define mmGCK1_GCK_SMC_IND_DATA                                                 0x83
++#define mmGCK2_GCK_SMC_IND_DATA                                                 0x85
++#define mmGCK3_GCK_SMC_IND_DATA                                                 0x87
++#define ixCG_DCLK_CNTL                                                          0xc050009c
++#define ixCG_DCLK_STATUS                                                        0xc05000a0
++#define ixCG_VCLK_CNTL                                                          0xc05000a4
++#define ixCG_VCLK_STATUS                                                        0xc05000a8
++#define ixCG_ECLK_CNTL                                                          0xc05000ac
++#define ixCG_ECLK_STATUS                                                        0xc05000b0
++#define ixCG_ACLK_CNTL                                                          0xc05000dc
++#define ixGCK_DFS_BYPASS_CNTL                                                   0xc0500118
++#define ixCG_SPLL_FUNC_CNTL                                                     0xc0500140
++#define ixCG_SPLL_FUNC_CNTL_2                                                   0xc0500144
++#define ixCG_SPLL_FUNC_CNTL_3                                                   0xc0500148
++#define ixCG_SPLL_FUNC_CNTL_4                                                   0xc050014c
++#define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
++#define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
++#define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixSPLL_CNTL_MODE                                                        0xc0500160
++#define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
++#define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
++#define ixMPLL_BYPASSCLK_SEL                                                    0xc050019c
++#define ixCG_CLKPIN_CNTL                                                        0xc05001a0
++#define ixCG_CLKPIN_CNTL_2                                                      0xc05001a4
++#define ixCG_CLKPIN_CNTL_DC                                                     0xc0500204
++#define ixTHM_CLK_CNTL                                                          0xc05001a8
++#define ixMISC_CLK_CTRL                                                         0xc05001ac
++#define ixGCK_PLL_TEST_CNTL                                                     0xc05001c0
++#define ixGCK_PLL_TEST_CNTL_2                                                   0xc05001c4
++#define ixGCK_ADFS_CLK_BYPASS_CNTL1                                             0xc05001c8
++#define mmSMC_IND_INDEX                                                         0x80
++#define mmSMC0_SMC_IND_INDEX                                                    0x80
++#define mmSMC1_SMC_IND_INDEX                                                    0x82
++#define mmSMC2_SMC_IND_INDEX                                                    0x84
++#define mmSMC3_SMC_IND_INDEX                                                    0x86
++#define mmSMC_IND_DATA                                                          0x81
++#define mmSMC0_SMC_IND_DATA                                                     0x81
++#define mmSMC1_SMC_IND_DATA                                                     0x83
++#define mmSMC2_SMC_IND_DATA                                                     0x85
++#define mmSMC3_SMC_IND_DATA                                                     0x87
++#define mmSMC_IND_INDEX_0                                                       0x80
++#define mmSMC_IND_DATA_0                                                        0x81
++#define mmSMC_IND_INDEX_1                                                       0x82
++#define mmSMC_IND_DATA_1                                                        0x83
++#define mmSMC_IND_INDEX_2                                                       0x84
++#define mmSMC_IND_DATA_2                                                        0x85
++#define mmSMC_IND_INDEX_3                                                       0x86
++#define mmSMC_IND_DATA_3                                                        0x87
++#define mmSMC_IND_INDEX_4                                                       0x88
++#define mmSMC_IND_DATA_4                                                        0x89
++#define mmSMC_IND_INDEX_5                                                       0x8a
++#define mmSMC_IND_DATA_5                                                        0x8b
++#define mmSMC_IND_INDEX_6                                                       0x8c
++#define mmSMC_IND_DATA_6                                                        0x8d
++#define mmSMC_IND_INDEX_7                                                       0x8e
++#define mmSMC_IND_DATA_7                                                        0x8f
++#define mmSMC_IND_ACCESS_CNTL                                                   0x92
++#define mmSMC_MESSAGE_0                                                         0x94
++#define mmSMC_RESP_0                                                            0x95
++#define mmSMC_MESSAGE_1                                                         0x96
++#define mmSMC_RESP_1                                                            0x97
++#define mmSMC_MESSAGE_2                                                         0x98
++#define mmSMC_RESP_2                                                            0x99
++#define mmSMC_MESSAGE_3                                                         0x9a
++#define mmSMC_RESP_3                                                            0x9b
++#define mmSMC_MESSAGE_4                                                         0x9c
++#define mmSMC_RESP_4                                                            0x9d
++#define mmSMC_MESSAGE_5                                                         0x9e
++#define mmSMC_RESP_5                                                            0x9f
++#define mmSMC_MESSAGE_6                                                         0xa0
++#define mmSMC_RESP_6                                                            0xa1
++#define mmSMC_MESSAGE_7                                                         0xa2
++#define mmSMC_RESP_7                                                            0xa3
++#define mmSMC_MSG_ARG_0                                                         0xa4
++#define mmSMC_MSG_ARG_1                                                         0xa5
++#define mmSMC_MSG_ARG_2                                                         0xa6
++#define mmSMC_MSG_ARG_3                                                         0xa7
++#define mmSMC_MSG_ARG_4                                                         0xa8
++#define mmSMC_MSG_ARG_5                                                         0xa9
++#define mmSMC_MSG_ARG_6                                                         0xaa
++#define mmSMC_MSG_ARG_7                                                         0xab
++#define mmSMC_MESSAGE_8                                                         0xb5
++#define mmSMC_RESP_8                                                            0xb6
++#define mmSMC_MESSAGE_9                                                         0xb7
++#define mmSMC_RESP_9                                                            0xb8
++#define mmSMC_MESSAGE_10                                                        0xb9
++#define mmSMC_RESP_10                                                           0xba
++#define mmSMC_MESSAGE_11                                                        0xbb
++#define mmSMC_RESP_11                                                           0xbc
++#define mmSMC_MSG_ARG_8                                                         0xbd
++#define mmSMC_MSG_ARG_9                                                         0xbe
++#define mmSMC_MSG_ARG_10                                                        0xbf
++#define mmSMC_MSG_ARG_11                                                        0x93
++#define ixSMC_SYSCON_RESET_CNTL                                                 0x80000000
++#define ixSMC_SYSCON_CLOCK_CNTL_0                                               0x80000004
++#define ixSMC_SYSCON_CLOCK_CNTL_1                                               0x80000008
++#define ixSMC_SYSCON_CLOCK_CNTL_2                                               0x8000000c
++#define ixSMC_SYSCON_MISC_CNTL                                                  0x80000010
++#define ixSMC_SYSCON_MSG_ARG_0                                                  0x80000068
++#define ixSMC_PC_C                                                              0x80000370
++#define ixSMC_SCRATCH9                                                          0x80000424
++#define mmGPIOPAD_SW_INT_STAT                                                   0x180
++#define mmGPIOPAD_STRENGTH                                                      0x181
++#define mmGPIOPAD_MASK                                                          0x182
++#define mmGPIOPAD_A                                                             0x183
++#define mmGPIOPAD_EN                                                            0x184
++#define mmGPIOPAD_Y                                                             0x185
++#define mmGPIOPAD_PINSTRAPS                                                     0x186
++#define mmGPIOPAD_INT_STAT_EN                                                   0x187
++#define mmGPIOPAD_INT_STAT                                                      0x188
++#define mmGPIOPAD_INT_STAT_AK                                                   0x189
++#define mmGPIOPAD_INT_EN                                                        0x18a
++#define mmGPIOPAD_INT_TYPE                                                      0x18b
++#define mmGPIOPAD_INT_POLARITY                                                  0x18c
++#define mmGPIOPAD_EXTERN_TRIG_CNTL                                              0x18d
++#define mmGPIOPAD_RCVR_SEL                                                      0x191
++#define mmGPIOPAD_PU_EN                                                         0x192
++#define mmGPIOPAD_PD_EN                                                         0x193
++#define mmCG_FPS_CNT                                                            0x1b6
++#define mmSMU_IND_INDEX_0                                                       0x1a6
++#define mmSMU_IND_DATA_0                                                        0x1a7
++#define mmSMU_IND_INDEX_1                                                       0x1a8
++#define mmSMU_IND_DATA_1                                                        0x1a9
++#define mmSMU_IND_INDEX_2                                                       0x1aa
++#define mmSMU_IND_DATA_2                                                        0x1ab
++#define mmSMU_IND_INDEX_3                                                       0x1ac
++#define mmSMU_IND_DATA_3                                                        0x1ad
++#define mmSMU_IND_INDEX_4                                                       0x1ae
++#define mmSMU_IND_DATA_4                                                        0x1af
++#define mmSMU_IND_INDEX_5                                                       0x1b0
++#define mmSMU_IND_DATA_5                                                        0x1b1
++#define mmSMU_IND_INDEX_6                                                       0x1b2
++#define mmSMU_IND_DATA_6                                                        0x1b3
++#define mmSMU_IND_INDEX_7                                                       0x1b4
++#define mmSMU_IND_DATA_7                                                        0x1b5
++#define mmSMU_SMC_IND_INDEX                                                     0x80
++#define mmSMU0_SMU_SMC_IND_INDEX                                                0x80
++#define mmSMU1_SMU_SMC_IND_INDEX                                                0x82
++#define mmSMU2_SMU_SMC_IND_INDEX                                                0x84
++#define mmSMU3_SMU_SMC_IND_INDEX                                                0x86
++#define mmSMU_SMC_IND_DATA                                                      0x81
++#define mmSMU0_SMU_SMC_IND_DATA                                                 0x81
++#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83
++#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85
++#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87
++#define ixRCU_UC_EVENTS                                                         0xc0000004
++#define ixRCU_MISC_CTRL                                                         0xc0000010
++#define ixCC_RCU_FUSES                                                          0xc00c0000
++#define ixCC_SMU_MISC_FUSES                                                     0xc00c0004
++#define ixCC_SCLK_VID_FUSES                                                     0xc00c0008
++#define ixCC_GIO_IOCCFG_FUSES                                                   0xc00c000c
++#define ixCC_GIO_IOC_FUSES                                                      0xc00c0010
++#define ixCC_SMU_TST_EFUSE1_MISC                                                0xc00c001c
++#define ixCC_TST_ID_STRAPS                                                      0xc00c0020
++#define ixCC_FCTRL_FUSES                                                        0xc00c0024
++#define ixCC_HARVEST_FUSES                                                      0xc00c0028
++#define ixSMU_MAIN_PLL_OP_FREQ                                                  0xe0003020
++#define ixSMU_STATUS                                                            0xe0003088
++#define ixSMU_FIRMWARE                                                          0xe00030a4
++#define ixSMU_INPUT_DATA                                                        0xe00030b8
++#define ixSMU_EFUSE_0                                                           0xc0100000
++#define ixMCARB_DRAM_TIMING_TABLE_1                                             0x33018
++#define ixMCARB_DRAM_TIMING_TABLE_2                                             0x3301c
++#define ixMCARB_DRAM_TIMING_TABLE_3                                             0x33020
++#define ixMCARB_DRAM_TIMING_TABLE_4                                             0x33024
++#define ixMCARB_DRAM_TIMING_TABLE_5                                             0x33028
++#define ixMCARB_DRAM_TIMING_TABLE_6                                             0x3302c
++#define ixMCARB_DRAM_TIMING_TABLE_7                                             0x33030
++#define ixMCARB_DRAM_TIMING_TABLE_8                                             0x33034
++#define ixMCARB_DRAM_TIMING_TABLE_9                                             0x33038
++#define ixMCARB_DRAM_TIMING_TABLE_10                                            0x3303c
++#define ixMCARB_DRAM_TIMING_TABLE_11                                            0x33040
++#define ixMCARB_DRAM_TIMING_TABLE_12                                            0x33044
++#define ixMCARB_DRAM_TIMING_TABLE_13                                            0x33048
++#define ixMCARB_DRAM_TIMING_TABLE_14                                            0x3304c
++#define ixMCARB_DRAM_TIMING_TABLE_15                                            0x33050
++#define ixMCARB_DRAM_TIMING_TABLE_16                                            0x33054
++#define ixMCARB_DRAM_TIMING_TABLE_17                                            0x33058
++#define ixMCARB_DRAM_TIMING_TABLE_18                                            0x3305c
++#define ixMCARB_DRAM_TIMING_TABLE_19                                            0x33060
++#define ixMCARB_DRAM_TIMING_TABLE_20                                            0x33064
++#define ixMCARB_DRAM_TIMING_TABLE_21                                            0x33068
++#define ixMCARB_DRAM_TIMING_TABLE_22                                            0x3306c
++#define ixMCARB_DRAM_TIMING_TABLE_23                                            0x33070
++#define ixMCARB_DRAM_TIMING_TABLE_24                                            0x33074
++#define ixMCARB_DRAM_TIMING_TABLE_25                                            0x33078
++#define ixMCARB_DRAM_TIMING_TABLE_26                                            0x3307c
++#define ixMCARB_DRAM_TIMING_TABLE_27                                            0x33080
++#define ixMCARB_DRAM_TIMING_TABLE_28                                            0x33084
++#define ixMCARB_DRAM_TIMING_TABLE_29                                            0x33088
++#define ixMCARB_DRAM_TIMING_TABLE_30                                            0x3308c
++#define ixMCARB_DRAM_TIMING_TABLE_31                                            0x33090
++#define ixMCARB_DRAM_TIMING_TABLE_32                                            0x33094
++#define ixMCARB_DRAM_TIMING_TABLE_33                                            0x33098
++#define ixMCARB_DRAM_TIMING_TABLE_34                                            0x3309c
++#define ixMCARB_DRAM_TIMING_TABLE_35                                            0x330a0
++#define ixMCARB_DRAM_TIMING_TABLE_36                                            0x330a4
++#define ixMCARB_DRAM_TIMING_TABLE_37                                            0x330a8
++#define ixMCARB_DRAM_TIMING_TABLE_38                                            0x330ac
++#define ixMCARB_DRAM_TIMING_TABLE_39                                            0x330b0
++#define ixMCARB_DRAM_TIMING_TABLE_40                                            0x330b4
++#define ixMCARB_DRAM_TIMING_TABLE_41                                            0x330b8
++#define ixMCARB_DRAM_TIMING_TABLE_42                                            0x330bc
++#define ixMCARB_DRAM_TIMING_TABLE_43                                            0x330c0
++#define ixMCARB_DRAM_TIMING_TABLE_44                                            0x330c4
++#define ixMCARB_DRAM_TIMING_TABLE_45                                            0x330c8
++#define ixMCARB_DRAM_TIMING_TABLE_46                                            0x330cc
++#define ixMCARB_DRAM_TIMING_TABLE_47                                            0x330d0
++#define ixMCARB_DRAM_TIMING_TABLE_48                                            0x330d4
++#define ixMCARB_DRAM_TIMING_TABLE_49                                            0x330d8
++#define ixMCARB_DRAM_TIMING_TABLE_50                                            0x330dc
++#define ixMCARB_DRAM_TIMING_TABLE_51                                            0x330e0
++#define ixMCARB_DRAM_TIMING_TABLE_52                                            0x330e4
++#define ixMCARB_DRAM_TIMING_TABLE_53                                            0x330e8
++#define ixMCARB_DRAM_TIMING_TABLE_54                                            0x330ec
++#define ixMCARB_DRAM_TIMING_TABLE_55                                            0x330f0
++#define ixMCARB_DRAM_TIMING_TABLE_56                                            0x330f4
++#define ixMCARB_DRAM_TIMING_TABLE_57                                            0x330f8
++#define ixMCARB_DRAM_TIMING_TABLE_58                                            0x330fc
++#define ixMCARB_DRAM_TIMING_TABLE_59                                            0x33100
++#define ixMCARB_DRAM_TIMING_TABLE_60                                            0x33104
++#define ixMCARB_DRAM_TIMING_TABLE_61                                            0x33108
++#define ixMCARB_DRAM_TIMING_TABLE_62                                            0x3310c
++#define ixMCARB_DRAM_TIMING_TABLE_63                                            0x33110
++#define ixMCARB_DRAM_TIMING_TABLE_64                                            0x33114
++#define ixMCARB_DRAM_TIMING_TABLE_65                                            0x33118
++#define ixMCARB_DRAM_TIMING_TABLE_66                                            0x3311c
++#define ixMCARB_DRAM_TIMING_TABLE_67                                            0x33120
++#define ixMCARB_DRAM_TIMING_TABLE_68                                            0x33124
++#define ixMCARB_DRAM_TIMING_TABLE_69                                            0x33128
++#define ixMCARB_DRAM_TIMING_TABLE_70                                            0x3312c
++#define ixMCARB_DRAM_TIMING_TABLE_71                                            0x33130
++#define ixMCARB_DRAM_TIMING_TABLE_72                                            0x33134
++#define ixMCARB_DRAM_TIMING_TABLE_73                                            0x33138
++#define ixMCARB_DRAM_TIMING_TABLE_74                                            0x3313c
++#define ixMCARB_DRAM_TIMING_TABLE_75                                            0x33140
++#define ixMCARB_DRAM_TIMING_TABLE_76                                            0x33144
++#define ixMCARB_DRAM_TIMING_TABLE_77                                            0x33148
++#define ixMCARB_DRAM_TIMING_TABLE_78                                            0x3314c
++#define ixMCARB_DRAM_TIMING_TABLE_79                                            0x33150
++#define ixMCARB_DRAM_TIMING_TABLE_80                                            0x33154
++#define ixMCARB_DRAM_TIMING_TABLE_81                                            0x33158
++#define ixMCARB_DRAM_TIMING_TABLE_82                                            0x3315c
++#define ixMCARB_DRAM_TIMING_TABLE_83                                            0x33160
++#define ixMCARB_DRAM_TIMING_TABLE_84                                            0x33164
++#define ixMCARB_DRAM_TIMING_TABLE_85                                            0x33168
++#define ixMCARB_DRAM_TIMING_TABLE_86                                            0x3316c
++#define ixMCARB_DRAM_TIMING_TABLE_87                                            0x33170
++#define ixMCARB_DRAM_TIMING_TABLE_88                                            0x33174
++#define ixMCARB_DRAM_TIMING_TABLE_89                                            0x33178
++#define ixMCARB_DRAM_TIMING_TABLE_90                                            0x3317c
++#define ixMCARB_DRAM_TIMING_TABLE_91                                            0x33180
++#define ixMCARB_DRAM_TIMING_TABLE_92                                            0x33184
++#define ixMCARB_DRAM_TIMING_TABLE_93                                            0x33188
++#define ixMCARB_DRAM_TIMING_TABLE_94                                            0x3318c
++#define ixMCARB_DRAM_TIMING_TABLE_95                                            0x33190
++#define ixMCARB_DRAM_TIMING_TABLE_96                                            0x33194
++#define ixMC_REGISTERS_TABLE_1                                                  0x33198
++#define ixMC_REGISTERS_TABLE_2                                                  0x3319c
++#define ixMC_REGISTERS_TABLE_3                                                  0x331a0
++#define ixMC_REGISTERS_TABLE_4                                                  0x331a4
++#define ixMC_REGISTERS_TABLE_5                                                  0x331a8
++#define ixMC_REGISTERS_TABLE_6                                                  0x331ac
++#define ixMC_REGISTERS_TABLE_7                                                  0x331b0
++#define ixMC_REGISTERS_TABLE_8                                                  0x331b4
++#define ixMC_REGISTERS_TABLE_9                                                  0x331b8
++#define ixMC_REGISTERS_TABLE_10                                                 0x331bc
++#define ixMC_REGISTERS_TABLE_11                                                 0x331c0
++#define ixMC_REGISTERS_TABLE_12                                                 0x331c4
++#define ixMC_REGISTERS_TABLE_13                                                 0x331c8
++#define ixMC_REGISTERS_TABLE_14                                                 0x331cc
++#define ixMC_REGISTERS_TABLE_15                                                 0x331d0
++#define ixMC_REGISTERS_TABLE_16                                                 0x331d4
++#define ixMC_REGISTERS_TABLE_17                                                 0x331d8
++#define ixMC_REGISTERS_TABLE_18                                                 0x331dc
++#define ixMC_REGISTERS_TABLE_19                                                 0x331e0
++#define ixMC_REGISTERS_TABLE_20                                                 0x331e4
++#define ixMC_REGISTERS_TABLE_21                                                 0x331e8
++#define ixMC_REGISTERS_TABLE_22                                                 0x331ec
++#define ixMC_REGISTERS_TABLE_23                                                 0x331f0
++#define ixMC_REGISTERS_TABLE_24                                                 0x331f4
++#define ixMC_REGISTERS_TABLE_25                                                 0x331f8
++#define ixMC_REGISTERS_TABLE_26                                                 0x331fc
++#define ixMC_REGISTERS_TABLE_27                                                 0x33200
++#define ixMC_REGISTERS_TABLE_28                                                 0x33204
++#define ixMC_REGISTERS_TABLE_29                                                 0x33208
++#define ixMC_REGISTERS_TABLE_30                                                 0x3320c
++#define ixMC_REGISTERS_TABLE_31                                                 0x33210
++#define ixMC_REGISTERS_TABLE_32                                                 0x33214
++#define ixMC_REGISTERS_TABLE_33                                                 0x33218
++#define ixMC_REGISTERS_TABLE_34                                                 0x3321c
++#define ixMC_REGISTERS_TABLE_35                                                 0x33220
++#define ixMC_REGISTERS_TABLE_36                                                 0x33224
++#define ixMC_REGISTERS_TABLE_37                                                 0x33228
++#define ixMC_REGISTERS_TABLE_38                                                 0x3322c
++#define ixMC_REGISTERS_TABLE_39                                                 0x33230
++#define ixMC_REGISTERS_TABLE_40                                                 0x33234
++#define ixMC_REGISTERS_TABLE_41                                                 0x33238
++#define ixMC_REGISTERS_TABLE_42                                                 0x3323c
++#define ixMC_REGISTERS_TABLE_43                                                 0x33240
++#define ixMC_REGISTERS_TABLE_44                                                 0x33244
++#define ixMC_REGISTERS_TABLE_45                                                 0x33248
++#define ixMC_REGISTERS_TABLE_46                                                 0x3324c
++#define ixMC_REGISTERS_TABLE_47                                                 0x33250
++#define ixMC_REGISTERS_TABLE_48                                                 0x33254
++#define ixMC_REGISTERS_TABLE_49                                                 0x33258
++#define ixMC_REGISTERS_TABLE_50                                                 0x3325c
++#define ixMC_REGISTERS_TABLE_51                                                 0x33260
++#define ixMC_REGISTERS_TABLE_52                                                 0x33264
++#define ixMC_REGISTERS_TABLE_53                                                 0x33268
++#define ixMC_REGISTERS_TABLE_54                                                 0x3326c
++#define ixMC_REGISTERS_TABLE_55                                                 0x33270
++#define ixMC_REGISTERS_TABLE_56                                                 0x33274
++#define ixMC_REGISTERS_TABLE_57                                                 0x33278
++#define ixMC_REGISTERS_TABLE_58                                                 0x3327c
++#define ixMC_REGISTERS_TABLE_59                                                 0x33280
++#define ixMC_REGISTERS_TABLE_60                                                 0x33284
++#define ixMC_REGISTERS_TABLE_61                                                 0x33288
++#define ixMC_REGISTERS_TABLE_62                                                 0x3328c
++#define ixMC_REGISTERS_TABLE_63                                                 0x33290
++#define ixMC_REGISTERS_TABLE_64                                                 0x33294
++#define ixMC_REGISTERS_TABLE_65                                                 0x33298
++#define ixMC_REGISTERS_TABLE_66                                                 0x3329c
++#define ixMC_REGISTERS_TABLE_67                                                 0x332a0
++#define ixMC_REGISTERS_TABLE_68                                                 0x332a4
++#define ixMC_REGISTERS_TABLE_69                                                 0x332a8
++#define ixMC_REGISTERS_TABLE_70                                                 0x332ac
++#define ixMC_REGISTERS_TABLE_71                                                 0x332b0
++#define ixMC_REGISTERS_TABLE_72                                                 0x332b4
++#define ixMC_REGISTERS_TABLE_73                                                 0x332b8
++#define ixMC_REGISTERS_TABLE_74                                                 0x332bc
++#define ixMC_REGISTERS_TABLE_75                                                 0x332c0
++#define ixMC_REGISTERS_TABLE_76                                                 0x332c4
++#define ixMC_REGISTERS_TABLE_77                                                 0x332c8
++#define ixMC_REGISTERS_TABLE_78                                                 0x332cc
++#define ixMC_REGISTERS_TABLE_79                                                 0x332d0
++#define ixMC_REGISTERS_TABLE_80                                                 0x332d4
++#define ixMC_REGISTERS_TABLE_81                                                 0x332d8
++#define ixDPM_TABLE_1                                                           0x332dc
++#define ixDPM_TABLE_2                                                           0x332e0
++#define ixDPM_TABLE_3                                                           0x332e4
++#define ixDPM_TABLE_4                                                           0x332e8
++#define ixDPM_TABLE_5                                                           0x332ec
++#define ixDPM_TABLE_6                                                           0x332f0
++#define ixDPM_TABLE_7                                                           0x332f4
++#define ixDPM_TABLE_8                                                           0x332f8
++#define ixDPM_TABLE_9                                                           0x332fc
++#define ixDPM_TABLE_10                                                          0x33300
++#define ixDPM_TABLE_11                                                          0x33304
++#define ixDPM_TABLE_12                                                          0x33308
++#define ixDPM_TABLE_13                                                          0x3330c
++#define ixDPM_TABLE_14                                                          0x33310
++#define ixDPM_TABLE_15                                                          0x33314
++#define ixDPM_TABLE_16                                                          0x33318
++#define ixDPM_TABLE_17                                                          0x3331c
++#define ixDPM_TABLE_18                                                          0x33320
++#define ixDPM_TABLE_19                                                          0x33324
++#define ixDPM_TABLE_20                                                          0x33328
++#define ixDPM_TABLE_21                                                          0x3332c
++#define ixDPM_TABLE_22                                                          0x33330
++#define ixDPM_TABLE_23                                                          0x33334
++#define ixDPM_TABLE_24                                                          0x33338
++#define ixDPM_TABLE_25                                                          0x3333c
++#define ixDPM_TABLE_26                                                          0x33340
++#define ixDPM_TABLE_27                                                          0x33344
++#define ixDPM_TABLE_28                                                          0x33348
++#define ixDPM_TABLE_29                                                          0x3334c
++#define ixDPM_TABLE_30                                                          0x33350
++#define ixDPM_TABLE_31                                                          0x33354
++#define ixDPM_TABLE_32                                                          0x33358
++#define ixDPM_TABLE_33                                                          0x3335c
++#define ixDPM_TABLE_34                                                          0x33360
++#define ixDPM_TABLE_35                                                          0x33364
++#define ixDPM_TABLE_36                                                          0x33368
++#define ixDPM_TABLE_37                                                          0x3336c
++#define ixDPM_TABLE_38                                                          0x33370
++#define ixDPM_TABLE_39                                                          0x33374
++#define ixDPM_TABLE_40                                                          0x33378
++#define ixDPM_TABLE_41                                                          0x3337c
++#define ixDPM_TABLE_42                                                          0x33380
++#define ixDPM_TABLE_43                                                          0x33384
++#define ixDPM_TABLE_44                                                          0x33388
++#define ixDPM_TABLE_45                                                          0x3338c
++#define ixDPM_TABLE_46                                                          0x33390
++#define ixDPM_TABLE_47                                                          0x33394
++#define ixDPM_TABLE_48                                                          0x33398
++#define ixDPM_TABLE_49                                                          0x3339c
++#define ixDPM_TABLE_50                                                          0x333a0
++#define ixDPM_TABLE_51                                                          0x333a4
++#define ixDPM_TABLE_52                                                          0x333a8
++#define ixDPM_TABLE_53                                                          0x333ac
++#define ixDPM_TABLE_54                                                          0x333b0
++#define ixDPM_TABLE_55                                                          0x333b4
++#define ixDPM_TABLE_56                                                          0x333b8
++#define ixDPM_TABLE_57                                                          0x333bc
++#define ixDPM_TABLE_58                                                          0x333c0
++#define ixDPM_TABLE_59                                                          0x333c4
++#define ixDPM_TABLE_60                                                          0x333c8
++#define ixDPM_TABLE_61                                                          0x333cc
++#define ixDPM_TABLE_62                                                          0x333d0
++#define ixDPM_TABLE_63                                                          0x333d4
++#define ixDPM_TABLE_64                                                          0x333d8
++#define ixDPM_TABLE_65                                                          0x333dc
++#define ixDPM_TABLE_66                                                          0x333e0
++#define ixDPM_TABLE_67                                                          0x333e4
++#define ixDPM_TABLE_68                                                          0x333e8
++#define ixDPM_TABLE_69                                                          0x333ec
++#define ixDPM_TABLE_70                                                          0x333f0
++#define ixDPM_TABLE_71                                                          0x333f4
++#define ixDPM_TABLE_72                                                          0x333f8
++#define ixDPM_TABLE_73                                                          0x333fc
++#define ixDPM_TABLE_74                                                          0x33400
++#define ixDPM_TABLE_75                                                          0x33404
++#define ixDPM_TABLE_76                                                          0x33408
++#define ixDPM_TABLE_77                                                          0x3340c
++#define ixDPM_TABLE_78                                                          0x33410
++#define ixDPM_TABLE_79                                                          0x33414
++#define ixDPM_TABLE_80                                                          0x33418
++#define ixDPM_TABLE_81                                                          0x3341c
++#define ixDPM_TABLE_82                                                          0x33420
++#define ixDPM_TABLE_83                                                          0x33424
++#define ixDPM_TABLE_84                                                          0x33428
++#define ixDPM_TABLE_85                                                          0x3342c
++#define ixDPM_TABLE_86                                                          0x33430
++#define ixDPM_TABLE_87                                                          0x33434
++#define ixDPM_TABLE_88                                                          0x33438
++#define ixDPM_TABLE_89                                                          0x3343c
++#define ixDPM_TABLE_90                                                          0x33440
++#define ixDPM_TABLE_91                                                          0x33444
++#define ixDPM_TABLE_92                                                          0x33448
++#define ixDPM_TABLE_93                                                          0x3344c
++#define ixDPM_TABLE_94                                                          0x33450
++#define ixDPM_TABLE_95                                                          0x33454
++#define ixDPM_TABLE_96                                                          0x33458
++#define ixDPM_TABLE_97                                                          0x3345c
++#define ixDPM_TABLE_98                                                          0x33460
++#define ixDPM_TABLE_99                                                          0x33464
++#define ixDPM_TABLE_100                                                         0x33468
++#define ixDPM_TABLE_101                                                         0x3346c
++#define ixDPM_TABLE_102                                                         0x33470
++#define ixDPM_TABLE_103                                                         0x33474
++#define ixDPM_TABLE_104                                                         0x33478
++#define ixDPM_TABLE_105                                                         0x3347c
++#define ixDPM_TABLE_106                                                         0x33480
++#define ixDPM_TABLE_107                                                         0x33484
++#define ixDPM_TABLE_108                                                         0x33488
++#define ixDPM_TABLE_109                                                         0x3348c
++#define ixDPM_TABLE_110                                                         0x33490
++#define ixDPM_TABLE_111                                                         0x33494
++#define ixDPM_TABLE_112                                                         0x33498
++#define ixDPM_TABLE_113                                                         0x3349c
++#define ixDPM_TABLE_114                                                         0x334a0
++#define ixDPM_TABLE_115                                                         0x334a4
++#define ixDPM_TABLE_116                                                         0x334a8
++#define ixDPM_TABLE_117                                                         0x334ac
++#define ixDPM_TABLE_118                                                         0x334b0
++#define ixDPM_TABLE_119                                                         0x334b4
++#define ixDPM_TABLE_120                                                         0x334b8
++#define ixDPM_TABLE_121                                                         0x334bc
++#define ixDPM_TABLE_122                                                         0x334c0
++#define ixDPM_TABLE_123                                                         0x334c4
++#define ixDPM_TABLE_124                                                         0x334c8
++#define ixDPM_TABLE_125                                                         0x334cc
++#define ixDPM_TABLE_126                                                         0x334d0
++#define ixDPM_TABLE_127                                                         0x334d4
++#define ixDPM_TABLE_128                                                         0x334d8
++#define ixDPM_TABLE_129                                                         0x334dc
++#define ixDPM_TABLE_130                                                         0x334e0
++#define ixDPM_TABLE_131                                                         0x334e4
++#define ixDPM_TABLE_132                                                         0x334e8
++#define ixDPM_TABLE_133                                                         0x334ec
++#define ixDPM_TABLE_134                                                         0x334f0
++#define ixDPM_TABLE_135                                                         0x334f4
++#define ixDPM_TABLE_136                                                         0x334f8
++#define ixDPM_TABLE_137                                                         0x334fc
++#define ixDPM_TABLE_138                                                         0x33500
++#define ixDPM_TABLE_139                                                         0x33504
++#define ixDPM_TABLE_140                                                         0x33508
++#define ixDPM_TABLE_141                                                         0x3350c
++#define ixDPM_TABLE_142                                                         0x33510
++#define ixDPM_TABLE_143                                                         0x33514
++#define ixDPM_TABLE_144                                                         0x33518
++#define ixDPM_TABLE_145                                                         0x3351c
++#define ixDPM_TABLE_146                                                         0x33520
++#define ixDPM_TABLE_147                                                         0x33524
++#define ixDPM_TABLE_148                                                         0x33528
++#define ixDPM_TABLE_149                                                         0x3352c
++#define ixDPM_TABLE_150                                                         0x33530
++#define ixDPM_TABLE_151                                                         0x33534
++#define ixDPM_TABLE_152                                                         0x33538
++#define ixDPM_TABLE_153                                                         0x3353c
++#define ixDPM_TABLE_154                                                         0x33540
++#define ixDPM_TABLE_155                                                         0x33544
++#define ixDPM_TABLE_156                                                         0x33548
++#define ixDPM_TABLE_157                                                         0x3354c
++#define ixDPM_TABLE_158                                                         0x33550
++#define ixDPM_TABLE_159                                                         0x33554
++#define ixDPM_TABLE_160                                                         0x33558
++#define ixDPM_TABLE_161                                                         0x3355c
++#define ixDPM_TABLE_162                                                         0x33560
++#define ixDPM_TABLE_163                                                         0x33564
++#define ixDPM_TABLE_164                                                         0x33568
++#define ixDPM_TABLE_165                                                         0x3356c
++#define ixDPM_TABLE_166                                                         0x33570
++#define ixDPM_TABLE_167                                                         0x33574
++#define ixDPM_TABLE_168                                                         0x33578
++#define ixDPM_TABLE_169                                                         0x3357c
++#define ixDPM_TABLE_170                                                         0x33580
++#define ixDPM_TABLE_171                                                         0x33584
++#define ixDPM_TABLE_172                                                         0x33588
++#define ixDPM_TABLE_173                                                         0x3358c
++#define ixDPM_TABLE_174                                                         0x33590
++#define ixDPM_TABLE_175                                                         0x33594
++#define ixDPM_TABLE_176                                                         0x33598
++#define ixDPM_TABLE_177                                                         0x3359c
++#define ixDPM_TABLE_178                                                         0x335a0
++#define ixDPM_TABLE_179                                                         0x335a4
++#define ixDPM_TABLE_180                                                         0x335a8
++#define ixDPM_TABLE_181                                                         0x335ac
++#define ixDPM_TABLE_182                                                         0x335b0
++#define ixDPM_TABLE_183                                                         0x335b4
++#define ixDPM_TABLE_184                                                         0x335b8
++#define ixDPM_TABLE_185                                                         0x335bc
++#define ixDPM_TABLE_186                                                         0x335c0
++#define ixDPM_TABLE_187                                                         0x335c4
++#define ixDPM_TABLE_188                                                         0x335c8
++#define ixDPM_TABLE_189                                                         0x335cc
++#define ixDPM_TABLE_190                                                         0x335d0
++#define ixDPM_TABLE_191                                                         0x335d4
++#define ixDPM_TABLE_192                                                         0x335d8
++#define ixDPM_TABLE_193                                                         0x335dc
++#define ixDPM_TABLE_194                                                         0x335e0
++#define ixDPM_TABLE_195                                                         0x335e4
++#define ixDPM_TABLE_196                                                         0x335e8
++#define ixDPM_TABLE_197                                                         0x335ec
++#define ixDPM_TABLE_198                                                         0x335f0
++#define ixDPM_TABLE_199                                                         0x335f4
++#define ixDPM_TABLE_200                                                         0x335f8
++#define ixDPM_TABLE_201                                                         0x335fc
++#define ixDPM_TABLE_202                                                         0x33600
++#define ixDPM_TABLE_203                                                         0x33604
++#define ixDPM_TABLE_204                                                         0x33608
++#define ixDPM_TABLE_205                                                         0x3360c
++#define ixDPM_TABLE_206                                                         0x33610
++#define ixDPM_TABLE_207                                                         0x33614
++#define ixDPM_TABLE_208                                                         0x33618
++#define ixDPM_TABLE_209                                                         0x3361c
++#define ixDPM_TABLE_210                                                         0x33620
++#define ixDPM_TABLE_211                                                         0x33624
++#define ixDPM_TABLE_212                                                         0x33628
++#define ixDPM_TABLE_213                                                         0x3362c
++#define ixDPM_TABLE_214                                                         0x33630
++#define ixDPM_TABLE_215                                                         0x33634
++#define ixDPM_TABLE_216                                                         0x33638
++#define ixDPM_TABLE_217                                                         0x3363c
++#define ixDPM_TABLE_218                                                         0x33640
++#define ixDPM_TABLE_219                                                         0x33644
++#define ixDPM_TABLE_220                                                         0x33648
++#define ixDPM_TABLE_221                                                         0x3364c
++#define ixDPM_TABLE_222                                                         0x33650
++#define ixDPM_TABLE_223                                                         0x33654
++#define ixDPM_TABLE_224                                                         0x33658
++#define ixDPM_TABLE_225                                                         0x3365c
++#define ixDPM_TABLE_226                                                         0x33660
++#define ixDPM_TABLE_227                                                         0x33664
++#define ixDPM_TABLE_228                                                         0x33668
++#define ixDPM_TABLE_229                                                         0x3366c
++#define ixDPM_TABLE_230                                                         0x33670
++#define ixDPM_TABLE_231                                                         0x33674
++#define ixDPM_TABLE_232                                                         0x33678
++#define ixDPM_TABLE_233                                                         0x3367c
++#define ixDPM_TABLE_234                                                         0x33680
++#define ixDPM_TABLE_235                                                         0x33684
++#define ixDPM_TABLE_236                                                         0x33688
++#define ixDPM_TABLE_237                                                         0x3368c
++#define ixDPM_TABLE_238                                                         0x33690
++#define ixDPM_TABLE_239                                                         0x33694
++#define ixDPM_TABLE_240                                                         0x33698
++#define ixDPM_TABLE_241                                                         0x3369c
++#define ixDPM_TABLE_242                                                         0x336a0
++#define ixDPM_TABLE_243                                                         0x336a4
++#define ixDPM_TABLE_244                                                         0x336a8
++#define ixDPM_TABLE_245                                                         0x336ac
++#define ixDPM_TABLE_246                                                         0x336b0
++#define ixDPM_TABLE_247                                                         0x336b4
++#define ixDPM_TABLE_248                                                         0x336b8
++#define ixDPM_TABLE_249                                                         0x336bc
++#define ixDPM_TABLE_250                                                         0x336c0
++#define ixDPM_TABLE_251                                                         0x336c4
++#define ixDPM_TABLE_252                                                         0x336c8
++#define ixDPM_TABLE_253                                                         0x336cc
++#define ixDPM_TABLE_254                                                         0x336d0
++#define ixDPM_TABLE_255                                                         0x336d4
++#define ixDPM_TABLE_256                                                         0x336d8
++#define ixDPM_TABLE_257                                                         0x336dc
++#define ixDPM_TABLE_258                                                         0x336e0
++#define ixDPM_TABLE_259                                                         0x336e4
++#define ixDPM_TABLE_260                                                         0x336e8
++#define ixDPM_TABLE_261                                                         0x336ec
++#define ixDPM_TABLE_262                                                         0x336f0
++#define ixDPM_TABLE_263                                                         0x336f4
++#define ixDPM_TABLE_264                                                         0x336f8
++#define ixDPM_TABLE_265                                                         0x336fc
++#define ixDPM_TABLE_266                                                         0x33700
++#define ixDPM_TABLE_267                                                         0x33704
++#define ixDPM_TABLE_268                                                         0x33708
++#define ixDPM_TABLE_269                                                         0x3370c
++#define ixDPM_TABLE_270                                                         0x33710
++#define ixDPM_TABLE_271                                                         0x33714
++#define ixDPM_TABLE_272                                                         0x33718
++#define ixDPM_TABLE_273                                                         0x3371c
++#define ixDPM_TABLE_274                                                         0x33720
++#define ixDPM_TABLE_275                                                         0x33724
++#define ixDPM_TABLE_276                                                         0x33728
++#define ixDPM_TABLE_277                                                         0x3372c
++#define ixDPM_TABLE_278                                                         0x33730
++#define ixDPM_TABLE_279                                                         0x33734
++#define ixDPM_TABLE_280                                                         0x33738
++#define ixDPM_TABLE_281                                                         0x3373c
++#define ixDPM_TABLE_282                                                         0x33740
++#define ixDPM_TABLE_283                                                         0x33744
++#define ixDPM_TABLE_284                                                         0x33748
++#define ixDPM_TABLE_285                                                         0x3374c
++#define ixDPM_TABLE_286                                                         0x33750
++#define ixDPM_TABLE_287                                                         0x33754
++#define ixDPM_TABLE_288                                                         0x33758
++#define ixDPM_TABLE_289                                                         0x3375c
++#define ixDPM_TABLE_290                                                         0x33760
++#define ixDPM_TABLE_291                                                         0x33764
++#define ixDPM_TABLE_292                                                         0x33768
++#define ixDPM_TABLE_293                                                         0x3376c
++#define ixDPM_TABLE_294                                                         0x33770
++#define ixDPM_TABLE_295                                                         0x33774
++#define ixDPM_TABLE_296                                                         0x33778
++#define ixDPM_TABLE_297                                                         0x3377c
++#define ixDPM_TABLE_298                                                         0x33780
++#define ixDPM_TABLE_299                                                         0x33784
++#define ixDPM_TABLE_300                                                         0x33788
++#define ixDPM_TABLE_301                                                         0x3378c
++#define ixDPM_TABLE_302                                                         0x33790
++#define ixDPM_TABLE_303                                                         0x33794
++#define ixDPM_TABLE_304                                                         0x33798
++#define ixDPM_TABLE_305                                                         0x3379c
++#define ixDPM_TABLE_306                                                         0x337a0
++#define ixDPM_TABLE_307                                                         0x337a4
++#define ixDPM_TABLE_308                                                         0x337a8
++#define ixDPM_TABLE_309                                                         0x337ac
++#define ixDPM_TABLE_310                                                         0x337b0
++#define ixDPM_TABLE_311                                                         0x337b4
++#define ixDPM_TABLE_312                                                         0x337b8
++#define ixDPM_TABLE_313                                                         0x337bc
++#define ixDPM_TABLE_314                                                         0x337c0
++#define ixDPM_TABLE_315                                                         0x337c4
++#define ixDPM_TABLE_316                                                         0x337c8
++#define ixDPM_TABLE_317                                                         0x337cc
++#define ixDPM_TABLE_318                                                         0x337d0
++#define ixDPM_TABLE_319                                                         0x337d4
++#define ixDPM_TABLE_320                                                         0x337d8
++#define ixDPM_TABLE_321                                                         0x337dc
++#define ixDPM_TABLE_322                                                         0x337e0
++#define ixDPM_TABLE_323                                                         0x337e4
++#define ixDPM_TABLE_324                                                         0x337e8
++#define ixDPM_TABLE_325                                                         0x337ec
++#define ixDPM_TABLE_326                                                         0x337f0
++#define ixDPM_TABLE_327                                                         0x337f4
++#define ixDPM_TABLE_328                                                         0x337f8
++#define ixDPM_TABLE_329                                                         0x337fc
++#define ixDPM_TABLE_330                                                         0x33800
++#define ixDPM_TABLE_331                                                         0x33804
++#define ixDPM_TABLE_332                                                         0x33808
++#define ixDPM_TABLE_333                                                         0x3380c
++#define ixDPM_TABLE_334                                                         0x33810
++#define ixDPM_TABLE_335                                                         0x33814
++#define ixDPM_TABLE_336                                                         0x33818
++#define ixDPM_TABLE_337                                                         0x3381c
++#define ixDPM_TABLE_338                                                         0x33820
++#define ixDPM_TABLE_339                                                         0x33824
++#define ixDPM_TABLE_340                                                         0x33828
++#define ixDPM_TABLE_341                                                         0x3382c
++#define ixDPM_TABLE_342                                                         0x33830
++#define ixDPM_TABLE_343                                                         0x33834
++#define ixDPM_TABLE_344                                                         0x33838
++#define ixDPM_TABLE_345                                                         0x3383c
++#define ixDPM_TABLE_346                                                         0x33840
++#define ixDPM_TABLE_347                                                         0x33844
++#define ixDPM_TABLE_348                                                         0x33848
++#define ixDPM_TABLE_349                                                         0x3384c
++#define ixDPM_TABLE_350                                                         0x33850
++#define ixDPM_TABLE_351                                                         0x33854
++#define ixDPM_TABLE_352                                                         0x33858
++#define ixDPM_TABLE_353                                                         0x3385c
++#define ixDPM_TABLE_354                                                         0x33860
++#define ixDPM_TABLE_355                                                         0x33864
++#define ixDPM_TABLE_356                                                         0x33868
++#define ixDPM_TABLE_357                                                         0x3386c
++#define ixDPM_TABLE_358                                                         0x33870
++#define ixDPM_TABLE_359                                                         0x33874
++#define ixDPM_TABLE_360                                                         0x33878
++#define ixDPM_TABLE_361                                                         0x3387c
++#define ixDPM_TABLE_362                                                         0x33880
++#define ixDPM_TABLE_363                                                         0x33884
++#define ixDPM_TABLE_364                                                         0x33888
++#define ixDPM_TABLE_365                                                         0x3388c
++#define ixDPM_TABLE_366                                                         0x33890
++#define ixDPM_TABLE_367                                                         0x33894
++#define ixDPM_TABLE_368                                                         0x33898
++#define ixDPM_TABLE_369                                                         0x3389c
++#define ixDPM_TABLE_370                                                         0x338a0
++#define ixSOFT_REGISTERS_TABLE_1                                                0x338c8
++#define ixSOFT_REGISTERS_TABLE_2                                                0x338cc
++#define ixSOFT_REGISTERS_TABLE_3                                                0x338d0
++#define ixSOFT_REGISTERS_TABLE_4                                                0x338d4
++#define ixSOFT_REGISTERS_TABLE_5                                                0x338d8
++#define ixSOFT_REGISTERS_TABLE_6                                                0x338dc
++#define ixSOFT_REGISTERS_TABLE_7                                                0x338e0
++#define ixSOFT_REGISTERS_TABLE_8                                                0x338e4
++#define ixSOFT_REGISTERS_TABLE_9                                                0x338e8
++#define ixSOFT_REGISTERS_TABLE_10                                               0x338ec
++#define ixSOFT_REGISTERS_TABLE_11                                               0x338f0
++#define ixSOFT_REGISTERS_TABLE_12                                               0x338f4
++#define ixSOFT_REGISTERS_TABLE_13                                               0x338f8
++#define ixSOFT_REGISTERS_TABLE_14                                               0x338fc
++#define ixSOFT_REGISTERS_TABLE_15                                               0x33900
++#define ixSOFT_REGISTERS_TABLE_16                                               0x33904
++#define ixSOFT_REGISTERS_TABLE_17                                               0x33908
++#define ixSOFT_REGISTERS_TABLE_18                                               0x3390c
++#define ixSOFT_REGISTERS_TABLE_19                                               0x33910
++#define ixSOFT_REGISTERS_TABLE_20                                               0x33914
++#define ixSOFT_REGISTERS_TABLE_21                                               0x33918
++#define ixSOFT_REGISTERS_TABLE_22                                               0x3391c
++#define ixSOFT_REGISTERS_TABLE_23                                               0x33920
++#define ixSOFT_REGISTERS_TABLE_24                                               0x33924
++#define ixSOFT_REGISTERS_TABLE_25                                               0x33928
++#define ixSOFT_REGISTERS_TABLE_26                                               0x3392c
++#define ixSOFT_REGISTERS_TABLE_27                                               0x33930
++#define ixSOFT_REGISTERS_TABLE_28                                               0x33934
++#define ixSOFT_REGISTERS_TABLE_29                                               0x33938
++#define ixFIRMWARE_FLAGS                                                        0x33000
++#define ixTDC_STATUS                                                            0x33004
++#define ixTDC_MV_AVERAGE                                                        0x33008
++#define ixTDC_VRM_LIMIT                                                         0x3300c
++#define ixFEATURE_STATUS                                                        0x33010
++#define ixENTITY_TEMPERATURES_1                                                 0x33014
++#define ixPM_FUSES_1                                                            0x3394c
++#define ixPM_FUSES_2                                                            0x33950
++#define ixPM_FUSES_3                                                            0x33954
++#define ixPM_FUSES_4                                                            0x33958
++#define ixPM_FUSES_5                                                            0x3395c
++#define ixPM_FUSES_6                                                            0x33960
++#define ixPM_FUSES_7                                                            0x33964
++#define ixPM_FUSES_8                                                            0x33968
++#define ixPM_FUSES_9                                                            0x3396c
++#define ixPM_FUSES_10                                                           0x33970
++#define ixPM_FUSES_11                                                           0x33974
++#define ixPM_FUSES_12                                                           0x33978
++#define ixPM_FUSES_13                                                           0x3397c
++#define ixPM_FUSES_14                                                           0x33980
++#define ixPM_FUSES_15                                                           0x33984
++#define ixPM_FUSES_16                                                           0x33988
++#define ixPM_FUSES_17                                                           0x3398c
++#define ixPM_FUSES_18                                                           0x33990
++#define ixPM_FUSES_19                                                           0x33994
++#define ixPM_FUSES_20                                                           0x33998
++#define ixPM_FUSES_21                                                           0x3399c
++#define ixSMU_PM_STATUS_0                                                       0x33e00
++#define ixSMU_PM_STATUS_1                                                       0x33e04
++#define ixSMU_PM_STATUS_2                                                       0x33e08
++#define ixSMU_PM_STATUS_3                                                       0x33e0c
++#define ixSMU_PM_STATUS_4                                                       0x33e10
++#define ixSMU_PM_STATUS_5                                                       0x33e14
++#define ixSMU_PM_STATUS_6                                                       0x33e18
++#define ixSMU_PM_STATUS_7                                                       0x33e1c
++#define ixSMU_PM_STATUS_8                                                       0x33e20
++#define ixSMU_PM_STATUS_9                                                       0x33e24
++#define ixSMU_PM_STATUS_10                                                      0x33e28
++#define ixSMU_PM_STATUS_11                                                      0x33e2c
++#define ixSMU_PM_STATUS_12                                                      0x33e30
++#define ixSMU_PM_STATUS_13                                                      0x33e34
++#define ixSMU_PM_STATUS_14                                                      0x33e38
++#define ixSMU_PM_STATUS_15                                                      0x33e3c
++#define ixSMU_PM_STATUS_16                                                      0x33e40
++#define ixSMU_PM_STATUS_17                                                      0x33e44
++#define ixSMU_PM_STATUS_18                                                      0x33e48
++#define ixSMU_PM_STATUS_19                                                      0x33e4c
++#define ixSMU_PM_STATUS_20                                                      0x33e50
++#define ixSMU_PM_STATUS_21                                                      0x33e54
++#define ixSMU_PM_STATUS_22                                                      0x33e58
++#define ixSMU_PM_STATUS_23                                                      0x33e5c
++#define ixSMU_PM_STATUS_24                                                      0x33e60
++#define ixSMU_PM_STATUS_25                                                      0x33e64
++#define ixSMU_PM_STATUS_26                                                      0x33e68
++#define ixSMU_PM_STATUS_27                                                      0x33e6c
++#define ixSMU_PM_STATUS_28                                                      0x33e70
++#define ixSMU_PM_STATUS_29                                                      0x33e74
++#define ixSMU_PM_STATUS_30                                                      0x33e78
++#define ixSMU_PM_STATUS_31                                                      0x33e7c
++#define ixSMU_PM_STATUS_32                                                      0x33e80
++#define ixSMU_PM_STATUS_33                                                      0x33e84
++#define ixSMU_PM_STATUS_34                                                      0x33e88
++#define ixSMU_PM_STATUS_35                                                      0x33e8c
++#define ixSMU_PM_STATUS_36                                                      0x33e90
++#define ixSMU_PM_STATUS_37                                                      0x33e94
++#define ixSMU_PM_STATUS_38                                                      0x33e98
++#define ixSMU_PM_STATUS_39                                                      0x33e9c
++#define ixSMU_PM_STATUS_40                                                      0x33ea0
++#define ixSMU_PM_STATUS_41                                                      0x33ea4
++#define ixSMU_PM_STATUS_42                                                      0x33ea8
++#define ixSMU_PM_STATUS_43                                                      0x33eac
++#define ixSMU_PM_STATUS_44                                                      0x33eb0
++#define ixSMU_PM_STATUS_45                                                      0x33eb4
++#define ixSMU_PM_STATUS_46                                                      0x33eb8
++#define ixSMU_PM_STATUS_47                                                      0x33ebc
++#define ixSMU_PM_STATUS_48                                                      0x33ec0
++#define ixSMU_PM_STATUS_49                                                      0x33ec4
++#define ixSMU_PM_STATUS_50                                                      0x33ec8
++#define ixSMU_PM_STATUS_51                                                      0x33ecc
++#define ixSMU_PM_STATUS_52                                                      0x33ed0
++#define ixSMU_PM_STATUS_53                                                      0x33ed4
++#define ixSMU_PM_STATUS_54                                                      0x33ed8
++#define ixSMU_PM_STATUS_55                                                      0x33edc
++#define ixSMU_PM_STATUS_56                                                      0x33ee0
++#define ixSMU_PM_STATUS_57                                                      0x33ee4
++#define ixSMU_PM_STATUS_58                                                      0x33ee8
++#define ixSMU_PM_STATUS_59                                                      0x33eec
++#define ixSMU_PM_STATUS_60                                                      0x33ef0
++#define ixSMU_PM_STATUS_61                                                      0x33ef4
++#define ixSMU_PM_STATUS_62                                                      0x33ef8
++#define ixSMU_PM_STATUS_63                                                      0x33efc
++#define ixSMU_PM_STATUS_64                                                      0x33f00
++#define ixSMU_PM_STATUS_65                                                      0x33f04
++#define ixSMU_PM_STATUS_66                                                      0x33f08
++#define ixSMU_PM_STATUS_67                                                      0x33f0c
++#define ixSMU_PM_STATUS_68                                                      0x33f10
++#define ixSMU_PM_STATUS_69                                                      0x33f14
++#define ixSMU_PM_STATUS_70                                                      0x33f18
++#define ixSMU_PM_STATUS_71                                                      0x33f1c
++#define ixSMU_PM_STATUS_72                                                      0x33f20
++#define ixSMU_PM_STATUS_73                                                      0x33f24
++#define ixSMU_PM_STATUS_74                                                      0x33f28
++#define ixSMU_PM_STATUS_75                                                      0x33f2c
++#define ixSMU_PM_STATUS_76                                                      0x33f30
++#define ixSMU_PM_STATUS_77                                                      0x33f34
++#define ixSMU_PM_STATUS_78                                                      0x33f38
++#define ixSMU_PM_STATUS_79                                                      0x33f3c
++#define ixSMU_PM_STATUS_80                                                      0x33f40
++#define ixSMU_PM_STATUS_81                                                      0x33f44
++#define ixSMU_PM_STATUS_82                                                      0x33f48
++#define ixSMU_PM_STATUS_83                                                      0x33f4c
++#define ixSMU_PM_STATUS_84                                                      0x33f50
++#define ixSMU_PM_STATUS_85                                                      0x33f54
++#define ixSMU_PM_STATUS_86                                                      0x33f58
++#define ixSMU_PM_STATUS_87                                                      0x33f5c
++#define ixSMU_PM_STATUS_88                                                      0x33f60
++#define ixSMU_PM_STATUS_89                                                      0x33f64
++#define ixSMU_PM_STATUS_90                                                      0x33f68
++#define ixSMU_PM_STATUS_91                                                      0x33f6c
++#define ixSMU_PM_STATUS_92                                                      0x33f70
++#define ixSMU_PM_STATUS_93                                                      0x33f74
++#define ixSMU_PM_STATUS_94                                                      0x33f78
++#define ixSMU_PM_STATUS_95                                                      0x33f7c
++#define ixSMU_PM_STATUS_96                                                      0x33f80
++#define ixSMU_PM_STATUS_97                                                      0x33f84
++#define ixSMU_PM_STATUS_98                                                      0x33f88
++#define ixSMU_PM_STATUS_99                                                      0x33f8c
++#define ixSMU_PM_STATUS_100                                                     0x33f90
++#define ixSMU_PM_STATUS_101                                                     0x33f94
++#define ixSMU_PM_STATUS_102                                                     0x33f98
++#define ixSMU_PM_STATUS_103                                                     0x33f9c
++#define ixSMU_PM_STATUS_104                                                     0x33fa0
++#define ixSMU_PM_STATUS_105                                                     0x33fa4
++#define ixSMU_PM_STATUS_106                                                     0x33fa8
++#define ixSMU_PM_STATUS_107                                                     0x33fac
++#define ixSMU_PM_STATUS_108                                                     0x33fb0
++#define ixSMU_PM_STATUS_109                                                     0x33fb4
++#define ixSMU_PM_STATUS_110                                                     0x33fb8
++#define ixSMU_PM_STATUS_111                                                     0x33fbc
++#define ixSMU_PM_STATUS_112                                                     0x33fc0
++#define ixSMU_PM_STATUS_113                                                     0x33fc4
++#define ixSMU_PM_STATUS_114                                                     0x33fc8
++#define ixSMU_PM_STATUS_115                                                     0x33fcc
++#define ixSMU_PM_STATUS_116                                                     0x33fd0
++#define ixSMU_PM_STATUS_117                                                     0x33fd4
++#define ixSMU_PM_STATUS_118                                                     0x33fd8
++#define ixSMU_PM_STATUS_119                                                     0x33fdc
++#define ixSMU_PM_STATUS_120                                                     0x33fe0
++#define ixSMU_PM_STATUS_121                                                     0x33fe4
++#define ixSMU_PM_STATUS_122                                                     0x33fe8
++#define ixSMU_PM_STATUS_123                                                     0x33fec
++#define ixSMU_PM_STATUS_124                                                     0x33ff0
++#define ixSMU_PM_STATUS_125                                                     0x33ff4
++#define ixSMU_PM_STATUS_126                                                     0x33ff8
++#define ixSMU_PM_STATUS_127                                                     0x33ffc
++#define ixCG_THERMAL_INT_ENA                                                    0xc2100024
++#define ixCG_THERMAL_INT_CTRL                                                   0xc2100028
++#define ixCG_THERMAL_INT_STATUS                                                 0xc210002c
++#define ixCG_THERMAL_CTRL                                                       0xc0300004
++#define ixCG_THERMAL_STATUS                                                     0xc0300008
++#define ixCG_THERMAL_INT                                                        0xc030000c
++#define ixCG_MULT_THERMAL_CTRL                                                  0xc0300010
++#define ixCG_MULT_THERMAL_STATUS                                                0xc0300014
++#define ixCG_FDO_CTRL0                                                          0xc0300064
++#define ixCG_FDO_CTRL1                                                          0xc0300068
++#define ixCG_FDO_CTRL2                                                          0xc030006c
++#define ixCG_TACH_CTRL                                                          0xc0300070
++#define ixCG_TACH_STATUS                                                        0xc0300074
++#define ixCC_THM_STRAPS0                                                        0xc0300080
++#define ixTHM_TMON0_RDIL0_DATA                                                  0xc0300100
++#define ixTHM_TMON0_RDIL1_DATA                                                  0xc0300104
++#define ixTHM_TMON0_RDIL2_DATA                                                  0xc0300108
++#define ixTHM_TMON0_RDIL3_DATA                                                  0xc030010c
++#define ixTHM_TMON0_RDIL4_DATA                                                  0xc0300110
++#define ixTHM_TMON0_RDIL5_DATA                                                  0xc0300114
++#define ixTHM_TMON0_RDIL6_DATA                                                  0xc0300118
++#define ixTHM_TMON0_RDIL7_DATA                                                  0xc030011c
++#define ixTHM_TMON0_RDIL8_DATA                                                  0xc0300120
++#define ixTHM_TMON0_RDIL9_DATA                                                  0xc0300124
++#define ixTHM_TMON0_RDIL10_DATA                                                 0xc0300128
++#define ixTHM_TMON0_RDIL11_DATA                                                 0xc030012c
++#define ixTHM_TMON0_RDIL12_DATA                                                 0xc0300130
++#define ixTHM_TMON0_RDIL13_DATA                                                 0xc0300134
++#define ixTHM_TMON0_RDIL14_DATA                                                 0xc0300138
++#define ixTHM_TMON0_RDIL15_DATA                                                 0xc030013c
++#define ixTHM_TMON0_RDIR0_DATA                                                  0xc0300140
++#define ixTHM_TMON0_RDIR1_DATA                                                  0xc0300144
++#define ixTHM_TMON0_RDIR2_DATA                                                  0xc0300148
++#define ixTHM_TMON0_RDIR3_DATA                                                  0xc030014c
++#define ixTHM_TMON0_RDIR4_DATA                                                  0xc0300150
++#define ixTHM_TMON0_RDIR5_DATA                                                  0xc0300154
++#define ixTHM_TMON0_RDIR6_DATA                                                  0xc0300158
++#define ixTHM_TMON0_RDIR7_DATA                                                  0xc030015c
++#define ixTHM_TMON0_RDIR8_DATA                                                  0xc0300160
++#define ixTHM_TMON0_RDIR9_DATA                                                  0xc0300164
++#define ixTHM_TMON0_RDIR10_DATA                                                 0xc0300168
++#define ixTHM_TMON0_RDIR11_DATA                                                 0xc030016c
++#define ixTHM_TMON0_RDIR12_DATA                                                 0xc0300170
++#define ixTHM_TMON0_RDIR13_DATA                                                 0xc0300174
++#define ixTHM_TMON0_RDIR14_DATA                                                 0xc0300178
++#define ixTHM_TMON0_RDIR15_DATA                                                 0xc030017c
++#define ixTHM_TMON0_INT_DATA                                                    0xc0300300
++#define ixTHM_TMON0_DEBUG                                                       0xc0300310
++#define ixTHM_TMON0_STATUS                                                      0xc0300320
++#define ixGENERAL_PWRMGT                                                        0xc0200000
++#define ixCNB_PWRMGT_CNTL                                                       0xc0200004
++#define ixSCLK_PWRMGT_CNTL                                                      0xc0200008
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xc0200014
++#define ixPWR_PCC_CONTROL                                                       0xc0200018
++#define ixPWR_PCC_GPIO_SELECT                                                   0xc020001c
++#define ixCG_FREQ_TRAN_VOTING_0                                                 0xc02001a8
++#define ixCG_FREQ_TRAN_VOTING_1                                                 0xc02001ac
++#define ixCG_FREQ_TRAN_VOTING_2                                                 0xc02001b0
++#define ixCG_FREQ_TRAN_VOTING_3                                                 0xc02001b4
++#define ixCG_FREQ_TRAN_VOTING_4                                                 0xc02001b8
++#define ixCG_FREQ_TRAN_VOTING_5                                                 0xc02001bc
++#define ixCG_FREQ_TRAN_VOTING_6                                                 0xc02001c0
++#define ixCG_FREQ_TRAN_VOTING_7                                                 0xc02001c4
++#define ixPLL_TEST_CNTL                                                         0xc020003c
++#define ixCG_STATIC_SCREEN_PARAMETER                                            0xc0200044
++#define ixCG_DISPLAY_GAP_CNTL                                                   0xc0200060
++#define ixCG_DISPLAY_GAP_CNTL2                                                  0xc0200230
++#define ixCG_ACPI_CNTL                                                          0xc0200064
++#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xc0200080
++#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xc0200084
++#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xc020009c
++#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xc0200088
++#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xc020008c
++#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xc0200310
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xc02000f0
++#define ixCG_ULV_PARAMETER                                                      0xc020015c
++#define ixSCLK_MIN_DIV                                                          0xc02003ac
++#define ixPWR_DISP_TIMER_0_CONTROL                                              0xc0200390
++#define ixPWR_DISP_TIMER_1_CONTROL                                              0xc020037c
++#define ixPWR_DISP_TIMER_2_CONTROL                                              0xc02003d0
++#define ixPWR_DISP_TIMER_3_CONTROL                                              0xc02003d4
++#define ixPWR_DISP_TIMER_4_CONTROL                                              0xc02003d8
++#define ixPWR_DISP_TIMER_5_CONTROL                                              0xc02003dc
++#define ixPWR_DISP_TIMER_6_CONTROL                                              0xc02003e0
++#define ixPWR_DISP_TIMER_7_CONTROL                                              0xc02003e4
++#define ixPWR_DISP_TIMER_8_CONTROL                                              0xc02003e8
++#define ixPWR_DISP_TIMER_9_CONTROL                                              0xc02003ec
++#define ixPWR_DISP_TIMER_10_CONTROL                                             0xc02003f0
++#define ixPWR_DISP_TIMER_11_CONTROL                                             0xc02003f4
++#define ixPWR_DISP_TIMER_12_CONTROL                                             0xc02003f8
++#define ixPWR_DISP_TIMER_13_CONTROL                                             0xc02003fc
++#define ixPWR_DISP_TIMER_14_CONTROL                                             0xc0200074
++#define ixPWR_DISP_TIMER_15_CONTROL                                             0xc0200078
++#define ixPWR_DISP_TIMER_CONTROL2                                               0xc0200378
++#define ixVDDGFX_IDLE_PARAMETER                                                 0xc020036c
++#define ixVDDGFX_IDLE_CONTROL                                                   0xc0200370
++#define ixVDDGFX_IDLE_EXIT                                                      0xc0200374
++#define ixLCAC_MC0_CNTL                                                         0xc0400130
++#define ixLCAC_MC0_OVR_SEL                                                      0xc0400134
++#define ixLCAC_MC0_OVR_VAL                                                      0xc0400138
++#define ixLCAC_MC1_CNTL                                                         0xc040013c
++#define ixLCAC_MC1_OVR_SEL                                                      0xc0400140
++#define ixLCAC_MC1_OVR_VAL                                                      0xc0400144
++#define ixLCAC_MC2_CNTL                                                         0xc0400148
++#define ixLCAC_MC2_OVR_SEL                                                      0xc040014c
++#define ixLCAC_MC2_OVR_VAL                                                      0xc0400150
++#define ixLCAC_MC3_CNTL                                                         0xc0400154
++#define ixLCAC_MC3_OVR_SEL                                                      0xc0400158
++#define ixLCAC_MC3_OVR_VAL                                                      0xc040015c
++#define ixLCAC_CPL_CNTL                                                         0xc0400160
++#define ixLCAC_CPL_OVR_SEL                                                      0xc0400164
++#define ixLCAC_CPL_OVR_VAL                                                      0xc0400168
++#define mmROM_SMC_IND_INDEX                                                     0x80
++#define mmROM0_ROM_SMC_IND_INDEX                                                0x80
++#define mmROM1_ROM_SMC_IND_INDEX                                                0x82
++#define mmROM2_ROM_SMC_IND_INDEX                                                0x84
++#define mmROM3_ROM_SMC_IND_INDEX                                                0x86
++#define mmROM_SMC_IND_DATA                                                      0x81
++#define mmROM0_ROM_SMC_IND_DATA                                                 0x81
++#define mmROM1_ROM_SMC_IND_DATA                                                 0x83
++#define mmROM2_ROM_SMC_IND_DATA                                                 0x85
++#define mmROM3_ROM_SMC_IND_DATA                                                 0x87
++#define ixROM_CNTL                                                              0xc0600000
++#define ixPAGE_MIRROR_CNTL                                                      0xc0600004
++#define ixROM_STATUS                                                            0xc0600008
++#define ixCGTT_ROM_CLK_CTRL0                                                    0xc060000c
++#define ixROM_INDEX                                                             0xc0600010
++#define ixROM_DATA                                                              0xc0600014
++#define ixROM_START                                                             0xc0600018
++#define ixROM_SW_CNTL                                                           0xc060001c
++#define ixROM_SW_STATUS                                                         0xc0600020
++#define ixROM_SW_COMMAND                                                        0xc0600024
++#define ixROM_SW_DATA_1                                                         0xc0600028
++#define ixROM_SW_DATA_2                                                         0xc060002c
++#define ixROM_SW_DATA_3                                                         0xc0600030
++#define ixROM_SW_DATA_4                                                         0xc0600034
++#define ixROM_SW_DATA_5                                                         0xc0600038
++#define ixROM_SW_DATA_6                                                         0xc060003c
++#define ixROM_SW_DATA_7                                                         0xc0600040
++#define ixROM_SW_DATA_8                                                         0xc0600044
++#define ixROM_SW_DATA_9                                                         0xc0600048
++#define ixROM_SW_DATA_10                                                        0xc060004c
++#define ixROM_SW_DATA_11                                                        0xc0600050
++#define ixROM_SW_DATA_12                                                        0xc0600054
++#define ixROM_SW_DATA_13                                                        0xc0600058
++#define ixROM_SW_DATA_14                                                        0xc060005c
++#define ixROM_SW_DATA_15                                                        0xc0600060
++#define ixROM_SW_DATA_16                                                        0xc0600064
++#define ixROM_SW_DATA_17                                                        0xc0600068
++#define ixROM_SW_DATA_18                                                        0xc060006c
++#define ixROM_SW_DATA_19                                                        0xc0600070
++#define ixROM_SW_DATA_20                                                        0xc0600074
++#define ixROM_SW_DATA_21                                                        0xc0600078
++#define ixROM_SW_DATA_22                                                        0xc060007c
++#define ixROM_SW_DATA_23                                                        0xc0600080
++#define ixROM_SW_DATA_24                                                        0xc0600084
++#define ixROM_SW_DATA_25                                                        0xc0600088
++#define ixROM_SW_DATA_26                                                        0xc060008c
++#define ixROM_SW_DATA_27                                                        0xc0600090
++#define ixROM_SW_DATA_28                                                        0xc0600094
++#define ixROM_SW_DATA_29                                                        0xc0600098
++#define ixROM_SW_DATA_30                                                        0xc060009c
++#define ixROM_SW_DATA_31                                                        0xc06000a0
++#define ixROM_SW_DATA_32                                                        0xc06000a4
++#define ixROM_SW_DATA_33                                                        0xc06000a8
++#define ixROM_SW_DATA_34                                                        0xc06000ac
++#define ixROM_SW_DATA_35                                                        0xc06000b0
++#define ixROM_SW_DATA_36                                                        0xc06000b4
++#define ixROM_SW_DATA_37                                                        0xc06000b8
++#define ixROM_SW_DATA_38                                                        0xc06000bc
++#define ixROM_SW_DATA_39                                                        0xc06000c0
++#define ixROM_SW_DATA_40                                                        0xc06000c4
++#define ixROM_SW_DATA_41                                                        0xc06000c8
++#define ixROM_SW_DATA_42                                                        0xc06000cc
++#define ixROM_SW_DATA_43                                                        0xc06000d0
++#define ixROM_SW_DATA_44                                                        0xc06000d4
++#define ixROM_SW_DATA_45                                                        0xc06000d8
++#define ixROM_SW_DATA_46                                                        0xc06000dc
++#define ixROM_SW_DATA_47                                                        0xc06000e0
++#define ixROM_SW_DATA_48                                                        0xc06000e4
++#define ixROM_SW_DATA_49                                                        0xc06000e8
++#define ixROM_SW_DATA_50                                                        0xc06000ec
++#define ixROM_SW_DATA_51                                                        0xc06000f0
++#define ixROM_SW_DATA_52                                                        0xc06000f4
++#define ixROM_SW_DATA_53                                                        0xc06000f8
++#define ixROM_SW_DATA_54                                                        0xc06000fc
++#define ixROM_SW_DATA_55                                                        0xc0600100
++#define ixROM_SW_DATA_56                                                        0xc0600104
++#define ixROM_SW_DATA_57                                                        0xc0600108
++#define ixROM_SW_DATA_58                                                        0xc060010c
++#define ixROM_SW_DATA_59                                                        0xc0600110
++#define ixROM_SW_DATA_60                                                        0xc0600114
++#define ixROM_SW_DATA_61                                                        0xc0600118
++#define ixROM_SW_DATA_62                                                        0xc060011c
++#define ixROM_SW_DATA_63                                                        0xc0600120
++#define ixROM_SW_DATA_64                                                        0xc0600124
++
++#endif /* SMU_7_1_1_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
+new file mode 100644
+index 0000000..c1a7aba
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
+@@ -0,0 +1,1205 @@
++/*
++ * SMU_7_1_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_1_ENUM_H
++#define SMU_7_1_1_ENUM_H
++
++#define CG_SRBM_START_ADDR                        0x600
++#define CG_SRBM_END_ADDR                          0x8ff
++#define RCU_CCF_DWORDS0                           0x80
++#define RCU_CCF_BITS0                             0x1000
++#define RCU_CCF_DWORDS1                           0x0
++#define RCU_CCF_BITS1                             0x0
++#define RCU_SAM_BYTES                             0x0
++#define RCU_SAM_RTL_BYTES                         0x0
++#define RCU_SMU_BYTES                             0x0
++#define RCU_SMU_RTL_BYTES                         0x0
++#define SFP_CHAIN_ADDR                            0x0
++#define SFP_BYTES                                 0x80
++#define SFP_SADR                                  0x180
++#define SFP_EADR                                  0x1ff
++#define SAMU_KEY_CHAIN_ADR                        0x0
++#define SAMU_KEY_SADR                             0x0
++#define SAMU_KEY_EADR                             0x0
++#define SMU_KEY_CHAIN_ADR                         0x0
++#define SMU_KEY_SADR                              0x0
++#define SMU_KEY_EADR                              0x0
++#define SMC_MSG_TEST                              0x1
++#define SMC_MSG_PHY_LN_OFF                        0x2
++#define SMC_MSG_PHY_LN_ON                         0x3
++#define SMC_MSG_DDI_PHY_OFF                       0x4
++#define SMC_MSG_DDI_PHY_ON                        0x5
++#define SMC_MSG_CASCADE_PLL_OFF                   0x6
++#define SMC_MSG_CASCADE_PLL_ON                    0x7
++#define SMC_MSG_PWR_OFF_x16                       0x8
++#define SMC_MSG_CONFIG_LCLK_DPM                   0x9
++#define SMC_MSG_FLUSH_DATA_CACHE                  0xa
++#define SMC_MSG_FLUSH_INSTRUCTION_CACHE           0xb
++#define SMC_MSG_CONFIG_VPC_ACCUMULATOR            0xc
++#define SMC_MSG_CONFIG_BAPM                       0xd
++#define SMC_MSG_CONFIG_TDC_LIMIT                  0xe
++#define SMC_MSG_CONFIG_LPMx                       0xf
++#define SMC_MSG_CONFIG_HTC_LIMIT                  0x10
++#define SMC_MSG_CONFIG_THERMAL_CNTL               0x11
++#define SMC_MSG_CONFIG_VOLTAGE_CNTL               0x12
++#define SMC_MSG_CONFIG_TDP_CNTL                   0x13
++#define SMC_MSG_EN_PM_CNTL                        0x14
++#define SMC_MSG_DIS_PM_CNTL                       0x15
++#define SMC_MSG_CONFIG_NBDPM                      0x16
++#define SMC_MSG_CONFIG_LOADLINE                   0x17
++#define SMC_MSG_ADJUST_LOADLINE                   0x18
++#define SMC_MSG_RESET                             0x20
++#define SMC_MSG_VOLTAGE                           0x25
++#define SMC_VERSION_MAJOR                         0x7
++#define SMC_VERSION_MINOR                         0x0
++#define SMC_HEADER_SIZE                           0x40
++#define ROM_SIGNATURE                             0xaa55
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x2,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x3,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x4,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x5,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x6,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x7,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x8,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x9,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xc,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xd,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0xe,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0xf,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x10,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x11,
++	DBG_CLIENT_BLKID_vcea_0                          = 0x12,
++	DBG_CLIENT_BLKID_vcea_1                          = 0x13,
++	DBG_CLIENT_BLKID_vcea_2                          = 0x14,
++	DBG_CLIENT_BLKID_vcea_3                          = 0x15,
++	DBG_CLIENT_BLKID_vceb_0                          = 0x16,
++	DBG_CLIENT_BLKID_vcec_0                          = 0x17,
++	DBG_CLIENT_BLKID_dco                             = 0x18,
++	DBG_CLIENT_BLKID_xdma                            = 0x19,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x1a,
++	DBG_CLIENT_BLKID_smu_0                           = 0x1b,
++	DBG_CLIENT_BLKID_smu_1                           = 0x1c,
++	DBG_CLIENT_BLKID_smu_2                           = 0x1d,
++	DBG_CLIENT_BLKID_gck                             = 0x1e,
++	DBG_CLIENT_BLKID_tmonw0                          = 0x1f,
++	DBG_CLIENT_BLKID_tmonw1                          = 0x20,
++	DBG_CLIENT_BLKID_grbm                            = 0x21,
++	DBG_CLIENT_BLKID_rlc                             = 0x22,
++	DBG_CLIENT_BLKID_ds0                             = 0x23,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x24,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x25,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x26,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x27,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x29,
++	DBG_CLIENT_BLKID_scf0                            = 0x2a,
++	DBG_CLIENT_BLKID_scf1                            = 0x2b,
++	DBG_CLIENT_BLKID_scf2                            = 0x2c,
++	DBG_CLIENT_BLKID_scf3                            = 0x2d,
++	DBG_CLIENT_BLKID_pc0                             = 0x2e,
++	DBG_CLIENT_BLKID_pc1                             = 0x2f,
++	DBG_CLIENT_BLKID_pc2                             = 0x30,
++	DBG_CLIENT_BLKID_pc3                             = 0x31,
++	DBG_CLIENT_BLKID_vgt0                            = 0x32,
++	DBG_CLIENT_BLKID_vgt1                            = 0x33,
++	DBG_CLIENT_BLKID_vgt2                            = 0x34,
++	DBG_CLIENT_BLKID_vgt3                            = 0x35,
++	DBG_CLIENT_BLKID_sx00                            = 0x36,
++	DBG_CLIENT_BLKID_sx10                            = 0x37,
++	DBG_CLIENT_BLKID_sx20                            = 0x38,
++	DBG_CLIENT_BLKID_sx30                            = 0x39,
++	DBG_CLIENT_BLKID_cb001                           = 0x3a,
++	DBG_CLIENT_BLKID_cb200                           = 0x3b,
++	DBG_CLIENT_BLKID_cb201                           = 0x3c,
++	DBG_CLIENT_BLKID_cbr0                            = 0x3d,
++	DBG_CLIENT_BLKID_cb000                           = 0x3e,
++	DBG_CLIENT_BLKID_cb101                           = 0x3f,
++	DBG_CLIENT_BLKID_cb300                           = 0x40,
++	DBG_CLIENT_BLKID_cb301                           = 0x41,
++	DBG_CLIENT_BLKID_cbr1                            = 0x42,
++	DBG_CLIENT_BLKID_cb100                           = 0x43,
++	DBG_CLIENT_BLKID_ia0                             = 0x44,
++	DBG_CLIENT_BLKID_ia1                             = 0x45,
++	DBG_CLIENT_BLKID_bci0                            = 0x46,
++	DBG_CLIENT_BLKID_bci1                            = 0x47,
++	DBG_CLIENT_BLKID_bci2                            = 0x48,
++	DBG_CLIENT_BLKID_bci3                            = 0x49,
++	DBG_CLIENT_BLKID_pa0                             = 0x4a,
++	DBG_CLIENT_BLKID_pa1                             = 0x4b,
++	DBG_CLIENT_BLKID_spim0                           = 0x4c,
++	DBG_CLIENT_BLKID_spim1                           = 0x4d,
++	DBG_CLIENT_BLKID_spim2                           = 0x4e,
++	DBG_CLIENT_BLKID_spim3                           = 0x4f,
++	DBG_CLIENT_BLKID_sdma                            = 0x50,
++	DBG_CLIENT_BLKID_ih                              = 0x51,
++	DBG_CLIENT_BLKID_sem                             = 0x52,
++	DBG_CLIENT_BLKID_srbm                            = 0x53,
++	DBG_CLIENT_BLKID_hdp                             = 0x54,
++	DBG_CLIENT_BLKID_acp_0                           = 0x55,
++	DBG_CLIENT_BLKID_acp_1                           = 0x56,
++	DBG_CLIENT_BLKID_sam                             = 0x57,
++	DBG_CLIENT_BLKID_mcc0                            = 0x58,
++	DBG_CLIENT_BLKID_mcc1                            = 0x59,
++	DBG_CLIENT_BLKID_mcc2                            = 0x5a,
++	DBG_CLIENT_BLKID_mcc3                            = 0x5b,
++	DBG_CLIENT_BLKID_mcd0                            = 0x5c,
++	DBG_CLIENT_BLKID_mcd1                            = 0x5d,
++	DBG_CLIENT_BLKID_mcd2                            = 0x5e,
++	DBG_CLIENT_BLKID_mcd3                            = 0x5f,
++	DBG_CLIENT_BLKID_mcb                             = 0x60,
++	DBG_CLIENT_BLKID_vmc                             = 0x61,
++	DBG_CLIENT_BLKID_gmcon                           = 0x62,
++	DBG_CLIENT_BLKID_gdc_0                           = 0x63,
++	DBG_CLIENT_BLKID_gdc_1                           = 0x64,
++	DBG_CLIENT_BLKID_gdc_2                           = 0x65,
++	DBG_CLIENT_BLKID_gdc_3                           = 0x66,
++	DBG_CLIENT_BLKID_gdc_4                           = 0x67,
++	DBG_CLIENT_BLKID_gdc_5                           = 0x68,
++	DBG_CLIENT_BLKID_gdc_6                           = 0x69,
++	DBG_CLIENT_BLKID_gdc_7                           = 0x6a,
++	DBG_CLIENT_BLKID_gdc_8                           = 0x6b,
++	DBG_CLIENT_BLKID_gdc_9                           = 0x6c,
++	DBG_CLIENT_BLKID_gdc_10                          = 0x6d,
++	DBG_CLIENT_BLKID_gdc_11                          = 0x6e,
++	DBG_CLIENT_BLKID_gdc_12                          = 0x6f,
++	DBG_CLIENT_BLKID_gdc_13                          = 0x70,
++	DBG_CLIENT_BLKID_gdc_14                          = 0x71,
++	DBG_CLIENT_BLKID_gdc_15                          = 0x72,
++	DBG_CLIENT_BLKID_gdc_16                          = 0x73,
++	DBG_CLIENT_BLKID_gdc_17                          = 0x74,
++	DBG_CLIENT_BLKID_gdc_18                          = 0x75,
++	DBG_CLIENT_BLKID_gdc_19                          = 0x76,
++	DBG_CLIENT_BLKID_gdc_20                          = 0x77,
++	DBG_CLIENT_BLKID_gdc_21                          = 0x78,
++	DBG_CLIENT_BLKID_gdc_22                          = 0x79,
++	DBG_CLIENT_BLKID_gdc_23                          = 0x7a,
++	DBG_CLIENT_BLKID_gdc_24                          = 0x7b,
++	DBG_CLIENT_BLKID_gdc_25                          = 0x7c,
++	DBG_CLIENT_BLKID_gdc_26                          = 0x7d,
++	DBG_CLIENT_BLKID_gdc_27                          = 0x7e,
++	DBG_CLIENT_BLKID_gdc_28                          = 0x7f,
++	DBG_CLIENT_BLKID_wd                              = 0x80,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x81,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x82,
++	DBG_CLIENT_BLKID_sammsp                          = 0x83,
++	DBG_CLIENT_BLKID_dci_0                           = 0x84,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x85,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x86,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x87,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x88,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x89,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++
++#endif /* SMU_7_1_1_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
+new file mode 100644
+index 0000000..2c997f7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
+@@ -0,0 +1,4864 @@
++/*
++ * SMU_7_1_1 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_1_SH_MASK_H
++#define SMU_7_1_1_SH_MASK_H
++
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
++#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
++#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
++#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
++#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
++#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
++#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
++#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
++#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
++#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
++#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
++#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
++#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
++#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
++#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
++#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
++#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
++#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
++#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
++#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
++#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
++#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200
++#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
++#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
++#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
++#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
++#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
++#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
++#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
++#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
++#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
++#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
++#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_0__SMC_RESP_MASK 0xffff
++#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_1__SMC_RESP_MASK 0xffff
++#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_2__SMC_RESP_MASK 0xffff
++#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_3__SMC_RESP_MASK 0xffff
++#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_4__SMC_RESP_MASK 0xffff
++#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_5__SMC_RESP_MASK 0xffff
++#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_6__SMC_RESP_MASK 0xffff
++#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_7__SMC_RESP_MASK 0xffff
++#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_8__SMC_RESP_MASK 0xffff
++#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_9__SMC_RESP_MASK 0xffff
++#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_10__SMC_RESP_MASK 0xffff
++#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_11__SMC_RESP_MASK 0xffff
++#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
++#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
++#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
++#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
++#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
++#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
++#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
++#define SMC_PC_C__smc_pc_c__SHIFT 0x0
++#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
++#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
++#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
++#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
++#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
++#define GPIOPAD_A__GPIO_A__SHIFT 0x0
++#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
++#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
++#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
++#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
++#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
++#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
++#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
++#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
++#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
++#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff
++#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
++#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
++#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
++#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
++#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
++#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
++#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
++#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
++#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
++#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
++#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
++#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
++#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
++#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
++#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
++#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
++#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
++#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
++#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
++#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
++#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
++#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
++#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
++#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
++#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
++#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
++#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
++#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
++#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
++#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
++#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
++#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10
++#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000
++#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13
++#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000
++#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16
++#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000
++#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17
++#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000
++#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18
++#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000
++#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19
++#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000
++#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
++#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
++#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
++#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
++#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
++#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
++#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
++#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
++#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
++#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
++#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
++#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
++#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
++#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
++#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
++#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
++#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
++#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
++#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
++#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
++#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
++#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
++#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6
++#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1
++#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10
++#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4
++#define CC_HARVEST_FUSES__ACP_EXISTS_MASK 0x40
++#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT 0x6
++#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00
++#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
++#define SMU_STATUS__SMU_DONE_MASK 0x1
++#define SMU_STATUS__SMU_DONE__SHIFT 0x0
++#define SMU_STATUS__SMU_PASS_MASK 0x2
++#define SMU_STATUS__SMU_PASS__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
++#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
++#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
++#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
++#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
++#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
++#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
++#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
++#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
++#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
++#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
++#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
++#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
++#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
++#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18
++#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
++#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
++#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
++#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
++#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
++#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
++#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
++#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
++#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
++#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
++#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
++#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
++#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
++#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
++#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
++#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
++#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
++#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
++#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
++#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
++#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
++#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
++#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
++#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
++#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
++#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
++#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
++#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
++#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
++#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
++#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
++#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
++#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
++#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
++#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
++#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
++#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
++#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
++#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
++#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
++#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
++#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
++#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
++#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
++#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
++#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
++#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
++#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
++#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
++#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
++#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
++#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
++#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
++#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
++#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
++#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
++#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
++#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
++#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
++#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
++#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
++#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
++#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
++#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
++#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
++#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
++#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
++#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
++#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
++#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
++#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
++#define DPM_TABLE_68__MasterDeepSleepControl_MASK 0xff
++#define DPM_TABLE_68__MasterDeepSleepControl__SHIFT 0x0
++#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
++#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
++#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
++#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
++#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
++#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
++#define DPM_TABLE_69__Reserved_0_MASK 0xffffffff
++#define DPM_TABLE_69__Reserved_0__SHIFT 0x0
++#define DPM_TABLE_70__Reserved_1_MASK 0xffffffff
++#define DPM_TABLE_70__Reserved_1__SHIFT 0x0
++#define DPM_TABLE_71__Reserved_2_MASK 0xffffffff
++#define DPM_TABLE_71__Reserved_2__SHIFT 0x0
++#define DPM_TABLE_72__Reserved_3_MASK 0xffffffff
++#define DPM_TABLE_72__Reserved_3__SHIFT 0x0
++#define DPM_TABLE_73__Reserved_4_MASK 0xffffffff
++#define DPM_TABLE_73__Reserved_4__SHIFT 0x0
++#define DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT 0x0
++#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK 0xff000000
++#define DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT 0x18
++#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK 0xff
++#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT 0x0
++#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK 0xff000000
++#define DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT 0x18
++#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK 0xff
++#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT 0x0
++#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK 0xff000000
++#define DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT 0x18
++#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK 0xff
++#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT 0x0
++#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK 0xff000000
++#define DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT 0x18
++#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK 0xff
++#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT 0x0
++#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK 0xff000000
++#define DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT 0x18
++#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK 0xff
++#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK 0xff0000
++#define DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT 0x10
++#define DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK 0xff000000
++#define DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT 0x18
++#define DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT 0x0
++#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK 0xff000000
++#define DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT 0x18
++#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK 0xff
++#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK 0xff0000
++#define DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT 0x10
++#define DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK 0xff000000
++#define DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT 0x18
++#define DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT 0x0
++#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK 0xff000000
++#define DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT 0x18
++#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK 0xff
++#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK 0xff0000
++#define DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT 0x10
++#define DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK 0xff000000
++#define DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT 0x18
++#define DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT 0x0
++#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK 0xff000000
++#define DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT 0x18
++#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK 0xff
++#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK 0xff0000
++#define DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT 0x10
++#define DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK 0xff000000
++#define DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT 0x18
++#define DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT 0x0
++#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT 0x0
++#define DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK 0xff
++#define DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK 0xff00
++#define DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT 0x8
++#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_177__MemoryACPILevel_padding_MASK 0xff
++#define DPM_TABLE_177__MemoryACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK 0xff0000
++#define DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT 0x10
++#define DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK 0xff000000
++#define DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT 0x18
++#define DPM_TABLE_178__MemoryACPILevel_padding1_MASK 0xff
++#define DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT 0x0
++#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT 0x0
++#define DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT 0x0
++#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT 0x0
++#define DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK 0xff
++#define DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK 0xff00
++#define DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT 0x8
++#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_195__MemoryLevel_0_padding_MASK 0xff
++#define DPM_TABLE_195__MemoryLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_196__MemoryLevel_0_padding1_MASK 0xff
++#define DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT 0x0
++#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT 0x0
++#define DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT 0x0
++#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT 0x0
++#define DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK 0xff
++#define DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK 0xff00
++#define DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT 0x8
++#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_213__MemoryLevel_1_padding_MASK 0xff
++#define DPM_TABLE_213__MemoryLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_214__MemoryLevel_1_padding1_MASK 0xff
++#define DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT 0x0
++#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT 0x0
++#define DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT 0x0
++#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT 0x0
++#define DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK 0xff
++#define DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK 0xff00
++#define DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT 0x8
++#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_231__MemoryLevel_2_padding_MASK 0xff
++#define DPM_TABLE_231__MemoryLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_232__MemoryLevel_2_padding1_MASK 0xff
++#define DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT 0x0
++#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT 0x0
++#define DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT 0x0
++#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK 0xffffffff
++#define DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT 0x0
++#define DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK 0xff
++#define DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK 0xff00
++#define DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT 0x8
++#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_249__MemoryLevel_3_padding_MASK 0xff
++#define DPM_TABLE_249__MemoryLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_250__MemoryLevel_3_padding1_MASK 0xff
++#define DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT 0x0
++#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT 0x0
++#define DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_260__LinkLevel_0_SPC_MASK 0xff
++#define DPM_TABLE_260__LinkLevel_0_SPC__SHIFT 0x0
++#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_263__LinkLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_264__LinkLevel_1_SPC_MASK 0xff
++#define DPM_TABLE_264__LinkLevel_1_SPC__SHIFT 0x0
++#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_267__LinkLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_268__LinkLevel_2_SPC_MASK 0xff
++#define DPM_TABLE_268__LinkLevel_2_SPC__SHIFT 0x0
++#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_271__LinkLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_272__LinkLevel_3_SPC_MASK 0xff
++#define DPM_TABLE_272__LinkLevel_3_SPC__SHIFT 0x0
++#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_275__LinkLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_276__LinkLevel_4_SPC_MASK 0xff
++#define DPM_TABLE_276__LinkLevel_4_SPC__SHIFT 0x0
++#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_279__LinkLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_280__LinkLevel_5_SPC_MASK 0xff
++#define DPM_TABLE_280__LinkLevel_5_SPC__SHIFT 0x0
++#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_283__LinkLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_284__LinkLevel_6_SPC_MASK 0xff
++#define DPM_TABLE_284__LinkLevel_6_SPC__SHIFT 0x0
++#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_287__LinkLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_288__LinkLevel_7_SPC_MASK 0xff
++#define DPM_TABLE_288__LinkLevel_7_SPC__SHIFT 0x0
++#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_291__LinkLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_292__ACPILevel_Flags_MASK 0xffffffff
++#define DPM_TABLE_292__ACPILevel_Flags__SHIFT 0x0
++#define DPM_TABLE_293__ACPILevel_MinVddc_MASK 0xffffffff
++#define DPM_TABLE_293__ACPILevel_MinVddc__SHIFT 0x0
++#define DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK 0xffffffff
++#define DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT 0x0
++#define DPM_TABLE_295__ACPILevel_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_296__ACPILevel_padding_MASK 0xff
++#define DPM_TABLE_296__ACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_296__ACPILevel_SclkDid_MASK 0xff000000
++#define DPM_TABLE_296__ACPILevel_SclkDid__SHIFT 0x18
++#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
++#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
++#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_305__SclkStepSize_MASK 0xffffffff
++#define DPM_TABLE_305__SclkStepSize__SHIFT 0x0
++#define DPM_TABLE_306__Smio_0_MASK 0xffffffff
++#define DPM_TABLE_306__Smio_0__SHIFT 0x0
++#define DPM_TABLE_307__Smio_1_MASK 0xffffffff
++#define DPM_TABLE_307__Smio_1__SHIFT 0x0
++#define DPM_TABLE_308__Smio_2_MASK 0xffffffff
++#define DPM_TABLE_308__Smio_2__SHIFT 0x0
++#define DPM_TABLE_309__Smio_3_MASK 0xffffffff
++#define DPM_TABLE_309__Smio_3__SHIFT 0x0
++#define DPM_TABLE_310__Smio_4_MASK 0xffffffff
++#define DPM_TABLE_310__Smio_4__SHIFT 0x0
++#define DPM_TABLE_311__Smio_5_MASK 0xffffffff
++#define DPM_TABLE_311__Smio_5__SHIFT 0x0
++#define DPM_TABLE_312__Smio_6_MASK 0xffffffff
++#define DPM_TABLE_312__Smio_6__SHIFT 0x0
++#define DPM_TABLE_313__Smio_7_MASK 0xffffffff
++#define DPM_TABLE_313__Smio_7__SHIFT 0x0
++#define DPM_TABLE_314__Smio_8_MASK 0xffffffff
++#define DPM_TABLE_314__Smio_8__SHIFT 0x0
++#define DPM_TABLE_315__Smio_9_MASK 0xffffffff
++#define DPM_TABLE_315__Smio_9__SHIFT 0x0
++#define DPM_TABLE_316__Smio_10_MASK 0xffffffff
++#define DPM_TABLE_316__Smio_10__SHIFT 0x0
++#define DPM_TABLE_317__Smio_11_MASK 0xffffffff
++#define DPM_TABLE_317__Smio_11__SHIFT 0x0
++#define DPM_TABLE_318__Smio_12_MASK 0xffffffff
++#define DPM_TABLE_318__Smio_12__SHIFT 0x0
++#define DPM_TABLE_319__Smio_13_MASK 0xffffffff
++#define DPM_TABLE_319__Smio_13__SHIFT 0x0
++#define DPM_TABLE_320__Smio_14_MASK 0xffffffff
++#define DPM_TABLE_320__Smio_14__SHIFT 0x0
++#define DPM_TABLE_321__Smio_15_MASK 0xffffffff
++#define DPM_TABLE_321__Smio_15__SHIFT 0x0
++#define DPM_TABLE_322__Smio_16_MASK 0xffffffff
++#define DPM_TABLE_322__Smio_16__SHIFT 0x0
++#define DPM_TABLE_323__Smio_17_MASK 0xffffffff
++#define DPM_TABLE_323__Smio_17__SHIFT 0x0
++#define DPM_TABLE_324__Smio_18_MASK 0xffffffff
++#define DPM_TABLE_324__Smio_18__SHIFT 0x0
++#define DPM_TABLE_325__Smio_19_MASK 0xffffffff
++#define DPM_TABLE_325__Smio_19__SHIFT 0x0
++#define DPM_TABLE_326__Smio_20_MASK 0xffffffff
++#define DPM_TABLE_326__Smio_20__SHIFT 0x0
++#define DPM_TABLE_327__Smio_21_MASK 0xffffffff
++#define DPM_TABLE_327__Smio_21__SHIFT 0x0
++#define DPM_TABLE_328__Smio_22_MASK 0xffffffff
++#define DPM_TABLE_328__Smio_22__SHIFT 0x0
++#define DPM_TABLE_329__Smio_23_MASK 0xffffffff
++#define DPM_TABLE_329__Smio_23__SHIFT 0x0
++#define DPM_TABLE_330__Smio_24_MASK 0xffffffff
++#define DPM_TABLE_330__Smio_24__SHIFT 0x0
++#define DPM_TABLE_331__Smio_25_MASK 0xffffffff
++#define DPM_TABLE_331__Smio_25__SHIFT 0x0
++#define DPM_TABLE_332__Smio_26_MASK 0xffffffff
++#define DPM_TABLE_332__Smio_26__SHIFT 0x0
++#define DPM_TABLE_333__Smio_27_MASK 0xffffffff
++#define DPM_TABLE_333__Smio_27__SHIFT 0x0
++#define DPM_TABLE_334__Smio_28_MASK 0xffffffff
++#define DPM_TABLE_334__Smio_28__SHIFT 0x0
++#define DPM_TABLE_335__Smio_29_MASK 0xffffffff
++#define DPM_TABLE_335__Smio_29__SHIFT 0x0
++#define DPM_TABLE_336__Smio_30_MASK 0xffffffff
++#define DPM_TABLE_336__Smio_30__SHIFT 0x0
++#define DPM_TABLE_337__Smio_31_MASK 0xffffffff
++#define DPM_TABLE_337__Smio_31__SHIFT 0x0
++#define DPM_TABLE_338__GraphicsInterval_MASK 0xff
++#define DPM_TABLE_338__GraphicsInterval__SHIFT 0x0
++#define DPM_TABLE_338__GraphicsThermThrottleEnable_MASK 0xff00
++#define DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT 0x8
++#define DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK 0xff0000
++#define DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT 0x10
++#define DPM_TABLE_338__GraphicsBootLevel_MASK 0xff000000
++#define DPM_TABLE_338__GraphicsBootLevel__SHIFT 0x18
++#define DPM_TABLE_339__TemperatureLimitHigh_MASK 0xffff
++#define DPM_TABLE_339__TemperatureLimitHigh__SHIFT 0x0
++#define DPM_TABLE_339__ThermalInterval_MASK 0xff0000
++#define DPM_TABLE_339__ThermalInterval__SHIFT 0x10
++#define DPM_TABLE_339__VoltageInterval_MASK 0xff000000
++#define DPM_TABLE_339__VoltageInterval__SHIFT 0x18
++#define DPM_TABLE_340__MemoryVoltageChangeEnable_MASK 0xff
++#define DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT 0x0
++#define DPM_TABLE_340__MemoryBootLevel_MASK 0xff00
++#define DPM_TABLE_340__MemoryBootLevel__SHIFT 0x8
++#define DPM_TABLE_340__TemperatureLimitLow_MASK 0xffff0000
++#define DPM_TABLE_340__TemperatureLimitLow__SHIFT 0x10
++#define DPM_TABLE_341__padding2_MASK 0xff
++#define DPM_TABLE_341__padding2__SHIFT 0x0
++#define DPM_TABLE_341__MergedVddci_MASK 0xff00
++#define DPM_TABLE_341__MergedVddci__SHIFT 0x8
++#define DPM_TABLE_341__MemoryThermThrottleEnable_MASK 0xff0000
++#define DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT 0x10
++#define DPM_TABLE_341__MemoryInterval_MASK 0xff000000
++#define DPM_TABLE_341__MemoryInterval__SHIFT 0x18
++#define DPM_TABLE_342__PhaseResponseTime_MASK 0xffff
++#define DPM_TABLE_342__PhaseResponseTime__SHIFT 0x0
++#define DPM_TABLE_342__VoltageResponseTime_MASK 0xffff0000
++#define DPM_TABLE_342__VoltageResponseTime__SHIFT 0x10
++#define DPM_TABLE_343__DTEMode_MASK 0xff
++#define DPM_TABLE_343__DTEMode__SHIFT 0x0
++#define DPM_TABLE_343__DTEInterval_MASK 0xff00
++#define DPM_TABLE_343__DTEInterval__SHIFT 0x8
++#define DPM_TABLE_343__PCIeGenInterval_MASK 0xff0000
++#define DPM_TABLE_343__PCIeGenInterval__SHIFT 0x10
++#define DPM_TABLE_343__PCIeBootLinkLevel_MASK 0xff000000
++#define DPM_TABLE_343__PCIeBootLinkLevel__SHIFT 0x18
++#define DPM_TABLE_344__ThermGpio_MASK 0xff
++#define DPM_TABLE_344__ThermGpio__SHIFT 0x0
++#define DPM_TABLE_344__AcDcGpio_MASK 0xff00
++#define DPM_TABLE_344__AcDcGpio__SHIFT 0x8
++#define DPM_TABLE_344__VRHotGpio_MASK 0xff0000
++#define DPM_TABLE_344__VRHotGpio__SHIFT 0x10
++#define DPM_TABLE_344__SVI2Enable_MASK 0xff000000
++#define DPM_TABLE_344__SVI2Enable__SHIFT 0x18
++#define DPM_TABLE_345__DisplayCac_MASK 0xffffffff
++#define DPM_TABLE_345__DisplayCac__SHIFT 0x0
++#define DPM_TABLE_346__NomPwr_MASK 0xffff
++#define DPM_TABLE_346__NomPwr__SHIFT 0x0
++#define DPM_TABLE_346__MaxPwr_MASK 0xffff0000
++#define DPM_TABLE_346__MaxPwr__SHIFT 0x10
++#define DPM_TABLE_347__FpsLowThreshold_MASK 0xffff
++#define DPM_TABLE_347__FpsLowThreshold__SHIFT 0x0
++#define DPM_TABLE_347__FpsHighThreshold_MASK 0xffff0000
++#define DPM_TABLE_347__FpsHighThreshold__SHIFT 0x10
++#define DPM_TABLE_348__BAPMTI_R_0_1_0_MASK 0xffff
++#define DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT 0x0
++#define DPM_TABLE_348__BAPMTI_R_0_0_0_MASK 0xffff0000
++#define DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT 0x10
++#define DPM_TABLE_349__BAPMTI_R_1_0_0_MASK 0xffff
++#define DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT 0x0
++#define DPM_TABLE_349__BAPMTI_R_0_2_0_MASK 0xffff0000
++#define DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT 0x10
++#define DPM_TABLE_350__BAPMTI_R_1_2_0_MASK 0xffff
++#define DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT 0x0
++#define DPM_TABLE_350__BAPMTI_R_1_1_0_MASK 0xffff0000
++#define DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT 0x10
++#define DPM_TABLE_351__BAPMTI_R_2_1_0_MASK 0xffff
++#define DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT 0x0
++#define DPM_TABLE_351__BAPMTI_R_2_0_0_MASK 0xffff0000
++#define DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT 0x10
++#define DPM_TABLE_352__BAPMTI_R_3_0_0_MASK 0xffff
++#define DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT 0x0
++#define DPM_TABLE_352__BAPMTI_R_2_2_0_MASK 0xffff0000
++#define DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT 0x10
++#define DPM_TABLE_353__BAPMTI_R_3_2_0_MASK 0xffff
++#define DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT 0x0
++#define DPM_TABLE_353__BAPMTI_R_3_1_0_MASK 0xffff0000
++#define DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT 0x10
++#define DPM_TABLE_354__BAPMTI_R_4_1_0_MASK 0xffff
++#define DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT 0x0
++#define DPM_TABLE_354__BAPMTI_R_4_0_0_MASK 0xffff0000
++#define DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT 0x10
++#define DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK 0xffff
++#define DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT 0x0
++#define DPM_TABLE_355__BAPMTI_R_4_2_0_MASK 0xffff0000
++#define DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT 0x10
++#define DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK 0xffff
++#define DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT 0x0
++#define DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK 0xffff0000
++#define DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT 0x10
++#define DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK 0xffff
++#define DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT 0x0
++#define DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK 0xffff0000
++#define DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT 0x10
++#define DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK 0xffff
++#define DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT 0x0
++#define DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK 0xffff0000
++#define DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT 0x10
++#define DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK 0xffff
++#define DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT 0x0
++#define DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK 0xffff0000
++#define DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT 0x10
++#define DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK 0xffff
++#define DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT 0x0
++#define DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK 0xffff0000
++#define DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT 0x10
++#define DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK 0xffff
++#define DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT 0x0
++#define DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK 0xffff0000
++#define DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT 0x10
++#define DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK 0xffff
++#define DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT 0x0
++#define DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK 0xffff0000
++#define DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT 0x10
++#define DPM_TABLE_363__GpuTjHyst_MASK 0xff
++#define DPM_TABLE_363__GpuTjHyst__SHIFT 0x0
++#define DPM_TABLE_363__GpuTjMax_MASK 0xff00
++#define DPM_TABLE_363__GpuTjMax__SHIFT 0x8
++#define DPM_TABLE_363__DTETjOffset_MASK 0xff0000
++#define DPM_TABLE_363__DTETjOffset__SHIFT 0x10
++#define DPM_TABLE_363__DTEAmbientTempBase_MASK 0xff000000
++#define DPM_TABLE_363__DTEAmbientTempBase__SHIFT 0x18
++#define DPM_TABLE_364__BootVddci_MASK 0xffff
++#define DPM_TABLE_364__BootVddci__SHIFT 0x0
++#define DPM_TABLE_364__BootVddc_MASK 0xffff0000
++#define DPM_TABLE_364__BootVddc__SHIFT 0x10
++#define DPM_TABLE_365__padding_MASK 0xffff
++#define DPM_TABLE_365__padding__SHIFT 0x0
++#define DPM_TABLE_365__BootMVdd_MASK 0xffff0000
++#define DPM_TABLE_365__BootMVdd__SHIFT 0x10
++#define DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK 0xffffffff
++#define DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT 0x0
++#define DPM_TABLE_367__LowSclkInterruptThreshold_MASK 0xffffffff
++#define DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT 0x0
++#define DPM_TABLE_368__VddGfxReChkWait_MASK 0xffffffff
++#define DPM_TABLE_368__VddGfxReChkWait__SHIFT 0x0
++#define DPM_TABLE_369__PPM_TemperatureLimit_MASK 0xffff
++#define DPM_TABLE_369__PPM_TemperatureLimit__SHIFT 0x0
++#define DPM_TABLE_369__PPM_PkgPwrLimit_MASK 0xffff0000
++#define DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT 0x10
++#define DPM_TABLE_370__TargetTdp_MASK 0xffff
++#define DPM_TABLE_370__TargetTdp__SHIFT 0x0
++#define DPM_TABLE_370__DefaultTdp_MASK 0xffff0000
++#define DPM_TABLE_370__DefaultTdp__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_25__UlvEnterCount_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_25__UlvEnterCount__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_26__UlvTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_26__UlvTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
++#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
++#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
++#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
++#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
++#define TDC_STATUS__VDD_Boost_MASK 0xff
++#define TDC_STATUS__VDD_Boost__SHIFT 0x0
++#define TDC_STATUS__VDD_Throttle_MASK 0xff00
++#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
++#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
++#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
++#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
++#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
++#define TDC_MV_AVERAGE__IDD_MASK 0xffff
++#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
++#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
++#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
++#define TDC_VRM_LIMIT__IDD_MASK 0xffff
++#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
++#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
++#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
++#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
++#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
++#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
++#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
++#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
++#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
++#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
++#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
++#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
++#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
++#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20
++#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5
++#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40
++#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6
++#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
++#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
++#define FEATURE_STATUS__BAPM_ON_MASK 0x100
++#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
++#define FEATURE_STATUS__LPMX_ON_MASK 0x200
++#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
++#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
++#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
++#define FEATURE_STATUS__LHTC_ON_MASK 0x800
++#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
++#define FEATURE_STATUS__VPC_ON_MASK 0x1000
++#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
++#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
++#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
++#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
++#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
++#define FEATURE_STATUS__AVS_ON_MASK 0x10000
++#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
++#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
++#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
++#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
++#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
++#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
++#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
++#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
++#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
++#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
++#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
++#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
++#define FEATURE_STATUS__RESERVED__SHIFT 0x16
++#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
++#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
++#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
++#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
++#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
++#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
++#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
++#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
++#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
++#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
++#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
++#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
++#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
++#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
++#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
++#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
++#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
++#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
++#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
++#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
++#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
++#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
++#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
++#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
++#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
++#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
++#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
++#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
++#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
++#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
++#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
++#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
++#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
++#define PM_FUSES_5__VddCVid_3_MASK 0xff
++#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
++#define PM_FUSES_5__VddCVid_2_MASK 0xff00
++#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
++#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
++#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
++#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
++#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
++#define PM_FUSES_6__VddCVid_7_MASK 0xff
++#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
++#define PM_FUSES_6__VddCVid_6_MASK 0xff00
++#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
++#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
++#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
++#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
++#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
++#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
++#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
++#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
++#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
++#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
++#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
++#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
++#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
++#define PM_FUSES_8__TDC_MAWt_MASK 0xff
++#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
++#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
++#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
++#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
++#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
++#define PM_FUSES_9__Reserved_MASK 0xff
++#define PM_FUSES_9__Reserved__SHIFT 0x0
++#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
++#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
++#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
++#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
++#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
++#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
++#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff
++#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0
++#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00
++#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8
++#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000
++#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10
++#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000
++#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18
++#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff
++#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0
++#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00
++#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8
++#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000
++#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10
++#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000
++#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18
++#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff
++#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0
++#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00
++#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8
++#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000
++#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10
++#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000
++#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18
++#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff
++#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0
++#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00
++#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8
++#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000
++#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10
++#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000
++#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18
++#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
++#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
++#define PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
++#define PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT 0x10
++#define PM_FUSES_15__Reserved6_MASK 0xffff
++#define PM_FUSES_15__Reserved6__SHIFT 0x0
++#define PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK 0xffff0000
++#define PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT 0x10
++#define PM_FUSES_16__GnbLPML_3_MASK 0xff
++#define PM_FUSES_16__GnbLPML_3__SHIFT 0x0
++#define PM_FUSES_16__GnbLPML_2_MASK 0xff00
++#define PM_FUSES_16__GnbLPML_2__SHIFT 0x8
++#define PM_FUSES_16__GnbLPML_1_MASK 0xff0000
++#define PM_FUSES_16__GnbLPML_1__SHIFT 0x10
++#define PM_FUSES_16__GnbLPML_0_MASK 0xff000000
++#define PM_FUSES_16__GnbLPML_0__SHIFT 0x18
++#define PM_FUSES_17__GnbLPML_7_MASK 0xff
++#define PM_FUSES_17__GnbLPML_7__SHIFT 0x0
++#define PM_FUSES_17__GnbLPML_6_MASK 0xff00
++#define PM_FUSES_17__GnbLPML_6__SHIFT 0x8
++#define PM_FUSES_17__GnbLPML_5_MASK 0xff0000
++#define PM_FUSES_17__GnbLPML_5__SHIFT 0x10
++#define PM_FUSES_17__GnbLPML_4_MASK 0xff000000
++#define PM_FUSES_17__GnbLPML_4__SHIFT 0x18
++#define PM_FUSES_18__GnbLPML_11_MASK 0xff
++#define PM_FUSES_18__GnbLPML_11__SHIFT 0x0
++#define PM_FUSES_18__GnbLPML_10_MASK 0xff00
++#define PM_FUSES_18__GnbLPML_10__SHIFT 0x8
++#define PM_FUSES_18__GnbLPML_9_MASK 0xff0000
++#define PM_FUSES_18__GnbLPML_9__SHIFT 0x10
++#define PM_FUSES_18__GnbLPML_8_MASK 0xff000000
++#define PM_FUSES_18__GnbLPML_8__SHIFT 0x18
++#define PM_FUSES_19__GnbLPML_15_MASK 0xff
++#define PM_FUSES_19__GnbLPML_15__SHIFT 0x0
++#define PM_FUSES_19__GnbLPML_14_MASK 0xff00
++#define PM_FUSES_19__GnbLPML_14__SHIFT 0x8
++#define PM_FUSES_19__GnbLPML_13_MASK 0xff0000
++#define PM_FUSES_19__GnbLPML_13__SHIFT 0x10
++#define PM_FUSES_19__GnbLPML_12_MASK 0xff000000
++#define PM_FUSES_19__GnbLPML_12__SHIFT 0x18
++#define PM_FUSES_20__Reserved1_1_MASK 0xff
++#define PM_FUSES_20__Reserved1_1__SHIFT 0x0
++#define PM_FUSES_20__Reserved1_0_MASK 0xff00
++#define PM_FUSES_20__Reserved1_0__SHIFT 0x8
++#define PM_FUSES_20__GnbLPMLMinVid_MASK 0xff0000
++#define PM_FUSES_20__GnbLPMLMinVid__SHIFT 0x10
++#define PM_FUSES_20__GnbLPMLMaxVid_MASK 0xff000000
++#define PM_FUSES_20__GnbLPMLMaxVid__SHIFT 0x18
++#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK 0xffff
++#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
++#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
++#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
++#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
++#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
++#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
++#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
++#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
++#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
++#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
++#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
++#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
++#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
++#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
++#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
++#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
++#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
++#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
++#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
++#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
++#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
++#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
++#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
++#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
++#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
++#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
++#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
++#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
++#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
++#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
++#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
++#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
++#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000
++#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
++#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
++#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
++#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
++#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL1__M_MASK 0xff0000
++#define CG_FDO_CTRL1__M__SHIFT 0x10
++#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
++#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
++#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
++#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
++#define CG_FDO_CTRL2__TMIN_MASK 0xff
++#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
++#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
++#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
++#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
++#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
++#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
++#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
++#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
++#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
++#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
++#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
++#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
++#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
++#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
++#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
++#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
++#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
++#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
++#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
++#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
++#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
++#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
++#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
++#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
++#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
++#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
++#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
++#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
++#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
++#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
++#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
++#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
++#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
++#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
++#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
++#define THM_TMON0_INT_DATA__VALID_MASK 0x800
++#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
++#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
++#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
++#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f
++#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0
++#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20
++#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
++#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
++#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
++#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
++#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
++#define GENERAL_PWRMGT__SPARE11_MASK 0x800
++#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
++#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
++#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
++#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
++#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
++#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
++#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
++#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
++#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
++#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
++#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
++#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
++#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
++#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
++#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1
++#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
++#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff
++#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
++#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
++#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
++#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
++#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
++#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
++#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
++#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
++#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
++#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
++#define SCLK_MIN_DIV__FRACV_MASK 0xfff
++#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
++#define SCLK_MIN_DIV__INTV_MASK 0x7f000
++#define SCLK_MIN_DIV__INTV__SHIFT 0xc
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK 0x40000000
++#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
++#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff
++#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
++#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
++#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
++#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
++#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
++#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
++#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
++#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
++#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
++#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
++#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
++#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
++#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
++#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
++#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
++#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
++#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
++#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
++#define ROM_STATUS__ROM_BUSY_MASK 0x1
++#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
++#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
++#define ROM_DATA__ROM_DATA_MASK 0xffffffff
++#define ROM_DATA__ROM_DATA__SHIFT 0x0
++#define ROM_START__ROM_START_MASK 0xffffff
++#define ROM_START__ROM_START__SHIFT 0x0
++#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
++#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
++#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
++#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
++#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
++#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
++#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
++
++#endif /* SMU_7_1_1_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0022-yocto-amd-drm-amdgpu-add-SMU-7-1-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0022-yocto-amd-drm-amdgpu-add-SMU-7-1-0-register-headers.patch
new file mode 100644
index 00000000..b8ab5c56
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0022-yocto-amd-drm-amdgpu-add-SMU-7-1-0-register-headers.patch
@@ -0,0 +1,8385 @@
+From 324fee2509de7979bdd28b109889a4347e54c137 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:31:26 -0400
+Subject: drm/amdgpu: add SMU 7.1.2 register headers
+
+These are register headers for the SMU (System Management Unit)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+new file mode 100644
+index 0000000..9339174
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+@@ -0,0 +1,1273 @@
++/*
++ * SMU_7_1_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_2_D_H
++#define SMU_7_1_2_D_H
++
++#define mmGCK_SMC_IND_INDEX                                                     0x80
++#define mmGCK0_GCK_SMC_IND_INDEX                                                0x80
++#define mmGCK1_GCK_SMC_IND_INDEX                                                0x82
++#define mmGCK2_GCK_SMC_IND_INDEX                                                0x84
++#define mmGCK3_GCK_SMC_IND_INDEX                                                0x86
++#define mmGCK_SMC_IND_DATA                                                      0x81
++#define mmGCK0_GCK_SMC_IND_DATA                                                 0x81
++#define mmGCK1_GCK_SMC_IND_DATA                                                 0x83
++#define mmGCK2_GCK_SMC_IND_DATA                                                 0x85
++#define mmGCK3_GCK_SMC_IND_DATA                                                 0x87
++#define ixCG_DCLK_CNTL                                                          0xc050009c
++#define ixCG_DCLK_STATUS                                                        0xc05000a0
++#define ixCG_VCLK_CNTL                                                          0xc05000a4
++#define ixCG_VCLK_STATUS                                                        0xc05000a8
++#define ixCG_ECLK_CNTL                                                          0xc05000ac
++#define ixCG_ECLK_STATUS                                                        0xc05000b0
++#define ixCG_ACLK_CNTL                                                          0xc05000dc
++#define ixGCK_DFS_BYPASS_CNTL                                                   0xc0500118
++#define ixCG_SPLL_FUNC_CNTL                                                     0xc0500140
++#define ixCG_SPLL_FUNC_CNTL_2                                                   0xc0500144
++#define ixCG_SPLL_FUNC_CNTL_3                                                   0xc0500148
++#define ixCG_SPLL_FUNC_CNTL_4                                                   0xc050014c
++#define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
++#define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
++#define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixSPLL_CNTL_MODE                                                        0xc0500160
++#define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
++#define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
++#define ixMPLL_BYPASSCLK_SEL                                                    0xc050019c
++#define ixCG_CLKPIN_CNTL                                                        0xc05001a0
++#define ixCG_CLKPIN_CNTL_2                                                      0xc05001a4
++#define ixCG_CLKPIN_CNTL_DC                                                     0xc0500204
++#define ixTHM_CLK_CNTL                                                          0xc05001a8
++#define ixMISC_CLK_CTRL                                                         0xc05001ac
++#define ixGCK_PLL_TEST_CNTL                                                     0xc05001c0
++#define ixGCK_PLL_TEST_CNTL_2                                                   0xc05001c4
++#define ixGCK_ADFS_CLK_BYPASS_CNTL1                                             0xc05001c8
++#define mmSMC_IND_INDEX                                                         0x80
++#define mmSMC0_SMC_IND_INDEX                                                    0x80
++#define mmSMC1_SMC_IND_INDEX                                                    0x82
++#define mmSMC2_SMC_IND_INDEX                                                    0x84
++#define mmSMC3_SMC_IND_INDEX                                                    0x86
++#define mmSMC_IND_DATA                                                          0x81
++#define mmSMC0_SMC_IND_DATA                                                     0x81
++#define mmSMC1_SMC_IND_DATA                                                     0x83
++#define mmSMC2_SMC_IND_DATA                                                     0x85
++#define mmSMC3_SMC_IND_DATA                                                     0x87
++#define mmSMC_IND_INDEX_0                                                       0x80
++#define mmSMC_IND_DATA_0                                                        0x81
++#define mmSMC_IND_INDEX_1                                                       0x82
++#define mmSMC_IND_DATA_1                                                        0x83
++#define mmSMC_IND_INDEX_2                                                       0x84
++#define mmSMC_IND_DATA_2                                                        0x85
++#define mmSMC_IND_INDEX_3                                                       0x86
++#define mmSMC_IND_DATA_3                                                        0x87
++#define mmSMC_IND_INDEX_4                                                       0x88
++#define mmSMC_IND_DATA_4                                                        0x89
++#define mmSMC_IND_INDEX_5                                                       0x8a
++#define mmSMC_IND_DATA_5                                                        0x8b
++#define mmSMC_IND_INDEX_6                                                       0x8c
++#define mmSMC_IND_DATA_6                                                        0x8d
++#define mmSMC_IND_INDEX_7                                                       0x8e
++#define mmSMC_IND_DATA_7                                                        0x8f
++#define mmSMC_IND_ACCESS_CNTL                                                   0x92
++#define mmSMC_MESSAGE_0                                                         0x94
++#define mmSMC_RESP_0                                                            0x95
++#define mmSMC_MESSAGE_1                                                         0x96
++#define mmSMC_RESP_1                                                            0x97
++#define mmSMC_MESSAGE_2                                                         0x98
++#define mmSMC_RESP_2                                                            0x99
++#define mmSMC_MESSAGE_3                                                         0x9a
++#define mmSMC_RESP_3                                                            0x9b
++#define mmSMC_MESSAGE_4                                                         0x9c
++#define mmSMC_RESP_4                                                            0x9d
++#define mmSMC_MESSAGE_5                                                         0x9e
++#define mmSMC_RESP_5                                                            0x9f
++#define mmSMC_MESSAGE_6                                                         0xa0
++#define mmSMC_RESP_6                                                            0xa1
++#define mmSMC_MESSAGE_7                                                         0xa2
++#define mmSMC_RESP_7                                                            0xa3
++#define mmSMC_MSG_ARG_0                                                         0xa4
++#define mmSMC_MSG_ARG_1                                                         0xa5
++#define mmSMC_MSG_ARG_2                                                         0xa6
++#define mmSMC_MSG_ARG_3                                                         0xa7
++#define mmSMC_MSG_ARG_4                                                         0xa8
++#define mmSMC_MSG_ARG_5                                                         0xa9
++#define mmSMC_MSG_ARG_6                                                         0xaa
++#define mmSMC_MSG_ARG_7                                                         0xab
++#define mmSMC_MESSAGE_8                                                         0xb5
++#define mmSMC_RESP_8                                                            0xb6
++#define mmSMC_MESSAGE_9                                                         0xb7
++#define mmSMC_RESP_9                                                            0xb8
++#define mmSMC_MESSAGE_10                                                        0xb9
++#define mmSMC_RESP_10                                                           0xba
++#define mmSMC_MESSAGE_11                                                        0xbb
++#define mmSMC_RESP_11                                                           0xbc
++#define mmSMC_MSG_ARG_8                                                         0xbd
++#define mmSMC_MSG_ARG_9                                                         0xbe
++#define mmSMC_MSG_ARG_10                                                        0xbf
++#define mmSMC_MSG_ARG_11                                                        0x93
++#define ixSMC_SYSCON_RESET_CNTL                                                 0x80000000
++#define ixSMC_SYSCON_CLOCK_CNTL_0                                               0x80000004
++#define ixSMC_SYSCON_CLOCK_CNTL_1                                               0x80000008
++#define ixSMC_SYSCON_CLOCK_CNTL_2                                               0x8000000c
++#define ixSMC_SYSCON_MISC_CNTL                                                  0x80000010
++#define ixSMC_SYSCON_MSG_ARG_0                                                  0x80000068
++#define ixSMC_PC_C                                                              0x80000370
++#define ixSMC_SCRATCH9                                                          0x80000424
++#define mmGPIOPAD_SW_INT_STAT                                                   0x180
++#define mmGPIOPAD_STRENGTH                                                      0x181
++#define mmGPIOPAD_MASK                                                          0x182
++#define mmGPIOPAD_A                                                             0x183
++#define mmGPIOPAD_EN                                                            0x184
++#define mmGPIOPAD_Y                                                             0x185
++#define mmGPIOPAD_PINSTRAPS                                                     0x186
++#define mmGPIOPAD_INT_STAT_EN                                                   0x187
++#define mmGPIOPAD_INT_STAT                                                      0x188
++#define mmGPIOPAD_INT_STAT_AK                                                   0x189
++#define mmGPIOPAD_INT_EN                                                        0x18a
++#define mmGPIOPAD_INT_TYPE                                                      0x18b
++#define mmGPIOPAD_INT_POLARITY                                                  0x18c
++#define mmGPIOPAD_EXTERN_TRIG_CNTL                                              0x18d
++#define mmGPIOPAD_RCVR_SEL                                                      0x191
++#define mmGPIOPAD_PU_EN                                                         0x192
++#define mmGPIOPAD_PD_EN                                                         0x193
++#define mmCG_FPS_CNT                                                            0x1b6
++#define mmSMU_IND_INDEX_0                                                       0x1a6
++#define mmSMU_IND_DATA_0                                                        0x1a7
++#define mmSMU_IND_INDEX_1                                                       0x1a8
++#define mmSMU_IND_DATA_1                                                        0x1a9
++#define mmSMU_IND_INDEX_2                                                       0x1aa
++#define mmSMU_IND_DATA_2                                                        0x1ab
++#define mmSMU_IND_INDEX_3                                                       0x1ac
++#define mmSMU_IND_DATA_3                                                        0x1ad
++#define mmSMU_IND_INDEX_4                                                       0x1ae
++#define mmSMU_IND_DATA_4                                                        0x1af
++#define mmSMU_IND_INDEX_5                                                       0x1b0
++#define mmSMU_IND_DATA_5                                                        0x1b1
++#define mmSMU_IND_INDEX_6                                                       0x1b2
++#define mmSMU_IND_DATA_6                                                        0x1b3
++#define mmSMU_IND_INDEX_7                                                       0x1b4
++#define mmSMU_IND_DATA_7                                                        0x1b5
++#define mmSMU_SMC_IND_INDEX                                                     0x80
++#define mmSMU0_SMU_SMC_IND_INDEX                                                0x80
++#define mmSMU1_SMU_SMC_IND_INDEX                                                0x82
++#define mmSMU2_SMU_SMC_IND_INDEX                                                0x84
++#define mmSMU3_SMU_SMC_IND_INDEX                                                0x86
++#define mmSMU_SMC_IND_DATA                                                      0x81
++#define mmSMU0_SMU_SMC_IND_DATA                                                 0x81
++#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83
++#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85
++#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87
++#define ixRCU_UC_EVENTS                                                         0xc0000004
++#define ixRCU_MISC_CTRL                                                         0xc0000010
++#define ixRCU_VIRT_RESET_REQ                                                    0xc0000024
++#define ixCC_RCU_FUSES                                                          0xc00c0000
++#define ixCC_SMU_MISC_FUSES                                                     0xc00c0004
++#define ixCC_SCLK_VID_FUSES                                                     0xc00c0008
++#define ixCC_GIO_IOCCFG_FUSES                                                   0xc00c000c
++#define ixCC_GIO_IOC_FUSES                                                      0xc00c0010
++#define ixCC_SMU_TST_EFUSE1_MISC                                                0xc00c001c
++#define ixCC_TST_ID_STRAPS                                                      0xc00c0020
++#define ixCC_FCTRL_FUSES                                                        0xc00c0024
++#define ixCC_HARVEST_FUSES                                                      0xc00c0028
++#define ixSMU_MAIN_PLL_OP_FREQ                                                  0xe0003020
++#define ixSMU_STATUS                                                            0xe0003088
++#define ixSMU_FIRMWARE                                                          0xe00030a4
++#define ixSMU_INPUT_DATA                                                        0xe00030b8
++#define ixSMU_EFUSE_0                                                           0xc0100000
++#define ixFIRMWARE_FLAGS                                                        0x3f800
++#define ixTDC_STATUS                                                            0x3f804
++#define ixTDC_MV_AVERAGE                                                        0x3f808
++#define ixTDC_VRM_LIMIT                                                         0x3f80c
++#define ixFEATURE_STATUS                                                        0x3f810
++#define ixENTITY_TEMPERATURES_1                                                 0x3f814
++#define ixDPM_TABLE_1                                                           0x3f000
++#define ixDPM_TABLE_2                                                           0x3f004
++#define ixDPM_TABLE_3                                                           0x3f008
++#define ixDPM_TABLE_4                                                           0x3f00c
++#define ixDPM_TABLE_5                                                           0x3f010
++#define ixDPM_TABLE_6                                                           0x3f014
++#define ixDPM_TABLE_7                                                           0x3f018
++#define ixDPM_TABLE_8                                                           0x3f01c
++#define ixDPM_TABLE_9                                                           0x3f020
++#define ixDPM_TABLE_10                                                          0x3f024
++#define ixDPM_TABLE_11                                                          0x3f028
++#define ixDPM_TABLE_12                                                          0x3f02c
++#define ixDPM_TABLE_13                                                          0x3f030
++#define ixDPM_TABLE_14                                                          0x3f034
++#define ixDPM_TABLE_15                                                          0x3f038
++#define ixDPM_TABLE_16                                                          0x3f03c
++#define ixDPM_TABLE_17                                                          0x3f040
++#define ixDPM_TABLE_18                                                          0x3f044
++#define ixDPM_TABLE_19                                                          0x3f048
++#define ixDPM_TABLE_20                                                          0x3f04c
++#define ixDPM_TABLE_21                                                          0x3f050
++#define ixDPM_TABLE_22                                                          0x3f054
++#define ixDPM_TABLE_23                                                          0x3f058
++#define ixDPM_TABLE_24                                                          0x3f05c
++#define ixDPM_TABLE_25                                                          0x3f060
++#define ixDPM_TABLE_26                                                          0x3f064
++#define ixDPM_TABLE_27                                                          0x3f068
++#define ixDPM_TABLE_28                                                          0x3f06c
++#define ixDPM_TABLE_29                                                          0x3f070
++#define ixDPM_TABLE_30                                                          0x3f074
++#define ixDPM_TABLE_31                                                          0x3f078
++#define ixDPM_TABLE_32                                                          0x3f07c
++#define ixDPM_TABLE_33                                                          0x3f080
++#define ixDPM_TABLE_34                                                          0x3f084
++#define ixDPM_TABLE_35                                                          0x3f088
++#define ixDPM_TABLE_36                                                          0x3f08c
++#define ixDPM_TABLE_37                                                          0x3f090
++#define ixDPM_TABLE_38                                                          0x3f094
++#define ixDPM_TABLE_39                                                          0x3f098
++#define ixDPM_TABLE_40                                                          0x3f09c
++#define ixDPM_TABLE_41                                                          0x3f0a0
++#define ixDPM_TABLE_42                                                          0x3f0a4
++#define ixDPM_TABLE_43                                                          0x3f0a8
++#define ixDPM_TABLE_44                                                          0x3f0ac
++#define ixDPM_TABLE_45                                                          0x3f0b0
++#define ixDPM_TABLE_46                                                          0x3f0b4
++#define ixDPM_TABLE_47                                                          0x3f0b8
++#define ixDPM_TABLE_48                                                          0x3f0bc
++#define ixDPM_TABLE_49                                                          0x3f0c0
++#define ixDPM_TABLE_50                                                          0x3f0c4
++#define ixDPM_TABLE_51                                                          0x3f0c8
++#define ixDPM_TABLE_52                                                          0x3f0cc
++#define ixDPM_TABLE_53                                                          0x3f0d0
++#define ixDPM_TABLE_54                                                          0x3f0d4
++#define ixDPM_TABLE_55                                                          0x3f0d8
++#define ixDPM_TABLE_56                                                          0x3f0dc
++#define ixDPM_TABLE_57                                                          0x3f0e0
++#define ixDPM_TABLE_58                                                          0x3f0e4
++#define ixDPM_TABLE_59                                                          0x3f0e8
++#define ixDPM_TABLE_60                                                          0x3f0ec
++#define ixDPM_TABLE_61                                                          0x3f0f0
++#define ixDPM_TABLE_62                                                          0x3f0f4
++#define ixDPM_TABLE_63                                                          0x3f0f8
++#define ixDPM_TABLE_64                                                          0x3f0fc
++#define ixDPM_TABLE_65                                                          0x3f100
++#define ixDPM_TABLE_66                                                          0x3f104
++#define ixDPM_TABLE_67                                                          0x3f108
++#define ixDPM_TABLE_68                                                          0x3f10c
++#define ixDPM_TABLE_69                                                          0x3f110
++#define ixDPM_TABLE_70                                                          0x3f114
++#define ixDPM_TABLE_71                                                          0x3f118
++#define ixDPM_TABLE_72                                                          0x3f11c
++#define ixDPM_TABLE_73                                                          0x3f120
++#define ixDPM_TABLE_74                                                          0x3f124
++#define ixDPM_TABLE_75                                                          0x3f128
++#define ixDPM_TABLE_76                                                          0x3f12c
++#define ixDPM_TABLE_77                                                          0x3f130
++#define ixDPM_TABLE_78                                                          0x3f134
++#define ixDPM_TABLE_79                                                          0x3f138
++#define ixDPM_TABLE_80                                                          0x3f13c
++#define ixDPM_TABLE_81                                                          0x3f140
++#define ixDPM_TABLE_82                                                          0x3f144
++#define ixDPM_TABLE_83                                                          0x3f148
++#define ixDPM_TABLE_84                                                          0x3f14c
++#define ixDPM_TABLE_85                                                          0x3f150
++#define ixDPM_TABLE_86                                                          0x3f154
++#define ixDPM_TABLE_87                                                          0x3f158
++#define ixDPM_TABLE_88                                                          0x3f15c
++#define ixDPM_TABLE_89                                                          0x3f160
++#define ixDPM_TABLE_90                                                          0x3f164
++#define ixDPM_TABLE_91                                                          0x3f168
++#define ixDPM_TABLE_92                                                          0x3f16c
++#define ixDPM_TABLE_93                                                          0x3f170
++#define ixDPM_TABLE_94                                                          0x3f174
++#define ixDPM_TABLE_95                                                          0x3f178
++#define ixDPM_TABLE_96                                                          0x3f17c
++#define ixDPM_TABLE_97                                                          0x3f180
++#define ixDPM_TABLE_98                                                          0x3f184
++#define ixDPM_TABLE_99                                                          0x3f188
++#define ixDPM_TABLE_100                                                         0x3f18c
++#define ixDPM_TABLE_101                                                         0x3f190
++#define ixDPM_TABLE_102                                                         0x3f194
++#define ixDPM_TABLE_103                                                         0x3f198
++#define ixDPM_TABLE_104                                                         0x3f19c
++#define ixDPM_TABLE_105                                                         0x3f1a0
++#define ixDPM_TABLE_106                                                         0x3f1a4
++#define ixDPM_TABLE_107                                                         0x3f1a8
++#define ixDPM_TABLE_108                                                         0x3f1ac
++#define ixDPM_TABLE_109                                                         0x3f1b0
++#define ixDPM_TABLE_110                                                         0x3f1b4
++#define ixDPM_TABLE_111                                                         0x3f1b8
++#define ixDPM_TABLE_112                                                         0x3f1bc
++#define ixDPM_TABLE_113                                                         0x3f1c0
++#define ixDPM_TABLE_114                                                         0x3f1c4
++#define ixDPM_TABLE_115                                                         0x3f1c8
++#define ixDPM_TABLE_116                                                         0x3f1cc
++#define ixDPM_TABLE_117                                                         0x3f1d0
++#define ixDPM_TABLE_118                                                         0x3f1d4
++#define ixDPM_TABLE_119                                                         0x3f1d8
++#define ixDPM_TABLE_120                                                         0x3f1dc
++#define ixDPM_TABLE_121                                                         0x3f1e0
++#define ixDPM_TABLE_122                                                         0x3f1e4
++#define ixDPM_TABLE_123                                                         0x3f1e8
++#define ixDPM_TABLE_124                                                         0x3f1ec
++#define ixDPM_TABLE_125                                                         0x3f1f0
++#define ixDPM_TABLE_126                                                         0x3f1f4
++#define ixDPM_TABLE_127                                                         0x3f1f8
++#define ixDPM_TABLE_128                                                         0x3f1fc
++#define ixDPM_TABLE_129                                                         0x3f200
++#define ixDPM_TABLE_130                                                         0x3f204
++#define ixDPM_TABLE_131                                                         0x3f208
++#define ixDPM_TABLE_132                                                         0x3f20c
++#define ixDPM_TABLE_133                                                         0x3f210
++#define ixDPM_TABLE_134                                                         0x3f214
++#define ixDPM_TABLE_135                                                         0x3f218
++#define ixDPM_TABLE_136                                                         0x3f21c
++#define ixDPM_TABLE_137                                                         0x3f220
++#define ixDPM_TABLE_138                                                         0x3f224
++#define ixDPM_TABLE_139                                                         0x3f228
++#define ixDPM_TABLE_140                                                         0x3f22c
++#define ixDPM_TABLE_141                                                         0x3f230
++#define ixDPM_TABLE_142                                                         0x3f234
++#define ixDPM_TABLE_143                                                         0x3f238
++#define ixDPM_TABLE_144                                                         0x3f23c
++#define ixDPM_TABLE_145                                                         0x3f240
++#define ixDPM_TABLE_146                                                         0x3f244
++#define ixDPM_TABLE_147                                                         0x3f248
++#define ixDPM_TABLE_148                                                         0x3f24c
++#define ixDPM_TABLE_149                                                         0x3f250
++#define ixDPM_TABLE_150                                                         0x3f254
++#define ixDPM_TABLE_151                                                         0x3f258
++#define ixDPM_TABLE_152                                                         0x3f25c
++#define ixDPM_TABLE_153                                                         0x3f260
++#define ixDPM_TABLE_154                                                         0x3f264
++#define ixDPM_TABLE_155                                                         0x3f268
++#define ixDPM_TABLE_156                                                         0x3f26c
++#define ixDPM_TABLE_157                                                         0x3f270
++#define ixDPM_TABLE_158                                                         0x3f274
++#define ixDPM_TABLE_159                                                         0x3f278
++#define ixDPM_TABLE_160                                                         0x3f27c
++#define ixDPM_TABLE_161                                                         0x3f280
++#define ixDPM_TABLE_162                                                         0x3f284
++#define ixDPM_TABLE_163                                                         0x3f288
++#define ixDPM_TABLE_164                                                         0x3f28c
++#define ixDPM_TABLE_165                                                         0x3f290
++#define ixDPM_TABLE_166                                                         0x3f294
++#define ixDPM_TABLE_167                                                         0x3f298
++#define ixDPM_TABLE_168                                                         0x3f29c
++#define ixDPM_TABLE_169                                                         0x3f2a0
++#define ixDPM_TABLE_170                                                         0x3f2a4
++#define ixDPM_TABLE_171                                                         0x3f2a8
++#define ixDPM_TABLE_172                                                         0x3f2ac
++#define ixDPM_TABLE_173                                                         0x3f2b0
++#define ixDPM_TABLE_174                                                         0x3f2b4
++#define ixDPM_TABLE_175                                                         0x3f2b8
++#define ixDPM_TABLE_176                                                         0x3f2bc
++#define ixDPM_TABLE_177                                                         0x3f2c0
++#define ixDPM_TABLE_178                                                         0x3f2c4
++#define ixDPM_TABLE_179                                                         0x3f2c8
++#define ixDPM_TABLE_180                                                         0x3f2cc
++#define ixDPM_TABLE_181                                                         0x3f2d0
++#define ixDPM_TABLE_182                                                         0x3f2d4
++#define ixDPM_TABLE_183                                                         0x3f2d8
++#define ixDPM_TABLE_184                                                         0x3f2dc
++#define ixDPM_TABLE_185                                                         0x3f2e0
++#define ixDPM_TABLE_186                                                         0x3f2e4
++#define ixDPM_TABLE_187                                                         0x3f2e8
++#define ixDPM_TABLE_188                                                         0x3f2ec
++#define ixDPM_TABLE_189                                                         0x3f2f0
++#define ixDPM_TABLE_190                                                         0x3f2f4
++#define ixDPM_TABLE_191                                                         0x3f2f8
++#define ixDPM_TABLE_192                                                         0x3f2fc
++#define ixDPM_TABLE_193                                                         0x3f300
++#define ixDPM_TABLE_194                                                         0x3f304
++#define ixDPM_TABLE_195                                                         0x3f308
++#define ixDPM_TABLE_196                                                         0x3f30c
++#define ixDPM_TABLE_197                                                         0x3f310
++#define ixDPM_TABLE_198                                                         0x3f314
++#define ixDPM_TABLE_199                                                         0x3f318
++#define ixDPM_TABLE_200                                                         0x3f31c
++#define ixDPM_TABLE_201                                                         0x3f320
++#define ixDPM_TABLE_202                                                         0x3f324
++#define ixDPM_TABLE_203                                                         0x3f328
++#define ixDPM_TABLE_204                                                         0x3f32c
++#define ixDPM_TABLE_205                                                         0x3f330
++#define ixDPM_TABLE_206                                                         0x3f334
++#define ixDPM_TABLE_207                                                         0x3f338
++#define ixDPM_TABLE_208                                                         0x3f33c
++#define ixDPM_TABLE_209                                                         0x3f340
++#define ixDPM_TABLE_210                                                         0x3f344
++#define ixDPM_TABLE_211                                                         0x3f348
++#define ixDPM_TABLE_212                                                         0x3f34c
++#define ixDPM_TABLE_213                                                         0x3f350
++#define ixDPM_TABLE_214                                                         0x3f354
++#define ixDPM_TABLE_215                                                         0x3f358
++#define ixDPM_TABLE_216                                                         0x3f35c
++#define ixDPM_TABLE_217                                                         0x3f360
++#define ixDPM_TABLE_218                                                         0x3f364
++#define ixDPM_TABLE_219                                                         0x3f368
++#define ixDPM_TABLE_220                                                         0x3f36c
++#define ixDPM_TABLE_221                                                         0x3f370
++#define ixDPM_TABLE_222                                                         0x3f374
++#define ixDPM_TABLE_223                                                         0x3f378
++#define ixDPM_TABLE_224                                                         0x3f37c
++#define ixDPM_TABLE_225                                                         0x3f380
++#define ixDPM_TABLE_226                                                         0x3f384
++#define ixDPM_TABLE_227                                                         0x3f388
++#define ixDPM_TABLE_228                                                         0x3f38c
++#define ixDPM_TABLE_229                                                         0x3f390
++#define ixDPM_TABLE_230                                                         0x3f394
++#define ixDPM_TABLE_231                                                         0x3f398
++#define ixDPM_TABLE_232                                                         0x3f39c
++#define ixDPM_TABLE_233                                                         0x3f3a0
++#define ixDPM_TABLE_234                                                         0x3f3a4
++#define ixDPM_TABLE_235                                                         0x3f3a8
++#define ixDPM_TABLE_236                                                         0x3f3ac
++#define ixDPM_TABLE_237                                                         0x3f3b0
++#define ixDPM_TABLE_238                                                         0x3f3b4
++#define ixDPM_TABLE_239                                                         0x3f3b8
++#define ixDPM_TABLE_240                                                         0x3f3bc
++#define ixDPM_TABLE_241                                                         0x3f3c0
++#define ixDPM_TABLE_242                                                         0x3f3c4
++#define ixDPM_TABLE_243                                                         0x3f3c8
++#define ixDPM_TABLE_244                                                         0x3f3cc
++#define ixDPM_TABLE_245                                                         0x3f3d0
++#define ixDPM_TABLE_246                                                         0x3f3d4
++#define ixDPM_TABLE_247                                                         0x3f3d8
++#define ixDPM_TABLE_248                                                         0x3f3dc
++#define ixDPM_TABLE_249                                                         0x3f3e0
++#define ixDPM_TABLE_250                                                         0x3f3e4
++#define ixDPM_TABLE_251                                                         0x3f3e8
++#define ixDPM_TABLE_252                                                         0x3f3ec
++#define ixDPM_TABLE_253                                                         0x3f3f0
++#define ixDPM_TABLE_254                                                         0x3f3f4
++#define ixDPM_TABLE_255                                                         0x3f3f8
++#define ixDPM_TABLE_256                                                         0x3f3fc
++#define ixDPM_TABLE_257                                                         0x3f400
++#define ixDPM_TABLE_258                                                         0x3f404
++#define ixDPM_TABLE_259                                                         0x3f408
++#define ixDPM_TABLE_260                                                         0x3f40c
++#define ixDPM_TABLE_261                                                         0x3f410
++#define ixDPM_TABLE_262                                                         0x3f414
++#define ixDPM_TABLE_263                                                         0x3f418
++#define ixDPM_TABLE_264                                                         0x3f41c
++#define ixDPM_TABLE_265                                                         0x3f420
++#define ixDPM_TABLE_266                                                         0x3f424
++#define ixDPM_TABLE_267                                                         0x3f428
++#define ixDPM_TABLE_268                                                         0x3f42c
++#define ixDPM_TABLE_269                                                         0x3f430
++#define ixDPM_TABLE_270                                                         0x3f434
++#define ixDPM_TABLE_271                                                         0x3f438
++#define ixDPM_TABLE_272                                                         0x3f43c
++#define ixDPM_TABLE_273                                                         0x3f440
++#define ixDPM_TABLE_274                                                         0x3f444
++#define ixDPM_TABLE_275                                                         0x3f448
++#define ixDPM_TABLE_276                                                         0x3f44c
++#define ixDPM_TABLE_277                                                         0x3f450
++#define ixDPM_TABLE_278                                                         0x3f454
++#define ixDPM_TABLE_279                                                         0x3f458
++#define ixDPM_TABLE_280                                                         0x3f45c
++#define ixDPM_TABLE_281                                                         0x3f460
++#define ixDPM_TABLE_282                                                         0x3f464
++#define ixDPM_TABLE_283                                                         0x3f468
++#define ixDPM_TABLE_284                                                         0x3f46c
++#define ixDPM_TABLE_285                                                         0x3f470
++#define ixDPM_TABLE_286                                                         0x3f474
++#define ixDPM_TABLE_287                                                         0x3f478
++#define ixDPM_TABLE_288                                                         0x3f47c
++#define ixDPM_TABLE_289                                                         0x3f480
++#define ixDPM_TABLE_290                                                         0x3f484
++#define ixDPM_TABLE_291                                                         0x3f488
++#define ixDPM_TABLE_292                                                         0x3f48c
++#define ixDPM_TABLE_293                                                         0x3f490
++#define ixDPM_TABLE_294                                                         0x3f494
++#define ixDPM_TABLE_295                                                         0x3f498
++#define ixDPM_TABLE_296                                                         0x3f49c
++#define ixDPM_TABLE_297                                                         0x3f4a0
++#define ixDPM_TABLE_298                                                         0x3f4a4
++#define ixDPM_TABLE_299                                                         0x3f4a8
++#define ixDPM_TABLE_300                                                         0x3f4ac
++#define ixDPM_TABLE_301                                                         0x3f4b0
++#define ixDPM_TABLE_302                                                         0x3f4b4
++#define ixDPM_TABLE_303                                                         0x3f4b8
++#define ixDPM_TABLE_304                                                         0x3f4bc
++#define ixDPM_TABLE_305                                                         0x3f4c0
++#define ixDPM_TABLE_306                                                         0x3f4c4
++#define ixDPM_TABLE_307                                                         0x3f4c8
++#define ixDPM_TABLE_308                                                         0x3f4cc
++#define ixDPM_TABLE_309                                                         0x3f4d0
++#define ixDPM_TABLE_310                                                         0x3f4d4
++#define ixDPM_TABLE_311                                                         0x3f4d8
++#define ixDPM_TABLE_312                                                         0x3f4dc
++#define ixDPM_TABLE_313                                                         0x3f4e0
++#define ixDPM_TABLE_314                                                         0x3f4e4
++#define ixDPM_TABLE_315                                                         0x3f4e8
++#define ixDPM_TABLE_316                                                         0x3f4ec
++#define ixDPM_TABLE_317                                                         0x3f4f0
++#define ixDPM_TABLE_318                                                         0x3f4f4
++#define ixDPM_TABLE_319                                                         0x3f4f8
++#define ixDPM_TABLE_320                                                         0x3f4fc
++#define ixDPM_TABLE_321                                                         0x3f500
++#define ixDPM_TABLE_322                                                         0x3f504
++#define ixDPM_TABLE_323                                                         0x3f508
++#define ixDPM_TABLE_324                                                         0x3f50c
++#define ixDPM_TABLE_325                                                         0x3f510
++#define ixDPM_TABLE_326                                                         0x3f514
++#define ixDPM_TABLE_327                                                         0x3f518
++#define ixDPM_TABLE_328                                                         0x3f51c
++#define ixDPM_TABLE_329                                                         0x3f520
++#define ixDPM_TABLE_330                                                         0x3f524
++#define ixDPM_TABLE_331                                                         0x3f528
++#define ixDPM_TABLE_332                                                         0x3f52c
++#define ixDPM_TABLE_333                                                         0x3f530
++#define ixDPM_TABLE_334                                                         0x3f534
++#define ixDPM_TABLE_335                                                         0x3f538
++#define ixDPM_TABLE_336                                                         0x3f53c
++#define ixDPM_TABLE_337                                                         0x3f540
++#define ixDPM_TABLE_338                                                         0x3f544
++#define ixDPM_TABLE_339                                                         0x3f548
++#define ixDPM_TABLE_340                                                         0x3f54c
++#define ixDPM_TABLE_341                                                         0x3f550
++#define ixDPM_TABLE_342                                                         0x3f554
++#define ixDPM_TABLE_343                                                         0x3f558
++#define ixDPM_TABLE_344                                                         0x3f55c
++#define ixDPM_TABLE_345                                                         0x3f560
++#define ixDPM_TABLE_346                                                         0x3f564
++#define ixDPM_TABLE_347                                                         0x3f568
++#define ixDPM_TABLE_348                                                         0x3f56c
++#define ixDPM_TABLE_349                                                         0x3f570
++#define ixDPM_TABLE_350                                                         0x3f574
++#define ixDPM_TABLE_351                                                         0x3f578
++#define ixDPM_TABLE_352                                                         0x3f57c
++#define ixDPM_TABLE_353                                                         0x3f580
++#define ixDPM_TABLE_354                                                         0x3f584
++#define ixDPM_TABLE_355                                                         0x3f588
++#define ixDPM_TABLE_356                                                         0x3f58c
++#define ixDPM_TABLE_357                                                         0x3f590
++#define ixDPM_TABLE_358                                                         0x3f594
++#define ixDPM_TABLE_359                                                         0x3f598
++#define ixDPM_TABLE_360                                                         0x3f59c
++#define ixDPM_TABLE_361                                                         0x3f5a0
++#define ixDPM_TABLE_362                                                         0x3f5a4
++#define ixDPM_TABLE_363                                                         0x3f5a8
++#define ixDPM_TABLE_364                                                         0x3f5ac
++#define ixDPM_TABLE_365                                                         0x3f5b0
++#define ixDPM_TABLE_366                                                         0x3f5b4
++#define ixDPM_TABLE_367                                                         0x3f5b8
++#define ixDPM_TABLE_368                                                         0x3f5bc
++#define ixDPM_TABLE_369                                                         0x3f5c0
++#define ixDPM_TABLE_370                                                         0x3f5c4
++#define ixDPM_TABLE_371                                                         0x3f5c8
++#define ixDPM_TABLE_372                                                         0x3f5cc
++#define ixDPM_TABLE_373                                                         0x3f5d0
++#define ixDPM_TABLE_374                                                         0x3f5d4
++#define ixDPM_TABLE_375                                                         0x3f5d8
++#define ixDPM_TABLE_376                                                         0x3f5dc
++#define ixDPM_TABLE_377                                                         0x3f5e0
++#define ixDPM_TABLE_378                                                         0x3f5e4
++#define ixDPM_TABLE_379                                                         0x3f5e8
++#define ixDPM_TABLE_380                                                         0x3f5ec
++#define ixDPM_TABLE_381                                                         0x3f5f0
++#define ixDPM_TABLE_382                                                         0x3f5f4
++#define ixDPM_TABLE_383                                                         0x3f5f8
++#define ixDPM_TABLE_384                                                         0x3f5fc
++#define ixDPM_TABLE_385                                                         0x3f600
++#define ixDPM_TABLE_386                                                         0x3f604
++#define ixDPM_TABLE_387                                                         0x3f608
++#define ixDPM_TABLE_388                                                         0x3f60c
++#define ixDPM_TABLE_389                                                         0x3f610
++#define ixDPM_TABLE_390                                                         0x3f614
++#define ixDPM_TABLE_391                                                         0x3f618
++#define ixDPM_TABLE_392                                                         0x3f61c
++#define ixDPM_TABLE_393                                                         0x3f620
++#define ixDPM_TABLE_394                                                         0x3f624
++#define ixDPM_TABLE_395                                                         0x3f628
++#define ixDPM_TABLE_396                                                         0x3f62c
++#define ixDPM_TABLE_397                                                         0x3f630
++#define ixDPM_TABLE_398                                                         0x3f634
++#define ixDPM_TABLE_399                                                         0x3f638
++#define ixDPM_TABLE_400                                                         0x3f63c
++#define ixDPM_TABLE_401                                                         0x3f640
++#define ixDPM_TABLE_402                                                         0x3f644
++#define ixDPM_TABLE_403                                                         0x3f648
++#define ixDPM_TABLE_404                                                         0x3f64c
++#define ixDPM_TABLE_405                                                         0x3f650
++#define ixDPM_TABLE_406                                                         0x3f654
++#define ixDPM_TABLE_407                                                         0x3f658
++#define ixDPM_TABLE_408                                                         0x3f65c
++#define ixDPM_TABLE_409                                                         0x3f660
++#define ixDPM_TABLE_410                                                         0x3f664
++#define ixDPM_TABLE_411                                                         0x3f668
++#define ixDPM_TABLE_412                                                         0x3f66c
++#define ixDPM_TABLE_413                                                         0x3f670
++#define ixDPM_TABLE_414                                                         0x3f674
++#define ixDPM_TABLE_415                                                         0x3f678
++#define ixDPM_TABLE_416                                                         0x3f67c
++#define ixDPM_TABLE_417                                                         0x3f680
++#define ixDPM_TABLE_418                                                         0x3f684
++#define ixDPM_TABLE_419                                                         0x3f688
++#define ixDPM_TABLE_420                                                         0x3f68c
++#define ixDPM_TABLE_421                                                         0x3f690
++#define ixDPM_TABLE_422                                                         0x3f694
++#define ixDPM_TABLE_423                                                         0x3f698
++#define ixDPM_TABLE_424                                                         0x3f69c
++#define ixDPM_TABLE_425                                                         0x3f6a0
++#define ixDPM_TABLE_426                                                         0x3f6a4
++#define ixDPM_TABLE_427                                                         0x3f6a8
++#define ixDPM_TABLE_428                                                         0x3f6ac
++#define ixDPM_TABLE_429                                                         0x3f6b0
++#define ixDPM_TABLE_430                                                         0x3f6b4
++#define ixDPM_TABLE_431                                                         0x3f6b8
++#define ixDPM_TABLE_432                                                         0x3f6bc
++#define ixDPM_TABLE_433                                                         0x3f6c0
++#define ixDPM_TABLE_434                                                         0x3f6c4
++#define ixDPM_TABLE_435                                                         0x3f6c8
++#define ixDPM_TABLE_436                                                         0x3f6cc
++#define ixDPM_TABLE_437                                                         0x3f6d0
++#define ixDPM_TABLE_438                                                         0x3f6d4
++#define ixDPM_TABLE_439                                                         0x3f6d8
++#define ixDPM_TABLE_440                                                         0x3f6dc
++#define ixDPM_TABLE_441                                                         0x3f6e0
++#define ixDPM_TABLE_442                                                         0x3f6e4
++#define ixDPM_TABLE_443                                                         0x3f6e8
++#define ixDPM_TABLE_444                                                         0x3f6ec
++#define ixDPM_TABLE_445                                                         0x3f6f0
++#define ixDPM_TABLE_446                                                         0x3f6f4
++#define ixDPM_TABLE_447                                                         0x3f6f8
++#define ixDPM_TABLE_448                                                         0x3f6fc
++#define ixDPM_TABLE_449                                                         0x3f700
++#define ixDPM_TABLE_450                                                         0x3f704
++#define ixDPM_TABLE_451                                                         0x3f708
++#define ixDPM_TABLE_452                                                         0x3f70c
++#define ixDPM_TABLE_453                                                         0x3f710
++#define ixDPM_TABLE_454                                                         0x3f714
++#define ixDPM_TABLE_455                                                         0x3f718
++#define ixDPM_TABLE_456                                                         0x3f71c
++#define ixDPM_TABLE_457                                                         0x3f720
++#define ixDPM_TABLE_458                                                         0x3f724
++#define ixDPM_TABLE_459                                                         0x3f728
++#define ixDPM_TABLE_460                                                         0x3f72c
++#define ixDPM_TABLE_461                                                         0x3f730
++#define ixDPM_TABLE_462                                                         0x3f734
++#define ixDPM_TABLE_463                                                         0x3f738
++#define ixDPM_TABLE_464                                                         0x3f73c
++#define ixDPM_TABLE_465                                                         0x3f740
++#define ixDPM_TABLE_466                                                         0x3f744
++#define ixDPM_TABLE_467                                                         0x3f748
++#define ixDPM_TABLE_468                                                         0x3f74c
++#define ixDPM_TABLE_469                                                         0x3f750
++#define ixDPM_TABLE_470                                                         0x3f754
++#define ixDPM_TABLE_471                                                         0x3f758
++#define ixDPM_TABLE_472                                                         0x3f75c
++#define ixDPM_TABLE_473                                                         0x3f760
++#define ixDPM_TABLE_474                                                         0x3f764
++#define ixDPM_TABLE_475                                                         0x3f768
++#define ixDPM_TABLE_476                                                         0x3f76c
++#define ixDPM_TABLE_477                                                         0x3f770
++#define ixDPM_TABLE_478                                                         0x3f774
++#define ixDPM_TABLE_479                                                         0x3f778
++#define ixDPM_TABLE_480                                                         0x3f77c
++#define ixDPM_TABLE_481                                                         0x3f780
++#define ixDPM_TABLE_482                                                         0x3f784
++#define ixDPM_TABLE_483                                                         0x3f788
++#define ixDPM_TABLE_484                                                         0x3f78c
++#define ixDPM_TABLE_485                                                         0x3f790
++#define ixDPM_TABLE_486                                                         0x3f794
++#define ixDPM_TABLE_487                                                         0x3f798
++#define ixDPM_TABLE_488                                                         0x3f79c
++#define ixDPM_TABLE_489                                                         0x3f7a0
++#define ixDPM_TABLE_490                                                         0x3f7a4
++#define ixMCARB_DRAM_TIMING_TABLE_1                                             0x3f900
++#define ixMCARB_DRAM_TIMING_TABLE_2                                             0x3f904
++#define ixMCARB_DRAM_TIMING_TABLE_3                                             0x3f908
++#define ixMCARB_DRAM_TIMING_TABLE_4                                             0x3f90c
++#define ixMCARB_DRAM_TIMING_TABLE_5                                             0x3f910
++#define ixMCARB_DRAM_TIMING_TABLE_6                                             0x3f914
++#define ixMCARB_DRAM_TIMING_TABLE_7                                             0x3f918
++#define ixMCARB_DRAM_TIMING_TABLE_8                                             0x3f91c
++#define ixMCARB_DRAM_TIMING_TABLE_9                                             0x3f920
++#define ixMCARB_DRAM_TIMING_TABLE_10                                            0x3f924
++#define ixMCARB_DRAM_TIMING_TABLE_11                                            0x3f928
++#define ixMCARB_DRAM_TIMING_TABLE_12                                            0x3f92c
++#define ixMCARB_DRAM_TIMING_TABLE_13                                            0x3f930
++#define ixMCARB_DRAM_TIMING_TABLE_14                                            0x3f934
++#define ixMCARB_DRAM_TIMING_TABLE_15                                            0x3f938
++#define ixMCARB_DRAM_TIMING_TABLE_16                                            0x3f93c
++#define ixMCARB_DRAM_TIMING_TABLE_17                                            0x3f940
++#define ixMCARB_DRAM_TIMING_TABLE_18                                            0x3f944
++#define ixMCARB_DRAM_TIMING_TABLE_19                                            0x3f948
++#define ixMCARB_DRAM_TIMING_TABLE_20                                            0x3f94c
++#define ixMCARB_DRAM_TIMING_TABLE_21                                            0x3f950
++#define ixMCARB_DRAM_TIMING_TABLE_22                                            0x3f954
++#define ixMCARB_DRAM_TIMING_TABLE_23                                            0x3f958
++#define ixMCARB_DRAM_TIMING_TABLE_24                                            0x3f95c
++#define ixMCARB_DRAM_TIMING_TABLE_25                                            0x3f960
++#define ixMCARB_DRAM_TIMING_TABLE_26                                            0x3f964
++#define ixMCARB_DRAM_TIMING_TABLE_27                                            0x3f968
++#define ixMCARB_DRAM_TIMING_TABLE_28                                            0x3f96c
++#define ixMCARB_DRAM_TIMING_TABLE_29                                            0x3f970
++#define ixMCARB_DRAM_TIMING_TABLE_30                                            0x3f974
++#define ixMCARB_DRAM_TIMING_TABLE_31                                            0x3f978
++#define ixMCARB_DRAM_TIMING_TABLE_32                                            0x3f97c
++#define ixMCARB_DRAM_TIMING_TABLE_33                                            0x3f980
++#define ixMCARB_DRAM_TIMING_TABLE_34                                            0x3f984
++#define ixMCARB_DRAM_TIMING_TABLE_35                                            0x3f988
++#define ixMCARB_DRAM_TIMING_TABLE_36                                            0x3f98c
++#define ixMCARB_DRAM_TIMING_TABLE_37                                            0x3f990
++#define ixMCARB_DRAM_TIMING_TABLE_38                                            0x3f994
++#define ixMCARB_DRAM_TIMING_TABLE_39                                            0x3f998
++#define ixMCARB_DRAM_TIMING_TABLE_40                                            0x3f99c
++#define ixMCARB_DRAM_TIMING_TABLE_41                                            0x3f9a0
++#define ixMCARB_DRAM_TIMING_TABLE_42                                            0x3f9a4
++#define ixMCARB_DRAM_TIMING_TABLE_43                                            0x3f9a8
++#define ixMCARB_DRAM_TIMING_TABLE_44                                            0x3f9ac
++#define ixMCARB_DRAM_TIMING_TABLE_45                                            0x3f9b0
++#define ixMCARB_DRAM_TIMING_TABLE_46                                            0x3f9b4
++#define ixMCARB_DRAM_TIMING_TABLE_47                                            0x3f9b8
++#define ixMCARB_DRAM_TIMING_TABLE_48                                            0x3f9bc
++#define ixMCARB_DRAM_TIMING_TABLE_49                                            0x3f9c0
++#define ixMCARB_DRAM_TIMING_TABLE_50                                            0x3f9c4
++#define ixMCARB_DRAM_TIMING_TABLE_51                                            0x3f9c8
++#define ixMCARB_DRAM_TIMING_TABLE_52                                            0x3f9cc
++#define ixMCARB_DRAM_TIMING_TABLE_53                                            0x3f9d0
++#define ixMCARB_DRAM_TIMING_TABLE_54                                            0x3f9d4
++#define ixMCARB_DRAM_TIMING_TABLE_55                                            0x3f9d8
++#define ixMCARB_DRAM_TIMING_TABLE_56                                            0x3f9dc
++#define ixMCARB_DRAM_TIMING_TABLE_57                                            0x3f9e0
++#define ixMCARB_DRAM_TIMING_TABLE_58                                            0x3f9e4
++#define ixMCARB_DRAM_TIMING_TABLE_59                                            0x3f9e8
++#define ixMCARB_DRAM_TIMING_TABLE_60                                            0x3f9ec
++#define ixMCARB_DRAM_TIMING_TABLE_61                                            0x3f9f0
++#define ixMCARB_DRAM_TIMING_TABLE_62                                            0x3f9f4
++#define ixMCARB_DRAM_TIMING_TABLE_63                                            0x3f9f8
++#define ixMCARB_DRAM_TIMING_TABLE_64                                            0x3f9fc
++#define ixMCARB_DRAM_TIMING_TABLE_65                                            0x3fa00
++#define ixMCARB_DRAM_TIMING_TABLE_66                                            0x3fa04
++#define ixMCARB_DRAM_TIMING_TABLE_67                                            0x3fa08
++#define ixMCARB_DRAM_TIMING_TABLE_68                                            0x3fa0c
++#define ixMCARB_DRAM_TIMING_TABLE_69                                            0x3fa10
++#define ixMCARB_DRAM_TIMING_TABLE_70                                            0x3fa14
++#define ixMCARB_DRAM_TIMING_TABLE_71                                            0x3fa18
++#define ixMCARB_DRAM_TIMING_TABLE_72                                            0x3fa1c
++#define ixMCARB_DRAM_TIMING_TABLE_73                                            0x3fa20
++#define ixMCARB_DRAM_TIMING_TABLE_74                                            0x3fa24
++#define ixMCARB_DRAM_TIMING_TABLE_75                                            0x3fa28
++#define ixMCARB_DRAM_TIMING_TABLE_76                                            0x3fa2c
++#define ixMCARB_DRAM_TIMING_TABLE_77                                            0x3fa30
++#define ixMCARB_DRAM_TIMING_TABLE_78                                            0x3fa34
++#define ixMCARB_DRAM_TIMING_TABLE_79                                            0x3fa38
++#define ixMCARB_DRAM_TIMING_TABLE_80                                            0x3fa3c
++#define ixMCARB_DRAM_TIMING_TABLE_81                                            0x3fa40
++#define ixMCARB_DRAM_TIMING_TABLE_82                                            0x3fa44
++#define ixMCARB_DRAM_TIMING_TABLE_83                                            0x3fa48
++#define ixMCARB_DRAM_TIMING_TABLE_84                                            0x3fa4c
++#define ixMCARB_DRAM_TIMING_TABLE_85                                            0x3fa50
++#define ixMCARB_DRAM_TIMING_TABLE_86                                            0x3fa54
++#define ixMCARB_DRAM_TIMING_TABLE_87                                            0x3fa58
++#define ixMCARB_DRAM_TIMING_TABLE_88                                            0x3fa5c
++#define ixMCARB_DRAM_TIMING_TABLE_89                                            0x3fa60
++#define ixMCARB_DRAM_TIMING_TABLE_90                                            0x3fa64
++#define ixMCARB_DRAM_TIMING_TABLE_91                                            0x3fa68
++#define ixMCARB_DRAM_TIMING_TABLE_92                                            0x3fa6c
++#define ixMCARB_DRAM_TIMING_TABLE_93                                            0x3fa70
++#define ixMCARB_DRAM_TIMING_TABLE_94                                            0x3fa74
++#define ixMCARB_DRAM_TIMING_TABLE_95                                            0x3fa78
++#define ixMCARB_DRAM_TIMING_TABLE_96                                            0x3fa7c
++#define ixMC_REGISTERS_TABLE_1                                                  0x3fa80
++#define ixMC_REGISTERS_TABLE_2                                                  0x3fa84
++#define ixMC_REGISTERS_TABLE_3                                                  0x3fa88
++#define ixMC_REGISTERS_TABLE_4                                                  0x3fa8c
++#define ixMC_REGISTERS_TABLE_5                                                  0x3fa90
++#define ixMC_REGISTERS_TABLE_6                                                  0x3fa94
++#define ixMC_REGISTERS_TABLE_7                                                  0x3fa98
++#define ixMC_REGISTERS_TABLE_8                                                  0x3fa9c
++#define ixMC_REGISTERS_TABLE_9                                                  0x3faa0
++#define ixMC_REGISTERS_TABLE_10                                                 0x3faa4
++#define ixMC_REGISTERS_TABLE_11                                                 0x3faa8
++#define ixMC_REGISTERS_TABLE_12                                                 0x3faac
++#define ixMC_REGISTERS_TABLE_13                                                 0x3fab0
++#define ixMC_REGISTERS_TABLE_14                                                 0x3fab4
++#define ixMC_REGISTERS_TABLE_15                                                 0x3fab8
++#define ixMC_REGISTERS_TABLE_16                                                 0x3fabc
++#define ixMC_REGISTERS_TABLE_17                                                 0x3fac0
++#define ixMC_REGISTERS_TABLE_18                                                 0x3fac4
++#define ixMC_REGISTERS_TABLE_19                                                 0x3fac8
++#define ixMC_REGISTERS_TABLE_20                                                 0x3facc
++#define ixMC_REGISTERS_TABLE_21                                                 0x3fad0
++#define ixMC_REGISTERS_TABLE_22                                                 0x3fad4
++#define ixMC_REGISTERS_TABLE_23                                                 0x3fad8
++#define ixMC_REGISTERS_TABLE_24                                                 0x3fadc
++#define ixMC_REGISTERS_TABLE_25                                                 0x3fae0
++#define ixMC_REGISTERS_TABLE_26                                                 0x3fae4
++#define ixMC_REGISTERS_TABLE_27                                                 0x3fae8
++#define ixMC_REGISTERS_TABLE_28                                                 0x3faec
++#define ixMC_REGISTERS_TABLE_29                                                 0x3faf0
++#define ixMC_REGISTERS_TABLE_30                                                 0x3faf4
++#define ixMC_REGISTERS_TABLE_31                                                 0x3faf8
++#define ixMC_REGISTERS_TABLE_32                                                 0x3fafc
++#define ixMC_REGISTERS_TABLE_33                                                 0x3fb00
++#define ixMC_REGISTERS_TABLE_34                                                 0x3fb04
++#define ixMC_REGISTERS_TABLE_35                                                 0x3fb08
++#define ixMC_REGISTERS_TABLE_36                                                 0x3fb0c
++#define ixMC_REGISTERS_TABLE_37                                                 0x3fb10
++#define ixMC_REGISTERS_TABLE_38                                                 0x3fb14
++#define ixMC_REGISTERS_TABLE_39                                                 0x3fb18
++#define ixMC_REGISTERS_TABLE_40                                                 0x3fb1c
++#define ixMC_REGISTERS_TABLE_41                                                 0x3fb20
++#define ixMC_REGISTERS_TABLE_42                                                 0x3fb24
++#define ixMC_REGISTERS_TABLE_43                                                 0x3fb28
++#define ixMC_REGISTERS_TABLE_44                                                 0x3fb2c
++#define ixMC_REGISTERS_TABLE_45                                                 0x3fb30
++#define ixMC_REGISTERS_TABLE_46                                                 0x3fb34
++#define ixMC_REGISTERS_TABLE_47                                                 0x3fb38
++#define ixMC_REGISTERS_TABLE_48                                                 0x3fb3c
++#define ixMC_REGISTERS_TABLE_49                                                 0x3fb40
++#define ixMC_REGISTERS_TABLE_50                                                 0x3fb44
++#define ixMC_REGISTERS_TABLE_51                                                 0x3fb48
++#define ixMC_REGISTERS_TABLE_52                                                 0x3fb4c
++#define ixMC_REGISTERS_TABLE_53                                                 0x3fb50
++#define ixMC_REGISTERS_TABLE_54                                                 0x3fb54
++#define ixMC_REGISTERS_TABLE_55                                                 0x3fb58
++#define ixMC_REGISTERS_TABLE_56                                                 0x3fb5c
++#define ixMC_REGISTERS_TABLE_57                                                 0x3fb60
++#define ixMC_REGISTERS_TABLE_58                                                 0x3fb64
++#define ixMC_REGISTERS_TABLE_59                                                 0x3fb68
++#define ixMC_REGISTERS_TABLE_60                                                 0x3fb6c
++#define ixMC_REGISTERS_TABLE_61                                                 0x3fb70
++#define ixMC_REGISTERS_TABLE_62                                                 0x3fb74
++#define ixMC_REGISTERS_TABLE_63                                                 0x3fb78
++#define ixMC_REGISTERS_TABLE_64                                                 0x3fb7c
++#define ixMC_REGISTERS_TABLE_65                                                 0x3fb80
++#define ixMC_REGISTERS_TABLE_66                                                 0x3fb84
++#define ixMC_REGISTERS_TABLE_67                                                 0x3fb88
++#define ixMC_REGISTERS_TABLE_68                                                 0x3fb8c
++#define ixMC_REGISTERS_TABLE_69                                                 0x3fb90
++#define ixMC_REGISTERS_TABLE_70                                                 0x3fb94
++#define ixMC_REGISTERS_TABLE_71                                                 0x3fb98
++#define ixMC_REGISTERS_TABLE_72                                                 0x3fb9c
++#define ixMC_REGISTERS_TABLE_73                                                 0x3fba0
++#define ixMC_REGISTERS_TABLE_74                                                 0x3fba4
++#define ixMC_REGISTERS_TABLE_75                                                 0x3fba8
++#define ixMC_REGISTERS_TABLE_76                                                 0x3fbac
++#define ixMC_REGISTERS_TABLE_77                                                 0x3fbb0
++#define ixMC_REGISTERS_TABLE_78                                                 0x3fbb4
++#define ixMC_REGISTERS_TABLE_79                                                 0x3fbb8
++#define ixMC_REGISTERS_TABLE_80                                                 0x3fbbc
++#define ixMC_REGISTERS_TABLE_81                                                 0x3fbc0
++#define ixFAN_TABLE_1                                                           0x3fbc4
++#define ixFAN_TABLE_2                                                           0x3fbc8
++#define ixFAN_TABLE_3                                                           0x3fbcc
++#define ixFAN_TABLE_4                                                           0x3fbd0
++#define ixFAN_TABLE_5                                                           0x3fbd4
++#define ixFAN_TABLE_6                                                           0x3fbd8
++#define ixFAN_TABLE_7                                                           0x3fbdc
++#define ixFAN_TABLE_8                                                           0x3fbe0
++#define ixFAN_TABLE_9                                                           0x3fbe4
++#define ixSOFT_REGISTERS_TABLE_1                                                0x3fbe8
++#define ixSOFT_REGISTERS_TABLE_2                                                0x3fbec
++#define ixSOFT_REGISTERS_TABLE_3                                                0x3fbf0
++#define ixSOFT_REGISTERS_TABLE_4                                                0x3fbf4
++#define ixSOFT_REGISTERS_TABLE_5                                                0x3fbf8
++#define ixSOFT_REGISTERS_TABLE_6                                                0x3fbfc
++#define ixSOFT_REGISTERS_TABLE_7                                                0x3fc00
++#define ixSOFT_REGISTERS_TABLE_8                                                0x3fc04
++#define ixSOFT_REGISTERS_TABLE_9                                                0x3fc08
++#define ixSOFT_REGISTERS_TABLE_10                                               0x3fc0c
++#define ixSOFT_REGISTERS_TABLE_11                                               0x3fc10
++#define ixSOFT_REGISTERS_TABLE_12                                               0x3fc14
++#define ixSOFT_REGISTERS_TABLE_13                                               0x3fc18
++#define ixSOFT_REGISTERS_TABLE_14                                               0x3fc1c
++#define ixSOFT_REGISTERS_TABLE_15                                               0x3fc20
++#define ixSOFT_REGISTERS_TABLE_16                                               0x3fc24
++#define ixSOFT_REGISTERS_TABLE_17                                               0x3fc28
++#define ixSOFT_REGISTERS_TABLE_18                                               0x3fc2c
++#define ixSOFT_REGISTERS_TABLE_19                                               0x3fc30
++#define ixSOFT_REGISTERS_TABLE_20                                               0x3fc34
++#define ixSOFT_REGISTERS_TABLE_21                                               0x3fc38
++#define ixSOFT_REGISTERS_TABLE_22                                               0x3fc3c
++#define ixSOFT_REGISTERS_TABLE_23                                               0x3fc40
++#define ixSOFT_REGISTERS_TABLE_24                                               0x3fc44
++#define ixSOFT_REGISTERS_TABLE_25                                               0x3fc48
++#define ixSOFT_REGISTERS_TABLE_26                                               0x3fc4c
++#define ixSOFT_REGISTERS_TABLE_27                                               0x3fc50
++#define ixSOFT_REGISTERS_TABLE_28                                               0x3fc54
++#define ixSOFT_REGISTERS_TABLE_29                                               0x3fc58
++#define ixSOFT_REGISTERS_TABLE_30                                               0x3fc5c
++#define ixPM_FUSES_1                                                            0x3fc60
++#define ixPM_FUSES_2                                                            0x3fc64
++#define ixPM_FUSES_3                                                            0x3fc68
++#define ixPM_FUSES_4                                                            0x3fc6c
++#define ixPM_FUSES_5                                                            0x3fc70
++#define ixPM_FUSES_6                                                            0x3fc74
++#define ixPM_FUSES_7                                                            0x3fc78
++#define ixPM_FUSES_8                                                            0x3fc7c
++#define ixPM_FUSES_9                                                            0x3fc80
++#define ixPM_FUSES_10                                                           0x3fc84
++#define ixPM_FUSES_11                                                           0x3fc88
++#define ixPM_FUSES_12                                                           0x3fc8c
++#define ixPM_FUSES_13                                                           0x3fc90
++#define ixPM_FUSES_14                                                           0x3fc94
++#define ixPM_FUSES_15                                                           0x3fc98
++#define ixSMU_PM_STATUS_0                                                       0x3fe00
++#define ixSMU_PM_STATUS_1                                                       0x3fe04
++#define ixSMU_PM_STATUS_2                                                       0x3fe08
++#define ixSMU_PM_STATUS_3                                                       0x3fe0c
++#define ixSMU_PM_STATUS_4                                                       0x3fe10
++#define ixSMU_PM_STATUS_5                                                       0x3fe14
++#define ixSMU_PM_STATUS_6                                                       0x3fe18
++#define ixSMU_PM_STATUS_7                                                       0x3fe1c
++#define ixSMU_PM_STATUS_8                                                       0x3fe20
++#define ixSMU_PM_STATUS_9                                                       0x3fe24
++#define ixSMU_PM_STATUS_10                                                      0x3fe28
++#define ixSMU_PM_STATUS_11                                                      0x3fe2c
++#define ixSMU_PM_STATUS_12                                                      0x3fe30
++#define ixSMU_PM_STATUS_13                                                      0x3fe34
++#define ixSMU_PM_STATUS_14                                                      0x3fe38
++#define ixSMU_PM_STATUS_15                                                      0x3fe3c
++#define ixSMU_PM_STATUS_16                                                      0x3fe40
++#define ixSMU_PM_STATUS_17                                                      0x3fe44
++#define ixSMU_PM_STATUS_18                                                      0x3fe48
++#define ixSMU_PM_STATUS_19                                                      0x3fe4c
++#define ixSMU_PM_STATUS_20                                                      0x3fe50
++#define ixSMU_PM_STATUS_21                                                      0x3fe54
++#define ixSMU_PM_STATUS_22                                                      0x3fe58
++#define ixSMU_PM_STATUS_23                                                      0x3fe5c
++#define ixSMU_PM_STATUS_24                                                      0x3fe60
++#define ixSMU_PM_STATUS_25                                                      0x3fe64
++#define ixSMU_PM_STATUS_26                                                      0x3fe68
++#define ixSMU_PM_STATUS_27                                                      0x3fe6c
++#define ixSMU_PM_STATUS_28                                                      0x3fe70
++#define ixSMU_PM_STATUS_29                                                      0x3fe74
++#define ixSMU_PM_STATUS_30                                                      0x3fe78
++#define ixSMU_PM_STATUS_31                                                      0x3fe7c
++#define ixSMU_PM_STATUS_32                                                      0x3fe80
++#define ixSMU_PM_STATUS_33                                                      0x3fe84
++#define ixSMU_PM_STATUS_34                                                      0x3fe88
++#define ixSMU_PM_STATUS_35                                                      0x3fe8c
++#define ixSMU_PM_STATUS_36                                                      0x3fe90
++#define ixSMU_PM_STATUS_37                                                      0x3fe94
++#define ixSMU_PM_STATUS_38                                                      0x3fe98
++#define ixSMU_PM_STATUS_39                                                      0x3fe9c
++#define ixSMU_PM_STATUS_40                                                      0x3fea0
++#define ixSMU_PM_STATUS_41                                                      0x3fea4
++#define ixSMU_PM_STATUS_42                                                      0x3fea8
++#define ixSMU_PM_STATUS_43                                                      0x3feac
++#define ixSMU_PM_STATUS_44                                                      0x3feb0
++#define ixSMU_PM_STATUS_45                                                      0x3feb4
++#define ixSMU_PM_STATUS_46                                                      0x3feb8
++#define ixSMU_PM_STATUS_47                                                      0x3febc
++#define ixSMU_PM_STATUS_48                                                      0x3fec0
++#define ixSMU_PM_STATUS_49                                                      0x3fec4
++#define ixSMU_PM_STATUS_50                                                      0x3fec8
++#define ixSMU_PM_STATUS_51                                                      0x3fecc
++#define ixSMU_PM_STATUS_52                                                      0x3fed0
++#define ixSMU_PM_STATUS_53                                                      0x3fed4
++#define ixSMU_PM_STATUS_54                                                      0x3fed8
++#define ixSMU_PM_STATUS_55                                                      0x3fedc
++#define ixSMU_PM_STATUS_56                                                      0x3fee0
++#define ixSMU_PM_STATUS_57                                                      0x3fee4
++#define ixSMU_PM_STATUS_58                                                      0x3fee8
++#define ixSMU_PM_STATUS_59                                                      0x3feec
++#define ixSMU_PM_STATUS_60                                                      0x3fef0
++#define ixSMU_PM_STATUS_61                                                      0x3fef4
++#define ixSMU_PM_STATUS_62                                                      0x3fef8
++#define ixSMU_PM_STATUS_63                                                      0x3fefc
++#define ixSMU_PM_STATUS_64                                                      0x3ff00
++#define ixSMU_PM_STATUS_65                                                      0x3ff04
++#define ixSMU_PM_STATUS_66                                                      0x3ff08
++#define ixSMU_PM_STATUS_67                                                      0x3ff0c
++#define ixSMU_PM_STATUS_68                                                      0x3ff10
++#define ixSMU_PM_STATUS_69                                                      0x3ff14
++#define ixSMU_PM_STATUS_70                                                      0x3ff18
++#define ixSMU_PM_STATUS_71                                                      0x3ff1c
++#define ixSMU_PM_STATUS_72                                                      0x3ff20
++#define ixSMU_PM_STATUS_73                                                      0x3ff24
++#define ixSMU_PM_STATUS_74                                                      0x3ff28
++#define ixSMU_PM_STATUS_75                                                      0x3ff2c
++#define ixSMU_PM_STATUS_76                                                      0x3ff30
++#define ixSMU_PM_STATUS_77                                                      0x3ff34
++#define ixSMU_PM_STATUS_78                                                      0x3ff38
++#define ixSMU_PM_STATUS_79                                                      0x3ff3c
++#define ixSMU_PM_STATUS_80                                                      0x3ff40
++#define ixSMU_PM_STATUS_81                                                      0x3ff44
++#define ixSMU_PM_STATUS_82                                                      0x3ff48
++#define ixSMU_PM_STATUS_83                                                      0x3ff4c
++#define ixSMU_PM_STATUS_84                                                      0x3ff50
++#define ixSMU_PM_STATUS_85                                                      0x3ff54
++#define ixSMU_PM_STATUS_86                                                      0x3ff58
++#define ixSMU_PM_STATUS_87                                                      0x3ff5c
++#define ixSMU_PM_STATUS_88                                                      0x3ff60
++#define ixSMU_PM_STATUS_89                                                      0x3ff64
++#define ixSMU_PM_STATUS_90                                                      0x3ff68
++#define ixSMU_PM_STATUS_91                                                      0x3ff6c
++#define ixSMU_PM_STATUS_92                                                      0x3ff70
++#define ixSMU_PM_STATUS_93                                                      0x3ff74
++#define ixSMU_PM_STATUS_94                                                      0x3ff78
++#define ixSMU_PM_STATUS_95                                                      0x3ff7c
++#define ixSMU_PM_STATUS_96                                                      0x3ff80
++#define ixSMU_PM_STATUS_97                                                      0x3ff84
++#define ixSMU_PM_STATUS_98                                                      0x3ff88
++#define ixSMU_PM_STATUS_99                                                      0x3ff8c
++#define ixSMU_PM_STATUS_100                                                     0x3ff90
++#define ixSMU_PM_STATUS_101                                                     0x3ff94
++#define ixSMU_PM_STATUS_102                                                     0x3ff98
++#define ixSMU_PM_STATUS_103                                                     0x3ff9c
++#define ixSMU_PM_STATUS_104                                                     0x3ffa0
++#define ixSMU_PM_STATUS_105                                                     0x3ffa4
++#define ixSMU_PM_STATUS_106                                                     0x3ffa8
++#define ixSMU_PM_STATUS_107                                                     0x3ffac
++#define ixSMU_PM_STATUS_108                                                     0x3ffb0
++#define ixSMU_PM_STATUS_109                                                     0x3ffb4
++#define ixSMU_PM_STATUS_110                                                     0x3ffb8
++#define ixSMU_PM_STATUS_111                                                     0x3ffbc
++#define ixSMU_PM_STATUS_112                                                     0x3ffc0
++#define ixSMU_PM_STATUS_113                                                     0x3ffc4
++#define ixSMU_PM_STATUS_114                                                     0x3ffc8
++#define ixSMU_PM_STATUS_115                                                     0x3ffcc
++#define ixSMU_PM_STATUS_116                                                     0x3ffd0
++#define ixSMU_PM_STATUS_117                                                     0x3ffd4
++#define ixSMU_PM_STATUS_118                                                     0x3ffd8
++#define ixSMU_PM_STATUS_119                                                     0x3ffdc
++#define ixSMU_PM_STATUS_120                                                     0x3ffe0
++#define ixSMU_PM_STATUS_121                                                     0x3ffe4
++#define ixSMU_PM_STATUS_122                                                     0x3ffe8
++#define ixSMU_PM_STATUS_123                                                     0x3ffec
++#define ixSMU_PM_STATUS_124                                                     0x3fff0
++#define ixSMU_PM_STATUS_125                                                     0x3fff4
++#define ixSMU_PM_STATUS_126                                                     0x3fff8
++#define ixSMU_PM_STATUS_127                                                     0x3fffc
++#define ixCG_THERMAL_INT_ENA                                                    0xc2100024
++#define ixCG_THERMAL_INT_CTRL                                                   0xc2100028
++#define ixCG_THERMAL_INT_STATUS                                                 0xc210002c
++#define ixCG_THERMAL_CTRL                                                       0xc0300004
++#define ixCG_THERMAL_STATUS                                                     0xc0300008
++#define ixCG_THERMAL_INT                                                        0xc030000c
++#define ixCG_MULT_THERMAL_CTRL                                                  0xc0300010
++#define ixCG_MULT_THERMAL_STATUS                                                0xc0300014
++#define ixCG_FDO_CTRL0                                                          0xc0300064
++#define ixCG_FDO_CTRL1                                                          0xc0300068
++#define ixCG_FDO_CTRL2                                                          0xc030006c
++#define ixCG_TACH_CTRL                                                          0xc0300070
++#define ixCG_TACH_STATUS                                                        0xc0300074
++#define ixCC_THM_STRAPS0                                                        0xc0300080
++#define ixTHM_TMON0_RDIL0_DATA                                                  0xc0300100
++#define ixTHM_TMON0_RDIL1_DATA                                                  0xc0300104
++#define ixTHM_TMON0_RDIL2_DATA                                                  0xc0300108
++#define ixTHM_TMON0_RDIL3_DATA                                                  0xc030010c
++#define ixTHM_TMON0_RDIL4_DATA                                                  0xc0300110
++#define ixTHM_TMON0_RDIL5_DATA                                                  0xc0300114
++#define ixTHM_TMON0_RDIL6_DATA                                                  0xc0300118
++#define ixTHM_TMON0_RDIL7_DATA                                                  0xc030011c
++#define ixTHM_TMON0_RDIL8_DATA                                                  0xc0300120
++#define ixTHM_TMON0_RDIL9_DATA                                                  0xc0300124
++#define ixTHM_TMON0_RDIL10_DATA                                                 0xc0300128
++#define ixTHM_TMON0_RDIL11_DATA                                                 0xc030012c
++#define ixTHM_TMON0_RDIL12_DATA                                                 0xc0300130
++#define ixTHM_TMON0_RDIL13_DATA                                                 0xc0300134
++#define ixTHM_TMON0_RDIL14_DATA                                                 0xc0300138
++#define ixTHM_TMON0_RDIL15_DATA                                                 0xc030013c
++#define ixTHM_TMON0_RDIR0_DATA                                                  0xc0300140
++#define ixTHM_TMON0_RDIR1_DATA                                                  0xc0300144
++#define ixTHM_TMON0_RDIR2_DATA                                                  0xc0300148
++#define ixTHM_TMON0_RDIR3_DATA                                                  0xc030014c
++#define ixTHM_TMON0_RDIR4_DATA                                                  0xc0300150
++#define ixTHM_TMON0_RDIR5_DATA                                                  0xc0300154
++#define ixTHM_TMON0_RDIR6_DATA                                                  0xc0300158
++#define ixTHM_TMON0_RDIR7_DATA                                                  0xc030015c
++#define ixTHM_TMON0_RDIR8_DATA                                                  0xc0300160
++#define ixTHM_TMON0_RDIR9_DATA                                                  0xc0300164
++#define ixTHM_TMON0_RDIR10_DATA                                                 0xc0300168
++#define ixTHM_TMON0_RDIR11_DATA                                                 0xc030016c
++#define ixTHM_TMON0_RDIR12_DATA                                                 0xc0300170
++#define ixTHM_TMON0_RDIR13_DATA                                                 0xc0300174
++#define ixTHM_TMON0_RDIR14_DATA                                                 0xc0300178
++#define ixTHM_TMON0_RDIR15_DATA                                                 0xc030017c
++#define ixTHM_TMON1_RDIL0_DATA                                                  0xc0300180
++#define ixTHM_TMON1_RDIL1_DATA                                                  0xc0300184
++#define ixTHM_TMON1_RDIL2_DATA                                                  0xc0300188
++#define ixTHM_TMON1_RDIL3_DATA                                                  0xc030018c
++#define ixTHM_TMON1_RDIL4_DATA                                                  0xc0300190
++#define ixTHM_TMON1_RDIL5_DATA                                                  0xc0300194
++#define ixTHM_TMON1_RDIL6_DATA                                                  0xc0300198
++#define ixTHM_TMON1_RDIL7_DATA                                                  0xc030019c
++#define ixTHM_TMON1_RDIL8_DATA                                                  0xc03001a0
++#define ixTHM_TMON1_RDIL9_DATA                                                  0xc03001a4
++#define ixTHM_TMON1_RDIL10_DATA                                                 0xc03001a8
++#define ixTHM_TMON1_RDIL11_DATA                                                 0xc03001ac
++#define ixTHM_TMON1_RDIL12_DATA                                                 0xc03001b0
++#define ixTHM_TMON1_RDIL13_DATA                                                 0xc03001b4
++#define ixTHM_TMON1_RDIL14_DATA                                                 0xc03001b8
++#define ixTHM_TMON1_RDIL15_DATA                                                 0xc03001bc
++#define ixTHM_TMON1_RDIR0_DATA                                                  0xc03001c0
++#define ixTHM_TMON1_RDIR1_DATA                                                  0xc03001c4
++#define ixTHM_TMON1_RDIR2_DATA                                                  0xc03001c8
++#define ixTHM_TMON1_RDIR3_DATA                                                  0xc03001cc
++#define ixTHM_TMON1_RDIR4_DATA                                                  0xc03001d0
++#define ixTHM_TMON1_RDIR5_DATA                                                  0xc03001d4
++#define ixTHM_TMON1_RDIR6_DATA                                                  0xc03001d8
++#define ixTHM_TMON1_RDIR7_DATA                                                  0xc03001dc
++#define ixTHM_TMON1_RDIR8_DATA                                                  0xc03001e0
++#define ixTHM_TMON1_RDIR9_DATA                                                  0xc03001e4
++#define ixTHM_TMON1_RDIR10_DATA                                                 0xc03001e8
++#define ixTHM_TMON1_RDIR11_DATA                                                 0xc03001ec
++#define ixTHM_TMON1_RDIR12_DATA                                                 0xc03001f0
++#define ixTHM_TMON1_RDIR13_DATA                                                 0xc03001f4
++#define ixTHM_TMON1_RDIR14_DATA                                                 0xc03001f8
++#define ixTHM_TMON1_RDIR15_DATA                                                 0xc03001fc
++#define ixTHM_TMON0_INT_DATA                                                    0xc0300300
++#define ixTHM_TMON1_INT_DATA                                                    0xc0300304
++#define ixTHM_TMON0_DEBUG                                                       0xc0300310
++#define ixTHM_TMON1_DEBUG                                                       0xc0300314
++#define ixTHM_TMON0_STATUS                                                      0xc0300320
++#define ixTHM_TMON1_STATUS                                                      0xc0300324
++#define ixGENERAL_PWRMGT                                                        0xc0200000
++#define ixCNB_PWRMGT_CNTL                                                       0xc0200004
++#define ixSCLK_PWRMGT_CNTL                                                      0xc0200008
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xc0200014
++#define ixPWR_PCC_CONTROL                                                       0xc0200018
++#define ixPWR_PCC_GPIO_SELECT                                                   0xc020001c
++#define ixCG_FREQ_TRAN_VOTING_0                                                 0xc02001a8
++#define ixCG_FREQ_TRAN_VOTING_1                                                 0xc02001ac
++#define ixCG_FREQ_TRAN_VOTING_2                                                 0xc02001b0
++#define ixCG_FREQ_TRAN_VOTING_3                                                 0xc02001b4
++#define ixCG_FREQ_TRAN_VOTING_4                                                 0xc02001b8
++#define ixCG_FREQ_TRAN_VOTING_5                                                 0xc02001bc
++#define ixCG_FREQ_TRAN_VOTING_6                                                 0xc02001c0
++#define ixCG_FREQ_TRAN_VOTING_7                                                 0xc02001c4
++#define ixPLL_TEST_CNTL                                                         0xc020003c
++#define ixCG_STATIC_SCREEN_PARAMETER                                            0xc0200044
++#define ixCG_DISPLAY_GAP_CNTL                                                   0xc0200060
++#define ixCG_DISPLAY_GAP_CNTL2                                                  0xc0200230
++#define ixCG_ACPI_CNTL                                                          0xc0200064
++#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xc0200080
++#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xc0200084
++#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xc020009c
++#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xc0200088
++#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xc020008c
++#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xc0200310
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xc02000f0
++#define ixCG_ULV_PARAMETER                                                      0xc020015c
++#define ixSCLK_MIN_DIV                                                          0xc02003ac
++#define ixPWR_CKS_ENABLE                                                        0xc020034c
++#define ixPWR_CKS_CNTL                                                          0xc0200350
++#define ixPWR_DISP_TIMER_CONTROL                                                0xc02003c0
++#define ixPWR_DISP_TIMER_DEBUG                                                  0xc02003c4
++#define ixPWR_DISP_TIMER2_CONTROL                                               0xc02003c8
++#define ixPWR_DISP_TIMER2_DEBUG                                                 0xc02003cc
++#define ixPWR_DISP_TIMER_CONTROL2                                               0xc0200378
++#define ixVDDGFX_IDLE_PARAMETER                                                 0xc020036c
++#define ixVDDGFX_IDLE_CONTROL                                                   0xc0200370
++#define ixVDDGFX_IDLE_EXIT                                                      0xc0200374
++#define ixLCAC_MC0_CNTL                                                         0xc0400130
++#define ixLCAC_MC0_OVR_SEL                                                      0xc0400134
++#define ixLCAC_MC0_OVR_VAL                                                      0xc0400138
++#define ixLCAC_MC1_CNTL                                                         0xc040013c
++#define ixLCAC_MC1_OVR_SEL                                                      0xc0400140
++#define ixLCAC_MC1_OVR_VAL                                                      0xc0400144
++#define ixLCAC_MC2_CNTL                                                         0xc0400148
++#define ixLCAC_MC2_OVR_SEL                                                      0xc040014c
++#define ixLCAC_MC2_OVR_VAL                                                      0xc0400150
++#define ixLCAC_MC3_CNTL                                                         0xc0400154
++#define ixLCAC_MC3_OVR_SEL                                                      0xc0400158
++#define ixLCAC_MC3_OVR_VAL                                                      0xc040015c
++#define ixLCAC_CPL_CNTL                                                         0xc0400160
++#define ixLCAC_CPL_OVR_SEL                                                      0xc0400164
++#define ixLCAC_CPL_OVR_VAL                                                      0xc0400168
++#define mmROM_SMC_IND_INDEX                                                     0x80
++#define mmROM0_ROM_SMC_IND_INDEX                                                0x80
++#define mmROM1_ROM_SMC_IND_INDEX                                                0x82
++#define mmROM2_ROM_SMC_IND_INDEX                                                0x84
++#define mmROM3_ROM_SMC_IND_INDEX                                                0x86
++#define mmROM_SMC_IND_DATA                                                      0x81
++#define mmROM0_ROM_SMC_IND_DATA                                                 0x81
++#define mmROM1_ROM_SMC_IND_DATA                                                 0x83
++#define mmROM2_ROM_SMC_IND_DATA                                                 0x85
++#define mmROM3_ROM_SMC_IND_DATA                                                 0x87
++#define ixROM_CNTL                                                              0xc0600000
++#define ixPAGE_MIRROR_CNTL                                                      0xc0600004
++#define ixROM_STATUS                                                            0xc0600008
++#define ixCGTT_ROM_CLK_CTRL0                                                    0xc060000c
++#define ixROM_INDEX                                                             0xc0600010
++#define ixROM_DATA                                                              0xc0600014
++#define ixROM_START                                                             0xc0600018
++#define ixROM_SW_CNTL                                                           0xc060001c
++#define ixROM_SW_STATUS                                                         0xc0600020
++#define ixROM_SW_COMMAND                                                        0xc0600024
++#define ixROM_SW_DATA_1                                                         0xc0600028
++#define ixROM_SW_DATA_2                                                         0xc060002c
++#define ixROM_SW_DATA_3                                                         0xc0600030
++#define ixROM_SW_DATA_4                                                         0xc0600034
++#define ixROM_SW_DATA_5                                                         0xc0600038
++#define ixROM_SW_DATA_6                                                         0xc060003c
++#define ixROM_SW_DATA_7                                                         0xc0600040
++#define ixROM_SW_DATA_8                                                         0xc0600044
++#define ixROM_SW_DATA_9                                                         0xc0600048
++#define ixROM_SW_DATA_10                                                        0xc060004c
++#define ixROM_SW_DATA_11                                                        0xc0600050
++#define ixROM_SW_DATA_12                                                        0xc0600054
++#define ixROM_SW_DATA_13                                                        0xc0600058
++#define ixROM_SW_DATA_14                                                        0xc060005c
++#define ixROM_SW_DATA_15                                                        0xc0600060
++#define ixROM_SW_DATA_16                                                        0xc0600064
++#define ixROM_SW_DATA_17                                                        0xc0600068
++#define ixROM_SW_DATA_18                                                        0xc060006c
++#define ixROM_SW_DATA_19                                                        0xc0600070
++#define ixROM_SW_DATA_20                                                        0xc0600074
++#define ixROM_SW_DATA_21                                                        0xc0600078
++#define ixROM_SW_DATA_22                                                        0xc060007c
++#define ixROM_SW_DATA_23                                                        0xc0600080
++#define ixROM_SW_DATA_24                                                        0xc0600084
++#define ixROM_SW_DATA_25                                                        0xc0600088
++#define ixROM_SW_DATA_26                                                        0xc060008c
++#define ixROM_SW_DATA_27                                                        0xc0600090
++#define ixROM_SW_DATA_28                                                        0xc0600094
++#define ixROM_SW_DATA_29                                                        0xc0600098
++#define ixROM_SW_DATA_30                                                        0xc060009c
++#define ixROM_SW_DATA_31                                                        0xc06000a0
++#define ixROM_SW_DATA_32                                                        0xc06000a4
++#define ixROM_SW_DATA_33                                                        0xc06000a8
++#define ixROM_SW_DATA_34                                                        0xc06000ac
++#define ixROM_SW_DATA_35                                                        0xc06000b0
++#define ixROM_SW_DATA_36                                                        0xc06000b4
++#define ixROM_SW_DATA_37                                                        0xc06000b8
++#define ixROM_SW_DATA_38                                                        0xc06000bc
++#define ixROM_SW_DATA_39                                                        0xc06000c0
++#define ixROM_SW_DATA_40                                                        0xc06000c4
++#define ixROM_SW_DATA_41                                                        0xc06000c8
++#define ixROM_SW_DATA_42                                                        0xc06000cc
++#define ixROM_SW_DATA_43                                                        0xc06000d0
++#define ixROM_SW_DATA_44                                                        0xc06000d4
++#define ixROM_SW_DATA_45                                                        0xc06000d8
++#define ixROM_SW_DATA_46                                                        0xc06000dc
++#define ixROM_SW_DATA_47                                                        0xc06000e0
++#define ixROM_SW_DATA_48                                                        0xc06000e4
++#define ixROM_SW_DATA_49                                                        0xc06000e8
++#define ixROM_SW_DATA_50                                                        0xc06000ec
++#define ixROM_SW_DATA_51                                                        0xc06000f0
++#define ixROM_SW_DATA_52                                                        0xc06000f4
++#define ixROM_SW_DATA_53                                                        0xc06000f8
++#define ixROM_SW_DATA_54                                                        0xc06000fc
++#define ixROM_SW_DATA_55                                                        0xc0600100
++#define ixROM_SW_DATA_56                                                        0xc0600104
++#define ixROM_SW_DATA_57                                                        0xc0600108
++#define ixROM_SW_DATA_58                                                        0xc060010c
++#define ixROM_SW_DATA_59                                                        0xc0600110
++#define ixROM_SW_DATA_60                                                        0xc0600114
++#define ixROM_SW_DATA_61                                                        0xc0600118
++#define ixROM_SW_DATA_62                                                        0xc060011c
++#define ixROM_SW_DATA_63                                                        0xc0600120
++#define ixROM_SW_DATA_64                                                        0xc0600124
++
++#endif /* SMU_7_1_2_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
+new file mode 100644
+index 0000000..73bbf50
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
+@@ -0,0 +1,1246 @@
++/*
++ * SMU_7_1_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_2_ENUM_H
++#define SMU_7_1_2_ENUM_H
++
++#define CG_SRBM_START_ADDR                        0x600
++#define CG_SRBM_END_ADDR                          0x8ff
++#define RCU_CCF_DWORDS0                           0xa0
++#define RCU_CCF_BITS0                             0x1400
++#define RCU_CCF_DWORDS1                           0x0
++#define RCU_CCF_BITS1                             0x0
++#define RCU_SAM_BYTES                             0x2c
++#define RCU_SAM_RTL_BYTES                         0x2c
++#define RCU_SMU_BYTES                             0x14
++#define RCU_SMU_RTL_BYTES                         0x14
++#define SFP_CHAIN_ADDR                            0x0
++#define SFP_BYTES                                 0x140
++#define SFP_SADR                                  0xc0
++#define SFP_EADR                                  0x1ff
++#define SAMU_KEY_CHAIN_ADR                        0x0
++#define SAMU_KEY_SADR                             0x2a0
++#define SAMU_KEY_EADR                             0x2cb
++#define SMU_KEY_CHAIN_ADR                         0x0
++#define SMU_KEY_SADR                              0x2cc
++#define SMU_KEY_EADR                              0x2df
++#define SMC_MSG_TEST                              0x1
++#define SMC_MSG_PHY_LN_OFF                        0x2
++#define SMC_MSG_PHY_LN_ON                         0x3
++#define SMC_MSG_DDI_PHY_OFF                       0x4
++#define SMC_MSG_DDI_PHY_ON                        0x5
++#define SMC_MSG_CASCADE_PLL_OFF                   0x6
++#define SMC_MSG_CASCADE_PLL_ON                    0x7
++#define SMC_MSG_PWR_OFF_x16                       0x8
++#define SMC_MSG_CONFIG_LCLK_DPM                   0x9
++#define SMC_MSG_FLUSH_DATA_CACHE                  0xa
++#define SMC_MSG_FLUSH_INSTRUCTION_CACHE           0xb
++#define SMC_MSG_CONFIG_VPC_ACCUMULATOR            0xc
++#define SMC_MSG_CONFIG_BAPM                       0xd
++#define SMC_MSG_CONFIG_TDC_LIMIT                  0xe
++#define SMC_MSG_CONFIG_LPMx                       0xf
++#define SMC_MSG_CONFIG_HTC_LIMIT                  0x10
++#define SMC_MSG_CONFIG_THERMAL_CNTL               0x11
++#define SMC_MSG_CONFIG_VOLTAGE_CNTL               0x12
++#define SMC_MSG_CONFIG_TDP_CNTL                   0x13
++#define SMC_MSG_EN_PM_CNTL                        0x14
++#define SMC_MSG_DIS_PM_CNTL                       0x15
++#define SMC_MSG_CONFIG_NBDPM                      0x16
++#define SMC_MSG_CONFIG_LOADLINE                   0x17
++#define SMC_MSG_ADJUST_LOADLINE                   0x18
++#define SMC_MSG_RESET                             0x20
++#define SMC_MSG_VOLTAGE                           0x25
++#define SMC_VERSION_MAJOR                         0x7
++#define SMC_VERSION_MINOR                         0x0
++#define SMC_HEADER_SIZE                           0x40
++#define ROM_SIGNATURE                             0xaa55
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_bci0                            = 0xc,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xd,
++	DBG_CLIENT_BLKID_cb100                           = 0xe,
++	DBG_CLIENT_BLKID_cb001                           = 0xf,
++	DBG_CLIENT_BLKID_mcd4                            = 0x10,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x11,
++	DBG_CLIENT_BLKID_cb101                           = 0x12,
++	DBG_CLIENT_BLKID_sx10                            = 0x13,
++	DBG_CLIENT_BLKID_cb301                           = 0x14,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x15,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x16,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x19,
++	DBG_CLIENT_BLKID_scf1                            = 0x1a,
++	DBG_CLIENT_BLKID_sx20                            = 0x1b,
++	DBG_CLIENT_BLKID_spim1                           = 0x1c,
++	DBG_CLIENT_BLKID_pa10                            = 0x1d,
++	DBG_CLIENT_BLKID_pa00                            = 0x1e,
++	DBG_CLIENT_BLKID_gmcon                           = 0x1f,
++	DBG_CLIENT_BLKID_mcb                             = 0x20,
++	DBG_CLIENT_BLKID_vgt0                            = 0x21,
++	DBG_CLIENT_BLKID_pc0                             = 0x22,
++	DBG_CLIENT_BLKID_bci2                            = 0x23,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x24,
++	DBG_CLIENT_BLKID_spim3                           = 0x25,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x26,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x27,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x28,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x29,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2b,
++	DBG_CLIENT_BLKID_cb000                           = 0x2c,
++	DBG_CLIENT_BLKID_spim0                           = 0x2d,
++	DBG_CLIENT_BLKID_mcc2                            = 0x2e,
++	DBG_CLIENT_BLKID_ds0                             = 0x2f,
++	DBG_CLIENT_BLKID_srbm                            = 0x30,
++	DBG_CLIENT_BLKID_ih                              = 0x31,
++	DBG_CLIENT_BLKID_sem                             = 0x32,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x33,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x34,
++	DBG_CLIENT_BLKID_hdp                             = 0x35,
++	DBG_CLIENT_BLKID_acp_0                           = 0x36,
++	DBG_CLIENT_BLKID_acp_1                           = 0x37,
++	DBG_CLIENT_BLKID_cb200                           = 0x38,
++	DBG_CLIENT_BLKID_scf3                            = 0x39,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3a,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3b,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x3e,
++	DBG_CLIENT_BLKID_bci3                            = 0x3f,
++	DBG_CLIENT_BLKID_mcd0                            = 0x40,
++	DBG_CLIENT_BLKID_pa11                            = 0x41,
++	DBG_CLIENT_BLKID_pa01                            = 0x42,
++	DBG_CLIENT_BLKID_cb201                           = 0x43,
++	DBG_CLIENT_BLKID_spim2                           = 0x44,
++	DBG_CLIENT_BLKID_vgt2                            = 0x45,
++	DBG_CLIENT_BLKID_pc2                             = 0x46,
++	DBG_CLIENT_BLKID_smu_0                           = 0x47,
++	DBG_CLIENT_BLKID_smu_1                           = 0x48,
++	DBG_CLIENT_BLKID_smu_2                           = 0x49,
++	DBG_CLIENT_BLKID_cb1                             = 0x4a,
++	DBG_CLIENT_BLKID_ia0                             = 0x4b,
++	DBG_CLIENT_BLKID_wd                              = 0x4c,
++	DBG_CLIENT_BLKID_ia1                             = 0x4d,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x4e,
++	DBG_CLIENT_BLKID_scf0                            = 0x4f,
++	DBG_CLIENT_BLKID_vgt1                            = 0x50,
++	DBG_CLIENT_BLKID_pc1                             = 0x51,
++	DBG_CLIENT_BLKID_cb0                             = 0x52,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x53,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x76,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x77,
++	DBG_CLIENT_BLKID_vgt3                            = 0x78,
++	DBG_CLIENT_BLKID_pc3                             = 0x79,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7a,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7b,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x81,
++	DBG_CLIENT_BLKID_cb300                           = 0x82,
++	DBG_CLIENT_BLKID_mcd1                            = 0x83,
++	DBG_CLIENT_BLKID_sx00                            = 0x84,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x85,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x86,
++	DBG_CLIENT_BLKID_mcc3                            = 0x87,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x88,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x89,
++	DBG_CLIENT_BLKID_gck                             = 0x8a,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8b,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8c,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8d,
++	DBG_CLIENT_BLKID_rlc                             = 0x8e,
++	DBG_CLIENT_BLKID_grbm                            = 0x8f,
++	DBG_CLIENT_BLKID_sammsp                          = 0x90,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x91,
++	DBG_CLIENT_BLKID_dci_0                           = 0x92,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x93,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x94,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x95,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x96,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9a,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9b,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* SMU_7_1_2_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+new file mode 100644
+index 0000000..518fd02
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+@@ -0,0 +1,5834 @@
++/*
++ * SMU_7_1_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_7_1_2_SH_MASK_H
++#define SMU_7_1_2_SH_MASK_H
++
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
++#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
++#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
++#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
++#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
++#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
++#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
++#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
++#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
++#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
++#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
++#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
++#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
++#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
++#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
++#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
++#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
++#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
++#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
++#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
++#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
++#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
++#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
++#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
++#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
++#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
++#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
++#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
++#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
++#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
++#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
++#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
++#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
++#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
++#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
++#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
++#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
++#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
++#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
++#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
++#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
++#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
++#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
++#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
++#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
++#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
++#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
++#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
++#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
++#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
++#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
++#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
++#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
++#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
++#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
++#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
++#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
++#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
++#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
++#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
++#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
++#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
++#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
++#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
++#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
++#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
++#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
++#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
++#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
++#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
++#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
++#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
++#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
++#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
++#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
++#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
++#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
++#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
++#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
++#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
++#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
++#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
++#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
++#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
++#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
++#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
++#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
++#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
++#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
++#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
++#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
++#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
++#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
++#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
++#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
++#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_0__SMC_RESP_MASK 0xffff
++#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_1__SMC_RESP_MASK 0xffff
++#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_2__SMC_RESP_MASK 0xffff
++#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_3__SMC_RESP_MASK 0xffff
++#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_4__SMC_RESP_MASK 0xffff
++#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_5__SMC_RESP_MASK 0xffff
++#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_6__SMC_RESP_MASK 0xffff
++#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_7__SMC_RESP_MASK 0xffff
++#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_8__SMC_RESP_MASK 0xffff
++#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_9__SMC_RESP_MASK 0xffff
++#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_10__SMC_RESP_MASK 0xffff
++#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
++#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
++#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
++#define SMC_RESP_11__SMC_RESP_MASK 0xffff
++#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
++#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
++#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
++#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
++#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
++#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
++#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
++#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
++#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
++#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
++#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
++#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
++#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2
++#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
++#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
++#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
++#define SMC_PC_C__smc_pc_c__SHIFT 0x0
++#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
++#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
++#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
++#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
++#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
++#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
++#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
++#define GPIOPAD_A__GPIO_A__SHIFT 0x0
++#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
++#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
++#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
++#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
++#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
++#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
++#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
++#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
++#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
++#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
++#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
++#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
++#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
++#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
++#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
++#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
++#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
++#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
++#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
++#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
++#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
++#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
++#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
++#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff
++#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
++#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
++#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
++#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
++#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
++#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
++#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
++#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
++#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
++#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
++#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
++#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
++#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
++#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
++#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
++#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
++#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
++#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
++#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
++#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
++#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
++#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
++#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
++#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
++#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
++#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
++#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
++#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
++#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
++#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
++#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
++#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
++#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
++#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
++#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
++#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
++#define RCU_VIRT_RESET_REQ__VF_MASK 0xffff
++#define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0
++#define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000
++#define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f
++#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
++#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
++#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
++#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
++#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
++#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
++#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
++#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
++#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
++#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
++#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
++#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
++#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
++#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
++#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
++#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000
++#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000
++#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000
++#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10
++#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000
++#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000
++#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000
++#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13
++#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000
++#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000
++#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16
++#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000
++#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17
++#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000
++#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18
++#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000
++#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19
++#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000
++#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
++#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
++#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
++#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
++#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
++#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
++#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
++#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
++#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
++#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
++#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
++#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
++#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
++#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
++#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
++#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
++#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
++#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
++#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
++#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
++#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
++#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
++#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
++#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
++#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
++#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
++#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
++#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
++#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
++#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
++#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
++#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
++#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
++#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
++#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
++#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
++#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
++#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
++#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
++#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
++#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
++#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
++#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
++#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
++#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
++#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6
++#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1
++#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10
++#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4
++#define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40
++#define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6
++#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00
++#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
++#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
++#define SMU_STATUS__SMU_DONE_MASK 0x1
++#define SMU_STATUS__SMU_DONE__SHIFT 0x0
++#define SMU_STATUS__SMU_PASS_MASK 0x2
++#define SMU_STATUS__SMU_PASS__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
++#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
++#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
++#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
++#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
++#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
++#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
++#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
++#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
++#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
++#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
++#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
++#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
++#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
++#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
++#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
++#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
++#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
++#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
++#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
++#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
++#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
++#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
++#define TDC_STATUS__VDD_Boost_MASK 0xff
++#define TDC_STATUS__VDD_Boost__SHIFT 0x0
++#define TDC_STATUS__VDD_Throttle_MASK 0xff00
++#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
++#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
++#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
++#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
++#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
++#define TDC_MV_AVERAGE__IDD_MASK 0xffff
++#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
++#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
++#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
++#define TDC_VRM_LIMIT__IDD_MASK 0xffff
++#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
++#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
++#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
++#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
++#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
++#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
++#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
++#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
++#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
++#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
++#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
++#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
++#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
++#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
++#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
++#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
++#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
++#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
++#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
++#define FEATURE_STATUS__BAPM_ON_MASK 0x100
++#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
++#define FEATURE_STATUS__LPMX_ON_MASK 0x200
++#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
++#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
++#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
++#define FEATURE_STATUS__LHTC_ON_MASK 0x800
++#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
++#define FEATURE_STATUS__VPC_ON_MASK 0x1000
++#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
++#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
++#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
++#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
++#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
++#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
++#define FEATURE_STATUS__AVS_ON_MASK 0x10000
++#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
++#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
++#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
++#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
++#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
++#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
++#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
++#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
++#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
++#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
++#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
++#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
++#define FEATURE_STATUS__RESERVED__SHIFT 0x16
++#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
++#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
++#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
++#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
++#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
++#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
++#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
++#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
++#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
++#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
++#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
++#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
++#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
++#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
++#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
++#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
++#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
++#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
++#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
++#define DPM_TABLE_29__VRConfig_MASK 0xffffffff
++#define DPM_TABLE_29__VRConfig__SHIFT 0x0
++#define DPM_TABLE_30__SmioMask1_MASK 0xffffffff
++#define DPM_TABLE_30__SmioMask1__SHIFT 0x0
++#define DPM_TABLE_31__SmioMask2_MASK 0xffffffff
++#define DPM_TABLE_31__SmioMask2__SHIFT 0x0
++#define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff
++#define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0
++#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00
++#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8
++#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff
++#define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0
++#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00
++#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8
++#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff
++#define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0
++#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00
++#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8
++#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff
++#define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0
++#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00
++#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8
++#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff
++#define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0
++#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00
++#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8
++#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000
++#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10
++#define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff
++#define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0
++#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00
++#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8
++#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000
++#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10
++#define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff
++#define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0
++#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00
++#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8
++#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000
++#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10
++#define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff
++#define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0
++#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00
++#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8
++#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000
++#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10
++#define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff
++#define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0
++#define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff
++#define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0
++#define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff
++#define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0
++#define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff
++#define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0
++#define DPM_TABLE_44__VddcTable_1_MASK 0xffff
++#define DPM_TABLE_44__VddcTable_1__SHIFT 0x0
++#define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000
++#define DPM_TABLE_44__VddcTable_0__SHIFT 0x10
++#define DPM_TABLE_45__VddcTable_3_MASK 0xffff
++#define DPM_TABLE_45__VddcTable_3__SHIFT 0x0
++#define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000
++#define DPM_TABLE_45__VddcTable_2__SHIFT 0x10
++#define DPM_TABLE_46__VddcTable_5_MASK 0xffff
++#define DPM_TABLE_46__VddcTable_5__SHIFT 0x0
++#define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000
++#define DPM_TABLE_46__VddcTable_4__SHIFT 0x10
++#define DPM_TABLE_47__VddcTable_7_MASK 0xffff
++#define DPM_TABLE_47__VddcTable_7__SHIFT 0x0
++#define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000
++#define DPM_TABLE_47__VddcTable_6__SHIFT 0x10
++#define DPM_TABLE_48__VddcTable_9_MASK 0xffff
++#define DPM_TABLE_48__VddcTable_9__SHIFT 0x0
++#define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000
++#define DPM_TABLE_48__VddcTable_8__SHIFT 0x10
++#define DPM_TABLE_49__VddcTable_11_MASK 0xffff
++#define DPM_TABLE_49__VddcTable_11__SHIFT 0x0
++#define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000
++#define DPM_TABLE_49__VddcTable_10__SHIFT 0x10
++#define DPM_TABLE_50__VddcTable_13_MASK 0xffff
++#define DPM_TABLE_50__VddcTable_13__SHIFT 0x0
++#define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000
++#define DPM_TABLE_50__VddcTable_12__SHIFT 0x10
++#define DPM_TABLE_51__VddcTable_15_MASK 0xffff
++#define DPM_TABLE_51__VddcTable_15__SHIFT 0x0
++#define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000
++#define DPM_TABLE_51__VddcTable_14__SHIFT 0x10
++#define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff
++#define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0
++#define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000
++#define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10
++#define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff
++#define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0
++#define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000
++#define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10
++#define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff
++#define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0
++#define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000
++#define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10
++#define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff
++#define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0
++#define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000
++#define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10
++#define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff
++#define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0
++#define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000
++#define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10
++#define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff
++#define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0
++#define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000
++#define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10
++#define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff
++#define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0
++#define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000
++#define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10
++#define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff
++#define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0
++#define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000
++#define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10
++#define DPM_TABLE_60__VddciTable_1_MASK 0xffff
++#define DPM_TABLE_60__VddciTable_1__SHIFT 0x0
++#define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000
++#define DPM_TABLE_60__VddciTable_0__SHIFT 0x10
++#define DPM_TABLE_61__VddciTable_3_MASK 0xffff
++#define DPM_TABLE_61__VddciTable_3__SHIFT 0x0
++#define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000
++#define DPM_TABLE_61__VddciTable_2__SHIFT 0x10
++#define DPM_TABLE_62__VddciTable_5_MASK 0xffff
++#define DPM_TABLE_62__VddciTable_5__SHIFT 0x0
++#define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000
++#define DPM_TABLE_62__VddciTable_4__SHIFT 0x10
++#define DPM_TABLE_63__VddciTable_7_MASK 0xffff
++#define DPM_TABLE_63__VddciTable_7__SHIFT 0x0
++#define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000
++#define DPM_TABLE_63__VddciTable_6__SHIFT 0x10
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000
++#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000
++#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000
++#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000
++#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000
++#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000
++#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000
++#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000
++#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000
++#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000
++#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000
++#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000
++#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18
++#define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff
++#define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0
++#define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00
++#define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8
++#define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000
++#define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10
++#define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000
++#define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18
++#define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff
++#define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0
++#define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00
++#define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8
++#define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000
++#define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10
++#define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000
++#define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18
++#define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff
++#define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0
++#define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00
++#define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8
++#define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000
++#define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10
++#define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000
++#define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18
++#define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff
++#define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0
++#define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00
++#define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8
++#define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000
++#define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10
++#define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000
++#define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18
++#define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff
++#define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0
++#define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00
++#define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8
++#define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000
++#define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10
++#define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000
++#define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18
++#define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff
++#define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0
++#define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00
++#define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8
++#define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000
++#define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10
++#define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000
++#define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18
++#define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff
++#define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0
++#define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00
++#define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8
++#define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000
++#define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10
++#define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000
++#define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18
++#define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff
++#define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0
++#define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00
++#define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8
++#define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000
++#define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10
++#define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000
++#define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000
++#define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000
++#define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000
++#define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000
++#define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18
++#define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff
++#define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0
++#define DPM_TABLE_88__LinkLevelCount_MASK 0xff00
++#define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8
++#define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000
++#define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10
++#define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000
++#define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18
++#define DPM_TABLE_89__SamuLevelCount_MASK 0xff
++#define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0
++#define DPM_TABLE_89__AcpLevelCount_MASK 0xff00
++#define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8
++#define DPM_TABLE_89__VceLevelCount_MASK 0xff0000
++#define DPM_TABLE_89__VceLevelCount__SHIFT 0x10
++#define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000
++#define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18
++#define DPM_TABLE_90__Reserved_0_MASK 0xffffffff
++#define DPM_TABLE_90__Reserved_0__SHIFT 0x0
++#define DPM_TABLE_91__Reserved_1_MASK 0xffffffff
++#define DPM_TABLE_91__Reserved_1__SHIFT 0x0
++#define DPM_TABLE_92__Reserved_2_MASK 0xffffffff
++#define DPM_TABLE_92__Reserved_2__SHIFT 0x0
++#define DPM_TABLE_93__Reserved_3_MASK 0xffffffff
++#define DPM_TABLE_93__Reserved_3__SHIFT 0x0
++#define DPM_TABLE_94__Reserved_4_MASK 0xffffffff
++#define DPM_TABLE_94__Reserved_4__SHIFT 0x0
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000
++#define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18
++#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff
++#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000
++#define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18
++#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff
++#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000
++#define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18
++#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff
++#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000
++#define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18
++#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff
++#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000
++#define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18
++#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff
++#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000
++#define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10
++#define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000
++#define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000
++#define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18
++#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff
++#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000
++#define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10
++#define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000
++#define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
++#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
++#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
++#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
++#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
++#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
++#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff
++#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
++#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000
++#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10
++#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
++#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
++#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
++#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
++#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000
++#define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18
++#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff
++#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
++#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000
++#define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10
++#define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000
++#define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff
++#define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_186__MemoryACPILevel_RttEnable_MASK 0xff00
++#define DPM_TABLE_186__MemoryACPILevel_RttEnable__SHIFT 0x8
++#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_188__MemoryACPILevel_padding_MASK 0xff
++#define DPM_TABLE_188__MemoryACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_188__MemoryACPILevel_DownHyst_MASK 0xff0000
++#define DPM_TABLE_188__MemoryACPILevel_DownHyst__SHIFT 0x10
++#define DPM_TABLE_188__MemoryACPILevel_UpHyst_MASK 0xff000000
++#define DPM_TABLE_188__MemoryACPILevel_UpHyst__SHIFT 0x18
++#define DPM_TABLE_189__MemoryACPILevel_padding1_MASK 0xff
++#define DPM_TABLE_189__MemoryACPILevel_padding1__SHIFT 0x0
++#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_196__MemoryACPILevel_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_196__MemoryACPILevel_DllCntl__SHIFT 0x0
++#define DPM_TABLE_197__MemoryACPILevel_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_197__MemoryACPILevel_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_198__MemoryACPILevel_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_198__MemoryACPILevel_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_200__MemoryLevel_0_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_200__MemoryLevel_0_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_202__MemoryLevel_0_StutterEnable_MASK 0xff
++#define DPM_TABLE_202__MemoryLevel_0_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_202__MemoryLevel_0_RttEnable_MASK 0xff00
++#define DPM_TABLE_202__MemoryLevel_0_RttEnable__SHIFT 0x8
++#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_204__MemoryLevel_0_padding_MASK 0xff
++#define DPM_TABLE_204__MemoryLevel_0_padding__SHIFT 0x0
++#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_204__MemoryLevel_0_DownHyst_MASK 0xff0000
++#define DPM_TABLE_204__MemoryLevel_0_DownHyst__SHIFT 0x10
++#define DPM_TABLE_204__MemoryLevel_0_UpHyst_MASK 0xff000000
++#define DPM_TABLE_204__MemoryLevel_0_UpHyst__SHIFT 0x18
++#define DPM_TABLE_205__MemoryLevel_0_padding1_MASK 0xff
++#define DPM_TABLE_205__MemoryLevel_0_padding1__SHIFT 0x0
++#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_212__MemoryLevel_0_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_212__MemoryLevel_0_DllCntl__SHIFT 0x0
++#define DPM_TABLE_213__MemoryLevel_0_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_213__MemoryLevel_0_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_214__MemoryLevel_0_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_214__MemoryLevel_0_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_216__MemoryLevel_1_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_216__MemoryLevel_1_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_218__MemoryLevel_1_StutterEnable_MASK 0xff
++#define DPM_TABLE_218__MemoryLevel_1_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_218__MemoryLevel_1_RttEnable_MASK 0xff00
++#define DPM_TABLE_218__MemoryLevel_1_RttEnable__SHIFT 0x8
++#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_220__MemoryLevel_1_padding_MASK 0xff
++#define DPM_TABLE_220__MemoryLevel_1_padding__SHIFT 0x0
++#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_220__MemoryLevel_1_DownHyst_MASK 0xff0000
++#define DPM_TABLE_220__MemoryLevel_1_DownHyst__SHIFT 0x10
++#define DPM_TABLE_220__MemoryLevel_1_UpHyst_MASK 0xff000000
++#define DPM_TABLE_220__MemoryLevel_1_UpHyst__SHIFT 0x18
++#define DPM_TABLE_221__MemoryLevel_1_padding1_MASK 0xff
++#define DPM_TABLE_221__MemoryLevel_1_padding1__SHIFT 0x0
++#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_228__MemoryLevel_1_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_228__MemoryLevel_1_DllCntl__SHIFT 0x0
++#define DPM_TABLE_229__MemoryLevel_1_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_229__MemoryLevel_1_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_230__MemoryLevel_1_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_230__MemoryLevel_1_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_232__MemoryLevel_2_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_232__MemoryLevel_2_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_234__MemoryLevel_2_StutterEnable_MASK 0xff
++#define DPM_TABLE_234__MemoryLevel_2_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_234__MemoryLevel_2_RttEnable_MASK 0xff00
++#define DPM_TABLE_234__MemoryLevel_2_RttEnable__SHIFT 0x8
++#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_236__MemoryLevel_2_padding_MASK 0xff
++#define DPM_TABLE_236__MemoryLevel_2_padding__SHIFT 0x0
++#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_236__MemoryLevel_2_DownHyst_MASK 0xff0000
++#define DPM_TABLE_236__MemoryLevel_2_DownHyst__SHIFT 0x10
++#define DPM_TABLE_236__MemoryLevel_2_UpHyst_MASK 0xff000000
++#define DPM_TABLE_236__MemoryLevel_2_UpHyst__SHIFT 0x18
++#define DPM_TABLE_237__MemoryLevel_2_padding1_MASK 0xff
++#define DPM_TABLE_237__MemoryLevel_2_padding1__SHIFT 0x0
++#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_244__MemoryLevel_2_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_244__MemoryLevel_2_DllCntl__SHIFT 0x0
++#define DPM_TABLE_245__MemoryLevel_2_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_245__MemoryLevel_2_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_246__MemoryLevel_2_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_246__MemoryLevel_2_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_248__MemoryLevel_3_MinMvdd_MASK 0xffffffff
++#define DPM_TABLE_248__MemoryLevel_3_MinMvdd__SHIFT 0x0
++#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency__SHIFT 0x0
++#define DPM_TABLE_250__MemoryLevel_3_StutterEnable_MASK 0xff
++#define DPM_TABLE_250__MemoryLevel_3_StutterEnable__SHIFT 0x0
++#define DPM_TABLE_250__MemoryLevel_3_RttEnable_MASK 0xff00
++#define DPM_TABLE_250__MemoryLevel_3_RttEnable__SHIFT 0x8
++#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
++#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
++#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
++#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
++#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity_MASK 0xff
++#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
++#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
++#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
++#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio_MASK 0xff0000
++#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio__SHIFT 0x10
++#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable_MASK 0xff000000
++#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable__SHIFT 0x18
++#define DPM_TABLE_252__MemoryLevel_3_padding_MASK 0xff
++#define DPM_TABLE_252__MemoryLevel_3_padding__SHIFT 0x0
++#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
++#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
++#define DPM_TABLE_252__MemoryLevel_3_DownHyst_MASK 0xff0000
++#define DPM_TABLE_252__MemoryLevel_3_DownHyst__SHIFT 0x10
++#define DPM_TABLE_252__MemoryLevel_3_UpHyst_MASK 0xff000000
++#define DPM_TABLE_252__MemoryLevel_3_UpHyst__SHIFT 0x18
++#define DPM_TABLE_253__MemoryLevel_3_padding1_MASK 0xff
++#define DPM_TABLE_253__MemoryLevel_3_padding1__SHIFT 0x0
++#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark_MASK 0xff00
++#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
++#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
++#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel__SHIFT 0x10
++#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
++#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
++#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
++#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
++#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
++#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
++#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
++#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
++#define DPM_TABLE_260__MemoryLevel_3_DllCntl_MASK 0xffffffff
++#define DPM_TABLE_260__MemoryLevel_3_DllCntl__SHIFT 0x0
++#define DPM_TABLE_261__MemoryLevel_3_MpllSs1_MASK 0xffffffff
++#define DPM_TABLE_261__MemoryLevel_3_MpllSs1__SHIFT 0x0
++#define DPM_TABLE_262__MemoryLevel_3_MpllSs2_MASK 0xffffffff
++#define DPM_TABLE_262__MemoryLevel_3_MpllSs2__SHIFT 0x0
++#define DPM_TABLE_263__LinkLevel_0_SPC_MASK 0xff
++#define DPM_TABLE_263__LinkLevel_0_SPC__SHIFT 0x0
++#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_264__LinkLevel_0_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_264__LinkLevel_0_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_265__LinkLevel_0_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_265__LinkLevel_0_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_266__LinkLevel_0_Reserved_MASK 0xffffffff
++#define DPM_TABLE_266__LinkLevel_0_Reserved__SHIFT 0x0
++#define DPM_TABLE_267__LinkLevel_1_SPC_MASK 0xff
++#define DPM_TABLE_267__LinkLevel_1_SPC__SHIFT 0x0
++#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_268__LinkLevel_1_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_268__LinkLevel_1_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_269__LinkLevel_1_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_269__LinkLevel_1_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_270__LinkLevel_1_Reserved_MASK 0xffffffff
++#define DPM_TABLE_270__LinkLevel_1_Reserved__SHIFT 0x0
++#define DPM_TABLE_271__LinkLevel_2_SPC_MASK 0xff
++#define DPM_TABLE_271__LinkLevel_2_SPC__SHIFT 0x0
++#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_272__LinkLevel_2_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_272__LinkLevel_2_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_273__LinkLevel_2_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_273__LinkLevel_2_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_274__LinkLevel_2_Reserved_MASK 0xffffffff
++#define DPM_TABLE_274__LinkLevel_2_Reserved__SHIFT 0x0
++#define DPM_TABLE_275__LinkLevel_3_SPC_MASK 0xff
++#define DPM_TABLE_275__LinkLevel_3_SPC__SHIFT 0x0
++#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_276__LinkLevel_3_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_276__LinkLevel_3_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_277__LinkLevel_3_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_277__LinkLevel_3_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_278__LinkLevel_3_Reserved_MASK 0xffffffff
++#define DPM_TABLE_278__LinkLevel_3_Reserved__SHIFT 0x0
++#define DPM_TABLE_279__LinkLevel_4_SPC_MASK 0xff
++#define DPM_TABLE_279__LinkLevel_4_SPC__SHIFT 0x0
++#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_280__LinkLevel_4_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_280__LinkLevel_4_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_281__LinkLevel_4_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_281__LinkLevel_4_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_282__LinkLevel_4_Reserved_MASK 0xffffffff
++#define DPM_TABLE_282__LinkLevel_4_Reserved__SHIFT 0x0
++#define DPM_TABLE_283__LinkLevel_5_SPC_MASK 0xff
++#define DPM_TABLE_283__LinkLevel_5_SPC__SHIFT 0x0
++#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_284__LinkLevel_5_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_284__LinkLevel_5_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_285__LinkLevel_5_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_285__LinkLevel_5_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_286__LinkLevel_5_Reserved_MASK 0xffffffff
++#define DPM_TABLE_286__LinkLevel_5_Reserved__SHIFT 0x0
++#define DPM_TABLE_287__LinkLevel_6_SPC_MASK 0xff
++#define DPM_TABLE_287__LinkLevel_6_SPC__SHIFT 0x0
++#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_288__LinkLevel_6_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_288__LinkLevel_6_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_289__LinkLevel_6_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_289__LinkLevel_6_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_290__LinkLevel_6_Reserved_MASK 0xffffffff
++#define DPM_TABLE_290__LinkLevel_6_Reserved__SHIFT 0x0
++#define DPM_TABLE_291__LinkLevel_7_SPC_MASK 0xff
++#define DPM_TABLE_291__LinkLevel_7_SPC__SHIFT 0x0
++#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity_MASK 0xff00
++#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity__SHIFT 0x8
++#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount_MASK 0xff0000
++#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount__SHIFT 0x10
++#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
++#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
++#define DPM_TABLE_292__LinkLevel_7_DownThreshold_MASK 0xffffffff
++#define DPM_TABLE_292__LinkLevel_7_DownThreshold__SHIFT 0x0
++#define DPM_TABLE_293__LinkLevel_7_UpThreshold_MASK 0xffffffff
++#define DPM_TABLE_293__LinkLevel_7_UpThreshold__SHIFT 0x0
++#define DPM_TABLE_294__LinkLevel_7_Reserved_MASK 0xffffffff
++#define DPM_TABLE_294__LinkLevel_7_Reserved__SHIFT 0x0
++#define DPM_TABLE_295__ACPILevel_Flags_MASK 0xffffffff
++#define DPM_TABLE_295__ACPILevel_Flags__SHIFT 0x0
++#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_297__ACPILevel_SclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_297__ACPILevel_SclkFrequency__SHIFT 0x0
++#define DPM_TABLE_298__ACPILevel_padding_MASK 0xff
++#define DPM_TABLE_298__ACPILevel_padding__SHIFT 0x0
++#define DPM_TABLE_298__ACPILevel_DeepSleepDivId_MASK 0xff00
++#define DPM_TABLE_298__ACPILevel_DeepSleepDivId__SHIFT 0x8
++#define DPM_TABLE_298__ACPILevel_DisplayWatermark_MASK 0xff0000
++#define DPM_TABLE_298__ACPILevel_DisplayWatermark__SHIFT 0x10
++#define DPM_TABLE_298__ACPILevel_SclkDid_MASK 0xff000000
++#define DPM_TABLE_298__ACPILevel_SclkDid__SHIFT 0x18
++#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
++#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
++#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
++#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
++#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
++#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
++#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
++#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
++#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
++#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
++#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
++#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
++#define DPM_TABLE_305__ACPILevel_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_305__ACPILevel_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_307__UvdLevel_0_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_307__UvdLevel_0_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_308__UvdLevel_0_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_308__UvdLevel_0_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_310__UvdLevel_0_padding_1_MASK 0xff
++#define DPM_TABLE_310__UvdLevel_0_padding_1__SHIFT 0x0
++#define DPM_TABLE_310__UvdLevel_0_padding_0_MASK 0xff00
++#define DPM_TABLE_310__UvdLevel_0_padding_0__SHIFT 0x8
++#define DPM_TABLE_310__UvdLevel_0_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_310__UvdLevel_0_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_310__UvdLevel_0_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_310__UvdLevel_0_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_311__UvdLevel_1_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_311__UvdLevel_1_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_312__UvdLevel_1_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_312__UvdLevel_1_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_314__UvdLevel_1_padding_1_MASK 0xff
++#define DPM_TABLE_314__UvdLevel_1_padding_1__SHIFT 0x0
++#define DPM_TABLE_314__UvdLevel_1_padding_0_MASK 0xff00
++#define DPM_TABLE_314__UvdLevel_1_padding_0__SHIFT 0x8
++#define DPM_TABLE_314__UvdLevel_1_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_314__UvdLevel_1_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_314__UvdLevel_1_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_314__UvdLevel_1_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_315__UvdLevel_2_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_315__UvdLevel_2_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_316__UvdLevel_2_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_316__UvdLevel_2_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_318__UvdLevel_2_padding_1_MASK 0xff
++#define DPM_TABLE_318__UvdLevel_2_padding_1__SHIFT 0x0
++#define DPM_TABLE_318__UvdLevel_2_padding_0_MASK 0xff00
++#define DPM_TABLE_318__UvdLevel_2_padding_0__SHIFT 0x8
++#define DPM_TABLE_318__UvdLevel_2_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_318__UvdLevel_2_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_318__UvdLevel_2_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_318__UvdLevel_2_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_319__UvdLevel_3_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_319__UvdLevel_3_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_320__UvdLevel_3_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_320__UvdLevel_3_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_322__UvdLevel_3_padding_1_MASK 0xff
++#define DPM_TABLE_322__UvdLevel_3_padding_1__SHIFT 0x0
++#define DPM_TABLE_322__UvdLevel_3_padding_0_MASK 0xff00
++#define DPM_TABLE_322__UvdLevel_3_padding_0__SHIFT 0x8
++#define DPM_TABLE_322__UvdLevel_3_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_322__UvdLevel_3_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_322__UvdLevel_3_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_322__UvdLevel_3_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_323__UvdLevel_4_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_323__UvdLevel_4_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_324__UvdLevel_4_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_324__UvdLevel_4_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_326__UvdLevel_4_padding_1_MASK 0xff
++#define DPM_TABLE_326__UvdLevel_4_padding_1__SHIFT 0x0
++#define DPM_TABLE_326__UvdLevel_4_padding_0_MASK 0xff00
++#define DPM_TABLE_326__UvdLevel_4_padding_0__SHIFT 0x8
++#define DPM_TABLE_326__UvdLevel_4_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_326__UvdLevel_4_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_326__UvdLevel_4_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_326__UvdLevel_4_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_327__UvdLevel_5_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_327__UvdLevel_5_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_328__UvdLevel_5_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_328__UvdLevel_5_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_330__UvdLevel_5_padding_1_MASK 0xff
++#define DPM_TABLE_330__UvdLevel_5_padding_1__SHIFT 0x0
++#define DPM_TABLE_330__UvdLevel_5_padding_0_MASK 0xff00
++#define DPM_TABLE_330__UvdLevel_5_padding_0__SHIFT 0x8
++#define DPM_TABLE_330__UvdLevel_5_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_330__UvdLevel_5_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_330__UvdLevel_5_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_330__UvdLevel_5_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_331__UvdLevel_6_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_331__UvdLevel_6_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_332__UvdLevel_6_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_332__UvdLevel_6_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_334__UvdLevel_6_padding_1_MASK 0xff
++#define DPM_TABLE_334__UvdLevel_6_padding_1__SHIFT 0x0
++#define DPM_TABLE_334__UvdLevel_6_padding_0_MASK 0xff00
++#define DPM_TABLE_334__UvdLevel_6_padding_0__SHIFT 0x8
++#define DPM_TABLE_334__UvdLevel_6_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_334__UvdLevel_6_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_334__UvdLevel_6_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_334__UvdLevel_6_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_335__UvdLevel_7_VclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_335__UvdLevel_7_VclkFrequency__SHIFT 0x0
++#define DPM_TABLE_336__UvdLevel_7_DclkFrequency_MASK 0xffffffff
++#define DPM_TABLE_336__UvdLevel_7_DclkFrequency__SHIFT 0x0
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_338__UvdLevel_7_padding_1_MASK 0xff
++#define DPM_TABLE_338__UvdLevel_7_padding_1__SHIFT 0x0
++#define DPM_TABLE_338__UvdLevel_7_padding_0_MASK 0xff00
++#define DPM_TABLE_338__UvdLevel_7_padding_0__SHIFT 0x8
++#define DPM_TABLE_338__UvdLevel_7_DclkDivider_MASK 0xff0000
++#define DPM_TABLE_338__UvdLevel_7_DclkDivider__SHIFT 0x10
++#define DPM_TABLE_338__UvdLevel_7_VclkDivider_MASK 0xff000000
++#define DPM_TABLE_338__UvdLevel_7_VclkDivider__SHIFT 0x18
++#define DPM_TABLE_339__VceLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_339__VceLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_341__VceLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_341__VceLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_341__VceLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_341__VceLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_341__VceLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_341__VceLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_341__VceLevel_0_Divider_MASK 0xff000000
++#define DPM_TABLE_341__VceLevel_0_Divider__SHIFT 0x18
++#define DPM_TABLE_342__VceLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_342__VceLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_344__VceLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_344__VceLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_344__VceLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_344__VceLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_344__VceLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_344__VceLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_344__VceLevel_1_Divider_MASK 0xff000000
++#define DPM_TABLE_344__VceLevel_1_Divider__SHIFT 0x18
++#define DPM_TABLE_345__VceLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_345__VceLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_347__VceLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_347__VceLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_347__VceLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_347__VceLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_347__VceLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_347__VceLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_347__VceLevel_2_Divider_MASK 0xff000000
++#define DPM_TABLE_347__VceLevel_2_Divider__SHIFT 0x18
++#define DPM_TABLE_348__VceLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_348__VceLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_350__VceLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_350__VceLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_350__VceLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_350__VceLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_350__VceLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_350__VceLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_350__VceLevel_3_Divider_MASK 0xff000000
++#define DPM_TABLE_350__VceLevel_3_Divider__SHIFT 0x18
++#define DPM_TABLE_351__VceLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_351__VceLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_353__VceLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_353__VceLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_353__VceLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_353__VceLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_353__VceLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_353__VceLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_353__VceLevel_4_Divider_MASK 0xff000000
++#define DPM_TABLE_353__VceLevel_4_Divider__SHIFT 0x18
++#define DPM_TABLE_354__VceLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_354__VceLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_356__VceLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_356__VceLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_356__VceLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_356__VceLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_356__VceLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_356__VceLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_356__VceLevel_5_Divider_MASK 0xff000000
++#define DPM_TABLE_356__VceLevel_5_Divider__SHIFT 0x18
++#define DPM_TABLE_357__VceLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_357__VceLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_359__VceLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_359__VceLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_359__VceLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_359__VceLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_359__VceLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_359__VceLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_359__VceLevel_6_Divider_MASK 0xff000000
++#define DPM_TABLE_359__VceLevel_6_Divider__SHIFT 0x18
++#define DPM_TABLE_360__VceLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_360__VceLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_362__VceLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_362__VceLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_362__VceLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_362__VceLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_362__VceLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_362__VceLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_362__VceLevel_7_Divider_MASK 0xff000000
++#define DPM_TABLE_362__VceLevel_7_Divider__SHIFT 0x18
++#define DPM_TABLE_363__AcpLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_363__AcpLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_365__AcpLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_365__AcpLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_365__AcpLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_365__AcpLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_365__AcpLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_365__AcpLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_365__AcpLevel_0_Divider_MASK 0xff000000
++#define DPM_TABLE_365__AcpLevel_0_Divider__SHIFT 0x18
++#define DPM_TABLE_366__AcpLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_366__AcpLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_368__AcpLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_368__AcpLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_368__AcpLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_368__AcpLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_368__AcpLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_368__AcpLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_368__AcpLevel_1_Divider_MASK 0xff000000
++#define DPM_TABLE_368__AcpLevel_1_Divider__SHIFT 0x18
++#define DPM_TABLE_369__AcpLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_369__AcpLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_371__AcpLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_371__AcpLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_371__AcpLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_371__AcpLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_371__AcpLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_371__AcpLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_371__AcpLevel_2_Divider_MASK 0xff000000
++#define DPM_TABLE_371__AcpLevel_2_Divider__SHIFT 0x18
++#define DPM_TABLE_372__AcpLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_372__AcpLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_374__AcpLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_374__AcpLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_374__AcpLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_374__AcpLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_374__AcpLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_374__AcpLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_374__AcpLevel_3_Divider_MASK 0xff000000
++#define DPM_TABLE_374__AcpLevel_3_Divider__SHIFT 0x18
++#define DPM_TABLE_375__AcpLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_375__AcpLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_377__AcpLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_377__AcpLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_377__AcpLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_377__AcpLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_377__AcpLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_377__AcpLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_377__AcpLevel_4_Divider_MASK 0xff000000
++#define DPM_TABLE_377__AcpLevel_4_Divider__SHIFT 0x18
++#define DPM_TABLE_378__AcpLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_378__AcpLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_380__AcpLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_380__AcpLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_380__AcpLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_380__AcpLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_380__AcpLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_380__AcpLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_380__AcpLevel_5_Divider_MASK 0xff000000
++#define DPM_TABLE_380__AcpLevel_5_Divider__SHIFT 0x18
++#define DPM_TABLE_381__AcpLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_381__AcpLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_383__AcpLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_383__AcpLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_383__AcpLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_383__AcpLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_383__AcpLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_383__AcpLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_383__AcpLevel_6_Divider_MASK 0xff000000
++#define DPM_TABLE_383__AcpLevel_6_Divider__SHIFT 0x18
++#define DPM_TABLE_384__AcpLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_384__AcpLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_386__AcpLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_386__AcpLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_386__AcpLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_386__AcpLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_386__AcpLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_386__AcpLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_386__AcpLevel_7_Divider_MASK 0xff000000
++#define DPM_TABLE_386__AcpLevel_7_Divider__SHIFT 0x18
++#define DPM_TABLE_387__SamuLevel_0_Frequency_MASK 0xffffffff
++#define DPM_TABLE_387__SamuLevel_0_Frequency__SHIFT 0x0
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_389__SamuLevel_0_padding_2_MASK 0xff
++#define DPM_TABLE_389__SamuLevel_0_padding_2__SHIFT 0x0
++#define DPM_TABLE_389__SamuLevel_0_padding_1_MASK 0xff00
++#define DPM_TABLE_389__SamuLevel_0_padding_1__SHIFT 0x8
++#define DPM_TABLE_389__SamuLevel_0_padding_0_MASK 0xff0000
++#define DPM_TABLE_389__SamuLevel_0_padding_0__SHIFT 0x10
++#define DPM_TABLE_389__SamuLevel_0_Divider_MASK 0xff000000
++#define DPM_TABLE_389__SamuLevel_0_Divider__SHIFT 0x18
++#define DPM_TABLE_390__SamuLevel_1_Frequency_MASK 0xffffffff
++#define DPM_TABLE_390__SamuLevel_1_Frequency__SHIFT 0x0
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_392__SamuLevel_1_padding_2_MASK 0xff
++#define DPM_TABLE_392__SamuLevel_1_padding_2__SHIFT 0x0
++#define DPM_TABLE_392__SamuLevel_1_padding_1_MASK 0xff00
++#define DPM_TABLE_392__SamuLevel_1_padding_1__SHIFT 0x8
++#define DPM_TABLE_392__SamuLevel_1_padding_0_MASK 0xff0000
++#define DPM_TABLE_392__SamuLevel_1_padding_0__SHIFT 0x10
++#define DPM_TABLE_392__SamuLevel_1_Divider_MASK 0xff000000
++#define DPM_TABLE_392__SamuLevel_1_Divider__SHIFT 0x18
++#define DPM_TABLE_393__SamuLevel_2_Frequency_MASK 0xffffffff
++#define DPM_TABLE_393__SamuLevel_2_Frequency__SHIFT 0x0
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_395__SamuLevel_2_padding_2_MASK 0xff
++#define DPM_TABLE_395__SamuLevel_2_padding_2__SHIFT 0x0
++#define DPM_TABLE_395__SamuLevel_2_padding_1_MASK 0xff00
++#define DPM_TABLE_395__SamuLevel_2_padding_1__SHIFT 0x8
++#define DPM_TABLE_395__SamuLevel_2_padding_0_MASK 0xff0000
++#define DPM_TABLE_395__SamuLevel_2_padding_0__SHIFT 0x10
++#define DPM_TABLE_395__SamuLevel_2_Divider_MASK 0xff000000
++#define DPM_TABLE_395__SamuLevel_2_Divider__SHIFT 0x18
++#define DPM_TABLE_396__SamuLevel_3_Frequency_MASK 0xffffffff
++#define DPM_TABLE_396__SamuLevel_3_Frequency__SHIFT 0x0
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_398__SamuLevel_3_padding_2_MASK 0xff
++#define DPM_TABLE_398__SamuLevel_3_padding_2__SHIFT 0x0
++#define DPM_TABLE_398__SamuLevel_3_padding_1_MASK 0xff00
++#define DPM_TABLE_398__SamuLevel_3_padding_1__SHIFT 0x8
++#define DPM_TABLE_398__SamuLevel_3_padding_0_MASK 0xff0000
++#define DPM_TABLE_398__SamuLevel_3_padding_0__SHIFT 0x10
++#define DPM_TABLE_398__SamuLevel_3_Divider_MASK 0xff000000
++#define DPM_TABLE_398__SamuLevel_3_Divider__SHIFT 0x18
++#define DPM_TABLE_399__SamuLevel_4_Frequency_MASK 0xffffffff
++#define DPM_TABLE_399__SamuLevel_4_Frequency__SHIFT 0x0
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_401__SamuLevel_4_padding_2_MASK 0xff
++#define DPM_TABLE_401__SamuLevel_4_padding_2__SHIFT 0x0
++#define DPM_TABLE_401__SamuLevel_4_padding_1_MASK 0xff00
++#define DPM_TABLE_401__SamuLevel_4_padding_1__SHIFT 0x8
++#define DPM_TABLE_401__SamuLevel_4_padding_0_MASK 0xff0000
++#define DPM_TABLE_401__SamuLevel_4_padding_0__SHIFT 0x10
++#define DPM_TABLE_401__SamuLevel_4_Divider_MASK 0xff000000
++#define DPM_TABLE_401__SamuLevel_4_Divider__SHIFT 0x18
++#define DPM_TABLE_402__SamuLevel_5_Frequency_MASK 0xffffffff
++#define DPM_TABLE_402__SamuLevel_5_Frequency__SHIFT 0x0
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_404__SamuLevel_5_padding_2_MASK 0xff
++#define DPM_TABLE_404__SamuLevel_5_padding_2__SHIFT 0x0
++#define DPM_TABLE_404__SamuLevel_5_padding_1_MASK 0xff00
++#define DPM_TABLE_404__SamuLevel_5_padding_1__SHIFT 0x8
++#define DPM_TABLE_404__SamuLevel_5_padding_0_MASK 0xff0000
++#define DPM_TABLE_404__SamuLevel_5_padding_0__SHIFT 0x10
++#define DPM_TABLE_404__SamuLevel_5_Divider_MASK 0xff000000
++#define DPM_TABLE_404__SamuLevel_5_Divider__SHIFT 0x18
++#define DPM_TABLE_405__SamuLevel_6_Frequency_MASK 0xffffffff
++#define DPM_TABLE_405__SamuLevel_6_Frequency__SHIFT 0x0
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_407__SamuLevel_6_padding_2_MASK 0xff
++#define DPM_TABLE_407__SamuLevel_6_padding_2__SHIFT 0x0
++#define DPM_TABLE_407__SamuLevel_6_padding_1_MASK 0xff00
++#define DPM_TABLE_407__SamuLevel_6_padding_1__SHIFT 0x8
++#define DPM_TABLE_407__SamuLevel_6_padding_0_MASK 0xff0000
++#define DPM_TABLE_407__SamuLevel_6_padding_0__SHIFT 0x10
++#define DPM_TABLE_407__SamuLevel_6_Divider_MASK 0xff000000
++#define DPM_TABLE_407__SamuLevel_6_Divider__SHIFT 0x18
++#define DPM_TABLE_408__SamuLevel_7_Frequency_MASK 0xffffffff
++#define DPM_TABLE_408__SamuLevel_7_Frequency__SHIFT 0x0
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases_MASK 0xff
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_410__SamuLevel_7_padding_2_MASK 0xff
++#define DPM_TABLE_410__SamuLevel_7_padding_2__SHIFT 0x0
++#define DPM_TABLE_410__SamuLevel_7_padding_1_MASK 0xff00
++#define DPM_TABLE_410__SamuLevel_7_padding_1__SHIFT 0x8
++#define DPM_TABLE_410__SamuLevel_7_padding_0_MASK 0xff0000
++#define DPM_TABLE_410__SamuLevel_7_padding_0__SHIFT 0x10
++#define DPM_TABLE_410__SamuLevel_7_Divider_MASK 0xff000000
++#define DPM_TABLE_410__SamuLevel_7_Divider__SHIFT 0x18
++#define DPM_TABLE_411__Ulv_CcPwrDynRm_MASK 0xffffffff
++#define DPM_TABLE_411__Ulv_CcPwrDynRm__SHIFT 0x0
++#define DPM_TABLE_412__Ulv_CcPwrDynRm1_MASK 0xffffffff
++#define DPM_TABLE_412__Ulv_CcPwrDynRm1__SHIFT 0x0
++#define DPM_TABLE_413__Ulv_VddcPhase_MASK 0xff
++#define DPM_TABLE_413__Ulv_VddcPhase__SHIFT 0x0
++#define DPM_TABLE_413__Ulv_VddcOffsetVid_MASK 0xff00
++#define DPM_TABLE_413__Ulv_VddcOffsetVid__SHIFT 0x8
++#define DPM_TABLE_413__Ulv_VddcOffset_MASK 0xffff0000
++#define DPM_TABLE_413__Ulv_VddcOffset__SHIFT 0x10
++#define DPM_TABLE_414__Ulv_Reserved_MASK 0xffffffff
++#define DPM_TABLE_414__Ulv_Reserved__SHIFT 0x0
++#define DPM_TABLE_415__SclkStepSize_MASK 0xffffffff
++#define DPM_TABLE_415__SclkStepSize__SHIFT 0x0
++#define DPM_TABLE_416__Smio_0_MASK 0xffffffff
++#define DPM_TABLE_416__Smio_0__SHIFT 0x0
++#define DPM_TABLE_417__Smio_1_MASK 0xffffffff
++#define DPM_TABLE_417__Smio_1__SHIFT 0x0
++#define DPM_TABLE_418__Smio_2_MASK 0xffffffff
++#define DPM_TABLE_418__Smio_2__SHIFT 0x0
++#define DPM_TABLE_419__Smio_3_MASK 0xffffffff
++#define DPM_TABLE_419__Smio_3__SHIFT 0x0
++#define DPM_TABLE_420__Smio_4_MASK 0xffffffff
++#define DPM_TABLE_420__Smio_4__SHIFT 0x0
++#define DPM_TABLE_421__Smio_5_MASK 0xffffffff
++#define DPM_TABLE_421__Smio_5__SHIFT 0x0
++#define DPM_TABLE_422__Smio_6_MASK 0xffffffff
++#define DPM_TABLE_422__Smio_6__SHIFT 0x0
++#define DPM_TABLE_423__Smio_7_MASK 0xffffffff
++#define DPM_TABLE_423__Smio_7__SHIFT 0x0
++#define DPM_TABLE_424__Smio_8_MASK 0xffffffff
++#define DPM_TABLE_424__Smio_8__SHIFT 0x0
++#define DPM_TABLE_425__Smio_9_MASK 0xffffffff
++#define DPM_TABLE_425__Smio_9__SHIFT 0x0
++#define DPM_TABLE_426__Smio_10_MASK 0xffffffff
++#define DPM_TABLE_426__Smio_10__SHIFT 0x0
++#define DPM_TABLE_427__Smio_11_MASK 0xffffffff
++#define DPM_TABLE_427__Smio_11__SHIFT 0x0
++#define DPM_TABLE_428__Smio_12_MASK 0xffffffff
++#define DPM_TABLE_428__Smio_12__SHIFT 0x0
++#define DPM_TABLE_429__Smio_13_MASK 0xffffffff
++#define DPM_TABLE_429__Smio_13__SHIFT 0x0
++#define DPM_TABLE_430__Smio_14_MASK 0xffffffff
++#define DPM_TABLE_430__Smio_14__SHIFT 0x0
++#define DPM_TABLE_431__Smio_15_MASK 0xffffffff
++#define DPM_TABLE_431__Smio_15__SHIFT 0x0
++#define DPM_TABLE_432__Smio_16_MASK 0xffffffff
++#define DPM_TABLE_432__Smio_16__SHIFT 0x0
++#define DPM_TABLE_433__Smio_17_MASK 0xffffffff
++#define DPM_TABLE_433__Smio_17__SHIFT 0x0
++#define DPM_TABLE_434__Smio_18_MASK 0xffffffff
++#define DPM_TABLE_434__Smio_18__SHIFT 0x0
++#define DPM_TABLE_435__Smio_19_MASK 0xffffffff
++#define DPM_TABLE_435__Smio_19__SHIFT 0x0
++#define DPM_TABLE_436__Smio_20_MASK 0xffffffff
++#define DPM_TABLE_436__Smio_20__SHIFT 0x0
++#define DPM_TABLE_437__Smio_21_MASK 0xffffffff
++#define DPM_TABLE_437__Smio_21__SHIFT 0x0
++#define DPM_TABLE_438__Smio_22_MASK 0xffffffff
++#define DPM_TABLE_438__Smio_22__SHIFT 0x0
++#define DPM_TABLE_439__Smio_23_MASK 0xffffffff
++#define DPM_TABLE_439__Smio_23__SHIFT 0x0
++#define DPM_TABLE_440__Smio_24_MASK 0xffffffff
++#define DPM_TABLE_440__Smio_24__SHIFT 0x0
++#define DPM_TABLE_441__Smio_25_MASK 0xffffffff
++#define DPM_TABLE_441__Smio_25__SHIFT 0x0
++#define DPM_TABLE_442__Smio_26_MASK 0xffffffff
++#define DPM_TABLE_442__Smio_26__SHIFT 0x0
++#define DPM_TABLE_443__Smio_27_MASK 0xffffffff
++#define DPM_TABLE_443__Smio_27__SHIFT 0x0
++#define DPM_TABLE_444__Smio_28_MASK 0xffffffff
++#define DPM_TABLE_444__Smio_28__SHIFT 0x0
++#define DPM_TABLE_445__Smio_29_MASK 0xffffffff
++#define DPM_TABLE_445__Smio_29__SHIFT 0x0
++#define DPM_TABLE_446__Smio_30_MASK 0xffffffff
++#define DPM_TABLE_446__Smio_30__SHIFT 0x0
++#define DPM_TABLE_447__Smio_31_MASK 0xffffffff
++#define DPM_TABLE_447__Smio_31__SHIFT 0x0
++#define DPM_TABLE_448__SamuBootLevel_MASK 0xff
++#define DPM_TABLE_448__SamuBootLevel__SHIFT 0x0
++#define DPM_TABLE_448__AcpBootLevel_MASK 0xff00
++#define DPM_TABLE_448__AcpBootLevel__SHIFT 0x8
++#define DPM_TABLE_448__VceBootLevel_MASK 0xff0000
++#define DPM_TABLE_448__VceBootLevel__SHIFT 0x10
++#define DPM_TABLE_448__UvdBootLevel_MASK 0xff000000
++#define DPM_TABLE_448__UvdBootLevel__SHIFT 0x18
++#define DPM_TABLE_449__GraphicsInterval_MASK 0xff
++#define DPM_TABLE_449__GraphicsInterval__SHIFT 0x0
++#define DPM_TABLE_449__GraphicsThermThrottleEnable_MASK 0xff00
++#define DPM_TABLE_449__GraphicsThermThrottleEnable__SHIFT 0x8
++#define DPM_TABLE_449__GraphicsVoltageChangeEnable_MASK 0xff0000
++#define DPM_TABLE_449__GraphicsVoltageChangeEnable__SHIFT 0x10
++#define DPM_TABLE_449__GraphicsBootLevel_MASK 0xff000000
++#define DPM_TABLE_449__GraphicsBootLevel__SHIFT 0x18
++#define DPM_TABLE_450__TemperatureLimitHigh_MASK 0xffff
++#define DPM_TABLE_450__TemperatureLimitHigh__SHIFT 0x0
++#define DPM_TABLE_450__ThermalInterval_MASK 0xff0000
++#define DPM_TABLE_450__ThermalInterval__SHIFT 0x10
++#define DPM_TABLE_450__VoltageInterval_MASK 0xff000000
++#define DPM_TABLE_450__VoltageInterval__SHIFT 0x18
++#define DPM_TABLE_451__MemoryVoltageChangeEnable_MASK 0xff
++#define DPM_TABLE_451__MemoryVoltageChangeEnable__SHIFT 0x0
++#define DPM_TABLE_451__MemoryBootLevel_MASK 0xff00
++#define DPM_TABLE_451__MemoryBootLevel__SHIFT 0x8
++#define DPM_TABLE_451__TemperatureLimitLow_MASK 0xffff0000
++#define DPM_TABLE_451__TemperatureLimitLow__SHIFT 0x10
++#define DPM_TABLE_452__MemoryThermThrottleEnable_MASK 0xff
++#define DPM_TABLE_452__MemoryThermThrottleEnable__SHIFT 0x0
++#define DPM_TABLE_452__MemoryInterval_MASK 0xff00
++#define DPM_TABLE_452__MemoryInterval__SHIFT 0x8
++#define DPM_TABLE_452__BootMVdd_MASK 0xffff0000
++#define DPM_TABLE_452__BootMVdd__SHIFT 0x10
++#define DPM_TABLE_453__PhaseResponseTime_MASK 0xffff
++#define DPM_TABLE_453__PhaseResponseTime__SHIFT 0x0
++#define DPM_TABLE_453__VoltageResponseTime_MASK 0xffff0000
++#define DPM_TABLE_453__VoltageResponseTime__SHIFT 0x10
++#define DPM_TABLE_454__DTEMode_MASK 0xff
++#define DPM_TABLE_454__DTEMode__SHIFT 0x0
++#define DPM_TABLE_454__DTEInterval_MASK 0xff00
++#define DPM_TABLE_454__DTEInterval__SHIFT 0x8
++#define DPM_TABLE_454__PCIeGenInterval_MASK 0xff0000
++#define DPM_TABLE_454__PCIeGenInterval__SHIFT 0x10
++#define DPM_TABLE_454__PCIeBootLinkLevel_MASK 0xff000000
++#define DPM_TABLE_454__PCIeBootLinkLevel__SHIFT 0x18
++#define DPM_TABLE_455__ThermGpio_MASK 0xff
++#define DPM_TABLE_455__ThermGpio__SHIFT 0x0
++#define DPM_TABLE_455__AcDcGpio_MASK 0xff00
++#define DPM_TABLE_455__AcDcGpio__SHIFT 0x8
++#define DPM_TABLE_455__VRHotGpio_MASK 0xff0000
++#define DPM_TABLE_455__VRHotGpio__SHIFT 0x10
++#define DPM_TABLE_455__SVI2Enable_MASK 0xff000000
++#define DPM_TABLE_455__SVI2Enable__SHIFT 0x18
++#define DPM_TABLE_456__PPM_TemperatureLimit_MASK 0xffff
++#define DPM_TABLE_456__PPM_TemperatureLimit__SHIFT 0x0
++#define DPM_TABLE_456__PPM_PkgPwrLimit_MASK 0xffff0000
++#define DPM_TABLE_456__PPM_PkgPwrLimit__SHIFT 0x10
++#define DPM_TABLE_457__TargetTdp_MASK 0xffff
++#define DPM_TABLE_457__TargetTdp__SHIFT 0x0
++#define DPM_TABLE_457__DefaultTdp_MASK 0xffff0000
++#define DPM_TABLE_457__DefaultTdp__SHIFT 0x10
++#define DPM_TABLE_458__FpsLowThreshold_MASK 0xffff
++#define DPM_TABLE_458__FpsLowThreshold__SHIFT 0x0
++#define DPM_TABLE_458__FpsHighThreshold_MASK 0xffff0000
++#define DPM_TABLE_458__FpsHighThreshold__SHIFT 0x10
++#define DPM_TABLE_459__BAPMTI_R_0_1_0_MASK 0xffff
++#define DPM_TABLE_459__BAPMTI_R_0_1_0__SHIFT 0x0
++#define DPM_TABLE_459__BAPMTI_R_0_0_0_MASK 0xffff0000
++#define DPM_TABLE_459__BAPMTI_R_0_0_0__SHIFT 0x10
++#define DPM_TABLE_460__BAPMTI_R_1_0_0_MASK 0xffff
++#define DPM_TABLE_460__BAPMTI_R_1_0_0__SHIFT 0x0
++#define DPM_TABLE_460__BAPMTI_R_0_2_0_MASK 0xffff0000
++#define DPM_TABLE_460__BAPMTI_R_0_2_0__SHIFT 0x10
++#define DPM_TABLE_461__BAPMTI_R_1_2_0_MASK 0xffff
++#define DPM_TABLE_461__BAPMTI_R_1_2_0__SHIFT 0x0
++#define DPM_TABLE_461__BAPMTI_R_1_1_0_MASK 0xffff0000
++#define DPM_TABLE_461__BAPMTI_R_1_1_0__SHIFT 0x10
++#define DPM_TABLE_462__BAPMTI_R_2_1_0_MASK 0xffff
++#define DPM_TABLE_462__BAPMTI_R_2_1_0__SHIFT 0x0
++#define DPM_TABLE_462__BAPMTI_R_2_0_0_MASK 0xffff0000
++#define DPM_TABLE_462__BAPMTI_R_2_0_0__SHIFT 0x10
++#define DPM_TABLE_463__BAPMTI_R_3_0_0_MASK 0xffff
++#define DPM_TABLE_463__BAPMTI_R_3_0_0__SHIFT 0x0
++#define DPM_TABLE_463__BAPMTI_R_2_2_0_MASK 0xffff0000
++#define DPM_TABLE_463__BAPMTI_R_2_2_0__SHIFT 0x10
++#define DPM_TABLE_464__BAPMTI_R_3_2_0_MASK 0xffff
++#define DPM_TABLE_464__BAPMTI_R_3_2_0__SHIFT 0x0
++#define DPM_TABLE_464__BAPMTI_R_3_1_0_MASK 0xffff0000
++#define DPM_TABLE_464__BAPMTI_R_3_1_0__SHIFT 0x10
++#define DPM_TABLE_465__BAPMTI_R_4_1_0_MASK 0xffff
++#define DPM_TABLE_465__BAPMTI_R_4_1_0__SHIFT 0x0
++#define DPM_TABLE_465__BAPMTI_R_4_0_0_MASK 0xffff0000
++#define DPM_TABLE_465__BAPMTI_R_4_0_0__SHIFT 0x10
++#define DPM_TABLE_466__BAPMTI_RC_0_0_0_MASK 0xffff
++#define DPM_TABLE_466__BAPMTI_RC_0_0_0__SHIFT 0x0
++#define DPM_TABLE_466__BAPMTI_R_4_2_0_MASK 0xffff0000
++#define DPM_TABLE_466__BAPMTI_R_4_2_0__SHIFT 0x10
++#define DPM_TABLE_467__BAPMTI_RC_0_2_0_MASK 0xffff
++#define DPM_TABLE_467__BAPMTI_RC_0_2_0__SHIFT 0x0
++#define DPM_TABLE_467__BAPMTI_RC_0_1_0_MASK 0xffff0000
++#define DPM_TABLE_467__BAPMTI_RC_0_1_0__SHIFT 0x10
++#define DPM_TABLE_468__BAPMTI_RC_1_1_0_MASK 0xffff
++#define DPM_TABLE_468__BAPMTI_RC_1_1_0__SHIFT 0x0
++#define DPM_TABLE_468__BAPMTI_RC_1_0_0_MASK 0xffff0000
++#define DPM_TABLE_468__BAPMTI_RC_1_0_0__SHIFT 0x10
++#define DPM_TABLE_469__BAPMTI_RC_2_0_0_MASK 0xffff
++#define DPM_TABLE_469__BAPMTI_RC_2_0_0__SHIFT 0x0
++#define DPM_TABLE_469__BAPMTI_RC_1_2_0_MASK 0xffff0000
++#define DPM_TABLE_469__BAPMTI_RC_1_2_0__SHIFT 0x10
++#define DPM_TABLE_470__BAPMTI_RC_2_2_0_MASK 0xffff
++#define DPM_TABLE_470__BAPMTI_RC_2_2_0__SHIFT 0x0
++#define DPM_TABLE_470__BAPMTI_RC_2_1_0_MASK 0xffff0000
++#define DPM_TABLE_470__BAPMTI_RC_2_1_0__SHIFT 0x10
++#define DPM_TABLE_471__BAPMTI_RC_3_1_0_MASK 0xffff
++#define DPM_TABLE_471__BAPMTI_RC_3_1_0__SHIFT 0x0
++#define DPM_TABLE_471__BAPMTI_RC_3_0_0_MASK 0xffff0000
++#define DPM_TABLE_471__BAPMTI_RC_3_0_0__SHIFT 0x10
++#define DPM_TABLE_472__BAPMTI_RC_4_0_0_MASK 0xffff
++#define DPM_TABLE_472__BAPMTI_RC_4_0_0__SHIFT 0x0
++#define DPM_TABLE_472__BAPMTI_RC_3_2_0_MASK 0xffff0000
++#define DPM_TABLE_472__BAPMTI_RC_3_2_0__SHIFT 0x10
++#define DPM_TABLE_473__BAPMTI_RC_4_2_0_MASK 0xffff
++#define DPM_TABLE_473__BAPMTI_RC_4_2_0__SHIFT 0x0
++#define DPM_TABLE_473__BAPMTI_RC_4_1_0_MASK 0xffff0000
++#define DPM_TABLE_473__BAPMTI_RC_4_1_0__SHIFT 0x10
++#define DPM_TABLE_474__GpuTjHyst_MASK 0xff
++#define DPM_TABLE_474__GpuTjHyst__SHIFT 0x0
++#define DPM_TABLE_474__GpuTjMax_MASK 0xff00
++#define DPM_TABLE_474__GpuTjMax__SHIFT 0x8
++#define DPM_TABLE_474__DTETjOffset_MASK 0xff0000
++#define DPM_TABLE_474__DTETjOffset__SHIFT 0x10
++#define DPM_TABLE_474__DTEAmbientTempBase_MASK 0xff000000
++#define DPM_TABLE_474__DTEAmbientTempBase__SHIFT 0x18
++#define DPM_TABLE_475__BootVoltage_Phases_MASK 0xff
++#define DPM_TABLE_475__BootVoltage_Phases__SHIFT 0x0
++#define DPM_TABLE_475__BootVoltage_VddGfx_MASK 0xff00
++#define DPM_TABLE_475__BootVoltage_VddGfx__SHIFT 0x8
++#define DPM_TABLE_475__BootVoltage_Vddci_MASK 0xff0000
++#define DPM_TABLE_475__BootVoltage_Vddci__SHIFT 0x10
++#define DPM_TABLE_475__BootVoltage_Vddc_MASK 0xff000000
++#define DPM_TABLE_475__BootVoltage_Vddc__SHIFT 0x18
++#define DPM_TABLE_476__BAPM_TEMP_GRADIENT_MASK 0xffffffff
++#define DPM_TABLE_476__BAPM_TEMP_GRADIENT__SHIFT 0x0
++#define DPM_TABLE_477__LowSclkInterruptThreshold_MASK 0xffffffff
++#define DPM_TABLE_477__LowSclkInterruptThreshold__SHIFT 0x0
++#define DPM_TABLE_478__VddGfxReChkWait_MASK 0xffffffff
++#define DPM_TABLE_478__VddGfxReChkWait__SHIFT 0x0
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000
++#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000
++#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000
++#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000
++#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000
++#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000
++#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000
++#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000
++#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000
++#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000
++#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000
++#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000
++#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18
++#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff
++#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000
++#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18
++#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
++#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
++#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
++#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
++#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
++#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
++#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
++#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
++#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
++#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
++#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
++#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
++#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
++#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
++#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
++#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
++#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
++#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
++#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
++#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
++#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
++#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
++#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
++#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
++#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
++#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
++#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
++#define FAN_TABLE_1__TempMin_MASK 0xffff
++#define FAN_TABLE_1__TempMin__SHIFT 0x0
++#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
++#define FAN_TABLE_1__FdoMode__SHIFT 0x10
++#define FAN_TABLE_2__TempMax_MASK 0xffff
++#define FAN_TABLE_2__TempMax__SHIFT 0x0
++#define FAN_TABLE_2__TempMed_MASK 0xffff0000
++#define FAN_TABLE_2__TempMed__SHIFT 0x10
++#define FAN_TABLE_3__Slope2_MASK 0xffff
++#define FAN_TABLE_3__Slope2__SHIFT 0x0
++#define FAN_TABLE_3__Slope1_MASK 0xffff0000
++#define FAN_TABLE_3__Slope1__SHIFT 0x10
++#define FAN_TABLE_4__HystUp_MASK 0xffff
++#define FAN_TABLE_4__HystUp__SHIFT 0x0
++#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
++#define FAN_TABLE_4__FdoMin__SHIFT 0x10
++#define FAN_TABLE_5__HystSlope_MASK 0xffff
++#define FAN_TABLE_5__HystSlope__SHIFT 0x0
++#define FAN_TABLE_5__HystDown_MASK 0xffff0000
++#define FAN_TABLE_5__HystDown__SHIFT 0x10
++#define FAN_TABLE_6__TempCurr_MASK 0xffff
++#define FAN_TABLE_6__TempCurr__SHIFT 0x0
++#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
++#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
++#define FAN_TABLE_7__PwmCurr_MASK 0xffff
++#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
++#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
++#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
++#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
++#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
++#define FAN_TABLE_9__Padding_MASK 0xff
++#define FAN_TABLE_9__Padding__SHIFT 0x0
++#define FAN_TABLE_9__TempSrc_MASK 0xff00
++#define FAN_TABLE_9__TempSrc__SHIFT 0x8
++#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
++#define FAN_TABLE_9__FdoMax__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
++#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
++#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
++#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
++#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
++#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
++#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
++#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0
++#define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff
++#define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0
++#define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff
++#define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0
++#define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00
++#define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8
++#define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000
++#define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10
++#define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000
++#define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18
++#define PM_FUSES_2__TDC_MAWt_MASK 0xff
++#define PM_FUSES_2__TDC_MAWt__SHIFT 0x0
++#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
++#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
++#define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000
++#define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10
++#define PM_FUSES_3__Reserved_MASK 0xff
++#define PM_FUSES_3__Reserved__SHIFT 0x0
++#define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00
++#define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8
++#define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000
++#define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10
++#define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000
++#define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18
++#define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff
++#define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0
++#define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00
++#define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8
++#define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000
++#define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10
++#define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000
++#define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18
++#define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff
++#define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0
++#define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00
++#define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8
++#define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000
++#define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10
++#define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000
++#define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18
++#define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff
++#define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0
++#define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00
++#define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8
++#define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000
++#define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10
++#define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000
++#define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18
++#define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff
++#define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0
++#define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00
++#define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8
++#define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000
++#define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10
++#define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000
++#define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18
++#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
++#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
++#define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
++#define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10
++#define PM_FUSES_9__Reserved6_MASK 0xffff
++#define PM_FUSES_9__Reserved6__SHIFT 0x0
++#define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000
++#define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10
++#define PM_FUSES_10__GnbLPML_3_MASK 0xff
++#define PM_FUSES_10__GnbLPML_3__SHIFT 0x0
++#define PM_FUSES_10__GnbLPML_2_MASK 0xff00
++#define PM_FUSES_10__GnbLPML_2__SHIFT 0x8
++#define PM_FUSES_10__GnbLPML_1_MASK 0xff0000
++#define PM_FUSES_10__GnbLPML_1__SHIFT 0x10
++#define PM_FUSES_10__GnbLPML_0_MASK 0xff000000
++#define PM_FUSES_10__GnbLPML_0__SHIFT 0x18
++#define PM_FUSES_11__GnbLPML_7_MASK 0xff
++#define PM_FUSES_11__GnbLPML_7__SHIFT 0x0
++#define PM_FUSES_11__GnbLPML_6_MASK 0xff00
++#define PM_FUSES_11__GnbLPML_6__SHIFT 0x8
++#define PM_FUSES_11__GnbLPML_5_MASK 0xff0000
++#define PM_FUSES_11__GnbLPML_5__SHIFT 0x10
++#define PM_FUSES_11__GnbLPML_4_MASK 0xff000000
++#define PM_FUSES_11__GnbLPML_4__SHIFT 0x18
++#define PM_FUSES_12__GnbLPML_11_MASK 0xff
++#define PM_FUSES_12__GnbLPML_11__SHIFT 0x0
++#define PM_FUSES_12__GnbLPML_10_MASK 0xff00
++#define PM_FUSES_12__GnbLPML_10__SHIFT 0x8
++#define PM_FUSES_12__GnbLPML_9_MASK 0xff0000
++#define PM_FUSES_12__GnbLPML_9__SHIFT 0x10
++#define PM_FUSES_12__GnbLPML_8_MASK 0xff000000
++#define PM_FUSES_12__GnbLPML_8__SHIFT 0x18
++#define PM_FUSES_13__GnbLPML_15_MASK 0xff
++#define PM_FUSES_13__GnbLPML_15__SHIFT 0x0
++#define PM_FUSES_13__GnbLPML_14_MASK 0xff00
++#define PM_FUSES_13__GnbLPML_14__SHIFT 0x8
++#define PM_FUSES_13__GnbLPML_13_MASK 0xff0000
++#define PM_FUSES_13__GnbLPML_13__SHIFT 0x10
++#define PM_FUSES_13__GnbLPML_12_MASK 0xff000000
++#define PM_FUSES_13__GnbLPML_12__SHIFT 0x18
++#define PM_FUSES_14__Reserved1_1_MASK 0xff
++#define PM_FUSES_14__Reserved1_1__SHIFT 0x0
++#define PM_FUSES_14__Reserved1_0_MASK 0xff00
++#define PM_FUSES_14__Reserved1_0__SHIFT 0x8
++#define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000
++#define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10
++#define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000
++#define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18
++#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff
++#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
++#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
++#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
++#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
++#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
++#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
++#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
++#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
++#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
++#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
++#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
++#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
++#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
++#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
++#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
++#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
++#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
++#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
++#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
++#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
++#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
++#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
++#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
++#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
++#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
++#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
++#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
++#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
++#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
++#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
++#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
++#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
++#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
++#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
++#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
++#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
++#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
++#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
++#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
++#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
++#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
++#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
++#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
++#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
++#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
++#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
++#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
++#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
++#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0
++#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
++#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
++#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
++#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000
++#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
++#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
++#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
++#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
++#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
++#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
++#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
++#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
++#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
++#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
++#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
++#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
++#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
++#define CG_FDO_CTRL1__M_MASK 0xff0000
++#define CG_FDO_CTRL1__M__SHIFT 0x10
++#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
++#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
++#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
++#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
++#define CG_FDO_CTRL2__TMIN_MASK 0xff
++#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
++#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
++#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
++#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
++#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
++#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
++#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
++#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
++#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
++#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
++#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
++#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
++#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
++#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
++#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
++#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
++#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
++#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
++#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
++#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
++#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
++#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
++#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
++#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
++#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
++#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
++#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
++#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
++#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
++#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
++#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
++#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
++#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
++#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
++#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
++#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
++#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
++#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
++#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
++#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
++#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff
++#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
++#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800
++#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
++#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
++#define THM_TMON0_INT_DATA__VALID_MASK 0x800
++#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
++#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
++#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
++#define THM_TMON1_INT_DATA__Z_MASK 0x7ff
++#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
++#define THM_TMON1_INT_DATA__VALID_MASK 0x800
++#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
++#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000
++#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
++#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
++#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
++#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
++#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f
++#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0
++#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5
++#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f
++#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0
++#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20
++#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5
++#define THM_TMON1_STATUS__CURRENT_RDI_MASK 0x1f
++#define THM_TMON1_STATUS__CURRENT_RDI__SHIFT 0x0
++#define THM_TMON1_STATUS__MEAS_DONE_MASK 0x20
++#define THM_TMON1_STATUS__MEAS_DONE__SHIFT 0x5
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
++#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
++#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
++#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
++#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
++#define GENERAL_PWRMGT__SPARE11_MASK 0x800
++#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
++#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
++#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
++#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
++#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
++#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
++#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
++#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
++#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
++#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
++#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
++#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
++#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
++#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
++#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
++#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
++#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
++#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
++#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
++#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1
++#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
++#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff
++#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
++#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
++#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
++#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
++#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
++#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
++#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
++#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
++#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
++#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
++#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
++#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
++#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
++#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
++#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
++#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
++#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
++#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
++#define SCLK_MIN_DIV__FRACV_MASK 0xfff
++#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
++#define SCLK_MIN_DIV__INTV_MASK 0x7f000
++#define SCLK_MIN_DIV__INTV__SHIFT 0xc
++#define PWR_CKS_ENABLE__STRETCH_ENABLE_MASK 0x1
++#define PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT 0x0
++#define PWR_CKS_ENABLE__masterReset_MASK 0x2
++#define PWR_CKS_ENABLE__masterReset__SHIFT 0x1
++#define PWR_CKS_ENABLE__staticEnable_MASK 0x4
++#define PWR_CKS_ENABLE__staticEnable__SHIFT 0x2
++#define PWR_CKS_CNTL__CKS_BYPASS_MASK 0x1
++#define PWR_CKS_CNTL__CKS_BYPASS__SHIFT 0x0
++#define PWR_CKS_CNTL__CKS_PCCEnable_MASK 0x2
++#define PWR_CKS_CNTL__CKS_PCCEnable__SHIFT 0x1
++#define PWR_CKS_CNTL__CKS_TEMP_COMP_MASK 0x4
++#define PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT 0x2
++#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK 0x78
++#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT 0x3
++#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK 0x80
++#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT 0x7
++#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK 0xf00
++#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT 0x8
++#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK 0xf000
++#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT 0xc
++#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK 0x10000
++#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT 0x10
++#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK 0x20000
++#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT 0x11
++#define PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK 0x3c0000
++#define PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT 0x12
++#define PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK 0x400000
++#define PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT 0x16
++#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK 0x7f800000
++#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT 0x17
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000
++#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x4
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80
++#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000
++#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x4
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80
++#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7
++#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff
++#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
++#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
++#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
++#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
++#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
++#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
++#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
++#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
++#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
++#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
++#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
++#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
++#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
++#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
++#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
++#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
++#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
++#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
++#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
++#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
++#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
++#define ROM_STATUS__ROM_BUSY_MASK 0x1
++#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
++#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
++#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
++#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
++#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
++#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
++#define ROM_DATA__ROM_DATA_MASK 0xffffffff
++#define ROM_DATA__ROM_DATA__SHIFT 0x0
++#define ROM_START__ROM_START_MASK 0xffffff
++#define ROM_START__ROM_START__SHIFT 0x0
++#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
++#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
++#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
++#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
++#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
++#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
++#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
++#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
++#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
++#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
++#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
++#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
++
++#endif /* SMU_7_1_2_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0023-yocto-amd-drm-amdgpu-add-SMU-7-0-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0023-yocto-amd-drm-amdgpu-add-SMU-7-0-1-register-headers.patch
new file mode 100644
index 00000000..25fce82a
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0023-yocto-amd-drm-amdgpu-add-SMU-7-0-1-register-headers.patch
@@ -0,0 +1,4739 @@
+From c84648bb88d519b7fc6c8edf2f25de593db29e78 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:32:09 -0400
+Subject: drm/amdgpu: add SMU 8.0 register headers
+
+These are register headers for the SMU (System Management Unit)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h
+new file mode 100644
+index 0000000..b404815
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h
+@@ -0,0 +1,671 @@
++/*
++ * SMU_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_8_0_D_H
++#define SMU_8_0_D_H
++
++#define ixTHM_TCON_CSR_CONFIG                                                   0xd82014a4
++#define ixTHM_TCON_CSR_DATA                                                     0xd82014a8
++#define ixTHM_TCON_HTC                                                          0xd8200c64
++#define ixTHM_TCON_CUR_TMP                                                      0xd8200ca4
++#define ixTHM_TCON_THERM_TRIP                                                   0xd8200ce4
++#define ixTHM_GPIO_PROCHOT_CTRL                                                 0xd8200d00
++#define ixTHM_GPIO_THERMTRIP_CTRL                                               0xd8200d04
++#define ixTHM_THERMAL_INT_ENA                                                   0xd8200d10
++#define ixTHM_THERMAL_INT_CTRL                                                  0xd8200d14
++#define ixTHM_THERMAL_INT_STATUS                                                0xd8200d18
++#define ixTMON0_RDIL0_DATA                                                      0xd8202000
++#define ixTMON0_RDIL1_DATA                                                      0xd8202004
++#define ixTMON0_RDIL2_DATA                                                      0xd8202008
++#define ixTMON0_RDIL3_DATA                                                      0xd820200c
++#define ixTMON0_RDIL4_DATA                                                      0xd8202010
++#define ixTMON0_RDIL5_DATA                                                      0xd8202014
++#define ixTMON0_RDIL6_DATA                                                      0xd8202018
++#define ixTMON0_RDIL7_DATA                                                      0xd820201c
++#define ixTMON0_RDIL8_DATA                                                      0xd8202020
++#define ixTMON0_RDIL9_DATA                                                      0xd8202024
++#define ixTMON0_RDIL10_DATA                                                     0xd8202028
++#define ixTMON0_RDIL11_DATA                                                     0xd820202c
++#define ixTMON0_RDIL12_DATA                                                     0xd8202030
++#define ixTMON0_RDIL13_DATA                                                     0xd8202034
++#define ixTMON0_RDIL14_DATA                                                     0xd8202038
++#define ixTMON0_RDIL15_DATA                                                     0xd820203c
++#define ixTMON0_RDIR0_DATA                                                      0xd8202040
++#define ixTMON0_RDIR1_DATA                                                      0xd8202044
++#define ixTMON0_RDIR2_DATA                                                      0xd8202048
++#define ixTMON0_RDIR3_DATA                                                      0xd820204c
++#define ixTMON0_RDIR4_DATA                                                      0xd8202050
++#define ixTMON0_RDIR5_DATA                                                      0xd8202054
++#define ixTMON0_RDIR6_DATA                                                      0xd8202058
++#define ixTMON0_RDIR7_DATA                                                      0xd820205c
++#define ixTMON0_RDIR8_DATA                                                      0xd8202060
++#define ixTMON0_RDIR9_DATA                                                      0xd8202064
++#define ixTMON0_RDIR10_DATA                                                     0xd8202068
++#define ixTMON0_RDIR11_DATA                                                     0xd820206c
++#define ixTMON0_RDIR12_DATA                                                     0xd8202070
++#define ixTMON0_RDIR13_DATA                                                     0xd8202074
++#define ixTMON0_RDIR14_DATA                                                     0xd8202078
++#define ixTMON0_RDIR15_DATA                                                     0xd820207c
++#define ixTMON0_INT_DATA                                                        0xd8202080
++#define ixTMON0_RDIL_PRESENT0                                                   0xd8202084
++#define ixTMON0_RDIL_PRESENT1                                                   0xd8202088
++#define ixTMON0_RDIR_PRESENT0                                                   0xd820208c
++#define ixTMON0_RDIR_PRESENT1                                                   0xd8202090
++#define ixTMON0_CONFIG                                                          0xd8202098
++#define ixTMON0_TEMP_CALC_COEFF0                                                0xd82020a0
++#define ixTMON0_TEMP_CALC_COEFF1                                                0xd82020a4
++#define ixTMON0_TEMP_CALC_COEFF2                                                0xd82020a8
++#define ixTMON0_TEMP_CALC_COEFF3                                                0xd82020ac
++#define ixTMON0_TEMP_CALC_COEFF4                                                0xd82020b0
++#define ixTMON0_DEBUG0                                                          0xd82020b4
++#define ixTMON0_DEBUG1                                                          0xd82020b8
++#define ixTMON1_RDIL0_DATA                                                      0xd8202100
++#define ixTMON1_RDIL1_DATA                                                      0xd8202104
++#define ixTMON1_RDIL2_DATA                                                      0xd8202108
++#define ixTMON1_RDIL3_DATA                                                      0xd820210c
++#define ixTMON1_RDIL4_DATA                                                      0xd8202110
++#define ixTMON1_RDIL5_DATA                                                      0xd8202114
++#define ixTMON1_RDIL6_DATA                                                      0xd8202118
++#define ixTMON1_RDIL7_DATA                                                      0xd820211c
++#define ixTMON1_RDIL8_DATA                                                      0xd8202120
++#define ixTMON1_RDIL9_DATA                                                      0xd8202124
++#define ixTMON1_RDIL10_DATA                                                     0xd8202128
++#define ixTMON1_RDIL11_DATA                                                     0xd820212c
++#define ixTMON1_RDIL12_DATA                                                     0xd8202130
++#define ixTMON1_RDIL13_DATA                                                     0xd8202134
++#define ixTMON1_RDIL14_DATA                                                     0xd8202138
++#define ixTMON1_RDIL15_DATA                                                     0xd820213c
++#define ixTMON1_RDIR0_DATA                                                      0xd8202140
++#define ixTMON1_RDIR1_DATA                                                      0xd8202144
++#define ixTMON1_RDIR2_DATA                                                      0xd8202148
++#define ixTMON1_RDIR3_DATA                                                      0xd820214c
++#define ixTMON1_RDIR4_DATA                                                      0xd8202150
++#define ixTMON1_RDIR5_DATA                                                      0xd8202154
++#define ixTMON1_RDIR6_DATA                                                      0xd8202158
++#define ixTMON1_RDIR7_DATA                                                      0xd820215c
++#define ixTMON1_RDIR8_DATA                                                      0xd8202160
++#define ixTMON1_RDIR9_DATA                                                      0xd8202164
++#define ixTMON1_RDIR10_DATA                                                     0xd8202168
++#define ixTMON1_RDIR11_DATA                                                     0xd820216c
++#define ixTMON1_RDIR12_DATA                                                     0xd8202170
++#define ixTMON1_RDIR13_DATA                                                     0xd8202174
++#define ixTMON1_RDIR14_DATA                                                     0xd8202178
++#define ixTMON1_RDIR15_DATA                                                     0xd820217c
++#define ixTMON1_INT_DATA                                                        0xd8202180
++#define ixTMON1_RDIL_PRESENT0                                                   0xd8202184
++#define ixTMON1_RDIL_PRESENT1                                                   0xd8202188
++#define ixTMON1_RDIR_PRESENT0                                                   0xd820218c
++#define ixTMON1_RDIR_PRESENT1                                                   0xd8202190
++#define ixTMON1_CONFIG                                                          0xd8202198
++#define ixTMON1_TEMP_CALC_COEFF0                                                0xd82021a0
++#define ixTMON1_TEMP_CALC_COEFF1                                                0xd82021a4
++#define ixTMON1_TEMP_CALC_COEFF2                                                0xd82021a8
++#define ixTMON1_TEMP_CALC_COEFF3                                                0xd82021ac
++#define ixTMON1_TEMP_CALC_COEFF4                                                0xd82021b0
++#define ixTMON1_DEBUG0                                                          0xd82021b4
++#define ixTMON1_DEBUG1                                                          0xd82021b8
++#define ixTHM_TMON0_REMOTE_START                                                0xd8202800
++#define ixTHM_TMON0_REMOTE_END                                                  0xd82028fc
++#define ixTHM_TMON1_REMOTE_START                                                0xd8202900
++#define ixTHM_TMON1_REMOTE_END                                                  0xd82029fc
++#define ixTHM_TCON_LOCAL0                                                       0xd8202e00
++#define ixTHM_TCON_LOCAL1                                                       0xd8202e04
++#define ixTHM_TCON_LOCAL2                                                       0xd8202e08
++#define ixTHM_TCON_LOCAL3                                                       0xd8202e0c
++#define ixTHM_TCON_LOCAL4                                                       0xd8202e10
++#define ixTHM_TCON_LOCAL5                                                       0xd8202e14
++#define ixTHM_TCON_LOCAL6                                                       0xd8202e18
++#define ixTHM_TCON_LOCAL7                                                       0xd8202e1c
++#define ixTHM_TCON_LOCAL8                                                       0xd8202e20
++#define ixTHM_TCON_LOCAL9                                                       0xd8202e24
++#define ixTHM_TCON_LOCAL10                                                      0xd8202e28
++#define ixTHM_TCON_LOCAL11                                                      0xd8202e2c
++#define ixTHM_TCON_LOCAL12                                                      0xd8202e30
++#define ixTHM_TCON_LOCAL13                                                      0xd8202ef8
++#define ixTHM_TCON_LOCAL14                                                      0xd8202efc
++#define ixTHM_FUSE0                                                             0xd8210000
++#define ixTHM_FUSE1                                                             0xd8210004
++#define ixTHM_FUSE2                                                             0xd8210008
++#define ixTHM_FUSE3                                                             0xd821000c
++#define ixTHM_FUSE4                                                             0xd8210010
++#define ixTHM_FUSE5                                                             0xd8210014
++#define ixTHM_FUSE6                                                             0xd8210018
++#define ixTHM_FUSE7                                                             0xd821001c
++#define ixTHM_FUSE8                                                             0xd8210020
++#define ixTHM_FUSE9                                                             0xd8210024
++#define ixTHM_FUSE10                                                            0xd8210028
++#define ixTHM_FUSE11                                                            0xd821002c
++#define ixTHM_FUSE12                                                            0xd8210030
++#define mmMP0PUB_IND_INDEX                                                      0x180
++#define mmMP_SMUIF0_MP0PUB_IND_INDEX                                            0x180
++#define mmMP_SMUIF1_MP0PUB_IND_INDEX                                            0x182
++#define mmMP_SMUIF2_MP0PUB_IND_INDEX                                            0x184
++#define mmMP_SMUIF3_MP0PUB_IND_INDEX                                            0x186
++#define mmMP_SMUIF4_MP0PUB_IND_INDEX                                            0x188
++#define mmMP_SMUIF5_MP0PUB_IND_INDEX                                            0x18a
++#define mmMP_SMUIF6_MP0PUB_IND_INDEX                                            0x18c
++#define mmMP_SMUIF7_MP0PUB_IND_INDEX                                            0x18e
++#define mmMP_SMUIF8_MP0PUB_IND_INDEX                                            0x190
++#define mmMP_SMUIF9_MP0PUB_IND_INDEX                                            0x192
++#define mmMP_SMUIF10_MP0PUB_IND_INDEX                                           0x194
++#define mmMP_SMUIF11_MP0PUB_IND_INDEX                                           0x196
++#define mmMP_SMUIF12_MP0PUB_IND_INDEX                                           0x198
++#define mmMP_SMUIF13_MP0PUB_IND_INDEX                                           0x19a
++#define mmMP_SMUIF14_MP0PUB_IND_INDEX                                           0x19c
++#define mmMP_SMUIF15_MP0PUB_IND_INDEX                                           0x19e
++#define mmMP0PUB_IND_DATA                                                       0x181
++#define mmMP_SMUIF0_MP0PUB_IND_DATA                                             0x181
++#define mmMP_SMUIF1_MP0PUB_IND_DATA                                             0x183
++#define mmMP_SMUIF2_MP0PUB_IND_DATA                                             0x185
++#define mmMP_SMUIF3_MP0PUB_IND_DATA                                             0x187
++#define mmMP_SMUIF4_MP0PUB_IND_DATA                                             0x189
++#define mmMP_SMUIF5_MP0PUB_IND_DATA                                             0x18b
++#define mmMP_SMUIF6_MP0PUB_IND_DATA                                             0x18d
++#define mmMP_SMUIF7_MP0PUB_IND_DATA                                             0x18f
++#define mmMP_SMUIF8_MP0PUB_IND_DATA                                             0x191
++#define mmMP_SMUIF9_MP0PUB_IND_DATA                                             0x193
++#define mmMP_SMUIF10_MP0PUB_IND_DATA                                            0x195
++#define mmMP_SMUIF11_MP0PUB_IND_DATA                                            0x197
++#define mmMP_SMUIF12_MP0PUB_IND_DATA                                            0x199
++#define mmMP_SMUIF13_MP0PUB_IND_DATA                                            0x19b
++#define mmMP_SMUIF14_MP0PUB_IND_DATA                                            0x19d
++#define mmMP_SMUIF15_MP0PUB_IND_DATA                                            0x19f
++#define mmMP0PUB_IND_INDEX_0                                                    0x180
++#define mmMP0PUB_IND_DATA_0                                                     0x181
++#define mmMP0PUB_IND_INDEX_1                                                    0x182
++#define mmMP0PUB_IND_DATA_1                                                     0x183
++#define mmMP0PUB_IND_INDEX_2                                                    0x184
++#define mmMP0PUB_IND_DATA_2                                                     0x185
++#define mmMP0PUB_IND_INDEX_3                                                    0x186
++#define mmMP0PUB_IND_DATA_3                                                     0x187
++#define mmMP0PUB_IND_INDEX_4                                                    0x188
++#define mmMP0PUB_IND_DATA_4                                                     0x189
++#define mmMP0PUB_IND_INDEX_5                                                    0x18a
++#define mmMP0PUB_IND_DATA_5                                                     0x18b
++#define mmMP0PUB_IND_INDEX_6                                                    0x18c
++#define mmMP0PUB_IND_DATA_6                                                     0x18d
++#define mmMP0PUB_IND_INDEX_7                                                    0x18e
++#define mmMP0PUB_IND_DATA_7                                                     0x18f
++#define mmMP0PUB_IND_INDEX_8                                                    0x190
++#define mmMP0PUB_IND_DATA_8                                                     0x191
++#define mmMP0PUB_IND_INDEX_9                                                    0x192
++#define mmMP0PUB_IND_DATA_9                                                     0x193
++#define mmMP0PUB_IND_INDEX_10                                                   0x194
++#define mmMP0PUB_IND_DATA_10                                                    0x195
++#define mmMP0PUB_IND_INDEX_11                                                   0x196
++#define mmMP0PUB_IND_DATA_11                                                    0x197
++#define mmMP0PUB_IND_INDEX_12                                                   0x198
++#define mmMP0PUB_IND_DATA_12                                                    0x199
++#define mmMP0PUB_IND_INDEX_13                                                   0x19a
++#define mmMP0PUB_IND_DATA_13                                                    0x19b
++#define mmMP0PUB_IND_INDEX_14                                                   0x19c
++#define mmMP0PUB_IND_DATA_14                                                    0x19d
++#define mmMP0PUB_IND_INDEX_15                                                   0x19e
++#define mmMP0PUB_IND_DATA_15                                                    0x19f
++#define mmMP0_IND_ACCESS_CNTL                                                   0x1a0
++#define mmMP0_MSP_MESSAGE_0                                                     0x1a1
++#define mmMP0_MSP_MESSAGE_1                                                     0x1a2
++#define mmMP0_MSP_MESSAGE_2                                                     0x1a3
++#define mmMP0_MSP_MESSAGE_3                                                     0x1a4
++#define mmMP0_MSP_MESSAGE_4                                                     0x1a5
++#define mmMP0_MSP_MESSAGE_5                                                     0x1a6
++#define mmMP0_MSP_MESSAGE_6                                                     0x1a7
++#define mmMP0_MSP_MESSAGE_7                                                     0x1a8
++#define mmSAM_IH_EXT_ERR_INTR                                                   0x1a9
++#define mmSAM_IH_EXT_ERR_INTR_STATUS                                            0x1aa
++#define mmMP0_DISP_TIMER0_CTRL0                                                 0x1ab
++#define mmMP0_DISP_TIMER0_CTRL1                                                 0x1ac
++#define mmMP0_DISP_TIMER0_CMP_AUTOINC                                           0x1ad
++#define mmMP0_DISP_TIMER0_INTEN                                                 0x1ae
++#define mmMP0_DISP_TIMER0_OCMP_0_0                                              0x1af
++#define mmMP0_DISP_TIMER0_OCMP_0_1                                              0x1b0
++#define mmMP0_DISP_TIMER0_CNT                                                   0x1b1
++#define mmMP0_DISP_TIMER1_CTRL0                                                 0x1b2
++#define mmMP0_DISP_TIMER1_CTRL1                                                 0x1b3
++#define mmMP0_DISP_TIMER1_CMP_AUTOINC                                           0x1b4
++#define mmMP0_DISP_TIMER1_INTEN                                                 0x1b5
++#define mmMP0_DISP_TIMER1_OCMP_0_0                                              0x1b6
++#define mmMP0_DISP_TIMER1_OCMP_0_1                                              0x1b7
++#define mmMP0_DISP_TIMER1_CNT                                                   0x1b8
++#define mmSMU_MP1_SRBM2P_MSG_0                                                  0x1c0
++#define mmSMU_MP1_SRBM2P_MSG_1                                                  0x1c1
++#define mmSMU_MP1_SRBM2P_MSG_2                                                  0x1c2
++#define mmSMU_MP1_SRBM2P_MSG_3                                                  0x1c3
++#define mmSMU_MP1_SRBM2P_MSG_4                                                  0x1c4
++#define mmSMU_MP1_SRBM2P_MSG_5                                                  0x1c5
++#define mmSMU_MP1_SRBM2P_MSG_6                                                  0x1c6
++#define mmSMU_MP1_SRBM2P_MSG_7                                                  0x1c7
++#define mmSMU_MP1_SRBM2P_MSG_8                                                  0x1c8
++#define mmSMU_MP1_SRBM2P_MSG_9                                                  0x1c9
++#define mmSMU_MP1_SRBM2P_MSG_10                                                 0x1ca
++#define mmSMU_MP1_SRBM2P_MSG_11                                                 0x1cb
++#define mmSMU_MP1_SRBM2P_MSG_12                                                 0x1cc
++#define mmSMU_MP1_SRBM2P_MSG_13                                                 0x1cd
++#define mmSMU_MP1_SRBM2P_MSG_14                                                 0x1ce
++#define mmSMU_MP1_SRBM2P_MSG_15                                                 0x1cf
++#define mmSMU_MP1_SRBM2P_RESP_0                                                 0x1d0
++#define mmSMU_MP1_SRBM2P_RESP_1                                                 0x1d1
++#define mmSMU_MP1_SRBM2P_RESP_2                                                 0x1d2
++#define mmSMU_MP1_SRBM2P_RESP_3                                                 0x1d3
++#define mmSMU_MP1_SRBM2P_RESP_4                                                 0x1d4
++#define mmSMU_MP1_SRBM2P_RESP_5                                                 0x1d5
++#define mmSMU_MP1_SRBM2P_RESP_6                                                 0x1d6
++#define mmSMU_MP1_SRBM2P_RESP_7                                                 0x1d7
++#define mmSMU_MP1_SRBM2P_RESP_8                                                 0x1d8
++#define mmSMU_MP1_SRBM2P_RESP_9                                                 0x1d9
++#define mmSMU_MP1_SRBM2P_RESP_10                                                0x1da
++#define mmSMU_MP1_SRBM2P_RESP_11                                                0x1db
++#define mmSMU_MP1_SRBM2P_RESP_12                                                0x1dc
++#define mmSMU_MP1_SRBM2P_RESP_13                                                0x1dd
++#define mmSMU_MP1_SRBM2P_RESP_14                                                0x1de
++#define mmSMU_MP1_SRBM2P_RESP_15                                                0x1df
++#define mmSMU_MP1_SRBM2P_ARG_0                                                  0x1e0
++#define mmSMU_MP1_SRBM2P_ARG_1                                                  0x1e1
++#define mmSMU_MP1_SRBM2P_ARG_2                                                  0x1e2
++#define mmSMU_MP1_SRBM2P_ARG_3                                                  0x1e3
++#define mmSMU_MP1_SRBM2P_ARG_4                                                  0x1e4
++#define mmSMU_MP1_SRBM2P_ARG_5                                                  0x1e5
++#define mmSMU_MP1_SRBM2P_ARG_6                                                  0x1e6
++#define mmSMU_MP1_SRBM2P_ARG_7                                                  0x1e7
++#define mmSMU_MP1_SRBM2P_ARG_8                                                  0x1e8
++#define mmSMU_MP1_SRBM2P_ARG_9                                                  0x1e9
++#define mmSMU_MP1_SRBM2P_ARG_10                                                 0x1ea
++#define mmSMU_MP1_SRBM2P_ARG_11                                                 0x1eb
++#define mmSMU_MP1_SRBM2P_ARG_12                                                 0x1ec
++#define mmSMU_MP1_SRBM2P_ARG_13                                                 0x1ed
++#define mmSMU_MP1_SRBM2P_ARG_14                                                 0x1ee
++#define mmSMU_MP1_SRBM2P_ARG_15                                                 0x1ef
++#define mmSMU_MP1_ACP2MP_RESP                                                   0x1f0
++#define mmSMU_MP1_DC2MP_RESP                                                    0x1f1
++#define mmSMU_MP1_UVD2MP_RESP                                                   0x1f2
++#define mmSMU_MP1_VCE2MP_RESP                                                   0x1f3
++#define mmSMU_MP1_RLC2MP_RESP                                                   0x1f4
++#define mmMP_FPS_CNT                                                            0x1f5
++#define mmSMU_DISP0_TIMER_INT_CONTROL                                           0x1f6
++#define mmSMU_DISP1_TIMER_INT_CONTROL                                           0x1f7
++#define mmSMU_SRBM_CONFIG                                                       0x1f8
++#define ixMP_FPS_CNT_XBAR                                                       0xcf200800
++#define ixMP_SRBM_CONFIG_XBAR                                                   0xcf200804
++#define ixMP_SRBM_CONTROL                                                       0xcf200c00
++#define ixMP_SRBM_ACCVIO_LOG                                                    0xcf200c04
++#define ixMP_SRBM_ACCVIO_ADDR                                                   0xcf200c08
++#define ixMP_CRBBM_CONTROL                                                      0xcf200c0c
++#define ixMP_CRBBM_ACCVIO_LOG                                                   0xcf200c10
++#define ixMP_CRBBM_ACCVIO_ADDR                                                  0xcf200c14
++#define ixMP_DRAM_CNTL_WRREQ_CNTL                                               0xcf200000
++#define ixMP_DRAM_CNTL_WRREQ_CNTL_1                                             0xcf200004
++#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR                                           0xcf200008
++#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR                                          0xcf20000c
++#define ixMP_DRAM_CNTL_WRREQ_MASK                                               0xcf200010
++#define ixMP_DRAM_CNTL_WRREQ_DATA_0                                             0xcf200014
++#define ixMP_DRAM_CNTL_WRREQ_DATA_1                                             0xcf200018
++#define ixMP_DRAM_CNTL_WRREQ_DATA_2                                             0xcf20001c
++#define ixMP_DRAM_CNTL_WRREQ_DATA_3                                             0xcf200020
++#define ixMP_DRAM_CNTL_WRREQ_DATA_4                                             0xcf200024
++#define ixMP_DRAM_CNTL_WRREQ_DATA_5                                             0xcf200028
++#define ixMP_DRAM_CNTL_WRREQ_DATA_6                                             0xcf20002c
++#define ixMP_DRAM_CNTL_WRREQ_DATA_7                                             0xcf200030
++#define ixMP_DRAM_CNTL_WRREQ_STATUS                                             0xcf200038
++#define ixMP_DRAM_CNTL_WRRET_STATUS_0                                           0xcf20003c
++#define ixMP_DRAM_CNTL_RDREQ_ADDR                                               0xcf200040
++#define ixMP_DRAM_CNTL_RDREQ_CNTL                                               0xcf200044
++#define ixMP_DRAM_CNTL_RDREQ_CNTL_1                                             0xcf200048
++#define ixMP_DRAM_CNTL_RDRET_VALID                                              0xcf20004c
++#define ixMP_DRAM_CNTL_RDRET_NACK                                               0xcf200050
++#define ixMP_DRAM_CNTL_RDRET_DATA_0                                             0xcf200054
++#define ixMP_DRAM_CNTL_RDRET_DATA_1                                             0xcf200058
++#define ixMP_DRAM_CNTL_RDRET_DATA_2                                             0xcf20005c
++#define ixMP_DRAM_CNTL_RDRET_DATA_3                                             0xcf200060
++#define ixMP_DRAM_CNTL_RDRET_DATA_4                                             0xcf200064
++#define ixMP_DRAM_CNTL_RDRET_DATA_5                                             0xcf200068
++#define ixMP_DRAM_CNTL_RDRET_DATA_6                                             0xcf20006c
++#define ixMP_DRAM_CNTL_RDRET_DATA_7                                             0xcf200070
++#define ixMP_DRAM_CNTL_RDRET_DATA_8                                             0xcf200074
++#define ixMP_DRAM_CNTL_RDRET_DATA_9                                             0xcf200078
++#define ixMP_DRAM_CNTL_RDRET_DATA_10                                            0xcf20007c
++#define ixMP_DRAM_CNTL_RDRET_DATA_11                                            0xcf200080
++#define ixMP_DRAM_CNTL_RDRET_DATA_12                                            0xcf200084
++#define ixMP_DRAM_CNTL_RDRET_DATA_13                                            0xcf200088
++#define ixMP_DRAM_CNTL_RDRET_DATA_14                                            0xcf20008c
++#define ixMP_DRAM_CNTL_RDRET_DATA_15                                            0xcf200090
++#define ixMP_DRAM_CNTL_RDRET_DATA_16                                            0xcf200094
++#define ixMP_DRAM_CNTL_RDRET_DATA_17                                            0xcf200098
++#define ixMP_DRAM_CNTL_RDRET_DATA_18                                            0xcf20009c
++#define ixMP_DRAM_CNTL_RDRET_DATA_19                                            0xcf2000a0
++#define ixMP_DRAM_CNTL_RDRET_DATA_20                                            0xcf2000a4
++#define ixMP_DRAM_CNTL_RDRET_DATA_21                                            0xcf2000a8
++#define ixMP_DRAM_CNTL_RDRET_DATA_22                                            0xcf2000ac
++#define ixMP_DRAM_CNTL_RDRET_DATA_23                                            0xcf2000b0
++#define ixMP_DRAM_CNTL_RDRET_DATA_24                                            0xcf2000b4
++#define ixMP_DRAM_CNTL_RDRET_DATA_25                                            0xcf2000b8
++#define ixMP_DRAM_CNTL_RDRET_DATA_26                                            0xcf2000bc
++#define ixMP_DRAM_CNTL_RDRET_DATA_27                                            0xcf2000c0
++#define ixMP_DRAM_CNTL_RDRET_DATA_28                                            0xcf2000c4
++#define ixMP_DRAM_CNTL_RDRET_DATA_29                                            0xcf2000c8
++#define ixMP_DRAM_CNTL_RDRET_DATA_30                                            0xcf2000cc
++#define ixMP_DRAM_CNTL_RDRET_DATA_31                                            0xcf2000d0
++#define ixMP_DRAM_CNTL_RDRET_DATA_32                                            0xcf2000d4
++#define ixMP_DRAM_CNTL_RDRET_DATA_33                                            0xcf2000d8
++#define ixMP_DRAM_CNTL_RDRET_DATA_34                                            0xcf2000dc
++#define ixMP_DRAM_CNTL_RDRET_DATA_35                                            0xcf2000e0
++#define ixMP_DRAM_CNTL_RDRET_DATA_36                                            0xcf2000e4
++#define ixMP_DRAM_CNTL_RDRET_DATA_37                                            0xcf2000e8
++#define ixMP_DRAM_CNTL_RDRET_DATA_38                                            0xcf2000ec
++#define ixMP_DRAM_CNTL_RDRET_DATA_39                                            0xcf2000f0
++#define ixMP_DRAM_CNTL_RDRET_DATA_40                                            0xcf2000f4
++#define ixMP_DRAM_CNTL_RDRET_DATA_41                                            0xcf2000f8
++#define ixMP_DRAM_CNTL_RDRET_DATA_42                                            0xcf2000fc
++#define ixMP_DRAM_CNTL_RDRET_DATA_43                                            0xcf200100
++#define ixMP_DRAM_CNTL_RDRET_DATA_44                                            0xcf200104
++#define ixMP_DRAM_CNTL_RDRET_DATA_45                                            0xcf200108
++#define ixMP_DRAM_CNTL_RDRET_DATA_46                                            0xcf20010c
++#define ixMP_DRAM_CNTL_RDRET_DATA_47                                            0xcf200110
++#define ixMP_DRAM_CNTL_RDRET_DATA_48                                            0xcf200114
++#define ixMP_DRAM_CNTL_RDRET_DATA_49                                            0xcf200118
++#define ixMP_DRAM_CNTL_RDRET_DATA_50                                            0xcf20011c
++#define ixMP_DRAM_CNTL_RDRET_DATA_51                                            0xcf200120
++#define ixMP_DRAM_CNTL_RDRET_DATA_52                                            0xcf200124
++#define ixMP_DRAM_CNTL_RDRET_DATA_53                                            0xcf200128
++#define ixMP_DRAM_CNTL_RDRET_DATA_54                                            0xcf20012c
++#define ixMP_DRAM_CNTL_RDRET_DATA_55                                            0xcf200130
++#define ixMP_DRAM_CNTL_RDRET_DATA_56                                            0xcf200134
++#define ixMP_DRAM_CNTL_RDRET_DATA_57                                            0xcf200138
++#define ixMP_DRAM_CNTL_RDRET_DATA_58                                            0xcf20013c
++#define ixMP_DRAM_CNTL_RDRET_DATA_59                                            0xcf200140
++#define ixMP_DRAM_CNTL_RDRET_DATA_60                                            0xcf200144
++#define ixMP_DRAM_CNTL_RDRET_DATA_61                                            0xcf200148
++#define ixMP_DRAM_CNTL_RDRET_DATA_62                                            0xcf20014c
++#define ixMP_DRAM_CNTL_RDRET_DATA_63                                            0xcf200150
++#define ixMP_IOC_CTRL                                                           0xcf100000
++#define ixMP_IOC_RDDATA                                                         0xcf100004
++#define ixMP_IOC_PHASE1                                                         0xcf100008
++#define ixMP_IOC_PHASE2                                                         0xcf10000c
++#define ixMP_IOC_PHASE3                                                         0xcf100010
++#define ixMP_IOC_READ_0                                                         0xcf100024
++#define ixMP_IOC_READ_1                                                         0xcf100028
++#define ixMP_IOC_READ_2                                                         0xcf10002c
++#define ixMP_IOC_READ_3                                                         0xcf100030
++#define ixMP_IOC_READ_4                                                         0xcf100034
++#define ixMP_IOC_READ_5                                                         0xcf100038
++#define ixMP_IOC_READ_6                                                         0xcf10003c
++#define ixMP_IOC_READ_7                                                         0xcf100040
++#define ixMP_IOC_READ_8                                                         0xcf100044
++#define ixMP_IOC_READ_9                                                         0xcf100048
++#define ixMP_IOC_READ_10                                                        0xcf10004c
++#define ixMP_IOC_READ_11                                                        0xcf100050
++#define ixMP_IOC_READ_12                                                        0xcf100054
++#define ixMP_IOC_READ_13                                                        0xcf100058
++#define ixMP_IOC_READ_14                                                        0xcf10005c
++#define ixMP_IOC_READ_15                                                        0xcf100060
++#define ixMP_IOC_WRITE_0                                                        0xcf100064
++#define ixMP_IOC_WRITE_1                                                        0xcf100068
++#define ixMP_IOC_WRITE_2                                                        0xcf10006c
++#define ixMP_IOC_WRITE_3                                                        0xcf100070
++#define ixMP_IOC_WRITE_4                                                        0xcf100074
++#define ixMP_IOC_WRITE_5                                                        0xcf100078
++#define ixMP_IOC_WRITE_6                                                        0xcf10007c
++#define ixMP_IOC_WRITE_7                                                        0xcf100080
++#define ixMP_IOC_WRITE_8                                                        0xcf100084
++#define ixMP_IOC_WRITE_9                                                        0xcf100088
++#define ixMP_IOC_WRITE_10                                                       0xcf10008c
++#define ixMP_IOC_WRITE_11                                                       0xcf100090
++#define ixMP_IOC_WRITE_12                                                       0xcf100094
++#define ixMP_IOC_WRITE_13                                                       0xcf100098
++#define ixMP_IOC_WRITE_14                                                       0xcf10009c
++#define ixMP_IOC_WRITE_15                                                       0xcf1000a0
++#define ixMP_INTERRUPT_CONTROL                                                  0xcf200400
++#define ixMP0_SW_INT                                                            0xcf200404
++#define ixMP0_SW_INT_CTXID                                                      0xcf200408
++#define ixMP1_SW_INT                                                            0xcf20040c
++#define ixMP1_SW_INT_CTXID                                                      0xcf200410
++#define ixDISP_TIMER_ID                                                         0xcf200414
++#define mmPWRHW_SMC_IND_INDEX                                                   0x180
++#define mmPWRHW0_PWRHW_SMC_IND_INDEX                                            0x180
++#define mmPWRHW1_PWRHW_SMC_IND_INDEX                                            0x182
++#define mmPWRHW2_PWRHW_SMC_IND_INDEX                                            0x184
++#define mmPWRHW3_PWRHW_SMC_IND_INDEX                                            0x186
++#define mmPWRHW_SMC_IND_DATA                                                    0x181
++#define mmPWRHW0_PWRHW_SMC_IND_DATA                                             0x181
++#define mmPWRHW1_PWRHW_SMC_IND_DATA                                             0x183
++#define mmPWRHW2_PWRHW_SMC_IND_DATA                                             0x185
++#define mmPWRHW3_PWRHW_SMC_IND_DATA                                             0x187
++#define ixCURRENT_STATE_CPU0                                                    0xd0210000
++#define ixCURRENT_STATE_CPU1                                                    0xd0210010
++#define ixCPU_REDUN_DONE0                                                       0xd0210004
++#define ixCPU_REDUN_DONE1                                                       0xd0210014
++#define ixCURRENT_VID_CPU0                                                      0xd0210008
++#define ixCURRENT_VID_CPU1                                                      0xd0210018
++#define ixUNBPM_PWRMGT_ACK                                                      0xd0211000
++#define ixCURRENT_FREQ_STATE_NB                                                 0xd0211004
++#define ixCURRENT_PSTATE_NB                                                     0xd0211008
++#define ixUNBPM_MSG_INT_CONFIG                                                  0xd021100c
++#define ixUNBPM_NBPWRMGT_CMD                                                    0xd0211010
++#define ixUNBPM_NBPWRMGT_FSM_CFG                                                0xd0211014
++#define ixDDR0_FUSE_SSB_XFER                                                    0xd0211018
++#define ixDDR0_FUSE_SSB_XFER_CFG                                                0xd021101c
++#define ixDDR1_FUSE_SSB_XFER                                                    0xd0211020
++#define ixDDR1_FUSE_SSB_XFER_CFG                                                0xd0211024
++#define ixUNBPM_FUSES_VAL_PWROK                                                 0xd0211028
++#define ixSYNFIFO_CLK_RATIO                                                     0xd021102c
++#define ixMISC_SMU_PWRMGT_CFG0                                                  0xd0211030
++#define ixMISC_GNB_PWRMGT_CFG1                                                  0xd0211034
++#define ixMISC_SMU_PWRMGT_CFG1                                                  0xd0211038
++#define ixMISC_GNB_PWRMGT_DATA                                                  0xd021103c
++#define ixGN_GNB_SLOW                                                           0xd0211040
++#define ixGN_FORCE_NBPS1                                                        0xd0211044
++#define ixMISC_SMU_PWRMGT_DATA                                                  0xd0211048
++#define ixNB_COF                                                                0xd021104c
++#define ixUNBPM_CK_IRESET                                                       0xd0211050
++#define ixCURRENT_VID_NB                                                        0xd0211054
++#define ixSPR_FUSE_PSTATEPWR1                                                   0xd0211058
++#define ixSPR_FUSE_PSTATEPWR2                                                   0xd021105c
++#define ixSPR_FUSE_PSTATEPWR3                                                   0xd0211060
++#define ixSPR_FUSE_THERMAL_SCRATCH                                              0xd0211064
++#define ixSPR_PRODUCT_INFO0                                                     0xd0211068
++#define ixSPR_SERIALNUM_REG1                                                    0xd021106c
++#define ixSPR_SERIALNUM_REG2                                                    0xd0211070
++#define ixSPR_PRODUCT_INFO1                                                     0xd0211074
++#define ixSPR_EXT_PRODUCT_INFO                                                  0xd021107c
++#define ixSPR_MSIDFUSE                                                          0xd0211080
++#define ixSPR_LINK_PRODUCT_INFO                                                 0xd0211084
++#define ixSPR_BRAND_NAME_ADDR                                                   0xd0211088
++#define ixSPR_BRAND_NAME_DATA                                                   0xd021108c
++#define ixSPR_COMBO_PHY_PRODUCT_INFO                                            0xd0211090
++#define ixMISC_GNB_PWRMGT_CFG0                                                  0xd0211094
++#define ixUNBPM_EXIT_TO_PSTATE                                                  0xd0211098
++#define ixUNBPM_WARM_RESET_HS_STATUS                                            0xd021109c
++#define ixUNBPM_VOLTAGE_CNTL                                                    0xd02110a0
++#define ixUNBPM_VOLTAGE_STATUS                                                  0xd02110a4
++#define ixNUM_BOOST_STATES                                                      0xd02110a8
++#define ixWARM_RESET_NB_CONTROL                                                 0xd02110ac
++#define ixONION_NO_STREAMS_PEND                                                 0xd02110b0
++#define ixSPR_PROGRAMMABLE_CTRL                                                 0xd02110b4
++#define ixPHN_FUSERX_MISC_FUSES                                                 0xd02110b8
++#define ixUNBPM_PWRCTRL_MISC                                                    0xd02110bc
++#define ixCSTATE_ACTIVE_SAMPLER                                                 0xd02110c0
++#define ixUNBPM_DEBUG_CONFIG_STATUS                                             0xd02110c4
++#define ixUNBPM_AXIMST_LAST_CMD                                                 0xd02110c8
++#define ixUNB_IF_INTRGEN_LAST_SENT                                              0xd02110cc
++#define ixUNBPM_DEBUG_BUS_CNTL                                                  0xd02110d0
++#define ixUNBPM_PWRMGT_REQ_DBG_STATUS                                           0xd02110d4
++#define ixUNBPM_VIDCHG_REQ_DBG_STATUS                                           0xd02110d8
++#define ixUNBPM_SCRATCH_0                                                       0xd021e000
++#define ixUNBPM_SCRATCH_1                                                       0xd021e004
++#define ixPOWERON_CPU_0                                                         0xd0220000
++#define ixPOWERREADY_CPU_0                                                      0xd0220004
++#define ixPGRUNFEEDBACK_CPU_0                                                   0xd0220008
++#define ixRCC3ON_CPU_0                                                          0xd022000c
++#define ixRCC3EXITDONE_CPU_0                                                    0xd0220010
++#define ixCORE_FUNC_LATE_SSB_XFER_0                                             0xd0220014
++#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0                                         0xd0220018
++#define ixCORE_REDUN_SSB_XFER_0                                                 0xd022001c
++#define ixCORE_REDUN_SSB_XFER_CFG_0                                             0xd0220020
++#define ixCORE_APM_SSB_XFER_0                                                   0xd0220024
++#define ixCORE_APM_SSB_XFER_CFG_0                                               0xd0220028
++#define ixCOREPM_PWRCTRL_MISC_0                                                 0xd022002c
++#define ixLDOIVRON_CPU_0                                                        0xd0220030
++#define ixLDOIVREXITDONE_CPU_0                                                  0xd0220034
++#define ixRCC3_TARGETPSMREF_CPU_0                                               0xd0220038
++#define ixIVR_TARGETPSMREF_CPU_0                                                0xd022003c
++#define ixCK_JTCOOLRESET_LATCHED_CPU_0                                          0xd0220044
++#define ixCK_DISABLECORE_CPU_0                                                  0xd0220048
++#define ixCOREPM_ID_0                                                           0xd022004c
++#define ixCOREPM_SCRATCH_0                                                      0xd0220050
++#define ixRCC3_WAKEMIN_CPU_0                                                    0xd0220054
++#define ixSPMI_CONFIG0_0                                                        0xd0221000
++#define ixSPMI_CONFIG1_0                                                        0xd0221004
++#define ixSPMI_FSM_READ_TRIGGER_0                                               0xd0221008
++#define ixSPMI_FSM_WRITE_TRIGGER_0                                              0xd022100c
++#define ixSPMI_FSM_RESET_TRIGGER_0                                              0xd0221010
++#define ixSPMI_FSM_BUSY_0                                                       0xd0221014
++#define ixSPMI_PATH_0                                                           0xd0221018
++#define ixSPMI_C6_STATE_0                                                       0xd022101c
++#define ixSPMI_JTAG_OVER_0                                                      0xd0221020
++#define ixSPMI_SRAM_ADDRESS_0                                                   0xd0221024
++#define ixSPMI_SRAM_DATA_0                                                      0xd0221028
++#define ixSPMI_RESET_0                                                          0xd022102c
++#define ixSPMI_FORCE_CLOCK_GATERS_0                                             0xd0221030
++#define ixSPMI_SPARE_0                                                          0xd0221034
++#define ixSPMI_SPARE_EX_0                                                       0xd0221038
++#define ixSPMI_SRAM_CLK_GATER_0                                                 0xd022103c
++#define ixPOWERON_CPU_1                                                         0xd0230000
++#define ixPOWERREADY_CPU_1                                                      0xd0230004
++#define ixPGRUNFEEDBACK_CPU_1                                                   0xd0230008
++#define ixRCC3ON_CPU_1                                                          0xd023000c
++#define ixRCC3EXITDONE_CPU_1                                                    0xd0230010
++#define ixCORE_FUNC_LATE_SSB_XFER_1                                             0xd0230014
++#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1                                         0xd0230018
++#define ixCORE_REDUN_SSB_XFER_1                                                 0xd023001c
++#define ixCORE_REDUN_SSB_XFER_CFG_1                                             0xd0230020
++#define ixCORE_APM_SSB_XFER_1                                                   0xd0230024
++#define ixCORE_APM_SSB_XFER_CFG_1                                               0xd0230028
++#define ixCOREPM_PWRCTRL_MISC_1                                                 0xd023002c
++#define ixLDOIVRON_CPU_1                                                        0xd0230030
++#define ixLDOIVREXITDONE_CPU_1                                                  0xd0230034
++#define ixRCC3_TARGETPSMREF_CPU_1                                               0xd0230038
++#define ixIVR_TARGETPSMREF_CPU_1                                                0xd023003c
++#define ixCK_JTCOOLRESET_LATCHED_CPU_1                                          0xd0230044
++#define ixCK_DISABLECORE_CPU_1                                                  0xd0230048
++#define ixCOREPM_ID_1                                                           0xd023004c
++#define ixCOREPM_SCRATCH_1                                                      0xd0230050
++#define ixRCC3_WAKEMIN_CPU_1                                                    0xd0230054
++#define ixSPMI_CONFIG0_1                                                        0xd0231000
++#define ixSPMI_CONFIG1_1                                                        0xd0231004
++#define ixSPMI_FSM_READ_TRIGGER_1                                               0xd0231008
++#define ixSPMI_FSM_WRITE_TRIGGER_1                                              0xd023100c
++#define ixSPMI_FSM_RESET_TRIGGER_1                                              0xd0231010
++#define ixSPMI_FSM_BUSY_1                                                       0xd0231014
++#define ixSPMI_PATH_1                                                           0xd0231018
++#define ixSPMI_C6_STATE_1                                                       0xd023101c
++#define ixSPMI_JTAG_OVER_1                                                      0xd0231020
++#define ixSPMI_SRAM_ADDRESS_1                                                   0xd0231024
++#define ixSPMI_SRAM_DATA_1                                                      0xd0231028
++#define ixSPMI_RESET_1                                                          0xd023102c
++#define ixSPMI_FORCE_CLOCK_GATERS_1                                             0xd0231030
++#define ixSPMI_SPARE_1                                                          0xd0231034
++#define ixSPMI_SPARE_EX_1                                                       0xd0231038
++#define ixSPMI_SRAM_CLK_GATER_1                                                 0xd023103c
++#define ixGENERAL_PWRMGT                                                        0xd0200000
++#define ixCNB_PWRMGT_CNTL                                                       0xd0200004
++#define ixSCLK_PWRMGT_CNTL                                                      0xd0200008
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xd0200014
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xd02000f0
++#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2                                    0xd02000f4
++#define ixCG_FREQ_TRAN_VOTING_0                                                 0xd02001a8
++#define ixCG_FREQ_TRAN_VOTING_1                                                 0xd02001ac
++#define ixCG_FREQ_TRAN_VOTING_2                                                 0xd02001b0
++#define ixCG_FREQ_TRAN_VOTING_3                                                 0xd02001b4
++#define ixCG_FREQ_TRAN_VOTING_4                                                 0xd02001b8
++#define ixCG_FREQ_TRAN_VOTING_5                                                 0xd02001bc
++#define ixCG_FREQ_TRAN_VOTING_6                                                 0xd02001c0
++#define ixCG_FREQ_TRAN_VOTING_7                                                 0xd02001c4
++#define ixCG_STATIC_SCREEN_PARAMETER                                            0xd0200044
++#define ixCG_ACPI_CNTL                                                          0xd0200064
++#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xd0200080
++#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xd0200084
++#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xd020009c
++#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xd0200088
++#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xd020008c
++#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xd0200310
++#define ixSMU_VOLTAGE_STATUS                                                    0xd0200094
++#define ixCG_ULV_PARAMETER                                                      0xd020015c
++#define ixPWR_DC_RESP                                                           0xd0200300
++#define ixPWR_VCE_RESP                                                          0xd0200304
++#define ixPWR_UVD_RESP                                                          0xd0200308
++#define ixPWR_ACP_RESP                                                          0xd020030c
++#define ixPWR_DC_REQ                                                            0xd020031c
++#define ixSCLK_MIN_DIV                                                          0xd02003ac
++#define ixPCIE_PGFSM_CONFIG                                                     0xd02002d0
++#define ixPCIE_PGFSM_WRITE                                                      0xd02002d4
++#define ixSERDES_BUSY                                                           0xd02002d8
++#define ixPCIE_PGFSM2_CONFIG                                                    0xd02002dc
++#define ixPCIE_PGFSM2_WRITE                                                     0xd02002e0
++#define ixSERDES2_BUSY                                                          0xd02002e4
++#define ixPCIE_PGFSM_0_READ                                                     0xd02002e8
++#define ixPCIE_PGFSM_1_READ                                                     0xd02002ec
++#define ixPWR_ACPI_INTERRUPT                                                    0xd0200318
++#define ixVDDGFX_IDLE_PARAMETER                                                 0xd020036c
++#define ixVDDGFX_IDLE_CONTROL                                                   0xd0200370
++#define ixVDDGFX_IDLE_EXIT                                                      0xd0200374
++#define ixREG_SCLK_DEEP_SLEEP_EXIT                                              0xd0200378
++#define ixCAC_WEIGHT_LKG_DC_3                                                   0xd020803c
++#define ixLCAC_MC0_CNTL                                                         0xd0208130
++#define ixLCAC_MC0_OVR_SEL                                                      0xd0208134
++#define ixLCAC_MC0_OVR_VAL                                                      0xd0208138
++#define ixLCAC_MC1_CNTL                                                         0xd020813c
++#define ixLCAC_MC1_OVR_SEL                                                      0xd0208140
++#define ixLCAC_MC1_OVR_VAL                                                      0xd0208144
++#define ixLCAC_MC2_CNTL                                                         0xd0208148
++#define ixLCAC_MC2_OVR_SEL                                                      0xd020814c
++#define ixLCAC_MC2_OVR_VAL                                                      0xd0208150
++#define ixLCAC_MC3_CNTL                                                         0xd0208154
++#define ixLCAC_MC3_OVR_SEL                                                      0xd0208158
++#define ixLCAC_MC3_OVR_VAL                                                      0xd020815c
++#define ixLCAC_CPL_CNTL                                                         0xd0208160
++#define ixLCAC_CPL_OVR_SEL                                                      0xd0208164
++#define ixLCAC_CPL_OVR_VAL                                                      0xd0208168
++#define ixMISC_UNB_PWRMGT_CFG0                                                  0xd020c000
++#define ixMISC_UNB_PWRMGT_CFG1                                                  0xd020c004
++#define ixMISC_UNB_PWRMGT_DATA                                                  0xd020c00c
++#define ixGNBPM_SMU_PWRMGT_DATA                                                 0xd020c010
++#define ixDMA_ACTIVE_SAMPLER_CFG                                                0xd020c014
++#define ixSOUTHBRIDGE_TYPE                                                      0xd020c01c
++#define ixGNBPM_SMU_PWRMGT_STATUS                                               0xd020c020
++#define ixALLOW_SR_INTR_CTRL                                                    0xd020c024
++#define mmGC_CAC_LKG_AGGR_LOWER                                                 0x3294
++#define mmGC_CAC_LKG_AGGR_UPPER                                                 0x3295
++#define ixGC_CAC_WEIGHT_CU_0                                                    0x32
++#define ixGC_CAC_WEIGHT_CU_1                                                    0x33
++#define ixGC_CAC_WEIGHT_CU_2                                                    0x34
++#define ixGC_CAC_WEIGHT_CU_3                                                    0x35
++#define ixGC_CAC_ACC_CU0                                                        0xba
++#define ixGC_CAC_ACC_CU1                                                        0xbb
++#define ixGC_CAC_ACC_CU2                                                        0xbc
++#define ixGC_CAC_ACC_CU3                                                        0xbd
++#define ixGC_CAC_ACC_CU4                                                        0xbe
++#define ixGC_CAC_ACC_CU5                                                        0xbf
++#define ixGC_CAC_ACC_CU6                                                        0xc0
++#define ixGC_CAC_ACC_CU7                                                        0xc1
++#define ixGC_CAC_OVRD_CU                                                        0xe7
++
++#endif /* SMU_8_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
+new file mode 100644
+index 0000000..e1540c1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
+@@ -0,0 +1,1072 @@
++/*
++ * SMU_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_8_0_ENUM_H
++#define SMU_8_0_ENUM_H
++
++typedef enum DebugBlockId {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_UVDU                                = 0xd,
++	DBG_BLOCK_ID_SQA                                 = 0xe,
++	DBG_BLOCK_ID_SDMA0                               = 0xf,
++	DBG_BLOCK_ID_SDMA1                               = 0x10,
++	DBG_BLOCK_ID_SPIM                                = 0x11,
++	DBG_BLOCK_ID_GDS                                 = 0x12,
++	DBG_BLOCK_ID_VC0                                 = 0x13,
++	DBG_BLOCK_ID_VC1                                 = 0x14,
++	DBG_BLOCK_ID_PA0                                 = 0x15,
++	DBG_BLOCK_ID_PA1                                 = 0x16,
++	DBG_BLOCK_ID_CP0                                 = 0x17,
++	DBG_BLOCK_ID_CP1                                 = 0x18,
++	DBG_BLOCK_ID_CP2                                 = 0x19,
++	DBG_BLOCK_ID_XBR                                 = 0x1a,
++	DBG_BLOCK_ID_UVDM                                = 0x1b,
++	DBG_BLOCK_ID_VGT0                                = 0x1c,
++	DBG_BLOCK_ID_VGT1                                = 0x1d,
++	DBG_BLOCK_ID_IA                                  = 0x1e,
++	DBG_BLOCK_ID_SXM0                                = 0x1f,
++	DBG_BLOCK_ID_SXM1                                = 0x20,
++	DBG_BLOCK_ID_SCT0                                = 0x21,
++	DBG_BLOCK_ID_SCT1                                = 0x22,
++	DBG_BLOCK_ID_SPM0                                = 0x23,
++	DBG_BLOCK_ID_SPM1                                = 0x24,
++	DBG_BLOCK_ID_UNUSED0                             = 0x25,
++	DBG_BLOCK_ID_UNUSED1                             = 0x26,
++	DBG_BLOCK_ID_TCAA                                = 0x27,
++	DBG_BLOCK_ID_TCAB                                = 0x28,
++	DBG_BLOCK_ID_TCCA                                = 0x29,
++	DBG_BLOCK_ID_TCCB                                = 0x2a,
++	DBG_BLOCK_ID_MCC0                                = 0x2b,
++	DBG_BLOCK_ID_MCC1                                = 0x2c,
++	DBG_BLOCK_ID_MCC2                                = 0x2d,
++	DBG_BLOCK_ID_MCC3                                = 0x2e,
++	DBG_BLOCK_ID_SXS0                                = 0x2f,
++	DBG_BLOCK_ID_SXS1                                = 0x30,
++	DBG_BLOCK_ID_SXS2                                = 0x31,
++	DBG_BLOCK_ID_SXS3                                = 0x32,
++	DBG_BLOCK_ID_SXS4                                = 0x33,
++	DBG_BLOCK_ID_SXS5                                = 0x34,
++	DBG_BLOCK_ID_SXS6                                = 0x35,
++	DBG_BLOCK_ID_SXS7                                = 0x36,
++	DBG_BLOCK_ID_SXS8                                = 0x37,
++	DBG_BLOCK_ID_SXS9                                = 0x38,
++	DBG_BLOCK_ID_BCI0                                = 0x39,
++	DBG_BLOCK_ID_BCI1                                = 0x3a,
++	DBG_BLOCK_ID_BCI2                                = 0x3b,
++	DBG_BLOCK_ID_BCI3                                = 0x3c,
++	DBG_BLOCK_ID_MCB                                 = 0x3d,
++	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
++	DBG_BLOCK_ID_SQA00                               = 0x3f,
++	DBG_BLOCK_ID_SQA01                               = 0x40,
++	DBG_BLOCK_ID_SQA02                               = 0x41,
++	DBG_BLOCK_ID_SQA10                               = 0x42,
++	DBG_BLOCK_ID_SQA11                               = 0x43,
++	DBG_BLOCK_ID_SQA12                               = 0x44,
++	DBG_BLOCK_ID_UNUSED7                             = 0x45,
++	DBG_BLOCK_ID_UNUSED8                             = 0x46,
++	DBG_BLOCK_ID_SQB00                               = 0x47,
++	DBG_BLOCK_ID_SQB01                               = 0x48,
++	DBG_BLOCK_ID_SQB10                               = 0x49,
++	DBG_BLOCK_ID_SQB11                               = 0x4a,
++	DBG_BLOCK_ID_SQ00                                = 0x4b,
++	DBG_BLOCK_ID_SQ01                                = 0x4c,
++	DBG_BLOCK_ID_SQ10                                = 0x4d,
++	DBG_BLOCK_ID_SQ11                                = 0x4e,
++	DBG_BLOCK_ID_CB00                                = 0x4f,
++	DBG_BLOCK_ID_CB01                                = 0x50,
++	DBG_BLOCK_ID_CB02                                = 0x51,
++	DBG_BLOCK_ID_CB03                                = 0x52,
++	DBG_BLOCK_ID_CB04                                = 0x53,
++	DBG_BLOCK_ID_UNUSED9                             = 0x54,
++	DBG_BLOCK_ID_UNUSED10                            = 0x55,
++	DBG_BLOCK_ID_UNUSED11                            = 0x56,
++	DBG_BLOCK_ID_CB10                                = 0x57,
++	DBG_BLOCK_ID_CB11                                = 0x58,
++	DBG_BLOCK_ID_CB12                                = 0x59,
++	DBG_BLOCK_ID_CB13                                = 0x5a,
++	DBG_BLOCK_ID_CB14                                = 0x5b,
++	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
++	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
++	DBG_BLOCK_ID_TCP0                                = 0x5f,
++	DBG_BLOCK_ID_TCP1                                = 0x60,
++	DBG_BLOCK_ID_TCP2                                = 0x61,
++	DBG_BLOCK_ID_TCP3                                = 0x62,
++	DBG_BLOCK_ID_TCP4                                = 0x63,
++	DBG_BLOCK_ID_TCP5                                = 0x64,
++	DBG_BLOCK_ID_TCP6                                = 0x65,
++	DBG_BLOCK_ID_TCP7                                = 0x66,
++	DBG_BLOCK_ID_TCP8                                = 0x67,
++	DBG_BLOCK_ID_TCP9                                = 0x68,
++	DBG_BLOCK_ID_TCP10                               = 0x69,
++	DBG_BLOCK_ID_TCP11                               = 0x6a,
++	DBG_BLOCK_ID_TCP12                               = 0x6b,
++	DBG_BLOCK_ID_TCP13                               = 0x6c,
++	DBG_BLOCK_ID_TCP14                               = 0x6d,
++	DBG_BLOCK_ID_TCP15                               = 0x6e,
++	DBG_BLOCK_ID_TCP16                               = 0x6f,
++	DBG_BLOCK_ID_TCP17                               = 0x70,
++	DBG_BLOCK_ID_TCP18                               = 0x71,
++	DBG_BLOCK_ID_TCP19                               = 0x72,
++	DBG_BLOCK_ID_TCP20                               = 0x73,
++	DBG_BLOCK_ID_TCP21                               = 0x74,
++	DBG_BLOCK_ID_TCP22                               = 0x75,
++	DBG_BLOCK_ID_TCP23                               = 0x76,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
++	DBG_BLOCK_ID_DB00                                = 0x7f,
++	DBG_BLOCK_ID_DB01                                = 0x80,
++	DBG_BLOCK_ID_DB02                                = 0x81,
++	DBG_BLOCK_ID_DB03                                = 0x82,
++	DBG_BLOCK_ID_DB04                                = 0x83,
++	DBG_BLOCK_ID_UNUSED15                            = 0x84,
++	DBG_BLOCK_ID_UNUSED16                            = 0x85,
++	DBG_BLOCK_ID_UNUSED17                            = 0x86,
++	DBG_BLOCK_ID_DB10                                = 0x87,
++	DBG_BLOCK_ID_DB11                                = 0x88,
++	DBG_BLOCK_ID_DB12                                = 0x89,
++	DBG_BLOCK_ID_DB13                                = 0x8a,
++	DBG_BLOCK_ID_DB14                                = 0x8b,
++	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
++	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
++	DBG_BLOCK_ID_TCC0                                = 0x8f,
++	DBG_BLOCK_ID_TCC1                                = 0x90,
++	DBG_BLOCK_ID_TCC2                                = 0x91,
++	DBG_BLOCK_ID_TCC3                                = 0x92,
++	DBG_BLOCK_ID_TCC4                                = 0x93,
++	DBG_BLOCK_ID_TCC5                                = 0x94,
++	DBG_BLOCK_ID_TCC6                                = 0x95,
++	DBG_BLOCK_ID_TCC7                                = 0x96,
++	DBG_BLOCK_ID_SPS00                               = 0x97,
++	DBG_BLOCK_ID_SPS01                               = 0x98,
++	DBG_BLOCK_ID_SPS02                               = 0x99,
++	DBG_BLOCK_ID_SPS10                               = 0x9a,
++	DBG_BLOCK_ID_SPS11                               = 0x9b,
++	DBG_BLOCK_ID_SPS12                               = 0x9c,
++	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
++	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
++	DBG_BLOCK_ID_TA00                                = 0x9f,
++	DBG_BLOCK_ID_TA01                                = 0xa0,
++	DBG_BLOCK_ID_TA02                                = 0xa1,
++	DBG_BLOCK_ID_TA03                                = 0xa2,
++	DBG_BLOCK_ID_TA04                                = 0xa3,
++	DBG_BLOCK_ID_TA05                                = 0xa4,
++	DBG_BLOCK_ID_TA06                                = 0xa5,
++	DBG_BLOCK_ID_TA07                                = 0xa6,
++	DBG_BLOCK_ID_TA08                                = 0xa7,
++	DBG_BLOCK_ID_TA09                                = 0xa8,
++	DBG_BLOCK_ID_TA0A                                = 0xa9,
++	DBG_BLOCK_ID_TA0B                                = 0xaa,
++	DBG_BLOCK_ID_UNUSED23                            = 0xab,
++	DBG_BLOCK_ID_UNUSED24                            = 0xac,
++	DBG_BLOCK_ID_UNUSED25                            = 0xad,
++	DBG_BLOCK_ID_UNUSED26                            = 0xae,
++	DBG_BLOCK_ID_TA10                                = 0xaf,
++	DBG_BLOCK_ID_TA11                                = 0xb0,
++	DBG_BLOCK_ID_TA12                                = 0xb1,
++	DBG_BLOCK_ID_TA13                                = 0xb2,
++	DBG_BLOCK_ID_TA14                                = 0xb3,
++	DBG_BLOCK_ID_TA15                                = 0xb4,
++	DBG_BLOCK_ID_TA16                                = 0xb5,
++	DBG_BLOCK_ID_TA17                                = 0xb6,
++	DBG_BLOCK_ID_TA18                                = 0xb7,
++	DBG_BLOCK_ID_TA19                                = 0xb8,
++	DBG_BLOCK_ID_TA1A                                = 0xb9,
++	DBG_BLOCK_ID_TA1B                                = 0xba,
++	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
++	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
++	DBG_BLOCK_ID_TD00                                = 0xbf,
++	DBG_BLOCK_ID_TD01                                = 0xc0,
++	DBG_BLOCK_ID_TD02                                = 0xc1,
++	DBG_BLOCK_ID_TD03                                = 0xc2,
++	DBG_BLOCK_ID_TD04                                = 0xc3,
++	DBG_BLOCK_ID_TD05                                = 0xc4,
++	DBG_BLOCK_ID_TD06                                = 0xc5,
++	DBG_BLOCK_ID_TD07                                = 0xc6,
++	DBG_BLOCK_ID_TD08                                = 0xc7,
++	DBG_BLOCK_ID_TD09                                = 0xc8,
++	DBG_BLOCK_ID_TD0A                                = 0xc9,
++	DBG_BLOCK_ID_TD0B                                = 0xca,
++	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
++	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED34                            = 0xce,
++	DBG_BLOCK_ID_TD10                                = 0xcf,
++	DBG_BLOCK_ID_TD11                                = 0xd0,
++	DBG_BLOCK_ID_TD12                                = 0xd1,
++	DBG_BLOCK_ID_TD13                                = 0xd2,
++	DBG_BLOCK_ID_TD14                                = 0xd3,
++	DBG_BLOCK_ID_TD15                                = 0xd4,
++	DBG_BLOCK_ID_TD16                                = 0xd5,
++	DBG_BLOCK_ID_TD17                                = 0xd6,
++	DBG_BLOCK_ID_TD18                                = 0xd7,
++	DBG_BLOCK_ID_TD19                                = 0xd8,
++	DBG_BLOCK_ID_TD1A                                = 0xd9,
++	DBG_BLOCK_ID_TD1B                                = 0xda,
++	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
++	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED38                            = 0xde,
++	DBG_BLOCK_ID_LDS00                               = 0xdf,
++	DBG_BLOCK_ID_LDS01                               = 0xe0,
++	DBG_BLOCK_ID_LDS02                               = 0xe1,
++	DBG_BLOCK_ID_LDS03                               = 0xe2,
++	DBG_BLOCK_ID_LDS04                               = 0xe3,
++	DBG_BLOCK_ID_LDS05                               = 0xe4,
++	DBG_BLOCK_ID_LDS06                               = 0xe5,
++	DBG_BLOCK_ID_LDS07                               = 0xe6,
++	DBG_BLOCK_ID_LDS08                               = 0xe7,
++	DBG_BLOCK_ID_LDS09                               = 0xe8,
++	DBG_BLOCK_ID_LDS0A                               = 0xe9,
++	DBG_BLOCK_ID_LDS0B                               = 0xea,
++	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
++	DBG_BLOCK_ID_UNUSED40                            = 0xec,
++	DBG_BLOCK_ID_UNUSED41                            = 0xed,
++	DBG_BLOCK_ID_UNUSED42                            = 0xee,
++	DBG_BLOCK_ID_LDS10                               = 0xef,
++	DBG_BLOCK_ID_LDS11                               = 0xf0,
++	DBG_BLOCK_ID_LDS12                               = 0xf1,
++	DBG_BLOCK_ID_LDS13                               = 0xf2,
++	DBG_BLOCK_ID_LDS14                               = 0xf3,
++	DBG_BLOCK_ID_LDS15                               = 0xf4,
++	DBG_BLOCK_ID_LDS16                               = 0xf5,
++	DBG_BLOCK_ID_LDS17                               = 0xf6,
++	DBG_BLOCK_ID_LDS18                               = 0xf7,
++	DBG_BLOCK_ID_LDS19                               = 0xf8,
++	DBG_BLOCK_ID_LDS1A                               = 0xf9,
++	DBG_BLOCK_ID_LDS1B                               = 0xfa,
++	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
++	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
++	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
++	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
++} DebugBlockId;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
++	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
++	DBG_BLOCK_ID_PA_BY2                              = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
++	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
++	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
++	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
++	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
++	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
++	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
++	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
++	DBG_BLOCK_ID_CB_BY2                              = 0x24,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
++	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
++	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
++	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
++	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
++	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
++	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
++	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
++	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
++	DBG_BLOCK_ID_TA_BY2                              = 0x48,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
++	DBG_BLOCK_ID_TD_BY2                              = 0x58,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
++	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
++	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
++	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
++	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
++	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
++	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
++	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
++	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
++	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
++	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
++	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
++	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
++	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
++	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
++	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
++	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
++	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
++	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
++	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
++	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
++	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
++	DBG_BLOCK_ID_CB_BY4                              = 0x12,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
++	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
++	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
++	DBG_BLOCK_ID_DB_BY4                              = 0x16,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
++	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
++	DBG_BLOCK_ID_TA_BY4                              = 0x24,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
++	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
++	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
++	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
++	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
++	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
++	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
++	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
++	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
++	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
++	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
++	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
++	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
++	DBG_BLOCK_ID_CB_BY8                              = 0x9,
++	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
++	DBG_BLOCK_ID_DB_BY8                              = 0xb,
++	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
++	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
++	DBG_BLOCK_ID_TA_BY8                              = 0x12,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
++	DBG_BLOCK_ID_TD_BY8                              = 0x16,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
++	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
++	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
++	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
++	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
++	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
++	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
++	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
++	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
++	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
++	DBG_BLOCK_ID_TA_BY16                             = 0x9,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
++	DBG_BLOCK_ID_TD_BY16                             = 0xb,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
++	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
++	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
++} DebugBlockId_BY16;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++#define CG_SRBM_START_ADDR                        0x600
++#define CG_SRBM_END_ADDR                          0x8ff
++#define CG_SRBM_DEC0_START_ADDR                   0x200
++#define CG_SRBM_DEC0_END_ADDR                     0x2ff
++
++#endif /* SMU_8_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h
+new file mode 100644
+index 0000000..3dbe24d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h
+@@ -0,0 +1,2964 @@
++/*
++ * SMU_8_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef SMU_8_0_SH_MASK_H
++#define SMU_8_0_SH_MASK_H
++
++#define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
++#define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
++#define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
++#define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
++#define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
++#define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
++#define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
++#define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
++#define THM_TCON_HTC__HTC_EN_MASK 0x1
++#define THM_TCON_HTC__HTC_EN__SHIFT 0x0
++#define THM_TCON_HTC__RSVD0_MASK 0x2
++#define THM_TCON_HTC__RSVD0__SHIFT 0x1
++#define THM_TCON_HTC__HTC_P_STATE_EN_MASK 0x4
++#define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2
++#define THM_TCON_HTC__RSVD1_MASK 0x8
++#define THM_TCON_HTC__RSVD1__SHIFT 0x3
++#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x10
++#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4
++#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x20
++#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5
++#define THM_TCON_HTC__HTC_APIC_HI_EN_MASK 0x40
++#define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT 0x6
++#define THM_TCON_HTC__HTC_APIC_LO_EN_MASK 0x80
++#define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT 0x7
++#define THM_TCON_HTC__HTC_DIAG_MASK 0x100
++#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8
++#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x200
++#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9
++#define THM_TCON_HTC__HTC_TO_GNB_EN_MASK 0x400
++#define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT 0xa
++#define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK 0x800
++#define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT 0xb
++#define THM_TCON_HTC__RSVD2_MASK 0xf000
++#define THM_TCON_HTC__RSVD2__SHIFT 0xc
++#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x7f0000
++#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10
++#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x800000
++#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x17
++#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0xf000000
++#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x18
++#define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK 0x70000000
++#define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT 0x1c
++#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x1f
++#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
++#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x60
++#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
++#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x80
++#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
++#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x1f00
++#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
++#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x30000
++#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
++#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x40000
++#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
++#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x80000
++#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
++#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xffe00000
++#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15
++#define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1
++#define THM_TCON_THERM_TRIP__RSVD0__SHIFT 0x0
++#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2
++#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
++#define THM_TCON_THERM_TRIP__RSVD1_MASK 0x4
++#define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2
++#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x8
++#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
++#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x10
++#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
++#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x20
++#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
++#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7fffffc0
++#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0x6
++#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000
++#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
++#define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1
++#define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT 0x0
++#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2
++#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1
++#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x4
++#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2
++#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x8
++#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3
++#define THM_GPIO_PROCHOT_CTRL__SN_MASK 0x10
++#define THM_GPIO_PROCHOT_CTRL__SN__SHIFT 0x4
++#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x100
++#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x8
++#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x200
++#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x9
++#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x400
++#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0xa
++#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x800
++#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0xb
++#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x1000
++#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0xc
++#define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK 0x1
++#define THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT 0x0
++#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x2
++#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1
++#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x4
++#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2
++#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x8
++#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3
++#define THM_GPIO_THERMTRIP_CTRL__SN_MASK 0x10
++#define THM_GPIO_THERMTRIP_CTRL__SN__SHIFT 0x4
++#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x100
++#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x8
++#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x200
++#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x9
++#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x400
++#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0xa
++#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x800
++#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0xb
++#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x1000
++#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0xc
++#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
++#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
++#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
++#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
++#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
++#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
++#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
++#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
++#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
++#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
++#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
++#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
++#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
++#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
++#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
++#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
++#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
++#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
++#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
++#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
++#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
++#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
++#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
++#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
++#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
++#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
++#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
++#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
++#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
++#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
++#define TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_INT_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON0_INT_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff
++#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0
++#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff
++#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0
++#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff
++#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0
++#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff
++#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0
++#define TMON0_CONFIG__NUM_ACQ_MASK 0x7
++#define TMON0_CONFIG__NUM_ACQ__SHIFT 0x0
++#define TMON0_CONFIG__FORCE_MAX_ACQ_MASK 0x8
++#define TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3
++#define TMON0_CONFIG__RDI_INTERLEAVE_MASK 0x10
++#define TMON0_CONFIG__RDI_INTERLEAVE__SHIFT 0x4
++#define TMON0_CONFIG__RE_CALIB_EN_MASK 0x40
++#define TMON0_CONFIG__RE_CALIB_EN__SHIFT 0x6
++#define TMON0_TEMP_CALC_COEFF0__Z_MASK 0x7ff
++#define TMON0_TEMP_CALC_COEFF0__Z__SHIFT 0x0
++#define TMON0_TEMP_CALC_COEFF1__A_MASK 0xfff
++#define TMON0_TEMP_CALC_COEFF1__A__SHIFT 0x0
++#define TMON0_TEMP_CALC_COEFF2__B_MASK 0x3f
++#define TMON0_TEMP_CALC_COEFF2__B__SHIFT 0x0
++#define TMON0_TEMP_CALC_COEFF3__C_MASK 0x7ff
++#define TMON0_TEMP_CALC_COEFF3__C__SHIFT 0x0
++#define TMON0_TEMP_CALC_COEFF4__K_MASK 0x1
++#define TMON0_TEMP_CALC_COEFF4__K__SHIFT 0x0
++#define TMON0_DEBUG0__DEBUG_Z_MASK 0x7ff
++#define TMON0_DEBUG0__DEBUG_Z__SHIFT 0x0
++#define TMON0_DEBUG0__DEBUG_Z_EN_MASK 0x800
++#define TMON0_DEBUG0__DEBUG_Z_EN__SHIFT 0xb
++#define TMON0_DEBUG1__DEBUG_RDI_MASK 0x1f
++#define TMON0_DEBUG1__DEBUG_RDI__SHIFT 0x0
++#define TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_INT_DATA__TEMP_Z_DATA_MASK 0xfff
++#define TMON1_INT_DATA__TEMP_Z_DATA__SHIFT 0x0
++#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff
++#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0
++#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff
++#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0
++#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff
++#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0
++#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff
++#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0
++#define TMON1_CONFIG__NUM_ACQ_MASK 0x7
++#define TMON1_CONFIG__NUM_ACQ__SHIFT 0x0
++#define TMON1_CONFIG__FORCE_MAX_ACQ_MASK 0x8
++#define TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3
++#define TMON1_CONFIG__RDI_INTERLEAVE_MASK 0x10
++#define TMON1_CONFIG__RDI_INTERLEAVE__SHIFT 0x4
++#define TMON1_CONFIG__RE_CALIB_EN_MASK 0x40
++#define TMON1_CONFIG__RE_CALIB_EN__SHIFT 0x6
++#define TMON1_TEMP_CALC_COEFF0__Z_MASK 0x7ff
++#define TMON1_TEMP_CALC_COEFF0__Z__SHIFT 0x0
++#define TMON1_TEMP_CALC_COEFF1__A_MASK 0xfff
++#define TMON1_TEMP_CALC_COEFF1__A__SHIFT 0x0
++#define TMON1_TEMP_CALC_COEFF2__B_MASK 0x3f
++#define TMON1_TEMP_CALC_COEFF2__B__SHIFT 0x0
++#define TMON1_TEMP_CALC_COEFF3__C_MASK 0x7ff
++#define TMON1_TEMP_CALC_COEFF3__C__SHIFT 0x0
++#define TMON1_TEMP_CALC_COEFF4__K_MASK 0x1
++#define TMON1_TEMP_CALC_COEFF4__K__SHIFT 0x0
++#define TMON1_DEBUG0__DEBUG_Z_MASK 0x7ff
++#define TMON1_DEBUG0__DEBUG_Z__SHIFT 0x0
++#define TMON1_DEBUG0__DEBUG_Z_EN_MASK 0x800
++#define TMON1_DEBUG0__DEBUG_Z_EN__SHIFT 0xb
++#define TMON1_DEBUG1__DEBUG_RDI_MASK 0x1f
++#define TMON1_DEBUG1__DEBUG_RDI__SHIFT 0x0
++#define THM_TMON0_REMOTE_START__DATA_MASK 0xffffffff
++#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0
++#define THM_TMON0_REMOTE_END__DATA_MASK 0xffffffff
++#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0
++#define THM_TMON1_REMOTE_START__DATA_MASK 0xffffffff
++#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0
++#define THM_TMON1_REMOTE_END__DATA_MASK 0xffffffff
++#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0
++#define THM_TCON_LOCAL0__HaltPolling_MASK 0x1
++#define THM_TCON_LOCAL0__HaltPolling__SHIFT 0x0
++#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x2
++#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1
++#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x4
++#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2
++#define THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK 0x7
++#define THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT 0x0
++#define THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK 0x38
++#define THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT 0x3
++#define THM_TCON_LOCAL1__PwrDn_MinDelay_MASK 0x1c0
++#define THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT 0x6
++#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK 0x3
++#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT 0x0
++#define THM_TCON_LOCAL2__PwrDn_NumSensors_MASK 0xc
++#define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT 0x2
++#define THM_TCON_LOCAL2__start_mission_polling_MASK 0x10
++#define THM_TCON_LOCAL2__start_mission_polling__SHIFT 0x4
++#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x20
++#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5
++#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x40
++#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6
++#define THM_TCON_LOCAL2__csrslave_use_corrected_MASK 0x80
++#define THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT 0x7
++#define THM_TCON_LOCAL2__smu_use_corrected_MASK 0x100
++#define THM_TCON_LOCAL2__smu_use_corrected__SHIFT 0x8
++#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x800
++#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb
++#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x7ff
++#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0
++#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0xff
++#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0
++#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x7ff
++#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0
++#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0xff
++#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0
++#define THM_TCON_LOCAL7__THERMID_MASK 0xff
++#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0
++#define THM_TCON_LOCAL8__THERMMAX_MASK 0x7ff
++#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0
++#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x7ff
++#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0
++#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0xf
++#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0
++#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x7ff
++#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0
++#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0xf
++#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0
++#define THM_TCON_LOCAL13__PowerDownTmon0_MASK 0x1
++#define THM_TCON_LOCAL13__PowerDownTmon0__SHIFT 0x0
++#define THM_TCON_LOCAL13__PowerDownTmon1_MASK 0x2
++#define THM_TCON_LOCAL13__PowerDownTmon1__SHIFT 0x1
++#define THM_TCON_LOCAL14__boot_done_MASK 0x1
++#define THM_TCON_LOCAL14__boot_done__SHIFT 0x0
++#define THM_FUSE0__FUSE_TmonRsInterleave_MASK 0x1
++#define THM_FUSE0__FUSE_TmonRsInterleave__SHIFT 0x0
++#define THM_FUSE0__FUSE_TmonNumAcq_MASK 0xe
++#define THM_FUSE0__FUSE_TmonNumAcq__SHIFT 0x1
++#define THM_FUSE0__FUSE_TmonForceMaxAcq_MASK 0x10
++#define THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT 0x4
++#define THM_FUSE0__FUSE_TmonClkDiv_MASK 0x60
++#define THM_FUSE0__FUSE_TmonClkDiv__SHIFT 0x5
++#define THM_FUSE0__FUSE_TmonBGAdj1_MASK 0x7f80
++#define THM_FUSE0__FUSE_TmonBGAdj1__SHIFT 0x7
++#define THM_FUSE0__FUSE_TmonBGAdj0_MASK 0x7f8000
++#define THM_FUSE0__FUSE_TmonBGAdj0__SHIFT 0xf
++#define THM_FUSE0__FUSE_TconZtValue_MASK 0xff800000
++#define THM_FUSE0__FUSE_TconZtValue__SHIFT 0x17
++#define THM_FUSE1__FUSE_TconZtValue_MASK 0x3
++#define THM_FUSE1__FUSE_TconZtValue__SHIFT 0x0
++#define THM_FUSE1__FUSE_TconUseSecondary_MASK 0xc
++#define THM_FUSE1__FUSE_TconUseSecondary__SHIFT 0x2
++#define THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK 0x10
++#define THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT 0x4
++#define THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK 0x60
++#define THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT 0x5
++#define THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK 0x380
++#define THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT 0x7
++#define THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK 0xc00
++#define THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT 0xa
++#define THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK 0x7000
++#define THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT 0xc
++#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK 0x18000
++#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT 0xf
++#define THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK 0xe0000
++#define THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT 0x11
++#define THM_FUSE1__FUSE_TconKValue_MASK 0x100000
++#define THM_FUSE1__FUSE_TconKValue__SHIFT 0x14
++#define THM_FUSE1__FUSE_TconDtValue31_MASK 0x7e00000
++#define THM_FUSE1__FUSE_TconDtValue31__SHIFT 0x15
++#define THM_FUSE1__FUSE_TconDtValue30_MASK 0xf8000000
++#define THM_FUSE1__FUSE_TconDtValue30__SHIFT 0x1b
++#define THM_FUSE2__FUSE_TconDtValue30_MASK 0x1
++#define THM_FUSE2__FUSE_TconDtValue30__SHIFT 0x0
++#define THM_FUSE2__FUSE_TconDtValue29_MASK 0x7e
++#define THM_FUSE2__FUSE_TconDtValue29__SHIFT 0x1
++#define THM_FUSE2__FUSE_TconDtValue28_MASK 0x1f80
++#define THM_FUSE2__FUSE_TconDtValue28__SHIFT 0x7
++#define THM_FUSE2__FUSE_TconDtValue27_MASK 0x7e000
++#define THM_FUSE2__FUSE_TconDtValue27__SHIFT 0xd
++#define THM_FUSE2__FUSE_TconDtValue26_MASK 0x1f80000
++#define THM_FUSE2__FUSE_TconDtValue26__SHIFT 0x13
++#define THM_FUSE2__FUSE_TconDtValue25_MASK 0x7e000000
++#define THM_FUSE2__FUSE_TconDtValue25__SHIFT 0x19
++#define THM_FUSE2__FUSE_TconDtValue24_MASK 0x80000000
++#define THM_FUSE2__FUSE_TconDtValue24__SHIFT 0x1f
++#define THM_FUSE3__FUSE_TconDtValue24_MASK 0x1f
++#define THM_FUSE3__FUSE_TconDtValue24__SHIFT 0x0
++#define THM_FUSE3__FUSE_TconDtValue23_MASK 0x7e0
++#define THM_FUSE3__FUSE_TconDtValue23__SHIFT 0x5
++#define THM_FUSE3__FUSE_TconDtValue22_MASK 0x1f800
++#define THM_FUSE3__FUSE_TconDtValue22__SHIFT 0xb
++#define THM_FUSE3__FUSE_TconDtValue21_MASK 0x7e0000
++#define THM_FUSE3__FUSE_TconDtValue21__SHIFT 0x11
++#define THM_FUSE3__FUSE_TconDtValue20_MASK 0x1f800000
++#define THM_FUSE3__FUSE_TconDtValue20__SHIFT 0x17
++#define THM_FUSE3__FUSE_TconDtValue19_MASK 0xe0000000
++#define THM_FUSE3__FUSE_TconDtValue19__SHIFT 0x1d
++#define THM_FUSE4__FUSE_TconDtValue19_MASK 0x7
++#define THM_FUSE4__FUSE_TconDtValue19__SHIFT 0x0
++#define THM_FUSE4__FUSE_TconDtValue18_MASK 0x1f8
++#define THM_FUSE4__FUSE_TconDtValue18__SHIFT 0x3
++#define THM_FUSE4__FUSE_TconDtValue17_MASK 0x7e00
++#define THM_FUSE4__FUSE_TconDtValue17__SHIFT 0x9
++#define THM_FUSE4__FUSE_TconDtValue16_MASK 0x1f8000
++#define THM_FUSE4__FUSE_TconDtValue16__SHIFT 0xf
++#define THM_FUSE4__FUSE_TconDtValue15_MASK 0x7e00000
++#define THM_FUSE4__FUSE_TconDtValue15__SHIFT 0x15
++#define THM_FUSE4__FUSE_TconDtValue14_MASK 0xf8000000
++#define THM_FUSE4__FUSE_TconDtValue14__SHIFT 0x1b
++#define THM_FUSE5__FUSE_TconDtValue14_MASK 0x1
++#define THM_FUSE5__FUSE_TconDtValue14__SHIFT 0x0
++#define THM_FUSE5__FUSE_TconDtValue13_MASK 0x7e
++#define THM_FUSE5__FUSE_TconDtValue13__SHIFT 0x1
++#define THM_FUSE5__FUSE_TconDtValue12_MASK 0x1f80
++#define THM_FUSE5__FUSE_TconDtValue12__SHIFT 0x7
++#define THM_FUSE5__FUSE_TconDtValue11_MASK 0x7e000
++#define THM_FUSE5__FUSE_TconDtValue11__SHIFT 0xd
++#define THM_FUSE5__FUSE_TconDtValue10_MASK 0x1f80000
++#define THM_FUSE5__FUSE_TconDtValue10__SHIFT 0x13
++#define THM_FUSE5__FUSE_TconDtValue9_MASK 0x7e000000
++#define THM_FUSE5__FUSE_TconDtValue9__SHIFT 0x19
++#define THM_FUSE5__FUSE_TconDtValue8_MASK 0x80000000
++#define THM_FUSE5__FUSE_TconDtValue8__SHIFT 0x1f
++#define THM_FUSE6__FUSE_TconDtValue8_MASK 0x1f
++#define THM_FUSE6__FUSE_TconDtValue8__SHIFT 0x0
++#define THM_FUSE6__FUSE_TconDtValue7_MASK 0x7e0
++#define THM_FUSE6__FUSE_TconDtValue7__SHIFT 0x5
++#define THM_FUSE6__FUSE_TconDtValue6_MASK 0x1f800
++#define THM_FUSE6__FUSE_TconDtValue6__SHIFT 0xb
++#define THM_FUSE6__FUSE_TconDtValue5_MASK 0x7e0000
++#define THM_FUSE6__FUSE_TconDtValue5__SHIFT 0x11
++#define THM_FUSE6__FUSE_TconDtValue4_MASK 0x1f800000
++#define THM_FUSE6__FUSE_TconDtValue4__SHIFT 0x17
++#define THM_FUSE6__FUSE_TconDtValue3_MASK 0xe0000000
++#define THM_FUSE6__FUSE_TconDtValue3__SHIFT 0x1d
++#define THM_FUSE7__FUSE_TconDtValue3_MASK 0x7
++#define THM_FUSE7__FUSE_TconDtValue3__SHIFT 0x0
++#define THM_FUSE7__FUSE_TconDtValue2_MASK 0x1f8
++#define THM_FUSE7__FUSE_TconDtValue2__SHIFT 0x3
++#define THM_FUSE7__FUSE_TconDtValue1_MASK 0x7e00
++#define THM_FUSE7__FUSE_TconDtValue1__SHIFT 0x9
++#define THM_FUSE7__FUSE_TconDtValue0_MASK 0x1f8000
++#define THM_FUSE7__FUSE_TconDtValue0__SHIFT 0xf
++#define THM_FUSE7__FUSE_TconCtValue1_MASK 0xffe00000
++#define THM_FUSE7__FUSE_TconCtValue1__SHIFT 0x15
++#define THM_FUSE8__FUSE_TconCtValue0_MASK 0x7ff
++#define THM_FUSE8__FUSE_TconCtValue0__SHIFT 0x0
++#define THM_FUSE8__FUSE_TconBtValue_MASK 0x1f800
++#define THM_FUSE8__FUSE_TconBtValue__SHIFT 0xb
++#define THM_FUSE8__FUSE_TconBootDelay_MASK 0x60000
++#define THM_FUSE8__FUSE_TconBootDelay__SHIFT 0x11
++#define THM_FUSE8__FUSE_TconAtValue1_MASK 0x7ff80000
++#define THM_FUSE8__FUSE_TconAtValue1__SHIFT 0x13
++#define THM_FUSE8__FUSE_TconAtValue0_MASK 0x80000000
++#define THM_FUSE8__FUSE_TconAtValue0__SHIFT 0x1f
++#define THM_FUSE9__FUSE_TconAtValue0_MASK 0x7ff
++#define THM_FUSE9__FUSE_TconAtValue0__SHIFT 0x0
++#define THM_FUSE9__FUSE_ThermTripLimit_MASK 0x7f800
++#define THM_FUSE9__FUSE_ThermTripLimit__SHIFT 0xb
++#define THM_FUSE9__FUSE_ThermTripEn_MASK 0x80000
++#define THM_FUSE9__FUSE_ThermTripEn__SHIFT 0x13
++#define THM_FUSE9__FUSE_HtcTmpLmt_MASK 0x7f00000
++#define THM_FUSE9__FUSE_HtcTmpLmt__SHIFT 0x14
++#define THM_FUSE9__FUSE_HtcMsrLock_MASK 0x8000000
++#define THM_FUSE9__FUSE_HtcMsrLock__SHIFT 0x1b
++#define THM_FUSE9__FUSE_HtcHystLmt_MASK 0xf0000000
++#define THM_FUSE9__FUSE_HtcHystLmt__SHIFT 0x1c
++#define THM_FUSE10__FUSE_HtcDis_MASK 0x1
++#define THM_FUSE10__FUSE_HtcDis__SHIFT 0x0
++#define THM_FUSE10__FUSE_HtcClkInact_MASK 0xe
++#define THM_FUSE10__FUSE_HtcClkInact__SHIFT 0x1
++#define THM_FUSE10__FUSE_HtcClkAct_MASK 0x70
++#define THM_FUSE10__FUSE_HtcClkAct__SHIFT 0x4
++#define THM_FUSE10__FUSE_UnusedBits_MASK 0xffffff80
++#define THM_FUSE10__FUSE_UnusedBits__SHIFT 0x7
++#define THM_FUSE11__PA_SPARE_MASK 0xff
++#define THM_FUSE11__PA_SPARE__SHIFT 0x0
++#define THM_FUSE12__FusesValid_MASK 0x1
++#define THM_FUSE12__FusesValid__SHIFT 0x0
++#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR_MASK 0xffffffff
++#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR__SHIFT 0x0
++#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA_MASK 0xffffffff
++#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA__SHIFT 0x0
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
++#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
++#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG__SHIFT 0x0
++#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG_MASK 0xffffffff
++#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG__SHIFT 0x0
++#define SAM_IH_EXT_ERR_INTR__UVD_MASK 0x1
++#define SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x0
++#define SAM_IH_EXT_ERR_INTR__VCE_MASK 0x2
++#define SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x1
++#define SAM_IH_EXT_ERR_INTR__ISP_MASK 0x4
++#define SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x2
++#define SAM_IH_EXT_ERR_INTR__RESERVED_MASK 0xfffffff8
++#define SAM_IH_EXT_ERR_INTR__RESERVED__SHIFT 0x3
++#define SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x1
++#define SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x0
++#define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x2
++#define SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x1
++#define SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x4
++#define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x2
++#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED_MASK 0xfffffff8
++#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED__SHIFT 0x3
++#define MP0_DISP_TIMER0_CTRL0__START_MASK 0x1
++#define MP0_DISP_TIMER0_CTRL0__START__SHIFT 0x0
++#define MP0_DISP_TIMER0_CTRL0__CLEAR_MASK 0x100
++#define MP0_DISP_TIMER0_CTRL0__CLEAR__SHIFT 0x8
++#define MP0_DISP_TIMER0_CTRL0__DEC_MASK 0x10000
++#define MP0_DISP_TIMER0_CTRL0__DEC__SHIFT 0x10
++#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000
++#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18
++#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN_MASK 0x1
++#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0
++#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100
++#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8
++#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN_MASK 0x10000
++#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10
++#define MP0_DISP_TIMER0_CTRL1__RESERVED_MASK 0xff000000
++#define MP0_DISP_TIMER0_CTRL1__RESERVED__SHIFT 0x18
++#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC_MASK 0xf
++#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC__SHIFT 0x0
++#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0
++#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED__SHIFT 0x4
++#define MP0_DISP_TIMER0_INTEN__INTEN_MASK 0xf
++#define MP0_DISP_TIMER0_INTEN__INTEN__SHIFT 0x0
++#define MP0_DISP_TIMER0_INTEN__RESERVED_MASK 0xfffffff0
++#define MP0_DISP_TIMER0_INTEN__RESERVED__SHIFT 0x4
++#define MP0_DISP_TIMER0_OCMP_0_0__OCMP_MASK 0xffffffff
++#define MP0_DISP_TIMER0_OCMP_0_0__OCMP__SHIFT 0x0
++#define MP0_DISP_TIMER0_OCMP_0_1__OCMP_MASK 0xffffffff
++#define MP0_DISP_TIMER0_OCMP_0_1__OCMP__SHIFT 0x0
++#define MP0_DISP_TIMER0_CNT__COUNT_MASK 0xffffffff
++#define MP0_DISP_TIMER0_CNT__COUNT__SHIFT 0x0
++#define MP0_DISP_TIMER1_CTRL0__START_MASK 0x1
++#define MP0_DISP_TIMER1_CTRL0__START__SHIFT 0x0
++#define MP0_DISP_TIMER1_CTRL0__CLEAR_MASK 0x100
++#define MP0_DISP_TIMER1_CTRL0__CLEAR__SHIFT 0x8
++#define MP0_DISP_TIMER1_CTRL0__DEC_MASK 0x10000
++#define MP0_DISP_TIMER1_CTRL0__DEC__SHIFT 0x10
++#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000
++#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18
++#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN_MASK 0x1
++#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0
++#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100
++#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8
++#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN_MASK 0x10000
++#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10
++#define MP0_DISP_TIMER1_CTRL1__RESERVED_MASK 0xff000000
++#define MP0_DISP_TIMER1_CTRL1__RESERVED__SHIFT 0x18
++#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC_MASK 0xf
++#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC__SHIFT 0x0
++#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0
++#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED__SHIFT 0x4
++#define MP0_DISP_TIMER1_INTEN__INTEN_MASK 0xf
++#define MP0_DISP_TIMER1_INTEN__INTEN__SHIFT 0x0
++#define MP0_DISP_TIMER1_INTEN__RESERVED_MASK 0xfffffff0
++#define MP0_DISP_TIMER1_INTEN__RESERVED__SHIFT 0x4
++#define MP0_DISP_TIMER1_OCMP_0_0__OCMP_MASK 0xffffffff
++#define MP0_DISP_TIMER1_OCMP_0_0__OCMP__SHIFT 0x0
++#define MP0_DISP_TIMER1_OCMP_0_1__OCMP_MASK 0xffffffff
++#define MP0_DISP_TIMER1_OCMP_0_1__OCMP__SHIFT 0x0
++#define MP0_DISP_TIMER1_CNT__COUNT_MASK 0xffffffff
++#define MP0_DISP_TIMER1_CNT__COUNT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_0__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_0__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_1__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_1__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_2__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_2__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_3__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_3__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_4__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_4__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_6__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_6__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_7__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_7__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_8__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_8__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_9__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_9__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_10__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_10__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_11__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_11__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_12__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_12__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_13__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_13__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_14__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_14__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_MSG_15__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_MSG_15__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_0__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_0__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_1__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_1__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_2__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_2__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_3__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_3__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_4__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_4__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_5__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_5__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_6__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_6__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_7__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_7__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_8__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_8__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_9__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_9__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_10__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_10__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_11__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_11__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_12__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_12__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_13__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_13__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_14__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_14__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_RESP_15__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_RESP_15__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_0__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_0__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_1__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_1__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_2__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_2__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_3__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_3__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_4__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_4__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_5__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_5__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_6__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_6__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_7__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_7__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_8__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_8__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_9__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_9__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_10__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_10__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_11__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_11__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_12__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_12__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_13__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_13__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_14__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_14__CONTENT__SHIFT 0x0
++#define SMU_MP1_SRBM2P_ARG_15__CONTENT_MASK 0xffffffff
++#define SMU_MP1_SRBM2P_ARG_15__CONTENT__SHIFT 0x0
++#define SMU_MP1_ACP2MP_RESP__CONTENT_MASK 0xffffffff
++#define SMU_MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
++#define SMU_MP1_DC2MP_RESP__CONTENT_MASK 0xffffffff
++#define SMU_MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
++#define SMU_MP1_UVD2MP_RESP__CONTENT_MASK 0xffffffff
++#define SMU_MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
++#define SMU_MP1_VCE2MP_RESP__CONTENT_MASK 0xffffffff
++#define SMU_MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
++#define SMU_MP1_RLC2MP_RESP__CONTENT_MASK 0xffffffff
++#define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
++#define MP_FPS_CNT__FPS_CNT_MASK 0xffffffff
++#define MP_FPS_CNT__FPS_CNT__SHIFT 0x0
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT_MASK 0x1
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK_MASK 0x8
++#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3
++#define SMU_DISP0_TIMER_INT_CONTROL__MASK_MASK 0x10
++#define SMU_DISP0_TIMER_INT_CONTROL__MASK__SHIFT 0x4
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT_MASK 0x1
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK_MASK 0x8
++#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3
++#define SMU_DISP1_TIMER_INT_CONTROL__MASK_MASK 0x10
++#define SMU_DISP1_TIMER_INT_CONTROL__MASK__SHIFT 0x4
++#define SMU_SRBM_CONFIG__MSTR_CREDITS_MASK 0x1f
++#define SMU_SRBM_CONFIG__MSTR_CREDITS__SHIFT 0x0
++#define MP_FPS_CNT_XBAR__FPS_CNT_MASK 0xffffffff
++#define MP_FPS_CNT_XBAR__FPS_CNT__SHIFT 0x0
++#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS_MASK 0x1f
++#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS__SHIFT 0x0
++#define MP_SRBM_CONTROL__ACC_VIO_EN_MASK 0x1
++#define MP_SRBM_CONTROL__ACC_VIO_EN__SHIFT 0x0
++#define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK 0x2
++#define MP_SRBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x1
++#define MP_SRBM_CONTROL__SOFT_RST_MASK_MASK 0x4
++#define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT 0x2
++#define MP_SRBM_CONTROL__SOFT_RST_STS_MASK 0x8
++#define MP_SRBM_CONTROL__SOFT_RST_STS__SHIFT 0x3
++#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1
++#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0
++#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID_MASK 0xe
++#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID__SHIFT 0x1
++#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000
++#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f
++#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff
++#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0
++#define MP_CRBBM_CONTROL__ACC_VIO_EN_MASK 0x1
++#define MP_CRBBM_CONTROL__ACC_VIO_EN__SHIFT 0x0
++#define MP_CRBBM_CONTROL__MP0_ACCESS_MASK 0x2
++#define MP_CRBBM_CONTROL__MP0_ACCESS__SHIFT 0x1
++#define MP_CRBBM_CONTROL__ALLOW_NS_ACC_MASK 0x4
++#define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x2
++#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1
++#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0
++#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK 0x2
++#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF__SHIFT 0x1
++#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000
++#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f
++#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff
++#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_CNTL__tag_MASK 0x1ffff
++#define MP_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_CNTL__urg_MASK 0x1e0000
++#define MP_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT 0x11
++#define MP_DRAM_CNTL_WRREQ_CNTL__stall_MASK 0x200000
++#define MP_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT 0x15
++#define MP_DRAM_CNTL_WRREQ_CNTL__priv_MASK 0x400000
++#define MP_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT 0x16
++#define MP_DRAM_CNTL_WRREQ_CNTL__cid_MASK 0xff800000
++#define MP_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT 0x17
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf_MASK 0x1
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid_MASK 0xfe
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid__SHIFT 0x1
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical_MASK 0x100
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical__SHIFT 0x8
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop_MASK 0x200
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop__SHIFT 0x9
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval_MASK 0x400
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval__SHIFT 0xa
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__op_MASK 0x3f800
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__op__SHIFT 0xb
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap_MASK 0x300000
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap__SHIFT 0x14
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid_MASK 0x3c00000
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid__SHIFT 0x16
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc_MASK 0x4000000
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc__SHIFT 0x1a
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed_MASK 0x8000000
++#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed__SHIFT 0x1b
++#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37_MASK 0x7ff
++#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK 0xfffff800
++#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT 0xb
++#define MP_DRAM_CNTL_WRREQ_MASK__mask_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_MASK__mask__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_0__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_1__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_2__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_3__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_4__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_5__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_6__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_DATA_7__data_MASK 0xffffffff
++#define MP_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK 0x1f
++#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT 0x0
++#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK 0xe0
++#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT 0x5
++#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK 0x100
++#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT 0x8
++#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK 0xfe00
++#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT 0x9
++#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK 0xf0000
++#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT 0x10
++#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK 0xfff00000
++#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT 0x14
++#define MP_DRAM_CNTL_WRRET_STATUS_0__valid_MASK 0x1
++#define MP_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT 0x0
++#define MP_DRAM_CNTL_WRRET_STATUS_0__nack_MASK 0x6
++#define MP_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT 0x1
++#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK 0xfff8
++#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT 0x3
++#define MP_DRAM_CNTL_WRRET_STATUS_0__tag_MASK 0xffff0000
++#define MP_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT 0x10
++#define MP_DRAM_CNTL_RDREQ_ADDR__addr_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT 0x0
++#define MP_DRAM_CNTL_RDREQ_CNTL__tag_MASK 0xffff
++#define MP_DRAM_CNTL_RDREQ_CNTL__tag__SHIFT 0x0
++#define MP_DRAM_CNTL_RDREQ_CNTL__mask_MASK 0xff0000
++#define MP_DRAM_CNTL_RDREQ_CNTL__mask__SHIFT 0x10
++#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40_MASK 0xff000000
++#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40__SHIFT 0x18
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK 0xf
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT 0x0
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK 0x10
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT 0x4
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK 0x20
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT 0x5
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK 0xc0
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT 0x6
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK 0x1ff00
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT 0x8
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK 0x1e0000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT 0x11
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK 0x200000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT 0x15
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical_MASK 0x400000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical__SHIFT 0x16
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe_MASK 0x800000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe__SHIFT 0x17
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop_MASK 0x1000000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop__SHIFT 0x18
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared_MASK 0x2000000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared__SHIFT 0x19
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf_MASK 0x4000000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf__SHIFT 0x1a
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid_MASK 0xf8000000
++#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid__SHIFT 0x1b
++#define MP_DRAM_CNTL_RDRET_VALID__vld_0_MASK 0x1
++#define MP_DRAM_CNTL_RDRET_VALID__vld_0__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x2
++#define MP_DRAM_CNTL_RDRET_VALID__vld_1__SHIFT 0x1
++#define MP_DRAM_CNTL_RDRET_VALID__vld_2_MASK 0x4
++#define MP_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x2
++#define MP_DRAM_CNTL_RDRET_VALID__vld_3_MASK 0x8
++#define MP_DRAM_CNTL_RDRET_VALID__vld_3__SHIFT 0x3
++#define MP_DRAM_CNTL_RDRET_VALID__vld_4_MASK 0x10
++#define MP_DRAM_CNTL_RDRET_VALID__vld_4__SHIFT 0x4
++#define MP_DRAM_CNTL_RDRET_VALID__vld_5_MASK 0x20
++#define MP_DRAM_CNTL_RDRET_VALID__vld_5__SHIFT 0x5
++#define MP_DRAM_CNTL_RDRET_VALID__vld_6_MASK 0x40
++#define MP_DRAM_CNTL_RDRET_VALID__vld_6__SHIFT 0x6
++#define MP_DRAM_CNTL_RDRET_VALID__vld_7_MASK 0x80
++#define MP_DRAM_CNTL_RDRET_VALID__vld_7__SHIFT 0x7
++#define MP_DRAM_CNTL_RDRET_VALID__reserved_MASK 0xffff00
++#define MP_DRAM_CNTL_RDRET_VALID__reserved__SHIFT 0x8
++#define MP_DRAM_CNTL_RDRET_VALID__atomic_MASK 0xff000000
++#define MP_DRAM_CNTL_RDRET_VALID__atomic__SHIFT 0x18
++#define MP_DRAM_CNTL_RDRET_NACK__nack_0_MASK 0x3
++#define MP_DRAM_CNTL_RDRET_NACK__nack_0__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_NACK__nack_1_MASK 0xc
++#define MP_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x2
++#define MP_DRAM_CNTL_RDRET_NACK__nack_2_MASK 0x30
++#define MP_DRAM_CNTL_RDRET_NACK__nack_2__SHIFT 0x4
++#define MP_DRAM_CNTL_RDRET_NACK__nack_3_MASK 0xc0
++#define MP_DRAM_CNTL_RDRET_NACK__nack_3__SHIFT 0x6
++#define MP_DRAM_CNTL_RDRET_NACK__nack_4_MASK 0x300
++#define MP_DRAM_CNTL_RDRET_NACK__nack_4__SHIFT 0x8
++#define MP_DRAM_CNTL_RDRET_NACK__nack_5_MASK 0xc00
++#define MP_DRAM_CNTL_RDRET_NACK__nack_5__SHIFT 0xa
++#define MP_DRAM_CNTL_RDRET_NACK__nack_6_MASK 0x3000
++#define MP_DRAM_CNTL_RDRET_NACK__nack_6__SHIFT 0xc
++#define MP_DRAM_CNTL_RDRET_NACK__nack_7_MASK 0xc000
++#define MP_DRAM_CNTL_RDRET_NACK__nack_7__SHIFT 0xe
++#define MP_DRAM_CNTL_RDRET_NACK__reserved_MASK 0xffff0000
++#define MP_DRAM_CNTL_RDRET_NACK__reserved__SHIFT 0x10
++#define MP_DRAM_CNTL_RDRET_DATA_0__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_0__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_1__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_1__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_2__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_2__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_3__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_3__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_4__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_4__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_5__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_5__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_6__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_6__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_7__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_7__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_8__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_8__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_9__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_9__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_10__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_10__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_11__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_11__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_12__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_12__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_13__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_13__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_14__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_14__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_15__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_15__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_16__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_16__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_17__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_17__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_18__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_18__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_19__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_19__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_20__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_20__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_21__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_21__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_22__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_22__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_23__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_23__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_24__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_24__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_25__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_25__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_26__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_26__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_27__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_27__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_28__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_28__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_29__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_29__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_30__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_30__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_31__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_31__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_32__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_32__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_33__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_33__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_34__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_34__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_35__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_35__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_36__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_36__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_37__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_37__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_38__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_38__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_39__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_39__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_40__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_40__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_41__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_41__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_42__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_42__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_43__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_43__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_44__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_44__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_45__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_45__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_46__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_46__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_47__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_47__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_48__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_48__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_49__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_49__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_50__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_50__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_51__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_51__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_52__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_52__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_53__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_53__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_54__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_54__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_55__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_55__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_56__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_56__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_57__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_57__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_58__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_58__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_59__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_59__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_60__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_60__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_61__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_61__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_62__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_62__DATA__SHIFT 0x0
++#define MP_DRAM_CNTL_RDRET_DATA_63__DATA_MASK 0xffffffff
++#define MP_DRAM_CNTL_RDRET_DATA_63__DATA__SHIFT 0x0
++#define MP_IOC_CTRL__IOC_mst_send_MASK 0x1
++#define MP_IOC_CTRL__IOC_mst_send__SHIFT 0x0
++#define MP_IOC_CTRL__IOC_mst_stop_MASK 0x2
++#define MP_IOC_CTRL__IOC_mst_stop__SHIFT 0x1
++#define MP_IOC_CTRL__IOC_mst_force_active_MASK 0x4
++#define MP_IOC_CTRL__IOC_mst_force_active__SHIFT 0x2
++#define MP_IOC_CTRL__IOC_mst_rdValid_MASK 0x8
++#define MP_IOC_CTRL__IOC_mst_rdValid__SHIFT 0x3
++#define MP_IOC_CTRL__IOC_mst_busy_MASK 0x10
++#define MP_IOC_CTRL__IOC_mst_busy__SHIFT 0x4
++#define MP_IOC_CTRL__IOC_mst_disabled_MASK 0x20
++#define MP_IOC_CTRL__IOC_mst_disabled__SHIFT 0x5
++#define MP_IOC_CTRL__IOC_mst_debug_rst_MASK 0x40
++#define MP_IOC_CTRL__IOC_mst_debug_rst__SHIFT 0x6
++#define MP_IOC_CTRL__IOC_mst_stop_ack_MASK 0x80
++#define MP_IOC_CTRL__IOC_mst_stop_ack__SHIFT 0x7
++#define MP_IOC_CTRL__IOC_mst_rderr_MASK 0x300
++#define MP_IOC_CTRL__IOC_mst_rderr__SHIFT 0x8
++#define MP_IOC_RDDATA__IOC_mst_rdData_MASK 0xffffffff
++#define MP_IOC_RDDATA__IOC_mst_rdData__SHIFT 0x0
++#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK 0x2
++#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit__SHIFT 0x1
++#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd_MASK 0x4
++#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT 0x2
++#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo_MASK 0xfffffff8
++#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo__SHIFT 0x3
++#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid_MASK 0xff
++#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid__SHIFT 0x0
++#define MP_IOC_PHASE2__BiuCqfC_AltReqMask_MASK 0xff00
++#define MP_IOC_PHASE2__BiuCqfC_AltReqMask__SHIFT 0x8
++#define MP_IOC_PHASE2__BiuCqfC_AltReqSize_MASK 0x30000
++#define MP_IOC_PHASE2__BiuCqfC_AltReqSize__SHIFT 0x10
++#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi_MASK 0xff000000
++#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi__SHIFT 0x18
++#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut_MASK 0xffffffff
++#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut__SHIFT 0x0
++#define MP_IOC_READ_0__data_MASK 0xffffffff
++#define MP_IOC_READ_0__data__SHIFT 0x0
++#define MP_IOC_READ_1__data_MASK 0xffffffff
++#define MP_IOC_READ_1__data__SHIFT 0x0
++#define MP_IOC_READ_2__data_MASK 0xffffffff
++#define MP_IOC_READ_2__data__SHIFT 0x0
++#define MP_IOC_READ_3__data_MASK 0xffffffff
++#define MP_IOC_READ_3__data__SHIFT 0x0
++#define MP_IOC_READ_4__data_MASK 0xffffffff
++#define MP_IOC_READ_4__data__SHIFT 0x0
++#define MP_IOC_READ_5__data_MASK 0xffffffff
++#define MP_IOC_READ_5__data__SHIFT 0x0
++#define MP_IOC_READ_6__data_MASK 0xffffffff
++#define MP_IOC_READ_6__data__SHIFT 0x0
++#define MP_IOC_READ_7__data_MASK 0xffffffff
++#define MP_IOC_READ_7__data__SHIFT 0x0
++#define MP_IOC_READ_8__data_MASK 0xffffffff
++#define MP_IOC_READ_8__data__SHIFT 0x0
++#define MP_IOC_READ_9__data_MASK 0xffffffff
++#define MP_IOC_READ_9__data__SHIFT 0x0
++#define MP_IOC_READ_10__data_MASK 0xffffffff
++#define MP_IOC_READ_10__data__SHIFT 0x0
++#define MP_IOC_READ_11__data_MASK 0xffffffff
++#define MP_IOC_READ_11__data__SHIFT 0x0
++#define MP_IOC_READ_12__data_MASK 0xffffffff
++#define MP_IOC_READ_12__data__SHIFT 0x0
++#define MP_IOC_READ_13__data_MASK 0xffffffff
++#define MP_IOC_READ_13__data__SHIFT 0x0
++#define MP_IOC_READ_14__data_MASK 0xffffffff
++#define MP_IOC_READ_14__data__SHIFT 0x0
++#define MP_IOC_READ_15__data_MASK 0xffffffff
++#define MP_IOC_READ_15__data__SHIFT 0x0
++#define MP_IOC_WRITE_0__data_MASK 0xffffffff
++#define MP_IOC_WRITE_0__data__SHIFT 0x0
++#define MP_IOC_WRITE_1__data_MASK 0xffffffff
++#define MP_IOC_WRITE_1__data__SHIFT 0x0
++#define MP_IOC_WRITE_2__data_MASK 0xffffffff
++#define MP_IOC_WRITE_2__data__SHIFT 0x0
++#define MP_IOC_WRITE_3__data_MASK 0xffffffff
++#define MP_IOC_WRITE_3__data__SHIFT 0x0
++#define MP_IOC_WRITE_4__data_MASK 0xffffffff
++#define MP_IOC_WRITE_4__data__SHIFT 0x0
++#define MP_IOC_WRITE_5__data_MASK 0xffffffff
++#define MP_IOC_WRITE_5__data__SHIFT 0x0
++#define MP_IOC_WRITE_6__data_MASK 0xffffffff
++#define MP_IOC_WRITE_6__data__SHIFT 0x0
++#define MP_IOC_WRITE_7__data_MASK 0xffffffff
++#define MP_IOC_WRITE_7__data__SHIFT 0x0
++#define MP_IOC_WRITE_8__data_MASK 0xffffffff
++#define MP_IOC_WRITE_8__data__SHIFT 0x0
++#define MP_IOC_WRITE_9__data_MASK 0xffffffff
++#define MP_IOC_WRITE_9__data__SHIFT 0x0
++#define MP_IOC_WRITE_10__data_MASK 0xffffffff
++#define MP_IOC_WRITE_10__data__SHIFT 0x0
++#define MP_IOC_WRITE_11__data_MASK 0xffffffff
++#define MP_IOC_WRITE_11__data__SHIFT 0x0
++#define MP_IOC_WRITE_12__data_MASK 0xffffffff
++#define MP_IOC_WRITE_12__data__SHIFT 0x0
++#define MP_IOC_WRITE_13__data_MASK 0xffffffff
++#define MP_IOC_WRITE_13__data__SHIFT 0x0
++#define MP_IOC_WRITE_14__data_MASK 0xffffffff
++#define MP_IOC_WRITE_14__data__SHIFT 0x0
++#define MP_IOC_WRITE_15__data_MASK 0xffffffff
++#define MP_IOC_WRITE_15__data__SHIFT 0x0
++#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE_MASK 0x1f
++#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE__SHIFT 0x0
++#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK_MASK 0x20
++#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK__SHIFT 0x5
++#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK_MASK 0x40
++#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK__SHIFT 0x6
++#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK_MASK 0x80
++#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK__SHIFT 0x7
++#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK_MASK 0x100
++#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK__SHIFT 0x8
++#define MP0_SW_INT__VALID_MASK 0x1
++#define MP0_SW_INT__VALID__SHIFT 0x0
++#define MP0_SW_INT__INT_ID_MASK 0x1fe
++#define MP0_SW_INT__INT_ID__SHIFT 0x1
++#define MP0_SW_INT_CTXID__CTXID_MASK 0xfffffff
++#define MP0_SW_INT_CTXID__CTXID__SHIFT 0x0
++#define MP1_SW_INT__VALID_MASK 0x1
++#define MP1_SW_INT__VALID__SHIFT 0x0
++#define MP1_SW_INT__INT_ID_MASK 0x1fe
++#define MP1_SW_INT__INT_ID__SHIFT 0x1
++#define MP1_SW_INT_CTXID__CTXID_MASK 0xfffffff
++#define MP1_SW_INT_CTXID__CTXID__SHIFT 0x0
++#define DISP_TIMER_ID__DISP_T0_INT_ID_MASK 0xff
++#define DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT 0x0
++#define DISP_TIMER_ID__DISP_T1_INT_ID_MASK 0xff00
++#define DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT 0x8
++#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
++#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
++#define PWRHW_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
++#define PWRHW_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
++#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID_MASK 0x7
++#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID__SHIFT 0x0
++#define CURRENT_STATE_CPU0__CURRENT_DID_MASK 0x38
++#define CURRENT_STATE_CPU0__CURRENT_DID__SHIFT 0x3
++#define CURRENT_STATE_CPU0__CURRENT_FID_MASK 0xfc0
++#define CURRENT_STATE_CPU0__CURRENT_FID__SHIFT 0x6
++#define CURRENT_STATE_CPU0__CPU_COF_MASK 0xfff000
++#define CURRENT_STATE_CPU0__CPU_COF__SHIFT 0xc
++#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG_MASK 0x7f000000
++#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG__SHIFT 0x18
++#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID_MASK 0x7
++#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID__SHIFT 0x0
++#define CURRENT_STATE_CPU1__CURRENT_DID_MASK 0x38
++#define CURRENT_STATE_CPU1__CURRENT_DID__SHIFT 0x3
++#define CURRENT_STATE_CPU1__CURRENT_FID_MASK 0xfc0
++#define CURRENT_STATE_CPU1__CURRENT_FID__SHIFT 0x6
++#define CURRENT_STATE_CPU1__CPU_COF_MASK 0xfff000
++#define CURRENT_STATE_CPU1__CPU_COF__SHIFT 0xc
++#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG_MASK 0x7f000000
++#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG__SHIFT 0x18
++#define CPU_REDUN_DONE0__CPU_REDUN_DONE_MASK 0x1
++#define CPU_REDUN_DONE0__CPU_REDUN_DONE__SHIFT 0x0
++#define CPU_REDUN_DONE1__CPU_REDUN_DONE_MASK 0x1
++#define CPU_REDUN_DONE1__CPU_REDUN_DONE__SHIFT 0x0
++#define CURRENT_VID_CPU0__CURRENT_VID_MASK 0xff
++#define CURRENT_VID_CPU0__CURRENT_VID__SHIFT 0x0
++#define CURRENT_VID_CPU1__CURRENT_VID_MASK 0xff
++#define CURRENT_VID_CPU1__CURRENT_VID__SHIFT 0x0
++#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE_MASK 0x1f
++#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE__SHIFT 0x0
++#define UNBPM_PWRMGT_ACK__REQUEST_ACK_MASK 0x100
++#define UNBPM_PWRMGT_ACK__REQUEST_ACK__SHIFT 0x8
++#define UNBPM_PWRMGT_ACK__REQUEST_NACK_MASK 0x10000
++#define UNBPM_PWRMGT_ACK__REQUEST_NACK__SHIFT 0x10
++#define UNBPM_PWRMGT_ACK__ERROR_CODE_MASK 0xff000000
++#define UNBPM_PWRMGT_ACK__ERROR_CODE__SHIFT 0x18
++#define CURRENT_FREQ_STATE_NB__CURRENT_FID_MASK 0xff
++#define CURRENT_FREQ_STATE_NB__CURRENT_FID__SHIFT 0x0
++#define CURRENT_FREQ_STATE_NB__CURRENT_DID_MASK 0xff00
++#define CURRENT_FREQ_STATE_NB__CURRENT_DID__SHIFT 0x8
++#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER_MASK 0xff0000
++#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER__SHIFT 0x10
++#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE_MASK 0xff000000
++#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE__SHIFT 0x18
++#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID_MASK 0xff
++#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID__SHIFT 0x0
++#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO_MASK 0x100
++#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO__SHIFT 0x8
++#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID_MASK 0x200
++#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID__SHIFT 0x9
++#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR_MASK 0xffffffff
++#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR__SHIFT 0x0
++#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK_MASK 0x3
++#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK__SHIFT 0x0
++#define UNBPM_NBPWRMGT_CMD__TARGET_CMD_MASK 0x100
++#define UNBPM_NBPWRMGT_CMD__TARGET_CMD__SHIFT 0x8
++#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP_MASK 0xff0000
++#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP__SHIFT 0x10
++#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK_MASK 0x1000000
++#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK__SHIFT 0x18
++#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS_MASK 0x2000000
++#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS__SHIFT 0x19
++#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER_MASK 0x4000000
++#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER__SHIFT 0x1a
++#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE_MASK 0x8000000
++#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE__SHIFT 0x1b
++#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK 0x2
++#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT__SHIFT 0x1
++#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1
++#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0
++#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR_MASK 0x7ff
++#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR__SHIFT 0x0
++#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1
++#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0
++#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR_MASK 0x7ff
++#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR__SHIFT 0x0
++#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK_MASK 0x1
++#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK__SHIFT 0x0
++#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0_MASK 0x1
++#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0__SHIFT 0x0
++#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1_MASK 0x2
++#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1__SHIFT 0x1
++#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0_MASK 0x4
++#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0__SHIFT 0x2
++#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1_MASK 0x8
++#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1__SHIFT 0x3
++#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0_MASK 0x10
++#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0__SHIFT 0x4
++#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1_MASK 0x20
++#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1__SHIFT 0x5
++#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff
++#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0
++#define MISC_GNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1
++#define MISC_GNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0
++#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe
++#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1
++#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000
++#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11
++#define MISC_SMU_PWRMGT_CFG1__TIMER_EN_MASK 0x1
++#define MISC_SMU_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0
++#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe
++#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1
++#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000
++#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11
++#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE_MASK 0x1
++#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE__SHIFT 0x0
++#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES_MASK 0x2
++#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES__SHIFT 0x1
++#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE_MASK 0x4
++#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE__SHIFT 0x2
++#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER_MASK 0x78
++#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER__SHIFT 0x3
++#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS_MASK 0x80
++#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS__SHIFT 0x7
++#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE_MASK 0x100
++#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE__SHIFT 0x8
++#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE_MASK 0x200
++#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE__SHIFT 0x9
++#define GN_GNB_SLOW__GN_GNB_SLOW_DATA_MASK 0x1
++#define GN_GNB_SLOW__GN_GNB_SLOW_DATA__SHIFT 0x0
++#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA_MASK 0x1
++#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA__SHIFT 0x0
++#define MISC_SMU_PWRMGT_DATA__NB_NBPS_MASK 0x1
++#define MISC_SMU_PWRMGT_DATA__NB_NBPS__SHIFT 0x0
++#define MISC_SMU_PWRMGT_DATA__NB_MEMPS_MASK 0x2
++#define MISC_SMU_PWRMGT_DATA__NB_MEMPS__SHIFT 0x1
++#define NB_COF__NB_COF_MASK 0xffff
++#define NB_COF__NB_COF__SHIFT 0x0
++#define UNBPM_CK_IRESET__CK_IRESET_LOCAL_MASK 0x1
++#define UNBPM_CK_IRESET__CK_IRESET_LOCAL__SHIFT 0x0
++#define CURRENT_VID_NB__CURRENT_VID_MASK 0xff
++#define CURRENT_VID_NB__CURRENT_VID__SHIFT 0x0
++#define SPR_FUSE_PSTATEPWR1__PwrValue0_MASK 0xff
++#define SPR_FUSE_PSTATEPWR1__PwrValue0__SHIFT 0x0
++#define SPR_FUSE_PSTATEPWR1__PwrValue1_MASK 0xff00
++#define SPR_FUSE_PSTATEPWR1__PwrValue1__SHIFT 0x8
++#define SPR_FUSE_PSTATEPWR1__PwrValue2_MASK 0xff0000
++#define SPR_FUSE_PSTATEPWR1__PwrValue2__SHIFT 0x10
++#define SPR_FUSE_PSTATEPWR1__PwrValue3_MASK 0xff000000
++#define SPR_FUSE_PSTATEPWR1__PwrValue3__SHIFT 0x18
++#define SPR_FUSE_PSTATEPWR2__PwrValue4_MASK 0xff
++#define SPR_FUSE_PSTATEPWR2__PwrValue4__SHIFT 0x0
++#define SPR_FUSE_PSTATEPWR2__PwrDiv0_MASK 0x300
++#define SPR_FUSE_PSTATEPWR2__PwrDiv0__SHIFT 0x8
++#define SPR_FUSE_PSTATEPWR2__PwrDiv1_MASK 0xc00
++#define SPR_FUSE_PSTATEPWR2__PwrDiv1__SHIFT 0xa
++#define SPR_FUSE_PSTATEPWR2__PwrDiv2_MASK 0x3000
++#define SPR_FUSE_PSTATEPWR2__PwrDiv2__SHIFT 0xc
++#define SPR_FUSE_PSTATEPWR2__PwrDiv3_MASK 0xc000
++#define SPR_FUSE_PSTATEPWR2__PwrDiv3__SHIFT 0xe
++#define SPR_FUSE_PSTATEPWR2__PwrDiv4_MASK 0x30000
++#define SPR_FUSE_PSTATEPWR2__PwrDiv4__SHIFT 0x10
++#define SPR_FUSE_PSTATEPWR2__PwrDiv5_MASK 0xc0000
++#define SPR_FUSE_PSTATEPWR2__PwrDiv5__SHIFT 0x12
++#define SPR_FUSE_PSTATEPWR2__PwrDiv6_MASK 0x300000
++#define SPR_FUSE_PSTATEPWR2__PwrDiv6__SHIFT 0x14
++#define SPR_FUSE_PSTATEPWR2__PwrDiv7_MASK 0xc00000
++#define SPR_FUSE_PSTATEPWR2__PwrDiv7__SHIFT 0x16
++#define SPR_FUSE_PSTATEPWR2__Reserved_MASK 0xff000000
++#define SPR_FUSE_PSTATEPWR2__Reserved__SHIFT 0x18
++#define SPR_FUSE_PSTATEPWR3__PwrValue5_MASK 0xff
++#define SPR_FUSE_PSTATEPWR3__PwrValue5__SHIFT 0x0
++#define SPR_FUSE_PSTATEPWR3__PwrValue6_MASK 0xff00
++#define SPR_FUSE_PSTATEPWR3__PwrValue6__SHIFT 0x8
++#define SPR_FUSE_PSTATEPWR3__PwrValue7_MASK 0xff0000
++#define SPR_FUSE_PSTATEPWR3__PwrValue7__SHIFT 0x10
++#define SPR_FUSE_PSTATEPWR3__Reserved_MASK 0xff000000
++#define SPR_FUSE_PSTATEPWR3__Reserved__SHIFT 0x18
++#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch_MASK 0xffffffff
++#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch__SHIFT 0x0
++#define SPR_PRODUCT_INFO0__BrandId_MASK 0xffff
++#define SPR_PRODUCT_INFO0__BrandId__SHIFT 0x0
++#define SPR_PRODUCT_INFO0__Reserved0_MASK 0x70000
++#define SPR_PRODUCT_INFO0__Reserved0__SHIFT 0x10
++#define SPR_PRODUCT_INFO0__SerialNumRdDis_MASK 0x80000
++#define SPR_PRODUCT_INFO0__SerialNumRdDis__SHIFT 0x13
++#define SPR_PRODUCT_INFO0__Reserved1_MASK 0xfff00000
++#define SPR_PRODUCT_INFO0__Reserved1__SHIFT 0x14
++#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1_MASK 0xffffffff
++#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1__SHIFT 0x0
++#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2_MASK 0xffffffff
++#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2__SHIFT 0x0
++#define SPR_PRODUCT_INFO1__DiDtMode_MASK 0x1
++#define SPR_PRODUCT_INFO1__DiDtMode__SHIFT 0x0
++#define SPR_PRODUCT_INFO1__DiDtCfg0_MASK 0x3e
++#define SPR_PRODUCT_INFO1__DiDtCfg0__SHIFT 0x1
++#define SPR_PRODUCT_INFO1__DiDtCfg1_MASK 0x3fc0
++#define SPR_PRODUCT_INFO1__DiDtCfg1__SHIFT 0x6
++#define SPR_PRODUCT_INFO1__DiDtCfg2_MASK 0xc000
++#define SPR_PRODUCT_INFO1__DiDtCfg2__SHIFT 0xe
++#define SPR_PRODUCT_INFO1__DiDtCfg3_MASK 0x10000
++#define SPR_PRODUCT_INFO1__DiDtCfg3__SHIFT 0x10
++#define SPR_PRODUCT_INFO1__DiDtCfg4_MASK 0x1e0000
++#define SPR_PRODUCT_INFO1__DiDtCfg4__SHIFT 0x11
++#define SPR_PRODUCT_INFO1__Reserved_MASK 0xffe00000
++#define SPR_PRODUCT_INFO1__Reserved__SHIFT 0x15
++#define SPR_EXT_PRODUCT_INFO__Reserved_MASK 0xffffffff
++#define SPR_EXT_PRODUCT_INFO__Reserved__SHIFT 0x0
++#define SPR_MSIDFUSE__MSID_MASK 0xffffff
++#define SPR_MSIDFUSE__MSID__SHIFT 0x0
++#define SPR_MSIDFUSE__Reserved_MASK 0xff000000
++#define SPR_MSIDFUSE__Reserved__SHIFT 0x18
++#define SPR_LINK_PRODUCT_INFO__Reserved_MASK 0xffffffff
++#define SPR_LINK_PRODUCT_INFO__Reserved__SHIFT 0x0
++#define SPR_BRAND_NAME_ADDR__Index_MASK 0xf
++#define SPR_BRAND_NAME_ADDR__Index__SHIFT 0x0
++#define SPR_BRAND_NAME_ADDR__Reserved_MASK 0xfffffff0
++#define SPR_BRAND_NAME_ADDR__Reserved__SHIFT 0x4
++#define SPR_BRAND_NAME_DATA__DATA_MASK 0xffffffff
++#define SPR_BRAND_NAME_DATA__DATA__SHIFT 0x0
++#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO_MASK 0xffffffff
++#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO__SHIFT 0x0
++#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff
++#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0
++#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE_MASK 0x1
++#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE__SHIFT 0x0
++#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE_MASK 0x1
++#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE__SHIFT 0x0
++#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK 0x2
++#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE__SHIFT 0x1
++#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN_MASK 0x1
++#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN__SHIFT 0x0
++#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL_MASK 0x1fe
++#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL__SHIFT 0x1
++#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS_MASK 0x1
++#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS__SHIFT 0x0
++#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
++#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
++#define NUM_BOOST_STATES__NUM_BOOST_STATES_MASK 0x7
++#define NUM_BOOST_STATES__NUM_BOOST_STATES__SHIFT 0x0
++#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID_MASK 0xff
++#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID__SHIFT 0x0
++#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE_MASK 0xff00
++#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE__SHIFT 0x8
++#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND_MASK 0x1
++#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND__SHIFT 0x0
++#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK 0x2
++#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0__SHIFT 0x1
++#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1_MASK 0x4
++#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT 0x2
++#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime_MASK 0x3
++#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime__SHIFT 0x0
++#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime_MASK 0xc
++#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime__SHIFT 0x2
++#define SPR_PROGRAMMABLE_CTRL__ResonanceTime_MASK 0x30
++#define SPR_PROGRAMMABLE_CTRL__ResonanceTime__SHIFT 0x4
++#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg_MASK 0x40
++#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg__SHIFT 0x6
++#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO_MASK 0x80
++#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO__SHIFT 0x7
++#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg_MASK 0x100
++#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg__SHIFT 0x8
++#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg_MASK 0x200
++#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg__SHIFT 0x9
++#define SPR_PROGRAMMABLE_CTRL__SOIWait_MASK 0x3c00
++#define SPR_PROGRAMMABLE_CTRL__SOIWait__SHIFT 0xa
++#define PHN_FUSERX_MISC_FUSES__Spare_MASK 0xff
++#define PHN_FUSERX_MISC_FUSES__Spare__SHIFT 0x0
++#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis_MASK 0x100
++#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis__SHIFT 0x8
++#define PHN_FUSERX_MISC_FUSES__MemPstate_MASK 0x1e00
++#define PHN_FUSERX_MISC_FUSES__MemPstate__SHIFT 0x9
++#define PHN_FUSERX_MISC_FUSES__NbPstateHi_MASK 0x6000
++#define PHN_FUSERX_MISC_FUSES__NbPstateHi__SHIFT 0xd
++#define PHN_FUSERX_MISC_FUSES__NbPstateLo_MASK 0x18000
++#define PHN_FUSERX_MISC_FUSES__NbPstateLo__SHIFT 0xf
++#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz_MASK 0x20000
++#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz__SHIFT 0x11
++#define PHN_FUSERX_MISC_FUSES__CoreDis_MASK 0x3c0000
++#define PHN_FUSERX_MISC_FUSES__CoreDis__SHIFT 0x12
++#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid_MASK 0x80000000
++#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid__SHIFT 0x1f
++#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS_MASK 0x1
++#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS__SHIFT 0x0
++#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME_MASK 0x1f
++#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME__SHIFT 0x0
++#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS_MASK 0xf
++#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS__SHIFT 0x0
++#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH_MASK 0x10
++#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH__SHIFT 0x4
++#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN_MASK 0x20
++#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN__SHIFT 0x5
++#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE_MASK 0x100
++#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE__SHIFT 0x8
++#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY_MASK 0x200
++#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY__SHIFT 0x9
++#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT_MASK 0x3c00
++#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT__SHIFT 0xa
++#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS_MASK 0xff0000
++#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS__SHIFT 0x10
++#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD_MASK 0xffffffff
++#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD__SHIFT 0x0
++#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT_MASK 0xffff
++#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT__SHIFT 0x0
++#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT_MASK 0xffff0000
++#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT__SHIFT 0x10
++#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN_MASK 0x1
++#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN__SHIFT 0x0
++#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM_MASK 0x1fe
++#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM__SHIFT 0x1
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb_MASK 0x1
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb__SHIFT 0x0
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct_MASK 0x6
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct__SHIFT 0x1
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu_MASK 0x38
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu__SHIFT 0x3
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog_MASK 0x40
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog__SHIFT 0x6
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo_MASK 0x80
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo__SHIFT 0x7
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate_MASK 0x100
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate__SHIFT 0x8
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid_MASK 0x7e00
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid__SHIFT 0x9
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid_MASK 0x38000
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid__SHIFT 0xf
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate_MASK 0x40000
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate__SHIFT 0x12
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId_MASK 0x380000
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId__SHIFT 0x13
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn_MASK 0x400000
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn__SHIFT 0x16
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn_MASK 0x800000
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn__SHIFT 0x17
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding_MASK 0x7000000
++#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding__SHIFT 0x18
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid_MASK 0x1
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid__SHIFT 0x0
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane_MASK 0x6
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane__SHIFT 0x1
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp_MASK 0x8
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp__SHIFT 0x3
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid_MASK 0xff0
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid__SHIFT 0x4
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime_MASK 0x7000
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime__SHIFT 0xc
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy_MASK 0x10000
++#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy__SHIFT 0x10
++#define UNBPM_SCRATCH_0__DATA_MASK 0xffffffff
++#define UNBPM_SCRATCH_0__DATA__SHIFT 0x0
++#define UNBPM_SCRATCH_1__DATA_MASK 0xffffffff
++#define UNBPM_SCRATCH_1__DATA__SHIFT 0x0
++#define POWERON_CPU_0__POWERON_MASK 0x1
++#define POWERON_CPU_0__POWERON__SHIFT 0x0
++#define POWERREADY_CPU_0__POWERREADY_MASK 0x1
++#define POWERREADY_CPU_0__POWERREADY__SHIFT 0x0
++#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK_MASK 0x1
++#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK__SHIFT 0x0
++#define RCC3ON_CPU_0__CK_RCC3ON_MASK 0x1
++#define RCC3ON_CPU_0__CK_RCC3ON__SHIFT 0x0
++#define RCC3ON_CPU_0__RCC3_PSM_EN_MASK 0x2
++#define RCC3ON_CPU_0__RCC3_PSM_EN__SHIFT 0x1
++#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV_MASK 0xc
++#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT 0x2
++#define RCC3ON_CPU_0__RCC3_AVG_EN_MASK 0x10
++#define RCC3ON_CPU_0__RCC3_AVG_EN__SHIFT 0x4
++#define RCC3ON_CPU_0__RCC3_AVG_DIV_MASK 0x7e0
++#define RCC3ON_CPU_0__RCC3_AVG_DIV__SHIFT 0x5
++#define RCC3ON_CPU_0__RCC3_DIDT_TIMER_MASK 0x1f800
++#define RCC3ON_CPU_0__RCC3_DIDT_TIMER__SHIFT 0xb
++#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000
++#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0__SHIFT 0x11
++#define RCC3EXITDONE_CPU_0__RCC3EXITDONE_MASK 0x1
++#define RCC3EXITDONE_CPU_0__RCC3EXITDONE__SHIFT 0x0
++#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER_MASK 0x1
++#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0
++#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR_MASK 0x7ff
++#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR__SHIFT 0x0
++#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000
++#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR__SHIFT 0x10
++#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER_MASK 0x1
++#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0
++#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR_MASK 0x7ff
++#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR__SHIFT 0x0
++#define CORE_APM_SSB_XFER_0__START_STATUS_XFER_MASK 0x1
++#define CORE_APM_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0
++#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR_MASK 0x7ff
++#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR__SHIFT 0x0
++#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS_MASK 0x1
++#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS__SHIFT 0x0
++#define LDOIVRON_CPU_0__CK_LDOIVRON_MASK 0x1
++#define LDOIVRON_CPU_0__CK_LDOIVRON__SHIFT 0x0
++#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE_MASK 0x1
++#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE__SHIFT 0x0
++#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF_MASK 0x3fff
++#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF__SHIFT 0x0
++#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF_MASK 0x3fff
++#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF__SHIFT 0x0
++#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED_MASK 0x1
++#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED__SHIFT 0x0
++#define CK_DISABLECORE_CPU_0__CK_DISABLECORE_MASK 0x1
++#define CK_DISABLECORE_CPU_0__CK_DISABLECORE__SHIFT 0x0
++#define COREPM_ID_0__COREPM_INDEX_MASK 0x1
++#define COREPM_ID_0__COREPM_INDEX__SHIFT 0x0
++#define COREPM_SCRATCH_0__SCRATCH_DATA_MASK 0xffffffff
++#define COREPM_SCRATCH_0__SCRATCH_DATA__SHIFT 0x0
++#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15_MASK 0xffffffff
++#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15__SHIFT 0x0
++#define SPMI_CONFIG0_0__SPMI_ENABLE_MASK 0x1
++#define SPMI_CONFIG0_0__SPMI_ENABLE__SHIFT 0x0
++#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c
++#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2
++#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80
++#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7
++#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000
++#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc
++#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000
++#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11
++#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000
++#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16
++#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f
++#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0
++#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE_MASK 0xffe0
++#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE__SHIFT 0x5
++#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER_MASK 0x1
++#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER__SHIFT 0x0
++#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER_MASK 0x1
++#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER__SHIFT 0x0
++#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER_MASK 0x1
++#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER__SHIFT 0x0
++#define SPMI_FSM_BUSY_0__FSM_BUSY_MASK 0x1
++#define SPMI_FSM_BUSY_0__FSM_BUSY__SHIFT 0x0
++#define SPMI_PATH_0__PATH_ENABLE_REQ_MASK 0x1
++#define SPMI_PATH_0__PATH_ENABLE_REQ__SHIFT 0x0
++#define SPMI_PATH_0__PATH_ENABLE_ACK_MASK 0x2
++#define SPMI_PATH_0__PATH_ENABLE_ACK__SHIFT 0x1
++#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear_MASK 0x10
++#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4
++#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_MASK 0x1
++#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0
++#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2
++#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1
++#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc
++#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2
++#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1
++#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0
++#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS_MASK 0xffffffff
++#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS__SHIFT 0x0
++#define SPMI_SRAM_DATA_0__SRAM_DATA_MASK 0xffffffff
++#define SPMI_SRAM_DATA_0__SRAM_DATA__SHIFT 0x0
++#define SPMI_RESET_0__ASYNC_RESET_0_MASK 0x1
++#define SPMI_RESET_0__ASYNC_RESET_0__SHIFT 0x0
++#define SPMI_RESET_0__SYNC_RESET_MASK 0x80000000
++#define SPMI_RESET_0__SYNC_RESET__SHIFT 0x1f
++#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE_MASK 0x1
++#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE__SHIFT 0x0
++#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE_MASK 0x100
++#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8
++#define SPMI_SPARE_0__SPARE_DATA_MASK 0xffffffff
++#define SPMI_SPARE_0__SPARE_DATA__SHIFT 0x0
++#define SPMI_SPARE_EX_0__SPARE_DATA_EX_MASK 0xffffffff
++#define SPMI_SPARE_EX_0__SPARE_DATA_EX__SHIFT 0x0
++#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN_MASK 0x1
++#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN__SHIFT 0x0
++#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER_MASK 0x7fe
++#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER__SHIFT 0x1
++#define POWERON_CPU_1__POWERON_MASK 0x1
++#define POWERON_CPU_1__POWERON__SHIFT 0x0
++#define POWERREADY_CPU_1__POWERREADY_MASK 0x1
++#define POWERREADY_CPU_1__POWERREADY__SHIFT 0x0
++#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK_MASK 0x1
++#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK__SHIFT 0x0
++#define RCC3ON_CPU_1__CK_RCC3ON_MASK 0x1
++#define RCC3ON_CPU_1__CK_RCC3ON__SHIFT 0x0
++#define RCC3ON_CPU_1__RCC3_PSM_EN_MASK 0x2
++#define RCC3ON_CPU_1__RCC3_PSM_EN__SHIFT 0x1
++#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV_MASK 0xc
++#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT 0x2
++#define RCC3ON_CPU_1__RCC3_AVG_EN_MASK 0x10
++#define RCC3ON_CPU_1__RCC3_AVG_EN__SHIFT 0x4
++#define RCC3ON_CPU_1__RCC3_AVG_DIV_MASK 0x7e0
++#define RCC3ON_CPU_1__RCC3_AVG_DIV__SHIFT 0x5
++#define RCC3ON_CPU_1__RCC3_DIDT_TIMER_MASK 0x1f800
++#define RCC3ON_CPU_1__RCC3_DIDT_TIMER__SHIFT 0xb
++#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000
++#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0__SHIFT 0x11
++#define RCC3EXITDONE_CPU_1__RCC3EXITDONE_MASK 0x1
++#define RCC3EXITDONE_CPU_1__RCC3EXITDONE__SHIFT 0x0
++#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER_MASK 0x1
++#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0
++#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR_MASK 0x7ff
++#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR__SHIFT 0x0
++#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000
++#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR__SHIFT 0x10
++#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER_MASK 0x1
++#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0
++#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR_MASK 0x7ff
++#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR__SHIFT 0x0
++#define CORE_APM_SSB_XFER_1__START_STATUS_XFER_MASK 0x1
++#define CORE_APM_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0
++#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR_MASK 0x7ff
++#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR__SHIFT 0x0
++#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS_MASK 0x1
++#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS__SHIFT 0x0
++#define LDOIVRON_CPU_1__CK_LDOIVRON_MASK 0x1
++#define LDOIVRON_CPU_1__CK_LDOIVRON__SHIFT 0x0
++#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE_MASK 0x1
++#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE__SHIFT 0x0
++#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF_MASK 0x3fff
++#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF__SHIFT 0x0
++#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF_MASK 0x3fff
++#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF__SHIFT 0x0
++#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED_MASK 0x1
++#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED__SHIFT 0x0
++#define CK_DISABLECORE_CPU_1__CK_DISABLECORE_MASK 0x1
++#define CK_DISABLECORE_CPU_1__CK_DISABLECORE__SHIFT 0x0
++#define COREPM_ID_1__COREPM_INDEX_MASK 0x1
++#define COREPM_ID_1__COREPM_INDEX__SHIFT 0x0
++#define COREPM_SCRATCH_1__SCRATCH_DATA_MASK 0xffffffff
++#define COREPM_SCRATCH_1__SCRATCH_DATA__SHIFT 0x0
++#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15_MASK 0xffffffff
++#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15__SHIFT 0x0
++#define SPMI_CONFIG0_1__SPMI_ENABLE_MASK 0x1
++#define SPMI_CONFIG0_1__SPMI_ENABLE__SHIFT 0x0
++#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c
++#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2
++#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80
++#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7
++#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000
++#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc
++#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000
++#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11
++#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000
++#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16
++#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f
++#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0
++#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE_MASK 0xffe0
++#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE__SHIFT 0x5
++#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER_MASK 0x1
++#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER__SHIFT 0x0
++#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER_MASK 0x1
++#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER__SHIFT 0x0
++#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER_MASK 0x1
++#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER__SHIFT 0x0
++#define SPMI_FSM_BUSY_1__FSM_BUSY_MASK 0x1
++#define SPMI_FSM_BUSY_1__FSM_BUSY__SHIFT 0x0
++#define SPMI_PATH_1__PATH_ENABLE_REQ_MASK 0x1
++#define SPMI_PATH_1__PATH_ENABLE_REQ__SHIFT 0x0
++#define SPMI_PATH_1__PATH_ENABLE_ACK_MASK 0x2
++#define SPMI_PATH_1__PATH_ENABLE_ACK__SHIFT 0x1
++#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear_MASK 0x10
++#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4
++#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_MASK 0x1
++#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0
++#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2
++#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1
++#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc
++#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2
++#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1
++#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0
++#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS_MASK 0xffffffff
++#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS__SHIFT 0x0
++#define SPMI_SRAM_DATA_1__SRAM_DATA_MASK 0xffffffff
++#define SPMI_SRAM_DATA_1__SRAM_DATA__SHIFT 0x0
++#define SPMI_RESET_1__ASYNC_RESET_0_MASK 0x1
++#define SPMI_RESET_1__ASYNC_RESET_0__SHIFT 0x0
++#define SPMI_RESET_1__SYNC_RESET_MASK 0x80000000
++#define SPMI_RESET_1__SYNC_RESET__SHIFT 0x1f
++#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE_MASK 0x1
++#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE__SHIFT 0x0
++#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE_MASK 0x100
++#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8
++#define SPMI_SPARE_1__SPARE_DATA_MASK 0xffffffff
++#define SPMI_SPARE_1__SPARE_DATA__SHIFT 0x0
++#define SPMI_SPARE_EX_1__SPARE_DATA_EX_MASK 0xffffffff
++#define SPMI_SPARE_EX_1__SPARE_DATA_EX__SHIFT 0x0
++#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN_MASK 0x1
++#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN__SHIFT 0x0
++#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER_MASK 0x7fe
++#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER__SHIFT 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
++#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
++#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
++#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
++#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
++#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
++#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
++#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
++#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
++#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
++#define GENERAL_PWRMGT__SPARE11_MASK 0x800
++#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
++#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
++#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
++#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
++#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
++#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
++#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
++#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
++#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
++#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
++#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
++#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
++#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
++#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
++#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
++#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
++#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
++#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
++#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
++#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
++#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
++#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
++#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
++#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
++#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
++#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
++#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX_MASK 0xf
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX__SHIFT 0x0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX_MASK 0xf0
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX__SHIFT 0x4
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX_MASK 0xf00
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX__SHIFT 0x8
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX_MASK 0xf000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX__SHIFT 0xc
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX_MASK 0xf0000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX__SHIFT 0x10
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX_MASK 0xf00000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX__SHIFT 0x14
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX_MASK 0xf000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX__SHIFT 0x18
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX_MASK 0xf0000000
++#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
++#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
++#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
++#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
++#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
++#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
++#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
++#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
++#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
++#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
++#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
++#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
++#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
++#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
++#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
++#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
++#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
++#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
++#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
++#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
++#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
++#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
++#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
++#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
++#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
++#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
++#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
++#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
++#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
++#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK_MASK 0x20000000
++#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK__SHIFT 0x1d
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
++#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK_MASK 0x200000
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK__SHIFT 0x15
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK_MASK 0x400000
++#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK__SHIFT 0x16
++#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK_MASK 0x800000
++#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK__SHIFT 0x17
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
++#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
++#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
++#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK_MASK 0x10000
++#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK_MASK 0x20000
++#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
++#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
++#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
++#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
++#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
++#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
++#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
++#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
++#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
++#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
++#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
++#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
++#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK_MASK 0x200000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK__SHIFT 0x15
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK_MASK 0x400000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK__SHIFT 0x16
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK_MASK 0x800000
++#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK__SHIFT 0x17
++#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK_MASK 0x1000000
++#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK__SHIFT 0x18
++#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK_MASK 0x2000000
++#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK__SHIFT 0x19
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK_MASK 0x4000000
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK__SHIFT 0x1a
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK_MASK 0x8000000
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK__SHIFT 0x1b
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK_MASK 0x10000000
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK__SHIFT 0x1c
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK_MASK 0x20000000
++#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK__SHIFT 0x1d
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xc0000000
++#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x1e
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
++#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
++#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
++#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
++#define PWR_DC_RESP__RESPONSE_MASK 0x1
++#define PWR_DC_RESP__RESPONSE__SHIFT 0x0
++#define PWR_VCE_RESP__RESPONSE_MASK 0xffffffff
++#define PWR_VCE_RESP__RESPONSE__SHIFT 0x0
++#define PWR_UVD_RESP__RESPONSE_MASK 0xffffffff
++#define PWR_UVD_RESP__RESPONSE__SHIFT 0x0
++#define PWR_ACP_RESP__RESPONSE_MASK 0xffffffff
++#define PWR_ACP_RESP__RESPONSE__SHIFT 0x0
++#define PWR_DC_REQ__REQUEST_MASK 0x1
++#define PWR_DC_REQ__REQUEST__SHIFT 0x0
++#define SCLK_MIN_DIV__FRACV_MASK 0xfff
++#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
++#define SCLK_MIN_DIV__INTV_MASK 0x7f000
++#define SCLK_MIN_DIV__INTV__SHIFT 0xc
++#define PCIE_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
++#define PCIE_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
++#define PCIE_PGFSM_CONFIG__Power_Down_MASK 0x100
++#define PCIE_PGFSM_CONFIG__Power_Down__SHIFT 0x8
++#define PCIE_PGFSM_CONFIG__Power_Up_MASK 0x200
++#define PCIE_PGFSM_CONFIG__Power_Up__SHIFT 0x9
++#define PCIE_PGFSM_CONFIG__P1_Select_MASK 0x400
++#define PCIE_PGFSM_CONFIG__P1_Select__SHIFT 0xa
++#define PCIE_PGFSM_CONFIG__P2_Select_MASK 0x800
++#define PCIE_PGFSM_CONFIG__P2_Select__SHIFT 0xb
++#define PCIE_PGFSM_CONFIG__Write_Op_MASK 0x1000
++#define PCIE_PGFSM_CONFIG__Write_Op__SHIFT 0xc
++#define PCIE_PGFSM_CONFIG__Read_Op_MASK 0x2000
++#define PCIE_PGFSM_CONFIG__Read_Op__SHIFT 0xd
++#define PCIE_PGFSM_CONFIG__Reserved_MASK 0xfffc000
++#define PCIE_PGFSM_CONFIG__Reserved__SHIFT 0xe
++#define PCIE_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
++#define PCIE_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
++#define PCIE_PGFSM_WRITE__Write_value_MASK 0xffffffff
++#define PCIE_PGFSM_WRITE__Write_value__SHIFT 0x0
++#define SERDES_BUSY__PCIE_SERDES_BUSY_MASK 0x1
++#define SERDES_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0
++#define PCIE_PGFSM2_CONFIG__FSM_ADDR_MASK 0xff
++#define PCIE_PGFSM2_CONFIG__FSM_ADDR__SHIFT 0x0
++#define PCIE_PGFSM2_CONFIG__Power_Down_MASK 0x100
++#define PCIE_PGFSM2_CONFIG__Power_Down__SHIFT 0x8
++#define PCIE_PGFSM2_CONFIG__Power_Up_MASK 0x200
++#define PCIE_PGFSM2_CONFIG__Power_Up__SHIFT 0x9
++#define PCIE_PGFSM2_CONFIG__P1_Select_MASK 0x400
++#define PCIE_PGFSM2_CONFIG__P1_Select__SHIFT 0xa
++#define PCIE_PGFSM2_CONFIG__P2_Select_MASK 0x800
++#define PCIE_PGFSM2_CONFIG__P2_Select__SHIFT 0xb
++#define PCIE_PGFSM2_CONFIG__Write_Op_MASK 0x1000
++#define PCIE_PGFSM2_CONFIG__Write_Op__SHIFT 0xc
++#define PCIE_PGFSM2_CONFIG__Read_Op_MASK 0x2000
++#define PCIE_PGFSM2_CONFIG__Read_Op__SHIFT 0xd
++#define PCIE_PGFSM2_CONFIG__Reserved_MASK 0xfffc000
++#define PCIE_PGFSM2_CONFIG__Reserved__SHIFT 0xe
++#define PCIE_PGFSM2_CONFIG__REG_ADDR_MASK 0xf0000000
++#define PCIE_PGFSM2_CONFIG__REG_ADDR__SHIFT 0x1c
++#define PCIE_PGFSM2_WRITE__Write_value_MASK 0xffffffff
++#define PCIE_PGFSM2_WRITE__Write_value__SHIFT 0x0
++#define SERDES2_BUSY__PCIE_SERDES_BUSY_MASK 0x1
++#define SERDES2_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0
++#define PCIE_PGFSM_0_READ__Read_value_MASK 0xffffff
++#define PCIE_PGFSM_0_READ__Read_value__SHIFT 0x0
++#define PCIE_PGFSM_0_READ__Read_valid_MASK 0x1000000
++#define PCIE_PGFSM_0_READ__Read_valid__SHIFT 0x18
++#define PCIE_PGFSM_1_READ__Read_value_MASK 0xffffff
++#define PCIE_PGFSM_1_READ__Read_value__SHIFT 0x0
++#define PCIE_PGFSM_1_READ__Read_valid_MASK 0x1000000
++#define PCIE_PGFSM_1_READ__Read_valid__SHIFT 0x18
++#define PWR_ACPI_INTERRUPT__BIF_CG_req_MASK 0x1
++#define PWR_ACPI_INTERRUPT__BIF_CG_req__SHIFT 0x0
++#define PWR_ACPI_INTERRUPT__AZ_CG_req_MASK 0x2
++#define PWR_ACPI_INTERRUPT__AZ_CG_req__SHIFT 0x1
++#define PWR_ACPI_INTERRUPT__AZ_CG_resp_MASK 0x4
++#define PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT 0x2
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
++#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
++#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
++#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
++#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
++#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
++#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
++#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
++#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
++#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit_MASK 0x1
++#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit__SHIFT 0x0
++#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4_MASK 0xffff
++#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4__SHIFT 0x0
++#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5_MASK 0xffff0000
++#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5__SHIFT 0x10
++#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
++#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
++#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
++#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
++#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
++#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
++#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
++#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
++#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
++#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
++#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
++#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
++#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
++#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
++#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
++#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
++#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
++#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
++#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
++#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
++#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff
++#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0
++#define MISC_UNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1
++#define MISC_UNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0
++#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe
++#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1
++#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000
++#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11
++#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER_MASK 0xf
++#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER__SHIFT 0x0
++#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH_MASK 0x10
++#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH__SHIFT 0x4
++#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE_MASK 0x20
++#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE__SHIFT 0x5
++#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE_MASK 0x40
++#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE__SHIFT 0x6
++#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK_MASK 0x80
++#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK__SHIFT 0x7
++#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK_MASK 0x100
++#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK__SHIFT 0x8
++#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK_MASK 0x200
++#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK__SHIFT 0x9
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6_MASK 0x1
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6__SHIFT 0x0
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK 0x2
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive__SHIFT 0x1
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt_MASK 0x4
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT 0x2
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE_MASK 0xf8
++#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE__SHIFT 0x3
++#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN_MASK 0x1
++#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN__SHIFT 0x0
++#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD_MASK 0x1fffe
++#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD__SHIFT 0x1
++#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT_MASK 0x60000
++#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT__SHIFT 0x11
++#define SOUTHBRIDGE_TYPE__DISCRETE_SB_MASK 0x1
++#define SOUTHBRIDGE_TYPE__DISCRETE_SB__SHIFT 0x0
++#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6_MASK 0x1
++#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6__SHIFT 0x0
++#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK 0x2
++#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive__SHIFT 0x1
++#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt_MASK 0x4
++#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT 0x2
++#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit_MASK 0x8
++#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit__SHIFT 0x3
++#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh_MASK 0x10
++#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh__SHIFT 0x4
++#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate_MASK 0x20
++#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate__SHIFT 0x5
++#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate_MASK 0x40
++#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate__SHIFT 0x6
++#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh_MASK 0x80
++#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh__SHIFT 0x7
++#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake_MASK 0x100
++#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake__SHIFT 0x8
++#define GNBPM_SMU_PWRMGT_STATUS__SPARE_MASK 0xfe00
++#define GNBPM_SMU_PWRMGT_STATUS__SPARE__SHIFT 0x9
++#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL_MASK 0x3
++#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL__SHIFT 0x0
++#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xffffffff
++#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0
++#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xffffffff
++#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0
++#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0xffff
++#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
++#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000
++#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10
++#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0xffff
++#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0
++#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000
++#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10
++#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0xffff
++#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0
++#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000
++#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10
++#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0xffff
++#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0
++#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000
++#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10
++#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffff
++#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
++#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0xffff
++#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
++#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000
++#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
++
++#endif /* SMU_8_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0024-yocto-amd-drm-amdgpu-add-SMU-7-0-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0024-yocto-amd-drm-amdgpu-add-SMU-7-0-0-register-headers.patch
new file mode 100644
index 00000000..8f753f71
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0024-yocto-amd-drm-amdgpu-add-SMU-7-0-0-register-headers.patch
@@ -0,0 +1,921 @@
+From 5ba38ac32645e56090d9939df74ab9bef3675fa5 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:33:44 -0400
+Subject: drm/amdgpu: add UVD 4.2 register headers
+
+These are register headers for the UVD (Universal Video Decoder)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h
+new file mode 100644
+index 0000000..f3e53b1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h
+@@ -0,0 +1,95 @@
++/*
++ * UVD_4_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_4_2_D_H
++#define UVD_4_2_D_H
++
++#define mmUVD_SEMA_ADDR_LOW                                                     0x3bc0
++#define mmUVD_SEMA_ADDR_HIGH                                                    0x3bc1
++#define mmUVD_SEMA_CMD                                                          0x3bc2
++#define mmUVD_GPCOM_VCPU_CMD                                                    0x3bc3
++#define mmUVD_GPCOM_VCPU_DATA0                                                  0x3bc4
++#define mmUVD_GPCOM_VCPU_DATA1                                                  0x3bc5
++#define mmUVD_ENGINE_CNTL                                                       0x3bc6
++#define mmUVD_UDEC_ADDR_CONFIG                                                  0x3bd3
++#define mmUVD_UDEC_DB_ADDR_CONFIG                                               0x3bd4
++#define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5
++#define mmUVD_SEMA_CNTL                                                         0x3d00
++#define mmUVD_LMI_EXT40_ADDR                                                    0x3d26
++#define mmUVD_CTX_INDEX                                                         0x3d28
++#define mmUVD_CTX_DATA                                                          0x3d29
++#define mmUVD_CGC_GATE                                                          0x3d2a
++#define mmUVD_CGC_STATUS                                                        0x3d2b
++#define mmUVD_CGC_CTRL                                                          0x3d2c
++#define mmUVD_CGC_UDEC_STATUS                                                   0x3d2d
++#define mmUVD_LMI_CTRL2                                                         0x3d3d
++#define mmUVD_MASTINT_EN                                                        0x3d40
++#define mmUVD_LMI_ADDR_EXT                                                      0x3d65
++#define mmUVD_LMI_CTRL                                                          0x3d66
++#define mmUVD_LMI_STATUS                                                        0x3d67
++#define mmUVD_LMI_SWAP_CNTL                                                     0x3d6d
++#define mmUVD_MP_SWAP_CNTL                                                      0x3d6f
++#define mmUVD_MPC_CNTL                                                          0x3d77
++#define mmUVD_MPC_SET_MUXA0                                                     0x3d79
++#define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
++#define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
++#define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
++#define mmUVD_MPC_SET_MUX                                                       0x3d7d
++#define mmUVD_MPC_SET_ALU                                                       0x3d7e
++#define mmUVD_VCPU_CACHE_OFFSET0                                                0x3d82
++#define mmUVD_VCPU_CACHE_SIZE0                                                  0x3d83
++#define mmUVD_VCPU_CACHE_OFFSET1                                                0x3d84
++#define mmUVD_VCPU_CACHE_SIZE1                                                  0x3d85
++#define mmUVD_VCPU_CACHE_OFFSET2                                                0x3d86
++#define mmUVD_VCPU_CACHE_SIZE2                                                  0x3d87
++#define mmUVD_VCPU_CNTL                                                         0x3d98
++#define mmUVD_SOFT_RESET                                                        0x3da0
++#define mmUVD_RBC_IB_BASE                                                       0x3da1
++#define mmUVD_RBC_IB_SIZE                                                       0x3da2
++#define mmUVD_RBC_RB_BASE                                                       0x3da3
++#define mmUVD_RBC_RB_RPTR                                                       0x3da4
++#define mmUVD_RBC_RB_WPTR                                                       0x3da5
++#define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
++#define mmUVD_RBC_RB_CNTL                                                       0x3da9
++#define mmUVD_RBC_RB_RPTR_ADDR                                                  0x3daa
++#define mmUVD_STATUS                                                            0x3daf
++#define mmUVD_SEMA_TIMEOUT_STATUS                                               0x3db0
++#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                 0x3db1
++#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                      0x3db2
++#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                               0x3db3
++#define mmUVD_CONTEXT_ID                                                        0x3dbd
++#define mmUVD_RBC_IB_SIZE_UPDATE                                                0x3df1
++#define ixUVD_LMI_CACHE_CTRL                                                    0x9b
++#define ixUVD_LMI_SWAP_CNTL2                                                    0xaa
++#define ixUVD_LMI_ADDR_EXT2                                                     0xab
++#define ixUVD_CGC_MEM_CTRL                                                      0xc0
++#define ixUVD_CGC_CTRL2                                                         0xc1
++#define mmUVD_PGFSM_CONFIG                                                      0x38f8
++#define mmUVD_PGFSM_READ_TILE1                                                  0x38fa
++#define mmUVD_PGFSM_READ_TILE2                                                  0x38fb
++#define mmUVD_POWER_STATUS                                                      0x38fc
++#define ixUVD_MIF_CURR_ADDR_CONFIG                                              0x48
++#define ixUVD_MIF_REF_ADDR_CONFIG                                               0x4c
++#define ixUVD_MIF_RECON1_ADDR_CONFIG                                            0x114
++
++#endif /* UVD_4_2_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
+new file mode 100644
+index 0000000..65e8be9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
+@@ -0,0 +1,800 @@
++/*
++ * UVD_4_2 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_4_2_SH_MASK_H
++#define UVD_4_2_SH_MASK_H
++
++#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
++#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
++#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
++#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
++#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
++#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
++#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
++#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
++#define UVD_SEMA_CMD__MODE_MASK 0x40
++#define UVD_SEMA_CMD__MODE__SHIFT 0x6
++#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
++#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
++#define UVD_SEMA_CMD__VMID_MASK 0xf00
++#define UVD_SEMA_CMD__VMID__SHIFT 0x8
++#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
++#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
++#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
++#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
++#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
++#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
++#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
++#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
++#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
++#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
++#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
++#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
++#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
++#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
++#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
++#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
++#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
++#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
++#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
++#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
++#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
++#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
++#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
++#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
++#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
++#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
++#define UVD_CTX_DATA__DATA_MASK 0xffffffff
++#define UVD_CTX_DATA__DATA__SHIFT 0x0
++#define UVD_CGC_GATE__SYS_MASK 0x1
++#define UVD_CGC_GATE__SYS__SHIFT 0x0
++#define UVD_CGC_GATE__UDEC_MASK 0x2
++#define UVD_CGC_GATE__UDEC__SHIFT 0x1
++#define UVD_CGC_GATE__MPEG2_MASK 0x4
++#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
++#define UVD_CGC_GATE__REGS_MASK 0x8
++#define UVD_CGC_GATE__REGS__SHIFT 0x3
++#define UVD_CGC_GATE__RBC_MASK 0x10
++#define UVD_CGC_GATE__RBC__SHIFT 0x4
++#define UVD_CGC_GATE__LMI_MC_MASK 0x20
++#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
++#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
++#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
++#define UVD_CGC_GATE__IDCT_MASK 0x80
++#define UVD_CGC_GATE__IDCT__SHIFT 0x7
++#define UVD_CGC_GATE__MPRD_MASK 0x100
++#define UVD_CGC_GATE__MPRD__SHIFT 0x8
++#define UVD_CGC_GATE__MPC_MASK 0x200
++#define UVD_CGC_GATE__MPC__SHIFT 0x9
++#define UVD_CGC_GATE__LBSI_MASK 0x400
++#define UVD_CGC_GATE__LBSI__SHIFT 0xa
++#define UVD_CGC_GATE__LRBBM_MASK 0x800
++#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
++#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
++#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
++#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
++#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
++#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
++#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
++#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
++#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
++#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
++#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
++#define UVD_CGC_GATE__WCB_MASK 0x20000
++#define UVD_CGC_GATE__WCB__SHIFT 0x11
++#define UVD_CGC_GATE__VCPU_MASK 0x40000
++#define UVD_CGC_GATE__VCPU__SHIFT 0x12
++#define UVD_CGC_GATE__SCPU_MASK 0x80000
++#define UVD_CGC_GATE__SCPU__SHIFT 0x13
++#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
++#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
++#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
++#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
++#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
++#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
++#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
++#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
++#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
++#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
++#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
++#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
++#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
++#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
++#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
++#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
++#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
++#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
++#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
++#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
++#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
++#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
++#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
++#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
++#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
++#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
++#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
++#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
++#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
++#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
++#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
++#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
++#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
++#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
++#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
++#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
++#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
++#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
++#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
++#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
++#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
++#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
++#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
++#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
++#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
++#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
++#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
++#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
++#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
++#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
++#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
++#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
++#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
++#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
++#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
++#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
++#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
++#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
++#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
++#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
++#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
++#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
++#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
++#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
++#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
++#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
++#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
++#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
++#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
++#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
++#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
++#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
++#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
++#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
++#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
++#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
++#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
++#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
++#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
++#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
++#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
++#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
++#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
++#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
++#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
++#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
++#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
++#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
++#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
++#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
++#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
++#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
++#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
++#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
++#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
++#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
++#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
++#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
++#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
++#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
++#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
++#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
++#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
++#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
++#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
++#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
++#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
++#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
++#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
++#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
++#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
++#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
++#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
++#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
++#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
++#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
++#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
++#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
++#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
++#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
++#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
++#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
++#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
++#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
++#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
++#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
++#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
++#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
++#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
++#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
++#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
++#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
++#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
++#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
++#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
++#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
++#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
++#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
++#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
++#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
++#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
++#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
++#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
++#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
++#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
++#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
++#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
++#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
++#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
++#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
++#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
++#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
++#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
++#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
++#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
++#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
++#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
++#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
++#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
++#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
++#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
++#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
++#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
++#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
++#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
++#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
++#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
++#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
++#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
++#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
++#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
++#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
++#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
++#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
++#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
++#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
++#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
++#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
++#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
++#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
++#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
++#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
++#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
++#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
++#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
++#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
++#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
++#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
++#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
++#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
++#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
++#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
++#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
++#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
++#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
++#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
++#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
++#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
++#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
++#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
++#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
++#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
++#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
++#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
++#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
++#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
++#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
++#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
++#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
++#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
++#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
++#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
++#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
++#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
++#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
++#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
++#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
++#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
++#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
++#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
++#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
++#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
++#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
++#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
++#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
++#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
++#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
++#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
++#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
++#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
++#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
++#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
++#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
++#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
++#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
++#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
++#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
++#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
++#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
++#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
++#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
++#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
++#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
++#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
++#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
++#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
++#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
++#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
++#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
++#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
++#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
++#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
++#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
++#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
++#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
++#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
++#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
++#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
++#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
++#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
++#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
++#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
++#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
++#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
++#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
++#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
++#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
++#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
++#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
++#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
++#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
++#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
++#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
++#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
++#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
++#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
++#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
++#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
++#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
++#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
++#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
++#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
++#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
++#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
++#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
++#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
++#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
++#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
++#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
++#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
++#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
++#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
++#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
++#define UVD_MPC_CNTL__DBG_MUX_MASK 0x700
++#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
++#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
++#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
++#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
++#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
++#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
++#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
++#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
++#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
++#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
++#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
++#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
++#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
++#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
++#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
++#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
++#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
++#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
++#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
++#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
++#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
++#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
++#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
++#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
++#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
++#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
++#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
++#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
++#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
++#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
++#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
++#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
++#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
++#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
++#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
++#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
++#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
++#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
++#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
++#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
++#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
++#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
++#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
++#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
++#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
++#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
++#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
++#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
++#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
++#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
++#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
++#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
++#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
++#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
++#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
++#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
++#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
++#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
++#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
++#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
++#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
++#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
++#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
++#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
++#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
++#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
++#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
++#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
++#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
++#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
++#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
++#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
++#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000
++#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11
++#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
++#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
++#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
++#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
++#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
++#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
++#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000
++#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d
++#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
++#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
++#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
++#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
++#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
++#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
++#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
++#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
++#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
++#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
++#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
++#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
++#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
++#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
++#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
++#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
++#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
++#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
++#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
++#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
++#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
++#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
++#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200
++#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9
++#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
++#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
++#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
++#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
++#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
++#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
++#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
++#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
++#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
++#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
++#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
++#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
++#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
++#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
++#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0
++#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6
++#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
++#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
++#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0
++#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6
++#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
++#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
++#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
++#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
++#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
++#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
++#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
++#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
++#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
++#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
++#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
++#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
++#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
++#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
++#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
++#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
++#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
++#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
++#define UVD_STATUS__RBC_BUSY_MASK 0x1
++#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
++#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
++#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
++#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
++#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
++#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
++#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
++#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
++#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
++#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
++#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
++#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
++#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
++#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
++#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
++#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
++#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
++#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
++#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
++#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
++#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
++#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
++#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
++#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
++#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
++#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
++#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
++#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
++#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
++#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
++#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
++#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
++#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
++#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
++#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
++#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
++#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
++#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
++#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
++#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
++#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
++#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
++#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
++#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
++#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
++#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
++#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
++#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
++#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
++#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
++#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
++#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
++#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
++#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
++#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
++#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
++#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
++#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
++#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
++#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
++#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
++#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
++#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
++#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
++#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
++#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
++#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1
++#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++
++#endif /* UVD_4_2_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0025-yocto-amd-drm-amdgpu-add-OSS-3-0-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0025-yocto-amd-drm-amdgpu-add-OSS-3-0-1-register-headers.patch
new file mode 100644
index 00000000..3dc213a5
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0025-yocto-amd-drm-amdgpu-add-OSS-3-0-1-register-headers.patch
@@ -0,0 +1,2403 @@
+From 20ef7fab75f282661ccc1fcc389b601b13ebd5aa Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:34:14 -0400
+Subject: drm/amdgpu: add UVD 5.0 register headers
+
+These are register headers for the UVD (Universal Video Decoder)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
+new file mode 100644
+index 0000000..eb4cf53
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
+@@ -0,0 +1,114 @@
++/*
++ * UVD_5_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_5_0_D_H
++#define UVD_5_0_D_H
++
++#define mmUVD_SEMA_ADDR_LOW                                                     0x3bc0
++#define mmUVD_SEMA_ADDR_HIGH                                                    0x3bc1
++#define mmUVD_SEMA_CMD                                                          0x3bc2
++#define mmUVD_GPCOM_VCPU_CMD                                                    0x3bc3
++#define mmUVD_GPCOM_VCPU_DATA0                                                  0x3bc4
++#define mmUVD_GPCOM_VCPU_DATA1                                                  0x3bc5
++#define mmUVD_ENGINE_CNTL                                                       0x3bc6
++#define mmUVD_UDEC_ADDR_CONFIG                                                  0x3bd3
++#define mmUVD_UDEC_DB_ADDR_CONFIG                                               0x3bd4
++#define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5
++#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                          0x3c69
++#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                         0x3c68
++#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                          0x3c67
++#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                         0x3c66
++#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                      0x3c5f
++#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                     0x3c5e
++#define mmUVD_SEMA_CNTL                                                         0x3d00
++#define mmUVD_LMI_EXT40_ADDR                                                    0x3d26
++#define mmUVD_CTX_INDEX                                                         0x3d28
++#define mmUVD_CTX_DATA                                                          0x3d29
++#define mmUVD_CGC_GATE                                                          0x3d2a
++#define mmUVD_CGC_STATUS                                                        0x3d2b
++#define mmUVD_CGC_CTRL                                                          0x3d2c
++#define mmUVD_CGC_UDEC_STATUS                                                   0x3d2d
++#define mmUVD_LMI_CTRL2                                                         0x3d3d
++#define mmUVD_MASTINT_EN                                                        0x3d40
++#define mmUVD_LMI_ADDR_EXT                                                      0x3d65
++#define mmUVD_LMI_CTRL                                                          0x3d66
++#define mmUVD_LMI_STATUS                                                        0x3d67
++#define mmUVD_LMI_SWAP_CNTL                                                     0x3d6d
++#define mmUVD_MP_SWAP_CNTL                                                      0x3d6f
++#define mmUVD_MPC_CNTL                                                          0x3d77
++#define mmUVD_MPC_SET_MUXA0                                                     0x3d79
++#define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
++#define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
++#define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
++#define mmUVD_MPC_SET_MUX                                                       0x3d7d
++#define mmUVD_MPC_SET_ALU                                                       0x3d7e
++#define mmUVD_VCPU_CACHE_OFFSET0                                                0x3d82
++#define mmUVD_VCPU_CACHE_SIZE0                                                  0x3d83
++#define mmUVD_VCPU_CACHE_OFFSET1                                                0x3d84
++#define mmUVD_VCPU_CACHE_SIZE1                                                  0x3d85
++#define mmUVD_VCPU_CACHE_OFFSET2                                                0x3d86
++#define mmUVD_VCPU_CACHE_SIZE2                                                  0x3d87
++#define mmUVD_VCPU_CNTL                                                         0x3d98
++#define mmUVD_SOFT_RESET                                                        0x3da0
++#define mmUVD_LMI_RBC_IB_VMID                                                   0x3da1
++#define mmUVD_RBC_IB_SIZE                                                       0x3da2
++#define mmUVD_LMI_RBC_RB_VMID                                                   0x3da3
++#define mmUVD_RBC_RB_RPTR                                                       0x3da4
++#define mmUVD_RBC_RB_WPTR                                                       0x3da5
++#define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
++#define mmUVD_RBC_RB_CNTL                                                       0x3da9
++#define mmUVD_RBC_RB_RPTR_ADDR                                                  0x3daa
++#define mmUVD_STATUS                                                            0x3daf
++#define mmUVD_SEMA_TIMEOUT_STATUS                                               0x3db0
++#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                 0x3db1
++#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                      0x3db2
++#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                               0x3db3
++#define mmUVD_CONTEXT_ID                                                        0x3dbd
++#define mmUVD_RBC_IB_SIZE_UPDATE                                                0x3df1
++#define mmUVD_SUVD_CGC_GATE                                                     0x3be4
++#define mmUVD_SUVD_CGC_STATUS                                                   0x3be5
++#define mmUVD_SUVD_CGC_CTRL                                                     0x3be6
++#define ixUVD_LMI_VMID_INTERNAL                                                 0x99
++#define ixUVD_LMI_VMID_INTERNAL2                                                0x9a
++#define ixUVD_LMI_CACHE_CTRL                                                    0x9b
++#define ixUVD_LMI_SWAP_CNTL2                                                    0xaa
++#define ixUVD_LMI_ADDR_EXT2                                                     0xab
++#define ixUVD_CGC_MEM_CTRL                                                      0xc0
++#define ixUVD_CGC_CTRL2                                                         0xc1
++#define ixUVD_LMI_VMID_INTERNAL3                                                0x162
++#define mmUVD_PGFSM_CONFIG                                                      0x38c0
++#define mmUVD_PGFSM_READ_TILE1                                                  0x38c2
++#define mmUVD_PGFSM_READ_TILE2                                                  0x38c3
++#define mmUVD_POWER_STATUS                                                      0x38c4
++#define mmUVD_PGFSM_READ_TILE3                                                  0x38c5
++#define mmUVD_PGFSM_READ_TILE4                                                  0x38c6
++#define mmUVD_PGFSM_READ_TILE5                                                  0x38c8
++#define mmUVD_PGFSM_READ_TILE6                                                  0x38ee
++#define mmUVD_PGFSM_READ_TILE7                                                  0x38ef
++#define mmUVD_MIF_CURR_ADDR_CONFIG                                              0x3992
++#define mmUVD_MIF_REF_ADDR_CONFIG                                               0x3993
++#define mmUVD_MIF_RECON1_ADDR_CONFIG                                            0x39c5
++#define ixUVD_MIF_SCLR_ADDR_CONFIG                                              0x4
++#define mmUVD_JPEG_ADDR_CONFIG                                                  0x3a1f
++
++#endif /* UVD_5_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
+new file mode 100644
+index 0000000..981086f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
+@@ -0,0 +1,1211 @@
++/*
++ * UVD_5_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_5_0_ENUM_H
++#define UVD_5_0_ENUM_H
++
++typedef enum UVDFirmwareCommand {
++	UVDFC_FENCE                                      = 0x0,
++	UVDFC_TRAP                                       = 0x1,
++	UVDFC_DECODED_ADDR                               = 0x2,
++	UVDFC_MBLOCK_ADDR                                = 0x3,
++	UVDFC_ITBUF_ADDR                                 = 0x4,
++	UVDFC_DISPLAY_ADDR                               = 0x5,
++	UVDFC_EOD                                        = 0x6,
++	UVDFC_DISPLAY_PITCH                              = 0x7,
++	UVDFC_DISPLAY_TILING                             = 0x8,
++	UVDFC_BITSTREAM_ADDR                             = 0x9,
++	UVDFC_BITSTREAM_SIZE                             = 0xa,
++} UVDFirmwareCommand;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum DebugBlockId {
++	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
++	DBG_CLIENT_BLKID_dbg                             = 0x1,
++	DBG_CLIENT_BLKID_scf2                            = 0x2,
++	DBG_CLIENT_BLKID_mcd5                            = 0x3,
++	DBG_CLIENT_BLKID_vmc                             = 0x4,
++	DBG_CLIENT_BLKID_sx30                            = 0x5,
++	DBG_CLIENT_BLKID_mcd2                            = 0x6,
++	DBG_CLIENT_BLKID_bci1                            = 0x7,
++	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
++	DBG_CLIENT_BLKID_mcc0                            = 0x9,
++	DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
++	DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
++	DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
++	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
++	DBG_CLIENT_BLKID_bci0                            = 0xe,
++	DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
++	DBG_CLIENT_BLKID_cb100                           = 0x10,
++	DBG_CLIENT_BLKID_cb001                           = 0x11,
++	DBG_CLIENT_BLKID_mcd4                            = 0x12,
++	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
++	DBG_CLIENT_BLKID_cb101                           = 0x14,
++	DBG_CLIENT_BLKID_sx10                            = 0x15,
++	DBG_CLIENT_BLKID_cb301                           = 0x16,
++	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
++	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
++	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
++	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
++	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
++	DBG_CLIENT_BLKID_scf1                            = 0x1c,
++	DBG_CLIENT_BLKID_sx20                            = 0x1d,
++	DBG_CLIENT_BLKID_spim1                           = 0x1e,
++	DBG_CLIENT_BLKID_pa10                            = 0x1f,
++	DBG_CLIENT_BLKID_pa00                            = 0x20,
++	DBG_CLIENT_BLKID_gmcon                           = 0x21,
++	DBG_CLIENT_BLKID_mcb                             = 0x22,
++	DBG_CLIENT_BLKID_vgt0                            = 0x23,
++	DBG_CLIENT_BLKID_pc0                             = 0x24,
++	DBG_CLIENT_BLKID_bci2                            = 0x25,
++	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
++	DBG_CLIENT_BLKID_spim3                           = 0x27,
++	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
++	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
++	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
++	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
++	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
++	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
++	DBG_CLIENT_BLKID_cb000                           = 0x2e,
++	DBG_CLIENT_BLKID_spim0                           = 0x2f,
++	DBG_CLIENT_BLKID_mcc2                            = 0x30,
++	DBG_CLIENT_BLKID_ds0                             = 0x31,
++	DBG_CLIENT_BLKID_srbm                            = 0x32,
++	DBG_CLIENT_BLKID_ih                              = 0x33,
++	DBG_CLIENT_BLKID_sem                             = 0x34,
++	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
++	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
++	DBG_CLIENT_BLKID_hdp                             = 0x37,
++	DBG_CLIENT_BLKID_acp_0                           = 0x38,
++	DBG_CLIENT_BLKID_acp_1                           = 0x39,
++	DBG_CLIENT_BLKID_cb200                           = 0x3a,
++	DBG_CLIENT_BLKID_scf3                            = 0x3b,
++	DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
++	DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
++	DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
++	DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
++	DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
++	DBG_CLIENT_BLKID_bci3                            = 0x41,
++	DBG_CLIENT_BLKID_mcd0                            = 0x42,
++	DBG_CLIENT_BLKID_pa11                            = 0x43,
++	DBG_CLIENT_BLKID_pa01                            = 0x44,
++	DBG_CLIENT_BLKID_cb201                           = 0x45,
++	DBG_CLIENT_BLKID_spim2                           = 0x46,
++	DBG_CLIENT_BLKID_vgt2                            = 0x47,
++	DBG_CLIENT_BLKID_pc2                             = 0x48,
++	DBG_CLIENT_BLKID_smu_0                           = 0x49,
++	DBG_CLIENT_BLKID_smu_1                           = 0x4a,
++	DBG_CLIENT_BLKID_smu_2                           = 0x4b,
++	DBG_CLIENT_BLKID_cb1                             = 0x4c,
++	DBG_CLIENT_BLKID_ia0                             = 0x4d,
++	DBG_CLIENT_BLKID_wd                              = 0x4e,
++	DBG_CLIENT_BLKID_ia1                             = 0x4f,
++	DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
++	DBG_CLIENT_BLKID_scf0                            = 0x51,
++	DBG_CLIENT_BLKID_vgt1                            = 0x52,
++	DBG_CLIENT_BLKID_pc1                             = 0x53,
++	DBG_CLIENT_BLKID_cb0                             = 0x54,
++	DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
++	DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
++	DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
++	DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
++	DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
++	DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
++	DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
++	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
++	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
++	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
++	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
++	DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
++	DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
++	DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
++	DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
++	DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
++	DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
++	DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
++	DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
++	DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
++	DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
++	DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
++	DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
++	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
++	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
++	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
++	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
++	DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
++	DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
++	DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
++	DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
++	DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
++	DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
++	DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
++	DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
++	DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
++	DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
++	DBG_CLIENT_BLKID_vgt3                            = 0x7a,
++	DBG_CLIENT_BLKID_pc3                             = 0x7b,
++	DBG_CLIENT_BLKID_mcd3                            = 0x7c,
++	DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
++	DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
++	DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
++	DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
++	DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
++	DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
++	DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
++	DBG_CLIENT_BLKID_cb300                           = 0x84,
++	DBG_CLIENT_BLKID_mcd1                            = 0x85,
++	DBG_CLIENT_BLKID_sx00                            = 0x86,
++	DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
++	DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
++	DBG_CLIENT_BLKID_mcc3                            = 0x89,
++	DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
++	DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
++	DBG_CLIENT_BLKID_gck                             = 0x8c,
++	DBG_CLIENT_BLKID_mcc1                            = 0x8d,
++	DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
++	DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
++	DBG_CLIENT_BLKID_rlc                             = 0x90,
++	DBG_CLIENT_BLKID_grbm                            = 0x91,
++	DBG_CLIENT_BLKID_sammsp                          = 0x92,
++	DBG_CLIENT_BLKID_dci_pg                          = 0x93,
++	DBG_CLIENT_BLKID_dci_0                           = 0x94,
++	DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
++	DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
++	DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
++	DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
++	DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
++	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
++	DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
++	DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
++	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
++} DebugBlockId;
++typedef enum DebugBlockId_OLD {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_AVP                                 = 0xd,
++	DBG_BLOCK_ID_GMCON                               = 0xe,
++	DBG_BLOCK_ID_SMU                                 = 0xf,
++	DBG_BLOCK_ID_DMA0                                = 0x10,
++	DBG_BLOCK_ID_DMA1                                = 0x11,
++	DBG_BLOCK_ID_SPIM                                = 0x12,
++	DBG_BLOCK_ID_GDS                                 = 0x13,
++	DBG_BLOCK_ID_SPIS                                = 0x14,
++	DBG_BLOCK_ID_UNUSED0                             = 0x15,
++	DBG_BLOCK_ID_PA0                                 = 0x16,
++	DBG_BLOCK_ID_PA1                                 = 0x17,
++	DBG_BLOCK_ID_CP0                                 = 0x18,
++	DBG_BLOCK_ID_CP1                                 = 0x19,
++	DBG_BLOCK_ID_CP2                                 = 0x1a,
++	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
++	DBG_BLOCK_ID_UVDU                                = 0x1c,
++	DBG_BLOCK_ID_UVDM                                = 0x1d,
++	DBG_BLOCK_ID_VCE                                 = 0x1e,
++	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
++	DBG_BLOCK_ID_VGT0                                = 0x20,
++	DBG_BLOCK_ID_VGT1                                = 0x21,
++	DBG_BLOCK_ID_IA                                  = 0x22,
++	DBG_BLOCK_ID_UNUSED3                             = 0x23,
++	DBG_BLOCK_ID_SCT0                                = 0x24,
++	DBG_BLOCK_ID_SCT1                                = 0x25,
++	DBG_BLOCK_ID_SPM0                                = 0x26,
++	DBG_BLOCK_ID_SPM1                                = 0x27,
++	DBG_BLOCK_ID_TCAA                                = 0x28,
++	DBG_BLOCK_ID_TCAB                                = 0x29,
++	DBG_BLOCK_ID_TCCA                                = 0x2a,
++	DBG_BLOCK_ID_TCCB                                = 0x2b,
++	DBG_BLOCK_ID_MCC0                                = 0x2c,
++	DBG_BLOCK_ID_MCC1                                = 0x2d,
++	DBG_BLOCK_ID_MCC2                                = 0x2e,
++	DBG_BLOCK_ID_MCC3                                = 0x2f,
++	DBG_BLOCK_ID_SX0                                 = 0x30,
++	DBG_BLOCK_ID_SX1                                 = 0x31,
++	DBG_BLOCK_ID_SX2                                 = 0x32,
++	DBG_BLOCK_ID_SX3                                 = 0x33,
++	DBG_BLOCK_ID_UNUSED4                             = 0x34,
++	DBG_BLOCK_ID_UNUSED5                             = 0x35,
++	DBG_BLOCK_ID_UNUSED6                             = 0x36,
++	DBG_BLOCK_ID_UNUSED7                             = 0x37,
++	DBG_BLOCK_ID_PC0                                 = 0x38,
++	DBG_BLOCK_ID_PC1                                 = 0x39,
++	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
++	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
++	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
++	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
++	DBG_BLOCK_ID_MCB                                 = 0x3e,
++	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
++	DBG_BLOCK_ID_SCB0                                = 0x40,
++	DBG_BLOCK_ID_SCB1                                = 0x41,
++	DBG_BLOCK_ID_UNUSED13                            = 0x42,
++	DBG_BLOCK_ID_UNUSED14                            = 0x43,
++	DBG_BLOCK_ID_SCF0                                = 0x44,
++	DBG_BLOCK_ID_SCF1                                = 0x45,
++	DBG_BLOCK_ID_UNUSED15                            = 0x46,
++	DBG_BLOCK_ID_UNUSED16                            = 0x47,
++	DBG_BLOCK_ID_BCI0                                = 0x48,
++	DBG_BLOCK_ID_BCI1                                = 0x49,
++	DBG_BLOCK_ID_BCI2                                = 0x4a,
++	DBG_BLOCK_ID_BCI3                                = 0x4b,
++	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
++	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
++	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
++	DBG_BLOCK_ID_CB00                                = 0x50,
++	DBG_BLOCK_ID_CB01                                = 0x51,
++	DBG_BLOCK_ID_CB02                                = 0x52,
++	DBG_BLOCK_ID_CB03                                = 0x53,
++	DBG_BLOCK_ID_CB04                                = 0x54,
++	DBG_BLOCK_ID_UNUSED21                            = 0x55,
++	DBG_BLOCK_ID_UNUSED22                            = 0x56,
++	DBG_BLOCK_ID_UNUSED23                            = 0x57,
++	DBG_BLOCK_ID_CB10                                = 0x58,
++	DBG_BLOCK_ID_CB11                                = 0x59,
++	DBG_BLOCK_ID_CB12                                = 0x5a,
++	DBG_BLOCK_ID_CB13                                = 0x5b,
++	DBG_BLOCK_ID_CB14                                = 0x5c,
++	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
++	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
++	DBG_BLOCK_ID_TCP0                                = 0x60,
++	DBG_BLOCK_ID_TCP1                                = 0x61,
++	DBG_BLOCK_ID_TCP2                                = 0x62,
++	DBG_BLOCK_ID_TCP3                                = 0x63,
++	DBG_BLOCK_ID_TCP4                                = 0x64,
++	DBG_BLOCK_ID_TCP5                                = 0x65,
++	DBG_BLOCK_ID_TCP6                                = 0x66,
++	DBG_BLOCK_ID_TCP7                                = 0x67,
++	DBG_BLOCK_ID_TCP8                                = 0x68,
++	DBG_BLOCK_ID_TCP9                                = 0x69,
++	DBG_BLOCK_ID_TCP10                               = 0x6a,
++	DBG_BLOCK_ID_TCP11                               = 0x6b,
++	DBG_BLOCK_ID_TCP12                               = 0x6c,
++	DBG_BLOCK_ID_TCP13                               = 0x6d,
++	DBG_BLOCK_ID_TCP14                               = 0x6e,
++	DBG_BLOCK_ID_TCP15                               = 0x6f,
++	DBG_BLOCK_ID_TCP16                               = 0x70,
++	DBG_BLOCK_ID_TCP17                               = 0x71,
++	DBG_BLOCK_ID_TCP18                               = 0x72,
++	DBG_BLOCK_ID_TCP19                               = 0x73,
++	DBG_BLOCK_ID_TCP20                               = 0x74,
++	DBG_BLOCK_ID_TCP21                               = 0x75,
++	DBG_BLOCK_ID_TCP22                               = 0x76,
++	DBG_BLOCK_ID_TCP23                               = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
++	DBG_BLOCK_ID_DB00                                = 0x80,
++	DBG_BLOCK_ID_DB01                                = 0x81,
++	DBG_BLOCK_ID_DB02                                = 0x82,
++	DBG_BLOCK_ID_DB03                                = 0x83,
++	DBG_BLOCK_ID_DB04                                = 0x84,
++	DBG_BLOCK_ID_UNUSED27                            = 0x85,
++	DBG_BLOCK_ID_UNUSED28                            = 0x86,
++	DBG_BLOCK_ID_UNUSED29                            = 0x87,
++	DBG_BLOCK_ID_DB10                                = 0x88,
++	DBG_BLOCK_ID_DB11                                = 0x89,
++	DBG_BLOCK_ID_DB12                                = 0x8a,
++	DBG_BLOCK_ID_DB13                                = 0x8b,
++	DBG_BLOCK_ID_DB14                                = 0x8c,
++	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
++	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
++	DBG_BLOCK_ID_TCC0                                = 0x90,
++	DBG_BLOCK_ID_TCC1                                = 0x91,
++	DBG_BLOCK_ID_TCC2                                = 0x92,
++	DBG_BLOCK_ID_TCC3                                = 0x93,
++	DBG_BLOCK_ID_TCC4                                = 0x94,
++	DBG_BLOCK_ID_TCC5                                = 0x95,
++	DBG_BLOCK_ID_TCC6                                = 0x96,
++	DBG_BLOCK_ID_TCC7                                = 0x97,
++	DBG_BLOCK_ID_SPS00                               = 0x98,
++	DBG_BLOCK_ID_SPS01                               = 0x99,
++	DBG_BLOCK_ID_SPS02                               = 0x9a,
++	DBG_BLOCK_ID_SPS10                               = 0x9b,
++	DBG_BLOCK_ID_SPS11                               = 0x9c,
++	DBG_BLOCK_ID_SPS12                               = 0x9d,
++	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
++	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
++	DBG_BLOCK_ID_TA00                                = 0xa0,
++	DBG_BLOCK_ID_TA01                                = 0xa1,
++	DBG_BLOCK_ID_TA02                                = 0xa2,
++	DBG_BLOCK_ID_TA03                                = 0xa3,
++	DBG_BLOCK_ID_TA04                                = 0xa4,
++	DBG_BLOCK_ID_TA05                                = 0xa5,
++	DBG_BLOCK_ID_TA06                                = 0xa6,
++	DBG_BLOCK_ID_TA07                                = 0xa7,
++	DBG_BLOCK_ID_TA08                                = 0xa8,
++	DBG_BLOCK_ID_TA09                                = 0xa9,
++	DBG_BLOCK_ID_TA0A                                = 0xaa,
++	DBG_BLOCK_ID_TA0B                                = 0xab,
++	DBG_BLOCK_ID_UNUSED35                            = 0xac,
++	DBG_BLOCK_ID_UNUSED36                            = 0xad,
++	DBG_BLOCK_ID_UNUSED37                            = 0xae,
++	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
++	DBG_BLOCK_ID_TA10                                = 0xb0,
++	DBG_BLOCK_ID_TA11                                = 0xb1,
++	DBG_BLOCK_ID_TA12                                = 0xb2,
++	DBG_BLOCK_ID_TA13                                = 0xb3,
++	DBG_BLOCK_ID_TA14                                = 0xb4,
++	DBG_BLOCK_ID_TA15                                = 0xb5,
++	DBG_BLOCK_ID_TA16                                = 0xb6,
++	DBG_BLOCK_ID_TA17                                = 0xb7,
++	DBG_BLOCK_ID_TA18                                = 0xb8,
++	DBG_BLOCK_ID_TA19                                = 0xb9,
++	DBG_BLOCK_ID_TA1A                                = 0xba,
++	DBG_BLOCK_ID_TA1B                                = 0xbb,
++	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
++	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
++	DBG_BLOCK_ID_TD00                                = 0xc0,
++	DBG_BLOCK_ID_TD01                                = 0xc1,
++	DBG_BLOCK_ID_TD02                                = 0xc2,
++	DBG_BLOCK_ID_TD03                                = 0xc3,
++	DBG_BLOCK_ID_TD04                                = 0xc4,
++	DBG_BLOCK_ID_TD05                                = 0xc5,
++	DBG_BLOCK_ID_TD06                                = 0xc6,
++	DBG_BLOCK_ID_TD07                                = 0xc7,
++	DBG_BLOCK_ID_TD08                                = 0xc8,
++	DBG_BLOCK_ID_TD09                                = 0xc9,
++	DBG_BLOCK_ID_TD0A                                = 0xca,
++	DBG_BLOCK_ID_TD0B                                = 0xcb,
++	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED45                            = 0xce,
++	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
++	DBG_BLOCK_ID_TD10                                = 0xd0,
++	DBG_BLOCK_ID_TD11                                = 0xd1,
++	DBG_BLOCK_ID_TD12                                = 0xd2,
++	DBG_BLOCK_ID_TD13                                = 0xd3,
++	DBG_BLOCK_ID_TD14                                = 0xd4,
++	DBG_BLOCK_ID_TD15                                = 0xd5,
++	DBG_BLOCK_ID_TD16                                = 0xd6,
++	DBG_BLOCK_ID_TD17                                = 0xd7,
++	DBG_BLOCK_ID_TD18                                = 0xd8,
++	DBG_BLOCK_ID_TD19                                = 0xd9,
++	DBG_BLOCK_ID_TD1A                                = 0xda,
++	DBG_BLOCK_ID_TD1B                                = 0xdb,
++	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED49                            = 0xde,
++	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
++	DBG_BLOCK_ID_MCD0                                = 0xe0,
++	DBG_BLOCK_ID_MCD1                                = 0xe1,
++	DBG_BLOCK_ID_MCD2                                = 0xe2,
++	DBG_BLOCK_ID_MCD3                                = 0xe3,
++	DBG_BLOCK_ID_MCD4                                = 0xe4,
++	DBG_BLOCK_ID_MCD5                                = 0xe5,
++	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
++	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
++} DebugBlockId_OLD;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_CG_BY2                              = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
++	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
++	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
++	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
++	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
++	DBG_BLOCK_ID_IA_BY2                              = 0x11,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
++	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
++	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
++	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
++	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
++	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
++	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
++	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
++	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
++	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
++	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
++	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
++	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
++	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
++	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
++	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
++	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
++	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
++	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
++	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
++	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
++	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
++	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
++	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_CG_BY4                              = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
++	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
++	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
++	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
++	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
++	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
++	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
++	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
++	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
++	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
++	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
++	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
++	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_DB_BY4                              = 0x20,
++	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
++	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
++	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
++	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
++	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
++	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
++	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
++	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
++	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
++	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
++	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
++	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
++	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
++	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
++	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
++	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
++	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
++	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
++	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
++	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
++	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
++	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
++	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
++	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
++	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
++	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
++	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
++	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
++} DebugBlockId_BY16;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* UVD_5_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
+new file mode 100644
+index 0000000..64749b7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
+@@ -0,0 +1,1046 @@
++/*
++ * UVD_5_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_5_0_SH_MASK_H
++#define UVD_5_0_SH_MASK_H
++
++#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
++#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
++#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
++#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
++#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
++#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
++#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
++#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
++#define UVD_SEMA_CMD__MODE_MASK 0x40
++#define UVD_SEMA_CMD__MODE__SHIFT 0x6
++#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
++#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
++#define UVD_SEMA_CMD__VMID_MASK 0xf00
++#define UVD_SEMA_CMD__VMID__SHIFT 0x8
++#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
++#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
++#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
++#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
++#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
++#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
++#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
++#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
++#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
++#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
++#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
++#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
++#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
++#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
++#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
++#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
++#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
++#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
++#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
++#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
++#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
++#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
++#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
++#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
++#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
++#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
++#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
++#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
++#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
++#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
++#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
++#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
++#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
++#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
++#define UVD_CTX_DATA__DATA_MASK 0xffffffff
++#define UVD_CTX_DATA__DATA__SHIFT 0x0
++#define UVD_CGC_GATE__SYS_MASK 0x1
++#define UVD_CGC_GATE__SYS__SHIFT 0x0
++#define UVD_CGC_GATE__UDEC_MASK 0x2
++#define UVD_CGC_GATE__UDEC__SHIFT 0x1
++#define UVD_CGC_GATE__MPEG2_MASK 0x4
++#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
++#define UVD_CGC_GATE__REGS_MASK 0x8
++#define UVD_CGC_GATE__REGS__SHIFT 0x3
++#define UVD_CGC_GATE__RBC_MASK 0x10
++#define UVD_CGC_GATE__RBC__SHIFT 0x4
++#define UVD_CGC_GATE__LMI_MC_MASK 0x20
++#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
++#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
++#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
++#define UVD_CGC_GATE__IDCT_MASK 0x80
++#define UVD_CGC_GATE__IDCT__SHIFT 0x7
++#define UVD_CGC_GATE__MPRD_MASK 0x100
++#define UVD_CGC_GATE__MPRD__SHIFT 0x8
++#define UVD_CGC_GATE__MPC_MASK 0x200
++#define UVD_CGC_GATE__MPC__SHIFT 0x9
++#define UVD_CGC_GATE__LBSI_MASK 0x400
++#define UVD_CGC_GATE__LBSI__SHIFT 0xa
++#define UVD_CGC_GATE__LRBBM_MASK 0x800
++#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
++#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
++#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
++#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
++#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
++#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
++#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
++#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
++#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
++#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
++#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
++#define UVD_CGC_GATE__WCB_MASK 0x20000
++#define UVD_CGC_GATE__WCB__SHIFT 0x11
++#define UVD_CGC_GATE__VCPU_MASK 0x40000
++#define UVD_CGC_GATE__VCPU__SHIFT 0x12
++#define UVD_CGC_GATE__SCPU_MASK 0x80000
++#define UVD_CGC_GATE__SCPU__SHIFT 0x13
++#define UVD_CGC_GATE__JPEG_MASK 0x100000
++#define UVD_CGC_GATE__JPEG__SHIFT 0x14
++#define UVD_CGC_GATE__JPEG2_MASK 0x200000
++#define UVD_CGC_GATE__JPEG2__SHIFT 0x15
++#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
++#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
++#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
++#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
++#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
++#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
++#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
++#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
++#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
++#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
++#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
++#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
++#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
++#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
++#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
++#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
++#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
++#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
++#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
++#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
++#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
++#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
++#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
++#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
++#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
++#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
++#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
++#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
++#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
++#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
++#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
++#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
++#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
++#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
++#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
++#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
++#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
++#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
++#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
++#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
++#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
++#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
++#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
++#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
++#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
++#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
++#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
++#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
++#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
++#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
++#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
++#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
++#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
++#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
++#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
++#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
++#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
++#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
++#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000
++#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
++#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000
++#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
++#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
++#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
++#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
++#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
++#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
++#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
++#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
++#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
++#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
++#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
++#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
++#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
++#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
++#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
++#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
++#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
++#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
++#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
++#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
++#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
++#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
++#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
++#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
++#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
++#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
++#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
++#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
++#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
++#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
++#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
++#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
++#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
++#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
++#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
++#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
++#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
++#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
++#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
++#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
++#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
++#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
++#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
++#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
++#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
++#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
++#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
++#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
++#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
++#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000
++#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
++#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
++#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
++#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
++#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
++#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
++#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
++#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
++#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
++#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
++#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
++#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
++#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
++#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
++#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
++#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
++#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
++#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
++#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
++#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
++#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
++#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
++#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
++#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
++#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
++#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
++#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
++#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
++#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
++#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
++#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
++#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000
++#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf
++#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000
++#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10
++#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000
++#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11
++#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000
++#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12
++#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
++#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
++#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
++#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
++#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
++#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
++#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
++#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
++#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
++#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
++#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
++#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
++#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
++#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
++#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
++#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
++#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
++#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
++#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
++#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
++#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
++#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
++#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
++#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
++#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
++#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
++#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
++#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
++#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
++#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
++#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
++#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
++#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
++#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
++#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
++#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
++#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
++#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
++#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
++#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
++#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
++#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
++#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
++#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
++#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
++#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
++#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
++#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
++#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
++#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
++#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
++#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
++#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
++#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
++#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
++#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
++#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
++#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
++#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
++#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
++#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
++#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
++#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
++#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
++#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
++#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
++#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
++#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
++#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
++#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
++#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
++#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
++#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
++#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
++#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
++#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
++#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
++#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
++#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
++#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
++#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
++#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
++#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
++#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
++#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
++#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
++#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
++#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
++#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
++#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
++#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
++#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
++#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
++#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
++#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
++#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
++#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
++#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
++#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
++#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
++#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
++#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
++#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
++#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
++#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
++#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
++#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
++#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
++#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
++#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
++#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
++#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
++#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
++#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
++#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
++#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
++#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
++#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
++#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
++#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
++#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
++#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
++#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
++#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
++#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
++#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
++#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
++#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
++#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
++#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
++#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
++#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
++#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
++#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
++#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
++#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
++#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
++#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
++#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
++#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
++#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
++#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
++#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
++#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
++#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
++#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
++#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
++#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
++#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
++#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
++#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
++#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
++#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
++#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
++#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
++#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
++#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
++#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
++#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
++#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
++#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
++#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
++#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
++#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
++#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
++#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
++#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
++#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
++#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
++#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
++#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
++#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
++#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
++#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
++#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
++#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
++#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
++#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
++#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
++#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
++#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
++#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
++#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
++#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
++#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
++#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
++#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
++#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
++#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
++#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
++#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
++#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
++#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
++#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
++#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
++#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
++#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
++#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
++#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
++#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
++#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
++#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
++#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
++#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
++#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
++#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
++#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
++#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
++#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
++#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
++#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
++#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
++#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
++#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
++#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
++#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
++#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
++#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
++#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
++#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
++#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
++#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
++#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
++#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
++#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
++#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
++#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
++#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
++#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
++#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
++#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
++#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
++#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000
++#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
++#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
++#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
++#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000
++#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
++#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
++#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
++#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
++#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
++#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
++#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
++#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
++#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
++#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
++#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
++#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
++#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
++#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
++#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
++#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
++#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
++#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
++#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
++#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
++#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
++#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
++#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
++#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
++#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
++#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
++#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
++#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
++#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9
++#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
++#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
++#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
++#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
++#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
++#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
++#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
++#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
++#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
++#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
++#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
++#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
++#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
++#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
++#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000
++#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
++#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000
++#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
++#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000
++#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
++#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000
++#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
++#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000
++#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
++#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000
++#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
++#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000
++#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
++#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000
++#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
++#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000
++#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
++#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000
++#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
++#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000
++#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
++#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000
++#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
++#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000
++#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
++#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000
++#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
++#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000
++#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
++#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf
++#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
++#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
++#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
++#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf
++#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
++#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
++#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
++#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
++#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
++#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
++#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
++#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
++#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
++#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
++#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
++#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
++#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
++#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
++#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
++#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
++#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
++#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
++#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
++#define UVD_STATUS__RBC_BUSY_MASK 0x1
++#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
++#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
++#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
++#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
++#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1
++#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
++#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
++#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
++#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4
++#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
++#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8
++#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
++#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10
++#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
++#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20
++#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
++#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40
++#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
++#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80
++#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
++#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
++#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
++#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
++#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
++#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
++#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
++#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800
++#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
++#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000
++#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
++#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000
++#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
++#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000
++#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
++#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
++#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
++#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
++#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
++#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
++#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
++#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8
++#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
++#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
++#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
++#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20
++#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
++#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40
++#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
++#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80
++#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
++#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
++#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
++#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
++#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
++#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400
++#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
++#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
++#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
++#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000
++#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
++#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
++#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
++#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000
++#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
++#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000
++#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
++#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
++#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
++#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
++#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
++#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4
++#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
++#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8
++#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
++#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10
++#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
++#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20
++#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
++#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40
++#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00
++#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8
++#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000
++#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc
++#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000
++#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10
++#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000
++#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14
++#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000
++#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18
++#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000
++#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c
++#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf
++#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0
++#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0
++#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00
++#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8
++#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000
++#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc
++#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000
++#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18
++#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000
++#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c
++#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
++#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
++#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
++#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
++#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
++#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
++#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
++#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
++#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
++#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
++#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
++#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
++#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
++#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
++#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
++#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
++#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
++#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
++#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
++#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
++#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
++#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
++#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
++#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
++#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
++#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
++#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
++#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
++#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
++#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
++#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
++#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
++#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
++#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
++#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
++#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
++#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
++#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
++#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
++#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
++#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
++#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
++#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
++#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
++#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
++#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
++#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
++#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
++#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
++#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
++#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
++#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000
++#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
++#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000
++#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf
++#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
++#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
++#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
++#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
++#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
++#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
++#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
++#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
++#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
++#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc
++#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000
++#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
++#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
++#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3
++#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
++#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4
++#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
++#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8
++#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
++#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10
++#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
++#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20
++#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
++#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0
++#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
++#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100
++#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
++#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200
++#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
++#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400
++#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
++#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++
++#endif /* UVD_5_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0026-yocto-amd-drm-amdgpu-add-OSS-3-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0026-yocto-amd-drm-amdgpu-add-OSS-3-0-register-headers.patch
new file mode 100644
index 00000000..27a2044b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0026-yocto-amd-drm-amdgpu-add-OSS-3-0-register-headers.patch
@@ -0,0 +1,2262 @@
+From c51d6c9a5cfeeb24267b9dffab9f8d45062c00c0 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:34:40 -0400
+Subject: drm/amdgpu: add UVD 6.0 register headers
+
+These are register headers for the UVD (Universal Video Decoder)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
+new file mode 100644
+index 0000000..b2d4aaf
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
+@@ -0,0 +1,115 @@
++/*
++ * UVD_6_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_6_0_D_H
++#define UVD_6_0_D_H
++
++#define mmUVD_SEMA_ADDR_LOW                                                     0x3bc0
++#define mmUVD_SEMA_ADDR_HIGH                                                    0x3bc1
++#define mmUVD_SEMA_CMD                                                          0x3bc2
++#define mmUVD_GPCOM_VCPU_CMD                                                    0x3bc3
++#define mmUVD_GPCOM_VCPU_DATA0                                                  0x3bc4
++#define mmUVD_GPCOM_VCPU_DATA1                                                  0x3bc5
++#define mmUVD_ENGINE_CNTL                                                       0x3bc6
++#define mmUVD_UDEC_ADDR_CONFIG                                                  0x3bd3
++#define mmUVD_UDEC_DB_ADDR_CONFIG                                               0x3bd4
++#define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5
++#define mmUVD_POWER_STATUS_U                                                    0x3bfd
++#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                          0x3c69
++#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                         0x3c68
++#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                          0x3c67
++#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                         0x3c66
++#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                      0x3c5f
++#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                     0x3c5e
++#define mmUVD_SEMA_CNTL                                                         0x3d00
++#define mmUVD_LMI_EXT40_ADDR                                                    0x3d26
++#define mmUVD_CTX_INDEX                                                         0x3d28
++#define mmUVD_CTX_DATA                                                          0x3d29
++#define mmUVD_CGC_GATE                                                          0x3d2a
++#define mmUVD_CGC_STATUS                                                        0x3d2b
++#define mmUVD_CGC_CTRL                                                          0x3d2c
++#define mmUVD_CGC_UDEC_STATUS                                                   0x3d2d
++#define mmUVD_LMI_CTRL2                                                         0x3d3d
++#define mmUVD_MASTINT_EN                                                        0x3d40
++#define mmUVD_LMI_ADDR_EXT                                                      0x3d65
++#define mmUVD_LMI_CTRL                                                          0x3d66
++#define mmUVD_LMI_STATUS                                                        0x3d67
++#define mmUVD_LMI_SWAP_CNTL                                                     0x3d6d
++#define mmUVD_MP_SWAP_CNTL                                                      0x3d6f
++#define mmUVD_MPC_CNTL                                                          0x3d77
++#define mmUVD_MPC_SET_MUXA0                                                     0x3d79
++#define mmUVD_MPC_SET_MUXA1                                                     0x3d7a
++#define mmUVD_MPC_SET_MUXB0                                                     0x3d7b
++#define mmUVD_MPC_SET_MUXB1                                                     0x3d7c
++#define mmUVD_MPC_SET_MUX                                                       0x3d7d
++#define mmUVD_MPC_SET_ALU                                                       0x3d7e
++#define mmUVD_VCPU_CACHE_OFFSET0                                                0x3d82
++#define mmUVD_VCPU_CACHE_SIZE0                                                  0x3d83
++#define mmUVD_VCPU_CACHE_OFFSET1                                                0x3d84
++#define mmUVD_VCPU_CACHE_SIZE1                                                  0x3d85
++#define mmUVD_VCPU_CACHE_OFFSET2                                                0x3d86
++#define mmUVD_VCPU_CACHE_SIZE2                                                  0x3d87
++#define mmUVD_VCPU_CNTL                                                         0x3d98
++#define mmUVD_SOFT_RESET                                                        0x3da0
++#define mmUVD_LMI_RBC_IB_VMID                                                   0x3da1
++#define mmUVD_RBC_IB_SIZE                                                       0x3da2
++#define mmUVD_LMI_RBC_RB_VMID                                                   0x3da3
++#define mmUVD_RBC_RB_RPTR                                                       0x3da4
++#define mmUVD_RBC_RB_WPTR                                                       0x3da5
++#define mmUVD_RBC_RB_WPTR_CNTL                                                  0x3da6
++#define mmUVD_RBC_RB_CNTL                                                       0x3da9
++#define mmUVD_RBC_RB_RPTR_ADDR                                                  0x3daa
++#define mmUVD_STATUS                                                            0x3daf
++#define mmUVD_SEMA_TIMEOUT_STATUS                                               0x3db0
++#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                 0x3db1
++#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                      0x3db2
++#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                               0x3db3
++#define mmUVD_CONTEXT_ID                                                        0x3dbd
++#define mmUVD_RBC_IB_SIZE_UPDATE                                                0x3df1
++#define mmUVD_SUVD_CGC_GATE                                                     0x3be4
++#define mmUVD_SUVD_CGC_STATUS                                                   0x3be5
++#define mmUVD_SUVD_CGC_CTRL                                                     0x3be6
++#define ixUVD_LMI_VMID_INTERNAL                                                 0x99
++#define ixUVD_LMI_VMID_INTERNAL2                                                0x9a
++#define ixUVD_LMI_CACHE_CTRL                                                    0x9b
++#define ixUVD_LMI_SWAP_CNTL2                                                    0xaa
++#define ixUVD_LMI_ADDR_EXT2                                                     0xab
++#define ixUVD_CGC_MEM_CTRL                                                      0xc0
++#define ixUVD_CGC_CTRL2                                                         0xc1
++#define ixUVD_LMI_VMID_INTERNAL3                                                0x162
++#define mmUVD_PGFSM_CONFIG                                                      0x38c0
++#define mmUVD_PGFSM_READ_TILE1                                                  0x38c2
++#define mmUVD_PGFSM_READ_TILE2                                                  0x38c3
++#define mmUVD_POWER_STATUS                                                      0x38c4
++#define mmUVD_PGFSM_READ_TILE3                                                  0x38c5
++#define mmUVD_PGFSM_READ_TILE4                                                  0x38c6
++#define mmUVD_PGFSM_READ_TILE5                                                  0x38c8
++#define mmUVD_PGFSM_READ_TILE6                                                  0x38ee
++#define mmUVD_PGFSM_READ_TILE7                                                  0x38ef
++#define mmUVD_MIF_CURR_ADDR_CONFIG                                              0x3992
++#define mmUVD_MIF_REF_ADDR_CONFIG                                               0x3993
++#define mmUVD_MIF_RECON1_ADDR_CONFIG                                            0x39c5
++#define ixUVD_MIF_SCLR_ADDR_CONFIG                                              0x4
++#define mmUVD_JPEG_ADDR_CONFIG                                                  0x3a1f
++
++#endif /* UVD_6_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
+new file mode 100644
+index 0000000..ecf47ba
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
+@@ -0,0 +1,1081 @@
++/*
++ * UVD_6_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_6_0_ENUM_H
++#define UVD_6_0_ENUM_H
++
++typedef enum UVDFirmwareCommand {
++	UVDFC_FENCE                                      = 0x0,
++	UVDFC_TRAP                                       = 0x1,
++	UVDFC_DECODED_ADDR                               = 0x2,
++	UVDFC_MBLOCK_ADDR                                = 0x3,
++	UVDFC_ITBUF_ADDR                                 = 0x4,
++	UVDFC_DISPLAY_ADDR                               = 0x5,
++	UVDFC_EOD                                        = 0x6,
++	UVDFC_DISPLAY_PITCH                              = 0x7,
++	UVDFC_DISPLAY_TILING                             = 0x8,
++	UVDFC_BITSTREAM_ADDR                             = 0x9,
++	UVDFC_BITSTREAM_SIZE                             = 0xa,
++} UVDFirmwareCommand;
++typedef enum DebugBlockId {
++	DBG_BLOCK_ID_RESERVED                            = 0x0,
++	DBG_BLOCK_ID_DBG                                 = 0x1,
++	DBG_BLOCK_ID_VMC                                 = 0x2,
++	DBG_BLOCK_ID_PDMA                                = 0x3,
++	DBG_BLOCK_ID_CG                                  = 0x4,
++	DBG_BLOCK_ID_SRBM                                = 0x5,
++	DBG_BLOCK_ID_GRBM                                = 0x6,
++	DBG_BLOCK_ID_RLC                                 = 0x7,
++	DBG_BLOCK_ID_CSC                                 = 0x8,
++	DBG_BLOCK_ID_SEM                                 = 0x9,
++	DBG_BLOCK_ID_IH                                  = 0xa,
++	DBG_BLOCK_ID_SC                                  = 0xb,
++	DBG_BLOCK_ID_SQ                                  = 0xc,
++	DBG_BLOCK_ID_UVDU                                = 0xd,
++	DBG_BLOCK_ID_SQA                                 = 0xe,
++	DBG_BLOCK_ID_SDMA0                               = 0xf,
++	DBG_BLOCK_ID_SDMA1                               = 0x10,
++	DBG_BLOCK_ID_SPIM                                = 0x11,
++	DBG_BLOCK_ID_GDS                                 = 0x12,
++	DBG_BLOCK_ID_VC0                                 = 0x13,
++	DBG_BLOCK_ID_VC1                                 = 0x14,
++	DBG_BLOCK_ID_PA0                                 = 0x15,
++	DBG_BLOCK_ID_PA1                                 = 0x16,
++	DBG_BLOCK_ID_CP0                                 = 0x17,
++	DBG_BLOCK_ID_CP1                                 = 0x18,
++	DBG_BLOCK_ID_CP2                                 = 0x19,
++	DBG_BLOCK_ID_XBR                                 = 0x1a,
++	DBG_BLOCK_ID_UVDM                                = 0x1b,
++	DBG_BLOCK_ID_VGT0                                = 0x1c,
++	DBG_BLOCK_ID_VGT1                                = 0x1d,
++	DBG_BLOCK_ID_IA                                  = 0x1e,
++	DBG_BLOCK_ID_SXM0                                = 0x1f,
++	DBG_BLOCK_ID_SXM1                                = 0x20,
++	DBG_BLOCK_ID_SCT0                                = 0x21,
++	DBG_BLOCK_ID_SCT1                                = 0x22,
++	DBG_BLOCK_ID_SPM0                                = 0x23,
++	DBG_BLOCK_ID_SPM1                                = 0x24,
++	DBG_BLOCK_ID_UNUSED0                             = 0x25,
++	DBG_BLOCK_ID_UNUSED1                             = 0x26,
++	DBG_BLOCK_ID_TCAA                                = 0x27,
++	DBG_BLOCK_ID_TCAB                                = 0x28,
++	DBG_BLOCK_ID_TCCA                                = 0x29,
++	DBG_BLOCK_ID_TCCB                                = 0x2a,
++	DBG_BLOCK_ID_MCC0                                = 0x2b,
++	DBG_BLOCK_ID_MCC1                                = 0x2c,
++	DBG_BLOCK_ID_MCC2                                = 0x2d,
++	DBG_BLOCK_ID_MCC3                                = 0x2e,
++	DBG_BLOCK_ID_SXS0                                = 0x2f,
++	DBG_BLOCK_ID_SXS1                                = 0x30,
++	DBG_BLOCK_ID_SXS2                                = 0x31,
++	DBG_BLOCK_ID_SXS3                                = 0x32,
++	DBG_BLOCK_ID_SXS4                                = 0x33,
++	DBG_BLOCK_ID_SXS5                                = 0x34,
++	DBG_BLOCK_ID_SXS6                                = 0x35,
++	DBG_BLOCK_ID_SXS7                                = 0x36,
++	DBG_BLOCK_ID_SXS8                                = 0x37,
++	DBG_BLOCK_ID_SXS9                                = 0x38,
++	DBG_BLOCK_ID_BCI0                                = 0x39,
++	DBG_BLOCK_ID_BCI1                                = 0x3a,
++	DBG_BLOCK_ID_BCI2                                = 0x3b,
++	DBG_BLOCK_ID_BCI3                                = 0x3c,
++	DBG_BLOCK_ID_MCB                                 = 0x3d,
++	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
++	DBG_BLOCK_ID_SQA00                               = 0x3f,
++	DBG_BLOCK_ID_SQA01                               = 0x40,
++	DBG_BLOCK_ID_SQA02                               = 0x41,
++	DBG_BLOCK_ID_SQA10                               = 0x42,
++	DBG_BLOCK_ID_SQA11                               = 0x43,
++	DBG_BLOCK_ID_SQA12                               = 0x44,
++	DBG_BLOCK_ID_UNUSED7                             = 0x45,
++	DBG_BLOCK_ID_UNUSED8                             = 0x46,
++	DBG_BLOCK_ID_SQB00                               = 0x47,
++	DBG_BLOCK_ID_SQB01                               = 0x48,
++	DBG_BLOCK_ID_SQB10                               = 0x49,
++	DBG_BLOCK_ID_SQB11                               = 0x4a,
++	DBG_BLOCK_ID_SQ00                                = 0x4b,
++	DBG_BLOCK_ID_SQ01                                = 0x4c,
++	DBG_BLOCK_ID_SQ10                                = 0x4d,
++	DBG_BLOCK_ID_SQ11                                = 0x4e,
++	DBG_BLOCK_ID_CB00                                = 0x4f,
++	DBG_BLOCK_ID_CB01                                = 0x50,
++	DBG_BLOCK_ID_CB02                                = 0x51,
++	DBG_BLOCK_ID_CB03                                = 0x52,
++	DBG_BLOCK_ID_CB04                                = 0x53,
++	DBG_BLOCK_ID_UNUSED9                             = 0x54,
++	DBG_BLOCK_ID_UNUSED10                            = 0x55,
++	DBG_BLOCK_ID_UNUSED11                            = 0x56,
++	DBG_BLOCK_ID_CB10                                = 0x57,
++	DBG_BLOCK_ID_CB11                                = 0x58,
++	DBG_BLOCK_ID_CB12                                = 0x59,
++	DBG_BLOCK_ID_CB13                                = 0x5a,
++	DBG_BLOCK_ID_CB14                                = 0x5b,
++	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
++	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
++	DBG_BLOCK_ID_TCP0                                = 0x5f,
++	DBG_BLOCK_ID_TCP1                                = 0x60,
++	DBG_BLOCK_ID_TCP2                                = 0x61,
++	DBG_BLOCK_ID_TCP3                                = 0x62,
++	DBG_BLOCK_ID_TCP4                                = 0x63,
++	DBG_BLOCK_ID_TCP5                                = 0x64,
++	DBG_BLOCK_ID_TCP6                                = 0x65,
++	DBG_BLOCK_ID_TCP7                                = 0x66,
++	DBG_BLOCK_ID_TCP8                                = 0x67,
++	DBG_BLOCK_ID_TCP9                                = 0x68,
++	DBG_BLOCK_ID_TCP10                               = 0x69,
++	DBG_BLOCK_ID_TCP11                               = 0x6a,
++	DBG_BLOCK_ID_TCP12                               = 0x6b,
++	DBG_BLOCK_ID_TCP13                               = 0x6c,
++	DBG_BLOCK_ID_TCP14                               = 0x6d,
++	DBG_BLOCK_ID_TCP15                               = 0x6e,
++	DBG_BLOCK_ID_TCP16                               = 0x6f,
++	DBG_BLOCK_ID_TCP17                               = 0x70,
++	DBG_BLOCK_ID_TCP18                               = 0x71,
++	DBG_BLOCK_ID_TCP19                               = 0x72,
++	DBG_BLOCK_ID_TCP20                               = 0x73,
++	DBG_BLOCK_ID_TCP21                               = 0x74,
++	DBG_BLOCK_ID_TCP22                               = 0x75,
++	DBG_BLOCK_ID_TCP23                               = 0x76,
++	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
++	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
++	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
++	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
++	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
++	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
++	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
++	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
++	DBG_BLOCK_ID_DB00                                = 0x7f,
++	DBG_BLOCK_ID_DB01                                = 0x80,
++	DBG_BLOCK_ID_DB02                                = 0x81,
++	DBG_BLOCK_ID_DB03                                = 0x82,
++	DBG_BLOCK_ID_DB04                                = 0x83,
++	DBG_BLOCK_ID_UNUSED15                            = 0x84,
++	DBG_BLOCK_ID_UNUSED16                            = 0x85,
++	DBG_BLOCK_ID_UNUSED17                            = 0x86,
++	DBG_BLOCK_ID_DB10                                = 0x87,
++	DBG_BLOCK_ID_DB11                                = 0x88,
++	DBG_BLOCK_ID_DB12                                = 0x89,
++	DBG_BLOCK_ID_DB13                                = 0x8a,
++	DBG_BLOCK_ID_DB14                                = 0x8b,
++	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
++	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
++	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
++	DBG_BLOCK_ID_TCC0                                = 0x8f,
++	DBG_BLOCK_ID_TCC1                                = 0x90,
++	DBG_BLOCK_ID_TCC2                                = 0x91,
++	DBG_BLOCK_ID_TCC3                                = 0x92,
++	DBG_BLOCK_ID_TCC4                                = 0x93,
++	DBG_BLOCK_ID_TCC5                                = 0x94,
++	DBG_BLOCK_ID_TCC6                                = 0x95,
++	DBG_BLOCK_ID_TCC7                                = 0x96,
++	DBG_BLOCK_ID_SPS00                               = 0x97,
++	DBG_BLOCK_ID_SPS01                               = 0x98,
++	DBG_BLOCK_ID_SPS02                               = 0x99,
++	DBG_BLOCK_ID_SPS10                               = 0x9a,
++	DBG_BLOCK_ID_SPS11                               = 0x9b,
++	DBG_BLOCK_ID_SPS12                               = 0x9c,
++	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
++	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
++	DBG_BLOCK_ID_TA00                                = 0x9f,
++	DBG_BLOCK_ID_TA01                                = 0xa0,
++	DBG_BLOCK_ID_TA02                                = 0xa1,
++	DBG_BLOCK_ID_TA03                                = 0xa2,
++	DBG_BLOCK_ID_TA04                                = 0xa3,
++	DBG_BLOCK_ID_TA05                                = 0xa4,
++	DBG_BLOCK_ID_TA06                                = 0xa5,
++	DBG_BLOCK_ID_TA07                                = 0xa6,
++	DBG_BLOCK_ID_TA08                                = 0xa7,
++	DBG_BLOCK_ID_TA09                                = 0xa8,
++	DBG_BLOCK_ID_TA0A                                = 0xa9,
++	DBG_BLOCK_ID_TA0B                                = 0xaa,
++	DBG_BLOCK_ID_UNUSED23                            = 0xab,
++	DBG_BLOCK_ID_UNUSED24                            = 0xac,
++	DBG_BLOCK_ID_UNUSED25                            = 0xad,
++	DBG_BLOCK_ID_UNUSED26                            = 0xae,
++	DBG_BLOCK_ID_TA10                                = 0xaf,
++	DBG_BLOCK_ID_TA11                                = 0xb0,
++	DBG_BLOCK_ID_TA12                                = 0xb1,
++	DBG_BLOCK_ID_TA13                                = 0xb2,
++	DBG_BLOCK_ID_TA14                                = 0xb3,
++	DBG_BLOCK_ID_TA15                                = 0xb4,
++	DBG_BLOCK_ID_TA16                                = 0xb5,
++	DBG_BLOCK_ID_TA17                                = 0xb6,
++	DBG_BLOCK_ID_TA18                                = 0xb7,
++	DBG_BLOCK_ID_TA19                                = 0xb8,
++	DBG_BLOCK_ID_TA1A                                = 0xb9,
++	DBG_BLOCK_ID_TA1B                                = 0xba,
++	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
++	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
++	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
++	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
++	DBG_BLOCK_ID_TD00                                = 0xbf,
++	DBG_BLOCK_ID_TD01                                = 0xc0,
++	DBG_BLOCK_ID_TD02                                = 0xc1,
++	DBG_BLOCK_ID_TD03                                = 0xc2,
++	DBG_BLOCK_ID_TD04                                = 0xc3,
++	DBG_BLOCK_ID_TD05                                = 0xc4,
++	DBG_BLOCK_ID_TD06                                = 0xc5,
++	DBG_BLOCK_ID_TD07                                = 0xc6,
++	DBG_BLOCK_ID_TD08                                = 0xc7,
++	DBG_BLOCK_ID_TD09                                = 0xc8,
++	DBG_BLOCK_ID_TD0A                                = 0xc9,
++	DBG_BLOCK_ID_TD0B                                = 0xca,
++	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
++	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
++	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
++	DBG_BLOCK_ID_UNUSED34                            = 0xce,
++	DBG_BLOCK_ID_TD10                                = 0xcf,
++	DBG_BLOCK_ID_TD11                                = 0xd0,
++	DBG_BLOCK_ID_TD12                                = 0xd1,
++	DBG_BLOCK_ID_TD13                                = 0xd2,
++	DBG_BLOCK_ID_TD14                                = 0xd3,
++	DBG_BLOCK_ID_TD15                                = 0xd4,
++	DBG_BLOCK_ID_TD16                                = 0xd5,
++	DBG_BLOCK_ID_TD17                                = 0xd6,
++	DBG_BLOCK_ID_TD18                                = 0xd7,
++	DBG_BLOCK_ID_TD19                                = 0xd8,
++	DBG_BLOCK_ID_TD1A                                = 0xd9,
++	DBG_BLOCK_ID_TD1B                                = 0xda,
++	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
++	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
++	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
++	DBG_BLOCK_ID_UNUSED38                            = 0xde,
++	DBG_BLOCK_ID_LDS00                               = 0xdf,
++	DBG_BLOCK_ID_LDS01                               = 0xe0,
++	DBG_BLOCK_ID_LDS02                               = 0xe1,
++	DBG_BLOCK_ID_LDS03                               = 0xe2,
++	DBG_BLOCK_ID_LDS04                               = 0xe3,
++	DBG_BLOCK_ID_LDS05                               = 0xe4,
++	DBG_BLOCK_ID_LDS06                               = 0xe5,
++	DBG_BLOCK_ID_LDS07                               = 0xe6,
++	DBG_BLOCK_ID_LDS08                               = 0xe7,
++	DBG_BLOCK_ID_LDS09                               = 0xe8,
++	DBG_BLOCK_ID_LDS0A                               = 0xe9,
++	DBG_BLOCK_ID_LDS0B                               = 0xea,
++	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
++	DBG_BLOCK_ID_UNUSED40                            = 0xec,
++	DBG_BLOCK_ID_UNUSED41                            = 0xed,
++	DBG_BLOCK_ID_UNUSED42                            = 0xee,
++	DBG_BLOCK_ID_LDS10                               = 0xef,
++	DBG_BLOCK_ID_LDS11                               = 0xf0,
++	DBG_BLOCK_ID_LDS12                               = 0xf1,
++	DBG_BLOCK_ID_LDS13                               = 0xf2,
++	DBG_BLOCK_ID_LDS14                               = 0xf3,
++	DBG_BLOCK_ID_LDS15                               = 0xf4,
++	DBG_BLOCK_ID_LDS16                               = 0xf5,
++	DBG_BLOCK_ID_LDS17                               = 0xf6,
++	DBG_BLOCK_ID_LDS18                               = 0xf7,
++	DBG_BLOCK_ID_LDS19                               = 0xf8,
++	DBG_BLOCK_ID_LDS1A                               = 0xf9,
++	DBG_BLOCK_ID_LDS1B                               = 0xfa,
++	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
++	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
++	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
++	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
++} DebugBlockId;
++typedef enum DebugBlockId_BY2 {
++	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
++	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
++	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
++	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
++	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
++	DBG_BLOCK_ID_IH_BY2                              = 0x5,
++	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
++	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
++	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
++	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
++	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
++	DBG_BLOCK_ID_PA_BY2                              = 0xb,
++	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
++	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
++	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
++	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
++	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
++	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
++	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
++	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
++	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
++	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
++	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
++	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
++	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
++	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
++	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
++	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
++	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
++	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
++	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
++	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
++	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
++	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
++	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
++	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
++	DBG_BLOCK_ID_CB_BY2                              = 0x24,
++	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
++	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
++	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
++	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
++	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
++	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
++	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
++	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
++	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
++	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
++	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
++	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
++	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
++	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
++	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
++	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
++	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
++	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
++	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
++	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
++	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
++	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
++	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
++	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
++	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
++	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
++	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
++	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
++	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
++	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
++	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
++	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
++	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
++	DBG_BLOCK_ID_TA_BY2                              = 0x48,
++	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
++	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
++	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
++	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
++	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
++	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
++	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
++	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
++	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
++	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
++	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
++	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
++	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
++	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
++	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
++	DBG_BLOCK_ID_TD_BY2                              = 0x58,
++	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
++	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
++	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
++	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
++	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
++	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
++	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
++	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
++	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
++	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
++	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
++	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
++	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
++	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
++	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
++	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
++	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
++	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
++	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
++	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
++	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
++	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
++	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
++	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
++	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
++	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
++	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
++	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
++	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
++	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
++	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
++} DebugBlockId_BY2;
++typedef enum DebugBlockId_BY4 {
++	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
++	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
++	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
++	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
++	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
++	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
++	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
++	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
++	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
++	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
++	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
++	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
++	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
++	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
++	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
++	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
++	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
++	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
++	DBG_BLOCK_ID_CB_BY4                              = 0x12,
++	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
++	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
++	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
++	DBG_BLOCK_ID_DB_BY4                              = 0x16,
++	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
++	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
++	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
++	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
++	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
++	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
++	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
++	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
++	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
++	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
++	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
++	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
++	DBG_BLOCK_ID_TA_BY4                              = 0x24,
++	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
++	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
++	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
++	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
++	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
++	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
++	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
++	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
++	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
++	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
++	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
++	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
++	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
++	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
++	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
++	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
++	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
++	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
++	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
++	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
++	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
++	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
++	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
++} DebugBlockId_BY4;
++typedef enum DebugBlockId_BY8 {
++	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
++	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
++	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
++	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
++	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
++	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
++	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
++	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
++	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
++	DBG_BLOCK_ID_CB_BY8                              = 0x9,
++	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
++	DBG_BLOCK_ID_DB_BY8                              = 0xb,
++	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
++	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
++	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
++	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
++	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
++	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
++	DBG_BLOCK_ID_TA_BY8                              = 0x12,
++	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
++	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
++	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
++	DBG_BLOCK_ID_TD_BY8                              = 0x16,
++	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
++	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
++	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
++	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
++	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
++	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
++	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
++} DebugBlockId_BY8;
++typedef enum DebugBlockId_BY16 {
++	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
++	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
++	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
++	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
++	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
++	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
++	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
++	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
++	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
++	DBG_BLOCK_ID_TA_BY16                             = 0x9,
++	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
++	DBG_BLOCK_ID_TD_BY16                             = 0xb,
++	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
++	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
++	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
++} DebugBlockId_BY16;
++typedef enum SurfaceEndian {
++	ENDIAN_NONE                                      = 0x0,
++	ENDIAN_8IN16                                     = 0x1,
++	ENDIAN_8IN32                                     = 0x2,
++	ENDIAN_8IN64                                     = 0x3,
++} SurfaceEndian;
++typedef enum ArrayMode {
++	ARRAY_LINEAR_GENERAL                             = 0x0,
++	ARRAY_LINEAR_ALIGNED                             = 0x1,
++	ARRAY_1D_TILED_THIN1                             = 0x2,
++	ARRAY_1D_TILED_THICK                             = 0x3,
++	ARRAY_2D_TILED_THIN1                             = 0x4,
++	ARRAY_PRT_TILED_THIN1                            = 0x5,
++	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
++	ARRAY_2D_TILED_THICK                             = 0x7,
++	ARRAY_2D_TILED_XTHICK                            = 0x8,
++	ARRAY_PRT_TILED_THICK                            = 0x9,
++	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
++	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
++	ARRAY_3D_TILED_THIN1                             = 0xc,
++	ARRAY_3D_TILED_THICK                             = 0xd,
++	ARRAY_3D_TILED_XTHICK                            = 0xe,
++	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
++} ArrayMode;
++typedef enum PipeTiling {
++	CONFIG_1_PIPE                                    = 0x0,
++	CONFIG_2_PIPE                                    = 0x1,
++	CONFIG_4_PIPE                                    = 0x2,
++	CONFIG_8_PIPE                                    = 0x3,
++} PipeTiling;
++typedef enum BankTiling {
++	CONFIG_4_BANK                                    = 0x0,
++	CONFIG_8_BANK                                    = 0x1,
++} BankTiling;
++typedef enum GroupInterleave {
++	CONFIG_256B_GROUP                                = 0x0,
++	CONFIG_512B_GROUP                                = 0x1,
++} GroupInterleave;
++typedef enum RowTiling {
++	CONFIG_1KB_ROW                                   = 0x0,
++	CONFIG_2KB_ROW                                   = 0x1,
++	CONFIG_4KB_ROW                                   = 0x2,
++	CONFIG_8KB_ROW                                   = 0x3,
++	CONFIG_1KB_ROW_OPT                               = 0x4,
++	CONFIG_2KB_ROW_OPT                               = 0x5,
++	CONFIG_4KB_ROW_OPT                               = 0x6,
++	CONFIG_8KB_ROW_OPT                               = 0x7,
++} RowTiling;
++typedef enum BankSwapBytes {
++	CONFIG_128B_SWAPS                                = 0x0,
++	CONFIG_256B_SWAPS                                = 0x1,
++	CONFIG_512B_SWAPS                                = 0x2,
++	CONFIG_1KB_SWAPS                                 = 0x3,
++} BankSwapBytes;
++typedef enum SampleSplitBytes {
++	CONFIG_1KB_SPLIT                                 = 0x0,
++	CONFIG_2KB_SPLIT                                 = 0x1,
++	CONFIG_4KB_SPLIT                                 = 0x2,
++	CONFIG_8KB_SPLIT                                 = 0x3,
++} SampleSplitBytes;
++typedef enum NumPipes {
++	ADDR_CONFIG_1_PIPE                               = 0x0,
++	ADDR_CONFIG_2_PIPE                               = 0x1,
++	ADDR_CONFIG_4_PIPE                               = 0x2,
++	ADDR_CONFIG_8_PIPE                               = 0x3,
++} NumPipes;
++typedef enum PipeInterleaveSize {
++	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
++	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
++} PipeInterleaveSize;
++typedef enum BankInterleaveSize {
++	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
++	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
++	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
++	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
++} BankInterleaveSize;
++typedef enum NumShaderEngines {
++	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
++	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
++} NumShaderEngines;
++typedef enum ShaderEngineTileSize {
++	ADDR_CONFIG_SE_TILE_16                           = 0x0,
++	ADDR_CONFIG_SE_TILE_32                           = 0x1,
++} ShaderEngineTileSize;
++typedef enum NumGPUs {
++	ADDR_CONFIG_1_GPU                                = 0x0,
++	ADDR_CONFIG_2_GPU                                = 0x1,
++	ADDR_CONFIG_4_GPU                                = 0x2,
++} NumGPUs;
++typedef enum MultiGPUTileSize {
++	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
++	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
++	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
++	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
++} MultiGPUTileSize;
++typedef enum RowSize {
++	ADDR_CONFIG_1KB_ROW                              = 0x0,
++	ADDR_CONFIG_2KB_ROW                              = 0x1,
++	ADDR_CONFIG_4KB_ROW                              = 0x2,
++} RowSize;
++typedef enum NumLowerPipes {
++	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
++	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
++} NumLowerPipes;
++typedef enum ColorTransform {
++	DCC_CT_AUTO                                      = 0x0,
++	DCC_CT_NONE                                      = 0x1,
++	ABGR_TO_A_BG_G_RB                                = 0x2,
++	BGRA_TO_BG_G_RB_A                                = 0x3,
++} ColorTransform;
++typedef enum CompareRef {
++	REF_NEVER                                        = 0x0,
++	REF_LESS                                         = 0x1,
++	REF_EQUAL                                        = 0x2,
++	REF_LEQUAL                                       = 0x3,
++	REF_GREATER                                      = 0x4,
++	REF_NOTEQUAL                                     = 0x5,
++	REF_GEQUAL                                       = 0x6,
++	REF_ALWAYS                                       = 0x7,
++} CompareRef;
++typedef enum ReadSize {
++	READ_256_BITS                                    = 0x0,
++	READ_512_BITS                                    = 0x1,
++} ReadSize;
++typedef enum DepthFormat {
++	DEPTH_INVALID                                    = 0x0,
++	DEPTH_16                                         = 0x1,
++	DEPTH_X8_24                                      = 0x2,
++	DEPTH_8_24                                       = 0x3,
++	DEPTH_X8_24_FLOAT                                = 0x4,
++	DEPTH_8_24_FLOAT                                 = 0x5,
++	DEPTH_32_FLOAT                                   = 0x6,
++	DEPTH_X24_8_32_FLOAT                             = 0x7,
++} DepthFormat;
++typedef enum ZFormat {
++	Z_INVALID                                        = 0x0,
++	Z_16                                             = 0x1,
++	Z_24                                             = 0x2,
++	Z_32_FLOAT                                       = 0x3,
++} ZFormat;
++typedef enum StencilFormat {
++	STENCIL_INVALID                                  = 0x0,
++	STENCIL_8                                        = 0x1,
++} StencilFormat;
++typedef enum CmaskMode {
++	CMASK_CLEAR_NONE                                 = 0x0,
++	CMASK_CLEAR_ONE                                  = 0x1,
++	CMASK_CLEAR_ALL                                  = 0x2,
++	CMASK_ANY_EXPANDED                               = 0x3,
++	CMASK_ALPHA0_FRAG1                               = 0x4,
++	CMASK_ALPHA0_FRAG2                               = 0x5,
++	CMASK_ALPHA0_FRAG4                               = 0x6,
++	CMASK_ALPHA0_FRAGS                               = 0x7,
++	CMASK_ALPHA1_FRAG1                               = 0x8,
++	CMASK_ALPHA1_FRAG2                               = 0x9,
++	CMASK_ALPHA1_FRAG4                               = 0xa,
++	CMASK_ALPHA1_FRAGS                               = 0xb,
++	CMASK_ALPHAX_FRAG1                               = 0xc,
++	CMASK_ALPHAX_FRAG2                               = 0xd,
++	CMASK_ALPHAX_FRAG4                               = 0xe,
++	CMASK_ALPHAX_FRAGS                               = 0xf,
++} CmaskMode;
++typedef enum QuadExportFormat {
++	EXPORT_UNUSED                                    = 0x0,
++	EXPORT_32_R                                      = 0x1,
++	EXPORT_32_GR                                     = 0x2,
++	EXPORT_32_AR                                     = 0x3,
++	EXPORT_FP16_ABGR                                 = 0x4,
++	EXPORT_UNSIGNED16_ABGR                           = 0x5,
++	EXPORT_SIGNED16_ABGR                             = 0x6,
++	EXPORT_32_ABGR                                   = 0x7,
++} QuadExportFormat;
++typedef enum QuadExportFormatOld {
++	EXPORT_4P_32BPC_ABGR                             = 0x0,
++	EXPORT_4P_16BPC_ABGR                             = 0x1,
++	EXPORT_4P_32BPC_GR                               = 0x2,
++	EXPORT_4P_32BPC_AR                               = 0x3,
++	EXPORT_2P_32BPC_ABGR                             = 0x4,
++	EXPORT_8P_32BPC_R                                = 0x5,
++} QuadExportFormatOld;
++typedef enum ColorFormat {
++	COLOR_INVALID                                    = 0x0,
++	COLOR_8                                          = 0x1,
++	COLOR_16                                         = 0x2,
++	COLOR_8_8                                        = 0x3,
++	COLOR_32                                         = 0x4,
++	COLOR_16_16                                      = 0x5,
++	COLOR_10_11_11                                   = 0x6,
++	COLOR_11_11_10                                   = 0x7,
++	COLOR_10_10_10_2                                 = 0x8,
++	COLOR_2_10_10_10                                 = 0x9,
++	COLOR_8_8_8_8                                    = 0xa,
++	COLOR_32_32                                      = 0xb,
++	COLOR_16_16_16_16                                = 0xc,
++	COLOR_RESERVED_13                                = 0xd,
++	COLOR_32_32_32_32                                = 0xe,
++	COLOR_RESERVED_15                                = 0xf,
++	COLOR_5_6_5                                      = 0x10,
++	COLOR_1_5_5_5                                    = 0x11,
++	COLOR_5_5_5_1                                    = 0x12,
++	COLOR_4_4_4_4                                    = 0x13,
++	COLOR_8_24                                       = 0x14,
++	COLOR_24_8                                       = 0x15,
++	COLOR_X24_8_32_FLOAT                             = 0x16,
++	COLOR_RESERVED_23                                = 0x17,
++} ColorFormat;
++typedef enum SurfaceFormat {
++	FMT_INVALID                                      = 0x0,
++	FMT_8                                            = 0x1,
++	FMT_16                                           = 0x2,
++	FMT_8_8                                          = 0x3,
++	FMT_32                                           = 0x4,
++	FMT_16_16                                        = 0x5,
++	FMT_10_11_11                                     = 0x6,
++	FMT_11_11_10                                     = 0x7,
++	FMT_10_10_10_2                                   = 0x8,
++	FMT_2_10_10_10                                   = 0x9,
++	FMT_8_8_8_8                                      = 0xa,
++	FMT_32_32                                        = 0xb,
++	FMT_16_16_16_16                                  = 0xc,
++	FMT_32_32_32                                     = 0xd,
++	FMT_32_32_32_32                                  = 0xe,
++	FMT_RESERVED_4                                   = 0xf,
++	FMT_5_6_5                                        = 0x10,
++	FMT_1_5_5_5                                      = 0x11,
++	FMT_5_5_5_1                                      = 0x12,
++	FMT_4_4_4_4                                      = 0x13,
++	FMT_8_24                                         = 0x14,
++	FMT_24_8                                         = 0x15,
++	FMT_X24_8_32_FLOAT                               = 0x16,
++	FMT_RESERVED_33                                  = 0x17,
++	FMT_11_11_10_FLOAT                               = 0x18,
++	FMT_16_FLOAT                                     = 0x19,
++	FMT_32_FLOAT                                     = 0x1a,
++	FMT_16_16_FLOAT                                  = 0x1b,
++	FMT_8_24_FLOAT                                   = 0x1c,
++	FMT_24_8_FLOAT                                   = 0x1d,
++	FMT_32_32_FLOAT                                  = 0x1e,
++	FMT_10_11_11_FLOAT                               = 0x1f,
++	FMT_16_16_16_16_FLOAT                            = 0x20,
++	FMT_3_3_2                                        = 0x21,
++	FMT_6_5_5                                        = 0x22,
++	FMT_32_32_32_32_FLOAT                            = 0x23,
++	FMT_RESERVED_36                                  = 0x24,
++	FMT_1                                            = 0x25,
++	FMT_1_REVERSED                                   = 0x26,
++	FMT_GB_GR                                        = 0x27,
++	FMT_BG_RG                                        = 0x28,
++	FMT_32_AS_8                                      = 0x29,
++	FMT_32_AS_8_8                                    = 0x2a,
++	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
++	FMT_8_8_8                                        = 0x2c,
++	FMT_16_16_16                                     = 0x2d,
++	FMT_16_16_16_FLOAT                               = 0x2e,
++	FMT_4_4                                          = 0x2f,
++	FMT_32_32_32_FLOAT                               = 0x30,
++	FMT_BC1                                          = 0x31,
++	FMT_BC2                                          = 0x32,
++	FMT_BC3                                          = 0x33,
++	FMT_BC4                                          = 0x34,
++	FMT_BC5                                          = 0x35,
++	FMT_BC6                                          = 0x36,
++	FMT_BC7                                          = 0x37,
++	FMT_32_AS_32_32_32_32                            = 0x38,
++	FMT_APC3                                         = 0x39,
++	FMT_APC4                                         = 0x3a,
++	FMT_APC5                                         = 0x3b,
++	FMT_APC6                                         = 0x3c,
++	FMT_APC7                                         = 0x3d,
++	FMT_CTX1                                         = 0x3e,
++	FMT_RESERVED_63                                  = 0x3f,
++} SurfaceFormat;
++typedef enum BUF_DATA_FORMAT {
++	BUF_DATA_FORMAT_INVALID                          = 0x0,
++	BUF_DATA_FORMAT_8                                = 0x1,
++	BUF_DATA_FORMAT_16                               = 0x2,
++	BUF_DATA_FORMAT_8_8                              = 0x3,
++	BUF_DATA_FORMAT_32                               = 0x4,
++	BUF_DATA_FORMAT_16_16                            = 0x5,
++	BUF_DATA_FORMAT_10_11_11                         = 0x6,
++	BUF_DATA_FORMAT_11_11_10                         = 0x7,
++	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
++	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
++	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
++	BUF_DATA_FORMAT_32_32                            = 0xb,
++	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
++	BUF_DATA_FORMAT_32_32_32                         = 0xd,
++	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
++	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
++} BUF_DATA_FORMAT;
++typedef enum IMG_DATA_FORMAT {
++	IMG_DATA_FORMAT_INVALID                          = 0x0,
++	IMG_DATA_FORMAT_8                                = 0x1,
++	IMG_DATA_FORMAT_16                               = 0x2,
++	IMG_DATA_FORMAT_8_8                              = 0x3,
++	IMG_DATA_FORMAT_32                               = 0x4,
++	IMG_DATA_FORMAT_16_16                            = 0x5,
++	IMG_DATA_FORMAT_10_11_11                         = 0x6,
++	IMG_DATA_FORMAT_11_11_10                         = 0x7,
++	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
++	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
++	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
++	IMG_DATA_FORMAT_32_32                            = 0xb,
++	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
++	IMG_DATA_FORMAT_32_32_32                         = 0xd,
++	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
++	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
++	IMG_DATA_FORMAT_5_6_5                            = 0x10,
++	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
++	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
++	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
++	IMG_DATA_FORMAT_8_24                             = 0x14,
++	IMG_DATA_FORMAT_24_8                             = 0x15,
++	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
++	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
++	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
++	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
++	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
++	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
++	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
++	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
++	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
++	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
++	IMG_DATA_FORMAT_GB_GR                            = 0x20,
++	IMG_DATA_FORMAT_BG_RG                            = 0x21,
++	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
++	IMG_DATA_FORMAT_BC1                              = 0x23,
++	IMG_DATA_FORMAT_BC2                              = 0x24,
++	IMG_DATA_FORMAT_BC3                              = 0x25,
++	IMG_DATA_FORMAT_BC4                              = 0x26,
++	IMG_DATA_FORMAT_BC5                              = 0x27,
++	IMG_DATA_FORMAT_BC6                              = 0x28,
++	IMG_DATA_FORMAT_BC7                              = 0x29,
++	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
++	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
++	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
++	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
++	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
++	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
++	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
++	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
++	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
++	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
++	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
++	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
++	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
++	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
++	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
++	IMG_DATA_FORMAT_4_4                              = 0x39,
++	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
++	IMG_DATA_FORMAT_1                                = 0x3b,
++	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
++	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
++	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
++	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
++} IMG_DATA_FORMAT;
++typedef enum BUF_NUM_FORMAT {
++	BUF_NUM_FORMAT_UNORM                             = 0x0,
++	BUF_NUM_FORMAT_SNORM                             = 0x1,
++	BUF_NUM_FORMAT_USCALED                           = 0x2,
++	BUF_NUM_FORMAT_SSCALED                           = 0x3,
++	BUF_NUM_FORMAT_UINT                              = 0x4,
++	BUF_NUM_FORMAT_SINT                              = 0x5,
++	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
++	BUF_NUM_FORMAT_FLOAT                             = 0x7,
++} BUF_NUM_FORMAT;
++typedef enum IMG_NUM_FORMAT {
++	IMG_NUM_FORMAT_UNORM                             = 0x0,
++	IMG_NUM_FORMAT_SNORM                             = 0x1,
++	IMG_NUM_FORMAT_USCALED                           = 0x2,
++	IMG_NUM_FORMAT_SSCALED                           = 0x3,
++	IMG_NUM_FORMAT_UINT                              = 0x4,
++	IMG_NUM_FORMAT_SINT                              = 0x5,
++	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
++	IMG_NUM_FORMAT_FLOAT                             = 0x7,
++	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
++	IMG_NUM_FORMAT_SRGB                              = 0x9,
++	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
++	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
++	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
++	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
++	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
++	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
++} IMG_NUM_FORMAT;
++typedef enum TileType {
++	ARRAY_COLOR_TILE                                 = 0x0,
++	ARRAY_DEPTH_TILE                                 = 0x1,
++} TileType;
++typedef enum NonDispTilingOrder {
++	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
++	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
++} NonDispTilingOrder;
++typedef enum MicroTileMode {
++	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
++	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
++	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
++	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
++	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
++} MicroTileMode;
++typedef enum TileSplit {
++	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
++	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
++	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
++	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
++	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
++	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
++	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
++} TileSplit;
++typedef enum SampleSplit {
++	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
++	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
++	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
++	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
++} SampleSplit;
++typedef enum PipeConfig {
++	ADDR_SURF_P2                                     = 0x0,
++	ADDR_SURF_P2_RESERVED0                           = 0x1,
++	ADDR_SURF_P2_RESERVED1                           = 0x2,
++	ADDR_SURF_P2_RESERVED2                           = 0x3,
++	ADDR_SURF_P4_8x16                                = 0x4,
++	ADDR_SURF_P4_16x16                               = 0x5,
++	ADDR_SURF_P4_16x32                               = 0x6,
++	ADDR_SURF_P4_32x32                               = 0x7,
++	ADDR_SURF_P8_16x16_8x16                          = 0x8,
++	ADDR_SURF_P8_16x32_8x16                          = 0x9,
++	ADDR_SURF_P8_32x32_8x16                          = 0xa,
++	ADDR_SURF_P8_16x32_16x16                         = 0xb,
++	ADDR_SURF_P8_32x32_16x16                         = 0xc,
++	ADDR_SURF_P8_32x32_16x32                         = 0xd,
++	ADDR_SURF_P8_32x64_32x32                         = 0xe,
++	ADDR_SURF_P8_RESERVED0                           = 0xf,
++	ADDR_SURF_P16_32x32_8x16                         = 0x10,
++	ADDR_SURF_P16_32x32_16x16                        = 0x11,
++} PipeConfig;
++typedef enum NumBanks {
++	ADDR_SURF_2_BANK                                 = 0x0,
++	ADDR_SURF_4_BANK                                 = 0x1,
++	ADDR_SURF_8_BANK                                 = 0x2,
++	ADDR_SURF_16_BANK                                = 0x3,
++} NumBanks;
++typedef enum BankWidth {
++	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
++	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
++	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
++	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
++} BankWidth;
++typedef enum BankHeight {
++	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
++	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
++	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
++	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
++} BankHeight;
++typedef enum BankWidthHeight {
++	ADDR_SURF_BANK_WH_1                              = 0x0,
++	ADDR_SURF_BANK_WH_2                              = 0x1,
++	ADDR_SURF_BANK_WH_4                              = 0x2,
++	ADDR_SURF_BANK_WH_8                              = 0x3,
++} BankWidthHeight;
++typedef enum MacroTileAspect {
++	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
++	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
++	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
++	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
++} MacroTileAspect;
++typedef enum GATCL1RequestType {
++	GATCL1_TYPE_NORMAL                               = 0x0,
++	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
++	GATCL1_TYPE_BYPASS                               = 0x2,
++} GATCL1RequestType;
++typedef enum TCC_CACHE_POLICIES {
++	TCC_CACHE_POLICY_LRU                             = 0x0,
++	TCC_CACHE_POLICY_STREAM                          = 0x1,
++} TCC_CACHE_POLICIES;
++typedef enum MTYPE {
++	MTYPE_NC_NV                                      = 0x0,
++	MTYPE_NC                                         = 0x1,
++	MTYPE_CC                                         = 0x2,
++	MTYPE_UC                                         = 0x3,
++} MTYPE;
++typedef enum PERFMON_COUNTER_MODE {
++	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
++	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
++	PERFMON_COUNTER_MODE_MAX                         = 0x2,
++	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
++	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
++	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
++	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
++	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
++	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
++	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
++} PERFMON_COUNTER_MODE;
++typedef enum PERFMON_SPM_MODE {
++	PERFMON_SPM_MODE_OFF                             = 0x0,
++	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
++	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
++	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
++	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
++	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
++	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
++	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
++	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
++	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
++	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
++} PERFMON_SPM_MODE;
++typedef enum SurfaceTiling {
++	ARRAY_LINEAR                                     = 0x0,
++	ARRAY_TILED                                      = 0x1,
++} SurfaceTiling;
++typedef enum SurfaceArray {
++	ARRAY_1D                                         = 0x0,
++	ARRAY_2D                                         = 0x1,
++	ARRAY_3D                                         = 0x2,
++	ARRAY_3D_SLICE                                   = 0x3,
++} SurfaceArray;
++typedef enum ColorArray {
++	ARRAY_2D_ALT_COLOR                               = 0x0,
++	ARRAY_2D_COLOR                                   = 0x1,
++	ARRAY_3D_SLICE_COLOR                             = 0x3,
++} ColorArray;
++typedef enum DepthArray {
++	ARRAY_2D_ALT_DEPTH                               = 0x0,
++	ARRAY_2D_DEPTH                                   = 0x1,
++} DepthArray;
++typedef enum ENUM_NUM_SIMD_PER_CU {
++	NUM_SIMD_PER_CU                                  = 0x4,
++} ENUM_NUM_SIMD_PER_CU;
++typedef enum MEM_PWR_FORCE_CTRL {
++	NO_FORCE_REQUEST                                 = 0x0,
++	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
++	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
++	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
++} MEM_PWR_FORCE_CTRL;
++typedef enum MEM_PWR_FORCE_CTRL2 {
++	NO_FORCE_REQ                                     = 0x0,
++	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
++} MEM_PWR_FORCE_CTRL2;
++typedef enum MEM_PWR_DIS_CTRL {
++	ENABLE_MEM_PWR_CTRL                              = 0x0,
++	DISABLE_MEM_PWR_CTRL                             = 0x1,
++} MEM_PWR_DIS_CTRL;
++typedef enum MEM_PWR_SEL_CTRL {
++	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
++	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
++	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
++} MEM_PWR_SEL_CTRL;
++typedef enum MEM_PWR_SEL_CTRL2 {
++	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
++	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
++} MEM_PWR_SEL_CTRL2;
++
++#endif /* UVD_6_0_ENUM_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
+new file mode 100644
+index 0000000..9917c54
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
+@@ -0,0 +1,1034 @@
++/*
++ * UVD_6_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef UVD_6_0_SH_MASK_H
++#define UVD_6_0_SH_MASK_H
++
++#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
++#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
++#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
++#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
++#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
++#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
++#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
++#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
++#define UVD_SEMA_CMD__MODE_MASK 0x40
++#define UVD_SEMA_CMD__MODE__SHIFT 0x6
++#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
++#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
++#define UVD_SEMA_CMD__VMID_MASK 0xf00
++#define UVD_SEMA_CMD__VMID__SHIFT 0x8
++#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
++#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
++#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
++#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
++#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
++#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
++#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
++#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
++#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
++#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
++#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
++#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
++#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
++#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
++#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3
++#define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0
++#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
++#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
++#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
++#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
++#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
++#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
++#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
++#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
++#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
++#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
++#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
++#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
++#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
++#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
++#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
++#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
++#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
++#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
++#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
++#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
++#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
++#define UVD_CTX_DATA__DATA_MASK 0xffffffff
++#define UVD_CTX_DATA__DATA__SHIFT 0x0
++#define UVD_CGC_GATE__SYS_MASK 0x1
++#define UVD_CGC_GATE__SYS__SHIFT 0x0
++#define UVD_CGC_GATE__UDEC_MASK 0x2
++#define UVD_CGC_GATE__UDEC__SHIFT 0x1
++#define UVD_CGC_GATE__MPEG2_MASK 0x4
++#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
++#define UVD_CGC_GATE__REGS_MASK 0x8
++#define UVD_CGC_GATE__REGS__SHIFT 0x3
++#define UVD_CGC_GATE__RBC_MASK 0x10
++#define UVD_CGC_GATE__RBC__SHIFT 0x4
++#define UVD_CGC_GATE__LMI_MC_MASK 0x20
++#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
++#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
++#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
++#define UVD_CGC_GATE__IDCT_MASK 0x80
++#define UVD_CGC_GATE__IDCT__SHIFT 0x7
++#define UVD_CGC_GATE__MPRD_MASK 0x100
++#define UVD_CGC_GATE__MPRD__SHIFT 0x8
++#define UVD_CGC_GATE__MPC_MASK 0x200
++#define UVD_CGC_GATE__MPC__SHIFT 0x9
++#define UVD_CGC_GATE__LBSI_MASK 0x400
++#define UVD_CGC_GATE__LBSI__SHIFT 0xa
++#define UVD_CGC_GATE__LRBBM_MASK 0x800
++#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
++#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
++#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
++#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
++#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
++#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
++#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
++#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
++#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
++#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
++#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
++#define UVD_CGC_GATE__WCB_MASK 0x20000
++#define UVD_CGC_GATE__WCB__SHIFT 0x11
++#define UVD_CGC_GATE__VCPU_MASK 0x40000
++#define UVD_CGC_GATE__VCPU__SHIFT 0x12
++#define UVD_CGC_GATE__SCPU_MASK 0x80000
++#define UVD_CGC_GATE__SCPU__SHIFT 0x13
++#define UVD_CGC_GATE__JPEG_MASK 0x100000
++#define UVD_CGC_GATE__JPEG__SHIFT 0x14
++#define UVD_CGC_GATE__JPEG2_MASK 0x200000
++#define UVD_CGC_GATE__JPEG2__SHIFT 0x15
++#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
++#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
++#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
++#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
++#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
++#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
++#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
++#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
++#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
++#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
++#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
++#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
++#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
++#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
++#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
++#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
++#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
++#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
++#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
++#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
++#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
++#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
++#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
++#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
++#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
++#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
++#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
++#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
++#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
++#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
++#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
++#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
++#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
++#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
++#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
++#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
++#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
++#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
++#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
++#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
++#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
++#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
++#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
++#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
++#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
++#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
++#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
++#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
++#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
++#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
++#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
++#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
++#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
++#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
++#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
++#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
++#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
++#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
++#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000
++#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
++#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000
++#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
++#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
++#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
++#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
++#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
++#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
++#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
++#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
++#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
++#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
++#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
++#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
++#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
++#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
++#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
++#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
++#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
++#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
++#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
++#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
++#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
++#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
++#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
++#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
++#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
++#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
++#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
++#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
++#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
++#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
++#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
++#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
++#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
++#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
++#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
++#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
++#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
++#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
++#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
++#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
++#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
++#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
++#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
++#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
++#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
++#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
++#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
++#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
++#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
++#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000
++#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
++#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
++#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
++#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
++#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
++#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
++#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
++#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
++#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
++#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
++#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
++#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
++#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
++#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
++#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
++#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
++#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
++#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
++#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
++#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
++#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
++#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
++#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
++#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
++#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
++#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
++#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
++#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
++#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
++#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
++#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
++#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000
++#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf
++#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000
++#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10
++#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000
++#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11
++#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000
++#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12
++#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
++#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
++#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
++#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
++#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
++#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
++#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
++#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
++#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
++#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
++#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
++#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
++#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
++#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
++#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
++#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
++#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
++#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
++#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
++#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
++#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
++#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
++#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
++#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
++#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
++#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
++#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
++#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
++#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
++#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
++#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
++#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
++#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
++#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
++#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
++#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
++#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
++#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
++#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
++#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
++#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
++#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
++#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
++#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
++#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
++#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
++#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
++#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
++#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
++#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
++#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
++#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
++#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
++#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
++#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
++#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
++#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
++#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
++#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
++#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
++#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
++#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
++#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
++#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
++#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
++#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
++#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
++#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
++#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
++#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
++#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
++#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
++#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
++#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
++#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
++#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
++#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
++#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
++#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
++#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
++#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
++#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
++#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
++#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
++#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
++#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
++#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
++#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
++#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
++#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
++#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
++#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
++#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
++#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
++#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
++#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
++#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
++#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
++#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
++#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
++#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
++#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
++#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
++#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
++#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
++#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
++#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
++#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
++#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
++#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
++#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
++#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
++#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
++#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
++#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
++#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
++#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
++#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
++#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
++#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
++#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
++#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
++#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
++#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
++#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
++#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
++#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
++#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
++#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
++#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
++#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
++#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
++#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
++#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
++#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
++#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
++#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
++#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
++#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
++#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
++#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
++#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
++#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
++#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
++#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
++#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
++#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
++#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
++#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
++#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
++#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
++#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
++#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
++#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
++#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
++#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
++#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
++#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
++#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
++#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
++#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
++#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
++#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
++#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
++#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
++#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
++#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
++#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
++#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
++#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
++#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
++#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
++#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
++#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
++#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
++#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
++#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
++#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
++#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
++#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
++#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
++#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
++#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
++#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
++#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
++#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
++#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
++#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
++#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
++#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
++#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
++#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
++#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
++#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
++#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
++#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
++#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
++#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
++#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
++#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
++#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
++#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
++#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
++#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
++#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
++#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
++#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
++#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
++#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
++#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
++#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
++#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
++#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
++#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
++#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
++#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
++#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
++#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
++#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
++#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
++#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
++#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
++#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
++#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
++#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
++#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
++#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
++#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
++#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
++#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
++#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
++#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
++#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
++#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
++#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
++#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
++#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000
++#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
++#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
++#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
++#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000
++#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
++#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
++#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
++#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
++#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
++#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
++#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
++#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
++#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
++#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
++#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
++#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
++#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
++#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
++#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
++#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
++#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
++#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
++#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
++#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
++#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
++#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
++#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
++#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
++#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
++#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
++#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
++#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
++#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9
++#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
++#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
++#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
++#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
++#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
++#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
++#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
++#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
++#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
++#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
++#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
++#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
++#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
++#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
++#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000
++#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
++#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000
++#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
++#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000
++#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
++#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000
++#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
++#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000
++#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
++#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000
++#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
++#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000
++#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
++#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000
++#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
++#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000
++#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
++#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000
++#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
++#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000
++#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
++#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000
++#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
++#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000
++#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
++#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000
++#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
++#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000
++#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
++#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf
++#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
++#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
++#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
++#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf
++#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
++#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
++#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
++#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
++#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
++#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
++#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
++#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
++#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
++#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
++#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
++#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
++#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
++#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
++#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
++#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
++#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
++#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
++#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
++#define UVD_STATUS__RBC_BUSY_MASK 0x1
++#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
++#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
++#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
++#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
++#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
++#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
++#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
++#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1
++#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
++#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
++#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
++#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4
++#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
++#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8
++#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
++#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10
++#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
++#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20
++#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
++#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40
++#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
++#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80
++#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
++#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
++#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
++#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
++#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
++#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
++#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
++#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800
++#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
++#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000
++#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
++#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
++#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
++#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
++#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
++#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
++#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
++#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8
++#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
++#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
++#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
++#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20
++#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
++#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40
++#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
++#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80
++#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
++#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
++#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
++#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
++#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
++#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400
++#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
++#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
++#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
++#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000
++#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
++#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
++#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
++#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
++#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
++#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
++#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
++#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4
++#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
++#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8
++#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
++#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10
++#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0
++#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00
++#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8
++#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000
++#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc
++#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000
++#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10
++#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000
++#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14
++#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000
++#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18
++#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000
++#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c
++#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf
++#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0
++#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0
++#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00
++#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8
++#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000
++#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc
++#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000
++#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000
++#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18
++#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000
++#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c
++#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
++#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
++#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
++#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
++#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
++#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
++#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
++#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
++#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
++#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
++#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
++#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
++#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
++#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
++#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
++#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
++#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
++#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
++#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
++#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
++#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
++#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
++#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
++#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
++#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
++#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
++#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
++#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
++#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
++#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
++#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
++#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
++#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
++#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
++#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
++#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
++#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
++#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
++#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
++#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
++#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
++#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
++#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
++#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
++#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
++#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
++#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
++#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
++#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
++#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
++#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
++#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
++#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000
++#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
++#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000
++#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf
++#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
++#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
++#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
++#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
++#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
++#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
++#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
++#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
++#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
++#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000
++#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
++#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
++#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
++#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3
++#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
++#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4
++#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
++#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8
++#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
++#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10
++#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
++#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20
++#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
++#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0
++#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
++#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100
++#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
++#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200
++#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
++#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400
++#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
++#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0
++#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff
++#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7
++#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
++#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
++#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
++#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
++#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
++#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
++#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
++#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
++#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
++#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
++#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
++#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
++#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
++#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
++#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
++#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
++#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
++
++#endif /* UVD_6_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0027-yocto-amd-drm-amdgpu-add-OSS-2-4-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0027-yocto-amd-drm-amdgpu-add-OSS-2-4-register-headers.patch
new file mode 100644
index 00000000..7c38e75f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0027-yocto-amd-drm-amdgpu-add-OSS-2-4-register-headers.patch
@@ -0,0 +1,198 @@
+From 111079e28f955384ec02f2e4f2be944d2a7d81e9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:35:39 -0400
+Subject: drm/amdgpu: add VCE 2.0 register headers
+
+These are register headers for the VCE (Video Codec Engine)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h
+new file mode 100644
+index 0000000..9064338
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h
+@@ -0,0 +1,68 @@
++/*
++ * VCE_2_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef VCE_2_0_D_H
++#define VCE_2_0_D_H
++
++#define mmVCE_STATUS                                                            0x8001
++#define mmVCE_VCPU_CNTL                                                         0x8005
++#define mmVCE_VCPU_CACHE_OFFSET0                                                0x8009
++#define mmVCE_VCPU_CACHE_SIZE0                                                  0x800a
++#define mmVCE_VCPU_CACHE_OFFSET1                                                0x800b
++#define mmVCE_VCPU_CACHE_SIZE1                                                  0x800c
++#define mmVCE_VCPU_CACHE_OFFSET2                                                0x800d
++#define mmVCE_VCPU_CACHE_SIZE2                                                  0x800e
++#define mmVCE_SOFT_RESET                                                        0x8048
++#define mmVCE_RB_BASE_LO2                                                       0x805b
++#define mmVCE_RB_BASE_HI2                                                       0x805c
++#define mmVCE_RB_SIZE2                                                          0x805d
++#define mmVCE_RB_RPTR2                                                          0x805e
++#define mmVCE_RB_WPTR2                                                          0x805f
++#define mmVCE_RB_BASE_LO                                                        0x8060
++#define mmVCE_RB_BASE_HI                                                        0x8061
++#define mmVCE_RB_SIZE                                                           0x8062
++#define mmVCE_RB_RPTR                                                           0x8063
++#define mmVCE_RB_WPTR                                                           0x8064
++#define mmVCE_RB_ARB_CTRL                                                       0x809f
++#define mmVCE_CLOCK_GATING_A                                                    0x80be
++#define mmVCE_CLOCK_GATING_B                                                    0x80bf
++#define mmVCE_UENC_DMA_DCLK_CTRL                                                0x8390
++#define mmVCE_CGTT_CLK_OVERRIDE                                                 0x81e8
++#define mmVCE_UENC_CLOCK_GATING                                                 0x81ef
++#define mmVCE_UENC_REG_CLOCK_GATING                                             0x81f0
++#define mmVCE_SYS_INT_EN                                                        0x84c0
++#define mmVCE_SYS_INT_STATUS                                                    0x84c1
++#define mmVCE_SYS_INT_ACK                                                       0x84c1
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR                                          0x8517
++#define mmVCE_LMI_CTRL2                                                         0x851d
++#define mmVCE_LMI_SWAP_CNTL3                                                    0x851e
++#define mmVCE_LMI_CTRL                                                          0x8526
++#define mmVCE_LMI_STATUS                                                        0x8527
++#define mmVCE_LMI_VM_CTRL                                                       0x8528
++#define mmVCE_LMI_SWAP_CNTL                                                     0x852d
++#define mmVCE_LMI_SWAP_CNTL1                                                    0x852e
++#define mmVCE_LMI_SWAP_CNTL2                                                    0x8533
++#define mmVCE_LMI_MISC_CTRL                                                     0x8535
++#define mmVCE_LMI_CACHE_CTRL                                                    0x853d
++
++#endif /* VCE_2_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h
+new file mode 100644
+index 0000000..9b4b952
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h
+@@ -0,0 +1,104 @@
++/*
++ * VCE_2_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef VCE_2_0_SH_MASK_H
++#define VCE_2_0_SH_MASK_H
++
++#define VCE_STATUS__JOB_BUSY_MASK 0x1
++#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
++#define VCE_STATUS__VCPU_REPORT_MASK 0xfe
++#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
++#define VCE_STATUS__UENC_BUSY_MASK 0x100
++#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
++#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
++#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
++#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
++#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
++#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff
++#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff
++#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff
++#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff
++#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff
++#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff
++#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
++#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1
++#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
++#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0
++#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff
++#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0
++#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
++#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0
++#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
++#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0
++#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
++#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0
++#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff
++#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0
++#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
++#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0
++#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
++#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0
++#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
++#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1
++#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0
++#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2
++#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1
++#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4
++#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2
++#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8
++#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
++#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
++#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
++#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
++#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
++#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3
++#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
++#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3
++#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
++#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1
++#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
++
++#endif /* VCE_2_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0028-yocto-amd-drm-amdgpu-add-OSS-2-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0028-yocto-amd-drm-amdgpu-add-OSS-2-0-register-headers.patch
new file mode 100644
index 00000000..c8a973db
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0028-yocto-amd-drm-amdgpu-add-OSS-2-0-register-headers.patch
@@ -0,0 +1,219 @@
+From a281d8c0d6a871f238c9942765c6356eabae5e40 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:36:06 -0400
+Subject: drm/amdgpu: add VCE 3.0 register headers
+
+These are register headers for the VCE (Video Codec Engine)
+block on the GPU.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h
+new file mode 100644
+index 0000000..3e698b7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h
+@@ -0,0 +1,73 @@
++/*
++ * VCE_3_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef VCE_3_0_D_H
++#define VCE_3_0_D_H
++
++#define mmVCE_STATUS                                                            0x8001
++#define mmVCE_VCPU_CNTL                                                         0x8005
++#define mmVCE_VCPU_CACHE_OFFSET0                                                0x8009
++#define mmVCE_VCPU_CACHE_SIZE0                                                  0x800a
++#define mmVCE_VCPU_CACHE_OFFSET1                                                0x800b
++#define mmVCE_VCPU_CACHE_SIZE1                                                  0x800c
++#define mmVCE_VCPU_CACHE_OFFSET2                                                0x800d
++#define mmVCE_VCPU_CACHE_SIZE2                                                  0x800e
++#define mmVCE_SOFT_RESET                                                        0x8048
++#define mmVCE_RB_BASE_LO2                                                       0x805b
++#define mmVCE_RB_BASE_HI2                                                       0x805c
++#define mmVCE_RB_SIZE2                                                          0x805d
++#define mmVCE_RB_RPTR2                                                          0x805e
++#define mmVCE_RB_WPTR2                                                          0x805f
++#define mmVCE_RB_BASE_LO                                                        0x8060
++#define mmVCE_RB_BASE_HI                                                        0x8061
++#define mmVCE_RB_SIZE                                                           0x8062
++#define mmVCE_RB_RPTR                                                           0x8063
++#define mmVCE_RB_WPTR                                                           0x8064
++#define mmVCE_RB_ARB_CTRL                                                       0x809f
++#define mmVCE_CLOCK_GATING_A                                                    0x80be
++#define mmVCE_CLOCK_GATING_B                                                    0x80bf
++#define mmVCE_RB_BASE_LO3                                                       0x80d4
++#define mmVCE_RB_BASE_HI3                                                       0x80d5
++#define mmVCE_RB_SIZE3                                                          0x80d6
++#define mmVCE_RB_RPTR3                                                          0x80d7
++#define mmVCE_RB_WPTR3                                                          0x80d8
++#define mmVCE_UENC_DMA_DCLK_CTRL                                                0x8390
++#define mmVCE_UENC_CLOCK_GATING                                                 0x81ef
++#define mmVCE_UENC_REG_CLOCK_GATING                                             0x81f0
++#define mmVCE_UENC_CLOCK_GATING_2                                               0x8210
++#define mmVCE_SYS_INT_EN                                                        0x8540
++#define mmVCE_SYS_INT_STATUS                                                    0x8541
++#define mmVCE_SYS_INT_ACK                                                       0x8541
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR                                          0x8597
++#define mmVCE_LMI_CTRL2                                                         0x859d
++#define mmVCE_LMI_SWAP_CNTL3                                                    0x859e
++#define mmVCE_LMI_CTRL                                                          0x85a6
++#define mmVCE_LMI_STATUS                                                        0x85a7
++#define mmVCE_LMI_VM_CTRL                                                       0x85a8
++#define mmVCE_LMI_SWAP_CNTL                                                     0x85ad
++#define mmVCE_LMI_SWAP_CNTL1                                                    0x85ae
++#define mmVCE_LMI_SWAP_CNTL2                                                    0x85b3
++#define mmVCE_LMI_MISC_CTRL                                                     0x85b5
++#define mmVCE_LMI_CACHE_CTRL                                                    0x85bd
++
++#endif /* VCE_3_0_D_H */
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h
+new file mode 100644
+index 0000000..235dc13
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h
+@@ -0,0 +1,120 @@
++/*
++ * VCE_3_0 Register documentation
++ *
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef VCE_3_0_SH_MASK_H
++#define VCE_3_0_SH_MASK_H
++
++#define VCE_STATUS__JOB_BUSY_MASK 0x1
++#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
++#define VCE_STATUS__VCPU_REPORT_MASK 0xfe
++#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
++#define VCE_STATUS__UENC_BUSY_MASK 0x100
++#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
++#define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
++#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
++#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
++#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
++#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
++#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
++#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
++#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
++#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff
++#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff
++#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff
++#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff
++#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff
++#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff
++#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
++#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1
++#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
++#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0
++#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff
++#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0
++#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
++#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0
++#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
++#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0
++#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
++#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0
++#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff
++#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0
++#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
++#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0
++#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
++#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0
++#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
++#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x10000
++#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10
++#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xffffffc0
++#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xffffffff
++#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_SIZE3__RB_SIZE_MASK 0x7ffff0
++#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4
++#define VCE_RB_RPTR3__RB_RPTR_MASK 0x7ffff0
++#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4
++#define VCE_RB_WPTR3__RB_WPTR_MASK 0x7ffff0
++#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4
++#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1
++#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0
++#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2
++#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1
++#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4
++#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2
++#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8
++#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
++#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
++#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
++#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
++#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
++#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3
++#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
++#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3
++#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
++#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1
++#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
++
++#endif /* VCE_3_0_SH_MASK_H */
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0029-yocto-amd-drm-amdgpu-add-GMC-8-2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0029-yocto-amd-drm-amdgpu-add-GMC-8-2-register-headers.patch
new file mode 100644
index 00000000..8073007e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0029-yocto-amd-drm-amdgpu-add-GMC-8-2-register-headers.patch
@@ -0,0 +1,623 @@
+From a2d24fafbed3fa47fb2568486475fa32f76a9dbe Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:42:01 -0400
+Subject: drm/amdgpu: add amdgpu uapi header
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This header defines the ioctl interface to the driver.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+new file mode 100755
+index 0000000..5330a46
+--- /dev/null
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -0,0 +1,600 @@
++/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
++ *
++ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
++ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
++ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ *    Kevin E. Martin <martin@valinux.com>
++ *    Gareth Hughes <gareth@valinux.com>
++ *    Keith Whitwell <keith@tungstengraphics.com>
++ */
++
++#ifndef __AMDGPU_DRM_H__
++#define __AMDGPU_DRM_H__
++
++#include <drm/drm.h>
++
++#define DRM_AMDGPU_GEM_CREATE		0x00
++#define DRM_AMDGPU_GEM_MMAP		0x01
++#define DRM_AMDGPU_CTX			0x02
++#define DRM_AMDGPU_BO_LIST		0x03
++#define DRM_AMDGPU_CS			0x04
++#define DRM_AMDGPU_INFO			0x05
++#define DRM_AMDGPU_GEM_METADATA		0x06
++#define DRM_AMDGPU_GEM_WAIT_IDLE	0x07
++#define DRM_AMDGPU_GEM_VA		0x08
++#define DRM_AMDGPU_WAIT_CS		0x09
++#define DRM_AMDGPU_GEM_OP		0x10
++#define DRM_AMDGPU_GEM_USERPTR		0x11
++
++#define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
++#define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
++#define DRM_IOCTL_AMDGPU_CTX		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
++#define DRM_IOCTL_AMDGPU_BO_LIST	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
++#define DRM_IOCTL_AMDGPU_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
++#define DRM_IOCTL_AMDGPU_INFO		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
++#define DRM_IOCTL_AMDGPU_GEM_METADATA	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
++#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
++#define DRM_IOCTL_AMDGPU_GEM_VA		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va)
++#define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
++#define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
++#define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
++
++#define AMDGPU_GEM_DOMAIN_CPU		0x1
++#define AMDGPU_GEM_DOMAIN_GTT		0x2
++#define AMDGPU_GEM_DOMAIN_VRAM		0x4
++#define AMDGPU_GEM_DOMAIN_GDS		0x8
++#define AMDGPU_GEM_DOMAIN_GWS		0x10
++#define AMDGPU_GEM_DOMAIN_OA		0x20
++
++#define AMDGPU_GEM_DOMAIN_MASK		0x3F
++
++/* Flag that CPU access will be required for the case of VRAM domain */
++#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
++/* Flag that CPU access will not work, this VRAM domain is invisible */
++#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS		(1 << 1)
++/* Flag that un-cached attributes should be used for GTT */
++#define AMDGPU_GEM_CREATE_CPU_GTT_UC		(1 << 2)
++/* Flag that USWC attributes should be used for GTT */
++#define AMDGPU_GEM_CREATE_CPU_GTT_WC		(1 << 3)
++
++/* Flag mask for GTT domain_flags */
++#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
++	(AMDGPU_GEM_CREATE_CPU_GTT_WC | \
++	 AMDGPU_GEM_CREATE_CPU_GTT_UC | \
++	 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
++	 AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
++
++struct drm_amdgpu_gem_create_in  {
++	/** the requested memory size */
++	uint64_t bo_size;
++	/** physical start_addr alignment in bytes for some HW requirements */
++	uint64_t alignment;
++	/** the requested memory domains */
++	uint64_t domains;
++	/** allocation flags */
++	uint64_t domain_flags;
++};
++
++struct drm_amdgpu_gem_create_out  {
++	/** returned GEM object handle */
++	uint32_t handle;
++};
++
++union drm_amdgpu_gem_create {
++	struct drm_amdgpu_gem_create_in		in;
++	struct drm_amdgpu_gem_create_out	out;
++};
++
++/** Opcode to create new residency list.  */
++#define AMDGPU_BO_LIST_OP_CREATE	0
++/** Opcode to destroy previously created residency list */
++#define AMDGPU_BO_LIST_OP_DESTROY	1
++/** Opcode to update resource information in the list */
++#define AMDGPU_BO_LIST_OP_UPDATE	2
++
++struct drm_amdgpu_bo_list_in {
++	/** Type of operation */
++	uint32_t operation;
++	/** Handle of list or 0 if we want to create one */
++	uint32_t list_handle;
++	/** Number of BOs in list  */
++	uint32_t bo_number;
++	/** Size of each element describing BO */
++	uint32_t bo_info_size;
++	/** Pointer to array describing BOs */
++	uint64_t bo_info_ptr;
++};
++
++struct drm_amdgpu_bo_list_entry {
++	/** Handle of BO */
++	uint32_t bo_handle;
++	/** New (if specified) BO priority to be used during migration */
++	uint32_t bo_priority;
++};
++
++struct drm_amdgpu_bo_list_out {
++	/** Handle of resource list  */
++	uint32_t list_handle;
++};
++
++union drm_amdgpu_bo_list {
++	struct drm_amdgpu_bo_list_in in;
++	struct drm_amdgpu_bo_list_out out;
++};
++
++/* context related */
++#define AMDGPU_CTX_OP_ALLOC_CTX	1
++#define AMDGPU_CTX_OP_FREE_CTX	2
++#define AMDGPU_CTX_OP_QUERY_STATE	3
++
++#define AMDGPU_CTX_OP_STATE_RUNNING	1
++
++struct drm_amdgpu_ctx_in {
++	uint32_t	op;
++	uint32_t	flags;
++	uint32_t	ctx_id;
++	uint32_t	pad;
++};
++
++union drm_amdgpu_ctx_out {
++		struct {
++			uint32_t	ctx_id;
++		} alloc;
++
++		struct {
++			uint64_t	flags;
++			uint64_t	hangs;
++		} state;
++};
++
++union drm_amdgpu_ctx {
++	struct drm_amdgpu_ctx_in in;
++	union drm_amdgpu_ctx_out out;
++};
++
++/*
++ * This is not a reliable API and you should expect it to fail for any
++ * number of reasons and have fallback path that do not use userptr to
++ * perform any operation.
++ */
++#define AMDGPU_GEM_USERPTR_READONLY	(1 << 0)
++#define AMDGPU_GEM_USERPTR_ANONONLY	(1 << 1)
++#define AMDGPU_GEM_USERPTR_VALIDATE	(1 << 2)
++#define AMDGPU_GEM_USERPTR_REGISTER	(1 << 3)
++
++struct drm_amdgpu_gem_userptr {
++	uint64_t		addr;
++	uint64_t		size;
++	uint32_t		flags;
++	uint32_t		handle;
++};
++
++#define AMDGPU_TILING_MACRO				0x1
++#define AMDGPU_TILING_MICRO				0x2
++#define AMDGPU_TILING_SWAP_16BIT			0x4
++#define AMDGPU_TILING_R600_NO_SCANOUT			AMDGPU_TILING_SWAP_16BIT
++#define AMDGPU_TILING_SWAP_32BIT			0x8
++/* this object requires a surface when mapped - i.e. front buffer */
++#define AMDGPU_TILING_SURFACE				0x10
++#define AMDGPU_TILING_MICRO_SQUARE			0x20
++#define AMDGPU_TILING_EG_BANKW_SHIFT			8
++#define AMDGPU_TILING_EG_BANKW_MASK			0xf
++#define AMDGPU_TILING_EG_BANKH_SHIFT			12
++#define AMDGPU_TILING_EG_BANKH_MASK			0xf
++#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT	16
++#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK	0xf
++#define AMDGPU_TILING_EG_TILE_SPLIT_SHIFT		24
++#define AMDGPU_TILING_EG_TILE_SPLIT_MASK		0xf
++#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT	28
++#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf
++
++#define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
++#define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
++
++/** The same structure is shared for input/output */
++struct drm_amdgpu_gem_metadata {
++	uint32_t	handle;		/* GEM Object handle */
++	uint32_t	op;		/** Do we want get or set metadata */
++	struct {
++		uint64_t	flags;
++		uint64_t	tiling_info; /* family specific tiling info */
++		uint32_t	data_size_bytes;
++		uint32_t	data[64];
++	} data;
++};
++
++struct drm_amdgpu_gem_mmap_in {
++	uint32_t handle;		/** the GEM object handle */
++};
++
++struct drm_amdgpu_gem_mmap_out {
++	uint64_t addr_ptr;	/** mmap offset from the vma offset manager */
++};
++
++union drm_amdgpu_gem_mmap {
++	struct drm_amdgpu_gem_mmap_in   in;
++	struct drm_amdgpu_gem_mmap_out out;
++};
++
++struct drm_amdgpu_gem_wait_idle_in {
++	uint32_t handle;   	/* GEM object handle */
++	uint32_t flags;
++	uint64_t timeout; 	/* Timeout to wait. If 0 then returned immediately with the status */
++};
++
++struct drm_amdgpu_gem_wait_idle_out {
++	uint32_t status;	/*   BO status:  0 - BO is idle, 1 - BO is busy */
++	uint32_t domain; /*  Returned current memory domain */
++};
++
++union drm_amdgpu_gem_wait_idle {
++	struct drm_amdgpu_gem_wait_idle_in  in;
++	struct drm_amdgpu_gem_wait_idle_out out;
++};
++
++struct drm_amdgpu_wait_cs_in {
++	uint64_t handle;
++	uint64_t timeout;
++	uint32_t ip_type;
++	uint32_t ip_instance;
++	uint32_t ring;
++};
++
++struct drm_amdgpu_wait_cs_out {
++	uint64_t status;
++};
++
++union drm_amdgpu_wait_cs {
++	struct drm_amdgpu_wait_cs_in in;
++	struct drm_amdgpu_wait_cs_out out;
++};
++
++/* Sets or returns a value associated with a buffer. */
++struct drm_amdgpu_gem_op {
++	uint32_t	handle; /* buffer */
++	uint32_t	op;     /* AMDGPU_GEM_OP_* */
++	uint64_t	value;  /* input or return value */
++};
++
++#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO		0
++#define AMDGPU_GEM_OP_SET_INITIAL_DOMAIN	1
++
++#define AMDGPU_VA_OP_MAP			1
++#define AMDGPU_VA_OP_UNMAP			2
++
++#define AMDGPU_VA_RESULT_OK			0
++#define AMDGPU_VA_RESULT_ERROR			1
++#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT	2
++
++/* Mapping flags */
++/* readable mapping */
++#define AMDGPU_VM_PAGE_READABLE		(1 << 1)
++/* writable mapping */
++#define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
++/* executable mapping, new for VI */
++#define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
++
++struct drm_amdgpu_gem_va_in {
++	/* GEM object handle */
++	uint32_t handle;
++	uint32_t pad;
++	/* map or unmap*/
++	uint32_t operation;
++	/* specify mapping flags */
++	uint32_t flags;
++	/* va address to assign . Must be correctly aligned.*/
++	uint64_t va_address;
++	/* Specify offset inside of BO to assign. Must be correctly aligned.*/
++	uint64_t offset_in_bo;
++	/* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
++	/* Must be correctly aligned. */
++	uint64_t map_size;
++};
++
++struct drm_amdgpu_gem_va_out {
++	uint32_t result;
++};
++
++union drm_amdgpu_gem_va {
++	struct drm_amdgpu_gem_va_in  in;
++	struct drm_amdgpu_gem_va_out out;
++};
++
++#define AMDGPU_HW_IP_GFX          0
++#define AMDGPU_HW_IP_COMPUTE      1
++#define AMDGPU_HW_IP_DMA          2
++#define AMDGPU_HW_IP_UVD          3
++#define AMDGPU_HW_IP_VCE          4
++#define AMDGPU_HW_IP_NUM          5
++
++#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
++
++#define AMDGPU_CHUNK_ID_IB		0x01
++#define AMDGPU_CHUNK_ID_FENCE		0x02
++struct drm_amdgpu_cs_chunk {
++	uint32_t		chunk_id;
++	uint32_t		length_dw;
++	uint64_t		chunk_data;
++};
++
++struct drm_amdgpu_cs_in {
++	/** Rendering context id */
++	uint32_t		ctx_id;
++	/**  Handle of resource list associated with CS */
++	uint32_t		bo_list_handle;
++	uint32_t		num_chunks;
++	uint32_t		pad;
++	/* this points to uint64_t * which point to cs chunks */
++	uint64_t		chunks;
++};
++
++struct drm_amdgpu_cs_out {
++	uint64_t handle;
++};
++
++union drm_amdgpu_cs {
++       struct drm_amdgpu_cs_in in;
++       struct drm_amdgpu_cs_out out;
++};
++
++/* Specify flags to be used for IB */
++
++/* This IB should be submitted to CE */
++#define AMDGPU_IB_FLAG_CE	(1<<0)
++
++/* GDS is used by this IB */
++#define AMDGPU_IB_FLAG_GDS	(1<<1)
++
++struct drm_amdgpu_cs_chunk_ib {
++	/**
++	 * Handle of GEM object to be used as IB or 0 if it is already in
++	 * residency list.
++	 */
++	uint32_t handle;
++	uint32_t flags;		/* IB Flags */
++	uint64_t va_start;	/* Virtual address to begin IB execution */
++	uint32_t ib_bytes;	/* Size of submission */
++	uint32_t ip_type;	/* HW IP to submit to */
++	uint32_t ip_instance;	/* HW IP index of the same type to submit to  */
++	uint32_t ring;		/* Ring index to submit to */
++};
++
++struct drm_amdgpu_cs_chunk_fence {
++	uint32_t handle;
++	uint32_t offset;
++};
++
++struct drm_amdgpu_cs_chunk_data {
++	union {
++		struct drm_amdgpu_cs_chunk_ib		ib_data;
++		struct drm_amdgpu_cs_chunk_fence	fence_data;
++	};
++};
++
++/**
++ *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
++ *
++ */
++#define AMDGPU_IDS_FLAGS_FUSION         0x1
++
++/* indicate if acceleration can be working */
++#define AMDGPU_INFO_ACCEL_WORKING		0x00
++/* get the crtc_id from the mode object id? */
++#define AMDGPU_INFO_CRTC_FROM_ID		0x01
++/* query hw IP info */
++#define AMDGPU_INFO_HW_IP_INFO			0x02
++/* query hw IP instance count for the specified type */
++#define AMDGPU_INFO_HW_IP_COUNT			0x03
++/* timestamp for GL_ARB_timer_query */
++#define AMDGPU_INFO_TIMESTAMP			0x05
++/* Query the firmware version */
++#define AMDGPU_INFO_FW_VERSION			0x0e
++	/* Subquery id: Query VCE firmware version */
++	#define AMDGPU_INFO_FW_VCE		0x1
++	/* Subquery id: Query UVD firmware version */
++	#define AMDGPU_INFO_FW_UVD		0x2
++	/* Subquery id: Query GMC firmware version */
++	#define AMDGPU_INFO_FW_GMC		0x03
++	/* Subquery id: Query GFX ME firmware version */
++	#define AMDGPU_INFO_FW_GFX_ME		0x04
++	/* Subquery id: Query GFX PFP firmware version */
++	#define AMDGPU_INFO_FW_GFX_PFP		0x05
++	/* Subquery id: Query GFX CE firmware version */
++	#define AMDGPU_INFO_FW_GFX_CE		0x06
++	/* Subquery id: Query GFX RLC firmware version */
++	#define AMDGPU_INFO_FW_GFX_RLC		0x07
++	/* Subquery id: Query GFX MEC firmware version */
++	#define AMDGPU_INFO_FW_GFX_MEC		0x08
++	/* Subquery id: Query SMC firmware version */
++	#define AMDGPU_INFO_FW_SMC		0x0a
++	/* Subquery id: Query SDMA firmware version */
++	#define AMDGPU_INFO_FW_SDMA		0x0b
++/* number of bytes moved for TTM migration */
++#define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
++/* the used VRAM size */
++#define AMDGPU_INFO_VRAM_USAGE			0x10
++/* the used GTT size */
++#define AMDGPU_INFO_GTT_USAGE			0x11
++/* Information about GDS, etc. resource configuration */
++#define AMDGPU_INFO_GDS_CONFIG			0x13
++/* Query information about VRAM and GTT domains */
++#define AMDGPU_INFO_VRAM_GTT			0x14
++/* Query information about register in MMR address space*/
++#define AMDGPU_INFO_READ_MMR_REG		0x15
++/* Query information about device: rev id, family, etc. */
++#define AMDGPU_INFO_DEV_INFO			0x16
++/* visible vram usage */
++#define AMDGPU_INFO_VIS_VRAM_USAGE		0x17
++
++#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
++#define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
++#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
++#define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
++
++/* Input structure for the INFO ioctl */
++struct drm_amdgpu_info {
++	/* Where the return value will be stored */
++	uint64_t return_pointer;
++	/* The size of the return value. Just like "size" in "snprintf",
++	 * it limits how many bytes the kernel can write. */
++	uint32_t return_size;
++	/* The query request id. */
++	uint32_t query;
++
++	union {
++		struct {
++			uint32_t id;
++		} mode_crtc;
++
++		struct {
++			/** AMDGPU_HW_IP_* */
++			uint32_t type;
++			/**
++			 * Index of the IP if there are more IPs of the same type.
++			 * Ignored by AMDGPU_INFO_HW_IP_COUNT.
++			 */
++			uint32_t ip_instance;
++		} query_hw_ip;
++
++		struct {
++			uint32_t dword_offset;
++			uint32_t count; /* number of registers to read */
++			uint32_t instance;
++			uint32_t flags;
++		} read_mmr_reg;
++
++		struct {
++			/** AMDGPU_INFO_FW_* */
++			uint32_t fw_type;
++			/** Index of the IP if there are more IPs of the same type. */
++			uint32_t ip_instance;
++			/**
++			 * Index of the engine. Whether this is used depends
++			 * on the firmware type. (e.g. MEC, SDMA)
++			 */
++			uint32_t index;
++		} query_fw;
++	};
++};
++
++struct drm_amdgpu_info_gds {
++	/** GDS GFX partition size */
++	uint32_t gds_gfx_partition_size;
++	/** GDS compute partition size */
++	uint32_t compute_partition_size;
++	/** total GDS memory size */
++	uint32_t gds_total_size;
++	/** GWS size per GFX partition */
++	uint32_t gws_per_gfx_partition;
++	/** GSW size per compute partition */
++	uint32_t gws_per_compute_partition;
++	/** OA size per GFX partition */
++	uint32_t oa_per_gfx_partition;
++	/** OA size per compute partition */
++	uint32_t oa_per_compute_partition;
++};
++
++struct drm_amdgpu_info_vram_gtt {
++	uint64_t vram_size;
++	uint64_t vram_cpu_accessible_size;
++	uint64_t gtt_size;
++};
++
++struct drm_amdgpu_info_firmware {
++	uint32_t ver;
++	uint32_t feature;
++};
++
++struct drm_amdgpu_info_device {
++	/** PCI Device ID */
++	uint32_t device_id;
++	/** Internal chip revision: A0, A1, etc.) */
++	uint32_t chip_rev;
++	uint32_t external_rev;
++	/** Revision id in PCI Config space */
++	uint32_t pci_rev;
++	uint32_t family;
++	uint32_t num_shader_engines;
++	uint32_t num_shader_arrays_per_engine;
++	uint32_t gpu_counter_freq; /* in KHz */
++	uint64_t max_engine_clock; /* in KHz */
++	/* cu information */
++	uint32_t cu_active_number;
++	uint32_t cu_ao_mask;
++	uint32_t cu_bitmap[4][4];
++	/** Render backend pipe mask. One render backend is CB+DB. */
++	uint32_t enabled_rb_pipes_mask;
++	uint32_t num_rb_pipes;
++	uint32_t num_hw_gfx_contexts;
++	uint32_t _pad;
++	uint64_t ids_flags;
++	/** Starting virtual address for UMDs. */
++	uint64_t virtual_address_offset;
++	/** Required alignment of virtual addresses. */
++	uint32_t virtual_address_alignment;
++	/** Page table entry - fragment size */
++	uint32_t pte_fragment_size;
++	uint32_t gart_page_size;
++};
++
++struct drm_amdgpu_info_hw_ip {
++	/** Version of h/w IP */
++	uint32_t  hw_ip_version_major;
++	uint32_t  hw_ip_version_minor;
++	/** Capabilities */
++	uint64_t  capabilities_flags;
++	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
++	uint32_t  available_rings;
++};
++
++/* Those correspond to the tile index to use, this is to explicitly state
++ * the API that is implicitly defined by the tile mode array.
++ */
++#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED	8
++#define SI_TILE_MODE_COLOR_1D			13
++#define SI_TILE_MODE_COLOR_1D_SCANOUT		9
++#define SI_TILE_MODE_COLOR_2D_8BPP		14
++#define SI_TILE_MODE_COLOR_2D_16BPP		15
++#define SI_TILE_MODE_COLOR_2D_32BPP		16
++#define SI_TILE_MODE_COLOR_2D_64BPP		17
++#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP	11
++#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP	12
++#define SI_TILE_MODE_DEPTH_STENCIL_1D		4
++#define SI_TILE_MODE_DEPTH_STENCIL_2D		0
++#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA	3
++#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3
++#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2
++
++#define CIK_TILE_MODE_DEPTH_STENCIL_1D		5
++
++/*
++ * Supported GPU families
++ */
++#define AMDGPU_FAMILY_UNKNOWN			0
++#define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
++#define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
++#define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
++#define AMDGPU_FAMILY_CZ			135 /* Carrizo */
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0030-yocto-amd-drm-amdgpu-add-GMC-8-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0030-yocto-amd-drm-amdgpu-add-GMC-8-1-register-headers.patch
new file mode 100644
index 00000000..3b59048e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0030-yocto-amd-drm-amdgpu-add-GMC-8-1-register-headers.patch
@@ -0,0 +1,10025 @@
+From 520f92aabfe8d85f0fd3d8127956868eb693bc7b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:44:53 -0400
+Subject: drm/amdgpu: add atombios headers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These headers define the atombios table structure and
+driver interface.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/ObjectID.h b/drivers/gpu/drm/amd/amdgpu/ObjectID.h
+new file mode 100644
+index 0000000..0619269
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/ObjectID.h
+@@ -0,0 +1,736 @@
++/*
++* Copyright 2006-2007 Advanced Micro Devices, Inc.  
++*
++* Permission is hereby granted, free of charge, to any person obtaining a
++* copy of this software and associated documentation files (the "Software"),
++* to deal in the Software without restriction, including without limitation
++* the rights to use, copy, modify, merge, publish, distribute, sublicense,
++* and/or sell copies of the Software, and to permit persons to whom the
++* Software is furnished to do so, subject to the following conditions:
++*
++* The above copyright notice and this permission notice shall be included in
++* all copies or substantial portions of the Software.
++*
++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++* OTHER DEALINGS IN THE SOFTWARE.
++*/
++/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
++
++#ifndef _OBJECTID_H
++#define _OBJECTID_H
++
++#if defined(_X86_)
++#pragma pack(1)
++#endif
++
++/****************************************************/
++/* Graphics Object Type Definition                  */
++/****************************************************/
++#define GRAPH_OBJECT_TYPE_NONE                    0x0
++#define GRAPH_OBJECT_TYPE_GPU                     0x1
++#define GRAPH_OBJECT_TYPE_ENCODER                 0x2
++#define GRAPH_OBJECT_TYPE_CONNECTOR               0x3
++#define GRAPH_OBJECT_TYPE_ROUTER                  0x4
++/* deleted */
++#define GRAPH_OBJECT_TYPE_DISPLAY_PATH            0x6  
++#define GRAPH_OBJECT_TYPE_GENERIC                 0x7
++
++/****************************************************/
++/* Encoder Object ID Definition                     */
++/****************************************************/
++#define ENCODER_OBJECT_ID_NONE                    0x00 
++
++/* Radeon Class Display Hardware */
++#define ENCODER_OBJECT_ID_INTERNAL_LVDS           0x01
++#define ENCODER_OBJECT_ID_INTERNAL_TMDS1          0x02
++#define ENCODER_OBJECT_ID_INTERNAL_TMDS2          0x03
++#define ENCODER_OBJECT_ID_INTERNAL_DAC1           0x04
++#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05     /* TV/CV DAC */
++#define ENCODER_OBJECT_ID_INTERNAL_SDVOA          0x06
++#define ENCODER_OBJECT_ID_INTERNAL_SDVOB          0x07
++
++/* External Third Party Encoders */
++#define ENCODER_OBJECT_ID_SI170B                  0x08
++#define ENCODER_OBJECT_ID_CH7303                  0x09
++#define ENCODER_OBJECT_ID_CH7301                  0x0A
++#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B    /* This belongs to Radeon Class Display Hardware */
++#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA          0x0C
++#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB          0x0D
++#define ENCODER_OBJECT_ID_TITFP513                0x0E
++#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F    /* not used for Radeon */
++#define ENCODER_OBJECT_ID_VT1623                  0x10
++#define ENCODER_OBJECT_ID_HDMI_SI1930             0x11
++#define ENCODER_OBJECT_ID_HDMI_INTERNAL           0x12
++#define ENCODER_OBJECT_ID_ALMOND                  0x22
++#define ENCODER_OBJECT_ID_TRAVIS                  0x23
++#define ENCODER_OBJECT_ID_NUTMEG                  0x22
++#define ENCODER_OBJECT_ID_HDMI_ANX9805            0x26
++
++/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13
++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1    0x15
++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
++#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
++#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
++#define ENCODER_OBJECT_ID_INTERNAL_DDI            0x19
++#define ENCODER_OBJECT_ID_VT1625                  0x1A
++#define ENCODER_OBJECT_ID_HDMI_SI1932             0x1B
++#define ENCODER_OBJECT_ID_DP_AN9801               0x1C
++#define ENCODER_OBJECT_ID_DP_DP501                0x1D
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY         0x1E
++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA   0x1F
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1        0x20
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2        0x21
++#define ENCODER_OBJECT_ID_INTERNAL_VCE            0x24
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY3        0x25
++#define ENCODER_OBJECT_ID_INTERNAL_AMCLK          0x27
++
++#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO    0xFF
++
++/****************************************************/
++/* Connector Object ID Definition                   */
++/****************************************************/
++#define CONNECTOR_OBJECT_ID_NONE                  0x00 
++#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I     0x01
++#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I       0x02
++#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D     0x03
++#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D       0x04
++#define CONNECTOR_OBJECT_ID_VGA                   0x05
++#define CONNECTOR_OBJECT_ID_COMPOSITE             0x06
++#define CONNECTOR_OBJECT_ID_SVIDEO                0x07
++#define CONNECTOR_OBJECT_ID_YPbPr                 0x08
++#define CONNECTOR_OBJECT_ID_D_CONNECTOR           0x09
++#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
++#define CONNECTOR_OBJECT_ID_SCART                 0x0B
++#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A           0x0C
++#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B           0x0D
++#define CONNECTOR_OBJECT_ID_LVDS                  0x0E
++#define CONNECTOR_OBJECT_ID_7PIN_DIN              0x0F
++#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR        0x10
++#define CONNECTOR_OBJECT_ID_CROSSFIRE             0x11
++#define CONNECTOR_OBJECT_ID_HARDCODE_DVI          0x12
++#define CONNECTOR_OBJECT_ID_DISPLAYPORT           0x13
++#define CONNECTOR_OBJECT_ID_eDP                   0x14
++#define CONNECTOR_OBJECT_ID_MXM                   0x15
++#define CONNECTOR_OBJECT_ID_LVDS_eDP              0x16
++
++/* deleted */
++
++/****************************************************/
++/* Router Object ID Definition                      */
++/****************************************************/
++#define ROUTER_OBJECT_ID_NONE											0x00
++#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL				0x01
++
++/****************************************************/
++/* Generic Object ID Definition                     */
++/****************************************************/
++#define GENERIC_OBJECT_ID_NONE                    0x00
++#define GENERIC_OBJECT_ID_GLSYNC                  0x01
++#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE        0x02
++#define GENERIC_OBJECT_ID_MXM_OPM                 0x03
++#define GENERIC_OBJECT_ID_STEREO_PIN              0x04        //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin
++
++/****************************************************/
++/* Graphics Object ENUM ID Definition               */
++/****************************************************/
++#define GRAPH_OBJECT_ENUM_ID1                     0x01
++#define GRAPH_OBJECT_ENUM_ID2                     0x02
++#define GRAPH_OBJECT_ENUM_ID3                     0x03
++#define GRAPH_OBJECT_ENUM_ID4                     0x04
++#define GRAPH_OBJECT_ENUM_ID5                     0x05
++#define GRAPH_OBJECT_ENUM_ID6                     0x06
++#define GRAPH_OBJECT_ENUM_ID7                     0x07
++
++/****************************************************/
++/* Graphics Object ID Bit definition                */
++/****************************************************/
++#define OBJECT_ID_MASK                            0x00FF
++#define ENUM_ID_MASK                              0x0700
++#define RESERVED1_ID_MASK                         0x0800
++#define OBJECT_TYPE_MASK                          0x7000
++#define RESERVED2_ID_MASK                         0x8000
++                                                  
++#define OBJECT_ID_SHIFT                           0x00
++#define ENUM_ID_SHIFT                             0x08
++#define OBJECT_TYPE_SHIFT                         0x0C
++
++
++/****************************************************/
++/* Graphics Object family definition                */
++/****************************************************/
++#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
++                                                                           GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
++/****************************************************/
++/* GPU Object ID definition - Shared with BIOS      */
++/****************************************************/
++#define GPU_ENUM_ID1                            ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
++
++/****************************************************/
++/* Encoder Object ID definition - Shared with BIOS  */
++/****************************************************/
++/*
++#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101      
++#define ENCODER_INTERNAL_TMDS1_ENUM_ID1       0x2102
++#define ENCODER_INTERNAL_TMDS2_ENUM_ID1       0x2103
++#define ENCODER_INTERNAL_DAC1_ENUM_ID1        0x2104
++#define ENCODER_INTERNAL_DAC2_ENUM_ID1        0x2105
++#define ENCODER_INTERNAL_SDVOA_ENUM_ID1       0x2106
++#define ENCODER_INTERNAL_SDVOB_ENUM_ID1       0x2107
++#define ENCODER_SIL170B_ENUM_ID1              0x2108  
++#define ENCODER_CH7303_ENUM_ID1               0x2109
++#define ENCODER_CH7301_ENUM_ID1               0x210A
++#define ENCODER_INTERNAL_DVO1_ENUM_ID1        0x210B
++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1       0x210C
++#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1       0x210D
++#define ENCODER_TITFP513_ENUM_ID1             0x210E
++#define ENCODER_INTERNAL_LVTM1_ENUM_ID1       0x210F
++#define ENCODER_VT1623_ENUM_ID1               0x2110
++#define ENCODER_HDMI_SI1930_ENUM_ID1          0x2111
++#define ENCODER_HDMI_INTERNAL_ENUM_ID1        0x2112
++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   0x2113
++#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    0x2114
++#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    0x2115
++#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116  
++#define ENCODER_SI178_ENUM_ID1                   0x2117 
++#define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
++#define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
++#define ENCODER_VT1625_ENUM_ID1                  0x211A
++#define ENCODER_HDMI_SI1932_ENUM_ID1             0x211B
++#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1       0x211C
++#define ENCODER_DP_DP501_ENUM_ID1                0x211D
++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         0x211E
++*/
++#define ENCODER_INTERNAL_LVDS_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_TMDS1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_TMDS2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_DAC1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_DAC2_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
++
++#define ENCODER_SIL170B_ENUM_ID1           ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
++
++#define ENCODER_CH7303_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
++
++#define ENCODER_CH7301_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_DVO1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
++
++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
++
++
++#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
++
++
++#define ENCODER_TITFP513_ENUM_ID1          ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_LVTM1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_VT1623_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
++
++#define ENCODER_HDMI_SI1930_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
++
++#define ENCODER_HDMI_INTERNAL_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
++
++
++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
++
++
++#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT)  // Shared with CV/TV and CRT
++
++#define ENCODER_SI178_ENUM_ID1                    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)  
++
++#define ENCODER_MVPU_FPGA_ENUM_ID1                ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                   ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_DDI_ENUM_ID1     (  GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) 
++
++#define ENCODER_VT1625_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
++
++#define ENCODER_HDMI_SI1932_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
++
++#define ENCODER_DP_DP501_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
++
++#define ENCODER_DP_AN9801_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                             ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)  
++
++#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT)
++
++#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
++
++#define ENCODER_ALMOND_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
++
++#define ENCODER_ALMOND_ENUM_ID2                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
++
++#define ENCODER_TRAVIS_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
++
++#define ENCODER_TRAVIS_ENUM_ID2                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
++
++#define ENCODER_NUTMEG_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT)
++
++#define ENCODER_VCE_ENUM_ID1                     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT)
++
++#define ENCODER_HDMI_ANX9805_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_HDMI_ANX9805 << OBJECT_ID_SHIFT)
++
++/****************************************************/
++/* Connector Object ID definition - Shared with BIOS */
++/****************************************************/
++/*
++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1        0x3101
++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1          0x3102
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1        0x3103
++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1          0x3104
++#define CONNECTOR_VGA_ENUM_ID1                      0x3105
++#define CONNECTOR_COMPOSITE_ENUM_ID1                0x3106
++#define CONNECTOR_SVIDEO_ENUM_ID1                   0x3107
++#define CONNECTOR_YPbPr_ENUM_ID1                    0x3108
++#define CONNECTOR_D_CONNECTORE_ENUM_ID1             0x3109
++#define CONNECTOR_9PIN_DIN_ENUM_ID1                 0x310A
++#define CONNECTOR_SCART_ENUM_ID1                    0x310B
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1              0x310C
++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1              0x310D
++#define CONNECTOR_LVDS_ENUM_ID1                     0x310E
++#define CONNECTOR_7PIN_DIN_ENUM_ID1                 0x310F
++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1           0x3110
++*/
++#define CONNECTOR_LVDS_ENUM_ID1                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_LVDS_ENUM_ID2                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_eDP_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_eDP_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID5   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID6   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID4     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_VGA_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_VGA_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_COMPOSITE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_COMPOSITE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SVIDEO_ENUM_ID1              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SVIDEO_ENUM_ID2              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_YPbPr_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_YPbPr_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_D_CONNECTOR_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_D_CONNECTOR_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_9PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_9PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SCART_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_SCART_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID5         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID6         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_7PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_7PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_CROSSFIRE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_CROSSFIRE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
++
++
++#define CONNECTOR_HARDCODE_DVI_ENUM_ID1        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_HARDCODE_DVI_ENUM_ID2        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID5         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID6         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_MXM_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_A
++
++#define CONNECTOR_MXM_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_B
++
++#define CONNECTOR_MXM_ENUM_ID3                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_C
++
++#define CONNECTOR_MXM_ENUM_ID4                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_D
++
++#define CONNECTOR_MXM_ENUM_ID5                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_TXxx
++
++#define CONNECTOR_MXM_ENUM_ID6                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_UXxx
++
++#define CONNECTOR_MXM_ENUM_ID7                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DAC
++
++#define CONNECTOR_LVDS_eDP_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_LVDS_eDP_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
++
++/****************************************************/
++/* Router Object ID definition - Shared with BIOS   */
++/****************************************************/
++#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1      ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
++                                                GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
++
++/* deleted */
++
++/****************************************************/
++/* Generic Object ID definition - Shared with BIOS  */
++/****************************************************/
++#define GENERICOBJECT_GLSYNC_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
++
++#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
++
++#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
++
++#define GENERICOBJECT_MXM_OPM_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
++
++#define GENERICOBJECT_STEREO_PIN_ENUM_ID1        (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT)
++
++/****************************************************/
++/* Object Cap definition - Shared with BIOS         */
++/****************************************************/
++#define GRAPHICS_OBJECT_CAP_I2C                 0x00000001L
++#define GRAPHICS_OBJECT_CAP_TABLE_ID            0x00000002L
++
++
++#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID                   0x01
++#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID     0x02
++#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID    0x03
++
++#if defined(_X86_)
++#pragma pack()
++#endif
++
++#endif  /*GRAPHICTYPE */
++
++
++
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios.h b/drivers/gpu/drm/amd/amdgpu/atombios.h
+new file mode 100644
+index 0000000..44c5d4a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios.h
+@@ -0,0 +1,8555 @@
++/*
++ * Copyright 2006-2007 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++
++/****************************************************************************/
++/*Portion I: Definitions  shared between VBIOS and Driver                   */
++/****************************************************************************/
++
++#ifndef _ATOMBIOS_H
++#define _ATOMBIOS_H
++
++#define ATOM_VERSION_MAJOR                   0x00020000
++#define ATOM_VERSION_MINOR                   0x00000002
++
++#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
++
++/* Endianness should be specified before inclusion,
++ * default to little endian
++ */
++#ifndef ATOM_BIG_ENDIAN
++#error Endian not specified
++#endif
++
++#ifdef _H2INC
++  #ifndef ULONG
++    typedef unsigned long ULONG;
++  #endif
++
++  #ifndef UCHAR
++    typedef unsigned char UCHAR;
++  #endif
++
++  #ifndef USHORT
++    typedef unsigned short USHORT;
++  #endif
++#endif
++
++#define ATOM_DAC_A            0
++#define ATOM_DAC_B            1
++#define ATOM_EXT_DAC          2
++
++#define ATOM_CRTC1            0
++#define ATOM_CRTC2            1
++#define ATOM_CRTC3            2
++#define ATOM_CRTC4            3
++#define ATOM_CRTC5            4
++#define ATOM_CRTC6            5
++
++#define ATOM_UNDERLAY_PIPE0   16
++#define ATOM_UNDERLAY_PIPE1   17
++
++#define ATOM_CRTC_INVALID     0xFF
++
++#define ATOM_DIGA             0
++#define ATOM_DIGB             1
++
++#define ATOM_PPLL1            0
++#define ATOM_PPLL2            1
++#define ATOM_DCPLL            2
++#define ATOM_PPLL0            2
++#define ATOM_PPLL3            3
++
++#define ATOM_EXT_PLL1         8
++#define ATOM_EXT_PLL2         9
++#define ATOM_EXT_CLOCK        10
++#define ATOM_PPLL_INVALID     0xFF
++
++#define ENCODER_REFCLK_SRC_P1PLL       0
++#define ENCODER_REFCLK_SRC_P2PLL       1
++#define ENCODER_REFCLK_SRC_DCPLL       2
++#define ENCODER_REFCLK_SRC_EXTCLK      3
++#define ENCODER_REFCLK_SRC_INVALID     0xFF
++
++#define ATOM_SCALER_DISABLE   0   //For Fudo, it's bypass and auto-cengter & no replication
++#define ATOM_SCALER_CENTER    1   //For Fudo, it's bypass and auto-center & auto replication
++#define ATOM_SCALER_EXPANSION 2   //For Fudo, it's 2 Tap alpha blending mode
++#define ATOM_SCALER_MULTI_EX  3   //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios
++
++#define ATOM_DISABLE          0
++#define ATOM_ENABLE           1
++#define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
++#define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
++#define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
++#define ATOM_LCD_SELFTEST_START                 (ATOM_DISABLE+5)
++#define ATOM_LCD_SELFTEST_STOP                  (ATOM_ENABLE+5)
++#define ATOM_ENCODER_INIT                       (ATOM_DISABLE+7)
++#define ATOM_INIT                               (ATOM_DISABLE+7)
++#define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
++
++#define ATOM_BLANKING         1
++#define ATOM_BLANKING_OFF     0
++
++
++#define ATOM_CRT1             0
++#define ATOM_CRT2             1
++
++#define ATOM_TV_NTSC          1
++#define ATOM_TV_NTSCJ         2
++#define ATOM_TV_PAL           3
++#define ATOM_TV_PALM          4
++#define ATOM_TV_PALCN         5
++#define ATOM_TV_PALN          6
++#define ATOM_TV_PAL60         7
++#define ATOM_TV_SECAM         8
++#define ATOM_TV_CV            16
++
++#define ATOM_DAC1_PS2         1
++#define ATOM_DAC1_CV          2
++#define ATOM_DAC1_NTSC        3
++#define ATOM_DAC1_PAL         4
++
++#define ATOM_DAC2_PS2         ATOM_DAC1_PS2
++#define ATOM_DAC2_CV          ATOM_DAC1_CV
++#define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
++#define ATOM_DAC2_PAL         ATOM_DAC1_PAL
++
++#define ATOM_PM_ON            0
++#define ATOM_PM_STANDBY       1
++#define ATOM_PM_SUSPEND       2
++#define ATOM_PM_OFF           3
++
++// For ATOM_LVDS_INFO_V12
++// Bit0:{=0:single, =1:dual},
++// Bit1 {=0:666RGB, =1:888RGB},
++// Bit2:3:{Grey level}
++// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
++#define ATOM_PANEL_MISC_DUAL               0x00000001
++#define ATOM_PANEL_MISC_888RGB             0x00000002
++#define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
++#define ATOM_PANEL_MISC_FPDI               0x00000010
++#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
++#define ATOM_PANEL_MISC_SPATIAL            0x00000020
++#define ATOM_PANEL_MISC_TEMPORAL           0x00000040
++#define ATOM_PANEL_MISC_API_ENABLED        0x00000080
++
++#define MEMTYPE_DDR1                       "DDR1"
++#define MEMTYPE_DDR2                       "DDR2"
++#define MEMTYPE_DDR3                       "DDR3"
++#define MEMTYPE_DDR4                       "DDR4"
++
++#define ASIC_BUS_TYPE_PCI                  "PCI"
++#define ASIC_BUS_TYPE_AGP                  "AGP"
++#define ASIC_BUS_TYPE_PCIE                 "PCI_EXPRESS"
++
++//Maximum size of that FireGL flag string
++#define ATOM_FIREGL_FLAG_STRING            "FGL"      //Flag used to enable FireGL Support
++#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING     3     //sizeof( ATOM_FIREGL_FLAG_STRING )
++
++#define ATOM_FAKE_DESKTOP_STRING           "DSK"      //Flag used to enable mobile ASIC on Desktop
++#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING    ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
++
++#define ATOM_M54T_FLAG_STRING              "M54T"     //Flag used to enable M54T Support
++#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING  4          //sizeof( ATOM_M54T_FLAG_STRING )
++
++#define HW_ASSISTED_I2C_STATUS_FAILURE     2
++#define HW_ASSISTED_I2C_STATUS_SUCCESS     1
++
++#pragma pack(1)                                       // BIOS data must use byte aligment
++
++// Define offset to location of ROM header.
++#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER         0x00000048L
++#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                0x00000002L
++
++#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE         0x94
++#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE        20    //including the terminator 0x0!
++#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER      0x002f
++#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START       0x006e
++
++/****************************************************************************/
++// Common header for all tables (Data table, Command table).
++// Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
++// And the pointer actually points to this header.
++/****************************************************************************/
++
++typedef struct _ATOM_COMMON_TABLE_HEADER
++{
++  USHORT usStructureSize;
++  UCHAR  ucTableFormatRevision;   //Change it when the Parser is not backward compatible
++  UCHAR  ucTableContentRevision;  //Change it only when the table needs to change but the firmware
++                                  //Image can't be updated, while Driver needs to carry the new table!
++}ATOM_COMMON_TABLE_HEADER;
++
++/****************************************************************************/
++// Structure stores the ROM header.
++/****************************************************************************/
++typedef struct _ATOM_ROM_HEADER
++{
++  ATOM_COMMON_TABLE_HEADER      sHeader;
++  UCHAR  uaFirmWareSignature[4];    //Signature to distinguish between Atombios and non-atombios,
++                                    //atombios should init it as "ATOM", don't change the position
++  USHORT usBiosRuntimeSegmentAddress;
++  USHORT usProtectedModeInfoOffset;
++  USHORT usConfigFilenameOffset;
++  USHORT usCRC_BlockOffset;
++  USHORT usBIOS_BootupMessageOffset;
++  USHORT usInt10Offset;
++  USHORT usPciBusDevInitCode;
++  USHORT usIoBaseAddress;
++  USHORT usSubsystemVendorID;
++  USHORT usSubsystemID;
++  USHORT usPCI_InfoOffset;
++  USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
++  USHORT usMasterDataTableOffset;   //Offest for SW to get all data table offsets, Don't change the position
++  UCHAR  ucExtendedFunctionCode;
++  UCHAR  ucReserved;
++}ATOM_ROM_HEADER;
++
++//==============================Command Table Portion====================================
++
++
++/****************************************************************************/
++// Structures used in Command.mtb
++/****************************************************************************/
++typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
++  USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
++  USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
++  USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
++  USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
++  USHORT DIGxEncoderControl;                     //Only used by Bios
++  USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
++  USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
++  USHORT MemoryParamAdjust;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
++  USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
++  USHORT GPIOPinControl;                         //Atomic Table,  only used by Bios
++  USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
++  USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
++  USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2
++  USHORT EnableDispPowerGating;                  //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
++  USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
++  USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
++  USHORT MemoryPLLInit;                          //Atomic Table,  used only by Bios
++  USHORT AdjustDisplayPll;                       //Atomic Table,  used by various SW componentes.
++  USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
++  USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
++  USHORT SetUniphyInstance;                      //Atomic Table,  only used by Bios
++  USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2
++  USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
++  USHORT HW_Misc_Operation;                      //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
++  USHORT GetConditionalGoldenSetting;            //Only used by Bios
++  USHORT SMC_Init;                               //Function Table,directly used by various SW components,latest version 1.1
++  USHORT PatchMCSetting;                         //only used by BIOS
++  USHORT MC_SEQ_Control;                         //only used by BIOS
++  USHORT Gfx_Harvesting;                         //Atomic Table,  Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
++  USHORT EnableScaler;                           //Atomic Table,  used only by Bios
++  USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
++  USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
++  USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
++  USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
++  USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
++  USHORT UpdateCRTC_DoubleBufferRegisters;       //Atomic Table,  used only by Bios
++  USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
++  USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
++  USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
++  USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
++  USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios
++  USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
++  USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components
++  USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
++  USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
++  USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
++  USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
++  USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
++  USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
++  USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
++  USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
++  USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
++  USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
++  USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT ReadEfuseValue;                         //Atomic Table,  directly used by various SW components,latest version 1.1
++  USHORT ComputeMemoryClockParam;                //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
++  USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
++  USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
++  USHORT GetDispObjectInfo;                      //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
++  USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
++  USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
++  USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
++  USHORT DIG2TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
++  USHORT ProcessAuxChannelTransaction;           //Function Table,only used by Bios
++  USHORT DPEncoderService;                       //Function Table,only used by Bios
++  USHORT GetVoltageInfo;                         //Function Table,only used by Bios since SI
++}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
++
++// For backward compatible
++#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
++#define DPTranslatorControl                      DIG2EncoderControl
++#define UNIPHYTransmitterControl                 DIG1TransmitterControl
++#define LVTMATransmitterControl                  DIG2TransmitterControl
++#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
++#define ASIC_StaticPwrMgtStatusChange            SetUniphyInstance
++#define HPDInterruptService                      ReadHWAssistedI2CStatus
++#define EnableVGA_Access                         GetSCLKOverMCLKRatio
++#define EnableYUV                                GetDispObjectInfo
++#define DynamicClockGating                       EnableDispPowerGating
++#define SetupHWAssistedI2CStatus                 ComputeMemoryClockParam
++#define DAC2OutputControl                        ReadEfuseValue
++
++#define TMDSAEncoderControl                      PatchMCSetting
++#define LVDSEncoderControl                       MC_SEQ_Control
++#define LCD1OutputControl                        HW_Misc_Operation
++#define TV1OutputControl                         Gfx_Harvesting
++#define TVEncoderControl                         SMC_Init
++
++typedef struct _ATOM_MASTER_COMMAND_TABLE
++{
++  ATOM_COMMON_TABLE_HEADER           sHeader;
++  ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
++}ATOM_MASTER_COMMAND_TABLE;
++
++/****************************************************************************/
++// Structures used in every command table
++/****************************************************************************/
++typedef struct _ATOM_TABLE_ATTRIBUTE
++{
++#if ATOM_BIG_ENDIAN
++  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
++  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
++  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
++#else
++  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
++  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
++  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
++#endif
++}ATOM_TABLE_ATTRIBUTE;
++
++/****************************************************************************/
++// Common header for all command tables.
++// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
++// And the pointer actually points to this header.
++/****************************************************************************/
++typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
++{
++  ATOM_COMMON_TABLE_HEADER CommonHeader;
++  ATOM_TABLE_ATTRIBUTE     TableAttribute;
++}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
++
++/****************************************************************************/
++// Structures used by ComputeMemoryEnginePLLTable
++/****************************************************************************/
++
++#define COMPUTE_MEMORY_PLL_PARAM        1
++#define COMPUTE_ENGINE_PLL_PARAM        2
++#define ADJUST_MC_SETTING_PARAM         3
++
++/****************************************************************************/
++// Structures used by AdjustMemoryControllerTable
++/****************************************************************************/
++typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
++{
++#if ATOM_BIG_ENDIAN
++  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
++  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
++  ULONG ulClockFreq:24;
++#else
++  ULONG ulClockFreq:24;
++  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
++  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
++#endif
++}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
++#define POINTER_RETURN_FLAG             0x80
++
++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
++{
++  ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
++  UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine
++  UCHAR   ucReserved;     //may expand to return larger Fbdiv later
++  UCHAR   ucFbDiv;        //return value
++  UCHAR   ucPostDiv;      //return value
++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
++
++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
++{
++  ULONG   ulClock;        //When return, [23:0] return real clock
++  UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
++  USHORT  usFbDiv;          //return Feedback value to be written to register
++  UCHAR   ucPostDiv;      //return post div to be written to register
++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
++
++#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
++
++#define SET_CLOCK_FREQ_MASK                       0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
++#define USE_NON_BUS_CLOCK_MASK                    0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
++#define USE_MEMORY_SELF_REFRESH_MASK              0x02000000   //Only applicable to memory clock change, when set, using memory self refresh during clock transition
++#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE     0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
++#define FIRST_TIME_CHANGE_CLOCK                   0x08000000   //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
++#define SKIP_SW_PROGRAM_PLL                       0x10000000   //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
++#define USE_SS_ENABLED_PIXEL_CLOCK                USE_NON_BUS_CLOCK_MASK
++
++#define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
++#define b3USE_MEMORY_SELF_REFRESH                 0x02        //Only applicable to memory clock change, when set, using memory self refresh during clock transition
++#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
++#define b3FIRST_TIME_CHANGE_CLOCK                 0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
++#define b3SKIP_SW_PROGRAM_PLL                     0x10       //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
++#define b3DRAM_SELF_REFRESH_EXIT                  0x20       //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path
++
++typedef struct _ATOM_COMPUTE_CLOCK_FREQ
++{
++#if ATOM_BIG_ENDIAN
++  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
++  ULONG ulClockFreq:24;                       // in unit of 10kHz
++#else
++  ULONG ulClockFreq:24;                       // in unit of 10kHz
++  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
++#endif
++}ATOM_COMPUTE_CLOCK_FREQ;
++
++typedef struct _ATOM_S_MPLL_FB_DIVIDER
++{
++  USHORT usFbDivFrac;
++  USHORT usFbDiv;
++}ATOM_S_MPLL_FB_DIVIDER;
++
++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
++{
++  union
++  {
++    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
++    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
++  };
++  UCHAR   ucRefDiv;                           //Output Parameter
++  UCHAR   ucPostDiv;                          //Output Parameter
++  UCHAR   ucCntlFlag;                         //Output Parameter
++  UCHAR   ucReserved;
++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
++
++// ucCntlFlag
++#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
++#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
++#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
++#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9                  8
++
++
++// V4 are only used for APU which PLL outside GPU
++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
++{
++#if ATOM_BIG_ENDIAN
++  ULONG  ucPostDiv:8;        //return parameter: post divider which is used to program to register directly
++  ULONG  ulClock:24;         //Input= target clock, output = actual clock
++#else
++  ULONG  ulClock:24;         //Input= target clock, output = actual clock
++  ULONG  ucPostDiv:8;        //return parameter: post divider which is used to program to register directly
++#endif
++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
++
++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
++{
++  union
++  {
++    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
++    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
++  };
++  UCHAR   ucRefDiv;                           //Output Parameter
++  UCHAR   ucPostDiv;                          //Output Parameter
++  union
++  {
++    UCHAR   ucCntlFlag;                       //Output Flags
++    UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
++  };
++  UCHAR   ucReserved;
++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
++
++
++typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
++{
++  ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
++  ULONG   ulReserved[2];
++}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
++
++//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
++#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK            0x0f
++#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK           0x00
++#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK                     0x01
++
++
++typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
++{
++  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4  ulClock;         //Output Parameter: ucPostDiv=DFS divider
++  ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter: PLL FB divider
++  UCHAR   ucPllRefDiv;                      //Output Parameter: PLL ref divider
++  UCHAR   ucPllPostDiv;                     //Output Parameter: PLL post divider
++  UCHAR   ucPllCntlFlag;                    //Output Flags: control flag
++  UCHAR   ucReserved;
++}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
++
++//ucPllCntlFlag
++#define SPLL_CNTL_FLAG_VCO_MODE_MASK            0x03
++
++
++// ucInputFlag
++#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
++
++// use for ComputeMemoryClockParamTable
++typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
++{
++  union
++  {
++    ULONG  ulClock;
++    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output:UPPER_WORD=FB_DIV_INTEGER,  LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
++  };
++  UCHAR   ucDllSpeed;                         //Output
++  UCHAR   ucPostDiv;                          //Output
++  union{
++    UCHAR   ucInputFlag;                      //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
++    UCHAR   ucPllCntlFlag;                    //Output:
++  };
++  UCHAR   ucBWCntl;
++}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
++
++// definition of ucInputFlag
++#define MPLL_INPUT_FLAG_STROBE_MODE_EN          0x01
++// definition of ucPllCntlFlag
++#define MPLL_CNTL_FLAG_VCO_MODE_MASK            0x03
++#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL            0x04
++#define MPLL_CNTL_FLAG_QDR_ENABLE               0x08
++#define MPLL_CNTL_FLAG_AD_HALF_RATE             0x10
++
++//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
++#define MPLL_CNTL_FLAG_BYPASS_AD_PLL            0x04
++
++typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
++{
++  ATOM_COMPUTE_CLOCK_FREQ ulClock;
++  ULONG ulReserved[2];
++}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
++
++typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
++{
++  ATOM_COMPUTE_CLOCK_FREQ ulClock;
++  ULONG ulMemoryClock;
++  ULONG ulReserved;
++}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
++
++/****************************************************************************/
++// Structures used by SetEngineClockTable
++/****************************************************************************/
++typedef struct _SET_ENGINE_CLOCK_PARAMETERS
++{
++  ULONG ulTargetEngineClock;          //In 10Khz unit
++}SET_ENGINE_CLOCK_PARAMETERS;
++
++typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
++{
++  ULONG ulTargetEngineClock;          //In 10Khz unit
++  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
++}SET_ENGINE_CLOCK_PS_ALLOCATION;
++
++/****************************************************************************/
++// Structures used by SetMemoryClockTable
++/****************************************************************************/
++typedef struct _SET_MEMORY_CLOCK_PARAMETERS
++{
++  ULONG ulTargetMemoryClock;          //In 10Khz unit
++}SET_MEMORY_CLOCK_PARAMETERS;
++
++typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
++{
++  ULONG ulTargetMemoryClock;          //In 10Khz unit
++  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
++}SET_MEMORY_CLOCK_PS_ALLOCATION;
++
++/****************************************************************************/
++// Structures used by ASIC_Init.ctb
++/****************************************************************************/
++typedef struct _ASIC_INIT_PARAMETERS
++{
++  ULONG ulDefaultEngineClock;         //In 10Khz unit
++  ULONG ulDefaultMemoryClock;         //In 10Khz unit
++}ASIC_INIT_PARAMETERS;
++
++typedef struct _ASIC_INIT_PS_ALLOCATION
++{
++  ASIC_INIT_PARAMETERS sASICInitClocks;
++  SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
++}ASIC_INIT_PS_ALLOCATION;
++
++typedef struct _ASIC_INIT_CLOCK_PARAMETERS
++{
++  ULONG ulClkFreqIn10Khz:24;
++  ULONG ucClkFlag:8;
++}ASIC_INIT_CLOCK_PARAMETERS;
++
++typedef struct _ASIC_INIT_PARAMETERS_V1_2
++{
++  ASIC_INIT_CLOCK_PARAMETERS asSclkClock;         //In 10Khz unit
++  ASIC_INIT_CLOCK_PARAMETERS asMemClock;          //In 10Khz unit
++}ASIC_INIT_PARAMETERS_V1_2;
++
++typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2
++{
++  ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks;
++  ULONG ulReserved[8];
++}ASIC_INIT_PS_ALLOCATION_V1_2;
++
++/****************************************************************************/
++// Structure used by DynamicClockGatingTable.ctb
++/****************************************************************************/
++typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
++{
++  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR ucPadding[3];
++}DYNAMIC_CLOCK_GATING_PARAMETERS;
++#define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
++
++/****************************************************************************/
++// Structure used by EnableDispPowerGatingTable.ctb
++/****************************************************************************/
++typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
++{
++  UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
++  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR ucPadding[2];
++}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
++
++typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION
++{
++  UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
++  UCHAR ucEnable;                     // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
++  UCHAR ucPadding[2];
++  ULONG ulReserved[4];
++}ENABLE_DISP_POWER_GATING_PS_ALLOCATION;
++
++/****************************************************************************/
++// Structure used by EnableASIC_StaticPwrMgtTable.ctb
++/****************************************************************************/
++typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
++{
++  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR ucPadding[3];
++}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
++#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
++
++/****************************************************************************/
++// Structures used by DAC_LoadDetectionTable.ctb
++/****************************************************************************/
++typedef struct _DAC_LOAD_DETECTION_PARAMETERS
++{
++  USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
++  UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
++  UCHAR  ucMisc;                                 //Valid only when table revision =1.3 and above
++}DAC_LOAD_DETECTION_PARAMETERS;
++
++// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
++#define DAC_LOAD_MISC_YPrPb                  0x01
++
++typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
++{
++  DAC_LOAD_DETECTION_PARAMETERS            sDacload;
++  ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
++}DAC_LOAD_DETECTION_PS_ALLOCATION;
++
++/****************************************************************************/
++// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
++/****************************************************************************/
++typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
++{
++  USHORT usPixelClock;                // in 10KHz; for bios convenient
++  UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
++  UCHAR  ucAction;                    // 0: turn off encoder
++                                      // 1: setup and turn on encoder
++                                      // 7: ATOM_ENCODER_INIT Initialize DAC
++}DAC_ENCODER_CONTROL_PARAMETERS;
++
++#define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
++
++/****************************************************************************/
++// Structures used by DIG1EncoderControlTable
++//                    DIG2EncoderControlTable
++//                    ExternalEncoderControlTable
++/****************************************************************************/
++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
++{
++  USHORT usPixelClock;      // in 10KHz; for bios convenient
++  UCHAR  ucConfig;
++                            // [2] Link Select:
++                            // =0: PHY linkA if bfLane<3
++                            // =1: PHY linkB if bfLanes<3
++                            // =0: PHY linkA+B if bfLanes=3
++                            // [3] Transmitter Sel
++                            // =0: UNIPHY or PCIEPHY
++                            // =1: LVTMA
++  UCHAR ucAction;           // =0: turn off encoder
++                            // =1: turn on encoder
++  UCHAR ucEncoderMode;
++                            // =0: DP   encoder
++                            // =1: LVDS encoder
++                            // =2: DVI  encoder
++                            // =3: HDMI encoder
++                            // =4: SDVO encoder
++  UCHAR ucLaneNum;          // how many lanes to enable
++  UCHAR ucReserved[2];
++}DIG_ENCODER_CONTROL_PARAMETERS;
++#define DIG_ENCODER_CONTROL_PS_ALLOCATION             DIG_ENCODER_CONTROL_PARAMETERS
++#define EXTERNAL_ENCODER_CONTROL_PARAMETER            DIG_ENCODER_CONTROL_PARAMETERS
++
++//ucConfig
++#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK           0x01
++#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ        0x00
++#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ        0x01
++#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ        0x02
++#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK             0x04
++#define ATOM_ENCODER_CONFIG_LINKA                     0x00
++#define ATOM_ENCODER_CONFIG_LINKB                     0x04
++#define ATOM_ENCODER_CONFIG_LINKA_B                   ATOM_TRANSMITTER_CONFIG_LINKA
++#define ATOM_ENCODER_CONFIG_LINKB_A                   ATOM_ENCODER_CONFIG_LINKB
++#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK      0x08
++#define ATOM_ENCODER_CONFIG_UNIPHY                    0x00
++#define ATOM_ENCODER_CONFIG_LVTMA                     0x08
++#define ATOM_ENCODER_CONFIG_TRANSMITTER1              0x00
++#define ATOM_ENCODER_CONFIG_TRANSMITTER2              0x08
++#define ATOM_ENCODER_CONFIG_DIGB                      0x80         // VBIOS Internal use, outside SW should set this bit=0
++// ucAction
++// ATOM_ENABLE:  Enable Encoder
++// ATOM_DISABLE: Disable Encoder
++
++//ucEncoderMode
++#define ATOM_ENCODER_MODE_DP                          0
++#define ATOM_ENCODER_MODE_LVDS                        1
++#define ATOM_ENCODER_MODE_DVI                         2
++#define ATOM_ENCODER_MODE_HDMI                        3
++#define ATOM_ENCODER_MODE_SDVO                        4
++#define ATOM_ENCODER_MODE_DP_AUDIO                    5
++#define ATOM_ENCODER_MODE_TV                          13
++#define ATOM_ENCODER_MODE_CV                          14
++#define ATOM_ENCODER_MODE_CRT                         15
++#define ATOM_ENCODER_MODE_DVO                         16
++#define ATOM_ENCODER_MODE_DP_SST                      ATOM_ENCODER_MODE_DP    // For DP1.2
++#define ATOM_ENCODER_MODE_DP_MST                      5                       // For DP1.2
++
++
++typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
++{
++#if ATOM_BIG_ENDIAN
++    UCHAR ucReserved1:2;
++    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
++    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
++    UCHAR ucReserved:1;
++    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
++#else
++    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
++    UCHAR ucReserved:1;
++    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
++    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
++    UCHAR ucReserved1:2;
++#endif
++}ATOM_DIG_ENCODER_CONFIG_V2;
++
++
++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
++{
++  USHORT usPixelClock;      // in 10KHz; for bios convenient
++  ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
++  UCHAR ucAction;
++  UCHAR ucEncoderMode;
++                            // =0: DP   encoder
++                            // =1: LVDS encoder
++                            // =2: DVI  encoder
++                            // =3: HDMI encoder
++                            // =4: SDVO encoder
++  UCHAR ucLaneNum;          // how many lanes to enable
++  UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
++  UCHAR ucReserved;
++}DIG_ENCODER_CONTROL_PARAMETERS_V2;
++
++//ucConfig
++#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK            0x01
++#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ        0x00
++#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ        0x01
++#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK              0x04
++#define ATOM_ENCODER_CONFIG_V2_LINKA                          0x00
++#define ATOM_ENCODER_CONFIG_V2_LINKB                          0x04
++#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK     0x18
++#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                0x00
++#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                0x08
++#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                0x10
++
++// ucAction:
++// ATOM_DISABLE
++// ATOM_ENABLE
++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
++#define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
++#define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
++#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
++#define ATOM_ENCODER_CMD_SETUP                        0x0f
++#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE            0x10
++
++// ucStatus
++#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
++#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=3
++// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
++typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
++{
++#if ATOM_BIG_ENDIAN
++    UCHAR ucReserved1:1;
++    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
++    UCHAR ucReserved:3;
++    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
++#else
++    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
++    UCHAR ucReserved:3;
++    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
++    UCHAR ucReserved1:1;
++#endif
++}ATOM_DIG_ENCODER_CONFIG_V3;
++
++#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK            0x03
++#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ        0x00
++#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ        0x01
++#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL                 0x70
++#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER                 0x00
++#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER                 0x10
++#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER                 0x20
++#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER                 0x30
++#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER                 0x40
++#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER                 0x50
++
++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
++{
++  USHORT usPixelClock;      // in 10KHz; for bios convenient
++  ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
++  UCHAR ucAction;
++  union{
++    UCHAR ucEncoderMode;
++                            // =0: DP   encoder
++                            // =1: LVDS encoder
++                            // =2: DVI  encoder
++                            // =3: HDMI encoder
++                            // =4: SDVO encoder
++                            // =5: DP audio
++    UCHAR ucPanelMode;        // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
++                            // =0:     external DP
++                            // =0x1:   internal DP2
++                            // =0x11:  internal DP1 for NutMeg/Travis DP translator
++  };
++  UCHAR ucLaneNum;          // how many lanes to enable
++  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
++  UCHAR ucReserved;
++}DIG_ENCODER_CONTROL_PARAMETERS_V3;
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=4
++// start from NI
++// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
++typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
++{
++#if ATOM_BIG_ENDIAN
++    UCHAR ucReserved1:1;
++    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
++    UCHAR ucReserved:2;
++    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
++#else
++    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
++    UCHAR ucReserved:2;
++    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
++    UCHAR ucReserved1:1;
++#endif
++}ATOM_DIG_ENCODER_CONFIG_V4;
++
++#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK            0x03
++#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ        0x00
++#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ        0x01
++#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ        0x02
++#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ        0x03
++#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL                 0x70
++#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER                 0x00
++#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER                 0x10
++#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER                 0x20
++#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER                 0x30
++#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER                 0x40
++#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER                 0x50
++#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER                 0x60
++
++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
++{
++  USHORT usPixelClock;      // in 10KHz; for bios convenient
++  union{
++  ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
++  UCHAR ucConfig;
++  };
++  UCHAR ucAction;
++  union{
++    UCHAR ucEncoderMode;
++                            // =0: DP   encoder
++                            // =1: LVDS encoder
++                            // =2: DVI  encoder
++                            // =3: HDMI encoder
++                            // =4: SDVO encoder
++                            // =5: DP audio
++    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
++                            // =0:     external DP
++                            // =0x1:   internal DP2
++                            // =0x11:  internal DP1 for NutMeg/Travis DP translator
++  };
++  UCHAR ucLaneNum;          // how many lanes to enable
++  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
++  UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
++}DIG_ENCODER_CONTROL_PARAMETERS_V4;
++
++// define ucBitPerColor:
++#define PANEL_BPC_UNDEFINE                               0x00
++#define PANEL_6BIT_PER_COLOR                             0x01
++#define PANEL_8BIT_PER_COLOR                             0x02
++#define PANEL_10BIT_PER_COLOR                            0x03
++#define PANEL_12BIT_PER_COLOR                            0x04
++#define PANEL_16BIT_PER_COLOR                            0x05
++
++//define ucPanelMode
++#define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
++#define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
++#define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
++
++/****************************************************************************/
++// Structures used by UNIPHYTransmitterControlTable
++//                    LVTMATransmitterControlTable
++//                    DVOOutputControlTable
++/****************************************************************************/
++typedef struct _ATOM_DP_VS_MODE
++{
++  UCHAR ucLaneSel;
++  UCHAR ucLaneSet;
++}ATOM_DP_VS_MODE;
++
++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
++{
++   union
++   {
++  USHORT usPixelClock;      // in 10KHz; for bios convenient
++   USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
++  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
++   };
++  UCHAR ucConfig;
++                                       // [0]=0: 4 lane Link,
++                                       //    =1: 8 lane Link ( Dual Links TMDS )
++                          // [1]=0: InCoherent mode
++                                       //    =1: Coherent Mode
++                                       // [2] Link Select:
++                                      // =0: PHY linkA   if bfLane<3
++                                       // =1: PHY linkB   if bfLanes<3
++                                      // =0: PHY linkA+B if bfLanes=3
++                          // [5:4]PCIE lane Sel
++                          // =0: lane 0~3 or 0~7
++                          // =1: lane 4~7
++                          // =2: lane 8~11 or 8~15
++                          // =3: lane 12~15
++   UCHAR ucAction;              // =0: turn off encoder
++                           // =1: turn on encoder
++  UCHAR ucReserved[4];
++}DIG_TRANSMITTER_CONTROL_PARAMETERS;
++
++#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION      DIG_TRANSMITTER_CONTROL_PARAMETERS
++
++//ucInitInfo
++#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK   0x00ff
++
++//ucConfig
++#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK         0x01
++#define ATOM_TRANSMITTER_CONFIG_COHERENT            0x02
++#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK      0x04
++#define ATOM_TRANSMITTER_CONFIG_LINKA                  0x00
++#define ATOM_TRANSMITTER_CONFIG_LINKB                  0x04
++#define ATOM_TRANSMITTER_CONFIG_LINKA_B               0x00
++#define ATOM_TRANSMITTER_CONFIG_LINKB_A               0x04
++
++#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK   0x08         // only used when ATOM_TRANSMITTER_ACTION_ENABLE
++#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER      0x00            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
++#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER      0x08            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
++
++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK         0x30
++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL         0x00
++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE         0x20
++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN      0x30
++#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK      0xc0
++#define ATOM_TRANSMITTER_CONFIG_LANE_0_3            0x00
++#define ATOM_TRANSMITTER_CONFIG_LANE_0_7            0x00
++#define ATOM_TRANSMITTER_CONFIG_LANE_4_7            0x40
++#define ATOM_TRANSMITTER_CONFIG_LANE_8_11            0x80
++#define ATOM_TRANSMITTER_CONFIG_LANE_8_15            0x80
++#define ATOM_TRANSMITTER_CONFIG_LANE_12_15         0xc0
++
++//ucAction
++#define ATOM_TRANSMITTER_ACTION_DISABLE                      0
++#define ATOM_TRANSMITTER_ACTION_ENABLE                      1
++#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                   2
++#define ATOM_TRANSMITTER_ACTION_LCD_BLON                   3
++#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
++#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START       5
++#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP          6
++#define ATOM_TRANSMITTER_ACTION_INIT                         7
++#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT          8
++#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT             9
++#define ATOM_TRANSMITTER_ACTION_SETUP                         10
++#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
++#define ATOM_TRANSMITTER_ACTION_POWER_ON               12
++#define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
++
++// Following are used for DigTransmitterControlTable ver1.2
++typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
++                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
++                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
++  UCHAR ucReserved:1;
++  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
++  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
++  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
++                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
++
++  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
++  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
++#else
++  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
++  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
++  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
++                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
++  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
++  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
++  UCHAR ucReserved:1;
++  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
++                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
++                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
++#endif
++}ATOM_DIG_TRANSMITTER_CONFIG_V2;
++
++//ucConfig
++//Bit0
++#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR         0x01
++
++//Bit1
++#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                      0x02
++
++//Bit2
++#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK              0x04
++#define ATOM_TRANSMITTER_CONFIG_V2_LINKA                       0x00
++#define ATOM_TRANSMITTER_CONFIG_V2_LINKB                        0x04
++
++// Bit3
++#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK           0x08
++#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                0x00            // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
++#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                0x08            // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
++
++// Bit4
++#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                 0x10
++
++// Bit7:6
++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1              0x00   //AB
++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2              0x40   //CD
++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3              0x80   //EF
++
++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
++{
++   union
++   {
++  USHORT usPixelClock;      // in 10KHz; for bios convenient
++   USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
++  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
++   };
++  ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
++   UCHAR ucAction;              // define as ATOM_TRANSMITER_ACTION_XXX
++  UCHAR ucReserved[4];
++}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
++
++typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
++                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
++                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
++  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
++  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
++  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
++                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
++  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
++  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
++#else
++  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
++  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
++  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
++                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
++  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
++  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
++  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
++                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
++                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
++#endif
++}ATOM_DIG_TRANSMITTER_CONFIG_V3;
++
++
++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
++{
++   union
++   {
++    USHORT usPixelClock;      // in 10KHz; for bios convenient
++     USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
++    ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
++   };
++  ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
++   UCHAR ucAction;                // define as ATOM_TRANSMITER_ACTION_XXX
++  UCHAR ucLaneNum;
++  UCHAR ucReserved[3];
++}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
++
++//ucConfig
++//Bit0
++#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR         0x01
++
++//Bit1
++#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT                      0x02
++
++//Bit2
++#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK              0x04
++#define ATOM_TRANSMITTER_CONFIG_V3_LINKA                       0x00
++#define ATOM_TRANSMITTER_CONFIG_V3_LINKB                        0x04
++
++// Bit3
++#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK           0x08
++#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER                0x00
++#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER                0x08
++
++// Bit5:4
++#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK            0x30
++#define ATOM_TRASMITTER_CONFIG_V3_P1PLL                        0x00
++#define ATOM_TRASMITTER_CONFIG_V3_P2PLL                        0x10
++#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
++
++// Bit7:6
++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1              0x00   //AB
++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2              0x40   //CD
++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3              0x80   //EF
++
++
++/****************************************************************************/
++// Structures used by UNIPHYTransmitterControlTable V1.4
++// ASIC Families: NI
++// ucTableFormatRevision=1
++// ucTableContentRevision=4
++/****************************************************************************/
++typedef struct _ATOM_DP_VS_MODE_V4
++{
++  UCHAR ucLaneSel;
++ 	union
++	{
++ 	  UCHAR ucLaneSet;
++ 	  struct {
++#if ATOM_BIG_ENDIAN
++ 		  UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
++ 		  UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
++ 		  UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
++#else
++ 		  UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
++ 		  UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
++ 		  UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
++#endif
++		};
++	};
++}ATOM_DP_VS_MODE_V4;
++
++typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
++                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
++                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
++  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
++  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
++  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
++                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
++  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
++  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
++#else
++  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
++  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
++  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
++                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
++  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
++  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
++  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
++                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
++                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
++#endif
++}ATOM_DIG_TRANSMITTER_CONFIG_V4;
++
++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
++{
++  union
++  {
++    USHORT usPixelClock;      // in 10KHz; for bios convenient
++    USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
++    ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode     Redefined comparing to previous version
++  };
++  union
++  {
++  ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
++  UCHAR ucConfig;
++  };
++  UCHAR ucAction;                // define as ATOM_TRANSMITER_ACTION_XXX
++  UCHAR ucLaneNum;
++  UCHAR ucReserved[3];
++}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
++
++//ucConfig
++//Bit0
++#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR         0x01
++//Bit1
++#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT                      0x02
++//Bit2
++#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK              0x04
++#define ATOM_TRANSMITTER_CONFIG_V4_LINKA                       0x00
++#define ATOM_TRANSMITTER_CONFIG_V4_LINKB                        0x04
++// Bit3
++#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK           0x08
++#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER                0x00
++#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER                0x08
++// Bit5:4
++#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK            0x30
++#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL                       0x00
++#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL                      0x10
++#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL                      0x20   // New in _V4
++#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT           0x30   // Changed comparing to V3
++// Bit7:6
++#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK     0xC0
++#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1              0x00   //AB
++#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2              0x40   //CD
++#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3              0x80   //EF
++
++
++typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR ucReservd1:1;
++  UCHAR ucHPDSel:3;
++  UCHAR ucPhyClkSrcId:2;
++  UCHAR ucCoherentMode:1;
++  UCHAR ucReserved:1;
++#else
++  UCHAR ucReserved:1;
++  UCHAR ucCoherentMode:1;
++  UCHAR ucPhyClkSrcId:2;
++  UCHAR ucHPDSel:3;
++  UCHAR ucReservd1:1;
++#endif
++}ATOM_DIG_TRANSMITTER_CONFIG_V5;
++
++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
++{
++  USHORT usSymClock;              // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock,  (HDMI deep color), =pixel clock * deep_color_ratio
++  UCHAR  ucPhyId;                   // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
++  UCHAR  ucAction;                // define as ATOM_TRANSMITER_ACTION_xxx
++  UCHAR  ucLaneNum;                 // indicate lane number 1-8
++  UCHAR  ucConnObjId;               // Connector Object Id defined in ObjectId.h
++  UCHAR  ucDigMode;                 // indicate DIG mode
++  union{
++  ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
++  UCHAR ucConfig;
++  };
++  UCHAR  ucDigEncoderSel;           // indicate DIG front end encoder
++  UCHAR  ucDPLaneSet;
++  UCHAR  ucReserved;
++  UCHAR  ucReserved1;
++}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
++
++//ucPhyId
++#define ATOM_PHY_ID_UNIPHYA                                 0
++#define ATOM_PHY_ID_UNIPHYB                                 1
++#define ATOM_PHY_ID_UNIPHYC                                 2
++#define ATOM_PHY_ID_UNIPHYD                                 3
++#define ATOM_PHY_ID_UNIPHYE                                 4
++#define ATOM_PHY_ID_UNIPHYF                                 5
++#define ATOM_PHY_ID_UNIPHYG                                 6
++
++// ucDigEncoderSel
++#define ATOM_TRANMSITTER_V5__DIGA_SEL                       0x01
++#define ATOM_TRANMSITTER_V5__DIGB_SEL                       0x02
++#define ATOM_TRANMSITTER_V5__DIGC_SEL                       0x04
++#define ATOM_TRANMSITTER_V5__DIGD_SEL                       0x08
++#define ATOM_TRANMSITTER_V5__DIGE_SEL                       0x10
++#define ATOM_TRANMSITTER_V5__DIGF_SEL                       0x20
++#define ATOM_TRANMSITTER_V5__DIGG_SEL                       0x40
++
++// ucDigMode
++#define ATOM_TRANSMITTER_DIGMODE_V5_DP                      0
++#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS                    1
++#define ATOM_TRANSMITTER_DIGMODE_V5_DVI                     2
++#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI                    3
++#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO                    4
++#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST                  5
++
++// ucDPLaneSet
++#define DP_LANE_SET__0DB_0_4V                               0x00
++#define DP_LANE_SET__0DB_0_6V                               0x01
++#define DP_LANE_SET__0DB_0_8V                               0x02
++#define DP_LANE_SET__0DB_1_2V                               0x03
++#define DP_LANE_SET__3_5DB_0_4V                             0x08
++#define DP_LANE_SET__3_5DB_0_6V                             0x09
++#define DP_LANE_SET__3_5DB_0_8V                             0x0a
++#define DP_LANE_SET__6DB_0_4V                               0x10
++#define DP_LANE_SET__6DB_0_6V                               0x11
++#define DP_LANE_SET__9_5DB_0_4V                             0x18
++
++// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
++// Bit1
++#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT                      0x02
++
++// Bit3:2
++#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK            0x0c
++#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT          0x02
++
++#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL                       0x00
++#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL                      0x04
++#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL                      0x08
++#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT           0x0c
++// Bit6:4
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK                0x70
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT            0x04
++
++#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL                    0x00
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL                      0x10
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL                      0x20
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL                      0x30
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL                      0x40
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL                      0x50
++#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL                      0x60
++
++#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5            DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
++
++
++/****************************************************************************/
++// Structures used by ExternalEncoderControlTable V1.3
++// ASIC Families: Evergreen, Llano, NI
++// ucTableFormatRevision=1
++// ucTableContentRevision=3
++/****************************************************************************/
++
++typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
++{
++  union{
++  USHORT usPixelClock;      // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
++  USHORT usConnectorId;     // connector id, valid when ucAction = INIT
++  };
++  UCHAR  ucConfig;          // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
++  UCHAR  ucAction;          //
++  UCHAR  ucEncoderMode;     // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
++  UCHAR  ucLaneNum;         // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
++  UCHAR  ucBitPerColor;     // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
++  UCHAR  ucReserved;
++}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
++
++// ucAction
++#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT         0x00
++#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT          0x01
++#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT           0x07
++#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP          0x0f
++#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
++#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING       0x11
++#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION      0x12
++#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP              0x14
++
++// ucConfig
++#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK            0x03
++#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ        0x00
++#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ        0x01
++#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ        0x02
++#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS          0x70
++#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                  0x00
++#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                  0x10
++#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                  0x20
++
++typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
++{
++  EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
++  ULONG ulReserved[2];
++}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
++
++
++/****************************************************************************/
++// Structures used by DAC1OuputControlTable
++//                    DAC2OuputControlTable
++//                    LVTMAOutputControlTable  (Before DEC30)
++//                    TMDSAOutputControlTable  (Before DEC30)
++/****************************************************************************/
++typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++{
++  UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
++                                      // When the display is LCD, in addition to above:
++                                      // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
++                                      // ATOM_LCD_SELFTEST_STOP
++
++  UCHAR  aucPadding[3];               // padding to DWORD aligned
++}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
++
++#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++
++
++#define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
++#define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
++#define DVO_OUTPUT_CONTROL_PARAMETERS_V3   DIG_TRANSMITTER_CONTROL_PARAMETERS
++
++
++typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2
++{
++  // Possible value of ucAction
++  // ATOM_TRANSMITTER_ACTION_LCD_BLON
++  // ATOM_TRANSMITTER_ACTION_LCD_BLOFF
++  // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
++  // ATOM_TRANSMITTER_ACTION_POWER_ON
++  // ATOM_TRANSMITTER_ACTION_POWER_OFF
++  UCHAR  ucAction;
++  UCHAR  ucBriLevel;
++  USHORT usPwmFreq;                  // in unit of Hz, 200 means 200Hz
++}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;
++
++
++
++/****************************************************************************/
++// Structures used by BlankCRTCTable
++/****************************************************************************/
++typedef struct _BLANK_CRTC_PARAMETERS
++{
++  UCHAR  ucCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
++  USHORT usBlackColorRCr;
++  USHORT usBlackColorGY;
++  USHORT usBlackColorBCb;
++}BLANK_CRTC_PARAMETERS;
++#define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
++
++/****************************************************************************/
++// Structures used by EnableCRTCTable
++//                    EnableCRTCMemReqTable
++//                    UpdateCRTC_DoubleBufferRegistersTable
++/****************************************************************************/
++typedef struct _ENABLE_CRTC_PARAMETERS
++{
++  UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR ucPadding[2];
++}ENABLE_CRTC_PARAMETERS;
++#define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
++
++/****************************************************************************/
++// Structures used by SetCRTC_OverScanTable
++/****************************************************************************/
++typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
++{
++  USHORT usOverscanRight;             // right
++  USHORT usOverscanLeft;              // left
++  USHORT usOverscanBottom;            // bottom
++  USHORT usOverscanTop;               // top
++  UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR  ucPadding[3];
++}SET_CRTC_OVERSCAN_PARAMETERS;
++#define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
++
++/****************************************************************************/
++// Structures used by SetCRTC_ReplicationTable
++/****************************************************************************/
++typedef struct _SET_CRTC_REPLICATION_PARAMETERS
++{
++  UCHAR ucH_Replication;              // horizontal replication
++  UCHAR ucV_Replication;              // vertical replication
++  UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR ucPadding;
++}SET_CRTC_REPLICATION_PARAMETERS;
++#define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
++
++/****************************************************************************/
++// Structures used by SelectCRTC_SourceTable
++/****************************************************************************/
++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
++{
++  UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
++  UCHAR ucPadding[2];
++}SELECT_CRTC_SOURCE_PARAMETERS;
++#define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
++
++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
++{
++  UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
++  UCHAR ucEncodeMode;                           // Encoding mode, only valid when using DIG1/DIG2/DVO
++  UCHAR ucPadding;
++}SELECT_CRTC_SOURCE_PARAMETERS_V2;
++
++//ucEncoderID
++//#define ASIC_INT_DAC1_ENCODER_ID                      0x00
++//#define ASIC_INT_TV_ENCODER_ID                           0x02
++//#define ASIC_INT_DIG1_ENCODER_ID                        0x03
++//#define ASIC_INT_DAC2_ENCODER_ID                        0x04
++//#define ASIC_EXT_TV_ENCODER_ID                           0x06
++//#define ASIC_INT_DVO_ENCODER_ID                           0x07
++//#define ASIC_INT_DIG2_ENCODER_ID                        0x09
++//#define ASIC_EXT_DIG_ENCODER_ID                           0x05
++
++//ucEncodeMode
++//#define ATOM_ENCODER_MODE_DP                              0
++//#define ATOM_ENCODER_MODE_LVDS                           1
++//#define ATOM_ENCODER_MODE_DVI                              2
++//#define ATOM_ENCODER_MODE_HDMI                           3
++//#define ATOM_ENCODER_MODE_SDVO                           4
++//#define ATOM_ENCODER_MODE_TV                              13
++//#define ATOM_ENCODER_MODE_CV                              14
++//#define ATOM_ENCODER_MODE_CRT                              15
++
++
++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3
++{
++  UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR ucEncoderID;                    // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
++  UCHAR ucEncodeMode;                   // Encoding mode, only valid when using DIG1/DIG2/DVO
++  UCHAR ucDstBpc;                       // PANEL_6/8/10/12BIT_PER_COLOR
++}SELECT_CRTC_SOURCE_PARAMETERS_V3;
++
++
++/****************************************************************************/
++// Structures used by SetPixelClockTable
++//                    GetPixelClockTable
++/****************************************************************************/
++//Major revision=1., Minor revision=1
++typedef struct _PIXEL_CLOCK_PARAMETERS
++{
++  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
++                                      // 0 means disable PPLL
++  USHORT usRefDiv;                    // Reference divider
++  USHORT usFbDiv;                     // feedback divider
++  UCHAR  ucPostDiv;                   // post divider
++  UCHAR  ucFracFbDiv;                 // fractional feedback divider
++  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
++  UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
++  UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
++  UCHAR  ucPadding;
++}PIXEL_CLOCK_PARAMETERS;
++
++//Major revision=1., Minor revision=2, add ucMiscIfno
++//ucMiscInfo:
++#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
++#define MISC_DEVICE_INDEX_MASK        0xF0
++#define MISC_DEVICE_INDEX_SHIFT       4
++
++typedef struct _PIXEL_CLOCK_PARAMETERS_V2
++{
++  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
++                                      // 0 means disable PPLL
++  USHORT usRefDiv;                    // Reference divider
++  USHORT usFbDiv;                     // feedback divider
++  UCHAR  ucPostDiv;                   // post divider
++  UCHAR  ucFracFbDiv;                 // fractional feedback divider
++  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
++  UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
++  UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
++  UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
++}PIXEL_CLOCK_PARAMETERS_V2;
++
++//Major revision=1., Minor revision=3, structure/definition change
++//ucEncoderMode:
++//ATOM_ENCODER_MODE_DP
++//ATOM_ENOCDER_MODE_LVDS
++//ATOM_ENOCDER_MODE_DVI
++//ATOM_ENOCDER_MODE_HDMI
++//ATOM_ENOCDER_MODE_SDVO
++//ATOM_ENCODER_MODE_TV                                          13
++//ATOM_ENCODER_MODE_CV                                          14
++//ATOM_ENCODER_MODE_CRT                                          15
++
++//ucDVOConfig
++//#define DVO_ENCODER_CONFIG_RATE_SEL                     0x01
++//#define DVO_ENCODER_CONFIG_DDR_SPEED                  0x00
++//#define DVO_ENCODER_CONFIG_SDR_SPEED                  0x01
++//#define DVO_ENCODER_CONFIG_OUTPUT_SEL                  0x0c
++//#define DVO_ENCODER_CONFIG_LOW12BIT                     0x00
++//#define DVO_ENCODER_CONFIG_UPPER12BIT                  0x04
++//#define DVO_ENCODER_CONFIG_24BIT                        0x08
++
++//ucMiscInfo: also changed, see below
++#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                  0x01
++#define PIXEL_CLOCK_MISC_VGA_MODE                              0x02
++#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                     0x04
++#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                     0x00
++#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                     0x04
++#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK         0x08
++#define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
++// V1.4 for RoadRunner
++#define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
++#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
++
++
++typedef struct _PIXEL_CLOCK_PARAMETERS_V3
++{
++  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
++                                      // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
++  USHORT usRefDiv;                    // Reference divider
++  USHORT usFbDiv;                     // feedback divider
++  UCHAR  ucPostDiv;                   // post divider
++  UCHAR  ucFracFbDiv;                 // fractional feedback divider
++  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
++  UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
++   union
++   {
++  UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
++   UCHAR  ucDVOConfig;                           // when use DVO, need to know SDR/DDR, 12bit or 24bit
++   };
++  UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
++                                      // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
++                                      // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
++}PIXEL_CLOCK_PARAMETERS_V3;
++
++#define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
++#define GET_PIXEL_CLOCK_PS_ALLOCATION                  PIXEL_CLOCK_PARAMETERS_LAST
++
++
++typedef struct _PIXEL_CLOCK_PARAMETERS_V5
++{
++  UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to
++                             // drive the pixel clock. not used for DCPLL case.
++  union{
++  UCHAR  ucReserved;
++  UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
++  };
++  USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
++                             // 0 means disable PPLL/DCPLL.
++  USHORT usFbDiv;            // feedback divider integer part.
++  UCHAR  ucPostDiv;          // post divider.
++  UCHAR  ucRefDiv;           // Reference divider
++  UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
++  UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
++                             // indicate which graphic encoder will be used.
++  UCHAR  ucEncoderMode;      // Encoder mode:
++  UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
++                             // bit[1]= when VGA timing is used.
++                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
++                             // bit[4]= RefClock source for PPLL.
++                             // =0: XTLAIN( default mode )
++                              // =1: other external clock source, which is pre-defined
++                             //     by VBIOS depend on the feature required.
++                             // bit[7:5]: reserved.
++  ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
++
++}PIXEL_CLOCK_PARAMETERS_V5;
++
++#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL               0x01
++#define PIXEL_CLOCK_V5_MISC_VGA_MODE                        0x02
++#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
++#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
++#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
++#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
++#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
++
++typedef struct _CRTC_PIXEL_CLOCK_FREQ
++{
++#if ATOM_BIG_ENDIAN
++  ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
++                              // drive the pixel clock. not used for DCPLL case.
++  ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
++                              // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
++#else
++  ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
++                              // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
++  ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
++                              // drive the pixel clock. not used for DCPLL case.
++#endif
++}CRTC_PIXEL_CLOCK_FREQ;
++
++typedef struct _PIXEL_CLOCK_PARAMETERS_V6
++{
++  union{
++    CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;    // pixel clock and CRTC id frequency
++    ULONG ulDispEngClkFreq;                  // dispclk frequency
++  };
++  USHORT usFbDiv;            // feedback divider integer part.
++  UCHAR  ucPostDiv;          // post divider.
++  UCHAR  ucRefDiv;           // Reference divider
++  UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
++  UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
++                             // indicate which graphic encoder will be used.
++  UCHAR  ucEncoderMode;      // Encoder mode:
++  UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
++                             // bit[1]= when VGA timing is used.
++                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
++                             // bit[4]= RefClock source for PPLL.
++                             // =0: XTLAIN( default mode )
++                              // =1: other external clock source, which is pre-defined
++                             //     by VBIOS depend on the feature required.
++                             // bit[7:5]: reserved.
++  ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
++
++}PIXEL_CLOCK_PARAMETERS_V6;
++
++#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL               0x01
++#define PIXEL_CLOCK_V6_MISC_VGA_MODE                        0x02
++#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK           0x0c
++#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP              0x00
++#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP              0x04
++#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6           0x08    //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
++#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP              0x08
++#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6           0x04    //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
++#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP              0x0c
++#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC             0x10
++#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK            0x40
++#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS         0x40
++
++typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
++{
++  PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
++}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
++
++typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
++{
++  UCHAR  ucStatus;
++  UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
++  UCHAR  ucReserved[2];
++}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
++
++typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
++{
++  PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
++}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
++
++
++/****************************************************************************/
++// Structures used by AdjustDisplayPllTable
++/****************************************************************************/
++typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
++{
++   USHORT usPixelClock;
++   UCHAR ucTransmitterID;
++   UCHAR ucEncodeMode;
++   union
++   {
++      UCHAR ucDVOConfig;                           //if DVO, need passing link rate and output 12bitlow or 24bit
++      UCHAR ucConfig;                                 //if none DVO, not defined yet
++   };
++   UCHAR ucReserved[3];
++}ADJUST_DISPLAY_PLL_PARAMETERS;
++
++#define ADJUST_DISPLAY_CONFIG_SS_ENABLE            0x10
++#define ADJUST_DISPLAY_PLL_PS_ALLOCATION              ADJUST_DISPLAY_PLL_PARAMETERS
++
++typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
++{
++   USHORT usPixelClock;                    // target pixel clock
++   UCHAR ucTransmitterID;                  // GPU transmitter id defined in objectid.h
++   UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
++  UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
++  UCHAR ucExtTransmitterID;               // external encoder id.
++   UCHAR ucReserved[2];
++}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
++
++// usDispPllConfig v1.2 for RoadRunner
++#define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
++#define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
++#define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
++#define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
++
++
++typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
++{
++  ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
++  UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
++  UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
++  UCHAR ucReserved[2];
++}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
++
++typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
++{
++  union
++  {
++    ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
++    ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
++  };
++} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
++
++/****************************************************************************/
++// Structures used by EnableYUVTable
++/****************************************************************************/
++typedef struct _ENABLE_YUV_PARAMETERS
++{
++  UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
++  UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
++  UCHAR ucPadding[2];
++}ENABLE_YUV_PARAMETERS;
++#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
++
++/****************************************************************************/
++// Structures used by GetMemoryClockTable
++/****************************************************************************/
++typedef struct _GET_MEMORY_CLOCK_PARAMETERS
++{
++  ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
++} GET_MEMORY_CLOCK_PARAMETERS;
++#define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
++
++/****************************************************************************/
++// Structures used by GetEngineClockTable
++/****************************************************************************/
++typedef struct _GET_ENGINE_CLOCK_PARAMETERS
++{
++  ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
++} GET_ENGINE_CLOCK_PARAMETERS;
++#define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
++
++/****************************************************************************/
++// Following Structures and constant may be obsolete
++/****************************************************************************/
++//Maxium 8 bytes,the data read in will be placed in the parameter space.
++//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
++typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
++{
++  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
++  USHORT    usVRAMAddress;      //Adress in Frame Buffer where to pace raw EDID
++  USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
++                                //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
++  UCHAR     ucSlaveAddr;        //Read from which slave
++  UCHAR     ucLineNumber;       //Read from which HW assisted line
++}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
++#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
++
++
++#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
++#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
++#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
++#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
++#define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
++
++typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
++{
++  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
++  USHORT    usByteOffset;       //Write to which byte
++                                //Upper portion of usByteOffset is Format of data
++                                //1bytePS+offsetPS
++                                //2bytesPS+offsetPS
++                                //blockID+offsetPS
++                                //blockID+offsetID
++                                //blockID+counterID+offsetID
++  UCHAR     ucData;             //PS data1
++  UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
++  UCHAR     ucSlaveAddr;        //Write to which slave
++  UCHAR     ucLineNumber;       //Write from which HW assisted line
++}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
++
++#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
++
++typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
++{
++  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
++  UCHAR     ucSlaveAddr;        //Write to which slave
++  UCHAR     ucLineNumber;       //Write from which HW assisted line
++}SET_UP_HW_I2C_DATA_PARAMETERS;
++
++/**************************************************************************/
++#define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
++
++
++/****************************************************************************/
++// Structures used by PowerConnectorDetectionTable
++/****************************************************************************/
++typedef struct   _POWER_CONNECTOR_DETECTION_PARAMETERS
++{
++  UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
++   UCHAR   ucPwrBehaviorId;
++   USHORT   usPwrBudget;                         //how much power currently boot to in unit of watt
++}POWER_CONNECTOR_DETECTION_PARAMETERS;
++
++typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
++{
++  UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
++   UCHAR   ucReserved;
++   USHORT   usPwrBudget;                         //how much power currently boot to in unit of watt
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
++}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
++
++
++/****************************LVDS SS Command Table Definitions**********************/
++
++/****************************************************************************/
++// Structures used by EnableSpreadSpectrumOnPPLLTable
++/****************************************************************************/
++typedef struct   _ENABLE_LVDS_SS_PARAMETERS
++{
++  USHORT  usSpreadSpectrumPercentage;
++  UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
++  UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
++  UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
++  UCHAR   ucPadding[3];
++}ENABLE_LVDS_SS_PARAMETERS;
++
++//ucTableFormatRevision=1,ucTableContentRevision=2
++typedef struct   _ENABLE_LVDS_SS_PARAMETERS_V2
++{
++  USHORT  usSpreadSpectrumPercentage;
++  UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
++  UCHAR   ucSpreadSpectrumStep;           //
++  UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
++  UCHAR   ucSpreadSpectrumDelay;
++  UCHAR   ucSpreadSpectrumRange;
++  UCHAR   ucPadding;
++}ENABLE_LVDS_SS_PARAMETERS_V2;
++
++//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
++typedef struct   _ENABLE_SPREAD_SPECTRUM_ON_PPLL
++{
++  USHORT  usSpreadSpectrumPercentage;
++  UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
++  UCHAR   ucSpreadSpectrumStep;           //
++  UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR   ucSpreadSpectrumDelay;
++  UCHAR   ucSpreadSpectrumRange;
++  UCHAR   ucPpll;                                      // ATOM_PPLL1/ATOM_PPLL2
++}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
++
++ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
++{
++  USHORT  usSpreadSpectrumPercentage;
++  UCHAR   ucSpreadSpectrumType;           // Bit[0]: 0-Down Spread,1-Center Spread.
++                                        // Bit[1]: 1-Ext. 0-Int.
++                                        // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
++                                        // Bits[7:4] reserved
++  UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
++  USHORT  usSpreadSpectrumAmount;         // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
++  USHORT  usSpreadSpectrumStep;           // SS_STEP_SIZE_DSFRAC
++}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
++
++#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
++#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
++#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
++#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
++#define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
++#define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
++#define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
++#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
++#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
++#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
++#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
++
++// Used by DCE5.0
++ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
++{
++  USHORT  usSpreadSpectrumAmountFrac;   // SS_AMOUNT_DSFRAC New in DCE5.0
++  UCHAR   ucSpreadSpectrumType;           // Bit[0]: 0-Down Spread,1-Center Spread.
++                                        // Bit[1]: 1-Ext. 0-Int.
++                                        // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
++                                        // Bits[7:4] reserved
++  UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
++  USHORT  usSpreadSpectrumAmount;         // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
++  USHORT  usSpreadSpectrumStep;           // SS_STEP_SIZE_DSFRAC
++}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
++
++
++#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD      0x00
++#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD    0x01
++#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD       0x02
++#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK    0x0c
++#define ATOM_PPLL_SS_TYPE_V3_P1PLL            0x00
++#define ATOM_PPLL_SS_TYPE_V3_P2PLL            0x04
++#define ATOM_PPLL_SS_TYPE_V3_DCPLL            0x08
++#define ATOM_PPLL_SS_TYPE_V3_P0PLL            ATOM_PPLL_SS_TYPE_V3_DCPLL
++#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK     0x00FF
++#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT    0
++#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK     0x0F00
++#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT    8
++
++#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
++
++typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
++{
++  PIXEL_CLOCK_PARAMETERS sPCLKInput;
++  ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
++}SET_PIXEL_CLOCK_PS_ALLOCATION;
++
++
++
++#define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
++
++/****************************************************************************/
++// Structures used by ###
++/****************************************************************************/
++typedef struct   _MEMORY_TRAINING_PARAMETERS
++{
++  ULONG ulTargetMemoryClock;          //In 10Khz unit
++}MEMORY_TRAINING_PARAMETERS;
++#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
++
++
++typedef struct   _MEMORY_TRAINING_PARAMETERS_V1_2
++{
++  USHORT usMemTrainingMode;
++  USHORT usReserved;
++}MEMORY_TRAINING_PARAMETERS_V1_2;
++
++//usMemTrainingMode
++#define NORMAL_MEMORY_TRAINING_MODE       0
++#define ENTER_DRAM_SELFREFRESH_MODE       1
++#define EXIT_DRAM_SELFRESH_MODE           2
++
++/****************************LVDS and other encoder command table definitions **********************/
++
++
++/****************************************************************************/
++// Structures used by LVDSEncoderControlTable   (Before DEC30)
++//                    LVTMAEncoderControlTable  (Before DEC30)
++//                    TMDSAEncoderControlTable  (Before DEC30)
++/****************************************************************************/
++typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
++{
++  USHORT usPixelClock;  // in 10KHz; for bios convenient
++  UCHAR  ucMisc;        // bit0=0: Enable single link
++                        //     =1: Enable dual link
++                        // Bit1=0: 666RGB
++                        //     =1: 888RGB
++  UCHAR  ucAction;      // 0: turn off encoder
++                        // 1: setup and turn on encoder
++}LVDS_ENCODER_CONTROL_PARAMETERS;
++
++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
++
++#define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
++
++#define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
++
++//ucTableFormatRevision=1,ucTableContentRevision=2
++typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
++{
++  USHORT usPixelClock;  // in 10KHz; for bios convenient
++  UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
++  UCHAR  ucAction;      // 0: turn off encoder
++                        // 1: setup and turn on encoder
++  UCHAR  ucTruncate;    // bit0=0: Disable truncate
++                        //     =1: Enable truncate
++                        // bit4=0: 666RGB
++                        //     =1: 888RGB
++  UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
++                        //     =1: Enable spatial dithering
++                        // bit4=0: 666RGB
++                        //     =1: 888RGB
++  UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
++                        //     =1: Enable temporal dithering
++                        // bit4=0: 666RGB
++                        //     =1: 888RGB
++                        // bit5=0: Gray level 2
++                        //     =1: Gray level 4
++  UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
++                        //     =1: 25FRC_SEL pattern F
++                        // bit6:5=0: 50FRC_SEL pattern A
++                        //       =1: 50FRC_SEL pattern B
++                        //       =2: 50FRC_SEL pattern C
++                        //       =3: 50FRC_SEL pattern D
++                        // bit7=0: 75FRC_SEL pattern E
++                        //     =1: 75FRC_SEL pattern F
++}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
++
++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
++
++#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
++
++#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
++
++
++#define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
++
++#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
++
++#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
++
++/****************************************************************************/
++// Structures used by ###
++/****************************************************************************/
++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
++{
++  UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
++  UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
++  UCHAR    ucPadding[2];
++}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
++
++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
++{
++  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
++}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
++
++#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
++{
++  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
++}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
++
++typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
++{
++  DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
++}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
++
++/****************************************************************************/
++// Structures used by DVOEncoderControlTable
++/****************************************************************************/
++//ucTableFormatRevision=1,ucTableContentRevision=3
++//ucDVOConfig:
++#define DVO_ENCODER_CONFIG_RATE_SEL                     0x01
++#define DVO_ENCODER_CONFIG_DDR_SPEED                  0x00
++#define DVO_ENCODER_CONFIG_SDR_SPEED                  0x01
++#define DVO_ENCODER_CONFIG_OUTPUT_SEL                  0x0c
++#define DVO_ENCODER_CONFIG_LOW12BIT                     0x00
++#define DVO_ENCODER_CONFIG_UPPER12BIT                  0x04
++#define DVO_ENCODER_CONFIG_24BIT                        0x08
++
++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
++{
++  USHORT usPixelClock;
++  UCHAR  ucDVOConfig;
++  UCHAR  ucAction;                                          //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
++  UCHAR  ucReseved[4];
++}DVO_ENCODER_CONTROL_PARAMETERS_V3;
++#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3   DVO_ENCODER_CONTROL_PARAMETERS_V3
++
++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
++{
++  USHORT usPixelClock;
++  UCHAR  ucDVOConfig;
++  UCHAR  ucAction;                                          //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
++  UCHAR  ucBitPerColor;                       //please refer to definition of PANEL_xBIT_PER_COLOR
++  UCHAR  ucReseved[3];
++}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
++#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4   DVO_ENCODER_CONTROL_PARAMETERS_V1_4
++
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
++// bit1=0: non-coherent mode
++//     =1: coherent mode
++
++//==========================================================================================
++//Only change is here next time when changing encoder parameter definitions again!
++#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
++
++#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
++
++#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
++
++#define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
++#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
++
++//==========================================================================================
++#define PANEL_ENCODER_MISC_DUAL                0x01
++#define PANEL_ENCODER_MISC_COHERENT            0x02
++#define   PANEL_ENCODER_MISC_TMDS_LINKB                0x04
++#define   PANEL_ENCODER_MISC_HDMI_TYPE                0x08
++
++#define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
++#define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
++#define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
++
++#define PANEL_ENCODER_TRUNCATE_EN              0x01
++#define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
++#define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
++#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
++#define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
++#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
++#define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
++#define PANEL_ENCODER_25FRC_MASK               0x10
++#define PANEL_ENCODER_25FRC_E                  0x00
++#define PANEL_ENCODER_25FRC_F                  0x10
++#define PANEL_ENCODER_50FRC_MASK               0x60
++#define PANEL_ENCODER_50FRC_A                  0x00
++#define PANEL_ENCODER_50FRC_B                  0x20
++#define PANEL_ENCODER_50FRC_C                  0x40
++#define PANEL_ENCODER_50FRC_D                  0x60
++#define PANEL_ENCODER_75FRC_MASK               0x80
++#define PANEL_ENCODER_75FRC_E                  0x00
++#define PANEL_ENCODER_75FRC_F                  0x80
++
++/****************************************************************************/
++// Structures used by SetVoltageTable
++/****************************************************************************/
++#define SET_VOLTAGE_TYPE_ASIC_VDDC             1
++#define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
++#define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
++#define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
++#define SET_VOLTAGE_INIT_MODE                  5
++#define SET_VOLTAGE_GET_MAX_VOLTAGE            6               //Gets the Max. voltage for the soldered Asic
++
++#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
++#define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
++#define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
++
++#define   SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
++#define   SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1
++#define   SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
++
++typedef struct   _SET_VOLTAGE_PARAMETERS
++{
++  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
++  UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
++  UCHAR    ucVoltageIndex;              // An index to tell which voltage level
++  UCHAR    ucReserved;
++}SET_VOLTAGE_PARAMETERS;
++
++typedef struct   _SET_VOLTAGE_PARAMETERS_V2
++{
++  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
++  UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
++  USHORT   usVoltageLevel;              // real voltage level
++}SET_VOLTAGE_PARAMETERS_V2;
++
++// used by both SetVoltageTable v1.3 and v1.4
++typedef struct   _SET_VOLTAGE_PARAMETERS_V1_3
++{
++  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
++  UCHAR    ucVoltageMode;               // Indicate action: Set voltage level
++  USHORT   usVoltageLevel;              // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
++}SET_VOLTAGE_PARAMETERS_V1_3;
++
++//ucVoltageType
++#define VOLTAGE_TYPE_VDDC                    1
++#define VOLTAGE_TYPE_MVDDC                   2
++#define VOLTAGE_TYPE_MVDDQ                   3
++#define VOLTAGE_TYPE_VDDCI                   4
++#define VOLTAGE_TYPE_VDDGFX                  5
++#define VOLTAGE_TYPE_PCC                     6
++
++#define VOLTAGE_TYPE_GENERIC_I2C_1           0x11
++#define VOLTAGE_TYPE_GENERIC_I2C_2           0x12
++#define VOLTAGE_TYPE_GENERIC_I2C_3           0x13
++#define VOLTAGE_TYPE_GENERIC_I2C_4           0x14
++#define VOLTAGE_TYPE_GENERIC_I2C_5           0x15
++#define VOLTAGE_TYPE_GENERIC_I2C_6           0x16
++#define VOLTAGE_TYPE_GENERIC_I2C_7           0x17
++#define VOLTAGE_TYPE_GENERIC_I2C_8           0x18
++#define VOLTAGE_TYPE_GENERIC_I2C_9           0x19
++#define VOLTAGE_TYPE_GENERIC_I2C_10          0x1A
++
++//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
++#define ATOM_SET_VOLTAGE                     0        //Set voltage Level
++#define ATOM_INIT_VOLTAGE_REGULATOR          3        //Init Regulator
++#define ATOM_SET_VOLTAGE_PHASE               4        //Set Vregulator Phase, only for SVID/PVID regulator
++#define ATOM_GET_MAX_VOLTAGE                 6        //Get Max Voltage, not used from SetVoltageTable v1.3
++#define ATOM_GET_VOLTAGE_LEVEL               6        //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
++#define ATOM_GET_LEAKAGE_ID                  8        //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
++
++// define vitual voltage id in usVoltageLevel
++#define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
++#define ATOM_VIRTUAL_VOLTAGE_ID1             0xff02
++#define ATOM_VIRTUAL_VOLTAGE_ID2             0xff03
++#define ATOM_VIRTUAL_VOLTAGE_ID3             0xff04
++#define ATOM_VIRTUAL_VOLTAGE_ID4             0xff05
++#define ATOM_VIRTUAL_VOLTAGE_ID5             0xff06
++#define ATOM_VIRTUAL_VOLTAGE_ID6             0xff07
++#define ATOM_VIRTUAL_VOLTAGE_ID7             0xff08
++
++typedef struct _SET_VOLTAGE_PS_ALLOCATION
++{
++  SET_VOLTAGE_PARAMETERS sASICSetVoltage;
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
++}SET_VOLTAGE_PS_ALLOCATION;
++
++// New Added from SI for GetVoltageInfoTable, input parameter structure
++typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
++{
++  UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
++  UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
++  USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
++  ULONG    ulReserved;
++}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
++
++// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
++typedef struct  _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
++{
++  ULONG    ulVotlageGpioState;
++  ULONG    ulVoltageGPioMask;
++}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
++
++// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
++typedef struct  _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
++{
++  USHORT   usVoltageLevel;
++  USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
++  ULONG    ulReseved;
++}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
++
++// GetVoltageInfo v1.1 ucVoltageMode
++#define ATOM_GET_VOLTAGE_VID                0x00
++#define ATOM_GET_VOTLAGE_INIT_SEQ           0x03
++#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID   0x04
++#define ATOM_GET_VOLTAGE_SVID2              0x07        //Get SVI2 Regulator Info
++
++// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
++#define   ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
++// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
++#define   ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
++
++#define   ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
++#define   ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
++
++
++// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
++typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
++{
++  UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
++  UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
++  USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
++  ULONG    ulSCLKFreq;                  // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
++}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
++
++// New in GetVoltageInfo v1.2 ucVoltageMode
++#define ATOM_GET_VOLTAGE_EVV_VOLTAGE        0x09
++
++// New Added from CI Hawaii for EVV feature
++typedef struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
++{
++  USHORT   usVoltageLevel;                               // real voltage level in unit of mv
++  USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
++  USHORT   usTDP_Current;                                // TDP_Current in unit of  0.01A
++  USHORT   usTDP_Power;                                  // TDP_Current in unit  of 0.1W
++}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
++
++/****************************************************************************/
++// Structures used by TVEncoderControlTable
++/****************************************************************************/
++typedef struct _TV_ENCODER_CONTROL_PARAMETERS
++{
++  USHORT usPixelClock;                // in 10KHz; for bios convenient
++  UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
++  UCHAR  ucAction;                    // 0: turn off encoder
++                                      // 1: setup and turn on encoder
++}TV_ENCODER_CONTROL_PARAMETERS;
++
++typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
++{
++  TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
++}TV_ENCODER_CONTROL_PS_ALLOCATION;
++
++//==============================Data Table Portion====================================
++
++
++/****************************************************************************/
++// Structure used in Data.mtb
++/****************************************************************************/
++typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
++{
++  USHORT        UtilityPipeLine;          // Offest for the utility to get parser info,Don't change this position!
++  USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
++  USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
++  USHORT        StandardVESA_Timing;      // Only used by Bios
++  USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
++  USHORT        PaletteData;              // Only used by BIOS
++  USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info
++  USHORT        DIGTransmitterInfo;       // Internal used by VBIOS only version 3.1
++  USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
++  USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
++  USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600
++  USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
++  USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
++  USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
++  USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
++  USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
++  USHORT        GPUVirtualizationInfo;    // Will be obsolete from R600
++  USHORT        SaveRestoreInfo;          // Only used by Bios
++  USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
++  USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
++  USHORT        XTMDS_Info;               // Will be obsolete from R600
++  USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
++  USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
++  USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
++  USHORT        MC_InitParameter;         // Only used by command table
++  USHORT        ASIC_VDDC_Info;           // Will be obsolete from R600
++  USHORT        ASIC_InternalSS_Info;     // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
++  USHORT        TV_VideoMode;             // Only used by command table
++  USHORT        VRAM_Info;                // Only used by command table, latest version 1.3
++  USHORT        MemoryTrainingInfo;       // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
++  USHORT        IntegratedSystemInfo;     // Shared by various SW components
++  USHORT        ASIC_ProfilingInfo;       // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
++  USHORT        VoltageObjectInfo;        // Shared by various SW components, latest version 1.1
++  USHORT        PowerSourceInfo;          // Shared by various SW components, latest versoin 1.1
++  USHORT	      ServiceInfo;
++}ATOM_MASTER_LIST_OF_DATA_TABLES;
++
++typedef struct _ATOM_MASTER_DATA_TABLE
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
++}ATOM_MASTER_DATA_TABLE;
++
++// For backward compatible
++#define LVDS_Info                LCD_Info
++#define DAC_Info                 PaletteData
++#define TMDS_Info                DIGTransmitterInfo
++#define CompassionateData        GPUVirtualizationInfo
++
++/****************************************************************************/
++// Structure used in MultimediaCapabilityInfoTable
++/****************************************************************************/
++typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ULONG                    ulSignature;      // HW info table signature string "$ATI"
++  UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
++  UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
++  UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
++  UCHAR                    ucHostPortInfo;   // Provides host port configuration information
++}ATOM_MULTIMEDIA_CAPABILITY_INFO;
++
++
++/****************************************************************************/
++// Structure used in MultimediaConfigInfoTable
++/****************************************************************************/
++typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ULONG                    ulSignature;      // MM info table signature sting "$MMT"
++  UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
++  UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
++  UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
++  UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
++  UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
++  UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
++  UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
++  UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
++  UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
++  UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
++  UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
++  UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
++}ATOM_MULTIMEDIA_CONFIG_INFO;
++
++
++/****************************************************************************/
++// Structures used in FirmwareInfoTable
++/****************************************************************************/
++
++// usBIOSCapability Defintion:
++// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
++// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
++// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
++// Others: Reserved
++#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
++#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
++#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
++#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008      // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
++#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010      // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
++#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
++#define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
++#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
++#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
++#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
++#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
++#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
++#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008      // (valid from v2.1 ): =1: memclk ss enable with external ss chip
++#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010      // (valid from v2.1 ): =1: engclk ss enable with external ss chip
++
++
++#ifndef _H2INC
++
++//Please don't add or expand this bitfield structure below, this one will retire soon.!
++typedef struct _ATOM_FIRMWARE_CAPABILITY
++{
++#if ATOM_BIG_ENDIAN
++  USHORT Reserved:1;
++  USHORT SCL2Redefined:1;
++  USHORT PostWithoutModeSet:1;
++  USHORT HyperMemory_Size:4;
++  USHORT HyperMemory_Support:1;
++  USHORT PPMode_Assigned:1;
++  USHORT WMI_SUPPORT:1;
++  USHORT GPUControlsBL:1;
++  USHORT EngineClockSS_Support:1;
++  USHORT MemoryClockSS_Support:1;
++  USHORT ExtendedDesktopSupport:1;
++  USHORT DualCRTC_Support:1;
++  USHORT FirmwarePosted:1;
++#else
++  USHORT FirmwarePosted:1;
++  USHORT DualCRTC_Support:1;
++  USHORT ExtendedDesktopSupport:1;
++  USHORT MemoryClockSS_Support:1;
++  USHORT EngineClockSS_Support:1;
++  USHORT GPUControlsBL:1;
++  USHORT WMI_SUPPORT:1;
++  USHORT PPMode_Assigned:1;
++  USHORT HyperMemory_Support:1;
++  USHORT HyperMemory_Size:4;
++  USHORT PostWithoutModeSet:1;
++  USHORT SCL2Redefined:1;
++  USHORT Reserved:1;
++#endif
++}ATOM_FIRMWARE_CAPABILITY;
++
++typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
++{
++  ATOM_FIRMWARE_CAPABILITY sbfAccess;
++  USHORT                   susAccess;
++}ATOM_FIRMWARE_CAPABILITY_ACCESS;
++
++#else
++
++typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
++{
++  USHORT                   susAccess;
++}ATOM_FIRMWARE_CAPABILITY_ACCESS;
++
++#endif
++
++typedef struct _ATOM_FIRMWARE_INFO
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulFirmwareRevision;
++  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
++  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
++  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
++  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
++  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
++  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
++  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
++  UCHAR                           ucASICMaxTemperature;
++  UCHAR                           ucPadding[3];               //Don't use them
++  ULONG                           aulReservedForBIOS[3];      //Don't use them
++  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
++  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
++  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
++  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
++  USHORT                          usReferenceClock;           //In 10Khz unit
++  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
++  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
++  UCHAR                           ucDesign_ID;                //Indicate what is the board design
++  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
++}ATOM_FIRMWARE_INFO;
++
++typedef struct _ATOM_FIRMWARE_INFO_V1_2
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulFirmwareRevision;
++  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
++  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
++  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
++  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
++  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
++  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
++  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
++  UCHAR                           ucASICMaxTemperature;
++  UCHAR                           ucMinAllowedBL_Level;
++  UCHAR                           ucPadding[2];               //Don't use them
++  ULONG                           aulReservedForBIOS[2];      //Don't use them
++  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
++  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
++  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
++  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
++  USHORT                          usReferenceClock;           //In 10Khz unit
++  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
++  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
++  UCHAR                           ucDesign_ID;                //Indicate what is the board design
++  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
++}ATOM_FIRMWARE_INFO_V1_2;
++
++typedef struct _ATOM_FIRMWARE_INFO_V1_3
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulFirmwareRevision;
++  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
++  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
++  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
++  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
++  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
++  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
++  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
++  UCHAR                           ucASICMaxTemperature;
++  UCHAR                           ucMinAllowedBL_Level;
++  UCHAR                           ucPadding[2];               //Don't use them
++  ULONG                           aulReservedForBIOS;         //Don't use them
++  ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
++  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
++  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
++  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
++  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
++  USHORT                          usReferenceClock;           //In 10Khz unit
++  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
++  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
++  UCHAR                           ucDesign_ID;                //Indicate what is the board design
++  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
++}ATOM_FIRMWARE_INFO_V1_3;
++
++typedef struct _ATOM_FIRMWARE_INFO_V1_4
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulFirmwareRevision;
++  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
++  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
++  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
++  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
++  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
++  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
++  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
++  UCHAR                           ucASICMaxTemperature;
++  UCHAR                           ucMinAllowedBL_Level;
++  USHORT                          usBootUpVDDCVoltage;        //In MV unit
++  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
++  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
++  ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
++  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
++  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
++  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
++  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
++  USHORT                          usReferenceClock;           //In 10Khz unit
++  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
++  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
++  UCHAR                           ucDesign_ID;                //Indicate what is the board design
++  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
++}ATOM_FIRMWARE_INFO_V1_4;
++
++//the structure below to be used from Cypress
++typedef struct _ATOM_FIRMWARE_INFO_V2_1
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulFirmwareRevision;
++  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
++  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
++  ULONG                           ulReserved1;
++  ULONG                           ulReserved2;
++  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
++  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
++  ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
++  ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
++  UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
++  UCHAR                           ucMinAllowedBL_Level;
++  USHORT                          usBootUpVDDCVoltage;        //In MV unit
++  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
++  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
++  ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
++  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
++  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
++  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
++  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
++  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
++  USHORT                          usCoreReferenceClock;       //In 10Khz unit
++  USHORT                          usMemoryReferenceClock;     //In 10Khz unit
++  USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
++  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
++  UCHAR                           ucReserved4[3];
++
++}ATOM_FIRMWARE_INFO_V2_1;
++
++//the structure below to be used from NI
++//ucTableFormatRevision=2
++//ucTableContentRevision=2
++
++typedef struct _PRODUCT_BRANDING
++{
++    UCHAR     ucEMBEDDED_CAP:2;          // Bit[1:0] Embedded feature level
++    UCHAR     ucReserved:2;              // Bit[3:2] Reserved
++    UCHAR     ucBRANDING_ID:4;           // Bit[7:4] Branding ID
++}PRODUCT_BRANDING;
++
++typedef struct _ATOM_FIRMWARE_INFO_V2_2
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulFirmwareRevision;
++  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
++  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
++  ULONG                           ulSPLL_OutputFreq;          //In 10Khz unit
++  ULONG                           ulGPUPLL_OutputFreq;        //In 10Khz unit
++  ULONG                           ulReserved1;                //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
++  ULONG                           ulReserved2;                //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
++  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
++  ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock  ?
++  ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
++  UCHAR                           ucReserved3;                //Was ucASICMaxTemperature;
++  UCHAR                           ucMinAllowedBL_Level;
++  USHORT                          usBootUpVDDCVoltage;        //In MV unit
++  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
++  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
++  ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
++  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
++  UCHAR                           ucRemoteDisplayConfig;
++  UCHAR                           ucReserved5[3];             //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
++  ULONG                           ulReserved6;                //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
++  ULONG                           ulReserved7;                //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
++  USHORT                          usReserved11;               //Was usMaxPixelClock;  //In 10Khz unit, Max.  Pclk used only for DAC
++  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
++  USHORT                          usBootUpVDDCIVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
++  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
++  USHORT                          usCoreReferenceClock;       //In 10Khz unit
++  USHORT                          usMemoryReferenceClock;     //In 10Khz unit
++  USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
++  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
++  UCHAR                           ucCoolingSolution_ID;       //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
++  PRODUCT_BRANDING                ucProductBranding;          // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level.
++  UCHAR                           ucReserved9;
++  USHORT                          usBootUpMVDDCVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
++  USHORT                          usBootUpVDDGFXVoltage;      //In unit of mv;
++  ULONG                           ulReserved10[3];            // New added comparing to previous version
++}ATOM_FIRMWARE_INFO_V2_2;
++
++#define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_2
++
++
++// definition of ucRemoteDisplayConfig
++#define REMOTE_DISPLAY_DISABLE                   0x00
++#define REMOTE_DISPLAY_ENABLE                    0x01
++
++/****************************************************************************/
++// Structures used in IntegratedSystemInfoTable
++/****************************************************************************/
++#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
++#define IGP_CAP_FLAG_AC_CARD               0x4
++#define IGP_CAP_FLAG_SDVO_CARD             0x8
++#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
++
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
++{
++  ATOM_COMMON_TABLE_HEADER        sHeader;
++  ULONG                           ulBootUpEngineClock;          //in 10kHz unit
++  ULONG                           ulBootUpMemoryClock;          //in 10kHz unit
++  ULONG                           ulMaxSystemMemoryClock;       //in 10kHz unit
++  ULONG                           ulMinSystemMemoryClock;       //in 10kHz unit
++  UCHAR                           ucNumberOfCyclesInPeriodHi;
++  UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
++  USHORT                          usReserved1;
++  USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage
++  USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage
++  ULONG                           ulReserved[2];
++
++  USHORT                          usFSBClock;                     //In MHz unit
++  USHORT                          usCapabilityFlag;              //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
++                                                                              //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
++                                                              //Bit[4]==1: P/2 mode, ==0: P/1 mode
++  USHORT                          usPCIENBCfgReg7;                //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
++  USHORT                          usK8MemoryClock;            //in MHz unit
++  USHORT                          usK8SyncStartDelay;         //in 0.01 us unit
++  USHORT                          usK8DataReturnTime;         //in 0.01 us unit
++  UCHAR                           ucMaxNBVoltage;
++  UCHAR                           ucMinNBVoltage;
++  UCHAR                           ucMemoryType;                     //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
++  UCHAR                           ucNumberOfCyclesInPeriod;      //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
++  UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
++  UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
++  UCHAR                           ucMaxNBVoltageHigh;
++  UCHAR                           ucMinNBVoltageHigh;
++}ATOM_INTEGRATED_SYSTEM_INFO;
++
++/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
++ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
++                        For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
++ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
++                        For AMD IGP,for now this can be 0
++ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
++                        For AMD IGP,for now this can be 0
++
++usFSBClock:             For Intel IGP,it's FSB Freq
++                        For AMD IGP,it's HT Link Speed
++
++usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
++usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
++usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
++
++VC:Voltage Control
++ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
++ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
++
++ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
++ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
++
++ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
++ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
++
++
++usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
++usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
++*/
++
++
++/*
++The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
++Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
++The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
++
++SW components can access the IGP system infor structure in the same way as before
++*/
++
++
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG                      ulBootUpEngineClock;       //in 10kHz unit
++  ULONG                      ulReserved1[2];            //must be 0x0 for the reserved
++  ULONG                      ulBootUpUMAClock;          //in 10kHz unit
++  ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
++  ULONG                      ulMinSidePortClock;        //in 10kHz unit
++  ULONG                      ulReserved2[6];            //must be 0x0 for the reserved
++  ULONG                      ulSystemConfig;            //see explanation below
++  ULONG                      ulBootUpReqDisplayVector;
++  ULONG                      ulOtherDisplayMisc;
++  ULONG                      ulDDISlot1Config;
++  ULONG                      ulDDISlot2Config;
++  UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
++  UCHAR                      ucUMAChannelNumber;
++  UCHAR                      ucDockingPinBit;
++  UCHAR                      ucDockingPinPolarity;
++  ULONG                      ulDockingPinCFGInfo;
++  ULONG                      ulCPUCapInfo;
++  USHORT                     usNumberOfCyclesInPeriod;
++  USHORT                     usMaxNBVoltage;
++  USHORT                     usMinNBVoltage;
++  USHORT                     usBootUpNBVoltage;
++  ULONG                      ulHTLinkFreq;              //in 10Khz
++  USHORT                     usMinHTLinkWidth;
++  USHORT                     usMaxHTLinkWidth;
++  USHORT                     usUMASyncStartDelay;
++  USHORT                     usUMADataReturnTime;
++  USHORT                     usLinkStatusZeroTime;
++  USHORT                     usDACEfuse;            //for storing badgap value (for RS880 only)
++  ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
++  ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
++  USHORT                     usMaxUpStreamHTLinkWidth;
++  USHORT                     usMaxDownStreamHTLinkWidth;
++  USHORT                     usMinUpStreamHTLinkWidth;
++  USHORT                     usMinDownStreamHTLinkWidth;
++  USHORT                     usFirmwareVersion;         //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
++  USHORT                     usFullT0Time;             // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
++  ULONG                      ulReserved3[96];          //must be 0x0
++}ATOM_INTEGRATED_SYSTEM_INFO_V2;
++
++/*
++ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
++ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
++ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
++
++ulSystemConfig:
++Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
++Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
++      =0: system boots up at driver control state. Power state depends on PowerPlay table.
++Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
++Bit[3]=1: Only one power state(Performance) will be supported.
++      =0: Multiple power states supported from PowerPlay table.
++Bit[4]=1: CLMC is supported and enabled on current system.
++      =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
++Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
++      =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
++Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
++      =0: Voltage settings is determined by powerplay table.
++Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
++      =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
++Bit[8]=1: CDLF is supported and enabled on current system.
++      =0: CDLF is not supported or enabled on current system.
++Bit[9]=1: DLL Shut Down feature is enabled on current system.
++      =0: DLL Shut Down feature is not enabled or supported on current system.
++
++ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
++
++ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
++                       [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
++
++ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
++      [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
++         [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
++      When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
++      in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
++      one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
++
++         [15:8] - Lane configuration attribute;
++      [23:16]- Connector type, possible value:
++               CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
++               CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
++               CONNECTOR_OBJECT_ID_HDMI_TYPE_A
++               CONNECTOR_OBJECT_ID_DISPLAYPORT
++               CONNECTOR_OBJECT_ID_eDP
++         [31:24]- Reserved
++
++ulDDISlot2Config: Same as Slot1.
++ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
++For IGP, Hypermemory is the only memory type showed in CCC.
++
++ucUMAChannelNumber:  how many channels for the UMA;
++
++ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
++ucDockingPinBit:     which bit in this register to read the pin status;
++ucDockingPinPolarity:Polarity of the pin when docked;
++
++ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
++
++usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
++
++usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
++usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
++                    GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
++                    PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
++                    GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
++
++usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
++
++
++ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
++usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
++                    If CDLW enabled, both upstream and downstream width should be the same during bootup.
++usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
++                    If CDLW enabled, both upstream and downstream width should be the same during bootup.
++
++usUMASyncStartDelay: Memory access latency, required for watermark calculation
++usUMADataReturnTime: Memory access latency, required for watermark calculation
++usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
++for Griffin or Greyhound. SBIOS needs to convert to actual time by:
++                     if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
++                     if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
++                     if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
++                     if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
++
++ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
++                             This must be less than or equal to ulHTLinkFreq(bootup frequency).
++ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
++                             This must be less than or equal to ulHighVoltageHTLinkFreq.
++
++usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
++usMaxDownStreamHTLinkWidth:  same as above.
++usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
++usMinDownStreamHTLinkWidth:  same as above.
++*/
++
++// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo  - CPU type definition
++#define    INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU             0
++#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN        1
++#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND      2
++#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__K8             3
++#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH        4
++#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI         5
++
++#define    INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE       INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI    // this deff reflects max defined CPU code
++
++#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
++#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
++#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004
++#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
++#define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
++#define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
++#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
++#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
++#define SYSTEM_CONFIG_CDLF_ENABLED                        0x00000100
++#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED                0x00000200
++
++#define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
++
++#define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
++#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
++#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
++#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
++#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
++#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
++
++#define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
++#define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
++#define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
++
++#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
++
++// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG                        ulBootUpEngineClock;       //in 10kHz unit
++  ULONG                      ulDentistVCOFreq;          //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
++  ULONG                      ulLClockFreq;              //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
++  ULONG                        ulBootUpUMAClock;          //in 10kHz unit
++  ULONG                      ulReserved1[8];            //must be 0x0 for the reserved
++  ULONG                      ulBootUpReqDisplayVector;
++  ULONG                      ulOtherDisplayMisc;
++  ULONG                      ulReserved2[4];            //must be 0x0 for the reserved
++  ULONG                      ulSystemConfig;            //TBD
++  ULONG                      ulCPUCapInfo;              //TBD
++  USHORT                     usMaxNBVoltage;            //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
++  USHORT                     usMinNBVoltage;            //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
++  USHORT                     usBootUpNBVoltage;         //boot up NB voltage
++  UCHAR                      ucHtcTmpLmt;               //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
++  UCHAR                      ucTjOffset;                //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
++  ULONG                      ulReserved3[4];            //must be 0x0 for the reserved
++  ULONG                      ulDDISlot1Config;          //see above ulDDISlot1Config definition
++  ULONG                      ulDDISlot2Config;
++  ULONG                      ulDDISlot3Config;
++  ULONG                      ulDDISlot4Config;
++  ULONG                      ulReserved4[4];            //must be 0x0 for the reserved
++  UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
++  UCHAR                      ucUMAChannelNumber;
++  USHORT                     usReserved;
++  ULONG                      ulReserved5[4];            //must be 0x0 for the reserved
++  ULONG                      ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
++  ULONG                      ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
++  ULONG                      ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
++  ULONG                      ulReserved6[61];           //must be 0x0
++}ATOM_INTEGRATED_SYSTEM_INFO_V5;
++
++
++
++/****************************************************************************/
++// Structure used in GPUVirtualizationInfoTable
++/****************************************************************************/
++typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG ulMCUcodeRomStartAddr;
++  ULONG ulMCUcodeLength;
++  ULONG ulSMCUcodeRomStartAddr;
++  ULONG ulSMCUcodeLength;
++  ULONG ulRLCVUcodeRomStartAddr;
++  ULONG ulRLCVUcodeLength;
++  ULONG ulTOCUcodeStartAddr;
++  ULONG ulTOCUcodeLength;
++  ULONG ulSMCPatchTableStartAddr;
++  ULONG ulSmcPatchTableLength;
++  ULONG ulSystemFlag;
++}ATOM_GPU_VIRTUALIZATION_INFO_V2_1;
++
++
++#define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
++#define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
++#define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
++#define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
++#define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
++#define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
++#define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
++#define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
++#define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
++#define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
++#define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
++#define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
++#define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
++#define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
++
++// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
++#define ASIC_INT_DAC1_ENCODER_ID                                     0x00
++#define ASIC_INT_TV_ENCODER_ID                                       0x02
++#define ASIC_INT_DIG1_ENCODER_ID                                     0x03
++#define ASIC_INT_DAC2_ENCODER_ID                                     0x04
++#define ASIC_EXT_TV_ENCODER_ID                                       0x06
++#define ASIC_INT_DVO_ENCODER_ID                                      0x07
++#define ASIC_INT_DIG2_ENCODER_ID                                     0x09
++#define ASIC_EXT_DIG_ENCODER_ID                                      0x05
++#define ASIC_EXT_DIG2_ENCODER_ID                                     0x08
++#define ASIC_INT_DIG3_ENCODER_ID                                     0x0a
++#define ASIC_INT_DIG4_ENCODER_ID                                     0x0b
++#define ASIC_INT_DIG5_ENCODER_ID                                     0x0c
++#define ASIC_INT_DIG6_ENCODER_ID                                     0x0d
++#define ASIC_INT_DIG7_ENCODER_ID                                     0x0e
++
++//define Encoder attribute
++#define ATOM_ANALOG_ENCODER                                                0
++#define ATOM_DIGITAL_ENCODER                                             1
++#define ATOM_DP_ENCODER                                                   2
++
++#define ATOM_ENCODER_ENUM_MASK                            0x70
++#define ATOM_ENCODER_ENUM_ID1                             0x00
++#define ATOM_ENCODER_ENUM_ID2                             0x10
++#define ATOM_ENCODER_ENUM_ID3                             0x20
++#define ATOM_ENCODER_ENUM_ID4                             0x30
++#define ATOM_ENCODER_ENUM_ID5                             0x40
++#define ATOM_ENCODER_ENUM_ID6                             0x50
++
++#define ATOM_DEVICE_CRT1_INDEX                            0x00000000
++#define ATOM_DEVICE_LCD1_INDEX                            0x00000001
++#define ATOM_DEVICE_TV1_INDEX                             0x00000002
++#define ATOM_DEVICE_DFP1_INDEX                            0x00000003
++#define ATOM_DEVICE_CRT2_INDEX                            0x00000004
++#define ATOM_DEVICE_LCD2_INDEX                            0x00000005
++#define ATOM_DEVICE_DFP6_INDEX                            0x00000006
++#define ATOM_DEVICE_DFP2_INDEX                            0x00000007
++#define ATOM_DEVICE_CV_INDEX                              0x00000008
++#define ATOM_DEVICE_DFP3_INDEX                            0x00000009
++#define ATOM_DEVICE_DFP4_INDEX                            0x0000000A
++#define ATOM_DEVICE_DFP5_INDEX                            0x0000000B
++
++#define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
++#define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
++#define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
++#define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
++#define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
++#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
++#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
++
++#define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
++
++#define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
++#define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
++#define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
++#define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX )
++#define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
++#define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
++#define ATOM_DEVICE_DFP6_SUPPORT                          (0x1L << ATOM_DEVICE_DFP6_INDEX )
++#define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX )
++#define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
++#define ATOM_DEVICE_DFP3_SUPPORT                          (0x1L << ATOM_DEVICE_DFP3_INDEX )
++#define ATOM_DEVICE_DFP4_SUPPORT                          (0x1L << ATOM_DEVICE_DFP4_INDEX )
++#define ATOM_DEVICE_DFP5_SUPPORT                          (0x1L << ATOM_DEVICE_DFP5_INDEX )
++
++
++#define ATOM_DEVICE_CRT_SUPPORT                           (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
++#define ATOM_DEVICE_DFP_SUPPORT                           (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
++#define ATOM_DEVICE_TV_SUPPORT                            ATOM_DEVICE_TV1_SUPPORT
++#define ATOM_DEVICE_LCD_SUPPORT                           (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
++
++#define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
++#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
++#define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
++#define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
++#define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
++#define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
++#define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
++#define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
++#define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
++#define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
++#define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
++#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
++#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
++#define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
++#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
++
++
++#define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
++#define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
++#define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
++#define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
++#define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
++#define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
++
++#define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
++
++#define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
++#define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
++
++#define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
++#define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
++#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
++#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
++#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
++#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
++
++#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
++#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
++#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
++#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
++
++//  usDeviceSupport:
++//  Bits0   = 0 - no CRT1 support= 1- CRT1 is supported
++//  Bit 1   = 0 - no LCD1 support= 1- LCD1 is supported
++//  Bit 2   = 0 - no TV1  support= 1- TV1  is supported
++//  Bit 3   = 0 - no DFP1 support= 1- DFP1 is supported
++//  Bit 4   = 0 - no CRT2 support= 1- CRT2 is supported
++//  Bit 5   = 0 - no LCD2 support= 1- LCD2 is supported
++//  Bit 6   = 0 - no DFP6 support= 1- DFP6 is supported
++//  Bit 7   = 0 - no DFP2 support= 1- DFP2 is supported
++//  Bit 8   = 0 - no CV   support= 1- CV   is supported
++//  Bit 9   = 0 - no DFP3 support= 1- DFP3 is supported
++//  Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
++//  Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
++//
++//
++
++/****************************************************************************/
++// Structure used in MclkSS_InfoTable
++/****************************************************************************/
++//      ucI2C_ConfigID
++//    [7:0] - I2C LINE Associate ID
++//          = 0   - no I2C
++//    [7]      -   HW_Cap        =   1,  [6:0]=HW assisted I2C ID(HW line selection)
++//                          =   0,  [6:0]=SW assisted I2C ID
++//    [6-4]   - HW_ENGINE_ID  =   1,  HW engine for NON multimedia use
++//                          =   2,   HW engine for Multimedia use
++//                          =   3-7   Reserved for future I2C engines
++//      [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
++
++typedef struct _ATOM_I2C_ID_CONFIG
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR   bfHW_Capable:1;
++  UCHAR   bfHW_EngineID:3;
++  UCHAR   bfI2C_LineMux:4;
++#else
++  UCHAR   bfI2C_LineMux:4;
++  UCHAR   bfHW_EngineID:3;
++  UCHAR   bfHW_Capable:1;
++#endif
++}ATOM_I2C_ID_CONFIG;
++
++typedef union _ATOM_I2C_ID_CONFIG_ACCESS
++{
++  ATOM_I2C_ID_CONFIG sbfAccess;
++  UCHAR              ucAccess;
++}ATOM_I2C_ID_CONFIG_ACCESS;
++
++
++/****************************************************************************/
++// Structure used in GPIO_I2C_InfoTable
++/****************************************************************************/
++typedef struct _ATOM_GPIO_I2C_ASSIGMENT
++{
++  USHORT                    usClkMaskRegisterIndex;
++  USHORT                    usClkEnRegisterIndex;
++  USHORT                    usClkY_RegisterIndex;
++  USHORT                    usClkA_RegisterIndex;
++  USHORT                    usDataMaskRegisterIndex;
++  USHORT                    usDataEnRegisterIndex;
++  USHORT                    usDataY_RegisterIndex;
++  USHORT                    usDataA_RegisterIndex;
++  ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
++  UCHAR                     ucClkMaskShift;
++  UCHAR                     ucClkEnShift;
++  UCHAR                     ucClkY_Shift;
++  UCHAR                     ucClkA_Shift;
++  UCHAR                     ucDataMaskShift;
++  UCHAR                     ucDataEnShift;
++  UCHAR                     ucDataY_Shift;
++  UCHAR                     ucDataA_Shift;
++  UCHAR                     ucReserved1;
++  UCHAR                     ucReserved2;
++}ATOM_GPIO_I2C_ASSIGMENT;
++
++typedef struct _ATOM_GPIO_I2C_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
++}ATOM_GPIO_I2C_INFO;
++
++/****************************************************************************/
++// Common Structure used in other structures
++/****************************************************************************/
++
++#ifndef _H2INC
++
++//Please don't add or expand this bitfield structure below, this one will retire soon.!
++typedef struct _ATOM_MODE_MISC_INFO
++{
++#if ATOM_BIG_ENDIAN
++  USHORT Reserved:6;
++  USHORT RGB888:1;
++  USHORT DoubleClock:1;
++  USHORT Interlace:1;
++  USHORT CompositeSync:1;
++  USHORT V_ReplicationBy2:1;
++  USHORT H_ReplicationBy2:1;
++  USHORT VerticalCutOff:1;
++  USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
++  USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
++  USHORT HorizontalCutOff:1;
++#else
++  USHORT HorizontalCutOff:1;
++  USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
++  USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
++  USHORT VerticalCutOff:1;
++  USHORT H_ReplicationBy2:1;
++  USHORT V_ReplicationBy2:1;
++  USHORT CompositeSync:1;
++  USHORT Interlace:1;
++  USHORT DoubleClock:1;
++  USHORT RGB888:1;
++  USHORT Reserved:6;
++#endif
++}ATOM_MODE_MISC_INFO;
++
++typedef union _ATOM_MODE_MISC_INFO_ACCESS
++{
++  ATOM_MODE_MISC_INFO sbfAccess;
++  USHORT              usAccess;
++}ATOM_MODE_MISC_INFO_ACCESS;
++
++#else
++
++typedef union _ATOM_MODE_MISC_INFO_ACCESS
++{
++  USHORT              usAccess;
++}ATOM_MODE_MISC_INFO_ACCESS;
++
++#endif
++
++// usModeMiscInfo-
++#define ATOM_H_CUTOFF           0x01
++#define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
++#define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
++#define ATOM_V_CUTOFF           0x08
++#define ATOM_H_REPLICATIONBY2   0x10
++#define ATOM_V_REPLICATIONBY2   0x20
++#define ATOM_COMPOSITESYNC      0x40
++#define ATOM_INTERLACE          0x80
++#define ATOM_DOUBLE_CLOCK_MODE  0x100
++#define ATOM_RGB888_MODE        0x200
++
++//usRefreshRate-
++#define ATOM_REFRESH_43         43
++#define ATOM_REFRESH_47         47
++#define ATOM_REFRESH_56         56
++#define ATOM_REFRESH_60         60
++#define ATOM_REFRESH_65         65
++#define ATOM_REFRESH_70         70
++#define ATOM_REFRESH_72         72
++#define ATOM_REFRESH_75         75
++#define ATOM_REFRESH_85         85
++
++// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
++// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
++//
++//   VESA_HTOTAL         =   VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
++//                  =   EDID_HA + EDID_HBL
++//   VESA_HDISP         =   VESA_ACTIVE   =   EDID_HA
++//   VESA_HSYNC_START   =   VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
++//                  =   EDID_HA + EDID_HSO
++//   VESA_HSYNC_WIDTH   =   VESA_HSYNC_TIME   =   EDID_HSPW
++//   VESA_BORDER         =   EDID_BORDER
++
++
++/****************************************************************************/
++// Structure used in SetCRTC_UsingDTDTimingTable
++/****************************************************************************/
++typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
++{
++  USHORT  usH_Size;
++  USHORT  usH_Blanking_Time;
++  USHORT  usV_Size;
++  USHORT  usV_Blanking_Time;
++  USHORT  usH_SyncOffset;
++  USHORT  usH_SyncWidth;
++  USHORT  usV_SyncOffset;
++  USHORT  usV_SyncWidth;
++  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
++  UCHAR   ucH_Border;         // From DFP EDID
++  UCHAR   ucV_Border;
++  UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR   ucPadding[3];
++}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
++
++/****************************************************************************/
++// Structure used in SetCRTC_TimingTable
++/****************************************************************************/
++typedef struct _SET_CRTC_TIMING_PARAMETERS
++{
++  USHORT                      usH_Total;        // horizontal total
++  USHORT                      usH_Disp;         // horizontal display
++  USHORT                      usH_SyncStart;    // horozontal Sync start
++  USHORT                      usH_SyncWidth;    // horizontal Sync width
++  USHORT                      usV_Total;        // vertical total
++  USHORT                      usV_Disp;         // vertical display
++  USHORT                      usV_SyncStart;    // vertical Sync start
++  USHORT                      usV_SyncWidth;    // vertical Sync width
++  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
++  UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
++  UCHAR                       ucOverscanRight;  // right
++  UCHAR                       ucOverscanLeft;   // left
++  UCHAR                       ucOverscanBottom; // bottom
++  UCHAR                       ucOverscanTop;    // top
++  UCHAR                       ucReserved;
++}SET_CRTC_TIMING_PARAMETERS;
++#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
++
++
++/****************************************************************************/
++// Structure used in StandardVESA_TimingTable
++//                   AnalogTV_InfoTable
++//                   ComponentVideoInfoTable
++/****************************************************************************/
++typedef struct _ATOM_MODE_TIMING
++{
++  USHORT  usCRTC_H_Total;
++  USHORT  usCRTC_H_Disp;
++  USHORT  usCRTC_H_SyncStart;
++  USHORT  usCRTC_H_SyncWidth;
++  USHORT  usCRTC_V_Total;
++  USHORT  usCRTC_V_Disp;
++  USHORT  usCRTC_V_SyncStart;
++  USHORT  usCRTC_V_SyncWidth;
++  USHORT  usPixelClock;                                //in 10Khz unit
++  ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
++  USHORT  usCRTC_OverscanRight;
++  USHORT  usCRTC_OverscanLeft;
++  USHORT  usCRTC_OverscanBottom;
++  USHORT  usCRTC_OverscanTop;
++  USHORT  usReserve;
++  UCHAR   ucInternalModeNumber;
++  UCHAR   ucRefreshRate;
++}ATOM_MODE_TIMING;
++
++typedef struct _ATOM_DTD_FORMAT
++{
++  USHORT  usPixClk;
++  USHORT  usHActive;
++  USHORT  usHBlanking_Time;
++  USHORT  usVActive;
++  USHORT  usVBlanking_Time;
++  USHORT  usHSyncOffset;
++  USHORT  usHSyncWidth;
++  USHORT  usVSyncOffset;
++  USHORT  usVSyncWidth;
++  USHORT  usImageHSize;
++  USHORT  usImageVSize;
++  UCHAR   ucHBorder;
++  UCHAR   ucVBorder;
++  ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
++  UCHAR   ucInternalModeNumber;
++  UCHAR   ucRefreshRate;
++}ATOM_DTD_FORMAT;
++
++/****************************************************************************/
++// Structure used in LVDS_InfoTable
++//  * Need a document to describe this table
++/****************************************************************************/
++#define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
++#define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
++#define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
++#define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
++#define SUPPORTED_LCD_REFRESHRATE_48Hz          0x0040
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=1
++typedef struct _ATOM_LVDS_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_DTD_FORMAT     sLCDTiming;
++  USHORT              usModePatchTableOffset;
++  USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
++  USHORT              usOffDelayInMs;
++  UCHAR               ucPowerSequenceDigOntoDEin10Ms;
++  UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
++  UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
++                                                 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
++                                                 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
++                                                 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
++  UCHAR               ucPanelDefaultRefreshRate;
++  UCHAR               ucPanelIdentification;
++  UCHAR               ucSS_Id;
++}ATOM_LVDS_INFO;
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=2
++typedef struct _ATOM_LVDS_INFO_V12
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_DTD_FORMAT     sLCDTiming;
++  USHORT              usExtInfoTableOffset;
++  USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
++  USHORT              usOffDelayInMs;
++  UCHAR               ucPowerSequenceDigOntoDEin10Ms;
++  UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
++  UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
++                                                 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
++                                                 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
++                                                 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
++  UCHAR               ucPanelDefaultRefreshRate;
++  UCHAR               ucPanelIdentification;
++  UCHAR               ucSS_Id;
++  USHORT              usLCDVenderID;
++  USHORT              usLCDProductID;
++  UCHAR               ucLCDPanel_SpecialHandlingCap;
++   UCHAR                        ucPanelInfoSize;               //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
++  UCHAR               ucReserved[2];
++}ATOM_LVDS_INFO_V12;
++
++//Definitions for ucLCDPanel_SpecialHandlingCap:
++
++//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
++//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
++#define   LCDPANEL_CAP_READ_EDID                  0x1
++
++//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
++//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
++//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
++#define   LCDPANEL_CAP_DRR_SUPPORTED              0x2
++
++//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
++#define   LCDPANEL_CAP_eDP                        0x4
++
++
++//Color Bit Depth definition in EDID V1.4 @BYTE 14h
++//Bit 6  5  4
++                              //      0  0  0  -  Color bit depth is undefined
++                              //      0  0  1  -  6 Bits per Primary Color
++                              //      0  1  0  -  8 Bits per Primary Color
++                              //      0  1  1  - 10 Bits per Primary Color
++                              //      1  0  0  - 12 Bits per Primary Color
++                              //      1  0  1  - 14 Bits per Primary Color
++                              //      1  1  0  - 16 Bits per Primary Color
++                              //      1  1  1  - Reserved
++
++#define PANEL_COLOR_BIT_DEPTH_MASK    0x70
++
++// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
++#define PANEL_RANDOM_DITHER   0x80
++#define PANEL_RANDOM_DITHER_MASK   0x80
++
++#define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12   // no need to change this
++
++
++typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT
++{
++    UCHAR ucSupportedRefreshRate;
++    UCHAR ucMinRefreshRateForDRR;
++}ATOM_LCD_REFRESH_RATE_SUPPORT;
++
++/****************************************************************************/
++// Structures used by LCD_InfoTable V1.3    Note: previous version was called ATOM_LVDS_INFO_V12
++// ASIC Families:  NI
++// ucTableFormatRevision=1
++// ucTableContentRevision=3
++/****************************************************************************/
++typedef struct _ATOM_LCD_INFO_V13
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_DTD_FORMAT     sLCDTiming;
++  USHORT              usExtInfoTableOffset;
++  union
++  {
++    USHORT            usSupportedRefreshRate;
++    ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport;
++  };
++  ULONG               ulReserved0;
++  UCHAR               ucLCD_Misc;                // Reorganized in V13
++                                                 // Bit0: {=0:single, =1:dual},
++                                                 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888}  // was {=0:666RGB, =1:888RGB},
++                                                 // Bit3:2: {Grey level}
++                                                 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
++                                                 // Bit7   Reserved.  was for ATOM_PANEL_MISC_API_ENABLED, still need it?
++  UCHAR               ucPanelDefaultRefreshRate;
++  UCHAR               ucPanelIdentification;
++  UCHAR               ucSS_Id;
++  USHORT              usLCDVenderID;
++  USHORT              usLCDProductID;
++  UCHAR               ucLCDPanel_SpecialHandlingCap;  // Reorganized in V13
++                                                 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
++                                                 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
++                                                 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
++                                                 // Bit7-3: Reserved
++  UCHAR               ucPanelInfoSize;                //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
++  USHORT              usBacklightPWM;            //  Backlight PWM in Hz. New in _V13
++
++  UCHAR               ucPowerSequenceDIGONtoDE_in4Ms;
++  UCHAR               ucPowerSequenceDEtoVARY_BL_in4Ms;
++  UCHAR               ucPowerSequenceVARY_BLtoDE_in4Ms;
++  UCHAR               ucPowerSequenceDEtoDIGON_in4Ms;
++
++  UCHAR               ucOffDelay_in4Ms;
++  UCHAR               ucPowerSequenceVARY_BLtoBLON_in4Ms;
++  UCHAR               ucPowerSequenceBLONtoVARY_BL_in4Ms;
++  UCHAR               ucReserved1;
++
++  UCHAR               ucDPCD_eDP_CONFIGURATION_CAP;     // dpcd 0dh
++  UCHAR               ucDPCD_MAX_LINK_RATE;             // dpcd 01h
++  UCHAR               ucDPCD_MAX_LANE_COUNT;            // dpcd 02h
++  UCHAR               ucDPCD_MAX_DOWNSPREAD;            // dpcd 03h
++
++  USHORT              usMaxPclkFreqInSingleLink;        // Max PixelClock frequency in single link mode.
++  UCHAR               uceDPToLVDSRxId;
++  UCHAR               ucLcdReservd;
++  ULONG               ulReserved[2];
++}ATOM_LCD_INFO_V13;
++
++#define ATOM_LCD_INFO_LAST  ATOM_LCD_INFO_V13
++
++//Definitions for ucLCD_Misc
++#define ATOM_PANEL_MISC_V13_DUAL                   0x00000001
++#define ATOM_PANEL_MISC_V13_FPDI                   0x00000002
++#define ATOM_PANEL_MISC_V13_GREY_LEVEL             0x0000000C
++#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT       2
++#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK   0x70
++#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR         0x10
++#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR         0x20
++
++//Color Bit Depth definition in EDID V1.4 @BYTE 14h
++//Bit 6  5  4
++                              //      0  0  0  -  Color bit depth is undefined
++                              //      0  0  1  -  6 Bits per Primary Color
++                              //      0  1  0  -  8 Bits per Primary Color
++                              //      0  1  1  - 10 Bits per Primary Color
++                              //      1  0  0  - 12 Bits per Primary Color
++                              //      1  0  1  - 14 Bits per Primary Color
++                              //      1  1  0  - 16 Bits per Primary Color
++                              //      1  1  1  - Reserved
++
++//Definitions for ucLCDPanel_SpecialHandlingCap:
++
++//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
++//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
++#define   LCDPANEL_CAP_V13_READ_EDID              0x1        // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
++
++//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
++//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
++//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
++#define   LCDPANEL_CAP_V13_DRR_SUPPORTED          0x2        // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
++
++//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
++#define   LCDPANEL_CAP_V13_eDP                    0x4        // = LCDPANEL_CAP_eDP no change comparing to previous version
++
++//uceDPToLVDSRxId
++#define eDP_TO_LVDS_RX_DISABLE                  0x00       // no eDP->LVDS translator chip
++#define eDP_TO_LVDS_COMMON_ID                   0x01       // common eDP->LVDS translator chip without AMD SW init
++#define eDP_TO_LVDS_RT_ID                       0x02       // RT tansaltor which require AMD SW init
++
++typedef struct  _ATOM_PATCH_RECORD_MODE
++{
++  UCHAR     ucRecordType;
++  USHORT    usHDisp;
++  USHORT    usVDisp;
++}ATOM_PATCH_RECORD_MODE;
++
++typedef struct  _ATOM_LCD_RTS_RECORD
++{
++  UCHAR     ucRecordType;
++  UCHAR     ucRTSValue;
++}ATOM_LCD_RTS_RECORD;
++
++//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
++// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
++typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
++{
++  UCHAR     ucRecordType;
++  USHORT    usLCDCap;
++}ATOM_LCD_MODE_CONTROL_CAP;
++
++#define LCD_MODE_CAP_BL_OFF                   1
++#define LCD_MODE_CAP_CRTC_OFF                 2
++#define LCD_MODE_CAP_PANEL_OFF                4
++
++
++typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
++{
++  UCHAR ucRecordType;
++  UCHAR ucFakeEDIDLength;       // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
++  UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
++} ATOM_FAKE_EDID_PATCH_RECORD;
++
++typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
++{
++   UCHAR    ucRecordType;
++   USHORT      usHSize;
++   USHORT      usVSize;
++}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
++
++#define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
++#define LCD_RTS_RECORD_TYPE                   2
++#define LCD_CAP_RECORD_TYPE                   3
++#define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
++#define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
++#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE     6
++#define ATOM_RECORD_END_TYPE                  0xFF
++
++/****************************Spread Spectrum Info Table Definitions **********************/
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=2
++typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
++{
++  USHORT              usSpreadSpectrumPercentage;
++  UCHAR               ucSpreadSpectrumType;       //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS  Others:TBD
++  UCHAR               ucSS_Step;
++  UCHAR               ucSS_Delay;
++  UCHAR               ucSS_Id;
++  UCHAR               ucRecommendedRef_Div;
++  UCHAR               ucSS_Range;               //it was reserved for V11
++}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
++
++#define ATOM_MAX_SS_ENTRY                      16
++#define ATOM_DP_SS_ID1                                     0x0f1         // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
++#define ATOM_DP_SS_ID2                                     0x0f2         // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
++#define ATOM_LVLINK_2700MHz_SS_ID              0x0f3      // SS ID for LV link translator chip at 2.7Ghz
++#define ATOM_LVLINK_1620MHz_SS_ID              0x0f4      // SS ID for LV link translator chip at 1.62Ghz
++
++
++
++#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
++#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
++#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
++#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
++#define ATOM_INTERNAL_SS_MASK                  0x00000000
++#define ATOM_EXTERNAL_SS_MASK                  0x00000002
++#define EXEC_SS_STEP_SIZE_SHIFT                2
++#define EXEC_SS_DELAY_SHIFT                    4
++#define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
++
++typedef struct _ATOM_SPREAD_SPECTRUM_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info[ATOM_MAX_SS_ENTRY];
++}ATOM_SPREAD_SPECTRUM_INFO;
++
++
++/****************************************************************************/
++// Structure used in AnalogTV_InfoTable (Top level)
++/****************************************************************************/
++//ucTVBootUpDefaultStd definiton:
++
++//ATOM_TV_NTSC                1
++//ATOM_TV_NTSCJ               2
++//ATOM_TV_PAL                 3
++//ATOM_TV_PALM                4
++//ATOM_TV_PALCN               5
++//ATOM_TV_PALN                6
++//ATOM_TV_PAL60               7
++//ATOM_TV_SECAM               8
++
++//ucTVSuppportedStd definition:
++#define NTSC_SUPPORT          0x1
++#define NTSCJ_SUPPORT         0x2
++
++#define PAL_SUPPORT           0x4
++#define PALM_SUPPORT          0x8
++#define PALCN_SUPPORT         0x10
++#define PALN_SUPPORT          0x20
++#define PAL60_SUPPORT         0x40
++#define SECAM_SUPPORT         0x80
++
++#define MAX_SUPPORTED_TV_TIMING    2
++
++typedef struct _ATOM_ANALOG_TV_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  UCHAR                    ucTV_SuppportedStandard;
++  UCHAR                    ucTV_BootUpDefaultStandard;
++  UCHAR                    ucExt_TV_ASIC_ID;
++  UCHAR                    ucExt_TV_ASIC_SlaveAddr;
++  ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];
++}ATOM_ANALOG_TV_INFO;
++
++typedef struct _ATOM_DPCD_INFO
++{
++  UCHAR   ucRevisionNumber;        //10h : Revision 1.0; 11h : Revision 1.1
++  UCHAR   ucMaxLinkRate;           //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
++  UCHAR   ucMaxLane;               //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
++  UCHAR   ucMaxDownSpread;         //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
++}ATOM_DPCD_INFO;
++
++#define ATOM_DPCD_MAX_LANE_MASK    0x1F
++
++/**************************************************************************/
++// VRAM usage and their defintions
++
++// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
++// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
++// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
++// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
++// To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
++
++// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU).
++//#ifndef VESA_MEMORY_IN_64K_BLOCK
++//#define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
++//#endif
++
++#define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
++#define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
++#define ATOM_HWICON_INFOTABLE_SIZE      32
++#define MAX_DTD_MODE_IN_VRAM            6
++#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT)
++#define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
++//20 bytes for Encoder Type and DPCD in STD EDID area
++#define DFP_ENCODER_TYPE_OFFSET         (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
++#define ATOM_DP_DPCD_OFFSET             (DFP_ENCODER_TYPE_OFFSET + 4 )
++
++#define ATOM_HWICON1_SURFACE_ADDR       0
++#define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
++#define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
++#define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
++#define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_CRT1_STD_MODE_TBL_ADDR       (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_LCD1_STD_MODE_TBL_ADDR      (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_DFP1_STD_MODE_TBL_ADDR       (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_CRT2_STD_MODE_TBL_ADDR       (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_LCD2_STD_MODE_TBL_ADDR      (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DFP6_EDID_ADDR             (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_DFP6_DTD_MODE_TBL_ADDR     (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_DFP6_STD_MODE_TBL_ADDR     (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DFP2_EDID_ADDR             (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++#define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
++#define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_DP_TRAINING_TBL_ADDR       (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
++
++#define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR + 1024)
++#define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START + 512
++
++//The size below is in Kb!
++#define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
++
++#define ATOM_VRAM_RESERVE_V2_SIZE      32
++
++#define   ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
++#define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
++#define   ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
++#define   ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
++
++/***********************************************************************************/
++// Structure used in VRAM_UsageByFirmwareTable
++// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
++//        at running time.
++// note2: From RV770, the memory is more than 32bit addressable, so we will change
++//        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
++//        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
++//        (in offset to start of memory address) is KB aligned instead of byte aligend.
++// Note3:
++/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged
++constant across VGA or non VGA adapter,
++for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can  have:
++
++If (ulStartAddrUsedByFirmware!=0)
++FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
++Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
++else   //Non VGA case
++ if (FB_Size<=2Gb)
++    FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
++ else
++     FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
++
++CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
++
++/***********************************************************************************/
++#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO         1
++
++typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
++{
++  ULONG   ulStartAddrUsedByFirmware;
++  USHORT  usFirmwareUseInKb;
++  USHORT  usReserved;
++}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
++
++typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_FIRMWARE_VRAM_RESERVE_INFO   asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
++}ATOM_VRAM_USAGE_BY_FIRMWARE;
++
++// change verion to 1.5, when allow driver to allocate the vram area for command table access.
++typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
++{
++  ULONG   ulStartAddrUsedByFirmware;
++  USHORT  usFirmwareUseInKb;
++  USHORT  usFBUsedByDrvInKb;
++}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
++
++typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5   asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
++}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
++
++/****************************************************************************/
++// Structure used in GPIO_Pin_LUTTable
++/****************************************************************************/
++typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
++{
++  USHORT                   usGpioPin_AIndex;
++  UCHAR                    ucGpioPinBitShift;
++  UCHAR                    ucGPIO_ID;
++}ATOM_GPIO_PIN_ASSIGNMENT;
++
++//ucGPIO_ID pre-define id for multiple usage
++// GPIO use to control PCIE_VDDC in certain SLT board
++#define PCIE_VDDC_CONTROL_GPIO_PINID        56
++
++//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable
++#define PP_AC_DC_SWITCH_GPIO_PINID          60
++//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
++#define VDDC_VRHOT_GPIO_PINID               61
++//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
++#define VDDC_PCC_GPIO_PINID                 62
++// Only used on certain SLT/PA board to allow utility to cut Efuse.
++#define EFUSE_CUT_ENABLE_GPIO_PINID         63
++// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses  for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO=
++#define DRAM_SELF_REFRESH_GPIO_PINID        64
++// Thermal interrupt output->system thermal chip GPIO pin
++#define THERMAL_INT_OUTPUT_GPIO_PINID       65
++
++
++typedef struct _ATOM_GPIO_PIN_LUT
++{
++  ATOM_COMMON_TABLE_HEADER  sHeader;
++  ATOM_GPIO_PIN_ASSIGNMENT   asGPIO_Pin[1];
++}ATOM_GPIO_PIN_LUT;
++
++/****************************************************************************/
++// Structure used in ComponentVideoInfoTable
++/****************************************************************************/
++#define GPIO_PIN_ACTIVE_HIGH          0x1
++#define MAX_SUPPORTED_CV_STANDARDS    5
++
++// definitions for ATOM_D_INFO.ucSettings
++#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
++#define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
++#define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
++
++typedef struct _ATOM_GPIO_INFO
++{
++  USHORT  usAOffset;
++  UCHAR   ucSettings;
++  UCHAR   ucReserved;
++}ATOM_GPIO_INFO;
++
++// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
++#define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
++
++// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
++#define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
++#define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
++
++// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
++//Line 3 out put 5V.
++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
++
++//Line 3 out put 2.2V
++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
++
++//Line 3 out put 0V
++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
++
++#define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
++
++#define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
++
++//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
++#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
++#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
++
++
++typedef struct _ATOM_COMPONENT_VIDEO_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT             usMask_PinRegisterIndex;
++  USHORT             usEN_PinRegisterIndex;
++  USHORT             usY_PinRegisterIndex;
++  USHORT             usA_PinRegisterIndex;
++  UCHAR              ucBitShift;
++  UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
++  ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
++  UCHAR              ucMiscInfo;
++  UCHAR              uc480i;
++  UCHAR              uc480p;
++  UCHAR              uc720p;
++  UCHAR              uc1080i;
++  UCHAR              ucLetterBoxMode;
++  UCHAR              ucReserved[3];
++  UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
++  ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
++  ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
++}ATOM_COMPONENT_VIDEO_INFO;
++
++//ucTableFormatRevision=2
++//ucTableContentRevision=1
++typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  UCHAR              ucMiscInfo;
++  UCHAR              uc480i;
++  UCHAR              uc480p;
++  UCHAR              uc720p;
++  UCHAR              uc1080i;
++  UCHAR              ucReserved;
++  UCHAR              ucLetterBoxMode;
++  UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
++  ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
++  ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
++}ATOM_COMPONENT_VIDEO_INFO_V21;
++
++#define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
++
++/****************************************************************************/
++// Structure used in object_InfoTable
++/****************************************************************************/
++typedef struct _ATOM_OBJECT_HEADER
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                    usDeviceSupport;
++  USHORT                    usConnectorObjectTableOffset;
++  USHORT                    usRouterObjectTableOffset;
++  USHORT                    usEncoderObjectTableOffset;
++  USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
++  USHORT                    usDisplayPathTableOffset;
++}ATOM_OBJECT_HEADER;
++
++typedef struct _ATOM_OBJECT_HEADER_V3
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                    usDeviceSupport;
++  USHORT                    usConnectorObjectTableOffset;
++  USHORT                    usRouterObjectTableOffset;
++  USHORT                    usEncoderObjectTableOffset;
++  USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
++  USHORT                    usDisplayPathTableOffset;
++  USHORT                    usMiscObjectTableOffset;
++}ATOM_OBJECT_HEADER_V3;
++
++
++typedef struct  _ATOM_DISPLAY_OBJECT_PATH
++{
++  USHORT    usDeviceTag;                                   //supported device
++  USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
++  USHORT    usConnObjectId;                                //Connector Object ID
++  USHORT    usGPUObjectId;                                 //GPU ID
++  USHORT    usGraphicObjIds[1];                            //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
++}ATOM_DISPLAY_OBJECT_PATH;
++
++typedef struct  _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
++{
++  USHORT    usDeviceTag;                                   //supported device
++  USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
++  USHORT    usConnObjectId;                                //Connector Object ID
++  USHORT    usGPUObjectId;                                 //GPU ID
++  USHORT    usGraphicObjIds[2];                            //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
++}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
++
++typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
++{
++  UCHAR                           ucNumOfDispPath;
++  UCHAR                           ucVersion;
++  UCHAR                           ucPadding[2];
++  ATOM_DISPLAY_OBJECT_PATH        asDispPath[1];
++}ATOM_DISPLAY_OBJECT_PATH_TABLE;
++
++typedef struct _ATOM_OBJECT                                //each object has this structure
++{
++  USHORT              usObjectID;
++  USHORT              usSrcDstTableOffset;
++  USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
++  USHORT              usReserved;
++}ATOM_OBJECT;
++
++typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure
++{
++  UCHAR               ucNumberOfObjects;
++  UCHAR               ucPadding[3];
++  ATOM_OBJECT         asObjects[1];
++}ATOM_OBJECT_TABLE;
++
++typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
++{
++  UCHAR               ucNumberOfSrc;
++  USHORT              usSrcObjectID[1];
++  UCHAR               ucNumberOfDst;
++  USHORT              usDstObjectID[1];
++}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
++
++
++//Two definitions below are for OPM on MXM module designs
++
++#define EXT_HPDPIN_LUTINDEX_0                   0
++#define EXT_HPDPIN_LUTINDEX_1                   1
++#define EXT_HPDPIN_LUTINDEX_2                   2
++#define EXT_HPDPIN_LUTINDEX_3                   3
++#define EXT_HPDPIN_LUTINDEX_4                   4
++#define EXT_HPDPIN_LUTINDEX_5                   5
++#define EXT_HPDPIN_LUTINDEX_6                   6
++#define EXT_HPDPIN_LUTINDEX_7                   7
++#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES   (EXT_HPDPIN_LUTINDEX_7+1)
++
++#define EXT_AUXDDC_LUTINDEX_0                   0
++#define EXT_AUXDDC_LUTINDEX_1                   1
++#define EXT_AUXDDC_LUTINDEX_2                   2
++#define EXT_AUXDDC_LUTINDEX_3                   3
++#define EXT_AUXDDC_LUTINDEX_4                   4
++#define EXT_AUXDDC_LUTINDEX_5                   5
++#define EXT_AUXDDC_LUTINDEX_6                   6
++#define EXT_AUXDDC_LUTINDEX_7                   7
++#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES   (EXT_AUXDDC_LUTINDEX_7+1)
++
++//ucChannelMapping are defined as following
++//for DP connector, eDP, DP to VGA/LVDS
++//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR ucDP_Lane3_Source:2;
++  UCHAR ucDP_Lane2_Source:2;
++  UCHAR ucDP_Lane1_Source:2;
++  UCHAR ucDP_Lane0_Source:2;
++#else
++  UCHAR ucDP_Lane0_Source:2;
++  UCHAR ucDP_Lane1_Source:2;
++  UCHAR ucDP_Lane2_Source:2;
++  UCHAR ucDP_Lane3_Source:2;
++#endif
++}ATOM_DP_CONN_CHANNEL_MAPPING;
++
++//for DVI/HDMI, in dual link case, both links have to have same mapping.
++//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
++typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR ucDVI_CLK_Source:2;
++  UCHAR ucDVI_DATA0_Source:2;
++  UCHAR ucDVI_DATA1_Source:2;
++  UCHAR ucDVI_DATA2_Source:2;
++#else
++  UCHAR ucDVI_DATA2_Source:2;
++  UCHAR ucDVI_DATA1_Source:2;
++  UCHAR ucDVI_DATA0_Source:2;
++  UCHAR ucDVI_CLK_Source:2;
++#endif
++}ATOM_DVI_CONN_CHANNEL_MAPPING;
++
++typedef struct _EXT_DISPLAY_PATH
++{
++  USHORT  usDeviceTag;                    //A bit vector to show what devices are supported
++  USHORT  usDeviceACPIEnum;               //16bit device ACPI id.
++  USHORT  usDeviceConnector;              //A physical connector for displays to plug in, using object connector definitions
++  UCHAR   ucExtAUXDDCLutIndex;            //An index into external AUX/DDC channel LUT
++  UCHAR   ucExtHPDPINLutIndex;            //An index into external HPD pin LUT
++  USHORT  usExtEncoderObjId;              //external encoder object id
++  union{
++    UCHAR   ucChannelMapping;                  // if ucChannelMapping=0, using default one to one mapping
++    ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
++    ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
++  };
++  UCHAR   ucChPNInvert;                   // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
++  USHORT  usCaps;
++  USHORT  usReserved;
++}EXT_DISPLAY_PATH;
++
++#define NUMBER_OF_UCHAR_FOR_GUID          16
++#define MAX_NUMBER_OF_EXT_DISPLAY_PATH    7
++
++//usCaps
++#define  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE               0x01
++#define  EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN             0x02
++#define  EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204          0x04
++#define  EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT     0x08
++
++typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  UCHAR                    ucGuid [NUMBER_OF_UCHAR_FOR_GUID];     // a GUID is a 16 byte long string
++  EXT_DISPLAY_PATH         sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
++  UCHAR                    ucChecksum;                            // a simple Checksum of the sum of whole structure equal to 0x0.
++  UCHAR                    uc3DStereoPinId;                       // use for eDP panel
++  UCHAR                    ucRemoteDisplayConfig;
++  UCHAR                    uceDPToLVDSRxId;
++  UCHAR                    ucFixDPVoltageSwing;                   // usCaps[1]=1, this indicate DP_LANE_SET value
++  UCHAR                    Reserved[3];                           // for potential expansion
++}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
++
++//Related definitions, all records are differnt but they have a commond header
++typedef struct _ATOM_COMMON_RECORD_HEADER
++{
++  UCHAR               ucRecordType;                      //An emun to indicate the record type
++  UCHAR               ucRecordSize;                      //The size of the whole record in byte
++}ATOM_COMMON_RECORD_HEADER;
++
++
++#define ATOM_I2C_RECORD_TYPE                           1
++#define ATOM_HPD_INT_RECORD_TYPE                       2
++#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
++#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
++#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE       5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
++#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
++#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
++#define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
++#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
++#define ATOM_ENCODER_DVO_CF_RECORD_TYPE                10
++#define ATOM_CONNECTOR_CF_RECORD_TYPE                  11
++#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE        12
++#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE   13
++#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE        14
++#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
++#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE          16 //This is for the case when connectors are not known to object table
++#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE          17 //This is for the case when connectors are not known to object table
++#define ATOM_OBJECT_LINK_RECORD_TYPE                   18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
++#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE          19
++#define ATOM_ENCODER_CAP_RECORD_TYPE                   20
++#define ATOM_BRACKET_LAYOUT_RECORD_TYPE                21
++
++
++//Must be updated when new record type is added,equal to that record definition!
++#define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_ENCODER_CAP_RECORD_TYPE
++
++typedef struct  _ATOM_I2C_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  ATOM_I2C_ID_CONFIG          sucI2cId;
++  UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
++}ATOM_I2C_RECORD;
++
++typedef struct  _ATOM_HPD_INT_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info
++  UCHAR                       ucPlugged_PinState;
++}ATOM_HPD_INT_RECORD;
++
++
++typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucProtectionFlag;
++  UCHAR                       ucReserved;
++}ATOM_OUTPUT_PROTECTION_RECORD;
++
++typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
++{
++  ULONG                       ulACPIDeviceEnum;       //Reserved for now
++  USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
++  USHORT                      usPadding;
++}ATOM_CONNECTOR_DEVICE_TAG;
++
++typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucNumberOfDevice;
++  UCHAR                       ucReserved;
++  ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
++}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
++
++
++typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                              ucConfigGPIOID;
++  UCHAR                              ucConfigGPIOState;       //Set to 1 when it's active high to enable external flow in
++  UCHAR                       ucFlowinGPIPID;
++  UCHAR                       ucExtInGPIPID;
++}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
++
++typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucCTL1GPIO_ID;
++  UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
++  UCHAR                       ucCTL2GPIO_ID;
++  UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
++  UCHAR                       ucCTL3GPIO_ID;
++  UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
++  UCHAR                       ucCTLFPGA_IN_ID;
++  UCHAR                       ucPadding[3];
++}ATOM_ENCODER_FPGA_CONTROL_RECORD;
++
++typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info
++  UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
++}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
++
++typedef struct  _ATOM_JTAG_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucTMSGPIO_ID;
++  UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
++  UCHAR                       ucTCKGPIO_ID;
++  UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
++  UCHAR                       ucTDOGPIO_ID;
++  UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
++  UCHAR                       ucTDIGPIO_ID;
++  UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
++  UCHAR                       ucPadding[2];
++}ATOM_JTAG_RECORD;
++
++
++//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
++typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
++{
++  UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
++  UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
++}ATOM_GPIO_PIN_CONTROL_PAIR;
++
++typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucFlags;                // Future expnadibility
++  UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
++  ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
++}ATOM_OBJECT_GPIO_CNTL_RECORD;
++
++//Definitions for GPIO pin state
++#define GPIO_PIN_TYPE_INPUT             0x00
++#define GPIO_PIN_TYPE_OUTPUT            0x10
++#define GPIO_PIN_TYPE_HW_CONTROL        0x20
++
++//For GPIO_PIN_TYPE_OUTPUT the following is defined
++#define GPIO_PIN_OUTPUT_STATE_MASK      0x01
++#define GPIO_PIN_OUTPUT_STATE_SHIFT     0
++#define GPIO_PIN_STATE_ACTIVE_LOW       0x0
++#define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
++
++// Indexes to GPIO array in GLSync record
++// GLSync record is for Frame Lock/Gen Lock feature.
++#define ATOM_GPIO_INDEX_GLSYNC_REFCLK    0
++#define ATOM_GPIO_INDEX_GLSYNC_HSYNC     1
++#define ATOM_GPIO_INDEX_GLSYNC_VSYNC     2
++#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  3
++#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  4
++#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
++#define ATOM_GPIO_INDEX_GLSYNC_V_RESET   6
++#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
++#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  8
++#define ATOM_GPIO_INDEX_GLSYNC_MAX       9
++
++typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  ULONG                       ulStrengthControl;      // DVOA strength control for CF
++  UCHAR                       ucPadding[2];
++}ATOM_ENCODER_DVO_CF_RECORD;
++
++// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
++#define ATOM_ENCODER_CAP_RECORD_HBR2                  0x01         // DP1.2 HBR2 is supported by HW encoder
++#define ATOM_ENCODER_CAP_RECORD_HBR2_EN               0x02         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
++#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          0x04         // HDMI2.0 6Gbps enable or not.
++
++typedef struct  _ATOM_ENCODER_CAP_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  union {
++    USHORT                    usEncoderCap;
++    struct {
++#if ATOM_BIG_ENDIAN
++      USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
++      USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
++      USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
++#else
++      USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
++      USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
++      USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
++#endif
++    };
++  };
++}ATOM_ENCODER_CAP_RECORD;
++
++// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
++#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
++#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
++
++typedef struct  _ATOM_CONNECTOR_CF_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  USHORT                      usMaxPixClk;
++  UCHAR                       ucFlowCntlGpioId;
++  UCHAR                       ucSwapCntlGpioId;
++  UCHAR                       ucConnectedDvoBundle;
++  UCHAR                       ucPadding;
++}ATOM_CONNECTOR_CF_RECORD;
++
++typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++   ATOM_DTD_FORMAT                     asTiming;
++}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
++
++typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
++  UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
++  UCHAR                       ucReserved;
++}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
++
++
++typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
++{
++   ATOM_COMMON_RECORD_HEADER   sheader;
++   UCHAR                                    ucMuxType;                     //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
++   UCHAR                                    ucMuxControlPin;
++   UCHAR                                    ucMuxState[2];               //for alligment purpose
++}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
++
++typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
++{
++   ATOM_COMMON_RECORD_HEADER   sheader;
++   UCHAR                                    ucMuxType;
++   UCHAR                                    ucMuxControlPin;
++   UCHAR                                    ucMuxState[2];               //for alligment purpose
++}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
++
++// define ucMuxType
++#define ATOM_ROUTER_MUX_PIN_STATE_MASK                        0x0f
++#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT      0x01
++
++typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES];  //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
++}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
++
++typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD  //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  ATOM_I2C_ID_CONFIG          ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES];  //An fixed size array which maps external pins to internal DDC ID
++}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
++
++typedef struct _ATOM_OBJECT_LINK_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  USHORT                      usObjectID;         //could be connector, encorder or other object in object.h
++}ATOM_OBJECT_LINK_RECORD;
++
++typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  USHORT                      usReserved;
++}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
++
++typedef struct  _ATOM_CONNECTOR_LAYOUT_INFO
++{
++   USHORT usConnectorObjectId;
++   UCHAR  ucConnectorType;
++   UCHAR  ucPosition;
++}ATOM_CONNECTOR_LAYOUT_INFO;
++
++// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
++#define CONNECTOR_TYPE_DVI_D                 1
++#define CONNECTOR_TYPE_DVI_I                 2
++#define CONNECTOR_TYPE_VGA                   3
++#define CONNECTOR_TYPE_HDMI                  4
++#define CONNECTOR_TYPE_DISPLAY_PORT          5
++#define CONNECTOR_TYPE_MINI_DISPLAY_PORT     6
++
++typedef struct  _ATOM_BRACKET_LAYOUT_RECORD
++{
++  ATOM_COMMON_RECORD_HEADER   sheader;
++  UCHAR                       ucLength;
++  UCHAR                       ucWidth;
++  UCHAR                       ucConnNum;
++  UCHAR                       ucReserved;
++  ATOM_CONNECTOR_LAYOUT_INFO  asConnInfo[1];
++}ATOM_BRACKET_LAYOUT_RECORD;
++
++
++/****************************************************************************/
++// Structure used in XXXX
++/****************************************************************************/
++typedef struct  _ATOM_VOLTAGE_INFO_HEADER
++{
++   USHORT   usVDDCBaseLevel;                //In number of 50mv unit
++   USHORT   usReserved;                     //For possible extension table offset
++   UCHAR    ucNumOfVoltageEntries;
++   UCHAR    ucBytesPerVoltageEntry;
++   UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
++   UCHAR    ucDefaultVoltageEntry;
++   UCHAR    ucVoltageControlI2cLine;
++   UCHAR    ucVoltageControlAddress;
++   UCHAR    ucVoltageControlOffset;
++}ATOM_VOLTAGE_INFO_HEADER;
++
++typedef struct  _ATOM_VOLTAGE_INFO
++{
++   ATOM_COMMON_TABLE_HEADER   sHeader;
++   ATOM_VOLTAGE_INFO_HEADER viHeader;
++   UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
++}ATOM_VOLTAGE_INFO;
++
++
++typedef struct  _ATOM_VOLTAGE_FORMULA
++{
++   USHORT   usVoltageBaseLevel;             // In number of 1mv unit
++   USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
++   UCHAR    ucNumOfVoltageEntries;          // Number of Voltage Entry, which indicate max Voltage
++   UCHAR    ucFlag;                         // bit0=0 :step is 1mv =1 0.5mv
++   UCHAR    ucBaseVID;                      // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
++   UCHAR    ucReserved;
++   UCHAR    ucVIDAdjustEntries[32];         // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
++}ATOM_VOLTAGE_FORMULA;
++
++typedef struct  _VOLTAGE_LUT_ENTRY
++{
++    USHORT     usVoltageCode;               // The Voltage ID, either GPIO or I2C code
++    USHORT     usVoltageValue;              // The corresponding Voltage Value, in mV
++}VOLTAGE_LUT_ENTRY;
++
++typedef struct  _ATOM_VOLTAGE_FORMULA_V2
++{
++    UCHAR      ucNumOfVoltageEntries;               // Number of Voltage Entry, which indicate max Voltage
++    UCHAR      ucReserved[3];
++    VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
++}ATOM_VOLTAGE_FORMULA_V2;
++
++typedef struct _ATOM_VOLTAGE_CONTROL
++{
++  UCHAR    ucVoltageControlId;                     //Indicate it is controlled by I2C or GPIO or HW state machine
++  UCHAR    ucVoltageControlI2cLine;
++  UCHAR    ucVoltageControlAddress;
++  UCHAR    ucVoltageControlOffset;
++  USHORT   usGpioPin_AIndex;                       //GPIO_PAD register index
++  UCHAR    ucGpioPinBitShift[9];                   //at most 8 pin support 255 VIDs, termintate with 0xff
++  UCHAR    ucReserved;
++}ATOM_VOLTAGE_CONTROL;
++
++// Define ucVoltageControlId
++#define VOLTAGE_CONTROLLED_BY_HW              0x00
++#define VOLTAGE_CONTROLLED_BY_I2C_MASK        0x7F
++#define VOLTAGE_CONTROLLED_BY_GPIO            0x80
++#define VOLTAGE_CONTROL_ID_LM64               0x01                           //I2C control, used for R5xx Core Voltage
++#define VOLTAGE_CONTROL_ID_DAC                0x02                           //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
++#define VOLTAGE_CONTROL_ID_VT116xM            0x03                           //I2C control, used for R6xx Core Voltage
++#define VOLTAGE_CONTROL_ID_DS4402             0x04
++#define VOLTAGE_CONTROL_ID_UP6266             0x05
++#define VOLTAGE_CONTROL_ID_SCORPIO            0x06
++#define VOLTAGE_CONTROL_ID_VT1556M            0x07
++#define VOLTAGE_CONTROL_ID_CHL822x            0x08
++#define VOLTAGE_CONTROL_ID_VT1586M            0x09
++#define VOLTAGE_CONTROL_ID_UP1637             0x0A
++#define VOLTAGE_CONTROL_ID_CHL8214            0x0B
++#define VOLTAGE_CONTROL_ID_UP1801             0x0C
++#define VOLTAGE_CONTROL_ID_ST6788A            0x0D
++#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2      0x0E
++#define VOLTAGE_CONTROL_ID_AD527x      	      0x0F
++#define VOLTAGE_CONTROL_ID_NCP81022    	      0x10
++#define VOLTAGE_CONTROL_ID_LTC2635			  0x11
++#define VOLTAGE_CONTROL_ID_NCP4208	          0x12
++#define VOLTAGE_CONTROL_ID_IR35xx             0x13
++#define VOLTAGE_CONTROL_ID_RT9403	          0x14
++
++#define VOLTAGE_CONTROL_ID_GENERIC_I2C        0x40
++
++typedef struct  _ATOM_VOLTAGE_OBJECT
++{
++   UCHAR      ucVoltageType;                           //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
++   UCHAR      ucSize;                                       //Size of Object
++   ATOM_VOLTAGE_CONTROL         asControl;         //describ how to control
++   ATOM_VOLTAGE_FORMULA         asFormula;         //Indicate How to convert real Voltage to VID
++}ATOM_VOLTAGE_OBJECT;
++
++typedef struct  _ATOM_VOLTAGE_OBJECT_V2
++{
++    UCHAR ucVoltageType;                      //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
++    UCHAR ucSize;                             //Size of Object
++    ATOM_VOLTAGE_CONTROL    asControl;        //describ how to control
++    ATOM_VOLTAGE_FORMULA_V2 asFormula;        //Indicate How to convert real Voltage to VID
++}ATOM_VOLTAGE_OBJECT_V2;
++
++typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
++{
++   ATOM_COMMON_TABLE_HEADER   sHeader;
++   ATOM_VOLTAGE_OBJECT        asVoltageObj[3];   //Info for Voltage control
++}ATOM_VOLTAGE_OBJECT_INFO;
++
++typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V2
++{
++   ATOM_COMMON_TABLE_HEADER   sHeader;
++    ATOM_VOLTAGE_OBJECT_V2    asVoltageObj[3];   //Info for Voltage control
++}ATOM_VOLTAGE_OBJECT_INFO_V2;
++
++typedef struct  _ATOM_LEAKID_VOLTAGE
++{
++   UCHAR    ucLeakageId;
++   UCHAR    ucReserved;
++   USHORT   usVoltage;
++}ATOM_LEAKID_VOLTAGE;
++
++typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
++   UCHAR    ucVoltageType;                            //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
++   UCHAR    ucVoltageMode;                            //Indicate voltage control mode: Init/Set/Leakage/Set phase
++   USHORT   usSize;                                   //Size of Object
++}ATOM_VOLTAGE_OBJECT_HEADER_V3;
++
++// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode
++#define VOLTAGE_OBJ_GPIO_LUT                 0        //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
++#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ          3        //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
++#define VOLTAGE_OBJ_PHASE_LUT                4        //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
++#define VOLTAGE_OBJ_SVID2                    7        //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
++#define VOLTAGE_OBJ_EVV                      8
++#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT     0x10     //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
++#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT   0x11     //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
++#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT  0x12     //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
++
++typedef struct  _VOLTAGE_LUT_ENTRY_V2
++{
++  ULONG   ulVoltageId;                       // The Voltage ID which is used to program GPIO register
++  USHORT  usVoltageValue;                    // The corresponding Voltage Value, in mV
++}VOLTAGE_LUT_ENTRY_V2;
++
++typedef struct  _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
++{
++  USHORT  usVoltageLevel;                    // The Voltage ID which is used to program GPIO register
++  USHORT  usVoltageId;
++  USHORT  usLeakageId;                       // The corresponding Voltage Value, in mV
++}LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
++
++
++typedef struct  _ATOM_I2C_VOLTAGE_OBJECT_V3
++{
++   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
++   UCHAR  ucVoltageRegulatorId;              //Indicate Voltage Regulator Id
++   UCHAR  ucVoltageControlI2cLine;
++   UCHAR  ucVoltageControlAddress;
++   UCHAR  ucVoltageControlOffset;
++   UCHAR  ucVoltageControlFlag;              // Bit0: 0 - One byte data; 1 - Two byte data
++   UCHAR  ulReserved[3];
++   VOLTAGE_LUT_ENTRY asVolI2cLut[1];         // end with 0xff
++}ATOM_I2C_VOLTAGE_OBJECT_V3;
++
++// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
++#define VOLTAGE_DATA_ONE_BYTE                0
++#define VOLTAGE_DATA_TWO_BYTE                1
++
++typedef struct  _ATOM_GPIO_VOLTAGE_OBJECT_V3
++{
++   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
++   UCHAR  ucVoltageGpioCntlId;               // default is 0 which indicate control through CG VID mode
++   UCHAR  ucGpioEntryNum;                    // indiate the entry numbers of Votlage/Gpio value Look up table
++   UCHAR  ucPhaseDelay;                      // phase delay in unit of micro second
++   UCHAR  ucReserved;
++   ULONG  ulGpioMaskVal;                     // GPIO Mask value
++   VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
++}ATOM_GPIO_VOLTAGE_OBJECT_V3;
++
++typedef struct  _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
++{
++   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = 0x10/0x11/0x12
++   UCHAR    ucLeakageCntlId;                 // default is 0
++   UCHAR    ucLeakageEntryNum;               // indicate the entry number of LeakageId/Voltage Lut table
++   UCHAR    ucReserved[2];
++   ULONG    ulMaxVoltageLevel;
++   LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
++}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
++
++
++typedef struct  _ATOM_SVID2_VOLTAGE_OBJECT_V3
++{
++   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_SVID2
++// 14:7 � PSI0_VID
++// 6 � PSI0_EN
++// 5 � PSI1
++// 4:2 � load line slope trim.
++// 1:0 � offset trim,
++   USHORT   usLoadLine_PSI;
++// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
++   UCHAR    ucSVDGpioId;     //0~31 indicate GPIO0~31
++   UCHAR    ucSVCGpioId;     //0~31 indicate GPIO0~31
++   ULONG    ulReserved;
++}ATOM_SVID2_VOLTAGE_OBJECT_V3;
++
++typedef union _ATOM_VOLTAGE_OBJECT_V3{
++  ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
++  ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
++  ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
++  ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
++}ATOM_VOLTAGE_OBJECT_V3;
++
++typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V3_1
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ATOM_VOLTAGE_OBJECT_V3     asVoltageObj[3];   //Info for Voltage control
++}ATOM_VOLTAGE_OBJECT_INFO_V3_1;
++
++
++typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
++{
++   UCHAR    ucProfileId;
++   UCHAR    ucReserved;
++   USHORT   usSize;
++   USHORT   usEfuseSpareStartAddr;
++   USHORT   usFuseIndex[8];                                    //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
++   ATOM_LEAKID_VOLTAGE               asLeakVol[2];         //Leakid and relatd voltage
++}ATOM_ASIC_PROFILE_VOLTAGE;
++
++//ucProfileId
++#define   ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                     1
++#define   ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE         1
++#define   ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE             2
++
++typedef struct  _ATOM_ASIC_PROFILING_INFO
++{
++  ATOM_COMMON_TABLE_HEADER         asHeader;
++  ATOM_ASIC_PROFILE_VOLTAGE        asVoltage;
++}ATOM_ASIC_PROFILING_INFO;
++
++typedef struct  _ATOM_ASIC_PROFILING_INFO_V2_1
++{
++  ATOM_COMMON_TABLE_HEADER         asHeader;
++  UCHAR  ucLeakageBinNum;                // indicate the entry number of LeakageId/Voltage Lut table
++  USHORT usLeakageBinArrayOffset;        // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
++
++  UCHAR  ucElbVDDC_Num;
++  USHORT usElbVDDC_IdArrayOffset;        // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
++  USHORT usElbVDDC_LevelArrayOffset;     // offset of 2 dimension voltage level USHORT array
++
++  UCHAR  ucElbVDDCI_Num;
++  USHORT usElbVDDCI_IdArrayOffset;       // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
++  USHORT usElbVDDCI_LevelArrayOffset;    // offset of 2 dimension voltage level USHORT array
++}ATOM_ASIC_PROFILING_INFO_V2_1;
++
++
++//Here is parameter to convert Efuse value to Measure value
++//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
++typedef struct _EFUSE_LOGISTIC_FUNC_PARAM
++{
++  USHORT usEfuseIndex;                  // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
++  UCHAR  ucEfuseBitLSB;                 // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
++  UCHAR  ucEfuseLength;                 // Efuse bits length,
++  ULONG  ulEfuseEncodeRange;            // Range = Max - Min, bit31 indicate the efuse is negative number
++  ULONG  ulEfuseEncodeAverage;          // Average = ( Max + Min )/2
++}EFUSE_LOGISTIC_FUNC_PARAM;
++
++//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
++typedef struct _EFUSE_LINEAR_FUNC_PARAM
++{
++  USHORT usEfuseIndex;                  // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
++  UCHAR  ucEfuseBitLSB;                 // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
++  UCHAR  ucEfuseLength;                 // Efuse bits length,
++  ULONG  ulEfuseEncodeRange;            // Range = Max - Min, bit31 indicate the efuse is negative number
++  ULONG  ulEfuseMin;                    // Min
++}EFUSE_LINEAR_FUNC_PARAM;
++
++
++typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_1
++{
++  ATOM_COMMON_TABLE_HEADER         asHeader;
++  ULONG  ulEvvDerateTdp;
++  ULONG  ulEvvDerateTdc;
++  ULONG  ulBoardCoreTemp;
++  ULONG  ulMaxVddc;
++  ULONG  ulMinVddc;
++  ULONG  ulLoadLineSlop;
++  ULONG  ulLeakageTemp;
++  ULONG  ulLeakageVoltage;
++  EFUSE_LINEAR_FUNC_PARAM sCACm;
++  EFUSE_LINEAR_FUNC_PARAM sCACb;
++  EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
++  EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
++  EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
++  USHORT usLkgEuseIndex;
++  UCHAR  ucLkgEfuseBitLSB;
++  UCHAR  ucLkgEfuseLength;
++  ULONG  ulLkgEncodeLn_MaxDivMin;
++  ULONG  ulLkgEncodeMax;
++  ULONG  ulLkgEncodeMin;
++  ULONG  ulEfuseLogisticAlpha;
++  USHORT usPowerDpm0;
++  USHORT usCurrentDpm0;
++  USHORT usPowerDpm1;
++  USHORT usCurrentDpm1;
++  USHORT usPowerDpm2;
++  USHORT usCurrentDpm2;
++  USHORT usPowerDpm3;
++  USHORT usCurrentDpm3;
++  USHORT usPowerDpm4;
++  USHORT usCurrentDpm4;
++  USHORT usPowerDpm5;
++  USHORT usCurrentDpm5;
++  USHORT usPowerDpm6;
++  USHORT usCurrentDpm6;
++  USHORT usPowerDpm7;
++  USHORT usCurrentDpm7;
++}ATOM_ASIC_PROFILING_INFO_V3_1;
++
++
++typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_2
++{
++  ATOM_COMMON_TABLE_HEADER         asHeader;
++  ULONG  ulEvvLkgFactor;
++  ULONG  ulBoardCoreTemp;
++  ULONG  ulMaxVddc;
++  ULONG  ulMinVddc;
++  ULONG  ulLoadLineSlop;
++  ULONG  ulLeakageTemp;
++  ULONG  ulLeakageVoltage;
++  EFUSE_LINEAR_FUNC_PARAM sCACm;
++  EFUSE_LINEAR_FUNC_PARAM sCACb;
++  EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
++  EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
++  EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
++  USHORT usLkgEuseIndex;
++  UCHAR  ucLkgEfuseBitLSB;
++  UCHAR  ucLkgEfuseLength;
++  ULONG  ulLkgEncodeLn_MaxDivMin;
++  ULONG  ulLkgEncodeMax;
++  ULONG  ulLkgEncodeMin;
++  ULONG  ulEfuseLogisticAlpha;
++  USHORT usPowerDpm0;
++  USHORT usPowerDpm1;
++  USHORT usPowerDpm2;
++  USHORT usPowerDpm3;
++  USHORT usPowerDpm4;
++  USHORT usPowerDpm5;
++  USHORT usPowerDpm6;
++  USHORT usPowerDpm7;
++  ULONG  ulTdpDerateDPM0;
++  ULONG  ulTdpDerateDPM1;
++  ULONG  ulTdpDerateDPM2;
++  ULONG  ulTdpDerateDPM3;
++  ULONG  ulTdpDerateDPM4;
++  ULONG  ulTdpDerateDPM5;
++  ULONG  ulTdpDerateDPM6;
++  ULONG  ulTdpDerateDPM7;
++}ATOM_ASIC_PROFILING_INFO_V3_2;
++
++
++// for Tonga/Fiji speed EVV algorithm
++typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_3
++{
++  ATOM_COMMON_TABLE_HEADER         asHeader;
++  ULONG  ulEvvLkgFactor;
++  ULONG  ulBoardCoreTemp;
++  ULONG  ulMaxVddc;
++  ULONG  ulMinVddc;
++  ULONG  ulLoadLineSlop;
++  ULONG  ulLeakageTemp;
++  ULONG  ulLeakageVoltage;
++  EFUSE_LINEAR_FUNC_PARAM sCACm;
++  EFUSE_LINEAR_FUNC_PARAM sCACb;
++  EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
++  EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
++  EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
++  USHORT usLkgEuseIndex;
++  UCHAR  ucLkgEfuseBitLSB;
++  UCHAR  ucLkgEfuseLength;
++  ULONG  ulLkgEncodeLn_MaxDivMin;
++  ULONG  ulLkgEncodeMax;
++  ULONG  ulLkgEncodeMin;
++  ULONG  ulEfuseLogisticAlpha;
++  USHORT usPowerDpm0;
++  USHORT usPowerDpm1;
++  USHORT usPowerDpm2;
++  USHORT usPowerDpm3;
++  USHORT usPowerDpm4;
++  USHORT usPowerDpm5;
++  USHORT usPowerDpm6;
++  USHORT usPowerDpm7;
++  ULONG  ulTdpDerateDPM0;
++  ULONG  ulTdpDerateDPM1;
++  ULONG  ulTdpDerateDPM2;
++  ULONG  ulTdpDerateDPM3;
++  ULONG  ulTdpDerateDPM4;
++  ULONG  ulTdpDerateDPM5;
++  ULONG  ulTdpDerateDPM6;
++  ULONG  ulTdpDerateDPM7;
++  EFUSE_LINEAR_FUNC_PARAM sRoFuse;
++  ULONG  ulRoAlpha;
++  ULONG  ulRoBeta;
++  ULONG  ulRoGamma;
++  ULONG  ulRoEpsilon;
++  ULONG  ulATermRo;
++  ULONG  ulBTermRo;
++  ULONG  ulCTermRo;
++  ULONG  ulSclkMargin;
++  ULONG  ulFmaxPercent;
++  ULONG  ulCRPercent;
++  ULONG  ulSFmaxPercent;
++  ULONG  ulSCRPercent;
++  ULONG  ulSDCMargine;
++}ATOM_ASIC_PROFILING_INFO_V3_3;
++
++typedef struct _ATOM_POWER_SOURCE_OBJECT
++{
++   UCHAR  ucPwrSrcId;                                   // Power source
++   UCHAR  ucPwrSensorType;                              // GPIO, I2C or none
++   UCHAR  ucPwrSensId;                                  // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
++   UCHAR  ucPwrSensSlaveAddr;                           // Slave address if I2C detect
++   UCHAR  ucPwrSensRegIndex;                            // I2C register Index if I2C detect
++   UCHAR  ucPwrSensRegBitMask;                          // detect which bit is used if I2C detect
++   UCHAR  ucPwrSensActiveState;                         // high active or low active
++   UCHAR  ucReserve[3];                                 // reserve
++   USHORT usSensPwr;                                    // in unit of watt
++}ATOM_POWER_SOURCE_OBJECT;
++
++typedef struct _ATOM_POWER_SOURCE_INFO
++{
++      ATOM_COMMON_TABLE_HEADER      asHeader;
++      UCHAR                                    asPwrbehave[16];
++      ATOM_POWER_SOURCE_OBJECT      asPwrObj[1];
++}ATOM_POWER_SOURCE_INFO;
++
++
++//Define ucPwrSrcId
++#define POWERSOURCE_PCIE_ID1                  0x00
++#define POWERSOURCE_6PIN_CONNECTOR_ID1   0x01
++#define POWERSOURCE_8PIN_CONNECTOR_ID1   0x02
++#define POWERSOURCE_6PIN_CONNECTOR_ID2   0x04
++#define POWERSOURCE_8PIN_CONNECTOR_ID2   0x08
++
++//define ucPwrSensorId
++#define POWER_SENSOR_ALWAYS                     0x00
++#define POWER_SENSOR_GPIO                        0x01
++#define POWER_SENSOR_I2C                        0x02
++
++typedef struct _ATOM_CLK_VOLT_CAPABILITY
++{
++  ULONG      ulVoltageIndex;                      // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
++  ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
++}ATOM_CLK_VOLT_CAPABILITY;
++
++
++typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2
++{
++  USHORT     usVoltageLevel;                      // The real Voltage Level round up value in unit of mv,
++  ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
++}ATOM_CLK_VOLT_CAPABILITY_V2;
++
++typedef struct _ATOM_AVAILABLE_SCLK_LIST
++{
++  ULONG      ulSupportedSCLK;               // Maximum clock supported with specified voltage index,  unit in 10kHz
++  USHORT     usVoltageIndex;                // The Voltage Index indicated by FUSE for specified SCLK
++  USHORT     usVoltageID;                   // The Voltage ID indicated by FUSE for specified SCLK
++}ATOM_AVAILABLE_SCLK_LIST;
++
++// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
++#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE             1       // refer to ulSystemConfig bit[0]
++
++// this IntegrateSystemInfoTable is used for Liano/Ontario APU
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG  ulBootUpEngineClock;
++  ULONG  ulDentistVCOFreq;
++  ULONG  ulBootUpUMAClock;
++  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
++  ULONG  ulBootUpReqDisplayVector;
++  ULONG  ulOtherDisplayMisc;
++  ULONG  ulGPUCapInfo;
++  ULONG  ulSB_MMIO_Base_Addr;
++  USHORT usRequestedPWMFreqInHz;
++  UCHAR  ucHtcTmpLmt;
++  UCHAR  ucHtcHystLmt;
++  ULONG  ulMinEngineClock;
++  ULONG  ulSystemConfig;
++  ULONG  ulCPUCapInfo;
++  USHORT usNBP0Voltage;
++  USHORT usNBP1Voltage;
++  USHORT usBootUpNBVoltage;
++  USHORT usExtDispConnInfoOffset;
++  USHORT usPanelRefreshRateRange;
++  UCHAR  ucMemoryType;
++  UCHAR  ucUMAChannelNumber;
++  ULONG  ulCSR_M3_ARB_CNTL_DEFAULT[10];
++  ULONG  ulCSR_M3_ARB_CNTL_UVD[10];
++  ULONG  ulCSR_M3_ARB_CNTL_FS3D[10];
++  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
++  ULONG  ulGMCRestoreResetTime;
++  ULONG  ulMinimumNClk;
++  ULONG  ulIdleNClk;
++  ULONG  ulDDR_DLL_PowerUpTime;
++  ULONG  ulDDR_PLL_PowerUpTime;
++  USHORT usPCIEClkSSPercentage;
++  USHORT usPCIEClkSSType;
++  USHORT usLvdsSSPercentage;
++  USHORT usLvdsSSpreadRateIn10Hz;
++  USHORT usHDMISSPercentage;
++  USHORT usHDMISSpreadRateIn10Hz;
++  USHORT usDVISSPercentage;
++  USHORT usDVISSpreadRateIn10Hz;
++  ULONG  SclkDpmBoostMargin;
++  ULONG  SclkDpmThrottleMargin;
++  USHORT SclkDpmTdpLimitPG;
++  USHORT SclkDpmTdpLimitBoost;
++  ULONG  ulBoostEngineCLock;
++  UCHAR  ulBoostVid_2bit;
++  UCHAR  EnableBoost;
++  USHORT GnbTdpLimit;
++  USHORT usMaxLVDSPclkFreqInSingleLink;
++  UCHAR  ucLvdsMisc;
++  UCHAR  ucLVDSReserved;
++  ULONG  ulReserved3[15];
++  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
++}ATOM_INTEGRATED_SYSTEM_INFO_V6;
++
++// ulGPUCapInfo
++#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE       0x01
++#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION          0x08
++
++//ucLVDSMisc:
++#define SYS_INFO_LVDSMISC__888_FPDI_MODE                                             0x01
++#define SYS_INFO_LVDSMISC__DL_CH_SWAP                                                0x02
++#define SYS_INFO_LVDSMISC__888_BPC                                                   0x04
++#define SYS_INFO_LVDSMISC__OVERRIDE_EN                                               0x08
++#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW                                           0x10
++// new since Trinity
++#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN                               0x20
++
++// not used any more
++#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW                                          0x04
++#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW                                          0x08
++
++/**********************************************************************************************************************
++  ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
++ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
++ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
++ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
++sDISPCLK_Voltage:                 Report Display clock voltage requirement.
++
++ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
++                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
++                                  ATOM_DEVICE_CRT2_SUPPORT                  0x0010
++                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008
++                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040
++                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080
++                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200
++                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400
++                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
++                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
++ulOtherDisplayMisc:                 Other display related flags, not defined yet.
++ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
++                                        =1: TMDS/HDMI Coherent Mode use signel PLL mode.
++                                  bit[3]=0: Enable HW AUX mode detection logic
++                                        =1: Disable HW AUX mode dettion logic
++ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
++
++usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
++                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
++
++                                  When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
++                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
++                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
++                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment;
++                                  and enabling VariBri under the driver environment from PP table is optional.
++
++                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
++                                  that BL control from GPU is expected.
++                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
++                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
++                                  it's per platform
++                                  and enabling VariBri under the driver environment from PP table is optional.
++
++ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
++                                  Threshold on value to enter HTC_active state.
++ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
++                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
++ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
++ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
++                                        =1: PCIE Power Gating Enabled
++                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
++                                         1: DDR-DLL shut-down feature enabled.
++                                  Bit[2]=0: DDR-PLL Power down feature disabled.
++                                         1: DDR-PLL Power down feature enabled.
++ulCPUCapInfo:                     TBD
++usNBP0Voltage:                    VID for voltage on NB P0 State
++usNBP1Voltage:                    VID for voltage on NB P1 State
++usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
++usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
++usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
++                                  to indicate a range.
++                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
++                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
++                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
++                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
++ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
++ucUMAChannelNumber:                 System memory channel numbers.
++ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
++ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
++ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
++sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
++ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
++ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
++ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
++ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
++ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
++usPCIEClkSSPercentage:            PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
++usPCIEClkSSType:                  PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
++usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
++usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
++usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
++usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
++usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
++usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
++usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
++ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
++                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
++                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
++                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
++                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
++**********************************************************************************************************************/
++
++// this Table is used for Liano/Ontario APU
++typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
++{
++  ATOM_INTEGRATED_SYSTEM_INFO_V6    sIntegratedSysInfo;
++  ULONG  ulPowerplayTable[128];
++}ATOM_FUSION_SYSTEM_INFO_V1;
++
++
++typedef struct _ATOM_TDP_CONFIG_BITS
++{
++#if ATOM_BIG_ENDIAN
++  ULONG   uReserved:2;
++  ULONG   uTDP_Value:14;  // Original TDP value in tens of milli watts
++  ULONG   uCTDP_Value:14; // Override value in tens of milli watts
++  ULONG   uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
++#else
++  ULONG   uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
++  ULONG   uCTDP_Value:14; // Override value in tens of milli watts
++  ULONG   uTDP_Value:14;  // Original TDP value in tens of milli watts
++  ULONG   uReserved:2;
++#endif
++}ATOM_TDP_CONFIG_BITS;
++
++typedef union _ATOM_TDP_CONFIG
++{
++  ATOM_TDP_CONFIG_BITS TDP_config;
++  ULONG            TDP_config_all;
++}ATOM_TDP_CONFIG;
++
++/**********************************************************************************************************************
++  ATOM_FUSION_SYSTEM_INFO_V1 Description
++sIntegratedSysInfo:               refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
++ulPowerplayTable[128]:            This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
++**********************************************************************************************************************/
++
++// this IntegrateSystemInfoTable is used for Trinity APU
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG  ulBootUpEngineClock;
++  ULONG  ulDentistVCOFreq;
++  ULONG  ulBootUpUMAClock;
++  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
++  ULONG  ulBootUpReqDisplayVector;
++  ULONG  ulOtherDisplayMisc;
++  ULONG  ulGPUCapInfo;
++  ULONG  ulSB_MMIO_Base_Addr;
++  USHORT usRequestedPWMFreqInHz;
++  UCHAR  ucHtcTmpLmt;
++  UCHAR  ucHtcHystLmt;
++  ULONG  ulMinEngineClock;
++  ULONG  ulSystemConfig;
++  ULONG  ulCPUCapInfo;
++  USHORT usNBP0Voltage;
++  USHORT usNBP1Voltage;
++  USHORT usBootUpNBVoltage;
++  USHORT usExtDispConnInfoOffset;
++  USHORT usPanelRefreshRateRange;
++  UCHAR  ucMemoryType;
++  UCHAR  ucUMAChannelNumber;
++  UCHAR  strVBIOSMsg[40];
++  ATOM_TDP_CONFIG  asTdpConfig;
++  ULONG  ulReserved[19];
++  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
++  ULONG  ulGMCRestoreResetTime;
++  ULONG  ulMinimumNClk;
++  ULONG  ulIdleNClk;
++  ULONG  ulDDR_DLL_PowerUpTime;
++  ULONG  ulDDR_PLL_PowerUpTime;
++  USHORT usPCIEClkSSPercentage;
++  USHORT usPCIEClkSSType;
++  USHORT usLvdsSSPercentage;
++  USHORT usLvdsSSpreadRateIn10Hz;
++  USHORT usHDMISSPercentage;
++  USHORT usHDMISSpreadRateIn10Hz;
++  USHORT usDVISSPercentage;
++  USHORT usDVISSpreadRateIn10Hz;
++  ULONG  SclkDpmBoostMargin;
++  ULONG  SclkDpmThrottleMargin;
++  USHORT SclkDpmTdpLimitPG;
++  USHORT SclkDpmTdpLimitBoost;
++  ULONG  ulBoostEngineCLock;
++  UCHAR  ulBoostVid_2bit;
++  UCHAR  EnableBoost;
++  USHORT GnbTdpLimit;
++  USHORT usMaxLVDSPclkFreqInSingleLink;
++  UCHAR  ucLvdsMisc;
++  UCHAR  ucTravisLVDSVolAdjust;
++  UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
++  UCHAR  ucLVDSOffToOnDelay_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
++  UCHAR  ucMinAllowedBL_Level;
++  ULONG  ulLCDBitDepthControlVal;
++  ULONG  ulNbpStateMemclkFreq[4];
++  USHORT usNBP2Voltage;
++  USHORT usNBP3Voltage;
++  ULONG  ulNbpStateNClkFreq[4];
++  UCHAR  ucNBDPMEnable;
++  UCHAR  ucReserved[3];
++  UCHAR  ucDPMState0VclkFid;
++  UCHAR  ucDPMState0DclkFid;
++  UCHAR  ucDPMState1VclkFid;
++  UCHAR  ucDPMState1DclkFid;
++  UCHAR  ucDPMState2VclkFid;
++  UCHAR  ucDPMState2DclkFid;
++  UCHAR  ucDPMState3VclkFid;
++  UCHAR  ucDPMState3DclkFid;
++  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
++}ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
++
++// ulOtherDisplayMisc
++#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT            0x01
++#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT  0x02
++#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT       0x04
++#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT                         0x08
++
++// ulGPUCapInfo
++#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
++#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
++#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
++#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
++//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
++#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
++
++//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML
++#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE                            0x00020000
++
++/**********************************************************************************************************************
++  ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
++ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
++ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
++ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
++sDISPCLK_Voltage:                 Report Display clock voltage requirement.
++
++ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
++                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
++                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008
++                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040
++                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080
++                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200
++                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400
++                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
++                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
++ulOtherDisplayMisc:                 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
++                                        =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
++                                  bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
++                                        =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
++                                  bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
++                                        =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
++                                  bit[3]=0: VBIOS fast boot is disable
++                                        =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
++ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
++                                        =1: TMDS/HDMI Coherent Mode use signel PLL mode.
++                                  bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
++                                        =1: DP mode use single PLL mode
++                                  bit[3]=0: Enable AUX HW mode detection logic
++                                        =1: Disable AUX HW mode detection logic
++
++ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
++
++usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
++                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
++
++                                  When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
++                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
++                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
++                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment;
++                                  and enabling VariBri under the driver environment from PP table is optional.
++
++                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
++                                  that BL control from GPU is expected.
++                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
++                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
++                                  it's per platform
++                                  and enabling VariBri under the driver environment from PP table is optional.
++
++ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
++                                  Threshold on value to enter HTC_active state.
++ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
++                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
++ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
++ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
++                                        =1: PCIE Power Gating Enabled
++                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
++                                         1: DDR-DLL shut-down feature enabled.
++                                  Bit[2]=0: DDR-PLL Power down feature disabled.
++                                         1: DDR-PLL Power down feature enabled.
++ulCPUCapInfo:                     TBD
++usNBP0Voltage:                    VID for voltage on NB P0 State
++usNBP1Voltage:                    VID for voltage on NB P1 State
++usNBP2Voltage:                    VID for voltage on NB P2 State
++usNBP3Voltage:                    VID for voltage on NB P3 State
++usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
++usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
++usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
++                                  to indicate a range.
++                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
++                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
++                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
++                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
++ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
++ucUMAChannelNumber:                 System memory channel numbers.
++ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
++ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
++ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
++sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
++ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
++ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
++ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
++ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
++ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
++usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
++usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
++usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
++usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
++usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
++usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
++usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
++usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
++usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
++ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
++                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
++                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
++                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
++                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
++                                  [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
++ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
++                                  value to program Travis register LVDS_CTRL_4
++ucLVDSPwrOnSeqDIGONtoDE_in4Ms:    LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
++                                  =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucLVDSPwrOnDEtoVARY_BL_in4Ms:     LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
++                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucLVDSPwrOffVARY_BLtoDE_in4Ms:    LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
++                                  =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucLVDSPwrOffDEtoDIGON_in4Ms:      LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
++                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
++                                  =0 means to use VBIOS default delay which is 125 ( 500ms ).
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
++                                  LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
++                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
++                                  LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
++                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
++
++ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB pstate.
++
++**********************************************************************************************************************/
++
++// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG  ulBootUpEngineClock;
++  ULONG  ulDentistVCOFreq;
++  ULONG  ulBootUpUMAClock;
++  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
++  ULONG  ulBootUpReqDisplayVector;
++  ULONG  ulVBIOSMisc;
++  ULONG  ulGPUCapInfo;
++  ULONG  ulDISP_CLK2Freq;
++  USHORT usRequestedPWMFreqInHz;
++  UCHAR  ucHtcTmpLmt;
++  UCHAR  ucHtcHystLmt;
++  ULONG  ulReserved2;
++  ULONG  ulSystemConfig;
++  ULONG  ulCPUCapInfo;
++  ULONG  ulReserved3;
++  USHORT usGPUReservedSysMemSize;
++  USHORT usExtDispConnInfoOffset;
++  USHORT usPanelRefreshRateRange;
++  UCHAR  ucMemoryType;
++  UCHAR  ucUMAChannelNumber;
++  UCHAR  strVBIOSMsg[40];
++  ATOM_TDP_CONFIG  asTdpConfig;
++  ULONG  ulReserved[19];
++  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
++  ULONG  ulGMCRestoreResetTime;
++  ULONG  ulReserved4;
++  ULONG  ulIdleNClk;
++  ULONG  ulDDR_DLL_PowerUpTime;
++  ULONG  ulDDR_PLL_PowerUpTime;
++  USHORT usPCIEClkSSPercentage;
++  USHORT usPCIEClkSSType;
++  USHORT usLvdsSSPercentage;
++  USHORT usLvdsSSpreadRateIn10Hz;
++  USHORT usHDMISSPercentage;
++  USHORT usHDMISSpreadRateIn10Hz;
++  USHORT usDVISSPercentage;
++  USHORT usDVISSpreadRateIn10Hz;
++  ULONG  ulGPUReservedSysMemBaseAddrLo;
++  ULONG  ulGPUReservedSysMemBaseAddrHi;
++  ATOM_CLK_VOLT_CAPABILITY   s5thDISPCLK_Voltage;
++  ULONG  ulReserved5;
++  USHORT usMaxLVDSPclkFreqInSingleLink;
++  UCHAR  ucLvdsMisc;
++  UCHAR  ucTravisLVDSVolAdjust;
++  UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
++  UCHAR  ucLVDSOffToOnDelay_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
++  UCHAR  ucMinAllowedBL_Level;
++  ULONG  ulLCDBitDepthControlVal;
++  ULONG  ulNbpStateMemclkFreq[4];
++  ULONG  ulPSPVersion;
++  ULONG  ulNbpStateNClkFreq[4];
++  USHORT usNBPStateVoltage[4];
++  USHORT usBootUpNBVoltage;
++  USHORT usReserved2;
++  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
++}ATOM_INTEGRATED_SYSTEM_INFO_V1_8;
++
++/**********************************************************************************************************************
++  ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description
++ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
++ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
++ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
++sDISPCLK_Voltage:                 Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
++
++ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
++                                  ATOM_DEVICE_CRT1_SUPPORT                  0x0001
++                                  ATOM_DEVICE_DFP1_SUPPORT                  0x0008
++                                  ATOM_DEVICE_DFP6_SUPPORT                  0x0040
++                                  ATOM_DEVICE_DFP2_SUPPORT                  0x0080
++                                  ATOM_DEVICE_DFP3_SUPPORT                  0x0200
++                                  ATOM_DEVICE_DFP4_SUPPORT                  0x0400
++                                  ATOM_DEVICE_DFP5_SUPPORT                  0x0800
++                                  ATOM_DEVICE_LCD1_SUPPORT                  0x0002
++
++ulVBIOSMisc:                       Miscellenous flags for VBIOS requirement and interface
++                                  bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
++                                        =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
++                                  bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
++                                        =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
++                                  bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
++                                        =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
++                                  bit[3]=0: VBIOS fast boot is disable
++                                        =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
++
++ulGPUCapInfo:                     bit[0~2]= Reserved
++                                  bit[3]=0: Enable AUX HW mode detection logic
++                                        =1: Disable AUX HW mode detection logic
++                                  bit[4]=0: Disable DFS bypass feature
++                                        =1: Enable DFS bypass feature
++
++usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
++                                  Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
++
++                                  When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
++                                  1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
++                                  VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
++                                  Changing BL using VBIOS function is functional in both driver and non-driver present environment;
++                                  and enabling VariBri under the driver environment from PP table is optional.
++
++                                  2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
++                                  that BL control from GPU is expected.
++                                  VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
++                                  Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
++                                  it's per platform
++                                  and enabling VariBri under the driver environment from PP table is optional.
++
++ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.
++ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
++                                  To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
++
++ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
++                                        =1: PCIE Power Gating Enabled
++                                  Bit[1]=0: DDR-DLL shut-down feature disabled.
++                                         1: DDR-DLL shut-down feature enabled.
++                                  Bit[2]=0: DDR-PLL Power down feature disabled.
++                                         1: DDR-PLL Power down feature enabled.
++                                  Bit[3]=0: GNB DPM is disabled
++                                        =1: GNB DPM is enabled
++ulCPUCapInfo:                     TBD
++
++usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
++usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
++                                  to indicate a range.
++                                  SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
++                                  SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
++                                  SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
++                                  SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
++
++ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
++ucUMAChannelNumber:                 System memory channel numbers.
++
++strVBIOSMsg[40]:                  VBIOS boot up customized message string
++
++sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
++
++ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
++ulIdleNClk:                       NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
++ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
++ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
++
++usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
++usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
++usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
++usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
++usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
++usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
++usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
++usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
++
++usGPUReservedSysMemSize:          Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.
++ulGPUReservedSysMemBaseAddrLo:    Low 32 bits base address to the reserved system memory.
++ulGPUReservedSysMemBaseAddrHi:    High 32 bits base address to the reserved system memory.
++
++usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
++ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
++                                  [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
++                                  [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
++                                  [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
++                                  [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
++                                  [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
++ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
++                                  value to program Travis register LVDS_CTRL_4
++ucLVDSPwrOnSeqDIGONtoDE_in4Ms:
++                                  LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
++                                  =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucLVDSPwrOnDEtoVARY_BL_in4Ms:
++                                  LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
++                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucLVDSPwrOffVARY_BLtoDE_in4Ms:
++                                  LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
++                                  =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucLVDSPwrOffDEtoDIGON_in4Ms:
++                                   LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
++                                  =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucLVDSOffToOnDelay_in4Ms:
++                                  LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
++                                  =0 means to use VBIOS default delay which is 125 ( 500ms ).
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
++                                  LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
++                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++
++ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
++                                  LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
++                                  =0 means to use VBIOS default delay which is 0 ( 0ms ).
++                                  This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
++ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
++
++ulLCDBitDepthControlVal:          GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
++
++ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
++ulNbpStateNClkFreq[4]:            NB P-State NClk frequency in different NB P-State
++usNBPStateVoltage[4]:             NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
++usBootUpNBVoltage:                NB P-State voltage during boot up before driver loaded
++sExtDispConnInfo:                 Display connector information table provided to VBIOS
++
++**********************************************************************************************************************/
++
++// this Table is used for Kaveri/Kabini APU
++typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
++{
++  ATOM_INTEGRATED_SYSTEM_INFO_V1_8    sIntegratedSysInfo;       // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
++  ULONG                               ulPowerplayTable[128];    // Update comments here to link new powerplay table definition structure
++}ATOM_FUSION_SYSTEM_INFO_V2;
++
++
++typedef struct _ATOM_I2C_REG_INFO
++{
++  UCHAR ucI2cRegIndex;
++  UCHAR ucI2cRegVal;
++}ATOM_I2C_REG_INFO;
++
++// this IntegrateSystemInfoTable is used for Carrizo
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG  ulBootUpEngineClock;
++  ULONG  ulDentistVCOFreq;
++  ULONG  ulBootUpUMAClock;
++  ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];       // no longer used, keep it as is to avoid driver compiling error
++  ULONG  ulBootUpReqDisplayVector;
++  ULONG  ulVBIOSMisc;
++  ULONG  ulGPUCapInfo;
++  ULONG  ulDISP_CLK2Freq;
++  USHORT usRequestedPWMFreqInHz;
++  UCHAR  ucHtcTmpLmt;
++  UCHAR  ucHtcHystLmt;
++  ULONG  ulReserved2;
++  ULONG  ulSystemConfig;
++  ULONG  ulCPUCapInfo;
++  ULONG  ulReserved3;
++  USHORT usGPUReservedSysMemSize;
++  USHORT usExtDispConnInfoOffset;
++  USHORT usPanelRefreshRateRange;
++  UCHAR  ucMemoryType;
++  UCHAR  ucUMAChannelNumber;
++  UCHAR  strVBIOSMsg[40];
++  ATOM_TDP_CONFIG  asTdpConfig;
++  UCHAR  ucExtHDMIReDrvSlvAddr;
++  UCHAR  ucExtHDMIReDrvRegNum;
++  ATOM_I2C_REG_INFO asExtHDMIRegSetting[9];
++  ULONG  ulReserved[2];
++  ATOM_CLK_VOLT_CAPABILITY_V2   sDispClkVoltageMapping[8];
++  ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];            // no longer used, keep it as is to avoid driver compiling error
++  ULONG  ulGMCRestoreResetTime;
++  ULONG  ulReserved4;
++  ULONG  ulIdleNClk;
++  ULONG  ulDDR_DLL_PowerUpTime;
++  ULONG  ulDDR_PLL_PowerUpTime;
++  USHORT usPCIEClkSSPercentage;
++  USHORT usPCIEClkSSType;
++  USHORT usLvdsSSPercentage;
++  USHORT usLvdsSSpreadRateIn10Hz;
++  USHORT usHDMISSPercentage;
++  USHORT usHDMISSpreadRateIn10Hz;
++  USHORT usDVISSPercentage;
++  USHORT usDVISSpreadRateIn10Hz;
++  ULONG  ulGPUReservedSysMemBaseAddrLo;
++  ULONG  ulGPUReservedSysMemBaseAddrHi;
++  ULONG  ulReserved5[3];
++  USHORT usMaxLVDSPclkFreqInSingleLink;
++  UCHAR  ucLvdsMisc;
++  UCHAR  ucTravisLVDSVolAdjust;
++  UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
++  UCHAR  ucLVDSOffToOnDelay_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
++  UCHAR  ucMinAllowedBL_Level;
++  ULONG  ulLCDBitDepthControlVal;
++  ULONG  ulNbpStateMemclkFreq[4];          // only 2 level is changed.
++  ULONG  ulPSPVersion;
++  ULONG  ulNbpStateNClkFreq[4];
++  USHORT usNBPStateVoltage[4];
++  USHORT usBootUpNBVoltage;
++  UCHAR  ucEDPv1_4VSMode;
++  UCHAR  ucReserved2;
++  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
++}ATOM_INTEGRATED_SYSTEM_INFO_V1_9;
++
++
++// definition for ucEDPv1_4VSMode
++#define EDP_VS_LEGACY_MODE                  0
++#define EDP_VS_LOW_VDIFF_MODE               1
++#define EDP_VS_HIGH_VDIFF_MODE              2
++#define EDP_VS_STRETCH_MODE                 3
++#define EDP_VS_SINGLE_VDIFF_MODE            4
++#define EDP_VS_VARIABLE_PREM_MODE           5
++
++
++// this IntegrateSystemInfoTable is used for Carrizo
++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ULONG  ulBootUpEngineClock;
++  ULONG  ulDentistVCOFreq;
++  ULONG  ulBootUpUMAClock;
++  ULONG  ulReserved0[8];
++  ULONG  ulBootUpReqDisplayVector;
++  ULONG  ulVBIOSMisc;
++  ULONG  ulGPUCapInfo;
++  ULONG  ulReserved1;
++  USHORT usRequestedPWMFreqInHz;
++  UCHAR  ucHtcTmpLmt;
++  UCHAR  ucHtcHystLmt;
++  ULONG  ulReserved2;
++  ULONG  ulSystemConfig;
++  ULONG  ulCPUCapInfo;
++  ULONG  ulReserved3;
++  USHORT usGPUReservedSysMemSize;
++  USHORT usExtDispConnInfoOffset;
++  USHORT usPanelRefreshRateRange;
++  UCHAR  ucMemoryType;
++  UCHAR  ucUMAChannelNumber;
++  UCHAR  strVBIOSMsg[40];
++  ATOM_TDP_CONFIG  asTdpConfig;
++  ULONG  ulReserved[7];
++  ATOM_CLK_VOLT_CAPABILITY_V2   sDispClkVoltageMapping[8];
++  ULONG  ulReserved6[10];
++  ULONG  ulGMCRestoreResetTime;
++  ULONG  ulReserved4;
++  ULONG  ulIdleNClk;
++  ULONG  ulDDR_DLL_PowerUpTime;
++  ULONG  ulDDR_PLL_PowerUpTime;
++  USHORT usPCIEClkSSPercentage;
++  USHORT usPCIEClkSSType;
++  USHORT usLvdsSSPercentage;
++  USHORT usLvdsSSpreadRateIn10Hz;
++  USHORT usHDMISSPercentage;
++  USHORT usHDMISSpreadRateIn10Hz;
++  USHORT usDVISSPercentage;
++  USHORT usDVISSpreadRateIn10Hz;
++  ULONG  ulGPUReservedSysMemBaseAddrLo;
++  ULONG  ulGPUReservedSysMemBaseAddrHi;
++  ULONG  ulReserved5[3];
++  USHORT usMaxLVDSPclkFreqInSingleLink;
++  UCHAR  ucLvdsMisc;
++  UCHAR  ucTravisLVDSVolAdjust;
++  UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
++  UCHAR  ucLVDSOffToOnDelay_in4Ms;
++  UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
++  UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
++  UCHAR  ucMinAllowedBL_Level;
++  ULONG  ulLCDBitDepthControlVal;
++  ULONG  ulNbpStateMemclkFreq[2];
++  ULONG  ulReserved7[2];
++  ULONG  ulPSPVersion;
++  ULONG  ulNbpStateNClkFreq[4];
++  USHORT usNBPStateVoltage[4];
++  USHORT usBootUpNBVoltage;
++  UCHAR  ucEDPv1_4VSMode;
++  UCHAR  ucReserved2;
++  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
++}ATOM_INTEGRATED_SYSTEM_INFO_V1_10;
++
++/**************************************************************************/
++// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
++//Memory SS Info Table
++//Define Memory Clock SS chip ID
++#define ICS91719  1
++#define ICS91720  2
++
++//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
++typedef struct _ATOM_I2C_DATA_RECORD
++{
++  UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
++  UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
++}ATOM_I2C_DATA_RECORD;
++
++
++//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
++typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
++{
++  ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
++  UCHAR                              ucSSChipID;             //SS chip being used
++  UCHAR                              ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
++  UCHAR                           ucNumOfI2CDataRecords;  //number of data block
++  ATOM_I2C_DATA_RECORD            asI2CData[1];
++}ATOM_I2C_DEVICE_SETUP_INFO;
++
++//==========================================================================================
++typedef struct  _ATOM_ASIC_MVDD_INFO
++{
++  ATOM_COMMON_TABLE_HEADER         sHeader;
++  ATOM_I2C_DEVICE_SETUP_INFO      asI2CSetup[1];
++}ATOM_ASIC_MVDD_INFO;
++
++//==========================================================================================
++#define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
++
++//==========================================================================================
++/**************************************************************************/
++
++typedef struct _ATOM_ASIC_SS_ASSIGNMENT
++{
++   ULONG                        ulTargetClockRange;                  //Clock Out frequence (VCO ), in unit of 10Khz
++  USHORT              usSpreadSpectrumPercentage;      //in unit of 0.01%
++   USHORT                     usSpreadRateInKhz;                  //in unit of kHz, modulation freq
++  UCHAR               ucClockIndication;                 //Indicate which clock source needs SS
++   UCHAR                        ucSpreadSpectrumMode;               //Bit1=0 Down Spread,=1 Center Spread.
++   UCHAR                        ucReserved[2];
++}ATOM_ASIC_SS_ASSIGNMENT;
++
++//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
++//SS is not required or enabled if a match is not found.
++#define ASIC_INTERNAL_MEMORY_SS            1
++#define ASIC_INTERNAL_ENGINE_SS            2
++#define ASIC_INTERNAL_UVD_SS             3
++#define ASIC_INTERNAL_SS_ON_TMDS         4
++#define ASIC_INTERNAL_SS_ON_HDMI         5
++#define ASIC_INTERNAL_SS_ON_LVDS         6
++#define ASIC_INTERNAL_SS_ON_DP           7
++#define ASIC_INTERNAL_SS_ON_DCPLL        8
++#define ASIC_EXTERNAL_SS_ON_DP_CLOCK     9
++#define ASIC_INTERNAL_VCE_SS             10
++#define ASIC_INTERNAL_GPUPLL_SS          11
++
++
++typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
++{
++   ULONG                        ulTargetClockRange;                  //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
++                                                    //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
++  USHORT              usSpreadSpectrumPercentage;      //in unit of 0.01%
++   USHORT                     usSpreadRateIn10Hz;                  //in unit of 10Hz, modulation freq
++  UCHAR               ucClockIndication;                 //Indicate which clock source needs SS
++   UCHAR                        ucSpreadSpectrumMode;               //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
++   UCHAR                        ucReserved[2];
++}ATOM_ASIC_SS_ASSIGNMENT_V2;
++
++//ucSpreadSpectrumMode
++//#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
++//#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
++//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
++//#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
++//#define ATOM_INTERNAL_SS_MASK                  0x00000000
++//#define ATOM_EXTERNAL_SS_MASK                  0x00000002
++
++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
++{
++  ATOM_COMMON_TABLE_HEADER         sHeader;
++  ATOM_ASIC_SS_ASSIGNMENT            asSpreadSpectrum[4];
++}ATOM_ASIC_INTERNAL_SS_INFO;
++
++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
++{
++  ATOM_COMMON_TABLE_HEADER         sHeader;
++  ATOM_ASIC_SS_ASSIGNMENT_V2        asSpreadSpectrum[1];      //this is point only.
++}ATOM_ASIC_INTERNAL_SS_INFO_V2;
++
++typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
++{
++   ULONG                        ulTargetClockRange;                  //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
++                                                    //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
++  USHORT              usSpreadSpectrumPercentage;      //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
++   USHORT                     usSpreadRateIn10Hz;                  //in unit of 10Hz, modulation freq
++  UCHAR               ucClockIndication;                 //Indicate which clock source needs SS
++   UCHAR                        ucSpreadSpectrumMode;               //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
++   UCHAR                        ucReserved[2];
++}ATOM_ASIC_SS_ASSIGNMENT_V3;
++
++//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode
++#define SS_MODE_V3_CENTRE_SPREAD_MASK             0x01
++#define SS_MODE_V3_EXTERNAL_SS_MASK               0x02
++#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK    0x10
++
++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
++{
++  ATOM_COMMON_TABLE_HEADER         sHeader;
++  ATOM_ASIC_SS_ASSIGNMENT_V3        asSpreadSpectrum[1];      //this is pointer only.
++}ATOM_ASIC_INTERNAL_SS_INFO_V3;
++
++
++//==============================Scratch Pad Definition Portion===============================
++#define ATOM_DEVICE_CONNECT_INFO_DEF  0
++#define ATOM_ROM_LOCATION_DEF         1
++#define ATOM_TV_STANDARD_DEF          2
++#define ATOM_ACTIVE_INFO_DEF          3
++#define ATOM_LCD_INFO_DEF             4
++#define ATOM_DOS_REQ_INFO_DEF         5
++#define ATOM_ACC_CHANGE_INFO_DEF      6
++#define ATOM_DOS_MODE_INFO_DEF        7
++#define ATOM_I2C_CHANNEL_STATUS_DEF   8
++#define ATOM_I2C_CHANNEL_STATUS1_DEF  9
++#define ATOM_INTERNAL_TIMER_DEF       10
++
++// BIOS_0_SCRATCH Definition
++#define ATOM_S0_CRT1_MONO               0x00000001L
++#define ATOM_S0_CRT1_COLOR              0x00000002L
++#define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
++
++#define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
++#define ATOM_S0_TV1_SVIDEO_A            0x00000008L
++#define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
++
++#define ATOM_S0_CV_A                    0x00000010L
++#define ATOM_S0_CV_DIN_A                0x00000020L
++#define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
++
++
++#define ATOM_S0_CRT2_MONO               0x00000100L
++#define ATOM_S0_CRT2_COLOR              0x00000200L
++#define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
++
++#define ATOM_S0_TV1_COMPOSITE           0x00000400L
++#define ATOM_S0_TV1_SVIDEO              0x00000800L
++#define ATOM_S0_TV1_SCART               0x00004000L
++#define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
++
++#define ATOM_S0_CV                      0x00001000L
++#define ATOM_S0_CV_DIN                  0x00002000L
++#define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
++
++#define ATOM_S0_DFP1                    0x00010000L
++#define ATOM_S0_DFP2                    0x00020000L
++#define ATOM_S0_LCD1                    0x00040000L
++#define ATOM_S0_LCD2                    0x00080000L
++#define ATOM_S0_DFP6                    0x00100000L
++#define ATOM_S0_DFP3                    0x00200000L
++#define ATOM_S0_DFP4                    0x00400000L
++#define ATOM_S0_DFP5                    0x00800000L
++
++
++#define ATOM_S0_DFP_MASK                ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
++
++#define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with
++                                                    // the FAD/HDP reg access bug.  Bit is read by DAL, this is obsolete from RV5xx
++
++#define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
++#define ATOM_S0_THERMAL_STATE_SHIFT     26
++
++#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
++#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
++
++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
++
++//Byte aligned defintion for BIOS usage
++#define ATOM_S0_CRT1_MONOb0             0x01
++#define ATOM_S0_CRT1_COLORb0            0x02
++#define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
++
++#define ATOM_S0_TV1_COMPOSITEb0         0x04
++#define ATOM_S0_TV1_SVIDEOb0            0x08
++#define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
++
++#define ATOM_S0_CVb0                    0x10
++#define ATOM_S0_CV_DINb0                0x20
++#define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
++
++#define ATOM_S0_CRT2_MONOb1             0x01
++#define ATOM_S0_CRT2_COLORb1            0x02
++#define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
++
++#define ATOM_S0_TV1_COMPOSITEb1         0x04
++#define ATOM_S0_TV1_SVIDEOb1            0x08
++#define ATOM_S0_TV1_SCARTb1             0x40
++#define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
++
++#define ATOM_S0_CVb1                    0x10
++#define ATOM_S0_CV_DINb1                0x20
++#define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
++
++#define ATOM_S0_DFP1b2                  0x01
++#define ATOM_S0_DFP2b2                  0x02
++#define ATOM_S0_LCD1b2                  0x04
++#define ATOM_S0_LCD2b2                  0x08
++#define ATOM_S0_DFP6b2                  0x10
++#define ATOM_S0_DFP3b2                  0x20
++#define ATOM_S0_DFP4b2                  0x40
++#define ATOM_S0_DFP5b2                  0x80
++
++
++#define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
++#define ATOM_S0_THERMAL_STATE_SHIFTb3   2
++
++#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
++#define ATOM_S0_LCD1_SHIFT              18
++
++// BIOS_1_SCRATCH Definition
++#define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
++#define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
++
++//   BIOS_2_SCRATCH Definition
++#define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
++#define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
++#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
++
++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
++
++#define ATOM_S2_DEVICE_DPMS_STATE       0x00010000L
++#define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
++
++#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
++#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
++#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
++#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
++#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
++#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
++
++
++//Byte aligned defintion for BIOS usage
++#define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
++#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
++#define ATOM_S2_DEVICE_DPMS_STATEb2     0x01
++
++#define ATOM_S2_TMDS_COHERENT_MODEb3    0x10          // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
++#define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
++#define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
++
++
++// BIOS_3_SCRATCH Definition
++#define ATOM_S3_CRT1_ACTIVE             0x00000001L
++#define ATOM_S3_LCD1_ACTIVE             0x00000002L
++#define ATOM_S3_TV1_ACTIVE              0x00000004L
++#define ATOM_S3_DFP1_ACTIVE             0x00000008L
++#define ATOM_S3_CRT2_ACTIVE             0x00000010L
++#define ATOM_S3_LCD2_ACTIVE             0x00000020L
++#define ATOM_S3_DFP6_ACTIVE                     0x00000040L
++#define ATOM_S3_DFP2_ACTIVE             0x00000080L
++#define ATOM_S3_CV_ACTIVE               0x00000100L
++#define ATOM_S3_DFP3_ACTIVE                     0x00000200L
++#define ATOM_S3_DFP4_ACTIVE                     0x00000400L
++#define ATOM_S3_DFP5_ACTIVE                     0x00000800L
++
++
++#define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
++
++#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
++#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
++
++#define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
++#define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
++#define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
++#define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
++#define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
++#define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
++#define ATOM_S3_DFP6_CRTC_ACTIVE        0x00400000L
++#define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
++#define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
++#define ATOM_S3_DFP3_CRTC_ACTIVE            0x02000000L
++#define ATOM_S3_DFP4_CRTC_ACTIVE            0x04000000L
++#define ATOM_S3_DFP5_CRTC_ACTIVE            0x08000000L
++
++
++#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
++#define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
++//Below two definitions are not supported in pplib, but in the old powerplay in DAL
++#define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
++#define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
++
++
++
++//Byte aligned defintion for BIOS usage
++#define ATOM_S3_CRT1_ACTIVEb0           0x01
++#define ATOM_S3_LCD1_ACTIVEb0           0x02
++#define ATOM_S3_TV1_ACTIVEb0            0x04
++#define ATOM_S3_DFP1_ACTIVEb0           0x08
++#define ATOM_S3_CRT2_ACTIVEb0           0x10
++#define ATOM_S3_LCD2_ACTIVEb0           0x20
++#define ATOM_S3_DFP6_ACTIVEb0           0x40
++#define ATOM_S3_DFP2_ACTIVEb0           0x80
++#define ATOM_S3_CV_ACTIVEb1             0x01
++#define ATOM_S3_DFP3_ACTIVEb1                  0x02
++#define ATOM_S3_DFP4_ACTIVEb1                  0x04
++#define ATOM_S3_DFP5_ACTIVEb1                  0x08
++
++
++#define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
++
++#define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
++#define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
++#define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
++#define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
++#define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
++#define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
++#define ATOM_S3_DFP6_CRTC_ACTIVEb2      0x40
++#define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
++#define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
++#define ATOM_S3_DFP3_CRTC_ACTIVEb3         0x02
++#define ATOM_S3_DFP4_CRTC_ACTIVEb3         0x04
++#define ATOM_S3_DFP5_CRTC_ACTIVEb3         0x08
++
++
++#define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
++
++
++// BIOS_4_SCRATCH Definition
++#define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
++#define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
++#define ATOM_S4_LCD1_REFRESH_SHIFT      8
++
++//Byte aligned defintion for BIOS usage
++#define ATOM_S4_LCD1_PANEL_ID_MASKb0    0x0FF
++#define ATOM_S4_LCD1_REFRESH_MASKb1     ATOM_S4_LCD1_PANEL_ID_MASKb0
++#define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
++
++// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
++#define ATOM_S5_DOS_REQ_CRT1b0          0x01
++#define ATOM_S5_DOS_REQ_LCD1b0          0x02
++#define ATOM_S5_DOS_REQ_TV1b0           0x04
++#define ATOM_S5_DOS_REQ_DFP1b0          0x08
++#define ATOM_S5_DOS_REQ_CRT2b0          0x10
++#define ATOM_S5_DOS_REQ_LCD2b0          0x20
++#define ATOM_S5_DOS_REQ_DFP6b0          0x40
++#define ATOM_S5_DOS_REQ_DFP2b0          0x80
++#define ATOM_S5_DOS_REQ_CVb1            0x01
++#define ATOM_S5_DOS_REQ_DFP3b1          0x02
++#define ATOM_S5_DOS_REQ_DFP4b1          0x04
++#define ATOM_S5_DOS_REQ_DFP5b1          0x08
++
++
++#define ATOM_S5_DOS_REQ_DEVICEw0        0x0FFF
++
++#define ATOM_S5_DOS_REQ_CRT1            0x0001
++#define ATOM_S5_DOS_REQ_LCD1            0x0002
++#define ATOM_S5_DOS_REQ_TV1             0x0004
++#define ATOM_S5_DOS_REQ_DFP1            0x0008
++#define ATOM_S5_DOS_REQ_CRT2            0x0010
++#define ATOM_S5_DOS_REQ_LCD2            0x0020
++#define ATOM_S5_DOS_REQ_DFP6            0x0040
++#define ATOM_S5_DOS_REQ_DFP2            0x0080
++#define ATOM_S5_DOS_REQ_CV              0x0100
++#define ATOM_S5_DOS_REQ_DFP3            0x0200
++#define ATOM_S5_DOS_REQ_DFP4            0x0400
++#define ATOM_S5_DOS_REQ_DFP5            0x0800
++
++#define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
++#define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
++#define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
++#define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
++#define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
++                                        (ATOM_S5_DOS_FORCE_CVb3<<8))
++// BIOS_6_SCRATCH Definition
++#define ATOM_S6_DEVICE_CHANGE           0x00000001L
++#define ATOM_S6_SCALER_CHANGE           0x00000002L
++#define ATOM_S6_LID_CHANGE              0x00000004L
++#define ATOM_S6_DOCKING_CHANGE          0x00000008L
++#define ATOM_S6_ACC_MODE                0x00000010L
++#define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
++#define ATOM_S6_LID_STATE               0x00000040L
++#define ATOM_S6_DOCK_STATE              0x00000080L
++#define ATOM_S6_CRITICAL_STATE          0x00000100L
++#define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
++#define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
++#define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
++#define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
++#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
++
++#define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
++#define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
++
++#define ATOM_S6_ACC_REQ_CRT1            0x00010000L
++#define ATOM_S6_ACC_REQ_LCD1            0x00020000L
++#define ATOM_S6_ACC_REQ_TV1             0x00040000L
++#define ATOM_S6_ACC_REQ_DFP1            0x00080000L
++#define ATOM_S6_ACC_REQ_CRT2            0x00100000L
++#define ATOM_S6_ACC_REQ_LCD2            0x00200000L
++#define ATOM_S6_ACC_REQ_DFP6            0x00400000L
++#define ATOM_S6_ACC_REQ_DFP2            0x00800000L
++#define ATOM_S6_ACC_REQ_CV              0x01000000L
++#define ATOM_S6_ACC_REQ_DFP3                  0x02000000L
++#define ATOM_S6_ACC_REQ_DFP4                  0x04000000L
++#define ATOM_S6_ACC_REQ_DFP5                  0x08000000L
++
++#define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
++#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
++#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
++#define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
++#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
++
++//Byte aligned defintion for BIOS usage
++#define ATOM_S6_DEVICE_CHANGEb0         0x01
++#define ATOM_S6_SCALER_CHANGEb0         0x02
++#define ATOM_S6_LID_CHANGEb0            0x04
++#define ATOM_S6_DOCKING_CHANGEb0        0x08
++#define ATOM_S6_ACC_MODEb0              0x10
++#define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
++#define ATOM_S6_LID_STATEb0             0x40
++#define ATOM_S6_DOCK_STATEb0            0x80
++#define ATOM_S6_CRITICAL_STATEb1        0x01
++#define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02
++#define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
++#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
++#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10
++#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
++
++#define ATOM_S6_ACC_REQ_CRT1b2          0x01
++#define ATOM_S6_ACC_REQ_LCD1b2          0x02
++#define ATOM_S6_ACC_REQ_TV1b2           0x04
++#define ATOM_S6_ACC_REQ_DFP1b2          0x08
++#define ATOM_S6_ACC_REQ_CRT2b2          0x10
++#define ATOM_S6_ACC_REQ_LCD2b2          0x20
++#define ATOM_S6_ACC_REQ_DFP6b2          0x40
++#define ATOM_S6_ACC_REQ_DFP2b2          0x80
++#define ATOM_S6_ACC_REQ_CVb3            0x01
++#define ATOM_S6_ACC_REQ_DFP3b3          0x02
++#define ATOM_S6_ACC_REQ_DFP4b3          0x04
++#define ATOM_S6_ACC_REQ_DFP5b3          0x08
++
++#define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
++#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
++#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
++#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
++#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
++
++#define ATOM_S6_DEVICE_CHANGE_SHIFT             0
++#define ATOM_S6_SCALER_CHANGE_SHIFT             1
++#define ATOM_S6_LID_CHANGE_SHIFT                2
++#define ATOM_S6_DOCKING_CHANGE_SHIFT            3
++#define ATOM_S6_ACC_MODE_SHIFT                  4
++#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
++#define ATOM_S6_LID_STATE_SHIFT                 6
++#define ATOM_S6_DOCK_STATE_SHIFT                7
++#define ATOM_S6_CRITICAL_STATE_SHIFT            8
++#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
++#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
++#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
++#define ATOM_S6_REQ_SCALER_SHIFT                12
++#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
++#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
++#define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
++#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
++#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
++#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
++#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
++
++// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
++#define ATOM_S7_DOS_MODE_TYPEb0             0x03
++#define ATOM_S7_DOS_MODE_VGAb0              0x00
++#define ATOM_S7_DOS_MODE_VESAb0             0x01
++#define ATOM_S7_DOS_MODE_EXTb0              0x02
++#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
++#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
++#define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
++#define ATOM_S7_ASIC_INIT_COMPLETEb1        0x02
++#define ATOM_S7_ASIC_INIT_COMPLETE_MASK     0x00000200
++#define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
++
++#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
++
++// BIOS_8_SCRATCH Definition
++#define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
++#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000
++
++#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
++#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
++
++// BIOS_9_SCRATCH Definition
++#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
++#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
++#endif
++#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
++#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
++#endif
++#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
++#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
++#endif
++#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
++#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
++#endif
++
++
++#define ATOM_FLAG_SET                         0x20
++#define ATOM_FLAG_CLEAR                       0
++#define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
++#define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
++
++#define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
++#define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
++
++#define SET_ATOM_S6_DOCK_CHANGE                   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
++#define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
++
++#define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
++
++#define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
++#define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
++
++#define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
++#define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
++
++#define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
++#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
++
++#define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
++
++#define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
++
++#define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
++#define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
++#define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
++#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
++
++/****************************************************************************/
++//Portion II: Definitinos only used in Driver
++/****************************************************************************/
++
++// Macros used by driver
++
++#ifdef __cplusplus
++#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
++
++#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
++#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
++#else // not __cplusplus
++#define   GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
++
++#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
++#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
++#endif // __cplusplus
++
++#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
++#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
++
++/****************************************************************************/
++//Portion III: Definitinos only used in VBIOS
++/****************************************************************************/
++#define ATOM_DAC_SRC               0x80
++#define ATOM_SRC_DAC1               0
++#define ATOM_SRC_DAC2               0x80
++
++
++
++typedef struct _MEMORY_PLLINIT_PARAMETERS
++{
++  ULONG ulTargetMemoryClock; //In 10Khz unit
++  UCHAR   ucAction;                //not define yet
++  UCHAR   ucFbDiv_Hi;             //Fbdiv Hi byte
++  UCHAR   ucFbDiv;                //FB value
++  UCHAR   ucPostDiv;             //Post div
++}MEMORY_PLLINIT_PARAMETERS;
++
++#define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
++
++
++#define   GPIO_PIN_WRITE                                       0x01
++#define   GPIO_PIN_READ                                          0x00
++
++typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
++{
++  UCHAR ucGPIO_ID;           //return value, read from GPIO pins
++  UCHAR ucGPIOBitShift;        //define which bit in uGPIOBitVal need to be update
++   UCHAR ucGPIOBitVal;           //Set/Reset corresponding bit defined in ucGPIOBitMask
++  UCHAR ucAction;                 //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
++}GPIO_PIN_CONTROL_PARAMETERS;
++
++typedef struct _ENABLE_SCALER_PARAMETERS
++{
++  UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
++  UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
++  UCHAR ucTVStandard;        //
++  UCHAR ucPadding[1];
++}ENABLE_SCALER_PARAMETERS;
++#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
++
++//ucEnable:
++#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
++#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
++#define SCALER_ENABLE_2TAP_ALPHA_MODE               2
++#define SCALER_ENABLE_MULTITAP_MODE                 3
++
++typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
++{
++  ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
++  UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
++  UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
++  UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
++  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
++}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
++
++typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
++{
++  ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS  sEnableIcon;
++  ENABLE_CRTC_PARAMETERS                  sReserved;
++}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
++
++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
++{
++  USHORT usHight;                     // Image Hight
++  USHORT usWidth;                     // Image Width
++  UCHAR  ucSurface;                   // Surface 1 or 2
++  UCHAR  ucPadding[3];
++}ENABLE_GRAPH_SURFACE_PARAMETERS;
++
++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
++{
++  USHORT usHight;                     // Image Hight
++  USHORT usWidth;                     // Image Width
++  UCHAR  ucSurface;                   // Surface 1 or 2
++  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR  ucPadding[2];
++}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
++
++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
++{
++  USHORT usHight;                     // Image Hight
++  USHORT usWidth;                     // Image Width
++  UCHAR  ucSurface;                   // Surface 1 or 2
++  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
++  USHORT usDeviceId;                  // Active Device Id for this surface. If no device, set to 0.
++}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
++
++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
++{
++  USHORT usHight;                     // Image Hight
++  USHORT usWidth;                     // Image Width
++  USHORT usGraphPitch;
++  UCHAR  ucColorDepth;
++  UCHAR  ucPixelFormat;
++  UCHAR  ucSurface;                   // Surface 1 or 2
++  UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
++  UCHAR  ucModeType;
++  UCHAR  ucReserved;
++}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
++
++// ucEnable
++#define ATOM_GRAPH_CONTROL_SET_PITCH             0x0f
++#define ATOM_GRAPH_CONTROL_SET_DISP_START        0x10
++
++typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
++{
++  ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
++  ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
++}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
++
++typedef struct _MEMORY_CLEAN_UP_PARAMETERS
++{
++  USHORT  usMemoryStart;                //in 8Kb boundry, offset from memory base address
++  USHORT  usMemorySize;                 //8Kb blocks aligned
++}MEMORY_CLEAN_UP_PARAMETERS;
++
++#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
++
++typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
++{
++  USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
++  USHORT  usY_Size;
++}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
++
++typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
++{
++  union{
++    USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
++    USHORT  usSurface;
++  };
++  USHORT usY_Size;
++  USHORT usDispXStart;
++  USHORT usDispYStart;
++}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
++
++
++typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
++{
++  UCHAR  ucLutId;
++  UCHAR  ucAction;
++  USHORT usLutStartIndex;
++  USHORT usLutLength;
++  USHORT usLutOffsetInVram;
++}PALETTE_DATA_CONTROL_PARAMETERS_V3;
++
++// ucAction:
++#define PALETTE_DATA_AUTO_FILL            1
++#define PALETTE_DATA_READ                 2
++#define PALETTE_DATA_WRITE                3
++
++
++typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
++{
++  UCHAR  ucInterruptId;
++  UCHAR  ucServiceId;
++  UCHAR  ucStatus;
++  UCHAR  ucReserved;
++}INTERRUPT_SERVICE_PARAMETER_V2;
++
++// ucInterruptId
++#define HDP1_INTERRUPT_ID                 1
++#define HDP2_INTERRUPT_ID                 2
++#define HDP3_INTERRUPT_ID                 3
++#define HDP4_INTERRUPT_ID                 4
++#define HDP5_INTERRUPT_ID                 5
++#define HDP6_INTERRUPT_ID                 6
++#define SW_INTERRUPT_ID                   11
++
++// ucAction
++#define INTERRUPT_SERVICE_GEN_SW_INT      1
++#define INTERRUPT_SERVICE_GET_STATUS      2
++
++ // ucStatus
++#define INTERRUPT_STATUS__INT_TRIGGER     1
++#define INTERRUPT_STATUS__HPD_HIGH        2
++
++typedef struct _EFUSE_INPUT_PARAMETER
++{
++  USHORT usEfuseIndex;
++  UCHAR  ucBitShift;
++  UCHAR  ucBitLength;
++}EFUSE_INPUT_PARAMETER;
++
++// ReadEfuseValue command table input/output parameter
++typedef union _READ_EFUSE_VALUE_PARAMETER
++{
++  EFUSE_INPUT_PARAMETER sEfuse;
++  ULONG                 ulEfuseValue;
++}READ_EFUSE_VALUE_PARAMETER;
++
++typedef struct _INDIRECT_IO_ACCESS
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  UCHAR                    IOAccessSequence[256];
++} INDIRECT_IO_ACCESS;
++
++#define INDIRECT_READ              0x00
++#define INDIRECT_WRITE             0x80
++
++#define INDIRECT_IO_MM             0
++#define INDIRECT_IO_PLL            1
++#define INDIRECT_IO_MC             2
++#define INDIRECT_IO_PCIE           3
++#define INDIRECT_IO_PCIEP          4
++#define INDIRECT_IO_NBMISC         5
++#define INDIRECT_IO_SMU            5
++
++#define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
++#define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
++#define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
++#define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
++#define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
++#define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
++#define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
++#define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
++#define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
++#define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
++#define INDIRECT_IO_SMU_READ       INDIRECT_IO_SMU | INDIRECT_READ
++#define INDIRECT_IO_SMU_WRITE      INDIRECT_IO_SMU | INDIRECT_WRITE
++
++
++typedef struct _ATOM_OEM_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
++}ATOM_OEM_INFO;
++
++typedef struct _ATOM_TV_MODE
++{
++   UCHAR   ucVMode_Num;           //Video mode number
++   UCHAR   ucTV_Mode_Num;         //Internal TV mode number
++}ATOM_TV_MODE;
++
++typedef struct _ATOM_BIOS_INT_TVSTD_MODE
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++   USHORT   usTV_Mode_LUT_Offset;   // Pointer to standard to internal number conversion table
++   USHORT   usTV_FIFO_Offset;        // Pointer to FIFO entry table
++   USHORT   usNTSC_Tbl_Offset;      // Pointer to SDTV_Mode_NTSC table
++   USHORT   usPAL_Tbl_Offset;        // Pointer to SDTV_Mode_PAL table
++   USHORT   usCV_Tbl_Offset;        // Pointer to SDTV_Mode_PAL table
++}ATOM_BIOS_INT_TVSTD_MODE;
++
++
++typedef struct _ATOM_TV_MODE_SCALER_PTR
++{
++   USHORT   ucFilter0_Offset;      //Pointer to filter format 0 coefficients
++   USHORT   usFilter1_Offset;      //Pointer to filter format 0 coefficients
++   UCHAR   ucTV_Mode_Num;
++}ATOM_TV_MODE_SCALER_PTR;
++
++typedef struct _ATOM_STANDARD_VESA_TIMING
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  ATOM_DTD_FORMAT              aModeTimings[16];      // 16 is not the real array number, just for initial allocation
++}ATOM_STANDARD_VESA_TIMING;
++
++
++typedef struct _ATOM_STD_FORMAT
++{
++  USHORT    usSTD_HDisp;
++  USHORT    usSTD_VDisp;
++  USHORT    usSTD_RefreshRate;
++  USHORT    usReserved;
++}ATOM_STD_FORMAT;
++
++typedef struct _ATOM_VESA_TO_EXTENDED_MODE
++{
++  USHORT  usVESA_ModeNumber;
++  USHORT  usExtendedModeNumber;
++}ATOM_VESA_TO_EXTENDED_MODE;
++
++typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
++}ATOM_VESA_TO_INTENAL_MODE_LUT;
++
++/*************** ATOM Memory Related Data Structure ***********************/
++typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
++   UCHAR                                    ucMemoryType;
++   UCHAR                                    ucMemoryVendor;
++   UCHAR                                    ucAdjMCId;
++   UCHAR                                    ucDynClkId;
++   ULONG                                    ulDllResetClkRange;
++}ATOM_MEMORY_VENDOR_BLOCK;
++
++
++typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
++#if ATOM_BIG_ENDIAN
++	ULONG												ucMemBlkId:8;
++	ULONG												ulMemClockRange:24;
++#else
++	ULONG												ulMemClockRange:24;
++	ULONG												ucMemBlkId:8;
++#endif
++}ATOM_MEMORY_SETTING_ID_CONFIG;
++
++typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
++{
++  ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
++  ULONG                         ulAccess;
++}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
++
++
++typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
++   ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS  ulMemoryID;
++   ULONG                                 aulMemData[1];
++}ATOM_MEMORY_SETTING_DATA_BLOCK;
++
++
++typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
++    USHORT usRegIndex;                                     // MC register index
++    UCHAR  ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
++}ATOM_INIT_REG_INDEX_FORMAT;
++
++
++typedef struct _ATOM_INIT_REG_BLOCK{
++   USHORT                           usRegIndexTblSize;          //size of asRegIndexBuf
++   USHORT                           usRegDataBlkSize;           //size of ATOM_MEMORY_SETTING_DATA_BLOCK
++   ATOM_INIT_REG_INDEX_FORMAT       asRegIndexBuf[1];
++   ATOM_MEMORY_SETTING_DATA_BLOCK   asRegDataBuf[1];
++}ATOM_INIT_REG_BLOCK;
++
++#define END_OF_REG_INDEX_BLOCK  0x0ffff
++#define END_OF_REG_DATA_BLOCK   0x00000000
++#define ATOM_INIT_REG_MASK_FLAG 0x80               //Not used in BIOS
++#define CLOCK_RANGE_HIGHEST     0x00ffffff
++
++#define VALUE_DWORD             SIZEOF ULONG
++#define VALUE_SAME_AS_ABOVE     0
++#define VALUE_MASK_DWORD        0x84
++
++#define INDEX_ACCESS_RANGE_BEGIN       (VALUE_DWORD + 1)
++#define INDEX_ACCESS_RANGE_END          (INDEX_ACCESS_RANGE_BEGIN + 1)
++#define VALUE_INDEX_ACCESS_SINGLE       (INDEX_ACCESS_RANGE_END + 1)
++//#define ACCESS_MCIODEBUGIND            0x40       //defined in BIOS code
++#define ACCESS_PLACEHOLDER             0x80
++
++
++typedef struct _ATOM_MC_INIT_PARAM_TABLE
++{
++  ATOM_COMMON_TABLE_HEADER      sHeader;
++  USHORT                        usAdjustARB_SEQDataOffset;
++  USHORT                        usMCInitMemTypeTblOffset;
++  USHORT                        usMCInitCommonTblOffset;
++  USHORT                        usMCInitPowerDownTblOffset;
++  ULONG                         ulARB_SEQDataBuf[32];
++  ATOM_INIT_REG_BLOCK           asMCInitMemType;
++  ATOM_INIT_REG_BLOCK           asMCInitCommon;
++}ATOM_MC_INIT_PARAM_TABLE;
++
++
++typedef struct _ATOM_REG_INIT_SETTING
++{
++  USHORT  usRegIndex;
++  ULONG   ulRegValue;
++}ATOM_REG_INIT_SETTING;
++
++typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1
++{
++  ATOM_COMMON_TABLE_HEADER      sHeader;
++  ULONG                         ulMCUcodeVersion;
++  ULONG                         ulMCUcodeRomStartAddr;
++  ULONG                         ulMCUcodeLength;
++  USHORT                        usMcRegInitTableOffset;     // offset of ATOM_REG_INIT_SETTING array for MC core register settings.
++  USHORT                        usReserved;                 // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY regsiter setting
++}ATOM_MC_INIT_PARAM_TABLE_V2_1;
++
++
++#define _4Mx16              0x2
++#define _4Mx32              0x3
++#define _8Mx16              0x12
++#define _8Mx32              0x13
++#define _8Mx128             0x15
++#define _16Mx16             0x22
++#define _16Mx32             0x23
++#define _16Mx128            0x25
++#define _32Mx16             0x32
++#define _32Mx32             0x33
++#define _32Mx128            0x35
++#define _64Mx32             0x43
++#define _64Mx8              0x41
++#define _64Mx16             0x42
++#define _128Mx8             0x51
++#define _128Mx16            0x52
++#define _128Mx32            0x53
++#define _256Mx8             0x61
++#define _256Mx16            0x62
++#define _512Mx8             0x71
++
++
++#define SAMSUNG             0x1
++#define INFINEON            0x2
++#define ELPIDA              0x3
++#define ETRON               0x4
++#define NANYA               0x5
++#define HYNIX               0x6
++#define MOSEL               0x7
++#define WINBOND             0x8
++#define ESMT                0x9
++#define MICRON              0xF
++
++#define QIMONDA             INFINEON
++#define PROMOS              MOSEL
++#define KRETON              INFINEON
++#define ELIXIR              NANYA
++#define MEZZA               ELPIDA
++
++
++/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
++
++#define UCODE_ROM_START_ADDRESS      0x1b800
++#define   UCODE_SIGNATURE         0x4375434d // 'MCuC' - MC uCode
++
++//uCode block header for reference
++
++typedef struct _MCuCodeHeader
++{
++  ULONG  ulSignature;
++  UCHAR  ucRevision;
++  UCHAR  ucChecksum;
++  UCHAR  ucReserved1;
++  UCHAR  ucReserved2;
++  USHORT usParametersLength;
++  USHORT usUCodeLength;
++  USHORT usReserved1;
++  USHORT usReserved2;
++} MCuCodeHeader;
++
++//////////////////////////////////////////////////////////////////////////////////
++
++#define ATOM_MAX_NUMBER_OF_VRAM_MODULE   16
++
++#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK   0xF
++typedef struct _ATOM_VRAM_MODULE_V1
++{
++  ULONG                      ulReserved;
++  USHORT                     usEMRSValue;
++  USHORT                     usMRSValue;
++  USHORT                     usReserved;
++  UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
++  UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
++  UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender
++  UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
++  UCHAR                      ucRow;             // Number of Row,in power of 2;
++  UCHAR                      ucColumn;          // Number of Column,in power of 2;
++  UCHAR                      ucBank;            // Nunber of Bank;
++  UCHAR                      ucRank;            // Number of Rank, in power of 2
++  UCHAR                      ucChannelNum;      // Number of channel;
++  UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
++  UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
++  UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
++  UCHAR                      ucReserved[2];
++}ATOM_VRAM_MODULE_V1;
++
++
++typedef struct _ATOM_VRAM_MODULE_V2
++{
++  ULONG                      ulReserved;
++  ULONG                      ulFlags;              // To enable/disable functionalities based on memory type
++  ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
++  ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
++  USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
++  USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
++  USHORT                     usEMRSValue;
++  USHORT                     usMRSValue;
++  USHORT                     usReserved;
++  UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
++  UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
++  UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
++  UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
++  UCHAR                      ucRow;             // Number of Row,in power of 2;
++  UCHAR                      ucColumn;          // Number of Column,in power of 2;
++  UCHAR                      ucBank;            // Nunber of Bank;
++  UCHAR                      ucRank;            // Number of Rank, in power of 2
++  UCHAR                      ucChannelNum;      // Number of channel;
++  UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
++  UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
++  UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
++  UCHAR                      ucRefreshRateFactor;
++  UCHAR                      ucReserved[3];
++}ATOM_VRAM_MODULE_V2;
++
++
++typedef   struct _ATOM_MEMORY_TIMING_FORMAT
++{
++   ULONG                     ulClkRange;            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
++  union{
++    USHORT                   usMRS;                 // mode register
++    USHORT                   usDDR3_MR0;
++  };
++  union{
++    USHORT                   usEMRS;                  // extended mode register
++    USHORT                   usDDR3_MR1;
++  };
++   UCHAR                     ucCL;                    // CAS latency
++   UCHAR                     ucWL;                    // WRITE Latency
++   UCHAR                     uctRAS;                  // tRAS
++   UCHAR                     uctRC;                   // tRC
++   UCHAR                     uctRFC;                  // tRFC
++   UCHAR                     uctRCDR;                 // tRCDR
++   UCHAR                     uctRCDW;                 // tRCDW
++   UCHAR                     uctRP;                   // tRP
++   UCHAR                     uctRRD;                  // tRRD
++   UCHAR                     uctWR;                   // tWR
++   UCHAR                     uctWTR;                  // tWTR
++   UCHAR                     uctPDIX;                 // tPDIX
++   UCHAR                     uctFAW;                  // tFAW
++   UCHAR                     uctAOND;                 // tAOND
++  union
++  {
++    struct {
++       UCHAR                                  ucflag;                  // flag to control memory timing calculation. bit0= control EMRS2 Infineon
++       UCHAR                                  ucReserved;
++    };
++    USHORT                   usDDR3_MR2;
++  };
++}ATOM_MEMORY_TIMING_FORMAT;
++
++
++typedef   struct _ATOM_MEMORY_TIMING_FORMAT_V1
++{
++   ULONG                      ulClkRange;            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
++   USHORT                     usMRS;                 // mode register
++   USHORT                     usEMRS;                // extended mode register
++   UCHAR                      ucCL;                  // CAS latency
++   UCHAR                      ucWL;                  // WRITE Latency
++   UCHAR                      uctRAS;                // tRAS
++   UCHAR                      uctRC;                 // tRC
++   UCHAR                      uctRFC;                // tRFC
++   UCHAR                      uctRCDR;               // tRCDR
++   UCHAR                      uctRCDW;               // tRCDW
++   UCHAR                      uctRP;                 // tRP
++   UCHAR                      uctRRD;                // tRRD
++   UCHAR                      uctWR;                 // tWR
++   UCHAR                      uctWTR;                // tWTR
++   UCHAR                      uctPDIX;               // tPDIX
++   UCHAR                      uctFAW;                // tFAW
++   UCHAR                      uctAOND;               // tAOND
++   UCHAR                      ucflag;                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
++////////////////////////////////////GDDR parameters///////////////////////////////////
++   UCHAR                      uctCCDL;               //
++   UCHAR                      uctCRCRL;              //
++   UCHAR                      uctCRCWL;              //
++   UCHAR                      uctCKE;                //
++   UCHAR                      uctCKRSE;              //
++   UCHAR                      uctCKRSX;              //
++   UCHAR                      uctFAW32;              //
++   UCHAR                      ucMR5lo;               //
++   UCHAR                      ucMR5hi;               //
++   UCHAR                      ucTerminator;
++}ATOM_MEMORY_TIMING_FORMAT_V1;
++
++
++
++
++typedef   struct _ATOM_MEMORY_TIMING_FORMAT_V2
++{
++   ULONG                                  ulClkRange;            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
++   USHORT                               usMRS;                     // mode register
++   USHORT                               usEMRS;                  // extended mode register
++   UCHAR                                  ucCL;                     // CAS latency
++   UCHAR                                  ucWL;                     // WRITE Latency
++   UCHAR                                  uctRAS;                  // tRAS
++   UCHAR                                  uctRC;                     // tRC
++   UCHAR                                  uctRFC;                  // tRFC
++   UCHAR                                  uctRCDR;                  // tRCDR
++   UCHAR                                  uctRCDW;                  // tRCDW
++   UCHAR                                  uctRP;                     // tRP
++   UCHAR                                  uctRRD;                  // tRRD
++   UCHAR                                  uctWR;                     // tWR
++   UCHAR                                  uctWTR;                  // tWTR
++   UCHAR                                  uctPDIX;                  // tPDIX
++   UCHAR                                  uctFAW;                  // tFAW
++   UCHAR                                  uctAOND;                  // tAOND
++   UCHAR                                  ucflag;                  // flag to control memory timing calculation. bit0= control EMRS2 Infineon
++////////////////////////////////////GDDR parameters///////////////////////////////////
++   UCHAR                                  uctCCDL;                  //
++   UCHAR                                  uctCRCRL;                  //
++   UCHAR                                  uctCRCWL;                  //
++   UCHAR                                  uctCKE;                  //
++   UCHAR                                  uctCKRSE;                  //
++   UCHAR                                  uctCKRSX;                  //
++   UCHAR                                  uctFAW32;                  //
++   UCHAR                                  ucMR4lo;               //
++   UCHAR                                  ucMR4hi;               //
++   UCHAR                                  ucMR5lo;               //
++   UCHAR                                  ucMR5hi;               //
++   UCHAR                                  ucTerminator;
++   UCHAR                                  ucReserved;
++}ATOM_MEMORY_TIMING_FORMAT_V2;
++
++
++typedef   struct _ATOM_MEMORY_FORMAT
++{
++   ULONG                       ulDllDisClock;     // memory DLL will be disable when target memory clock is below this clock
++  union{
++    USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
++    USHORT                     usDDR3_Reserved;   // Not used for DDR3 memory
++  };
++  union{
++    USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
++    USHORT                     usDDR3_MR3;        // Used for DDR3 memory
++  };
++  UCHAR                        ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
++  UCHAR                        ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
++  UCHAR                        ucRow;             // Number of Row,in power of 2;
++  UCHAR                        ucColumn;          // Number of Column,in power of 2;
++  UCHAR                        ucBank;            // Nunber of Bank;
++  UCHAR                        ucRank;            // Number of Rank, in power of 2
++  UCHAR                        ucBurstSize;           // burst size, 0= burst size=4  1= burst size=8
++  UCHAR                        ucDllDisBit;           // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
++  UCHAR                        ucRefreshRateFactor;   // memory refresh rate in unit of ms
++  UCHAR                        ucDensity;             // _8Mx32, _16Mx32, _16Mx16, _32Mx16
++  UCHAR                        ucPreamble;            // [7:4] Write Preamble, [3:0] Read Preamble
++  UCHAR                        ucMemAttrib;           // Memory Device Addribute, like RDBI/WDBI etc
++  ATOM_MEMORY_TIMING_FORMAT    asMemTiming[5];        // Memory Timing block sort from lower clock to higher clock
++}ATOM_MEMORY_FORMAT;
++
++
++typedef struct _ATOM_VRAM_MODULE_V3
++{
++  ULONG                      ulChannelMapCfg;     // board dependent paramenter:Channel combination
++  USHORT                     usSize;              // size of ATOM_VRAM_MODULE_V3
++  USHORT                     usDefaultMVDDQ;      // board dependent parameter:Default Memory Core Voltage
++  USHORT                     usDefaultMVDDC;      // board dependent parameter:Default Memory IO Voltage
++  UCHAR                      ucExtMemoryID;       // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
++  UCHAR                      ucChannelNum;        // board dependent parameter:Number of channel;
++  UCHAR                      ucChannelSize;       // board dependent parameter:32bit or 64bit
++  UCHAR                      ucVREFI;             // board dependnt parameter: EXT or INT +160mv to -140mv
++  UCHAR                      ucNPL_RT;            // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
++  UCHAR                      ucFlag;              // To enable/disable functionalities based on memory type
++  ATOM_MEMORY_FORMAT         asMemory;            // describ all of video memory parameters from memory spec
++}ATOM_VRAM_MODULE_V3;
++
++
++//ATOM_VRAM_MODULE_V3.ucNPL_RT
++#define NPL_RT_MASK                                         0x0f
++#define BATTERY_ODT_MASK                                    0xc0
++
++#define ATOM_VRAM_MODULE       ATOM_VRAM_MODULE_V3
++
++typedef struct _ATOM_VRAM_MODULE_V4
++{
++  ULONG     ulChannelMapCfg;                   // board dependent parameter: Channel combination
++  USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
++  USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
++                                            // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
++  USHORT  usReserved;
++  UCHAR   ucExtMemoryID;                      // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
++  UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
++  UCHAR   ucChannelNum;                     // Number of channels present in this module config
++  UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
++   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
++   UCHAR     ucFlag;                                  // To enable/disable functionalities based on memory type
++   UCHAR     ucMisc;                                  // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
++  UCHAR      ucVREFI;                          // board dependent parameter
++  UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
++  UCHAR      ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
++  UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
++                                            // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
++  UCHAR   ucReserved[3];
++
++//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
++  union{
++    USHORT   usEMRS2Value;                   // EMRS2 Value is used for GDDR2 and GDDR4 memory type
++    USHORT  usDDR3_Reserved;
++  };
++  union{
++    USHORT   usEMRS3Value;                   // EMRS3 Value is used for GDDR2 and GDDR4 memory type
++    USHORT  usDDR3_MR3;                     // Used for DDR3 memory
++  };
++  UCHAR   ucMemoryVenderID;                    // Predefined, If not predefined, vendor detection table gets executed
++  UCHAR     ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
++  UCHAR   ucReserved2[2];
++  ATOM_MEMORY_TIMING_FORMAT  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
++}ATOM_VRAM_MODULE_V4;
++
++#define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
++#define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
++#define VRAM_MODULE_V4_MISC_BL_MASK         0x4
++#define VRAM_MODULE_V4_MISC_BL8             0x4
++#define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
++
++typedef struct _ATOM_VRAM_MODULE_V5
++{
++  ULONG     ulChannelMapCfg;                   // board dependent parameter: Channel combination
++  USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
++  USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
++                                            // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
++  USHORT  usReserved;
++  UCHAR   ucExtMemoryID;                      // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
++  UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
++  UCHAR   ucChannelNum;                     // Number of channels present in this module config
++  UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
++   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
++   UCHAR     ucFlag;                                  // To enable/disable functionalities based on memory type
++   UCHAR     ucMisc;                                  // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
++  UCHAR      ucVREFI;                          // board dependent parameter
++  UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
++  UCHAR      ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
++  UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
++                                            // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
++  UCHAR   ucReserved[3];
++
++//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
++  USHORT   usEMRS2Value;                        // EMRS2 Value is used for GDDR2 and GDDR4 memory type
++  USHORT   usEMRS3Value;                        // EMRS3 Value is used for GDDR2 and GDDR4 memory type
++  UCHAR   ucMemoryVenderID;                    // Predefined, If not predefined, vendor detection table gets executed
++  UCHAR     ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
++  UCHAR     ucFIFODepth;                         // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
++  UCHAR   ucCDR_Bandwidth;         // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
++  ATOM_MEMORY_TIMING_FORMAT_V1  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
++}ATOM_VRAM_MODULE_V5;
++
++
++typedef struct _ATOM_VRAM_MODULE_V6
++{
++  ULONG     ulChannelMapCfg;                   // board dependent parameter: Channel combination
++  USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
++  USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
++                                            // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
++  USHORT  usReserved;
++  UCHAR   ucExtMemoryID;                      // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
++  UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
++  UCHAR   ucChannelNum;                     // Number of channels present in this module config
++  UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
++   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
++   UCHAR     ucFlag;                                  // To enable/disable functionalities based on memory type
++   UCHAR     ucMisc;                                  // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
++  UCHAR      ucVREFI;                          // board dependent parameter
++  UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
++  UCHAR      ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
++  UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
++                                            // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
++  UCHAR   ucReserved[3];
++
++//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
++  USHORT   usEMRS2Value;                        // EMRS2 Value is used for GDDR2 and GDDR4 memory type
++  USHORT   usEMRS3Value;                        // EMRS3 Value is used for GDDR2 and GDDR4 memory type
++  UCHAR   ucMemoryVenderID;                    // Predefined, If not predefined, vendor detection table gets executed
++  UCHAR     ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
++  UCHAR     ucFIFODepth;                         // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
++  UCHAR   ucCDR_Bandwidth;         // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
++  ATOM_MEMORY_TIMING_FORMAT_V2  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
++}ATOM_VRAM_MODULE_V6;
++
++typedef struct _ATOM_VRAM_MODULE_V7
++{
++// Design Specific Values
++  ULONG   ulChannelMapCfg;                   // mmMC_SHARED_CHREMAP
++  USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
++  USHORT  usPrivateReserved;                // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
++  USHORT  usEnableChannels;                 // bit vector which indicate which channels are enabled
++  UCHAR   ucExtMemoryID;                    // Current memory module ID
++  UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
++  UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
++  UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
++  UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
++  UCHAR   ucReserve;                        // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
++  UCHAR   ucMisc;                           // RANK_OF_THISMEMORY etc.
++  UCHAR   ucVREFI;                          // Not used.
++  UCHAR   ucNPL_RT;                         // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
++  UCHAR   ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
++  UCHAR   ucMemorySize;                     // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
++  USHORT  usSEQSettingOffset;
++  UCHAR   ucReserved;
++// Memory Module specific values
++  USHORT  usEMRS2Value;                     // EMRS2/MR2 Value.
++  USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
++  UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
++  UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
++  UCHAR   ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
++  UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
++  char    strMemPNString[20];               // part number end with '0'.
++}ATOM_VRAM_MODULE_V7;
++
++
++typedef struct _ATOM_VRAM_MODULE_V8
++{
++// Design Specific Values
++  ULONG   ulChannelMapCfg;                  // mmMC_SHARED_CHREMAP
++  USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
++  USHORT  usMcRamCfg;                       // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
++  USHORT  usEnableChannels;                 // bit vector which indicate which channels are enabled
++  UCHAR   ucExtMemoryID;                    // Current memory module ID
++  UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
++  UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
++  UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
++  UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
++  UCHAR   ucBankCol;                        // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
++  UCHAR   ucMisc;                           // RANK_OF_THISMEMORY etc.
++  UCHAR   ucVREFI;                          // Not used.
++  USHORT  usReserved;                       // Not used
++  USHORT  usMemorySize;                     // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
++  UCHAR   ucMcTunningSetId;                 // MC phy registers set per.
++  UCHAR   ucRowNum;
++// Memory Module specific values
++  USHORT  usEMRS2Value;                     // EMRS2/MR2 Value.
++  USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
++  UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
++  UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
++  UCHAR   ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
++  UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
++
++  ULONG   ulChannelMapCfg1;                 // channel mapping for channel8~15
++  ULONG   ulBankMapCfg;
++  ULONG   ulReserved;
++  char    strMemPNString[20];               // part number end with '0'.
++}ATOM_VRAM_MODULE_V8;
++
++
++typedef struct _ATOM_VRAM_INFO_V2
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  UCHAR                      ucNumOfVRAMModule;
++  ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
++}ATOM_VRAM_INFO_V2;
++
++typedef struct _ATOM_VRAM_INFO_V3
++{
++  ATOM_COMMON_TABLE_HEADER  sHeader;
++  USHORT                    usMemAdjustTblOffset;                            // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
++  USHORT                    usMemClkPatchTblOffset;                          // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
++  USHORT                    usRerseved;
++  UCHAR                     aVID_PinsShift[9];                               // 8 bit strap maximum+terminator
++  UCHAR                     ucNumOfVRAMModule;
++  ATOM_VRAM_MODULE          aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];       // just for allocation, real number of blocks is in ucNumOfVRAMModule;
++  ATOM_INIT_REG_BLOCK       asMemPatch;                                      // for allocation
++
++}ATOM_VRAM_INFO_V3;
++
++#define   ATOM_VRAM_INFO_LAST        ATOM_VRAM_INFO_V3
++
++typedef struct _ATOM_VRAM_INFO_V4
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                     usMemAdjustTblOffset;                           // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
++  USHORT                     usMemClkPatchTblOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
++  USHORT                     usRerseved;
++  UCHAR                      ucMemDQ7_0ByteRemap;                            // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
++  ULONG                      ulMemDQ7_0BitRemap;                             // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
++  UCHAR                      ucReservde[4];
++  UCHAR                      ucNumOfVRAMModule;
++  ATOM_VRAM_MODULE_V4        aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
++  ATOM_INIT_REG_BLOCK        asMemPatch;                                     // for allocation
++}ATOM_VRAM_INFO_V4;
++
++typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                     usMemAdjustTblOffset;                           // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
++  USHORT                     usMemClkPatchTblOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
++  USHORT                     usPerBytePresetOffset;                          // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
++  USHORT                     usReserved[3];
++  UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
++  UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
++  UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
++  UCHAR                      ucReserved;
++  ATOM_VRAM_MODULE_V7        aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
++}ATOM_VRAM_INFO_HEADER_V2_1;
++
++typedef struct _ATOM_VRAM_INFO_HEADER_V2_2
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                     usMemAdjustTblOffset;                           // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
++  USHORT                     usMemClkPatchTblOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
++  USHORT                     usMcAdjustPerTileTblOffset;                     // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
++  USHORT                     usMcPhyInitTableOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set
++  USHORT                     usDramDataRemapTblOffset;                       // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping
++  USHORT                     usReserved1;
++  UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
++  UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
++  UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
++  UCHAR                      ucMcPhyTileNum;                                 // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
++  ATOM_VRAM_MODULE_V8        aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
++}ATOM_VRAM_INFO_HEADER_V2_2;
++
++
++typedef struct _ATOM_DRAM_DATA_REMAP
++{
++  UCHAR ucByteRemapCh0;
++  UCHAR ucByteRemapCh1;
++  ULONG ulByte0BitRemapCh0;
++  ULONG ulByte1BitRemapCh0;
++  ULONG ulByte2BitRemapCh0;
++  ULONG ulByte3BitRemapCh0;
++  ULONG ulByte0BitRemapCh1;
++  ULONG ulByte1BitRemapCh1;
++  ULONG ulByte2BitRemapCh1;
++  ULONG ulByte3BitRemapCh1;
++}ATOM_DRAM_DATA_REMAP;
++
++typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  UCHAR                      aVID_PinsShift[9];                              // 8 bit strap maximum+terminator
++}ATOM_VRAM_GPIO_DETECTION_INFO;
++
++
++typedef struct _ATOM_MEMORY_TRAINING_INFO
++{
++   ATOM_COMMON_TABLE_HEADER   sHeader;
++   UCHAR                                  ucTrainingLoop;
++   UCHAR                                  ucReserved[3];
++   ATOM_INIT_REG_BLOCK             asMemTrainingSetting;
++}ATOM_MEMORY_TRAINING_INFO;
++
++
++typedef struct SW_I2C_CNTL_DATA_PARAMETERS
++{
++  UCHAR    ucControl;
++  UCHAR    ucData;
++  UCHAR    ucSatus;
++  UCHAR    ucTemp;
++} SW_I2C_CNTL_DATA_PARAMETERS;
++
++#define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
++
++typedef struct _SW_I2C_IO_DATA_PARAMETERS
++{
++  USHORT   GPIO_Info;
++  UCHAR    ucAct;
++  UCHAR    ucData;
++ } SW_I2C_IO_DATA_PARAMETERS;
++
++#define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
++
++/****************************SW I2C CNTL DEFINITIONS**********************/
++#define SW_I2C_IO_RESET       0
++#define SW_I2C_IO_GET         1
++#define SW_I2C_IO_DRIVE       2
++#define SW_I2C_IO_SET         3
++#define SW_I2C_IO_START       4
++
++#define SW_I2C_IO_CLOCK       0
++#define SW_I2C_IO_DATA        0x80
++
++#define SW_I2C_IO_ZERO        0
++#define SW_I2C_IO_ONE         0x100
++
++#define SW_I2C_CNTL_READ      0
++#define SW_I2C_CNTL_WRITE     1
++#define SW_I2C_CNTL_START     2
++#define SW_I2C_CNTL_STOP      3
++#define SW_I2C_CNTL_OPEN      4
++#define SW_I2C_CNTL_CLOSE     5
++#define SW_I2C_CNTL_WRITE1BIT 6
++
++//==============================VESA definition Portion===============================
++#define VESA_OEM_PRODUCT_REV                     '01.00'
++#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT        0xBB   //refer to VBE spec p.32, no TTY support
++#define VESA_MODE_WIN_ATTRIBUTE                       7
++#define VESA_WIN_SIZE                                      64
++
++typedef struct _PTR_32_BIT_STRUCTURE
++{
++   USHORT   Offset16;
++   USHORT   Segment16;
++} PTR_32_BIT_STRUCTURE;
++
++typedef union _PTR_32_BIT_UNION
++{
++   PTR_32_BIT_STRUCTURE   SegmentOffset;
++   ULONG                       Ptr32_Bit;
++} PTR_32_BIT_UNION;
++
++typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
++{
++   UCHAR                  VbeSignature[4];
++   USHORT                VbeVersion;
++   PTR_32_BIT_UNION   OemStringPtr;
++   UCHAR                  Capabilities[4];
++   PTR_32_BIT_UNION   VideoModePtr;
++   USHORT                TotalMemory;
++} VBE_1_2_INFO_BLOCK_UPDATABLE;
++
++
++typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
++{
++   VBE_1_2_INFO_BLOCK_UPDATABLE   CommonBlock;
++   USHORT                         OemSoftRev;
++   PTR_32_BIT_UNION            OemVendorNamePtr;
++   PTR_32_BIT_UNION            OemProductNamePtr;
++   PTR_32_BIT_UNION            OemProductRevPtr;
++} VBE_2_0_INFO_BLOCK_UPDATABLE;
++
++typedef union _VBE_VERSION_UNION
++{
++   VBE_2_0_INFO_BLOCK_UPDATABLE   VBE_2_0_InfoBlock;
++   VBE_1_2_INFO_BLOCK_UPDATABLE   VBE_1_2_InfoBlock;
++} VBE_VERSION_UNION;
++
++typedef struct _VBE_INFO_BLOCK
++{
++   VBE_VERSION_UNION         UpdatableVBE_Info;
++   UCHAR                        Reserved[222];
++   UCHAR                        OemData[256];
++} VBE_INFO_BLOCK;
++
++typedef struct _VBE_FP_INFO
++{
++  USHORT   HSize;
++  USHORT   VSize;
++  USHORT   FPType;
++  UCHAR    RedBPP;
++  UCHAR    GreenBPP;
++  UCHAR    BlueBPP;
++  UCHAR    ReservedBPP;
++  ULONG    RsvdOffScrnMemSize;
++  ULONG    RsvdOffScrnMEmPtr;
++  UCHAR    Reserved[14];
++} VBE_FP_INFO;
++
++typedef struct _VESA_MODE_INFO_BLOCK
++{
++// Mandatory information for all VBE revisions
++  USHORT   ModeAttributes;  //         dw   ?   ; mode attributes
++  UCHAR    WinAAttributes;  //         db   ?   ; window A attributes
++  UCHAR    WinBAttributes;  //         db   ?   ; window B attributes
++  USHORT   WinGranularity;  //         dw   ?   ; window granularity
++  USHORT   WinSize;         //         dw   ?   ; window size
++  USHORT   WinASegment;     //         dw   ?   ; window A start segment
++  USHORT   WinBSegment;     //         dw   ?   ; window B start segment
++  ULONG    WinFuncPtr;      //         dd   ?   ; real mode pointer to window function
++  USHORT   BytesPerScanLine;//         dw   ?   ; bytes per scan line
++
++//; Mandatory information for VBE 1.2 and above
++  USHORT   XResolution;      //         dw   ?   ; horizontal resolution in pixels or characters
++  USHORT   YResolution;      //         dw   ?   ; vertical resolution in pixels or characters
++  UCHAR    XCharSize;        //         db   ?   ; character cell width in pixels
++  UCHAR    YCharSize;        //         db   ?   ; character cell height in pixels
++  UCHAR    NumberOfPlanes;   //         db   ?   ; number of memory planes
++  UCHAR    BitsPerPixel;     //         db   ?   ; bits per pixel
++  UCHAR    NumberOfBanks;    //         db   ?   ; number of banks
++  UCHAR    MemoryModel;      //         db   ?   ; memory model type
++  UCHAR    BankSize;         //         db   ?   ; bank size in KB
++  UCHAR    NumberOfImagePages;//        db   ?   ; number of images
++  UCHAR    ReservedForPageFunction;//db   1   ; reserved for page function
++
++//; Direct Color fields(required for direct/6 and YUV/7 memory models)
++  UCHAR    RedMaskSize;        //      db   ?   ; size of direct color red mask in bits
++  UCHAR    RedFieldPosition;   //      db   ?   ; bit position of lsb of red mask
++  UCHAR    GreenMaskSize;      //      db   ?   ; size of direct color green mask in bits
++  UCHAR    GreenFieldPosition; //      db   ?   ; bit position of lsb of green mask
++  UCHAR    BlueMaskSize;       //      db   ?   ; size of direct color blue mask in bits
++  UCHAR    BlueFieldPosition;  //      db   ?   ; bit position of lsb of blue mask
++  UCHAR    RsvdMaskSize;       //      db   ?   ; size of direct color reserved mask in bits
++  UCHAR    RsvdFieldPosition;  //      db   ?   ; bit position of lsb of reserved mask
++  UCHAR    DirectColorModeInfo;//      db   ?   ; direct color mode attributes
++
++//; Mandatory information for VBE 2.0 and above
++  ULONG    PhysBasePtr;        //      dd   ?   ; physical address for flat memory frame buffer
++  ULONG    Reserved_1;         //      dd   0   ; reserved - always set to 0
++  USHORT   Reserved_2;         //     dw   0   ; reserved - always set to 0
++
++//; Mandatory information for VBE 3.0 and above
++  USHORT   LinBytesPerScanLine;  //   dw   ?   ; bytes per scan line for linear modes
++  UCHAR    BnkNumberOfImagePages;//   db   ?   ; number of images for banked modes
++  UCHAR    LinNumberOfImagPages; //   db   ?   ; number of images for linear modes
++  UCHAR    LinRedMaskSize;       //   db   ?   ; size of direct color red mask(linear modes)
++  UCHAR    LinRedFieldPosition;  //   db   ?   ; bit position of lsb of red mask(linear modes)
++  UCHAR    LinGreenMaskSize;     //   db   ?   ; size of direct color green mask(linear modes)
++  UCHAR    LinGreenFieldPosition;//   db   ?   ; bit position of lsb of green mask(linear modes)
++  UCHAR    LinBlueMaskSize;      //   db   ?   ; size of direct color blue mask(linear modes)
++  UCHAR    LinBlueFieldPosition; //   db   ?   ; bit position of lsb of blue mask(linear modes)
++  UCHAR    LinRsvdMaskSize;      //   db   ?   ; size of direct color reserved mask(linear modes)
++  UCHAR    LinRsvdFieldPosition; //   db   ?   ; bit position of lsb of reserved mask(linear modes)
++  ULONG    MaxPixelClock;        //   dd   ?   ; maximum pixel clock(in Hz) for graphics mode
++  UCHAR    Reserved;             //   db   190 dup (0)
++} VESA_MODE_INFO_BLOCK;
++
++// BIOS function CALLS
++#define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0           // ATI Extended Function code
++#define ATOM_BIOS_FUNCTION_COP_MODE             0x00
++#define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
++#define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
++#define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
++#define ATOM_BIOS_FUNCTION_GET_DDC              0x0B
++#define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
++#define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
++#define ATOM_BIOS_FUNCTION_STV_STD              0x16
++#define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
++#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
++
++#define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
++#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
++#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
++#define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
++#define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
++#define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
++#define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
++
++#define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
++#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
++#define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
++#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03
++#define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
++#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
++#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
++#define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
++#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
++#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
++
++
++#define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS
++#define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01
++#define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02
++#define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.
++#define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY
++#define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
++#define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
++#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
++
++#define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
++#define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
++#define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
++
++// structure used for VBIOS only
++
++//DispOutInfoTable
++typedef struct _ASIC_TRANSMITTER_INFO
++{
++   USHORT usTransmitterObjId;
++   USHORT usSupportDevice;
++  UCHAR  ucTransmitterCmdTblId;
++   UCHAR  ucConfig;
++   UCHAR  ucEncoderID;                //available 1st encoder ( default )
++   UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
++   UCHAR  uc2ndEncoderID;
++   UCHAR  ucReserved;
++}ASIC_TRANSMITTER_INFO;
++
++#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE          0x01
++#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE         0x02
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK    0xc4
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A             0x00
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B             0x04
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C             0x40
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D             0x44
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E             0x80
++#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F             0x84
++
++typedef struct _ASIC_ENCODER_INFO
++{
++   UCHAR ucEncoderID;
++   UCHAR ucEncoderConfig;
++  USHORT usEncoderCmdTblId;
++}ASIC_ENCODER_INFO;
++
++typedef struct _ATOM_DISP_OUT_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++   USHORT ptrTransmitterInfo;
++   USHORT ptrEncoderInfo;
++   ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
++   ASIC_ENCODER_INFO      asEncoderInfo[1];
++}ATOM_DISP_OUT_INFO;
++
++
++typedef struct _ATOM_DISP_OUT_INFO_V2
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++   USHORT ptrTransmitterInfo;
++   USHORT ptrEncoderInfo;
++  USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
++   ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
++   ASIC_ENCODER_INFO      asEncoderInfo[1];
++}ATOM_DISP_OUT_INFO_V2;
++
++
++typedef struct _ATOM_DISP_CLOCK_ID {
++  UCHAR ucPpllId;
++  UCHAR ucPpllAttribute;
++}ATOM_DISP_CLOCK_ID;
++
++// ucPpllAttribute
++#define CLOCK_SOURCE_SHAREABLE            0x01
++#define CLOCK_SOURCE_DP_MODE              0x02
++#define CLOCK_SOURCE_NONE_DP_MODE         0x04
++
++//DispOutInfoTable
++typedef struct _ASIC_TRANSMITTER_INFO_V2
++{
++   USHORT usTransmitterObjId;
++   USHORT usDispClkIdOffset;    // point to clock source id list supported by Encoder Object
++  UCHAR  ucTransmitterCmdTblId;
++   UCHAR  ucConfig;
++   UCHAR  ucEncoderID;                // available 1st encoder ( default )
++   UCHAR  ucOptionEncoderID;    // available 2nd encoder ( optional )
++   UCHAR  uc2ndEncoderID;
++   UCHAR  ucReserved;
++}ASIC_TRANSMITTER_INFO_V2;
++
++typedef struct _ATOM_DISP_OUT_INFO_V3
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT ptrTransmitterInfo;
++  USHORT ptrEncoderInfo;
++  USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
++  USHORT usReserved;
++  UCHAR  ucDCERevision;
++  UCHAR  ucMaxDispEngineNum;
++  UCHAR  ucMaxActiveDispEngineNum;
++  UCHAR  ucMaxPPLLNum;
++  UCHAR  ucCoreRefClkSource;                    // value of CORE_REF_CLK_SOURCE
++  UCHAR  ucDispCaps;
++  UCHAR  ucReserved[2];
++  ASIC_TRANSMITTER_INFO_V2  asTransmitterInfo[1];     // for alligment only
++}ATOM_DISP_OUT_INFO_V3;
++
++//ucDispCaps
++#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL        0x01
++#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED  0x02
++
++typedef enum CORE_REF_CLK_SOURCE{
++  CLOCK_SRC_XTALIN=0,
++  CLOCK_SRC_XO_IN=1,
++  CLOCK_SRC_XO_IN2=2,
++}CORE_REF_CLK_SOURCE;
++
++// DispDevicePriorityInfo
++typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++   USHORT asDevicePriority[16];
++}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
++
++//ProcessAuxChannelTransactionTable
++typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
++{
++   USHORT  lpAuxRequest;
++   USHORT  lpDataOut;
++   UCHAR   ucChannelID;
++   union
++   {
++  UCHAR   ucReplyStatus;
++   UCHAR   ucDelay;
++   };
++  UCHAR   ucDataOutLen;
++   UCHAR   ucReserved;
++}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
++
++//ProcessAuxChannelTransactionTable
++typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
++{
++   USHORT   lpAuxRequest;
++   USHORT  lpDataOut;
++   UCHAR      ucChannelID;
++   union
++   {
++  UCHAR   ucReplyStatus;
++   UCHAR   ucDelay;
++   };
++  UCHAR   ucDataOutLen;
++   UCHAR   ucHPD_ID;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
++}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
++
++#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
++
++//GetSinkType
++
++typedef struct _DP_ENCODER_SERVICE_PARAMETERS
++{
++   USHORT ucLinkClock;
++   union
++   {
++   UCHAR ucConfig;            // for DP training command
++   UCHAR ucI2cId;            // use for GET_SINK_TYPE command
++   };
++   UCHAR ucAction;
++   UCHAR ucStatus;
++   UCHAR ucLaneNum;
++   UCHAR ucReserved[2];
++}DP_ENCODER_SERVICE_PARAMETERS;
++
++// ucAction
++#define ATOM_DP_ACTION_GET_SINK_TYPE                     0x01
++
++#define DP_ENCODER_SERVICE_PS_ALLOCATION            WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
++
++
++typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
++{
++   USHORT usExtEncoderObjId;   // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
++  UCHAR  ucAuxId;
++  UCHAR  ucAction;
++  UCHAR  ucSinkType;          // Iput and Output parameters.
++  UCHAR  ucHPDId;             // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
++   UCHAR  ucReserved[2];
++}DP_ENCODER_SERVICE_PARAMETERS_V2;
++
++typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
++{
++  DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
++  PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
++}DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
++
++// ucAction
++#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE                     0x01
++#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION             0x02
++
++
++// DP_TRAINING_TABLE
++#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR            ATOM_DP_TRAINING_TBL_ADDR
++#define DPCD_SET_SS_CNTL_TBL_ADDR                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
++#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                     (ATOM_DP_TRAINING_TBL_ADDR + 16 )
++#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 24 )
++#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 32)
++#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                     (ATOM_DP_TRAINING_TBL_ADDR + 40)
++#define   DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                     (ATOM_DP_TRAINING_TBL_ADDR + 48)
++#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 60)
++#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                 (ATOM_DP_TRAINING_TBL_ADDR + 64)
++#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 72)
++#define DP_I2C_AUX_DDC_READ_TBL_ADDR                                 (ATOM_DP_TRAINING_TBL_ADDR + 76)
++#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR                 (ATOM_DP_TRAINING_TBL_ADDR + 80)
++#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                           (ATOM_DP_TRAINING_TBL_ADDR + 84)
++
++
++typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
++{
++   UCHAR   ucI2CSpeed;
++    union
++   {
++   UCHAR ucRegIndex;
++   UCHAR ucStatus;
++   };
++   USHORT  lpI2CDataOut;
++  UCHAR   ucFlag;
++  UCHAR   ucTransBytes;
++  UCHAR   ucSlaveAddr;
++  UCHAR   ucLineNumber;
++}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
++
++#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
++
++//ucFlag
++#define HW_I2C_WRITE        1
++#define HW_I2C_READ         0
++#define I2C_2BYTE_ADDR      0x02
++
++/****************************************************************************/
++// Structures used by HW_Misc_OperationTable
++/****************************************************************************/
++typedef struct  _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
++{
++  UCHAR  ucCmd;                //  Input: To tell which action to take
++  UCHAR  ucReserved[3];
++  ULONG  ulReserved;
++}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
++
++typedef struct  _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
++{
++  UCHAR  ucReturnCode;        // Output: Return value base on action was taken
++  UCHAR  ucReserved[3];
++  ULONG  ulReserved;
++}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
++
++// Actions code
++#define  ATOM_GET_SDI_SUPPORT              0xF0
++
++// Return code
++#define  ATOM_UNKNOWN_CMD                   0
++#define  ATOM_FEATURE_NOT_SUPPORTED         1
++#define  ATOM_FEATURE_SUPPORTED             2
++
++typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
++{
++   ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1        sInput_Output;
++   PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS         sReserved;
++}ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
++
++/****************************************************************************/
++
++typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
++{
++   UCHAR ucHWBlkInst;                // HW block instance, 0, 1, 2, ...
++   UCHAR ucReserved[3];
++}SET_HWBLOCK_INSTANCE_PARAMETER_V2;
++
++#define HWBLKINST_INSTANCE_MASK       0x07
++#define HWBLKINST_HWBLK_MASK          0xF0
++#define HWBLKINST_HWBLK_SHIFT         0x04
++
++//ucHWBlock
++#define SELECT_DISP_ENGINE            0
++#define SELECT_DISP_PLL               1
++#define SELECT_DCIO_UNIPHY_LINK0      2
++#define SELECT_DCIO_UNIPHY_LINK1      3
++#define SELECT_DCIO_IMPCAL            4
++#define SELECT_DCIO_DIG               6
++#define SELECT_CRTC_PIXEL_RATE        7
++#define SELECT_VGA_BLK                8
++
++// DIGTransmitterInfoTable structure used to program UNIPHY settings
++typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
++  USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
++  USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
++  USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
++}DIG_TRANSMITTER_INFO_HEADER_V3_1;
++
++typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
++  USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
++  USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
++  USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
++  USHORT usDPSSRegListOffset;            // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
++  USHORT usDPSSSettingOffset;            // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
++}DIG_TRANSMITTER_INFO_HEADER_V3_2;
++
++
++typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
++  USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
++  USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
++  USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
++  USHORT usDPSSRegListOffset;            // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
++  USHORT usDPSSSettingOffset;            // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
++  USHORT usEDPVsLegacyModeOffset;        // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT useDPVsLowVdiffModeOffset;      // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT useDPVsHighVdiffModeOffset;     // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT useDPVsStretchModeOffset;       // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT useDPVsSingleVdiffModeOffset;   // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock
++  USHORT useDPVsVariablePremModeOffset;  // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock
++}DIG_TRANSMITTER_INFO_HEADER_V3_3;
++
++
++typedef struct _CLOCK_CONDITION_REGESTER_INFO{
++  USHORT usRegisterIndex;
++  UCHAR  ucStartBit;
++  UCHAR  ucEndBit;
++}CLOCK_CONDITION_REGESTER_INFO;
++
++typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
++  USHORT usMaxClockFreq;
++  UCHAR  ucEncodeMode;
++  UCHAR  ucPhySel;
++  ULONG  ulAnalogSetting[1];
++}CLOCK_CONDITION_SETTING_ENTRY;
++
++typedef struct _CLOCK_CONDITION_SETTING_INFO{
++  USHORT usEntrySize;
++  CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
++}CLOCK_CONDITION_SETTING_INFO;
++
++typedef struct _PHY_CONDITION_REG_VAL{
++  ULONG  ulCondition;
++  ULONG  ulRegVal;
++}PHY_CONDITION_REG_VAL;
++
++typedef struct _PHY_CONDITION_REG_VAL_V2{
++  ULONG  ulCondition;
++  UCHAR  ucCondition2;
++  ULONG  ulRegVal;
++}PHY_CONDITION_REG_VAL_V2;
++
++typedef struct _PHY_CONDITION_REG_INFO{
++  USHORT usRegIndex;
++  USHORT usSize;
++  PHY_CONDITION_REG_VAL asRegVal[1];
++}PHY_CONDITION_REG_INFO;
++
++typedef struct _PHY_CONDITION_REG_INFO_V2{
++  USHORT usRegIndex;
++  USHORT usSize;
++  PHY_CONDITION_REG_VAL_V2 asRegVal[1];
++}PHY_CONDITION_REG_INFO_V2;
++
++typedef struct _PHY_ANALOG_SETTING_INFO{
++  UCHAR  ucEncodeMode;
++  UCHAR  ucPhySel;
++  USHORT usSize;
++  PHY_CONDITION_REG_INFO  asAnalogSetting[1];
++}PHY_ANALOG_SETTING_INFO;
++
++typedef struct _PHY_ANALOG_SETTING_INFO_V2{
++  UCHAR  ucEncodeMode;
++  UCHAR  ucPhySel;
++  USHORT usSize;
++  PHY_CONDITION_REG_INFO_V2  asAnalogSetting[1];
++}PHY_ANALOG_SETTING_INFO_V2;
++
++
++typedef struct _GFX_HAVESTING_PARAMETERS {
++  UCHAR ucGfxBlkId;                        //GFX blk id to be harvested, like CU, RB or PRIM
++  UCHAR ucReserved;                        //reserved
++  UCHAR ucActiveUnitNumPerSH;              //requested active CU/RB/PRIM number per shader array
++  UCHAR ucMaxUnitNumPerSH;                 //max CU/RB/PRIM number per shader array
++} GFX_HAVESTING_PARAMETERS;
++
++//ucGfxBlkId
++#define GFX_HARVESTING_CU_ID               0
++#define GFX_HARVESTING_RB_ID               1
++#define GFX_HARVESTING_PRIM_ID             2
++
++
++typedef struct _VBIOS_ROM_HEADER{
++  UCHAR  PciRomSignature[2];
++  UCHAR  ucPciRomSizeIn512bytes;
++  UCHAR  ucJumpCoreMainInitBIOS;
++  USHORT usLabelCoreMainInitBIOS;
++  UCHAR  PciReservedSpace[18];
++  USHORT usPciDataStructureOffset;
++  UCHAR  Rsvd1d_1a[4];
++  char   strIbm[3];
++  UCHAR  CheckSum[14];
++  UCHAR  ucBiosMsgNumber;
++  char   str761295520[16];
++  USHORT usLabelCoreVPOSTNoMode;
++  USHORT usSpecialPostOffset;
++  UCHAR  ucSpeicalPostImageSizeIn512Bytes;
++  UCHAR  Rsved47_45[3];
++  USHORT usROM_HeaderInformationTableOffset;
++  UCHAR  Rsved4f_4a[6];
++  char   strBuildTimeStamp[20];
++  UCHAR  ucJumpCoreXFuncFarHandler;
++  USHORT usCoreXFuncFarHandlerOffset;
++  UCHAR  ucRsved67;
++  UCHAR  ucJumpCoreVFuncFarHandler;
++  USHORT usCoreVFuncFarHandlerOffset;
++  UCHAR  Rsved6d_6b[3];
++  USHORT usATOM_BIOS_MESSAGE_Offset;
++}VBIOS_ROM_HEADER;
++
++/****************************************************************************/
++//Portion VI: Definitinos for vbios MC scratch registers that driver used
++/****************************************************************************/
++
++#define MC_MISC0__MEMORY_TYPE_MASK    0xF0000000
++#define MC_MISC0__MEMORY_TYPE__GDDR1  0x10000000
++#define MC_MISC0__MEMORY_TYPE__DDR2   0x20000000
++#define MC_MISC0__MEMORY_TYPE__GDDR3  0x30000000
++#define MC_MISC0__MEMORY_TYPE__GDDR4  0x40000000
++#define MC_MISC0__MEMORY_TYPE__GDDR5  0x50000000
++#define MC_MISC0__MEMORY_TYPE__HBM    0x60000000
++#define MC_MISC0__MEMORY_TYPE__DDR3   0xB0000000
++
++#define ATOM_MEM_TYPE_DDR_STRING      "DDR"
++#define ATOM_MEM_TYPE_DDR2_STRING     "DDR2"
++#define ATOM_MEM_TYPE_GDDR3_STRING    "GDDR3"
++#define ATOM_MEM_TYPE_GDDR4_STRING    "GDDR4"
++#define ATOM_MEM_TYPE_GDDR5_STRING    "GDDR5"
++#define ATOM_MEM_TYPE_HBM_STRING      "HBM"
++#define ATOM_MEM_TYPE_DDR3_STRING     "DDR3"
++
++/****************************************************************************/
++//Portion VII: Definitinos being oboselete
++/****************************************************************************/
++
++//==========================================================================================
++//Remove the definitions below when driver is ready!
++typedef struct _ATOM_DAC_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT                   usMaxFrequency;      // in 10kHz unit
++  USHORT                   usReserved;
++}ATOM_DAC_INFO;
++
++
++typedef struct  _COMPASSIONATE_DATA
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++
++  //==============================  DAC1 portion
++  UCHAR   ucDAC1_BG_Adjustment;
++  UCHAR   ucDAC1_DAC_Adjustment;
++  USHORT  usDAC1_FORCE_Data;
++  //==============================  DAC2 portion
++  UCHAR   ucDAC2_CRT2_BG_Adjustment;
++  UCHAR   ucDAC2_CRT2_DAC_Adjustment;
++  USHORT  usDAC2_CRT2_FORCE_Data;
++  USHORT  usDAC2_CRT2_MUX_RegisterIndex;
++  UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
++  UCHAR   ucDAC2_NTSC_BG_Adjustment;
++  UCHAR   ucDAC2_NTSC_DAC_Adjustment;
++  USHORT  usDAC2_TV1_FORCE_Data;
++  USHORT  usDAC2_TV1_MUX_RegisterIndex;
++  UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
++  UCHAR   ucDAC2_CV_BG_Adjustment;
++  UCHAR   ucDAC2_CV_DAC_Adjustment;
++  USHORT  usDAC2_CV_FORCE_Data;
++  USHORT  usDAC2_CV_MUX_RegisterIndex;
++  UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
++  UCHAR   ucDAC2_PAL_BG_Adjustment;
++  UCHAR   ucDAC2_PAL_DAC_Adjustment;
++  USHORT  usDAC2_TV2_FORCE_Data;
++}COMPASSIONATE_DATA;
++
++/****************************Supported Device Info Table Definitions**********************/
++//  ucConnectInfo:
++//    [7:4] - connector type
++//      = 1   - VGA connector
++//      = 2   - DVI-I
++//      = 3   - DVI-D
++//      = 4   - DVI-A
++//      = 5   - SVIDEO
++//      = 6   - COMPOSITE
++//      = 7   - LVDS
++//      = 8   - DIGITAL LINK
++//      = 9   - SCART
++//      = 0xA - HDMI_type A
++//      = 0xB - HDMI_type B
++//      = 0xE - Special case1 (DVI+DIN)
++//      Others=TBD
++//    [3:0] - DAC Associated
++//      = 0   - no DAC
++//      = 1   - DACA
++//      = 2   - DACB
++//      = 3   - External DAC
++//      Others=TBD
++//
++
++typedef struct _ATOM_CONNECTOR_INFO
++{
++#if ATOM_BIG_ENDIAN
++  UCHAR   bfConnectorType:4;
++  UCHAR   bfAssociatedDAC:4;
++#else
++  UCHAR   bfAssociatedDAC:4;
++  UCHAR   bfConnectorType:4;
++#endif
++}ATOM_CONNECTOR_INFO;
++
++typedef union _ATOM_CONNECTOR_INFO_ACCESS
++{
++  ATOM_CONNECTOR_INFO sbfAccess;
++  UCHAR               ucAccess;
++}ATOM_CONNECTOR_INFO_ACCESS;
++
++typedef struct _ATOM_CONNECTOR_INFO_I2C
++{
++  ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
++  ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;
++}ATOM_CONNECTOR_INFO_I2C;
++
++
++typedef struct _ATOM_SUPPORTED_DEVICES_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                    usDeviceSupport;
++  ATOM_CONNECTOR_INFO_I2C   asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
++}ATOM_SUPPORTED_DEVICES_INFO;
++
++#define NO_INT_SRC_MAPPED       0xFF
++
++typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
++{
++  UCHAR   ucIntSrcBitmap;
++}ATOM_CONNECTOR_INC_SRC_BITMAP;
++
++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
++{
++  ATOM_COMMON_TABLE_HEADER      sHeader;
++  USHORT                        usDeviceSupport;
++  ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
++  ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
++}ATOM_SUPPORTED_DEVICES_INFO_2;
++
++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
++{
++  ATOM_COMMON_TABLE_HEADER      sHeader;
++  USHORT                        usDeviceSupport;
++  ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
++  ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
++}ATOM_SUPPORTED_DEVICES_INFO_2d1;
++
++#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
++
++
++
++typedef struct _ATOM_MISC_CONTROL_INFO
++{
++   USHORT usFrequency;
++   UCHAR  ucPLL_ChargePump;                            // PLL charge-pump gain control
++   UCHAR  ucPLL_DutyCycle;                            // PLL duty cycle control
++   UCHAR  ucPLL_VCO_Gain;                              // PLL VCO gain control
++   UCHAR  ucPLL_VoltageSwing;                         // PLL driver voltage swing control
++}ATOM_MISC_CONTROL_INFO;
++
++
++#define ATOM_MAX_MISC_INFO       4
++
++typedef struct _ATOM_TMDS_INFO
++{
++  ATOM_COMMON_TABLE_HEADER sHeader;
++  USHORT                     usMaxFrequency;             // in 10Khz
++  ATOM_MISC_CONTROL_INFO            asMiscInfo[ATOM_MAX_MISC_INFO];
++}ATOM_TMDS_INFO;
++
++
++typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
++{
++  UCHAR ucTVStandard;     //Same as TV standards defined above,
++  UCHAR ucPadding[1];
++}ATOM_ENCODER_ANALOG_ATTRIBUTE;
++
++typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
++{
++  UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
++  UCHAR ucPadding[1];
++}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
++
++typedef union _ATOM_ENCODER_ATTRIBUTE
++{
++  ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
++  ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
++}ATOM_ENCODER_ATTRIBUTE;
++
++
++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
++{
++  USHORT usPixelClock;
++  USHORT usEncoderID;
++  UCHAR  ucDeviceType;                                    //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
++  UCHAR  ucAction;                                          //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
++  ATOM_ENCODER_ATTRIBUTE usDevAttr;
++}DVO_ENCODER_CONTROL_PARAMETERS;
++
++typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
++{
++  DVO_ENCODER_CONTROL_PARAMETERS    sDVOEncoder;
++  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
++}DVO_ENCODER_CONTROL_PS_ALLOCATION;
++
++
++#define ATOM_XTMDS_ASIC_SI164_ID        1
++#define ATOM_XTMDS_ASIC_SI178_ID        2
++#define ATOM_XTMDS_ASIC_TFP513_ID       3
++#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
++#define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
++#define ATOM_XTMDS_MVPU_FPGA            0x00000004
++
++
++typedef struct _ATOM_XTMDS_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  USHORT                     usSingleLinkMaxFrequency;
++  ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
++  UCHAR                      ucXtransimitterID;
++  UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
++  UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters
++                                                 // due to design. This ID is used to alert driver that the sequence is not "standard"!
++  UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
++  UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
++}ATOM_XTMDS_INFO;
++
++typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
++{
++  UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
++  UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
++  UCHAR ucPadding[2];
++}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
++
++/****************************Legacy Power Play Table Definitions **********************/
++
++//Definitions for ulPowerPlayMiscInfo
++#define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
++#define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
++#define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
++
++#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
++#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
++
++#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
++
++#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
++#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
++#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
++
++#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
++#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
++#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
++#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
++#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
++#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
++#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
++
++#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
++#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
++#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
++#define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
++#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
++
++#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
++#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
++
++#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
++#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
++#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
++#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic
++#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
++#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
++
++#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
++#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
++#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
++
++#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
++#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
++#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
++#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
++#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
++#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
++#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
++                                                                      //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
++#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
++#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
++#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
++
++//ucTableFormatRevision=1
++//ucTableContentRevision=1
++typedef struct  _ATOM_POWERMODE_INFO
++{
++  ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
++  ULONG     ulReserved1;                // must set to 0
++  ULONG     ulReserved2;                // must set to 0
++  USHORT    usEngineClock;
++  USHORT    usMemoryClock;
++  UCHAR     ucVoltageDropIndex;         // index to GPIO table
++  UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
++  UCHAR     ucMinTemperature;
++  UCHAR     ucMaxTemperature;
++  UCHAR     ucNumPciELanes;             // number of PCIE lanes
++}ATOM_POWERMODE_INFO;
++
++//ucTableFormatRevision=2
++//ucTableContentRevision=1
++typedef struct  _ATOM_POWERMODE_INFO_V2
++{
++  ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
++  ULONG     ulMiscInfo2;
++  ULONG     ulEngineClock;
++  ULONG     ulMemoryClock;
++  UCHAR     ucVoltageDropIndex;         // index to GPIO table
++  UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
++  UCHAR     ucMinTemperature;
++  UCHAR     ucMaxTemperature;
++  UCHAR     ucNumPciELanes;             // number of PCIE lanes
++}ATOM_POWERMODE_INFO_V2;
++
++//ucTableFormatRevision=2
++//ucTableContentRevision=2
++typedef struct  _ATOM_POWERMODE_INFO_V3
++{
++  ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
++  ULONG     ulMiscInfo2;
++  ULONG     ulEngineClock;
++  ULONG     ulMemoryClock;
++  UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
++  UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
++  UCHAR     ucMinTemperature;
++  UCHAR     ucMaxTemperature;
++  UCHAR     ucNumPciELanes;             // number of PCIE lanes
++  UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
++}ATOM_POWERMODE_INFO_V3;
++
++
++#define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
++
++#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
++#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
++
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07   // Andigilog
++
++
++typedef struct  _ATOM_POWERPLAY_INFO
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  UCHAR    ucOverdriveThermalController;
++  UCHAR    ucOverdriveI2cLine;
++  UCHAR    ucOverdriveIntBitmap;
++  UCHAR    ucOverdriveControllerAddress;
++  UCHAR    ucSizeOfPowerModeEntry;
++  UCHAR    ucNumOfPowerModeEntries;
++  ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
++}ATOM_POWERPLAY_INFO;
++
++typedef struct  _ATOM_POWERPLAY_INFO_V2
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  UCHAR    ucOverdriveThermalController;
++  UCHAR    ucOverdriveI2cLine;
++  UCHAR    ucOverdriveIntBitmap;
++  UCHAR    ucOverdriveControllerAddress;
++  UCHAR    ucSizeOfPowerModeEntry;
++  UCHAR    ucNumOfPowerModeEntries;
++  ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
++}ATOM_POWERPLAY_INFO_V2;
++
++typedef struct  _ATOM_POWERPLAY_INFO_V3
++{
++  ATOM_COMMON_TABLE_HEADER   sHeader;
++  UCHAR    ucOverdriveThermalController;
++  UCHAR    ucOverdriveI2cLine;
++  UCHAR    ucOverdriveIntBitmap;
++  UCHAR    ucOverdriveControllerAddress;
++  UCHAR    ucSizeOfPowerModeEntry;
++  UCHAR    ucNumOfPowerModeEntries;
++  ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
++}ATOM_POWERPLAY_INFO_V3;
++
++
++
++/**************************************************************************/
++
++
++// Following definitions are for compatiblity issue in different SW components.
++#define ATOM_MASTER_DATA_TABLE_REVISION   0x01
++#define Object_Info                       Object_Header
++#define AdjustARB_SEQ                     MC_InitParameter
++#define VRAM_GPIO_DetectionInfo           VoltageObjectInfo
++#define ASIC_VDDCI_Info                   ASIC_ProfilingInfo
++#define ASIC_MVDDQ_Info                   MemoryTrainingInfo
++#define SS_Info                           PPLL_SS_Info
++#define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
++#define DispDevicePriorityInfo            SaveRestoreInfo
++#define DispOutInfo                       TV_VideoMode
++
++
++#define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
++#define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
++
++//New device naming, remove them when both DAL/VBIOS is ready
++#define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
++#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
++
++#define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
++#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
++
++#define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
++#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
++
++#define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
++#define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
++
++#define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
++#define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
++
++#define ATOM_DEVICE_DFP2I_INDEX            0x00000009
++#define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
++
++#define ATOM_S0_DFP1I                      ATOM_S0_DFP1
++#define ATOM_S0_DFP1X                      ATOM_S0_DFP2
++
++#define ATOM_S0_DFP2I                      0x00200000L
++#define ATOM_S0_DFP2Ib2                    0x20
++
++#define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
++#define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
++
++#define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
++#define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
++
++#define ATOM_S3_DFP2I_ACTIVEb1             0x02
++
++#define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
++#define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
++
++#define ATOM_S3_DFP2I_ACTIVE               0x00000200L
++
++#define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
++#define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
++#define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
++
++
++#define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
++#define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
++
++#define ATOM_S5_DOS_REQ_DFP2I              0x0200
++#define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
++#define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
++
++#define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
++#define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
++
++#define TMDS1XEncoderControl               DVOEncoderControl
++#define DFP1XOutputControl                 DVOOutputControl
++
++#define ExternalDFPOutputControl           DFP1XOutputControl
++#define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
++
++#define DFP1IOutputControl                 TMDSAOutputControl
++#define DFP2IOutputControl                 LVTMAOutputControl
++
++#define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
++#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
++
++#define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
++#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
++
++#define ucDac1Standard  ucDacStandard
++#define ucDac2Standard  ucDacStandard
++
++#define TMDS1EncoderControl TMDSAEncoderControl
++#define TMDS2EncoderControl LVTMAEncoderControl
++
++#define DFP1OutputControl   TMDSAOutputControl
++#define DFP2OutputControl   LVTMAOutputControl
++#define CRT1OutputControl   DAC1OutputControl
++#define CRT2OutputControl   DAC2OutputControl
++
++//These two lines will be removed for sure in a few days, will follow up with Michael V.
++#define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
++#define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL
++
++#define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
++#define ATOM_S2_LCD1_DPMS_STATE           ATOM_S2_CRT1_DPMS_STATE
++#define ATOM_S2_TV1_DPMS_STATE          ATOM_S2_CRT1_DPMS_STATE
++#define ATOM_S2_DFP1_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
++#define ATOM_S2_CRT2_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
++
++#define ATOM_S6_ACC_REQ_TV2             0x00400000L
++#define ATOM_DEVICE_TV2_INDEX           0x00000006
++#define ATOM_DEVICE_TV2_SUPPORT         (0x1L << ATOM_DEVICE_TV2_INDEX)
++#define ATOM_S0_TV2                     0x00100000L
++#define ATOM_S3_TV2_ACTIVE              ATOM_S3_DFP6_ACTIVE
++#define ATOM_S3_TV2_CRTC_ACTIVE         ATOM_S3_DFP6_CRTC_ACTIVE
++
++/*********************************************************************************/
++
++#pragma pack() // BIOS data must use byte aligment
++
++#pragma pack(1)
++
++typedef struct _ATOM_HOLE_INFO
++{
++	USHORT	usOffset;		// offset of the hole ( from the start of the binary )
++	USHORT	usLength;		// length of the hole ( in bytes )
++}ATOM_HOLE_INFO;
++
++typedef struct _ATOM_SERVICE_DESCRIPTION
++{
++   UCHAR   ucRevision;                               // Holes set revision
++   UCHAR   ucAlgorithm;                              // Hash algorithm
++   UCHAR   ucSignatureType;							 // Signature type ( 0 - no signature, 1 - test, 2 - production )
++   UCHAR   ucReserved;
++   USHORT  usSigOffset;							     // Signature offset ( from the start of the binary )
++   USHORT  usSigLength;                              // Signature length
++}ATOM_SERVICE_DESCRIPTION;
++
++
++typedef struct _ATOM_SERVICE_INFO
++{
++      ATOM_COMMON_TABLE_HEADER      asHeader;
++      ATOM_SERVICE_DESCRIPTION		asDescr;
++	  UCHAR							ucholesNo;		// number of holes that follow
++	  ATOM_HOLE_INFO				holes[1];       // array of hole descriptions
++}ATOM_SERVICE_INFO;
++
++
++
++#pragma pack() // BIOS data must use byte aligment
++
++//
++// AMD ACPI Table
++//
++#pragma pack(1)
++
++typedef struct {
++  ULONG Signature;
++  ULONG TableLength;      //Length
++  UCHAR Revision;
++  UCHAR Checksum;
++  UCHAR OemId[6];
++  UCHAR OemTableId[8];    //UINT64  OemTableId;
++  ULONG OemRevision;
++  ULONG CreatorId;
++  ULONG CreatorRevision;
++} AMD_ACPI_DESCRIPTION_HEADER;
++/*
++//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
++typedef struct {
++  UINT32  Signature;       //0x0
++  UINT32  Length;          //0x4
++  UINT8   Revision;        //0x8
++  UINT8   Checksum;        //0x9
++  UINT8   OemId[6];        //0xA
++  UINT64  OemTableId;      //0x10
++  UINT32  OemRevision;     //0x18
++  UINT32  CreatorId;       //0x1C
++  UINT32  CreatorRevision; //0x20
++}EFI_ACPI_DESCRIPTION_HEADER;
++*/
++typedef struct {
++  AMD_ACPI_DESCRIPTION_HEADER SHeader;
++  UCHAR TableUUID[16];    //0x24
++  ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
++  ULONG Lib1ImageOffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
++  ULONG Reserved[4];      //0x3C
++}UEFI_ACPI_VFCT;
++
++typedef struct {
++  ULONG  PCIBus;          //0x4C
++  ULONG  PCIDevice;       //0x50
++  ULONG  PCIFunction;     //0x54
++  USHORT VendorID;        //0x58
++  USHORT DeviceID;        //0x5A
++  USHORT SSVID;           //0x5C
++  USHORT SSID;            //0x5E
++  ULONG  Revision;        //0x60
++  ULONG  ImageLength;     //0x64
++}VFCT_IMAGE_HEADER;
++
++
++typedef struct {
++  VFCT_IMAGE_HEADER   VbiosHeader;
++  UCHAR   VbiosContent[1];
++}GOP_VBIOS_CONTENT;
++
++typedef struct {
++  VFCT_IMAGE_HEADER   Lib1Header;
++  UCHAR   Lib1Content[1];
++}GOP_LIB1_CONTENT;
++
++#pragma pack()
++
++
++#endif /* _ATOMBIOS_H */
++
++#include "pptable.h"
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/pptable.h b/drivers/gpu/drm/amd/amdgpu/pptable.h
+new file mode 100644
+index 0000000..0030f72
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/pptable.h
+@@ -0,0 +1,698 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef _PPTABLE_H
++#define _PPTABLE_H
++
++#pragma pack(1)
++
++typedef struct _ATOM_PPLIB_THERMALCONTROLLER
++
++{
++    UCHAR ucType;           // one of ATOM_PP_THERMALCONTROLLER_*
++    UCHAR ucI2cLine;        // as interpreted by DAL I2C
++    UCHAR ucI2cAddress;
++    UCHAR ucFanParameters;  // Fan Control Parameters.
++    UCHAR ucFanMinRPM;      // Fan Minimum RPM (hundreds) -- for display purposes only.
++    UCHAR ucFanMaxRPM;      // Fan Maximum RPM (hundreds) -- for display purposes only.
++    UCHAR ucReserved;       // ----
++    UCHAR ucFlags;          // to be defined
++} ATOM_PPLIB_THERMALCONTROLLER;
++
++#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
++#define ATOM_PP_FANPARAMETERS_NOFAN                                 0x80    // No fan is connected to this controller.
++
++#define ATOM_PP_THERMALCONTROLLER_NONE      0
++#define ATOM_PP_THERMALCONTROLLER_LM63      1  // Not used by PPLib
++#define ATOM_PP_THERMALCONTROLLER_ADM1032   2  // Not used by PPLib
++#define ATOM_PP_THERMALCONTROLLER_ADM1030   3  // Not used by PPLib
++#define ATOM_PP_THERMALCONTROLLER_MUA6649   4  // Not used by PPLib
++#define ATOM_PP_THERMALCONTROLLER_LM64      5
++#define ATOM_PP_THERMALCONTROLLER_F75375    6  // Not used by PPLib
++#define ATOM_PP_THERMALCONTROLLER_RV6xx     7
++#define ATOM_PP_THERMALCONTROLLER_RV770     8
++#define ATOM_PP_THERMALCONTROLLER_ADT7473   9
++#define ATOM_PP_THERMALCONTROLLER_KONG      10
++#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO     11
++#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
++#define ATOM_PP_THERMALCONTROLLER_EMC2103   13  /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
++#define ATOM_PP_THERMALCONTROLLER_SUMO      14  /* 0x0E */ // Sumo type, used internally
++#define ATOM_PP_THERMALCONTROLLER_NISLANDS  15
++#define ATOM_PP_THERMALCONTROLLER_SISLANDS  16
++#define ATOM_PP_THERMALCONTROLLER_LM96163   17
++#define ATOM_PP_THERMALCONTROLLER_CISLANDS  18
++#define ATOM_PP_THERMALCONTROLLER_KAVERI    19
++
++
++// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
++// We probably should reserve the bit 0x80 for this use.
++// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
++// The driver can pick the correct internal controller based on the ASIC.
++
++#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL   0x89    // ADT7473 Fan Control + Internal Thermal Controller
++#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL   0x8D    // EMC2103 Fan Control + Internal Thermal Controller
++
++typedef struct _ATOM_PPLIB_STATE
++{
++    UCHAR ucNonClockStateIndex;
++    UCHAR ucClockStateIndices[1]; // variable-sized
++} ATOM_PPLIB_STATE;
++
++
++typedef struct _ATOM_PPLIB_FANTABLE
++{
++    UCHAR   ucFanTableFormat;                // Change this if the table format changes or version changes so that the other fields are not the same.
++    UCHAR   ucTHyst;                         // Temperature hysteresis. Integer.
++    USHORT  usTMin;                          // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
++    USHORT  usTMed;                          // The middle temperature where we change slopes.
++    USHORT  usTHigh;                         // The high point above TMed for adjusting the second slope.
++    USHORT  usPWMMin;                        // The minimum PWM value in percent (0.01% increments).
++    USHORT  usPWMMed;                        // The PWM value (in percent) at TMed.
++    USHORT  usPWMHigh;                       // The PWM value at THigh.
++} ATOM_PPLIB_FANTABLE;
++
++typedef struct _ATOM_PPLIB_FANTABLE2
++{
++    ATOM_PPLIB_FANTABLE basicTable;
++    USHORT  usTMax;                          // The max temperature
++} ATOM_PPLIB_FANTABLE2;
++
++typedef struct _ATOM_PPLIB_FANTABLE3
++{
++	ATOM_PPLIB_FANTABLE2 basicTable2;
++	UCHAR ucFanControlMode;
++	USHORT usFanPWMMax;
++	USHORT usFanOutputSensitivity;
++} ATOM_PPLIB_FANTABLE3;
++
++typedef struct _ATOM_PPLIB_EXTENDEDHEADER
++{
++    USHORT  usSize;
++    ULONG   ulMaxEngineClock;   // For Overdrive.
++    ULONG   ulMaxMemoryClock;   // For Overdrive.
++    // Add extra system parameters here, always adjust size to include all fields.
++    USHORT  usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
++    USHORT  usUVDTableOffset;   //points to ATOM_PPLIB_UVD_Table
++    USHORT  usSAMUTableOffset;  //points to ATOM_PPLIB_SAMU_Table
++    USHORT  usPPMTableOffset;   //points to ATOM_PPLIB_PPM_Table
++    USHORT  usACPTableOffset;  //points to ATOM_PPLIB_ACP_Table   
++    /* points to ATOM_PPLIB_POWERTUNE_Table */
++    USHORT  usPowerTuneTableOffset;
++    /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
++    USHORT  usSclkVddgfxTableOffset;
++} ATOM_PPLIB_EXTENDEDHEADER;
++
++//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
++#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
++#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
++#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
++#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
++#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
++#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
++#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
++#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
++#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
++#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
++#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
++#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
++#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
++#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000              // Go to boot state on alerts, e.g. on an AC->DC transition.
++#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000   // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
++#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000                   // Does the driver control VDDCI independently from VDDC.
++#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000               // Enable the 'regulator hot' feature.
++#define ATOM_PP_PLATFORM_CAP_BACO          0x00020000               // Does the driver supports BACO state.
++#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE   0x00040000           // Does the driver supports new CAC voltage table.
++#define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY   0x00080000     // Does the driver supports revert GPIO5 polarity.
++#define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17   0x00100000     // Does the driver supports thermal2GPIO17.
++#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE   0x00200000   // Does the driver supports VR HOT GPIO Configurable.
++#define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION   0x00400000            // Does the driver supports Temp Inversion feature.
++#define ATOM_PP_PLATFORM_CAP_EVV    0x00800000
++
++typedef struct _ATOM_PPLIB_POWERPLAYTABLE
++{
++      ATOM_COMMON_TABLE_HEADER sHeader;
++
++      UCHAR ucDataRevision;
++
++      UCHAR ucNumStates;
++      UCHAR ucStateEntrySize;
++      UCHAR ucClockInfoSize;
++      UCHAR ucNonClockSize;
++
++      // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
++      USHORT usStateArrayOffset;
++
++      // offset from start of this table to array of ASIC-specific structures,
++      // currently ATOM_PPLIB_CLOCK_INFO.
++      USHORT usClockInfoArrayOffset;
++
++      // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
++      USHORT usNonClockInfoArrayOffset;
++
++      USHORT usBackbiasTime;    // in microseconds
++      USHORT usVoltageTime;     // in microseconds
++      USHORT usTableSize;       //the size of this structure, or the extended structure
++
++      ULONG ulPlatformCaps;            // See ATOM_PPLIB_CAPS_*
++
++      ATOM_PPLIB_THERMALCONTROLLER    sThermalController;
++
++      USHORT usBootClockInfoOffset;
++      USHORT usBootNonClockInfoOffset;
++
++} ATOM_PPLIB_POWERPLAYTABLE;
++
++typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
++{
++    ATOM_PPLIB_POWERPLAYTABLE basicTable;
++    UCHAR   ucNumCustomThermalPolicy;
++    USHORT  usCustomThermalPolicyArrayOffset;
++}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
++
++typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
++{
++    ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
++    USHORT                     usFormatID;                      // To be used ONLY by PPGen.
++    USHORT                     usFanTableOffset;
++    USHORT                     usExtendendedHeaderOffset;
++} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
++
++typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
++{
++    ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
++    ULONG                      ulGoldenPPID;                    // PPGen use only     
++    ULONG                      ulGoldenRevision;                // PPGen use only
++    USHORT                     usVddcDependencyOnSCLKOffset;
++    USHORT                     usVddciDependencyOnMCLKOffset;
++    USHORT                     usVddcDependencyOnMCLKOffset;
++    USHORT                     usMaxClockVoltageOnDCOffset;
++    USHORT                     usVddcPhaseShedLimitsTableOffset;    // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
++    USHORT                     usMvddDependencyOnMCLKOffset;  
++} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
++
++typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
++{
++    ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
++    ULONG                      ulTDPLimit;
++    ULONG                      ulNearTDPLimit;
++    ULONG                      ulSQRampingThreshold;
++    USHORT                     usCACLeakageTableOffset;         // Points to ATOM_PPLIB_CAC_Leakage_Table
++    ULONG                      ulCACLeakage;                    // The iLeakage for driver calculated CAC leakage table
++    USHORT                     usTDPODLimit;
++    USHORT                     usLoadLineSlope;                 // in milliOhms * 100
++} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
++
++//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
++#define ATOM_PPLIB_CLASSIFICATION_UI_MASK          0x0007
++#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT         0
++#define ATOM_PPLIB_CLASSIFICATION_UI_NONE          0
++#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY       1
++#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED      3
++#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE   5
++// 2, 4, 6, 7 are reserved
++
++#define ATOM_PPLIB_CLASSIFICATION_BOOT                   0x0008
++#define ATOM_PPLIB_CLASSIFICATION_THERMAL                0x0010
++#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE     0x0020
++#define ATOM_PPLIB_CLASSIFICATION_REST                   0x0040
++#define ATOM_PPLIB_CLASSIFICATION_FORCED                 0x0080
++#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE          0x0100
++#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE      0x0200
++#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE               0x0400
++#define ATOM_PPLIB_CLASSIFICATION_3DLOW                  0x0800
++#define ATOM_PPLIB_CLASSIFICATION_ACPI                   0x1000
++#define ATOM_PPLIB_CLASSIFICATION_HD2STATE               0x2000
++#define ATOM_PPLIB_CLASSIFICATION_HDSTATE                0x4000
++#define ATOM_PPLIB_CLASSIFICATION_SDSTATE                0x8000
++
++//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
++#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2     0x0001
++#define ATOM_PPLIB_CLASSIFICATION2_ULV                      0x0002
++#define ATOM_PPLIB_CLASSIFICATION2_MVC                      0x0004   //Multi-View Codec (BD-3D)
++
++//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
++#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY           0x00000001
++#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK         0x00000002
++
++// 0 is 2.5Gb/s, 1 is 5Gb/s
++#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK            0x00000004
++#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT           2
++
++// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
++#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK            0x000000F8
++#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT           3
++
++// lookup into reduced refresh-rate table
++#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK  0x00000F00
++#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
++
++#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED    0
++#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ         1
++// 2-15 TBD as needed.
++
++#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING        0x00001000
++#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS  0x00002000
++
++#define ATOM_PPLIB_DISALLOW_ON_DC                       0x00004000
++
++#define ATOM_PPLIB_ENABLE_VARIBRIGHT                     0x00008000
++
++//memory related flags
++#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF               0x000010000
++
++//M3 Arb    //2bits, current 3 sets of parameters in total
++#define ATOM_PPLIB_M3ARB_MASK                       0x00060000
++#define ATOM_PPLIB_M3ARB_SHIFT                      17
++
++#define ATOM_PPLIB_ENABLE_DRR                       0x00080000
++
++// remaining 16 bits are reserved
++typedef struct _ATOM_PPLIB_THERMAL_STATE
++{
++    UCHAR   ucMinTemperature;
++    UCHAR   ucMaxTemperature;
++    UCHAR   ucThermalAction;
++}ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
++
++// Contained in an array starting at the offset
++// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
++// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
++#define ATOM_PPLIB_NONCLOCKINFO_VER1      12
++#define ATOM_PPLIB_NONCLOCKINFO_VER2      24
++typedef struct _ATOM_PPLIB_NONCLOCK_INFO
++{
++      USHORT usClassification;
++      UCHAR  ucMinTemperature;
++      UCHAR  ucMaxTemperature;
++      ULONG  ulCapsAndSettings;
++      UCHAR  ucRequiredPower;
++      USHORT usClassification2;
++      ULONG  ulVCLK;
++      ULONG  ulDCLK;
++      UCHAR  ucUnused[5];
++} ATOM_PPLIB_NONCLOCK_INFO;
++
++// Contained in an array starting at the offset
++// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
++// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
++typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
++{
++      USHORT usEngineClockLow;
++      UCHAR ucEngineClockHigh;
++
++      USHORT usMemoryClockLow;
++      UCHAR ucMemoryClockHigh;
++
++      USHORT usVDDC;
++      USHORT usUnused1;
++      USHORT usUnused2;
++
++      ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
++
++} ATOM_PPLIB_R600_CLOCK_INFO;
++
++// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
++#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2          1
++#define ATOM_PPLIB_R600_FLAGS_UVDSAFE           2
++#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE    4
++#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF    8
++#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF   16
++#define ATOM_PPLIB_R600_FLAGS_LOWPOWER         32   // On the RV770 use 'low power' setting (sequencer S0).
++
++typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
++
++{
++      USHORT usLowEngineClockLow;         // Low Engine clock in MHz (the same way as on the R600).
++      UCHAR  ucLowEngineClockHigh;
++      USHORT usHighEngineClockLow;        // High Engine clock in MHz.
++      UCHAR  ucHighEngineClockHigh;
++      USHORT usMemoryClockLow;            // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
++      UCHAR  ucMemoryClockHigh;           // Currentyl unused.
++      UCHAR  ucPadding;                   // For proper alignment and size.
++      USHORT usVDDC;                      // For the 780, use: None, Low, High, Variable
++      UCHAR  ucMaxHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}
++      UCHAR  ucMinHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could 
++      USHORT usHTLinkFreq;                // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
++      ULONG  ulFlags; 
++} ATOM_PPLIB_RS780_CLOCK_INFO;
++
++#define ATOM_PPLIB_RS780_VOLTAGE_NONE       0 
++#define ATOM_PPLIB_RS780_VOLTAGE_LOW        1 
++#define ATOM_PPLIB_RS780_VOLTAGE_HIGH       2 
++#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE   3 
++
++#define ATOM_PPLIB_RS780_SPMCLK_NONE        0   // We cannot change the side port memory clock, leave it as it is.
++#define ATOM_PPLIB_RS780_SPMCLK_LOW         1
++#define ATOM_PPLIB_RS780_SPMCLK_HIGH        2
++
++#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE       0 
++#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW        1 
++#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH       2 
++
++typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
++{
++      USHORT usEngineClockLow;
++      UCHAR  ucEngineClockHigh;
++
++      USHORT usMemoryClockLow;
++      UCHAR  ucMemoryClockHigh;
++
++      USHORT usVDDC;
++      USHORT usVDDCI;
++      USHORT usUnused;
++
++      ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
++
++} ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
++
++typedef struct _ATOM_PPLIB_SI_CLOCK_INFO
++{
++      USHORT usEngineClockLow;
++      UCHAR  ucEngineClockHigh;
++
++      USHORT usMemoryClockLow;
++      UCHAR  ucMemoryClockHigh;
++
++      USHORT usVDDC;
++      USHORT usVDDCI;
++      UCHAR  ucPCIEGen;
++      UCHAR  ucUnused1;
++
++      ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now
++
++} ATOM_PPLIB_SI_CLOCK_INFO;
++
++typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
++{
++      USHORT usEngineClockLow;
++      UCHAR  ucEngineClockHigh;
++
++      USHORT usMemoryClockLow;
++      UCHAR  ucMemoryClockHigh;
++      
++      UCHAR  ucPCIEGen;
++      USHORT usPCIELane;
++} ATOM_PPLIB_CI_CLOCK_INFO;
++
++typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
++      USHORT usEngineClockLow;  //clockfrequency & 0xFFFF. The unit is in 10khz
++      UCHAR  ucEngineClockHigh; //clockfrequency >> 16. 
++      UCHAR  vddcIndex;         //2-bit vddc index;
++      USHORT tdpLimit;
++      //please initalize to 0
++      USHORT rsv1;
++      //please initialize to 0s
++      ULONG rsv2[2];
++}ATOM_PPLIB_SUMO_CLOCK_INFO;
++
++typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
++      UCHAR index;
++      UCHAR rsv[3];
++} ATOM_PPLIB_CZ_CLOCK_INFO;
++
++typedef struct _ATOM_PPLIB_STATE_V2
++{
++      //number of valid dpm levels in this state; Driver uses it to calculate the whole 
++      //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
++      UCHAR ucNumDPMLevels;
++      
++      //a index to the array of nonClockInfos
++      UCHAR nonClockInfoIndex;
++      /**
++      * Driver will read the first ucNumDPMLevels in this array
++      */
++      UCHAR clockInfoIndex[1];
++} ATOM_PPLIB_STATE_V2;
++
++typedef struct _StateArray{
++    //how many states we have 
++    UCHAR ucNumEntries;
++    
++    ATOM_PPLIB_STATE_V2 states[1];
++}StateArray;
++
++
++typedef struct _ClockInfoArray{
++    //how many clock levels we have
++    UCHAR ucNumEntries;
++    
++    //sizeof(ATOM_PPLIB_CLOCK_INFO)
++    UCHAR ucEntrySize;
++    
++    UCHAR clockInfo[1];
++}ClockInfoArray;
++
++typedef struct _NonClockInfoArray{
++
++    //how many non-clock levels we have. normally should be same as number of states
++    UCHAR ucNumEntries;
++    //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
++    UCHAR ucEntrySize;
++    
++    ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
++}NonClockInfoArray;
++
++typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
++{
++    USHORT usClockLow;
++    UCHAR  ucClockHigh;
++    USHORT usVoltage;
++}ATOM_PPLIB_Clock_Voltage_Dependency_Record;
++
++typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
++{
++    UCHAR ucNumEntries;                                                // Number of entries.
++    ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1];             // Dynamically allocate entries.
++}ATOM_PPLIB_Clock_Voltage_Dependency_Table;
++
++typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
++{
++    USHORT usSclkLow;
++    UCHAR  ucSclkHigh;
++    USHORT usMclkLow;
++    UCHAR  ucMclkHigh;
++    USHORT usVddc;
++    USHORT usVddci;
++}ATOM_PPLIB_Clock_Voltage_Limit_Record;
++
++typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
++{
++    UCHAR ucNumEntries;                                                // Number of entries.
++    ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1];                  // Dynamically allocate entries.
++}ATOM_PPLIB_Clock_Voltage_Limit_Table;
++
++union _ATOM_PPLIB_CAC_Leakage_Record
++{
++    struct
++    {
++        USHORT usVddc;          // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd
++        ULONG  ulLeakageValue;  // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd
++
++    };
++    struct
++     {
++        USHORT usVddc1;
++        USHORT usVddc2;
++        USHORT usVddc3;
++     };
++};
++
++typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record;
++
++typedef struct _ATOM_PPLIB_CAC_Leakage_Table
++{
++    UCHAR ucNumEntries;                                                 // Number of entries.
++    ATOM_PPLIB_CAC_Leakage_Record entries[1];                           // Dynamically allocate entries.
++}ATOM_PPLIB_CAC_Leakage_Table;
++
++typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
++{
++    USHORT usVoltage;
++    USHORT usSclkLow;
++    UCHAR  ucSclkHigh;
++    USHORT usMclkLow;
++    UCHAR  ucMclkHigh;
++}ATOM_PPLIB_PhaseSheddingLimits_Record;
++
++typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
++{
++    UCHAR ucNumEntries;                                                 // Number of entries.
++    ATOM_PPLIB_PhaseSheddingLimits_Record entries[1];                   // Dynamically allocate entries.
++}ATOM_PPLIB_PhaseSheddingLimits_Table;
++
++typedef struct _VCEClockInfo{
++    USHORT usEVClkLow;
++    UCHAR  ucEVClkHigh;
++    USHORT usECClkLow;
++    UCHAR  ucECClkHigh;
++}VCEClockInfo;
++
++typedef struct _VCEClockInfoArray{
++    UCHAR ucNumEntries;
++    VCEClockInfo entries[1];
++}VCEClockInfoArray;
++
++typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
++{
++    USHORT usVoltage;
++    UCHAR  ucVCEClockInfoIndex;
++}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record;
++
++typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
++{
++    UCHAR numEntries;
++    ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
++}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
++
++typedef struct _ATOM_PPLIB_VCE_State_Record
++{
++    UCHAR  ucVCEClockInfoIndex;
++    UCHAR  ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
++}ATOM_PPLIB_VCE_State_Record;
++
++typedef struct _ATOM_PPLIB_VCE_State_Table
++{
++    UCHAR numEntries;
++    ATOM_PPLIB_VCE_State_Record entries[1];
++}ATOM_PPLIB_VCE_State_Table;
++
++
++typedef struct _ATOM_PPLIB_VCE_Table
++{
++      UCHAR revid;
++//    VCEClockInfoArray array;
++//    ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits;
++//    ATOM_PPLIB_VCE_State_Table states;
++}ATOM_PPLIB_VCE_Table;
++
++
++typedef struct _UVDClockInfo{
++    USHORT usVClkLow;
++    UCHAR  ucVClkHigh;
++    USHORT usDClkLow;
++    UCHAR  ucDClkHigh;
++}UVDClockInfo;
++
++typedef struct _UVDClockInfoArray{
++    UCHAR ucNumEntries;
++    UVDClockInfo entries[1];
++}UVDClockInfoArray;
++
++typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
++{
++    USHORT usVoltage;
++    UCHAR  ucUVDClockInfoIndex;
++}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record;
++
++typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
++{
++    UCHAR numEntries;
++    ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
++}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
++
++typedef struct _ATOM_PPLIB_UVD_Table
++{
++      UCHAR revid;
++//    UVDClockInfoArray array;
++//    ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits;
++}ATOM_PPLIB_UVD_Table;
++
++typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
++{
++      USHORT usVoltage;
++      USHORT usSAMClockLow;
++      UCHAR  ucSAMClockHigh;
++}ATOM_PPLIB_SAMClk_Voltage_Limit_Record;
++
++typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{
++    UCHAR numEntries;
++    ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1];
++}ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
++
++typedef struct _ATOM_PPLIB_SAMU_Table
++{
++      UCHAR revid;
++      ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits;
++}ATOM_PPLIB_SAMU_Table;
++
++typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record
++{
++      USHORT usVoltage;
++      USHORT usACPClockLow;
++      UCHAR  ucACPClockHigh;
++}ATOM_PPLIB_ACPClk_Voltage_Limit_Record;
++
++typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{
++    UCHAR numEntries;
++    ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1];
++}ATOM_PPLIB_ACPClk_Voltage_Limit_Table;
++
++typedef struct _ATOM_PPLIB_ACP_Table
++{
++      UCHAR revid;
++      ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits;
++}ATOM_PPLIB_ACP_Table;
++
++typedef struct _ATOM_PowerTune_Table{
++    USHORT usTDP;
++    USHORT usConfigurableTDP;
++    USHORT usTDC;
++    USHORT usBatteryPowerLimit;
++    USHORT usSmallPowerLimit;
++    USHORT usLowCACLeakage;
++    USHORT usHighCACLeakage;
++}ATOM_PowerTune_Table;
++
++typedef struct _ATOM_PPLIB_POWERTUNE_Table
++{
++      UCHAR revid;
++      ATOM_PowerTune_Table power_tune_table;
++}ATOM_PPLIB_POWERTUNE_Table;
++
++typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1
++{
++      UCHAR revid;
++      ATOM_PowerTune_Table power_tune_table;
++      USHORT usMaximumPowerDeliveryLimit;
++      USHORT usReserve[7];
++} ATOM_PPLIB_POWERTUNE_Table_V1;
++
++#define ATOM_PPM_A_A    1
++#define ATOM_PPM_A_I    2
++typedef struct _ATOM_PPLIB_PPM_Table
++{
++      UCHAR  ucRevId;
++      UCHAR  ucPpmDesign;          //A+I or A+A
++      USHORT usCpuCoreNumber;
++      ULONG  ulPlatformTDP;
++      ULONG  ulSmallACPlatformTDP;
++      ULONG  ulPlatformTDC;
++      ULONG  ulSmallACPlatformTDC;
++      ULONG  ulApuTDP;
++      ULONG  ulDGpuTDP;  
++      ULONG  ulDGpuUlvPower;
++      ULONG  ulTjmax;
++} ATOM_PPLIB_PPM_Table;
++
++#pragma pack()
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0031-yocto-amd-drm-amdgpu-add-GMC-7-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0031-yocto-amd-drm-amdgpu-add-GMC-7-1-register-headers.patch
new file mode 100644
index 00000000..69d7030e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0031-yocto-amd-drm-amdgpu-add-GMC-7-1-register-headers.patch
@@ -0,0 +1,69 @@
+From f904f51e193820c1ee5c60f9be963f84a8591f06 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:46:13 -0400
+Subject: drm/amdgpu: add clearstate_defs.h
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This header provides for format for the GCA blocks
+clear state (i.e., default state).  Each GCA version
+has a specific clear state.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_defs.h b/drivers/gpu/drm/amd/amdgpu/clearstate_defs.h
+new file mode 100644
+index 0000000..3eda707
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/clearstate_defs.h
+@@ -0,0 +1,44 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef CLEARSTATE_DEFS_H
++#define CLEARSTATE_DEFS_H
++
++enum section_id {
++    SECT_NONE,
++    SECT_CONTEXT,
++    SECT_CLEAR,
++    SECT_CTRLCONST
++};
++
++struct cs_extent_def {
++    const unsigned int *extent;
++    const unsigned int reg_index;
++    const unsigned int reg_count;
++};
++
++struct cs_section_def {
++    const struct cs_extent_def *section;
++    const enum section_id id;
++};
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0032-yocto-amd-drm-amdgpu-add-GMC-7-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0032-yocto-amd-drm-amdgpu-add-GMC-7-0-register-headers.patch
new file mode 100644
index 00000000..4ef1c4ad
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0032-yocto-amd-drm-amdgpu-add-GMC-7-0-register-headers.patch
@@ -0,0 +1,215 @@
+From 5c734776297dd93c1ee10e1c2376393f64734eb4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:48:06 -0400
+Subject: drm/amdgpu: add ppsmc.h
+
+This header provides the smc message interface for the driver.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/ppsmc.h b/drivers/gpu/drm/amd/amdgpu/ppsmc.h
+new file mode 100644
+index 0000000..7837f2e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/ppsmc.h
+@@ -0,0 +1,196 @@
++/*
++ * Copyright 2011 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef PP_SMC_H
++#define PP_SMC_H
++
++#pragma pack(push, 1)
++
++#define PPSMC_SWSTATE_FLAG_DC                           0x01
++#define PPSMC_SWSTATE_FLAG_UVD                          0x02
++#define PPSMC_SWSTATE_FLAG_VCE                          0x04
++#define PPSMC_SWSTATE_FLAG_PCIE_X1                      0x08
++
++#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
++#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
++#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
++
++#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
++#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
++#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
++#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
++#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
++#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
++#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO        0x40
++
++#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
++#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
++#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
++#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
++#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH      0x02
++
++#define PPSMC_DISPLAY_WATERMARK_LOW                     0
++#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
++
++#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
++#define PPSMC_STATEFLAG_POWERBOOST         0x02
++#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
++#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
++
++#define FDO_MODE_HARDWARE 0
++#define FDO_MODE_PIECE_WISE_LINEAR 1
++
++enum FAN_CONTROL {
++	FAN_CONTROL_FUZZY,
++	FAN_CONTROL_TABLE
++};
++
++#define PPSMC_Result_OK             ((uint8_t)0x01)
++#define PPSMC_Result_Failed         ((uint8_t)0xFF)
++
++typedef uint8_t PPSMC_Result;
++
++#define PPSMC_MSG_Halt                      ((uint8_t)0x10)
++#define PPSMC_MSG_Resume                    ((uint8_t)0x11)
++#define PPSMC_MSG_ZeroLevelsDisabled        ((uint8_t)0x13)
++#define PPSMC_MSG_OneLevelsDisabled         ((uint8_t)0x14)
++#define PPSMC_MSG_TwoLevelsDisabled         ((uint8_t)0x15)
++#define PPSMC_MSG_EnableThermalInterrupt    ((uint8_t)0x16)
++#define PPSMC_MSG_RunningOnAC               ((uint8_t)0x17)
++#define PPSMC_MSG_SwitchToSwState           ((uint8_t)0x20)
++#define PPSMC_MSG_SwitchToInitialState      ((uint8_t)0x40)
++#define PPSMC_MSG_NoForcedLevel             ((uint8_t)0x41)
++#define PPSMC_MSG_ForceHigh                 ((uint8_t)0x42)
++#define PPSMC_MSG_ForceMediumOrHigh         ((uint8_t)0x43)
++#define PPSMC_MSG_SwitchToMinimumPower      ((uint8_t)0x51)
++#define PPSMC_MSG_ResumeFromMinimumPower    ((uint8_t)0x52)
++#define PPSMC_MSG_EnableCac                 ((uint8_t)0x53)
++#define PPSMC_MSG_DisableCac                ((uint8_t)0x54)
++#define PPSMC_TDPClampingActive             ((uint8_t)0x59)
++#define PPSMC_TDPClampingInactive           ((uint8_t)0x5A)
++#define PPSMC_StartFanControl               ((uint8_t)0x5B)
++#define PPSMC_StopFanControl                ((uint8_t)0x5C)
++#define PPSMC_MSG_NoDisplay                 ((uint8_t)0x5D)
++#define PPSMC_MSG_HasDisplay                ((uint8_t)0x5E)
++#define PPSMC_MSG_UVDPowerOFF               ((uint8_t)0x60)
++#define PPSMC_MSG_UVDPowerON                ((uint8_t)0x61)
++#define PPSMC_MSG_EnableULV                 ((uint8_t)0x62)
++#define PPSMC_MSG_DisableULV                ((uint8_t)0x63)
++#define PPSMC_MSG_EnterULV                  ((uint8_t)0x64)
++#define PPSMC_MSG_ExitULV                   ((uint8_t)0x65)
++#define PPSMC_CACLongTermAvgEnable          ((uint8_t)0x6E)
++#define PPSMC_CACLongTermAvgDisable         ((uint8_t)0x6F)
++#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint8_t)0x7A)
++#define PPSMC_FlushDataCache                ((uint8_t)0x80)
++#define PPSMC_MSG_SetEnabledLevels          ((uint8_t)0x82)
++#define PPSMC_MSG_SetForcedLevels           ((uint8_t)0x83)
++#define PPSMC_MSG_ResetToDefaults           ((uint8_t)0x84)
++#define PPSMC_MSG_EnableDTE                 ((uint8_t)0x87)
++#define PPSMC_MSG_DisableDTE                ((uint8_t)0x88)
++#define PPSMC_MSG_ThrottleOVRDSCLKDS        ((uint8_t)0x96)
++#define PPSMC_MSG_CancelThrottleOVRDSCLKDS  ((uint8_t)0x97)
++
++/* CI/KV/KB */
++#define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
++#define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
++#define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
++#define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
++#define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
++#define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
++#define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
++#define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
++#define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
++#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
++#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
++#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
++#define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
++#define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
++#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
++#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
++#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
++#define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
++#define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
++#define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
++#define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
++#define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
++#define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
++#define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
++#define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
++#define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
++#define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
++#define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
++#define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
++#define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
++#define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
++#define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
++#define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
++#define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
++#define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
++#define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
++#define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
++#define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
++#define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
++#define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
++#define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
++#define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
++#define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
++#define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
++#define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
++#define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
++#define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
++#define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
++#define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
++#define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
++#define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
++
++#define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
++#define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
++
++#define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
++#define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
++
++/* TN */
++#define PPSMC_MSG_DPM_Config                ((uint32_t) 0x102)
++#define PPSMC_MSG_DPM_ForceState            ((uint32_t) 0x104)
++#define PPSMC_MSG_PG_SIMD_Config            ((uint32_t) 0x108)
++#define PPSMC_MSG_Voltage_Cntl_Enable       ((uint32_t) 0x109)
++#define PPSMC_MSG_Thermal_Cntl_Enable       ((uint32_t) 0x10a)
++#define PPSMC_MSG_VCEPowerOFF               ((uint32_t) 0x10e)
++#define PPSMC_MSG_VCEPowerON                ((uint32_t) 0x10f)
++#define PPSMC_MSG_DPM_N_LevelsDisabled      ((uint32_t) 0x112)
++#define PPSMC_MSG_DCE_RemoveVoltageAdjustment   ((uint32_t) 0x11d)
++#define PPSMC_MSG_DCE_AllowVoltageAdjustment    ((uint32_t) 0x11e)
++#define PPSMC_MSG_EnableBAPM                ((uint32_t) 0x120)
++#define PPSMC_MSG_DisableBAPM               ((uint32_t) 0x121)
++#define PPSMC_MSG_UVD_DPM_Config            ((uint32_t) 0x124)
++
++#define PPSMC_MSG_DRV_DRAM_ADDR_HI            ((uint16_t) 0x250)
++#define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
++#define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
++#define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
++#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
++
++typedef uint16_t PPSMC_Msg;
++
++#pragma pack(pop)
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0033-yocto-amd-drm-amdgpu-add-GCA-8-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0033-yocto-amd-drm-amdgpu-add-GCA-8-0-register-headers.patch
new file mode 100644
index 00000000..45648cb7
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0033-yocto-amd-drm-amdgpu-add-GCA-8-0-register-headers.patch
@@ -0,0 +1,85 @@
+From 5890e474773b74fa46770d548527f36d6848fbb8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:49:21 -0400
+Subject: drm/amdgpu: add amdgpu_family.h
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This header defines asic families and attributes.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h
+new file mode 100644
+index 0000000..0698764
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h
+@@ -0,0 +1,62 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++
++/* this file defines the CHIP_  and family flags used in the pciids,
++ * its is common between kms and non-kms because duplicating it and
++ * changing one place is fail.
++ */
++#ifndef AMDGPU_FAMILY_H
++#define AMDGPU_FAMILY_H
++/*
++ * Supported ASIC types
++ */
++enum amdgpu_asic_type {
++	CHIP_BONAIRE = 0,
++	CHIP_KAVERI,
++	CHIP_KABINI,
++	CHIP_HAWAII,
++	CHIP_MULLINS,
++	CHIP_TOPAZ,
++	CHIP_TONGA,
++	CHIP_CARRIZO,
++	CHIP_LAST,
++};
++
++/*
++ * Chip flags
++ */
++enum amdgpu_chip_flags {
++	AMDGPU_ASIC_MASK = 0x0000ffffUL,
++	AMDGPU_FLAGS_MASK  = 0xffff0000UL,
++	AMDGPU_IS_MOBILITY = 0x00010000UL,
++	AMDGPU_IS_APU      = 0x00020000UL,
++	AMDGPU_IS_PX       = 0x00040000UL,
++	AMDGPU_EXP_HW_SUPPORT = 0x00080000UL,
++};
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0034-yocto-amd-drm-amdgpu-add-GCA-7-2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0034-yocto-amd-drm-amdgpu-add-GCA-7-2-register-headers.patch
new file mode 100644
index 00000000..8965af38
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0034-yocto-amd-drm-amdgpu-add-GCA-7-2-register-headers.patch
@@ -0,0 +1,2442 @@
+From dbe0e6e949c1cc4921b034c59e8cff7875961e6b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:51:00 -0400
+Subject: drm/amdgpu: add amdgpu.h
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is the main header file for amdgpu.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+new file mode 100644
+index 0000000..6d69b9c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -0,0 +1,2419 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#ifndef __AMDGPU_H__
++#define __AMDGPU_H__
++
++/* TODO: Here are things that needs to be done :
++ *	- surface allocator & initializer : (bit like scratch reg) should
++ *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
++ *	  related to surface
++ *	- WB : write back stuff (do it bit like scratch reg things)
++ *	- Vblank : look at Jesse's rework and what we should do
++ *	- r600/r700: gart & cp
++ *	- cs : clean cs ioctl use bitmap & things like that.
++ *	- power management stuff
++ *	- Barrier in gart code
++ *	- Unmappabled vram ?
++ *	- TESTING, TESTING, TESTING
++ */
++
++/* Initialization path:
++ *  We expect that acceleration initialization might fail for various
++ *  reasons even thought we work hard to make it works on most
++ *  configurations. In order to still have a working userspace in such
++ *  situation the init path must succeed up to the memory controller
++ *  initialization point. Failure before this point are considered as
++ *  fatal error. Here is the init callchain :
++ *      amdgpu_device_init  perform common structure, mutex initialization
++ *      asic_init           setup the GPU memory layout and perform all
++ *                          one time initialization (failure in this
++ *                          function are considered fatal)
++ *      asic_startup        setup the GPU acceleration, in order to
++ *                          follow guideline the first thing this
++ *                          function should do is setting the GPU
++ *                          memory controller (only MC setup failure
++ *                          are considered as fatal)
++ */
++
++#include <linux/atomic.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/kref.h>
++#include <linux/interval_tree.h>
++#include <linux/hashtable.h>
++#include <linux/fence.h>
++
++#include <ttm/ttm_bo_api.h>
++#include <ttm/ttm_bo_driver.h>
++#include <ttm/ttm_placement.h>
++#include <ttm/ttm_module.h>
++#include <ttm/ttm_execbuf_util.h>
++
++#include <drm/drm_gem.h>
++
++#include "amdgpu_family.h"
++#include "amdgpu_mode.h"
++#include "amdgpu_ih.h"
++#include "amdgpu_irq.h"
++#include "amdgpu_ucode.h"
++#include "amdgpu_gds.h"
++
++/*
++ * Modules parameters.
++ */
++extern int amdgpu_modeset;
++extern int amdgpu_vram_limit;
++extern int amdgpu_gart_size;
++extern int amdgpu_benchmarking;
++extern int amdgpu_testing;
++extern int amdgpu_audio;
++extern int amdgpu_disp_priority;
++extern int amdgpu_hw_i2c;
++extern int amdgpu_pcie_gen2;
++extern int amdgpu_msi;
++extern int amdgpu_lockup_timeout;
++extern int amdgpu_dpm;
++extern int amdgpu_smc_load_fw;
++extern int amdgpu_aspm;
++extern int amdgpu_runtime_pm;
++extern int amdgpu_hard_reset;
++extern unsigned amdgpu_ip_block_mask;
++extern int amdgpu_bapm;
++extern int amdgpu_deep_color;
++extern int amdgpu_vm_size;
++extern int amdgpu_vm_block_size;
++
++#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
++#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
++/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
++#define AMDGPU_IB_POOL_SIZE			16
++#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
++#define AMDGPUFB_CONN_LIMIT			4
++#define AMDGPU_BIOS_NUM_SCRATCH			8
++
++/* fence seq are set to this number when signaled */
++#define AMDGPU_FENCE_SIGNALED_SEQ		0LL
++
++/* max number of rings */
++#define AMDGPU_MAX_RINGS			16
++#define AMDGPU_MAX_GFX_RINGS			1
++#define AMDGPU_MAX_COMPUTE_RINGS		8
++#define AMDGPU_MAX_VCE_RINGS			2
++
++/* number of hw syncs before falling back on blocking */
++#define AMDGPU_NUM_SYNCS			4
++
++/* hardcode that limit for now */
++#define AMDGPU_VA_RESERVED_SIZE			(8 << 20)
++
++/* hard reset data */
++#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
++
++/* reset flags */
++#define AMDGPU_RESET_GFX			(1 << 0)
++#define AMDGPU_RESET_COMPUTE			(1 << 1)
++#define AMDGPU_RESET_DMA			(1 << 2)
++#define AMDGPU_RESET_CP				(1 << 3)
++#define AMDGPU_RESET_GRBM			(1 << 4)
++#define AMDGPU_RESET_DMA1			(1 << 5)
++#define AMDGPU_RESET_RLC			(1 << 6)
++#define AMDGPU_RESET_SEM			(1 << 7)
++#define AMDGPU_RESET_IH				(1 << 8)
++#define AMDGPU_RESET_VMC			(1 << 9)
++#define AMDGPU_RESET_MC				(1 << 10)
++#define AMDGPU_RESET_DISPLAY			(1 << 11)
++#define AMDGPU_RESET_UVD			(1 << 12)
++#define AMDGPU_RESET_VCE			(1 << 13)
++#define AMDGPU_RESET_VCE1			(1 << 14)
++
++/* CG block flags */
++#define AMDGPU_CG_BLOCK_GFX			(1 << 0)
++#define AMDGPU_CG_BLOCK_MC			(1 << 1)
++#define AMDGPU_CG_BLOCK_SDMA			(1 << 2)
++#define AMDGPU_CG_BLOCK_UVD			(1 << 3)
++#define AMDGPU_CG_BLOCK_VCE			(1 << 4)
++#define AMDGPU_CG_BLOCK_HDP			(1 << 5)
++#define AMDGPU_CG_BLOCK_BIF			(1 << 6)
++
++/* CG flags */
++#define AMDGPU_CG_SUPPORT_GFX_MGCG		(1 << 0)
++#define AMDGPU_CG_SUPPORT_GFX_MGLS		(1 << 1)
++#define AMDGPU_CG_SUPPORT_GFX_CGCG		(1 << 2)
++#define AMDGPU_CG_SUPPORT_GFX_CGLS		(1 << 3)
++#define AMDGPU_CG_SUPPORT_GFX_CGTS		(1 << 4)
++#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
++#define AMDGPU_CG_SUPPORT_GFX_CP_LS		(1 << 6)
++#define AMDGPU_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
++#define AMDGPU_CG_SUPPORT_MC_LS			(1 << 8)
++#define AMDGPU_CG_SUPPORT_MC_MGCG		(1 << 9)
++#define AMDGPU_CG_SUPPORT_SDMA_LS		(1 << 10)
++#define AMDGPU_CG_SUPPORT_SDMA_MGCG		(1 << 11)
++#define AMDGPU_CG_SUPPORT_BIF_LS		(1 << 12)
++#define AMDGPU_CG_SUPPORT_UVD_MGCG		(1 << 13)
++#define AMDGPU_CG_SUPPORT_VCE_MGCG		(1 << 14)
++#define AMDGPU_CG_SUPPORT_HDP_LS		(1 << 15)
++#define AMDGPU_CG_SUPPORT_HDP_MGCG		(1 << 16)
++
++/* PG flags */
++#define AMDGPU_PG_SUPPORT_GFX_PG		(1 << 0)
++#define AMDGPU_PG_SUPPORT_GFX_SMG		(1 << 1)
++#define AMDGPU_PG_SUPPORT_GFX_DMG		(1 << 2)
++#define AMDGPU_PG_SUPPORT_UVD			(1 << 3)
++#define AMDGPU_PG_SUPPORT_VCE			(1 << 4)
++#define AMDGPU_PG_SUPPORT_CP			(1 << 5)
++#define AMDGPU_PG_SUPPORT_GDS			(1 << 6)
++#define AMDGPU_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
++#define AMDGPU_PG_SUPPORT_SDMA			(1 << 8)
++#define AMDGPU_PG_SUPPORT_ACP			(1 << 9)
++#define AMDGPU_PG_SUPPORT_SAMU			(1 << 10)
++
++/* GFX current status */
++#define AMDGPU_GFX_NORMAL_MODE			0x00000000L
++#define AMDGPU_GFX_SAFE_MODE			0x00000001L
++#define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
++#define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
++#define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L
++
++/* max cursor sizes (in pixels) */
++#define CIK_CURSOR_WIDTH 128
++#define CIK_CURSOR_HEIGHT 128
++
++struct amdgpu_device;
++struct amdgpu_fence;
++struct amdgpu_ib;
++struct amdgpu_vm;
++struct amdgpu_ring;
++struct amdgpu_semaphore;
++struct amdgpu_cs_parser;
++struct amdgpu_irq_src;
++
++enum amdgpu_cp_irq {
++	AMDGPU_CP_IRQ_GFX_EOP = 0,
++	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
++	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
++
++	AMDGPU_CP_IRQ_LAST
++};
++
++enum amdgpu_sdma_irq {
++	AMDGPU_SDMA_IRQ_TRAP0 = 0,
++	AMDGPU_SDMA_IRQ_TRAP1,
++
++	AMDGPU_SDMA_IRQ_LAST
++};
++
++enum amdgpu_thermal_irq {
++	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
++	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
++
++	AMDGPU_THERMAL_IRQ_LAST
++};
++
++/*
++ * IP block functions
++ */
++enum amdgpu_ip_block_type {
++	AMDGPU_IP_BLOCK_TYPE_COMMON,
++	AMDGPU_IP_BLOCK_TYPE_GMC,
++	AMDGPU_IP_BLOCK_TYPE_IH,
++	AMDGPU_IP_BLOCK_TYPE_SMC,
++	AMDGPU_IP_BLOCK_TYPE_DCE,
++	AMDGPU_IP_BLOCK_TYPE_GFX,
++	AMDGPU_IP_BLOCK_TYPE_SDMA,
++	AMDGPU_IP_BLOCK_TYPE_UVD,
++	AMDGPU_IP_BLOCK_TYPE_VCE,
++};
++
++enum amdgpu_clockgating_state {
++	AMDGPU_CG_STATE_GATE = 0,
++	AMDGPU_CG_STATE_UNGATE,
++};
++
++enum amdgpu_powergating_state {
++	AMDGPU_PG_STATE_GATE = 0,
++	AMDGPU_PG_STATE_UNGATE,
++};
++
++struct amdgpu_ip_funcs {
++	/* sets up early driver state (pre sw_init), does not configure hw - Optional */
++	int (*early_init)(struct amdgpu_device *adev);
++	/* sets up late driver/hw state (post hw_init) - Optional */
++	int (*late_init)(struct amdgpu_device *adev);
++	/* sets up driver state, does not configure hw */
++	int (*sw_init)(struct amdgpu_device *adev);
++	/* tears down driver state, does not configure hw */
++	int (*sw_fini)(struct amdgpu_device *adev);
++	/* sets up the hw state */
++	int (*hw_init)(struct amdgpu_device *adev);
++	/* tears down the hw state */
++	int (*hw_fini)(struct amdgpu_device *adev);
++	/* handles IP specific hw/sw changes for suspend */
++	int (*suspend)(struct amdgpu_device *adev);
++	/* handles IP specific hw/sw changes for resume */
++	int (*resume)(struct amdgpu_device *adev);
++	/* returns current IP block idle status */
++	bool (*is_idle)(struct amdgpu_device *adev);
++	/* poll for idle */
++	int (*wait_for_idle)(struct amdgpu_device *adev);
++	/* soft reset the IP block */
++	int (*soft_reset)(struct amdgpu_device *adev);
++	/* dump the IP block status registers */
++	void (*print_status)(struct amdgpu_device *adev);
++	/* enable/disable cg for the IP block */
++	int (*set_clockgating_state)(struct amdgpu_device *adev,
++				     enum amdgpu_clockgating_state state);
++	/* enable/disable pg for the IP block */
++	int (*set_powergating_state)(struct amdgpu_device *adev,
++				     enum amdgpu_powergating_state state);
++};
++
++int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
++				  enum amdgpu_ip_block_type block_type,
++				  enum amdgpu_clockgating_state state);
++int amdgpu_set_powergating_state(struct amdgpu_device *adev,
++				  enum amdgpu_ip_block_type block_type,
++				  enum amdgpu_powergating_state state);
++
++struct amdgpu_ip_block_version {
++	enum amdgpu_ip_block_type type;
++	u32 major;
++	u32 minor;
++	u32 rev;
++	const struct amdgpu_ip_funcs *funcs;
++};
++
++int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
++				enum amdgpu_ip_block_type type,
++				u32 major, u32 minor);
++
++const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
++					struct amdgpu_device *adev,
++					enum amdgpu_ip_block_type type);
++
++/* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */
++struct amdgpu_buffer_funcs {
++	/* maximum bytes in a single operation */
++	uint32_t	copy_max_bytes;
++
++	/* number of dw to reserve per operation */
++	unsigned	copy_num_dw;
++
++	/* used for buffer migration */
++	void (*emit_copy_buffer)(struct amdgpu_ring *ring,
++				 /* src addr in bytes */
++				 uint64_t src_offset,
++				 /* dst addr in bytes */
++				 uint64_t dst_offset,
++				 /* number of byte to transfer */
++				 uint32_t byte_count);
++
++	/* maximum bytes in a single operation */
++	uint32_t	fill_max_bytes;
++
++	/* number of dw to reserve per operation */
++	unsigned	fill_num_dw;
++
++	/* used for buffer clearing */
++	void (*emit_fill_buffer)(struct amdgpu_ring *ring,
++				 /* value to write to memory */
++				 uint32_t src_data,
++				 /* dst addr in bytes */
++				 uint64_t dst_offset,
++				 /* number of byte to fill */
++				 uint32_t byte_count);
++};
++
++/* provided by hw blocks that can write ptes, e.g., sdma */
++struct amdgpu_vm_pte_funcs {
++	/* copy pte entries from GART */
++	void (*copy_pte)(struct amdgpu_ib *ib,
++			 uint64_t pe, uint64_t src,
++			 unsigned count);
++	/* write pte one entry at a time with addr mapping */
++	void (*write_pte)(struct amdgpu_ib *ib,
++			  uint64_t pe,
++			  uint64_t addr, unsigned count,
++			  uint32_t incr, uint32_t flags);
++	/* for linear pte/pde updates without addr mapping */
++	void (*set_pte_pde)(struct amdgpu_ib *ib,
++			    uint64_t pe,
++			    uint64_t addr, unsigned count,
++			    uint32_t incr, uint32_t flags);
++	/* pad the indirect buffer to the necessary number of dw */
++	void (*pad_ib)(struct amdgpu_ib *ib);
++};
++
++/* provided by the gmc block */
++struct amdgpu_gart_funcs {
++	/* flush the vm tlb via mmio */
++	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
++			      uint32_t vmid);
++	/* write pte/pde updates using the cpu */
++	int (*set_pte_pde)(struct amdgpu_device *adev,
++			   void *cpu_pt_addr, /* cpu addr of page table */
++			   uint32_t gpu_page_idx, /* pte/pde to update */
++			   uint64_t addr, /* addr to write into pte/pde */
++			   uint32_t flags); /* access flags */
++};
++
++/* provided by the ih block */
++struct amdgpu_ih_funcs {
++	/* ring read/write ptr handling, called from interrupt context */
++	u32 (*get_wptr)(struct amdgpu_device *adev);
++	void (*decode_iv)(struct amdgpu_device *adev,
++			  struct amdgpu_iv_entry *entry);
++	void (*set_rptr)(struct amdgpu_device *adev);
++};
++
++/* provided by hw blocks that expose a ring buffer for commands */
++struct amdgpu_ring_funcs {
++	/* ring read/write ptr handling */
++	u32 (*get_rptr)(struct amdgpu_ring *ring);
++	u32 (*get_wptr)(struct amdgpu_ring *ring);
++	void (*set_wptr)(struct amdgpu_ring *ring);
++	/* validating and patching of IBs */
++	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
++	/* command emit functions */
++	void (*emit_ib)(struct amdgpu_ring *ring,
++			struct amdgpu_ib *ib);
++	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
++			   uint64_t seq, bool write64bit);
++	bool (*emit_semaphore)(struct amdgpu_ring *ring,
++			       struct amdgpu_semaphore *semaphore,
++			       bool emit_wait);
++	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
++			      uint64_t pd_addr);
++	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
++				uint32_t gds_base, uint32_t gds_size,
++				uint32_t gws_base, uint32_t gws_size,
++				uint32_t oa_base, uint32_t oa_size);
++	/* testing functions */
++	int (*test_ring)(struct amdgpu_ring *ring);
++	int (*test_ib)(struct amdgpu_ring *ring);
++	bool (*is_lockup)(struct amdgpu_ring *ring);
++};
++
++/*
++ * BIOS.
++ */
++bool amdgpu_get_bios(struct amdgpu_device *adev);
++bool amdgpu_read_bios(struct amdgpu_device *adev);
++
++/*
++ * Dummy page
++ */
++struct amdgpu_dummy_page {
++	struct page	*page;
++	dma_addr_t	addr;
++};
++int amdgpu_dummy_page_init(struct amdgpu_device *adev);
++void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
++
++
++/*
++ * Clocks
++ */
++
++#define AMDGPU_MAX_PPLL 3
++
++struct amdgpu_clock {
++	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
++	struct amdgpu_pll spll;
++	struct amdgpu_pll mpll;
++	/* 10 Khz units */
++	uint32_t default_mclk;
++	uint32_t default_sclk;
++	uint32_t default_dispclk;
++	uint32_t current_dispclk;
++	uint32_t dp_extclk;
++	uint32_t max_pixel_clock;
++};
++
++/*
++ * Fences.
++ */
++struct amdgpu_fence_driver {
++	struct amdgpu_ring		*ring;
++	uint64_t			gpu_addr;
++	volatile uint32_t		*cpu_addr;
++	/* sync_seq is protected by ring emission lock */
++	uint64_t			sync_seq[AMDGPU_MAX_RINGS];
++	atomic64_t			last_seq;
++	bool				initialized;
++	bool				delayed_irq;
++	struct amdgpu_irq_src		*irq_src;
++	unsigned			irq_type;
++	struct delayed_work             lockup_work;
++};
++
++/* some special values for the owner field */
++#define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
++#define AMDGPU_FENCE_OWNER_VM		((void*)1ul)
++#define AMDGPU_FENCE_OWNER_MOVE		((void*)2ul)
++
++struct amdgpu_fence {
++	struct fence base;
++
++	/* RB, DMA, etc. */
++	struct amdgpu_ring		*ring;
++	uint64_t			seq;
++
++	/* filp or special value for fence creator */
++	void				*owner;
++
++	wait_queue_t			fence_wake;
++};
++
++struct amdgpu_user_fence {
++	/* write-back bo */
++	struct amdgpu_bo 	*bo;
++	/* write-back address offset to bo start */
++	uint32_t                offset;
++};
++
++int amdgpu_fence_driver_init(struct amdgpu_device *adev);
++void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
++void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
++
++void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
++int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
++				   struct amdgpu_irq_src *irq_src,
++				   unsigned irq_type);
++int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
++		      struct amdgpu_fence **fence);
++void amdgpu_fence_process(struct amdgpu_ring *ring);
++int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
++int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
++unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
++
++bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
++int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
++int amdgpu_fence_wait_any(struct amdgpu_device *adev,
++			  struct amdgpu_fence **fences,
++			  bool intr);
++long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev,
++				   u64 *target_seq, bool intr,
++				   long timeout);
++struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
++void amdgpu_fence_unref(struct amdgpu_fence **fence);
++
++bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
++			    struct amdgpu_ring *ring);
++void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
++			    struct amdgpu_ring *ring);
++
++static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
++						      struct amdgpu_fence *b)
++{
++	if (!a) {
++		return b;
++	}
++
++	if (!b) {
++		return a;
++	}
++
++	BUG_ON(a->ring != b->ring);
++
++	if (a->seq > b->seq) {
++		return a;
++	} else {
++		return b;
++	}
++}
++
++static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
++					   struct amdgpu_fence *b)
++{
++	if (!a) {
++		return false;
++	}
++
++	if (!b) {
++		return true;
++	}
++
++	BUG_ON(a->ring != b->ring);
++
++	return a->seq < b->seq;
++}
++
++int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, 
++			   void *owner, struct amdgpu_fence **fence);
++
++/*
++ * TTM.
++ */
++struct amdgpu_mman {
++	struct ttm_bo_global_ref        bo_global_ref;
++	struct drm_global_reference	mem_global_ref;
++	struct ttm_bo_device		bdev;
++	bool				mem_global_referenced;
++	bool				initialized;
++
++#if defined(CONFIG_DEBUG_FS)
++	struct dentry			*vram;
++	struct dentry			*gtt;
++#endif
++
++	/* buffer handling */
++	const struct amdgpu_buffer_funcs	*buffer_funcs;
++	struct amdgpu_ring			*buffer_funcs_ring;
++};
++
++int amdgpu_copy_buffer(struct amdgpu_ring *ring,
++		       uint64_t src_offset,
++		       uint64_t dst_offset,
++		       uint32_t byte_count,
++		       struct reservation_object *resv,
++		       struct amdgpu_fence **fence);
++int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
++
++struct amdgpu_bo_list_entry {
++	struct amdgpu_bo		*robj;
++	struct ttm_validate_buffer	tv;
++	struct amdgpu_bo_va		*bo_va;
++	unsigned			prefered_domains;
++	unsigned			allowed_domains;
++	uint32_t			priority;
++};
++
++struct amdgpu_bo_va_mapping {
++	struct list_head		list;
++	struct interval_tree_node	it;
++	uint64_t			offset;
++	uint32_t			flags;
++};
++
++/* bo virtual addresses in a specific vm */
++struct amdgpu_bo_va {
++	/* protected by bo being reserved */
++	struct list_head		bo_list;
++	uint64_t			addr;
++	struct amdgpu_fence		*last_pt_update;
++	unsigned			ref_count;
++
++	/* protected by vm mutex */
++	struct list_head		mappings;
++	struct list_head		vm_status;
++
++	/* constant after initialization */
++	struct amdgpu_vm		*vm;
++	struct amdgpu_bo		*bo;
++};
++
++struct amdgpu_bo {
++	/* Protected by gem.mutex */
++	struct list_head		list;
++	/* Protected by tbo.reserved */
++	u32				initial_domain;
++	struct ttm_place		placements[4];
++	struct ttm_placement		placement;
++	struct ttm_buffer_object	tbo;
++	struct ttm_bo_kmap_obj		kmap;
++	u64				flags;
++	unsigned			pin_count;
++	void				*kptr;
++	u64				tiling_flags;
++	u64				metadata_flags;
++	void				*metadata;
++	u32				metadata_size;
++	/* list of all virtual address to which this bo
++	 * is associated to
++	 */
++	struct list_head		va;
++	/* Constant after initialization */
++	struct amdgpu_device		*adev;
++	struct drm_gem_object		gem_base;
++
++	struct ttm_bo_kmap_obj		dma_buf_vmap;
++	pid_t				pid;
++	struct amdgpu_mn		*mn;
++	struct list_head		mn_list;
++};
++#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
++
++void amdgpu_gem_object_free(struct drm_gem_object *obj);
++int amdgpu_gem_object_open(struct drm_gem_object *obj,
++				struct drm_file *file_priv);
++void amdgpu_gem_object_close(struct drm_gem_object *obj,
++				struct drm_file *file_priv);
++unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
++struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
++struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
++							struct dma_buf_attachment *attach,
++							struct sg_table *sg);
++struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
++					struct drm_gem_object *gobj,
++					int flags);
++int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
++void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
++struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
++void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
++void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
++int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
++
++/* sub-allocation manager, it has to be protected by another lock.
++ * By conception this is an helper for other part of the driver
++ * like the indirect buffer or semaphore, which both have their
++ * locking.
++ *
++ * Principe is simple, we keep a list of sub allocation in offset
++ * order (first entry has offset == 0, last entry has the highest
++ * offset).
++ *
++ * When allocating new object we first check if there is room at
++ * the end total_size - (last_object_offset + last_object_size) >=
++ * alloc_size. If so we allocate new object there.
++ *
++ * When there is not enough room at the end, we start waiting for
++ * each sub object until we reach object_offset+object_size >=
++ * alloc_size, this object then become the sub object we return.
++ *
++ * Alignment can't be bigger than page size.
++ *
++ * Hole are not considered for allocation to keep things simple.
++ * Assumption is that there won't be hole (all object on same
++ * alignment).
++ */
++struct amdgpu_sa_manager {
++	wait_queue_head_t	wq;
++	struct amdgpu_bo	*bo;
++	struct list_head	*hole;
++	struct list_head	flist[AMDGPU_MAX_RINGS];
++	struct list_head	olist;
++	unsigned		size;
++	uint64_t		gpu_addr;
++	void			*cpu_ptr;
++	uint32_t		domain;
++	uint32_t		align;
++};
++
++struct amdgpu_sa_bo;
++
++/* sub-allocation buffer */
++struct amdgpu_sa_bo {
++	struct list_head		olist;
++	struct list_head		flist;
++	struct amdgpu_sa_manager	*manager;
++	unsigned			soffset;
++	unsigned			eoffset;
++	struct amdgpu_fence		*fence;
++};
++
++/*
++ * GEM objects.
++ */
++struct amdgpu_gem {
++	struct mutex		mutex;
++	struct list_head	objects;
++};
++
++int amdgpu_gem_init(struct amdgpu_device *adev);
++void amdgpu_gem_fini(struct amdgpu_device *adev);
++int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
++				int alignment, u32 initial_domain,
++				u64 flags, bool kernel,
++				struct drm_gem_object **obj);
++
++int amdgpu_mode_dumb_create(struct drm_file *file_priv,
++			    struct drm_device *dev,
++			    struct drm_mode_create_dumb *args);
++int amdgpu_mode_dumb_mmap(struct drm_file *filp,
++			  struct drm_device *dev,
++			  uint32_t handle, uint64_t *offset_p);
++
++/*
++ * Semaphores.
++ */
++struct amdgpu_semaphore {
++	struct amdgpu_sa_bo	*sa_bo;
++	signed			waiters;
++	uint64_t		gpu_addr;
++};
++
++int amdgpu_semaphore_create(struct amdgpu_device *adev,
++			    struct amdgpu_semaphore **semaphore);
++bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
++				  struct amdgpu_semaphore *semaphore);
++bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
++				struct amdgpu_semaphore *semaphore);
++void amdgpu_semaphore_free(struct amdgpu_device *adev,
++			   struct amdgpu_semaphore **semaphore,
++			   struct amdgpu_fence *fence);
++
++/*
++ * Synchronization
++ */
++struct amdgpu_sync {
++	struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
++	struct amdgpu_fence	*sync_to[AMDGPU_MAX_RINGS];
++	struct amdgpu_fence	*last_vm_update;
++};
++
++void amdgpu_sync_create(struct amdgpu_sync *sync);
++void amdgpu_sync_fence(struct amdgpu_sync *sync,
++		       struct amdgpu_fence *fence);
++int amdgpu_sync_resv(struct amdgpu_device *adev,
++		     struct amdgpu_sync *sync,
++		     struct reservation_object *resv,
++		     void *owner);
++int amdgpu_sync_rings(struct amdgpu_sync *sync,
++		      struct amdgpu_ring *ring);
++void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
++		      struct amdgpu_fence *fence);
++
++/*
++ * GART structures, functions & helpers
++ */
++struct amdgpu_mc;
++
++#define AMDGPU_GPU_PAGE_SIZE 4096
++#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
++#define AMDGPU_GPU_PAGE_SHIFT 12
++#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
++
++struct amdgpu_gart {
++	dma_addr_t			table_addr;
++	struct amdgpu_bo		*robj;
++	void				*ptr;
++	unsigned			num_gpu_pages;
++	unsigned			num_cpu_pages;
++	unsigned			table_size;
++	struct page			**pages;
++	dma_addr_t			*pages_addr;
++	bool				ready;
++	const struct amdgpu_gart_funcs *gart_funcs;
++};
++
++int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
++void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
++int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
++void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
++int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
++void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
++int amdgpu_gart_init(struct amdgpu_device *adev);
++void amdgpu_gart_fini(struct amdgpu_device *adev);
++void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
++			int pages);
++int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
++		     int pages, struct page **pagelist,
++		     dma_addr_t *dma_addr, uint32_t flags);
++
++/*
++ * GPU MC structures, functions & helpers
++ */
++struct amdgpu_mc {
++	resource_size_t		aper_size;
++	resource_size_t		aper_base;
++	resource_size_t		agp_base;
++	/* for some chips with <= 32MB we need to lie
++	 * about vram size near mc fb location */
++	u64			mc_vram_size;
++	u64			visible_vram_size;
++	u64			gtt_size;
++	u64			gtt_start;
++	u64			gtt_end;
++	u64			vram_start;
++	u64			vram_end;
++	unsigned		vram_width;
++	u64			real_vram_size;
++	int			vram_mtrr;
++	u64                     gtt_base_align;
++	u64                     mc_mask;
++	const struct firmware   *fw;	/* MC firmware */
++	uint32_t                fw_version;
++	struct amdgpu_irq_src	vm_fault;
++	bool                    is_gddr5;
++};
++
++/*
++ * GPU doorbell structures, functions & helpers
++ */
++typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
++{
++	AMDGPU_DOORBELL_KIQ                     = 0x000,
++	AMDGPU_DOORBELL_HIQ                     = 0x001,
++	AMDGPU_DOORBELL_DIQ                     = 0x002,
++	AMDGPU_DOORBELL_MEC_RING0               = 0x010,
++	AMDGPU_DOORBELL_MEC_RING1               = 0x011,
++	AMDGPU_DOORBELL_MEC_RING2               = 0x012,
++	AMDGPU_DOORBELL_MEC_RING3               = 0x013,
++	AMDGPU_DOORBELL_MEC_RING4               = 0x014,
++	AMDGPU_DOORBELL_MEC_RING5               = 0x015,
++	AMDGPU_DOORBELL_MEC_RING6               = 0x016,
++	AMDGPU_DOORBELL_MEC_RING7               = 0x017,
++	AMDGPU_DOORBELL_GFX_RING0               = 0x020,
++	AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
++	AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
++	AMDGPU_DOORBELL_IH                      = 0x1E8,
++	AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
++	AMDGPU_DOORBELL_INVALID                 = 0xFFFF
++} AMDGPU_DOORBELL_ASSIGNMENT;
++
++struct amdgpu_doorbell {
++	/* doorbell mmio */
++	resource_size_t		base;
++	resource_size_t		size;
++	u32 __iomem		*ptr;
++	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */
++};
++
++void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
++				phys_addr_t *aperture_base,
++				size_t *aperture_size,
++				size_t *start_offset);
++
++/*
++ * IRQS.
++ */
++
++struct amdgpu_flip_work {
++	struct work_struct		flip_work;
++	struct work_struct		unpin_work;
++	struct amdgpu_device		*adev;
++	int				crtc_id;
++	uint64_t			base;
++	struct drm_pending_vblank_event *event;
++	struct amdgpu_bo		*old_rbo;
++	struct fence			*fence;
++};
++
++
++/*
++ * CP & rings.
++ */
++
++struct amdgpu_ib {
++	struct amdgpu_sa_bo		*sa_bo;
++	uint32_t			length_dw;
++	uint64_t			gpu_addr;
++	uint32_t			*ptr;
++	struct amdgpu_ring		*ring;
++	struct amdgpu_fence		*fence;
++	struct amdgpu_user_fence        *user;
++	struct amdgpu_vm		*vm;
++	bool				is_const_ib;
++	bool				flush_hdp_writefifo;
++	struct amdgpu_sync		sync;
++	bool				gds_needed;
++	uint32_t			gds_base, gds_size;
++	uint32_t			gws_base, gws_size;
++	uint32_t			oa_base, oa_size;
++};
++
++enum amdgpu_ring_type {
++	AMDGPU_RING_TYPE_GFX,
++	AMDGPU_RING_TYPE_COMPUTE,
++	AMDGPU_RING_TYPE_SDMA,
++	AMDGPU_RING_TYPE_UVD,
++	AMDGPU_RING_TYPE_VCE
++};
++
++struct amdgpu_ring {
++	struct amdgpu_device		*adev;
++	const struct amdgpu_ring_funcs	*funcs;
++	struct amdgpu_fence_driver	fence_drv;
++
++	struct mutex		*ring_lock;
++	struct amdgpu_bo	*ring_obj;
++	volatile uint32_t	*ring;
++	unsigned		rptr_offs;
++	u64			next_rptr_gpu_addr;
++	volatile u32		*next_rptr_cpu_addr;
++	unsigned		wptr;
++	unsigned		wptr_old;
++	unsigned		ring_size;
++	unsigned		ring_free_dw;
++	int			count_dw;
++	atomic_t		last_rptr;
++	atomic64_t		last_activity;
++	uint64_t		gpu_addr;
++	uint32_t		align_mask;
++	uint32_t		ptr_mask;
++	bool			ready;
++	u32			nop;
++	u32			idx;
++	u64			last_semaphore_signal_addr;
++	u64			last_semaphore_wait_addr;
++	u32			me;
++	u32			pipe;
++	u32			queue;
++	struct amdgpu_bo	*mqd_obj;
++	u32			doorbell_index;
++	bool			use_doorbell;
++	unsigned		wptr_offs;
++	unsigned		next_rptr_offs;
++	unsigned		fence_offs;
++	struct drm_file		*current_filp;
++	bool			need_ctx_switch;
++	enum amdgpu_ring_type	type;
++	char			name[16];
++};
++
++/*
++ * VM
++ */
++
++/* maximum number of VMIDs */
++#define AMDGPU_NUM_VM	16
++
++/* number of entries in page table */
++#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
++
++/* PTBs (Page Table Blocks) need to be aligned to 32K */
++#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
++#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
++#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
++
++#define AMDGPU_PTE_VALID	(1 << 0)
++#define AMDGPU_PTE_SYSTEM	(1 << 1)
++#define AMDGPU_PTE_SNOOPED	(1 << 2)
++
++/* VI only */
++#define AMDGPU_PTE_EXECUTABLE	(1 << 4)
++
++#define AMDGPU_PTE_READABLE	(1 << 5)
++#define AMDGPU_PTE_WRITEABLE	(1 << 6)
++
++/* PTE (Page Table Entry) fragment field for different page sizes */
++#define AMDGPU_PTE_FRAG_4KB	(0 << 7)
++#define AMDGPU_PTE_FRAG_64KB	(4 << 7)
++#define AMDGPU_LOG2_PAGES_PER_FRAG 4
++
++struct amdgpu_vm_pt {
++	struct amdgpu_bo		*bo;
++	uint64_t			addr;
++};
++
++struct amdgpu_vm_id {
++	unsigned		id;
++	uint64_t		pd_gpu_addr;
++	/* last flushed PD/PT update */
++	struct amdgpu_fence	*flushed_updates;
++	/* last use of vmid */
++	struct amdgpu_fence	*last_id_use;
++};
++
++struct amdgpu_vm {
++	struct mutex		mutex;
++
++	struct rb_root		va;
++
++	/* protecting invalidated and freed */
++	spinlock_t		status_lock;
++
++	/* BOs moved, but not yet updated in the PT */
++	struct list_head	invalidated;
++
++	/* BOs freed, but not yet updated in the PT */
++	struct list_head	freed;
++
++	/* contains the page directory */
++	struct amdgpu_bo	*page_directory;
++	unsigned		max_pde_used;
++
++	/* array of page tables, one for each page directory entry */
++	struct amdgpu_vm_pt	*page_tables;
++
++	/* for id and flush management per ring */
++	struct amdgpu_vm_id	ids[AMDGPU_MAX_RINGS];
++};
++
++struct amdgpu_vm_manager {
++	struct amdgpu_fence		*active[AMDGPU_NUM_VM];
++	uint32_t			max_pfn;
++	/* number of VMIDs */
++	unsigned			nvm;
++	/* vram base address for page table entry  */
++	u64				vram_base_offset;
++	/* is vm enabled? */
++	bool				enabled;
++	/* for hw to save the PD addr on suspend/resume */
++	uint32_t			saved_table_addr[AMDGPU_NUM_VM];
++	/* vm pte handling */
++	const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
++	struct amdgpu_ring                      *vm_pte_funcs_ring;
++};
++
++/*
++ * context related structures
++ */
++
++struct amdgpu_ctx_state {
++	uint64_t flags;
++	uint64_t hangs;
++};
++
++struct amdgpu_ctx {
++	/* call kref_get()before CS start and kref_put() after CS fence signaled */
++	struct kref refcount;
++	struct amdgpu_fpriv *fpriv;
++	struct amdgpu_ctx_state state;
++	uint32_t id;
++};
++
++struct amdgpu_ctx_mgr {
++	struct amdgpu_device *adev;
++	struct idr ctx_handles;
++	/* lock for IDR system */
++	struct mutex hlock;
++};
++
++/*
++ * file private structure
++ */
++
++struct amdgpu_fpriv {
++	struct amdgpu_vm	vm;
++	struct mutex		bo_list_lock;
++	struct idr		bo_list_handles;
++	struct amdgpu_ctx_mgr ctx_mgr;
++};
++
++/*
++ * residency list
++ */
++
++struct amdgpu_bo_list {
++	struct mutex lock;
++	struct amdgpu_bo *gds_obj;
++	struct amdgpu_bo *gws_obj;
++	struct amdgpu_bo *oa_obj;
++	bool has_userptr;
++	unsigned num_entries;
++	struct amdgpu_bo_list_entry *array;
++};
++
++struct amdgpu_bo_list *
++amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
++void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
++void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
++
++/*
++ * GFX stuff
++ */
++#include "clearstate_defs.h"
++
++struct amdgpu_rlc {
++	/* for power gating */
++	struct amdgpu_bo	*save_restore_obj;
++	uint64_t		save_restore_gpu_addr;
++	volatile uint32_t	*sr_ptr;
++	const u32               *reg_list;
++	u32                     reg_list_size;
++	/* for clear state */
++	struct amdgpu_bo	*clear_state_obj;
++	uint64_t		clear_state_gpu_addr;
++	volatile uint32_t	*cs_ptr;
++	const struct cs_section_def   *cs_data;
++	u32                     clear_state_size;
++	/* for cp tables */
++	struct amdgpu_bo	*cp_table_obj;
++	uint64_t		cp_table_gpu_addr;
++	volatile uint32_t	*cp_table_ptr;
++	u32                     cp_table_size;
++};
++
++struct amdgpu_mec {
++	struct amdgpu_bo	*hpd_eop_obj;
++	u64			hpd_eop_gpu_addr;
++	u32 num_pipe;
++	u32 num_mec;
++	u32 num_queue;
++};
++
++/*
++ * GPU scratch registers structures, functions & helpers
++ */
++struct amdgpu_scratch {
++	unsigned		num_reg;
++	uint32_t                reg_base;
++	bool			free[32];
++	uint32_t		reg[32];
++};
++
++/*
++ * GFX configurations
++ */
++struct amdgpu_gca_config {
++	unsigned max_shader_engines;
++	unsigned max_tile_pipes;
++	unsigned max_cu_per_sh;
++	unsigned max_sh_per_se;
++	unsigned max_backends_per_se;
++	unsigned max_texture_channel_caches;
++	unsigned max_gprs;
++	unsigned max_gs_threads;
++	unsigned max_hw_contexts;
++	unsigned sc_prim_fifo_size_frontend;
++	unsigned sc_prim_fifo_size_backend;
++	unsigned sc_hiz_tile_fifo_size;
++	unsigned sc_earlyz_tile_fifo_size;
++
++	unsigned num_tile_pipes;
++	unsigned backend_enable_mask;
++	unsigned mem_max_burst_length_bytes;
++	unsigned mem_row_size_in_kb;
++	unsigned shader_engine_tile_size;
++	unsigned num_gpus;
++	unsigned multi_gpu_tile_size;
++	unsigned mc_arb_ramcfg;
++	unsigned gb_addr_config;
++
++	uint32_t tile_mode_array[32];
++	uint32_t macrotile_mode_array[16];
++};
++
++struct amdgpu_gfx {
++	struct mutex			gpu_clock_mutex;
++	struct amdgpu_gca_config	config;
++	struct amdgpu_rlc		rlc;
++	struct amdgpu_mec		mec;
++	struct amdgpu_scratch		scratch;
++	const struct firmware		*me_fw;	/* ME firmware */
++	uint32_t			me_fw_version;
++	const struct firmware		*pfp_fw; /* PFP firmware */
++	uint32_t			pfp_fw_version;
++	const struct firmware		*ce_fw;	/* CE firmware */
++	uint32_t			ce_fw_version;
++	const struct firmware		*rlc_fw; /* RLC firmware */
++	uint32_t			rlc_fw_version;
++	const struct firmware		*mec_fw; /* MEC firmware */
++	uint32_t			mec_fw_version;
++	const struct firmware		*mec2_fw; /* MEC2 firmware */
++	uint32_t			mec2_fw_version;
++	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
++	unsigned			num_gfx_rings;
++	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
++	unsigned			num_compute_rings;
++	struct amdgpu_irq_src		eop_irq;
++	struct amdgpu_irq_src		priv_reg_irq;
++	struct amdgpu_irq_src		priv_inst_irq;
++	/* gfx status */
++	uint32_t gfx_current_status;
++	/* sync signal for const engine */
++	unsigned ce_sync_offs;
++};
++
++int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
++		  unsigned size, struct amdgpu_ib *ib);
++void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
++int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
++		       struct amdgpu_ib *ib, void *owner);
++int amdgpu_ib_pool_init(struct amdgpu_device *adev);
++void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
++int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
++/* Ring access between begin & end cannot sleep */
++void amdgpu_ring_free_size(struct amdgpu_ring *ring);
++int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
++int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
++void amdgpu_ring_commit(struct amdgpu_ring *ring);
++void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
++void amdgpu_ring_undo(struct amdgpu_ring *ring);
++void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
++void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
++bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
++unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
++			    uint32_t **data);
++int amdgpu_ring_restore(struct amdgpu_ring *ring,
++			unsigned size, uint32_t *data);
++int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
++		     unsigned ring_size, u32 nop, u32 align_mask,
++		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
++		     enum amdgpu_ring_type ring_type);
++void amdgpu_ring_fini(struct amdgpu_ring *ring);
++
++/*
++ * CS.
++ */
++struct amdgpu_cs_chunk {
++	uint32_t		chunk_id;
++	uint32_t		length_dw;
++	uint32_t		*kdata;
++	void __user		*user_ptr;
++};
++
++struct amdgpu_cs_parser {
++	struct amdgpu_device	*adev;
++	struct drm_file		*filp;
++	uint32_t ctx_id;
++	struct amdgpu_bo_list *bo_list;
++	/* chunks */
++	unsigned		nchunks;
++	struct amdgpu_cs_chunk	*chunks;
++	/* relocations */
++	struct amdgpu_bo_list_entry	*vm_bos;
++	struct amdgpu_bo_list_entry	*ib_bos;
++	struct list_head	validated;
++
++	struct amdgpu_ib	*ibs;
++	uint32_t		num_ibs;
++
++	struct ww_acquire_ctx	ticket;
++
++	/* user fence */
++	struct amdgpu_user_fence uf;
++};
++
++static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
++{
++	return p->ibs[ib_idx].ptr[idx];
++}
++
++/*
++ * Writeback
++ */
++#define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */
++
++struct amdgpu_wb {
++	struct amdgpu_bo	*wb_obj;
++	volatile uint32_t	*wb;
++	uint64_t		gpu_addr;
++	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
++	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
++};
++
++int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
++void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
++
++/**
++ * struct amdgpu_pm - power management datas
++ * It keeps track of various data needed to take powermanagement decision.
++ */
++
++enum amdgpu_pm_state_type {
++	/* not used for dpm */
++	POWER_STATE_TYPE_DEFAULT,
++	POWER_STATE_TYPE_POWERSAVE,
++	/* user selectable states */
++	POWER_STATE_TYPE_BATTERY,
++	POWER_STATE_TYPE_BALANCED,
++	POWER_STATE_TYPE_PERFORMANCE,
++	/* internal states */
++	POWER_STATE_TYPE_INTERNAL_UVD,
++	POWER_STATE_TYPE_INTERNAL_UVD_SD,
++	POWER_STATE_TYPE_INTERNAL_UVD_HD,
++	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
++	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
++	POWER_STATE_TYPE_INTERNAL_BOOT,
++	POWER_STATE_TYPE_INTERNAL_THERMAL,
++	POWER_STATE_TYPE_INTERNAL_ACPI,
++	POWER_STATE_TYPE_INTERNAL_ULV,
++	POWER_STATE_TYPE_INTERNAL_3DPERF,
++};
++
++enum amdgpu_int_thermal_type {
++	THERMAL_TYPE_NONE,
++	THERMAL_TYPE_EXTERNAL,
++	THERMAL_TYPE_EXTERNAL_GPIO,
++	THERMAL_TYPE_RV6XX,
++	THERMAL_TYPE_RV770,
++	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
++	THERMAL_TYPE_EVERGREEN,
++	THERMAL_TYPE_SUMO,
++	THERMAL_TYPE_NI,
++	THERMAL_TYPE_SI,
++	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
++	THERMAL_TYPE_CI,
++	THERMAL_TYPE_KV,
++};
++
++enum amdgpu_dpm_auto_throttle_src {
++	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
++	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
++};
++
++enum amdgpu_dpm_event_src {
++	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
++	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
++	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
++	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
++	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
++};
++
++#define AMDGPU_MAX_VCE_LEVELS 6
++
++enum amdgpu_vce_level {
++	AMDGPU_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
++	AMDGPU_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
++	AMDGPU_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
++	AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
++	AMDGPU_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
++	AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
++};
++
++struct amdgpu_ps {
++	u32 caps; /* vbios flags */
++	u32 class; /* vbios flags */
++	u32 class2; /* vbios flags */
++	/* UVD clocks */
++	u32 vclk;
++	u32 dclk;
++	/* VCE clocks */
++	u32 evclk;
++	u32 ecclk;
++	bool vce_active;
++	enum amdgpu_vce_level vce_level;
++	/* asic priv */
++	void *ps_priv;
++};
++
++struct amdgpu_dpm_thermal {
++	/* thermal interrupt work */
++	struct work_struct work;
++	/* low temperature threshold */
++	int                min_temp;
++	/* high temperature threshold */
++	int                max_temp;
++	/* was last interrupt low to high or high to low */
++	bool               high_to_low;
++	/* interrupt source */
++	struct amdgpu_irq_src	irq;
++};
++
++enum amdgpu_clk_action
++{
++	AMDGPU_SCLK_UP = 1,
++	AMDGPU_SCLK_DOWN
++};
++
++struct amdgpu_blacklist_clocks
++{
++	u32 sclk;
++	u32 mclk;
++	enum amdgpu_clk_action action;
++};
++
++struct amdgpu_clock_and_voltage_limits {
++	u32 sclk;
++	u32 mclk;
++	u16 vddc;
++	u16 vddci;
++};
++
++struct amdgpu_clock_array {
++	u32 count;
++	u32 *values;
++};
++
++struct amdgpu_clock_voltage_dependency_entry {
++	u32 clk;
++	u16 v;
++};
++
++struct amdgpu_clock_voltage_dependency_table {
++	u32 count;
++	struct amdgpu_clock_voltage_dependency_entry *entries;
++};
++
++union amdgpu_cac_leakage_entry {
++	struct {
++		u16 vddc;
++		u32 leakage;
++	};
++	struct {
++		u16 vddc1;
++		u16 vddc2;
++		u16 vddc3;
++	};
++};
++
++struct amdgpu_cac_leakage_table {
++	u32 count;
++	union amdgpu_cac_leakage_entry *entries;
++};
++
++struct amdgpu_phase_shedding_limits_entry {
++	u16 voltage;
++	u32 sclk;
++	u32 mclk;
++};
++
++struct amdgpu_phase_shedding_limits_table {
++	u32 count;
++	struct amdgpu_phase_shedding_limits_entry *entries;
++};
++
++struct amdgpu_uvd_clock_voltage_dependency_entry {
++	u32 vclk;
++	u32 dclk;
++	u16 v;
++};
++
++struct amdgpu_uvd_clock_voltage_dependency_table {
++	u8 count;
++	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
++};
++
++struct amdgpu_vce_clock_voltage_dependency_entry {
++	u32 ecclk;
++	u32 evclk;
++	u16 v;
++};
++
++struct amdgpu_vce_clock_voltage_dependency_table {
++	u8 count;
++	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
++};
++
++struct amdgpu_ppm_table {
++	u8 ppm_design;
++	u16 cpu_core_number;
++	u32 platform_tdp;
++	u32 small_ac_platform_tdp;
++	u32 platform_tdc;
++	u32 small_ac_platform_tdc;
++	u32 apu_tdp;
++	u32 dgpu_tdp;
++	u32 dgpu_ulv_power;
++	u32 tj_max;
++};
++
++struct amdgpu_cac_tdp_table {
++	u16 tdp;
++	u16 configurable_tdp;
++	u16 tdc;
++	u16 battery_power_limit;
++	u16 small_power_limit;
++	u16 low_cac_leakage;
++	u16 high_cac_leakage;
++	u16 maximum_power_delivery_limit;
++};
++
++struct amdgpu_dpm_dynamic_state {
++	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
++	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
++	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
++	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
++	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
++	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
++	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
++	struct amdgpu_clock_array valid_sclk_values;
++	struct amdgpu_clock_array valid_mclk_values;
++	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
++	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
++	u32 mclk_sclk_ratio;
++	u32 sclk_mclk_delta;
++	u16 vddc_vddci_delta;
++	u16 min_vddc_for_pcie_gen2;
++	struct amdgpu_cac_leakage_table cac_leakage_table;
++	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
++	struct amdgpu_ppm_table *ppm_table;
++	struct amdgpu_cac_tdp_table *cac_tdp_table;
++};
++
++struct amdgpu_dpm_fan {
++	u16 t_min;
++	u16 t_med;
++	u16 t_high;
++	u16 pwm_min;
++	u16 pwm_med;
++	u16 pwm_high;
++	u8 t_hyst;
++	u32 cycle_delay;
++	u16 t_max;
++	u8 control_mode;
++	u16 default_max_fan_pwm;
++	u16 default_fan_output_sensitivity;
++	u16 fan_output_sensitivity;
++	bool ucode_fan_control;
++};
++
++enum amdgpu_pcie_gen {
++	AMDGPU_PCIE_GEN1 = 0,
++	AMDGPU_PCIE_GEN2 = 1,
++	AMDGPU_PCIE_GEN3 = 2,
++	AMDGPU_PCIE_GEN_INVALID = 0xffff
++};
++
++enum amdgpu_dpm_forced_level {
++	AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
++	AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
++	AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
++};
++
++struct amdgpu_vce_state {
++	/* vce clocks */
++	u32 evclk;
++	u32 ecclk;
++	/* gpu clocks */
++	u32 sclk;
++	u32 mclk;
++	u8 clk_idx;
++	u8 pstate;
++};
++
++struct amdgpu_dpm_funcs {
++	int (*get_temperature)(struct amdgpu_device *adev);
++	int (*pre_set_power_state)(struct amdgpu_device *adev);
++	int (*set_power_state)(struct amdgpu_device *adev);
++	void (*post_set_power_state)(struct amdgpu_device *adev);
++	void (*display_configuration_changed)(struct amdgpu_device *adev);
++	u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
++	u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
++	void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
++	void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
++	int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
++	bool (*vblank_too_short)(struct amdgpu_device *adev);
++	void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
++	void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
++	void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
++	u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
++	int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
++	int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
++};
++
++struct amdgpu_dpm {
++	struct amdgpu_ps        *ps;
++	/* number of valid power states */
++	int                     num_ps;
++	/* current power state that is active */
++	struct amdgpu_ps        *current_ps;
++	/* requested power state */
++	struct amdgpu_ps        *requested_ps;
++	/* boot up power state */
++	struct amdgpu_ps        *boot_ps;
++	/* default uvd power state */
++	struct amdgpu_ps        *uvd_ps;
++	/* vce requirements */
++	struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
++	enum amdgpu_vce_level vce_level;
++	enum amdgpu_pm_state_type state;
++	enum amdgpu_pm_state_type user_state;
++	u32                     platform_caps;
++	u32                     voltage_response_time;
++	u32                     backbias_response_time;
++	void                    *priv;
++	u32			new_active_crtcs;
++	int			new_active_crtc_count;
++	u32			current_active_crtcs;
++	int			current_active_crtc_count;
++	struct amdgpu_dpm_dynamic_state dyn_state;
++	struct amdgpu_dpm_fan fan;
++	u32 tdp_limit;
++	u32 near_tdp_limit;
++	u32 near_tdp_limit_adjusted;
++	u32 sq_ramping_threshold;
++	u32 cac_leakage;
++	u16 tdp_od_limit;
++	u32 tdp_adjustment;
++	u16 load_line_slope;
++	bool power_control;
++	bool ac_power;
++	/* special states active */
++	bool                    thermal_active;
++	bool                    uvd_active;
++	bool                    vce_active;
++	/* thermal handling */
++	struct amdgpu_dpm_thermal thermal;
++	/* forced levels */
++	enum amdgpu_dpm_forced_level forced_level;
++};
++
++struct amdgpu_pm {
++	struct mutex		mutex;
++	/* write locked while reprogramming mclk */
++	struct rw_semaphore	mclk_lock;
++	u32                     current_sclk;
++	u32                     current_mclk;
++	u32                     default_sclk;
++	u32                     default_mclk;
++	struct amdgpu_i2c_chan *i2c_bus;
++	/* internal thermal controller on rv6xx+ */
++	enum amdgpu_int_thermal_type int_thermal_type;
++	struct device	        *int_hwmon_dev;
++	/* fan control parameters */
++	bool                    no_fan;
++	u8                      fan_pulses_per_revolution;
++	u8                      fan_min_rpm;
++	u8                      fan_max_rpm;
++	/* dpm */
++	bool                    dpm_enabled;
++	struct amdgpu_dpm       dpm;
++	const struct firmware	*fw;	/* SMC firmware */
++	uint32_t                fw_version;
++	const struct amdgpu_dpm_funcs *funcs;
++};
++
++/*
++ * UVD
++ */
++#define AMDGPU_MAX_UVD_HANDLES	10
++#define AMDGPU_UVD_STACK_SIZE	(1024*1024)
++#define AMDGPU_UVD_HEAP_SIZE	(1024*1024)
++#define AMDGPU_UVD_FIRMWARE_OFFSET 256
++
++struct amdgpu_uvd {
++	struct amdgpu_bo	*vcpu_bo;
++	void			*cpu_addr;
++	uint64_t		gpu_addr;
++	void			*saved_bo;
++	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
++	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
++	struct delayed_work	idle_work;
++	const struct firmware	*fw;	/* UVD firmware */
++	struct amdgpu_ring	ring;
++	struct amdgpu_irq_src	irq;
++	bool			address_64_bit;
++};
++
++/*
++ * VCE
++ */
++#define AMDGPU_MAX_VCE_HANDLES	16
++#define AMDGPU_VCE_STACK_SIZE	(1024*1024)
++#define AMDGPU_VCE_HEAP_SIZE	(4*1024*1024)
++#define AMDGPU_VCE_FIRMWARE_OFFSET 256
++
++struct amdgpu_vce {
++	struct amdgpu_bo	*vcpu_bo;
++	uint64_t		gpu_addr;
++	unsigned		fw_version;
++	unsigned		fb_version;
++	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];
++	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];
++	struct delayed_work	idle_work;
++	const struct firmware	*fw;	/* VCE firmware */
++	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
++	struct amdgpu_irq_src	irq;
++};
++
++/*
++ * SDMA
++ */
++struct amdgpu_sdma {
++	/* SDMA firmware */
++	const struct firmware	*fw;
++	uint32_t		fw_version;
++
++	struct amdgpu_ring	ring;
++};
++
++/*
++ * Firmware
++ */
++struct amdgpu_firmware {
++	struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
++	bool smu_load;
++	struct amdgpu_bo *fw_buf;
++	unsigned int fw_size;
++};
++
++/*
++ * Benchmarking
++ */
++void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
++
++
++/*
++ * Testing
++ */
++void amdgpu_test_moves(struct amdgpu_device *adev);
++void amdgpu_test_ring_sync(struct amdgpu_device *adev,
++			   struct amdgpu_ring *cpA,
++			   struct amdgpu_ring *cpB);
++void amdgpu_test_syncing(struct amdgpu_device *adev);
++
++/*
++ * MMU Notifier
++ */
++#if defined(CONFIG_MMU_NOTIFIER)
++int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
++void amdgpu_mn_unregister(struct amdgpu_bo *bo);
++#else
++static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
++{
++	return -ENODEV;
++}
++static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
++#endif
++
++/*
++ * Debugfs
++ */
++struct amdgpu_debugfs {
++	struct drm_info_list	*files;
++	unsigned		num_files;
++};
++
++int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
++			     struct drm_info_list *files,
++			     unsigned nfiles);
++int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
++
++#if defined(CONFIG_DEBUG_FS)
++int amdgpu_debugfs_init(struct drm_minor *minor);
++void amdgpu_debugfs_cleanup(struct drm_minor *minor);
++#endif
++
++/*
++ * amdgpu smumgr functions
++ */
++struct amdgpu_smumgr_funcs {
++	int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
++	int (*request_smu_load_fw)(struct amdgpu_device *adev);
++	int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
++};
++
++/*
++ * amdgpu smumgr
++ */
++struct amdgpu_smumgr {
++	struct amdgpu_bo *toc_buf;
++	struct amdgpu_bo *smu_buf;
++	/* asic priv smu data */
++	void *priv;
++	spinlock_t smu_lock;
++	/* smumgr functions */
++	const struct amdgpu_smumgr_funcs *smumgr_funcs;
++	/* ucode loading complete flag */
++	uint32_t fw_flags;
++};
++
++/*
++ * ASIC specific register table accessible by UMD
++ */
++struct amdgpu_allowed_register_entry {
++	uint32_t reg_offset;
++	bool untouched;
++	bool grbm_indexed;
++};
++
++struct amdgpu_cu_info {
++	uint32_t number; /* total active CU number */
++	uint32_t ao_cu_mask;
++	uint32_t bitmap[4][4];
++};
++
++
++/*
++ * ASIC specific functions.
++ */
++struct amdgpu_asic_funcs {
++	bool (*read_disabled_bios)(struct amdgpu_device *adev);
++	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
++			     u32 sh_num, u32 reg_offset, u32 *value);
++	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
++	int (*reset)(struct amdgpu_device *adev);
++	/* wait for mc_idle */
++	int (*wait_for_mc_idle)(struct amdgpu_device *adev);
++	/* get the reference clock */
++	u32 (*get_xclk)(struct amdgpu_device *adev);
++	/* get the gpu clock counter */
++	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
++	int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
++	/* MM block clocks */
++	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
++	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
++};
++
++/*
++ * IOCTL.
++ */
++int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
++			    struct drm_file *filp);
++int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
++				struct drm_file *filp);
++
++int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
++			  struct drm_file *filp);
++int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *filp);
++int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
++			  struct drm_file *filp);
++int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
++			      struct drm_file *filp);
++int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
++			  struct drm_file *filp);
++int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *filp);
++int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
++int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
++
++int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
++				struct drm_file *filp);
++
++/* VRAM scratch page for HDP bug, default vram page */
++struct amdgpu_vram_scratch {
++	struct amdgpu_bo		*robj;
++	volatile uint32_t		*ptr;
++	u64				gpu_addr;
++};
++
++/*
++ * ACPI
++ */
++struct amdgpu_atif_notification_cfg {
++	bool enabled;
++	int command_code;
++};
++
++struct amdgpu_atif_notifications {
++	bool display_switch;
++	bool expansion_mode_change;
++	bool thermal_state;
++	bool forced_power_state;
++	bool system_power_state;
++	bool display_conf_change;
++	bool px_gfx_switch;
++	bool brightness_change;
++	bool dgpu_display_event;
++};
++
++struct amdgpu_atif_functions {
++	bool system_params;
++	bool sbios_requests;
++	bool select_active_disp;
++	bool lid_state;
++	bool get_tv_standard;
++	bool set_tv_standard;
++	bool get_panel_expansion_mode;
++	bool set_panel_expansion_mode;
++	bool temperature_change;
++	bool graphics_device_types;
++};
++
++struct amdgpu_atif {
++	struct amdgpu_atif_notifications notifications;
++	struct amdgpu_atif_functions functions;
++	struct amdgpu_atif_notification_cfg notification_cfg;
++	struct amdgpu_encoder *encoder_for_bl;
++};
++
++struct amdgpu_atcs_functions {
++	bool get_ext_state;
++	bool pcie_perf_req;
++	bool pcie_dev_rdy;
++	bool pcie_bus_width;
++};
++
++struct amdgpu_atcs {
++	struct amdgpu_atcs_functions functions;
++};
++
++int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv,
++							uint32_t *id,uint32_t flags);
++int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
++						  uint32_t id);
++int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
++							uint32_t id,struct amdgpu_ctx_state *state);
++
++void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
++
++extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
++						 struct drm_file *filp);
++
++/*
++ * Core structure, functions and helpers.
++ */
++typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
++typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
++
++typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
++typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
++
++struct amdgpu_device {
++	struct device			*dev;
++	struct drm_device		*ddev;
++	struct pci_dev			*pdev;
++	struct rw_semaphore		exclusive_lock;
++
++	/* ASIC */
++	enum amdgpu_asic_type           asic_type;
++	uint32_t			family;
++	uint32_t			rev_id;
++	uint32_t			external_rev_id;
++	unsigned long			flags;
++	int				usec_timeout;
++	const struct amdgpu_asic_funcs	*asic_funcs;
++	bool				shutdown;
++	bool				suspend;
++	bool				need_dma32;
++	bool				accel_working;
++	bool				needs_reset;
++	struct work_struct 		reset_work;
++	struct notifier_block		acpi_nb;
++	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
++	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
++	unsigned 			debugfs_count;
++#if defined(CONFIG_DEBUG_FS)
++	struct dentry			*debugfs_regs;
++#endif
++	struct amdgpu_atif		atif;
++	struct amdgpu_atcs		atcs;
++	struct mutex			srbm_mutex;
++	/* GRBM index mutex. Protects concurrent access to GRBM index */
++	struct mutex                    grbm_idx_mutex;
++	struct dev_pm_domain		vga_pm_domain;
++	bool				have_disp_power_ref;
++
++	/* BIOS */
++	uint8_t				*bios;
++	bool				is_atom_bios;
++	uint16_t			bios_header_start;
++	struct amdgpu_bo		*stollen_vga_memory;
++	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
++
++	/* Register/doorbell mmio */
++	resource_size_t			rmmio_base;
++	resource_size_t			rmmio_size;
++	void __iomem			*rmmio;
++	/* protects concurrent MM_INDEX/DATA based register access */
++	spinlock_t mmio_idx_lock;
++	/* protects concurrent SMC based register access */
++	spinlock_t smc_idx_lock;
++	amdgpu_rreg_t			smc_rreg;
++	amdgpu_wreg_t			smc_wreg;
++	/* protects concurrent PCIE register access */
++	spinlock_t pcie_idx_lock;
++	amdgpu_rreg_t			pcie_rreg;
++	amdgpu_wreg_t			pcie_wreg;
++	/* protects concurrent UVD register access */
++	spinlock_t uvd_ctx_idx_lock;
++	amdgpu_rreg_t			uvd_ctx_rreg;
++	amdgpu_wreg_t			uvd_ctx_wreg;
++	/* protects concurrent DIDT register access */
++	spinlock_t didt_idx_lock;
++	amdgpu_rreg_t			didt_rreg;
++	amdgpu_wreg_t			didt_wreg;
++	/* protects concurrent ENDPOINT (audio) register access */
++	spinlock_t audio_endpt_idx_lock;
++	amdgpu_block_rreg_t		audio_endpt_rreg;
++	amdgpu_block_wreg_t		audio_endpt_wreg;
++	void __iomem                    *rio_mem;
++	resource_size_t			rio_mem_size;
++	struct amdgpu_doorbell		doorbell;
++
++	/* clock/pll info */
++	struct amdgpu_clock            clock;
++
++	/* MC */
++	struct amdgpu_mc		mc;
++	struct amdgpu_gart		gart;
++	struct amdgpu_dummy_page	dummy_page;
++	struct amdgpu_vm_manager	vm_manager;
++
++	/* memory management */
++	struct amdgpu_mman		mman;
++	struct amdgpu_gem		gem;
++	struct amdgpu_vram_scratch	vram_scratch;
++	struct amdgpu_wb		wb;
++	atomic64_t			vram_usage;
++	atomic64_t			vram_vis_usage;
++	atomic64_t			gtt_usage;
++	atomic64_t			num_bytes_moved;
++
++	/* display */
++	struct amdgpu_mode_info		mode_info;
++	struct work_struct		hotplug_work;
++	struct amdgpu_irq_src		crtc_irq;
++	struct amdgpu_irq_src		pageflip_irq;
++	struct amdgpu_irq_src		hpd_irq;
++
++	/* rings */
++	wait_queue_head_t		fence_queue;
++	unsigned			fence_context;
++	struct mutex			ring_lock;
++	unsigned			num_rings;
++	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
++	bool				ib_pool_ready;
++	struct amdgpu_sa_manager	ring_tmp_bo;
++
++	/* interrupts */
++	struct amdgpu_irq		irq;
++
++	/* dpm */
++	struct amdgpu_pm		pm;
++	u32				cg_flags;
++	u32				pg_flags;
++
++	/* amdgpu smumgr */
++	struct amdgpu_smumgr smu;
++
++	/* gfx */
++	struct amdgpu_gfx		gfx;
++
++	/* sdma */
++	struct amdgpu_sdma		sdma[2];
++	struct amdgpu_irq_src		sdma_trap_irq;
++	struct amdgpu_irq_src		sdma_illegal_inst_irq;
++
++	/* uvd */
++	bool				has_uvd;
++	struct amdgpu_uvd		uvd;
++
++	/* vce */
++	struct amdgpu_vce		vce;
++
++	/* firmwares */
++	struct amdgpu_firmware		firmware;
++
++	/* GDS */
++	struct amdgpu_gds		gds;
++
++	const struct amdgpu_ip_block_version *ip_blocks;
++	int				num_ip_blocks;
++	bool				*ip_block_enabled;
++	struct mutex	mn_lock;
++	DECLARE_HASHTABLE(mn_hash, 7);
++
++	/* tracking pinned memory */
++	u64 vram_pin_size;
++	u64 gart_pin_size;
++};
++
++bool amdgpu_device_is_px(struct drm_device *dev);
++int amdgpu_device_init(struct amdgpu_device *adev,
++		       struct drm_device *ddev,
++		       struct pci_dev *pdev,
++		       uint32_t flags);
++void amdgpu_device_fini(struct amdgpu_device *adev);
++int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
++
++uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
++			bool always_indirect);
++void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
++		    bool always_indirect);
++u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
++void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
++
++u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
++void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
++
++/*
++ * Cast helper
++ */
++extern const struct fence_ops amdgpu_fence_ops;
++static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
++{
++	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
++
++	if (__f->base.ops == &amdgpu_fence_ops)
++		return __f;
++
++	return NULL;
++}
++
++/*
++ * Registers read & write functions.
++ */
++#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
++#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
++#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
++#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
++#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
++#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
++#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
++#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
++#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
++#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
++#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
++#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
++#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
++#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
++#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
++#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
++#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
++#define WREG32_P(reg, val, mask)				\
++	do {							\
++		uint32_t tmp_ = RREG32(reg);			\
++		tmp_ &= (mask);					\
++		tmp_ |= ((val) & ~(mask));			\
++		WREG32(reg, tmp_);				\
++	} while (0)
++#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
++#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
++#define WREG32_PLL_P(reg, val, mask)				\
++	do {							\
++		uint32_t tmp_ = RREG32_PLL(reg);		\
++		tmp_ &= (mask);					\
++		tmp_ |= ((val) & ~(mask));			\
++		WREG32_PLL(reg, tmp_);				\
++	} while (0)
++#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
++#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
++#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
++
++#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
++#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
++
++#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
++#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
++
++#define REG_SET_FIELD(orig_val, reg, field, field_val)			\
++	(((orig_val) & ~REG_FIELD_MASK(reg, field)) |			\
++	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
++
++#define REG_GET_FIELD(value, reg, field)				\
++	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
++
++/*
++ * BIOS helpers.
++ */
++#define RBIOS8(i) (adev->bios[i])
++#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
++#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
++
++/*
++ * RING helpers.
++ */
++static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
++{
++	if (ring->count_dw <= 0)
++		DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
++	ring->ring[ring->wptr++] = v;
++	ring->wptr &= ring->ptr_mask;
++	ring->count_dw--;
++	ring->ring_free_dw--;
++}
++
++/*
++ * ASICs macro.
++ */
++#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
++#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
++#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
++#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
++#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
++#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
++#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
++#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
++#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
++#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
++#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
++#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
++#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
++#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
++#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
++#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
++#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
++#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
++#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
++#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
++#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
++#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
++#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
++#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
++#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
++#define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit))
++#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
++#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
++#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
++#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
++#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
++#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
++#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
++#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
++#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
++#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
++#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
++#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
++#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
++#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
++#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
++#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
++#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
++#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
++#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
++#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
++#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
++#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
++#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
++#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
++#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
++#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
++#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
++#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
++#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
++#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
++#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
++#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
++#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
++#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
++#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
++#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
++#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
++#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
++#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
++#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
++
++#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
++
++/* Common functions */
++int amdgpu_gpu_reset(struct amdgpu_device *adev);
++void amdgpu_pci_config_reset(struct amdgpu_device *adev);
++bool amdgpu_card_posted(struct amdgpu_device *adev);
++void amdgpu_update_display_priority(struct amdgpu_device *adev);
++bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
++int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
++int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
++		       u32 ip_instance, u32 ring,
++		       struct amdgpu_ring **out_ring);
++void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
++bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
++int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
++				     uint32_t flags);
++bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
++bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
++uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
++				 struct ttm_mem_reg *mem);
++void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
++void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
++void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
++void amdgpu_program_register_sequence(struct amdgpu_device *adev,
++					     const u32 *registers,
++					     const u32 array_size);
++
++bool amdgpu_device_is_px(struct drm_device *dev);
++/* atpx handler */
++#if defined(CONFIG_VGA_SWITCHEROO)
++void amdgpu_register_atpx_handler(void);
++void amdgpu_unregister_atpx_handler(void);
++#else
++static inline void amdgpu_register_atpx_handler(void) {}
++static inline void amdgpu_unregister_atpx_handler(void) {}
++#endif
++
++/*
++ * KMS
++ */
++extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
++extern int amdgpu_max_kms_ioctl;
++
++int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
++int amdgpu_driver_unload_kms(struct drm_device *dev);
++void amdgpu_driver_lastclose_kms(struct drm_device *dev);
++int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
++void amdgpu_driver_postclose_kms(struct drm_device *dev,
++				 struct drm_file *file_priv);
++void amdgpu_driver_preclose_kms(struct drm_device *dev,
++				struct drm_file *file_priv);
++int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
++int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
++u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
++int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
++void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
++int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
++				    int *max_error,
++				    struct timeval *vblank_time,
++				    unsigned flags);
++long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
++			     unsigned long arg);
++
++/*
++ * vm
++ */
++int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
++void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
++struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
++					  struct amdgpu_vm *vm,
++					  struct list_head *head);
++struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring,
++				       struct amdgpu_vm *vm);
++void amdgpu_vm_flush(struct amdgpu_ring *ring,
++		     struct amdgpu_vm *vm,
++		     struct amdgpu_fence *updates);
++void amdgpu_vm_fence(struct amdgpu_device *adev,
++		     struct amdgpu_vm *vm,
++		     struct amdgpu_fence *fence);
++uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
++int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
++				    struct amdgpu_vm *vm);
++int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
++				struct amdgpu_vm *vm);
++int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
++				struct amdgpu_vm *vm);
++int amdgpu_vm_bo_update(struct amdgpu_device *adev,
++			struct amdgpu_bo_va *bo_va,
++			struct ttm_mem_reg *mem);
++void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
++			     struct amdgpu_bo *bo);
++struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
++				       struct amdgpu_bo *bo);
++struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
++				      struct amdgpu_vm *vm,
++				      struct amdgpu_bo *bo);
++int amdgpu_vm_bo_map(struct amdgpu_device *adev,
++		     struct amdgpu_bo_va *bo_va,
++		     uint64_t addr, uint64_t offset,
++		     uint64_t size, uint32_t flags);
++int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
++		       struct amdgpu_bo_va *bo_va,
++		       uint64_t addr);
++void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
++		      struct amdgpu_bo_va *bo_va);
++
++/*
++ * functions used by amdgpu_encoder.c
++ */
++struct amdgpu_afmt_acr {
++	u32 clock;
++
++	int n_32khz;
++	int cts_32khz;
++
++	int n_44_1khz;
++	int cts_44_1khz;
++
++	int n_48khz;
++	int cts_48khz;
++
++};
++
++struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
++
++/* amdgpu_acpi.c */
++#if defined(CONFIG_ACPI)
++int amdgpu_acpi_init(struct amdgpu_device *adev);
++void amdgpu_acpi_fini(struct amdgpu_device *adev);
++bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
++int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
++						u8 perf_req, bool advertise);
++int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
++#else
++static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
++static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
++#endif
++
++struct amdgpu_bo_va_mapping *
++amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
++		       uint64_t addr, struct amdgpu_bo **bo);
++
++#include "amdgpu_object.h"
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0035-yocto-amd-drm-amdgpu-add-GCA-7-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0035-yocto-amd-drm-amdgpu-add-GCA-7-0-register-headers.patch
new file mode 100644
index 00000000..193fb4f2
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0035-yocto-amd-drm-amdgpu-add-GCA-7-0-register-headers.patch
@@ -0,0 +1,34087 @@
+From fa0009cd518c0c131a04b309b7b25ce2af688d90 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 16:55:21 -0400
+Subject: drm/amdgpu: add core driver
+
+This adds the non-asic specific core driver code.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
+index 47f2ce8..1a39f24 100644
+--- a/drivers/gpu/drm/Kconfig
++++ b/drivers/gpu/drm/Kconfig
+@@ -121,6 +121,28 @@ config DRM_RADEON
+ 
+ source "drivers/gpu/drm/radeon/Kconfig"
+ 
++config DRM_AMDGPU
++	tristate "AMD GPU"
++	depends on DRM && PCI
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	select FW_LOADER
++        select DRM_KMS_HELPER
++	select DRM_KMS_FB_HELPER
++        select DRM_TTM
++	select POWER_SUPPLY
++	select HWMON
++	select BACKLIGHT_CLASS_DEVICE
++	select DRM_AMD_GNB_BUS
++	select INTERVAL_TREE
++	help
++	  Choose this option if you have a recent AMD Radeon graphics card.
++
++	  If M is selected, the module will be called amdgpu.
++
++source "drivers/gpu/drm/amd/amdgpu/Kconfig"
++
+ source "drivers/gpu/drm/nouveau/Kconfig"
+ 
+ config DRM_I810
+diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
+index 7d4944e..ca5cf1a 100644
+--- a/drivers/gpu/drm/Makefile
++++ b/drivers/gpu/drm/Makefile
+@@ -39,5 +39,6 @@ obj-$(CONFIG_DRM_TDFX)	+= tdfx/
+ obj-$(CONFIG_DRM_R128)	+= r128/
+ obj-$(CONFIG_DRM_RADEON)+= radeon/
++obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
+ obj-$(CONFIG_DRM_MGA)	+= mga/
+ obj-$(CONFIG_DRM_I810)	+= i810/
+ obj-$(CONFIG_DRM_I915)  += i915/
+diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig
+new file mode 100644
+index 0000000..b30fcfa
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
+@@ -0,0 +1,17 @@
++config DRM_AMDGPU_CIK
++	bool "Enable amdgpu support for CIK parts"
++	depends on DRM_AMDGPU
++	help
++	  Choose this option if you want to enable experimental support
++	  for CIK asics.
++
++	  CIK is already supported in radeon.  CIK support in amdgpu
++	  is for experimentation and testing.
++
++config DRM_AMDGPU_USERPTR
++	bool "Always enable userptr write support"
++	depends on DRM_AMDGPU
++	select MMU_NOTIFIER
++	help
++	  This option selects CONFIG_MMU_NOTIFIER if it isn't already
++	  selected to enabled full userptr support.
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+new file mode 100644
+index 0000000..01276a5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -0,0 +1,49 @@
++#
++# Makefile for the drm device driver.  This driver provides support for the
++# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
++
++ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg
++
++amdgpu-y := amdgpu_drv.o
++
++# add KMS driver
++amdgpu-y += amdgpu_device.o amdgpu_kms.o \
++	amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \
++	atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \
++	amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \
++	amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \
++	amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \
++	amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \
++	atombios_encoders.o amdgpu_semaphore.o amdgpu_sa.o atombios_i2c.o \
++	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
++	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
++
++# add IH block
++amdgpu-y += \
++	amdgpu_irq.o \
++	amdgpu_ih.o
++
++# add SMC block
++amdgpu-y += \
++	amdgpu_dpm.o
++
++# add GFX block
++amdgpu-y += \
++	amdgpu_gfx.o
++
++# add UVD block
++amdgpu-y += \
++	amdgpu_uvd.o
++
++# add VCE block
++amdgpu-y += \
++	amdgpu_vce.o
++
++amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
++amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
++amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
++amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
++
++obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
++
++CFLAGS_amdgpu_trace_points.o := -I$(src)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+new file mode 100644
+index 0000000..aef4a7a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+@@ -0,0 +1,768 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/acpi.h>
++#include <linux/slab.h>
++#include <linux/power_supply.h>
++#include <linux/vga_switcheroo.h>
++#include <acpi/video.h>
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include "amdgpu.h"
++#include "amdgpu_acpi.h"
++#include "atom.h"
++
++#define ACPI_AC_CLASS           "ac_adapter"
++
++extern void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
++
++struct atif_verify_interface {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u16 version;		/* version */
++	u32 notification_mask;	/* supported notifications mask */
++	u32 function_bits;	/* supported functions bit vector */
++} __packed;
++
++struct atif_system_params {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u32 valid_mask;		/* valid flags mask */
++	u32 flags;		/* flags */
++	u8 command_code;	/* notify command code */
++} __packed;
++
++struct atif_sbios_requests {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u32 pending;		/* pending sbios requests */
++	u8 panel_exp_mode;	/* panel expansion mode */
++	u8 thermal_gfx;		/* thermal state: target gfx controller */
++	u8 thermal_state;	/* thermal state: state id (0: exit state, non-0: state) */
++	u8 forced_power_gfx;	/* forced power state: target gfx controller */
++	u8 forced_power_state;	/* forced power state: state id */
++	u8 system_power_src;	/* system power source */
++	u8 backlight_level;	/* panel backlight level (0-255) */
++} __packed;
++
++#define ATIF_NOTIFY_MASK	0x3
++#define ATIF_NOTIFY_NONE	0
++#define ATIF_NOTIFY_81		1
++#define ATIF_NOTIFY_N		2
++
++struct atcs_verify_interface {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u16 version;		/* version */
++	u32 function_bits;	/* supported functions bit vector */
++} __packed;
++
++#define ATCS_VALID_FLAGS_MASK	0x3
++
++struct atcs_pref_req_input {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u16 client_id;		/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
++	u16 valid_flags_mask;	/* valid flags mask */
++	u16 flags;		/* flags */
++	u8 req_type;		/* request type */
++	u8 perf_req;		/* performance request */
++} __packed;
++
++struct atcs_pref_req_output {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u8 ret_val;		/* return value */
++} __packed;
++
++/* Call the ATIF method
++ */
++/**
++ * amdgpu_atif_call - call an ATIF method
++ *
++ * @handle: acpi handle
++ * @function: the ATIF function to execute
++ * @params: ATIF function params
++ *
++ * Executes the requested ATIF function (all asics).
++ * Returns a pointer to the acpi output buffer.
++ */
++static union acpi_object *amdgpu_atif_call(acpi_handle handle, int function,
++		struct acpi_buffer *params)
++{
++	acpi_status status;
++	union acpi_object atif_arg_elements[2];
++	struct acpi_object_list atif_arg;
++	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
++
++	atif_arg.count = 2;
++	atif_arg.pointer = &atif_arg_elements[0];
++
++	atif_arg_elements[0].type = ACPI_TYPE_INTEGER;
++	atif_arg_elements[0].integer.value = function;
++
++	if (params) {
++		atif_arg_elements[1].type = ACPI_TYPE_BUFFER;
++		atif_arg_elements[1].buffer.length = params->length;
++		atif_arg_elements[1].buffer.pointer = params->pointer;
++	} else {
++		/* We need a second fake parameter */
++		atif_arg_elements[1].type = ACPI_TYPE_INTEGER;
++		atif_arg_elements[1].integer.value = 0;
++	}
++
++	status = acpi_evaluate_object(handle, "ATIF", &atif_arg, &buffer);
++
++	/* Fail only if calling the method fails and ATIF is supported */
++	if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
++		DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n",
++				 acpi_format_exception(status));
++		kfree(buffer.pointer);
++		return NULL;
++	}
++
++	return buffer.pointer;
++}
++
++/**
++ * amdgpu_atif_parse_notification - parse supported notifications
++ *
++ * @n: supported notifications struct
++ * @mask: supported notifications mask from ATIF
++ *
++ * Use the supported notifications mask from ATIF function
++ * ATIF_FUNCTION_VERIFY_INTERFACE to determine what notifications
++ * are supported (all asics).
++ */
++static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask)
++{
++	n->display_switch = mask & ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED;
++	n->expansion_mode_change = mask & ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED;
++	n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED;
++	n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED;
++	n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED;
++	n->display_conf_change = mask & ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED;
++	n->px_gfx_switch = mask & ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED;
++	n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED;
++	n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED;
++}
++
++/**
++ * amdgpu_atif_parse_functions - parse supported functions
++ *
++ * @f: supported functions struct
++ * @mask: supported functions mask from ATIF
++ *
++ * Use the supported functions mask from ATIF function
++ * ATIF_FUNCTION_VERIFY_INTERFACE to determine what functions
++ * are supported (all asics).
++ */
++static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mask)
++{
++	f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED;
++	f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED;
++	f->select_active_disp = mask & ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED;
++	f->lid_state = mask & ATIF_GET_LID_STATE_SUPPORTED;
++	f->get_tv_standard = mask & ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED;
++	f->set_tv_standard = mask & ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED;
++	f->get_panel_expansion_mode = mask & ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED;
++	f->set_panel_expansion_mode = mask & ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED;
++	f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED;
++	f->graphics_device_types = mask & ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED;
++}
++
++/**
++ * amdgpu_atif_verify_interface - verify ATIF
++ *
++ * @handle: acpi handle
++ * @atif: amdgpu atif struct
++ *
++ * Execute the ATIF_FUNCTION_VERIFY_INTERFACE ATIF function
++ * to initialize ATIF and determine what features are supported
++ * (all asics).
++ * returns 0 on success, error on failure.
++ */
++static int amdgpu_atif_verify_interface(acpi_handle handle,
++		struct amdgpu_atif *atif)
++{
++	union acpi_object *info;
++	struct atif_verify_interface output;
++	size_t size;
++	int err = 0;
++
++	info = amdgpu_atif_call(handle, ATIF_FUNCTION_VERIFY_INTERFACE, NULL);
++	if (!info)
++		return -EIO;
++
++	memset(&output, 0, sizeof(output));
++
++	size = *(u16 *) info->buffer.pointer;
++	if (size < 12) {
++		DRM_INFO("ATIF buffer is too small: %zu\n", size);
++		err = -EINVAL;
++		goto out;
++	}
++	size = min(sizeof(output), size);
++
++	memcpy(&output, info->buffer.pointer, size);
++
++	/* TODO: check version? */
++	DRM_DEBUG_DRIVER("ATIF version %u\n", output.version);
++
++	amdgpu_atif_parse_notification(&atif->notifications, output.notification_mask);
++	amdgpu_atif_parse_functions(&atif->functions, output.function_bits);
++
++out:
++	kfree(info);
++	return err;
++}
++
++/**
++ * amdgpu_atif_get_notification_params - determine notify configuration
++ *
++ * @handle: acpi handle
++ * @n: atif notification configuration struct
++ *
++ * Execute the ATIF_FUNCTION_GET_SYSTEM_PARAMETERS ATIF function
++ * to determine if a notifier is used and if so which one
++ * (all asics).  This is either Notify(VGA, 0x81) or Notify(VGA, n)
++ * where n is specified in the result if a notifier is used.
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atif_get_notification_params(acpi_handle handle,
++		struct amdgpu_atif_notification_cfg *n)
++{
++	union acpi_object *info;
++	struct atif_system_params params;
++	size_t size;
++	int err = 0;
++
++	info = amdgpu_atif_call(handle, ATIF_FUNCTION_GET_SYSTEM_PARAMETERS, NULL);
++	if (!info) {
++		err = -EIO;
++		goto out;
++	}
++
++	size = *(u16 *) info->buffer.pointer;
++	if (size < 10) {
++		err = -EINVAL;
++		goto out;
++	}
++
++	memset(&params, 0, sizeof(params));
++	size = min(sizeof(params), size);
++	memcpy(&params, info->buffer.pointer, size);
++
++	DRM_DEBUG_DRIVER("SYSTEM_PARAMS: mask = %#x, flags = %#x\n",
++			params.flags, params.valid_mask);
++	params.flags = params.flags & params.valid_mask;
++
++	if ((params.flags & ATIF_NOTIFY_MASK) == ATIF_NOTIFY_NONE) {
++		n->enabled = false;
++		n->command_code = 0;
++	} else if ((params.flags & ATIF_NOTIFY_MASK) == ATIF_NOTIFY_81) {
++		n->enabled = true;
++		n->command_code = 0x81;
++	} else {
++		if (size < 11) {
++			err = -EINVAL;
++			goto out;
++		}
++		n->enabled = true;
++		n->command_code = params.command_code;
++	}
++
++out:
++	DRM_DEBUG_DRIVER("Notification %s, command code = %#x\n",
++			(n->enabled ? "enabled" : "disabled"),
++			n->command_code);
++	kfree(info);
++	return err;
++}
++
++/**
++ * amdgpu_atif_get_sbios_requests - get requested sbios event
++ *
++ * @handle: acpi handle
++ * @req: atif sbios request struct
++ *
++ * Execute the ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS ATIF function
++ * to determine what requests the sbios is making to the driver
++ * (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atif_get_sbios_requests(acpi_handle handle,
++		struct atif_sbios_requests *req)
++{
++	union acpi_object *info;
++	size_t size;
++	int count = 0;
++
++	info = amdgpu_atif_call(handle, ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS, NULL);
++	if (!info)
++		return -EIO;
++
++	size = *(u16 *)info->buffer.pointer;
++	if (size < 0xd) {
++		count = -EINVAL;
++		goto out;
++	}
++	memset(req, 0, sizeof(*req));
++
++	size = min(sizeof(*req), size);
++	memcpy(req, info->buffer.pointer, size);
++	DRM_DEBUG_DRIVER("SBIOS pending requests: %#x\n", req->pending);
++
++	count = hweight32(req->pending);
++
++out:
++	kfree(info);
++	return count;
++}
++
++/**
++ * amdgpu_atif_handler - handle ATIF notify requests
++ *
++ * @adev: amdgpu_device pointer
++ * @event: atif sbios request struct
++ *
++ * Checks the acpi event and if it matches an atif event,
++ * handles it.
++ * Returns NOTIFY code
++ */
++int amdgpu_atif_handler(struct amdgpu_device *adev,
++			struct acpi_bus_event *event)
++{
++	struct amdgpu_atif *atif = &adev->atif;
++	struct atif_sbios_requests req;
++	acpi_handle handle;
++	int count;
++
++	DRM_DEBUG_DRIVER("event, device_class = %s, type = %#x\n",
++			event->device_class, event->type);
++
++	if (strcmp(event->device_class, ACPI_VIDEO_CLASS) != 0)
++		return NOTIFY_DONE;
++
++	if (!atif->notification_cfg.enabled ||
++	    event->type != atif->notification_cfg.command_code)
++		/* Not our event */
++		return NOTIFY_DONE;
++
++	/* Check pending SBIOS requests */
++	handle = ACPI_HANDLE(&adev->pdev->dev);
++	count = amdgpu_atif_get_sbios_requests(handle, &req);
++
++	if (count <= 0)
++		return NOTIFY_DONE;
++
++	DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count);
++
++	if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) {
++		struct amdgpu_encoder *enc = atif->encoder_for_bl;
++
++		if (enc) {
++			struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;
++
++			DRM_DEBUG_DRIVER("Changing brightness to %d\n",
++					req.backlight_level);
++
++			amdgpu_display_backlight_set_level(adev, enc, req.backlight_level);
++
++#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
++			backlight_force_update(dig->bl_dev,
++					       BACKLIGHT_UPDATE_HOTKEY);
++#endif
++		}
++	}
++	/* TODO: check other events */
++
++	/* We've handled the event, stop the notifier chain. The ACPI interface
++	 * overloads ACPI_VIDEO_NOTIFY_PROBE, we don't want to send that to
++	 * userspace if the event was generated only to signal a SBIOS
++	 * request.
++	 */
++	return NOTIFY_BAD;
++}
++
++/* Call the ATCS method
++ */
++/**
++ * amdgpu_atcs_call - call an ATCS method
++ *
++ * @handle: acpi handle
++ * @function: the ATCS function to execute
++ * @params: ATCS function params
++ *
++ * Executes the requested ATCS function (all asics).
++ * Returns a pointer to the acpi output buffer.
++ */
++static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function,
++					   struct acpi_buffer *params)
++{
++	acpi_status status;
++	union acpi_object atcs_arg_elements[2];
++	struct acpi_object_list atcs_arg;
++	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
++
++	atcs_arg.count = 2;
++	atcs_arg.pointer = &atcs_arg_elements[0];
++
++	atcs_arg_elements[0].type = ACPI_TYPE_INTEGER;
++	atcs_arg_elements[0].integer.value = function;
++
++	if (params) {
++		atcs_arg_elements[1].type = ACPI_TYPE_BUFFER;
++		atcs_arg_elements[1].buffer.length = params->length;
++		atcs_arg_elements[1].buffer.pointer = params->pointer;
++	} else {
++		/* We need a second fake parameter */
++		atcs_arg_elements[1].type = ACPI_TYPE_INTEGER;
++		atcs_arg_elements[1].integer.value = 0;
++	}
++
++	status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer);
++
++	/* Fail only if calling the method fails and ATIF is supported */
++	if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
++		DRM_DEBUG_DRIVER("failed to evaluate ATCS got %s\n",
++				 acpi_format_exception(status));
++		kfree(buffer.pointer);
++		return NULL;
++	}
++
++	return buffer.pointer;
++}
++
++/**
++ * amdgpu_atcs_parse_functions - parse supported functions
++ *
++ * @f: supported functions struct
++ * @mask: supported functions mask from ATCS
++ *
++ * Use the supported functions mask from ATCS function
++ * ATCS_FUNCTION_VERIFY_INTERFACE to determine what functions
++ * are supported (all asics).
++ */
++static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mask)
++{
++	f->get_ext_state = mask & ATCS_GET_EXTERNAL_STATE_SUPPORTED;
++	f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED;
++	f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED;
++	f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED;
++}
++
++/**
++ * amdgpu_atcs_verify_interface - verify ATCS
++ *
++ * @handle: acpi handle
++ * @atcs: amdgpu atcs struct
++ *
++ * Execute the ATCS_FUNCTION_VERIFY_INTERFACE ATCS function
++ * to initialize ATCS and determine what features are supported
++ * (all asics).
++ * returns 0 on success, error on failure.
++ */
++static int amdgpu_atcs_verify_interface(acpi_handle handle,
++					struct amdgpu_atcs *atcs)
++{
++	union acpi_object *info;
++	struct atcs_verify_interface output;
++	size_t size;
++	int err = 0;
++
++	info = amdgpu_atcs_call(handle, ATCS_FUNCTION_VERIFY_INTERFACE, NULL);
++	if (!info)
++		return -EIO;
++
++	memset(&output, 0, sizeof(output));
++
++	size = *(u16 *) info->buffer.pointer;
++	if (size < 8) {
++		DRM_INFO("ATCS buffer is too small: %zu\n", size);
++		err = -EINVAL;
++		goto out;
++	}
++	size = min(sizeof(output), size);
++
++	memcpy(&output, info->buffer.pointer, size);
++
++	/* TODO: check version? */
++	DRM_DEBUG_DRIVER("ATCS version %u\n", output.version);
++
++	amdgpu_atcs_parse_functions(&atcs->functions, output.function_bits);
++
++out:
++	kfree(info);
++	return err;
++}
++
++/**
++ * amdgpu_acpi_is_pcie_performance_request_supported
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Check if the ATCS pcie_perf_req and pcie_dev_rdy methods
++ * are supported (all asics).
++ * returns true if supported, false if not.
++ */
++bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev)
++{
++	struct amdgpu_atcs *atcs = &adev->atcs;
++
++	if (atcs->functions.pcie_perf_req && atcs->functions.pcie_dev_rdy)
++		return true;
++
++	return false;
++}
++
++/**
++ * amdgpu_acpi_pcie_notify_device_ready
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Executes the PCIE_DEVICE_READY_NOTIFICATION method
++ * (all asics).
++ * returns 0 on success, error on failure.
++ */
++int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev)
++{
++	acpi_handle handle;
++	union acpi_object *info;
++	struct amdgpu_atcs *atcs = &adev->atcs;
++
++	/* Get the device handle */
++	handle = ACPI_HANDLE(&adev->pdev->dev);
++	if (!handle)
++		return -EINVAL;
++
++	if (!atcs->functions.pcie_dev_rdy)
++		return -EINVAL;
++
++	info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL);
++	if (!info)
++		return -EIO;
++
++	kfree(info);
++
++	return 0;
++}
++
++/**
++ * amdgpu_acpi_pcie_performance_request
++ *
++ * @adev: amdgpu_device pointer
++ * @perf_req: requested perf level (pcie gen speed)
++ * @advertise: set advertise caps flag if set
++ *
++ * Executes the PCIE_PERFORMANCE_REQUEST method to
++ * change the pcie gen speed (all asics).
++ * returns 0 on success, error on failure.
++ */
++int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
++					 u8 perf_req, bool advertise)
++{
++	acpi_handle handle;
++	union acpi_object *info;
++	struct amdgpu_atcs *atcs = &adev->atcs;
++	struct atcs_pref_req_input atcs_input;
++	struct atcs_pref_req_output atcs_output;
++	struct acpi_buffer params;
++	size_t size;
++	u32 retry = 3;
++
++	/* Get the device handle */
++	handle = ACPI_HANDLE(&adev->pdev->dev);
++	if (!handle)
++		return -EINVAL;
++
++	if (!atcs->functions.pcie_perf_req)
++		return -EINVAL;
++
++	atcs_input.size = sizeof(struct atcs_pref_req_input);
++	/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
++	atcs_input.client_id = adev->pdev->devfn | (adev->pdev->bus->number << 8);
++	atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK;
++	atcs_input.flags = ATCS_WAIT_FOR_COMPLETION;
++	if (advertise)
++		atcs_input.flags |= ATCS_ADVERTISE_CAPS;
++	atcs_input.req_type = ATCS_PCIE_LINK_SPEED;
++	atcs_input.perf_req = perf_req;
++
++	params.length = sizeof(struct atcs_pref_req_input);
++	params.pointer = &atcs_input;
++
++	while (retry--) {
++		info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, &params);
++		if (!info)
++			return -EIO;
++
++		memset(&atcs_output, 0, sizeof(atcs_output));
++
++		size = *(u16 *) info->buffer.pointer;
++		if (size < 3) {
++			DRM_INFO("ATCS buffer is too small: %zu\n", size);
++			kfree(info);
++			return -EINVAL;
++		}
++		size = min(sizeof(atcs_output), size);
++
++		memcpy(&atcs_output, info->buffer.pointer, size);
++
++		kfree(info);
++
++		switch (atcs_output.ret_val) {
++		case ATCS_REQUEST_REFUSED:
++		default:
++			return -EINVAL;
++		case ATCS_REQUEST_COMPLETE:
++			return 0;
++		case ATCS_REQUEST_IN_PROGRESS:
++			udelay(10);
++			break;
++		}
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_acpi_event - handle notify events
++ *
++ * @nb: notifier block
++ * @val: val
++ * @data: acpi event
++ *
++ * Calls relevant amdgpu functions in response to various
++ * acpi events.
++ * Returns NOTIFY code
++ */
++static int amdgpu_acpi_event(struct notifier_block *nb,
++			     unsigned long val,
++			     void *data)
++{
++	struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, acpi_nb);
++	struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
++
++	if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
++		if (power_supply_is_system_supplied() > 0)
++			DRM_DEBUG_DRIVER("pm: AC\n");
++		else
++			DRM_DEBUG_DRIVER("pm: DC\n");
++
++		amdgpu_pm_acpi_event_handler(adev);
++	}
++
++	/* Check for pending SBIOS requests */
++	return amdgpu_atif_handler(adev, entry);
++}
++
++/* Call all ACPI methods here */
++/**
++ * amdgpu_acpi_init - init driver acpi support
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Verifies the AMD ACPI interfaces and registers with the acpi
++ * notifier chain (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_acpi_init(struct amdgpu_device *adev)
++{
++	acpi_handle handle;
++	struct amdgpu_atif *atif = &adev->atif;
++	struct amdgpu_atcs *atcs = &adev->atcs;
++	int ret;
++
++	/* Get the device handle */
++	handle = ACPI_HANDLE(&adev->pdev->dev);
++
++	if (!adev->bios || !handle)
++		return 0;
++
++	/* Call the ATCS method */
++	ret = amdgpu_atcs_verify_interface(handle, atcs);
++	if (ret) {
++		DRM_DEBUG_DRIVER("Call to ATCS verify_interface failed: %d\n", ret);
++	}
++
++	/* Call the ATIF method */
++	ret = amdgpu_atif_verify_interface(handle, atif);
++	if (ret) {
++		DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret);
++		goto out;
++	}
++
++	if (atif->notifications.brightness_change) {
++		struct drm_encoder *tmp;
++
++		/* Find the encoder controlling the brightness */
++		list_for_each_entry(tmp, &adev->ddev->mode_config.encoder_list,
++				head) {
++			struct amdgpu_encoder *enc = to_amdgpu_encoder(tmp);
++
++			if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
++			    enc->enc_priv) {
++				if (adev->is_atom_bios) {
++					struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;
++					if (dig->bl_dev) {
++						atif->encoder_for_bl = enc;
++						break;
++					}
++				}
++			}
++		}
++	}
++
++	if (atif->functions.sbios_requests && !atif->functions.system_params) {
++		/* XXX check this workraround, if sbios request function is
++		 * present we have to see how it's configured in the system
++		 * params
++		 */
++		atif->functions.system_params = true;
++	}
++
++	if (atif->functions.system_params) {
++		ret = amdgpu_atif_get_notification_params(handle,
++				&atif->notification_cfg);
++		if (ret) {
++			DRM_DEBUG_DRIVER("Call to GET_SYSTEM_PARAMS failed: %d\n",
++					ret);
++			/* Disable notification */
++			atif->notification_cfg.enabled = false;
++		}
++	}
++
++out:
++	adev->acpi_nb.notifier_call = amdgpu_acpi_event;
++	register_acpi_notifier(&adev->acpi_nb);
++
++	return ret;
++}
++
++/**
++ * amdgpu_acpi_fini - tear down driver acpi support
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Unregisters with the acpi notifier chain (all asics).
++ */
++void amdgpu_acpi_fini(struct amdgpu_device *adev)
++{
++	unregister_acpi_notifier(&adev->acpi_nb);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
+new file mode 100644
+index 0000000..01a29c3
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
+@@ -0,0 +1,445 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef AMDGPU_ACPI_H
++#define AMDGPU_ACPI_H
++
++struct amdgpu_device;
++struct acpi_bus_event;
++
++int amdgpu_atif_handler(struct amdgpu_device *adev,
++		struct acpi_bus_event *event);
++
++/* AMD hw uses four ACPI control methods:
++ * 1. ATIF
++ * ARG0: (ACPI_INTEGER) function code
++ * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
++ * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
++ * ATIF provides an entry point for the gfx driver to interact with the sbios.
++ * The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom
++ * notification. Which notification is used as indicated by the ATIF Control
++ * Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or
++ * a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS
++ * to identify pending System BIOS requests and associated parameters. For
++ * example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver
++ * will perform display device detection and invoke ATIF Control Method
++ * SELECT_ACTIVE_DISPLAYS.
++ *
++ * 2. ATPX
++ * ARG0: (ACPI_INTEGER) function code
++ * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
++ * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
++ * ATPX methods are used on PowerXpress systems to handle mux switching and
++ * discrete GPU power control.
++ *
++ * 3. ATRM
++ * ARG0: (ACPI_INTEGER) offset of vbios rom data
++ * ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K).
++ * OUTPUT: (ACPI_BUFFER) output buffer
++ * ATRM provides an interfacess to access the discrete GPU vbios image on
++ * PowerXpress systems with multiple GPUs.
++ *
++ * 4. ATCS
++ * ARG0: (ACPI_INTEGER) function code
++ * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
++ * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
++ * ATCS provides an interface to AMD chipset specific functionality.
++ *
++ */
++/* ATIF */
++#define ATIF_FUNCTION_VERIFY_INTERFACE                             0x0
++/* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - version
++ * DWORD - supported notifications mask
++ * DWORD - supported functions bit vector
++ */
++/* Notifications mask */
++#       define ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED               (1 << 0)
++#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED        (1 << 1)
++#       define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED         (1 << 2)
++#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED    (1 << 3)
++#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED   (1 << 4)
++#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED          (1 << 5)
++#       define ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED                (1 << 6)
++#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED      (1 << 7)
++#       define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED                   (1 << 8)
++/* supported functions vector */
++#       define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED               (1 << 0)
++#       define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED            (1 << 1)
++#       define ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED              (1 << 2)
++#       define ATIF_GET_LID_STATE_SUPPORTED                       (1 << 3)
++#       define ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED           (1 << 4)
++#       define ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED             (1 << 5)
++#       define ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED  (1 << 6)
++#       define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED    (1 << 7)
++#       define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED     (1 << 12)
++#       define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED           (1 << 14)
++#define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS                        0x1
++/* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * DWORD - valid flags mask
++ * DWORD - flags
++ *
++ * OR
++ *
++ * WORD  - structure size in bytes (includes size field)
++ * DWORD - valid flags mask
++ * DWORD - flags
++ * BYTE  - notify command code
++ *
++ * flags
++ * bits 1:0:
++ * 0 - Notify(VGA, 0x81) is not used for notification
++ * 1 - Notify(VGA, 0x81) is used for notification
++ * 2 - Notify(VGA, n) is used for notification where
++ * n (0xd0-0xd9) is specified in notify command code.
++ * bit 2:
++ * 1 - lid changes not reported though int10
++ */
++#define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS                     0x2
++/* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * DWORD - pending sbios requests
++ * BYTE  - panel expansion mode
++ * BYTE  - thermal state: target gfx controller
++ * BYTE  - thermal state: state id (0: exit state, non-0: state)
++ * BYTE  - forced power state: target gfx controller
++ * BYTE  - forced power state: state id
++ * BYTE  - system power source
++ * BYTE  - panel backlight level (0-255)
++ */
++/* pending sbios requests */
++#       define ATIF_DISPLAY_SWITCH_REQUEST                         (1 << 0)
++#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST                  (1 << 1)
++#       define ATIF_THERMAL_STATE_CHANGE_REQUEST                   (1 << 2)
++#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST              (1 << 3)
++#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST             (1 << 4)
++#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST                    (1 << 5)
++#       define ATIF_PX_GFX_SWITCH_REQUEST                          (1 << 6)
++#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST                (1 << 7)
++#       define ATIF_DGPU_DISPLAY_EVENT                             (1 << 8)
++/* panel expansion mode */
++#       define ATIF_PANEL_EXPANSION_DISABLE                        0
++#       define ATIF_PANEL_EXPANSION_FULL                           1
++#       define ATIF_PANEL_EXPANSION_ASPECT                         2
++/* target gfx controller */
++#       define ATIF_TARGET_GFX_SINGLE                              0
++#       define ATIF_TARGET_GFX_PX_IGPU                             1
++#       define ATIF_TARGET_GFX_PX_DGPU                             2
++/* system power source */
++#       define ATIF_POWER_SOURCE_AC                                1
++#       define ATIF_POWER_SOURCE_DC                                2
++#       define ATIF_POWER_SOURCE_RESTRICTED_AC_1                   3
++#       define ATIF_POWER_SOURCE_RESTRICTED_AC_2                   4
++#define ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS                       0x3
++/* ARG0: ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - selected displays
++ * WORD  - connected displays
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - selected displays
++ */
++#       define ATIF_LCD1                                           (1 << 0)
++#       define ATIF_CRT1                                           (1 << 1)
++#       define ATIF_TV                                             (1 << 2)
++#       define ATIF_DFP1                                           (1 << 3)
++#       define ATIF_CRT2                                           (1 << 4)
++#       define ATIF_LCD2                                           (1 << 5)
++#       define ATIF_DFP2                                           (1 << 7)
++#       define ATIF_CV                                             (1 << 8)
++#       define ATIF_DFP3                                           (1 << 9)
++#       define ATIF_DFP4                                           (1 << 10)
++#       define ATIF_DFP5                                           (1 << 11)
++#       define ATIF_DFP6                                           (1 << 12)
++#define ATIF_FUNCTION_GET_LID_STATE                                0x4
++/* ARG0: ATIF_FUNCTION_GET_LID_STATE
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - lid state (0: open, 1: closed)
++ *
++ * GET_LID_STATE only works at boot and resume, for general lid
++ * status, use the kernel provided status
++ */
++#define ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS                    0x5
++/* ARG0: ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - 0
++ * BYTE  - TV standard
++ */
++#       define ATIF_TV_STD_NTSC                                    0
++#       define ATIF_TV_STD_PAL                                     1
++#       define ATIF_TV_STD_PALM                                    2
++#       define ATIF_TV_STD_PAL60                                   3
++#       define ATIF_TV_STD_NTSCJ                                   4
++#       define ATIF_TV_STD_PALCN                                   5
++#       define ATIF_TV_STD_PALN                                    6
++#       define ATIF_TV_STD_SCART_RGB                               9
++#define ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS                      0x6
++/* ARG0: ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - 0
++ * BYTE  - TV standard
++ * OUTPUT: none
++ */
++#define ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS           0x7
++/* ARG0: ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - panel expansion mode
++ */
++#define ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS             0x8
++/* ARG0: ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - panel expansion mode
++ * OUTPUT: none
++ */
++#define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION              0xD
++/* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - gfx controller id
++ * BYTE  - current temperature (degress Celsius)
++ * OUTPUT: none
++ */
++#define ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES                    0xF
++/* ARG0: ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - number of gfx devices
++ * WORD  - device structure size in bytes (excludes device size field)
++ * DWORD - flags         \
++ * WORD  - bus number     } repeated structure
++ * WORD  - device number /
++ */
++/* flags */
++#       define ATIF_PX_REMOVABLE_GRAPHICS_DEVICE                   (1 << 0)
++#       define ATIF_XGP_PORT                                       (1 << 1)
++#       define ATIF_VGA_ENABLED_GRAPHICS_DEVICE                    (1 << 2)
++#       define ATIF_XGP_PORT_IN_DOCK                               (1 << 3)
++
++/* ATPX */
++#define ATPX_FUNCTION_VERIFY_INTERFACE                             0x0
++/* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - version
++ * DWORD - supported functions bit vector
++ */
++/* supported functions vector */
++#       define ATPX_GET_PX_PARAMETERS_SUPPORTED                    (1 << 0)
++#       define ATPX_POWER_CONTROL_SUPPORTED                        (1 << 1)
++#       define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED                  (1 << 2)
++#       define ATPX_I2C_MUX_CONTROL_SUPPORTED                      (1 << 3)
++#       define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4)
++#       define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED   (1 << 5)
++#       define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED       (1 << 7)
++#       define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED          (1 << 8)
++#define ATPX_FUNCTION_GET_PX_PARAMETERS                            0x1
++/* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * DWORD - valid flags mask
++ * DWORD - flags
++ */
++/* flags */
++#       define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 0)
++#       define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 1)
++#       define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 2)
++#       define ATPX_CRT1_RGB_SIGNAL_MUXED                          (1 << 3)
++#       define ATPX_TV_SIGNAL_MUXED                                (1 << 4)
++#       define ATPX_DFP_SIGNAL_MUXED                               (1 << 5)
++#       define ATPX_SEPARATE_MUX_FOR_I2C                           (1 << 6)
++#       define ATPX_DYNAMIC_PX_SUPPORTED                           (1 << 7)
++#       define ATPX_ACF_NOT_SUPPORTED                              (1 << 8)
++#       define ATPX_FIXED_NOT_SUPPORTED                            (1 << 9)
++#       define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED               (1 << 10)
++#       define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS                    (1 << 11)
++#define ATPX_FUNCTION_POWER_CONTROL                                0x2
++/* ARG0: ATPX_FUNCTION_POWER_CONTROL
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - dGPU power state (0: power off, 1: power on)
++ * OUTPUT: none
++ */
++#define ATPX_FUNCTION_DISPLAY_MUX_CONTROL                          0x3
++/* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - display mux control (0: iGPU, 1: dGPU)
++ * OUTPUT: none
++ */
++#       define ATPX_INTEGRATED_GPU                                 0
++#       define ATPX_DISCRETE_GPU                                   1
++#define ATPX_FUNCTION_I2C_MUX_CONTROL                              0x4
++/* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - i2c/aux/hpd mux control (0: iGPU, 1: dGPU)
++ * OUTPUT: none
++ */
++#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION    0x5
++/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - target gpu (0: iGPU, 1: dGPU)
++ * OUTPUT: none
++ */
++#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION      0x6
++/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - target gpu (0: iGPU, 1: dGPU)
++ * OUTPUT: none
++ */
++#define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING               0x8
++/* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - number of display connectors
++ * WORD  - connector structure size in bytes (excludes connector size field)
++ * BYTE  - flags                                                     \
++ * BYTE  - ATIF display vector bit position                           } repeated
++ * BYTE  - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure
++ * WORD  - connector ACPI id                                         /
++ */
++/* flags */
++#       define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE  (1 << 0)
++#       define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 1)
++#       define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 2)
++#define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS                  0x9
++/* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - number of HPD/DDC ports
++ * WORD  - port structure size in bytes (excludes port size field)
++ * BYTE  - ATIF display vector bit position \
++ * BYTE  - hpd id                            } reapeated structure
++ * BYTE  - ddc id                           /
++ *
++ * available on A+A systems only
++ */
++/* hpd id */
++#       define ATPX_HPD_NONE                                       0
++#       define ATPX_HPD1                                           1
++#       define ATPX_HPD2                                           2
++#       define ATPX_HPD3                                           3
++#       define ATPX_HPD4                                           4
++#       define ATPX_HPD5                                           5
++#       define ATPX_HPD6                                           6
++/* ddc id */
++#       define ATPX_DDC_NONE                                       0
++#       define ATPX_DDC1                                           1
++#       define ATPX_DDC2                                           2
++#       define ATPX_DDC3                                           3
++#       define ATPX_DDC4                                           4
++#       define ATPX_DDC5                                           5
++#       define ATPX_DDC6                                           6
++#       define ATPX_DDC7                                           7
++#       define ATPX_DDC8                                           8
++
++/* ATCS */
++#define ATCS_FUNCTION_VERIFY_INTERFACE                             0x0
++/* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - version
++ * DWORD - supported functions bit vector
++ */
++/* supported functions vector */
++#       define ATCS_GET_EXTERNAL_STATE_SUPPORTED                   (1 << 0)
++#       define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED             (1 << 1)
++#       define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED       (1 << 2)
++#       define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED                   (1 << 3)
++#define ATCS_FUNCTION_GET_EXTERNAL_STATE                           0x1
++/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
++ * ARG1: none
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * DWORD - valid flags mask
++ * DWORD - flags (0: undocked, 1: docked)
++ */
++/* flags */
++#       define ATCS_DOCKED                                         (1 << 0)
++#define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST                     0x2
++/* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
++ * WORD  - valid flags mask
++ * WORD  - flags
++ * BYTE  - request type
++ * BYTE  - performance request
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - return value
++ */
++/* flags */
++#       define ATCS_ADVERTISE_CAPS                                 (1 << 0)
++#       define ATCS_WAIT_FOR_COMPLETION                            (1 << 1)
++/* request type */
++#       define ATCS_PCIE_LINK_SPEED                                1
++/* performance request */
++#       define ATCS_REMOVE                                         0
++#       define ATCS_FORCE_LOW_POWER                                1
++#       define ATCS_PERF_LEVEL_1                                   2 /* PCIE Gen 1 */
++#       define ATCS_PERF_LEVEL_2                                   3 /* PCIE Gen 2 */
++#       define ATCS_PERF_LEVEL_3                                   4 /* PCIE Gen 3 */
++/* return value */
++#       define ATCS_REQUEST_REFUSED                                1
++#       define ATCS_REQUEST_COMPLETE                               2
++#       define ATCS_REQUEST_IN_PROGRESS                            3
++#define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION               0x3
++/* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION
++ * ARG1: none
++ * OUTPUT: none
++ */
++#define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH                           0x4
++/* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH
++ * ARG1:
++ * WORD  - structure size in bytes (includes size field)
++ * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
++ * BYTE  - number of active lanes
++ * OUTPUT:
++ * WORD  - structure size in bytes (includes size field)
++ * BYTE  - number of active lanes
++ */
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
+new file mode 100644
+index 0000000..857ba08
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Christian König.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Christian König
++ */
++#include <linux/hdmi.h>
++#include <linux/gcd.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++static const struct amdgpu_afmt_acr amdgpu_afmt_predefined_acr[] = {
++    /*	     32kHz	  44.1kHz	48kHz    */
++    /* Clock      N     CTS      N     CTS      N     CTS */
++    {  25175,  4096,  25175, 28224, 125875,  6144,  25175 }, /*  25,20/1.001 MHz */
++    {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
++    {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
++    {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
++    {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
++    {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
++    {  74176,  4096,  74176,  5733,  75335,  6144,  74176 }, /*  74.25/1.001 MHz */
++    {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
++    { 148352,  4096, 148352,  5733, 150670,  6144, 148352 }, /* 148.50/1.001 MHz */
++    { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
++};
++
++
++/*
++ * calculate CTS and N values if they are not found in the table
++ */
++static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
++{
++	int n, cts;
++	unsigned long div, mul;
++
++	/* Safe, but overly large values */
++	n = 128 * freq;
++	cts = clock * 1000;
++
++	/* Smallest valid fraction */
++	div = gcd(n, cts);
++
++	n /= div;
++	cts /= div;
++
++	/*
++	 * The optimal N is 128*freq/1000. Calculate the closest larger
++	 * value that doesn't truncate any bits.
++	 */
++	mul = ((128*freq/1000) + (n-1))/n;
++
++	n *= mul;
++	cts *= mul;
++
++	/* Check that we are in spec (not always possible) */
++	if (n < (128*freq/1500))
++		printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
++	if (n > (128*freq/300))
++		printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
++
++	*N = n;
++	*CTS = cts;
++
++	DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
++		  *N, *CTS, freq);
++}
++
++struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)
++{
++	struct amdgpu_afmt_acr res;
++	u8 i;
++
++	/* Precalculated values for common clocks */
++	for (i = 0; i < ARRAY_SIZE(amdgpu_afmt_predefined_acr); i++) {
++		if (amdgpu_afmt_predefined_acr[i].clock == clock)
++			return amdgpu_afmt_predefined_acr[i];
++	}
++
++	/* And odd clocks get manually calculated */
++	amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
++	amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
++	amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
++
++	return res;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+new file mode 100644
+index 0000000..6a58837
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -0,0 +1,1598 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_i2c.h"
++
++#include "atom.h"
++#include "atom-bits.h"
++#include "atombios_encoders.h"
++#include "bif/bif_4_1_d.h"
++
++static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
++					  ATOM_GPIO_I2C_ASSIGMENT *gpio,
++					  u8 index)
++{
++
++}
++
++static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
++{
++	struct amdgpu_i2c_bus_rec i2c;
++
++	memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
++
++	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
++	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
++	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
++	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
++	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
++	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
++	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
++	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
++	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
++	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
++	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
++	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
++	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
++	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
++	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
++	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
++
++	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
++		i2c.hw_capable = true;
++	else
++		i2c.hw_capable = false;
++
++	if (gpio->sucI2cId.ucAccess == 0xa0)
++		i2c.mm_i2c = true;
++	else
++		i2c.mm_i2c = false;
++
++	i2c.i2c_id = gpio->sucI2cId.ucAccess;
++
++	if (i2c.mask_clk_reg)
++		i2c.valid = true;
++	else
++		i2c.valid = false;
++
++	return i2c;
++}
++
++struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
++							  uint8_t id)
++{
++	struct atom_context *ctx = adev->mode_info.atom_context;
++	ATOM_GPIO_I2C_ASSIGMENT *gpio;
++	struct amdgpu_i2c_bus_rec i2c;
++	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
++	struct _ATOM_GPIO_I2C_INFO *i2c_info;
++	uint16_t data_offset, size;
++	int i, num_indices;
++
++	memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
++	i2c.valid = false;
++
++	if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
++		i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
++
++		num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
++			sizeof(ATOM_GPIO_I2C_ASSIGMENT);
++
++		gpio = &i2c_info->asGPIO_Info[0];
++		for (i = 0; i < num_indices; i++) {
++
++			amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
++
++			if (gpio->sucI2cId.ucAccess == id) {
++				i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
++				break;
++			}
++			gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
++				((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
++		}
++	}
++
++	return i2c;
++}
++
++void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
++{
++	struct atom_context *ctx = adev->mode_info.atom_context;
++	ATOM_GPIO_I2C_ASSIGMENT *gpio;
++	struct amdgpu_i2c_bus_rec i2c;
++	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
++	struct _ATOM_GPIO_I2C_INFO *i2c_info;
++	uint16_t data_offset, size;
++	int i, num_indices;
++	char stmp[32];
++
++	if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
++		i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
++
++		num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
++			sizeof(ATOM_GPIO_I2C_ASSIGMENT);
++
++		gpio = &i2c_info->asGPIO_Info[0];
++		for (i = 0; i < num_indices; i++) {
++			amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
++
++			i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
++
++			if (i2c.valid) {
++				sprintf(stmp, "0x%x", i2c.i2c_id);
++				adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
++			}
++			gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
++				((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
++		}
++	}
++}
++
++struct amdgpu_gpio_rec
++amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
++			    u8 id)
++{
++	struct atom_context *ctx = adev->mode_info.atom_context;
++	struct amdgpu_gpio_rec gpio;
++	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
++	struct _ATOM_GPIO_PIN_LUT *gpio_info;
++	ATOM_GPIO_PIN_ASSIGNMENT *pin;
++	u16 data_offset, size;
++	int i, num_indices;
++
++	memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
++	gpio.valid = false;
++
++	if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
++		gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
++
++		num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
++			sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
++
++		pin = gpio_info->asGPIO_Pin;
++		for (i = 0; i < num_indices; i++) {
++			if (id == pin->ucGPIO_ID) {
++				gpio.id = pin->ucGPIO_ID;
++				gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
++				gpio.shift = pin->ucGpioPinBitShift;
++				gpio.mask = (1 << pin->ucGpioPinBitShift);
++				gpio.valid = true;
++				break;
++			}
++			pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
++				((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
++		}
++	}
++
++	return gpio;
++}
++
++static struct amdgpu_hpd
++amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
++				       struct amdgpu_gpio_rec *gpio)
++{
++	struct amdgpu_hpd hpd;
++	u32 reg;
++
++	memset(&hpd, 0, sizeof(struct amdgpu_hpd));
++
++	reg = amdgpu_display_hpd_get_gpio_reg(adev);
++
++	hpd.gpio = *gpio;
++	if (gpio->reg == reg) {
++		switch(gpio->mask) {
++		case (1 << 0):
++			hpd.hpd = AMDGPU_HPD_1;
++			break;
++		case (1 << 8):
++			hpd.hpd = AMDGPU_HPD_2;
++			break;
++		case (1 << 16):
++			hpd.hpd = AMDGPU_HPD_3;
++			break;
++		case (1 << 24):
++			hpd.hpd = AMDGPU_HPD_4;
++			break;
++		case (1 << 26):
++			hpd.hpd = AMDGPU_HPD_5;
++			break;
++		case (1 << 28):
++			hpd.hpd = AMDGPU_HPD_6;
++			break;
++		default:
++			hpd.hpd = AMDGPU_HPD_NONE;
++			break;
++		}
++	} else
++		hpd.hpd = AMDGPU_HPD_NONE;
++	return hpd;
++}
++
++static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev,
++					 uint32_t supported_device,
++					 int *connector_type,
++					 struct amdgpu_i2c_bus_rec *i2c_bus,
++					 uint16_t *line_mux,
++					 struct amdgpu_hpd *hpd)
++{
++	return true;
++}
++
++static const int object_connector_convert[] = {
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_DVII,
++	DRM_MODE_CONNECTOR_DVII,
++	DRM_MODE_CONNECTOR_DVID,
++	DRM_MODE_CONNECTOR_DVID,
++	DRM_MODE_CONNECTOR_VGA,
++	DRM_MODE_CONNECTOR_Composite,
++	DRM_MODE_CONNECTOR_SVIDEO,
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_9PinDIN,
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_HDMIA,
++	DRM_MODE_CONNECTOR_HDMIB,
++	DRM_MODE_CONNECTOR_LVDS,
++	DRM_MODE_CONNECTOR_9PinDIN,
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_Unknown,
++	DRM_MODE_CONNECTOR_DisplayPort,
++	DRM_MODE_CONNECTOR_eDP,
++	DRM_MODE_CONNECTOR_Unknown
++};
++
++bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	struct atom_context *ctx = mode_info->atom_context;
++	int index = GetIndexIntoMasterTable(DATA, Object_Header);
++	u16 size, data_offset;
++	u8 frev, crev;
++	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
++	ATOM_ENCODER_OBJECT_TABLE *enc_obj;
++	ATOM_OBJECT_TABLE *router_obj;
++	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
++	ATOM_OBJECT_HEADER *obj_header;
++	int i, j, k, path_size, device_support;
++	int connector_type;
++	u16 conn_id, connector_object_id;
++	struct amdgpu_i2c_bus_rec ddc_bus;
++	struct amdgpu_router router;
++	struct amdgpu_gpio_rec gpio;
++	struct amdgpu_hpd hpd;
++
++	if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
++		return false;
++
++	if (crev < 2)
++		return false;
++
++	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
++	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
++	    (ctx->bios + data_offset +
++	     le16_to_cpu(obj_header->usDisplayPathTableOffset));
++	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
++	    (ctx->bios + data_offset +
++	     le16_to_cpu(obj_header->usConnectorObjectTableOffset));
++	enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
++	    (ctx->bios + data_offset +
++	     le16_to_cpu(obj_header->usEncoderObjectTableOffset));
++	router_obj = (ATOM_OBJECT_TABLE *)
++		(ctx->bios + data_offset +
++		 le16_to_cpu(obj_header->usRouterObjectTableOffset));
++	device_support = le16_to_cpu(obj_header->usDeviceSupport);
++
++	path_size = 0;
++	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
++		uint8_t *addr = (uint8_t *) path_obj->asDispPath;
++		ATOM_DISPLAY_OBJECT_PATH *path;
++		addr += path_size;
++		path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
++		path_size += le16_to_cpu(path->usSize);
++
++		if (device_support & le16_to_cpu(path->usDeviceTag)) {
++			uint8_t con_obj_id, con_obj_num, con_obj_type;
++
++			con_obj_id =
++			    (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
++			    >> OBJECT_ID_SHIFT;
++			con_obj_num =
++			    (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
++			    >> ENUM_ID_SHIFT;
++			con_obj_type =
++			    (le16_to_cpu(path->usConnObjectId) &
++			     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
++
++			connector_type =
++				object_connector_convert[con_obj_id];
++			connector_object_id = con_obj_id;
++
++			if (connector_type == DRM_MODE_CONNECTOR_Unknown)
++				continue;
++
++			router.ddc_valid = false;
++			router.cd_valid = false;
++			for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
++				uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
++
++				grph_obj_id =
++				    (le16_to_cpu(path->usGraphicObjIds[j]) &
++				     OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
++				grph_obj_num =
++				    (le16_to_cpu(path->usGraphicObjIds[j]) &
++				     ENUM_ID_MASK) >> ENUM_ID_SHIFT;
++				grph_obj_type =
++				    (le16_to_cpu(path->usGraphicObjIds[j]) &
++				     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
++
++				if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
++					for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
++						u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
++						if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
++							ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
++								(ctx->bios + data_offset +
++								 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
++							ATOM_ENCODER_CAP_RECORD *cap_record;
++							u16 caps = 0;
++
++							while (record->ucRecordSize > 0 &&
++							       record->ucRecordType > 0 &&
++							       record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
++								switch (record->ucRecordType) {
++								case ATOM_ENCODER_CAP_RECORD_TYPE:
++									cap_record =(ATOM_ENCODER_CAP_RECORD *)
++										record;
++									caps = le16_to_cpu(cap_record->usEncoderCap);
++									break;
++								}
++								record = (ATOM_COMMON_RECORD_HEADER *)
++									((char *)record + record->ucRecordSize);
++							}
++							amdgpu_display_add_encoder(adev, encoder_obj,
++										    le16_to_cpu(path->usDeviceTag),
++										    caps);
++						}
++					}
++				} else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
++					for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
++						u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
++						if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
++							ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
++								(ctx->bios + data_offset +
++								 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
++							ATOM_I2C_RECORD *i2c_record;
++							ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
++							ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
++							ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
++							ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
++								(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
++								(ctx->bios + data_offset +
++								 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
++							u8 *num_dst_objs = (u8 *)
++								((u8 *)router_src_dst_table + 1 +
++								 (router_src_dst_table->ucNumberOfSrc * 2));
++							u16 *dst_objs = (u16 *)(num_dst_objs + 1);
++							int enum_id;
++
++							router.router_id = router_obj_id;
++							for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
++								if (le16_to_cpu(path->usConnObjectId) ==
++								    le16_to_cpu(dst_objs[enum_id]))
++									break;
++							}
++
++							while (record->ucRecordSize > 0 &&
++							       record->ucRecordType > 0 &&
++							       record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
++								switch (record->ucRecordType) {
++								case ATOM_I2C_RECORD_TYPE:
++									i2c_record =
++										(ATOM_I2C_RECORD *)
++										record;
++									i2c_config =
++										(ATOM_I2C_ID_CONFIG_ACCESS *)
++										&i2c_record->sucI2cId;
++									router.i2c_info =
++										amdgpu_atombios_lookup_i2c_gpio(adev,
++												       i2c_config->
++												       ucAccess);
++									router.i2c_addr = i2c_record->ucI2CAddr >> 1;
++									break;
++								case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
++									ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
++										record;
++									router.ddc_valid = true;
++									router.ddc_mux_type = ddc_path->ucMuxType;
++									router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
++									router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
++									break;
++								case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
++									cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
++										record;
++									router.cd_valid = true;
++									router.cd_mux_type = cd_path->ucMuxType;
++									router.cd_mux_control_pin = cd_path->ucMuxControlPin;
++									router.cd_mux_state = cd_path->ucMuxState[enum_id];
++									break;
++								}
++								record = (ATOM_COMMON_RECORD_HEADER *)
++									((char *)record + record->ucRecordSize);
++							}
++						}
++					}
++				}
++			}
++
++			/* look up gpio for ddc, hpd */
++			ddc_bus.valid = false;
++			hpd.hpd = AMDGPU_HPD_NONE;
++			if ((le16_to_cpu(path->usDeviceTag) &
++			     (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
++				for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
++					if (le16_to_cpu(path->usConnObjectId) ==
++					    le16_to_cpu(con_obj->asObjects[j].
++							usObjectID)) {
++						ATOM_COMMON_RECORD_HEADER
++						    *record =
++						    (ATOM_COMMON_RECORD_HEADER
++						     *)
++						    (ctx->bios + data_offset +
++						     le16_to_cpu(con_obj->
++								 asObjects[j].
++								 usRecordOffset));
++						ATOM_I2C_RECORD *i2c_record;
++						ATOM_HPD_INT_RECORD *hpd_record;
++						ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
++
++						while (record->ucRecordSize > 0 &&
++						       record->ucRecordType > 0 &&
++						       record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
++							switch (record->ucRecordType) {
++							case ATOM_I2C_RECORD_TYPE:
++								i2c_record =
++								    (ATOM_I2C_RECORD *)
++									record;
++								i2c_config =
++									(ATOM_I2C_ID_CONFIG_ACCESS *)
++									&i2c_record->sucI2cId;
++								ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
++												 i2c_config->
++												 ucAccess);
++								break;
++							case ATOM_HPD_INT_RECORD_TYPE:
++								hpd_record =
++									(ATOM_HPD_INT_RECORD *)
++									record;
++								gpio = amdgpu_atombios_lookup_gpio(adev,
++											  hpd_record->ucHPDIntGPIOID);
++								hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
++								hpd.plugged_state = hpd_record->ucPlugged_PinState;
++								break;
++							}
++							record =
++							    (ATOM_COMMON_RECORD_HEADER
++							     *) ((char *)record
++								 +
++								 record->
++								 ucRecordSize);
++						}
++						break;
++					}
++				}
++			}
++
++			/* needed for aux chan transactions */
++			ddc_bus.hpd = hpd.hpd;
++
++			conn_id = le16_to_cpu(path->usConnObjectId);
++
++			if (!amdgpu_atombios_apply_quirks
++			    (adev, le16_to_cpu(path->usDeviceTag), &connector_type,
++			     &ddc_bus, &conn_id, &hpd))
++				continue;
++
++			amdgpu_display_add_connector(adev,
++						      conn_id,
++						      le16_to_cpu(path->usDeviceTag),
++						      connector_type, &ddc_bus,
++						      connector_object_id,
++						      &hpd,
++						      &router);
++
++		}
++	}
++
++	amdgpu_link_encoder_connector(adev->ddev);
++
++	return true;
++}
++
++union firmware_info {
++	ATOM_FIRMWARE_INFO info;
++	ATOM_FIRMWARE_INFO_V1_2 info_12;
++	ATOM_FIRMWARE_INFO_V1_3 info_13;
++	ATOM_FIRMWARE_INFO_V1_4 info_14;
++	ATOM_FIRMWARE_INFO_V2_1 info_21;
++	ATOM_FIRMWARE_INFO_V2_2 info_22;
++};
++
++int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
++	uint8_t frev, crev;
++	uint16_t data_offset;
++	int ret = -EINVAL;
++
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset)) {
++		int i;
++		struct amdgpu_pll *ppll = &adev->clock.ppll[0];
++		struct amdgpu_pll *spll = &adev->clock.spll;
++		struct amdgpu_pll *mpll = &adev->clock.mpll;
++		union firmware_info *firmware_info =
++			(union firmware_info *)(mode_info->atom_context->bios +
++						data_offset);
++		/* pixel clocks */
++		ppll->reference_freq =
++		    le16_to_cpu(firmware_info->info.usReferenceClock);
++		ppll->reference_div = 0;
++
++		if (crev < 2)
++			ppll->pll_out_min =
++				le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
++		else
++			ppll->pll_out_min =
++				le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
++		ppll->pll_out_max =
++		    le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
++
++		if (crev >= 4) {
++			ppll->lcd_pll_out_min =
++				le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
++			if (ppll->lcd_pll_out_min == 0)
++				ppll->lcd_pll_out_min = ppll->pll_out_min;
++			ppll->lcd_pll_out_max =
++				le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
++			if (ppll->lcd_pll_out_max == 0)
++				ppll->lcd_pll_out_max = ppll->pll_out_max;
++		} else {
++			ppll->lcd_pll_out_min = ppll->pll_out_min;
++			ppll->lcd_pll_out_max = ppll->pll_out_max;
++		}
++
++		if (ppll->pll_out_min == 0)
++			ppll->pll_out_min = 64800;
++
++		ppll->pll_in_min =
++		    le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
++		ppll->pll_in_max =
++		    le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
++
++		ppll->min_post_div = 2;
++		ppll->max_post_div = 0x7f;
++		ppll->min_frac_feedback_div = 0;
++		ppll->max_frac_feedback_div = 9;
++		ppll->min_ref_div = 2;
++		ppll->max_ref_div = 0x3ff;
++		ppll->min_feedback_div = 4;
++		ppll->max_feedback_div = 0xfff;
++		ppll->best_vco = 0;
++
++		for (i = 1; i < AMDGPU_MAX_PPLL; i++)
++			adev->clock.ppll[i] = *ppll;
++
++		/* system clock */
++		spll->reference_freq =
++			le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
++		spll->reference_div = 0;
++
++		spll->pll_out_min =
++		    le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
++		spll->pll_out_max =
++		    le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
++
++		/* ??? */
++		if (spll->pll_out_min == 0)
++			spll->pll_out_min = 64800;
++
++		spll->pll_in_min =
++		    le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
++		spll->pll_in_max =
++		    le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
++
++		spll->min_post_div = 1;
++		spll->max_post_div = 1;
++		spll->min_ref_div = 2;
++		spll->max_ref_div = 0xff;
++		spll->min_feedback_div = 4;
++		spll->max_feedback_div = 0xff;
++		spll->best_vco = 0;
++
++		/* memory clock */
++		mpll->reference_freq =
++			le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
++		mpll->reference_div = 0;
++
++		mpll->pll_out_min =
++		    le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
++		mpll->pll_out_max =
++		    le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
++
++		/* ??? */
++		if (mpll->pll_out_min == 0)
++			mpll->pll_out_min = 64800;
++
++		mpll->pll_in_min =
++		    le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
++		mpll->pll_in_max =
++		    le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
++
++		adev->clock.default_sclk =
++		    le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
++		adev->clock.default_mclk =
++		    le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
++
++		mpll->min_post_div = 1;
++		mpll->max_post_div = 1;
++		mpll->min_ref_div = 2;
++		mpll->max_ref_div = 0xff;
++		mpll->min_feedback_div = 4;
++		mpll->max_feedback_div = 0xff;
++		mpll->best_vco = 0;
++
++		/* disp clock */
++		adev->clock.default_dispclk =
++			le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
++		if (adev->clock.default_dispclk == 0)
++			adev->clock.default_dispclk = 54000; /* 540 Mhz */
++		adev->clock.dp_extclk =
++			le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
++		adev->clock.current_dispclk = adev->clock.default_dispclk;
++
++		adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
++		if (adev->clock.max_pixel_clock == 0)
++			adev->clock.max_pixel_clock = 40000;
++
++		/* not technically a clock, but... */
++		adev->mode_info.firmware_flags =
++			le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
++
++		ret = 0;
++	}
++
++	adev->pm.current_sclk = adev->clock.default_sclk;
++	adev->pm.current_mclk = adev->clock.default_mclk;
++
++	return ret;
++}
++
++union igp_info {
++	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
++};
++
++static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
++						 struct amdgpu_atom_ss *ss,
++						 int id)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
++	u16 data_offset, size;
++	union igp_info *igp_info;
++	u8 frev, crev;
++	u16 percentage = 0, rate = 0;
++
++	/* get any igp specific overrides */
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
++				   &frev, &crev, &data_offset)) {
++		igp_info = (union igp_info *)
++			(mode_info->atom_context->bios + data_offset);
++		switch (crev) {
++		case 6:
++			switch (id) {
++			case ASIC_INTERNAL_SS_ON_TMDS:
++				percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
++				rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_HDMI:
++				percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
++				rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_LVDS:
++				percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
++				rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
++				break;
++			}
++			break;
++		case 7:
++			switch (id) {
++			case ASIC_INTERNAL_SS_ON_TMDS:
++				percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
++				rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_HDMI:
++				percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
++				rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_LVDS:
++				percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
++				rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
++				break;
++			}
++			break;
++		case 8:
++			switch (id) {
++			case ASIC_INTERNAL_SS_ON_TMDS:
++				percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
++				rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_HDMI:
++				percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
++				rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_LVDS:
++				percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
++				rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
++				break;
++			}
++			break;
++		case 9:
++			switch (id) {
++			case ASIC_INTERNAL_SS_ON_TMDS:
++				percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
++				rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_HDMI:
++				percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
++				rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
++				break;
++			case ASIC_INTERNAL_SS_ON_LVDS:
++				percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
++				rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
++				break;
++			}
++			break;
++		default:
++			DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
++			break;
++		}
++		if (percentage)
++			ss->percentage = percentage;
++		if (rate)
++			ss->rate = rate;
++	}
++}
++
++union asic_ss_info {
++	struct _ATOM_ASIC_INTERNAL_SS_INFO info;
++	struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
++	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
++};
++
++union asic_ss_assignment {
++	struct _ATOM_ASIC_SS_ASSIGNMENT v1;
++	struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
++	struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
++};
++
++bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
++				      struct amdgpu_atom_ss *ss,
++				      int id, u32 clock)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
++	uint16_t data_offset, size;
++	union asic_ss_info *ss_info;
++	union asic_ss_assignment *ss_assign;
++	uint8_t frev, crev;
++	int i, num_indices;
++
++	if (id == ASIC_INTERNAL_MEMORY_SS) {
++		if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
++			return false;
++	}
++	if (id == ASIC_INTERNAL_ENGINE_SS) {
++		if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
++			return false;
++	}
++
++	memset(ss, 0, sizeof(struct amdgpu_atom_ss));
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
++				   &frev, &crev, &data_offset)) {
++
++		ss_info =
++			(union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
++
++		switch (frev) {
++		case 1:
++			num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
++				sizeof(ATOM_ASIC_SS_ASSIGNMENT);
++
++			ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
++			for (i = 0; i < num_indices; i++) {
++				if ((ss_assign->v1.ucClockIndication == id) &&
++				    (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
++					ss->percentage =
++						le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
++					ss->type = ss_assign->v1.ucSpreadSpectrumMode;
++					ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
++					ss->percentage_divider = 100;
++					return true;
++				}
++				ss_assign = (union asic_ss_assignment *)
++					((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
++			}
++			break;
++		case 2:
++			num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
++				sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
++			ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
++			for (i = 0; i < num_indices; i++) {
++				if ((ss_assign->v2.ucClockIndication == id) &&
++				    (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
++					ss->percentage =
++						le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
++					ss->type = ss_assign->v2.ucSpreadSpectrumMode;
++					ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
++					ss->percentage_divider = 100;
++					if ((crev == 2) &&
++					    ((id == ASIC_INTERNAL_ENGINE_SS) ||
++					     (id == ASIC_INTERNAL_MEMORY_SS)))
++						ss->rate /= 100;
++					return true;
++				}
++				ss_assign = (union asic_ss_assignment *)
++					((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
++			}
++			break;
++		case 3:
++			num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
++				sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
++			ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
++			for (i = 0; i < num_indices; i++) {
++				if ((ss_assign->v3.ucClockIndication == id) &&
++				    (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
++					ss->percentage =
++						le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
++					ss->type = ss_assign->v3.ucSpreadSpectrumMode;
++					ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
++					if (ss_assign->v3.ucSpreadSpectrumMode &
++					    SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
++						ss->percentage_divider = 1000;
++					else
++						ss->percentage_divider = 100;
++					if ((id == ASIC_INTERNAL_ENGINE_SS) ||
++					    (id == ASIC_INTERNAL_MEMORY_SS))
++						ss->rate /= 100;
++					if (adev->flags & AMDGPU_IS_APU)
++						amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
++					return true;
++				}
++				ss_assign = (union asic_ss_assignment *)
++					((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
++			}
++			break;
++		default:
++			DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
++			break;
++		}
++
++	}
++	return false;
++}
++
++union get_clock_dividers {
++	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
++	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
++	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
++	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
++	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
++	struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
++	struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
++};
++
++int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
++				       u8 clock_type,
++				       u32 clock,
++				       bool strobe_mode,
++				       struct atom_clock_dividers *dividers)
++{
++	union get_clock_dividers args;
++	int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
++	u8 frev, crev;
++
++	memset(&args, 0, sizeof(args));
++	memset(dividers, 0, sizeof(struct atom_clock_dividers));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return -EINVAL;
++
++	switch (crev) {
++	case 4:
++		/* fusion */
++		args.v4.ulClock = cpu_to_le32(clock);	/* 10 khz */
++
++		amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++		dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
++		dividers->real_clock = le32_to_cpu(args.v4.ulClock);
++		break;
++	case 6:
++		/* CI */
++		/* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
++		args.v6_in.ulClock.ulComputeClockFlag = clock_type;
++		args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);	/* 10 khz */
++
++		amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++		dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
++		dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
++		dividers->ref_div = args.v6_out.ucPllRefDiv;
++		dividers->post_div = args.v6_out.ucPllPostDiv;
++		dividers->flags = args.v6_out.ucPllCntlFlag;
++		dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
++		dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
++		break;
++	default:
++		return -EINVAL;
++	}
++	return 0;
++}
++
++int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
++					    u32 clock,
++					    bool strobe_mode,
++					    struct atom_mpll_param *mpll_param)
++{
++	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
++	int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
++	u8 frev, crev;
++
++	memset(&args, 0, sizeof(args));
++	memset(mpll_param, 0, sizeof(struct atom_mpll_param));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return -EINVAL;
++
++	switch (frev) {
++	case 2:
++		switch (crev) {
++		case 1:
++			/* SI */
++			args.ulClock = cpu_to_le32(clock);	/* 10 khz */
++			args.ucInputFlag = 0;
++			if (strobe_mode)
++				args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
++
++			amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++			mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
++			mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
++			mpll_param->post_div = args.ucPostDiv;
++			mpll_param->dll_speed = args.ucDllSpeed;
++			mpll_param->bwcntl = args.ucBWCntl;
++			mpll_param->vco_mode =
++				(args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
++			mpll_param->yclk_sel =
++				(args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
++			mpll_param->qdr =
++				(args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
++			mpll_param->half_rate =
++				(args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
++			break;
++		default:
++			return -EINVAL;
++		}
++		break;
++	default:
++		return -EINVAL;
++	}
++	return 0;
++}
++
++uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
++{
++	GET_ENGINE_CLOCK_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++	return le32_to_cpu(args.ulReturnEngineClock);
++}
++
++uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
++{
++	GET_MEMORY_CLOCK_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++	return le32_to_cpu(args.ulReturnMemoryClock);
++}
++
++void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
++				      uint32_t eng_clock)
++{
++	SET_ENGINE_CLOCK_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
++
++	args.ulTargetEngineClock = cpu_to_le32(eng_clock);	/* 10 khz */
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
++				      uint32_t mem_clock)
++{
++	SET_MEMORY_CLOCK_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
++
++	if (adev->flags & AMDGPU_IS_APU)
++		return;
++
++	args.ulTargetMemoryClock = cpu_to_le32(mem_clock);	/* 10 khz */
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
++					     u32 eng_clock, u32 mem_clock)
++{
++	SET_ENGINE_CLOCK_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
++	u32 tmp;
++
++	memset(&args, 0, sizeof(args));
++
++	tmp = eng_clock & SET_CLOCK_FREQ_MASK;
++	tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
++
++	args.ulTargetEngineClock = cpu_to_le32(tmp);
++	if (mem_clock)
++		args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++union set_voltage {
++	struct _SET_VOLTAGE_PS_ALLOCATION alloc;
++	struct _SET_VOLTAGE_PARAMETERS v1;
++	struct _SET_VOLTAGE_PARAMETERS_V2 v2;
++	struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
++};
++
++void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
++				 u16 voltage_level,
++				 u8 voltage_type)
++{
++	union set_voltage args;
++	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
++	u8 frev, crev, volt_index = voltage_level;
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return;
++
++	/* 0xff01 is a flag rather then an actual voltage */
++	if (voltage_level == 0xff01)
++		return;
++
++	switch (crev) {
++	case 1:
++		args.v1.ucVoltageType = voltage_type;
++		args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
++		args.v1.ucVoltageIndex = volt_index;
++		break;
++	case 2:
++		args.v2.ucVoltageType = voltage_type;
++		args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
++		args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
++		break;
++	case 3:
++		args.v3.ucVoltageType = voltage_type;
++		args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
++		args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++		return;
++	}
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
++					      u16 *leakage_id)
++{
++	union set_voltage args;
++	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
++	u8 frev, crev;
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return -EINVAL;
++
++	switch (crev) {
++	case 3:
++	case 4:
++		args.v3.ucVoltageType = 0;
++		args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
++		args.v3.usVoltageLevel = 0;
++
++		amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++		*leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
++							     u16 *vddc, u16 *vddci,
++							     u16 virtual_voltage_id,
++							     u16 vbios_voltage_id)
++{
++	int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
++	u8 frev, crev;
++	u16 data_offset, size;
++	int i, j;
++	ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
++	u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
++
++	*vddc = 0;
++	*vddci = 0;
++
++	if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
++				    &frev, &crev, &data_offset))
++		return -EINVAL;
++
++	profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
++		(adev->mode_info.atom_context->bios + data_offset);
++
++	switch (frev) {
++	case 1:
++		return -EINVAL;
++	case 2:
++		switch (crev) {
++		case 1:
++			if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
++				return -EINVAL;
++			leakage_bin = (u16 *)
++				(adev->mode_info.atom_context->bios + data_offset +
++				 le16_to_cpu(profile->usLeakageBinArrayOffset));
++			vddc_id_buf = (u16 *)
++				(adev->mode_info.atom_context->bios + data_offset +
++				 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
++			vddc_buf = (u16 *)
++				(adev->mode_info.atom_context->bios + data_offset +
++				 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
++			vddci_id_buf = (u16 *)
++				(adev->mode_info.atom_context->bios + data_offset +
++				 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
++			vddci_buf = (u16 *)
++				(adev->mode_info.atom_context->bios + data_offset +
++				 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
++
++			if (profile->ucElbVDDC_Num > 0) {
++				for (i = 0; i < profile->ucElbVDDC_Num; i++) {
++					if (vddc_id_buf[i] == virtual_voltage_id) {
++						for (j = 0; j < profile->ucLeakageBinNum; j++) {
++							if (vbios_voltage_id <= leakage_bin[j]) {
++								*vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
++								break;
++							}
++						}
++						break;
++					}
++				}
++			}
++			if (profile->ucElbVDDCI_Num > 0) {
++				for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
++					if (vddci_id_buf[i] == virtual_voltage_id) {
++						for (j = 0; j < profile->ucLeakageBinNum; j++) {
++							if (vbios_voltage_id <= leakage_bin[j]) {
++								*vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
++								break;
++							}
++						}
++						break;
++					}
++				}
++			}
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++			return -EINVAL;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++union get_voltage_info {
++	struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
++	struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
++};
++
++int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
++				    u16 virtual_voltage_id,
++				    u16 *voltage)
++{
++	int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
++	u32 entry_id;
++	u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
++	union get_voltage_info args;
++
++	for (entry_id = 0; entry_id < count; entry_id++) {
++		if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
++		    virtual_voltage_id)
++			break;
++	}
++
++	if (entry_id >= count)
++		return -EINVAL;
++
++	args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
++	args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
++	args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
++	args.in.ulSCLKFreq =
++		cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++	*voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
++
++	return 0;
++}
++
++union voltage_object_info {
++	struct _ATOM_VOLTAGE_OBJECT_INFO v1;
++	struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
++	struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
++};
++
++union voltage_object {
++	struct _ATOM_VOLTAGE_OBJECT v1;
++	struct _ATOM_VOLTAGE_OBJECT_V2 v2;
++	union _ATOM_VOLTAGE_OBJECT_V3 v3;
++};
++
++
++static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
++									u8 voltage_type, u8 voltage_mode)
++{
++	u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
++	u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
++	u8 *start = (u8*)v3;
++
++	while (offset < size) {
++		ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
++		if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
++		    (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
++			return vo;
++		offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
++	}
++	return NULL;
++}
++
++bool
++amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
++				u8 voltage_type, u8 voltage_mode)
++{
++	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
++	u8 frev, crev;
++	u16 data_offset, size;
++	union voltage_object_info *voltage_info;
++
++	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
++				   &frev, &crev, &data_offset)) {
++		voltage_info = (union voltage_object_info *)
++			(adev->mode_info.atom_context->bios + data_offset);
++
++		switch (frev) {
++		case 3:
++			switch (crev) {
++			case 1:
++				if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
++								  voltage_type, voltage_mode))
++					return true;
++				break;
++			default:
++				DRM_ERROR("unknown voltage object table\n");
++				return false;
++			}
++			break;
++		default:
++			DRM_ERROR("unknown voltage object table\n");
++			return false;
++		}
++
++	}
++	return false;
++}
++
++int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
++				      u8 voltage_type, u8 voltage_mode,
++				      struct atom_voltage_table *voltage_table)
++{
++	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
++	u8 frev, crev;
++	u16 data_offset, size;
++	int i;
++	union voltage_object_info *voltage_info;
++	union voltage_object *voltage_object = NULL;
++
++	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
++				   &frev, &crev, &data_offset)) {
++		voltage_info = (union voltage_object_info *)
++			(adev->mode_info.atom_context->bios + data_offset);
++
++		switch (frev) {
++		case 3:
++			switch (crev) {
++			case 1:
++				voltage_object = (union voltage_object *)
++					amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
++								      voltage_type, voltage_mode);
++				if (voltage_object) {
++					ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
++						&voltage_object->v3.asGpioVoltageObj;
++					VOLTAGE_LUT_ENTRY_V2 *lut;
++					if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
++						return -EINVAL;
++					lut = &gpio->asVolGpioLut[0];
++					for (i = 0; i < gpio->ucGpioEntryNum; i++) {
++						voltage_table->entries[i].value =
++							le16_to_cpu(lut->usVoltageValue);
++						voltage_table->entries[i].smio_low =
++							le32_to_cpu(lut->ulVoltageId);
++						lut = (VOLTAGE_LUT_ENTRY_V2 *)
++							((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
++					}
++					voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
++					voltage_table->count = gpio->ucGpioEntryNum;
++					voltage_table->phase_delay = gpio->ucPhaseDelay;
++					return 0;
++				}
++				break;
++			default:
++				DRM_ERROR("unknown voltage object table\n");
++				return -EINVAL;
++			}
++			break;
++		default:
++			DRM_ERROR("unknown voltage object table\n");
++			return -EINVAL;
++		}
++	}
++	return -EINVAL;
++}
++
++union vram_info {
++	struct _ATOM_VRAM_INFO_V3 v1_3;
++	struct _ATOM_VRAM_INFO_V4 v1_4;
++	struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
++};
++
++#define MEM_ID_MASK           0xff000000
++#define MEM_ID_SHIFT          24
++#define CLOCK_RANGE_MASK      0x00ffffff
++#define CLOCK_RANGE_SHIFT     0
++#define LOW_NIBBLE_MASK       0xf
++#define DATA_EQU_PREV         0
++#define DATA_FROM_TABLE       4
++
++int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
++				      u8 module_index,
++				      struct atom_mc_reg_table *reg_table)
++{
++	int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
++	u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
++	u32 i = 0, j;
++	u16 data_offset, size;
++	union vram_info *vram_info;
++
++	memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
++
++	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
++				   &frev, &crev, &data_offset)) {
++		vram_info = (union vram_info *)
++			(adev->mode_info.atom_context->bios + data_offset);
++		switch (frev) {
++		case 1:
++			DRM_ERROR("old table version %d, %d\n", frev, crev);
++			return -EINVAL;
++		case 2:
++			switch (crev) {
++			case 1:
++				if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
++					ATOM_INIT_REG_BLOCK *reg_block =
++						(ATOM_INIT_REG_BLOCK *)
++						((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
++					ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
++						(ATOM_MEMORY_SETTING_DATA_BLOCK *)
++						((u8 *)reg_block + (2 * sizeof(u16)) +
++						 le16_to_cpu(reg_block->usRegIndexTblSize));
++					ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
++					num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
++							   sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
++					if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
++						return -EINVAL;
++					while (i < num_entries) {
++						if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
++							break;
++						reg_table->mc_reg_address[i].s1 =
++							(u16)(le16_to_cpu(format->usRegIndex));
++						reg_table->mc_reg_address[i].pre_reg_data =
++							(u8)(format->ucPreRegDataLength);
++						i++;
++						format = (ATOM_INIT_REG_INDEX_FORMAT *)
++							((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
++					}
++					reg_table->last = i;
++					while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
++					       (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
++						t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
++								>> MEM_ID_SHIFT);
++						if (module_index == t_mem_id) {
++							reg_table->mc_reg_table_entry[num_ranges].mclk_max =
++								(u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
++								      >> CLOCK_RANGE_SHIFT);
++							for (i = 0, j = 1; i < reg_table->last; i++) {
++								if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
++									reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
++										(u32)le32_to_cpu(*((u32 *)reg_data + j));
++									j++;
++								} else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
++									reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
++										reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
++								}
++							}
++							num_ranges++;
++						}
++						reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
++							((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
++					}
++					if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
++						return -EINVAL;
++					reg_table->num_entries = num_ranges;
++				} else
++					return -EINVAL;
++				break;
++			default:
++				DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++				return -EINVAL;
++			}
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++			return -EINVAL;
++		}
++		return 0;
++	}
++	return -EINVAL;
++}
++
++void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
++{
++	uint32_t bios_6_scratch;
++
++	bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
++
++	if (lock) {
++		bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
++		bios_6_scratch &= ~ATOM_S6_ACC_MODE;
++	} else {
++		bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
++		bios_6_scratch |= ATOM_S6_ACC_MODE;
++	}
++
++	WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
++}
++
++void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
++{
++	uint32_t bios_2_scratch, bios_6_scratch;
++
++	bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
++	bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
++
++	/* let the bios control the backlight */
++	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
++
++	/* tell the bios not to handle mode switching */
++	bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
++
++	/* clear the vbios dpms state */
++	bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
++
++	WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
++	WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
++}
++
++void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
++		adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
++}
++
++void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
++		WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
++}
++
++/* Atom needs data in little endian format
++ * so swap as appropriate when copying data to
++ * or from atom. Note that atom operates on
++ * dw units.
++ */
++void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
++{
++#ifdef __BIG_ENDIAN
++	u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
++	u32 *dst32, *src32;
++	int i;
++
++	memcpy(src_tmp, src, num_bytes);
++	src32 = (u32 *)src_tmp;
++	dst32 = (u32 *)dst_tmp;
++	if (to_le) {
++		for (i = 0; i < ((num_bytes + 3) / 4); i++)
++			dst32[i] = cpu_to_le32(src32[i]);
++		memcpy(dst, dst_tmp, num_bytes);
++	} else {
++		u8 dws = num_bytes & ~3;
++		for (i = 0; i < ((num_bytes + 3) / 4); i++)
++			dst32[i] = le32_to_cpu(src32[i]);
++		memcpy(dst, dst_tmp, dws);
++		if (num_bytes % 4) {
++			for (i = 0; i < (num_bytes % 4); i++)
++				dst[dws+i] = dst_tmp[dws+i];
++		}
++	}
++#else
++	memcpy(dst, src, num_bytes);
++#endif
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
+new file mode 100644
+index 0000000..0ebb959
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
+@@ -0,0 +1,206 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_ATOMBIOS_H__
++#define __AMDGPU_ATOMBIOS_H__
++
++struct atom_clock_dividers {
++	u32 post_div;
++	union {
++		struct {
++#ifdef __BIG_ENDIAN
++			u32 reserved : 6;
++			u32 whole_fb_div : 12;
++			u32 frac_fb_div : 14;
++#else
++			u32 frac_fb_div : 14;
++			u32 whole_fb_div : 12;
++			u32 reserved : 6;
++#endif
++		};
++		u32 fb_div;
++	};
++	u32 ref_div;
++	bool enable_post_div;
++	bool enable_dithen;
++	u32 vco_mode;
++	u32 real_clock;
++	/* added for CI */
++	u32 post_divider;
++	u32 flags;
++};
++
++struct atom_mpll_param {
++	union {
++		struct {
++#ifdef __BIG_ENDIAN
++			u32 reserved : 8;
++			u32 clkfrac : 12;
++			u32 clkf : 12;
++#else
++			u32 clkf : 12;
++			u32 clkfrac : 12;
++			u32 reserved : 8;
++#endif
++		};
++		u32 fb_div;
++	};
++	u32 post_div;
++	u32 bwcntl;
++	u32 dll_speed;
++	u32 vco_mode;
++	u32 yclk_sel;
++	u32 qdr;
++	u32 half_rate;
++};
++
++#define MEM_TYPE_GDDR5  0x50
++#define MEM_TYPE_GDDR4  0x40
++#define MEM_TYPE_GDDR3  0x30
++#define MEM_TYPE_DDR2   0x20
++#define MEM_TYPE_GDDR1  0x10
++#define MEM_TYPE_DDR3   0xb0
++#define MEM_TYPE_MASK   0xf0
++
++struct atom_memory_info {
++	u8 mem_vendor;
++	u8 mem_type;
++};
++
++#define MAX_AC_TIMING_ENTRIES 16
++
++struct atom_memory_clock_range_table
++{
++	u8 num_entries;
++	u8 rsv[3];
++	u32 mclk[MAX_AC_TIMING_ENTRIES];
++};
++
++#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
++#define VBIOS_MAX_AC_TIMING_ENTRIES 20
++
++struct atom_mc_reg_entry {
++	u32 mclk_max;
++	u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
++};
++
++struct atom_mc_register_address {
++	u16 s1;
++	u8 pre_reg_data;
++};
++
++struct atom_mc_reg_table {
++	u8 last;
++	u8 num_entries;
++	struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
++	struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
++};
++
++#define MAX_VOLTAGE_ENTRIES 32
++
++struct atom_voltage_table_entry
++{
++	u16 value;
++	u32 smio_low;
++};
++
++struct atom_voltage_table
++{
++	u32 count;
++	u32 mask_low;
++	u32 phase_delay;
++	struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
++};
++
++struct amdgpu_gpio_rec
++amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
++			    u8 id);
++
++struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
++							  uint8_t id);
++void amdgpu_atombios_i2c_init(struct amdgpu_device *adev);
++
++bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev);
++
++int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev);
++
++bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
++				      struct amdgpu_atom_ss *ss,
++				      int id, u32 clock);
++
++int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
++				       u8 clock_type,
++				       u32 clock,
++				       bool strobe_mode,
++				       struct atom_clock_dividers *dividers);
++
++int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
++					    u32 clock,
++					    bool strobe_mode,
++					    struct atom_mpll_param *mpll_param);
++
++uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev);
++uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev);
++void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
++				      uint32_t eng_clock);
++void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
++				      uint32_t mem_clock);
++void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
++				 u16 voltage_level,
++				 u8 voltage_type);
++
++void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
++					     u32 eng_clock, u32 mem_clock);
++
++int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
++					      u16 *leakage_id);
++
++int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
++							     u16 *vddc, u16 *vddci,
++							     u16 virtual_voltage_id,
++							     u16 vbios_voltage_id);
++
++int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
++				    u16 virtual_voltage_id,
++				    u16 *voltage);
++
++bool
++amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
++				u8 voltage_type, u8 voltage_mode);
++
++int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
++				      u8 voltage_type, u8 voltage_mode,
++				      struct atom_voltage_table *voltage_table);
++
++int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
++				      u8 module_index,
++				      struct atom_mc_reg_table *reg_table);
++
++void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
++void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
++void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
++void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
++
++void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+new file mode 100644
+index 0000000..3f7aaa4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+@@ -0,0 +1,572 @@
++/*
++ * Copyright (c) 2010 Red Hat Inc.
++ * Author : Dave Airlie <airlied@redhat.com>
++ *
++ * Licensed under GPLv2
++ *
++ * ATPX support for both Intel/ATI
++ */
++#include <linux/vga_switcheroo.h>
++#include <linux/slab.h>
++#include <linux/acpi.h>
++#include <linux/pci.h>
++
++#include "amdgpu_acpi.h"
++
++struct amdgpu_atpx_functions {
++	bool px_params;
++	bool power_cntl;
++	bool disp_mux_cntl;
++	bool i2c_mux_cntl;
++	bool switch_start;
++	bool switch_end;
++	bool disp_connectors_mapping;
++	bool disp_detetion_ports;
++};
++
++struct amdgpu_atpx {
++	acpi_handle handle;
++	struct amdgpu_atpx_functions functions;
++};
++
++static struct amdgpu_atpx_priv {
++	bool atpx_detected;
++	/* handle for device - and atpx */
++	acpi_handle dhandle;
++	acpi_handle other_handle;
++	struct amdgpu_atpx atpx;
++} amdgpu_atpx_priv;
++
++struct atpx_verify_interface {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u16 version;		/* version */
++	u32 function_bits;	/* supported functions bit vector */
++} __packed;
++
++struct atpx_px_params {
++	u16 size;		/* structure size in bytes (includes size field) */
++	u32 valid_flags;	/* which flags are valid */
++	u32 flags;		/* flags */
++} __packed;
++
++struct atpx_power_control {
++	u16 size;
++	u8 dgpu_state;
++} __packed;
++
++struct atpx_mux {
++	u16 size;
++	u16 mux;
++} __packed;
++
++bool amdgpu_has_atpx(void) {
++	return amdgpu_atpx_priv.atpx_detected;
++}
++
++/**
++ * amdgpu_atpx_call - call an ATPX method
++ *
++ * @handle: acpi handle
++ * @function: the ATPX function to execute
++ * @params: ATPX function params
++ *
++ * Executes the requested ATPX function (all asics).
++ * Returns a pointer to the acpi output buffer.
++ */
++static union acpi_object *amdgpu_atpx_call(acpi_handle handle, int function,
++					   struct acpi_buffer *params)
++{
++	acpi_status status;
++	union acpi_object atpx_arg_elements[2];
++	struct acpi_object_list atpx_arg;
++	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
++
++	atpx_arg.count = 2;
++	atpx_arg.pointer = &atpx_arg_elements[0];
++
++	atpx_arg_elements[0].type = ACPI_TYPE_INTEGER;
++	atpx_arg_elements[0].integer.value = function;
++
++	if (params) {
++		atpx_arg_elements[1].type = ACPI_TYPE_BUFFER;
++		atpx_arg_elements[1].buffer.length = params->length;
++		atpx_arg_elements[1].buffer.pointer = params->pointer;
++	} else {
++		/* We need a second fake parameter */
++		atpx_arg_elements[1].type = ACPI_TYPE_INTEGER;
++		atpx_arg_elements[1].integer.value = 0;
++	}
++
++	status = acpi_evaluate_object(handle, NULL, &atpx_arg, &buffer);
++
++	/* Fail only if calling the method fails and ATPX is supported */
++	if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
++		printk("failed to evaluate ATPX got %s\n",
++		       acpi_format_exception(status));
++		kfree(buffer.pointer);
++		return NULL;
++	}
++
++	return buffer.pointer;
++}
++
++/**
++ * amdgpu_atpx_parse_functions - parse supported functions
++ *
++ * @f: supported functions struct
++ * @mask: supported functions mask from ATPX
++ *
++ * Use the supported functions mask from ATPX function
++ * ATPX_FUNCTION_VERIFY_INTERFACE to determine what functions
++ * are supported (all asics).
++ */
++static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mask)
++{
++	f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED;
++	f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED;
++	f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED;
++	f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED;
++	f->switch_start = mask & ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED;
++	f->switch_end = mask & ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED;
++	f->disp_connectors_mapping = mask & ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED;
++	f->disp_detetion_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED;
++}
++
++/**
++ * amdgpu_atpx_validate_functions - validate ATPX functions
++ *
++ * @atpx: amdgpu atpx struct
++ *
++ * Validate that required functions are enabled (all asics).
++ * returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
++{
++	/* make sure required functions are enabled */
++	/* dGPU power control is required */
++	atpx->functions.power_cntl = true;
++
++	if (atpx->functions.px_params) {
++		union acpi_object *info;
++		struct atpx_px_params output;
++		size_t size;
++		u32 valid_bits;
++
++		info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_GET_PX_PARAMETERS, NULL);
++		if (!info)
++			return -EIO;
++
++		memset(&output, 0, sizeof(output));
++
++		size = *(u16 *) info->buffer.pointer;
++		if (size < 10) {
++			printk("ATPX buffer is too small: %zu\n", size);
++			kfree(info);
++			return -EINVAL;
++		}
++		size = min(sizeof(output), size);
++
++		memcpy(&output, info->buffer.pointer, size);
++
++		valid_bits = output.flags & output.valid_flags;
++		/* if separate mux flag is set, mux controls are required */
++		if (valid_bits & ATPX_SEPARATE_MUX_FOR_I2C) {
++			atpx->functions.i2c_mux_cntl = true;
++			atpx->functions.disp_mux_cntl = true;
++		}
++		/* if any outputs are muxed, mux controls are required */
++		if (valid_bits & (ATPX_CRT1_RGB_SIGNAL_MUXED |
++				  ATPX_TV_SIGNAL_MUXED |
++				  ATPX_DFP_SIGNAL_MUXED))
++			atpx->functions.disp_mux_cntl = true;
++
++		kfree(info);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_verify_interface - verify ATPX
++ *
++ * @atpx: amdgpu atpx struct
++ *
++ * Execute the ATPX_FUNCTION_VERIFY_INTERFACE ATPX function
++ * to initialize ATPX and determine what features are supported
++ * (all asics).
++ * returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_verify_interface(struct amdgpu_atpx *atpx)
++{
++	union acpi_object *info;
++	struct atpx_verify_interface output;
++	size_t size;
++	int err = 0;
++
++	info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_VERIFY_INTERFACE, NULL);
++	if (!info)
++		return -EIO;
++
++	memset(&output, 0, sizeof(output));
++
++	size = *(u16 *) info->buffer.pointer;
++	if (size < 8) {
++		printk("ATPX buffer is too small: %zu\n", size);
++		err = -EINVAL;
++		goto out;
++	}
++	size = min(sizeof(output), size);
++
++	memcpy(&output, info->buffer.pointer, size);
++
++	/* TODO: check version? */
++	printk("ATPX version %u, functions 0x%08x\n",
++	       output.version, output.function_bits);
++
++	amdgpu_atpx_parse_functions(&atpx->functions, output.function_bits);
++
++out:
++	kfree(info);
++	return err;
++}
++
++/**
++ * amdgpu_atpx_set_discrete_state - power up/down discrete GPU
++ *
++ * @atpx: atpx info struct
++ * @state: discrete GPU state (0 = power down, 1 = power up)
++ *
++ * Execute the ATPX_FUNCTION_POWER_CONTROL ATPX function to
++ * power down/up the discrete GPU (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_set_discrete_state(struct amdgpu_atpx *atpx, u8 state)
++{
++	struct acpi_buffer params;
++	union acpi_object *info;
++	struct atpx_power_control input;
++
++	if (atpx->functions.power_cntl) {
++		input.size = 3;
++		input.dgpu_state = state;
++		params.length = input.size;
++		params.pointer = &input;
++		info = amdgpu_atpx_call(atpx->handle,
++					ATPX_FUNCTION_POWER_CONTROL,
++					&params);
++		if (!info)
++			return -EIO;
++		kfree(info);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_switch_disp_mux - switch display mux
++ *
++ * @atpx: atpx info struct
++ * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
++ *
++ * Execute the ATPX_FUNCTION_DISPLAY_MUX_CONTROL ATPX function to
++ * switch the display mux between the discrete GPU and integrated GPU
++ * (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_switch_disp_mux(struct amdgpu_atpx *atpx, u16 mux_id)
++{
++	struct acpi_buffer params;
++	union acpi_object *info;
++	struct atpx_mux input;
++
++	if (atpx->functions.disp_mux_cntl) {
++		input.size = 4;
++		input.mux = mux_id;
++		params.length = input.size;
++		params.pointer = &input;
++		info = amdgpu_atpx_call(atpx->handle,
++					ATPX_FUNCTION_DISPLAY_MUX_CONTROL,
++					&params);
++		if (!info)
++			return -EIO;
++		kfree(info);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_switch_i2c_mux - switch i2c/hpd mux
++ *
++ * @atpx: atpx info struct
++ * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
++ *
++ * Execute the ATPX_FUNCTION_I2C_MUX_CONTROL ATPX function to
++ * switch the i2c/hpd mux between the discrete GPU and integrated GPU
++ * (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_switch_i2c_mux(struct amdgpu_atpx *atpx, u16 mux_id)
++{
++	struct acpi_buffer params;
++	union acpi_object *info;
++	struct atpx_mux input;
++
++	if (atpx->functions.i2c_mux_cntl) {
++		input.size = 4;
++		input.mux = mux_id;
++		params.length = input.size;
++		params.pointer = &input;
++		info = amdgpu_atpx_call(atpx->handle,
++					ATPX_FUNCTION_I2C_MUX_CONTROL,
++					&params);
++		if (!info)
++			return -EIO;
++		kfree(info);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_switch_start - notify the sbios of a GPU switch
++ *
++ * @atpx: atpx info struct
++ * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
++ *
++ * Execute the ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION ATPX
++ * function to notify the sbios that a switch between the discrete GPU and
++ * integrated GPU has begun (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_switch_start(struct amdgpu_atpx *atpx, u16 mux_id)
++{
++	struct acpi_buffer params;
++	union acpi_object *info;
++	struct atpx_mux input;
++
++	if (atpx->functions.switch_start) {
++		input.size = 4;
++		input.mux = mux_id;
++		params.length = input.size;
++		params.pointer = &input;
++		info = amdgpu_atpx_call(atpx->handle,
++					ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION,
++					&params);
++		if (!info)
++			return -EIO;
++		kfree(info);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_switch_end - notify the sbios of a GPU switch
++ *
++ * @atpx: atpx info struct
++ * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
++ *
++ * Execute the ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION ATPX
++ * function to notify the sbios that a switch between the discrete GPU and
++ * integrated GPU has ended (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_switch_end(struct amdgpu_atpx *atpx, u16 mux_id)
++{
++	struct acpi_buffer params;
++	union acpi_object *info;
++	struct atpx_mux input;
++
++	if (atpx->functions.switch_end) {
++		input.size = 4;
++		input.mux = mux_id;
++		params.length = input.size;
++		params.pointer = &input;
++		info = amdgpu_atpx_call(atpx->handle,
++					ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION,
++					&params);
++		if (!info)
++			return -EIO;
++		kfree(info);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_switchto - switch to the requested GPU
++ *
++ * @id: GPU to switch to
++ *
++ * Execute the necessary ATPX functions to switch between the discrete GPU and
++ * integrated GPU (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_switchto(enum vga_switcheroo_client_id id)
++{
++	u16 gpu_id;
++
++	if (id == VGA_SWITCHEROO_IGD)
++		gpu_id = ATPX_INTEGRATED_GPU;
++	else
++		gpu_id = ATPX_DISCRETE_GPU;
++
++	amdgpu_atpx_switch_start(&amdgpu_atpx_priv.atpx, gpu_id);
++	amdgpu_atpx_switch_disp_mux(&amdgpu_atpx_priv.atpx, gpu_id);
++	amdgpu_atpx_switch_i2c_mux(&amdgpu_atpx_priv.atpx, gpu_id);
++	amdgpu_atpx_switch_end(&amdgpu_atpx_priv.atpx, gpu_id);
++
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_power_state - power down/up the requested GPU
++ *
++ * @id: GPU to power down/up
++ * @state: requested power state (0 = off, 1 = on)
++ *
++ * Execute the necessary ATPX function to power down/up the discrete GPU
++ * (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_power_state(enum vga_switcheroo_client_id id,
++				   enum vga_switcheroo_state state)
++{
++	/* on w500 ACPI can't change intel gpu state */
++	if (id == VGA_SWITCHEROO_IGD)
++		return 0;
++
++	amdgpu_atpx_set_discrete_state(&amdgpu_atpx_priv.atpx, state);
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_pci_probe_handle - look up the ATPX handle
++ *
++ * @pdev: pci device
++ *
++ * Look up the ATPX handles (all asics).
++ * Returns true if the handles are found, false if not.
++ */
++static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
++{
++	acpi_handle dhandle, atpx_handle;
++	acpi_status status;
++
++	dhandle = ACPI_HANDLE(&pdev->dev);
++	if (!dhandle)
++		return false;
++
++	status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
++	if (ACPI_FAILURE(status)) {
++		amdgpu_atpx_priv.other_handle = dhandle;
++		return false;
++	}
++	amdgpu_atpx_priv.dhandle = dhandle;
++	amdgpu_atpx_priv.atpx.handle = atpx_handle;
++	return true;
++}
++
++/**
++ * amdgpu_atpx_init - verify the ATPX interface
++ *
++ * Verify the ATPX interface (all asics).
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_atpx_init(void)
++{
++	int r;
++
++	/* set up the ATPX handle */
++	r = amdgpu_atpx_verify_interface(&amdgpu_atpx_priv.atpx);
++	if (r)
++		return r;
++
++	/* validate the atpx setup */
++	r = amdgpu_atpx_validate(&amdgpu_atpx_priv.atpx);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++/**
++ * amdgpu_atpx_get_client_id - get the client id
++ *
++ * @pdev: pci device
++ *
++ * look up whether we are the integrated or discrete GPU (all asics).
++ * Returns the client id.
++ */
++static int amdgpu_atpx_get_client_id(struct pci_dev *pdev)
++{
++	if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))
++		return VGA_SWITCHEROO_IGD;
++	else
++		return VGA_SWITCHEROO_DIS;
++}
++
++static struct vga_switcheroo_handler amdgpu_atpx_handler = {
++	.switchto = amdgpu_atpx_switchto,
++	.power_state = amdgpu_atpx_power_state,
++	.init = amdgpu_atpx_init,
++	.get_client_id = amdgpu_atpx_get_client_id,
++};
++
++/**
++ * amdgpu_atpx_detect - detect whether we have PX
++ *
++ * Check if we have a PX system (all asics).
++ * Returns true if we have a PX system, false if not.
++ */
++static bool amdgpu_atpx_detect(void)
++{
++	char acpi_method_name[255] = { 0 };
++	struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
++	struct pci_dev *pdev = NULL;
++	bool has_atpx = false;
++	int vga_count = 0;
++
++	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
++		vga_count++;
++
++		has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
++	}
++
++	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
++		vga_count++;
++
++		has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
++	}
++
++	if (has_atpx && vga_count == 2) {
++		acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
++		printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n",
++		       acpi_method_name);
++		amdgpu_atpx_priv.atpx_detected = true;
++		return true;
++	}
++	return false;
++}
++
++/**
++ * amdgpu_register_atpx_handler - register with vga_switcheroo
++ *
++ * Register the PX callbacks with vga_switcheroo (all asics).
++ */
++void amdgpu_register_atpx_handler(void)
++{
++	bool r;
++
++	/* detect if we have any ATPX + 2 VGA in the system */
++	r = amdgpu_atpx_detect();
++	if (!r)
++		return;
++
++	vga_switcheroo_register_handler(&amdgpu_atpx_handler);
++}
++
++/**
++ * amdgpu_unregister_atpx_handler - unregister with vga_switcheroo
++ *
++ * Unregister the PX callbacks with vga_switcheroo (all asics).
++ */
++void amdgpu_unregister_atpx_handler(void)
++{
++	vga_switcheroo_unregister_handler();
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+new file mode 100644
+index 0000000..2742b9a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+@@ -0,0 +1,221 @@
++/*
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++#define AMDGPU_BENCHMARK_ITERATIONS 1024
++#define AMDGPU_BENCHMARK_COMMON_MODES_N 17
++
++static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
++				    uint64_t saddr, uint64_t daddr, int n)
++{
++	unsigned long start_jiffies;
++	unsigned long end_jiffies;
++	struct amdgpu_fence *fence = NULL;
++	int i, r;
++
++	start_jiffies = jiffies;
++	for (i = 0; i < n; i++) {
++		struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
++		r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence);
++		if (r)
++			goto exit_do_move;
++		r = amdgpu_fence_wait(fence, false);
++		if (r)
++			goto exit_do_move;
++		amdgpu_fence_unref(&fence);
++	}
++	end_jiffies = jiffies;
++	r = jiffies_to_msecs(end_jiffies - start_jiffies);
++
++exit_do_move:
++	if (fence)
++		amdgpu_fence_unref(&fence);
++	return r;
++}
++
++
++static void amdgpu_benchmark_log_results(int n, unsigned size,
++					 unsigned int time,
++					 unsigned sdomain, unsigned ddomain,
++					 char *kind)
++{
++	unsigned int throughput = (n * (size >> 10)) / time;
++	DRM_INFO("amdgpu: %s %u bo moves of %u kB from"
++		 " %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
++		 kind, n, size >> 10, sdomain, ddomain, time,
++		 throughput * 8, throughput);
++}
++
++static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size,
++				  unsigned sdomain, unsigned ddomain)
++{
++	struct amdgpu_bo *dobj = NULL;
++	struct amdgpu_bo *sobj = NULL;
++	uint64_t saddr, daddr;
++	int r, n;
++	int time;
++
++	n = AMDGPU_BENCHMARK_ITERATIONS;
++	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, sdomain, 0, NULL, &sobj);
++	if (r) {
++		goto out_cleanup;
++	}
++	r = amdgpu_bo_reserve(sobj, false);
++	if (unlikely(r != 0))
++		goto out_cleanup;
++	r = amdgpu_bo_pin(sobj, sdomain, &saddr);
++	amdgpu_bo_unreserve(sobj);
++	if (r) {
++		goto out_cleanup;
++	}
++	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, ddomain, 0, NULL, &dobj);
++	if (r) {
++		goto out_cleanup;
++	}
++	r = amdgpu_bo_reserve(dobj, false);
++	if (unlikely(r != 0))
++		goto out_cleanup;
++	r = amdgpu_bo_pin(dobj, ddomain, &daddr);
++	amdgpu_bo_unreserve(dobj);
++	if (r) {
++		goto out_cleanup;
++	}
++
++	if (adev->mman.buffer_funcs) {
++		time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
++		if (time < 0)
++			goto out_cleanup;
++		if (time > 0)
++			amdgpu_benchmark_log_results(n, size, time,
++						     sdomain, ddomain, "dma");
++	}
++
++out_cleanup:
++	if (sobj) {
++		r = amdgpu_bo_reserve(sobj, false);
++		if (likely(r == 0)) {
++			amdgpu_bo_unpin(sobj);
++			amdgpu_bo_unreserve(sobj);
++		}
++		amdgpu_bo_unref(&sobj);
++	}
++	if (dobj) {
++		r = amdgpu_bo_reserve(dobj, false);
++		if (likely(r == 0)) {
++			amdgpu_bo_unpin(dobj);
++			amdgpu_bo_unreserve(dobj);
++		}
++		amdgpu_bo_unref(&dobj);
++	}
++
++	if (r) {
++		DRM_ERROR("Error while benchmarking BO move.\n");
++	}
++}
++
++void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)
++{
++	int i;
++	int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = {
++		640 * 480 * 4,
++		720 * 480 * 4,
++		800 * 600 * 4,
++		848 * 480 * 4,
++		1024 * 768 * 4,
++		1152 * 768 * 4,
++		1280 * 720 * 4,
++		1280 * 800 * 4,
++		1280 * 854 * 4,
++		1280 * 960 * 4,
++		1280 * 1024 * 4,
++		1440 * 900 * 4,
++		1400 * 1050 * 4,
++		1680 * 1050 * 4,
++		1600 * 1200 * 4,
++		1920 * 1080 * 4,
++		1920 * 1200 * 4
++	};
++
++	switch (test_number) {
++	case 1:
++		/* simple test, VRAM to GTT and GTT to VRAM */
++		amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_GTT,
++				      AMDGPU_GEM_DOMAIN_VRAM);
++		amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM,
++				      AMDGPU_GEM_DOMAIN_GTT);
++		break;
++	case 2:
++		/* simple test, VRAM to VRAM */
++		amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM,
++				      AMDGPU_GEM_DOMAIN_VRAM);
++		break;
++	case 3:
++		/* GTT to VRAM, buffer size sweep, powers of 2 */
++		for (i = 1; i <= 16384; i <<= 1)
++			amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
++					      AMDGPU_GEM_DOMAIN_GTT,
++					      AMDGPU_GEM_DOMAIN_VRAM);
++		break;
++	case 4:
++		/* VRAM to GTT, buffer size sweep, powers of 2 */
++		for (i = 1; i <= 16384; i <<= 1)
++			amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
++					      AMDGPU_GEM_DOMAIN_VRAM,
++					      AMDGPU_GEM_DOMAIN_GTT);
++		break;
++	case 5:
++		/* VRAM to VRAM, buffer size sweep, powers of 2 */
++		for (i = 1; i <= 16384; i <<= 1)
++			amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
++					      AMDGPU_GEM_DOMAIN_VRAM,
++					      AMDGPU_GEM_DOMAIN_VRAM);
++		break;
++	case 6:
++		/* GTT to VRAM, buffer size sweep, common modes */
++		for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++)
++			amdgpu_benchmark_move(adev, common_modes[i],
++					      AMDGPU_GEM_DOMAIN_GTT,
++					      AMDGPU_GEM_DOMAIN_VRAM);
++		break;
++	case 7:
++		/* VRAM to GTT, buffer size sweep, common modes */
++		for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++)
++			amdgpu_benchmark_move(adev, common_modes[i],
++					      AMDGPU_GEM_DOMAIN_VRAM,
++					      AMDGPU_GEM_DOMAIN_GTT);
++		break;
++	case 8:
++		/* VRAM to VRAM, buffer size sweep, common modes */
++		for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++)
++			amdgpu_benchmark_move(adev, common_modes[i],
++					      AMDGPU_GEM_DOMAIN_VRAM,
++					      AMDGPU_GEM_DOMAIN_VRAM);
++		break;
++
++	default:
++		DRM_ERROR("Unknown benchmark\n");
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+new file mode 100644
+index 0000000..d938a11
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+@@ -0,0 +1,359 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "atom.h"
++
++#include <linux/vga_switcheroo.h>
++#include <linux/slab.h>
++#include <linux/acpi.h>
++/*
++ * BIOS.
++ */
++
++/* If you boot an IGP board with a discrete card as the primary,
++ * the IGP rom is not accessible via the rom bar as the IGP rom is
++ * part of the system bios.  On boot, the system bios puts a
++ * copy of the igp rom at the start of vram if a discrete card is
++ * present.
++ */
++static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
++{
++	uint8_t __iomem *bios;
++	resource_size_t vram_base;
++	resource_size_t size = 256 * 1024; /* ??? */
++
++	if (!(adev->flags & AMDGPU_IS_APU))
++		if (!amdgpu_card_posted(adev))
++			return false;
++
++	adev->bios = NULL;
++	vram_base = pci_resource_start(adev->pdev, 0);
++	bios = ioremap(vram_base, size);
++	if (!bios) {
++		return false;
++	}
++
++	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
++		iounmap(bios);
++		return false;
++	}
++	adev->bios = kmalloc(size, GFP_KERNEL);
++	if (adev->bios == NULL) {
++		iounmap(bios);
++		return false;
++	}
++	memcpy_fromio(adev->bios, bios, size);
++	iounmap(bios);
++	return true;
++}
++
++bool amdgpu_read_bios(struct amdgpu_device *adev)
++{
++	uint8_t __iomem *bios;
++	size_t size;
++
++	adev->bios = NULL;
++	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
++	bios = pci_map_rom(adev->pdev, &size);
++	if (!bios) {
++		return false;
++	}
++
++	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
++		pci_unmap_rom(adev->pdev, bios);
++		return false;
++	}
++	adev->bios = kmemdup(bios, size, GFP_KERNEL);
++	if (adev->bios == NULL) {
++		pci_unmap_rom(adev->pdev, bios);
++		return false;
++	}
++	pci_unmap_rom(adev->pdev, bios);
++	return true;
++}
++
++static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
++{
++	uint8_t __iomem *bios;
++	size_t size;
++
++	adev->bios = NULL;
++
++	bios = pci_platform_rom(adev->pdev, &size);
++	if (!bios) {
++		return false;
++	}
++
++	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
++		return false;
++	}
++	adev->bios = kmemdup(bios, size, GFP_KERNEL);
++	if (adev->bios == NULL) {
++		return false;
++	}
++
++	return true;
++}
++
++#ifdef CONFIG_ACPI
++/* ATRM is used to get the BIOS on the discrete cards in
++ * dual-gpu systems.
++ */
++/* retrieve the ROM in 4k blocks */
++#define ATRM_BIOS_PAGE 4096
++/**
++ * amdgpu_atrm_call - fetch a chunk of the vbios
++ *
++ * @atrm_handle: acpi ATRM handle
++ * @bios: vbios image pointer
++ * @offset: offset of vbios image data to fetch
++ * @len: length of vbios image data to fetch
++ *
++ * Executes ATRM to fetch a chunk of the discrete
++ * vbios image on PX systems (all asics).
++ * Returns the length of the buffer fetched.
++ */
++static int amdgpu_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
++			    int offset, int len)
++{
++	acpi_status status;
++	union acpi_object atrm_arg_elements[2], *obj;
++	struct acpi_object_list atrm_arg;
++	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
++
++	atrm_arg.count = 2;
++	atrm_arg.pointer = &atrm_arg_elements[0];
++
++	atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
++	atrm_arg_elements[0].integer.value = offset;
++
++	atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
++	atrm_arg_elements[1].integer.value = len;
++
++	status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
++	if (ACPI_FAILURE(status)) {
++		printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
++		return -ENODEV;
++	}
++
++	obj = (union acpi_object *)buffer.pointer;
++	memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
++	len = obj->buffer.length;
++	kfree(buffer.pointer);
++	return len;
++}
++
++static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
++{
++	int ret;
++	int size = 256 * 1024;
++	int i;
++	struct pci_dev *pdev = NULL;
++	acpi_handle dhandle, atrm_handle;
++	acpi_status status;
++	bool found = false;
++
++	/* ATRM is for the discrete card only */
++	if (adev->flags & AMDGPU_IS_APU)
++		return false;
++
++	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
++		dhandle = ACPI_HANDLE(&pdev->dev);
++		if (!dhandle)
++			continue;
++
++		status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
++		if (!ACPI_FAILURE(status)) {
++			found = true;
++			break;
++		}
++	}
++
++	if (!found) {
++		while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
++			dhandle = ACPI_HANDLE(&pdev->dev);
++			if (!dhandle)
++				continue;
++
++			status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
++			if (!ACPI_FAILURE(status)) {
++				found = true;
++				break;
++			}
++		}
++	}
++
++	if (!found)
++		return false;
++
++	adev->bios = kmalloc(size, GFP_KERNEL);
++	if (!adev->bios) {
++		DRM_ERROR("Unable to allocate bios\n");
++		return false;
++	}
++
++	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
++		ret = amdgpu_atrm_call(atrm_handle,
++				       adev->bios,
++				       (i * ATRM_BIOS_PAGE),
++				       ATRM_BIOS_PAGE);
++		if (ret < ATRM_BIOS_PAGE)
++			break;
++	}
++
++	if (i == 0 || adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) {
++		kfree(adev->bios);
++		return false;
++	}
++	return true;
++}
++#else
++static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
++{
++	return false;
++}
++#endif
++
++static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
++{
++	if (adev->flags & AMDGPU_IS_APU)
++		return igp_read_bios_from_vram(adev);
++	else
++		return amdgpu_asic_read_disabled_bios(adev);
++}
++
++#ifdef CONFIG_ACPI
++static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
++{
++	bool ret = false;
++	struct acpi_table_header *hdr;
++	acpi_size tbl_size;
++	UEFI_ACPI_VFCT *vfct;
++	GOP_VBIOS_CONTENT *vbios;
++	VFCT_IMAGE_HEADER *vhdr;
++
++	if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
++		return false;
++	if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
++		DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
++		goto out_unmap;
++	}
++
++	vfct = (UEFI_ACPI_VFCT *)hdr;
++	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
++		DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
++		goto out_unmap;
++	}
++
++	vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
++	vhdr = &vbios->VbiosHeader;
++	DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
++			vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
++			vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
++
++	if (vhdr->PCIBus != adev->pdev->bus->number ||
++	    vhdr->PCIDevice != PCI_SLOT(adev->pdev->devfn) ||
++	    vhdr->PCIFunction != PCI_FUNC(adev->pdev->devfn) ||
++	    vhdr->VendorID != adev->pdev->vendor ||
++	    vhdr->DeviceID != adev->pdev->device) {
++		DRM_INFO("ACPI VFCT table is not for this card\n");
++		goto out_unmap;
++	};
++
++	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
++		DRM_ERROR("ACPI VFCT image truncated\n");
++		goto out_unmap;
++	}
++
++	adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
++	ret = !!adev->bios;
++
++out_unmap:
++	return ret;
++}
++#else
++static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
++{
++	return false;
++}
++#endif
++
++bool amdgpu_get_bios(struct amdgpu_device *adev)
++{
++	bool r;
++	uint16_t tmp;
++
++	r = amdgpu_atrm_get_bios(adev);
++	if (r == false)
++		r = amdgpu_acpi_vfct_bios(adev);
++	if (r == false)
++		r = igp_read_bios_from_vram(adev);
++	if (r == false)
++		r = amdgpu_read_bios(adev);
++	if (r == false) {
++		r = amdgpu_read_disabled_bios(adev);
++	}
++	if (r == false) {
++		r = amdgpu_read_platform_bios(adev);
++	}
++	if (r == false || adev->bios == NULL) {
++		DRM_ERROR("Unable to locate a BIOS ROM\n");
++		adev->bios = NULL;
++		return false;
++	}
++	if (adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) {
++		printk("BIOS signature incorrect %x %x\n", adev->bios[0], adev->bios[1]);
++		goto free_bios;
++	}
++
++	tmp = RBIOS16(0x18);
++	if (RBIOS8(tmp + 0x14) != 0x0) {
++		DRM_INFO("Not an x86 BIOS ROM, not using.\n");
++		goto free_bios;
++	}
++
++	adev->bios_header_start = RBIOS16(0x48);
++	if (!adev->bios_header_start) {
++		goto free_bios;
++	}
++	tmp = adev->bios_header_start + 4;
++	if (!memcmp(adev->bios + tmp, "ATOM", 4) ||
++	    !memcmp(adev->bios + tmp, "MOTA", 4)) {
++		adev->is_atom_bios = true;
++	} else {
++		adev->is_atom_bios = false;
++	}
++
++	DRM_DEBUG("%sBIOS detected\n", adev->is_atom_bios ? "ATOM" : "COM");
++	return true;
++free_bios:
++	kfree(adev->bios);
++	adev->bios = NULL;
++	return false;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+new file mode 100644
+index 0000000..819fb86
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+@@ -0,0 +1,268 @@
++/*
++ * Copyright 2015 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Christian König <deathsimple@vodafone.de>
++ */
++
++#include <drm/drmP.h>
++#include "amdgpu.h"
++
++static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv,
++				 struct amdgpu_bo_list **result,
++				 int *id)
++{
++	int r;
++
++	*result = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL);
++	if (!*result)
++		return -ENOMEM;
++
++	mutex_lock(&fpriv->bo_list_lock);
++	r = idr_alloc(&fpriv->bo_list_handles, *result,
++		      0, 0, GFP_KERNEL);
++	if (r < 0) {
++		mutex_unlock(&fpriv->bo_list_lock);
++		kfree(*result);
++		return r;
++	}
++	*id = r;
++
++	mutex_init(&(*result)->lock);
++	(*result)->num_entries = 0;
++	(*result)->array = NULL;
++
++	mutex_lock(&(*result)->lock);
++	mutex_unlock(&fpriv->bo_list_lock);
++
++	return 0;
++}
++
++static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)
++{
++	struct amdgpu_bo_list *list;
++
++	mutex_lock(&fpriv->bo_list_lock);
++	list = idr_find(&fpriv->bo_list_handles, id);
++	if (list) {
++		mutex_lock(&list->lock);
++		idr_remove(&fpriv->bo_list_handles, id);
++		mutex_unlock(&list->lock);
++		amdgpu_bo_list_free(list);
++	}
++	mutex_unlock(&fpriv->bo_list_lock);
++}
++
++static int amdgpu_bo_list_set(struct amdgpu_device *adev,
++				     struct drm_file *filp,
++				     struct amdgpu_bo_list *list,
++				     struct drm_amdgpu_bo_list_entry *info,
++				     unsigned num_entries)
++{
++	struct amdgpu_bo_list_entry *array;
++	struct amdgpu_bo *gds_obj = adev->gds.gds_gfx_bo;
++	struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo;
++	struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo;
++
++	bool has_userptr = false;
++	unsigned i;
++
++	array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry));
++	if (!array)
++		return -ENOMEM;
++	memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));
++
++	for (i = 0; i < num_entries; ++i) {
++		struct amdgpu_bo_list_entry *entry = &array[i];
++		struct drm_gem_object *gobj;
++
++		gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
++		if (!gobj)
++			goto error_free;
++
++		entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
++		drm_gem_object_unreference_unlocked(gobj);
++		entry->priority = info[i].bo_priority;
++		entry->prefered_domains = entry->robj->initial_domain;
++		entry->allowed_domains = entry->prefered_domains;
++		if (entry->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
++			entry->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
++		if (amdgpu_ttm_tt_has_userptr(entry->robj->tbo.ttm)) {
++			has_userptr = true;
++			entry->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
++			entry->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
++		}
++		entry->tv.bo = &entry->robj->tbo;
++		entry->tv.shared = true;
++
++		if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
++			gds_obj = entry->robj;
++		if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GWS)
++			gws_obj = entry->robj;
++		if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_OA)
++			oa_obj = entry->robj;
++	}
++
++	for (i = 0; i < list->num_entries; ++i)
++		amdgpu_bo_unref(&list->array[i].robj);
++
++	drm_free_large(list->array);
++
++	list->gds_obj = gds_obj;
++	list->gws_obj = gws_obj;
++	list->oa_obj = oa_obj;
++	list->has_userptr = has_userptr;
++	list->array = array;
++	list->num_entries = num_entries;
++
++	return 0;
++
++error_free:
++	drm_free_large(array);
++	return -ENOENT;
++}
++
++struct amdgpu_bo_list *
++amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id)
++{
++	struct amdgpu_bo_list *result;
++
++	mutex_lock(&fpriv->bo_list_lock);
++	result = idr_find(&fpriv->bo_list_handles, id);
++	if (result)
++		mutex_lock(&result->lock);
++	mutex_unlock(&fpriv->bo_list_lock);
++	return result;
++}
++
++void amdgpu_bo_list_put(struct amdgpu_bo_list *list)
++{
++	mutex_unlock(&list->lock);
++}
++
++void amdgpu_bo_list_free(struct amdgpu_bo_list *list)
++{
++	unsigned i;
++
++	for (i = 0; i < list->num_entries; ++i)
++		amdgpu_bo_unref(&list->array[i].robj);
++
++	mutex_destroy(&list->lock);
++	drm_free_large(list->array);
++	kfree(list);
++}
++
++int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
++				struct drm_file *filp)
++{
++	const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);
++
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_fpriv *fpriv = filp->driver_priv;
++	union drm_amdgpu_bo_list *args = data;
++	uint32_t handle = args->in.list_handle;
++	const void __user *uptr = (const void*)(long)args->in.bo_info_ptr;
++
++	struct drm_amdgpu_bo_list_entry *info;
++	struct amdgpu_bo_list *list;
++
++	int r;
++
++	info = drm_malloc_ab(args->in.bo_number,
++			     sizeof(struct drm_amdgpu_bo_list_entry));
++	if (!info)
++		return -ENOMEM;
++
++	/* copy the handle array from userspace to a kernel buffer */
++	r = -EFAULT;
++	if (likely(info_size == args->in.bo_info_size)) {
++		unsigned long bytes = args->in.bo_number *
++			args->in.bo_info_size;
++
++		if (copy_from_user(info, uptr, bytes))
++			goto error_free;
++
++	} else {
++		unsigned long bytes = min(args->in.bo_info_size, info_size);
++		unsigned i;
++
++		memset(info, 0, args->in.bo_number * info_size);
++		for (i = 0; i < args->in.bo_number; ++i) {
++			if (copy_from_user(&info[i], uptr, bytes))
++				goto error_free;
++			
++			uptr += args->in.bo_info_size;
++		}
++	}
++
++	switch (args->in.operation) {
++	case AMDGPU_BO_LIST_OP_CREATE:
++		r = amdgpu_bo_list_create(fpriv, &list, &handle);
++		if (r) 
++			goto error_free;
++
++		r = amdgpu_bo_list_set(adev, filp, list, info,
++					      args->in.bo_number);
++		amdgpu_bo_list_put(list);
++		if (r)
++			goto error_free;
++
++		break;
++		
++	case AMDGPU_BO_LIST_OP_DESTROY:
++		amdgpu_bo_list_destroy(fpriv, handle);
++		handle = 0;
++		break;
++
++	case AMDGPU_BO_LIST_OP_UPDATE:
++		r = -ENOENT;
++		list = amdgpu_bo_list_get(fpriv, handle);
++		if (!list)
++			goto error_free;
++
++		r = amdgpu_bo_list_set(adev, filp, list, info,
++					      args->in.bo_number);
++		amdgpu_bo_list_put(list);
++		if (r)
++			goto error_free;
++
++		break;
++
++	default:
++		r = -EINVAL;
++		goto error_free;
++	}
++
++	memset(args, 0, sizeof(*args));
++	args->out.list_handle = handle;
++	drm_free_large(info);
++
++	return 0;
++
++error_free:
++	drm_free_large(info);
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+new file mode 100644
+index 0000000..6a8d28f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+@@ -0,0 +1,1907 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <drm/drmP.h>
++#include <drm/drm_edid.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_fb_helper.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "atom.h"
++#include "atombios_encoders.h"
++#include "atombios_dp.h"
++#include "amdgpu_connectors.h"
++#include "amdgpu_i2c.h"
++
++#include <linux/pm_runtime.h>
++
++void amdgpu_connector_hotplug(struct drm_connector *connector)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++	/* bail if the connector does not have hpd pin, e.g.,
++	 * VGA, TV, etc.
++	 */
++	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
++		return;
++
++	amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
++
++	/* if the connector is already off, don't turn it back on */
++	if (connector->dpms != DRM_MODE_DPMS_ON)
++		return;
++
++	/* just deal with DP (not eDP) here. */
++	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
++		struct amdgpu_connector_atom_dig *dig_connector =
++			amdgpu_connector->con_priv;
++
++		/* if existing sink type was not DP no need to retrain */
++		if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
++			return;
++
++		/* first get sink type as it may be reset after (un)plug */
++		dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
++		/* don't do anything if sink is not display port, i.e.,
++		 * passive dp->(dvi|hdmi) adaptor
++		 */
++		if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
++			int saved_dpms = connector->dpms;
++			/* Only turn off the display if it's physically disconnected */
++			if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
++				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
++			} else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
++				/* set it to OFF so that drm_helper_connector_dpms()
++				 * won't return immediately since the current state
++				 * is ON at this point.
++				 */
++				connector->dpms = DRM_MODE_DPMS_OFF;
++				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
++			}
++			connector->dpms = saved_dpms;
++		}
++	}
++}
++
++static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
++{
++	struct drm_crtc *crtc = encoder->crtc;
++
++	if (crtc && crtc->enabled) {
++		drm_crtc_helper_set_mode(crtc, &crtc->mode,
++					 crtc->x, crtc->y, crtc->primary->fb);
++	}
++}
++
++int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *dig_connector;
++	int bpc = 8;
++	unsigned mode_clock, max_tmds_clock;
++
++	switch (connector->connector_type) {
++	case DRM_MODE_CONNECTOR_DVII:
++	case DRM_MODE_CONNECTOR_HDMIB:
++		if (amdgpu_connector->use_digital) {
++			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++				if (connector->display_info.bpc)
++					bpc = connector->display_info.bpc;
++			}
++		}
++		break;
++	case DRM_MODE_CONNECTOR_DVID:
++	case DRM_MODE_CONNECTOR_HDMIA:
++		if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++			if (connector->display_info.bpc)
++				bpc = connector->display_info.bpc;
++		}
++		break;
++	case DRM_MODE_CONNECTOR_DisplayPort:
++		dig_connector = amdgpu_connector->con_priv;
++		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
++		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
++		    drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++			if (connector->display_info.bpc)
++				bpc = connector->display_info.bpc;
++		}
++		break;
++	case DRM_MODE_CONNECTOR_eDP:
++	case DRM_MODE_CONNECTOR_LVDS:
++		if (connector->display_info.bpc)
++			bpc = connector->display_info.bpc;
++		else {
++			struct drm_connector_helper_funcs *connector_funcs =
++				connector->helper_private;
++			struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
++			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++			struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++			if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
++				bpc = 6;
++			else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
++				bpc = 8;
++		}
++		break;
++	}
++
++	if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++		/*
++		 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
++		 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
++		 * 12 bpc is always supported on hdmi deep color sinks, as this is
++		 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
++		 */
++		if (bpc > 12) {
++			DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
++				  connector->name, bpc);
++			bpc = 12;
++		}
++
++		/* Any defined maximum tmds clock limit we must not exceed? */
++		if (connector->max_tmds_clock > 0) {
++			/* mode_clock is clock in kHz for mode to be modeset on this connector */
++			mode_clock = amdgpu_connector->pixelclock_for_modeset;
++
++			/* Maximum allowable input clock in kHz */
++			max_tmds_clock = connector->max_tmds_clock * 1000;
++
++			DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
++				  connector->name, mode_clock, max_tmds_clock);
++
++			/* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
++			if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
++				if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
++				    (mode_clock * 5/4 <= max_tmds_clock))
++					bpc = 10;
++				else
++					bpc = 8;
++
++				DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
++					  connector->name, bpc);
++			}
++
++			if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
++				bpc = 8;
++				DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
++					  connector->name, bpc);
++			} else if (bpc > 8) {
++				/* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
++				DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
++					  connector->name);
++				bpc = 8;
++			}
++		}
++	}
++
++	if ((amdgpu_deep_color == 0) && (bpc > 8)) {
++		DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
++			  connector->name);
++		bpc = 8;
++	}
++
++	DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
++		  connector->name, connector->display_info.bpc, bpc);
++
++	return bpc;
++}
++
++static void
++amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
++				      enum drm_connector_status status)
++{
++	struct drm_encoder *best_encoder = NULL;
++	struct drm_encoder *encoder = NULL;
++	struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
++	bool connected;
++	int i;
++
++	best_encoder = connector_funcs->best_encoder(connector);
++
++	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++		if (connector->encoder_ids[i] == 0)
++			break;
++
++		encoder = drm_encoder_find(connector->dev,
++					connector->encoder_ids[i]);
++		if (!encoder)
++			continue;
++
++		if ((encoder == best_encoder) && (status == connector_status_connected))
++			connected = true;
++		else
++			connected = false;
++
++		amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
++
++	}
++}
++
++static struct drm_encoder *
++amdgpu_connector_find_encoder(struct drm_connector *connector,
++			       int encoder_type)
++{
++	struct drm_encoder *encoder;
++	int i;
++
++	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++		if (connector->encoder_ids[i] == 0)
++			break;
++		encoder = drm_encoder_find(connector->dev,
++					connector->encoder_ids[i]);
++		if (!encoder)
++			continue;
++
++		if (encoder->encoder_type == encoder_type)
++			return encoder;
++	}
++	return NULL;
++}
++
++struct edid *amdgpu_connector_edid(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
++
++	if (amdgpu_connector->edid) {
++		return amdgpu_connector->edid;
++	} else if (edid_blob) {
++		struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
++		if (edid)
++			amdgpu_connector->edid = edid;
++	}
++	return amdgpu_connector->edid;
++}
++
++static struct edid *
++amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
++{
++	struct edid *edid;
++
++	if (adev->mode_info.bios_hardcoded_edid) {
++		edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
++		if (edid) {
++			memcpy((unsigned char *)edid,
++			       (unsigned char *)adev->mode_info.bios_hardcoded_edid,
++			       adev->mode_info.bios_hardcoded_edid_size);
++			return edid;
++		}
++	}
++	return NULL;
++}
++
++static void amdgpu_connector_get_edid(struct drm_connector *connector)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++	if (amdgpu_connector->edid)
++		return;
++
++	/* on hw with routers, select right port */
++	if (amdgpu_connector->router.ddc_valid)
++		amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
++
++	if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++	     ENCODER_OBJECT_ID_NONE) &&
++	    amdgpu_connector->ddc_bus->has_aux) {
++		amdgpu_connector->edid = drm_get_edid(connector,
++						      &amdgpu_connector->ddc_bus->aux.ddc);
++	} else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
++		   (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
++		struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
++
++		if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
++		     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
++		    amdgpu_connector->ddc_bus->has_aux)
++			amdgpu_connector->edid = drm_get_edid(connector,
++							      &amdgpu_connector->ddc_bus->aux.ddc);
++		else if (amdgpu_connector->ddc_bus)
++			amdgpu_connector->edid = drm_get_edid(connector,
++							      &amdgpu_connector->ddc_bus->adapter);
++	} else if (amdgpu_connector->ddc_bus) {
++		amdgpu_connector->edid = drm_get_edid(connector,
++						      &amdgpu_connector->ddc_bus->adapter);
++	}
++
++	if (!amdgpu_connector->edid) {
++		/* some laptops provide a hardcoded edid in rom for LCDs */
++		if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
++		     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
++			amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
++	}
++}
++
++static void amdgpu_connector_free_edid(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++	if (amdgpu_connector->edid) {
++		kfree(amdgpu_connector->edid);
++		amdgpu_connector->edid = NULL;
++	}
++}
++
++static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	int ret;
++
++	if (amdgpu_connector->edid) {
++		drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
++		ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
++		drm_edid_to_eld(connector, amdgpu_connector->edid);
++		return ret;
++	}
++	drm_mode_connector_update_edid_property(connector, NULL);
++	return 0;
++}
++
++static struct drm_encoder *
++amdgpu_connector_best_single_encoder(struct drm_connector *connector)
++{
++	int enc_id = connector->encoder_ids[0];
++
++	/* pick the encoder ids */
++	if (enc_id)
++		return drm_encoder_find(connector->dev, enc_id);
++	return NULL;
++}
++
++static void amdgpu_get_native_mode(struct drm_connector *connector)
++{
++	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
++	struct amdgpu_encoder *amdgpu_encoder;
++
++	if (encoder == NULL)
++		return;
++
++	amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++	if (!list_empty(&connector->probed_modes)) {
++		struct drm_display_mode *preferred_mode =
++			list_first_entry(&connector->probed_modes,
++					 struct drm_display_mode, head);
++
++		amdgpu_encoder->native_mode = *preferred_mode;
++	} else {
++		amdgpu_encoder->native_mode.clock = 0;
++	}
++}
++
++static struct drm_display_mode *
++amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_display_mode *mode = NULL;
++	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++
++	if (native_mode->hdisplay != 0 &&
++	    native_mode->vdisplay != 0 &&
++	    native_mode->clock != 0) {
++		mode = drm_mode_duplicate(dev, native_mode);
++		mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
++		drm_mode_set_name(mode);
++
++		DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
++	} else if (native_mode->hdisplay != 0 &&
++		   native_mode->vdisplay != 0) {
++		/* mac laptops without an edid */
++		/* Note that this is not necessarily the exact panel mode,
++		 * but an approximation based on the cvt formula.  For these
++		 * systems we should ideally read the mode info out of the
++		 * registers or add a mode table, but this works and is much
++		 * simpler.
++		 */
++		mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
++		mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
++		DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
++	}
++	return mode;
++}
++
++static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
++					       struct drm_connector *connector)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_display_mode *mode = NULL;
++	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++	int i;
++	struct mode_size {
++		int w;
++		int h;
++	} common_modes[17] = {
++		{ 640,  480},
++		{ 720,  480},
++		{ 800,  600},
++		{ 848,  480},
++		{1024,  768},
++		{1152,  768},
++		{1280,  720},
++		{1280,  800},
++		{1280,  854},
++		{1280,  960},
++		{1280, 1024},
++		{1440,  900},
++		{1400, 1050},
++		{1680, 1050},
++		{1600, 1200},
++		{1920, 1080},
++		{1920, 1200}
++	};
++
++	for (i = 0; i < 17; i++) {
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
++			if (common_modes[i].w > 1024 ||
++			    common_modes[i].h > 768)
++				continue;
++		}
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++			if (common_modes[i].w > native_mode->hdisplay ||
++			    common_modes[i].h > native_mode->vdisplay ||
++			    (common_modes[i].w == native_mode->hdisplay &&
++			     common_modes[i].h == native_mode->vdisplay))
++				continue;
++		}
++		if (common_modes[i].w < 320 || common_modes[i].h < 200)
++			continue;
++
++		mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
++		drm_mode_probed_add(connector, mode);
++	}
++}
++
++static int amdgpu_connector_set_property(struct drm_connector *connector,
++					  struct drm_property *property,
++					  uint64_t val)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++
++	if (property == adev->mode_info.coherent_mode_property) {
++		struct amdgpu_encoder_atom_dig *dig;
++		bool new_coherent_mode;
++
++		/* need to find digital encoder on connector */
++		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
++		if (!encoder)
++			return 0;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		if (!amdgpu_encoder->enc_priv)
++			return 0;
++
++		dig = amdgpu_encoder->enc_priv;
++		new_coherent_mode = val ? true : false;
++		if (dig->coherent_mode != new_coherent_mode) {
++			dig->coherent_mode = new_coherent_mode;
++			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++		}
++	}
++
++	if (property == adev->mode_info.audio_property) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		/* need to find digital encoder on connector */
++		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
++		if (!encoder)
++			return 0;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		if (amdgpu_connector->audio != val) {
++			amdgpu_connector->audio = val;
++			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++		}
++	}
++
++	if (property == adev->mode_info.dither_property) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		/* need to find digital encoder on connector */
++		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
++		if (!encoder)
++			return 0;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		if (amdgpu_connector->dither != val) {
++			amdgpu_connector->dither = val;
++			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++		}
++	}
++
++	if (property == adev->mode_info.underscan_property) {
++		/* need to find digital encoder on connector */
++		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
++		if (!encoder)
++			return 0;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		if (amdgpu_encoder->underscan_type != val) {
++			amdgpu_encoder->underscan_type = val;
++			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++		}
++	}
++
++	if (property == adev->mode_info.underscan_hborder_property) {
++		/* need to find digital encoder on connector */
++		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
++		if (!encoder)
++			return 0;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		if (amdgpu_encoder->underscan_hborder != val) {
++			amdgpu_encoder->underscan_hborder = val;
++			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++		}
++	}
++
++	if (property == adev->mode_info.underscan_vborder_property) {
++		/* need to find digital encoder on connector */
++		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
++		if (!encoder)
++			return 0;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		if (amdgpu_encoder->underscan_vborder != val) {
++			amdgpu_encoder->underscan_vborder = val;
++			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++		}
++	}
++
++	if (property == adev->mode_info.load_detect_property) {
++		struct amdgpu_connector *amdgpu_connector =
++			to_amdgpu_connector(connector);
++
++		if (val == 0)
++			amdgpu_connector->dac_load_detect = false;
++		else
++			amdgpu_connector->dac_load_detect = true;
++	}
++
++	if (property == dev->mode_config.scaling_mode_property) {
++		enum amdgpu_rmx_type rmx_type;
++
++		if (connector->encoder) {
++			amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
++		} else {
++			struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
++			amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
++		}
++
++		switch (val) {
++		default:
++		case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
++		case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
++		case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
++		case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
++		}
++		if (amdgpu_encoder->rmx_type == rmx_type)
++			return 0;
++
++		if ((rmx_type != DRM_MODE_SCALE_NONE) &&
++		    (amdgpu_encoder->native_mode.clock == 0))
++			return 0;
++
++		amdgpu_encoder->rmx_type = rmx_type;
++
++		amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++	}
++
++	return 0;
++}
++
++static void
++amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
++					struct drm_connector *connector)
++{
++	struct amdgpu_encoder *amdgpu_encoder =	to_amdgpu_encoder(encoder);
++	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++	struct drm_display_mode *t, *mode;
++
++	/* If the EDID preferred mode doesn't match the native mode, use it */
++	list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
++		if (mode->type & DRM_MODE_TYPE_PREFERRED) {
++			if (mode->hdisplay != native_mode->hdisplay ||
++			    mode->vdisplay != native_mode->vdisplay)
++				memcpy(native_mode, mode, sizeof(*mode));
++		}
++	}
++
++	/* Try to get native mode details from EDID if necessary */
++	if (!native_mode->clock) {
++		list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
++			if (mode->hdisplay == native_mode->hdisplay &&
++			    mode->vdisplay == native_mode->vdisplay) {
++				*native_mode = *mode;
++				drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
++				DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
++				break;
++			}
++		}
++	}
++
++	if (!native_mode->clock) {
++		DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
++		amdgpu_encoder->rmx_type = RMX_OFF;
++	}
++}
++
++static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
++{
++	struct drm_encoder *encoder;
++	int ret = 0;
++	struct drm_display_mode *mode;
++
++	amdgpu_connector_get_edid(connector);
++	ret = amdgpu_connector_ddc_get_modes(connector);
++	if (ret > 0) {
++		encoder = amdgpu_connector_best_single_encoder(connector);
++		if (encoder) {
++			amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
++			/* add scaled modes */
++			amdgpu_connector_add_common_modes(encoder, connector);
++		}
++		return ret;
++	}
++
++	encoder = amdgpu_connector_best_single_encoder(connector);
++	if (!encoder)
++		return 0;
++
++	/* we have no EDID modes */
++	mode = amdgpu_connector_lcd_native_mode(encoder);
++	if (mode) {
++		ret = 1;
++		drm_mode_probed_add(connector, mode);
++		/* add the width/height from vbios tables if available */
++		connector->display_info.width_mm = mode->width_mm;
++		connector->display_info.height_mm = mode->height_mm;
++		/* add scaled modes */
++		amdgpu_connector_add_common_modes(encoder, connector);
++	}
++
++	return ret;
++}
++
++static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
++					     struct drm_display_mode *mode)
++{
++	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
++
++	if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
++		return MODE_PANEL;
++
++	if (encoder) {
++		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++		struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++
++		/* AVIVO hardware supports downscaling modes larger than the panel
++		 * to the panel size, but I'm not sure this is desirable.
++		 */
++		if ((mode->hdisplay > native_mode->hdisplay) ||
++		    (mode->vdisplay > native_mode->vdisplay))
++			return MODE_PANEL;
++
++		/* if scaling is disabled, block non-native modes */
++		if (amdgpu_encoder->rmx_type == RMX_OFF) {
++			if ((mode->hdisplay != native_mode->hdisplay) ||
++			    (mode->vdisplay != native_mode->vdisplay))
++				return MODE_PANEL;
++		}
++	}
++
++	return MODE_OK;
++}
++
++static enum drm_connector_status
++amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
++	enum drm_connector_status ret = connector_status_disconnected;
++	int r;
++
++	r = pm_runtime_get_sync(connector->dev->dev);
++	if (r < 0)
++		return connector_status_disconnected;
++
++	if (encoder) {
++		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++		struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++
++		/* check if panel is valid */
++		if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
++			ret = connector_status_connected;
++
++	}
++
++	/* check for edid as well */
++	amdgpu_connector_get_edid(connector);
++	if (amdgpu_connector->edid)
++		ret = connector_status_connected;
++	/* check acpi lid status ??? */
++
++	amdgpu_connector_update_scratch_regs(connector, ret);
++	pm_runtime_mark_last_busy(connector->dev->dev);
++	pm_runtime_put_autosuspend(connector->dev->dev);
++	return ret;
++}
++
++static void amdgpu_connector_destroy(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++	if (amdgpu_connector->ddc_bus->has_aux)
++		drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
++	amdgpu_connector_free_edid(connector);
++	kfree(amdgpu_connector->con_priv);
++	drm_connector_unregister(connector);
++	drm_connector_cleanup(connector);
++	kfree(connector);
++}
++
++static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
++					      struct drm_property *property,
++					      uint64_t value)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_encoder *amdgpu_encoder;
++	enum amdgpu_rmx_type rmx_type;
++
++	DRM_DEBUG_KMS("\n");
++	if (property != dev->mode_config.scaling_mode_property)
++		return 0;
++
++	if (connector->encoder)
++		amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
++	else {
++		struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
++		amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
++	}
++
++	switch (value) {
++	case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
++	case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
++	case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
++	default:
++	case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
++	}
++	if (amdgpu_encoder->rmx_type == rmx_type)
++		return 0;
++
++	amdgpu_encoder->rmx_type = rmx_type;
++
++	amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
++	return 0;
++}
++
++
++static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
++	.get_modes = amdgpu_connector_lvds_get_modes,
++	.mode_valid = amdgpu_connector_lvds_mode_valid,
++	.best_encoder = amdgpu_connector_best_single_encoder,
++};
++
++static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
++	.dpms = drm_helper_connector_dpms,
++	.detect = amdgpu_connector_lvds_detect,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.destroy = amdgpu_connector_destroy,
++	.set_property = amdgpu_connector_set_lcd_property,
++};
++
++static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
++{
++	int ret;
++
++	amdgpu_connector_get_edid(connector);
++	ret = amdgpu_connector_ddc_get_modes(connector);
++
++	return ret;
++}
++
++static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
++					    struct drm_display_mode *mode)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	/* XXX check mode bandwidth */
++
++	if ((mode->clock / 10) > adev->clock.max_pixel_clock)
++		return MODE_CLOCK_HIGH;
++
++	return MODE_OK;
++}
++
++static enum drm_connector_status
++amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_encoder *encoder;
++	struct drm_encoder_helper_funcs *encoder_funcs;
++	bool dret = false;
++	enum drm_connector_status ret = connector_status_disconnected;
++	int r;
++
++	r = pm_runtime_get_sync(connector->dev->dev);
++	if (r < 0)
++		return connector_status_disconnected;
++
++	encoder = amdgpu_connector_best_single_encoder(connector);
++	if (!encoder)
++		ret = connector_status_disconnected;
++
++	if (amdgpu_connector->ddc_bus)
++		dret = amdgpu_ddc_probe(amdgpu_connector, false);
++	if (dret) {
++		amdgpu_connector->detected_by_load = false;
++		amdgpu_connector_free_edid(connector);
++		amdgpu_connector_get_edid(connector);
++
++		if (!amdgpu_connector->edid) {
++			DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
++					connector->name);
++			ret = connector_status_connected;
++		} else {
++			amdgpu_connector->use_digital =
++				!!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
++
++			/* some oems have boards with separate digital and analog connectors
++			 * with a shared ddc line (often vga + hdmi)
++			 */
++			if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
++				amdgpu_connector_free_edid(connector);
++				ret = connector_status_disconnected;
++			} else {
++				ret = connector_status_connected;
++			}
++		}
++	} else {
++
++		/* if we aren't forcing don't do destructive polling */
++		if (!force) {
++			/* only return the previous status if we last
++			 * detected a monitor via load.
++			 */
++			if (amdgpu_connector->detected_by_load)
++				ret = connector->status;
++			goto out;
++		}
++
++		if (amdgpu_connector->dac_load_detect && encoder) {
++			encoder_funcs = encoder->helper_private;
++			ret = encoder_funcs->detect(encoder, connector);
++			if (ret != connector_status_disconnected)
++				amdgpu_connector->detected_by_load = true;
++		}
++	}
++
++	amdgpu_connector_update_scratch_regs(connector, ret);
++
++out:
++	pm_runtime_mark_last_busy(connector->dev->dev);
++	pm_runtime_put_autosuspend(connector->dev->dev);
++
++	return ret;
++}
++
++static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
++	.get_modes = amdgpu_connector_vga_get_modes,
++	.mode_valid = amdgpu_connector_vga_mode_valid,
++	.best_encoder = amdgpu_connector_best_single_encoder,
++};
++
++static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
++	.dpms = drm_helper_connector_dpms,
++	.detect = amdgpu_connector_vga_detect,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.destroy = amdgpu_connector_destroy,
++	.set_property = amdgpu_connector_set_property,
++};
++
++static bool
++amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	enum drm_connector_status status;
++
++	if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
++		if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
++			status = connector_status_connected;
++		else
++			status = connector_status_disconnected;
++		if (connector->status == status)
++			return true;
++	}
++
++	return false;
++}
++
++/*
++ * DVI is complicated
++ * Do a DDC probe, if DDC probe passes, get the full EDID so
++ * we can do analog/digital monitor detection at this point.
++ * If the monitor is an analog monitor or we got no DDC,
++ * we need to find the DAC encoder object for this connector.
++ * If we got no DDC, we do load detection on the DAC encoder object.
++ * If we got analog DDC or load detection passes on the DAC encoder
++ * we have to check if this analog encoder is shared with anyone else (TV)
++ * if its shared we have to set the other connector to disconnected.
++ */
++static enum drm_connector_status
++amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_encoder *encoder = NULL;
++	struct drm_encoder_helper_funcs *encoder_funcs;
++	int i, r;
++	enum drm_connector_status ret = connector_status_disconnected;
++	bool dret = false, broken_edid = false;
++
++	r = pm_runtime_get_sync(connector->dev->dev);
++	if (r < 0)
++		return connector_status_disconnected;
++
++	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
++		ret = connector->status;
++		goto exit;
++	}
++
++	if (amdgpu_connector->ddc_bus)
++		dret = amdgpu_ddc_probe(amdgpu_connector, false);
++	if (dret) {
++		amdgpu_connector->detected_by_load = false;
++		amdgpu_connector_free_edid(connector);
++		amdgpu_connector_get_edid(connector);
++
++		if (!amdgpu_connector->edid) {
++			DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
++					connector->name);
++			ret = connector_status_connected;
++			broken_edid = true; /* defer use_digital to later */
++		} else {
++			amdgpu_connector->use_digital =
++				!!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
++
++			/* some oems have boards with separate digital and analog connectors
++			 * with a shared ddc line (often vga + hdmi)
++			 */
++			if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
++				amdgpu_connector_free_edid(connector);
++				ret = connector_status_disconnected;
++			} else {
++				ret = connector_status_connected;
++			}
++
++			/* This gets complicated.  We have boards with VGA + HDMI with a
++			 * shared DDC line and we have boards with DVI-D + HDMI with a shared
++			 * DDC line.  The latter is more complex because with DVI<->HDMI adapters
++			 * you don't really know what's connected to which port as both are digital.
++			 */
++			if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
++				struct drm_connector *list_connector;
++				struct amdgpu_connector *list_amdgpu_connector;
++				list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
++					if (connector == list_connector)
++						continue;
++					list_amdgpu_connector = to_amdgpu_connector(list_connector);
++					if (list_amdgpu_connector->shared_ddc &&
++					    (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
++					     amdgpu_connector->ddc_bus->rec.i2c_id)) {
++						/* cases where both connectors are digital */
++						if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
++							/* hpd is our only option in this case */
++							if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
++								amdgpu_connector_free_edid(connector);
++								ret = connector_status_disconnected;
++							}
++						}
++					}
++				}
++			}
++		}
++	}
++
++	if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
++		goto out;
++
++	/* DVI-D and HDMI-A are digital only */
++	if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
++	    (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
++		goto out;
++
++	/* if we aren't forcing don't do destructive polling */
++	if (!force) {
++		/* only return the previous status if we last
++		 * detected a monitor via load.
++		 */
++		if (amdgpu_connector->detected_by_load)
++			ret = connector->status;
++		goto out;
++	}
++
++	/* find analog encoder */
++	if (amdgpu_connector->dac_load_detect) {
++		for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++			if (connector->encoder_ids[i] == 0)
++				break;
++
++			encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
++			if (!encoder)
++				continue;
++
++			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
++			    encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
++				continue;
++
++			encoder_funcs = encoder->helper_private;
++			if (encoder_funcs->detect) {
++				if (!broken_edid) {
++					if (ret != connector_status_connected) {
++						/* deal with analog monitors without DDC */
++						ret = encoder_funcs->detect(encoder, connector);
++						if (ret == connector_status_connected) {
++							amdgpu_connector->use_digital = false;
++						}
++						if (ret != connector_status_disconnected)
++							amdgpu_connector->detected_by_load = true;
++					}
++				} else {
++					enum drm_connector_status lret;
++					/* assume digital unless load detected otherwise */
++					amdgpu_connector->use_digital = true;
++					lret = encoder_funcs->detect(encoder, connector);
++					DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
++					if (lret == connector_status_connected)
++						amdgpu_connector->use_digital = false;
++				}
++				break;
++			}
++		}
++	}
++
++out:
++	/* updated in get modes as well since we need to know if it's analog or digital */
++	amdgpu_connector_update_scratch_regs(connector, ret);
++
++exit:
++	pm_runtime_mark_last_busy(connector->dev->dev);
++	pm_runtime_put_autosuspend(connector->dev->dev);
++
++	return ret;
++}
++
++/* okay need to be smart in here about which encoder to pick */
++static struct drm_encoder *
++amdgpu_connector_dvi_encoder(struct drm_connector *connector)
++{
++	int enc_id = connector->encoder_ids[0];
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_encoder *encoder;
++	int i;
++	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++		if (connector->encoder_ids[i] == 0)
++			break;
++
++		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
++		if (!encoder)
++			continue;
++
++		if (amdgpu_connector->use_digital == true) {
++			if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
++				return encoder;
++		} else {
++			if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
++			    encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
++				return encoder;
++		}
++	}
++
++	/* see if we have a default encoder  TODO */
++
++	/* then check use digitial */
++	/* pick the first one */
++	if (enc_id)
++		return drm_encoder_find(connector->dev, enc_id);
++	return NULL;
++}
++
++static void amdgpu_connector_dvi_force(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	if (connector->force == DRM_FORCE_ON)
++		amdgpu_connector->use_digital = false;
++	if (connector->force == DRM_FORCE_ON_DIGITAL)
++		amdgpu_connector->use_digital = true;
++}
++
++static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
++					    struct drm_display_mode *mode)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++	/* XXX check mode bandwidth */
++
++	if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
++		if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
++		    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
++		    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
++			return MODE_OK;
++		} else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++			/* HDMI 1.3+ supports max clock of 340 Mhz */
++			if (mode->clock > 340000)
++				return MODE_CLOCK_HIGH;
++			else
++				return MODE_OK;
++		} else {
++			return MODE_CLOCK_HIGH;
++		}
++	}
++
++	/* check against the max pixel clock */
++	if ((mode->clock / 10) > adev->clock.max_pixel_clock)
++		return MODE_CLOCK_HIGH;
++
++	return MODE_OK;
++}
++
++static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
++	.get_modes = amdgpu_connector_vga_get_modes,
++	.mode_valid = amdgpu_connector_dvi_mode_valid,
++	.best_encoder = amdgpu_connector_dvi_encoder,
++};
++
++static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
++	.dpms = drm_helper_connector_dpms,
++	.detect = amdgpu_connector_dvi_detect,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.set_property = amdgpu_connector_set_property,
++	.destroy = amdgpu_connector_destroy,
++	.force = amdgpu_connector_dvi_force,
++};
++
++static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
++	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
++	int ret;
++
++	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
++	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
++		struct drm_display_mode *mode;
++
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
++			if (!amdgpu_dig_connector->edp_on)
++				amdgpu_atombios_encoder_set_edp_panel_power(connector,
++								     ATOM_TRANSMITTER_ACTION_POWER_ON);
++			amdgpu_connector_get_edid(connector);
++			ret = amdgpu_connector_ddc_get_modes(connector);
++			if (!amdgpu_dig_connector->edp_on)
++				amdgpu_atombios_encoder_set_edp_panel_power(connector,
++								     ATOM_TRANSMITTER_ACTION_POWER_OFF);
++		} else {
++			/* need to setup ddc on the bridge */
++			if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++			    ENCODER_OBJECT_ID_NONE) {
++				if (encoder)
++					amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
++			}
++			amdgpu_connector_get_edid(connector);
++			ret = amdgpu_connector_ddc_get_modes(connector);
++		}
++
++		if (ret > 0) {
++			if (encoder) {
++				amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
++				/* add scaled modes */
++				amdgpu_connector_add_common_modes(encoder, connector);
++			}
++			return ret;
++		}
++
++		if (!encoder)
++			return 0;
++
++		/* we have no EDID modes */
++		mode = amdgpu_connector_lcd_native_mode(encoder);
++		if (mode) {
++			ret = 1;
++			drm_mode_probed_add(connector, mode);
++			/* add the width/height from vbios tables if available */
++			connector->display_info.width_mm = mode->width_mm;
++			connector->display_info.height_mm = mode->height_mm;
++			/* add scaled modes */
++			amdgpu_connector_add_common_modes(encoder, connector);
++		}
++	} else {
++		/* need to setup ddc on the bridge */
++		if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++			ENCODER_OBJECT_ID_NONE) {
++			if (encoder)
++				amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
++		}
++		amdgpu_connector_get_edid(connector);
++		ret = amdgpu_connector_ddc_get_modes(connector);
++
++		amdgpu_get_native_mode(connector);
++	}
++
++	return ret;
++}
++
++u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
++{
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++	int i;
++
++	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++		if (connector->encoder_ids[i] == 0)
++			break;
++
++		encoder = drm_encoder_find(connector->dev,
++					connector->encoder_ids[i]);
++		if (!encoder)
++			continue;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++		switch (amdgpu_encoder->encoder_id) {
++		case ENCODER_OBJECT_ID_TRAVIS:
++		case ENCODER_OBJECT_ID_NUTMEG:
++			return amdgpu_encoder->encoder_id;
++		default:
++			break;
++		}
++	}
++
++	return ENCODER_OBJECT_ID_NONE;
++}
++
++static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
++{
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++	int i;
++	bool found = false;
++
++	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++		if (connector->encoder_ids[i] == 0)
++			break;
++		encoder = drm_encoder_find(connector->dev,
++					connector->encoder_ids[i]);
++		if (!encoder)
++			continue;
++
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++		if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
++			found = true;
++	}
++
++	return found;
++}
++
++bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if ((adev->clock.default_dispclk >= 53900) &&
++	    amdgpu_connector_encoder_is_hbr2(connector)) {
++		return true;
++	}
++
++	return false;
++}
++
++static enum drm_connector_status
++amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	enum drm_connector_status ret = connector_status_disconnected;
++	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
++	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
++	int r;
++
++	r = pm_runtime_get_sync(connector->dev->dev);
++	if (r < 0)
++		return connector_status_disconnected;
++
++	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
++		ret = connector->status;
++		goto out;
++	}
++
++	amdgpu_connector_free_edid(connector);
++
++	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
++	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
++		if (encoder) {
++			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++			struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++
++			/* check if panel is valid */
++			if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
++				ret = connector_status_connected;
++		}
++		/* eDP is always DP */
++		amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
++		if (!amdgpu_dig_connector->edp_on)
++			amdgpu_atombios_encoder_set_edp_panel_power(connector,
++							     ATOM_TRANSMITTER_ACTION_POWER_ON);
++		if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
++			ret = connector_status_connected;
++		if (!amdgpu_dig_connector->edp_on)
++			amdgpu_atombios_encoder_set_edp_panel_power(connector,
++							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
++	} else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
++		   ENCODER_OBJECT_ID_NONE) {
++		/* DP bridges are always DP */
++		amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
++		/* get the DPCD from the bridge */
++		amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
++
++		if (encoder) {
++			/* setup ddc on the bridge */
++			amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
++			/* bridge chips are always aux */
++			if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
++				ret = connector_status_connected;
++			else if (amdgpu_connector->dac_load_detect) { /* try load detection */
++				struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
++				ret = encoder_funcs->detect(encoder, connector);
++			}
++		}
++	} else {
++		amdgpu_dig_connector->dp_sink_type =
++			amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
++		if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
++			ret = connector_status_connected;
++			if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
++				amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
++		} else {
++			if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
++				if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
++					ret = connector_status_connected;
++			} else {
++				/* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
++				if (amdgpu_ddc_probe(amdgpu_connector, false))
++					ret = connector_status_connected;
++			}
++		}
++	}
++
++	amdgpu_connector_update_scratch_regs(connector, ret);
++out:
++	pm_runtime_mark_last_busy(connector->dev->dev);
++	pm_runtime_put_autosuspend(connector->dev->dev);
++
++	return ret;
++}
++
++static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
++					   struct drm_display_mode *mode)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
++
++	/* XXX check mode bandwidth */
++
++	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
++	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
++		struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
++
++		if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
++			return MODE_PANEL;
++
++		if (encoder) {
++			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++			struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++
++			/* AVIVO hardware supports downscaling modes larger than the panel
++			 * to the panel size, but I'm not sure this is desirable.
++			 */
++			if ((mode->hdisplay > native_mode->hdisplay) ||
++			    (mode->vdisplay > native_mode->vdisplay))
++				return MODE_PANEL;
++
++			/* if scaling is disabled, block non-native modes */
++			if (amdgpu_encoder->rmx_type == RMX_OFF) {
++				if ((mode->hdisplay != native_mode->hdisplay) ||
++				    (mode->vdisplay != native_mode->vdisplay))
++					return MODE_PANEL;
++			}
++		}
++		return MODE_OK;
++	} else {
++		if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
++		    (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
++			return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
++		} else {
++			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++				/* HDMI 1.3+ supports max clock of 340 Mhz */
++				if (mode->clock > 340000)
++					return MODE_CLOCK_HIGH;
++			} else {
++				if (mode->clock > 165000)
++					return MODE_CLOCK_HIGH;
++			}
++		}
++	}
++
++	return MODE_OK;
++}
++
++static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
++	.get_modes = amdgpu_connector_dp_get_modes,
++	.mode_valid = amdgpu_connector_dp_mode_valid,
++	.best_encoder = amdgpu_connector_dvi_encoder,
++};
++
++static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
++	.dpms = drm_helper_connector_dpms,
++	.detect = amdgpu_connector_dp_detect,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.set_property = amdgpu_connector_set_property,
++	.destroy = amdgpu_connector_destroy,
++	.force = amdgpu_connector_dvi_force,
++};
++
++static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
++	.dpms = drm_helper_connector_dpms,
++	.detect = amdgpu_connector_dp_detect,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.set_property = amdgpu_connector_set_lcd_property,
++	.destroy = amdgpu_connector_destroy,
++	.force = amdgpu_connector_dvi_force,
++};
++
++void
++amdgpu_connector_add(struct amdgpu_device *adev,
++		      uint32_t connector_id,
++		      uint32_t supported_device,
++		      int connector_type,
++		      struct amdgpu_i2c_bus_rec *i2c_bus,
++		      uint16_t connector_object_id,
++		      struct amdgpu_hpd *hpd,
++		      struct amdgpu_router *router)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++	struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++	uint32_t subpixel_order = SubPixelNone;
++	bool shared_ddc = false;
++	bool is_dp_bridge = false;
++	bool has_aux = false;
++
++	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
++		return;
++
++	/* see if we already added it */
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		amdgpu_connector = to_amdgpu_connector(connector);
++		if (amdgpu_connector->connector_id == connector_id) {
++			amdgpu_connector->devices |= supported_device;
++			return;
++		}
++		if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
++			if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
++				amdgpu_connector->shared_ddc = true;
++				shared_ddc = true;
++			}
++			if (amdgpu_connector->router_bus && router->ddc_valid &&
++			    (amdgpu_connector->router.router_id == router->router_id)) {
++				amdgpu_connector->shared_ddc = false;
++				shared_ddc = false;
++			}
++		}
++	}
++
++	/* check if it's a dp bridge */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++		if (amdgpu_encoder->devices & supported_device) {
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_TRAVIS:
++			case ENCODER_OBJECT_ID_NUTMEG:
++				is_dp_bridge = true;
++				break;
++			default:
++				break;
++			}
++		}
++	}
++
++	amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
++	if (!amdgpu_connector)
++		return;
++
++	connector = &amdgpu_connector->base;
++
++	amdgpu_connector->connector_id = connector_id;
++	amdgpu_connector->devices = supported_device;
++	amdgpu_connector->shared_ddc = shared_ddc;
++	amdgpu_connector->connector_object_id = connector_object_id;
++	amdgpu_connector->hpd = *hpd;
++
++	amdgpu_connector->router = *router;
++	if (router->ddc_valid || router->cd_valid) {
++		amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
++		if (!amdgpu_connector->router_bus)
++			DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
++	}
++
++	if (is_dp_bridge) {
++		amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
++		if (!amdgpu_dig_connector)
++			goto failed;
++		amdgpu_connector->con_priv = amdgpu_dig_connector;
++		if (i2c_bus->valid) {
++			amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++			if (amdgpu_connector->ddc_bus)
++				has_aux = true;
++			else
++				DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++		}
++		switch (connector_type) {
++		case DRM_MODE_CONNECTOR_VGA:
++		case DRM_MODE_CONNECTOR_DVIA:
++		default:
++			drm_connector_init(dev, &amdgpu_connector->base,
++					   &amdgpu_connector_dp_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base,
++						 &amdgpu_connector_dp_helper_funcs);
++			connector->interlace_allowed = true;
++			connector->doublescan_allowed = true;
++			amdgpu_connector->dac_load_detect = true;
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.load_detect_property,
++						      1);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++			break;
++		case DRM_MODE_CONNECTOR_DVII:
++		case DRM_MODE_CONNECTOR_DVID:
++		case DRM_MODE_CONNECTOR_HDMIA:
++		case DRM_MODE_CONNECTOR_HDMIB:
++		case DRM_MODE_CONNECTOR_DisplayPort:
++			drm_connector_init(dev, &amdgpu_connector->base,
++					   &amdgpu_connector_dp_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base,
++						 &amdgpu_connector_dp_helper_funcs);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.underscan_property,
++						      UNDERSCAN_OFF);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.underscan_hborder_property,
++						      0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.underscan_vborder_property,
++						      0);
++
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.dither_property,
++						   AMDGPU_FMT_DITHER_DISABLE);
++
++			if (amdgpu_audio != 0)
++				drm_object_attach_property(&amdgpu_connector->base.base,
++							   adev->mode_info.audio_property,
++							   AMDGPU_AUDIO_AUTO);
++
++			subpixel_order = SubPixelHorizontalRGB;
++			connector->interlace_allowed = true;
++			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
++				connector->doublescan_allowed = true;
++			else
++				connector->doublescan_allowed = false;
++			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
++				amdgpu_connector->dac_load_detect = true;
++				drm_object_attach_property(&amdgpu_connector->base.base,
++							      adev->mode_info.load_detect_property,
++							      1);
++			}
++			break;
++		case DRM_MODE_CONNECTOR_LVDS:
++		case DRM_MODE_CONNECTOR_eDP:
++			drm_connector_init(dev, &amdgpu_connector->base,
++					   &amdgpu_connector_edp_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base,
++						 &amdgpu_connector_dp_helper_funcs);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      dev->mode_config.scaling_mode_property,
++						      DRM_MODE_SCALE_FULLSCREEN);
++			subpixel_order = SubPixelHorizontalRGB;
++			connector->interlace_allowed = false;
++			connector->doublescan_allowed = false;
++			break;
++		}
++	} else {
++		switch (connector_type) {
++		case DRM_MODE_CONNECTOR_VGA:
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (!amdgpu_connector->ddc_bus)
++					DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			amdgpu_connector->dac_load_detect = true;
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.load_detect_property,
++						      1);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++			/* no HPD on analog connectors */
++			amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
++			connector->polled = DRM_CONNECTOR_POLL_CONNECT;
++			connector->interlace_allowed = true;
++			connector->doublescan_allowed = true;
++			break;
++		case DRM_MODE_CONNECTOR_DVIA:
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (!amdgpu_connector->ddc_bus)
++					DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			amdgpu_connector->dac_load_detect = true;
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.load_detect_property,
++						      1);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++			/* no HPD on analog connectors */
++			amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
++			connector->interlace_allowed = true;
++			connector->doublescan_allowed = true;
++			break;
++		case DRM_MODE_CONNECTOR_DVII:
++		case DRM_MODE_CONNECTOR_DVID:
++			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
++			if (!amdgpu_dig_connector)
++				goto failed;
++			amdgpu_connector->con_priv = amdgpu_dig_connector;
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (!amdgpu_connector->ddc_bus)
++					DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			subpixel_order = SubPixelHorizontalRGB;
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.coherent_mode_property,
++						      1);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_property,
++						   UNDERSCAN_OFF);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_hborder_property,
++						   0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_vborder_property,
++						   0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++
++			if (amdgpu_audio != 0) {
++				drm_object_attach_property(&amdgpu_connector->base.base,
++							   adev->mode_info.audio_property,
++							   AMDGPU_AUDIO_AUTO);
++			}
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.dither_property,
++						   AMDGPU_FMT_DITHER_DISABLE);
++			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
++				amdgpu_connector->dac_load_detect = true;
++				drm_object_attach_property(&amdgpu_connector->base.base,
++							   adev->mode_info.load_detect_property,
++							   1);
++			}
++			connector->interlace_allowed = true;
++			if (connector_type == DRM_MODE_CONNECTOR_DVII)
++				connector->doublescan_allowed = true;
++			else
++				connector->doublescan_allowed = false;
++			break;
++		case DRM_MODE_CONNECTOR_HDMIA:
++		case DRM_MODE_CONNECTOR_HDMIB:
++			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
++			if (!amdgpu_dig_connector)
++				goto failed;
++			amdgpu_connector->con_priv = amdgpu_dig_connector;
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (!amdgpu_connector->ddc_bus)
++					DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.coherent_mode_property,
++						      1);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_property,
++						   UNDERSCAN_OFF);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_hborder_property,
++						   0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_vborder_property,
++						   0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++			if (amdgpu_audio != 0) {
++				drm_object_attach_property(&amdgpu_connector->base.base,
++							   adev->mode_info.audio_property,
++							   AMDGPU_AUDIO_AUTO);
++			}
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.dither_property,
++						   AMDGPU_FMT_DITHER_DISABLE);
++			subpixel_order = SubPixelHorizontalRGB;
++			connector->interlace_allowed = true;
++			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
++				connector->doublescan_allowed = true;
++			else
++				connector->doublescan_allowed = false;
++			break;
++		case DRM_MODE_CONNECTOR_DisplayPort:
++			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
++			if (!amdgpu_dig_connector)
++				goto failed;
++			amdgpu_connector->con_priv = amdgpu_dig_connector;
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (amdgpu_connector->ddc_bus)
++					has_aux = true;
++				else
++					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			subpixel_order = SubPixelHorizontalRGB;
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      adev->mode_info.coherent_mode_property,
++						      1);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_property,
++						   UNDERSCAN_OFF);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_hborder_property,
++						   0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.underscan_vborder_property,
++						   0);
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   dev->mode_config.scaling_mode_property,
++						   DRM_MODE_SCALE_NONE);
++			if (amdgpu_audio != 0) {
++				drm_object_attach_property(&amdgpu_connector->base.base,
++							   adev->mode_info.audio_property,
++							   AMDGPU_AUDIO_AUTO);
++			}
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						   adev->mode_info.dither_property,
++						   AMDGPU_FMT_DITHER_DISABLE);
++			connector->interlace_allowed = true;
++			/* in theory with a DP to VGA converter... */
++			connector->doublescan_allowed = false;
++			break;
++		case DRM_MODE_CONNECTOR_eDP:
++			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
++			if (!amdgpu_dig_connector)
++				goto failed;
++			amdgpu_connector->con_priv = amdgpu_dig_connector;
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (amdgpu_connector->ddc_bus)
++					has_aux = true;
++				else
++					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      dev->mode_config.scaling_mode_property,
++						      DRM_MODE_SCALE_FULLSCREEN);
++			subpixel_order = SubPixelHorizontalRGB;
++			connector->interlace_allowed = false;
++			connector->doublescan_allowed = false;
++			break;
++		case DRM_MODE_CONNECTOR_LVDS:
++			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
++			if (!amdgpu_dig_connector)
++				goto failed;
++			amdgpu_connector->con_priv = amdgpu_dig_connector;
++			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
++			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
++			if (i2c_bus->valid) {
++				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
++				if (!amdgpu_connector->ddc_bus)
++					DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
++			}
++			drm_object_attach_property(&amdgpu_connector->base.base,
++						      dev->mode_config.scaling_mode_property,
++						      DRM_MODE_SCALE_FULLSCREEN);
++			subpixel_order = SubPixelHorizontalRGB;
++			connector->interlace_allowed = false;
++			connector->doublescan_allowed = false;
++			break;
++		}
++	}
++
++	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
++		if (i2c_bus->valid)
++			connector->polled = DRM_CONNECTOR_POLL_CONNECT;
++	} else
++		connector->polled = DRM_CONNECTOR_POLL_HPD;
++
++	connector->display_info.subpixel_order = subpixel_order;
++	drm_connector_register(connector);
++
++	if (has_aux)
++		amdgpu_atombios_dp_aux_init(amdgpu_connector);
++
++	return;
++
++failed:
++	drm_connector_cleanup(connector);
++	kfree(connector);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
+new file mode 100644
+index 0000000..61fcef1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_CONNECTORS_H__
++#define __AMDGPU_CONNECTORS_H__
++
++struct edid *amdgpu_connector_edid(struct drm_connector *connector);
++void amdgpu_connector_hotplug(struct drm_connector *connector);
++int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);
++u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
++bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector);
++void
++amdgpu_connector_add(struct amdgpu_device *adev,
++		      uint32_t connector_id,
++		      uint32_t supported_device,
++		      int connector_type,
++		      struct amdgpu_i2c_bus_rec *i2c_bus,
++		      uint16_t connector_object_id,
++		      struct amdgpu_hpd *hpd,
++		      struct amdgpu_router *router);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+new file mode 100644
+index 0000000..70a9031
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -0,0 +1,825 @@
++/*
++ * Copyright 2008 Jerome Glisse.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ *    Jerome Glisse <glisse@freedesktop.org>
++ */
++#include <linux/list_sort.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_trace.h"
++
++#define AMDGPU_CS_MAX_PRIORITY		32u
++#define AMDGPU_CS_NUM_BUCKETS		(AMDGPU_CS_MAX_PRIORITY + 1)
++
++/* This is based on the bucket sort with O(n) time complexity.
++ * An item with priority "i" is added to bucket[i]. The lists are then
++ * concatenated in descending order.
++ */
++struct amdgpu_cs_buckets {
++	struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
++};
++
++static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
++{
++	unsigned i;
++
++	for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
++		INIT_LIST_HEAD(&b->bucket[i]);
++}
++
++static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
++				  struct list_head *item, unsigned priority)
++{
++	/* Since buffers which appear sooner in the relocation list are
++	 * likely to be used more often than buffers which appear later
++	 * in the list, the sort mustn't change the ordering of buffers
++	 * with the same priority, i.e. it must be stable.
++	 */
++	list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
++}
++
++static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
++				       struct list_head *out_list)
++{
++	unsigned i;
++
++	/* Connect the sorted buckets in the output list. */
++	for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
++		list_splice(&b->bucket[i], out_list);
++	}
++}
++
++int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
++		       u32 ip_instance, u32 ring,
++		       struct amdgpu_ring **out_ring)
++{
++	/* Right now all IPs have only one instance - multiple rings. */
++	if (ip_instance != 0) {
++		DRM_ERROR("invalid ip instance: %d\n", ip_instance);
++		return -EINVAL;
++	}
++
++	switch (ip_type) {
++	default:
++		DRM_ERROR("unknown ip type: %d\n", ip_type);
++		return -EINVAL;
++	case AMDGPU_HW_IP_GFX:
++		if (ring < adev->gfx.num_gfx_rings) {
++			*out_ring = &adev->gfx.gfx_ring[ring];
++		} else {
++			DRM_ERROR("only %d gfx rings are supported now\n",
++				  adev->gfx.num_gfx_rings);
++			return -EINVAL;
++		}
++		break;
++	case AMDGPU_HW_IP_COMPUTE:
++		if (ring < adev->gfx.num_compute_rings) {
++			*out_ring = &adev->gfx.compute_ring[ring];
++		} else {
++			DRM_ERROR("only %d compute rings are supported now\n",
++				  adev->gfx.num_compute_rings);
++			return -EINVAL;
++		}
++		break;
++	case AMDGPU_HW_IP_DMA:
++		if (ring < 2) {
++			*out_ring = &adev->sdma[ring].ring;
++		} else {
++			DRM_ERROR("only two SDMA rings are supported\n");
++			return -EINVAL;
++		}
++		break;
++	case AMDGPU_HW_IP_UVD:
++		*out_ring = &adev->uvd.ring;
++		break;
++	case AMDGPU_HW_IP_VCE:
++		if (ring < 2){
++			*out_ring = &adev->vce.ring[ring];
++		} else {
++			DRM_ERROR("only two VCE rings are supported\n");
++			return -EINVAL;
++		}
++		break;
++	}
++	return 0;
++}
++
++int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
++{
++	union drm_amdgpu_cs *cs = data;
++	uint64_t *chunk_array_user;
++	uint64_t *chunk_array = NULL;
++	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
++	unsigned size, i;
++	int r = 0;
++
++	if (!cs->in.num_chunks)
++		goto out;
++
++	p->ctx_id = cs->in.ctx_id;
++	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
++
++	/* get chunks */
++	INIT_LIST_HEAD(&p->validated);
++	chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
++	if (chunk_array == NULL) {
++		r = -ENOMEM;
++		goto out;
++	}
++
++	chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks);
++	if (copy_from_user(chunk_array, chunk_array_user,
++			   sizeof(uint64_t)*cs->in.num_chunks)) {
++		r = -EFAULT;
++		goto out;
++	}
++
++	p->nchunks = cs->in.num_chunks;
++	p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk),
++			    GFP_KERNEL);
++	if (p->chunks == NULL) {
++		r = -ENOMEM;
++		goto out;
++	}
++
++	for (i = 0; i < p->nchunks; i++) {
++		struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
++		struct drm_amdgpu_cs_chunk user_chunk;
++		uint32_t __user *cdata;
++
++		chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
++		if (copy_from_user(&user_chunk, chunk_ptr,
++				       sizeof(struct drm_amdgpu_cs_chunk))) {
++			r = -EFAULT;
++			goto out;
++		}
++		p->chunks[i].chunk_id = user_chunk.chunk_id;
++		p->chunks[i].length_dw = user_chunk.length_dw;
++		if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_IB)
++			p->num_ibs++;
++
++		size = p->chunks[i].length_dw;
++		cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
++		p->chunks[i].user_ptr = cdata;
++
++		p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
++		if (p->chunks[i].kdata == NULL) {
++			r = -ENOMEM;
++			goto out;
++		}
++		size *= sizeof(uint32_t);
++		if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
++			r = -EFAULT;
++			goto out;
++		}
++
++		if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_FENCE) {
++			size = sizeof(struct drm_amdgpu_cs_chunk_fence);
++			if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
++				uint32_t handle;
++				struct drm_gem_object *gobj;
++				struct drm_amdgpu_cs_chunk_fence *fence_data;
++
++				fence_data = (void *)p->chunks[i].kdata;
++				handle = fence_data->handle;
++				gobj = drm_gem_object_lookup(p->adev->ddev,
++							     p->filp, handle);
++				if (gobj == NULL) {
++					r = -EINVAL;
++					goto out;
++				}
++
++				p->uf.bo = gem_to_amdgpu_bo(gobj);
++				p->uf.offset = fence_data->offset;
++			} else {
++				r = -EINVAL;
++				goto out;
++			}
++		}
++	}
++
++	p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
++	if (!p->ibs) {
++		r = -ENOMEM;
++		goto out;
++	}
++
++	p->ib_bos = kcalloc(p->num_ibs, sizeof(struct amdgpu_bo_list_entry),
++			    GFP_KERNEL);
++	if (!p->ib_bos)
++		r = -ENOMEM;
++
++out:
++	kfree(chunk_array);
++	return r;
++}
++
++/* Returns how many bytes TTM can move per IB.
++ */
++static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
++{
++	u64 real_vram_size = adev->mc.real_vram_size;
++	u64 vram_usage = atomic64_read(&adev->vram_usage);
++
++	/* This function is based on the current VRAM usage.
++	 *
++	 * - If all of VRAM is free, allow relocating the number of bytes that
++	 *   is equal to 1/4 of the size of VRAM for this IB.
++
++	 * - If more than one half of VRAM is occupied, only allow relocating
++	 *   1 MB of data for this IB.
++	 *
++	 * - From 0 to one half of used VRAM, the threshold decreases
++	 *   linearly.
++	 *         __________________
++	 * 1/4 of -|\               |
++	 * VRAM    | \              |
++	 *         |  \             |
++	 *         |   \            |
++	 *         |    \           |
++	 *         |     \          |
++	 *         |      \         |
++	 *         |       \________|1 MB
++	 *         |----------------|
++	 *    VRAM 0 %             100 %
++	 *         used            used
++	 *
++	 * Note: It's a threshold, not a limit. The threshold must be crossed
++	 * for buffer relocations to stop, so any buffer of an arbitrary size
++	 * can be moved as long as the threshold isn't crossed before
++	 * the relocation takes place. We don't want to disable buffer
++	 * relocations completely.
++	 *
++	 * The idea is that buffers should be placed in VRAM at creation time
++	 * and TTM should only do a minimum number of relocations during
++	 * command submission. In practice, you need to submit at least
++	 * a dozen IBs to move all buffers to VRAM if they are in GTT.
++	 *
++	 * Also, things can get pretty crazy under memory pressure and actual
++	 * VRAM usage can change a lot, so playing safe even at 50% does
++	 * consistently increase performance.
++	 */
++
++	u64 half_vram = real_vram_size >> 1;
++	u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
++	u64 bytes_moved_threshold = half_free_vram >> 1;
++	return max(bytes_moved_threshold, 1024*1024ull);
++}
++
++int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
++{
++	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
++	struct amdgpu_vm *vm = &fpriv->vm;
++	struct amdgpu_device *adev = p->adev;
++	struct amdgpu_bo_list_entry *lobj;
++	struct list_head duplicates;
++	struct amdgpu_bo *bo;
++	u64 bytes_moved = 0, initial_bytes_moved;
++	u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
++	int r;
++
++	INIT_LIST_HEAD(&duplicates);
++	r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
++	if (unlikely(r != 0)) {
++		return r;
++	}
++
++	list_for_each_entry(lobj, &p->validated, tv.head) {
++		bo = lobj->robj;
++		if (!bo->pin_count) {
++			u32 domain = lobj->prefered_domains;
++			u32 current_domain =
++				amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
++
++			/* Check if this buffer will be moved and don't move it
++			 * if we have moved too many buffers for this IB already.
++			 *
++			 * Note that this allows moving at least one buffer of
++			 * any size, because it doesn't take the current "bo"
++			 * into account. We don't want to disallow buffer moves
++			 * completely.
++			 */
++			if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
++			    (domain & current_domain) == 0 && /* will be moved */
++			    bytes_moved > bytes_moved_threshold) {
++				/* don't move it */
++				domain = current_domain;
++			}
++
++		retry:
++			amdgpu_ttm_placement_from_domain(bo, domain);
++			initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
++			r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
++			bytes_moved += atomic64_read(&adev->num_bytes_moved) -
++				       initial_bytes_moved;
++
++			if (unlikely(r)) {
++				if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
++					domain = lobj->allowed_domains;
++					goto retry;
++				}
++				ttm_eu_backoff_reservation(&p->ticket, &p->validated);
++				return r;
++			}
++		}
++		lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
++	}
++	return 0;
++}
++
++static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
++{
++	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
++	struct amdgpu_cs_buckets buckets;
++	bool need_mmap_lock;
++	int i, r;
++
++	if (p->bo_list == NULL)
++		return 0;
++
++	need_mmap_lock = p->bo_list->has_userptr;
++	amdgpu_cs_buckets_init(&buckets);
++	for (i = 0; i < p->bo_list->num_entries; i++)
++		amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
++					      p->bo_list->array[i].priority);
++
++	amdgpu_cs_buckets_get_list(&buckets, &p->validated);
++	p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
++				      &p->validated);
++
++	for (i = 0; i < p->num_ibs; i++) {
++		if (!p->ib_bos[i].robj)
++			continue;
++
++		list_add(&p->ib_bos[i].tv.head, &p->validated);
++	}
++
++	if (need_mmap_lock)
++		down_read(&current->mm->mmap_sem);
++
++	r = amdgpu_cs_list_validate(p);
++
++	if (need_mmap_lock)
++		up_read(&current->mm->mmap_sem);
++
++	return r;
++}
++
++static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
++{
++	struct amdgpu_bo_list_entry *e;
++	int r;
++
++	list_for_each_entry(e, &p->validated, tv.head) {
++		struct reservation_object *resv = e->robj->tbo.resv;
++		r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
++
++		if (r)
++			return r;
++	}
++	return 0;
++}
++
++static int cmp_size_smaller_first(void *priv, struct list_head *a,
++				  struct list_head *b)
++{
++	struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
++	struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
++
++	/* Sort A before B if A is smaller. */
++	return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
++}
++
++/**
++ * cs_parser_fini() - clean parser states
++ * @parser:	parser structure holding parsing context.
++ * @error:	error number
++ *
++ * If error is set than unvalidate buffer, otherwise just free memory
++ * used by parsing context.
++ **/
++static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
++{
++	unsigned i;
++
++	if (!error) {
++		/* Sort the buffer list from the smallest to largest buffer,
++		 * which affects the order of buffers in the LRU list.
++		 * This assures that the smallest buffers are added first
++		 * to the LRU list, so they are likely to be later evicted
++		 * first, instead of large buffers whose eviction is more
++		 * expensive.
++		 *
++		 * This slightly lowers the number of bytes moved by TTM
++		 * per frame under memory pressure.
++		 */
++		list_sort(NULL, &parser->validated, cmp_size_smaller_first);
++
++		ttm_eu_fence_buffer_objects(&parser->ticket,
++				&parser->validated,
++				&parser->ibs[parser->num_ibs-1].fence->base);
++	} else if (backoff) {
++		ttm_eu_backoff_reservation(&parser->ticket,
++					   &parser->validated);
++	}
++
++	if (parser->bo_list)
++		amdgpu_bo_list_put(parser->bo_list);
++	drm_free_large(parser->vm_bos);
++	for (i = 0; i < parser->nchunks; i++)
++		drm_free_large(parser->chunks[i].kdata);
++	kfree(parser->chunks);
++	for (i = 0; i < parser->num_ibs; i++) {
++		struct amdgpu_bo *bo = parser->ib_bos[i].robj;
++		amdgpu_ib_free(parser->adev, &parser->ibs[i]);
++
++		if (bo)
++			drm_gem_object_unreference_unlocked(&bo->gem_base);
++	}
++	kfree(parser->ibs);
++	kfree(parser->ib_bos);
++	if (parser->uf.bo)
++		drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
++}
++
++static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
++				   struct amdgpu_vm *vm)
++{
++	struct amdgpu_device *adev = p->adev;
++	struct amdgpu_bo_va *bo_va;
++	struct amdgpu_bo *bo;
++	int i, r;
++
++	r = amdgpu_vm_update_page_directory(adev, vm);
++	if (r)
++		return r;
++
++	r = amdgpu_vm_clear_freed(adev, vm);
++	if (r)
++		return r;
++
++	if (p->bo_list) {
++		for (i = 0; i < p->bo_list->num_entries; i++) {
++			/* ignore duplicates */
++			bo = p->bo_list->array[i].robj;
++			if (!bo)
++				continue;
++
++			bo_va = p->bo_list->array[i].bo_va;
++			if (bo_va == NULL)
++				continue;
++
++			r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
++			if (r)
++				return r;
++
++			amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
++		}
++	}
++
++	for (i = 0; i < p->num_ibs; i++) {
++		bo = p->ib_bos[i].robj;
++		if (!bo)
++			continue;
++
++		bo_va = p->ib_bos[i].bo_va;
++		if (!bo_va)
++			continue;
++
++		r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
++		if (r)
++			return r;
++
++		amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
++	}
++	return amdgpu_vm_clear_invalids(adev, vm);
++}
++
++static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
++				 struct amdgpu_cs_parser *parser)
++{
++	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
++	struct amdgpu_vm *vm = &fpriv->vm;
++	struct amdgpu_ring *ring;
++	int i, r;
++
++	if (parser->num_ibs == 0)
++		return 0;
++
++	/* Only for UVD/VCE VM emulation */
++	for (i = 0; i < parser->num_ibs; i++) {
++		ring = parser->ibs[i].ring;
++		if (ring->funcs->parse_cs) {
++			r = amdgpu_ring_parse_cs(ring, parser, i);
++			if (r)
++				return r;
++		}
++	}
++
++	mutex_lock(&vm->mutex);
++	r = amdgpu_bo_vm_update_pte(parser, vm);
++	if (r) {
++		goto out;
++	}
++	amdgpu_cs_sync_rings(parser);
++
++	r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
++			       parser->filp);
++
++out:
++	mutex_unlock(&vm->mutex);
++	return r;
++}
++
++static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
++{
++	if (r == -EDEADLK) {
++		r = amdgpu_gpu_reset(adev);
++		if (!r)
++			r = -EAGAIN;
++	}
++	return r;
++}
++
++static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
++			     struct amdgpu_cs_parser *parser)
++{
++	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
++	struct amdgpu_vm *vm = &fpriv->vm;
++	int i, j;
++	int r;
++
++	for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
++		struct amdgpu_cs_chunk *chunk;
++		struct amdgpu_ib *ib;
++		struct drm_amdgpu_cs_chunk_ib *chunk_ib;
++		struct amdgpu_bo_list_entry *ib_bo;
++		struct amdgpu_ring *ring;
++		struct drm_gem_object *gobj;
++		struct amdgpu_bo *aobj;
++		void *kptr;
++
++		chunk = &parser->chunks[i];
++		ib = &parser->ibs[j];
++		chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
++
++		if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
++			continue;
++
++		gobj = drm_gem_object_lookup(adev->ddev, parser->filp, chunk_ib->handle);
++		if (gobj == NULL)
++			return -ENOENT;
++		aobj = gem_to_amdgpu_bo(gobj);
++
++		r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
++				       chunk_ib->ip_instance, chunk_ib->ring,
++				       &ring);
++		if (r) {
++			drm_gem_object_unreference_unlocked(gobj);
++			return r;
++		}
++
++		if (ring->funcs->parse_cs) {
++			r = amdgpu_bo_reserve(aobj, false);
++			if (r) {
++				drm_gem_object_unreference_unlocked(gobj);
++				return r;
++			}
++
++			r = amdgpu_bo_kmap(aobj, &kptr);
++			if (r) {
++				amdgpu_bo_unreserve(aobj);
++				drm_gem_object_unreference_unlocked(gobj);
++				return r;
++			}
++
++			r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
++			if (r) {
++				DRM_ERROR("Failed to get ib !\n");
++				amdgpu_bo_unreserve(aobj);
++				drm_gem_object_unreference_unlocked(gobj);
++				return r;
++			}
++
++			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
++			amdgpu_bo_kunmap(aobj);
++			amdgpu_bo_unreserve(aobj);
++		} else {
++			r =  amdgpu_ib_get(ring, vm, 0, ib);
++			if (r) {
++				DRM_ERROR("Failed to get ib !\n");
++				drm_gem_object_unreference_unlocked(gobj);
++				return r;
++			}
++
++			ib->gpu_addr = chunk_ib->va_start;
++		}
++		ib->length_dw = chunk_ib->ib_bytes / 4;
++
++		if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
++			ib->is_const_ib = true;
++		if (chunk_ib->flags & AMDGPU_IB_FLAG_GDS)
++			ib->gds_needed = true;
++		if (ib->ring->current_filp != parser->filp) {
++			ib->ring->need_ctx_switch = true;
++			ib->ring->current_filp = parser->filp;
++		}
++
++		ib_bo = &parser->ib_bos[j];
++		ib_bo->robj = aobj;
++		ib_bo->prefered_domains = aobj->initial_domain;
++		ib_bo->allowed_domains = aobj->initial_domain;
++		ib_bo->priority = 0;
++		ib_bo->tv.bo = &aobj->tbo;
++		ib_bo->tv.shared = true;
++		j++;
++	}
++
++	if (!parser->num_ibs)
++		return 0;
++
++	/* add GDS resources to first IB */
++	if (parser->bo_list) {
++		struct amdgpu_bo *gds = parser->bo_list->gds_obj;
++		struct amdgpu_bo *gws = parser->bo_list->gws_obj;
++		struct amdgpu_bo *oa = parser->bo_list->oa_obj;
++		struct amdgpu_ib *ib = &parser->ibs[0];
++
++		if (gds) {
++			ib->gds_base = amdgpu_bo_gpu_offset(gds);
++			ib->gds_size = amdgpu_bo_size(gds);
++		}
++		if (gws) {
++			ib->gws_base = amdgpu_bo_gpu_offset(gws);
++			ib->gws_size = amdgpu_bo_size(gws);
++		}
++		if (oa) {
++			ib->oa_base = amdgpu_bo_gpu_offset(oa);
++			ib->oa_size = amdgpu_bo_size(oa);
++		}
++	}
++
++	/* wrap the last IB with user fence */
++	if (parser->uf.bo) {
++		struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
++
++		/* UVD & VCE fw doesn't support user fences */
++		if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
++		    ib->ring->type == AMDGPU_RING_TYPE_VCE)
++			return -EINVAL;
++
++		ib->user = &parser->uf;
++	}
++
++	return 0;
++}
++
++int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	union drm_amdgpu_cs *cs = data;
++	struct amdgpu_cs_parser parser;
++	int r, i;
++
++	down_read(&adev->exclusive_lock);
++	if (!adev->accel_working) {
++		up_read(&adev->exclusive_lock);
++		return -EBUSY;
++	}
++	/* initialize parser */
++	memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
++	parser.filp = filp;
++	parser.adev = adev;
++	r = amdgpu_cs_parser_init(&parser, data);
++	if (r) {
++		DRM_ERROR("Failed to initialize parser !\n");
++		amdgpu_cs_parser_fini(&parser, r, false);
++		up_read(&adev->exclusive_lock);
++		r = amdgpu_cs_handle_lockup(adev, r);
++		return r;
++	}
++
++	r = amdgpu_cs_ib_fill(adev, &parser);
++	if (!r) {
++		r = amdgpu_cs_parser_relocs(&parser);
++		if (r && r != -ERESTARTSYS)
++			DRM_ERROR("Failed to parse relocation %d!\n", r);
++	}
++
++	if (r) {
++		amdgpu_cs_parser_fini(&parser, r, false);
++		up_read(&adev->exclusive_lock);
++		r = amdgpu_cs_handle_lockup(adev, r);
++		return r;
++	}
++
++	for (i = 0; i < parser.num_ibs; i++)
++		trace_amdgpu_cs(&parser, i);
++
++	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
++	if (r) {
++		goto out;
++	}
++
++	cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq;
++out:
++	amdgpu_cs_parser_fini(&parser, r, true);
++	up_read(&adev->exclusive_lock);
++	r = amdgpu_cs_handle_lockup(adev, r);
++	return r;
++}
++
++/**
++ * amdgpu_cs_wait_ioctl - wait for a command submission to finish
++ *
++ * @dev: drm device
++ * @data: data from userspace
++ * @filp: file private
++ *
++ * Wait for the command submission identified by handle to finish.
++ */
++int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
++			 struct drm_file *filp)
++{
++	union drm_amdgpu_wait_cs *wait = data;
++	struct amdgpu_device *adev = dev->dev_private;
++	uint64_t seq[AMDGPU_MAX_RINGS] = {0};
++	struct amdgpu_ring *ring = NULL;
++	unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
++	long r;
++
++	r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
++			       wait->in.ring, &ring);
++	if (r)
++		return r;
++
++	seq[ring->idx] = wait->in.handle;
++
++	r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout);
++	if (r < 0)
++		return r;
++
++	memset(wait, 0, sizeof(*wait));
++	wait->out.status = (r == 0);
++
++	return 0;
++}
++
++/**
++ * amdgpu_cs_find_bo_va - find bo_va for VM address
++ *
++ * @parser: command submission parser context
++ * @addr: VM address
++ * @bo: resulting BO of the mapping found
++ *
++ * Search the buffer objects in the command submission context for a certain
++ * virtual memory address. Returns allocation structure when found, NULL
++ * otherwise.
++ */
++struct amdgpu_bo_va_mapping *
++amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
++		       uint64_t addr, struct amdgpu_bo **bo)
++{
++	struct amdgpu_bo_list_entry *reloc;
++	struct amdgpu_bo_va_mapping *mapping;
++
++	addr /= AMDGPU_GPU_PAGE_SIZE;
++
++	list_for_each_entry(reloc, &parser->validated, tv.head) {
++		if (!reloc->bo_va)
++			continue;
++
++		list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
++			if (mapping->it.start > addr ||
++			    addr > mapping->it.last)
++				continue;
++
++			*bo = reloc->bo_va->bo;
++			return mapping;
++		}
++	}
++
++	return NULL;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+new file mode 100644
+index 0000000..235010a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -0,0 +1,161 @@
++/*
++ * Copyright 2015 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: monk liu <monk.liu@amd.com>
++ */
++
++#include <drm/drmP.h>
++#include "amdgpu.h"
++
++static void amdgpu_ctx_do_release(struct kref *ref)
++{
++	struct amdgpu_ctx *ctx;
++	struct amdgpu_ctx_mgr *mgr;
++
++	ctx = container_of(ref, struct amdgpu_ctx, refcount);
++	mgr = &ctx->fpriv->ctx_mgr;
++
++	mutex_lock(&mgr->hlock);
++	idr_remove(&mgr->ctx_handles, ctx->id);
++	mutex_unlock(&mgr->hlock);
++	kfree(ctx);
++}
++
++int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t *id, uint32_t flags)
++{
++	int r;
++	struct amdgpu_ctx *ctx;
++	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
++
++	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
++	if (!ctx)
++		return -ENOMEM;
++
++	mutex_lock(&mgr->hlock);
++	r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL);
++	if (r < 0) {
++		mutex_unlock(&mgr->hlock);
++		kfree(ctx);
++		return r;
++	}
++	mutex_unlock(&mgr->hlock);
++	*id = (uint32_t)r;
++
++	memset(ctx, 0, sizeof(*ctx));
++	ctx->id = *id;
++	ctx->fpriv = fpriv;
++	kref_init(&ctx->refcount);
++
++	return 0;
++}
++
++int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
++{
++	int r;
++	struct amdgpu_ctx *ctx;
++	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
++
++	rcu_read_lock();
++	ctx = idr_find(&mgr->ctx_handles, id);
++	rcu_read_unlock();
++	if (ctx) {
++		/* if no task is pending on this context, free it */
++		r = kref_put(&ctx->refcount, amdgpu_ctx_do_release);
++		if (r == 1)
++			return 0;//context is removed successfully
++		else {
++			/* context is still in using */
++			kref_get(&ctx->refcount);
++			return -ERESTARTSYS;
++		}
++	}
++	return -EINVAL;
++}
++
++int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id, struct amdgpu_ctx_state *state)
++{
++	struct amdgpu_ctx *ctx;
++	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
++
++	rcu_read_lock();
++	ctx = idr_find(&mgr->ctx_handles, id);
++	rcu_read_unlock();
++	if (ctx) {
++		/* state should alter with CS activity */
++		*state = ctx->state;
++		return 0;
++	}
++	return -EINVAL;
++}
++
++void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
++{
++	struct idr *idp;
++	struct amdgpu_ctx *ctx;
++	uint32_t id;
++	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
++	idp = &mgr->ctx_handles;
++
++	idr_for_each_entry(idp,ctx,id) {
++		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
++			DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id);
++	}
++
++	mutex_destroy(&mgr->hlock);
++}
++
++int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
++							struct drm_file *filp)
++{
++	int r;
++	uint32_t id;
++	uint32_t flags;
++	struct amdgpu_ctx_state state;
++
++	union drm_amdgpu_ctx *args = data;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_fpriv *fpriv = filp->driver_priv;
++
++	r = 0;
++	id = args->in.ctx_id;
++	flags = args->in.flags;
++
++	switch (args->in.op) {
++		case AMDGPU_CTX_OP_ALLOC_CTX:
++			r = amdgpu_ctx_alloc(adev, fpriv, &id, flags);
++			args->out.alloc.ctx_id = id;
++			break;
++		case AMDGPU_CTX_OP_FREE_CTX:
++			r = amdgpu_ctx_free(adev, fpriv, id);
++			break;
++		case AMDGPU_CTX_OP_QUERY_STATE:
++			r = amdgpu_ctx_query(adev, fpriv, id, &state);
++			if (r == 0) {
++				args->out.state.flags = state.flags;
++				args->out.state.hangs = state.hangs;
++			}
++			break;
++		default:
++			return -EINVAL;
++	}
++
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+new file mode 100644
+index 0000000..cd4bb90
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -0,0 +1,1971 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <linux/console.h>
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/amdgpu_drm.h>
++#include <linux/vgaarb.h>
++#include <linux/vga_switcheroo.h>
++#include <linux/efi.h>
++#include "amdgpu.h"
++#include "amdgpu_i2c.h"
++#include "atom.h"
++#include "amdgpu_atombios.h"
++#include "bif/bif_4_1_d.h"
++
++static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
++static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
++
++static const char *amdgpu_asic_name[] = {
++	"BONAIRE",
++	"KAVERI",
++	"KABINI",
++	"HAWAII",
++	"MULLINS",
++	"TOPAZ",
++	"TONGA",
++	"CARRIZO",
++	"LAST",
++};
++
++bool amdgpu_device_is_px(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (adev->flags & AMDGPU_IS_PX)
++		return true;
++	return false;
++}
++
++/*
++ * MMIO register access helper functions.
++ */
++uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
++			bool always_indirect)
++{
++	if ((reg * 4) < adev->rmmio_size && !always_indirect)
++		return readl(((void __iomem *)adev->rmmio) + (reg * 4));
++	else {
++		unsigned long flags;
++		uint32_t ret;
++
++		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
++		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
++		ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
++		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
++
++		return ret;
++	}
++}
++
++void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
++		    bool always_indirect)
++{
++	if ((reg * 4) < adev->rmmio_size && !always_indirect)
++		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
++	else {
++		unsigned long flags;
++
++		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
++		writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
++		writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
++		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
++	}
++}
++
++u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	if ((reg * 4) < adev->rio_mem_size)
++		return ioread32(adev->rio_mem + (reg * 4));
++	else {
++		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
++		return ioread32(adev->rio_mem + (mmMM_DATA * 4));
++	}
++}
++
++void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++
++	if ((reg * 4) < adev->rio_mem_size)
++		iowrite32(v, adev->rio_mem + (reg * 4));
++	else {
++		iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
++		iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
++	}
++}
++
++/**
++ * amdgpu_mm_rdoorbell - read a doorbell dword
++ *
++ * @adev: amdgpu_device pointer
++ * @index: doorbell index
++ *
++ * Returns the value in the doorbell aperture at the
++ * requested doorbell index (CIK).
++ */
++u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
++{
++	if (index < adev->doorbell.num_doorbells) {
++		return readl(adev->doorbell.ptr + index);
++	} else {
++		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
++		return 0;
++	}
++}
++
++/**
++ * amdgpu_mm_wdoorbell - write a doorbell dword
++ *
++ * @adev: amdgpu_device pointer
++ * @index: doorbell index
++ * @v: value to write
++ *
++ * Writes @v to the doorbell aperture at the
++ * requested doorbell index (CIK).
++ */
++void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
++{
++	if (index < adev->doorbell.num_doorbells) {
++		writel(v, adev->doorbell.ptr + index);
++	} else {
++		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
++	}
++}
++
++/**
++ * amdgpu_invalid_rreg - dummy reg read function
++ *
++ * @adev: amdgpu device pointer
++ * @reg: offset of register
++ *
++ * Dummy register read function.  Used for register blocks
++ * that certain asics don't have (all asics).
++ * Returns the value in the register.
++ */
++static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
++{
++	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
++	BUG();
++	return 0;
++}
++
++/**
++ * amdgpu_invalid_wreg - dummy reg write function
++ *
++ * @adev: amdgpu device pointer
++ * @reg: offset of register
++ * @v: value to write to the register
++ *
++ * Dummy register read function.  Used for register blocks
++ * that certain asics don't have (all asics).
++ */
++static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
++{
++	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
++		  reg, v);
++	BUG();
++}
++
++/**
++ * amdgpu_block_invalid_rreg - dummy reg read function
++ *
++ * @adev: amdgpu device pointer
++ * @block: offset of instance
++ * @reg: offset of register
++ *
++ * Dummy register read function.  Used for register blocks
++ * that certain asics don't have (all asics).
++ * Returns the value in the register.
++ */
++static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
++					  uint32_t block, uint32_t reg)
++{
++	DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
++		  reg, block);
++	BUG();
++	return 0;
++}
++
++/**
++ * amdgpu_block_invalid_wreg - dummy reg write function
++ *
++ * @adev: amdgpu device pointer
++ * @block: offset of instance
++ * @reg: offset of register
++ * @v: value to write to the register
++ *
++ * Dummy register read function.  Used for register blocks
++ * that certain asics don't have (all asics).
++ */
++static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
++				      uint32_t block,
++				      uint32_t reg, uint32_t v)
++{
++	DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
++		  reg, block, v);
++	BUG();
++}
++
++static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->vram_scratch.robj == NULL) {
++		r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
++				     PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0,
++				     NULL, &adev->vram_scratch.robj);
++		if (r) {
++			return r;
++		}
++	}
++
++	r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
++	if (unlikely(r != 0))
++		return r;
++	r = amdgpu_bo_pin(adev->vram_scratch.robj,
++			  AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
++	if (r) {
++		amdgpu_bo_unreserve(adev->vram_scratch.robj);
++		return r;
++	}
++	r = amdgpu_bo_kmap(adev->vram_scratch.robj,
++				(void **)&adev->vram_scratch.ptr);
++	if (r)
++		amdgpu_bo_unpin(adev->vram_scratch.robj);
++	amdgpu_bo_unreserve(adev->vram_scratch.robj);
++
++	return r;
++}
++
++static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->vram_scratch.robj == NULL) {
++		return;
++	}
++	r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
++	if (likely(r == 0)) {
++		amdgpu_bo_kunmap(adev->vram_scratch.robj);
++		amdgpu_bo_unpin(adev->vram_scratch.robj);
++		amdgpu_bo_unreserve(adev->vram_scratch.robj);
++	}
++	amdgpu_bo_unref(&adev->vram_scratch.robj);
++}
++
++/**
++ * amdgpu_program_register_sequence - program an array of registers.
++ *
++ * @adev: amdgpu_device pointer
++ * @registers: pointer to the register array
++ * @array_size: size of the register array
++ *
++ * Programs an array or registers with and and or masks.
++ * This is a helper for setting golden registers.
++ */
++void amdgpu_program_register_sequence(struct amdgpu_device *adev,
++				      const u32 *registers,
++				      const u32 array_size)
++{
++	u32 tmp, reg, and_mask, or_mask;
++	int i;
++
++	if (array_size % 3)
++		return;
++
++	for (i = 0; i < array_size; i +=3) {
++		reg = registers[i + 0];
++		and_mask = registers[i + 1];
++		or_mask = registers[i + 2];
++
++		if (and_mask == 0xffffffff) {
++			tmp = or_mask;
++		} else {
++			tmp = RREG32(reg);
++			tmp &= ~and_mask;
++			tmp |= or_mask;
++		}
++		WREG32(reg, tmp);
++	}
++}
++
++void amdgpu_pci_config_reset(struct amdgpu_device *adev)
++{
++	pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
++}
++
++/*
++ * GPU doorbell aperture helpers function.
++ */
++/**
++ * amdgpu_doorbell_init - Init doorbell driver information.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Init doorbell driver information (CIK)
++ * Returns 0 on success, error on failure.
++ */
++static int amdgpu_doorbell_init(struct amdgpu_device *adev)
++{
++	/* doorbell bar mapping */
++	adev->doorbell.base = pci_resource_start(adev->pdev, 2);
++	adev->doorbell.size = pci_resource_len(adev->pdev, 2);
++
++	adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), 
++					     AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
++	if (adev->doorbell.num_doorbells == 0)
++		return -EINVAL;
++
++	adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
++	if (adev->doorbell.ptr == NULL) {
++		return -ENOMEM;
++	}
++	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
++	DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
++
++	return 0;
++}
++
++/**
++ * amdgpu_doorbell_fini - Tear down doorbell driver information.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down doorbell driver information (CIK)
++ */
++static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
++{
++	iounmap(adev->doorbell.ptr);
++	adev->doorbell.ptr = NULL;
++}
++
++/**
++ * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
++ *                                setup amdkfd
++ *
++ * @adev: amdgpu_device pointer
++ * @aperture_base: output returning doorbell aperture base physical address
++ * @aperture_size: output returning doorbell aperture size in bytes
++ * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
++ *
++ * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
++ * takes doorbells required for its own rings and reports the setup to amdkfd.
++ * amdgpu reserved doorbells are at the start of the doorbell aperture.
++ */
++void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
++				phys_addr_t *aperture_base,
++				size_t *aperture_size,
++				size_t *start_offset)
++{
++	/*
++	 * The first num_doorbells are used by amdgpu.
++	 * amdkfd takes whatever's left in the aperture.
++	 */
++	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
++		*aperture_base = adev->doorbell.base;
++		*aperture_size = adev->doorbell.size;
++		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
++	} else {
++		*aperture_base = 0;
++		*aperture_size = 0;
++		*start_offset = 0;
++	}
++}
++
++/*
++ * amdgpu_wb_*()
++ * Writeback is the the method by which the the GPU updates special pages
++ * in memory with the status of certain GPU events (fences, ring pointers,
++ * etc.).
++ */
++
++/**
++ * amdgpu_wb_fini - Disable Writeback and free memory
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disables Writeback and frees the Writeback memory (all asics).
++ * Used at driver shutdown.
++ */
++static void amdgpu_wb_fini(struct amdgpu_device *adev)
++{
++	if (adev->wb.wb_obj) {
++		if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
++			amdgpu_bo_kunmap(adev->wb.wb_obj);
++			amdgpu_bo_unpin(adev->wb.wb_obj);
++			amdgpu_bo_unreserve(adev->wb.wb_obj);
++		}
++		amdgpu_bo_unref(&adev->wb.wb_obj);
++		adev->wb.wb = NULL;
++		adev->wb.wb_obj = NULL;
++	}
++}
++
++/**
++ * amdgpu_wb_init- Init Writeback driver info and allocate memory
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disables Writeback and frees the Writeback memory (all asics).
++ * Used at driver startup.
++ * Returns 0 on success or an -error on failure.
++ */
++static int amdgpu_wb_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->wb.wb_obj == NULL) {
++		r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, &adev->wb.wb_obj);
++		if (r) {
++			dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
++			return r;
++		}
++		r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
++		if (unlikely(r != 0)) {
++			amdgpu_wb_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
++				&adev->wb.gpu_addr);
++		if (r) {
++			amdgpu_bo_unreserve(adev->wb.wb_obj);
++			dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
++			amdgpu_wb_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
++		amdgpu_bo_unreserve(adev->wb.wb_obj);
++		if (r) {
++			dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
++			amdgpu_wb_fini(adev);
++			return r;
++		}
++
++		adev->wb.num_wb = AMDGPU_MAX_WB;
++		memset(&adev->wb.used, 0, sizeof(adev->wb.used));
++
++		/* clear wb memory */
++		memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_wb_get - Allocate a wb entry
++ *
++ * @adev: amdgpu_device pointer
++ * @wb: wb index
++ *
++ * Allocate a wb slot for use by the driver (all asics).
++ * Returns 0 on success or -EINVAL on failure.
++ */
++int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
++{
++	unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
++	if (offset < adev->wb.num_wb) {
++		__set_bit(offset, adev->wb.used);
++		*wb = offset;
++		return 0;
++	} else {
++		return -EINVAL;
++	}
++}
++
++/**
++ * amdgpu_wb_free - Free a wb entry
++ *
++ * @adev: amdgpu_device pointer
++ * @wb: wb index
++ *
++ * Free a wb slot allocated for use by the driver (all asics)
++ */
++void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
++{
++	if (wb < adev->wb.num_wb)
++		__clear_bit(wb, adev->wb.used);
++}
++
++/**
++ * amdgpu_vram_location - try to find VRAM location
++ * @adev: amdgpu device structure holding all necessary informations
++ * @mc: memory controller structure holding memory informations
++ * @base: base address at which to put VRAM
++ *
++ * Function will place try to place VRAM at base address provided
++ * as parameter (which is so far either PCI aperture address or
++ * for IGP TOM base address).
++ *
++ * If there is not enough space to fit the unvisible VRAM in the 32bits
++ * address space then we limit the VRAM size to the aperture.
++ *
++ * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
++ * this shouldn't be a problem as we are using the PCI aperture as a reference.
++ * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
++ * not IGP.
++ *
++ * Note: we use mc_vram_size as on some board we need to program the mc to
++ * cover the whole aperture even if VRAM size is inferior to aperture size
++ * Novell bug 204882 + along with lots of ubuntu ones
++ *
++ * Note: when limiting vram it's safe to overwritte real_vram_size because
++ * we are not in case where real_vram_size is inferior to mc_vram_size (ie
++ * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
++ * ones)
++ *
++ * Note: IGP TOM addr should be the same as the aperture addr, we don't
++ * explicitly check for that thought.
++ *
++ * FIXME: when reducing VRAM size align new size on power of 2.
++ */
++void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
++{
++	uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
++
++	mc->vram_start = base;
++	if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
++		dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
++		mc->real_vram_size = mc->aper_size;
++		mc->mc_vram_size = mc->aper_size;
++	}
++	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
++	if (limit && limit < mc->real_vram_size)
++		mc->real_vram_size = limit;
++	dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
++			mc->mc_vram_size >> 20, mc->vram_start,
++			mc->vram_end, mc->real_vram_size >> 20);
++}
++
++/**
++ * amdgpu_gtt_location - try to find GTT location
++ * @adev: amdgpu device structure holding all necessary informations
++ * @mc: memory controller structure holding memory informations
++ *
++ * Function will place try to place GTT before or after VRAM.
++ *
++ * If GTT size is bigger than space left then we ajust GTT size.
++ * Thus function will never fails.
++ *
++ * FIXME: when reducing GTT size align new size on power of 2.
++ */
++void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
++{
++	u64 size_af, size_bf;
++
++	size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
++	size_bf = mc->vram_start & ~mc->gtt_base_align;
++	if (size_bf > size_af) {
++		if (mc->gtt_size > size_bf) {
++			dev_warn(adev->dev, "limiting GTT\n");
++			mc->gtt_size = size_bf;
++		}
++		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
++	} else {
++		if (mc->gtt_size > size_af) {
++			dev_warn(adev->dev, "limiting GTT\n");
++			mc->gtt_size = size_af;
++		}
++		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
++	}
++	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
++	dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
++			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
++}
++
++/*
++ * GPU helpers function.
++ */
++/**
++ * amdgpu_card_posted - check if the hw has already been initialized
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Check if the asic has been initialized (all asics).
++ * Used at driver startup.
++ * Returns true if initialized or false if not.
++ */
++bool amdgpu_card_posted(struct amdgpu_device *adev)
++{
++	uint32_t reg;
++
++	/* then check MEM_SIZE, in case the crtcs are off */
++	reg = RREG32(mmCONFIG_MEMSIZE);
++
++	if (reg)
++		return true;
++
++	return false;
++
++}
++
++/**
++ * amdgpu_boot_test_post_card - check and possibly initialize the hw
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Check if the asic is initialized and if not, attempt to initialize
++ * it (all asics).
++ * Returns true if initialized or false if not.
++ */
++bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
++{
++	if (amdgpu_card_posted(adev))
++		return true;
++
++	if (adev->bios) {
++		DRM_INFO("GPU not posted. posting now...\n");
++		if (adev->is_atom_bios)
++			amdgpu_atom_asic_init(adev->mode_info.atom_context);
++		return true;
++	} else {
++		dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
++		return false;
++	}
++}
++
++/**
++ * amdgpu_dummy_page_init - init dummy page used by the driver
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate the dummy page used by the driver (all asics).
++ * This dummy page is used by the driver as a filler for gart entries
++ * when pages are taken out of the GART
++ * Returns 0 on sucess, -ENOMEM on failure.
++ */
++int amdgpu_dummy_page_init(struct amdgpu_device *adev)
++{
++	if (adev->dummy_page.page)
++		return 0;
++	adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
++	if (adev->dummy_page.page == NULL)
++		return -ENOMEM;
++	adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
++					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
++	if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
++		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
++		__free_page(adev->dummy_page.page);
++		adev->dummy_page.page = NULL;
++		return -ENOMEM;
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_dummy_page_fini - free dummy page used by the driver
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Frees the dummy page used by the driver (all asics).
++ */
++void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
++{
++	if (adev->dummy_page.page == NULL)
++		return;
++	pci_unmap_page(adev->pdev, adev->dummy_page.addr,
++			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
++	__free_page(adev->dummy_page.page);
++	adev->dummy_page.page = NULL;
++}
++
++
++/* ATOM accessor methods */
++/*
++ * ATOM is an interpreted byte code stored in tables in the vbios.  The
++ * driver registers callbacks to access registers and the interpreter
++ * in the driver parses the tables and executes then to program specific
++ * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
++ * atombios.h, and atom.c
++ */
++
++/**
++ * cail_pll_read - read PLL register
++ *
++ * @info: atom card_info pointer
++ * @reg: PLL register offset
++ *
++ * Provides a PLL register accessor for the atom interpreter (r4xx+).
++ * Returns the value of the PLL register.
++ */
++static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
++{
++	return 0;
++}
++
++/**
++ * cail_pll_write - write PLL register
++ *
++ * @info: atom card_info pointer
++ * @reg: PLL register offset
++ * @val: value to write to the pll register
++ *
++ * Provides a PLL register accessor for the atom interpreter (r4xx+).
++ */
++static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
++{
++
++}
++
++/**
++ * cail_mc_read - read MC (Memory Controller) register
++ *
++ * @info: atom card_info pointer
++ * @reg: MC register offset
++ *
++ * Provides an MC register accessor for the atom interpreter (r4xx+).
++ * Returns the value of the MC register.
++ */
++static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
++{
++	return 0;
++}
++
++/**
++ * cail_mc_write - write MC (Memory Controller) register
++ *
++ * @info: atom card_info pointer
++ * @reg: MC register offset
++ * @val: value to write to the pll register
++ *
++ * Provides a MC register accessor for the atom interpreter (r4xx+).
++ */
++static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
++{
++
++}
++
++/**
++ * cail_reg_write - write MMIO register
++ *
++ * @info: atom card_info pointer
++ * @reg: MMIO register offset
++ * @val: value to write to the pll register
++ *
++ * Provides a MMIO register accessor for the atom interpreter (r4xx+).
++ */
++static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
++{
++	struct amdgpu_device *adev = info->dev->dev_private;
++
++	WREG32(reg, val);
++}
++
++/**
++ * cail_reg_read - read MMIO register
++ *
++ * @info: atom card_info pointer
++ * @reg: MMIO register offset
++ *
++ * Provides an MMIO register accessor for the atom interpreter (r4xx+).
++ * Returns the value of the MMIO register.
++ */
++static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
++{
++	struct amdgpu_device *adev = info->dev->dev_private;
++	uint32_t r;
++
++	r = RREG32(reg);
++	return r;
++}
++
++/**
++ * cail_ioreg_write - write IO register
++ *
++ * @info: atom card_info pointer
++ * @reg: IO register offset
++ * @val: value to write to the pll register
++ *
++ * Provides a IO register accessor for the atom interpreter (r4xx+).
++ */
++static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
++{
++	struct amdgpu_device *adev = info->dev->dev_private;
++
++	WREG32_IO(reg, val);
++}
++
++/**
++ * cail_ioreg_read - read IO register
++ *
++ * @info: atom card_info pointer
++ * @reg: IO register offset
++ *
++ * Provides an IO register accessor for the atom interpreter (r4xx+).
++ * Returns the value of the IO register.
++ */
++static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
++{
++	struct amdgpu_device *adev = info->dev->dev_private;
++	uint32_t r;
++
++	r = RREG32_IO(reg);
++	return r;
++}
++
++/**
++ * amdgpu_atombios_fini - free the driver info and callbacks for atombios
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Frees the driver info and register access callbacks for the ATOM
++ * interpreter (r4xx+).
++ * Called at driver shutdown.
++ */
++static void amdgpu_atombios_fini(struct amdgpu_device *adev)
++{
++	if (adev->mode_info.atom_context)
++		kfree(adev->mode_info.atom_context->scratch);
++	kfree(adev->mode_info.atom_context);
++	adev->mode_info.atom_context = NULL;
++	kfree(adev->mode_info.atom_card_info);
++	adev->mode_info.atom_card_info = NULL;
++}
++
++/**
++ * amdgpu_atombios_init - init the driver info and callbacks for atombios
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initializes the driver info and register access callbacks for the
++ * ATOM interpreter (r4xx+).
++ * Returns 0 on sucess, -ENOMEM on failure.
++ * Called at driver startup.
++ */
++static int amdgpu_atombios_init(struct amdgpu_device *adev)
++{
++	struct card_info *atom_card_info =
++	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
++
++	if (!atom_card_info)
++		return -ENOMEM;
++
++	adev->mode_info.atom_card_info = atom_card_info;
++	atom_card_info->dev = adev->ddev;
++	atom_card_info->reg_read = cail_reg_read;
++	atom_card_info->reg_write = cail_reg_write;
++	/* needed for iio ops */
++	if (adev->rio_mem) {
++		atom_card_info->ioreg_read = cail_ioreg_read;
++		atom_card_info->ioreg_write = cail_ioreg_write;
++	} else {
++		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
++		atom_card_info->ioreg_read = cail_reg_read;
++		atom_card_info->ioreg_write = cail_reg_write;
++	}
++	atom_card_info->mc_read = cail_mc_read;
++	atom_card_info->mc_write = cail_mc_write;
++	atom_card_info->pll_read = cail_pll_read;
++	atom_card_info->pll_write = cail_pll_write;
++
++	adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
++	if (!adev->mode_info.atom_context) {
++		amdgpu_atombios_fini(adev);
++		return -ENOMEM;
++	}
++
++	mutex_init(&adev->mode_info.atom_context->mutex);
++	amdgpu_atombios_scratch_regs_init(adev);
++	amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
++	return 0;
++}
++
++/* if we get transitioned to only one device, take VGA back */
++/**
++ * amdgpu_vga_set_decode - enable/disable vga decode
++ *
++ * @cookie: amdgpu_device pointer
++ * @state: enable/disable vga decode
++ *
++ * Enable/disable vga decode (all asics).
++ * Returns VGA resource flags.
++ */
++static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
++{
++	struct amdgpu_device *adev = cookie;
++	amdgpu_asic_set_vga_state(adev, state);
++	if (state)
++		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
++		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
++	else
++		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
++}
++
++/**
++ * amdgpu_check_pot_argument - check that argument is a power of two
++ *
++ * @arg: value to check
++ *
++ * Validates that a certain argument is a power of two (all asics).
++ * Returns true if argument is valid.
++ */
++static bool amdgpu_check_pot_argument(int arg)
++{
++	return (arg & (arg - 1)) == 0;
++}
++
++/**
++ * amdgpu_check_arguments - validate module params
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Validates certain module parameters and updates
++ * the associated values used by the driver (all asics).
++ */
++static void amdgpu_check_arguments(struct amdgpu_device *adev)
++{
++	/* vramlimit must be a power of two */
++	if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
++		dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
++				amdgpu_vram_limit);
++		amdgpu_vram_limit = 0;
++	}
++
++	if (amdgpu_gart_size != -1) {
++		/* gtt size must be power of two and greater or equal to 32M */
++		if (amdgpu_gart_size < 32) {
++			dev_warn(adev->dev, "gart size (%d) too small\n",
++				 amdgpu_gart_size);
++			amdgpu_gart_size = -1;
++		} else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
++			dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
++				 amdgpu_gart_size);
++			amdgpu_gart_size = -1;
++		}
++	}
++
++	if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
++		dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
++			 amdgpu_vm_size);
++		amdgpu_vm_size = 4;
++	}
++
++	if (amdgpu_vm_size < 1) {
++		dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
++			 amdgpu_vm_size);
++		amdgpu_vm_size = 4;
++	}
++
++	/*
++	 * Max GPUVM size for Cayman, SI and CI are 40 bits.
++	 */
++	if (amdgpu_vm_size > 1024) {
++		dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
++			 amdgpu_vm_size);
++		amdgpu_vm_size = 4;
++	}
++
++	/* defines number of bits in page table versus page directory,
++	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
++	 * page table and the remaining bits are in the page directory */
++	if (amdgpu_vm_block_size == -1) {
++
++		/* Total bits covered by PD + PTs */
++		unsigned bits = ilog2(amdgpu_vm_size) + 18;
++
++		/* Make sure the PD is 4K in size up to 8GB address space.
++		   Above that split equal between PD and PTs */
++		if (amdgpu_vm_size <= 8)
++			amdgpu_vm_block_size = bits - 9;
++		else
++			amdgpu_vm_block_size = (bits + 3) / 2;
++
++	} else if (amdgpu_vm_block_size < 9) {
++		dev_warn(adev->dev, "VM page table size (%d) too small\n",
++			 amdgpu_vm_block_size);
++		amdgpu_vm_block_size = 9;
++	}
++
++	if (amdgpu_vm_block_size > 24 ||
++	    (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
++		dev_warn(adev->dev, "VM page table size (%d) too large\n",
++			 amdgpu_vm_block_size);
++		amdgpu_vm_block_size = 9;
++	}
++}
++
++/**
++ * amdgpu_switcheroo_set_state - set switcheroo state
++ *
++ * @pdev: pci dev pointer
++ * @state: vga switcheroo state
++ *
++ * Callback for the switcheroo driver.  Suspends or resumes the
++ * the asics before or after it is powered up using ACPI methods.
++ */
++static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
++{
++	struct drm_device *dev = pci_get_drvdata(pdev);
++
++	if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
++		return;
++
++	if (state == VGA_SWITCHEROO_ON) {
++		unsigned d3_delay = dev->pdev->d3_delay;
++
++		printk(KERN_INFO "amdgpu: switched on\n");
++		/* don't suspend or resume card normally */
++		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++
++		amdgpu_resume_kms(dev, true, true);
++
++		dev->pdev->d3_delay = d3_delay;
++
++		dev->switch_power_state = DRM_SWITCH_POWER_ON;
++		drm_kms_helper_poll_enable(dev);
++	} else {
++		printk(KERN_INFO "amdgpu: switched off\n");
++		drm_kms_helper_poll_disable(dev);
++		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++		amdgpu_suspend_kms(dev, true, true);
++		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
++	}
++}
++
++/**
++ * amdgpu_switcheroo_can_switch - see if switcheroo state can change
++ *
++ * @pdev: pci dev pointer
++ *
++ * Callback for the switcheroo driver.  Check of the switcheroo
++ * state can be changed.
++ * Returns true if the state can be changed, false if not.
++ */
++static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
++{
++	struct drm_device *dev = pci_get_drvdata(pdev);
++
++	/*
++	* FIXME: open_count is protected by drm_global_mutex but that would lead to
++	* locking inversion with the driver load path. And the access here is
++	* completely racy anyway. So don't bother with locking for now.
++	*/
++	return dev->open_count == 0;
++}
++
++static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
++	.set_gpu_state = amdgpu_switcheroo_set_state,
++	.reprobe = NULL,
++	.can_switch = amdgpu_switcheroo_can_switch,
++};
++
++int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
++				  enum amdgpu_ip_block_type block_type,
++				  enum amdgpu_clockgating_state state)
++{
++	int i, r = 0;
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if (adev->ip_blocks[i].type == block_type) {
++			r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
++									    state);
++			if (r)
++				return r;
++		}
++	}
++	return r;
++}
++
++int amdgpu_set_powergating_state(struct amdgpu_device *adev,
++				  enum amdgpu_ip_block_type block_type,
++				  enum amdgpu_powergating_state state)
++{
++	int i, r = 0;
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if (adev->ip_blocks[i].type == block_type) {
++			r = adev->ip_blocks[i].funcs->set_powergating_state(adev,
++									    state);
++			if (r)
++				return r;
++		}
++	}
++	return r;
++}
++
++const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
++					struct amdgpu_device *adev,
++					enum amdgpu_ip_block_type type)
++{
++	int i;
++
++	for (i = 0; i < adev->num_ip_blocks; i++)
++		if (adev->ip_blocks[i].type == type)
++			return &adev->ip_blocks[i];
++
++	return NULL;
++}
++
++/**
++ * amdgpu_ip_block_version_cmp
++ *
++ * @adev: amdgpu_device pointer
++ * @type: enum amdgpu_ip_block_type
++ * @major: major version
++ * @minor: minor version
++ *
++ * return 0 if equal or greater
++ * return 1 if smaller or the ip_block doesn't exist
++ */
++int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
++				enum amdgpu_ip_block_type type,
++				u32 major, u32 minor)
++{
++	const struct amdgpu_ip_block_version *ip_block;
++	ip_block = amdgpu_get_ip_block(adev, type);
++
++	if (ip_block && ((ip_block->major > major) ||
++			((ip_block->major == major) &&
++			(ip_block->minor >= minor))))
++		return 0;
++
++	return 1;
++}
++
++static int amdgpu_early_init(struct amdgpu_device *adev)
++{
++	int i, r = -EINVAL;
++
++	switch (adev->asic_type) {
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++
++
++	if (adev->ip_blocks == NULL) {
++		DRM_ERROR("No IP blocks found!\n");
++		return r;
++	}
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
++			DRM_ERROR("disabled ip block: %d\n", i);
++			adev->ip_block_enabled[i] = false;
++		} else {
++			if (adev->ip_blocks[i].funcs->early_init) {
++				r = adev->ip_blocks[i].funcs->early_init(adev);
++				if (r)
++					return r;
++			}
++			adev->ip_block_enabled[i] = true;
++		}
++	}
++
++	return 0;
++}
++
++static int amdgpu_init(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		r = adev->ip_blocks[i].funcs->sw_init(adev);
++		if (r)
++			return r;
++		/* need to do gmc hw init early so we can allocate gpu mem */
++		if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) {
++			r = amdgpu_vram_scratch_init(adev);
++			if (r)
++				return r;
++			r = adev->ip_blocks[i].funcs->hw_init(adev);
++			if (r)
++				return r;
++			r = amdgpu_wb_init(adev);
++			if (r)
++				return r;
++		}
++	}
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		/* gmc hw init is done early */
++		if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC)
++			continue;
++		r = adev->ip_blocks[i].funcs->hw_init(adev);
++		if (r)
++			return r;
++	}
++
++	return 0;
++}
++
++static int amdgpu_late_init(struct amdgpu_device *adev)
++{
++	int i = 0, r;
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		/* enable clockgating to save power */
++		r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
++								    AMDGPU_CG_STATE_GATE);
++		if (r)
++			return r;
++		if (adev->ip_blocks[i].funcs->late_init) {
++			r = adev->ip_blocks[i].funcs->late_init(adev);
++			if (r)
++				return r;
++		}
++	}
++
++	return 0;
++}
++
++static int amdgpu_fini(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) {
++			amdgpu_wb_fini(adev);
++			amdgpu_vram_scratch_fini(adev);
++		}
++		/* ungate blocks before hw fini so that we can shutdown the blocks safely */
++		r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
++								    AMDGPU_CG_STATE_UNGATE);
++		if (r)
++			return r;
++		r = adev->ip_blocks[i].funcs->hw_fini(adev);
++		/* XXX handle errors */
++	}
++
++	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		r = adev->ip_blocks[i].funcs->sw_fini(adev);
++		/* XXX handle errors */
++		adev->ip_block_enabled[i] = false;
++	}
++
++	return 0;
++}
++
++static int amdgpu_suspend(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		/* ungate blocks so that suspend can properly shut them down */
++		r = adev->ip_blocks[i].funcs->set_clockgating_state(adev,
++								    AMDGPU_CG_STATE_UNGATE);
++		/* XXX handle errors */
++		r = adev->ip_blocks[i].funcs->suspend(adev);
++		/* XXX handle errors */
++	}
++
++	return 0;
++}
++
++static int amdgpu_resume(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	for (i = 0; i < adev->num_ip_blocks; i++) {
++		if (!adev->ip_block_enabled[i])
++			continue;
++		r = adev->ip_blocks[i].funcs->resume(adev);
++		if (r)
++			return r;
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_device_init - initialize the driver
++ *
++ * @adev: amdgpu_device pointer
++ * @pdev: drm dev pointer
++ * @pdev: pci dev pointer
++ * @flags: driver flags
++ *
++ * Initializes the driver info and hw (all asics).
++ * Returns 0 for success or an error on failure.
++ * Called at driver startup.
++ */
++int amdgpu_device_init(struct amdgpu_device *adev,
++		       struct drm_device *ddev,
++		       struct pci_dev *pdev,
++		       uint32_t flags)
++{
++	int r, i;
++	bool runtime = false;
++
++	adev->shutdown = false;
++	adev->dev = &pdev->dev;
++	adev->ddev = ddev;
++	adev->pdev = pdev;
++	adev->flags = flags;
++	adev->asic_type = flags & AMDGPU_ASIC_MASK;
++	adev->is_atom_bios = false;
++	adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
++	adev->mc.gtt_size = 512 * 1024 * 1024;
++	adev->accel_working = false;
++	adev->num_rings = 0;
++	adev->mman.buffer_funcs = NULL;
++	adev->mman.buffer_funcs_ring = NULL;
++	adev->vm_manager.vm_pte_funcs = NULL;
++	adev->vm_manager.vm_pte_funcs_ring = NULL;
++	adev->gart.gart_funcs = NULL;
++	adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
++
++	adev->smc_rreg = &amdgpu_invalid_rreg;
++	adev->smc_wreg = &amdgpu_invalid_wreg;
++	adev->pcie_rreg = &amdgpu_invalid_rreg;
++	adev->pcie_wreg = &amdgpu_invalid_wreg;
++	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
++	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
++	adev->didt_rreg = &amdgpu_invalid_rreg;
++	adev->didt_wreg = &amdgpu_invalid_wreg;
++	adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
++	adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
++
++	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
++		amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
++		pdev->subsystem_vendor, pdev->subsystem_device);
++
++	/* mutex initialization are all done here so we
++	 * can recall function without having locking issues */
++	mutex_init(&adev->ring_lock);
++	atomic_set(&adev->irq.ih.lock, 0);
++	mutex_init(&adev->gem.mutex);
++	mutex_init(&adev->pm.mutex);
++	mutex_init(&adev->gfx.gpu_clock_mutex);
++	mutex_init(&adev->srbm_mutex);
++	mutex_init(&adev->grbm_idx_mutex);
++	init_rwsem(&adev->pm.mclk_lock);
++	init_rwsem(&adev->exclusive_lock);
++	mutex_init(&adev->mn_lock);
++	hash_init(adev->mn_hash);
++
++	amdgpu_check_arguments(adev);
++
++	/* Registers mapping */
++	/* TODO: block userspace mapping of io register */
++	spin_lock_init(&adev->mmio_idx_lock);
++	spin_lock_init(&adev->smc_idx_lock);
++	spin_lock_init(&adev->pcie_idx_lock);
++	spin_lock_init(&adev->uvd_ctx_idx_lock);
++	spin_lock_init(&adev->didt_idx_lock);
++	spin_lock_init(&adev->audio_endpt_idx_lock);
++
++	adev->rmmio_base = pci_resource_start(adev->pdev, 5);
++	adev->rmmio_size = pci_resource_len(adev->pdev, 5);
++	adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
++	if (adev->rmmio == NULL) {
++		return -ENOMEM;
++	}
++	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
++	DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
++
++	/* doorbell bar mapping */
++	amdgpu_doorbell_init(adev);
++
++	/* io port mapping */
++	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
++		if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
++			adev->rio_mem_size = pci_resource_len(adev->pdev, i);
++			adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
++			break;
++		}
++	}
++	if (adev->rio_mem == NULL)
++		DRM_ERROR("Unable to find PCI I/O BAR\n");
++
++	/* early init functions */
++	r = amdgpu_early_init(adev);
++	if (r)
++		return r;
++
++	/* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
++	/* this will fail for cards that aren't VGA class devices, just
++	 * ignore it */
++	vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
++
++	if (amdgpu_runtime_pm == 1)
++		runtime = true;
++	if (amdgpu_device_is_px(ddev))
++		runtime = true;
++	vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
++	if (runtime)
++		vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
++
++	/* Read BIOS */
++	if (!amdgpu_get_bios(adev))
++		return -EINVAL;
++	/* Must be an ATOMBIOS */
++	if (!adev->is_atom_bios) {
++		dev_err(adev->dev, "Expecting atombios for GPU\n");
++		return -EINVAL;
++	}
++	r = amdgpu_atombios_init(adev);
++	if (r)
++		return r;
++
++	/* Post card if necessary */
++	if (!amdgpu_card_posted(adev)) {
++		if (!adev->bios) {
++			dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
++			return -EINVAL;
++		}
++		DRM_INFO("GPU not posted. posting now...\n");
++		amdgpu_atom_asic_init(adev->mode_info.atom_context);
++	}
++
++	/* Initialize clocks */
++	r = amdgpu_atombios_get_clock_info(adev);
++	if (r)
++		return r;
++	/* init i2c buses */
++	amdgpu_atombios_i2c_init(adev);
++
++	/* Fence driver */
++	r = amdgpu_fence_driver_init(adev);
++	if (r)
++		return r;
++
++	/* init the mode config */
++	drm_mode_config_init(adev->ddev);
++
++	r = amdgpu_init(adev);
++	if (r) {
++		amdgpu_fini(adev);
++		return r;
++	}
++
++	adev->accel_working = true;
++
++	amdgpu_fbdev_init(adev);
++
++	r = amdgpu_ib_pool_init(adev);
++	if (r) {
++		dev_err(adev->dev, "IB initialization failed (%d).\n", r);
++		return r;
++	}
++
++	r = amdgpu_ib_ring_tests(adev);
++	if (r)
++		DRM_ERROR("ib ring test failed (%d).\n", r);
++
++	r = amdgpu_gem_debugfs_init(adev);
++	if (r) {
++		DRM_ERROR("registering gem debugfs failed (%d).\n", r);
++	}
++
++	r = amdgpu_debugfs_regs_init(adev);
++	if (r) {
++		DRM_ERROR("registering register debugfs failed (%d).\n", r);
++	}
++
++	if ((amdgpu_testing & 1)) {
++		if (adev->accel_working)
++			amdgpu_test_moves(adev);
++		else
++			DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
++	}
++	if ((amdgpu_testing & 2)) {
++		if (adev->accel_working)
++			amdgpu_test_syncing(adev);
++		else
++			DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
++	}
++	if (amdgpu_benchmarking) {
++		if (adev->accel_working)
++			amdgpu_benchmark(adev, amdgpu_benchmarking);
++		else
++			DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
++	}
++
++	/* enable clockgating, etc. after ib tests, etc. since some blocks require
++	 * explicit gating rather than handling it automatically.
++	 */
++	r = amdgpu_late_init(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
++
++/**
++ * amdgpu_device_fini - tear down the driver
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down the driver info (all asics).
++ * Called at driver shutdown.
++ */
++void amdgpu_device_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	DRM_INFO("amdgpu: finishing device.\n");
++	adev->shutdown = true;
++	/* evict vram memory */
++	amdgpu_bo_evict_vram(adev);
++	amdgpu_ib_pool_fini(adev);
++	amdgpu_fence_driver_fini(adev);
++	amdgpu_fbdev_fini(adev);
++	r = amdgpu_fini(adev);
++	if (adev->ip_block_enabled)
++		kfree(adev->ip_block_enabled);
++	adev->ip_block_enabled = NULL;
++	adev->accel_working = false;
++	/* free i2c buses */
++	amdgpu_i2c_fini(adev);
++	amdgpu_atombios_fini(adev);
++	kfree(adev->bios);
++	adev->bios = NULL;
++	vga_switcheroo_unregister_client(adev->pdev);
++	vga_client_register(adev->pdev, NULL, NULL, NULL);
++	if (adev->rio_mem)
++		pci_iounmap(adev->pdev, adev->rio_mem);
++	adev->rio_mem = NULL;
++	iounmap(adev->rmmio);
++	adev->rmmio = NULL;
++	amdgpu_doorbell_fini(adev);
++	amdgpu_debugfs_regs_cleanup(adev);
++	amdgpu_debugfs_remove_files(adev);
++}
++
++
++/*
++ * Suspend & resume.
++ */
++/**
++ * amdgpu_suspend_kms - initiate device suspend
++ *
++ * @pdev: drm dev pointer
++ * @state: suspend state
++ *
++ * Puts the hw in the suspend state (all asics).
++ * Returns 0 for success or an error on failure.
++ * Called at driver suspend.
++ */
++int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
++{
++	struct amdgpu_device *adev;
++	struct drm_crtc *crtc;
++	struct drm_connector *connector;
++	int i, r;
++	bool force_completion = false;
++
++	if (dev == NULL || dev->dev_private == NULL) {
++		return -ENODEV;
++	}
++
++	adev = dev->dev_private;
++
++	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
++		return 0;
++
++	drm_kms_helper_poll_disable(dev);
++
++	/* turn off display hw */
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
++	}
++
++	/* unpin the front buffers */
++	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
++		struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
++		struct amdgpu_bo *robj;
++
++		if (rfb == NULL || rfb->obj == NULL) {
++			continue;
++		}
++		robj = gem_to_amdgpu_bo(rfb->obj);
++		/* don't unpin kernel fb objects */
++		if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
++			r = amdgpu_bo_reserve(robj, false);
++			if (r == 0) {
++				amdgpu_bo_unpin(robj);
++				amdgpu_bo_unreserve(robj);
++			}
++		}
++	}
++	/* evict vram memory */
++	amdgpu_bo_evict_vram(adev);
++
++	/* wait for gpu to finish processing current batch */
++	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
++		struct amdgpu_ring *ring = adev->rings[i];
++		if (!ring)
++			continue;
++
++		r = amdgpu_fence_wait_empty(ring);
++		if (r) {
++			/* delay GPU reset to resume */
++			force_completion = true;
++		}
++	}
++	if (force_completion) {
++		amdgpu_fence_driver_force_completion(adev);
++	}
++
++	r = amdgpu_suspend(adev);
++
++	/* evict remaining vram memory */
++	amdgpu_bo_evict_vram(adev);
++
++	pci_save_state(dev->pdev);
++	if (suspend) {
++		/* Shut down the device */
++		pci_disable_device(dev->pdev);
++		pci_set_power_state(dev->pdev, PCI_D3hot);
++	}
++
++	if (fbcon) {
++		console_lock();
++		amdgpu_fbdev_set_suspend(adev, 1);
++		console_unlock();
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_resume_kms - initiate device resume
++ *
++ * @pdev: drm dev pointer
++ *
++ * Bring the hw back to operating state (all asics).
++ * Returns 0 for success or an error on failure.
++ * Called at driver resume.
++ */
++int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
++{
++	struct drm_connector *connector;
++	struct amdgpu_device *adev = dev->dev_private;
++	int r;
++
++	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
++		return 0;
++
++	if (fbcon) {
++		console_lock();
++	}
++	if (resume) {
++		pci_set_power_state(dev->pdev, PCI_D0);
++		pci_restore_state(dev->pdev);
++		if (pci_enable_device(dev->pdev)) {
++			if (fbcon)
++				console_unlock();
++			return -1;
++		}
++	}
++
++	/* post card */
++	amdgpu_atom_asic_init(adev->mode_info.atom_context);
++
++	r = amdgpu_resume(adev);
++
++	r = amdgpu_ib_ring_tests(adev);
++	if (r)
++		DRM_ERROR("ib ring test failed (%d).\n", r);
++
++	r = amdgpu_late_init(adev);
++	if (r)
++		return r;
++
++	/* blat the mode back in */
++	if (fbcon) {
++		drm_helper_resume_force_mode(dev);
++		/* turn on display hw */
++		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
++		}
++	}
++
++	drm_kms_helper_poll_enable(dev);
++
++	if (fbcon) {
++		amdgpu_fbdev_set_suspend(adev, 0);
++		console_unlock();
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_gpu_reset - reset the asic
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Attempt the reset the GPU if it has hung (all asics).
++ * Returns 0 for success or an error on failure.
++ */
++int amdgpu_gpu_reset(struct amdgpu_device *adev)
++{
++	unsigned ring_sizes[AMDGPU_MAX_RINGS];
++	uint32_t *ring_data[AMDGPU_MAX_RINGS];
++
++	bool saved = false;
++
++	int i, r;
++	int resched;
++
++	down_write(&adev->exclusive_lock);
++
++	if (!adev->needs_reset) {
++		up_write(&adev->exclusive_lock);
++		return 0;
++	}
++
++	adev->needs_reset = false;
++
++	/* block TTM */
++	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
++
++	r = amdgpu_suspend(adev);
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		struct amdgpu_ring *ring = adev->rings[i];
++		if (!ring)
++			continue;
++
++		ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
++		if (ring_sizes[i]) {
++			saved = true;
++			dev_info(adev->dev, "Saved %d dwords of commands "
++				 "on ring %d.\n", ring_sizes[i], i);
++		}
++	}
++
++retry:
++	r = amdgpu_asic_reset(adev);
++	if (!r) {
++		dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
++		r = amdgpu_resume(adev);
++	}
++
++	if (!r) {
++		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++			struct amdgpu_ring *ring = adev->rings[i];
++			if (!ring)
++				continue;
++
++			amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
++			ring_sizes[i] = 0;
++			ring_data[i] = NULL;
++		}
++
++		r = amdgpu_ib_ring_tests(adev);
++		if (r) {
++			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
++			if (saved) {
++				saved = false;
++				r = amdgpu_suspend(adev);
++				goto retry;
++			}
++		}
++	} else {
++		amdgpu_fence_driver_force_completion(adev);
++		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++			if (adev->rings[i])
++				kfree(ring_data[i]);
++		}
++	}
++
++	drm_helper_resume_force_mode(adev->ddev);
++
++	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
++	if (r) {
++		/* bad news, how to tell it to userspace ? */
++		dev_info(adev->dev, "GPU reset failed\n");
++	}
++
++	up_write(&adev->exclusive_lock);
++	return r;
++}
++
++
++/*
++ * Debugfs
++ */
++int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
++			     struct drm_info_list *files,
++			     unsigned nfiles)
++{
++	unsigned i;
++
++	for (i = 0; i < adev->debugfs_count; i++) {
++		if (adev->debugfs[i].files == files) {
++			/* Already registered */
++			return 0;
++		}
++	}
++
++	i = adev->debugfs_count + 1;
++	if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
++		DRM_ERROR("Reached maximum number of debugfs components.\n");
++		DRM_ERROR("Report so we increase "
++			  "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
++		return -EINVAL;
++	}
++	adev->debugfs[adev->debugfs_count].files = files;
++	adev->debugfs[adev->debugfs_count].num_files = nfiles;
++	adev->debugfs_count = i;
++#if defined(CONFIG_DEBUG_FS)
++	drm_debugfs_create_files(files, nfiles,
++				 adev->ddev->control->debugfs_root,
++				 adev->ddev->control);
++	drm_debugfs_create_files(files, nfiles,
++				 adev->ddev->primary->debugfs_root,
++				 adev->ddev->primary);
++#endif
++	return 0;
++}
++
++static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++	unsigned i;
++
++	for (i = 0; i < adev->debugfs_count; i++) {
++		drm_debugfs_remove_files(adev->debugfs[i].files,
++					 adev->debugfs[i].num_files,
++					 adev->ddev->control);
++		drm_debugfs_remove_files(adev->debugfs[i].files,
++					 adev->debugfs[i].num_files,
++					 adev->ddev->primary);
++	}
++#endif
++}
++
++#if defined(CONFIG_DEBUG_FS)
++
++static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
++					size_t size, loff_t *pos)
++{
++	struct amdgpu_device *adev = f->f_inode->i_private;
++	ssize_t result = 0;
++	int r;
++
++	if (size & 0x3 || *pos & 0x3)
++		return -EINVAL;
++
++	while (size) {
++		uint32_t value;
++
++		if (*pos > adev->rmmio_size)
++			return result;
++
++		value = RREG32(*pos >> 2);
++		r = put_user(value, (uint32_t *)buf);
++		if (r)
++			return r;
++
++		result += 4;
++		buf += 4;
++		*pos += 4;
++		size -= 4;
++	}
++
++	return result;
++}
++
++static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
++					 size_t size, loff_t *pos)
++{
++	struct amdgpu_device *adev = f->f_inode->i_private;
++	ssize_t result = 0;
++	int r;
++
++	if (size & 0x3 || *pos & 0x3)
++		return -EINVAL;
++
++	while (size) {
++		uint32_t value;
++
++		if (*pos > adev->rmmio_size)
++			return result;
++
++		r = get_user(value, (uint32_t *)buf);
++		if (r)
++			return r;
++
++		WREG32(*pos >> 2, value);
++
++		result += 4;
++		buf += 4;
++		*pos += 4;
++		size -= 4;
++	}
++
++	return result;
++}
++
++static const struct file_operations amdgpu_debugfs_regs_fops = {
++	.owner = THIS_MODULE,
++	.read = amdgpu_debugfs_regs_read,
++	.write = amdgpu_debugfs_regs_write,
++	.llseek = default_llseek
++};
++
++static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
++{
++	struct drm_minor *minor = adev->ddev->primary;
++	struct dentry *ent, *root = minor->debugfs_root;
++
++	ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
++				  adev, &amdgpu_debugfs_regs_fops);
++	if (IS_ERR(ent))
++		return PTR_ERR(ent);
++	i_size_write(ent->d_inode, adev->rmmio_size);
++	adev->debugfs_regs = ent;
++
++	return 0;
++}
++
++static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
++{
++	debugfs_remove(adev->debugfs_regs);
++	adev->debugfs_regs = NULL;
++}
++
++int amdgpu_debugfs_init(struct drm_minor *minor)
++{
++	return 0;
++}
++
++void amdgpu_debugfs_cleanup(struct drm_minor *minor)
++{
++}
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+new file mode 100644
+index 0000000..f22c067
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -0,0 +1,832 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_i2c.h"
++#include "atom.h"
++#include "amdgpu_connectors.h"
++#include <asm/div64.h>
++
++#include <linux/pm_runtime.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_edid.h>
++
++
++static void amdgpu_flip_work_func(struct work_struct *__work)
++{
++	struct amdgpu_flip_work *work =
++		container_of(__work, struct amdgpu_flip_work, flip_work);
++	struct amdgpu_device *adev = work->adev;
++	struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
++
++	struct drm_crtc *crtc = &amdgpuCrtc->base;
++	struct amdgpu_fence *fence;
++	unsigned long flags;
++	int r;
++
++	down_read(&adev->exclusive_lock);
++	if (work->fence) {
++		fence = to_amdgpu_fence(work->fence);
++		if (fence) {
++			r = amdgpu_fence_wait(fence, false);
++			if (r == -EDEADLK) {
++				up_read(&adev->exclusive_lock);
++				r = amdgpu_gpu_reset(adev);
++				down_read(&adev->exclusive_lock);
++			}
++		} else
++			r = fence_wait(work->fence, false);
++
++		if (r)
++			DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
++
++		/* We continue with the page flip even if we failed to wait on
++		 * the fence, otherwise the DRM core and userspace will be
++		 * confused about which BO the CRTC is scanning out
++		 */
++
++		fence_put(work->fence);
++		work->fence = NULL;
++	}
++
++	/* We borrow the event spin lock for protecting flip_status */
++	spin_lock_irqsave(&crtc->dev->event_lock, flags);
++
++	/* set the proper interrupt */
++	amdgpu_irq_get(adev, &adev->pageflip_irq, work->crtc_id);
++	/* do the flip (mmio) */
++	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
++	/* set the flip status */
++	amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
++
++	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
++	up_read(&adev->exclusive_lock);
++}
++
++/*
++ * Handle unpin events outside the interrupt handler proper.
++ */
++static void amdgpu_unpin_work_func(struct work_struct *__work)
++{
++	struct amdgpu_flip_work *work =
++		container_of(__work, struct amdgpu_flip_work, unpin_work);
++	int r;
++
++	/* unpin of the old buffer */
++	r = amdgpu_bo_reserve(work->old_rbo, false);
++	if (likely(r == 0)) {
++		r = amdgpu_bo_unpin(work->old_rbo);
++		if (unlikely(r != 0)) {
++			DRM_ERROR("failed to unpin buffer after flip\n");
++		}
++		amdgpu_bo_unreserve(work->old_rbo);
++	} else
++		DRM_ERROR("failed to reserve buffer after flip\n");
++
++	drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
++	kfree(work);
++}
++
++int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
++			  struct drm_framebuffer *fb,
++			  struct drm_pending_vblank_event *event,
++			  uint32_t page_flip_flags)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_framebuffer *old_amdgpu_fb;
++	struct amdgpu_framebuffer *new_amdgpu_fb;
++	struct drm_gem_object *obj;
++	struct amdgpu_flip_work *work;
++	struct amdgpu_bo *new_rbo;
++	unsigned long flags;
++	u64 tiling_flags;
++	u64 base;
++	int r;
++
++	work = kzalloc(sizeof *work, GFP_KERNEL);
++	if (work == NULL)
++		return -ENOMEM;
++
++	INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
++	INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
++
++	work->event = event;
++	work->adev = adev;
++	work->crtc_id = amdgpu_crtc->crtc_id;
++
++	/* schedule unpin of the old buffer */
++	old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++	obj = old_amdgpu_fb->obj;
++
++	/* take a reference to the old object */
++	drm_gem_object_reference(obj);
++	work->old_rbo = gem_to_amdgpu_bo(obj);
++
++	new_amdgpu_fb = to_amdgpu_framebuffer(fb);
++	obj = new_amdgpu_fb->obj;
++	new_rbo = gem_to_amdgpu_bo(obj);
++
++	/* pin the new buffer */
++	r = amdgpu_bo_reserve(new_rbo, false);
++	if (unlikely(r != 0)) {
++		DRM_ERROR("failed to reserve new rbo buffer before flip\n");
++		goto cleanup;
++	}
++
++	r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, &base);
++	if (unlikely(r != 0)) {
++		amdgpu_bo_unreserve(new_rbo);
++		r = -EINVAL;
++		DRM_ERROR("failed to pin new rbo buffer before flip\n");
++		goto cleanup;
++	}
++
++	work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
++	amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
++	amdgpu_bo_unreserve(new_rbo);
++
++	work->base = base;
++
++	r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
++	if (r) {
++		DRM_ERROR("failed to get vblank before flip\n");
++		goto pflip_cleanup;
++	}
++
++	/* we borrow the event spin lock for protecting flip_wrok */
++	spin_lock_irqsave(&crtc->dev->event_lock, flags);
++	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
++		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
++		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
++		r = -EBUSY;
++		goto vblank_cleanup;
++	}
++
++	amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
++	amdgpu_crtc->pflip_works = work;
++
++	/* update crtc fb */
++	crtc->primary->fb = fb;
++	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
++	queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
++	return 0;
++
++vblank_cleanup:
++	drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
++
++pflip_cleanup:
++	if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
++		DRM_ERROR("failed to reserve new rbo in error path\n");
++		goto cleanup;
++	}
++	if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
++		DRM_ERROR("failed to unpin new rbo in error path\n");
++	}
++	amdgpu_bo_unreserve(new_rbo);
++
++cleanup:
++	drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
++	fence_put(work->fence);
++	kfree(work);
++
++	return r;
++}
++
++int amdgpu_crtc_set_config(struct drm_mode_set *set)
++{
++	struct drm_device *dev;
++	struct amdgpu_device *adev;
++	struct drm_crtc *crtc;
++	bool active = false;
++	int ret;
++
++	if (!set || !set->crtc)
++		return -EINVAL;
++
++	dev = set->crtc->dev;
++
++	ret = pm_runtime_get_sync(dev->dev);
++	if (ret < 0)
++		return ret;
++
++	ret = drm_crtc_helper_set_config(set);
++
++	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
++		if (crtc->enabled)
++			active = true;
++
++	pm_runtime_mark_last_busy(dev->dev);
++
++	adev = dev->dev_private;
++	/* if we have active crtcs and we don't have a power ref,
++	   take the current one */
++	if (active && !adev->have_disp_power_ref) {
++		adev->have_disp_power_ref = true;
++		return ret;
++	}
++	/* if we have no active crtcs, then drop the power ref
++	   we got before */
++	if (!active && adev->have_disp_power_ref) {
++		pm_runtime_put_autosuspend(dev->dev);
++		adev->have_disp_power_ref = false;
++	}
++
++	/* drop the power reference we got coming in here */
++	pm_runtime_put_autosuspend(dev->dev);
++	return ret;
++}
++
++static const char *encoder_names[38] = {
++	"NONE",
++	"INTERNAL_LVDS",
++	"INTERNAL_TMDS1",
++	"INTERNAL_TMDS2",
++	"INTERNAL_DAC1",
++	"INTERNAL_DAC2",
++	"INTERNAL_SDVOA",
++	"INTERNAL_SDVOB",
++	"SI170B",
++	"CH7303",
++	"CH7301",
++	"INTERNAL_DVO1",
++	"EXTERNAL_SDVOA",
++	"EXTERNAL_SDVOB",
++	"TITFP513",
++	"INTERNAL_LVTM1",
++	"VT1623",
++	"HDMI_SI1930",
++	"HDMI_INTERNAL",
++	"INTERNAL_KLDSCP_TMDS1",
++	"INTERNAL_KLDSCP_DVO1",
++	"INTERNAL_KLDSCP_DAC1",
++	"INTERNAL_KLDSCP_DAC2",
++	"SI178",
++	"MVPU_FPGA",
++	"INTERNAL_DDI",
++	"VT1625",
++	"HDMI_SI1932",
++	"DP_AN9801",
++	"DP_DP501",
++	"INTERNAL_UNIPHY",
++	"INTERNAL_KLDSCP_LVTMA",
++	"INTERNAL_UNIPHY1",
++	"INTERNAL_UNIPHY2",
++	"NUTMEG",
++	"TRAVIS",
++	"INTERNAL_VCE",
++	"INTERNAL_UNIPHY3",
++};
++
++static const char *hpd_names[6] = {
++	"HPD1",
++	"HPD2",
++	"HPD3",
++	"HPD4",
++	"HPD5",
++	"HPD6",
++};
++
++void amdgpu_print_display_setup(struct drm_device *dev)
++{
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++	uint32_t devices;
++	int i = 0;
++
++	DRM_INFO("AMDGPU Display Connectors\n");
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		amdgpu_connector = to_amdgpu_connector(connector);
++		DRM_INFO("Connector %d:\n", i);
++		DRM_INFO("  %s\n", connector->name);
++		if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
++			DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
++		if (amdgpu_connector->ddc_bus) {
++			DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++				 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
++				 amdgpu_connector->ddc_bus->rec.mask_data_reg,
++				 amdgpu_connector->ddc_bus->rec.a_clk_reg,
++				 amdgpu_connector->ddc_bus->rec.a_data_reg,
++				 amdgpu_connector->ddc_bus->rec.en_clk_reg,
++				 amdgpu_connector->ddc_bus->rec.en_data_reg,
++				 amdgpu_connector->ddc_bus->rec.y_clk_reg,
++				 amdgpu_connector->ddc_bus->rec.y_data_reg);
++			if (amdgpu_connector->router.ddc_valid)
++				DRM_INFO("  DDC Router 0x%x/0x%x\n",
++					 amdgpu_connector->router.ddc_mux_control_pin,
++					 amdgpu_connector->router.ddc_mux_state);
++			if (amdgpu_connector->router.cd_valid)
++				DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
++					 amdgpu_connector->router.cd_mux_control_pin,
++					 amdgpu_connector->router.cd_mux_state);
++		} else {
++			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
++			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
++			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
++			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
++			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
++			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
++				DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
++		}
++		DRM_INFO("  Encoders:\n");
++		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++			amdgpu_encoder = to_amdgpu_encoder(encoder);
++			devices = amdgpu_encoder->devices & amdgpu_connector->devices;
++			if (devices) {
++				if (devices & ATOM_DEVICE_CRT1_SUPPORT)
++					DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_CRT2_SUPPORT)
++					DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_LCD1_SUPPORT)
++					DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_DFP1_SUPPORT)
++					DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_DFP2_SUPPORT)
++					DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_DFP3_SUPPORT)
++					DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_DFP4_SUPPORT)
++					DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_DFP5_SUPPORT)
++					DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_DFP6_SUPPORT)
++					DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_TV1_SUPPORT)
++					DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++				if (devices & ATOM_DEVICE_CV_SUPPORT)
++					DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
++			}
++		}
++		i++;
++	}
++}
++
++/**
++ * amdgpu_ddc_probe
++ *
++ */
++bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
++		       bool use_aux)
++{
++	u8 out = 0x0;
++	u8 buf[8];
++	int ret;
++	struct i2c_msg msgs[] = {
++		{
++			.addr = DDC_ADDR,
++			.flags = 0,
++			.len = 1,
++			.buf = &out,
++		},
++		{
++			.addr = DDC_ADDR,
++			.flags = I2C_M_RD,
++			.len = 8,
++			.buf = buf,
++		}
++	};
++
++	/* on hw with routers, select right port */
++	if (amdgpu_connector->router.ddc_valid)
++		amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
++
++	if (use_aux) {
++		ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
++	} else {
++		ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
++	}
++
++	if (ret != 2)
++		/* Couldn't find an accessible DDC on this connector */
++		return false;
++	/* Probe also for valid EDID header
++	 * EDID header starts with:
++	 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
++	 * Only the first 6 bytes must be valid as
++	 * drm_edid_block_valid() can fix the last 2 bytes */
++	if (drm_edid_header_is_valid(buf) < 6) {
++		/* Couldn't find an accessible EDID on this
++		 * connector */
++		return false;
++	}
++	return true;
++}
++
++static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
++{
++	struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
++
++	if (amdgpu_fb->obj) {
++		drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
++	}
++	drm_framebuffer_cleanup(fb);
++	kfree(amdgpu_fb);
++}
++
++static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
++						  struct drm_file *file_priv,
++						  unsigned int *handle)
++{
++	struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
++
++	return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
++}
++
++static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
++	.destroy = amdgpu_user_framebuffer_destroy,
++	.create_handle = amdgpu_user_framebuffer_create_handle,
++};
++
++int
++amdgpu_framebuffer_init(struct drm_device *dev,
++			struct amdgpu_framebuffer *rfb,
++			struct drm_mode_fb_cmd2 *mode_cmd,
++			struct drm_gem_object *obj)
++{
++	int ret;
++	rfb->obj = obj;
++	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
++	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
++	if (ret) {
++		rfb->obj = NULL;
++		return ret;
++	}
++	return 0;
++}
++
++static struct drm_framebuffer *
++amdgpu_user_framebuffer_create(struct drm_device *dev,
++			       struct drm_file *file_priv,
++			       struct drm_mode_fb_cmd2 *mode_cmd)
++{
++	struct drm_gem_object *obj;
++	struct amdgpu_framebuffer *amdgpu_fb;
++	int ret;
++
++	obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
++	if (obj ==  NULL) {
++		dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
++			"can't create framebuffer\n", mode_cmd->handles[0]);
++		return ERR_PTR(-ENOENT);
++	}
++
++	amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
++	if (amdgpu_fb == NULL) {
++		drm_gem_object_unreference_unlocked(obj);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
++	if (ret) {
++		kfree(amdgpu_fb);
++		drm_gem_object_unreference_unlocked(obj);
++		return ERR_PTR(ret);
++	}
++
++	return &amdgpu_fb->base;
++}
++
++static void amdgpu_output_poll_changed(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	amdgpu_fb_output_poll_changed(adev);
++}
++
++const struct drm_mode_config_funcs amdgpu_mode_funcs = {
++	.fb_create = amdgpu_user_framebuffer_create,
++	.output_poll_changed = amdgpu_output_poll_changed
++};
++
++static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
++{	{ UNDERSCAN_OFF, "off" },
++	{ UNDERSCAN_ON, "on" },
++	{ UNDERSCAN_AUTO, "auto" },
++};
++
++static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
++{	{ AMDGPU_AUDIO_DISABLE, "off" },
++	{ AMDGPU_AUDIO_ENABLE, "on" },
++	{ AMDGPU_AUDIO_AUTO, "auto" },
++};
++
++/* XXX support different dither options? spatial, temporal, both, etc. */
++static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
++{	{ AMDGPU_FMT_DITHER_DISABLE, "off" },
++	{ AMDGPU_FMT_DITHER_ENABLE, "on" },
++};
++
++int amdgpu_modeset_create_props(struct amdgpu_device *adev)
++{
++	int sz;
++
++	if (adev->is_atom_bios) {
++		adev->mode_info.coherent_mode_property =
++			drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
++		if (!adev->mode_info.coherent_mode_property)
++			return -ENOMEM;
++	}
++
++	adev->mode_info.load_detect_property =
++		drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
++	if (!adev->mode_info.load_detect_property)
++		return -ENOMEM;
++
++	drm_mode_create_scaling_mode_property(adev->ddev);
++
++	sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
++	adev->mode_info.underscan_property =
++		drm_property_create_enum(adev->ddev, 0,
++				    "underscan",
++				    amdgpu_underscan_enum_list, sz);
++
++	adev->mode_info.underscan_hborder_property =
++		drm_property_create_range(adev->ddev, 0,
++					"underscan hborder", 0, 128);
++	if (!adev->mode_info.underscan_hborder_property)
++		return -ENOMEM;
++
++	adev->mode_info.underscan_vborder_property =
++		drm_property_create_range(adev->ddev, 0,
++					"underscan vborder", 0, 128);
++	if (!adev->mode_info.underscan_vborder_property)
++		return -ENOMEM;
++
++	sz = ARRAY_SIZE(amdgpu_audio_enum_list);
++	adev->mode_info.audio_property =
++		drm_property_create_enum(adev->ddev, 0,
++					 "audio",
++					 amdgpu_audio_enum_list, sz);
++
++	sz = ARRAY_SIZE(amdgpu_dither_enum_list);
++	adev->mode_info.dither_property =
++		drm_property_create_enum(adev->ddev, 0,
++					 "dither",
++					 amdgpu_dither_enum_list, sz);
++
++	return 0;
++}
++
++void amdgpu_update_display_priority(struct amdgpu_device *adev)
++{
++	/* adjustment options for the display watermarks */
++	if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
++		adev->mode_info.disp_priority = 0;
++	else
++		adev->mode_info.disp_priority = amdgpu_disp_priority;
++
++}
++
++static bool is_hdtv_mode(const struct drm_display_mode *mode)
++{
++	/* try and guess if this is a tv or a monitor */
++	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
++	    (mode->vdisplay == 576) || /* 576p */
++	    (mode->vdisplay == 720) || /* 720p */
++	    (mode->vdisplay == 1080)) /* 1080p */
++		return true;
++	else
++		return false;
++}
++
++bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
++				    const struct drm_display_mode *mode,
++				    struct drm_display_mode *adjusted_mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct drm_encoder *encoder;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_encoder *amdgpu_encoder;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++	u32 src_v = 1, dst_v = 1;
++	u32 src_h = 1, dst_h = 1;
++
++	amdgpu_crtc->h_border = 0;
++	amdgpu_crtc->v_border = 0;
++
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		if (encoder->crtc != crtc)
++			continue;
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++		connector = amdgpu_get_connector_for_encoder(encoder);
++		amdgpu_connector = to_amdgpu_connector(connector);
++
++		/* set scaling */
++		if (amdgpu_encoder->rmx_type == RMX_OFF)
++			amdgpu_crtc->rmx_type = RMX_OFF;
++		else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
++			 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
++			amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
++		else
++			amdgpu_crtc->rmx_type = RMX_OFF;
++		/* copy native mode */
++		memcpy(&amdgpu_crtc->native_mode,
++		       &amdgpu_encoder->native_mode,
++		       sizeof(struct drm_display_mode));
++		src_v = crtc->mode.vdisplay;
++		dst_v = amdgpu_crtc->native_mode.vdisplay;
++		src_h = crtc->mode.hdisplay;
++		dst_h = amdgpu_crtc->native_mode.hdisplay;
++
++		/* fix up for overscan on hdmi */
++		if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
++		    ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
++		     ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
++		      drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
++		      is_hdtv_mode(mode)))) {
++			if (amdgpu_encoder->underscan_hborder != 0)
++				amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
++			else
++				amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
++			if (amdgpu_encoder->underscan_vborder != 0)
++				amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
++			else
++				amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
++			amdgpu_crtc->rmx_type = RMX_FULL;
++			src_v = crtc->mode.vdisplay;
++			dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
++			src_h = crtc->mode.hdisplay;
++			dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
++		}
++	}
++	if (amdgpu_crtc->rmx_type != RMX_OFF) {
++		fixed20_12 a, b;
++		a.full = dfixed_const(src_v);
++		b.full = dfixed_const(dst_v);
++		amdgpu_crtc->vsc.full = dfixed_div(a, b);
++		a.full = dfixed_const(src_h);
++		b.full = dfixed_const(dst_h);
++		amdgpu_crtc->hsc.full = dfixed_div(a, b);
++	} else {
++		amdgpu_crtc->vsc.full = dfixed_const(1);
++		amdgpu_crtc->hsc.full = dfixed_const(1);
++	}
++	return true;
++}
++
++/*
++ * Retrieve current video scanout position of crtc on a given gpu, and
++ * an optional accurate timestamp of when query happened.
++ *
++ * \param dev Device to query.
++ * \param crtc Crtc to query.
++ * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
++ * \param *vpos Location where vertical scanout position should be stored.
++ * \param *hpos Location where horizontal scanout position should go.
++ * \param *stime Target location for timestamp taken immediately before
++ *               scanout position query. Can be NULL to skip timestamp.
++ * \param *etime Target location for timestamp taken immediately after
++ *               scanout position query. Can be NULL to skip timestamp.
++ *
++ * Returns vpos as a positive number while in active scanout area.
++ * Returns vpos as a negative number inside vblank, counting the number
++ * of scanlines to go until end of vblank, e.g., -1 means "one scanline
++ * until start of active scanout / end of vblank."
++ *
++ * \return Flags, or'ed together as follows:
++ *
++ * DRM_SCANOUTPOS_VALID = Query successful.
++ * DRM_SCANOUTPOS_INVBL = Inside vblank.
++ * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
++ * this flag means that returned position may be offset by a constant but
++ * unknown small number of scanlines wrt. real scanout position.
++ *
++ */
++int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
++			       int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
++{
++	u32 vbl = 0, position = 0;
++	int vbl_start, vbl_end, vtotal, ret = 0;
++	bool in_vbl = true;
++
++	struct amdgpu_device *adev = dev->dev_private;
++
++	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
++
++	/* Get optional system timestamp before query. */
++	if (stime)
++		*stime = ktime_get();
++
++	if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0)
++		ret |= DRM_SCANOUTPOS_VALID;
++
++	/* Get optional system timestamp after query. */
++	if (etime)
++		*etime = ktime_get();
++
++	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
++
++	/* Decode into vertical and horizontal scanout position. */
++	*vpos = position & 0x1fff;
++	*hpos = (position >> 16) & 0x1fff;
++
++	/* Valid vblank area boundaries from gpu retrieved? */
++	if (vbl > 0) {
++		/* Yes: Decode. */
++		ret |= DRM_SCANOUTPOS_ACCURATE;
++		vbl_start = vbl & 0x1fff;
++		vbl_end = (vbl >> 16) & 0x1fff;
++	}
++	else {
++		/* No: Fake something reasonable which gives at least ok results. */
++		vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
++		vbl_end = 0;
++	}
++
++	/* Test scanout position against vblank region. */
++	if ((*vpos < vbl_start) && (*vpos >= vbl_end))
++		in_vbl = false;
++
++	/* Check if inside vblank area and apply corrective offsets:
++	 * vpos will then be >=0 in video scanout area, but negative
++	 * within vblank area, counting down the number of lines until
++	 * start of scanout.
++	 */
++
++	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
++	if (in_vbl && (*vpos >= vbl_start)) {
++		vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
++		*vpos = *vpos - vtotal;
++	}
++
++	/* Correct for shifted end of vbl at vbl_end. */
++	*vpos = *vpos - vbl_end;
++
++	/* In vblank? */
++	if (in_vbl)
++		ret |= DRM_SCANOUTPOS_IN_VBLANK;
++
++	/* Is vpos outside nominal vblank area, but less than
++	 * 1/100 of a frame height away from start of vblank?
++	 * If so, assume this isn't a massively delayed vblank
++	 * interrupt, but a vblank interrupt that fired a few
++	 * microseconds before true start of vblank. Compensate
++	 * by adding a full frame duration to the final timestamp.
++	 * Happens, e.g., on ATI R500, R600.
++	 *
++	 * We only do this if DRM_CALLED_FROM_VBLIRQ.
++	 */
++	if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
++		vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
++		vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
++
++		if (vbl_start - *vpos < vtotal / 100) {
++			*vpos -= vtotal;
++
++			/* Signal this correction as "applied". */
++			ret |= 0x8;
++		}
++	}
++
++	return ret;
++}
++
++int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
++{
++	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
++		return AMDGPU_CRTC_IRQ_NONE;
++
++	switch (crtc) {
++	case 0:
++		return AMDGPU_CRTC_IRQ_VBLANK1;
++	case 1:
++		return AMDGPU_CRTC_IRQ_VBLANK2;
++	case 2:
++		return AMDGPU_CRTC_IRQ_VBLANK3;
++	case 3:
++		return AMDGPU_CRTC_IRQ_VBLANK4;
++	case 4:
++		return AMDGPU_CRTC_IRQ_VBLANK5;
++	case 5:
++		return AMDGPU_CRTC_IRQ_VBLANK6;
++	default:
++		return AMDGPU_CRTC_IRQ_NONE;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+new file mode 100644
+index 0000000..7b7f4ab
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+@@ -0,0 +1,955 @@
++/*
++ * Copyright 2011 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_i2c.h"
++#include "amdgpu_dpm.h"
++#include "atom.h"
++
++void amdgpu_dpm_print_class_info(u32 class, u32 class2)
++{
++	printk("\tui class: ");
++	switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
++	case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
++	default:
++		printk("none\n");
++		break;
++	case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
++		printk("battery\n");
++		break;
++	case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
++		printk("balanced\n");
++		break;
++	case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
++		printk("performance\n");
++		break;
++	}
++	printk("\tinternal class: ");
++	if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
++	    (class2 == 0))
++		printk("none");
++	else {
++		if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
++			printk("boot ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
++			printk("thermal ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
++			printk("limited_pwr ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_REST)
++			printk("rest ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
++			printk("forced ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
++			printk("3d_perf ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
++			printk("ovrdrv ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
++			printk("uvd ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
++			printk("3d_low ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
++			printk("acpi ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
++			printk("uvd_hd2 ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
++			printk("uvd_hd ");
++		if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
++			printk("uvd_sd ");
++		if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
++			printk("limited_pwr2 ");
++		if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
++			printk("ulv ");
++		if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
++			printk("uvd_mvc ");
++	}
++	printk("\n");
++}
++
++void amdgpu_dpm_print_cap_info(u32 caps)
++{
++	printk("\tcaps: ");
++	if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
++		printk("single_disp ");
++	if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
++		printk("video ");
++	if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
++		printk("no_dc ");
++	printk("\n");
++}
++
++void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
++				struct amdgpu_ps *rps)
++{
++	printk("\tstatus: ");
++	if (rps == adev->pm.dpm.current_ps)
++		printk("c ");
++	if (rps == adev->pm.dpm.requested_ps)
++		printk("r ");
++	if (rps == adev->pm.dpm.boot_ps)
++		printk("b ");
++	printk("\n");
++}
++
++u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_crtc *crtc;
++	struct amdgpu_crtc *amdgpu_crtc;
++	u32 line_time_us, vblank_lines;
++	u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
++
++	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
++		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
++			amdgpu_crtc = to_amdgpu_crtc(crtc);
++			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
++				line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
++					amdgpu_crtc->hw_mode.clock;
++				vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
++					amdgpu_crtc->hw_mode.crtc_vdisplay +
++					(amdgpu_crtc->v_border * 2);
++				vblank_time_us = vblank_lines * line_time_us;
++				break;
++			}
++		}
++	}
++
++	return vblank_time_us;
++}
++
++u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_crtc *crtc;
++	struct amdgpu_crtc *amdgpu_crtc;
++	u32 vrefresh = 0;
++
++	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
++		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
++			amdgpu_crtc = to_amdgpu_crtc(crtc);
++			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
++				vrefresh = amdgpu_crtc->hw_mode.vrefresh;
++				break;
++			}
++		}
++	}
++
++	return vrefresh;
++}
++
++void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
++			      u32 *p, u32 *u)
++{
++	u32 b_c = 0;
++	u32 i_c;
++	u32 tmp;
++
++	i_c = (i * r_c) / 100;
++	tmp = i_c >> p_b;
++
++	while (tmp) {
++		b_c++;
++		tmp >>= 1;
++	}
++
++	*u = (b_c + 1) / 2;
++	*p = i_c / (1 << (2 * (*u)));
++}
++
++int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
++{
++	u32 k, a, ah, al;
++	u32 t1;
++
++	if ((fl == 0) || (fh == 0) || (fl > fh))
++		return -EINVAL;
++
++	k = (100 * fh) / fl;
++	t1 = (t * (k - 100));
++	a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
++	a = (a + 5) / 10;
++	ah = ((a * t) + 5000) / 10000;
++	al = a - ah;
++
++	*th = t - ah;
++	*tl = t + al;
++
++	return 0;
++}
++
++bool amdgpu_is_uvd_state(u32 class, u32 class2)
++{
++	if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
++		return true;
++	if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
++		return true;
++	if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
++		return true;
++	if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
++		return true;
++	if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
++		return true;
++	return false;
++}
++
++bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor)
++{
++	switch (sensor) {
++	case THERMAL_TYPE_RV6XX:
++	case THERMAL_TYPE_RV770:
++	case THERMAL_TYPE_EVERGREEN:
++	case THERMAL_TYPE_SUMO:
++	case THERMAL_TYPE_NI:
++	case THERMAL_TYPE_SI:
++	case THERMAL_TYPE_CI:
++	case THERMAL_TYPE_KV:
++		return true;
++	case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
++	case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
++		return false; /* need special handling */
++	case THERMAL_TYPE_NONE:
++	case THERMAL_TYPE_EXTERNAL:
++	case THERMAL_TYPE_EXTERNAL_GPIO:
++	default:
++		return false;
++	}
++}
++
++union power_info {
++	struct _ATOM_POWERPLAY_INFO info;
++	struct _ATOM_POWERPLAY_INFO_V2 info_2;
++	struct _ATOM_POWERPLAY_INFO_V3 info_3;
++	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
++	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
++	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
++	struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
++	struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
++};
++
++union fan_info {
++	struct _ATOM_PPLIB_FANTABLE fan;
++	struct _ATOM_PPLIB_FANTABLE2 fan2;
++	struct _ATOM_PPLIB_FANTABLE3 fan3;
++};
++
++static int amdgpu_parse_clk_voltage_dep_table(struct amdgpu_clock_voltage_dependency_table *amdgpu_table,
++					      ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table)
++{
++	u32 size = atom_table->ucNumEntries *
++		sizeof(struct amdgpu_clock_voltage_dependency_entry);
++	int i;
++	ATOM_PPLIB_Clock_Voltage_Dependency_Record *entry;
++
++	amdgpu_table->entries = kzalloc(size, GFP_KERNEL);
++	if (!amdgpu_table->entries)
++		return -ENOMEM;
++
++	entry = &atom_table->entries[0];
++	for (i = 0; i < atom_table->ucNumEntries; i++) {
++		amdgpu_table->entries[i].clk = le16_to_cpu(entry->usClockLow) |
++			(entry->ucClockHigh << 16);
++		amdgpu_table->entries[i].v = le16_to_cpu(entry->usVoltage);
++		entry = (ATOM_PPLIB_Clock_Voltage_Dependency_Record *)
++			((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));
++	}
++	amdgpu_table->count = atom_table->ucNumEntries;
++
++	return 0;
++}
++
++int amdgpu_get_platform_caps(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	union power_info *power_info;
++	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
++	u16 data_offset;
++	u8 frev, crev;
++
++	if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset))
++		return -EINVAL;
++	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
++
++	adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
++	adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
++	adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
++
++	return 0;
++}
++
++/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8 24
++#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V9 26
++
++int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	union power_info *power_info;
++	union fan_info *fan_info;
++	ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table;
++	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
++	u16 data_offset;
++	u8 frev, crev;
++	int ret, i;
++
++	if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset))
++		return -EINVAL;
++	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
++
++	/* fan table */
++	if (le16_to_cpu(power_info->pplib.usTableSize) >=
++	    sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
++		if (power_info->pplib3.usFanTableOffset) {
++			fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset +
++						      le16_to_cpu(power_info->pplib3.usFanTableOffset));
++			adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
++			adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
++			adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
++			adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
++			adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
++			adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
++			adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
++			if (fan_info->fan.ucFanTableFormat >= 2)
++				adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
++			else
++				adev->pm.dpm.fan.t_max = 10900;
++			adev->pm.dpm.fan.cycle_delay = 100000;
++			if (fan_info->fan.ucFanTableFormat >= 3) {
++				adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode;
++				adev->pm.dpm.fan.default_max_fan_pwm =
++					le16_to_cpu(fan_info->fan3.usFanPWMMax);
++				adev->pm.dpm.fan.default_fan_output_sensitivity = 4836;
++				adev->pm.dpm.fan.fan_output_sensitivity =
++					le16_to_cpu(fan_info->fan3.usFanOutputSensitivity);
++			}
++			adev->pm.dpm.fan.ucode_fan_control = true;
++		}
++	}
++
++	/* clock dependancy tables, shedding tables */
++	if (le16_to_cpu(power_info->pplib.usTableSize) >=
++	    sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
++		if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
++			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
++			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
++								 dep_table);
++			if (ret) {
++				amdgpu_free_extended_power_table(adev);
++				return ret;
++			}
++		}
++		if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
++			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset));
++			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
++								 dep_table);
++			if (ret) {
++				amdgpu_free_extended_power_table(adev);
++				return ret;
++			}
++		}
++		if (power_info->pplib4.usVddcDependencyOnMCLKOffset) {
++			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset));
++			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
++								 dep_table);
++			if (ret) {
++				amdgpu_free_extended_power_table(adev);
++				return ret;
++			}
++		}
++		if (power_info->pplib4.usMvddDependencyOnMCLKOffset) {
++			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset));
++			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
++								 dep_table);
++			if (ret) {
++				amdgpu_free_extended_power_table(adev);
++				return ret;
++			}
++		}
++		if (power_info->pplib4.usMaxClockVoltageOnDCOffset) {
++			ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =
++				(ATOM_PPLIB_Clock_Voltage_Limit_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset));
++			if (clk_v->ucNumEntries) {
++				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
++					le16_to_cpu(clk_v->entries[0].usSclkLow) |
++					(clk_v->entries[0].ucSclkHigh << 16);
++				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
++					le16_to_cpu(clk_v->entries[0].usMclkLow) |
++					(clk_v->entries[0].ucMclkHigh << 16);
++				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
++					le16_to_cpu(clk_v->entries[0].usVddc);
++				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
++					le16_to_cpu(clk_v->entries[0].usVddci);
++			}
++		}
++		if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
++			ATOM_PPLIB_PhaseSheddingLimits_Table *psl =
++				(ATOM_PPLIB_PhaseSheddingLimits_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
++			ATOM_PPLIB_PhaseSheddingLimits_Record *entry;
++
++			adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
++				kzalloc(psl->ucNumEntries *
++					sizeof(struct amdgpu_phase_shedding_limits_entry),
++					GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++
++			entry = &psl->entries[0];
++			for (i = 0; i < psl->ucNumEntries; i++) {
++				adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
++					le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16);
++				adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
++					le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16);
++				adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
++					le16_to_cpu(entry->usVoltage);
++				entry = (ATOM_PPLIB_PhaseSheddingLimits_Record *)
++					((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));
++			}
++			adev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
++				psl->ucNumEntries;
++		}
++	}
++
++	/* cac data */
++	if (le16_to_cpu(power_info->pplib.usTableSize) >=
++	    sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
++		adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
++		adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
++		adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit;
++		adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
++		if (adev->pm.dpm.tdp_od_limit)
++			adev->pm.dpm.power_control = true;
++		else
++			adev->pm.dpm.power_control = false;
++		adev->pm.dpm.tdp_adjustment = 0;
++		adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
++		adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
++		adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
++		if (power_info->pplib5.usCACLeakageTableOffset) {
++			ATOM_PPLIB_CAC_Leakage_Table *cac_table =
++				(ATOM_PPLIB_CAC_Leakage_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset));
++			ATOM_PPLIB_CAC_Leakage_Record *entry;
++			u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table);
++			adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			entry = &cac_table->entries[0];
++			for (i = 0; i < cac_table->ucNumEntries; i++) {
++				if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
++						le16_to_cpu(entry->usVddc1);
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
++						le16_to_cpu(entry->usVddc2);
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
++						le16_to_cpu(entry->usVddc3);
++				} else {
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
++						le16_to_cpu(entry->usVddc);
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
++						le32_to_cpu(entry->ulLeakageValue);
++				}
++				entry = (ATOM_PPLIB_CAC_Leakage_Record *)
++					((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));
++			}
++			adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
++		}
++	}
++
++	/* ext tables */
++	if (le16_to_cpu(power_info->pplib.usTableSize) >=
++	    sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
++		ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *)
++			(mode_info->atom_context->bios + data_offset +
++			 le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset));
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) &&
++			ext_hdr->usVCETableOffset) {
++			VCEClockInfoArray *array = (VCEClockInfoArray *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usVCETableOffset) + 1);
++			ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =
++				(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
++				 1 + array->ucNumEntries * sizeof(VCEClockInfo));
++			ATOM_PPLIB_VCE_State_Table *states =
++				(ATOM_PPLIB_VCE_State_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
++				 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) +
++				 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)));
++			ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *entry;
++			ATOM_PPLIB_VCE_State_Record *state_entry;
++			VCEClockInfo *vce_clk;
++			u32 size = limits->numEntries *
++				sizeof(struct amdgpu_vce_clock_voltage_dependency_entry);
++			adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
++				kzalloc(size, GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
++				limits->numEntries;
++			entry = &limits->entries[0];
++			state_entry = &states->entries[0];
++			for (i = 0; i < limits->numEntries; i++) {
++				vce_clk = (VCEClockInfo *)
++					((u8 *)&array->entries[0] +
++					 (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo)));
++				adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
++					le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16);
++				adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
++					le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16);
++				adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
++					le16_to_cpu(entry->usVoltage);
++				entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *)
++					((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));
++			}
++			for (i = 0; i < states->numEntries; i++) {
++				if (i >= AMDGPU_MAX_VCE_LEVELS)
++					break;
++				vce_clk = (VCEClockInfo *)
++					((u8 *)&array->entries[0] +
++					 (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo)));
++				adev->pm.dpm.vce_states[i].evclk =
++					le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16);
++				adev->pm.dpm.vce_states[i].ecclk =
++					le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16);
++				adev->pm.dpm.vce_states[i].clk_idx =
++					state_entry->ucClockInfoIndex & 0x3f;
++				adev->pm.dpm.vce_states[i].pstate =
++					(state_entry->ucClockInfoIndex & 0xc0) >> 6;
++				state_entry = (ATOM_PPLIB_VCE_State_Record *)
++					((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record));
++			}
++		}
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) &&
++			ext_hdr->usUVDTableOffset) {
++			UVDClockInfoArray *array = (UVDClockInfoArray *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1);
++			ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits =
++				(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 +
++				 1 + (array->ucNumEntries * sizeof (UVDClockInfo)));
++			ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *entry;
++			u32 size = limits->numEntries *
++				sizeof(struct amdgpu_uvd_clock_voltage_dependency_entry);
++			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
++				kzalloc(size, GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
++				limits->numEntries;
++			entry = &limits->entries[0];
++			for (i = 0; i < limits->numEntries; i++) {
++				UVDClockInfo *uvd_clk = (UVDClockInfo *)
++					((u8 *)&array->entries[0] +
++					 (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo)));
++				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
++					le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16);
++				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
++					le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16);
++				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
++					le16_to_cpu(entry->usVoltage);
++				entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *)
++					((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));
++			}
++		}
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) &&
++			ext_hdr->usSAMUTableOffset) {
++			ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits =
++				(ATOM_PPLIB_SAMClk_Voltage_Limit_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1);
++			ATOM_PPLIB_SAMClk_Voltage_Limit_Record *entry;
++			u32 size = limits->numEntries *
++				sizeof(struct amdgpu_clock_voltage_dependency_entry);
++			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
++				kzalloc(size, GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
++				limits->numEntries;
++			entry = &limits->entries[0];
++			for (i = 0; i < limits->numEntries; i++) {
++				adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =
++					le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16);
++				adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
++					le16_to_cpu(entry->usVoltage);
++				entry = (ATOM_PPLIB_SAMClk_Voltage_Limit_Record *)
++					((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));
++			}
++		}
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) &&
++		    ext_hdr->usPPMTableOffset) {
++			ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usPPMTableOffset));
++			adev->pm.dpm.dyn_state.ppm_table =
++				kzalloc(sizeof(struct amdgpu_ppm_table), GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.ppm_table) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
++			adev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
++				le16_to_cpu(ppm->usCpuCoreNumber);
++			adev->pm.dpm.dyn_state.ppm_table->platform_tdp =
++				le32_to_cpu(ppm->ulPlatformTDP);
++			adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
++				le32_to_cpu(ppm->ulSmallACPlatformTDP);
++			adev->pm.dpm.dyn_state.ppm_table->platform_tdc =
++				le32_to_cpu(ppm->ulPlatformTDC);
++			adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
++				le32_to_cpu(ppm->ulSmallACPlatformTDC);
++			adev->pm.dpm.dyn_state.ppm_table->apu_tdp =
++				le32_to_cpu(ppm->ulApuTDP);
++			adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
++				le32_to_cpu(ppm->ulDGpuTDP);
++			adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
++				le32_to_cpu(ppm->ulDGpuUlvPower);
++			adev->pm.dpm.dyn_state.ppm_table->tj_max =
++				le32_to_cpu(ppm->ulTjmax);
++		}
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) &&
++			ext_hdr->usACPTableOffset) {
++			ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits =
++				(ATOM_PPLIB_ACPClk_Voltage_Limit_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usACPTableOffset) + 1);
++			ATOM_PPLIB_ACPClk_Voltage_Limit_Record *entry;
++			u32 size = limits->numEntries *
++				sizeof(struct amdgpu_clock_voltage_dependency_entry);
++			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
++				kzalloc(size, GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
++				limits->numEntries;
++			entry = &limits->entries[0];
++			for (i = 0; i < limits->numEntries; i++) {
++				adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =
++					le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16);
++				adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
++					le16_to_cpu(entry->usVoltage);
++				entry = (ATOM_PPLIB_ACPClk_Voltage_Limit_Record *)
++					((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));
++			}
++		}
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) &&
++			ext_hdr->usPowerTuneTableOffset) {
++			u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +
++					 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
++			ATOM_PowerTune_Table *pt;
++			adev->pm.dpm.dyn_state.cac_tdp_table =
++				kzalloc(sizeof(struct amdgpu_cac_tdp_table), GFP_KERNEL);
++			if (!adev->pm.dpm.dyn_state.cac_tdp_table) {
++				amdgpu_free_extended_power_table(adev);
++				return -ENOMEM;
++			}
++			if (rev > 0) {
++				ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *)
++					(mode_info->atom_context->bios + data_offset +
++					 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
++				adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
++					ppt->usMaximumPowerDeliveryLimit;
++				pt = &ppt->power_tune_table;
++			} else {
++				ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
++					(mode_info->atom_context->bios + data_offset +
++					 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
++				adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
++				pt = &ppt->power_tune_table;
++			}
++			adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
++			adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
++				le16_to_cpu(pt->usConfigurableTDP);
++			adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
++			adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
++				le16_to_cpu(pt->usBatteryPowerLimit);
++			adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
++				le16_to_cpu(pt->usSmallPowerLimit);
++			adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
++				le16_to_cpu(pt->usLowCACLeakage);
++			adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
++				le16_to_cpu(pt->usHighCACLeakage);
++		}
++		if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8) &&
++				ext_hdr->usSclkVddgfxTableOffset) {
++			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
++				(mode_info->atom_context->bios + data_offset +
++				 le16_to_cpu(ext_hdr->usSclkVddgfxTableOffset));
++			ret = amdgpu_parse_clk_voltage_dep_table(
++					&adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk,
++					dep_table);
++			if (ret) {
++				kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries);
++				return ret;
++			}
++		}
++	}
++
++	return 0;
++}
++
++void amdgpu_free_extended_power_table(struct amdgpu_device *adev)
++{
++	struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state;
++
++	kfree(dyn_state->vddc_dependency_on_sclk.entries);
++	kfree(dyn_state->vddci_dependency_on_mclk.entries);
++	kfree(dyn_state->vddc_dependency_on_mclk.entries);
++	kfree(dyn_state->mvdd_dependency_on_mclk.entries);
++	kfree(dyn_state->cac_leakage_table.entries);
++	kfree(dyn_state->phase_shedding_limits_table.entries);
++	kfree(dyn_state->ppm_table);
++	kfree(dyn_state->cac_tdp_table);
++	kfree(dyn_state->vce_clock_voltage_dependency_table.entries);
++	kfree(dyn_state->uvd_clock_voltage_dependency_table.entries);
++	kfree(dyn_state->samu_clock_voltage_dependency_table.entries);
++	kfree(dyn_state->acp_clock_voltage_dependency_table.entries);
++	kfree(dyn_state->vddgfx_dependency_on_sclk.entries);
++}
++
++static const char *pp_lib_thermal_controller_names[] = {
++	"NONE",
++	"lm63",
++	"adm1032",
++	"adm1030",
++	"max6649",
++	"lm64",
++	"f75375",
++	"RV6xx",
++	"RV770",
++	"adt7473",
++	"NONE",
++	"External GPIO",
++	"Evergreen",
++	"emc2103",
++	"Sumo",
++	"Northern Islands",
++	"Southern Islands",
++	"lm96163",
++	"Sea Islands",
++	"Kaveri/Kabini",
++};
++
++void amdgpu_add_thermal_controller(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	ATOM_PPLIB_POWERPLAYTABLE *power_table;
++	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
++	ATOM_PPLIB_THERMALCONTROLLER *controller;
++	struct amdgpu_i2c_bus_rec i2c_bus;
++	u16 data_offset;
++	u8 frev, crev;
++
++	if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset))
++		return;
++	power_table = (ATOM_PPLIB_POWERPLAYTABLE *)
++		(mode_info->atom_context->bios + data_offset);
++	controller = &power_table->sThermalController;
++
++	/* add the i2c bus for thermal/fan chip */
++	if (controller->ucType > 0) {
++		if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
++			adev->pm.no_fan = true;
++		adev->pm.fan_pulses_per_revolution =
++			controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
++		if (adev->pm.fan_pulses_per_revolution) {
++			adev->pm.fan_min_rpm = controller->ucFanMinRPM;
++			adev->pm.fan_max_rpm = controller->ucFanMaxRPM;
++		}
++		if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_RV770;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_NI;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_SI;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_CI;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
++			DRM_INFO("Internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_KV;
++		} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
++			DRM_INFO("External GPIO thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
++		} else if (controller->ucType ==
++			   ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
++			DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
++		} else if (controller->ucType ==
++			   ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
++			DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
++		} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
++			DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
++				 pp_lib_thermal_controller_names[controller->ucType],
++				 controller->ucI2cAddress >> 1,
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++			adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
++			i2c_bus = amdgpu_atombios_lookup_i2c_gpio(adev, controller->ucI2cLine);
++			adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus);
++			if (adev->pm.i2c_bus) {
++				struct i2c_board_info info = { };
++				const char *name = pp_lib_thermal_controller_names[controller->ucType];
++				info.addr = controller->ucI2cAddress >> 1;
++				strlcpy(info.type, name, sizeof(info.type));
++				i2c_new_device(&adev->pm.i2c_bus->adapter, &info);
++			}
++		} else {
++			DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
++				 controller->ucType,
++				 controller->ucI2cAddress >> 1,
++				 (controller->ucFanParameters &
++				  ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
++		}
++	}
++}
++
++enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
++						 u32 sys_mask,
++						 enum amdgpu_pcie_gen asic_gen,
++						 enum amdgpu_pcie_gen default_gen)
++{
++	switch (asic_gen) {
++	case AMDGPU_PCIE_GEN1:
++		return AMDGPU_PCIE_GEN1;
++	case AMDGPU_PCIE_GEN2:
++		return AMDGPU_PCIE_GEN2;
++	case AMDGPU_PCIE_GEN3:
++		return AMDGPU_PCIE_GEN3;
++	default:
++		if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
++			return AMDGPU_PCIE_GEN3;
++		else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
++			return AMDGPU_PCIE_GEN2;
++		else
++			return AMDGPU_PCIE_GEN1;
++	}
++	return AMDGPU_PCIE_GEN1;
++}
++
++u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
++				 u16 asic_lanes,
++				 u16 default_lanes)
++{
++	switch (asic_lanes) {
++	case 0:
++	default:
++		return default_lanes;
++	case 1:
++		return 1;
++	case 2:
++		return 2;
++	case 4:
++		return 4;
++	case 8:
++		return 8;
++	case 12:
++		return 12;
++	case 16:
++		return 16;
++	}
++}
++
++u8 amdgpu_encode_pci_lane_width(u32 lanes)
++{
++	u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 };
++
++	if (lanes > 16)
++		return 0;
++
++	return encoded_lanes[lanes];
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+new file mode 100644
+index 0000000..3738a96
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+@@ -0,0 +1,85 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __AMDGPU_DPM_H__
++#define __AMDGPU_DPM_H__
++
++#define R600_SSTU_DFLT                               0
++#define R600_SST_DFLT                                0x00C8
++
++/* XXX are these ok? */
++#define R600_TEMP_RANGE_MIN (90 * 1000)
++#define R600_TEMP_RANGE_MAX (120 * 1000)
++
++#define FDO_PWM_MODE_STATIC  1
++#define FDO_PWM_MODE_STATIC_RPM 5
++
++enum amdgpu_td {
++	AMDGPU_TD_AUTO,
++	AMDGPU_TD_UP,
++	AMDGPU_TD_DOWN,
++};
++
++enum amdgpu_display_watermark {
++	AMDGPU_DISPLAY_WATERMARK_LOW = 0,
++	AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
++};
++
++enum amdgpu_display_gap
++{
++    AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
++    AMDGPU_PM_DISPLAY_GAP_VBLANK       = 1,
++    AMDGPU_PM_DISPLAY_GAP_WATERMARK    = 2,
++    AMDGPU_PM_DISPLAY_GAP_IGNORE       = 3,
++};
++
++void amdgpu_dpm_print_class_info(u32 class, u32 class2);
++void amdgpu_dpm_print_cap_info(u32 caps);
++void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
++				struct amdgpu_ps *rps);
++u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
++u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
++bool amdgpu_is_uvd_state(u32 class, u32 class2);
++void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
++			      u32 *p, u32 *u);
++int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
++
++bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
++
++int amdgpu_get_platform_caps(struct amdgpu_device *adev);
++
++int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
++void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
++
++void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
++
++enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
++						 u32 sys_mask,
++						 enum amdgpu_pcie_gen asic_gen,
++						 enum amdgpu_pcie_gen default_gen);
++
++u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
++				 u16 asic_lanes,
++				 u16 default_lanes);
++u8 amdgpu_encode_pci_lane_width(u32 lanes);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+new file mode 100644
+index 0000000..d1af448
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -0,0 +1,439 @@
++/**
++ * \file amdgpu_drv.c
++ * AMD Amdgpu driver
++ *
++ * \author Gareth Hughes <gareth@valinux.com>
++ */
++
++/*
++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include <drm/drm_gem.h>
++#include "amdgpu_drv.h"
++
++#include <drm/drm_pciids.h>
++#include <linux/console.h>
++#include <linux/module.h>
++#include <linux/pm_runtime.h>
++#include <linux/vga_switcheroo.h>
++#include "drm_crtc_helper.h"
++
++#include "amdgpu.h"
++#include "amdgpu_irq.h"
++
++/*
++ * KMS wrapper.
++ * - 3.0.0 - initial driver
++ */
++#define KMS_DRIVER_MAJOR	3
++#define KMS_DRIVER_MINOR	0
++#define KMS_DRIVER_PATCHLEVEL	0
++
++int amdgpu_vram_limit = 0;
++int amdgpu_gart_size = -1; /* auto */
++int amdgpu_benchmarking = 0;
++int amdgpu_testing = 0;
++int amdgpu_audio = -1;
++int amdgpu_disp_priority = 0;
++int amdgpu_hw_i2c = 0;
++int amdgpu_pcie_gen2 = -1;
++int amdgpu_msi = -1;
++int amdgpu_lockup_timeout = 10000;
++int amdgpu_dpm = -1;
++int amdgpu_smc_load_fw = 1;
++int amdgpu_aspm = -1;
++int amdgpu_runtime_pm = -1;
++int amdgpu_hard_reset = 0;
++unsigned amdgpu_ip_block_mask = 0xffffffff;
++int amdgpu_bapm = -1;
++int amdgpu_deep_color = 0;
++int amdgpu_vm_size = 8;
++int amdgpu_vm_block_size = -1;
++int amdgpu_exp_hw_support = 0;
++
++MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
++module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
++
++MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
++module_param_named(gartsize, amdgpu_gart_size, int, 0600);
++
++MODULE_PARM_DESC(benchmark, "Run benchmark");
++module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
++
++MODULE_PARM_DESC(test, "Run tests");
++module_param_named(test, amdgpu_testing, int, 0444);
++
++MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
++module_param_named(audio, amdgpu_audio, int, 0444);
++
++MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
++module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
++
++MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
++module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
++
++MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
++module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
++
++MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
++module_param_named(msi, amdgpu_msi, int, 0444);
++
++MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
++module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
++
++MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
++module_param_named(dpm, amdgpu_dpm, int, 0444);
++
++MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
++module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
++
++MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
++module_param_named(aspm, amdgpu_aspm, int, 0444);
++
++MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
++module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
++
++MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
++module_param_named(hard_reset, amdgpu_hard_reset, int, 0444);
++
++MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
++module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
++
++MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
++module_param_named(bapm, amdgpu_bapm, int, 0444);
++
++MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
++module_param_named(deep_color, amdgpu_deep_color, int, 0444);
++
++MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
++module_param_named(vm_size, amdgpu_vm_size, int, 0444);
++
++MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
++module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
++
++MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
++module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
++
++static struct pci_device_id pciidlist[] = {
++
++	{0, 0, 0}
++};
++
++MODULE_DEVICE_TABLE(pci, pciidlist);
++
++static struct drm_driver kms_driver;
++
++static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
++{
++	struct apertures_struct *ap;
++	bool primary = false;
++
++	ap = alloc_apertures(1);
++	if (!ap)
++		return -ENOMEM;
++
++	ap->ranges[0].base = pci_resource_start(pdev, 0);
++	ap->ranges[0].size = pci_resource_len(pdev, 0);
++
++#ifdef CONFIG_X86
++	primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
++#endif
++	remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
++	kfree(ap);
++
++	return 0;
++}
++
++static int amdgpu_pci_probe(struct pci_dev *pdev,
++			    const struct pci_device_id *ent)
++{
++	unsigned long flags = ent->driver_data;
++	int ret;
++
++	if ((flags & AMDGPU_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
++		DRM_INFO("This hardware requires experimental hardware support.\n"
++			 "See modparam exp_hw_support\n");
++		return -ENODEV;
++	}
++
++	/* Get rid of things like offb */
++	ret = amdgpu_kick_out_firmware_fb(pdev);
++	if (ret)
++		return ret;
++
++	return drm_get_pci_dev(pdev, ent, &kms_driver);
++}
++
++static void
++amdgpu_pci_remove(struct pci_dev *pdev)
++{
++	struct drm_device *dev = pci_get_drvdata(pdev);
++
++	drm_put_dev(dev);
++}
++
++static int amdgpu_pmops_suspend(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	return amdgpu_suspend_kms(drm_dev, true, true);
++}
++
++static int amdgpu_pmops_resume(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	return amdgpu_resume_kms(drm_dev, true, true);
++}
++
++static int amdgpu_pmops_freeze(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	return amdgpu_suspend_kms(drm_dev, false, true);
++}
++
++static int amdgpu_pmops_thaw(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	return amdgpu_resume_kms(drm_dev, false, true);
++}
++
++static int amdgpu_pmops_runtime_suspend(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	int ret;
++
++	if (!amdgpu_device_is_px(drm_dev)) {
++		pm_runtime_forbid(dev);
++		return -EBUSY;
++	}
++
++	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++	drm_kms_helper_poll_disable(drm_dev);
++	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
++
++	ret = amdgpu_suspend_kms(drm_dev, false, false);
++	pci_save_state(pdev);
++	pci_disable_device(pdev);
++	pci_ignore_hotplug(pdev);
++	pci_set_power_state(pdev, PCI_D3cold);
++	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++
++	return 0;
++}
++
++static int amdgpu_pmops_runtime_resume(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	int ret;
++
++	if (!amdgpu_device_is_px(drm_dev))
++		return -EINVAL;
++
++	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++
++	pci_set_power_state(pdev, PCI_D0);
++	pci_restore_state(pdev);
++	ret = pci_enable_device(pdev);
++	if (ret)
++		return ret;
++	pci_set_master(pdev);
++
++	ret = amdgpu_resume_kms(drm_dev, false, false);
++	drm_kms_helper_poll_enable(drm_dev);
++	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
++	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
++	return 0;
++}
++
++static int amdgpu_pmops_runtime_idle(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	struct drm_crtc *crtc;
++
++	if (!amdgpu_device_is_px(drm_dev)) {
++		pm_runtime_forbid(dev);
++		return -EBUSY;
++	}
++
++	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
++		if (crtc->enabled) {
++			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
++			return -EBUSY;
++		}
++	}
++
++	pm_runtime_mark_last_busy(dev);
++	pm_runtime_autosuspend(dev);
++	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
++	return 1;
++}
++
++long amdgpu_drm_ioctl(struct file *filp,
++		      unsigned int cmd, unsigned long arg)
++{
++	struct drm_file *file_priv = filp->private_data;
++	struct drm_device *dev;
++	long ret;
++	dev = file_priv->minor->dev;
++	ret = pm_runtime_get_sync(dev->dev);
++	if (ret < 0)
++		return ret;
++
++	ret = drm_ioctl(filp, cmd, arg);
++
++	pm_runtime_mark_last_busy(dev->dev);
++	pm_runtime_put_autosuspend(dev->dev);
++	return ret;
++}
++
++static const struct dev_pm_ops amdgpu_pm_ops = {
++	.suspend = amdgpu_pmops_suspend,
++	.resume = amdgpu_pmops_resume,
++	.freeze = amdgpu_pmops_freeze,
++	.thaw = amdgpu_pmops_thaw,
++	.poweroff = amdgpu_pmops_freeze,
++	.restore = amdgpu_pmops_resume,
++	.runtime_suspend = amdgpu_pmops_runtime_suspend,
++	.runtime_resume = amdgpu_pmops_runtime_resume,
++	.runtime_idle = amdgpu_pmops_runtime_idle,
++};
++
++static const struct file_operations amdgpu_driver_kms_fops = {
++	.owner = THIS_MODULE,
++	.open = drm_open,
++	.release = drm_release,
++	.unlocked_ioctl = amdgpu_drm_ioctl,
++	.mmap = amdgpu_mmap,
++	.poll = drm_poll,
++	.read = drm_read,
++#ifdef CONFIG_COMPAT
++	.compat_ioctl = amdgpu_kms_compat_ioctl,
++#endif
++};
++
++static struct drm_driver kms_driver = {
++	.driver_features =
++	    DRIVER_USE_AGP |
++	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
++	    DRIVER_PRIME | DRIVER_RENDER,
++	.dev_priv_size = 0,
++	.load = amdgpu_driver_load_kms,
++	.open = amdgpu_driver_open_kms,
++	.preclose = amdgpu_driver_preclose_kms,
++	.postclose = amdgpu_driver_postclose_kms,
++	.lastclose = amdgpu_driver_lastclose_kms,
++	.set_busid = drm_pci_set_busid,
++	.unload = amdgpu_driver_unload_kms,
++	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
++	.enable_vblank = amdgpu_enable_vblank_kms,
++	.disable_vblank = amdgpu_disable_vblank_kms,
++	.get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
++	.get_scanout_position = amdgpu_get_crtc_scanoutpos,
++#if defined(CONFIG_DEBUG_FS)
++	.debugfs_init = amdgpu_debugfs_init,
++	.debugfs_cleanup = amdgpu_debugfs_cleanup,
++#endif
++	.irq_preinstall = amdgpu_irq_preinstall,
++	.irq_postinstall = amdgpu_irq_postinstall,
++	.irq_uninstall = amdgpu_irq_uninstall,
++	.irq_handler = amdgpu_irq_handler,
++	.ioctls = amdgpu_ioctls_kms,
++	.gem_free_object = amdgpu_gem_object_free,
++	.gem_open_object = amdgpu_gem_object_open,
++	.gem_close_object = amdgpu_gem_object_close,
++	.dumb_create = amdgpu_mode_dumb_create,
++	.dumb_map_offset = amdgpu_mode_dumb_mmap,
++	.dumb_destroy = drm_gem_dumb_destroy,
++	.fops = &amdgpu_driver_kms_fops,
++
++	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
++	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
++	.gem_prime_export = amdgpu_gem_prime_export,
++	.gem_prime_import = drm_gem_prime_import,
++	.gem_prime_pin = amdgpu_gem_prime_pin,
++	.gem_prime_unpin = amdgpu_gem_prime_unpin,
++	.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
++	.gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
++	.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
++	.gem_prime_vmap = amdgpu_gem_prime_vmap,
++	.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
++
++	.name = DRIVER_NAME,
++	.desc = DRIVER_DESC,
++	.date = DRIVER_DATE,
++	.major = KMS_DRIVER_MAJOR,
++	.minor = KMS_DRIVER_MINOR,
++	.patchlevel = KMS_DRIVER_PATCHLEVEL,
++};
++
++static struct drm_driver *driver;
++static struct pci_driver *pdriver;
++
++static struct pci_driver amdgpu_kms_pci_driver = {
++	.name = DRIVER_NAME,
++	.id_table = pciidlist,
++	.probe = amdgpu_pci_probe,
++	.remove = amdgpu_pci_remove,
++	.driver.pm = &amdgpu_pm_ops,
++};
++
++static int __init amdgpu_init(void)
++{
++#ifdef CONFIG_VGA_CONSOLE
++	if (vgacon_text_force()) {
++		DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
++		return -EINVAL;
++	}
++#endif
++	DRM_INFO("amdgpu kernel modesetting enabled.\n");
++	driver = &kms_driver;
++	pdriver = &amdgpu_kms_pci_driver;
++	driver->driver_features |= DRIVER_MODESET;
++	driver->num_ioctls = amdgpu_max_kms_ioctl;
++	amdgpu_register_atpx_handler();
++
++	/* let modprobe override vga console setting */
++	return drm_pci_init(driver, pdriver);
++}
++
++static void __exit amdgpu_exit(void)
++{
++	drm_pci_exit(driver, pdriver);
++	amdgpu_unregister_atpx_handler();
++}
++
++module_init(amdgpu_init);
++module_exit(amdgpu_exit);
++
++MODULE_AUTHOR(DRIVER_AUTHOR);
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_LICENSE("GPL and additional rights");
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h
+new file mode 100644
+index 0000000..cceeb33
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h
+@@ -0,0 +1,48 @@
++/* amdgpu_drv.h -- Private header for amdgpu driver -*- linux-c -*-
++ *
++ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
++ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
++ * All rights reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_DRV_H__
++#define __AMDGPU_DRV_H__
++
++#include <linux/firmware.h>
++#include <linux/platform_device.h>
++
++#include "amdgpu_family.h"
++
++/* General customization:
++ */
++
++#define DRIVER_AUTHOR		"AMD linux driver team"
++
++#define DRIVER_NAME		"amdgpu"
++#define DRIVER_DESC		"AMD GPU"
++#define DRIVER_DATE		"20150101"
++
++long amdgpu_drm_ioctl(struct file *filp,
++		      unsigned int cmd, unsigned long arg);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+new file mode 100644
+index 0000000..94138ab
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+@@ -0,0 +1,245 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_connectors.h"
++#include "atom.h"
++#include "atombios_encoders.h"
++
++void
++amdgpu_link_encoder_connector(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++
++	/* walk the list and link encoders to connectors */
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		amdgpu_connector = to_amdgpu_connector(connector);
++		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++			amdgpu_encoder = to_amdgpu_encoder(encoder);
++			if (amdgpu_encoder->devices & amdgpu_connector->devices) {
++				drm_mode_connector_attach_encoder(connector, encoder);
++				if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++					amdgpu_atombios_encoder_init_backlight(amdgpu_encoder, connector);
++					adev->mode_info.bl_encoder = amdgpu_encoder;
++				}
++			}
++		}
++	}
++}
++
++void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++			amdgpu_encoder->active_device = amdgpu_encoder->devices & amdgpu_connector->devices;
++			DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
++				  amdgpu_encoder->active_device, amdgpu_encoder->devices,
++				  amdgpu_connector->devices, encoder->encoder_type);
++		}
++	}
++}
++
++struct drm_connector *
++amdgpu_get_connector_for_encoder(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		amdgpu_connector = to_amdgpu_connector(connector);
++		if (amdgpu_encoder->active_device & amdgpu_connector->devices)
++			return connector;
++	}
++	return NULL;
++}
++
++struct drm_connector *
++amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		amdgpu_connector = to_amdgpu_connector(connector);
++		if (amdgpu_encoder->devices & amdgpu_connector->devices)
++			return connector;
++	}
++	return NULL;
++}
++
++struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_encoder *other_encoder;
++	struct amdgpu_encoder *other_amdgpu_encoder;
++
++	if (amdgpu_encoder->is_ext_encoder)
++		return NULL;
++
++	list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
++		if (other_encoder == encoder)
++			continue;
++		other_amdgpu_encoder = to_amdgpu_encoder(other_encoder);
++		if (other_amdgpu_encoder->is_ext_encoder &&
++		    (amdgpu_encoder->devices & other_amdgpu_encoder->devices))
++			return other_encoder;
++	}
++	return NULL;
++}
++
++u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
++{
++	struct drm_encoder *other_encoder = amdgpu_get_external_encoder(encoder);
++
++	if (other_encoder) {
++		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(other_encoder);
++
++		switch (amdgpu_encoder->encoder_id) {
++		case ENCODER_OBJECT_ID_TRAVIS:
++		case ENCODER_OBJECT_ID_NUTMEG:
++			return amdgpu_encoder->encoder_id;
++		default:
++			return ENCODER_OBJECT_ID_NONE;
++		}
++	}
++	return ENCODER_OBJECT_ID_NONE;
++}
++
++void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
++			     struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
++	unsigned hblank = native_mode->htotal - native_mode->hdisplay;
++	unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
++	unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
++	unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
++	unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
++	unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
++
++	adjusted_mode->clock = native_mode->clock;
++	adjusted_mode->flags = native_mode->flags;
++
++	adjusted_mode->hdisplay = native_mode->hdisplay;
++	adjusted_mode->vdisplay = native_mode->vdisplay;
++
++	adjusted_mode->htotal = native_mode->hdisplay + hblank;
++	adjusted_mode->hsync_start = native_mode->hdisplay + hover;
++	adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
++
++	adjusted_mode->vtotal = native_mode->vdisplay + vblank;
++	adjusted_mode->vsync_start = native_mode->vdisplay + vover;
++	adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
++
++	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
++
++	adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
++	adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
++
++	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
++	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
++	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
++
++	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
++	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
++	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
++
++}
++
++bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
++				    u32 pixel_clock)
++{
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++	struct amdgpu_connector_atom_dig *dig_connector;
++
++	connector = amdgpu_get_connector_for_encoder(encoder);
++	/* if we don't have an active device yet, just use one of
++	 * the connectors tied to the encoder.
++	 */
++	if (!connector)
++		connector = amdgpu_get_connector_for_encoder_init(encoder);
++	amdgpu_connector = to_amdgpu_connector(connector);
++
++	switch (connector->connector_type) {
++	case DRM_MODE_CONNECTOR_DVII:
++	case DRM_MODE_CONNECTOR_HDMIB:
++		if (amdgpu_connector->use_digital) {
++			/* HDMI 1.3 supports up to 340 Mhz over single link */
++			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++				if (pixel_clock > 340000)
++					return true;
++				else
++					return false;
++			} else {
++				if (pixel_clock > 165000)
++					return true;
++				else
++					return false;
++			}
++		} else
++			return false;
++	case DRM_MODE_CONNECTOR_DVID:
++	case DRM_MODE_CONNECTOR_HDMIA:
++	case DRM_MODE_CONNECTOR_DisplayPort:
++		dig_connector = amdgpu_connector->con_priv;
++		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
++		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
++			return false;
++		else {
++			/* HDMI 1.3 supports up to 340 Mhz over single link */
++			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
++				if (pixel_clock > 340000)
++					return true;
++				else
++					return false;
++			} else {
++				if (pixel_clock > 165000)
++					return true;
++				else
++					return false;
++			}
++		}
++	default:
++		return false;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+new file mode 100644
+index 0000000..2b1735d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+@@ -0,0 +1,432 @@
++/*
++ * Copyright © 2007 David Airlie
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ *     David Airlie
++ */
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/fb.h>
++
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++#include <drm/drm_fb_helper.h>
++
++#include <linux/vga_switcheroo.h>
++
++/* object hierarchy -
++   this contains a helper + a amdgpu fb
++   the helper contains a pointer to amdgpu framebuffer baseclass.
++*/
++struct amdgpu_fbdev {
++	struct drm_fb_helper helper;
++	struct amdgpu_framebuffer rfb;
++	struct list_head fbdev_list;
++	struct amdgpu_device *adev;
++};
++
++static struct fb_ops amdgpufb_ops = {
++	.owner = THIS_MODULE,
++	.fb_check_var = drm_fb_helper_check_var,
++	.fb_set_par = drm_fb_helper_set_par,
++	.fb_fillrect = cfb_fillrect,
++	.fb_copyarea = cfb_copyarea,
++	.fb_imageblit = cfb_imageblit,
++	.fb_pan_display = drm_fb_helper_pan_display,
++	.fb_blank = drm_fb_helper_blank,
++	.fb_setcmap = drm_fb_helper_setcmap,
++	.fb_debug_enter = drm_fb_helper_debug_enter,
++	.fb_debug_leave = drm_fb_helper_debug_leave,
++};
++
++
++int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled)
++{
++	int aligned = width;
++	int pitch_mask = 0;
++
++	switch (bpp / 8) {
++	case 1:
++		pitch_mask = 255;
++		break;
++	case 2:
++		pitch_mask = 127;
++		break;
++	case 3:
++	case 4:
++		pitch_mask = 63;
++		break;
++	}
++
++	aligned += pitch_mask;
++	aligned &= ~pitch_mask;
++	return aligned;
++}
++
++static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
++{
++	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(gobj);
++	int ret;
++
++	ret = amdgpu_bo_reserve(rbo, false);
++	if (likely(ret == 0)) {
++		amdgpu_bo_kunmap(rbo);
++		amdgpu_bo_unpin(rbo);
++		amdgpu_bo_unreserve(rbo);
++	}
++	drm_gem_object_unreference_unlocked(gobj);
++}
++
++static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
++					 struct drm_mode_fb_cmd2 *mode_cmd,
++					 struct drm_gem_object **gobj_p)
++{
++	struct amdgpu_device *adev = rfbdev->adev;
++	struct drm_gem_object *gobj = NULL;
++	struct amdgpu_bo *rbo = NULL;
++	bool fb_tiled = false; /* useful for testing */
++	u32 tiling_flags = 0;
++	int ret;
++	int aligned_size, size;
++	int height = mode_cmd->height;
++	u32 bpp, depth;
++
++	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
++
++	/* need to align pitch with crtc limits */
++	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, bpp,
++						  fb_tiled) * ((bpp + 1) / 8);
++
++	height = ALIGN(mode_cmd->height, 8);
++	size = mode_cmd->pitches[0] * height;
++	aligned_size = ALIGN(size, PAGE_SIZE);
++	ret = amdgpu_gem_object_create(adev, aligned_size, 0,
++				       AMDGPU_GEM_DOMAIN_VRAM,
++				       0, true,
++				       &gobj);
++	if (ret) {
++		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
++		       aligned_size);
++		return -ENOMEM;
++	}
++	rbo = gem_to_amdgpu_bo(gobj);
++
++	if (fb_tiled)
++		tiling_flags = AMDGPU_TILING_MACRO;
++
++#ifdef __BIG_ENDIAN
++	switch (bpp) {
++	case 32:
++		tiling_flags |= AMDGPU_TILING_SWAP_32BIT;
++		break;
++	case 16:
++		tiling_flags |= AMDGPU_TILING_SWAP_16BIT;
++	default:
++		break;
++	}
++#endif
++
++	ret = amdgpu_bo_reserve(rbo, false);
++	if (unlikely(ret != 0))
++		goto out_unref;
++
++	if (tiling_flags) {
++		ret = amdgpu_bo_set_tiling_flags(rbo,
++						 tiling_flags | AMDGPU_TILING_SURFACE);
++		if (ret)
++			dev_err(adev->dev, "FB failed to set tiling flags\n");
++	}
++
++
++	ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL);
++	if (ret) {
++		amdgpu_bo_unreserve(rbo);
++		goto out_unref;
++	}
++	ret = amdgpu_bo_kmap(rbo, NULL);
++	amdgpu_bo_unreserve(rbo);
++	if (ret) {
++		goto out_unref;
++	}
++
++	*gobj_p = gobj;
++	return 0;
++out_unref:
++	amdgpufb_destroy_pinned_object(gobj);
++	*gobj_p = NULL;
++	return ret;
++}
++
++static int amdgpufb_create(struct drm_fb_helper *helper,
++			   struct drm_fb_helper_surface_size *sizes)
++{
++	struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
++	struct amdgpu_device *adev = rfbdev->adev;
++	struct fb_info *info;
++	struct drm_framebuffer *fb = NULL;
++	struct drm_mode_fb_cmd2 mode_cmd;
++	struct drm_gem_object *gobj = NULL;
++	struct amdgpu_bo *rbo = NULL;
++	struct device *device = &adev->pdev->dev;
++	int ret;
++	unsigned long tmp;
++
++	mode_cmd.width = sizes->surface_width;
++	mode_cmd.height = sizes->surface_height;
++
++	if (sizes->surface_bpp == 24)
++		sizes->surface_bpp = 32;
++
++	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
++							  sizes->surface_depth);
++
++	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
++	if (ret) {
++		DRM_ERROR("failed to create fbcon object %d\n", ret);
++		return ret;
++	}
++
++	rbo = gem_to_amdgpu_bo(gobj);
++
++	/* okay we have an object now allocate the framebuffer */
++	info = framebuffer_alloc(0, device);
++	if (info == NULL) {
++		ret = -ENOMEM;
++		goto out_unref;
++	}
++
++	info->par = rfbdev;
++
++	ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
++	if (ret) {
++		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
++		goto out_unref;
++	}
++
++	fb = &rfbdev->rfb.base;
++
++	/* setup helper */
++	rfbdev->helper.fb = fb;
++	rfbdev->helper.fbdev = info;
++
++	memset_io(rbo->kptr, 0x0, amdgpu_bo_size(rbo));
++
++	strcpy(info->fix.id, "amdgpudrmfb");
++
++	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
++
++	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
++	info->fbops = &amdgpufb_ops;
++
++	tmp = amdgpu_bo_gpu_offset(rbo) - adev->mc.vram_start;
++	info->fix.smem_start = adev->mc.aper_base + tmp;
++	info->fix.smem_len = amdgpu_bo_size(rbo);
++	info->screen_base = rbo->kptr;
++	info->screen_size = amdgpu_bo_size(rbo);
++
++	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
++
++	/* setup aperture base/size for vesafb takeover */
++	info->apertures = alloc_apertures(1);
++	if (!info->apertures) {
++		ret = -ENOMEM;
++		goto out_unref;
++	}
++	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
++	info->apertures->ranges[0].size = adev->mc.aper_size;
++
++	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
++
++	if (info->screen_base == NULL) {
++		ret = -ENOSPC;
++		goto out_unref;
++	}
++
++	ret = fb_alloc_cmap(&info->cmap, 256, 0);
++	if (ret) {
++		ret = -ENOMEM;
++		goto out_unref;
++	}
++
++	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
++	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)adev->mc.aper_base);
++	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(rbo));
++	DRM_INFO("fb depth is %d\n", fb->depth);
++	DRM_INFO("   pitch is %d\n", fb->pitches[0]);
++
++	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
++	return 0;
++
++out_unref:
++	if (rbo) {
++
++	}
++	if (fb && ret) {
++		drm_gem_object_unreference(gobj);
++		drm_framebuffer_unregister_private(fb);
++		drm_framebuffer_cleanup(fb);
++		kfree(fb);
++	}
++	return ret;
++}
++
++void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
++{
++	if (adev->mode_info.rfbdev)
++		drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
++}
++
++static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
++{
++	struct fb_info *info;
++	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
++
++	if (rfbdev->helper.fbdev) {
++		info = rfbdev->helper.fbdev;
++
++		unregister_framebuffer(info);
++		if (info->cmap.len)
++			fb_dealloc_cmap(&info->cmap);
++		framebuffer_release(info);
++	}
++
++	if (rfb->obj) {
++		amdgpufb_destroy_pinned_object(rfb->obj);
++		rfb->obj = NULL;
++	}
++	drm_fb_helper_fini(&rfbdev->helper);
++	drm_framebuffer_unregister_private(&rfb->base);
++	drm_framebuffer_cleanup(&rfb->base);
++
++	return 0;
++}
++
++/** Sets the color ramps on behalf of fbcon */
++static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
++				      u16 blue, int regno)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	amdgpu_crtc->lut_r[regno] = red >> 6;
++	amdgpu_crtc->lut_g[regno] = green >> 6;
++	amdgpu_crtc->lut_b[regno] = blue >> 6;
++}
++
++/** Gets the color ramps on behalf of fbcon */
++static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
++				      u16 *blue, int regno)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	*red = amdgpu_crtc->lut_r[regno] << 6;
++	*green = amdgpu_crtc->lut_g[regno] << 6;
++	*blue = amdgpu_crtc->lut_b[regno] << 6;
++}
++
++static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
++	.gamma_set = amdgpu_crtc_fb_gamma_set,
++	.gamma_get = amdgpu_crtc_fb_gamma_get,
++	.fb_probe = amdgpufb_create,
++};
++
++int amdgpu_fbdev_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_fbdev *rfbdev;
++	int bpp_sel = 32;
++	int ret;
++
++	/* don't init fbdev on hw without DCE */
++	if (!adev->mode_info.mode_config_initialized)
++		return 0;
++
++	/* select 8 bpp console on low vram cards */
++	if (adev->mc.real_vram_size <= (32*1024*1024))
++		bpp_sel = 8;
++
++	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
++	if (!rfbdev)
++		return -ENOMEM;
++
++	rfbdev->adev = adev;
++	adev->mode_info.rfbdev = rfbdev;
++
++	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
++			&amdgpu_fb_helper_funcs);
++
++	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
++				 adev->mode_info.num_crtc,
++				 AMDGPUFB_CONN_LIMIT);
++	if (ret) {
++		kfree(rfbdev);
++		return ret;
++	}
++
++	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
++
++	/* disable all the possible outputs/crtcs before entering KMS mode */
++	drm_helper_disable_unused_functions(adev->ddev);
++
++	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
++	return 0;
++}
++
++void amdgpu_fbdev_fini(struct amdgpu_device *adev)
++{
++	if (!adev->mode_info.rfbdev)
++		return;
++
++	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
++	kfree(adev->mode_info.rfbdev);
++	adev->mode_info.rfbdev = NULL;
++}
++
++void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
++{
++	if (adev->mode_info.rfbdev)
++		fb_set_suspend(adev->mode_info.rfbdev->helper.fbdev, state);
++}
++
++int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
++{
++	struct amdgpu_bo *robj;
++	int size = 0;
++
++	if (!adev->mode_info.rfbdev)
++		return 0;
++
++	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
++	size += amdgpu_bo_size(robj);
++	return size;
++}
++
++bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
++{
++	if (!adev->mode_info.rfbdev)
++		return false;
++	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
++		return true;
++	return false;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+new file mode 100644
+index 0000000..fc63855e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+@@ -0,0 +1,1139 @@
++/*
++ * Copyright 2009 Jerome Glisse.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Jerome Glisse <glisse@freedesktop.org>
++ *    Dave Airlie
++ */
++#include <linux/seq_file.h>
++#include <linux/atomic.h>
++#include <linux/wait.h>
++#include <linux/kref.h>
++#include <linux/slab.h>
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_trace.h"
++
++/*
++ * Fences
++ * Fences mark an event in the GPUs pipeline and are used
++ * for GPU/CPU synchronization.  When the fence is written,
++ * it is expected that all buffers associated with that fence
++ * are no longer in use by the associated ring on the GPU and
++ * that the the relevant GPU caches have been flushed.
++ */
++
++/**
++ * amdgpu_fence_write - write a fence value
++ *
++ * @ring: ring the fence is associated with
++ * @seq: sequence number to write
++ *
++ * Writes a fence value to memory (all asics).
++ */
++static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
++{
++	struct amdgpu_fence_driver *drv = &ring->fence_drv;
++
++	if (drv->cpu_addr)
++		*drv->cpu_addr = cpu_to_le32(seq);
++}
++
++/**
++ * amdgpu_fence_read - read a fence value
++ *
++ * @ring: ring the fence is associated with
++ *
++ * Reads a fence value from memory (all asics).
++ * Returns the value of the fence read from memory.
++ */
++static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
++{
++	struct amdgpu_fence_driver *drv = &ring->fence_drv;
++	u32 seq = 0;
++
++	if (drv->cpu_addr)
++		seq = le32_to_cpu(*drv->cpu_addr);
++	else
++		seq = lower_32_bits(atomic64_read(&drv->last_seq));
++
++	return seq;
++}
++
++/**
++ * amdgpu_fence_schedule_check - schedule lockup check
++ *
++ * @ring: pointer to struct amdgpu_ring
++ *
++ * Queues a delayed work item to check for lockups.
++ */
++static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring)
++{
++	/*
++	 * Do not reset the timer here with mod_delayed_work,
++	 * this can livelock in an interaction with TTM delayed destroy.
++	 */
++	queue_delayed_work(system_power_efficient_wq,
++		&ring->fence_drv.lockup_work,
++		AMDGPU_FENCE_JIFFIES_TIMEOUT);
++}
++
++/**
++ * amdgpu_fence_emit - emit a fence on the requested ring
++ *
++ * @ring: ring the fence is associated with
++ * @owner: creator of the fence
++ * @fence: amdgpu fence object
++ *
++ * Emits a fence command on the requested ring (all asics).
++ * Returns 0 on success, -ENOMEM on failure.
++ */
++int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
++		      struct amdgpu_fence **fence)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	/* we are protected by the ring emission mutex */
++	*fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
++	if ((*fence) == NULL) {
++		return -ENOMEM;
++	}
++	(*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
++	(*fence)->ring = ring;
++	(*fence)->owner = owner;
++	fence_init(&(*fence)->base, &amdgpu_fence_ops,
++		&adev->fence_queue.lock, adev->fence_context + ring->idx,
++		(*fence)->seq);
++	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, (*fence)->seq, false);
++	trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq);
++	return 0;
++}
++
++/**
++ * amdgpu_fence_check_signaled - callback from fence_queue
++ *
++ * this function is called with fence_queue lock held, which is also used
++ * for the fence locking itself, so unlocked variants are used for
++ * fence_signal, and remove_wait_queue.
++ */
++static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
++{
++	struct amdgpu_fence *fence;
++	struct amdgpu_device *adev;
++	u64 seq;
++	int ret;
++
++	fence = container_of(wait, struct amdgpu_fence, fence_wake);
++	adev = fence->ring->adev;
++
++	/*
++	 * We cannot use amdgpu_fence_process here because we're already
++	 * in the waitqueue, in a call from wake_up_all.
++	 */
++	seq = atomic64_read(&fence->ring->fence_drv.last_seq);
++	if (seq >= fence->seq) {
++		ret = fence_signal_locked(&fence->base);
++		if (!ret)
++			FENCE_TRACE(&fence->base, "signaled from irq context\n");
++		else
++			FENCE_TRACE(&fence->base, "was already signaled\n");
++
++		amdgpu_irq_put(adev, fence->ring->fence_drv.irq_src,
++				fence->ring->fence_drv.irq_type);
++		__remove_wait_queue(&adev->fence_queue, &fence->fence_wake);
++		fence_put(&fence->base);
++	} else
++		FENCE_TRACE(&fence->base, "pending\n");
++	return 0;
++}
++
++/**
++ * amdgpu_fence_activity - check for fence activity
++ *
++ * @ring: pointer to struct amdgpu_ring
++ *
++ * Checks the current fence value and calculates the last
++ * signalled fence value. Returns true if activity occured
++ * on the ring, and the fence_queue should be waken up.
++ */
++static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
++{
++	uint64_t seq, last_seq, last_emitted;
++	unsigned count_loop = 0;
++	bool wake = false;
++
++	/* Note there is a scenario here for an infinite loop but it's
++	 * very unlikely to happen. For it to happen, the current polling
++	 * process need to be interrupted by another process and another
++	 * process needs to update the last_seq btw the atomic read and
++	 * xchg of the current process.
++	 *
++	 * More over for this to go in infinite loop there need to be
++	 * continuously new fence signaled ie radeon_fence_read needs
++	 * to return a different value each time for both the currently
++	 * polling process and the other process that xchg the last_seq
++	 * btw atomic read and xchg of the current process. And the
++	 * value the other process set as last seq must be higher than
++	 * the seq value we just read. Which means that current process
++	 * need to be interrupted after radeon_fence_read and before
++	 * atomic xchg.
++	 *
++	 * To be even more safe we count the number of time we loop and
++	 * we bail after 10 loop just accepting the fact that we might
++	 * have temporarly set the last_seq not to the true real last
++	 * seq but to an older one.
++	 */
++	last_seq = atomic64_read(&ring->fence_drv.last_seq);
++	do {
++		last_emitted = ring->fence_drv.sync_seq[ring->idx];
++		seq = amdgpu_fence_read(ring);
++		seq |= last_seq & 0xffffffff00000000LL;
++		if (seq < last_seq) {
++			seq &= 0xffffffff;
++			seq |= last_emitted & 0xffffffff00000000LL;
++		}
++
++		if (seq <= last_seq || seq > last_emitted) {
++			break;
++		}
++		/* If we loop over we don't want to return without
++		 * checking if a fence is signaled as it means that the
++		 * seq we just read is different from the previous on.
++		 */
++		wake = true;
++		last_seq = seq;
++		if ((count_loop++) > 10) {
++			/* We looped over too many time leave with the
++			 * fact that we might have set an older fence
++			 * seq then the current real last seq as signaled
++			 * by the hw.
++			 */
++			break;
++		}
++	} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
++
++	if (seq < last_emitted)
++		amdgpu_fence_schedule_check(ring);
++
++	return wake;
++}
++
++/**
++ * amdgpu_fence_check_lockup - check for hardware lockup
++ *
++ * @work: delayed work item
++ *
++ * Checks for fence activity and if there is none probe
++ * the hardware if a lockup occured.
++ */
++static void amdgpu_fence_check_lockup(struct work_struct *work)
++{
++	struct amdgpu_fence_driver *fence_drv;
++	struct amdgpu_ring *ring;
++
++	fence_drv = container_of(work, struct amdgpu_fence_driver,
++				lockup_work.work);
++	ring = fence_drv->ring;
++
++	if (!down_read_trylock(&ring->adev->exclusive_lock)) {
++		/* just reschedule the check if a reset is going on */
++		amdgpu_fence_schedule_check(ring);
++		return;
++	}
++
++	if (fence_drv->delayed_irq && ring->adev->ddev->irq_enabled) {
++		fence_drv->delayed_irq = false;
++		amdgpu_irq_update(ring->adev, fence_drv->irq_src,
++				fence_drv->irq_type);
++	}
++
++	if (amdgpu_fence_activity(ring))
++		wake_up_all(&ring->adev->fence_queue);
++	else if (amdgpu_ring_is_lockup(ring)) {
++		/* good news we believe it's a lockup */
++		dev_warn(ring->adev->dev, "GPU lockup (current fence id "
++			"0x%016llx last fence id 0x%016llx on ring %d)\n",
++			(uint64_t)atomic64_read(&fence_drv->last_seq),
++			fence_drv->sync_seq[ring->idx], ring->idx);
++
++		/* remember that we need an reset */
++		ring->adev->needs_reset = true;
++		wake_up_all(&ring->adev->fence_queue);
++	}
++	up_read(&ring->adev->exclusive_lock);
++}
++
++/**
++ * amdgpu_fence_process - process a fence
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: ring index the fence is associated with
++ *
++ * Checks the current fence value and wakes the fence queue
++ * if the sequence number has increased (all asics).
++ */
++void amdgpu_fence_process(struct amdgpu_ring *ring)
++{
++	uint64_t seq, last_seq, last_emitted;
++	unsigned count_loop = 0;
++	bool wake = false;
++
++	/* Note there is a scenario here for an infinite loop but it's
++	 * very unlikely to happen. For it to happen, the current polling
++	 * process need to be interrupted by another process and another
++	 * process needs to update the last_seq btw the atomic read and
++	 * xchg of the current process.
++	 *
++	 * More over for this to go in infinite loop there need to be
++	 * continuously new fence signaled ie amdgpu_fence_read needs
++	 * to return a different value each time for both the currently
++	 * polling process and the other process that xchg the last_seq
++	 * btw atomic read and xchg of the current process. And the
++	 * value the other process set as last seq must be higher than
++	 * the seq value we just read. Which means that current process
++	 * need to be interrupted after amdgpu_fence_read and before
++	 * atomic xchg.
++	 *
++	 * To be even more safe we count the number of time we loop and
++	 * we bail after 10 loop just accepting the fact that we might
++	 * have temporarly set the last_seq not to the true real last
++	 * seq but to an older one.
++	 */
++	last_seq = atomic64_read(&ring->fence_drv.last_seq);
++	do {
++		last_emitted = ring->fence_drv.sync_seq[ring->idx];
++		seq = amdgpu_fence_read(ring);
++		seq |= last_seq & 0xffffffff00000000LL;
++		if (seq < last_seq) {
++			seq &= 0xffffffff;
++			seq |= last_emitted & 0xffffffff00000000LL;
++		}
++
++		if (seq <= last_seq || seq > last_emitted) {
++			break;
++		}
++		/* If we loop over we don't want to return without
++		 * checking if a fence is signaled as it means that the
++		 * seq we just read is different from the previous on.
++		 */
++		wake = true;
++		last_seq = seq;
++		if ((count_loop++) > 10) {
++			/* We looped over too many time leave with the
++			 * fact that we might have set an older fence
++			 * seq then the current real last seq as signaled
++			 * by the hw.
++			 */
++			break;
++		}
++	} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
++
++	if (wake)
++		wake_up_all(&ring->adev->fence_queue);
++}
++
++/**
++ * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
++ *
++ * @ring: ring the fence is associated with
++ * @seq: sequence number
++ *
++ * Check if the last signaled fence sequnce number is >= the requested
++ * sequence number (all asics).
++ * Returns true if the fence has signaled (current fence value
++ * is >= requested value) or false if it has not (current fence
++ * value is < the requested value.  Helper function for
++ * amdgpu_fence_signaled().
++ */
++static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
++{
++	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
++		return true;
++
++	/* poll new last sequence at least once */
++	amdgpu_fence_process(ring);
++	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
++		return true;
++
++	return false;
++}
++
++static bool amdgpu_fence_is_signaled(struct fence *f)
++{
++	struct amdgpu_fence *fence = to_amdgpu_fence(f);
++	struct amdgpu_ring *ring = fence->ring;
++	struct amdgpu_device *adev = ring->adev;
++
++	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
++		return true;
++
++	if (down_read_trylock(&adev->exclusive_lock)) {
++		amdgpu_fence_process(ring);
++		up_read(&adev->exclusive_lock);
++
++		if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
++			return true;
++	}
++	return false;
++}
++
++/**
++ * amdgpu_fence_enable_signaling - enable signalling on fence
++ * @fence: fence
++ *
++ * This function is called with fence_queue lock held, and adds a callback
++ * to fence_queue that checks if this fence is signaled, and if so it
++ * signals the fence and removes itself.
++ */
++static bool amdgpu_fence_enable_signaling(struct fence *f)
++{
++	struct amdgpu_fence *fence = to_amdgpu_fence(f);
++	struct amdgpu_ring *ring = fence->ring;
++	struct amdgpu_device *adev = ring->adev;
++
++	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
++		return false;
++
++	if (down_read_trylock(&adev->exclusive_lock)) {
++		amdgpu_irq_get(adev, ring->fence_drv.irq_src,
++			ring->fence_drv.irq_type);
++		if (amdgpu_fence_activity(ring))
++			wake_up_all_locked(&adev->fence_queue);
++
++		/* did fence get signaled after we enabled the sw irq? */
++		if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) {
++			amdgpu_irq_put(adev, ring->fence_drv.irq_src,
++				ring->fence_drv.irq_type);
++			up_read(&adev->exclusive_lock);
++			return false;
++		}
++
++		up_read(&adev->exclusive_lock);
++	} else {
++		/* we're probably in a lockup, lets not fiddle too much */
++		if (amdgpu_irq_get_delayed(adev, ring->fence_drv.irq_src,
++			ring->fence_drv.irq_type))
++			ring->fence_drv.delayed_irq = true;
++		amdgpu_fence_schedule_check(ring);
++	}
++
++	fence->fence_wake.flags = 0;
++	fence->fence_wake.private = NULL;
++	fence->fence_wake.func = amdgpu_fence_check_signaled;
++	__add_wait_queue(&adev->fence_queue, &fence->fence_wake);
++	fence_get(f);
++	FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
++	return true;
++}
++
++/**
++ * amdgpu_fence_signaled - check if a fence has signaled
++ *
++ * @fence: amdgpu fence object
++ *
++ * Check if the requested fence has signaled (all asics).
++ * Returns true if the fence has signaled or false if it has not.
++ */
++bool amdgpu_fence_signaled(struct amdgpu_fence *fence)
++{
++	if (!fence)
++		return true;
++
++	if (fence->seq == AMDGPU_FENCE_SIGNALED_SEQ)
++		return true;
++
++	if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) {
++		fence->seq = AMDGPU_FENCE_SIGNALED_SEQ;
++		if (!fence_signal(&fence->base))
++			FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n");
++		return true;
++	}
++
++	return false;
++}
++
++/**
++ * amdgpu_fence_any_seq_signaled - check if any sequence number is signaled
++ *
++ * @adev: amdgpu device pointer
++ * @seq: sequence numbers
++ *
++ * Check if the last signaled fence sequnce number is >= the requested
++ * sequence number (all asics).
++ * Returns true if any has signaled (current value is >= requested value)
++ * or false if it has not. Helper function for amdgpu_fence_wait_seq.
++ */
++static bool amdgpu_fence_any_seq_signaled(struct amdgpu_device *adev, u64 *seq)
++{
++	unsigned i;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		if (!adev->rings[i] || !seq[i])
++			continue;
++
++		if (amdgpu_fence_seq_signaled(adev->rings[i], seq[i]))
++			return true;
++	}
++
++	return false;
++}
++
++/**
++ * amdgpu_fence_wait_seq_timeout - wait for a specific sequence numbers
++ *
++ * @adev: amdgpu device pointer
++ * @target_seq: sequence number(s) we want to wait for
++ * @intr: use interruptable sleep
++ * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
++ *
++ * Wait for the requested sequence number(s) to be written by any ring
++ * (all asics).  Sequnce number array is indexed by ring id.
++ * @intr selects whether to use interruptable (true) or non-interruptable
++ * (false) sleep when waiting for the sequence number.  Helper function
++ * for amdgpu_fence_wait_*().
++ * Returns remaining time if the sequence number has passed, 0 when
++ * the wait timeout, or an error for all other cases.
++ * -EDEADLK is returned when a GPU lockup has been detected.
++ */
++long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev, u64 *target_seq,
++				   bool intr, long timeout)
++{
++	uint64_t last_seq[AMDGPU_MAX_RINGS];
++	bool signaled;
++	int i, r;
++
++	while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) {
++
++		/* Save current sequence values, used to check for GPU lockups */
++		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++			struct amdgpu_ring *ring = adev->rings[i];
++
++			if (!ring || !target_seq[i])
++				continue;
++
++			last_seq[i] = atomic64_read(&ring->fence_drv.last_seq);
++			trace_amdgpu_fence_wait_begin(adev->ddev, i, target_seq[i]);
++			amdgpu_irq_get(adev, ring->fence_drv.irq_src,
++				       ring->fence_drv.irq_type);
++		}
++
++		if (intr) {
++			r = wait_event_interruptible_timeout(adev->fence_queue, (
++				(signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
++				 || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
++		} else {
++			r = wait_event_timeout(adev->fence_queue, (
++				(signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
++				 || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
++		}
++
++		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++			struct amdgpu_ring *ring = adev->rings[i];
++
++			if (!ring || !target_seq[i])
++				continue;
++
++			amdgpu_irq_put(adev, ring->fence_drv.irq_src,
++				       ring->fence_drv.irq_type);
++			trace_amdgpu_fence_wait_end(adev->ddev, i, target_seq[i]);
++		}
++
++		if (unlikely(r < 0))
++			return r;
++
++		if (unlikely(!signaled)) {
++
++			if (adev->needs_reset)
++				return -EDEADLK;
++
++			/* we were interrupted for some reason and fence
++			 * isn't signaled yet, resume waiting */
++			if (r)
++				continue;
++
++			for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++				struct amdgpu_ring *ring = adev->rings[i];
++
++				if (!ring || !target_seq[i])
++					continue;
++
++				if (last_seq[i] != atomic64_read(&ring->fence_drv.last_seq))
++					break;
++			}
++
++			if (i != AMDGPU_MAX_RINGS)
++				continue;
++
++			for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++				if (!adev->rings[i] || !target_seq[i])
++					continue;
++
++				if (amdgpu_ring_is_lockup(adev->rings[i]))
++					break;
++			}
++
++			if (i < AMDGPU_MAX_RINGS) {
++				/* good news we believe it's a lockup */
++				dev_warn(adev->dev, "GPU lockup (waiting for "
++					 "0x%016llx last fence id 0x%016llx on"
++					 " ring %d)\n",
++					 target_seq[i], last_seq[i], i);
++
++				/* remember that we need an reset */
++				adev->needs_reset = true;
++				wake_up_all(&adev->fence_queue);
++				return -EDEADLK;
++			}
++
++			if (timeout < MAX_SCHEDULE_TIMEOUT) {
++				timeout -= AMDGPU_FENCE_JIFFIES_TIMEOUT;
++				if (timeout <= 0) {
++					return 0;
++				}
++			}
++		}
++	}
++	return timeout;
++}
++
++/**
++ * amdgpu_fence_wait - wait for a fence to signal
++ *
++ * @fence: amdgpu fence object
++ * @intr: use interruptable sleep
++ *
++ * Wait for the requested fence to signal (all asics).
++ * @intr selects whether to use interruptable (true) or non-interruptable
++ * (false) sleep when waiting for the fence.
++ * Returns 0 if the fence has passed, error for all other cases.
++ */
++int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr)
++{
++	uint64_t seq[AMDGPU_MAX_RINGS] = {};
++	long r;
++
++	seq[fence->ring->idx] = fence->seq;
++	if (seq[fence->ring->idx] == AMDGPU_FENCE_SIGNALED_SEQ)
++		return 0;
++
++	r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
++	if (r < 0) {
++		return r;
++	}
++
++	fence->seq = AMDGPU_FENCE_SIGNALED_SEQ;
++	r = fence_signal(&fence->base);
++	if (!r)
++		FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
++	return 0;
++}
++
++/**
++ * amdgpu_fence_wait_any - wait for a fence to signal on any ring
++ *
++ * @adev: amdgpu device pointer
++ * @fences: amdgpu fence object(s)
++ * @intr: use interruptable sleep
++ *
++ * Wait for any requested fence to signal (all asics).  Fence
++ * array is indexed by ring id.  @intr selects whether to use
++ * interruptable (true) or non-interruptable (false) sleep when
++ * waiting for the fences. Used by the suballocator.
++ * Returns 0 if any fence has passed, error for all other cases.
++ */
++int amdgpu_fence_wait_any(struct amdgpu_device *adev,
++			  struct amdgpu_fence **fences,
++			  bool intr)
++{
++	uint64_t seq[AMDGPU_MAX_RINGS];
++	unsigned i, num_rings = 0;
++	long r;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		seq[i] = 0;
++
++		if (!fences[i]) {
++			continue;
++		}
++
++		seq[i] = fences[i]->seq;
++		++num_rings;
++
++		/* test if something was allready signaled */
++		if (seq[i] == AMDGPU_FENCE_SIGNALED_SEQ)
++			return 0;
++	}
++
++	/* nothing to wait for ? */
++	if (num_rings == 0)
++		return -ENOENT;
++
++	r = amdgpu_fence_wait_seq_timeout(adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
++	if (r < 0) {
++		return r;
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_fence_wait_next - wait for the next fence to signal
++ *
++ * @adev: amdgpu device pointer
++ * @ring: ring index the fence is associated with
++ *
++ * Wait for the next fence on the requested ring to signal (all asics).
++ * Returns 0 if the next fence has passed, error for all other cases.
++ * Caller must hold ring lock.
++ */
++int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
++{
++	uint64_t seq[AMDGPU_MAX_RINGS] = {};
++	long r;
++
++	seq[ring->idx] = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
++	if (seq[ring->idx] >= ring->fence_drv.sync_seq[ring->idx]) {
++		/* nothing to wait for, last_seq is
++		   already the last emited fence */
++		return -ENOENT;
++	}
++	r = amdgpu_fence_wait_seq_timeout(ring->adev, seq, false, MAX_SCHEDULE_TIMEOUT);
++	if (r < 0)
++		return r;
++	return 0;
++}
++
++/**
++ * amdgpu_fence_wait_empty - wait for all fences to signal
++ *
++ * @adev: amdgpu device pointer
++ * @ring: ring index the fence is associated with
++ *
++ * Wait for all fences on the requested ring to signal (all asics).
++ * Returns 0 if the fences have passed, error for all other cases.
++ * Caller must hold ring lock.
++ */
++int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint64_t seq[AMDGPU_MAX_RINGS] = {};
++	long r;
++
++	seq[ring->idx] = ring->fence_drv.sync_seq[ring->idx];
++	if (!seq[ring->idx])
++		return 0;
++
++	r = amdgpu_fence_wait_seq_timeout(adev, seq, false, MAX_SCHEDULE_TIMEOUT);
++	if (r < 0) {
++		if (r == -EDEADLK)
++			return -EDEADLK;
++
++		dev_err(adev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
++			ring->idx, r);
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_fence_ref - take a ref on a fence
++ *
++ * @fence: amdgpu fence object
++ *
++ * Take a reference on a fence (all asics).
++ * Returns the fence.
++ */
++struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence)
++{
++	fence_get(&fence->base);
++	return fence;
++}
++
++/**
++ * amdgpu_fence_unref - remove a ref on a fence
++ *
++ * @fence: amdgpu fence object
++ *
++ * Remove a reference on a fence (all asics).
++ */
++void amdgpu_fence_unref(struct amdgpu_fence **fence)
++{
++	struct amdgpu_fence *tmp = *fence;
++
++	*fence = NULL;
++	if (tmp)
++		fence_put(&tmp->base);
++}
++
++/**
++ * amdgpu_fence_count_emitted - get the count of emitted fences
++ *
++ * @ring: ring the fence is associated with
++ *
++ * Get the number of fences emitted on the requested ring (all asics).
++ * Returns the number of emitted fences on the ring.  Used by the
++ * dynpm code to ring track activity.
++ */
++unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
++{
++	uint64_t emitted;
++
++	/* We are not protected by ring lock when reading the last sequence
++	 * but it's ok to report slightly wrong fence count here.
++	 */
++	amdgpu_fence_process(ring);
++	emitted = ring->fence_drv.sync_seq[ring->idx]
++		- atomic64_read(&ring->fence_drv.last_seq);
++	/* to avoid 32bits warp around */
++	if (emitted > 0x10000000)
++		emitted = 0x10000000;
++
++	return (unsigned)emitted;
++}
++
++/**
++ * amdgpu_fence_need_sync - do we need a semaphore
++ *
++ * @fence: amdgpu fence object
++ * @dst_ring: which ring to check against
++ *
++ * Check if the fence needs to be synced against another ring
++ * (all asics).  If so, we need to emit a semaphore.
++ * Returns true if we need to sync with another ring, false if
++ * not.
++ */
++bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
++			    struct amdgpu_ring *dst_ring)
++{
++	struct amdgpu_fence_driver *fdrv;
++
++	if (!fence)
++		return false;
++
++	if (fence->ring == dst_ring)
++		return false;
++
++	/* we are protected by the ring mutex */
++	fdrv = &dst_ring->fence_drv;
++	if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
++		return false;
++
++	return true;
++}
++
++/**
++ * amdgpu_fence_note_sync - record the sync point
++ *
++ * @fence: amdgpu fence object
++ * @dst_ring: which ring to check against
++ *
++ * Note the sequence number at which point the fence will
++ * be synced with the requested ring (all asics).
++ */
++void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
++			    struct amdgpu_ring *dst_ring)
++{
++	struct amdgpu_fence_driver *dst, *src;
++	unsigned i;
++
++	if (!fence)
++		return;
++
++	if (fence->ring == dst_ring)
++		return;
++
++	/* we are protected by the ring mutex */
++	src = &fence->ring->fence_drv;
++	dst = &dst_ring->fence_drv;
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		if (i == dst_ring->idx)
++			continue;
++
++		dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
++	}
++}
++
++/**
++ * amdgpu_fence_driver_start_ring - make the fence driver
++ * ready for use on the requested ring.
++ *
++ * @ring: ring to start the fence driver on
++ * @irq_src: interrupt source to use for this ring
++ * @irq_type: interrupt type to use for this ring
++ *
++ * Make the fence driver ready for processing (all asics).
++ * Not all asics have all rings, so each asic will only
++ * start the fence driver on the rings it has.
++ * Returns 0 for success, errors for failure.
++ */
++int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
++				   struct amdgpu_irq_src *irq_src,
++				   unsigned irq_type)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint64_t index;
++
++	if (ring != &adev->uvd.ring) {
++		ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
++		ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
++	} else {
++		/* put fence directly behind firmware */
++		index = ALIGN(adev->uvd.fw->size, 8);
++		ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
++		ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
++	}
++	amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
++	ring->fence_drv.initialized = true;
++	ring->fence_drv.irq_src = irq_src;
++	ring->fence_drv.irq_type = irq_type;
++	dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
++		 "cpu addr 0x%p\n", ring->idx,
++		 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
++	return 0;
++}
++
++/**
++ * amdgpu_fence_driver_init_ring - init the fence driver
++ * for the requested ring.
++ *
++ * @ring: ring to init the fence driver on
++ *
++ * Init the fence driver for the requested ring (all asics).
++ * Helper function for amdgpu_fence_driver_init().
++ */
++void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
++{
++	int i;
++
++	ring->fence_drv.cpu_addr = NULL;
++	ring->fence_drv.gpu_addr = 0;
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
++		ring->fence_drv.sync_seq[i] = 0;
++
++	atomic64_set(&ring->fence_drv.last_seq, 0);
++	ring->fence_drv.initialized = false;
++
++	INIT_DELAYED_WORK(&ring->fence_drv.lockup_work,
++			amdgpu_fence_check_lockup);
++	ring->fence_drv.ring = ring;
++}
++
++/**
++ * amdgpu_fence_driver_init - init the fence driver
++ * for all possible rings.
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Init the fence driver for all possible rings (all asics).
++ * Not all asics have all rings, so each asic will only
++ * start the fence driver on the rings it has using
++ * amdgpu_fence_driver_start_ring().
++ * Returns 0 for success.
++ */
++int amdgpu_fence_driver_init(struct amdgpu_device *adev)
++{
++	init_waitqueue_head(&adev->fence_queue);
++	if (amdgpu_debugfs_fence_init(adev))
++		dev_err(adev->dev, "fence debugfs file creation failed\n");
++
++	return 0;
++}
++
++/**
++ * amdgpu_fence_driver_fini - tear down the fence driver
++ * for all possible rings.
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Tear down the fence driver for all possible rings (all asics).
++ */
++void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	mutex_lock(&adev->ring_lock);
++	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
++		struct amdgpu_ring *ring = adev->rings[i];
++		if (!ring || !ring->fence_drv.initialized)
++			continue;
++		r = amdgpu_fence_wait_empty(ring);
++		if (r) {
++			/* no need to trigger GPU reset as we are unloading */
++			amdgpu_fence_driver_force_completion(adev);
++		}
++		wake_up_all(&adev->fence_queue);
++		ring->fence_drv.initialized = false;
++	}
++	mutex_unlock(&adev->ring_lock);
++}
++
++/**
++ * amdgpu_fence_driver_force_completion - force all fence waiter to complete
++ *
++ * @adev: amdgpu device pointer
++ *
++ * In case of GPU reset failure make sure no process keep waiting on fence
++ * that will never complete.
++ */
++void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
++		struct amdgpu_ring *ring = adev->rings[i];
++		if (!ring || !ring->fence_drv.initialized)
++			continue;
++
++		amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
++	}
++}
++
++
++/*
++ * Fence debugfs
++ */
++#if defined(CONFIG_DEBUG_FS)
++static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *)m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int i, j;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		struct amdgpu_ring *ring = adev->rings[i];
++		if (!ring || !ring->fence_drv.initialized)
++			continue;
++
++		amdgpu_fence_process(ring);
++
++		seq_printf(m, "--- ring %d ---\n", i);
++		seq_printf(m, "Last signaled fence 0x%016llx\n",
++			   (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
++		seq_printf(m, "Last emitted        0x%016llx\n",
++			   ring->fence_drv.sync_seq[i]);
++
++		for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
++			struct amdgpu_ring *other = adev->rings[j];
++			if (i != j && other && other->fence_drv.initialized)
++				seq_printf(m, "Last sync to ring %d 0x%016llx\n",
++					   j, ring->fence_drv.sync_seq[j]);
++		}
++	}
++	return 0;
++}
++
++static struct drm_info_list amdgpu_debugfs_fence_list[] = {
++	{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
++};
++#endif
++
++int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1);
++#else
++	return 0;
++#endif
++}
++
++static const char *amdgpu_fence_get_driver_name(struct fence *fence)
++{
++	return "amdgpu";
++}
++
++static const char *amdgpu_fence_get_timeline_name(struct fence *f)
++{
++	struct amdgpu_fence *fence = to_amdgpu_fence(f);
++	return (const char *)fence->ring->name;
++}
++
++static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence)
++{
++	return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
++}
++
++struct amdgpu_wait_cb {
++	struct fence_cb base;
++	struct task_struct *task;
++};
++
++static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
++{
++	struct amdgpu_wait_cb *wait =
++		container_of(cb, struct amdgpu_wait_cb, base);
++	wake_up_process(wait->task);
++}
++
++static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
++					     signed long t)
++{
++	struct amdgpu_fence *fence = to_amdgpu_fence(f);
++	struct amdgpu_device *adev = fence->ring->adev;
++	struct amdgpu_wait_cb cb;
++
++	cb.task = current;
++
++	if (fence_add_callback(f, &cb.base, amdgpu_fence_wait_cb))
++		return t;
++
++	while (t > 0) {
++		if (intr)
++			set_current_state(TASK_INTERRUPTIBLE);
++		else
++			set_current_state(TASK_UNINTERRUPTIBLE);
++
++		/*
++		 * amdgpu_test_signaled must be called after
++		 * set_current_state to prevent a race with wake_up_process
++		 */
++		if (amdgpu_test_signaled(fence))
++			break;
++
++		if (adev->needs_reset) {
++			t = -EDEADLK;
++			break;
++		}
++
++		t = schedule_timeout(t);
++
++		if (t > 0 && intr && signal_pending(current))
++			t = -ERESTARTSYS;
++	}
++
++	__set_current_state(TASK_RUNNING);
++	fence_remove_callback(f, &cb.base);
++
++	return t;
++}
++
++const struct fence_ops amdgpu_fence_ops = {
++	.get_driver_name = amdgpu_fence_get_driver_name,
++	.get_timeline_name = amdgpu_fence_get_timeline_name,
++	.enable_signaling = amdgpu_fence_enable_signaling,
++	.signaled = amdgpu_fence_is_signaled,
++	.wait = amdgpu_fence_default_wait,
++	.release = NULL,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+new file mode 100644
+index 0000000..e02db0b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -0,0 +1,371 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++/*
++ * GART
++ * The GART (Graphics Aperture Remapping Table) is an aperture
++ * in the GPU's address space.  System pages can be mapped into
++ * the aperture and look like contiguous pages from the GPU's
++ * perspective.  A page table maps the pages in the aperture
++ * to the actual backing pages in system memory.
++ *
++ * Radeon GPUs support both an internal GART, as described above,
++ * and AGP.  AGP works similarly, but the GART table is configured
++ * and maintained by the northbridge rather than the driver.
++ * Radeon hw has a separate AGP aperture that is programmed to
++ * point to the AGP aperture provided by the northbridge and the
++ * requests are passed through to the northbridge aperture.
++ * Both AGP and internal GART can be used at the same time, however
++ * that is not currently supported by the driver.
++ *
++ * This file handles the common internal GART management.
++ */
++
++/*
++ * Common GART table functions.
++ */
++/**
++ * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate system memory for GART page table
++ * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
++ * gart table to be in system memory.
++ * Returns 0 for success, -ENOMEM for failure.
++ */
++int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
++{
++	void *ptr;
++
++	ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
++				   &adev->gart.table_addr);
++	if (ptr == NULL) {
++		return -ENOMEM;
++	}
++#ifdef CONFIG_X86
++	if (0) {
++		set_memory_uc((unsigned long)ptr,
++			      adev->gart.table_size >> PAGE_SHIFT);
++	}
++#endif
++	adev->gart.ptr = ptr;
++	memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
++	return 0;
++}
++
++/**
++ * amdgpu_gart_table_ram_free - free system ram for gart page table
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Free system memory for GART page table
++ * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
++ * gart table to be in system memory.
++ */
++void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
++{
++	if (adev->gart.ptr == NULL) {
++		return;
++	}
++#ifdef CONFIG_X86
++	if (0) {
++		set_memory_wb((unsigned long)adev->gart.ptr,
++			      adev->gart.table_size >> PAGE_SHIFT);
++	}
++#endif
++	pci_free_consistent(adev->pdev, adev->gart.table_size,
++			    (void *)adev->gart.ptr,
++			    adev->gart.table_addr);
++	adev->gart.ptr = NULL;
++	adev->gart.table_addr = 0;
++}
++
++/**
++ * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate video memory for GART page table
++ * (pcie r4xx, r5xx+).  These asics require the
++ * gart table to be in video memory.
++ * Returns 0 for success, error for failure.
++ */
++int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->gart.robj == NULL) {
++		r = amdgpu_bo_create(adev, adev->gart.table_size,
++				     PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0,
++				     NULL, &adev->gart.robj);
++		if (r) {
++			return r;
++		}
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_gart_table_vram_pin - pin gart page table in vram
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Pin the GART page table in vram so it will not be moved
++ * by the memory manager (pcie r4xx, r5xx+).  These asics require the
++ * gart table to be in video memory.
++ * Returns 0 for success, error for failure.
++ */
++int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
++{
++	uint64_t gpu_addr;
++	int r;
++
++	r = amdgpu_bo_reserve(adev->gart.robj, false);
++	if (unlikely(r != 0))
++		return r;
++	r = amdgpu_bo_pin(adev->gart.robj,
++				AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
++	if (r) {
++		amdgpu_bo_unreserve(adev->gart.robj);
++		return r;
++	}
++	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
++	if (r)
++		amdgpu_bo_unpin(adev->gart.robj);
++	amdgpu_bo_unreserve(adev->gart.robj);
++	adev->gart.table_addr = gpu_addr;
++	return r;
++}
++
++/**
++ * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Unpin the GART page table in vram (pcie r4xx, r5xx+).
++ * These asics require the gart table to be in video memory.
++ */
++void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->gart.robj == NULL) {
++		return;
++	}
++	r = amdgpu_bo_reserve(adev->gart.robj, false);
++	if (likely(r == 0)) {
++		amdgpu_bo_kunmap(adev->gart.robj);
++		amdgpu_bo_unpin(adev->gart.robj);
++		amdgpu_bo_unreserve(adev->gart.robj);
++		adev->gart.ptr = NULL;
++	}
++}
++
++/**
++ * amdgpu_gart_table_vram_free - free gart page table vram
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Free the video memory used for the GART page table
++ * (pcie r4xx, r5xx+).  These asics require the gart table to
++ * be in video memory.
++ */
++void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
++{
++	if (adev->gart.robj == NULL) {
++		return;
++	}
++	amdgpu_bo_unref(&adev->gart.robj);
++}
++
++/*
++ * Common gart functions.
++ */
++/**
++ * amdgpu_gart_unbind - unbind pages from the gart page table
++ *
++ * @adev: amdgpu_device pointer
++ * @offset: offset into the GPU's gart aperture
++ * @pages: number of pages to unbind
++ *
++ * Unbinds the requested pages from the gart page table and
++ * replaces them with the dummy page (all asics).
++ */
++void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
++			int pages)
++{
++	unsigned t;
++	unsigned p;
++	int i, j;
++	u64 page_base;
++	uint32_t flags = AMDGPU_PTE_SYSTEM;
++
++	if (!adev->gart.ready) {
++		WARN(1, "trying to unbind memory from uninitialized GART !\n");
++		return;
++	}
++
++	t = offset / AMDGPU_GPU_PAGE_SIZE;
++	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
++	for (i = 0; i < pages; i++, p++) {
++		if (adev->gart.pages[p]) {
++			adev->gart.pages[p] = NULL;
++			adev->gart.pages_addr[p] = adev->dummy_page.addr;
++			page_base = adev->gart.pages_addr[p];
++			if (!adev->gart.ptr)
++				continue;
++
++			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
++				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
++							t, page_base, flags);
++				page_base += AMDGPU_GPU_PAGE_SIZE;
++			}
++		}
++	}
++	mb();
++	amdgpu_gart_flush_gpu_tlb(adev, 0);
++}
++
++/**
++ * amdgpu_gart_bind - bind pages into the gart page table
++ *
++ * @adev: amdgpu_device pointer
++ * @offset: offset into the GPU's gart aperture
++ * @pages: number of pages to bind
++ * @pagelist: pages to bind
++ * @dma_addr: DMA addresses of pages
++ *
++ * Binds the requested pages to the gart page table
++ * (all asics).
++ * Returns 0 for success, -EINVAL for failure.
++ */
++int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
++		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
++		     uint32_t flags)
++{
++	unsigned t;
++	unsigned p;
++	uint64_t page_base;
++	int i, j;
++
++	if (!adev->gart.ready) {
++		WARN(1, "trying to bind memory to uninitialized GART !\n");
++		return -EINVAL;
++	}
++
++	t = offset / AMDGPU_GPU_PAGE_SIZE;
++	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
++
++	for (i = 0; i < pages; i++, p++) {
++		adev->gart.pages_addr[p] = dma_addr[i];
++		adev->gart.pages[p] = pagelist[i];
++		if (adev->gart.ptr) {
++			page_base = adev->gart.pages_addr[p];
++			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
++				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
++				page_base += AMDGPU_GPU_PAGE_SIZE;
++			}
++		}
++	}
++	mb();
++	amdgpu_gart_flush_gpu_tlb(adev, 0);
++	return 0;
++}
++
++/**
++ * amdgpu_gart_init - init the driver info for managing the gart
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate the dummy page and init the gart driver info (all asics).
++ * Returns 0 for success, error for failure.
++ */
++int amdgpu_gart_init(struct amdgpu_device *adev)
++{
++	int r, i;
++
++	if (adev->gart.pages) {
++		return 0;
++	}
++	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
++	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
++		DRM_ERROR("Page size is smaller than GPU page size!\n");
++		return -EINVAL;
++	}
++	r = amdgpu_dummy_page_init(adev);
++	if (r)
++		return r;
++	/* Compute table size */
++	adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
++	adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
++	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
++		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
++	/* Allocate pages table */
++	adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
++	if (adev->gart.pages == NULL) {
++		amdgpu_gart_fini(adev);
++		return -ENOMEM;
++	}
++	adev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
++					adev->gart.num_cpu_pages);
++	if (adev->gart.pages_addr == NULL) {
++		amdgpu_gart_fini(adev);
++		return -ENOMEM;
++	}
++	/* set GART entry to point to the dummy page by default */
++	for (i = 0; i < adev->gart.num_cpu_pages; i++) {
++		adev->gart.pages_addr[i] = adev->dummy_page.addr;
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_gart_fini - tear down the driver info for managing the gart
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down the gart driver info and free the dummy page (all asics).
++ */
++void amdgpu_gart_fini(struct amdgpu_device *adev)
++{
++	if (adev->gart.pages && adev->gart.pages_addr && adev->gart.ready) {
++		/* unbind pages */
++		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
++	}
++	adev->gart.ready = false;
++	vfree(adev->gart.pages);
++	vfree(adev->gart.pages_addr);
++	adev->gart.pages = NULL;
++	adev->gart.pages_addr = NULL;
++
++	amdgpu_dummy_page_fini(adev);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+new file mode 100644
+index 0000000..c3f4e85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+@@ -0,0 +1,72 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_GDS_H__
++#define __AMDGPU_GDS_H__
++
++/* Because TTM request that alloacted buffer should be PAGE_SIZE aligned,
++ * we should report GDS/GWS/OA size as PAGE_SIZE aligned
++ * */
++#define AMDGPU_GDS_SHIFT	2
++#define AMDGPU_GWS_SHIFT	PAGE_SHIFT
++#define AMDGPU_OA_SHIFT		PAGE_SHIFT
++
++#define AMDGPU_PL_GDS		TTM_PL_PRIV0
++#define AMDGPU_PL_GWS		TTM_PL_PRIV1
++#define AMDGPU_PL_OA		TTM_PL_PRIV2
++
++#define AMDGPU_PL_FLAG_GDS		TTM_PL_FLAG_PRIV0
++#define AMDGPU_PL_FLAG_GWS		TTM_PL_FLAG_PRIV1
++#define AMDGPU_PL_FLAG_OA		TTM_PL_FLAG_PRIV2
++
++struct amdgpu_ring;
++struct amdgpu_bo;
++
++struct amdgpu_gds_asic_info {
++	uint32_t 	total_size;
++	uint32_t	gfx_partition_size;
++	uint32_t	cs_partition_size;
++};
++
++struct amdgpu_gds {
++	struct amdgpu_gds_asic_info	mem;
++	struct amdgpu_gds_asic_info	gws;
++	struct amdgpu_gds_asic_info	oa;
++	/* At present, GDS, GWS and OA resources for gfx (graphics) 
++	 * is always pre-allocated and available for graphics operation. 
++	 * Such resource is shared between all gfx clients.
++	 * TODO: move this operation to user space
++	 * */
++	struct amdgpu_bo*		gds_gfx_bo;
++	struct amdgpu_bo*		gws_gfx_bo;
++	struct amdgpu_bo*		oa_gfx_bo;
++};
++
++struct amdgpu_gds_reg_offset {
++	uint32_t	mem_base;
++	uint32_t	mem_size;
++	uint32_t	gws;
++	uint32_t	oa;
++};
++
++#endif /* __AMDGPU_GDS_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+new file mode 100644
+index 0000000..5fd0bc7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -0,0 +1,735 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <linux/ktime.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++void amdgpu_gem_object_free(struct drm_gem_object *gobj)
++{
++	struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
++
++	if (robj) {
++		if (robj->gem_base.import_attach)
++			drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
++		amdgpu_bo_unref(&robj);
++	}
++}
++
++int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
++				int alignment, u32 initial_domain,
++				u64 flags, bool kernel,
++				struct drm_gem_object **obj)
++{
++	struct amdgpu_bo *robj;
++	unsigned long max_size;
++	int r;
++
++	*obj = NULL;
++	/* At least align on page size */
++	if (alignment < PAGE_SIZE) {
++		alignment = PAGE_SIZE;
++	}
++
++	if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
++		/* Maximum bo size is the unpinned gtt size since we use the gtt to
++		 * handle vram to system pool migrations.
++		 */
++		max_size = adev->mc.gtt_size - adev->gart_pin_size;
++		if (size > max_size) {
++			DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
++				  size >> 20, max_size >> 20);
++			return -ENOMEM;
++		}
++	}
++retry:
++	r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, flags, NULL, &robj);
++	if (r) {
++		if (r != -ERESTARTSYS) {
++			if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
++				initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
++				goto retry;
++			}
++			DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
++				  size, initial_domain, alignment, r);
++		}
++		return r;
++	}
++	*obj = &robj->gem_base;
++	robj->pid = task_pid_nr(current);
++
++	mutex_lock(&adev->gem.mutex);
++	list_add_tail(&robj->list, &adev->gem.objects);
++	mutex_unlock(&adev->gem.mutex);
++
++	return 0;
++}
++
++int amdgpu_gem_init(struct amdgpu_device *adev)
++{
++	INIT_LIST_HEAD(&adev->gem.objects);
++	return 0;
++}
++
++void amdgpu_gem_fini(struct amdgpu_device *adev)
++{
++	amdgpu_bo_force_delete(adev);
++}
++
++/*
++ * Call from drm_gem_handle_create which appear in both new and open ioctl
++ * case.
++ */
++int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
++{
++	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
++	struct amdgpu_device *adev = rbo->adev;
++	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
++	struct amdgpu_vm *vm = &fpriv->vm;
++	struct amdgpu_bo_va *bo_va;
++	int r;
++
++	r = amdgpu_bo_reserve(rbo, false);
++	if (r) {
++		return r;
++	}
++
++	bo_va = amdgpu_vm_bo_find(vm, rbo);
++	if (!bo_va) {
++		bo_va = amdgpu_vm_bo_add(adev, vm, rbo);
++	} else {
++		++bo_va->ref_count;
++	}
++	amdgpu_bo_unreserve(rbo);
++
++	return 0;
++}
++
++void amdgpu_gem_object_close(struct drm_gem_object *obj,
++			     struct drm_file *file_priv)
++{
++	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
++	struct amdgpu_device *adev = rbo->adev;
++	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
++	struct amdgpu_vm *vm = &fpriv->vm;
++	struct amdgpu_bo_va *bo_va;
++	int r;
++
++	r = amdgpu_bo_reserve(rbo, true);
++	if (r) {
++		dev_err(adev->dev, "leaking bo va because "
++			"we fail to reserve bo (%d)\n", r);
++		return;
++	}
++	bo_va = amdgpu_vm_bo_find(vm, rbo);
++	if (bo_va) {
++		if (--bo_va->ref_count == 0) {
++			amdgpu_vm_bo_rmv(adev, bo_va);
++		}
++	}
++	amdgpu_bo_unreserve(rbo);
++}
++
++static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
++{
++	if (r == -EDEADLK) {
++		r = amdgpu_gpu_reset(adev);
++		if (!r)
++			r = -EAGAIN;
++	}
++	return r;
++}
++
++/*
++ * GEM ioctls.
++ */
++int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
++			    struct drm_file *filp)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	union drm_amdgpu_gem_create *args = data;
++	uint64_t size = args->in.bo_size;
++	struct drm_gem_object *gobj;
++	uint32_t handle;
++	bool kernel = false;
++	int r;
++
++	down_read(&adev->exclusive_lock);
++	/* create a gem object to contain this object in */
++	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
++	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
++		kernel = true;
++		if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
++			size = size << AMDGPU_GDS_SHIFT;
++		else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
++			size = size << AMDGPU_GWS_SHIFT;
++		else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
++			size = size << AMDGPU_OA_SHIFT;
++		else {
++			r = -EINVAL;
++			goto error_unlock;
++		}
++	}
++	size = roundup(size, PAGE_SIZE);
++
++	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
++				     (u32)(0xffffffff & args->in.domains),
++				     args->in.domain_flags,
++				     kernel, &gobj);
++	if (r)
++		goto error_unlock;
++
++	r = drm_gem_handle_create(filp, gobj, &handle);
++	/* drop reference from allocate - handle holds it now */
++	drm_gem_object_unreference_unlocked(gobj);
++	if (r)
++		goto error_unlock;
++
++	memset(args, 0, sizeof(*args));
++	args->out.handle = handle;
++	up_read(&adev->exclusive_lock);
++	return 0;
++
++error_unlock:
++	up_read(&adev->exclusive_lock);
++	r = amdgpu_gem_handle_lockup(adev, r);
++	return r;
++}
++
++int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
++			     struct drm_file *filp)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_amdgpu_gem_userptr *args = data;
++	struct drm_gem_object *gobj;
++	struct amdgpu_bo *bo;
++	uint32_t handle;
++	int r;
++
++	if (offset_in_page(args->addr | args->size))
++		return -EINVAL;
++
++	/* reject unknown flag values */
++	if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
++	    AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
++	    AMDGPU_GEM_USERPTR_REGISTER))
++		return -EINVAL;
++
++	if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
++		   !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
++
++		/* if we want to write to it we must require anonymous
++		   memory and install a MMU notifier */
++		return -EACCES;
++	}
++
++	down_read(&adev->exclusive_lock);
++
++	/* create a gem object to contain this object in */
++	r = amdgpu_gem_object_create(adev, args->size, 0,
++				     AMDGPU_GEM_DOMAIN_CPU, 0,
++				     0, &gobj);
++	if (r)
++		goto handle_lockup;
++
++	bo = gem_to_amdgpu_bo(gobj);
++	r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
++	if (r)
++		goto release_object;
++
++	if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
++		r = amdgpu_mn_register(bo, args->addr);
++		if (r)
++			goto release_object;
++	}
++
++	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
++		down_read(&current->mm->mmap_sem);
++		r = amdgpu_bo_reserve(bo, true);
++		if (r) {
++			up_read(&current->mm->mmap_sem);
++			goto release_object;
++		}
++
++		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
++		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
++		amdgpu_bo_unreserve(bo);
++		up_read(&current->mm->mmap_sem);
++		if (r)
++			goto release_object;
++	}
++
++	r = drm_gem_handle_create(filp, gobj, &handle);
++	/* drop reference from allocate - handle holds it now */
++	drm_gem_object_unreference_unlocked(gobj);
++	if (r)
++		goto handle_lockup;
++
++	args->handle = handle;
++	up_read(&adev->exclusive_lock);
++	return 0;
++
++release_object:
++	drm_gem_object_unreference_unlocked(gobj);
++
++handle_lockup:
++	up_read(&adev->exclusive_lock);
++	r = amdgpu_gem_handle_lockup(adev, r);
++
++	return r;
++}
++
++int amdgpu_mode_dumb_mmap(struct drm_file *filp,
++			  struct drm_device *dev,
++			  uint32_t handle, uint64_t *offset_p)
++{
++	struct drm_gem_object *gobj;
++	struct amdgpu_bo *robj;
++
++	gobj = drm_gem_object_lookup(dev, filp, handle);
++	if (gobj == NULL) {
++		return -ENOENT;
++	}
++	robj = gem_to_amdgpu_bo(gobj);
++	if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
++		drm_gem_object_unreference_unlocked(gobj);
++		return -EPERM;
++	}
++	*offset_p = amdgpu_bo_mmap_offset(robj);
++	drm_gem_object_unreference_unlocked(gobj);
++	return 0;
++}
++
++int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
++			  struct drm_file *filp)
++{
++	union drm_amdgpu_gem_mmap *args = data;
++	uint32_t handle = args->in.handle;
++	memset(args, 0, sizeof(*args));
++	return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
++}
++
++/**
++ * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
++ *
++ * @timeout_ns: timeout in ns
++ *
++ * Calculate the timeout in jiffies from an absolute timeout in ns.
++ */
++unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
++{
++	unsigned long timeout_jiffies;
++	ktime_t timeout;
++
++	/* clamp timeout if it's to large */
++	if (((int64_t)timeout_ns) < 0)
++		return MAX_SCHEDULE_TIMEOUT;
++
++	timeout = ktime_sub_ns(ktime_get(), timeout_ns);
++	if (ktime_to_ns(timeout) < 0)
++		return 0;
++
++	timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
++	/*  clamp timeout to avoid unsigned-> signed overflow */
++	if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
++		return MAX_SCHEDULE_TIMEOUT - 1;
++
++	return timeout_jiffies;
++}
++
++int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
++			      struct drm_file *filp)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	union drm_amdgpu_gem_wait_idle *args = data;
++	struct drm_gem_object *gobj;
++	struct amdgpu_bo *robj;
++	uint32_t handle = args->in.handle;
++	unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
++	int r = 0;
++	long ret;
++
++	gobj = drm_gem_object_lookup(dev, filp, handle);
++	if (gobj == NULL) {
++		return -ENOENT;
++	}
++	robj = gem_to_amdgpu_bo(gobj);
++	if (timeout == 0)
++		ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
++	else
++		ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
++
++	/* ret == 0 means not signaled,
++	 * ret > 0 means signaled
++	 * ret < 0 means interrupted before timeout
++	 */
++	if (ret >= 0) {
++		memset(args, 0, sizeof(*args));
++		args->out.status = (ret == 0);
++	} else
++		r = ret;
++
++	drm_gem_object_unreference_unlocked(gobj);
++	r = amdgpu_gem_handle_lockup(adev, r);
++	return r;
++}
++
++int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
++				struct drm_file *filp)
++{
++	struct drm_amdgpu_gem_metadata *args = data;
++	struct drm_gem_object *gobj;
++	struct amdgpu_bo *robj;
++	int r = -1;
++
++	DRM_DEBUG("%d \n", args->handle);
++	gobj = drm_gem_object_lookup(dev, filp, args->handle);
++	if (gobj == NULL)
++		return -ENOENT;
++	robj = gem_to_amdgpu_bo(gobj);
++
++	r = amdgpu_bo_reserve(robj, false);
++	if (unlikely(r != 0))
++		goto out;
++
++	if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
++		amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
++		r = amdgpu_bo_get_metadata(robj, args->data.data,
++					   sizeof(args->data.data),
++					   &args->data.data_size_bytes,
++					   &args->data.flags);
++	} else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
++		r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
++		if (!r)
++			r = amdgpu_bo_set_metadata(robj, args->data.data,
++						   args->data.data_size_bytes,
++						   args->data.flags);
++	}
++
++	amdgpu_bo_unreserve(robj);
++out:
++	drm_gem_object_unreference_unlocked(gobj);
++	return r;
++}
++
++/**
++ * amdgpu_gem_va_update_vm -update the bo_va in its VM
++ *
++ * @adev: amdgpu_device pointer
++ * @bo_va: bo_va to update
++ *
++ * Update the bo_va directly after setting it's address. Errors are not
++ * vital here, so they are not reported back to userspace.
++ */
++static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
++				    struct amdgpu_bo_va *bo_va)
++{
++	struct ttm_validate_buffer tv, *entry;
++	struct amdgpu_bo_list_entry *vm_bos;
++	struct ww_acquire_ctx ticket;
++	struct list_head list;
++	unsigned domain;
++	int r;
++
++	INIT_LIST_HEAD(&list);
++
++	tv.bo = &bo_va->bo->tbo;
++	tv.shared = true;
++	list_add(&tv.head, &list);
++
++	vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
++	if (!vm_bos)
++		return;
++
++	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
++	if (r)
++		goto error_free;
++
++	list_for_each_entry(entry, &list, head) {
++		domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
++		/* if anything is swapped out don't swap it in here,
++		   just abort and wait for the next CS */
++		if (domain == AMDGPU_GEM_DOMAIN_CPU)
++			goto error_unreserve;
++	}
++
++	mutex_lock(&bo_va->vm->mutex);
++	r = amdgpu_vm_clear_freed(adev, bo_va->vm);
++	if (r)
++		goto error_unlock;
++
++	r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
++
++error_unlock:
++	mutex_unlock(&bo_va->vm->mutex);
++
++error_unreserve:
++	ttm_eu_backoff_reservation(&ticket, &list);
++
++error_free:
++	drm_free_large(vm_bos);
++
++	if (r)
++		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
++}
++
++
++
++int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
++			  struct drm_file *filp)
++{
++	union drm_amdgpu_gem_va *args = data;
++	struct drm_gem_object *gobj;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_fpriv *fpriv = filp->driver_priv;
++	struct amdgpu_bo *rbo;
++	struct amdgpu_bo_va *bo_va;
++	uint32_t invalid_flags, va_flags = 0;
++	int r = 0;
++
++	if (!adev->vm_manager.enabled) {
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++		return -ENOTTY;
++	}
++
++	if (args->in.va_address < AMDGPU_VA_RESERVED_SIZE) {
++		dev_err(&dev->pdev->dev,
++			"va_address 0x%lX is in reserved area 0x%X\n",
++			(unsigned long)args->in.va_address,
++			AMDGPU_VA_RESERVED_SIZE);
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++		return -EINVAL;
++	}
++
++	invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
++			AMDGPU_VM_PAGE_EXECUTABLE);
++	if ((args->in.flags & invalid_flags)) {
++		dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
++			args->in.flags, invalid_flags);
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++		return -EINVAL;
++	}
++
++	switch (args->in.operation) {
++	case AMDGPU_VA_OP_MAP:
++	case AMDGPU_VA_OP_UNMAP:
++		break;
++	default:
++		dev_err(&dev->pdev->dev, "unsupported operation %d\n",
++			args->in.operation);
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++		return -EINVAL;
++	}
++
++	gobj = drm_gem_object_lookup(dev, filp, args->in.handle);
++	if (gobj == NULL) {
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++		return -ENOENT;
++	}
++	rbo = gem_to_amdgpu_bo(gobj);
++	r = amdgpu_bo_reserve(rbo, false);
++	if (r) {
++		if (r != -ERESTARTSYS) {
++			memset(args, 0, sizeof(*args));
++			args->out.result = AMDGPU_VA_RESULT_ERROR;
++		}
++		drm_gem_object_unreference_unlocked(gobj);
++		return r;
++	}
++	bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
++	if (!bo_va) {
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++		drm_gem_object_unreference_unlocked(gobj);
++		return -ENOENT;
++	}
++
++	switch (args->in.operation) {
++	case AMDGPU_VA_OP_MAP:
++		if (args->in.flags & AMDGPU_VM_PAGE_READABLE)
++			va_flags |= AMDGPU_PTE_READABLE;
++		if (args->in.flags & AMDGPU_VM_PAGE_WRITEABLE)
++			va_flags |= AMDGPU_PTE_WRITEABLE;
++		if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE)
++			va_flags |= AMDGPU_PTE_EXECUTABLE;
++		r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, 0,
++				     amdgpu_bo_size(bo_va->bo), va_flags);
++		break;
++	case AMDGPU_VA_OP_UNMAP:
++		r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address);
++		break;
++	default:
++		break;
++	}
++
++	if (!r) {
++		amdgpu_gem_va_update_vm(adev, bo_va);
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_OK;
++	} else {
++		memset(args, 0, sizeof(*args));
++		args->out.result = AMDGPU_VA_RESULT_ERROR;
++	}
++
++	drm_gem_object_unreference_unlocked(gobj);
++	return r;
++}
++
++int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
++			struct drm_file *filp)
++{
++	struct drm_amdgpu_gem_op *args = data;
++	struct drm_gem_object *gobj;
++	struct amdgpu_bo *robj;
++	int r;
++
++	gobj = drm_gem_object_lookup(dev, filp, args->handle);
++	if (gobj == NULL) {
++		return -ENOENT;
++	}
++	robj = gem_to_amdgpu_bo(gobj);
++
++	r = amdgpu_bo_reserve(robj, false);
++	if (unlikely(r))
++		goto out;
++
++	switch (args->op) {
++	case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
++		struct drm_amdgpu_gem_create_in info;
++		void __user *out = (void __user *)(long)args->value;
++
++		info.bo_size = robj->gem_base.size;
++		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
++		info.domains = robj->initial_domain;
++		info.domain_flags = robj->flags;
++		if (copy_to_user(out, &info, sizeof(info)))
++			r = -EFAULT;
++		break;
++	}
++	case AMDGPU_GEM_OP_SET_INITIAL_DOMAIN:
++		if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
++			r = -EPERM;
++			break;
++		}
++		robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
++						      AMDGPU_GEM_DOMAIN_GTT |
++						      AMDGPU_GEM_DOMAIN_CPU);
++		break;
++	default:
++		r = -EINVAL;
++	}
++
++	amdgpu_bo_unreserve(robj);
++out:
++	drm_gem_object_unreference_unlocked(gobj);
++	return r;
++}
++
++int amdgpu_mode_dumb_create(struct drm_file *file_priv,
++			    struct drm_device *dev,
++			    struct drm_mode_create_dumb *args)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_gem_object *gobj;
++	uint32_t handle;
++	int r;
++
++	args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
++	args->size = args->pitch * args->height;
++	args->size = ALIGN(args->size, PAGE_SIZE);
++
++	r = amdgpu_gem_object_create(adev, args->size, 0,
++				     AMDGPU_GEM_DOMAIN_VRAM,
++				     0, ttm_bo_type_device,
++				     &gobj);
++	if (r)
++		return -ENOMEM;
++
++	r = drm_gem_handle_create(file_priv, gobj, &handle);
++	/* drop reference from allocate - handle holds it now */
++	drm_gem_object_unreference_unlocked(gobj);
++	if (r) {
++		return r;
++	}
++	args->handle = handle;
++	return 0;
++}
++
++#if defined(CONFIG_DEBUG_FS)
++static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *)m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_bo *rbo;
++	unsigned i = 0;
++
++	mutex_lock(&adev->gem.mutex);
++	list_for_each_entry(rbo, &adev->gem.objects, list) {
++		unsigned domain;
++		const char *placement;
++
++		domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
++		switch (domain) {
++		case AMDGPU_GEM_DOMAIN_VRAM:
++			placement = "VRAM";
++			break;
++		case AMDGPU_GEM_DOMAIN_GTT:
++			placement = " GTT";
++			break;
++		case AMDGPU_GEM_DOMAIN_CPU:
++		default:
++			placement = " CPU";
++			break;
++		}
++		seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
++			   i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
++			   placement, (unsigned long)rbo->pid);
++		i++;
++	}
++	mutex_unlock(&adev->gem.mutex);
++	return 0;
++}
++
++static struct drm_info_list amdgpu_debugfs_gem_list[] = {
++	{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
++};
++#endif
++
++int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
++#endif
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+new file mode 100644
+index 0000000..9f95da4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -0,0 +1,72 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <drm/drmP.h>
++#include "amdgpu.h"
++
++/*
++ * GPU scratch registers helpers function.
++ */
++/**
++ * amdgpu_gfx_scratch_get - Allocate a scratch register
++ *
++ * @adev: amdgpu_device pointer
++ * @reg: scratch register mmio offset
++ *
++ * Allocate a CP scratch register for use by the driver (all asics).
++ * Returns 0 on success or -EINVAL on failure.
++ */
++int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
++{
++	int i;
++
++	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
++		if (adev->gfx.scratch.free[i]) {
++			adev->gfx.scratch.free[i] = false;
++			*reg = adev->gfx.scratch.reg[i];
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++/**
++ * amdgpu_gfx_scratch_free - Free a scratch register
++ *
++ * @adev: amdgpu_device pointer
++ * @reg: scratch register mmio offset
++ *
++ * Free a CP scratch register allocated for use by the driver (all asics)
++ */
++void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
++{
++	int i;
++
++	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
++		if (adev->gfx.scratch.reg[i] == reg) {
++			adev->gfx.scratch.free[i] = true;
++			return;
++		}
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+new file mode 100644
+index 0000000..dc06cbd
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -0,0 +1,30 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_GFX_H__
++#define __AMDGPU_GFX_H__
++
++int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
++void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c
+new file mode 100644
+index 0000000..31a6763
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c
+@@ -0,0 +1,395 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <linux/export.h>
++
++#include <drm/drmP.h>
++#include <drm/drm_edid.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_i2c.h"
++#include "amdgpu_atombios.h"
++#include "atom.h"
++#include "atombios_dp.h"
++#include "atombios_i2c.h"
++
++/* bit banging i2c */
++static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
++	struct amdgpu_device *adev = i2c->dev->dev_private;
++	struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
++	uint32_t temp;
++
++	mutex_lock(&i2c->mutex);
++
++	/* switch the pads to ddc mode */
++	if (rec->hw_capable) {
++		temp = RREG32(rec->mask_clk_reg);
++		temp &= ~(1 << 16);
++		WREG32(rec->mask_clk_reg, temp);
++	}
++
++	/* clear the output pin values */
++	temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
++	WREG32(rec->a_clk_reg, temp);
++
++	temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
++	WREG32(rec->a_data_reg, temp);
++
++	/* set the pins to input */
++	temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
++	WREG32(rec->en_clk_reg, temp);
++
++	temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
++	WREG32(rec->en_data_reg, temp);
++
++	/* mask the gpio pins for software use */
++	temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
++	WREG32(rec->mask_clk_reg, temp);
++	temp = RREG32(rec->mask_clk_reg);
++
++	temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
++	WREG32(rec->mask_data_reg, temp);
++	temp = RREG32(rec->mask_data_reg);
++
++	return 0;
++}
++
++static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
++	struct amdgpu_device *adev = i2c->dev->dev_private;
++	struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
++	uint32_t temp;
++
++	/* unmask the gpio pins for software use */
++	temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
++	WREG32(rec->mask_clk_reg, temp);
++	temp = RREG32(rec->mask_clk_reg);
++
++	temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
++	WREG32(rec->mask_data_reg, temp);
++	temp = RREG32(rec->mask_data_reg);
++
++	mutex_unlock(&i2c->mutex);
++}
++
++static int amdgpu_i2c_get_clock(void *i2c_priv)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_priv;
++	struct amdgpu_device *adev = i2c->dev->dev_private;
++	struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
++	uint32_t val;
++
++	/* read the value off the pin */
++	val = RREG32(rec->y_clk_reg);
++	val &= rec->y_clk_mask;
++
++	return (val != 0);
++}
++
++
++static int amdgpu_i2c_get_data(void *i2c_priv)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_priv;
++	struct amdgpu_device *adev = i2c->dev->dev_private;
++	struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
++	uint32_t val;
++
++	/* read the value off the pin */
++	val = RREG32(rec->y_data_reg);
++	val &= rec->y_data_mask;
++
++	return (val != 0);
++}
++
++static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_priv;
++	struct amdgpu_device *adev = i2c->dev->dev_private;
++	struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
++	uint32_t val;
++
++	/* set pin direction */
++	val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
++	val |= clock ? 0 : rec->en_clk_mask;
++	WREG32(rec->en_clk_reg, val);
++}
++
++static void amdgpu_i2c_set_data(void *i2c_priv, int data)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_priv;
++	struct amdgpu_device *adev = i2c->dev->dev_private;
++	struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
++	uint32_t val;
++
++	/* set pin direction */
++	val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
++	val |= data ? 0 : rec->en_data_mask;
++	WREG32(rec->en_data_reg, val);
++}
++
++static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
++	.master_xfer = amdgpu_atombios_i2c_xfer,
++	.functionality = amdgpu_atombios_i2c_func,
++};
++
++struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
++					    struct amdgpu_i2c_bus_rec *rec,
++					    const char *name)
++{
++	struct amdgpu_i2c_chan *i2c;
++	int ret;
++
++	/* don't add the mm_i2c bus unless hw_i2c is enabled */
++	if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
++		return NULL;
++
++	i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
++	if (i2c == NULL)
++		return NULL;
++
++	i2c->rec = *rec;
++	i2c->adapter.owner = THIS_MODULE;
++	i2c->adapter.class = I2C_CLASS_DDC;
++	i2c->adapter.dev.parent = &dev->pdev->dev;
++	i2c->dev = dev;
++	i2c_set_adapdata(&i2c->adapter, i2c);
++	mutex_init(&i2c->mutex);
++	if (rec->hw_capable &&
++	    amdgpu_hw_i2c) {
++		/* hw i2c using atom */
++		snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
++			 "AMDGPU i2c hw bus %s", name);
++		i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
++		ret = i2c_add_adapter(&i2c->adapter);
++		if (ret) {
++			DRM_ERROR("Failed to register hw i2c %s\n", name);
++			goto out_free;
++		}
++	} else {
++		/* set the amdgpu bit adapter */
++		snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
++			 "AMDGPU i2c bit bus %s", name);
++		i2c->adapter.algo_data = &i2c->bit;
++		i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
++		i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
++		i2c->bit.setsda = amdgpu_i2c_set_data;
++		i2c->bit.setscl = amdgpu_i2c_set_clock;
++		i2c->bit.getsda = amdgpu_i2c_get_data;
++		i2c->bit.getscl = amdgpu_i2c_get_clock;
++		i2c->bit.udelay = 10;
++		i2c->bit.timeout = usecs_to_jiffies(2200);	/* from VESA */
++		i2c->bit.data = i2c;
++		ret = i2c_bit_add_bus(&i2c->adapter);
++		if (ret) {
++			DRM_ERROR("Failed to register bit i2c %s\n", name);
++			goto out_free;
++		}
++	}
++
++	return i2c;
++out_free:
++	kfree(i2c);
++	return NULL;
++
++}
++
++void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
++{
++	if (!i2c)
++		return;
++	i2c_del_adapter(&i2c->adapter);
++	kfree(i2c);
++}
++
++/* Add the default buses */
++void amdgpu_i2c_init(struct amdgpu_device *adev)
++{
++	if (amdgpu_hw_i2c)
++		DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
++
++	if (adev->is_atom_bios)
++		amdgpu_atombios_i2c_init(adev);
++}
++
++/* remove all the buses */
++void amdgpu_i2c_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
++		if (adev->i2c_bus[i]) {
++			amdgpu_i2c_destroy(adev->i2c_bus[i]);
++			adev->i2c_bus[i] = NULL;
++		}
++	}
++}
++
++/* Add additional buses */
++void amdgpu_i2c_add(struct amdgpu_device *adev,
++		     struct amdgpu_i2c_bus_rec *rec,
++		     const char *name)
++{
++	struct drm_device *dev = adev->ddev;
++	int i;
++
++	for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
++		if (!adev->i2c_bus[i]) {
++			adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
++			return;
++		}
++	}
++}
++
++/* looks up bus based on id */
++struct amdgpu_i2c_chan *
++amdgpu_i2c_lookup(struct amdgpu_device *adev,
++		   struct amdgpu_i2c_bus_rec *i2c_bus)
++{
++	int i;
++
++	for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
++		if (adev->i2c_bus[i] &&
++		    (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
++			return adev->i2c_bus[i];
++		}
++	}
++	return NULL;
++}
++
++static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
++				 u8 slave_addr,
++				 u8 addr,
++				 u8 *val)
++{
++	u8 out_buf[2];
++	u8 in_buf[2];
++	struct i2c_msg msgs[] = {
++		{
++			.addr = slave_addr,
++			.flags = 0,
++			.len = 1,
++			.buf = out_buf,
++		},
++		{
++			.addr = slave_addr,
++			.flags = I2C_M_RD,
++			.len = 1,
++			.buf = in_buf,
++		}
++	};
++
++	out_buf[0] = addr;
++	out_buf[1] = 0;
++
++	if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
++		*val = in_buf[0];
++		DRM_DEBUG("val = 0x%02x\n", *val);
++	} else {
++		DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
++			  addr, *val);
++	}
++}
++
++static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
++				 u8 slave_addr,
++				 u8 addr,
++				 u8 val)
++{
++	uint8_t out_buf[2];
++	struct i2c_msg msg = {
++		.addr = slave_addr,
++		.flags = 0,
++		.len = 2,
++		.buf = out_buf,
++	};
++
++	out_buf[0] = addr;
++	out_buf[1] = val;
++
++	if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
++		DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
++			  addr, val);
++}
++
++/* ddc router switching */
++void
++amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector)
++{
++	u8 val;
++
++	if (!amdgpu_connector->router.ddc_valid)
++		return;
++
++	if (!amdgpu_connector->router_bus)
++		return;
++
++	amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x3, &val);
++	val &= ~amdgpu_connector->router.ddc_mux_control_pin;
++	amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x3, val);
++	amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x1, &val);
++	val &= ~amdgpu_connector->router.ddc_mux_control_pin;
++	val |= amdgpu_connector->router.ddc_mux_state;
++	amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x1, val);
++}
++
++/* clock/data router switching */
++void
++amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector)
++{
++	u8 val;
++
++	if (!amdgpu_connector->router.cd_valid)
++		return;
++
++	if (!amdgpu_connector->router_bus)
++		return;
++
++	amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x3, &val);
++	val &= ~amdgpu_connector->router.cd_mux_control_pin;
++	amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x3, val);
++	amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x1, &val);
++	val &= ~amdgpu_connector->router.cd_mux_control_pin;
++	val |= amdgpu_connector->router.cd_mux_state;
++	amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
++			    amdgpu_connector->router.i2c_addr,
++			    0x1, val);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h
+new file mode 100644
+index 0000000..d81e19b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h
+@@ -0,0 +1,44 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_I2C_H__
++#define __AMDGPU_I2C_H__
++
++struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
++					    struct amdgpu_i2c_bus_rec *rec,
++					    const char *name);
++void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c);
++void amdgpu_i2c_init(struct amdgpu_device *adev);
++void amdgpu_i2c_fini(struct amdgpu_device *adev);
++void amdgpu_i2c_add(struct amdgpu_device *adev,
++		     struct amdgpu_i2c_bus_rec *rec,
++		     const char *name);
++struct amdgpu_i2c_chan *
++amdgpu_i2c_lookup(struct amdgpu_device *adev,
++		   struct amdgpu_i2c_bus_rec *i2c_bus);
++void
++amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector);
++void
++amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+new file mode 100644
+index 0000000..847cab2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -0,0 +1,345 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ *          Christian König
++ */
++#include <linux/seq_file.h>
++#include <linux/slab.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "atom.h"
++
++/*
++ * IB
++ * IBs (Indirect Buffers) and areas of GPU accessible memory where
++ * commands are stored.  You can put a pointer to the IB in the
++ * command ring and the hw will fetch the commands from the IB
++ * and execute them.  Generally userspace acceleration drivers
++ * produce command buffers which are send to the kernel and
++ * put in IBs for execution by the requested ring.
++ */
++static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
++
++/**
++ * amdgpu_ib_get - request an IB (Indirect Buffer)
++ *
++ * @ring: ring index the IB is associated with
++ * @size: requested IB size
++ * @ib: IB object returned
++ *
++ * Request an IB (all asics).  IBs are allocated using the
++ * suballocator.
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
++		  unsigned size, struct amdgpu_ib *ib)
++{
++	struct amdgpu_device *adev = ring->adev;
++	int r;
++
++	if (size) {
++		r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo,
++				      &ib->sa_bo, size, 256);
++		if (r) {
++			dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
++			return r;
++		}
++
++		ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
++
++		if (!vm)
++			ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
++		else
++			ib->gpu_addr = 0;
++
++	} else {
++		ib->sa_bo = NULL;
++		ib->ptr = NULL;
++		ib->gpu_addr = 0;
++	}
++
++	amdgpu_sync_create(&ib->sync);
++
++	ib->ring = ring;
++	ib->fence = NULL;
++	ib->user = NULL;
++	ib->vm = vm;
++	ib->is_const_ib = false;
++	ib->gds_base = 0;
++	ib->gds_size = 0;
++	ib->gws_base = 0;
++	ib->gws_size = 0;
++	ib->oa_base = 0;
++	ib->oa_size = 0;
++
++	return 0;
++}
++
++/**
++ * amdgpu_ib_free - free an IB (Indirect Buffer)
++ *
++ * @adev: amdgpu_device pointer
++ * @ib: IB object to free
++ *
++ * Free an IB (all asics).
++ */
++void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
++{
++	amdgpu_sync_free(adev, &ib->sync, ib->fence);
++	amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence);
++	amdgpu_fence_unref(&ib->fence);
++}
++
++/**
++ * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
++ *
++ * @adev: amdgpu_device pointer
++ * @num_ibs: number of IBs to schedule
++ * @ibs: IB objects to schedule
++ * @owner: owner for creating the fences
++ *
++ * Schedule an IB on the associated ring (all asics).
++ * Returns 0 on success, error on failure.
++ *
++ * On SI, there are two parallel engines fed from the primary ring,
++ * the CE (Constant Engine) and the DE (Drawing Engine).  Since
++ * resource descriptors have moved to memory, the CE allows you to
++ * prime the caches while the DE is updating register state so that
++ * the resource descriptors will be already in cache when the draw is
++ * processed.  To accomplish this, the userspace driver submits two
++ * IBs, one for the CE and one for the DE.  If there is a CE IB (called
++ * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
++ * to SI there was just a DE IB.
++ */
++int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
++		       struct amdgpu_ib *ibs, void *owner)
++{
++	struct amdgpu_ring *ring;
++	struct amdgpu_vm *vm = ibs->vm;
++	struct amdgpu_ib *ib = &ibs[0];
++	unsigned i;
++	int r = 0;
++	bool flush_hdp = true;
++
++	if (num_ibs == 0)
++		return -EINVAL;
++
++	ring = ibs->ring;
++	if (!ring->ready) {
++		dev_err(adev->dev, "couldn't schedule ib\n");
++		return -EINVAL;
++	}
++
++	r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
++	if (r) {
++		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
++		return r;
++	}
++
++	if (vm) {
++		/* grab a vm id if necessary */
++		struct amdgpu_fence *vm_id_fence = NULL;
++		vm_id_fence = amdgpu_vm_grab_id(ibs->ring, ibs->vm);
++		amdgpu_sync_fence(&ibs->sync, vm_id_fence);
++	}
++
++	r = amdgpu_sync_rings(&ibs->sync, ring);
++	if (r) {
++		amdgpu_ring_unlock_undo(ring);
++		dev_err(adev->dev, "failed to sync rings (%d)\n", r);
++		return r;
++	}
++
++	if (vm) {
++		/* do context switch */
++		amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
++	}
++
++	if (ring->funcs->emit_gds_switch && ib->vm && ib->gds_needed)
++		amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
++					    ib->gds_base, ib->gds_size,
++					    ib->gws_base, ib->gws_size,
++					    ib->oa_base, ib->oa_size);
++
++	for (i = 0; i < num_ibs; ++i) {
++		ib = &ibs[i];
++
++		if (ib->ring != ring) {
++			amdgpu_ring_unlock_undo(ring);
++			return -EINVAL;
++		}
++		ib->flush_hdp_writefifo = flush_hdp;
++		flush_hdp = false;
++		amdgpu_ring_emit_ib(ring, ib);
++	}
++
++	r = amdgpu_fence_emit(ring, owner, &ib->fence);
++	if (r) {
++		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
++		amdgpu_ring_unlock_undo(ring);
++		return r;
++	}
++
++	/* wrap the last IB with fence */
++	if (ib->user) {
++		uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
++		addr += ib->user->offset;
++		amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, true);
++	}
++
++	if (ib->vm)
++		amdgpu_vm_fence(adev, ib->vm, ib->fence);
++
++	amdgpu_ring_unlock_commit(ring);
++	return 0;
++}
++
++/**
++ * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initialize the suballocator to manage a pool of memory
++ * for use as IBs (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_ib_pool_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->ib_pool_ready) {
++		return 0;
++	}
++	r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
++				      AMDGPU_IB_POOL_SIZE*64*1024,
++				      AMDGPU_GPU_PAGE_SIZE,
++				      AMDGPU_GEM_DOMAIN_GTT);
++	if (r) {
++		return r;
++	}
++
++	r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
++	if (r) {
++		return r;
++	}
++
++	adev->ib_pool_ready = true;
++	if (amdgpu_debugfs_sa_init(adev)) {
++		dev_err(adev->dev, "failed to register debugfs file for SA\n");
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down the suballocator managing the pool of memory
++ * for use as IBs (all asics).
++ */
++void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
++{
++	if (adev->ib_pool_ready) {
++		amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
++		amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
++		adev->ib_pool_ready = false;
++	}
++}
++
++/**
++ * amdgpu_ib_ring_tests - test IBs on the rings
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Test an IB (Indirect Buffer) on each ring.
++ * If the test fails, disable the ring.
++ * Returns 0 on success, error if the primary GFX ring
++ * IB test fails.
++ */
++int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
++{
++	unsigned i;
++	int r;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		struct amdgpu_ring *ring = adev->rings[i];
++
++		if (!ring || !ring->ready)
++			continue;
++
++		r = amdgpu_ring_test_ib(ring);
++		if (r) {
++			ring->ready = false;
++			adev->needs_reset = false;
++
++			if (ring == &adev->gfx.gfx_ring[0]) {
++				/* oh, oh, that's really bad */
++				DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
++				adev->accel_working = false;
++				return r;
++
++			} else {
++				/* still not good, but we can live with it */
++				DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
++			}
++		}
++	}
++	return 0;
++}
++
++/*
++ * Debugfs info
++ */
++#if defined(CONFIG_DEBUG_FS)
++
++static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *) m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
++
++	return 0;
++
++}
++
++static struct drm_info_list amdgpu_debugfs_sa_list[] = {
++	{"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
++};
++
++#endif
++
++static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
++#else
++	return 0;
++#endif
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+new file mode 100644
+index 0000000..db5422e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+@@ -0,0 +1,216 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++
++/**
++ * amdgpu_ih_ring_alloc - allocate memory for the IH ring
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate a ring buffer for the interrupt controller.
++ * Returns 0 for success, errors for failure.
++ */
++static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
++{
++	int r;
++
++	/* Allocate ring buffer */
++	if (adev->irq.ih.ring_obj == NULL) {
++		r = amdgpu_bo_create(adev, adev->irq.ih.ring_size,
++				     PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_GTT, 0,
++				     NULL, &adev->irq.ih.ring_obj);
++		if (r) {
++			DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
++			return r;
++		}
++		r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
++		if (unlikely(r != 0))
++			return r;
++		r = amdgpu_bo_pin(adev->irq.ih.ring_obj,
++				  AMDGPU_GEM_DOMAIN_GTT,
++				  &adev->irq.ih.gpu_addr);
++		if (r) {
++			amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
++			DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r);
++			return r;
++		}
++		r = amdgpu_bo_kmap(adev->irq.ih.ring_obj,
++				   (void **)&adev->irq.ih.ring);
++		amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
++		if (r) {
++			DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r);
++			return r;
++		}
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_ih_ring_init - initialize the IH state
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initializes the IH state and allocates a buffer
++ * for the IH ring buffer.
++ * Returns 0 for success, errors for failure.
++ */
++int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
++			bool use_bus_addr)
++{
++	u32 rb_bufsz;
++	int r;
++
++	/* Align ring size */
++	rb_bufsz = order_base_2(ring_size / 4);
++	ring_size = (1 << rb_bufsz) * 4;
++	adev->irq.ih.ring_size = ring_size;
++	adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
++	adev->irq.ih.rptr = 0;
++	adev->irq.ih.use_bus_addr = use_bus_addr;
++
++	if (adev->irq.ih.use_bus_addr) {
++		if (!adev->irq.ih.ring) {
++			/* add 8 bytes for the rptr/wptr shadows and
++			 * add them to the end of the ring allocation.
++			 */
++			adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
++			if (adev->irq.ih.ring == NULL)
++				return -ENOMEM;
++			adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
++								  (void *)adev->irq.ih.ring,
++								  adev->irq.ih.ring_size,
++								  PCI_DMA_BIDIRECTIONAL);
++			if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) {
++				dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n");
++				kfree((void *)adev->irq.ih.ring);
++				return -ENOMEM;
++			}
++			adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
++			adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
++		}
++		return 0;
++	} else {
++		r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
++		if (r) {
++			dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
++			return r;
++		}
++
++		r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
++		if (r) {
++			amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
++			dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
++			return r;
++		}
++
++		return amdgpu_ih_ring_alloc(adev);
++	}
++}
++
++/**
++ * amdgpu_ih_ring_fini - tear down the IH state
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tears down the IH state and frees buffer
++ * used for the IH ring buffer.
++ */
++void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->irq.ih.use_bus_addr) {
++		if (adev->irq.ih.ring) {
++			/* add 8 bytes for the rptr/wptr shadows and
++			 * add them to the end of the ring allocation.
++			 */
++			pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr,
++					 adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL);
++			kfree((void *)adev->irq.ih.ring);
++			adev->irq.ih.ring = NULL;
++		}
++	} else {
++		if (adev->irq.ih.ring_obj) {
++			r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
++			if (likely(r == 0)) {
++				amdgpu_bo_kunmap(adev->irq.ih.ring_obj);
++				amdgpu_bo_unpin(adev->irq.ih.ring_obj);
++				amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
++			}
++			amdgpu_bo_unref(&adev->irq.ih.ring_obj);
++			adev->irq.ih.ring = NULL;
++			adev->irq.ih.ring_obj = NULL;
++		}
++		amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
++		amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
++	}
++}
++
++/**
++ * amdgpu_ih_process - interrupt handler
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Interrupt hander (VI), walk the IH ring.
++ * Returns irq process return code.
++ */
++int amdgpu_ih_process(struct amdgpu_device *adev)
++{
++	struct amdgpu_iv_entry entry;
++	u32 wptr;
++
++	if (!adev->irq.ih.enabled || adev->shutdown)
++		return IRQ_NONE;
++
++	wptr = amdgpu_ih_get_wptr(adev);
++
++restart_ih:
++	/* is somebody else already processing irqs? */
++	if (atomic_xchg(&adev->irq.ih.lock, 1))
++		return IRQ_NONE;
++
++	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
++
++	/* Order reading of wptr vs. reading of IH ring data */
++	rmb();
++
++	while (adev->irq.ih.rptr != wptr) {
++		amdgpu_ih_decode_iv(adev, &entry);
++		adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
++
++		amdgpu_irq_dispatch(adev, &entry);
++	}
++	amdgpu_ih_set_rptr(adev);
++	atomic_set(&adev->irq.ih.lock, 0);
++
++	/* make sure wptr hasn't changed while processing */
++	wptr = amdgpu_ih_get_wptr(adev);
++	if (wptr != adev->irq.ih.rptr)
++		goto restart_ih;
++
++	return IRQ_HANDLED;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+new file mode 100644
+index 0000000..c62b09e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+@@ -0,0 +1,62 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_IH_H__
++#define __AMDGPU_IH_H__
++
++struct amdgpu_device;
++
++/*
++ * R6xx+ IH ring
++ */
++struct amdgpu_ih_ring {
++	struct amdgpu_bo	*ring_obj;
++	volatile uint32_t	*ring;
++	unsigned		rptr;
++	unsigned		ring_size;
++	uint64_t		gpu_addr;
++	uint32_t		ptr_mask;
++	atomic_t		lock;
++	bool                    enabled;
++	unsigned		wptr_offs;
++	unsigned		rptr_offs;
++	u32			doorbell_index;
++	bool			use_doorbell;
++	bool			use_bus_addr;
++	dma_addr_t		rb_dma_addr; /* only used when use_bus_addr = true */
++};
++
++struct amdgpu_iv_entry {
++	unsigned src_id;
++	unsigned src_data;
++	unsigned ring_id;
++	unsigned vm_id;
++	unsigned pas_id;
++};
++
++int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
++			bool use_bus_addr);
++void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
++int amdgpu_ih_process(struct amdgpu_device *adev);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c
+new file mode 100644
+index 0000000..2648291
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c
+@@ -0,0 +1,47 @@
++/**
++ * \file amdgpu_ioc32.c
++ *
++ * 32-bit ioctl compatibility routines for the AMDGPU DRM.
++ *
++ * \author Paul Mackerras <paulus@samba.org>
++ *
++ * Copyright (C) Paul Mackerras 2005
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
++ * IN THE SOFTWARE.
++ */
++#include <linux/compat.h>
++
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu_drv.h"
++
++long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
++{
++	unsigned int nr = DRM_IOCTL_NR(cmd);
++	int ret;
++
++	if (nr < DRM_COMMAND_BASE)
++		return drm_compat_ioctl(filp, cmd, arg);
++
++	ret = amdgpu_drm_ioctl(filp, cmd, arg);
++
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+new file mode 100644
+index 0000000..2187960
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -0,0 +1,456 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++#include "atom.h"
++#include "amdgpu_connectors.h"
++
++#include <linux/pm_runtime.h>
++
++#define AMDGPU_WAIT_IDLE_TIMEOUT 200
++
++/*
++ * Handle hotplug events outside the interrupt handler proper.
++ */
++/**
++ * amdgpu_hotplug_work_func - display hotplug work handler
++ *
++ * @work: work struct
++ *
++ * This is the hot plug event work handler (all asics).
++ * The work gets scheduled from the irq handler if there
++ * was a hot plug interrupt.  It walks the connector table
++ * and calls the hotplug handler for each one, then sends
++ * a drm hotplug event to alert userspace.
++ */
++static void amdgpu_hotplug_work_func(struct work_struct *work)
++{
++	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
++						  hotplug_work);
++	struct drm_device *dev = adev->ddev;
++	struct drm_mode_config *mode_config = &dev->mode_config;
++	struct drm_connector *connector;
++
++	if (mode_config->num_connector) {
++		list_for_each_entry(connector, &mode_config->connector_list, head)
++			amdgpu_connector_hotplug(connector);
++	}
++	/* Just fire off a uevent and let userspace tell us what to do */
++	drm_helper_hpd_irq_event(dev);
++}
++
++/**
++ * amdgpu_irq_reset_work_func - execute gpu reset
++ *
++ * @work: work struct
++ *
++ * Execute scheduled gpu reset (cayman+).
++ * This function is called when the irq handler
++ * thinks we need a gpu reset.
++ */
++static void amdgpu_irq_reset_work_func(struct work_struct *work)
++{
++	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
++						  reset_work);
++
++	amdgpu_gpu_reset(adev);
++}
++
++/* Disable *all* interrupts */
++static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
++{
++	unsigned long irqflags;
++	unsigned i, j;
++	int r;
++
++	spin_lock_irqsave(&adev->irq.lock, irqflags);
++	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
++		struct amdgpu_irq_src *src = adev->irq.sources[i];
++
++		if (!src || !src->funcs->set || !src->num_types)
++			continue;
++
++		for (j = 0; j < src->num_types; ++j) {
++			atomic_set(&src->enabled_types[j], 0);
++			r = src->funcs->set(adev, src, j,
++					    AMDGPU_IRQ_STATE_DISABLE);
++			if (r)
++				DRM_ERROR("error disabling interrupt (%d)\n",
++					  r);
++		}
++	}
++	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
++}
++
++/**
++ * amdgpu_irq_preinstall - drm irq preinstall callback
++ *
++ * @dev: drm dev pointer
++ *
++ * Gets the hw ready to enable irqs (all asics).
++ * This function disables all interrupt sources on the GPU.
++ */
++void amdgpu_irq_preinstall(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	/* Disable *all* interrupts */
++	amdgpu_irq_disable_all(adev);
++	/* Clear bits */
++	amdgpu_ih_process(adev);
++}
++
++/**
++ * amdgpu_irq_postinstall - drm irq preinstall callback
++ *
++ * @dev: drm dev pointer
++ *
++ * Handles stuff to be done after enabling irqs (all asics).
++ * Returns 0 on success.
++ */
++int amdgpu_irq_postinstall(struct drm_device *dev)
++{
++	dev->max_vblank_count = 0x001fffff;
++	return 0;
++}
++
++/**
++ * amdgpu_irq_uninstall - drm irq uninstall callback
++ *
++ * @dev: drm dev pointer
++ *
++ * This function disables all interrupt sources on the GPU (all asics).
++ */
++void amdgpu_irq_uninstall(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (adev == NULL) {
++		return;
++	}
++	amdgpu_irq_disable_all(adev);
++}
++
++/**
++ * amdgpu_irq_handler - irq handler
++ *
++ * @int irq, void *arg: args
++ *
++ * This is the irq handler for the amdgpu driver (all asics).
++ */
++irqreturn_t amdgpu_irq_handler(int irq, void *arg)
++{
++	struct drm_device *dev = (struct drm_device *) arg;
++	struct amdgpu_device *adev = dev->dev_private;
++	irqreturn_t ret;
++
++	ret = amdgpu_ih_process(adev);
++	if (ret == IRQ_HANDLED)
++		pm_runtime_mark_last_busy(dev->dev);
++	return ret;
++}
++
++/**
++ * amdgpu_msi_ok - asic specific msi checks
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Handles asic specific MSI checks to determine if
++ * MSIs should be enabled on a particular chip (all asics).
++ * Returns true if MSIs should be enabled, false if MSIs
++ * should not be enabled.
++ */
++static bool amdgpu_msi_ok(struct amdgpu_device *adev)
++{
++	/* force MSI on */
++	if (amdgpu_msi == 1)
++		return true;
++	else if (amdgpu_msi == 0)
++		return false;
++
++	return true;
++}
++
++/**
++ * amdgpu_irq_init - init driver interrupt info
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
++ * Returns 0 for success, error for failure.
++ */
++int amdgpu_irq_init(struct amdgpu_device *adev)
++{
++	int r = 0;
++
++	spin_lock_init(&adev->irq.lock);
++	r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
++	if (r) {
++		return r;
++	}
++	/* enable msi */
++	adev->irq.msi_enabled = false;
++
++	if (amdgpu_msi_ok(adev)) {
++		int ret = pci_enable_msi(adev->pdev);
++		if (!ret) {
++			adev->irq.msi_enabled = true;
++			dev_info(adev->dev, "amdgpu: using MSI.\n");
++		}
++	}
++
++	INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
++	INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
++
++	adev->irq.installed = true;
++	r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
++	if (r) {
++		adev->irq.installed = false;
++		flush_work(&adev->hotplug_work);
++		return r;
++	}
++
++	DRM_INFO("amdgpu: irq initialized.\n");
++	return 0;
++}
++
++/**
++ * amdgpu_irq_fini - tear down driver interrupt info
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
++ */
++void amdgpu_irq_fini(struct amdgpu_device *adev)
++{
++	unsigned i;
++
++	drm_vblank_cleanup(adev->ddev);
++	if (adev->irq.installed) {
++		drm_irq_uninstall(adev->ddev);
++		adev->irq.installed = false;
++		if (adev->irq.msi_enabled)
++			pci_disable_msi(adev->pdev);
++		flush_work(&adev->hotplug_work);
++	}
++
++	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
++		struct amdgpu_irq_src *src = adev->irq.sources[i];
++
++		if (!src)
++			continue;
++
++		kfree(src->enabled_types);
++		src->enabled_types = NULL;
++	}
++}
++
++/**
++ * amdgpu_irq_add_id - register irq source
++ *
++ * @adev: amdgpu device pointer
++ * @src_id: source id for this source
++ * @source: irq source
++ *
++ */
++int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
++		      struct amdgpu_irq_src *source)
++{
++	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
++		return -EINVAL;
++
++	if (adev->irq.sources[src_id] != NULL)
++		return -EINVAL;
++
++	if (!source->funcs)
++		return -EINVAL;
++
++	if (source->num_types && !source->enabled_types) {
++		atomic_t *types;
++
++		types = kcalloc(source->num_types, sizeof(atomic_t),
++				GFP_KERNEL);
++		if (!types)
++			return -ENOMEM;
++
++		source->enabled_types = types;
++	}
++
++	adev->irq.sources[src_id] = source;
++	return 0;
++}
++
++/**
++ * amdgpu_irq_dispatch - dispatch irq to IP blocks
++ *
++ * @adev: amdgpu device pointer
++ * @entry: interrupt vector
++ *
++ * Dispatches the irq to the different IP blocks
++ */
++void amdgpu_irq_dispatch(struct amdgpu_device *adev,
++			 struct amdgpu_iv_entry *entry)
++{
++	unsigned src_id = entry->src_id;
++	struct amdgpu_irq_src *src;
++	int r;
++
++	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
++		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
++		return;
++	}
++
++	src = adev->irq.sources[src_id];
++	if (!src) {
++		DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
++		return;
++	}
++
++	r = src->funcs->process(adev, src, entry);
++	if (r)
++		DRM_ERROR("error processing interrupt (%d)\n", r);
++}
++
++/**
++ * amdgpu_irq_update - update hw interrupt state
++ *
++ * @adev: amdgpu device pointer
++ * @src: interrupt src you want to enable
++ * @type: type of interrupt you want to update
++ *
++ * Updates the interrupt state for a specific src (all asics).
++ */
++int amdgpu_irq_update(struct amdgpu_device *adev,
++			     struct amdgpu_irq_src *src, unsigned type)
++{
++	unsigned long irqflags;
++	enum amdgpu_interrupt_state state;
++	int r;
++
++	spin_lock_irqsave(&adev->irq.lock, irqflags);
++
++	/* we need to determine after taking the lock, otherwise
++	   we might disable just enabled interrupts again */
++	if (amdgpu_irq_enabled(adev, src, type))
++		state = AMDGPU_IRQ_STATE_ENABLE;
++	else
++		state = AMDGPU_IRQ_STATE_DISABLE;
++
++	r = src->funcs->set(adev, src, type, state);
++	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
++	return r;
++}
++
++/**
++ * amdgpu_irq_get - enable interrupt
++ *
++ * @adev: amdgpu device pointer
++ * @src: interrupt src you want to enable
++ * @type: type of interrupt you want to enable
++ *
++ * Enables the interrupt type for a specific src (all asics).
++ */
++int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++		   unsigned type)
++{
++	if (!adev->ddev->irq_enabled)
++		return -ENOENT;
++
++	if (type >= src->num_types)
++		return -EINVAL;
++
++	if (!src->enabled_types || !src->funcs->set)
++		return -EINVAL;
++
++	if (atomic_inc_return(&src->enabled_types[type]) == 1)
++		return amdgpu_irq_update(adev, src, type);
++
++	return 0;
++}
++
++bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
++			struct amdgpu_irq_src *src,
++			unsigned type)
++{
++	if ((type >= src->num_types) || !src->enabled_types)
++		return false;
++	return atomic_inc_return(&src->enabled_types[type]) == 1;
++}
++
++/**
++ * amdgpu_irq_put - disable interrupt
++ *
++ * @adev: amdgpu device pointer
++ * @src: interrupt src you want to disable
++ * @type: type of interrupt you want to disable
++ *
++ * Disables the interrupt type for a specific src (all asics).
++ */
++int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++		   unsigned type)
++{
++	if (!adev->ddev->irq_enabled)
++		return -ENOENT;
++
++	if (type >= src->num_types)
++		return -EINVAL;
++
++	if (!src->enabled_types || !src->funcs->set)
++		return -EINVAL;
++
++	if (atomic_dec_and_test(&src->enabled_types[type]))
++		return amdgpu_irq_update(adev, src, type);
++
++	return 0;
++}
++
++/**
++ * amdgpu_irq_enabled - test if irq is enabled or not
++ *
++ * @adev: amdgpu device pointer
++ * @idx: interrupt src you want to test
++ *
++ * Tests if the given interrupt source is enabled or not
++ */
++bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++			unsigned type)
++{
++	if (!adev->ddev->irq_enabled)
++		return false;
++
++	if (type >= src->num_types)
++		return false;
++
++	if (!src->enabled_types || !src->funcs->set)
++		return false;
++
++	return !!atomic_read(&src->enabled_types[type]);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+new file mode 100644
+index 0000000..8299795
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+@@ -0,0 +1,92 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_IRQ_H__
++#define __AMDGPU_IRQ_H__
++
++#include "amdgpu_ih.h"
++
++#define AMDGPU_MAX_IRQ_SRC_ID	0x100
++
++struct amdgpu_device;
++struct amdgpu_iv_entry;
++
++enum amdgpu_interrupt_state {
++	AMDGPU_IRQ_STATE_DISABLE,
++	AMDGPU_IRQ_STATE_ENABLE,
++};
++
++struct amdgpu_irq_src {
++	unsigned				num_types;
++	atomic_t				*enabled_types;
++	const struct amdgpu_irq_src_funcs	*funcs;
++};
++
++/* provided by interrupt generating IP blocks */
++struct amdgpu_irq_src_funcs {
++	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
++		   unsigned type, enum amdgpu_interrupt_state state);
++
++	int (*process)(struct amdgpu_device *adev,
++		       struct amdgpu_irq_src *source,
++		       struct amdgpu_iv_entry *entry);
++};
++
++struct amdgpu_irq {
++	bool				installed;
++	spinlock_t			lock;
++	/* interrupt sources */
++	struct amdgpu_irq_src		*sources[AMDGPU_MAX_IRQ_SRC_ID];
++
++	/* status, etc. */
++	bool				msi_enabled; /* msi enabled */
++
++	/* interrupt ring */
++	struct amdgpu_ih_ring		ih;
++	const struct amdgpu_ih_funcs	*ih_funcs;
++};
++
++void amdgpu_irq_preinstall(struct drm_device *dev);
++int amdgpu_irq_postinstall(struct drm_device *dev);
++void amdgpu_irq_uninstall(struct drm_device *dev);
++irqreturn_t amdgpu_irq_handler(int irq, void *arg);
++
++int amdgpu_irq_init(struct amdgpu_device *adev);
++void amdgpu_irq_fini(struct amdgpu_device *adev);
++int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
++		      struct amdgpu_irq_src *source);
++void amdgpu_irq_dispatch(struct amdgpu_device *adev,
++			 struct amdgpu_iv_entry *entry);
++int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++		      unsigned type);
++int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++		   unsigned type);
++bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
++			    struct amdgpu_irq_src *src,
++			    unsigned type);
++int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++		   unsigned type);
++bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
++			unsigned type);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+new file mode 100644
+index 0000000..c271da3
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -0,0 +1,674 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include <drm/amdgpu_drm.h>
++#include "amdgpu_uvd.h"
++#include "amdgpu_vce.h"
++
++#include <linux/vga_switcheroo.h>
++#include <linux/slab.h>
++#include <linux/pm_runtime.h>
++
++#if defined(CONFIG_VGA_SWITCHEROO)
++bool amdgpu_has_atpx(void);
++#else
++static inline bool amdgpu_has_atpx(void) { return false; }
++#endif
++
++/**
++ * amdgpu_driver_unload_kms - Main unload function for KMS.
++ *
++ * @dev: drm dev pointer
++ *
++ * This is the main unload function for KMS (all asics).
++ * Returns 0 on success.
++ */
++int amdgpu_driver_unload_kms(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (adev == NULL)
++		return 0;
++
++	if (adev->rmmio == NULL)
++		goto done_free;
++
++	pm_runtime_get_sync(dev->dev);
++
++	amdgpu_acpi_fini(adev);
++
++	amdgpu_device_fini(adev);
++
++done_free:
++	kfree(adev);
++	dev->dev_private = NULL;
++	return 0;
++}
++
++/**
++ * amdgpu_driver_load_kms - Main load function for KMS.
++ *
++ * @dev: drm dev pointer
++ * @flags: device flags
++ *
++ * This is the main load function for KMS (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
++{
++	struct amdgpu_device *adev;
++	int r, acpi_status;
++
++	adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
++	if (adev == NULL) {
++		return -ENOMEM;
++	}
++	dev->dev_private = (void *)adev;
++
++	if ((amdgpu_runtime_pm != 0) &&
++	    amdgpu_has_atpx() &&
++	    ((flags & AMDGPU_IS_APU) == 0))
++		flags |= AMDGPU_IS_PX;
++
++	/* amdgpu_device_init should report only fatal error
++	 * like memory allocation failure or iomapping failure,
++	 * or memory manager initialization failure, it must
++	 * properly initialize the GPU MC controller and permit
++	 * VRAM allocation
++	 */
++	r = amdgpu_device_init(adev, dev, dev->pdev, flags);
++	if (r) {
++		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
++		goto out;
++	}
++
++	/* Call ACPI methods: require modeset init
++	 * but failure is not fatal
++	 */
++	if (!r) {
++		acpi_status = amdgpu_acpi_init(adev);
++		if (acpi_status)
++		dev_dbg(&dev->pdev->dev,
++				"Error during ACPI methods call\n");
++	}
++
++	if (amdgpu_device_is_px(dev)) {
++		pm_runtime_use_autosuspend(dev->dev);
++		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
++		pm_runtime_set_active(dev->dev);
++		pm_runtime_allow(dev->dev);
++		pm_runtime_mark_last_busy(dev->dev);
++		pm_runtime_put_autosuspend(dev->dev);
++	}
++
++out:
++	if (r)
++		amdgpu_driver_unload_kms(dev);
++
++
++	return r;
++}
++
++/*
++ * Userspace get information ioctl
++ */
++/**
++ * amdgpu_info_ioctl - answer a device specific request.
++ *
++ * @adev: amdgpu device pointer
++ * @data: request object
++ * @filp: drm filp
++ *
++ * This function is used to pass device specific parameters to the userspace
++ * drivers.  Examples include: pci device id, pipeline parms, tiling params,
++ * etc. (all asics).
++ * Returns 0 on success, -EINVAL on failure.
++ */
++static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_amdgpu_info *info = data;
++	struct amdgpu_mode_info *minfo = &adev->mode_info;
++	void __user *out = (void __user *)(long)info->return_pointer;
++	uint32_t size = info->return_size;
++	struct drm_crtc *crtc;
++	uint32_t ui32 = 0;
++	uint64_t ui64 = 0;
++	int i, found;
++
++	if (!info->return_size || !info->return_pointer)
++		return -EINVAL;
++
++	switch (info->query) {
++	case AMDGPU_INFO_ACCEL_WORKING:
++		ui32 = adev->accel_working;
++		return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_CRTC_FROM_ID:
++		for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
++			crtc = (struct drm_crtc *)minfo->crtcs[i];
++			if (crtc && crtc->base.id == info->mode_crtc.id) {
++				struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++				ui32 = amdgpu_crtc->crtc_id;
++				found = 1;
++				break;
++			}
++		}
++		if (!found) {
++			DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
++			return -EINVAL;
++		}
++		return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_HW_IP_INFO: {
++		struct drm_amdgpu_info_hw_ip ip = {};
++		enum amdgpu_ip_block_type type;
++		uint32_t ring_mask = 0;
++
++		if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
++			return -EINVAL;
++
++		switch (info->query_hw_ip.type) {
++		case AMDGPU_HW_IP_GFX:
++			type = AMDGPU_IP_BLOCK_TYPE_GFX;
++			for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++				ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
++			break;
++		case AMDGPU_HW_IP_COMPUTE:
++			type = AMDGPU_IP_BLOCK_TYPE_GFX;
++			for (i = 0; i < adev->gfx.num_compute_rings; i++)
++				ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
++			break;
++		case AMDGPU_HW_IP_DMA:
++			type = AMDGPU_IP_BLOCK_TYPE_SDMA;
++			ring_mask = adev->sdma[0].ring.ready ? 1 : 0;
++			ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1);
++			break;
++		case AMDGPU_HW_IP_UVD:
++			type = AMDGPU_IP_BLOCK_TYPE_UVD;
++			ring_mask = adev->uvd.ring.ready ? 1 : 0;
++			break;
++		case AMDGPU_HW_IP_VCE:
++			type = AMDGPU_IP_BLOCK_TYPE_VCE;
++			for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
++				ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		for (i = 0; i < adev->num_ip_blocks; i++) {
++			if (adev->ip_blocks[i].type == type &&
++			    adev->ip_block_enabled[i]) {
++				ip.hw_ip_version_major = adev->ip_blocks[i].major;
++				ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
++				ip.capabilities_flags = 0;
++				ip.available_rings = ring_mask;
++				break;
++			}
++		}
++		return copy_to_user(out, &ip,
++				    min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
++	}
++	case AMDGPU_INFO_HW_IP_COUNT: {
++		enum amdgpu_ip_block_type type;
++		uint32_t count = 0;
++
++		switch (info->query_hw_ip.type) {
++		case AMDGPU_HW_IP_GFX:
++			type = AMDGPU_IP_BLOCK_TYPE_GFX;
++			break;
++		case AMDGPU_HW_IP_COMPUTE:
++			type = AMDGPU_IP_BLOCK_TYPE_GFX;
++			break;
++		case AMDGPU_HW_IP_DMA:
++			type = AMDGPU_IP_BLOCK_TYPE_SDMA;
++			break;
++		case AMDGPU_HW_IP_UVD:
++			type = AMDGPU_IP_BLOCK_TYPE_UVD;
++			break;
++		case AMDGPU_HW_IP_VCE:
++			type = AMDGPU_IP_BLOCK_TYPE_VCE;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		for (i = 0; i < adev->num_ip_blocks; i++)
++			if (adev->ip_blocks[i].type == type &&
++			    adev->ip_block_enabled[i] &&
++			    count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
++				count++;
++
++		return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
++	}
++	case AMDGPU_INFO_TIMESTAMP:
++		ui64 = amdgpu_asic_get_gpu_clock_counter(adev);
++		return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_FW_VERSION: {
++		struct drm_amdgpu_info_firmware fw_info;
++
++		/* We only support one instance of each IP block right now. */
++		if (info->query_fw.ip_instance != 0)
++			return -EINVAL;
++
++		switch (info->query_fw.fw_type) {
++		case AMDGPU_INFO_FW_VCE:
++			fw_info.ver = adev->vce.fw_version;
++			fw_info.feature = adev->vce.fb_version;
++			break;
++		case AMDGPU_INFO_FW_UVD:
++			fw_info.ver = 0;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_GMC:
++			fw_info.ver = adev->mc.fw_version;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_GFX_ME:
++			fw_info.ver = adev->gfx.me_fw_version;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_GFX_PFP:
++			fw_info.ver = adev->gfx.pfp_fw_version;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_GFX_CE:
++			fw_info.ver = adev->gfx.ce_fw_version;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_GFX_RLC:
++			fw_info.ver = adev->gfx.rlc_fw_version;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_GFX_MEC:
++			if (info->query_fw.index == 0)
++				fw_info.ver = adev->gfx.mec_fw_version;
++			else if (info->query_fw.index == 1)
++				fw_info.ver = adev->gfx.mec2_fw_version;
++			else
++				return -EINVAL;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_SMC:
++			fw_info.ver = adev->pm.fw_version;
++			fw_info.feature = 0;
++			break;
++		case AMDGPU_INFO_FW_SDMA:
++			if (info->query_fw.index >= 2)
++				return -EINVAL;
++			fw_info.ver = adev->sdma[info->query_fw.index].fw_version;
++			fw_info.feature = 0;
++			break;
++		default:
++			return -EINVAL;
++		}
++		return copy_to_user(out, &fw_info,
++				    min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
++	}
++	case AMDGPU_INFO_NUM_BYTES_MOVED:
++		ui64 = atomic64_read(&adev->num_bytes_moved);
++		return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_VRAM_USAGE:
++		ui64 = atomic64_read(&adev->vram_usage);
++		return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_VIS_VRAM_USAGE:
++		ui64 = atomic64_read(&adev->vram_vis_usage);
++		return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_GTT_USAGE:
++		ui64 = atomic64_read(&adev->gtt_usage);
++		return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
++	case AMDGPU_INFO_GDS_CONFIG: {
++		struct drm_amdgpu_info_gds gds_info;
++
++		gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
++		gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
++		gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
++		gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
++		gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
++		gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
++		gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
++		return copy_to_user(out, &gds_info,
++				    min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
++	}
++	case AMDGPU_INFO_VRAM_GTT: {
++		struct drm_amdgpu_info_vram_gtt vram_gtt;
++
++		vram_gtt.vram_size = adev->mc.real_vram_size;
++		vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
++		vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
++		vram_gtt.gtt_size  = adev->mc.gtt_size;
++		vram_gtt.gtt_size -= adev->gart_pin_size;
++		return copy_to_user(out, &vram_gtt,
++				    min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
++	}
++	case AMDGPU_INFO_READ_MMR_REG: {
++		unsigned n, alloc_size = info->read_mmr_reg.count * 4;
++		uint32_t *regs;
++		unsigned se_num = (info->read_mmr_reg.instance >>
++				   AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
++				  AMDGPU_INFO_MMR_SE_INDEX_MASK;
++		unsigned sh_num = (info->read_mmr_reg.instance >>
++				   AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
++				  AMDGPU_INFO_MMR_SH_INDEX_MASK;
++
++		/* set full masks if the userspace set all bits
++		 * in the bitfields */
++		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
++			se_num = 0xffffffff;
++		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
++			sh_num = 0xffffffff;
++
++		regs = kmalloc(alloc_size, GFP_KERNEL);
++		if (!regs)
++			return -ENOMEM;
++
++		for (i = 0; i < info->read_mmr_reg.count; i++)
++			if (amdgpu_asic_read_register(adev, se_num, sh_num,
++						      info->read_mmr_reg.dword_offset + i,
++						      &regs[i])) {
++				DRM_DEBUG_KMS("unallowed offset %#x\n",
++					      info->read_mmr_reg.dword_offset + i);
++				kfree(regs);
++				return -EFAULT;
++			}
++		n = copy_to_user(out, regs, min(size, alloc_size));
++		kfree(regs);
++		return n ? -EFAULT : 0;
++	}
++	case AMDGPU_INFO_DEV_INFO: {
++		struct drm_amdgpu_info_device dev_info;
++		struct amdgpu_cu_info cu_info;
++
++		dev_info.device_id = dev->pdev->device;
++		dev_info.chip_rev = adev->rev_id;
++		dev_info.external_rev = adev->external_rev_id;
++		dev_info.pci_rev = dev->pdev->revision;
++		dev_info.family = adev->family;
++		dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
++		dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
++		/* return all clocks in KHz */
++		dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
++		if (adev->pm.dpm_enabled)
++			dev_info.max_engine_clock =
++				adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
++		else
++			dev_info.max_engine_clock = adev->pm.default_sclk * 10;
++		dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
++		dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
++					adev->gfx.config.max_shader_engines;
++		dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
++		dev_info._pad = 0;
++		dev_info.ids_flags = 0;
++		if (adev->flags & AMDGPU_IS_APU)
++			dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
++		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
++		dev_info.virtual_address_alignment = max(PAGE_SIZE, 0x10000UL);
++		dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
++					     AMDGPU_GPU_PAGE_SIZE;
++		dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
++
++		amdgpu_asic_get_cu_info(adev, &cu_info);
++		dev_info.cu_active_number = cu_info.number;
++		dev_info.cu_ao_mask = cu_info.ao_cu_mask;
++		memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
++
++		return copy_to_user(out, &dev_info,
++				    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
++	}
++	default:
++		DRM_DEBUG_KMS("Invalid request %d\n", info->query);
++		return -EINVAL;
++	}
++	return 0;
++}
++
++
++/*
++ * Outdated mess for old drm with Xorg being in charge (void function now).
++ */
++/**
++ * amdgpu_driver_firstopen_kms - drm callback for last close
++ *
++ * @dev: drm dev pointer
++ *
++ * Switch vga switcheroo state after last close (all asics).
++ */
++void amdgpu_driver_lastclose_kms(struct drm_device *dev)
++{
++	vga_switcheroo_process_delayed_switch();
++}
++
++/**
++ * amdgpu_driver_open_kms - drm callback for open
++ *
++ * @dev: drm dev pointer
++ * @file_priv: drm file
++ *
++ * On device open, init vm on cayman+ (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_fpriv *fpriv;
++	int r;
++
++	file_priv->driver_priv = NULL;
++
++	r = pm_runtime_get_sync(dev->dev);
++	if (r < 0)
++		return r;
++
++	fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
++	if (unlikely(!fpriv))
++		return -ENOMEM;
++
++	r = amdgpu_vm_init(adev, &fpriv->vm);
++	if (r)
++		goto error_free;
++
++	mutex_init(&fpriv->bo_list_lock);
++	idr_init(&fpriv->bo_list_handles);
++
++	/* init context manager */
++	mutex_init(&fpriv->ctx_mgr.hlock);
++	idr_init(&fpriv->ctx_mgr.ctx_handles);
++	fpriv->ctx_mgr.adev = adev;
++
++	file_priv->driver_priv = fpriv;
++
++	pm_runtime_mark_last_busy(dev->dev);
++	pm_runtime_put_autosuspend(dev->dev);
++	return 0;
++
++error_free:
++	kfree(fpriv);
++
++	return r;
++}
++
++/**
++ * amdgpu_driver_postclose_kms - drm callback for post close
++ *
++ * @dev: drm dev pointer
++ * @file_priv: drm file
++ *
++ * On device post close, tear down vm on cayman+ (all asics).
++ */
++void amdgpu_driver_postclose_kms(struct drm_device *dev,
++				 struct drm_file *file_priv)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
++	struct amdgpu_bo_list *list;
++	int handle;
++
++	if (!fpriv)
++		return;
++
++	amdgpu_vm_fini(adev, &fpriv->vm);
++
++	idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
++		amdgpu_bo_list_free(list);
++
++	idr_destroy(&fpriv->bo_list_handles);
++	mutex_destroy(&fpriv->bo_list_lock);
++
++	/* release context */
++	amdgpu_ctx_fini(fpriv);
++
++	kfree(fpriv);
++	file_priv->driver_priv = NULL;
++}
++
++/**
++ * amdgpu_driver_preclose_kms - drm callback for pre close
++ *
++ * @dev: drm dev pointer
++ * @file_priv: drm file
++ *
++ * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
++ * (all asics).
++ */
++void amdgpu_driver_preclose_kms(struct drm_device *dev,
++				struct drm_file *file_priv)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	amdgpu_uvd_free_handles(adev, file_priv);
++	amdgpu_vce_free_handles(adev, file_priv);
++}
++
++/*
++ * VBlank related functions.
++ */
++/**
++ * amdgpu_get_vblank_counter_kms - get frame count
++ *
++ * @dev: drm dev pointer
++ * @crtc: crtc to get the frame count from
++ *
++ * Gets the frame count on the requested crtc (all asics).
++ * Returns frame count on success, -EINVAL on failure.
++ */
++u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
++		DRM_ERROR("Invalid crtc %d\n", crtc);
++		return -EINVAL;
++	}
++
++	return amdgpu_display_vblank_get_counter(adev, crtc);
++}
++
++/**
++ * amdgpu_enable_vblank_kms - enable vblank interrupt
++ *
++ * @dev: drm dev pointer
++ * @crtc: crtc to enable vblank interrupt for
++ *
++ * Enable the interrupt on the requested crtc (all asics).
++ * Returns 0 on success, -EINVAL on failure.
++ */
++int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc);
++
++	return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
++}
++
++/**
++ * amdgpu_disable_vblank_kms - disable vblank interrupt
++ *
++ * @dev: drm dev pointer
++ * @crtc: crtc to disable vblank interrupt for
++ *
++ * Disable the interrupt on the requested crtc (all asics).
++ */
++void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc);
++
++	amdgpu_irq_put(adev, &adev->crtc_irq, idx);
++}
++
++/**
++ * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
++ *
++ * @dev: drm dev pointer
++ * @crtc: crtc to get the timestamp for
++ * @max_error: max error
++ * @vblank_time: time value
++ * @flags: flags passed to the driver
++ *
++ * Gets the timestamp on the requested crtc based on the
++ * scanout position.  (all asics).
++ * Returns postive status flags on success, negative error on failure.
++ */
++int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
++				    int *max_error,
++				    struct timeval *vblank_time,
++				    unsigned flags)
++{
++	struct drm_crtc *drmcrtc;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (crtc < 0 || crtc >= dev->num_crtcs) {
++		DRM_ERROR("Invalid crtc %d\n", crtc);
++		return -EINVAL;
++	}
++
++	/* Get associated drm_crtc: */
++	drmcrtc = &adev->mode_info.crtcs[crtc]->base;
++
++	/* Helper routine in DRM core does all the work: */
++	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
++						     vblank_time, flags,
++						     drmcrtc, &drmcrtc->hwmode);
++}
++
++const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	/* KMS */
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
++};
++int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+new file mode 100644
+index 0000000..e944291
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+@@ -0,0 +1,319 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <linux/module.h>
++#include <linux/mmu_notifier.h>
++#include <drm/drmP.h>
++#include <drm/drm.h>
++
++#include "amdgpu.h"
++
++struct amdgpu_mn {
++	/* constant after initialisation */
++	struct amdgpu_device	*adev;
++	struct mm_struct	*mm;
++	struct mmu_notifier	mn;
++
++	/* only used on destruction */
++	struct work_struct	work;
++
++	/* protected by adev->mn_lock */
++	struct hlist_node	node;
++
++	/* objects protected by lock */
++	struct mutex		lock;
++	struct rb_root		objects;
++};
++
++struct amdgpu_mn_node {
++	struct interval_tree_node	it;
++	struct list_head		bos;
++};
++
++/**
++ * amdgpu_mn_destroy - destroy the rmn
++ *
++ * @work: previously sheduled work item
++ *
++ * Lazy destroys the notifier from a work item
++ */
++static void amdgpu_mn_destroy(struct work_struct *work)
++{
++	struct amdgpu_mn *rmn = container_of(work, struct amdgpu_mn, work);
++	struct amdgpu_device *adev = rmn->adev;
++	struct amdgpu_mn_node *node, *next_node;
++	struct amdgpu_bo *bo, *next_bo;
++
++	mutex_lock(&adev->mn_lock);
++	mutex_lock(&rmn->lock);
++	hash_del(&rmn->node);
++	rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects,
++					     it.rb) {
++
++		interval_tree_remove(&node->it, &rmn->objects);
++		list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
++			bo->mn = NULL;
++			list_del_init(&bo->mn_list);
++		}
++		kfree(node);
++	}
++	mutex_unlock(&rmn->lock);
++	mutex_unlock(&adev->mn_lock);
++	mmu_notifier_unregister(&rmn->mn, rmn->mm);
++	kfree(rmn);
++}
++
++/**
++ * amdgpu_mn_release - callback to notify about mm destruction
++ *
++ * @mn: our notifier
++ * @mn: the mm this callback is about
++ *
++ * Shedule a work item to lazy destroy our notifier.
++ */
++static void amdgpu_mn_release(struct mmu_notifier *mn,
++			      struct mm_struct *mm)
++{
++	struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
++	INIT_WORK(&rmn->work, amdgpu_mn_destroy);
++	schedule_work(&rmn->work);
++}
++
++/**
++ * amdgpu_mn_invalidate_range_start - callback to notify about mm change
++ *
++ * @mn: our notifier
++ * @mn: the mm this callback is about
++ * @start: start of updated range
++ * @end: end of updated range
++ *
++ * We block for all BOs between start and end to be idle and
++ * unmap them by move them into system domain again.
++ */
++static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
++					     struct mm_struct *mm,
++					     unsigned long start,
++					     unsigned long end)
++{
++	struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
++	struct interval_tree_node *it;
++
++	/* notification is exclusive, but interval is inclusive */
++	end -= 1;
++
++	mutex_lock(&rmn->lock);
++
++	it = interval_tree_iter_first(&rmn->objects, start, end);
++	while (it) {
++		struct amdgpu_mn_node *node;
++		struct amdgpu_bo *bo;
++		int r;
++
++		node = container_of(it, struct amdgpu_mn_node, it);
++		it = interval_tree_iter_next(it, start, end);
++
++		list_for_each_entry(bo, &node->bos, mn_list) {
++
++			r = amdgpu_bo_reserve(bo, true);
++			if (r) {
++				DRM_ERROR("(%d) failed to reserve user bo\n", r);
++				continue;
++			}
++
++			r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
++				true, false, MAX_SCHEDULE_TIMEOUT);
++			if (r)
++				DRM_ERROR("(%d) failed to wait for user bo\n", r);
++
++			amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
++			r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
++			if (r)
++				DRM_ERROR("(%d) failed to validate user bo\n", r);
++
++			amdgpu_bo_unreserve(bo);
++		}
++	}
++
++	mutex_unlock(&rmn->lock);
++}
++
++static const struct mmu_notifier_ops amdgpu_mn_ops = {
++	.release = amdgpu_mn_release,
++	.invalidate_range_start = amdgpu_mn_invalidate_range_start,
++};
++
++/**
++ * amdgpu_mn_get - create notifier context
++ *
++ * @adev: amdgpu device pointer
++ *
++ * Creates a notifier context for current->mm.
++ */
++static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
++{
++	struct mm_struct *mm = current->mm;
++	struct amdgpu_mn *rmn;
++	int r;
++
++	down_write(&mm->mmap_sem);
++	mutex_lock(&adev->mn_lock);
++
++	hash_for_each_possible(adev->mn_hash, rmn, node, (unsigned long)mm)
++		if (rmn->mm == mm)
++			goto release_locks;
++
++	rmn = kzalloc(sizeof(*rmn), GFP_KERNEL);
++	if (!rmn) {
++		rmn = ERR_PTR(-ENOMEM);
++		goto release_locks;
++	}
++
++	rmn->adev = adev;
++	rmn->mm = mm;
++	rmn->mn.ops = &amdgpu_mn_ops;
++	mutex_init(&rmn->lock);
++	rmn->objects = RB_ROOT;
++
++	r = __mmu_notifier_register(&rmn->mn, mm);
++	if (r)
++		goto free_rmn;
++
++	hash_add(adev->mn_hash, &rmn->node, (unsigned long)mm);
++
++release_locks:
++	mutex_unlock(&adev->mn_lock);
++	up_write(&mm->mmap_sem);
++
++	return rmn;
++
++free_rmn:
++	mutex_unlock(&adev->mn_lock);
++	up_write(&mm->mmap_sem);
++	kfree(rmn);
++
++	return ERR_PTR(r);
++}
++
++/**
++ * amdgpu_mn_register - register a BO for notifier updates
++ *
++ * @bo: amdgpu buffer object
++ * @addr: userptr addr we should monitor
++ *
++ * Registers an MMU notifier for the given BO at the specified address.
++ * Returns 0 on success, -ERRNO if anything goes wrong.
++ */
++int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
++{
++	unsigned long end = addr + amdgpu_bo_size(bo) - 1;
++	struct amdgpu_device *adev = bo->adev;
++	struct amdgpu_mn *rmn;
++	struct amdgpu_mn_node *node = NULL;
++	struct list_head bos;
++	struct interval_tree_node *it;
++
++	rmn = amdgpu_mn_get(adev);
++	if (IS_ERR(rmn))
++		return PTR_ERR(rmn);
++
++	INIT_LIST_HEAD(&bos);
++
++	mutex_lock(&rmn->lock);
++
++	while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
++		kfree(node);
++		node = container_of(it, struct amdgpu_mn_node, it);
++		interval_tree_remove(&node->it, &rmn->objects);
++		addr = min(it->start, addr);
++		end = max(it->last, end);
++		list_splice(&node->bos, &bos);
++	}
++
++	if (!node) {
++		node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
++		if (!node) {
++			mutex_unlock(&rmn->lock);
++			return -ENOMEM;
++		}
++	}
++
++	bo->mn = rmn;
++
++	node->it.start = addr;
++	node->it.last = end;
++	INIT_LIST_HEAD(&node->bos);
++	list_splice(&bos, &node->bos);
++	list_add(&bo->mn_list, &node->bos);
++
++	interval_tree_insert(&node->it, &rmn->objects);
++
++	mutex_unlock(&rmn->lock);
++
++	return 0;
++}
++
++/**
++ * amdgpu_mn_unregister - unregister a BO for notifier updates
++ *
++ * @bo: amdgpu buffer object
++ *
++ * Remove any registration of MMU notifier updates from the buffer object.
++ */
++void amdgpu_mn_unregister(struct amdgpu_bo *bo)
++{
++	struct amdgpu_device *adev = bo->adev;
++	struct amdgpu_mn *rmn;
++	struct list_head *head;
++
++	mutex_lock(&adev->mn_lock);
++	rmn = bo->mn;
++	if (rmn == NULL) {
++		mutex_unlock(&adev->mn_lock);
++		return;
++	}
++
++	mutex_lock(&rmn->lock);
++	/* save the next list entry for later */
++	head = bo->mn_list.next;
++
++	bo->mn = NULL;
++	list_del(&bo->mn_list);
++
++	if (list_empty(head)) {
++		struct amdgpu_mn_node *node;
++		node = container_of(head, struct amdgpu_mn_node, bos);
++		interval_tree_remove(&node->it, &rmn->objects);
++		kfree(node);
++	}
++
++	mutex_unlock(&rmn->lock);
++	mutex_unlock(&adev->mn_lock);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+new file mode 100644
+index 0000000..64efe5b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+@@ -0,0 +1,586 @@
++/*
++ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
++ *                VA Linux Systems Inc., Fremont, California.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Original Authors:
++ *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
++ *
++ * Kernel port Author: Dave Airlie
++ */
++
++#ifndef AMDGPU_MODE_H
++#define AMDGPU_MODE_H
++
++#include <drm/drm_crtc.h>
++#include <drm/drm_edid.h>
++#include <drm/drm_dp_helper.h>
++#include <drm/drm_fixed.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_plane_helper.h>
++#include <linux/i2c.h>
++#include <linux/i2c-algo-bit.h>
++
++struct amdgpu_bo;
++struct amdgpu_device;
++struct amdgpu_encoder;
++struct amdgpu_router;
++struct amdgpu_hpd;
++
++#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
++#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
++#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
++#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
++
++#define AMDGPU_MAX_HPD_PINS 6
++#define AMDGPU_MAX_CRTCS 6
++#define AMDGPU_MAX_AFMT_BLOCKS 7
++
++enum amdgpu_rmx_type {
++	RMX_OFF,
++	RMX_FULL,
++	RMX_CENTER,
++	RMX_ASPECT
++};
++
++enum amdgpu_underscan_type {
++	UNDERSCAN_OFF,
++	UNDERSCAN_ON,
++	UNDERSCAN_AUTO,
++};
++
++#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
++#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
++
++enum amdgpu_hpd_id {
++	AMDGPU_HPD_1 = 0,
++	AMDGPU_HPD_2,
++	AMDGPU_HPD_3,
++	AMDGPU_HPD_4,
++	AMDGPU_HPD_5,
++	AMDGPU_HPD_6,
++	AMDGPU_HPD_LAST,
++	AMDGPU_HPD_NONE = 0xff,
++};
++
++enum amdgpu_crtc_irq {
++	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
++	AMDGPU_CRTC_IRQ_VBLANK2,
++	AMDGPU_CRTC_IRQ_VBLANK3,
++	AMDGPU_CRTC_IRQ_VBLANK4,
++	AMDGPU_CRTC_IRQ_VBLANK5,
++	AMDGPU_CRTC_IRQ_VBLANK6,
++	AMDGPU_CRTC_IRQ_VLINE1,
++	AMDGPU_CRTC_IRQ_VLINE2,
++	AMDGPU_CRTC_IRQ_VLINE3,
++	AMDGPU_CRTC_IRQ_VLINE4,
++	AMDGPU_CRTC_IRQ_VLINE5,
++	AMDGPU_CRTC_IRQ_VLINE6,
++	AMDGPU_CRTC_IRQ_LAST,
++	AMDGPU_CRTC_IRQ_NONE = 0xff
++};
++
++enum amdgpu_pageflip_irq {
++	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
++	AMDGPU_PAGEFLIP_IRQ_D2,
++	AMDGPU_PAGEFLIP_IRQ_D3,
++	AMDGPU_PAGEFLIP_IRQ_D4,
++	AMDGPU_PAGEFLIP_IRQ_D5,
++	AMDGPU_PAGEFLIP_IRQ_D6,
++	AMDGPU_PAGEFLIP_IRQ_LAST,
++	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
++};
++
++enum amdgpu_flip_status {
++	AMDGPU_FLIP_NONE,
++	AMDGPU_FLIP_PENDING,
++	AMDGPU_FLIP_SUBMITTED
++};
++
++#define AMDGPU_MAX_I2C_BUS 16
++
++/* amdgpu gpio-based i2c
++ * 1. "mask" reg and bits
++ *    grabs the gpio pins for software use
++ *    0=not held  1=held
++ * 2. "a" reg and bits
++ *    output pin value
++ *    0=low 1=high
++ * 3. "en" reg and bits
++ *    sets the pin direction
++ *    0=input 1=output
++ * 4. "y" reg and bits
++ *    input pin value
++ *    0=low 1=high
++ */
++struct amdgpu_i2c_bus_rec {
++	bool valid;
++	/* id used by atom */
++	uint8_t i2c_id;
++	/* id used by atom */
++	enum amdgpu_hpd_id hpd;
++	/* can be used with hw i2c engine */
++	bool hw_capable;
++	/* uses multi-media i2c engine */
++	bool mm_i2c;
++	/* regs and bits */
++	uint32_t mask_clk_reg;
++	uint32_t mask_data_reg;
++	uint32_t a_clk_reg;
++	uint32_t a_data_reg;
++	uint32_t en_clk_reg;
++	uint32_t en_data_reg;
++	uint32_t y_clk_reg;
++	uint32_t y_data_reg;
++	uint32_t mask_clk_mask;
++	uint32_t mask_data_mask;
++	uint32_t a_clk_mask;
++	uint32_t a_data_mask;
++	uint32_t en_clk_mask;
++	uint32_t en_data_mask;
++	uint32_t y_clk_mask;
++	uint32_t y_data_mask;
++};
++
++#define AMDGPU_MAX_BIOS_CONNECTOR 16
++
++/* pll flags */
++#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
++#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
++#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
++#define AMDGPU_PLL_LEGACY               (1 << 3)
++#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
++#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
++#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
++#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
++#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
++#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
++#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
++#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
++#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
++#define AMDGPU_PLL_IS_LCD               (1 << 13)
++#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
++
++struct amdgpu_pll {
++	/* reference frequency */
++	uint32_t reference_freq;
++
++	/* fixed dividers */
++	uint32_t reference_div;
++	uint32_t post_div;
++
++	/* pll in/out limits */
++	uint32_t pll_in_min;
++	uint32_t pll_in_max;
++	uint32_t pll_out_min;
++	uint32_t pll_out_max;
++	uint32_t lcd_pll_out_min;
++	uint32_t lcd_pll_out_max;
++	uint32_t best_vco;
++
++	/* divider limits */
++	uint32_t min_ref_div;
++	uint32_t max_ref_div;
++	uint32_t min_post_div;
++	uint32_t max_post_div;
++	uint32_t min_feedback_div;
++	uint32_t max_feedback_div;
++	uint32_t min_frac_feedback_div;
++	uint32_t max_frac_feedback_div;
++
++	/* flags for the current clock */
++	uint32_t flags;
++
++	/* pll id */
++	uint32_t id;
++};
++
++struct amdgpu_i2c_chan {
++	struct i2c_adapter adapter;
++	struct drm_device *dev;
++	struct i2c_algo_bit_data bit;
++	struct amdgpu_i2c_bus_rec rec;
++	struct drm_dp_aux aux;
++	bool has_aux;
++	struct mutex mutex;
++};
++
++struct amdgpu_fbdev;
++
++struct amdgpu_afmt {
++	bool enabled;
++	int offset;
++	bool last_buffer_filled_status;
++	int id;
++	struct amdgpu_audio_pin *pin;
++};
++
++/*
++ * Audio
++ */
++struct amdgpu_audio_pin {
++	int			channels;
++	int			rate;
++	int			bits_per_sample;
++	u8			status_bits;
++	u8			category_code;
++	u32			offset;
++	bool			connected;
++	u32			id;
++};
++
++struct amdgpu_audio {
++	bool enabled;
++	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
++	int num_pins;
++};
++
++struct amdgpu_mode_mc_save {
++	u32 vga_render_control;
++	u32 vga_hdp_control;
++	bool crtc_enabled[AMDGPU_MAX_CRTCS];
++};
++
++struct amdgpu_display_funcs {
++	/* vga render */
++	void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
++	/* display watermarks */
++	void (*bandwidth_update)(struct amdgpu_device *adev);
++	/* get frame count */
++	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
++	/* wait for vblank */
++	void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
++	/* is dce hung */
++	bool (*is_display_hung)(struct amdgpu_device *adev);
++	/* set backlight level */
++	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
++				    u8 level);
++	/* get backlight level */
++	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
++	/* hotplug detect */
++	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
++	void (*hpd_set_polarity)(struct amdgpu_device *adev,
++				 enum amdgpu_hpd_id hpd);
++	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
++	/* pageflipping */
++	void (*page_flip)(struct amdgpu_device *adev,
++			 int crtc_id, u64 crtc_base);
++	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
++					u32 *vbl, u32 *position);
++	/* display topology setup */
++	void (*add_encoder)(struct amdgpu_device *adev,
++			    uint32_t encoder_enum,
++			    uint32_t supported_device,
++			    u16 caps);
++	void (*add_connector)(struct amdgpu_device *adev,
++			      uint32_t connector_id,
++			      uint32_t supported_device,
++			      int connector_type,
++			      struct amdgpu_i2c_bus_rec *i2c_bus,
++			      uint16_t connector_object_id,
++			      struct amdgpu_hpd *hpd,
++			      struct amdgpu_router *router);
++	void (*stop_mc_access)(struct amdgpu_device *adev,
++			       struct amdgpu_mode_mc_save *save);
++	void (*resume_mc_access)(struct amdgpu_device *adev,
++				 struct amdgpu_mode_mc_save *save);
++};
++
++struct amdgpu_mode_info {
++	struct atom_context *atom_context;
++	struct card_info *atom_card_info;
++	bool mode_config_initialized;
++	struct amdgpu_crtc *crtcs[6];
++	struct amdgpu_afmt *afmt[7];
++	/* DVI-I properties */
++	struct drm_property *coherent_mode_property;
++	/* DAC enable load detect */
++	struct drm_property *load_detect_property;
++	/* underscan */
++	struct drm_property *underscan_property;
++	struct drm_property *underscan_hborder_property;
++	struct drm_property *underscan_vborder_property;
++	/* audio */
++	struct drm_property *audio_property;
++	/* FMT dithering */
++	struct drm_property *dither_property;
++	/* hardcoded DFP edid from BIOS */
++	struct edid *bios_hardcoded_edid;
++	int bios_hardcoded_edid_size;
++
++	/* pointer to fbdev info structure */
++	struct amdgpu_fbdev *rfbdev;
++	/* firmware flags */
++	u16 firmware_flags;
++	/* pointer to backlight encoder */
++	struct amdgpu_encoder *bl_encoder;
++	struct amdgpu_audio	audio; /* audio stuff */
++	int			num_crtc; /* number of crtcs */
++	int			num_hpd; /* number of hpd pins */
++	int			num_dig; /* number of dig blocks */
++	int			disp_priority;
++	const struct amdgpu_display_funcs *funcs;
++};
++
++#define AMDGPU_MAX_BL_LEVEL 0xFF
++
++#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
++
++struct amdgpu_backlight_privdata {
++	struct amdgpu_encoder *encoder;
++	uint8_t negative;
++};
++
++#endif
++
++struct amdgpu_atom_ss {
++	uint16_t percentage;
++	uint16_t percentage_divider;
++	uint8_t type;
++	uint16_t step;
++	uint8_t delay;
++	uint8_t range;
++	uint8_t refdiv;
++	/* asic_ss */
++	uint16_t rate;
++	uint16_t amount;
++};
++
++struct amdgpu_crtc {
++	struct drm_crtc base;
++	int crtc_id;
++	u16 lut_r[256], lut_g[256], lut_b[256];
++	bool enabled;
++	bool can_tile;
++	uint32_t crtc_offset;
++	struct drm_gem_object *cursor_bo;
++	uint64_t cursor_addr;
++	int cursor_width;
++	int cursor_height;
++	int max_cursor_width;
++	int max_cursor_height;
++	enum amdgpu_rmx_type rmx_type;
++	u8 h_border;
++	u8 v_border;
++	fixed20_12 vsc;
++	fixed20_12 hsc;
++	struct drm_display_mode native_mode;
++	u32 pll_id;
++	/* page flipping */
++	struct workqueue_struct *pflip_queue;
++	struct amdgpu_flip_work *pflip_works;
++	enum amdgpu_flip_status pflip_status;
++	int deferred_flip_completion;
++	/* pll sharing */
++	struct amdgpu_atom_ss ss;
++	bool ss_enabled;
++	u32 adjusted_clock;
++	int bpc;
++	u32 pll_reference_div;
++	u32 pll_post_div;
++	u32 pll_flags;
++	struct drm_encoder *encoder;
++	struct drm_connector *connector;
++	/* for dpm */
++	u32 line_time;
++	u32 wm_low;
++	u32 wm_high;
++	struct drm_display_mode hw_mode;
++};
++
++struct amdgpu_encoder_atom_dig {
++	bool linkb;
++	/* atom dig */
++	bool coherent_mode;
++	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
++	/* atom lvds/edp */
++	uint32_t lcd_misc;
++	uint16_t panel_pwr_delay;
++	uint32_t lcd_ss_id;
++	/* panel mode */
++	struct drm_display_mode native_mode;
++	struct backlight_device *bl_dev;
++	int dpms_mode;
++	uint8_t backlight_level;
++	int panel_mode;
++	struct amdgpu_afmt *afmt;
++};
++
++struct amdgpu_encoder {
++	struct drm_encoder base;
++	uint32_t encoder_enum;
++	uint32_t encoder_id;
++	uint32_t devices;
++	uint32_t active_device;
++	uint32_t flags;
++	uint32_t pixel_clock;
++	enum amdgpu_rmx_type rmx_type;
++	enum amdgpu_underscan_type underscan_type;
++	uint32_t underscan_hborder;
++	uint32_t underscan_vborder;
++	struct drm_display_mode native_mode;
++	void *enc_priv;
++	int audio_polling_active;
++	bool is_ext_encoder;
++	u16 caps;
++};
++
++struct amdgpu_connector_atom_dig {
++	/* displayport */
++	u8 dpcd[DP_RECEIVER_CAP_SIZE];
++	u8 dp_sink_type;
++	int dp_clock;
++	int dp_lane_count;
++	bool edp_on;
++};
++
++struct amdgpu_gpio_rec {
++	bool valid;
++	u8 id;
++	u32 reg;
++	u32 mask;
++	u32 shift;
++};
++
++struct amdgpu_hpd {
++	enum amdgpu_hpd_id hpd;
++	u8 plugged_state;
++	struct amdgpu_gpio_rec gpio;
++};
++
++struct amdgpu_router {
++	u32 router_id;
++	struct amdgpu_i2c_bus_rec i2c_info;
++	u8 i2c_addr;
++	/* i2c mux */
++	bool ddc_valid;
++	u8 ddc_mux_type;
++	u8 ddc_mux_control_pin;
++	u8 ddc_mux_state;
++	/* clock/data mux */
++	bool cd_valid;
++	u8 cd_mux_type;
++	u8 cd_mux_control_pin;
++	u8 cd_mux_state;
++};
++
++enum amdgpu_connector_audio {
++	AMDGPU_AUDIO_DISABLE = 0,
++	AMDGPU_AUDIO_ENABLE = 1,
++	AMDGPU_AUDIO_AUTO = 2
++};
++
++enum amdgpu_connector_dither {
++	AMDGPU_FMT_DITHER_DISABLE = 0,
++	AMDGPU_FMT_DITHER_ENABLE = 1,
++};
++
++struct amdgpu_connector {
++	struct drm_connector base;
++	uint32_t connector_id;
++	uint32_t devices;
++	struct amdgpu_i2c_chan *ddc_bus;
++	/* some systems have an hdmi and vga port with a shared ddc line */
++	bool shared_ddc;
++	bool use_digital;
++	/* we need to mind the EDID between detect
++	   and get modes due to analog/digital/tvencoder */
++	struct edid *edid;
++	void *con_priv;
++	bool dac_load_detect;
++	bool detected_by_load; /* if the connection status was determined by load */
++	uint16_t connector_object_id;
++	struct amdgpu_hpd hpd;
++	struct amdgpu_router router;
++	struct amdgpu_i2c_chan *router_bus;
++	enum amdgpu_connector_audio audio;
++	enum amdgpu_connector_dither dither;
++	unsigned pixelclock_for_modeset;
++};
++
++struct amdgpu_framebuffer {
++	struct drm_framebuffer base;
++	struct drm_gem_object *obj;
++};
++
++#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
++				((em) == ATOM_ENCODER_MODE_DP_MST))
++
++void amdgpu_link_encoder_connector(struct drm_device *dev);
++
++struct drm_connector *
++amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
++struct drm_connector *
++amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
++bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
++				    u32 pixel_clock);
++
++u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
++struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
++
++bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
++
++void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
++
++int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
++				      unsigned int flags,
++				      int *vpos, int *hpos, ktime_t *stime,
++				      ktime_t *etime);
++
++int amdgpu_framebuffer_init(struct drm_device *dev,
++			     struct amdgpu_framebuffer *rfb,
++			     struct drm_mode_fb_cmd2 *mode_cmd,
++			     struct drm_gem_object *obj);
++
++int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
++
++void amdgpu_enc_destroy(struct drm_encoder *encoder);
++void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
++bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
++					const struct drm_display_mode *mode,
++					struct drm_display_mode *adjusted_mode);
++void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
++			     struct drm_display_mode *adjusted_mode);
++int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
++
++/* fbdev layer */
++int amdgpu_fbdev_init(struct amdgpu_device *adev);
++void amdgpu_fbdev_fini(struct amdgpu_device *adev);
++void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
++int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
++bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
++
++void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
++
++
++int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
++
++/* amdgpu_display.c */
++void amdgpu_print_display_setup(struct drm_device *dev);
++int amdgpu_modeset_create_props(struct amdgpu_device *adev);
++int amdgpu_crtc_set_config(struct drm_mode_set *set);
++int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
++			  struct drm_framebuffer *fb,
++			  struct drm_pending_vblank_event *event,
++			  uint32_t page_flip_flags);
++extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+new file mode 100644
+index 0000000..b515827
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -0,0 +1,646 @@
++/*
++ * Copyright 2009 Jerome Glisse.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Jerome Glisse <glisse@freedesktop.org>
++ *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
++ *    Dave Airlie
++ */
++#include <linux/list.h>
++#include <linux/slab.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_trace.h"
++
++
++int amdgpu_ttm_init(struct amdgpu_device *adev);
++void amdgpu_ttm_fini(struct amdgpu_device *adev);
++
++static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
++						struct ttm_mem_reg * mem)
++{
++	u64 ret = 0;
++	if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
++		ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
++			   adev->mc.visible_vram_size ?
++			   adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT):
++			   mem->size;
++	}
++	return ret;
++}
++
++static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
++		       struct ttm_mem_reg *old_mem,
++		       struct ttm_mem_reg *new_mem)
++{
++	u64 vis_size;
++	if (!adev)
++		return;
++
++	if (new_mem) {
++		switch (new_mem->mem_type) {
++		case TTM_PL_TT:
++			atomic64_add(new_mem->size, &adev->gtt_usage);
++			break;
++		case TTM_PL_VRAM:
++			atomic64_add(new_mem->size, &adev->vram_usage);
++			vis_size = amdgpu_get_vis_part_size(adev, new_mem);
++			atomic64_add(vis_size, &adev->vram_vis_usage);
++			break;
++		}
++	}
++
++	if (old_mem) {
++		switch (old_mem->mem_type) {
++		case TTM_PL_TT:
++			atomic64_sub(old_mem->size, &adev->gtt_usage);
++			break;
++		case TTM_PL_VRAM:
++			atomic64_sub(old_mem->size, &adev->vram_usage);
++			vis_size = amdgpu_get_vis_part_size(adev, old_mem);
++			atomic64_sub(vis_size, &adev->vram_vis_usage);
++			break;
++		}
++	}
++}
++
++static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
++{
++	struct amdgpu_bo *bo;
++
++	bo = container_of(tbo, struct amdgpu_bo, tbo);
++
++	amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
++	amdgpu_mn_unregister(bo);
++
++	mutex_lock(&bo->adev->gem.mutex);
++	list_del_init(&bo->list);
++	mutex_unlock(&bo->adev->gem.mutex);
++	drm_gem_object_release(&bo->gem_base);
++	kfree(bo->metadata);
++	kfree(bo);
++}
++
++bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
++{
++	if (bo->destroy == &amdgpu_ttm_bo_destroy)
++		return true;
++	return false;
++}
++
++void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
++{
++	u32 c = 0, i;
++	rbo->placement.placement = rbo->placements;
++	rbo->placement.busy_placement = rbo->placements;
++
++	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
++		if (rbo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
++			rbo->adev->mc.visible_vram_size < rbo->adev->mc.real_vram_size) {
++			rbo->placements[c].fpfn =
++				rbo->adev->mc.visible_vram_size >> PAGE_SHIFT;
++			rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
++										 TTM_PL_FLAG_VRAM;
++		}
++		rbo->placements[c].fpfn = 0;
++		rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
++									 TTM_PL_FLAG_VRAM;
++	}
++
++	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
++		if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) {
++			rbo->placements[c].fpfn = 0;
++			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT;
++		} else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) {
++			rbo->placements[c].fpfn = 0;
++			rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
++										 TTM_PL_FLAG_UNCACHED;
++		} else {
++			rbo->placements[c].fpfn = 0;
++			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
++		}
++	}
++
++	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
++		if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) {
++			rbo->placements[c].fpfn = 0;
++			rbo->placements[c++].flags =  TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM;
++		} else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) {
++			rbo->placements[c].fpfn = 0;
++			rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
++										 TTM_PL_FLAG_UNCACHED;
++		} else {
++			rbo->placements[c].fpfn = 0;
++			rbo->placements[c++].flags =  TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
++		}
++	}
++
++	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
++		rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
++					AMDGPU_PL_FLAG_GDS;
++	}
++	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
++		rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
++					AMDGPU_PL_FLAG_GWS;
++	}
++	if (domain & AMDGPU_GEM_DOMAIN_OA) {
++		rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
++					AMDGPU_PL_FLAG_OA;
++	}
++
++	if (!c) {
++		rbo->placements[c].fpfn = 0;
++		rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
++					TTM_PL_FLAG_SYSTEM;
++	}
++	rbo->placement.num_placement = c;
++	rbo->placement.num_busy_placement = c;
++
++	for (i = 0; i < c; i++) {
++		if ((rbo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
++			(rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
++			!rbo->placements[i].fpfn)
++			rbo->placements[i].lpfn =
++				rbo->adev->mc.visible_vram_size >> PAGE_SHIFT;
++		else
++			rbo->placements[i].lpfn = 0;
++	}
++
++	if (rbo->tbo.mem.size > 512 * 1024) {
++		for (i = 0; i < c; i++) {
++			rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
++		}
++	}
++}
++
++int amdgpu_bo_create(struct amdgpu_device *adev,
++		     unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags,
++		     struct sg_table *sg, struct amdgpu_bo **bo_ptr)
++{
++	struct amdgpu_bo *bo;
++	enum ttm_bo_type type;
++	unsigned long page_align;
++	size_t acc_size;
++	int r;
++
++	/* VI has a hw bug where VM PTEs have to be allocated in groups of 8.
++	 * do this as a temporary workaround
++	 */
++	if (!(domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
++		if (adev->asic_type >= CHIP_TOPAZ) {
++			if (byte_align & 0x7fff)
++				byte_align = ALIGN(byte_align, 0x8000);
++			if (size & 0x7fff)
++				size = ALIGN(size, 0x8000);
++		}
++	}
++
++	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
++	size = ALIGN(size, PAGE_SIZE);
++
++	if (kernel) {
++		type = ttm_bo_type_kernel;
++	} else if (sg) {
++		type = ttm_bo_type_sg;
++	} else {
++		type = ttm_bo_type_device;
++	}
++	*bo_ptr = NULL;
++
++	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
++				       sizeof(struct amdgpu_bo));
++
++	bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
++	if (bo == NULL)
++		return -ENOMEM;
++	r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
++	if (unlikely(r)) {
++		kfree(bo);
++		return r;
++	}
++	bo->adev = adev;
++	INIT_LIST_HEAD(&bo->list);
++	INIT_LIST_HEAD(&bo->va);
++	bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM |
++				       AMDGPU_GEM_DOMAIN_GTT |
++				       AMDGPU_GEM_DOMAIN_CPU |
++				       AMDGPU_GEM_DOMAIN_GDS |
++				       AMDGPU_GEM_DOMAIN_GWS |
++				       AMDGPU_GEM_DOMAIN_OA);
++
++	bo->flags = flags;
++	amdgpu_ttm_placement_from_domain(bo, domain);
++	/* Kernel allocation are uninterruptible */
++	down_read(&adev->pm.mclk_lock);
++	r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
++			&bo->placement, page_align, !kernel, NULL,
++			acc_size, sg, NULL, &amdgpu_ttm_bo_destroy);
++	up_read(&adev->pm.mclk_lock);
++	if (unlikely(r != 0)) {
++		return r;
++	}
++	*bo_ptr = bo;
++
++	trace_amdgpu_bo_create(bo);
++
++	return 0;
++}
++
++int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
++{
++	bool is_iomem;
++	int r;
++
++	if (bo->kptr) {
++		if (ptr) {
++			*ptr = bo->kptr;
++		}
++		return 0;
++	}
++	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
++	if (r) {
++		return r;
++	}
++	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
++	if (ptr) {
++		*ptr = bo->kptr;
++	}
++	return 0;
++}
++
++void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
++{
++	if (bo->kptr == NULL)
++		return;
++	bo->kptr = NULL;
++	ttm_bo_kunmap(&bo->kmap);
++}
++
++struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
++{
++	if (bo == NULL)
++		return NULL;
++
++	ttm_bo_reference(&bo->tbo);
++	return bo;
++}
++
++void amdgpu_bo_unref(struct amdgpu_bo **bo)
++{
++	struct ttm_buffer_object *tbo;
++
++	if ((*bo) == NULL)
++		return;
++
++	tbo = &((*bo)->tbo);
++	ttm_bo_unref(&tbo);
++	if (tbo == NULL)
++		*bo = NULL;
++}
++
++int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset,
++			     u64 *gpu_addr)
++{
++	int r, i;
++
++	if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm))
++		return -EPERM;
++
++	if (bo->pin_count) {
++		bo->pin_count++;
++		if (gpu_addr)
++			*gpu_addr = amdgpu_bo_gpu_offset(bo);
++
++		if (max_offset != 0) {
++			u64 domain_start;
++
++			if (domain == AMDGPU_GEM_DOMAIN_VRAM)
++				domain_start = bo->adev->mc.vram_start;
++			else
++				domain_start = bo->adev->mc.gtt_start;
++			WARN_ON_ONCE(max_offset <
++				     (amdgpu_bo_gpu_offset(bo) - domain_start));
++		}
++
++		return 0;
++	}
++	amdgpu_ttm_placement_from_domain(bo, domain);
++	for (i = 0; i < bo->placement.num_placement; i++) {
++		/* force to pin into visible video ram */
++		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
++			!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
++			(!max_offset || max_offset > bo->adev->mc.visible_vram_size))
++			bo->placements[i].lpfn =
++				bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
++		else
++			bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
++
++		bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
++	}
++
++	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
++	if (likely(r == 0)) {
++		bo->pin_count = 1;
++		if (gpu_addr != NULL)
++			*gpu_addr = amdgpu_bo_gpu_offset(bo);
++		if (domain == AMDGPU_GEM_DOMAIN_VRAM)
++			bo->adev->vram_pin_size += amdgpu_bo_size(bo);
++		else
++			bo->adev->gart_pin_size += amdgpu_bo_size(bo);
++	} else {
++		dev_err(bo->adev->dev, "%p pin failed\n", bo);
++	}
++	return r;
++}
++
++int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
++{
++	return amdgpu_bo_pin_restricted(bo, domain, 0, gpu_addr);
++}
++
++int amdgpu_bo_unpin(struct amdgpu_bo *bo)
++{
++	int r, i;
++
++	if (!bo->pin_count) {
++		dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
++		return 0;
++	}
++	bo->pin_count--;
++	if (bo->pin_count)
++		return 0;
++	for (i = 0; i < bo->placement.num_placement; i++) {
++		bo->placements[i].lpfn = 0;
++		bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
++	}
++	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
++	if (likely(r == 0)) {
++		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
++			bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
++		else
++			bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
++	} else {
++		dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
++	}
++	return r;
++}
++
++int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
++{
++	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
++	if (0 && (adev->flags & AMDGPU_IS_APU)) {
++		/* Useless to evict on IGP chips */
++		return 0;
++	}
++	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
++}
++
++void amdgpu_bo_force_delete(struct amdgpu_device *adev)
++{
++	struct amdgpu_bo *bo, *n;
++
++	if (list_empty(&adev->gem.objects)) {
++		return;
++	}
++	dev_err(adev->dev, "Userspace still has active objects !\n");
++	list_for_each_entry_safe(bo, n, &adev->gem.objects, list) {
++		mutex_lock(&adev->ddev->struct_mutex);
++		dev_err(adev->dev, "%p %p %lu %lu force free\n",
++			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
++			*((unsigned long *)&bo->gem_base.refcount));
++		mutex_lock(&bo->adev->gem.mutex);
++		list_del_init(&bo->list);
++		mutex_unlock(&bo->adev->gem.mutex);
++		/* this should unref the ttm bo */
++		drm_gem_object_unreference(&bo->gem_base);
++		mutex_unlock(&adev->ddev->struct_mutex);
++	}
++}
++
++int amdgpu_bo_init(struct amdgpu_device *adev)
++{
++	/* Add an MTRR for the VRAM */
++	adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
++					      adev->mc.aper_size);
++	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
++		adev->mc.mc_vram_size >> 20,
++		(unsigned long long)adev->mc.aper_size >> 20);
++	DRM_INFO("RAM width %dbits DDR\n",
++			adev->mc.vram_width);
++	return amdgpu_ttm_init(adev);
++}
++
++void amdgpu_bo_fini(struct amdgpu_device *adev)
++{
++	amdgpu_ttm_fini(adev);
++	arch_phys_wc_del(adev->mc.vram_mtrr);
++}
++
++int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
++			     struct vm_area_struct *vma)
++{
++	return ttm_fbdev_mmap(vma, &bo->tbo);
++}
++
++int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
++{
++	unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
++
++	bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK;
++	bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK;
++	mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
++	tilesplit = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK;
++	stilesplit = (tiling_flags >> AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK;
++	switch (bankw) {
++	case 0:
++	case 1:
++	case 2:
++	case 4:
++	case 8:
++		break;
++	default:
++		return -EINVAL;
++	}
++	switch (bankh) {
++	case 0:
++	case 1:
++	case 2:
++	case 4:
++	case 8:
++		break;
++	default:
++		return -EINVAL;
++	}
++	switch (mtaspect) {
++	case 0:
++	case 1:
++	case 2:
++	case 4:
++	case 8:
++		break;
++	default:
++		return -EINVAL;
++	}
++	if (tilesplit > 6) {
++		return -EINVAL;
++	}
++	if (stilesplit > 6) {
++		return -EINVAL;
++	}
++
++	bo->tiling_flags = tiling_flags;
++	return 0;
++}
++
++void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
++{
++	lockdep_assert_held(&bo->tbo.resv->lock.base);
++
++	if (tiling_flags)
++		*tiling_flags = bo->tiling_flags;
++}
++
++int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
++			    uint32_t metadata_size, uint64_t flags)
++{
++	void *buffer;
++
++	if (!metadata_size) {
++		if (bo->metadata_size) {
++			kfree(bo->metadata);
++			bo->metadata_size = 0;
++		}
++		return 0;
++	}
++
++	if (metadata == NULL)
++		return -EINVAL;
++
++	buffer = kzalloc(metadata_size, GFP_KERNEL);
++	if (buffer == NULL)
++		return -ENOMEM;
++
++	memcpy(buffer, metadata, metadata_size);
++
++	kfree(bo->metadata);
++	bo->metadata_flags = flags;
++	bo->metadata = buffer;
++	bo->metadata_size = metadata_size;
++
++	return 0;
++}
++
++int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
++			   size_t buffer_size, uint32_t *metadata_size,
++			   uint64_t *flags)
++{
++	if (!buffer && !metadata_size)
++		return -EINVAL;
++
++	if (buffer) {
++		if (buffer_size < bo->metadata_size)
++			return -EINVAL;
++
++		if (bo->metadata_size)
++			memcpy(buffer, bo->metadata, bo->metadata_size);
++	}
++
++	if (metadata_size)
++		*metadata_size = bo->metadata_size;
++	if (flags)
++		*flags = bo->metadata_flags;
++
++	return 0;
++}
++
++void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
++			   struct ttm_mem_reg *new_mem)
++{
++	struct amdgpu_bo *rbo;
++
++	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
++		return;
++
++	rbo = container_of(bo, struct amdgpu_bo, tbo);
++	amdgpu_vm_bo_invalidate(rbo->adev, rbo);
++
++	/* update statistics */
++	if (!new_mem)
++		return;
++
++	/* move_notify is called before move happens */
++	amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
++}
++
++int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
++{
++	struct amdgpu_device *adev;
++	struct amdgpu_bo *rbo;
++	unsigned long offset, size;
++	int r;
++
++	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
++		return 0;
++	rbo = container_of(bo, struct amdgpu_bo, tbo);
++	adev = rbo->adev;
++	if (bo->mem.mem_type == TTM_PL_VRAM) {
++		size = bo->mem.num_pages << PAGE_SHIFT;
++		offset = bo->mem.start << PAGE_SHIFT;
++		if ((offset + size) > adev->mc.visible_vram_size) {
++			/* hurrah the memory is not visible ! */
++			amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_VRAM);
++			rbo->placements[0].lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
++			r = ttm_bo_validate(bo, &rbo->placement, false, false);
++			if (unlikely(r != 0))
++				return r;
++			offset = bo->mem.start << PAGE_SHIFT;
++			/* this should not happen */
++			if ((offset + size) > adev->mc.visible_vram_size)
++				return -EINVAL;
++		}
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_bo_fence - add fence to buffer object
++ *
++ * @bo: buffer object in question
++ * @fence: fence to add
++ * @shared: true if fence should be added shared
++ *
++ */
++void amdgpu_bo_fence(struct amdgpu_bo *bo, struct amdgpu_fence *fence,
++		     bool shared)
++{
++	struct reservation_object *resv = bo->tbo.resv;
++
++	if (shared)
++		reservation_object_add_shared_fence(resv, &fence->base);
++	else
++		reservation_object_add_excl_fence(resv, &fence->base);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+new file mode 100644
+index 0000000..b1e0a03
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+@@ -0,0 +1,196 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#ifndef __AMDGPU_OBJECT_H__
++#define __AMDGPU_OBJECT_H__
++
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++/**
++ * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
++ * @mem_type:	ttm memory type
++ *
++ * Returns corresponding domain of the ttm mem_type
++ */
++static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
++{
++	switch (mem_type) {
++	case TTM_PL_VRAM:
++		return AMDGPU_GEM_DOMAIN_VRAM;
++	case TTM_PL_TT:
++		return AMDGPU_GEM_DOMAIN_GTT;
++	case TTM_PL_SYSTEM:
++		return AMDGPU_GEM_DOMAIN_CPU;
++	case AMDGPU_PL_GDS:
++		return AMDGPU_GEM_DOMAIN_GDS;
++	case AMDGPU_PL_GWS:
++		return AMDGPU_GEM_DOMAIN_GWS;
++	case AMDGPU_PL_OA:
++		return AMDGPU_GEM_DOMAIN_OA;
++	default:
++		break;
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_bo_reserve - reserve bo
++ * @bo:		bo structure
++ * @no_intr:	don't return -ERESTARTSYS on pending signal
++ *
++ * Returns:
++ * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
++ * a signal. Release all buffer reservations and return to user-space.
++ */
++static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
++{
++	int r;
++
++	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
++	if (unlikely(r != 0)) {
++		if (r != -ERESTARTSYS)
++			dev_err(bo->adev->dev, "%p reserve failed\n", bo);
++		return r;
++	}
++	return 0;
++}
++
++static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
++{
++	ttm_bo_unreserve(&bo->tbo);
++}
++
++/**
++ * amdgpu_bo_gpu_offset - return GPU offset of bo
++ * @bo:	amdgpu object for which we query the offset
++ *
++ * Returns current GPU offset of the object.
++ *
++ * Note: object should either be pinned or reserved when calling this
++ * function, it might be useful to add check for this for debugging.
++ */
++static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
++{
++	return bo->tbo.offset;
++}
++
++static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
++{
++	return bo->tbo.num_pages << PAGE_SHIFT;
++}
++
++static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
++{
++	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
++}
++
++static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
++{
++	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
++}
++
++/**
++ * amdgpu_bo_mmap_offset - return mmap offset of bo
++ * @bo:	amdgpu object for which we query the offset
++ *
++ * Returns mmap offset of the object.
++ */
++static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
++{
++	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
++}
++
++int amdgpu_bo_create(struct amdgpu_device *adev,
++			    unsigned long size, int byte_align,
++			    bool kernel, u32 domain, u64 flags,
++			    struct sg_table *sg,
++			    struct amdgpu_bo **bo_ptr);
++int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
++void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
++struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
++void amdgpu_bo_unref(struct amdgpu_bo **bo);
++int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
++int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
++				    u64 max_offset, u64 *gpu_addr);
++int amdgpu_bo_unpin(struct amdgpu_bo *bo);
++int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
++void amdgpu_bo_force_delete(struct amdgpu_device *adev);
++int amdgpu_bo_init(struct amdgpu_device *adev);
++void amdgpu_bo_fini(struct amdgpu_device *adev);
++int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
++				struct vm_area_struct *vma);
++int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
++void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
++int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
++			    uint32_t metadata_size, uint64_t flags);
++int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
++			   size_t buffer_size, uint32_t *metadata_size,
++			   uint64_t *flags);
++void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
++				  struct ttm_mem_reg *new_mem);
++int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
++void amdgpu_bo_fence(struct amdgpu_bo *bo, struct amdgpu_fence *fence,
++		     bool shared);
++
++/*
++ * sub allocation
++ */
++
++static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
++{
++	return sa_bo->manager->gpu_addr + sa_bo->soffset;
++}
++
++static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
++{
++	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
++}
++
++int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
++				     struct amdgpu_sa_manager *sa_manager,
++				     unsigned size, u32 align, u32 domain);
++void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
++				      struct amdgpu_sa_manager *sa_manager);
++int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
++				      struct amdgpu_sa_manager *sa_manager);
++int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
++					struct amdgpu_sa_manager *sa_manager);
++int amdgpu_sa_bo_new(struct amdgpu_device *adev,
++			    struct amdgpu_sa_manager *sa_manager,
++			    struct amdgpu_sa_bo **sa_bo,
++			    unsigned size, unsigned align);
++void amdgpu_sa_bo_free(struct amdgpu_device *adev,
++			      struct amdgpu_sa_bo **sa_bo,
++			      struct amdgpu_fence *fence);
++#if defined(CONFIG_DEBUG_FS)
++void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
++					 struct seq_file *m);
++#endif
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
+new file mode 100644
+index 0000000..d153149
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
+@@ -0,0 +1,350 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "atom.h"
++#include "atombios_encoders.h"
++#include <asm/div64.h>
++#include <linux/gcd.h>
++
++/**
++ * amdgpu_pll_reduce_ratio - fractional number reduction
++ *
++ * @nom: nominator
++ * @den: denominator
++ * @nom_min: minimum value for nominator
++ * @den_min: minimum value for denominator
++ *
++ * Find the greatest common divisor and apply it on both nominator and
++ * denominator, but make nominator and denominator are at least as large
++ * as their minimum values.
++ */
++static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den,
++				    unsigned nom_min, unsigned den_min)
++{
++	unsigned tmp;
++
++	/* reduce the numbers to a simpler ratio */
++	tmp = gcd(*nom, *den);
++	*nom /= tmp;
++	*den /= tmp;
++
++	/* make sure nominator is large enough */
++	if (*nom < nom_min) {
++		tmp = DIV_ROUND_UP(nom_min, *nom);
++		*nom *= tmp;
++		*den *= tmp;
++	}
++
++	/* make sure the denominator is large enough */
++	if (*den < den_min) {
++		tmp = DIV_ROUND_UP(den_min, *den);
++		*nom *= tmp;
++		*den *= tmp;
++	}
++}
++
++/**
++ * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
++ *
++ * @nom: nominator
++ * @den: denominator
++ * @post_div: post divider
++ * @fb_div_max: feedback divider maximum
++ * @ref_div_max: reference divider maximum
++ * @fb_div: resulting feedback divider
++ * @ref_div: resulting reference divider
++ *
++ * Calculate feedback and reference divider for a given post divider. Makes
++ * sure we stay within the limits.
++ */
++static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
++				      unsigned fb_div_max, unsigned ref_div_max,
++				      unsigned *fb_div, unsigned *ref_div)
++{
++	/* limit reference * post divider to a maximum */
++	ref_div_max = min(128 / post_div, ref_div_max);
++
++	/* get matching reference and feedback divider */
++	*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
++	*fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
++
++	/* limit fb divider to its maximum */
++	if (*fb_div > fb_div_max) {
++		*ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
++		*fb_div = fb_div_max;
++	}
++}
++
++/**
++ * amdgpu_pll_compute - compute PLL paramaters
++ *
++ * @pll: information about the PLL
++ * @dot_clock_p: resulting pixel clock
++ * fb_div_p: resulting feedback divider
++ * frac_fb_div_p: fractional part of the feedback divider
++ * ref_div_p: resulting reference divider
++ * post_div_p: resulting reference divider
++ *
++ * Try to calculate the PLL parameters to generate the given frequency:
++ * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
++ */
++void amdgpu_pll_compute(struct amdgpu_pll *pll,
++			u32 freq,
++			u32 *dot_clock_p,
++			u32 *fb_div_p,
++			u32 *frac_fb_div_p,
++			u32 *ref_div_p,
++			u32 *post_div_p)
++{
++	unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
++		freq : freq / 10;
++
++	unsigned fb_div_min, fb_div_max, fb_div;
++	unsigned post_div_min, post_div_max, post_div;
++	unsigned ref_div_min, ref_div_max, ref_div;
++	unsigned post_div_best, diff_best;
++	unsigned nom, den;
++
++	/* determine allowed feedback divider range */
++	fb_div_min = pll->min_feedback_div;
++	fb_div_max = pll->max_feedback_div;
++
++	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
++		fb_div_min *= 10;
++		fb_div_max *= 10;
++	}
++
++	/* determine allowed ref divider range */
++	if (pll->flags & AMDGPU_PLL_USE_REF_DIV)
++		ref_div_min = pll->reference_div;
++	else
++		ref_div_min = pll->min_ref_div;
++
++	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&
++	    pll->flags & AMDGPU_PLL_USE_REF_DIV)
++		ref_div_max = pll->reference_div;
++	else
++		ref_div_max = pll->max_ref_div;
++
++	/* determine allowed post divider range */
++	if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {
++		post_div_min = pll->post_div;
++		post_div_max = pll->post_div;
++	} else {
++		unsigned vco_min, vco_max;
++
++		if (pll->flags & AMDGPU_PLL_IS_LCD) {
++			vco_min = pll->lcd_pll_out_min;
++			vco_max = pll->lcd_pll_out_max;
++		} else {
++			vco_min = pll->pll_out_min;
++			vco_max = pll->pll_out_max;
++		}
++
++		if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
++			vco_min *= 10;
++			vco_max *= 10;
++		}
++
++		post_div_min = vco_min / target_clock;
++		if ((target_clock * post_div_min) < vco_min)
++			++post_div_min;
++		if (post_div_min < pll->min_post_div)
++			post_div_min = pll->min_post_div;
++
++		post_div_max = vco_max / target_clock;
++		if ((target_clock * post_div_max) > vco_max)
++			--post_div_max;
++		if (post_div_max > pll->max_post_div)
++			post_div_max = pll->max_post_div;
++	}
++
++	/* represent the searched ratio as fractional number */
++	nom = target_clock;
++	den = pll->reference_freq;
++
++	/* reduce the numbers to a simpler ratio */
++	amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
++
++	/* now search for a post divider */
++	if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)
++		post_div_best = post_div_min;
++	else
++		post_div_best = post_div_max;
++	diff_best = ~0;
++
++	for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
++		unsigned diff;
++		amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max,
++					  ref_div_max, &fb_div, &ref_div);
++		diff = abs(target_clock - (pll->reference_freq * fb_div) /
++			(ref_div * post_div));
++
++		if (diff < diff_best || (diff == diff_best &&
++		    !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {
++
++			post_div_best = post_div;
++			diff_best = diff;
++		}
++	}
++	post_div = post_div_best;
++
++	/* get the feedback and reference divider for the optimal value */
++	amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
++				  &fb_div, &ref_div);
++
++	/* reduce the numbers to a simpler ratio once more */
++	/* this also makes sure that the reference divider is large enough */
++	amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
++
++	/* avoid high jitter with small fractional dividers */
++	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
++		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
++		if (fb_div < fb_div_min) {
++			unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
++			fb_div *= tmp;
++			ref_div *= tmp;
++		}
++	}
++
++	/* and finally save the result */
++	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
++		*fb_div_p = fb_div / 10;
++		*frac_fb_div_p = fb_div % 10;
++	} else {
++		*fb_div_p = fb_div;
++		*frac_fb_div_p = 0;
++	}
++
++	*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
++			(pll->reference_freq * *frac_fb_div_p)) /
++		       (ref_div * post_div * 10);
++	*ref_div_p = ref_div;
++	*post_div_p = post_div;
++
++	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
++		      freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
++		      ref_div, post_div);
++}
++
++/**
++ * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
++ *
++ * @crtc: drm crtc
++ *
++ * Returns the mask of which PPLLs (Pixel PLLs) are in use.
++ */
++u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)
++{
++	struct drm_device *dev = crtc->dev;
++	struct drm_crtc *test_crtc;
++	struct amdgpu_crtc *test_amdgpu_crtc;
++	u32 pll_in_use = 0;
++
++	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
++		if (crtc == test_crtc)
++			continue;
++
++		test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
++		if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
++			pll_in_use |= (1 << test_amdgpu_crtc->pll_id);
++	}
++	return pll_in_use;
++}
++
++/**
++ * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
++ *
++ * @crtc: drm crtc
++ *
++ * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
++ * also in DP mode.  For DP, a single PPLL can be used for all DP
++ * crtcs/encoders.
++ */
++int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc)
++{
++	struct drm_device *dev = crtc->dev;
++	struct drm_crtc *test_crtc;
++	struct amdgpu_crtc *test_amdgpu_crtc;
++
++	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
++		if (crtc == test_crtc)
++			continue;
++		test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
++		if (test_amdgpu_crtc->encoder &&
++		    ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
++			/* for DP use the same PLL for all */
++			if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
++				return test_amdgpu_crtc->pll_id;
++		}
++	}
++	return ATOM_PPLL_INVALID;
++}
++
++/**
++ * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
++ *
++ * @crtc: drm crtc
++ * @encoder: drm encoder
++ *
++ * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
++ * be shared (i.e., same clock).
++ */
++int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct drm_crtc *test_crtc;
++	struct amdgpu_crtc *test_amdgpu_crtc;
++	u32 adjusted_clock, test_adjusted_clock;
++
++	adjusted_clock = amdgpu_crtc->adjusted_clock;
++
++	if (adjusted_clock == 0)
++		return ATOM_PPLL_INVALID;
++
++	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
++		if (crtc == test_crtc)
++			continue;
++		test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
++		if (test_amdgpu_crtc->encoder &&
++		    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
++			/* check if we are already driving this connector with another crtc */
++			if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {
++				/* if we are, return that pll */
++				if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
++					return test_amdgpu_crtc->pll_id;
++			}
++			/* for non-DP check the clock */
++			test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;
++			if ((crtc->mode.clock == test_crtc->mode.clock) &&
++			    (adjusted_clock == test_adjusted_clock) &&
++			    (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&
++			    (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))
++				return test_amdgpu_crtc->pll_id;
++		}
++	}
++	return ATOM_PPLL_INVALID;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h
+new file mode 100644
+index 0000000..db6136f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_PLL_H__
++#define __AMDGPU_PLL_H__
++
++void amdgpu_pll_compute(struct amdgpu_pll *pll,
++			 u32 freq,
++			 u32 *dot_clock_p,
++			 u32 *fb_div_p,
++			 u32 *frac_fb_div_p,
++			 u32 *ref_div_p,
++			 u32 *post_div_p);
++u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc);
++int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc);
++int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+new file mode 100644
+index 0000000..8978254
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -0,0 +1,801 @@
++/*
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Rafał Miłecki <zajec5@gmail.com>
++ *          Alex Deucher <alexdeucher@gmail.com>
++ */
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_drv.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_dpm.h"
++#include "atom.h"
++#include <linux/power_supply.h>
++#include <linux/hwmon.h>
++#include <linux/hwmon-sysfs.h>
++
++static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
++
++void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++		if (power_supply_is_system_supplied() > 0)
++			adev->pm.dpm.ac_power = true;
++		else
++			adev->pm.dpm.ac_power = false;
++		if (adev->pm.funcs->enable_bapm)
++			amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
++		mutex_unlock(&adev->pm.mutex);
++	}
++}
++
++static ssize_t amdgpu_get_dpm_state(struct device *dev,
++				    struct device_attribute *attr,
++				    char *buf)
++{
++	struct drm_device *ddev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = ddev->dev_private;
++	enum amdgpu_pm_state_type pm = adev->pm.dpm.user_state;
++
++	return snprintf(buf, PAGE_SIZE, "%s\n",
++			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
++			(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
++}
++
++static ssize_t amdgpu_set_dpm_state(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf,
++				    size_t count)
++{
++	struct drm_device *ddev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = ddev->dev_private;
++
++	mutex_lock(&adev->pm.mutex);
++	if (strncmp("battery", buf, strlen("battery")) == 0)
++		adev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
++	else if (strncmp("balanced", buf, strlen("balanced")) == 0)
++		adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
++	else if (strncmp("performance", buf, strlen("performance")) == 0)
++		adev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
++	else {
++		mutex_unlock(&adev->pm.mutex);
++		count = -EINVAL;
++		goto fail;
++	}
++	mutex_unlock(&adev->pm.mutex);
++
++	/* Can't set dpm state when the card is off */
++	if (!(adev->flags & AMDGPU_IS_PX) ||
++	    (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
++		amdgpu_pm_compute_clocks(adev);
++fail:
++	return count;
++}
++
++static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
++						       struct device_attribute *attr,
++						       char *buf)
++{
++	struct drm_device *ddev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = ddev->dev_private;
++	enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
++
++	return snprintf(buf, PAGE_SIZE, "%s\n",
++			(level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
++			(level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
++}
++
++static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
++						       struct device_attribute *attr,
++						       const char *buf,
++						       size_t count)
++{
++	struct drm_device *ddev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = ddev->dev_private;
++	enum amdgpu_dpm_forced_level level;
++	int ret = 0;
++
++	mutex_lock(&adev->pm.mutex);
++	if (strncmp("low", buf, strlen("low")) == 0) {
++		level = AMDGPU_DPM_FORCED_LEVEL_LOW;
++	} else if (strncmp("high", buf, strlen("high")) == 0) {
++		level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
++	} else if (strncmp("auto", buf, strlen("auto")) == 0) {
++		level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
++	} else {
++		count = -EINVAL;
++		goto fail;
++	}
++	if (adev->pm.funcs->force_performance_level) {
++		if (adev->pm.dpm.thermal_active) {
++			count = -EINVAL;
++			goto fail;
++		}
++		ret = amdgpu_dpm_force_performance_level(adev, level);
++		if (ret)
++			count = -EINVAL;
++	}
++fail:
++	mutex_unlock(&adev->pm.mutex);
++
++	return count;
++}
++
++static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
++static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
++		   amdgpu_get_dpm_forced_performance_level,
++		   amdgpu_set_dpm_forced_performance_level);
++
++static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
++				      struct device_attribute *attr,
++				      char *buf)
++{
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	int temp;
++
++	if (adev->pm.funcs->get_temperature)
++		temp = amdgpu_dpm_get_temperature(adev);
++	else
++		temp = 0;
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
++}
++
++static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
++					     struct device_attribute *attr,
++					     char *buf)
++{
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	int hyst = to_sensor_dev_attr(attr)->index;
++	int temp;
++
++	if (hyst)
++		temp = adev->pm.dpm.thermal.min_temp;
++	else
++		temp = adev->pm.dpm.thermal.max_temp;
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
++}
++
++static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
++					    struct device_attribute *attr,
++					    char *buf)
++{
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	u32 pwm_mode = 0;
++
++	if (adev->pm.funcs->get_fan_control_mode)
++		pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
++
++	/* never 0 (full-speed), fuse or smc-controlled always */
++	return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
++}
++
++static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
++					    struct device_attribute *attr,
++					    const char *buf,
++					    size_t count)
++{
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	int err;
++	int value;
++
++	if(!adev->pm.funcs->set_fan_control_mode)
++		return -EINVAL;
++
++	err = kstrtoint(buf, 10, &value);
++	if (err)
++		return err;
++
++	switch (value) {
++	case 1: /* manual, percent-based */
++		amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
++		break;
++	default: /* disable */
++		amdgpu_dpm_set_fan_control_mode(adev, 0);
++		break;
++	}
++
++	return count;
++}
++
++static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
++					 struct device_attribute *attr,
++					 char *buf)
++{
++	return sprintf(buf, "%i\n", 0);
++}
++
++static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
++					 struct device_attribute *attr,
++					 char *buf)
++{
++	return sprintf(buf, "%i\n", 255);
++}
++
++static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
++				     struct device_attribute *attr,
++				     const char *buf, size_t count)
++{
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	int err;
++	u32 value;
++
++	err = kstrtou32(buf, 10, &value);
++	if (err)
++		return err;
++
++	value = (value * 100) / 255;
++
++	err = amdgpu_dpm_set_fan_speed_percent(adev, value);
++	if (err)
++		return err;
++
++	return count;
++}
++
++static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
++				     struct device_attribute *attr,
++				     char *buf)
++{
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	int err;
++	u32 speed;
++
++	err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
++	if (err)
++		return err;
++
++	speed = (speed * 255) / 100;
++
++	return sprintf(buf, "%i\n", speed);
++}
++
++static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
++static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
++static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
++static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
++static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
++static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
++static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
++
++static struct attribute *hwmon_attributes[] = {
++	&sensor_dev_attr_temp1_input.dev_attr.attr,
++	&sensor_dev_attr_temp1_crit.dev_attr.attr,
++	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
++	&sensor_dev_attr_pwm1.dev_attr.attr,
++	&sensor_dev_attr_pwm1_enable.dev_attr.attr,
++	&sensor_dev_attr_pwm1_min.dev_attr.attr,
++	&sensor_dev_attr_pwm1_max.dev_attr.attr,
++	NULL
++};
++
++static umode_t hwmon_attributes_visible(struct kobject *kobj,
++					struct attribute *attr, int index)
++{
++	struct device *dev = container_of(kobj, struct device, kobj);
++	struct amdgpu_device *adev = dev_get_drvdata(dev);
++	umode_t effective_mode = attr->mode;
++
++	/* Skip limit attributes if DPM is not enabled */
++	if (!adev->pm.dpm_enabled &&
++	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
++	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
++		return 0;
++
++	/* Skip fan attributes if fan is not present */
++	if (adev->pm.no_fan &&
++	    (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
++	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
++	     attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
++	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
++		return 0;
++
++	/* mask fan attributes if we have no bindings for this asic to expose */
++	if ((!adev->pm.funcs->get_fan_speed_percent &&
++	     attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
++	    (!adev->pm.funcs->get_fan_control_mode &&
++	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
++		effective_mode &= ~S_IRUGO;
++
++	if ((!adev->pm.funcs->set_fan_speed_percent &&
++	     attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
++	    (!adev->pm.funcs->set_fan_control_mode &&
++	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
++		effective_mode &= ~S_IWUSR;
++
++	/* hide max/min values if we can't both query and manage the fan */
++	if ((!adev->pm.funcs->set_fan_speed_percent &&
++	     !adev->pm.funcs->get_fan_speed_percent) &&
++	    (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
++	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
++		return 0;
++
++	return effective_mode;
++}
++
++static const struct attribute_group hwmon_attrgroup = {
++	.attrs = hwmon_attributes,
++	.is_visible = hwmon_attributes_visible,
++};
++
++static const struct attribute_group *hwmon_groups[] = {
++	&hwmon_attrgroup,
++	NULL
++};
++
++void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
++{
++	struct amdgpu_device *adev =
++		container_of(work, struct amdgpu_device,
++			     pm.dpm.thermal.work);
++	/* switch to the thermal state */
++	enum amdgpu_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
++
++	if (!adev->pm.dpm_enabled)
++		return;
++
++	if (adev->pm.funcs->get_temperature) {
++		int temp = amdgpu_dpm_get_temperature(adev);
++
++		if (temp < adev->pm.dpm.thermal.min_temp)
++			/* switch back the user state */
++			dpm_state = adev->pm.dpm.user_state;
++	} else {
++		if (adev->pm.dpm.thermal.high_to_low)
++			/* switch back the user state */
++			dpm_state = adev->pm.dpm.user_state;
++	}
++	mutex_lock(&adev->pm.mutex);
++	if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
++		adev->pm.dpm.thermal_active = true;
++	else
++		adev->pm.dpm.thermal_active = false;
++	adev->pm.dpm.state = dpm_state;
++	mutex_unlock(&adev->pm.mutex);
++
++	amdgpu_pm_compute_clocks(adev);
++}
++
++static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
++						     enum amdgpu_pm_state_type dpm_state)
++{
++	int i;
++	struct amdgpu_ps *ps;
++	u32 ui_class;
++	bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
++		true : false;
++
++	/* check if the vblank period is too short to adjust the mclk */
++	if (single_display && adev->pm.funcs->vblank_too_short) {
++		if (amdgpu_dpm_vblank_too_short(adev))
++			single_display = false;
++	}
++
++	/* certain older asics have a separare 3D performance state,
++	 * so try that first if the user selected performance
++	 */
++	if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
++		dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
++	/* balanced states don't exist at the moment */
++	if (dpm_state == POWER_STATE_TYPE_BALANCED)
++		dpm_state = POWER_STATE_TYPE_PERFORMANCE;
++
++restart_search:
++	/* Pick the best power state based on current conditions */
++	for (i = 0; i < adev->pm.dpm.num_ps; i++) {
++		ps = &adev->pm.dpm.ps[i];
++		ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
++		switch (dpm_state) {
++		/* user states */
++		case POWER_STATE_TYPE_BATTERY:
++			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
++				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
++					if (single_display)
++						return ps;
++				} else
++					return ps;
++			}
++			break;
++		case POWER_STATE_TYPE_BALANCED:
++			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
++				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
++					if (single_display)
++						return ps;
++				} else
++					return ps;
++			}
++			break;
++		case POWER_STATE_TYPE_PERFORMANCE:
++			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
++				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
++					if (single_display)
++						return ps;
++				} else
++					return ps;
++			}
++			break;
++		/* internal states */
++		case POWER_STATE_TYPE_INTERNAL_UVD:
++			if (adev->pm.dpm.uvd_ps)
++				return adev->pm.dpm.uvd_ps;
++			else
++				break;
++		case POWER_STATE_TYPE_INTERNAL_UVD_SD:
++			if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_UVD_HD:
++			if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
++			if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
++			if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_BOOT:
++			return adev->pm.dpm.boot_ps;
++		case POWER_STATE_TYPE_INTERNAL_THERMAL:
++			if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_ACPI:
++			if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_ULV:
++			if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
++				return ps;
++			break;
++		case POWER_STATE_TYPE_INTERNAL_3DPERF:
++			if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
++				return ps;
++			break;
++		default:
++			break;
++		}
++	}
++	/* use a fallback state if we didn't match */
++	switch (dpm_state) {
++	case POWER_STATE_TYPE_INTERNAL_UVD_SD:
++		dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
++		goto restart_search;
++	case POWER_STATE_TYPE_INTERNAL_UVD_HD:
++	case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
++	case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
++		if (adev->pm.dpm.uvd_ps) {
++			return adev->pm.dpm.uvd_ps;
++		} else {
++			dpm_state = POWER_STATE_TYPE_PERFORMANCE;
++			goto restart_search;
++		}
++	case POWER_STATE_TYPE_INTERNAL_THERMAL:
++		dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
++		goto restart_search;
++	case POWER_STATE_TYPE_INTERNAL_ACPI:
++		dpm_state = POWER_STATE_TYPE_BATTERY;
++		goto restart_search;
++	case POWER_STATE_TYPE_BATTERY:
++	case POWER_STATE_TYPE_BALANCED:
++	case POWER_STATE_TYPE_INTERNAL_3DPERF:
++		dpm_state = POWER_STATE_TYPE_PERFORMANCE;
++		goto restart_search;
++	default:
++		break;
++	}
++
++	return NULL;
++}
++
++static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
++{
++	int i;
++	struct amdgpu_ps *ps;
++	enum amdgpu_pm_state_type dpm_state;
++	int ret;
++
++	/* if dpm init failed */
++	if (!adev->pm.dpm_enabled)
++		return;
++
++	if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
++		/* add other state override checks here */
++		if ((!adev->pm.dpm.thermal_active) &&
++		    (!adev->pm.dpm.uvd_active))
++			adev->pm.dpm.state = adev->pm.dpm.user_state;
++	}
++	dpm_state = adev->pm.dpm.state;
++
++	ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
++	if (ps)
++		adev->pm.dpm.requested_ps = ps;
++	else
++		return;
++
++	/* no need to reprogram if nothing changed unless we are on BTC+ */
++	if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
++		/* vce just modifies an existing state so force a change */
++		if (ps->vce_active != adev->pm.dpm.vce_active)
++			goto force;
++		if (adev->flags & AMDGPU_IS_APU) {
++			/* for APUs if the num crtcs changed but state is the same,
++			 * all we need to do is update the display configuration.
++			 */
++			if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
++				/* update display watermarks based on new power state */
++				amdgpu_display_bandwidth_update(adev);
++				/* update displays */
++				amdgpu_dpm_display_configuration_changed(adev);
++				adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
++				adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
++			}
++			return;
++		} else {
++			/* for BTC+ if the num crtcs hasn't changed and state is the same,
++			 * nothing to do, if the num crtcs is > 1 and state is the same,
++			 * update display configuration.
++			 */
++			if (adev->pm.dpm.new_active_crtcs ==
++			    adev->pm.dpm.current_active_crtcs) {
++				return;
++			} else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
++				   (adev->pm.dpm.new_active_crtc_count > 1)) {
++				/* update display watermarks based on new power state */
++				amdgpu_display_bandwidth_update(adev);
++				/* update displays */
++				amdgpu_dpm_display_configuration_changed(adev);
++				adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
++				adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
++				return;
++			}
++		}
++	}
++
++force:
++	if (amdgpu_dpm == 1) {
++		printk("switching from power state:\n");
++		amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
++		printk("switching to power state:\n");
++		amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
++	}
++
++	mutex_lock(&adev->ddev->struct_mutex);
++	down_write(&adev->pm.mclk_lock);
++	mutex_lock(&adev->ring_lock);
++
++	/* update whether vce is active */
++	ps->vce_active = adev->pm.dpm.vce_active;
++
++	ret = amdgpu_dpm_pre_set_power_state(adev);
++	if (ret)
++		goto done;
++
++	/* update display watermarks based on new power state */
++	amdgpu_display_bandwidth_update(adev);
++	/* update displays */
++	amdgpu_dpm_display_configuration_changed(adev);
++
++	adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
++	adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
++
++	/* wait for the rings to drain */
++	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
++		struct amdgpu_ring *ring = adev->rings[i];
++		if (ring && ring->ready)
++			amdgpu_fence_wait_empty(ring);
++	}
++
++	/* program the new power state */
++	amdgpu_dpm_set_power_state(adev);
++
++	/* update current power state */
++	adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
++
++	amdgpu_dpm_post_set_power_state(adev);
++
++	if (adev->pm.funcs->force_performance_level) {
++		if (adev->pm.dpm.thermal_active) {
++			enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
++			/* force low perf level for thermal */
++			amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
++			/* save the user's level */
++			adev->pm.dpm.forced_level = level;
++		} else {
++			/* otherwise, user selected level */
++			amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
++		}
++	}
++
++done:
++	mutex_unlock(&adev->ring_lock);
++	up_write(&adev->pm.mclk_lock);
++	mutex_unlock(&adev->ddev->struct_mutex);
++}
++
++void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
++{
++	if (adev->pm.funcs->powergate_uvd) {
++		mutex_lock(&adev->pm.mutex);
++		/* enable/disable UVD */
++		amdgpu_dpm_powergate_uvd(adev, !enable);
++		mutex_unlock(&adev->pm.mutex);
++	} else {
++		if (enable) {
++			mutex_lock(&adev->pm.mutex);
++			adev->pm.dpm.uvd_active = true;
++			adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
++			mutex_unlock(&adev->pm.mutex);
++		} else {
++			mutex_lock(&adev->pm.mutex);
++			adev->pm.dpm.uvd_active = false;
++			mutex_unlock(&adev->pm.mutex);
++		}
++
++		amdgpu_pm_compute_clocks(adev);
++	}
++}
++
++void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
++{
++	if (enable) {
++		mutex_lock(&adev->pm.mutex);
++		adev->pm.dpm.vce_active = true;
++		/* XXX select vce level based on ring/task */
++		adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
++		mutex_unlock(&adev->pm.mutex);
++	} else {
++		mutex_lock(&adev->pm.mutex);
++		adev->pm.dpm.vce_active = false;
++		mutex_unlock(&adev->pm.mutex);
++	}
++
++	amdgpu_pm_compute_clocks(adev);
++}
++
++void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->pm.dpm.num_ps; i++) {
++		printk("== power state %d ==\n", i);
++		amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
++	}
++}
++
++int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (adev->pm.funcs->get_temperature == NULL)
++		return 0;
++	adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
++								   DRIVER_NAME, adev,
++								   hwmon_groups);
++	if (IS_ERR(adev->pm.int_hwmon_dev)) {
++		ret = PTR_ERR(adev->pm.int_hwmon_dev);
++		dev_err(adev->dev,
++			"Unable to register hwmon device: %d\n", ret);
++		return ret;
++	}
++
++	ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
++	if (ret) {
++		DRM_ERROR("failed to create device file for dpm state\n");
++		return ret;
++	}
++	ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
++	if (ret) {
++		DRM_ERROR("failed to create device file for dpm state\n");
++		return ret;
++	}
++	ret = amdgpu_debugfs_pm_init(adev);
++	if (ret) {
++		DRM_ERROR("Failed to register debugfs file for dpm!\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
++{
++	if (adev->pm.int_hwmon_dev)
++		hwmon_device_unregister(adev->pm.int_hwmon_dev);
++	device_remove_file(adev->dev, &dev_attr_power_dpm_state);
++	device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
++}
++
++void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
++{
++	struct drm_device *ddev = adev->ddev;
++	struct drm_crtc *crtc;
++	struct amdgpu_crtc *amdgpu_crtc;
++
++	if (!adev->pm.dpm_enabled)
++		return;
++
++	mutex_lock(&adev->pm.mutex);
++
++	/* update active crtc counts */
++	adev->pm.dpm.new_active_crtcs = 0;
++	adev->pm.dpm.new_active_crtc_count = 0;
++	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
++		list_for_each_entry(crtc,
++				    &ddev->mode_config.crtc_list, head) {
++			amdgpu_crtc = to_amdgpu_crtc(crtc);
++			if (crtc->enabled) {
++				adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
++				adev->pm.dpm.new_active_crtc_count++;
++			}
++		}
++	}
++
++	/* update battery/ac status */
++	if (power_supply_is_system_supplied() > 0)
++		adev->pm.dpm.ac_power = true;
++	else
++		adev->pm.dpm.ac_power = false;
++
++	amdgpu_dpm_change_power_state_locked(adev);
++
++	mutex_unlock(&adev->pm.mutex);
++
++}
++
++/*
++ * Debugfs info
++ */
++#if defined(CONFIG_DEBUG_FS)
++
++static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *) m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++		if (adev->pm.funcs->debugfs_print_current_performance_level)
++			amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
++		else
++			seq_printf(m, "Debugfs support not implemented for this asic\n");
++		mutex_unlock(&adev->pm.mutex);
++	}
++
++	return 0;
++}
++
++static struct drm_info_list amdgpu_pm_info_list[] = {
++	{"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
++};
++#endif
++
++static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++	return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
++#else
++	return 0;
++#endif
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+new file mode 100644
+index 0000000..5fd7734
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_PM_H__
++#define __AMDGPU_PM_H__
++
++int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
++void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
++void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
++void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
++void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
++void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
++void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+new file mode 100644
+index 0000000..d9652fe
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+@@ -0,0 +1,125 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * based on nouveau_prime.c
++ *
++ * Authors: Alex Deucher
++ */
++#include <drm/drmP.h>
++
++#include "amdgpu.h"
++#include <drm/amdgpu_drm.h>
++#include <linux/dma-buf.h>
++
++struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
++	int npages = bo->tbo.num_pages;
++
++	return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
++}
++
++void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
++	int ret;
++
++	ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
++			  &bo->dma_buf_vmap);
++	if (ret)
++		return ERR_PTR(ret);
++
++	return bo->dma_buf_vmap.virtual;
++}
++
++void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
++
++	ttm_bo_kunmap(&bo->dma_buf_vmap);
++}
++
++struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
++							struct dma_buf_attachment *attach,
++							struct sg_table *sg)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_bo *bo;
++	int ret;
++
++	ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false,
++			       AMDGPU_GEM_DOMAIN_GTT, 0, sg, &bo);
++	if (ret)
++		return ERR_PTR(ret);
++
++	mutex_lock(&adev->gem.mutex);
++	list_add_tail(&bo->list, &adev->gem.objects);
++	mutex_unlock(&adev->gem.mutex);
++
++	return &bo->gem_base;
++}
++
++int amdgpu_gem_prime_pin(struct drm_gem_object *obj)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
++	int ret = 0;
++
++	ret = amdgpu_bo_reserve(bo, false);
++	if (unlikely(ret != 0))
++		return ret;
++
++	/* pin buffer into GTT */
++	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
++	amdgpu_bo_unreserve(bo);
++	return ret;
++}
++
++void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
++	int ret = 0;
++
++	ret = amdgpu_bo_reserve(bo, false);
++	if (unlikely(ret != 0))
++		return;
++
++	amdgpu_bo_unpin(bo);
++	amdgpu_bo_unreserve(bo);
++}
++
++struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
++
++	return bo->tbo.resv;
++}
++
++struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
++					struct drm_gem_object *gobj,
++					int flags)
++{
++	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
++
++	if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm))
++		return ERR_PTR(-EPERM);
++
++	return drm_gem_prime_export(dev, gobj, flags);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+new file mode 100644
+index 0000000..855e219
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+@@ -0,0 +1,561 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ *          Christian König
++ */
++#include <linux/seq_file.h>
++#include <linux/slab.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "atom.h"
++
++/*
++ * Rings
++ * Most engines on the GPU are fed via ring buffers.  Ring
++ * buffers are areas of GPU accessible memory that the host
++ * writes commands into and the GPU reads commands out of.
++ * There is a rptr (read pointer) that determines where the
++ * GPU is currently reading, and a wptr (write pointer)
++ * which determines where the host has written.  When the
++ * pointers are equal, the ring is idle.  When the host
++ * writes commands to the ring buffer, it increments the
++ * wptr.  The GPU then starts fetching commands and executes
++ * them until the pointers are equal again.
++ */
++static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
++
++/**
++ * amdgpu_ring_free_size - update the free size
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Update the free dw slots in the ring buffer (all asics).
++ */
++void amdgpu_ring_free_size(struct amdgpu_ring *ring)
++{
++	uint32_t rptr = amdgpu_ring_get_rptr(ring);
++
++	/* This works because ring_size is a power of 2 */
++	ring->ring_free_dw = rptr + (ring->ring_size / 4);
++	ring->ring_free_dw -= ring->wptr;
++	ring->ring_free_dw &= ring->ptr_mask;
++	if (!ring->ring_free_dw) {
++		/* this is an empty ring */
++		ring->ring_free_dw = ring->ring_size / 4;
++		/*  update lockup info to avoid false positive */
++		amdgpu_ring_lockup_update(ring);
++	}
++}
++
++/**
++ * amdgpu_ring_alloc - allocate space on the ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ * @ndw: number of dwords to allocate in the ring buffer
++ *
++ * Allocate @ndw dwords in the ring buffer (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
++{
++	int r;
++
++	/* make sure we aren't trying to allocate more space than there is on the ring */
++	if (ndw > (ring->ring_size / 4))
++		return -ENOMEM;
++	/* Align requested size with padding so unlock_commit can
++	 * pad safely */
++	amdgpu_ring_free_size(ring);
++	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
++	while (ndw > (ring->ring_free_dw - 1)) {
++		amdgpu_ring_free_size(ring);
++		if (ndw < ring->ring_free_dw) {
++			break;
++		}
++		r = amdgpu_fence_wait_next(ring);
++		if (r)
++			return r;
++	}
++	ring->count_dw = ndw;
++	ring->wptr_old = ring->wptr;
++	return 0;
++}
++
++/**
++ * amdgpu_ring_lock - lock the ring and allocate space on it
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ * @ndw: number of dwords to allocate in the ring buffer
++ *
++ * Lock the ring and allocate @ndw dwords in the ring buffer
++ * (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw)
++{
++	int r;
++
++	mutex_lock(ring->ring_lock);
++	r = amdgpu_ring_alloc(ring, ndw);
++	if (r) {
++		mutex_unlock(ring->ring_lock);
++		return r;
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_ring_commit - tell the GPU to execute the new
++ * commands on the ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Update the wptr (write pointer) to tell the GPU to
++ * execute new commands on the ring buffer (all asics).
++ */
++void amdgpu_ring_commit(struct amdgpu_ring *ring)
++{
++	/* We pad to match fetch size */
++	while (ring->wptr & ring->align_mask) {
++		amdgpu_ring_write(ring, ring->nop);
++	}
++	mb();
++	amdgpu_ring_set_wptr(ring);
++}
++
++/**
++ * amdgpu_ring_unlock_commit - tell the GPU to execute the new
++ * commands on the ring buffer and unlock it
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Call amdgpu_ring_commit() then unlock the ring (all asics).
++ */
++void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring)
++{
++	amdgpu_ring_commit(ring);
++	mutex_unlock(ring->ring_lock);
++}
++
++/**
++ * amdgpu_ring_undo - reset the wptr
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Reset the driver's copy of the wptr (all asics).
++ */
++void amdgpu_ring_undo(struct amdgpu_ring *ring)
++{
++	ring->wptr = ring->wptr_old;
++}
++
++/**
++ * amdgpu_ring_unlock_undo - reset the wptr and unlock the ring
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Call amdgpu_ring_undo() then unlock the ring (all asics).
++ */
++void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring)
++{
++	amdgpu_ring_undo(ring);
++	mutex_unlock(ring->ring_lock);
++}
++
++/**
++ * amdgpu_ring_lockup_update - update lockup variables
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Update the last rptr value and timestamp (all asics).
++ */
++void amdgpu_ring_lockup_update(struct amdgpu_ring *ring)
++{
++	atomic_set(&ring->last_rptr, amdgpu_ring_get_rptr(ring));
++	atomic64_set(&ring->last_activity, jiffies_64);
++}
++
++/**
++ * amdgpu_ring_test_lockup() - check if ring is lockedup by recording information
++ * @ring:       amdgpu_ring structure holding ring information
++ *
++ */
++bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring)
++{
++	uint32_t rptr = amdgpu_ring_get_rptr(ring);
++	uint64_t last = atomic64_read(&ring->last_activity);
++	uint64_t elapsed;
++
++	if (rptr != atomic_read(&ring->last_rptr)) {
++		/* ring is still working, no lockup */
++		amdgpu_ring_lockup_update(ring);
++		return false;
++	}
++
++	elapsed = jiffies_to_msecs(jiffies_64 - last);
++	if (amdgpu_lockup_timeout && elapsed >= amdgpu_lockup_timeout) {
++		dev_err(ring->adev->dev, "ring %d stalled for more than %llumsec\n",
++			ring->idx, elapsed);
++		return true;
++	}
++	/* give a chance to the GPU ... */
++	return false;
++}
++
++/**
++ * amdgpu_ring_backup - Back up the content of a ring
++ *
++ * @ring: the ring we want to back up
++ *
++ * Saves all unprocessed commits from a ring, returns the number of dwords saved.
++ */
++unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
++			    uint32_t **data)
++{
++	unsigned size, ptr, i;
++
++	/* just in case lock the ring */
++	mutex_lock(ring->ring_lock);
++	*data = NULL;
++
++	if (ring->ring_obj == NULL) {
++		mutex_unlock(ring->ring_lock);
++		return 0;
++	}
++
++	/* it doesn't make sense to save anything if all fences are signaled */
++	if (!amdgpu_fence_count_emitted(ring)) {
++		mutex_unlock(ring->ring_lock);
++		return 0;
++	}
++
++	ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
++
++	size = ring->wptr + (ring->ring_size / 4);
++	size -= ptr;
++	size &= ring->ptr_mask;
++	if (size == 0) {
++		mutex_unlock(ring->ring_lock);
++		return 0;
++	}
++
++	/* and then save the content of the ring */
++	*data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
++	if (!*data) {
++		mutex_unlock(ring->ring_lock);
++		return 0;
++	}
++	for (i = 0; i < size; ++i) {
++		(*data)[i] = ring->ring[ptr++];
++		ptr &= ring->ptr_mask;
++	}
++
++	mutex_unlock(ring->ring_lock);
++	return size;
++}
++
++/**
++ * amdgpu_ring_restore - append saved commands to the ring again
++ *
++ * @ring: ring to append commands to
++ * @size: number of dwords we want to write
++ * @data: saved commands
++ *
++ * Allocates space on the ring and restore the previously saved commands.
++ */
++int amdgpu_ring_restore(struct amdgpu_ring *ring,
++			unsigned size, uint32_t *data)
++{
++	int i, r;
++
++	if (!size || !data)
++		return 0;
++
++	/* restore the saved ring content */
++	r = amdgpu_ring_lock(ring, size);
++	if (r)
++		return r;
++
++	for (i = 0; i < size; ++i) {
++		amdgpu_ring_write(ring, data[i]);
++	}
++
++	amdgpu_ring_unlock_commit(ring);
++	kfree(data);
++	return 0;
++}
++
++/**
++ * amdgpu_ring_init - init driver ring struct.
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ * @ring_size: size of the ring
++ * @nop: nop packet for this ring
++ *
++ * Initialize the driver information for the selected ring (all asics).
++ * Returns 0 on success, error on failure.
++ */
++int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
++		     unsigned ring_size, u32 nop, u32 align_mask,
++		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
++		     enum amdgpu_ring_type ring_type)
++{
++	u32 rb_bufsz;
++	int r;
++
++	if (ring->adev == NULL) {
++		if (adev->num_rings >= AMDGPU_MAX_RINGS)
++			return -EINVAL;
++
++		ring->adev = adev;
++		ring->idx = adev->num_rings++;
++		adev->rings[ring->idx] = ring;
++		amdgpu_fence_driver_init_ring(ring);
++	}
++
++	r = amdgpu_wb_get(adev, &ring->rptr_offs);
++	if (r) {
++		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
++		return r;
++	}
++
++	r = amdgpu_wb_get(adev, &ring->wptr_offs);
++	if (r) {
++		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
++		return r;
++	}
++
++	r = amdgpu_wb_get(adev, &ring->fence_offs);
++	if (r) {
++		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
++		return r;
++	}
++
++	r = amdgpu_wb_get(adev, &ring->next_rptr_offs);
++	if (r) {
++		dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r);
++		return r;
++	}
++	ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4);
++	ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
++
++	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
++	if (r) {
++		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
++		return r;
++	}
++
++	ring->ring_lock = &adev->ring_lock;
++	/* Align ring size */
++	rb_bufsz = order_base_2(ring_size / 8);
++	ring_size = (1 << (rb_bufsz + 1)) * 4;
++	ring->ring_size = ring_size;
++	ring->align_mask = align_mask;
++	ring->nop = nop;
++	ring->type = ring_type;
++
++	/* Allocate ring buffer */
++	if (ring->ring_obj == NULL) {
++		r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_GTT, 0,
++				     NULL, &ring->ring_obj);
++		if (r) {
++			dev_err(adev->dev, "(%d) ring create failed\n", r);
++			return r;
++		}
++		r = amdgpu_bo_reserve(ring->ring_obj, false);
++		if (unlikely(r != 0))
++			return r;
++		r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT,
++					&ring->gpu_addr);
++		if (r) {
++			amdgpu_bo_unreserve(ring->ring_obj);
++			dev_err(adev->dev, "(%d) ring pin failed\n", r);
++			return r;
++		}
++		r = amdgpu_bo_kmap(ring->ring_obj,
++				       (void **)&ring->ring);
++		amdgpu_bo_unreserve(ring->ring_obj);
++		if (r) {
++			dev_err(adev->dev, "(%d) ring map failed\n", r);
++			return r;
++		}
++	}
++	ring->ptr_mask = (ring->ring_size / 4) - 1;
++	ring->ring_free_dw = ring->ring_size / 4;
++
++	if (amdgpu_debugfs_ring_init(adev, ring)) {
++		DRM_ERROR("Failed to register debugfs file for rings !\n");
++	}
++	amdgpu_ring_lockup_update(ring);
++	return 0;
++}
++
++/**
++ * amdgpu_ring_fini - tear down the driver ring struct.
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Tear down the driver information for the selected ring (all asics).
++ */
++void amdgpu_ring_fini(struct amdgpu_ring *ring)
++{
++	int r;
++	struct amdgpu_bo *ring_obj;
++
++	if (ring->ring_lock == NULL)
++		return;
++
++	mutex_lock(ring->ring_lock);
++	ring_obj = ring->ring_obj;
++	ring->ready = false;
++	ring->ring = NULL;
++	ring->ring_obj = NULL;
++	mutex_unlock(ring->ring_lock);
++
++	amdgpu_wb_free(ring->adev, ring->fence_offs);
++	amdgpu_wb_free(ring->adev, ring->rptr_offs);
++	amdgpu_wb_free(ring->adev, ring->wptr_offs);
++	amdgpu_wb_free(ring->adev, ring->next_rptr_offs);
++
++	if (ring_obj) {
++		r = amdgpu_bo_reserve(ring_obj, false);
++		if (likely(r == 0)) {
++			amdgpu_bo_kunmap(ring_obj);
++			amdgpu_bo_unpin(ring_obj);
++			amdgpu_bo_unreserve(ring_obj);
++		}
++		amdgpu_bo_unref(&ring_obj);
++	}
++}
++
++/*
++ * Debugfs info
++ */
++#if defined(CONFIG_DEBUG_FS)
++
++static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *) m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int roffset = *(int*)node->info_ent->data;
++	struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset);
++
++	uint32_t rptr, wptr, rptr_next;
++	unsigned count, i, j;
++
++	amdgpu_ring_free_size(ring);
++	count = (ring->ring_size / 4) - ring->ring_free_dw;
++
++	wptr = amdgpu_ring_get_wptr(ring);
++	seq_printf(m, "wptr: 0x%08x [%5d]\n",
++		   wptr, wptr);
++
++	rptr = amdgpu_ring_get_rptr(ring);
++	seq_printf(m, "rptr: 0x%08x [%5d]\n",
++		   rptr, rptr);
++
++	rptr_next = ~0;
++
++	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
++		   ring->wptr, ring->wptr);
++	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
++		   ring->last_semaphore_signal_addr);
++	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
++		   ring->last_semaphore_wait_addr);
++	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
++	seq_printf(m, "%u dwords in ring\n", count);
++
++	if (!ring->ready)
++		return 0;
++
++	/* print 8 dw before current rptr as often it's the last executed
++	 * packet that is the root issue
++	 */
++	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
++	for (j = 0; j <= (count + 32); j++) {
++		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
++		if (rptr == i)
++			seq_puts(m, " *");
++		if (rptr_next == i)
++			seq_puts(m, " #");
++		seq_puts(m, "\n");
++		i = (i + 1) & ring->ptr_mask;
++	}
++	return 0;
++}
++
++/* TODO: clean this up !*/
++static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);
++static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);
++static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
++static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma[0].ring);
++static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma[1].ring);
++static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
++static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
++static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
++
++static struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
++	{"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index},
++	{"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index},
++	{"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index},
++	{"amdgpu_ring_dma1", amdgpu_debugfs_ring_info, 0, &amdgpu_dma1_index},
++	{"amdgpu_ring_dma2", amdgpu_debugfs_ring_info, 0, &amdgpu_dma2_index},
++	{"amdgpu_ring_uvd", amdgpu_debugfs_ring_info, 0, &r600_uvd_index},
++	{"amdgpu_ring_vce1", amdgpu_debugfs_ring_info, 0, &si_vce1_index},
++	{"amdgpu_ring_vce2", amdgpu_debugfs_ring_info, 0, &si_vce2_index},
++};
++
++#endif
++
++static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)
++{
++#if defined(CONFIG_DEBUG_FS)
++	unsigned i;
++	for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
++		struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
++		int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data;
++		struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset);
++		unsigned r;
++
++		if (other != ring)
++			continue;
++
++		r = amdgpu_debugfs_add_files(adev, info, 1);
++		if (r)
++			return r;
++	}
++#endif
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+new file mode 100644
+index 0000000..eb20987
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+@@ -0,0 +1,419 @@
++/*
++ * Copyright 2011 Red Hat Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Jerome Glisse <glisse@freedesktop.org>
++ */
++/* Algorithm:
++ *
++ * We store the last allocated bo in "hole", we always try to allocate
++ * after the last allocated bo. Principle is that in a linear GPU ring
++ * progression was is after last is the oldest bo we allocated and thus
++ * the first one that should no longer be in use by the GPU.
++ *
++ * If it's not the case we skip over the bo after last to the closest
++ * done bo if such one exist. If none exist and we are not asked to
++ * block we report failure to allocate.
++ *
++ * If we are asked to block we wait on all the oldest fence of all
++ * rings. We just wait for any of those fence to complete.
++ */
++#include <drm/drmP.h>
++#include "amdgpu.h"
++
++static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo);
++static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager);
++
++int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
++			      struct amdgpu_sa_manager *sa_manager,
++			      unsigned size, u32 align, u32 domain)
++{
++	int i, r;
++
++	init_waitqueue_head(&sa_manager->wq);
++	sa_manager->bo = NULL;
++	sa_manager->size = size;
++	sa_manager->domain = domain;
++	sa_manager->align = align;
++	sa_manager->hole = &sa_manager->olist;
++	INIT_LIST_HEAD(&sa_manager->olist);
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		INIT_LIST_HEAD(&sa_manager->flist[i]);
++	}
++
++	r = amdgpu_bo_create(adev, size, align, true,
++			     domain, 0, NULL, &sa_manager->bo);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
++		return r;
++	}
++
++	return r;
++}
++
++void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
++			       struct amdgpu_sa_manager *sa_manager)
++{
++	struct amdgpu_sa_bo *sa_bo, *tmp;
++
++	if (!list_empty(&sa_manager->olist)) {
++		sa_manager->hole = &sa_manager->olist,
++		amdgpu_sa_bo_try_free(sa_manager);
++		if (!list_empty(&sa_manager->olist)) {
++			dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n");
++		}
++	}
++	list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
++		amdgpu_sa_bo_remove_locked(sa_bo);
++	}
++	amdgpu_bo_unref(&sa_manager->bo);
++	sa_manager->size = 0;
++}
++
++int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
++			       struct amdgpu_sa_manager *sa_manager)
++{
++	int r;
++
++	if (sa_manager->bo == NULL) {
++		dev_err(adev->dev, "no bo for sa manager\n");
++		return -EINVAL;
++	}
++
++	/* map the buffer */
++	r = amdgpu_bo_reserve(sa_manager->bo, false);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to reserve manager bo\n", r);
++		return r;
++	}
++	r = amdgpu_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
++	if (r) {
++		amdgpu_bo_unreserve(sa_manager->bo);
++		dev_err(adev->dev, "(%d) failed to pin manager bo\n", r);
++		return r;
++	}
++	r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr);
++	amdgpu_bo_unreserve(sa_manager->bo);
++	return r;
++}
++
++int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
++				 struct amdgpu_sa_manager *sa_manager)
++{
++	int r;
++
++	if (sa_manager->bo == NULL) {
++		dev_err(adev->dev, "no bo for sa manager\n");
++		return -EINVAL;
++	}
++
++	r = amdgpu_bo_reserve(sa_manager->bo, false);
++	if (!r) {
++		amdgpu_bo_kunmap(sa_manager->bo);
++		amdgpu_bo_unpin(sa_manager->bo);
++		amdgpu_bo_unreserve(sa_manager->bo);
++	}
++	return r;
++}
++
++static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo)
++{
++	struct amdgpu_sa_manager *sa_manager = sa_bo->manager;
++	if (sa_manager->hole == &sa_bo->olist) {
++		sa_manager->hole = sa_bo->olist.prev;
++	}
++	list_del_init(&sa_bo->olist);
++	list_del_init(&sa_bo->flist);
++	amdgpu_fence_unref(&sa_bo->fence);
++	kfree(sa_bo);
++}
++
++static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager)
++{
++	struct amdgpu_sa_bo *sa_bo, *tmp;
++
++	if (sa_manager->hole->next == &sa_manager->olist)
++		return;
++
++	sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist);
++	list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
++		if (sa_bo->fence == NULL || !amdgpu_fence_signaled(sa_bo->fence)) {
++			return;
++		}
++		amdgpu_sa_bo_remove_locked(sa_bo);
++	}
++}
++
++static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager *sa_manager)
++{
++	struct list_head *hole = sa_manager->hole;
++
++	if (hole != &sa_manager->olist) {
++		return list_entry(hole, struct amdgpu_sa_bo, olist)->eoffset;
++	}
++	return 0;
++}
++
++static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager *sa_manager)
++{
++	struct list_head *hole = sa_manager->hole;
++
++	if (hole->next != &sa_manager->olist) {
++		return list_entry(hole->next, struct amdgpu_sa_bo, olist)->soffset;
++	}
++	return sa_manager->size;
++}
++
++static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager *sa_manager,
++				   struct amdgpu_sa_bo *sa_bo,
++				   unsigned size, unsigned align)
++{
++	unsigned soffset, eoffset, wasted;
++
++	soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
++	eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
++	wasted = (align - (soffset % align)) % align;
++
++	if ((eoffset - soffset) >= (size + wasted)) {
++		soffset += wasted;
++
++		sa_bo->manager = sa_manager;
++		sa_bo->soffset = soffset;
++		sa_bo->eoffset = soffset + size;
++		list_add(&sa_bo->olist, sa_manager->hole);
++		INIT_LIST_HEAD(&sa_bo->flist);
++		sa_manager->hole = &sa_bo->olist;
++		return true;
++	}
++	return false;
++}
++
++/**
++ * amdgpu_sa_event - Check if we can stop waiting
++ *
++ * @sa_manager: pointer to the sa_manager
++ * @size: number of bytes we want to allocate
++ * @align: alignment we need to match
++ *
++ * Check if either there is a fence we can wait for or
++ * enough free memory to satisfy the allocation directly
++ */
++static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
++			    unsigned size, unsigned align)
++{
++	unsigned soffset, eoffset, wasted;
++	int i;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		if (!list_empty(&sa_manager->flist[i])) {
++			return true;
++		}
++	}
++
++	soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
++	eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
++	wasted = (align - (soffset % align)) % align;
++
++	if ((eoffset - soffset) >= (size + wasted)) {
++		return true;
++	}
++
++	return false;
++}
++
++static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
++				   struct amdgpu_fence **fences,
++				   unsigned *tries)
++{
++	struct amdgpu_sa_bo *best_bo = NULL;
++	unsigned i, soffset, best, tmp;
++
++	/* if hole points to the end of the buffer */
++	if (sa_manager->hole->next == &sa_manager->olist) {
++		/* try again with its beginning */
++		sa_manager->hole = &sa_manager->olist;
++		return true;
++	}
++
++	soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
++	/* to handle wrap around we add sa_manager->size */
++	best = sa_manager->size * 2;
++	/* go over all fence list and try to find the closest sa_bo
++	 * of the current last
++	 */
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		struct amdgpu_sa_bo *sa_bo;
++
++		if (list_empty(&sa_manager->flist[i])) {
++			continue;
++		}
++
++		sa_bo = list_first_entry(&sa_manager->flist[i],
++					 struct amdgpu_sa_bo, flist);
++
++		if (!amdgpu_fence_signaled(sa_bo->fence)) {
++			fences[i] = sa_bo->fence;
++			continue;
++		}
++
++		/* limit the number of tries each ring gets */
++		if (tries[i] > 2) {
++			continue;
++		}
++
++		tmp = sa_bo->soffset;
++		if (tmp < soffset) {
++			/* wrap around, pretend it's after */
++			tmp += sa_manager->size;
++		}
++		tmp -= soffset;
++		if (tmp < best) {
++			/* this sa bo is the closest one */
++			best = tmp;
++			best_bo = sa_bo;
++		}
++	}
++
++	if (best_bo) {
++		++tries[best_bo->fence->ring->idx];
++		sa_manager->hole = best_bo->olist.prev;
++
++		/* we knew that this one is signaled,
++		   so it's save to remote it */
++		amdgpu_sa_bo_remove_locked(best_bo);
++		return true;
++	}
++	return false;
++}
++
++int amdgpu_sa_bo_new(struct amdgpu_device *adev,
++		     struct amdgpu_sa_manager *sa_manager,
++		     struct amdgpu_sa_bo **sa_bo,
++		     unsigned size, unsigned align)
++{
++	struct amdgpu_fence *fences[AMDGPU_MAX_RINGS];
++	unsigned tries[AMDGPU_MAX_RINGS];
++	int i, r;
++
++	BUG_ON(align > sa_manager->align);
++	BUG_ON(size > sa_manager->size);
++
++	*sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
++	if ((*sa_bo) == NULL) {
++		return -ENOMEM;
++	}
++	(*sa_bo)->manager = sa_manager;
++	(*sa_bo)->fence = NULL;
++	INIT_LIST_HEAD(&(*sa_bo)->olist);
++	INIT_LIST_HEAD(&(*sa_bo)->flist);
++
++	spin_lock(&sa_manager->wq.lock);
++	do {
++		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++			fences[i] = NULL;
++			tries[i] = 0;
++		}
++
++		do {
++			amdgpu_sa_bo_try_free(sa_manager);
++
++			if (amdgpu_sa_bo_try_alloc(sa_manager, *sa_bo,
++						   size, align)) {
++				spin_unlock(&sa_manager->wq.lock);
++				return 0;
++			}
++
++			/* see if we can skip over some allocations */
++		} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
++
++		spin_unlock(&sa_manager->wq.lock);
++		r = amdgpu_fence_wait_any(adev, fences, false);
++		spin_lock(&sa_manager->wq.lock);
++		/* if we have nothing to wait for block */
++		if (r == -ENOENT) {
++			r = wait_event_interruptible_locked(
++				sa_manager->wq,
++				amdgpu_sa_event(sa_manager, size, align)
++			);
++		}
++
++	} while (!r);
++
++	spin_unlock(&sa_manager->wq.lock);
++	kfree(*sa_bo);
++	*sa_bo = NULL;
++	return r;
++}
++
++void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
++		       struct amdgpu_fence *fence)
++{
++	struct amdgpu_sa_manager *sa_manager;
++
++	if (sa_bo == NULL || *sa_bo == NULL) {
++		return;
++	}
++
++	sa_manager = (*sa_bo)->manager;
++	spin_lock(&sa_manager->wq.lock);
++	if (fence && !amdgpu_fence_signaled(fence)) {
++		(*sa_bo)->fence = amdgpu_fence_ref(fence);
++		list_add_tail(&(*sa_bo)->flist,
++			      &sa_manager->flist[fence->ring->idx]);
++	} else {
++		amdgpu_sa_bo_remove_locked(*sa_bo);
++	}
++	wake_up_all_locked(&sa_manager->wq);
++	spin_unlock(&sa_manager->wq.lock);
++	*sa_bo = NULL;
++}
++
++#if defined(CONFIG_DEBUG_FS)
++void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
++				  struct seq_file *m)
++{
++	struct amdgpu_sa_bo *i;
++
++	spin_lock(&sa_manager->wq.lock);
++	list_for_each_entry(i, &sa_manager->olist, olist) {
++		uint64_t soffset = i->soffset + sa_manager->gpu_addr;
++		uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
++		if (&i->olist == sa_manager->hole) {
++			seq_printf(m, ">");
++		} else {
++			seq_printf(m, " ");
++		}
++		seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
++			   soffset, eoffset, eoffset - soffset);
++		if (i->fence) {
++			seq_printf(m, " protected by 0x%016llx on ring %d",
++				   i->fence->seq, i->fence->ring->idx);
++		}
++		seq_printf(m, "\n");
++	}
++	spin_unlock(&sa_manager->wq.lock);
++}
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c
+new file mode 100644
+index 0000000..d6d41a4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c
+@@ -0,0 +1,102 @@
++/*
++ * Copyright 2011 Christian König.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Christian König <deathsimple@vodafone.de>
++ */
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_trace.h"
++
++int amdgpu_semaphore_create(struct amdgpu_device *adev,
++			    struct amdgpu_semaphore **semaphore)
++{
++	int r;
++
++	*semaphore = kmalloc(sizeof(struct amdgpu_semaphore), GFP_KERNEL);
++	if (*semaphore == NULL) {
++		return -ENOMEM;
++	}
++	r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo,
++			     &(*semaphore)->sa_bo, 8, 8);
++	if (r) {
++		kfree(*semaphore);
++		*semaphore = NULL;
++		return r;
++	}
++	(*semaphore)->waiters = 0;
++	(*semaphore)->gpu_addr = amdgpu_sa_bo_gpu_addr((*semaphore)->sa_bo);
++
++	*((uint64_t *)amdgpu_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0;
++
++	return 0;
++}
++
++bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
++				  struct amdgpu_semaphore *semaphore)
++{
++	trace_amdgpu_semaphore_signale(ring->idx, semaphore);
++
++	if (amdgpu_ring_emit_semaphore(ring, semaphore, false)) {
++		--semaphore->waiters;
++
++		/* for debugging lockup only, used by sysfs debug files */
++		ring->last_semaphore_signal_addr = semaphore->gpu_addr;
++		return true;
++	}
++	return false;
++}
++
++bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
++				struct amdgpu_semaphore *semaphore)
++{
++	trace_amdgpu_semaphore_wait(ring->idx, semaphore);
++
++	if (amdgpu_ring_emit_semaphore(ring, semaphore, true)) {
++		++semaphore->waiters;
++
++		/* for debugging lockup only, used by sysfs debug files */
++		ring->last_semaphore_wait_addr = semaphore->gpu_addr;
++		return true;
++	}
++	return false;
++}
++
++void amdgpu_semaphore_free(struct amdgpu_device *adev,
++			   struct amdgpu_semaphore **semaphore,
++			   struct amdgpu_fence *fence)
++{
++	if (semaphore == NULL || *semaphore == NULL) {
++		return;
++	}
++	if ((*semaphore)->waiters > 0) {
++		dev_err(adev->dev, "semaphore %p has more waiters than signalers,"
++			" hardware lockup imminent!\n", *semaphore);
++	}
++	amdgpu_sa_bo_free(adev, &(*semaphore)->sa_bo, fence);
++	kfree(*semaphore);
++	*semaphore = NULL;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+new file mode 100644
+index 0000000..855d56a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+@@ -0,0 +1,231 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Christian König <christian.koenig@amd.com>
++ */
++
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_trace.h"
++
++/**
++ * amdgpu_sync_create - zero init sync object
++ *
++ * @sync: sync object to initialize
++ *
++ * Just clear the sync object for now.
++ */
++void amdgpu_sync_create(struct amdgpu_sync *sync)
++{
++	unsigned i;
++
++	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
++		sync->semaphores[i] = NULL;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
++		sync->sync_to[i] = NULL;
++
++	sync->last_vm_update = NULL;
++}
++
++/**
++ * amdgpu_sync_fence - use the semaphore to sync to a fence
++ *
++ * @sync: sync object to add fence to
++ * @fence: fence to sync to
++ *
++ * Sync to the fence using the semaphore objects
++ */
++void amdgpu_sync_fence(struct amdgpu_sync *sync,
++		       struct amdgpu_fence *fence)
++{
++	struct amdgpu_fence *other;
++
++	if (!fence)
++		return;
++
++	other = sync->sync_to[fence->ring->idx];
++	sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
++		amdgpu_fence_later(fence, other));
++	amdgpu_fence_unref(&other);
++
++	if (fence->owner == AMDGPU_FENCE_OWNER_VM) {
++		other = sync->last_vm_update;
++		sync->last_vm_update = amdgpu_fence_ref(
++			amdgpu_fence_later(fence, other));
++		amdgpu_fence_unref(&other);
++	}
++}
++
++/**
++ * amdgpu_sync_resv - use the semaphores to sync to a reservation object
++ *
++ * @sync: sync object to add fences from reservation object to
++ * @resv: reservation object with embedded fence
++ * @shared: true if we should only sync to the exclusive fence
++ *
++ * Sync to the fence using the semaphore objects
++ */
++int amdgpu_sync_resv(struct amdgpu_device *adev,
++		     struct amdgpu_sync *sync,
++		     struct reservation_object *resv,
++		     void *owner)
++{
++	struct reservation_object_list *flist;
++	struct fence *f;
++	struct amdgpu_fence *fence;
++	unsigned i;
++	int r = 0;
++
++	/* always sync to the exclusive fence */
++	f = reservation_object_get_excl(resv);
++	fence = f ? to_amdgpu_fence(f) : NULL;
++	if (fence && fence->ring->adev == adev)
++		amdgpu_sync_fence(sync, fence);
++	else if (f)
++		r = fence_wait(f, true);
++
++	flist = reservation_object_get_list(resv);
++	if (!flist || r)
++		return r;
++
++	for (i = 0; i < flist->shared_count; ++i) {
++		f = rcu_dereference_protected(flist->shared[i],
++					      reservation_object_held(resv));
++		fence = to_amdgpu_fence(f);
++		if (fence && fence->ring->adev == adev) {
++			if (fence->owner != owner ||
++			    fence->owner == AMDGPU_FENCE_OWNER_UNDEFINED)
++				amdgpu_sync_fence(sync, fence);
++		} else {
++			r = fence_wait(f, true);
++			if (r)
++				break;
++		}
++	}
++	return r;
++}
++
++/**
++ * amdgpu_sync_rings - sync ring to all registered fences
++ *
++ * @sync: sync object to use
++ * @ring: ring that needs sync
++ *
++ * Ensure that all registered fences are signaled before letting
++ * the ring continue. The caller must hold the ring lock.
++ */
++int amdgpu_sync_rings(struct amdgpu_sync *sync,
++		      struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	unsigned count = 0;
++	int i, r;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		struct amdgpu_fence *fence = sync->sync_to[i];
++		struct amdgpu_semaphore *semaphore;
++		struct amdgpu_ring *other = adev->rings[i];
++
++		/* check if we really need to sync */
++		if (!amdgpu_fence_need_sync(fence, ring))
++			continue;
++
++		/* prevent GPU deadlocks */
++		if (!other->ready) {
++			dev_err(adev->dev, "Syncing to a disabled ring!");
++			return -EINVAL;
++		}
++
++		if (count >= AMDGPU_NUM_SYNCS) {
++			/* not enough room, wait manually */
++			r = amdgpu_fence_wait(fence, false);
++			if (r)
++				return r;
++			continue;
++		}
++		r = amdgpu_semaphore_create(adev, &semaphore);
++		if (r)
++			return r;
++
++		sync->semaphores[count++] = semaphore;
++
++		/* allocate enough space for sync command */
++		r = amdgpu_ring_alloc(other, 16);
++		if (r)
++			return r;
++
++		/* emit the signal semaphore */
++		if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
++			/* signaling wasn't successful wait manually */
++			amdgpu_ring_undo(other);
++			r = amdgpu_fence_wait(fence, false);
++			if (r)
++				return r;
++			continue;
++		}
++
++		/* we assume caller has already allocated space on waiters ring */
++		if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
++			/* waiting wasn't successful wait manually */
++			amdgpu_ring_undo(other);
++			r = amdgpu_fence_wait(fence, false);
++			if (r)
++				return r;
++			continue;
++		}
++
++		amdgpu_ring_commit(other);
++		amdgpu_fence_note_sync(fence, ring);
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_sync_free - free the sync object
++ *
++ * @adev: amdgpu_device pointer
++ * @sync: sync object to use
++ * @fence: fence to use for the free
++ *
++ * Free the sync object by freeing all semaphores in it.
++ */
++void amdgpu_sync_free(struct amdgpu_device *adev,
++		      struct amdgpu_sync *sync,
++		      struct amdgpu_fence *fence)
++{
++	unsigned i;
++
++	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
++		amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
++		amdgpu_fence_unref(&sync->sync_to[i]);
++
++	amdgpu_fence_unref(&sync->last_vm_update);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+new file mode 100644
+index 0000000..df20299
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+@@ -0,0 +1,552 @@
++/*
++ * Copyright 2009 VMware, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Michel Dänzer
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_uvd.h"
++#include "amdgpu_vce.h"
++
++/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
++static void amdgpu_do_test_moves(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
++	struct amdgpu_bo *vram_obj = NULL;
++	struct amdgpu_bo **gtt_obj = NULL;
++	uint64_t gtt_addr, vram_addr;
++	unsigned n, size;
++	int i, r;
++
++	size = 1024 * 1024;
++
++	/* Number of tests =
++	 * (Total GTT - IB pool - writeback page - ring buffers) / test size
++	 */
++	n = adev->mc.gtt_size - AMDGPU_IB_POOL_SIZE*64*1024;
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
++		if (adev->rings[i])
++			n -= adev->rings[i]->ring_size;
++	if (adev->wb.wb_obj)
++		n -= AMDGPU_GPU_PAGE_SIZE;
++	if (adev->irq.ih.ring_obj)
++		n -= adev->irq.ih.ring_size;
++	n /= size;
++
++	gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
++	if (!gtt_obj) {
++		DRM_ERROR("Failed to allocate %d pointers\n", n);
++		r = 1;
++		goto out_cleanup;
++	}
++
++	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0,
++			     NULL, &vram_obj);
++	if (r) {
++		DRM_ERROR("Failed to create VRAM object\n");
++		goto out_cleanup;
++	}
++	r = amdgpu_bo_reserve(vram_obj, false);
++	if (unlikely(r != 0))
++		goto out_unref;
++	r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM, &vram_addr);
++	if (r) {
++		DRM_ERROR("Failed to pin VRAM object\n");
++		goto out_unres;
++	}
++	for (i = 0; i < n; i++) {
++		void *gtt_map, *vram_map;
++		void **gtt_start, **gtt_end;
++		void **vram_start, **vram_end;
++		struct amdgpu_fence *fence = NULL;
++
++		r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_GTT, 0, NULL, gtt_obj + i);
++		if (r) {
++			DRM_ERROR("Failed to create GTT object %d\n", i);
++			goto out_lclean;
++		}
++
++		r = amdgpu_bo_reserve(gtt_obj[i], false);
++		if (unlikely(r != 0))
++			goto out_lclean_unref;
++		r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT, &gtt_addr);
++		if (r) {
++			DRM_ERROR("Failed to pin GTT object %d\n", i);
++			goto out_lclean_unres;
++		}
++
++		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
++		if (r) {
++			DRM_ERROR("Failed to map GTT object %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		for (gtt_start = gtt_map, gtt_end = gtt_map + size;
++		     gtt_start < gtt_end;
++		     gtt_start++)
++			*gtt_start = gtt_start;
++
++		amdgpu_bo_kunmap(gtt_obj[i]);
++
++		r = amdgpu_copy_buffer(ring, gtt_addr, vram_addr,
++				       size, NULL, &fence);
++
++		if (r) {
++			DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		r = amdgpu_fence_wait(fence, false);
++		if (r) {
++			DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		amdgpu_fence_unref(&fence);
++
++		r = amdgpu_bo_kmap(vram_obj, &vram_map);
++		if (r) {
++			DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		for (gtt_start = gtt_map, gtt_end = gtt_map + size,
++		     vram_start = vram_map, vram_end = vram_map + size;
++		     vram_start < vram_end;
++		     gtt_start++, vram_start++) {
++			if (*vram_start != gtt_start) {
++				DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
++					  "expected 0x%p (GTT/VRAM offset "
++					  "0x%16llx/0x%16llx)\n",
++					  i, *vram_start, gtt_start,
++					  (unsigned long long)
++					  (gtt_addr - adev->mc.gtt_start +
++					   (void*)gtt_start - gtt_map),
++					  (unsigned long long)
++					  (vram_addr - adev->mc.vram_start +
++					   (void*)gtt_start - gtt_map));
++				amdgpu_bo_kunmap(vram_obj);
++				goto out_lclean_unpin;
++			}
++			*vram_start = vram_start;
++		}
++
++		amdgpu_bo_kunmap(vram_obj);
++
++		r = amdgpu_copy_buffer(ring, vram_addr, gtt_addr,
++				       size, NULL, &fence);
++
++		if (r) {
++			DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		r = amdgpu_fence_wait(fence, false);
++		if (r) {
++			DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		amdgpu_fence_unref(&fence);
++
++		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
++		if (r) {
++			DRM_ERROR("Failed to map GTT object after copy %d\n", i);
++			goto out_lclean_unpin;
++		}
++
++		for (gtt_start = gtt_map, gtt_end = gtt_map + size,
++		     vram_start = vram_map, vram_end = vram_map + size;
++		     gtt_start < gtt_end;
++		     gtt_start++, vram_start++) {
++			if (*gtt_start != vram_start) {
++				DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
++					  "expected 0x%p (VRAM/GTT offset "
++					  "0x%16llx/0x%16llx)\n",
++					  i, *gtt_start, vram_start,
++					  (unsigned long long)
++					  (vram_addr - adev->mc.vram_start +
++					   (void*)vram_start - vram_map),
++					  (unsigned long long)
++					  (gtt_addr - adev->mc.gtt_start +
++					   (void*)vram_start - vram_map));
++				amdgpu_bo_kunmap(gtt_obj[i]);
++				goto out_lclean_unpin;
++			}
++		}
++
++		amdgpu_bo_kunmap(gtt_obj[i]);
++
++		DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
++			 gtt_addr - adev->mc.gtt_start);
++		continue;
++
++out_lclean_unpin:
++		amdgpu_bo_unpin(gtt_obj[i]);
++out_lclean_unres:
++		amdgpu_bo_unreserve(gtt_obj[i]);
++out_lclean_unref:
++		amdgpu_bo_unref(&gtt_obj[i]);
++out_lclean:
++		for (--i; i >= 0; --i) {
++			amdgpu_bo_unpin(gtt_obj[i]);
++			amdgpu_bo_unreserve(gtt_obj[i]);
++			amdgpu_bo_unref(&gtt_obj[i]);
++		}
++		if (fence)
++			amdgpu_fence_unref(&fence);
++		break;
++	}
++
++	amdgpu_bo_unpin(vram_obj);
++out_unres:
++	amdgpu_bo_unreserve(vram_obj);
++out_unref:
++	amdgpu_bo_unref(&vram_obj);
++out_cleanup:
++	kfree(gtt_obj);
++	if (r) {
++		printk(KERN_WARNING "Error while testing BO move.\n");
++	}
++}
++
++void amdgpu_test_moves(struct amdgpu_device *adev)
++{
++	if (adev->mman.buffer_funcs)
++		amdgpu_do_test_moves(adev);
++}
++
++static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev,
++					     struct amdgpu_ring *ring,
++					     struct amdgpu_fence **fence)
++{
++	uint32_t handle = ring->idx ^ 0xdeafbeef;
++	int r;
++
++	if (ring == &adev->uvd.ring) {
++		r = amdgpu_uvd_get_create_msg(ring, handle, NULL);
++		if (r) {
++			DRM_ERROR("Failed to get dummy create msg\n");
++			return r;
++		}
++
++		r = amdgpu_uvd_get_destroy_msg(ring, handle, fence);
++		if (r) {
++			DRM_ERROR("Failed to get dummy destroy msg\n");
++			return r;
++		}
++
++	} else if (ring == &adev->vce.ring[0] ||
++		   ring == &adev->vce.ring[1]) {
++		r = amdgpu_vce_get_create_msg(ring, handle, NULL);
++		if (r) {
++			DRM_ERROR("Failed to get dummy create msg\n");
++			return r;
++		}
++
++		r = amdgpu_vce_get_destroy_msg(ring, handle, fence);
++		if (r) {
++			DRM_ERROR("Failed to get dummy destroy msg\n");
++			return r;
++		}
++
++	} else {
++		r = amdgpu_ring_lock(ring, 64);
++		if (r) {
++			DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
++			return r;
++		}
++		amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, fence);
++		amdgpu_ring_unlock_commit(ring);
++	}
++	return 0;
++}
++
++void amdgpu_test_ring_sync(struct amdgpu_device *adev,
++			   struct amdgpu_ring *ringA,
++			   struct amdgpu_ring *ringB)
++{
++	struct amdgpu_fence *fence1 = NULL, *fence2 = NULL;
++	struct amdgpu_semaphore *semaphore = NULL;
++	int r;
++
++	r = amdgpu_semaphore_create(adev, &semaphore);
++	if (r) {
++		DRM_ERROR("Failed to create semaphore\n");
++		goto out_cleanup;
++	}
++
++	r = amdgpu_ring_lock(ringA, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_wait(ringA, semaphore);
++	amdgpu_ring_unlock_commit(ringA);
++
++	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1);
++	if (r)
++		goto out_cleanup;
++
++	r = amdgpu_ring_lock(ringA, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_wait(ringA, semaphore);
++	amdgpu_ring_unlock_commit(ringA);
++
++	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2);
++	if (r)
++		goto out_cleanup;
++
++	mdelay(1000);
++
++	if (amdgpu_fence_signaled(fence1)) {
++		DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
++		goto out_cleanup;
++	}
++
++	r = amdgpu_ring_lock(ringB, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring B %p\n", ringB);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_signal(ringB, semaphore);
++	amdgpu_ring_unlock_commit(ringB);
++
++	r = amdgpu_fence_wait(fence1, false);
++	if (r) {
++		DRM_ERROR("Failed to wait for sync fence 1\n");
++		goto out_cleanup;
++	}
++
++	mdelay(1000);
++
++	if (amdgpu_fence_signaled(fence2)) {
++		DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
++		goto out_cleanup;
++	}
++
++	r = amdgpu_ring_lock(ringB, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring B %p\n", ringB);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_signal(ringB, semaphore);
++	amdgpu_ring_unlock_commit(ringB);
++
++	r = amdgpu_fence_wait(fence2, false);
++	if (r) {
++		DRM_ERROR("Failed to wait for sync fence 1\n");
++		goto out_cleanup;
++	}
++
++out_cleanup:
++	amdgpu_semaphore_free(adev, &semaphore, NULL);
++
++	if (fence1)
++		amdgpu_fence_unref(&fence1);
++
++	if (fence2)
++		amdgpu_fence_unref(&fence2);
++
++	if (r)
++		printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
++}
++
++static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
++			    struct amdgpu_ring *ringA,
++			    struct amdgpu_ring *ringB,
++			    struct amdgpu_ring *ringC)
++{
++	struct amdgpu_fence *fenceA = NULL, *fenceB = NULL;
++	struct amdgpu_semaphore *semaphore = NULL;
++	bool sigA, sigB;
++	int i, r;
++
++	r = amdgpu_semaphore_create(adev, &semaphore);
++	if (r) {
++		DRM_ERROR("Failed to create semaphore\n");
++		goto out_cleanup;
++	}
++
++	r = amdgpu_ring_lock(ringA, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_wait(ringA, semaphore);
++	amdgpu_ring_unlock_commit(ringA);
++
++	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA);
++	if (r)
++		goto out_cleanup;
++
++	r = amdgpu_ring_lock(ringB, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_wait(ringB, semaphore);
++	amdgpu_ring_unlock_commit(ringB);
++	r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB);
++	if (r)
++		goto out_cleanup;
++
++	mdelay(1000);
++
++	if (amdgpu_fence_signaled(fenceA)) {
++		DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
++		goto out_cleanup;
++	}
++	if (amdgpu_fence_signaled(fenceB)) {
++		DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
++		goto out_cleanup;
++	}
++
++	r = amdgpu_ring_lock(ringC, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring B %p\n", ringC);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_signal(ringC, semaphore);
++	amdgpu_ring_unlock_commit(ringC);
++
++	for (i = 0; i < 30; ++i) {
++		mdelay(100);
++		sigA = amdgpu_fence_signaled(fenceA);
++		sigB = amdgpu_fence_signaled(fenceB);
++		if (sigA || sigB)
++			break;
++	}
++
++	if (!sigA && !sigB) {
++		DRM_ERROR("Neither fence A nor B has been signaled\n");
++		goto out_cleanup;
++	} else if (sigA && sigB) {
++		DRM_ERROR("Both fence A and B has been signaled\n");
++		goto out_cleanup;
++	}
++
++	DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
++
++	r = amdgpu_ring_lock(ringC, 64);
++	if (r) {
++		DRM_ERROR("Failed to lock ring B %p\n", ringC);
++		goto out_cleanup;
++	}
++	amdgpu_semaphore_emit_signal(ringC, semaphore);
++	amdgpu_ring_unlock_commit(ringC);
++
++	mdelay(1000);
++
++	r = amdgpu_fence_wait(fenceA, false);
++	if (r) {
++		DRM_ERROR("Failed to wait for sync fence A\n");
++		goto out_cleanup;
++	}
++	r = amdgpu_fence_wait(fenceB, false);
++	if (r) {
++		DRM_ERROR("Failed to wait for sync fence B\n");
++		goto out_cleanup;
++	}
++
++out_cleanup:
++	amdgpu_semaphore_free(adev, &semaphore, NULL);
++
++	if (fenceA)
++		amdgpu_fence_unref(&fenceA);
++
++	if (fenceB)
++		amdgpu_fence_unref(&fenceB);
++
++	if (r)
++		printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
++}
++
++static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA,
++				      struct amdgpu_ring *ringB)
++{
++	if (ringA == &ringA->adev->vce.ring[0] &&
++	    ringB == &ringB->adev->vce.ring[1])
++		return false;
++
++	return true;
++}
++
++void amdgpu_test_syncing(struct amdgpu_device *adev)
++{
++	int i, j, k;
++
++	for (i = 1; i < AMDGPU_MAX_RINGS; ++i) {
++		struct amdgpu_ring *ringA = adev->rings[i];
++		if (!ringA || !ringA->ready)
++			continue;
++
++		for (j = 0; j < i; ++j) {
++			struct amdgpu_ring *ringB = adev->rings[j];
++			if (!ringB || !ringB->ready)
++				continue;
++
++			if (!amdgpu_test_sync_possible(ringA, ringB))
++				continue;
++
++			DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
++			amdgpu_test_ring_sync(adev, ringA, ringB);
++
++			DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
++			amdgpu_test_ring_sync(adev, ringB, ringA);
++
++			for (k = 0; k < j; ++k) {
++				struct amdgpu_ring *ringC = adev->rings[k];
++				if (!ringC || !ringC->ready)
++					continue;
++
++				if (!amdgpu_test_sync_possible(ringA, ringC))
++					continue;
++
++				if (!amdgpu_test_sync_possible(ringB, ringC))
++					continue;
++
++				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
++				amdgpu_test_ring_sync2(adev, ringA, ringB, ringC);
++
++				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
++				amdgpu_test_ring_sync2(adev, ringA, ringC, ringB);
++
++				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
++				amdgpu_test_ring_sync2(adev, ringB, ringA, ringC);
++
++				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
++				amdgpu_test_ring_sync2(adev, ringB, ringC, ringA);
++
++				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
++				amdgpu_test_ring_sync2(adev, ringC, ringA, ringB);
++
++				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
++				amdgpu_test_ring_sync2(adev, ringC, ringB, ringA);
++			}
++		}
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+new file mode 100644
+index 0000000..b57647e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+@@ -0,0 +1,209 @@
++#if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _AMDGPU_TRACE_H_
++
++#include <linux/stringify.h>
++#include <linux/types.h>
++#include <linux/tracepoint.h>
++
++#include <drm/drmP.h>
++
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM amdgpu
++#define TRACE_SYSTEM_STRING __stringify(TRACE_SYSTEM)
++#define TRACE_INCLUDE_FILE amdgpu_trace
++
++TRACE_EVENT(amdgpu_bo_create,
++	    TP_PROTO(struct amdgpu_bo *bo),
++	    TP_ARGS(bo),
++	    TP_STRUCT__entry(
++			     __field(struct amdgpu_bo *, bo)
++			     __field(u32, pages)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->bo = bo;
++			   __entry->pages = bo->tbo.num_pages;
++			   ),
++	    TP_printk("bo=%p, pages=%u", __entry->bo, __entry->pages)
++);
++
++TRACE_EVENT(amdgpu_cs,
++	    TP_PROTO(struct amdgpu_cs_parser *p, int i),
++	    TP_ARGS(p, i),
++	    TP_STRUCT__entry(
++			     __field(u32, ring)
++			     __field(u32, dw)
++			     __field(u32, fences)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->ring = p->ibs[i].ring->idx;
++			   __entry->dw = p->ibs[i].length_dw;
++			   __entry->fences = amdgpu_fence_count_emitted(
++				p->ibs[i].ring);
++			   ),
++	    TP_printk("ring=%u, dw=%u, fences=%u",
++		      __entry->ring, __entry->dw,
++		      __entry->fences)
++);
++
++TRACE_EVENT(amdgpu_vm_grab_id,
++	    TP_PROTO(unsigned vmid, int ring),
++	    TP_ARGS(vmid, ring),
++	    TP_STRUCT__entry(
++			     __field(u32, vmid)
++			     __field(u32, ring)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->vmid = vmid;
++			   __entry->ring = ring;
++			   ),
++	    TP_printk("vmid=%u, ring=%u", __entry->vmid, __entry->ring)
++);
++
++TRACE_EVENT(amdgpu_vm_bo_update,
++	    TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
++	    TP_ARGS(mapping),
++	    TP_STRUCT__entry(
++			     __field(u64, soffset)
++			     __field(u64, eoffset)
++			     __field(u32, flags)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->soffset = mapping->it.start;
++			   __entry->eoffset = mapping->it.last + 1;
++			   __entry->flags = mapping->flags;
++			   ),
++	    TP_printk("soffs=%010llx, eoffs=%010llx, flags=%08x",
++		      __entry->soffset, __entry->eoffset, __entry->flags)
++);
++
++TRACE_EVENT(amdgpu_vm_set_page,
++	    TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
++		     uint32_t incr, uint32_t flags),
++	    TP_ARGS(pe, addr, count, incr, flags),
++	    TP_STRUCT__entry(
++			     __field(u64, pe)
++			     __field(u64, addr)
++			     __field(u32, count)
++			     __field(u32, incr)
++			     __field(u32, flags)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->pe = pe;
++			   __entry->addr = addr;
++			   __entry->count = count;
++			   __entry->incr = incr;
++			   __entry->flags = flags;
++			   ),
++	    TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u",
++		      __entry->pe, __entry->addr, __entry->incr,
++		      __entry->flags, __entry->count)
++);
++
++TRACE_EVENT(amdgpu_vm_flush,
++	    TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id),
++	    TP_ARGS(pd_addr, ring, id),
++	    TP_STRUCT__entry(
++			     __field(u64, pd_addr)
++			     __field(u32, ring)
++			     __field(u32, id)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->pd_addr = pd_addr;
++			   __entry->ring = ring;
++			   __entry->id = id;
++			   ),
++	    TP_printk("pd_addr=%010Lx, ring=%u, id=%u",
++		      __entry->pd_addr, __entry->ring, __entry->id)
++);
++
++DECLARE_EVENT_CLASS(amdgpu_fence_request,
++
++	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
++
++	    TP_ARGS(dev, ring, seqno),
++
++	    TP_STRUCT__entry(
++			     __field(u32, dev)
++			     __field(int, ring)
++			     __field(u32, seqno)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->dev = dev->primary->index;
++			   __entry->ring = ring;
++			   __entry->seqno = seqno;
++			   ),
++
++	    TP_printk("dev=%u, ring=%d, seqno=%u",
++		      __entry->dev, __entry->ring, __entry->seqno)
++);
++
++DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_emit,
++
++	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
++
++	    TP_ARGS(dev, ring, seqno)
++);
++
++DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_wait_begin,
++
++	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
++
++	    TP_ARGS(dev, ring, seqno)
++);
++
++DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_wait_end,
++
++	    TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
++
++	    TP_ARGS(dev, ring, seqno)
++);
++
++DECLARE_EVENT_CLASS(amdgpu_semaphore_request,
++
++	    TP_PROTO(int ring, struct amdgpu_semaphore *sem),
++
++	    TP_ARGS(ring, sem),
++
++	    TP_STRUCT__entry(
++			     __field(int, ring)
++			     __field(signed, waiters)
++			     __field(uint64_t, gpu_addr)
++			     ),
++
++	    TP_fast_assign(
++			   __entry->ring = ring;
++			   __entry->waiters = sem->waiters;
++			   __entry->gpu_addr = sem->gpu_addr;
++			   ),
++
++	    TP_printk("ring=%u, waiters=%d, addr=%010Lx", __entry->ring,
++		      __entry->waiters, __entry->gpu_addr)
++);
++
++DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_signale,
++
++	    TP_PROTO(int ring, struct amdgpu_semaphore *sem),
++
++	    TP_ARGS(ring, sem)
++);
++
++DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_wait,
++
++	    TP_PROTO(int ring, struct amdgpu_semaphore *sem),
++
++	    TP_ARGS(ring, sem)
++);
++
++#endif
++
++/* This part must be outside protection */
++#undef TRACE_INCLUDE_PATH
++#define TRACE_INCLUDE_PATH .
++#include <trace/define_trace.h>
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
+new file mode 100644
+index 0000000..385b7e1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
+@@ -0,0 +1,9 @@
++/* Copyright Red Hat Inc 2010.
++ * Author : Dave Airlie <airlied@redhat.com>
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++#define CREATE_TRACE_POINTS
++#include "amdgpu_trace.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+new file mode 100644
+index 0000000..120e6e7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -0,0 +1,1249 @@
++/*
++ * Copyright 2009 Jerome Glisse.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Jerome Glisse <glisse@freedesktop.org>
++ *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
++ *    Dave Airlie
++ */
++#include <ttm/ttm_bo_api.h>
++#include <ttm/ttm_bo_driver.h>
++#include <ttm/ttm_placement.h>
++#include <ttm/ttm_module.h>
++#include <ttm/ttm_page_alloc.h>
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include <linux/seq_file.h>
++#include <linux/slab.h>
++#include <linux/swiotlb.h>
++#include <linux/swap.h>
++#include <linux/pagemap.h>
++#include <linux/debugfs.h>
++#include "amdgpu.h"
++#include "bif/bif_4_1_d.h"
++
++#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
++
++static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
++static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
++
++static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
++{
++	struct amdgpu_mman *mman;
++	struct amdgpu_device *adev;
++
++	mman = container_of(bdev, struct amdgpu_mman, bdev);
++	adev = container_of(mman, struct amdgpu_device, mman);
++	return adev;
++}
++
++
++/*
++ * Global memory.
++ */
++static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
++{
++	return ttm_mem_global_init(ref->object);
++}
++
++static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
++{
++	ttm_mem_global_release(ref->object);
++}
++
++static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
++{
++	struct drm_global_reference *global_ref;
++	int r;
++
++	adev->mman.mem_global_referenced = false;
++	global_ref = &adev->mman.mem_global_ref;
++	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
++	global_ref->size = sizeof(struct ttm_mem_global);
++	global_ref->init = &amdgpu_ttm_mem_global_init;
++	global_ref->release = &amdgpu_ttm_mem_global_release;
++	r = drm_global_item_ref(global_ref);
++	if (r != 0) {
++		DRM_ERROR("Failed setting up TTM memory accounting "
++			  "subsystem.\n");
++		return r;
++	}
++
++	adev->mman.bo_global_ref.mem_glob =
++		adev->mman.mem_global_ref.object;
++	global_ref = &adev->mman.bo_global_ref.ref;
++	global_ref->global_type = DRM_GLOBAL_TTM_BO;
++	global_ref->size = sizeof(struct ttm_bo_global);
++	global_ref->init = &ttm_bo_global_init;
++	global_ref->release = &ttm_bo_global_release;
++	r = drm_global_item_ref(global_ref);
++	if (r != 0) {
++		DRM_ERROR("Failed setting up TTM BO subsystem.\n");
++		drm_global_item_unref(&adev->mman.mem_global_ref);
++		return r;
++	}
++
++	adev->mman.mem_global_referenced = true;
++	return 0;
++}
++
++static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
++{
++	if (adev->mman.mem_global_referenced) {
++		drm_global_item_unref(&adev->mman.bo_global_ref.ref);
++		drm_global_item_unref(&adev->mman.mem_global_ref);
++		adev->mman.mem_global_referenced = false;
++	}
++}
++
++static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
++{
++	return 0;
++}
++
++static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
++				struct ttm_mem_type_manager *man)
++{
++	struct amdgpu_device *adev;
++
++	adev = amdgpu_get_adev(bdev);
++
++	switch (type) {
++	case TTM_PL_SYSTEM:
++		/* System memory */
++		man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
++		man->available_caching = TTM_PL_MASK_CACHING;
++		man->default_caching = TTM_PL_FLAG_CACHED;
++		break;
++	case TTM_PL_TT:
++		man->func = &ttm_bo_manager_func;
++		man->gpu_offset = adev->mc.gtt_start;
++		man->available_caching = TTM_PL_MASK_CACHING;
++		man->default_caching = TTM_PL_FLAG_CACHED;
++		man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
++		break;
++	case TTM_PL_VRAM:
++		/* "On-card" video ram */
++		man->func = &ttm_bo_manager_func;
++		man->gpu_offset = adev->mc.vram_start;
++		man->flags = TTM_MEMTYPE_FLAG_FIXED |
++			     TTM_MEMTYPE_FLAG_MAPPABLE;
++		man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
++		man->default_caching = TTM_PL_FLAG_WC;
++		break;
++	case AMDGPU_PL_GDS:
++	case AMDGPU_PL_GWS:
++	case AMDGPU_PL_OA:
++		/* On-chip GDS memory*/
++		man->func = &ttm_bo_manager_func;
++		man->gpu_offset = 0;
++		man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
++		man->available_caching = TTM_PL_FLAG_UNCACHED;
++		man->default_caching = TTM_PL_FLAG_UNCACHED;
++		break;
++	default:
++		DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
++				struct ttm_placement *placement)
++{
++	struct amdgpu_bo *rbo;
++	static struct ttm_place placements = {
++		.fpfn = 0,
++		.lpfn = 0,
++		.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
++	};
++
++	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
++		placement->placement = &placements;
++		placement->busy_placement = &placements;
++		placement->num_placement = 1;
++		placement->num_busy_placement = 1;
++		return;
++	}
++	rbo = container_of(bo, struct amdgpu_bo, tbo);
++	switch (bo->mem.mem_type) {
++	case TTM_PL_VRAM:
++		if (rbo->adev->mman.buffer_funcs_ring->ready == false)
++			amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
++		else
++			amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
++		break;
++	case TTM_PL_TT:
++	default:
++		amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
++	}
++	*placement = rbo->placement;
++}
++
++static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
++{
++	struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
++
++	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
++}
++
++static void amdgpu_move_null(struct ttm_buffer_object *bo,
++			     struct ttm_mem_reg *new_mem)
++{
++	struct ttm_mem_reg *old_mem = &bo->mem;
++
++	BUG_ON(old_mem->mm_node != NULL);
++	*old_mem = *new_mem;
++	new_mem->mm_node = NULL;
++}
++
++static int amdgpu_move_blit(struct ttm_buffer_object *bo,
++			bool evict, bool no_wait_gpu,
++			struct ttm_mem_reg *new_mem,
++			struct ttm_mem_reg *old_mem)
++{
++	struct amdgpu_device *adev;
++	struct amdgpu_ring *ring;
++	uint64_t old_start, new_start;
++	struct amdgpu_fence *fence;
++	int r;
++
++	adev = amdgpu_get_adev(bo->bdev);
++	ring = adev->mman.buffer_funcs_ring;
++	old_start = old_mem->start << PAGE_SHIFT;
++	new_start = new_mem->start << PAGE_SHIFT;
++
++	switch (old_mem->mem_type) {
++	case TTM_PL_VRAM:
++		old_start += adev->mc.vram_start;
++		break;
++	case TTM_PL_TT:
++		old_start += adev->mc.gtt_start;
++		break;
++	default:
++		DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
++		return -EINVAL;
++	}
++	switch (new_mem->mem_type) {
++	case TTM_PL_VRAM:
++		new_start += adev->mc.vram_start;
++		break;
++	case TTM_PL_TT:
++		new_start += adev->mc.gtt_start;
++		break;
++	default:
++		DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
++		return -EINVAL;
++	}
++	if (!ring->ready) {
++		DRM_ERROR("Trying to move memory with ring turned off.\n");
++		return -EINVAL;
++	}
++
++	BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
++
++	r = amdgpu_copy_buffer(ring, old_start, new_start,
++			       new_mem->num_pages * PAGE_SIZE, /* bytes */
++			       bo->resv, &fence);
++	/* FIXME: handle copy error */
++	r = ttm_bo_move_accel_cleanup(bo, &fence->base,
++				      evict, no_wait_gpu, new_mem);
++	amdgpu_fence_unref(&fence);
++	return r;
++}
++
++static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
++				bool evict, bool interruptible,
++				bool no_wait_gpu,
++				struct ttm_mem_reg *new_mem)
++{
++	struct amdgpu_device *adev;
++	struct ttm_mem_reg *old_mem = &bo->mem;
++	struct ttm_mem_reg tmp_mem;
++	struct ttm_place placements;
++	struct ttm_placement placement;
++	int r;
++
++	adev = amdgpu_get_adev(bo->bdev);
++	tmp_mem = *new_mem;
++	tmp_mem.mm_node = NULL;
++	placement.num_placement = 1;
++	placement.placement = &placements;
++	placement.num_busy_placement = 1;
++	placement.busy_placement = &placements;
++	placements.fpfn = 0;
++	placements.lpfn = 0;
++	placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
++	r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
++			     interruptible, no_wait_gpu);
++	if (unlikely(r)) {
++		return r;
++	}
++
++	r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
++	if (unlikely(r)) {
++		goto out_cleanup;
++	}
++
++	r = ttm_tt_bind(bo->ttm, &tmp_mem);
++	if (unlikely(r)) {
++		goto out_cleanup;
++	}
++	r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
++	if (unlikely(r)) {
++		goto out_cleanup;
++	}
++	r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
++out_cleanup:
++	ttm_bo_mem_put(bo, &tmp_mem);
++	return r;
++}
++
++static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
++				bool evict, bool interruptible,
++				bool no_wait_gpu,
++				struct ttm_mem_reg *new_mem)
++{
++	struct amdgpu_device *adev;
++	struct ttm_mem_reg *old_mem = &bo->mem;
++	struct ttm_mem_reg tmp_mem;
++	struct ttm_placement placement;
++	struct ttm_place placements;
++	int r;
++
++	adev = amdgpu_get_adev(bo->bdev);
++	tmp_mem = *new_mem;
++	tmp_mem.mm_node = NULL;
++	placement.num_placement = 1;
++	placement.placement = &placements;
++	placement.num_busy_placement = 1;
++	placement.busy_placement = &placements;
++	placements.fpfn = 0;
++	placements.lpfn = 0;
++	placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
++	r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
++			     interruptible, no_wait_gpu);
++	if (unlikely(r)) {
++		return r;
++	}
++	r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
++	if (unlikely(r)) {
++		goto out_cleanup;
++	}
++	r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
++	if (unlikely(r)) {
++		goto out_cleanup;
++	}
++out_cleanup:
++	ttm_bo_mem_put(bo, &tmp_mem);
++	return r;
++}
++
++static int amdgpu_bo_move(struct ttm_buffer_object *bo,
++			bool evict, bool interruptible,
++			bool no_wait_gpu,
++			struct ttm_mem_reg *new_mem)
++{
++	struct amdgpu_device *adev;
++	struct ttm_mem_reg *old_mem = &bo->mem;
++	int r;
++
++	adev = amdgpu_get_adev(bo->bdev);
++	if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
++		amdgpu_move_null(bo, new_mem);
++		return 0;
++	}
++	if ((old_mem->mem_type == TTM_PL_TT &&
++	     new_mem->mem_type == TTM_PL_SYSTEM) ||
++	    (old_mem->mem_type == TTM_PL_SYSTEM &&
++	     new_mem->mem_type == TTM_PL_TT)) {
++		/* bind is enough */
++		amdgpu_move_null(bo, new_mem);
++		return 0;
++	}
++	if (adev->mman.buffer_funcs == NULL ||
++	    adev->mman.buffer_funcs_ring == NULL ||
++	    !adev->mman.buffer_funcs_ring->ready) {
++		/* use memcpy */
++		goto memcpy;
++	}
++
++	if (old_mem->mem_type == TTM_PL_VRAM &&
++	    new_mem->mem_type == TTM_PL_SYSTEM) {
++		r = amdgpu_move_vram_ram(bo, evict, interruptible,
++					no_wait_gpu, new_mem);
++	} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
++		   new_mem->mem_type == TTM_PL_VRAM) {
++		r = amdgpu_move_ram_vram(bo, evict, interruptible,
++					    no_wait_gpu, new_mem);
++	} else {
++		r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
++	}
++
++	if (r) {
++memcpy:
++		r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
++		if (r) {
++			return r;
++		}
++	}
++
++	/* update statistics */
++	atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
++	return 0;
++}
++
++static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
++{
++	struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
++	struct amdgpu_device *adev = amdgpu_get_adev(bdev);
++
++	mem->bus.addr = NULL;
++	mem->bus.offset = 0;
++	mem->bus.size = mem->num_pages << PAGE_SHIFT;
++	mem->bus.base = 0;
++	mem->bus.is_iomem = false;
++	if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
++		return -EINVAL;
++	switch (mem->mem_type) {
++	case TTM_PL_SYSTEM:
++		/* system memory */
++		return 0;
++	case TTM_PL_TT:
++		break;
++	case TTM_PL_VRAM:
++		mem->bus.offset = mem->start << PAGE_SHIFT;
++		/* check if it's visible */
++		if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
++			return -EINVAL;
++		mem->bus.base = adev->mc.aper_base;
++		mem->bus.is_iomem = true;
++#ifdef __alpha__
++		/*
++		 * Alpha: use bus.addr to hold the ioremap() return,
++		 * so we can modify bus.base below.
++		 */
++		if (mem->placement & TTM_PL_FLAG_WC)
++			mem->bus.addr =
++				ioremap_wc(mem->bus.base + mem->bus.offset,
++					   mem->bus.size);
++		else
++			mem->bus.addr =
++				ioremap_nocache(mem->bus.base + mem->bus.offset,
++						mem->bus.size);
++
++		/*
++		 * Alpha: Use just the bus offset plus
++		 * the hose/domain memory base for bus.base.
++		 * It then can be used to build PTEs for VRAM
++		 * access, as done in ttm_bo_vm_fault().
++		 */
++		mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
++			adev->ddev->hose->dense_mem_base;
++#endif
++		break;
++	default:
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
++{
++}
++
++/*
++ * TTM backend functions.
++ */
++struct amdgpu_ttm_tt {
++	struct ttm_dma_tt		ttm;
++	struct amdgpu_device		*adev;
++	u64				offset;
++	uint64_t			userptr;
++	struct mm_struct		*usermm;
++	uint32_t			userflags;
++};
++
++/* prepare the sg table with the user pages */
++static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
++{
++	struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++	unsigned pinned = 0, nents;
++	int r;
++
++	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
++	enum dma_data_direction direction = write ?
++		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
++
++	if (current->mm != gtt->usermm)
++		return -EPERM;
++
++	if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
++		/* check that we only pin down anonymous memory
++		   to prevent problems with writeback */
++		unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
++		struct vm_area_struct *vma;
++
++		vma = find_vma(gtt->usermm, gtt->userptr);
++		if (!vma || vma->vm_file || vma->vm_end < end)
++			return -EPERM;
++	}
++
++	do {
++		unsigned num_pages = ttm->num_pages - pinned;
++		uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
++		struct page **pages = ttm->pages + pinned;
++
++		r = get_user_pages(current, current->mm, userptr, num_pages,
++				   write, 0, pages, NULL);
++		if (r < 0)
++			goto release_pages;
++
++		pinned += r;
++
++	} while (pinned < ttm->num_pages);
++
++	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
++				      ttm->num_pages << PAGE_SHIFT,
++				      GFP_KERNEL);
++	if (r)
++		goto release_sg;
++
++	r = -ENOMEM;
++	nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
++	if (nents != ttm->sg->nents)
++		goto release_sg;
++
++	drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
++					 gtt->ttm.dma_address, ttm->num_pages);
++
++	return 0;
++
++release_sg:
++	kfree(ttm->sg);
++
++release_pages:
++	release_pages(ttm->pages, pinned, 0);
++	return r;
++}
++
++static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
++{
++	struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++	struct scatterlist *sg;
++	int i;
++
++	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
++	enum dma_data_direction direction = write ?
++		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
++
++	/* double check that we don't free the table twice */
++	if (!ttm->sg->sgl)
++		return;
++
++	/* free the sg table and pages again */
++	dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
++
++	for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) {
++		struct page *page = sg_page(sg);
++
++		if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
++			set_page_dirty(page);
++
++		mark_page_accessed(page);
++		page_cache_release(page);
++	}
++
++	sg_free_table(ttm->sg);
++}
++
++static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
++				   struct ttm_mem_reg *bo_mem)
++{
++	struct amdgpu_ttm_tt *gtt = (void*)ttm;
++	uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
++	int r;
++
++	if (gtt->userptr)
++		amdgpu_ttm_tt_pin_userptr(ttm);
++
++	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
++	if (!ttm->num_pages) {
++		WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
++		     ttm->num_pages, bo_mem, ttm);
++	}
++
++	if (bo_mem->mem_type == AMDGPU_PL_GDS ||
++	    bo_mem->mem_type == AMDGPU_PL_GWS ||
++	    bo_mem->mem_type == AMDGPU_PL_OA)
++		return -EINVAL;
++
++	r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
++		ttm->pages, gtt->ttm.dma_address, flags);
++
++	if (r) {
++		DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
++			  ttm->num_pages, (unsigned)gtt->offset);
++		return r;
++	}
++	return 0;
++}
++
++static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
++{
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++
++	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
++	if (gtt->adev->gart.ready)
++		amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
++
++	if (gtt->userptr)
++		amdgpu_ttm_tt_unpin_userptr(ttm);
++
++	return 0;
++}
++
++static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
++{
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++
++	ttm_dma_tt_fini(&gtt->ttm);
++	kfree(gtt);
++}
++
++static struct ttm_backend_func amdgpu_backend_func = {
++	.bind = &amdgpu_ttm_backend_bind,
++	.unbind = &amdgpu_ttm_backend_unbind,
++	.destroy = &amdgpu_ttm_backend_destroy,
++};
++
++static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
++				    unsigned long size, uint32_t page_flags,
++				    struct page *dummy_read_page)
++{
++	struct amdgpu_device *adev;
++	struct amdgpu_ttm_tt *gtt;
++
++	adev = amdgpu_get_adev(bdev);
++
++	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
++	if (gtt == NULL) {
++		return NULL;
++	}
++	gtt->ttm.ttm.func = &amdgpu_backend_func;
++	gtt->adev = adev;
++	if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
++		kfree(gtt);
++		return NULL;
++	}
++	return &gtt->ttm.ttm;
++}
++
++static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
++{
++	struct amdgpu_device *adev;
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++	unsigned i;
++	int r;
++	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
++
++	if (ttm->state != tt_unpopulated)
++		return 0;
++
++	if (gtt && gtt->userptr) {
++		ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL);
++		if (!ttm->sg)
++			return -ENOMEM;
++
++		ttm->page_flags |= TTM_PAGE_FLAG_SG;
++		ttm->state = tt_unbound;
++		return 0;
++	}
++
++	if (slave && ttm->sg) {
++		drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
++						 gtt->ttm.dma_address, ttm->num_pages);
++		ttm->state = tt_unbound;
++		return 0;
++	}
++
++	adev = amdgpu_get_adev(ttm->bdev);
++
++#ifdef CONFIG_SWIOTLB
++	if (swiotlb_nr_tbl()) {
++		return ttm_dma_populate(&gtt->ttm, adev->dev);
++	}
++#endif
++
++	r = ttm_pool_populate(ttm);
++	if (r) {
++		return r;
++	}
++
++	for (i = 0; i < ttm->num_pages; i++) {
++		gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
++						       0, PAGE_SIZE,
++						       PCI_DMA_BIDIRECTIONAL);
++		if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
++			while (--i) {
++				pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
++					       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
++				gtt->ttm.dma_address[i] = 0;
++			}
++			ttm_pool_unpopulate(ttm);
++			return -EFAULT;
++		}
++	}
++	return 0;
++}
++
++static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
++{
++	struct amdgpu_device *adev;
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++	unsigned i;
++	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
++
++	if (gtt && gtt->userptr) {
++		kfree(ttm->sg);
++		ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
++		return;
++	}
++
++	if (slave)
++		return;
++
++	adev = amdgpu_get_adev(ttm->bdev);
++
++#ifdef CONFIG_SWIOTLB
++	if (swiotlb_nr_tbl()) {
++		ttm_dma_unpopulate(&gtt->ttm, adev->dev);
++		return;
++	}
++#endif
++
++	for (i = 0; i < ttm->num_pages; i++) {
++		if (gtt->ttm.dma_address[i]) {
++			pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
++				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
++		}
++	}
++
++	ttm_pool_unpopulate(ttm);
++}
++
++int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
++			      uint32_t flags)
++{
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++
++	if (gtt == NULL)
++		return -EINVAL;
++
++	gtt->userptr = addr;
++	gtt->usermm = current->mm;
++	gtt->userflags = flags;
++	return 0;
++}
++
++bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
++{
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++
++	if (gtt == NULL)
++		return false;
++
++	return !!gtt->userptr;
++}
++
++bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
++{
++	struct amdgpu_ttm_tt *gtt = (void *)ttm;
++
++	if (gtt == NULL)
++		return false;
++
++	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
++}
++
++uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
++				 struct ttm_mem_reg *mem)
++{
++	uint32_t flags = 0;
++
++	if (mem && mem->mem_type != TTM_PL_SYSTEM)
++		flags |= AMDGPU_PTE_VALID;
++
++	if (mem && mem->mem_type == TTM_PL_TT)
++		flags |= AMDGPU_PTE_SYSTEM;
++
++	if (!ttm || ttm->caching_state == tt_cached)
++		flags |= AMDGPU_PTE_SNOOPED;
++
++	if (adev->asic_type >= CHIP_TOPAZ)
++		flags |= AMDGPU_PTE_EXECUTABLE;
++
++	flags |= AMDGPU_PTE_READABLE;
++
++	if (!amdgpu_ttm_tt_is_readonly(ttm))
++		flags |= AMDGPU_PTE_WRITEABLE;
++
++	return flags;
++}
++
++static struct ttm_bo_driver amdgpu_bo_driver = {
++	.ttm_tt_create = &amdgpu_ttm_tt_create,
++	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
++	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
++	.invalidate_caches = &amdgpu_invalidate_caches,
++	.init_mem_type = &amdgpu_init_mem_type,
++	.evict_flags = &amdgpu_evict_flags,
++	.move = &amdgpu_bo_move,
++	.verify_access = &amdgpu_verify_access,
++	.move_notify = &amdgpu_bo_move_notify,
++	.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
++	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
++	.io_mem_free = &amdgpu_ttm_io_mem_free,
++};
++
++int amdgpu_ttm_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_ttm_global_init(adev);
++	if (r) {
++		return r;
++	}
++	/* No others user of address space so set it to 0 */
++	r = ttm_bo_device_init(&adev->mman.bdev,
++			       adev->mman.bo_global_ref.ref.object,
++			       &amdgpu_bo_driver,
++			       adev->ddev->anon_inode->i_mapping,
++			       DRM_FILE_PAGE_OFFSET,
++			       adev->need_dma32);
++	if (r) {
++		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
++		return r;
++	}
++	adev->mman.initialized = true;
++	r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
++				adev->mc.real_vram_size >> PAGE_SHIFT);
++	if (r) {
++		DRM_ERROR("Failed initializing VRAM heap.\n");
++		return r;
++	}
++	/* Change the size here instead of the init above so only lpfn is affected */
++	amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
++
++	r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
++			     AMDGPU_GEM_DOMAIN_VRAM, 0,
++			     NULL, &adev->stollen_vga_memory);
++	if (r) {
++		return r;
++	}
++	r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
++	if (r)
++		return r;
++	r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
++	amdgpu_bo_unreserve(adev->stollen_vga_memory);
++	if (r) {
++		amdgpu_bo_unref(&adev->stollen_vga_memory);
++		return r;
++	}
++	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
++		 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
++	r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
++				adev->mc.gtt_size >> PAGE_SHIFT);
++	if (r) {
++		DRM_ERROR("Failed initializing GTT heap.\n");
++		return r;
++	}
++	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
++		 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
++
++	adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
++	adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
++	adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
++	adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
++	adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
++	adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
++	adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
++	adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
++	adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
++	/* GDS Memory */
++	r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
++				adev->gds.mem.total_size >> PAGE_SHIFT);
++	if (r) {
++		DRM_ERROR("Failed initializing GDS heap.\n");
++		return r;
++	}
++
++	/* GWS */
++	r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
++				adev->gds.gws.total_size >> PAGE_SHIFT);
++	if (r) {
++		DRM_ERROR("Failed initializing gws heap.\n");
++		return r;
++	}
++
++	/* OA */
++	r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
++				adev->gds.oa.total_size >> PAGE_SHIFT);
++	if (r) {
++		DRM_ERROR("Failed initializing oa heap.\n");
++		return r;
++	}
++
++	r = amdgpu_ttm_debugfs_init(adev);
++	if (r) {
++		DRM_ERROR("Failed to init debugfs\n");
++		return r;
++	}
++	return 0;
++}
++
++void amdgpu_ttm_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (!adev->mman.initialized)
++		return;
++	amdgpu_ttm_debugfs_fini(adev);
++	if (adev->stollen_vga_memory) {
++		r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
++		if (r == 0) {
++			amdgpu_bo_unpin(adev->stollen_vga_memory);
++			amdgpu_bo_unreserve(adev->stollen_vga_memory);
++		}
++		amdgpu_bo_unref(&adev->stollen_vga_memory);
++	}
++	ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
++	ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
++	ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
++	ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
++	ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
++	ttm_bo_device_release(&adev->mman.bdev);
++	amdgpu_gart_fini(adev);
++	amdgpu_ttm_global_fini(adev);
++	adev->mman.initialized = false;
++	DRM_INFO("amdgpu: ttm finalized\n");
++}
++
++/* this should only be called at bootup or when userspace
++ * isn't running */
++void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
++{
++	struct ttm_mem_type_manager *man;
++
++	if (!adev->mman.initialized)
++		return;
++
++	man = &adev->mman.bdev.man[TTM_PL_VRAM];
++	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
++	man->size = size >> PAGE_SHIFT;
++}
++
++static struct vm_operations_struct amdgpu_ttm_vm_ops;
++static const struct vm_operations_struct *ttm_vm_ops = NULL;
++
++static int amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
++{
++	struct ttm_buffer_object *bo;
++	struct amdgpu_device *adev;
++	int r;
++
++	bo = (struct ttm_buffer_object *)vma->vm_private_data;
++	if (bo == NULL) {
++		return VM_FAULT_NOPAGE;
++	}
++	adev = amdgpu_get_adev(bo->bdev);
++	down_read(&adev->pm.mclk_lock);
++	r = ttm_vm_ops->fault(vma, vmf);
++	up_read(&adev->pm.mclk_lock);
++	return r;
++}
++
++int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++	struct drm_file *file_priv;
++	struct amdgpu_device *adev;
++	int r;
++
++	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
++		return -EINVAL;
++	}
++
++	file_priv = filp->private_data;
++	adev = file_priv->minor->dev->dev_private;
++	if (adev == NULL) {
++		return -EINVAL;
++	}
++	r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
++	if (unlikely(r != 0)) {
++		return r;
++	}
++	if (unlikely(ttm_vm_ops == NULL)) {
++		ttm_vm_ops = vma->vm_ops;
++		amdgpu_ttm_vm_ops = *ttm_vm_ops;
++		amdgpu_ttm_vm_ops.fault = &amdgpu_ttm_fault;
++	}
++	vma->vm_ops = &amdgpu_ttm_vm_ops;
++	return 0;
++}
++
++int amdgpu_copy_buffer(struct amdgpu_ring *ring,
++		       uint64_t src_offset,
++		       uint64_t dst_offset,
++		       uint32_t byte_count,
++		       struct reservation_object *resv,
++		       struct amdgpu_fence **fence)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_sync sync;
++	uint32_t max_bytes;
++	unsigned num_loops, num_dw;
++	unsigned i;
++	int r;
++
++	/* sync other rings */
++	amdgpu_sync_create(&sync);
++	if (resv) {
++		r = amdgpu_sync_resv(adev, &sync, resv, false);
++		if (r) {
++			DRM_ERROR("sync failed (%d).\n", r);
++			amdgpu_sync_free(adev, &sync, NULL);
++			return r;
++		}
++	}
++
++	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
++	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
++	num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
++
++	/* for fence and sync */
++	num_dw += 64 + AMDGPU_NUM_SYNCS * 8;
++
++	r = amdgpu_ring_lock(ring, num_dw);
++	if (r) {
++		DRM_ERROR("ring lock failed (%d).\n", r);
++		amdgpu_sync_free(adev, &sync, NULL);
++		return r;
++	}
++
++	amdgpu_sync_rings(&sync, ring);
++
++	for (i = 0; i < num_loops; i++) {
++		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
++
++		amdgpu_emit_copy_buffer(adev, ring, src_offset, dst_offset,
++					cur_size_in_bytes);
++
++		src_offset += cur_size_in_bytes;
++		dst_offset += cur_size_in_bytes;
++		byte_count -= cur_size_in_bytes;
++	}
++
++	r = amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_MOVE, fence);
++	if (r) {
++		amdgpu_ring_unlock_undo(ring);
++		amdgpu_sync_free(adev, &sync, NULL);
++		return r;
++	}
++
++	amdgpu_ring_unlock_commit(ring);
++	amdgpu_sync_free(adev, &sync, *fence);
++
++	return 0;
++}
++
++#if defined(CONFIG_DEBUG_FS)
++
++static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
++{
++	struct drm_info_node *node = (struct drm_info_node *)m->private;
++	unsigned ttm_pl = *(int *)node->info_ent->data;
++	struct drm_device *dev = node->minor->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
++	int ret;
++	struct ttm_bo_global *glob = adev->mman.bdev.glob;
++
++	spin_lock(&glob->lru_lock);
++	ret = drm_mm_dump_table(m, mm);
++	spin_unlock(&glob->lru_lock);
++	return ret;
++}
++
++static int ttm_pl_vram = TTM_PL_VRAM;
++static int ttm_pl_tt = TTM_PL_TT;
++
++static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
++	{"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
++	{"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
++	{"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
++#ifdef CONFIG_SWIOTLB
++	{"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
++#endif
++};
++
++static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
++				    size_t size, loff_t *pos)
++{
++	struct amdgpu_device *adev = f->f_inode->i_private;
++	ssize_t result = 0;
++	int r;
++
++	if (size & 0x3 || *pos & 0x3)
++		return -EINVAL;
++
++	while (size) {
++		unsigned long flags;
++		uint32_t value;
++
++		if (*pos >= adev->mc.mc_vram_size)
++			return result;
++
++		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
++		WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
++		WREG32(mmMM_INDEX_HI, *pos >> 31);
++		value = RREG32(mmMM_DATA);
++		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
++
++		r = put_user(value, (uint32_t *)buf);
++		if (r)
++			return r;
++
++		result += 4;
++		buf += 4;
++		*pos += 4;
++		size -= 4;
++	}
++
++	return result;
++}
++
++static const struct file_operations amdgpu_ttm_vram_fops = {
++	.owner = THIS_MODULE,
++	.read = amdgpu_ttm_vram_read,
++	.llseek = default_llseek
++};
++
++static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
++				   size_t size, loff_t *pos)
++{
++	struct amdgpu_device *adev = f->f_inode->i_private;
++	ssize_t result = 0;
++	int r;
++
++	while (size) {
++		loff_t p = *pos / PAGE_SIZE;
++		unsigned off = *pos & ~PAGE_MASK;
++		size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
++		struct page *page;
++		void *ptr;
++
++		if (p >= adev->gart.num_cpu_pages)
++			return result;
++
++		page = adev->gart.pages[p];
++		if (page) {
++			ptr = kmap(page);
++			ptr += off;
++
++			r = copy_to_user(buf, ptr, cur_size);
++			kunmap(adev->gart.pages[p]);
++		} else
++			r = clear_user(buf, cur_size);
++
++		if (r)
++			return -EFAULT;
++
++		result += cur_size;
++		buf += cur_size;
++		*pos += cur_size;
++		size -= cur_size;
++	}
++
++	return result;
++}
++
++static const struct file_operations amdgpu_ttm_gtt_fops = {
++	.owner = THIS_MODULE,
++	.read = amdgpu_ttm_gtt_read,
++	.llseek = default_llseek
++};
++
++#endif
++
++static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++	unsigned count;
++
++	struct drm_minor *minor = adev->ddev->primary;
++	struct dentry *ent, *root = minor->debugfs_root;
++
++	ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
++				  adev, &amdgpu_ttm_vram_fops);
++	if (IS_ERR(ent))
++		return PTR_ERR(ent);
++	i_size_write(ent->d_inode, adev->mc.mc_vram_size);
++	adev->mman.vram = ent;
++
++	ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
++				  adev, &amdgpu_ttm_gtt_fops);
++	if (IS_ERR(ent))
++		return PTR_ERR(ent);
++	i_size_write(ent->d_inode, adev->mc.gtt_size);
++	adev->mman.gtt = ent;
++
++	count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
++
++#ifdef CONFIG_SWIOTLB
++	if (!swiotlb_nr_tbl())
++		--count;
++#endif
++
++	return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
++#else
++
++	return 0;
++#endif
++}
++
++static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
++{
++#if defined(CONFIG_DEBUG_FS)
++
++	debugfs_remove(adev->mman.vram);
++	adev->mman.vram = NULL;
++
++	debugfs_remove(adev->mman.gtt);
++	adev->mman.gtt = NULL;
++#endif
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+new file mode 100644
+index 0000000..93af9f9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -0,0 +1,317 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_ucode.h"
++
++static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
++{
++	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
++	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
++	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
++	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
++	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
++	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
++	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
++	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
++	DRM_DEBUG("ucode_array_offset_bytes: %u\n",
++		  le32_to_cpu(hdr->ucode_array_offset_bytes));
++	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
++}
++
++void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
++{
++	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
++	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
++
++	DRM_DEBUG("MC\n");
++	amdgpu_ucode_print_common_hdr(hdr);
++
++	if (version_major == 1) {
++		const struct mc_firmware_header_v1_0 *mc_hdr =
++			container_of(hdr, struct mc_firmware_header_v1_0, header);
++
++		DRM_DEBUG("io_debug_size_bytes: %u\n",
++			  le32_to_cpu(mc_hdr->io_debug_size_bytes));
++		DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
++			  le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
++	} else {
++		DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
++	}
++}
++
++void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
++{
++	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
++	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
++
++	DRM_DEBUG("SMC\n");
++	amdgpu_ucode_print_common_hdr(hdr);
++
++	if (version_major == 1) {
++		const struct smc_firmware_header_v1_0 *smc_hdr =
++			container_of(hdr, struct smc_firmware_header_v1_0, header);
++
++		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
++	} else {
++		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
++	}
++}
++
++void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
++{
++	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
++	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
++
++	DRM_DEBUG("GFX\n");
++	amdgpu_ucode_print_common_hdr(hdr);
++
++	if (version_major == 1) {
++		const struct gfx_firmware_header_v1_0 *gfx_hdr =
++			container_of(hdr, struct gfx_firmware_header_v1_0, header);
++
++		DRM_DEBUG("ucode_feature_version: %u\n",
++			  le32_to_cpu(gfx_hdr->ucode_feature_version));
++		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
++		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
++	} else {
++		DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
++	}
++}
++
++void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
++{
++	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
++	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
++
++	DRM_DEBUG("RLC\n");
++	amdgpu_ucode_print_common_hdr(hdr);
++
++	if (version_major == 1) {
++		const struct rlc_firmware_header_v1_0 *rlc_hdr =
++			container_of(hdr, struct rlc_firmware_header_v1_0, header);
++
++		DRM_DEBUG("ucode_feature_version: %u\n",
++			  le32_to_cpu(rlc_hdr->ucode_feature_version));
++		DRM_DEBUG("save_and_restore_offset: %u\n",
++			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
++		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
++			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
++		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
++			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
++		DRM_DEBUG("master_pkt_description_offset: %u\n",
++			  le32_to_cpu(rlc_hdr->master_pkt_description_offset));
++	} else if (version_major == 2) {
++		const struct rlc_firmware_header_v2_0 *rlc_hdr =
++			container_of(hdr, struct rlc_firmware_header_v2_0, header);
++
++		DRM_DEBUG("ucode_feature_version: %u\n",
++			  le32_to_cpu(rlc_hdr->ucode_feature_version));
++		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
++		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
++		DRM_DEBUG("save_and_restore_offset: %u\n",
++			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
++		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
++			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
++		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
++			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
++		DRM_DEBUG("reg_restore_list_size: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_restore_list_size));
++		DRM_DEBUG("reg_list_format_start: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_format_start));
++		DRM_DEBUG("reg_list_format_separate_start: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
++		DRM_DEBUG("starting_offsets_start: %u\n",
++			  le32_to_cpu(rlc_hdr->starting_offsets_start));
++		DRM_DEBUG("reg_list_format_size_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
++		DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
++		DRM_DEBUG("reg_list_size_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_size_bytes));
++		DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
++		DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
++		DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
++		DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
++		DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
++			  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
++	} else {
++		DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
++	}
++}
++
++void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
++{
++	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
++	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
++
++	DRM_DEBUG("SDMA\n");
++	amdgpu_ucode_print_common_hdr(hdr);
++
++	if (version_major == 1) {
++		const struct sdma_firmware_header_v1_0 *sdma_hdr =
++			container_of(hdr, struct sdma_firmware_header_v1_0, header);
++
++		DRM_DEBUG("ucode_feature_version: %u\n",
++			  le32_to_cpu(sdma_hdr->ucode_feature_version));
++		DRM_DEBUG("ucode_change_version: %u\n",
++			  le32_to_cpu(sdma_hdr->ucode_change_version));
++		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
++		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
++		if (version_minor >= 1) {
++			const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
++				container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
++			DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
++		}
++	} else {
++		DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
++			  version_major, version_minor);
++	}
++}
++
++int amdgpu_ucode_validate(const struct firmware *fw)
++{
++	const struct common_firmware_header *hdr =
++		(const struct common_firmware_header *)fw->data;
++
++	if (fw->size == le32_to_cpu(hdr->size_bytes))
++		return 0;
++
++	return -EINVAL;
++}
++
++bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
++				uint16_t hdr_major, uint16_t hdr_minor)
++{
++	if ((hdr->common.header_version_major == hdr_major) &&
++		(hdr->common.header_version_minor == hdr_minor))
++		return 0;
++	return 1;
++}
++
++static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
++				uint64_t mc_addr, void *kptr)
++{
++	const struct common_firmware_header *header = NULL;
++
++	if (NULL == ucode->fw)
++		return 0;
++
++	ucode->mc_addr = mc_addr;
++	ucode->kaddr = kptr;
++
++	header = (const struct common_firmware_header *)ucode->fw->data;
++	memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
++		le32_to_cpu(header->ucode_array_offset_bytes)),
++		le32_to_cpu(header->ucode_size_bytes));
++
++	return 0;
++}
++
++int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
++{
++	struct amdgpu_bo **bo = &adev->firmware.fw_buf;
++	uint64_t fw_mc_addr;
++	void *fw_buf_ptr = NULL;
++	uint64_t fw_offset = 0;
++	int i, err;
++	struct amdgpu_firmware_info *ucode = NULL;
++	const struct common_firmware_header *header = NULL;
++
++	err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
++			AMDGPU_GEM_DOMAIN_GTT, 0, NULL, bo);
++	if (err) {
++		dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
++		err = -ENOMEM;
++		goto failed;
++	}
++
++	err = amdgpu_bo_reserve(*bo, false);
++	if (err) {
++		amdgpu_bo_unref(bo);
++		dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
++		goto failed;
++	}
++
++	err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr);
++	if (err) {
++		amdgpu_bo_unreserve(*bo);
++		amdgpu_bo_unref(bo);
++		dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
++		goto failed;
++	}
++
++	err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
++	if (err) {
++		dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
++		amdgpu_bo_unpin(*bo);
++		amdgpu_bo_unreserve(*bo);
++		amdgpu_bo_unref(bo);
++		goto failed;
++	}
++
++	amdgpu_bo_unreserve(*bo);
++
++	fw_offset = 0;
++	for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
++		ucode = &adev->firmware.ucode[i];
++		if (ucode->fw) {
++			header = (const struct common_firmware_header *)ucode->fw->data;
++			amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
++				(void *)((uint64_t)fw_buf_ptr + fw_offset));
++			fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++		}
++	}
++
++failed:
++	if (err)
++		adev->firmware.smu_load = false;
++
++	return err;
++}
++
++int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
++{
++	int i;
++	struct amdgpu_firmware_info *ucode = NULL;
++
++	for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) {
++		ucode = &adev->firmware.ucode[i];
++		if (ucode->fw) {
++			ucode->mc_addr = 0;
++			ucode->kaddr = NULL;
++		}
++	}
++	amdgpu_bo_unref(&adev->firmware.fw_buf);
++	adev->firmware.fw_buf = NULL;
++
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+new file mode 100644
+index 0000000..e468be4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -0,0 +1,176 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __AMDGPU_UCODE_H__
++#define __AMDGPU_UCODE_H__
++
++struct common_firmware_header {
++	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
++	uint32_t header_size_bytes; /* size of just the header in bytes */
++	uint16_t header_version_major; /* header version */
++	uint16_t header_version_minor; /* header version */
++	uint16_t ip_version_major; /* IP version */
++	uint16_t ip_version_minor; /* IP version */
++	uint32_t ucode_version;
++	uint32_t ucode_size_bytes; /* size of ucode in bytes */
++	uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
++	uint32_t crc32;  /* crc32 checksum of the payload */
++};
++
++/* version_major=1, version_minor=0 */
++struct mc_firmware_header_v1_0 {
++	struct common_firmware_header header;
++	uint32_t io_debug_size_bytes; /* size of debug array in dwords */
++	uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
++};
++
++/* version_major=1, version_minor=0 */
++struct smc_firmware_header_v1_0 {
++	struct common_firmware_header header;
++	uint32_t ucode_start_addr;
++};
++
++/* version_major=1, version_minor=0 */
++struct gfx_firmware_header_v1_0 {
++	struct common_firmware_header header;
++	uint32_t ucode_feature_version;
++	uint32_t jt_offset; /* jt location */
++	uint32_t jt_size;  /* size of jt */
++};
++
++/* version_major=1, version_minor=0 */
++struct rlc_firmware_header_v1_0 {
++	struct common_firmware_header header;
++	uint32_t ucode_feature_version;
++	uint32_t save_and_restore_offset;
++	uint32_t clear_state_descriptor_offset;
++	uint32_t avail_scratch_ram_locations;
++	uint32_t master_pkt_description_offset;
++};
++
++/* version_major=2, version_minor=0 */
++struct rlc_firmware_header_v2_0 {
++	struct common_firmware_header header;
++	uint32_t ucode_feature_version;
++	uint32_t jt_offset; /* jt location */
++	uint32_t jt_size;  /* size of jt */
++	uint32_t save_and_restore_offset;
++	uint32_t clear_state_descriptor_offset;
++	uint32_t avail_scratch_ram_locations;
++	uint32_t reg_restore_list_size;
++	uint32_t reg_list_format_start;
++	uint32_t reg_list_format_separate_start;
++	uint32_t starting_offsets_start;
++	uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
++	uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
++	uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
++	uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
++	uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
++	uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
++	uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
++	uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
++};
++
++/* version_major=1, version_minor=0 */
++struct sdma_firmware_header_v1_0 {
++	struct common_firmware_header header;
++	uint32_t ucode_feature_version;
++	uint32_t ucode_change_version;
++	uint32_t jt_offset; /* jt location */
++	uint32_t jt_size; /* size of jt */
++};
++
++/* version_major=1, version_minor=1 */
++struct sdma_firmware_header_v1_1 {
++	struct sdma_firmware_header_v1_0 v1_0;
++	uint32_t digest_size;
++};
++
++/* header is fixed size */
++union amdgpu_firmware_header {
++	struct common_firmware_header common;
++	struct mc_firmware_header_v1_0 mc;
++	struct smc_firmware_header_v1_0 smc;
++	struct gfx_firmware_header_v1_0 gfx;
++	struct rlc_firmware_header_v1_0 rlc;
++	struct rlc_firmware_header_v2_0 rlc_v2_0;
++	struct sdma_firmware_header_v1_0 sdma;
++	struct sdma_firmware_header_v1_1 sdma_v1_1;
++	uint8_t raw[0x100];
++};
++
++/*
++ * fw loading support
++ */
++enum AMDGPU_UCODE_ID {
++	AMDGPU_UCODE_ID_SDMA0 = 0,
++	AMDGPU_UCODE_ID_SDMA1,
++	AMDGPU_UCODE_ID_CP_CE,
++	AMDGPU_UCODE_ID_CP_PFP,
++	AMDGPU_UCODE_ID_CP_ME,
++	AMDGPU_UCODE_ID_CP_MEC1,
++	AMDGPU_UCODE_ID_CP_MEC2,
++	AMDGPU_UCODE_ID_RLC_G,
++	AMDGPU_UCODE_ID_MAXIMUM,
++};
++
++/* engine firmware status */
++enum AMDGPU_UCODE_STATUS {
++	AMDGPU_UCODE_STATUS_INVALID,
++	AMDGPU_UCODE_STATUS_NOT_LOADED,
++	AMDGPU_UCODE_STATUS_LOADED,
++};
++
++/* conform to smu_ucode_xfer_cz.h */
++#define AMDGPU_SDMA0_UCODE_LOADED	0x00000001
++#define AMDGPU_SDMA1_UCODE_LOADED	0x00000002
++#define AMDGPU_CPCE_UCODE_LOADED	0x00000004
++#define AMDGPU_CPPFP_UCODE_LOADED	0x00000008
++#define AMDGPU_CPME_UCODE_LOADED	0x00000010
++#define AMDGPU_CPMEC1_UCODE_LOADED	0x00000020
++#define AMDGPU_CPMEC2_UCODE_LOADED	0x00000040
++#define AMDGPU_CPRLC_UCODE_LOADED	0x00000100
++
++/* amdgpu firmware info */
++struct amdgpu_firmware_info {
++	/* ucode ID */
++	enum AMDGPU_UCODE_ID ucode_id;
++	/* request_firmware */
++	const struct firmware *fw;
++	/* starting mc address */
++	uint64_t mc_addr;
++	/* kernel linear address */
++	void *kaddr;
++};
++
++void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
++void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
++void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
++void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
++void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
++int amdgpu_ucode_validate(const struct firmware *fw);
++bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
++				uint16_t hdr_major, uint16_t hdr_minor);
++int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
++int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+new file mode 100644
+index 0000000..c03bce6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -0,0 +1,976 @@
++/*
++ * Copyright 2011 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++/*
++ * Authors:
++ *    Christian König <deathsimple@vodafone.de>
++ */
++
++#include <linux/firmware.h>
++#include <linux/module.h>
++#include <drm/drmP.h>
++#include <drm/drm.h>
++
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_uvd.h"
++#include "cikd.h"
++#include "uvd/uvd_4_2_d.h"
++
++/* 1 second timeout */
++#define UVD_IDLE_TIMEOUT_MS	1000
++
++/* Firmware Names */
++#ifdef CONFIG_DRM_AMDGPU_CIK
++#define FIRMWARE_BONAIRE	"radeon/bonaire_uvd.bin"
++#define FIRMWARE_KABINI 	"radeon/kabini_uvd.bin"
++#define FIRMWARE_KAVERI 	"radeon/kaveri_uvd.bin"
++#define FIRMWARE_HAWAII 	"radeon/hawaii_uvd.bin"
++#define FIRMWARE_MULLINS	"radeon/mullins_uvd.bin"
++#endif
++#define FIRMWARE_TONGA		"radeon/tonga_uvd.bin"
++#define FIRMWARE_CARRIZO	"radeon/carrizo_uvd.bin"
++
++/**
++ * amdgpu_uvd_cs_ctx - Command submission parser context
++ *
++ * Used for emulating virtual memory support on UVD 4.2.
++ */
++struct amdgpu_uvd_cs_ctx {
++	struct amdgpu_cs_parser *parser;
++	unsigned reg, count;
++	unsigned data0, data1;
++	unsigned idx;
++	unsigned ib_idx;
++
++	/* does the IB has a msg command */
++	bool has_msg_cmd;
++
++	/* minimum buffer sizes */
++	unsigned *buf_sizes;
++};
++
++#ifdef CONFIG_DRM_AMDGPU_CIK
++MODULE_FIRMWARE(FIRMWARE_BONAIRE);
++MODULE_FIRMWARE(FIRMWARE_KABINI);
++MODULE_FIRMWARE(FIRMWARE_KAVERI);
++MODULE_FIRMWARE(FIRMWARE_HAWAII);
++MODULE_FIRMWARE(FIRMWARE_MULLINS);
++#endif
++MODULE_FIRMWARE(FIRMWARE_TONGA);
++MODULE_FIRMWARE(FIRMWARE_CARRIZO);
++
++static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
++static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
++
++int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
++{
++	unsigned long bo_size;
++	const char *fw_name;
++	const struct common_firmware_header *hdr;
++	unsigned version_major, version_minor, family_id;
++	int i, r;
++
++	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
++
++	switch (adev->asic_type) {
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	case CHIP_BONAIRE:
++		fw_name = FIRMWARE_BONAIRE;
++		break;
++	case CHIP_KABINI:
++		fw_name = FIRMWARE_KABINI;
++		break;
++	case CHIP_KAVERI:
++		fw_name = FIRMWARE_KAVERI;
++		break;
++	case CHIP_HAWAII:
++		fw_name = FIRMWARE_HAWAII;
++		break;
++	case CHIP_MULLINS:
++		fw_name = FIRMWARE_MULLINS;
++		break;
++#endif
++	case CHIP_TONGA:
++		fw_name = FIRMWARE_TONGA;
++		break;
++	case CHIP_CARRIZO:
++		fw_name = FIRMWARE_CARRIZO;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
++	if (r) {
++		dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
++			fw_name);
++		return r;
++	}
++
++	r = amdgpu_ucode_validate(adev->uvd.fw);
++	if (r) {
++		dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
++			fw_name);
++		release_firmware(adev->uvd.fw);
++		adev->uvd.fw = NULL;
++		return r;
++	}
++
++	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
++	family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
++	version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
++	version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
++	DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
++		version_major, version_minor, family_id);
++
++	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
++		 +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
++	r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
++			     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
++		return r;
++	}
++
++	r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
++	if (r) {
++		amdgpu_bo_unref(&adev->uvd.vcpu_bo);
++		dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
++		return r;
++	}
++
++	r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
++			  &adev->uvd.gpu_addr);
++	if (r) {
++		amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
++		amdgpu_bo_unref(&adev->uvd.vcpu_bo);
++		dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
++		return r;
++	}
++
++	r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
++	if (r) {
++		dev_err(adev->dev, "(%d) UVD map failed\n", r);
++		return r;
++	}
++
++	amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
++
++	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
++		atomic_set(&adev->uvd.handles[i], 0);
++		adev->uvd.filp[i] = NULL;
++	}
++
++	/* from uvd v5.0 HW addressing capacity increased to 64 bits */
++	if (!amdgpu_ip_block_version_cmp(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 5, 0))
++		adev->uvd.address_64_bit = true;
++
++	return 0;
++}
++
++int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->uvd.vcpu_bo == NULL)
++		return 0;
++
++	r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
++	if (!r) {
++		amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
++		amdgpu_bo_unpin(adev->uvd.vcpu_bo);
++		amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
++	}
++
++	amdgpu_bo_unref(&adev->uvd.vcpu_bo);
++
++	amdgpu_ring_fini(&adev->uvd.ring);
++
++	release_firmware(adev->uvd.fw);
++
++	return 0;
++}
++
++int amdgpu_uvd_suspend(struct amdgpu_device *adev)
++{
++	unsigned size;
++	void *ptr;
++	const struct common_firmware_header *hdr;
++	int i;
++
++	if (adev->uvd.vcpu_bo == NULL)
++		return 0;
++
++	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
++		if (atomic_read(&adev->uvd.handles[i]))
++			break;
++
++	if (i == AMDGPU_MAX_UVD_HANDLES)
++		return 0;
++
++	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
++
++	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
++	size -= le32_to_cpu(hdr->ucode_size_bytes);
++
++	ptr = adev->uvd.cpu_addr;
++	ptr += le32_to_cpu(hdr->ucode_size_bytes);
++
++	adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
++	memcpy(adev->uvd.saved_bo, ptr, size);
++
++	return 0;
++}
++
++int amdgpu_uvd_resume(struct amdgpu_device *adev)
++{
++	unsigned size;
++	void *ptr;
++	const struct common_firmware_header *hdr;
++	unsigned offset;
++
++	if (adev->uvd.vcpu_bo == NULL)
++		return -EINVAL;
++
++	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
++	offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
++	memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
++		(adev->uvd.fw->size) - offset);
++
++	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
++	size -= le32_to_cpu(hdr->ucode_size_bytes);
++	ptr = adev->uvd.cpu_addr;
++	ptr += le32_to_cpu(hdr->ucode_size_bytes);
++
++	if (adev->uvd.saved_bo != NULL) {
++		memcpy(ptr, adev->uvd.saved_bo, size);
++		kfree(adev->uvd.saved_bo);
++		adev->uvd.saved_bo = NULL;
++	} else
++		memset(ptr, 0, size);
++
++	return 0;
++}
++
++void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	int i, r;
++
++	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
++		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
++		if (handle != 0 && adev->uvd.filp[i] == filp) {
++			struct amdgpu_fence *fence;
++
++			amdgpu_uvd_note_usage(adev);
++
++			r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
++			if (r) {
++				DRM_ERROR("Error destroying UVD (%d)!\n", r);
++				continue;
++			}
++
++			amdgpu_fence_wait(fence, false);
++			amdgpu_fence_unref(&fence);
++
++			adev->uvd.filp[i] = NULL;
++			atomic_set(&adev->uvd.handles[i], 0);
++		}
++	}
++}
++
++static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
++{
++	int i;
++	for (i = 0; i < rbo->placement.num_placement; ++i) {
++		rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
++		rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
++	}
++}
++
++/**
++ * amdgpu_uvd_cs_pass1 - first parsing round
++ *
++ * @ctx: UVD parser context
++ *
++ * Make sure UVD message and feedback buffers are in VRAM and
++ * nobody is violating an 256MB boundary.
++ */
++static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
++{
++	struct amdgpu_bo_va_mapping *mapping;
++	struct amdgpu_bo *bo;
++	uint32_t cmd, lo, hi;
++	uint64_t addr;
++	int r = 0;
++
++	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
++	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
++	addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
++
++	mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
++	if (mapping == NULL) {
++		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
++		return -EINVAL;
++	}
++
++	if (!ctx->parser->adev->uvd.address_64_bit) {
++		/* check if it's a message or feedback command */
++		cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
++		if (cmd == 0x0 || cmd == 0x3) {
++			/* yes, force it into VRAM */
++			uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
++			amdgpu_ttm_placement_from_domain(bo, domain);
++		}
++		amdgpu_uvd_force_into_uvd_segment(bo);
++
++		r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
++	}
++
++	return r;
++}
++
++/**
++ * amdgpu_uvd_cs_msg_decode - handle UVD decode message
++ *
++ * @msg: pointer to message structure
++ * @buf_sizes: returned buffer sizes
++ *
++ * Peek into the decode message and calculate the necessary buffer sizes.
++ */
++static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
++{
++	unsigned stream_type = msg[4];
++	unsigned width = msg[6];
++	unsigned height = msg[7];
++	unsigned dpb_size = msg[9];
++	unsigned pitch = msg[28];
++	unsigned level = msg[57];
++
++	unsigned width_in_mb = width / 16;
++	unsigned height_in_mb = ALIGN(height / 16, 2);
++	unsigned fs_in_mb = width_in_mb * height_in_mb;
++
++	unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
++
++	image_size = width * height;
++	image_size += image_size / 2;
++	image_size = ALIGN(image_size, 1024);
++
++	switch (stream_type) {
++	case 0: /* H264 */
++	case 7: /* H264 Perf */
++		switch(level) {
++		case 30:
++			num_dpb_buffer = 8100 / fs_in_mb;
++			break;
++		case 31:
++			num_dpb_buffer = 18000 / fs_in_mb;
++			break;
++		case 32:
++			num_dpb_buffer = 20480 / fs_in_mb;
++			break;
++		case 41:
++			num_dpb_buffer = 32768 / fs_in_mb;
++			break;
++		case 42:
++			num_dpb_buffer = 34816 / fs_in_mb;
++			break;
++		case 50:
++			num_dpb_buffer = 110400 / fs_in_mb;
++			break;
++		case 51:
++			num_dpb_buffer = 184320 / fs_in_mb;
++			break;
++		default:
++			num_dpb_buffer = 184320 / fs_in_mb;
++			break;
++		}
++		num_dpb_buffer++;
++		if (num_dpb_buffer > 17)
++			num_dpb_buffer = 17;
++
++		/* reference picture buffer */
++		min_dpb_size = image_size * num_dpb_buffer;
++
++		/* macroblock context buffer */
++		min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
++
++		/* IT surface buffer */
++		min_dpb_size += width_in_mb * height_in_mb * 32;
++		break;
++
++	case 1: /* VC1 */
++
++		/* reference picture buffer */
++		min_dpb_size = image_size * 3;
++
++		/* CONTEXT_BUFFER */
++		min_dpb_size += width_in_mb * height_in_mb * 128;
++
++		/* IT surface buffer */
++		min_dpb_size += width_in_mb * 64;
++
++		/* DB surface buffer */
++		min_dpb_size += width_in_mb * 128;
++
++		/* BP */
++		tmp = max(width_in_mb, height_in_mb);
++		min_dpb_size += ALIGN(tmp * 7 * 16, 64);
++		break;
++
++	case 3: /* MPEG2 */
++
++		/* reference picture buffer */
++		min_dpb_size = image_size * 3;
++		break;
++
++	case 4: /* MPEG4 */
++
++		/* reference picture buffer */
++		min_dpb_size = image_size * 3;
++
++		/* CM */
++		min_dpb_size += width_in_mb * height_in_mb * 64;
++
++		/* IT surface buffer */
++		min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
++		break;
++
++	default:
++		DRM_ERROR("UVD codec not handled %d!\n", stream_type);
++		return -EINVAL;
++	}
++
++	if (width > pitch) {
++		DRM_ERROR("Invalid UVD decoding target pitch!\n");
++		return -EINVAL;
++	}
++
++	if (dpb_size < min_dpb_size) {
++		DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
++			  dpb_size, min_dpb_size);
++		return -EINVAL;
++	}
++
++	buf_sizes[0x1] = dpb_size;
++	buf_sizes[0x2] = image_size;
++	return 0;
++}
++
++/**
++ * amdgpu_uvd_cs_msg - handle UVD message
++ *
++ * @ctx: UVD parser context
++ * @bo: buffer object containing the message
++ * @offset: offset into the buffer object
++ *
++ * Peek into the UVD message and extract the session id.
++ * Make sure that we don't open up to many sessions.
++ */
++static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
++			     struct amdgpu_bo *bo, unsigned offset)
++{
++	struct amdgpu_device *adev = ctx->parser->adev;
++	int32_t *msg, msg_type, handle;
++	struct fence *f;
++	void *ptr;
++
++	int i, r;
++
++	if (offset & 0x3F) {
++		DRM_ERROR("UVD messages must be 64 byte aligned!\n");
++		return -EINVAL;
++	}
++
++	f = reservation_object_get_excl(bo->tbo.resv);
++	if (f) {
++		r = amdgpu_fence_wait((struct amdgpu_fence *)f, false);
++		if (r) {
++			DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
++			return r;
++		}
++	}
++
++	r = amdgpu_bo_kmap(bo, &ptr);
++	if (r) {
++		DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
++		return r;
++	}
++
++	msg = ptr + offset;
++
++	msg_type = msg[1];
++	handle = msg[2];
++
++	if (handle == 0) {
++		DRM_ERROR("Invalid UVD handle!\n");
++		return -EINVAL;
++	}
++
++	if (msg_type == 1) {
++		/* it's a decode msg, calc buffer sizes */
++		r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
++		amdgpu_bo_kunmap(bo);
++		if (r)
++			return r;
++
++	} else if (msg_type == 2) {
++		/* it's a destroy msg, free the handle */
++		for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
++			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
++		amdgpu_bo_kunmap(bo);
++		return 0;
++	} else {
++		/* it's a create msg */
++		amdgpu_bo_kunmap(bo);
++
++		if (msg_type != 0) {
++			DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
++			return -EINVAL;
++		}
++
++		/* it's a create msg, no special handling needed */
++	}
++
++	/* create or decode, validate the handle */
++	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
++		if (atomic_read(&adev->uvd.handles[i]) == handle)
++			return 0;
++	}
++
++	/* handle not found try to alloc a new one */
++	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
++		if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
++			adev->uvd.filp[i] = ctx->parser->filp;
++			return 0;
++		}
++	}
++
++	DRM_ERROR("No more free UVD handles!\n");
++	return -EINVAL;
++}
++
++/**
++ * amdgpu_uvd_cs_pass2 - second parsing round
++ *
++ * @ctx: UVD parser context
++ *
++ * Patch buffer addresses, make sure buffer sizes are correct.
++ */
++static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
++{
++	struct amdgpu_bo_va_mapping *mapping;
++	struct amdgpu_bo *bo;
++	struct amdgpu_ib *ib;
++	uint32_t cmd, lo, hi;
++	uint64_t start, end;
++	uint64_t addr;
++	int r;
++
++	lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
++	hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
++	addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
++
++	mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
++	if (mapping == NULL)
++		return -EINVAL;
++
++	start = amdgpu_bo_gpu_offset(bo);
++
++	end = (mapping->it.last + 1 - mapping->it.start);
++	end = end * AMDGPU_GPU_PAGE_SIZE + start;
++
++	addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
++	start += addr;
++
++	ib = &ctx->parser->ibs[ctx->ib_idx];
++	ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
++	ib->ptr[ctx->data1] = start >> 32;
++
++	cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
++	if (cmd < 0x4) {
++		if ((end - start) < ctx->buf_sizes[cmd]) {
++			DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
++				  (unsigned)(end - start),
++				  ctx->buf_sizes[cmd]);
++			return -EINVAL;
++		}
++
++	} else if ((cmd != 0x100) && (cmd != 0x204)) {
++		DRM_ERROR("invalid UVD command %X!\n", cmd);
++		return -EINVAL;
++	}
++
++	if (!ctx->parser->adev->uvd.address_64_bit) {
++		if ((start >> 28) != ((end - 1) >> 28)) {
++			DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
++				  start, end);
++			return -EINVAL;
++		}
++
++		if ((cmd == 0 || cmd == 0x3) &&
++		    (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
++			DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
++				  start, end);
++			return -EINVAL;
++		}
++	}
++
++	if (cmd == 0) {
++		ctx->has_msg_cmd = true;
++		r = amdgpu_uvd_cs_msg(ctx, bo, addr);
++		if (r)
++			return r;
++	} else if (!ctx->has_msg_cmd) {
++		DRM_ERROR("Message needed before other commands are send!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_uvd_cs_reg - parse register writes
++ *
++ * @ctx: UVD parser context
++ * @cb: callback function
++ *
++ * Parse the register writes, call cb on each complete command.
++ */
++static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
++			     int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
++{
++	struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
++	int i, r;
++
++	ctx->idx++;
++	for (i = 0; i <= ctx->count; ++i) {
++		unsigned reg = ctx->reg + i;
++
++		if (ctx->idx >= ib->length_dw) {
++			DRM_ERROR("Register command after end of CS!\n");
++			return -EINVAL;
++		}
++
++		switch (reg) {
++		case mmUVD_GPCOM_VCPU_DATA0:
++			ctx->data0 = ctx->idx;
++			break;
++		case mmUVD_GPCOM_VCPU_DATA1:
++			ctx->data1 = ctx->idx;
++			break;
++		case mmUVD_GPCOM_VCPU_CMD:
++			r = cb(ctx);
++			if (r)
++				return r;
++			break;
++		case mmUVD_ENGINE_CNTL:
++			break;
++		default:
++			DRM_ERROR("Invalid reg 0x%X!\n", reg);
++			return -EINVAL;
++		}
++		ctx->idx++;
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_uvd_cs_packets - parse UVD packets
++ *
++ * @ctx: UVD parser context
++ * @cb: callback function
++ *
++ * Parse the command stream packets.
++ */
++static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
++				 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
++{
++	struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
++	int r;
++
++	for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
++		uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
++		unsigned type = CP_PACKET_GET_TYPE(cmd);
++		switch (type) {
++		case PACKET_TYPE0:
++			ctx->reg = CP_PACKET0_GET_REG(cmd);
++			ctx->count = CP_PACKET_GET_COUNT(cmd);
++			r = amdgpu_uvd_cs_reg(ctx, cb);
++			if (r)
++				return r;
++			break;
++		case PACKET_TYPE2:
++			++ctx->idx;
++			break;
++		default:
++			DRM_ERROR("Unknown packet type %d !\n", type);
++			return -EINVAL;
++		}
++	}
++	return 0;
++}
++
++/**
++ * amdgpu_uvd_ring_parse_cs - UVD command submission parser
++ *
++ * @parser: Command submission parser context
++ *
++ * Parse the command stream, patch in addresses as necessary.
++ */
++int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
++{
++	struct amdgpu_uvd_cs_ctx ctx = {};
++	unsigned buf_sizes[] = {
++		[0x00000000]	=	2048,
++		[0x00000001]	=	32 * 1024 * 1024,
++		[0x00000002]	=	2048 * 1152 * 3,
++		[0x00000003]	=	2048,
++	};
++	struct amdgpu_ib *ib = &parser->ibs[ib_idx];
++	int r;
++
++	if (ib->length_dw % 16) {
++		DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
++			  ib->length_dw);
++		return -EINVAL;
++	}
++
++	ctx.parser = parser;
++	ctx.buf_sizes = buf_sizes;
++	ctx.ib_idx = ib_idx;
++
++	/* first round, make sure the buffers are actually in the UVD segment */
++	r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
++	if (r)
++		return r;
++
++	/* second round, patch buffer addresses into the command stream */
++	r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
++	if (r)
++		return r;
++
++	if (!ctx.has_msg_cmd) {
++		DRM_ERROR("UVD-IBs need a msg command!\n");
++		return -EINVAL;
++	}
++
++	amdgpu_uvd_note_usage(ctx.parser->adev);
++
++	return 0;
++}
++
++static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
++			       struct amdgpu_bo *bo,
++			       struct amdgpu_fence **fence)
++{
++	struct ttm_validate_buffer tv;
++	struct ww_acquire_ctx ticket;
++	struct list_head head;
++	struct amdgpu_ib ib;
++	uint64_t addr;
++	int i, r;
++
++	memset(&tv, 0, sizeof(tv));
++	tv.bo = &bo->tbo;
++
++	INIT_LIST_HEAD(&head);
++	list_add(&tv.head, &head);
++
++	r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
++	if (r)
++		return r;
++
++	if (!bo->adev->uvd.address_64_bit) {
++		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
++		amdgpu_uvd_force_into_uvd_segment(bo);
++	}
++
++	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
++	if (r)
++		goto err;
++
++	r = amdgpu_ib_get(ring, NULL, 64, &ib);
++	if (r)
++		goto err;
++
++	addr = amdgpu_bo_gpu_offset(bo);
++	ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
++	ib.ptr[1] = addr;
++	ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
++	ib.ptr[3] = addr >> 32;
++	ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
++	ib.ptr[5] = 0;
++	for (i = 6; i < 16; ++i)
++		ib.ptr[i] = PACKET2(0);
++	ib.length_dw = 16;
++
++	r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r)
++		goto err;
++	ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base);
++
++	if (fence)
++		*fence = amdgpu_fence_ref(ib.fence);
++
++	amdgpu_ib_free(ring->adev, &ib);
++	amdgpu_bo_unref(&bo);
++	return 0;
++
++err:
++	ttm_eu_backoff_reservation(&ticket, &head);
++	return r;
++}
++
++/* multiple fence commands without any stream commands in between can
++   crash the vcpu so just try to emmit a dummy create/destroy msg to
++   avoid this */
++int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++			      struct amdgpu_fence **fence)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_bo *bo;
++	uint32_t *msg;
++	int r, i;
++
++	r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
++			     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_reserve(bo, false);
++	if (r) {
++		amdgpu_bo_unref(&bo);
++		return r;
++	}
++
++	r = amdgpu_bo_kmap(bo, (void **)&msg);
++	if (r) {
++		amdgpu_bo_unreserve(bo);
++		amdgpu_bo_unref(&bo);
++		return r;
++	}
++
++	/* stitch together an UVD create msg */
++	msg[0] = cpu_to_le32(0x00000de4);
++	msg[1] = cpu_to_le32(0x00000000);
++	msg[2] = cpu_to_le32(handle);
++	msg[3] = cpu_to_le32(0x00000000);
++	msg[4] = cpu_to_le32(0x00000000);
++	msg[5] = cpu_to_le32(0x00000000);
++	msg[6] = cpu_to_le32(0x00000000);
++	msg[7] = cpu_to_le32(0x00000780);
++	msg[8] = cpu_to_le32(0x00000440);
++	msg[9] = cpu_to_le32(0x00000000);
++	msg[10] = cpu_to_le32(0x01b37000);
++	for (i = 11; i < 1024; ++i)
++		msg[i] = cpu_to_le32(0x0);
++
++	amdgpu_bo_kunmap(bo);
++	amdgpu_bo_unreserve(bo);
++
++	return amdgpu_uvd_send_msg(ring, bo, fence);
++}
++
++int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++			       struct amdgpu_fence **fence)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_bo *bo;
++	uint32_t *msg;
++	int r, i;
++
++	r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
++			     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_reserve(bo, false);
++	if (r) {
++		amdgpu_bo_unref(&bo);
++		return r;
++	}
++
++	r = amdgpu_bo_kmap(bo, (void **)&msg);
++	if (r) {
++		amdgpu_bo_unreserve(bo);
++		amdgpu_bo_unref(&bo);
++		return r;
++	}
++
++	/* stitch together an UVD destroy msg */
++	msg[0] = cpu_to_le32(0x00000de4);
++	msg[1] = cpu_to_le32(0x00000002);
++	msg[2] = cpu_to_le32(handle);
++	msg[3] = cpu_to_le32(0x00000000);
++	for (i = 4; i < 1024; ++i)
++		msg[i] = cpu_to_le32(0x0);
++
++	amdgpu_bo_kunmap(bo);
++	amdgpu_bo_unreserve(bo);
++
++	return amdgpu_uvd_send_msg(ring, bo, fence);
++}
++
++static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
++{
++	struct amdgpu_device *adev =
++		container_of(work, struct amdgpu_device, uvd.idle_work.work);
++	unsigned i, fences, handles = 0;
++
++	fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
++
++	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
++		if (atomic_read(&adev->uvd.handles[i]))
++			++handles;
++
++	if (fences == 0 && handles == 0) {
++		if (adev->pm.dpm_enabled) {
++			amdgpu_dpm_enable_uvd(adev, false);
++		} else {
++			amdgpu_asic_set_uvd_clocks(adev, 0, 0);
++		}
++	} else {
++		schedule_delayed_work(&adev->uvd.idle_work,
++				      msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
++	}
++}
++
++static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
++{
++	bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
++	set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
++					    msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
++
++	if (set_clocks) {
++		if (adev->pm.dpm_enabled) {
++			amdgpu_dpm_enable_uvd(adev, true);
++		} else {
++			amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
++		}
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+new file mode 100644
+index 0000000..2255aa7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+@@ -0,0 +1,39 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_UVD_H__
++#define __AMDGPU_UVD_H__
++
++int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
++int amdgpu_uvd_sw_fini(struct amdgpu_device *adev);
++int amdgpu_uvd_suspend(struct amdgpu_device *adev);
++int amdgpu_uvd_resume(struct amdgpu_device *adev);
++int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++			      struct amdgpu_fence **fence);
++int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++			       struct amdgpu_fence **fence);
++void amdgpu_uvd_free_handles(struct amdgpu_device *adev,
++			     struct drm_file *filp);
++int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+new file mode 100644
+index 0000000..c65d93c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -0,0 +1,727 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * Authors: Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <linux/module.h>
++#include <drm/drmP.h>
++#include <drm/drm.h>
++
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_vce.h"
++#include "cikd.h"
++
++/* 1 second timeout */
++#define VCE_IDLE_TIMEOUT_MS	1000
++
++/* Firmware Names */
++#ifdef CONFIG_DRM_AMDGPU_CIK
++#define FIRMWARE_BONAIRE	"radeon/bonaire_vce.bin"
++#define FIRMWARE_KABINI 	"radeon/kabini_vce.bin"
++#define FIRMWARE_KAVERI 	"radeon/kaveri_vce.bin"
++#define FIRMWARE_HAWAII 	"radeon/hawaii_vce.bin"
++#define FIRMWARE_MULLINS	"radeon/mullins_vce.bin"
++#endif
++#define FIRMWARE_TONGA		"radeon/tonga_vce.bin"
++#define FIRMWARE_CARRIZO	"radeon/carrizo_vce.bin"
++
++#ifdef CONFIG_DRM_AMDGPU_CIK
++MODULE_FIRMWARE(FIRMWARE_BONAIRE);
++MODULE_FIRMWARE(FIRMWARE_KABINI);
++MODULE_FIRMWARE(FIRMWARE_KAVERI);
++MODULE_FIRMWARE(FIRMWARE_HAWAII);
++MODULE_FIRMWARE(FIRMWARE_MULLINS);
++#endif
++MODULE_FIRMWARE(FIRMWARE_TONGA);
++MODULE_FIRMWARE(FIRMWARE_CARRIZO);
++
++static void amdgpu_vce_idle_work_handler(struct work_struct *work);
++
++/**
++ * amdgpu_vce_init - allocate memory, load vce firmware
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * First step to get VCE online, allocate memory and load the firmware
++ */
++int amdgpu_vce_sw_init(struct amdgpu_device *adev)
++{
++	unsigned long size;
++	const char *fw_name;
++	const struct common_firmware_header *hdr;
++	unsigned ucode_version, version_major, version_minor, binary_id;
++	int i, r;
++
++	INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
++
++	switch (adev->asic_type) {
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	case CHIP_BONAIRE:
++		fw_name = FIRMWARE_BONAIRE;
++		break;
++	case CHIP_KAVERI:
++		fw_name = FIRMWARE_KAVERI;
++		break;
++	case CHIP_KABINI:
++		fw_name = FIRMWARE_KABINI;
++		break;
++	case CHIP_HAWAII:
++		fw_name = FIRMWARE_HAWAII;
++		break;
++	case CHIP_MULLINS:
++		fw_name = FIRMWARE_MULLINS;
++		break;
++#endif
++	case CHIP_TONGA:
++		fw_name = FIRMWARE_TONGA;
++		break;
++	case CHIP_CARRIZO:
++		fw_name = FIRMWARE_CARRIZO;
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
++	if (r) {
++		dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
++			fw_name);
++		return r;
++	}
++
++	r = amdgpu_ucode_validate(adev->vce.fw);
++	if (r) {
++		dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
++			fw_name);
++		release_firmware(adev->vce.fw);
++		adev->vce.fw = NULL;
++		return r;
++	}
++
++	hdr = (const struct common_firmware_header *)adev->vce.fw->data;
++
++	ucode_version = le32_to_cpu(hdr->ucode_version);
++	version_major = (ucode_version >> 20) & 0xfff;
++	version_minor = (ucode_version >> 8) & 0xfff;
++	binary_id = ucode_version & 0xff;
++	DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
++		version_major, version_minor, binary_id);
++	adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
++				(binary_id << 8));
++
++	/* allocate firmware, stack and heap BO */
++
++	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes)) +
++	       AMDGPU_VCE_STACK_SIZE + AMDGPU_VCE_HEAP_SIZE;
++	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
++			     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
++		return r;
++	}
++
++	r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
++	if (r) {
++		amdgpu_bo_unref(&adev->vce.vcpu_bo);
++		dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
++		return r;
++	}
++
++	r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
++			  &adev->vce.gpu_addr);
++	amdgpu_bo_unreserve(adev->vce.vcpu_bo);
++	if (r) {
++		amdgpu_bo_unref(&adev->vce.vcpu_bo);
++		dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
++		return r;
++	}
++
++	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
++		atomic_set(&adev->vce.handles[i], 0);
++		adev->vce.filp[i] = NULL;
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_vce_fini - free memory
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Last step on VCE teardown, free firmware memory
++ */
++int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
++{
++	if (adev->vce.vcpu_bo == NULL)
++		return 0;
++
++	amdgpu_bo_unref(&adev->vce.vcpu_bo);
++
++	amdgpu_ring_fini(&adev->vce.ring[0]);
++	amdgpu_ring_fini(&adev->vce.ring[1]);
++
++	release_firmware(adev->vce.fw);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vce_suspend - unpin VCE fw memory
++ *
++ * @adev: amdgpu_device pointer
++ *
++ */
++int amdgpu_vce_suspend(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (adev->vce.vcpu_bo == NULL)
++		return 0;
++
++	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
++		if (atomic_read(&adev->vce.handles[i]))
++			break;
++
++	if (i == AMDGPU_MAX_VCE_HANDLES)
++		return 0;
++
++	/* TODO: suspending running encoding sessions isn't supported */
++	return -EINVAL;
++}
++
++/**
++ * amdgpu_vce_resume - pin VCE fw memory
++ *
++ * @adev: amdgpu_device pointer
++ *
++ */
++int amdgpu_vce_resume(struct amdgpu_device *adev)
++{
++	void *cpu_addr;
++	const struct common_firmware_header *hdr;
++	unsigned offset;
++	int r;
++
++	if (adev->vce.vcpu_bo == NULL)
++		return -EINVAL;
++
++	r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
++		return r;
++	}
++
++	r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
++	if (r) {
++		amdgpu_bo_unreserve(adev->vce.vcpu_bo);
++		dev_err(adev->dev, "(%d) VCE map failed\n", r);
++		return r;
++	}
++
++	hdr = (const struct common_firmware_header *)adev->vce.fw->data;
++	offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
++	memcpy(cpu_addr, (adev->vce.fw->data) + offset,
++		(adev->vce.fw->size) - offset);
++
++	amdgpu_bo_kunmap(adev->vce.vcpu_bo);
++
++	amdgpu_bo_unreserve(adev->vce.vcpu_bo);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vce_idle_work_handler - power off VCE
++ *
++ * @work: pointer to work structure
++ *
++ * power of VCE when it's not used any more
++ */
++static void amdgpu_vce_idle_work_handler(struct work_struct *work)
++{
++	struct amdgpu_device *adev =
++		container_of(work, struct amdgpu_device, vce.idle_work.work);
++
++	if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
++	    (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
++		if (adev->pm.dpm_enabled) {
++			amdgpu_dpm_enable_vce(adev, false);
++		} else {
++			amdgpu_asic_set_vce_clocks(adev, 0, 0);
++		}
++	} else {
++		schedule_delayed_work(&adev->vce.idle_work,
++				      msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
++	}
++}
++
++/**
++ * amdgpu_vce_note_usage - power up VCE
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Make sure VCE is powerd up when we want to use it
++ */
++static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
++{
++	bool streams_changed = false;
++	bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
++	set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
++					    msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
++
++	if (adev->pm.dpm_enabled) {
++		/* XXX figure out if the streams changed */
++		streams_changed = false;
++	}
++
++	if (set_clocks || streams_changed) {
++		if (adev->pm.dpm_enabled) {
++			amdgpu_dpm_enable_vce(adev, true);
++		} else {
++			amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
++		}
++	}
++}
++
++/**
++ * amdgpu_vce_free_handles - free still open VCE handles
++ *
++ * @adev: amdgpu_device pointer
++ * @filp: drm file pointer
++ *
++ * Close all VCE handles still open by this file pointer
++ */
++void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
++{
++	struct amdgpu_ring *ring = &adev->vce.ring[0];
++	int i, r;
++	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
++		uint32_t handle = atomic_read(&adev->vce.handles[i]);
++		if (!handle || adev->vce.filp[i] != filp)
++			continue;
++
++		amdgpu_vce_note_usage(adev);
++
++		r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
++		if (r)
++			DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
++
++		adev->vce.filp[i] = NULL;
++		atomic_set(&adev->vce.handles[i], 0);
++	}
++}
++
++/**
++ * amdgpu_vce_get_create_msg - generate a VCE create msg
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: ring we should submit the msg to
++ * @handle: VCE session handle to use
++ * @fence: optional fence to return
++ *
++ * Open up a stream for HW test
++ */
++int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++			      struct amdgpu_fence **fence)
++{
++	const unsigned ib_size_dw = 1024;
++	struct amdgpu_ib ib;
++	uint64_t dummy;
++	int i, r;
++
++	r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		return r;
++	}
++
++	dummy = ib.gpu_addr + 1024;
++
++	/* stitch together an VCE create msg */
++	ib.length_dw = 0;
++	ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
++	ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
++	ib.ptr[ib.length_dw++] = handle;
++
++	ib.ptr[ib.length_dw++] = 0x00000030; /* len */
++	ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
++	ib.ptr[ib.length_dw++] = 0x00000000;
++	ib.ptr[ib.length_dw++] = 0x00000042;
++	ib.ptr[ib.length_dw++] = 0x0000000a;
++	ib.ptr[ib.length_dw++] = 0x00000001;
++	ib.ptr[ib.length_dw++] = 0x00000080;
++	ib.ptr[ib.length_dw++] = 0x00000060;
++	ib.ptr[ib.length_dw++] = 0x00000100;
++	ib.ptr[ib.length_dw++] = 0x00000100;
++	ib.ptr[ib.length_dw++] = 0x0000000c;
++	ib.ptr[ib.length_dw++] = 0x00000000;
++
++	ib.ptr[ib.length_dw++] = 0x00000014; /* len */
++	ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
++	ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
++	ib.ptr[ib.length_dw++] = dummy;
++	ib.ptr[ib.length_dw++] = 0x00000001;
++
++	for (i = ib.length_dw; i < ib_size_dw; ++i)
++		ib.ptr[i] = 0x0;
++
++	r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++	}
++
++	if (fence)
++		*fence = amdgpu_fence_ref(ib.fence);
++
++	amdgpu_ib_free(ring->adev, &ib);
++
++	return r;
++}
++
++/**
++ * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: ring we should submit the msg to
++ * @handle: VCE session handle to use
++ * @fence: optional fence to return
++ *
++ * Close up a stream for HW test or if userspace failed to do so
++ */
++int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++			       struct amdgpu_fence **fence)
++{
++	const unsigned ib_size_dw = 1024;
++	struct amdgpu_ib ib;
++	uint64_t dummy;
++	int i, r;
++
++	r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		return r;
++	}
++
++	dummy = ib.gpu_addr + 1024;
++
++	/* stitch together an VCE destroy msg */
++	ib.length_dw = 0;
++	ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
++	ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
++	ib.ptr[ib.length_dw++] = handle;
++
++	ib.ptr[ib.length_dw++] = 0x00000014; /* len */
++	ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
++	ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
++	ib.ptr[ib.length_dw++] = dummy;
++	ib.ptr[ib.length_dw++] = 0x00000001;
++
++	ib.ptr[ib.length_dw++] = 0x00000008; /* len */
++	ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
++
++	for (i = ib.length_dw; i < ib_size_dw; ++i)
++		ib.ptr[i] = 0x0;
++
++	r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++	}
++
++	if (fence)
++		*fence = amdgpu_fence_ref(ib.fence);
++
++	amdgpu_ib_free(ring->adev, &ib);
++
++	return r;
++}
++
++/**
++ * amdgpu_vce_cs_reloc - command submission relocation
++ *
++ * @p: parser context
++ * @lo: address of lower dword
++ * @hi: address of higher dword
++ *
++ * Patch relocation inside command stream with real buffer address
++ */
++int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi)
++{
++	struct amdgpu_bo_va_mapping *mapping;
++	struct amdgpu_ib *ib = &p->ibs[ib_idx];
++	struct amdgpu_bo *bo;
++	uint64_t addr;
++
++	addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
++	       ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
++
++	mapping = amdgpu_cs_find_mapping(p, addr, &bo);
++	if (mapping == NULL) {
++		DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d\n",
++			  addr, lo, hi);
++		return -EINVAL;
++	}
++
++	addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
++	addr += amdgpu_bo_gpu_offset(bo);
++
++	ib->ptr[lo] = addr & 0xFFFFFFFF;
++	ib->ptr[hi] = addr >> 32;
++
++	return 0;
++}
++
++/**
++ * amdgpu_vce_cs_parse - parse and validate the command stream
++ *
++ * @p: parser context
++ *
++ */
++int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
++{
++	uint32_t handle = 0;
++	bool destroy = false;
++	int i, r, idx = 0;
++	struct amdgpu_ib *ib = &p->ibs[ib_idx];
++
++	amdgpu_vce_note_usage(p->adev);
++
++	while (idx < ib->length_dw) {
++		uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
++		uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
++
++		if ((len < 8) || (len & 3)) {
++			DRM_ERROR("invalid VCE command length (%d)!\n", len);
++			return -EINVAL;
++		}
++
++		switch (cmd) {
++		case 0x00000001: // session
++			handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
++			break;
++
++		case 0x00000002: // task info
++		case 0x01000001: // create
++		case 0x04000001: // config extension
++		case 0x04000002: // pic control
++		case 0x04000005: // rate control
++		case 0x04000007: // motion estimation
++		case 0x04000008: // rdo
++		case 0x04000009: // vui
++		case 0x05000002: // auxiliary buffer
++			break;
++
++		case 0x03000001: // encode
++			r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9);
++			if (r)
++				return r;
++
++			r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11);
++			if (r)
++				return r;
++			break;
++
++		case 0x02000001: // destroy
++			destroy = true;
++			break;
++
++		case 0x05000001: // context buffer
++		case 0x05000004: // video bitstream buffer
++		case 0x05000005: // feedback buffer
++			r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2);
++			if (r)
++				return r;
++			break;
++
++		default:
++			DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
++			return -EINVAL;
++		}
++
++		idx += len / 4;
++	}
++
++	if (destroy) {
++		/* IB contains a destroy msg, free the handle */
++		for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
++			atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
++
++		return 0;
++	}
++
++	/* create or encode, validate the handle */
++	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
++		if (atomic_read(&p->adev->vce.handles[i]) == handle)
++			return 0;
++	}
++
++	/* handle not found try to alloc a new one */
++	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
++		if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
++			p->adev->vce.filp[i] = p->filp;
++			return 0;
++		}
++	}
++
++	DRM_ERROR("No more free VCE handles!\n");
++
++	return -EINVAL;
++}
++
++/**
++ * amdgpu_vce_ring_emit_semaphore - emit a semaphore command
++ *
++ * @ring: engine to use
++ * @semaphore: address of semaphore
++ * @emit_wait: true=emit wait, false=emit signal
++ *
++ */
++bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
++				    struct amdgpu_semaphore *semaphore,
++				    bool emit_wait)
++{
++	uint64_t addr = semaphore->gpu_addr;
++
++	amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
++	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
++	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
++	amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
++	if (!emit_wait)
++		amdgpu_ring_write(ring, VCE_CMD_END);
++
++	return true;
++}
++
++/**
++ * amdgpu_vce_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: engine to use
++ * @ib: the IB to execute
++ *
++ */
++void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
++{
++	amdgpu_ring_write(ring, VCE_CMD_IB);
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, ib->length_dw);
++}
++
++/**
++ * amdgpu_vce_ring_emit_fence - add a fence command to the ring
++ *
++ * @ring: engine to use
++ * @fence: the fence
++ *
++ */
++void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				bool write64bits)
++{
++	WARN_ON(write64bits);
++
++	amdgpu_ring_write(ring, VCE_CMD_FENCE);
++	amdgpu_ring_write(ring, addr);
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++	amdgpu_ring_write(ring, seq);
++	amdgpu_ring_write(ring, VCE_CMD_TRAP);
++	amdgpu_ring_write(ring, VCE_CMD_END);
++}
++
++/**
++ * amdgpu_vce_ring_test_ring - test if VCE ring is working
++ *
++ * @ring: the engine to test on
++ *
++ */
++int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t rptr = amdgpu_ring_get_rptr(ring);
++	unsigned i;
++	int r;
++
++	r = amdgpu_ring_lock(ring, 16);
++	if (r) {
++		DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
++			  ring->idx, r);
++		return r;
++	}
++	amdgpu_ring_write(ring, VCE_CMD_END);
++	amdgpu_ring_unlock_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (amdgpu_ring_get_rptr(ring) != rptr)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n",
++			 ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed\n",
++			  ring->idx);
++		r = -ETIMEDOUT;
++	}
++
++	return r;
++}
++
++/**
++ * amdgpu_vce_ring_test_ib - test if VCE IBs are working
++ *
++ * @ring: the engine to test on
++ *
++ */
++int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_fence *fence = NULL;
++	int r;
++
++	r = amdgpu_vce_get_create_msg(ring, 1, NULL);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_fence_wait(fence, false);
++	if (r) {
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++	} else {
++		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
++	}
++error:
++	amdgpu_fence_unref(&fence);
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+new file mode 100644
+index 0000000..b9411e4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+@@ -0,0 +1,47 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_VCE_H__
++#define __AMDGPU_VCE_H__
++
++int amdgpu_vce_sw_init(struct amdgpu_device *adev);
++int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
++int amdgpu_vce_suspend(struct amdgpu_device *adev);
++int amdgpu_vce_resume(struct amdgpu_device *adev);
++int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++			      struct amdgpu_fence **fence);
++int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++			       struct amdgpu_fence **fence);
++void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
++int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi);
++int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
++bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
++				    struct amdgpu_semaphore *semaphore,
++				    bool emit_wait);
++void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
++void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				bool write64bit);
++int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
++int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+new file mode 100644
+index 0000000..1cc01fb
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -0,0 +1,1248 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ * Copyright 2009 Jerome Glisse.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_trace.h"
++
++/*
++ * GPUVM
++ * GPUVM is similar to the legacy gart on older asics, however
++ * rather than there being a single global gart table
++ * for the entire GPU, there are multiple VM page tables active
++ * at any given time.  The VM page tables can contain a mix
++ * vram pages and system memory pages and system memory pages
++ * can be mapped as snooped (cached system pages) or unsnooped
++ * (uncached system pages).
++ * Each VM has an ID associated with it and there is a page table
++ * associated with each VMID.  When execting a command buffer,
++ * the kernel tells the the ring what VMID to use for that command
++ * buffer.  VMIDs are allocated dynamically as commands are submitted.
++ * The userspace drivers maintain their own address space and the kernel
++ * sets up their pages tables accordingly when they submit their
++ * command buffers and a VMID is assigned.
++ * Cayman/Trinity support up to 8 active VMs at any given time;
++ * SI supports 16.
++ */
++
++/**
++ * amdgpu_vm_num_pde - return the number of page directory entries
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Calculate the number of page directory entries (cayman+).
++ */
++static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
++{
++	return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
++}
++
++/**
++ * amdgpu_vm_directory_size - returns the size of the page directory in bytes
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Calculate the size of the page directory in bytes (cayman+).
++ */
++static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
++{
++	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
++}
++
++/**
++ * amdgpu_vm_get_bos - add the vm BOs to a validation list
++ *
++ * @vm: vm providing the BOs
++ * @head: head of validation list
++ *
++ * Add the page directory to the list of BOs to
++ * validate for command submission (cayman+).
++ */
++struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
++					  struct amdgpu_vm *vm,
++					  struct list_head *head)
++{
++	struct amdgpu_bo_list_entry *list;
++	unsigned i, idx;
++
++	list = drm_malloc_ab(vm->max_pde_used + 2,
++			     sizeof(struct amdgpu_bo_list_entry));
++	if (!list)
++		return NULL;
++
++	/* add the vm page table to the list */
++	list[0].robj = vm->page_directory;
++	list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
++	list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
++	list[0].priority = 0;
++	list[0].tv.bo = &vm->page_directory->tbo;
++	list[0].tv.shared = true;
++	list_add(&list[0].tv.head, head);
++
++	for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
++		if (!vm->page_tables[i].bo)
++			continue;
++
++		list[idx].robj = vm->page_tables[i].bo;
++		list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
++		list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
++		list[idx].priority = 0;
++		list[idx].tv.bo = &list[idx].robj->tbo;
++		list[idx].tv.shared = true;
++		list_add(&list[idx++].tv.head, head);
++	}
++
++	return list;
++}
++
++/**
++ * amdgpu_vm_grab_id - allocate the next free VMID
++ *
++ * @ring: ring we want to submit job to
++ * @vm: vm to allocate id for
++ *
++ * Allocate an id for the vm (cayman+).
++ * Returns the fence we need to sync to (if any).
++ *
++ * Global and local mutex must be locked!
++ */
++struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring,
++				       struct amdgpu_vm *vm)
++{
++	struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {};
++	struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
++	struct amdgpu_device *adev = ring->adev;
++
++	unsigned choices[2] = {};
++	unsigned i;
++
++	/* check if the id is still valid */
++	if (vm_id->id && vm_id->last_id_use &&
++	    vm_id->last_id_use == adev->vm_manager.active[vm_id->id])
++		return NULL;
++
++	/* we definately need to flush */
++	vm_id->pd_gpu_addr = ~0ll;
++
++	/* skip over VMID 0, since it is the system VM */
++	for (i = 1; i < adev->vm_manager.nvm; ++i) {
++		struct amdgpu_fence *fence = adev->vm_manager.active[i];
++
++		if (fence == NULL) {
++			/* found a free one */
++			vm_id->id = i;
++			trace_amdgpu_vm_grab_id(i, ring->idx);
++			return NULL;
++		}
++
++		if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) {
++			best[fence->ring->idx] = fence;
++			choices[fence->ring == ring ? 0 : 1] = i;
++		}
++	}
++
++	for (i = 0; i < 2; ++i) {
++		if (choices[i]) {
++			vm_id->id = choices[i];
++			trace_amdgpu_vm_grab_id(choices[i], ring->idx);
++			return adev->vm_manager.active[choices[i]];
++		}
++	}
++
++	/* should never happen */
++	BUG();
++	return NULL;
++}
++
++/**
++ * amdgpu_vm_flush - hardware flush the vm
++ *
++ * @ring: ring to use for flush
++ * @vm: vm we want to flush
++ * @updates: last vm update that we waited for
++ *
++ * Flush the vm (cayman+).
++ *
++ * Global and local mutex must be locked!
++ */
++void amdgpu_vm_flush(struct amdgpu_ring *ring,
++		     struct amdgpu_vm *vm,
++		     struct amdgpu_fence *updates)
++{
++	uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
++	struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
++
++	if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates ||
++	    amdgpu_fence_is_earlier(vm_id->flushed_updates, updates)) {
++
++		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
++		amdgpu_fence_unref(&vm_id->flushed_updates);
++		vm_id->flushed_updates = amdgpu_fence_ref(updates);
++		vm_id->pd_gpu_addr = pd_addr;
++		amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
++	}
++}
++
++/**
++ * amdgpu_vm_fence - remember fence for vm
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: vm we want to fence
++ * @fence: fence to remember
++ *
++ * Fence the vm (cayman+).
++ * Set the fence used to protect page table and id.
++ *
++ * Global and local mutex must be locked!
++ */
++void amdgpu_vm_fence(struct amdgpu_device *adev,
++		     struct amdgpu_vm *vm,
++		     struct amdgpu_fence *fence)
++{
++	unsigned ridx = fence->ring->idx;
++	unsigned vm_id = vm->ids[ridx].id;
++
++	amdgpu_fence_unref(&adev->vm_manager.active[vm_id]);
++	adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence);
++
++	amdgpu_fence_unref(&vm->ids[ridx].last_id_use);
++	vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence);
++}
++
++/**
++ * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
++ *
++ * @vm: requested vm
++ * @bo: requested buffer object
++ *
++ * Find @bo inside the requested vm (cayman+).
++ * Search inside the @bos vm list for the requested vm
++ * Returns the found bo_va or NULL if none is found
++ *
++ * Object has to be reserved!
++ */
++struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
++				       struct amdgpu_bo *bo)
++{
++	struct amdgpu_bo_va *bo_va;
++
++	list_for_each_entry(bo_va, &bo->va, bo_list) {
++		if (bo_va->vm == vm) {
++			return bo_va;
++		}
++	}
++	return NULL;
++}
++
++/**
++ * amdgpu_vm_update_pages - helper to call the right asic function
++ *
++ * @adev: amdgpu_device pointer
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: hw access flags
++ * @gtt_flags: GTT hw access flags
++ *
++ * Traces the parameters and calls the right asic functions
++ * to setup the page table using the DMA.
++ */
++static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
++				   struct amdgpu_ib *ib,
++				   uint64_t pe, uint64_t addr,
++				   unsigned count, uint32_t incr,
++				   uint32_t flags, uint32_t gtt_flags)
++{
++	trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
++
++	if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
++		uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
++		amdgpu_vm_copy_pte(adev, ib, pe, src, count);
++
++	} else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
++		amdgpu_vm_write_pte(adev, ib, pe, addr,
++				      count, incr, flags);
++
++	} else {
++		amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
++				      count, incr, flags);
++	}
++}
++
++/**
++ * amdgpu_vm_clear_bo - initially clear the page dir/table
++ *
++ * @adev: amdgpu_device pointer
++ * @bo: bo to clear
++ */
++static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
++			      struct amdgpu_bo *bo)
++{
++	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
++	struct amdgpu_ib ib;
++	unsigned entries;
++	uint64_t addr;
++	int r;
++
++	r = amdgpu_bo_reserve(bo, false);
++	if (r)
++		return r;
++
++	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
++	if (r)
++		goto error_unreserve;
++
++	addr = amdgpu_bo_gpu_offset(bo);
++	entries = amdgpu_bo_size(bo) / 8;
++
++	r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, &ib);
++	if (r)
++		goto error_unreserve;
++
++	ib.length_dw = 0;
++
++	amdgpu_vm_update_pages(adev, &ib, addr, 0, entries, 0, 0, 0);
++	amdgpu_vm_pad_ib(adev, &ib);
++	WARN_ON(ib.length_dw > 64);
++
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_VM);
++	if (r)
++		goto error_free;
++
++	amdgpu_bo_fence(bo, ib.fence, false);
++
++error_free:
++	amdgpu_ib_free(adev, &ib);
++
++error_unreserve:
++	amdgpu_bo_unreserve(bo);
++	return r;
++}
++
++/**
++ * amdgpu_vm_map_gart - get the physical address of a gart page
++ *
++ * @adev: amdgpu_device pointer
++ * @addr: the unmapped addr
++ *
++ * Look up the physical address of the page that the pte resolves
++ * to (cayman+).
++ * Returns the physical address of the page.
++ */
++uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
++{
++	uint64_t result;
++
++	/* page table offset */
++	result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
++
++	/* in case cpu page size != gpu page size*/
++	result |= addr & (~PAGE_MASK);
++
++	return result;
++}
++
++/**
++ * amdgpu_vm_update_pdes - make sure that page directory is valid
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ * @start: start of GPU address range
++ * @end: end of GPU address range
++ *
++ * Allocates new page tables if necessary
++ * and updates the page directory (cayman+).
++ * Returns 0 for success, error for failure.
++ *
++ * Global and local mutex must be locked!
++ */
++int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
++				    struct amdgpu_vm *vm)
++{
++	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
++	struct amdgpu_bo *pd = vm->page_directory;
++	uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
++	uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
++	uint64_t last_pde = ~0, last_pt = ~0;
++	unsigned count = 0, pt_idx, ndw;
++	struct amdgpu_ib ib;
++	int r;
++
++	/* padding, etc. */
++	ndw = 64;
++
++	/* assume the worst case */
++	ndw += vm->max_pde_used * 6;
++
++	/* update too big for an IB */
++	if (ndw > 0xfffff)
++		return -ENOMEM;
++
++	r = amdgpu_ib_get(ring, NULL, ndw * 4, &ib);
++	if (r)
++		return r;
++	ib.length_dw = 0;
++
++	/* walk over the address space and update the page directory */
++	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
++		struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
++		uint64_t pde, pt;
++
++		if (bo == NULL)
++			continue;
++
++		pt = amdgpu_bo_gpu_offset(bo);
++		if (vm->page_tables[pt_idx].addr == pt)
++			continue;
++		vm->page_tables[pt_idx].addr = pt;
++
++		pde = pd_addr + pt_idx * 8;
++		if (((last_pde + 8 * count) != pde) ||
++		    ((last_pt + incr * count) != pt)) {
++
++			if (count) {
++				amdgpu_vm_update_pages(adev, &ib, last_pde,
++						       last_pt, count, incr,
++						       AMDGPU_PTE_VALID, 0);
++			}
++
++			count = 1;
++			last_pde = pde;
++			last_pt = pt;
++		} else {
++			++count;
++		}
++	}
++
++	if (count)
++		amdgpu_vm_update_pages(adev, &ib, last_pde, last_pt, count,
++				       incr, AMDGPU_PTE_VALID, 0);
++
++	if (ib.length_dw != 0) {
++		amdgpu_vm_pad_ib(adev, &ib);
++		amdgpu_sync_resv(adev, &ib.sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
++		WARN_ON(ib.length_dw > ndw);
++		r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_VM);
++		if (r) {
++			amdgpu_ib_free(adev, &ib);
++			return r;
++		}
++		amdgpu_bo_fence(pd, ib.fence, false);
++	}
++	amdgpu_ib_free(adev, &ib);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_frag_ptes - add fragment information to PTEs
++ *
++ * @adev: amdgpu_device pointer
++ * @ib: IB for the update
++ * @pe_start: first PTE to handle
++ * @pe_end: last PTE to handle
++ * @addr: addr those PTEs should point to
++ * @flags: hw mapping flags
++ * @gtt_flags: GTT hw mapping flags
++ *
++ * Global and local mutex must be locked!
++ */
++static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
++				struct amdgpu_ib *ib,
++				uint64_t pe_start, uint64_t pe_end,
++				uint64_t addr, uint32_t flags,
++				uint32_t gtt_flags)
++{
++	/**
++	 * The MC L1 TLB supports variable sized pages, based on a fragment
++	 * field in the PTE. When this field is set to a non-zero value, page
++	 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
++	 * flags are considered valid for all PTEs within the fragment range
++	 * and corresponding mappings are assumed to be physically contiguous.
++	 *
++	 * The L1 TLB can store a single PTE for the whole fragment,
++	 * significantly increasing the space available for translation
++	 * caching. This leads to large improvements in throughput when the
++	 * TLB is under pressure.
++	 *
++	 * The L2 TLB distributes small and large fragments into two
++	 * asymmetric partitions. The large fragment cache is significantly
++	 * larger. Thus, we try to use large fragments wherever possible.
++	 * Userspace can support this by aligning virtual base address and
++	 * allocation size to the fragment size.
++	 */
++
++	/* SI and newer are optimized for 64KB */
++	uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
++	uint64_t frag_align = 0x80;
++
++	uint64_t frag_start = ALIGN(pe_start, frag_align);
++	uint64_t frag_end = pe_end & ~(frag_align - 1);
++
++	unsigned count;
++
++	/* system pages are non continuously */
++	if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
++	    (frag_start >= frag_end)) {
++
++		count = (pe_end - pe_start) / 8;
++		amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
++				       AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
++		return;
++	}
++
++	/* handle the 4K area at the beginning */
++	if (pe_start != frag_start) {
++		count = (frag_start - pe_start) / 8;
++		amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
++				       AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
++		addr += AMDGPU_GPU_PAGE_SIZE * count;
++	}
++
++	/* handle the area in the middle */
++	count = (frag_end - frag_start) / 8;
++	amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
++			       AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
++			       gtt_flags);
++
++	/* handle the 4K area at the end */
++	if (frag_end != pe_end) {
++		addr += AMDGPU_GPU_PAGE_SIZE * count;
++		count = (pe_end - frag_end) / 8;
++		amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
++				       AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
++	}
++}
++
++/**
++ * amdgpu_vm_update_ptes - make sure that page tables are valid
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ * @start: start of GPU address range
++ * @end: end of GPU address range
++ * @dst: destination address to map to
++ * @flags: mapping flags
++ *
++ * Update the page tables in the range @start - @end (cayman+).
++ *
++ * Global and local mutex must be locked!
++ */
++static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
++				 struct amdgpu_vm *vm,
++				 struct amdgpu_ib *ib,
++				 uint64_t start, uint64_t end,
++				 uint64_t dst, uint32_t flags,
++				 uint32_t gtt_flags)
++{
++	uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
++	uint64_t last_pte = ~0, last_dst = ~0;
++	unsigned count = 0;
++	uint64_t addr;
++
++	/* walk over the address space and update the page tables */
++	for (addr = start; addr < end; ) {
++		uint64_t pt_idx = addr >> amdgpu_vm_block_size;
++		struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
++		unsigned nptes;
++		uint64_t pte;
++		int r;
++
++		amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv,
++				 AMDGPU_FENCE_OWNER_VM);
++		r = reservation_object_reserve_shared(pt->tbo.resv);
++		if (r)
++			return r;
++
++		if ((addr & ~mask) == (end & ~mask))
++			nptes = end - addr;
++		else
++			nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
++
++		pte = amdgpu_bo_gpu_offset(pt);
++		pte += (addr & mask) * 8;
++
++		if ((last_pte + 8 * count) != pte) {
++
++			if (count) {
++				amdgpu_vm_frag_ptes(adev, ib, last_pte,
++						    last_pte + 8 * count,
++						    last_dst, flags,
++						    gtt_flags);
++			}
++
++			count = nptes;
++			last_pte = pte;
++			last_dst = dst;
++		} else {
++			count += nptes;
++		}
++
++		addr += nptes;
++		dst += nptes * AMDGPU_GPU_PAGE_SIZE;
++	}
++
++	if (count) {
++		amdgpu_vm_frag_ptes(adev, ib, last_pte,
++				    last_pte + 8 * count,
++				    last_dst, flags, gtt_flags);
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_fence_pts - fence page tables after an update
++ *
++ * @vm: requested vm
++ * @start: start of GPU address range
++ * @end: end of GPU address range
++ * @fence: fence to use
++ *
++ * Fence the page tables in the range @start - @end (cayman+).
++ *
++ * Global and local mutex must be locked!
++ */
++static void amdgpu_vm_fence_pts(struct amdgpu_vm *vm,
++				uint64_t start, uint64_t end,
++				struct amdgpu_fence *fence)
++{
++	unsigned i;
++
++	start >>= amdgpu_vm_block_size;
++	end >>= amdgpu_vm_block_size;
++
++	for (i = start; i <= end; ++i)
++		amdgpu_bo_fence(vm->page_tables[i].bo, fence, true);
++}
++
++/**
++ * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ * @mapping: mapped range and flags to use for the update
++ * @addr: addr to set the area to
++ * @gtt_flags: flags as they are used for GTT
++ * @fence: optional resulting fence
++ *
++ * Fill in the page table entries for @mapping.
++ * Returns 0 for success, -EINVAL for failure.
++ *
++ * Object have to be reserved and mutex must be locked!
++ */
++static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
++				       struct amdgpu_vm *vm,
++				       struct amdgpu_bo_va_mapping *mapping,
++				       uint64_t addr, uint32_t gtt_flags,
++				       struct amdgpu_fence **fence)
++{
++	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
++	unsigned nptes, ncmds, ndw;
++	uint32_t flags = gtt_flags;
++	struct amdgpu_ib ib;
++	int r;
++
++	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
++	 * but in case of something, we filter the flags in first place
++	 */
++	if (!(mapping->flags & AMDGPU_PTE_READABLE))
++		flags &= ~AMDGPU_PTE_READABLE;
++	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
++		flags &= ~AMDGPU_PTE_WRITEABLE;
++
++	trace_amdgpu_vm_bo_update(mapping);
++
++	nptes = mapping->it.last - mapping->it.start + 1;
++
++	/*
++	 * reserve space for one command every (1 << BLOCK_SIZE)
++	 *  entries or 2k dwords (whatever is smaller)
++	 */
++	ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
++
++	/* padding, etc. */
++	ndw = 64;
++
++	if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
++		/* only copy commands needed */
++		ndw += ncmds * 7;
++
++	} else if (flags & AMDGPU_PTE_SYSTEM) {
++		/* header for write data commands */
++		ndw += ncmds * 4;
++
++		/* body of write data command */
++		ndw += nptes * 2;
++
++	} else {
++		/* set page commands needed */
++		ndw += ncmds * 10;
++
++		/* two extra commands for begin/end of fragment */
++		ndw += 2 * 10;
++	}
++
++	/* update too big for an IB */
++	if (ndw > 0xfffff)
++		return -ENOMEM;
++
++	r = amdgpu_ib_get(ring, NULL, ndw * 4, &ib);
++	if (r)
++		return r;
++	ib.length_dw = 0;
++
++	if (!(flags & AMDGPU_PTE_VALID)) {
++		unsigned i;
++
++		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++			struct amdgpu_fence *f = vm->ids[i].last_id_use;
++			amdgpu_sync_fence(&ib.sync, f);
++		}
++	}
++
++	r = amdgpu_vm_update_ptes(adev, vm, &ib, mapping->it.start,
++				  mapping->it.last + 1, addr + mapping->offset,
++				  flags, gtt_flags);
++
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		return r;
++	}
++
++	amdgpu_vm_pad_ib(adev, &ib);
++	WARN_ON(ib.length_dw > ndw);
++
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_VM);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		return r;
++	}
++	amdgpu_vm_fence_pts(vm, mapping->it.start,
++			    mapping->it.last + 1, ib.fence);
++	if (fence) {
++		amdgpu_fence_unref(fence);
++		*fence = amdgpu_fence_ref(ib.fence);
++	}
++	amdgpu_ib_free(adev, &ib);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_bo_update - update all BO mappings in the vm page table
++ *
++ * @adev: amdgpu_device pointer
++ * @bo_va: requested BO and VM object
++ * @mem: ttm mem
++ *
++ * Fill in the page table entries for @bo_va.
++ * Returns 0 for success, -EINVAL for failure.
++ *
++ * Object have to be reserved and mutex must be locked!
++ */
++int amdgpu_vm_bo_update(struct amdgpu_device *adev,
++			struct amdgpu_bo_va *bo_va,
++			struct ttm_mem_reg *mem)
++{
++	struct amdgpu_vm *vm = bo_va->vm;
++	struct amdgpu_bo_va_mapping *mapping;
++	uint32_t flags;
++	uint64_t addr;
++	int r;
++
++	if (mem) {
++		addr = mem->start << PAGE_SHIFT;
++		if (mem->mem_type != TTM_PL_TT)
++			addr += adev->vm_manager.vram_base_offset;
++	} else {
++		addr = 0;
++	}
++
++	if (addr == bo_va->addr)
++		return 0;
++
++	flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
++
++	list_for_each_entry(mapping, &bo_va->mappings, list) {
++		r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
++						flags, &bo_va->last_pt_update);
++		if (r)
++			return r;
++	}
++
++	bo_va->addr = addr;
++	spin_lock(&vm->status_lock);
++	list_del_init(&bo_va->vm_status);
++	spin_unlock(&vm->status_lock);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_clear_freed - clear freed BOs in the PT
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ *
++ * Make sure all freed BOs are cleared in the PT.
++ * Returns 0 for success.
++ *
++ * PTs have to be reserved and mutex must be locked!
++ */
++int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
++			  struct amdgpu_vm *vm)
++{
++	struct amdgpu_bo_va_mapping *mapping;
++	int r;
++
++	while (!list_empty(&vm->freed)) {
++		mapping = list_first_entry(&vm->freed,
++			struct amdgpu_bo_va_mapping, list);
++		list_del(&mapping->list);
++
++		r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
++		kfree(mapping);
++		if (r)
++			return r;
++
++	}
++	return 0;
++
++}
++
++/**
++ * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ *
++ * Make sure all invalidated BOs are cleared in the PT.
++ * Returns 0 for success.
++ *
++ * PTs have to be reserved and mutex must be locked!
++ */
++int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
++			     struct amdgpu_vm *vm)
++{
++	struct amdgpu_bo_va *bo_va;
++	int r;
++
++	spin_lock(&vm->status_lock);
++	while (!list_empty(&vm->invalidated)) {
++		bo_va = list_first_entry(&vm->invalidated,
++			struct amdgpu_bo_va, vm_status);
++		spin_unlock(&vm->status_lock);
++
++		r = amdgpu_vm_bo_update(adev, bo_va, NULL);
++		if (r)
++			return r;
++
++		spin_lock(&vm->status_lock);
++	}
++	spin_unlock(&vm->status_lock);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_bo_add - add a bo to a specific vm
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ * @bo: amdgpu buffer object
++ *
++ * Add @bo into the requested vm (cayman+).
++ * Add @bo to the list of bos associated with the vm
++ * Returns newly added bo_va or NULL for failure
++ *
++ * Object has to be reserved!
++ */
++struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
++				      struct amdgpu_vm *vm,
++				      struct amdgpu_bo *bo)
++{
++	struct amdgpu_bo_va *bo_va;
++
++	bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
++	if (bo_va == NULL) {
++		return NULL;
++	}
++	bo_va->vm = vm;
++	bo_va->bo = bo;
++	bo_va->addr = 0;
++	bo_va->ref_count = 1;
++	INIT_LIST_HEAD(&bo_va->bo_list);
++	INIT_LIST_HEAD(&bo_va->mappings);
++	INIT_LIST_HEAD(&bo_va->vm_status);
++
++	mutex_lock(&vm->mutex);
++	list_add_tail(&bo_va->bo_list, &bo->va);
++	mutex_unlock(&vm->mutex);
++
++	return bo_va;
++}
++
++/**
++ * amdgpu_vm_bo_map - map bo inside a vm
++ *
++ * @adev: amdgpu_device pointer
++ * @bo_va: bo_va to store the address
++ * @saddr: where to map the BO
++ * @offset: requested offset in the BO
++ * @flags: attributes of pages (read/write/valid/etc.)
++ *
++ * Add a mapping of the BO at the specefied addr into the VM.
++ * Returns 0 for success, error for failure.
++ *
++ * Object has to be reserved and gets unreserved by this function!
++ */
++int amdgpu_vm_bo_map(struct amdgpu_device *adev,
++		     struct amdgpu_bo_va *bo_va,
++		     uint64_t saddr, uint64_t offset,
++		     uint64_t size, uint32_t flags)
++{
++	struct amdgpu_bo_va_mapping *mapping;
++	struct amdgpu_vm *vm = bo_va->vm;
++	struct interval_tree_node *it;
++	unsigned last_pfn, pt_idx;
++	uint64_t eaddr;
++	int r;
++
++	/* make sure object fit at this offset */
++	eaddr = saddr + size;
++	if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) {
++		amdgpu_bo_unreserve(bo_va->bo);
++		return -EINVAL;
++	}
++
++	last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
++	if (last_pfn > adev->vm_manager.max_pfn) {
++		dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n",
++			last_pfn, adev->vm_manager.max_pfn);
++		amdgpu_bo_unreserve(bo_va->bo);
++		return -EINVAL;
++	}
++
++	mutex_lock(&vm->mutex);
++
++	saddr /= AMDGPU_GPU_PAGE_SIZE;
++	eaddr /= AMDGPU_GPU_PAGE_SIZE;
++
++	it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1);
++	if (it) {
++		struct amdgpu_bo_va_mapping *tmp;
++		tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
++		/* bo and tmp overlap, invalid addr */
++		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
++			"0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
++			tmp->it.start, tmp->it.last + 1);
++		amdgpu_bo_unreserve(bo_va->bo);
++		r = -EINVAL;
++		goto error_unlock;
++	}
++
++	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
++	if (!mapping) {
++		amdgpu_bo_unreserve(bo_va->bo);
++		r = -ENOMEM;
++		goto error_unlock;
++	}
++
++	INIT_LIST_HEAD(&mapping->list);
++	mapping->it.start = saddr;
++	mapping->it.last = eaddr - 1;
++	mapping->offset = offset;
++	mapping->flags = flags;
++
++	list_add(&mapping->list, &bo_va->mappings);
++	interval_tree_insert(&mapping->it, &vm->va);
++
++	/* Make sure the page tables are allocated */
++	saddr >>= amdgpu_vm_block_size;
++	eaddr >>= amdgpu_vm_block_size;
++
++	BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
++
++	if (eaddr > vm->max_pde_used)
++		vm->max_pde_used = eaddr;
++
++	amdgpu_bo_unreserve(bo_va->bo);
++
++	/* walk over the address space and allocate the page tables */
++	for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
++		struct amdgpu_bo *pt;
++
++		if (vm->page_tables[pt_idx].bo)
++			continue;
++
++		/* drop mutex to allocate and clear page table */
++		mutex_unlock(&vm->mutex);
++
++		r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
++				     AMDGPU_GPU_PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &pt);
++		if (r)
++			goto error_free;
++
++		r = amdgpu_vm_clear_bo(adev, pt);
++		if (r) {
++			amdgpu_bo_unref(&pt);
++			goto error_free;
++		}
++
++		/* aquire mutex again */
++		mutex_lock(&vm->mutex);
++		if (vm->page_tables[pt_idx].bo) {
++			/* someone else allocated the pt in the meantime */
++			mutex_unlock(&vm->mutex);
++			amdgpu_bo_unref(&pt);
++			mutex_lock(&vm->mutex);
++			continue;
++		}
++
++		vm->page_tables[pt_idx].addr = 0;
++		vm->page_tables[pt_idx].bo = pt;
++	}
++
++	mutex_unlock(&vm->mutex);
++	return 0;
++
++error_free:
++	mutex_lock(&vm->mutex);
++	list_del(&mapping->list);
++	interval_tree_remove(&mapping->it, &vm->va);
++	kfree(mapping);
++
++error_unlock:
++	mutex_unlock(&vm->mutex);
++	return r;
++}
++
++/**
++ * amdgpu_vm_bo_unmap - remove bo mapping from vm
++ *
++ * @adev: amdgpu_device pointer
++ * @bo_va: bo_va to remove the address from
++ * @saddr: where to the BO is mapped
++ *
++ * Remove a mapping of the BO at the specefied addr from the VM.
++ * Returns 0 for success, error for failure.
++ *
++ * Object has to be reserved and gets unreserved by this function!
++ */
++int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
++		       struct amdgpu_bo_va *bo_va,
++		       uint64_t saddr)
++{
++	struct amdgpu_bo_va_mapping *mapping;
++	struct amdgpu_vm *vm = bo_va->vm;
++
++	list_for_each_entry(mapping, &bo_va->mappings, list) {
++		if (mapping->it.start == saddr)
++			break;
++	}
++
++	if (&mapping->list == &bo_va->mappings) {
++		amdgpu_bo_unreserve(bo_va->bo);
++		return -ENOENT;
++	}
++
++	mutex_lock(&vm->mutex);
++	list_del(&mapping->list);
++	interval_tree_remove(&mapping->it, &vm->va);
++
++	if (bo_va->addr) {
++		/* clear the old address */
++		list_add(&mapping->list, &vm->freed);
++	} else {
++		kfree(mapping);
++	}
++	mutex_unlock(&vm->mutex);
++	amdgpu_bo_unreserve(bo_va->bo);
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_bo_rmv - remove a bo to a specific vm
++ *
++ * @adev: amdgpu_device pointer
++ * @bo_va: requested bo_va
++ *
++ * Remove @bo_va->bo from the requested vm (cayman+).
++ *
++ * Object have to be reserved!
++ */
++void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
++		      struct amdgpu_bo_va *bo_va)
++{
++	struct amdgpu_bo_va_mapping *mapping, *next;
++	struct amdgpu_vm *vm = bo_va->vm;
++
++	list_del(&bo_va->bo_list);
++
++	mutex_lock(&vm->mutex);
++
++	spin_lock(&vm->status_lock);
++	list_del(&bo_va->vm_status);
++	spin_unlock(&vm->status_lock);
++
++	list_for_each_entry_safe(mapping, next, &bo_va->mappings, list) {
++		list_del(&mapping->list);
++		interval_tree_remove(&mapping->it, &vm->va);
++		if (bo_va->addr)
++			list_add(&mapping->list, &vm->freed);
++		else
++			kfree(mapping);
++	}
++	amdgpu_fence_unref(&bo_va->last_pt_update);
++	kfree(bo_va);
++
++	mutex_unlock(&vm->mutex);
++}
++
++/**
++ * amdgpu_vm_bo_invalidate - mark the bo as invalid
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ * @bo: amdgpu buffer object
++ *
++ * Mark @bo as invalid (cayman+).
++ */
++void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
++			     struct amdgpu_bo *bo)
++{
++	struct amdgpu_bo_va *bo_va;
++
++	list_for_each_entry(bo_va, &bo->va, bo_list) {
++		if (bo_va->addr) {
++			spin_lock(&bo_va->vm->status_lock);
++			list_del(&bo_va->vm_status);
++			list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
++			spin_unlock(&bo_va->vm->status_lock);
++		}
++	}
++}
++
++/**
++ * amdgpu_vm_init - initialize a vm instance
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ *
++ * Init @vm fields (cayman+).
++ */
++int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
++{
++	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
++		AMDGPU_VM_PTE_COUNT * 8);
++	unsigned pd_size, pd_entries, pts_size;
++	int i, r;
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		vm->ids[i].id = 0;
++		vm->ids[i].flushed_updates = NULL;
++		vm->ids[i].last_id_use = NULL;
++	}
++	mutex_init(&vm->mutex);
++	vm->va = RB_ROOT;
++	spin_lock_init(&vm->status_lock);
++	INIT_LIST_HEAD(&vm->invalidated);
++	INIT_LIST_HEAD(&vm->freed);
++
++	pd_size = amdgpu_vm_directory_size(adev);
++	pd_entries = amdgpu_vm_num_pdes(adev);
++
++	/* allocate page table array */
++	pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
++	vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
++	if (vm->page_tables == NULL) {
++		DRM_ERROR("Cannot allocate memory for page table array\n");
++		return -ENOMEM;
++	}
++
++	r = amdgpu_bo_create(adev, pd_size, align, true,
++			     AMDGPU_GEM_DOMAIN_VRAM, 0,
++			     NULL, &vm->page_directory);
++	if (r)
++		return r;
++
++	r = amdgpu_vm_clear_bo(adev, vm->page_directory);
++	if (r) {
++		amdgpu_bo_unref(&vm->page_directory);
++		vm->page_directory = NULL;
++		return r;
++	}
++
++	return 0;
++}
++
++/**
++ * amdgpu_vm_fini - tear down a vm instance
++ *
++ * @adev: amdgpu_device pointer
++ * @vm: requested vm
++ *
++ * Tear down @vm (cayman+).
++ * Unbind the VM and remove all bos from the vm bo list
++ */
++void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
++{
++	struct amdgpu_bo_va_mapping *mapping, *tmp;
++	int i;
++
++	if (!RB_EMPTY_ROOT(&vm->va)) {
++		dev_err(adev->dev, "still active bo inside vm\n");
++	}
++	rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
++		list_del(&mapping->list);
++		interval_tree_remove(&mapping->it, &vm->va);
++		kfree(mapping);
++	}
++	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
++		list_del(&mapping->list);
++		kfree(mapping);
++	}
++
++	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
++		amdgpu_bo_unref(&vm->page_tables[i].bo);
++	kfree(vm->page_tables);
++
++	amdgpu_bo_unref(&vm->page_directory);
++
++	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
++		amdgpu_fence_unref(&vm->ids[i].flushed_updates);
++		amdgpu_fence_unref(&vm->ids[i].last_id_use);
++	}
++
++	mutex_destroy(&vm->mutex);
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/atom-bits.h b/drivers/gpu/drm/amd/amdgpu/atom-bits.h
+new file mode 100644
+index 0000000..e8fae5c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atom-bits.h
+@@ -0,0 +1,48 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Author: Stanislaw Skowronek
++ */
++
++#ifndef ATOM_BITS_H
++#define ATOM_BITS_H
++
++static inline uint8_t get_u8(void *bios, int ptr)
++{
++    return ((unsigned char *)bios)[ptr];
++}
++#define U8(ptr) get_u8(ctx->ctx->bios, (ptr))
++#define CU8(ptr) get_u8(ctx->bios, (ptr))
++static inline uint16_t get_u16(void *bios, int ptr)
++{
++    return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
++}
++#define U16(ptr) get_u16(ctx->ctx->bios, (ptr))
++#define CU16(ptr) get_u16(ctx->bios, (ptr))
++static inline uint32_t get_u32(void *bios, int ptr)
++{
++    return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);
++}
++#define U32(ptr) get_u32(ctx->ctx->bios, (ptr))
++#define CU32(ptr) get_u32(ctx->bios, (ptr))
++#define CSTR(ptr) (((char *)(ctx->bios))+(ptr))
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atom-names.h b/drivers/gpu/drm/amd/amdgpu/atom-names.h
+new file mode 100644
+index 0000000..6f907a5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atom-names.h
+@@ -0,0 +1,100 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Author: Stanislaw Skowronek
++ */
++
++#ifndef ATOM_NAMES_H
++#define ATOM_NAMES_H
++
++#include "atom.h"
++
++#ifdef ATOM_DEBUG
++
++#define ATOM_OP_NAMES_CNT 123
++static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
++"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
++"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
++"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
++"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
++"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
++"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
++"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
++"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
++"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
++"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
++"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
++"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
++"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
++"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
++"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
++"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
++"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
++"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
++"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
++"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
++"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
++"DEBUG", "CTB_DS",
++};
++
++#define ATOM_TABLE_NAMES_CNT 74
++static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
++"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
++"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
++"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
++"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
++"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
++"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
++"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
++"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
++"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
++"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
++"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
++"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
++"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
++"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
++"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
++"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
++"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
++"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
++"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
++"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
++"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
++"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
++"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
++"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
++"MemoryDeviceInit", "EnableYUV",
++};
++
++#define ATOM_IO_NAMES_CNT 5
++static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
++"MM", "PLL", "MC", "PCIE", "PCIE PORT",
++};
++
++#else
++
++#define ATOM_OP_NAMES_CNT 0
++#define ATOM_TABLE_NAMES_CNT 0
++#define ATOM_IO_NAMES_CNT 0
++
++#endif
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atom-types.h b/drivers/gpu/drm/amd/amdgpu/atom-types.h
+new file mode 100644
+index 0000000..1125b86
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atom-types.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Author: Dave Airlie
++ */
++
++#ifndef ATOM_TYPES_H
++#define ATOM_TYPES_H
++
++/* sync atom types to kernel types */
++
++typedef uint16_t USHORT;
++typedef uint32_t ULONG;
++typedef uint8_t UCHAR;
++
++
++#ifndef ATOM_BIG_ENDIAN
++#if defined(__BIG_ENDIAN)
++#define ATOM_BIG_ENDIAN 1
++#else
++#define ATOM_BIG_ENDIAN 0
++#endif
++#endif
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
+new file mode 100644
+index 0000000..a0346a9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atom.c
+@@ -0,0 +1,1408 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Author: Stanislaw Skowronek
++ */
++
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <asm/unaligned.h>
++
++#define ATOM_DEBUG
++
++#include "atom.h"
++#include "atom-names.h"
++#include "atom-bits.h"
++#include "amdgpu.h"
++
++#define ATOM_COND_ABOVE		0
++#define ATOM_COND_ABOVEOREQUAL	1
++#define ATOM_COND_ALWAYS	2
++#define ATOM_COND_BELOW		3
++#define ATOM_COND_BELOWOREQUAL	4
++#define ATOM_COND_EQUAL		5
++#define ATOM_COND_NOTEQUAL	6
++
++#define ATOM_PORT_ATI	0
++#define ATOM_PORT_PCI	1
++#define ATOM_PORT_SYSIO	2
++
++#define ATOM_UNIT_MICROSEC	0
++#define ATOM_UNIT_MILLISEC	1
++
++#define PLL_INDEX	2
++#define PLL_DATA	3
++
++typedef struct {
++	struct atom_context *ctx;
++	uint32_t *ps, *ws;
++	int ps_shift;
++	uint16_t start;
++	unsigned last_jump;
++	unsigned long last_jump_jiffies;
++	bool abort;
++} atom_exec_context;
++
++int amdgpu_atom_debug = 0;
++static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
++int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
++
++static uint32_t atom_arg_mask[8] =
++    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
++0xFF000000 };
++static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
++
++static int atom_dst_to_src[8][4] = {
++	/* translate destination alignment field to the source alignment encoding */
++	{0, 0, 0, 0},
++	{1, 2, 3, 0},
++	{1, 2, 3, 0},
++	{1, 2, 3, 0},
++	{4, 5, 6, 7},
++	{4, 5, 6, 7},
++	{4, 5, 6, 7},
++	{4, 5, 6, 7},
++};
++static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
++
++static int debug_depth = 0;
++#ifdef ATOM_DEBUG
++static void debug_print_spaces(int n)
++{
++	while (n--)
++		printk("   ");
++}
++
++#define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
++#define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
++#else
++#define DEBUG(...) do { } while (0)
++#define SDEBUG(...) do { } while (0)
++#endif
++
++static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
++				 uint32_t index, uint32_t data)
++{
++	uint32_t temp = 0xCDCDCDCD;
++
++	while (1)
++		switch (CU8(base)) {
++		case ATOM_IIO_NOP:
++			base++;
++			break;
++		case ATOM_IIO_READ:
++			temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
++			base += 3;
++			break;
++		case ATOM_IIO_WRITE:
++			ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
++			base += 3;
++			break;
++		case ATOM_IIO_CLEAR:
++			temp &=
++			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
++			      CU8(base + 2));
++			base += 3;
++			break;
++		case ATOM_IIO_SET:
++			temp |=
++			    (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
++									2);
++			base += 3;
++			break;
++		case ATOM_IIO_MOVE_INDEX:
++			temp &=
++			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
++			      CU8(base + 3));
++			temp |=
++			    ((index >> CU8(base + 2)) &
++			     (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
++									  3);
++			base += 4;
++			break;
++		case ATOM_IIO_MOVE_DATA:
++			temp &=
++			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
++			      CU8(base + 3));
++			temp |=
++			    ((data >> CU8(base + 2)) &
++			     (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
++									  3);
++			base += 4;
++			break;
++		case ATOM_IIO_MOVE_ATTR:
++			temp &=
++			    ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
++			      CU8(base + 3));
++			temp |=
++			    ((ctx->
++			      io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
++									  CU8
++									  (base
++									   +
++									   1))))
++			    << CU8(base + 3);
++			base += 4;
++			break;
++		case ATOM_IIO_END:
++			return temp;
++		default:
++			printk(KERN_INFO "Unknown IIO opcode.\n");
++			return 0;
++		}
++}
++
++static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
++				 int *ptr, uint32_t *saved, int print)
++{
++	uint32_t idx, val = 0xCDCDCDCD, align, arg;
++	struct atom_context *gctx = ctx->ctx;
++	arg = attr & 7;
++	align = (attr >> 3) & 7;
++	switch (arg) {
++	case ATOM_ARG_REG:
++		idx = U16(*ptr);
++		(*ptr) += 2;
++		if (print)
++			DEBUG("REG[0x%04X]", idx);
++		idx += gctx->reg_block;
++		switch (gctx->io_mode) {
++		case ATOM_IO_MM:
++			val = gctx->card->reg_read(gctx->card, idx);
++			break;
++		case ATOM_IO_PCI:
++			printk(KERN_INFO
++			       "PCI registers are not implemented.\n");
++			return 0;
++		case ATOM_IO_SYSIO:
++			printk(KERN_INFO
++			       "SYSIO registers are not implemented.\n");
++			return 0;
++		default:
++			if (!(gctx->io_mode & 0x80)) {
++				printk(KERN_INFO "Bad IO mode.\n");
++				return 0;
++			}
++			if (!gctx->iio[gctx->io_mode & 0x7F]) {
++				printk(KERN_INFO
++				       "Undefined indirect IO read method %d.\n",
++				       gctx->io_mode & 0x7F);
++				return 0;
++			}
++			val =
++			    atom_iio_execute(gctx,
++					     gctx->iio[gctx->io_mode & 0x7F],
++					     idx, 0);
++		}
++		break;
++	case ATOM_ARG_PS:
++		idx = U8(*ptr);
++		(*ptr)++;
++		/* get_unaligned_le32 avoids unaligned accesses from atombios
++		 * tables, noticed on a DEC Alpha. */
++		val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
++		if (print)
++			DEBUG("PS[0x%02X,0x%04X]", idx, val);
++		break;
++	case ATOM_ARG_WS:
++		idx = U8(*ptr);
++		(*ptr)++;
++		if (print)
++			DEBUG("WS[0x%02X]", idx);
++		switch (idx) {
++		case ATOM_WS_QUOTIENT:
++			val = gctx->divmul[0];
++			break;
++		case ATOM_WS_REMAINDER:
++			val = gctx->divmul[1];
++			break;
++		case ATOM_WS_DATAPTR:
++			val = gctx->data_block;
++			break;
++		case ATOM_WS_SHIFT:
++			val = gctx->shift;
++			break;
++		case ATOM_WS_OR_MASK:
++			val = 1 << gctx->shift;
++			break;
++		case ATOM_WS_AND_MASK:
++			val = ~(1 << gctx->shift);
++			break;
++		case ATOM_WS_FB_WINDOW:
++			val = gctx->fb_base;
++			break;
++		case ATOM_WS_ATTRIBUTES:
++			val = gctx->io_attr;
++			break;
++		case ATOM_WS_REGPTR:
++			val = gctx->reg_block;
++			break;
++		default:
++			val = ctx->ws[idx];
++		}
++		break;
++	case ATOM_ARG_ID:
++		idx = U16(*ptr);
++		(*ptr) += 2;
++		if (print) {
++			if (gctx->data_block)
++				DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
++			else
++				DEBUG("ID[0x%04X]", idx);
++		}
++		val = U32(idx + gctx->data_block);
++		break;
++	case ATOM_ARG_FB:
++		idx = U8(*ptr);
++		(*ptr)++;
++		if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
++			DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
++				  gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
++			val = 0;
++		} else
++			val = gctx->scratch[(gctx->fb_base / 4) + idx];
++		if (print)
++			DEBUG("FB[0x%02X]", idx);
++		break;
++	case ATOM_ARG_IMM:
++		switch (align) {
++		case ATOM_SRC_DWORD:
++			val = U32(*ptr);
++			(*ptr) += 4;
++			if (print)
++				DEBUG("IMM 0x%08X\n", val);
++			return val;
++		case ATOM_SRC_WORD0:
++		case ATOM_SRC_WORD8:
++		case ATOM_SRC_WORD16:
++			val = U16(*ptr);
++			(*ptr) += 2;
++			if (print)
++				DEBUG("IMM 0x%04X\n", val);
++			return val;
++		case ATOM_SRC_BYTE0:
++		case ATOM_SRC_BYTE8:
++		case ATOM_SRC_BYTE16:
++		case ATOM_SRC_BYTE24:
++			val = U8(*ptr);
++			(*ptr)++;
++			if (print)
++				DEBUG("IMM 0x%02X\n", val);
++			return val;
++		}
++		return 0;
++	case ATOM_ARG_PLL:
++		idx = U8(*ptr);
++		(*ptr)++;
++		if (print)
++			DEBUG("PLL[0x%02X]", idx);
++		val = gctx->card->pll_read(gctx->card, idx);
++		break;
++	case ATOM_ARG_MC:
++		idx = U8(*ptr);
++		(*ptr)++;
++		if (print)
++			DEBUG("MC[0x%02X]", idx);
++		val = gctx->card->mc_read(gctx->card, idx);
++		break;
++	}
++	if (saved)
++		*saved = val;
++	val &= atom_arg_mask[align];
++	val >>= atom_arg_shift[align];
++	if (print)
++		switch (align) {
++		case ATOM_SRC_DWORD:
++			DEBUG(".[31:0] -> 0x%08X\n", val);
++			break;
++		case ATOM_SRC_WORD0:
++			DEBUG(".[15:0] -> 0x%04X\n", val);
++			break;
++		case ATOM_SRC_WORD8:
++			DEBUG(".[23:8] -> 0x%04X\n", val);
++			break;
++		case ATOM_SRC_WORD16:
++			DEBUG(".[31:16] -> 0x%04X\n", val);
++			break;
++		case ATOM_SRC_BYTE0:
++			DEBUG(".[7:0] -> 0x%02X\n", val);
++			break;
++		case ATOM_SRC_BYTE8:
++			DEBUG(".[15:8] -> 0x%02X\n", val);
++			break;
++		case ATOM_SRC_BYTE16:
++			DEBUG(".[23:16] -> 0x%02X\n", val);
++			break;
++		case ATOM_SRC_BYTE24:
++			DEBUG(".[31:24] -> 0x%02X\n", val);
++			break;
++		}
++	return val;
++}
++
++static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
++{
++	uint32_t align = (attr >> 3) & 7, arg = attr & 7;
++	switch (arg) {
++	case ATOM_ARG_REG:
++	case ATOM_ARG_ID:
++		(*ptr) += 2;
++		break;
++	case ATOM_ARG_PLL:
++	case ATOM_ARG_MC:
++	case ATOM_ARG_PS:
++	case ATOM_ARG_WS:
++	case ATOM_ARG_FB:
++		(*ptr)++;
++		break;
++	case ATOM_ARG_IMM:
++		switch (align) {
++		case ATOM_SRC_DWORD:
++			(*ptr) += 4;
++			return;
++		case ATOM_SRC_WORD0:
++		case ATOM_SRC_WORD8:
++		case ATOM_SRC_WORD16:
++			(*ptr) += 2;
++			return;
++		case ATOM_SRC_BYTE0:
++		case ATOM_SRC_BYTE8:
++		case ATOM_SRC_BYTE16:
++		case ATOM_SRC_BYTE24:
++			(*ptr)++;
++			return;
++		}
++		return;
++	}
++}
++
++static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
++{
++	return atom_get_src_int(ctx, attr, ptr, NULL, 1);
++}
++
++static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
++{
++	uint32_t val = 0xCDCDCDCD;
++
++	switch (align) {
++	case ATOM_SRC_DWORD:
++		val = U32(*ptr);
++		(*ptr) += 4;
++		break;
++	case ATOM_SRC_WORD0:
++	case ATOM_SRC_WORD8:
++	case ATOM_SRC_WORD16:
++		val = U16(*ptr);
++		(*ptr) += 2;
++		break;
++	case ATOM_SRC_BYTE0:
++	case ATOM_SRC_BYTE8:
++	case ATOM_SRC_BYTE16:
++	case ATOM_SRC_BYTE24:
++		val = U8(*ptr);
++		(*ptr)++;
++		break;
++	}
++	return val;
++}
++
++static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
++			     int *ptr, uint32_t *saved, int print)
++{
++	return atom_get_src_int(ctx,
++				arg | atom_dst_to_src[(attr >> 3) &
++						      7][(attr >> 6) & 3] << 3,
++				ptr, saved, print);
++}
++
++static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
++{
++	atom_skip_src_int(ctx,
++			  arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
++								 3] << 3, ptr);
++}
++
++static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
++			 int *ptr, uint32_t val, uint32_t saved)
++{
++	uint32_t align =
++	    atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
++	    val, idx;
++	struct atom_context *gctx = ctx->ctx;
++	old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
++	val <<= atom_arg_shift[align];
++	val &= atom_arg_mask[align];
++	saved &= ~atom_arg_mask[align];
++	val |= saved;
++	switch (arg) {
++	case ATOM_ARG_REG:
++		idx = U16(*ptr);
++		(*ptr) += 2;
++		DEBUG("REG[0x%04X]", idx);
++		idx += gctx->reg_block;
++		switch (gctx->io_mode) {
++		case ATOM_IO_MM:
++			if (idx == 0)
++				gctx->card->reg_write(gctx->card, idx,
++						      val << 2);
++			else
++				gctx->card->reg_write(gctx->card, idx, val);
++			break;
++		case ATOM_IO_PCI:
++			printk(KERN_INFO
++			       "PCI registers are not implemented.\n");
++			return;
++		case ATOM_IO_SYSIO:
++			printk(KERN_INFO
++			       "SYSIO registers are not implemented.\n");
++			return;
++		default:
++			if (!(gctx->io_mode & 0x80)) {
++				printk(KERN_INFO "Bad IO mode.\n");
++				return;
++			}
++			if (!gctx->iio[gctx->io_mode & 0xFF]) {
++				printk(KERN_INFO
++				       "Undefined indirect IO write method %d.\n",
++				       gctx->io_mode & 0x7F);
++				return;
++			}
++			atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
++					 idx, val);
++		}
++		break;
++	case ATOM_ARG_PS:
++		idx = U8(*ptr);
++		(*ptr)++;
++		DEBUG("PS[0x%02X]", idx);
++		ctx->ps[idx] = cpu_to_le32(val);
++		break;
++	case ATOM_ARG_WS:
++		idx = U8(*ptr);
++		(*ptr)++;
++		DEBUG("WS[0x%02X]", idx);
++		switch (idx) {
++		case ATOM_WS_QUOTIENT:
++			gctx->divmul[0] = val;
++			break;
++		case ATOM_WS_REMAINDER:
++			gctx->divmul[1] = val;
++			break;
++		case ATOM_WS_DATAPTR:
++			gctx->data_block = val;
++			break;
++		case ATOM_WS_SHIFT:
++			gctx->shift = val;
++			break;
++		case ATOM_WS_OR_MASK:
++		case ATOM_WS_AND_MASK:
++			break;
++		case ATOM_WS_FB_WINDOW:
++			gctx->fb_base = val;
++			break;
++		case ATOM_WS_ATTRIBUTES:
++			gctx->io_attr = val;
++			break;
++		case ATOM_WS_REGPTR:
++			gctx->reg_block = val;
++			break;
++		default:
++			ctx->ws[idx] = val;
++		}
++		break;
++	case ATOM_ARG_FB:
++		idx = U8(*ptr);
++		(*ptr)++;
++		if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
++			DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
++				  gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
++		} else
++			gctx->scratch[(gctx->fb_base / 4) + idx] = val;
++		DEBUG("FB[0x%02X]", idx);
++		break;
++	case ATOM_ARG_PLL:
++		idx = U8(*ptr);
++		(*ptr)++;
++		DEBUG("PLL[0x%02X]", idx);
++		gctx->card->pll_write(gctx->card, idx, val);
++		break;
++	case ATOM_ARG_MC:
++		idx = U8(*ptr);
++		(*ptr)++;
++		DEBUG("MC[0x%02X]", idx);
++		gctx->card->mc_write(gctx->card, idx, val);
++		return;
++	}
++	switch (align) {
++	case ATOM_SRC_DWORD:
++		DEBUG(".[31:0] <- 0x%08X\n", old_val);
++		break;
++	case ATOM_SRC_WORD0:
++		DEBUG(".[15:0] <- 0x%04X\n", old_val);
++		break;
++	case ATOM_SRC_WORD8:
++		DEBUG(".[23:8] <- 0x%04X\n", old_val);
++		break;
++	case ATOM_SRC_WORD16:
++		DEBUG(".[31:16] <- 0x%04X\n", old_val);
++		break;
++	case ATOM_SRC_BYTE0:
++		DEBUG(".[7:0] <- 0x%02X\n", old_val);
++		break;
++	case ATOM_SRC_BYTE8:
++		DEBUG(".[15:8] <- 0x%02X\n", old_val);
++		break;
++	case ATOM_SRC_BYTE16:
++		DEBUG(".[23:16] <- 0x%02X\n", old_val);
++		break;
++	case ATOM_SRC_BYTE24:
++		DEBUG(".[31:24] <- 0x%02X\n", old_val);
++		break;
++	}
++}
++
++static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src, saved;
++	int dptr = *ptr;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	dst += src;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src, saved;
++	int dptr = *ptr;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	dst &= src;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
++{
++	printk("ATOM BIOS beeped!\n");
++}
++
++static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
++{
++	int idx = U8((*ptr)++);
++	int r = 0;
++
++	if (idx < ATOM_TABLE_NAMES_CNT)
++		SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
++	else
++		SDEBUG("   table: %d\n", idx);
++	if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
++		r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
++	if (r) {
++		ctx->abort = true;
++	}
++}
++
++static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t saved;
++	int dptr = *ptr;
++	attr &= 0x38;
++	attr |= atom_def_dst[attr >> 3] << 6;
++	atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
++}
++
++static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src;
++	SDEBUG("   src1: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
++	SDEBUG("   src2: ");
++	src = atom_get_src(ctx, attr, ptr);
++	ctx->ctx->cs_equal = (dst == src);
++	ctx->ctx->cs_above = (dst > src);
++	SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
++	       ctx->ctx->cs_above ? "GT" : "LE");
++}
++
++static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
++{
++	unsigned count = U8((*ptr)++);
++	SDEBUG("   count: %d\n", count);
++	if (arg == ATOM_UNIT_MICROSEC)
++		udelay(count);
++	else if (!drm_can_sleep())
++		mdelay(count);
++	else
++		msleep(count);
++}
++
++static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src;
++	SDEBUG("   src1: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
++	SDEBUG("   src2: ");
++	src = atom_get_src(ctx, attr, ptr);
++	if (src != 0) {
++		ctx->ctx->divmul[0] = dst / src;
++		ctx->ctx->divmul[1] = dst % src;
++	} else {
++		ctx->ctx->divmul[0] = 0;
++		ctx->ctx->divmul[1] = 0;
++	}
++}
++
++static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
++{
++	/* functionally, a nop */
++}
++
++static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
++{
++	int execute = 0, target = U16(*ptr);
++	unsigned long cjiffies;
++
++	(*ptr) += 2;
++	switch (arg) {
++	case ATOM_COND_ABOVE:
++		execute = ctx->ctx->cs_above;
++		break;
++	case ATOM_COND_ABOVEOREQUAL:
++		execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
++		break;
++	case ATOM_COND_ALWAYS:
++		execute = 1;
++		break;
++	case ATOM_COND_BELOW:
++		execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
++		break;
++	case ATOM_COND_BELOWOREQUAL:
++		execute = !ctx->ctx->cs_above;
++		break;
++	case ATOM_COND_EQUAL:
++		execute = ctx->ctx->cs_equal;
++		break;
++	case ATOM_COND_NOTEQUAL:
++		execute = !ctx->ctx->cs_equal;
++		break;
++	}
++	if (arg != ATOM_COND_ALWAYS)
++		SDEBUG("   taken: %s\n", execute ? "yes" : "no");
++	SDEBUG("   target: 0x%04X\n", target);
++	if (execute) {
++		if (ctx->last_jump == (ctx->start + target)) {
++			cjiffies = jiffies;
++			if (time_after(cjiffies, ctx->last_jump_jiffies)) {
++				cjiffies -= ctx->last_jump_jiffies;
++				if ((jiffies_to_msecs(cjiffies) > 5000)) {
++					DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
++					ctx->abort = true;
++				}
++			} else {
++				/* jiffies wrap around we will just wait a little longer */
++				ctx->last_jump_jiffies = jiffies;
++			}
++		} else {
++			ctx->last_jump = ctx->start + target;
++			ctx->last_jump_jiffies = jiffies;
++		}
++		*ptr = ctx->start + target;
++	}
++}
++
++static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, mask, src, saved;
++	int dptr = *ptr;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
++	SDEBUG("   mask: 0x%08x", mask);
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	dst &= mask;
++	dst |= src;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t src, saved;
++	int dptr = *ptr;
++	if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
++		atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
++	else {
++		atom_skip_dst(ctx, arg, attr, ptr);
++		saved = 0xCDCDCDCD;
++	}
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, src, saved);
++}
++
++static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src;
++	SDEBUG("   src1: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
++	SDEBUG("   src2: ");
++	src = atom_get_src(ctx, attr, ptr);
++	ctx->ctx->divmul[0] = dst * src;
++}
++
++static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
++{
++	/* nothing */
++}
++
++static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src, saved;
++	int dptr = *ptr;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	dst |= src;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t val = U8((*ptr)++);
++	SDEBUG("POST card output: 0x%02X\n", val);
++}
++
++static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
++{
++	printk(KERN_INFO "unimplemented!\n");
++}
++
++static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
++{
++	printk(KERN_INFO "unimplemented!\n");
++}
++
++static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
++{
++	printk(KERN_INFO "unimplemented!\n");
++}
++
++static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
++{
++	int idx = U8(*ptr);
++	(*ptr)++;
++	SDEBUG("   block: %d\n", idx);
++	if (!idx)
++		ctx->ctx->data_block = 0;
++	else if (idx == 255)
++		ctx->ctx->data_block = ctx->start;
++	else
++		ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
++	SDEBUG("   base: 0x%04X\n", ctx->ctx->data_block);
++}
++
++static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	SDEBUG("   fb_base: ");
++	ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
++}
++
++static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
++{
++	int port;
++	switch (arg) {
++	case ATOM_PORT_ATI:
++		port = U16(*ptr);
++		if (port < ATOM_IO_NAMES_CNT)
++			SDEBUG("   port: %d (%s)\n", port, atom_io_names[port]);
++		else
++			SDEBUG("   port: %d\n", port);
++		if (!port)
++			ctx->ctx->io_mode = ATOM_IO_MM;
++		else
++			ctx->ctx->io_mode = ATOM_IO_IIO | port;
++		(*ptr) += 2;
++		break;
++	case ATOM_PORT_PCI:
++		ctx->ctx->io_mode = ATOM_IO_PCI;
++		(*ptr)++;
++		break;
++	case ATOM_PORT_SYSIO:
++		ctx->ctx->io_mode = ATOM_IO_SYSIO;
++		(*ptr)++;
++		break;
++	}
++}
++
++static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
++{
++	ctx->ctx->reg_block = U16(*ptr);
++	(*ptr) += 2;
++	SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
++}
++
++static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++), shift;
++	uint32_t saved, dst;
++	int dptr = *ptr;
++	attr &= 0x38;
++	attr |= atom_def_dst[attr >> 3] << 6;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
++	SDEBUG("   shift: %d\n", shift);
++	dst <<= shift;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++), shift;
++	uint32_t saved, dst;
++	int dptr = *ptr;
++	attr &= 0x38;
++	attr |= atom_def_dst[attr >> 3] << 6;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
++	SDEBUG("   shift: %d\n", shift);
++	dst >>= shift;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++), shift;
++	uint32_t saved, dst;
++	int dptr = *ptr;
++	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	/* op needs to full dst value */
++	dst = saved;
++	shift = atom_get_src(ctx, attr, ptr);
++	SDEBUG("   shift: %d\n", shift);
++	dst <<= shift;
++	dst &= atom_arg_mask[dst_align];
++	dst >>= atom_arg_shift[dst_align];
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++), shift;
++	uint32_t saved, dst;
++	int dptr = *ptr;
++	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	/* op needs to full dst value */
++	dst = saved;
++	shift = atom_get_src(ctx, attr, ptr);
++	SDEBUG("   shift: %d\n", shift);
++	dst >>= shift;
++	dst &= atom_arg_mask[dst_align];
++	dst >>= atom_arg_shift[dst_align];
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src, saved;
++	int dptr = *ptr;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	dst -= src;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t src, val, target;
++	SDEBUG("   switch: ");
++	src = atom_get_src(ctx, attr, ptr);
++	while (U16(*ptr) != ATOM_CASE_END)
++		if (U8(*ptr) == ATOM_CASE_MAGIC) {
++			(*ptr)++;
++			SDEBUG("   case: ");
++			val =
++			    atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
++					 ptr);
++			target = U16(*ptr);
++			if (val == src) {
++				SDEBUG("   target: %04X\n", target);
++				*ptr = ctx->start + target;
++				return;
++			}
++			(*ptr) += 2;
++		} else {
++			printk(KERN_INFO "Bad case.\n");
++			return;
++		}
++	(*ptr) += 2;
++}
++
++static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src;
++	SDEBUG("   src1: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
++	SDEBUG("   src2: ");
++	src = atom_get_src(ctx, attr, ptr);
++	ctx->ctx->cs_equal = ((dst & src) == 0);
++	SDEBUG("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
++}
++
++static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
++{
++	uint8_t attr = U8((*ptr)++);
++	uint32_t dst, src, saved;
++	int dptr = *ptr;
++	SDEBUG("   dst: ");
++	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
++	SDEBUG("   src: ");
++	src = atom_get_src(ctx, attr, ptr);
++	dst ^= src;
++	SDEBUG("   dst: ");
++	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
++}
++
++static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
++{
++	printk(KERN_INFO "unimplemented!\n");
++}
++
++static struct {
++	void (*func) (atom_exec_context *, int *, int);
++	int arg;
++} opcode_table[ATOM_OP_CNT] = {
++	{
++	NULL, 0}, {
++	atom_op_move, ATOM_ARG_REG}, {
++	atom_op_move, ATOM_ARG_PS}, {
++	atom_op_move, ATOM_ARG_WS}, {
++	atom_op_move, ATOM_ARG_FB}, {
++	atom_op_move, ATOM_ARG_PLL}, {
++	atom_op_move, ATOM_ARG_MC}, {
++	atom_op_and, ATOM_ARG_REG}, {
++	atom_op_and, ATOM_ARG_PS}, {
++	atom_op_and, ATOM_ARG_WS}, {
++	atom_op_and, ATOM_ARG_FB}, {
++	atom_op_and, ATOM_ARG_PLL}, {
++	atom_op_and, ATOM_ARG_MC}, {
++	atom_op_or, ATOM_ARG_REG}, {
++	atom_op_or, ATOM_ARG_PS}, {
++	atom_op_or, ATOM_ARG_WS}, {
++	atom_op_or, ATOM_ARG_FB}, {
++	atom_op_or, ATOM_ARG_PLL}, {
++	atom_op_or, ATOM_ARG_MC}, {
++	atom_op_shift_left, ATOM_ARG_REG}, {
++	atom_op_shift_left, ATOM_ARG_PS}, {
++	atom_op_shift_left, ATOM_ARG_WS}, {
++	atom_op_shift_left, ATOM_ARG_FB}, {
++	atom_op_shift_left, ATOM_ARG_PLL}, {
++	atom_op_shift_left, ATOM_ARG_MC}, {
++	atom_op_shift_right, ATOM_ARG_REG}, {
++	atom_op_shift_right, ATOM_ARG_PS}, {
++	atom_op_shift_right, ATOM_ARG_WS}, {
++	atom_op_shift_right, ATOM_ARG_FB}, {
++	atom_op_shift_right, ATOM_ARG_PLL}, {
++	atom_op_shift_right, ATOM_ARG_MC}, {
++	atom_op_mul, ATOM_ARG_REG}, {
++	atom_op_mul, ATOM_ARG_PS}, {
++	atom_op_mul, ATOM_ARG_WS}, {
++	atom_op_mul, ATOM_ARG_FB}, {
++	atom_op_mul, ATOM_ARG_PLL}, {
++	atom_op_mul, ATOM_ARG_MC}, {
++	atom_op_div, ATOM_ARG_REG}, {
++	atom_op_div, ATOM_ARG_PS}, {
++	atom_op_div, ATOM_ARG_WS}, {
++	atom_op_div, ATOM_ARG_FB}, {
++	atom_op_div, ATOM_ARG_PLL}, {
++	atom_op_div, ATOM_ARG_MC}, {
++	atom_op_add, ATOM_ARG_REG}, {
++	atom_op_add, ATOM_ARG_PS}, {
++	atom_op_add, ATOM_ARG_WS}, {
++	atom_op_add, ATOM_ARG_FB}, {
++	atom_op_add, ATOM_ARG_PLL}, {
++	atom_op_add, ATOM_ARG_MC}, {
++	atom_op_sub, ATOM_ARG_REG}, {
++	atom_op_sub, ATOM_ARG_PS}, {
++	atom_op_sub, ATOM_ARG_WS}, {
++	atom_op_sub, ATOM_ARG_FB}, {
++	atom_op_sub, ATOM_ARG_PLL}, {
++	atom_op_sub, ATOM_ARG_MC}, {
++	atom_op_setport, ATOM_PORT_ATI}, {
++	atom_op_setport, ATOM_PORT_PCI}, {
++	atom_op_setport, ATOM_PORT_SYSIO}, {
++	atom_op_setregblock, 0}, {
++	atom_op_setfbbase, 0}, {
++	atom_op_compare, ATOM_ARG_REG}, {
++	atom_op_compare, ATOM_ARG_PS}, {
++	atom_op_compare, ATOM_ARG_WS}, {
++	atom_op_compare, ATOM_ARG_FB}, {
++	atom_op_compare, ATOM_ARG_PLL}, {
++	atom_op_compare, ATOM_ARG_MC}, {
++	atom_op_switch, 0}, {
++	atom_op_jump, ATOM_COND_ALWAYS}, {
++	atom_op_jump, ATOM_COND_EQUAL}, {
++	atom_op_jump, ATOM_COND_BELOW}, {
++	atom_op_jump, ATOM_COND_ABOVE}, {
++	atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
++	atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
++	atom_op_jump, ATOM_COND_NOTEQUAL}, {
++	atom_op_test, ATOM_ARG_REG}, {
++	atom_op_test, ATOM_ARG_PS}, {
++	atom_op_test, ATOM_ARG_WS}, {
++	atom_op_test, ATOM_ARG_FB}, {
++	atom_op_test, ATOM_ARG_PLL}, {
++	atom_op_test, ATOM_ARG_MC}, {
++	atom_op_delay, ATOM_UNIT_MILLISEC}, {
++	atom_op_delay, ATOM_UNIT_MICROSEC}, {
++	atom_op_calltable, 0}, {
++	atom_op_repeat, 0}, {
++	atom_op_clear, ATOM_ARG_REG}, {
++	atom_op_clear, ATOM_ARG_PS}, {
++	atom_op_clear, ATOM_ARG_WS}, {
++	atom_op_clear, ATOM_ARG_FB}, {
++	atom_op_clear, ATOM_ARG_PLL}, {
++	atom_op_clear, ATOM_ARG_MC}, {
++	atom_op_nop, 0}, {
++	atom_op_eot, 0}, {
++	atom_op_mask, ATOM_ARG_REG}, {
++	atom_op_mask, ATOM_ARG_PS}, {
++	atom_op_mask, ATOM_ARG_WS}, {
++	atom_op_mask, ATOM_ARG_FB}, {
++	atom_op_mask, ATOM_ARG_PLL}, {
++	atom_op_mask, ATOM_ARG_MC}, {
++	atom_op_postcard, 0}, {
++	atom_op_beep, 0}, {
++	atom_op_savereg, 0}, {
++	atom_op_restorereg, 0}, {
++	atom_op_setdatablock, 0}, {
++	atom_op_xor, ATOM_ARG_REG}, {
++	atom_op_xor, ATOM_ARG_PS}, {
++	atom_op_xor, ATOM_ARG_WS}, {
++	atom_op_xor, ATOM_ARG_FB}, {
++	atom_op_xor, ATOM_ARG_PLL}, {
++	atom_op_xor, ATOM_ARG_MC}, {
++	atom_op_shl, ATOM_ARG_REG}, {
++	atom_op_shl, ATOM_ARG_PS}, {
++	atom_op_shl, ATOM_ARG_WS}, {
++	atom_op_shl, ATOM_ARG_FB}, {
++	atom_op_shl, ATOM_ARG_PLL}, {
++	atom_op_shl, ATOM_ARG_MC}, {
++	atom_op_shr, ATOM_ARG_REG}, {
++	atom_op_shr, ATOM_ARG_PS}, {
++	atom_op_shr, ATOM_ARG_WS}, {
++	atom_op_shr, ATOM_ARG_FB}, {
++	atom_op_shr, ATOM_ARG_PLL}, {
++	atom_op_shr, ATOM_ARG_MC}, {
++atom_op_debug, 0},};
++
++static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
++{
++	int base = CU16(ctx->cmd_table + 4 + 2 * index);
++	int len, ws, ps, ptr;
++	unsigned char op;
++	atom_exec_context ectx;
++	int ret = 0;
++
++	if (!base)
++		return -EINVAL;
++
++	len = CU16(base + ATOM_CT_SIZE_PTR);
++	ws = CU8(base + ATOM_CT_WS_PTR);
++	ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
++	ptr = base + ATOM_CT_CODE_PTR;
++
++	SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
++
++	ectx.ctx = ctx;
++	ectx.ps_shift = ps / 4;
++	ectx.start = base;
++	ectx.ps = params;
++	ectx.abort = false;
++	ectx.last_jump = 0;
++	if (ws)
++		ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
++	else
++		ectx.ws = NULL;
++
++	debug_depth++;
++	while (1) {
++		op = CU8(ptr++);
++		if (op < ATOM_OP_NAMES_CNT)
++			SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
++		else
++			SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
++		if (ectx.abort) {
++			DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
++				base, len, ws, ps, ptr - 1);
++			ret = -EINVAL;
++			goto free;
++		}
++
++		if (op < ATOM_OP_CNT && op > 0)
++			opcode_table[op].func(&ectx, &ptr,
++					      opcode_table[op].arg);
++		else
++			break;
++
++		if (op == ATOM_OP_EOT)
++			break;
++	}
++	debug_depth--;
++	SDEBUG("<<\n");
++
++free:
++	if (ws)
++		kfree(ectx.ws);
++	return ret;
++}
++
++int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
++{
++	int r;
++
++	mutex_lock(&ctx->mutex);
++	/* reset data block */
++	ctx->data_block = 0;
++	/* reset reg block */
++	ctx->reg_block = 0;
++	/* reset fb window */
++	ctx->fb_base = 0;
++	/* reset io mode */
++	ctx->io_mode = ATOM_IO_MM;
++	/* reset divmul */
++	ctx->divmul[0] = 0;
++	ctx->divmul[1] = 0;
++	r = amdgpu_atom_execute_table_locked(ctx, index, params);
++	mutex_unlock(&ctx->mutex);
++	return r;
++}
++
++static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
++
++static void atom_index_iio(struct atom_context *ctx, int base)
++{
++	ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
++	if (!ctx->iio)
++		return;
++	while (CU8(base) == ATOM_IIO_START) {
++		ctx->iio[CU8(base + 1)] = base + 2;
++		base += 2;
++		while (CU8(base) != ATOM_IIO_END)
++			base += atom_iio_len[CU8(base)];
++		base += 3;
++	}
++}
++
++struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
++{
++	int base;
++	struct atom_context *ctx =
++	    kzalloc(sizeof(struct atom_context), GFP_KERNEL);
++	char *str;
++	char name[512];
++	int i;
++
++	if (!ctx)
++		return NULL;
++
++	ctx->card = card;
++	ctx->bios = bios;
++
++	if (CU16(0) != ATOM_BIOS_MAGIC) {
++		printk(KERN_INFO "Invalid BIOS magic.\n");
++		kfree(ctx);
++		return NULL;
++	}
++	if (strncmp
++	    (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
++	     strlen(ATOM_ATI_MAGIC))) {
++		printk(KERN_INFO "Invalid ATI magic.\n");
++		kfree(ctx);
++		return NULL;
++	}
++
++	base = CU16(ATOM_ROM_TABLE_PTR);
++	if (strncmp
++	    (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
++	     strlen(ATOM_ROM_MAGIC))) {
++		printk(KERN_INFO "Invalid ATOM magic.\n");
++		kfree(ctx);
++		return NULL;
++	}
++
++	ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
++	ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
++	atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
++	if (!ctx->iio) {
++		amdgpu_atom_destroy(ctx);
++		return NULL;
++	}
++
++	str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));
++	while (*str && ((*str == '\n') || (*str == '\r')))
++		str++;
++	/* name string isn't always 0 terminated */
++	for (i = 0; i < 511; i++) {
++		name[i] = str[i];
++		if (name[i] < '.' || name[i] > 'z') {
++			name[i] = 0;
++			break;
++		}
++	}
++	printk(KERN_INFO "ATOM BIOS: %s\n", name);
++
++	return ctx;
++}
++
++int amdgpu_atom_asic_init(struct atom_context *ctx)
++{
++	int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
++	uint32_t ps[16];
++	int ret;
++
++	memset(ps, 0, 64);
++
++	ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
++	ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
++	if (!ps[0] || !ps[1])
++		return 1;
++
++	if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
++		return 1;
++	ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps);
++	if (ret)
++		return ret;
++
++	memset(ps, 0, 64);
++
++	return ret;
++}
++
++void amdgpu_atom_destroy(struct atom_context *ctx)
++{
++	kfree(ctx->iio);
++	kfree(ctx);
++}
++
++bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
++			    uint16_t * size, uint8_t * frev, uint8_t * crev,
++			    uint16_t * data_start)
++{
++	int offset = index * 2 + 4;
++	int idx = CU16(ctx->data_table + offset);
++	u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
++
++	if (!mdt[index])
++		return false;
++
++	if (size)
++		*size = CU16(idx);
++	if (frev)
++		*frev = CU8(idx + 2);
++	if (crev)
++		*crev = CU8(idx + 3);
++	*data_start = idx;
++	return true;
++}
++
++bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
++			   uint8_t * crev)
++{
++	int offset = index * 2 + 4;
++	int idx = CU16(ctx->cmd_table + offset);
++	u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
++
++	if (!mct[index])
++		return false;
++
++	if (frev)
++		*frev = CU8(idx + 2);
++	if (crev)
++		*crev = CU8(idx + 3);
++	return true;
++}
++
++int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx)
++{
++	int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
++	uint16_t data_offset;
++	int usage_bytes = 0;
++	struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
++
++	if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
++		firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
++
++		DRM_DEBUG("atom firmware requested %08x %dkb\n",
++			  le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
++			  le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
++
++		usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
++	}
++	ctx->scratch_size_bytes = 0;
++	if (usage_bytes == 0)
++		usage_bytes = 20 * 1024;
++	/* allocate some scratch memory */
++	ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
++	if (!ctx->scratch)
++		return -ENOMEM;
++	ctx->scratch_size_bytes = usage_bytes;
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h
+new file mode 100644
+index 0000000..09d0f82
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atom.h
+@@ -0,0 +1,159 @@
++/*
++ * Copyright 2008 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Author: Stanislaw Skowronek
++ */
++
++#ifndef ATOM_H
++#define ATOM_H
++
++#include <linux/types.h>
++#include <drm/drmP.h>
++
++#define ATOM_BIOS_MAGIC		0xAA55
++#define ATOM_ATI_MAGIC_PTR	0x30
++#define ATOM_ATI_MAGIC		" 761295520"
++#define ATOM_ROM_TABLE_PTR	0x48
++
++#define ATOM_ROM_MAGIC		"ATOM"
++#define ATOM_ROM_MAGIC_PTR	4
++
++#define ATOM_ROM_MSG_PTR	0x10
++#define ATOM_ROM_CMD_PTR	0x1E
++#define ATOM_ROM_DATA_PTR	0x20
++
++#define ATOM_CMD_INIT		0
++#define ATOM_CMD_SETSCLK	0x0A
++#define ATOM_CMD_SETMCLK	0x0B
++#define ATOM_CMD_SETPCLK	0x0C
++#define ATOM_CMD_SPDFANCNTL	0x39
++
++#define ATOM_DATA_FWI_PTR	0xC
++#define ATOM_DATA_IIO_PTR	0x32
++
++#define ATOM_FWI_DEFSCLK_PTR	8
++#define ATOM_FWI_DEFMCLK_PTR	0xC
++#define ATOM_FWI_MAXSCLK_PTR	0x24
++#define ATOM_FWI_MAXMCLK_PTR	0x28
++
++#define ATOM_CT_SIZE_PTR	0
++#define ATOM_CT_WS_PTR		4
++#define ATOM_CT_PS_PTR		5
++#define ATOM_CT_PS_MASK		0x7F
++#define ATOM_CT_CODE_PTR	6
++
++#define ATOM_OP_CNT		123
++#define ATOM_OP_EOT		91
++
++#define ATOM_CASE_MAGIC		0x63
++#define ATOM_CASE_END		0x5A5A
++
++#define ATOM_ARG_REG		0
++#define ATOM_ARG_PS		1
++#define ATOM_ARG_WS		2
++#define ATOM_ARG_FB		3
++#define ATOM_ARG_ID		4
++#define ATOM_ARG_IMM		5
++#define ATOM_ARG_PLL		6
++#define ATOM_ARG_MC		7
++
++#define ATOM_SRC_DWORD		0
++#define ATOM_SRC_WORD0		1
++#define ATOM_SRC_WORD8		2
++#define ATOM_SRC_WORD16		3
++#define ATOM_SRC_BYTE0		4
++#define ATOM_SRC_BYTE8		5
++#define ATOM_SRC_BYTE16		6
++#define ATOM_SRC_BYTE24		7
++
++#define ATOM_WS_QUOTIENT	0x40
++#define ATOM_WS_REMAINDER	0x41
++#define ATOM_WS_DATAPTR		0x42
++#define ATOM_WS_SHIFT		0x43
++#define ATOM_WS_OR_MASK		0x44
++#define ATOM_WS_AND_MASK	0x45
++#define ATOM_WS_FB_WINDOW	0x46
++#define ATOM_WS_ATTRIBUTES	0x47
++#define ATOM_WS_REGPTR  	0x48
++
++#define ATOM_IIO_NOP		0
++#define ATOM_IIO_START		1
++#define ATOM_IIO_READ		2
++#define ATOM_IIO_WRITE		3
++#define ATOM_IIO_CLEAR		4
++#define ATOM_IIO_SET		5
++#define ATOM_IIO_MOVE_INDEX	6
++#define ATOM_IIO_MOVE_ATTR	7
++#define ATOM_IIO_MOVE_DATA	8
++#define ATOM_IIO_END		9
++
++#define ATOM_IO_MM		0
++#define ATOM_IO_PCI		1
++#define ATOM_IO_SYSIO		2
++#define ATOM_IO_IIO		0x80
++
++struct card_info {
++	struct drm_device *dev;
++	void (* reg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
++	uint32_t (* reg_read)(struct card_info *, uint32_t);          /*  filled by driver */
++	void (* ioreg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
++	uint32_t (* ioreg_read)(struct card_info *, uint32_t);          /*  filled by driver */
++	void (* mc_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
++	uint32_t (* mc_read)(struct card_info *, uint32_t);          /*  filled by driver */
++	void (* pll_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
++	uint32_t (* pll_read)(struct card_info *, uint32_t);          /*  filled by driver */
++};
++
++struct atom_context {
++	struct card_info *card;
++	struct mutex mutex;
++	void *bios;
++	uint32_t cmd_table, data_table;
++	uint16_t *iio;
++
++	uint16_t data_block;
++	uint32_t fb_base;
++	uint32_t divmul[2];
++	uint16_t io_attr;
++	uint16_t reg_block;
++	uint8_t shift;
++	int cs_equal, cs_above;
++	int io_mode;
++	uint32_t *scratch;
++	int scratch_size_bytes;
++};
++
++extern int amdgpu_atom_debug;
++
++struct atom_context *amdgpu_atom_parse(struct card_info *, void *);
++int amdgpu_atom_execute_table(struct atom_context *, int, uint32_t *);
++int amdgpu_atom_asic_init(struct atom_context *);
++void amdgpu_atom_destroy(struct atom_context *);
++bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
++			    uint8_t *frev, uint8_t *crev, uint16_t *data_start);
++bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index,
++			   uint8_t *frev, uint8_t *crev);
++int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx);
++#include "atom-types.h"
++#include "atombios.h"
++#include "ObjectID.h"
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
+new file mode 100644
+index 0000000..49aa350
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
+@@ -0,0 +1,807 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/amdgpu_drm.h>
++#include <drm/drm_fixed.h>
++#include "amdgpu.h"
++#include "atom.h"
++#include "atom-bits.h"
++#include "atombios_encoders.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_pll.h"
++#include "amdgpu_connectors.h"
++
++void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode,
++				  struct drm_display_mode *adjusted_mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
++	int a1, a2;
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucCRTC = amdgpu_crtc->crtc_id;
++
++	switch (amdgpu_crtc->rmx_type) {
++	case RMX_CENTER:
++		args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
++		args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
++		args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
++		args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
++		break;
++	case RMX_ASPECT:
++		a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
++		a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
++
++		if (a1 > a2) {
++			args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
++			args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
++		} else if (a2 > a1) {
++			args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
++			args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
++		}
++		break;
++	case RMX_FULL:
++	default:
++		args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border);
++		args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border);
++		args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border);
++		args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border);
++		break;
++	}
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	ENABLE_SCALER_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucScaler = amdgpu_crtc->crtc_id;
++
++	switch (amdgpu_crtc->rmx_type) {
++	case RMX_FULL:
++		args.ucEnable = ATOM_SCALER_EXPANSION;
++		break;
++	case RMX_CENTER:
++		args.ucEnable = ATOM_SCALER_CENTER;
++		break;
++	case RMX_ASPECT:
++		args.ucEnable = ATOM_SCALER_EXPANSION;
++		break;
++	default:
++		args.ucEnable = ATOM_SCALER_DISABLE;
++		break;
++	}
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int index =
++	    GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
++	ENABLE_CRTC_PS_ALLOCATION args;
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucCRTC = amdgpu_crtc->crtc_id;
++	args.ucEnable = lock;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
++	ENABLE_CRTC_PS_ALLOCATION args;
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucCRTC = amdgpu_crtc->crtc_id;
++	args.ucEnable = state;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
++	BLANK_CRTC_PS_ALLOCATION args;
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucCRTC = amdgpu_crtc->crtc_id;
++	args.ucBlanking = state;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
++	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucDispPipeId = amdgpu_crtc->crtc_id;
++	args.ucEnable = state;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev)
++{
++	int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
++	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
++
++	memset(&args, 0, sizeof(args));
++
++	args.ucEnable = ATOM_INIT;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
++	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
++	u16 misc = 0;
++
++	memset(&args, 0, sizeof(args));
++	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
++	args.usH_Blanking_Time =
++		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));
++	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));
++	args.usV_Blanking_Time =
++		cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));
++	args.usH_SyncOffset =
++		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);
++	args.usH_SyncWidth =
++		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
++	args.usV_SyncOffset =
++		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);
++	args.usV_SyncWidth =
++		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
++	args.ucH_Border = amdgpu_crtc->h_border;
++	args.ucV_Border = amdgpu_crtc->v_border;
++
++	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
++		misc |= ATOM_VSYNC_POLARITY;
++	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
++		misc |= ATOM_HSYNC_POLARITY;
++	if (mode->flags & DRM_MODE_FLAG_CSYNC)
++		misc |= ATOM_COMPOSITESYNC;
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		misc |= ATOM_INTERLACE;
++	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
++		misc |= ATOM_DOUBLE_CLOCK_MODE;
++
++	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
++	args.ucCRTC = amdgpu_crtc->crtc_id;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++union atom_enable_ss {
++	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
++	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
++	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
++};
++
++static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev,
++				     int enable,
++				     int pll_id,
++				     int crtc_id,
++				     struct amdgpu_atom_ss *ss)
++{
++	unsigned i;
++	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
++	union atom_enable_ss args;
++
++	if (enable) {
++		/* Don't mess with SS if percentage is 0 or external ss.
++		 * SS is already disabled previously, and disabling it
++		 * again can cause display problems if the pll is already
++		 * programmed.
++		 */
++		if (ss->percentage == 0)
++			return;
++		if (ss->type & ATOM_EXTERNAL_SS_MASK)
++			return;
++	} else {
++		for (i = 0; i < adev->mode_info.num_crtc; i++) {
++			if (adev->mode_info.crtcs[i] &&
++			    adev->mode_info.crtcs[i]->enabled &&
++			    i != crtc_id &&
++			    pll_id == adev->mode_info.crtcs[i]->pll_id) {
++				/* one other crtc is using this pll don't turn
++				 * off spread spectrum as it might turn off
++				 * display on active crtc
++				 */
++				return;
++			}
++		}
++	}
++
++	memset(&args, 0, sizeof(args));
++
++	args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
++	args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
++	switch (pll_id) {
++	case ATOM_PPLL1:
++		args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
++		break;
++	case ATOM_PPLL2:
++		args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
++		break;
++	case ATOM_DCPLL:
++		args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
++		break;
++	case ATOM_PPLL_INVALID:
++		return;
++	}
++	args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
++	args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
++	args.v3.ucEnable = enable;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++union adjust_pixel_clock {
++	ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
++	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
++};
++
++static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
++				    struct drm_display_mode *mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct drm_encoder *encoder = amdgpu_crtc->encoder;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	u32 adjusted_clock = mode->clock;
++	int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++	u32 dp_clock = mode->clock;
++	u32 clock = mode->clock;
++	int bpc = amdgpu_crtc->bpc;
++	bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
++	union adjust_pixel_clock args;
++	u8 frev, crev;
++	int index;
++
++	amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
++
++	if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
++	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
++		if (connector) {
++			struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++			struct amdgpu_connector_atom_dig *dig_connector =
++				amdgpu_connector->con_priv;
++
++			dp_clock = dig_connector->dp_clock;
++		}
++	}
++
++	/* use recommended ref_div for ss */
++	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++		if (amdgpu_crtc->ss_enabled) {
++			if (amdgpu_crtc->ss.refdiv) {
++				amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
++				amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv;
++				amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
++			}
++		}
++	}
++
++	/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
++	if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
++		adjusted_clock = mode->clock * 2;
++	if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++		amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER;
++	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++		amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD;
++
++
++	/* adjust pll for deep color modes */
++	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
++		switch (bpc) {
++		case 8:
++		default:
++			break;
++		case 10:
++			clock = (clock * 5) / 4;
++			break;
++		case 12:
++			clock = (clock * 3) / 2;
++			break;
++		case 16:
++			clock = clock * 2;
++			break;
++		}
++	}
++
++	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
++	 * accordingly based on the encoder/transmitter to work around
++	 * special hw requirements.
++	 */
++	index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
++				   &crev))
++		return adjusted_clock;
++
++	memset(&args, 0, sizeof(args));
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 1:
++		case 2:
++			args.v1.usPixelClock = cpu_to_le16(clock / 10);
++			args.v1.ucTransmitterID = amdgpu_encoder->encoder_id;
++			args.v1.ucEncodeMode = encoder_mode;
++			if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
++				args.v1.ucConfig |=
++					ADJUST_DISPLAY_CONFIG_SS_ENABLE;
++
++			amdgpu_atom_execute_table(adev->mode_info.atom_context,
++					   index, (uint32_t *)&args);
++			adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
++			break;
++		case 3:
++			args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
++			args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id;
++			args.v3.sInput.ucEncodeMode = encoder_mode;
++			args.v3.sInput.ucDispPllConfig = 0;
++			if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
++				args.v3.sInput.ucDispPllConfig |=
++					DISPPLL_CONFIG_SS_ENABLE;
++			if (ENCODER_MODE_IS_DP(encoder_mode)) {
++				args.v3.sInput.ucDispPllConfig |=
++					DISPPLL_CONFIG_COHERENT_MODE;
++				/* 16200 or 27000 */
++				args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
++			} else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
++				struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++				if (dig->coherent_mode)
++					args.v3.sInput.ucDispPllConfig |=
++						DISPPLL_CONFIG_COHERENT_MODE;
++				if (is_duallink)
++					args.v3.sInput.ucDispPllConfig |=
++						DISPPLL_CONFIG_DUAL_LINK;
++			}
++			if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
++			    ENCODER_OBJECT_ID_NONE)
++				args.v3.sInput.ucExtTransmitterID =
++					amdgpu_encoder_get_dp_bridge_encoder_id(encoder);
++			else
++				args.v3.sInput.ucExtTransmitterID = 0;
++
++			amdgpu_atom_execute_table(adev->mode_info.atom_context,
++					   index, (uint32_t *)&args);
++			adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
++			if (args.v3.sOutput.ucRefDiv) {
++				amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
++				amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
++				amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
++			}
++			if (args.v3.sOutput.ucPostDiv) {
++				amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
++				amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV;
++				amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
++			}
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
++			return adjusted_clock;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
++		return adjusted_clock;
++	}
++
++	return adjusted_clock;
++}
++
++union set_pixel_clock {
++	SET_PIXEL_CLOCK_PS_ALLOCATION base;
++	PIXEL_CLOCK_PARAMETERS v1;
++	PIXEL_CLOCK_PARAMETERS_V2 v2;
++	PIXEL_CLOCK_PARAMETERS_V3 v3;
++	PIXEL_CLOCK_PARAMETERS_V5 v5;
++	PIXEL_CLOCK_PARAMETERS_V6 v6;
++};
++
++/* on DCE5, make sure the voltage is high enough to support the
++ * required disp clk.
++ */
++void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
++				    u32 dispclk)
++{
++	u8 frev, crev;
++	int index;
++	union set_pixel_clock args;
++
++	memset(&args, 0, sizeof(args));
++
++	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
++				   &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 5:
++			/* if the default dcpll clock is specified,
++			 * SetPixelClock provides the dividers
++			 */
++			args.v5.ucCRTC = ATOM_CRTC_INVALID;
++			args.v5.usPixelClock = cpu_to_le16(dispclk);
++			args.v5.ucPpll = ATOM_DCPLL;
++			break;
++		case 6:
++			/* if the default dcpll clock is specified,
++			 * SetPixelClock provides the dividers
++			 */
++			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
++			args.v6.ucPpll = ATOM_EXT_PLL1;
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
++			return;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
++		return;
++	}
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
++{
++	if (ENCODER_MODE_IS_DP(encoder_mode)) {
++		if (pll_id < ATOM_EXT_PLL1)
++			return true;
++		else
++			return false;
++	} else {
++		return true;
++	}
++}
++
++void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
++			       u32 crtc_id,
++			       int pll_id,
++			       u32 encoder_mode,
++			       u32 encoder_id,
++			       u32 clock,
++			       u32 ref_div,
++			       u32 fb_div,
++			       u32 frac_fb_div,
++			       u32 post_div,
++			       int bpc,
++			       bool ss_enabled,
++			       struct amdgpu_atom_ss *ss)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u8 frev, crev;
++	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
++	union set_pixel_clock args;
++
++	memset(&args, 0, sizeof(args));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
++				   &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 1:
++			if (clock == ATOM_DISABLE)
++				return;
++			args.v1.usPixelClock = cpu_to_le16(clock / 10);
++			args.v1.usRefDiv = cpu_to_le16(ref_div);
++			args.v1.usFbDiv = cpu_to_le16(fb_div);
++			args.v1.ucFracFbDiv = frac_fb_div;
++			args.v1.ucPostDiv = post_div;
++			args.v1.ucPpll = pll_id;
++			args.v1.ucCRTC = crtc_id;
++			args.v1.ucRefDivSrc = 1;
++			break;
++		case 2:
++			args.v2.usPixelClock = cpu_to_le16(clock / 10);
++			args.v2.usRefDiv = cpu_to_le16(ref_div);
++			args.v2.usFbDiv = cpu_to_le16(fb_div);
++			args.v2.ucFracFbDiv = frac_fb_div;
++			args.v2.ucPostDiv = post_div;
++			args.v2.ucPpll = pll_id;
++			args.v2.ucCRTC = crtc_id;
++			args.v2.ucRefDivSrc = 1;
++			break;
++		case 3:
++			args.v3.usPixelClock = cpu_to_le16(clock / 10);
++			args.v3.usRefDiv = cpu_to_le16(ref_div);
++			args.v3.usFbDiv = cpu_to_le16(fb_div);
++			args.v3.ucFracFbDiv = frac_fb_div;
++			args.v3.ucPostDiv = post_div;
++			args.v3.ucPpll = pll_id;
++			if (crtc_id == ATOM_CRTC2)
++				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
++			else
++				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
++			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
++				args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
++			args.v3.ucTransmitterId = encoder_id;
++			args.v3.ucEncoderMode = encoder_mode;
++			break;
++		case 5:
++			args.v5.ucCRTC = crtc_id;
++			args.v5.usPixelClock = cpu_to_le16(clock / 10);
++			args.v5.ucRefDiv = ref_div;
++			args.v5.usFbDiv = cpu_to_le16(fb_div);
++			args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
++			args.v5.ucPostDiv = post_div;
++			args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
++			if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
++			    (pll_id < ATOM_EXT_PLL1))
++				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
++			if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
++				switch (bpc) {
++				case 8:
++				default:
++					args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
++					break;
++				case 10:
++					/* yes this is correct, the atom define is wrong */
++					args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
++					break;
++				case 12:
++					/* yes this is correct, the atom define is wrong */
++					args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
++					break;
++				}
++			}
++			args.v5.ucTransmitterID = encoder_id;
++			args.v5.ucEncoderMode = encoder_mode;
++			args.v5.ucPpll = pll_id;
++			break;
++		case 6:
++			args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
++			args.v6.ucRefDiv = ref_div;
++			args.v6.usFbDiv = cpu_to_le16(fb_div);
++			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
++			args.v6.ucPostDiv = post_div;
++			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
++			if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
++			    (pll_id < ATOM_EXT_PLL1) &&
++			    !is_pixel_clock_source_from_pll(encoder_mode, pll_id))
++				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
++			if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
++				switch (bpc) {
++				case 8:
++				default:
++					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
++					break;
++				case 10:
++					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
++					break;
++				case 12:
++					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
++					break;
++				case 16:
++					args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
++					break;
++				}
++			}
++			args.v6.ucTransmitterID = encoder_id;
++			args.v6.ucEncoderMode = encoder_mode;
++			args.v6.ucPpll = pll_id;
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
++			return;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
++		return;
++	}
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc,
++			      struct drm_display_mode *mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder =
++		to_amdgpu_encoder(amdgpu_crtc->encoder);
++	int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
++
++	amdgpu_crtc->bpc = 8;
++	amdgpu_crtc->ss_enabled = false;
++
++	if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
++	    (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
++		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++		struct drm_connector *connector =
++			amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);
++		struct amdgpu_connector *amdgpu_connector =
++			to_amdgpu_connector(connector);
++		struct amdgpu_connector_atom_dig *dig_connector =
++			amdgpu_connector->con_priv;
++		int dp_clock;
++
++		/* Assign mode clock for hdmi deep color max clock limit check */
++		amdgpu_connector->pixelclock_for_modeset = mode->clock;
++		amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);
++
++		switch (encoder_mode) {
++		case ATOM_ENCODER_MODE_DP_MST:
++		case ATOM_ENCODER_MODE_DP:
++			/* DP/eDP */
++			dp_clock = dig_connector->dp_clock / 10;
++			amdgpu_crtc->ss_enabled =
++				amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss,
++								 ASIC_INTERNAL_SS_ON_DP,
++								 dp_clock);
++			break;
++		case ATOM_ENCODER_MODE_LVDS:
++			amdgpu_crtc->ss_enabled =
++				amdgpu_atombios_get_asic_ss_info(adev,
++								 &amdgpu_crtc->ss,
++								 dig->lcd_ss_id,
++								 mode->clock / 10);
++			break;
++		case ATOM_ENCODER_MODE_DVI:
++			amdgpu_crtc->ss_enabled =
++				amdgpu_atombios_get_asic_ss_info(adev,
++								 &amdgpu_crtc->ss,
++								 ASIC_INTERNAL_SS_ON_TMDS,
++								 mode->clock / 10);
++			break;
++		case ATOM_ENCODER_MODE_HDMI:
++			amdgpu_crtc->ss_enabled =
++				amdgpu_atombios_get_asic_ss_info(adev,
++								 &amdgpu_crtc->ss,
++								 ASIC_INTERNAL_SS_ON_HDMI,
++								 mode->clock / 10);
++			break;
++		default:
++			break;
++		}
++	}
++
++	/* adjust pixel clock as needed */
++	amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);
++
++	return 0;
++}
++
++void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder =
++		to_amdgpu_encoder(amdgpu_crtc->encoder);
++	u32 pll_clock = mode->clock;
++	u32 clock = mode->clock;
++	u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
++	struct amdgpu_pll *pll;
++	int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
++
++	/* pass the actual clock to amdgpu_atombios_crtc_program_pll for HDMI */
++	if ((encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
++	    (amdgpu_crtc->bpc > 8))
++		clock = amdgpu_crtc->adjusted_clock;
++
++	switch (amdgpu_crtc->pll_id) {
++	case ATOM_PPLL1:
++		pll = &adev->clock.ppll[0];
++		break;
++	case ATOM_PPLL2:
++		pll = &adev->clock.ppll[1];
++		break;
++	case ATOM_PPLL0:
++	case ATOM_PPLL_INVALID:
++	default:
++		pll = &adev->clock.ppll[2];
++		break;
++	}
++
++	/* update pll params */
++	pll->flags = amdgpu_crtc->pll_flags;
++	pll->reference_div = amdgpu_crtc->pll_reference_div;
++	pll->post_div = amdgpu_crtc->pll_post_div;
++
++	amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock,
++			    &fb_div, &frac_fb_div, &ref_div, &post_div);
++
++	amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,
++				 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
++
++	amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
++				  encoder_mode, amdgpu_encoder->encoder_id, clock,
++				  ref_div, fb_div, frac_fb_div, post_div,
++				  amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
++
++	if (amdgpu_crtc->ss_enabled) {
++		/* calculate ss amount and step size */
++		u32 step_size;
++		u32 amount = (((fb_div * 10) + frac_fb_div) *
++			      (u32)amdgpu_crtc->ss.percentage) /
++			(100 * (u32)amdgpu_crtc->ss.percentage_divider);
++		amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
++		amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
++			ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
++		if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
++			step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
++				(125 * 25 * pll->reference_freq / 100);
++		else
++			step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
++				(125 * 25 * pll->reference_freq / 100);
++		amdgpu_crtc->ss.step = step_size;
++
++		amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,
++					 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
++	}
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h
+new file mode 100644
+index 0000000..c670833
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h
+@@ -0,0 +1,58 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __ATOMBIOS_CRTC_H__
++#define __ATOMBIOS_CRTC_H__
++
++void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode,
++				  struct drm_display_mode *adjusted_mode);
++void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc);
++void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock);
++void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state);
++void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state);
++void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state);
++void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev);
++void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode);
++void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
++				    u32 dispclk);
++void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
++			       u32 crtc_id,
++			       int pll_id,
++			       u32 encoder_mode,
++			       u32 encoder_id,
++			       u32 clock,
++			       u32 ref_div,
++			       u32 fb_div,
++			       u32 frac_fb_div,
++			       u32 post_div,
++			       int bpc,
++			       bool ss_enabled,
++			       struct amdgpu_atom_ss *ss);
++int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc,
++			      struct drm_display_mode *mode);
++void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc,
++			   struct drm_display_mode *mode);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+new file mode 100644
+index 0000000..e00b8ad
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -0,0 +1,774 @@
++/*
++ * Copyright 2007-8 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ *          Jerome Glisse
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++
++#include "atom.h"
++#include "atom-bits.h"
++#include "atombios_encoders.h"
++#include "atombios_dp.h"
++#include "amdgpu_connectors.h"
++#include "amdgpu_atombios.h"
++#include <drm/drm_dp_helper.h>
++
++/* move these to drm_dp_helper.c/h */
++#define DP_LINK_CONFIGURATION_SIZE 9
++#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
++
++static char *voltage_names[] = {
++	"0.4V", "0.6V", "0.8V", "1.2V"
++};
++static char *pre_emph_names[] = {
++	"0dB", "3.5dB", "6dB", "9.5dB"
++};
++
++/***** amdgpu AUX functions *****/
++
++union aux_channel_transaction {
++	PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
++	PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
++};
++
++static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
++				      u8 *send, int send_bytes,
++				      u8 *recv, int recv_size,
++				      u8 delay, u8 *ack)
++{
++	struct drm_device *dev = chan->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	union aux_channel_transaction args;
++	int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
++	unsigned char *base;
++	int recv_bytes;
++	int r = 0;
++
++	memset(&args, 0, sizeof(args));
++
++	mutex_lock(&chan->mutex);
++
++	base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
++
++	amdgpu_atombios_copy_swap(base, send, send_bytes, true);
++
++	args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
++	args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
++	args.v2.ucDataOutLen = 0;
++	args.v2.ucChannelID = chan->rec.i2c_id;
++	args.v2.ucDelay = delay / 10;
++	args.v2.ucHPD_ID = chan->rec.hpd;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++	*ack = args.v2.ucReplyStatus;
++
++	/* timeout */
++	if (args.v2.ucReplyStatus == 1) {
++		DRM_DEBUG_KMS("dp_aux_ch timeout\n");
++		r = -ETIMEDOUT;
++		goto done;
++	}
++
++	/* flags not zero */
++	if (args.v2.ucReplyStatus == 2) {
++		DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
++		r = -EIO;
++		goto done;
++	}
++
++	/* error */
++	if (args.v2.ucReplyStatus == 3) {
++		DRM_DEBUG_KMS("dp_aux_ch error\n");
++		r = -EIO;
++		goto done;
++	}
++
++	recv_bytes = args.v1.ucDataOutLen;
++	if (recv_bytes > recv_size)
++		recv_bytes = recv_size;
++
++	if (recv && recv_size)
++		amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
++
++	r = recv_bytes;
++done:
++	mutex_unlock(&chan->mutex);
++
++	return r;
++}
++
++#define BARE_ADDRESS_SIZE 3
++#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
++
++static ssize_t
++amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
++{
++	struct amdgpu_i2c_chan *chan =
++		container_of(aux, struct amdgpu_i2c_chan, aux);
++	int ret;
++	u8 tx_buf[20];
++	size_t tx_size;
++	u8 ack, delay = 0;
++
++	if (WARN_ON(msg->size > 16))
++		return -E2BIG;
++
++	tx_buf[0] = msg->address & 0xff;
++	tx_buf[1] = msg->address >> 8;
++	tx_buf[2] = msg->request << 4;
++	tx_buf[3] = msg->size ? (msg->size - 1) : 0;
++
++	switch (msg->request & ~DP_AUX_I2C_MOT) {
++	case DP_AUX_NATIVE_WRITE:
++	case DP_AUX_I2C_WRITE:
++		/* tx_size needs to be 4 even for bare address packets since the atom
++		 * table needs the info in tx_buf[3].
++		 */
++		tx_size = HEADER_SIZE + msg->size;
++		if (msg->size == 0)
++			tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
++		else
++			tx_buf[3] |= tx_size << 4;
++		memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
++		ret = amdgpu_atombios_dp_process_aux_ch(chan,
++						 tx_buf, tx_size, NULL, 0, delay, &ack);
++		if (ret >= 0)
++			/* Return payload size. */
++			ret = msg->size;
++		break;
++	case DP_AUX_NATIVE_READ:
++	case DP_AUX_I2C_READ:
++		/* tx_size needs to be 4 even for bare address packets since the atom
++		 * table needs the info in tx_buf[3].
++		 */
++		tx_size = HEADER_SIZE;
++		if (msg->size == 0)
++			tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
++		else
++			tx_buf[3] |= tx_size << 4;
++		ret = amdgpu_atombios_dp_process_aux_ch(chan,
++						 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	if (ret >= 0)
++		msg->reply = ack >> 4;
++
++	return ret;
++}
++
++void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
++{
++	int ret;
++
++	amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
++	amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
++	amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
++	ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
++	if (!ret)
++		amdgpu_connector->ddc_bus->has_aux = true;
++
++	WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
++}
++
++/***** general DP utility functions *****/
++
++#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
++#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
++
++static void amdgpu_atombios_dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
++					 int lane_count,
++					 u8 train_set[4])
++{
++	u8 v = 0;
++	u8 p = 0;
++	int lane;
++
++	for (lane = 0; lane < lane_count; lane++) {
++		u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
++		u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
++
++		DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
++			  lane,
++			  voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
++			  pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
++
++		if (this_v > v)
++			v = this_v;
++		if (this_p > p)
++			p = this_p;
++	}
++
++	if (v >= DP_VOLTAGE_MAX)
++		v |= DP_TRAIN_MAX_SWING_REACHED;
++
++	if (p >= DP_PRE_EMPHASIS_MAX)
++		p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
++
++	DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
++		  voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
++		  pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
++
++	for (lane = 0; lane < 4; lane++)
++		train_set[lane] = v | p;
++}
++
++/* convert bits per color to bits per pixel */
++/* get bpc from the EDID */
++static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
++{
++	if (bpc == 0)
++		return 24;
++	else
++		return bpc * 3;
++}
++
++/* get the max pix clock supported by the link rate and lane num */
++static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate,
++					    int lane_num,
++					    int bpp)
++{
++	return (link_rate * lane_num * 8) / bpp;
++}
++
++/***** amdgpu specific DP functions *****/
++
++/* First get the min lane# when low rate is used according to pixel clock
++ * (prefer low rate), second check max lane# supported by DP panel,
++ * if the max lane# < low rate lane# then use max lane# instead.
++ */
++static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector,
++					  u8 dpcd[DP_DPCD_SIZE],
++					  int pix_clock)
++{
++	int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
++	int max_link_rate = drm_dp_max_link_rate(dpcd);
++	int max_lane_num = drm_dp_max_lane_count(dpcd);
++	int lane_num;
++	int max_dp_pix_clock;
++
++	for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
++		max_dp_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
++		if (pix_clock <= max_dp_pix_clock)
++			break;
++	}
++
++	return lane_num;
++}
++
++static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector,
++					 u8 dpcd[DP_DPCD_SIZE],
++					 int pix_clock)
++{
++	int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
++	int lane_num, max_pix_clock;
++
++	if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
++	    ENCODER_OBJECT_ID_NUTMEG)
++		return 270000;
++
++	lane_num = amdgpu_atombios_dp_get_dp_lane_number(connector, dpcd, pix_clock);
++	max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(162000, lane_num, bpp);
++	if (pix_clock <= max_pix_clock)
++		return 162000;
++	max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(270000, lane_num, bpp);
++	if (pix_clock <= max_pix_clock)
++		return 270000;
++	if (amdgpu_connector_is_dp12_capable(connector)) {
++		max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(540000, lane_num, bpp);
++		if (pix_clock <= max_pix_clock)
++			return 540000;
++	}
++
++	return drm_dp_max_link_rate(dpcd);
++}
++
++static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
++				      int action, int dp_clock,
++				      u8 ucconfig, u8 lane_num)
++{
++	DP_ENCODER_SERVICE_PARAMETERS args;
++	int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
++
++	memset(&args, 0, sizeof(args));
++	args.ucLinkClock = dp_clock / 10;
++	args.ucConfig = ucconfig;
++	args.ucAction = action;
++	args.ucLaneNum = lane_num;
++	args.ucStatus = 0;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++	return args.ucStatus;
++}
++
++u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
++{
++	struct drm_device *dev = amdgpu_connector->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
++					   amdgpu_connector->ddc_bus->rec.i2c_id, 0);
++}
++
++static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
++{
++	struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
++	u8 buf[3];
++
++	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
++		return;
++
++	if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
++		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
++			      buf[0], buf[1], buf[2]);
++
++	if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
++		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
++			      buf[0], buf[1], buf[2]);
++}
++
++int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
++{
++	struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
++	u8 msg[DP_DPCD_SIZE];
++	int ret, i;
++
++	ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg,
++			       DP_DPCD_SIZE);
++	if (ret > 0) {
++		memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
++		DRM_DEBUG_KMS("DPCD: ");
++		for (i = 0; i < DP_DPCD_SIZE; i++)
++			DRM_DEBUG_KMS("%02x ", msg[i]);
++		DRM_DEBUG_KMS("\n");
++
++		amdgpu_atombios_dp_probe_oui(amdgpu_connector);
++
++		return 0;
++	}
++	dig_connector->dpcd[0] = 0;
++	return -EINVAL;
++}
++
++int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
++			       struct drm_connector *connector)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *dig_connector;
++	int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
++	u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
++	u8 tmp;
++
++	if (!amdgpu_connector->con_priv)
++		return panel_mode;
++
++	dig_connector = amdgpu_connector->con_priv;
++
++	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
++		/* DP bridge chips */
++		if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
++				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
++			if (tmp & 1)
++				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
++			else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
++				 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
++				panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
++			else
++				panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
++		}
++	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
++		/* eDP */
++		if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
++				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
++			if (tmp & 1)
++				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
++		}
++	}
++
++	return panel_mode;
++}
++
++void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
++				 const struct drm_display_mode *mode)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *dig_connector;
++
++	if (!amdgpu_connector->con_priv)
++		return;
++	dig_connector = amdgpu_connector->con_priv;
++
++	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
++	    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
++		dig_connector->dp_clock =
++			amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
++		dig_connector->dp_lane_count =
++			amdgpu_atombios_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
++	}
++}
++
++int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
++				  struct drm_display_mode *mode)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *dig_connector;
++	int dp_clock;
++
++	if (!amdgpu_connector->con_priv)
++		return MODE_CLOCK_HIGH;
++	dig_connector = amdgpu_connector->con_priv;
++
++	dp_clock =
++		amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
++
++	if ((dp_clock == 540000) &&
++	    (!amdgpu_connector_is_dp12_capable(connector)))
++		return MODE_CLOCK_HIGH;
++
++	return MODE_OK;
++}
++
++bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
++{
++	u8 link_status[DP_LINK_STATUS_SIZE];
++	struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
++
++	if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
++	    <= 0)
++		return false;
++	if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
++		return false;
++	return true;
++}
++
++void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
++				    u8 power_state)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct amdgpu_connector_atom_dig *dig_connector;
++
++	if (!amdgpu_connector->con_priv)
++		return;
++
++	dig_connector = amdgpu_connector->con_priv;
++
++	/* power up/down the sink */
++	if (dig_connector->dpcd[0] >= 0x11) {
++		drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
++				   DP_SET_POWER, power_state);
++		usleep_range(1000, 2000);
++	}
++}
++
++struct amdgpu_atombios_dp_link_train_info {
++	struct amdgpu_device *adev;
++	struct drm_encoder *encoder;
++	struct drm_connector *connector;
++	int dp_clock;
++	int dp_lane_count;
++	bool tp3_supported;
++	u8 dpcd[DP_RECEIVER_CAP_SIZE];
++	u8 train_set[4];
++	u8 link_status[DP_LINK_STATUS_SIZE];
++	u8 tries;
++	struct drm_dp_aux *aux;
++};
++
++static void
++amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
++{
++	/* set the initial vs/emph on the source */
++	amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
++					       ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
++					       0, dp_info->train_set[0]); /* sets all lanes at once */
++
++	/* set the vs/emph on the sink */
++	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
++			  dp_info->train_set, dp_info->dp_lane_count);
++}
++
++static void
++amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
++{
++	int rtp = 0;
++
++	/* set training pattern on the source */
++	switch (tp) {
++	case DP_TRAINING_PATTERN_1:
++		rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
++		break;
++	case DP_TRAINING_PATTERN_2:
++		rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
++		break;
++	case DP_TRAINING_PATTERN_3:
++		rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
++			break;
++	}
++	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
++
++	/* enable training pattern on the sink */
++	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
++}
++
++static int
++amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u8 tmp;
++
++	/* power up the sink */
++	amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
++
++	/* possibly enable downspread on the sink */
++	if (dp_info->dpcd[3] & 0x1)
++		drm_dp_dpcd_writeb(dp_info->aux,
++				   DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
++	else
++		drm_dp_dpcd_writeb(dp_info->aux,
++				   DP_DOWNSPREAD_CTRL, 0);
++
++	if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
++		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
++
++	/* set the lane count on the sink */
++	tmp = dp_info->dp_lane_count;
++	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
++		tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
++	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
++
++	/* set the link rate on the sink */
++	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
++	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
++
++	/* start training on the source */
++	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
++					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
++
++	/* disable the training pattern on the sink */
++	drm_dp_dpcd_writeb(dp_info->aux,
++			   DP_TRAINING_PATTERN_SET,
++			   DP_TRAINING_PATTERN_DISABLE);
++
++	return 0;
++}
++
++static int
++amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
++{
++	udelay(400);
++
++	/* disable the training pattern on the sink */
++	drm_dp_dpcd_writeb(dp_info->aux,
++			   DP_TRAINING_PATTERN_SET,
++			   DP_TRAINING_PATTERN_DISABLE);
++
++	/* disable the training pattern on the source */
++	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
++					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
++
++	return 0;
++}
++
++static int
++amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
++{
++	bool clock_recovery;
++	u8 voltage;
++	int i;
++
++	amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
++	memset(dp_info->train_set, 0, 4);
++	amdgpu_atombios_dp_update_vs_emph(dp_info);
++
++	udelay(400);
++
++	/* clock recovery loop */
++	clock_recovery = false;
++	dp_info->tries = 0;
++	voltage = 0xff;
++	while (1) {
++		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
++
++		if (drm_dp_dpcd_read_link_status(dp_info->aux,
++						 dp_info->link_status) <= 0) {
++			DRM_ERROR("displayport link status failed\n");
++			break;
++		}
++
++		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
++			clock_recovery = true;
++			break;
++		}
++
++		for (i = 0; i < dp_info->dp_lane_count; i++) {
++			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
++				break;
++		}
++		if (i == dp_info->dp_lane_count) {
++			DRM_ERROR("clock recovery reached max voltage\n");
++			break;
++		}
++
++		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
++			++dp_info->tries;
++			if (dp_info->tries == 5) {
++				DRM_ERROR("clock recovery tried 5 times\n");
++				break;
++			}
++		} else
++			dp_info->tries = 0;
++
++		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
++
++		/* Compute new train_set as requested by sink */
++		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
++					     dp_info->train_set);
++
++		amdgpu_atombios_dp_update_vs_emph(dp_info);
++	}
++	if (!clock_recovery) {
++		DRM_ERROR("clock recovery failed\n");
++		return -1;
++	} else {
++		DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
++			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
++			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
++			  DP_TRAIN_PRE_EMPHASIS_SHIFT);
++		return 0;
++	}
++}
++
++static int
++amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
++{
++	bool channel_eq;
++
++	if (dp_info->tp3_supported)
++		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
++	else
++		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
++
++	/* channel equalization loop */
++	dp_info->tries = 0;
++	channel_eq = false;
++	while (1) {
++		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
++
++		if (drm_dp_dpcd_read_link_status(dp_info->aux,
++						 dp_info->link_status) <= 0) {
++			DRM_ERROR("displayport link status failed\n");
++			break;
++		}
++
++		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
++			channel_eq = true;
++			break;
++		}
++
++		/* Try 5 times */
++		if (dp_info->tries > 5) {
++			DRM_ERROR("channel eq failed: 5 tries\n");
++			break;
++		}
++
++		/* Compute new train_set as requested by sink */
++		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
++					     dp_info->train_set);
++
++		amdgpu_atombios_dp_update_vs_emph(dp_info);
++		dp_info->tries++;
++	}
++
++	if (!channel_eq) {
++		DRM_ERROR("channel eq failed\n");
++		return -1;
++	} else {
++		DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
++			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
++			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
++			  >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
++		return 0;
++	}
++}
++
++void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
++			    struct drm_connector *connector)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig;
++	struct amdgpu_connector *amdgpu_connector;
++	struct amdgpu_connector_atom_dig *dig_connector;
++	struct amdgpu_atombios_dp_link_train_info dp_info;
++	u8 tmp;
++
++	if (!amdgpu_encoder->enc_priv)
++		return;
++	dig = amdgpu_encoder->enc_priv;
++
++	amdgpu_connector = to_amdgpu_connector(connector);
++	if (!amdgpu_connector->con_priv)
++		return;
++	dig_connector = amdgpu_connector->con_priv;
++
++	if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
++	    (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
++		return;
++
++	if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
++	    == 1) {
++		if (tmp & DP_TPS3_SUPPORTED)
++			dp_info.tp3_supported = true;
++		else
++			dp_info.tp3_supported = false;
++	} else {
++		dp_info.tp3_supported = false;
++	}
++
++	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
++	dp_info.adev = adev;
++	dp_info.encoder = encoder;
++	dp_info.connector = connector;
++	dp_info.dp_lane_count = dig_connector->dp_lane_count;
++	dp_info.dp_clock = dig_connector->dp_clock;
++	dp_info.aux = &amdgpu_connector->ddc_bus->aux;
++
++	if (amdgpu_atombios_dp_link_train_init(&dp_info))
++		goto done;
++	if (amdgpu_atombios_dp_link_train_cr(&dp_info))
++		goto done;
++	if (amdgpu_atombios_dp_link_train_ce(&dp_info))
++		goto done;
++done:
++	if (amdgpu_atombios_dp_link_train_finish(&dp_info))
++		return;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.h b/drivers/gpu/drm/amd/amdgpu/atombios_dp.h
+new file mode 100644
+index 0000000..f59d85e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __ATOMBIOS_DP_H__
++#define __ATOMBIOS_DP_H__
++
++void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector);
++u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector);
++int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector);
++int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
++			       struct drm_connector *connector);
++void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
++				 const struct drm_display_mode *mode);
++int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
++				  struct drm_display_mode *mode);
++bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector);
++void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
++				    u8 power_state);
++void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
++			    struct drm_connector *connector);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+new file mode 100644
+index 0000000..ae8caca
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+@@ -0,0 +1,2066 @@
++/*
++ * Copyright 2007-11 Advanced Micro Devices, Inc.
++ * Copyright 2008 Red Hat Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie
++ *          Alex Deucher
++ */
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "amdgpu_connectors.h"
++#include "atom.h"
++#include "atombios_encoders.h"
++#include "atombios_dp.h"
++#include <linux/backlight.h>
++#include "bif/bif_4_1_d.h"
++
++static u8
++amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
++{
++	u8 backlight_level;
++	u32 bios_2_scratch;
++
++	bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
++
++	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
++			   ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
++
++	return backlight_level;
++}
++
++static void
++amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
++					    u8 backlight_level)
++{
++	u32 bios_2_scratch;
++
++	bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
++
++	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
++	bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
++			   ATOM_S2_CURRENT_BL_LEVEL_MASK);
++
++	WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
++}
++
++u8
++amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
++{
++	struct drm_device *dev = amdgpu_encoder->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
++		return 0;
++
++	return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
++}
++
++void
++amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
++				     u8 level)
++{
++	struct drm_encoder *encoder = &amdgpu_encoder->base;
++	struct drm_device *dev = amdgpu_encoder->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder_atom_dig *dig;
++
++	if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
++		return;
++
++	if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
++	    amdgpu_encoder->enc_priv) {
++		dig = amdgpu_encoder->enc_priv;
++		dig->backlight_level = level;
++		amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, dig->backlight_level);
++
++		switch (amdgpu_encoder->encoder_id) {
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++			if (dig->backlight_level == 0)
++				amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++								       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
++			else {
++				amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++								       ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
++				amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++								       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
++			}
++			break;
++		default:
++			break;
++		}
++	}
++}
++
++#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
++
++static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd)
++{
++	u8 level;
++
++	/* Convert brightness to hardware level */
++	if (bd->props.brightness < 0)
++		level = 0;
++	else if (bd->props.brightness > AMDGPU_MAX_BL_LEVEL)
++		level = AMDGPU_MAX_BL_LEVEL;
++	else
++		level = bd->props.brightness;
++
++	return level;
++}
++
++static int amdgpu_atombios_encoder_update_backlight_status(struct backlight_device *bd)
++{
++	struct amdgpu_backlight_privdata *pdata = bl_get_data(bd);
++	struct amdgpu_encoder *amdgpu_encoder = pdata->encoder;
++
++	amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder,
++					     amdgpu_atombios_encoder_backlight_level(bd));
++
++	return 0;
++}
++
++static int
++amdgpu_atombios_encoder_get_backlight_brightness(struct backlight_device *bd)
++{
++	struct amdgpu_backlight_privdata *pdata = bl_get_data(bd);
++	struct amdgpu_encoder *amdgpu_encoder = pdata->encoder;
++	struct drm_device *dev = amdgpu_encoder->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
++}
++
++static const struct backlight_ops amdgpu_atombios_encoder_backlight_ops = {
++	.get_brightness = amdgpu_atombios_encoder_get_backlight_brightness,
++	.update_status	= amdgpu_atombios_encoder_update_backlight_status,
++};
++
++void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encoder,
++				     struct drm_connector *drm_connector)
++{
++	struct drm_device *dev = amdgpu_encoder->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct backlight_device *bd;
++	struct backlight_properties props;
++	struct amdgpu_backlight_privdata *pdata;
++	struct amdgpu_encoder_atom_dig *dig;
++	u8 backlight_level;
++	char bl_name[16];
++
++	/* Mac laptops with multiple GPUs use the gmux driver for backlight
++	 * so don't register a backlight device
++	 */
++	if ((adev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
++	    (adev->pdev->device == 0x6741))
++		return;
++
++	if (!amdgpu_encoder->enc_priv)
++		return;
++
++	if (!adev->is_atom_bios)
++		return;
++
++	if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
++		return;
++
++	pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL);
++	if (!pdata) {
++		DRM_ERROR("Memory allocation failed\n");
++		goto error;
++	}
++
++	memset(&props, 0, sizeof(props));
++	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
++	props.type = BACKLIGHT_RAW;
++	snprintf(bl_name, sizeof(bl_name),
++		 "amdgpu_bl%d", dev->primary->index);
++	bd = backlight_device_register(bl_name, drm_connector->kdev,
++				       pdata, &amdgpu_atombios_encoder_backlight_ops, &props);
++	if (IS_ERR(bd)) {
++		DRM_ERROR("Backlight registration failed\n");
++		goto error;
++	}
++
++	pdata->encoder = amdgpu_encoder;
++
++	backlight_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
++
++	dig = amdgpu_encoder->enc_priv;
++	dig->bl_dev = bd;
++
++	bd->props.brightness = amdgpu_atombios_encoder_get_backlight_brightness(bd);
++	bd->props.power = FB_BLANK_UNBLANK;
++	backlight_update_status(bd);
++
++	DRM_INFO("amdgpu atom DIG backlight initialized\n");
++
++	return;
++
++error:
++	kfree(pdata);
++	return;
++}
++
++void
++amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder)
++{
++	struct drm_device *dev = amdgpu_encoder->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct backlight_device *bd = NULL;
++	struct amdgpu_encoder_atom_dig *dig;
++
++	if (!amdgpu_encoder->enc_priv)
++		return;
++
++	if (!adev->is_atom_bios)
++		return;
++
++	if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
++		return;
++
++	dig = amdgpu_encoder->enc_priv;
++	bd = dig->bl_dev;
++	dig->bl_dev = NULL;
++
++	if (bd) {
++		struct amdgpu_legacy_backlight_privdata *pdata;
++
++		pdata = bl_get_data(bd);
++		backlight_device_unregister(bd);
++		kfree(pdata);
++
++		DRM_INFO("amdgpu atom LVDS backlight unloaded\n");
++	}
++}
++
++#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
++
++void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *encoder)
++{
++}
++
++void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder)
++{
++}
++
++#endif
++
++bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		return true;
++	default:
++		return false;
++	}
++}
++
++bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder,
++				 const struct drm_display_mode *mode,
++				 struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++	/* set the active encoder to connector routing */
++	amdgpu_encoder_set_active_device(encoder);
++	drm_mode_set_crtcinfo(adjusted_mode, 0);
++
++	/* hw bug */
++	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
++	    && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
++		adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
++
++	/* get the native mode for scaling */
++	if (amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
++		amdgpu_panel_mode_fixup(encoder, adjusted_mode);
++	else if (amdgpu_encoder->rmx_type != RMX_OFF)
++		amdgpu_panel_mode_fixup(encoder, adjusted_mode);
++
++	if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
++	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
++		struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++		amdgpu_atombios_dp_set_link_config(connector, adjusted_mode);
++	}
++
++	return true;
++}
++
++static void
++amdgpu_atombios_encoder_setup_dac(struct drm_encoder *encoder, int action)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
++	int index = 0;
++
++	memset(&args, 0, sizeof(args));
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++		index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++		index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
++		break;
++	}
++
++	args.ucAction = action;
++	args.ucDacStandard = ATOM_DAC1_PS2;
++	args.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++}
++
++static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder)
++{
++	int bpc = 8;
++
++	if (encoder->crtc) {
++		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++		bpc = amdgpu_crtc->bpc;
++	}
++
++	switch (bpc) {
++	case 0:
++		return PANEL_BPC_UNDEFINE;
++	case 6:
++		return PANEL_6BIT_PER_COLOR;
++	case 8:
++	default:
++		return PANEL_8BIT_PER_COLOR;
++	case 10:
++		return PANEL_10BIT_PER_COLOR;
++	case 12:
++		return PANEL_12BIT_PER_COLOR;
++	case 16:
++		return PANEL_16BIT_PER_COLOR;
++	}
++}
++
++union dvo_encoder_control {
++	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
++	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
++	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
++	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
++};
++
++static void
++amdgpu_atombios_encoder_setup_dvo(struct drm_encoder *encoder, int action)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	union dvo_encoder_control args;
++	int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
++	uint8_t frev, crev;
++
++	memset(&args, 0, sizeof(args));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 1:
++			/* R4xx, R5xx */
++			args.ext_tmds.sXTmdsEncoder.ucEnable = action;
++
++			if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
++
++			args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
++			break;
++		case 2:
++			/* RS600/690/740 */
++			args.dvo.sDVOEncoder.ucAction = action;
++			args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			/* DFP1, CRT1, TV1 depending on the type of port */
++			args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
++
++			if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
++			break;
++		case 3:
++			/* R6xx */
++			args.dvo_v3.ucAction = action;
++			args.dvo_v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			args.dvo_v3.ucDVOConfig = 0; /* XXX */
++			break;
++		case 4:
++			/* DCE8 */
++			args.dvo_v4.ucAction = action;
++			args.dvo_v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			args.dvo_v4.ucDVOConfig = 0; /* XXX */
++			args.dvo_v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++			break;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++		break;
++	}
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector;
++	struct amdgpu_connector_atom_dig *dig_connector;
++
++	/* dp bridges are always DP */
++	if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
++		return ATOM_ENCODER_MODE_DP;
++
++	/* DVO is always DVO */
++	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
++	    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
++		return ATOM_ENCODER_MODE_DVO;
++
++	connector = amdgpu_get_connector_for_encoder(encoder);
++	/* if we don't have an active device yet, just use one of
++	 * the connectors tied to the encoder.
++	 */
++	if (!connector)
++		connector = amdgpu_get_connector_for_encoder_init(encoder);
++	amdgpu_connector = to_amdgpu_connector(connector);
++
++	switch (connector->connector_type) {
++	case DRM_MODE_CONNECTOR_DVII:
++	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
++		if (amdgpu_audio != 0) {
++			if (amdgpu_connector->use_digital &&
++			    (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE))
++				return ATOM_ENCODER_MODE_HDMI;
++			else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
++				 (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO))
++				return ATOM_ENCODER_MODE_HDMI;
++			else if (amdgpu_connector->use_digital)
++				return ATOM_ENCODER_MODE_DVI;
++			else
++				return ATOM_ENCODER_MODE_CRT;
++		} else if (amdgpu_connector->use_digital) {
++			return ATOM_ENCODER_MODE_DVI;
++		} else {
++			return ATOM_ENCODER_MODE_CRT;
++		}
++		break;
++	case DRM_MODE_CONNECTOR_DVID:
++	case DRM_MODE_CONNECTOR_HDMIA:
++	default:
++		if (amdgpu_audio != 0) {
++			if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)
++				return ATOM_ENCODER_MODE_HDMI;
++			else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
++				 (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO))
++				return ATOM_ENCODER_MODE_HDMI;
++			else
++				return ATOM_ENCODER_MODE_DVI;
++		} else {
++			return ATOM_ENCODER_MODE_DVI;
++		}
++		break;
++	case DRM_MODE_CONNECTOR_LVDS:
++		return ATOM_ENCODER_MODE_LVDS;
++		break;
++	case DRM_MODE_CONNECTOR_DisplayPort:
++		dig_connector = amdgpu_connector->con_priv;
++		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
++		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
++			return ATOM_ENCODER_MODE_DP;
++		} else if (amdgpu_audio != 0) {
++			if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)
++				return ATOM_ENCODER_MODE_HDMI;
++			else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
++				 (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO))
++				return ATOM_ENCODER_MODE_HDMI;
++			else
++				return ATOM_ENCODER_MODE_DVI;
++		} else {
++			return ATOM_ENCODER_MODE_DVI;
++		}
++		break;
++	case DRM_MODE_CONNECTOR_eDP:
++		return ATOM_ENCODER_MODE_DP;
++	case DRM_MODE_CONNECTOR_DVIA:
++	case DRM_MODE_CONNECTOR_VGA:
++		return ATOM_ENCODER_MODE_CRT;
++		break;
++	case DRM_MODE_CONNECTOR_Composite:
++	case DRM_MODE_CONNECTOR_SVIDEO:
++	case DRM_MODE_CONNECTOR_9PinDIN:
++		/* fix me */
++		return ATOM_ENCODER_MODE_TV;
++		/*return ATOM_ENCODER_MODE_CV;*/
++		break;
++	}
++}
++
++/*
++ * DIG Encoder/Transmitter Setup
++ *
++ * DCE 6.0
++ * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
++ * Supports up to 6 digital outputs
++ * - 6 DIG encoder blocks.
++ * - DIG to PHY mapping is hardcoded
++ * DIG1 drives UNIPHY0 link A, A+B
++ * DIG2 drives UNIPHY0 link B
++ * DIG3 drives UNIPHY1 link A, A+B
++ * DIG4 drives UNIPHY1 link B
++ * DIG5 drives UNIPHY2 link A, A+B
++ * DIG6 drives UNIPHY2 link B
++ *
++ * Routing
++ * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
++ * Examples:
++ * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
++ * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
++ * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
++ * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
++ */
++
++union dig_encoder_control {
++	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
++	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
++	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
++	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
++};
++
++void
++amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
++				   int action, int panel_mode)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	union dig_encoder_control args;
++	int index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
++	uint8_t frev, crev;
++	int dp_clock = 0;
++	int dp_lane_count = 0;
++	int hpd_id = AMDGPU_HPD_NONE;
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		struct amdgpu_connector_atom_dig *dig_connector =
++			amdgpu_connector->con_priv;
++
++		dp_clock = dig_connector->dp_clock;
++		dp_lane_count = dig_connector->dp_lane_count;
++		hpd_id = amdgpu_connector->hpd.hpd;
++	}
++
++	/* no dig encoder assigned */
++	if (dig->dig_encoder == -1)
++		return;
++
++	memset(&args, 0, sizeof(args));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 1:
++			args.v1.ucAction = action;
++			args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
++				args.v3.ucPanelMode = panel_mode;
++			else
++				args.v1.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++
++			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
++				args.v1.ucLaneNum = dp_lane_count;
++			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v1.ucLaneNum = 8;
++			else
++				args.v1.ucLaneNum = 4;
++
++			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
++				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
++				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
++				break;
++			}
++			if (dig->linkb)
++				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
++			else
++				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
++			break;
++		case 2:
++		case 3:
++			args.v3.ucAction = action;
++			args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
++				args.v3.ucPanelMode = panel_mode;
++			else
++				args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++
++			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
++				args.v3.ucLaneNum = dp_lane_count;
++			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v3.ucLaneNum = 8;
++			else
++				args.v3.ucLaneNum = 4;
++
++			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
++				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
++			args.v3.acConfig.ucDigSel = dig->dig_encoder;
++			args.v3.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
++			break;
++		case 4:
++			args.v4.ucAction = action;
++			args.v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
++				args.v4.ucPanelMode = panel_mode;
++			else
++				args.v4.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++
++			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
++				args.v4.ucLaneNum = dp_lane_count;
++			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v4.ucLaneNum = 8;
++			else
++				args.v4.ucLaneNum = 4;
++
++			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
++				if (dp_clock == 540000)
++					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
++				else if (dp_clock == 324000)
++					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
++				else if (dp_clock == 270000)
++					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
++				else
++					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
++			}
++			args.v4.acConfig.ucDigSel = dig->dig_encoder;
++			args.v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
++			if (hpd_id == AMDGPU_HPD_NONE)
++				args.v4.ucHPD_ID = 0;
++			else
++				args.v4.ucHPD_ID = hpd_id + 1;
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++			break;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++		break;
++	}
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++}
++
++union dig_transmitter_control {
++	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
++	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
++	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
++	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
++	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
++};
++
++void
++amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action,
++				       uint8_t lane_num, uint8_t lane_set)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	union dig_transmitter_control args;
++	int index = 0;
++	uint8_t frev, crev;
++	bool is_dp = false;
++	int pll_id = 0;
++	int dp_clock = 0;
++	int dp_lane_count = 0;
++	int connector_object_id = 0;
++	int igp_lane_info = 0;
++	int dig_encoder = dig->dig_encoder;
++	int hpd_id = AMDGPU_HPD_NONE;
++
++	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
++		connector = amdgpu_get_connector_for_encoder_init(encoder);
++		/* just needed to avoid bailing in the encoder check.  the encoder
++		 * isn't used for init
++		 */
++		dig_encoder = 0;
++	} else
++		connector = amdgpu_get_connector_for_encoder(encoder);
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		struct amdgpu_connector_atom_dig *dig_connector =
++			amdgpu_connector->con_priv;
++
++		hpd_id = amdgpu_connector->hpd.hpd;
++		dp_clock = dig_connector->dp_clock;
++		dp_lane_count = dig_connector->dp_lane_count;
++		connector_object_id =
++			(amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
++	}
++
++	if (encoder->crtc) {
++		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++		pll_id = amdgpu_crtc->pll_id;
++	}
++
++	/* no dig encoder assigned */
++	if (dig_encoder == -1)
++		return;
++
++	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)))
++		is_dp = true;
++
++	memset(&args, 0, sizeof(args));
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
++		index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
++		break;
++	}
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 1:
++			args.v1.ucAction = action;
++			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
++				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
++			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
++				args.v1.asMode.ucLaneSel = lane_num;
++				args.v1.asMode.ucLaneSet = lane_set;
++			} else {
++				if (is_dp)
++					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
++				else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v1.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
++				else
++					args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			}
++
++			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
++
++			if (dig_encoder)
++				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
++			else
++				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
++
++			if ((adev->flags & AMDGPU_IS_APU) &&
++			    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
++				if (is_dp ||
++				    !amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) {
++					if (igp_lane_info & 0x1)
++						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
++					else if (igp_lane_info & 0x2)
++						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
++					else if (igp_lane_info & 0x4)
++						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
++					else if (igp_lane_info & 0x8)
++						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
++				} else {
++					if (igp_lane_info & 0x3)
++						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
++					else if (igp_lane_info & 0xc)
++						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
++				}
++			}
++
++			if (dig->linkb)
++				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
++			else
++				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
++
++			if (is_dp)
++				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
++			else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
++				if (dig->coherent_mode)
++					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
++				if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
++			}
++			break;
++		case 2:
++			args.v2.ucAction = action;
++			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
++				args.v2.usInitInfo = cpu_to_le16(connector_object_id);
++			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
++				args.v2.asMode.ucLaneSel = lane_num;
++				args.v2.asMode.ucLaneSet = lane_set;
++			} else {
++				if (is_dp)
++					args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
++				else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v2.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
++				else
++					args.v2.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			}
++
++			args.v2.acConfig.ucEncoderSel = dig_encoder;
++			if (dig->linkb)
++				args.v2.acConfig.ucLinkSel = 1;
++
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++				args.v2.acConfig.ucTransmitterSel = 0;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++				args.v2.acConfig.ucTransmitterSel = 1;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++				args.v2.acConfig.ucTransmitterSel = 2;
++				break;
++			}
++
++			if (is_dp) {
++				args.v2.acConfig.fCoherentMode = 1;
++				args.v2.acConfig.fDPConnector = 1;
++			} else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
++				if (dig->coherent_mode)
++					args.v2.acConfig.fCoherentMode = 1;
++				if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v2.acConfig.fDualLinkConnector = 1;
++			}
++			break;
++		case 3:
++			args.v3.ucAction = action;
++			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
++				args.v3.usInitInfo = cpu_to_le16(connector_object_id);
++			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
++				args.v3.asMode.ucLaneSel = lane_num;
++				args.v3.asMode.ucLaneSet = lane_set;
++			} else {
++				if (is_dp)
++					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
++				else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v3.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
++				else
++					args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			}
++
++			if (is_dp)
++				args.v3.ucLaneNum = dp_lane_count;
++			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v3.ucLaneNum = 8;
++			else
++				args.v3.ucLaneNum = 4;
++
++			if (dig->linkb)
++				args.v3.acConfig.ucLinkSel = 1;
++			if (dig_encoder & 1)
++				args.v3.acConfig.ucEncoderSel = 1;
++
++			/* Select the PLL for the PHY
++			 * DP PHY should be clocked from external src if there is
++			 * one.
++			 */
++			/* On DCE4, if there is an external clock, it generates the DP ref clock */
++			if (is_dp && adev->clock.dp_extclk)
++				args.v3.acConfig.ucRefClkSource = 2; /* external src */
++			else
++				args.v3.acConfig.ucRefClkSource = pll_id;
++
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++				args.v3.acConfig.ucTransmitterSel = 0;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++				args.v3.acConfig.ucTransmitterSel = 1;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++				args.v3.acConfig.ucTransmitterSel = 2;
++				break;
++			}
++
++			if (is_dp)
++				args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
++			else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
++				if (dig->coherent_mode)
++					args.v3.acConfig.fCoherentMode = 1;
++				if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v3.acConfig.fDualLinkConnector = 1;
++			}
++			break;
++		case 4:
++			args.v4.ucAction = action;
++			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
++				args.v4.usInitInfo = cpu_to_le16(connector_object_id);
++			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
++				args.v4.asMode.ucLaneSel = lane_num;
++				args.v4.asMode.ucLaneSet = lane_set;
++			} else {
++				if (is_dp)
++					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
++				else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v4.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
++				else
++					args.v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			}
++
++			if (is_dp)
++				args.v4.ucLaneNum = dp_lane_count;
++			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v4.ucLaneNum = 8;
++			else
++				args.v4.ucLaneNum = 4;
++
++			if (dig->linkb)
++				args.v4.acConfig.ucLinkSel = 1;
++			if (dig_encoder & 1)
++				args.v4.acConfig.ucEncoderSel = 1;
++
++			/* Select the PLL for the PHY
++			 * DP PHY should be clocked from external src if there is
++			 * one.
++			 */
++			/* On DCE5 DCPLL usually generates the DP ref clock */
++			if (is_dp) {
++				if (adev->clock.dp_extclk)
++					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
++				else
++					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
++			} else
++				args.v4.acConfig.ucRefClkSource = pll_id;
++
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++				args.v4.acConfig.ucTransmitterSel = 0;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++				args.v4.acConfig.ucTransmitterSel = 1;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++				args.v4.acConfig.ucTransmitterSel = 2;
++				break;
++			}
++
++			if (is_dp)
++				args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
++			else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
++				if (dig->coherent_mode)
++					args.v4.acConfig.fCoherentMode = 1;
++				if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++					args.v4.acConfig.fDualLinkConnector = 1;
++			}
++			break;
++		case 5:
++			args.v5.ucAction = action;
++			if (is_dp)
++				args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
++			else
++				args.v5.usSymClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++				if (dig->linkb)
++					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
++				else
++					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++				if (dig->linkb)
++					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
++				else
++					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++				if (dig->linkb)
++					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
++				else
++					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++				args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
++				break;
++			}
++			if (is_dp)
++				args.v5.ucLaneNum = dp_lane_count;
++			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v5.ucLaneNum = 8;
++			else
++				args.v5.ucLaneNum = 4;
++			args.v5.ucConnObjId = connector_object_id;
++			args.v5.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++
++			if (is_dp && adev->clock.dp_extclk)
++				args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
++			else
++				args.v5.asConfig.ucPhyClkSrcId = pll_id;
++
++			if (is_dp)
++				args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
++			else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
++				if (dig->coherent_mode)
++					args.v5.asConfig.ucCoherentMode = 1;
++			}
++			if (hpd_id == AMDGPU_HPD_NONE)
++				args.v5.asConfig.ucHPDSel = 0;
++			else
++				args.v5.asConfig.ucHPDSel = hpd_id + 1;
++			args.v5.ucDigEncoderSel = 1 << dig_encoder;
++			args.v5.ucDPLaneSet = lane_set;
++			break;
++		default:
++			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++			break;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
++		break;
++	}
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++bool
++amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector *connector,
++				     int action)
++{
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_device *dev = amdgpu_connector->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	union dig_transmitter_control args;
++	int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
++	uint8_t frev, crev;
++
++	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
++		goto done;
++
++	if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
++	    (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
++		goto done;
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		goto done;
++
++	memset(&args, 0, sizeof(args));
++
++	args.v1.ucAction = action;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++	/* wait for the panel to power up */
++	if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
++		int i;
++
++		for (i = 0; i < 300; i++) {
++			if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
++				return true;
++			mdelay(1);
++		}
++		return false;
++	}
++done:
++	return true;
++}
++
++union external_encoder_control {
++	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
++	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
++};
++
++static void
++amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder,
++					struct drm_encoder *ext_encoder,
++					int action)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder *ext_amdgpu_encoder = to_amdgpu_encoder(ext_encoder);
++	union external_encoder_control args;
++	struct drm_connector *connector;
++	int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
++	u8 frev, crev;
++	int dp_clock = 0;
++	int dp_lane_count = 0;
++	int connector_object_id = 0;
++	u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
++
++	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
++		connector = amdgpu_get_connector_for_encoder_init(encoder);
++	else
++		connector = amdgpu_get_connector_for_encoder(encoder);
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		struct amdgpu_connector_atom_dig *dig_connector =
++			amdgpu_connector->con_priv;
++
++		dp_clock = dig_connector->dp_clock;
++		dp_lane_count = dig_connector->dp_lane_count;
++		connector_object_id =
++			(amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
++	}
++
++	memset(&args, 0, sizeof(args));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		/* no params on frev 1 */
++		break;
++	case 2:
++		switch (crev) {
++		case 1:
++		case 2:
++			args.v1.sDigEncoder.ucAction = action;
++			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			args.v1.sDigEncoder.ucEncoderMode =
++				amdgpu_atombios_encoder_get_encoder_mode(encoder);
++
++			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
++				if (dp_clock == 270000)
++					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
++				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
++			} else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v1.sDigEncoder.ucLaneNum = 8;
++			else
++				args.v1.sDigEncoder.ucLaneNum = 4;
++			break;
++		case 3:
++			args.v3.sExtEncoder.ucAction = action;
++			if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
++				args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
++			else
++				args.v3.sExtEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
++			args.v3.sExtEncoder.ucEncoderMode =
++				amdgpu_atombios_encoder_get_encoder_mode(encoder);
++
++			if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
++				if (dp_clock == 270000)
++					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
++				else if (dp_clock == 540000)
++					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
++				args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
++			} else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
++				args.v3.sExtEncoder.ucLaneNum = 8;
++			else
++				args.v3.sExtEncoder.ucLaneNum = 4;
++			switch (ext_enum) {
++			case GRAPH_OBJECT_ENUM_ID1:
++				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
++				break;
++			case GRAPH_OBJECT_ENUM_ID2:
++				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
++				break;
++			case GRAPH_OBJECT_ENUM_ID3:
++				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
++				break;
++			}
++			args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
++			break;
++		default:
++			DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
++			return;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
++		return;
++	}
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++static void
++amdgpu_atombios_encoder_setup_dig(struct drm_encoder *encoder, int action)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = NULL;
++
++	if (connector) {
++		amdgpu_connector = to_amdgpu_connector(connector);
++		amdgpu_dig_connector = amdgpu_connector->con_priv;
++	}
++
++	if (action == ATOM_ENABLE) {
++		if (!connector)
++			dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
++		else
++			dig->panel_mode = amdgpu_atombios_dp_get_panel_mode(encoder, connector);
++
++		/* setup and enable the encoder */
++		amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_SETUP, 0);
++		amdgpu_atombios_encoder_setup_dig_encoder(encoder,
++						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
++						   dig->panel_mode);
++		if (ext_encoder)
++			amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
++								EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
++		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
++		    connector) {
++			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
++				amdgpu_atombios_encoder_set_edp_panel_power(connector,
++								     ATOM_TRANSMITTER_ACTION_POWER_ON);
++				amdgpu_dig_connector->edp_on = true;
++			}
++		}
++		/* enable the transmitter */
++		amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++						       ATOM_TRANSMITTER_ACTION_ENABLE,
++						       0, 0);
++		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
++		    connector) {
++			/* DP_SET_POWER_D0 is set in amdgpu_atombios_dp_link_train */
++			amdgpu_atombios_dp_link_train(encoder, connector);
++			amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
++		}
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++			amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++							       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
++		if (ext_encoder)
++			amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_ENABLE);
++	} else {
++		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
++		    connector)
++			amdgpu_atombios_encoder_setup_dig_encoder(encoder,
++							   ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
++		if (ext_encoder)
++			amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_DISABLE);
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++			amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++							       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
++
++		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
++		    connector)
++			amdgpu_atombios_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
++		/* disable the transmitter */
++		amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
++						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
++		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) &&
++		    connector) {
++			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
++				amdgpu_atombios_encoder_set_edp_panel_power(connector,
++								     ATOM_TRANSMITTER_ACTION_POWER_OFF);
++				amdgpu_dig_connector->edp_on = false;
++			}
++		}
++	}
++}
++
++void
++amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
++		  amdgpu_encoder->encoder_id, mode, amdgpu_encoder->devices,
++		  amdgpu_encoder->active_device);
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		switch (mode) {
++		case DRM_MODE_DPMS_ON:
++			amdgpu_atombios_encoder_setup_dig(encoder, ATOM_ENABLE);
++			break;
++		case DRM_MODE_DPMS_STANDBY:
++		case DRM_MODE_DPMS_SUSPEND:
++		case DRM_MODE_DPMS_OFF:
++			amdgpu_atombios_encoder_setup_dig(encoder, ATOM_DISABLE);
++			break;
++		}
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++		switch (mode) {
++		case DRM_MODE_DPMS_ON:
++			amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_ENABLE);
++			break;
++		case DRM_MODE_DPMS_STANDBY:
++		case DRM_MODE_DPMS_SUSPEND:
++		case DRM_MODE_DPMS_OFF:
++			amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_DISABLE);
++			break;
++		}
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++		switch (mode) {
++		case DRM_MODE_DPMS_ON:
++			amdgpu_atombios_encoder_setup_dac(encoder, ATOM_ENABLE);
++			break;
++		case DRM_MODE_DPMS_STANDBY:
++		case DRM_MODE_DPMS_SUSPEND:
++		case DRM_MODE_DPMS_OFF:
++			amdgpu_atombios_encoder_setup_dac(encoder, ATOM_DISABLE);
++			break;
++		}
++		break;
++	default:
++		return;
++	}
++}
++
++union crtc_source_param {
++	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
++	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
++	SELECT_CRTC_SOURCE_PARAMETERS_V3 v3;
++};
++
++void
++amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	union crtc_source_param args;
++	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
++	uint8_t frev, crev;
++	struct amdgpu_encoder_atom_dig *dig;
++
++	memset(&args, 0, sizeof(args));
++
++	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++		return;
++
++	switch (frev) {
++	case 1:
++		switch (crev) {
++		case 1:
++		default:
++			args.v1.ucCRTC = amdgpu_crtc->crtc_id;
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
++				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_LVDS:
++			case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
++				if (amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
++					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
++				else
++					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_DVO1:
++			case ENCODER_OBJECT_ID_INTERNAL_DDI:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_DAC1:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++				if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
++				else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
++					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
++				else
++					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_DAC2:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++				if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
++				else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
++					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
++				else
++					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
++				break;
++			}
++			break;
++		case 2:
++			args.v2.ucCRTC = amdgpu_crtc->crtc_id;
++			if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
++				struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++
++				if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
++					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
++				else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
++					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
++				else
++					args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++			} else if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++				args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
++			} else {
++				args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++			}
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
++				dig = amdgpu_encoder->enc_priv;
++				switch (dig->dig_encoder) {
++				case 0:
++					args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
++					break;
++				case 1:
++					args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
++					break;
++				case 2:
++					args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
++					break;
++				case 3:
++					args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
++					break;
++				case 4:
++					args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
++					break;
++				case 5:
++					args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
++					break;
++				case 6:
++					args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
++					break;
++				}
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++				args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++				if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
++					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else
++					args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++				if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
++					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else
++					args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
++				break;
++			}
++			break;
++		case 3:
++			args.v3.ucCRTC = amdgpu_crtc->crtc_id;
++			if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
++				struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++
++				if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
++					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
++				else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
++					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
++				else
++					args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++			} else if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++				args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
++			} else {
++				args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
++			}
++			args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder);
++			switch (amdgpu_encoder->encoder_id) {
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
++				dig = amdgpu_encoder->enc_priv;
++				switch (dig->dig_encoder) {
++				case 0:
++					args.v3.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
++					break;
++				case 1:
++					args.v3.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
++					break;
++				case 2:
++					args.v3.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
++					break;
++				case 3:
++					args.v3.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
++					break;
++				case 4:
++					args.v3.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
++					break;
++				case 5:
++					args.v3.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
++					break;
++				case 6:
++					args.v3.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
++					break;
++				}
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++				args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++				if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
++					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else
++					args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
++				break;
++			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++				if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
++					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
++					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
++				else
++					args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
++				break;
++			}
++			break;
++		}
++		break;
++	default:
++		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
++		return;
++	}
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++/* This only needs to be called once at startup */
++void
++amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_encoder *encoder;
++
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++		struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
++
++		switch (amdgpu_encoder->encoder_id) {
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++			amdgpu_atombios_encoder_setup_dig_transmitter(encoder, ATOM_TRANSMITTER_ACTION_INIT,
++							       0, 0);
++			break;
++		}
++
++		if (ext_encoder)
++			amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
++								EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
++	}
++}
++
++static bool
++amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder,
++				 struct drm_connector *connector)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++	if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
++				       ATOM_DEVICE_CV_SUPPORT |
++				       ATOM_DEVICE_CRT_SUPPORT)) {
++		DAC_LOAD_DETECTION_PS_ALLOCATION args;
++		int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
++		uint8_t frev, crev;
++
++		memset(&args, 0, sizeof(args));
++
++		if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
++			return false;
++
++		args.sDacload.ucMisc = 0;
++
++		if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
++		    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
++			args.sDacload.ucDacType = ATOM_DAC_A;
++		else
++			args.sDacload.ucDacType = ATOM_DAC_B;
++
++		if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
++			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
++		else if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
++			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
++		else if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
++			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
++			if (crev >= 3)
++				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
++		} else if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
++			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
++			if (crev >= 3)
++				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
++		}
++
++		amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++		return true;
++	} else
++		return false;
++}
++
++enum drm_connector_status
++amdgpu_atombios_encoder_dac_detect(struct drm_encoder *encoder,
++			    struct drm_connector *connector)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	uint32_t bios_0_scratch;
++
++	if (!amdgpu_atombios_encoder_dac_load_detect(encoder, connector)) {
++		DRM_DEBUG_KMS("detect returned false \n");
++		return connector_status_unknown;
++	}
++
++	bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
++
++	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, amdgpu_encoder->devices);
++	if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
++		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
++			return connector_status_connected;
++	}
++	if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
++		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
++			return connector_status_connected;
++	}
++	if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
++		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
++			return connector_status_connected;
++	}
++	if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
++		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
++			return connector_status_connected; /* CTV */
++		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
++			return connector_status_connected; /* STV */
++	}
++	return connector_status_disconnected;
++}
++
++enum drm_connector_status
++amdgpu_atombios_encoder_dig_detect(struct drm_encoder *encoder,
++			    struct drm_connector *connector)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++	struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
++	u32 bios_0_scratch;
++
++	if (!ext_encoder)
++		return connector_status_unknown;
++
++	if ((amdgpu_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
++		return connector_status_unknown;
++
++	/* load detect on the dp bridge */
++	amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
++						EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
++
++	bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
++
++	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, amdgpu_encoder->devices);
++	if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
++		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
++			return connector_status_connected;
++	}
++	if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
++		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
++			return connector_status_connected;
++	}
++	if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
++		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
++			return connector_status_connected;
++	}
++	if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
++		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
++			return connector_status_connected; /* CTV */
++		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
++			return connector_status_connected; /* STV */
++	}
++	return connector_status_disconnected;
++}
++
++void
++amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder *encoder)
++{
++	struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
++
++	if (ext_encoder)
++		/* ddc_setup on the dp bridge */
++		amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder,
++							EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
++
++}
++
++void
++amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector *connector,
++				       struct drm_encoder *encoder,
++				       bool connected)
++{
++	struct drm_device *dev = connector->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_connector *amdgpu_connector =
++	    to_amdgpu_connector(connector);
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
++
++	bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
++	bios_3_scratch = RREG32(mmBIOS_SCRATCH_3);
++	bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
++
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("LCD1 connected\n");
++			bios_0_scratch |= ATOM_S0_LCD1;
++			bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
++		} else {
++			DRM_DEBUG_KMS("LCD1 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_LCD1;
++			bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("CRT1 connected\n");
++			bios_0_scratch |= ATOM_S0_CRT1_COLOR;
++			bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
++		} else {
++			DRM_DEBUG_KMS("CRT1 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
++			bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("CRT2 connected\n");
++			bios_0_scratch |= ATOM_S0_CRT2_COLOR;
++			bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
++		} else {
++			DRM_DEBUG_KMS("CRT2 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
++			bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("DFP1 connected\n");
++			bios_0_scratch |= ATOM_S0_DFP1;
++			bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
++		} else {
++			DRM_DEBUG_KMS("DFP1 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_DFP1;
++			bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("DFP2 connected\n");
++			bios_0_scratch |= ATOM_S0_DFP2;
++			bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
++		} else {
++			DRM_DEBUG_KMS("DFP2 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_DFP2;
++			bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("DFP3 connected\n");
++			bios_0_scratch |= ATOM_S0_DFP3;
++			bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
++		} else {
++			DRM_DEBUG_KMS("DFP3 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_DFP3;
++			bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("DFP4 connected\n");
++			bios_0_scratch |= ATOM_S0_DFP4;
++			bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
++		} else {
++			DRM_DEBUG_KMS("DFP4 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_DFP4;
++			bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("DFP5 connected\n");
++			bios_0_scratch |= ATOM_S0_DFP5;
++			bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
++		} else {
++			DRM_DEBUG_KMS("DFP5 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_DFP5;
++			bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
++		}
++	}
++	if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
++	    (amdgpu_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
++		if (connected) {
++			DRM_DEBUG_KMS("DFP6 connected\n");
++			bios_0_scratch |= ATOM_S0_DFP6;
++			bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
++			bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
++		} else {
++			DRM_DEBUG_KMS("DFP6 disconnected\n");
++			bios_0_scratch &= ~ATOM_S0_DFP6;
++			bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
++			bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
++		}
++	}
++
++	WREG32(mmBIOS_SCRATCH_0, bios_0_scratch);
++	WREG32(mmBIOS_SCRATCH_3, bios_3_scratch);
++	WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
++}
++
++union lvds_info {
++	struct _ATOM_LVDS_INFO info;
++	struct _ATOM_LVDS_INFO_V12 info_12;
++};
++
++struct amdgpu_encoder_atom_dig *
++amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
++{
++	struct drm_device *dev = encoder->base.dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
++	uint16_t data_offset, misc;
++	union lvds_info *lvds_info;
++	uint8_t frev, crev;
++	struct amdgpu_encoder_atom_dig *lvds = NULL;
++	int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
++
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset)) {
++		lvds_info =
++			(union lvds_info *)(mode_info->atom_context->bios + data_offset);
++		lvds =
++		    kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL);
++
++		if (!lvds)
++			return NULL;
++
++		lvds->native_mode.clock =
++		    le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
++		lvds->native_mode.hdisplay =
++		    le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
++		lvds->native_mode.vdisplay =
++		    le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
++		lvds->native_mode.htotal = lvds->native_mode.hdisplay +
++			le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
++		lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
++			le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
++		lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
++			le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
++		lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
++			le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
++		lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
++			le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
++		lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
++			le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
++		lvds->panel_pwr_delay =
++		    le16_to_cpu(lvds_info->info.usOffDelayInMs);
++		lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
++
++		misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
++		if (misc & ATOM_VSYNC_POLARITY)
++			lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
++		if (misc & ATOM_HSYNC_POLARITY)
++			lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
++		if (misc & ATOM_COMPOSITESYNC)
++			lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
++		if (misc & ATOM_INTERLACE)
++			lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
++		if (misc & ATOM_DOUBLE_CLOCK_MODE)
++			lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
++
++		lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
++		lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
++
++		/* set crtc values */
++		drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
++
++		lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
++
++		encoder->native_mode = lvds->native_mode;
++
++		if (encoder_enum == 2)
++			lvds->linkb = true;
++		else
++			lvds->linkb = false;
++
++		/* parse the lcd record table */
++		if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
++			ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
++			ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
++			bool bad_record = false;
++			u8 *record;
++
++			if ((frev == 1) && (crev < 2))
++				/* absolute */
++				record = (u8 *)(mode_info->atom_context->bios +
++						le16_to_cpu(lvds_info->info.usModePatchTableOffset));
++			else
++				/* relative */
++				record = (u8 *)(mode_info->atom_context->bios +
++						data_offset +
++						le16_to_cpu(lvds_info->info.usModePatchTableOffset));
++			while (*record != ATOM_RECORD_END_TYPE) {
++				switch (*record) {
++				case LCD_MODE_PATCH_RECORD_MODE_TYPE:
++					record += sizeof(ATOM_PATCH_RECORD_MODE);
++					break;
++				case LCD_RTS_RECORD_TYPE:
++					record += sizeof(ATOM_LCD_RTS_RECORD);
++					break;
++				case LCD_CAP_RECORD_TYPE:
++					record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
++					break;
++				case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
++					fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
++					if (fake_edid_record->ucFakeEDIDLength) {
++						struct edid *edid;
++						int edid_size =
++							max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
++						edid = kmalloc(edid_size, GFP_KERNEL);
++						if (edid) {
++							memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
++							       fake_edid_record->ucFakeEDIDLength);
++
++							if (drm_edid_is_valid(edid)) {
++								adev->mode_info.bios_hardcoded_edid = edid;
++								adev->mode_info.bios_hardcoded_edid_size = edid_size;
++							} else
++								kfree(edid);
++						}
++					}
++					record += fake_edid_record->ucFakeEDIDLength ?
++						fake_edid_record->ucFakeEDIDLength + 2 :
++						sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
++					break;
++				case LCD_PANEL_RESOLUTION_RECORD_TYPE:
++					panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
++					lvds->native_mode.width_mm = panel_res_record->usHSize;
++					lvds->native_mode.height_mm = panel_res_record->usVSize;
++					record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
++					break;
++				default:
++					DRM_ERROR("Bad LCD record %d\n", *record);
++					bad_record = true;
++					break;
++				}
++				if (bad_record)
++					break;
++			}
++		}
++	}
++	return lvds;
++}
++
++struct amdgpu_encoder_atom_dig *
++amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder)
++{
++	int encoder_enum = (amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
++	struct amdgpu_encoder_atom_dig *dig = kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL);
++
++	if (!dig)
++		return NULL;
++
++	/* coherent mode by default */
++	dig->coherent_mode = true;
++	dig->dig_encoder = -1;
++
++	if (encoder_enum == 2)
++		dig->linkb = true;
++	else
++		dig->linkb = false;
++
++	return dig;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
+new file mode 100644
+index 0000000..2bdec40
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
+@@ -0,0 +1,73 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __ATOMBIOS_ENCODER_H__
++#define __ATOMBIOS_ENCODER_H__
++
++u8
++amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder);
++void
++amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
++				     u8 level);
++void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encoder,
++				     struct drm_connector *drm_connector);
++void
++amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder);
++bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder);
++bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder,
++				 const struct drm_display_mode *mode,
++				 struct drm_display_mode *adjusted_mode);
++int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder);
++void
++amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
++				   int action, int panel_mode);
++void
++amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action,
++				       uint8_t lane_num, uint8_t lane_set);
++bool
++amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector *connector,
++				     int action);
++void
++amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode);
++void
++amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder);
++void
++amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev);
++enum drm_connector_status
++amdgpu_atombios_encoder_dac_detect(struct drm_encoder *encoder,
++			    struct drm_connector *connector);
++enum drm_connector_status
++amdgpu_atombios_encoder_dig_detect(struct drm_encoder *encoder,
++			    struct drm_connector *connector);
++void
++amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder *encoder);
++void
++amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector *connector,
++				       struct drm_encoder *encoder,
++				       bool connected);
++struct amdgpu_encoder_atom_dig *
++amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder);
++struct amdgpu_encoder_atom_dig *
++amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+new file mode 100644
+index 0000000..13cdb01
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+@@ -0,0 +1,158 @@
++/*
++ * Copyright 2011 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ *
++ */
++#include <drm/drmP.h>
++#include <drm/amdgpu_drm.h>
++#include "amdgpu.h"
++#include "atom.h"
++#include "amdgpu_atombios.h"
++
++#define TARGET_HW_I2C_CLOCK 50
++
++/* these are a limitation of ProcessI2cChannelTransaction not the hw */
++#define ATOM_MAX_HW_I2C_WRITE 3
++#define ATOM_MAX_HW_I2C_READ  255
++
++static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
++				       u8 slave_addr, u8 flags,
++				       u8 *buf, u8 num)
++{
++	struct drm_device *dev = chan->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
++	int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
++	unsigned char *base;
++	u16 out = cpu_to_le16(0);
++	int r = 0;
++
++	memset(&args, 0, sizeof(args));
++
++	mutex_lock(&chan->mutex);
++
++	base = (unsigned char *)adev->mode_info.atom_context->scratch;
++
++	if (flags & HW_I2C_WRITE) {
++		if (num > ATOM_MAX_HW_I2C_WRITE) {
++			DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
++			r = -EINVAL;
++			goto done;
++		}
++		if (buf == NULL)
++			args.ucRegIndex = 0;
++		else
++			args.ucRegIndex = buf[0];
++		if (num)
++			num--;
++		if (num)
++			memcpy(&out, &buf[1], num);
++		args.lpI2CDataOut = cpu_to_le16(out);
++	} else {
++		if (num > ATOM_MAX_HW_I2C_READ) {
++			DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
++			r = -EINVAL;
++			goto done;
++		}
++		args.ucRegIndex = 0;
++		args.lpI2CDataOut = 0;
++	}
++
++	args.ucFlag = flags;
++	args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
++	args.ucTransBytes = num;
++	args.ucSlaveAddr = slave_addr << 1;
++	args.ucLineNumber = chan->rec.i2c_id;
++
++	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
++
++	/* error */
++	if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
++		DRM_DEBUG_KMS("hw_i2c error\n");
++		r = -EIO;
++		goto done;
++	}
++
++	if (!(flags & HW_I2C_WRITE))
++		amdgpu_atombios_copy_swap(buf, base, num, false);
++
++done:
++	mutex_unlock(&chan->mutex);
++
++	return r;
++}
++
++int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap,
++		      struct i2c_msg *msgs, int num)
++{
++	struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
++	struct i2c_msg *p;
++	int i, remaining, current_count, buffer_offset, max_bytes, ret;
++	u8 flags;
++
++	/* check for bus probe */
++	p = &msgs[0];
++	if ((num == 1) && (p->len == 0)) {
++		ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
++						  p->addr, HW_I2C_WRITE,
++						  NULL, 0);
++		if (ret)
++			return ret;
++		else
++			return num;
++	}
++
++	for (i = 0; i < num; i++) {
++		p = &msgs[i];
++		remaining = p->len;
++		buffer_offset = 0;
++		/* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
++		if (p->flags & I2C_M_RD) {
++			max_bytes = ATOM_MAX_HW_I2C_READ;
++			flags = HW_I2C_READ;
++		} else {
++			max_bytes = ATOM_MAX_HW_I2C_WRITE;
++			flags = HW_I2C_WRITE;
++		}
++		while (remaining) {
++			if (remaining > max_bytes)
++				current_count = max_bytes;
++			else
++				current_count = remaining;
++			ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
++							  p->addr, flags,
++							  &p->buf[buffer_offset], current_count);
++			if (ret)
++				return ret;
++			remaining -= current_count;
++			buffer_offset += current_count;
++		}
++	}
++
++	return num;
++}
++
++u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.h b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.h
+new file mode 100644
+index 0000000..d6128d9d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __ATOMBIOS_I2C_H__
++#define __ATOMBIOS_I2C_H__
++
++int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap,
++		      struct i2c_msg *msgs, int num);
++u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
+new file mode 100644
+index 0000000..11828e2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
+@@ -0,0 +1,550 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++#ifndef CIK_H
++#define CIK_H
++
++#define MC_SEQ_MISC0__GDDR5__SHIFT	0x1c
++#define MC_SEQ_MISC0__GDDR5_MASK	0xf0000000
++#define MC_SEQ_MISC0__GDDR5_VALUE	5
++
++#define CP_ME_TABLE_SIZE    96
++
++/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
++#define CRTC0_REGISTER_OFFSET                 (0x1b7c - 0x1b7c)
++#define CRTC1_REGISTER_OFFSET                 (0x1e7c - 0x1b7c)
++#define CRTC2_REGISTER_OFFSET                 (0x417c - 0x1b7c)
++#define CRTC3_REGISTER_OFFSET                 (0x447c - 0x1b7c)
++#define CRTC4_REGISTER_OFFSET                 (0x477c - 0x1b7c)
++#define CRTC5_REGISTER_OFFSET                 (0x4a7c - 0x1b7c)
++
++#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
++#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003
++
++#define CIK_RB_BITMAP_WIDTH_PER_SH     2
++#define HAWAII_RB_BITMAP_WIDTH_PER_SH  4
++
++#define AMDGPU_NUM_OF_VMIDS	8
++
++#define		PIPEID(x)					((x) << 0)
++#define		MEID(x)						((x) << 2)
++#define		VMID(x)						((x) << 4)
++#define		QUEUEID(x)					((x) << 8)
++
++#define mmCC_DRM_ID_STRAPS				0x1559
++#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK		0xf0000000
++
++#define mmCHUB_CONTROL					0x619
++#define		BYPASS_VM					(1 << 0)
++
++#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
++
++#define mmGRPH_LUT_10BIT_BYPASS_CONTROL			0x1a02
++#define		LUT_10BIT_BYPASS_EN			(1 << 8)
++
++#       define CURSOR_MONO                    0
++#       define CURSOR_24_1                    1
++#       define CURSOR_24_8_PRE_MULT           2
++#       define CURSOR_24_8_UNPRE_MULT         3
++#       define CURSOR_URGENT_ALWAYS           0
++#       define CURSOR_URGENT_1_8              1
++#       define CURSOR_URGENT_1_4              2
++#       define CURSOR_URGENT_3_8              3
++#       define CURSOR_URGENT_1_2              4
++
++#       define GRPH_DEPTH_8BPP                0
++#       define GRPH_DEPTH_16BPP               1
++#       define GRPH_DEPTH_32BPP               2
++/* 8 BPP */
++#       define GRPH_FORMAT_INDEXED            0
++/* 16 BPP */
++#       define GRPH_FORMAT_ARGB1555           0
++#       define GRPH_FORMAT_ARGB565            1
++#       define GRPH_FORMAT_ARGB4444           2
++#       define GRPH_FORMAT_AI88               3
++#       define GRPH_FORMAT_MONO16             4
++#       define GRPH_FORMAT_BGRA5551           5
++/* 32 BPP */
++#       define GRPH_FORMAT_ARGB8888           0
++#       define GRPH_FORMAT_ARGB2101010        1
++#       define GRPH_FORMAT_32BPP_DIG          2
++#       define GRPH_FORMAT_8B_ARGB2101010     3
++#       define GRPH_FORMAT_BGRA1010102        4
++#       define GRPH_FORMAT_8B_BGRA1010102     5
++#       define GRPH_FORMAT_RGB111110          6
++#       define GRPH_FORMAT_BGR101111          7
++#       define ADDR_SURF_MACRO_TILE_ASPECT_1  0
++#       define ADDR_SURF_MACRO_TILE_ASPECT_2  1
++#       define ADDR_SURF_MACRO_TILE_ASPECT_4  2
++#       define ADDR_SURF_MACRO_TILE_ASPECT_8  3
++#       define GRPH_ARRAY_LINEAR_GENERAL      0
++#       define GRPH_ARRAY_LINEAR_ALIGNED      1
++#       define GRPH_ARRAY_1D_TILED_THIN1      2
++#       define GRPH_ARRAY_2D_TILED_THIN1      4
++#       define DISPLAY_MICRO_TILING          0
++#       define THIN_MICRO_TILING             1
++#       define DEPTH_MICRO_TILING            2
++#       define ROTATED_MICRO_TILING          4
++#       define GRPH_ENDIAN_NONE               0
++#       define GRPH_ENDIAN_8IN16              1
++#       define GRPH_ENDIAN_8IN32              2
++#       define GRPH_ENDIAN_8IN64              3
++#       define GRPH_RED_SEL_R                 0
++#       define GRPH_RED_SEL_G                 1
++#       define GRPH_RED_SEL_B                 2
++#       define GRPH_RED_SEL_A                 3
++#       define GRPH_GREEN_SEL_G               0
++#       define GRPH_GREEN_SEL_B               1
++#       define GRPH_GREEN_SEL_A               2
++#       define GRPH_GREEN_SEL_R               3
++#       define GRPH_BLUE_SEL_B                0
++#       define GRPH_BLUE_SEL_A                1
++#       define GRPH_BLUE_SEL_R                2
++#       define GRPH_BLUE_SEL_G                3
++#       define GRPH_ALPHA_SEL_A               0
++#       define GRPH_ALPHA_SEL_R               1
++#       define GRPH_ALPHA_SEL_G               2
++#       define GRPH_ALPHA_SEL_B               3
++#       define INPUT_GAMMA_USE_LUT                  0
++#       define INPUT_GAMMA_BYPASS                   1
++#       define INPUT_GAMMA_SRGB_24                  2
++#       define INPUT_GAMMA_XVYCC_222                3
++
++#       define INPUT_CSC_BYPASS                     0
++#       define INPUT_CSC_PROG_COEFF                 1
++#       define INPUT_CSC_PROG_SHARED_MATRIXA        2
++
++#       define OUTPUT_CSC_BYPASS                    0
++#       define OUTPUT_CSC_TV_RGB                    1
++#       define OUTPUT_CSC_YCBCR_601                 2
++#       define OUTPUT_CSC_YCBCR_709                 3
++#       define OUTPUT_CSC_PROG_COEFF                4
++#       define OUTPUT_CSC_PROG_SHARED_MATRIXB       5
++
++#       define DEGAMMA_BYPASS                       0
++#       define DEGAMMA_SRGB_24                      1
++#       define DEGAMMA_XVYCC_222                    2
++#       define GAMUT_REMAP_BYPASS                   0
++#       define GAMUT_REMAP_PROG_COEFF               1
++#       define GAMUT_REMAP_PROG_SHARED_MATRIXA      2
++#       define GAMUT_REMAP_PROG_SHARED_MATRIXB      3
++
++#       define REGAMMA_BYPASS                       0
++#       define REGAMMA_SRGB_24                      1
++#       define REGAMMA_XVYCC_222                    2
++#       define REGAMMA_PROG_A                       3
++#       define REGAMMA_PROG_B                       4
++
++#       define FMT_CLAMP_6BPC                0
++#       define FMT_CLAMP_8BPC                1
++#       define FMT_CLAMP_10BPC               2
++
++#       define HDMI_24BIT_DEEP_COLOR         0
++#       define HDMI_30BIT_DEEP_COLOR         1
++#       define HDMI_36BIT_DEEP_COLOR         2
++#       define HDMI_ACR_HW                   0
++#       define HDMI_ACR_32                   1
++#       define HDMI_ACR_44                   2
++#       define HDMI_ACR_48                   3
++#       define HDMI_ACR_X1                   1
++#       define HDMI_ACR_X2                   2
++#       define HDMI_ACR_X4                   4
++#       define AFMT_AVI_INFO_Y_RGB           0
++#       define AFMT_AVI_INFO_Y_YCBCR422      1
++#       define AFMT_AVI_INFO_Y_YCBCR444      2
++
++#define			NO_AUTO						0
++#define			ES_AUTO						1
++#define			GS_AUTO						2
++#define			ES_AND_GS_AUTO					3
++
++#       define ARRAY_MODE(x)					((x) << 2)
++#       define PIPE_CONFIG(x)					((x) << 6)
++#       define TILE_SPLIT(x)					((x) << 11)
++#       define MICRO_TILE_MODE_NEW(x)				((x) << 22)
++#       define SAMPLE_SPLIT(x)					((x) << 25)
++#       define BANK_WIDTH(x)					((x) << 0)
++#       define BANK_HEIGHT(x)					((x) << 2)
++#       define MACRO_TILE_ASPECT(x)				((x) << 4)
++#       define NUM_BANKS(x)					((x) << 6)
++
++#define		MSG_ENTER_RLC_SAFE_MODE      			1
++#define		MSG_EXIT_RLC_SAFE_MODE      			0
++
++/*
++ * PM4
++ */
++#define	PACKET_TYPE0	0
++#define	PACKET_TYPE1	1
++#define	PACKET_TYPE2	2
++#define	PACKET_TYPE3	3
++
++#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
++#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
++#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
++#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
++#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
++			 ((reg) & 0xFFFF) |			\
++			 ((n) & 0x3FFF) << 16)
++#define CP_PACKET2			0x80000000
++#define		PACKET2_PAD_SHIFT		0
++#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
++
++#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
++
++#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
++			 (((op) & 0xFF) << 8) |				\
++			 ((n) & 0x3FFF) << 16)
++
++#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
++
++/* Packet 3 types */
++#define	PACKET3_NOP					0x10
++#define	PACKET3_SET_BASE				0x11
++#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
++#define			CE_PARTITION_BASE		3
++#define	PACKET3_CLEAR_STATE				0x12
++#define	PACKET3_INDEX_BUFFER_SIZE			0x13
++#define	PACKET3_DISPATCH_DIRECT				0x15
++#define	PACKET3_DISPATCH_INDIRECT			0x16
++#define	PACKET3_ATOMIC_GDS				0x1D
++#define	PACKET3_ATOMIC_MEM				0x1E
++#define	PACKET3_OCCLUSION_QUERY				0x1F
++#define	PACKET3_SET_PREDICATION				0x20
++#define	PACKET3_REG_RMW					0x21
++#define	PACKET3_COND_EXEC				0x22
++#define	PACKET3_PRED_EXEC				0x23
++#define	PACKET3_DRAW_INDIRECT				0x24
++#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
++#define	PACKET3_INDEX_BASE				0x26
++#define	PACKET3_DRAW_INDEX_2				0x27
++#define	PACKET3_CONTEXT_CONTROL				0x28
++#define	PACKET3_INDEX_TYPE				0x2A
++#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
++#define	PACKET3_DRAW_INDEX_AUTO				0x2D
++#define	PACKET3_NUM_INSTANCES				0x2F
++#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
++#define	PACKET3_INDIRECT_BUFFER_CONST			0x33
++#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
++#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
++#define	PACKET3_DRAW_PREAMBLE				0x36
++#define	PACKET3_WRITE_DATA				0x37
++#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
++		/* 0 - register
++		 * 1 - memory (sync - via GRBM)
++		 * 2 - gl2
++		 * 3 - gds
++		 * 4 - reserved
++		 * 5 - memory (async - direct)
++		 */
++#define		WR_ONE_ADDR                             (1 << 16)
++#define		WR_CONFIRM                              (1 << 20)
++#define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
++		/* 0 - LRU
++		 * 1 - Stream
++		 */
++#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
++		/* 0 - me
++		 * 1 - pfp
++		 * 2 - ce
++		 */
++#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
++#define	PACKET3_MEM_SEMAPHORE				0x39
++#              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
++#              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
++#              define PACKET3_SEM_CLIENT_CODE	    ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
++#              define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
++#              define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
++#define	PACKET3_COPY_DW					0x3B
++#define	PACKET3_WAIT_REG_MEM				0x3C
++#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
++		/* 0 - always
++		 * 1 - <
++		 * 2 - <=
++		 * 3 - ==
++		 * 4 - !=
++		 * 5 - >=
++		 * 6 - >
++		 */
++#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
++		/* 0 - reg
++		 * 1 - mem
++		 */
++#define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
++		/* 0 - wait_reg_mem
++		 * 1 - wr_wait_wr_reg
++		 */
++#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
++		/* 0 - me
++		 * 1 - pfp
++		 */
++#define	PACKET3_INDIRECT_BUFFER				0x3F
++#define		INDIRECT_BUFFER_TCL2_VOLATILE           (1 << 22)
++#define		INDIRECT_BUFFER_VALID                   (1 << 23)
++#define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#define	PACKET3_COPY_DATA				0x40
++#define	PACKET3_PFP_SYNC_ME				0x42
++#define	PACKET3_SURFACE_SYNC				0x43
++#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
++#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
++#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
++#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
++#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
++#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
++#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
++#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
++#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
++#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
++#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
++#              define PACKET3_TCL1_VOL_ACTION_ENA  (1 << 15)
++#              define PACKET3_TC_VOL_ACTION_ENA    (1 << 16) /* L2 */
++#              define PACKET3_TC_WB_ACTION_ENA     (1 << 18) /* L2 */
++#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
++#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
++#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
++#              define PACKET3_TC_ACTION_ENA        (1 << 23) /* L2 */
++#              define PACKET3_CB_ACTION_ENA        (1 << 25)
++#              define PACKET3_DB_ACTION_ENA        (1 << 26)
++#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
++#              define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
++#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
++#define	PACKET3_COND_WRITE				0x45
++#define	PACKET3_EVENT_WRITE				0x46
++#define		EVENT_TYPE(x)                           ((x) << 0)
++#define		EVENT_INDEX(x)                          ((x) << 8)
++		/* 0 - any non-TS event
++		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
++		 * 2 - SAMPLE_PIPELINESTAT
++		 * 3 - SAMPLE_STREAMOUTSTAT*
++		 * 4 - *S_PARTIAL_FLUSH
++		 * 5 - EOP events
++		 * 6 - EOS events
++		 */
++#define	PACKET3_EVENT_WRITE_EOP				0x47
++#define		EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
++#define		EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
++#define		EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
++#define		EOP_TCL1_ACTION_EN                      (1 << 16)
++#define		EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
++#define		EOP_TCL2_VOLATILE                       (1 << 24)
++#define		EOP_CACHE_POLICY(x)                     ((x) << 25)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#define		DATA_SEL(x)                             ((x) << 29)
++		/* 0 - discard
++		 * 1 - send low 32bit data
++		 * 2 - send 64bit data
++		 * 3 - send 64bit GPU counter value
++		 * 4 - send 64bit sys counter value
++		 */
++#define		INT_SEL(x)                              ((x) << 24)
++		/* 0 - none
++		 * 1 - interrupt only (DATA_SEL = 0)
++		 * 2 - interrupt when data write is confirmed
++		 */
++#define		DST_SEL(x)                              ((x) << 16)
++		/* 0 - MC
++		 * 1 - TC/L2
++		 */
++#define	PACKET3_EVENT_WRITE_EOS				0x48
++#define	PACKET3_RELEASE_MEM				0x49
++#define	PACKET3_PREAMBLE_CNTL				0x4A
++#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
++#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
++#define	PACKET3_DMA_DATA				0x50
++/* 1. header
++ * 2. CONTROL
++ * 3. SRC_ADDR_LO or DATA [31:0]
++ * 4. SRC_ADDR_HI [31:0]
++ * 5. DST_ADDR_LO [31:0]
++ * 6. DST_ADDR_HI [7:0]
++ * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
++ */
++/* CONTROL */
++#              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
++		/* 0 - ME
++		 * 1 - PFP
++		 */
++#              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#              define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
++#              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
++		/* 0 - DST_ADDR using DAS
++		 * 1 - GDS
++		 * 3 - DST_ADDR using L2
++		 */
++#              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#              define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
++#              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
++		/* 0 - SRC_ADDR using SAS
++		 * 1 - GDS
++		 * 2 - DATA
++		 * 3 - SRC_ADDR using L2
++		 */
++#              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
++/* COMMAND */
++#              define PACKET3_DMA_DATA_DIS_WC      (1 << 21)
++#              define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
++		/* 0 - none
++		 * 1 - 8 in 16
++		 * 2 - 8 in 32
++		 * 3 - 8 in 64
++		 */
++#              define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
++		/* 0 - none
++		 * 1 - 8 in 16
++		 * 2 - 8 in 32
++		 * 3 - 8 in 64
++		 */
++#              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
++		/* 0 - memory
++		 * 1 - register
++		 */
++#              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
++		/* 0 - memory
++		 * 1 - register
++		 */
++#              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
++#              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
++#              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
++#define	PACKET3_AQUIRE_MEM				0x58
++#define	PACKET3_REWIND					0x59
++#define	PACKET3_LOAD_UCONFIG_REG			0x5E
++#define	PACKET3_LOAD_SH_REG				0x5F
++#define	PACKET3_LOAD_CONFIG_REG				0x60
++#define	PACKET3_LOAD_CONTEXT_REG			0x61
++#define	PACKET3_SET_CONFIG_REG				0x68
++#define		PACKET3_SET_CONFIG_REG_START			0x00002000
++#define		PACKET3_SET_CONFIG_REG_END			0x00002c00
++#define	PACKET3_SET_CONTEXT_REG				0x69
++#define		PACKET3_SET_CONTEXT_REG_START			0x0000a000
++#define		PACKET3_SET_CONTEXT_REG_END			0x0000a400
++#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
++#define	PACKET3_SET_SH_REG				0x76
++#define		PACKET3_SET_SH_REG_START			0x00002c00
++#define		PACKET3_SET_SH_REG_END				0x00003000
++#define	PACKET3_SET_SH_REG_OFFSET			0x77
++#define	PACKET3_SET_QUEUE_REG				0x78
++#define	PACKET3_SET_UCONFIG_REG				0x79
++#define		PACKET3_SET_UCONFIG_REG_START			0x0000c000
++#define		PACKET3_SET_UCONFIG_REG_END			0x0000c400
++#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
++#define	PACKET3_SCRATCH_RAM_READ			0x7E
++#define	PACKET3_LOAD_CONST_RAM				0x80
++#define	PACKET3_WRITE_CONST_RAM				0x81
++#define	PACKET3_DUMP_CONST_RAM				0x83
++#define	PACKET3_INCREMENT_CE_COUNTER			0x84
++#define	PACKET3_INCREMENT_DE_COUNTER			0x85
++#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
++#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
++#define	PACKET3_SWITCH_BUFFER				0x8B
++
++/* SDMA - first instance at 0xd000, second at 0xd800 */
++#define SDMA0_REGISTER_OFFSET                             0x0 /* not a register */
++#define SDMA1_REGISTER_OFFSET                             0x200 /* not a register */
++#define SDMA_MAX_INSTANCE 2
++
++#define SDMA_PACKET(op, sub_op, e)	((((e) & 0xFFFF) << 16) |	\
++					 (((sub_op) & 0xFF) << 8) |	\
++					 (((op) & 0xFF) << 0))
++/* sDMA opcodes */
++#define	SDMA_OPCODE_NOP					  0
++#define	SDMA_OPCODE_COPY				  1
++#       define SDMA_COPY_SUB_OPCODE_LINEAR                0
++#       define SDMA_COPY_SUB_OPCODE_TILED                 1
++#       define SDMA_COPY_SUB_OPCODE_SOA                   3
++#       define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW     4
++#       define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW      5
++#       define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW        6
++#define	SDMA_OPCODE_WRITE				  2
++#       define SDMA_WRITE_SUB_OPCODE_LINEAR               0
++#       define SDMA_WRTIE_SUB_OPCODE_TILED                1
++#define	SDMA_OPCODE_INDIRECT_BUFFER			  4
++#define	SDMA_OPCODE_FENCE				  5
++#define	SDMA_OPCODE_TRAP				  6
++#define	SDMA_OPCODE_SEMAPHORE				  7
++#       define SDMA_SEMAPHORE_EXTRA_O                     (1 << 13)
++		/* 0 - increment
++		 * 1 - write 1
++		 */
++#       define SDMA_SEMAPHORE_EXTRA_S                     (1 << 14)
++		/* 0 - wait
++		 * 1 - signal
++		 */
++#       define SDMA_SEMAPHORE_EXTRA_M                     (1 << 15)
++		/* mailbox */
++#define	SDMA_OPCODE_POLL_REG_MEM			  8
++#       define SDMA_POLL_REG_MEM_EXTRA_OP(x)              ((x) << 10)
++		/* 0 - wait_reg_mem
++		 * 1 - wr_wait_wr_reg
++		 */
++#       define SDMA_POLL_REG_MEM_EXTRA_FUNC(x)            ((x) << 12)
++		/* 0 - always
++		 * 1 - <
++		 * 2 - <=
++		 * 3 - ==
++		 * 4 - !=
++		 * 5 - >=
++		 * 6 - >
++		 */
++#       define SDMA_POLL_REG_MEM_EXTRA_M                  (1 << 15)
++		/* 0 = register
++		 * 1 = memory
++		 */
++#define	SDMA_OPCODE_COND_EXEC				  9
++#define	SDMA_OPCODE_CONSTANT_FILL			  11
++#       define SDMA_CONSTANT_FILL_EXTRA_SIZE(x)           ((x) << 14)
++		/* 0 = byte fill
++		 * 2 = DW fill
++		 */
++#define	SDMA_OPCODE_GENERATE_PTE_PDE			  12
++#define	SDMA_OPCODE_TIMESTAMP				  13
++#       define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL        0
++#       define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL        1
++#       define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL       2
++#define	SDMA_OPCODE_SRBM_WRITE				  14
++#       define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x)       ((x) << 12)
++		/* byte mask */
++
++#define VCE_CMD_NO_OP		0x00000000
++#define VCE_CMD_END		0x00000001
++#define VCE_CMD_IB		0x00000002
++#define VCE_CMD_FENCE		0x00000003
++#define VCE_CMD_TRAP		0x00000004
++#define VCE_CMD_IB_AUTO		0x00000005
++#define VCE_CMD_SEMAPHORE	0x00000006
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0036-yocto-amd-drm-amdgpu-add-DCE-11-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0036-yocto-amd-drm-amdgpu-add-DCE-11-0-register-headers.patch
new file mode 100644
index 00000000..25794fa9
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0036-yocto-amd-drm-amdgpu-add-DCE-11-0-register-headers.patch
@@ -0,0 +1,78 @@
+From d5fb272c56a68d4cae42a80c37a7dd320e57c3bc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Apr 2015 15:48:09 -0400
+Subject: drm/amdgpu: fix const warnings in amdgpu_connectors.c
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+index 6a8d28f..27df17a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+@@ -135,7 +135,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
+ 		if (connector->display_info.bpc)
+ 			bpc = connector->display_info.bpc;
+ 		else {
+-			struct drm_connector_helper_funcs *connector_funcs =
++			const struct drm_connector_helper_funcs *connector_funcs =
+ 				connector->helper_private;
+ 			struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
+ 			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+@@ -216,7 +216,7 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
+ {
+ 	struct drm_encoder *best_encoder = NULL;
+ 	struct drm_encoder *encoder = NULL;
+-	struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
++	const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
+ 	bool connected;
+ 	int i;
+ 
+@@ -597,7 +597,7 @@ static int amdgpu_connector_set_property(struct drm_connector *connector,
+ 		if (connector->encoder) {
+ 			amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
+ 		} else {
+-			struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
++			const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
+ 			amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
+ 		}
+ 
+@@ -788,7 +788,7 @@ static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
+ 	if (connector->encoder)
+ 		amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
+ 	else {
+-		struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
++		const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
+ 		amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
+ 	}
+ 
+@@ -852,7 +852,7 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
+ {
+ 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 	struct drm_encoder *encoder;
+-	struct drm_encoder_helper_funcs *encoder_funcs;
++	const struct drm_encoder_helper_funcs *encoder_funcs;
+ 	bool dret = false;
+ 	enum drm_connector_status ret = connector_status_disconnected;
+ 	int r;
+@@ -971,7 +971,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 	struct drm_encoder *encoder = NULL;
+-	struct drm_encoder_helper_funcs *encoder_funcs;
++	const struct drm_encoder_helper_funcs *encoder_funcs;
+ 	int i, r;
+ 	enum drm_connector_status ret = connector_status_disconnected;
+ 	bool dret = false, broken_edid = false;
+@@ -1391,7 +1391,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
+ 			if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
+ 				ret = connector_status_connected;
+ 			else if (amdgpu_connector->dac_load_detect) { /* try load detection */
+-				struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
++				const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
+ 				ret = encoder_funcs->detect(encoder, connector);
+ 			}
+ 		}
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0037-yocto-amd-drm-amdgpu-add-DCE-10-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0037-yocto-amd-drm-amdgpu-add-DCE-10-0-register-headers.patch
new file mode 100644
index 00000000..8535ac98
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0037-yocto-amd-drm-amdgpu-add-DCE-10-0-register-headers.patch
@@ -0,0 +1,51 @@
+From 704b46b07711e5459ae845bc5ef074dda2473361 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 17 Apr 2015 10:50:02 -0400
+Subject: drm/amdgpu: Do not directly dereference pointers to BIOS area.
+
+Use readb() and memcpy_fromio() accessors instead.
+
+Ported from radeon commit:
+f2c9e560b406f2f6b14b345c7da33467dee9cdf2
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+index d938a11..cdcadf8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+@@ -75,7 +75,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
+ 
+ bool amdgpu_read_bios(struct amdgpu_device *adev)
+ {
+-	uint8_t __iomem *bios;
++	uint8_t __iomem *bios, val1, val2;
+ 	size_t size;
+ 
+ 	adev->bios = NULL;
+@@ -85,15 +85,19 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
+ 		return false;
+ 	}
+ 
+-	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
++	val1 = readb(&bios[0]);
++	val2 = readb(&bios[1]);
++
++	if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
+ 		pci_unmap_rom(adev->pdev, bios);
+ 		return false;
+ 	}
+-	adev->bios = kmemdup(bios, size, GFP_KERNEL);
++	adev->bios = kzalloc(size, GFP_KERNEL);
+ 	if (adev->bios == NULL) {
+ 		pci_unmap_rom(adev->pdev, bios);
+ 		return false;
+ 	}
++	memcpy_fromio(adev->bios, bios, size);
+ 	pci_unmap_rom(adev->pdev, bios);
+ 	return true;
+ }
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0038-yocto-amd-drm-amdgpu-add-DCE-8-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0038-yocto-amd-drm-amdgpu-add-DCE-8-0-register-headers.patch
new file mode 100644
index 00000000..8311a3ed
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0038-yocto-amd-drm-amdgpu-add-DCE-8-0-register-headers.patch
@@ -0,0 +1,30215 @@
+From 19f67d8fe982a14725e3ab94697ca490cfcbf62a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 17:09:27 -0400
+Subject: drm/amdgpu: Add support for CIK parts
+
+This patch adds support for CIK parts.  These parts
+are also supported by radeon which is the preferred
+option, so there is a config option to enable support
+for CIK parts in amdgpu for testing.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 01276a5..aec2886 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -18,6 +18,9 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
+ 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
+ 
++amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \
++	ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
++
+ # add IH block
+ amdgpu-y += \
+ 	amdgpu_irq.o \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index cd4bb90..548e084 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -38,6 +38,9 @@
+ #include "amdgpu_i2c.h"
+ #include "atom.h"
+ #include "amdgpu_atombios.h"
++#ifdef CONFIG_DRM_AMDGPU_CIK
++#include "cik.h"
++#endif
+ #include "bif/bif_4_1_d.h"
+ 
+ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
+@@ -1154,6 +1157,22 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
+ 	int i, r = -EINVAL;
+ 
+ 	switch (adev->asic_type) {
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	case CHIP_BONAIRE:
++	case CHIP_HAWAII:
++	case CHIP_KAVERI:
++	case CHIP_KABINI:
++	case CHIP_MULLINS:
++		if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
++			adev->family = AMDGPU_FAMILY_CI;
++		else
++			adev->family = AMDGPU_FAMILY_KV;
++
++		r = cik_set_ip_blocks(adev);
++		if (r)
++			return r;
++		break;
++#endif
+ 	default:
+ 		/* FIXME: not supported yet */
+ 		return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+new file mode 100644
+index 0000000..5a9dad8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+@@ -0,0 +1,6684 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_ucode.h"
++#include "cikd.h"
++#include "amdgpu_dpm.h"
++#include "ci_dpm.h"
++#include "gfx_v7_0.h"
++#include "atom.h"
++#include <linux/seq_file.h>
++
++#include "smu/smu_7_0_1_d.h"
++#include "smu/smu_7_0_1_sh_mask.h"
++
++#include "dce/dce_8_0_d.h"
++#include "dce/dce_8_0_sh_mask.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "gca/gfx_7_2_d.h"
++#include "gca/gfx_7_2_sh_mask.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++MODULE_FIRMWARE("radeon/bonaire_smc.bin");
++MODULE_FIRMWARE("radeon/hawaii_smc.bin");
++
++#define MC_CG_ARB_FREQ_F0           0x0a
++#define MC_CG_ARB_FREQ_F1           0x0b
++#define MC_CG_ARB_FREQ_F2           0x0c
++#define MC_CG_ARB_FREQ_F3           0x0d
++
++#define SMC_RAM_END 0x40000
++
++#define VOLTAGE_SCALE               4
++#define VOLTAGE_VID_OFFSET_SCALE1    625
++#define VOLTAGE_VID_OFFSET_SCALE2    100
++
++static const struct ci_pt_defaults defaults_hawaii_xt =
++{
++	1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
++	{ 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
++	{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
++};
++
++static const struct ci_pt_defaults defaults_hawaii_pro =
++{
++	1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
++	{ 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
++	{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
++};
++
++static const struct ci_pt_defaults defaults_bonaire_xt =
++{
++	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
++	{ 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
++	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
++};
++
++static const struct ci_pt_defaults defaults_bonaire_pro =
++{
++	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
++	{ 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
++	{ 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
++};
++
++static const struct ci_pt_defaults defaults_saturn_xt =
++{
++	1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
++	{ 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
++	{ 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
++};
++
++static const struct ci_pt_defaults defaults_saturn_pro =
++{
++	1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
++	{ 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
++	{ 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
++};
++
++static const struct ci_pt_config_reg didt_config_ci[] =
++{
++	{ 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
++	{ 0xFFFFFFFF }
++};
++
++static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
++{
++	return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
++}
++
++#define MC_CG_ARB_FREQ_F0           0x0a
++#define MC_CG_ARB_FREQ_F1           0x0b
++#define MC_CG_ARB_FREQ_F2           0x0c
++#define MC_CG_ARB_FREQ_F3           0x0d
++
++static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
++				       u32 arb_freq_src, u32 arb_freq_dest)
++{
++	u32 mc_arb_dram_timing;
++	u32 mc_arb_dram_timing2;
++	u32 burst_time;
++	u32 mc_cg_config;
++
++	switch (arb_freq_src) {
++	case MC_CG_ARB_FREQ_F0:
++		mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
++		mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
++		burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
++			 MC_ARB_BURST_TIME__STATE0__SHIFT;
++		break;
++	case MC_CG_ARB_FREQ_F1:
++		mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
++		mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
++		burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
++			 MC_ARB_BURST_TIME__STATE1__SHIFT;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	switch (arb_freq_dest) {
++	case MC_CG_ARB_FREQ_F0:
++		WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
++		WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
++		WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
++			~MC_ARB_BURST_TIME__STATE0_MASK);
++		break;
++	case MC_CG_ARB_FREQ_F1:
++		WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
++		WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
++		WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
++			~MC_ARB_BURST_TIME__STATE1_MASK);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
++	WREG32(mmMC_CG_CONFIG, mc_cg_config);
++	WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
++		~MC_ARB_CG__CG_ARB_REQ_MASK);
++
++	return 0;
++}
++
++static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
++{
++	u8 mc_para_index;
++
++	if (memory_clock < 10000)
++		mc_para_index = 0;
++	else if (memory_clock >= 80000)
++		mc_para_index = 0x0f;
++	else
++		mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
++	return mc_para_index;
++}
++
++static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
++{
++	u8 mc_para_index;
++
++	if (strobe_mode) {
++		if (memory_clock < 12500)
++			mc_para_index = 0x00;
++		else if (memory_clock > 47500)
++			mc_para_index = 0x0f;
++		else
++			mc_para_index = (u8)((memory_clock - 10000) / 2500);
++	} else {
++		if (memory_clock < 65000)
++			mc_para_index = 0x00;
++		else if (memory_clock > 135000)
++			mc_para_index = 0x0f;
++		else
++			mc_para_index = (u8)((memory_clock - 60000) / 5000);
++	}
++	return mc_para_index;
++}
++
++static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
++						     u32 max_voltage_steps,
++						     struct atom_voltage_table *voltage_table)
++{
++	unsigned int i, diff;
++
++	if (voltage_table->count <= max_voltage_steps)
++		return;
++
++	diff = voltage_table->count - max_voltage_steps;
++
++	for (i = 0; i < max_voltage_steps; i++)
++		voltage_table->entries[i] = voltage_table->entries[i + diff];
++
++	voltage_table->count = max_voltage_steps;
++}
++
++static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
++					 struct atom_voltage_table_entry *voltage_table,
++					 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
++static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
++static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
++				       u32 target_tdp);
++static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
++static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
++static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
++
++static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++							     PPSMC_Msg msg, u32 parameter);
++static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
++static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
++
++static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = adev->pm.dpm.priv;
++
++	return pi;
++}
++
++static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
++{
++	struct ci_ps *ps = rps->ps_priv;
++
++	return ps;
++}
++
++static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	switch (adev->pdev->device) {
++	case 0x6649:
++	case 0x6650:
++	case 0x6651:
++	case 0x6658:
++	case 0x665C:
++	case 0x665D:
++	default:
++		pi->powertune_defaults = &defaults_bonaire_xt;
++		break;
++	case 0x6640:
++	case 0x6641:
++	case 0x6646:
++	case 0x6647:
++		pi->powertune_defaults = &defaults_saturn_xt;
++		break;
++	case 0x67B8:
++	case 0x67B0:
++		pi->powertune_defaults = &defaults_hawaii_xt;
++		break;
++	case 0x67BA:
++	case 0x67B1:
++		pi->powertune_defaults = &defaults_hawaii_pro;
++		break;
++	case 0x67A0:
++	case 0x67A1:
++	case 0x67A2:
++	case 0x67A8:
++	case 0x67A9:
++	case 0x67AA:
++	case 0x67B9:
++	case 0x67BE:
++		pi->powertune_defaults = &defaults_bonaire_xt;
++		break;
++	}
++
++	pi->dte_tj_offset = 0;
++
++	pi->caps_power_containment = true;
++	pi->caps_cac = false;
++	pi->caps_sq_ramping = false;
++	pi->caps_db_ramping = false;
++	pi->caps_td_ramping = false;
++	pi->caps_tcp_ramping = false;
++
++	if (pi->caps_power_containment) {
++		pi->caps_cac = true;
++		if (adev->asic_type == CHIP_HAWAII)
++			pi->enable_bapm_feature = false;
++		else
++			pi->enable_bapm_feature = true;
++		pi->enable_tdc_limit_feature = true;
++		pi->enable_pkg_pwr_tracking_feature = true;
++	}
++}
++
++static u8 ci_convert_to_vid(u16 vddc)
++{
++	return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
++}
++
++static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
++	u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
++	u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
++	u32 i;
++
++	if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
++		return -EINVAL;
++	if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
++		return -EINVAL;
++	if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
++	    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
++		return -EINVAL;
++
++	for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
++		if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
++			lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
++			hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
++			hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
++		} else {
++			lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
++			hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
++		}
++	}
++	return 0;
++}
++
++static int ci_populate_vddc_vid(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u8 *vid = pi->smc_powertune_table.VddCVid;
++	u32 i;
++
++	if (pi->vddc_voltage_table.count > 8)
++		return -EINVAL;
++
++	for (i = 0; i < pi->vddc_voltage_table.count; i++)
++		vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
++
++	return 0;
++}
++
++static int ci_populate_svi_load_line(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
++
++	pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
++	pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
++	pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
++	pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
++
++	return 0;
++}
++
++static int ci_populate_tdc_limit(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
++	u16 tdc_limit;
++
++	tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
++	pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
++	pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
++		pt_defaults->tdc_vddc_throttle_release_limit_perc;
++	pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
++
++	return 0;
++}
++
++static int ci_populate_dw8(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
++	int ret;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev,
++				     SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, PmFuseTable) +
++				     offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
++				     (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
++				     pi->sram_end);
++	if (ret)
++		return -EINVAL;
++	else
++		pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
++
++	return 0;
++}
++
++static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
++	    (adev->pm.dpm.fan.fan_output_sensitivity == 0))
++		adev->pm.dpm.fan.fan_output_sensitivity =
++			adev->pm.dpm.fan.default_fan_output_sensitivity;
++
++	pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
++		cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
++
++	return 0;
++}
++
++static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
++	u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
++	int i, min, max;
++
++	min = max = hi_vid[0];
++	for (i = 0; i < 8; i++) {
++		if (0 != hi_vid[i]) {
++			if (min > hi_vid[i])
++				min = hi_vid[i];
++			if (max < hi_vid[i])
++				max = hi_vid[i];
++		}
++
++		if (0 != lo_vid[i]) {
++			if (min > lo_vid[i])
++				min = lo_vid[i];
++			if (max < lo_vid[i])
++				max = lo_vid[i];
++		}
++	}
++
++	if ((min == 0) || (max == 0))
++		return -EINVAL;
++	pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
++	pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
++
++	return 0;
++}
++
++static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
++	u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
++	struct amdgpu_cac_tdp_table *cac_tdp_table =
++		adev->pm.dpm.dyn_state.cac_tdp_table;
++
++	hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
++	lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
++
++	pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
++	pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
++
++	return 0;
++}
++
++static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
++	SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
++	struct amdgpu_cac_tdp_table *cac_tdp_table =
++		adev->pm.dpm.dyn_state.cac_tdp_table;
++	struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
++	int i, j, k;
++	const u16 *def1;
++	const u16 *def2;
++
++	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
++	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
++
++	dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
++	dpm_table->GpuTjMax =
++		(u8)(pi->thermal_temp_setting.temperature_high / 1000);
++	dpm_table->GpuTjHyst = 8;
++
++	dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
++
++	if (ppm) {
++		dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
++		dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
++	} else {
++		dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
++		dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
++	}
++
++	dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
++	def1 = pt_defaults->bapmti_r;
++	def2 = pt_defaults->bapmti_rc;
++
++	for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
++		for (j = 0; j < SMU7_DTE_SOURCES; j++) {
++			for (k = 0; k < SMU7_DTE_SINKS; k++) {
++				dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
++				dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
++				def1++;
++				def2++;
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int ci_populate_pm_base(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 pm_fuse_table_offset;
++	int ret;
++
++	if (pi->caps_power_containment) {
++		ret = amdgpu_ci_read_smc_sram_dword(adev,
++					     SMU7_FIRMWARE_HEADER_LOCATION +
++					     offsetof(SMU7_Firmware_Header, PmFuseTable),
++					     &pm_fuse_table_offset, pi->sram_end);
++		if (ret)
++			return ret;
++		ret = ci_populate_bapm_vddc_vid_sidd(adev);
++		if (ret)
++			return ret;
++		ret = ci_populate_vddc_vid(adev);
++		if (ret)
++			return ret;
++		ret = ci_populate_svi_load_line(adev);
++		if (ret)
++			return ret;
++		ret = ci_populate_tdc_limit(adev);
++		if (ret)
++			return ret;
++		ret = ci_populate_dw8(adev);
++		if (ret)
++			return ret;
++		ret = ci_populate_fuzzy_fan(adev);
++		if (ret)
++			return ret;
++		ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
++		if (ret)
++			return ret;
++		ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
++		if (ret)
++			return ret;
++		ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
++					   (u8 *)&pi->smc_powertune_table,
++					   sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 data;
++
++	if (pi->caps_sq_ramping) {
++		data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
++		if (enable)
++			data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
++	}
++
++	if (pi->caps_db_ramping) {
++		data = RREG32_DIDT(ixDIDT_DB_CTRL0);
++		if (enable)
++			data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_DB_CTRL0, data);
++	}
++
++	if (pi->caps_td_ramping) {
++		data = RREG32_DIDT(ixDIDT_TD_CTRL0);
++		if (enable)
++			data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_TD_CTRL0, data);
++	}
++
++	if (pi->caps_tcp_ramping) {
++		data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
++		if (enable)
++			data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
++	}
++}
++
++static int ci_program_pt_config_registers(struct amdgpu_device *adev,
++					  const struct ci_pt_config_reg *cac_config_regs)
++{
++	const struct ci_pt_config_reg *config_regs = cac_config_regs;
++	u32 data;
++	u32 cache = 0;
++
++	if (config_regs == NULL)
++		return -EINVAL;
++
++	while (config_regs->offset != 0xFFFFFFFF) {
++		if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
++			cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
++		} else {
++			switch (config_regs->type) {
++			case CISLANDS_CONFIGREG_SMC_IND:
++				data = RREG32_SMC(config_regs->offset);
++				break;
++			case CISLANDS_CONFIGREG_DIDT_IND:
++				data = RREG32_DIDT(config_regs->offset);
++				break;
++			default:
++				data = RREG32(config_regs->offset);
++				break;
++			}
++
++			data &= ~config_regs->mask;
++			data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
++			data |= cache;
++
++			switch (config_regs->type) {
++			case CISLANDS_CONFIGREG_SMC_IND:
++				WREG32_SMC(config_regs->offset, data);
++				break;
++			case CISLANDS_CONFIGREG_DIDT_IND:
++				WREG32_DIDT(config_regs->offset, data);
++				break;
++			default:
++				WREG32(config_regs->offset, data);
++				break;
++			}
++			cache = 0;
++		}
++		config_regs++;
++	}
++	return 0;
++}
++
++static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret;
++
++	if (pi->caps_sq_ramping || pi->caps_db_ramping ||
++	    pi->caps_td_ramping || pi->caps_tcp_ramping) {
++		gfx_v7_0_enter_rlc_safe_mode(adev);
++
++		if (enable) {
++			ret = ci_program_pt_config_registers(adev, didt_config_ci);
++			if (ret) {
++				gfx_v7_0_exit_rlc_safe_mode(adev);
++				return ret;
++			}
++		}
++
++		ci_do_enable_didt(adev, enable);
++
++		gfx_v7_0_exit_rlc_safe_mode(adev);
++	}
++
++	return 0;
++}
++
++static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++	int ret = 0;
++
++	if (enable) {
++		pi->power_containment_features = 0;
++		if (pi->caps_power_containment) {
++			if (pi->enable_bapm_feature) {
++				smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
++				if (smc_result != PPSMC_Result_OK)
++					ret = -EINVAL;
++				else
++					pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
++			}
++
++			if (pi->enable_tdc_limit_feature) {
++				smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
++				if (smc_result != PPSMC_Result_OK)
++					ret = -EINVAL;
++				else
++					pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
++			}
++
++			if (pi->enable_pkg_pwr_tracking_feature) {
++				smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
++				if (smc_result != PPSMC_Result_OK) {
++					ret = -EINVAL;
++				} else {
++					struct amdgpu_cac_tdp_table *cac_tdp_table =
++						adev->pm.dpm.dyn_state.cac_tdp_table;
++					u32 default_pwr_limit =
++						(u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
++
++					pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
++
++					ci_set_power_limit(adev, default_pwr_limit);
++				}
++			}
++		}
++	} else {
++		if (pi->caps_power_containment && pi->power_containment_features) {
++			if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
++				amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
++
++			if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
++				amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
++
++			if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
++				amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
++			pi->power_containment_features = 0;
++		}
++	}
++
++	return ret;
++}
++
++static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++	int ret = 0;
++
++	if (pi->caps_cac) {
++		if (enable) {
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
++			if (smc_result != PPSMC_Result_OK) {
++				ret = -EINVAL;
++				pi->cac_enabled = false;
++			} else {
++				pi->cac_enabled = true;
++			}
++		} else if (pi->cac_enabled) {
++			amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
++			pi->cac_enabled = false;
++		}
++	}
++
++	return ret;
++}
++
++static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
++					    bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result = PPSMC_Result_OK;
++
++	if (pi->thermal_sclk_dpm_enabled) {
++		if (enable)
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
++		else
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
++	}
++
++	if (smc_result == PPSMC_Result_OK)
++		return 0;
++	else
++		return -EINVAL;
++}
++
++static int ci_power_control_set_level(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_cac_tdp_table *cac_tdp_table =
++		adev->pm.dpm.dyn_state.cac_tdp_table;
++	s32 adjust_percent;
++	s32 target_tdp;
++	int ret = 0;
++	bool adjust_polarity = false; /* ??? */
++
++	if (pi->caps_power_containment) {
++		adjust_percent = adjust_polarity ?
++			adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
++		target_tdp = ((100 + adjust_percent) *
++			      (s32)cac_tdp_table->configurable_tdp) / 100;
++
++		ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
++	}
++
++	return ret;
++}
++
++static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (pi->uvd_power_gated == gate)
++		return;
++
++	pi->uvd_power_gated = gate;
++
++	ci_update_uvd_dpm(adev, gate);
++}
++
++static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
++{
++	u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
++	u32 switch_limit = adev->mc.is_gddr5 ? 450 : 300;
++
++	if (vblank_time < switch_limit)
++		return true;
++	else
++		return false;
++
++}
++
++static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
++					struct amdgpu_ps *rps)
++{
++	struct ci_ps *ps = ci_get_ps(rps);
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_clock_and_voltage_limits *max_limits;
++	bool disable_mclk_switching;
++	u32 sclk, mclk;
++	int i;
++
++	if (rps->vce_active) {
++		rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
++		rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
++	} else {
++		rps->evclk = 0;
++		rps->ecclk = 0;
++	}
++
++	if ((adev->pm.dpm.new_active_crtc_count > 1) ||
++	    ci_dpm_vblank_too_short(adev))
++		disable_mclk_switching = true;
++	else
++		disable_mclk_switching = false;
++
++	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
++		pi->battery_state = true;
++	else
++		pi->battery_state = false;
++
++	if (adev->pm.dpm.ac_power)
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	else
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
++
++	if (adev->pm.dpm.ac_power == false) {
++		for (i = 0; i < ps->performance_level_count; i++) {
++			if (ps->performance_levels[i].mclk > max_limits->mclk)
++				ps->performance_levels[i].mclk = max_limits->mclk;
++			if (ps->performance_levels[i].sclk > max_limits->sclk)
++				ps->performance_levels[i].sclk = max_limits->sclk;
++		}
++	}
++
++	/* XXX validate the min clocks required for display */
++
++	if (disable_mclk_switching) {
++		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
++		sclk = ps->performance_levels[0].sclk;
++	} else {
++		mclk = ps->performance_levels[0].mclk;
++		sclk = ps->performance_levels[0].sclk;
++	}
++
++	if (rps->vce_active) {
++		if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
++			sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
++		if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
++			mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
++	}
++
++	ps->performance_levels[0].sclk = sclk;
++	ps->performance_levels[0].mclk = mclk;
++
++	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
++		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
++
++	if (disable_mclk_switching) {
++		if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
++			ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
++	} else {
++		if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
++			ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
++	}
++}
++
++static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
++					    int min_temp, int max_temp)
++{
++	int low_temp = 0 * 1000;
++	int high_temp = 255 * 1000;
++	u32 tmp;
++
++	if (low_temp < min_temp)
++		low_temp = min_temp;
++	if (high_temp > max_temp)
++		high_temp = max_temp;
++	if (high_temp < low_temp) {
++		DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
++		return -EINVAL;
++	}
++
++	tmp = RREG32_SMC(ixCG_THERMAL_INT);
++	tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
++	tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
++		((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
++	WREG32_SMC(ixCG_THERMAL_INT, tmp);
++
++#if 0
++	/* XXX: need to figure out how to handle this properly */
++	tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
++	tmp &= DIG_THERM_DPM_MASK;
++	tmp |= DIG_THERM_DPM(high_temp / 1000);
++	WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
++#endif
++
++	adev->pm.dpm.thermal.min_temp = low_temp;
++	adev->pm.dpm.thermal.max_temp = high_temp;
++	return 0;
++}
++
++static int ci_thermal_enable_alert(struct amdgpu_device *adev,
++				   bool enable)
++{
++	u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
++	PPSMC_Result result;
++
++	if (enable) {
++		thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
++				 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
++		WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
++		result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
++		if (result != PPSMC_Result_OK) {
++			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
++			return -EINVAL;
++		}
++	} else {
++		thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
++			CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
++		WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
++		result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
++		if (result != PPSMC_Result_OK) {
++			DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++
++	if (pi->fan_ctrl_is_in_default_mode) {
++		tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
++			>> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
++		pi->fan_ctrl_default_mode = tmp;
++		tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
++			>> CG_FDO_CTRL2__TMIN__SHIFT;
++		pi->t_min = tmp;
++		pi->fan_ctrl_is_in_default_mode = false;
++	}
++
++	tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
++	tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
++	WREG32_SMC(ixCG_FDO_CTRL2, tmp);
++
++	tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
++	tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
++	WREG32_SMC(ixCG_FDO_CTRL2, tmp);
++}
++
++static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
++	u32 duty100;
++	u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
++	u16 fdo_min, slope1, slope2;
++	u32 reference_clock, tmp;
++	int ret;
++	u64 tmp64;
++
++	if (!pi->fan_table_start) {
++		adev->pm.dpm.fan.ucode_fan_control = false;
++		return 0;
++	}
++
++	duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
++		>> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
++
++	if (duty100 == 0) {
++		adev->pm.dpm.fan.ucode_fan_control = false;
++		return 0;
++	}
++
++	tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
++	do_div(tmp64, 10000);
++	fdo_min = (u16)tmp64;
++
++	t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
++	t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
++
++	pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
++	pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
++
++	slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
++	slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
++
++	fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
++	fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
++	fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
++
++	fan_table.Slope1 = cpu_to_be16(slope1);
++	fan_table.Slope2 = cpu_to_be16(slope2);
++
++	fan_table.FdoMin = cpu_to_be16(fdo_min);
++
++	fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
++
++	fan_table.HystUp = cpu_to_be16(1);
++
++	fan_table.HystSlope = cpu_to_be16(1);
++
++	fan_table.TempRespLim = cpu_to_be16(5);
++
++	reference_clock = amdgpu_asic_get_xclk(adev);
++
++	fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
++					       reference_clock) / 1600);
++
++	fan_table.FdoMax = cpu_to_be16((u16)duty100);
++
++	tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
++		>> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
++	fan_table.TempSrc = (uint8_t)tmp;
++
++	ret = amdgpu_ci_copy_bytes_to_smc(adev,
++					  pi->fan_table_start,
++					  (u8 *)(&fan_table),
++					  sizeof(fan_table),
++					  pi->sram_end);
++
++	if (ret) {
++		DRM_ERROR("Failed to load fan table to the SMC.");
++		adev->pm.dpm.fan.ucode_fan_control = false;
++	}
++
++	return 0;
++}
++
++static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result ret;
++
++	if (pi->caps_od_fuzzy_fan_control_support) {
++		ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++							       PPSMC_StartFanControl,
++							       FAN_CONTROL_FUZZY);
++		if (ret != PPSMC_Result_OK)
++			return -EINVAL;
++		ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++							       PPSMC_MSG_SetFanPwmMax,
++							       adev->pm.dpm.fan.default_max_fan_pwm);
++		if (ret != PPSMC_Result_OK)
++			return -EINVAL;
++	} else {
++		ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++							       PPSMC_StartFanControl,
++							       FAN_CONTROL_TABLE);
++		if (ret != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	pi->fan_is_controlled_by_smc = true;
++	return 0;
++}
++
++
++static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
++{
++	PPSMC_Result ret;
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
++	if (ret == PPSMC_Result_OK) {
++		pi->fan_is_controlled_by_smc = false;
++		return 0;
++	} else {
++		return -EINVAL;
++	}
++}
++
++static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
++					u32 *speed)
++{
++	u32 duty, duty100;
++	u64 tmp64;
++
++	if (adev->pm.no_fan)
++		return -ENOENT;
++
++	duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
++		>> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
++	duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
++		>> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
++
++	if (duty100 == 0)
++		return -EINVAL;
++
++	tmp64 = (u64)duty * 100;
++	do_div(tmp64, duty100);
++	*speed = (u32)tmp64;
++
++	if (*speed > 100)
++		*speed = 100;
++
++	return 0;
++}
++
++static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
++					u32 speed)
++{
++	u32 tmp;
++	u32 duty, duty100;
++	u64 tmp64;
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (adev->pm.no_fan)
++		return -ENOENT;
++
++	if (pi->fan_is_controlled_by_smc)
++		return -EINVAL;
++
++	if (speed > 100)
++		return -EINVAL;
++
++	duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
++		>> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
++
++	if (duty100 == 0)
++		return -EINVAL;
++
++	tmp64 = (u64)speed * duty100;
++	do_div(tmp64, 100);
++	duty = (u32)tmp64;
++
++	tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
++	tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
++	WREG32_SMC(ixCG_FDO_CTRL0, tmp);
++
++	return 0;
++}
++
++static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
++{
++	if (mode) {
++		/* stop auto-manage */
++		if (adev->pm.dpm.fan.ucode_fan_control)
++			ci_fan_ctrl_stop_smc_fan_control(adev);
++		ci_fan_ctrl_set_static_mode(adev, mode);
++	} else {
++		/* restart auto-manage */
++		if (adev->pm.dpm.fan.ucode_fan_control)
++			ci_thermal_start_smc_fan_control(adev);
++		else
++			ci_fan_ctrl_set_default_mode(adev);
++	}
++}
++
++static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++
++	if (pi->fan_is_controlled_by_smc)
++		return 0;
++
++	tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
++	return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
++}
++
++#if 0
++static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
++					 u32 *speed)
++{
++	u32 tach_period;
++	u32 xclk = amdgpu_asic_get_xclk(adev);
++
++	if (adev->pm.no_fan)
++		return -ENOENT;
++
++	if (adev->pm.fan_pulses_per_revolution == 0)
++		return -ENOENT;
++
++	tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
++		>> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
++	if (tach_period == 0)
++		return -ENOENT;
++
++	*speed = 60 * xclk * 10000 / tach_period;
++
++	return 0;
++}
++
++static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
++					 u32 speed)
++{
++	u32 tach_period, tmp;
++	u32 xclk = amdgpu_asic_get_xclk(adev);
++
++	if (adev->pm.no_fan)
++		return -ENOENT;
++
++	if (adev->pm.fan_pulses_per_revolution == 0)
++		return -ENOENT;
++
++	if ((speed < adev->pm.fan_min_rpm) ||
++	    (speed > adev->pm.fan_max_rpm))
++		return -EINVAL;
++
++	if (adev->pm.dpm.fan.ucode_fan_control)
++		ci_fan_ctrl_stop_smc_fan_control(adev);
++
++	tach_period = 60 * xclk * 10000 / (8 * speed);
++	tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
++	tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
++	WREG32_SMC(CG_TACH_CTRL, tmp);
++
++	ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
++
++	return 0;
++}
++#endif
++
++static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++
++	if (!pi->fan_ctrl_is_in_default_mode) {
++		tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
++		tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
++		WREG32_SMC(ixCG_FDO_CTRL2, tmp);
++
++		tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
++		tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
++		WREG32_SMC(ixCG_FDO_CTRL2, tmp);
++		pi->fan_ctrl_is_in_default_mode = true;
++	}
++}
++
++static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm.fan.ucode_fan_control) {
++		ci_fan_ctrl_start_smc_fan_control(adev);
++		ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
++	}
++}
++
++static void ci_thermal_initialize(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	if (adev->pm.fan_pulses_per_revolution) {
++		tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
++		tmp |= (adev->pm.fan_pulses_per_revolution - 1)
++			<< CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
++		WREG32_SMC(ixCG_TACH_CTRL, tmp);
++	}
++
++	tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
++	tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
++	WREG32_SMC(ixCG_FDO_CTRL2, tmp);
++}
++
++static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
++{
++	int ret;
++
++	ci_thermal_initialize(adev);
++	ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
++	if (ret)
++		return ret;
++	ret = ci_thermal_enable_alert(adev, true);
++	if (ret)
++		return ret;
++	if (adev->pm.dpm.fan.ucode_fan_control) {
++		ret = ci_thermal_setup_fan_table(adev);
++		if (ret)
++			return ret;
++		ci_thermal_start_smc_fan_control(adev);
++	}
++
++	return 0;
++}
++
++static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
++{
++	if (!adev->pm.no_fan)
++		ci_fan_ctrl_set_default_mode(adev);
++}
++
++#if 0
++static int ci_read_smc_soft_register(struct amdgpu_device *adev,
++				     u16 reg_offset, u32 *value)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	return amdgpu_ci_read_smc_sram_dword(adev,
++				      pi->soft_regs_start + reg_offset,
++				      value, pi->sram_end);
++}
++#endif
++
++static int ci_write_smc_soft_register(struct amdgpu_device *adev,
++				      u16 reg_offset, u32 value)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	return amdgpu_ci_write_smc_sram_dword(adev,
++				       pi->soft_regs_start + reg_offset,
++				       value, pi->sram_end);
++}
++
++static void ci_init_fps_limits(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
++
++	if (pi->caps_fps) {
++		u16 tmp;
++
++		tmp = 45;
++		table->FpsHighT = cpu_to_be16(tmp);
++
++		tmp = 30;
++		table->FpsLowT = cpu_to_be16(tmp);
++	}
++}
++
++static int ci_update_sclk_t(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret = 0;
++	u32 low_sclk_interrupt_t = 0;
++
++	if (pi->caps_sclk_throttle_low_notification) {
++		low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
++
++		ret = amdgpu_ci_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
++					   (u8 *)&low_sclk_interrupt_t,
++					   sizeof(u32), pi->sram_end);
++
++	}
++
++	return ret;
++}
++
++static void ci_get_leakage_voltages(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u16 leakage_id, virtual_voltage_id;
++	u16 vddc, vddci;
++	int i;
++
++	pi->vddc_leakage.count = 0;
++	pi->vddci_leakage.count = 0;
++
++	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
++		for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
++			virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
++			if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
++				continue;
++			if (vddc != 0 && vddc != virtual_voltage_id) {
++				pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
++				pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
++				pi->vddc_leakage.count++;
++			}
++		}
++	} else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
++		for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
++			virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
++			if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
++										     virtual_voltage_id,
++										     leakage_id) == 0) {
++				if (vddc != 0 && vddc != virtual_voltage_id) {
++					pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
++					pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
++					pi->vddc_leakage.count++;
++				}
++				if (vddci != 0 && vddci != virtual_voltage_id) {
++					pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
++					pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
++					pi->vddci_leakage.count++;
++				}
++			}
++		}
++	}
++}
++
++static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	bool want_thermal_protection;
++	enum amdgpu_dpm_event_src dpm_event_src;
++	u32 tmp;
++
++	switch (sources) {
++	case 0:
++	default:
++		want_thermal_protection = false;
++		break;
++	case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
++		want_thermal_protection = true;
++		dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
++		break;
++	case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
++		want_thermal_protection = true;
++		dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
++		break;
++	case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
++	      (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
++		want_thermal_protection = true;
++		dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
++		break;
++	}
++
++	if (want_thermal_protection) {
++#if 0
++		/* XXX: need to figure out how to handle this properly */
++		tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
++		tmp &= DPM_EVENT_SRC_MASK;
++		tmp |= DPM_EVENT_SRC(dpm_event_src);
++		WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
++#endif
++
++		tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++		if (pi->thermal_protection)
++			tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
++		else
++			tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
++		WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++	} else {
++		tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++		tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
++		WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++	}
++}
++
++static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
++					   enum amdgpu_dpm_auto_throttle_src source,
++					   bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (enable) {
++		if (!(pi->active_auto_throttle_sources & (1 << source))) {
++			pi->active_auto_throttle_sources |= 1 << source;
++			ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
++		}
++	} else {
++		if (pi->active_auto_throttle_sources & (1 << source)) {
++			pi->active_auto_throttle_sources &= ~(1 << source);
++			ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
++		}
++	}
++}
++
++static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
++		amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
++}
++
++static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++
++	if (!pi->need_update_smu7_dpm_table)
++		return 0;
++
++	if ((!pi->sclk_dpm_key_disabled) &&
++	    (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
++		smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	if ((!pi->mclk_dpm_key_disabled) &&
++	    (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
++		smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	pi->need_update_smu7_dpm_table = 0;
++	return 0;
++}
++
++static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++
++	if (enable) {
++		if (!pi->sclk_dpm_key_disabled) {
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
++			if (smc_result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++
++		if (!pi->mclk_dpm_key_disabled) {
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
++			if (smc_result != PPSMC_Result_OK)
++				return -EINVAL;
++
++			WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
++					~MC_SEQ_CNTL_3__CAC_EN_MASK);
++
++			WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
++			WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
++			WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
++
++			udelay(10);
++
++			WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
++			WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
++			WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
++		}
++	} else {
++		if (!pi->sclk_dpm_key_disabled) {
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
++			if (smc_result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++
++		if (!pi->mclk_dpm_key_disabled) {
++			smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
++			if (smc_result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int ci_start_dpm(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++	int ret;
++	u32 tmp;
++
++	tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++	tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
++	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++
++	tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++	tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
++
++	ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
++
++	WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
++
++	smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
++	if (smc_result != PPSMC_Result_OK)
++		return -EINVAL;
++
++	ret = ci_enable_sclk_mclk_dpm(adev, true);
++	if (ret)
++		return ret;
++
++	if (!pi->pcie_dpm_key_disabled) {
++		smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++
++	if (!pi->need_update_smu7_dpm_table)
++		return 0;
++
++	if ((!pi->sclk_dpm_key_disabled) &&
++	    (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
++		smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	if ((!pi->mclk_dpm_key_disabled) &&
++	    (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
++		smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_stop_dpm(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result smc_result;
++	int ret;
++	u32 tmp;
++
++	tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++	tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
++	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++
++	tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++	tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
++
++	if (!pi->pcie_dpm_key_disabled) {
++		smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	ret = ci_enable_sclk_mclk_dpm(adev, false);
++	if (ret)
++		return ret;
++
++	smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
++	if (smc_result != PPSMC_Result_OK)
++		return -EINVAL;
++
++	return 0;
++}
++
++static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
++{
++	u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++
++	if (enable)
++		tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
++	else
++		tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
++}
++
++#if 0
++static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
++					bool ac_power)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_cac_tdp_table *cac_tdp_table =
++		adev->pm.dpm.dyn_state.cac_tdp_table;
++	u32 power_limit;
++
++	if (ac_power)
++		power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
++	else
++		power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
++
++	ci_set_power_limit(adev, power_limit);
++
++	if (pi->caps_automatic_dc_transition) {
++		if (ac_power)
++			amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
++		else
++			amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
++	}
++
++	return 0;
++}
++#endif
++
++static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++						      PPSMC_Msg msg, u32 parameter)
++{
++	WREG32(mmSMC_MSG_ARG_0, parameter);
++	return amdgpu_ci_send_msg_to_smc(adev, msg);
++}
++
++static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
++							PPSMC_Msg msg, u32 *parameter)
++{
++	PPSMC_Result smc_result;
++
++	smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
++
++	if ((smc_result == PPSMC_Result_OK) && parameter)
++		*parameter = RREG32(mmSMC_MSG_ARG_0);
++
++	return smc_result;
++}
++
++static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (!pi->sclk_dpm_key_disabled) {
++		PPSMC_Result smc_result =
++			amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (!pi->mclk_dpm_key_disabled) {
++		PPSMC_Result smc_result =
++			amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (!pi->pcie_dpm_key_disabled) {
++		PPSMC_Result smc_result =
++			amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
++		PPSMC_Result smc_result =
++			amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
++		if (smc_result != PPSMC_Result_OK)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
++				       u32 target_tdp)
++{
++	PPSMC_Result smc_result =
++		amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
++	if (smc_result != PPSMC_Result_OK)
++		return -EINVAL;
++	return 0;
++}
++
++#if 0
++static int ci_set_boot_state(struct amdgpu_device *adev)
++{
++	return ci_enable_sclk_mclk_dpm(adev, false);
++}
++#endif
++
++static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
++{
++	u32 sclk_freq;
++	PPSMC_Result smc_result =
++		amdgpu_ci_send_msg_to_smc_return_parameter(adev,
++						    PPSMC_MSG_API_GetSclkFrequency,
++						    &sclk_freq);
++	if (smc_result != PPSMC_Result_OK)
++		sclk_freq = 0;
++
++	return sclk_freq;
++}
++
++static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
++{
++	u32 mclk_freq;
++	PPSMC_Result smc_result =
++		amdgpu_ci_send_msg_to_smc_return_parameter(adev,
++						    PPSMC_MSG_API_GetMclkFrequency,
++						    &mclk_freq);
++	if (smc_result != PPSMC_Result_OK)
++		mclk_freq = 0;
++
++	return mclk_freq;
++}
++
++static void ci_dpm_start_smc(struct amdgpu_device *adev)
++{
++	int i;
++
++	amdgpu_ci_program_jump_on_start(adev);
++	amdgpu_ci_start_smc_clock(adev);
++	amdgpu_ci_start_smc(adev);
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
++			break;
++	}
++}
++
++static void ci_dpm_stop_smc(struct amdgpu_device *adev)
++{
++	amdgpu_ci_reset_smc(adev);
++	amdgpu_ci_stop_smc_clock(adev);
++}
++
++static int ci_process_firmware_header(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++	int ret;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev,
++				     SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, DpmTable),
++				     &tmp, pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->dpm_table_start = tmp;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev,
++				     SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, SoftRegisters),
++				     &tmp, pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->soft_regs_start = tmp;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev,
++				     SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, mcRegisterTable),
++				     &tmp, pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->mc_reg_table_start = tmp;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev,
++				     SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, FanTable),
++				     &tmp, pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->fan_table_start = tmp;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev,
++				     SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
++				     &tmp, pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->arb_table_start = tmp;
++
++	return 0;
++}
++
++static void ci_read_clock_registers(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	pi->clock_registers.cg_spll_func_cntl =
++		RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
++	pi->clock_registers.cg_spll_func_cntl_2 =
++		RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
++	pi->clock_registers.cg_spll_func_cntl_3 =
++		RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
++	pi->clock_registers.cg_spll_func_cntl_4 =
++		RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
++	pi->clock_registers.cg_spll_spread_spectrum =
++		RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
++	pi->clock_registers.cg_spll_spread_spectrum_2 =
++		RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
++	pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
++	pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
++	pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
++	pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
++	pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
++	pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
++	pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
++	pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
++	pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
++}
++
++static void ci_init_sclk_t(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	pi->low_sclk_interrupt_t = 0;
++}
++
++static void ci_enable_thermal_protection(struct amdgpu_device *adev,
++					 bool enable)
++{
++	u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++
++	if (enable)
++		tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
++	else
++		tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
++	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++}
++
++static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++
++	tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
++
++	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++}
++
++#if 0
++static int ci_enter_ulp_state(struct amdgpu_device *adev)
++{
++
++	WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
++
++	udelay(25000);
++
++	return 0;
++}
++
++static int ci_exit_ulp_state(struct amdgpu_device *adev)
++{
++	int i;
++
++	WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
++
++	udelay(7000);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmSMC_RESP_0) == 1)
++			break;
++		udelay(1000);
++	}
++
++	return 0;
++}
++#endif
++
++static int ci_notify_smc_display_change(struct amdgpu_device *adev,
++					bool has_display)
++{
++	PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
++
++	return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
++}
++
++static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
++				      bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (enable) {
++		if (pi->caps_sclk_ds) {
++			if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
++				return -EINVAL;
++		} else {
++			if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++	} else {
++		if (pi->caps_sclk_ds) {
++			if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static void ci_program_display_gap(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
++	u32 pre_vbi_time_in_us;
++	u32 frame_time_in_us;
++	u32 ref_clock = adev->clock.spll.reference_freq;
++	u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
++	u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
++
++	tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
++	if (adev->pm.dpm.new_active_crtc_count > 0)
++		tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
++	else
++		tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
++	WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
++
++	if (refresh_rate == 0)
++		refresh_rate = 60;
++	if (vblank_time == 0xffffffff)
++		vblank_time = 500;
++	frame_time_in_us = 1000000 / refresh_rate;
++	pre_vbi_time_in_us =
++		frame_time_in_us - 200 - vblank_time;
++	tmp = pre_vbi_time_in_us * (ref_clock / 100);
++
++	WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
++	ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
++	ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
++
++
++	ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
++
++}
++
++static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++
++	if (enable) {
++		if (pi->caps_sclk_ss_support) {
++			tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++			tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
++			WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++		}
++	} else {
++		tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
++		tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
++		WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
++
++		tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++		tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
++		WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++	}
++}
++
++static void ci_program_sstp(struct amdgpu_device *adev)
++{
++	WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
++	((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
++	 (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
++}
++
++static void ci_enable_display_gap(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
++
++	tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
++			CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
++	tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
++		(AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
++
++	WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
++}
++
++static void ci_program_vc(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++	tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
++
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
++}
++
++static void ci_clear_vc(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++	tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
++
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
++}
++
++static int ci_upload_firmware(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int i, ret;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
++			break;
++	}
++	WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
++
++	amdgpu_ci_stop_smc_clock(adev);
++	amdgpu_ci_reset_smc(adev);
++
++	ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
++
++	return ret;
++
++}
++
++static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
++				     struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
++				     struct atom_voltage_table *voltage_table)
++{
++	u32 i;
++
++	if (voltage_dependency_table == NULL)
++		return -EINVAL;
++
++	voltage_table->mask_low = 0;
++	voltage_table->phase_delay = 0;
++
++	voltage_table->count = voltage_dependency_table->count;
++	for (i = 0; i < voltage_table->count; i++) {
++		voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
++		voltage_table->entries[i].smio_low = 0;
++	}
++
++	return 0;
++}
++
++static int ci_construct_voltage_tables(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret;
++
++	if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
++		ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
++							VOLTAGE_OBJ_GPIO_LUT,
++							&pi->vddc_voltage_table);
++		if (ret)
++			return ret;
++	} else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
++		ret = ci_get_svi2_voltage_table(adev,
++						&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
++						&pi->vddc_voltage_table);
++		if (ret)
++			return ret;
++	}
++
++	if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
++		ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
++							 &pi->vddc_voltage_table);
++
++	if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
++		ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
++							VOLTAGE_OBJ_GPIO_LUT,
++							&pi->vddci_voltage_table);
++		if (ret)
++			return ret;
++	} else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
++		ret = ci_get_svi2_voltage_table(adev,
++						&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
++						&pi->vddci_voltage_table);
++		if (ret)
++			return ret;
++	}
++
++	if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
++		ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
++							 &pi->vddci_voltage_table);
++
++	if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
++		ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
++							VOLTAGE_OBJ_GPIO_LUT,
++							&pi->mvdd_voltage_table);
++		if (ret)
++			return ret;
++	} else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
++		ret = ci_get_svi2_voltage_table(adev,
++						&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
++						&pi->mvdd_voltage_table);
++		if (ret)
++			return ret;
++	}
++
++	if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
++		ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
++							 &pi->mvdd_voltage_table);
++
++	return 0;
++}
++
++static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
++					  struct atom_voltage_table_entry *voltage_table,
++					  SMU7_Discrete_VoltageLevel *smc_voltage_table)
++{
++	int ret;
++
++	ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
++					    &smc_voltage_table->StdVoltageHiSidd,
++					    &smc_voltage_table->StdVoltageLoSidd);
++
++	if (ret) {
++		smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
++		smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
++	}
++
++	smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
++	smc_voltage_table->StdVoltageHiSidd =
++		cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
++	smc_voltage_table->StdVoltageLoSidd =
++		cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
++}
++
++static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
++				      SMU7_Discrete_DpmTable *table)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	unsigned int count;
++
++	table->VddcLevelCount = pi->vddc_voltage_table.count;
++	for (count = 0; count < table->VddcLevelCount; count++) {
++		ci_populate_smc_voltage_table(adev,
++					      &pi->vddc_voltage_table.entries[count],
++					      &table->VddcLevel[count]);
++
++		if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
++			table->VddcLevel[count].Smio |=
++				pi->vddc_voltage_table.entries[count].smio_low;
++		else
++			table->VddcLevel[count].Smio = 0;
++	}
++	table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
++
++	return 0;
++}
++
++static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
++				       SMU7_Discrete_DpmTable *table)
++{
++	unsigned int count;
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	table->VddciLevelCount = pi->vddci_voltage_table.count;
++	for (count = 0; count < table->VddciLevelCount; count++) {
++		ci_populate_smc_voltage_table(adev,
++					      &pi->vddci_voltage_table.entries[count],
++					      &table->VddciLevel[count]);
++
++		if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
++			table->VddciLevel[count].Smio |=
++				pi->vddci_voltage_table.entries[count].smio_low;
++		else
++			table->VddciLevel[count].Smio = 0;
++	}
++	table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
++
++	return 0;
++}
++
++static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
++				      SMU7_Discrete_DpmTable *table)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	unsigned int count;
++
++	table->MvddLevelCount = pi->mvdd_voltage_table.count;
++	for (count = 0; count < table->MvddLevelCount; count++) {
++		ci_populate_smc_voltage_table(adev,
++					      &pi->mvdd_voltage_table.entries[count],
++					      &table->MvddLevel[count]);
++
++		if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
++			table->MvddLevel[count].Smio |=
++				pi->mvdd_voltage_table.entries[count].smio_low;
++		else
++			table->MvddLevel[count].Smio = 0;
++	}
++	table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
++
++	return 0;
++}
++
++static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
++					  SMU7_Discrete_DpmTable *table)
++{
++	int ret;
++
++	ret = ci_populate_smc_vddc_table(adev, table);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_smc_vddci_table(adev, table);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_smc_mvdd_table(adev, table);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
++				  SMU7_Discrete_VoltageLevel *voltage)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 i = 0;
++
++	if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
++		for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
++			if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
++				voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
++				break;
++			}
++		}
++
++		if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
++			return -EINVAL;
++	}
++
++	return -EINVAL;
++}
++
++static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
++					 struct atom_voltage_table_entry *voltage_table,
++					 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
++{
++	u16 v_index, idx;
++	bool voltage_found = false;
++	*std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
++	*std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
++
++	if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
++		return -EINVAL;
++
++	if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
++		for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
++			if (voltage_table->value ==
++			    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
++				voltage_found = true;
++				if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
++					idx = v_index;
++				else
++					idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
++				*std_voltage_lo_sidd =
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
++				*std_voltage_hi_sidd =
++					adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
++				break;
++			}
++		}
++
++		if (!voltage_found) {
++			for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
++				if (voltage_table->value <=
++				    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
++					voltage_found = true;
++					if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
++						idx = v_index;
++					else
++						idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
++					*std_voltage_lo_sidd =
++						adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
++					*std_voltage_hi_sidd =
++						adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
++					break;
++				}
++			}
++		}
++	}
++
++	return 0;
++}
++
++static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
++						  const struct amdgpu_phase_shedding_limits_table *limits,
++						  u32 sclk,
++						  u32 *phase_shedding)
++{
++	unsigned int i;
++
++	*phase_shedding = 1;
++
++	for (i = 0; i < limits->count; i++) {
++		if (sclk < limits->entries[i].sclk) {
++			*phase_shedding = i;
++			break;
++		}
++	}
++}
++
++static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
++						  const struct amdgpu_phase_shedding_limits_table *limits,
++						  u32 mclk,
++						  u32 *phase_shedding)
++{
++	unsigned int i;
++
++	*phase_shedding = 1;
++
++	for (i = 0; i < limits->count; i++) {
++		if (mclk < limits->entries[i].mclk) {
++			*phase_shedding = i;
++			break;
++		}
++	}
++}
++
++static int ci_init_arb_table_index(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++	int ret;
++
++	ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
++				     &tmp, pi->sram_end);
++	if (ret)
++		return ret;
++
++	tmp &= 0x00FFFFFF;
++	tmp |= MC_CG_ARB_FREQ_F1 << 24;
++
++	return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
++				       tmp, pi->sram_end);
++}
++
++static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
++					 struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
++					 u32 clock, u32 *voltage)
++{
++	u32 i = 0;
++
++	if (allowed_clock_voltage_table->count == 0)
++		return -EINVAL;
++
++	for (i = 0; i < allowed_clock_voltage_table->count; i++) {
++		if (allowed_clock_voltage_table->entries[i].clk >= clock) {
++			*voltage = allowed_clock_voltage_table->entries[i].v;
++			return 0;
++		}
++	}
++
++	*voltage = allowed_clock_voltage_table->entries[i-1].v;
++
++	return 0;
++}
++
++static u8 ci_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
++					     u32 sclk, u32 min_sclk_in_sr)
++{
++	u32 i;
++	u32 tmp;
++	u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
++		min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
++
++	if (sclk < min)
++		return 0;
++
++	for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
++		tmp = sclk / (1 << i);
++		if (tmp >= min || i == 0)
++			break;
++	}
++
++	return (u8)i;
++}
++
++static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
++{
++	return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
++}
++
++static int ci_reset_to_default(struct amdgpu_device *adev)
++{
++	return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
++		0 : -EINVAL;
++}
++
++static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
++
++	if (tmp == MC_CG_ARB_FREQ_F0)
++		return 0;
++
++	return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
++}
++
++static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
++					const u32 engine_clock,
++					const u32 memory_clock,
++					u32 *dram_timimg2)
++{
++	bool patch;
++	u32 tmp, tmp2;
++
++	tmp = RREG32(mmMC_SEQ_MISC0);
++	patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
++
++	if (patch &&
++	    ((adev->pdev->device == 0x67B0) ||
++	     (adev->pdev->device == 0x67B1))) {
++		if ((memory_clock > 100000) && (memory_clock <= 125000)) {
++			tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
++			*dram_timimg2 &= ~0x00ff0000;
++			*dram_timimg2 |= tmp2 << 16;
++		} else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
++			tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
++			*dram_timimg2 &= ~0x00ff0000;
++			*dram_timimg2 |= tmp2 << 16;
++		}
++	}
++}
++
++static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
++						u32 sclk,
++						u32 mclk,
++						SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
++{
++	u32 dram_timing;
++	u32 dram_timing2;
++	u32 burst_time;
++
++	amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
++
++	dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
++	dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
++	burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
++
++	ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
++
++	arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
++	arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
++	arb_regs->McArbBurstTime = (u8)burst_time;
++
++	return 0;
++}
++
++static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	SMU7_Discrete_MCArbDramTimingTable arb_regs;
++	u32 i, j;
++	int ret =  0;
++
++	memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
++
++	for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
++		for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
++			ret = ci_populate_memory_timing_parameters(adev,
++								   pi->dpm_table.sclk_table.dpm_levels[i].value,
++								   pi->dpm_table.mclk_table.dpm_levels[j].value,
++								   &arb_regs.entries[i][j]);
++			if (ret)
++				break;
++		}
++	}
++
++	if (ret == 0)
++		ret = amdgpu_ci_copy_bytes_to_smc(adev,
++					   pi->arb_table_start,
++					   (u8 *)&arb_regs,
++					   sizeof(SMU7_Discrete_MCArbDramTimingTable),
++					   pi->sram_end);
++
++	return ret;
++}
++
++static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (pi->need_update_smu7_dpm_table == 0)
++		return 0;
++
++	return ci_do_program_memory_timing_parameters(adev);
++}
++
++static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
++					  struct amdgpu_ps *amdgpu_boot_state)
++{
++	struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 level = 0;
++
++	for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
++		if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
++		    boot_state->performance_levels[0].sclk) {
++			pi->smc_state_table.GraphicsBootLevel = level;
++			break;
++		}
++	}
++
++	for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
++		if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
++		    boot_state->performance_levels[0].mclk) {
++			pi->smc_state_table.MemoryBootLevel = level;
++			break;
++		}
++	}
++}
++
++static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
++{
++	u32 i;
++	u32 mask_value = 0;
++
++	for (i = dpm_table->count; i > 0; i--) {
++		mask_value = mask_value << 1;
++		if (dpm_table->dpm_levels[i-1].enabled)
++			mask_value |= 0x1;
++		else
++			mask_value &= 0xFFFFFFFE;
++	}
++
++	return mask_value;
++}
++
++static void ci_populate_smc_link_level(struct amdgpu_device *adev,
++				       SMU7_Discrete_DpmTable *table)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_dpm_table *dpm_table = &pi->dpm_table;
++	u32 i;
++
++	for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
++		table->LinkLevel[i].PcieGenSpeed =
++			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
++		table->LinkLevel[i].PcieLaneCount =
++			amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
++		table->LinkLevel[i].EnabledForActivity = 1;
++		table->LinkLevel[i].DownT = cpu_to_be32(5);
++		table->LinkLevel[i].UpT = cpu_to_be32(30);
++	}
++
++	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
++	pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
++		ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
++}
++
++static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
++				     SMU7_Discrete_DpmTable *table)
++{
++	u32 count;
++	struct atom_clock_dividers dividers;
++	int ret = -EINVAL;
++
++	table->UvdLevelCount =
++		adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
++
++	for (count = 0; count < table->UvdLevelCount; count++) {
++		table->UvdLevel[count].VclkFrequency =
++			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
++		table->UvdLevel[count].DclkFrequency =
++			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
++		table->UvdLevel[count].MinVddc =
++			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
++		table->UvdLevel[count].MinVddcPhases = 1;
++
++		ret = amdgpu_atombios_get_clock_dividers(adev,
++							 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++							 table->UvdLevel[count].VclkFrequency, false, &dividers);
++		if (ret)
++			return ret;
++
++		table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
++
++		ret = amdgpu_atombios_get_clock_dividers(adev,
++							 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++							 table->UvdLevel[count].DclkFrequency, false, &dividers);
++		if (ret)
++			return ret;
++
++		table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
++
++		table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
++		table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
++		table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
++	}
++
++	return ret;
++}
++
++static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
++				     SMU7_Discrete_DpmTable *table)
++{
++	u32 count;
++	struct atom_clock_dividers dividers;
++	int ret = -EINVAL;
++
++	table->VceLevelCount =
++		adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
++
++	for (count = 0; count < table->VceLevelCount; count++) {
++		table->VceLevel[count].Frequency =
++			adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
++		table->VceLevel[count].MinVoltage =
++			(u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
++		table->VceLevel[count].MinPhases = 1;
++
++		ret = amdgpu_atombios_get_clock_dividers(adev,
++							 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++							 table->VceLevel[count].Frequency, false, &dividers);
++		if (ret)
++			return ret;
++
++		table->VceLevel[count].Divider = (u8)dividers.post_divider;
++
++		table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
++		table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
++	}
++
++	return ret;
++
++}
++
++static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
++				     SMU7_Discrete_DpmTable *table)
++{
++	u32 count;
++	struct atom_clock_dividers dividers;
++	int ret = -EINVAL;
++
++	table->AcpLevelCount = (u8)
++		(adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
++
++	for (count = 0; count < table->AcpLevelCount; count++) {
++		table->AcpLevel[count].Frequency =
++			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
++		table->AcpLevel[count].MinVoltage =
++			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
++		table->AcpLevel[count].MinPhases = 1;
++
++		ret = amdgpu_atombios_get_clock_dividers(adev,
++							 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++							 table->AcpLevel[count].Frequency, false, &dividers);
++		if (ret)
++			return ret;
++
++		table->AcpLevel[count].Divider = (u8)dividers.post_divider;
++
++		table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
++		table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
++	}
++
++	return ret;
++}
++
++static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
++				      SMU7_Discrete_DpmTable *table)
++{
++	u32 count;
++	struct atom_clock_dividers dividers;
++	int ret = -EINVAL;
++
++	table->SamuLevelCount =
++		adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
++
++	for (count = 0; count < table->SamuLevelCount; count++) {
++		table->SamuLevel[count].Frequency =
++			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
++		table->SamuLevel[count].MinVoltage =
++			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
++		table->SamuLevel[count].MinPhases = 1;
++
++		ret = amdgpu_atombios_get_clock_dividers(adev,
++							 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++							 table->SamuLevel[count].Frequency, false, &dividers);
++		if (ret)
++			return ret;
++
++		table->SamuLevel[count].Divider = (u8)dividers.post_divider;
++
++		table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
++		table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
++	}
++
++	return ret;
++}
++
++static int ci_calculate_mclk_params(struct amdgpu_device *adev,
++				    u32 memory_clock,
++				    SMU7_Discrete_MemoryLevel *mclk,
++				    bool strobe_mode,
++				    bool dll_state_on)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32  dll_cntl = pi->clock_registers.dll_cntl;
++	u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
++	u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
++	u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
++	u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
++	u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
++	u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
++	u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
++	u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
++	struct atom_mpll_param mpll_param;
++	int ret;
++
++	ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
++	if (ret)
++		return ret;
++
++	mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
++	mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
++
++	mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
++			MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
++	mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
++		(mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
++		(mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
++
++	mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
++	mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
++
++	if (adev->mc.is_gddr5) {
++		mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
++				MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
++		mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
++				(mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
++	}
++
++	if (pi->caps_mclk_ss_support) {
++		struct amdgpu_atom_ss ss;
++		u32 freq_nom;
++		u32 tmp;
++		u32 reference_clock = adev->clock.mpll.reference_freq;
++
++		if (mpll_param.qdr == 1)
++			freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
++		else
++			freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
++
++		tmp = (freq_nom / reference_clock);
++		tmp = tmp * tmp;
++		if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
++						     ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
++			u32 clks = reference_clock * 5 / ss.rate;
++			u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
++
++			mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
++			mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
++
++			mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
++			mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
++		}
++	}
++
++	mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
++	mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
++
++	if (dll_state_on)
++		mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
++			MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
++	else
++		mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
++			MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
++
++	mclk->MclkFrequency = memory_clock;
++	mclk->MpllFuncCntl = mpll_func_cntl;
++	mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
++	mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
++	mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
++	mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
++	mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
++	mclk->DllCntl = dll_cntl;
++	mclk->MpllSs1 = mpll_ss1;
++	mclk->MpllSs2 = mpll_ss2;
++
++	return 0;
++}
++
++static int ci_populate_single_memory_level(struct amdgpu_device *adev,
++					   u32 memory_clock,
++					   SMU7_Discrete_MemoryLevel *memory_level)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret;
++	bool dll_state_on;
++
++	if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
++		ret = ci_get_dependency_volt_by_clk(adev,
++						    &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
++						    memory_clock, &memory_level->MinVddc);
++		if (ret)
++			return ret;
++	}
++
++	if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
++		ret = ci_get_dependency_volt_by_clk(adev,
++						    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
++						    memory_clock, &memory_level->MinVddci);
++		if (ret)
++			return ret;
++	}
++
++	if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
++		ret = ci_get_dependency_volt_by_clk(adev,
++						    &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
++						    memory_clock, &memory_level->MinMvdd);
++		if (ret)
++			return ret;
++	}
++
++	memory_level->MinVddcPhases = 1;
++
++	if (pi->vddc_phase_shed_control)
++		ci_populate_phase_value_based_on_mclk(adev,
++						      &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
++						      memory_clock,
++						      &memory_level->MinVddcPhases);
++
++	memory_level->EnabledForThrottle = 1;
++	memory_level->EnabledForActivity = 1;
++	memory_level->UpH = 0;
++	memory_level->DownH = 100;
++	memory_level->VoltageDownH = 0;
++	memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
++
++	memory_level->StutterEnable = false;
++	memory_level->StrobeEnable = false;
++	memory_level->EdcReadEnable = false;
++	memory_level->EdcWriteEnable = false;
++	memory_level->RttEnable = false;
++
++	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
++
++	if (pi->mclk_stutter_mode_threshold &&
++	    (memory_clock <= pi->mclk_stutter_mode_threshold) &&
++	    (pi->uvd_enabled == false) &&
++	    (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
++	    (adev->pm.dpm.new_active_crtc_count <= 2))
++		memory_level->StutterEnable = true;
++
++	if (pi->mclk_strobe_mode_threshold &&
++	    (memory_clock <= pi->mclk_strobe_mode_threshold))
++		memory_level->StrobeEnable = 1;
++
++	if (adev->mc.is_gddr5) {
++		memory_level->StrobeRatio =
++			ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
++		if (pi->mclk_edc_enable_threshold &&
++		    (memory_clock > pi->mclk_edc_enable_threshold))
++			memory_level->EdcReadEnable = true;
++
++		if (pi->mclk_edc_wr_enable_threshold &&
++		    (memory_clock > pi->mclk_edc_wr_enable_threshold))
++			memory_level->EdcWriteEnable = true;
++
++		if (memory_level->StrobeEnable) {
++			if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
++			    ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
++				dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
++			else
++				dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
++		} else {
++			dll_state_on = pi->dll_default_on;
++		}
++	} else {
++		memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
++		dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
++	}
++
++	ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
++	if (ret)
++		return ret;
++
++	memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
++	memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
++	memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
++	memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
++
++	memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
++	memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
++	memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
++	memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
++	memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
++	memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
++	memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
++	memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
++	memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
++	memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
++	memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
++
++	return 0;
++}
++
++static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
++				      SMU7_Discrete_DpmTable *table)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct atom_clock_dividers dividers;
++	SMU7_Discrete_VoltageLevel voltage_level;
++	u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
++	u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
++	u32 dll_cntl = pi->clock_registers.dll_cntl;
++	u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
++	int ret;
++
++	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
++
++	if (pi->acpi_vddc)
++		table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
++	else
++		table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
++
++	table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
++
++	table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
++
++	ret = amdgpu_atombios_get_clock_dividers(adev,
++						 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
++						 table->ACPILevel.SclkFrequency, false, &dividers);
++	if (ret)
++		return ret;
++
++	table->ACPILevel.SclkDid = (u8)dividers.post_divider;
++	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
++	table->ACPILevel.DeepSleepDivId = 0;
++
++	spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
++	spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
++
++	spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
++	spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
++
++	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
++	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
++	table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
++	table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
++	table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
++	table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
++	table->ACPILevel.CcPwrDynRm = 0;
++	table->ACPILevel.CcPwrDynRm1 = 0;
++
++	table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
++	table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
++	table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
++	table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
++	table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
++	table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
++	table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
++	table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
++	table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
++	table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
++	table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
++
++	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
++	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
++
++	if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
++		if (pi->acpi_vddci)
++			table->MemoryACPILevel.MinVddci =
++				cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
++		else
++			table->MemoryACPILevel.MinVddci =
++				cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
++	}
++
++	if (ci_populate_mvdd_value(adev, 0, &voltage_level))
++		table->MemoryACPILevel.MinMvdd = 0;
++	else
++		table->MemoryACPILevel.MinMvdd =
++			cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
++
++	mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
++		MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
++	mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
++			MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
++
++	dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
++
++	table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
++	table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
++	table->MemoryACPILevel.MpllAdFuncCntl =
++		cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
++	table->MemoryACPILevel.MpllDqFuncCntl =
++		cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
++	table->MemoryACPILevel.MpllFuncCntl =
++		cpu_to_be32(pi->clock_registers.mpll_func_cntl);
++	table->MemoryACPILevel.MpllFuncCntl_1 =
++		cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
++	table->MemoryACPILevel.MpllFuncCntl_2 =
++		cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
++	table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
++	table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
++
++	table->MemoryACPILevel.EnabledForThrottle = 0;
++	table->MemoryACPILevel.EnabledForActivity = 0;
++	table->MemoryACPILevel.UpH = 0;
++	table->MemoryACPILevel.DownH = 100;
++	table->MemoryACPILevel.VoltageDownH = 0;
++	table->MemoryACPILevel.ActivityLevel =
++		cpu_to_be16((u16)pi->mclk_activity_target);
++
++	table->MemoryACPILevel.StutterEnable = false;
++	table->MemoryACPILevel.StrobeEnable = false;
++	table->MemoryACPILevel.EdcReadEnable = false;
++	table->MemoryACPILevel.EdcWriteEnable = false;
++	table->MemoryACPILevel.RttEnable = false;
++
++	return 0;
++}
++
++
++static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ulv_parm *ulv = &pi->ulv;
++
++	if (ulv->supported) {
++		if (enable)
++			return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
++				0 : -EINVAL;
++		else
++			return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
++				0 : -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ci_populate_ulv_level(struct amdgpu_device *adev,
++				 SMU7_Discrete_Ulv *state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
++
++	state->CcPwrDynRm = 0;
++	state->CcPwrDynRm1 = 0;
++
++	if (ulv_voltage == 0) {
++		pi->ulv.supported = false;
++		return 0;
++	}
++
++	if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
++		if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
++			state->VddcOffset = 0;
++		else
++			state->VddcOffset =
++				adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
++	} else {
++		if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
++			state->VddcOffsetVid = 0;
++		else
++			state->VddcOffsetVid = (u8)
++				((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
++				 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
++	}
++	state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
++
++	state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
++	state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
++	state->VddcOffset = cpu_to_be16(state->VddcOffset);
++
++	return 0;
++}
++
++static int ci_calculate_sclk_params(struct amdgpu_device *adev,
++				    u32 engine_clock,
++				    SMU7_Discrete_GraphicsLevel *sclk)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct atom_clock_dividers dividers;
++	u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
++	u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
++	u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
++	u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
++	u32 reference_clock = adev->clock.spll.reference_freq;
++	u32 reference_divider;
++	u32 fbdiv;
++	int ret;
++
++	ret = amdgpu_atombios_get_clock_dividers(adev,
++						 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
++						 engine_clock, false, &dividers);
++	if (ret)
++		return ret;
++
++	reference_divider = 1 + dividers.ref_div;
++	fbdiv = dividers.fb_div & 0x3FFFFFF;
++
++	spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
++	spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
++	spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
++
++	if (pi->caps_sclk_ss_support) {
++		struct amdgpu_atom_ss ss;
++		u32 vco_freq = engine_clock * dividers.post_div;
++
++		if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
++						     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
++			u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
++			u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
++
++			cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
++			cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
++			cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
++
++			cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
++			cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
++		}
++	}
++
++	sclk->SclkFrequency = engine_clock;
++	sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
++	sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
++	sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
++	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
++	sclk->SclkDid = (u8)dividers.post_divider;
++
++	return 0;
++}
++
++static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
++					    u32 engine_clock,
++					    u16 sclk_activity_level_t,
++					    SMU7_Discrete_GraphicsLevel *graphic_level)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret;
++
++	ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
++	if (ret)
++		return ret;
++
++	ret = ci_get_dependency_volt_by_clk(adev,
++					    &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
++					    engine_clock, &graphic_level->MinVddc);
++	if (ret)
++		return ret;
++
++	graphic_level->SclkFrequency = engine_clock;
++
++	graphic_level->Flags =  0;
++	graphic_level->MinVddcPhases = 1;
++
++	if (pi->vddc_phase_shed_control)
++		ci_populate_phase_value_based_on_sclk(adev,
++						      &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
++						      engine_clock,
++						      &graphic_level->MinVddcPhases);
++
++	graphic_level->ActivityLevel = sclk_activity_level_t;
++
++	graphic_level->CcPwrDynRm = 0;
++	graphic_level->CcPwrDynRm1 = 0;
++	graphic_level->EnabledForThrottle = 1;
++	graphic_level->UpH = 0;
++	graphic_level->DownH = 0;
++	graphic_level->VoltageDownH = 0;
++	graphic_level->PowerThrottle = 0;
++
++	if (pi->caps_sclk_ds)
++		graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(adev,
++										   engine_clock,
++										   CISLAND_MINIMUM_ENGINE_CLOCK);
++
++	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
++
++	graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
++	graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
++	graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
++	graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
++	graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
++	graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
++	graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
++	graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
++	graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
++	graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
++	graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
++	graphic_level->EnabledForActivity = 1;
++
++	return 0;
++}
++
++static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_dpm_table *dpm_table = &pi->dpm_table;
++	u32 level_array_address = pi->dpm_table_start +
++		offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
++	u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
++		SMU7_MAX_LEVELS_GRAPHICS;
++	SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
++	u32 i, ret;
++
++	memset(levels, 0, level_array_size);
++
++	for (i = 0; i < dpm_table->sclk_table.count; i++) {
++		ret = ci_populate_single_graphic_level(adev,
++						       dpm_table->sclk_table.dpm_levels[i].value,
++						       (u16)pi->activity_target[i],
++						       &pi->smc_state_table.GraphicsLevel[i]);
++		if (ret)
++			return ret;
++		if (i > 1)
++			pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
++		if (i == (dpm_table->sclk_table.count - 1))
++			pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
++				PPSMC_DISPLAY_WATERMARK_HIGH;
++	}
++
++	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
++	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
++		ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
++
++	ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
++				   (u8 *)levels, level_array_size,
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int ci_populate_ulv_state(struct amdgpu_device *adev,
++				 SMU7_Discrete_Ulv *ulv_level)
++{
++	return ci_populate_ulv_level(adev, ulv_level);
++}
++
++static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_dpm_table *dpm_table = &pi->dpm_table;
++	u32 level_array_address = pi->dpm_table_start +
++		offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
++	u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
++		SMU7_MAX_LEVELS_MEMORY;
++	SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
++	u32 i, ret;
++
++	memset(levels, 0, level_array_size);
++
++	for (i = 0; i < dpm_table->mclk_table.count; i++) {
++		if (dpm_table->mclk_table.dpm_levels[i].value == 0)
++			return -EINVAL;
++		ret = ci_populate_single_memory_level(adev,
++						      dpm_table->mclk_table.dpm_levels[i].value,
++						      &pi->smc_state_table.MemoryLevel[i]);
++		if (ret)
++			return ret;
++	}
++
++	if ((dpm_table->mclk_table.count >= 2) &&
++	    ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
++		pi->smc_state_table.MemoryLevel[1].MinVddc =
++			pi->smc_state_table.MemoryLevel[0].MinVddc;
++		pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
++			pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
++	}
++
++	pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
++
++	pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
++	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
++		ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
++
++	pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
++		PPSMC_DISPLAY_WATERMARK_HIGH;
++
++	ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
++				   (u8 *)levels, level_array_size,
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
++				      struct ci_single_dpm_table* dpm_table,
++				      u32 count)
++{
++	u32 i;
++
++	dpm_table->count = count;
++	for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
++		dpm_table->dpm_levels[i].enabled = false;
++}
++
++static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
++				      u32 index, u32 pcie_gen, u32 pcie_lanes)
++{
++	dpm_table->dpm_levels[index].value = pcie_gen;
++	dpm_table->dpm_levels[index].param1 = pcie_lanes;
++	dpm_table->dpm_levels[index].enabled = true;
++}
++
++static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
++		return -EINVAL;
++
++	if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
++		pi->pcie_gen_powersaving = pi->pcie_gen_performance;
++		pi->pcie_lane_powersaving = pi->pcie_lane_performance;
++	} else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
++		pi->pcie_gen_performance = pi->pcie_gen_powersaving;
++		pi->pcie_lane_performance = pi->pcie_lane_powersaving;
++	}
++
++	ci_reset_single_dpm_table(adev,
++				  &pi->dpm_table.pcie_speed_table,
++				  SMU7_MAX_LEVELS_LINK);
++
++	if (adev->asic_type == CHIP_BONAIRE)
++		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
++					  pi->pcie_gen_powersaving.min,
++					  pi->pcie_lane_powersaving.max);
++	else
++		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
++					  pi->pcie_gen_powersaving.min,
++					  pi->pcie_lane_powersaving.min);
++	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
++				  pi->pcie_gen_performance.min,
++				  pi->pcie_lane_performance.min);
++	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
++				  pi->pcie_gen_powersaving.min,
++				  pi->pcie_lane_powersaving.max);
++	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
++				  pi->pcie_gen_performance.min,
++				  pi->pcie_lane_performance.max);
++	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
++				  pi->pcie_gen_powersaving.max,
++				  pi->pcie_lane_powersaving.max);
++	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
++				  pi->pcie_gen_performance.max,
++				  pi->pcie_lane_performance.max);
++
++	pi->dpm_table.pcie_speed_table.count = 6;
++
++	return 0;
++}
++
++static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
++	struct amdgpu_cac_leakage_table *std_voltage_table =
++		&adev->pm.dpm.dyn_state.cac_leakage_table;
++	u32 i;
++
++	if (allowed_sclk_vddc_table == NULL)
++		return -EINVAL;
++	if (allowed_sclk_vddc_table->count < 1)
++		return -EINVAL;
++	if (allowed_mclk_table == NULL)
++		return -EINVAL;
++	if (allowed_mclk_table->count < 1)
++		return -EINVAL;
++
++	memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
++
++	ci_reset_single_dpm_table(adev,
++				  &pi->dpm_table.sclk_table,
++				  SMU7_MAX_LEVELS_GRAPHICS);
++	ci_reset_single_dpm_table(adev,
++				  &pi->dpm_table.mclk_table,
++				  SMU7_MAX_LEVELS_MEMORY);
++	ci_reset_single_dpm_table(adev,
++				  &pi->dpm_table.vddc_table,
++				  SMU7_MAX_LEVELS_VDDC);
++	ci_reset_single_dpm_table(adev,
++				  &pi->dpm_table.vddci_table,
++				  SMU7_MAX_LEVELS_VDDCI);
++	ci_reset_single_dpm_table(adev,
++				  &pi->dpm_table.mvdd_table,
++				  SMU7_MAX_LEVELS_MVDD);
++
++	pi->dpm_table.sclk_table.count = 0;
++	for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
++		if ((i == 0) ||
++		    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
++		     allowed_sclk_vddc_table->entries[i].clk)) {
++			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
++				allowed_sclk_vddc_table->entries[i].clk;
++			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
++				(i == 0) ? true : false;
++			pi->dpm_table.sclk_table.count++;
++		}
++	}
++
++	pi->dpm_table.mclk_table.count = 0;
++	for (i = 0; i < allowed_mclk_table->count; i++) {
++		if ((i == 0) ||
++		    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
++		     allowed_mclk_table->entries[i].clk)) {
++			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
++				allowed_mclk_table->entries[i].clk;
++			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
++				(i == 0) ? true : false;
++			pi->dpm_table.mclk_table.count++;
++		}
++	}
++
++	for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
++		pi->dpm_table.vddc_table.dpm_levels[i].value =
++			allowed_sclk_vddc_table->entries[i].v;
++		pi->dpm_table.vddc_table.dpm_levels[i].param1 =
++			std_voltage_table->entries[i].leakage;
++		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
++	}
++	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
++
++	allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
++	if (allowed_mclk_table) {
++		for (i = 0; i < allowed_mclk_table->count; i++) {
++			pi->dpm_table.vddci_table.dpm_levels[i].value =
++				allowed_mclk_table->entries[i].v;
++			pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
++		}
++		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
++	}
++
++	allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
++	if (allowed_mclk_table) {
++		for (i = 0; i < allowed_mclk_table->count; i++) {
++			pi->dpm_table.mvdd_table.dpm_levels[i].value =
++				allowed_mclk_table->entries[i].v;
++			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
++		}
++		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
++	}
++
++	ci_setup_default_pcie_tables(adev);
++
++	return 0;
++}
++
++static int ci_find_boot_level(struct ci_single_dpm_table *table,
++			      u32 value, u32 *boot_level)
++{
++	u32 i;
++	int ret = -EINVAL;
++
++	for(i = 0; i < table->count; i++) {
++		if (value == table->dpm_levels[i].value) {
++			*boot_level = i;
++			ret = 0;
++		}
++	}
++
++	return ret;
++}
++
++static int ci_init_smc_table(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ulv_parm *ulv = &pi->ulv;
++	struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
++	SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
++	int ret;
++
++	ret = ci_setup_default_dpm_tables(adev);
++	if (ret)
++		return ret;
++
++	if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
++		ci_populate_smc_voltage_tables(adev, table);
++
++	ci_init_fps_limits(adev);
++
++	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
++		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
++
++	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
++		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
++
++	if (adev->mc.is_gddr5)
++		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
++
++	if (ulv->supported) {
++		ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
++		if (ret)
++			return ret;
++		WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
++	}
++
++	ret = ci_populate_all_graphic_levels(adev);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_all_memory_levels(adev);
++	if (ret)
++		return ret;
++
++	ci_populate_smc_link_level(adev, table);
++
++	ret = ci_populate_smc_acpi_level(adev, table);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_smc_vce_level(adev, table);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_smc_acp_level(adev, table);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_smc_samu_level(adev, table);
++	if (ret)
++		return ret;
++
++	ret = ci_do_program_memory_timing_parameters(adev);
++	if (ret)
++		return ret;
++
++	ret = ci_populate_smc_uvd_level(adev, table);
++	if (ret)
++		return ret;
++
++	table->UvdBootLevel  = 0;
++	table->VceBootLevel  = 0;
++	table->AcpBootLevel  = 0;
++	table->SamuBootLevel  = 0;
++	table->GraphicsBootLevel  = 0;
++	table->MemoryBootLevel  = 0;
++
++	ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
++				 pi->vbios_boot_state.sclk_bootup_value,
++				 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
++
++	ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
++				 pi->vbios_boot_state.mclk_bootup_value,
++				 (u32 *)&pi->smc_state_table.MemoryBootLevel);
++
++	table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
++	table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
++	table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
++
++	ci_populate_smc_initial_state(adev, amdgpu_boot_state);
++
++	ret = ci_populate_bapm_parameters_in_dpm_table(adev);
++	if (ret)
++		return ret;
++
++	table->UVDInterval = 1;
++	table->VCEInterval = 1;
++	table->ACPInterval = 1;
++	table->SAMUInterval = 1;
++	table->GraphicsVoltageChangeEnable = 1;
++	table->GraphicsThermThrottleEnable = 1;
++	table->GraphicsInterval = 1;
++	table->VoltageInterval = 1;
++	table->ThermalInterval = 1;
++	table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
++					     CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
++	table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
++					    CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
++	table->MemoryVoltageChangeEnable = 1;
++	table->MemoryInterval = 1;
++	table->VoltageResponseTime = 0;
++	table->VddcVddciDelta = 4000;
++	table->PhaseResponseTime = 0;
++	table->MemoryThermThrottleEnable = 1;
++	table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
++	table->PCIeGenInterval = 1;
++	if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
++		table->SVI2Enable  = 1;
++	else
++		table->SVI2Enable  = 0;
++
++	table->ThermGpio = 17;
++	table->SclkStepSize = 0x4000;
++
++	table->SystemFlags = cpu_to_be32(table->SystemFlags);
++	table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
++	table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
++	table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
++	table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
++	table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
++	table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
++	table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
++	table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
++	table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
++	table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
++	table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
++	table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
++	table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
++
++	ret = amdgpu_ci_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Discrete_DpmTable, SystemFlags),
++				   (u8 *)&table->SystemFlags,
++				   sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
++				      struct ci_single_dpm_table *dpm_table,
++				      u32 low_limit, u32 high_limit)
++{
++	u32 i;
++
++	for (i = 0; i < dpm_table->count; i++) {
++		if ((dpm_table->dpm_levels[i].value < low_limit) ||
++		    (dpm_table->dpm_levels[i].value > high_limit))
++			dpm_table->dpm_levels[i].enabled = false;
++		else
++			dpm_table->dpm_levels[i].enabled = true;
++	}
++}
++
++static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
++				    u32 speed_low, u32 lanes_low,
++				    u32 speed_high, u32 lanes_high)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
++	u32 i, j;
++
++	for (i = 0; i < pcie_table->count; i++) {
++		if ((pcie_table->dpm_levels[i].value < speed_low) ||
++		    (pcie_table->dpm_levels[i].param1 < lanes_low) ||
++		    (pcie_table->dpm_levels[i].value > speed_high) ||
++		    (pcie_table->dpm_levels[i].param1 > lanes_high))
++			pcie_table->dpm_levels[i].enabled = false;
++		else
++			pcie_table->dpm_levels[i].enabled = true;
++	}
++
++	for (i = 0; i < pcie_table->count; i++) {
++		if (pcie_table->dpm_levels[i].enabled) {
++			for (j = i + 1; j < pcie_table->count; j++) {
++				if (pcie_table->dpm_levels[j].enabled) {
++					if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
++					    (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
++						pcie_table->dpm_levels[j].enabled = false;
++				}
++			}
++		}
++	}
++}
++
++static int ci_trim_dpm_states(struct amdgpu_device *adev,
++			      struct amdgpu_ps *amdgpu_state)
++{
++	struct ci_ps *state = ci_get_ps(amdgpu_state);
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 high_limit_count;
++
++	if (state->performance_level_count < 1)
++		return -EINVAL;
++
++	if (state->performance_level_count == 1)
++		high_limit_count = 0;
++	else
++		high_limit_count = 1;
++
++	ci_trim_single_dpm_states(adev,
++				  &pi->dpm_table.sclk_table,
++				  state->performance_levels[0].sclk,
++				  state->performance_levels[high_limit_count].sclk);
++
++	ci_trim_single_dpm_states(adev,
++				  &pi->dpm_table.mclk_table,
++				  state->performance_levels[0].mclk,
++				  state->performance_levels[high_limit_count].mclk);
++
++	ci_trim_pcie_dpm_states(adev,
++				state->performance_levels[0].pcie_gen,
++				state->performance_levels[0].pcie_lane,
++				state->performance_levels[high_limit_count].pcie_gen,
++				state->performance_levels[high_limit_count].pcie_lane);
++
++	return 0;
++}
++
++static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
++{
++	struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
++	struct amdgpu_clock_voltage_dependency_table *vddc_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	u32 requested_voltage = 0;
++	u32 i;
++
++	if (disp_voltage_table == NULL)
++		return -EINVAL;
++	if (!disp_voltage_table->count)
++		return -EINVAL;
++
++	for (i = 0; i < disp_voltage_table->count; i++) {
++		if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
++			requested_voltage = disp_voltage_table->entries[i].v;
++	}
++
++	for (i = 0; i < vddc_table->count; i++) {
++		if (requested_voltage <= vddc_table->entries[i].v) {
++			requested_voltage = vddc_table->entries[i].v;
++			return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++								  PPSMC_MSG_VddC_Request,
++								  requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
++				0 : -EINVAL;
++		}
++	}
++
++	return -EINVAL;
++}
++
++static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	PPSMC_Result result;
++
++	ci_apply_disp_minimum_voltage_request(adev);
++
++	if (!pi->sclk_dpm_key_disabled) {
++		if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
++			result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++								   PPSMC_MSG_SCLKDPM_SetEnabledMask,
++								   pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
++			if (result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++	}
++
++	if (!pi->mclk_dpm_key_disabled) {
++		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
++			result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++								   PPSMC_MSG_MCLKDPM_SetEnabledMask,
++								   pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
++			if (result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++	}
++
++#if 0
++	if (!pi->pcie_dpm_key_disabled) {
++		if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
++			result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++								   PPSMC_MSG_PCIeDPM_SetEnabledMask,
++								   pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
++			if (result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++	}
++#endif
++
++	return 0;
++}
++
++static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
++						   struct amdgpu_ps *amdgpu_state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ps *state = ci_get_ps(amdgpu_state);
++	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
++	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
++	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
++	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
++	u32 i;
++
++	pi->need_update_smu7_dpm_table = 0;
++
++	for (i = 0; i < sclk_table->count; i++) {
++		if (sclk == sclk_table->dpm_levels[i].value)
++			break;
++	}
++
++	if (i >= sclk_table->count) {
++		pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
++	} else {
++		/* XXX check display min clock requirements */
++		if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
++			pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
++	}
++
++	for (i = 0; i < mclk_table->count; i++) {
++		if (mclk == mclk_table->dpm_levels[i].value)
++			break;
++	}
++
++	if (i >= mclk_table->count)
++		pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
++
++	if (adev->pm.dpm.current_active_crtc_count !=
++	    adev->pm.dpm.new_active_crtc_count)
++		pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
++}
++
++static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
++						       struct amdgpu_ps *amdgpu_state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ps *state = ci_get_ps(amdgpu_state);
++	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
++	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
++	struct ci_dpm_table *dpm_table = &pi->dpm_table;
++	int ret;
++
++	if (!pi->need_update_smu7_dpm_table)
++		return 0;
++
++	if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
++		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
++
++	if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
++		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
++
++	if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
++		ret = ci_populate_all_graphic_levels(adev);
++		if (ret)
++			return ret;
++	}
++
++	if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
++		ret = ci_populate_all_memory_levels(adev);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct amdgpu_clock_and_voltage_limits *max_limits;
++	int i;
++
++	if (adev->pm.dpm.ac_power)
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	else
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
++
++	if (enable) {
++		pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
++
++		for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
++			if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
++				pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
++
++				if (!pi->caps_uvd_dpm)
++					break;
++			}
++		}
++
++		amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++						  PPSMC_MSG_UVDDPM_SetEnabledMask,
++						  pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
++
++		if (pi->last_mclk_dpm_enable_mask & 0x1) {
++			pi->uvd_enabled = true;
++			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
++			amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++							  PPSMC_MSG_MCLKDPM_SetEnabledMask,
++							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
++		}
++	} else {
++		if (pi->last_mclk_dpm_enable_mask & 0x1) {
++			pi->uvd_enabled = false;
++			pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
++			amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++							  PPSMC_MSG_MCLKDPM_SetEnabledMask,
++							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
++		}
++	}
++
++	return (amdgpu_ci_send_msg_to_smc(adev, enable ?
++				   PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
++		0 : -EINVAL;
++}
++
++static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct amdgpu_clock_and_voltage_limits *max_limits;
++	int i;
++
++	if (adev->pm.dpm.ac_power)
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	else
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
++
++	if (enable) {
++		pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
++		for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
++			if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
++				pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
++
++				if (!pi->caps_vce_dpm)
++					break;
++			}
++		}
++
++		amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++						  PPSMC_MSG_VCEDPM_SetEnabledMask,
++						  pi->dpm_level_enable_mask.vce_dpm_enable_mask);
++	}
++
++	return (amdgpu_ci_send_msg_to_smc(adev, enable ?
++				   PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
++		0 : -EINVAL;
++}
++
++#if 0
++static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct amdgpu_clock_and_voltage_limits *max_limits;
++	int i;
++
++	if (adev->pm.dpm.ac_power)
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	else
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
++
++	if (enable) {
++		pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
++		for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
++			if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
++				pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
++
++				if (!pi->caps_samu_dpm)
++					break;
++			}
++		}
++
++		amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++						  PPSMC_MSG_SAMUDPM_SetEnabledMask,
++						  pi->dpm_level_enable_mask.samu_dpm_enable_mask);
++	}
++	return (amdgpu_ci_send_msg_to_smc(adev, enable ?
++				   PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
++		0 : -EINVAL;
++}
++
++static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	const struct amdgpu_clock_and_voltage_limits *max_limits;
++	int i;
++
++	if (adev->pm.dpm.ac_power)
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	else
++		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
++
++	if (enable) {
++		pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
++		for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
++			if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
++				pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
++
++				if (!pi->caps_acp_dpm)
++					break;
++			}
++		}
++
++		amdgpu_ci_send_msg_to_smc_with_parameter(adev,
++						  PPSMC_MSG_ACPDPM_SetEnabledMask,
++						  pi->dpm_level_enable_mask.acp_dpm_enable_mask);
++	}
++
++	return (amdgpu_ci_send_msg_to_smc(adev, enable ?
++				   PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
++		0 : -EINVAL;
++}
++#endif
++
++static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++
++	if (!gate) {
++		if (pi->caps_uvd_dpm ||
++		    (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
++			pi->smc_state_table.UvdBootLevel = 0;
++		else
++			pi->smc_state_table.UvdBootLevel =
++				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
++
++		tmp = RREG32_SMC(ixDPM_TABLE_475);
++		tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
++		tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
++		WREG32_SMC(ixDPM_TABLE_475, tmp);
++	}
++
++	return ci_enable_uvd_dpm(adev, !gate);
++}
++
++static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
++{
++	u8 i;
++	u32 min_evclk = 30000; /* ??? */
++	struct amdgpu_vce_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++
++	for (i = 0; i < table->count; i++) {
++		if (table->entries[i].evclk >= min_evclk)
++			return i;
++	}
++
++	return table->count - 1;
++}
++
++static int ci_update_vce_dpm(struct amdgpu_device *adev,
++			     struct amdgpu_ps *amdgpu_new_state,
++			     struct amdgpu_ps *amdgpu_current_state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret = 0;
++	u32 tmp;
++
++	if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
++		if (amdgpu_new_state->evclk) {
++			/* turn the clocks on when encoding */
++			ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
++							    AMDGPU_CG_STATE_UNGATE);
++			if (ret)
++				return ret;
++
++			pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
++			tmp = RREG32_SMC(ixDPM_TABLE_475);
++			tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
++			tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
++			WREG32_SMC(ixDPM_TABLE_475, tmp);
++
++			ret = ci_enable_vce_dpm(adev, true);
++		} else {
++			/* turn the clocks off when not encoding */
++			ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
++							    AMDGPU_CG_STATE_GATE);
++			if (ret)
++				return ret;
++
++			ret = ci_enable_vce_dpm(adev, false);
++		}
++	}
++	return ret;
++}
++
++#if 0
++static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
++{
++	return ci_enable_samu_dpm(adev, gate);
++}
++
++static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp;
++
++	if (!gate) {
++		pi->smc_state_table.AcpBootLevel = 0;
++
++		tmp = RREG32_SMC(ixDPM_TABLE_475);
++		tmp &= ~AcpBootLevel_MASK;
++		tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
++		WREG32_SMC(ixDPM_TABLE_475, tmp);
++	}
++
++	return ci_enable_acp_dpm(adev, !gate);
++}
++#endif
++
++static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
++					     struct amdgpu_ps *amdgpu_state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret;
++
++	ret = ci_trim_dpm_states(adev, amdgpu_state);
++	if (ret)
++		return ret;
++
++	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
++		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
++	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
++		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
++	pi->last_mclk_dpm_enable_mask =
++		pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
++	if (pi->uvd_enabled) {
++		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
++			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
++	}
++	pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
++		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
++
++	return 0;
++}
++
++static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
++				       u32 level_mask)
++{
++	u32 level = 0;
++
++	while ((level_mask & (1 << level)) == 0)
++		level++;
++
++	return level;
++}
++
++
++static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
++					  enum amdgpu_dpm_forced_level level)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 tmp, levels, i;
++	int ret;
++
++	if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
++		if ((!pi->pcie_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
++			levels = 0;
++			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
++			while (tmp >>= 1)
++				levels++;
++			if (levels) {
++				ret = ci_dpm_force_state_pcie(adev, level);
++				if (ret)
++					return ret;
++				for (i = 0; i < adev->usec_timeout; i++) {
++					tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
++					TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
++					TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
++					if (tmp == levels)
++						break;
++					udelay(1);
++				}
++			}
++		}
++		if ((!pi->sclk_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
++			levels = 0;
++			tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
++			while (tmp >>= 1)
++				levels++;
++			if (levels) {
++				ret = ci_dpm_force_state_sclk(adev, levels);
++				if (ret)
++					return ret;
++				for (i = 0; i < adev->usec_timeout; i++) {
++					tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
++					TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
++					TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
++					if (tmp == levels)
++						break;
++					udelay(1);
++				}
++			}
++		}
++		if ((!pi->mclk_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
++			levels = 0;
++			tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
++			while (tmp >>= 1)
++				levels++;
++			if (levels) {
++				ret = ci_dpm_force_state_mclk(adev, levels);
++				if (ret)
++					return ret;
++				for (i = 0; i < adev->usec_timeout; i++) {
++					tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
++					TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
++					TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
++					if (tmp == levels)
++						break;
++					udelay(1);
++				}
++			}
++		}
++		if ((!pi->pcie_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
++			levels = 0;
++			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
++			while (tmp >>= 1)
++				levels++;
++			if (levels) {
++				ret = ci_dpm_force_state_pcie(adev, level);
++				if (ret)
++					return ret;
++				for (i = 0; i < adev->usec_timeout; i++) {
++					tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
++					TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
++					TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
++					if (tmp == levels)
++						break;
++					udelay(1);
++				}
++			}
++		}
++	} else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
++		if ((!pi->sclk_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
++			levels = ci_get_lowest_enabled_level(adev,
++							     pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
++			ret = ci_dpm_force_state_sclk(adev, levels);
++			if (ret)
++				return ret;
++			for (i = 0; i < adev->usec_timeout; i++) {
++				tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
++				TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
++				TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
++				if (tmp == levels)
++					break;
++				udelay(1);
++			}
++		}
++		if ((!pi->mclk_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
++			levels = ci_get_lowest_enabled_level(adev,
++							     pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
++			ret = ci_dpm_force_state_mclk(adev, levels);
++			if (ret)
++				return ret;
++			for (i = 0; i < adev->usec_timeout; i++) {
++				tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
++				TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
++				TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
++				if (tmp == levels)
++					break;
++				udelay(1);
++			}
++		}
++		if ((!pi->pcie_dpm_key_disabled) &&
++		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
++			levels = ci_get_lowest_enabled_level(adev,
++							     pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
++			ret = ci_dpm_force_state_pcie(adev, levels);
++			if (ret)
++				return ret;
++			for (i = 0; i < adev->usec_timeout; i++) {
++				tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
++				TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
++				TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
++				if (tmp == levels)
++					break;
++				udelay(1);
++			}
++		}
++	} else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
++		if (!pi->pcie_dpm_key_disabled) {
++			PPSMC_Result smc_result;
++
++			smc_result = amdgpu_ci_send_msg_to_smc(adev,
++							       PPSMC_MSG_PCIeDPM_UnForceLevel);
++			if (smc_result != PPSMC_Result_OK)
++				return -EINVAL;
++		}
++		ret = ci_upload_dpm_level_enable_mask(adev);
++		if (ret)
++			return ret;
++	}
++
++	adev->pm.dpm.forced_level = level;
++
++	return 0;
++}
++
++static int ci_set_mc_special_registers(struct amdgpu_device *adev,
++				       struct ci_mc_reg_table *table)
++{
++	u8 i, j, k;
++	u32 temp_reg;
++
++	for (i = 0, j = table->last; i < table->last; i++) {
++		if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++			return -EINVAL;
++		switch(table->mc_reg_address[i].s1) {
++		case mmMC_SEQ_MISC1:
++			temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
++			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
++			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
++			for (k = 0; k < table->num_entries; k++) {
++				table->mc_reg_table_entry[k].mc_data[j] =
++					((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
++			}
++			j++;
++			if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++				return -EINVAL;
++
++			temp_reg = RREG32(mmMC_PMG_CMD_MRS);
++			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
++			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
++			for (k = 0; k < table->num_entries; k++) {
++				table->mc_reg_table_entry[k].mc_data[j] =
++					(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
++				if (!adev->mc.is_gddr5)
++					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
++			}
++			j++;
++			if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++				return -EINVAL;
++
++			if (!adev->mc.is_gddr5) {
++				table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
++				table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
++				for (k = 0; k < table->num_entries; k++) {
++					table->mc_reg_table_entry[k].mc_data[j] =
++						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
++				}
++				j++;
++				if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++					return -EINVAL;
++			}
++			break;
++		case mmMC_SEQ_RESERVE_M:
++			temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
++			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
++			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
++			for (k = 0; k < table->num_entries; k++) {
++				table->mc_reg_table_entry[k].mc_data[j] =
++					(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
++			}
++			j++;
++			if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++				return -EINVAL;
++			break;
++		default:
++			break;
++		}
++
++	}
++
++	table->last = j;
++
++	return 0;
++}
++
++static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
++{
++	bool result = true;
++
++	switch(in_reg) {
++	case mmMC_SEQ_RAS_TIMING:
++		*out_reg = mmMC_SEQ_RAS_TIMING_LP;
++		break;
++	case mmMC_SEQ_DLL_STBY:
++		*out_reg = mmMC_SEQ_DLL_STBY_LP;
++		break;
++	case mmMC_SEQ_G5PDX_CMD0:
++		*out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
++		break;
++	case mmMC_SEQ_G5PDX_CMD1:
++		*out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
++		break;
++	case mmMC_SEQ_G5PDX_CTRL:
++		*out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
++		break;
++	case mmMC_SEQ_CAS_TIMING:
++		*out_reg = mmMC_SEQ_CAS_TIMING_LP;
++	    break;
++	case mmMC_SEQ_MISC_TIMING:
++		*out_reg = mmMC_SEQ_MISC_TIMING_LP;
++		break;
++	case mmMC_SEQ_MISC_TIMING2:
++		*out_reg = mmMC_SEQ_MISC_TIMING2_LP;
++		break;
++	case mmMC_SEQ_PMG_DVS_CMD:
++		*out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
++		break;
++	case mmMC_SEQ_PMG_DVS_CTL:
++		*out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
++		break;
++	case mmMC_SEQ_RD_CTL_D0:
++		*out_reg = mmMC_SEQ_RD_CTL_D0_LP;
++		break;
++	case mmMC_SEQ_RD_CTL_D1:
++		*out_reg = mmMC_SEQ_RD_CTL_D1_LP;
++		break;
++	case mmMC_SEQ_WR_CTL_D0:
++		*out_reg = mmMC_SEQ_WR_CTL_D0_LP;
++		break;
++	case mmMC_SEQ_WR_CTL_D1:
++		*out_reg = mmMC_SEQ_WR_CTL_D1_LP;
++		break;
++	case mmMC_PMG_CMD_EMRS:
++		*out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
++		break;
++	case mmMC_PMG_CMD_MRS:
++		*out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
++		break;
++	case mmMC_PMG_CMD_MRS1:
++		*out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
++		break;
++	case mmMC_SEQ_PMG_TIMING:
++		*out_reg = mmMC_SEQ_PMG_TIMING_LP;
++		break;
++	case mmMC_PMG_CMD_MRS2:
++		*out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
++		break;
++	case mmMC_SEQ_WR_CTL_2:
++		*out_reg = mmMC_SEQ_WR_CTL_2_LP;
++		break;
++	default:
++		result = false;
++		break;
++	}
++
++	return result;
++}
++
++static void ci_set_valid_flag(struct ci_mc_reg_table *table)
++{
++	u8 i, j;
++
++	for (i = 0; i < table->last; i++) {
++		for (j = 1; j < table->num_entries; j++) {
++			if (table->mc_reg_table_entry[j-1].mc_data[i] !=
++			    table->mc_reg_table_entry[j].mc_data[i]) {
++				table->valid_flag |= 1 << i;
++				break;
++			}
++		}
++	}
++}
++
++static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
++{
++	u32 i;
++	u16 address;
++
++	for (i = 0; i < table->last; i++) {
++		table->mc_reg_address[i].s0 =
++			ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
++			address : table->mc_reg_address[i].s1;
++	}
++}
++
++static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
++				      struct ci_mc_reg_table *ci_table)
++{
++	u8 i, j;
++
++	if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++		return -EINVAL;
++	if (table->num_entries > MAX_AC_TIMING_ENTRIES)
++		return -EINVAL;
++
++	for (i = 0; i < table->last; i++)
++		ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
++
++	ci_table->last = table->last;
++
++	for (i = 0; i < table->num_entries; i++) {
++		ci_table->mc_reg_table_entry[i].mclk_max =
++			table->mc_reg_table_entry[i].mclk_max;
++		for (j = 0; j < table->last; j++)
++			ci_table->mc_reg_table_entry[i].mc_data[j] =
++				table->mc_reg_table_entry[i].mc_data[j];
++	}
++	ci_table->num_entries = table->num_entries;
++
++	return 0;
++}
++
++static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
++				       struct ci_mc_reg_table *table)
++{
++	u8 i, k;
++	u32 tmp;
++	bool patch;
++
++	tmp = RREG32(mmMC_SEQ_MISC0);
++	patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
++
++	if (patch &&
++	    ((adev->pdev->device == 0x67B0) ||
++	     (adev->pdev->device == 0x67B1))) {
++		for (i = 0; i < table->last; i++) {
++			if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++				return -EINVAL;
++			switch (table->mc_reg_address[i].s1) {
++			case mmMC_SEQ_MISC1:
++				for (k = 0; k < table->num_entries; k++) {
++					if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
++					    (table->mc_reg_table_entry[k].mclk_max == 137500))
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
++							0x00000007;
++				}
++				break;
++			case mmMC_SEQ_WR_CTL_D0:
++				for (k = 0; k < table->num_entries; k++) {
++					if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
++					    (table->mc_reg_table_entry[k].mclk_max == 137500))
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
++							0x0000D0DD;
++				}
++				break;
++			case mmMC_SEQ_WR_CTL_D1:
++				for (k = 0; k < table->num_entries; k++) {
++					if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
++					    (table->mc_reg_table_entry[k].mclk_max == 137500))
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
++							0x0000D0DD;
++				}
++				break;
++			case mmMC_SEQ_WR_CTL_2:
++				for (k = 0; k < table->num_entries; k++) {
++					if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
++					    (table->mc_reg_table_entry[k].mclk_max == 137500))
++						table->mc_reg_table_entry[k].mc_data[i] = 0;
++				}
++				break;
++			case mmMC_SEQ_CAS_TIMING:
++				for (k = 0; k < table->num_entries; k++) {
++					if (table->mc_reg_table_entry[k].mclk_max == 125000)
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
++							0x000C0140;
++					else if (table->mc_reg_table_entry[k].mclk_max == 137500)
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
++							0x000C0150;
++				}
++				break;
++			case mmMC_SEQ_MISC_TIMING:
++				for (k = 0; k < table->num_entries; k++) {
++					if (table->mc_reg_table_entry[k].mclk_max == 125000)
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
++							0x00000030;
++					else if (table->mc_reg_table_entry[k].mclk_max == 137500)
++						table->mc_reg_table_entry[k].mc_data[i] =
++							(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
++							0x00000035;
++				}
++				break;
++			default:
++				break;
++			}
++		}
++
++		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
++		tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
++		tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
++		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
++		WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
++	}
++
++	return 0;
++}
++
++static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct atom_mc_reg_table *table;
++	struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
++	u8 module_index = ci_get_memory_module_index(adev);
++	int ret;
++
++	table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
++	if (!table)
++		return -ENOMEM;
++
++	WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
++	WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
++	WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
++	WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
++	WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
++	WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
++	WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
++	WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
++	WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
++	WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
++	WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
++	WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
++	WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
++	WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
++	WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
++	WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
++	WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
++	WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
++	WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
++	WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
++
++	ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
++	if (ret)
++		goto init_mc_done;
++
++	ret = ci_copy_vbios_mc_reg_table(table, ci_table);
++	if (ret)
++		goto init_mc_done;
++
++	ci_set_s0_mc_reg_index(ci_table);
++
++	ret = ci_register_patching_mc_seq(adev, ci_table);
++	if (ret)
++		goto init_mc_done;
++
++	ret = ci_set_mc_special_registers(adev, ci_table);
++	if (ret)
++		goto init_mc_done;
++
++	ci_set_valid_flag(ci_table);
++
++init_mc_done:
++	kfree(table);
++
++	return ret;
++}
++
++static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
++					SMU7_Discrete_MCRegisters *mc_reg_table)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 i, j;
++
++	for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
++		if (pi->mc_reg_table.valid_flag & (1 << j)) {
++			if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
++				return -EINVAL;
++			mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
++			mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
++			i++;
++		}
++	}
++
++	mc_reg_table->last = (u8)i;
++
++	return 0;
++}
++
++static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
++				    SMU7_Discrete_MCRegisterSet *data,
++				    u32 num_entries, u32 valid_flag)
++{
++	u32 i, j;
++
++	for (i = 0, j = 0; j < num_entries; j++) {
++		if (valid_flag & (1 << j)) {
++			data->value[i] = cpu_to_be32(entry->mc_data[j]);
++			i++;
++		}
++	}
++}
++
++static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
++						 const u32 memory_clock,
++						 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 i = 0;
++
++	for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
++		if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
++			break;
++	}
++
++	if ((i == pi->mc_reg_table.num_entries) && (i > 0))
++		--i;
++
++	ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
++				mc_reg_table_data, pi->mc_reg_table.last,
++				pi->mc_reg_table.valid_flag);
++}
++
++static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
++					   SMU7_Discrete_MCRegisters *mc_reg_table)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	u32 i;
++
++	for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
++		ci_convert_mc_reg_table_entry_to_smc(adev,
++						     pi->dpm_table.mclk_table.dpm_levels[i].value,
++						     &mc_reg_table->data[i]);
++}
++
++static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	int ret;
++
++	memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
++
++	ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
++	if (ret)
++		return ret;
++	ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
++
++	return amdgpu_ci_copy_bytes_to_smc(adev,
++				    pi->mc_reg_table_start,
++				    (u8 *)&pi->smc_mc_reg_table,
++				    sizeof(SMU7_Discrete_MCRegisters),
++				    pi->sram_end);
++}
++
++static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
++		return 0;
++
++	memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
++
++	ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
++
++	return amdgpu_ci_copy_bytes_to_smc(adev,
++				    pi->mc_reg_table_start +
++				    offsetof(SMU7_Discrete_MCRegisters, data[0]),
++				    (u8 *)&pi->smc_mc_reg_table.data[0],
++				    sizeof(SMU7_Discrete_MCRegisterSet) *
++				    pi->dpm_table.mclk_table.count,
++				    pi->sram_end);
++}
++
++static void ci_enable_voltage_control(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++
++	tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
++	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++}
++
++static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
++						      struct amdgpu_ps *amdgpu_state)
++{
++	struct ci_ps *state = ci_get_ps(amdgpu_state);
++	int i;
++	u16 pcie_speed, max_speed = 0;
++
++	for (i = 0; i < state->performance_level_count; i++) {
++		pcie_speed = state->performance_levels[i].pcie_gen;
++		if (max_speed < pcie_speed)
++			max_speed = pcie_speed;
++	}
++
++	return max_speed;
++}
++
++static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
++{
++	u32 speed_cntl = 0;
++
++	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
++		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
++	speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
++
++	return (u16)speed_cntl;
++}
++
++static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
++{
++	u32 link_width = 0;
++
++	link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
++		PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
++	link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
++
++	switch (link_width) {
++	case 1:
++		return 1;
++	case 2:
++		return 2;
++	case 3:
++		return 4;
++	case 4:
++		return 8;
++	case 0:
++	case 6:
++	default:
++		return 16;
++	}
++}
++
++static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
++							     struct amdgpu_ps *amdgpu_new_state,
++							     struct amdgpu_ps *amdgpu_current_state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	enum amdgpu_pcie_gen target_link_speed =
++		ci_get_maximum_link_speed(adev, amdgpu_new_state);
++	enum amdgpu_pcie_gen current_link_speed;
++
++	if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
++		current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
++	else
++		current_link_speed = pi->force_pcie_gen;
++
++	pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
++	pi->pspp_notify_required = false;
++	if (target_link_speed > current_link_speed) {
++		switch (target_link_speed) {
++#ifdef CONFIG_ACPI
++		case AMDGPU_PCIE_GEN3:
++			if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
++				break;
++			pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
++			if (current_link_speed == AMDGPU_PCIE_GEN2)
++				break;
++		case AMDGPU_PCIE_GEN2:
++			if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
++				break;
++#endif
++		default:
++			pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
++			break;
++		}
++	} else {
++		if (target_link_speed < current_link_speed)
++			pi->pspp_notify_required = true;
++	}
++}
++
++static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
++							   struct amdgpu_ps *amdgpu_new_state,
++							   struct amdgpu_ps *amdgpu_current_state)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	enum amdgpu_pcie_gen target_link_speed =
++		ci_get_maximum_link_speed(adev, amdgpu_new_state);
++	u8 request;
++
++	if (pi->pspp_notify_required) {
++		if (target_link_speed == AMDGPU_PCIE_GEN3)
++			request = PCIE_PERF_REQ_PECI_GEN3;
++		else if (target_link_speed == AMDGPU_PCIE_GEN2)
++			request = PCIE_PERF_REQ_PECI_GEN2;
++		else
++			request = PCIE_PERF_REQ_PECI_GEN1;
++
++		if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
++		    (ci_get_current_pcie_speed(adev) > 0))
++			return;
++
++#ifdef CONFIG_ACPI
++		amdgpu_acpi_pcie_performance_request(adev, request, false);
++#endif
++	}
++}
++
++static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
++	struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
++		&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
++
++	if (allowed_sclk_vddc_table == NULL)
++		return -EINVAL;
++	if (allowed_sclk_vddc_table->count < 1)
++		return -EINVAL;
++	if (allowed_mclk_vddc_table == NULL)
++		return -EINVAL;
++	if (allowed_mclk_vddc_table->count < 1)
++		return -EINVAL;
++	if (allowed_mclk_vddci_table == NULL)
++		return -EINVAL;
++	if (allowed_mclk_vddci_table->count < 1)
++		return -EINVAL;
++
++	pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
++	pi->max_vddc_in_pp_table =
++		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
++
++	pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
++	pi->max_vddci_in_pp_table =
++		allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
++
++	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
++		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
++	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
++		allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
++	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
++		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
++	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
++		allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
++
++	return 0;
++}
++
++static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
++	u32 leakage_index;
++
++	for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
++		if (leakage_table->leakage_id[leakage_index] == *vddc) {
++			*vddc = leakage_table->actual_voltage[leakage_index];
++			break;
++		}
++	}
++}
++
++static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
++	u32 leakage_index;
++
++	for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
++		if (leakage_table->leakage_id[leakage_index] == *vddci) {
++			*vddci = leakage_table->actual_voltage[leakage_index];
++			break;
++		}
++	}
++}
++
++static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
++								      struct amdgpu_clock_voltage_dependency_table *table)
++{
++	u32 i;
++
++	if (table) {
++		for (i = 0; i < table->count; i++)
++			ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
++	}
++}
++
++static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
++								       struct amdgpu_clock_voltage_dependency_table *table)
++{
++	u32 i;
++
++	if (table) {
++		for (i = 0; i < table->count; i++)
++			ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
++	}
++}
++
++static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
++									  struct amdgpu_vce_clock_voltage_dependency_table *table)
++{
++	u32 i;
++
++	if (table) {
++		for (i = 0; i < table->count; i++)
++			ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
++	}
++}
++
++static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
++									  struct amdgpu_uvd_clock_voltage_dependency_table *table)
++{
++	u32 i;
++
++	if (table) {
++		for (i = 0; i < table->count; i++)
++			ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
++	}
++}
++
++static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
++								   struct amdgpu_phase_shedding_limits_table *table)
++{
++	u32 i;
++
++	if (table) {
++		for (i = 0; i < table->count; i++)
++			ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
++	}
++}
++
++static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
++							    struct amdgpu_clock_and_voltage_limits *table)
++{
++	if (table) {
++		ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
++		ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
++	}
++}
++
++static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
++							 struct amdgpu_cac_leakage_table *table)
++{
++	u32 i;
++
++	if (table) {
++		for (i = 0; i < table->count; i++)
++			ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
++	}
++}
++
++static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
++{
++
++	ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								  &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
++	ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								  &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
++	ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								  &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
++	ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
++								   &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
++	ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								      &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
++	ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								      &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
++	ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								  &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
++	ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
++								  &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
++	ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
++							       &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
++	ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
++							&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
++	ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
++							&adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
++	ci_patch_cac_leakage_table_with_vddc_leakage(adev,
++						     &adev->pm.dpm.dyn_state.cac_leakage_table);
++
++}
++
++static void ci_update_current_ps(struct amdgpu_device *adev,
++				 struct amdgpu_ps *rps)
++{
++	struct ci_ps *new_ps = ci_get_ps(rps);
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	pi->current_rps = *rps;
++	pi->current_ps = *new_ps;
++	pi->current_rps.ps_priv = &pi->current_ps;
++}
++
++static void ci_update_requested_ps(struct amdgpu_device *adev,
++				   struct amdgpu_ps *rps)
++{
++	struct ci_ps *new_ps = ci_get_ps(rps);
++	struct ci_power_info *pi = ci_get_pi(adev);
++
++	pi->requested_rps = *rps;
++	pi->requested_ps = *new_ps;
++	pi->requested_rps.ps_priv = &pi->requested_ps;
++}
++
++static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
++	struct amdgpu_ps *new_ps = &requested_ps;
++
++	ci_update_requested_ps(adev, new_ps);
++
++	ci_apply_state_adjust_rules(adev, &pi->requested_rps);
++
++	return 0;
++}
++
++static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_ps *new_ps = &pi->requested_rps;
++
++	ci_update_current_ps(adev, new_ps);
++}
++
++
++static void ci_dpm_setup_asic(struct amdgpu_device *adev)
++{
++	ci_read_clock_registers(adev);
++	ci_enable_acpi_power_management(adev);
++	ci_init_sclk_t(adev);
++}
++
++static int ci_dpm_enable(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
++	int ret;
++
++	if (amdgpu_ci_is_smc_running(adev))
++		return -EINVAL;
++	if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
++		ci_enable_voltage_control(adev);
++		ret = ci_construct_voltage_tables(adev);
++		if (ret) {
++			DRM_ERROR("ci_construct_voltage_tables failed\n");
++			return ret;
++		}
++	}
++	if (pi->caps_dynamic_ac_timing) {
++		ret = ci_initialize_mc_reg_table(adev);
++		if (ret)
++			pi->caps_dynamic_ac_timing = false;
++	}
++	if (pi->dynamic_ss)
++		ci_enable_spread_spectrum(adev, true);
++	if (pi->thermal_protection)
++		ci_enable_thermal_protection(adev, true);
++	ci_program_sstp(adev);
++	ci_enable_display_gap(adev);
++	ci_program_vc(adev);
++	ret = ci_upload_firmware(adev);
++	if (ret) {
++		DRM_ERROR("ci_upload_firmware failed\n");
++		return ret;
++	}
++	ret = ci_process_firmware_header(adev);
++	if (ret) {
++		DRM_ERROR("ci_process_firmware_header failed\n");
++		return ret;
++	}
++	ret = ci_initial_switch_from_arb_f0_to_f1(adev);
++	if (ret) {
++		DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
++		return ret;
++	}
++	ret = ci_init_smc_table(adev);
++	if (ret) {
++		DRM_ERROR("ci_init_smc_table failed\n");
++		return ret;
++	}
++	ret = ci_init_arb_table_index(adev);
++	if (ret) {
++		DRM_ERROR("ci_init_arb_table_index failed\n");
++		return ret;
++	}
++	if (pi->caps_dynamic_ac_timing) {
++		ret = ci_populate_initial_mc_reg_table(adev);
++		if (ret) {
++			DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
++			return ret;
++		}
++	}
++	ret = ci_populate_pm_base(adev);
++	if (ret) {
++		DRM_ERROR("ci_populate_pm_base failed\n");
++		return ret;
++	}
++	ci_dpm_start_smc(adev);
++	ci_enable_vr_hot_gpio_interrupt(adev);
++	ret = ci_notify_smc_display_change(adev, false);
++	if (ret) {
++		DRM_ERROR("ci_notify_smc_display_change failed\n");
++		return ret;
++	}
++	ci_enable_sclk_control(adev, true);
++	ret = ci_enable_ulv(adev, true);
++	if (ret) {
++		DRM_ERROR("ci_enable_ulv failed\n");
++		return ret;
++	}
++	ret = ci_enable_ds_master_switch(adev, true);
++	if (ret) {
++		DRM_ERROR("ci_enable_ds_master_switch failed\n");
++		return ret;
++	}
++	ret = ci_start_dpm(adev);
++	if (ret) {
++		DRM_ERROR("ci_start_dpm failed\n");
++		return ret;
++	}
++	ret = ci_enable_didt(adev, true);
++	if (ret) {
++		DRM_ERROR("ci_enable_didt failed\n");
++		return ret;
++	}
++	ret = ci_enable_smc_cac(adev, true);
++	if (ret) {
++		DRM_ERROR("ci_enable_smc_cac failed\n");
++		return ret;
++	}
++	ret = ci_enable_power_containment(adev, true);
++	if (ret) {
++		DRM_ERROR("ci_enable_power_containment failed\n");
++		return ret;
++	}
++
++	ret = ci_power_control_set_level(adev);
++	if (ret) {
++		DRM_ERROR("ci_power_control_set_level failed\n");
++		return ret;
++	}
++
++	ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
++
++	ret = ci_enable_thermal_based_sclk_dpm(adev, true);
++	if (ret) {
++		DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
++		return ret;
++	}
++
++	ci_thermal_start_thermal_controller(adev);
++
++	ci_update_current_ps(adev, boot_ps);
++
++	if (adev->irq.installed &&
++	    amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
++#if 0
++		PPSMC_Result result;
++#endif
++		ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
++						       CISLANDS_TEMP_RANGE_MAX);
++		if (ret) {
++			DRM_ERROR("ci_thermal_set_temperature_range failed\n");
++			return ret;
++		}
++		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
++			       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
++		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
++			       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
++
++#if 0
++		result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
++
++		if (result != PPSMC_Result_OK)
++			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
++#endif
++	}
++
++	return 0;
++}
++
++static void ci_dpm_disable(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
++
++	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
++		       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
++	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
++		       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
++
++	ci_dpm_powergate_uvd(adev, false);
++
++	if (!amdgpu_ci_is_smc_running(adev))
++		return;
++
++	ci_thermal_stop_thermal_controller(adev);
++
++	if (pi->thermal_protection)
++		ci_enable_thermal_protection(adev, false);
++	ci_enable_power_containment(adev, false);
++	ci_enable_smc_cac(adev, false);
++	ci_enable_didt(adev, false);
++	ci_enable_spread_spectrum(adev, false);
++	ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
++	ci_stop_dpm(adev);
++	ci_enable_ds_master_switch(adev, false);
++	ci_enable_ulv(adev, false);
++	ci_clear_vc(adev);
++	ci_reset_to_default(adev);
++	ci_dpm_stop_smc(adev);
++	ci_force_switch_to_arb_f0(adev);
++	ci_enable_thermal_based_sclk_dpm(adev, false);
++
++	ci_update_current_ps(adev, boot_ps);
++}
++
++static int ci_dpm_set_power_state(struct amdgpu_device *adev)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_ps *new_ps = &pi->requested_rps;
++	struct amdgpu_ps *old_ps = &pi->current_rps;
++	int ret;
++
++	ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
++	if (pi->pcie_performance_request)
++		ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
++	ret = ci_freeze_sclk_mclk_dpm(adev);
++	if (ret) {
++		DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
++		return ret;
++	}
++	ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
++	if (ret) {
++		DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
++		return ret;
++	}
++	ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
++	if (ret) {
++		DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
++		return ret;
++	}
++
++	ret = ci_update_vce_dpm(adev, new_ps, old_ps);
++	if (ret) {
++		DRM_ERROR("ci_update_vce_dpm failed\n");
++		return ret;
++	}
++
++	ret = ci_update_sclk_t(adev);
++	if (ret) {
++		DRM_ERROR("ci_update_sclk_t failed\n");
++		return ret;
++	}
++	if (pi->caps_dynamic_ac_timing) {
++		ret = ci_update_and_upload_mc_reg_table(adev);
++		if (ret) {
++			DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
++			return ret;
++		}
++	}
++	ret = ci_program_memory_timing_parameters(adev);
++	if (ret) {
++		DRM_ERROR("ci_program_memory_timing_parameters failed\n");
++		return ret;
++	}
++	ret = ci_unfreeze_sclk_mclk_dpm(adev);
++	if (ret) {
++		DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
++		return ret;
++	}
++	ret = ci_upload_dpm_level_enable_mask(adev);
++	if (ret) {
++		DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
++		return ret;
++	}
++	if (pi->pcie_performance_request)
++		ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
++
++	return 0;
++}
++
++#if 0
++static void ci_dpm_reset_asic(struct amdgpu_device *adev)
++{
++	ci_set_boot_state(adev);
++}
++#endif
++
++static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
++{
++	ci_program_display_gap(adev);
++}
++
++union power_info {
++	struct _ATOM_POWERPLAY_INFO info;
++	struct _ATOM_POWERPLAY_INFO_V2 info_2;
++	struct _ATOM_POWERPLAY_INFO_V3 info_3;
++	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
++	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
++	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
++};
++
++union pplib_clock_info {
++	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
++	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
++	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
++	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
++	struct _ATOM_PPLIB_SI_CLOCK_INFO si;
++	struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
++};
++
++union pplib_power_state {
++	struct _ATOM_PPLIB_STATE v1;
++	struct _ATOM_PPLIB_STATE_V2 v2;
++};
++
++static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
++					  struct amdgpu_ps *rps,
++					  struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
++					  u8 table_rev)
++{
++	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
++	rps->class = le16_to_cpu(non_clock_info->usClassification);
++	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
++
++	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
++		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
++		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
++	} else {
++		rps->vclk = 0;
++		rps->dclk = 0;
++	}
++
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
++		adev->pm.dpm.boot_ps = rps;
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
++		adev->pm.dpm.uvd_ps = rps;
++}
++
++static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
++				      struct amdgpu_ps *rps, int index,
++				      union pplib_clock_info *clock_info)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ps *ps = ci_get_ps(rps);
++	struct ci_pl *pl = &ps->performance_levels[index];
++
++	ps->performance_level_count = index + 1;
++
++	pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
++	pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
++	pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
++	pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
++
++	pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
++						   pi->sys_pcie_mask,
++						   pi->vbios_boot_state.pcie_gen_bootup_value,
++						   clock_info->ci.ucPCIEGen);
++	pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
++						     pi->vbios_boot_state.pcie_lane_bootup_value,
++						     le16_to_cpu(clock_info->ci.usPCIELane));
++
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
++		pi->acpi_pcie_gen = pl->pcie_gen;
++	}
++
++	if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
++		pi->ulv.supported = true;
++		pi->ulv.pl = *pl;
++		pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
++	}
++
++	/* patch up boot state */
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
++		pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
++		pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
++		pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
++		pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
++	}
++
++	switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
++	case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
++		pi->use_pcie_powersaving_levels = true;
++		if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
++			pi->pcie_gen_powersaving.max = pl->pcie_gen;
++		if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
++			pi->pcie_gen_powersaving.min = pl->pcie_gen;
++		if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
++			pi->pcie_lane_powersaving.max = pl->pcie_lane;
++		if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
++			pi->pcie_lane_powersaving.min = pl->pcie_lane;
++		break;
++	case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
++		pi->use_pcie_performance_levels = true;
++		if (pi->pcie_gen_performance.max < pl->pcie_gen)
++			pi->pcie_gen_performance.max = pl->pcie_gen;
++		if (pi->pcie_gen_performance.min > pl->pcie_gen)
++			pi->pcie_gen_performance.min = pl->pcie_gen;
++		if (pi->pcie_lane_performance.max < pl->pcie_lane)
++			pi->pcie_lane_performance.max = pl->pcie_lane;
++		if (pi->pcie_lane_performance.min > pl->pcie_lane)
++			pi->pcie_lane_performance.min = pl->pcie_lane;
++		break;
++	default:
++		break;
++	}
++}
++
++static int ci_parse_power_table(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
++	union pplib_power_state *power_state;
++	int i, j, k, non_clock_array_index, clock_array_index;
++	union pplib_clock_info *clock_info;
++	struct _StateArray *state_array;
++	struct _ClockInfoArray *clock_info_array;
++	struct _NonClockInfoArray *non_clock_info_array;
++	union power_info *power_info;
++	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
++	u16 data_offset;
++	u8 frev, crev;
++	u8 *power_state_offset;
++	struct ci_ps *ps;
++
++	if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset))
++		return -EINVAL;
++	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
++
++	amdgpu_add_thermal_controller(adev);
++
++	state_array = (struct _StateArray *)
++		(mode_info->atom_context->bios + data_offset +
++		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
++	clock_info_array = (struct _ClockInfoArray *)
++		(mode_info->atom_context->bios + data_offset +
++		 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
++	non_clock_info_array = (struct _NonClockInfoArray *)
++		(mode_info->atom_context->bios + data_offset +
++		 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
++
++	adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
++				  state_array->ucNumEntries, GFP_KERNEL);
++	if (!adev->pm.dpm.ps)
++		return -ENOMEM;
++	power_state_offset = (u8 *)state_array->states;
++	for (i = 0; i < state_array->ucNumEntries; i++) {
++		u8 *idx;
++		power_state = (union pplib_power_state *)power_state_offset;
++		non_clock_array_index = power_state->v2.nonClockInfoIndex;
++		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
++			&non_clock_info_array->nonClockInfo[non_clock_array_index];
++		ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
++		if (ps == NULL) {
++			kfree(adev->pm.dpm.ps);
++			return -ENOMEM;
++		}
++		adev->pm.dpm.ps[i].ps_priv = ps;
++		ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
++					      non_clock_info,
++					      non_clock_info_array->ucEntrySize);
++		k = 0;
++		idx = (u8 *)&power_state->v2.clockInfoIndex[0];
++		for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
++			clock_array_index = idx[j];
++			if (clock_array_index >= clock_info_array->ucNumEntries)
++				continue;
++			if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
++				break;
++			clock_info = (union pplib_clock_info *)
++				((u8 *)&clock_info_array->clockInfo[0] +
++				 (clock_array_index * clock_info_array->ucEntrySize));
++			ci_parse_pplib_clock_info(adev,
++						  &adev->pm.dpm.ps[i], k,
++						  clock_info);
++			k++;
++		}
++		power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
++	}
++	adev->pm.dpm.num_ps = state_array->ucNumEntries;
++
++	/* fill in the vce power states */
++	for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
++		u32 sclk, mclk;
++		clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
++		clock_info = (union pplib_clock_info *)
++			&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
++		sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
++		sclk |= clock_info->ci.ucEngineClockHigh << 16;
++		mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
++		mclk |= clock_info->ci.ucMemoryClockHigh << 16;
++		adev->pm.dpm.vce_states[i].sclk = sclk;
++		adev->pm.dpm.vce_states[i].mclk = mclk;
++	}
++
++	return 0;
++}
++
++static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
++				    struct ci_vbios_boot_state *boot_state)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
++	ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
++	u8 frev, crev;
++	u16 data_offset;
++
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset)) {
++		firmware_info =
++			(ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
++						    data_offset);
++		boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
++		boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
++		boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
++		boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
++		boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
++		boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
++		boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
++
++		return 0;
++	}
++	return -EINVAL;
++}
++
++static void ci_dpm_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->pm.dpm.num_ps; i++) {
++		kfree(adev->pm.dpm.ps[i].ps_priv);
++	}
++	kfree(adev->pm.dpm.ps);
++	kfree(adev->pm.dpm.priv);
++	kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
++	amdgpu_free_extended_power_table(adev);
++}
++
++/**
++ * ci_dpm_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int ci_dpm_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		chip_name = "bonaire";
++		break;
++	case CHIP_HAWAII:
++		chip_name = "hawaii";
++		break;
++	case CHIP_KAVERI:
++	case CHIP_KABINI:
++	default: BUG();
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
++	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->pm.fw);
++
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "cik_smc: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		release_firmware(adev->pm.fw);
++		adev->pm.fw = NULL;
++	}
++	return err;
++}
++
++static int ci_dpm_init(struct amdgpu_device *adev)
++{
++	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
++	SMU7_Discrete_DpmTable *dpm_table;
++	struct amdgpu_gpio_rec gpio;
++	u16 data_offset, size;
++	u8 frev, crev;
++	struct ci_power_info *pi;
++	int ret;
++	u32 mask;
++
++	ret = ci_dpm_init_microcode(adev);
++	if (ret)
++		return ret;
++
++	pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
++	if (pi == NULL)
++		return -ENOMEM;
++	adev->pm.dpm.priv = pi;
++
++	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
++	if (ret)
++		pi->sys_pcie_mask = 0;
++	else
++		pi->sys_pcie_mask = mask;
++	pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
++
++	pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
++	pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
++	pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
++	pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
++
++	pi->pcie_lane_performance.max = 0;
++	pi->pcie_lane_performance.min = 16;
++	pi->pcie_lane_powersaving.max = 0;
++	pi->pcie_lane_powersaving.min = 16;
++
++	ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
++	if (ret) {
++		ci_dpm_fini(adev);
++		return ret;
++	}
++
++	ret = amdgpu_get_platform_caps(adev);
++	if (ret) {
++		ci_dpm_fini(adev);
++		return ret;
++	}
++
++	ret = amdgpu_parse_extended_power_table(adev);
++	if (ret) {
++		ci_dpm_fini(adev);
++		return ret;
++	}
++
++	ret = ci_parse_power_table(adev);
++	if (ret) {
++		ci_dpm_fini(adev);
++		return ret;
++	}
++
++	pi->dll_default_on = false;
++	pi->sram_end = SMC_RAM_END;
++
++	pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
++	pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
++
++	pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
++
++	pi->sclk_dpm_key_disabled = 0;
++	pi->mclk_dpm_key_disabled = 0;
++	pi->pcie_dpm_key_disabled = 0;
++	pi->thermal_sclk_dpm_enabled = 0;
++
++	pi->caps_sclk_ds = true;
++
++	pi->mclk_strobe_mode_threshold = 40000;
++	pi->mclk_stutter_mode_threshold = 40000;
++	pi->mclk_edc_enable_threshold = 40000;
++	pi->mclk_edc_wr_enable_threshold = 40000;
++
++	ci_initialize_powertune_defaults(adev);
++
++	pi->caps_fps = false;
++
++	pi->caps_sclk_throttle_low_notification = false;
++
++	pi->caps_uvd_dpm = true;
++	pi->caps_vce_dpm = true;
++
++	ci_get_leakage_voltages(adev);
++	ci_patch_dependency_tables_with_leakage(adev);
++	ci_set_private_data_variables_based_on_pptable(adev);
++
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
++		kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
++	if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
++		ci_dpm_fini(adev);
++		return -ENOMEM;
++	}
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
++	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
++
++	adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
++	adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
++	adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
++
++	adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
++	adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
++	adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
++	adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
++
++	if (adev->asic_type == CHIP_HAWAII) {
++		pi->thermal_temp_setting.temperature_low = 94500;
++		pi->thermal_temp_setting.temperature_high = 95000;
++		pi->thermal_temp_setting.temperature_shutdown = 104000;
++	} else {
++		pi->thermal_temp_setting.temperature_low = 99500;
++		pi->thermal_temp_setting.temperature_high = 100000;
++		pi->thermal_temp_setting.temperature_shutdown = 104000;
++	}
++
++	pi->uvd_enabled = false;
++
++	dpm_table = &pi->smc_state_table;
++
++	gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
++	if (gpio.valid) {
++		dpm_table->VRHotGpio = gpio.shift;
++		adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
++	} else {
++		dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
++		adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
++	}
++
++	gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
++	if (gpio.valid) {
++		dpm_table->AcDcGpio = gpio.shift;
++		adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
++	} else {
++		dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
++		adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
++	}
++
++	gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
++	if (gpio.valid) {
++		u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
++
++		switch (gpio.shift) {
++		case 0:
++			tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
++			tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
++			break;
++		case 1:
++			tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
++			tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
++			break;
++		case 2:
++			tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
++			break;
++		case 3:
++			tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
++			break;
++		case 4:
++			tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
++			break;
++		default:
++			DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
++			break;
++		}
++		WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
++	}
++
++	pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
++	pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
++	pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
++	if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
++		pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
++	else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
++		pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
++
++	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
++		if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
++			pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
++		else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
++			pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
++		else
++			adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
++	}
++
++	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
++		if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
++			pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
++		else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
++			pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
++		else
++			adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
++	}
++
++	pi->vddc_phase_shed_control = true;
++
++#if defined(CONFIG_ACPI)
++	pi->pcie_performance_request =
++		amdgpu_acpi_is_pcie_performance_request_supported(adev);
++#else
++	pi->pcie_performance_request = false;
++#endif
++
++	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
++				   &frev, &crev, &data_offset)) {
++		pi->caps_sclk_ss_support = true;
++		pi->caps_mclk_ss_support = true;
++		pi->dynamic_ss = true;
++	} else {
++		pi->caps_sclk_ss_support = false;
++		pi->caps_mclk_ss_support = false;
++		pi->dynamic_ss = true;
++	}
++
++	if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
++		pi->thermal_protection = true;
++	else
++		pi->thermal_protection = false;
++
++	pi->caps_dynamic_ac_timing = true;
++
++	pi->uvd_power_gated = false;
++
++	/* make sure dc limits are valid */
++	if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
++	    (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
++		adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
++			adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++
++	pi->fan_ctrl_is_in_default_mode = true;
++
++	return 0;
++}
++
++static void
++ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
++					       struct seq_file *m)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct amdgpu_ps *rps = &pi->current_rps;
++	u32 sclk = ci_get_average_sclk_freq(adev);
++	u32 mclk = ci_get_average_mclk_freq(adev);
++
++	seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
++	seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
++	seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
++		   sclk, mclk);
++}
++
++static void ci_dpm_print_power_state(struct amdgpu_device *adev,
++				     struct amdgpu_ps *rps)
++{
++	struct ci_ps *ps = ci_get_ps(rps);
++	struct ci_pl *pl;
++	int i;
++
++	amdgpu_dpm_print_class_info(rps->class, rps->class2);
++	amdgpu_dpm_print_cap_info(rps->caps);
++	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
++	for (i = 0; i < ps->performance_level_count; i++) {
++		pl = &ps->performance_levels[i];
++		printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
++		       i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
++	}
++	amdgpu_dpm_print_ps_status(adev, rps);
++}
++
++static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
++
++	if (low)
++		return requested_state->performance_levels[0].sclk;
++	else
++		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
++}
++
++static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
++{
++	struct ci_power_info *pi = ci_get_pi(adev);
++	struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
++
++	if (low)
++		return requested_state->performance_levels[0].mclk;
++	else
++		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
++}
++
++/* get temperature in millidegrees */
++static int ci_dpm_get_temp(struct amdgpu_device *adev)
++{
++	u32 temp;
++	int actual_temp = 0;
++
++	temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
++		CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
++
++	if (temp & 0x200)
++		actual_temp = 255;
++	else
++		actual_temp = temp & 0x1ff;
++
++	actual_temp = actual_temp * 1000;
++
++	return actual_temp;
++}
++
++static int ci_set_temperature_range(struct amdgpu_device *adev)
++{
++	int ret;
++
++	ret = ci_thermal_enable_alert(adev, false);
++	if (ret)
++		return ret;
++	ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
++					       CISLANDS_TEMP_RANGE_MAX);
++	if (ret)
++		return ret;
++	ret = ci_thermal_enable_alert(adev, true);
++	if (ret)
++		return ret;
++	return ret;
++}
++
++static int ci_dpm_early_init(struct amdgpu_device *adev)
++{
++	ci_dpm_set_dpm_funcs(adev);
++	ci_dpm_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int ci_dpm_late_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (!amdgpu_dpm)
++		return 0;
++
++	ret = ci_set_temperature_range(adev);
++	if (ret)
++		return ret;
++
++	ci_dpm_powergate_uvd(adev, true);
++
++	return 0;
++}
++
++static int ci_dpm_sw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
++	if (ret)
++		return ret;
++
++	/* default to balanced state */
++	adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
++	adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
++	adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
++	adev->pm.default_sclk = adev->clock.default_sclk;
++	adev->pm.default_mclk = adev->clock.default_mclk;
++	adev->pm.current_sclk = adev->clock.default_sclk;
++	adev->pm.current_mclk = adev->clock.default_mclk;
++	adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
++
++	if (amdgpu_dpm == 0)
++		return 0;
++
++	INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
++	mutex_lock(&adev->pm.mutex);
++	ret = ci_dpm_init(adev);
++	if (ret)
++		goto dpm_failed;
++	adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
++	if (amdgpu_dpm == 1)
++		amdgpu_pm_print_power_states(adev);
++	ret = amdgpu_pm_sysfs_init(adev);
++	if (ret)
++		goto dpm_failed;
++	mutex_unlock(&adev->pm.mutex);
++	DRM_INFO("amdgpu: dpm initialized\n");
++
++	return 0;
++
++dpm_failed:
++	ci_dpm_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++	DRM_ERROR("amdgpu: dpm initialization failed\n");
++	return ret;
++}
++
++static int ci_dpm_sw_fini(struct amdgpu_device *adev)
++{
++	mutex_lock(&adev->pm.mutex);
++	amdgpu_pm_sysfs_fini(adev);
++	ci_dpm_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++
++	return 0;
++}
++
++static int ci_dpm_hw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (!amdgpu_dpm)
++		return 0;
++
++	mutex_lock(&adev->pm.mutex);
++	ci_dpm_setup_asic(adev);
++	ret = ci_dpm_enable(adev);
++	if (ret)
++		adev->pm.dpm_enabled = false;
++	else
++		adev->pm.dpm_enabled = true;
++	mutex_unlock(&adev->pm.mutex);
++
++	return ret;
++}
++
++static int ci_dpm_hw_fini(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++		ci_dpm_disable(adev);
++		mutex_unlock(&adev->pm.mutex);
++	}
++
++	return 0;
++}
++
++static int ci_dpm_suspend(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++		/* disable dpm */
++		ci_dpm_disable(adev);
++		/* reset the power state */
++		adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
++		mutex_unlock(&adev->pm.mutex);
++	}
++	return 0;
++}
++
++static int ci_dpm_resume(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (adev->pm.dpm_enabled) {
++		/* asic init will reset to the boot state */
++		mutex_lock(&adev->pm.mutex);
++		ci_dpm_setup_asic(adev);
++		ret = ci_dpm_enable(adev);
++		if (ret)
++			adev->pm.dpm_enabled = false;
++		else
++			adev->pm.dpm_enabled = true;
++		mutex_unlock(&adev->pm.mutex);
++		if (adev->pm.dpm_enabled)
++			amdgpu_pm_compute_clocks(adev);
++	}
++	return 0;
++}
++
++static bool ci_dpm_is_idle(struct amdgpu_device *adev)
++{
++	/* XXX */
++	return true;
++}
++
++static int ci_dpm_wait_for_idle(struct amdgpu_device *adev)
++{
++	/* XXX */
++	return 0;
++}
++
++static void ci_dpm_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "CIK DPM registers\n");
++	dev_info(adev->dev, "  BIOS_SCRATCH_4=0x%08X\n",
++		 RREG32(mmBIOS_SCRATCH_4));
++	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING=0x%08X\n",
++		 RREG32(mmMC_ARB_DRAM_TIMING));
++	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2=0x%08X\n",
++		 RREG32(mmMC_ARB_DRAM_TIMING2));
++	dev_info(adev->dev, "  MC_ARB_BURST_TIME=0x%08X\n",
++		 RREG32(mmMC_ARB_BURST_TIME));
++	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING_1=0x%08X\n",
++		 RREG32(mmMC_ARB_DRAM_TIMING_1));
++	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2_1=0x%08X\n",
++		 RREG32(mmMC_ARB_DRAM_TIMING2_1));
++	dev_info(adev->dev, "  MC_CG_CONFIG=0x%08X\n",
++		 RREG32(mmMC_CG_CONFIG));
++	dev_info(adev->dev, "  MC_ARB_CG=0x%08X\n",
++		 RREG32(mmMC_ARB_CG));
++	dev_info(adev->dev, "  DIDT_SQ_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_SQ_CTRL0));
++	dev_info(adev->dev, "  DIDT_DB_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_DB_CTRL0));
++	dev_info(adev->dev, "  DIDT_TD_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_TD_CTRL0));
++	dev_info(adev->dev, "  DIDT_TCP_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_TCP_CTRL0));
++	dev_info(adev->dev, "  CG_THERMAL_INT=0x%08X\n",
++		 RREG32_SMC(ixCG_THERMAL_INT));
++	dev_info(adev->dev, "  CG_THERMAL_CTRL=0x%08X\n",
++		 RREG32_SMC(ixCG_THERMAL_CTRL));
++	dev_info(adev->dev, "  GENERAL_PWRMGT=0x%08X\n",
++		 RREG32_SMC(ixGENERAL_PWRMGT));
++	dev_info(adev->dev, "  MC_SEQ_CNTL_3=0x%08X\n",
++		 RREG32(mmMC_SEQ_CNTL_3));
++	dev_info(adev->dev, "  LCAC_MC0_CNTL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC0_CNTL));
++	dev_info(adev->dev, "  LCAC_MC1_CNTL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC1_CNTL));
++	dev_info(adev->dev, "  LCAC_CPL_CNTL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_CPL_CNTL));
++	dev_info(adev->dev, "  SCLK_PWRMGT_CNTL=0x%08X\n",
++		 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
++	dev_info(adev->dev, "  BIF_LNCNT_RESET=0x%08X\n",
++		 RREG32(mmBIF_LNCNT_RESET));
++	dev_info(adev->dev, "  FIRMWARE_FLAGS=0x%08X\n",
++		 RREG32_SMC(ixFIRMWARE_FLAGS));
++	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL=0x%08X\n",
++		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
++	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_2=0x%08X\n",
++		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
++	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_3=0x%08X\n",
++		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
++	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_4=0x%08X\n",
++		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
++	dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
++		 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
++	dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
++		 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
++	dev_info(adev->dev, "  DLL_CNTL=0x%08X\n",
++		 RREG32(mmDLL_CNTL));
++	dev_info(adev->dev, "  MCLK_PWRMGT_CNTL=0x%08X\n",
++		 RREG32(mmMCLK_PWRMGT_CNTL));
++	dev_info(adev->dev, "  MPLL_AD_FUNC_CNTL=0x%08X\n",
++		 RREG32(mmMPLL_AD_FUNC_CNTL));
++	dev_info(adev->dev, "  MPLL_DQ_FUNC_CNTL=0x%08X\n",
++		 RREG32(mmMPLL_DQ_FUNC_CNTL));
++	dev_info(adev->dev, "  MPLL_FUNC_CNTL=0x%08X\n",
++		 RREG32(mmMPLL_FUNC_CNTL));
++	dev_info(adev->dev, "  MPLL_FUNC_CNTL_1=0x%08X\n",
++		 RREG32(mmMPLL_FUNC_CNTL_1));
++	dev_info(adev->dev, "  MPLL_FUNC_CNTL_2=0x%08X\n",
++		 RREG32(mmMPLL_FUNC_CNTL_2));
++	dev_info(adev->dev, "  MPLL_SS1=0x%08X\n",
++		 RREG32(mmMPLL_SS1));
++	dev_info(adev->dev, "  MPLL_SS2=0x%08X\n",
++		 RREG32(mmMPLL_SS2));
++	dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL=0x%08X\n",
++		 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
++	dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL2=0x%08X\n",
++		 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
++	dev_info(adev->dev, "  CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
++		 RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_0=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_1=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_2=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_3=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_4=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_5=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_6=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_7=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
++	dev_info(adev->dev, "  RCU_UC_EVENTS=0x%08X\n",
++		 RREG32_SMC(ixRCU_UC_EVENTS));
++	dev_info(adev->dev, "  DPM_TABLE_475=0x%08X\n",
++		 RREG32_SMC(ixDPM_TABLE_475));
++	dev_info(adev->dev, "  MC_SEQ_RAS_TIMING_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_RAS_TIMING_LP));
++	dev_info(adev->dev, "  MC_SEQ_RAS_TIMING=0x%08X\n",
++		 RREG32(mmMC_SEQ_RAS_TIMING));
++	dev_info(adev->dev, "  MC_SEQ_CAS_TIMING_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_CAS_TIMING_LP));
++	dev_info(adev->dev, "  MC_SEQ_CAS_TIMING=0x%08X\n",
++		 RREG32(mmMC_SEQ_CAS_TIMING));
++	dev_info(adev->dev, "  MC_SEQ_DLL_STBY_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_DLL_STBY_LP));
++	dev_info(adev->dev, "  MC_SEQ_DLL_STBY=0x%08X\n",
++		 RREG32(mmMC_SEQ_DLL_STBY));
++	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
++	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0=0x%08X\n",
++		 RREG32(mmMC_SEQ_G5PDX_CMD0));
++	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
++	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1=0x%08X\n",
++		 RREG32(mmMC_SEQ_G5PDX_CMD1));
++	dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
++	dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL=0x%08X\n",
++		 RREG32(mmMC_SEQ_G5PDX_CTRL));
++	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
++	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_DVS_CMD));
++	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
++	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_DVS_CTL));
++	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_MISC_TIMING_LP));
++	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING=0x%08X\n",
++		 RREG32(mmMC_SEQ_MISC_TIMING));
++	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_MISC_TIMING2_LP));
++	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2=0x%08X\n",
++		 RREG32(mmMC_SEQ_MISC_TIMING2));
++	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
++	dev_info(adev->dev, "  MC_PMG_CMD_EMRS=0x%08X\n",
++		 RREG32(mmMC_PMG_CMD_EMRS));
++	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
++	dev_info(adev->dev, "  MC_PMG_CMD_MRS=0x%08X\n",
++		 RREG32(mmMC_PMG_CMD_MRS));
++	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
++	dev_info(adev->dev, "  MC_PMG_CMD_MRS1=0x%08X\n",
++		 RREG32(mmMC_PMG_CMD_MRS1));
++	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_WR_CTL_D0_LP));
++	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0=0x%08X\n",
++		 RREG32(mmMC_SEQ_WR_CTL_D0));
++	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_WR_CTL_D1_LP));
++	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1=0x%08X\n",
++		 RREG32(mmMC_SEQ_WR_CTL_D1));
++	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_RD_CTL_D0_LP));
++	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0=0x%08X\n",
++		 RREG32(mmMC_SEQ_RD_CTL_D0));
++	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_RD_CTL_D1_LP));
++	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1=0x%08X\n",
++		 RREG32(mmMC_SEQ_RD_CTL_D1));
++	dev_info(adev->dev, "  MC_SEQ_PMG_TIMING_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_TIMING_LP));
++	dev_info(adev->dev, "  MC_SEQ_PMG_TIMING=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_TIMING));
++	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
++	dev_info(adev->dev, "  MC_PMG_CMD_MRS2=0x%08X\n",
++		 RREG32(mmMC_PMG_CMD_MRS2));
++	dev_info(adev->dev, "  MC_SEQ_WR_CTL_2_LP=0x%08X\n",
++		 RREG32(mmMC_SEQ_WR_CTL_2_LP));
++	dev_info(adev->dev, "  MC_SEQ_WR_CTL_2=0x%08X\n",
++		 RREG32(mmMC_SEQ_WR_CTL_2));
++	dev_info(adev->dev, "  PCIE_LC_SPEED_CNTL=0x%08X\n",
++		 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
++	dev_info(adev->dev, "  PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
++		 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
++	dev_info(adev->dev, "  SMC_IND_INDEX_0=0x%08X\n",
++		 RREG32(mmSMC_IND_INDEX_0));
++	dev_info(adev->dev, "  SMC_IND_DATA_0=0x%08X\n",
++		 RREG32(mmSMC_IND_DATA_0));
++	dev_info(adev->dev, "  SMC_IND_ACCESS_CNTL=0x%08X\n",
++		 RREG32(mmSMC_IND_ACCESS_CNTL));
++	dev_info(adev->dev, "  SMC_RESP_0=0x%08X\n",
++		 RREG32(mmSMC_RESP_0));
++	dev_info(adev->dev, "  SMC_MESSAGE_0=0x%08X\n",
++		 RREG32(mmSMC_MESSAGE_0));
++	dev_info(adev->dev, "  SMC_SYSCON_RESET_CNTL=0x%08X\n",
++		 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
++	dev_info(adev->dev, "  SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
++		 RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
++	dev_info(adev->dev, "  SMC_SYSCON_MISC_CNTL=0x%08X\n",
++		 RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
++	dev_info(adev->dev, "  SMC_PC_C=0x%08X\n",
++		 RREG32_SMC(ixSMC_PC_C));
++}
++
++static int ci_dpm_soft_reset(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      unsigned type,
++				      enum amdgpu_interrupt_state state)
++{
++	u32 cg_thermal_int;
++
++	switch (type) {
++	case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
++			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
++			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
++			break;
++		default:
++			break;
++		}
++		break;
++
++	case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
++			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
++			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
++			break;
++		default:
++			break;
++		}
++		break;
++
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
++				    struct amdgpu_irq_src *source, 
++				    struct amdgpu_iv_entry *entry)
++{
++	bool queue_thermal = false;
++
++	if (entry == NULL)
++		return -EINVAL;
++
++	switch (entry->src_id) {
++	case 230: /* thermal low to high */
++		DRM_DEBUG("IH: thermal low to high\n");
++		adev->pm.dpm.thermal.high_to_low = false;
++		queue_thermal = true;
++		break;
++	case 231: /* thermal high to low */
++		DRM_DEBUG("IH: thermal high to low\n");
++		adev->pm.dpm.thermal.high_to_low = true;
++		queue_thermal = true;
++		break;
++	default:
++		break;
++	}
++
++	if (queue_thermal)
++		schedule_work(&adev->pm.dpm.thermal.work);
++
++	return 0;
++}
++
++static int ci_dpm_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int ci_dpm_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs ci_dpm_ip_funcs = {
++	.early_init = ci_dpm_early_init,
++	.late_init = ci_dpm_late_init,
++	.sw_init = ci_dpm_sw_init,
++	.sw_fini = ci_dpm_sw_fini,
++	.hw_init = ci_dpm_hw_init,
++	.hw_fini = ci_dpm_hw_fini,
++	.suspend = ci_dpm_suspend,
++	.resume = ci_dpm_resume,
++	.is_idle = ci_dpm_is_idle,
++	.wait_for_idle = ci_dpm_wait_for_idle,
++	.soft_reset = ci_dpm_soft_reset,
++	.print_status = ci_dpm_print_status,
++	.set_clockgating_state = ci_dpm_set_clockgating_state,
++	.set_powergating_state = ci_dpm_set_powergating_state,
++};
++
++static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
++	.get_temperature = &ci_dpm_get_temp,
++	.pre_set_power_state = &ci_dpm_pre_set_power_state,
++	.set_power_state = &ci_dpm_set_power_state,
++	.post_set_power_state = &ci_dpm_post_set_power_state,
++	.display_configuration_changed = &ci_dpm_display_configuration_changed,
++	.get_sclk = &ci_dpm_get_sclk,
++	.get_mclk = &ci_dpm_get_mclk,
++	.print_power_state = &ci_dpm_print_power_state,
++	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
++	.force_performance_level = &ci_dpm_force_performance_level,
++	.vblank_too_short = &ci_dpm_vblank_too_short,
++	.powergate_uvd = &ci_dpm_powergate_uvd,
++	.set_fan_control_mode = &ci_dpm_set_fan_control_mode,
++	.get_fan_control_mode = &ci_dpm_get_fan_control_mode,
++	.set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
++	.get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
++};
++
++static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
++{
++	if (adev->pm.funcs == NULL)
++		adev->pm.funcs = &ci_dpm_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
++	.set = ci_dpm_set_interrupt_state,
++	.process = ci_dpm_process_interrupt,
++};
++
++static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
++	adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.h b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h
+new file mode 100644
+index 0000000..faccc30
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h
+@@ -0,0 +1,348 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __CI_DPM_H__
++#define __CI_DPM_H__
++
++#include "amdgpu_atombios.h"
++#include "ppsmc.h"
++
++#define SMU__NUM_SCLK_DPM_STATE  8
++#define SMU__NUM_MCLK_DPM_LEVELS 6
++#define SMU__NUM_LCLK_DPM_LEVELS 8
++#define SMU__NUM_PCIE_DPM_LEVELS 8
++#include "smu7_discrete.h"
++
++#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
++
++#define CISLANDS_UNUSED_GPIO_PIN 0x7F
++
++struct ci_pl {
++	u32 mclk;
++	u32 sclk;
++	enum amdgpu_pcie_gen pcie_gen;
++	u16 pcie_lane;
++};
++
++struct ci_ps {
++	u16 performance_level_count;
++	bool dc_compatible;
++	u32 sclk_t;
++	struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
++};
++
++struct ci_dpm_level {
++	bool enabled;
++	u32 value;
++	u32 param1;
++};
++
++#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
++#define MAX_REGULAR_DPM_NUMBER 8
++#define CISLAND_MINIMUM_ENGINE_CLOCK 800
++
++struct ci_single_dpm_table {
++	u32 count;
++	struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
++};
++
++struct ci_dpm_table {
++	struct ci_single_dpm_table sclk_table;
++	struct ci_single_dpm_table mclk_table;
++	struct ci_single_dpm_table pcie_speed_table;
++	struct ci_single_dpm_table vddc_table;
++	struct ci_single_dpm_table vddci_table;
++	struct ci_single_dpm_table mvdd_table;
++};
++
++struct ci_mc_reg_entry {
++	u32 mclk_max;
++	u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
++};
++
++struct ci_mc_reg_table {
++	u8 last;
++	u8 num_entries;
++	u16 valid_flag;
++	struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
++	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
++};
++
++struct ci_ulv_parm
++{
++	bool supported;
++	u32 cg_ulv_parameter;
++	u32 volt_change_delay;
++	struct ci_pl pl;
++};
++
++#define CISLANDS_MAX_LEAKAGE_COUNT  8
++
++struct ci_leakage_voltage {
++	u16 count;
++	u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
++	u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
++};
++
++struct ci_dpm_level_enable_mask {
++	u32 uvd_dpm_enable_mask;
++	u32 vce_dpm_enable_mask;
++	u32 acp_dpm_enable_mask;
++	u32 samu_dpm_enable_mask;
++	u32 sclk_dpm_enable_mask;
++	u32 mclk_dpm_enable_mask;
++	u32 pcie_dpm_enable_mask;
++};
++
++struct ci_vbios_boot_state
++{
++	u16 mvdd_bootup_value;
++	u16 vddc_bootup_value;
++	u16 vddci_bootup_value;
++	u32 sclk_bootup_value;
++	u32 mclk_bootup_value;
++	u16 pcie_gen_bootup_value;
++	u16 pcie_lane_bootup_value;
++};
++
++struct ci_clock_registers {
++	u32 cg_spll_func_cntl;
++	u32 cg_spll_func_cntl_2;
++	u32 cg_spll_func_cntl_3;
++	u32 cg_spll_func_cntl_4;
++	u32 cg_spll_spread_spectrum;
++	u32 cg_spll_spread_spectrum_2;
++	u32 dll_cntl;
++	u32 mclk_pwrmgt_cntl;
++	u32 mpll_ad_func_cntl;
++	u32 mpll_dq_func_cntl;
++	u32 mpll_func_cntl;
++	u32 mpll_func_cntl_1;
++	u32 mpll_func_cntl_2;
++	u32 mpll_ss1;
++	u32 mpll_ss2;
++};
++
++struct ci_thermal_temperature_setting {
++	s32 temperature_low;
++	s32 temperature_high;
++	s32 temperature_shutdown;
++};
++
++struct ci_pcie_perf_range {
++	u16 max;
++	u16 min;
++};
++
++enum ci_pt_config_reg_type {
++	CISLANDS_CONFIGREG_MMR = 0,
++	CISLANDS_CONFIGREG_SMC_IND,
++	CISLANDS_CONFIGREG_DIDT_IND,
++	CISLANDS_CONFIGREG_CACHE,
++	CISLANDS_CONFIGREG_MAX
++};
++
++#define POWERCONTAINMENT_FEATURE_BAPM            0x00000001
++#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
++#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
++
++struct ci_pt_config_reg {
++	u32 offset;
++	u32 mask;
++	u32 shift;
++	u32 value;
++	enum ci_pt_config_reg_type type;
++};
++
++struct ci_pt_defaults {
++	u8 svi_load_line_en;
++	u8 svi_load_line_vddc;
++	u8 tdc_vddc_throttle_release_limit_perc;
++	u8 tdc_mawt;
++	u8 tdc_waterfall_ctl;
++	u8 dte_ambient_temp_base;
++	u32 display_cac;
++	u32 bapm_temp_gradient;
++	u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
++	u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
++};
++
++#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
++#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
++#define DPMTABLE_UPDATE_SCLK        0x00000004
++#define DPMTABLE_UPDATE_MCLK        0x00000008
++
++struct ci_power_info {
++	struct ci_dpm_table dpm_table;
++	u32 voltage_control;
++	u32 mvdd_control;
++	u32 vddci_control;
++	u32 active_auto_throttle_sources;
++	struct ci_clock_registers clock_registers;
++	u16 acpi_vddc;
++	u16 acpi_vddci;
++	enum amdgpu_pcie_gen force_pcie_gen;
++	enum amdgpu_pcie_gen acpi_pcie_gen;
++	struct ci_leakage_voltage vddc_leakage;
++	struct ci_leakage_voltage vddci_leakage;
++	u16 max_vddc_in_pp_table;
++	u16 min_vddc_in_pp_table;
++	u16 max_vddci_in_pp_table;
++	u16 min_vddci_in_pp_table;
++	u32 mclk_strobe_mode_threshold;
++	u32 mclk_stutter_mode_threshold;
++	u32 mclk_edc_enable_threshold;
++	u32 mclk_edc_wr_enable_threshold;
++	struct ci_vbios_boot_state vbios_boot_state;
++	/* smc offsets */
++	u32 sram_end;
++	u32 dpm_table_start;
++	u32 soft_regs_start;
++	u32 mc_reg_table_start;
++	u32 fan_table_start;
++	u32 arb_table_start;
++	/* smc tables */
++	SMU7_Discrete_DpmTable smc_state_table;
++	SMU7_Discrete_MCRegisters smc_mc_reg_table;
++	SMU7_Discrete_PmFuses smc_powertune_table;
++	/* other stuff */
++	struct ci_mc_reg_table mc_reg_table;
++	struct atom_voltage_table vddc_voltage_table;
++	struct atom_voltage_table vddci_voltage_table;
++	struct atom_voltage_table mvdd_voltage_table;
++	struct ci_ulv_parm ulv;
++	u32 power_containment_features;
++	const struct ci_pt_defaults *powertune_defaults;
++	u32 dte_tj_offset;
++	bool vddc_phase_shed_control;
++	struct ci_thermal_temperature_setting thermal_temp_setting;
++	struct ci_dpm_level_enable_mask dpm_level_enable_mask;
++	u32 need_update_smu7_dpm_table;
++	u32 sclk_dpm_key_disabled;
++	u32 mclk_dpm_key_disabled;
++	u32 pcie_dpm_key_disabled;
++	u32 thermal_sclk_dpm_enabled;
++	struct ci_pcie_perf_range pcie_gen_performance;
++	struct ci_pcie_perf_range pcie_lane_performance;
++	struct ci_pcie_perf_range pcie_gen_powersaving;
++	struct ci_pcie_perf_range pcie_lane_powersaving;
++	u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
++	u32 mclk_activity_target;
++	u32 low_sclk_interrupt_t;
++	u32 last_mclk_dpm_enable_mask;
++	u32 sys_pcie_mask;
++	/* caps */
++	bool caps_power_containment;
++	bool caps_cac;
++	bool caps_sq_ramping;
++	bool caps_db_ramping;
++	bool caps_td_ramping;
++	bool caps_tcp_ramping;
++	bool caps_fps;
++	bool caps_sclk_ds;
++	bool caps_sclk_ss_support;
++	bool caps_mclk_ss_support;
++	bool caps_uvd_dpm;
++	bool caps_vce_dpm;
++	bool caps_samu_dpm;
++	bool caps_acp_dpm;
++	bool caps_automatic_dc_transition;
++	bool caps_sclk_throttle_low_notification;
++	bool caps_dynamic_ac_timing;
++	bool caps_od_fuzzy_fan_control_support;
++	/* flags */
++	bool thermal_protection;
++	bool pcie_performance_request;
++	bool dynamic_ss;
++	bool dll_default_on;
++	bool cac_enabled;
++	bool uvd_enabled;
++	bool battery_state;
++	bool pspp_notify_required;
++	bool enable_bapm_feature;
++	bool enable_tdc_limit_feature;
++	bool enable_pkg_pwr_tracking_feature;
++	bool use_pcie_performance_levels;
++	bool use_pcie_powersaving_levels;
++	bool uvd_power_gated;
++	/* driver states */
++	struct amdgpu_ps current_rps;
++	struct ci_ps current_ps;
++	struct amdgpu_ps requested_rps;
++	struct ci_ps requested_ps;
++	/* fan control */
++	bool fan_ctrl_is_in_default_mode;
++	bool fan_is_controlled_by_smc;
++	u32 t_min;
++	u32 fan_ctrl_default_mode;
++};
++
++#define CISLANDS_VOLTAGE_CONTROL_NONE                   0x0
++#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO                0x1
++#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2               0x2
++
++#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT             256
++
++#define CISLANDS_VRC_DFLT0                              0x3FFFC000
++#define CISLANDS_VRC_DFLT1                              0x000400
++#define CISLANDS_VRC_DFLT2                              0xC00080
++#define CISLANDS_VRC_DFLT3                              0xC00200
++#define CISLANDS_VRC_DFLT4                              0xC01680
++#define CISLANDS_VRC_DFLT5                              0xC00033
++#define CISLANDS_VRC_DFLT6                              0xC00033
++#define CISLANDS_VRC_DFLT7                              0x3FFFC000
++
++#define CISLANDS_CGULVPARAMETER_DFLT                    0x00040035
++#define CISLAND_TARGETACTIVITY_DFLT                     30
++#define CISLAND_MCLK_TARGETACTIVITY_DFLT                10
++
++#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
++#define PCIE_PERF_REQ_FORCE_LOWPOWER    1
++#define PCIE_PERF_REQ_PECI_GEN1         2
++#define PCIE_PERF_REQ_PECI_GEN2         3
++#define PCIE_PERF_REQ_PECI_GEN3         4
++
++#define CISLANDS_SSTU_DFLT                               0
++#define CISLANDS_SST_DFLT                                0x00C8
++
++/* XXX are these ok? */
++#define CISLANDS_TEMP_RANGE_MIN (90 * 1000)
++#define CISLANDS_TEMP_RANGE_MAX (120 * 1000)
++
++int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev,
++			 u32 smc_start_address,
++			 const u8 *src, u32 byte_count, u32 limit);
++void amdgpu_ci_start_smc(struct amdgpu_device *adev);
++void amdgpu_ci_reset_smc(struct amdgpu_device *adev);
++int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev);
++void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev);
++void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev);
++bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev);
++PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
++PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev);
++int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
++int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev,
++			   u32 smc_address, u32 *value, u32 limit);
++int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev,
++			    u32 smc_address, u32 value, u32 limit);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/ci_smc.c b/drivers/gpu/drm/amd/amdgpu/ci_smc.c
+new file mode 100644
+index 0000000..7eb9069
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/ci_smc.c
+@@ -0,0 +1,279 @@
++/*
++ * Copyright 2011 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "cikd.h"
++#include "ppsmc.h"
++#include "amdgpu_ucode.h"
++#include "ci_dpm.h"
++
++#include "smu/smu_7_0_1_d.h"
++#include "smu/smu_7_0_1_sh_mask.h"
++
++static int ci_set_smc_sram_address(struct amdgpu_device *adev,
++				   u32 smc_address, u32 limit)
++{
++	if (smc_address & 3)
++		return -EINVAL;
++	if ((smc_address + 3) > limit)
++		return -EINVAL;
++
++	WREG32(mmSMC_IND_INDEX_0, smc_address);
++	WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
++
++	return 0;
++}
++
++int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev,
++			 u32 smc_start_address,
++			 const u8 *src, u32 byte_count, u32 limit)
++{
++	unsigned long flags;
++	u32 data, original_data;
++	u32 addr;
++	u32 extra_shift;
++	int ret = 0;
++
++	if (smc_start_address & 3)
++		return -EINVAL;
++	if ((smc_start_address + byte_count) > limit)
++		return -EINVAL;
++
++	addr = smc_start_address;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	while (byte_count >= 4) {
++		/* SMC address space is BE */
++		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
++
++		ret = ci_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			goto done;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++
++		src += 4;
++		byte_count -= 4;
++		addr += 4;
++	}
++
++	/* RMW for the final bytes */
++	if (byte_count > 0) {
++		data = 0;
++
++		ret = ci_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			goto done;
++
++		original_data = RREG32(mmSMC_IND_DATA_0);
++
++		extra_shift = 8 * (4 - byte_count);
++
++		while (byte_count > 0) {
++			data = (data << 8) + *src++;
++			byte_count--;
++		}
++
++		data <<= extra_shift;
++
++		data |= (original_data & ~((~0UL) << extra_shift));
++
++		ret = ci_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			goto done;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++	}
++
++done:
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++
++	return ret;
++}
++
++void amdgpu_ci_start_smc(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++
++	tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
++}
++
++void amdgpu_ci_reset_smc(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++
++	tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
++}
++
++int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev)
++{
++	static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };
++
++	return amdgpu_ci_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
++}
++
++void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++
++	tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
++
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
++}
++
++void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++
++	tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
++
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
++}
++
++bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev)
++{
++	u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++	u32 pc_c = RREG32_SMC(ixSMC_PC_C);
++
++	if (!(clk & SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK) && (0x20100 <= pc_c))
++		return true;
++
++	return false;
++}
++
++PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
++{
++	u32 tmp;
++	int i;
++
++	if (!amdgpu_ci_is_smc_running(adev))
++		return PPSMC_Result_Failed;
++
++	WREG32(mmSMC_MESSAGE_0, msg);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmSMC_RESP_0);
++		if (tmp != 0)
++			break;
++		udelay(1);
++	}
++	tmp = RREG32(mmSMC_RESP_0);
++
++	return (PPSMC_Result)tmp;
++}
++
++PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev)
++{
++	u32 tmp;
++	int i;
++
++	if (!amdgpu_ci_is_smc_running(adev))
++		return PPSMC_Result_OK;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++		if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0)
++			break;
++		udelay(1);
++	}
++
++	return PPSMC_Result_OK;
++}
++
++int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
++{
++	const struct smc_firmware_header_v1_0 *hdr;
++	unsigned long flags;
++	u32 ucode_start_address;
++	u32 ucode_size;
++	const u8 *src;
++	u32 data;
++
++	if (!adev->pm.fw)
++		return -EINVAL;
++
++	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
++	amdgpu_ucode_print_smc_hdr(&hdr->header);
++
++	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
++	ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
++	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
++	src = (const u8 *)
++		(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++
++	if (ucode_size & 3)
++		return -EINVAL;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
++	WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK,
++		~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
++	while (ucode_size >= 4) {
++		/* SMC address space is BE */
++		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
++
++		WREG32(mmSMC_IND_DATA_0, data);
++
++		src += 4;
++		ucode_size -= 4;
++	}
++	WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++
++	return 0;
++}
++
++int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev,
++			   u32 smc_address, u32 *value, u32 limit)
++{
++	unsigned long flags;
++	int ret;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	ret = ci_set_smc_sram_address(adev, smc_address, limit);
++	if (ret == 0)
++		*value = RREG32(mmSMC_IND_DATA_0);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++
++	return ret;
++}
++
++int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev,
++			    u32 smc_address, u32 value, u32 limit)
++{
++	unsigned long flags;
++	int ret;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	ret = ci_set_smc_sram_address(adev, smc_address, limit);
++	if (ret == 0)
++		WREG32(mmSMC_IND_DATA_0, value);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+new file mode 100644
+index 0000000..74ce0be
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -0,0 +1,2505 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++#include <linux/firmware.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_ih.h"
++#include "amdgpu_uvd.h"
++#include "amdgpu_vce.h"
++#include "cikd.h"
++#include "atom.h"
++
++#include "cik.h"
++#include "gmc_v7_0.h"
++#include "cik_ih.h"
++#include "dce_v8_0.h"
++#include "gfx_v7_0.h"
++#include "cik_sdma.h"
++#include "uvd_v4_2.h"
++#include "vce_v2_0.h"
++#include "cik_dpm.h"
++
++#include "uvd/uvd_4_2_d.h"
++
++#include "smu/smu_7_0_1_d.h"
++#include "smu/smu_7_0_1_sh_mask.h"
++
++#include "dce/dce_8_0_d.h"
++#include "dce/dce_8_0_sh_mask.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "gca/gfx_7_2_d.h"
++#include "gca/gfx_7_2_enum.h"
++#include "gca/gfx_7_2_sh_mask.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++/*
++ * Indirect registers accessor
++ */
++static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(mmPCIE_INDEX, reg);
++	(void)RREG32(mmPCIE_INDEX);
++	r = RREG32(mmPCIE_DATA);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++	return r;
++}
++
++static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(mmPCIE_INDEX, reg);
++	(void)RREG32(mmPCIE_INDEX);
++	WREG32(mmPCIE_DATA, v);
++	(void)RREG32(mmPCIE_DATA);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
++static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, (reg));
++	r = RREG32(mmSMC_IND_DATA_0);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return r;
++}
++
++static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, (reg));
++	WREG32(mmSMC_IND_DATA_0, (v));
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++}
++
++static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
++	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
++	r = RREG32(mmUVD_CTX_DATA);
++	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
++	return r;
++}
++
++static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
++	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
++	WREG32(mmUVD_CTX_DATA, (v));
++	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
++}
++
++static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->didt_idx_lock, flags);
++	WREG32(mmDIDT_IND_INDEX, (reg));
++	r = RREG32(mmDIDT_IND_DATA);
++	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
++	return r;
++}
++
++static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->didt_idx_lock, flags);
++	WREG32(mmDIDT_IND_INDEX, (reg));
++	WREG32(mmDIDT_IND_DATA, (v));
++	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
++}
++
++static const u32 bonaire_golden_spm_registers[] =
++{
++	0xc200, 0xe0ffffff, 0xe0000000
++};
++
++static const u32 bonaire_golden_common_registers[] =
++{
++	0x31dc, 0xffffffff, 0x00000800,
++	0x31dd, 0xffffffff, 0x00000800,
++	0x31e6, 0xffffffff, 0x00007fbf,
++	0x31e7, 0xffffffff, 0x00007faf
++};
++
++static const u32 bonaire_golden_registers[] =
++{
++	0xcd5, 0x00000333, 0x00000333,
++	0xcd4, 0x000c0fc0, 0x00040200,
++	0x2684, 0x00010000, 0x00058208,
++	0xf000, 0xffff1fff, 0x00140000,
++	0xf080, 0xfdfc0fff, 0x00000100,
++	0xf08d, 0x40000000, 0x40000200,
++	0x260c, 0xffffffff, 0x00000000,
++	0x260d, 0xf00fffff, 0x00000400,
++	0x260e, 0x0002021c, 0x00020200,
++	0x31e, 0x00000080, 0x00000000,
++	0x16ec, 0x000000f0, 0x00000070,
++	0x16f0, 0xf0311fff, 0x80300000,
++	0x263e, 0x73773777, 0x12010001,
++	0xd43, 0x00810000, 0x408af000,
++	0x1c0c, 0x31000111, 0x00000011,
++	0xbd2, 0x73773777, 0x12010001,
++	0x883, 0x00007fb6, 0x0021a1b1,
++	0x884, 0x00007fb6, 0x002021b1,
++	0x860, 0x00007fb6, 0x00002191,
++	0x886, 0x00007fb6, 0x002121b1,
++	0x887, 0x00007fb6, 0x002021b1,
++	0x877, 0x00007fb6, 0x00002191,
++	0x878, 0x00007fb6, 0x00002191,
++	0xd8a, 0x0000003f, 0x0000000a,
++	0xd8b, 0x0000003f, 0x0000000a,
++	0xab9, 0x00073ffe, 0x000022a2,
++	0x903, 0x000007ff, 0x00000000,
++	0x2285, 0xf000003f, 0x00000007,
++	0x22fc, 0x00002001, 0x00000001,
++	0x22c9, 0xffffffff, 0x00ffffff,
++	0xc281, 0x0000ff0f, 0x00000000,
++	0xa293, 0x07ffffff, 0x06000000,
++	0x136, 0x00000fff, 0x00000100,
++	0xf9e, 0x00000001, 0x00000002,
++	0x2440, 0x03000000, 0x0362c688,
++	0x2300, 0x000000ff, 0x00000001,
++	0x390, 0x00001fff, 0x00001fff,
++	0x2418, 0x0000007f, 0x00000020,
++	0x2542, 0x00010000, 0x00010000,
++	0x2b05, 0x000003ff, 0x000000f3,
++	0x2b03, 0xffffffff, 0x00001032
++};
++
++static const u32 bonaire_mgcg_cgcg_init[] =
++{
++	0x3108, 0xffffffff, 0xfffffffc,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf0a8, 0xffffffff, 0x00000100,
++	0xf082, 0xffffffff, 0x00000100,
++	0xf0b0, 0xffffffff, 0xc0000100,
++	0xf0b2, 0xffffffff, 0xc0000100,
++	0xf0b1, 0xffffffff, 0xc0000100,
++	0x1579, 0xffffffff, 0x00600100,
++	0xf0a0, 0xffffffff, 0x00000100,
++	0xf085, 0xffffffff, 0x06000100,
++	0xf088, 0xffffffff, 0x00000100,
++	0xf086, 0xffffffff, 0x06000100,
++	0xf081, 0xffffffff, 0x00000100,
++	0xf0b8, 0xffffffff, 0x00000100,
++	0xf089, 0xffffffff, 0x00000100,
++	0xf080, 0xffffffff, 0x00000100,
++	0xf08c, 0xffffffff, 0x00000100,
++	0xf08d, 0xffffffff, 0x00000100,
++	0xf094, 0xffffffff, 0x00000100,
++	0xf095, 0xffffffff, 0x00000100,
++	0xf096, 0xffffffff, 0x00000100,
++	0xf097, 0xffffffff, 0x00000100,
++	0xf098, 0xffffffff, 0x00000100,
++	0xf09f, 0xffffffff, 0x00000100,
++	0xf09e, 0xffffffff, 0x00000100,
++	0xf084, 0xffffffff, 0x06000100,
++	0xf0a4, 0xffffffff, 0x00000100,
++	0xf09d, 0xffffffff, 0x00000100,
++	0xf0ad, 0xffffffff, 0x00000100,
++	0xf0ac, 0xffffffff, 0x00000100,
++	0xf09c, 0xffffffff, 0x00000100,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf008, 0xffffffff, 0x00010000,
++	0xf009, 0xffffffff, 0x00030002,
++	0xf00a, 0xffffffff, 0x00040007,
++	0xf00b, 0xffffffff, 0x00060005,
++	0xf00c, 0xffffffff, 0x00090008,
++	0xf00d, 0xffffffff, 0x00010000,
++	0xf00e, 0xffffffff, 0x00030002,
++	0xf00f, 0xffffffff, 0x00040007,
++	0xf010, 0xffffffff, 0x00060005,
++	0xf011, 0xffffffff, 0x00090008,
++	0xf012, 0xffffffff, 0x00010000,
++	0xf013, 0xffffffff, 0x00030002,
++	0xf014, 0xffffffff, 0x00040007,
++	0xf015, 0xffffffff, 0x00060005,
++	0xf016, 0xffffffff, 0x00090008,
++	0xf017, 0xffffffff, 0x00010000,
++	0xf018, 0xffffffff, 0x00030002,
++	0xf019, 0xffffffff, 0x00040007,
++	0xf01a, 0xffffffff, 0x00060005,
++	0xf01b, 0xffffffff, 0x00090008,
++	0xf01c, 0xffffffff, 0x00010000,
++	0xf01d, 0xffffffff, 0x00030002,
++	0xf01e, 0xffffffff, 0x00040007,
++	0xf01f, 0xffffffff, 0x00060005,
++	0xf020, 0xffffffff, 0x00090008,
++	0xf021, 0xffffffff, 0x00010000,
++	0xf022, 0xffffffff, 0x00030002,
++	0xf023, 0xffffffff, 0x00040007,
++	0xf024, 0xffffffff, 0x00060005,
++	0xf025, 0xffffffff, 0x00090008,
++	0xf026, 0xffffffff, 0x00010000,
++	0xf027, 0xffffffff, 0x00030002,
++	0xf028, 0xffffffff, 0x00040007,
++	0xf029, 0xffffffff, 0x00060005,
++	0xf02a, 0xffffffff, 0x00090008,
++	0xf000, 0xffffffff, 0x96e00200,
++	0x21c2, 0xffffffff, 0x00900100,
++	0x3109, 0xffffffff, 0x0020003f,
++	0xe, 0xffffffff, 0x0140001c,
++	0xf, 0x000f0000, 0x000f0000,
++	0x88, 0xffffffff, 0xc060000c,
++	0x89, 0xc0000fff, 0x00000100,
++	0x3e4, 0xffffffff, 0x00000100,
++	0x3e6, 0x00000101, 0x00000000,
++	0x82a, 0xffffffff, 0x00000104,
++	0x1579, 0xff000fff, 0x00000100,
++	0xc33, 0xc0000fff, 0x00000104,
++	0x3079, 0x00000001, 0x00000001,
++	0x3403, 0xff000ff0, 0x00000100,
++	0x3603, 0xff000ff0, 0x00000100
++};
++
++static const u32 spectre_golden_spm_registers[] =
++{
++	0xc200, 0xe0ffffff, 0xe0000000
++};
++
++static const u32 spectre_golden_common_registers[] =
++{
++	0x31dc, 0xffffffff, 0x00000800,
++	0x31dd, 0xffffffff, 0x00000800,
++	0x31e6, 0xffffffff, 0x00007fbf,
++	0x31e7, 0xffffffff, 0x00007faf
++};
++
++static const u32 spectre_golden_registers[] =
++{
++	0xf000, 0xffff1fff, 0x96940200,
++	0xf003, 0xffff0001, 0xff000000,
++	0xf080, 0xfffc0fff, 0x00000100,
++	0x1bb6, 0x00010101, 0x00010000,
++	0x260d, 0xf00fffff, 0x00000400,
++	0x260e, 0xfffffffc, 0x00020200,
++	0x16ec, 0x000000f0, 0x00000070,
++	0x16f0, 0xf0311fff, 0x80300000,
++	0x263e, 0x73773777, 0x12010001,
++	0x26df, 0x00ff0000, 0x00fc0000,
++	0xbd2, 0x73773777, 0x12010001,
++	0x2285, 0xf000003f, 0x00000007,
++	0x22c9, 0xffffffff, 0x00ffffff,
++	0xa0d4, 0x3f3f3fff, 0x00000082,
++	0xa0d5, 0x0000003f, 0x00000000,
++	0xf9e, 0x00000001, 0x00000002,
++	0x244f, 0xffff03df, 0x00000004,
++	0x31da, 0x00000008, 0x00000008,
++	0x2300, 0x000008ff, 0x00000800,
++	0x2542, 0x00010000, 0x00010000,
++	0x2b03, 0xffffffff, 0x54763210,
++	0x853e, 0x01ff01ff, 0x00000002,
++	0x8526, 0x007ff800, 0x00200000,
++	0x8057, 0xffffffff, 0x00000f40,
++	0xc24d, 0xffffffff, 0x00000001
++};
++
++static const u32 spectre_mgcg_cgcg_init[] =
++{
++	0x3108, 0xffffffff, 0xfffffffc,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf0a8, 0xffffffff, 0x00000100,
++	0xf082, 0xffffffff, 0x00000100,
++	0xf0b0, 0xffffffff, 0x00000100,
++	0xf0b2, 0xffffffff, 0x00000100,
++	0xf0b1, 0xffffffff, 0x00000100,
++	0x1579, 0xffffffff, 0x00600100,
++	0xf0a0, 0xffffffff, 0x00000100,
++	0xf085, 0xffffffff, 0x06000100,
++	0xf088, 0xffffffff, 0x00000100,
++	0xf086, 0xffffffff, 0x06000100,
++	0xf081, 0xffffffff, 0x00000100,
++	0xf0b8, 0xffffffff, 0x00000100,
++	0xf089, 0xffffffff, 0x00000100,
++	0xf080, 0xffffffff, 0x00000100,
++	0xf08c, 0xffffffff, 0x00000100,
++	0xf08d, 0xffffffff, 0x00000100,
++	0xf094, 0xffffffff, 0x00000100,
++	0xf095, 0xffffffff, 0x00000100,
++	0xf096, 0xffffffff, 0x00000100,
++	0xf097, 0xffffffff, 0x00000100,
++	0xf098, 0xffffffff, 0x00000100,
++	0xf09f, 0xffffffff, 0x00000100,
++	0xf09e, 0xffffffff, 0x00000100,
++	0xf084, 0xffffffff, 0x06000100,
++	0xf0a4, 0xffffffff, 0x00000100,
++	0xf09d, 0xffffffff, 0x00000100,
++	0xf0ad, 0xffffffff, 0x00000100,
++	0xf0ac, 0xffffffff, 0x00000100,
++	0xf09c, 0xffffffff, 0x00000100,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf008, 0xffffffff, 0x00010000,
++	0xf009, 0xffffffff, 0x00030002,
++	0xf00a, 0xffffffff, 0x00040007,
++	0xf00b, 0xffffffff, 0x00060005,
++	0xf00c, 0xffffffff, 0x00090008,
++	0xf00d, 0xffffffff, 0x00010000,
++	0xf00e, 0xffffffff, 0x00030002,
++	0xf00f, 0xffffffff, 0x00040007,
++	0xf010, 0xffffffff, 0x00060005,
++	0xf011, 0xffffffff, 0x00090008,
++	0xf012, 0xffffffff, 0x00010000,
++	0xf013, 0xffffffff, 0x00030002,
++	0xf014, 0xffffffff, 0x00040007,
++	0xf015, 0xffffffff, 0x00060005,
++	0xf016, 0xffffffff, 0x00090008,
++	0xf017, 0xffffffff, 0x00010000,
++	0xf018, 0xffffffff, 0x00030002,
++	0xf019, 0xffffffff, 0x00040007,
++	0xf01a, 0xffffffff, 0x00060005,
++	0xf01b, 0xffffffff, 0x00090008,
++	0xf01c, 0xffffffff, 0x00010000,
++	0xf01d, 0xffffffff, 0x00030002,
++	0xf01e, 0xffffffff, 0x00040007,
++	0xf01f, 0xffffffff, 0x00060005,
++	0xf020, 0xffffffff, 0x00090008,
++	0xf021, 0xffffffff, 0x00010000,
++	0xf022, 0xffffffff, 0x00030002,
++	0xf023, 0xffffffff, 0x00040007,
++	0xf024, 0xffffffff, 0x00060005,
++	0xf025, 0xffffffff, 0x00090008,
++	0xf026, 0xffffffff, 0x00010000,
++	0xf027, 0xffffffff, 0x00030002,
++	0xf028, 0xffffffff, 0x00040007,
++	0xf029, 0xffffffff, 0x00060005,
++	0xf02a, 0xffffffff, 0x00090008,
++	0xf02b, 0xffffffff, 0x00010000,
++	0xf02c, 0xffffffff, 0x00030002,
++	0xf02d, 0xffffffff, 0x00040007,
++	0xf02e, 0xffffffff, 0x00060005,
++	0xf02f, 0xffffffff, 0x00090008,
++	0xf000, 0xffffffff, 0x96e00200,
++	0x21c2, 0xffffffff, 0x00900100,
++	0x3109, 0xffffffff, 0x0020003f,
++	0xe, 0xffffffff, 0x0140001c,
++	0xf, 0x000f0000, 0x000f0000,
++	0x88, 0xffffffff, 0xc060000c,
++	0x89, 0xc0000fff, 0x00000100,
++	0x3e4, 0xffffffff, 0x00000100,
++	0x3e6, 0x00000101, 0x00000000,
++	0x82a, 0xffffffff, 0x00000104,
++	0x1579, 0xff000fff, 0x00000100,
++	0xc33, 0xc0000fff, 0x00000104,
++	0x3079, 0x00000001, 0x00000001,
++	0x3403, 0xff000ff0, 0x00000100,
++	0x3603, 0xff000ff0, 0x00000100
++};
++
++static const u32 kalindi_golden_spm_registers[] =
++{
++	0xc200, 0xe0ffffff, 0xe0000000
++};
++
++static const u32 kalindi_golden_common_registers[] =
++{
++	0x31dc, 0xffffffff, 0x00000800,
++	0x31dd, 0xffffffff, 0x00000800,
++	0x31e6, 0xffffffff, 0x00007fbf,
++	0x31e7, 0xffffffff, 0x00007faf
++};
++
++static const u32 kalindi_golden_registers[] =
++{
++	0xf000, 0xffffdfff, 0x6e944040,
++	0x1579, 0xff607fff, 0xfc000100,
++	0xf088, 0xff000fff, 0x00000100,
++	0xf089, 0xff000fff, 0x00000100,
++	0xf080, 0xfffc0fff, 0x00000100,
++	0x1bb6, 0x00010101, 0x00010000,
++	0x260c, 0xffffffff, 0x00000000,
++	0x260d, 0xf00fffff, 0x00000400,
++	0x16ec, 0x000000f0, 0x00000070,
++	0x16f0, 0xf0311fff, 0x80300000,
++	0x263e, 0x73773777, 0x12010001,
++	0x263f, 0xffffffff, 0x00000010,
++	0x26df, 0x00ff0000, 0x00fc0000,
++	0x200c, 0x00001f0f, 0x0000100a,
++	0xbd2, 0x73773777, 0x12010001,
++	0x902, 0x000fffff, 0x000c007f,
++	0x2285, 0xf000003f, 0x00000007,
++	0x22c9, 0x3fff3fff, 0x00ffcfff,
++	0xc281, 0x0000ff0f, 0x00000000,
++	0xa293, 0x07ffffff, 0x06000000,
++	0x136, 0x00000fff, 0x00000100,
++	0xf9e, 0x00000001, 0x00000002,
++	0x31da, 0x00000008, 0x00000008,
++	0x2300, 0x000000ff, 0x00000003,
++	0x853e, 0x01ff01ff, 0x00000002,
++	0x8526, 0x007ff800, 0x00200000,
++	0x8057, 0xffffffff, 0x00000f40,
++	0x2231, 0x001f3ae3, 0x00000082,
++	0x2235, 0x0000001f, 0x00000010,
++	0xc24d, 0xffffffff, 0x00000000
++};
++
++static const u32 kalindi_mgcg_cgcg_init[] =
++{
++	0x3108, 0xffffffff, 0xfffffffc,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf0a8, 0xffffffff, 0x00000100,
++	0xf082, 0xffffffff, 0x00000100,
++	0xf0b0, 0xffffffff, 0x00000100,
++	0xf0b2, 0xffffffff, 0x00000100,
++	0xf0b1, 0xffffffff, 0x00000100,
++	0x1579, 0xffffffff, 0x00600100,
++	0xf0a0, 0xffffffff, 0x00000100,
++	0xf085, 0xffffffff, 0x06000100,
++	0xf088, 0xffffffff, 0x00000100,
++	0xf086, 0xffffffff, 0x06000100,
++	0xf081, 0xffffffff, 0x00000100,
++	0xf0b8, 0xffffffff, 0x00000100,
++	0xf089, 0xffffffff, 0x00000100,
++	0xf080, 0xffffffff, 0x00000100,
++	0xf08c, 0xffffffff, 0x00000100,
++	0xf08d, 0xffffffff, 0x00000100,
++	0xf094, 0xffffffff, 0x00000100,
++	0xf095, 0xffffffff, 0x00000100,
++	0xf096, 0xffffffff, 0x00000100,
++	0xf097, 0xffffffff, 0x00000100,
++	0xf098, 0xffffffff, 0x00000100,
++	0xf09f, 0xffffffff, 0x00000100,
++	0xf09e, 0xffffffff, 0x00000100,
++	0xf084, 0xffffffff, 0x06000100,
++	0xf0a4, 0xffffffff, 0x00000100,
++	0xf09d, 0xffffffff, 0x00000100,
++	0xf0ad, 0xffffffff, 0x00000100,
++	0xf0ac, 0xffffffff, 0x00000100,
++	0xf09c, 0xffffffff, 0x00000100,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf008, 0xffffffff, 0x00010000,
++	0xf009, 0xffffffff, 0x00030002,
++	0xf00a, 0xffffffff, 0x00040007,
++	0xf00b, 0xffffffff, 0x00060005,
++	0xf00c, 0xffffffff, 0x00090008,
++	0xf00d, 0xffffffff, 0x00010000,
++	0xf00e, 0xffffffff, 0x00030002,
++	0xf00f, 0xffffffff, 0x00040007,
++	0xf010, 0xffffffff, 0x00060005,
++	0xf011, 0xffffffff, 0x00090008,
++	0xf000, 0xffffffff, 0x96e00200,
++	0x21c2, 0xffffffff, 0x00900100,
++	0x3109, 0xffffffff, 0x0020003f,
++	0xe, 0xffffffff, 0x0140001c,
++	0xf, 0x000f0000, 0x000f0000,
++	0x88, 0xffffffff, 0xc060000c,
++	0x89, 0xc0000fff, 0x00000100,
++	0x82a, 0xffffffff, 0x00000104,
++	0x1579, 0xff000fff, 0x00000100,
++	0xc33, 0xc0000fff, 0x00000104,
++	0x3079, 0x00000001, 0x00000001,
++	0x3403, 0xff000ff0, 0x00000100,
++	0x3603, 0xff000ff0, 0x00000100
++};
++
++static const u32 hawaii_golden_spm_registers[] =
++{
++	0xc200, 0xe0ffffff, 0xe0000000
++};
++
++static const u32 hawaii_golden_common_registers[] =
++{
++	0xc200, 0xffffffff, 0xe0000000,
++	0xa0d4, 0xffffffff, 0x3a00161a,
++	0xa0d5, 0xffffffff, 0x0000002e,
++	0x2684, 0xffffffff, 0x00018208,
++	0x263e, 0xffffffff, 0x12011003
++};
++
++static const u32 hawaii_golden_registers[] =
++{
++	0xcd5, 0x00000333, 0x00000333,
++	0x2684, 0x00010000, 0x00058208,
++	0x260c, 0xffffffff, 0x00000000,
++	0x260d, 0xf00fffff, 0x00000400,
++	0x260e, 0x0002021c, 0x00020200,
++	0x31e, 0x00000080, 0x00000000,
++	0x16ec, 0x000000f0, 0x00000070,
++	0x16f0, 0xf0311fff, 0x80300000,
++	0xd43, 0x00810000, 0x408af000,
++	0x1c0c, 0x31000111, 0x00000011,
++	0xbd2, 0x73773777, 0x12010001,
++	0x848, 0x0000007f, 0x0000001b,
++	0x877, 0x00007fb6, 0x00002191,
++	0xd8a, 0x0000003f, 0x0000000a,
++	0xd8b, 0x0000003f, 0x0000000a,
++	0xab9, 0x00073ffe, 0x000022a2,
++	0x903, 0x000007ff, 0x00000000,
++	0x22fc, 0x00002001, 0x00000001,
++	0x22c9, 0xffffffff, 0x00ffffff,
++	0xc281, 0x0000ff0f, 0x00000000,
++	0xa293, 0x07ffffff, 0x06000000,
++	0xf9e, 0x00000001, 0x00000002,
++	0x31da, 0x00000008, 0x00000008,
++	0x31dc, 0x00000f00, 0x00000800,
++	0x31dd, 0x00000f00, 0x00000800,
++	0x31e6, 0x00ffffff, 0x00ff7fbf,
++	0x31e7, 0x00ffffff, 0x00ff7faf,
++	0x2300, 0x000000ff, 0x00000800,
++	0x390, 0x00001fff, 0x00001fff,
++	0x2418, 0x0000007f, 0x00000020,
++	0x2542, 0x00010000, 0x00010000,
++	0x2b80, 0x00100000, 0x000ff07c,
++	0x2b05, 0x000003ff, 0x0000000f,
++	0x2b04, 0xffffffff, 0x7564fdec,
++	0x2b03, 0xffffffff, 0x3120b9a8,
++	0x2b02, 0x20000000, 0x0f9c0000
++};
++
++static const u32 hawaii_mgcg_cgcg_init[] =
++{
++	0x3108, 0xffffffff, 0xfffffffd,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf0a8, 0xffffffff, 0x00000100,
++	0xf082, 0xffffffff, 0x00000100,
++	0xf0b0, 0xffffffff, 0x00000100,
++	0xf0b2, 0xffffffff, 0x00000100,
++	0xf0b1, 0xffffffff, 0x00000100,
++	0x1579, 0xffffffff, 0x00200100,
++	0xf0a0, 0xffffffff, 0x00000100,
++	0xf085, 0xffffffff, 0x06000100,
++	0xf088, 0xffffffff, 0x00000100,
++	0xf086, 0xffffffff, 0x06000100,
++	0xf081, 0xffffffff, 0x00000100,
++	0xf0b8, 0xffffffff, 0x00000100,
++	0xf089, 0xffffffff, 0x00000100,
++	0xf080, 0xffffffff, 0x00000100,
++	0xf08c, 0xffffffff, 0x00000100,
++	0xf08d, 0xffffffff, 0x00000100,
++	0xf094, 0xffffffff, 0x00000100,
++	0xf095, 0xffffffff, 0x00000100,
++	0xf096, 0xffffffff, 0x00000100,
++	0xf097, 0xffffffff, 0x00000100,
++	0xf098, 0xffffffff, 0x00000100,
++	0xf09f, 0xffffffff, 0x00000100,
++	0xf09e, 0xffffffff, 0x00000100,
++	0xf084, 0xffffffff, 0x06000100,
++	0xf0a4, 0xffffffff, 0x00000100,
++	0xf09d, 0xffffffff, 0x00000100,
++	0xf0ad, 0xffffffff, 0x00000100,
++	0xf0ac, 0xffffffff, 0x00000100,
++	0xf09c, 0xffffffff, 0x00000100,
++	0xc200, 0xffffffff, 0xe0000000,
++	0xf008, 0xffffffff, 0x00010000,
++	0xf009, 0xffffffff, 0x00030002,
++	0xf00a, 0xffffffff, 0x00040007,
++	0xf00b, 0xffffffff, 0x00060005,
++	0xf00c, 0xffffffff, 0x00090008,
++	0xf00d, 0xffffffff, 0x00010000,
++	0xf00e, 0xffffffff, 0x00030002,
++	0xf00f, 0xffffffff, 0x00040007,
++	0xf010, 0xffffffff, 0x00060005,
++	0xf011, 0xffffffff, 0x00090008,
++	0xf012, 0xffffffff, 0x00010000,
++	0xf013, 0xffffffff, 0x00030002,
++	0xf014, 0xffffffff, 0x00040007,
++	0xf015, 0xffffffff, 0x00060005,
++	0xf016, 0xffffffff, 0x00090008,
++	0xf017, 0xffffffff, 0x00010000,
++	0xf018, 0xffffffff, 0x00030002,
++	0xf019, 0xffffffff, 0x00040007,
++	0xf01a, 0xffffffff, 0x00060005,
++	0xf01b, 0xffffffff, 0x00090008,
++	0xf01c, 0xffffffff, 0x00010000,
++	0xf01d, 0xffffffff, 0x00030002,
++	0xf01e, 0xffffffff, 0x00040007,
++	0xf01f, 0xffffffff, 0x00060005,
++	0xf020, 0xffffffff, 0x00090008,
++	0xf021, 0xffffffff, 0x00010000,
++	0xf022, 0xffffffff, 0x00030002,
++	0xf023, 0xffffffff, 0x00040007,
++	0xf024, 0xffffffff, 0x00060005,
++	0xf025, 0xffffffff, 0x00090008,
++	0xf026, 0xffffffff, 0x00010000,
++	0xf027, 0xffffffff, 0x00030002,
++	0xf028, 0xffffffff, 0x00040007,
++	0xf029, 0xffffffff, 0x00060005,
++	0xf02a, 0xffffffff, 0x00090008,
++	0xf02b, 0xffffffff, 0x00010000,
++	0xf02c, 0xffffffff, 0x00030002,
++	0xf02d, 0xffffffff, 0x00040007,
++	0xf02e, 0xffffffff, 0x00060005,
++	0xf02f, 0xffffffff, 0x00090008,
++	0xf030, 0xffffffff, 0x00010000,
++	0xf031, 0xffffffff, 0x00030002,
++	0xf032, 0xffffffff, 0x00040007,
++	0xf033, 0xffffffff, 0x00060005,
++	0xf034, 0xffffffff, 0x00090008,
++	0xf035, 0xffffffff, 0x00010000,
++	0xf036, 0xffffffff, 0x00030002,
++	0xf037, 0xffffffff, 0x00040007,
++	0xf038, 0xffffffff, 0x00060005,
++	0xf039, 0xffffffff, 0x00090008,
++	0xf03a, 0xffffffff, 0x00010000,
++	0xf03b, 0xffffffff, 0x00030002,
++	0xf03c, 0xffffffff, 0x00040007,
++	0xf03d, 0xffffffff, 0x00060005,
++	0xf03e, 0xffffffff, 0x00090008,
++	0x30c6, 0xffffffff, 0x00020200,
++	0xcd4, 0xffffffff, 0x00000200,
++	0x570, 0xffffffff, 0x00000400,
++	0x157a, 0xffffffff, 0x00000000,
++	0xbd4, 0xffffffff, 0x00000902,
++	0xf000, 0xffffffff, 0x96940200,
++	0x21c2, 0xffffffff, 0x00900100,
++	0x3109, 0xffffffff, 0x0020003f,
++	0xe, 0xffffffff, 0x0140001c,
++	0xf, 0x000f0000, 0x000f0000,
++	0x88, 0xffffffff, 0xc060000c,
++	0x89, 0xc0000fff, 0x00000100,
++	0x3e4, 0xffffffff, 0x00000100,
++	0x3e6, 0x00000101, 0x00000000,
++	0x82a, 0xffffffff, 0x00000104,
++	0x1579, 0xff000fff, 0x00000100,
++	0xc33, 0xc0000fff, 0x00000104,
++	0x3079, 0x00000001, 0x00000001,
++	0x3403, 0xff000ff0, 0x00000100,
++	0x3603, 0xff000ff0, 0x00000100
++};
++
++static const u32 godavari_golden_registers[] =
++{
++	0x1579, 0xff607fff, 0xfc000100,
++	0x1bb6, 0x00010101, 0x00010000,
++	0x260c, 0xffffffff, 0x00000000,
++	0x260c0, 0xf00fffff, 0x00000400,
++	0x184c, 0xffffffff, 0x00010000,
++	0x16ec, 0x000000f0, 0x00000070,
++	0x16f0, 0xf0311fff, 0x80300000,
++	0x263e, 0x73773777, 0x12010001,
++	0x263f, 0xffffffff, 0x00000010,
++	0x200c, 0x00001f0f, 0x0000100a,
++	0xbd2, 0x73773777, 0x12010001,
++	0x902, 0x000fffff, 0x000c007f,
++	0x2285, 0xf000003f, 0x00000007,
++	0x22c9, 0xffffffff, 0x00ff0fff,
++	0xc281, 0x0000ff0f, 0x00000000,
++	0xa293, 0x07ffffff, 0x06000000,
++	0x136, 0x00000fff, 0x00000100,
++	0x3405, 0x00010000, 0x00810001,
++	0x3605, 0x00010000, 0x00810001,
++	0xf9e, 0x00000001, 0x00000002,
++	0x31da, 0x00000008, 0x00000008,
++	0x31dc, 0x00000f00, 0x00000800,
++	0x31dd, 0x00000f00, 0x00000800,
++	0x31e6, 0x00ffffff, 0x00ff7fbf,
++	0x31e7, 0x00ffffff, 0x00ff7faf,
++	0x2300, 0x000000ff, 0x00000001,
++	0x853e, 0x01ff01ff, 0x00000002,
++	0x8526, 0x007ff800, 0x00200000,
++	0x8057, 0xffffffff, 0x00000f40,
++	0x2231, 0x001f3ae3, 0x00000082,
++	0x2235, 0x0000001f, 0x00000010,
++	0xc24d, 0xffffffff, 0x00000000
++};
++
++static void cik_init_golden_registers(struct amdgpu_device *adev)
++{
++	/* Some of the registers might be dependent on GRBM_GFX_INDEX */
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		amdgpu_program_register_sequence(adev,
++						 bonaire_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 bonaire_golden_registers,
++						 (const u32)ARRAY_SIZE(bonaire_golden_registers));
++		amdgpu_program_register_sequence(adev,
++						 bonaire_golden_common_registers,
++						 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
++		amdgpu_program_register_sequence(adev,
++						 bonaire_golden_spm_registers,
++						 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
++		break;
++	case CHIP_KABINI:
++		amdgpu_program_register_sequence(adev,
++						 kalindi_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 kalindi_golden_registers,
++						 (const u32)ARRAY_SIZE(kalindi_golden_registers));
++		amdgpu_program_register_sequence(adev,
++						 kalindi_golden_common_registers,
++						 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
++		amdgpu_program_register_sequence(adev,
++						 kalindi_golden_spm_registers,
++						 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
++		break;
++	case CHIP_MULLINS:
++		amdgpu_program_register_sequence(adev,
++						 kalindi_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 godavari_golden_registers,
++						 (const u32)ARRAY_SIZE(godavari_golden_registers));
++		amdgpu_program_register_sequence(adev,
++						 kalindi_golden_common_registers,
++						 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
++		amdgpu_program_register_sequence(adev,
++						 kalindi_golden_spm_registers,
++						 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
++		break;
++	case CHIP_KAVERI:
++		amdgpu_program_register_sequence(adev,
++						 spectre_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 spectre_golden_registers,
++						 (const u32)ARRAY_SIZE(spectre_golden_registers));
++		amdgpu_program_register_sequence(adev,
++						 spectre_golden_common_registers,
++						 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
++		amdgpu_program_register_sequence(adev,
++						 spectre_golden_spm_registers,
++						 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
++		break;
++	case CHIP_HAWAII:
++		amdgpu_program_register_sequence(adev,
++						 hawaii_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 hawaii_golden_registers,
++						 (const u32)ARRAY_SIZE(hawaii_golden_registers));
++		amdgpu_program_register_sequence(adev,
++						 hawaii_golden_common_registers,
++						 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
++		amdgpu_program_register_sequence(adev,
++						 hawaii_golden_spm_registers,
++						 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
++		break;
++	default:
++		break;
++	}
++	mutex_unlock(&adev->grbm_idx_mutex);
++}
++
++/**
++ * cik_get_xclk - get the xclk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Returns the reference clock used by the gfx engine
++ * (CIK).
++ */
++static u32 cik_get_xclk(struct amdgpu_device *adev)
++{
++	u32 reference_clock = adev->clock.spll.reference_freq;
++
++	if (adev->flags & AMDGPU_IS_APU) {
++		if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
++			return reference_clock / 2;
++	} else {
++		if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
++			return reference_clock / 4;
++	}
++	return reference_clock;
++}
++
++/**
++ * cik_srbm_select - select specific register instances
++ *
++ * @adev: amdgpu_device pointer
++ * @me: selected ME (micro engine)
++ * @pipe: pipe
++ * @queue: queue
++ * @vmid: VMID
++ *
++ * Switches the currently active registers instances.  Some
++ * registers are instanced per VMID, others are instanced per
++ * me/pipe/queue combination.
++ */
++void cik_srbm_select(struct amdgpu_device *adev,
++		     u32 me, u32 pipe, u32 queue, u32 vmid)
++{
++	u32 srbm_gfx_cntl =
++		(((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)|
++		((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)|
++		((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)|
++		((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK));
++	WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
++}
++
++static void cik_vga_set_state(struct amdgpu_device *adev, bool state)
++{
++	uint32_t tmp;
++
++	tmp = RREG32(mmCONFIG_CNTL);
++	if (state == false)
++		tmp |= CONFIG_CNTL__VGA_DIS_MASK;
++	else
++		tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;
++	WREG32(mmCONFIG_CNTL, tmp);
++}
++
++static bool cik_read_disabled_bios(struct amdgpu_device *adev)
++{
++	u32 bus_cntl;
++	u32 d1vga_control = 0;
++	u32 d2vga_control = 0;
++	u32 vga_render_control = 0;
++	u32 rom_cntl;
++	bool r;
++
++	bus_cntl = RREG32(mmBUS_CNTL);
++	if (adev->mode_info.num_crtc) {
++		d1vga_control = RREG32(mmD1VGA_CONTROL);
++		d2vga_control = RREG32(mmD2VGA_CONTROL);
++		vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
++	}
++	rom_cntl = RREG32_SMC(ixROM_CNTL);
++
++	/* enable the rom */
++	WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
++	if (adev->mode_info.num_crtc) {
++		/* Disable VGA mode */
++		WREG32(mmD1VGA_CONTROL,
++		       (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
++					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
++		WREG32(mmD2VGA_CONTROL,
++		       (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
++					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
++		WREG32(mmVGA_RENDER_CONTROL,
++		       (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
++	}
++	WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
++
++	r = amdgpu_read_bios(adev);
++
++	/* restore regs */
++	WREG32(mmBUS_CNTL, bus_cntl);
++	if (adev->mode_info.num_crtc) {
++		WREG32(mmD1VGA_CONTROL, d1vga_control);
++		WREG32(mmD2VGA_CONTROL, d2vga_control);
++		WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
++	}
++	WREG32_SMC(ixROM_CNTL, rom_cntl);
++	return r;
++}
++
++static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
++	{mmGRBM_STATUS, false},
++	{mmGB_ADDR_CONFIG, false},
++	{mmMC_ARB_RAMCFG, false},
++	{mmGB_TILE_MODE0, false},
++	{mmGB_TILE_MODE1, false},
++	{mmGB_TILE_MODE2, false},
++	{mmGB_TILE_MODE3, false},
++	{mmGB_TILE_MODE4, false},
++	{mmGB_TILE_MODE5, false},
++	{mmGB_TILE_MODE6, false},
++	{mmGB_TILE_MODE7, false},
++	{mmGB_TILE_MODE8, false},
++	{mmGB_TILE_MODE9, false},
++	{mmGB_TILE_MODE10, false},
++	{mmGB_TILE_MODE11, false},
++	{mmGB_TILE_MODE12, false},
++	{mmGB_TILE_MODE13, false},
++	{mmGB_TILE_MODE14, false},
++	{mmGB_TILE_MODE15, false},
++	{mmGB_TILE_MODE16, false},
++	{mmGB_TILE_MODE17, false},
++	{mmGB_TILE_MODE18, false},
++	{mmGB_TILE_MODE19, false},
++	{mmGB_TILE_MODE20, false},
++	{mmGB_TILE_MODE21, false},
++	{mmGB_TILE_MODE22, false},
++	{mmGB_TILE_MODE23, false},
++	{mmGB_TILE_MODE24, false},
++	{mmGB_TILE_MODE25, false},
++	{mmGB_TILE_MODE26, false},
++	{mmGB_TILE_MODE27, false},
++	{mmGB_TILE_MODE28, false},
++	{mmGB_TILE_MODE29, false},
++	{mmGB_TILE_MODE30, false},
++	{mmGB_TILE_MODE31, false},
++	{mmGB_MACROTILE_MODE0, false},
++	{mmGB_MACROTILE_MODE1, false},
++	{mmGB_MACROTILE_MODE2, false},
++	{mmGB_MACROTILE_MODE3, false},
++	{mmGB_MACROTILE_MODE4, false},
++	{mmGB_MACROTILE_MODE5, false},
++	{mmGB_MACROTILE_MODE6, false},
++	{mmGB_MACROTILE_MODE7, false},
++	{mmGB_MACROTILE_MODE8, false},
++	{mmGB_MACROTILE_MODE9, false},
++	{mmGB_MACROTILE_MODE10, false},
++	{mmGB_MACROTILE_MODE11, false},
++	{mmGB_MACROTILE_MODE12, false},
++	{mmGB_MACROTILE_MODE13, false},
++	{mmGB_MACROTILE_MODE14, false},
++	{mmGB_MACROTILE_MODE15, false},
++	{mmCC_RB_BACKEND_DISABLE, false, true},
++	{mmGC_USER_RB_BACKEND_DISABLE, false, true},
++	{mmGB_BACKEND_MAP, false, false},
++	{mmPA_SC_RASTER_CONFIG, false, true},
++	{mmPA_SC_RASTER_CONFIG_1, false, true},
++};
++
++static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
++					  u32 se_num, u32 sh_num,
++					  u32 reg_offset)
++{
++	uint32_t val;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	if (se_num != 0xffffffff || sh_num != 0xffffffff)
++		gfx_v7_0_select_se_sh(adev, se_num, sh_num);
++
++	val = RREG32(reg_offset);
++
++	if (se_num != 0xffffffff || sh_num != 0xffffffff)
++		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++	return val;
++}
++
++static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
++			     u32 sh_num, u32 reg_offset, u32 *value)
++{
++	uint32_t i;
++
++	*value = 0;
++	for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {
++		if (reg_offset != cik_allowed_read_registers[i].reg_offset)
++			continue;
++
++		if (!cik_allowed_read_registers[i].untouched)
++			*value = cik_allowed_read_registers[i].grbm_indexed ?
++				 cik_read_indexed_register(adev, se_num,
++							   sh_num, reg_offset) :
++				 RREG32(reg_offset);
++		return 0;
++	}
++	return -EINVAL;
++}
++
++static void cik_print_gpu_status_regs(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
++		RREG32(mmGRBM_STATUS));
++	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
++		RREG32(mmGRBM_STATUS2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE0));
++	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE1));
++	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE3));
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++	dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
++		RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
++	dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
++		 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
++	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
++	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT2));
++	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT3));
++	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
++		 RREG32(mmCP_CPF_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPF_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
++	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPC_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
++}
++
++/**
++ * cik_gpu_check_soft_reset - check which blocks are busy
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Check which blocks are busy and return the relevant reset
++ * mask to be used by cik_gpu_soft_reset().
++ * Returns a mask of the blocks to be reset.
++ */
++u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev)
++{
++	u32 reset_mask = 0;
++	u32 tmp;
++
++	/* GRBM_STATUS */
++	tmp = RREG32(mmGRBM_STATUS);
++	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
++		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
++		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
++		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
++		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
++		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
++		reset_mask |= AMDGPU_RESET_GFX;
++
++	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
++		reset_mask |= AMDGPU_RESET_CP;
++
++	/* GRBM_STATUS2 */
++	tmp = RREG32(mmGRBM_STATUS2);
++	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_RLC;
++
++	/* SDMA0_STATUS_REG */
++	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
++	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
++		reset_mask |= AMDGPU_RESET_DMA;
++
++	/* SDMA1_STATUS_REG */
++	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
++	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
++		reset_mask |= AMDGPU_RESET_DMA1;
++
++	/* SRBM_STATUS2 */
++	tmp = RREG32(mmSRBM_STATUS2);
++	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_DMA;
++
++	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_DMA1;
++
++	/* SRBM_STATUS */
++	tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_IH;
++
++	if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_SEM;
++
++	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
++		reset_mask |= AMDGPU_RESET_GRBM;
++
++	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_VMC;
++
++	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
++		reset_mask |= AMDGPU_RESET_MC;
++
++	if (amdgpu_display_is_display_hung(adev))
++		reset_mask |= AMDGPU_RESET_DISPLAY;
++
++	/* Skip MC reset as it's mostly likely not hung, just busy */
++	if (reset_mask & AMDGPU_RESET_MC) {
++		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
++		reset_mask &= ~AMDGPU_RESET_MC;
++	}
++
++	return reset_mask;
++}
++
++/**
++ * cik_gpu_soft_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ * @reset_mask: mask of which blocks to reset
++ *
++ * Soft reset the blocks specified in @reset_mask.
++ */
++static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
++	u32 tmp;
++
++	if (reset_mask == 0)
++		return;
++
++	dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
++
++	cik_print_gpu_status_regs(adev);
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
++
++	/* disable CG/PG */
++
++	/* stop the rlc */
++	gfx_v7_0_rlc_stop(adev);
++
++	/* Disable GFX parsing/prefetching */
++	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
++
++	/* Disable MEC parsing/prefetching */
++	WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
++
++	if (reset_mask & AMDGPU_RESET_DMA) {
++		/* sdma0 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++		tmp |= SDMA0_F32_CNTL__HALT_MASK;
++		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++	}
++	if (reset_mask & AMDGPU_RESET_DMA1) {
++		/* sdma1 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++		tmp |= SDMA0_F32_CNTL__HALT_MASK;
++		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++	}
++
++	gmc_v7_0_mc_stop(adev, &save);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
++	}
++
++	if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP))
++		grbm_soft_reset = GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
++			GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
++
++	if (reset_mask & AMDGPU_RESET_CP) {
++		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
++
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
++	}
++
++	if (reset_mask & AMDGPU_RESET_DMA)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
++
++	if (reset_mask & AMDGPU_RESET_DMA1)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
++
++	if (reset_mask & AMDGPU_RESET_DISPLAY)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
++
++	if (reset_mask & AMDGPU_RESET_RLC)
++		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
++
++	if (reset_mask & AMDGPU_RESET_SEM)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK;
++
++	if (reset_mask & AMDGPU_RESET_IH)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
++
++	if (reset_mask & AMDGPU_RESET_GRBM)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
++
++	if (reset_mask & AMDGPU_RESET_VMC)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK;
++
++	if (!(adev->flags & AMDGPU_IS_APU)) {
++		if (reset_mask & AMDGPU_RESET_MC)
++			srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK;
++	}
++
++	if (grbm_soft_reset) {
++		tmp = RREG32(mmGRBM_SOFT_RESET);
++		tmp |= grbm_soft_reset;
++		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmGRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmGRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~grbm_soft_reset;
++		WREG32(mmGRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmGRBM_SOFT_RESET);
++	}
++
++	if (srbm_soft_reset) {
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++	}
++
++	/* Wait a little for things to settle down */
++	udelay(50);
++
++	gmc_v7_0_mc_resume(adev, &save);
++	udelay(50);
++
++	cik_print_gpu_status_regs(adev);
++}
++
++struct kv_reset_save_regs {
++	u32 gmcon_reng_execute;
++	u32 gmcon_misc;
++	u32 gmcon_misc3;
++};
++
++static void kv_save_regs_for_reset(struct amdgpu_device *adev,
++				   struct kv_reset_save_regs *save)
++{
++	save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);
++	save->gmcon_misc = RREG32(mmGMCON_MISC);
++	save->gmcon_misc3 = RREG32(mmGMCON_MISC3);
++
++	WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &
++		~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK);
++	WREG32(mmGMCON_MISC, save->gmcon_misc &
++		~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK |
++			GMCON_MISC__STCTRL_STUTTER_EN_MASK));
++}
++
++static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
++				      struct kv_reset_save_regs *save)
++{
++	int i;
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x210000);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x21003);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x420000);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x120202);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);
++
++	for (i = 0; i < 5; i++)
++		WREG32(mmGMCON_PGFSM_WRITE, 0);
++
++	WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);
++	WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);
++
++	WREG32(mmGMCON_MISC3, save->gmcon_misc3);
++	WREG32(mmGMCON_MISC, save->gmcon_misc);
++	WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);
++}
++
++static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_mc_save save;
++	struct kv_reset_save_regs kv_save = { 0 };
++	u32 tmp, i;
++
++	dev_info(adev->dev, "GPU pci config reset\n");
++
++	/* disable dpm? */
++
++	/* disable cg/pg */
++
++	/* Disable GFX parsing/prefetching */
++	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
++		CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
++
++	/* Disable MEC parsing/prefetching */
++	WREG32(mmCP_MEC_CNTL,
++			CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
++
++	/* sdma0 */
++	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++	tmp |= SDMA0_F32_CNTL__HALT_MASK;
++	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++	/* sdma1 */
++	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++	tmp |= SDMA0_F32_CNTL__HALT_MASK;
++	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++	/* XXX other engines? */
++
++	/* halt the rlc, disable cp internal ints */
++	gfx_v7_0_rlc_stop(adev);
++
++	udelay(50);
++
++	/* disable mem access */
++	gmc_v7_0_mc_stop(adev, &save);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timed out !\n");
++	}
++
++	if (adev->flags & AMDGPU_IS_APU)
++		kv_save_regs_for_reset(adev, &kv_save);
++
++	/* disable BM */
++	pci_clear_master(adev->pdev);
++	/* reset */
++	amdgpu_pci_config_reset(adev);
++
++	udelay(100);
++
++	/* wait for asic to come out of reset */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
++			break;
++		udelay(1);
++	}
++
++	/* does asic init need to be run first??? */
++	if (adev->flags & AMDGPU_IS_APU)
++		kv_restore_regs_for_reset(adev, &kv_save);
++}
++
++static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
++{
++	u32 tmp = RREG32(mmBIOS_SCRATCH_3);
++
++	if (hung)
++		tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
++	else
++		tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
++
++	WREG32(mmBIOS_SCRATCH_3, tmp);
++}
++
++/**
++ * cik_asic_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up which blocks are hung and attempt
++ * to reset them.
++ * Returns 0 for success.
++ */
++static int cik_asic_reset(struct amdgpu_device *adev)
++{
++	u32 reset_mask;
++
++	reset_mask = amdgpu_cik_gpu_check_soft_reset(adev);
++
++	if (reset_mask)
++		cik_set_bios_scratch_engine_hung(adev, true);
++
++	/* try soft reset */
++	cik_gpu_soft_reset(adev, reset_mask);
++
++	reset_mask = amdgpu_cik_gpu_check_soft_reset(adev);
++
++	/* try pci config reset */
++	if (reset_mask && amdgpu_hard_reset)
++		cik_gpu_pci_config_reset(adev);
++
++	reset_mask = amdgpu_cik_gpu_check_soft_reset(adev);
++
++	if (!reset_mask)
++		cik_set_bios_scratch_engine_hung(adev, false);
++
++	return 0;
++}
++
++static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
++			      u32 cntl_reg, u32 status_reg)
++{
++	int r, i;
++	struct atom_clock_dividers dividers;
++	uint32_t tmp;
++
++	r = amdgpu_atombios_get_clock_dividers(adev,
++					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++					       clock, false, &dividers);
++	if (r)
++		return r;
++
++	tmp = RREG32_SMC(cntl_reg);
++	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
++		CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
++	tmp |= dividers.post_divider;
++	WREG32_SMC(cntl_reg, tmp);
++
++	for (i = 0; i < 100; i++) {
++		if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
++			break;
++		mdelay(10);
++	}
++	if (i == 100)
++		return -ETIMEDOUT;
++
++	return 0;
++}
++
++static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
++{
++	int r = 0;
++
++	r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
++	if (r)
++		return r;
++
++	r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
++	return r;
++}
++
++static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
++{
++	int r, i;
++	struct atom_clock_dividers dividers;
++	u32 tmp;
++
++	r = amdgpu_atombios_get_clock_dividers(adev,
++					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++					       ecclk, false, &dividers);
++	if (r)
++		return r;
++
++	for (i = 0; i < 100; i++) {
++		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
++			break;
++		mdelay(10);
++	}
++	if (i == 100)
++		return -ETIMEDOUT;
++
++	tmp = RREG32_SMC(ixCG_ECLK_CNTL);
++	tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
++		CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
++	tmp |= dividers.post_divider;
++	WREG32_SMC(ixCG_ECLK_CNTL, tmp);
++
++	for (i = 0; i < 100; i++) {
++		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
++			break;
++		mdelay(10);
++	}
++	if (i == 100)
++		return -ETIMEDOUT;
++
++	return 0;
++}
++
++static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
++{
++	struct pci_dev *root = adev->pdev->bus->self;
++	int bridge_pos, gpu_pos;
++	u32 speed_cntl, mask, current_data_rate;
++	int ret, i;
++	u16 tmp16;
++
++	if (amdgpu_pcie_gen2 == 0)
++		return;
++
++	if (adev->flags & AMDGPU_IS_APU)
++		return;
++
++	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
++	if (ret != 0)
++		return;
++
++	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
++		return;
++
++	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
++	current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
++		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
++	if (mask & DRM_PCIE_SPEED_80) {
++		if (current_data_rate == 2) {
++			DRM_INFO("PCIE gen 3 link speeds already enabled\n");
++			return;
++		}
++		DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
++	} else if (mask & DRM_PCIE_SPEED_50) {
++		if (current_data_rate == 1) {
++			DRM_INFO("PCIE gen 2 link speeds already enabled\n");
++			return;
++		}
++		DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
++	}
++
++	bridge_pos = pci_pcie_cap(root);
++	if (!bridge_pos)
++		return;
++
++	gpu_pos = pci_pcie_cap(adev->pdev);
++	if (!gpu_pos)
++		return;
++
++	if (mask & DRM_PCIE_SPEED_80) {
++		/* re-try equalization if gen3 is not already enabled */
++		if (current_data_rate != 2) {
++			u16 bridge_cfg, gpu_cfg;
++			u16 bridge_cfg2, gpu_cfg2;
++			u32 max_lw, current_lw, tmp;
++
++			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
++			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
++
++			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
++			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
++
++			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
++			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
++
++			tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
++			max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
++				PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;
++			current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)
++				>> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;
++
++			if (current_lw < max_lw) {
++				tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
++				if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
++					tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |
++						PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);
++					tmp |= (max_lw <<
++						PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);
++					tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |
++					PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK |
++					PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;
++					WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
++				}
++			}
++
++			for (i = 0; i < 10; i++) {
++				/* check status */
++				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
++				if (tmp16 & PCI_EXP_DEVSTA_TRPND)
++					break;
++
++				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
++				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
++
++				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
++				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
++
++				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
++				tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
++				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
++
++				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
++				tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
++				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
++
++				mdelay(100);
++
++				/* linkctl */
++				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
++				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
++				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
++				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
++
++				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
++				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
++				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
++				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
++
++				/* linkctl2 */
++				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
++				tmp16 &= ~((1 << 4) | (7 << 9));
++				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
++				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
++
++				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
++				tmp16 &= ~((1 << 4) | (7 << 9));
++				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
++				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
++
++				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
++				tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
++				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
++			}
++		}
++	}
++
++	/* set the link speed */
++	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK |
++		PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK;
++	speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
++	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
++
++	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
++	tmp16 &= ~0xf;
++	if (mask & DRM_PCIE_SPEED_80)
++		tmp16 |= 3; /* gen3 */
++	else if (mask & DRM_PCIE_SPEED_50)
++		tmp16 |= 2; /* gen2 */
++	else
++		tmp16 |= 1; /* gen1 */
++	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
++
++	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
++	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
++	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
++		if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)
++			break;
++		udelay(1);
++	}
++}
++
++static void cik_program_aspm(struct amdgpu_device *adev)
++{
++	u32 data, orig;
++	bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
++	bool disable_clkreq = false;
++
++	if (amdgpu_aspm == 0)
++		return;
++
++	/* XXX double check APUs */
++	if (adev->flags & AMDGPU_IS_APU)
++		return;
++
++	orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
++	data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
++	data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) |
++		PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
++	if (orig != data)
++		WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
++
++	orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
++	data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
++	if (orig != data)
++		WREG32_PCIE(ixPCIE_LC_CNTL3, data);
++
++	orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
++	data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
++	if (orig != data)
++		WREG32_PCIE(ixPCIE_P_CNTL, data);
++
++	orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
++	data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK |
++		PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
++	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
++	if (!disable_l0s)
++		data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);
++
++	if (!disable_l1) {
++		data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);
++		data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
++		if (orig != data)
++			WREG32_PCIE(ixPCIE_LC_CNTL, data);
++
++		if (!disable_plloff_in_l1) {
++			bool clk_req_support;
++
++			orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0);
++			data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
++				PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
++			data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
++				(7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
++			if (orig != data)
++				WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data);
++
++			orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1);
++			data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
++				PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
++			data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
++				(7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
++			if (orig != data)
++				WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data);
++
++			orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0);
++			data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
++				PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
++			data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
++				(7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
++			if (orig != data)
++				WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data);
++
++			orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1);
++			data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
++				PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
++			data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
++				(7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
++			if (orig != data)
++				WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data);
++
++			orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
++			data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
++			data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
++			if (orig != data)
++				WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
++
++			if (!disable_clkreq) {
++				struct pci_dev *root = adev->pdev->bus->self;
++				u32 lnkcap;
++
++				clk_req_support = false;
++				pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
++				if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
++					clk_req_support = true;
++			} else {
++				clk_req_support = false;
++			}
++
++			if (clk_req_support) {
++				orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
++				data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
++					PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
++				if (orig != data)
++					WREG32_PCIE(ixPCIE_LC_CNTL2, data);
++
++				orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
++				data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |
++					THM_CLK_CNTL__TMON_CLK_SEL_MASK);
++				data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
++					(1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
++				if (orig != data)
++					WREG32_SMC(ixTHM_CLK_CNTL, data);
++
++				orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
++				data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
++					MISC_CLK_CTRL__ZCLK_SEL_MASK);
++				data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
++					(1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT);
++				if (orig != data)
++					WREG32_SMC(ixMISC_CLK_CTRL, data);
++
++				orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
++				data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
++				if (orig != data)
++					WREG32_SMC(ixCG_CLKPIN_CNTL, data);
++
++				orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
++				data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;
++				if (orig != data)
++					WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
++
++				orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
++				data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
++				data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
++				if (orig != data)
++					WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
++			}
++		}
++	} else {
++		if (orig != data)
++			WREG32_PCIE(ixPCIE_LC_CNTL, data);
++	}
++
++	orig = data = RREG32_PCIE(ixPCIE_CNTL2);
++	data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
++		PCIE_CNTL2__MST_MEM_LS_EN_MASK |
++		PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
++	if (orig != data)
++		WREG32_PCIE(ixPCIE_CNTL2, data);
++
++	if (!disable_l0s) {
++		data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
++		if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) ==
++				PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) {
++			data = RREG32_PCIE(ixPCIE_LC_STATUS1);
++			if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) &&
++			(data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {
++				orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
++				data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
++				if (orig != data)
++					WREG32_PCIE(ixPCIE_LC_CNTL, data);
++			}
++		}
++	}
++}
++
++static uint32_t cik_get_rev_id(struct amdgpu_device *adev)
++{
++	return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
++		>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
++}
++
++static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 1,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &ci_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 8,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &dce_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 7,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &gfx_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_sdma_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 4,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &uvd_v4_2_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v2_0_ip_funcs,
++	},
++};
++
++static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 1,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &ci_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 8,
++		.minor = 5,
++		.rev = 0,
++		.funcs = &dce_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 7,
++		.minor = 3,
++		.rev = 0,
++		.funcs = &gfx_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_sdma_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 4,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &uvd_v4_2_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v2_0_ip_funcs,
++	},
++};
++
++static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 1,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &kv_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 8,
++		.minor = 3,
++		.rev = 0,
++		.funcs = &dce_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 7,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &gfx_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_sdma_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 4,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &uvd_v4_2_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v2_0_ip_funcs,
++	},
++};
++
++static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 1,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &kv_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 8,
++		.minor = 3,
++		.rev = 0,
++		.funcs = &dce_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 7,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &gfx_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_sdma_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 4,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &uvd_v4_2_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v2_0_ip_funcs,
++	},
++};
++
++static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 1,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &kv_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 8,
++		.minor = 1,
++		.rev = 0,
++		.funcs = &dce_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 7,
++		.minor = 1,
++		.rev = 0,
++		.funcs = &gfx_v7_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cik_sdma_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 4,
++		.minor = 2,
++		.rev = 0,
++		.funcs = &uvd_v4_2_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v2_0_ip_funcs,
++	},
++};
++
++int cik_set_ip_blocks(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		adev->ip_blocks = bonaire_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
++		break;
++	case CHIP_HAWAII:
++		adev->ip_blocks = hawaii_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
++		break;
++	case CHIP_KAVERI:
++		adev->ip_blocks = kaveri_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
++		break;
++	case CHIP_KABINI:
++		adev->ip_blocks = kabini_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
++		break;
++	case CHIP_MULLINS:
++		adev->ip_blocks = mullins_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL);
++	if (adev->ip_block_enabled == NULL)
++		return -ENOMEM;
++
++	return 0;
++}
++
++static const struct amdgpu_asic_funcs cik_asic_funcs =
++{
++	.read_disabled_bios = &cik_read_disabled_bios,
++	.read_register = &cik_read_register,
++	.reset = &cik_asic_reset,
++	.set_vga_state = &cik_vga_set_state,
++	.get_xclk = &cik_get_xclk,
++	.set_uvd_clocks = &cik_set_uvd_clocks,
++	.set_vce_clocks = &cik_set_vce_clocks,
++	.get_cu_info = &gfx_v7_0_get_cu_info,
++	/* these should be moved to their own ip modules */
++	.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
++	.wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,
++};
++
++static int cik_common_early_init(struct amdgpu_device *adev)
++{
++	adev->smc_rreg = &cik_smc_rreg;
++	adev->smc_wreg = &cik_smc_wreg;
++	adev->pcie_rreg = &cik_pcie_rreg;
++	adev->pcie_wreg = &cik_pcie_wreg;
++	adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;
++	adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;
++	adev->didt_rreg = &cik_didt_rreg;
++	adev->didt_wreg = &cik_didt_wreg;
++
++	adev->asic_funcs = &cik_asic_funcs;
++
++	adev->has_uvd = true;
++
++	adev->rev_id = cik_get_rev_id(adev);
++	adev->external_rev_id = 0xFF;
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		adev->cg_flags =
++			AMDGPU_CG_SUPPORT_GFX_MGCG |
++			AMDGPU_CG_SUPPORT_GFX_MGLS |
++			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
++			AMDGPU_CG_SUPPORT_GFX_CGLS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
++			AMDGPU_CG_SUPPORT_GFX_CP_LS |
++			AMDGPU_CG_SUPPORT_MC_LS |
++			AMDGPU_CG_SUPPORT_MC_MGCG |
++			AMDGPU_CG_SUPPORT_SDMA_MGCG |
++			AMDGPU_CG_SUPPORT_SDMA_LS |
++			AMDGPU_CG_SUPPORT_BIF_LS |
++			AMDGPU_CG_SUPPORT_VCE_MGCG |
++			AMDGPU_CG_SUPPORT_UVD_MGCG |
++			AMDGPU_CG_SUPPORT_HDP_LS |
++			AMDGPU_CG_SUPPORT_HDP_MGCG;
++		adev->pg_flags = 0;
++		adev->external_rev_id = adev->rev_id + 0x14;
++		break;
++	case CHIP_HAWAII:
++		adev->cg_flags =
++			AMDGPU_CG_SUPPORT_GFX_MGCG |
++			AMDGPU_CG_SUPPORT_GFX_MGLS |
++			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
++			AMDGPU_CG_SUPPORT_GFX_CGLS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS |
++			AMDGPU_CG_SUPPORT_GFX_CP_LS |
++			AMDGPU_CG_SUPPORT_MC_LS |
++			AMDGPU_CG_SUPPORT_MC_MGCG |
++			AMDGPU_CG_SUPPORT_SDMA_MGCG |
++			AMDGPU_CG_SUPPORT_SDMA_LS |
++			AMDGPU_CG_SUPPORT_BIF_LS |
++			AMDGPU_CG_SUPPORT_VCE_MGCG |
++			AMDGPU_CG_SUPPORT_UVD_MGCG |
++			AMDGPU_CG_SUPPORT_HDP_LS |
++			AMDGPU_CG_SUPPORT_HDP_MGCG;
++		adev->pg_flags = 0;
++		adev->external_rev_id = 0x28;
++		break;
++	case CHIP_KAVERI:
++		adev->cg_flags =
++			AMDGPU_CG_SUPPORT_GFX_MGCG |
++			AMDGPU_CG_SUPPORT_GFX_MGLS |
++			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
++			AMDGPU_CG_SUPPORT_GFX_CGLS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
++			AMDGPU_CG_SUPPORT_GFX_CP_LS |
++			AMDGPU_CG_SUPPORT_SDMA_MGCG |
++			AMDGPU_CG_SUPPORT_SDMA_LS |
++			AMDGPU_CG_SUPPORT_BIF_LS |
++			AMDGPU_CG_SUPPORT_VCE_MGCG |
++			AMDGPU_CG_SUPPORT_UVD_MGCG |
++			AMDGPU_CG_SUPPORT_HDP_LS |
++			AMDGPU_CG_SUPPORT_HDP_MGCG;
++		adev->pg_flags =
++			/*AMDGPU_PG_SUPPORT_GFX_PG |
++			  AMDGPU_PG_SUPPORT_GFX_SMG |
++			  AMDGPU_PG_SUPPORT_GFX_DMG |*/
++			AMDGPU_PG_SUPPORT_UVD |
++			/*AMDGPU_PG_SUPPORT_VCE |
++			  AMDGPU_PG_SUPPORT_CP |
++			  AMDGPU_PG_SUPPORT_GDS |
++			  AMDGPU_PG_SUPPORT_RLC_SMU_HS |
++			  AMDGPU_PG_SUPPORT_ACP |
++			  AMDGPU_PG_SUPPORT_SAMU |*/
++			0;
++		if (adev->pdev->device == 0x1312 ||
++			adev->pdev->device == 0x1316 ||
++			adev->pdev->device == 0x1317)
++			adev->external_rev_id = 0x41;
++		else
++			adev->external_rev_id = 0x1;
++		break;
++	case CHIP_KABINI:
++	case CHIP_MULLINS:
++		adev->cg_flags =
++			AMDGPU_CG_SUPPORT_GFX_MGCG |
++			AMDGPU_CG_SUPPORT_GFX_MGLS |
++			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
++			AMDGPU_CG_SUPPORT_GFX_CGLS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS |
++			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
++			AMDGPU_CG_SUPPORT_GFX_CP_LS |
++			AMDGPU_CG_SUPPORT_SDMA_MGCG |
++			AMDGPU_CG_SUPPORT_SDMA_LS |
++			AMDGPU_CG_SUPPORT_BIF_LS |
++			AMDGPU_CG_SUPPORT_VCE_MGCG |
++			AMDGPU_CG_SUPPORT_UVD_MGCG |
++			AMDGPU_CG_SUPPORT_HDP_LS |
++			AMDGPU_CG_SUPPORT_HDP_MGCG;
++		adev->pg_flags =
++			/*AMDGPU_PG_SUPPORT_GFX_PG |
++			  AMDGPU_PG_SUPPORT_GFX_SMG | */
++			AMDGPU_PG_SUPPORT_UVD |
++			/*AMDGPU_PG_SUPPORT_VCE |
++			  AMDGPU_PG_SUPPORT_CP |
++			  AMDGPU_PG_SUPPORT_GDS |
++			  AMDGPU_PG_SUPPORT_RLC_SMU_HS |
++			  AMDGPU_PG_SUPPORT_SAMU |*/
++			0;
++		if (adev->asic_type == CHIP_KABINI) {
++			if (adev->rev_id == 0)
++				adev->external_rev_id = 0x81;
++			else if (adev->rev_id == 1)
++				adev->external_rev_id = 0x82;
++			else if (adev->rev_id == 2)
++				adev->external_rev_id = 0x85;
++		} else
++			adev->external_rev_id = adev->rev_id + 0xa1;
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int cik_common_sw_init(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int cik_common_sw_fini(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int cik_common_hw_init(struct amdgpu_device *adev)
++{
++	/* move the golden regs per IP block */
++	cik_init_golden_registers(adev);
++	/* enable pcie gen2/3 link */
++	cik_pcie_gen3_enable(adev);
++	/* enable aspm */
++	cik_program_aspm(adev);
++
++	return 0;
++}
++
++static int cik_common_hw_fini(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int cik_common_suspend(struct amdgpu_device *adev)
++{
++	return cik_common_hw_fini(adev);
++}
++
++static int cik_common_resume(struct amdgpu_device *adev)
++{
++	return cik_common_hw_init(adev);
++}
++
++static bool cik_common_is_idle(struct amdgpu_device *adev)
++{
++	return true;
++}
++
++static int cik_common_wait_for_idle(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static void cik_common_print_status(struct amdgpu_device *adev)
++{
++
++}
++
++static int cik_common_soft_reset(struct amdgpu_device *adev)
++{
++	/* XXX hard reset?? */
++	return 0;
++}
++
++static int cik_common_set_clockgating_state(struct amdgpu_device *adev,
++					    enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int cik_common_set_powergating_state(struct amdgpu_device *adev,
++					    enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs cik_common_ip_funcs = {
++	.early_init = cik_common_early_init,
++	.late_init = NULL,
++	.sw_init = cik_common_sw_init,
++	.sw_fini = cik_common_sw_fini,
++	.hw_init = cik_common_hw_init,
++	.hw_fini = cik_common_hw_fini,
++	.suspend = cik_common_suspend,
++	.resume = cik_common_resume,
++	.is_idle = cik_common_is_idle,
++	.wait_for_idle = cik_common_wait_for_idle,
++	.soft_reset = cik_common_soft_reset,
++	.print_status = cik_common_print_status,
++	.set_clockgating_state = cik_common_set_clockgating_state,
++	.set_powergating_state = cik_common_set_powergating_state,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
+new file mode 100644
+index 0000000..967d630
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __CIK_H__
++#define __CIK_H__
++
++extern const struct amdgpu_ip_funcs cik_common_ip_funcs;
++
++void cik_srbm_select(struct amdgpu_device *adev,
++		     u32 me, u32 pipe, u32 queue, u32 vmid);
++int cik_set_ip_blocks(struct amdgpu_device *adev);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+new file mode 100644
+index 0000000..35d8efd
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+@@ -0,0 +1,30 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __CIK_DPM_H__
++#define __CIK_DPM_H__
++
++extern const struct amdgpu_ip_funcs ci_dpm_ip_funcs;
++extern const struct amdgpu_ip_funcs kv_dpm_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+new file mode 100644
+index 0000000..81e8bbab
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+@@ -0,0 +1,453 @@
++/*
++ * Copyright 2012 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++#include "cikd.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++/*
++ * Interrupts
++ * Starting with r6xx, interrupts are handled via a ring buffer.
++ * Ring buffers are areas of GPU accessible memory that the GPU
++ * writes interrupt vectors into and the host reads vectors out of.
++ * There is a rptr (read pointer) that determines where the
++ * host is currently reading, and a wptr (write pointer)
++ * which determines where the GPU has written.  When the
++ * pointers are equal, the ring is idle.  When the GPU
++ * writes vectors to the ring buffer, it increments the
++ * wptr.  When there is an interrupt, the host then starts
++ * fetching commands and processing them until the pointers are
++ * equal again at which point it updates the rptr.
++ */
++
++static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
++
++/**
++ * cik_ih_enable_interrupts - Enable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Enable the interrupt ring buffer (CIK).
++ */
++static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_cntl = RREG32(mmIH_CNTL);
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++
++	ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
++	ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
++	WREG32(mmIH_CNTL, ih_cntl);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	adev->irq.ih.enabled = true;
++}
++
++/**
++ * cik_ih_disable_interrupts - Disable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable the interrupt ring buffer (CIK).
++ */
++static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++	u32 ih_cntl = RREG32(mmIH_CNTL);
++
++	ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
++	ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	WREG32(mmIH_CNTL, ih_cntl);
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++	adev->irq.ih.enabled = false;
++	adev->irq.ih.rptr = 0;
++}
++
++/**
++ * cik_ih_irq_init - init and enable the interrupt ring
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate a ring buffer for the interrupt controller,
++ * enable the RLC, disable interrupts, enable the IH
++ * ring buffer and enable it (CIK).
++ * Called at device load and reume.
++ * Returns 0 for success, errors for failure.
++ */
++static int cik_ih_irq_init(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	int rb_bufsz;
++	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
++	u64 wptr_off;
++
++	/* disable irqs */
++	cik_ih_disable_interrupts(adev);
++
++	/* setup interrupt control */
++	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
++	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
++	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
++	 */
++	interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
++	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
++	interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
++	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
++
++	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
++	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
++
++	ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
++		      IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
++		      (rb_bufsz << 1));
++
++	ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
++
++	/* set the writeback address whether it's enabled or not */
++	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
++	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
++	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
++
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++
++	/* Default settings for IH_CNTL (disabled at first) */
++	ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
++		(0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
++		(0 << IH_CNTL__MC_VMID__SHIFT);
++	/* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
++	if (adev->irq.msi_enabled)
++		ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
++	WREG32(mmIH_CNTL, ih_cntl);
++
++	pci_set_master(adev->pdev);
++
++	/* enable irqs */
++	cik_ih_enable_interrupts(adev);
++
++	return ret;
++}
++
++/**
++ * cik_ih_irq_disable - disable interrupts
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable interrupts on the hw (CIK).
++ */
++static void cik_ih_irq_disable(struct amdgpu_device *adev)
++{
++	cik_ih_disable_interrupts(adev);
++	/* Wait and acknowledge irq */
++	mdelay(1);
++}
++
++/**
++ * cik_ih_get_wptr - get the IH ring buffer wptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Get the IH ring buffer wptr from either the register
++ * or the writeback memory buffer (CIK).  Also check for
++ * ring buffer overflow and deal with it.
++ * Used by cik_irq_process().
++ * Returns the value of the wptr.
++ */
++static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
++{
++	u32 wptr, tmp;
++
++	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
++
++	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
++		wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
++		/* When a ring buffer overflow happen start parsing interrupt
++		 * from the last not overwritten vector (wptr + 16). Hopefully
++		 * this should allow us to catchup.
++		 */
++		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
++			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
++		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
++		tmp = RREG32(mmIH_RB_CNTL);
++		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
++		WREG32(mmIH_RB_CNTL, tmp);
++	}
++	return (wptr & adev->irq.ih.ptr_mask);
++}
++
++/*        CIK IV Ring
++ * Each IV ring entry is 128 bits:
++ * [7:0]    - interrupt source id
++ * [31:8]   - reserved
++ * [59:32]  - interrupt source data
++ * [63:60]  - reserved
++ * [71:64]  - RINGID
++ *            CP:
++ *            ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
++ *            QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
++ *                     - for gfx, hw shader state (0=PS...5=LS, 6=CS)
++ *            ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
++ *            PIPE_ID - ME0 0=3D
++ *                    - ME1&2 compute dispatcher (4 pipes each)
++ *            SDMA:
++ *            INSTANCE_ID [1:0], QUEUE_ID[1:0]
++ *            INSTANCE_ID - 0 = sdma0, 1 = sdma1
++ *            QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
++ * [79:72]  - VMID
++ * [95:80]  - PASID
++ * [127:96] - reserved
++ */
++
++ /**
++ * cik_ih_decode_iv - decode an interrupt vector
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Decodes the interrupt vector at the current rptr
++ * position and also advance the position.
++ */
++static void cik_ih_decode_iv(struct amdgpu_device *adev,
++			     struct amdgpu_iv_entry *entry)
++{
++	/* wptr/rptr are in bytes! */
++	u32 ring_index = adev->irq.ih.rptr >> 2;
++	uint32_t dw[4];
++	
++	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
++	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
++	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
++	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
++
++	entry->src_id = dw[0] & 0xff;
++	entry->src_data = dw[1] & 0xfffffff;
++	entry->ring_id = dw[2] & 0xff;
++	entry->vm_id = (dw[2] >> 8) & 0xff;
++	entry->pas_id = (dw[2] >> 16) & 0xffff;
++
++	/* wptr/rptr are in bytes! */
++	adev->irq.ih.rptr += 16;
++}
++
++/**
++ * cik_ih_set_rptr - set the IH ring buffer rptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set the IH ring buffer rptr.
++ */
++static void cik_ih_set_rptr(struct amdgpu_device *adev)
++{
++	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
++}
++
++static int cik_ih_early_init(struct amdgpu_device *adev)
++{
++	cik_ih_set_interrupt_funcs(adev);
++
++	return 0;
++}
++
++static int cik_ih_sw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_init(adev);
++
++	return r;
++}
++
++static int cik_ih_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_irq_fini(adev);
++	amdgpu_ih_ring_fini(adev);
++
++	return 0;
++}
++
++static int cik_ih_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = cik_ih_irq_init(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static int cik_ih_hw_fini(struct amdgpu_device *adev)
++{
++	cik_ih_irq_disable(adev);
++
++	return 0;
++}
++
++static int cik_ih_suspend(struct amdgpu_device *adev)
++{
++	return cik_ih_hw_fini(adev);
++}
++
++static int cik_ih_resume(struct amdgpu_device *adev)
++{
++	return cik_ih_hw_init(adev);
++}
++
++static bool cik_ih_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		return false;
++
++	return true;
++}
++
++static int cik_ih_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void cik_ih_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "CIK IH registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL));
++	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL2));
++	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
++		 RREG32(mmIH_CNTL));
++	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
++		 RREG32(mmIH_RB_CNTL));
++	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
++		 RREG32(mmIH_RB_BASE));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_LO));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_HI));
++	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
++		 RREG32(mmIH_RB_RPTR));
++	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR));
++}
++
++static int cik_ih_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
++
++	if (srbm_soft_reset) {
++		cik_ih_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		cik_ih_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int cik_ih_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int cik_ih_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs cik_ih_ip_funcs = {
++	.early_init = cik_ih_early_init,
++	.late_init = NULL,
++	.sw_init = cik_ih_sw_init,
++	.sw_fini = cik_ih_sw_fini,
++	.hw_init = cik_ih_hw_init,
++	.hw_fini = cik_ih_hw_fini,
++	.suspend = cik_ih_suspend,
++	.resume = cik_ih_resume,
++	.is_idle = cik_ih_is_idle,
++	.wait_for_idle = cik_ih_wait_for_idle,
++	.soft_reset = cik_ih_soft_reset,
++	.print_status = cik_ih_print_status,
++	.set_clockgating_state = cik_ih_set_clockgating_state,
++	.set_powergating_state = cik_ih_set_powergating_state,
++};
++
++static const struct amdgpu_ih_funcs cik_ih_funcs = {
++	.get_wptr = cik_ih_get_wptr,
++	.decode_iv = cik_ih_decode_iv,
++	.set_rptr = cik_ih_set_rptr
++};
++
++static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
++{
++	if (adev->irq.ih_funcs == NULL)
++		adev->irq.ih_funcs = &cik_ih_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
+new file mode 100644
+index 0000000..f701625
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __CIK_IH_H__
++#define __CIK_IH_H__
++
++extern const struct amdgpu_ip_funcs cik_ih_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+new file mode 100644
+index 0000000..ae2bb26
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -0,0 +1,1422 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_ucode.h"
++#include "amdgpu_trace.h"
++#include "cikd.h"
++#include "cik.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "gca/gfx_7_2_d.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
++{
++	SDMA0_REGISTER_OFFSET,
++	SDMA1_REGISTER_OFFSET
++};
++
++static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
++static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
++static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
++static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
++
++MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
++MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
++MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
++MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
++MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
++MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
++MODULE_FIRMWARE("radeon/kabini_sdma.bin");
++MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
++MODULE_FIRMWARE("radeon/mullins_sdma.bin");
++MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
++
++u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
++
++/*
++ * sDMA - System DMA
++ * Starting with CIK, the GPU has new asynchronous
++ * DMA engines.  These engines are used for compute
++ * and gfx.  There are two DMA engines (SDMA0, SDMA1)
++ * and each one supports 1 ring buffer used for gfx
++ * and 2 queues used for compute.
++ *
++ * The programming model is very similar to the CP
++ * (ring buffer, IBs, etc.), but sDMA has it's own
++ * packet format that is different from the PM4 format
++ * used by the CP. sDMA supports copying data, writing
++ * embedded data, solid fills, and a number of other
++ * things.  It also has support for tiling/detiling of
++ * buffers.
++ */
++
++/**
++ * cik_sdma_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int cik_sdma_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err, i;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		chip_name = "bonaire";
++		break;
++	case CHIP_HAWAII:
++		chip_name = "hawaii";
++		break;
++	case CHIP_KAVERI:
++		chip_name = "kaveri";
++		break;
++	case CHIP_KABINI:
++		chip_name = "kabini";
++		break;
++	case CHIP_MULLINS:
++		chip_name = "mullins";
++		break;
++	default: BUG();
++	}
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		if (i == 0)
++			snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
++		else
++			snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
++		err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
++		if (err)
++			goto out;
++		err = amdgpu_ucode_validate(adev->sdma[i].fw);
++	}
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "cik_sdma: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++			release_firmware(adev->sdma[i].fw);
++			adev->sdma[i].fw = NULL;
++		}
++	}
++	return err;
++}
++
++/**
++ * cik_sdma_ring_get_rptr - get the current read pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Get the current rptr from the hardware (CIK+).
++ */
++static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	u32 rptr;
++
++	rptr = ring->adev->wb.wb[ring->rptr_offs];
++
++	return (rptr & 0x3fffc) >> 2;
++}
++
++/**
++ * cik_sdma_ring_get_wptr - get the current write pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Get the current wptr from the hardware (CIK+).
++ */
++static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
++
++	return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
++}
++
++/**
++ * cik_sdma_ring_set_wptr - commit the write pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Write the wptr back to the hardware (CIK+).
++ */
++static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
++
++	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
++}
++
++static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *);
++
++/**
++ * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
++ *
++ * @ring: amdgpu ring pointer
++ * @ib: IB object to schedule
++ *
++ * Schedule an IB in the DMA ring (CIK).
++ */
++static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
++			   struct amdgpu_ib *ib)
++{
++	u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
++	u32 next_rptr = ring->wptr + 5;
++
++	if (ib->flush_hdp_writefifo)
++		next_rptr += 6;
++
++	while ((next_rptr & 7) != 4)
++		next_rptr++;
++
++	next_rptr += 4;
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
++	amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 1); /* number of DWs to follow */
++	amdgpu_ring_write(ring, next_rptr);
++
++	if (ib->flush_hdp_writefifo) {
++		/* flush HDP */
++		cik_sdma_hdp_flush_ring_emit(ring);
++	}
++
++	/* IB packet must end on a 8 DW boundary */
++	while ((ring->wptr & 7) != 4)
++		amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
++	amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, ib->length_dw);
++
++}
++
++/**
++ * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Emit an hdp flush packet on the requested DMA ring.
++ */
++static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *ring)
++{
++	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
++			  SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
++	u32 ref_and_mask;
++
++	if (ring == &ring->adev->sdma[0].ring)
++		ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
++	else
++		ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
++	amdgpu_ring_write(ring, ref_and_mask); /* reference */
++	amdgpu_ring_write(ring, ref_and_mask); /* mask */
++	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
++}
++
++/**
++ * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
++ *
++ * @ring: amdgpu ring pointer
++ * @fence: amdgpu fence object
++ *
++ * Add a DMA fence packet to the ring to write
++ * the fence seq number and DMA trap packet to generate
++ * an interrupt if needed (CIK).
++ */
++static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				     bool write64bit)
++{
++	/* write the fence */
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
++	amdgpu_ring_write(ring, lower_32_bits(addr));
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++
++	/* optionally write high bits as well */
++	if (write64bit) {
++		addr += 4;
++		amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
++		amdgpu_ring_write(ring, lower_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(seq));
++	}
++
++	/* generate an interrupt */
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
++}
++
++/**
++ * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @semaphore: amdgpu semaphore object
++ * @emit_wait: wait or signal semaphore
++ *
++ * Add a DMA semaphore packet to the ring wait on or signal
++ * other rings (CIK).
++ */
++static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
++					 struct amdgpu_semaphore *semaphore,
++					 bool emit_wait)
++{
++	u64 addr = semaphore->gpu_addr;
++	u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
++	amdgpu_ring_write(ring, addr & 0xfffffff8);
++	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
++
++	return true;
++}
++
++/**
++ * cik_sdma_gfx_stop - stop the gfx async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the gfx async dma ring buffers (CIK).
++ */
++static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
++	struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
++	u32 rb_cntl;
++	int i;
++
++	if ((adev->mman.buffer_funcs_ring == sdma0) ||
++	    (adev->mman.buffer_funcs_ring == sdma1))
++		amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
++		rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
++	}
++	sdma0->ready = false;
++	sdma1->ready = false;
++}
++
++/**
++ * cik_sdma_rlc_stop - stop the compute async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the compute async dma queues (CIK).
++ */
++static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++}
++
++/**
++ * cik_sdma_enable - stop the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ * @enable: enable/disable the DMA MEs.
++ *
++ * Halt or unhalt the async dma engines (CIK).
++ */
++static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
++{
++	u32 me_cntl;
++	int i;
++
++	if (enable == false) {
++		cik_sdma_gfx_stop(adev);
++		cik_sdma_rlc_stop(adev);
++	}
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
++		if (enable)
++			me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
++		else
++			me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
++		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
++	}
++}
++
++/**
++ * cik_sdma_gfx_resume - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the gfx DMA ring buffers and enable them (CIK).
++ * Returns 0 for success, error for failure.
++ */
++static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	u32 rb_cntl, ib_cntl;
++	u32 rb_bufsz;
++	u32 wb_offset;
++	int i, j, r;
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		ring = &adev->sdma[i].ring;
++		wb_offset = (ring->rptr_offs * 4);
++
++		mutex_lock(&adev->srbm_mutex);
++		for (j = 0; j < 16; j++) {
++			cik_srbm_select(adev, 0, 0, 0, j);
++			/* SDMA GFX */
++			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
++			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
++			/* XXX SDMA RLC - todo */
++		}
++		cik_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++
++		WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
++		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
++
++		/* Set ring buffer size in dwords */
++		rb_bufsz = order_base_2(ring->ring_size / 4);
++		rb_cntl = rb_bufsz << 1;
++#ifdef __BIG_ENDIAN
++		rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
++#endif
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++
++		/* Initialize the ring buffer's read and write pointers */
++		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
++
++		/* set the wb address whether it's enabled or not */
++		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
++		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
++		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
++		       ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
++
++		rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
++
++		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
++		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
++
++		ring->wptr = 0;
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
++
++		/* enable DMA RB */
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
++		       rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
++
++		ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
++#ifdef __BIG_ENDIAN
++		ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
++#endif
++		/* enable DMA IBs */
++		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
++
++		ring->ready = true;
++
++		r = amdgpu_ring_test_ring(ring);
++		if (r) {
++			ring->ready = false;
++			return r;
++		}
++
++		if (adev->mman.buffer_funcs_ring == ring)
++			amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
++	}
++
++	return 0;
++}
++
++/**
++ * cik_sdma_rlc_resume - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the compute DMA queues and enable them (CIK).
++ * Returns 0 for success, error for failure.
++ */
++static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return 0;
++}
++
++/**
++ * cik_sdma_load_microcode - load the sDMA ME ucode
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Loads the sDMA0/1 ucode.
++ * Returns 0 for success, -EINVAL if the ucode is not available.
++ */
++static int cik_sdma_load_microcode(struct amdgpu_device *adev)
++{
++	const struct sdma_firmware_header_v1_0 *hdr;
++	const __le32 *fw_data;
++	u32 fw_size;
++	int i, j;
++
++	if (!adev->sdma[0].fw || !adev->sdma[1].fw)
++		return -EINVAL;
++
++	/* halt the MEs */
++	cik_sdma_enable(adev, false);
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
++		amdgpu_ucode_print_sdma_hdr(&hdr->header);
++		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
++		fw_data = (const __le32 *)
++			(adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
++		for (j = 0; j < fw_size; j++)
++			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
++		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
++	}
++
++	return 0;
++}
++
++/**
++ * cik_sdma_start - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the DMA engines and enable them (CIK).
++ * Returns 0 for success, error for failure.
++ */
++static int cik_sdma_start(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = cik_sdma_load_microcode(adev);
++	if (r)
++		return r;
++
++	/* unhalt the MEs */
++	cik_sdma_enable(adev, true);
++
++	/* start the gfx rings and rlc compute queues */
++	r = cik_sdma_gfx_resume(adev);
++	if (r)
++		return r;
++	r = cik_sdma_rlc_resume(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++/**
++ * cik_sdma_ring_test_ring - simple async dma engine test
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Test the DMA engine by writing using it to write an
++ * value to memory. (CIK).
++ * Returns 0 for success, error for failure.
++ */
++static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	unsigned i;
++	unsigned index;
++	int r;
++	u32 tmp;
++	u64 gpu_addr;
++
++	r = amdgpu_wb_get(adev, &index);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
++		return r;
++	}
++
++	gpu_addr = adev->wb.gpu_addr + (index * 4);
++	tmp = 0xCAFEDEAD;
++	adev->wb.wb[index] = cpu_to_le32(tmp);
++
++	r = amdgpu_ring_lock(ring, 5);
++	if (r) {
++		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
++		amdgpu_wb_free(adev, index);
++		return r;
++	}
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
++	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
++	amdgpu_ring_write(ring, 1); /* number of DWs to follow */
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = le32_to_cpu(adev->wb.wb[index]);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
++			  ring->idx, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_wb_free(adev, index);
++
++	return r;
++}
++
++/**
++ * cik_sdma_ring_test_ib - test an IB on the DMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Test a simple IB in the DMA ring (CIK).
++ * Returns 0 on success, error on failure.
++ */
++static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_ib ib;
++	unsigned i;
++	unsigned index;
++	int r;
++	u32 tmp = 0;
++	u64 gpu_addr;
++
++	r = amdgpu_wb_get(adev, &index);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
++		return r;
++	}
++
++	gpu_addr = adev->wb.gpu_addr + (index * 4);
++	tmp = 0xCAFEDEAD;
++	adev->wb.wb[index] = cpu_to_le32(tmp);
++
++	r = amdgpu_ib_get(ring, NULL, 256, &ib);
++	if (r) {
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		return r;
++	}
++
++	ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
++	ib.ptr[1] = lower_32_bits(gpu_addr);
++	ib.ptr[2] = upper_32_bits(gpu_addr);
++	ib.ptr[3] = 1;
++	ib.ptr[4] = 0xDEADBEEF;
++	ib.length_dw = 5;
++
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++		return r;
++	}
++	r = amdgpu_fence_wait(ib.fence, false);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		return r;
++	}
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = le32_to_cpu(adev->wb.wb[index]);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
++			 ib.fence->ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
++		r = -EINVAL;
++	}
++	amdgpu_ib_free(adev, &ib);
++	amdgpu_wb_free(adev, index);
++	return r;
++}
++
++/**
++ * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @src: src addr to copy from
++ * @count: number of page entries to update
++ *
++ * Update PTEs by copying them from the GART using sDMA (CIK).
++ */
++static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
++				 uint64_t pe, uint64_t src,
++				 unsigned count)
++{
++	while (count) {
++		unsigned bytes = count * 8;
++		if (bytes > 0x1FFFF8)
++			bytes = 0x1FFFF8;
++
++		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
++			SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
++		ib->ptr[ib->length_dw++] = bytes;
++		ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
++		ib->ptr[ib->length_dw++] = lower_32_bits(src);
++		ib->ptr[ib->length_dw++] = upper_32_bits(src);
++		ib->ptr[ib->length_dw++] = lower_32_bits(pe);
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++
++		pe += bytes;
++		src += bytes;
++		count -= bytes / 8;
++	}
++}
++
++/**
++ * cik_sdma_vm_write_pages - update PTEs by writing them manually
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: access flags
++ *
++ * Update PTEs by writing them manually using sDMA (CIK).
++ */
++static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
++				  uint64_t pe,
++				  uint64_t addr, unsigned count,
++				  uint32_t incr, uint32_t flags)
++{
++	uint64_t value;
++	unsigned ndw;
++
++	while (count) {
++		ndw = count * 2;
++		if (ndw > 0xFFFFE)
++			ndw = 0xFFFFE;
++
++		/* for non-physically contiguous pages (system) */
++		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
++			SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
++		ib->ptr[ib->length_dw++] = pe;
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++		ib->ptr[ib->length_dw++] = ndw;
++		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
++			if (flags & AMDGPU_PTE_SYSTEM) {
++				value = amdgpu_vm_map_gart(ib->ring->adev, addr);
++				value &= 0xFFFFFFFFFFFFF000ULL;
++			} else if (flags & AMDGPU_PTE_VALID) {
++				value = addr;
++			} else {
++				value = 0;
++			}
++			addr += incr;
++			value |= flags;
++			ib->ptr[ib->length_dw++] = value;
++			ib->ptr[ib->length_dw++] = upper_32_bits(value);
++		}
++	}
++}
++
++/**
++ * cik_sdma_vm_set_pages - update the page tables using sDMA
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: access flags
++ *
++ * Update the page tables using sDMA (CIK).
++ */
++static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
++				    uint64_t pe,
++				    uint64_t addr, unsigned count,
++				    uint32_t incr, uint32_t flags)
++{
++	uint64_t value;
++	unsigned ndw;
++
++	while (count) {
++		ndw = count;
++		if (ndw > 0x7FFFF)
++			ndw = 0x7FFFF;
++
++		if (flags & AMDGPU_PTE_VALID)
++			value = addr;
++		else
++			value = 0;
++
++		/* for physically contiguous pages (vram) */
++		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
++		ib->ptr[ib->length_dw++] = pe; /* dst addr */
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++		ib->ptr[ib->length_dw++] = flags; /* mask */
++		ib->ptr[ib->length_dw++] = 0;
++		ib->ptr[ib->length_dw++] = value; /* value */
++		ib->ptr[ib->length_dw++] = upper_32_bits(value);
++		ib->ptr[ib->length_dw++] = incr; /* increment size */
++		ib->ptr[ib->length_dw++] = 0;
++		ib->ptr[ib->length_dw++] = ndw; /* number of entries */
++
++		pe += ndw * 8;
++		addr += ndw * incr;
++		count -= ndw;
++	}
++}
++
++/**
++ * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
++ *
++ * @ib: indirect buffer to fill with padding
++ *
++ */
++static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
++{
++	while (ib->length_dw & 0x7)
++		ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
++}
++
++/**
++ * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
++ *
++ * @ring: amdgpu_ring pointer
++ * @vm: amdgpu_vm pointer
++ *
++ * Update the page table base and flush the VM TLB
++ * using sDMA (CIK).
++ */
++static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
++					unsigned vm_id, uint64_t pd_addr)
++{
++	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
++			  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	if (vm_id < 8) {
++		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
++	} else {
++		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
++	}
++	amdgpu_ring_write(ring, pd_addr >> 12);
++
++	/* update SH_MEM_* regs */
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, VMID(vm_id));
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmSH_MEM_BASES);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
++	amdgpu_ring_write(ring, 1);
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, VMID(0));
++
++	/* flush TLB */
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 1 << vm_id);
++
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0); /* reference */
++	amdgpu_ring_write(ring, 0); /* mask */
++	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
++}
++
++static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
++				 bool enable)
++{
++	u32 orig, data;
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
++		WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
++		WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
++	} else {
++		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
++		data |= 0xff000000;
++		if (data != orig)
++			WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
++
++		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
++		data |= 0xff000000;
++		if (data != orig)
++			WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
++	}
++}
++
++static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
++				 bool enable)
++{
++	u32 orig, data;
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
++		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
++		data |= 0x100;
++		if (orig != data)
++			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
++
++		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
++		data |= 0x100;
++		if (orig != data)
++			WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
++	} else {
++		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
++		data &= ~0x100;
++		if (orig != data)
++			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
++
++		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
++		data &= ~0x100;
++		if (orig != data)
++			WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
++	}
++}
++
++static int cik_sdma_early_init(struct amdgpu_device *adev)
++{
++	cik_sdma_set_ring_funcs(adev);
++	cik_sdma_set_irq_funcs(adev);
++	cik_sdma_set_buffer_funcs(adev);
++	cik_sdma_set_vm_pte_funcs(adev);
++
++	return 0;
++}
++
++static int cik_sdma_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	r = cik_sdma_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load sdma firmware!\n");
++		return r;
++	}
++
++	/* SDMA trap event */
++	r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
++	if (r)
++		return r;
++
++	/* SDMA Privileged inst */
++	r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
++	if (r)
++		return r;
++
++	/* SDMA Privileged inst */
++	r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
++	if (r)
++		return r;
++
++	ring = &adev->sdma[0].ring;
++	ring->ring_obj = NULL;
++
++	ring = &adev->sdma[1].ring;
++	ring->ring_obj = NULL;
++
++	ring = &adev->sdma[0].ring;
++	sprintf(ring->name, "sdma0");
++	r = amdgpu_ring_init(adev, ring, 256 * 1024,
++			     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
++			     &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
++			     AMDGPU_RING_TYPE_SDMA);
++	if (r)
++		return r;
++
++	ring = &adev->sdma[1].ring;
++	sprintf(ring->name, "sdma1");
++	r = amdgpu_ring_init(adev, ring, 256 * 1024,
++			     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
++			     &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
++			     AMDGPU_RING_TYPE_SDMA);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int cik_sdma_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_ring_fini(&adev->sdma[0].ring);
++	amdgpu_ring_fini(&adev->sdma[1].ring);
++
++	return 0;
++}
++
++static int cik_sdma_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = cik_sdma_start(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int cik_sdma_hw_fini(struct amdgpu_device *adev)
++{
++	cik_sdma_enable(adev, false);
++
++	return 0;
++}
++
++static int cik_sdma_suspend(struct amdgpu_device *adev)
++{
++
++	return cik_sdma_hw_fini(adev);
++}
++
++static int cik_sdma_resume(struct amdgpu_device *adev)
++{
++
++	return cik_sdma_hw_init(adev);
++}
++
++static bool cik_sdma_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS2);
++
++	if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
++				SRBM_STATUS2__SDMA1_BUSY_MASK))
++	    return false;
++
++	return true;
++}
++
++static int cik_sdma_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
++				SRBM_STATUS2__SDMA1_BUSY_MASK);
++
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void cik_sdma_print_status(struct amdgpu_device *adev)
++{
++	int i, j;
++
++	dev_info(adev->dev, "CIK SDMA registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		 RREG32(mmSRBM_STATUS2));
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
++			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
++		mutex_lock(&adev->srbm_mutex);
++		for (j = 0; j < 16; j++) {
++			cik_srbm_select(adev, 0, 0, 0, j);
++			dev_info(adev->dev, "  VM %d:\n", j);
++			dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
++				 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
++			dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
++				 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
++		}
++		cik_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++	}
++}
++
++static int cik_sdma_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS2);
++
++	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
++		/* sdma0 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++		tmp |= SDMA0_F32_CNTL__HALT_MASK;
++		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
++	}
++	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
++		/* sdma1 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++		tmp |= SDMA0_F32_CNTL__HALT_MASK;
++		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
++	}
++
++	if (srbm_soft_reset) {
++		cik_sdma_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		cik_sdma_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
++				       struct amdgpu_irq_src *src,
++				       unsigned type,
++				       enum amdgpu_interrupt_state state)
++{
++	u32 sdma_cntl;
++
++	switch (type) {
++	case AMDGPU_SDMA_IRQ_TRAP0:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
++			sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
++			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
++			sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
++			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
++			break;
++		default:
++			break;
++		}
++		break;
++	case AMDGPU_SDMA_IRQ_TRAP1:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
++			sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
++			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
++			sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
++			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
++			break;
++		default:
++			break;
++		}
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
++				     struct amdgpu_irq_src *source,
++				     struct amdgpu_iv_entry *entry)
++{
++	u8 instance_id, queue_id;
++
++	instance_id = (entry->ring_id & 0x3) >> 0;
++	queue_id = (entry->ring_id & 0xc) >> 2;
++	DRM_DEBUG("IH: SDMA trap\n");
++	switch (instance_id) {
++	case 0:
++		switch (queue_id) {
++		case 0:
++			amdgpu_fence_process(&adev->sdma[0].ring);
++			break;
++		case 1:
++			/* XXX compute */
++			break;
++		case 2:
++			/* XXX compute */
++			break;
++		}
++		break;
++	case 1:
++		switch (queue_id) {
++		case 0:
++			amdgpu_fence_process(&adev->sdma[1].ring);
++			break;
++		case 1:
++			/* XXX compute */
++			break;
++		case 2:
++			/* XXX compute */
++			break;
++		}
++		break;
++	}
++
++	return 0;
++}
++
++static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
++					     struct amdgpu_irq_src *source,
++					     struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal instruction in SDMA command stream\n");
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	bool gate = false;
++
++	if (state == AMDGPU_CG_STATE_GATE)
++		gate = true;
++
++	cik_enable_sdma_mgcg(adev, gate);
++	cik_enable_sdma_mgls(adev, gate);
++
++	return 0;
++}
++
++static int cik_sdma_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs cik_sdma_ip_funcs = {
++	.early_init = cik_sdma_early_init,
++	.late_init = NULL,
++	.sw_init = cik_sdma_sw_init,
++	.sw_fini = cik_sdma_sw_fini,
++	.hw_init = cik_sdma_hw_init,
++	.hw_fini = cik_sdma_hw_fini,
++	.suspend = cik_sdma_suspend,
++	.resume = cik_sdma_resume,
++	.is_idle = cik_sdma_is_idle,
++	.wait_for_idle = cik_sdma_wait_for_idle,
++	.soft_reset = cik_sdma_soft_reset,
++	.print_status = cik_sdma_print_status,
++	.set_clockgating_state = cik_sdma_set_clockgating_state,
++	.set_powergating_state = cik_sdma_set_powergating_state,
++};
++
++/**
++ * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Check if the async DMA engine is locked up (CIK).
++ * Returns true if the engine appears to be locked up, false if not.
++ */
++static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
++{
++
++	if (cik_sdma_is_idle(ring->adev)) {
++		amdgpu_ring_lockup_update(ring);
++		return false;
++	}
++	return amdgpu_ring_test_lockup(ring);
++}
++
++static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
++	.get_rptr = cik_sdma_ring_get_rptr,
++	.get_wptr = cik_sdma_ring_get_wptr,
++	.set_wptr = cik_sdma_ring_set_wptr,
++	.parse_cs = NULL,
++	.emit_ib = cik_sdma_ring_emit_ib,
++	.emit_fence = cik_sdma_ring_emit_fence,
++	.emit_semaphore = cik_sdma_ring_emit_semaphore,
++	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
++	.test_ring = cik_sdma_ring_test_ring,
++	.test_ib = cik_sdma_ring_test_ib,
++	.is_lockup = cik_sdma_ring_is_lockup,
++};
++
++static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs;
++	adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
++	.set = cik_sdma_set_trap_irq_state,
++	.process = cik_sdma_process_trap_irq,
++};
++
++static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
++	.process = cik_sdma_process_illegal_inst_irq,
++};
++
++static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++	adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs;
++	adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
++}
++
++/**
++ * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @src_offset: src GPU address
++ * @dst_offset: dst GPU address
++ * @byte_count: number of bytes to xfer
++ *
++ * Copy GPU buffers using the DMA engine (CIK).
++ * Used by the amdgpu ttm implementation to move pages if
++ * registered as the asic copy callback.
++ */
++static void cik_sdma_emit_copy_buffer(struct amdgpu_ring *ring,
++				      uint64_t src_offset,
++				      uint64_t dst_offset,
++				      uint32_t byte_count)
++{
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
++	amdgpu_ring_write(ring, byte_count);
++	amdgpu_ring_write(ring, 0); /* src/dst endian swap */
++	amdgpu_ring_write(ring, lower_32_bits(src_offset));
++	amdgpu_ring_write(ring, upper_32_bits(src_offset));
++	amdgpu_ring_write(ring, lower_32_bits(dst_offset));
++	amdgpu_ring_write(ring, upper_32_bits(dst_offset));
++}
++
++/**
++ * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @src_data: value to write to buffer
++ * @dst_offset: dst GPU address
++ * @byte_count: number of bytes to xfer
++ *
++ * Fill GPU buffers using the DMA engine (CIK).
++ */
++static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring,
++				      uint32_t src_data,
++				      uint64_t dst_offset,
++				      uint32_t byte_count)
++{
++	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0));
++	amdgpu_ring_write(ring, lower_32_bits(dst_offset));
++	amdgpu_ring_write(ring, upper_32_bits(dst_offset));
++	amdgpu_ring_write(ring, src_data);
++	amdgpu_ring_write(ring, byte_count);
++}
++
++static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
++	.copy_max_bytes = 0x1fffff,
++	.copy_num_dw = 7,
++	.emit_copy_buffer = cik_sdma_emit_copy_buffer,
++
++	.fill_max_bytes = 0x1fffff,
++	.fill_num_dw = 5,
++	.emit_fill_buffer = cik_sdma_emit_fill_buffer,
++};
++
++static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
++{
++	if (adev->mman.buffer_funcs == NULL) {
++		adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
++		adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
++	}
++}
++
++static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
++	.copy_pte = cik_sdma_vm_copy_pte,
++	.write_pte = cik_sdma_vm_write_pte,
++	.set_pte_pde = cik_sdma_vm_set_pte_pde,
++	.pad_ib = cik_sdma_vm_pad_ib,
++};
++
++static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
++{
++	if (adev->vm_manager.vm_pte_funcs == NULL) {
++		adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
++		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
+new file mode 100644
+index 0000000..42b5996
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __CIK_SDMA_H__
++#define __CIK_SDMA_H__
++
++extern const struct amdgpu_ip_funcs cik_sdma_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_ci.h b/drivers/gpu/drm/amd/amdgpu/clearstate_ci.h
+new file mode 100644
+index 0000000..c3982f9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/clearstate_ci.h
+@@ -0,0 +1,944 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++static const unsigned int ci_SECT_CONTEXT_def_1[] =
++{
++    0x00000000, // DB_RENDER_CONTROL
++    0x00000000, // DB_COUNT_CONTROL
++    0x00000000, // DB_DEPTH_VIEW
++    0x00000000, // DB_RENDER_OVERRIDE
++    0x00000000, // DB_RENDER_OVERRIDE2
++    0x00000000, // DB_HTILE_DATA_BASE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // DB_DEPTH_BOUNDS_MIN
++    0x00000000, // DB_DEPTH_BOUNDS_MAX
++    0x00000000, // DB_STENCIL_CLEAR
++    0x00000000, // DB_DEPTH_CLEAR
++    0x00000000, // PA_SC_SCREEN_SCISSOR_TL
++    0x40004000, // PA_SC_SCREEN_SCISSOR_BR
++    0, // HOLE
++    0x00000000, // DB_DEPTH_INFO
++    0x00000000, // DB_Z_INFO
++    0x00000000, // DB_STENCIL_INFO
++    0x00000000, // DB_Z_READ_BASE
++    0x00000000, // DB_STENCIL_READ_BASE
++    0x00000000, // DB_Z_WRITE_BASE
++    0x00000000, // DB_STENCIL_WRITE_BASE
++    0x00000000, // DB_DEPTH_SIZE
++    0x00000000, // DB_DEPTH_SLICE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // TA_BC_BASE_ADDR
++    0x00000000, // TA_BC_BASE_ADDR_HI
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // COHER_DEST_BASE_HI_0
++    0x00000000, // COHER_DEST_BASE_HI_1
++    0x00000000, // COHER_DEST_BASE_HI_2
++    0x00000000, // COHER_DEST_BASE_HI_3
++    0x00000000, // COHER_DEST_BASE_2
++    0x00000000, // COHER_DEST_BASE_3
++    0x00000000, // PA_SC_WINDOW_OFFSET
++    0x80000000, // PA_SC_WINDOW_SCISSOR_TL
++    0x40004000, // PA_SC_WINDOW_SCISSOR_BR
++    0x0000ffff, // PA_SC_CLIPRECT_RULE
++    0x00000000, // PA_SC_CLIPRECT_0_TL
++    0x40004000, // PA_SC_CLIPRECT_0_BR
++    0x00000000, // PA_SC_CLIPRECT_1_TL
++    0x40004000, // PA_SC_CLIPRECT_1_BR
++    0x00000000, // PA_SC_CLIPRECT_2_TL
++    0x40004000, // PA_SC_CLIPRECT_2_BR
++    0x00000000, // PA_SC_CLIPRECT_3_TL
++    0x40004000, // PA_SC_CLIPRECT_3_BR
++    0xaa99aaaa, // PA_SC_EDGERULE
++    0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
++    0xffffffff, // CB_TARGET_MASK
++    0xffffffff, // CB_SHADER_MASK
++    0x80000000, // PA_SC_GENERIC_SCISSOR_TL
++    0x40004000, // PA_SC_GENERIC_SCISSOR_BR
++    0x00000000, // COHER_DEST_BASE_0
++    0x00000000, // COHER_DEST_BASE_1
++    0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
++    0x00000000, // PA_SC_VPORT_ZMIN_0
++    0x3f800000, // PA_SC_VPORT_ZMAX_0
++    0x00000000, // PA_SC_VPORT_ZMIN_1
++    0x3f800000, // PA_SC_VPORT_ZMAX_1
++    0x00000000, // PA_SC_VPORT_ZMIN_2
++    0x3f800000, // PA_SC_VPORT_ZMAX_2
++    0x00000000, // PA_SC_VPORT_ZMIN_3
++    0x3f800000, // PA_SC_VPORT_ZMAX_3
++    0x00000000, // PA_SC_VPORT_ZMIN_4
++    0x3f800000, // PA_SC_VPORT_ZMAX_4
++    0x00000000, // PA_SC_VPORT_ZMIN_5
++    0x3f800000, // PA_SC_VPORT_ZMAX_5
++    0x00000000, // PA_SC_VPORT_ZMIN_6
++    0x3f800000, // PA_SC_VPORT_ZMAX_6
++    0x00000000, // PA_SC_VPORT_ZMIN_7
++    0x3f800000, // PA_SC_VPORT_ZMAX_7
++    0x00000000, // PA_SC_VPORT_ZMIN_8
++    0x3f800000, // PA_SC_VPORT_ZMAX_8
++    0x00000000, // PA_SC_VPORT_ZMIN_9
++    0x3f800000, // PA_SC_VPORT_ZMAX_9
++    0x00000000, // PA_SC_VPORT_ZMIN_10
++    0x3f800000, // PA_SC_VPORT_ZMAX_10
++    0x00000000, // PA_SC_VPORT_ZMIN_11
++    0x3f800000, // PA_SC_VPORT_ZMAX_11
++    0x00000000, // PA_SC_VPORT_ZMIN_12
++    0x3f800000, // PA_SC_VPORT_ZMAX_12
++    0x00000000, // PA_SC_VPORT_ZMIN_13
++    0x3f800000, // PA_SC_VPORT_ZMAX_13
++    0x00000000, // PA_SC_VPORT_ZMIN_14
++    0x3f800000, // PA_SC_VPORT_ZMAX_14
++    0x00000000, // PA_SC_VPORT_ZMIN_15
++    0x3f800000, // PA_SC_VPORT_ZMAX_15
++};
++static const unsigned int ci_SECT_CONTEXT_def_2[] =
++{
++    0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL
++    0, // HOLE
++    0x00000000, // CP_PERFMON_CNTX_CNTL
++    0x00000000, // CP_RINGID
++    0x00000000, // CP_VMID
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0xffffffff, // VGT_MAX_VTX_INDX
++    0x00000000, // VGT_MIN_VTX_INDX
++    0x00000000, // VGT_INDX_OFFSET
++    0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
++    0, // HOLE
++    0x00000000, // CB_BLEND_RED
++    0x00000000, // CB_BLEND_GREEN
++    0x00000000, // CB_BLEND_BLUE
++    0x00000000, // CB_BLEND_ALPHA
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // DB_STENCIL_CONTROL
++    0x00000000, // DB_STENCILREFMASK
++    0x00000000, // DB_STENCILREFMASK_BF
++    0, // HOLE
++    0x00000000, // PA_CL_VPORT_XSCALE
++    0x00000000, // PA_CL_VPORT_XOFFSET
++    0x00000000, // PA_CL_VPORT_YSCALE
++    0x00000000, // PA_CL_VPORT_YOFFSET
++    0x00000000, // PA_CL_VPORT_ZSCALE
++    0x00000000, // PA_CL_VPORT_ZOFFSET
++    0x00000000, // PA_CL_VPORT_XSCALE_1
++    0x00000000, // PA_CL_VPORT_XOFFSET_1
++    0x00000000, // PA_CL_VPORT_YSCALE_1
++    0x00000000, // PA_CL_VPORT_YOFFSET_1
++    0x00000000, // PA_CL_VPORT_ZSCALE_1
++    0x00000000, // PA_CL_VPORT_ZOFFSET_1
++    0x00000000, // PA_CL_VPORT_XSCALE_2
++    0x00000000, // PA_CL_VPORT_XOFFSET_2
++    0x00000000, // PA_CL_VPORT_YSCALE_2
++    0x00000000, // PA_CL_VPORT_YOFFSET_2
++    0x00000000, // PA_CL_VPORT_ZSCALE_2
++    0x00000000, // PA_CL_VPORT_ZOFFSET_2
++    0x00000000, // PA_CL_VPORT_XSCALE_3
++    0x00000000, // PA_CL_VPORT_XOFFSET_3
++    0x00000000, // PA_CL_VPORT_YSCALE_3
++    0x00000000, // PA_CL_VPORT_YOFFSET_3
++    0x00000000, // PA_CL_VPORT_ZSCALE_3
++    0x00000000, // PA_CL_VPORT_ZOFFSET_3
++    0x00000000, // PA_CL_VPORT_XSCALE_4
++    0x00000000, // PA_CL_VPORT_XOFFSET_4
++    0x00000000, // PA_CL_VPORT_YSCALE_4
++    0x00000000, // PA_CL_VPORT_YOFFSET_4
++    0x00000000, // PA_CL_VPORT_ZSCALE_4
++    0x00000000, // PA_CL_VPORT_ZOFFSET_4
++    0x00000000, // PA_CL_VPORT_XSCALE_5
++    0x00000000, // PA_CL_VPORT_XOFFSET_5
++    0x00000000, // PA_CL_VPORT_YSCALE_5
++    0x00000000, // PA_CL_VPORT_YOFFSET_5
++    0x00000000, // PA_CL_VPORT_ZSCALE_5
++    0x00000000, // PA_CL_VPORT_ZOFFSET_5
++    0x00000000, // PA_CL_VPORT_XSCALE_6
++    0x00000000, // PA_CL_VPORT_XOFFSET_6
++    0x00000000, // PA_CL_VPORT_YSCALE_6
++    0x00000000, // PA_CL_VPORT_YOFFSET_6
++    0x00000000, // PA_CL_VPORT_ZSCALE_6
++    0x00000000, // PA_CL_VPORT_ZOFFSET_6
++    0x00000000, // PA_CL_VPORT_XSCALE_7
++    0x00000000, // PA_CL_VPORT_XOFFSET_7
++    0x00000000, // PA_CL_VPORT_YSCALE_7
++    0x00000000, // PA_CL_VPORT_YOFFSET_7
++    0x00000000, // PA_CL_VPORT_ZSCALE_7
++    0x00000000, // PA_CL_VPORT_ZOFFSET_7
++    0x00000000, // PA_CL_VPORT_XSCALE_8
++    0x00000000, // PA_CL_VPORT_XOFFSET_8
++    0x00000000, // PA_CL_VPORT_YSCALE_8
++    0x00000000, // PA_CL_VPORT_YOFFSET_8
++    0x00000000, // PA_CL_VPORT_ZSCALE_8
++    0x00000000, // PA_CL_VPORT_ZOFFSET_8
++    0x00000000, // PA_CL_VPORT_XSCALE_9
++    0x00000000, // PA_CL_VPORT_XOFFSET_9
++    0x00000000, // PA_CL_VPORT_YSCALE_9
++    0x00000000, // PA_CL_VPORT_YOFFSET_9
++    0x00000000, // PA_CL_VPORT_ZSCALE_9
++    0x00000000, // PA_CL_VPORT_ZOFFSET_9
++    0x00000000, // PA_CL_VPORT_XSCALE_10
++    0x00000000, // PA_CL_VPORT_XOFFSET_10
++    0x00000000, // PA_CL_VPORT_YSCALE_10
++    0x00000000, // PA_CL_VPORT_YOFFSET_10
++    0x00000000, // PA_CL_VPORT_ZSCALE_10
++    0x00000000, // PA_CL_VPORT_ZOFFSET_10
++    0x00000000, // PA_CL_VPORT_XSCALE_11
++    0x00000000, // PA_CL_VPORT_XOFFSET_11
++    0x00000000, // PA_CL_VPORT_YSCALE_11
++    0x00000000, // PA_CL_VPORT_YOFFSET_11
++    0x00000000, // PA_CL_VPORT_ZSCALE_11
++    0x00000000, // PA_CL_VPORT_ZOFFSET_11
++    0x00000000, // PA_CL_VPORT_XSCALE_12
++    0x00000000, // PA_CL_VPORT_XOFFSET_12
++    0x00000000, // PA_CL_VPORT_YSCALE_12
++    0x00000000, // PA_CL_VPORT_YOFFSET_12
++    0x00000000, // PA_CL_VPORT_ZSCALE_12
++    0x00000000, // PA_CL_VPORT_ZOFFSET_12
++    0x00000000, // PA_CL_VPORT_XSCALE_13
++    0x00000000, // PA_CL_VPORT_XOFFSET_13
++    0x00000000, // PA_CL_VPORT_YSCALE_13
++    0x00000000, // PA_CL_VPORT_YOFFSET_13
++    0x00000000, // PA_CL_VPORT_ZSCALE_13
++    0x00000000, // PA_CL_VPORT_ZOFFSET_13
++    0x00000000, // PA_CL_VPORT_XSCALE_14
++    0x00000000, // PA_CL_VPORT_XOFFSET_14
++    0x00000000, // PA_CL_VPORT_YSCALE_14
++    0x00000000, // PA_CL_VPORT_YOFFSET_14
++    0x00000000, // PA_CL_VPORT_ZSCALE_14
++    0x00000000, // PA_CL_VPORT_ZOFFSET_14
++    0x00000000, // PA_CL_VPORT_XSCALE_15
++    0x00000000, // PA_CL_VPORT_XOFFSET_15
++    0x00000000, // PA_CL_VPORT_YSCALE_15
++    0x00000000, // PA_CL_VPORT_YOFFSET_15
++    0x00000000, // PA_CL_VPORT_ZSCALE_15
++    0x00000000, // PA_CL_VPORT_ZOFFSET_15
++    0x00000000, // PA_CL_UCP_0_X
++    0x00000000, // PA_CL_UCP_0_Y
++    0x00000000, // PA_CL_UCP_0_Z
++    0x00000000, // PA_CL_UCP_0_W
++    0x00000000, // PA_CL_UCP_1_X
++    0x00000000, // PA_CL_UCP_1_Y
++    0x00000000, // PA_CL_UCP_1_Z
++    0x00000000, // PA_CL_UCP_1_W
++    0x00000000, // PA_CL_UCP_2_X
++    0x00000000, // PA_CL_UCP_2_Y
++    0x00000000, // PA_CL_UCP_2_Z
++    0x00000000, // PA_CL_UCP_2_W
++    0x00000000, // PA_CL_UCP_3_X
++    0x00000000, // PA_CL_UCP_3_Y
++    0x00000000, // PA_CL_UCP_3_Z
++    0x00000000, // PA_CL_UCP_3_W
++    0x00000000, // PA_CL_UCP_4_X
++    0x00000000, // PA_CL_UCP_4_Y
++    0x00000000, // PA_CL_UCP_4_Z
++    0x00000000, // PA_CL_UCP_4_W
++    0x00000000, // PA_CL_UCP_5_X
++    0x00000000, // PA_CL_UCP_5_Y
++    0x00000000, // PA_CL_UCP_5_Z
++    0x00000000, // PA_CL_UCP_5_W
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // SPI_PS_INPUT_CNTL_0
++    0x00000000, // SPI_PS_INPUT_CNTL_1
++    0x00000000, // SPI_PS_INPUT_CNTL_2
++    0x00000000, // SPI_PS_INPUT_CNTL_3
++    0x00000000, // SPI_PS_INPUT_CNTL_4
++    0x00000000, // SPI_PS_INPUT_CNTL_5
++    0x00000000, // SPI_PS_INPUT_CNTL_6
++    0x00000000, // SPI_PS_INPUT_CNTL_7
++    0x00000000, // SPI_PS_INPUT_CNTL_8
++    0x00000000, // SPI_PS_INPUT_CNTL_9
++    0x00000000, // SPI_PS_INPUT_CNTL_10
++    0x00000000, // SPI_PS_INPUT_CNTL_11
++    0x00000000, // SPI_PS_INPUT_CNTL_12
++    0x00000000, // SPI_PS_INPUT_CNTL_13
++    0x00000000, // SPI_PS_INPUT_CNTL_14
++    0x00000000, // SPI_PS_INPUT_CNTL_15
++    0x00000000, // SPI_PS_INPUT_CNTL_16
++    0x00000000, // SPI_PS_INPUT_CNTL_17
++    0x00000000, // SPI_PS_INPUT_CNTL_18
++    0x00000000, // SPI_PS_INPUT_CNTL_19
++    0x00000000, // SPI_PS_INPUT_CNTL_20
++    0x00000000, // SPI_PS_INPUT_CNTL_21
++    0x00000000, // SPI_PS_INPUT_CNTL_22
++    0x00000000, // SPI_PS_INPUT_CNTL_23
++    0x00000000, // SPI_PS_INPUT_CNTL_24
++    0x00000000, // SPI_PS_INPUT_CNTL_25
++    0x00000000, // SPI_PS_INPUT_CNTL_26
++    0x00000000, // SPI_PS_INPUT_CNTL_27
++    0x00000000, // SPI_PS_INPUT_CNTL_28
++    0x00000000, // SPI_PS_INPUT_CNTL_29
++    0x00000000, // SPI_PS_INPUT_CNTL_30
++    0x00000000, // SPI_PS_INPUT_CNTL_31
++    0x00000000, // SPI_VS_OUT_CONFIG
++    0, // HOLE
++    0x00000000, // SPI_PS_INPUT_ENA
++    0x00000000, // SPI_PS_INPUT_ADDR
++    0x00000000, // SPI_INTERP_CONTROL_0
++    0x00000002, // SPI_PS_IN_CONTROL
++    0, // HOLE
++    0x00000000, // SPI_BARYC_CNTL
++    0, // HOLE
++    0x00000000, // SPI_TMPRING_SIZE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // SPI_SHADER_POS_FORMAT
++    0x00000000, // SPI_SHADER_Z_FORMAT
++    0x00000000, // SPI_SHADER_COL_FORMAT
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_BLEND0_CONTROL
++    0x00000000, // CB_BLEND1_CONTROL
++    0x00000000, // CB_BLEND2_CONTROL
++    0x00000000, // CB_BLEND3_CONTROL
++    0x00000000, // CB_BLEND4_CONTROL
++    0x00000000, // CB_BLEND5_CONTROL
++    0x00000000, // CB_BLEND6_CONTROL
++    0x00000000, // CB_BLEND7_CONTROL
++};
++static const unsigned int ci_SECT_CONTEXT_def_3[] =
++{
++    0x00000000, // PA_CL_POINT_X_RAD
++    0x00000000, // PA_CL_POINT_Y_RAD
++    0x00000000, // PA_CL_POINT_SIZE
++    0x00000000, // PA_CL_POINT_CULL_RAD
++    0x00000000, // VGT_DMA_BASE_HI
++    0x00000000, // VGT_DMA_BASE
++};
++static const unsigned int ci_SECT_CONTEXT_def_4[] =
++{
++    0x00000000, // DB_DEPTH_CONTROL
++    0x00000000, // DB_EQAA
++    0x00000000, // CB_COLOR_CONTROL
++    0x00000000, // DB_SHADER_CONTROL
++    0x00090000, // PA_CL_CLIP_CNTL
++    0x00000004, // PA_SU_SC_MODE_CNTL
++    0x00000000, // PA_CL_VTE_CNTL
++    0x00000000, // PA_CL_VS_OUT_CNTL
++    0x00000000, // PA_CL_NANINF_CNTL
++    0x00000000, // PA_SU_LINE_STIPPLE_CNTL
++    0x00000000, // PA_SU_LINE_STIPPLE_SCALE
++    0x00000000, // PA_SU_PRIM_FILTER_CNTL
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // PA_SU_POINT_SIZE
++    0x00000000, // PA_SU_POINT_MINMAX
++    0x00000000, // PA_SU_LINE_CNTL
++    0x00000000, // PA_SC_LINE_STIPPLE
++    0x00000000, // VGT_OUTPUT_PATH_CNTL
++    0x00000000, // VGT_HOS_CNTL
++    0x00000000, // VGT_HOS_MAX_TESS_LEVEL
++    0x00000000, // VGT_HOS_MIN_TESS_LEVEL
++    0x00000000, // VGT_HOS_REUSE_DEPTH
++    0x00000000, // VGT_GROUP_PRIM_TYPE
++    0x00000000, // VGT_GROUP_FIRST_DECR
++    0x00000000, // VGT_GROUP_DECR
++    0x00000000, // VGT_GROUP_VECT_0_CNTL
++    0x00000000, // VGT_GROUP_VECT_1_CNTL
++    0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
++    0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
++    0x00000000, // VGT_GS_MODE
++    0x00000000, // VGT_GS_ONCHIP_CNTL
++    0x00000000, // PA_SC_MODE_CNTL_0
++    0x00000000, // PA_SC_MODE_CNTL_1
++    0x00000000, // VGT_ENHANCE
++    0x00000100, // VGT_GS_PER_ES
++    0x00000080, // VGT_ES_PER_GS
++    0x00000002, // VGT_GS_PER_VS
++    0x00000000, // VGT_GSVS_RING_OFFSET_1
++    0x00000000, // VGT_GSVS_RING_OFFSET_2
++    0x00000000, // VGT_GSVS_RING_OFFSET_3
++    0x00000000, // VGT_GS_OUT_PRIM_TYPE
++    0x00000000, // IA_ENHANCE
++};
++static const unsigned int ci_SECT_CONTEXT_def_5[] =
++{
++    0x00000000, // WD_ENHANCE
++    0x00000000, // VGT_PRIMITIVEID_EN
++};
++static const unsigned int ci_SECT_CONTEXT_def_6[] =
++{
++    0x00000000, // VGT_PRIMITIVEID_RESET
++};
++static const unsigned int ci_SECT_CONTEXT_def_7[] =
++{
++    0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // VGT_INSTANCE_STEP_RATE_0
++    0x00000000, // VGT_INSTANCE_STEP_RATE_1
++    0x000000ff, // IA_MULTI_VGT_PARAM
++    0x00000000, // VGT_ESGS_RING_ITEMSIZE
++    0x00000000, // VGT_GSVS_RING_ITEMSIZE
++    0x00000000, // VGT_REUSE_OFF
++    0x00000000, // VGT_VTX_CNT_EN
++    0x00000000, // DB_HTILE_SURFACE
++    0x00000000, // DB_SRESULTS_COMPARE_STATE0
++    0x00000000, // DB_SRESULTS_COMPARE_STATE1
++    0x00000000, // DB_PRELOAD_CONTROL
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
++    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
++    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
++    0, // HOLE
++    0x00000000, // VGT_GS_MAX_VERT_OUT
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // VGT_SHADER_STAGES_EN
++    0x00000000, // VGT_LS_HS_CONFIG
++    0x00000000, // VGT_GS_VERT_ITEMSIZE
++    0x00000000, // VGT_GS_VERT_ITEMSIZE_1
++    0x00000000, // VGT_GS_VERT_ITEMSIZE_2
++    0x00000000, // VGT_GS_VERT_ITEMSIZE_3
++    0x00000000, // VGT_TF_PARAM
++    0x00000000, // DB_ALPHA_TO_MASK
++    0, // HOLE
++    0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
++    0x00000000, // PA_SU_POLY_OFFSET_CLAMP
++    0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
++    0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
++    0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
++    0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
++    0x00000000, // VGT_GS_INSTANCE_CNT
++    0x00000000, // VGT_STRMOUT_CONFIG
++    0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // PA_SC_CENTROID_PRIORITY_0
++    0x00000000, // PA_SC_CENTROID_PRIORITY_1
++    0x00001000, // PA_SC_LINE_CNTL
++    0x00000000, // PA_SC_AA_CONFIG
++    0x00000005, // PA_SU_VTX_CNTL
++    0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
++    0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
++    0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
++    0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
++    0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0
++    0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
++    0x00000010, // VGT_OUT_DEALLOC_CNTL
++    0x00000000, // CB_COLOR0_BASE
++    0x00000000, // CB_COLOR0_PITCH
++    0x00000000, // CB_COLOR0_SLICE
++    0x00000000, // CB_COLOR0_VIEW
++    0x00000000, // CB_COLOR0_INFO
++    0x00000000, // CB_COLOR0_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR0_CMASK
++    0x00000000, // CB_COLOR0_CMASK_SLICE
++    0x00000000, // CB_COLOR0_FMASK
++    0x00000000, // CB_COLOR0_FMASK_SLICE
++    0x00000000, // CB_COLOR0_CLEAR_WORD0
++    0x00000000, // CB_COLOR0_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR1_BASE
++    0x00000000, // CB_COLOR1_PITCH
++    0x00000000, // CB_COLOR1_SLICE
++    0x00000000, // CB_COLOR1_VIEW
++    0x00000000, // CB_COLOR1_INFO
++    0x00000000, // CB_COLOR1_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR1_CMASK
++    0x00000000, // CB_COLOR1_CMASK_SLICE
++    0x00000000, // CB_COLOR1_FMASK
++    0x00000000, // CB_COLOR1_FMASK_SLICE
++    0x00000000, // CB_COLOR1_CLEAR_WORD0
++    0x00000000, // CB_COLOR1_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR2_BASE
++    0x00000000, // CB_COLOR2_PITCH
++    0x00000000, // CB_COLOR2_SLICE
++    0x00000000, // CB_COLOR2_VIEW
++    0x00000000, // CB_COLOR2_INFO
++    0x00000000, // CB_COLOR2_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR2_CMASK
++    0x00000000, // CB_COLOR2_CMASK_SLICE
++    0x00000000, // CB_COLOR2_FMASK
++    0x00000000, // CB_COLOR2_FMASK_SLICE
++    0x00000000, // CB_COLOR2_CLEAR_WORD0
++    0x00000000, // CB_COLOR2_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR3_BASE
++    0x00000000, // CB_COLOR3_PITCH
++    0x00000000, // CB_COLOR3_SLICE
++    0x00000000, // CB_COLOR3_VIEW
++    0x00000000, // CB_COLOR3_INFO
++    0x00000000, // CB_COLOR3_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR3_CMASK
++    0x00000000, // CB_COLOR3_CMASK_SLICE
++    0x00000000, // CB_COLOR3_FMASK
++    0x00000000, // CB_COLOR3_FMASK_SLICE
++    0x00000000, // CB_COLOR3_CLEAR_WORD0
++    0x00000000, // CB_COLOR3_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR4_BASE
++    0x00000000, // CB_COLOR4_PITCH
++    0x00000000, // CB_COLOR4_SLICE
++    0x00000000, // CB_COLOR4_VIEW
++    0x00000000, // CB_COLOR4_INFO
++    0x00000000, // CB_COLOR4_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR4_CMASK
++    0x00000000, // CB_COLOR4_CMASK_SLICE
++    0x00000000, // CB_COLOR4_FMASK
++    0x00000000, // CB_COLOR4_FMASK_SLICE
++    0x00000000, // CB_COLOR4_CLEAR_WORD0
++    0x00000000, // CB_COLOR4_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR5_BASE
++    0x00000000, // CB_COLOR5_PITCH
++    0x00000000, // CB_COLOR5_SLICE
++    0x00000000, // CB_COLOR5_VIEW
++    0x00000000, // CB_COLOR5_INFO
++    0x00000000, // CB_COLOR5_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR5_CMASK
++    0x00000000, // CB_COLOR5_CMASK_SLICE
++    0x00000000, // CB_COLOR5_FMASK
++    0x00000000, // CB_COLOR5_FMASK_SLICE
++    0x00000000, // CB_COLOR5_CLEAR_WORD0
++    0x00000000, // CB_COLOR5_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR6_BASE
++    0x00000000, // CB_COLOR6_PITCH
++    0x00000000, // CB_COLOR6_SLICE
++    0x00000000, // CB_COLOR6_VIEW
++    0x00000000, // CB_COLOR6_INFO
++    0x00000000, // CB_COLOR6_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR6_CMASK
++    0x00000000, // CB_COLOR6_CMASK_SLICE
++    0x00000000, // CB_COLOR6_FMASK
++    0x00000000, // CB_COLOR6_FMASK_SLICE
++    0x00000000, // CB_COLOR6_CLEAR_WORD0
++    0x00000000, // CB_COLOR6_CLEAR_WORD1
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_COLOR7_BASE
++    0x00000000, // CB_COLOR7_PITCH
++    0x00000000, // CB_COLOR7_SLICE
++    0x00000000, // CB_COLOR7_VIEW
++    0x00000000, // CB_COLOR7_INFO
++    0x00000000, // CB_COLOR7_ATTRIB
++    0, // HOLE
++    0x00000000, // CB_COLOR7_CMASK
++    0x00000000, // CB_COLOR7_CMASK_SLICE
++    0x00000000, // CB_COLOR7_FMASK
++    0x00000000, // CB_COLOR7_FMASK_SLICE
++    0x00000000, // CB_COLOR7_CLEAR_WORD0
++    0x00000000, // CB_COLOR7_CLEAR_WORD1
++};
++static const struct cs_extent_def ci_SECT_CONTEXT_defs[] =
++{
++    {ci_SECT_CONTEXT_def_1, 0x0000a000, 212 },
++    {ci_SECT_CONTEXT_def_2, 0x0000a0d6, 274 },
++    {ci_SECT_CONTEXT_def_3, 0x0000a1f5, 6 },
++    {ci_SECT_CONTEXT_def_4, 0x0000a200, 157 },
++    {ci_SECT_CONTEXT_def_5, 0x0000a2a0, 2 },
++    {ci_SECT_CONTEXT_def_6, 0x0000a2a3, 1 },
++    {ci_SECT_CONTEXT_def_7, 0x0000a2a5, 233 },
++    { 0, 0, 0 }
++};
++static const struct cs_section_def ci_cs_data[] = {
++    { ci_SECT_CONTEXT_defs, SECT_CONTEXT },
++    { 0, SECT_NONE }
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+new file mode 100644
+index 0000000..c1bc693
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -0,0 +1,3830 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_i2c.h"
++#include "cikd.h"
++#include "atom.h"
++#include "amdgpu_atombios.h"
++#include "atombios_crtc.h"
++#include "atombios_encoders.h"
++#include "amdgpu_pll.h"
++#include "amdgpu_connectors.h"
++
++#include "dce/dce_8_0_d.h"
++#include "dce/dce_8_0_sh_mask.h"
++
++#include "gca/gfx_7_2_enum.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
++static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
++
++static const u32 crtc_offsets[6] =
++{
++	CRTC0_REGISTER_OFFSET,
++	CRTC1_REGISTER_OFFSET,
++	CRTC2_REGISTER_OFFSET,
++	CRTC3_REGISTER_OFFSET,
++	CRTC4_REGISTER_OFFSET,
++	CRTC5_REGISTER_OFFSET
++};
++
++static const uint32_t dig_offsets[] = {
++	CRTC0_REGISTER_OFFSET,
++	CRTC1_REGISTER_OFFSET,
++	CRTC2_REGISTER_OFFSET,
++	CRTC3_REGISTER_OFFSET,
++	CRTC4_REGISTER_OFFSET,
++	CRTC5_REGISTER_OFFSET,
++	(0x13830 - 0x7030) >> 2,
++};
++
++static const struct {
++	uint32_t	reg;
++	uint32_t	vblank;
++	uint32_t	vline;
++	uint32_t	hpd;
++
++} interrupt_status_offsets[6] = { {
++	.reg = mmDISP_INTERRUPT_STATUS,
++	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
++} };
++
++static const uint32_t hpd_int_control_offsets[6] = {
++	mmDC_HPD1_INT_CONTROL,
++	mmDC_HPD2_INT_CONTROL,
++	mmDC_HPD3_INT_CONTROL,
++	mmDC_HPD4_INT_CONTROL,
++	mmDC_HPD5_INT_CONTROL,
++	mmDC_HPD6_INT_CONTROL,
++};
++
++static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
++				     u32 block_offset, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
++	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
++	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
++
++	return r;
++}
++
++static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
++				      u32 block_offset, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
++	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
++}
++
++static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
++{
++	if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
++			CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
++		return true;
++	else
++		return false;
++}
++
++static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
++{
++	u32 pos1, pos2;
++
++	pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++	pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++	if (pos1 != pos2)
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v8_0_vblank_wait - vblank wait asic callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @crtc: crtc to wait for vblank on
++ *
++ * Wait for vblank on the requested crtc (evergreen+).
++ */
++static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
++{
++	unsigned i = 0;
++
++	if (crtc >= adev->mode_info.num_crtc)
++		return;
++
++	if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
++		return;
++
++	/* depending on when we hit vblank, we may be close to active; if so,
++	 * wait for another frame.
++	 */
++	while (dce_v8_0_is_in_vblank(adev, crtc)) {
++		if (i++ % 100 == 0) {
++			if (!dce_v8_0_is_counter_moving(adev, crtc))
++				break;
++		}
++	}
++
++	while (!dce_v8_0_is_in_vblank(adev, crtc)) {
++		if (i++ % 100 == 0) {
++			if (!dce_v8_0_is_counter_moving(adev, crtc))
++				break;
++		}
++	}
++}
++
++static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
++{
++	if (crtc >= adev->mode_info.num_crtc)
++		return 0;
++	else
++		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
++}
++
++/**
++ * dce_v8_0_page_flip - pageflip callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @crtc_id: crtc to cleanup pageflip on
++ * @crtc_base: new address of the crtc (GPU MC address)
++ *
++ * Does the actual pageflip (evergreen+).
++ * During vblank we take the crtc lock and wait for the update_pending
++ * bit to go high, when it does, we release the lock, and allow the
++ * double buffered update to take place.
++ * Returns the current update pending status.
++ */
++static void dce_v8_0_page_flip(struct amdgpu_device *adev,
++			      int crtc_id, u64 crtc_base)
++{
++	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
++	int i;
++
++	/* Lock the graphics update lock */
++	tmp |= GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
++	WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
++
++	/* update the scanout addresses */
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(crtc_base));
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32)crtc_base);
++
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(crtc_base));
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32)crtc_base);
++
++	/* Wait for update_pending to go high. */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
++				GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
++			break;
++		udelay(1);
++	}
++	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
++
++	/* Unlock the lock, so double-buffering can take place inside vblank */
++	tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
++	WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
++					u32 *vbl, u32 *position)
++{
++	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
++		return -EINVAL;
++
++	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
++	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++	return 0;
++}
++
++/**
++ * dce_v8_0_hpd_sense - hpd sense callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @hpd: hpd (hotplug detect) pin
++ *
++ * Checks if a digital monitor is connected (evergreen+).
++ * Returns true if connected, false if not connected.
++ */
++static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
++			       enum amdgpu_hpd_id hpd)
++{
++	bool connected = false;
++
++	switch (hpd) {
++	case AMDGPU_HPD_1:
++		if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
++			connected = true;
++		break;
++	case AMDGPU_HPD_2:
++		if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
++			connected = true;
++		break;
++	case AMDGPU_HPD_3:
++		if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
++			connected = true;
++		break;
++	case AMDGPU_HPD_4:
++		if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
++			connected = true;
++		break;
++	case AMDGPU_HPD_5:
++		if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
++			connected = true;
++		break;
++	case AMDGPU_HPD_6:
++		if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
++			connected = true;
++		break;
++	default:
++		break;
++	}
++
++	return connected;
++}
++
++/**
++ * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @hpd: hpd (hotplug detect) pin
++ *
++ * Set the polarity of the hpd pin (evergreen+).
++ */
++static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
++				      enum amdgpu_hpd_id hpd)
++{
++	u32 tmp;
++	bool connected = dce_v8_0_hpd_sense(adev, hpd);
++
++	switch (hpd) {
++	case AMDGPU_HPD_1:
++		tmp = RREG32(mmDC_HPD1_INT_CONTROL);
++		if (connected)
++			tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
++		else
++			tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
++		WREG32(mmDC_HPD1_INT_CONTROL, tmp);
++		break;
++	case AMDGPU_HPD_2:
++		tmp = RREG32(mmDC_HPD2_INT_CONTROL);
++		if (connected)
++			tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
++		else
++			tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
++		WREG32(mmDC_HPD2_INT_CONTROL, tmp);
++		break;
++	case AMDGPU_HPD_3:
++		tmp = RREG32(mmDC_HPD3_INT_CONTROL);
++		if (connected)
++			tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
++		else
++			tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
++		WREG32(mmDC_HPD3_INT_CONTROL, tmp);
++		break;
++	case AMDGPU_HPD_4:
++		tmp = RREG32(mmDC_HPD4_INT_CONTROL);
++		if (connected)
++			tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
++		else
++			tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
++		WREG32(mmDC_HPD4_INT_CONTROL, tmp);
++		break;
++	case AMDGPU_HPD_5:
++		tmp = RREG32(mmDC_HPD5_INT_CONTROL);
++		if (connected)
++			tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
++		else
++			tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
++		WREG32(mmDC_HPD5_INT_CONTROL, tmp);
++			break;
++	case AMDGPU_HPD_6:
++		tmp = RREG32(mmDC_HPD6_INT_CONTROL);
++		if (connected)
++			tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
++		else
++			tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
++		WREG32(mmDC_HPD6_INT_CONTROL, tmp);
++		break;
++	default:
++		break;
++	}
++}
++
++/**
++ * dce_v8_0_hpd_init - hpd setup callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup the hpd pins used by the card (evergreen+).
++ * Enable the pin, set the polarity, and enable the hpd interrupts.
++ */
++static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++	u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
++		(0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
++		DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
++		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
++			/* don't try to enable hpd on eDP or LVDS avoid breaking the
++			 * aux dp channel on imac and help (but not completely fix)
++			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
++			 * also avoid interrupt storms during dpms.
++			 */
++			continue;
++		}
++		switch (amdgpu_connector->hpd.hpd) {
++		case AMDGPU_HPD_1:
++			WREG32(mmDC_HPD1_CONTROL, tmp);
++			break;
++		case AMDGPU_HPD_2:
++			WREG32(mmDC_HPD2_CONTROL, tmp);
++			break;
++		case AMDGPU_HPD_3:
++			WREG32(mmDC_HPD3_CONTROL, tmp);
++			break;
++		case AMDGPU_HPD_4:
++			WREG32(mmDC_HPD4_CONTROL, tmp);
++			break;
++		case AMDGPU_HPD_5:
++			WREG32(mmDC_HPD5_CONTROL, tmp);
++			break;
++		case AMDGPU_HPD_6:
++			WREG32(mmDC_HPD6_CONTROL, tmp);
++			break;
++		default:
++			break;
++		}
++		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
++		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
++	}
++}
++
++/**
++ * dce_v8_0_hpd_fini - hpd tear down callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down the hpd pins used by the card (evergreen+).
++ * Disable the hpd interrupts.
++ */
++static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		switch (amdgpu_connector->hpd.hpd) {
++		case AMDGPU_HPD_1:
++			WREG32(mmDC_HPD1_CONTROL, 0);
++			break;
++		case AMDGPU_HPD_2:
++			WREG32(mmDC_HPD2_CONTROL, 0);
++			break;
++		case AMDGPU_HPD_3:
++			WREG32(mmDC_HPD3_CONTROL, 0);
++			break;
++		case AMDGPU_HPD_4:
++			WREG32(mmDC_HPD4_CONTROL, 0);
++			break;
++		case AMDGPU_HPD_5:
++			WREG32(mmDC_HPD5_CONTROL, 0);
++			break;
++		case AMDGPU_HPD_6:
++			WREG32(mmDC_HPD6_CONTROL, 0);
++			break;
++		default:
++			break;
++		}
++		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
++	}
++}
++
++static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
++{
++	return mmDC_GPIO_HPD_A;
++}
++
++static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
++{
++	u32 crtc_hung = 0;
++	u32 crtc_status[6];
++	u32 i, j, tmp;
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
++			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
++			crtc_hung |= (1 << i);
++		}
++	}
++
++	for (j = 0; j < 10; j++) {
++		for (i = 0; i < adev->mode_info.num_crtc; i++) {
++			if (crtc_hung & (1 << i)) {
++				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
++				if (tmp != crtc_status[i])
++					crtc_hung &= ~(1 << i);
++			}
++		}
++		if (crtc_hung == 0)
++			return false;
++		udelay(100);
++	}
++
++	return true;
++}
++
++static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
++				    struct amdgpu_mode_mc_save *save)
++{
++	u32 crtc_enabled, tmp;
++	int i;
++
++	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
++	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
++
++	/* disable VGA render */
++	tmp = RREG32(mmVGA_RENDER_CONTROL);
++	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++	WREG32(mmVGA_RENDER_CONTROL, tmp);
++
++	/* blank the display controllers */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
++					     CRTC_CONTROL, CRTC_MASTER_EN);
++		if (crtc_enabled) {
++#if 0
++			u32 frame_count;
++			int j;
++
++			save->crtc_enabled[i] = true;
++			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
++				amdgpu_display_vblank_wait(adev, i);
++				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
++				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			}
++			/* wait for the next frame */
++			frame_count = amdgpu_display_vblank_get_counter(adev, i);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
++					break;
++				udelay(1);
++			}
++			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
++				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
++				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
++				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
++				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++			}
++#else
++			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
++			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
++			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			save->crtc_enabled[i] = false;
++			/* ***** */
++#endif
++		} else {
++			save->crtc_enabled[i] = false;
++		}
++	}
++}
++
++static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
++				      struct amdgpu_mode_mc_save *save)
++{
++	u32 tmp, frame_count;
++	int i, j;
++
++	/* update crtc base addresses */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
++		       upper_32_bits(adev->mc.vram_start));
++		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
++		       upper_32_bits(adev->mc.vram_start));
++		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
++		       (u32)adev->mc.vram_start);
++		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
++		       (u32)adev->mc.vram_start);
++
++		if (save->crtc_enabled[i]) {
++			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
++				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
++				WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
++				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
++				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
++				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
++				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++			}
++			for (j = 0; j < adev->usec_timeout; j++) {
++				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
++					break;
++				udelay(1);
++			}
++			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
++			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			/* wait for the next frame */
++			frame_count = amdgpu_display_vblank_get_counter(adev, i);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
++					break;
++				udelay(1);
++			}
++		}
++	}
++
++	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
++	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
++
++	/* Unlock vga access */
++	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
++	mdelay(1);
++	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
++}
++
++static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
++					  bool render)
++{
++	u32 tmp;
++
++	/* Lockout access through VGA aperture*/
++	tmp = RREG32(mmVGA_HDP_CONTROL);
++	if (render)
++		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
++	else
++		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
++	WREG32(mmVGA_HDP_CONTROL, tmp);
++
++	/* disable VGA render */
++	tmp = RREG32(mmVGA_RENDER_CONTROL);
++	if (render)
++		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++	WREG32(mmVGA_RENDER_CONTROL, tmp);
++}
++
++static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	int bpc = 0;
++	u32 tmp = 0;
++	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		bpc = amdgpu_connector_get_monitor_bpc(connector);
++		dither = amdgpu_connector->dither;
++	}
++
++	/* LVDS/eDP FMT is set up by atom */
++	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
++		return;
++
++	/* not needed for analog */
++	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
++	    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
++		return;
++
++	if (bpc == 0)
++		return;
++
++	switch (bpc) {
++	case 6:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE)
++			/* XXX sort out optimal dither settings */
++			tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
++				(0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
++		else
++			tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
++			(0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
++		break;
++	case 8:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE)
++			/* XXX sort out optimal dither settings */
++			tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
++				(1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
++		else
++			tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
++			(1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
++		break;
++	case 10:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE)
++			/* XXX sort out optimal dither settings */
++			tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
++				FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
++				(2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
++		else
++			tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
++			(2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
++		break;
++	default:
++		/* not needed */
++		break;
++	}
++
++	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++
++/* display watermark setup */
++/**
++ * dce_v8_0_line_buffer_adjust - Set up the line buffer
++ *
++ * @adev: amdgpu_device pointer
++ * @amdgpu_crtc: the selected display controller
++ * @mode: the current display mode on the selected display
++ * controller
++ *
++ * Setup up the line buffer allocation for
++ * the selected display controller (CIK).
++ * Returns the line buffer size in pixels.
++ */
++static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
++				       struct amdgpu_crtc *amdgpu_crtc,
++				       struct drm_display_mode *mode)
++{
++	u32 tmp, buffer_alloc, i;
++	u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
++	/*
++	 * Line Buffer Setup
++	 * There are 6 line buffers, one for each display controllers.
++	 * There are 3 partitions per LB. Select the number of partitions
++	 * to enable based on the display width.  For display widths larger
++	 * than 4096, you need use to use 2 display controllers and combine
++	 * them using the stereo blender.
++	 */
++	if (amdgpu_crtc->base.enabled && mode) {
++		if (mode->crtc_hdisplay < 1920) {
++			tmp = 1;
++			buffer_alloc = 2;
++		} else if (mode->crtc_hdisplay < 2560) {
++			tmp = 2;
++			buffer_alloc = 2;
++		} else if (mode->crtc_hdisplay < 4096) {
++			tmp = 0;
++			buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
++		} else {
++			DRM_DEBUG_KMS("Mode too big for LB!\n");
++			tmp = 0;
++			buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
++		}
++	} else {
++		tmp = 1;
++		buffer_alloc = 0;
++	}
++
++	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
++	      (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
++	      (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
++
++	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
++	       (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
++		    PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
++			break;
++		udelay(1);
++	}
++
++	if (amdgpu_crtc->base.enabled && mode) {
++		switch (tmp) {
++		case 0:
++		default:
++			return 4096 * 2;
++		case 1:
++			return 1920 * 2;
++		case 2:
++			return 2560 * 2;
++		}
++	}
++
++	/* controller not enabled, so no lb used */
++	return 0;
++}
++
++/**
++ * cik_get_number_of_dram_channels - get the number of dram channels
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up the number of video ram channels (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the number of dram channels
++ */
++static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
++
++	switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
++	case 0:
++	default:
++		return 1;
++	case 1:
++		return 2;
++	case 2:
++		return 4;
++	case 3:
++		return 8;
++	case 4:
++		return 3;
++	case 5:
++		return 6;
++	case 6:
++		return 10;
++	case 7:
++		return 12;
++	case 8:
++		return 16;
++	}
++}
++
++struct dce8_wm_params {
++	u32 dram_channels; /* number of dram channels */
++	u32 yclk;          /* bandwidth per dram data pin in kHz */
++	u32 sclk;          /* engine clock in kHz */
++	u32 disp_clk;      /* display clock in kHz */
++	u32 src_width;     /* viewport width */
++	u32 active_time;   /* active display time in ns */
++	u32 blank_time;    /* blank time in ns */
++	bool interlaced;    /* mode is interlaced */
++	fixed20_12 vsc;    /* vertical scale ratio */
++	u32 num_heads;     /* number of active crtcs */
++	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
++	u32 lb_size;       /* line buffer allocated to pipe */
++	u32 vtaps;         /* vertical scaler taps */
++};
++
++/**
++ * dce_v8_0_dram_bandwidth - get the dram bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the raw dram bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dram bandwidth in MBytes/s
++ */
++static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
++{
++	/* Calculate raw DRAM Bandwidth */
++	fixed20_12 dram_efficiency; /* 0.7 */
++	fixed20_12 yclk, dram_channels, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	yclk.full = dfixed_const(wm->yclk);
++	yclk.full = dfixed_div(yclk, a);
++	dram_channels.full = dfixed_const(wm->dram_channels * 4);
++	a.full = dfixed_const(10);
++	dram_efficiency.full = dfixed_const(7);
++	dram_efficiency.full = dfixed_div(dram_efficiency, a);
++	bandwidth.full = dfixed_mul(dram_channels, yclk);
++	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the dram bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dram bandwidth for display in MBytes/s
++ */
++static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
++{
++	/* Calculate DRAM Bandwidth and the part allocated to display. */
++	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
++	fixed20_12 yclk, dram_channels, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	yclk.full = dfixed_const(wm->yclk);
++	yclk.full = dfixed_div(yclk, a);
++	dram_channels.full = dfixed_const(wm->dram_channels * 4);
++	a.full = dfixed_const(10);
++	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
++	disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
++	bandwidth.full = dfixed_mul(dram_channels, yclk);
++	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v8_0_data_return_bandwidth - get the data return bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the data return bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the data return bandwidth in MBytes/s
++ */
++static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
++{
++	/* Calculate the display Data return Bandwidth */
++	fixed20_12 return_efficiency; /* 0.8 */
++	fixed20_12 sclk, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	sclk.full = dfixed_const(wm->sclk);
++	sclk.full = dfixed_div(sclk, a);
++	a.full = dfixed_const(10);
++	return_efficiency.full = dfixed_const(8);
++	return_efficiency.full = dfixed_div(return_efficiency, a);
++	a.full = dfixed_const(32);
++	bandwidth.full = dfixed_mul(a, sclk);
++	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the dmif bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dmif bandwidth in MBytes/s
++ */
++static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
++{
++	/* Calculate the DMIF Request Bandwidth */
++	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
++	fixed20_12 disp_clk, bandwidth;
++	fixed20_12 a, b;
++
++	a.full = dfixed_const(1000);
++	disp_clk.full = dfixed_const(wm->disp_clk);
++	disp_clk.full = dfixed_div(disp_clk, a);
++	a.full = dfixed_const(32);
++	b.full = dfixed_mul(a, disp_clk);
++
++	a.full = dfixed_const(10);
++	disp_clk_request_efficiency.full = dfixed_const(8);
++	disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
++
++	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v8_0_available_bandwidth - get the min available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the min available bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the min available bandwidth in MBytes/s
++ */
++static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
++{
++	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
++	u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
++	u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
++	u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
++
++	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
++}
++
++/**
++ * dce_v8_0_average_bandwidth - get the average available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the average available bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the average available bandwidth in MBytes/s
++ */
++static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
++{
++	/* Calculate the display mode Average Bandwidth
++	 * DisplayMode should contain the source and destination dimensions,
++	 * timing, etc.
++	 */
++	fixed20_12 bpp;
++	fixed20_12 line_time;
++	fixed20_12 src_width;
++	fixed20_12 bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
++	line_time.full = dfixed_div(line_time, a);
++	bpp.full = dfixed_const(wm->bytes_per_pixel);
++	src_width.full = dfixed_const(wm->src_width);
++	bandwidth.full = dfixed_mul(src_width, bpp);
++	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
++	bandwidth.full = dfixed_div(bandwidth, line_time);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v8_0_latency_watermark - get the latency watermark
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the latency watermark (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the latency watermark in ns
++ */
++static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
++{
++	/* First calculate the latency in ns */
++	u32 mc_latency = 2000; /* 2000 ns. */
++	u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
++	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
++	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
++	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
++	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
++		(wm->num_heads * cursor_line_pair_return_time);
++	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
++	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
++	u32 tmp, dmif_size = 12288;
++	fixed20_12 a, b, c;
++
++	if (wm->num_heads == 0)
++		return 0;
++
++	a.full = dfixed_const(2);
++	b.full = dfixed_const(1);
++	if ((wm->vsc.full > a.full) ||
++	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
++	    (wm->vtaps >= 5) ||
++	    ((wm->vsc.full >= a.full) && wm->interlaced))
++		max_src_lines_per_dst_line = 4;
++	else
++		max_src_lines_per_dst_line = 2;
++
++	a.full = dfixed_const(available_bandwidth);
++	b.full = dfixed_const(wm->num_heads);
++	a.full = dfixed_div(a, b);
++
++	b.full = dfixed_const(mc_latency + 512);
++	c.full = dfixed_const(wm->disp_clk);
++	b.full = dfixed_div(b, c);
++
++	c.full = dfixed_const(dmif_size);
++	b.full = dfixed_div(c, b);
++
++	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
++
++	b.full = dfixed_const(1000);
++	c.full = dfixed_const(wm->disp_clk);
++	b.full = dfixed_div(c, b);
++	c.full = dfixed_const(wm->bytes_per_pixel);
++	b.full = dfixed_mul(b, c);
++
++	lb_fill_bw = min(tmp, dfixed_trunc(b));
++
++	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
++	b.full = dfixed_const(1000);
++	c.full = dfixed_const(lb_fill_bw);
++	b.full = dfixed_div(c, b);
++	a.full = dfixed_div(a, b);
++	line_fill_time = dfixed_trunc(a);
++
++	if (line_fill_time < wm->active_time)
++		return latency;
++	else
++		return latency + (line_fill_time - wm->active_time);
++
++}
++
++/**
++ * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
++ * average and available dram bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Check if the display average bandwidth fits in the display
++ * dram bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
++{
++	if (dce_v8_0_average_bandwidth(wm) <=
++	    (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
++ * average and available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Check if the display average bandwidth fits in the display
++ * available bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
++{
++	if (dce_v8_0_average_bandwidth(wm) <=
++	    (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v8_0_check_latency_hiding - check latency hiding
++ *
++ * @wm: watermark calculation data
++ *
++ * Check latency hiding (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
++{
++	u32 lb_partitions = wm->lb_size / wm->src_width;
++	u32 line_time = wm->active_time + wm->blank_time;
++	u32 latency_tolerant_lines;
++	u32 latency_hiding;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1);
++	if (wm->vsc.full > a.full)
++		latency_tolerant_lines = 1;
++	else {
++		if (lb_partitions <= (wm->vtaps + 1))
++			latency_tolerant_lines = 1;
++		else
++			latency_tolerant_lines = 2;
++	}
++
++	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
++
++	if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v8_0_program_watermarks - program display watermarks
++ *
++ * @adev: amdgpu_device pointer
++ * @amdgpu_crtc: the selected display controller
++ * @lb_size: line buffer size
++ * @num_heads: number of display controllers in use
++ *
++ * Calculate and program the display watermarks for the
++ * selected display controller (CIK).
++ */
++static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
++					struct amdgpu_crtc *amdgpu_crtc,
++					u32 lb_size, u32 num_heads)
++{
++	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
++	struct dce8_wm_params wm_low, wm_high;
++	u32 pixel_period;
++	u32 line_time = 0;
++	u32 latency_watermark_a = 0, latency_watermark_b = 0;
++	u32 tmp, wm_mask;
++
++	if (amdgpu_crtc->base.enabled && num_heads && mode) {
++		pixel_period = 1000000 / (u32)mode->clock;
++		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
++
++		/* watermark for high clocks */
++		if (adev->pm.dpm_enabled) {
++			wm_high.yclk =
++				amdgpu_dpm_get_mclk(adev, false) * 10;
++			wm_high.sclk =
++				amdgpu_dpm_get_sclk(adev, false) * 10;
++		} else {
++			wm_high.yclk = adev->pm.current_mclk * 10;
++			wm_high.sclk = adev->pm.current_sclk * 10;
++		}
++
++		wm_high.disp_clk = mode->clock;
++		wm_high.src_width = mode->crtc_hdisplay;
++		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
++		wm_high.blank_time = line_time - wm_high.active_time;
++		wm_high.interlaced = false;
++		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++			wm_high.interlaced = true;
++		wm_high.vsc = amdgpu_crtc->vsc;
++		wm_high.vtaps = 1;
++		if (amdgpu_crtc->rmx_type != RMX_OFF)
++			wm_high.vtaps = 2;
++		wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
++		wm_high.lb_size = lb_size;
++		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
++		wm_high.num_heads = num_heads;
++
++		/* set for high clocks */
++		latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
++
++		/* possibly force display priority to high */
++		/* should really do this at mode validation time... */
++		if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
++		    !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
++		    !dce_v8_0_check_latency_hiding(&wm_high) ||
++		    (adev->mode_info.disp_priority == 2)) {
++			DRM_DEBUG_KMS("force priority to high\n");
++		}
++
++		/* watermark for low clocks */
++		if (adev->pm.dpm_enabled) {
++			wm_low.yclk =
++				amdgpu_dpm_get_mclk(adev, true) * 10;
++			wm_low.sclk =
++				amdgpu_dpm_get_sclk(adev, true) * 10;
++		} else {
++			wm_low.yclk = adev->pm.current_mclk * 10;
++			wm_low.sclk = adev->pm.current_sclk * 10;
++		}
++
++		wm_low.disp_clk = mode->clock;
++		wm_low.src_width = mode->crtc_hdisplay;
++		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
++		wm_low.blank_time = line_time - wm_low.active_time;
++		wm_low.interlaced = false;
++		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++			wm_low.interlaced = true;
++		wm_low.vsc = amdgpu_crtc->vsc;
++		wm_low.vtaps = 1;
++		if (amdgpu_crtc->rmx_type != RMX_OFF)
++			wm_low.vtaps = 2;
++		wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
++		wm_low.lb_size = lb_size;
++		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
++		wm_low.num_heads = num_heads;
++
++		/* set for low clocks */
++		latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
++
++		/* possibly force display priority to high */
++		/* should really do this at mode validation time... */
++		if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
++		    !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
++		    !dce_v8_0_check_latency_hiding(&wm_low) ||
++		    (adev->mode_info.disp_priority == 2)) {
++			DRM_DEBUG_KMS("force priority to high\n");
++		}
++	}
++
++	/* select wm A */
++	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = wm_mask;
++	tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
++	tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
++		(line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
++	/* select wm B */
++	tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
++	tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
++		(line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
++	/* restore original selection */
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
++
++	/* save values for DPM */
++	amdgpu_crtc->line_time = line_time;
++	amdgpu_crtc->wm_high = latency_watermark_a;
++	amdgpu_crtc->wm_low = latency_watermark_b;
++}
++
++/**
++ * dce_v8_0_bandwidth_update - program display watermarks
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Calculate and program the display watermarks and line
++ * buffer allocation (CIK).
++ */
++static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
++{
++	struct drm_display_mode *mode = NULL;
++	u32 num_heads = 0, lb_size;
++	int i;
++
++	amdgpu_update_display_priority(adev);
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (adev->mode_info.crtcs[i]->base.enabled)
++			num_heads++;
++	}
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		mode = &adev->mode_info.crtcs[i]->base.mode;
++		lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
++		dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
++					    lb_size, num_heads);
++	}
++}
++
++static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
++{
++	int i;
++	u32 offset, tmp;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		offset = adev->mode_info.audio.pin[i].offset;
++		tmp = RREG32_AUDIO_ENDPT(offset,
++					 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
++		if (((tmp &
++		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
++		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
++			adev->mode_info.audio.pin[i].connected = false;
++		else
++			adev->mode_info.audio.pin[i].connected = true;
++	}
++}
++
++static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v8_0_audio_get_connected_pins(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		if (adev->mode_info.audio.pin[i].connected)
++			return &adev->mode_info.audio.pin[i];
++	}
++	DRM_ERROR("No connected audio pins found!\n");
++	return NULL;
++}
++
++static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u32 offset;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	offset = dig->afmt->offset;
++
++	WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
++	       (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
++}
++
++static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
++						struct drm_display_mode *mode)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	u32 tmp = 0, offset;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	offset = dig->afmt->pin->offset;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
++		if (connector->latency_present[1])
++			tmp =
++			(connector->video_latency[1] <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
++			(connector->audio_latency[1] <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
++		else
++			tmp =
++			(0 <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
++			(0 <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
++	} else {
++		if (connector->latency_present[0])
++			tmp =
++			(connector->video_latency[0] <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
++			(connector->audio_latency[0] <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
++		else
++			tmp =
++			(0 <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
++			(0 <<
++			 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
++
++	}
++	WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
++}
++
++static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	u32 offset, tmp;
++	u8 *sadb = NULL;
++	int sad_count;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	offset = dig->afmt->pin->offset;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
++	if (sad_count < 0) {
++		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
++		sad_count = 0;
++	}
++
++	/* program the speaker allocation */
++	tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
++	tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
++		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
++	/* set HDMI mode */
++	tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
++	if (sad_count)
++		tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
++	else
++		tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
++	WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
++
++	kfree(sadb);
++}
++
++static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u32 offset;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	struct cea_sad *sads;
++	int i, sad_count;
++
++	static const u16 eld_reg_to_type[][2] = {
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
++	};
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	offset = dig->afmt->pin->offset;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
++	if (sad_count <= 0) {
++		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++		return;
++	}
++	BUG_ON(!sads);
++
++	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
++		u32 value = 0;
++		u8 stereo_freqs = 0;
++		int max_channels = -1;
++		int j;
++
++		for (j = 0; j < sad_count; j++) {
++			struct cea_sad *sad = &sads[j];
++
++			if (sad->format == eld_reg_to_type[i][1]) {
++				if (sad->channels > max_channels) {
++				value = (sad->channels <<
++				 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
++				(sad->byte2 <<
++				 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
++				(sad->freq <<
++				 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
++				max_channels = sad->channels;
++				}
++
++				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
++					stereo_freqs |= sad->freq;
++				else
++					break;
++			}
++		}
++
++		value |= (stereo_freqs <<
++			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
++
++		WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
++	}
++
++	kfree(sads);
++}
++
++static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
++				  struct amdgpu_audio_pin *pin,
++				  bool enable)
++{
++	if (!pin)
++		return;
++
++	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
++		enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
++}
++
++static const u32 pin_offsets[7] =
++{
++	(0x1780 - 0x1780),
++	(0x1786 - 0x1780),
++	(0x178c - 0x1780),
++	(0x1792 - 0x1780),
++	(0x1798 - 0x1780),
++	(0x179d - 0x1780),
++	(0x17a4 - 0x1780),
++};
++
++static int dce_v8_0_audio_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (!amdgpu_audio)
++		return 0;
++
++	adev->mode_info.audio.enabled = true;
++
++	if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
++		adev->mode_info.audio.num_pins = 7;
++	else if ((adev->asic_type == CHIP_KABINI) ||
++		 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
++		adev->mode_info.audio.num_pins = 3;
++	else if ((adev->asic_type == CHIP_BONAIRE) ||
++		 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
++		adev->mode_info.audio.num_pins = 7;
++	else
++		adev->mode_info.audio.num_pins = 3;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		adev->mode_info.audio.pin[i].channels = -1;
++		adev->mode_info.audio.pin[i].rate = -1;
++		adev->mode_info.audio.pin[i].bits_per_sample = -1;
++		adev->mode_info.audio.pin[i].status_bits = 0;
++		adev->mode_info.audio.pin[i].category_code = 0;
++		adev->mode_info.audio.pin[i].connected = false;
++		adev->mode_info.audio.pin[i].offset = pin_offsets[i];
++		adev->mode_info.audio.pin[i].id = i;
++		/* disable audio.  it will be set up later */
++		/* XXX remove once we switch to ip funcs */
++		dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (!adev->mode_info.audio.enabled)
++		return;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++)
++		dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++
++	adev->mode_info.audio.enabled = false;
++}
++
++/*
++ * update the N and CTS parameters for a given pixel clock rate
++ */
++static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	uint32_t offset = dig->afmt->offset;
++
++	WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
++	WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
++
++	WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
++	WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
++
++	WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
++	WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
++}
++
++/*
++ * build a HDMI Video Info Frame
++ */
++static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
++					       void *buffer, size_t size)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	uint32_t offset = dig->afmt->offset;
++	uint8_t *frame = buffer + 3;
++	uint8_t *header = buffer;
++
++	WREG32(mmAFMT_AVI_INFO0 + offset,
++		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
++	WREG32(mmAFMT_AVI_INFO1 + offset,
++		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
++	WREG32(mmAFMT_AVI_INFO2 + offset,
++		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
++	WREG32(mmAFMT_AVI_INFO3 + offset,
++		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
++}
++
++static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	u32 dto_phase = 24 * 1000;
++	u32 dto_modulo = clock;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* XXX two dtos; generally use dto0 for hdmi */
++	/* Express [24MHz / target pixel clock] as an exact rational
++	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
++	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
++	 */
++	WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
++	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
++	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
++}
++
++/*
++ * update the info frames with the data from the current display mode
++ */
++static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
++				  struct drm_display_mode *mode)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
++	struct hdmi_avi_infoframe frame;
++	uint32_t offset, val;
++	ssize_t err;
++	int bpc = 8;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* Silent, r600_hdmi_enable will raise WARN for us */
++	if (!dig->afmt->enabled)
++		return;
++	offset = dig->afmt->offset;
++
++	/* hdmi deep color mode general control packets setup, if bpc > 8 */
++	if (encoder->crtc) {
++		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++		bpc = amdgpu_crtc->bpc;
++	}
++
++	/* disable audio prior to setting up hw */
++	dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
++	dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
++
++	dce_v8_0_audio_set_dto(encoder, mode->clock);
++
++	WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
++	       HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
++
++	WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
++
++	val = RREG32(mmHDMI_CONTROL + offset);
++	val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
++	val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
++
++	switch (bpc) {
++	case 0:
++	case 6:
++	case 8:
++	case 16:
++	default:
++		DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
++			  connector->name, bpc);
++		break;
++	case 10:
++		val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
++		val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
++		DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
++			  connector->name);
++		break;
++	case 12:
++		val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
++		val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
++		DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
++			  connector->name);
++		break;
++	}
++
++	WREG32(mmHDMI_CONTROL + offset, val);
++
++	WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
++	       HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
++	       HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
++	       HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
++
++	WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
++	       HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
++	       HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
++
++	WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
++	       AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
++
++	WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
++	       (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
++
++	WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
++
++	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
++	       (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
++	       (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
++
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
++	       AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
++
++	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
++
++	if (bpc > 8)
++		WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
++		       HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
++	else
++		WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
++		       HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
++		       HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
++
++	dce_v8_0_afmt_update_ACR(encoder, mode->clock);
++
++	WREG32(mmAFMT_60958_0 + offset,
++	       (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
++
++	WREG32(mmAFMT_60958_1 + offset,
++	       (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
++
++	WREG32(mmAFMT_60958_2 + offset,
++	       (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
++	       (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
++	       (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
++	       (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
++	       (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
++	       (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
++
++	dce_v8_0_audio_write_speaker_allocation(encoder);
++
++
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
++	       (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
++
++	dce_v8_0_afmt_audio_select_pin(encoder);
++	dce_v8_0_audio_write_sad_regs(encoder);
++	dce_v8_0_audio_write_latency_fields(encoder, mode);
++
++	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
++	if (err < 0) {
++		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
++		return;
++	}
++
++	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
++	if (err < 0) {
++		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
++		return;
++	}
++
++	dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
++
++	WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
++		  HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
++		  HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */
++
++	WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
++		 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
++		 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
++
++	WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
++		  AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
++
++	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
++	WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
++	WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
++	WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
++	WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
++
++	/* enable audio after to setting up hw */
++	dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
++}
++
++static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* Silent, r600_hdmi_enable will raise WARN for us */
++	if (enable && dig->afmt->enabled)
++		return;
++	if (!enable && !dig->afmt->enabled)
++		return;
++
++	if (!enable && dig->afmt->pin) {
++		dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
++		dig->afmt->pin = NULL;
++	}
++
++	dig->afmt->enabled = enable;
++
++	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
++		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
++}
++
++static void dce_v8_0_afmt_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->mode_info.num_dig; i++)
++		adev->mode_info.afmt[i] = NULL;
++
++	/* DCE8 has audio blocks tied to DIG encoders */
++	for (i = 0; i < adev->mode_info.num_dig; i++) {
++		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
++		if (adev->mode_info.afmt[i]) {
++			adev->mode_info.afmt[i]->offset = dig_offsets[i];
++			adev->mode_info.afmt[i]->id = i;
++		}
++	}
++}
++
++static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->mode_info.num_dig; i++) {
++		kfree(adev->mode_info.afmt[i]);
++		adev->mode_info.afmt[i] = NULL;
++	}
++}
++
++static const u32 vga_control_regs[6] =
++{
++	mmD1VGA_CONTROL,
++	mmD2VGA_CONTROL,
++	mmD3VGA_CONTROL,
++	mmD4VGA_CONTROL,
++	mmD5VGA_CONTROL,
++	mmD6VGA_CONTROL,
++};
++
++static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u32 vga_control;
++
++	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
++	if (enable)
++		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
++	else
++		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
++}
++
++static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (enable)
++		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
++	else
++		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
++}
++
++static void dce_v8_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw,
++				   unsigned *bankh, unsigned *mtaspect,
++				   unsigned *tile_split)
++{
++	*bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK;
++	*bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK;
++	*mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
++	*tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK;
++	switch (*bankw) {
++	default:
++	case 1:
++		*bankw = ADDR_SURF_BANK_WIDTH_1;
++		break;
++	case 2:
++		*bankw = ADDR_SURF_BANK_WIDTH_2;
++		break;
++	case 4:
++		*bankw = ADDR_SURF_BANK_WIDTH_4;
++		break;
++	case 8:
++		*bankw = ADDR_SURF_BANK_WIDTH_8;
++		break;
++	}
++	switch (*bankh) {
++	default:
++	case 1:
++		*bankh = ADDR_SURF_BANK_HEIGHT_1;
++		break;
++	case 2:
++		*bankh = ADDR_SURF_BANK_HEIGHT_2;
++		break;
++	case 4:
++		*bankh = ADDR_SURF_BANK_HEIGHT_4;
++		break;
++	case 8:
++		*bankh = ADDR_SURF_BANK_HEIGHT_8;
++		break;
++	}
++	switch (*mtaspect) {
++	default:
++	case 1:
++		*mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_1;
++		break;
++	case 2:
++		*mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_2;
++		break;
++	case 4:
++		*mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_4;
++		break;
++	case 8:
++		*mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_8;
++		break;
++	}
++}
++
++static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
++				     struct drm_framebuffer *fb,
++				     int x, int y, int atomic)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_framebuffer *amdgpu_fb;
++	struct drm_framebuffer *target_fb;
++	struct drm_gem_object *obj;
++	struct amdgpu_bo *rbo;
++	uint64_t fb_location, tiling_flags;
++	uint32_t fb_format, fb_pitch_pixels;
++	unsigned bankw, bankh, mtaspect, tile_split;
++	u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++	u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f;
++	u32 tmp, viewport_w, viewport_h;
++	int r;
++	bool bypass_lut = false;
++
++	/* no fb bound */
++	if (!atomic && !crtc->primary->fb) {
++		DRM_DEBUG_KMS("No FB bound\n");
++		return 0;
++	}
++
++	if (atomic) {
++		amdgpu_fb = to_amdgpu_framebuffer(fb);
++		target_fb = fb;
++	}
++	else {
++		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++		target_fb = crtc->primary->fb;
++	}
++
++	/* If atomic, assume fb object is pinned & idle & fenced and
++	 * just update base pointers
++	 */
++	obj = amdgpu_fb->obj;
++	rbo = gem_to_amdgpu_bo(obj);
++	r = amdgpu_bo_reserve(rbo, false);
++	if (unlikely(r != 0))
++		return r;
++
++	if (atomic)
++		fb_location = amdgpu_bo_gpu_offset(rbo);
++	else {
++		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
++		if (unlikely(r != 0)) {
++			amdgpu_bo_unreserve(rbo);
++			return -EINVAL;
++		}
++	}
++
++	amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
++	amdgpu_bo_unreserve(rbo);
++
++	switch (target_fb->pixel_format) {
++	case DRM_FORMAT_C8:
++		fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++		break;
++	case DRM_FORMAT_XRGB4444:
++	case DRM_FORMAT_ARGB4444:
++		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		break;
++	case DRM_FORMAT_XRGB1555:
++	case DRM_FORMAT_ARGB1555:
++		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		break;
++	case DRM_FORMAT_BGRX5551:
++	case DRM_FORMAT_BGRA5551:
++		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		break;
++	case DRM_FORMAT_RGB565:
++		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		break;
++	case DRM_FORMAT_XRGB8888:
++	case DRM_FORMAT_ARGB8888:
++		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		break;
++	case DRM_FORMAT_XRGB2101010:
++	case DRM_FORMAT_ARGB2101010:
++		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
++		bypass_lut = true;
++		break;
++	case DRM_FORMAT_BGRX1010102:
++	case DRM_FORMAT_BGRA1010102:
++		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
++			     (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
++#ifdef __BIG_ENDIAN
++		fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
++#endif
++		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
++		bypass_lut = true;
++		break;
++	default:
++		DRM_ERROR("Unsupported screen format %s\n",
++			  drm_get_format_name(target_fb->pixel_format));
++		return -EINVAL;
++	}
++
++	if (tiling_flags & AMDGPU_TILING_MACRO) {
++		unsigned tileb, index, num_banks, tile_split_bytes;
++
++		dce_v8_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
++		/* Set NUM_BANKS. */
++		/* Calculate the macrotile mode index. */
++		tile_split_bytes = 64 << tile_split;
++		tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
++		tileb = min(tile_split_bytes, tileb);
++
++		for (index = 0; tileb > 64; index++) {
++			tileb >>= 1;
++		}
++
++		if (index >= 16) {
++			DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
++				  target_fb->bits_per_pixel, tile_split);
++			return -EINVAL;
++		}
++
++		num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3;
++		fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
++		fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
++		fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
++		fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
++		fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
++		fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
++		fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
++	} else if (tiling_flags & AMDGPU_TILING_MICRO) {
++		fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
++	}
++
++	/* Read the pipe config from the 2D TILED SCANOUT mode.
++	 * It should be the same for the other modes too, but not all
++	 * modes set the pipe config field. */
++	fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
++
++	dce_v8_0_vga_enable(crtc, false);
++
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(fb_location));
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(fb_location));
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
++	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
++	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
++
++	/*
++	 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
++	 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
++	 * retain the full precision throughout the pipeline.
++	 */
++	WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
++		 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
++		 ~LUT_10BIT_BYPASS_EN);
++
++	if (bypass_lut)
++		DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
++
++	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
++	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
++
++	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
++
++	dce_v8_0_grph_enable(crtc, true);
++
++	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
++	       target_fb->height);
++
++	x &= ~3;
++	y &= ~1;
++	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
++	       (x << 16) | y);
++	viewport_w = crtc->mode.hdisplay;
++	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
++	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
++	       (viewport_w << 16) | viewport_h);
++
++	/* pageflip setup */
++	/* make sure flip is at vb rather than hb */
++	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK;
++	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	/* set pageflip to happen only at start of vblank interval (front porch) */
++	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
++
++	if (!atomic && fb && fb != crtc->primary->fb) {
++		amdgpu_fb = to_amdgpu_framebuffer(fb);
++		rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
++		r = amdgpu_bo_reserve(rbo, false);
++		if (unlikely(r != 0))
++			return r;
++		amdgpu_bo_unpin(rbo);
++		amdgpu_bo_unreserve(rbo);
++	}
++
++	/* Bytes per pixel may have changed */
++	dce_v8_0_bandwidth_update(adev);
++
++	return 0;
++}
++
++static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
++				    struct drm_display_mode *mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
++		       LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
++	else
++		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
++}
++
++static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int i;
++
++	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
++
++	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
++		(INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
++	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
++	       PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
++	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
++	       PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
++	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
++		(INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
++
++	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
++
++	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
++
++	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
++	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
++	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
++
++	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
++
++	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
++	for (i = 0; i < 256; i++) {
++		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
++		       (amdgpu_crtc->lut_r[i] << 20) |
++		       (amdgpu_crtc->lut_g[i] << 10) |
++		       (amdgpu_crtc->lut_b[i] << 0));
++	}
++
++	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
++		(DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
++		(DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
++	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
++		(GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
++	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
++		(REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
++	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
++	       ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
++		(OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
++	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
++	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
++	/* XXX this only needs to be programmed once per crtc at startup,
++	 * not sure where the best place for it is
++	 */
++	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
++	       ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
++}
++
++static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++		if (dig->linkb)
++			return 1;
++		else
++			return 0;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++		if (dig->linkb)
++			return 3;
++		else
++			return 2;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++		if (dig->linkb)
++			return 5;
++		else
++			return 4;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		return 6;
++		break;
++	default:
++		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
++		return 0;
++	}
++}
++
++/**
++ * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
++ *
++ * @crtc: drm crtc
++ *
++ * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
++ * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
++ * monitors a dedicated PPLL must be used.  If a particular board has
++ * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
++ * as there is no need to program the PLL itself.  If we are not able to
++ * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
++ * avoid messing up an existing monitor.
++ *
++ * Asic specific PLL information
++ *
++ * DCE 8.x
++ * KB/KV
++ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
++ * CI
++ * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
++ *
++ */
++static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u32 pll_in_use;
++	int pll;
++
++	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
++		if (adev->clock.dp_extclk)
++			/* skip PPLL programming if using ext clock */
++			return ATOM_PPLL_INVALID;
++		else {
++			/* use the same PPLL for all DP monitors */
++			pll = amdgpu_pll_get_shared_dp_ppll(crtc);
++			if (pll != ATOM_PPLL_INVALID)
++				return pll;
++		}
++	} else {
++		/* use the same PPLL for all monitors with the same clock */
++		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
++		if (pll != ATOM_PPLL_INVALID)
++			return pll;
++	}
++	/* otherwise, pick one of the plls */
++	if ((adev->asic_type == CHIP_KABINI) ||
++	    (adev->asic_type == CHIP_MULLINS)) {
++		/* KB/ML has PPLL1 and PPLL2 */
++		pll_in_use = amdgpu_pll_get_use_mask(crtc);
++		if (!(pll_in_use & (1 << ATOM_PPLL2)))
++			return ATOM_PPLL2;
++		if (!(pll_in_use & (1 << ATOM_PPLL1)))
++			return ATOM_PPLL1;
++		DRM_ERROR("unable to allocate a PPLL\n");
++		return ATOM_PPLL_INVALID;
++	} else {
++		/* CI/KV has PPLL0, PPLL1, and PPLL2 */
++		pll_in_use = amdgpu_pll_get_use_mask(crtc);
++		if (!(pll_in_use & (1 << ATOM_PPLL2)))
++			return ATOM_PPLL2;
++		if (!(pll_in_use & (1 << ATOM_PPLL1)))
++			return ATOM_PPLL1;
++		if (!(pll_in_use & (1 << ATOM_PPLL0)))
++			return ATOM_PPLL0;
++		DRM_ERROR("unable to allocate a PPLL\n");
++		return ATOM_PPLL_INVALID;
++	}
++	return ATOM_PPLL_INVALID;
++}
++
++static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
++{
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	uint32_t cur_lock;
++
++	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
++	if (lock)
++		cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
++	else
++		cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
++	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
++}
++
++static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++
++	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
++		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
++		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
++}
++
++static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++
++	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
++		   CUR_CONTROL__CURSOR_EN_MASK |
++		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
++		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
++}
++
++static void dce_v8_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
++			      uint64_t gpu_addr)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++
++	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(gpu_addr));
++	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       gpu_addr & 0xffffffff);
++}
++
++static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
++				     int x, int y)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	int xorigin = 0, yorigin = 0;
++
++	/* avivo cursor are offset into the total surface */
++	x += crtc->x;
++	y += crtc->y;
++	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
++
++	if (x < 0) {
++		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
++		x = 0;
++	}
++	if (y < 0) {
++		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
++		y = 0;
++	}
++
++	dce_v8_0_lock_cursor(crtc, true);
++	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
++	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
++	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
++	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
++	dce_v8_0_lock_cursor(crtc, false);
++
++	return 0;
++}
++
++static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc,
++				    struct drm_file *file_priv,
++				    uint32_t handle,
++				    uint32_t width,
++				    uint32_t height)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_gem_object *obj;
++	struct amdgpu_bo *robj;
++	uint64_t gpu_addr;
++	int ret;
++
++	if (!handle) {
++		/* turn off cursor */
++		dce_v8_0_hide_cursor(crtc);
++		obj = NULL;
++		goto unpin;
++	}
++
++	if ((width > amdgpu_crtc->max_cursor_width) ||
++	    (height > amdgpu_crtc->max_cursor_height)) {
++		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
++		return -EINVAL;
++	}
++
++	obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
++	if (!obj) {
++		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
++		return -ENOENT;
++	}
++
++	robj = gem_to_amdgpu_bo(obj);
++	ret = amdgpu_bo_reserve(robj, false);
++	if (unlikely(ret != 0))
++		goto fail;
++	ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
++				       0, &gpu_addr);
++	amdgpu_bo_unreserve(robj);
++	if (ret)
++		goto fail;
++
++	amdgpu_crtc->cursor_width = width;
++	amdgpu_crtc->cursor_height = height;
++
++	dce_v8_0_lock_cursor(crtc, true);
++	dce_v8_0_set_cursor(crtc, obj, gpu_addr);
++	dce_v8_0_show_cursor(crtc);
++	dce_v8_0_lock_cursor(crtc, false);
++
++unpin:
++	if (amdgpu_crtc->cursor_bo) {
++		robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
++		ret = amdgpu_bo_reserve(robj, false);
++		if (likely(ret == 0)) {
++			amdgpu_bo_unpin(robj);
++			amdgpu_bo_unreserve(robj);
++		}
++		drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
++	}
++
++	amdgpu_crtc->cursor_bo = obj;
++	return 0;
++fail:
++	drm_gem_object_unreference_unlocked(obj);
++
++	return ret;
++}
++
++static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
++				    u16 *blue, uint32_t start, uint32_t size)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	int end = (start + size > 256) ? 256 : start + size, i;
++
++	/* userspace palettes are always correct as is */
++	for (i = start; i < end; i++) {
++		amdgpu_crtc->lut_r[i] = red[i] >> 6;
++		amdgpu_crtc->lut_g[i] = green[i] >> 6;
++		amdgpu_crtc->lut_b[i] = blue[i] >> 6;
++	}
++	dce_v8_0_crtc_load_lut(crtc);
++}
++
++static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	drm_crtc_cleanup(crtc);
++	destroy_workqueue(amdgpu_crtc->pflip_queue);
++	kfree(amdgpu_crtc);
++}
++
++static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
++	.cursor_set = dce_v8_0_crtc_cursor_set,
++	.cursor_move = dce_v8_0_crtc_cursor_move,
++	.gamma_set = dce_v8_0_crtc_gamma_set,
++	.set_config = amdgpu_crtc_set_config,
++	.destroy = dce_v8_0_crtc_destroy,
++	.page_flip = amdgpu_crtc_page_flip,
++};
++
++static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	switch (mode) {
++	case DRM_MODE_DPMS_ON:
++		amdgpu_crtc->enabled = true;
++		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
++		dce_v8_0_vga_enable(crtc, true);
++		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
++		dce_v8_0_vga_enable(crtc, false);
++		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
++		dce_v8_0_crtc_load_lut(crtc);
++		break;
++	case DRM_MODE_DPMS_STANDBY:
++	case DRM_MODE_DPMS_SUSPEND:
++	case DRM_MODE_DPMS_OFF:
++		drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
++		if (amdgpu_crtc->enabled) {
++			dce_v8_0_vga_enable(crtc, true);
++			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
++			dce_v8_0_vga_enable(crtc, false);
++		}
++		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
++		amdgpu_crtc->enabled = false;
++		break;
++	}
++	/* adjust pm to dpms */
++	amdgpu_pm_compute_clocks(adev);
++}
++
++static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
++{
++	/* disable crtc pair power gating before programming */
++	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
++	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
++	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++}
++
++static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
++{
++	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
++	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
++}
++
++static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_atom_ss ss;
++	int i;
++
++	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++	if (crtc->primary->fb) {
++		int r;
++		struct amdgpu_framebuffer *amdgpu_fb;
++		struct amdgpu_bo *rbo;
++
++		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++		rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
++		r = amdgpu_bo_reserve(rbo, false);
++		if (unlikely(r))
++			DRM_ERROR("failed to reserve rbo before unpin\n");
++		else {
++			amdgpu_bo_unpin(rbo);
++			amdgpu_bo_unreserve(rbo);
++		}
++	}
++	/* disable the GRPH */
++	dce_v8_0_grph_enable(crtc, false);
++
++	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (adev->mode_info.crtcs[i] &&
++		    adev->mode_info.crtcs[i]->enabled &&
++		    i != amdgpu_crtc->crtc_id &&
++		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
++			/* one other crtc is using this pll don't turn
++			 * off the pll
++			 */
++			goto done;
++		}
++	}
++
++	switch (amdgpu_crtc->pll_id) {
++	case ATOM_PPLL1:
++	case ATOM_PPLL2:
++		/* disable the ppll */
++		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
++					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
++		break;
++	case ATOM_PPLL0:
++		/* disable the ppll */
++		if ((adev->asic_type == CHIP_KAVERI) ||
++		    (adev->asic_type == CHIP_BONAIRE) ||
++		    (adev->asic_type == CHIP_HAWAII))
++			amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
++						  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
++		break;
++	default:
++		break;
++	}
++done:
++	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
++	amdgpu_crtc->adjusted_clock = 0;
++	amdgpu_crtc->encoder = NULL;
++	amdgpu_crtc->connector = NULL;
++}
++
++static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode,
++				  struct drm_display_mode *adjusted_mode,
++				  int x, int y, struct drm_framebuffer *old_fb)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	if (!amdgpu_crtc->adjusted_clock)
++		return -EINVAL;
++
++	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
++	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
++	dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
++	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
++	amdgpu_atombios_crtc_scaler_setup(crtc);
++	/* update the hw version fpr dpm */
++	amdgpu_crtc->hw_mode = *adjusted_mode;
++
++	return 0;
++}
++
++static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
++				     const struct drm_display_mode *mode,
++				     struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct drm_encoder *encoder;
++
++	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		if (encoder->crtc == crtc) {
++			amdgpu_crtc->encoder = encoder;
++			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
++			break;
++		}
++	}
++	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
++		amdgpu_crtc->encoder = NULL;
++		amdgpu_crtc->connector = NULL;
++		return false;
++	}
++	if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
++		return false;
++	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
++		return false;
++	/* pick pll */
++	amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
++	/* if we can't get a PPLL for a non-DP encoder, fail */
++	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
++	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
++		return false;
++
++	return true;
++}
++
++static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
++				  struct drm_framebuffer *old_fb)
++{
++	return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
++}
++
++static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
++					 struct drm_framebuffer *fb,
++					 int x, int y, enum mode_set_atomic state)
++{
++       return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
++}
++
++static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
++	.dpms = dce_v8_0_crtc_dpms,
++	.mode_fixup = dce_v8_0_crtc_mode_fixup,
++	.mode_set = dce_v8_0_crtc_mode_set,
++	.mode_set_base = dce_v8_0_crtc_set_base,
++	.mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
++	.prepare = dce_v8_0_crtc_prepare,
++	.commit = dce_v8_0_crtc_commit,
++	.load_lut = dce_v8_0_crtc_load_lut,
++	.disable = dce_v8_0_crtc_disable,
++};
++
++static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
++{
++	struct amdgpu_crtc *amdgpu_crtc;
++	int i;
++
++	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
++			      (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
++	if (amdgpu_crtc == NULL)
++		return -ENOMEM;
++
++	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
++
++	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
++	amdgpu_crtc->crtc_id = index;
++	amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
++	adev->mode_info.crtcs[index] = amdgpu_crtc;
++
++	amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
++	amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
++	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
++	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
++
++	for (i = 0; i < 256; i++) {
++		amdgpu_crtc->lut_r[i] = i << 2;
++		amdgpu_crtc->lut_g[i] = i << 2;
++		amdgpu_crtc->lut_b[i] = i << 2;
++	}
++
++	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
++
++	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
++	amdgpu_crtc->adjusted_clock = 0;
++	amdgpu_crtc->encoder = NULL;
++	amdgpu_crtc->connector = NULL;
++	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
++
++	return 0;
++}
++
++static int dce_v8_0_early_init(struct amdgpu_device *adev)
++{
++	adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
++	adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
++
++	dce_v8_0_set_display_funcs(adev);
++	dce_v8_0_set_irq_funcs(adev);
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++	case CHIP_HAWAII:
++		adev->mode_info.num_crtc = 6;
++		adev->mode_info.num_hpd = 6;
++		adev->mode_info.num_dig = 6;
++		break;
++	case CHIP_KAVERI:
++		adev->mode_info.num_crtc = 4;
++		adev->mode_info.num_hpd = 6;
++		adev->mode_info.num_dig = 7;
++		break;
++	case CHIP_KABINI:
++	case CHIP_MULLINS:
++		adev->mode_info.num_crtc = 2;
++		adev->mode_info.num_hpd = 6;
++		adev->mode_info.num_dig = 6; /* ? */
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int dce_v8_0_sw_init(struct amdgpu_device *adev)
++{
++	int r, i;
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
++		if (r)
++			return r;
++	}
++
++	for (i = 8; i < 20; i += 2) {
++		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
++		if (r)
++			return r;
++	}
++
++	/* HPD hotplug */
++	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
++	if (r)
++		return r;
++
++	adev->mode_info.mode_config_initialized = true;
++
++	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
++
++	adev->ddev->mode_config.max_width = 16384;
++	adev->ddev->mode_config.max_height = 16384;
++
++	adev->ddev->mode_config.preferred_depth = 24;
++	adev->ddev->mode_config.prefer_shadow = 1;
++
++	adev->ddev->mode_config.fb_base = adev->mc.aper_base;
++
++	r = amdgpu_modeset_create_props(adev);
++	if (r)
++		return r;
++
++	adev->ddev->mode_config.max_width = 16384;
++	adev->ddev->mode_config.max_height = 16384;
++
++	/* allocate crtcs */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		r = dce_v8_0_crtc_init(adev, i);
++		if (r)
++			return r;
++	}
++
++	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
++		amdgpu_print_display_setup(adev->ddev);
++	else
++		return -EINVAL;
++
++	/* setup afmt */
++	dce_v8_0_afmt_init(adev);
++
++	r = dce_v8_0_audio_init(adev);
++	if (r)
++		return r;
++
++	drm_kms_helper_poll_init(adev->ddev);
++
++	return r;
++}
++
++static int dce_v8_0_sw_fini(struct amdgpu_device *adev)
++{
++	kfree(adev->mode_info.bios_hardcoded_edid);
++
++	drm_kms_helper_poll_fini(adev->ddev);
++
++	dce_v8_0_audio_fini(adev);
++
++	dce_v8_0_afmt_fini(adev);
++
++	drm_mode_config_cleanup(adev->ddev);
++	adev->mode_info.mode_config_initialized = false;
++
++	return 0;
++}
++
++static int dce_v8_0_hw_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	/* init dig PHYs, disp eng pll */
++	amdgpu_atombios_encoder_init_dig(adev);
++	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
++
++	/* initialize hpd */
++	dce_v8_0_hpd_init(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static int dce_v8_0_hw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v8_0_hpd_fini(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static int dce_v8_0_suspend(struct amdgpu_device *adev)
++{
++	struct drm_connector *connector;
++
++	drm_kms_helper_poll_disable(adev->ddev);
++
++	/* turn off display hw */
++	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
++	}
++
++	amdgpu_atombios_scratch_regs_save(adev);
++
++	dce_v8_0_hpd_fini(adev);
++
++	return 0;
++}
++
++static int dce_v8_0_resume(struct amdgpu_device *adev)
++{
++	struct drm_connector *connector;
++
++	amdgpu_atombios_scratch_regs_restore(adev);
++
++	/* init dig PHYs, disp eng pll */
++	amdgpu_atombios_encoder_init_dig(adev);
++	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
++	/* turn on the BL */
++	if (adev->mode_info.bl_encoder) {
++		u8 bl_level = amdgpu_display_backlight_get_level(adev,
++								  adev->mode_info.bl_encoder);
++		amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
++						    bl_level);
++	}
++
++	/* initialize hpd */
++	dce_v8_0_hpd_init(adev);
++
++	/* blat the mode back in */
++	drm_helper_resume_force_mode(adev->ddev);
++	/* turn on display hw */
++	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
++	}
++
++	drm_kms_helper_poll_enable(adev->ddev);
++
++	return 0;
++}
++
++static bool dce_v8_0_is_idle(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return true;
++}
++
++static int dce_v8_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return 0;
++}
++
++static void dce_v8_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "DCE 8.x registers\n");
++	/* XXX todo */
++}
++
++static int dce_v8_0_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0, tmp;
++
++	if (dce_v8_0_is_display_hung(adev))
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
++
++	if (srbm_soft_reset) {
++		dce_v8_0_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++		dce_v8_0_print_status(adev);
++	}
++	return 0;
++}
++
++static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
++						     int crtc,
++						     enum amdgpu_interrupt_state state)
++{
++	u32 reg_block, lb_interrupt_mask;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (crtc) {
++	case 0:
++		reg_block = CRTC0_REGISTER_OFFSET;
++		break;
++	case 1:
++		reg_block = CRTC1_REGISTER_OFFSET;
++		break;
++	case 2:
++		reg_block = CRTC2_REGISTER_OFFSET;
++		break;
++	case 3:
++		reg_block = CRTC3_REGISTER_OFFSET;
++		break;
++	case 4:
++		reg_block = CRTC4_REGISTER_OFFSET;
++		break;
++	case 5:
++		reg_block = CRTC5_REGISTER_OFFSET;
++		break;
++	default:
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
++		lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
++		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
++		lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
++		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
++		break;
++	default:
++		break;
++	}
++}
++
++static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
++						    int crtc,
++						    enum amdgpu_interrupt_state state)
++{
++	u32 reg_block, lb_interrupt_mask;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (crtc) {
++	case 0:
++		reg_block = CRTC0_REGISTER_OFFSET;
++		break;
++	case 1:
++		reg_block = CRTC1_REGISTER_OFFSET;
++		break;
++	case 2:
++		reg_block = CRTC2_REGISTER_OFFSET;
++		break;
++	case 3:
++		reg_block = CRTC3_REGISTER_OFFSET;
++		break;
++	case 4:
++		reg_block = CRTC4_REGISTER_OFFSET;
++		break;
++	case 5:
++		reg_block = CRTC5_REGISTER_OFFSET;
++		break;
++	default:
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
++		lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
++		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
++		lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
++		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
++		break;
++	default:
++		break;
++	}
++}
++
++static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
++					    struct amdgpu_irq_src *src,
++					    unsigned type,
++					    enum amdgpu_interrupt_state state)
++{
++	u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
++
++	switch (type) {
++	case AMDGPU_HPD_1:
++		dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
++		break;
++	case AMDGPU_HPD_2:
++		dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
++		break;
++	case AMDGPU_HPD_3:
++		dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
++		break;
++	case AMDGPU_HPD_4:
++		dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
++		break;
++	case AMDGPU_HPD_5:
++		dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
++		break;
++	case AMDGPU_HPD_6:
++		dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
++		break;
++	default:
++		DRM_DEBUG("invalid hdp %d\n", type);
++		return 0;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
++		dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
++		WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
++		dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
++		WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
++					     struct amdgpu_irq_src *src,
++					     unsigned type,
++					     enum amdgpu_interrupt_state state)
++{
++	switch (type) {
++	case AMDGPU_CRTC_IRQ_VBLANK1:
++		dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK2:
++		dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK3:
++		dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK4:
++		dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK5:
++		dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK6:
++		dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE1:
++		dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE2:
++		dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE3:
++		dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE4:
++		dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE5:
++		dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE6:
++		dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
++			     struct amdgpu_irq_src *source,
++			     struct amdgpu_iv_entry *entry)
++{
++	unsigned crtc = entry->src_id - 1;
++	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
++	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
++
++	switch (entry->src_data) {
++	case 0: /* vblank */
++		if (disp_int & interrupt_status_offsets[crtc].vblank) {
++			WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
++			if (amdgpu_irq_enabled(adev, source, irq_type)) {
++				drm_handle_vblank(adev->ddev, crtc);
++			}
++			DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
++		}
++		break;
++	case 1: /* vline */
++		if (disp_int & interrupt_status_offsets[crtc].vline) {
++			WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
++			DRM_DEBUG("IH: D%d vline\n", crtc + 1);
++		}
++		break;
++	default:
++		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
++		break;
++	}
++
++	return 0;
++}
++
++static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
++						 struct amdgpu_irq_src *src,
++						 unsigned type,
++						 enum amdgpu_interrupt_state state)
++{
++	u32 reg, reg_block;
++	/* now deal with page flip IRQ */
++	switch (type) {
++		case AMDGPU_PAGEFLIP_IRQ_D1:
++			reg_block = CRTC0_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D2:
++			reg_block = CRTC1_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D3:
++			reg_block = CRTC2_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D4:
++			reg_block = CRTC3_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D5:
++			reg_block = CRTC4_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D6:
++			reg_block = CRTC5_REGISTER_OFFSET;
++			break;
++		default:
++			DRM_ERROR("invalid pageflip crtc %d\n", type);
++			return -EINVAL;
++	}
++
++	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
++	if (state == AMDGPU_IRQ_STATE_DISABLE)
++		WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
++	else
++		WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
++
++	return 0;
++}
++
++static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
++				struct amdgpu_irq_src *source,
++				struct amdgpu_iv_entry *entry)
++{
++	int reg_block;
++	unsigned long flags;
++	unsigned crtc_id;
++	struct amdgpu_crtc *amdgpu_crtc;
++	struct amdgpu_flip_work *works;
++
++	crtc_id = (entry->src_id - 8) >> 1;
++	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++
++	/* ack the interrupt */
++	switch(crtc_id){
++		case AMDGPU_PAGEFLIP_IRQ_D1:
++			reg_block = CRTC0_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D2:
++			reg_block = CRTC1_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D3:
++			reg_block = CRTC2_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D4:
++			reg_block = CRTC3_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D5:
++			reg_block = CRTC4_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D6:
++			reg_block = CRTC5_REGISTER_OFFSET;
++			break;
++		default:
++			DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
++			return -EINVAL;
++	}
++
++	if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
++		WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
++
++	/* IRQ could occur when in initial stage */
++	if (amdgpu_crtc == NULL)
++		return 0;
++
++	spin_lock_irqsave(&adev->ddev->event_lock, flags);
++	works = amdgpu_crtc->pflip_works;
++	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
++		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
++						"AMDGPU_FLIP_SUBMITTED(%d)\n",
++						amdgpu_crtc->pflip_status,
++						AMDGPU_FLIP_SUBMITTED);
++		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++		return 0;
++	}
++
++	/* page flip completed. clean up */
++	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
++	amdgpu_crtc->pflip_works = NULL;
++
++	/* wakeup usersapce */
++	if (works->event)
++		drm_send_vblank_event(adev->ddev, crtc_id, works->event);
++
++	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++
++	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
++	amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
++	queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
++
++	return 0;
++}
++
++static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
++			    struct amdgpu_irq_src *source,
++			    struct amdgpu_iv_entry *entry)
++{
++	uint32_t disp_int, mask, int_control, tmp;
++	unsigned hpd;
++
++	if (entry->src_data > 6) {
++		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
++		return 0;
++	}
++
++	hpd = entry->src_data;
++	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
++	mask = interrupt_status_offsets[hpd].hpd;
++	int_control = hpd_int_control_offsets[hpd];
++
++	if (disp_int & mask) {
++		tmp = RREG32(int_control);
++		tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
++		WREG32(int_control, tmp);
++		schedule_work(&adev->hotplug_work);
++		DRM_DEBUG("IH: HPD%d\n", hpd + 1);
++	}
++
++	return 0;
++
++}
++
++static int dce_v8_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int dce_v8_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs dce_v8_0_ip_funcs = {
++	.early_init = dce_v8_0_early_init,
++	.late_init = NULL,
++	.sw_init = dce_v8_0_sw_init,
++	.sw_fini = dce_v8_0_sw_fini,
++	.hw_init = dce_v8_0_hw_init,
++	.hw_fini = dce_v8_0_hw_fini,
++	.suspend = dce_v8_0_suspend,
++	.resume = dce_v8_0_resume,
++	.is_idle = dce_v8_0_is_idle,
++	.wait_for_idle = dce_v8_0_wait_for_idle,
++	.soft_reset = dce_v8_0_soft_reset,
++	.print_status = dce_v8_0_print_status,
++	.set_clockgating_state = dce_v8_0_set_clockgating_state,
++	.set_powergating_state = dce_v8_0_set_powergating_state,
++};
++
++static void
++dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
++			  struct drm_display_mode *mode,
++			  struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
++
++	/* need to call this here rather than in prepare() since we need some crtc info */
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++
++	/* set scaler clears this on some chips */
++	dce_v8_0_set_interleave(encoder->crtc, mode);
++
++	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
++		dce_v8_0_afmt_enable(encoder, true);
++		dce_v8_0_afmt_setmode(encoder, adjusted_mode);
++	}
++}
++
++static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++
++	if ((amdgpu_encoder->active_device &
++	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
++	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
++	     ENCODER_OBJECT_ID_NONE)) {
++		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++		if (dig) {
++			dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
++			if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
++				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
++		}
++	}
++
++	amdgpu_atombios_scratch_regs_lock(adev, true);
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		/* select the clock/data port if it uses a router */
++		if (amdgpu_connector->router.cd_valid)
++			amdgpu_i2c_router_select_cd_port(amdgpu_connector);
++
++		/* turn eDP panel on for mode set */
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
++			amdgpu_atombios_encoder_set_edp_panel_power(connector,
++							     ATOM_TRANSMITTER_ACTION_POWER_ON);
++	}
++
++	/* this is needed for the pll/ss setup to work correctly in some cases */
++	amdgpu_atombios_encoder_set_crtc_source(encoder);
++	/* set up the FMT blocks */
++	dce_v8_0_program_fmt(encoder);
++}
++
++static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	/* need to call this here as we need the crtc set up */
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
++	amdgpu_atombios_scratch_regs_lock(adev, false);
++}
++
++static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig;
++
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++
++	if (amdgpu_atombios_encoder_is_digital(encoder)) {
++		if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
++			dce_v8_0_afmt_enable(encoder, false);
++		dig = amdgpu_encoder->enc_priv;
++		dig->dig_encoder = -1;
++	}
++	amdgpu_encoder->active_device = 0;
++}
++
++/* these are handled by the primary encoders */
++static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
++{
++
++}
++
++static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
++{
++
++}
++
++static void
++dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
++		      struct drm_display_mode *mode,
++		      struct drm_display_mode *adjusted_mode)
++{
++
++}
++
++static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
++{
++
++}
++
++static void
++dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
++{
++
++}
++
++static bool dce_v8_0_ext_mode_fixup(struct drm_encoder *encoder,
++				    const struct drm_display_mode *mode,
++				    struct drm_display_mode *adjusted_mode)
++{
++	return true;
++}
++
++static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
++	.dpms = dce_v8_0_ext_dpms,
++	.mode_fixup = dce_v8_0_ext_mode_fixup,
++	.prepare = dce_v8_0_ext_prepare,
++	.mode_set = dce_v8_0_ext_mode_set,
++	.commit = dce_v8_0_ext_commit,
++	.disable = dce_v8_0_ext_disable,
++	/* no detect for TMDS/LVDS yet */
++};
++
++static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
++	.dpms = amdgpu_atombios_encoder_dpms,
++	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
++	.prepare = dce_v8_0_encoder_prepare,
++	.mode_set = dce_v8_0_encoder_mode_set,
++	.commit = dce_v8_0_encoder_commit,
++	.disable = dce_v8_0_encoder_disable,
++	.detect = amdgpu_atombios_encoder_dig_detect,
++};
++
++static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
++	.dpms = amdgpu_atombios_encoder_dpms,
++	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
++	.prepare = dce_v8_0_encoder_prepare,
++	.mode_set = dce_v8_0_encoder_mode_set,
++	.commit = dce_v8_0_encoder_commit,
++	.detect = amdgpu_atombios_encoder_dac_detect,
++};
++
++static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++		amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
++	kfree(amdgpu_encoder->enc_priv);
++	drm_encoder_cleanup(encoder);
++	kfree(amdgpu_encoder);
++}
++
++static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
++	.destroy = dce_v8_0_encoder_destroy,
++};
++
++static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
++				 uint32_t encoder_enum,
++				 uint32_t supported_device,
++				 u16 caps)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++
++	/* see if we already added it */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++		if (amdgpu_encoder->encoder_enum == encoder_enum) {
++			amdgpu_encoder->devices |= supported_device;
++			return;
++		}
++
++	}
++
++	/* add a new one */
++	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
++	if (!amdgpu_encoder)
++		return;
++
++	encoder = &amdgpu_encoder->base;
++	switch (adev->mode_info.num_crtc) {
++	case 1:
++		encoder->possible_crtcs = 0x1;
++		break;
++	case 2:
++	default:
++		encoder->possible_crtcs = 0x3;
++		break;
++	case 4:
++		encoder->possible_crtcs = 0xf;
++		break;
++	case 6:
++		encoder->possible_crtcs = 0x3f;
++		break;
++	}
++
++	amdgpu_encoder->enc_priv = NULL;
++
++	amdgpu_encoder->encoder_enum = encoder_enum;
++	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
++	amdgpu_encoder->devices = supported_device;
++	amdgpu_encoder->rmx_type = RMX_OFF;
++	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
++	amdgpu_encoder->is_ext_encoder = false;
++	amdgpu_encoder->caps = caps;
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++		drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++				 DRM_MODE_ENCODER_DAC);
++		drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++			amdgpu_encoder->rmx_type = RMX_FULL;
++			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++					 DRM_MODE_ENCODER_LVDS);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
++		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
++			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++					 DRM_MODE_ENCODER_DAC);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
++		} else {
++			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++					 DRM_MODE_ENCODER_TMDS);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
++		}
++		drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
++		break;
++	case ENCODER_OBJECT_ID_SI170B:
++	case ENCODER_OBJECT_ID_CH7303:
++	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
++	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
++	case ENCODER_OBJECT_ID_TITFP513:
++	case ENCODER_OBJECT_ID_VT1623:
++	case ENCODER_OBJECT_ID_HDMI_SI1930:
++	case ENCODER_OBJECT_ID_TRAVIS:
++	case ENCODER_OBJECT_ID_NUTMEG:
++		/* these are handled by the primary encoders */
++		amdgpu_encoder->is_ext_encoder = true;
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++					 DRM_MODE_ENCODER_LVDS);
++		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
++			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++					 DRM_MODE_ENCODER_DAC);
++		else
++			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
++					 DRM_MODE_ENCODER_TMDS);
++		drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
++		break;
++	}
++}
++
++static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
++	.set_vga_render_state = &dce_v8_0_set_vga_render_state,
++	.bandwidth_update = &dce_v8_0_bandwidth_update,
++	.vblank_get_counter = &dce_v8_0_vblank_get_counter,
++	.vblank_wait = &dce_v8_0_vblank_wait,
++	.is_display_hung = &dce_v8_0_is_display_hung,
++	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
++	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
++	.hpd_sense = &dce_v8_0_hpd_sense,
++	.hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
++	.hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
++	.page_flip = &dce_v8_0_page_flip,
++	.page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
++	.add_encoder = &dce_v8_0_encoder_add,
++	.add_connector = &amdgpu_connector_add,
++	.stop_mc_access = &dce_v8_0_stop_mc_access,
++	.resume_mc_access = &dce_v8_0_resume_mc_access,
++};
++
++static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
++{
++	if (adev->mode_info.funcs == NULL)
++		adev->mode_info.funcs = &dce_v8_0_display_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
++	.set = dce_v8_0_set_crtc_interrupt_state,
++	.process = dce_v8_0_crtc_irq,
++};
++
++static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
++	.set = dce_v8_0_set_pageflip_interrupt_state,
++	.process = dce_v8_0_pageflip_irq,
++};
++
++static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
++	.set = dce_v8_0_set_hpd_interrupt_state,
++	.process = dce_v8_0_hpd_irq,
++};
++
++static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
++	adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
++
++	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
++	adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
++
++	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
++	adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
+new file mode 100644
+index 0000000..3a0a73b4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __DCE_V8_0_H__
++#define __DCE_V8_0_H__
++
++extern const struct amdgpu_ip_funcs dce_v8_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+new file mode 100644
+index 0000000..675b096
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -0,0 +1,5635 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++#include "amdgpu_gfx.h"
++#include "cikd.h"
++#include "cik.h"
++#include "atom.h"
++#include "amdgpu_ucode.h"
++#include "clearstate_ci.h"
++
++#include "uvd/uvd_4_2_d.h"
++
++#include "dce/dce_8_0_d.h"
++#include "dce/dce_8_0_sh_mask.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "gca/gfx_7_0_d.h"
++#include "gca/gfx_7_2_enum.h"
++#include "gca/gfx_7_2_sh_mask.h"
++
++#include "gmc/gmc_7_0_d.h"
++#include "gmc/gmc_7_0_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++#define GFX7_NUM_GFX_RINGS     1
++#define GFX7_NUM_COMPUTE_RINGS 8
++
++static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
++static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
++static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
++int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
++
++MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
++MODULE_FIRMWARE("radeon/bonaire_me.bin");
++MODULE_FIRMWARE("radeon/bonaire_ce.bin");
++MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
++MODULE_FIRMWARE("radeon/bonaire_mec.bin");
++
++MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
++MODULE_FIRMWARE("radeon/hawaii_me.bin");
++MODULE_FIRMWARE("radeon/hawaii_ce.bin");
++MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
++MODULE_FIRMWARE("radeon/hawaii_mec.bin");
++
++MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
++MODULE_FIRMWARE("radeon/kaveri_me.bin");
++MODULE_FIRMWARE("radeon/kaveri_ce.bin");
++MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
++MODULE_FIRMWARE("radeon/kaveri_mec.bin");
++MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
++
++MODULE_FIRMWARE("radeon/kabini_pfp.bin");
++MODULE_FIRMWARE("radeon/kabini_me.bin");
++MODULE_FIRMWARE("radeon/kabini_ce.bin");
++MODULE_FIRMWARE("radeon/kabini_rlc.bin");
++MODULE_FIRMWARE("radeon/kabini_mec.bin");
++
++MODULE_FIRMWARE("radeon/mullins_pfp.bin");
++MODULE_FIRMWARE("radeon/mullins_me.bin");
++MODULE_FIRMWARE("radeon/mullins_ce.bin");
++MODULE_FIRMWARE("radeon/mullins_rlc.bin");
++MODULE_FIRMWARE("radeon/mullins_mec.bin");
++
++static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
++{
++	{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
++	{mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
++	{mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
++	{mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
++	{mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
++	{mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
++	{mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
++	{mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
++	{mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
++	{mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
++	{mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
++	{mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
++	{mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
++	{mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
++	{mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
++	{mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
++};
++
++static const u32 spectre_rlc_save_restore_register_list[] =
++{
++	(0x0e00 << 16) | (0xc12c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc140 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc150 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc15c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc168 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc170 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc178 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc204 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2b8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2bc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2c0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8228 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x829c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x869c >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x98f4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x98f8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9900 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc260 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x90e8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c000 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c00c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c1c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9700 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x89bc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8900 >> 2),
++	0x00000000,
++	0x3,
++	(0x0e00 << 16) | (0xc130 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc134 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc1fc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc208 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc264 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc268 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc26c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc270 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc274 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc278 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc27c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc280 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc284 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc288 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc28c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc290 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc294 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc298 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc29c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2a0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2a4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2a8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2ac  >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2b0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x301d0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30238 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30250 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30254 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30258 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3025c >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc99c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9834 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f00 >> 2),
++	0x00000000,
++	(0x0001 << 16) | (0x30f00 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f04 >> 2),
++	0x00000000,
++	(0x0001 << 16) | (0x30f04 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f08 >> 2),
++	0x00000000,
++	(0x0001 << 16) | (0x30f08 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f0c >> 2),
++	0x00000000,
++	(0x0001 << 16) | (0x30f0c >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x9b7c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8a14 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8a18 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a00 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8bf0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8bcc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8b24 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30a04 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a10 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a14 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a18 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a2c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc700 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc704 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc708 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc768 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc770 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc774 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc778 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc77c >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc780 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc784 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc788 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc78c >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc798 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc79c >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc7a0 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc7a4 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc7a8 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc7ac >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc7b0 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc7b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9100 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c010 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92a8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92ac >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92b8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92bc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92c0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92c4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92c8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92cc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x92d0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c00 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c04 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c20 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c38 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c3c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xae00 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9604 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac08 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac0c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac10 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac14 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac58 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac68 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac6c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac70 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac74 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac78 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac7c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac80 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac84 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac88 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac8c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x970c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9714 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9718 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x971c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x8e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x9e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0xae00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0xbe00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xcd10 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xcd14 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88b0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88b8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88bc >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0x89c0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88c4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88c8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88d0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88d4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88d8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8980 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30938 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3093c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30940 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x89a0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30900 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30904 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x89b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c210 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c214 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c218 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8904 >> 2),
++	0x00000000,
++	0x5,
++	(0x0e00 << 16) | (0x8c28 >> 2),
++	(0x0e00 << 16) | (0x8c2c >> 2),
++	(0x0e00 << 16) | (0x8c30 >> 2),
++	(0x0e00 << 16) | (0x8c34 >> 2),
++	(0x0e00 << 16) | (0x9600 >> 2),
++};
++
++static const u32 kalindi_rlc_save_restore_register_list[] =
++{
++	(0x0e00 << 16) | (0xc12c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc140 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc150 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc15c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc168 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc170 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc204 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2b8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2bc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2c0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8228 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x829c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x869c >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x98f4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x98f8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9900 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc260 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x90e8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c000 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c00c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c1c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9700 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xcd20 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x89bc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8900 >> 2),
++	0x00000000,
++	0x3,
++	(0x0e00 << 16) | (0xc130 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc134 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc1fc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc208 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc264 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc268 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc26c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc270 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc274 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc28c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc290 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc294 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc298 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2a0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2a4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2a8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc2ac >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x301d0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30238 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30250 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30254 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30258 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3025c >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc900 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc904 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc908 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc90c >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0xc910 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc99c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9834 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f00 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f04 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f08 >> 2),
++	0x00000000,
++	(0x0000 << 16) | (0x30f0c >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x9b7c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8a14 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8a18 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a00 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8bf0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8bcc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8b24 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30a04 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a10 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a14 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a18 >> 2),
++	0x00000000,
++	(0x0600 << 16) | (0x30a2c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc700 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc704 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc708 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xc768 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc770 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc774 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc798 >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0xc79c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9100 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c010 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c00 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c04 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c20 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c38 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8c3c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xae00 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9604 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac08 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac0c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac10 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac14 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac58 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac68 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac6c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac70 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac74 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac78 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac7c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac80 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac84 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac88 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xac8c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x970c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9714 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x9718 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x971c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x4e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x5e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x6e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x7e00 << 16) | (0x31068 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xcd10 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0xcd14 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88b0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88b8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88bc >> 2),
++	0x00000000,
++	(0x0400 << 16) | (0x89c0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88c4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88c8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88d0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88d4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x88d8 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8980 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30938 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3093c >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30940 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x89a0 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30900 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x30904 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x89b4 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3e1fc >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c210 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c214 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x3c218 >> 2),
++	0x00000000,
++	(0x0e00 << 16) | (0x8904 >> 2),
++	0x00000000,
++	0x5,
++	(0x0e00 << 16) | (0x8c28 >> 2),
++	(0x0e00 << 16) | (0x8c2c >> 2),
++	(0x0e00 << 16) | (0x8c30 >> 2),
++	(0x0e00 << 16) | (0x8c34 >> 2),
++	(0x0e00 << 16) | (0x9600 >> 2),
++};
++
++static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
++static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
++static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
++static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
++
++/*
++ * Core functions
++ */
++/**
++ * gfx_v7_0_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		chip_name = "bonaire";
++		break;
++	case CHIP_HAWAII:
++		chip_name = "hawaii";
++		break;
++	case CHIP_KAVERI:
++		chip_name = "kaveri";
++		break;
++	case CHIP_KABINI:
++		chip_name = "kabini";
++		break;
++	case CHIP_MULLINS:
++		chip_name = "mullins";
++		break;
++	default: BUG();
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
++	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
++	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.me_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
++	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
++	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
++	if (err)
++		goto out;
++
++	if (adev->asic_type == CHIP_KAVERI) {
++		snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
++		err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
++		if (err)
++			goto out;
++		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
++		if (err)
++			goto out;
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
++	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
++
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "gfx7: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		release_firmware(adev->gfx.pfp_fw);
++		adev->gfx.pfp_fw = NULL;
++		release_firmware(adev->gfx.me_fw);
++		adev->gfx.me_fw = NULL;
++		release_firmware(adev->gfx.ce_fw);
++		adev->gfx.ce_fw = NULL;
++		release_firmware(adev->gfx.mec_fw);
++		adev->gfx.mec_fw = NULL;
++		release_firmware(adev->gfx.mec2_fw);
++		adev->gfx.mec2_fw = NULL;
++		release_firmware(adev->gfx.rlc_fw);
++		adev->gfx.rlc_fw = NULL;
++	}
++	return err;
++}
++
++/**
++ * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Starting with SI, the tiling setup is done globally in a
++ * set of 32 tiling modes.  Rather than selecting each set of
++ * parameters per surface as on older asics, we just select
++ * which index in the tiling table we want to use, and the
++ * surface uses those parameters (CIK).
++ */
++static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
++{
++	const u32 num_tile_mode_states = 32;
++	const u32 num_secondary_tile_mode_states = 16;
++	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
++
++	switch (adev->gfx.config.mem_row_size_in_kb) {
++	case 1:
++		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
++		break;
++	case 2:
++	default:
++		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
++		break;
++	case 4:
++		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
++		break;
++	}
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 1:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 2:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 3:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 4:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 5:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 6:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 7:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++
++			case 8:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16));
++				break;
++			case 9:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
++				break;
++			case 10:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 11:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 12:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 13:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
++				break;
++			case 14:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 15:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 16:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 17:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 18:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 19:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
++				break;
++			case 20:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 21:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 22:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 23:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 24:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 25:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 26:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 27:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
++				break;
++			case 28:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 29:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 30:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			}
++			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 1:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 2:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 3:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 4:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 5:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 6:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			case 8:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 9:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 10:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 11:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 12:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 13:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 14:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			}
++			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		break;
++	case CHIP_HAWAII:
++		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 1:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 2:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 3:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 4:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 5:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 6:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 7:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++
++			case 8:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
++				break;
++			case 9:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
++				break;
++			case 10:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 11:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 12:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 13:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
++				break;
++			case 14:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 15:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 16:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 17:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 18:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 19:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
++				break;
++			case 20:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 21:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 22:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 23:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 24:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 25:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 26:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 27:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
++				break;
++			case 28:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 29:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 30:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			}
++			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 1:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 2:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 3:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 4:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 5:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			case 6:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			case 8:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 9:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 10:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 11:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 12:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 13:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 14:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			}
++			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		break;
++	case CHIP_KABINI:
++	case CHIP_KAVERI:
++	case CHIP_MULLINS:
++	default:
++		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 1:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 2:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 3:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 4:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 5:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 6:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++						TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 7:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++
++			case 8:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++						PIPE_CONFIG(ADDR_SURF_P2));
++				break;
++			case 9:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
++				break;
++			case 10:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 11:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 12:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 13:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
++				break;
++			case 14:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 15:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 16:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 17:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 18:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 19:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
++				break;
++			case 20:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 21:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 22:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 23:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			case 24:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 25:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 26:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 27:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
++				break;
++			case 28:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 29:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 30:
++				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			}
++			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 1:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 2:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 3:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 4:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 5:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 6:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 8:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 9:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 10:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 11:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 12:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 13:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 14:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			}
++			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		break;
++	}
++}
++
++/**
++ * gfx_v7_0_select_se_sh - select which SE, SH to address
++ *
++ * @adev: amdgpu_device pointer
++ * @se_num: shader engine to address
++ * @sh_num: sh block to address
++ *
++ * Select which SE, SH combinations to address. Certain
++ * registers are instanced per SE or SH.  0xffffffff means
++ * broadcast to all SEs or SHs (CIK).
++ */
++void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
++{
++	u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
++
++	if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
++		data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
++			GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
++	else if (se_num == 0xffffffff)
++		data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
++			(sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
++	else if (sh_num == 0xffffffff)
++		data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
++			(se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
++	else
++		data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
++			(se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
++	WREG32(mmGRBM_GFX_INDEX, data);
++}
++
++/**
++ * gfx_v7_0_create_bitmask - create a bitmask
++ *
++ * @bit_width: length of the mask
++ *
++ * create a variable length bit mask (CIK).
++ * Returns the bitmask.
++ */
++static u32 gfx_v7_0_create_bitmask(u32 bit_width)
++{
++	u32 i, mask = 0;
++
++	for (i = 0; i < bit_width; i++) {
++		mask <<= 1;
++		mask |= 1;
++	}
++	return mask;
++}
++
++/**
++ * gfx_v7_0_get_rb_disabled - computes the mask of disabled RBs
++ *
++ * @adev: amdgpu_device pointer
++ * @max_rb_num: max RBs (render backends) for the asic
++ * @se_num: number of SEs (shader engines) for the asic
++ * @sh_per_se: number of SH blocks per SE for the asic
++ *
++ * Calculates the bitmask of disabled RBs (CIK).
++ * Returns the disabled RB bitmask.
++ */
++static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev,
++				    u32 max_rb_num_per_se,
++				    u32 sh_per_se)
++{
++	u32 data, mask;
++
++	data = RREG32(mmCC_RB_BACKEND_DISABLE);
++	if (data & 1)
++		data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
++	else
++		data = 0;
++
++	data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
++
++	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
++
++	mask = gfx_v7_0_create_bitmask(max_rb_num_per_se / sh_per_se);
++
++	return data & mask;
++}
++
++/**
++ * gfx_v7_0_setup_rb - setup the RBs on the asic
++ *
++ * @adev: amdgpu_device pointer
++ * @se_num: number of SEs (shader engines) for the asic
++ * @sh_per_se: number of SH blocks per SE for the asic
++ * @max_rb_num: max RBs (render backends) for the asic
++ *
++ * Configures per-SE/SH RB registers (CIK).
++ */
++static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
++			      u32 se_num, u32 sh_per_se,
++			      u32 max_rb_num_per_se)
++{
++	int i, j;
++	u32 data, mask;
++	u32 disabled_rbs = 0;
++	u32 enabled_rbs = 0;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < se_num; i++) {
++		for (j = 0; j < sh_per_se; j++) {
++			gfx_v7_0_select_se_sh(adev, i, j);
++			data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
++			if (adev->asic_type == CHIP_HAWAII)
++				disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
++			else
++				disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
++		}
++	}
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	mask = 1;
++	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
++		if (!(disabled_rbs & mask))
++			enabled_rbs |= mask;
++		mask <<= 1;
++	}
++
++	adev->gfx.config.backend_enable_mask = enabled_rbs;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < se_num; i++) {
++		gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
++		data = 0;
++		for (j = 0; j < sh_per_se; j++) {
++			switch (enabled_rbs & 3) {
++			case 0:
++				if (j == 0)
++					data |= (RASTER_CONFIG_RB_MAP_3 <<
++						PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
++				else
++					data |= (RASTER_CONFIG_RB_MAP_0 <<
++						PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
++				break;
++			case 1:
++				data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
++				break;
++			case 2:
++				data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
++				break;
++			case 3:
++			default:
++				data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
++				break;
++			}
++			enabled_rbs >>= 2;
++		}
++		WREG32(mmPA_SC_RASTER_CONFIG, data);
++	}
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++}
++
++/**
++ * gfx_v7_0_gpu_init - setup the 3D engine
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Configures the 3D engine and tiling configuration
++ * registers so that the 3D engine is usable.
++ */
++static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
++{
++	u32 gb_addr_config;
++	u32 mc_shared_chmap, mc_arb_ramcfg;
++	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
++	u32 tmp;
++	int i;
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		adev->gfx.config.max_shader_engines = 2;
++		adev->gfx.config.max_tile_pipes = 4;
++		adev->gfx.config.max_cu_per_sh = 7;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 2;
++		adev->gfx.config.max_texture_channel_caches = 4;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 32;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	case CHIP_HAWAII:
++		adev->gfx.config.max_shader_engines = 4;
++		adev->gfx.config.max_tile_pipes = 16;
++		adev->gfx.config.max_cu_per_sh = 11;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 4;
++		adev->gfx.config.max_texture_channel_caches = 16;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 32;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	case CHIP_KAVERI:
++		adev->gfx.config.max_shader_engines = 1;
++		adev->gfx.config.max_tile_pipes = 4;
++		if ((adev->pdev->device == 0x1304) ||
++		    (adev->pdev->device == 0x1305) ||
++		    (adev->pdev->device == 0x130C) ||
++		    (adev->pdev->device == 0x130F) ||
++		    (adev->pdev->device == 0x1310) ||
++		    (adev->pdev->device == 0x1311) ||
++		    (adev->pdev->device == 0x131C)) {
++			adev->gfx.config.max_cu_per_sh = 8;
++			adev->gfx.config.max_backends_per_se = 2;
++		} else if ((adev->pdev->device == 0x1309) ||
++			   (adev->pdev->device == 0x130A) ||
++			   (adev->pdev->device == 0x130D) ||
++			   (adev->pdev->device == 0x1313) ||
++			   (adev->pdev->device == 0x131D)) {
++			adev->gfx.config.max_cu_per_sh = 6;
++			adev->gfx.config.max_backends_per_se = 2;
++		} else if ((adev->pdev->device == 0x1306) ||
++			   (adev->pdev->device == 0x1307) ||
++			   (adev->pdev->device == 0x130B) ||
++			   (adev->pdev->device == 0x130E) ||
++			   (adev->pdev->device == 0x1315) ||
++			   (adev->pdev->device == 0x131B)) {
++			adev->gfx.config.max_cu_per_sh = 4;
++			adev->gfx.config.max_backends_per_se = 1;
++		} else {
++			adev->gfx.config.max_cu_per_sh = 3;
++			adev->gfx.config.max_backends_per_se = 1;
++		}
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_texture_channel_caches = 4;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 16;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	case CHIP_KABINI:
++	case CHIP_MULLINS:
++	default:
++		adev->gfx.config.max_shader_engines = 1;
++		adev->gfx.config.max_tile_pipes = 2;
++		adev->gfx.config.max_cu_per_sh = 2;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 1;
++		adev->gfx.config.max_texture_channel_caches = 2;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 16;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	}
++
++	WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
++
++	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
++	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
++	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
++
++	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
++	adev->gfx.config.mem_max_burst_length_bytes = 256;
++	if (adev->flags & AMDGPU_IS_APU) {
++		/* Get memory bank mapping mode. */
++		tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
++		dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
++		dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
++
++		tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
++		dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
++		dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
++
++		/* Validate settings in case only one DIMM installed. */
++		if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
++			dimm00_addr_map = 0;
++		if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
++			dimm01_addr_map = 0;
++		if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
++			dimm10_addr_map = 0;
++		if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
++			dimm11_addr_map = 0;
++
++		/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
++		/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
++		if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
++			adev->gfx.config.mem_row_size_in_kb = 2;
++		else
++			adev->gfx.config.mem_row_size_in_kb = 1;
++	} else {
++		tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
++		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
++		if (adev->gfx.config.mem_row_size_in_kb > 4)
++			adev->gfx.config.mem_row_size_in_kb = 4;
++	}
++	/* XXX use MC settings? */
++	adev->gfx.config.shader_engine_tile_size = 32;
++	adev->gfx.config.num_gpus = 1;
++	adev->gfx.config.multi_gpu_tile_size = 64;
++
++	/* fix up row size */
++	gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
++	switch (adev->gfx.config.mem_row_size_in_kb) {
++	case 1:
++	default:
++		gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
++		break;
++	case 2:
++		gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
++		break;
++	case 4:
++		gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
++		break;
++	}
++	adev->gfx.config.gb_addr_config = gb_addr_config;
++
++	WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
++	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
++	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
++	WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
++
++	gfx_v7_0_tiling_mode_table_init(adev);
++
++	gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
++			  adev->gfx.config.max_sh_per_se,
++			  adev->gfx.config.max_backends_per_se);
++
++	/* set HW defaults for 3D engine */
++	WREG32(mmCP_MEQ_THRESHOLDS,
++			(0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
++			(0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	/*
++	 * making sure that the following register writes will be broadcasted
++	 * to all the shaders
++	 */
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++
++	/* XXX SH_MEM regs */
++	/* where to put LDS, scratch, GPUVM in FSA64 space */
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < 16; i++) {
++		cik_srbm_select(adev, 0, 0, 0, i);
++		/* CP and shaders */
++		WREG32(mmSH_MEM_CONFIG, 0);
++		WREG32(mmSH_MEM_APE1_BASE, 1);
++		WREG32(mmSH_MEM_APE1_LIMIT, 0);
++		WREG32(mmSH_MEM_BASES, 0);
++	}
++	cik_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++
++	WREG32(mmSX_DEBUG_1, 0x20);
++
++	WREG32(mmTA_CNTL_AUX, 0x00010000);
++
++	tmp = RREG32(mmSPI_CONFIG_CNTL);
++	tmp |= 0x03000000;
++	WREG32(mmSPI_CONFIG_CNTL, tmp);
++
++	WREG32(mmSQ_CONFIG, 1);
++
++	WREG32(mmDB_DEBUG, 0);
++
++	tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
++	tmp |= 0x00000400;
++	WREG32(mmDB_DEBUG2, tmp);
++
++	tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
++	tmp |= 0x00020200;
++	WREG32(mmDB_DEBUG3, tmp);
++
++	tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
++	tmp |= 0x00018208;
++	WREG32(mmCB_HW_CONTROL, tmp);
++
++	WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
++
++	WREG32(mmPA_SC_FIFO_SIZE,
++		((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
++		(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
++		(adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
++		(adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
++
++	WREG32(mmVGT_NUM_INSTANCES, 1);
++
++	WREG32(mmCP_PERFMON_CNTL, 0);
++
++	WREG32(mmSQ_CONFIG, 0);
++
++	WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
++		((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
++		(255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
++
++	WREG32(mmVGT_CACHE_INVALIDATION,
++		(VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
++		(ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
++
++	WREG32(mmVGT_GS_VERTEX_REUSE, 16);
++	WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
++
++	WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
++			(3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
++	WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	udelay(50);
++}
++
++/*
++ * GPU scratch registers helpers function.
++ */
++/**
++ * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the number and offset of the CP scratch registers.
++ * NOTE: use of CP scratch registers is a legacy inferface and
++ * is not used by default on newer asics (r6xx+).  On newer asics,
++ * memory buffers are used for fences rather than scratch regs.
++ */
++static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	adev->gfx.scratch.num_reg = 7;
++	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
++	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
++		adev->gfx.scratch.free[i] = true;
++		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
++	}
++}
++
++/**
++ * gfx_v7_0_ring_test_ring - basic gfx ring test
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Allocate a scratch register and write to it using the gfx ring (CIK).
++ * Provides a basic gfx ring test to verify that the ring is working.
++ * Used by gfx_v7_0_cp_gfx_resume();
++ * Returns 0 on success, error on failure.
++ */
++static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t scratch;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	r = amdgpu_gfx_scratch_get(adev, &scratch);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
++		return r;
++	}
++	WREG32(scratch, 0xCAFEDEAD);
++	r = amdgpu_ring_lock(ring, 3);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
++		amdgpu_gfx_scratch_free(adev, scratch);
++		return r;
++	}
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
++	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(scratch);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
++			  ring->idx, scratch, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_gfx_scratch_free(adev, scratch);
++	return r;
++}
++
++/**
++ * gfx_v7_0_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
++ *
++ * @adev: amdgpu_device pointer
++ * @ridx: amdgpu ring index
++ *
++ * Emits an hdp flush on the cp.
++ */
++static void gfx_v7_0_hdp_flush_cp_ring_emit(struct amdgpu_ring *ring)
++{
++	u32 ref_and_mask;
++
++	if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
++		switch (ring->me) {
++		case 1:
++			ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
++			break;
++		case 2:
++			ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
++			break;
++		default:
++			return;
++		}
++	} else {
++		ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
++	}
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
++	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
++				 WAIT_REG_MEM_FUNCTION(3) |  /* == */
++				 WAIT_REG_MEM_ENGINE(1)));   /* pfp */
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
++	amdgpu_ring_write(ring, ref_and_mask);
++	amdgpu_ring_write(ring, ref_and_mask);
++	amdgpu_ring_write(ring, 0x20); /* poll interval */
++}
++
++/**
++ * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
++ *
++ * @adev: amdgpu_device pointer
++ * @fence: amdgpu fence object
++ *
++ * Emits a fence sequnce number on the gfx ring and flushes
++ * GPU caches.
++ */
++static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
++					 u64 seq, bool write64bit)
++{
++	/* Workaround for cache flush problems. First send a dummy EOP
++	 * event down the pipe with seq one below.
++	 */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
++	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++				 EOP_TC_ACTION_EN |
++				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++				 EVENT_INDEX(5)));
++	amdgpu_ring_write(ring, addr & 0xfffffffc);
++	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
++				DATA_SEL(1) | INT_SEL(0));
++	amdgpu_ring_write(ring, lower_32_bits(seq - 1));
++	amdgpu_ring_write(ring, upper_32_bits(seq - 1));
++
++	/* Then send the real EOP event down the pipe. */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
++	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++				 EOP_TC_ACTION_EN |
++				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++				 EVENT_INDEX(5)));
++	amdgpu_ring_write(ring, addr & 0xfffffffc);
++	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
++				DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++	amdgpu_ring_write(ring, upper_32_bits(seq));
++}
++
++/**
++ * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
++ *
++ * @adev: amdgpu_device pointer
++ * @fence: amdgpu fence object
++ *
++ * Emits a fence sequnce number on the compute ring and flushes
++ * GPU caches.
++ */
++static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
++					     u64 addr, u64 seq,
++					     bool write64bits)
++{
++	/* RELEASE_MEM - flush caches, send int */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
++	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++				 EOP_TC_ACTION_EN |
++				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++				 EVENT_INDEX(5)));
++	amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2));
++	amdgpu_ring_write(ring, addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++	amdgpu_ring_write(ring, upper_32_bits(seq));
++}
++
++/**
++ * gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring
++ *
++ * @ring: amdgpu ring buffer object
++ * @semaphore: amdgpu semaphore object
++ * @emit_wait: Is this a sempahore wait?
++ *
++ * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
++ * from running ahead of semaphore waits.
++ */
++static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
++					 struct amdgpu_semaphore *semaphore,
++					 bool emit_wait)
++{
++	uint64_t addr = semaphore->gpu_addr;
++	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
++	amdgpu_ring_write(ring, addr & 0xffffffff);
++	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
++
++	if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
++		/* Prevent the PFP from running ahead of the semaphore wait */
++		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
++		amdgpu_ring_write(ring, 0x0);
++	}
++
++	return true;
++}
++
++/*
++ * IB stuff
++ */
++/**
++ * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @ib: amdgpu indirect buffer object
++ *
++ * Emits an DE (drawing engine) or CE (constant engine) IB
++ * on the gfx ring.  IBs are usually generated by userspace
++ * acceleration drivers and submitted to the kernel for
++ * sheduling on the ring.  This function schedules the IB
++ * on the gfx ring for execution by the GPU.
++ */
++static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
++				  struct amdgpu_ib *ib)
++{
++	u32 header, control = 0;
++	u32 next_rptr = ring->wptr + 5;
++	if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
++		control |= INDIRECT_BUFFER_VALID;
++
++	if (ib->flush_hdp_writefifo)
++		next_rptr += 7;
++
++	if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
++		next_rptr += 2;
++
++	next_rptr += 4;
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
++	amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, next_rptr);
++
++	if (ib->flush_hdp_writefifo)
++		gfx_v7_0_hdp_flush_cp_ring_emit(ring);
++
++	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
++	if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
++		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
++		amdgpu_ring_write(ring, 0);
++		ring->need_ctx_switch = false;
++	}
++
++	if (ib->is_const_ib)
++		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
++	else
++		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
++
++	control |= ib->length_dw |
++		(ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
++
++	amdgpu_ring_write(ring, header);
++	amdgpu_ring_write(ring,
++#ifdef __BIG_ENDIAN
++			  (2 << 0) |
++#endif
++			  (ib->gpu_addr & 0xFFFFFFFC));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
++	amdgpu_ring_write(ring, control);
++}
++
++/**
++ * gfx_v7_0_ring_test_ib - basic ring IB test
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Allocate an IB and execute it on the gfx ring (CIK).
++ * Provides a basic gfx ring test to verify that IBs are working.
++ * Returns 0 on success, error on failure.
++ */
++static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_ib ib;
++	uint32_t scratch;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	r = amdgpu_gfx_scratch_get(adev, &scratch);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
++		return r;
++	}
++	WREG32(scratch, 0xCAFEDEAD);
++	r = amdgpu_ib_get(ring, NULL, 256, &ib);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		amdgpu_gfx_scratch_free(adev, scratch);
++		return r;
++	}
++	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
++	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
++	ib.ptr[2] = 0xDEADBEEF;
++	ib.length_dw = 3;
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		amdgpu_gfx_scratch_free(adev, scratch);
++		amdgpu_ib_free(adev, &ib);
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++		return r;
++	}
++	r = amdgpu_fence_wait(ib.fence, false);
++	if (r) {
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		amdgpu_gfx_scratch_free(adev, scratch);
++		amdgpu_ib_free(adev, &ib);
++		return r;
++	}
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(scratch);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
++			 ib.fence->ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
++			  scratch, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_gfx_scratch_free(adev, scratch);
++	amdgpu_ib_free(adev, &ib);
++	return r;
++}
++
++/*
++ * CP.
++ * On CIK, gfx and compute now have independant command processors.
++ *
++ * GFX
++ * Gfx consists of a single ring and can process both gfx jobs and
++ * compute jobs.  The gfx CP consists of three microengines (ME):
++ * PFP - Pre-Fetch Parser
++ * ME - Micro Engine
++ * CE - Constant Engine
++ * The PFP and ME make up what is considered the Drawing Engine (DE).
++ * The CE is an asynchronous engine used for updating buffer desciptors
++ * used by the DE so that they can be loaded into cache in parallel
++ * while the DE is processing state update packets.
++ *
++ * Compute
++ * The compute CP consists of two microengines (ME):
++ * MEC1 - Compute MicroEngine 1
++ * MEC2 - Compute MicroEngine 2
++ * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
++ * The queues are exposed to userspace and are programmed directly
++ * by the compute runtime.
++ */
++/**
++ * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
++ *
++ * @adev: amdgpu_device pointer
++ * @enable: enable or disable the MEs
++ *
++ * Halts or unhalts the gfx MEs.
++ */
++static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
++{
++	int i;
++
++	if (enable) {
++		WREG32(mmCP_ME_CNTL, 0);
++	} else {
++		WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
++		for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++			adev->gfx.gfx_ring[i].ready = false;
++	}
++	udelay(50);
++}
++
++/**
++ * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Loads the gfx PFP, ME, and CE ucode.
++ * Returns 0 for success, -EINVAL if the ucode is not available.
++ */
++static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
++{
++	const struct gfx_firmware_header_v1_0 *pfp_hdr;
++	const struct gfx_firmware_header_v1_0 *ce_hdr;
++	const struct gfx_firmware_header_v1_0 *me_hdr;
++	const __le32 *fw_data;
++	unsigned i, fw_size;
++
++	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
++		return -EINVAL;
++
++	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
++	ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
++	me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
++
++	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
++	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
++	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
++	adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
++	adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
++	adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
++
++	gfx_v7_0_cp_gfx_enable(adev, false);
++
++	/* PFP */
++	fw_data = (const __le32 *)
++		(adev->gfx.pfp_fw->data +
++		 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_PFP_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
++
++	/* CE */
++	fw_data = (const __le32 *)
++		(adev->gfx.ce_fw->data +
++		 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_CE_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
++
++	/* ME */
++	fw_data = (const __le32 *)
++		(adev->gfx.me_fw->data +
++		 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_ME_RAM_WADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
++
++	return 0;
++}
++
++/**
++ * gfx_v7_0_cp_gfx_start - start the gfx ring
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Enables the ring and loads the clear state context and other
++ * packets required to init the ring.
++ * Returns 0 for success, error for failure.
++ */
++static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
++	const struct cs_section_def *sect = NULL;
++	const struct cs_extent_def *ext = NULL;
++	int r, i;
++
++	/* init the CP */
++	WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
++	WREG32(mmCP_ENDIAN_SWAP, 0);
++	WREG32(mmCP_DEVICE_ID, 1);
++
++	gfx_v7_0_cp_gfx_enable(adev, true);
++
++	r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
++		return r;
++	}
++
++	/* init the CE partitions.  CE only used for gfx on CIK */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
++	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
++	amdgpu_ring_write(ring, 0x8000);
++	amdgpu_ring_write(ring, 0x8000);
++
++	/* clear state buffer */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
++	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
++	amdgpu_ring_write(ring, 0x80000000);
++	amdgpu_ring_write(ring, 0x80000000);
++
++	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
++		for (ext = sect->section; ext->extent != NULL; ++ext) {
++			if (sect->id == SECT_CONTEXT) {
++				amdgpu_ring_write(ring,
++						  PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
++				amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
++				for (i = 0; i < ext->reg_count; i++)
++					amdgpu_ring_write(ring, ext->extent[i]);
++			}
++		}
++	}
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
++	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		amdgpu_ring_write(ring, 0x16000012);
++		amdgpu_ring_write(ring, 0x00000000);
++		break;
++	case CHIP_KAVERI:
++		amdgpu_ring_write(ring, 0x00000000); /* XXX */
++		amdgpu_ring_write(ring, 0x00000000);
++		break;
++	case CHIP_KABINI:
++	case CHIP_MULLINS:
++		amdgpu_ring_write(ring, 0x00000000); /* XXX */
++		amdgpu_ring_write(ring, 0x00000000);
++		break;
++	case CHIP_HAWAII:
++		amdgpu_ring_write(ring, 0x3a00161a);
++		amdgpu_ring_write(ring, 0x0000002e);
++		break;
++	default:
++		amdgpu_ring_write(ring, 0x00000000);
++		amdgpu_ring_write(ring, 0x00000000);
++		break;
++	}
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
++	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
++	amdgpu_ring_write(ring, 0x00000316);
++	amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
++	amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
++
++	amdgpu_ring_unlock_commit(ring);
++
++	return 0;
++}
++
++/**
++ * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Program the location and size of the gfx ring buffer
++ * and test it to make sure it's working.
++ * Returns 0 for success, error for failure.
++ */
++static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	u32 tmp;
++	u32 rb_bufsz;
++	u64 rb_addr, rptr_addr;
++	int r;
++
++	WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
++	if (adev->asic_type != CHIP_HAWAII)
++		WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
++
++	/* Set the write pointer delay */
++	WREG32(mmCP_RB_WPTR_DELAY, 0);
++
++	/* set the RB to use vmid 0 */
++	WREG32(mmCP_RB_VMID, 0);
++
++	WREG32(mmSCRATCH_ADDR, 0);
++
++	/* ring 0 - compute and gfx */
++	/* Set ring buffer size */
++	ring = &adev->gfx.gfx_ring[0];
++	rb_bufsz = order_base_2(ring->ring_size / 8);
++	tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
++#ifdef __BIG_ENDIAN
++	tmp |= BUF_SWAP_32BIT;
++#endif
++	WREG32(mmCP_RB0_CNTL, tmp);
++
++	/* Initialize the ring buffer's read and write pointers */
++	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
++	ring->wptr = 0;
++	WREG32(mmCP_RB0_WPTR, ring->wptr);
++
++	/* set the wb address wether it's enabled or not */
++	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
++	WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
++	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
++
++	/* scratch register shadowing is no longer supported */
++	WREG32(mmSCRATCH_UMSK, 0);
++
++	mdelay(1);
++	WREG32(mmCP_RB0_CNTL, tmp);
++
++	rb_addr = ring->gpu_addr >> 8;
++	WREG32(mmCP_RB0_BASE, rb_addr);
++	WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
++
++	/* start the ring */
++	gfx_v7_0_cp_gfx_start(adev);
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		return r;
++	}
++
++	return 0;
++}
++
++static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
++{
++	u32 rptr;
++
++	rptr = ring->adev->wb.wb[ring->rptr_offs];
++
++	return rptr;
++}
++
++static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u32 wptr;
++
++	wptr = RREG32(mmCP_RB0_WPTR);
++
++	return wptr;
++}
++
++static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32(mmCP_RB0_WPTR, ring->wptr);
++	(void)RREG32(mmCP_RB0_WPTR);
++}
++
++static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
++{
++	u32 rptr;
++
++	rptr = ring->adev->wb.wb[ring->rptr_offs];
++
++	return rptr;
++}
++
++static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
++{
++	u32 wptr;
++
++	/* XXX check if swapping is necessary on BE */
++	wptr = ring->adev->wb.wb[ring->wptr_offs];
++
++	return wptr;
++}
++
++static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	/* XXX check if swapping is necessary on BE */
++	adev->wb.wb[ring->wptr_offs] = ring->wptr;
++	WDOORBELL32(ring->doorbell_index, ring->wptr);
++}
++
++/**
++ * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
++ *
++ * @adev: amdgpu_device pointer
++ * @enable: enable or disable the MEs
++ *
++ * Halts or unhalts the compute MEs.
++ */
++static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
++{
++	int i;
++
++	if (enable) {
++		WREG32(mmCP_MEC_CNTL, 0);
++	} else {
++		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
++		for (i = 0; i < adev->gfx.num_compute_rings; i++)
++			adev->gfx.compute_ring[i].ready = false;
++	}
++	udelay(50);
++}
++
++/**
++ * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Loads the compute MEC1&2 ucode.
++ * Returns 0 for success, -EINVAL if the ucode is not available.
++ */
++static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
++{
++	const struct gfx_firmware_header_v1_0 *mec_hdr;
++	const __le32 *fw_data;
++	unsigned i, fw_size;
++
++	if (!adev->gfx.mec_fw)
++		return -EINVAL;
++
++	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
++	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
++	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
++
++	gfx_v7_0_cp_compute_enable(adev, false);
++
++	/* MEC1 */
++	fw_data = (const __le32 *)
++		(adev->gfx.mec_fw->data +
++		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
++
++	if (adev->asic_type == CHIP_KAVERI) {
++		const struct gfx_firmware_header_v1_0 *mec2_hdr;
++
++		if (!adev->gfx.mec2_fw)
++			return -EINVAL;
++
++		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
++		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
++		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
++
++		/* MEC2 */
++		fw_data = (const __le32 *)
++			(adev->gfx.mec2_fw->data +
++			 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
++		fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
++		WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
++		for (i = 0; i < fw_size; i++)
++			WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
++		WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
++	}
++
++	return 0;
++}
++
++/**
++ * gfx_v7_0_cp_compute_start - start the compute queues
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Enable the compute queues.
++ * Returns 0 for success, error for failure.
++ */
++static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev)
++{
++	gfx_v7_0_cp_compute_enable(adev, true);
++
++	return 0;
++}
++
++/**
++ * gfx_v7_0_cp_compute_fini - stop the compute queues
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the compute queues and tear down the driver queue
++ * info.
++ */
++static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
++
++		if (ring->mqd_obj) {
++			r = amdgpu_bo_reserve(ring->mqd_obj, false);
++			if (unlikely(r != 0))
++				dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
++
++			amdgpu_bo_unpin(ring->mqd_obj);
++			amdgpu_bo_unreserve(ring->mqd_obj);
++
++			amdgpu_bo_unref(&ring->mqd_obj);
++			ring->mqd_obj = NULL;
++		}
++	}
++}
++
++static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->gfx.mec.hpd_eop_obj) {
++		r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
++		if (unlikely(r != 0))
++			dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
++		amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
++		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
++
++		amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
++		adev->gfx.mec.hpd_eop_obj = NULL;
++	}
++}
++
++#define MEC_HPD_SIZE 2048
++
++static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
++{
++	int r;
++	u32 *hpd;
++
++	/*
++	 * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
++	 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
++	 * Nonetheless, we assign only 1 pipe because all other pipes will
++	 * be handled by KFD
++	 */
++	adev->gfx.mec.num_mec = 1;
++	adev->gfx.mec.num_pipe = 1;
++	adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
++
++	if (adev->gfx.mec.hpd_eop_obj == NULL) {
++		r = amdgpu_bo_create(adev,
++				     adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
++				     PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
++				     &adev->gfx.mec.hpd_eop_obj);
++		if (r) {
++			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
++			return r;
++		}
++	}
++
++	r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
++	if (unlikely(r != 0)) {
++		gfx_v7_0_mec_fini(adev);
++		return r;
++	}
++	r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
++			  &adev->gfx.mec.hpd_eop_gpu_addr);
++	if (r) {
++		dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
++		gfx_v7_0_mec_fini(adev);
++		return r;
++	}
++	r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
++	if (r) {
++		dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
++		gfx_v7_0_mec_fini(adev);
++		return r;
++	}
++
++	/* clear memory.  Not sure if this is required or not */
++	memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
++
++	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
++	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
++
++	return 0;
++}
++
++struct hqd_registers
++{
++	u32 cp_mqd_base_addr;
++	u32 cp_mqd_base_addr_hi;
++	u32 cp_hqd_active;
++	u32 cp_hqd_vmid;
++	u32 cp_hqd_persistent_state;
++	u32 cp_hqd_pipe_priority;
++	u32 cp_hqd_queue_priority;
++	u32 cp_hqd_quantum;
++	u32 cp_hqd_pq_base;
++	u32 cp_hqd_pq_base_hi;
++	u32 cp_hqd_pq_rptr;
++	u32 cp_hqd_pq_rptr_report_addr;
++	u32 cp_hqd_pq_rptr_report_addr_hi;
++	u32 cp_hqd_pq_wptr_poll_addr;
++	u32 cp_hqd_pq_wptr_poll_addr_hi;
++	u32 cp_hqd_pq_doorbell_control;
++	u32 cp_hqd_pq_wptr;
++	u32 cp_hqd_pq_control;
++	u32 cp_hqd_ib_base_addr;
++	u32 cp_hqd_ib_base_addr_hi;
++	u32 cp_hqd_ib_rptr;
++	u32 cp_hqd_ib_control;
++	u32 cp_hqd_iq_timer;
++	u32 cp_hqd_iq_rptr;
++	u32 cp_hqd_dequeue_request;
++	u32 cp_hqd_dma_offload;
++	u32 cp_hqd_sema_cmd;
++	u32 cp_hqd_msg_type;
++	u32 cp_hqd_atomic0_preop_lo;
++	u32 cp_hqd_atomic0_preop_hi;
++	u32 cp_hqd_atomic1_preop_lo;
++	u32 cp_hqd_atomic1_preop_hi;
++	u32 cp_hqd_hq_scheduler0;
++	u32 cp_hqd_hq_scheduler1;
++	u32 cp_mqd_control;
++};
++
++struct bonaire_mqd
++{
++	u32 header;
++	u32 dispatch_initiator;
++	u32 dimensions[3];
++	u32 start_idx[3];
++	u32 num_threads[3];
++	u32 pipeline_stat_enable;
++	u32 perf_counter_enable;
++	u32 pgm[2];
++	u32 tba[2];
++	u32 tma[2];
++	u32 pgm_rsrc[2];
++	u32 vmid;
++	u32 resource_limits;
++	u32 static_thread_mgmt01[2];
++	u32 tmp_ring_size;
++	u32 static_thread_mgmt23[2];
++	u32 restart[3];
++	u32 thread_trace_enable;
++	u32 reserved1;
++	u32 user_data[16];
++	u32 vgtcs_invoke_count[2];
++	struct hqd_registers queue_state;
++	u32 dequeue_cntr;
++	u32 interrupt_queue[64];
++};
++
++/**
++ * gfx_v7_0_cp_compute_resume - setup the compute queue registers
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Program the compute queues and test them to make sure they
++ * are working.
++ * Returns 0 for success, error for failure.
++ */
++static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
++{
++	int r, i, j;
++	u32 tmp;
++	bool use_doorbell = true;
++	u64 hqd_gpu_addr;
++	u64 mqd_gpu_addr;
++	u64 eop_gpu_addr;
++	u64 wb_gpu_addr;
++	u32 *buf;
++	struct bonaire_mqd *mqd;
++
++	r = gfx_v7_0_cp_compute_start(adev);
++	if (r)
++		return r;
++
++	/* fix up chicken bits */
++	tmp = RREG32(mmCP_CPF_DEBUG);
++	tmp |= (1 << 23);
++	WREG32(mmCP_CPF_DEBUG, tmp);
++
++	/* init the pipes */
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
++		int me = (i < 4) ? 1 : 2;
++		int pipe = (i < 4) ? i : (i - 4);
++
++		eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
++
++		cik_srbm_select(adev, me, pipe, 0, 0);
++
++		/* write the EOP addr */
++		WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
++		WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
++
++		/* set the VMID assigned */
++		WREG32(mmCP_HPD_EOP_VMID, 0);
++
++		/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
++		tmp = RREG32(mmCP_HPD_EOP_CONTROL);
++		tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
++		tmp |= order_base_2(MEC_HPD_SIZE / 8);
++		WREG32(mmCP_HPD_EOP_CONTROL, tmp);
++	}
++	cik_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++
++	/* init the queues.  Just two for now. */
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
++
++		if (ring->mqd_obj == NULL) {
++			r = amdgpu_bo_create(adev,
++					     sizeof(struct bonaire_mqd),
++					     PAGE_SIZE, true,
++					     AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
++					     &ring->mqd_obj);
++			if (r) {
++				dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
++				return r;
++			}
++		}
++
++		r = amdgpu_bo_reserve(ring->mqd_obj, false);
++		if (unlikely(r != 0)) {
++			gfx_v7_0_cp_compute_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
++				  &mqd_gpu_addr);
++		if (r) {
++			dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
++			gfx_v7_0_cp_compute_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
++		if (r) {
++			dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
++			gfx_v7_0_cp_compute_fini(adev);
++			return r;
++		}
++
++		/* init the mqd struct */
++		memset(buf, 0, sizeof(struct bonaire_mqd));
++
++		mqd = (struct bonaire_mqd *)buf;
++		mqd->header = 0xC0310800;
++		mqd->static_thread_mgmt01[0] = 0xffffffff;
++		mqd->static_thread_mgmt01[1] = 0xffffffff;
++		mqd->static_thread_mgmt23[0] = 0xffffffff;
++		mqd->static_thread_mgmt23[1] = 0xffffffff;
++
++		mutex_lock(&adev->srbm_mutex);
++		cik_srbm_select(adev, ring->me,
++				ring->pipe,
++				ring->queue, 0);
++
++		/* disable wptr polling */
++		tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
++		tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
++		WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
++
++		/* enable doorbell? */
++		mqd->queue_state.cp_hqd_pq_doorbell_control =
++			RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
++		if (use_doorbell)
++			mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
++		else
++			mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
++		WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
++		       mqd->queue_state.cp_hqd_pq_doorbell_control);
++
++		/* disable the queue if it's active */
++		mqd->queue_state.cp_hqd_dequeue_request = 0;
++		mqd->queue_state.cp_hqd_pq_rptr = 0;
++		mqd->queue_state.cp_hqd_pq_wptr= 0;
++		if (RREG32(mmCP_HQD_ACTIVE) & 1) {
++			WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
++					break;
++				udelay(1);
++			}
++			WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
++			WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
++			WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
++		}
++
++		/* set the pointer to the MQD */
++		mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
++		mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
++		WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
++		WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
++		/* set MQD vmid to 0 */
++		mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
++		mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
++		WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
++
++		/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
++		hqd_gpu_addr = ring->gpu_addr >> 8;
++		mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
++		mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
++		WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
++		WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
++
++		/* set up the HQD, this is similar to CP_RB0_CNTL */
++		mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
++		mqd->queue_state.cp_hqd_pq_control &=
++			~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
++					CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
++
++		mqd->queue_state.cp_hqd_pq_control |=
++			order_base_2(ring->ring_size / 8);
++		mqd->queue_state.cp_hqd_pq_control |=
++			(order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
++#ifdef __BIG_ENDIAN
++		mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
++#endif
++		mqd->queue_state.cp_hqd_pq_control &=
++			~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
++				CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
++				CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
++		mqd->queue_state.cp_hqd_pq_control |=
++			CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
++			CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
++		WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
++
++		/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
++		wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
++		mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
++		mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
++		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
++		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
++		       mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
++
++		/* set the wb address wether it's enabled or not */
++		wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
++		mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
++		mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
++			upper_32_bits(wb_gpu_addr) & 0xffff;
++		WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
++		       mqd->queue_state.cp_hqd_pq_rptr_report_addr);
++		WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
++		       mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
++
++		/* enable the doorbell if requested */
++		if (use_doorbell) {
++			mqd->queue_state.cp_hqd_pq_doorbell_control =
++				RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
++			mqd->queue_state.cp_hqd_pq_doorbell_control &=
++				~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
++			mqd->queue_state.cp_hqd_pq_doorbell_control |=
++				(ring->doorbell_index <<
++				 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
++			mqd->queue_state.cp_hqd_pq_doorbell_control |=
++				CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
++			mqd->queue_state.cp_hqd_pq_doorbell_control &=
++				~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
++				CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
++
++		} else {
++			mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
++		}
++		WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
++		       mqd->queue_state.cp_hqd_pq_doorbell_control);
++
++		/* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
++		ring->wptr = 0;
++		mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
++		WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
++		mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
++
++		/* set the vmid for the queue */
++		mqd->queue_state.cp_hqd_vmid = 0;
++		WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
++
++		/* activate the queue */
++		mqd->queue_state.cp_hqd_active = 1;
++		WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
++
++		cik_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++
++		amdgpu_bo_kunmap(ring->mqd_obj);
++		amdgpu_bo_unreserve(ring->mqd_obj);
++
++		ring->ready = true;
++		r = amdgpu_ring_test_ring(ring);
++		if (r)
++			ring->ready = false;
++	}
++
++	return 0;
++}
++
++static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
++{
++	gfx_v7_0_cp_gfx_enable(adev, enable);
++	gfx_v7_0_cp_compute_enable(adev, enable);
++}
++
++static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = gfx_v7_0_cp_gfx_load_microcode(adev);
++	if (r)
++		return r;
++	r = gfx_v7_0_cp_compute_load_microcode(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
++					       bool enable)
++{
++	u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
++
++	if (enable)
++		tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
++				CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
++	else
++		tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
++				CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
++	WREG32(mmCP_INT_CNTL_RING0, tmp);
++}
++
++static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
++
++	r = gfx_v7_0_cp_load_microcode(adev);
++	if (r)
++		return r;
++
++	r = gfx_v7_0_cp_gfx_resume(adev);
++	if (r)
++		return r;
++	r = gfx_v7_0_cp_compute_resume(adev);
++	if (r)
++		return r;
++
++	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
++
++	return 0;
++}
++
++static void gfx_v7_0_ce_sync_me(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
++
++	/* instruct DE to set a magic number */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++							 WRITE_DATA_DST_SEL(5)));
++	amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 1);
++
++	/* let CE wait till condition satisfied */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
++	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
++							 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
++							 WAIT_REG_MEM_FUNCTION(3) |  /* == */
++							 WAIT_REG_MEM_ENGINE(2)));   /* ce */
++	amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 1);
++	amdgpu_ring_write(ring, 0xffffffff);
++	amdgpu_ring_write(ring, 4); /* poll interval */
++
++	/* instruct CE to reset wb of ce_sync to zero */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
++							 WRITE_DATA_DST_SEL(5) |
++							 WR_CONFIRM));
++	amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 0);
++}
++
++/*
++ * vm
++ * VMID 0 is the physical GPU addresses as used by the kernel.
++ * VMIDs 1-15 are used for userspace clients and are handled
++ * by the amdgpu vm/hsa code.
++ */
++/**
++ * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Update the page table base and flush the VM TLB
++ * using the CP (CIK).
++ */
++static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
++					unsigned vm_id, uint64_t pd_addr)
++{
++	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
++				 WRITE_DATA_DST_SEL(0)));
++	if (vm_id < 8) {
++		amdgpu_ring_write(ring,
++				  (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
++	} else {
++		amdgpu_ring_write(ring,
++				  (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
++	}
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, pd_addr >> 12);
++
++	/* update SH_MEM_* regs */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, VMID(vm_id));
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmSH_MEM_BASES);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
++	amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
++	amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
++	amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, VMID(0));
++
++
++	/* bits 0-15 are the VM contexts0-15 */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 1 << vm_id);
++
++	/* wait for the invalidate to complete */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
++	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
++				 WAIT_REG_MEM_FUNCTION(0) |  /* always */
++				 WAIT_REG_MEM_ENGINE(0))); /* me */
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0); /* ref */
++	amdgpu_ring_write(ring, 0); /* mask */
++	amdgpu_ring_write(ring, 0x20); /* poll interval */
++
++	/* compute doesn't have PFP */
++	if (usepfp) {
++		/* sync PFP to ME, otherwise we might get invalid PFP reads */
++		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
++		amdgpu_ring_write(ring, 0x0);
++
++		/* synce CE with ME to prevent CE fetch CEIB before context switch done */
++		gfx_v7_0_ce_sync_me(ring);
++	}
++}
++
++/*
++ * RLC
++ * The RLC is a multi-purpose microengine that handles a
++ * variety of functions.
++ */
++static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	/* save restore block */
++	if (adev->gfx.rlc.save_restore_obj) {
++		r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
++		if (unlikely(r != 0))
++			dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
++		amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
++
++		amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
++		adev->gfx.rlc.save_restore_obj = NULL;
++	}
++
++	/* clear state block */
++	if (adev->gfx.rlc.clear_state_obj) {
++		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++		if (unlikely(r != 0))
++			dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
++		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++
++		amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
++		adev->gfx.rlc.clear_state_obj = NULL;
++	}
++
++	/* clear state block */
++	if (adev->gfx.rlc.cp_table_obj) {
++		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
++		if (unlikely(r != 0))
++			dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
++		amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
++
++		amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
++		adev->gfx.rlc.cp_table_obj = NULL;
++	}
++}
++
++static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
++{
++	const u32 *src_ptr;
++	volatile u32 *dst_ptr;
++	u32 dws, i;
++	const struct cs_section_def *cs_data;
++	int r;
++
++	/* allocate rlc buffers */
++	if (adev->flags & AMDGPU_IS_APU) {
++		if (adev->asic_type == CHIP_KAVERI) {
++			adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
++			adev->gfx.rlc.reg_list_size =
++				(u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
++		} else {
++			adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
++			adev->gfx.rlc.reg_list_size =
++				(u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
++		}
++	}
++	adev->gfx.rlc.cs_data = ci_cs_data;
++	adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
++
++	src_ptr = adev->gfx.rlc.reg_list;
++	dws = adev->gfx.rlc.reg_list_size;
++	dws += (5 * 16) + 48 + 48 + 64;
++
++	cs_data = adev->gfx.rlc.cs_data;
++
++	if (src_ptr) {
++		/* save restore block */
++		if (adev->gfx.rlc.save_restore_obj == NULL) {
++			r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
++					     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.save_restore_obj);
++			if (r) {
++				dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
++				return r;
++			}
++		}
++
++		r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
++		if (unlikely(r != 0)) {
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
++				  &adev->gfx.rlc.save_restore_gpu_addr);
++		if (r) {
++			amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
++			dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++
++		r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
++		if (r) {
++			dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++		/* write the sr buffer */
++		dst_ptr = adev->gfx.rlc.sr_ptr;
++		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
++			dst_ptr[i] = cpu_to_le32(src_ptr[i]);
++		amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
++	}
++
++	if (cs_data) {
++		/* clear state block */
++		adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
++
++		if (adev->gfx.rlc.clear_state_obj == NULL) {
++			r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
++					     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.clear_state_obj);
++			if (r) {
++				dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
++				gfx_v7_0_rlc_fini(adev);
++				return r;
++			}
++		}
++		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++		if (unlikely(r != 0)) {
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
++				  &adev->gfx.rlc.clear_state_gpu_addr);
++		if (r) {
++			amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++			dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++
++		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
++		if (r) {
++			dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++		/* set up the cs buffer */
++		dst_ptr = adev->gfx.rlc.cs_ptr;
++		gfx_v7_0_get_csb_buffer(adev, dst_ptr);
++		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++	}
++
++	if (adev->gfx.rlc.cp_table_size) {
++		if (adev->gfx.rlc.cp_table_obj == NULL) {
++			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
++					     AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.cp_table_obj);
++			if (r) {
++				dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
++				gfx_v7_0_rlc_fini(adev);
++				return r;
++			}
++		}
++
++		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
++		if (unlikely(r != 0)) {
++			dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
++				  &adev->gfx.rlc.cp_table_gpu_addr);
++		if (r) {
++			amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
++			dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
++		if (r) {
++			dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
++			gfx_v7_0_rlc_fini(adev);
++			return r;
++		}
++
++		gfx_v7_0_init_cp_pg_table(adev);
++
++		amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
++
++	}
++
++	return 0;
++}
++
++static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
++{
++	u32 tmp;
++
++	tmp = RREG32(mmRLC_LB_CNTL);
++	if (enable)
++		tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
++	else
++		tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
++	WREG32(mmRLC_LB_CNTL, tmp);
++}
++
++static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
++{
++	u32 i, j, k;
++	u32 mask;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
++		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
++			gfx_v7_0_select_se_sh(adev, i, j);
++			for (k = 0; k < adev->usec_timeout; k++) {
++				if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
++					break;
++				udelay(1);
++			}
++		}
++	}
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
++		RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
++		RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
++		RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
++	for (k = 0; k < adev->usec_timeout; k++) {
++		if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
++			break;
++		udelay(1);
++	}
++}
++
++static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
++{
++	u32 tmp;
++
++	tmp = RREG32(mmRLC_CNTL);
++	if (tmp != rlc)
++		WREG32(mmRLC_CNTL, rlc);
++}
++
++static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_CNTL);
++
++	if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
++		u32 i;
++
++		data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
++		WREG32(mmRLC_CNTL, data);
++
++		for (i = 0; i < adev->usec_timeout; i++) {
++			if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
++				break;
++			udelay(1);
++		}
++
++		gfx_v7_0_wait_for_rlc_serdes(adev);
++	}
++
++	return orig;
++}
++
++void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
++{
++	u32 tmp, i, mask;
++
++	tmp = 0x1 | (1 << 1);
++	WREG32(mmRLC_GPR_REG2, tmp);
++
++	mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
++		RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
++			break;
++		udelay(1);
++	}
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
++			break;
++		udelay(1);
++	}
++}
++
++void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	tmp = 0x1 | (0 << 1);
++	WREG32(mmRLC_GPR_REG2, tmp);
++}
++
++/**
++ * gfx_v7_0_rlc_stop - stop the RLC ME
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Halt the RLC ME (MicroEngine) (CIK).
++ */
++void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
++{
++	WREG32(mmRLC_CNTL, 0);
++
++	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
++
++	gfx_v7_0_wait_for_rlc_serdes(adev);
++}
++
++/**
++ * gfx_v7_0_rlc_start - start the RLC ME
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Unhalt the RLC ME (MicroEngine) (CIK).
++ */
++static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
++{
++	WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
++
++	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
++
++	udelay(50);
++}
++
++static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmGRBM_SOFT_RESET);
++
++	tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
++	WREG32(mmGRBM_SOFT_RESET, tmp);
++	udelay(50);
++	tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
++	WREG32(mmGRBM_SOFT_RESET, tmp);
++	udelay(50);
++}
++
++/**
++ * gfx_v7_0_rlc_resume - setup the RLC hw
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initialize the RLC registers, load the ucode,
++ * and start the RLC (CIK).
++ * Returns 0 for success, -EINVAL if the ucode is not available.
++ */
++static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
++{
++	const struct rlc_firmware_header_v1_0 *hdr;
++	const __le32 *fw_data;
++	unsigned i, fw_size;
++	u32 tmp;
++
++	if (!adev->gfx.rlc_fw)
++		return -EINVAL;
++
++	hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
++	amdgpu_ucode_print_rlc_hdr(&hdr->header);
++	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
++
++	gfx_v7_0_rlc_stop(adev);
++
++	/* disable CG */
++	tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
++	WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
++
++	gfx_v7_0_rlc_reset(adev);
++
++	gfx_v7_0_init_pg(adev);
++
++	WREG32(mmRLC_LB_CNTR_INIT, 0);
++	WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
++	WREG32(mmRLC_LB_PARAMS, 0x00600408);
++	WREG32(mmRLC_LB_CNTL, 0x80000004);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	WREG32(mmRLC_MC_CNTL, 0);
++	WREG32(mmRLC_UCODE_CNTL, 0);
++
++	fw_data = (const __le32 *)
++		(adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmRLC_GPM_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
++
++	/* XXX - find out what chips support lbpw */
++	gfx_v7_0_enable_lbpw(adev, false);
++
++	if (adev->asic_type == CHIP_BONAIRE)
++		WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
++
++	gfx_v7_0_rlc_start(adev);
++
++	return 0;
++}
++
++static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
++{
++	u32 data, orig, tmp, tmp2;
++
++	orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
++		gfx_v7_0_enable_gui_idle_interrupt(adev, true);
++
++		tmp = gfx_v7_0_halt_rlc(adev);
++
++		mutex_lock(&adev->grbm_idx_mutex);
++		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++		WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
++		WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
++		tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
++			RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
++			RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
++		WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
++		mutex_unlock(&adev->grbm_idx_mutex);
++
++		gfx_v7_0_update_rlc(adev, tmp);
++
++		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
++	} else {
++		gfx_v7_0_enable_gui_idle_interrupt(adev, false);
++
++		RREG32(mmCB_CGTT_SCLK_CTRL);
++		RREG32(mmCB_CGTT_SCLK_CTRL);
++		RREG32(mmCB_CGTT_SCLK_CTRL);
++		RREG32(mmCB_CGTT_SCLK_CTRL);
++
++		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
++	}
++
++	if (orig != data)
++		WREG32(mmRLC_CGCG_CGLS_CTRL, data);
++
++}
++
++static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
++{
++	u32 data, orig, tmp = 0;
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
++		if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
++			if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
++				orig = data = RREG32(mmCP_MEM_SLP_CNTL);
++				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
++				if (orig != data)
++					WREG32(mmCP_MEM_SLP_CNTL, data);
++			}
++		}
++
++		orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
++		data |= 0x00000001;
++		data &= 0xfffffffd;
++		if (orig != data)
++			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
++
++		tmp = gfx_v7_0_halt_rlc(adev);
++
++		mutex_lock(&adev->grbm_idx_mutex);
++		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++		WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
++		WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
++		data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
++			RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
++		WREG32(mmRLC_SERDES_WR_CTRL, data);
++		mutex_unlock(&adev->grbm_idx_mutex);
++
++		gfx_v7_0_update_rlc(adev, tmp);
++
++		if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
++			orig = data = RREG32(mmCGTS_SM_CTRL_REG);
++			data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
++			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
++			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
++			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
++			if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
++			    (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
++				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
++			data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
++			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
++			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
++			if (orig != data)
++				WREG32(mmCGTS_SM_CTRL_REG, data);
++		}
++	} else {
++		orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
++		data |= 0x00000003;
++		if (orig != data)
++			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
++
++		data = RREG32(mmRLC_MEM_SLP_CNTL);
++		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
++			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
++			WREG32(mmRLC_MEM_SLP_CNTL, data);
++		}
++
++		data = RREG32(mmCP_MEM_SLP_CNTL);
++		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
++			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
++			WREG32(mmCP_MEM_SLP_CNTL, data);
++		}
++
++		orig = data = RREG32(mmCGTS_SM_CTRL_REG);
++		data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
++		if (orig != data)
++			WREG32(mmCGTS_SM_CTRL_REG, data);
++
++		tmp = gfx_v7_0_halt_rlc(adev);
++
++		mutex_lock(&adev->grbm_idx_mutex);
++		gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++		WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
++		WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
++		data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
++		WREG32(mmRLC_SERDES_WR_CTRL, data);
++		mutex_unlock(&adev->grbm_idx_mutex);
++
++		gfx_v7_0_update_rlc(adev, tmp);
++	}
++}
++
++static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
++			       bool enable)
++{
++	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
++	/* order matters! */
++	if (enable) {
++		gfx_v7_0_enable_mgcg(adev, true);
++		gfx_v7_0_enable_cgcg(adev, true);
++	} else {
++		gfx_v7_0_enable_cgcg(adev, false);
++		gfx_v7_0_enable_mgcg(adev, false);
++	}
++	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
++}
++
++static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
++						bool enable)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
++		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
++	else
++		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++}
++
++static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
++						bool enable)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
++		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
++	else
++		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++}
++
++static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
++		data &= ~0x8000;
++	else
++		data |= 0x8000;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++}
++
++static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
++		data &= ~0x2000;
++	else
++		data |= 0x2000;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++}
++
++static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
++{
++	const __le32 *fw_data;
++	volatile u32 *dst_ptr;
++	int me, i, max_me = 4;
++	u32 bo_offset = 0;
++	u32 table_offset, table_size;
++
++	if (adev->asic_type == CHIP_KAVERI)
++		max_me = 5;
++
++	if (adev->gfx.rlc.cp_table_ptr == NULL)
++		return;
++
++	/* write the cp table buffer */
++	dst_ptr = adev->gfx.rlc.cp_table_ptr;
++	for (me = 0; me < max_me; me++) {
++		if (me == 0) {
++			const struct gfx_firmware_header_v1_0 *hdr =
++				(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
++			fw_data = (const __le32 *)
++				(adev->gfx.ce_fw->data +
++				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++			table_offset = le32_to_cpu(hdr->jt_offset);
++			table_size = le32_to_cpu(hdr->jt_size);
++		} else if (me == 1) {
++			const struct gfx_firmware_header_v1_0 *hdr =
++				(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
++			fw_data = (const __le32 *)
++				(adev->gfx.pfp_fw->data +
++				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++			table_offset = le32_to_cpu(hdr->jt_offset);
++			table_size = le32_to_cpu(hdr->jt_size);
++		} else if (me == 2) {
++			const struct gfx_firmware_header_v1_0 *hdr =
++				(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
++			fw_data = (const __le32 *)
++				(adev->gfx.me_fw->data +
++				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++			table_offset = le32_to_cpu(hdr->jt_offset);
++			table_size = le32_to_cpu(hdr->jt_size);
++		} else if (me == 3) {
++			const struct gfx_firmware_header_v1_0 *hdr =
++				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
++			fw_data = (const __le32 *)
++				(adev->gfx.mec_fw->data +
++				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++			table_offset = le32_to_cpu(hdr->jt_offset);
++			table_size = le32_to_cpu(hdr->jt_size);
++		} else {
++			const struct gfx_firmware_header_v1_0 *hdr =
++				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
++			fw_data = (const __le32 *)
++				(adev->gfx.mec2_fw->data +
++				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++			table_offset = le32_to_cpu(hdr->jt_offset);
++			table_size = le32_to_cpu(hdr->jt_size);
++		}
++
++		for (i = 0; i < table_size; i ++) {
++			dst_ptr[bo_offset + i] =
++				cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
++		}
++
++		bo_offset += table_size;
++	}
++}
++
++static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
++				     bool enable)
++{
++	u32 data, orig;
++
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
++		orig = data = RREG32(mmRLC_PG_CNTL);
++		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
++		if (orig != data)
++			WREG32(mmRLC_PG_CNTL, data);
++
++		orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
++		data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
++		if (orig != data)
++			WREG32(mmRLC_AUTO_PG_CTRL, data);
++	} else {
++		orig = data = RREG32(mmRLC_PG_CNTL);
++		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
++		if (orig != data)
++			WREG32(mmRLC_PG_CNTL, data);
++
++		orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
++		data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
++		if (orig != data)
++			WREG32(mmRLC_AUTO_PG_CTRL, data);
++
++		data = RREG32(mmDB_RENDER_CONTROL);
++	}
++}
++
++static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev,
++					 u32 se, u32 sh)
++{
++	u32 mask = 0, tmp, tmp1;
++	int i;
++
++	gfx_v7_0_select_se_sh(adev, se, sh);
++	tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
++	tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++
++	tmp &= 0xffff0000;
++
++	tmp |= tmp1;
++	tmp >>= 16;
++
++	for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
++		mask <<= 1;
++		mask |= 1;
++	}
++
++	return (~tmp) & mask;
++}
++
++static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
++{
++	uint32_t tmp, active_cu_number;
++	struct amdgpu_cu_info cu_info;
++
++	gfx_v7_0_get_cu_info(adev, &cu_info);
++	tmp = cu_info.ao_cu_mask;
++	active_cu_number = cu_info.number;
++
++	WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
++
++	tmp = RREG32(mmRLC_MAX_PG_CU);
++	tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
++	tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
++	WREG32(mmRLC_MAX_PG_CU, tmp);
++}
++
++static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
++					    bool enable)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
++		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
++	else
++		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++}
++
++static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
++					     bool enable)
++{
++	u32 data, orig;
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
++		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
++	else
++		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++}
++
++#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
++#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
++
++static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
++{
++	u32 data, orig;
++	u32 i;
++
++	if (adev->gfx.rlc.cs_data) {
++		WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
++		WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
++		WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
++		WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
++	} else {
++		WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
++		for (i = 0; i < 3; i++)
++			WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
++	}
++	if (adev->gfx.rlc.reg_list) {
++		WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
++		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
++			WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
++	}
++
++	orig = data = RREG32(mmRLC_PG_CNTL);
++	data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
++	if (orig != data)
++		WREG32(mmRLC_PG_CNTL, data);
++
++	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
++	WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
++
++	data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
++	data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
++	data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
++	WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
++
++	data = 0x10101010;
++	WREG32(mmRLC_PG_DELAY, data);
++
++	data = RREG32(mmRLC_PG_DELAY_2);
++	data &= ~0xff;
++	data |= 0x3;
++	WREG32(mmRLC_PG_DELAY_2, data);
++
++	data = RREG32(mmRLC_AUTO_PG_CTRL);
++	data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
++	data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
++	WREG32(mmRLC_AUTO_PG_CTRL, data);
++
++}
++
++static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
++{
++	gfx_v7_0_enable_gfx_cgpg(adev, enable);
++	gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
++	gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
++}
++
++static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
++{
++	u32 count = 0;
++	const struct cs_section_def *sect = NULL;
++	const struct cs_extent_def *ext = NULL;
++
++	if (adev->gfx.rlc.cs_data == NULL)
++		return 0;
++
++	/* begin clear state */
++	count += 2;
++	/* context control state */
++	count += 3;
++
++	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
++		for (ext = sect->section; ext->extent != NULL; ++ext) {
++			if (sect->id == SECT_CONTEXT)
++				count += 2 + ext->reg_count;
++			else
++				return 0;
++		}
++	}
++	/* pa_sc_raster_config/pa_sc_raster_config1 */
++	count += 4;
++	/* end clear state */
++	count += 2;
++	/* clear state */
++	count += 2;
++
++	return count;
++}
++
++static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
++				    volatile u32 *buffer)
++{
++	u32 count = 0, i;
++	const struct cs_section_def *sect = NULL;
++	const struct cs_extent_def *ext = NULL;
++
++	if (adev->gfx.rlc.cs_data == NULL)
++		return;
++	if (buffer == NULL)
++		return;
++
++	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
++	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
++
++	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
++	buffer[count++] = cpu_to_le32(0x80000000);
++	buffer[count++] = cpu_to_le32(0x80000000);
++
++	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
++		for (ext = sect->section; ext->extent != NULL; ++ext) {
++			if (sect->id == SECT_CONTEXT) {
++				buffer[count++] =
++					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
++				buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
++				for (i = 0; i < ext->reg_count; i++)
++					buffer[count++] = cpu_to_le32(ext->extent[i]);
++			} else {
++				return;
++			}
++		}
++	}
++
++	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
++	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		buffer[count++] = cpu_to_le32(0x16000012);
++		buffer[count++] = cpu_to_le32(0x00000000);
++		break;
++	case CHIP_KAVERI:
++		buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
++		buffer[count++] = cpu_to_le32(0x00000000);
++		break;
++	case CHIP_KABINI:
++	case CHIP_MULLINS:
++		buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
++		buffer[count++] = cpu_to_le32(0x00000000);
++		break;
++	case CHIP_HAWAII:
++		buffer[count++] = cpu_to_le32(0x3a00161a);
++		buffer[count++] = cpu_to_le32(0x0000002e);
++		break;
++	default:
++		buffer[count++] = cpu_to_le32(0x00000000);
++		buffer[count++] = cpu_to_le32(0x00000000);
++		break;
++	}
++
++	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
++	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
++
++	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
++	buffer[count++] = cpu_to_le32(0);
++}
++
++static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
++{
++	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
++			      AMDGPU_PG_SUPPORT_GFX_SMG |
++			      AMDGPU_PG_SUPPORT_GFX_DMG |
++			      AMDGPU_PG_SUPPORT_CP |
++			      AMDGPU_PG_SUPPORT_GDS |
++			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
++		gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
++		gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
++		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
++			gfx_v7_0_init_gfx_cgpg(adev);
++			gfx_v7_0_enable_cp_pg(adev, true);
++			gfx_v7_0_enable_gds_pg(adev, true);
++		}
++		gfx_v7_0_init_ao_cu_mask(adev);
++		gfx_v7_0_update_gfx_pg(adev, true);
++	}
++}
++
++static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
++{
++	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
++			      AMDGPU_PG_SUPPORT_GFX_SMG |
++			      AMDGPU_PG_SUPPORT_GFX_DMG |
++			      AMDGPU_PG_SUPPORT_CP |
++			      AMDGPU_PG_SUPPORT_GDS |
++			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
++		gfx_v7_0_update_gfx_pg(adev, false);
++		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
++			gfx_v7_0_enable_cp_pg(adev, false);
++			gfx_v7_0_enable_gds_pg(adev, false);
++		}
++	}
++}
++
++/**
++ * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Fetches a GPU clock counter snapshot (SI).
++ * Returns the 64 bit clock counter snapshot.
++ */
++uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
++{
++	uint64_t clock;
++
++	mutex_lock(&adev->gfx.gpu_clock_mutex);
++	WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
++	clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
++		((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++	mutex_unlock(&adev->gfx.gpu_clock_mutex);
++	return clock;
++}
++
++static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
++					  uint32_t vmid,
++					  uint32_t gds_base, uint32_t gds_size,
++					  uint32_t gws_base, uint32_t gws_size,
++					  uint32_t oa_base, uint32_t oa_size)
++{
++	gds_base = gds_base >> AMDGPU_GDS_SHIFT;
++	gds_size = gds_size >> AMDGPU_GDS_SHIFT;
++
++	gws_base = gws_base >> AMDGPU_GWS_SHIFT;
++	gws_size = gws_size >> AMDGPU_GWS_SHIFT;
++
++	oa_base = oa_base >> AMDGPU_OA_SHIFT;
++	oa_size = oa_size >> AMDGPU_OA_SHIFT;
++
++	/* GDS Base */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, gds_base);
++
++	/* GDS Size */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, gds_size);
++
++	/* GWS */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
++
++	/* OA */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
++}
++
++static int gfx_v7_0_early_init(struct amdgpu_device *adev)
++{
++
++	adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
++	adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
++	gfx_v7_0_set_ring_funcs(adev);
++	gfx_v7_0_set_irq_funcs(adev);
++	gfx_v7_0_set_gds_init(adev);
++
++	return 0;
++}
++
++static int gfx_v7_0_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int i, r;
++
++	/* EOP Event */
++	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
++	if (r)
++		return r;
++
++	/* Privileged reg */
++	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
++	if (r)
++		return r;
++
++	/* Privileged inst */
++	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
++	if (r)
++		return r;
++
++	gfx_v7_0_scratch_init(adev);
++
++	r = gfx_v7_0_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load gfx firmware!\n");
++		return r;
++	}
++
++	r = gfx_v7_0_rlc_init(adev);
++	if (r) {
++		DRM_ERROR("Failed to init rlc BOs!\n");
++		return r;
++	}
++
++	/* allocate mec buffers */
++	r = gfx_v7_0_mec_init(adev);
++	if (r) {
++		DRM_ERROR("Failed to init MEC BOs!\n");
++		return r;
++	}
++
++	r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
++	if (r) {
++		DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
++		return r;
++	}
++
++	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
++		ring = &adev->gfx.gfx_ring[i];
++		ring->ring_obj = NULL;
++		sprintf(ring->name, "gfx");
++		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
++				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
++				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
++				     AMDGPU_RING_TYPE_GFX);
++		if (r)
++			return r;
++	}
++
++	/* set up the compute queues */
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		unsigned irq_type;
++
++		/* max 32 queues per MEC */
++		if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
++			DRM_ERROR("Too many (%d) compute rings!\n", i);
++			break;
++		}
++		ring = &adev->gfx.compute_ring[i];
++		ring->ring_obj = NULL;
++		ring->use_doorbell = true;
++		ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
++		ring->me = 1; /* first MEC */
++		ring->pipe = i / 8;
++		ring->queue = i % 8;
++		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
++		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
++		/* type-2 packets are deprecated on MEC, use type-3 instead */
++		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
++				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
++				     &adev->gfx.eop_irq, irq_type,
++				     AMDGPU_RING_TYPE_COMPUTE);
++		if (r)
++			return r;
++	}
++
++	/* reserve GDS, GWS and OA resource for gfx */
++	r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
++			PAGE_SIZE, true,
++			AMDGPU_GEM_DOMAIN_GDS, 0,
++			NULL, &adev->gds.gds_gfx_bo);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
++		PAGE_SIZE, true,
++		AMDGPU_GEM_DOMAIN_GWS, 0,
++		NULL, &adev->gds.gws_gfx_bo);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
++			PAGE_SIZE, true,
++			AMDGPU_GEM_DOMAIN_OA, 0,
++			NULL, &adev->gds.oa_gfx_bo);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int gfx_v7_0_sw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
++	amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
++	amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
++
++	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
++	for (i = 0; i < adev->gfx.num_compute_rings; i++)
++		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
++
++	amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
++
++	gfx_v7_0_cp_compute_fini(adev);
++	gfx_v7_0_rlc_fini(adev);
++	gfx_v7_0_mec_fini(adev);
++
++	return 0;
++}
++
++static int gfx_v7_0_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	gfx_v7_0_gpu_init(adev);
++
++	/* init rlc */
++	r = gfx_v7_0_rlc_resume(adev);
++	if (r)
++		return r;
++
++	r = gfx_v7_0_cp_resume(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int gfx_v7_0_hw_fini(struct amdgpu_device *adev)
++{
++	gfx_v7_0_cp_enable(adev, false);
++	gfx_v7_0_rlc_stop(adev);
++	gfx_v7_0_fini_pg(adev);
++
++	return 0;
++}
++
++static int gfx_v7_0_suspend(struct amdgpu_device *adev)
++{
++	return gfx_v7_0_hw_fini(adev);
++}
++
++static int gfx_v7_0_resume(struct amdgpu_device *adev)
++{
++	return gfx_v7_0_hw_init(adev);
++}
++
++static bool gfx_v7_0_is_idle(struct amdgpu_device *adev)
++{
++	if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
++		return false;
++	else
++		return true;
++}
++
++static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
++
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void gfx_v7_0_print_status(struct amdgpu_device *adev)
++{
++	int i;
++
++	dev_info(adev->dev, "GFX 7.x registers\n");
++	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
++		RREG32(mmGRBM_STATUS));
++	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
++		RREG32(mmGRBM_STATUS2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE0));
++	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE1));
++	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE3));
++	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
++	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT2));
++	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT3));
++	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
++		 RREG32(mmCP_CPF_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPF_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
++	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPC_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
++
++	for (i = 0; i < 32; i++) {
++		dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
++			 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
++	}
++	for (i = 0; i < 16; i++) {
++		dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
++			 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
++	}
++	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
++		dev_info(adev->dev, "  se: %d\n", i);
++		gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
++		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
++			 RREG32(mmPA_SC_RASTER_CONFIG));
++		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
++			 RREG32(mmPA_SC_RASTER_CONFIG_1));
++	}
++	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++
++	dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmGB_ADDR_CONFIG));
++	dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmHDP_ADDR_CONFIG));
++	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
++		 RREG32(mmDMIF_ADDR_CALC));
++	dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
++		 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
++	dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
++		 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
++	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
++
++	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
++		 RREG32(mmCP_MEQ_THRESHOLDS));
++	dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
++		 RREG32(mmSX_DEBUG_1));
++	dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
++		 RREG32(mmTA_CNTL_AUX));
++	dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
++		 RREG32(mmSPI_CONFIG_CNTL));
++	dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
++		 RREG32(mmSQ_CONFIG));
++	dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
++		 RREG32(mmDB_DEBUG));
++	dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
++		 RREG32(mmDB_DEBUG2));
++	dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
++		 RREG32(mmDB_DEBUG3));
++	dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
++		 RREG32(mmCB_HW_CONTROL));
++	dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
++		 RREG32(mmSPI_CONFIG_CNTL_1));
++	dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
++		 RREG32(mmPA_SC_FIFO_SIZE));
++	dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
++		 RREG32(mmVGT_NUM_INSTANCES));
++	dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
++		 RREG32(mmCP_PERFMON_CNTL));
++	dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
++		 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
++	dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
++		 RREG32(mmVGT_CACHE_INVALIDATION));
++	dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
++		 RREG32(mmVGT_GS_VERTEX_REUSE));
++	dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
++		 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
++	dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
++		 RREG32(mmPA_CL_ENHANCE));
++	dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
++		 RREG32(mmPA_SC_ENHANCE));
++
++	dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
++		 RREG32(mmCP_ME_CNTL));
++	dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
++		 RREG32(mmCP_MAX_CONTEXT));
++	dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
++		 RREG32(mmCP_ENDIAN_SWAP));
++	dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
++		 RREG32(mmCP_DEVICE_ID));
++
++	dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
++		 RREG32(mmCP_SEM_WAIT_TIMER));
++	if (adev->asic_type != CHIP_HAWAII)
++		dev_info(adev->dev, "  CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
++			 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
++
++	dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
++		 RREG32(mmCP_RB_WPTR_DELAY));
++	dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
++		 RREG32(mmCP_RB_VMID));
++	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
++		 RREG32(mmCP_RB0_CNTL));
++	dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
++		 RREG32(mmCP_RB0_WPTR));
++	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
++		 RREG32(mmCP_RB0_RPTR_ADDR));
++	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
++		 RREG32(mmCP_RB0_RPTR_ADDR_HI));
++	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
++		 RREG32(mmCP_RB0_CNTL));
++	dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
++		 RREG32(mmCP_RB0_BASE));
++	dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
++		 RREG32(mmCP_RB0_BASE_HI));
++	dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
++		 RREG32(mmCP_MEC_CNTL));
++	dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
++		 RREG32(mmCP_CPF_DEBUG));
++
++	dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
++		 RREG32(mmSCRATCH_ADDR));
++	dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
++		 RREG32(mmSCRATCH_UMSK));
++
++	/* init the pipes */
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
++		int me = (i < 4) ? 1 : 2;
++		int pipe = (i < 4) ? i : (i - 4);
++		int queue;
++
++		dev_info(adev->dev, "  me: %d, pipe: %d\n", me, pipe);
++		cik_srbm_select(adev, me, pipe, 0, 0);
++		dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR=0x%08X\n",
++			 RREG32(mmCP_HPD_EOP_BASE_ADDR));
++		dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
++			 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
++		dev_info(adev->dev, "  CP_HPD_EOP_VMID=0x%08X\n",
++			 RREG32(mmCP_HPD_EOP_VMID));
++		dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",
++			 RREG32(mmCP_HPD_EOP_CONTROL));
++
++		for (queue = 0; queue < 8; i++) {
++			cik_srbm_select(adev, me, pipe, queue, 0);
++			dev_info(adev->dev, "  queue: %d\n", queue);
++			dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
++				 RREG32(mmCP_PQ_WPTR_POLL_CNTL));
++			dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
++			dev_info(adev->dev, "  CP_HQD_ACTIVE=0x%08X\n",
++				 RREG32(mmCP_HQD_ACTIVE));
++			dev_info(adev->dev, "  CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
++				 RREG32(mmCP_HQD_DEQUEUE_REQUEST));
++			dev_info(adev->dev, "  CP_HQD_PQ_RPTR=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_RPTR));
++			dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_WPTR));
++			dev_info(adev->dev, "  CP_HQD_PQ_BASE=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_BASE));
++			dev_info(adev->dev, "  CP_HQD_PQ_BASE_HI=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_BASE_HI));
++			dev_info(adev->dev, "  CP_HQD_PQ_CONTROL=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_CONTROL));
++			dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
++			dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
++			dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
++			dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
++			dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
++			dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
++				 RREG32(mmCP_HQD_PQ_WPTR));
++			dev_info(adev->dev, "  CP_HQD_VMID=0x%08X\n",
++				 RREG32(mmCP_HQD_VMID));
++			dev_info(adev->dev, "  CP_MQD_BASE_ADDR=0x%08X\n",
++				 RREG32(mmCP_MQD_BASE_ADDR));
++			dev_info(adev->dev, "  CP_MQD_BASE_ADDR_HI=0x%08X\n",
++				 RREG32(mmCP_MQD_BASE_ADDR_HI));
++			dev_info(adev->dev, "  CP_MQD_CONTROL=0x%08X\n",
++				 RREG32(mmCP_MQD_CONTROL));
++		}
++	}
++	cik_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++
++	dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
++		 RREG32(mmCP_INT_CNTL_RING0));
++	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTL));
++	dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
++		 RREG32(mmRLC_CNTL));
++	dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
++		 RREG32(mmRLC_CGCG_CGLS_CTRL));
++	dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTR_INIT));
++	dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTR_MAX));
++	dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
++		 RREG32(mmRLC_LB_INIT_CU_MASK));
++	dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
++		 RREG32(mmRLC_LB_PARAMS));
++	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTL));
++	dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
++		 RREG32(mmRLC_MC_CNTL));
++	dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
++		 RREG32(mmRLC_UCODE_CNTL));
++
++	if (adev->asic_type == CHIP_BONAIRE)
++		dev_info(adev->dev, "  RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
++			 RREG32(mmRLC_DRIVER_CPDMA_STATUS));
++
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < 16; i++) {
++		cik_srbm_select(adev, 0, 0, 0, i);
++		dev_info(adev->dev, "  VM %d:\n", i);
++		dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
++			 RREG32(mmSH_MEM_CONFIG));
++		dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
++			 RREG32(mmSH_MEM_APE1_BASE));
++		dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
++			 RREG32(mmSH_MEM_APE1_LIMIT));
++		dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
++			 RREG32(mmSH_MEM_BASES));
++	}
++	cik_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++}
++
++static int gfx_v7_0_soft_reset(struct amdgpu_device *adev)
++{
++	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
++	u32 tmp;
++
++	/* GRBM_STATUS */
++	tmp = RREG32(mmGRBM_STATUS);
++	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
++		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
++		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
++		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
++		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
++		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
++		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
++			GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
++
++	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
++		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
++	}
++
++	/* GRBM_STATUS2 */
++	tmp = RREG32(mmGRBM_STATUS2);
++	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
++		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
++
++	/* SRBM_STATUS */
++	tmp = RREG32(mmSRBM_STATUS);
++	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
++
++	if (grbm_soft_reset || srbm_soft_reset) {
++		gfx_v7_0_print_status(adev);
++		/* disable CG/PG */
++		gfx_v7_0_fini_pg(adev);
++		gfx_v7_0_update_cg(adev, false);
++
++		/* stop the rlc */
++		gfx_v7_0_rlc_stop(adev);
++
++		/* Disable GFX parsing/prefetching */
++		WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
++
++		/* Disable MEC parsing/prefetching */
++		WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
++
++		if (grbm_soft_reset) {
++			tmp = RREG32(mmGRBM_SOFT_RESET);
++			tmp |= grbm_soft_reset;
++			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
++			WREG32(mmGRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmGRBM_SOFT_RESET);
++
++			udelay(50);
++
++			tmp &= ~grbm_soft_reset;
++			WREG32(mmGRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmGRBM_SOFT_RESET);
++		}
++
++		if (srbm_soft_reset) {
++			tmp = RREG32(mmSRBM_SOFT_RESET);
++			tmp |= srbm_soft_reset;
++			dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++			WREG32(mmSRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmSRBM_SOFT_RESET);
++
++			udelay(50);
++
++			tmp &= ~srbm_soft_reset;
++			WREG32(mmSRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmSRBM_SOFT_RESET);
++		}
++		/* Wait a little for things to settle down */
++		udelay(50);
++		gfx_v7_0_print_status(adev);
++	}
++	return 0;
++}
++
++static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
++						 enum amdgpu_interrupt_state state)
++{
++	u32 cp_int_cntl;
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	default:
++		break;
++	}
++}
++
++static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
++						     int me, int pipe,
++						     enum amdgpu_interrupt_state state)
++{
++	u32 mec_int_cntl, mec_int_cntl_reg;
++
++	/*
++	 * amdgpu controls only pipe 0 of MEC1. That's why this function only
++	 * handles the setting of interrupts for this specific pipe. All other
++	 * pipes' interrupts are set by amdkfd.
++	 */
++
++	if (me == 1) {
++		switch (pipe) {
++		case 0:
++			mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
++			break;
++		default:
++			DRM_DEBUG("invalid pipe %d\n", pipe);
++			return;
++		}
++	} else {
++		DRM_DEBUG("invalid me %d\n", me);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		mec_int_cntl = RREG32(mec_int_cntl_reg);
++		mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
++		WREG32(mec_int_cntl_reg, mec_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		mec_int_cntl = RREG32(mec_int_cntl_reg);
++		mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
++		WREG32(mec_int_cntl_reg, mec_int_cntl);
++		break;
++	default:
++		break;
++	}
++}
++
++static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
++					     struct amdgpu_irq_src *src,
++					     unsigned type,
++					     enum amdgpu_interrupt_state state)
++{
++	u32 cp_int_cntl;
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
++					      struct amdgpu_irq_src *src,
++					      unsigned type,
++					      enum amdgpu_interrupt_state state)
++{
++	u32 cp_int_cntl;
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
++					    struct amdgpu_irq_src *src,
++					    unsigned type,
++					    enum amdgpu_interrupt_state state)
++{
++	switch (type) {
++	case AMDGPU_CP_IRQ_GFX_EOP:
++		gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
++		gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
++			    struct amdgpu_irq_src *source,
++			    struct amdgpu_iv_entry *entry)
++{
++	u8 me_id, pipe_id;
++	struct amdgpu_ring *ring;
++	int i;
++
++	DRM_DEBUG("IH: CP EOP\n");
++	me_id = (entry->ring_id & 0x0c) >> 2;
++	pipe_id = (entry->ring_id & 0x03) >> 0;
++	switch (me_id) {
++	case 0:
++		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
++		break;
++	case 1:
++	case 2:
++		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++			ring = &adev->gfx.compute_ring[i];
++			if ((ring->me == me_id) & (ring->pipe == pipe_id))
++				amdgpu_fence_process(ring);
++		}
++		break;
++	}
++	return 0;
++}
++
++static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
++				 struct amdgpu_irq_src *source,
++				 struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal register access in command stream\n");
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
++				  struct amdgpu_irq_src *source,
++				  struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal instruction in command stream\n");
++	// XXX soft reset the gfx block only
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	bool gate = false;
++
++	if (state == AMDGPU_CG_STATE_GATE)
++		gate = true;
++
++	gfx_v7_0_enable_gui_idle_interrupt(adev, false);
++	/* order matters! */
++	if (gate) {
++		gfx_v7_0_enable_mgcg(adev, true);
++		gfx_v7_0_enable_cgcg(adev, true);
++	} else {
++		gfx_v7_0_enable_cgcg(adev, false);
++		gfx_v7_0_enable_mgcg(adev, false);
++	}
++	gfx_v7_0_enable_gui_idle_interrupt(adev, true);
++
++	return 0;
++}
++
++static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	bool gate = false;
++
++	if (state == AMDGPU_PG_STATE_GATE)
++		gate = true;
++
++	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
++			      AMDGPU_PG_SUPPORT_GFX_SMG |
++			      AMDGPU_PG_SUPPORT_GFX_DMG |
++			      AMDGPU_PG_SUPPORT_CP |
++			      AMDGPU_PG_SUPPORT_GDS |
++			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
++		gfx_v7_0_update_gfx_pg(adev, gate);
++		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
++			gfx_v7_0_enable_cp_pg(adev, gate);
++			gfx_v7_0_enable_gds_pg(adev, gate);
++		}
++	}
++
++	return 0;
++}
++
++const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs = {
++	.early_init = gfx_v7_0_early_init,
++	.late_init = NULL,
++	.sw_init = gfx_v7_0_sw_init,
++	.sw_fini = gfx_v7_0_sw_fini,
++	.hw_init = gfx_v7_0_hw_init,
++	.hw_fini = gfx_v7_0_hw_fini,
++	.suspend = gfx_v7_0_suspend,
++	.resume = gfx_v7_0_resume,
++	.is_idle = gfx_v7_0_is_idle,
++	.wait_for_idle = gfx_v7_0_wait_for_idle,
++	.soft_reset = gfx_v7_0_soft_reset,
++	.print_status = gfx_v7_0_print_status,
++	.set_clockgating_state = gfx_v7_0_set_clockgating_state,
++	.set_powergating_state = gfx_v7_0_set_powergating_state,
++};
++
++/**
++ * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up
++ *
++ * @adev: amdgpu_device pointer
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Check if the 3D engine is locked up (CIK).
++ * Returns true if the engine is locked, false if not.
++ */
++static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring)
++{
++	if (gfx_v7_0_is_idle(ring->adev)) {
++		amdgpu_ring_lockup_update(ring);
++		return false;
++	}
++	return amdgpu_ring_test_lockup(ring);
++}
++
++static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
++	.get_rptr = gfx_v7_0_ring_get_rptr_gfx,
++	.get_wptr = gfx_v7_0_ring_get_wptr_gfx,
++	.set_wptr = gfx_v7_0_ring_set_wptr_gfx,
++	.parse_cs = NULL,
++	.emit_ib = gfx_v7_0_ring_emit_ib,
++	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
++	.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
++	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
++	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
++	.test_ring = gfx_v7_0_ring_test_ring,
++	.test_ib = gfx_v7_0_ring_test_ib,
++	.is_lockup = gfx_v7_0_ring_is_lockup,
++};
++
++static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
++	.get_rptr = gfx_v7_0_ring_get_rptr_compute,
++	.get_wptr = gfx_v7_0_ring_get_wptr_compute,
++	.set_wptr = gfx_v7_0_ring_set_wptr_compute,
++	.parse_cs = NULL,
++	.emit_ib = gfx_v7_0_ring_emit_ib,
++	.emit_fence = gfx_v7_0_ring_emit_fence_compute,
++	.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
++	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
++	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
++	.test_ring = gfx_v7_0_ring_test_ring,
++	.test_ib = gfx_v7_0_ring_test_ib,
++	.is_lockup = gfx_v7_0_ring_is_lockup,
++};
++
++static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++		adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
++	for (i = 0; i < adev->gfx.num_compute_rings; i++)
++		adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
++}
++
++static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
++	.set = gfx_v7_0_set_eop_interrupt_state,
++	.process = gfx_v7_0_eop_irq,
++};
++
++static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
++	.set = gfx_v7_0_set_priv_reg_fault_state,
++	.process = gfx_v7_0_priv_reg_irq,
++};
++
++static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
++	.set = gfx_v7_0_set_priv_inst_fault_state,
++	.process = gfx_v7_0_priv_inst_irq,
++};
++
++static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
++	adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
++
++	adev->gfx.priv_reg_irq.num_types = 1;
++	adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
++
++	adev->gfx.priv_inst_irq.num_types = 1;
++	adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
++}
++
++static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
++{
++	/* init asci gds info */
++	adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
++	adev->gds.gws.total_size = 64;
++	adev->gds.oa.total_size = 16;
++
++	if (adev->gds.mem.total_size == 64 * 1024) {
++		adev->gds.mem.gfx_partition_size = 4096;
++		adev->gds.mem.cs_partition_size = 4096;
++
++		adev->gds.gws.gfx_partition_size = 4;
++		adev->gds.gws.cs_partition_size = 4;
++
++		adev->gds.oa.gfx_partition_size = 4;
++		adev->gds.oa.cs_partition_size = 1;
++	} else {
++		adev->gds.mem.gfx_partition_size = 1024;
++		adev->gds.mem.cs_partition_size = 1024;
++
++		adev->gds.gws.gfx_partition_size = 16;
++		adev->gds.gws.cs_partition_size = 16;
++
++		adev->gds.oa.gfx_partition_size = 4;
++		adev->gds.oa.cs_partition_size = 4;
++	}
++}
++
++
++int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
++								   struct amdgpu_cu_info *cu_info)
++{
++	int i, j, k, counter, active_cu_number = 0;
++	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
++
++	if (!adev || !cu_info)
++		return -EINVAL;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
++		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
++			mask = 1;
++			ao_bitmap = 0;
++			counter = 0;
++			bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j);
++			cu_info->bitmap[i][j] = bitmap;
++
++			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
++				if (bitmap & mask) {
++					if (counter < 2)
++						ao_bitmap |= mask;
++					counter ++;
++				}
++				mask <<= 1;
++			}
++			active_cu_number += counter;
++			ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
++		}
++	}
++
++	cu_info->number = active_cu_number;
++	cu_info->ao_cu_mask = ao_cu_mask;
++	mutex_unlock(&adev->grbm_idx_mutex);
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+new file mode 100644
+index 0000000..668b91a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __GFX_V7_0_H__
++#define __GFX_V7_0_H__
++
++extern const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs;
++
++/* XXX these shouldn't be exported */
++void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev);
++void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev);
++void gfx_v7_0_rlc_stop(struct amdgpu_device *adev);
++uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev);
++void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
++int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+new file mode 100644
+index 0000000..b9b1df6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -0,0 +1,1307 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "cikd.h"
++#include "cik.h"
++#include "gmc_v7_0.h"
++#include "amdgpu_ucode.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
++static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
++
++MODULE_FIRMWARE("radeon/boniare_mc.bin");
++MODULE_FIRMWARE("radeon/hawaii_mc.bin");
++
++/**
++ * gmc8_mc_wait_for_idle - wait for MC idle callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Wait for the MC (memory controller) to be idle.
++ * (evergreen+).
++ * Returns 0 if the MC is idle, -1 if not.
++ */
++int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS) & 0x1F00;
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -1;
++}
++
++void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
++		      struct amdgpu_mode_mc_save *save)
++{
++	u32 blackout;
++
++	if (adev->mode_info.num_crtc)
++		amdgpu_display_stop_mc_access(adev, save);
++
++	amdgpu_asic_wait_for_mc_idle(adev);
++
++	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
++	if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
++		/* Block CPU access */
++		WREG32(mmBIF_FB_EN, 0);
++		/* blackout the MC */
++		blackout = REG_SET_FIELD(blackout,
++					 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
++		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
++	}
++	/* wait for the MC to settle */
++	udelay(100);
++}
++
++void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
++			struct amdgpu_mode_mc_save *save)
++{
++	u32 tmp;
++
++	/* unblackout the MC */
++	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
++	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
++	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
++	/* allow CPU access */
++	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
++	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
++	WREG32(mmBIF_FB_EN, tmp);
++
++	if (adev->mode_info.num_crtc)
++		amdgpu_display_resume_mc_access(adev, save);
++}
++
++/**
++ * gmc_v7_0_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++		chip_name = "bonaire";
++		break;
++	case CHIP_HAWAII:
++		chip_name = "hawaii";
++		break;
++	case CHIP_KAVERI:
++	case CHIP_KABINI:
++		return 0;
++	default: BUG();
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
++	err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->mc.fw);
++
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "cik_mc: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		release_firmware(adev->mc.fw);
++		adev->mc.fw = NULL;
++	}
++	return err;
++}
++
++/**
++ * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Load the GDDR MC ucode into the hw (CIK).
++ * Returns 0 on success, error on failure.
++ */
++static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
++{
++	const struct mc_firmware_header_v1_0 *hdr;
++	const __le32 *fw_data = NULL;
++	const __le32 *io_mc_regs = NULL;
++	u32 running, blackout = 0;
++	int i, ucode_size, regs_size;
++
++	if (!adev->mc.fw)
++		return -EINVAL;
++
++	hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
++	amdgpu_ucode_print_mc_hdr(&hdr->header);
++
++	adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
++	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
++	io_mc_regs = (const __le32 *)
++		(adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
++	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++	fw_data = (const __le32 *)
++		(adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++
++	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
++
++	if (running == 0) {
++		if (running) {
++			blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
++			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
++		}
++
++		/* reset the engine and set to writable */
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
++
++		/* load mc io regs */
++		for (i = 0; i < regs_size; i++) {
++			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
++			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
++		}
++		/* load the MC ucode */
++		for (i = 0; i < ucode_size; i++)
++			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
++
++		/* put the engine back into the active state */
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
++
++		/* wait for training to complete */
++		for (i = 0; i < adev->usec_timeout; i++) {
++			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
++					  MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
++				break;
++			udelay(1);
++		}
++		for (i = 0; i < adev->usec_timeout; i++) {
++			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
++					  MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
++				break;
++			udelay(1);
++		}
++
++		if (running)
++			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
++	}
++
++	return 0;
++}
++
++static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
++				       struct amdgpu_mc *mc)
++{
++	if (mc->mc_vram_size > 0xFFC0000000ULL) {
++		/* leave room for at least 1024M GTT */
++		dev_warn(adev->dev, "limiting VRAM\n");
++		mc->real_vram_size = 0xFFC0000000ULL;
++		mc->mc_vram_size = 0xFFC0000000ULL;
++	}
++	amdgpu_vram_location(adev, &adev->mc, 0);
++	adev->mc.gtt_base_align = 0;
++	amdgpu_gtt_location(adev, mc);
++}
++
++/**
++ * gmc_v7_0_mc_program - program the GPU memory controller
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set the location of vram, gart, and AGP in the GPU's
++ * physical address space (CIK).
++ */
++static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 tmp;
++	int i, j;
++
++	/* Initialize HDP */
++	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
++		WREG32((0xb05 + j), 0x00000000);
++		WREG32((0xb06 + j), 0x00000000);
++		WREG32((0xb07 + j), 0x00000000);
++		WREG32((0xb08 + j), 0x00000000);
++		WREG32((0xb09 + j), 0x00000000);
++	}
++	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
++
++	if (adev->mode_info.num_crtc)
++		amdgpu_display_set_vga_render_state(adev, false);
++
++	gmc_v7_0_mc_stop(adev, &save);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
++	}
++	/* Update configuration */
++	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
++	       adev->mc.vram_start >> 12);
++	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
++	       adev->mc.vram_end >> 12);
++	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
++	       adev->vram_scratch.gpu_addr >> 12);
++	tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
++	tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
++	WREG32(mmMC_VM_FB_LOCATION, tmp);
++	/* XXX double check these! */
++	WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
++	WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
++	WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
++	WREG32(mmMC_VM_AGP_BASE, 0);
++	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
++	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
++	}
++	gmc_v7_0_mc_resume(adev, &save);
++
++	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
++
++	tmp = RREG32(mmHDP_MISC_CNTL);
++	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
++	WREG32(mmHDP_MISC_CNTL, tmp);
++
++	tmp = RREG32(mmHDP_HOST_PATH_CNTL);
++	WREG32(mmHDP_HOST_PATH_CNTL, tmp);
++}
++
++/**
++ * gmc_v7_0_mc_init - initialize the memory controller driver params
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up the amount of vram, vram width, and decide how to place
++ * vram and gart within the GPU's physical address space (CIK).
++ * Returns 0 for success.
++ */
++static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
++{
++	u32 tmp;
++	int chansize, numchan;
++
++	/* Get VRAM informations */
++	tmp = RREG32(mmMC_ARB_RAMCFG);
++	if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
++		chansize = 64;
++	} else {
++		chansize = 32;
++	}
++	tmp = RREG32(mmMC_SHARED_CHMAP);
++	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
++	case 0:
++	default:
++		numchan = 1;
++		break;
++	case 1:
++		numchan = 2;
++		break;
++	case 2:
++		numchan = 4;
++		break;
++	case 3:
++		numchan = 8;
++		break;
++	case 4:
++		numchan = 3;
++		break;
++	case 5:
++		numchan = 6;
++		break;
++	case 6:
++		numchan = 10;
++		break;
++	case 7:
++		numchan = 12;
++		break;
++	case 8:
++		numchan = 16;
++		break;
++	}
++	adev->mc.vram_width = numchan * chansize;
++	/* Could aper size report 0 ? */
++	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
++	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
++	/* size in MB on si */
++	adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
++	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
++	adev->mc.visible_vram_size = adev->mc.aper_size;
++
++	/* unless the user had overridden it, set the gart
++	 * size equal to the 1024 or vram, whichever is larger.
++	 */
++	if (amdgpu_gart_size == -1)
++		adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
++	else
++		adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
++
++	gmc_v7_0_vram_gtt_location(adev, &adev->mc);
++
++	return 0;
++}
++
++/*
++ * GART
++ * VMID 0 is the physical GPU addresses as used by the kernel.
++ * VMIDs 1-15 are used for userspace clients and are handled
++ * by the amdgpu vm/hsa code.
++ */
++
++/**
++ * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
++ *
++ * @adev: amdgpu_device pointer
++ * @vmid: vm instance to flush
++ *
++ * Flush the TLB for the requested page table (CIK).
++ */
++static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
++					uint32_t vmid)
++{
++	/* flush hdp cache */
++	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++
++	/* bits 0-15 are the VM contexts0-15 */
++	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
++}
++
++/**
++ * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
++ *
++ * @adev: amdgpu_device pointer
++ * @cpu_pt_addr: cpu address of the page table
++ * @gpu_page_idx: entry in the page table to update
++ * @addr: dst addr to write into pte/pde
++ * @flags: access flags
++ *
++ * Update the page tables using the CPU.
++ */
++static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
++				     void *cpu_pt_addr,
++				     uint32_t gpu_page_idx,
++				     uint64_t addr,
++				     uint32_t flags)
++{
++	void __iomem *ptr = (void *)cpu_pt_addr;
++	uint64_t value;
++
++	value = addr & 0xFFFFFFFFFFFFF000ULL;
++	value |= flags;
++	writeq(value, ptr + (gpu_page_idx * 8));
++
++	return 0;
++}
++
++/**
++ * gmc_v7_0_gart_enable - gart enable
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * This sets up the TLBs, programs the page tables for VMID0,
++ * sets up the hw for VMIDs 1-15 which are allocated on
++ * demand, and sets up the global locations for the LDS, GDS,
++ * and GPUVM for FSA64 clients (CIK).
++ * Returns 0 for success, errors for failure.
++ */
++static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
++{
++	int r, i;
++	u32 tmp;
++
++	if (adev->gart.robj == NULL) {
++		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
++		return -EINVAL;
++	}
++	r = amdgpu_gart_table_vram_pin(adev);
++	if (r)
++		return r;
++	/* Setup TLB control */
++	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
++	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
++	/* Setup L2 cache */
++	tmp = RREG32(mmVM_L2_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
++	WREG32(mmVM_L2_CNTL, tmp);
++	tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
++	WREG32(mmVM_L2_CNTL2, tmp);
++	tmp = RREG32(mmVM_L2_CNTL3);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
++	WREG32(mmVM_L2_CNTL3, tmp);
++	/* setup context0 */
++	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
++	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
++	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
++	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
++			(u32)(adev->dummy_page.addr >> 12));
++	WREG32(mmVM_CONTEXT0_CNTL2, 0);
++	tmp = RREG32(mmVM_CONTEXT0_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	WREG32(mmVM_CONTEXT0_CNTL, tmp);
++
++	WREG32(0x575, 0);
++	WREG32(0x576, 0);
++	WREG32(0x577, 0);
++
++	/* empty context1-15 */
++	/* FIXME start with 4G, once using 2 level pt switch to full
++	 * vm size space
++	 */
++	/* set vm size, must be a multiple of 4 */
++	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
++	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn);
++	for (i = 1; i < 16; i++) {
++		if (i < 8)
++			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
++			       adev->gart.table_addr >> 12);
++		else
++			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
++			       adev->gart.table_addr >> 12);
++	}
++
++	/* enable context1-15 */
++	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
++	       (u32)(adev->dummy_page.addr >> 12));
++	WREG32(mmVM_CONTEXT1_CNTL2, 4);
++	tmp = RREG32(mmVM_CONTEXT1_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
++			    amdgpu_vm_block_size - 9);
++	WREG32(mmVM_CONTEXT1_CNTL, tmp);
++
++	if (adev->asic_type == CHIP_KAVERI) {
++		tmp = RREG32(mmCHUB_CONTROL);
++		tmp &= ~BYPASS_VM;
++		WREG32(mmCHUB_CONTROL, tmp);
++	}
++
++	gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
++	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
++		 (unsigned)(adev->mc.gtt_size >> 20),
++		 (unsigned long long)adev->gart.table_addr);
++	adev->gart.ready = true;
++	return 0;
++}
++
++static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->gart.robj) {
++		WARN(1, "R600 PCIE GART already initialized\n");
++		return 0;
++	}
++	/* Initialize common gart structure */
++	r = amdgpu_gart_init(adev);
++	if (r)
++		return r;
++	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
++	return amdgpu_gart_table_vram_alloc(adev);
++}
++
++/**
++ * gmc_v7_0_gart_disable - gart disable
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * This disables all VM page table (CIK).
++ */
++static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	/* Disable all tables */
++	WREG32(mmVM_CONTEXT0_CNTL, 0);
++	WREG32(mmVM_CONTEXT1_CNTL, 0);
++	/* Setup TLB control */
++	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
++	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
++	/* Setup L2 cache */
++	tmp = RREG32(mmVM_L2_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
++	WREG32(mmVM_L2_CNTL, tmp);
++	WREG32(mmVM_L2_CNTL2, 0);
++	amdgpu_gart_table_vram_unpin(adev);
++}
++
++/**
++ * gmc_v7_0_gart_fini - vm fini callback
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tears down the driver GART/VM setup (CIK).
++ */
++static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
++{
++	amdgpu_gart_table_vram_free(adev);
++	amdgpu_gart_fini(adev);
++}
++
++/*
++ * vm
++ * VMID 0 is the physical GPU addresses as used by the kernel.
++ * VMIDs 1-15 are used for userspace clients and are handled
++ * by the amdgpu vm/hsa code.
++ */
++/**
++ * gmc_v7_0_vm_init - cik vm init callback
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Inits cik specific vm parameters (number of VMs, base of vram for
++ * VMIDs 1-15) (CIK).
++ * Returns 0 for success.
++ */
++static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
++{
++	/*
++	 * number of VMs
++	 * VMID 0 is reserved for System
++	 * amdgpu graphics/compute will use VMIDs 1-7
++	 * amdkfd will use VMIDs 8-15
++	 */
++	adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
++
++	/* base offset of vram pages */
++	if (adev->flags & AMDGPU_IS_APU) {
++		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
++		tmp <<= 22;
++		adev->vm_manager.vram_base_offset = tmp;
++	} else
++		adev->vm_manager.vram_base_offset = 0;
++
++	return 0;
++}
++
++/**
++ * gmc_v7_0_vm_fini - cik vm fini callback
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down any asic specific VM setup (CIK).
++ */
++static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
++{
++}
++
++/**
++ * gmc_v7_0_vm_decode_fault - print human readable fault info
++ *
++ * @adev: amdgpu_device pointer
++ * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
++ * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
++ *
++ * Print human readable fault information (CIK).
++ */
++static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
++				     u32 status, u32 addr, u32 mc_client)
++{
++	u32 mc_id;
++	u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
++	u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
++					PROTECTIONS);
++	char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
++		(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
++
++	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
++			      MEMORY_CLIENT_ID);
++
++	printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
++	       protections, vmid, addr,
++	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
++			     MEMORY_CLIENT_RW) ?
++	       "write" : "read", block, mc_client, mc_id);
++}
++
++
++static const u32 mc_cg_registers[] = {
++	mmMC_HUB_MISC_HUB_CG,
++	mmMC_HUB_MISC_SIP_CG,
++	mmMC_HUB_MISC_VM_CG,
++	mmMC_XPB_CLK_GAT,
++	mmATC_MISC_CG,
++	mmMC_CITF_MISC_WR_CG,
++	mmMC_CITF_MISC_RD_CG,
++	mmMC_CITF_MISC_VM_CG,
++	mmVM_L2_CG,
++};
++
++static const u32 mc_cg_ls_en[] = {
++	MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
++	MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
++	MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
++	MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
++	ATC_MISC_CG__MEM_LS_ENABLE_MASK,
++	MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
++	MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
++	MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
++	VM_L2_CG__MEM_LS_ENABLE_MASK,
++};
++
++static const u32 mc_cg_en[] = {
++	MC_HUB_MISC_HUB_CG__ENABLE_MASK,
++	MC_HUB_MISC_SIP_CG__ENABLE_MASK,
++	MC_HUB_MISC_VM_CG__ENABLE_MASK,
++	MC_XPB_CLK_GAT__ENABLE_MASK,
++	ATC_MISC_CG__ENABLE_MASK,
++	MC_CITF_MISC_WR_CG__ENABLE_MASK,
++	MC_CITF_MISC_RD_CG__ENABLE_MASK,
++	MC_CITF_MISC_VM_CG__ENABLE_MASK,
++	VM_L2_CG__ENABLE_MASK,
++};
++
++static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
++				  bool enable)
++{
++	int i;
++	u32 orig, data;
++
++	for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
++		orig = data = RREG32(mc_cg_registers[i]);
++		if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
++			data |= mc_cg_ls_en[i];
++		else
++			data &= ~mc_cg_ls_en[i];
++		if (data != orig)
++			WREG32(mc_cg_registers[i], data);
++	}
++}
++
++static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
++				    bool enable)
++{
++	int i;
++	u32 orig, data;
++
++	for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
++		orig = data = RREG32(mc_cg_registers[i]);
++		if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
++			data |= mc_cg_en[i];
++		else
++			data &= ~mc_cg_en[i];
++		if (data != orig)
++			WREG32(mc_cg_registers[i], data);
++	}
++}
++
++static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
++				     bool enable)
++{
++	u32 orig, data;
++
++	orig = data = RREG32_PCIE(ixPCIE_CNTL2);
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
++		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
++		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
++		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
++		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
++	} else {
++		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
++		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
++		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
++		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
++	}
++
++	if (orig != data)
++		WREG32_PCIE(ixPCIE_CNTL2, data);
++}
++
++static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
++				     bool enable)
++{
++	u32 orig, data;
++
++	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
++		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
++	else
++		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
++
++	if (orig != data)
++		WREG32(mmHDP_HOST_PATH_CNTL, data);
++}
++
++static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
++				   bool enable)
++{
++	u32 orig, data;
++
++	orig = data = RREG32(mmHDP_MEM_POWER_LS);
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
++		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
++	else
++		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
++
++	if (orig != data)
++		WREG32(mmHDP_MEM_POWER_LS, data);
++}
++
++static int gmc_v7_0_early_init(struct amdgpu_device *adev)
++{
++	gmc_v7_0_set_gart_funcs(adev);
++	gmc_v7_0_set_irq_funcs(adev);
++
++	if (adev->flags & AMDGPU_IS_APU) {
++		adev->mc.is_gddr5 = false;
++	} else {
++		u32 tmp = RREG32(mmMC_SEQ_MISC0);
++
++		if (((tmp & MC_SEQ_MISC0__GDDR5_MASK) >>
++		     MC_SEQ_MISC0__GDDR5__SHIFT) == MC_SEQ_MISC0__GDDR5_VALUE)
++			adev->mc.is_gddr5 = true;
++		else
++			adev->mc.is_gddr5 = false;
++	}
++
++	return 0;
++}
++
++static int gmc_v7_0_sw_init(struct amdgpu_device *adev)
++{
++	int r;
++	int dma_bits;
++
++	r = amdgpu_gem_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
++	if (r)
++		return r;
++
++	/* Adjust VM size here.
++	 * Currently set to 4GB ((1 << 20) 4k pages).
++	 * Max GPUVM size for cayman and SI is 40 bits.
++	 */
++	adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
++
++	/* Set the internal MC address mask
++	 * This is the max address of the GPU's
++	 * internal address space.
++	 */
++	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
++
++	/* set DMA mask + need_dma32 flags.
++	 * PCIE - can handle 40-bits.
++	 * IGP - can handle 40-bits
++	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
++	 */
++	adev->need_dma32 = false;
++	dma_bits = adev->need_dma32 ? 32 : 40;
++	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
++	if (r) {
++		adev->need_dma32 = true;
++		dma_bits = 32;
++		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
++	}
++	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
++	if (r) {
++		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
++		printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
++	}
++
++	r = gmc_v7_0_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load mc firmware!\n");
++		return r;
++	}
++
++	r = gmc_v7_0_mc_init(adev);
++	if (r)
++		return r;
++
++	/* Memory manager */
++	r = amdgpu_bo_init(adev);
++	if (r)
++		return r;
++
++	r = gmc_v7_0_gart_init(adev);
++	if (r)
++		return r;
++
++	if (!adev->vm_manager.enabled) {
++		r = gmc_v7_0_vm_init(adev);
++		if (r) {
++			dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
++			return r;
++		}
++		adev->vm_manager.enabled = true;
++	}
++
++	return r;
++}
++
++static int gmc_v7_0_sw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (adev->vm_manager.enabled) {
++		for (i = 0; i < AMDGPU_NUM_VM; ++i)
++			amdgpu_fence_unref(&adev->vm_manager.active[i]);
++		gmc_v7_0_vm_fini(adev);
++		adev->vm_manager.enabled = false;
++	}
++	gmc_v7_0_gart_fini(adev);
++	amdgpu_gem_fini(adev);
++	amdgpu_bo_fini(adev);
++
++	return 0;
++}
++
++static int gmc_v7_0_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	gmc_v7_0_mc_program(adev);
++
++	if (!(adev->flags & AMDGPU_IS_APU)) {
++		r = gmc_v7_0_mc_load_microcode(adev);
++		if (r) {
++			DRM_ERROR("Failed to load MC firmware!\n");
++			return r;
++		}
++	}
++
++	r = gmc_v7_0_gart_enable(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int gmc_v7_0_hw_fini(struct amdgpu_device *adev)
++{
++	gmc_v7_0_gart_disable(adev);
++
++	return 0;
++}
++
++static int gmc_v7_0_suspend(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (adev->vm_manager.enabled) {
++		for (i = 0; i < AMDGPU_NUM_VM; ++i)
++			amdgpu_fence_unref(&adev->vm_manager.active[i]);
++		gmc_v7_0_vm_fini(adev);
++		adev->vm_manager.enabled = false;
++	}
++	gmc_v7_0_hw_fini(adev);
++
++	return 0;
++}
++
++static int gmc_v7_0_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = gmc_v7_0_hw_init(adev);
++	if (r)
++		return r;
++
++	if (!adev->vm_manager.enabled) {
++		r = gmc_v7_0_vm_init(adev);
++		if (r) {
++			dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
++			return r;
++		}
++		adev->vm_manager.enabled = true;
++	}
++
++	return r;
++}
++
++static bool gmc_v7_0_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
++		return false;
++
++	return true;
++}
++
++static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
++					       SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++					       SRBM_STATUS__MCC_BUSY_MASK |
++					       SRBM_STATUS__MCD_BUSY_MASK |
++					       SRBM_STATUS__VMC_BUSY_MASK);
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++
++}
++
++static void gmc_v7_0_print_status(struct amdgpu_device *adev)
++{
++	int i, j;
++
++	dev_info(adev->dev, "GMC 8.x registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
++	dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
++		 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
++	dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL));
++	dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL2));
++	dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL3));
++	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_CNTL2));
++	dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_CNTL));
++	dev_info(adev->dev, "  0x15D4=0x%08X\n",
++		 RREG32(0x575));
++	dev_info(adev->dev, "  0x15D8=0x%08X\n",
++		 RREG32(0x576));
++	dev_info(adev->dev, "  0x15DC=0x%08X\n",
++		 RREG32(0x577));
++	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_CNTL2));
++	dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_CNTL));
++	for (i = 0; i < 16; i++) {
++		if (i < 8)
++			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
++				 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
++		else
++			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
++				 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
++	}
++	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
++		 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
++	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
++		 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
++	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
++		 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
++	dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
++		 RREG32(mmMC_VM_FB_LOCATION));
++	dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
++		 RREG32(mmMC_VM_AGP_BASE));
++	dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
++		 RREG32(mmMC_VM_AGP_TOP));
++	dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
++		 RREG32(mmMC_VM_AGP_BOT));
++
++	if (adev->asic_type == CHIP_KAVERI) {
++		dev_info(adev->dev, "  CHUB_CONTROL=0x%08X\n",
++			 RREG32(mmCHUB_CONTROL));
++	}
++
++	dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
++		 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
++	dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
++		 RREG32(mmHDP_NONSURFACE_BASE));
++	dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
++		 RREG32(mmHDP_NONSURFACE_INFO));
++	dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
++		 RREG32(mmHDP_NONSURFACE_SIZE));
++	dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
++		 RREG32(mmHDP_MISC_CNTL));
++	dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
++		 RREG32(mmHDP_HOST_PATH_CNTL));
++
++	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
++		dev_info(adev->dev, "  %d:\n", i);
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb05 + j, RREG32(0xb05 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb06 + j, RREG32(0xb06 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb07 + j, RREG32(0xb07 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb08 + j, RREG32(0xb08 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb09 + j, RREG32(0xb09 + j));
++	}
++
++	dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
++		 RREG32(mmBIF_FB_EN));
++}
++
++static int gmc_v7_0_soft_reset(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
++						SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
++
++	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
++		if (!(adev->flags & AMDGPU_IS_APU))
++			srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
++							SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
++	}
++
++	if (srbm_soft_reset) {
++		gmc_v7_0_print_status(adev);
++
++		gmc_v7_0_mc_stop(adev, &save);
++		if (gmc_v7_0_wait_for_idle(adev)) {
++			dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
++		}
++
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		gmc_v7_0_mc_resume(adev, &save);
++		udelay(50);
++
++		gmc_v7_0_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
++					     struct amdgpu_irq_src *src,
++					     unsigned type,
++					     enum amdgpu_interrupt_state state)
++{
++	u32 tmp;
++	u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		/* system context */
++		tmp = RREG32(mmVM_CONTEXT0_CNTL);
++		tmp &= ~bits;
++		WREG32(mmVM_CONTEXT0_CNTL, tmp);
++		/* VMs */
++		tmp = RREG32(mmVM_CONTEXT1_CNTL);
++		tmp &= ~bits;
++		WREG32(mmVM_CONTEXT1_CNTL, tmp);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		/* system context */
++		tmp = RREG32(mmVM_CONTEXT0_CNTL);
++		tmp |= bits;
++		WREG32(mmVM_CONTEXT0_CNTL, tmp);
++		/* VMs */
++		tmp = RREG32(mmVM_CONTEXT1_CNTL);
++		tmp |= bits;
++		WREG32(mmVM_CONTEXT1_CNTL, tmp);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	u32 addr, status, mc_client;
++
++	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
++	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
++	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
++	dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
++		entry->src_id, entry->src_data);
++	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
++		addr);
++	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++		status);
++	gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
++	/* reset addr and status */
++	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
++
++	return 0;
++}
++
++static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	bool gate = false;
++
++	if (state == AMDGPU_CG_STATE_GATE)
++		gate = true;
++
++	if (!(adev->flags & AMDGPU_IS_APU)) {
++		gmc_v7_0_enable_mc_mgcg(adev, gate);
++		gmc_v7_0_enable_mc_ls(adev, gate);
++	}
++	gmc_v7_0_enable_bif_mgls(adev, gate);
++	gmc_v7_0_enable_hdp_mgcg(adev, gate);
++	gmc_v7_0_enable_hdp_ls(adev, gate);
++
++	return 0;
++}
++
++static int gmc_v7_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs = {
++	.early_init = gmc_v7_0_early_init,
++	.late_init = NULL,
++	.sw_init = gmc_v7_0_sw_init,
++	.sw_fini = gmc_v7_0_sw_fini,
++	.hw_init = gmc_v7_0_hw_init,
++	.hw_fini = gmc_v7_0_hw_fini,
++	.suspend = gmc_v7_0_suspend,
++	.resume = gmc_v7_0_resume,
++	.is_idle = gmc_v7_0_is_idle,
++	.wait_for_idle = gmc_v7_0_wait_for_idle,
++	.soft_reset = gmc_v7_0_soft_reset,
++	.print_status = gmc_v7_0_print_status,
++	.set_clockgating_state = gmc_v7_0_set_clockgating_state,
++	.set_powergating_state = gmc_v7_0_set_powergating_state,
++};
++
++static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
++	.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
++	.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
++};
++
++static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
++	.set = gmc_v7_0_vm_fault_interrupt_state,
++	.process = gmc_v7_0_process_interrupt,
++};
++
++static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
++{
++	if (adev->gart.gart_funcs == NULL)
++		adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
++}
++
++static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->mc.vm_fault.num_types = 1;
++	adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
+new file mode 100644
+index 0000000..ab1a2fa
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
+@@ -0,0 +1,36 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __GMC_V7_0_H__
++#define __GMC_V7_0_H__
++
++extern const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs;
++
++/* XXX these shouldn't be exported */
++void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
++		      struct amdgpu_mode_mc_save *save);
++void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
++			struct amdgpu_mode_mc_save *save);
++int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+new file mode 100644
+index 0000000..cd90241
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+@@ -0,0 +1,3336 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "cikd.h"
++#include "atom.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_dpm.h"
++#include "kv_dpm.h"
++#include "gfx_v7_0.h"
++#include <linux/seq_file.h>
++
++#include "smu/smu_7_0_0_d.h"
++#include "smu/smu_7_0_0_sh_mask.h"
++
++#include "gca/gfx_7_2_d.h"
++#include "gca/gfx_7_2_sh_mask.h"
++
++#define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
++#define KV_MINIMUM_ENGINE_CLOCK         800
++#define SMC_RAM_END                     0x40000
++
++static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
++static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
++static int kv_enable_nb_dpm(struct amdgpu_device *adev,
++			    bool enable);
++static void kv_init_graphics_levels(struct amdgpu_device *adev);
++static int kv_calculate_ds_divider(struct amdgpu_device *adev);
++static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
++static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
++static void kv_enable_new_levels(struct amdgpu_device *adev);
++static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
++					   struct amdgpu_ps *new_rps);
++static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
++static int kv_set_enabled_levels(struct amdgpu_device *adev);
++static int kv_force_dpm_highest(struct amdgpu_device *adev);
++static int kv_force_dpm_lowest(struct amdgpu_device *adev);
++static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
++					struct amdgpu_ps *new_rps,
++					struct amdgpu_ps *old_rps);
++static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
++					    int min_temp, int max_temp);
++static int kv_init_fps_limits(struct amdgpu_device *adev);
++
++static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
++static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
++static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
++static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
++
++
++static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
++				   struct sumo_vid_mapping_table *vid_mapping_table,
++				   u32 vid_2bit)
++{
++	struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	u32 i;
++
++	if (vddc_sclk_table && vddc_sclk_table->count) {
++		if (vid_2bit < vddc_sclk_table->count)
++			return vddc_sclk_table->entries[vid_2bit].v;
++		else
++			return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
++	} else {
++		for (i = 0; i < vid_mapping_table->num_entries; i++) {
++			if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
++				return vid_mapping_table->entries[i].vid_7bit;
++		}
++		return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
++	}
++}
++
++static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
++				   struct sumo_vid_mapping_table *vid_mapping_table,
++				   u32 vid_7bit)
++{
++	struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	u32 i;
++
++	if (vddc_sclk_table && vddc_sclk_table->count) {
++		for (i = 0; i < vddc_sclk_table->count; i++) {
++			if (vddc_sclk_table->entries[i].v == vid_7bit)
++				return i;
++		}
++		return vddc_sclk_table->count - 1;
++	} else {
++		for (i = 0; i < vid_mapping_table->num_entries; i++) {
++			if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
++				return vid_mapping_table->entries[i].vid_2bit;
++		}
++
++		return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
++	}
++}
++
++static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
++{
++/* This bit selects who handles display phy powergating.
++ * Clear the bit to let atom handle it.
++ * Set it to let the driver handle it.
++ * For now we just let atom handle it.
++ */
++#if 0
++	u32 v = RREG32(mmDOUT_SCRATCH3);
++
++	if (enable)
++		v |= 0x4;
++	else
++		v &= 0xFFFFFFFB;
++
++	WREG32(mmDOUT_SCRATCH3, v);
++#endif
++}
++
++static u32 sumo_get_sleep_divider_from_id(u32 id)
++{
++	return 1 << id;
++}
++
++static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
++						      struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
++						      ATOM_AVAILABLE_SCLK_LIST *table)
++{
++	u32 i;
++	u32 n = 0;
++	u32 prev_sclk = 0;
++
++	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
++		if (table[i].ulSupportedSCLK > prev_sclk) {
++			sclk_voltage_mapping_table->entries[n].sclk_frequency =
++				table[i].ulSupportedSCLK;
++			sclk_voltage_mapping_table->entries[n].vid_2bit =
++				table[i].usVoltageIndex;
++			prev_sclk = table[i].ulSupportedSCLK;
++			n++;
++		}
++	}
++
++	sclk_voltage_mapping_table->num_max_dpm_entries = n;
++}
++
++static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
++					     struct sumo_vid_mapping_table *vid_mapping_table,
++					     ATOM_AVAILABLE_SCLK_LIST *table)
++{
++	u32 i, j;
++
++	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
++		if (table[i].ulSupportedSCLK != 0) {
++			vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
++				table[i].usVoltageID;
++			vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
++				table[i].usVoltageIndex;
++		}
++	}
++
++	for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
++		if (vid_mapping_table->entries[i].vid_7bit == 0) {
++			for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
++				if (vid_mapping_table->entries[j].vid_7bit != 0) {
++					vid_mapping_table->entries[i] =
++						vid_mapping_table->entries[j];
++					vid_mapping_table->entries[j].vid_7bit = 0;
++					break;
++				}
++			}
++
++			if (j == SUMO_MAX_NUMBER_VOLTAGES)
++				break;
++		}
++	}
++
++	vid_mapping_table->num_entries = i;
++}
++
++static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
++{
++	{  0,       4,        1    },
++	{  1,       4,        1    },
++	{  2,       5,        1    },
++	{  3,       4,        2    },
++	{  4,       1,        1    },
++	{  5,       5,        2    },
++	{  6,       6,        1    },
++	{  7,       9,        2    },
++	{ 0xffffffff }
++};
++
++static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
++{
++	{  0,       4,        1    },
++	{ 0xffffffff }
++};
++
++static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
++{
++	{  0,       4,        1    },
++	{ 0xffffffff }
++};
++
++static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
++{
++	{  0,       4,        1    },
++	{ 0xffffffff }
++};
++
++static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
++{
++	{  0,       4,        1    },
++	{ 0xffffffff }
++};
++
++static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
++{
++	{  0,       4,        1    },
++	{  1,       4,        1    },
++	{  2,       5,        1    },
++	{  3,       4,        1    },
++	{  4,       1,        1    },
++	{  5,       5,        1    },
++	{  6,       6,        1    },
++	{  7,       9,        1    },
++	{  8,       4,        1    },
++	{  9,       2,        1    },
++	{  10,      3,        1    },
++	{  11,      6,        1    },
++	{  12,      8,        2    },
++	{  13,      1,        1    },
++	{  14,      2,        1    },
++	{  15,      3,        1    },
++	{  16,      1,        1    },
++	{  17,      4,        1    },
++	{  18,      3,        1    },
++	{  19,      1,        1    },
++	{  20,      8,        1    },
++	{  21,      5,        1    },
++	{  22,      1,        1    },
++	{  23,      1,        1    },
++	{  24,      4,        1    },
++	{  27,      6,        1    },
++	{  28,      1,        1    },
++	{ 0xffffffff }
++};
++
++static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
++{
++	{ 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
++};
++
++static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
++{
++	{ 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
++};
++
++static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
++{
++	{ 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
++};
++
++static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
++{
++	{ 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
++};
++
++static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
++{
++	{ 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
++};
++
++static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
++{
++	{ 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
++};
++
++static const struct kv_pt_config_reg didt_config_kv[] =
++{
++	{ 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
++	{ 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
++	{ 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
++	{ 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
++	{ 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
++	{ 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
++	{ 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
++	{ 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
++	{ 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
++	{ 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
++	{ 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
++	{ 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
++	{ 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
++	{ 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
++	{ 0xFFFFFFFF }
++};
++
++static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
++{
++	struct kv_ps *ps = rps->ps_priv;
++
++	return ps;
++}
++
++static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = adev->pm.dpm.priv;
++
++	return pi;
++}
++
++#if 0
++static void kv_program_local_cac_table(struct amdgpu_device *adev,
++				       const struct kv_lcac_config_values *local_cac_table,
++				       const struct kv_lcac_config_reg *local_cac_reg)
++{
++	u32 i, count, data;
++	const struct kv_lcac_config_values *values = local_cac_table;
++
++	while (values->block_id != 0xffffffff) {
++		count = values->signal_id;
++		for (i = 0; i < count; i++) {
++			data = ((values->block_id << local_cac_reg->block_shift) &
++				local_cac_reg->block_mask);
++			data |= ((i << local_cac_reg->signal_shift) &
++				 local_cac_reg->signal_mask);
++			data |= ((values->t << local_cac_reg->t_shift) &
++				 local_cac_reg->t_mask);
++			data |= ((1 << local_cac_reg->enable_shift) &
++				 local_cac_reg->enable_mask);
++			WREG32_SMC(local_cac_reg->cntl, data);
++		}
++		values++;
++	}
++}
++#endif
++
++static int kv_program_pt_config_registers(struct amdgpu_device *adev,
++					  const struct kv_pt_config_reg *cac_config_regs)
++{
++	const struct kv_pt_config_reg *config_regs = cac_config_regs;
++	u32 data;
++	u32 cache = 0;
++
++	if (config_regs == NULL)
++		return -EINVAL;
++
++	while (config_regs->offset != 0xFFFFFFFF) {
++		if (config_regs->type == KV_CONFIGREG_CACHE) {
++			cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
++		} else {
++			switch (config_regs->type) {
++			case KV_CONFIGREG_SMC_IND:
++				data = RREG32_SMC(config_regs->offset);
++				break;
++			case KV_CONFIGREG_DIDT_IND:
++				data = RREG32_DIDT(config_regs->offset);
++				break;
++			default:
++				data = RREG32(config_regs->offset);
++				break;
++			}
++
++			data &= ~config_regs->mask;
++			data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
++			data |= cache;
++			cache = 0;
++
++			switch (config_regs->type) {
++			case KV_CONFIGREG_SMC_IND:
++				WREG32_SMC(config_regs->offset, data);
++				break;
++			case KV_CONFIGREG_DIDT_IND:
++				WREG32_DIDT(config_regs->offset, data);
++				break;
++			default:
++				WREG32(config_regs->offset, data);
++				break;
++			}
++		}
++		config_regs++;
++	}
++
++	return 0;
++}
++
++static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 data;
++
++	if (pi->caps_sq_ramping) {
++		data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
++		if (enable)
++			data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
++	}
++
++	if (pi->caps_db_ramping) {
++		data = RREG32_DIDT(ixDIDT_DB_CTRL0);
++		if (enable)
++			data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_DB_CTRL0, data);
++	}
++
++	if (pi->caps_td_ramping) {
++		data = RREG32_DIDT(ixDIDT_TD_CTRL0);
++		if (enable)
++			data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_TD_CTRL0, data);
++	}
++
++	if (pi->caps_tcp_ramping) {
++		data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
++		if (enable)
++			data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
++		else
++			data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
++		WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
++	}
++}
++
++static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	if (pi->caps_sq_ramping ||
++	    pi->caps_db_ramping ||
++	    pi->caps_td_ramping ||
++	    pi->caps_tcp_ramping) {
++		gfx_v7_0_enter_rlc_safe_mode(adev);
++
++		if (enable) {
++			ret = kv_program_pt_config_registers(adev, didt_config_kv);
++			if (ret) {
++				gfx_v7_0_exit_rlc_safe_mode(adev);
++				return ret;
++			}
++		}
++
++		kv_do_enable_didt(adev, enable);
++
++		gfx_v7_0_exit_rlc_safe_mode(adev);
++	}
++
++	return 0;
++}
++
++#if 0
++static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	if (pi->caps_cac) {
++		WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
++		WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
++		kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
++
++		WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
++		WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
++		kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
++
++		WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
++		WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
++		kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
++
++		WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
++		WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
++		kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
++
++		WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
++		WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
++		kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
++
++		WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
++		WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
++		kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
++	}
++}
++#endif
++
++static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret = 0;
++
++	if (pi->caps_cac) {
++		if (enable) {
++			ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
++			if (ret)
++				pi->cac_enabled = false;
++			else
++				pi->cac_enabled = true;
++		} else if (pi->cac_enabled) {
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
++			pi->cac_enabled = false;
++		}
++	}
++
++	return ret;
++}
++
++static int kv_process_firmware_header(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 tmp;
++	int ret;
++
++	ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, DpmTable),
++				     &tmp, pi->sram_end);
++
++	if (ret == 0)
++		pi->dpm_table_start = tmp;
++
++	ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
++				     offsetof(SMU7_Firmware_Header, SoftRegisters),
++				     &tmp, pi->sram_end);
++
++	if (ret == 0)
++		pi->soft_regs_start = tmp;
++
++	return ret;
++}
++
++static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	pi->graphics_voltage_change_enable = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
++				   &pi->graphics_voltage_change_enable,
++				   sizeof(u8), pi->sram_end);
++
++	return ret;
++}
++
++static int kv_set_dpm_interval(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	pi->graphics_interval = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
++				   &pi->graphics_interval,
++				   sizeof(u8), pi->sram_end);
++
++	return ret;
++}
++
++static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
++				   &pi->graphics_boot_level,
++				   sizeof(u8), pi->sram_end);
++
++	return ret;
++}
++
++static void kv_program_vc(struct amdgpu_device *adev)
++{
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
++}
++
++static void kv_clear_vc(struct amdgpu_device *adev)
++{
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
++}
++
++static int kv_set_divider_value(struct amdgpu_device *adev,
++				u32 index, u32 sclk)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct atom_clock_dividers dividers;
++	int ret;
++
++	ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
++						 sclk, false, &dividers);
++	if (ret)
++		return ret;
++
++	pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
++	pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
++
++	return 0;
++}
++
++static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
++					    u16 voltage)
++{
++	return 6200 - (voltage * 25);
++}
++
++static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
++					    u32 vid_2bit)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
++					       &pi->sys_info.vid_mapping_table,
++					       vid_2bit);
++
++	return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
++}
++
++
++static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
++	pi->graphics_level[index].MinVddNb =
++		cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
++
++	return 0;
++}
++
++static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->graphics_level[index].AT = cpu_to_be16((u16)at);
++
++	return 0;
++}
++
++static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
++				      u32 index, bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
++}
++
++static void kv_start_dpm(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
++
++	tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
++	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
++
++	amdgpu_kv_smc_dpm_enable(adev, true);
++}
++
++static void kv_stop_dpm(struct amdgpu_device *adev)
++{
++	amdgpu_kv_smc_dpm_enable(adev, false);
++}
++
++static void kv_start_am(struct amdgpu_device *adev)
++{
++	u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++
++	sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
++			SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
++	sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
++
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
++}
++
++static void kv_reset_am(struct amdgpu_device *adev)
++{
++	u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
++
++	sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
++			SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
++
++	WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
++}
++
++static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
++{
++	return amdgpu_kv_notify_message_to_smu(adev, freeze ?
++					PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
++}
++
++static int kv_force_lowest_valid(struct amdgpu_device *adev)
++{
++	return kv_force_dpm_lowest(adev);
++}
++
++static int kv_unforce_levels(struct amdgpu_device *adev)
++{
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
++		return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
++	else
++		return kv_set_enabled_levels(adev);
++}
++
++static int kv_update_sclk_t(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 low_sclk_interrupt_t = 0;
++	int ret = 0;
++
++	if (pi->caps_sclk_throttle_low_notification) {
++		low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
++
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
++					   (u8 *)&low_sclk_interrupt_t,
++					   sizeof(u32), pi->sram_end);
++	}
++	return ret;
++}
++
++static int kv_program_bootup_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	if (table && table->count) {
++		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
++			if (table->entries[i].clk == pi->boot_pl.sclk)
++				break;
++		}
++
++		pi->graphics_boot_level = (u8)i;
++		kv_dpm_power_level_enable(adev, i, true);
++	} else {
++		struct sumo_sclk_voltage_mapping_table *table =
++			&pi->sys_info.sclk_voltage_mapping_table;
++
++		if (table->num_max_dpm_entries == 0)
++			return -EINVAL;
++
++		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
++			if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
++				break;
++		}
++
++		pi->graphics_boot_level = (u8)i;
++		kv_dpm_power_level_enable(adev, i, true);
++	}
++	return 0;
++}
++
++static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	pi->graphics_therm_throttle_enable = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
++				   &pi->graphics_therm_throttle_enable,
++				   sizeof(u8), pi->sram_end);
++
++	return ret;
++}
++
++static int kv_upload_dpm_settings(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
++				   (u8 *)&pi->graphics_level,
++				   sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
++				   pi->sram_end);
++
++	if (ret)
++		return ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
++				   &pi->graphics_dpm_level_count,
++				   sizeof(u8), pi->sram_end);
++
++	return ret;
++}
++
++static u32 kv_get_clock_difference(u32 a, u32 b)
++{
++	return (a >= b) ? a - b : b - a;
++}
++
++static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 value;
++
++	if (pi->caps_enable_dfs_bypass) {
++		if (kv_get_clock_difference(clk, 40000) < 200)
++			value = 3;
++		else if (kv_get_clock_difference(clk, 30000) < 200)
++			value = 2;
++		else if (kv_get_clock_difference(clk, 20000) < 200)
++			value = 7;
++		else if (kv_get_clock_difference(clk, 15000) < 200)
++			value = 6;
++		else if (kv_get_clock_difference(clk, 10000) < 200)
++			value = 8;
++		else
++			value = 0;
++	} else {
++		value = 0;
++	}
++
++	return value;
++}
++
++static int kv_populate_uvd_table(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_uvd_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
++	struct atom_clock_dividers dividers;
++	int ret;
++	u32 i;
++
++	if (table == NULL || table->count == 0)
++		return 0;
++
++	pi->uvd_level_count = 0;
++	for (i = 0; i < table->count; i++) {
++		if (pi->high_voltage_t &&
++		    (pi->high_voltage_t < table->entries[i].v))
++			break;
++
++		pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
++		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
++		pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
++
++		pi->uvd_level[i].VClkBypassCntl =
++			(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
++		pi->uvd_level[i].DClkBypassCntl =
++			(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
++
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
++							 table->entries[i].vclk, false, &dividers);
++		if (ret)
++			return ret;
++		pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
++
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
++							 table->entries[i].dclk, false, &dividers);
++		if (ret)
++			return ret;
++		pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
++
++		pi->uvd_level_count++;
++	}
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
++				   (u8 *)&pi->uvd_level_count,
++				   sizeof(u8), pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->uvd_interval = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, UVDInterval),
++				   &pi->uvd_interval,
++				   sizeof(u8), pi->sram_end);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, UvdLevel),
++				   (u8 *)&pi->uvd_level,
++				   sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
++				   pi->sram_end);
++
++	return ret;
++
++}
++
++static int kv_populate_vce_table(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++	u32 i;
++	struct amdgpu_vce_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++	struct atom_clock_dividers dividers;
++
++	if (table == NULL || table->count == 0)
++		return 0;
++
++	pi->vce_level_count = 0;
++	for (i = 0; i < table->count; i++) {
++		if (pi->high_voltage_t &&
++		    pi->high_voltage_t < table->entries[i].v)
++			break;
++
++		pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
++		pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
++
++		pi->vce_level[i].ClkBypassCntl =
++			(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
++
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
++							 table->entries[i].evclk, false, &dividers);
++		if (ret)
++			return ret;
++		pi->vce_level[i].Divider = (u8)dividers.post_div;
++
++		pi->vce_level_count++;
++	}
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
++				   (u8 *)&pi->vce_level_count,
++				   sizeof(u8),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->vce_interval = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, VCEInterval),
++				   (u8 *)&pi->vce_interval,
++				   sizeof(u8),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, VceLevel),
++				   (u8 *)&pi->vce_level,
++				   sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
++				   pi->sram_end);
++
++	return ret;
++}
++
++static int kv_populate_samu_table(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
++	struct atom_clock_dividers dividers;
++	int ret;
++	u32 i;
++
++	if (table == NULL || table->count == 0)
++		return 0;
++
++	pi->samu_level_count = 0;
++	for (i = 0; i < table->count; i++) {
++		if (pi->high_voltage_t &&
++		    pi->high_voltage_t < table->entries[i].v)
++			break;
++
++		pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
++		pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
++
++		pi->samu_level[i].ClkBypassCntl =
++			(u8)kv_get_clk_bypass(adev, table->entries[i].clk);
++
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
++							 table->entries[i].clk, false, &dividers);
++		if (ret)
++			return ret;
++		pi->samu_level[i].Divider = (u8)dividers.post_div;
++
++		pi->samu_level_count++;
++	}
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
++				   (u8 *)&pi->samu_level_count,
++				   sizeof(u8),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->samu_interval = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
++				   (u8 *)&pi->samu_interval,
++				   sizeof(u8),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, SamuLevel),
++				   (u8 *)&pi->samu_level,
++				   sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
++
++static int kv_populate_acp_table(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++	struct atom_clock_dividers dividers;
++	int ret;
++	u32 i;
++
++	if (table == NULL || table->count == 0)
++		return 0;
++
++	pi->acp_level_count = 0;
++	for (i = 0; i < table->count; i++) {
++		pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
++		pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
++
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
++							 table->entries[i].clk, false, &dividers);
++		if (ret)
++			return ret;
++		pi->acp_level[i].Divider = (u8)dividers.post_div;
++
++		pi->acp_level_count++;
++	}
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
++				   (u8 *)&pi->acp_level_count,
++				   sizeof(u8),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	pi->acp_interval = 1;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, ACPInterval),
++				   (u8 *)&pi->acp_interval,
++				   sizeof(u8),
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_kv_copy_bytes_to_smc(adev,
++				   pi->dpm_table_start +
++				   offsetof(SMU7_Fusion_DpmTable, AcpLevel),
++				   (u8 *)&pi->acp_level,
++				   sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
++				   pi->sram_end);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
++static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	if (table && table->count) {
++		for (i = 0; i < pi->graphics_dpm_level_count; i++) {
++			if (pi->caps_enable_dfs_bypass) {
++				if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 3;
++				else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 2;
++				else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 7;
++				else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 6;
++				else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 8;
++				else
++					pi->graphics_level[i].ClkBypassCntl = 0;
++			} else {
++				pi->graphics_level[i].ClkBypassCntl = 0;
++			}
++		}
++	} else {
++		struct sumo_sclk_voltage_mapping_table *table =
++			&pi->sys_info.sclk_voltage_mapping_table;
++		for (i = 0; i < pi->graphics_dpm_level_count; i++) {
++			if (pi->caps_enable_dfs_bypass) {
++				if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 3;
++				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 2;
++				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 7;
++				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 6;
++				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
++					pi->graphics_level[i].ClkBypassCntl = 8;
++				else
++					pi->graphics_level[i].ClkBypassCntl = 0;
++			} else {
++				pi->graphics_level[i].ClkBypassCntl = 0;
++			}
++		}
++	}
++}
++
++static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
++{
++	return amdgpu_kv_notify_message_to_smu(adev, enable ?
++					PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
++}
++
++static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->acp_boot_level = 0xff;
++}
++
++static void kv_update_current_ps(struct amdgpu_device *adev,
++				 struct amdgpu_ps *rps)
++{
++	struct kv_ps *new_ps = kv_get_ps(rps);
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->current_rps = *rps;
++	pi->current_ps = *new_ps;
++	pi->current_rps.ps_priv = &pi->current_ps;
++}
++
++static void kv_update_requested_ps(struct amdgpu_device *adev,
++				   struct amdgpu_ps *rps)
++{
++	struct kv_ps *new_ps = kv_get_ps(rps);
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->requested_rps = *rps;
++	pi->requested_ps = *new_ps;
++	pi->requested_rps.ps_priv = &pi->requested_ps;
++}
++
++static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	if (pi->bapm_enable) {
++		ret = amdgpu_kv_smc_bapm_enable(adev, enable);
++		if (ret)
++			DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
++	}
++}
++
++static int kv_dpm_enable(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	ret = kv_process_firmware_header(adev);
++	if (ret) {
++		DRM_ERROR("kv_process_firmware_header failed\n");
++		return ret;
++	}
++	kv_init_fps_limits(adev);
++	kv_init_graphics_levels(adev);
++	ret = kv_program_bootup_state(adev);
++	if (ret) {
++		DRM_ERROR("kv_program_bootup_state failed\n");
++		return ret;
++	}
++	kv_calculate_dfs_bypass_settings(adev);
++	ret = kv_upload_dpm_settings(adev);
++	if (ret) {
++		DRM_ERROR("kv_upload_dpm_settings failed\n");
++		return ret;
++	}
++	ret = kv_populate_uvd_table(adev);
++	if (ret) {
++		DRM_ERROR("kv_populate_uvd_table failed\n");
++		return ret;
++	}
++	ret = kv_populate_vce_table(adev);
++	if (ret) {
++		DRM_ERROR("kv_populate_vce_table failed\n");
++		return ret;
++	}
++	ret = kv_populate_samu_table(adev);
++	if (ret) {
++		DRM_ERROR("kv_populate_samu_table failed\n");
++		return ret;
++	}
++	ret = kv_populate_acp_table(adev);
++	if (ret) {
++		DRM_ERROR("kv_populate_acp_table failed\n");
++		return ret;
++	}
++	kv_program_vc(adev);
++#if 0
++	kv_initialize_hardware_cac_manager(adev);
++#endif
++	kv_start_am(adev);
++	if (pi->enable_auto_thermal_throttling) {
++		ret = kv_enable_auto_thermal_throttling(adev);
++		if (ret) {
++			DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
++			return ret;
++		}
++	}
++	ret = kv_enable_dpm_voltage_scaling(adev);
++	if (ret) {
++		DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
++		return ret;
++	}
++	ret = kv_set_dpm_interval(adev);
++	if (ret) {
++		DRM_ERROR("kv_set_dpm_interval failed\n");
++		return ret;
++	}
++	ret = kv_set_dpm_boot_state(adev);
++	if (ret) {
++		DRM_ERROR("kv_set_dpm_boot_state failed\n");
++		return ret;
++	}
++	ret = kv_enable_ulv(adev, true);
++	if (ret) {
++		DRM_ERROR("kv_enable_ulv failed\n");
++		return ret;
++	}
++	kv_start_dpm(adev);
++	ret = kv_enable_didt(adev, true);
++	if (ret) {
++		DRM_ERROR("kv_enable_didt failed\n");
++		return ret;
++	}
++	ret = kv_enable_smc_cac(adev, true);
++	if (ret) {
++		DRM_ERROR("kv_enable_smc_cac failed\n");
++		return ret;
++	}
++
++	kv_reset_acp_boot_level(adev);
++
++	ret = amdgpu_kv_smc_bapm_enable(adev, false);
++	if (ret) {
++		DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
++		return ret;
++	}
++
++	kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
++
++	if (adev->irq.installed &&
++	    amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
++		ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
++		if (ret) {
++			DRM_ERROR("kv_set_thermal_temperature_range failed\n");
++			return ret;
++		}
++		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
++			       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
++		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
++			       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
++	}
++
++	return ret;
++}
++
++static void kv_dpm_disable(struct amdgpu_device *adev)
++{
++	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
++		       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
++	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
++		       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
++
++	amdgpu_kv_smc_bapm_enable(adev, false);
++
++	if (adev->asic_type == CHIP_MULLINS)
++		kv_enable_nb_dpm(adev, false);
++
++	/* powerup blocks */
++	kv_dpm_powergate_acp(adev, false);
++	kv_dpm_powergate_samu(adev, false);
++	kv_dpm_powergate_vce(adev, false);
++	kv_dpm_powergate_uvd(adev, false);
++
++	kv_enable_smc_cac(adev, false);
++	kv_enable_didt(adev, false);
++	kv_clear_vc(adev);
++	kv_stop_dpm(adev);
++	kv_enable_ulv(adev, false);
++	kv_reset_am(adev);
++
++	kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
++}
++
++#if 0
++static int kv_write_smc_soft_register(struct amdgpu_device *adev,
++				      u16 reg_offset, u32 value)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
++				    (u8 *)&value, sizeof(u16), pi->sram_end);
++}
++
++static int kv_read_smc_soft_register(struct amdgpu_device *adev,
++				     u16 reg_offset, u32 *value)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
++				      value, pi->sram_end);
++}
++#endif
++
++static void kv_init_sclk_t(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->low_sclk_interrupt_t = 0;
++}
++
++static int kv_init_fps_limits(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret = 0;
++
++	if (pi->caps_fps) {
++		u16 tmp;
++
++		tmp = 45;
++		pi->fps_high_t = cpu_to_be16(tmp);
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, FpsHighT),
++					   (u8 *)&pi->fps_high_t,
++					   sizeof(u16), pi->sram_end);
++
++		tmp = 30;
++		pi->fps_low_t = cpu_to_be16(tmp);
++
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, FpsLowT),
++					   (u8 *)&pi->fps_low_t,
++					   sizeof(u16), pi->sram_end);
++
++	}
++	return ret;
++}
++
++static void kv_init_powergate_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->uvd_power_gated = false;
++	pi->vce_power_gated = false;
++	pi->samu_power_gated = false;
++	pi->acp_power_gated = false;
++
++}
++
++static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
++{
++	return amdgpu_kv_notify_message_to_smu(adev, enable ?
++					PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
++}
++
++static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
++{
++	return amdgpu_kv_notify_message_to_smu(adev, enable ?
++					PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
++}
++
++static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
++{
++	return amdgpu_kv_notify_message_to_smu(adev, enable ?
++					PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
++}
++
++static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
++{
++	return amdgpu_kv_notify_message_to_smu(adev, enable ?
++					PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
++}
++
++static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_uvd_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
++	int ret;
++	u32 mask;
++
++	if (!gate) {
++		if (table->count)
++			pi->uvd_boot_level = table->count - 1;
++		else
++			pi->uvd_boot_level = 0;
++
++		if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
++			mask = 1 << pi->uvd_boot_level;
++		} else {
++			mask = 0x1f;
++		}
++
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
++					   (uint8_t *)&pi->uvd_boot_level,
++					   sizeof(u8), pi->sram_end);
++		if (ret)
++			return ret;
++
++		amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++						  PPSMC_MSG_UVDDPM_SetEnabledMask,
++						  mask);
++	}
++
++	return kv_enable_uvd_dpm(adev, !gate);
++}
++
++static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
++{
++	u8 i;
++	struct amdgpu_vce_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++
++	for (i = 0; i < table->count; i++) {
++		if (table->entries[i].evclk >= evclk)
++			break;
++	}
++
++	return i;
++}
++
++static int kv_update_vce_dpm(struct amdgpu_device *adev,
++			     struct amdgpu_ps *amdgpu_new_state,
++			     struct amdgpu_ps *amdgpu_current_state)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_vce_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++	int ret;
++
++	if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
++		kv_dpm_powergate_vce(adev, false);
++		/* turn the clocks on when encoding */
++		ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
++						    AMDGPU_CG_STATE_UNGATE);
++		if (ret)
++			return ret;
++		if (pi->caps_stable_p_state)
++			pi->vce_boot_level = table->count - 1;
++		else
++			pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
++
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
++					   (u8 *)&pi->vce_boot_level,
++					   sizeof(u8),
++					   pi->sram_end);
++		if (ret)
++			return ret;
++
++		if (pi->caps_stable_p_state)
++			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++							  PPSMC_MSG_VCEDPM_SetEnabledMask,
++							  (1 << pi->vce_boot_level));
++
++		kv_enable_vce_dpm(adev, true);
++	} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
++		kv_enable_vce_dpm(adev, false);
++		/* turn the clocks off when not encoding */
++		ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
++						    AMDGPU_CG_STATE_GATE);
++		if (ret)
++			return ret;
++		kv_dpm_powergate_vce(adev, true);
++	}
++
++	return 0;
++}
++
++static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
++	int ret;
++
++	if (!gate) {
++		if (pi->caps_stable_p_state)
++			pi->samu_boot_level = table->count - 1;
++		else
++			pi->samu_boot_level = 0;
++
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
++					   (u8 *)&pi->samu_boot_level,
++					   sizeof(u8),
++					   pi->sram_end);
++		if (ret)
++			return ret;
++
++		if (pi->caps_stable_p_state)
++			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++							  PPSMC_MSG_SAMUDPM_SetEnabledMask,
++							  (1 << pi->samu_boot_level));
++	}
++
++	return kv_enable_samu_dpm(adev, !gate);
++}
++
++static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
++{
++	u8 i;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++
++	for (i = 0; i < table->count; i++) {
++		if (table->entries[i].clk >= 0) /* XXX */
++			break;
++	}
++
++	if (i >= table->count)
++		i = table->count - 1;
++
++	return i;
++}
++
++static void kv_update_acp_boot_level(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u8 acp_boot_level;
++
++	if (!pi->caps_stable_p_state) {
++		acp_boot_level = kv_get_acp_boot_level(adev);
++		if (acp_boot_level != pi->acp_boot_level) {
++			pi->acp_boot_level = acp_boot_level;
++			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++							  PPSMC_MSG_ACPDPM_SetEnabledMask,
++							  (1 << pi->acp_boot_level));
++		}
++	}
++}
++
++static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++	int ret;
++
++	if (!gate) {
++		if (pi->caps_stable_p_state)
++			pi->acp_boot_level = table->count - 1;
++		else
++			pi->acp_boot_level = kv_get_acp_boot_level(adev);
++
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   pi->dpm_table_start +
++					   offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
++					   (u8 *)&pi->acp_boot_level,
++					   sizeof(u8),
++					   pi->sram_end);
++		if (ret)
++			return ret;
++
++		if (pi->caps_stable_p_state)
++			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++							  PPSMC_MSG_ACPDPM_SetEnabledMask,
++							  (1 << pi->acp_boot_level));
++	}
++
++	return kv_enable_acp_dpm(adev, !gate);
++}
++
++static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	if (pi->uvd_power_gated == gate)
++		return;
++
++	pi->uvd_power_gated = gate;
++
++	if (gate) {
++		if (pi->caps_uvd_pg) {
++			/* disable clockgating so we can properly shut down the block */
++			ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
++							    AMDGPU_CG_STATE_UNGATE);
++			/* shutdown the UVD block */
++			ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
++							    AMDGPU_PG_STATE_GATE);
++			/* XXX: check for errors */
++		}
++		kv_update_uvd_dpm(adev, gate);
++		if (pi->caps_uvd_pg)
++			/* power off the UVD block */
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
++	} else {
++		if (pi->caps_uvd_pg) {
++			/* power on the UVD block */
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
++			/* re-init the UVD block */
++			ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
++							    AMDGPU_PG_STATE_UNGATE);
++			/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
++			ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD,
++							    AMDGPU_CG_STATE_GATE);
++			/* XXX: check for errors */
++		}
++		kv_update_uvd_dpm(adev, gate);
++	}
++}
++
++static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret;
++
++	if (pi->vce_power_gated == gate)
++		return;
++
++	pi->vce_power_gated = gate;
++
++	if (gate) {
++		if (pi->caps_vce_pg) {
++			/* shutdown the VCE block */
++			ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
++							    AMDGPU_PG_STATE_GATE);
++			/* XXX: check for errors */
++			/* power off the VCE block */
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
++		}
++	} else {
++		if (pi->caps_vce_pg) {
++			/* power on the VCE block */
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
++			/* re-init the VCE block */
++			ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE,
++							    AMDGPU_PG_STATE_UNGATE);
++			/* XXX: check for errors */
++		}
++	}
++}
++
++static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	if (pi->samu_power_gated == gate)
++		return;
++
++	pi->samu_power_gated = gate;
++
++	if (gate) {
++		kv_update_samu_dpm(adev, true);
++		if (pi->caps_samu_pg)
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
++	} else {
++		if (pi->caps_samu_pg)
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
++		kv_update_samu_dpm(adev, false);
++	}
++}
++
++static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	if (pi->acp_power_gated == gate)
++		return;
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
++		return;
++
++	pi->acp_power_gated = gate;
++
++	if (gate) {
++		kv_update_acp_dpm(adev, true);
++		if (pi->caps_acp_pg)
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
++	} else {
++		if (pi->caps_acp_pg)
++			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
++		kv_update_acp_dpm(adev, false);
++	}
++}
++
++static void kv_set_valid_clock_range(struct amdgpu_device *adev,
++				     struct amdgpu_ps *new_rps)
++{
++	struct kv_ps *new_ps = kv_get_ps(new_rps);
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	if (table && table->count) {
++		for (i = 0; i < pi->graphics_dpm_level_count; i++) {
++			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
++			    (i == (pi->graphics_dpm_level_count - 1))) {
++				pi->lowest_valid = i;
++				break;
++			}
++		}
++
++		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
++			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
++				break;
++		}
++		pi->highest_valid = i;
++
++		if (pi->lowest_valid > pi->highest_valid) {
++			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
++			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
++				pi->highest_valid = pi->lowest_valid;
++			else
++				pi->lowest_valid =  pi->highest_valid;
++		}
++	} else {
++		struct sumo_sclk_voltage_mapping_table *table =
++			&pi->sys_info.sclk_voltage_mapping_table;
++
++		for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
++			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
++			    i == (int)(pi->graphics_dpm_level_count - 1)) {
++				pi->lowest_valid = i;
++				break;
++			}
++		}
++
++		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
++			if (table->entries[i].sclk_frequency <=
++			    new_ps->levels[new_ps->num_levels - 1].sclk)
++				break;
++		}
++		pi->highest_valid = i;
++
++		if (pi->lowest_valid > pi->highest_valid) {
++			if ((new_ps->levels[0].sclk -
++			     table->entries[pi->highest_valid].sclk_frequency) >
++			    (table->entries[pi->lowest_valid].sclk_frequency -
++			     new_ps->levels[new_ps->num_levels -1].sclk))
++				pi->highest_valid = pi->lowest_valid;
++			else
++				pi->lowest_valid =  pi->highest_valid;
++		}
++	}
++}
++
++static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
++					 struct amdgpu_ps *new_rps)
++{
++	struct kv_ps *new_ps = kv_get_ps(new_rps);
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret = 0;
++	u8 clk_bypass_cntl;
++
++	if (pi->caps_enable_dfs_bypass) {
++		clk_bypass_cntl = new_ps->need_dfs_bypass ?
++			pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
++		ret = amdgpu_kv_copy_bytes_to_smc(adev,
++					   (pi->dpm_table_start +
++					    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
++					    (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
++					    offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
++					   &clk_bypass_cntl,
++					   sizeof(u8), pi->sram_end);
++	}
++
++	return ret;
++}
++
++static int kv_enable_nb_dpm(struct amdgpu_device *adev,
++			    bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	int ret = 0;
++
++	if (enable) {
++		if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
++			ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
++			if (ret == 0)
++				pi->nb_dpm_enabled = true;
++		}
++	} else {
++		if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
++			ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
++			if (ret == 0)
++				pi->nb_dpm_enabled = false;
++		}
++	}
++
++	return ret;
++}
++
++static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
++					  enum amdgpu_dpm_forced_level level)
++{
++	int ret;
++
++	if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
++		ret = kv_force_dpm_highest(adev);
++		if (ret)
++			return ret;
++	} else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
++		ret = kv_force_dpm_lowest(adev);
++		if (ret)
++			return ret;
++	} else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
++		ret = kv_unforce_levels(adev);
++		if (ret)
++			return ret;
++	}
++
++	adev->pm.dpm.forced_level = level;
++
++	return 0;
++}
++
++static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
++	struct amdgpu_ps *new_ps = &requested_ps;
++
++	kv_update_requested_ps(adev, new_ps);
++
++	kv_apply_state_adjust_rules(adev,
++				    &pi->requested_rps,
++				    &pi->current_rps);
++
++	return 0;
++}
++
++static int kv_dpm_set_power_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_ps *new_ps = &pi->requested_rps;
++	struct amdgpu_ps *old_ps = &pi->current_rps;
++	int ret;
++
++	if (pi->bapm_enable) {
++		ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power);
++		if (ret) {
++			DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
++			return ret;
++		}
++	}
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
++		if (pi->enable_dpm) {
++			kv_set_valid_clock_range(adev, new_ps);
++			kv_update_dfs_bypass_settings(adev, new_ps);
++			ret = kv_calculate_ds_divider(adev);
++			if (ret) {
++				DRM_ERROR("kv_calculate_ds_divider failed\n");
++				return ret;
++			}
++			kv_calculate_nbps_level_settings(adev);
++			kv_calculate_dpm_settings(adev);
++			kv_force_lowest_valid(adev);
++			kv_enable_new_levels(adev);
++			kv_upload_dpm_settings(adev);
++			kv_program_nbps_index_settings(adev, new_ps);
++			kv_unforce_levels(adev);
++			kv_set_enabled_levels(adev);
++			kv_force_lowest_valid(adev);
++			kv_unforce_levels(adev);
++
++			ret = kv_update_vce_dpm(adev, new_ps, old_ps);
++			if (ret) {
++				DRM_ERROR("kv_update_vce_dpm failed\n");
++				return ret;
++			}
++			kv_update_sclk_t(adev);
++			if (adev->asic_type == CHIP_MULLINS)
++				kv_enable_nb_dpm(adev, true);
++		}
++	} else {
++		if (pi->enable_dpm) {
++			kv_set_valid_clock_range(adev, new_ps);
++			kv_update_dfs_bypass_settings(adev, new_ps);
++			ret = kv_calculate_ds_divider(adev);
++			if (ret) {
++				DRM_ERROR("kv_calculate_ds_divider failed\n");
++				return ret;
++			}
++			kv_calculate_nbps_level_settings(adev);
++			kv_calculate_dpm_settings(adev);
++			kv_freeze_sclk_dpm(adev, true);
++			kv_upload_dpm_settings(adev);
++			kv_program_nbps_index_settings(adev, new_ps);
++			kv_freeze_sclk_dpm(adev, false);
++			kv_set_enabled_levels(adev);
++			ret = kv_update_vce_dpm(adev, new_ps, old_ps);
++			if (ret) {
++				DRM_ERROR("kv_update_vce_dpm failed\n");
++				return ret;
++			}
++			kv_update_acp_boot_level(adev);
++			kv_update_sclk_t(adev);
++			kv_enable_nb_dpm(adev, true);
++		}
++	}
++
++	return 0;
++}
++
++static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_ps *new_ps = &pi->requested_rps;
++
++	kv_update_current_ps(adev, new_ps);
++}
++
++static void kv_dpm_setup_asic(struct amdgpu_device *adev)
++{
++	sumo_take_smu_control(adev, true);
++	kv_init_powergate_state(adev);
++	kv_init_sclk_t(adev);
++}
++
++#if 0
++static void kv_dpm_reset_asic(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
++		kv_force_lowest_valid(adev);
++		kv_init_graphics_levels(adev);
++		kv_program_bootup_state(adev);
++		kv_upload_dpm_settings(adev);
++		kv_force_lowest_valid(adev);
++		kv_unforce_levels(adev);
++	} else {
++		kv_init_graphics_levels(adev);
++		kv_program_bootup_state(adev);
++		kv_freeze_sclk_dpm(adev, true);
++		kv_upload_dpm_settings(adev);
++		kv_freeze_sclk_dpm(adev, false);
++		kv_set_enabled_level(adev, pi->graphics_boot_level);
++	}
++}
++#endif
++
++static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
++						struct amdgpu_clock_and_voltage_limits *table)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
++		int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
++		table->sclk =
++			pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
++		table->vddc =
++			kv_convert_2bit_index_to_voltage(adev,
++							 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
++	}
++
++	table->mclk = pi->sys_info.nbp_memory_clock[0];
++}
++
++static void kv_patch_voltage_values(struct amdgpu_device *adev)
++{
++	int i;
++	struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
++		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
++	struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table *samu_table =
++		&adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table *acp_table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++
++	if (uvd_table->count) {
++		for (i = 0; i < uvd_table->count; i++)
++			uvd_table->entries[i].v =
++				kv_convert_8bit_index_to_voltage(adev,
++								 uvd_table->entries[i].v);
++	}
++
++	if (vce_table->count) {
++		for (i = 0; i < vce_table->count; i++)
++			vce_table->entries[i].v =
++				kv_convert_8bit_index_to_voltage(adev,
++								 vce_table->entries[i].v);
++	}
++
++	if (samu_table->count) {
++		for (i = 0; i < samu_table->count; i++)
++			samu_table->entries[i].v =
++				kv_convert_8bit_index_to_voltage(adev,
++								 samu_table->entries[i].v);
++	}
++
++	if (acp_table->count) {
++		for (i = 0; i < acp_table->count; i++)
++			acp_table->entries[i].v =
++				kv_convert_8bit_index_to_voltage(adev,
++								 acp_table->entries[i].v);
++	}
++
++}
++
++static void kv_construct_boot_state(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
++	pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
++	pi->boot_pl.ds_divider_index = 0;
++	pi->boot_pl.ss_divider_index = 0;
++	pi->boot_pl.allow_gnb_slow = 1;
++	pi->boot_pl.force_nbp_state = 0;
++	pi->boot_pl.display_wm = 0;
++	pi->boot_pl.vce_wm = 0;
++}
++
++static int kv_force_dpm_highest(struct amdgpu_device *adev)
++{
++	int ret;
++	u32 enable_mask, i;
++
++	ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
++	if (ret)
++		return ret;
++
++	for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
++		if (enable_mask & (1 << i))
++			break;
++	}
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
++		return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
++	else
++		return kv_set_enabled_level(adev, i);
++}
++
++static int kv_force_dpm_lowest(struct amdgpu_device *adev)
++{
++	int ret;
++	u32 enable_mask, i;
++
++	ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
++		if (enable_mask & (1 << i))
++			break;
++	}
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
++		return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
++	else
++		return kv_set_enabled_level(adev, i);
++}
++
++static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
++					     u32 sclk, u32 min_sclk_in_sr)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++	u32 temp;
++	u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
++		min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
++
++	if (sclk < min)
++		return 0;
++
++	if (!pi->caps_sclk_ds)
++		return 0;
++
++	for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
++		temp = sclk / sumo_get_sleep_divider_from_id(i);
++		if (temp >= min)
++			break;
++	}
++
++	return (u8)i;
++}
++
++static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	int i;
++
++	if (table && table->count) {
++		for (i = table->count - 1; i >= 0; i--) {
++			if (pi->high_voltage_t &&
++			    (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
++			     pi->high_voltage_t)) {
++				*limit = i;
++				return 0;
++			}
++		}
++	} else {
++		struct sumo_sclk_voltage_mapping_table *table =
++			&pi->sys_info.sclk_voltage_mapping_table;
++
++		for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
++			if (pi->high_voltage_t &&
++			    (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
++			     pi->high_voltage_t)) {
++				*limit = i;
++				return 0;
++			}
++		}
++	}
++
++	*limit = 0;
++	return 0;
++}
++
++static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
++					struct amdgpu_ps *new_rps,
++					struct amdgpu_ps *old_rps)
++{
++	struct kv_ps *ps = kv_get_ps(new_rps);
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 min_sclk = 10000; /* ??? */
++	u32 sclk, mclk = 0;
++	int i, limit;
++	bool force_high;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	u32 stable_p_state_sclk = 0;
++	struct amdgpu_clock_and_voltage_limits *max_limits =
++		&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++
++	if (new_rps->vce_active) {
++		new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
++		new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
++	} else {
++		new_rps->evclk = 0;
++		new_rps->ecclk = 0;
++	}
++
++	mclk = max_limits->mclk;
++	sclk = min_sclk;
++
++	if (pi->caps_stable_p_state) {
++		stable_p_state_sclk = (max_limits->sclk * 75) / 100;
++
++		for (i = table->count - 1; i >= 0; i++) {
++			if (stable_p_state_sclk >= table->entries[i].clk) {
++				stable_p_state_sclk = table->entries[i].clk;
++				break;
++			}
++		}
++
++		if (i > 0)
++			stable_p_state_sclk = table->entries[0].clk;
++
++		sclk = stable_p_state_sclk;
++	}
++
++	if (new_rps->vce_active) {
++		if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
++			sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
++	}
++
++	ps->need_dfs_bypass = true;
++
++	for (i = 0; i < ps->num_levels; i++) {
++		if (ps->levels[i].sclk < sclk)
++			ps->levels[i].sclk = sclk;
++	}
++
++	if (table && table->count) {
++		for (i = 0; i < ps->num_levels; i++) {
++			if (pi->high_voltage_t &&
++			    (pi->high_voltage_t <
++			     kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
++				kv_get_high_voltage_limit(adev, &limit);
++				ps->levels[i].sclk = table->entries[limit].clk;
++			}
++		}
++	} else {
++		struct sumo_sclk_voltage_mapping_table *table =
++			&pi->sys_info.sclk_voltage_mapping_table;
++
++		for (i = 0; i < ps->num_levels; i++) {
++			if (pi->high_voltage_t &&
++			    (pi->high_voltage_t <
++			     kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
++				kv_get_high_voltage_limit(adev, &limit);
++				ps->levels[i].sclk = table->entries[limit].sclk_frequency;
++			}
++		}
++	}
++
++	if (pi->caps_stable_p_state) {
++		for (i = 0; i < ps->num_levels; i++) {
++			ps->levels[i].sclk = stable_p_state_sclk;
++		}
++	}
++
++	pi->video_start = new_rps->dclk || new_rps->vclk ||
++		new_rps->evclk || new_rps->ecclk;
++
++	if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
++	    ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
++		pi->battery_state = true;
++	else
++		pi->battery_state = false;
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
++		ps->dpm0_pg_nb_ps_lo = 0x1;
++		ps->dpm0_pg_nb_ps_hi = 0x0;
++		ps->dpmx_nb_ps_lo = 0x1;
++		ps->dpmx_nb_ps_hi = 0x0;
++	} else {
++		ps->dpm0_pg_nb_ps_lo = 0x3;
++		ps->dpm0_pg_nb_ps_hi = 0x0;
++		ps->dpmx_nb_ps_lo = 0x3;
++		ps->dpmx_nb_ps_hi = 0x0;
++
++		if (pi->sys_info.nb_dpm_enable) {
++			force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
++				pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
++				pi->disable_nb_ps3_in_battery;
++			ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
++			ps->dpm0_pg_nb_ps_hi = 0x2;
++			ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
++			ps->dpmx_nb_ps_hi = 0x2;
++		}
++	}
++}
++
++static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
++						    u32 index, bool enable)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
++}
++
++static int kv_calculate_ds_divider(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 sclk_in_sr = 10000; /* ??? */
++	u32 i;
++
++	if (pi->lowest_valid > pi->highest_valid)
++		return -EINVAL;
++
++	for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
++		pi->graphics_level[i].DeepSleepDivId =
++			kv_get_sleep_divider_id_from_clock(adev,
++							   be32_to_cpu(pi->graphics_level[i].SclkFrequency),
++							   sclk_in_sr);
++	}
++	return 0;
++}
++
++static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++	bool force_high;
++	struct amdgpu_clock_and_voltage_limits *max_limits =
++		&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	u32 mclk = max_limits->mclk;
++
++	if (pi->lowest_valid > pi->highest_valid)
++		return -EINVAL;
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
++		for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
++			pi->graphics_level[i].GnbSlow = 1;
++			pi->graphics_level[i].ForceNbPs1 = 0;
++			pi->graphics_level[i].UpH = 0;
++		}
++
++		if (!pi->sys_info.nb_dpm_enable)
++			return 0;
++
++		force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
++			      (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
++
++		if (force_high) {
++			for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
++				pi->graphics_level[i].GnbSlow = 0;
++		} else {
++			if (pi->battery_state)
++				pi->graphics_level[0].ForceNbPs1 = 1;
++
++			pi->graphics_level[1].GnbSlow = 0;
++			pi->graphics_level[2].GnbSlow = 0;
++			pi->graphics_level[3].GnbSlow = 0;
++			pi->graphics_level[4].GnbSlow = 0;
++		}
++	} else {
++		for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
++			pi->graphics_level[i].GnbSlow = 1;
++			pi->graphics_level[i].ForceNbPs1 = 0;
++			pi->graphics_level[i].UpH = 0;
++		}
++
++		if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
++			pi->graphics_level[pi->lowest_valid].UpH = 0x28;
++			pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
++			if (pi->lowest_valid != pi->highest_valid)
++				pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
++		}
++	}
++	return 0;
++}
++
++static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++
++	if (pi->lowest_valid > pi->highest_valid)
++		return -EINVAL;
++
++	for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
++		pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
++
++	return 0;
++}
++
++static void kv_init_graphics_levels(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	if (table && table->count) {
++		u32 vid_2bit;
++
++		pi->graphics_dpm_level_count = 0;
++		for (i = 0; i < table->count; i++) {
++			if (pi->high_voltage_t &&
++			    (pi->high_voltage_t <
++			     kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
++				break;
++
++			kv_set_divider_value(adev, i, table->entries[i].clk);
++			vid_2bit = kv_convert_vid7_to_vid2(adev,
++							   &pi->sys_info.vid_mapping_table,
++							   table->entries[i].v);
++			kv_set_vid(adev, i, vid_2bit);
++			kv_set_at(adev, i, pi->at[i]);
++			kv_dpm_power_level_enabled_for_throttle(adev, i, true);
++			pi->graphics_dpm_level_count++;
++		}
++	} else {
++		struct sumo_sclk_voltage_mapping_table *table =
++			&pi->sys_info.sclk_voltage_mapping_table;
++
++		pi->graphics_dpm_level_count = 0;
++		for (i = 0; i < table->num_max_dpm_entries; i++) {
++			if (pi->high_voltage_t &&
++			    pi->high_voltage_t <
++			    kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
++				break;
++
++			kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
++			kv_set_vid(adev, i, table->entries[i].vid_2bit);
++			kv_set_at(adev, i, pi->at[i]);
++			kv_dpm_power_level_enabled_for_throttle(adev, i, true);
++			pi->graphics_dpm_level_count++;
++		}
++	}
++
++	for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
++		kv_dpm_power_level_enable(adev, i, false);
++}
++
++static void kv_enable_new_levels(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i;
++
++	for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
++		if (i >= pi->lowest_valid && i <= pi->highest_valid)
++			kv_dpm_power_level_enable(adev, i, true);
++	}
++}
++
++static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
++{
++	u32 new_mask = (1 << level);
++
++	return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++						 PPSMC_MSG_SCLKDPM_SetEnabledMask,
++						 new_mask);
++}
++
++static int kv_set_enabled_levels(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 i, new_mask = 0;
++
++	for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
++		new_mask |= (1 << i);
++
++	return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
++						 PPSMC_MSG_SCLKDPM_SetEnabledMask,
++						 new_mask);
++}
++
++static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
++					   struct amdgpu_ps *new_rps)
++{
++	struct kv_ps *new_ps = kv_get_ps(new_rps);
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 nbdpmconfig1;
++
++	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
++		return;
++
++	if (pi->sys_info.nb_dpm_enable) {
++		nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
++		nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
++				NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
++				NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
++				NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
++		nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
++				(new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
++				(new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
++				(new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
++		WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
++	}
++}
++
++static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
++					    int min_temp, int max_temp)
++{
++	int low_temp = 0 * 1000;
++	int high_temp = 255 * 1000;
++	u32 tmp;
++
++	if (low_temp < min_temp)
++		low_temp = min_temp;
++	if (high_temp > max_temp)
++		high_temp = max_temp;
++	if (high_temp < low_temp) {
++		DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
++		return -EINVAL;
++	}
++
++	tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
++	tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
++		CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
++	tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
++		((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
++	WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
++
++	adev->pm.dpm.thermal.min_temp = low_temp;
++	adev->pm.dpm.thermal.max_temp = high_temp;
++
++	return 0;
++}
++
++union igp_info {
++	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
++};
++
++static int kv_parse_sys_info_table(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
++	union igp_info *igp_info;
++	u8 frev, crev;
++	u16 data_offset;
++	int i;
++
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset)) {
++		igp_info = (union igp_info *)(mode_info->atom_context->bios +
++					      data_offset);
++
++		if (crev != 8) {
++			DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
++			return -EINVAL;
++		}
++		pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
++		pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
++		pi->sys_info.bootup_nb_voltage_index =
++			le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
++		if (igp_info->info_8.ucHtcTmpLmt == 0)
++			pi->sys_info.htc_tmp_lmt = 203;
++		else
++			pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
++		if (igp_info->info_8.ucHtcHystLmt == 0)
++			pi->sys_info.htc_hyst_lmt = 5;
++		else
++			pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
++		if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
++			DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
++		}
++
++		if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
++			pi->sys_info.nb_dpm_enable = true;
++		else
++			pi->sys_info.nb_dpm_enable = false;
++
++		for (i = 0; i < KV_NUM_NBPSTATES; i++) {
++			pi->sys_info.nbp_memory_clock[i] =
++				le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
++			pi->sys_info.nbp_n_clock[i] =
++				le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
++		}
++		if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
++		    SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
++			pi->caps_enable_dfs_bypass = true;
++
++		sumo_construct_sclk_voltage_mapping_table(adev,
++							  &pi->sys_info.sclk_voltage_mapping_table,
++							  igp_info->info_8.sAvail_SCLK);
++
++		sumo_construct_vid_mapping_table(adev,
++						 &pi->sys_info.vid_mapping_table,
++						 igp_info->info_8.sAvail_SCLK);
++
++		kv_construct_max_power_limits_table(adev,
++						    &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
++	}
++	return 0;
++}
++
++union power_info {
++	struct _ATOM_POWERPLAY_INFO info;
++	struct _ATOM_POWERPLAY_INFO_V2 info_2;
++	struct _ATOM_POWERPLAY_INFO_V3 info_3;
++	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
++	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
++	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
++};
++
++union pplib_clock_info {
++	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
++	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
++	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
++	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
++};
++
++union pplib_power_state {
++	struct _ATOM_PPLIB_STATE v1;
++	struct _ATOM_PPLIB_STATE_V2 v2;
++};
++
++static void kv_patch_boot_state(struct amdgpu_device *adev,
++				struct kv_ps *ps)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	ps->num_levels = 1;
++	ps->levels[0] = pi->boot_pl;
++}
++
++static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
++					  struct amdgpu_ps *rps,
++					  struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
++					  u8 table_rev)
++{
++	struct kv_ps *ps = kv_get_ps(rps);
++
++	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
++	rps->class = le16_to_cpu(non_clock_info->usClassification);
++	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
++
++	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
++		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
++		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
++	} else {
++		rps->vclk = 0;
++		rps->dclk = 0;
++	}
++
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
++		adev->pm.dpm.boot_ps = rps;
++		kv_patch_boot_state(adev, ps);
++	}
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
++		adev->pm.dpm.uvd_ps = rps;
++}
++
++static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
++				      struct amdgpu_ps *rps, int index,
++					union pplib_clock_info *clock_info)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct kv_ps *ps = kv_get_ps(rps);
++	struct kv_pl *pl = &ps->levels[index];
++	u32 sclk;
++
++	sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
++	sclk |= clock_info->sumo.ucEngineClockHigh << 16;
++	pl->sclk = sclk;
++	pl->vddc_index = clock_info->sumo.vddcIndex;
++
++	ps->num_levels = index + 1;
++
++	if (pi->caps_sclk_ds) {
++		pl->ds_divider_index = 5;
++		pl->ss_divider_index = 5;
++	}
++}
++
++static int kv_parse_power_table(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
++	union pplib_power_state *power_state;
++	int i, j, k, non_clock_array_index, clock_array_index;
++	union pplib_clock_info *clock_info;
++	struct _StateArray *state_array;
++	struct _ClockInfoArray *clock_info_array;
++	struct _NonClockInfoArray *non_clock_info_array;
++	union power_info *power_info;
++	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
++	u16 data_offset;
++	u8 frev, crev;
++	u8 *power_state_offset;
++	struct kv_ps *ps;
++
++	if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset))
++		return -EINVAL;
++	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
++
++	amdgpu_add_thermal_controller(adev);
++
++	state_array = (struct _StateArray *)
++		(mode_info->atom_context->bios + data_offset +
++		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
++	clock_info_array = (struct _ClockInfoArray *)
++		(mode_info->atom_context->bios + data_offset +
++		 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
++	non_clock_info_array = (struct _NonClockInfoArray *)
++		(mode_info->atom_context->bios + data_offset +
++		 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
++
++	adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
++				  state_array->ucNumEntries, GFP_KERNEL);
++	if (!adev->pm.dpm.ps)
++		return -ENOMEM;
++	power_state_offset = (u8 *)state_array->states;
++	for (i = 0; i < state_array->ucNumEntries; i++) {
++		u8 *idx;
++		power_state = (union pplib_power_state *)power_state_offset;
++		non_clock_array_index = power_state->v2.nonClockInfoIndex;
++		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
++			&non_clock_info_array->nonClockInfo[non_clock_array_index];
++		ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
++		if (ps == NULL) {
++			kfree(adev->pm.dpm.ps);
++			return -ENOMEM;
++		}
++		adev->pm.dpm.ps[i].ps_priv = ps;
++		k = 0;
++		idx = (u8 *)&power_state->v2.clockInfoIndex[0];
++		for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
++			clock_array_index = idx[j];
++			if (clock_array_index >= clock_info_array->ucNumEntries)
++				continue;
++			if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
++				break;
++			clock_info = (union pplib_clock_info *)
++				((u8 *)&clock_info_array->clockInfo[0] +
++				 (clock_array_index * clock_info_array->ucEntrySize));
++			kv_parse_pplib_clock_info(adev,
++						  &adev->pm.dpm.ps[i], k,
++						  clock_info);
++			k++;
++		}
++		kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
++					      non_clock_info,
++					      non_clock_info_array->ucEntrySize);
++		power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
++	}
++	adev->pm.dpm.num_ps = state_array->ucNumEntries;
++
++	/* fill in the vce power states */
++	for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
++		u32 sclk;
++		clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
++		clock_info = (union pplib_clock_info *)
++			&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
++		sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
++		sclk |= clock_info->sumo.ucEngineClockHigh << 16;
++		adev->pm.dpm.vce_states[i].sclk = sclk;
++		adev->pm.dpm.vce_states[i].mclk = 0;
++	}
++
++	return 0;
++}
++
++static int kv_dpm_init(struct amdgpu_device *adev)
++{
++	struct kv_power_info *pi;
++	int ret, i;
++
++	pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
++	if (pi == NULL)
++		return -ENOMEM;
++	adev->pm.dpm.priv = pi;
++
++	ret = amdgpu_get_platform_caps(adev);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_parse_extended_power_table(adev);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
++		pi->at[i] = TRINITY_AT_DFLT;
++
++	pi->sram_end = SMC_RAM_END;
++
++	pi->enable_nb_dpm = true;
++
++	pi->caps_power_containment = true;
++	pi->caps_cac = true;
++	pi->enable_didt = false;
++	if (pi->enable_didt) {
++		pi->caps_sq_ramping = true;
++		pi->caps_db_ramping = true;
++		pi->caps_td_ramping = true;
++		pi->caps_tcp_ramping = true;
++	}
++
++	pi->caps_sclk_ds = true;
++	pi->enable_auto_thermal_throttling = true;
++	pi->disable_nb_ps3_in_battery = false;
++	if (amdgpu_bapm == 0)
++		pi->bapm_enable = false;
++	else
++		pi->bapm_enable = true;
++	pi->voltage_drop_t = 0;
++	pi->caps_sclk_throttle_low_notification = false;
++	pi->caps_fps = false; /* true? */
++	pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
++	pi->caps_uvd_dpm = true;
++	pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
++	pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false;
++	pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
++	pi->caps_stable_p_state = false;
++
++	ret = kv_parse_sys_info_table(adev);
++	if (ret)
++		return ret;
++
++	kv_patch_voltage_values(adev);
++	kv_construct_boot_state(adev);
++
++	ret = kv_parse_power_table(adev);
++	if (ret)
++		return ret;
++
++	pi->enable_dpm = true;
++
++	return 0;
++}
++
++static void
++kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
++					       struct seq_file *m)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	u32 current_index =
++		(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
++		TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
++		TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
++	u32 sclk, tmp;
++	u16 vddc;
++
++	if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
++		seq_printf(m, "invalid dpm profile %d\n", current_index);
++	} else {
++		sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
++		tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
++			SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
++			SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
++		vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
++		seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");
++		seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");
++		seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
++			   current_index, sclk, vddc);
++	}
++}
++
++static void
++kv_dpm_print_power_state(struct amdgpu_device *adev,
++			 struct amdgpu_ps *rps)
++{
++	int i;
++	struct kv_ps *ps = kv_get_ps(rps);
++
++	amdgpu_dpm_print_class_info(rps->class, rps->class2);
++	amdgpu_dpm_print_cap_info(rps->caps);
++	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
++	for (i = 0; i < ps->num_levels; i++) {
++		struct kv_pl *pl = &ps->levels[i];
++		printk("\t\tpower level %d    sclk: %u vddc: %u\n",
++		       i, pl->sclk,
++		       kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
++	}
++	amdgpu_dpm_print_ps_status(adev, rps);
++}
++
++static void kv_dpm_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->pm.dpm.num_ps; i++) {
++		kfree(adev->pm.dpm.ps[i].ps_priv);
++	}
++	kfree(adev->pm.dpm.ps);
++	kfree(adev->pm.dpm.priv);
++	amdgpu_free_extended_power_table(adev);
++}
++
++static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
++{
++
++}
++
++static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++	struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
++
++	if (low)
++		return requested_state->levels[0].sclk;
++	else
++		return requested_state->levels[requested_state->num_levels - 1].sclk;
++}
++
++static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
++{
++	struct kv_power_info *pi = kv_get_pi(adev);
++
++	return pi->sys_info.bootup_uma_clk;
++}
++
++/* get temperature in millidegrees */
++static int kv_dpm_get_temp(struct amdgpu_device *adev)
++{
++	u32 temp;
++	int actual_temp = 0;
++
++	temp = RREG32_SMC(0xC0300E0C);
++
++	if (temp)
++		actual_temp = (temp / 8) - 49;
++	else
++		actual_temp = 0;
++
++	actual_temp = actual_temp * 1000;
++
++	return actual_temp;
++}
++
++static int kv_dpm_early_init(struct amdgpu_device *adev)
++{
++	kv_dpm_set_dpm_funcs(adev);
++	kv_dpm_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int kv_dpm_late_init(struct amdgpu_device *adev)
++{
++	if (!amdgpu_dpm)
++		return 0;
++
++	/* powerdown unused blocks for now */
++	kv_dpm_powergate_acp(adev, true);
++	kv_dpm_powergate_samu(adev, true);
++	kv_dpm_powergate_vce(adev, true);
++	kv_dpm_powergate_uvd(adev, true);
++
++	return 0;
++}
++
++static int kv_dpm_sw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
++	if (ret)
++		return ret;
++
++	/* default to balanced state */
++	adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
++	adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
++	adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
++	adev->pm.default_sclk = adev->clock.default_sclk;
++	adev->pm.default_mclk = adev->clock.default_mclk;
++	adev->pm.current_sclk = adev->clock.default_sclk;
++	adev->pm.current_mclk = adev->clock.default_mclk;
++	adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
++
++	if (amdgpu_dpm == 0)
++		return 0;
++
++	INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
++	mutex_lock(&adev->pm.mutex);
++	ret = kv_dpm_init(adev);
++	if (ret)
++		goto dpm_failed;
++	adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
++	if (amdgpu_dpm == 1)
++		amdgpu_pm_print_power_states(adev);
++	ret = amdgpu_pm_sysfs_init(adev);
++	if (ret)
++		goto dpm_failed;
++	mutex_unlock(&adev->pm.mutex);
++	DRM_INFO("amdgpu: dpm initialized\n");
++
++	return 0;
++
++dpm_failed:
++	kv_dpm_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++	DRM_ERROR("amdgpu: dpm initialization failed\n");
++	return ret;
++}
++
++static int kv_dpm_sw_fini(struct amdgpu_device *adev)
++{
++	mutex_lock(&adev->pm.mutex);
++	amdgpu_pm_sysfs_fini(adev);
++	kv_dpm_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++
++	return 0;
++}
++
++static int kv_dpm_hw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (!amdgpu_dpm)
++		return 0;
++
++	mutex_lock(&adev->pm.mutex);
++	kv_dpm_setup_asic(adev);
++	ret = kv_dpm_enable(adev);
++	if (ret)
++		adev->pm.dpm_enabled = false;
++	else
++		adev->pm.dpm_enabled = true;
++	mutex_unlock(&adev->pm.mutex);
++
++	return ret;
++}
++
++static int kv_dpm_hw_fini(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++		kv_dpm_disable(adev);
++		mutex_unlock(&adev->pm.mutex);
++	}
++
++	return 0;
++}
++
++static int kv_dpm_suspend(struct amdgpu_device *adev)
++{
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++		/* disable dpm */
++		kv_dpm_disable(adev);
++		/* reset the power state */
++		adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
++		mutex_unlock(&adev->pm.mutex);
++	}
++	return 0;
++}
++
++static int kv_dpm_resume(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (adev->pm.dpm_enabled) {
++		/* asic init will reset to the boot state */
++		mutex_lock(&adev->pm.mutex);
++		kv_dpm_setup_asic(adev);
++		ret = kv_dpm_enable(adev);
++		if (ret)
++			adev->pm.dpm_enabled = false;
++		else
++			adev->pm.dpm_enabled = true;
++		mutex_unlock(&adev->pm.mutex);
++		if (adev->pm.dpm_enabled)
++			amdgpu_pm_compute_clocks(adev);
++	}
++	return 0;
++}
++
++static bool kv_dpm_is_idle(struct amdgpu_device *adev)
++{
++	/* XXX */
++	return true;
++}
++
++static int kv_dpm_wait_for_idle(struct amdgpu_device *adev)
++{
++	/* XXX */
++	return 0;
++}
++
++static void kv_dpm_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "KV/KB DPM registers\n");
++	dev_info(adev->dev, "  DIDT_SQ_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_SQ_CTRL0));
++	dev_info(adev->dev, "  DIDT_DB_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_DB_CTRL0));
++	dev_info(adev->dev, "  DIDT_TD_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_TD_CTRL0));
++	dev_info(adev->dev, "  DIDT_TCP_CTRL0=0x%08X\n",
++		 RREG32_DIDT(ixDIDT_TCP_CTRL0));
++	dev_info(adev->dev, "  LCAC_SX0_OVR_SEL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_SX0_OVR_SEL));
++	dev_info(adev->dev, "  LCAC_SX0_OVR_VAL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_SX0_OVR_VAL));
++	dev_info(adev->dev, "  LCAC_MC0_OVR_SEL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC0_OVR_SEL));
++	dev_info(adev->dev, "  LCAC_MC0_OVR_VAL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC0_OVR_VAL));
++	dev_info(adev->dev, "  LCAC_MC1_OVR_SEL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC1_OVR_SEL));
++	dev_info(adev->dev, "  LCAC_MC1_OVR_VAL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC1_OVR_VAL));
++	dev_info(adev->dev, "  LCAC_MC2_OVR_SEL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC2_OVR_SEL));
++	dev_info(adev->dev, "  LCAC_MC2_OVR_VAL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC2_OVR_VAL));
++	dev_info(adev->dev, "  LCAC_MC3_OVR_SEL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC3_OVR_SEL));
++	dev_info(adev->dev, "  LCAC_MC3_OVR_VAL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_MC3_OVR_VAL));
++	dev_info(adev->dev, "  LCAC_CPL_OVR_SEL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_CPL_OVR_SEL));
++	dev_info(adev->dev, "  LCAC_CPL_OVR_VAL=0x%08X\n",
++		 RREG32_SMC(ixLCAC_CPL_OVR_VAL));
++	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_0=0x%08X\n",
++		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
++	dev_info(adev->dev, "  GENERAL_PWRMGT=0x%08X\n",
++		 RREG32_SMC(ixGENERAL_PWRMGT));
++	dev_info(adev->dev, "  SCLK_PWRMGT_CNTL=0x%08X\n",
++		 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
++	dev_info(adev->dev, "  SMC_MESSAGE_0=0x%08X\n",
++		 RREG32(mmSMC_MESSAGE_0));
++	dev_info(adev->dev, "  SMC_RESP_0=0x%08X\n",
++		 RREG32(mmSMC_RESP_0));
++	dev_info(adev->dev, "  SMC_MSG_ARG_0=0x%08X\n",
++		 RREG32(mmSMC_MSG_ARG_0));
++	dev_info(adev->dev, "  SMC_IND_INDEX_0=0x%08X\n",
++		 RREG32(mmSMC_IND_INDEX_0));
++	dev_info(adev->dev, "  SMC_IND_DATA_0=0x%08X\n",
++		 RREG32(mmSMC_IND_DATA_0));
++	dev_info(adev->dev, "  SMC_IND_ACCESS_CNTL=0x%08X\n",
++		 RREG32(mmSMC_IND_ACCESS_CNTL));
++}
++
++static int kv_dpm_soft_reset(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *src,
++				      unsigned type,
++				      enum amdgpu_interrupt_state state)
++{
++	u32 cg_thermal_int;
++
++	switch (type) {
++	case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
++			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
++			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
++			break;
++		default:
++			break;
++		}
++		break;
++
++	case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
++			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
++			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
++			WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
++			break;
++		default:
++			break;
++		}
++		break;
++
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
++				    struct amdgpu_irq_src *source,
++				    struct amdgpu_iv_entry *entry)
++{
++	bool queue_thermal = false;
++
++	if (entry == NULL)
++		return -EINVAL;
++
++	switch (entry->src_id) {
++	case 230: /* thermal low to high */
++		DRM_DEBUG("IH: thermal low to high\n");
++		adev->pm.dpm.thermal.high_to_low = false;
++		queue_thermal = true;
++		break;
++	case 231: /* thermal high to low */
++		DRM_DEBUG("IH: thermal high to low\n");
++		adev->pm.dpm.thermal.high_to_low = true;
++		queue_thermal = true;
++		break;
++	default:
++		break;
++	}
++
++	if (queue_thermal)
++		schedule_work(&adev->pm.dpm.thermal.work);
++
++	return 0;
++}
++
++static int kv_dpm_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int kv_dpm_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs kv_dpm_ip_funcs = {
++	.early_init = kv_dpm_early_init,
++	.late_init = kv_dpm_late_init,
++	.sw_init = kv_dpm_sw_init,
++	.sw_fini = kv_dpm_sw_fini,
++	.hw_init = kv_dpm_hw_init,
++	.hw_fini = kv_dpm_hw_fini,
++	.suspend = kv_dpm_suspend,
++	.resume = kv_dpm_resume,
++	.is_idle = kv_dpm_is_idle,
++	.wait_for_idle = kv_dpm_wait_for_idle,
++	.soft_reset = kv_dpm_soft_reset,
++	.print_status = kv_dpm_print_status,
++	.set_clockgating_state = kv_dpm_set_clockgating_state,
++	.set_powergating_state = kv_dpm_set_powergating_state,
++};
++
++static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
++	.get_temperature = &kv_dpm_get_temp,
++	.pre_set_power_state = &kv_dpm_pre_set_power_state,
++	.set_power_state = &kv_dpm_set_power_state,
++	.post_set_power_state = &kv_dpm_post_set_power_state,
++	.display_configuration_changed = &kv_dpm_display_configuration_changed,
++	.get_sclk = &kv_dpm_get_sclk,
++	.get_mclk = &kv_dpm_get_mclk,
++	.print_power_state = &kv_dpm_print_power_state,
++	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
++	.force_performance_level = &kv_dpm_force_performance_level,
++	.powergate_uvd = &kv_dpm_powergate_uvd,
++	.enable_bapm = &kv_dpm_enable_bapm,
++};
++
++static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
++{
++	if (adev->pm.funcs == NULL)
++		adev->pm.funcs = &kv_dpm_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
++	.set = kv_dpm_set_interrupt_state,
++	.process = kv_dpm_process_interrupt,
++};
++
++static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
++	adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.h b/drivers/gpu/drm/amd/amdgpu/kv_dpm.h
+new file mode 100644
+index 0000000..6df0ed4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.h
+@@ -0,0 +1,229 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __KV_DPM_H__
++#define __KV_DPM_H__
++
++#define SMU__NUM_SCLK_DPM_STATE  8
++#define SMU__NUM_MCLK_DPM_LEVELS 4
++#define SMU__NUM_LCLK_DPM_LEVELS 8
++#define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
++#include "smu7_fusion.h"
++#include "ppsmc.h"
++
++#define SUMO_MAX_HARDWARE_POWERLEVELS 5
++
++#define SUMO_MAX_NUMBER_VOLTAGES    4
++
++struct sumo_vid_mapping_entry {
++	u16 vid_2bit;
++	u16 vid_7bit;
++};
++
++struct sumo_vid_mapping_table {
++	u32 num_entries;
++	struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
++};
++
++struct sumo_sclk_voltage_mapping_entry {
++	u32 sclk_frequency;
++	u16 vid_2bit;
++	u16 rsv;
++};
++
++struct sumo_sclk_voltage_mapping_table {
++	u32 num_max_dpm_entries;
++	struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
++};
++
++#define TRINITY_AT_DFLT            30
++
++#define KV_NUM_NBPSTATES   4
++
++enum kv_pt_config_reg_type {
++	KV_CONFIGREG_MMR = 0,
++	KV_CONFIGREG_SMC_IND,
++	KV_CONFIGREG_DIDT_IND,
++	KV_CONFIGREG_CACHE,
++	KV_CONFIGREG_MAX
++};
++
++struct kv_pt_config_reg {
++	u32 offset;
++	u32 mask;
++	u32 shift;
++	u32 value;
++	enum kv_pt_config_reg_type type;
++};
++
++struct kv_lcac_config_values {
++	u32 block_id;
++	u32 signal_id;
++	u32 t;
++};
++
++struct kv_lcac_config_reg {
++	u32 cntl;
++	u32 block_mask;
++	u32 block_shift;
++	u32 signal_mask;
++	u32 signal_shift;
++	u32 t_mask;
++	u32 t_shift;
++	u32 enable_mask;
++	u32 enable_shift;
++};
++
++struct kv_pl {
++	u32 sclk;
++	u8 vddc_index;
++	u8 ds_divider_index;
++	u8 ss_divider_index;
++	u8 allow_gnb_slow;
++	u8 force_nbp_state;
++	u8 display_wm;
++	u8 vce_wm;
++};
++
++struct kv_ps {
++	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
++	u32 num_levels;
++	bool need_dfs_bypass;
++	u8 dpm0_pg_nb_ps_lo;
++	u8 dpm0_pg_nb_ps_hi;
++	u8 dpmx_nb_ps_lo;
++	u8 dpmx_nb_ps_hi;
++};
++
++struct kv_sys_info {
++	u32 bootup_uma_clk;
++	u32 bootup_sclk;
++	u32 dentist_vco_freq;
++	u32 nb_dpm_enable;
++	u32 nbp_memory_clock[KV_NUM_NBPSTATES];
++	u32 nbp_n_clock[KV_NUM_NBPSTATES];
++	u16 bootup_nb_voltage_index;
++	u8 htc_tmp_lmt;
++	u8 htc_hyst_lmt;
++	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
++	struct sumo_vid_mapping_table vid_mapping_table;
++	u32 uma_channel_number;
++};
++
++struct kv_power_info {
++	u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
++	u32 voltage_drop_t;
++	struct kv_sys_info sys_info;
++	struct kv_pl boot_pl;
++	bool enable_nb_ps_policy;
++	bool disable_nb_ps3_in_battery;
++	bool video_start;
++	bool battery_state;
++	u32 lowest_valid;
++	u32 highest_valid;
++	u16 high_voltage_t;
++	bool cac_enabled;
++	bool bapm_enable;
++	/* smc offsets */
++	u32 sram_end;
++	u32 dpm_table_start;
++	u32 soft_regs_start;
++	/* dpm SMU tables */
++	u8 graphics_dpm_level_count;
++	u8 uvd_level_count;
++	u8 vce_level_count;
++	u8 acp_level_count;
++	u8 samu_level_count;
++	u16 fps_high_t;
++	SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
++	SMU7_Fusion_ACPILevel acpi_level;
++	SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
++	SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
++	SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
++	SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
++	u8 uvd_boot_level;
++	u8 vce_boot_level;
++	u8 acp_boot_level;
++	u8 samu_boot_level;
++	u8 uvd_interval;
++	u8 vce_interval;
++	u8 acp_interval;
++	u8 samu_interval;
++	u8 graphics_boot_level;
++	u8 graphics_interval;
++	u8 graphics_therm_throttle_enable;
++	u8 graphics_voltage_change_enable;
++	u8 graphics_clk_slow_enable;
++	u8 graphics_clk_slow_divider;
++	u8 fps_low_t;
++	u32 low_sclk_interrupt_t;
++	bool uvd_power_gated;
++	bool vce_power_gated;
++	bool acp_power_gated;
++	bool samu_power_gated;
++	bool nb_dpm_enabled;
++	/* flags */
++	bool enable_didt;
++	bool enable_dpm;
++	bool enable_auto_thermal_throttling;
++	bool enable_nb_dpm;
++	/* caps */
++	bool caps_cac;
++	bool caps_power_containment;
++	bool caps_sq_ramping;
++	bool caps_db_ramping;
++	bool caps_td_ramping;
++	bool caps_tcp_ramping;
++	bool caps_sclk_throttle_low_notification;
++	bool caps_fps;
++	bool caps_uvd_dpm;
++	bool caps_uvd_pg;
++	bool caps_vce_pg;
++	bool caps_samu_pg;
++	bool caps_acp_pg;
++	bool caps_stable_p_state;
++	bool caps_enable_dfs_bypass;
++	bool caps_sclk_ds;
++	struct amdgpu_ps current_rps;
++	struct kv_ps current_ps;
++	struct amdgpu_ps requested_rps;
++	struct kv_ps requested_ps;
++};
++
++/* XXX are these ok? */
++#define KV_TEMP_RANGE_MIN (90 * 1000)
++#define KV_TEMP_RANGE_MAX (120 * 1000)
++
++/* kv_smc.c */
++int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id);
++int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);
++int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++				      PPSMC_Msg msg, u32 parameter);
++int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
++			   u32 *value, u32 limit);
++int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable);
++int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable);
++int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev,
++			 u32 smc_start_address,
++			 const u8 *src, u32 byte_count, u32 limit);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/kv_smc.c b/drivers/gpu/drm/amd/amdgpu/kv_smc.c
+new file mode 100644
+index 0000000..e6b7b42
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/kv_smc.c
+@@ -0,0 +1,219 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++
++#include "drmP.h"
++#include "amdgpu.h"
++#include "cikd.h"
++#include "kv_dpm.h"
++
++#include "smu/smu_7_0_0_d.h"
++#include "smu/smu_7_0_0_sh_mask.h"
++
++int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id)
++{
++	u32 i;
++	u32 tmp = 0;
++
++	WREG32(mmSMC_MESSAGE_0, id & SMC_MESSAGE_0__SMC_MSG_MASK);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0)
++			break;
++		udelay(1);
++	}
++	tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
++
++	if (tmp != 1) {
++		if (tmp == 0xFF)
++			return -EINVAL;
++		else if (tmp == 0xFE)
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask)
++{
++	int ret;
++
++	ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SCLKDPM_GetEnabledMask);
++
++	if (ret == 0)
++		*enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);
++
++	return ret;
++}
++
++int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++				      PPSMC_Msg msg, u32 parameter)
++{
++
++	WREG32(mmSMC_MSG_ARG_0, parameter);
++
++	return amdgpu_kv_notify_message_to_smu(adev, msg);
++}
++
++static int kv_set_smc_sram_address(struct amdgpu_device *adev,
++				   u32 smc_address, u32 limit)
++{
++	if (smc_address & 3)
++		return -EINVAL;
++	if ((smc_address + 3) > limit)
++		return -EINVAL;
++
++	WREG32(mmSMC_IND_INDEX_0, smc_address);
++	WREG32_P(mmSMC_IND_ACCESS_CNTL, 0,
++			~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
++
++	return 0;
++}
++
++int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
++			   u32 *value, u32 limit)
++{
++	int ret;
++
++	ret = kv_set_smc_sram_address(adev, smc_address, limit);
++	if (ret)
++		return ret;
++
++	*value = RREG32(mmSMC_IND_DATA_0);
++	return 0;
++}
++
++int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable)
++{
++	if (enable)
++		return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DPM_Enable);
++	else
++		return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DPM_Disable);
++}
++
++int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable)
++{
++	if (enable)
++		return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableBAPM);
++	else
++		return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableBAPM);
++}
++
++int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev,
++			 u32 smc_start_address,
++			 const u8 *src, u32 byte_count, u32 limit)
++{
++	int ret;
++	u32 data, original_data, addr, extra_shift, t_byte, count, mask;
++
++	if ((smc_start_address + byte_count) > limit)
++		return -EINVAL;
++
++	addr = smc_start_address;
++	t_byte = addr & 3;
++
++	/* RMW for the initial bytes */
++	if  (t_byte != 0) {
++		addr -= t_byte;
++
++		ret = kv_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			return ret;
++
++		original_data = RREG32(mmSMC_IND_DATA_0);
++
++		data = 0;
++		mask = 0;
++		count = 4;
++		while (count > 0) {
++			if (t_byte > 0) {
++				mask = (mask << 8) | 0xff;
++				t_byte--;
++			} else if (byte_count > 0) {
++				data = (data << 8) + *src++;
++				byte_count--;
++				mask <<= 8;
++			} else {
++				data <<= 8;
++				mask = (mask << 8) | 0xff;
++			}
++			count--;
++		}
++
++		data |= original_data & mask;
++
++		ret = kv_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			return ret;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++
++		addr += 4;
++	}
++
++	while (byte_count >= 4) {
++		/* SMC address space is BE */
++		data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
++
++		ret = kv_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			return ret;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++
++		src += 4;
++		byte_count -= 4;
++		addr += 4;
++	}
++
++	/* RMW for the final bytes */
++	if (byte_count > 0) {
++		data = 0;
++
++		ret = kv_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			return ret;
++
++		original_data = RREG32(mmSMC_IND_DATA_0);
++
++		extra_shift = 8 * (4 - byte_count);
++
++		while (byte_count > 0) {
++			/* SMC address space is BE */
++			data = (data << 8) + *src++;
++			byte_count--;
++		}
++
++		data <<= extra_shift;
++
++		data |= (original_data & ~((~0UL) << extra_shift));
++
++		ret = kv_set_smc_sram_address(adev, addr, limit);
++		if (ret)
++			return ret;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++	}
++	return 0;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu7.h b/drivers/gpu/drm/amd/amdgpu/smu7.h
+new file mode 100644
+index 0000000..75a380a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu7.h
+@@ -0,0 +1,170 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU7_H
++#define SMU7_H
++
++#pragma pack(push, 1)
++
++#define SMU7_CONTEXT_ID_SMC        1
++#define SMU7_CONTEXT_ID_VBIOS      2
++
++
++#define SMU7_CONTEXT_ID_SMC        1
++#define SMU7_CONTEXT_ID_VBIOS      2
++
++#define SMU7_MAX_LEVELS_VDDC            8
++#define SMU7_MAX_LEVELS_VDDCI           4
++#define SMU7_MAX_LEVELS_MVDD            4
++#define SMU7_MAX_LEVELS_VDDNB           8
++
++#define SMU7_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
++#define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
++#define SMU7_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
++#define SMU7_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
++#define SMU7_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
++#define SMU7_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
++#define SMU7_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
++#define SMU7_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
++#define SMU7_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
++
++#define DPM_NO_LIMIT 0
++#define DPM_NO_UP 1
++#define DPM_GO_DOWN 2
++#define DPM_GO_UP 3
++
++#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
++#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
++
++#define GPIO_CLAMP_MODE_VRHOT      1
++#define GPIO_CLAMP_MODE_THERM      2
++#define GPIO_CLAMP_MODE_DC         4
++
++#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
++#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
++#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
++#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
++#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
++#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
++#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
++#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
++#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
++#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
++#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
++#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
++#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
++#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
++#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
++#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
++#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
++#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
++#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
++#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
++
++
++struct SMU7_PIDController
++{
++    uint32_t Ki;
++    int32_t LFWindupUL;
++    int32_t LFWindupLL;
++    uint32_t StatePrecision;
++    uint32_t LfPrecision;
++    uint32_t LfOffset;
++    uint32_t MaxState;
++    uint32_t MaxLfFraction;
++    uint32_t StateShift;
++};
++
++typedef struct SMU7_PIDController SMU7_PIDController;
++
++// -------------------------------------------------------------------------------------------------------------------------
++#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
++
++#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
++#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
++#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
++#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
++#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
++#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
++#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
++#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
++#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
++
++#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
++#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
++#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
++#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
++#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
++#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
++
++struct SMU7_Firmware_Header
++{
++    uint32_t Digest[5];
++    uint32_t Version;
++    uint32_t HeaderSize;
++    uint32_t Flags;
++    uint32_t EntryPoint;
++    uint32_t CodeSize;
++    uint32_t ImageSize;
++
++    uint32_t Rtos;
++    uint32_t SoftRegisters;
++    uint32_t DpmTable;
++    uint32_t FanTable;
++    uint32_t CacConfigTable;
++    uint32_t CacStatusTable;
++
++    uint32_t mcRegisterTable;
++
++    uint32_t mcArbDramTimingTable;
++
++    uint32_t PmFuseTable;
++    uint32_t Globals;
++    uint32_t Reserved[42];
++    uint32_t Signature;
++};
++
++typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
++
++#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
++
++enum  DisplayConfig {
++    PowerDown = 1,
++    DP54x4,
++    DP54x2,
++    DP54x1,
++    DP27x4,
++    DP27x2,
++    DP27x1,
++    HDMI297,
++    HDMI162,
++    LVDS,
++    DP324x4,
++    DP324x2,
++    DP324x1
++};
++
++#pragma pack(pop)
++
++#endif
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu7_discrete.h b/drivers/gpu/drm/amd/amdgpu/smu7_discrete.h
+new file mode 100644
+index 0000000..0b0b404
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu7_discrete.h
+@@ -0,0 +1,514 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU7_DISCRETE_H
++#define SMU7_DISCRETE_H
++
++#include "smu7.h"
++
++#pragma pack(push, 1)
++
++#define SMU7_DTE_ITERATIONS 5
++#define SMU7_DTE_SOURCES 3
++#define SMU7_DTE_SINKS 1
++#define SMU7_NUM_CPU_TES 0
++#define SMU7_NUM_GPU_TES 1
++#define SMU7_NUM_NON_TES 2
++
++struct SMU7_SoftRegisters
++{
++    uint32_t        RefClockFrequency;
++    uint32_t        PmTimerP;
++    uint32_t        FeatureEnables;
++    uint32_t        PreVBlankGap;
++    uint32_t        VBlankTimeout;
++    uint32_t        TrainTimeGap;
++
++    uint32_t        MvddSwitchTime;
++    uint32_t        LongestAcpiTrainTime;
++    uint32_t        AcpiDelay;
++    uint32_t        G5TrainTime;
++    uint32_t        DelayMpllPwron;
++    uint32_t        VoltageChangeTimeout;
++    uint32_t        HandshakeDisables;
++
++    uint8_t         DisplayPhy1Config;
++    uint8_t         DisplayPhy2Config;
++    uint8_t         DisplayPhy3Config;
++    uint8_t         DisplayPhy4Config;
++
++    uint8_t         DisplayPhy5Config;
++    uint8_t         DisplayPhy6Config;
++    uint8_t         DisplayPhy7Config;
++    uint8_t         DisplayPhy8Config;
++
++    uint32_t        AverageGraphicsA;
++    uint32_t        AverageMemoryA;
++    uint32_t        AverageGioA;
++
++    uint8_t         SClkDpmEnabledLevels;
++    uint8_t         MClkDpmEnabledLevels;
++    uint8_t         LClkDpmEnabledLevels;
++    uint8_t         PCIeDpmEnabledLevels;
++
++    uint8_t         UVDDpmEnabledLevels;
++    uint8_t         SAMUDpmEnabledLevels;
++    uint8_t         ACPDpmEnabledLevels;
++    uint8_t         VCEDpmEnabledLevels;
++
++    uint32_t        DRAM_LOG_ADDR_H;
++    uint32_t        DRAM_LOG_ADDR_L;
++    uint32_t        DRAM_LOG_PHY_ADDR_H;
++    uint32_t        DRAM_LOG_PHY_ADDR_L;
++    uint32_t        DRAM_LOG_BUFF_SIZE;
++    uint32_t        UlvEnterC;
++    uint32_t        UlvTime;
++    uint32_t        Reserved[3];
++
++};
++
++typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
++
++struct SMU7_Discrete_VoltageLevel
++{
++    uint16_t    Voltage;
++    uint16_t    StdVoltageHiSidd;
++    uint16_t    StdVoltageLoSidd;
++    uint8_t     Smio;
++    uint8_t     padding;
++};
++
++typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
++
++struct SMU7_Discrete_GraphicsLevel
++{
++    uint32_t    Flags;
++    uint32_t    MinVddc;
++    uint32_t    MinVddcPhases;
++
++    uint32_t    SclkFrequency;
++
++    uint8_t     padding1[2];
++    uint16_t    ActivityLevel;
++
++    uint32_t    CgSpllFuncCntl3;
++    uint32_t    CgSpllFuncCntl4;
++    uint32_t    SpllSpreadSpectrum;
++    uint32_t    SpllSpreadSpectrum2;
++    uint32_t    CcPwrDynRm;
++    uint32_t    CcPwrDynRm1;
++    uint8_t     SclkDid;
++    uint8_t     DisplayWatermark;
++    uint8_t     EnabledForActivity;
++    uint8_t     EnabledForThrottle;
++    uint8_t     UpH;
++    uint8_t     DownH;
++    uint8_t     VoltageDownH;
++    uint8_t     PowerThrottle;
++    uint8_t     DeepSleepDivId;
++    uint8_t     padding[3];
++};
++
++typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
++
++struct SMU7_Discrete_ACPILevel
++{
++    uint32_t    Flags;
++    uint32_t    MinVddc;
++    uint32_t    MinVddcPhases;
++    uint32_t    SclkFrequency;
++    uint8_t     SclkDid;
++    uint8_t     DisplayWatermark;
++    uint8_t     DeepSleepDivId;
++    uint8_t     padding;
++    uint32_t    CgSpllFuncCntl;
++    uint32_t    CgSpllFuncCntl2;
++    uint32_t    CgSpllFuncCntl3;
++    uint32_t    CgSpllFuncCntl4;
++    uint32_t    SpllSpreadSpectrum;
++    uint32_t    SpllSpreadSpectrum2;
++    uint32_t    CcPwrDynRm;
++    uint32_t    CcPwrDynRm1;
++};
++
++typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
++
++struct SMU7_Discrete_Ulv
++{
++    uint32_t    CcPwrDynRm;
++    uint32_t    CcPwrDynRm1;
++    uint16_t    VddcOffset;
++    uint8_t     VddcOffsetVid;
++    uint8_t     VddcPhase;
++    uint32_t    Reserved;
++};
++
++typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
++
++struct SMU7_Discrete_MemoryLevel
++{
++    uint32_t    MinVddc;
++    uint32_t    MinVddcPhases;
++    uint32_t    MinVddci;
++    uint32_t    MinMvdd;
++
++    uint32_t    MclkFrequency;
++
++    uint8_t     EdcReadEnable;
++    uint8_t     EdcWriteEnable;
++    uint8_t     RttEnable;
++    uint8_t     StutterEnable;
++
++    uint8_t     StrobeEnable;
++    uint8_t     StrobeRatio;
++    uint8_t     EnabledForThrottle;
++    uint8_t     EnabledForActivity;
++
++    uint8_t     UpH;
++    uint8_t     DownH;
++    uint8_t     VoltageDownH;
++    uint8_t     padding;
++
++    uint16_t    ActivityLevel;
++    uint8_t     DisplayWatermark;
++    uint8_t     padding1;
++
++    uint32_t    MpllFuncCntl;
++    uint32_t    MpllFuncCntl_1;
++    uint32_t    MpllFuncCntl_2;
++    uint32_t    MpllAdFuncCntl;
++    uint32_t    MpllDqFuncCntl;
++    uint32_t    MclkPwrmgtCntl;
++    uint32_t    DllCntl;
++    uint32_t    MpllSs1;
++    uint32_t    MpllSs2;
++};
++
++typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
++
++struct SMU7_Discrete_LinkLevel
++{
++    uint8_t     PcieGenSpeed;
++    uint8_t     PcieLaneCount;
++    uint8_t     EnabledForActivity;
++    uint8_t     Padding;
++    uint32_t    DownT;
++    uint32_t    UpT;
++    uint32_t    Reserved;
++};
++
++typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
++
++
++struct SMU7_Discrete_MCArbDramTimingTableEntry
++{
++    uint32_t McArbDramTiming;
++    uint32_t McArbDramTiming2;
++    uint8_t  McArbBurstTime;
++    uint8_t  padding[3];
++};
++
++typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
++
++struct SMU7_Discrete_MCArbDramTimingTable
++{
++    SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
++};
++
++typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
++
++struct SMU7_Discrete_UvdLevel
++{
++    uint32_t VclkFrequency;
++    uint32_t DclkFrequency;
++    uint16_t MinVddc;
++    uint8_t  MinVddcPhases;
++    uint8_t  VclkDivider;
++    uint8_t  DclkDivider;
++    uint8_t  padding[3];
++};
++
++typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
++
++struct SMU7_Discrete_ExtClkLevel
++{
++    uint32_t Frequency;
++    uint16_t MinVoltage;
++    uint8_t  MinPhases;
++    uint8_t  Divider;
++};
++
++typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
++
++struct SMU7_Discrete_StateInfo
++{
++    uint32_t SclkFrequency;
++    uint32_t MclkFrequency;
++    uint32_t VclkFrequency;
++    uint32_t DclkFrequency;
++    uint32_t SamclkFrequency;
++    uint32_t AclkFrequency;
++    uint32_t EclkFrequency;
++    uint16_t MvddVoltage;
++    uint16_t padding16;
++    uint8_t  DisplayWatermark;
++    uint8_t  McArbIndex;
++    uint8_t  McRegIndex;
++    uint8_t  SeqIndex;
++    uint8_t  SclkDid;
++    int8_t   SclkIndex;
++    int8_t   MclkIndex;
++    uint8_t  PCIeGen;
++
++};
++
++typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
++
++
++struct SMU7_Discrete_DpmTable
++{
++    SMU7_PIDController                  GraphicsPIDController;
++    SMU7_PIDController                  MemoryPIDController;
++    SMU7_PIDController                  LinkPIDController;
++
++    uint32_t                            SystemFlags;
++
++
++    uint32_t                            SmioMaskVddcVid;
++    uint32_t                            SmioMaskVddcPhase;
++    uint32_t                            SmioMaskVddciVid;
++    uint32_t                            SmioMaskMvddVid;
++
++    uint32_t                            VddcLevelCount;
++    uint32_t                            VddciLevelCount;
++    uint32_t                            MvddLevelCount;
++
++    SMU7_Discrete_VoltageLevel          VddcLevel               [SMU7_MAX_LEVELS_VDDC];
++//    SMU7_Discrete_VoltageLevel          VddcStandardReference   [SMU7_MAX_LEVELS_VDDC];
++    SMU7_Discrete_VoltageLevel          VddciLevel              [SMU7_MAX_LEVELS_VDDCI];
++    SMU7_Discrete_VoltageLevel          MvddLevel               [SMU7_MAX_LEVELS_MVDD];
++
++    uint8_t                             GraphicsDpmLevelCount;
++    uint8_t                             MemoryDpmLevelCount;
++    uint8_t                             LinkLevelCount;
++    uint8_t                             UvdLevelCount;
++    uint8_t                             VceLevelCount;
++    uint8_t                             AcpLevelCount;
++    uint8_t                             SamuLevelCount;
++    uint8_t                             MasterDeepSleepControl;
++    uint32_t                            Reserved[5];
++//    uint32_t                            SamuDefaultLevel;
++
++    SMU7_Discrete_GraphicsLevel         GraphicsLevel           [SMU7_MAX_LEVELS_GRAPHICS];
++    SMU7_Discrete_MemoryLevel           MemoryACPILevel;
++    SMU7_Discrete_MemoryLevel           MemoryLevel             [SMU7_MAX_LEVELS_MEMORY];
++    SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
++    SMU7_Discrete_ACPILevel             ACPILevel;
++    SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
++    SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
++    SMU7_Discrete_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
++    SMU7_Discrete_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
++    SMU7_Discrete_Ulv                   Ulv;
++
++    uint32_t                            SclkStepSize;
++    uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
++
++    uint8_t                             UvdBootLevel;
++    uint8_t                             VceBootLevel;
++    uint8_t                             AcpBootLevel;
++    uint8_t                             SamuBootLevel;
++
++    uint8_t                             UVDInterval;
++    uint8_t                             VCEInterval;
++    uint8_t                             ACPInterval;
++    uint8_t                             SAMUInterval;
++
++    uint8_t                             GraphicsBootLevel;
++    uint8_t                             GraphicsVoltageChangeEnable;
++    uint8_t                             GraphicsThermThrottleEnable;
++    uint8_t                             GraphicsInterval;
++
++    uint8_t                             VoltageInterval;
++    uint8_t                             ThermalInterval;
++    uint16_t                            TemperatureLimitHigh;
++
++    uint16_t                            TemperatureLimitLow;
++    uint8_t                             MemoryBootLevel;
++    uint8_t                             MemoryVoltageChangeEnable;
++
++    uint8_t                             MemoryInterval;
++    uint8_t                             MemoryThermThrottleEnable;
++    uint16_t                            VddcVddciDelta;
++
++    uint16_t                            VoltageResponseTime;
++    uint16_t                            PhaseResponseTime;
++
++    uint8_t                             PCIeBootLinkLevel;
++    uint8_t                             PCIeGenInterval;
++    uint8_t                             DTEInterval;
++    uint8_t                             DTEMode;
++
++    uint8_t                             SVI2Enable;
++    uint8_t                             VRHotGpio;
++    uint8_t                             AcDcGpio;
++    uint8_t                             ThermGpio;
++
++    uint16_t                            PPM_PkgPwrLimit;
++    uint16_t                            PPM_TemperatureLimit;
++
++    uint16_t                            DefaultTdp;
++    uint16_t                            TargetTdp;
++
++    uint16_t                            FpsHighT;
++    uint16_t                            FpsLowT;
++
++    uint16_t                            BAPMTI_R  [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
++    uint16_t                            BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
++
++    uint8_t                             DTEAmbientTempBase;
++    uint8_t                             DTETjOffset;
++    uint8_t                             GpuTjMax;
++    uint8_t                             GpuTjHyst;
++
++    uint16_t                            BootVddc;
++    uint16_t                            BootVddci;
++
++    uint16_t                            BootMVdd;
++    uint16_t                            padding;
++
++    uint32_t                            BAPM_TEMP_GRADIENT;
++
++    uint32_t                            LowSclkInterruptT;
++};
++
++typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
++
++#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
++#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
++
++struct SMU7_Discrete_MCRegisterAddress
++{
++    uint16_t s0;
++    uint16_t s1;
++};
++
++typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
++
++struct SMU7_Discrete_MCRegisterSet
++{
++    uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
++};
++
++typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
++
++struct SMU7_Discrete_MCRegisters
++{
++    uint8_t                             last;
++    uint8_t                             reserved[3];
++    SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
++    SMU7_Discrete_MCRegisterSet         data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
++};
++
++typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
++
++struct SMU7_Discrete_FanTable
++{
++	uint16_t FdoMode;
++	int16_t  TempMin;
++	int16_t  TempMed;
++	int16_t  TempMax;
++	int16_t  Slope1;
++	int16_t  Slope2;
++	int16_t  FdoMin;
++	int16_t  HystUp;
++	int16_t  HystDown;
++	int16_t  HystSlope;
++	int16_t  TempRespLim;
++	int16_t  TempCurr;
++	int16_t  SlopeCurr;
++	int16_t  PwmCurr;
++	uint32_t RefreshPeriod;
++	int16_t  FdoMax;
++	uint8_t  TempSrc;
++	int8_t   Padding;
++};
++
++typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
++
++
++struct SMU7_Discrete_PmFuses {
++  // dw0-dw1
++  uint8_t BapmVddCVidHiSidd[8];
++
++  // dw2-dw3
++  uint8_t BapmVddCVidLoSidd[8];
++
++  // dw4-dw5
++  uint8_t VddCVid[8];
++
++  // dw6
++  uint8_t SviLoadLineEn;
++  uint8_t SviLoadLineVddC;
++  uint8_t SviLoadLineTrimVddC;
++  uint8_t SviLoadLineOffsetVddC;
++
++  // dw7
++  uint16_t TDC_VDDC_PkgLimit;
++  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
++  uint8_t TDC_MAWt;
++
++  // dw8
++  uint8_t TdcWaterfallCtl;
++  uint8_t LPMLTemperatureMin;
++  uint8_t LPMLTemperatureMax;
++  uint8_t Reserved;
++
++  // dw9-dw10
++  uint8_t BapmVddCVidHiSidd2[8];
++
++  // dw11-dw12
++  int16_t FuzzyFan_ErrorSetDelta;
++  int16_t FuzzyFan_ErrorRateSetDelta;
++  int16_t FuzzyFan_PwmSetDelta;
++  uint16_t CalcMeasPowerBlend;
++
++  // dw13-dw16
++  uint8_t GnbLPML[16];
++
++  // dw17
++  uint8_t GnbLPMLMaxVid;
++  uint8_t GnbLPMLMinVid;
++  uint8_t Reserved1[2];
++
++  // dw18
++  uint16_t BapmVddCBaseLeakageHiSidd;
++  uint16_t BapmVddCBaseLeakageLoSidd;
++};
++
++typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
++
++
++#pragma pack(pop)
++
++#endif
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu7_fusion.h b/drivers/gpu/drm/amd/amdgpu/smu7_fusion.h
+new file mode 100644
+index 0000000..78ada9f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu7_fusion.h
+@@ -0,0 +1,300 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU7_FUSION_H
++#define SMU7_FUSION_H
++
++#include "smu7.h"
++
++#pragma pack(push, 1)
++
++#define SMU7_DTE_ITERATIONS 5
++#define SMU7_DTE_SOURCES 5
++#define SMU7_DTE_SINKS 3
++#define SMU7_NUM_CPU_TES 2
++#define SMU7_NUM_GPU_TES 1
++#define SMU7_NUM_NON_TES 2
++
++// All 'soft registers' should be uint32_t.
++struct SMU7_SoftRegisters
++{
++    uint32_t        RefClockFrequency;
++    uint32_t        PmTimerP;
++    uint32_t        FeatureEnables;
++    uint32_t        HandshakeDisables;
++
++    uint8_t         DisplayPhy1Config;
++    uint8_t         DisplayPhy2Config;
++    uint8_t         DisplayPhy3Config;
++    uint8_t         DisplayPhy4Config;
++
++    uint8_t         DisplayPhy5Config;
++    uint8_t         DisplayPhy6Config;
++    uint8_t         DisplayPhy7Config;
++    uint8_t         DisplayPhy8Config;
++
++    uint32_t        AverageGraphicsA;
++    uint32_t        AverageMemoryA;
++    uint32_t        AverageGioA;
++
++    uint8_t         SClkDpmEnabledLevels;
++    uint8_t         MClkDpmEnabledLevels;
++    uint8_t         LClkDpmEnabledLevels;
++    uint8_t         PCIeDpmEnabledLevels;
++
++    uint8_t         UVDDpmEnabledLevels;
++    uint8_t         SAMUDpmEnabledLevels;
++    uint8_t         ACPDpmEnabledLevels;
++    uint8_t         VCEDpmEnabledLevels;
++
++    uint32_t        DRAM_LOG_ADDR_H;
++    uint32_t        DRAM_LOG_ADDR_L;
++    uint32_t        DRAM_LOG_PHY_ADDR_H;
++    uint32_t        DRAM_LOG_PHY_ADDR_L;
++    uint32_t        DRAM_LOG_BUFF_SIZE;
++    uint32_t        UlvEnterC;
++    uint32_t        UlvTime;
++    uint32_t        Reserved[3];
++
++};
++
++typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
++
++struct SMU7_Fusion_GraphicsLevel
++{
++    uint32_t    MinVddNb;
++
++    uint32_t    SclkFrequency;
++
++    uint8_t     Vid;
++    uint8_t     VidOffset;
++    uint16_t    AT;
++
++    uint8_t     PowerThrottle;
++    uint8_t     GnbSlow;
++    uint8_t     ForceNbPs1;
++    uint8_t     SclkDid;
++
++    uint8_t     DisplayWatermark;
++    uint8_t     EnabledForActivity;
++    uint8_t     EnabledForThrottle;
++    uint8_t     UpH;
++
++    uint8_t     DownH;
++    uint8_t     VoltageDownH;
++    uint8_t     DeepSleepDivId;
++
++    uint8_t     ClkBypassCntl;
++
++    uint32_t    reserved;
++};
++
++typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
++
++struct SMU7_Fusion_GIOLevel
++{
++    uint8_t     EnabledForActivity;
++    uint8_t     LclkDid;
++    uint8_t     Vid;
++    uint8_t     VoltageDownH;
++
++    uint32_t    MinVddNb;
++
++    uint16_t    ResidencyCounter;
++    uint8_t     UpH;
++    uint8_t     DownH;
++
++    uint32_t    LclkFrequency;
++
++    uint8_t     ActivityLevel;
++    uint8_t     EnabledForThrottle;
++
++    uint8_t     ClkBypassCntl;
++
++    uint8_t     padding;
++};
++
++typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
++
++// UVD VCLK/DCLK state (level) definition.
++struct SMU7_Fusion_UvdLevel
++{
++    uint32_t VclkFrequency;
++    uint32_t DclkFrequency;
++    uint16_t MinVddNb;
++    uint8_t  VclkDivider;
++    uint8_t  DclkDivider;
++
++    uint8_t     VClkBypassCntl;
++    uint8_t     DClkBypassCntl;
++
++    uint8_t     padding[2];
++
++};
++
++typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
++
++// Clocks for other external blocks (VCE, ACP, SAMU).
++struct SMU7_Fusion_ExtClkLevel
++{
++    uint32_t Frequency;
++    uint16_t MinVoltage;
++    uint8_t  Divider;
++    uint8_t  ClkBypassCntl;
++
++    uint32_t Reserved;
++};
++typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
++
++struct SMU7_Fusion_ACPILevel
++{
++    uint32_t    Flags;
++    uint32_t    MinVddNb;
++    uint32_t    SclkFrequency;
++    uint8_t     SclkDid;
++    uint8_t     GnbSlow;
++    uint8_t     ForceNbPs1;
++    uint8_t     DisplayWatermark;
++    uint8_t     DeepSleepDivId;
++    uint8_t     padding[3];
++};
++
++typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
++
++struct SMU7_Fusion_NbDpm
++{
++    uint8_t DpmXNbPsHi;
++    uint8_t DpmXNbPsLo;
++    uint8_t Dpm0PgNbPsHi;
++    uint8_t Dpm0PgNbPsLo;
++    uint8_t EnablePsi1;
++    uint8_t SkipDPM0;
++    uint8_t SkipPG;
++    uint8_t Hysteresis;
++    uint8_t EnableDpmPstatePoll;
++    uint8_t padding[3];
++};
++
++typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
++
++struct SMU7_Fusion_StateInfo
++{
++    uint32_t SclkFrequency;
++    uint32_t LclkFrequency;
++    uint32_t VclkFrequency;
++    uint32_t DclkFrequency;
++    uint32_t SamclkFrequency;
++    uint32_t AclkFrequency;
++    uint32_t EclkFrequency;
++    uint8_t  DisplayWatermark;
++    uint8_t  McArbIndex;
++    int8_t   SclkIndex;
++    int8_t   MclkIndex;
++};
++
++typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
++
++struct SMU7_Fusion_DpmTable
++{
++    uint32_t                            SystemFlags;
++
++    SMU7_PIDController                  GraphicsPIDController;
++    SMU7_PIDController                  GioPIDController;
++
++    uint8_t                            GraphicsDpmLevelCount;
++    uint8_t                            GIOLevelCount;
++    uint8_t                            UvdLevelCount;
++    uint8_t                            VceLevelCount;
++
++    uint8_t                            AcpLevelCount;
++    uint8_t                            SamuLevelCount;
++    uint16_t                           FpsHighT;
++
++    SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
++    SMU7_Fusion_ACPILevel             ACPILevel;
++    SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
++    SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
++    SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
++    SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
++
++    uint8_t                           UvdBootLevel;
++    uint8_t                           VceBootLevel;
++    uint8_t                           AcpBootLevel;
++    uint8_t                           SamuBootLevel;
++    uint8_t                           UVDInterval;
++    uint8_t                           VCEInterval;
++    uint8_t                           ACPInterval;
++    uint8_t                           SAMUInterval;
++
++    uint8_t                           GraphicsBootLevel;
++    uint8_t                           GraphicsInterval;
++    uint8_t                           GraphicsThermThrottleEnable;
++    uint8_t                           GraphicsVoltageChangeEnable;
++
++    uint8_t                           GraphicsClkSlowEnable;
++    uint8_t                           GraphicsClkSlowDivider;
++    uint16_t                          FpsLowT;
++
++    uint32_t                          DisplayCac;
++    uint32_t                          LowSclkInterruptT;
++
++    uint32_t                          DRAM_LOG_ADDR_H;
++    uint32_t                          DRAM_LOG_ADDR_L;
++    uint32_t                          DRAM_LOG_PHY_ADDR_H;
++    uint32_t                          DRAM_LOG_PHY_ADDR_L;
++    uint32_t                          DRAM_LOG_BUFF_SIZE;
++
++};
++
++struct SMU7_Fusion_GIODpmTable
++{
++
++    SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];
++
++    SMU7_PIDController                GioPIDController;
++
++    uint32_t                          GIOLevelCount;
++
++    uint8_t                           Enable;
++    uint8_t                           GIOVoltageChangeEnable;
++    uint8_t                           GIOBootLevel;
++    uint8_t                           padding;
++    uint8_t                           padding1[2];
++    uint8_t                           TargetState;
++    uint8_t                           CurrenttState;
++    uint8_t                           ThrottleOnHtc;
++    uint8_t                           ThermThrottleStatus;
++    uint8_t                           ThermThrottleTempSelect;
++    uint8_t                           ThermThrottleEnable;
++    uint16_t                          TemperatureLimitHigh;
++    uint16_t                          TemperatureLimitLow;
++
++};
++
++typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
++typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
++
++#pragma pack(pop)
++
++#endif
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+new file mode 100644
+index 0000000..6e4cb60
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+@@ -0,0 +1,888 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_uvd.h"
++#include "cikd.h"
++
++#include "uvd/uvd_4_2_d.h"
++#include "uvd/uvd_4_2_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
++static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
++static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
++static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
++static int uvd_v4_2_start(struct amdgpu_device *adev);
++static void uvd_v4_2_stop(struct amdgpu_device *adev);
++
++/**
++ * uvd_v4_2_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32(mmUVD_RBC_RB_RPTR);
++}
++
++/**
++ * uvd_v4_2_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32(mmUVD_RBC_RB_WPTR);
++}
++
++/**
++ * uvd_v4_2_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
++}
++
++static int uvd_v4_2_early_init(struct amdgpu_device *adev)
++{
++	uvd_v4_2_set_ring_funcs(adev);
++	uvd_v4_2_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int uvd_v4_2_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* UVD TRAP */
++	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->uvd.ring;
++	sprintf(ring->name, "uvd");
++	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
++			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
++
++	return r;
++}
++
++static int uvd_v4_2_sw_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_uvd_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_sw_fini(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++/**
++ * uvd_v4_2_hw_init - start and test UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initialize the hardware, boot up the VCPU and do some testing
++ */
++static int uvd_v4_2_hw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	uint32_t tmp;
++	int r;
++
++	/* raise clocks while booting up the VCPU */
++	amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
++
++	r = uvd_v4_2_start(adev);
++	if (r)
++		goto done;
++
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		goto done;
++	}
++
++	r = amdgpu_ring_lock(ring, 10);
++	if (r) {
++		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
++		goto done;
++	}
++
++	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	/* Clear timeout status bits */
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
++	amdgpu_ring_write(ring, 0x8);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
++	amdgpu_ring_write(ring, 3);
++
++	amdgpu_ring_unlock_commit(ring);
++
++done:
++	/* lower clocks again */
++	amdgpu_asic_set_uvd_clocks(adev, 0, 0);
++
++	if (!r)
++		DRM_INFO("UVD initialized successfully.\n");
++
++	return r;
++}
++
++/**
++ * uvd_v4_2_hw_fini - stop the hardware block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the UVD block, mark ring as not ready any more
++ */
++static int uvd_v4_2_hw_fini(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++
++	uvd_v4_2_stop(adev);
++	ring->ready = false;
++
++	return 0;
++}
++
++static int uvd_v4_2_suspend(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = uvd_v4_2_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_suspend(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int uvd_v4_2_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_uvd_resume(adev);
++	if (r)
++		return r;
++
++	r = uvd_v4_2_hw_init(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++/**
++ * uvd_v4_2_start - start UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the UVD block
++ */
++static int uvd_v4_2_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	uint32_t rb_bufsz;
++	int i, j, r;
++
++	/* disable byte swapping */
++	u32 lmi_swap_cntl = 0;
++	u32 mp_swap_cntl = 0;
++
++	uvd_v4_2_mc_resume(adev);
++
++	/* disable clock gating */
++	WREG32(mmUVD_CGC_GATE, 0);
++
++	/* disable interupt */
++	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
++
++	/* Stall UMC and register bus before resetting VCPU */
++	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
++	mdelay(1);
++
++	/* put LMI, VCPU, RBC etc... into reset */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* take UVD block out of reset */
++	WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
++	mdelay(5);
++
++	/* initialize UVD memory controller */
++	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
++			     (1 << 21) | (1 << 9) | (1 << 20));
++
++#ifdef __BIG_ENDIAN
++	/* swap (8 in 32) RB and IB */
++	lmi_swap_cntl = 0xa;
++	mp_swap_cntl = 0;
++#endif
++	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
++	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
++
++	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
++	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
++	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
++	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
++	WREG32(mmUVD_MPC_SET_ALU, 0);
++	WREG32(mmUVD_MPC_SET_MUX, 0x88);
++
++	/* take all subblocks out of reset, except VCPU */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* enable VCPU clock */
++	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
++
++	/* enable UMC */
++	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
++
++	/* boot up the VCPU */
++	WREG32(mmUVD_SOFT_RESET, 0);
++	mdelay(10);
++
++	for (i = 0; i < 10; ++i) {
++		uint32_t status;
++		for (j = 0; j < 100; ++j) {
++			status = RREG32(mmUVD_STATUS);
++			if (status & 2)
++				break;
++			mdelay(10);
++		}
++		r = 0;
++		if (status & 2)
++			break;
++
++		DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
++		WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
++				~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++		mdelay(10);
++		WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++		mdelay(10);
++		r = -1;
++	}
++
++	if (r) {
++		DRM_ERROR("UVD not responding, giving up!!!\n");
++		return r;
++	}
++
++	/* enable interupt */
++	WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
++
++	/* force RBC into idle state */
++	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
++
++	/* Set the write pointer delay */
++	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
++
++	/* programm the 4GB memory segment for rptr and ring buffer */
++	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
++				   (0x7 << 16) | (0x1 << 31));
++
++	/* Initialize the ring buffer's read and write pointers */
++	WREG32(mmUVD_RBC_RB_RPTR, 0x0);
++
++	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
++	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
++
++	/* set the ring address */
++	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
++
++	/* Set ring buffer size */
++	rb_bufsz = order_base_2(ring->ring_size);
++	rb_bufsz = (0x1 << 8) | rb_bufsz;
++	WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
++
++	return 0;
++}
++
++/**
++ * uvd_v4_2_stop - stop UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the UVD block
++ */
++static void uvd_v4_2_stop(struct amdgpu_device *adev)
++{
++	/* force RBC into idle state */
++	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
++
++	/* Stall UMC and register bus before resetting VCPU */
++	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
++	mdelay(1);
++
++	/* put VCPU into reset */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* disable VCPU clock */
++	WREG32(mmUVD_VCPU_CNTL, 0x0);
++
++	/* Unstall UMC and register bus */
++	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
++}
++
++/**
++ * uvd_v4_2_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				     bool write64bit)
++{
++	WARN_ON(write64bit);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
++	amdgpu_ring_write(ring, seq);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
++	amdgpu_ring_write(ring, addr & 0xffffffff);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
++	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
++	amdgpu_ring_write(ring, 2);
++}
++
++/**
++ * uvd_v4_2_ring_emit_semaphore - emit semaphore command
++ *
++ * @ring: amdgpu_ring pointer
++ * @semaphore: semaphore to emit commands for
++ * @emit_wait: true if we should emit a wait command
++ *
++ * Emit a semaphore command (either wait or signal) to the UVD ring.
++ */
++static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring,
++					 struct amdgpu_semaphore *semaphore,
++					 bool emit_wait)
++{
++	uint64_t addr = semaphore->gpu_addr;
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
++	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
++	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
++	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
++
++	return true;
++}
++
++/**
++ * uvd_v4_2_ring_test_ring - register write test
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Test if we can successfully write to the context register
++ */
++static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
++	r = amdgpu_ring_lock(ring, 3);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
++			  ring->idx, r);
++		return r;
++	}
++	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmUVD_CONTEXT_ID);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n",
++			 ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
++			  ring->idx, tmp);
++		r = -EINVAL;
++	}
++	return r;
++}
++
++/**
++ * uvd_v4_2_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer
++ */
++static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
++				  struct amdgpu_ib *ib)
++{
++	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
++	amdgpu_ring_write(ring, ib->gpu_addr);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
++	amdgpu_ring_write(ring, ib->length_dw);
++}
++
++/**
++ * uvd_v4_2_ring_test_ib - test ib execution
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Test if we can successfully execute an IB
++ */
++static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_fence *fence = NULL;
++	int r;
++
++	r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
++		return r;
++	}
++
++	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_fence_wait(fence, false);
++	if (r) {
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		goto error;
++	}
++	DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
++error:
++	amdgpu_fence_unref(&fence);
++	amdgpu_asic_set_uvd_clocks(adev, 0, 0);
++	return r;
++}
++
++/**
++ * uvd_v4_2_mc_resume - memory controller programming
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Let the UVD memory controller know it's offsets
++ */
++static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
++{
++	uint64_t addr;
++	uint32_t size;
++
++	/* programm the VCPU memory controller bits 0-27 */
++	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
++	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
++	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
++
++	addr += size;
++	size = AMDGPU_UVD_STACK_SIZE >> 3;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
++	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
++
++	addr += size;
++	size = AMDGPU_UVD_HEAP_SIZE >> 3;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
++	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
++
++	/* bits 28-31 */
++	addr = (adev->uvd.gpu_addr >> 28) & 0xF;
++	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
++
++	/* bits 32-39 */
++	addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
++	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
++
++	uvd_v4_2_init_cg(adev);
++}
++
++static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
++				 bool enable)
++{
++	u32 orig, data;
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) {
++		data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
++		data = 0xfff;
++		WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
++
++		orig = data = RREG32(mmUVD_CGC_CTRL);
++		data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
++		if (orig != data)
++			WREG32(mmUVD_CGC_CTRL, data);
++	} else {
++		data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
++		data &= ~0xfff;
++		WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
++
++		orig = data = RREG32(mmUVD_CGC_CTRL);
++		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
++		if (orig != data)
++			WREG32(mmUVD_CGC_CTRL, data);
++	}
++}
++
++static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
++			     bool sw_mode)
++{
++	u32 tmp, tmp2;
++
++	tmp = RREG32(mmUVD_CGC_CTRL);
++	tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
++	tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
++		(1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
++		(4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
++
++	if (sw_mode) {
++		tmp &= ~0x7ffff800;
++		tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
++			UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
++			(7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
++	} else {
++		tmp |= 0x7ffff800;
++		tmp2 = 0;
++	}
++
++	WREG32(mmUVD_CGC_CTRL, tmp);
++	WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
++}
++
++static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
++{
++	bool hw_mode = true;
++
++	if (hw_mode) {
++		uvd_v4_2_set_dcm(adev, false);
++	} else {
++		u32 tmp = RREG32(mmUVD_CGC_CTRL);
++		tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
++		WREG32(mmUVD_CGC_CTRL, tmp);
++	}
++}
++
++static bool uvd_v4_2_is_idle(struct amdgpu_device *adev)
++{
++	return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
++}
++
++static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
++			return 0;
++	}
++	return -ETIMEDOUT;
++}
++
++static int uvd_v4_2_soft_reset(struct amdgpu_device *adev)
++{
++	uvd_v4_2_stop(adev);
++
++	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
++			~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
++	mdelay(5);
++
++	return uvd_v4_2_start(adev);
++}
++
++static void uvd_v4_2_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "UVD 4.2 registers\n");
++	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
++		 RREG32(mmUVD_SEMA_ADDR_LOW));
++	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
++		 RREG32(mmUVD_SEMA_ADDR_HIGH));
++	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
++		 RREG32(mmUVD_SEMA_CMD));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_CMD));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_DATA0));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_DATA1));
++	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
++		 RREG32(mmUVD_ENGINE_CNTL));
++	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_CNTL));
++	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
++		 RREG32(mmUVD_LMI_EXT40_ADDR));
++	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
++		 RREG32(mmUVD_CTX_INDEX));
++	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
++		 RREG32(mmUVD_CTX_DATA));
++	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
++		 RREG32(mmUVD_CGC_GATE));
++	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
++		 RREG32(mmUVD_CGC_CTRL));
++	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
++		 RREG32(mmUVD_LMI_CTRL2));
++	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
++		 RREG32(mmUVD_MASTINT_EN));
++	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
++		 RREG32(mmUVD_LMI_ADDR_EXT));
++	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
++		 RREG32(mmUVD_LMI_CTRL));
++	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmUVD_LMI_SWAP_CNTL));
++	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmUVD_MP_SWAP_CNTL));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXA0));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXA1));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXB0));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXB1));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUX));
++	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_ALU));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE0));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE1));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE2));
++	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CNTL));
++	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
++		 RREG32(mmUVD_SOFT_RESET));
++	dev_info(adev->dev, "  UVD_RBC_IB_BASE=0x%08X\n",
++		 RREG32(mmUVD_RBC_IB_BASE));
++	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
++		 RREG32(mmUVD_RBC_IB_SIZE));
++	dev_info(adev->dev, "  UVD_RBC_RB_BASE=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_BASE));
++	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_RPTR));
++	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_WPTR));
++	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
++	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_CNTL));
++	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
++		 RREG32(mmUVD_STATUS));
++	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
++		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
++	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
++		 RREG32(mmUVD_CONTEXT_ID));
++}
++
++static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	// TODO
++	return 0;
++}
++
++static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: UVD TRAP\n");
++	amdgpu_fence_process(&adev->uvd.ring);
++	return 0;
++}
++
++static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	bool gate = false;
++
++	if (state == AMDGPU_CG_STATE_GATE)
++		gate = true;
++
++	uvd_v4_2_enable_mgcg(adev, gate);
++
++	return 0;
++}
++
++static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	/* This doesn't actually powergate the UVD block.
++	 * That's done in the dpm code via the SMC.  This
++	 * just re-inits the block as necessary.  The actual
++	 * gating still happens in the dpm code.  We should
++	 * revisit this when there is a cleaner line between
++	 * the smc and the hw blocks
++	 */
++	if (state == AMDGPU_PG_STATE_GATE) {
++		uvd_v4_2_stop(adev);
++		return 0;
++	} else {
++		return uvd_v4_2_start(adev);
++	}
++}
++
++const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = {
++	.early_init = uvd_v4_2_early_init,
++	.late_init = NULL,
++	.sw_init = uvd_v4_2_sw_init,
++	.sw_fini = uvd_v4_2_sw_fini,
++	.hw_init = uvd_v4_2_hw_init,
++	.hw_fini = uvd_v4_2_hw_fini,
++	.suspend = uvd_v4_2_suspend,
++	.resume = uvd_v4_2_resume,
++	.is_idle = uvd_v4_2_is_idle,
++	.wait_for_idle = uvd_v4_2_wait_for_idle,
++	.soft_reset = uvd_v4_2_soft_reset,
++	.print_status = uvd_v4_2_print_status,
++	.set_clockgating_state = uvd_v4_2_set_clockgating_state,
++	.set_powergating_state = uvd_v4_2_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
++	.get_rptr = uvd_v4_2_ring_get_rptr,
++	.get_wptr = uvd_v4_2_ring_get_wptr,
++	.set_wptr = uvd_v4_2_ring_set_wptr,
++	.parse_cs = amdgpu_uvd_ring_parse_cs,
++	.emit_ib = uvd_v4_2_ring_emit_ib,
++	.emit_fence = uvd_v4_2_ring_emit_fence,
++	.emit_semaphore = uvd_v4_2_ring_emit_semaphore,
++	.test_ring = uvd_v4_2_ring_test_ring,
++	.test_ib = uvd_v4_2_ring_test_ib,
++	.is_lockup = amdgpu_ring_test_lockup,
++};
++
++static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
++	.set = uvd_v4_2_set_interrupt_state,
++	.process = uvd_v4_2_process_interrupt,
++};
++
++static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->uvd.irq.num_types = 1;
++	adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
+new file mode 100644
+index 0000000..323a6d8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __UVD_V4_2_H__
++#define __UVD_V4_2_H__
++
++extern const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+new file mode 100644
+index 0000000..b47c16d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+@@ -0,0 +1,642 @@
++/*
++ * Copyright 2013 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * Authors: Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_vce.h"
++#include "cikd.h"
++
++#include "vce/vce_2_0_d.h"
++#include "vce/vce_2_0_sh_mask.h"
++
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
++static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
++static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
++
++/**
++ * vce_v2_0_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vce.ring[0])
++		return RREG32(mmVCE_RB_RPTR);
++	else
++		return RREG32(mmVCE_RB_RPTR2);
++}
++
++/**
++ * vce_v2_0_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vce.ring[0])
++		return RREG32(mmVCE_RB_WPTR);
++	else
++		return RREG32(mmVCE_RB_WPTR2);
++}
++
++/**
++ * vce_v2_0_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vce.ring[0])
++		WREG32(mmVCE_RB_WPTR, ring->wptr);
++	else
++		WREG32(mmVCE_RB_WPTR2, ring->wptr);
++}
++
++/**
++ * vce_v2_0_start - start VCE block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the VCE block
++ */
++static int vce_v2_0_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int i, j, r;
++
++	vce_v2_0_mc_resume(adev);
++
++	/* set BUSY flag */
++	WREG32_P(mmVCE_STATUS, 1, ~1);
++
++	ring = &adev->vce.ring[0];
++	WREG32(mmVCE_RB_RPTR, ring->wptr);
++	WREG32(mmVCE_RB_WPTR, ring->wptr);
++	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
++	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
++	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
++
++	ring = &adev->vce.ring[1];
++	WREG32(mmVCE_RB_RPTR2, ring->wptr);
++	WREG32(mmVCE_RB_WPTR2, ring->wptr);
++	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
++	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
++	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
++
++	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
++
++	WREG32_P(mmVCE_SOFT_RESET,
++		 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
++		 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++
++	mdelay(100);
++
++	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++
++	for (i = 0; i < 10; ++i) {
++		uint32_t status;
++		for (j = 0; j < 100; ++j) {
++			status = RREG32(mmVCE_STATUS);
++			if (status & 2)
++				break;
++			mdelay(10);
++		}
++		r = 0;
++		if (status & 2)
++			break;
++
++		DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
++		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
++				~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++		mdelay(10);
++		WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++		mdelay(10);
++		r = -1;
++	}
++
++	/* clear BUSY flag */
++	WREG32_P(mmVCE_STATUS, 0, ~1);
++
++	if (r) {
++		DRM_ERROR("VCE not responding, giving up!!!\n");
++		return r;
++	}
++
++	return 0;
++}
++
++static int vce_v2_0_early_init(struct amdgpu_device *adev)
++{
++	vce_v2_0_set_ring_funcs(adev);
++	vce_v2_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int vce_v2_0_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* VCE */
++	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->vce.ring[0];
++	sprintf(ring->name, "vce0");
++	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
++			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
++	if (r)
++		return r;
++
++	ring = &adev->vce.ring[1];
++	sprintf(ring->name, "vce1");
++	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
++			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int vce_v2_0_sw_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_vce_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_sw_fini(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int vce_v2_0_hw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	r = vce_v2_0_start(adev);
++	if (r)
++		return r;
++
++	ring = &adev->vce.ring[0];
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		return r;
++	}
++
++	ring = &adev->vce.ring[1];
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		return r;
++	}
++
++	DRM_INFO("VCE initialized successfully.\n");
++
++	return 0;
++}
++
++static int vce_v2_0_hw_fini(struct amdgpu_device *adev)
++{
++	// TODO
++	return 0;
++}
++
++static int vce_v2_0_suspend(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = vce_v2_0_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_suspend(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int vce_v2_0_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_vce_resume(adev);
++	if (r)
++		return r;
++
++	r = vce_v2_0_hw_init(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
++{
++	u32 tmp;
++
++	if (gated) {
++		tmp = RREG32(mmVCE_CLOCK_GATING_B);
++		tmp |= 0xe70000;
++		WREG32(mmVCE_CLOCK_GATING_B, tmp);
++
++		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
++		tmp |= 0xff000000;
++		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
++
++		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
++		tmp &= ~0x3fc;
++		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
++
++		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
++    } else {
++		tmp = RREG32(mmVCE_CLOCK_GATING_B);
++		tmp |= 0xe7;
++		tmp &= ~0xe70000;
++		WREG32(mmVCE_CLOCK_GATING_B, tmp);
++
++		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
++		tmp |= 0x1fe000;
++		tmp &= ~0xff000000;
++		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
++
++		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
++		tmp |= 0x3fc;
++		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
++	}
++}
++
++static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
++{
++	u32 orig, tmp;
++
++	tmp = RREG32(mmVCE_CLOCK_GATING_B);
++	tmp &= ~0x00060006;
++	if (gated) {
++		tmp |= 0xe10000;
++	} else {
++		tmp |= 0xe1;
++		tmp &= ~0xe10000;
++	}
++	WREG32(mmVCE_CLOCK_GATING_B, tmp);
++
++	orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
++	tmp &= ~0x1fe000;
++	tmp &= ~0xff000000;
++	if (tmp != orig)
++		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
++
++	orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
++	tmp &= ~0x3fc;
++	if (tmp != orig)
++		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
++
++	if (gated)
++		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
++}
++
++static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
++{
++	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
++}
++
++static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
++{
++	bool sw_cg = false;
++
++	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) {
++		if (sw_cg)
++			vce_v2_0_set_sw_cg(adev, true);
++		else
++			vce_v2_0_set_dyn_cg(adev, true);
++	} else {
++		vce_v2_0_disable_cg(adev);
++
++		if (sw_cg)
++			vce_v2_0_set_sw_cg(adev, false);
++		else
++			vce_v2_0_set_dyn_cg(adev, false);
++	}
++}
++
++static void vce_v2_0_init_cg(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	tmp = RREG32(mmVCE_CLOCK_GATING_A);
++	tmp &= ~0xfff;
++	tmp |= ((0 << 0) | (4 << 4));
++	tmp |= 0x40000;
++	WREG32(mmVCE_CLOCK_GATING_A, tmp);
++
++	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
++	tmp &= ~0xfff;
++	tmp |= ((0 << 0) | (4 << 4));
++	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
++
++	tmp = RREG32(mmVCE_CLOCK_GATING_B);
++	tmp |= 0x10;
++	tmp &= ~0x100000;
++	WREG32(mmVCE_CLOCK_GATING_B, tmp);
++}
++
++static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
++{
++	uint64_t addr = adev->vce.gpu_addr;
++	uint32_t size;
++
++	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
++	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
++	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
++	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
++
++	WREG32(mmVCE_LMI_CTRL, 0x00398000);
++	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
++	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
++	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
++	WREG32(mmVCE_LMI_VM_CTRL, 0);
++
++	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
++	size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size);
++	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
++	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
++
++	addr += size;
++	size = AMDGPU_VCE_STACK_SIZE;
++	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
++	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
++
++	addr += size;
++	size = AMDGPU_VCE_HEAP_SIZE;
++	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
++	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
++
++	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
++
++	WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
++		 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
++
++	vce_v2_0_init_cg(adev);
++}
++
++static bool vce_v2_0_is_idle(struct amdgpu_device *adev)
++{
++	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
++}
++
++static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
++			return 0;
++	}
++	return -ETIMEDOUT;
++}
++
++static int vce_v2_0_soft_reset(struct amdgpu_device *adev)
++{
++	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
++			~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
++	mdelay(5);
++
++	return vce_v2_0_start(adev);
++}
++
++static void vce_v2_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "VCE 2.0 registers\n");
++	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",
++		 RREG32(mmVCE_STATUS));
++	dev_info(adev->dev, "  VCE_VCPU_CNTL=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CNTL));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE0=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_SIZE0));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE1=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_SIZE1));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE2=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_SIZE2));
++	dev_info(adev->dev, "  VCE_SOFT_RESET=0x%08X\n",
++		 RREG32(mmVCE_SOFT_RESET));
++	dev_info(adev->dev, "  VCE_RB_BASE_LO2=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_LO2));
++	dev_info(adev->dev, "  VCE_RB_BASE_HI2=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_HI2));
++	dev_info(adev->dev, "  VCE_RB_SIZE2=0x%08X\n",
++		 RREG32(mmVCE_RB_SIZE2));
++	dev_info(adev->dev, "  VCE_RB_RPTR2=0x%08X\n",
++		 RREG32(mmVCE_RB_RPTR2));
++	dev_info(adev->dev, "  VCE_RB_WPTR2=0x%08X\n",
++		 RREG32(mmVCE_RB_WPTR2));
++	dev_info(adev->dev, "  VCE_RB_BASE_LO=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_LO));
++	dev_info(adev->dev, "  VCE_RB_BASE_HI=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_HI));
++	dev_info(adev->dev, "  VCE_RB_SIZE=0x%08X\n",
++		 RREG32(mmVCE_RB_SIZE));
++	dev_info(adev->dev, "  VCE_RB_RPTR=0x%08X\n",
++		 RREG32(mmVCE_RB_RPTR));
++	dev_info(adev->dev, "  VCE_RB_WPTR=0x%08X\n",
++		 RREG32(mmVCE_RB_WPTR));
++	dev_info(adev->dev, "  VCE_CLOCK_GATING_A=0x%08X\n",
++		 RREG32(mmVCE_CLOCK_GATING_A));
++	dev_info(adev->dev, "  VCE_CLOCK_GATING_B=0x%08X\n",
++		 RREG32(mmVCE_CLOCK_GATING_B));
++	dev_info(adev->dev, "  VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
++		 RREG32(mmVCE_CGTT_CLK_OVERRIDE));
++	dev_info(adev->dev, "  VCE_UENC_CLOCK_GATING=0x%08X\n",
++		 RREG32(mmVCE_UENC_CLOCK_GATING));
++	dev_info(adev->dev, "  VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
++		 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
++	dev_info(adev->dev, "  VCE_SYS_INT_EN=0x%08X\n",
++		 RREG32(mmVCE_SYS_INT_EN));
++	dev_info(adev->dev, "  VCE_LMI_CTRL2=0x%08X\n",
++		 RREG32(mmVCE_LMI_CTRL2));
++	dev_info(adev->dev, "  VCE_LMI_CTRL=0x%08X\n",
++		 RREG32(mmVCE_LMI_CTRL));
++	dev_info(adev->dev, "  VCE_LMI_VM_CTRL=0x%08X\n",
++		 RREG32(mmVCE_LMI_VM_CTRL));
++	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmVCE_LMI_SWAP_CNTL));
++	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL1=0x%08X\n",
++		 RREG32(mmVCE_LMI_SWAP_CNTL1));
++	dev_info(adev->dev, "  VCE_LMI_CACHE_CTRL=0x%08X\n",
++		 RREG32(mmVCE_LMI_CACHE_CTRL));
++}
++
++static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	uint32_t val = 0;
++
++	if (state == AMDGPU_IRQ_STATE_ENABLE)
++		val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
++
++	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
++	return 0;
++}
++
++static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: VCE\n");
++	switch (entry->src_data) {
++	case 0:
++		amdgpu_fence_process(&adev->vce.ring[0]);
++		break;
++	case 1:
++		amdgpu_fence_process(&adev->vce.ring[1]);
++		break;
++	default:
++		DRM_ERROR("Unhandled interrupt: %d %d\n",
++			  entry->src_id, entry->src_data);
++		break;
++	}
++
++	return 0;
++}
++
++static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	bool gate = false;
++
++	if (state == AMDGPU_CG_STATE_GATE)
++		gate = true;
++
++	vce_v2_0_enable_mgcg(adev, gate);
++
++	return 0;
++}
++
++static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	/* This doesn't actually powergate the VCE block.
++	 * That's done in the dpm code via the SMC.  This
++	 * just re-inits the block as necessary.  The actual
++	 * gating still happens in the dpm code.  We should
++	 * revisit this when there is a cleaner line between
++	 * the smc and the hw blocks
++	 */
++	if (state == AMDGPU_PG_STATE_GATE)
++		/* XXX do we need a vce_v2_0_stop()? */
++		return 0;
++	else
++		return vce_v2_0_start(adev);
++}
++
++const struct amdgpu_ip_funcs vce_v2_0_ip_funcs = {
++	.early_init = vce_v2_0_early_init,
++	.late_init = NULL,
++	.sw_init = vce_v2_0_sw_init,
++	.sw_fini = vce_v2_0_sw_fini,
++	.hw_init = vce_v2_0_hw_init,
++	.hw_fini = vce_v2_0_hw_fini,
++	.suspend = vce_v2_0_suspend,
++	.resume = vce_v2_0_resume,
++	.is_idle = vce_v2_0_is_idle,
++	.wait_for_idle = vce_v2_0_wait_for_idle,
++	.soft_reset = vce_v2_0_soft_reset,
++	.print_status = vce_v2_0_print_status,
++	.set_clockgating_state = vce_v2_0_set_clockgating_state,
++	.set_powergating_state = vce_v2_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
++	.get_rptr = vce_v2_0_ring_get_rptr,
++	.get_wptr = vce_v2_0_ring_get_wptr,
++	.set_wptr = vce_v2_0_ring_set_wptr,
++	.parse_cs = amdgpu_vce_ring_parse_cs,
++	.emit_ib = amdgpu_vce_ring_emit_ib,
++	.emit_fence = amdgpu_vce_ring_emit_fence,
++	.emit_semaphore = amdgpu_vce_ring_emit_semaphore,
++	.test_ring = amdgpu_vce_ring_test_ring,
++	.test_ib = amdgpu_vce_ring_test_ib,
++	.is_lockup = amdgpu_ring_test_lockup,
++};
++
++static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
++	adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
++	.set = vce_v2_0_set_interrupt_state,
++	.process = vce_v2_0_process_interrupt,
++};
++
++static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->vce.irq.num_types = 1;
++	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
+new file mode 100644
+index 0000000..8eb1cf2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __VCE_V2_0_H__
++#define __VCE_V2_0_H__
++
++extern const struct amdgpu_ip_funcs vce_v2_0_ip_funcs;
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0039-yocto-amd-drm-amdgpu-add-BIF-5-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0039-yocto-amd-drm-amdgpu-add-BIF-5-1-register-headers.patch
new file mode 100644
index 00000000..bf3b4477
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0039-yocto-amd-drm-amdgpu-add-BIF-5-1-register-headers.patch
@@ -0,0 +1,33455 @@
+From 6377c9da05427ef167c74a0f613f4b2bd368ffb8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 17:31:14 -0400
+Subject: drm/amdgpu: Add initial VI support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds initial support for VI asics.  This
+includes Iceland, Tonga, and Carrizo.  Our inital
+focus as been Carrizo, so there are still gaps in
+support for Tonga and Iceland, notably power
+management.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index aec2886..9a573e8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -18,29 +18,57 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
+ 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
+ 
++# add asic specific block
+ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \
+ 	ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
+ 
++amdgpu-y += \
++	vi.o
++
++# add GMC block
++amdgpu-y += \
++	gmc_v8_0.o
++
+ # add IH block
+ amdgpu-y += \
+ 	amdgpu_irq.o \
+-	amdgpu_ih.o
++	amdgpu_ih.o \
++	iceland_ih.o \
++	tonga_ih.o \
++	cz_ih.o
+ 
+ # add SMC block
+ amdgpu-y += \
+-	amdgpu_dpm.o
++	amdgpu_dpm.o \
++	cz_smc.o cz_dpm.o \
++	tonga_smc.o tonga_dpm.o \
++	iceland_smc.o iceland_dpm.o
++
++# add DCE block
++amdgpu-y += \
++	dce_v10_0.o \
++	dce_v11_0.o
+ 
+ # add GFX block
+ amdgpu-y += \
+-	amdgpu_gfx.o
++	amdgpu_gfx.o \
++	gfx_v8_0.o
++
++# add async DMA block
++amdgpu-y += \
++	sdma_v2_4.o \
++	sdma_v3_0.o
+ 
+ # add UVD block
+ amdgpu-y += \
+-	amdgpu_uvd.o
++	amdgpu_uvd.o \
++	uvd_v5_0.o \
++	uvd_v6_0.o
+ 
+ # add VCE block
+ amdgpu-y += \
+-	amdgpu_vce.o
++	amdgpu_vce.o \
++	vce_v3_0.o
+ 
+ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
+ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 548e084..61cf5ad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -41,6 +41,7 @@
+ #ifdef CONFIG_DRM_AMDGPU_CIK
+ #include "cik.h"
+ #endif
++#include "vi.h"
+ #include "bif/bif_4_1_d.h"
+ 
+ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
+@@ -1154,9 +1155,21 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
+ 
+ static int amdgpu_early_init(struct amdgpu_device *adev)
+ {
+-	int i, r = -EINVAL;
++	int i, r;
+ 
+ 	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++	case CHIP_TONGA:
++	case CHIP_CARRIZO:
++		if (adev->asic_type == CHIP_CARRIZO)
++			adev->family = AMDGPU_FAMILY_CZ;
++		else
++			adev->family = AMDGPU_FAMILY_VI;
++
++		r = vi_set_ip_blocks(adev);
++		if (r)
++			return r;
++		break;
+ #ifdef CONFIG_DRM_AMDGPU_CIK
+ 	case CHIP_BONAIRE:
+ 	case CHIP_HAWAII:
+diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_vi.h b/drivers/gpu/drm/amd/amdgpu/clearstate_vi.h
+new file mode 100644
+index 0000000..1aab9be
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/clearstate_vi.h
+@@ -0,0 +1,944 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++static const unsigned int vi_SECT_CONTEXT_def_1[] =
++{
++    0x00000000, // DB_RENDER_CONTROL
++    0x00000000, // DB_COUNT_CONTROL
++    0x00000000, // DB_DEPTH_VIEW
++    0x00000000, // DB_RENDER_OVERRIDE
++    0x00000000, // DB_RENDER_OVERRIDE2
++    0x00000000, // DB_HTILE_DATA_BASE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // DB_DEPTH_BOUNDS_MIN
++    0x00000000, // DB_DEPTH_BOUNDS_MAX
++    0x00000000, // DB_STENCIL_CLEAR
++    0x00000000, // DB_DEPTH_CLEAR
++    0x00000000, // PA_SC_SCREEN_SCISSOR_TL
++    0x40004000, // PA_SC_SCREEN_SCISSOR_BR
++    0, // HOLE
++    0x00000000, // DB_DEPTH_INFO
++    0x00000000, // DB_Z_INFO
++    0x00000000, // DB_STENCIL_INFO
++    0x00000000, // DB_Z_READ_BASE
++    0x00000000, // DB_STENCIL_READ_BASE
++    0x00000000, // DB_Z_WRITE_BASE
++    0x00000000, // DB_STENCIL_WRITE_BASE
++    0x00000000, // DB_DEPTH_SIZE
++    0x00000000, // DB_DEPTH_SLICE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // TA_BC_BASE_ADDR
++    0x00000000, // TA_BC_BASE_ADDR_HI
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // COHER_DEST_BASE_HI_0
++    0x00000000, // COHER_DEST_BASE_HI_1
++    0x00000000, // COHER_DEST_BASE_HI_2
++    0x00000000, // COHER_DEST_BASE_HI_3
++    0x00000000, // COHER_DEST_BASE_2
++    0x00000000, // COHER_DEST_BASE_3
++    0x00000000, // PA_SC_WINDOW_OFFSET
++    0x80000000, // PA_SC_WINDOW_SCISSOR_TL
++    0x40004000, // PA_SC_WINDOW_SCISSOR_BR
++    0x0000ffff, // PA_SC_CLIPRECT_RULE
++    0x00000000, // PA_SC_CLIPRECT_0_TL
++    0x40004000, // PA_SC_CLIPRECT_0_BR
++    0x00000000, // PA_SC_CLIPRECT_1_TL
++    0x40004000, // PA_SC_CLIPRECT_1_BR
++    0x00000000, // PA_SC_CLIPRECT_2_TL
++    0x40004000, // PA_SC_CLIPRECT_2_BR
++    0x00000000, // PA_SC_CLIPRECT_3_TL
++    0x40004000, // PA_SC_CLIPRECT_3_BR
++    0xaa99aaaa, // PA_SC_EDGERULE
++    0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
++    0xffffffff, // CB_TARGET_MASK
++    0xffffffff, // CB_SHADER_MASK
++    0x80000000, // PA_SC_GENERIC_SCISSOR_TL
++    0x40004000, // PA_SC_GENERIC_SCISSOR_BR
++    0x00000000, // COHER_DEST_BASE_0
++    0x00000000, // COHER_DEST_BASE_1
++    0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
++    0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
++    0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
++    0x00000000, // PA_SC_VPORT_ZMIN_0
++    0x3f800000, // PA_SC_VPORT_ZMAX_0
++    0x00000000, // PA_SC_VPORT_ZMIN_1
++    0x3f800000, // PA_SC_VPORT_ZMAX_1
++    0x00000000, // PA_SC_VPORT_ZMIN_2
++    0x3f800000, // PA_SC_VPORT_ZMAX_2
++    0x00000000, // PA_SC_VPORT_ZMIN_3
++    0x3f800000, // PA_SC_VPORT_ZMAX_3
++    0x00000000, // PA_SC_VPORT_ZMIN_4
++    0x3f800000, // PA_SC_VPORT_ZMAX_4
++    0x00000000, // PA_SC_VPORT_ZMIN_5
++    0x3f800000, // PA_SC_VPORT_ZMAX_5
++    0x00000000, // PA_SC_VPORT_ZMIN_6
++    0x3f800000, // PA_SC_VPORT_ZMAX_6
++    0x00000000, // PA_SC_VPORT_ZMIN_7
++    0x3f800000, // PA_SC_VPORT_ZMAX_7
++    0x00000000, // PA_SC_VPORT_ZMIN_8
++    0x3f800000, // PA_SC_VPORT_ZMAX_8
++    0x00000000, // PA_SC_VPORT_ZMIN_9
++    0x3f800000, // PA_SC_VPORT_ZMAX_9
++    0x00000000, // PA_SC_VPORT_ZMIN_10
++    0x3f800000, // PA_SC_VPORT_ZMAX_10
++    0x00000000, // PA_SC_VPORT_ZMIN_11
++    0x3f800000, // PA_SC_VPORT_ZMAX_11
++    0x00000000, // PA_SC_VPORT_ZMIN_12
++    0x3f800000, // PA_SC_VPORT_ZMAX_12
++    0x00000000, // PA_SC_VPORT_ZMIN_13
++    0x3f800000, // PA_SC_VPORT_ZMAX_13
++    0x00000000, // PA_SC_VPORT_ZMIN_14
++    0x3f800000, // PA_SC_VPORT_ZMAX_14
++    0x00000000, // PA_SC_VPORT_ZMIN_15
++    0x3f800000, // PA_SC_VPORT_ZMAX_15
++};
++static const unsigned int vi_SECT_CONTEXT_def_2[] =
++{
++    0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL
++    0, // HOLE
++    0x00000000, // CP_PERFMON_CNTX_CNTL
++    0x00000000, // CP_RINGID
++    0x00000000, // CP_VMID
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0xffffffff, // VGT_MAX_VTX_INDX
++    0x00000000, // VGT_MIN_VTX_INDX
++    0x00000000, // VGT_INDX_OFFSET
++    0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
++    0, // HOLE
++    0x00000000, // CB_BLEND_RED
++    0x00000000, // CB_BLEND_GREEN
++    0x00000000, // CB_BLEND_BLUE
++    0x00000000, // CB_BLEND_ALPHA
++    0x00000000, // CB_DCC_CONTROL
++    0, // HOLE
++    0x00000000, // DB_STENCIL_CONTROL
++    0x00000000, // DB_STENCILREFMASK
++    0x00000000, // DB_STENCILREFMASK_BF
++    0, // HOLE
++    0x00000000, // PA_CL_VPORT_XSCALE
++    0x00000000, // PA_CL_VPORT_XOFFSET
++    0x00000000, // PA_CL_VPORT_YSCALE
++    0x00000000, // PA_CL_VPORT_YOFFSET
++    0x00000000, // PA_CL_VPORT_ZSCALE
++    0x00000000, // PA_CL_VPORT_ZOFFSET
++    0x00000000, // PA_CL_VPORT_XSCALE_1
++    0x00000000, // PA_CL_VPORT_XOFFSET_1
++    0x00000000, // PA_CL_VPORT_YSCALE_1
++    0x00000000, // PA_CL_VPORT_YOFFSET_1
++    0x00000000, // PA_CL_VPORT_ZSCALE_1
++    0x00000000, // PA_CL_VPORT_ZOFFSET_1
++    0x00000000, // PA_CL_VPORT_XSCALE_2
++    0x00000000, // PA_CL_VPORT_XOFFSET_2
++    0x00000000, // PA_CL_VPORT_YSCALE_2
++    0x00000000, // PA_CL_VPORT_YOFFSET_2
++    0x00000000, // PA_CL_VPORT_ZSCALE_2
++    0x00000000, // PA_CL_VPORT_ZOFFSET_2
++    0x00000000, // PA_CL_VPORT_XSCALE_3
++    0x00000000, // PA_CL_VPORT_XOFFSET_3
++    0x00000000, // PA_CL_VPORT_YSCALE_3
++    0x00000000, // PA_CL_VPORT_YOFFSET_3
++    0x00000000, // PA_CL_VPORT_ZSCALE_3
++    0x00000000, // PA_CL_VPORT_ZOFFSET_3
++    0x00000000, // PA_CL_VPORT_XSCALE_4
++    0x00000000, // PA_CL_VPORT_XOFFSET_4
++    0x00000000, // PA_CL_VPORT_YSCALE_4
++    0x00000000, // PA_CL_VPORT_YOFFSET_4
++    0x00000000, // PA_CL_VPORT_ZSCALE_4
++    0x00000000, // PA_CL_VPORT_ZOFFSET_4
++    0x00000000, // PA_CL_VPORT_XSCALE_5
++    0x00000000, // PA_CL_VPORT_XOFFSET_5
++    0x00000000, // PA_CL_VPORT_YSCALE_5
++    0x00000000, // PA_CL_VPORT_YOFFSET_5
++    0x00000000, // PA_CL_VPORT_ZSCALE_5
++    0x00000000, // PA_CL_VPORT_ZOFFSET_5
++    0x00000000, // PA_CL_VPORT_XSCALE_6
++    0x00000000, // PA_CL_VPORT_XOFFSET_6
++    0x00000000, // PA_CL_VPORT_YSCALE_6
++    0x00000000, // PA_CL_VPORT_YOFFSET_6
++    0x00000000, // PA_CL_VPORT_ZSCALE_6
++    0x00000000, // PA_CL_VPORT_ZOFFSET_6
++    0x00000000, // PA_CL_VPORT_XSCALE_7
++    0x00000000, // PA_CL_VPORT_XOFFSET_7
++    0x00000000, // PA_CL_VPORT_YSCALE_7
++    0x00000000, // PA_CL_VPORT_YOFFSET_7
++    0x00000000, // PA_CL_VPORT_ZSCALE_7
++    0x00000000, // PA_CL_VPORT_ZOFFSET_7
++    0x00000000, // PA_CL_VPORT_XSCALE_8
++    0x00000000, // PA_CL_VPORT_XOFFSET_8
++    0x00000000, // PA_CL_VPORT_YSCALE_8
++    0x00000000, // PA_CL_VPORT_YOFFSET_8
++    0x00000000, // PA_CL_VPORT_ZSCALE_8
++    0x00000000, // PA_CL_VPORT_ZOFFSET_8
++    0x00000000, // PA_CL_VPORT_XSCALE_9
++    0x00000000, // PA_CL_VPORT_XOFFSET_9
++    0x00000000, // PA_CL_VPORT_YSCALE_9
++    0x00000000, // PA_CL_VPORT_YOFFSET_9
++    0x00000000, // PA_CL_VPORT_ZSCALE_9
++    0x00000000, // PA_CL_VPORT_ZOFFSET_9
++    0x00000000, // PA_CL_VPORT_XSCALE_10
++    0x00000000, // PA_CL_VPORT_XOFFSET_10
++    0x00000000, // PA_CL_VPORT_YSCALE_10
++    0x00000000, // PA_CL_VPORT_YOFFSET_10
++    0x00000000, // PA_CL_VPORT_ZSCALE_10
++    0x00000000, // PA_CL_VPORT_ZOFFSET_10
++    0x00000000, // PA_CL_VPORT_XSCALE_11
++    0x00000000, // PA_CL_VPORT_XOFFSET_11
++    0x00000000, // PA_CL_VPORT_YSCALE_11
++    0x00000000, // PA_CL_VPORT_YOFFSET_11
++    0x00000000, // PA_CL_VPORT_ZSCALE_11
++    0x00000000, // PA_CL_VPORT_ZOFFSET_11
++    0x00000000, // PA_CL_VPORT_XSCALE_12
++    0x00000000, // PA_CL_VPORT_XOFFSET_12
++    0x00000000, // PA_CL_VPORT_YSCALE_12
++    0x00000000, // PA_CL_VPORT_YOFFSET_12
++    0x00000000, // PA_CL_VPORT_ZSCALE_12
++    0x00000000, // PA_CL_VPORT_ZOFFSET_12
++    0x00000000, // PA_CL_VPORT_XSCALE_13
++    0x00000000, // PA_CL_VPORT_XOFFSET_13
++    0x00000000, // PA_CL_VPORT_YSCALE_13
++    0x00000000, // PA_CL_VPORT_YOFFSET_13
++    0x00000000, // PA_CL_VPORT_ZSCALE_13
++    0x00000000, // PA_CL_VPORT_ZOFFSET_13
++    0x00000000, // PA_CL_VPORT_XSCALE_14
++    0x00000000, // PA_CL_VPORT_XOFFSET_14
++    0x00000000, // PA_CL_VPORT_YSCALE_14
++    0x00000000, // PA_CL_VPORT_YOFFSET_14
++    0x00000000, // PA_CL_VPORT_ZSCALE_14
++    0x00000000, // PA_CL_VPORT_ZOFFSET_14
++    0x00000000, // PA_CL_VPORT_XSCALE_15
++    0x00000000, // PA_CL_VPORT_XOFFSET_15
++    0x00000000, // PA_CL_VPORT_YSCALE_15
++    0x00000000, // PA_CL_VPORT_YOFFSET_15
++    0x00000000, // PA_CL_VPORT_ZSCALE_15
++    0x00000000, // PA_CL_VPORT_ZOFFSET_15
++    0x00000000, // PA_CL_UCP_0_X
++    0x00000000, // PA_CL_UCP_0_Y
++    0x00000000, // PA_CL_UCP_0_Z
++    0x00000000, // PA_CL_UCP_0_W
++    0x00000000, // PA_CL_UCP_1_X
++    0x00000000, // PA_CL_UCP_1_Y
++    0x00000000, // PA_CL_UCP_1_Z
++    0x00000000, // PA_CL_UCP_1_W
++    0x00000000, // PA_CL_UCP_2_X
++    0x00000000, // PA_CL_UCP_2_Y
++    0x00000000, // PA_CL_UCP_2_Z
++    0x00000000, // PA_CL_UCP_2_W
++    0x00000000, // PA_CL_UCP_3_X
++    0x00000000, // PA_CL_UCP_3_Y
++    0x00000000, // PA_CL_UCP_3_Z
++    0x00000000, // PA_CL_UCP_3_W
++    0x00000000, // PA_CL_UCP_4_X
++    0x00000000, // PA_CL_UCP_4_Y
++    0x00000000, // PA_CL_UCP_4_Z
++    0x00000000, // PA_CL_UCP_4_W
++    0x00000000, // PA_CL_UCP_5_X
++    0x00000000, // PA_CL_UCP_5_Y
++    0x00000000, // PA_CL_UCP_5_Z
++    0x00000000, // PA_CL_UCP_5_W
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // SPI_PS_INPUT_CNTL_0
++    0x00000000, // SPI_PS_INPUT_CNTL_1
++    0x00000000, // SPI_PS_INPUT_CNTL_2
++    0x00000000, // SPI_PS_INPUT_CNTL_3
++    0x00000000, // SPI_PS_INPUT_CNTL_4
++    0x00000000, // SPI_PS_INPUT_CNTL_5
++    0x00000000, // SPI_PS_INPUT_CNTL_6
++    0x00000000, // SPI_PS_INPUT_CNTL_7
++    0x00000000, // SPI_PS_INPUT_CNTL_8
++    0x00000000, // SPI_PS_INPUT_CNTL_9
++    0x00000000, // SPI_PS_INPUT_CNTL_10
++    0x00000000, // SPI_PS_INPUT_CNTL_11
++    0x00000000, // SPI_PS_INPUT_CNTL_12
++    0x00000000, // SPI_PS_INPUT_CNTL_13
++    0x00000000, // SPI_PS_INPUT_CNTL_14
++    0x00000000, // SPI_PS_INPUT_CNTL_15
++    0x00000000, // SPI_PS_INPUT_CNTL_16
++    0x00000000, // SPI_PS_INPUT_CNTL_17
++    0x00000000, // SPI_PS_INPUT_CNTL_18
++    0x00000000, // SPI_PS_INPUT_CNTL_19
++    0x00000000, // SPI_PS_INPUT_CNTL_20
++    0x00000000, // SPI_PS_INPUT_CNTL_21
++    0x00000000, // SPI_PS_INPUT_CNTL_22
++    0x00000000, // SPI_PS_INPUT_CNTL_23
++    0x00000000, // SPI_PS_INPUT_CNTL_24
++    0x00000000, // SPI_PS_INPUT_CNTL_25
++    0x00000000, // SPI_PS_INPUT_CNTL_26
++    0x00000000, // SPI_PS_INPUT_CNTL_27
++    0x00000000, // SPI_PS_INPUT_CNTL_28
++    0x00000000, // SPI_PS_INPUT_CNTL_29
++    0x00000000, // SPI_PS_INPUT_CNTL_30
++    0x00000000, // SPI_PS_INPUT_CNTL_31
++    0x00000000, // SPI_VS_OUT_CONFIG
++    0, // HOLE
++    0x00000000, // SPI_PS_INPUT_ENA
++    0x00000000, // SPI_PS_INPUT_ADDR
++    0x00000000, // SPI_INTERP_CONTROL_0
++    0x00000002, // SPI_PS_IN_CONTROL
++    0, // HOLE
++    0x00000000, // SPI_BARYC_CNTL
++    0, // HOLE
++    0x00000000, // SPI_TMPRING_SIZE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // SPI_SHADER_POS_FORMAT
++    0x00000000, // SPI_SHADER_Z_FORMAT
++    0x00000000, // SPI_SHADER_COL_FORMAT
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // CB_BLEND0_CONTROL
++    0x00000000, // CB_BLEND1_CONTROL
++    0x00000000, // CB_BLEND2_CONTROL
++    0x00000000, // CB_BLEND3_CONTROL
++    0x00000000, // CB_BLEND4_CONTROL
++    0x00000000, // CB_BLEND5_CONTROL
++    0x00000000, // CB_BLEND6_CONTROL
++    0x00000000, // CB_BLEND7_CONTROL
++};
++static const unsigned int vi_SECT_CONTEXT_def_3[] =
++{
++    0x00000000, // PA_CL_POINT_X_RAD
++    0x00000000, // PA_CL_POINT_Y_RAD
++    0x00000000, // PA_CL_POINT_SIZE
++    0x00000000, // PA_CL_POINT_CULL_RAD
++    0x00000000, // VGT_DMA_BASE_HI
++    0x00000000, // VGT_DMA_BASE
++};
++static const unsigned int vi_SECT_CONTEXT_def_4[] =
++{
++    0x00000000, // DB_DEPTH_CONTROL
++    0x00000000, // DB_EQAA
++    0x00000000, // CB_COLOR_CONTROL
++    0x00000000, // DB_SHADER_CONTROL
++    0x00090000, // PA_CL_CLIP_CNTL
++    0x00000004, // PA_SU_SC_MODE_CNTL
++    0x00000000, // PA_CL_VTE_CNTL
++    0x00000000, // PA_CL_VS_OUT_CNTL
++    0x00000000, // PA_CL_NANINF_CNTL
++    0x00000000, // PA_SU_LINE_STIPPLE_CNTL
++    0x00000000, // PA_SU_LINE_STIPPLE_SCALE
++    0x00000000, // PA_SU_PRIM_FILTER_CNTL
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // PA_SU_POINT_SIZE
++    0x00000000, // PA_SU_POINT_MINMAX
++    0x00000000, // PA_SU_LINE_CNTL
++    0x00000000, // PA_SC_LINE_STIPPLE
++    0x00000000, // VGT_OUTPUT_PATH_CNTL
++    0x00000000, // VGT_HOS_CNTL
++    0x00000000, // VGT_HOS_MAX_TESS_LEVEL
++    0x00000000, // VGT_HOS_MIN_TESS_LEVEL
++    0x00000000, // VGT_HOS_REUSE_DEPTH
++    0x00000000, // VGT_GROUP_PRIM_TYPE
++    0x00000000, // VGT_GROUP_FIRST_DECR
++    0x00000000, // VGT_GROUP_DECR
++    0x00000000, // VGT_GROUP_VECT_0_CNTL
++    0x00000000, // VGT_GROUP_VECT_1_CNTL
++    0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
++    0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
++    0x00000000, // VGT_GS_MODE
++    0x00000000, // VGT_GS_ONCHIP_CNTL
++    0x00000000, // PA_SC_MODE_CNTL_0
++    0x00000000, // PA_SC_MODE_CNTL_1
++    0x00000000, // VGT_ENHANCE
++    0x00000100, // VGT_GS_PER_ES
++    0x00000080, // VGT_ES_PER_GS
++    0x00000002, // VGT_GS_PER_VS
++    0x00000000, // VGT_GSVS_RING_OFFSET_1
++    0x00000000, // VGT_GSVS_RING_OFFSET_2
++    0x00000000, // VGT_GSVS_RING_OFFSET_3
++    0x00000000, // VGT_GS_OUT_PRIM_TYPE
++    0x00000000, // IA_ENHANCE
++};
++static const unsigned int vi_SECT_CONTEXT_def_5[] =
++{
++    0x00000000, // WD_ENHANCE
++    0x00000000, // VGT_PRIMITIVEID_EN
++};
++static const unsigned int vi_SECT_CONTEXT_def_6[] =
++{
++    0x00000000, // VGT_PRIMITIVEID_RESET
++};
++static const unsigned int vi_SECT_CONTEXT_def_7[] =
++{
++    0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // VGT_INSTANCE_STEP_RATE_0
++    0x00000000, // VGT_INSTANCE_STEP_RATE_1
++    0x000000ff, // IA_MULTI_VGT_PARAM
++    0x00000000, // VGT_ESGS_RING_ITEMSIZE
++    0x00000000, // VGT_GSVS_RING_ITEMSIZE
++    0x00000000, // VGT_REUSE_OFF
++    0x00000000, // VGT_VTX_CNT_EN
++    0x00000000, // DB_HTILE_SURFACE
++    0x00000000, // DB_SRESULTS_COMPARE_STATE0
++    0x00000000, // DB_SRESULTS_COMPARE_STATE1
++    0x00000000, // DB_PRELOAD_CONTROL
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
++    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
++    0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
++    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
++    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
++    0, // HOLE
++    0x00000000, // VGT_GS_MAX_VERT_OUT
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // VGT_TESS_DISTRIBUTION
++    0x00000000, // VGT_SHADER_STAGES_EN
++    0x00000000, // VGT_LS_HS_CONFIG
++    0x00000000, // VGT_GS_VERT_ITEMSIZE
++    0x00000000, // VGT_GS_VERT_ITEMSIZE_1
++    0x00000000, // VGT_GS_VERT_ITEMSIZE_2
++    0x00000000, // VGT_GS_VERT_ITEMSIZE_3
++    0x00000000, // VGT_TF_PARAM
++    0x00000000, // DB_ALPHA_TO_MASK
++    0x00000000, // VGT_DISPATCH_DRAW_INDEX
++    0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
++    0x00000000, // PA_SU_POLY_OFFSET_CLAMP
++    0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
++    0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
++    0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
++    0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
++    0x00000000, // VGT_GS_INSTANCE_CNT
++    0x00000000, // VGT_STRMOUT_CONFIG
++    0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x00000000, // PA_SC_CENTROID_PRIORITY_0
++    0x00000000, // PA_SC_CENTROID_PRIORITY_1
++    0x00001000, // PA_SC_LINE_CNTL
++    0x00000000, // PA_SC_AA_CONFIG
++    0x00000005, // PA_SU_VTX_CNTL
++    0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
++    0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
++    0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
++    0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
++    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
++    0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0
++    0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0, // HOLE
++    0x0000001e, // VGT_VERTEX_REUSE_BLOCK_CNTL
++    0x00000020, // VGT_OUT_DEALLOC_CNTL
++    0x00000000, // CB_COLOR0_BASE
++    0x00000000, // CB_COLOR0_PITCH
++    0x00000000, // CB_COLOR0_SLICE
++    0x00000000, // CB_COLOR0_VIEW
++    0x00000000, // CB_COLOR0_INFO
++    0x00000000, // CB_COLOR0_ATTRIB
++    0x00000000, // CB_COLOR0_DCC_CONTROL
++    0x00000000, // CB_COLOR0_CMASK
++    0x00000000, // CB_COLOR0_CMASK_SLICE
++    0x00000000, // CB_COLOR0_FMASK
++    0x00000000, // CB_COLOR0_FMASK_SLICE
++    0x00000000, // CB_COLOR0_CLEAR_WORD0
++    0x00000000, // CB_COLOR0_CLEAR_WORD1
++    0x00000000, // CB_COLOR0_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR1_BASE
++    0x00000000, // CB_COLOR1_PITCH
++    0x00000000, // CB_COLOR1_SLICE
++    0x00000000, // CB_COLOR1_VIEW
++    0x00000000, // CB_COLOR1_INFO
++    0x00000000, // CB_COLOR1_ATTRIB
++    0x00000000, // CB_COLOR1_DCC_CONTROL
++    0x00000000, // CB_COLOR1_CMASK
++    0x00000000, // CB_COLOR1_CMASK_SLICE
++    0x00000000, // CB_COLOR1_FMASK
++    0x00000000, // CB_COLOR1_FMASK_SLICE
++    0x00000000, // CB_COLOR1_CLEAR_WORD0
++    0x00000000, // CB_COLOR1_CLEAR_WORD1
++    0x00000000, // CB_COLOR1_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR2_BASE
++    0x00000000, // CB_COLOR2_PITCH
++    0x00000000, // CB_COLOR2_SLICE
++    0x00000000, // CB_COLOR2_VIEW
++    0x00000000, // CB_COLOR2_INFO
++    0x00000000, // CB_COLOR2_ATTRIB
++    0x00000000, // CB_COLOR2_DCC_CONTROL
++    0x00000000, // CB_COLOR2_CMASK
++    0x00000000, // CB_COLOR2_CMASK_SLICE
++    0x00000000, // CB_COLOR2_FMASK
++    0x00000000, // CB_COLOR2_FMASK_SLICE
++    0x00000000, // CB_COLOR2_CLEAR_WORD0
++    0x00000000, // CB_COLOR2_CLEAR_WORD1
++    0x00000000, // CB_COLOR2_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR3_BASE
++    0x00000000, // CB_COLOR3_PITCH
++    0x00000000, // CB_COLOR3_SLICE
++    0x00000000, // CB_COLOR3_VIEW
++    0x00000000, // CB_COLOR3_INFO
++    0x00000000, // CB_COLOR3_ATTRIB
++    0x00000000, // CB_COLOR3_DCC_CONTROL
++    0x00000000, // CB_COLOR3_CMASK
++    0x00000000, // CB_COLOR3_CMASK_SLICE
++    0x00000000, // CB_COLOR3_FMASK
++    0x00000000, // CB_COLOR3_FMASK_SLICE
++    0x00000000, // CB_COLOR3_CLEAR_WORD0
++    0x00000000, // CB_COLOR3_CLEAR_WORD1
++    0x00000000, // CB_COLOR3_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR4_BASE
++    0x00000000, // CB_COLOR4_PITCH
++    0x00000000, // CB_COLOR4_SLICE
++    0x00000000, // CB_COLOR4_VIEW
++    0x00000000, // CB_COLOR4_INFO
++    0x00000000, // CB_COLOR4_ATTRIB
++    0x00000000, // CB_COLOR4_DCC_CONTROL
++    0x00000000, // CB_COLOR4_CMASK
++    0x00000000, // CB_COLOR4_CMASK_SLICE
++    0x00000000, // CB_COLOR4_FMASK
++    0x00000000, // CB_COLOR4_FMASK_SLICE
++    0x00000000, // CB_COLOR4_CLEAR_WORD0
++    0x00000000, // CB_COLOR4_CLEAR_WORD1
++    0x00000000, // CB_COLOR4_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR5_BASE
++    0x00000000, // CB_COLOR5_PITCH
++    0x00000000, // CB_COLOR5_SLICE
++    0x00000000, // CB_COLOR5_VIEW
++    0x00000000, // CB_COLOR5_INFO
++    0x00000000, // CB_COLOR5_ATTRIB
++    0x00000000, // CB_COLOR5_DCC_CONTROL
++    0x00000000, // CB_COLOR5_CMASK
++    0x00000000, // CB_COLOR5_CMASK_SLICE
++    0x00000000, // CB_COLOR5_FMASK
++    0x00000000, // CB_COLOR5_FMASK_SLICE
++    0x00000000, // CB_COLOR5_CLEAR_WORD0
++    0x00000000, // CB_COLOR5_CLEAR_WORD1
++    0x00000000, // CB_COLOR5_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR6_BASE
++    0x00000000, // CB_COLOR6_PITCH
++    0x00000000, // CB_COLOR6_SLICE
++    0x00000000, // CB_COLOR6_VIEW
++    0x00000000, // CB_COLOR6_INFO
++    0x00000000, // CB_COLOR6_ATTRIB
++    0x00000000, // CB_COLOR6_DCC_CONTROL
++    0x00000000, // CB_COLOR6_CMASK
++    0x00000000, // CB_COLOR6_CMASK_SLICE
++    0x00000000, // CB_COLOR6_FMASK
++    0x00000000, // CB_COLOR6_FMASK_SLICE
++    0x00000000, // CB_COLOR6_CLEAR_WORD0
++    0x00000000, // CB_COLOR6_CLEAR_WORD1
++    0x00000000, // CB_COLOR6_DCC_BASE
++    0, // HOLE
++    0x00000000, // CB_COLOR7_BASE
++    0x00000000, // CB_COLOR7_PITCH
++    0x00000000, // CB_COLOR7_SLICE
++    0x00000000, // CB_COLOR7_VIEW
++    0x00000000, // CB_COLOR7_INFO
++    0x00000000, // CB_COLOR7_ATTRIB
++    0x00000000, // CB_COLOR7_DCC_CONTROL
++    0x00000000, // CB_COLOR7_CMASK
++    0x00000000, // CB_COLOR7_CMASK_SLICE
++    0x00000000, // CB_COLOR7_FMASK
++    0x00000000, // CB_COLOR7_FMASK_SLICE
++    0x00000000, // CB_COLOR7_CLEAR_WORD0
++    0x00000000, // CB_COLOR7_CLEAR_WORD1
++};
++static const struct cs_extent_def vi_SECT_CONTEXT_defs[] =
++{
++    {vi_SECT_CONTEXT_def_1, 0x0000a000, 212 },
++    {vi_SECT_CONTEXT_def_2, 0x0000a0d6, 274 },
++    {vi_SECT_CONTEXT_def_3, 0x0000a1f5, 6 },
++    {vi_SECT_CONTEXT_def_4, 0x0000a200, 157 },
++    {vi_SECT_CONTEXT_def_5, 0x0000a2a0, 2 },
++    {vi_SECT_CONTEXT_def_6, 0x0000a2a3, 1 },
++    {vi_SECT_CONTEXT_def_7, 0x0000a2a5, 233 },
++    { 0, 0, 0 }
++};
++static const struct cs_section_def vi_cs_data[] = {
++    { vi_SECT_CONTEXT_defs, SECT_CONTEXT },
++    { 0, SECT_NONE }
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+new file mode 100644
+index 0000000..b5c8485
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+@@ -0,0 +1,1712 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include <linux/seq_file.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_atombios.h"
++#include "vid.h"
++#include "vi_dpm.h"
++#include "amdgpu_dpm.h"
++#include "cz_dpm.h"
++#include "cz_ppsmc.h"
++#include "atom.h"
++
++#include "smu/smu_8_0_d.h"
++#include "smu/smu_8_0_sh_mask.h"
++#include "gca/gfx_8_0_d.h"
++#include "gca/gfx_8_0_sh_mask.h"
++#include "gmc/gmc_8_1_d.h"
++#include "bif/bif_5_1_d.h"
++#include "gfx_v8_0.h"
++
++static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
++{
++	struct cz_ps *ps = rps->ps_priv;
++
++	return ps;
++}
++
++static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = adev->pm.dpm.priv;
++
++	return pi;
++}
++
++static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
++							uint16_t voltage)
++{
++	uint16_t tmp = 6200 - voltage * 25;
++
++	return tmp;
++}
++
++static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
++				struct amdgpu_clock_and_voltage_limits *table)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *dep_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	if (dep_table->count > 0) {
++		table->sclk = dep_table->entries[dep_table->count - 1].clk;
++		table->vddc = cz_convert_8bit_index_to_voltage(adev,
++				dep_table->entries[dep_table->count - 1].v);
++	}
++
++	table->mclk = pi->sys_info.nbp_memory_clock[0];
++
++}
++
++union igp_info {
++	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
++	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
++};
++
++static int cz_parse_sys_info_table(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
++	union igp_info *igp_info;
++	u8 frev, crev;
++	u16 data_offset;
++	int i = 0;
++
++	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				   &frev, &crev, &data_offset)) {
++		igp_info = (union igp_info *)(mode_info->atom_context->bios +
++					      data_offset);
++
++		if (crev != 9) {
++			DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
++			return -EINVAL;
++		}
++		pi->sys_info.bootup_sclk =
++			le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
++		pi->sys_info.bootup_uma_clk =
++			le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
++		pi->sys_info.dentist_vco_freq =
++			le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
++		pi->sys_info.bootup_nb_voltage_index =
++			le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
++
++		if (igp_info->info_9.ucHtcTmpLmt == 0)
++			pi->sys_info.htc_tmp_lmt = 203;
++		else
++			pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
++
++		if (igp_info->info_9.ucHtcHystLmt == 0)
++			pi->sys_info.htc_hyst_lmt = 5;
++		else
++			pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
++
++		if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
++			DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
++			return -EINVAL;
++		}
++
++		if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
++				pi->enable_nb_ps_policy)
++			pi->sys_info.nb_dpm_enable = true;
++		else
++			pi->sys_info.nb_dpm_enable = false;
++
++		for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
++			if (i < CZ_NUM_NBPMEMORY_CLOCK)
++				pi->sys_info.nbp_memory_clock[i] =
++				le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
++			pi->sys_info.nbp_n_clock[i] =
++			le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
++		}
++
++		for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
++			pi->sys_info.display_clock[i] =
++			le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
++
++		for (i = 0; i < CZ_NUM_NBPSTATES; i++)
++			pi->sys_info.nbp_voltage_index[i] =
++				le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
++
++		if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
++			SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
++			pi->caps_enable_dfs_bypass = true;
++
++		pi->sys_info.uma_channel_number =
++			igp_info->info_9.ucUMAChannelNumber;
++
++		cz_construct_max_power_limits_table(adev,
++			&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
++	}
++
++	return 0;
++}
++
++static void cz_patch_voltage_values(struct amdgpu_device *adev)
++{
++	int i;
++	struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
++		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
++	struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table *acp_table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++
++	if (uvd_table->count) {
++		for (i = 0; i < uvd_table->count; i++)
++			uvd_table->entries[i].v =
++				cz_convert_8bit_index_to_voltage(adev,
++						uvd_table->entries[i].v);
++	}
++
++	if (vce_table->count) {
++		for (i = 0; i < vce_table->count; i++)
++			vce_table->entries[i].v =
++				cz_convert_8bit_index_to_voltage(adev,
++						vce_table->entries[i].v);
++	}
++
++	if (acp_table->count) {
++		for (i = 0; i < acp_table->count; i++)
++			acp_table->entries[i].v =
++				cz_convert_8bit_index_to_voltage(adev,
++						acp_table->entries[i].v);
++	}
++
++}
++
++static void cz_construct_boot_state(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
++	pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
++	pi->boot_pl.ds_divider_index = 0;
++	pi->boot_pl.ss_divider_index = 0;
++	pi->boot_pl.allow_gnb_slow = 1;
++	pi->boot_pl.force_nbp_state = 0;
++	pi->boot_pl.display_wm = 0;
++	pi->boot_pl.vce_wm = 0;
++
++}
++
++static void cz_patch_boot_state(struct amdgpu_device *adev,
++				struct cz_ps *ps)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	ps->num_levels = 1;
++	ps->levels[0] = pi->boot_pl;
++}
++
++union pplib_clock_info {
++	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
++	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
++	struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
++};
++
++static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
++					struct amdgpu_ps *rps, int index,
++					union pplib_clock_info *clock_info)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct cz_ps *ps = cz_get_ps(rps);
++	struct cz_pl *pl = &ps->levels[index];
++	struct amdgpu_clock_voltage_dependency_table *table =
++			&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	pl->sclk = table->entries[clock_info->carrizo.index].clk;
++	pl->vddc_index = table->entries[clock_info->carrizo.index].v;
++
++	ps->num_levels = index + 1;
++
++	if (pi->caps_sclk_ds) {
++		pl->ds_divider_index = 5;
++		pl->ss_divider_index = 5;
++	}
++
++}
++
++static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
++			struct amdgpu_ps *rps,
++			struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
++			u8 table_rev)
++{
++	struct cz_ps *ps = cz_get_ps(rps);
++
++	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
++	rps->class = le16_to_cpu(non_clock_info->usClassification);
++	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
++
++	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
++		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
++		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
++	} else {
++		rps->vclk = 0;
++		rps->dclk = 0;
++	}
++
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
++		adev->pm.dpm.boot_ps = rps;
++		cz_patch_boot_state(adev, ps);
++	}
++	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
++		adev->pm.dpm.uvd_ps = rps;
++
++}
++
++union power_info {
++	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
++	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
++	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
++	struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
++	struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
++};
++
++union pplib_power_state {
++	struct _ATOM_PPLIB_STATE v1;
++	struct _ATOM_PPLIB_STATE_V2 v2;
++};
++
++static int cz_parse_power_table(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_info *mode_info = &adev->mode_info;
++	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
++	union pplib_power_state *power_state;
++	int i, j, k, non_clock_array_index, clock_array_index;
++	union pplib_clock_info *clock_info;
++	struct _StateArray *state_array;
++	struct _ClockInfoArray *clock_info_array;
++	struct _NonClockInfoArray *non_clock_info_array;
++	union power_info *power_info;
++	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
++	u16 data_offset;
++	u8 frev, crev;
++	u8 *power_state_offset;
++	struct cz_ps *ps;
++
++	if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
++				    &frev, &crev, &data_offset))
++		return -EINVAL;
++	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
++
++	state_array = (struct _StateArray *)
++		(mode_info->atom_context->bios + data_offset +
++		le16_to_cpu(power_info->pplib.usStateArrayOffset));
++	clock_info_array = (struct _ClockInfoArray *)
++		(mode_info->atom_context->bios + data_offset +
++		le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
++	non_clock_info_array = (struct _NonClockInfoArray *)
++		(mode_info->atom_context->bios + data_offset +
++		le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
++
++	adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
++					state_array->ucNumEntries, GFP_KERNEL);
++
++	if (!adev->pm.dpm.ps)
++		return -ENOMEM;
++
++	power_state_offset = (u8 *)state_array->states;
++	adev->pm.dpm.platform_caps =
++			le32_to_cpu(power_info->pplib.ulPlatformCaps);
++	adev->pm.dpm.backbias_response_time =
++			le16_to_cpu(power_info->pplib.usBackbiasTime);
++	adev->pm.dpm.voltage_response_time =
++			le16_to_cpu(power_info->pplib.usVoltageTime);
++
++	for (i = 0; i < state_array->ucNumEntries; i++) {
++		power_state = (union pplib_power_state *)power_state_offset;
++		non_clock_array_index = power_state->v2.nonClockInfoIndex;
++		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
++			&non_clock_info_array->nonClockInfo[non_clock_array_index];
++
++		ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
++		if (ps == NULL) {
++			kfree(adev->pm.dpm.ps);
++			return -ENOMEM;
++		}
++
++		adev->pm.dpm.ps[i].ps_priv = ps;
++		k = 0;
++		for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
++			clock_array_index = power_state->v2.clockInfoIndex[j];
++			if (clock_array_index >= clock_info_array->ucNumEntries)
++				continue;
++			if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
++				break;
++			clock_info = (union pplib_clock_info *)
++				&clock_info_array->clockInfo[clock_array_index *
++				clock_info_array->ucEntrySize];
++			cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
++				k, clock_info);
++			k++;
++		}
++		cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
++					non_clock_info,
++					non_clock_info_array->ucEntrySize);
++		power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
++	}
++	adev->pm.dpm.num_ps = state_array->ucNumEntries;
++
++	return 0;
++}
++
++static int cz_process_firmware_header(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	u32 tmp;
++	int ret;
++
++	ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
++				     offsetof(struct SMU8_Firmware_Header,
++				     DpmTable),
++				     &tmp, pi->sram_end);
++
++	if (ret == 0)
++		pi->dpm_table_start = tmp;
++
++	return ret;
++}
++
++static int cz_dpm_init(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi;
++	int ret, i;
++
++	pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
++	if (NULL == pi)
++		return -ENOMEM;
++
++	adev->pm.dpm.priv = pi;
++
++	ret = amdgpu_get_platform_caps(adev);
++	if (ret)
++		return ret;
++
++	ret = amdgpu_parse_extended_power_table(adev);
++	if (ret)
++		return ret;
++
++	pi->sram_end = SMC_RAM_END;
++
++	/* set up DPM defaults */
++	for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
++		pi->active_target[i] = CZ_AT_DFLT;
++
++	pi->mgcg_cgtt_local0 = 0x0;
++	pi->mgcg_cgtt_local1 = 0x0;
++	pi->clock_slow_down_step = 25000;
++	pi->skip_clock_slow_down = 1;
++	pi->enable_nb_ps_policy = 1;
++	pi->caps_power_containment = true;
++	pi->caps_cac = true;
++	pi->didt_enabled = false;
++	if (pi->didt_enabled) {
++		pi->caps_sq_ramping = true;
++		pi->caps_db_ramping = true;
++		pi->caps_td_ramping = true;
++		pi->caps_tcp_ramping = true;
++	}
++	pi->caps_sclk_ds = true;
++	pi->voting_clients = 0x00c00033;
++	pi->auto_thermal_throttling_enabled = true;
++	pi->bapm_enabled = false;
++	pi->disable_nb_ps3_in_battery = false;
++	pi->voltage_drop_threshold = 0;
++	pi->caps_sclk_throttle_low_notification = false;
++	pi->gfx_pg_threshold = 500;
++	pi->caps_fps = true;
++	/* uvd */
++	pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
++	pi->caps_uvd_dpm = true;
++	/* vce */
++	pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
++	pi->caps_vce_dpm = true;
++	/* acp */
++	pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
++	pi->caps_acp_dpm = true;
++
++	pi->caps_stable_power_state = false;
++	pi->nb_dpm_enabled_by_driver = true;
++	pi->nb_dpm_enabled = false;
++	pi->caps_voltage_island = false;
++	/* flags which indicate need to upload pptable */
++	pi->need_pptable_upload = true;
++
++	ret = cz_parse_sys_info_table(adev);
++	if (ret)
++		return ret;
++
++	cz_patch_voltage_values(adev);
++	cz_construct_boot_state(adev);
++
++	ret = cz_parse_power_table(adev);
++	if (ret)
++		return ret;
++
++	ret = cz_process_firmware_header(adev);
++	if (ret)
++		return ret;
++
++	pi->dpm_enabled = true;
++
++	return 0;
++}
++
++static void cz_dpm_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->pm.dpm.num_ps; i++)
++		kfree(adev->pm.dpm.ps[i].ps_priv);
++
++	kfree(adev->pm.dpm.ps);
++	kfree(adev->pm.dpm.priv);
++	amdgpu_free_extended_power_table(adev);
++}
++
++static void
++cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
++					       struct seq_file *m)
++{
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	u32 current_index =
++		(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
++		TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
++		TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
++	u32 sclk, tmp;
++	u16 vddc;
++
++	if (current_index >= NUM_SCLK_LEVELS) {
++		seq_printf(m, "invalid dpm profile %d\n", current_index);
++	} else {
++		sclk = table->entries[current_index].clk;
++		tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
++			SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
++			SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
++		vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
++		seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
++			   current_index, sclk, vddc);
++	}
++}
++
++static void cz_dpm_print_power_state(struct amdgpu_device *adev,
++					struct amdgpu_ps *rps)
++{
++	int i;
++	struct cz_ps *ps = cz_get_ps(rps);
++
++	amdgpu_dpm_print_class_info(rps->class, rps->class2);
++	amdgpu_dpm_print_cap_info(rps->caps);
++
++	DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
++	for (i = 0; i < ps->num_levels; i++) {
++		struct cz_pl *pl = &ps->levels[i];
++
++		DRM_INFO("\t\tpower level %d    sclk: %u vddc: %u\n",
++		       i, pl->sclk,
++		       cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
++	}
++
++	amdgpu_dpm_print_ps_status(adev, rps);
++}
++
++static void cz_dpm_set_funcs(struct amdgpu_device *adev);
++
++static int cz_dpm_early_init(struct amdgpu_device *adev)
++{
++	cz_dpm_set_funcs(adev);
++
++	return 0;
++}
++
++static int cz_dpm_sw_init(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	/* fix me to add thermal support TODO */
++
++	/* default to balanced state */
++	adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
++	adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
++	adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
++	adev->pm.default_sclk = adev->clock.default_sclk;
++	adev->pm.default_mclk = adev->clock.default_mclk;
++	adev->pm.current_sclk = adev->clock.default_sclk;
++	adev->pm.current_mclk = adev->clock.default_mclk;
++	adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
++
++	if (amdgpu_dpm == 0)
++		return 0;
++
++	mutex_lock(&adev->pm.mutex);
++	ret = cz_dpm_init(adev);
++	if (ret)
++		goto dpm_init_failed;
++
++	adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
++	if (amdgpu_dpm == 1)
++		amdgpu_pm_print_power_states(adev);
++
++	ret = amdgpu_pm_sysfs_init(adev);
++	if (ret)
++		goto dpm_init_failed;
++
++	mutex_unlock(&adev->pm.mutex);
++	DRM_INFO("amdgpu: dpm initialized\n");
++
++	return 0;
++
++dpm_init_failed:
++	cz_dpm_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++	DRM_ERROR("amdgpu: dpm initialization failed\n");
++
++	return ret;
++}
++
++static int cz_dpm_sw_fini(struct amdgpu_device *adev)
++{
++	mutex_lock(&adev->pm.mutex);
++	amdgpu_pm_sysfs_fini(adev);
++	cz_dpm_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++
++	return 0;
++}
++
++static void cz_reset_ap_mask(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	pi->active_process_mask = 0;
++
++}
++
++static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
++							void **table)
++{
++	int ret = 0;
++
++	ret = cz_smu_download_pptable(adev, table);
++
++	return ret;
++}
++
++static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct SMU8_Fusion_ClkTable *clock_table;
++	struct atom_clock_dividers dividers;
++	void *table = NULL;
++	uint8_t i = 0;
++	int ret = 0;
++
++	struct amdgpu_clock_voltage_dependency_table *vddc_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
++		&adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
++	struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
++		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
++	struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++	struct amdgpu_clock_voltage_dependency_table *acp_table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++
++	if (!pi->need_pptable_upload)
++		return 0;
++
++	ret = cz_dpm_download_pptable_from_smu(adev, &table);
++	if (ret) {
++		DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
++		return -EINVAL;
++	}
++
++	clock_table = (struct SMU8_Fusion_ClkTable *)table;
++	/* patch clock table */
++	if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
++			vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
++			uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
++			vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
++			acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
++		DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
++		return -EINVAL;
++	}
++
++	for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
++
++		/* vddc sclk */
++		clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
++			(i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
++		clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
++			(i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++				clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
++				false, &dividers);
++		if (ret)
++			return ret;
++		clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
++						(uint8_t)dividers.post_divider;
++
++		/* vddgfx sclk */
++		clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
++			(i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
++
++		/* acp breakdown */
++		clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
++			(i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
++		clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
++			(i < acp_table->count) ? acp_table->entries[i].clk : 0;
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++				clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
++				false, &dividers);
++		if (ret)
++			return ret;
++		clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
++						(uint8_t)dividers.post_divider;
++
++		/* uvd breakdown */
++		clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
++			(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
++		clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
++			(i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++				clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
++				false, &dividers);
++		if (ret)
++			return ret;
++		clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
++						(uint8_t)dividers.post_divider;
++
++		clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
++			(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
++		clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
++			(i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++				clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
++				false, &dividers);
++		if (ret)
++			return ret;
++		clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
++						(uint8_t)dividers.post_divider;
++
++		/* vce breakdown */
++		clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
++			(i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
++		clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
++			(i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
++		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++				clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
++				false, &dividers);
++		if (ret)
++			return ret;
++		clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
++						(uint8_t)dividers.post_divider;
++	}
++
++	/* its time to upload to SMU */
++	ret = cz_smu_upload_pptable(adev);
++	if (ret) {
++		DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void cz_init_sclk_limit(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	uint32_t clock = 0, level;
++
++	if (!table || !table->count) {
++		DRM_ERROR("Invalid Voltage Dependency table.\n");
++		return;
++	}
++
++	pi->sclk_dpm.soft_min_clk = 0;
++	pi->sclk_dpm.hard_min_clk = 0;
++	cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
++	level = cz_get_argument(adev);
++	if (level < table->count)
++		clock = table->entries[level].clk;
++	else {
++		DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
++		clock = table->entries[table->count - 1].clk;
++	}
++
++	pi->sclk_dpm.soft_max_clk = clock;
++	pi->sclk_dpm.hard_max_clk = clock;
++
++}
++
++static void cz_init_uvd_limit(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_uvd_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
++	uint32_t clock = 0, level;
++
++	if (!table || !table->count) {
++		DRM_ERROR("Invalid Voltage Dependency table.\n");
++		return;
++	}
++
++	pi->uvd_dpm.soft_min_clk = 0;
++	pi->uvd_dpm.hard_min_clk = 0;
++	cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
++	level = cz_get_argument(adev);
++	if (level < table->count)
++		clock = table->entries[level].vclk;
++	else {
++		DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
++		clock = table->entries[table->count - 1].vclk;
++	}
++
++	pi->uvd_dpm.soft_max_clk = clock;
++	pi->uvd_dpm.hard_max_clk = clock;
++
++}
++
++static void cz_init_vce_limit(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_vce_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
++	uint32_t clock = 0, level;
++
++	if (!table || !table->count) {
++		DRM_ERROR("Invalid Voltage Dependency table.\n");
++		return;
++	}
++
++	pi->vce_dpm.soft_min_clk = 0;
++	pi->vce_dpm.hard_min_clk = 0;
++	cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
++	level = cz_get_argument(adev);
++	if (level < table->count)
++		clock = table->entries[level].evclk;
++	else {
++		/* future BIOS would fix this error */
++		DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
++		clock = table->entries[table->count - 1].evclk;
++	}
++
++	pi->vce_dpm.soft_max_clk = clock;
++	pi->vce_dpm.hard_max_clk = clock;
++
++}
++
++static void cz_init_acp_limit(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
++	uint32_t clock = 0, level;
++
++	if (!table || !table->count) {
++		DRM_ERROR("Invalid Voltage Dependency table.\n");
++		return;
++	}
++
++	pi->acp_dpm.soft_min_clk = 0;
++	pi->acp_dpm.hard_min_clk = 0;
++	cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
++	level = cz_get_argument(adev);
++	if (level < table->count)
++		clock = table->entries[level].clk;
++	else {
++		DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
++		clock = table->entries[table->count - 1].clk;
++	}
++
++	pi->acp_dpm.soft_max_clk = clock;
++	pi->acp_dpm.hard_max_clk = clock;
++
++}
++
++static void cz_init_pg_state(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	pi->uvd_power_gated = false;
++	pi->vce_power_gated = false;
++	pi->acp_power_gated = false;
++
++}
++
++static void cz_init_sclk_threshold(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	pi->low_sclk_interrupt_threshold = 0;
++
++}
++
++static void cz_dpm_setup_asic(struct amdgpu_device *adev)
++{
++	cz_reset_ap_mask(adev);
++	cz_dpm_upload_pptable_to_smu(adev);
++	cz_init_sclk_limit(adev);
++	cz_init_uvd_limit(adev);
++	cz_init_vce_limit(adev);
++	cz_init_acp_limit(adev);
++	cz_init_pg_state(adev);
++	cz_init_sclk_threshold(adev);
++
++}
++
++static bool cz_check_smu_feature(struct amdgpu_device *adev,
++				uint32_t feature)
++{
++	uint32_t smu_feature = 0;
++	int ret;
++
++	ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_GetFeatureStatus, 0);
++	if (ret) {
++		DRM_ERROR("Failed to get SMU features from SMC.\n");
++		return false;
++	} else {
++		smu_feature = cz_get_argument(adev);
++		if (feature & smu_feature)
++			return true;
++	}
++
++	return false;
++}
++
++static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
++{
++	if (cz_check_smu_feature(adev,
++				SMU_EnabledFeatureScoreboard_SclkDpmOn))
++		return true;
++
++	return false;
++}
++
++static void cz_program_voting_clients(struct amdgpu_device *adev)
++{
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
++}
++
++static void cz_clear_voting_clients(struct amdgpu_device *adev)
++{
++	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
++}
++
++static int cz_start_dpm(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	if (amdgpu_dpm) {
++		ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
++		if (ret) {
++			DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int cz_stop_dpm(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	if (amdgpu_dpm && adev->pm.dpm_enabled) {
++		ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
++		if (ret) {
++			DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
++				uint32_t clock, uint16_t msg)
++{
++	int i = 0;
++	struct amdgpu_clock_voltage_dependency_table *table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++
++	switch (msg) {
++	case PPSMC_MSG_SetSclkSoftMin:
++	case PPSMC_MSG_SetSclkHardMin:
++		for (i = 0; i < table->count; i++)
++			if (clock <= table->entries[i].clk)
++				break;
++		if (i == table->count)
++			i = table->count - 1;
++		break;
++	case PPSMC_MSG_SetSclkSoftMax:
++	case PPSMC_MSG_SetSclkHardMax:
++		for (i = table->count - 1; i >= 0; i--)
++			if (clock >= table->entries[i].clk)
++				break;
++		if (i < 0)
++			i = 0;
++		break;
++	default:
++		break;
++	}
++
++	return i;
++}
++
++static int cz_program_bootup_state(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	uint32_t soft_min_clk = 0;
++	uint32_t soft_max_clk = 0;
++	int ret = 0;
++
++	pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
++	pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
++
++	soft_min_clk = cz_get_sclk_level(adev,
++				pi->sclk_dpm.soft_min_clk,
++				PPSMC_MSG_SetSclkSoftMin);
++	soft_max_clk = cz_get_sclk_level(adev,
++				pi->sclk_dpm.soft_max_clk,
++				PPSMC_MSG_SetSclkSoftMax);
++
++	ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
++	if (ret)
++		return -EINVAL;
++
++	ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
++	if (ret)
++		return -EINVAL;
++
++	return 0;
++}
++
++/* TODO */
++static int cz_disable_cgpg(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++/* TODO */
++static int cz_enable_cgpg(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++/* TODO */
++static int cz_program_pt_config_registers(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	uint32_t reg = 0;
++
++	if (pi->caps_sq_ramping) {
++		reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
++		if (enable)
++			reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
++		else
++			reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
++		WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
++	}
++	if (pi->caps_db_ramping) {
++		reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
++		if (enable)
++			reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
++		else
++			reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
++		WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
++	}
++	if (pi->caps_td_ramping) {
++		reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
++		if (enable)
++			reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
++		else
++			reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
++		WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
++	}
++	if (pi->caps_tcp_ramping) {
++		reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
++		if (enable)
++			reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
++		else
++			reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
++		WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
++	}
++
++}
++
++static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	int ret;
++
++	if (pi->caps_sq_ramping || pi->caps_db_ramping ||
++			pi->caps_td_ramping || pi->caps_tcp_ramping) {
++		if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
++			ret = cz_disable_cgpg(adev);
++			if (ret) {
++				DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
++				return -EINVAL;
++			}
++			adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
++		}
++
++		ret = cz_program_pt_config_registers(adev);
++		if (ret) {
++			DRM_ERROR("Di/Dt config failed\n");
++			return -EINVAL;
++		}
++		cz_do_enable_didt(adev, enable);
++
++		if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
++			ret = cz_enable_cgpg(adev);
++			if (ret) {
++				DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
++				return -EINVAL;
++			}
++			adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
++		}
++	}
++
++	return 0;
++}
++
++/* TODO */
++static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
++{
++}
++
++static void cz_update_current_ps(struct amdgpu_device *adev,
++					struct amdgpu_ps *rps)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct cz_ps *ps = cz_get_ps(rps);
++
++	pi->current_ps = *ps;
++	pi->current_rps = *rps;
++	pi->current_rps.ps_priv = ps;
++
++}
++
++static void cz_update_requested_ps(struct amdgpu_device *adev,
++					struct amdgpu_ps *rps)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct cz_ps *ps = cz_get_ps(rps);
++
++	pi->requested_ps = *ps;
++	pi->requested_rps = *rps;
++	pi->requested_rps.ps_priv = ps;
++
++}
++
++/* PP arbiter support needed TODO */
++static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
++					struct amdgpu_ps *new_rps,
++					struct amdgpu_ps *old_rps)
++{
++	struct cz_ps *ps = cz_get_ps(new_rps);
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_clock_and_voltage_limits *limits =
++		&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	/* 10kHz memory clock */
++	uint32_t mclk = 0;
++
++	ps->force_high = false;
++	ps->need_dfs_bypass = true;
++	pi->video_start = new_rps->dclk || new_rps->vclk ||
++				new_rps->evclk || new_rps->ecclk;
++
++	if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
++			ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
++		pi->battery_state = true;
++	else
++		pi->battery_state = false;
++
++	if (pi->caps_stable_power_state)
++		mclk = limits->mclk;
++
++	if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
++		ps->force_high = true;
++
++}
++
++static int cz_dpm_enable(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	/* renable will hang up SMU, so check first */
++	if (cz_check_for_dpm_enabled(adev))
++		return -EINVAL;
++
++	cz_program_voting_clients(adev);
++
++	ret = cz_start_dpm(adev);
++	if (ret) {
++		DRM_ERROR("Carrizo DPM enable failed\n");
++		return -EINVAL;
++	}
++
++	ret = cz_program_bootup_state(adev);
++	if (ret) {
++		DRM_ERROR("Carrizo bootup state program failed\n");
++		return -EINVAL;
++	}
++
++	ret = cz_enable_didt(adev, true);
++	if (ret) {
++		DRM_ERROR("Carrizo enable di/dt failed\n");
++		return -EINVAL;
++	}
++
++	cz_reset_acp_boot_level(adev);
++
++	cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
++
++	return 0;
++}
++
++static int cz_dpm_hw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (!amdgpu_dpm)
++		return 0;
++
++	mutex_lock(&adev->pm.mutex);
++
++	/* init smc in dpm hw init */
++	ret = cz_smu_init(adev);
++	if (ret) {
++		DRM_ERROR("amdgpu: smc initialization failed\n");
++		mutex_unlock(&adev->pm.mutex);
++		return ret;
++	}
++
++	/* do the actual fw loading */
++	ret = cz_smu_start(adev);
++	if (ret) {
++		DRM_ERROR("amdgpu: smc start failed\n");
++		mutex_unlock(&adev->pm.mutex);
++		return ret;
++	}
++
++	/* cz dpm setup asic */
++	cz_dpm_setup_asic(adev);
++
++	/* cz dpm enable */
++	ret = cz_dpm_enable(adev);
++	if (ret)
++		adev->pm.dpm_enabled = false;
++	else
++		adev->pm.dpm_enabled = true;
++
++	mutex_unlock(&adev->pm.mutex);
++
++	return 0;
++}
++
++static int cz_dpm_disable(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	if (!cz_check_for_dpm_enabled(adev))
++		return -EINVAL;
++
++	ret = cz_enable_didt(adev, false);
++	if (ret) {
++		DRM_ERROR("Carrizo disable di/dt failed\n");
++		return -EINVAL;
++	}
++
++	cz_clear_voting_clients(adev);
++	cz_stop_dpm(adev);
++	cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
++
++	return 0;
++}
++
++static int cz_dpm_hw_fini(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	mutex_lock(&adev->pm.mutex);
++
++	cz_smu_fini(adev);
++
++	if (adev->pm.dpm_enabled) {
++		ret = cz_dpm_disable(adev);
++		if (ret)
++			return -EINVAL;
++
++		adev->pm.dpm.current_ps =
++			adev->pm.dpm.requested_ps =
++			adev->pm.dpm.boot_ps;
++	}
++
++	adev->pm.dpm_enabled = false;
++
++	mutex_unlock(&adev->pm.mutex);
++
++	return 0;
++}
++
++static int cz_dpm_suspend(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	if (adev->pm.dpm_enabled) {
++		mutex_lock(&adev->pm.mutex);
++
++		ret = cz_dpm_disable(adev);
++		if (ret)
++			return -EINVAL;
++
++		adev->pm.dpm.current_ps =
++			adev->pm.dpm.requested_ps =
++			adev->pm.dpm.boot_ps;
++
++		mutex_unlock(&adev->pm.mutex);
++	}
++
++	return 0;
++}
++
++static int cz_dpm_resume(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	mutex_lock(&adev->pm.mutex);
++	ret = cz_smu_init(adev);
++	if (ret) {
++		DRM_ERROR("amdgpu: smc resume failed\n");
++		mutex_unlock(&adev->pm.mutex);
++		return ret;
++	}
++
++	/* do the actual fw loading */
++	ret = cz_smu_start(adev);
++	if (ret) {
++		DRM_ERROR("amdgpu: smc start failed\n");
++		mutex_unlock(&adev->pm.mutex);
++		return ret;
++	}
++
++	/* cz dpm setup asic */
++	cz_dpm_setup_asic(adev);
++
++	/* cz dpm enable */
++	ret = cz_dpm_enable(adev);
++	if (ret)
++		adev->pm.dpm_enabled = false;
++	else
++		adev->pm.dpm_enabled = true;
++
++	mutex_unlock(&adev->pm.mutex);
++	/* upon resume, re-compute the clocks */
++	if (adev->pm.dpm_enabled)
++		amdgpu_pm_compute_clocks(adev);
++
++	return 0;
++}
++
++static int cz_dpm_set_clockgating_state(struct amdgpu_device *adev,
++					enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int cz_dpm_set_powergating_state(struct amdgpu_device *adev,
++					enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++/* borrowed from KV, need future unify */
++static int cz_dpm_get_temperature(struct amdgpu_device *adev)
++{
++	int actual_temp = 0;
++	uint32_t temp = RREG32_SMC(0xC0300E0C);
++
++	if (temp)
++		actual_temp = 1000 * ((temp / 8) - 49);
++
++	return actual_temp;
++}
++
++static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
++	struct amdgpu_ps *new_ps = &requested_ps;
++
++	cz_update_requested_ps(adev, new_ps);
++	cz_apply_state_adjust_rules(adev, &pi->requested_rps,
++					&pi->current_rps);
++
++	return 0;
++}
++
++static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_clock_and_voltage_limits *limits =
++		&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
++	uint32_t clock, stable_ps_clock = 0;
++
++	clock = pi->sclk_dpm.soft_min_clk;
++
++	if (pi->caps_stable_power_state) {
++		stable_ps_clock = limits->sclk * 75 / 100;
++		if (clock < stable_ps_clock)
++			clock = stable_ps_clock;
++	}
++
++	if (clock != pi->sclk_dpm.soft_min_clk) {
++		pi->sclk_dpm.soft_min_clk = clock;
++		cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMin,
++				cz_get_sclk_level(adev, clock,
++					PPSMC_MSG_SetSclkSoftMin));
++	}
++
++	if (pi->caps_stable_power_state &&
++			pi->sclk_dpm.soft_max_clk != clock) {
++		pi->sclk_dpm.soft_max_clk = clock;
++		cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMax,
++				cz_get_sclk_level(adev, clock,
++					PPSMC_MSG_SetSclkSoftMax));
++	} else {
++		cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMax,
++				cz_get_sclk_level(adev,
++					pi->sclk_dpm.soft_max_clk,
++					PPSMC_MSG_SetSclkSoftMax));
++	}
++
++	return 0;
++}
++
++static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	if (pi->caps_sclk_ds) {
++		cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetMinDeepSleepSclk,
++				CZ_MIN_DEEP_SLEEP_SCLK);
++	}
++
++	return ret;
++}
++
++/* ?? without dal support, is this still needed in setpowerstate list*/
++static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	cz_send_msg_to_smc_with_parameter(adev,
++			PPSMC_MSG_SetWatermarkFrequency,
++			pi->sclk_dpm.soft_max_clk);
++
++	return ret;
++}
++
++static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	/* also depend on dal NBPStateDisableRequired */
++	if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
++		ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_EnableAllSmuFeatures,
++				NB_DPM_MASK);
++		if (ret) {
++			DRM_ERROR("amdgpu: nb dpm enable failed\n");
++			return ret;
++		}
++		pi->nb_dpm_enabled = true;
++	}
++
++	return ret;
++}
++
++static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
++							bool enable)
++{
++	if (enable)
++		cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
++	else
++		cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
++
++}
++
++static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct cz_ps *ps = &pi->requested_ps;
++
++	if (pi->sys_info.nb_dpm_enable) {
++		if (ps->force_high)
++			cz_dpm_nbdpm_lm_pstate_enable(adev, true);
++		else
++			cz_dpm_nbdpm_lm_pstate_enable(adev, false);
++	}
++
++	return ret;
++}
++
++/* with dpm enabled */
++static int cz_dpm_set_power_state(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	cz_dpm_update_sclk_limit(adev);
++	cz_dpm_set_deep_sleep_sclk_threshold(adev);
++	cz_dpm_set_watermark_threshold(adev);
++	cz_dpm_enable_nbdpm(adev);
++	cz_dpm_update_low_memory_pstate(adev);
++
++	return ret;
++}
++
++static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_ps *ps = &pi->requested_rps;
++
++	cz_update_current_ps(adev, ps);
++
++}
++
++static int cz_dpm_force_highest(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	int ret = 0;
++
++	if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
++		pi->sclk_dpm.soft_min_clk =
++			pi->sclk_dpm.soft_max_clk;
++		ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMin,
++				cz_get_sclk_level(adev,
++					pi->sclk_dpm.soft_min_clk,
++					PPSMC_MSG_SetSclkSoftMin));
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int cz_dpm_force_lowest(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	int ret = 0;
++
++	if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
++		pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
++		ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMax,
++				cz_get_sclk_level(adev,
++					pi->sclk_dpm.soft_max_clk,
++					PPSMC_MSG_SetSclkSoftMax));
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	if (!pi->max_sclk_level) {
++		cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
++		pi->max_sclk_level = cz_get_argument(adev) + 1;
++	}
++
++	if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
++		DRM_ERROR("Invalid max sclk level!\n");
++		return -EINVAL;
++	}
++
++	return pi->max_sclk_level;
++}
++
++static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct amdgpu_clock_voltage_dependency_table *dep_table =
++		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
++	uint32_t level = 0;
++	int ret = 0;
++
++	pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
++	level = cz_dpm_get_max_sclk_level(adev) - 1;
++	if (level < dep_table->count)
++		pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
++	else
++		pi->sclk_dpm.soft_max_clk =
++			dep_table->entries[dep_table->count - 1].clk;
++
++	/* get min/max sclk soft value
++	 * notify SMU to execute */
++	ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMin,
++				cz_get_sclk_level(adev,
++					pi->sclk_dpm.soft_min_clk,
++					PPSMC_MSG_SetSclkSoftMin));
++	if (ret)
++		return ret;
++
++	ret = cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetSclkSoftMax,
++				cz_get_sclk_level(adev,
++					pi->sclk_dpm.soft_max_clk,
++					PPSMC_MSG_SetSclkSoftMax));
++	if (ret)
++		return ret;
++
++	DRM_INFO("DPM unforce state min=%d, max=%d.\n",
++			pi->sclk_dpm.soft_min_clk,
++			pi->sclk_dpm.soft_max_clk);
++
++	return 0;
++}
++
++static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
++				enum amdgpu_dpm_forced_level level)
++{
++	int ret = 0;
++
++	switch (level) {
++	case AMDGPU_DPM_FORCED_LEVEL_HIGH:
++		ret = cz_dpm_force_highest(adev);
++		if (ret)
++			return ret;
++		break;
++	case AMDGPU_DPM_FORCED_LEVEL_LOW:
++		ret = cz_dpm_force_lowest(adev);
++		if (ret)
++			return ret;
++		break;
++	case AMDGPU_DPM_FORCED_LEVEL_AUTO:
++		ret = cz_dpm_unforce_dpm_levels(adev);
++		if (ret)
++			return ret;
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++
++/* fix me, display configuration change lists here
++ * mostly dal related*/
++static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
++{
++}
++
++static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++	struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
++
++	if (low)
++		return requested_state->levels[0].sclk;
++	else
++		return requested_state->levels[requested_state->num_levels - 1].sclk;
++
++}
++
++static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
++{
++	struct cz_power_info *pi = cz_get_pi(adev);
++
++	return pi->sys_info.bootup_uma_clk;
++}
++
++const struct amdgpu_ip_funcs cz_dpm_ip_funcs = {
++	.early_init = cz_dpm_early_init,
++	.late_init = NULL,
++	.sw_init = cz_dpm_sw_init,
++	.sw_fini = cz_dpm_sw_fini,
++	.hw_init = cz_dpm_hw_init,
++	.hw_fini = cz_dpm_hw_fini,
++	.suspend = cz_dpm_suspend,
++	.resume = cz_dpm_resume,
++	.is_idle = NULL,
++	.wait_for_idle = NULL,
++	.soft_reset = NULL,
++	.print_status = NULL,
++	.set_clockgating_state = cz_dpm_set_clockgating_state,
++	.set_powergating_state = cz_dpm_set_powergating_state,
++};
++
++static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
++	.get_temperature = cz_dpm_get_temperature,
++	.pre_set_power_state = cz_dpm_pre_set_power_state,
++	.set_power_state = cz_dpm_set_power_state,
++	.post_set_power_state = cz_dpm_post_set_power_state,
++	.display_configuration_changed = cz_dpm_display_configuration_changed,
++	.get_sclk = cz_dpm_get_sclk,
++	.get_mclk = cz_dpm_get_mclk,
++	.print_power_state = cz_dpm_print_power_state,
++	.debugfs_print_current_performance_level =
++				cz_dpm_debugfs_print_current_performance_level,
++	.force_performance_level = cz_dpm_force_dpm_level,
++	.vblank_too_short = NULL,
++	.powergate_uvd = NULL,
++};
++
++static void cz_dpm_set_funcs(struct amdgpu_device *adev)
++{
++	if (NULL == adev->pm.funcs)
++		adev->pm.funcs = &cz_dpm_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
+new file mode 100644
+index 0000000..ed6449d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
+@@ -0,0 +1,235 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __CZ_DPM_H__
++#define __CZ_DPM_H__
++
++#include "smu8_fusion.h"
++
++#define CZ_AT_DFLT					30
++#define CZ_NUM_NBPSTATES				4
++#define CZ_NUM_NBPMEMORY_CLOCK				2
++#define CZ_MAX_HARDWARE_POWERLEVELS			8
++#define CZ_MAX_DISPLAY_CLOCK_LEVEL			8
++#define CZ_MAX_DISPLAYPHY_IDS				10
++
++#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0			0x3FFFC102
++
++#define SMC_RAM_END					0x40000
++
++#define DPMFlags_SCLK_Enabled				0x00000001
++#define DPMFlags_UVD_Enabled				0x00000002
++#define DPMFlags_VCE_Enabled				0x00000004
++#define DPMFlags_ACP_Enabled				0x00000008
++#define DPMFlags_ForceHighestValid			0x40000000
++#define DPMFlags_Debug					0x80000000
++
++/* Do not change the following, it is also defined in SMU8.h */
++#define SMU_EnabledFeatureScoreboard_AcpDpmOn		0x00000001
++#define SMU_EnabledFeatureScoreboard_SclkDpmOn		0x00100000
++#define SMU_EnabledFeatureScoreboard_UvdDpmOn		0x00800000
++#define SMU_EnabledFeatureScoreboard_VceDpmOn		0x01000000
++
++/* temporary solution to SetMinDeepSleepSclk
++ * should indicate by display adaptor
++ * 10k Hz unit*/
++#define CZ_MIN_DEEP_SLEEP_SCLK				800
++
++enum cz_pt_config_reg_type {
++	CZ_CONFIGREG_MMR = 0,
++	CZ_CONFIGREG_SMC_IND,
++	CZ_CONFIGREG_DIDT_IND,
++	CZ_CONFIGREG_CACHE,
++	CZ_CONFIGREG_MAX
++};
++
++struct cz_pt_config_reg {
++	uint32_t offset;
++	uint32_t mask;
++	uint32_t shift;
++	uint32_t value;
++	enum cz_pt_config_reg_type type;
++};
++
++struct cz_dpm_entry {
++	uint32_t	soft_min_clk;
++	uint32_t	hard_min_clk;
++	uint32_t	soft_max_clk;
++	uint32_t	hard_max_clk;
++};
++
++struct cz_pl {
++	uint32_t sclk;
++	uint8_t vddc_index;
++	uint8_t ds_divider_index;
++	uint8_t ss_divider_index;
++	uint8_t allow_gnb_slow;
++	uint8_t force_nbp_state;
++	uint8_t display_wm;
++	uint8_t vce_wm;
++};
++
++struct cz_ps {
++	struct cz_pl levels[CZ_MAX_HARDWARE_POWERLEVELS];
++	uint32_t num_levels;
++	bool need_dfs_bypass;
++	uint8_t dpm0_pg_nb_ps_lo;
++	uint8_t dpm0_pg_nb_ps_hi;
++	uint8_t dpmx_nb_ps_lo;
++	uint8_t dpmx_nb_ps_hi;
++	bool force_high;
++};
++
++struct cz_displayphy_entry {
++	uint8_t phy_present;
++	uint8_t active_lane_mapping;
++	uint8_t display_conf_type;
++	uint8_t num_active_lanes;
++};
++
++struct cz_displayphy_info {
++	bool phy_access_initialized;
++	struct cz_displayphy_entry entries[CZ_MAX_DISPLAYPHY_IDS];
++};
++
++struct cz_sys_info {
++	uint32_t bootup_uma_clk;
++	uint32_t bootup_sclk;
++	uint32_t dentist_vco_freq;
++	uint32_t nb_dpm_enable;
++	uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK];
++	uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
++	uint8_t nbp_voltage_index[CZ_NUM_NBPSTATES];
++	uint32_t display_clock[CZ_MAX_DISPLAY_CLOCK_LEVEL];
++	uint16_t bootup_nb_voltage_index;
++	uint8_t htc_tmp_lmt;
++	uint8_t htc_hyst_lmt;
++	uint32_t uma_channel_number;
++};
++
++struct cz_power_info {
++	uint32_t active_target[CZ_MAX_HARDWARE_POWERLEVELS];
++	struct cz_sys_info sys_info;
++	struct cz_pl boot_pl;
++	bool disable_nb_ps3_in_battery;
++	bool battery_state;
++	uint32_t lowest_valid;
++	uint32_t highest_valid;
++	uint16_t high_voltage_threshold;
++	/* smc offsets */
++	uint32_t sram_end;
++	uint32_t dpm_table_start;
++	uint32_t soft_regs_start;
++	/* dpm SMU tables */
++	uint8_t uvd_level_count;
++	uint8_t vce_level_count;
++	uint8_t acp_level_count;
++	uint32_t fps_high_threshold;
++	uint32_t fps_low_threshold;
++	/* dpm table */
++	uint32_t dpm_flags;
++	struct cz_dpm_entry sclk_dpm;
++	struct cz_dpm_entry uvd_dpm;
++	struct cz_dpm_entry vce_dpm;
++	struct cz_dpm_entry acp_dpm;
++
++	uint8_t uvd_boot_level;
++	uint8_t uvd_interval;
++	uint8_t vce_boot_level;
++	uint8_t vce_interval;
++	uint8_t acp_boot_level;
++	uint8_t acp_interval;
++
++	uint8_t graphics_boot_level;
++	uint8_t graphics_interval;
++	uint8_t graphics_therm_throttle_enable;
++	uint8_t graphics_voltage_change_enable;
++	uint8_t graphics_clk_slow_enable;
++	uint8_t graphics_clk_slow_divider;
++
++	uint32_t low_sclk_interrupt_threshold;
++	bool uvd_power_gated;
++	bool vce_power_gated;
++	bool acp_power_gated;
++
++	uint32_t active_process_mask;
++
++	uint32_t mgcg_cgtt_local0;
++	uint32_t mgcg_cgtt_local1;
++	uint32_t clock_slow_down_step;
++	uint32_t skip_clock_slow_down;
++	bool enable_nb_ps_policy;
++	uint32_t voting_clients;
++	uint32_t voltage_drop_threshold;
++	uint32_t gfx_pg_threshold;
++	uint32_t max_sclk_level;
++	/* flags */
++	bool didt_enabled;
++	bool video_start;
++	bool cac_enabled;
++	bool bapm_enabled;
++	bool nb_dpm_enabled_by_driver;
++	bool nb_dpm_enabled;
++	bool auto_thermal_throttling_enabled;
++	bool dpm_enabled;
++	bool need_pptable_upload;
++	/* caps */
++	bool caps_cac;
++	bool caps_power_containment;
++	bool caps_sq_ramping;
++	bool caps_db_ramping;
++	bool caps_td_ramping;
++	bool caps_tcp_ramping;
++	bool caps_sclk_throttle_low_notification;
++	bool caps_fps;
++	bool caps_uvd_dpm;
++	bool caps_uvd_pg;
++	bool caps_vce_dpm;
++	bool caps_vce_pg;
++	bool caps_acp_dpm;
++	bool caps_acp_pg;
++	bool caps_stable_power_state;
++	bool caps_enable_dfs_bypass;
++	bool caps_sclk_ds;
++	bool caps_voltage_island;
++	/* power state */
++	struct amdgpu_ps current_rps;
++	struct cz_ps current_ps;
++	struct amdgpu_ps requested_rps;
++	struct cz_ps requested_ps;
++
++	bool uvd_power_down;
++	bool vce_power_down;
++	bool acp_power_down;
++};
++
++/* cz_smc.c */
++uint32_t cz_get_argument(struct amdgpu_device *adev);
++int cz_send_msg_to_smc(struct amdgpu_device *adev, uint16_t msg);
++int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++			uint16_t msg, uint32_t parameter);
++int cz_read_smc_sram_dword(struct amdgpu_device *adev,
++			uint32_t smc_address, uint32_t *value, uint32_t limit);
++int cz_smu_upload_pptable(struct amdgpu_device *adev);
++int cz_smu_download_pptable(struct amdgpu_device *adev, void **table);
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+new file mode 100644
+index 0000000..80d508e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+@@ -0,0 +1,435 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++#include "vid.h"
++
++#include "oss/oss_3_0_1_d.h"
++#include "oss/oss_3_0_1_sh_mask.h"
++
++#include "bif/bif_5_1_d.h"
++#include "bif/bif_5_1_sh_mask.h"
++
++/*
++ * Interrupts
++ * Starting with r6xx, interrupts are handled via a ring buffer.
++ * Ring buffers are areas of GPU accessible memory that the GPU
++ * writes interrupt vectors into and the host reads vectors out of.
++ * There is a rptr (read pointer) that determines where the
++ * host is currently reading, and a wptr (write pointer)
++ * which determines where the GPU has written.  When the
++ * pointers are equal, the ring is idle.  When the GPU
++ * writes vectors to the ring buffer, it increments the
++ * wptr.  When there is an interrupt, the host then starts
++ * fetching commands and processing them until the pointers are
++ * equal again at which point it updates the rptr.
++ */
++
++static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
++
++/**
++ * cz_ih_enable_interrupts - Enable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Enable the interrupt ring buffer (VI).
++ */
++static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_cntl = RREG32(mmIH_CNTL);
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++
++	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
++	WREG32(mmIH_CNTL, ih_cntl);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	adev->irq.ih.enabled = true;
++}
++
++/**
++ * cz_ih_disable_interrupts - Disable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable the interrupt ring buffer (VI).
++ */
++static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++	u32 ih_cntl = RREG32(mmIH_CNTL);
++
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
++	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	WREG32(mmIH_CNTL, ih_cntl);
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++	adev->irq.ih.enabled = false;
++	adev->irq.ih.rptr = 0;
++}
++
++/**
++ * cz_ih_irq_init - init and enable the interrupt ring
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate a ring buffer for the interrupt controller,
++ * enable the RLC, disable interrupts, enable the IH
++ * ring buffer and enable it (VI).
++ * Called at device load and reume.
++ * Returns 0 for success, errors for failure.
++ */
++static int cz_ih_irq_init(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	int rb_bufsz;
++	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
++	u64 wptr_off;
++
++	/* disable irqs */
++	cz_ih_disable_interrupts(adev);
++
++	/* setup interrupt control */
++	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
++	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
++	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
++	 */
++	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
++	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
++	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
++	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
++
++	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
++	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
++
++	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
++	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
++
++	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
++
++	/* set the writeback address whether it's enabled or not */
++	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
++	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
++	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
++
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++
++	/* Default settings for IH_CNTL (disabled at first) */
++	ih_cntl = RREG32(mmIH_CNTL);
++	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
++
++	if (adev->irq.msi_enabled)
++		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
++	WREG32(mmIH_CNTL, ih_cntl);
++
++	pci_set_master(adev->pdev);
++
++	/* enable interrupts */
++	cz_ih_enable_interrupts(adev);
++
++	return ret;
++}
++
++/**
++ * cz_ih_irq_disable - disable interrupts
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable interrupts on the hw (VI).
++ */
++static void cz_ih_irq_disable(struct amdgpu_device *adev)
++{
++	cz_ih_disable_interrupts(adev);
++
++	/* Wait and acknowledge irq */
++	mdelay(1);
++}
++
++/**
++ * cz_ih_get_wptr - get the IH ring buffer wptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Get the IH ring buffer wptr from either the register
++ * or the writeback memory buffer (VI).  Also check for
++ * ring buffer overflow and deal with it.
++ * Used by cz_irq_process(VI).
++ * Returns the value of the wptr.
++ */
++static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
++{
++	u32 wptr, tmp;
++
++	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
++
++	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
++		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
++		/* When a ring buffer overflow happen start parsing interrupt
++		 * from the last not overwritten vector (wptr + 16). Hopefully
++		 * this should allow us to catchup.
++		 */
++		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
++			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
++		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
++		tmp = RREG32(mmIH_RB_CNTL);
++		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
++		WREG32(mmIH_RB_CNTL, tmp);
++	}
++	return (wptr & adev->irq.ih.ptr_mask);
++}
++
++/**
++ * cz_ih_decode_iv - decode an interrupt vector
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Decodes the interrupt vector at the current rptr
++ * position and also advance the position.
++ */
++static void cz_ih_decode_iv(struct amdgpu_device *adev,
++				 struct amdgpu_iv_entry *entry)
++{
++	/* wptr/rptr are in bytes! */
++	u32 ring_index = adev->irq.ih.rptr >> 2;
++	uint32_t dw[4];
++	
++	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
++	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
++	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
++	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
++
++	entry->src_id = dw[0] & 0xff;
++	entry->src_data = dw[1] & 0xfffffff;
++	entry->ring_id = dw[2] & 0xff;
++	entry->vm_id = (dw[2] >> 8) & 0xff;
++	entry->pas_id = (dw[2] >> 16) & 0xffff;
++
++	/* wptr/rptr are in bytes! */
++	adev->irq.ih.rptr += 16;
++}
++
++/**
++ * cz_ih_set_rptr - set the IH ring buffer rptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set the IH ring buffer rptr.
++ */
++static void cz_ih_set_rptr(struct amdgpu_device *adev)
++{
++	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
++}
++
++static int cz_ih_early_init(struct amdgpu_device *adev)
++{
++	cz_ih_set_interrupt_funcs(adev);
++	return 0;
++}
++
++static int cz_ih_sw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_init(adev);
++
++	return r;
++}
++
++static int cz_ih_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_irq_fini(adev);
++	amdgpu_ih_ring_fini(adev);
++
++	return 0;
++}
++
++static int cz_ih_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = cz_ih_irq_init(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static int cz_ih_hw_fini(struct amdgpu_device *adev)
++{
++	cz_ih_irq_disable(adev);
++
++	return 0;
++}
++
++static int cz_ih_suspend(struct amdgpu_device *adev)
++{
++	return cz_ih_hw_fini(adev);
++}
++
++static int cz_ih_resume(struct amdgpu_device *adev)
++{
++	return cz_ih_hw_init(adev);
++}
++
++static bool cz_ih_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
++		return false;
++
++	return true;
++}
++
++static int cz_ih_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS);
++		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void cz_ih_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "CZ IH registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL));
++	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL2));
++	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
++		 RREG32(mmIH_CNTL));
++	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
++		 RREG32(mmIH_RB_CNTL));
++	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
++		 RREG32(mmIH_RB_BASE));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_LO));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_HI));
++	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
++		 RREG32(mmIH_RB_RPTR));
++	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR));
++}
++
++static int cz_ih_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
++						SOFT_RESET_IH, 1);
++
++	if (srbm_soft_reset) {
++		cz_ih_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		cz_ih_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int cz_ih_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	// TODO
++	return 0;
++}
++
++static int cz_ih_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	// TODO
++	return 0;
++}
++
++const struct amdgpu_ip_funcs cz_ih_ip_funcs = {
++	.early_init = cz_ih_early_init,
++	.late_init = NULL,
++	.sw_init = cz_ih_sw_init,
++	.sw_fini = cz_ih_sw_fini,
++	.hw_init = cz_ih_hw_init,
++	.hw_fini = cz_ih_hw_fini,
++	.suspend = cz_ih_suspend,
++	.resume = cz_ih_resume,
++	.is_idle = cz_ih_is_idle,
++	.wait_for_idle = cz_ih_wait_for_idle,
++	.soft_reset = cz_ih_soft_reset,
++	.print_status = cz_ih_print_status,
++	.set_clockgating_state = cz_ih_set_clockgating_state,
++	.set_powergating_state = cz_ih_set_powergating_state,
++};
++
++static const struct amdgpu_ih_funcs cz_ih_funcs = {
++	.get_wptr = cz_ih_get_wptr,
++	.decode_iv = cz_ih_decode_iv,
++	.set_rptr = cz_ih_set_rptr
++};
++
++static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
++{
++	if (adev->irq.ih_funcs == NULL)
++		adev->irq.ih_funcs = &cz_ih_funcs;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
+new file mode 100644
+index 0000000..1bce136
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __CZ_IH_H__
++#define __CZ_IH_H__
++
++extern const struct amdgpu_ip_funcs cz_ih_ip_funcs;
++
++#endif /* __CZ_IH_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h
+new file mode 100644
+index 0000000..273616a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h
+@@ -0,0 +1,185 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef CZ_PP_SMC_H
++#define CZ_PP_SMC_H
++
++#pragma pack(push, 1)
++
++/* Fan control algorithm:*/
++#define FDO_MODE_HARDWARE 0
++#define FDO_MODE_PIECE_WISE_LINEAR 1
++
++enum FAN_CONTROL {
++    FAN_CONTROL_FUZZY,
++    FAN_CONTROL_TABLE
++};
++
++enum DPM_ARRAY {
++    DPM_ARRAY_HARD_MAX,
++    DPM_ARRAY_HARD_MIN,
++    DPM_ARRAY_SOFT_MAX,
++    DPM_ARRAY_SOFT_MIN
++};
++
++/*
++ * Return codes for driver to SMC communication.
++ * Leave these #define-s, enums might not be exactly 8-bits on the microcontroller.
++ */
++#define PPSMC_Result_OK             ((uint16_t)0x01)
++#define PPSMC_Result_NoMore         ((uint16_t)0x02)
++#define PPSMC_Result_NotNow         ((uint16_t)0x03)
++#define PPSMC_Result_Failed         ((uint16_t)0xFF)
++#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
++#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
++
++#define PPSMC_isERROR(x)            ((uint16_t)0x80 & (x))
++
++/*
++ * Supported driver messages
++ */
++#define PPSMC_MSG_Test                        ((uint16_t) 0x1)
++#define PPSMC_MSG_GetFeatureStatus            ((uint16_t) 0x2)
++#define PPSMC_MSG_EnableAllSmuFeatures        ((uint16_t) 0x3)
++#define PPSMC_MSG_DisableAllSmuFeatures       ((uint16_t) 0x4)
++#define PPSMC_MSG_OptimizeBattery             ((uint16_t) 0x5)
++#define PPSMC_MSG_MaximizePerf                ((uint16_t) 0x6)
++#define PPSMC_MSG_UVDPowerOFF                 ((uint16_t) 0x7)
++#define PPSMC_MSG_UVDPowerON                  ((uint16_t) 0x8)
++#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x9)
++#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0xA)
++#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0xB)
++#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0xC)
++#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0xD)
++#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0xE)
++#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0xF)
++#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x10)
++#define PPSMC_MSG_SetMinDeepSleepSclk         ((uint16_t) 0x11)
++#define PPSMC_MSG_SetSclkSoftMin              ((uint16_t) 0x12)
++#define PPSMC_MSG_SetSclkSoftMax              ((uint16_t) 0x13)
++#define PPSMC_MSG_SetSclkHardMin              ((uint16_t) 0x14)
++#define PPSMC_MSG_SetSclkHardMax              ((uint16_t) 0x15)
++#define PPSMC_MSG_SetLclkSoftMin              ((uint16_t) 0x16)
++#define PPSMC_MSG_SetLclkSoftMax              ((uint16_t) 0x17)
++#define PPSMC_MSG_SetLclkHardMin              ((uint16_t) 0x18)
++#define PPSMC_MSG_SetLclkHardMax              ((uint16_t) 0x19)
++#define PPSMC_MSG_SetUvdSoftMin               ((uint16_t) 0x1A)
++#define PPSMC_MSG_SetUvdSoftMax               ((uint16_t) 0x1B)
++#define PPSMC_MSG_SetUvdHardMin               ((uint16_t) 0x1C)
++#define PPSMC_MSG_SetUvdHardMax               ((uint16_t) 0x1D)
++#define PPSMC_MSG_SetEclkSoftMin              ((uint16_t) 0x1E)
++#define PPSMC_MSG_SetEclkSoftMax              ((uint16_t) 0x1F)
++#define PPSMC_MSG_SetEclkHardMin              ((uint16_t) 0x20)
++#define PPSMC_MSG_SetEclkHardMax              ((uint16_t) 0x21)
++#define PPSMC_MSG_SetAclkSoftMin              ((uint16_t) 0x22)
++#define PPSMC_MSG_SetAclkSoftMax              ((uint16_t) 0x23)
++#define PPSMC_MSG_SetAclkHardMin              ((uint16_t) 0x24)
++#define PPSMC_MSG_SetAclkHardMax              ((uint16_t) 0x25)
++#define PPSMC_MSG_SetNclkSoftMin              ((uint16_t) 0x26)
++#define PPSMC_MSG_SetNclkSoftMax              ((uint16_t) 0x27)
++#define PPSMC_MSG_SetNclkHardMin              ((uint16_t) 0x28)
++#define PPSMC_MSG_SetNclkHardMax              ((uint16_t) 0x29)
++#define PPSMC_MSG_SetPstateSoftMin            ((uint16_t) 0x2A)
++#define PPSMC_MSG_SetPstateSoftMax            ((uint16_t) 0x2B)
++#define PPSMC_MSG_SetPstateHardMin            ((uint16_t) 0x2C)
++#define PPSMC_MSG_SetPstateHardMax            ((uint16_t) 0x2D)
++#define PPSMC_MSG_DisableLowMemoryPstate      ((uint16_t) 0x2E)
++#define PPSMC_MSG_EnableLowMemoryPstate       ((uint16_t) 0x2F)
++#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x30)
++#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x31)
++#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x32)
++#define PPSMC_MSG_DriverDramAddrHi            ((uint16_t) 0x33)
++#define PPSMC_MSG_DriverDramAddrLo            ((uint16_t) 0x34)
++#define PPSMC_MSG_CondExecDramAddrHi          ((uint16_t) 0x35)
++#define PPSMC_MSG_CondExecDramAddrLo          ((uint16_t) 0x36)
++#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x37)
++#define PPSMC_MSG_DriverResetMode             ((uint16_t) 0x38)
++#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x39)
++#define PPSMC_MSG_SetDisplayPhyConfig         ((uint16_t) 0x3A)
++#define PPSMC_MSG_GetMaxSclkLevel             ((uint16_t) 0x3B)
++#define PPSMC_MSG_GetMaxLclkLevel             ((uint16_t) 0x3C)
++#define PPSMC_MSG_GetMaxUvdLevel              ((uint16_t) 0x3D)
++#define PPSMC_MSG_GetMaxEclkLevel             ((uint16_t) 0x3E)
++#define PPSMC_MSG_GetMaxAclkLevel             ((uint16_t) 0x3F)
++#define PPSMC_MSG_GetMaxNclkLevel             ((uint16_t) 0x40)
++#define PPSMC_MSG_GetMaxPstate                ((uint16_t) 0x41)
++#define PPSMC_MSG_DramAddrHiVirtual           ((uint16_t) 0x42)
++#define PPSMC_MSG_DramAddrLoVirtual           ((uint16_t) 0x43)
++#define PPSMC_MSG_DramAddrHiPhysical          ((uint16_t) 0x44)
++#define PPSMC_MSG_DramAddrLoPhysical          ((uint16_t) 0x45)
++#define PPSMC_MSG_DramBufferSize              ((uint16_t) 0x46)
++#define PPSMC_MSG_SetMmPwrLogDramAddrHi       ((uint16_t) 0x47)
++#define PPSMC_MSG_SetMmPwrLogDramAddrLo       ((uint16_t) 0x48)
++#define PPSMC_MSG_SetClkTableAddrHi           ((uint16_t) 0x49)
++#define PPSMC_MSG_SetClkTableAddrLo           ((uint16_t) 0x4A)
++#define PPSMC_MSG_GetConservativePowerLimit   ((uint16_t) 0x4B)
++
++#define PPSMC_MSG_InitJobs                    ((uint16_t) 0x252)
++#define PPSMC_MSG_ExecuteJob                  ((uint16_t) 0x254)
++
++#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
++#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
++
++#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
++#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
++
++#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
++#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
++
++#define PPSMC_MSG_AllowLowSclkInterrupt       ((uint16_t) 0x184)
++#define PPSMC_MSG_MmPowerMonitorStart         ((uint16_t) 0x18F)
++#define PPSMC_MSG_MmPowerMonitorStop          ((uint16_t) 0x190)
++#define PPSMC_MSG_MmPowerMonitorRestart       ((uint16_t) 0x191)
++
++#define PPSMC_MSG_SetClockGateMask            ((uint16_t) 0x260)
++#define PPSMC_MSG_SetFpsThresholdLo           ((uint16_t) 0x264)
++#define PPSMC_MSG_SetFpsThresholdHi           ((uint16_t) 0x265)
++#define PPSMC_MSG_SetLowSclkIntrThreshold     ((uint16_t) 0x266)
++
++#define PPSMC_MSG_ClkTableXferToDram          ((uint16_t) 0x267)
++#define PPSMC_MSG_ClkTableXferToSmu           ((uint16_t) 0x268)
++#define PPSMC_MSG_GetAverageGraphicsActivity  ((uint16_t) 0x269)
++#define PPSMC_MSG_GetAverageGioActivity       ((uint16_t) 0x26A)
++#define PPSMC_MSG_SetLoggerBufferSize         ((uint16_t) 0x26B)
++#define PPSMC_MSG_SetLoggerAddressHigh        ((uint16_t) 0x26C)
++#define PPSMC_MSG_SetLoggerAddressLow         ((uint16_t) 0x26D)
++#define PPSMC_MSG_SetWatermarkFrequency       ((uint16_t) 0x26E)
++
++/* REMOVE LATER*/
++#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
++
++/* Feature Enable Masks*/
++#define NB_DPM_MASK             0x00000800
++#define VDDGFX_MASK             0x00800000
++#define VCE_DPM_MASK            0x00400000
++#define ACP_DPM_MASK            0x00040000
++#define UVD_DPM_MASK            0x00010000
++#define GFX_CU_PG_MASK          0x00004000
++#define SCLK_DPM_MASK           0x00080000
++
++#if !defined(SMC_MICROCODE)
++#pragma pack(pop)
++
++#endif
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
+new file mode 100644
+index 0000000..a72ffc7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
+@@ -0,0 +1,962 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "smu8.h"
++#include "smu8_fusion.h"
++#include "cz_ppsmc.h"
++#include "cz_smumgr.h"
++#include "smu_ucode_xfer_cz.h"
++#include "amdgpu_ucode.h"
++
++#include "smu/smu_8_0_d.h"
++#include "smu/smu_8_0_sh_mask.h"
++#include "gca/gfx_8_0_d.h"
++#include "gca/gfx_8_0_sh_mask.h"
++
++uint32_t cz_get_argument(struct amdgpu_device *adev)
++{
++	return RREG32(mmSMU_MP1_SRBM2P_ARG_0);
++}
++
++static struct cz_smu_private_data *cz_smu_get_priv(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv =
++			(struct cz_smu_private_data *)(adev->smu.priv);
++
++	return priv;
++}
++
++int cz_send_msg_to_smc_async(struct amdgpu_device *adev, u16 msg)
++{
++	int i;
++	u32 content = 0, tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0),
++				SMU_MP1_SRBM2P_RESP_0, CONTENT);
++		if (content != tmp)
++			break;
++		udelay(1);
++	}
++
++	/* timeout means wrong logic*/
++	if (i == adev->usec_timeout)
++		return -EINVAL;
++
++	WREG32(mmSMU_MP1_SRBM2P_RESP_0, 0);
++	WREG32(mmSMU_MP1_SRBM2P_MSG_0, msg);
++
++	return 0;
++}
++
++int cz_send_msg_to_smc(struct amdgpu_device *adev, u16 msg)
++{
++	int i;
++	u32 content = 0, tmp = 0;
++
++	if (cz_send_msg_to_smc_async(adev, msg))
++		return -EINVAL;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0),
++				SMU_MP1_SRBM2P_RESP_0, CONTENT);
++		if (content != tmp)
++			break;
++		udelay(1);
++	}
++
++	/* timeout means wrong logic*/
++	if (i == adev->usec_timeout)
++		return -EINVAL;
++
++	if (PPSMC_Result_OK != tmp) {
++		dev_err(adev->dev, "SMC Failed to send Message.\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int cz_send_msg_to_smc_with_parameter_async(struct amdgpu_device *adev,
++						u16 msg, u32 parameter)
++{
++	WREG32(mmSMU_MP1_SRBM2P_ARG_0, parameter);
++	return cz_send_msg_to_smc_async(adev, msg);
++}
++
++int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++						u16 msg, u32 parameter)
++{
++	WREG32(mmSMU_MP1_SRBM2P_ARG_0, parameter);
++	return cz_send_msg_to_smc(adev, msg);
++}
++
++static int cz_set_smc_sram_address(struct amdgpu_device *adev,
++						u32 smc_address, u32 limit)
++{
++	if (smc_address & 3)
++		return -EINVAL;
++	if ((smc_address + 3) > limit)
++		return -EINVAL;
++
++	WREG32(mmMP0PUB_IND_INDEX_0, SMN_MP1_SRAM_START_ADDR + smc_address);
++
++	return 0;
++}
++
++int cz_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
++						u32 *value, u32 limit)
++{
++	int ret;
++
++	ret = cz_set_smc_sram_address(adev, smc_address, limit);
++	if (ret)
++		return ret;
++
++	*value = RREG32(mmMP0PUB_IND_DATA_0);
++
++	return 0;
++}
++
++int cz_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
++						u32 value, u32 limit)
++{
++	int ret;
++
++	ret = cz_set_smc_sram_address(adev, smc_address, limit);
++	if (ret)
++		return ret;
++
++	WREG32(mmMP0PUB_IND_DATA_0, value);
++
++	return 0;
++}
++
++static int cz_smu_request_load_fw(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++
++	uint32_t smc_addr = SMU8_FIRMWARE_HEADER_LOCATION +
++			offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
++
++	cz_write_smc_sram_dword(adev, smc_addr, 0, smc_addr + 4);
++
++	/*prepare toc buffers*/
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_DriverDramAddrHi,
++				priv->toc_buffer.mc_addr_high);
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_DriverDramAddrLo,
++				priv->toc_buffer.mc_addr_low);
++	cz_send_msg_to_smc(adev, PPSMC_MSG_InitJobs);
++
++	/*execute jobs*/
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_ExecuteJob,
++				priv->toc_entry_aram);
++
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_ExecuteJob,
++				priv->toc_entry_power_profiling_index);
++
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_ExecuteJob,
++				priv->toc_entry_initialize_index);
++
++	return 0;
++}
++
++/*
++ *Check if the FW has been loaded, SMU will not return if loading
++ *has not finished.
++ */
++static int cz_smu_check_fw_load_finish(struct amdgpu_device *adev,
++						uint32_t fw_mask)
++{
++	int i;
++	uint32_t index = SMN_MP1_SRAM_START_ADDR +
++			SMU8_FIRMWARE_HEADER_LOCATION +
++			offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
++
++	WREG32(mmMP0PUB_IND_INDEX, index);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (fw_mask == (RREG32(mmMP0PUB_IND_DATA) & fw_mask))
++			break;
++		udelay(1);
++	}
++
++	if (i >= adev->usec_timeout) {
++		dev_err(adev->dev,
++		"SMU check loaded firmware failed, expecting 0x%x, getting 0x%x",
++		fw_mask, RREG32(mmMP0PUB_IND_DATA));
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/*
++ * interfaces for different ip blocks to check firmware loading status
++ * 0 for success otherwise failed
++ */
++static int cz_smu_check_finished(struct amdgpu_device *adev,
++							enum AMDGPU_UCODE_ID id)
++{
++	switch (id) {
++	case AMDGPU_UCODE_ID_SDMA0:
++		if (adev->smu.fw_flags & AMDGPU_SDMA0_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_SDMA1:
++		if (adev->smu.fw_flags & AMDGPU_SDMA1_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_CP_CE:
++		if (adev->smu.fw_flags & AMDGPU_CPCE_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_CP_PFP:
++		if (adev->smu.fw_flags & AMDGPU_CPPFP_UCODE_LOADED)
++			return 0;
++	case AMDGPU_UCODE_ID_CP_ME:
++		if (adev->smu.fw_flags & AMDGPU_CPME_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_CP_MEC1:
++		if (adev->smu.fw_flags & AMDGPU_CPMEC1_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_CP_MEC2:
++		if (adev->smu.fw_flags & AMDGPU_CPMEC2_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_RLC_G:
++		if (adev->smu.fw_flags & AMDGPU_CPRLC_UCODE_LOADED)
++			return 0;
++		break;
++	case AMDGPU_UCODE_ID_MAXIMUM:
++	default:
++		break;
++	}
++
++	return 1;
++}
++
++static int cz_load_mec_firmware(struct amdgpu_device *adev)
++{
++	struct amdgpu_firmware_info *ucode =
++				&adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
++	uint32_t reg_data;
++	uint32_t tmp;
++
++	if (ucode->fw == NULL)
++		return -EINVAL;
++
++	/* Disable MEC parsing/prefetching */
++	tmp = RREG32(mmCP_MEC_CNTL);
++	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
++	WREG32(mmCP_MEC_CNTL, tmp);
++
++	tmp = RREG32(mmCP_CPC_IC_BASE_CNTL);
++	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
++	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
++	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
++	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
++	WREG32(mmCP_CPC_IC_BASE_CNTL, tmp);
++
++	reg_data = lower_32_bits(ucode->mc_addr) &
++			REG_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
++	WREG32(mmCP_CPC_IC_BASE_LO, reg_data);
++
++	reg_data = upper_32_bits(ucode->mc_addr) &
++			REG_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
++	WREG32(mmCP_CPC_IC_BASE_HI, reg_data);
++
++	return 0;
++}
++
++int cz_smu_start(struct amdgpu_device *adev)
++{
++	int ret = 0;
++
++	uint32_t fw_to_check = UCODE_ID_RLC_G_MASK |
++				UCODE_ID_SDMA0_MASK |
++				UCODE_ID_SDMA1_MASK |
++				UCODE_ID_CP_CE_MASK |
++				UCODE_ID_CP_ME_MASK |
++				UCODE_ID_CP_PFP_MASK |
++				UCODE_ID_CP_MEC_JT1_MASK |
++				UCODE_ID_CP_MEC_JT2_MASK;
++
++	cz_smu_request_load_fw(adev);
++	ret = cz_smu_check_fw_load_finish(adev, fw_to_check);
++	if (ret)
++		return ret;
++
++	/* manually load MEC firmware for CZ */
++	if (adev->asic_type == CHIP_CARRIZO) {
++		ret = cz_load_mec_firmware(adev);
++		if (ret) {
++			dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret);
++			return ret;
++		}
++	}
++
++	/* setup fw load flag */
++	adev->smu.fw_flags = AMDGPU_SDMA0_UCODE_LOADED |
++				AMDGPU_SDMA1_UCODE_LOADED |
++				AMDGPU_CPCE_UCODE_LOADED |
++				AMDGPU_CPPFP_UCODE_LOADED |
++				AMDGPU_CPME_UCODE_LOADED |
++				AMDGPU_CPMEC1_UCODE_LOADED |
++				AMDGPU_CPMEC2_UCODE_LOADED |
++				AMDGPU_CPRLC_UCODE_LOADED;
++
++	return ret;
++}
++
++static uint32_t cz_convert_fw_type(uint32_t fw_type)
++{
++	enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
++
++	switch (fw_type) {
++	case UCODE_ID_SDMA0:
++		result = AMDGPU_UCODE_ID_SDMA0;
++		break;
++	case UCODE_ID_SDMA1:
++		result = AMDGPU_UCODE_ID_SDMA1;
++		break;
++	case UCODE_ID_CP_CE:
++		result = AMDGPU_UCODE_ID_CP_CE;
++		break;
++	case UCODE_ID_CP_PFP:
++		result = AMDGPU_UCODE_ID_CP_PFP;
++		break;
++	case UCODE_ID_CP_ME:
++		result = AMDGPU_UCODE_ID_CP_ME;
++		break;
++	case UCODE_ID_CP_MEC_JT1:
++	case UCODE_ID_CP_MEC_JT2:
++		result = AMDGPU_UCODE_ID_CP_MEC1;
++		break;
++	case UCODE_ID_RLC_G:
++		result = AMDGPU_UCODE_ID_RLC_G;
++		break;
++	default:
++		DRM_ERROR("UCode type is out of range!");
++	}
++
++	return result;
++}
++
++static uint8_t cz_smu_translate_firmware_enum_to_arg(
++			enum cz_scratch_entry firmware_enum)
++{
++	uint8_t ret = 0;
++
++	switch (firmware_enum) {
++	case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0:
++		ret = UCODE_ID_SDMA0;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
++		ret = UCODE_ID_SDMA1;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
++		ret = UCODE_ID_CP_CE;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
++		ret = UCODE_ID_CP_PFP;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME:
++		ret = UCODE_ID_CP_ME;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
++		ret = UCODE_ID_CP_MEC_JT1;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
++		ret = UCODE_ID_CP_MEC_JT2;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
++		ret = UCODE_ID_GMCON_RENG;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G:
++		ret = UCODE_ID_RLC_G;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
++		ret = UCODE_ID_RLC_SCRATCH;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
++		ret = UCODE_ID_RLC_SRM_ARAM;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
++		ret = UCODE_ID_RLC_SRM_DRAM;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
++		ret = UCODE_ID_DMCU_ERAM;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
++		ret = UCODE_ID_DMCU_IRAM;
++		break;
++	case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
++		ret = TASK_ARG_INIT_MM_PWR_LOG;
++		break;
++	case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
++	case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
++	case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
++	case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
++	case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START:
++	case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
++		ret = TASK_ARG_REG_MMIO;
++		break;
++	case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
++		ret = TASK_ARG_INIT_CLK_TABLE;
++		break;
++	}
++
++	return ret;
++}
++
++static int cz_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
++					enum cz_scratch_entry firmware_enum,
++					struct cz_buffer_entry *entry)
++{
++	uint64_t gpu_addr;
++	uint32_t data_size;
++	uint8_t ucode_id = cz_smu_translate_firmware_enum_to_arg(firmware_enum);
++	enum AMDGPU_UCODE_ID id = cz_convert_fw_type(ucode_id);
++	struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
++	const struct gfx_firmware_header_v1_0 *header;
++
++	if (ucode->fw == NULL)
++		return -EINVAL;
++
++	gpu_addr  = ucode->mc_addr;
++	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
++	data_size = le32_to_cpu(header->header.ucode_size_bytes);
++
++	if ((firmware_enum == CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1) ||
++	    (firmware_enum == CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2)) {
++		gpu_addr += le32_to_cpu(header->jt_offset) << 2;
++		data_size = le32_to_cpu(header->jt_size) << 2;
++	}
++
++	entry->mc_addr_low = lower_32_bits(gpu_addr);
++	entry->mc_addr_high = upper_32_bits(gpu_addr);
++	entry->data_size = data_size;
++	entry->firmware_ID = firmware_enum;
++
++	return 0;
++}
++
++static int cz_smu_populate_single_scratch_entry(struct amdgpu_device *adev,
++					enum cz_scratch_entry scratch_type,
++					uint32_t size_in_byte,
++					struct cz_buffer_entry *entry)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	uint64_t mc_addr = (((uint64_t) priv->smu_buffer.mc_addr_high) << 32) |
++						priv->smu_buffer.mc_addr_low;
++	mc_addr += size_in_byte;
++
++	priv->smu_buffer_used_bytes += size_in_byte;
++	entry->data_size = size_in_byte;
++	entry->kaddr = priv->smu_buffer.kaddr + priv->smu_buffer_used_bytes;
++	entry->mc_addr_low = lower_32_bits(mc_addr);
++	entry->mc_addr_high = upper_32_bits(mc_addr);
++	entry->firmware_ID = scratch_type;
++
++	return 0;
++}
++
++static int cz_smu_populate_single_ucode_load_task(struct amdgpu_device *adev,
++						enum cz_scratch_entry firmware_enum,
++						bool is_last)
++{
++	uint8_t i;
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
++	struct SMU_Task *task = &toc->tasks[priv->toc_entry_used_count++];
++
++	task->type = TASK_TYPE_UCODE_LOAD;
++	task->arg = cz_smu_translate_firmware_enum_to_arg(firmware_enum);
++	task->next = is_last ? END_OF_TASK_LIST : priv->toc_entry_used_count;
++
++	for (i = 0; i < priv->driver_buffer_length; i++)
++		if (priv->driver_buffer[i].firmware_ID == firmware_enum)
++			break;
++
++	if (i >= priv->driver_buffer_length) {
++		dev_err(adev->dev, "Invalid Firmware Type\n");
++		return -EINVAL;
++	}
++
++	task->addr.low = priv->driver_buffer[i].mc_addr_low;
++	task->addr.high = priv->driver_buffer[i].mc_addr_high;
++	task->size_bytes = priv->driver_buffer[i].data_size;
++
++	return 0;
++}
++
++static int cz_smu_populate_single_scratch_task(struct amdgpu_device *adev,
++						enum cz_scratch_entry firmware_enum,
++						uint8_t type, bool is_last)
++{
++	uint8_t i;
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
++	struct SMU_Task *task = &toc->tasks[priv->toc_entry_used_count++];
++
++	task->type = type;
++	task->arg = cz_smu_translate_firmware_enum_to_arg(firmware_enum);
++	task->next = is_last ? END_OF_TASK_LIST : priv->toc_entry_used_count;
++
++	for (i = 0; i < priv->scratch_buffer_length; i++)
++		if (priv->scratch_buffer[i].firmware_ID == firmware_enum)
++			break;
++
++	if (i >= priv->scratch_buffer_length) {
++		dev_err(adev->dev, "Invalid Firmware Type\n");
++		return -EINVAL;
++	}
++
++	task->addr.low = priv->scratch_buffer[i].mc_addr_low;
++	task->addr.high = priv->scratch_buffer[i].mc_addr_high;
++	task->size_bytes = priv->scratch_buffer[i].data_size;
++
++	if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == firmware_enum) {
++		struct cz_ih_meta_data *pIHReg_restore =
++			(struct cz_ih_meta_data *)priv->scratch_buffer[i].kaddr;
++		pIHReg_restore->command =
++			METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD;
++	}
++
++	return 0;
++}
++
++static int cz_smu_construct_toc_for_rlc_aram_save(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	priv->toc_entry_aram = priv->toc_entry_used_count;
++	cz_smu_populate_single_scratch_task(adev,
++			CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
++			TASK_TYPE_UCODE_SAVE, true);
++
++	return 0;
++}
++
++static int cz_smu_construct_toc_for_vddgfx_enter(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
++
++	toc->JobList[JOB_GFX_SAVE] = (uint8_t)priv->toc_entry_used_count;
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
++				TASK_TYPE_UCODE_SAVE, false);
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
++				TASK_TYPE_UCODE_SAVE, true);
++
++	return 0;
++}
++
++static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
++
++	toc->JobList[JOB_GFX_RESTORE] = (uint8_t)priv->toc_entry_used_count;
++
++	/* populate ucode */
++	if (adev->firmware.smu_load) {
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
++	}
++
++	/* populate scratch */
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
++				TASK_TYPE_UCODE_LOAD, false);
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
++				TASK_TYPE_UCODE_LOAD, false);
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
++				TASK_TYPE_UCODE_LOAD, true);
++
++	return 0;
++}
++
++static int cz_smu_construct_toc_for_power_profiling(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++
++	priv->toc_entry_power_profiling_index = priv->toc_entry_used_count;
++
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
++				TASK_TYPE_INITIALIZE, true);
++	return 0;
++}
++
++static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++
++	priv->toc_entry_initialize_index = priv->toc_entry_used_count;
++
++	if (adev->firmware.smu_load) {
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
++		cz_smu_populate_single_ucode_load_task(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
++	}
++
++	return 0;
++}
++
++static int cz_smu_construct_toc_for_clock_table(struct amdgpu_device *adev)
++{
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++
++	priv->toc_entry_clock_table = priv->toc_entry_used_count;
++
++	cz_smu_populate_single_scratch_task(adev,
++				CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
++				TASK_TYPE_INITIALIZE, true);
++
++	return 0;
++}
++
++static int cz_smu_initialize_toc_empty_job_list(struct amdgpu_device *adev)
++{
++	int i;
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++	struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
++
++	for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
++		toc->JobList[i] = (uint8_t)IGNORE_JOB;
++
++	return 0;
++}
++
++/*
++ * cz smu uninitialization
++ */
++int cz_smu_fini(struct amdgpu_device *adev)
++{
++	amdgpu_bo_unref(&adev->smu.toc_buf);
++	amdgpu_bo_unref(&adev->smu.smu_buf);
++	kfree(adev->smu.priv);
++	adev->smu.priv = NULL;
++	if (adev->firmware.smu_load)
++		amdgpu_ucode_fini_bo(adev);
++
++	return 0;
++}
++
++int cz_smu_download_pptable(struct amdgpu_device *adev, void **table)
++{
++	uint8_t i;
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++
++	for (i = 0; i < priv->scratch_buffer_length; i++)
++		if (priv->scratch_buffer[i].firmware_ID ==
++				CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
++			break;
++
++	if (i >= priv->scratch_buffer_length) {
++		dev_err(adev->dev, "Invalid Scratch Type\n");
++		return -EINVAL;
++	}
++
++	*table = (struct SMU8_Fusion_ClkTable *)priv->scratch_buffer[i].kaddr;
++
++	/* prepare buffer for pptable */
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetClkTableAddrHi,
++				priv->scratch_buffer[i].mc_addr_high);
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetClkTableAddrLo,
++				priv->scratch_buffer[i].mc_addr_low);
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_ExecuteJob,
++				priv->toc_entry_clock_table);
++
++	/* actual downloading */
++	cz_send_msg_to_smc(adev, PPSMC_MSG_ClkTableXferToDram);
++
++	return 0;
++}
++
++int cz_smu_upload_pptable(struct amdgpu_device *adev)
++{
++	uint8_t i;
++	struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
++
++	for (i = 0; i < priv->scratch_buffer_length; i++)
++		if (priv->scratch_buffer[i].firmware_ID ==
++				CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
++			break;
++
++	if (i >= priv->scratch_buffer_length) {
++		dev_err(adev->dev, "Invalid Scratch Type\n");
++		return -EINVAL;
++	}
++
++	/* prepare SMU */
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetClkTableAddrHi,
++				priv->scratch_buffer[i].mc_addr_high);
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_SetClkTableAddrLo,
++				priv->scratch_buffer[i].mc_addr_low);
++	cz_send_msg_to_smc_with_parameter(adev,
++				PPSMC_MSG_ExecuteJob,
++				priv->toc_entry_clock_table);
++
++	/* actual uploading */
++	cz_send_msg_to_smc(adev, PPSMC_MSG_ClkTableXferToSmu);
++
++	return 0;
++}
++
++/*
++ * cz smumgr functions initialization
++ */
++static const struct amdgpu_smumgr_funcs cz_smumgr_funcs = {
++	.check_fw_load_finish = cz_smu_check_finished,
++	.request_smu_load_fw = NULL,
++	.request_smu_specific_fw = NULL,
++};
++
++/*
++ * cz smu initialization
++ */
++int cz_smu_init(struct amdgpu_device *adev)
++{
++	int ret = -EINVAL;
++	uint64_t mc_addr = 0;
++	struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
++	struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;
++	void *toc_buf_ptr = NULL;
++	void *smu_buf_ptr = NULL;
++
++	struct cz_smu_private_data *priv =
++		kzalloc(sizeof(struct cz_smu_private_data), GFP_KERNEL);
++	if (priv == NULL)
++		return -ENOMEM;
++
++	/* allocate firmware buffers */
++	if (adev->firmware.smu_load)
++		amdgpu_ucode_init_bo(adev);
++
++	adev->smu.priv = priv;
++	adev->smu.fw_flags = 0;
++	priv->toc_buffer.data_size = 4096;
++
++	priv->smu_buffer.data_size =
++				ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
++				ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) +
++				ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) +
++				ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
++				ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
++
++	/* prepare toc buffer and smu buffer:
++	* 1. create amdgpu_bo for toc buffer and smu buffer
++	* 2. pin mc address
++	* 3. map kernel virtual address
++	*/
++	ret = amdgpu_bo_create(adev, priv->toc_buffer.data_size, PAGE_SIZE,
++				true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, toc_buf);
++
++	if (ret) {
++		dev_err(adev->dev, "(%d) SMC TOC buffer allocation failed\n", ret);
++		return ret;
++	}
++
++	ret = amdgpu_bo_create(adev, priv->smu_buffer.data_size, PAGE_SIZE,
++				true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, smu_buf);
++
++	if (ret) {
++		dev_err(adev->dev, "(%d) SMC Internal buffer allocation failed\n", ret);
++		return ret;
++	}
++
++	/* toc buffer reserve/pin/map */
++	ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
++	if (ret) {
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		dev_err(adev->dev, "(%d) SMC TOC buffer reserve failed\n", ret);
++		return ret;
++	}
++
++	ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_GTT, &mc_addr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.toc_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		dev_err(adev->dev, "(%d) SMC TOC buffer pin failed\n", ret);
++		return ret;
++	}
++
++	ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
++	if (ret)
++		goto smu_init_failed;
++
++	amdgpu_bo_unreserve(adev->smu.toc_buf);
++
++	priv->toc_buffer.mc_addr_low = lower_32_bits(mc_addr);
++	priv->toc_buffer.mc_addr_high = upper_32_bits(mc_addr);
++	priv->toc_buffer.kaddr = toc_buf_ptr;
++
++	/* smu buffer reserve/pin/map */
++	ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);
++	if (ret) {
++		amdgpu_bo_unref(&adev->smu.smu_buf);
++		dev_err(adev->dev, "(%d) SMC Internal buffer reserve failed\n", ret);
++		return ret;
++	}
++
++	ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_GTT, &mc_addr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.smu_buf);
++		amdgpu_bo_unref(&adev->smu.smu_buf);
++		dev_err(adev->dev, "(%d) SMC Internal buffer pin failed\n", ret);
++		return ret;
++	}
++
++	ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr);
++	if (ret)
++		goto smu_init_failed;
++
++	amdgpu_bo_unreserve(adev->smu.smu_buf);
++
++	priv->smu_buffer.mc_addr_low = lower_32_bits(mc_addr);
++	priv->smu_buffer.mc_addr_high = upper_32_bits(mc_addr);
++	priv->smu_buffer.kaddr = smu_buf_ptr;
++
++	if (adev->firmware.smu_load) {
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++		if (cz_smu_populate_single_firmware_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
++				&priv->driver_buffer[priv->driver_buffer_length++]))
++			goto smu_init_failed;
++	}
++
++	if (cz_smu_populate_single_scratch_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
++				UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
++				&priv->scratch_buffer[priv->scratch_buffer_length++]))
++		goto smu_init_failed;
++	if (cz_smu_populate_single_scratch_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
++				UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
++				&priv->scratch_buffer[priv->scratch_buffer_length++]))
++		goto smu_init_failed;
++	if (cz_smu_populate_single_scratch_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
++				UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
++				&priv->scratch_buffer[priv->scratch_buffer_length++]))
++		goto smu_init_failed;
++	if (cz_smu_populate_single_scratch_entry(adev,
++				CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
++				sizeof(struct SMU8_MultimediaPowerLogData),
++				&priv->scratch_buffer[priv->scratch_buffer_length++]))
++		goto smu_init_failed;
++	if (cz_smu_populate_single_scratch_entry(adev,
++				CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
++				sizeof(struct SMU8_Fusion_ClkTable),
++				&priv->scratch_buffer[priv->scratch_buffer_length++]))
++		goto smu_init_failed;
++
++	cz_smu_initialize_toc_empty_job_list(adev);
++	cz_smu_construct_toc_for_rlc_aram_save(adev);
++	cz_smu_construct_toc_for_vddgfx_enter(adev);
++	cz_smu_construct_toc_for_vddgfx_exit(adev);
++	cz_smu_construct_toc_for_power_profiling(adev);
++	cz_smu_construct_toc_for_bootup(adev);
++	cz_smu_construct_toc_for_clock_table(adev);
++	/* init the smumgr functions */
++	adev->smu.smumgr_funcs = &cz_smumgr_funcs;
++
++	return 0;
++
++smu_init_failed:
++	amdgpu_bo_unref(toc_buf);
++	amdgpu_bo_unref(smu_buf);
++
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
+new file mode 100644
+index 0000000..924d355
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
+@@ -0,0 +1,94 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __CZ_SMC_H__
++#define __CZ_SMC_H__
++
++#define MAX_NUM_FIRMWARE                        8
++#define MAX_NUM_SCRATCH                         11
++#define CZ_SCRATCH_SIZE_NONGFX_CLOCKGATING      1024
++#define CZ_SCRATCH_SIZE_NONGFX_GOLDENSETTING    2048
++#define CZ_SCRATCH_SIZE_SDMA_METADATA           1024
++#define CZ_SCRATCH_SIZE_IH                      ((2*256+1)*4)
++
++enum cz_scratch_entry {
++	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
++	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
++	CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
++	CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
++	CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
++	CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
++	CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
++	CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
++	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
++	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
++	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
++	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
++	CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
++	CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
++	CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
++	CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
++	CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
++	CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
++	CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
++	CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START,
++	CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
++	CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
++};
++
++struct cz_buffer_entry {
++	uint32_t	data_size;
++	uint32_t	mc_addr_low;
++	uint32_t	mc_addr_high;
++	void		*kaddr;
++	enum cz_scratch_entry firmware_ID;
++};
++
++struct cz_register_index_data_pair {
++	uint32_t	offset;
++	uint32_t	value;
++};
++
++struct cz_ih_meta_data {
++	uint32_t	command;
++	struct cz_register_index_data_pair register_index_value_pair[1];
++};
++
++struct cz_smu_private_data {
++	uint8_t		driver_buffer_length;
++	uint8_t		scratch_buffer_length;
++	uint16_t	toc_entry_used_count;
++	uint16_t 	toc_entry_initialize_index;
++	uint16_t	toc_entry_power_profiling_index;
++	uint16_t	toc_entry_aram;
++	uint16_t	toc_entry_ih_register_restore_task_index;
++	uint16_t	toc_entry_clock_table;
++	uint16_t	ih_register_restore_task_size;
++	uint16_t	smu_buffer_used_bytes;
++
++	struct cz_buffer_entry  toc_buffer;
++	struct cz_buffer_entry  smu_buffer;
++	struct cz_buffer_entry  driver_buffer[MAX_NUM_FIRMWARE];
++	struct cz_buffer_entry  scratch_buffer[MAX_NUM_SCRATCH];
++};
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+new file mode 100644
+index 0000000..d412291
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+@@ -0,0 +1,3871 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_i2c.h"
++#include "vid.h"
++#include "atom.h"
++#include "amdgpu_atombios.h"
++#include "atombios_crtc.h"
++#include "atombios_encoders.h"
++#include "amdgpu_pll.h"
++#include "amdgpu_connectors.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++#include "dce/dce_10_0_enum.h"
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
++static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
++
++static const u32 crtc_offsets[] =
++{
++	CRTC0_REGISTER_OFFSET,
++	CRTC1_REGISTER_OFFSET,
++	CRTC2_REGISTER_OFFSET,
++	CRTC3_REGISTER_OFFSET,
++	CRTC4_REGISTER_OFFSET,
++	CRTC5_REGISTER_OFFSET,
++	CRTC6_REGISTER_OFFSET
++};
++
++static const u32 hpd_offsets[] =
++{
++	HPD0_REGISTER_OFFSET,
++	HPD1_REGISTER_OFFSET,
++	HPD2_REGISTER_OFFSET,
++	HPD3_REGISTER_OFFSET,
++	HPD4_REGISTER_OFFSET,
++	HPD5_REGISTER_OFFSET
++};
++
++static const uint32_t dig_offsets[] = {
++	DIG0_REGISTER_OFFSET,
++	DIG1_REGISTER_OFFSET,
++	DIG2_REGISTER_OFFSET,
++	DIG3_REGISTER_OFFSET,
++	DIG4_REGISTER_OFFSET,
++	DIG5_REGISTER_OFFSET,
++	DIG6_REGISTER_OFFSET
++};
++
++static const struct {
++	uint32_t        reg;
++	uint32_t        vblank;
++	uint32_t        vline;
++	uint32_t        hpd;
++
++} interrupt_status_offsets[] = { {
++	.reg = mmDISP_INTERRUPT_STATUS,
++	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
++} };
++
++static const u32 golden_settings_tonga_a11[] =
++{
++	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
++	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
++	mmFBC_MISC, 0x1f311fff, 0x12300000,
++	mmHDMI_CONTROL, 0x31000111, 0x00000011,
++};
++
++static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_TONGA:
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_tonga_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
++		break;
++	default:
++		break;
++	}
++}
++
++static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
++				     u32 block_offset, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
++	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
++	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
++
++	return r;
++}
++
++static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
++				      u32 block_offset, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
++	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
++}
++
++static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
++{
++	if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
++			CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
++		return true;
++	else
++		return false;
++}
++
++static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
++{
++	u32 pos1, pos2;
++
++	pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++	pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++	if (pos1 != pos2)
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v10_0_vblank_wait - vblank wait asic callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @crtc: crtc to wait for vblank on
++ *
++ * Wait for vblank on the requested crtc (evergreen+).
++ */
++static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
++{
++	unsigned i = 0;
++
++	if (crtc >= adev->mode_info.num_crtc)
++		return;
++
++	if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
++		return;
++
++	/* depending on when we hit vblank, we may be close to active; if so,
++	 * wait for another frame.
++	 */
++	while (dce_v10_0_is_in_vblank(adev, crtc)) {
++		if (i++ % 100 == 0) {
++			if (!dce_v10_0_is_counter_moving(adev, crtc))
++				break;
++		}
++	}
++
++	while (!dce_v10_0_is_in_vblank(adev, crtc)) {
++		if (i++ % 100 == 0) {
++			if (!dce_v10_0_is_counter_moving(adev, crtc))
++				break;
++		}
++	}
++}
++
++static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
++{
++	if (crtc >= adev->mode_info.num_crtc)
++		return 0;
++	else
++		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
++}
++
++/**
++ * dce_v10_0_page_flip - pageflip callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @crtc_id: crtc to cleanup pageflip on
++ * @crtc_base: new address of the crtc (GPU MC address)
++ *
++ * Does the actual pageflip (evergreen+).
++ * During vblank we take the crtc lock and wait for the update_pending
++ * bit to go high, when it does, we release the lock, and allow the
++ * double buffered update to take place.
++ * Returns the current update pending status.
++ */
++static void dce_v10_0_page_flip(struct amdgpu_device *adev,
++			      int crtc_id, u64 crtc_base)
++{
++	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
++	int i;
++
++	/* Lock the graphics update lock */
++	tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
++	WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
++
++	/* update the scanout addresses */
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(crtc_base));
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       lower_32_bits(crtc_base));
++
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(crtc_base));
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       lower_32_bits(crtc_base));
++
++	/* Wait for update_pending to go high. */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
++				GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
++			break;
++		udelay(1);
++	}
++	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
++
++	/* Unlock the lock, so double-buffering can take place inside vblank */
++	tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
++	WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
++					u32 *vbl, u32 *position)
++{
++	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
++		return -EINVAL;
++
++	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
++	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++	return 0;
++}
++
++/**
++ * dce_v10_0_hpd_sense - hpd sense callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @hpd: hpd (hotplug detect) pin
++ *
++ * Checks if a digital monitor is connected (evergreen+).
++ * Returns true if connected, false if not connected.
++ */
++static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
++			       enum amdgpu_hpd_id hpd)
++{
++	int idx;
++	bool connected = false;
++
++	switch (hpd) {
++	case AMDGPU_HPD_1:
++		idx = 0;
++		break;
++	case AMDGPU_HPD_2:
++		idx = 1;
++		break;
++	case AMDGPU_HPD_3:
++		idx = 2;
++		break;
++	case AMDGPU_HPD_4:
++		idx = 3;
++		break;
++	case AMDGPU_HPD_5:
++		idx = 4;
++		break;
++	case AMDGPU_HPD_6:
++		idx = 5;
++		break;
++	default:
++		return connected;
++	}
++
++	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
++	    DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
++		connected = true;
++
++	return connected;
++}
++
++/**
++ * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @hpd: hpd (hotplug detect) pin
++ *
++ * Set the polarity of the hpd pin (evergreen+).
++ */
++static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
++				      enum amdgpu_hpd_id hpd)
++{
++	u32 tmp;
++	bool connected = dce_v10_0_hpd_sense(adev, hpd);
++	int idx;
++
++	switch (hpd) {
++	case AMDGPU_HPD_1:
++		idx = 0;
++		break;
++	case AMDGPU_HPD_2:
++		idx = 1;
++		break;
++	case AMDGPU_HPD_3:
++		idx = 2;
++		break;
++	case AMDGPU_HPD_4:
++		idx = 3;
++		break;
++	case AMDGPU_HPD_5:
++		idx = 4;
++		break;
++	case AMDGPU_HPD_6:
++		idx = 5;
++		break;
++	default:
++		return;
++	}
++
++	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
++	if (connected)
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
++	else
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
++	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
++}
++
++/**
++ * dce_v10_0_hpd_init - hpd setup callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup the hpd pins used by the card (evergreen+).
++ * Enable the pin, set the polarity, and enable the hpd interrupts.
++ */
++static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++	u32 tmp;
++	int idx;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
++		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
++			/* don't try to enable hpd on eDP or LVDS avoid breaking the
++			 * aux dp channel on imac and help (but not completely fix)
++			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
++			 * also avoid interrupt storms during dpms.
++			 */
++			continue;
++		}
++
++		switch (amdgpu_connector->hpd.hpd) {
++		case AMDGPU_HPD_1:
++			idx = 0;
++			break;
++		case AMDGPU_HPD_2:
++			idx = 1;
++			break;
++		case AMDGPU_HPD_3:
++			idx = 2;
++			break;
++		case AMDGPU_HPD_4:
++			idx = 3;
++			break;
++		case AMDGPU_HPD_5:
++			idx = 4;
++			break;
++		case AMDGPU_HPD_6:
++			idx = 5;
++			break;
++		default:
++			continue;
++		}
++
++		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
++		WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
++
++		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
++				    DC_HPD_CONNECT_INT_DELAY,
++				    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
++				    DC_HPD_DISCONNECT_INT_DELAY,
++				    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
++		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
++
++		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
++		amdgpu_irq_get(adev, &adev->hpd_irq,
++			       amdgpu_connector->hpd.hpd);
++	}
++}
++
++/**
++ * dce_v10_0_hpd_fini - hpd tear down callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down the hpd pins used by the card (evergreen+).
++ * Disable the hpd interrupts.
++ */
++static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++	u32 tmp;
++	int idx;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		switch (amdgpu_connector->hpd.hpd) {
++		case AMDGPU_HPD_1:
++			idx = 0;
++			break;
++		case AMDGPU_HPD_2:
++			idx = 1;
++			break;
++		case AMDGPU_HPD_3:
++			idx = 2;
++			break;
++		case AMDGPU_HPD_4:
++			idx = 3;
++			break;
++		case AMDGPU_HPD_5:
++			idx = 4;
++			break;
++		case AMDGPU_HPD_6:
++			idx = 5;
++			break;
++		default:
++			continue;
++		}
++
++		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
++		WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
++
++		amdgpu_irq_put(adev, &adev->hpd_irq,
++			       amdgpu_connector->hpd.hpd);
++	}
++}
++
++static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
++{
++	return mmDC_GPIO_HPD_A;
++}
++
++static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
++{
++	u32 crtc_hung = 0;
++	u32 crtc_status[6];
++	u32 i, j, tmp;
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
++		if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
++			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
++			crtc_hung |= (1 << i);
++		}
++	}
++
++	for (j = 0; j < 10; j++) {
++		for (i = 0; i < adev->mode_info.num_crtc; i++) {
++			if (crtc_hung & (1 << i)) {
++				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
++				if (tmp != crtc_status[i])
++					crtc_hung &= ~(1 << i);
++			}
++		}
++		if (crtc_hung == 0)
++			return false;
++		udelay(100);
++	}
++
++	return true;
++}
++
++static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
++				     struct amdgpu_mode_mc_save *save)
++{
++	u32 crtc_enabled, tmp;
++	int i;
++
++	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
++	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
++
++	/* disable VGA render */
++	tmp = RREG32(mmVGA_RENDER_CONTROL);
++	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++	WREG32(mmVGA_RENDER_CONTROL, tmp);
++
++	/* blank the display controllers */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
++					     CRTC_CONTROL, CRTC_MASTER_EN);
++		if (crtc_enabled) {
++#if 0
++			u32 frame_count;
++			int j;
++
++			save->crtc_enabled[i] = true;
++			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
++				amdgpu_display_vblank_wait(adev, i);
++				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
++				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			}
++			/* wait for the next frame */
++			frame_count = amdgpu_display_vblank_get_counter(adev, i);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
++					break;
++				udelay(1);
++			}
++			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
++				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
++				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
++				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
++				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++			}
++#else
++			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
++			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
++			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			save->crtc_enabled[i] = false;
++			/* ***** */
++#endif
++		} else {
++			save->crtc_enabled[i] = false;
++		}
++	}
++}
++
++static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
++				       struct amdgpu_mode_mc_save *save)
++{
++	u32 tmp, frame_count;
++	int i, j;
++
++	/* update crtc base addresses */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
++		       upper_32_bits(adev->mc.vram_start));
++		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
++		       upper_32_bits(adev->mc.vram_start));
++		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
++		       (u32)adev->mc.vram_start);
++		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
++		       (u32)adev->mc.vram_start);
++
++		if (save->crtc_enabled[i]) {
++			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
++				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
++				WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
++				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
++				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
++				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
++				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++			}
++			for (j = 0; j < adev->usec_timeout; j++) {
++				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
++					break;
++				udelay(1);
++			}
++			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
++			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			/* wait for the next frame */
++			frame_count = amdgpu_display_vblank_get_counter(adev, i);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
++					break;
++				udelay(1);
++			}
++		}
++	}
++
++	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
++	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
++
++	/* Unlock vga access */
++	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
++	mdelay(1);
++	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
++}
++
++static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
++					   bool render)
++{
++	u32 tmp;
++
++	/* Lockout access through VGA aperture*/
++	tmp = RREG32(mmVGA_HDP_CONTROL);
++	if (render)
++		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
++	else
++		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
++	WREG32(mmVGA_HDP_CONTROL, tmp);
++
++	/* disable VGA render */
++	tmp = RREG32(mmVGA_RENDER_CONTROL);
++	if (render)
++		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++	WREG32(mmVGA_RENDER_CONTROL, tmp);
++}
++
++static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	int bpc = 0;
++	u32 tmp = 0;
++	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		bpc = amdgpu_connector_get_monitor_bpc(connector);
++		dither = amdgpu_connector->dither;
++	}
++
++	/* LVDS/eDP FMT is set up by atom */
++	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
++		return;
++
++	/* not needed for analog */
++	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
++	    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
++		return;
++
++	if (bpc == 0)
++		return;
++
++	switch (bpc) {
++	case 6:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
++			/* XXX sort out optimal dither settings */
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
++		} else {
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
++		}
++		break;
++	case 8:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
++			/* XXX sort out optimal dither settings */
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
++		} else {
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
++		}
++		break;
++	case 10:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
++			/* XXX sort out optimal dither settings */
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
++		} else {
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
++		}
++		break;
++	default:
++		/* not needed */
++		break;
++	}
++
++	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++
++/* display watermark setup */
++/**
++ * dce_v10_0_line_buffer_adjust - Set up the line buffer
++ *
++ * @adev: amdgpu_device pointer
++ * @amdgpu_crtc: the selected display controller
++ * @mode: the current display mode on the selected display
++ * controller
++ *
++ * Setup up the line buffer allocation for
++ * the selected display controller (CIK).
++ * Returns the line buffer size in pixels.
++ */
++static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
++				       struct amdgpu_crtc *amdgpu_crtc,
++				       struct drm_display_mode *mode)
++{
++	u32 tmp, buffer_alloc, i, mem_cfg;
++	u32 pipe_offset = amdgpu_crtc->crtc_id;
++	/*
++	 * Line Buffer Setup
++	 * There are 6 line buffers, one for each display controllers.
++	 * There are 3 partitions per LB. Select the number of partitions
++	 * to enable based on the display width.  For display widths larger
++	 * than 4096, you need use to use 2 display controllers and combine
++	 * them using the stereo blender.
++	 */
++	if (amdgpu_crtc->base.enabled && mode) {
++		if (mode->crtc_hdisplay < 1920) {
++			mem_cfg = 1;
++			buffer_alloc = 2;
++		} else if (mode->crtc_hdisplay < 2560) {
++			mem_cfg = 2;
++			buffer_alloc = 2;
++		} else if (mode->crtc_hdisplay < 4096) {
++			mem_cfg = 0;
++			buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
++		} else {
++			DRM_DEBUG_KMS("Mode too big for LB!\n");
++			mem_cfg = 0;
++			buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
++		}
++	} else {
++		mem_cfg = 1;
++		buffer_alloc = 0;
++	}
++
++	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
++	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
++	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
++	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
++		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
++			break;
++		udelay(1);
++	}
++
++	if (amdgpu_crtc->base.enabled && mode) {
++		switch (mem_cfg) {
++		case 0:
++		default:
++			return 4096 * 2;
++		case 1:
++			return 1920 * 2;
++		case 2:
++			return 2560 * 2;
++		}
++	}
++
++	/* controller not enabled, so no lb used */
++	return 0;
++}
++
++/**
++ * cik_get_number_of_dram_channels - get the number of dram channels
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up the number of video ram channels (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the number of dram channels
++ */
++static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
++
++	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
++	case 0:
++	default:
++		return 1;
++	case 1:
++		return 2;
++	case 2:
++		return 4;
++	case 3:
++		return 8;
++	case 4:
++		return 3;
++	case 5:
++		return 6;
++	case 6:
++		return 10;
++	case 7:
++		return 12;
++	case 8:
++		return 16;
++	}
++}
++
++struct dce10_wm_params {
++	u32 dram_channels; /* number of dram channels */
++	u32 yclk;          /* bandwidth per dram data pin in kHz */
++	u32 sclk;          /* engine clock in kHz */
++	u32 disp_clk;      /* display clock in kHz */
++	u32 src_width;     /* viewport width */
++	u32 active_time;   /* active display time in ns */
++	u32 blank_time;    /* blank time in ns */
++	bool interlaced;    /* mode is interlaced */
++	fixed20_12 vsc;    /* vertical scale ratio */
++	u32 num_heads;     /* number of active crtcs */
++	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
++	u32 lb_size;       /* line buffer allocated to pipe */
++	u32 vtaps;         /* vertical scaler taps */
++};
++
++/**
++ * dce_v10_0_dram_bandwidth - get the dram bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the raw dram bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dram bandwidth in MBytes/s
++ */
++static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate raw DRAM Bandwidth */
++	fixed20_12 dram_efficiency; /* 0.7 */
++	fixed20_12 yclk, dram_channels, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	yclk.full = dfixed_const(wm->yclk);
++	yclk.full = dfixed_div(yclk, a);
++	dram_channels.full = dfixed_const(wm->dram_channels * 4);
++	a.full = dfixed_const(10);
++	dram_efficiency.full = dfixed_const(7);
++	dram_efficiency.full = dfixed_div(dram_efficiency, a);
++	bandwidth.full = dfixed_mul(dram_channels, yclk);
++	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the dram bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dram bandwidth for display in MBytes/s
++ */
++static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
++{
++	/* Calculate DRAM Bandwidth and the part allocated to display. */
++	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
++	fixed20_12 yclk, dram_channels, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	yclk.full = dfixed_const(wm->yclk);
++	yclk.full = dfixed_div(yclk, a);
++	dram_channels.full = dfixed_const(wm->dram_channels * 4);
++	a.full = dfixed_const(10);
++	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
++	disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
++	bandwidth.full = dfixed_mul(dram_channels, yclk);
++	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v10_0_data_return_bandwidth - get the data return bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the data return bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the data return bandwidth in MBytes/s
++ */
++static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the display Data return Bandwidth */
++	fixed20_12 return_efficiency; /* 0.8 */
++	fixed20_12 sclk, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	sclk.full = dfixed_const(wm->sclk);
++	sclk.full = dfixed_div(sclk, a);
++	a.full = dfixed_const(10);
++	return_efficiency.full = dfixed_const(8);
++	return_efficiency.full = dfixed_div(return_efficiency, a);
++	a.full = dfixed_const(32);
++	bandwidth.full = dfixed_mul(a, sclk);
++	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the dmif bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dmif bandwidth in MBytes/s
++ */
++static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the DMIF Request Bandwidth */
++	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
++	fixed20_12 disp_clk, bandwidth;
++	fixed20_12 a, b;
++
++	a.full = dfixed_const(1000);
++	disp_clk.full = dfixed_const(wm->disp_clk);
++	disp_clk.full = dfixed_div(disp_clk, a);
++	a.full = dfixed_const(32);
++	b.full = dfixed_mul(a, disp_clk);
++
++	a.full = dfixed_const(10);
++	disp_clk_request_efficiency.full = dfixed_const(8);
++	disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
++
++	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v10_0_available_bandwidth - get the min available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the min available bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the min available bandwidth in MBytes/s
++ */
++static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
++	u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
++	u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
++	u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
++
++	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
++}
++
++/**
++ * dce_v10_0_average_bandwidth - get the average available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the average available bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the average available bandwidth in MBytes/s
++ */
++static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the display mode Average Bandwidth
++	 * DisplayMode should contain the source and destination dimensions,
++	 * timing, etc.
++	 */
++	fixed20_12 bpp;
++	fixed20_12 line_time;
++	fixed20_12 src_width;
++	fixed20_12 bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
++	line_time.full = dfixed_div(line_time, a);
++	bpp.full = dfixed_const(wm->bytes_per_pixel);
++	src_width.full = dfixed_const(wm->src_width);
++	bandwidth.full = dfixed_mul(src_width, bpp);
++	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
++	bandwidth.full = dfixed_div(bandwidth, line_time);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v10_0_latency_watermark - get the latency watermark
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the latency watermark (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the latency watermark in ns
++ */
++static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
++{
++	/* First calculate the latency in ns */
++	u32 mc_latency = 2000; /* 2000 ns. */
++	u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
++	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
++	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
++	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
++	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
++		(wm->num_heads * cursor_line_pair_return_time);
++	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
++	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
++	u32 tmp, dmif_size = 12288;
++	fixed20_12 a, b, c;
++
++	if (wm->num_heads == 0)
++		return 0;
++
++	a.full = dfixed_const(2);
++	b.full = dfixed_const(1);
++	if ((wm->vsc.full > a.full) ||
++	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
++	    (wm->vtaps >= 5) ||
++	    ((wm->vsc.full >= a.full) && wm->interlaced))
++		max_src_lines_per_dst_line = 4;
++	else
++		max_src_lines_per_dst_line = 2;
++
++	a.full = dfixed_const(available_bandwidth);
++	b.full = dfixed_const(wm->num_heads);
++	a.full = dfixed_div(a, b);
++
++	b.full = dfixed_const(mc_latency + 512);
++	c.full = dfixed_const(wm->disp_clk);
++	b.full = dfixed_div(b, c);
++
++	c.full = dfixed_const(dmif_size);
++	b.full = dfixed_div(c, b);
++
++	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
++
++	b.full = dfixed_const(1000);
++	c.full = dfixed_const(wm->disp_clk);
++	b.full = dfixed_div(c, b);
++	c.full = dfixed_const(wm->bytes_per_pixel);
++	b.full = dfixed_mul(b, c);
++
++	lb_fill_bw = min(tmp, dfixed_trunc(b));
++
++	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
++	b.full = dfixed_const(1000);
++	c.full = dfixed_const(lb_fill_bw);
++	b.full = dfixed_div(c, b);
++	a.full = dfixed_div(a, b);
++	line_fill_time = dfixed_trunc(a);
++
++	if (line_fill_time < wm->active_time)
++		return latency;
++	else
++		return latency + (line_fill_time - wm->active_time);
++
++}
++
++/**
++ * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
++ * average and available dram bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Check if the display average bandwidth fits in the display
++ * dram bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
++{
++	if (dce_v10_0_average_bandwidth(wm) <=
++	    (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
++ * average and available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Check if the display average bandwidth fits in the display
++ * available bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
++{
++	if (dce_v10_0_average_bandwidth(wm) <=
++	    (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v10_0_check_latency_hiding - check latency hiding
++ *
++ * @wm: watermark calculation data
++ *
++ * Check latency hiding (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
++{
++	u32 lb_partitions = wm->lb_size / wm->src_width;
++	u32 line_time = wm->active_time + wm->blank_time;
++	u32 latency_tolerant_lines;
++	u32 latency_hiding;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1);
++	if (wm->vsc.full > a.full)
++		latency_tolerant_lines = 1;
++	else {
++		if (lb_partitions <= (wm->vtaps + 1))
++			latency_tolerant_lines = 1;
++		else
++			latency_tolerant_lines = 2;
++	}
++
++	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
++
++	if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v10_0_program_watermarks - program display watermarks
++ *
++ * @adev: amdgpu_device pointer
++ * @amdgpu_crtc: the selected display controller
++ * @lb_size: line buffer size
++ * @num_heads: number of display controllers in use
++ *
++ * Calculate and program the display watermarks for the
++ * selected display controller (CIK).
++ */
++static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
++					struct amdgpu_crtc *amdgpu_crtc,
++					u32 lb_size, u32 num_heads)
++{
++	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
++	struct dce10_wm_params wm_low, wm_high;
++	u32 pixel_period;
++	u32 line_time = 0;
++	u32 latency_watermark_a = 0, latency_watermark_b = 0;
++	u32 tmp, wm_mask;
++
++	if (amdgpu_crtc->base.enabled && num_heads && mode) {
++		pixel_period = 1000000 / (u32)mode->clock;
++		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
++
++		/* watermark for high clocks */
++		if (adev->pm.dpm_enabled) {
++			wm_high.yclk =
++				amdgpu_dpm_get_mclk(adev, false) * 10;
++			wm_high.sclk =
++				amdgpu_dpm_get_sclk(adev, false) * 10;
++		} else {
++			wm_high.yclk = adev->pm.current_mclk * 10;
++			wm_high.sclk = adev->pm.current_sclk * 10;
++		}
++
++		wm_high.disp_clk = mode->clock;
++		wm_high.src_width = mode->crtc_hdisplay;
++		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
++		wm_high.blank_time = line_time - wm_high.active_time;
++		wm_high.interlaced = false;
++		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++			wm_high.interlaced = true;
++		wm_high.vsc = amdgpu_crtc->vsc;
++		wm_high.vtaps = 1;
++		if (amdgpu_crtc->rmx_type != RMX_OFF)
++			wm_high.vtaps = 2;
++		wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
++		wm_high.lb_size = lb_size;
++		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
++		wm_high.num_heads = num_heads;
++
++		/* set for high clocks */
++		latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
++
++		/* possibly force display priority to high */
++		/* should really do this at mode validation time... */
++		if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
++		    !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
++		    !dce_v10_0_check_latency_hiding(&wm_high) ||
++		    (adev->mode_info.disp_priority == 2)) {
++			DRM_DEBUG_KMS("force priority to high\n");
++		}
++
++		/* watermark for low clocks */
++		if (adev->pm.dpm_enabled) {
++			wm_low.yclk =
++				amdgpu_dpm_get_mclk(adev, true) * 10;
++			wm_low.sclk =
++				amdgpu_dpm_get_sclk(adev, true) * 10;
++		} else {
++			wm_low.yclk = adev->pm.current_mclk * 10;
++			wm_low.sclk = adev->pm.current_sclk * 10;
++		}
++
++		wm_low.disp_clk = mode->clock;
++		wm_low.src_width = mode->crtc_hdisplay;
++		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
++		wm_low.blank_time = line_time - wm_low.active_time;
++		wm_low.interlaced = false;
++		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++			wm_low.interlaced = true;
++		wm_low.vsc = amdgpu_crtc->vsc;
++		wm_low.vtaps = 1;
++		if (amdgpu_crtc->rmx_type != RMX_OFF)
++			wm_low.vtaps = 2;
++		wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
++		wm_low.lb_size = lb_size;
++		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
++		wm_low.num_heads = num_heads;
++
++		/* set for low clocks */
++		latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
++
++		/* possibly force display priority to high */
++		/* should really do this at mode validation time... */
++		if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
++		    !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
++		    !dce_v10_0_check_latency_hiding(&wm_low) ||
++		    (adev->mode_info.disp_priority == 2)) {
++			DRM_DEBUG_KMS("force priority to high\n");
++		}
++	}
++
++	/* select wm A */
++	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
++	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	/* select wm B */
++	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
++	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	/* restore original selection */
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
++
++	/* save values for DPM */
++	amdgpu_crtc->line_time = line_time;
++	amdgpu_crtc->wm_high = latency_watermark_a;
++	amdgpu_crtc->wm_low = latency_watermark_b;
++}
++
++/**
++ * dce_v10_0_bandwidth_update - program display watermarks
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Calculate and program the display watermarks and line
++ * buffer allocation (CIK).
++ */
++static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
++{
++	struct drm_display_mode *mode = NULL;
++	u32 num_heads = 0, lb_size;
++	int i;
++
++	amdgpu_update_display_priority(adev);
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (adev->mode_info.crtcs[i]->base.enabled)
++			num_heads++;
++	}
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		mode = &adev->mode_info.crtcs[i]->base.mode;
++		lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
++		dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
++					    lb_size, num_heads);
++	}
++}
++
++static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
++{
++	int i;
++	u32 offset, tmp;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		offset = adev->mode_info.audio.pin[i].offset;
++		tmp = RREG32_AUDIO_ENDPT(offset,
++					 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
++		if (((tmp &
++		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
++		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
++			adev->mode_info.audio.pin[i].connected = false;
++		else
++			adev->mode_info.audio.pin[i].connected = true;
++	}
++}
++
++static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v10_0_audio_get_connected_pins(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		if (adev->mode_info.audio.pin[i].connected)
++			return &adev->mode_info.audio.pin[i];
++	}
++	DRM_ERROR("No connected audio pins found!\n");
++	return NULL;
++}
++
++static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u32 tmp;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
++	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
++}
++
++static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
++						struct drm_display_mode *mode)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	u32 tmp;
++	int interlace = 0;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		interlace = 1;
++	if (connector->latency_present[interlace]) {
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    VIDEO_LIPSYNC, connector->video_latency[interlace]);
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    AUDIO_LIPSYNC, connector->audio_latency[interlace]);
++	} else {
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    VIDEO_LIPSYNC, 0);
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    AUDIO_LIPSYNC, 0);
++	}
++	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
++			   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
++}
++
++static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	u32 tmp;
++	u8 *sadb = NULL;
++	int sad_count;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
++	if (sad_count < 0) {
++		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
++		sad_count = 0;
++	}
++
++	/* program the speaker allocation */
++	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
++				 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
++	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++			    DP_CONNECTION, 0);
++	/* set HDMI mode */
++	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++			    HDMI_CONNECTION, 1);
++	if (sad_count)
++		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++				    SPEAKER_ALLOCATION, sadb[0]);
++	else
++		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++				    SPEAKER_ALLOCATION, 5); /* stereo */
++	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
++			   ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
++
++	kfree(sadb);
++}
++
++static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	struct cea_sad *sads;
++	int i, sad_count;
++
++	static const u16 eld_reg_to_type[][2] = {
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
++	};
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
++	if (sad_count <= 0) {
++		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++		return;
++	}
++	BUG_ON(!sads);
++
++	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
++		u32 tmp = 0;
++		u8 stereo_freqs = 0;
++		int max_channels = -1;
++		int j;
++
++		for (j = 0; j < sad_count; j++) {
++			struct cea_sad *sad = &sads[j];
++
++			if (sad->format == eld_reg_to_type[i][1]) {
++				if (sad->channels > max_channels) {
++					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++							    MAX_CHANNELS, sad->channels);
++					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++							    DESCRIPTOR_BYTE_2, sad->byte2);
++					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++							    SUPPORTED_FREQUENCIES, sad->freq);
++					max_channels = sad->channels;
++				}
++
++				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
++					stereo_freqs |= sad->freq;
++				else
++					break;
++			}
++		}
++
++		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++				    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
++		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
++	}
++
++	kfree(sads);
++}
++
++static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
++				  struct amdgpu_audio_pin *pin,
++				  bool enable)
++{
++	if (!pin)
++		return;
++
++	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
++			   enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
++}
++
++static const u32 pin_offsets[] =
++{
++	AUD0_REGISTER_OFFSET,
++	AUD1_REGISTER_OFFSET,
++	AUD2_REGISTER_OFFSET,
++	AUD3_REGISTER_OFFSET,
++	AUD4_REGISTER_OFFSET,
++	AUD5_REGISTER_OFFSET,
++	AUD6_REGISTER_OFFSET,
++};
++
++static int dce_v10_0_audio_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (!amdgpu_audio)
++		return 0;
++
++	adev->mode_info.audio.enabled = true;
++
++	adev->mode_info.audio.num_pins = 7;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		adev->mode_info.audio.pin[i].channels = -1;
++		adev->mode_info.audio.pin[i].rate = -1;
++		adev->mode_info.audio.pin[i].bits_per_sample = -1;
++		adev->mode_info.audio.pin[i].status_bits = 0;
++		adev->mode_info.audio.pin[i].category_code = 0;
++		adev->mode_info.audio.pin[i].connected = false;
++		adev->mode_info.audio.pin[i].offset = pin_offsets[i];
++		adev->mode_info.audio.pin[i].id = i;
++		/* disable audio.  it will be set up later */
++		/* XXX remove once we switch to ip funcs */
++		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (!adev->mode_info.audio.enabled)
++		return;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++)
++		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++
++	adev->mode_info.audio.enabled = false;
++}
++
++/*
++ * update the N and CTS parameters for a given pixel clock rate
++ */
++static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u32 tmp;
++
++	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
++	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
++	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
++	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
++	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
++	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
++	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
++	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
++	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
++	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
++
++}
++
++/*
++ * build a HDMI Video Info Frame
++ */
++static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
++					       void *buffer, size_t size)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	uint8_t *frame = buffer + 3;
++	uint8_t *header = buffer;
++
++	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
++		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
++	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
++		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
++	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
++		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
++	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
++		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
++}
++
++static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	u32 dto_phase = 24 * 1000;
++	u32 dto_modulo = clock;
++	u32 tmp;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* XXX two dtos; generally use dto0 for hdmi */
++	/* Express [24MHz / target pixel clock] as an exact rational
++	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
++	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
++	 */
++	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
++	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
++			    amdgpu_crtc->crtc_id);
++	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
++	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
++	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
++}
++
++/*
++ * update the info frames with the data from the current display mode
++ */
++static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
++				  struct drm_display_mode *mode)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
++	struct hdmi_avi_infoframe frame;
++	ssize_t err;
++	u32 tmp;
++	int bpc = 8;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* Silent, r600_hdmi_enable will raise WARN for us */
++	if (!dig->afmt->enabled)
++		return;
++
++	/* hdmi deep color mode general control packets setup, if bpc > 8 */
++	if (encoder->crtc) {
++		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++		bpc = amdgpu_crtc->bpc;
++	}
++
++	/* disable audio prior to setting up hw */
++	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
++	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
++
++	dce_v10_0_audio_set_dto(encoder, mode->clock);
++
++	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
++	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
++
++	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
++
++	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
++	switch (bpc) {
++	case 0:
++	case 6:
++	case 8:
++	case 16:
++	default:
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
++		DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
++			  connector->name, bpc);
++		break;
++	case 10:
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
++		DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
++			  connector->name);
++		break;
++	case 12:
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
++		DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
++			  connector->name);
++		break;
++	}
++	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
++	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
++	/* enable audio info frames (frames won't be set until audio is enabled) */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
++	/* required for audio info values to be updated */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
++	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
++	/* required for audio info values to be updated */
++	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
++	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
++	/* anything other than 0 */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
++	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
++
++	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
++
++	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
++	/* set the default audio delay */
++	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
++	/* should be suffient for all audio modes and small enough for all hblanks */
++	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
++	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
++	/* allow 60958 channel status fields to be updated */
++	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
++	if (bpc > 8)
++		/* clear SW CTS value */
++		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
++	else
++		/* select SW CTS value */
++		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
++	/* allow hw to sent ACR packets when required */
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
++	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	dce_v10_0_afmt_update_ACR(encoder, mode->clock);
++
++	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
++	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
++	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
++	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
++
++	dce_v10_0_audio_write_speaker_allocation(encoder);
++
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
++	       (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
++
++	dce_v10_0_afmt_audio_select_pin(encoder);
++	dce_v10_0_audio_write_sad_regs(encoder);
++	dce_v10_0_audio_write_latency_fields(encoder, mode);
++
++	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
++	if (err < 0) {
++		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
++		return;
++	}
++
++	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
++	if (err < 0) {
++		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
++		return;
++	}
++
++	dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
++	/* enable AVI info frames */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
++	/* required for audio info values to be updated */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
++	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
++	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
++	/* send audio packets */
++	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
++	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
++	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
++	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
++
++	/* enable audio after to setting up hw */
++	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
++}
++
++static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* Silent, r600_hdmi_enable will raise WARN for us */
++	if (enable && dig->afmt->enabled)
++		return;
++	if (!enable && !dig->afmt->enabled)
++		return;
++
++	if (!enable && dig->afmt->pin) {
++		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
++		dig->afmt->pin = NULL;
++	}
++
++	dig->afmt->enabled = enable;
++
++	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
++		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
++}
++
++static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->mode_info.num_dig; i++)
++		adev->mode_info.afmt[i] = NULL;
++
++	/* DCE10 has audio blocks tied to DIG encoders */
++	for (i = 0; i < adev->mode_info.num_dig; i++) {
++		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
++		if (adev->mode_info.afmt[i]) {
++			adev->mode_info.afmt[i]->offset = dig_offsets[i];
++			adev->mode_info.afmt[i]->id = i;
++		}
++	}
++}
++
++static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->mode_info.num_dig; i++) {
++		kfree(adev->mode_info.afmt[i]);
++		adev->mode_info.afmt[i] = NULL;
++	}
++}
++
++static const u32 vga_control_regs[6] =
++{
++	mmD1VGA_CONTROL,
++	mmD2VGA_CONTROL,
++	mmD3VGA_CONTROL,
++	mmD4VGA_CONTROL,
++	mmD5VGA_CONTROL,
++	mmD6VGA_CONTROL,
++};
++
++static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u32 vga_control;
++
++	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
++	if (enable)
++		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
++	else
++		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
++}
++
++static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (enable)
++		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
++	else
++		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
++}
++
++static void dce_v10_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw,
++				   unsigned *bankh, unsigned *mtaspect,
++				   unsigned *tile_split)
++{
++	*bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK;
++	*bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK;
++	*mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
++	*tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK;
++	switch (*bankw) {
++	default:
++	case 1:
++		*bankw = ADDR_SURF_BANK_WIDTH_1;
++		break;
++	case 2:
++		*bankw = ADDR_SURF_BANK_WIDTH_2;
++		break;
++	case 4:
++		*bankw = ADDR_SURF_BANK_WIDTH_4;
++		break;
++	case 8:
++		*bankw = ADDR_SURF_BANK_WIDTH_8;
++		break;
++	}
++	switch (*bankh) {
++	default:
++	case 1:
++		*bankh = ADDR_SURF_BANK_HEIGHT_1;
++		break;
++	case 2:
++		*bankh = ADDR_SURF_BANK_HEIGHT_2;
++		break;
++	case 4:
++		*bankh = ADDR_SURF_BANK_HEIGHT_4;
++		break;
++	case 8:
++		*bankh = ADDR_SURF_BANK_HEIGHT_8;
++		break;
++	}
++	switch (*mtaspect) {
++	default:
++	case 1:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_1;
++		break;
++	case 2:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_2;
++		break;
++	case 4:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_4;
++		break;
++	case 8:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_8;
++		break;
++	}
++}
++
++static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
++				     struct drm_framebuffer *fb,
++				     int x, int y, int atomic)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_framebuffer *amdgpu_fb;
++	struct drm_framebuffer *target_fb;
++	struct drm_gem_object *obj;
++	struct amdgpu_bo *rbo;
++	uint64_t fb_location, tiling_flags;
++	uint32_t fb_format, fb_pitch_pixels;
++	unsigned bankw, bankh, mtaspect, tile_split;
++	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
++	/* XXX change to VI */
++	u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f;
++	u32 tmp, viewport_w, viewport_h;
++	int r;
++	bool bypass_lut = false;
++
++	/* no fb bound */
++	if (!atomic && !crtc->primary->fb) {
++		DRM_DEBUG_KMS("No FB bound\n");
++		return 0;
++	}
++
++	if (atomic) {
++		amdgpu_fb = to_amdgpu_framebuffer(fb);
++		target_fb = fb;
++	}
++	else {
++		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++		target_fb = crtc->primary->fb;
++	}
++
++	/* If atomic, assume fb object is pinned & idle & fenced and
++	 * just update base pointers
++	 */
++	obj = amdgpu_fb->obj;
++	rbo = gem_to_amdgpu_bo(obj);
++	r = amdgpu_bo_reserve(rbo, false);
++	if (unlikely(r != 0))
++		return r;
++
++	if (atomic)
++		fb_location = amdgpu_bo_gpu_offset(rbo);
++	else {
++		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
++		if (unlikely(r != 0)) {
++			amdgpu_bo_unreserve(rbo);
++			return -EINVAL;
++		}
++	}
++
++	amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
++	amdgpu_bo_unreserve(rbo);
++
++	switch (target_fb->pixel_format) {
++	case DRM_FORMAT_C8:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
++		break;
++	case DRM_FORMAT_XRGB4444:
++	case DRM_FORMAT_ARGB4444:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_XRGB1555:
++	case DRM_FORMAT_ARGB1555:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_BGRX5551:
++	case DRM_FORMAT_BGRA5551:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_RGB565:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_XRGB8888:
++	case DRM_FORMAT_ARGB8888:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN32);
++#endif
++		break;
++	case DRM_FORMAT_XRGB2101010:
++	case DRM_FORMAT_ARGB2101010:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN32);
++#endif
++		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
++		bypass_lut = true;
++		break;
++	case DRM_FORMAT_BGRX1010102:
++	case DRM_FORMAT_BGRA1010102:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN32);
++#endif
++		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
++		bypass_lut = true;
++		break;
++	default:
++		DRM_ERROR("Unsupported screen format %s\n",
++			drm_get_format_name(target_fb->pixel_format));
++		return -EINVAL;
++	}
++
++	if (tiling_flags & AMDGPU_TILING_MACRO) {
++		unsigned tileb, index, num_banks, tile_split_bytes;
++
++		dce_v10_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
++		/* Set NUM_BANKS. */
++		/* Calculate the macrotile mode index. */
++		tile_split_bytes = 64 << tile_split;
++		tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
++		tileb = min(tile_split_bytes, tileb);
++
++		for (index = 0; tileb > 64; index++) {
++			tileb >>= 1;
++		}
++
++		if (index >= 16) {
++			DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
++				  target_fb->bits_per_pixel, tile_split);
++			return -EINVAL;
++		}
++
++		num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3;
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
++					  ARRAY_2D_TILED_THIN1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
++					  tile_split);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
++					  mtaspect);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
++					  ADDR_SURF_MICRO_TILING_DISPLAY);
++	} else if (tiling_flags & AMDGPU_TILING_MICRO) {
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
++					  ARRAY_1D_TILED_THIN1);
++	}
++
++	/* Read the pipe config from the 2D TILED SCANOUT mode.
++	 * It should be the same for the other modes too, but not all
++	 * modes set the pipe config field. */
++	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
++				  pipe_config);
++
++	dce_v10_0_vga_enable(crtc, false);
++
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(fb_location));
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(fb_location));
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
++	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
++	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
++
++	/*
++	 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
++	 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
++	 * retain the full precision throughout the pipeline.
++	 */
++	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
++	if (bypass_lut)
++		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
++	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
++
++	if (bypass_lut)
++		DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
++
++	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
++	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
++
++	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
++
++	dce_v10_0_grph_enable(crtc, true);
++
++	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
++	       target_fb->height);
++
++	x &= ~3;
++	y &= ~1;
++	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
++	       (x << 16) | y);
++	viewport_w = crtc->mode.hdisplay;
++	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
++	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
++	       (viewport_w << 16) | viewport_h);
++
++	/* pageflip setup */
++	/* make sure flip is at vb rather than hb */
++	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
++			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
++	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	/* set pageflip to happen only at start of vblank interval (front porch) */
++	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
++
++	if (!atomic && fb && fb != crtc->primary->fb) {
++		amdgpu_fb = to_amdgpu_framebuffer(fb);
++		rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
++		r = amdgpu_bo_reserve(rbo, false);
++		if (unlikely(r != 0))
++			return r;
++		amdgpu_bo_unpin(rbo);
++		amdgpu_bo_unreserve(rbo);
++	}
++
++	/* Bytes per pixel may have changed */
++	dce_v10_0_bandwidth_update(adev);
++
++	return 0;
++}
++
++static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
++				     struct drm_display_mode *mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	u32 tmp;
++
++	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
++	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int i;
++	u32 tmp;
++
++	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
++
++	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
++	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
++	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
++	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
++	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
++
++	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
++
++	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
++	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
++	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
++
++	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
++
++	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
++	for (i = 0; i < 256; i++) {
++		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
++		       (amdgpu_crtc->lut_r[i] << 20) |
++		       (amdgpu_crtc->lut_g[i] << 10) |
++		       (amdgpu_crtc->lut_b[i] << 0));
++	}
++
++	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
++	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
++	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
++	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
++	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
++	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
++	/* XXX this only needs to be programmed once per crtc at startup,
++	 * not sure where the best place for it is
++	 */
++	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
++	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++		if (dig->linkb)
++			return 1;
++		else
++			return 0;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++		if (dig->linkb)
++			return 3;
++		else
++			return 2;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++		if (dig->linkb)
++			return 5;
++		else
++			return 4;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		return 6;
++		break;
++	default:
++		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
++		return 0;
++	}
++}
++
++/**
++ * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
++ *
++ * @crtc: drm crtc
++ *
++ * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
++ * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
++ * monitors a dedicated PPLL must be used.  If a particular board has
++ * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
++ * as there is no need to program the PLL itself.  If we are not able to
++ * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
++ * avoid messing up an existing monitor.
++ *
++ * Asic specific PLL information
++ *
++ * DCE 10.x
++ * Tonga
++ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
++ * CI
++ * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
++ *
++ */
++static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u32 pll_in_use;
++	int pll;
++
++	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
++		if (adev->clock.dp_extclk)
++			/* skip PPLL programming if using ext clock */
++			return ATOM_PPLL_INVALID;
++		else {
++			/* use the same PPLL for all DP monitors */
++			pll = amdgpu_pll_get_shared_dp_ppll(crtc);
++			if (pll != ATOM_PPLL_INVALID)
++				return pll;
++		}
++	} else {
++		/* use the same PPLL for all monitors with the same clock */
++		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
++		if (pll != ATOM_PPLL_INVALID)
++			return pll;
++	}
++
++	/* DCE10 has PPLL0, PPLL1, and PPLL2 */
++	pll_in_use = amdgpu_pll_get_use_mask(crtc);
++	if (!(pll_in_use & (1 << ATOM_PPLL2)))
++		return ATOM_PPLL2;
++	if (!(pll_in_use & (1 << ATOM_PPLL1)))
++		return ATOM_PPLL1;
++	if (!(pll_in_use & (1 << ATOM_PPLL0)))
++		return ATOM_PPLL0;
++	DRM_ERROR("unable to allocate a PPLL\n");
++	return ATOM_PPLL_INVALID;
++}
++
++static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
++{
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	uint32_t cur_lock;
++
++	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
++	if (lock)
++		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
++	else
++		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
++	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
++}
++
++static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	u32 tmp;
++
++	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
++	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	u32 tmp;
++
++	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
++	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
++	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
++			      uint64_t gpu_addr)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++
++	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(gpu_addr));
++	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       lower_32_bits(gpu_addr));
++}
++
++static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
++				     int x, int y)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	int xorigin = 0, yorigin = 0;
++
++	/* avivo cursor are offset into the total surface */
++	x += crtc->x;
++	y += crtc->y;
++	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
++
++	if (x < 0) {
++		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
++		x = 0;
++	}
++	if (y < 0) {
++		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
++		y = 0;
++	}
++
++	dce_v10_0_lock_cursor(crtc, true);
++	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
++	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
++	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
++	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
++	dce_v10_0_lock_cursor(crtc, false);
++
++	return 0;
++}
++
++static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc,
++				    struct drm_file *file_priv,
++				    uint32_t handle,
++				    uint32_t width,
++				    uint32_t height)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_gem_object *obj;
++	struct amdgpu_bo *robj;
++	uint64_t gpu_addr;
++	int ret;
++
++	if (!handle) {
++		/* turn off cursor */
++		dce_v10_0_hide_cursor(crtc);
++		obj = NULL;
++		goto unpin;
++	}
++
++	if ((width > amdgpu_crtc->max_cursor_width) ||
++	    (height > amdgpu_crtc->max_cursor_height)) {
++		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
++		return -EINVAL;
++	}
++
++	obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
++	if (!obj) {
++		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
++		return -ENOENT;
++	}
++
++	robj = gem_to_amdgpu_bo(obj);
++	ret = amdgpu_bo_reserve(robj, false);
++	if (unlikely(ret != 0))
++		goto fail;
++	ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
++				       0, &gpu_addr);
++	amdgpu_bo_unreserve(robj);
++	if (ret)
++		goto fail;
++
++	amdgpu_crtc->cursor_width = width;
++	amdgpu_crtc->cursor_height = height;
++
++	dce_v10_0_lock_cursor(crtc, true);
++	dce_v10_0_set_cursor(crtc, obj, gpu_addr);
++	dce_v10_0_show_cursor(crtc);
++	dce_v10_0_lock_cursor(crtc, false);
++
++unpin:
++	if (amdgpu_crtc->cursor_bo) {
++		robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
++		ret = amdgpu_bo_reserve(robj, false);
++		if (likely(ret == 0)) {
++			amdgpu_bo_unpin(robj);
++			amdgpu_bo_unreserve(robj);
++		}
++		drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
++	}
++
++	amdgpu_crtc->cursor_bo = obj;
++	return 0;
++fail:
++	drm_gem_object_unreference_unlocked(obj);
++
++	return ret;
++}
++
++static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
++				    u16 *blue, uint32_t start, uint32_t size)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	int end = (start + size > 256) ? 256 : start + size, i;
++
++	/* userspace palettes are always correct as is */
++	for (i = start; i < end; i++) {
++		amdgpu_crtc->lut_r[i] = red[i] >> 6;
++		amdgpu_crtc->lut_g[i] = green[i] >> 6;
++		amdgpu_crtc->lut_b[i] = blue[i] >> 6;
++	}
++	dce_v10_0_crtc_load_lut(crtc);
++}
++
++static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	drm_crtc_cleanup(crtc);
++	destroy_workqueue(amdgpu_crtc->pflip_queue);
++	kfree(amdgpu_crtc);
++}
++
++static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
++	.cursor_set = dce_v10_0_crtc_cursor_set,
++	.cursor_move = dce_v10_0_crtc_cursor_move,
++	.gamma_set = dce_v10_0_crtc_gamma_set,
++	.set_config = amdgpu_crtc_set_config,
++	.destroy = dce_v10_0_crtc_destroy,
++	.page_flip = amdgpu_crtc_page_flip,
++};
++
++static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	switch (mode) {
++	case DRM_MODE_DPMS_ON:
++		amdgpu_crtc->enabled = true;
++		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
++		dce_v10_0_vga_enable(crtc, true);
++		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
++		dce_v10_0_vga_enable(crtc, false);
++		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
++		dce_v10_0_crtc_load_lut(crtc);
++		break;
++	case DRM_MODE_DPMS_STANDBY:
++	case DRM_MODE_DPMS_SUSPEND:
++	case DRM_MODE_DPMS_OFF:
++		drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
++		if (amdgpu_crtc->enabled) {
++			dce_v10_0_vga_enable(crtc, true);
++			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
++			dce_v10_0_vga_enable(crtc, false);
++		}
++		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
++		amdgpu_crtc->enabled = false;
++		break;
++	}
++	/* adjust pm to dpms */
++	amdgpu_pm_compute_clocks(adev);
++}
++
++static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
++{
++	/* disable crtc pair power gating before programming */
++	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
++	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
++	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++}
++
++static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
++{
++	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
++	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
++}
++
++static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_atom_ss ss;
++	int i;
++
++	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++	if (crtc->primary->fb) {
++		int r;
++		struct amdgpu_framebuffer *amdgpu_fb;
++		struct amdgpu_bo *rbo;
++
++		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++		rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
++		r = amdgpu_bo_reserve(rbo, false);
++		if (unlikely(r))
++			DRM_ERROR("failed to reserve rbo before unpin\n");
++		else {
++			amdgpu_bo_unpin(rbo);
++			amdgpu_bo_unreserve(rbo);
++		}
++	}
++	/* disable the GRPH */
++	dce_v10_0_grph_enable(crtc, false);
++
++	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (adev->mode_info.crtcs[i] &&
++		    adev->mode_info.crtcs[i]->enabled &&
++		    i != amdgpu_crtc->crtc_id &&
++		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
++			/* one other crtc is using this pll don't turn
++			 * off the pll
++			 */
++			goto done;
++		}
++	}
++
++	switch (amdgpu_crtc->pll_id) {
++	case ATOM_PPLL0:
++	case ATOM_PPLL1:
++	case ATOM_PPLL2:
++		/* disable the ppll */
++		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
++					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
++		break;
++	default:
++		break;
++	}
++done:
++	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
++	amdgpu_crtc->adjusted_clock = 0;
++	amdgpu_crtc->encoder = NULL;
++	amdgpu_crtc->connector = NULL;
++}
++
++static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode,
++				  struct drm_display_mode *adjusted_mode,
++				  int x, int y, struct drm_framebuffer *old_fb)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	if (!amdgpu_crtc->adjusted_clock)
++		return -EINVAL;
++
++	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
++	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
++	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
++	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
++	amdgpu_atombios_crtc_scaler_setup(crtc);
++	/* update the hw version fpr dpm */
++	amdgpu_crtc->hw_mode = *adjusted_mode;
++
++	return 0;
++}
++
++static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
++				     const struct drm_display_mode *mode,
++				     struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct drm_encoder *encoder;
++
++	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		if (encoder->crtc == crtc) {
++			amdgpu_crtc->encoder = encoder;
++			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
++			break;
++		}
++	}
++	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
++		amdgpu_crtc->encoder = NULL;
++		amdgpu_crtc->connector = NULL;
++		return false;
++	}
++	if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
++		return false;
++	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
++		return false;
++	/* pick pll */
++	amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
++	/* if we can't get a PPLL for a non-DP encoder, fail */
++	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
++	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
++		return false;
++
++	return true;
++}
++
++static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
++				  struct drm_framebuffer *old_fb)
++{
++	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
++}
++
++static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
++					 struct drm_framebuffer *fb,
++					 int x, int y, enum mode_set_atomic state)
++{
++       return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
++}
++
++static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
++	.dpms = dce_v10_0_crtc_dpms,
++	.mode_fixup = dce_v10_0_crtc_mode_fixup,
++	.mode_set = dce_v10_0_crtc_mode_set,
++	.mode_set_base = dce_v10_0_crtc_set_base,
++	.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
++	.prepare = dce_v10_0_crtc_prepare,
++	.commit = dce_v10_0_crtc_commit,
++	.load_lut = dce_v10_0_crtc_load_lut,
++	.disable = dce_v10_0_crtc_disable,
++};
++
++static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
++{
++	struct amdgpu_crtc *amdgpu_crtc;
++	int i;
++
++	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
++			      (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
++	if (amdgpu_crtc == NULL)
++		return -ENOMEM;
++
++	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
++
++	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
++	amdgpu_crtc->crtc_id = index;
++	amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
++	adev->mode_info.crtcs[index] = amdgpu_crtc;
++
++	amdgpu_crtc->max_cursor_width = 128;
++	amdgpu_crtc->max_cursor_height = 128;
++	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
++	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
++
++	for (i = 0; i < 256; i++) {
++		amdgpu_crtc->lut_r[i] = i << 2;
++		amdgpu_crtc->lut_g[i] = i << 2;
++		amdgpu_crtc->lut_b[i] = i << 2;
++	}
++
++	switch (amdgpu_crtc->crtc_id) {
++	case 0:
++	default:
++		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
++		break;
++	case 1:
++		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
++		break;
++	case 2:
++		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
++		break;
++	case 3:
++		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
++		break;
++	case 4:
++		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
++		break;
++	case 5:
++		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
++		break;
++	}
++
++	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
++	amdgpu_crtc->adjusted_clock = 0;
++	amdgpu_crtc->encoder = NULL;
++	amdgpu_crtc->connector = NULL;
++	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
++
++	return 0;
++}
++
++static int dce_v10_0_early_init(struct amdgpu_device *adev)
++{
++	adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
++	adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
++
++	dce_v10_0_set_display_funcs(adev);
++	dce_v10_0_set_irq_funcs(adev);
++
++	switch (adev->asic_type) {
++	case CHIP_TONGA:
++		adev->mode_info.num_crtc = 6; /* XXX 7??? */
++		adev->mode_info.num_hpd = 6;
++		adev->mode_info.num_dig = 7;
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int dce_v10_0_sw_init(struct amdgpu_device *adev)
++{
++	int r, i;
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
++		if (r)
++			return r;
++	}
++
++	for (i = 8; i < 20; i += 2) {
++		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
++		if (r)
++			return r;
++	}
++
++	/* HPD hotplug */
++	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
++	if (r)
++		return r;
++
++	adev->mode_info.mode_config_initialized = true;
++
++	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
++
++	adev->ddev->mode_config.max_width = 16384;
++	adev->ddev->mode_config.max_height = 16384;
++
++	adev->ddev->mode_config.preferred_depth = 24;
++	adev->ddev->mode_config.prefer_shadow = 1;
++
++	adev->ddev->mode_config.fb_base = adev->mc.aper_base;
++
++	r = amdgpu_modeset_create_props(adev);
++	if (r)
++		return r;
++
++	adev->ddev->mode_config.max_width = 16384;
++	adev->ddev->mode_config.max_height = 16384;
++
++	/* allocate crtcs */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		r = dce_v10_0_crtc_init(adev, i);
++		if (r)
++			return r;
++	}
++
++	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
++		amdgpu_print_display_setup(adev->ddev);
++	else
++		return -EINVAL;
++
++	/* setup afmt */
++	dce_v10_0_afmt_init(adev);
++
++	r = dce_v10_0_audio_init(adev);
++	if (r)
++		return r;
++
++	drm_kms_helper_poll_init(adev->ddev);
++
++	return r;
++}
++
++static int dce_v10_0_sw_fini(struct amdgpu_device *adev)
++{
++	kfree(adev->mode_info.bios_hardcoded_edid);
++
++	drm_kms_helper_poll_fini(adev->ddev);
++
++	dce_v10_0_audio_fini(adev);
++
++	dce_v10_0_afmt_fini(adev);
++
++	drm_mode_config_cleanup(adev->ddev);
++	adev->mode_info.mode_config_initialized = false;
++
++	return 0;
++}
++
++static int dce_v10_0_hw_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v10_0_init_golden_registers(adev);
++
++	/* init dig PHYs, disp eng pll */
++	amdgpu_atombios_encoder_init_dig(adev);
++	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
++
++	/* initialize hpd */
++	dce_v10_0_hpd_init(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static int dce_v10_0_hw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v10_0_hpd_fini(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static int dce_v10_0_suspend(struct amdgpu_device *adev)
++{
++	struct drm_connector *connector;
++
++	drm_kms_helper_poll_disable(adev->ddev);
++
++	/* turn off display hw */
++	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
++	}
++
++	amdgpu_atombios_scratch_regs_save(adev);
++
++	dce_v10_0_hpd_fini(adev);
++
++	return 0;
++}
++
++static int dce_v10_0_resume(struct amdgpu_device *adev)
++{
++	struct drm_connector *connector;
++
++	dce_v10_0_init_golden_registers(adev);
++
++	amdgpu_atombios_scratch_regs_restore(adev);
++
++	/* init dig PHYs, disp eng pll */
++	amdgpu_atombios_encoder_init_dig(adev);
++	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
++	/* turn on the BL */
++	if (adev->mode_info.bl_encoder) {
++		u8 bl_level = amdgpu_display_backlight_get_level(adev,
++								  adev->mode_info.bl_encoder);
++		amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
++						    bl_level);
++	}
++
++	/* initialize hpd */
++	dce_v10_0_hpd_init(adev);
++
++	/* blat the mode back in */
++	drm_helper_resume_force_mode(adev->ddev);
++	/* turn on display hw */
++	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
++	}
++
++	drm_kms_helper_poll_enable(adev->ddev);
++
++	return 0;
++}
++
++static bool dce_v10_0_is_idle(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return true;
++}
++
++static int dce_v10_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return 0;
++}
++
++static void dce_v10_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "DCE 10.x registers\n");
++	/* XXX todo */
++}
++
++static int dce_v10_0_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0, tmp;
++
++	if (dce_v10_0_is_display_hung(adev))
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
++
++	if (srbm_soft_reset) {
++		dce_v10_0_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++		dce_v10_0_print_status(adev);
++	}
++	return 0;
++}
++
++static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
++						     int crtc,
++						     enum amdgpu_interrupt_state state)
++{
++	u32 lb_interrupt_mask;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VBLANK_INTERRUPT_MASK, 0);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VBLANK_INTERRUPT_MASK, 1);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	default:
++		break;
++	}
++}
++
++static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
++						    int crtc,
++						    enum amdgpu_interrupt_state state)
++{
++	u32 lb_interrupt_mask;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VLINE_INTERRUPT_MASK, 0);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VLINE_INTERRUPT_MASK, 1);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	default:
++		break;
++	}
++}
++
++static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
++				       struct amdgpu_irq_src *source,
++				       unsigned hpd,
++				       enum amdgpu_interrupt_state state)
++{
++	u32 tmp;
++
++	if (hpd >= adev->mode_info.num_hpd) {
++		DRM_DEBUG("invalid hdp %d\n", hpd);
++		return 0;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
++		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
++		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	switch (type) {
++	case AMDGPU_CRTC_IRQ_VBLANK1:
++		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK2:
++		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK3:
++		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK4:
++		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK5:
++		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK6:
++		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE1:
++		dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE2:
++		dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE3:
++		dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE4:
++		dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE5:
++		dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE6:
++		dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
++					    struct amdgpu_irq_src *src,
++					    unsigned type,
++					    enum amdgpu_interrupt_state state)
++{
++	u32 reg, reg_block;
++	/* now deal with page flip IRQ */
++	switch (type) {
++		case AMDGPU_PAGEFLIP_IRQ_D1:
++			reg_block = CRTC0_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D2:
++			reg_block = CRTC1_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D3:
++			reg_block = CRTC2_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D4:
++			reg_block = CRTC3_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D5:
++			reg_block = CRTC4_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D6:
++			reg_block = CRTC5_REGISTER_OFFSET;
++			break;
++		default:
++			DRM_ERROR("invalid pageflip crtc %d\n", type);
++			return -EINVAL;
++	}
++
++	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
++	if (state == AMDGPU_IRQ_STATE_DISABLE)
++		WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
++	else
++		WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
++
++	return 0;
++}
++
++static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
++				  struct amdgpu_irq_src *source,
++				  struct amdgpu_iv_entry *entry)
++{
++	int reg_block;
++	unsigned long flags;
++	unsigned crtc_id;
++	struct amdgpu_crtc *amdgpu_crtc;
++	struct amdgpu_flip_work *works;
++
++	crtc_id = (entry->src_id - 8) >> 1;
++	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++
++	/* ack the interrupt */
++	switch(crtc_id){
++		case AMDGPU_PAGEFLIP_IRQ_D1:
++			reg_block = CRTC0_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D2:
++			reg_block = CRTC1_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D3:
++			reg_block = CRTC2_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D4:
++			reg_block = CRTC3_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D5:
++			reg_block = CRTC4_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D6:
++			reg_block = CRTC5_REGISTER_OFFSET;
++			break;
++		default:
++			DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
++			return -EINVAL;
++	}
++
++	if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
++		WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
++
++	/* IRQ could occur when in initial stage */
++	if (amdgpu_crtc == NULL)
++		return 0;
++
++	spin_lock_irqsave(&adev->ddev->event_lock, flags);
++	works = amdgpu_crtc->pflip_works;
++	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
++		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
++						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
++						 amdgpu_crtc->pflip_status,
++						 AMDGPU_FLIP_SUBMITTED);
++		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++		return 0;
++	}
++
++	/* page flip completed. clean up */
++	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
++	amdgpu_crtc->pflip_works = NULL;
++
++	/* wakeup usersapce */
++	if (works->event)
++		drm_send_vblank_event(adev->ddev, crtc_id, works->event);
++
++	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++
++	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
++	amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
++	queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
++
++	return 0;
++}
++
++static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
++				  int hpd)
++{
++	u32 tmp;
++
++	if (hpd >= adev->mode_info.num_hpd) {
++		DRM_DEBUG("invalid hdp %d\n", hpd);
++		return;
++	}
++
++	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
++	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
++	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
++}
++
++static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
++					  int crtc)
++{
++	u32 tmp;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
++	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
++	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
++}
++
++static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
++					 int crtc)
++{
++	u32 tmp;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
++	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
++	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
++}
++
++static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
++			      struct amdgpu_irq_src *source,
++			      struct amdgpu_iv_entry *entry)
++{
++	unsigned crtc = entry->src_id - 1;
++	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
++	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
++
++	switch (entry->src_data) {
++	case 0: /* vblank */
++		if (disp_int & interrupt_status_offsets[crtc].vblank) {
++			dce_v10_0_crtc_vblank_int_ack(adev, crtc);
++			if (amdgpu_irq_enabled(adev, source, irq_type)) {
++				drm_handle_vblank(adev->ddev, crtc);
++			}
++			DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
++		}
++		break;
++	case 1: /* vline */
++		if (disp_int & interrupt_status_offsets[crtc].vline) {
++			dce_v10_0_crtc_vline_int_ack(adev, crtc);
++			DRM_DEBUG("IH: D%d vline\n", crtc + 1);
++		}
++		break;
++	default:
++		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
++		break;
++	}
++
++	return 0;
++}
++
++static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
++			     struct amdgpu_irq_src *source,
++			     struct amdgpu_iv_entry *entry)
++{
++	uint32_t disp_int, mask;
++	unsigned hpd;
++
++	if (entry->src_data >= adev->mode_info.num_hpd) {
++		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
++		return 0;
++	}
++
++	hpd = entry->src_data;
++	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
++	mask = interrupt_status_offsets[hpd].hpd;
++
++	if (disp_int & mask) {
++		dce_v10_0_hpd_int_ack(adev, hpd);
++		schedule_work(&adev->hotplug_work);
++		DRM_DEBUG("IH: HPD%d\n", hpd + 1);
++	}
++
++	return 0;
++}
++
++static int dce_v10_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int dce_v10_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs dce_v10_0_ip_funcs = {
++	.early_init = dce_v10_0_early_init,
++	.late_init = NULL,
++	.sw_init = dce_v10_0_sw_init,
++	.sw_fini = dce_v10_0_sw_fini,
++	.hw_init = dce_v10_0_hw_init,
++	.hw_fini = dce_v10_0_hw_fini,
++	.suspend = dce_v10_0_suspend,
++	.resume = dce_v10_0_resume,
++	.is_idle = dce_v10_0_is_idle,
++	.wait_for_idle = dce_v10_0_wait_for_idle,
++	.soft_reset = dce_v10_0_soft_reset,
++	.print_status = dce_v10_0_print_status,
++	.set_clockgating_state = dce_v10_0_set_clockgating_state,
++	.set_powergating_state = dce_v10_0_set_powergating_state,
++};
++
++static void
++dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
++			  struct drm_display_mode *mode,
++			  struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
++
++	/* need to call this here rather than in prepare() since we need some crtc info */
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++
++	/* set scaler clears this on some chips */
++	dce_v10_0_set_interleave(encoder->crtc, mode);
++
++	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
++		dce_v10_0_afmt_enable(encoder, true);
++		dce_v10_0_afmt_setmode(encoder, adjusted_mode);
++	}
++}
++
++static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++
++	if ((amdgpu_encoder->active_device &
++	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
++	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
++	     ENCODER_OBJECT_ID_NONE)) {
++		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++		if (dig) {
++			dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
++			if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
++				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
++		}
++	}
++
++	amdgpu_atombios_scratch_regs_lock(adev, true);
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		/* select the clock/data port if it uses a router */
++		if (amdgpu_connector->router.cd_valid)
++			amdgpu_i2c_router_select_cd_port(amdgpu_connector);
++
++		/* turn eDP panel on for mode set */
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
++			amdgpu_atombios_encoder_set_edp_panel_power(connector,
++							     ATOM_TRANSMITTER_ACTION_POWER_ON);
++	}
++
++	/* this is needed for the pll/ss setup to work correctly in some cases */
++	amdgpu_atombios_encoder_set_crtc_source(encoder);
++	/* set up the FMT blocks */
++	dce_v10_0_program_fmt(encoder);
++}
++
++static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	/* need to call this here as we need the crtc set up */
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
++	amdgpu_atombios_scratch_regs_lock(adev, false);
++}
++
++static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig;
++
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++
++	if (amdgpu_atombios_encoder_is_digital(encoder)) {
++		if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
++			dce_v10_0_afmt_enable(encoder, false);
++		dig = amdgpu_encoder->enc_priv;
++		dig->dig_encoder = -1;
++	}
++	amdgpu_encoder->active_device = 0;
++}
++
++/* these are handled by the primary encoders */
++static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
++{
++
++}
++
++static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
++{
++
++}
++
++static void
++dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
++		      struct drm_display_mode *mode,
++		      struct drm_display_mode *adjusted_mode)
++{
++
++}
++
++static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
++{
++
++}
++
++static void
++dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
++{
++
++}
++
++static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder,
++				    const struct drm_display_mode *mode,
++				    struct drm_display_mode *adjusted_mode)
++{
++	return true;
++}
++
++static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
++	.dpms = dce_v10_0_ext_dpms,
++	.mode_fixup = dce_v10_0_ext_mode_fixup,
++	.prepare = dce_v10_0_ext_prepare,
++	.mode_set = dce_v10_0_ext_mode_set,
++	.commit = dce_v10_0_ext_commit,
++	.disable = dce_v10_0_ext_disable,
++	/* no detect for TMDS/LVDS yet */
++};
++
++static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
++	.dpms = amdgpu_atombios_encoder_dpms,
++	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
++	.prepare = dce_v10_0_encoder_prepare,
++	.mode_set = dce_v10_0_encoder_mode_set,
++	.commit = dce_v10_0_encoder_commit,
++	.disable = dce_v10_0_encoder_disable,
++	.detect = amdgpu_atombios_encoder_dig_detect,
++};
++
++static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
++	.dpms = amdgpu_atombios_encoder_dpms,
++	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
++	.prepare = dce_v10_0_encoder_prepare,
++	.mode_set = dce_v10_0_encoder_mode_set,
++	.commit = dce_v10_0_encoder_commit,
++	.detect = amdgpu_atombios_encoder_dac_detect,
++};
++
++static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++		amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
++	kfree(amdgpu_encoder->enc_priv);
++	drm_encoder_cleanup(encoder);
++	kfree(amdgpu_encoder);
++}
++
++static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
++	.destroy = dce_v10_0_encoder_destroy,
++};
++
++static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
++				 uint32_t encoder_enum,
++				 uint32_t supported_device,
++				 u16 caps)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++
++	/* see if we already added it */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++		if (amdgpu_encoder->encoder_enum == encoder_enum) {
++			amdgpu_encoder->devices |= supported_device;
++			return;
++		}
++
++	}
++
++	/* add a new one */
++	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
++	if (!amdgpu_encoder)
++		return;
++
++	encoder = &amdgpu_encoder->base;
++	switch (adev->mode_info.num_crtc) {
++	case 1:
++		encoder->possible_crtcs = 0x1;
++		break;
++	case 2:
++	default:
++		encoder->possible_crtcs = 0x3;
++		break;
++	case 4:
++		encoder->possible_crtcs = 0xf;
++		break;
++	case 6:
++		encoder->possible_crtcs = 0x3f;
++		break;
++	}
++
++	amdgpu_encoder->enc_priv = NULL;
++
++	amdgpu_encoder->encoder_enum = encoder_enum;
++	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
++	amdgpu_encoder->devices = supported_device;
++	amdgpu_encoder->rmx_type = RMX_OFF;
++	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
++	amdgpu_encoder->is_ext_encoder = false;
++	amdgpu_encoder->caps = caps;
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++		drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++				 DRM_MODE_ENCODER_DAC);
++		drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++			amdgpu_encoder->rmx_type = RMX_FULL;
++			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++					 DRM_MODE_ENCODER_LVDS);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
++		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
++			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++					 DRM_MODE_ENCODER_DAC);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
++		} else {
++			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++					 DRM_MODE_ENCODER_TMDS);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
++		}
++		drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
++		break;
++	case ENCODER_OBJECT_ID_SI170B:
++	case ENCODER_OBJECT_ID_CH7303:
++	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
++	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
++	case ENCODER_OBJECT_ID_TITFP513:
++	case ENCODER_OBJECT_ID_VT1623:
++	case ENCODER_OBJECT_ID_HDMI_SI1930:
++	case ENCODER_OBJECT_ID_TRAVIS:
++	case ENCODER_OBJECT_ID_NUTMEG:
++		/* these are handled by the primary encoders */
++		amdgpu_encoder->is_ext_encoder = true;
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++					 DRM_MODE_ENCODER_LVDS);
++		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
++			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++					 DRM_MODE_ENCODER_DAC);
++		else
++			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
++					 DRM_MODE_ENCODER_TMDS);
++		drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
++		break;
++	}
++}
++
++static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
++	.set_vga_render_state = &dce_v10_0_set_vga_render_state,
++	.bandwidth_update = &dce_v10_0_bandwidth_update,
++	.vblank_get_counter = &dce_v10_0_vblank_get_counter,
++	.vblank_wait = &dce_v10_0_vblank_wait,
++	.is_display_hung = &dce_v10_0_is_display_hung,
++	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
++	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
++	.hpd_sense = &dce_v10_0_hpd_sense,
++	.hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
++	.hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
++	.page_flip = &dce_v10_0_page_flip,
++	.page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
++	.add_encoder = &dce_v10_0_encoder_add,
++	.add_connector = &amdgpu_connector_add,
++	.stop_mc_access = &dce_v10_0_stop_mc_access,
++	.resume_mc_access = &dce_v10_0_resume_mc_access,
++};
++
++static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
++{
++	if (adev->mode_info.funcs == NULL)
++		adev->mode_info.funcs = &dce_v10_0_display_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
++	.set = dce_v10_0_set_crtc_irq_state,
++	.process = dce_v10_0_crtc_irq,
++};
++
++static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
++	.set = dce_v10_0_set_pageflip_irq_state,
++	.process = dce_v10_0_pageflip_irq,
++};
++
++static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
++	.set = dce_v10_0_set_hpd_irq_state,
++	.process = dce_v10_0_hpd_irq,
++};
++
++static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
++	adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
++
++	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
++	adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
++
++	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
++	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
+new file mode 100644
+index 0000000..72ca20d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __DCE_V10_0_H__
++#define __DCE_V10_0_H__
++
++extern const struct amdgpu_ip_funcs dce_v10_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+new file mode 100644
+index 0000000..55fef15
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+@@ -0,0 +1,3871 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_pm.h"
++#include "amdgpu_i2c.h"
++#include "vid.h"
++#include "atom.h"
++#include "amdgpu_atombios.h"
++#include "atombios_crtc.h"
++#include "atombios_encoders.h"
++#include "amdgpu_pll.h"
++#include "amdgpu_connectors.h"
++
++#include "dce/dce_11_0_d.h"
++#include "dce/dce_11_0_sh_mask.h"
++#include "dce/dce_11_0_enum.h"
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
++static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
++
++static const u32 crtc_offsets[] =
++{
++	CRTC0_REGISTER_OFFSET,
++	CRTC1_REGISTER_OFFSET,
++	CRTC2_REGISTER_OFFSET,
++	CRTC3_REGISTER_OFFSET,
++	CRTC4_REGISTER_OFFSET,
++	CRTC5_REGISTER_OFFSET,
++	CRTC6_REGISTER_OFFSET
++};
++
++static const u32 hpd_offsets[] =
++{
++	HPD0_REGISTER_OFFSET,
++	HPD1_REGISTER_OFFSET,
++	HPD2_REGISTER_OFFSET,
++	HPD3_REGISTER_OFFSET,
++	HPD4_REGISTER_OFFSET,
++	HPD5_REGISTER_OFFSET
++};
++
++static const uint32_t dig_offsets[] = {
++	DIG0_REGISTER_OFFSET,
++	DIG1_REGISTER_OFFSET,
++	DIG2_REGISTER_OFFSET,
++	DIG3_REGISTER_OFFSET,
++	DIG4_REGISTER_OFFSET,
++	DIG5_REGISTER_OFFSET,
++	DIG6_REGISTER_OFFSET,
++	DIG7_REGISTER_OFFSET,
++	DIG8_REGISTER_OFFSET
++};
++
++static const struct {
++	uint32_t        reg;
++	uint32_t        vblank;
++	uint32_t        vline;
++	uint32_t        hpd;
++
++} interrupt_status_offsets[] = { {
++	.reg = mmDISP_INTERRUPT_STATUS,
++	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
++}, {
++	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
++	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
++	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
++	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
++} };
++
++static const u32 cz_golden_settings_a11[] =
++{
++	mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
++	mmFBC_MISC, 0x1f311fff, 0x14300000,
++};
++
++static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_CARRIZO:
++		amdgpu_program_register_sequence(adev,
++						 cz_golden_settings_a11,
++						 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
++		break;
++	default:
++		break;
++	}
++}
++
++static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
++				     u32 block_offset, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
++	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
++	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
++
++	return r;
++}
++
++static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
++				      u32 block_offset, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
++	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
++	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
++}
++
++static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
++{
++	if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
++			CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
++		return true;
++	else
++		return false;
++}
++
++static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
++{
++	u32 pos1, pos2;
++
++	pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++	pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++	if (pos1 != pos2)
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v11_0_vblank_wait - vblank wait asic callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @crtc: crtc to wait for vblank on
++ *
++ * Wait for vblank on the requested crtc (evergreen+).
++ */
++static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
++{
++	unsigned i = 0;
++
++	if (crtc >= adev->mode_info.num_crtc)
++		return;
++
++	if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
++		return;
++
++	/* depending on when we hit vblank, we may be close to active; if so,
++	 * wait for another frame.
++	 */
++	while (dce_v11_0_is_in_vblank(adev, crtc)) {
++		if (i++ % 100 == 0) {
++			if (!dce_v11_0_is_counter_moving(adev, crtc))
++				break;
++		}
++	}
++
++	while (!dce_v11_0_is_in_vblank(adev, crtc)) {
++		if (i++ % 100 == 0) {
++			if (!dce_v11_0_is_counter_moving(adev, crtc))
++				break;
++		}
++	}
++}
++
++static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
++{
++	if (crtc >= adev->mode_info.num_crtc)
++		return 0;
++	else
++		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
++}
++
++/**
++ * dce_v11_0_page_flip - pageflip callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @crtc_id: crtc to cleanup pageflip on
++ * @crtc_base: new address of the crtc (GPU MC address)
++ *
++ * Does the actual pageflip (evergreen+).
++ * During vblank we take the crtc lock and wait for the update_pending
++ * bit to go high, when it does, we release the lock, and allow the
++ * double buffered update to take place.
++ * Returns the current update pending status.
++ */
++static void dce_v11_0_page_flip(struct amdgpu_device *adev,
++			      int crtc_id, u64 crtc_base)
++{
++	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
++	int i;
++
++	/* Lock the graphics update lock */
++	tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
++	WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
++
++	/* update the scanout addresses */
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(crtc_base));
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       lower_32_bits(crtc_base));
++
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(crtc_base));
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       lower_32_bits(crtc_base));
++
++	/* Wait for update_pending to go high. */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
++				GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
++			break;
++		udelay(1);
++	}
++	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
++
++	/* Unlock the lock, so double-buffering can take place inside vblank */
++	tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
++	WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);	
++}
++
++static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
++					u32 *vbl, u32 *position)
++{
++	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
++		return -EINVAL;
++
++	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
++	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
++
++	return 0;
++}
++
++/**
++ * dce_v11_0_hpd_sense - hpd sense callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @hpd: hpd (hotplug detect) pin
++ *
++ * Checks if a digital monitor is connected (evergreen+).
++ * Returns true if connected, false if not connected.
++ */
++static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
++			       enum amdgpu_hpd_id hpd)
++{
++	int idx;
++	bool connected = false;
++
++	switch (hpd) {
++	case AMDGPU_HPD_1:
++		idx = 0;
++		break;
++	case AMDGPU_HPD_2:
++		idx = 1;
++		break;
++	case AMDGPU_HPD_3:
++		idx = 2;
++		break;
++	case AMDGPU_HPD_4:
++		idx = 3;
++		break;
++	case AMDGPU_HPD_5:
++		idx = 4;
++		break;
++	case AMDGPU_HPD_6:
++		idx = 5;
++		break;
++	default:
++		return connected;
++	}
++
++	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
++	    DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
++		connected = true;
++
++	return connected;
++}
++
++/**
++ * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
++ *
++ * @adev: amdgpu_device pointer
++ * @hpd: hpd (hotplug detect) pin
++ *
++ * Set the polarity of the hpd pin (evergreen+).
++ */
++static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
++				      enum amdgpu_hpd_id hpd)
++{
++	u32 tmp;
++	bool connected = dce_v11_0_hpd_sense(adev, hpd);
++	int idx;
++
++	switch (hpd) {
++	case AMDGPU_HPD_1:
++		idx = 0;
++		break;
++	case AMDGPU_HPD_2:
++		idx = 1;
++		break;
++	case AMDGPU_HPD_3:
++		idx = 2;
++		break;
++	case AMDGPU_HPD_4:
++		idx = 3;
++		break;
++	case AMDGPU_HPD_5:
++		idx = 4;
++		break;
++	case AMDGPU_HPD_6:
++		idx = 5;
++		break;
++	default:
++		return;
++	}
++
++	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
++	if (connected)
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
++	else
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
++	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
++}
++
++/**
++ * dce_v11_0_hpd_init - hpd setup callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup the hpd pins used by the card (evergreen+).
++ * Enable the pin, set the polarity, and enable the hpd interrupts.
++ */
++static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++	u32 tmp;
++	int idx;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
++		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
++			/* don't try to enable hpd on eDP or LVDS avoid breaking the
++			 * aux dp channel on imac and help (but not completely fix)
++			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
++			 * also avoid interrupt storms during dpms.
++			 */
++			continue;
++		}
++
++		switch (amdgpu_connector->hpd.hpd) {
++		case AMDGPU_HPD_1:
++			idx = 0;
++			break;
++		case AMDGPU_HPD_2:
++			idx = 1;
++			break;
++		case AMDGPU_HPD_3:
++			idx = 2;
++			break;
++		case AMDGPU_HPD_4:
++			idx = 3;
++			break;
++		case AMDGPU_HPD_5:
++			idx = 4;
++			break;
++		case AMDGPU_HPD_6:
++			idx = 5;
++			break;
++		default:
++			continue;
++		}
++
++		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
++		WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
++
++		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
++				    DC_HPD_CONNECT_INT_DELAY,
++				    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
++				    DC_HPD_DISCONNECT_INT_DELAY,
++				    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
++		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
++
++		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
++		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
++	}
++}
++
++/**
++ * dce_v11_0_hpd_fini - hpd tear down callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down the hpd pins used by the card (evergreen+).
++ * Disable the hpd interrupts.
++ */
++static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_connector *connector;
++	u32 tmp;
++	int idx;
++
++	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		switch (amdgpu_connector->hpd.hpd) {
++		case AMDGPU_HPD_1:
++			idx = 0;
++			break;
++		case AMDGPU_HPD_2:
++			idx = 1;
++			break;
++		case AMDGPU_HPD_3:
++			idx = 2;
++			break;
++		case AMDGPU_HPD_4:
++			idx = 3;
++			break;
++		case AMDGPU_HPD_5:
++			idx = 4;
++			break;
++		case AMDGPU_HPD_6:
++			idx = 5;
++			break;
++		default:
++			continue;
++		}
++
++		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
++		WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
++
++		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
++	}
++}
++
++static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
++{
++	return mmDC_GPIO_HPD_A;
++}
++
++static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
++{
++	u32 crtc_hung = 0;
++	u32 crtc_status[6];
++	u32 i, j, tmp;
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
++		if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
++			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
++			crtc_hung |= (1 << i);
++		}
++	}
++
++	for (j = 0; j < 10; j++) {
++		for (i = 0; i < adev->mode_info.num_crtc; i++) {
++			if (crtc_hung & (1 << i)) {
++				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
++				if (tmp != crtc_status[i])
++					crtc_hung &= ~(1 << i);
++			}
++		}
++		if (crtc_hung == 0)
++			return false;
++		udelay(100);
++	}
++
++	return true;
++}
++
++static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
++				     struct amdgpu_mode_mc_save *save)
++{
++	u32 crtc_enabled, tmp;
++	int i;
++
++	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
++	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
++
++	/* disable VGA render */
++	tmp = RREG32(mmVGA_RENDER_CONTROL);
++	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++	WREG32(mmVGA_RENDER_CONTROL, tmp);
++
++	/* blank the display controllers */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
++					     CRTC_CONTROL, CRTC_MASTER_EN);
++		if (crtc_enabled) {
++#if 0
++			u32 frame_count;
++			int j;
++
++			save->crtc_enabled[i] = true;
++			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
++				amdgpu_display_vblank_wait(adev, i);
++				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
++				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			}
++			/* wait for the next frame */
++			frame_count = amdgpu_display_vblank_get_counter(adev, i);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
++					break;
++				udelay(1);
++			}
++			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
++				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
++				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
++				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
++				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++			}
++#else
++			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
++			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
++			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			save->crtc_enabled[i] = false;
++			/* ***** */
++#endif
++		} else {
++			save->crtc_enabled[i] = false;
++		}
++	}
++}
++
++static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
++				       struct amdgpu_mode_mc_save *save)
++{
++	u32 tmp, frame_count;
++	int i, j;
++
++	/* update crtc base addresses */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
++		       upper_32_bits(adev->mc.vram_start));
++		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
++		       upper_32_bits(adev->mc.vram_start));
++		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
++		       (u32)adev->mc.vram_start);
++		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
++		       (u32)adev->mc.vram_start);
++
++		if (save->crtc_enabled[i]) {
++			tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
++				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
++				WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
++				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
++				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
++			}
++			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
++			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
++				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
++				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
++			}
++			for (j = 0; j < adev->usec_timeout; j++) {
++				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
++				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
++					break;
++				udelay(1);
++			}
++			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
++			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
++			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
++			/* wait for the next frame */
++			frame_count = amdgpu_display_vblank_get_counter(adev, i);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
++					break;
++				udelay(1);
++			}
++		}
++	}
++
++	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
++	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
++
++	/* Unlock vga access */
++	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
++	mdelay(1);
++	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
++}
++
++static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
++					   bool render)
++{
++	u32 tmp;
++
++	/* Lockout access through VGA aperture*/
++	tmp = RREG32(mmVGA_HDP_CONTROL);
++	if (render)
++		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
++	else
++		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
++	WREG32(mmVGA_HDP_CONTROL, tmp);
++
++	/* disable VGA render */
++	tmp = RREG32(mmVGA_RENDER_CONTROL);
++	if (render)
++		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++	WREG32(mmVGA_RENDER_CONTROL, tmp);
++}
++
++static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	int bpc = 0;
++	u32 tmp = 0;
++	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++		bpc = amdgpu_connector_get_monitor_bpc(connector);
++		dither = amdgpu_connector->dither;
++	}
++
++	/* LVDS/eDP FMT is set up by atom */
++	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
++		return;
++
++	/* not needed for analog */
++	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
++	    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
++		return;
++
++	if (bpc == 0)
++		return;
++
++	switch (bpc) {
++	case 6:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
++			/* XXX sort out optimal dither settings */
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
++		} else {
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
++		}
++		break;
++	case 8:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
++			/* XXX sort out optimal dither settings */
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
++		} else {
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
++		}
++		break;
++	case 10:
++		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
++			/* XXX sort out optimal dither settings */
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
++		} else {
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
++			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
++		}
++		break;
++	default:
++		/* not needed */
++		break;
++	}
++
++	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++
++/* display watermark setup */
++/**
++ * dce_v11_0_line_buffer_adjust - Set up the line buffer
++ *
++ * @adev: amdgpu_device pointer
++ * @amdgpu_crtc: the selected display controller
++ * @mode: the current display mode on the selected display
++ * controller
++ *
++ * Setup up the line buffer allocation for
++ * the selected display controller (CIK).
++ * Returns the line buffer size in pixels.
++ */
++static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
++				       struct amdgpu_crtc *amdgpu_crtc,
++				       struct drm_display_mode *mode)
++{
++	u32 tmp, buffer_alloc, i, mem_cfg;
++	u32 pipe_offset = amdgpu_crtc->crtc_id;
++	/*
++	 * Line Buffer Setup
++	 * There are 6 line buffers, one for each display controllers.
++	 * There are 3 partitions per LB. Select the number of partitions
++	 * to enable based on the display width.  For display widths larger
++	 * than 4096, you need use to use 2 display controllers and combine
++	 * them using the stereo blender.
++	 */
++	if (amdgpu_crtc->base.enabled && mode) {
++		if (mode->crtc_hdisplay < 1920) {
++			mem_cfg = 1;
++			buffer_alloc = 2;
++		} else if (mode->crtc_hdisplay < 2560) {
++			mem_cfg = 2;
++			buffer_alloc = 2;
++		} else if (mode->crtc_hdisplay < 4096) {
++			mem_cfg = 0;
++			buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
++		} else {
++			DRM_DEBUG_KMS("Mode too big for LB!\n");
++			mem_cfg = 0;
++			buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4;
++		}
++	} else {
++		mem_cfg = 1;
++		buffer_alloc = 0;
++	}
++
++	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
++	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
++	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
++	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
++		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
++			break;
++		udelay(1);
++	}
++
++	if (amdgpu_crtc->base.enabled && mode) {
++		switch (mem_cfg) {
++		case 0:
++		default:
++			return 4096 * 2;
++		case 1:
++			return 1920 * 2;
++		case 2:
++			return 2560 * 2;
++		}
++	}
++
++	/* controller not enabled, so no lb used */
++	return 0;
++}
++
++/**
++ * cik_get_number_of_dram_channels - get the number of dram channels
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up the number of video ram channels (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the number of dram channels
++ */
++static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
++
++	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
++	case 0:
++	default:
++		return 1;
++	case 1:
++		return 2;
++	case 2:
++		return 4;
++	case 3:
++		return 8;
++	case 4:
++		return 3;
++	case 5:
++		return 6;
++	case 6:
++		return 10;
++	case 7:
++		return 12;
++	case 8:
++		return 16;
++	}
++}
++
++struct dce10_wm_params {
++	u32 dram_channels; /* number of dram channels */
++	u32 yclk;          /* bandwidth per dram data pin in kHz */
++	u32 sclk;          /* engine clock in kHz */
++	u32 disp_clk;      /* display clock in kHz */
++	u32 src_width;     /* viewport width */
++	u32 active_time;   /* active display time in ns */
++	u32 blank_time;    /* blank time in ns */
++	bool interlaced;    /* mode is interlaced */
++	fixed20_12 vsc;    /* vertical scale ratio */
++	u32 num_heads;     /* number of active crtcs */
++	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
++	u32 lb_size;       /* line buffer allocated to pipe */
++	u32 vtaps;         /* vertical scaler taps */
++};
++
++/**
++ * dce_v11_0_dram_bandwidth - get the dram bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the raw dram bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dram bandwidth in MBytes/s
++ */
++static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate raw DRAM Bandwidth */
++	fixed20_12 dram_efficiency; /* 0.7 */
++	fixed20_12 yclk, dram_channels, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	yclk.full = dfixed_const(wm->yclk);
++	yclk.full = dfixed_div(yclk, a);
++	dram_channels.full = dfixed_const(wm->dram_channels * 4);
++	a.full = dfixed_const(10);
++	dram_efficiency.full = dfixed_const(7);
++	dram_efficiency.full = dfixed_div(dram_efficiency, a);
++	bandwidth.full = dfixed_mul(dram_channels, yclk);
++	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the dram bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dram bandwidth for display in MBytes/s
++ */
++static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
++{
++	/* Calculate DRAM Bandwidth and the part allocated to display. */
++	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
++	fixed20_12 yclk, dram_channels, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	yclk.full = dfixed_const(wm->yclk);
++	yclk.full = dfixed_div(yclk, a);
++	dram_channels.full = dfixed_const(wm->dram_channels * 4);
++	a.full = dfixed_const(10);
++	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
++	disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
++	bandwidth.full = dfixed_mul(dram_channels, yclk);
++	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v11_0_data_return_bandwidth - get the data return bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the data return bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the data return bandwidth in MBytes/s
++ */
++static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the display Data return Bandwidth */
++	fixed20_12 return_efficiency; /* 0.8 */
++	fixed20_12 sclk, bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	sclk.full = dfixed_const(wm->sclk);
++	sclk.full = dfixed_div(sclk, a);
++	a.full = dfixed_const(10);
++	return_efficiency.full = dfixed_const(8);
++	return_efficiency.full = dfixed_div(return_efficiency, a);
++	a.full = dfixed_const(32);
++	bandwidth.full = dfixed_mul(a, sclk);
++	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the dmif bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the dmif bandwidth in MBytes/s
++ */
++static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the DMIF Request Bandwidth */
++	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
++	fixed20_12 disp_clk, bandwidth;
++	fixed20_12 a, b;
++
++	a.full = dfixed_const(1000);
++	disp_clk.full = dfixed_const(wm->disp_clk);
++	disp_clk.full = dfixed_div(disp_clk, a);
++	a.full = dfixed_const(32);
++	b.full = dfixed_mul(a, disp_clk);
++
++	a.full = dfixed_const(10);
++	disp_clk_request_efficiency.full = dfixed_const(8);
++	disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
++
++	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v11_0_available_bandwidth - get the min available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the min available bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the min available bandwidth in MBytes/s
++ */
++static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
++	u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
++	u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
++	u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
++
++	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
++}
++
++/**
++ * dce_v11_0_average_bandwidth - get the average available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the average available bandwidth used for display (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the average available bandwidth in MBytes/s
++ */
++static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
++{
++	/* Calculate the display mode Average Bandwidth
++	 * DisplayMode should contain the source and destination dimensions,
++	 * timing, etc.
++	 */
++	fixed20_12 bpp;
++	fixed20_12 line_time;
++	fixed20_12 src_width;
++	fixed20_12 bandwidth;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1000);
++	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
++	line_time.full = dfixed_div(line_time, a);
++	bpp.full = dfixed_const(wm->bytes_per_pixel);
++	src_width.full = dfixed_const(wm->src_width);
++	bandwidth.full = dfixed_mul(src_width, bpp);
++	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
++	bandwidth.full = dfixed_div(bandwidth, line_time);
++
++	return dfixed_trunc(bandwidth);
++}
++
++/**
++ * dce_v11_0_latency_watermark - get the latency watermark
++ *
++ * @wm: watermark calculation data
++ *
++ * Calculate the latency watermark (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns the latency watermark in ns
++ */
++static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
++{
++	/* First calculate the latency in ns */
++	u32 mc_latency = 2000; /* 2000 ns. */
++	u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
++	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
++	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
++	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
++	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
++		(wm->num_heads * cursor_line_pair_return_time);
++	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
++	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
++	u32 tmp, dmif_size = 12288;
++	fixed20_12 a, b, c;
++
++	if (wm->num_heads == 0)
++		return 0;
++
++	a.full = dfixed_const(2);
++	b.full = dfixed_const(1);
++	if ((wm->vsc.full > a.full) ||
++	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
++	    (wm->vtaps >= 5) ||
++	    ((wm->vsc.full >= a.full) && wm->interlaced))
++		max_src_lines_per_dst_line = 4;
++	else
++		max_src_lines_per_dst_line = 2;
++
++	a.full = dfixed_const(available_bandwidth);
++	b.full = dfixed_const(wm->num_heads);
++	a.full = dfixed_div(a, b);
++
++	b.full = dfixed_const(mc_latency + 512);
++	c.full = dfixed_const(wm->disp_clk);
++	b.full = dfixed_div(b, c);
++
++	c.full = dfixed_const(dmif_size);
++	b.full = dfixed_div(c, b);
++
++	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
++
++	b.full = dfixed_const(1000);
++	c.full = dfixed_const(wm->disp_clk);
++	b.full = dfixed_div(c, b);
++	c.full = dfixed_const(wm->bytes_per_pixel);
++	b.full = dfixed_mul(b, c);
++
++	lb_fill_bw = min(tmp, dfixed_trunc(b));
++
++	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
++	b.full = dfixed_const(1000);
++	c.full = dfixed_const(lb_fill_bw);
++	b.full = dfixed_div(c, b);
++	a.full = dfixed_div(a, b);
++	line_fill_time = dfixed_trunc(a);
++
++	if (line_fill_time < wm->active_time)
++		return latency;
++	else
++		return latency + (line_fill_time - wm->active_time);
++
++}
++
++/**
++ * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
++ * average and available dram bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Check if the display average bandwidth fits in the display
++ * dram bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
++{
++	if (dce_v11_0_average_bandwidth(wm) <=
++	    (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
++ * average and available bandwidth
++ *
++ * @wm: watermark calculation data
++ *
++ * Check if the display average bandwidth fits in the display
++ * available bandwidth (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
++{
++	if (dce_v11_0_average_bandwidth(wm) <=
++	    (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v11_0_check_latency_hiding - check latency hiding
++ *
++ * @wm: watermark calculation data
++ *
++ * Check latency hiding (CIK).
++ * Used for display watermark bandwidth calculations
++ * Returns true if the display fits, false if not.
++ */
++static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
++{
++	u32 lb_partitions = wm->lb_size / wm->src_width;
++	u32 line_time = wm->active_time + wm->blank_time;
++	u32 latency_tolerant_lines;
++	u32 latency_hiding;
++	fixed20_12 a;
++
++	a.full = dfixed_const(1);
++	if (wm->vsc.full > a.full)
++		latency_tolerant_lines = 1;
++	else {
++		if (lb_partitions <= (wm->vtaps + 1))
++			latency_tolerant_lines = 1;
++		else
++			latency_tolerant_lines = 2;
++	}
++
++	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
++
++	if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
++		return true;
++	else
++		return false;
++}
++
++/**
++ * dce_v11_0_program_watermarks - program display watermarks
++ *
++ * @adev: amdgpu_device pointer
++ * @amdgpu_crtc: the selected display controller
++ * @lb_size: line buffer size
++ * @num_heads: number of display controllers in use
++ *
++ * Calculate and program the display watermarks for the
++ * selected display controller (CIK).
++ */
++static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
++					struct amdgpu_crtc *amdgpu_crtc,
++					u32 lb_size, u32 num_heads)
++{
++	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
++	struct dce10_wm_params wm_low, wm_high;
++	u32 pixel_period;
++	u32 line_time = 0;
++	u32 latency_watermark_a = 0, latency_watermark_b = 0;
++	u32 tmp, wm_mask;
++
++	if (amdgpu_crtc->base.enabled && num_heads && mode) {
++		pixel_period = 1000000 / (u32)mode->clock;
++		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
++
++		/* watermark for high clocks */
++		if (adev->pm.dpm_enabled) {
++			wm_high.yclk =
++				amdgpu_dpm_get_mclk(adev, false) * 10;
++			wm_high.sclk =
++				amdgpu_dpm_get_sclk(adev, false) * 10;
++		} else {
++			wm_high.yclk = adev->pm.current_mclk * 10;
++			wm_high.sclk = adev->pm.current_sclk * 10;
++		}
++
++		wm_high.disp_clk = mode->clock;
++		wm_high.src_width = mode->crtc_hdisplay;
++		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
++		wm_high.blank_time = line_time - wm_high.active_time;
++		wm_high.interlaced = false;
++		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++			wm_high.interlaced = true;
++		wm_high.vsc = amdgpu_crtc->vsc;
++		wm_high.vtaps = 1;
++		if (amdgpu_crtc->rmx_type != RMX_OFF)
++			wm_high.vtaps = 2;
++		wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
++		wm_high.lb_size = lb_size;
++		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
++		wm_high.num_heads = num_heads;
++
++		/* set for high clocks */
++		latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
++
++		/* possibly force display priority to high */
++		/* should really do this at mode validation time... */
++		if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
++		    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
++		    !dce_v11_0_check_latency_hiding(&wm_high) ||
++		    (adev->mode_info.disp_priority == 2)) {
++			DRM_DEBUG_KMS("force priority to high\n");
++		}
++
++		/* watermark for low clocks */
++		if (adev->pm.dpm_enabled) {
++			wm_low.yclk =
++				amdgpu_dpm_get_mclk(adev, true) * 10;
++			wm_low.sclk =
++				amdgpu_dpm_get_sclk(adev, true) * 10;
++		} else {
++			wm_low.yclk = adev->pm.current_mclk * 10;
++			wm_low.sclk = adev->pm.current_sclk * 10;
++		}
++
++		wm_low.disp_clk = mode->clock;
++		wm_low.src_width = mode->crtc_hdisplay;
++		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
++		wm_low.blank_time = line_time - wm_low.active_time;
++		wm_low.interlaced = false;
++		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++			wm_low.interlaced = true;
++		wm_low.vsc = amdgpu_crtc->vsc;
++		wm_low.vtaps = 1;
++		if (amdgpu_crtc->rmx_type != RMX_OFF)
++			wm_low.vtaps = 2;
++		wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
++		wm_low.lb_size = lb_size;
++		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
++		wm_low.num_heads = num_heads;
++
++		/* set for low clocks */
++		latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
++
++		/* possibly force display priority to high */
++		/* should really do this at mode validation time... */
++		if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
++		    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
++		    !dce_v11_0_check_latency_hiding(&wm_low) ||
++		    (adev->mode_info.disp_priority == 2)) {
++			DRM_DEBUG_KMS("force priority to high\n");
++		}
++	}
++
++	/* select wm A */
++	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
++	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	/* select wm B */
++	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
++	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
++	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	/* restore original selection */
++	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
++
++	/* save values for DPM */
++	amdgpu_crtc->line_time = line_time;
++	amdgpu_crtc->wm_high = latency_watermark_a;
++	amdgpu_crtc->wm_low = latency_watermark_b;
++}
++
++/**
++ * dce_v11_0_bandwidth_update - program display watermarks
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Calculate and program the display watermarks and line
++ * buffer allocation (CIK).
++ */
++static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
++{
++	struct drm_display_mode *mode = NULL;
++	u32 num_heads = 0, lb_size;
++	int i;
++
++	amdgpu_update_display_priority(adev);
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (adev->mode_info.crtcs[i]->base.enabled)
++			num_heads++;
++	}
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		mode = &adev->mode_info.crtcs[i]->base.mode;
++		lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
++		dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
++					    lb_size, num_heads);
++	}
++}
++
++static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
++{
++	int i;
++	u32 offset, tmp;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		offset = adev->mode_info.audio.pin[i].offset;
++		tmp = RREG32_AUDIO_ENDPT(offset,
++					 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
++		if (((tmp &
++		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
++		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
++			adev->mode_info.audio.pin[i].connected = false;
++		else
++			adev->mode_info.audio.pin[i].connected = true;
++	}
++}
++
++static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v11_0_audio_get_connected_pins(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		if (adev->mode_info.audio.pin[i].connected)
++			return &adev->mode_info.audio.pin[i];
++	}
++	DRM_ERROR("No connected audio pins found!\n");
++	return NULL;
++}
++
++static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u32 tmp;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
++	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
++}
++
++static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
++						struct drm_display_mode *mode)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	u32 tmp;
++	int interlace = 0;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		interlace = 1;
++	if (connector->latency_present[interlace]) {
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    VIDEO_LIPSYNC, connector->video_latency[interlace]);
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    AUDIO_LIPSYNC, connector->audio_latency[interlace]);
++	} else {
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    VIDEO_LIPSYNC, 0);
++		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
++				    AUDIO_LIPSYNC, 0);
++	}
++	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
++			   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
++}
++
++static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	u32 tmp;
++	u8 *sadb = NULL;
++	int sad_count;
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
++	if (sad_count < 0) {
++		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
++		sad_count = 0;
++	}
++
++	/* program the speaker allocation */
++	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
++				 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
++	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++			    DP_CONNECTION, 0);
++	/* set HDMI mode */
++	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++			    HDMI_CONNECTION, 1);
++	if (sad_count)
++		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++				    SPEAKER_ALLOCATION, sadb[0]);
++	else
++		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
++				    SPEAKER_ALLOCATION, 5); /* stereo */
++	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
++			   ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
++
++	kfree(sadb);
++}
++
++static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector;
++	struct amdgpu_connector *amdgpu_connector = NULL;
++	struct cea_sad *sads;
++	int i, sad_count;
++
++	static const u16 eld_reg_to_type[][2] = {
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
++		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
++	};
++
++	if (!dig || !dig->afmt || !dig->afmt->pin)
++		return;
++
++	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++		if (connector->encoder == encoder) {
++			amdgpu_connector = to_amdgpu_connector(connector);
++			break;
++		}
++	}
++
++	if (!amdgpu_connector) {
++		DRM_ERROR("Couldn't find encoder's connector\n");
++		return;
++	}
++
++	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
++	if (sad_count <= 0) {
++		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++		return;
++	}
++	BUG_ON(!sads);
++
++	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
++		u32 tmp = 0;
++		u8 stereo_freqs = 0;
++		int max_channels = -1;
++		int j;
++
++		for (j = 0; j < sad_count; j++) {
++			struct cea_sad *sad = &sads[j];
++
++			if (sad->format == eld_reg_to_type[i][1]) {
++				if (sad->channels > max_channels) {
++					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++							    MAX_CHANNELS, sad->channels);
++					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++							    DESCRIPTOR_BYTE_2, sad->byte2);
++					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++							    SUPPORTED_FREQUENCIES, sad->freq);
++					max_channels = sad->channels;
++				}
++
++				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
++					stereo_freqs |= sad->freq;
++				else
++					break;
++			}
++		}
++
++		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
++				    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
++		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
++	}
++
++	kfree(sads);
++}
++
++static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
++				  struct amdgpu_audio_pin *pin,
++				  bool enable)
++{
++	if (!pin)
++		return;
++
++	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
++			   enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
++}
++
++static const u32 pin_offsets[] =
++{
++	AUD0_REGISTER_OFFSET,
++	AUD1_REGISTER_OFFSET,
++	AUD2_REGISTER_OFFSET,
++	AUD3_REGISTER_OFFSET,
++	AUD4_REGISTER_OFFSET,
++	AUD5_REGISTER_OFFSET,
++	AUD6_REGISTER_OFFSET,
++};
++
++static int dce_v11_0_audio_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (!amdgpu_audio)
++		return 0;
++
++	adev->mode_info.audio.enabled = true;
++
++	adev->mode_info.audio.num_pins = 7;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		adev->mode_info.audio.pin[i].channels = -1;
++		adev->mode_info.audio.pin[i].rate = -1;
++		adev->mode_info.audio.pin[i].bits_per_sample = -1;
++		adev->mode_info.audio.pin[i].status_bits = 0;
++		adev->mode_info.audio.pin[i].category_code = 0;
++		adev->mode_info.audio.pin[i].connected = false;
++		adev->mode_info.audio.pin[i].offset = pin_offsets[i];
++		adev->mode_info.audio.pin[i].id = i;
++		/* disable audio.  it will be set up later */
++		/* XXX remove once we switch to ip funcs */
++		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (!adev->mode_info.audio.enabled)
++		return;
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++)
++		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++
++	adev->mode_info.audio.enabled = false;
++}
++
++/*
++ * update the N and CTS parameters for a given pixel clock rate
++ */
++static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	u32 tmp;
++
++	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
++	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
++	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
++	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
++	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
++	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
++	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
++	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
++	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
++	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
++
++}
++
++/*
++ * build a HDMI Video Info Frame
++ */
++static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
++					       void *buffer, size_t size)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	uint8_t *frame = buffer + 3;
++	uint8_t *header = buffer;
++
++	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
++		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
++	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
++		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
++	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
++		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
++	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
++		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
++}
++
++static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++	u32 dto_phase = 24 * 1000;
++	u32 dto_modulo = clock;
++	u32 tmp;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* XXX two dtos; generally use dto0 for hdmi */
++	/* Express [24MHz / target pixel clock] as an exact rational
++	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
++	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
++	 */
++	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
++	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
++			    amdgpu_crtc->crtc_id);
++	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
++	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
++	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
++}
++
++/*
++ * update the info frames with the data from the current display mode
++ */
++static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
++				  struct drm_display_mode *mode)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
++	struct hdmi_avi_infoframe frame;
++	ssize_t err;
++	u32 tmp;
++	int bpc = 8;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* Silent, r600_hdmi_enable will raise WARN for us */
++	if (!dig->afmt->enabled)
++		return;
++
++	/* hdmi deep color mode general control packets setup, if bpc > 8 */
++	if (encoder->crtc) {
++		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
++		bpc = amdgpu_crtc->bpc;
++	}
++
++	/* disable audio prior to setting up hw */
++	dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
++	dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
++
++	dce_v11_0_audio_set_dto(encoder, mode->clock);
++
++	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
++	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
++
++	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
++
++	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
++	switch (bpc) {
++	case 0:
++	case 6:
++	case 8:
++	case 16:
++	default:
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
++		DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
++			  connector->name, bpc);
++		break;
++	case 10:
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
++		DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
++			  connector->name);
++		break;
++	case 12:
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
++		DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
++			  connector->name);
++		break;
++	}
++	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
++	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
++	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
++	/* enable audio info frames (frames won't be set until audio is enabled) */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
++	/* required for audio info values to be updated */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
++	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
++	/* required for audio info values to be updated */
++	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
++	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
++	/* anything other than 0 */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
++	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
++
++	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
++
++	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
++	/* set the default audio delay */
++	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
++	/* should be suffient for all audio modes and small enough for all hblanks */
++	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
++	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
++	/* allow 60958 channel status fields to be updated */
++	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
++	if (bpc > 8)
++		/* clear SW CTS value */
++		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
++	else
++		/* select SW CTS value */
++		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
++	/* allow hw to sent ACR packets when required */
++	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
++	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	dce_v11_0_afmt_update_ACR(encoder, mode->clock);
++
++	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
++	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
++	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
++	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
++	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
++
++	dce_v11_0_audio_write_speaker_allocation(encoder);
++
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
++	       (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
++
++	dce_v11_0_afmt_audio_select_pin(encoder);
++	dce_v11_0_audio_write_sad_regs(encoder);
++	dce_v11_0_audio_write_latency_fields(encoder, mode);
++
++	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
++	if (err < 0) {
++		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
++		return;
++	}
++
++	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
++	if (err < 0) {
++		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
++		return;
++	}
++
++	dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
++	/* enable AVI info frames */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
++	/* required for audio info values to be updated */
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
++	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
++	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
++	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
++
++	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
++	/* send audio packets */
++	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
++	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
++
++	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
++	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
++	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
++	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
++
++	/* enable audio after to setting up hw */
++	dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
++}
++
++static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++	if (!dig || !dig->afmt)
++		return;
++
++	/* Silent, r600_hdmi_enable will raise WARN for us */
++	if (enable && dig->afmt->enabled)
++		return;
++	if (!enable && !dig->afmt->enabled)
++		return;
++
++	if (!enable && dig->afmt->pin) {
++		dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
++		dig->afmt->pin = NULL;
++	}
++
++	dig->afmt->enabled = enable;
++
++	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
++		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
++}
++
++static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->mode_info.num_dig; i++)
++		adev->mode_info.afmt[i] = NULL;
++
++	/* DCE11 has audio blocks tied to DIG encoders */
++	for (i = 0; i < adev->mode_info.num_dig; i++) {
++		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
++		if (adev->mode_info.afmt[i]) {
++			adev->mode_info.afmt[i]->offset = dig_offsets[i];
++			adev->mode_info.afmt[i]->id = i;
++		}
++	}
++}
++
++static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->mode_info.num_dig; i++) {
++		kfree(adev->mode_info.afmt[i]);
++		adev->mode_info.afmt[i] = NULL;
++	}
++}
++
++static const u32 vga_control_regs[6] =
++{
++	mmD1VGA_CONTROL,
++	mmD2VGA_CONTROL,
++	mmD3VGA_CONTROL,
++	mmD4VGA_CONTROL,
++	mmD5VGA_CONTROL,
++	mmD6VGA_CONTROL,
++};
++
++static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u32 vga_control;
++
++	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
++	if (enable)
++		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
++	else
++		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
++}
++
++static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (enable)
++		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
++	else
++		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
++}
++
++static void dce_v11_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw,
++				   unsigned *bankh, unsigned *mtaspect,
++				   unsigned *tile_split)
++{
++	*bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK;
++	*bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK;
++	*mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
++	*tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK;
++	switch (*bankw) {
++	default:
++	case 1:
++		*bankw = ADDR_SURF_BANK_WIDTH_1;
++		break;
++	case 2:
++		*bankw = ADDR_SURF_BANK_WIDTH_2;
++		break;
++	case 4:
++		*bankw = ADDR_SURF_BANK_WIDTH_4;
++		break;
++	case 8:
++		*bankw = ADDR_SURF_BANK_WIDTH_8;
++		break;
++	}
++	switch (*bankh) {
++	default:
++	case 1:
++		*bankh = ADDR_SURF_BANK_HEIGHT_1;
++		break;
++	case 2:
++		*bankh = ADDR_SURF_BANK_HEIGHT_2;
++		break;
++	case 4:
++		*bankh = ADDR_SURF_BANK_HEIGHT_4;
++		break;
++	case 8:
++		*bankh = ADDR_SURF_BANK_HEIGHT_8;
++		break;
++	}
++	switch (*mtaspect) {
++	default:
++	case 1:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_1;
++		break;
++	case 2:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_2;
++		break;
++	case 4:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_4;
++		break;
++	case 8:
++		*mtaspect = ADDR_SURF_MACRO_ASPECT_8;
++		break;
++	}
++}
++
++static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
++				     struct drm_framebuffer *fb,
++				     int x, int y, int atomic)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_framebuffer *amdgpu_fb;
++	struct drm_framebuffer *target_fb;
++	struct drm_gem_object *obj;
++	struct amdgpu_bo *rbo;
++	uint64_t fb_location, tiling_flags;
++	uint32_t fb_format, fb_pitch_pixels;
++	unsigned bankw, bankh, mtaspect, tile_split;
++	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
++	/* XXX change to VI */
++	u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f;
++	u32 tmp, viewport_w, viewport_h;
++	int r;
++	bool bypass_lut = false;
++
++	/* no fb bound */
++	if (!atomic && !crtc->primary->fb) {
++		DRM_DEBUG_KMS("No FB bound\n");
++		return 0;
++	}
++
++	if (atomic) {
++		amdgpu_fb = to_amdgpu_framebuffer(fb);
++		target_fb = fb;
++	}
++	else {
++		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++		target_fb = crtc->primary->fb;
++	}
++
++	/* If atomic, assume fb object is pinned & idle & fenced and
++	 * just update base pointers
++	 */
++	obj = amdgpu_fb->obj;
++	rbo = gem_to_amdgpu_bo(obj);
++	r = amdgpu_bo_reserve(rbo, false);
++	if (unlikely(r != 0))
++		return r;
++
++	if (atomic)
++		fb_location = amdgpu_bo_gpu_offset(rbo);
++	else {
++		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
++		if (unlikely(r != 0)) {
++			amdgpu_bo_unreserve(rbo);
++			return -EINVAL;
++		}
++	}
++
++	amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
++	amdgpu_bo_unreserve(rbo);
++
++	switch (target_fb->pixel_format) {
++	case DRM_FORMAT_C8:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
++		break;
++	case DRM_FORMAT_XRGB4444:
++	case DRM_FORMAT_ARGB4444:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_XRGB1555:
++	case DRM_FORMAT_ARGB1555:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_BGRX5551:
++	case DRM_FORMAT_BGRA5551:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_RGB565:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN16);
++#endif
++		break;
++	case DRM_FORMAT_XRGB8888:
++	case DRM_FORMAT_ARGB8888:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN32);
++#endif
++		break;
++	case DRM_FORMAT_XRGB2101010:
++	case DRM_FORMAT_ARGB2101010:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN32);
++#endif
++		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
++		bypass_lut = true;
++		break;
++	case DRM_FORMAT_BGRX1010102:
++	case DRM_FORMAT_BGRA1010102:
++		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
++#ifdef __BIG_ENDIAN
++		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
++					ENDIAN_8IN32);
++#endif
++		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
++		bypass_lut = true;
++		break;
++	default:
++		DRM_ERROR("Unsupported screen format %s\n",
++			drm_get_format_name(target_fb->pixel_format));
++		return -EINVAL;
++	}
++
++	if (tiling_flags & AMDGPU_TILING_MACRO) {
++		unsigned tileb, index, num_banks, tile_split_bytes;
++
++		dce_v11_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
++		/* Set NUM_BANKS. */
++		/* Calculate the macrotile mode index. */
++		tile_split_bytes = 64 << tile_split;
++		tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
++		tileb = min(tile_split_bytes, tileb);
++
++		for (index = 0; tileb > 64; index++) {
++			tileb >>= 1;
++		}
++
++		if (index >= 16) {
++			DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
++				  target_fb->bits_per_pixel, tile_split);
++			return -EINVAL;
++		}
++
++		/* XXX fix me for VI */
++		num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3;
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
++					  ARRAY_2D_TILED_THIN1);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
++					  tile_split);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
++					  mtaspect);
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
++					  ADDR_SURF_MICRO_TILING_DISPLAY);
++	} else if (tiling_flags & AMDGPU_TILING_MICRO) {
++		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
++					  ARRAY_1D_TILED_THIN1);
++	}
++
++	/* Read the pipe config from the 2D TILED SCANOUT mode.
++	 * It should be the same for the other modes too, but not all
++	 * modes set the pipe config field. */
++	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
++				  pipe_config);
++
++	dce_v11_0_vga_enable(crtc, false);
++
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(fb_location));
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(fb_location));
++	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
++	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
++	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
++	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
++
++	/*
++	 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
++	 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
++	 * retain the full precision throughout the pipeline.
++	 */
++	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
++	if (bypass_lut)
++		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
++	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
++
++	if (bypass_lut)
++		DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
++
++	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
++	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
++
++	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
++
++	dce_v11_0_grph_enable(crtc, true);
++
++	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
++	       target_fb->height);
++
++	x &= ~3;
++	y &= ~1;
++	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
++	       (x << 16) | y);
++	viewport_w = crtc->mode.hdisplay;
++	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
++	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
++	       (viewport_w << 16) | viewport_h);
++
++	/* pageflip setup */
++	/* make sure flip is at vb rather than hb */
++	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
++			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
++	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	/* set pageflip to happen only at start of vblank interval (front porch) */
++	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
++
++	if (!atomic && fb && fb != crtc->primary->fb) {
++		amdgpu_fb = to_amdgpu_framebuffer(fb);
++		rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
++		r = amdgpu_bo_reserve(rbo, false);
++		if (unlikely(r != 0))
++			return r;
++		amdgpu_bo_unpin(rbo);
++		amdgpu_bo_unreserve(rbo);
++	}
++
++	/* Bytes per pixel may have changed */
++	dce_v11_0_bandwidth_update(adev);
++
++	return 0;
++}
++
++static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
++				     struct drm_display_mode *mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	u32 tmp;
++
++	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
++	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	int i;
++	u32 tmp;
++
++	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
++
++	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
++	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
++	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
++	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
++
++	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
++
++	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
++	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
++	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
++
++	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
++	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
++
++	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
++	for (i = 0; i < 256; i++) {
++		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
++		       (amdgpu_crtc->lut_r[i] << 20) |
++		       (amdgpu_crtc->lut_g[i] << 10) |
++		       (amdgpu_crtc->lut_b[i] << 0));
++	}
++
++	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
++	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
++	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
++	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
++	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
++	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++
++	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
++	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
++	/* XXX this only needs to be programmed once per crtc at startup,
++	 * not sure where the best place for it is
++	 */
++	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
++	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++		if (dig->linkb)
++			return 1;
++		else
++			return 0;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++		if (dig->linkb)
++			return 3;
++		else
++			return 2;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++		if (dig->linkb)
++			return 5;
++		else
++			return 4;
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		return 6;
++		break;
++	default:
++		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
++		return 0;
++	}
++}
++
++/**
++ * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
++ *
++ * @crtc: drm crtc
++ *
++ * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
++ * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
++ * monitors a dedicated PPLL must be used.  If a particular board has
++ * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
++ * as there is no need to program the PLL itself.  If we are not able to
++ * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
++ * avoid messing up an existing monitor.
++ *
++ * Asic specific PLL information
++ *
++ * DCE 10.x
++ * Tonga
++ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
++ * CI
++ * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
++ *
++ */
++static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	u32 pll_in_use;
++	int pll;
++
++	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
++		if (adev->clock.dp_extclk)
++			/* skip PPLL programming if using ext clock */
++			return ATOM_PPLL_INVALID;
++		else {
++			/* use the same PPLL for all DP monitors */
++			pll = amdgpu_pll_get_shared_dp_ppll(crtc);
++			if (pll != ATOM_PPLL_INVALID)
++				return pll;
++		}
++	} else {
++		/* use the same PPLL for all monitors with the same clock */
++		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
++		if (pll != ATOM_PPLL_INVALID)
++			return pll;
++	}
++
++	/* XXX need to determine what plls are available on each DCE11 part */
++	pll_in_use = amdgpu_pll_get_use_mask(crtc);
++	if (adev->asic_type == CHIP_CARRIZO) {
++		if (!(pll_in_use & (1 << ATOM_PPLL1)))
++			return ATOM_PPLL1;
++		if (!(pll_in_use & (1 << ATOM_PPLL0)))
++			return ATOM_PPLL0;
++		DRM_ERROR("unable to allocate a PPLL\n");
++		return ATOM_PPLL_INVALID;
++	} else {
++		if (!(pll_in_use & (1 << ATOM_PPLL2)))
++			return ATOM_PPLL2;
++		if (!(pll_in_use & (1 << ATOM_PPLL1)))
++			return ATOM_PPLL1;
++		if (!(pll_in_use & (1 << ATOM_PPLL0)))
++			return ATOM_PPLL0;
++		DRM_ERROR("unable to allocate a PPLL\n");
++		return ATOM_PPLL_INVALID;
++	}
++	return ATOM_PPLL_INVALID;
++}
++
++static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
++{
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	uint32_t cur_lock;
++
++	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
++	if (lock)
++		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
++	else
++		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
++	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
++}
++
++static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	u32 tmp;
++
++	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
++	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	u32 tmp;
++
++	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
++	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
++	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
++	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++}
++
++static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
++			      uint64_t gpu_addr)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++
++	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
++	       upper_32_bits(gpu_addr));
++	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
++	       lower_32_bits(gpu_addr));
++}
++
++static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
++				     int x, int y)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct amdgpu_device *adev = crtc->dev->dev_private;
++	int xorigin = 0, yorigin = 0;
++
++	/* avivo cursor are offset into the total surface */
++	x += crtc->x;
++	y += crtc->y;
++	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
++
++	if (x < 0) {
++		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
++		x = 0;
++	}
++	if (y < 0) {
++		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
++		y = 0;
++	}
++
++	dce_v11_0_lock_cursor(crtc, true);
++	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
++	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
++	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
++	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
++	dce_v11_0_lock_cursor(crtc, false);
++
++	return 0;
++}
++
++static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc,
++				    struct drm_file *file_priv,
++				    uint32_t handle,
++				    uint32_t width,
++				    uint32_t height)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_gem_object *obj;
++	struct amdgpu_bo *robj;
++	uint64_t gpu_addr;
++	int ret;
++
++	if (!handle) {
++		/* turn off cursor */
++		dce_v11_0_hide_cursor(crtc);
++		obj = NULL;
++		goto unpin;
++	}
++
++	if ((width > amdgpu_crtc->max_cursor_width) ||
++	    (height > amdgpu_crtc->max_cursor_height)) {
++		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
++		return -EINVAL;
++	}
++
++	obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
++	if (!obj) {
++		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
++		return -ENOENT;
++	}
++
++	robj = gem_to_amdgpu_bo(obj);
++	ret = amdgpu_bo_reserve(robj, false);
++	if (unlikely(ret != 0))
++		goto fail;
++	ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
++				       0, &gpu_addr);
++	amdgpu_bo_unreserve(robj);
++	if (ret)
++		goto fail;
++
++	amdgpu_crtc->cursor_width = width;
++	amdgpu_crtc->cursor_height = height;
++
++	dce_v11_0_lock_cursor(crtc, true);
++	dce_v11_0_set_cursor(crtc, obj, gpu_addr);
++	dce_v11_0_show_cursor(crtc);
++	dce_v11_0_lock_cursor(crtc, false);
++
++unpin:
++	if (amdgpu_crtc->cursor_bo) {
++		robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
++		ret = amdgpu_bo_reserve(robj, false);
++		if (likely(ret == 0)) {
++			amdgpu_bo_unpin(robj);
++			amdgpu_bo_unreserve(robj);
++		}
++		drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
++	}
++
++	amdgpu_crtc->cursor_bo = obj;
++	return 0;
++fail:
++	drm_gem_object_unreference_unlocked(obj);
++
++	return ret;
++}
++
++static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
++				    u16 *blue, uint32_t start, uint32_t size)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	int end = (start + size > 256) ? 256 : start + size, i;
++
++	/* userspace palettes are always correct as is */
++	for (i = start; i < end; i++) {
++		amdgpu_crtc->lut_r[i] = red[i] >> 6;
++		amdgpu_crtc->lut_g[i] = green[i] >> 6;
++		amdgpu_crtc->lut_b[i] = blue[i] >> 6;
++	}
++	dce_v11_0_crtc_load_lut(crtc);
++}
++
++static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	drm_crtc_cleanup(crtc);
++	destroy_workqueue(amdgpu_crtc->pflip_queue);
++	kfree(amdgpu_crtc);
++}
++
++static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
++	.cursor_set = dce_v11_0_crtc_cursor_set,
++	.cursor_move = dce_v11_0_crtc_cursor_move,
++	.gamma_set = dce_v11_0_crtc_gamma_set,
++	.set_config = amdgpu_crtc_set_config,
++	.destroy = dce_v11_0_crtc_destroy,
++	.page_flip = amdgpu_crtc_page_flip,
++};
++
++static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
++{
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	switch (mode) {
++	case DRM_MODE_DPMS_ON:
++		amdgpu_crtc->enabled = true;
++		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
++		dce_v11_0_vga_enable(crtc, true);
++		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
++		dce_v11_0_vga_enable(crtc, false);
++		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
++		dce_v11_0_crtc_load_lut(crtc);
++		break;
++	case DRM_MODE_DPMS_STANDBY:
++	case DRM_MODE_DPMS_SUSPEND:
++	case DRM_MODE_DPMS_OFF:
++		drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
++		if (amdgpu_crtc->enabled) {
++			dce_v11_0_vga_enable(crtc, true);
++			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
++			dce_v11_0_vga_enable(crtc, false);
++		}
++		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
++		amdgpu_crtc->enabled = false;
++		break;
++	}
++	/* adjust pm to dpms */
++	amdgpu_pm_compute_clocks(adev);
++}
++
++static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
++{
++	/* disable crtc pair power gating before programming */
++	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
++	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
++	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++}
++
++static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
++{
++	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
++	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
++}
++
++static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_atom_ss ss;
++	int i;
++
++	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++	if (crtc->primary->fb) {
++		int r;
++		struct amdgpu_framebuffer *amdgpu_fb;
++		struct amdgpu_bo *rbo;
++
++		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
++		rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
++		r = amdgpu_bo_reserve(rbo, false);
++		if (unlikely(r))
++			DRM_ERROR("failed to reserve rbo before unpin\n");
++		else {
++			amdgpu_bo_unpin(rbo);
++			amdgpu_bo_unreserve(rbo);
++		}
++	}
++	/* disable the GRPH */
++	dce_v11_0_grph_enable(crtc, false);
++
++	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		if (adev->mode_info.crtcs[i] &&
++		    adev->mode_info.crtcs[i]->enabled &&
++		    i != amdgpu_crtc->crtc_id &&
++		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
++			/* one other crtc is using this pll don't turn
++			 * off the pll
++			 */
++			goto done;
++		}
++	}
++
++	switch (amdgpu_crtc->pll_id) {
++	case ATOM_PPLL0:
++	case ATOM_PPLL1:
++	case ATOM_PPLL2:
++		/* disable the ppll */
++		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
++					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
++		break;
++	default:
++		break;
++	}
++done:
++	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
++	amdgpu_crtc->adjusted_clock = 0;
++	amdgpu_crtc->encoder = NULL;
++	amdgpu_crtc->connector = NULL;
++}
++
++static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
++				  struct drm_display_mode *mode,
++				  struct drm_display_mode *adjusted_mode,
++				  int x, int y, struct drm_framebuffer *old_fb)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++
++	if (!amdgpu_crtc->adjusted_clock)
++		return -EINVAL;
++
++	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
++	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
++	dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
++	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
++	amdgpu_atombios_crtc_scaler_setup(crtc);
++	/* update the hw version fpr dpm */
++	amdgpu_crtc->hw_mode = *adjusted_mode;
++
++	return 0;
++}
++
++static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
++				     const struct drm_display_mode *mode,
++				     struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
++	struct drm_device *dev = crtc->dev;
++	struct drm_encoder *encoder;
++
++	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		if (encoder->crtc == crtc) {
++			amdgpu_crtc->encoder = encoder;
++			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
++			break;
++		}
++	}
++	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
++		amdgpu_crtc->encoder = NULL;
++		amdgpu_crtc->connector = NULL;
++		return false;
++	}
++	if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
++		return false;
++	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
++		return false;
++	/* pick pll */
++	amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
++	/* if we can't get a PPLL for a non-DP encoder, fail */
++	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
++	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
++		return false;
++
++	return true;
++}
++
++static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
++				  struct drm_framebuffer *old_fb)
++{
++	return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
++}
++
++static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
++					 struct drm_framebuffer *fb,
++					 int x, int y, enum mode_set_atomic state)
++{
++       return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
++}
++
++static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
++	.dpms = dce_v11_0_crtc_dpms,
++	.mode_fixup = dce_v11_0_crtc_mode_fixup,
++	.mode_set = dce_v11_0_crtc_mode_set,
++	.mode_set_base = dce_v11_0_crtc_set_base,
++	.mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
++	.prepare = dce_v11_0_crtc_prepare,
++	.commit = dce_v11_0_crtc_commit,
++	.load_lut = dce_v11_0_crtc_load_lut,
++	.disable = dce_v11_0_crtc_disable,
++};
++
++static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
++{
++	struct amdgpu_crtc *amdgpu_crtc;
++	int i;
++
++	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
++			      (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
++	if (amdgpu_crtc == NULL)
++		return -ENOMEM;
++
++	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
++
++	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
++	amdgpu_crtc->crtc_id = index;
++	amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
++	adev->mode_info.crtcs[index] = amdgpu_crtc;
++
++	amdgpu_crtc->max_cursor_width = 128;
++	amdgpu_crtc->max_cursor_height = 128;
++	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
++	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
++
++	for (i = 0; i < 256; i++) {
++		amdgpu_crtc->lut_r[i] = i << 2;
++		amdgpu_crtc->lut_g[i] = i << 2;
++		amdgpu_crtc->lut_b[i] = i << 2;
++	}
++
++	switch (amdgpu_crtc->crtc_id) {
++	case 0:
++	default:
++		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
++		break;
++	case 1:
++		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
++		break;
++	case 2:
++		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
++		break;
++	case 3:
++		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
++		break;
++	case 4:
++		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
++		break;
++	case 5:
++		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
++		break;
++	}
++
++	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
++	amdgpu_crtc->adjusted_clock = 0;
++	amdgpu_crtc->encoder = NULL;
++	amdgpu_crtc->connector = NULL;
++	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
++
++	return 0;
++}
++
++static int dce_v11_0_early_init(struct amdgpu_device *adev)
++{
++	adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
++	adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
++
++	dce_v11_0_set_display_funcs(adev);
++	dce_v11_0_set_irq_funcs(adev);
++
++	switch (adev->asic_type) {
++	case CHIP_CARRIZO:
++		adev->mode_info.num_crtc = 4;
++		adev->mode_info.num_hpd = 6;
++		adev->mode_info.num_dig = 9;
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int dce_v11_0_sw_init(struct amdgpu_device *adev)
++{
++	int r, i;
++
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
++		if (r)
++		return r;
++	}
++
++	for (i = 8; i < 20; i += 2) {
++		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
++		if (r)
++			return r;
++	}
++
++	/* HPD hotplug */
++	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
++	if (r)
++	return r;
++
++	adev->mode_info.mode_config_initialized = true;
++
++	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
++
++	adev->ddev->mode_config.max_width = 16384;
++	adev->ddev->mode_config.max_height = 16384;
++
++	adev->ddev->mode_config.preferred_depth = 24;
++	adev->ddev->mode_config.prefer_shadow = 1;
++
++	adev->ddev->mode_config.fb_base = adev->mc.aper_base;
++
++	r = amdgpu_modeset_create_props(adev);
++	if (r)
++		return r;
++
++	adev->ddev->mode_config.max_width = 16384;
++	adev->ddev->mode_config.max_height = 16384;
++
++	/* allocate crtcs */
++	for (i = 0; i < adev->mode_info.num_crtc; i++) {
++		r = dce_v11_0_crtc_init(adev, i);
++		if (r)
++			return r;
++	}
++
++	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
++		amdgpu_print_display_setup(adev->ddev);
++	else
++		return -EINVAL;
++
++	/* setup afmt */
++	dce_v11_0_afmt_init(adev);
++
++	r = dce_v11_0_audio_init(adev);
++	if (r)
++		return r;
++
++	drm_kms_helper_poll_init(adev->ddev);
++
++	return r;
++}
++
++static int dce_v11_0_sw_fini(struct amdgpu_device *adev)
++{
++	kfree(adev->mode_info.bios_hardcoded_edid);
++
++	drm_kms_helper_poll_fini(adev->ddev);
++
++	dce_v11_0_audio_fini(adev);
++
++	dce_v11_0_afmt_fini(adev);
++
++	adev->mode_info.mode_config_initialized = false;
++
++	return 0;
++}
++
++static int dce_v11_0_hw_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v11_0_init_golden_registers(adev);
++
++	/* init dig PHYs, disp eng pll */
++	amdgpu_atombios_encoder_init_dig(adev);
++	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
++
++	/* initialize hpd */
++	dce_v11_0_hpd_init(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static int dce_v11_0_hw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	dce_v11_0_hpd_fini(adev);
++
++	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
++		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++	}
++
++	return 0;
++}
++
++static int dce_v11_0_suspend(struct amdgpu_device *adev)
++{
++	struct drm_connector *connector;
++
++	drm_kms_helper_poll_disable(adev->ddev);
++
++	/* turn off display hw */
++	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
++	}
++
++	amdgpu_atombios_scratch_regs_save(adev);
++
++	dce_v11_0_hpd_fini(adev);
++
++	return 0;
++}
++
++static int dce_v11_0_resume(struct amdgpu_device *adev)
++{
++	struct drm_connector *connector;
++
++	dce_v11_0_init_golden_registers(adev);
++
++	amdgpu_atombios_scratch_regs_restore(adev);
++
++	/* init dig PHYs, disp eng pll */
++	amdgpu_atombios_crtc_powergate_init(adev);
++	amdgpu_atombios_encoder_init_dig(adev);
++	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
++	/* turn on the BL */
++	if (adev->mode_info.bl_encoder) {
++		u8 bl_level = amdgpu_display_backlight_get_level(adev,
++								  adev->mode_info.bl_encoder);
++		amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
++						    bl_level);
++	}
++
++	/* initialize hpd */
++	dce_v11_0_hpd_init(adev);
++
++	/* blat the mode back in */
++	drm_helper_resume_force_mode(adev->ddev);
++	/* turn on display hw */
++	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) {
++		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
++	}
++
++	drm_kms_helper_poll_enable(adev->ddev);
++
++	return 0;
++}
++
++static bool dce_v11_0_is_idle(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return true;
++}
++
++static int dce_v11_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return 0;
++}
++
++static void dce_v11_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "DCE 10.x registers\n");
++	/* XXX todo */
++}
++
++static int dce_v11_0_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0, tmp;
++
++	if (dce_v11_0_is_display_hung(adev))
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
++
++	if (srbm_soft_reset) {
++		dce_v11_0_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++		dce_v11_0_print_status(adev);
++	}
++	return 0;
++}
++
++static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
++						     int crtc,
++						     enum amdgpu_interrupt_state state)
++{
++	u32 lb_interrupt_mask;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VBLANK_INTERRUPT_MASK, 0);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VBLANK_INTERRUPT_MASK, 1);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	default:
++		break;
++	}
++}
++
++static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
++						    int crtc,
++						    enum amdgpu_interrupt_state state)
++{
++	u32 lb_interrupt_mask;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VLINE_INTERRUPT_MASK, 0);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
++		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
++						  VLINE_INTERRUPT_MASK, 1);
++		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
++		break;
++	default:
++		break;
++	}
++}
++
++static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned hpd,
++					enum amdgpu_interrupt_state state)
++{
++	u32 tmp;
++
++	if (hpd >= adev->mode_info.num_hpd) {
++		DRM_DEBUG("invalid hdp %d\n", hpd);
++		return 0;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
++		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
++		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
++		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	switch (type) {
++	case AMDGPU_CRTC_IRQ_VBLANK1:
++		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK2:
++		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK3:
++		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK4:
++		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK5:
++		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VBLANK6:
++		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE1:
++		dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE2:
++		dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE3:
++		dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE4:
++		dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
++		break;
++	case AMDGPU_CRTC_IRQ_VLINE5:
++		dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
++		break;
++	 case AMDGPU_CRTC_IRQ_VLINE6:
++		dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
++					    struct amdgpu_irq_src *src,
++					    unsigned type,
++					    enum amdgpu_interrupt_state state)
++{
++	u32 reg, reg_block;
++	/* now deal with page flip IRQ */
++	switch (type) {
++		case AMDGPU_PAGEFLIP_IRQ_D1:
++			reg_block = CRTC0_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D2:
++			reg_block = CRTC1_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D3:
++			reg_block = CRTC2_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D4:
++			reg_block = CRTC3_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D5:
++			reg_block = CRTC4_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D6:
++			reg_block = CRTC5_REGISTER_OFFSET;
++			break;
++		default:
++			DRM_ERROR("invalid pageflip crtc %d\n", type);
++			return -EINVAL;
++	}
++
++	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
++	if (state == AMDGPU_IRQ_STATE_DISABLE)
++		WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
++	else
++		WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
++
++	return 0;
++}
++
++static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
++				  struct amdgpu_irq_src *source,
++				  struct amdgpu_iv_entry *entry)
++{
++	int reg_block;
++	unsigned long flags;
++	unsigned crtc_id;
++	struct amdgpu_crtc *amdgpu_crtc;
++	struct amdgpu_flip_work *works;
++
++	crtc_id = (entry->src_id - 8) >> 1;
++	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++
++	/* ack the interrupt */
++	switch(crtc_id){
++		case AMDGPU_PAGEFLIP_IRQ_D1:
++			reg_block = CRTC0_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D2:
++			reg_block = CRTC1_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D3:
++			reg_block = CRTC2_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D4:
++			reg_block = CRTC3_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D5:
++			reg_block = CRTC4_REGISTER_OFFSET;
++			break;
++		case AMDGPU_PAGEFLIP_IRQ_D6:
++			reg_block = CRTC5_REGISTER_OFFSET;
++			break;
++		default:
++			DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
++			return -EINVAL;
++	}
++
++	if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
++		WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
++
++	/* IRQ could occur when in initial stage */
++	if(amdgpu_crtc == NULL)
++		return 0;
++
++	spin_lock_irqsave(&adev->ddev->event_lock, flags);
++	works = amdgpu_crtc->pflip_works;
++	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
++		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
++						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
++						 amdgpu_crtc->pflip_status,
++						 AMDGPU_FLIP_SUBMITTED);
++		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++		return 0;
++	}
++
++	/* page flip completed. clean up */
++	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
++	amdgpu_crtc->pflip_works = NULL;
++
++	/* wakeup usersapce */
++	if(works->event)
++		drm_send_vblank_event(adev->ddev, crtc_id, works->event);
++
++	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++
++	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
++	amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
++	queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
++
++	return 0;
++}
++
++static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
++				  int hpd)
++{
++	u32 tmp;
++
++	if (hpd >= adev->mode_info.num_hpd) {
++		DRM_DEBUG("invalid hdp %d\n", hpd);
++		return;
++	}
++
++	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
++	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
++	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
++}
++
++static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
++					  int crtc)
++{
++	u32 tmp;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
++	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
++	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
++}
++
++static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
++					 int crtc)
++{
++	u32 tmp;
++
++	if (crtc >= adev->mode_info.num_crtc) {
++		DRM_DEBUG("invalid crtc %d\n", crtc);
++		return;
++	}
++
++	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
++	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
++	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
++}
++
++static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
++				struct amdgpu_irq_src *source,
++				struct amdgpu_iv_entry *entry)
++{
++	unsigned crtc = entry->src_id - 1;
++	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
++	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
++
++	switch (entry->src_data) {
++	case 0: /* vblank */
++		if (disp_int & interrupt_status_offsets[crtc].vblank) {
++			dce_v11_0_crtc_vblank_int_ack(adev, crtc);
++			if (amdgpu_irq_enabled(adev, source, irq_type)) {
++				drm_handle_vblank(adev->ddev, crtc);
++			}
++			DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
++		}
++		break;
++	case 1: /* vline */
++		if (disp_int & interrupt_status_offsets[crtc].vline) {
++			dce_v11_0_crtc_vline_int_ack(adev, crtc);
++			DRM_DEBUG("IH: D%d vline\n", crtc + 1);
++		}
++		break;
++	default:
++		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
++		break;
++	}
++
++	return 0;
++}
++
++static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
++			     struct amdgpu_irq_src *source,
++			     struct amdgpu_iv_entry *entry)
++{
++	uint32_t disp_int, mask;
++	unsigned hpd;
++
++	if (entry->src_data >= adev->mode_info.num_hpd) {
++		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
++		return 0;
++	}
++
++	hpd = entry->src_data;
++	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
++	mask = interrupt_status_offsets[hpd].hpd;
++
++	if (disp_int & mask) {
++		dce_v11_0_hpd_int_ack(adev, hpd);
++		schedule_work(&adev->hotplug_work);
++		DRM_DEBUG("IH: HPD%d\n", hpd + 1);
++	}
++
++	return 0;
++}
++
++static int dce_v11_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int dce_v11_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs dce_v11_0_ip_funcs = {
++	.early_init = dce_v11_0_early_init,
++	.late_init = NULL,
++	.sw_init = dce_v11_0_sw_init,
++	.sw_fini = dce_v11_0_sw_fini,
++	.hw_init = dce_v11_0_hw_init,
++	.hw_fini = dce_v11_0_hw_fini,
++	.suspend = dce_v11_0_suspend,
++	.resume = dce_v11_0_resume,
++	.is_idle = dce_v11_0_is_idle,
++	.wait_for_idle = dce_v11_0_wait_for_idle,
++	.soft_reset = dce_v11_0_soft_reset,
++	.print_status = dce_v11_0_print_status,
++	.set_clockgating_state = dce_v11_0_set_clockgating_state,
++	.set_powergating_state = dce_v11_0_set_powergating_state,
++};
++
++static void
++dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
++			  struct drm_display_mode *mode,
++			  struct drm_display_mode *adjusted_mode)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++
++	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
++
++	/* need to call this here rather than in prepare() since we need some crtc info */
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++
++	/* set scaler clears this on some chips */
++	dce_v11_0_set_interleave(encoder->crtc, mode);
++
++	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
++		dce_v11_0_afmt_enable(encoder, true);
++		dce_v11_0_afmt_setmode(encoder, adjusted_mode);
++	}
++}
++
++static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
++{
++	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
++
++	if ((amdgpu_encoder->active_device &
++	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
++	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
++	     ENCODER_OBJECT_ID_NONE)) {
++		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
++		if (dig) {
++			dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
++			if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
++				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
++		}
++	}
++
++	amdgpu_atombios_scratch_regs_lock(adev, true);
++
++	if (connector) {
++		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++
++		/* select the clock/data port if it uses a router */
++		if (amdgpu_connector->router.cd_valid)
++			amdgpu_i2c_router_select_cd_port(amdgpu_connector);
++
++		/* turn eDP panel on for mode set */
++		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
++			amdgpu_atombios_encoder_set_edp_panel_power(connector,
++							     ATOM_TRANSMITTER_ACTION_POWER_ON);
++	}
++
++	/* this is needed for the pll/ss setup to work correctly in some cases */
++	amdgpu_atombios_encoder_set_crtc_source(encoder);
++	/* set up the FMT blocks */
++	dce_v11_0_program_fmt(encoder);
++}
++
++static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
++{
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	/* need to call this here as we need the crtc set up */
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
++	amdgpu_atombios_scratch_regs_lock(adev, false);
++}
++
++static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	struct amdgpu_encoder_atom_dig *dig;
++
++	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++
++	if (amdgpu_atombios_encoder_is_digital(encoder)) {
++		if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
++			dce_v11_0_afmt_enable(encoder, false);
++		dig = amdgpu_encoder->enc_priv;
++		dig->dig_encoder = -1;
++	}
++	amdgpu_encoder->active_device = 0;
++}
++
++/* these are handled by the primary encoders */
++static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
++{
++
++}
++
++static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
++{
++
++}
++
++static void
++dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
++		      struct drm_display_mode *mode,
++		      struct drm_display_mode *adjusted_mode)
++{
++
++}
++
++static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
++{
++
++}
++
++static void
++dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
++{
++
++}
++
++static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
++				    const struct drm_display_mode *mode,
++				    struct drm_display_mode *adjusted_mode)
++{
++	return true;
++}
++
++static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
++	.dpms = dce_v11_0_ext_dpms,
++	.mode_fixup = dce_v11_0_ext_mode_fixup,
++	.prepare = dce_v11_0_ext_prepare,
++	.mode_set = dce_v11_0_ext_mode_set,
++	.commit = dce_v11_0_ext_commit,
++	.disable = dce_v11_0_ext_disable,
++	/* no detect for TMDS/LVDS yet */
++};
++
++static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
++	.dpms = amdgpu_atombios_encoder_dpms,
++	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
++	.prepare = dce_v11_0_encoder_prepare,
++	.mode_set = dce_v11_0_encoder_mode_set,
++	.commit = dce_v11_0_encoder_commit,
++	.disable = dce_v11_0_encoder_disable,
++	.detect = amdgpu_atombios_encoder_dig_detect,
++};
++
++static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
++	.dpms = amdgpu_atombios_encoder_dpms,
++	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
++	.prepare = dce_v11_0_encoder_prepare,
++	.mode_set = dce_v11_0_encoder_mode_set,
++	.commit = dce_v11_0_encoder_commit,
++	.detect = amdgpu_atombios_encoder_dac_detect,
++};
++
++static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
++{
++	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
++	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++		amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
++	kfree(amdgpu_encoder->enc_priv);
++	drm_encoder_cleanup(encoder);
++	kfree(amdgpu_encoder);
++}
++
++static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
++	.destroy = dce_v11_0_encoder_destroy,
++};
++
++static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
++				 uint32_t encoder_enum,
++				 uint32_t supported_device,
++				 u16 caps)
++{
++	struct drm_device *dev = adev->ddev;
++	struct drm_encoder *encoder;
++	struct amdgpu_encoder *amdgpu_encoder;
++
++	/* see if we already added it */
++	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
++		amdgpu_encoder = to_amdgpu_encoder(encoder);
++		if (amdgpu_encoder->encoder_enum == encoder_enum) {
++			amdgpu_encoder->devices |= supported_device;
++			return;
++		}
++
++	}
++
++	/* add a new one */
++	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
++	if (!amdgpu_encoder)
++		return;
++
++	encoder = &amdgpu_encoder->base;
++	switch (adev->mode_info.num_crtc) {
++	case 1:
++		encoder->possible_crtcs = 0x1;
++		break;
++	case 2:
++	default:
++		encoder->possible_crtcs = 0x3;
++		break;
++	case 4:
++		encoder->possible_crtcs = 0xf;
++		break;
++	case 6:
++		encoder->possible_crtcs = 0x3f;
++		break;
++	}
++
++	amdgpu_encoder->enc_priv = NULL;
++
++	amdgpu_encoder->encoder_enum = encoder_enum;
++	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
++	amdgpu_encoder->devices = supported_device;
++	amdgpu_encoder->rmx_type = RMX_OFF;
++	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
++	amdgpu_encoder->is_ext_encoder = false;
++	amdgpu_encoder->caps = caps;
++
++	switch (amdgpu_encoder->encoder_id) {
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
++		drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++				 DRM_MODE_ENCODER_DAC);
++		drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
++		break;
++	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
++	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++			amdgpu_encoder->rmx_type = RMX_FULL;
++			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++					 DRM_MODE_ENCODER_LVDS);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
++		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
++			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++					 DRM_MODE_ENCODER_DAC);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
++		} else {
++			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++					 DRM_MODE_ENCODER_TMDS);
++			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
++		}
++		drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
++		break;
++	case ENCODER_OBJECT_ID_SI170B:
++	case ENCODER_OBJECT_ID_CH7303:
++	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
++	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
++	case ENCODER_OBJECT_ID_TITFP513:
++	case ENCODER_OBJECT_ID_VT1623:
++	case ENCODER_OBJECT_ID_HDMI_SI1930:
++	case ENCODER_OBJECT_ID_TRAVIS:
++	case ENCODER_OBJECT_ID_NUTMEG:
++		/* these are handled by the primary encoders */
++		amdgpu_encoder->is_ext_encoder = true;
++		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++					 DRM_MODE_ENCODER_LVDS);
++		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
++			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++					 DRM_MODE_ENCODER_DAC);
++		else
++			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
++					 DRM_MODE_ENCODER_TMDS);
++		drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
++		break;
++	}
++}
++
++static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
++	.set_vga_render_state = &dce_v11_0_set_vga_render_state,
++	.bandwidth_update = &dce_v11_0_bandwidth_update,
++	.vblank_get_counter = &dce_v11_0_vblank_get_counter,
++	.vblank_wait = &dce_v11_0_vblank_wait,
++	.is_display_hung = &dce_v11_0_is_display_hung,
++	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
++	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
++	.hpd_sense = &dce_v11_0_hpd_sense,
++	.hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
++	.hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
++	.page_flip = &dce_v11_0_page_flip,
++	.page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
++	.add_encoder = &dce_v11_0_encoder_add,
++	.add_connector = &amdgpu_connector_add,
++	.stop_mc_access = &dce_v11_0_stop_mc_access,
++	.resume_mc_access = &dce_v11_0_resume_mc_access,
++};
++
++static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
++{
++	if (adev->mode_info.funcs == NULL)
++		adev->mode_info.funcs = &dce_v11_0_display_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
++	.set = dce_v11_0_set_crtc_irq_state,
++	.process = dce_v11_0_crtc_irq,
++};
++
++static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
++	.set = dce_v11_0_set_pageflip_irq_state,
++	.process = dce_v11_0_pageflip_irq,
++};
++
++static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
++	.set = dce_v11_0_set_hpd_irq_state,
++	.process = dce_v11_0_hpd_irq,
++};
++
++static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
++	adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
++
++	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
++	adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
++
++	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
++	adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
+new file mode 100644
+index 0000000..eeb9a56
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __DCE_V11_0_H__
++#define __DCE_V11_0_H__
++
++extern const struct amdgpu_ip_funcs dce_v11_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+new file mode 100644
+index 0000000..a8397dd
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -0,0 +1,4286 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_gfx.h"
++#include "vi.h"
++#include "vid.h"
++#include "amdgpu_ucode.h"
++#include "clearstate_vi.h"
++
++#include "gmc/gmc_8_2_d.h"
++#include "gmc/gmc_8_2_sh_mask.h"
++
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "gca/gfx_8_0_d.h"
++#include "gca/gfx_8_0_enum.h"
++#include "gca/gfx_8_0_sh_mask.h"
++#include "gca/gfx_8_0_enum.h"
++
++#include "uvd/uvd_5_0_d.h"
++#include "uvd/uvd_5_0_sh_mask.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++
++#define GFX8_NUM_GFX_RINGS     1
++#define GFX8_NUM_COMPUTE_RINGS 8
++
++#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
++#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
++#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
++
++#define ARRAY_MODE(x)					((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
++#define PIPE_CONFIG(x)					((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
++#define TILE_SPLIT(x)					((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
++#define MICRO_TILE_MODE_NEW(x)				((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
++#define SAMPLE_SPLIT(x)					((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
++#define BANK_WIDTH(x)					((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
++#define BANK_HEIGHT(x)					((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
++#define MACRO_TILE_ASPECT(x)				((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
++#define NUM_BANKS(x)					((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
++
++MODULE_FIRMWARE("radeon/carrizo_ce.bin");
++MODULE_FIRMWARE("radeon/carrizo_pfp.bin");
++MODULE_FIRMWARE("radeon/carrizo_me.bin");
++MODULE_FIRMWARE("radeon/carrizo_mec.bin");
++MODULE_FIRMWARE("radeon/carrizo_mec2.bin");
++MODULE_FIRMWARE("radeon/carrizo_rlc.bin");
++
++MODULE_FIRMWARE("radeon/tonga_ce.bin");
++MODULE_FIRMWARE("radeon/tonga_pfp.bin");
++MODULE_FIRMWARE("radeon/tonga_me.bin");
++MODULE_FIRMWARE("radeon/tonga_mec.bin");
++MODULE_FIRMWARE("radeon/tonga_mec2.bin");
++MODULE_FIRMWARE("radeon/tonga_rlc.bin");
++
++MODULE_FIRMWARE("radeon/topaz_ce.bin");
++MODULE_FIRMWARE("radeon/topaz_pfp.bin");
++MODULE_FIRMWARE("radeon/topaz_me.bin");
++MODULE_FIRMWARE("radeon/topaz_mec.bin");
++MODULE_FIRMWARE("radeon/topaz_mec2.bin");
++MODULE_FIRMWARE("radeon/topaz_rlc.bin");
++
++static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
++{
++	{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
++	{mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
++	{mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
++	{mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
++	{mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
++	{mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
++	{mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
++	{mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
++	{mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
++	{mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
++	{mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
++	{mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
++	{mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
++	{mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
++	{mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
++	{mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
++};
++
++static const u32 golden_settings_tonga_a11[] =
++{
++	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
++	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
++	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
++	mmGB_GPU_ID, 0x0000000f, 0x00000000,
++	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
++	mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
++	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
++	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
++	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
++	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
++	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
++	mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
++};
++
++static const u32 tonga_golden_common_all[] =
++{
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
++	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
++	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
++	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
++	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
++	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
++	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
++};
++
++static const u32 tonga_mgcg_cgcg_init[] =
++{
++	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
++	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
++	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
++	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
++	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
++	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
++	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
++	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
++};
++
++static const u32 golden_settings_iceland_a11[] =
++{
++	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
++	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
++	mmDB_DEBUG3, 0xc0000000, 0xc0000000,
++	mmGB_GPU_ID, 0x0000000f, 0x00000000,
++	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
++	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
++	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
++	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
++	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
++	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
++	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
++	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
++	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
++};
++
++static const u32 iceland_golden_common_all[] =
++{
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
++	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
++	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
++	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
++	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
++	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
++	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
++};
++
++static const u32 iceland_mgcg_cgcg_init[] =
++{
++	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
++	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
++	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
++	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
++	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
++	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
++	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
++	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
++	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
++	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
++	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
++	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
++};
++
++static const u32 cz_golden_settings_a11[] =
++{
++	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
++	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
++	mmGB_GPU_ID, 0x0000000f, 0x00000000,
++	mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
++	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
++	mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
++	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
++	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
++};
++
++static const u32 cz_golden_common_all[] =
++{
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
++	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
++	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
++	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
++	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
++	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
++	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
++};
++
++static const u32 cz_mgcg_cgcg_init[] =
++{
++	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
++	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
++	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
++	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
++	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
++	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
++	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
++	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
++	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
++	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
++	mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
++	mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
++	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
++	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
++	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
++	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
++	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
++};
++
++static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
++static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
++static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
++
++static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		amdgpu_program_register_sequence(adev,
++						 iceland_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_iceland_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
++		amdgpu_program_register_sequence(adev,
++						 iceland_golden_common_all,
++						 (const u32)ARRAY_SIZE(iceland_golden_common_all));
++		break;
++	case CHIP_TONGA:
++		amdgpu_program_register_sequence(adev,
++						 tonga_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_tonga_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
++		amdgpu_program_register_sequence(adev,
++						 tonga_golden_common_all,
++						 (const u32)ARRAY_SIZE(tonga_golden_common_all));
++		break;
++	case CHIP_CARRIZO:
++		amdgpu_program_register_sequence(adev,
++						 cz_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 cz_golden_settings_a11,
++						 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
++		amdgpu_program_register_sequence(adev,
++						 cz_golden_common_all,
++						 (const u32)ARRAY_SIZE(cz_golden_common_all));
++		break;
++	default:
++		break;
++	}
++}
++
++static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
++{
++	int i;
++
++	adev->gfx.scratch.num_reg = 7;
++	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
++	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
++		adev->gfx.scratch.free[i] = true;
++		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
++	}
++}
++
++static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t scratch;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	r = amdgpu_gfx_scratch_get(adev, &scratch);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
++		return r;
++	}
++	WREG32(scratch, 0xCAFEDEAD);
++	r = amdgpu_ring_lock(ring, 3);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
++			  ring->idx, r);
++		amdgpu_gfx_scratch_free(adev, scratch);
++		return r;
++	}
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
++	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(scratch);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n",
++			 ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
++			  ring->idx, scratch, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_gfx_scratch_free(adev, scratch);
++	return r;
++}
++
++static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_ib ib;
++	uint32_t scratch;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	r = amdgpu_gfx_scratch_get(adev, &scratch);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
++		return r;
++	}
++	WREG32(scratch, 0xCAFEDEAD);
++	r = amdgpu_ib_get(ring, NULL, 256, &ib);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		amdgpu_gfx_scratch_free(adev, scratch);
++		return r;
++	}
++	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
++	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
++	ib.ptr[2] = 0xDEADBEEF;
++	ib.length_dw = 3;
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		amdgpu_gfx_scratch_free(adev, scratch);
++		amdgpu_ib_free(adev, &ib);
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++		return r;
++	}
++	r = amdgpu_fence_wait(ib.fence, false);
++	if (r) {
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		amdgpu_gfx_scratch_free(adev, scratch);
++		amdgpu_ib_free(adev, &ib);
++		return r;
++	}
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(scratch);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
++			 ib.fence->ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
++			  scratch, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_gfx_scratch_free(adev, scratch);
++	amdgpu_ib_free(adev, &ib);
++	return r;
++}
++
++static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err;
++	struct amdgpu_firmware_info *info = NULL;
++	const struct common_firmware_header *header = NULL;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		chip_name = "topaz";
++		break;
++	case CHIP_TONGA:
++		chip_name = "tonga";
++		break;
++	case CHIP_CARRIZO:
++		chip_name = "carrizo";
++		break;
++	default:
++		BUG();
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
++	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
++	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.me_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
++	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
++	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
++	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
++	if (err)
++		goto out;
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
++	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
++	if (!err) {
++		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
++		if (err)
++			goto out;
++	} else {
++		err = 0;
++		adev->gfx.mec2_fw = NULL;
++	}
++
++	if (adev->firmware.smu_load) {
++		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
++		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
++		info->fw = adev->gfx.pfp_fw;
++		header = (const struct common_firmware_header *)info->fw->data;
++		adev->firmware.fw_size +=
++			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
++		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
++		info->fw = adev->gfx.me_fw;
++		header = (const struct common_firmware_header *)info->fw->data;
++		adev->firmware.fw_size +=
++			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
++		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
++		info->fw = adev->gfx.ce_fw;
++		header = (const struct common_firmware_header *)info->fw->data;
++		adev->firmware.fw_size +=
++			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
++		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
++		info->fw = adev->gfx.rlc_fw;
++		header = (const struct common_firmware_header *)info->fw->data;
++		adev->firmware.fw_size +=
++			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
++		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
++		info->fw = adev->gfx.mec_fw;
++		header = (const struct common_firmware_header *)info->fw->data;
++		adev->firmware.fw_size +=
++			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++		if (adev->gfx.mec2_fw) {
++			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
++			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
++			info->fw = adev->gfx.mec2_fw;
++			header = (const struct common_firmware_header *)info->fw->data;
++			adev->firmware.fw_size +=
++				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++		}
++
++	}
++
++out:
++	if (err) {
++		dev_err(adev->dev,
++			"gfx8: Failed to load firmware \"%s\"\n",
++			fw_name);
++		release_firmware(adev->gfx.pfp_fw);
++		adev->gfx.pfp_fw = NULL;
++		release_firmware(adev->gfx.me_fw);
++		adev->gfx.me_fw = NULL;
++		release_firmware(adev->gfx.ce_fw);
++		adev->gfx.ce_fw = NULL;
++		release_firmware(adev->gfx.rlc_fw);
++		adev->gfx.rlc_fw = NULL;
++		release_firmware(adev->gfx.mec_fw);
++		adev->gfx.mec_fw = NULL;
++		release_firmware(adev->gfx.mec2_fw);
++		adev->gfx.mec2_fw = NULL;
++	}
++	return err;
++}
++
++static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->gfx.mec.hpd_eop_obj) {
++		r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
++		if (unlikely(r != 0))
++			dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
++		amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
++		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
++
++		amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
++		adev->gfx.mec.hpd_eop_obj = NULL;
++	}
++}
++
++#define MEC_HPD_SIZE 2048
++
++static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
++{
++	int r;
++	u32 *hpd;
++
++	/*
++	 * we assign only 1 pipe because all other pipes will
++	 * be handled by KFD
++	 */
++	adev->gfx.mec.num_mec = 1;
++	adev->gfx.mec.num_pipe = 1;
++	adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
++
++	if (adev->gfx.mec.hpd_eop_obj == NULL) {
++		r = amdgpu_bo_create(adev,
++				     adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
++				     PAGE_SIZE, true,
++				     AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
++				     &adev->gfx.mec.hpd_eop_obj);
++		if (r) {
++			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
++			return r;
++		}
++	}
++
++	r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
++	if (unlikely(r != 0)) {
++		gfx_v8_0_mec_fini(adev);
++		return r;
++	}
++	r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
++			  &adev->gfx.mec.hpd_eop_gpu_addr);
++	if (r) {
++		dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
++		gfx_v8_0_mec_fini(adev);
++		return r;
++	}
++	r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
++	if (r) {
++		dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
++		gfx_v8_0_mec_fini(adev);
++		return r;
++	}
++
++	memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
++
++	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
++	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
++
++	return 0;
++}
++
++static int gfx_v8_0_sw_init(struct amdgpu_device *adev)
++{
++	int i, r;
++	struct amdgpu_ring *ring;
++
++	/* EOP Event */
++	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
++	if (r)
++		return r;
++
++	/* Privileged reg */
++	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
++	if (r)
++		return r;
++
++	/* Privileged inst */
++	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
++	if (r)
++		return r;
++
++	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
++
++	gfx_v8_0_scratch_init(adev);
++
++	r = gfx_v8_0_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load gfx firmware!\n");
++		return r;
++	}
++
++	r = gfx_v8_0_mec_init(adev);
++	if (r) {
++		DRM_ERROR("Failed to init MEC BOs!\n");
++		return r;
++	}
++
++	r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
++	if (r) {
++		DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
++		return r;
++	}
++
++	/* set up the gfx ring */
++	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
++		ring = &adev->gfx.gfx_ring[i];
++		ring->ring_obj = NULL;
++		sprintf(ring->name, "gfx");
++		/* no gfx doorbells on iceland */
++		if (adev->asic_type != CHIP_TOPAZ) {
++			ring->use_doorbell = true;
++			ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
++		}
++
++		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
++				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
++				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
++				     AMDGPU_RING_TYPE_GFX);
++		if (r)
++			return r;
++	}
++
++	/* set up the compute queues */
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		unsigned irq_type;
++
++		/* max 32 queues per MEC */
++		if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
++			DRM_ERROR("Too many (%d) compute rings!\n", i);
++			break;
++		}
++		ring = &adev->gfx.compute_ring[i];
++		ring->ring_obj = NULL;
++		ring->use_doorbell = true;
++		ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
++		ring->me = 1; /* first MEC */
++		ring->pipe = i / 8;
++		ring->queue = i % 8;
++		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
++		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
++		/* type-2 packets are deprecated on MEC, use type-3 instead */
++		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
++				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
++				     &adev->gfx.eop_irq, irq_type,
++				     AMDGPU_RING_TYPE_COMPUTE);
++		if (r)
++			return r;
++	}
++
++	/* reserve GDS, GWS and OA resource for gfx */
++	r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
++			PAGE_SIZE, true,
++			AMDGPU_GEM_DOMAIN_GDS, 0,
++			NULL, &adev->gds.gds_gfx_bo);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
++		PAGE_SIZE, true,
++		AMDGPU_GEM_DOMAIN_GWS, 0,
++		NULL, &adev->gds.gws_gfx_bo);
++	if (r)
++		return r;
++
++	r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
++			PAGE_SIZE, true,
++			AMDGPU_GEM_DOMAIN_OA, 0,
++			NULL, &adev->gds.oa_gfx_bo);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static int gfx_v8_0_sw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
++	amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
++	amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
++
++	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
++	for (i = 0; i < adev->gfx.num_compute_rings; i++)
++		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
++
++	amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
++
++	gfx_v8_0_mec_fini(adev);
++
++	return 0;
++}
++
++static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
++{
++	const u32 num_tile_mode_states = 32;
++	const u32 num_secondary_tile_mode_states = 16;
++	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
++
++	switch (adev->gfx.config.mem_row_size_in_kb) {
++	case 1:
++		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
++		break;
++	case 2:
++	default:
++		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
++		break;
++	case 4:
++		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
++		break;
++	}
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 1:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 2:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 3:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 4:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 5:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 6:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 8:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++						PIPE_CONFIG(ADDR_SURF_P2));
++				break;
++			case 9:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 10:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 11:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 13:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 14:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 15:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 16:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 18:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 19:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 20:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 21:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 22:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 24:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 25:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 26:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 27:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 28:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 29:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 7:
++			case 12:
++			case 17:
++			case 23:
++				/* unused idx */
++				continue;
++			default:
++				gb_tile_moden = 0;
++				break;
++			};
++			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 1:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 2:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 3:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 4:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 5:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 6:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 8:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 9:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 10:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 11:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 12:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 13:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 14:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 7:
++				/* unused idx */
++				continue;
++			default:
++				gb_tile_moden = 0;
++				break;
++			};
++			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++	case CHIP_TONGA:
++		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 1:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 2:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 3:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 4:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 5:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 6:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 7:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 8:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
++				break;
++			case 9:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 10:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 11:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 12:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 13:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 14:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 15:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 16:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 17:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 18:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 19:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 20:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 21:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 22:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 23:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 24:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 25:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 26:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 27:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 28:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 29:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 30:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			default:
++				gb_tile_moden = 0;
++				break;
++			};
++			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 1:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 2:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 3:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 4:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 5:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 6:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 8:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 9:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 10:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 11:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 12:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 13:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			case 14:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++						NUM_BANKS(ADDR_SURF_4_BANK));
++				break;
++			case 7:
++				/* unused idx */
++				continue;
++			default:
++				gb_tile_moden = 0;
++				break;
++			};
++			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		break;
++	case CHIP_CARRIZO:
++	default:
++		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 1:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 2:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 3:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 4:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 5:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 6:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++				break;
++			case 8:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++						PIPE_CONFIG(ADDR_SURF_P2));
++				break;
++			case 9:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 10:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 11:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 13:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 14:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 15:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 16:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 18:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 19:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 20:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 21:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 22:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 24:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 25:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 26:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++				break;
++			case 27:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 28:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++				break;
++			case 29:
++				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++						PIPE_CONFIG(ADDR_SURF_P2) |
++						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++				break;
++			case 7:
++			case 12:
++			case 17:
++			case 23:
++				/* unused idx */
++				continue;
++			default:
++				gb_tile_moden = 0;
++				break;
++			};
++			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
++			switch (reg_offset) {
++			case 0:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 1:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 2:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 3:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 4:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 5:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 6:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 8:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 9:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 10:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 11:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 12:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 13:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++						NUM_BANKS(ADDR_SURF_16_BANK));
++				break;
++			case 14:
++				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++						NUM_BANKS(ADDR_SURF_8_BANK));
++				break;
++			case 7:
++				/* unused idx */
++				continue;
++			default:
++				gb_tile_moden = 0;
++				break;
++			};
++			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
++			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
++		}
++	}
++}
++
++static u32 gfx_v8_0_create_bitmask(u32 bit_width)
++{
++	u32 i, mask = 0;
++
++	for (i = 0; i < bit_width; i++) {
++		mask <<= 1;
++		mask |= 1;
++	}
++	return mask;
++}
++
++void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
++{
++	u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
++
++	if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
++	} else if (se_num == 0xffffffff) {
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
++	} else if (sh_num == 0xffffffff) {
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
++	} else {
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
++		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
++	}
++	WREG32(mmGRBM_GFX_INDEX, data);
++}
++
++static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
++				    u32 max_rb_num_per_se,
++				    u32 sh_per_se)
++{
++	u32 data, mask;
++
++	data = RREG32(mmCC_RB_BACKEND_DISABLE);
++	if (data & 1)
++		data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
++	else
++		data = 0;
++
++	data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
++
++	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
++
++	mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
++
++	return data & mask;
++}
++
++static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
++			      u32 se_num, u32 sh_per_se,
++			      u32 max_rb_num_per_se)
++{
++	int i, j;
++	u32 data, mask;
++	u32 disabled_rbs = 0;
++	u32 enabled_rbs = 0;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < se_num; i++) {
++		for (j = 0; j < sh_per_se; j++) {
++			gfx_v8_0_select_se_sh(adev, i, j);
++			data = gfx_v8_0_get_rb_disabled(adev,
++					      max_rb_num_per_se, sh_per_se);
++			disabled_rbs |= data << ((i * sh_per_se + j) *
++						 RB_BITMAP_WIDTH_PER_SH);
++		}
++	}
++	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	mask = 1;
++	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
++		if (!(disabled_rbs & mask))
++			enabled_rbs |= mask;
++		mask <<= 1;
++	}
++
++	adev->gfx.config.backend_enable_mask = enabled_rbs;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < se_num; i++) {
++		gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
++		data = 0;
++		for (j = 0; j < sh_per_se; j++) {
++			switch (enabled_rbs & 3) {
++			case 0:
++				if (j == 0)
++					data |= (RASTER_CONFIG_RB_MAP_3 <<
++						 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
++				else
++					data |= (RASTER_CONFIG_RB_MAP_0 <<
++						 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
++				break;
++			case 1:
++				data |= (RASTER_CONFIG_RB_MAP_0 <<
++					 (i * sh_per_se + j) * 2);
++				break;
++			case 2:
++				data |= (RASTER_CONFIG_RB_MAP_3 <<
++					 (i * sh_per_se + j) * 2);
++				break;
++			case 3:
++			default:
++				data |= (RASTER_CONFIG_RB_MAP_2 <<
++					 (i * sh_per_se + j) * 2);
++				break;
++			}
++			enabled_rbs >>= 2;
++		}
++		WREG32(mmPA_SC_RASTER_CONFIG, data);
++	}
++	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++}
++
++static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
++{
++	u32 gb_addr_config;
++	u32 mc_shared_chmap, mc_arb_ramcfg;
++	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
++	u32 tmp;
++	int i;
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		adev->gfx.config.max_shader_engines = 1;
++		adev->gfx.config.max_tile_pipes = 2;
++		adev->gfx.config.max_cu_per_sh = 6;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 2;
++		adev->gfx.config.max_texture_channel_caches = 2;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 32;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	case CHIP_TONGA:
++		adev->gfx.config.max_shader_engines = 4;
++		adev->gfx.config.max_tile_pipes = 8;
++		adev->gfx.config.max_cu_per_sh = 8;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 2;
++		adev->gfx.config.max_texture_channel_caches = 8;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 32;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	case CHIP_CARRIZO:
++		adev->gfx.config.max_shader_engines = 1;
++		adev->gfx.config.max_tile_pipes = 2;
++		adev->gfx.config.max_cu_per_sh = 8;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 2;
++		adev->gfx.config.max_texture_channel_caches = 2;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 32;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	default:
++		adev->gfx.config.max_shader_engines = 2;
++		adev->gfx.config.max_tile_pipes = 4;
++		adev->gfx.config.max_cu_per_sh = 2;
++		adev->gfx.config.max_sh_per_se = 1;
++		adev->gfx.config.max_backends_per_se = 2;
++		adev->gfx.config.max_texture_channel_caches = 4;
++		adev->gfx.config.max_gprs = 256;
++		adev->gfx.config.max_gs_threads = 32;
++		adev->gfx.config.max_hw_contexts = 8;
++
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++		gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
++		break;
++	}
++
++	tmp = RREG32(mmGRBM_CNTL);
++	tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
++	WREG32(mmGRBM_CNTL, tmp);
++
++	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
++	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
++	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
++
++	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
++	adev->gfx.config.mem_max_burst_length_bytes = 256;
++	if (adev->flags & AMDGPU_IS_APU) {
++		/* Get memory bank mapping mode. */
++		tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
++		dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
++		dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
++
++		tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
++		dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
++		dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
++
++		/* Validate settings in case only one DIMM installed. */
++		if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
++			dimm00_addr_map = 0;
++		if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
++			dimm01_addr_map = 0;
++		if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
++			dimm10_addr_map = 0;
++		if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
++			dimm11_addr_map = 0;
++
++		/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
++		/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
++		if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
++			adev->gfx.config.mem_row_size_in_kb = 2;
++		else
++			adev->gfx.config.mem_row_size_in_kb = 1;
++	} else {
++		tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
++		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
++		if (adev->gfx.config.mem_row_size_in_kb > 4)
++			adev->gfx.config.mem_row_size_in_kb = 4;
++	}
++
++	adev->gfx.config.shader_engine_tile_size = 32;
++	adev->gfx.config.num_gpus = 1;
++	adev->gfx.config.multi_gpu_tile_size = 64;
++
++	/* fix up row size */
++	switch (adev->gfx.config.mem_row_size_in_kb) {
++	case 1:
++	default:
++		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
++		break;
++	case 2:
++		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
++		break;
++	case 4:
++		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
++		break;
++	}
++	adev->gfx.config.gb_addr_config = gb_addr_config;
++
++	WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
++	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
++	       gb_addr_config & 0x70);
++	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
++	       gb_addr_config & 0x70);
++	WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
++	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
++
++	gfx_v8_0_tiling_mode_table_init(adev);
++
++	gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
++				 adev->gfx.config.max_sh_per_se,
++				 adev->gfx.config.max_backends_per_se);
++
++	/* XXX SH_MEM regs */
++	/* where to put LDS, scratch, GPUVM in FSA64 space */
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < 16; i++) {
++		vi_srbm_select(adev, 0, 0, 0, i);
++		/* CP and shaders */
++		if (i == 0) {
++			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
++			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
++			WREG32(mmSH_MEM_CONFIG, tmp);
++		} else {
++			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
++			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
++			WREG32(mmSH_MEM_CONFIG, tmp);
++		}
++
++		WREG32(mmSH_MEM_APE1_BASE, 1);
++		WREG32(mmSH_MEM_APE1_LIMIT, 0);
++		WREG32(mmSH_MEM_BASES, 0);
++	}
++	vi_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	/*
++	 * making sure that the following register writes will be broadcasted
++	 * to all the shaders
++	 */
++	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++
++	WREG32(mmPA_SC_FIFO_SIZE,
++		   (adev->gfx.config.sc_prim_fifo_size_frontend <<
++			PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
++		   (adev->gfx.config.sc_prim_fifo_size_backend <<
++			PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
++		   (adev->gfx.config.sc_hiz_tile_fifo_size <<
++			PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
++		   (adev->gfx.config.sc_earlyz_tile_fifo_size <<
++			PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++}
++
++static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
++{
++	u32 i, j, k;
++	u32 mask;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
++		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
++			gfx_v8_0_select_se_sh(adev, i, j);
++			for (k = 0; k < adev->usec_timeout; k++) {
++				if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
++					break;
++				udelay(1);
++			}
++		}
++	}
++	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
++		RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
++		RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
++		RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
++	for (k = 0; k < adev->usec_timeout; k++) {
++		if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
++			break;
++		udelay(1);
++	}
++}
++
++static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
++					       bool enable)
++{
++	u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
++
++	if (enable) {
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
++	} else {
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
++		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
++	}
++	WREG32(mmCP_INT_CNTL_RING0, tmp);
++}
++
++void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmRLC_CNTL);
++
++	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
++	WREG32(mmRLC_CNTL, tmp);
++
++	gfx_v8_0_enable_gui_idle_interrupt(adev, false);
++
++	gfx_v8_0_wait_for_rlc_serdes(adev);
++}
++
++static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmGRBM_SOFT_RESET);
++
++	tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
++	WREG32(mmGRBM_SOFT_RESET, tmp);
++	udelay(50);
++	tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
++	WREG32(mmGRBM_SOFT_RESET, tmp);
++	udelay(50);
++}
++
++static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmRLC_CNTL);
++
++	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
++	WREG32(mmRLC_CNTL, tmp);
++
++	/* carrizo do enable cp interrupt after cp inited */
++	if (adev->asic_type != CHIP_CARRIZO)
++		gfx_v8_0_enable_gui_idle_interrupt(adev, true);
++
++	udelay(50);
++}
++
++static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
++{
++	const struct rlc_firmware_header_v2_0 *hdr;
++	const __le32 *fw_data;
++	unsigned i, fw_size;
++
++	if (!adev->gfx.rlc_fw)
++		return -EINVAL;
++
++	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
++	amdgpu_ucode_print_rlc_hdr(&hdr->header);
++	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
++
++	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
++			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++
++	WREG32(mmRLC_GPM_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
++
++	return 0;
++}
++
++static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	gfx_v8_0_rlc_stop(adev);
++
++	/* disable CG */
++	WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
++
++	/* disable PG */
++	WREG32(mmRLC_PG_CNTL, 0);
++
++	gfx_v8_0_rlc_reset(adev);
++
++	if (!adev->firmware.smu_load) {
++		/* legacy rlc firmware loading */
++		r = gfx_v8_0_rlc_load_microcode(adev);
++		if (r)
++			return r;
++	} else {
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_RLC_G);
++		if (r)
++			return -EINVAL;
++	}
++
++	gfx_v8_0_rlc_start(adev);
++
++	return 0;
++}
++
++static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
++{
++	int i;
++	u32 tmp = RREG32(mmCP_ME_CNTL);
++
++	if (enable) {
++		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
++		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
++		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
++	} else {
++		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
++		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
++		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
++		for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++			adev->gfx.gfx_ring[i].ready = false;
++	}
++	WREG32(mmCP_ME_CNTL, tmp);
++	udelay(50);
++}
++
++static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
++{
++	const struct gfx_firmware_header_v1_0 *pfp_hdr;
++	const struct gfx_firmware_header_v1_0 *ce_hdr;
++	const struct gfx_firmware_header_v1_0 *me_hdr;
++	const __le32 *fw_data;
++	unsigned i, fw_size;
++
++	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
++		return -EINVAL;
++
++	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
++		adev->gfx.pfp_fw->data;
++	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
++		adev->gfx.ce_fw->data;
++	me_hdr = (const struct gfx_firmware_header_v1_0 *)
++		adev->gfx.me_fw->data;
++
++	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
++	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
++	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
++	adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
++	adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
++	adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
++
++	gfx_v8_0_cp_gfx_enable(adev, false);
++
++	/* PFP */
++	fw_data = (const __le32 *)
++		(adev->gfx.pfp_fw->data +
++		 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_PFP_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
++
++	/* CE */
++	fw_data = (const __le32 *)
++		(adev->gfx.ce_fw->data +
++		 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_CE_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
++
++	/* ME */
++	fw_data = (const __le32 *)
++		(adev->gfx.me_fw->data +
++		 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
++	WREG32(mmCP_ME_RAM_WADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
++	WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
++
++	return 0;
++}
++
++static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
++{
++	u32 count = 0;
++	const struct cs_section_def *sect = NULL;
++	const struct cs_extent_def *ext = NULL;
++
++	/* begin clear state */
++	count += 2;
++	/* context control state */
++	count += 3;
++
++	for (sect = vi_cs_data; sect->section != NULL; ++sect) {
++		for (ext = sect->section; ext->extent != NULL; ++ext) {
++			if (sect->id == SECT_CONTEXT)
++				count += 2 + ext->reg_count;
++			else
++				return 0;
++		}
++	}
++	/* pa_sc_raster_config/pa_sc_raster_config1 */
++	count += 4;
++	/* end clear state */
++	count += 2;
++	/* clear state */
++	count += 2;
++
++	return count;
++}
++
++static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
++	const struct cs_section_def *sect = NULL;
++	const struct cs_extent_def *ext = NULL;
++	int r, i;
++
++	/* init the CP */
++	WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
++	WREG32(mmCP_ENDIAN_SWAP, 0);
++	WREG32(mmCP_DEVICE_ID, 1);
++
++	gfx_v8_0_cp_gfx_enable(adev, true);
++
++	r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
++		return r;
++	}
++
++	/* clear state buffer */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
++	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
++	amdgpu_ring_write(ring, 0x80000000);
++	amdgpu_ring_write(ring, 0x80000000);
++
++	for (sect = vi_cs_data; sect->section != NULL; ++sect) {
++		for (ext = sect->section; ext->extent != NULL; ++ext) {
++			if (sect->id == SECT_CONTEXT) {
++				amdgpu_ring_write(ring,
++				       PACKET3(PACKET3_SET_CONTEXT_REG,
++					       ext->reg_count));
++				amdgpu_ring_write(ring,
++				       ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
++				for (i = 0; i < ext->reg_count; i++)
++					amdgpu_ring_write(ring, ext->extent[i]);
++			}
++		}
++	}
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
++	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
++	switch (adev->asic_type) {
++	case CHIP_TONGA:
++		amdgpu_ring_write(ring, 0x16000012);
++		amdgpu_ring_write(ring, 0x0000002A);
++		break;
++	case CHIP_TOPAZ:
++	case CHIP_CARRIZO:
++		amdgpu_ring_write(ring, 0x00000002);
++		amdgpu_ring_write(ring, 0x00000000);
++		break;
++	default:
++		BUG();
++	}
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
++	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
++	amdgpu_ring_write(ring, 0);
++
++	/* init the CE partitions */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
++	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
++	amdgpu_ring_write(ring, 0x8000);
++	amdgpu_ring_write(ring, 0x8000);
++
++	amdgpu_ring_unlock_commit(ring);
++
++	return 0;
++}
++
++static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	u32 tmp;
++	u32 rb_bufsz;
++	u64 rb_addr, rptr_addr;
++	int r;
++
++	/* Set the write pointer delay */
++	WREG32(mmCP_RB_WPTR_DELAY, 0);
++
++	/* set the RB to use vmid 0 */
++	WREG32(mmCP_RB_VMID, 0);
++
++	/* Set ring buffer size */
++	ring = &adev->gfx.gfx_ring[0];
++	rb_bufsz = order_base_2(ring->ring_size / 8);
++	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
++	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
++	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
++	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
++#ifdef __BIG_ENDIAN
++	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
++#endif
++	WREG32(mmCP_RB0_CNTL, tmp);
++
++	/* Initialize the ring buffer's read and write pointers */
++	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
++	ring->wptr = 0;
++	WREG32(mmCP_RB0_WPTR, ring->wptr);
++
++	/* set the wb address wether it's enabled or not */
++	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
++	WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
++	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
++
++	mdelay(1);
++	WREG32(mmCP_RB0_CNTL, tmp);
++
++	rb_addr = ring->gpu_addr >> 8;
++	WREG32(mmCP_RB0_BASE, rb_addr);
++	WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
++
++	/* no gfx doorbells on iceland */
++	if (adev->asic_type != CHIP_TOPAZ) {
++		tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
++		if (ring->use_doorbell) {
++			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
++					    DOORBELL_OFFSET, ring->doorbell_index);
++			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
++					    DOORBELL_EN, 1);
++		} else {
++			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
++					    DOORBELL_EN, 0);
++		}
++		WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
++
++		if (adev->asic_type == CHIP_TONGA) {
++			tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
++					    DOORBELL_RANGE_LOWER,
++					    AMDGPU_DOORBELL_GFX_RING0);
++			WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
++
++			WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
++			       CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
++		}
++
++	}
++
++	/* start the ring */
++	gfx_v8_0_cp_gfx_start(adev);
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		return r;
++	}
++
++	return 0;
++}
++
++static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
++{
++	int i;
++
++	if (enable) {
++		WREG32(mmCP_MEC_CNTL, 0);
++	} else {
++		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
++		for (i = 0; i < adev->gfx.num_compute_rings; i++)
++			adev->gfx.compute_ring[i].ready = false;
++	}
++	udelay(50);
++}
++
++static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
++{
++	gfx_v8_0_cp_compute_enable(adev, true);
++
++	return 0;
++}
++
++static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
++{
++	const struct gfx_firmware_header_v1_0 *mec_hdr;
++	const __le32 *fw_data;
++	unsigned i, fw_size;
++
++	if (!adev->gfx.mec_fw)
++		return -EINVAL;
++
++	gfx_v8_0_cp_compute_enable(adev, false);
++
++	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
++	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
++	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
++
++	fw_data = (const __le32 *)
++		(adev->gfx.mec_fw->data +
++		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
++	fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
++
++	/* MEC1 */
++	WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
++	for (i = 0; i < fw_size; i++)
++		WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
++	WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
++
++	/* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
++	if (adev->gfx.mec2_fw) {
++		const struct gfx_firmware_header_v1_0 *mec2_hdr;
++
++		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
++		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
++		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
++
++		fw_data = (const __le32 *)
++			(adev->gfx.mec2_fw->data +
++			 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
++		fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
++
++		WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
++		for (i = 0; i < fw_size; i++)
++			WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
++		WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
++	}
++
++	return 0;
++}
++
++struct vi_mqd {
++	uint32_t header;  /* ordinal0 */
++	uint32_t compute_dispatch_initiator;  /* ordinal1 */
++	uint32_t compute_dim_x;  /* ordinal2 */
++	uint32_t compute_dim_y;  /* ordinal3 */
++	uint32_t compute_dim_z;  /* ordinal4 */
++	uint32_t compute_start_x;  /* ordinal5 */
++	uint32_t compute_start_y;  /* ordinal6 */
++	uint32_t compute_start_z;  /* ordinal7 */
++	uint32_t compute_num_thread_x;  /* ordinal8 */
++	uint32_t compute_num_thread_y;  /* ordinal9 */
++	uint32_t compute_num_thread_z;  /* ordinal10 */
++	uint32_t compute_pipelinestat_enable;  /* ordinal11 */
++	uint32_t compute_perfcount_enable;  /* ordinal12 */
++	uint32_t compute_pgm_lo;  /* ordinal13 */
++	uint32_t compute_pgm_hi;  /* ordinal14 */
++	uint32_t compute_tba_lo;  /* ordinal15 */
++	uint32_t compute_tba_hi;  /* ordinal16 */
++	uint32_t compute_tma_lo;  /* ordinal17 */
++	uint32_t compute_tma_hi;  /* ordinal18 */
++	uint32_t compute_pgm_rsrc1;  /* ordinal19 */
++	uint32_t compute_pgm_rsrc2;  /* ordinal20 */
++	uint32_t compute_vmid;  /* ordinal21 */
++	uint32_t compute_resource_limits;  /* ordinal22 */
++	uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
++	uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
++	uint32_t compute_tmpring_size;  /* ordinal25 */
++	uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
++	uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
++	uint32_t compute_restart_x;  /* ordinal28 */
++	uint32_t compute_restart_y;  /* ordinal29 */
++	uint32_t compute_restart_z;  /* ordinal30 */
++	uint32_t compute_thread_trace_enable;  /* ordinal31 */
++	uint32_t compute_misc_reserved;  /* ordinal32 */
++	uint32_t compute_dispatch_id;  /* ordinal33 */
++	uint32_t compute_threadgroup_id;  /* ordinal34 */
++	uint32_t compute_relaunch;  /* ordinal35 */
++	uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
++	uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
++	uint32_t compute_wave_restore_control;  /* ordinal38 */
++	uint32_t reserved9;  /* ordinal39 */
++	uint32_t reserved10;  /* ordinal40 */
++	uint32_t reserved11;  /* ordinal41 */
++	uint32_t reserved12;  /* ordinal42 */
++	uint32_t reserved13;  /* ordinal43 */
++	uint32_t reserved14;  /* ordinal44 */
++	uint32_t reserved15;  /* ordinal45 */
++	uint32_t reserved16;  /* ordinal46 */
++	uint32_t reserved17;  /* ordinal47 */
++	uint32_t reserved18;  /* ordinal48 */
++	uint32_t reserved19;  /* ordinal49 */
++	uint32_t reserved20;  /* ordinal50 */
++	uint32_t reserved21;  /* ordinal51 */
++	uint32_t reserved22;  /* ordinal52 */
++	uint32_t reserved23;  /* ordinal53 */
++	uint32_t reserved24;  /* ordinal54 */
++	uint32_t reserved25;  /* ordinal55 */
++	uint32_t reserved26;  /* ordinal56 */
++	uint32_t reserved27;  /* ordinal57 */
++	uint32_t reserved28;  /* ordinal58 */
++	uint32_t reserved29;  /* ordinal59 */
++	uint32_t reserved30;  /* ordinal60 */
++	uint32_t reserved31;  /* ordinal61 */
++	uint32_t reserved32;  /* ordinal62 */
++	uint32_t reserved33;  /* ordinal63 */
++	uint32_t reserved34;  /* ordinal64 */
++	uint32_t compute_user_data_0;  /* ordinal65 */
++	uint32_t compute_user_data_1;  /* ordinal66 */
++	uint32_t compute_user_data_2;  /* ordinal67 */
++	uint32_t compute_user_data_3;  /* ordinal68 */
++	uint32_t compute_user_data_4;  /* ordinal69 */
++	uint32_t compute_user_data_5;  /* ordinal70 */
++	uint32_t compute_user_data_6;  /* ordinal71 */
++	uint32_t compute_user_data_7;  /* ordinal72 */
++	uint32_t compute_user_data_8;  /* ordinal73 */
++	uint32_t compute_user_data_9;  /* ordinal74 */
++	uint32_t compute_user_data_10;  /* ordinal75 */
++	uint32_t compute_user_data_11;  /* ordinal76 */
++	uint32_t compute_user_data_12;  /* ordinal77 */
++	uint32_t compute_user_data_13;  /* ordinal78 */
++	uint32_t compute_user_data_14;  /* ordinal79 */
++	uint32_t compute_user_data_15;  /* ordinal80 */
++	uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
++	uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
++	uint32_t reserved35;  /* ordinal83 */
++	uint32_t reserved36;  /* ordinal84 */
++	uint32_t reserved37;  /* ordinal85 */
++	uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
++	uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
++	uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
++	uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
++	uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
++	uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
++	uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
++	uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
++	uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
++	uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
++	uint32_t reserved38;  /* ordinal96 */
++	uint32_t reserved39;  /* ordinal97 */
++	uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
++	uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
++	uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
++	uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
++	uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
++	uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
++	uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
++	uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
++	uint32_t reserved40;  /* ordinal106 */
++	uint32_t reserved41;  /* ordinal107 */
++	uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
++	uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
++	uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
++	uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
++	uint32_t reserved42;  /* ordinal112 */
++	uint32_t reserved43;  /* ordinal113 */
++	uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
++	uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
++	uint32_t cp_packet_id_lo;  /* ordinal116 */
++	uint32_t cp_packet_id_hi;  /* ordinal117 */
++	uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
++	uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
++	uint32_t gds_save_base_addr_lo;  /* ordinal120 */
++	uint32_t gds_save_base_addr_hi;  /* ordinal121 */
++	uint32_t gds_save_mask_lo;  /* ordinal122 */
++	uint32_t gds_save_mask_hi;  /* ordinal123 */
++	uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
++	uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
++	uint32_t reserved44;  /* ordinal126 */
++	uint32_t reserved45;  /* ordinal127 */
++	uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
++	uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
++	uint32_t cp_hqd_active;  /* ordinal130 */
++	uint32_t cp_hqd_vmid;  /* ordinal131 */
++	uint32_t cp_hqd_persistent_state;  /* ordinal132 */
++	uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
++	uint32_t cp_hqd_queue_priority;  /* ordinal134 */
++	uint32_t cp_hqd_quantum;  /* ordinal135 */
++	uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
++	uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
++	uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
++	uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
++	uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
++	uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
++	uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
++	uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
++	uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
++	uint32_t cp_hqd_pq_control;  /* ordinal145 */
++	uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
++	uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
++	uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
++	uint32_t cp_hqd_ib_control;  /* ordinal149 */
++	uint32_t cp_hqd_iq_timer;  /* ordinal150 */
++	uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
++	uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
++	uint32_t cp_hqd_dma_offload;  /* ordinal153 */
++	uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
++	uint32_t cp_hqd_msg_type;  /* ordinal155 */
++	uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
++	uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
++	uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
++	uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
++	uint32_t cp_hqd_hq_status0;  /* ordinal160 */
++	uint32_t cp_hqd_hq_control0;  /* ordinal161 */
++	uint32_t cp_mqd_control;  /* ordinal162 */
++	uint32_t cp_hqd_hq_status1;  /* ordinal163 */
++	uint32_t cp_hqd_hq_control1;  /* ordinal164 */
++	uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
++	uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
++	uint32_t cp_hqd_eop_control;  /* ordinal167 */
++	uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
++	uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
++	uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
++	uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
++	uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
++	uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
++	uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
++	uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
++	uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
++	uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
++	uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
++	uint32_t cp_hqd_error;  /* ordinal179 */
++	uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
++	uint32_t cp_hqd_eop_dones;  /* ordinal181 */
++	uint32_t reserved46;  /* ordinal182 */
++	uint32_t reserved47;  /* ordinal183 */
++	uint32_t reserved48;  /* ordinal184 */
++	uint32_t reserved49;  /* ordinal185 */
++	uint32_t reserved50;  /* ordinal186 */
++	uint32_t reserved51;  /* ordinal187 */
++	uint32_t reserved52;  /* ordinal188 */
++	uint32_t reserved53;  /* ordinal189 */
++	uint32_t reserved54;  /* ordinal190 */
++	uint32_t reserved55;  /* ordinal191 */
++	uint32_t iqtimer_pkt_header;  /* ordinal192 */
++	uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
++	uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
++	uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
++	uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
++	uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
++	uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
++	uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
++	uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
++	uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
++	uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
++	uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
++	uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
++	uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
++	uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
++	uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
++	uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
++	uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
++	uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
++	uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
++	uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
++	uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
++	uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
++	uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
++	uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
++	uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
++	uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
++	uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
++	uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
++	uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
++	uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
++	uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
++	uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
++	uint32_t reserved56;  /* ordinal225 */
++	uint32_t reserved57;  /* ordinal226 */
++	uint32_t reserved58;  /* ordinal227 */
++	uint32_t set_resources_header;  /* ordinal228 */
++	uint32_t set_resources_dw1;  /* ordinal229 */
++	uint32_t set_resources_dw2;  /* ordinal230 */
++	uint32_t set_resources_dw3;  /* ordinal231 */
++	uint32_t set_resources_dw4;  /* ordinal232 */
++	uint32_t set_resources_dw5;  /* ordinal233 */
++	uint32_t set_resources_dw6;  /* ordinal234 */
++	uint32_t set_resources_dw7;  /* ordinal235 */
++	uint32_t reserved59;  /* ordinal236 */
++	uint32_t reserved60;  /* ordinal237 */
++	uint32_t reserved61;  /* ordinal238 */
++	uint32_t reserved62;  /* ordinal239 */
++	uint32_t reserved63;  /* ordinal240 */
++	uint32_t reserved64;  /* ordinal241 */
++	uint32_t reserved65;  /* ordinal242 */
++	uint32_t reserved66;  /* ordinal243 */
++	uint32_t reserved67;  /* ordinal244 */
++	uint32_t reserved68;  /* ordinal245 */
++	uint32_t reserved69;  /* ordinal246 */
++	uint32_t reserved70;  /* ordinal247 */
++	uint32_t reserved71;  /* ordinal248 */
++	uint32_t reserved72;  /* ordinal249 */
++	uint32_t reserved73;  /* ordinal250 */
++	uint32_t reserved74;  /* ordinal251 */
++	uint32_t reserved75;  /* ordinal252 */
++	uint32_t reserved76;  /* ordinal253 */
++	uint32_t reserved77;  /* ordinal254 */
++	uint32_t reserved78;  /* ordinal255 */
++
++	uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
++};
++
++static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
++{
++	int i, r;
++
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
++
++		if (ring->mqd_obj) {
++			r = amdgpu_bo_reserve(ring->mqd_obj, false);
++			if (unlikely(r != 0))
++				dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
++
++			amdgpu_bo_unpin(ring->mqd_obj);
++			amdgpu_bo_unreserve(ring->mqd_obj);
++
++			amdgpu_bo_unref(&ring->mqd_obj);
++			ring->mqd_obj = NULL;
++		}
++	}
++}
++
++static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
++{
++	int r, i, j;
++	u32 tmp;
++	bool use_doorbell = true;
++	u64 hqd_gpu_addr;
++	u64 mqd_gpu_addr;
++	u64 eop_gpu_addr;
++	u64 wb_gpu_addr;
++	u32 *buf;
++	struct vi_mqd *mqd;
++
++	/* init the pipes */
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
++		int me = (i < 4) ? 1 : 2;
++		int pipe = (i < 4) ? i : (i - 4);
++
++		eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
++		eop_gpu_addr >>= 8;
++
++		vi_srbm_select(adev, me, pipe, 0, 0);
++
++		/* write the EOP addr */
++		WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
++		WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
++
++		/* set the VMID assigned */
++		WREG32(mmCP_HQD_VMID, 0);
++
++		/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
++		tmp = RREG32(mmCP_HQD_EOP_CONTROL);
++		tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
++				    (order_base_2(MEC_HPD_SIZE / 4) - 1));
++		WREG32(mmCP_HQD_EOP_CONTROL, tmp);
++	}
++	vi_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++
++	/* init the queues.  Just two for now. */
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
++
++		if (ring->mqd_obj == NULL) {
++			r = amdgpu_bo_create(adev,
++					     sizeof(struct vi_mqd),
++					     PAGE_SIZE, true,
++					     AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
++					     &ring->mqd_obj);
++			if (r) {
++				dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
++				return r;
++			}
++		}
++
++		r = amdgpu_bo_reserve(ring->mqd_obj, false);
++		if (unlikely(r != 0)) {
++			gfx_v8_0_cp_compute_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
++				  &mqd_gpu_addr);
++		if (r) {
++			dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
++			gfx_v8_0_cp_compute_fini(adev);
++			return r;
++		}
++		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
++		if (r) {
++			dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
++			gfx_v8_0_cp_compute_fini(adev);
++			return r;
++		}
++
++		/* init the mqd struct */
++		memset(buf, 0, sizeof(struct vi_mqd));
++
++		mqd = (struct vi_mqd *)buf;
++		mqd->header = 0xC0310800;
++		mqd->compute_pipelinestat_enable = 0x00000001;
++		mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
++		mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
++		mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
++		mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
++		mqd->compute_misc_reserved = 0x00000003;
++
++		mutex_lock(&adev->srbm_mutex);
++		vi_srbm_select(adev, ring->me,
++			       ring->pipe,
++			       ring->queue, 0);
++
++		/* disable wptr polling */
++		tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
++		tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
++		WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
++
++		mqd->cp_hqd_eop_base_addr_lo =
++			RREG32(mmCP_HQD_EOP_BASE_ADDR);
++		mqd->cp_hqd_eop_base_addr_hi =
++			RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
++
++		/* enable doorbell? */
++		tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
++		if (use_doorbell) {
++			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
++		} else {
++			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
++		}
++		WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
++		mqd->cp_hqd_pq_doorbell_control = tmp;
++
++		/* disable the queue if it's active */
++		mqd->cp_hqd_dequeue_request = 0;
++		mqd->cp_hqd_pq_rptr = 0;
++		mqd->cp_hqd_pq_wptr= 0;
++		if (RREG32(mmCP_HQD_ACTIVE) & 1) {
++			WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
++			for (j = 0; j < adev->usec_timeout; j++) {
++				if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
++					break;
++				udelay(1);
++			}
++			WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
++			WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
++			WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
++		}
++
++		/* set the pointer to the MQD */
++		mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
++		mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
++		WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
++		WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
++
++		/* set MQD vmid to 0 */
++		tmp = RREG32(mmCP_MQD_CONTROL);
++		tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
++		WREG32(mmCP_MQD_CONTROL, tmp);
++		mqd->cp_mqd_control = tmp;
++
++		/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
++		hqd_gpu_addr = ring->gpu_addr >> 8;
++		mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
++		mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
++		WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
++		WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
++
++		/* set up the HQD, this is similar to CP_RB0_CNTL */
++		tmp = RREG32(mmCP_HQD_PQ_CONTROL);
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
++				    (order_base_2(ring->ring_size / 4) - 1));
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
++			       ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
++#ifdef __BIG_ENDIAN
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
++#endif
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
++		WREG32(mmCP_HQD_PQ_CONTROL, tmp);
++		mqd->cp_hqd_pq_control = tmp;
++
++		/* set the wb address wether it's enabled or not */
++		wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
++		mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
++		mqd->cp_hqd_pq_rptr_report_addr_hi =
++			upper_32_bits(wb_gpu_addr) & 0xffff;
++		WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
++		       mqd->cp_hqd_pq_rptr_report_addr_lo);
++		WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
++		       mqd->cp_hqd_pq_rptr_report_addr_hi);
++
++		/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
++		wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
++		mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
++		mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
++		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
++		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
++		       mqd->cp_hqd_pq_wptr_poll_addr_hi);
++
++		/* enable the doorbell if requested */
++		if (use_doorbell) {
++			if (adev->asic_type == CHIP_CARRIZO) {
++				WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
++				       AMDGPU_DOORBELL_KIQ << 2);
++				WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
++				       AMDGPU_DOORBELL_MEC_RING7 << 2);
++			}
++			tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
++			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
++					    DOORBELL_OFFSET, ring->doorbell_index);
++			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
++			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
++			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
++			mqd->cp_hqd_pq_doorbell_control = tmp;
++
++		} else {
++			mqd->cp_hqd_pq_doorbell_control = 0;
++		}
++		WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
++		       mqd->cp_hqd_pq_doorbell_control);
++
++		/* set the vmid for the queue */
++		mqd->cp_hqd_vmid = 0;
++		WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
++
++		tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
++		tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
++		WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
++		mqd->cp_hqd_persistent_state = tmp;
++
++		/* activate the queue */
++		mqd->cp_hqd_active = 1;
++		WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
++
++		vi_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++
++		amdgpu_bo_kunmap(ring->mqd_obj);
++		amdgpu_bo_unreserve(ring->mqd_obj);
++	}
++
++	if (use_doorbell) {
++		tmp = RREG32(mmCP_PQ_STATUS);
++		tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
++		WREG32(mmCP_PQ_STATUS, tmp);
++	}
++
++	r = gfx_v8_0_cp_compute_start(adev);
++	if (r)
++		return r;
++
++	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
++
++		ring->ready = true;
++		r = amdgpu_ring_test_ring(ring);
++		if (r)
++			ring->ready = false;
++	}
++
++	return 0;
++}
++
++static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->asic_type != CHIP_CARRIZO)
++		gfx_v8_0_enable_gui_idle_interrupt(adev, false);
++
++	if (!adev->firmware.smu_load) {
++		/* legacy firmware loading */
++		r = gfx_v8_0_cp_gfx_load_microcode(adev);
++		if (r)
++			return r;
++
++		r = gfx_v8_0_cp_compute_load_microcode(adev);
++		if (r)
++			return r;
++	} else {
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_CP_CE);
++		if (r)
++			return -EINVAL;
++
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_CP_PFP);
++		if (r)
++			return -EINVAL;
++
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_CP_ME);
++		if (r)
++			return -EINVAL;
++
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_CP_MEC1);
++		if (r)
++			return -EINVAL;
++	}
++
++	r = gfx_v8_0_cp_gfx_resume(adev);
++	if (r)
++		return r;
++
++	r = gfx_v8_0_cp_compute_resume(adev);
++	if (r)
++		return r;
++
++	gfx_v8_0_enable_gui_idle_interrupt(adev, true);
++
++	return 0;
++}
++
++static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
++{
++	gfx_v8_0_cp_gfx_enable(adev, enable);
++	gfx_v8_0_cp_compute_enable(adev, enable);
++}
++
++static int gfx_v8_0_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	gfx_v8_0_init_golden_registers(adev);
++
++	gfx_v8_0_gpu_init(adev);
++
++	r = gfx_v8_0_rlc_resume(adev);
++	if (r)
++		return r;
++
++	r = gfx_v8_0_cp_resume(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int gfx_v8_0_hw_fini(struct amdgpu_device *adev)
++{
++	gfx_v8_0_cp_enable(adev, false);
++	gfx_v8_0_rlc_stop(adev);
++	gfx_v8_0_cp_compute_fini(adev);
++
++	return 0;
++}
++
++static int gfx_v8_0_suspend(struct amdgpu_device *adev)
++{
++	return gfx_v8_0_hw_fini(adev);
++}
++
++static int gfx_v8_0_resume(struct amdgpu_device *adev)
++{
++	return gfx_v8_0_hw_init(adev);
++}
++
++static bool gfx_v8_0_is_idle(struct amdgpu_device *adev)
++{
++	if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
++		return false;
++	else
++		return true;
++}
++
++static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
++
++		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void gfx_v8_0_print_status(struct amdgpu_device *adev)
++{
++	int i;
++
++	dev_info(adev->dev, "GFX 8.x registers\n");
++	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
++		 RREG32(mmGRBM_STATUS));
++	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
++		 RREG32(mmGRBM_STATUS2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
++		 RREG32(mmGRBM_STATUS_SE0));
++	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
++		 RREG32(mmGRBM_STATUS_SE1));
++	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
++		 RREG32(mmGRBM_STATUS_SE2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
++		 RREG32(mmGRBM_STATUS_SE3));
++	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
++	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT2));
++	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT3));
++	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
++		 RREG32(mmCP_CPF_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPF_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
++	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPC_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
++
++	for (i = 0; i < 32; i++) {
++		dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
++			 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
++	}
++	for (i = 0; i < 16; i++) {
++		dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
++			 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
++	}
++	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
++		dev_info(adev->dev, "  se: %d\n", i);
++		gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
++		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
++			 RREG32(mmPA_SC_RASTER_CONFIG));
++		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
++			 RREG32(mmPA_SC_RASTER_CONFIG_1));
++	}
++	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++
++	dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmGB_ADDR_CONFIG));
++	dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmHDP_ADDR_CONFIG));
++	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
++		 RREG32(mmDMIF_ADDR_CALC));
++	dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
++		 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
++	dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
++		 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
++	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
++
++	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
++		 RREG32(mmCP_MEQ_THRESHOLDS));
++	dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
++		 RREG32(mmSX_DEBUG_1));
++	dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
++		 RREG32(mmTA_CNTL_AUX));
++	dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
++		 RREG32(mmSPI_CONFIG_CNTL));
++	dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
++		 RREG32(mmSQ_CONFIG));
++	dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
++		 RREG32(mmDB_DEBUG));
++	dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
++		 RREG32(mmDB_DEBUG2));
++	dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
++		 RREG32(mmDB_DEBUG3));
++	dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
++		 RREG32(mmCB_HW_CONTROL));
++	dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
++		 RREG32(mmSPI_CONFIG_CNTL_1));
++	dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
++		 RREG32(mmPA_SC_FIFO_SIZE));
++	dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
++		 RREG32(mmVGT_NUM_INSTANCES));
++	dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
++		 RREG32(mmCP_PERFMON_CNTL));
++	dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
++		 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
++	dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
++		 RREG32(mmVGT_CACHE_INVALIDATION));
++	dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
++		 RREG32(mmVGT_GS_VERTEX_REUSE));
++	dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
++		 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
++	dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
++		 RREG32(mmPA_CL_ENHANCE));
++	dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
++		 RREG32(mmPA_SC_ENHANCE));
++
++	dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
++		 RREG32(mmCP_ME_CNTL));
++	dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
++		 RREG32(mmCP_MAX_CONTEXT));
++	dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
++		 RREG32(mmCP_ENDIAN_SWAP));
++	dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
++		 RREG32(mmCP_DEVICE_ID));
++
++	dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
++		 RREG32(mmCP_SEM_WAIT_TIMER));
++
++	dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
++		 RREG32(mmCP_RB_WPTR_DELAY));
++	dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
++		 RREG32(mmCP_RB_VMID));
++	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
++		 RREG32(mmCP_RB0_CNTL));
++	dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
++		 RREG32(mmCP_RB0_WPTR));
++	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
++		 RREG32(mmCP_RB0_RPTR_ADDR));
++	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
++		 RREG32(mmCP_RB0_RPTR_ADDR_HI));
++	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
++		 RREG32(mmCP_RB0_CNTL));
++	dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
++		 RREG32(mmCP_RB0_BASE));
++	dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
++		 RREG32(mmCP_RB0_BASE_HI));
++	dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
++		 RREG32(mmCP_MEC_CNTL));
++	dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
++		 RREG32(mmCP_CPF_DEBUG));
++
++	dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
++		 RREG32(mmSCRATCH_ADDR));
++	dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
++		 RREG32(mmSCRATCH_UMSK));
++
++	dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
++		 RREG32(mmCP_INT_CNTL_RING0));
++	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTL));
++	dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
++		 RREG32(mmRLC_CNTL));
++	dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
++		 RREG32(mmRLC_CGCG_CGLS_CTRL));
++	dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTR_INIT));
++	dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTR_MAX));
++	dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
++		 RREG32(mmRLC_LB_INIT_CU_MASK));
++	dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
++		 RREG32(mmRLC_LB_PARAMS));
++	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
++		 RREG32(mmRLC_LB_CNTL));
++	dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
++		 RREG32(mmRLC_MC_CNTL));
++	dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
++		 RREG32(mmRLC_UCODE_CNTL));
++
++	mutex_lock(&adev->srbm_mutex);
++	for (i = 0; i < 16; i++) {
++		vi_srbm_select(adev, 0, 0, 0, i);
++		dev_info(adev->dev, "  VM %d:\n", i);
++		dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
++			 RREG32(mmSH_MEM_CONFIG));
++		dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
++			 RREG32(mmSH_MEM_APE1_BASE));
++		dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
++			 RREG32(mmSH_MEM_APE1_LIMIT));
++		dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
++			 RREG32(mmSH_MEM_BASES));
++	}
++	vi_srbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++}
++
++static int gfx_v8_0_soft_reset(struct amdgpu_device *adev)
++{
++	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
++	u32 tmp;
++
++	/* GRBM_STATUS */
++	tmp = RREG32(mmGRBM_STATUS);
++	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
++		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
++		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
++		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
++		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
++		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
++		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
++						GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
++		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
++						GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
++	}
++
++	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
++		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
++						GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
++						SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
++	}
++
++	/* GRBM_STATUS2 */
++	tmp = RREG32(mmGRBM_STATUS2);
++	if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
++		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
++						GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
++
++	/* SRBM_STATUS */
++	tmp = RREG32(mmSRBM_STATUS);
++	if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
++						SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
++
++	if (grbm_soft_reset || srbm_soft_reset) {
++		gfx_v8_0_print_status(adev);
++		/* stop the rlc */
++		gfx_v8_0_rlc_stop(adev);
++
++		/* Disable GFX parsing/prefetching */
++		gfx_v8_0_cp_gfx_enable(adev, false);
++
++		/* Disable MEC parsing/prefetching */
++		/* XXX todo */
++
++		if (grbm_soft_reset) {
++			tmp = RREG32(mmGRBM_SOFT_RESET);
++			tmp |= grbm_soft_reset;
++			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
++			WREG32(mmGRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmGRBM_SOFT_RESET);
++
++			udelay(50);
++
++			tmp &= ~grbm_soft_reset;
++			WREG32(mmGRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmGRBM_SOFT_RESET);
++		}
++
++		if (srbm_soft_reset) {
++			tmp = RREG32(mmSRBM_SOFT_RESET);
++			tmp |= srbm_soft_reset;
++			dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++			WREG32(mmSRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmSRBM_SOFT_RESET);
++
++			udelay(50);
++
++			tmp &= ~srbm_soft_reset;
++			WREG32(mmSRBM_SOFT_RESET, tmp);
++			tmp = RREG32(mmSRBM_SOFT_RESET);
++		}
++		/* Wait a little for things to settle down */
++		udelay(50);
++		gfx_v8_0_print_status(adev);
++	}
++	return 0;
++}
++
++/**
++ * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Fetches a GPU clock counter snapshot.
++ * Returns the 64 bit clock counter snapshot.
++ */
++uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
++{
++	uint64_t clock;
++
++	mutex_lock(&adev->gfx.gpu_clock_mutex);
++	WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
++	clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
++		((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++	mutex_unlock(&adev->gfx.gpu_clock_mutex);
++	return clock;
++}
++
++static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
++					  uint32_t vmid,
++					  uint32_t gds_base, uint32_t gds_size,
++					  uint32_t gws_base, uint32_t gws_size,
++					  uint32_t oa_base, uint32_t oa_size)
++{
++	gds_base = gds_base >> AMDGPU_GDS_SHIFT;
++	gds_size = gds_size >> AMDGPU_GDS_SHIFT;
++
++	gws_base = gws_base >> AMDGPU_GWS_SHIFT;
++	gws_size = gws_size >> AMDGPU_GWS_SHIFT;
++
++	oa_base = oa_base >> AMDGPU_OA_SHIFT;
++	oa_size = oa_size >> AMDGPU_OA_SHIFT;
++
++	/* GDS Base */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, gds_base);
++
++	/* GDS Size */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, gds_size);
++
++	/* GWS */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
++
++	/* OA */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
++}
++
++static int gfx_v8_0_early_init(struct amdgpu_device *adev)
++{
++
++	adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
++	adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
++	gfx_v8_0_set_ring_funcs(adev);
++	gfx_v8_0_set_irq_funcs(adev);
++	gfx_v8_0_set_gds_init(adev);
++
++	return 0;
++}
++
++static int gfx_v8_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++static int gfx_v8_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
++{
++	u32 rptr;
++
++	rptr = ring->adev->wb.wb[ring->rptr_offs];
++
++	return rptr;
++}
++
++static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u32 wptr;
++
++	if (ring->use_doorbell)
++		/* XXX check if swapping is necessary on BE */
++		wptr = ring->adev->wb.wb[ring->wptr_offs];
++	else
++		wptr = RREG32(mmCP_RB0_WPTR);
++
++	return wptr;
++}
++
++static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring->use_doorbell) {
++		/* XXX check if swapping is necessary on BE */
++		adev->wb.wb[ring->wptr_offs] = ring->wptr;
++		WDOORBELL32(ring->doorbell_index, ring->wptr);
++	} else {
++		WREG32(mmCP_RB0_WPTR, ring->wptr);
++		(void)RREG32(mmCP_RB0_WPTR);
++	}
++}
++
++static void gfx_v8_0_hdp_flush_cp_ring_emit(struct amdgpu_ring *ring)
++{
++	u32 ref_and_mask, reg_mem_engine;
++
++	if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
++		switch (ring->me) {
++		case 1:
++			ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
++			break;
++		case 2:
++			ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
++			break;
++		default:
++			return;
++		}
++		reg_mem_engine = 0;
++	} else {
++		ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
++		reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
++	}
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
++	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
++				 WAIT_REG_MEM_FUNCTION(3) |  /* == */
++				 reg_mem_engine));
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
++	amdgpu_ring_write(ring, ref_and_mask);
++	amdgpu_ring_write(ring, ref_and_mask);
++	amdgpu_ring_write(ring, 0x20); /* poll interval */
++}
++
++static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
++				  struct amdgpu_ib *ib)
++{
++	u32 header, control = 0;
++	u32 next_rptr = ring->wptr + 5;
++	if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
++		control |= INDIRECT_BUFFER_VALID;
++
++	if (ib->flush_hdp_writefifo)
++		next_rptr += 7;
++
++	if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
++		next_rptr += 2;
++
++	next_rptr += 4;
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
++	amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, next_rptr);
++
++	if (ib->flush_hdp_writefifo)
++		gfx_v8_0_hdp_flush_cp_ring_emit(ring);
++
++	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
++	if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
++		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
++		amdgpu_ring_write(ring, 0);
++		ring->need_ctx_switch = false;
++	}
++
++	if (ib->is_const_ib)
++		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
++	else
++		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
++
++	control |= ib->length_dw |
++		(ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
++
++	amdgpu_ring_write(ring, header);
++	amdgpu_ring_write(ring,
++#ifdef __BIG_ENDIAN
++			  (2 << 0) |
++#endif
++			  (ib->gpu_addr & 0xFFFFFFFC));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
++	amdgpu_ring_write(ring, control);
++}
++
++static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
++					 u64 seq, bool write64bit)
++{
++	/* EVENT_WRITE_EOP - flush caches, send int */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
++	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++				 EOP_TC_ACTION_EN |
++				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++				 EVENT_INDEX(5)));
++	amdgpu_ring_write(ring, addr & 0xfffffffc);
++	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 
++			  DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++	amdgpu_ring_write(ring, upper_32_bits(seq));
++}
++
++/**
++ * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
++ *
++ * @ring: amdgpu ring buffer object
++ * @semaphore: amdgpu semaphore object
++ * @emit_wait: Is this a sempahore wait?
++ *
++ * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
++ * from running ahead of semaphore waits.
++ */
++static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
++					 struct amdgpu_semaphore *semaphore,
++					 bool emit_wait)
++{
++	uint64_t addr = semaphore->gpu_addr;
++	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
++
++	if (ring->adev->asic_type == CHIP_TOPAZ ||
++	    ring->adev->asic_type == CHIP_TONGA) {
++		amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
++		amdgpu_ring_write(ring, lower_32_bits(addr));
++		amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
++	} else {
++		amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
++		amdgpu_ring_write(ring, lower_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(addr));
++		amdgpu_ring_write(ring, sel);
++	}
++
++	if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
++		/* Prevent the PFP from running ahead of the semaphore wait */
++		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
++		amdgpu_ring_write(ring, 0x0);
++	}
++
++	return true;
++}
++
++static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
++
++	/* instruct DE to set a magic number */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++							 WRITE_DATA_DST_SEL(5)));
++	amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 1);
++
++	/* let CE wait till condition satisfied */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
++	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
++							 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
++							 WAIT_REG_MEM_FUNCTION(3) |  /* == */
++							 WAIT_REG_MEM_ENGINE(2)));   /* ce */
++	amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 1);
++	amdgpu_ring_write(ring, 0xffffffff);
++	amdgpu_ring_write(ring, 4); /* poll interval */
++
++	/* instruct CE to reset wb of ce_sync to zero */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
++							 WRITE_DATA_DST_SEL(5) |
++							 WR_CONFIRM));
++	amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
++	amdgpu_ring_write(ring, 0);
++}
++
++static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
++					unsigned vm_id, uint64_t pd_addr)
++{
++	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
++	u32 srbm_gfx_cntl = 0;
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
++				 WRITE_DATA_DST_SEL(0)));
++	if (vm_id < 8) {
++		amdgpu_ring_write(ring,
++				  (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
++	} else {
++		amdgpu_ring_write(ring,
++				  (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
++	}
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, pd_addr >> 12);
++
++	/* update SH_MEM_* regs */
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, srbm_gfx_cntl);
++
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmSH_MEM_BASES);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
++	amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
++	amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
++	amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
++
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, srbm_gfx_cntl);
++
++
++	/* bits 0-15 are the VM contexts0-15 */
++	/* invalidate the cache */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
++	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
++				 WRITE_DATA_DST_SEL(0)));
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 1 << vm_id);
++
++	/* wait for the invalidate to complete */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
++	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
++				 WAIT_REG_MEM_FUNCTION(0) |  /* always */
++				 WAIT_REG_MEM_ENGINE(0))); /* me */
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0); /* ref */
++	amdgpu_ring_write(ring, 0); /* mask */
++	amdgpu_ring_write(ring, 0x20); /* poll interval */
++
++	/* compute doesn't have PFP */
++	if (usepfp) {
++		/* sync PFP to ME, otherwise we might get invalid PFP reads */
++		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
++		amdgpu_ring_write(ring, 0x0);
++
++		/* synce CE with ME to prevent CE fetch CEIB before context switch done */
++		gfx_v8_0_ce_sync_me(ring);
++	}
++}
++
++static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
++{
++	if (gfx_v8_0_is_idle(ring->adev)) {
++		amdgpu_ring_lockup_update(ring);
++		return false;
++	}
++	return amdgpu_ring_test_lockup(ring);
++}
++
++static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
++{
++	return ring->adev->wb.wb[ring->rptr_offs];
++}
++
++static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
++{
++	return ring->adev->wb.wb[ring->wptr_offs];
++}
++
++static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	/* XXX check if swapping is necessary on BE */
++	adev->wb.wb[ring->wptr_offs] = ring->wptr;
++	WDOORBELL32(ring->doorbell_index, ring->wptr);
++}
++
++static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
++					     u64 addr, u64 seq,
++					     bool write64bits)
++{
++	/* RELEASE_MEM - flush caches, send int */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
++	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++				 EOP_TC_ACTION_EN |
++				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++				 EVENT_INDEX(5)));
++	amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2));
++	amdgpu_ring_write(ring, addr & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++	amdgpu_ring_write(ring, upper_32_bits(seq));
++}
++
++static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
++						 enum amdgpu_interrupt_state state)
++{
++	u32 cp_int_cntl;
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
++					    TIME_STAMP_INT_ENABLE, 0);
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl =
++			REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
++				      TIME_STAMP_INT_ENABLE, 1);
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	default:
++		break;
++	}
++}
++
++static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
++						     int me, int pipe,
++						     enum amdgpu_interrupt_state state)
++{
++	u32 mec_int_cntl, mec_int_cntl_reg;
++
++	/*
++	 * amdgpu controls only pipe 0 of MEC1. That's why this function only
++	 * handles the setting of interrupts for this specific pipe. All other
++	 * pipes' interrupts are set by amdkfd.
++	 */
++
++	if (me == 1) {
++		switch (pipe) {
++		case 0:
++			mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
++			break;
++		default:
++			DRM_DEBUG("invalid pipe %d\n", pipe);
++			return;
++		}
++	} else {
++		DRM_DEBUG("invalid me %d\n", me);
++		return;
++	}
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		mec_int_cntl = RREG32(mec_int_cntl_reg);
++		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
++					     TIME_STAMP_INT_ENABLE, 0);
++		WREG32(mec_int_cntl_reg, mec_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		mec_int_cntl = RREG32(mec_int_cntl_reg);
++		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
++					     TIME_STAMP_INT_ENABLE, 1);
++		WREG32(mec_int_cntl_reg, mec_int_cntl);
++		break;
++	default:
++		break;
++	}
++}
++
++static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
++					     struct amdgpu_irq_src *source,
++					     unsigned type,
++					     enum amdgpu_interrupt_state state)
++{
++	u32 cp_int_cntl;
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
++					    PRIV_REG_INT_ENABLE, 0);
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
++					    PRIV_REG_INT_ENABLE, 0);
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
++					      struct amdgpu_irq_src *source,
++					      unsigned type,
++					      enum amdgpu_interrupt_state state)
++{
++	u32 cp_int_cntl;
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
++					    PRIV_INSTR_INT_ENABLE, 0);
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
++		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
++					    PRIV_INSTR_INT_ENABLE, 1);
++		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
++					    struct amdgpu_irq_src *src,
++					    unsigned type,
++					    enum amdgpu_interrupt_state state)
++{
++	switch (type) {
++	case AMDGPU_CP_IRQ_GFX_EOP:
++		gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
++		break;
++	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
++		gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
++			    struct amdgpu_irq_src *source,
++			    struct amdgpu_iv_entry *entry)
++{
++	int i;
++	u8 me_id, pipe_id, queue_id;
++	struct amdgpu_ring *ring;
++
++	DRM_DEBUG("IH: CP EOP\n");
++	me_id = (entry->ring_id & 0x0c) >> 2;
++	pipe_id = (entry->ring_id & 0x03) >> 0;
++	queue_id = (entry->ring_id & 0x70) >> 4;
++
++	switch (me_id) {
++	case 0:
++		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
++		break;
++	case 1:
++	case 2:
++		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
++			ring = &adev->gfx.compute_ring[i];
++			/* Per-queue interrupt is supported for MEC starting from VI.
++			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
++			  */
++			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
++				amdgpu_fence_process(ring);
++		}
++		break;
++	}
++	return 0;
++}
++
++static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
++				 struct amdgpu_irq_src *source,
++				 struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal register access in command stream\n");
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
++				  struct amdgpu_irq_src *source,
++				  struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal instruction in command stream\n");
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs = {
++	.early_init = gfx_v8_0_early_init,
++	.late_init = NULL,
++	.sw_init = gfx_v8_0_sw_init,
++	.sw_fini = gfx_v8_0_sw_fini,
++	.hw_init = gfx_v8_0_hw_init,
++	.hw_fini = gfx_v8_0_hw_fini,
++	.suspend = gfx_v8_0_suspend,
++	.resume = gfx_v8_0_resume,
++	.is_idle = gfx_v8_0_is_idle,
++	.wait_for_idle = gfx_v8_0_wait_for_idle,
++	.soft_reset = gfx_v8_0_soft_reset,
++	.print_status = gfx_v8_0_print_status,
++	.set_clockgating_state = gfx_v8_0_set_clockgating_state,
++	.set_powergating_state = gfx_v8_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
++	.get_rptr = gfx_v8_0_ring_get_rptr_gfx,
++	.get_wptr = gfx_v8_0_ring_get_wptr_gfx,
++	.set_wptr = gfx_v8_0_ring_set_wptr_gfx,
++	.parse_cs = NULL,
++	.emit_ib = gfx_v8_0_ring_emit_ib,
++	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
++	.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
++	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
++	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
++	.test_ring = gfx_v8_0_ring_test_ring,
++	.test_ib = gfx_v8_0_ring_test_ib,
++	.is_lockup = gfx_v8_0_ring_is_lockup,
++};
++
++static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
++	.get_rptr = gfx_v8_0_ring_get_rptr_compute,
++	.get_wptr = gfx_v8_0_ring_get_wptr_compute,
++	.set_wptr = gfx_v8_0_ring_set_wptr_compute,
++	.parse_cs = NULL,
++	.emit_ib = gfx_v8_0_ring_emit_ib,
++	.emit_fence = gfx_v8_0_ring_emit_fence_compute,
++	.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
++	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
++	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
++	.test_ring = gfx_v8_0_ring_test_ring,
++	.test_ib = gfx_v8_0_ring_test_ib,
++	.is_lockup = gfx_v8_0_ring_is_lockup,
++};
++
++static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
++		adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
++
++	for (i = 0; i < adev->gfx.num_compute_rings; i++)
++		adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
++}
++
++static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
++	.set = gfx_v8_0_set_eop_interrupt_state,
++	.process = gfx_v8_0_eop_irq,
++};
++
++static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
++	.set = gfx_v8_0_set_priv_reg_fault_state,
++	.process = gfx_v8_0_priv_reg_irq,
++};
++
++static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
++	.set = gfx_v8_0_set_priv_inst_fault_state,
++	.process = gfx_v8_0_priv_inst_irq,
++};
++
++static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
++	adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
++
++	adev->gfx.priv_reg_irq.num_types = 1;
++	adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
++
++	adev->gfx.priv_inst_irq.num_types = 1;
++	adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
++}
++
++static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
++{
++	/* init asci gds info */
++	adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
++	adev->gds.gws.total_size = 64;
++	adev->gds.oa.total_size = 16;
++
++	if (adev->gds.mem.total_size == 64 * 1024) {
++		adev->gds.mem.gfx_partition_size = 4096;
++		adev->gds.mem.cs_partition_size = 4096;
++
++		adev->gds.gws.gfx_partition_size = 4;
++		adev->gds.gws.cs_partition_size = 4;
++
++		adev->gds.oa.gfx_partition_size = 4;
++		adev->gds.oa.cs_partition_size = 1;
++	} else {
++		adev->gds.mem.gfx_partition_size = 1024;
++		adev->gds.mem.cs_partition_size = 1024;
++
++		adev->gds.gws.gfx_partition_size = 16;
++		adev->gds.gws.cs_partition_size = 16;
++
++		adev->gds.oa.gfx_partition_size = 4;
++		adev->gds.oa.cs_partition_size = 4;
++	}
++}
++
++static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
++		u32 se, u32 sh)
++{
++	u32 mask = 0, tmp, tmp1;
++	int i;
++
++	gfx_v8_0_select_se_sh(adev, se, sh);
++	tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
++	tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
++	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++
++	tmp &= 0xffff0000;
++
++	tmp |= tmp1;
++	tmp >>= 16;
++
++	for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
++		mask <<= 1;
++		mask |= 1;
++	}
++
++	return (~tmp) & mask;
++}
++
++int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
++						 struct amdgpu_cu_info *cu_info)
++{
++	int i, j, k, counter, active_cu_number = 0;
++	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
++
++	if (!adev || !cu_info)
++		return -EINVAL;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
++		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
++			mask = 1;
++			ao_bitmap = 0;
++			counter = 0;
++			bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
++			cu_info->bitmap[i][j] = bitmap;
++
++			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
++				if (bitmap & mask) {
++					if (counter < 2)
++						ao_bitmap |= mask;
++					counter ++;
++				}
++				mask <<= 1;
++			}
++			active_cu_number += counter;
++			ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
++		}
++	}
++
++	cu_info->number = active_cu_number;
++	cu_info->ao_cu_mask = ao_cu_mask;
++	mutex_unlock(&adev->grbm_idx_mutex);
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
+new file mode 100644
+index 0000000..be8a5f8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __GFX_V8_0_H__
++#define __GFX_V8_0_H__
++
++extern const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs;
++
++uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev);
++void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
++int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+new file mode 100644
+index 0000000..ac8cff8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -0,0 +1,1271 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "gmc_v8_0.h"
++#include "amdgpu_ucode.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++
++#include "vid.h"
++#include "vi.h"
++
++static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
++static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
++
++MODULE_FIRMWARE("radeon/topaz_mc.bin");
++MODULE_FIRMWARE("radeon/tonga_mc.bin");
++
++static const u32 golden_settings_tonga_a11[] =
++{
++	mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
++	mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
++	mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
++	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++};
++
++static const u32 tonga_mgcg_cgcg_init[] =
++{
++	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
++};
++
++static const u32 golden_settings_iceland_a11[] =
++{
++	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
++	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
++};
++
++static const u32 iceland_mgcg_cgcg_init[] =
++{
++	mmMC_MEM_POWER_LS, 0xffffffff,        0x00000104
++};
++
++static const u32 cz_mgcg_cgcg_init[] =
++{
++	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
++};
++
++static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		amdgpu_program_register_sequence(adev,
++						 iceland_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_iceland_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
++		break;
++	case CHIP_TONGA:
++		amdgpu_program_register_sequence(adev,
++						 tonga_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_tonga_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
++		break;
++	case CHIP_CARRIZO:
++		amdgpu_program_register_sequence(adev,
++						 cz_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
++		break;
++	default:
++		break;
++	}
++}
++
++/**
++ * gmc8_mc_wait_for_idle - wait for MC idle callback.
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Wait for the MC (memory controller) to be idle.
++ * (evergreen+).
++ * Returns 0 if the MC is idle, -1 if not.
++ */
++int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
++					       SRBM_STATUS__MCB_BUSY_MASK |
++					       SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++					       SRBM_STATUS__MCC_BUSY_MASK |
++					       SRBM_STATUS__MCD_BUSY_MASK |
++					       SRBM_STATUS__VMC1_BUSY_MASK);
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -1;
++}
++
++void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
++		      struct amdgpu_mode_mc_save *save)
++{
++	u32 blackout;
++
++	if (adev->mode_info.num_crtc)
++		amdgpu_display_stop_mc_access(adev, save);
++
++	amdgpu_asic_wait_for_mc_idle(adev);
++
++	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
++	if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
++		/* Block CPU access */
++		WREG32(mmBIF_FB_EN, 0);
++		/* blackout the MC */
++		blackout = REG_SET_FIELD(blackout,
++					 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
++		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
++	}
++	/* wait for the MC to settle */
++	udelay(100);
++}
++
++void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
++			struct amdgpu_mode_mc_save *save)
++{
++	u32 tmp;
++
++	/* unblackout the MC */
++	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
++	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
++	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
++	/* allow CPU access */
++	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
++	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
++	WREG32(mmBIF_FB_EN, tmp);
++
++	if (adev->mode_info.num_crtc)
++		amdgpu_display_resume_mc_access(adev, save);
++}
++
++/**
++ * gmc_v8_0_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		chip_name = "topaz";
++		break;
++	case CHIP_TONGA:
++		chip_name = "tonga";
++		break;
++	case CHIP_CARRIZO:
++		return 0;
++	default: BUG();
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
++	err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->mc.fw);
++
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "mc: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		release_firmware(adev->mc.fw);
++		adev->mc.fw = NULL;
++	}
++	return err;
++}
++
++/**
++ * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Load the GDDR MC ucode into the hw (CIK).
++ * Returns 0 on success, error on failure.
++ */
++static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
++{
++	const struct mc_firmware_header_v1_0 *hdr;
++	const __le32 *fw_data = NULL;
++	const __le32 *io_mc_regs = NULL;
++	u32 running, blackout = 0;
++	int i, ucode_size, regs_size;
++
++	if (!adev->mc.fw)
++		return -EINVAL;
++
++	hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
++	amdgpu_ucode_print_mc_hdr(&hdr->header);
++
++	adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
++	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
++	io_mc_regs = (const __le32 *)
++		(adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
++	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++	fw_data = (const __le32 *)
++		(adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++
++	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
++
++	if (running == 0) {
++		if (running) {
++			blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
++			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
++		}
++
++		/* reset the engine and set to writable */
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
++
++		/* load mc io regs */
++		for (i = 0; i < regs_size; i++) {
++			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
++			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
++		}
++		/* load the MC ucode */
++		for (i = 0; i < ucode_size; i++)
++			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
++
++		/* put the engine back into the active state */
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
++		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
++
++		/* wait for training to complete */
++		for (i = 0; i < adev->usec_timeout; i++) {
++			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
++					  MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
++				break;
++			udelay(1);
++		}
++		for (i = 0; i < adev->usec_timeout; i++) {
++			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
++					  MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
++				break;
++			udelay(1);
++		}
++
++		if (running)
++			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
++	}
++
++	return 0;
++}
++
++static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
++				       struct amdgpu_mc *mc)
++{
++	if (mc->mc_vram_size > 0xFFC0000000ULL) {
++		/* leave room for at least 1024M GTT */
++		dev_warn(adev->dev, "limiting VRAM\n");
++		mc->real_vram_size = 0xFFC0000000ULL;
++		mc->mc_vram_size = 0xFFC0000000ULL;
++	}
++	amdgpu_vram_location(adev, &adev->mc, 0);
++	adev->mc.gtt_base_align = 0;
++	amdgpu_gtt_location(adev, mc);
++}
++
++/**
++ * gmc_v8_0_mc_program - program the GPU memory controller
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set the location of vram, gart, and AGP in the GPU's
++ * physical address space (CIK).
++ */
++static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 tmp;
++	int i, j;
++
++	/* Initialize HDP */
++	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
++		WREG32((0xb05 + j), 0x00000000);
++		WREG32((0xb06 + j), 0x00000000);
++		WREG32((0xb07 + j), 0x00000000);
++		WREG32((0xb08 + j), 0x00000000);
++		WREG32((0xb09 + j), 0x00000000);
++	}
++	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
++
++	if (adev->mode_info.num_crtc)
++		amdgpu_display_set_vga_render_state(adev, false);
++
++	gmc_v8_0_mc_stop(adev, &save);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
++	}
++	/* Update configuration */
++	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
++	       adev->mc.vram_start >> 12);
++	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
++	       adev->mc.vram_end >> 12);
++	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
++	       adev->vram_scratch.gpu_addr >> 12);
++	tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
++	tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
++	WREG32(mmMC_VM_FB_LOCATION, tmp);
++	/* XXX double check these! */
++	WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
++	WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
++	WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
++	WREG32(mmMC_VM_AGP_BASE, 0);
++	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
++	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
++	}
++	gmc_v8_0_mc_resume(adev, &save);
++
++	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
++
++	tmp = RREG32(mmHDP_MISC_CNTL);
++	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
++	WREG32(mmHDP_MISC_CNTL, tmp);
++
++	tmp = RREG32(mmHDP_HOST_PATH_CNTL);
++	WREG32(mmHDP_HOST_PATH_CNTL, tmp);
++}
++
++/**
++ * gmc_v8_0_mc_init - initialize the memory controller driver params
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up the amount of vram, vram width, and decide how to place
++ * vram and gart within the GPU's physical address space (CIK).
++ * Returns 0 for success.
++ */
++static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
++{
++	u32 tmp;
++	int chansize, numchan;
++
++	/* Get VRAM informations */
++	tmp = RREG32(mmMC_ARB_RAMCFG);
++	if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
++		chansize = 64;
++	} else {
++		chansize = 32;
++	}
++	tmp = RREG32(mmMC_SHARED_CHMAP);
++	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
++	case 0:
++	default:
++		numchan = 1;
++		break;
++	case 1:
++		numchan = 2;
++		break;
++	case 2:
++		numchan = 4;
++		break;
++	case 3:
++		numchan = 8;
++		break;
++	case 4:
++		numchan = 3;
++		break;
++	case 5:
++		numchan = 6;
++		break;
++	case 6:
++		numchan = 10;
++		break;
++	case 7:
++		numchan = 12;
++		break;
++	case 8:
++		numchan = 16;
++		break;
++	}
++	adev->mc.vram_width = numchan * chansize;
++	/* Could aper size report 0 ? */
++	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
++	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
++	/* size in MB on si */
++	adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
++	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
++	adev->mc.visible_vram_size = adev->mc.aper_size;
++
++	/* unless the user had overridden it, set the gart
++	 * size equal to the 1024 or vram, whichever is larger.
++	 */
++	if (amdgpu_gart_size == -1)
++		adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
++	else
++		adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
++
++	gmc_v8_0_vram_gtt_location(adev, &adev->mc);
++
++	return 0;
++}
++
++/*
++ * GART
++ * VMID 0 is the physical GPU addresses as used by the kernel.
++ * VMIDs 1-15 are used for userspace clients and are handled
++ * by the amdgpu vm/hsa code.
++ */
++
++/**
++ * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
++ *
++ * @adev: amdgpu_device pointer
++ * @vmid: vm instance to flush
++ *
++ * Flush the TLB for the requested page table (CIK).
++ */
++static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
++					uint32_t vmid)
++{
++	/* flush hdp cache */
++	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++
++	/* bits 0-15 are the VM contexts0-15 */
++	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
++}
++
++/**
++ * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
++ *
++ * @adev: amdgpu_device pointer
++ * @cpu_pt_addr: cpu address of the page table
++ * @gpu_page_idx: entry in the page table to update
++ * @addr: dst addr to write into pte/pde
++ * @flags: access flags
++ *
++ * Update the page tables using the CPU.
++ */
++static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
++				     void *cpu_pt_addr,
++				     uint32_t gpu_page_idx,
++				     uint64_t addr,
++				     uint32_t flags)
++{
++	void __iomem *ptr = (void *)cpu_pt_addr;
++	uint64_t value;
++
++	/*
++	 * PTE format on VI:
++	 * 63:40 reserved
++	 * 39:12 4k physical page base address
++	 * 11:7 fragment
++	 * 6 write
++	 * 5 read
++	 * 4 exe
++	 * 3 reserved
++	 * 2 snooped
++	 * 1 system
++	 * 0 valid
++	 *
++	 * PDE format on VI:
++	 * 63:59 block fragment size
++	 * 58:40 reserved
++	 * 39:1 physical base address of PTE
++	 * bits 5:1 must be 0.
++	 * 0 valid
++	 */
++	value = addr & 0x000000FFFFFFF000ULL;
++	value |= flags;
++	writeq(value, ptr + (gpu_page_idx * 8));
++
++	return 0;
++}
++
++/**
++ * gmc_v8_0_gart_enable - gart enable
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * This sets up the TLBs, programs the page tables for VMID0,
++ * sets up the hw for VMIDs 1-15 which are allocated on
++ * demand, and sets up the global locations for the LDS, GDS,
++ * and GPUVM for FSA64 clients (CIK).
++ * Returns 0 for success, errors for failure.
++ */
++static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
++{
++	int r, i;
++	u32 tmp;
++
++	if (adev->gart.robj == NULL) {
++		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
++		return -EINVAL;
++	}
++	r = amdgpu_gart_table_vram_pin(adev);
++	if (r)
++		return r;
++	/* Setup TLB control */
++	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
++	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
++	/* Setup L2 cache */
++	tmp = RREG32(mmVM_L2_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
++	WREG32(mmVM_L2_CNTL, tmp);
++	tmp = RREG32(mmVM_L2_CNTL2);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
++	WREG32(mmVM_L2_CNTL2, tmp);
++	tmp = RREG32(mmVM_L2_CNTL3);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
++	WREG32(mmVM_L2_CNTL3, tmp);
++	/* XXX: set to enable PTE/PDE in system memory */
++	tmp = RREG32(mmVM_L2_CNTL4);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
++	WREG32(mmVM_L2_CNTL4, tmp);
++	/* setup context0 */
++	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
++	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
++	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
++	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
++			(u32)(adev->dummy_page.addr >> 12));
++	WREG32(mmVM_CONTEXT0_CNTL2, 0);
++	tmp = RREG32(mmVM_CONTEXT0_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	WREG32(mmVM_CONTEXT0_CNTL, tmp);
++
++	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
++	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
++	WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
++
++	/* empty context1-15 */
++	/* FIXME start with 4G, once using 2 level pt switch to full
++	 * vm size space
++	 */
++	/* set vm size, must be a multiple of 4 */
++	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
++	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn);
++	for (i = 1; i < 16; i++) {
++		if (i < 8)
++			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
++			       adev->gart.table_addr >> 12);
++		else
++			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
++			       adev->gart.table_addr >> 12);
++	}
++
++	/* enable context1-15 */
++	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
++	       (u32)(adev->dummy_page.addr >> 12));
++	WREG32(mmVM_CONTEXT1_CNTL2, 4);
++	tmp = RREG32(mmVM_CONTEXT1_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
++			    amdgpu_vm_block_size - 9);
++	WREG32(mmVM_CONTEXT1_CNTL, tmp);
++
++	gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
++	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
++		 (unsigned)(adev->mc.gtt_size >> 20),
++		 (unsigned long long)adev->gart.table_addr);
++	adev->gart.ready = true;
++	return 0;
++}
++
++static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->gart.robj) {
++		WARN(1, "R600 PCIE GART already initialized\n");
++		return 0;
++	}
++	/* Initialize common gart structure */
++	r = amdgpu_gart_init(adev);
++	if (r)
++		return r;
++	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
++	return amdgpu_gart_table_vram_alloc(adev);
++}
++
++/**
++ * gmc_v8_0_gart_disable - gart disable
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * This disables all VM page table (CIK).
++ */
++static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
++{
++	u32 tmp;
++
++	/* Disable all tables */
++	WREG32(mmVM_CONTEXT0_CNTL, 0);
++	WREG32(mmVM_CONTEXT1_CNTL, 0);
++	/* Setup TLB control */
++	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
++	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
++	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
++	/* Setup L2 cache */
++	tmp = RREG32(mmVM_L2_CNTL);
++	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
++	WREG32(mmVM_L2_CNTL, tmp);
++	WREG32(mmVM_L2_CNTL2, 0);
++	amdgpu_gart_table_vram_unpin(adev);
++}
++
++/**
++ * gmc_v8_0_gart_fini - vm fini callback
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tears down the driver GART/VM setup (CIK).
++ */
++static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
++{
++	amdgpu_gart_table_vram_free(adev);
++	amdgpu_gart_fini(adev);
++}
++
++/*
++ * vm
++ * VMID 0 is the physical GPU addresses as used by the kernel.
++ * VMIDs 1-15 are used for userspace clients and are handled
++ * by the amdgpu vm/hsa code.
++ */
++/**
++ * gmc_v8_0_vm_init - cik vm init callback
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Inits cik specific vm parameters (number of VMs, base of vram for
++ * VMIDs 1-15) (CIK).
++ * Returns 0 for success.
++ */
++static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
++{
++	/*
++	 * number of VMs
++	 * VMID 0 is reserved for System
++	 * amdgpu graphics/compute will use VMIDs 1-7
++	 * amdkfd will use VMIDs 8-15
++	 */
++	adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
++
++	/* base offset of vram pages */
++	if (adev->flags & AMDGPU_IS_APU) {
++		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
++		tmp <<= 22;
++		adev->vm_manager.vram_base_offset = tmp;
++	} else
++		adev->vm_manager.vram_base_offset = 0;
++
++	return 0;
++}
++
++/**
++ * gmc_v8_0_vm_fini - cik vm fini callback
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Tear down any asic specific VM setup (CIK).
++ */
++static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
++{
++}
++
++/**
++ * gmc_v8_0_vm_decode_fault - print human readable fault info
++ *
++ * @adev: amdgpu_device pointer
++ * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
++ * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
++ *
++ * Print human readable fault information (CIK).
++ */
++static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
++				     u32 status, u32 addr, u32 mc_client)
++{
++	u32 mc_id;
++	u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
++	u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
++					PROTECTIONS);
++	char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
++		(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
++
++	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
++			      MEMORY_CLIENT_ID);
++
++	printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
++	       protections, vmid, addr,
++	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
++			     MEMORY_CLIENT_RW) ?
++	       "write" : "read", block, mc_client, mc_id);
++}
++
++static int gmc_v8_0_early_init(struct amdgpu_device *adev)
++{
++	gmc_v8_0_set_gart_funcs(adev);
++	gmc_v8_0_set_irq_funcs(adev);
++
++	if (adev->flags & AMDGPU_IS_APU) {
++		adev->mc.is_gddr5 = false;
++	} else {
++		u32 tmp = RREG32(mmMC_SEQ_MISC0);
++
++		if (((tmp & MC_SEQ_MISC0__GDDR5_MASK) >>
++		     MC_SEQ_MISC0__GDDR5__SHIFT) == MC_SEQ_MISC0__GDDR5_VALUE)
++			adev->mc.is_gddr5 = true;
++		else
++			adev->mc.is_gddr5 = false;
++	}
++
++	return 0;
++}
++
++static int gmc_v8_0_sw_init(struct amdgpu_device *adev)
++{
++	int r;
++	int dma_bits;
++
++	r = amdgpu_gem_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
++	if (r)
++		return r;
++
++	/* Adjust VM size here.
++	 * Currently set to 4GB ((1 << 20) 4k pages).
++	 * Max GPUVM size for cayman and SI is 40 bits.
++	 */
++	adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
++
++	/* Set the internal MC address mask
++	 * This is the max address of the GPU's
++	 * internal address space.
++	 */
++	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
++
++	/* set DMA mask + need_dma32 flags.
++	 * PCIE - can handle 40-bits.
++	 * IGP - can handle 40-bits
++	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
++	 */
++	adev->need_dma32 = false;
++	dma_bits = adev->need_dma32 ? 32 : 40;
++	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
++	if (r) {
++		adev->need_dma32 = true;
++		dma_bits = 32;
++		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
++	}
++	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
++	if (r) {
++		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
++		printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
++	}
++
++	r = gmc_v8_0_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load mc firmware!\n");
++		return r;
++	}
++
++	r = gmc_v8_0_mc_init(adev);
++	if (r)
++		return r;
++
++	/* Memory manager */
++	r = amdgpu_bo_init(adev);
++	if (r)
++		return r;
++
++	r = gmc_v8_0_gart_init(adev);
++	if (r)
++		return r;
++
++	if (!adev->vm_manager.enabled) {
++		r = gmc_v8_0_vm_init(adev);
++		if (r) {
++			dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
++			return r;
++		}
++		adev->vm_manager.enabled = true;
++	}
++
++	return r;
++}
++
++static int gmc_v8_0_sw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (adev->vm_manager.enabled) {
++		for (i = 0; i < AMDGPU_NUM_VM; ++i)
++			amdgpu_fence_unref(&adev->vm_manager.active[i]);
++		gmc_v8_0_vm_fini(adev);
++		adev->vm_manager.enabled = false;
++	}
++	gmc_v8_0_gart_fini(adev);
++	amdgpu_gem_fini(adev);
++	amdgpu_bo_fini(adev);
++
++	return 0;
++}
++
++static int gmc_v8_0_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	gmc_v8_0_init_golden_registers(adev);
++
++	gmc_v8_0_mc_program(adev);
++
++	if (!(adev->flags & AMDGPU_IS_APU)) {
++		r = gmc_v8_0_mc_load_microcode(adev);
++		if (r) {
++			DRM_ERROR("Failed to load MC firmware!\n");
++			return r;
++		}
++	}
++
++	r = gmc_v8_0_gart_enable(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int gmc_v8_0_hw_fini(struct amdgpu_device *adev)
++{
++	gmc_v8_0_gart_disable(adev);
++
++	return 0;
++}
++
++static int gmc_v8_0_suspend(struct amdgpu_device *adev)
++{
++	int i;
++
++	if (adev->vm_manager.enabled) {
++		for (i = 0; i < AMDGPU_NUM_VM; ++i)
++			amdgpu_fence_unref(&adev->vm_manager.active[i]);
++		gmc_v8_0_vm_fini(adev);
++		adev->vm_manager.enabled = false;
++	}
++	gmc_v8_0_hw_fini(adev);
++
++	return 0;
++}
++
++static int gmc_v8_0_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = gmc_v8_0_hw_init(adev);
++	if (r)
++		return r;
++
++	if (!adev->vm_manager.enabled) {
++		r = gmc_v8_0_vm_init(adev);
++		if (r) {
++			dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
++			return r;
++		}
++		adev->vm_manager.enabled = true;
++	}
++
++	return r;
++}
++
++static bool gmc_v8_0_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
++		return false;
++
++	return true;
++}
++
++static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
++					       SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++					       SRBM_STATUS__MCC_BUSY_MASK |
++					       SRBM_STATUS__MCD_BUSY_MASK |
++					       SRBM_STATUS__VMC_BUSY_MASK |
++					       SRBM_STATUS__VMC1_BUSY_MASK);
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++
++}
++
++static void gmc_v8_0_print_status(struct amdgpu_device *adev)
++{
++	int i, j;
++
++	dev_info(adev->dev, "GMC 8.x registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
++	dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
++		 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
++	dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL));
++	dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL2));
++	dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL3));
++	dev_info(adev->dev, "  VM_L2_CNTL4=0x%08X\n",
++		 RREG32(mmVM_L2_CNTL4));
++	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_CNTL2));
++	dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
++		 RREG32(mmVM_CONTEXT0_CNTL));
++	dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
++		 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
++	dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
++		 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
++	dev_info(adev->dev, "  mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
++		 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
++	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_CNTL2));
++	dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_CNTL));
++	for (i = 0; i < 16; i++) {
++		if (i < 8)
++			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
++				 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
++		else
++			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
++				 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
++	}
++	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
++		 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
++	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
++		 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
++	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
++		 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
++	dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
++		 RREG32(mmMC_VM_FB_LOCATION));
++	dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
++		 RREG32(mmMC_VM_AGP_BASE));
++	dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
++		 RREG32(mmMC_VM_AGP_TOP));
++	dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
++		 RREG32(mmMC_VM_AGP_BOT));
++
++	dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
++		 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
++	dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
++		 RREG32(mmHDP_NONSURFACE_BASE));
++	dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
++		 RREG32(mmHDP_NONSURFACE_INFO));
++	dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
++		 RREG32(mmHDP_NONSURFACE_SIZE));
++	dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
++		 RREG32(mmHDP_MISC_CNTL));
++	dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
++		 RREG32(mmHDP_HOST_PATH_CNTL));
++
++	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
++		dev_info(adev->dev, "  %d:\n", i);
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb05 + j, RREG32(0xb05 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb06 + j, RREG32(0xb06 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb07 + j, RREG32(0xb07 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb08 + j, RREG32(0xb08 + j));
++		dev_info(adev->dev, "  0x%04X=0x%08X\n",
++			 0xb09 + j, RREG32(0xb09 + j));
++	}
++
++	dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
++		 RREG32(mmBIF_FB_EN));
++}
++
++static int gmc_v8_0_soft_reset(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
++						SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
++
++	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
++		if (!(adev->flags & AMDGPU_IS_APU))
++			srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
++							SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
++	}
++
++	if (srbm_soft_reset) {
++		gmc_v8_0_print_status(adev);
++
++		gmc_v8_0_mc_stop(adev, &save);
++		if (gmc_v8_0_wait_for_idle(adev)) {
++			dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
++		}
++
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		gmc_v8_0_mc_resume(adev, &save);
++		udelay(50);
++
++		gmc_v8_0_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
++					     struct amdgpu_irq_src *src,
++					     unsigned type,
++					     enum amdgpu_interrupt_state state)
++{
++	u32 tmp;
++	u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
++		    VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
++
++	switch (state) {
++	case AMDGPU_IRQ_STATE_DISABLE:
++		/* system context */
++		tmp = RREG32(mmVM_CONTEXT0_CNTL);
++		tmp &= ~bits;
++		WREG32(mmVM_CONTEXT0_CNTL, tmp);
++		/* VMs */
++		tmp = RREG32(mmVM_CONTEXT1_CNTL);
++		tmp &= ~bits;
++		WREG32(mmVM_CONTEXT1_CNTL, tmp);
++		break;
++	case AMDGPU_IRQ_STATE_ENABLE:
++		/* system context */
++		tmp = RREG32(mmVM_CONTEXT0_CNTL);
++		tmp |= bits;
++		WREG32(mmVM_CONTEXT0_CNTL, tmp);
++		/* VMs */
++		tmp = RREG32(mmVM_CONTEXT1_CNTL);
++		tmp |= bits;
++		WREG32(mmVM_CONTEXT1_CNTL, tmp);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	u32 addr, status, mc_client;
++
++	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
++	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
++	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
++	dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
++		entry->src_id, entry->src_data);
++	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
++		addr);
++	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++		status);
++	gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
++	/* reset addr and status */
++	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
++
++	return 0;
++}
++
++static int gmc_v8_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	/* XXX handled via the smc on VI */
++
++	return 0;
++}
++
++static int gmc_v8_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs = {
++	.early_init = gmc_v8_0_early_init,
++	.late_init = NULL,
++	.sw_init = gmc_v8_0_sw_init,
++	.sw_fini = gmc_v8_0_sw_fini,
++	.hw_init = gmc_v8_0_hw_init,
++	.hw_fini = gmc_v8_0_hw_fini,
++	.suspend = gmc_v8_0_suspend,
++	.resume = gmc_v8_0_resume,
++	.is_idle = gmc_v8_0_is_idle,
++	.wait_for_idle = gmc_v8_0_wait_for_idle,
++	.soft_reset = gmc_v8_0_soft_reset,
++	.print_status = gmc_v8_0_print_status,
++	.set_clockgating_state = gmc_v8_0_set_clockgating_state,
++	.set_powergating_state = gmc_v8_0_set_powergating_state,
++};
++
++static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
++	.flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
++	.set_pte_pde = gmc_v8_0_gart_set_pte_pde,
++};
++
++static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
++	.set = gmc_v8_0_vm_fault_interrupt_state,
++	.process = gmc_v8_0_process_interrupt,
++};
++
++static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
++{
++	if (adev->gart.gart_funcs == NULL)
++		adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
++}
++
++static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->mc.vm_fault.num_types = 1;
++	adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
+new file mode 100644
+index 0000000..2dd7f80
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
+@@ -0,0 +1,36 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __GMC_V8_0_H__
++#define __GMC_V8_0_H__
++
++extern const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs;
++
++/* XXX these shouldn't be exported */
++void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
++		      struct amdgpu_mode_mc_save *save);
++void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
++			struct amdgpu_mode_mc_save *save);
++int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+new file mode 100644
+index 0000000..8f5c54b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+@@ -0,0 +1,172 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "iceland_smumgr.h"
++
++MODULE_FIRMWARE("radeon/topaz_smc.bin");
++
++static void iceland_dpm_set_funcs(struct amdgpu_device *adev);
++
++static int iceland_dpm_early_init(struct amdgpu_device *adev)
++{
++	iceland_dpm_set_funcs(adev);
++
++	return 0;
++}
++
++static int iceland_dpm_init_microcode(struct amdgpu_device *adev)
++{
++	char fw_name[30] = "radeon/topaz_smc.bin";
++	int err;
++
++	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->pm.fw);
++
++out:
++	if (err) {
++		DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
++		release_firmware(adev->pm.fw);
++		adev->pm.fw = NULL;
++	}
++	return err;
++}
++
++static int iceland_dpm_sw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	ret = iceland_dpm_init_microcode(adev);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int iceland_dpm_sw_fini(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int iceland_dpm_hw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	mutex_lock(&adev->pm.mutex);
++
++	ret = iceland_smu_init(adev);
++	if (ret) {
++		DRM_ERROR("SMU initialization failed\n");
++		goto fail;
++	}
++
++	ret = iceland_smu_start(adev);
++	if (ret) {
++		DRM_ERROR("SMU start failed\n");
++		goto fail;
++	}
++
++	mutex_unlock(&adev->pm.mutex);
++	return 0;
++
++fail:
++	adev->firmware.smu_load = false;
++	mutex_unlock(&adev->pm.mutex);
++	return -EINVAL;
++}
++
++static int iceland_dpm_hw_fini(struct amdgpu_device *adev)
++{
++	mutex_lock(&adev->pm.mutex);
++	iceland_smu_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++	return 0;
++}
++
++static int iceland_dpm_suspend(struct amdgpu_device *adev)
++{
++	iceland_dpm_hw_fini(adev);
++
++	return 0;
++}
++
++static int iceland_dpm_resume(struct amdgpu_device *adev)
++{
++	iceland_dpm_hw_init(adev);
++
++	return 0;
++}
++
++static int iceland_dpm_set_clockgating_state(struct amdgpu_device *adev,
++			enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int iceland_dpm_set_powergating_state(struct amdgpu_device *adev,
++			enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs iceland_dpm_ip_funcs = {
++	.early_init = iceland_dpm_early_init,
++	.late_init = NULL,
++	.sw_init = iceland_dpm_sw_init,
++	.sw_fini = iceland_dpm_sw_fini,
++	.hw_init = iceland_dpm_hw_init,
++	.hw_fini = iceland_dpm_hw_fini,
++	.suspend = iceland_dpm_suspend,
++	.resume = iceland_dpm_resume,
++	.is_idle = NULL,
++	.wait_for_idle = NULL,
++	.soft_reset = NULL,
++	.print_status = NULL,
++	.set_clockgating_state = iceland_dpm_set_clockgating_state,
++	.set_powergating_state = iceland_dpm_set_powergating_state,
++};
++
++static const struct amdgpu_dpm_funcs iceland_dpm_funcs = {
++	.get_temperature = NULL,
++	.pre_set_power_state = NULL,
++	.set_power_state = NULL,
++	.post_set_power_state = NULL,
++	.display_configuration_changed = NULL,
++	.get_sclk = NULL,
++	.get_mclk = NULL,
++	.print_power_state = NULL,
++	.debugfs_print_current_performance_level = NULL,
++	.force_performance_level = NULL,
++	.vblank_too_short = NULL,
++	.powergate_uvd = NULL,
++};
++
++static void iceland_dpm_set_funcs(struct amdgpu_device *adev)
++{
++	if (NULL == adev->pm.funcs)
++		adev->pm.funcs = &iceland_dpm_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+new file mode 100644
+index 0000000..2de8adf
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+@@ -0,0 +1,435 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++#include "vid.h"
++
++#include "oss/oss_2_4_d.h"
++#include "oss/oss_2_4_sh_mask.h"
++
++#include "bif/bif_5_1_d.h"
++#include "bif/bif_5_1_sh_mask.h"
++
++/*
++ * Interrupts
++ * Starting with r6xx, interrupts are handled via a ring buffer.
++ * Ring buffers are areas of GPU accessible memory that the GPU
++ * writes interrupt vectors into and the host reads vectors out of.
++ * There is a rptr (read pointer) that determines where the
++ * host is currently reading, and a wptr (write pointer)
++ * which determines where the GPU has written.  When the
++ * pointers are equal, the ring is idle.  When the GPU
++ * writes vectors to the ring buffer, it increments the
++ * wptr.  When there is an interrupt, the host then starts
++ * fetching commands and processing them until the pointers are
++ * equal again at which point it updates the rptr.
++ */
++
++static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev);
++
++/**
++ * iceland_ih_enable_interrupts - Enable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Enable the interrupt ring buffer (VI).
++ */
++static void iceland_ih_enable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_cntl = RREG32(mmIH_CNTL);
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++
++	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
++	WREG32(mmIH_CNTL, ih_cntl);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	adev->irq.ih.enabled = true;
++}
++
++/**
++ * iceland_ih_disable_interrupts - Disable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable the interrupt ring buffer (VI).
++ */
++static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++	u32 ih_cntl = RREG32(mmIH_CNTL);
++
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
++	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	WREG32(mmIH_CNTL, ih_cntl);
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++	adev->irq.ih.enabled = false;
++	adev->irq.ih.rptr = 0;
++}
++
++/**
++ * iceland_ih_irq_init - init and enable the interrupt ring
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate a ring buffer for the interrupt controller,
++ * enable the RLC, disable interrupts, enable the IH
++ * ring buffer and enable it (VI).
++ * Called at device load and reume.
++ * Returns 0 for success, errors for failure.
++ */
++static int iceland_ih_irq_init(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	int rb_bufsz;
++	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
++	u64 wptr_off;
++
++	/* disable irqs */
++	iceland_ih_disable_interrupts(adev);
++
++	/* setup interrupt control */
++	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
++	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
++	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
++	 */
++	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
++	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
++	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
++	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
++
++	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
++	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
++
++	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
++	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
++
++	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
++
++	/* set the writeback address whether it's enabled or not */
++	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
++	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
++	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
++
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++
++	/* Default settings for IH_CNTL (disabled at first) */
++	ih_cntl = RREG32(mmIH_CNTL);
++	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
++
++	if (adev->irq.msi_enabled)
++		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
++	WREG32(mmIH_CNTL, ih_cntl);
++
++	pci_set_master(adev->pdev);
++
++	/* enable interrupts */
++	iceland_ih_enable_interrupts(adev);
++
++	return ret;
++}
++
++/**
++ * iceland_ih_irq_disable - disable interrupts
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable interrupts on the hw (VI).
++ */
++static void iceland_ih_irq_disable(struct amdgpu_device *adev)
++{
++	iceland_ih_disable_interrupts(adev);
++
++	/* Wait and acknowledge irq */
++	mdelay(1);
++}
++
++/**
++ * iceland_ih_get_wptr - get the IH ring buffer wptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Get the IH ring buffer wptr from either the register
++ * or the writeback memory buffer (VI).  Also check for
++ * ring buffer overflow and deal with it.
++ * Used by cz_irq_process(VI).
++ * Returns the value of the wptr.
++ */
++static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
++{
++	u32 wptr, tmp;
++
++	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
++
++	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
++		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
++		/* When a ring buffer overflow happen start parsing interrupt
++		 * from the last not overwritten vector (wptr + 16). Hopefully
++		 * this should allow us to catchup.
++		 */
++		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
++			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
++		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
++		tmp = RREG32(mmIH_RB_CNTL);
++		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
++		WREG32(mmIH_RB_CNTL, tmp);
++	}
++	return (wptr & adev->irq.ih.ptr_mask);
++}
++
++/**
++ * iceland_ih_decode_iv - decode an interrupt vector
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Decodes the interrupt vector at the current rptr
++ * position and also advance the position.
++ */
++static void iceland_ih_decode_iv(struct amdgpu_device *adev,
++				 struct amdgpu_iv_entry *entry)
++{
++	/* wptr/rptr are in bytes! */
++	u32 ring_index = adev->irq.ih.rptr >> 2;
++	uint32_t dw[4];
++
++	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
++	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
++	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
++	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
++
++	entry->src_id = dw[0] & 0xff;
++	entry->src_data = dw[1] & 0xfffffff;
++	entry->ring_id = dw[2] & 0xff;
++	entry->vm_id = (dw[2] >> 8) & 0xff;
++	entry->pas_id = (dw[2] >> 16) & 0xffff;
++
++	/* wptr/rptr are in bytes! */
++	adev->irq.ih.rptr += 16;
++}
++
++/**
++ * iceland_ih_set_rptr - set the IH ring buffer rptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set the IH ring buffer rptr.
++ */
++static void iceland_ih_set_rptr(struct amdgpu_device *adev)
++{
++	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
++}
++
++static int iceland_ih_early_init(struct amdgpu_device *adev)
++{
++	iceland_ih_set_interrupt_funcs(adev);
++	return 0;
++}
++
++static int iceland_ih_sw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_init(adev);
++
++	return r;
++}
++
++static int iceland_ih_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_irq_fini(adev);
++	amdgpu_ih_ring_fini(adev);
++
++	return 0;
++}
++
++static int iceland_ih_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = iceland_ih_irq_init(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static int iceland_ih_hw_fini(struct amdgpu_device *adev)
++{
++	iceland_ih_irq_disable(adev);
++
++	return 0;
++}
++
++static int iceland_ih_suspend(struct amdgpu_device *adev)
++{
++	return iceland_ih_hw_fini(adev);
++}
++
++static int iceland_ih_resume(struct amdgpu_device *adev)
++{
++	return iceland_ih_hw_init(adev);
++}
++
++static bool iceland_ih_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
++		return false;
++
++	return true;
++}
++
++static int iceland_ih_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS);
++		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void iceland_ih_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "ICELAND IH registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL));
++	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL2));
++	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
++		 RREG32(mmIH_CNTL));
++	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
++		 RREG32(mmIH_RB_CNTL));
++	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
++		 RREG32(mmIH_RB_BASE));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_LO));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_HI));
++	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
++		 RREG32(mmIH_RB_RPTR));
++	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR));
++}
++
++static int iceland_ih_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
++						SOFT_RESET_IH, 1);
++
++	if (srbm_soft_reset) {
++		iceland_ih_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		iceland_ih_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int iceland_ih_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	// TODO
++	return 0;
++}
++
++static int iceland_ih_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	// TODO
++	return 0;
++}
++
++const struct amdgpu_ip_funcs iceland_ih_ip_funcs = {
++	.early_init = iceland_ih_early_init,
++	.late_init = NULL,
++	.sw_init = iceland_ih_sw_init,
++	.sw_fini = iceland_ih_sw_fini,
++	.hw_init = iceland_ih_hw_init,
++	.hw_fini = iceland_ih_hw_fini,
++	.suspend = iceland_ih_suspend,
++	.resume = iceland_ih_resume,
++	.is_idle = iceland_ih_is_idle,
++	.wait_for_idle = iceland_ih_wait_for_idle,
++	.soft_reset = iceland_ih_soft_reset,
++	.print_status = iceland_ih_print_status,
++	.set_clockgating_state = iceland_ih_set_clockgating_state,
++	.set_powergating_state = iceland_ih_set_powergating_state,
++};
++
++static const struct amdgpu_ih_funcs iceland_ih_funcs = {
++	.get_wptr = iceland_ih_get_wptr,
++	.decode_iv = iceland_ih_decode_iv,
++	.set_rptr = iceland_ih_set_rptr
++};
++
++static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
++{
++	if (adev->irq.ih_funcs == NULL)
++		adev->irq.ih_funcs = &iceland_ih_funcs;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
+new file mode 100644
+index 0000000..d001895
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __ICELAND_IH_H__
++#define __ICELAND_IH_H__
++
++extern const struct amdgpu_ip_funcs iceland_ih_ip_funcs;
++
++#endif /* __ICELAND_IH_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h
+new file mode 100644
+index 0000000..c723602
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h
+@@ -0,0 +1,2167 @@
++/*
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __ICELAND_SDMA_PKT_OPEN_H_
++#define __ICELAND_SDMA_PKT_OPEN_H_
++
++#define SDMA_OP_NOP  0
++#define SDMA_OP_COPY  1
++#define SDMA_OP_WRITE  2
++#define SDMA_OP_INDIRECT  4
++#define SDMA_OP_FENCE  5
++#define SDMA_OP_TRAP  6
++#define SDMA_OP_SEM  7
++#define SDMA_OP_POLL_REGMEM  8
++#define SDMA_OP_COND_EXE  9
++#define SDMA_OP_ATOMIC  10
++#define SDMA_OP_CONST_FILL  11
++#define SDMA_OP_GEN_PTEPDE  12
++#define SDMA_OP_TIMESTAMP  13
++#define SDMA_OP_SRBM_WRITE  14
++#define SDMA_OP_PRE_EXE  15
++#define SDMA_SUBOP_TIMESTAMP_SET  0
++#define SDMA_SUBOP_TIMESTAMP_GET  1
++#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL  2
++#define SDMA_SUBOP_COPY_LINEAR  0
++#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND  4
++#define SDMA_SUBOP_COPY_TILED  1
++#define SDMA_SUBOP_COPY_TILED_SUB_WIND  5
++#define SDMA_SUBOP_COPY_T2T_SUB_WIND  6
++#define SDMA_SUBOP_COPY_SOA  3
++#define SDMA_SUBOP_WRITE_LINEAR  0
++#define SDMA_SUBOP_WRITE_TILED  1
++
++/*define for op field*/
++#define SDMA_PKT_HEADER_op_offset 0
++#define SDMA_PKT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_HEADER_op_shift  0
++#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_HEADER_sub_op_offset 0
++#define SDMA_PKT_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_HEADER_sub_op_shift  8
++#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift)
++
++/*
++** Definitions for SDMA_PKT_COPY_LINEAR packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift  0
++#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift)
++
++/*define for broadcast field*/
++#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
++#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift  27
++#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1
++#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift  0
++#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift)
++
++/*define for PARAMETER word*/
++/*define for dst_sw field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift  16
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)
++
++/*define for dst_ha field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift  22
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift  24
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)
++
++/*define for src_ha field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift  30
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift)
++
++/*define for broadcast field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift  27
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift)
++
++/*define for PARAMETER word*/
++/*define for dst2_sw field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask   0x00000003
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift  8
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift)
++
++/*define for dst2_ha field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift  14
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift)
++
++/*define for dst1_sw field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask   0x00000003
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift  16
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift)
++
++/*define for dst1_ha field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift  22
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift  24
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift)
++
++/*define for src_ha field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift  30
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DST1_ADDR_LO word*/
++/*define for dst1_addr_31_0 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift)
++
++/*define for DST1_ADDR_HI word*/
++/*define for dst1_addr_63_32 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift)
++
++/*define for DST2_ADDR_LO word*/
++/*define for dst2_addr_31_0 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift)
++
++/*define for DST2_ADDR_HI word*/
++/*define for dst2_addr_63_32 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift)
++
++/*define for elementsize field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask   0x00000007
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift  29
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for src_x field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift)
++
++/*define for src_y field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift)
++
++/*define for DW_4 word*/
++/*define for src_z field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask   0x000007FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift)
++
++/*define for src_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift)
++
++/*define for DW_5 word*/
++/*define for src_slice_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask   0x0FFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_8 word*/
++/*define for dst_x field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift)
++
++/*define for dst_y field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift)
++
++/*define for DW_9 word*/
++/*define for dst_z field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask   0x000007FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift)
++
++/*define for dst_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift)
++
++/*define for DW_10 word*/
++/*define for dst_slice_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask   0x0FFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift)
++
++/*define for DW_11 word*/
++/*define for rect_x field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift)
++
++/*define for rect_y field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift)
++
++/*define for DW_12 word*/
++/*define for rect_z field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask   0x000007FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift)
++
++/*define for dst_sw field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift)
++
++/*define for dst_ha field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift  22
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift  24
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift)
++
++/*define for src_ha field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift  30
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_TILED packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
++#define SDMA_PKT_COPY_TILED_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_HEADER_op_shift  0
++#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift)
++
++/*define for detile field*/
++#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
++#define SDMA_PKT_COPY_TILED_HEADER_detile_mask   0x00000001
++#define SDMA_PKT_COPY_TILED_HEADER_detile_shift  31
++#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift)
++
++/*define for TILED_ADDR_LO word*/
++/*define for tiled_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift)
++
++/*define for TILED_ADDR_HI word*/
++/*define for tiled_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3
++#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift  0
++#define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift)
++
++/*define for height field*/
++#define SDMA_PKT_COPY_TILED_DW_3_height_offset 3
++#define SDMA_PKT_COPY_TILED_DW_3_height_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_DW_3_height_shift  16
++#define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift)
++
++/*define for DW_4 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4
++#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift)
++
++/*define for DW_5 word*/
++/*define for element_size field*/
++#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift  0
++#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift  3
++#define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift  8
++#define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift  15
++#define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift  18
++#define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift  21
++#define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift  24
++#define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift  26
++#define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift)
++
++/*define for DW_6 word*/
++/*define for x field*/
++#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6
++#define SDMA_PKT_COPY_TILED_DW_6_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_DW_6_x_shift  0
++#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift)
++
++/*define for y field*/
++#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6
++#define SDMA_PKT_COPY_TILED_DW_6_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_DW_6_y_shift  16
++#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift)
++
++/*define for DW_7 word*/
++/*define for z field*/
++#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7
++#define SDMA_PKT_COPY_TILED_DW_7_z_mask   0x00000FFF
++#define SDMA_PKT_COPY_TILED_DW_7_z_shift  0
++#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7
++#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift  16
++#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift)
++
++/*define for tile_sw field*/
++#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7
++#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift  24
++#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++/*define for LINEAR_PITCH word*/
++/*define for linear_pitch field*/
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_TILED_COUNT_count_offset 11
++#define SDMA_PKT_COPY_TILED_COUNT_count_mask   0x000FFFFF
++#define SDMA_PKT_COPY_TILED_COUNT_count_shift  0
++#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift)
++
++/*define for videocopy field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask   0x00000001
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift  26
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift)
++
++/*define for broadcast field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask   0x00000001
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift  27
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift)
++
++/*define for TILED_ADDR_LO_0 word*/
++/*define for tiled_addr0_31_0 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift)
++
++/*define for TILED_ADDR_HI_0 word*/
++/*define for tiled_addr0_63_32 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift)
++
++/*define for TILED_ADDR_LO_1 word*/
++/*define for tiled_addr1_31_0 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift)
++
++/*define for TILED_ADDR_HI_1 word*/
++/*define for tiled_addr1_63_32 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift)
++
++/*define for DW_5 word*/
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask   0x000007FF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift)
++
++/*define for height field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask   0x00003FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift  16
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift)
++
++/*define for DW_6 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift)
++
++/*define for DW_7 word*/
++/*define for element_size field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift  3
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift  8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift  15
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift  18
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift  21
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift  24
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift  26
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift)
++
++/*define for DW_8 word*/
++/*define for x field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift)
++
++/*define for y field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift  16
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift)
++
++/*define for DW_9 word*/
++/*define for z field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask   0x00000FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift)
++
++/*define for DW_10 word*/
++/*define for dst2_sw field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift  8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift)
++
++/*define for dst2_ha field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask   0x00000001
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift  14
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift  16
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift)
++
++/*define for tile_sw field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift  24
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++/*define for LINEAR_PITCH word*/
++/*define for linear_pitch field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask   0x000FFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_T2T packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
++#define SDMA_PKT_COPY_T2T_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_T2T_HEADER_op_shift  0
++#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for src_x field*/
++#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3
++#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift  0
++#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift)
++
++/*define for src_y field*/
++#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3
++#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift  16
++#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift)
++
++/*define for DW_4 word*/
++/*define for src_z field*/
++#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4
++#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask   0x000007FF
++#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift  0
++#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift)
++
++/*define for src_pitch_in_tile field*/
++#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4
++#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask   0x00000FFF
++#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift  16
++#define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift)
++
++/*define for DW_5 word*/
++/*define for src_slice_pitch field*/
++#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5
++#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift  0
++#define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift)
++
++/*define for DW_6 word*/
++/*define for src_element_size field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift  0
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift)
++
++/*define for src_array_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift  3
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift)
++
++/*define for src_mit_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift  8
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift)
++
++/*define for src_tilesplit_size field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift)
++
++/*define for src_bank_w field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift  15
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift)
++
++/*define for src_bank_h field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift  18
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift)
++
++/*define for src_num_bank field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift  21
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift)
++
++/*define for src_mat_aspt field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift  24
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift)
++
++/*define for src_pipe_config field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift  26
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_9 word*/
++/*define for dst_x field*/
++#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9
++#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift  0
++#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift)
++
++/*define for dst_y field*/
++#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9
++#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift  16
++#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift)
++
++/*define for DW_10 word*/
++/*define for dst_z field*/
++#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10
++#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask   0x000007FF
++#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift  0
++#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift)
++
++/*define for dst_pitch_in_tile field*/
++#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10
++#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask   0x00000FFF
++#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift  16
++#define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift)
++
++/*define for DW_11 word*/
++/*define for dst_slice_pitch field*/
++#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11
++#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift  0
++#define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift)
++
++/*define for DW_12 word*/
++/*define for dst_array_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift  3
++#define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift)
++
++/*define for dst_mit_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift  8
++#define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift)
++
++/*define for dst_tilesplit_size field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift)
++
++/*define for dst_bank_w field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift  15
++#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift)
++
++/*define for dst_bank_h field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift  18
++#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift)
++
++/*define for dst_num_bank field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift  21
++#define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift)
++
++/*define for dst_mat_aspt field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift  24
++#define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift)
++
++/*define for dst_pipe_config field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift  26
++#define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift)
++
++/*define for DW_13 word*/
++/*define for rect_x field*/
++#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13
++#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift  0
++#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift)
++
++/*define for rect_y field*/
++#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13
++#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift  16
++#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift)
++
++/*define for DW_14 word*/
++/*define for rect_z field*/
++#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14
++#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask   0x000007FF
++#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift  0
++#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift)
++
++/*define for dst_sw field*/
++#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14
++#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift  16
++#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14
++#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift  24
++#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift)
++
++/*define for detile field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask   0x00000001
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift  31
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift)
++
++/*define for TILED_ADDR_LO word*/
++/*define for tiled_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift)
++
++/*define for TILED_ADDR_HI word*/
++/*define for tiled_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for tiled_x field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift)
++
++/*define for tiled_y field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift)
++
++/*define for DW_4 word*/
++/*define for tiled_z field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift)
++
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask   0x00000FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift)
++
++/*define for DW_5 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift)
++
++/*define for DW_6 word*/
++/*define for element_size field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift  3
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift  8
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift  15
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift  18
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift  21
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift  24
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift  26
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++/*define for DW_9 word*/
++/*define for linear_x field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift)
++
++/*define for linear_y field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift)
++
++/*define for DW_10 word*/
++/*define for linear_z field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift)
++
++/*define for linear_pitch field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift)
++
++/*define for DW_11 word*/
++/*define for linear_slice_pitch field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask   0x0FFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift)
++
++/*define for DW_12 word*/
++/*define for rect_x field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift)
++
++/*define for rect_y field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift)
++
++/*define for DW_13 word*/
++/*define for rect_z field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift)
++
++/*define for tile_sw field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift  24
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_STRUCT packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
++#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift  0
++#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift)
++
++/*define for detile field*/
++#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
++#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask   0x00000001
++#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift  31
++#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift)
++
++/*define for SB_ADDR_LO word*/
++/*define for sb_addr_31_0 field*/
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift  0
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift)
++
++/*define for SB_ADDR_HI word*/
++/*define for sb_addr_63_32 field*/
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift  0
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift)
++
++/*define for START_INDEX word*/
++/*define for start_index field*/
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift  0
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4
++#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift  0
++#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift)
++
++/*define for DW_5 word*/
++/*define for stride field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask   0x000007FF
++#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift  0
++#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift)
++
++/*define for struct_sw field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask   0x00000003
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift  16
++#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift)
++
++/*define for struct_ha field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask   0x00000001
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift  22
++#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift  24
++#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift)
++
++/*define for linear_ha field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask   0x00000001
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift  30
++#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_WRITE_UNTILED packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
++#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift  0
++#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
++#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift  8
++#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for count field*/
++#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3
++#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask   0x003FFFFF
++#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift)
++
++/*define for sw field*/
++#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3
++#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask   0x00000003
++#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift  24
++#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift)
++
++/*define for DATA0 word*/
++/*define for data0 field*/
++#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4
++#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift)
++
++
++/*
++** Definitions for SDMA_PKT_WRITE_TILED packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
++#define SDMA_PKT_WRITE_TILED_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_TILED_HEADER_op_shift  0
++#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
++#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift  8
++#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3
++#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask   0x000007FF
++#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift)
++
++/*define for height field*/
++#define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3
++#define SDMA_PKT_WRITE_TILED_DW_3_height_mask   0x00003FFF
++#define SDMA_PKT_WRITE_TILED_DW_3_height_shift  16
++#define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift)
++
++/*define for DW_4 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4
++#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift)
++
++/*define for DW_5 word*/
++/*define for element_size field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask   0x00000007
++#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask   0x0000000F
++#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift  3
++#define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask   0x00000007
++#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift  8
++#define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift  11
++#define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift  15
++#define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift  18
++#define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift  21
++#define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift  24
++#define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask   0x0000001F
++#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift  26
++#define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift)
++
++/*define for DW_6 word*/
++/*define for x field*/
++#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6
++#define SDMA_PKT_WRITE_TILED_DW_6_x_mask   0x00003FFF
++#define SDMA_PKT_WRITE_TILED_DW_6_x_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift)
++
++/*define for y field*/
++#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6
++#define SDMA_PKT_WRITE_TILED_DW_6_y_mask   0x00003FFF
++#define SDMA_PKT_WRITE_TILED_DW_6_y_shift  16
++#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift)
++
++/*define for DW_7 word*/
++/*define for z field*/
++#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7
++#define SDMA_PKT_WRITE_TILED_DW_7_z_mask   0x00000FFF
++#define SDMA_PKT_WRITE_TILED_DW_7_z_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift)
++
++/*define for sw field*/
++#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7
++#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift  24
++#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8
++#define SDMA_PKT_WRITE_TILED_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_WRITE_TILED_COUNT_count_shift  0
++#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift)
++
++/*define for DATA0 word*/
++/*define for data0 field*/
++#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9
++#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift  0
++#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift)
++
++
++/*
++** Definitions for SDMA_PKT_WRITE_INCR packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
++#define SDMA_PKT_WRITE_INCR_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_INCR_HEADER_op_shift  0
++#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
++#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift  8
++#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for MASK_DW0 word*/
++/*define for mask_dw0 field*/
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift  0
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift)
++
++/*define for MASK_DW1 word*/
++/*define for mask_dw1 field*/
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift  0
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift)
++
++/*define for INIT_DW0 word*/
++/*define for init_dw0 field*/
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift  0
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift)
++
++/*define for INIT_DW1 word*/
++/*define for init_dw1 field*/
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift  0
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift)
++
++/*define for INCR_DW0 word*/
++/*define for incr_dw0 field*/
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift  0
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift)
++
++/*define for INCR_DW1 word*/
++/*define for incr_dw1 field*/
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift  0
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9
++#define SDMA_PKT_WRITE_INCR_COUNT_count_mask   0x0007FFFF
++#define SDMA_PKT_WRITE_INCR_COUNT_count_shift  0
++#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_INDIRECT packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_INDIRECT_HEADER_op_offset 0
++#define SDMA_PKT_INDIRECT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_INDIRECT_HEADER_op_shift  0
++#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
++#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift  8
++#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift)
++
++/*define for vmid field*/
++#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
++#define SDMA_PKT_INDIRECT_HEADER_vmid_mask   0x0000000F
++#define SDMA_PKT_INDIRECT_HEADER_vmid_shift  16
++#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift)
++
++/*define for BASE_LO word*/
++/*define for ib_base_31_0 field*/
++#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1
++#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift  0
++#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift)
++
++/*define for BASE_HI word*/
++/*define for ib_base_63_32 field*/
++#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2
++#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift  0
++#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift)
++
++/*define for IB_SIZE word*/
++/*define for ib_size field*/
++#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3
++#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask   0x000FFFFF
++#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift  0
++#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift)
++
++/*define for CSA_ADDR_LO word*/
++/*define for csa_addr_31_0 field*/
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift  0
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift)
++
++/*define for CSA_ADDR_HI word*/
++/*define for csa_addr_63_32 field*/
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift  0
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_SEMAPHORE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_SEMAPHORE_HEADER_op_shift  0
++#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift  8
++#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift)
++
++/*define for write_one field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask   0x00000001
++#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift  29
++#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift)
++
++/*define for signal field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask   0x00000001
++#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift  30
++#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift)
++
++/*define for mailbox field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask   0x00000001
++#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift  31
++#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_FENCE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_FENCE_HEADER_op_offset 0
++#define SDMA_PKT_FENCE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_FENCE_HEADER_op_shift  0
++#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
++#define SDMA_PKT_FENCE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_FENCE_HEADER_sub_op_shift  8
++#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift)
++
++/*define for DATA word*/
++/*define for data field*/
++#define SDMA_PKT_FENCE_DATA_data_offset 3
++#define SDMA_PKT_FENCE_DATA_data_mask   0xFFFFFFFF
++#define SDMA_PKT_FENCE_DATA_data_shift  0
++#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift)
++
++
++/*
++** Definitions for SDMA_PKT_SRBM_WRITE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
++#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift  0
++#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
++#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift  8
++#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift)
++
++/*define for byte_en field*/
++#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
++#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask   0x0000000F
++#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift  28
++#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift)
++
++/*define for ADDR word*/
++/*define for addr field*/
++#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1
++#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask   0x0000FFFF
++#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift  0
++#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift)
++
++/*define for DATA word*/
++/*define for data field*/
++#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2
++#define SDMA_PKT_SRBM_WRITE_DATA_data_mask   0xFFFFFFFF
++#define SDMA_PKT_SRBM_WRITE_DATA_data_shift  0
++#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift)
++
++
++/*
++** Definitions for SDMA_PKT_PRE_EXE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
++#define SDMA_PKT_PRE_EXE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_PRE_EXE_HEADER_op_shift  0
++#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
++#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift  8
++#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift)
++
++/*define for dev_sel field*/
++#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
++#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask   0x000000FF
++#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift  16
++#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift)
++
++/*define for EXEC_COUNT word*/
++/*define for exec_count field*/
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift  0
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COND_EXE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COND_EXE_HEADER_op_offset 0
++#define SDMA_PKT_COND_EXE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COND_EXE_HEADER_op_shift  0
++#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
++#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift  8
++#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift)
++
++/*define for REFERENCE word*/
++/*define for reference field*/
++#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3
++#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask   0xFFFFFFFF
++#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift  0
++#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift)
++
++/*define for EXEC_COUNT word*/
++/*define for exec_count field*/
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift  0
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_CONSTANT_FILL packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift  0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift  8
++#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift)
++
++/*define for sw field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask   0x00000003
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift  16
++#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift)
++
++/*define for fillsize field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask   0x00000003
++#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift  30
++#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DATA word*/
++/*define for src_data_31_0 field*/
++#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3
++#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift  0
++#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4
++#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift  0
++#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_POLL_REGMEM packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift  0
++#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift  8
++#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift)
++
++/*define for hdp_flush field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask   0x00000001
++#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift  26
++#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift)
++
++/*define for func field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask   0x00000007
++#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift  28
++#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift)
++
++/*define for mem_poll field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask   0x00000001
++#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift  31
++#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift)
++
++/*define for VALUE word*/
++/*define for value field*/
++#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3
++#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift  0
++#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift)
++
++/*define for MASK word*/
++/*define for mask field*/
++#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4
++#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift  0
++#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift)
++
++/*define for DW5 word*/
++/*define for interval field*/
++#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5
++#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask   0x0000FFFF
++#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift  0
++#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift)
++
++/*define for retry_count field*/
++#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5
++#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask   0x00000FFF
++#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift  16
++#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TIMESTAMP_SET packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift  0
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift  8
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift)
++
++/*define for INIT_DATA_LO word*/
++/*define for init_data_31_0 field*/
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift  0
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift)
++
++/*define for INIT_DATA_HI word*/
++/*define for init_data_63_32 field*/
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift  0
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TIMESTAMP_GET packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift  8
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift)
++
++/*define for WRITE_ADDR_LO word*/
++/*define for write_addr_31_3 field*/
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift  3
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift)
++
++/*define for WRITE_ADDR_HI word*/
++/*define for write_addr_63_32 field*/
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift  8
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift)
++
++/*define for WRITE_ADDR_LO word*/
++/*define for write_addr_31_3 field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift  3
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift)
++
++/*define for WRITE_ADDR_HI word*/
++/*define for write_addr_63_32 field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TRAP packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TRAP_HEADER_op_offset 0
++#define SDMA_PKT_TRAP_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TRAP_HEADER_op_shift  0
++#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
++#define SDMA_PKT_TRAP_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TRAP_HEADER_sub_op_shift  8
++#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift)
++
++/*define for INT_CONTEXT word*/
++/*define for int_context field*/
++#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1
++#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask   0x0FFFFFFF
++#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift  0
++#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift)
++
++
++/*
++** Definitions for SDMA_PKT_NOP packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_NOP_HEADER_op_offset 0
++#define SDMA_PKT_NOP_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_NOP_HEADER_op_shift  0
++#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_NOP_HEADER_sub_op_offset 0
++#define SDMA_PKT_NOP_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_NOP_HEADER_sub_op_shift  8
++#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift)
++
++
++#endif /* __ICELAND_SDMA_PKT_OPEN_H_ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
+new file mode 100644
+index 0000000..c6f1e2f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
+@@ -0,0 +1,675 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "ppsmc.h"
++#include "iceland_smumgr.h"
++#include "smu_ucode_xfer_vi.h"
++#include "amdgpu_ucode.h"
++
++#include "smu/smu_7_1_1_d.h"
++#include "smu/smu_7_1_1_sh_mask.h"
++
++#define ICELAND_SMC_SIZE 0x20000
++
++static int iceland_set_smc_sram_address(struct amdgpu_device *adev,
++					uint32_t smc_address, uint32_t limit)
++{
++	uint32_t val;
++
++	if (smc_address & 3)
++		return -EINVAL;
++
++	if ((smc_address + 3) > limit)
++		return -EINVAL;
++
++	WREG32(mmSMC_IND_INDEX_0, smc_address);
++
++	val = RREG32(mmSMC_IND_ACCESS_CNTL);
++	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
++	WREG32(mmSMC_IND_ACCESS_CNTL, val);
++
++	return 0;
++}
++
++static int iceland_copy_bytes_to_smc(struct amdgpu_device *adev,
++				     uint32_t smc_start_address,
++				     const uint8_t *src,
++				     uint32_t byte_count, uint32_t limit)
++{
++	uint32_t addr;
++	uint32_t data, orig_data;
++	int result = 0;
++	uint32_t extra_shift;
++	unsigned long flags;
++
++	if (smc_start_address & 3)
++		return -EINVAL;
++
++	if ((smc_start_address + byte_count) > limit)
++		return -EINVAL;
++
++	addr = smc_start_address;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	while (byte_count >= 4) {
++		/* Bytes are written into the SMC addres space with the MSB first */
++		data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
++
++		result = iceland_set_smc_sram_address(adev, addr, limit);
++
++		if (result)
++			goto out;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++
++		src += 4;
++		byte_count -= 4;
++		addr += 4;
++	}
++
++	if (0 != byte_count) {
++		/* Now write odd bytes left, do a read modify write cycle */
++		data = 0;
++
++		result = iceland_set_smc_sram_address(adev, addr, limit);
++		if (result)
++			goto out;
++
++		orig_data = RREG32(mmSMC_IND_DATA_0);
++		extra_shift = 8 * (4 - byte_count);
++
++		while (byte_count > 0) {
++			data = (data << 8) + *src++;
++			byte_count--;
++		}
++
++		data <<= extra_shift;
++		data |= (orig_data & ~((~0UL) << extra_shift));
++
++		result = iceland_set_smc_sram_address(adev, addr, limit);
++		if (result)
++			goto out;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++	}
++
++out:
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return result;
++}
++
++void iceland_start_smc(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++}
++
++void iceland_reset_smc(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++}
++
++static int iceland_program_jump_on_start(struct amdgpu_device *adev)
++{
++	static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40};
++	iceland_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
++
++	return 0;
++}
++
++void iceland_stop_smc_clock(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++
++	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
++}
++
++void iceland_start_smc_clock(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++
++	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
++}
++
++static bool iceland_is_smc_ram_running(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++	val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable);
++
++	return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));
++}
++
++static int wait_smu_response(struct amdgpu_device *adev)
++{
++	int i;
++	uint32_t val;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32(mmSMC_RESP_0);
++		if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int iceland_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
++{
++	if (!iceland_is_smc_ram_running(adev))
++		return -EINVAL;
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MESSAGE_0, msg);
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send message\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int iceland_send_msg_to_smc_without_waiting(struct amdgpu_device *adev,
++						   PPSMC_Msg msg)
++{
++	if (!iceland_is_smc_ram_running(adev))
++		return -EINVAL;;
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MESSAGE_0, msg);
++
++	return 0;
++}
++
++static int iceland_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++						  PPSMC_Msg msg,
++						  uint32_t parameter)
++{
++	WREG32(mmSMC_MSG_ARG_0, parameter);
++
++	return iceland_send_msg_to_smc(adev, msg);
++}
++
++static int iceland_send_msg_to_smc_with_parameter_without_waiting(
++					struct amdgpu_device *adev,
++					PPSMC_Msg msg, uint32_t parameter)
++{
++	WREG32(mmSMC_MSG_ARG_0, parameter);
++
++	return iceland_send_msg_to_smc_without_waiting(adev, msg);
++}
++
++#if 0 /* not used yet */
++static int iceland_wait_for_smc_inactive(struct amdgpu_device *adev)
++{
++	int i;
++	uint32_t val;
++
++	if (!iceland_is_smc_ram_running(adev))
++		return -EINVAL;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++		if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout)
++		return -EINVAL;
++
++	return 0;
++}
++#endif
++
++static int iceland_smu_upload_firmware_image(struct amdgpu_device *adev)
++{
++	const struct smc_firmware_header_v1_0 *hdr;
++	uint32_t ucode_size;
++	uint32_t ucode_start_address;
++	const uint8_t *src;
++	uint32_t val;
++	uint32_t byte_count;
++	uint32_t data;
++	unsigned long flags;
++	int i;
++
++	if (!adev->pm.fw)
++		return -EINVAL;
++
++	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
++	amdgpu_ucode_print_smc_hdr(&hdr->header);
++
++	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
++	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
++	ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
++	src = (const uint8_t *)
++		(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++
++	if (ucode_size & 3) {
++		DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
++		return -EINVAL;
++	}
++
++	if (ucode_size > ICELAND_SMC_SIZE) {
++		DRM_ERROR("SMC address is beyond the SMC RAM area\n");
++		return -EINVAL;
++	}
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixRCU_UC_EVENTS);
++		if (REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done) == 0)
++			break;
++		udelay(1);
++	}
++	val = RREG32_SMC(ixSMC_SYSCON_MISC_CNTL);
++	WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, val | 1);
++
++	iceland_stop_smc_clock(adev);
++	iceland_reset_smc(adev);
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
++
++	val = RREG32(mmSMC_IND_ACCESS_CNTL);
++	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
++	WREG32(mmSMC_IND_ACCESS_CNTL, val);
++
++	byte_count = ucode_size;
++	while (byte_count >= 4) {
++		data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
++		WREG32(mmSMC_IND_DATA_0, data);
++		src += 4;
++		byte_count -= 4;
++	}
++	val = RREG32(mmSMC_IND_ACCESS_CNTL);
++	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
++	WREG32(mmSMC_IND_ACCESS_CNTL, val);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++
++	return 0;
++}
++
++#if 0 /* not used yet */
++static int iceland_read_smc_sram_dword(struct amdgpu_device *adev,
++				       uint32_t smc_address,
++				       uint32_t *value,
++				       uint32_t limit)
++{
++	int result;
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	result = iceland_set_smc_sram_address(adev, smc_address, limit);
++	if (result == 0)
++		*value = RREG32(mmSMC_IND_DATA_0);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return result;
++}
++
++static int iceland_write_smc_sram_dword(struct amdgpu_device *adev,
++					uint32_t smc_address,
++					uint32_t value,
++					uint32_t limit)
++{
++	int result;
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	result = iceland_set_smc_sram_address(adev, smc_address, limit);
++	if (result == 0)
++		WREG32(mmSMC_IND_DATA_0, value);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return result;
++}
++
++static int iceland_smu_stop_smc(struct amdgpu_device *adev)
++{
++	iceland_reset_smc(adev);
++	iceland_stop_smc_clock(adev);
++
++	return 0;
++}
++#endif
++
++static int iceland_smu_start_smc(struct amdgpu_device *adev)
++{
++	int i;
++	uint32_t val;
++
++	iceland_program_jump_on_start(adev);
++	iceland_start_smc_clock(adev);
++	iceland_start_smc(adev);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixFIRMWARE_FLAGS);
++		if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED) == 1)
++			break;
++		udelay(1);
++	}
++	return 0;
++}
++
++static enum AMDGPU_UCODE_ID iceland_convert_fw_type(uint32_t fw_type)
++{
++	switch (fw_type) {
++		case UCODE_ID_SDMA0:
++			return AMDGPU_UCODE_ID_SDMA0;
++		case UCODE_ID_SDMA1:
++			return AMDGPU_UCODE_ID_SDMA1;
++		case UCODE_ID_CP_CE:
++			return AMDGPU_UCODE_ID_CP_CE;
++		case UCODE_ID_CP_PFP:
++			return AMDGPU_UCODE_ID_CP_PFP;
++		case UCODE_ID_CP_ME:
++			return AMDGPU_UCODE_ID_CP_ME;
++		case UCODE_ID_CP_MEC:
++		case UCODE_ID_CP_MEC_JT1:
++			return AMDGPU_UCODE_ID_CP_MEC1;
++		case UCODE_ID_CP_MEC_JT2:
++			return AMDGPU_UCODE_ID_CP_MEC2;
++		case UCODE_ID_RLC_G:
++			return AMDGPU_UCODE_ID_RLC_G;
++		default:
++			DRM_ERROR("ucode type is out of range!\n");
++			return AMDGPU_UCODE_ID_MAXIMUM;
++	}
++}
++
++static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type)
++{
++	switch (fw_type) {
++		case AMDGPU_UCODE_ID_SDMA0:
++			return UCODE_ID_SDMA0_MASK;
++		case AMDGPU_UCODE_ID_SDMA1:
++			return UCODE_ID_SDMA1_MASK;
++		case AMDGPU_UCODE_ID_CP_CE:
++			return UCODE_ID_CP_CE_MASK;
++		case AMDGPU_UCODE_ID_CP_PFP:
++			return UCODE_ID_CP_PFP_MASK;
++		case AMDGPU_UCODE_ID_CP_ME:
++			return UCODE_ID_CP_ME_MASK;
++		case AMDGPU_UCODE_ID_CP_MEC1:
++			return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK;
++		case AMDGPU_UCODE_ID_CP_MEC2:
++			return UCODE_ID_CP_MEC_MASK;
++		case AMDGPU_UCODE_ID_RLC_G:
++			return UCODE_ID_RLC_G_MASK;
++		default:
++			DRM_ERROR("ucode type is out of range!\n");
++			return 0;
++	}
++}
++
++static int iceland_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
++						      uint32_t fw_type,
++						      struct SMU_Entry *entry)
++{
++	enum AMDGPU_UCODE_ID id = iceland_convert_fw_type(fw_type);
++	struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
++	const struct gfx_firmware_header_v1_0 *header = NULL;
++	uint64_t gpu_addr;
++	uint32_t data_size;
++
++	if (ucode->fw == NULL)
++		return -EINVAL;
++
++	gpu_addr  = ucode->mc_addr;
++	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
++	data_size = le32_to_cpu(header->header.ucode_size_bytes);
++
++	entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
++	entry->id = (uint16_t)fw_type;
++	entry->image_addr_high = upper_32_bits(gpu_addr);
++	entry->image_addr_low = lower_32_bits(gpu_addr);
++	entry->meta_data_addr_high = 0;
++	entry->meta_data_addr_low = 0;
++	entry->data_size_byte = data_size;
++	entry->num_register_entries = 0;
++	entry->flags = 0;
++
++	return 0;
++}
++
++static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
++{
++	struct iceland_smu_private_data *private = (struct iceland_smu_private_data *)adev->smu.priv;
++	struct SMU_DRAMData_TOC *toc;
++	uint32_t fw_to_load;
++
++	toc = (struct SMU_DRAMData_TOC *)private->header;
++	toc->num_entries = 0;
++	toc->structure_version = 1;
++
++	if (!adev->firmware.smu_load)
++		return 0;
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for RLC\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for CE\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for PFP\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for ME\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for MEC\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for SDMA0\n");
++		return -EINVAL;
++	}
++
++	if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for SDMA1\n");
++		return -EINVAL;
++	}
++
++	iceland_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high);
++	iceland_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low);
++
++	fw_to_load = UCODE_ID_RLC_G_MASK |
++			UCODE_ID_SDMA0_MASK |
++			UCODE_ID_SDMA1_MASK |
++			UCODE_ID_CP_CE_MASK |
++			UCODE_ID_CP_ME_MASK |
++			UCODE_ID_CP_PFP_MASK |
++			UCODE_ID_CP_MEC_MASK |
++			UCODE_ID_CP_MEC_JT1_MASK |
++			UCODE_ID_CP_MEC_JT2_MASK;
++
++	if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
++		DRM_ERROR("Fail to request SMU load ucode\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int iceland_smu_check_fw_load_finish(struct amdgpu_device *adev,
++					    uint32_t fw_type)
++{
++	uint32_t fw_mask = iceland_smu_get_mask_for_fw_type(fw_type);
++	int i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_27) & fw_mask))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("check firmware loading failed\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int iceland_smu_start(struct amdgpu_device *adev)
++{
++	int result;
++
++	result = iceland_smu_upload_firmware_image(adev);
++	if (result)
++		return result;
++	result = iceland_smu_start_smc(adev);
++	if (result)
++		return result;
++
++	return iceland_smu_request_load_fw(adev);
++}
++
++static const struct amdgpu_smumgr_funcs iceland_smumgr_funcs = {
++	.check_fw_load_finish = iceland_smu_check_fw_load_finish,
++	.request_smu_load_fw = NULL,
++	.request_smu_specific_fw = NULL,
++};
++
++int iceland_smu_init(struct amdgpu_device *adev)
++{
++	struct iceland_smu_private_data *private;
++	uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
++	struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
++	uint64_t mc_addr;
++	void *toc_buf_ptr;
++	int ret;
++
++	private = kzalloc(sizeof(struct iceland_smu_private_data), GFP_KERNEL);
++	if (NULL == private)
++		return -ENOMEM;
++
++	/* allocate firmware buffers */
++	if (adev->firmware.smu_load)
++		amdgpu_ucode_init_bo(adev);
++
++	adev->smu.priv = private;
++	adev->smu.fw_flags = 0;
++
++	/* Allocate FW image data structure and header buffer */
++	ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE,
++			       true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, toc_buf);
++	if (ret) {
++		DRM_ERROR("Failed to allocate memory for TOC buffer\n");
++		return -ENOMEM;
++	}
++
++	/* Retrieve GPU address for header buffer and internal buffer */
++	ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
++	if (ret) {
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to reserve the TOC buffer\n");
++		return -EINVAL;
++	}
++
++	ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.toc_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to pin the TOC buffer\n");
++		return -EINVAL;
++	}
++
++	ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.toc_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to map the TOC buffer\n");
++		return -EINVAL;
++	}
++
++	amdgpu_bo_unreserve(adev->smu.toc_buf);
++	private->header_addr_low = lower_32_bits(mc_addr);
++	private->header_addr_high = upper_32_bits(mc_addr);
++	private->header = toc_buf_ptr;
++
++	adev->smu.smumgr_funcs = &iceland_smumgr_funcs;
++
++	return 0;
++}
++
++int iceland_smu_fini(struct amdgpu_device *adev)
++{
++	amdgpu_bo_unref(&adev->smu.toc_buf);
++	kfree(adev->smu.priv);
++	adev->smu.priv = NULL;
++	if (adev->firmware.fw_buf)
++		amdgpu_ucode_fini_bo(adev);
++
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h b/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h
+new file mode 100644
+index 0000000..1e0769e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef ICELAND_SMUMGR_H
++#define ICELAND_SMUMGR_H
++
++#include "ppsmc.h"
++
++extern int iceland_smu_init(struct amdgpu_device *adev);
++extern int iceland_smu_fini(struct amdgpu_device *adev);
++extern int iceland_smu_start(struct amdgpu_device *adev);
++
++struct iceland_smu_private_data
++{
++	uint8_t *header;
++	uint8_t *mec_image;
++	uint32_t header_addr_high;
++	uint32_t header_addr_low;
++};
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+new file mode 100644
+index 0000000..a83029d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -0,0 +1,1447 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_ucode.h"
++#include "amdgpu_trace.h"
++#include "vi.h"
++#include "vid.h"
++
++#include "oss/oss_2_4_d.h"
++#include "oss/oss_2_4_sh_mask.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "gca/gfx_8_0_d.h"
++#include "gca/gfx_8_0_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "iceland_sdma_pkt_open.h"
++
++static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
++static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
++static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
++static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
++
++MODULE_FIRMWARE("radeon/topaz_sdma.bin");
++MODULE_FIRMWARE("radeon/topaz_sdma1.bin");
++
++static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
++{
++	SDMA0_REGISTER_OFFSET,
++	SDMA1_REGISTER_OFFSET
++};
++
++static const u32 golden_settings_iceland_a11[] =
++{
++	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
++	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
++	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
++	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
++};
++
++static const u32 iceland_mgcg_cgcg_init[] =
++{
++	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
++	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
++};
++
++/*
++ * sDMA - System DMA
++ * Starting with CIK, the GPU has new asynchronous
++ * DMA engines.  These engines are used for compute
++ * and gfx.  There are two DMA engines (SDMA0, SDMA1)
++ * and each one supports 1 ring buffer used for gfx
++ * and 2 queues used for compute.
++ *
++ * The programming model is very similar to the CP
++ * (ring buffer, IBs, etc.), but sDMA has it's own
++ * packet format that is different from the PM4 format
++ * used by the CP. sDMA supports copying data, writing
++ * embedded data, solid fills, and a number of other
++ * things.  It also has support for tiling/detiling of
++ * buffers.
++ */
++
++static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		amdgpu_program_register_sequence(adev,
++						 iceland_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_iceland_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
++		break;
++	default:
++		break;
++	}
++}
++
++/**
++ * sdma_v2_4_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err, i;
++	struct amdgpu_firmware_info *info = NULL;
++	const struct common_firmware_header *header = NULL;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		chip_name = "topaz";
++		break;
++	default: BUG();
++	}
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		if (i == 0)
++			snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
++		else
++			snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
++		err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
++		if (err)
++			goto out;
++		err = amdgpu_ucode_validate(adev->sdma[i].fw);
++		if (err)
++			goto out;
++
++		if (adev->firmware.smu_load) {
++			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
++			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
++			info->fw = adev->sdma[i].fw;
++			header = (const struct common_firmware_header *)info->fw->data;
++			adev->firmware.fw_size +=
++				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++		}
++	}
++
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "sdma_v2_4: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++			release_firmware(adev->sdma[i].fw);
++			adev->sdma[i].fw = NULL;
++		}
++	}
++	return err;
++}
++
++/**
++ * sdma_v2_4_ring_get_rptr - get the current read pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Get the current rptr from the hardware (VI+).
++ */
++static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	u32 rptr;
++
++	/* XXX check if swapping is necessary on BE */
++	rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
++
++	return rptr;
++}
++
++/**
++ * sdma_v2_4_ring_get_wptr - get the current write pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Get the current wptr from the hardware (VI+).
++ */
++static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
++	u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
++
++	return wptr;
++}
++
++/**
++ * sdma_v2_4_ring_set_wptr - commit the write pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Write the wptr back to the hardware (VI+).
++ */
++static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
++
++	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
++}
++
++static void sdma_v2_4_hdp_flush_ring_emit(struct amdgpu_ring *);
++
++/**
++ * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
++ *
++ * @ring: amdgpu ring pointer
++ * @ib: IB object to schedule
++ *
++ * Schedule an IB in the DMA ring (VI).
++ */
++static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
++				   struct amdgpu_ib *ib)
++{
++	u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
++	u32 next_rptr = ring->wptr + 5;
++
++	if (ib->flush_hdp_writefifo)
++		next_rptr += 6;
++
++	while ((next_rptr & 7) != 2)
++		next_rptr++;
++
++	next_rptr += 6;
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
++	amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
++	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
++	amdgpu_ring_write(ring, next_rptr);
++
++	if (ib->flush_hdp_writefifo) {
++		/* flush HDP */
++		sdma_v2_4_hdp_flush_ring_emit(ring);
++	}
++
++	/* IB packet must end on a 8 DW boundary */
++	while ((ring->wptr & 7) != 2)
++		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
++			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
++	/* base must be 32 byte aligned */
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, ib->length_dw);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0);
++
++}
++
++/**
++ * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Emit an hdp flush packet on the requested DMA ring.
++ */
++static void sdma_v2_4_hdp_flush_ring_emit(struct amdgpu_ring *ring)
++{
++	u32 ref_and_mask = 0;
++
++	if (ring == &ring->adev->sdma[0].ring)
++		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
++	else
++		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
++	amdgpu_ring_write(ring, ref_and_mask); /* reference */
++	amdgpu_ring_write(ring, ref_and_mask); /* mask */
++	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
++			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
++}
++
++/**
++ * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
++ *
++ * @ring: amdgpu ring pointer
++ * @fence: amdgpu fence object
++ *
++ * Add a DMA fence packet to the ring to write
++ * the fence seq number and DMA trap packet to generate
++ * an interrupt if needed (VI).
++ */
++static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				      bool write64bits)
++{
++	/* write the fence */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
++	amdgpu_ring_write(ring, lower_32_bits(addr));
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++
++	/* optionally write high bits as well */
++	if (write64bits) {
++		addr += 4;
++		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
++		amdgpu_ring_write(ring, lower_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(seq));
++	}
++
++	/* generate an interrupt */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
++	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
++}
++
++/**
++ * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @semaphore: amdgpu semaphore object
++ * @emit_wait: wait or signal semaphore
++ *
++ * Add a DMA semaphore packet to the ring wait on or signal
++ * other rings (VI).
++ */
++static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
++					  struct amdgpu_semaphore *semaphore,
++					  bool emit_wait)
++{
++	u64 addr = semaphore->gpu_addr;
++	u32 sig = emit_wait ? 0 : 1;
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
++			  SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
++	amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++
++	return true;
++}
++
++/**
++ * sdma_v2_4_gfx_stop - stop the gfx async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the gfx async dma ring buffers (VI).
++ */
++static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
++	struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
++	u32 rb_cntl, ib_cntl;
++	int i;
++
++	if ((adev->mman.buffer_funcs_ring == sdma0) ||
++	    (adev->mman.buffer_funcs_ring == sdma1))
++		amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
++		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
++		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
++	}
++	sdma0->ready = false;
++	sdma1->ready = false;
++}
++
++/**
++ * sdma_v2_4_rlc_stop - stop the compute async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the compute async dma queues (VI).
++ */
++static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++}
++
++/**
++ * sdma_v2_4_enable - stop the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ * @enable: enable/disable the DMA MEs.
++ *
++ * Halt or unhalt the async dma engines (VI).
++ */
++static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
++{
++	u32 f32_cntl;
++	int i;
++
++	if (enable == false) {
++		sdma_v2_4_gfx_stop(adev);
++		sdma_v2_4_rlc_stop(adev);
++	}
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
++		if (enable)
++			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
++		else
++			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
++		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
++	}
++}
++
++/**
++ * sdma_v2_4_gfx_resume - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the gfx DMA ring buffers and enable them (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	u32 rb_cntl, ib_cntl;
++	u32 rb_bufsz;
++	u32 wb_offset;
++	int i, j, r;
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		ring = &adev->sdma[i].ring;
++		wb_offset = (ring->rptr_offs * 4);
++
++		mutex_lock(&adev->srbm_mutex);
++		for (j = 0; j < 16; j++) {
++			vi_srbm_select(adev, 0, 0, 0, j);
++			/* SDMA GFX */
++			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
++			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
++		}
++		vi_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++
++		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
++
++		/* Set ring buffer size in dwords */
++		rb_bufsz = order_base_2(ring->ring_size / 4);
++		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
++#ifdef __BIG_ENDIAN
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
++					RPTR_WRITEBACK_SWAP_ENABLE, 1);
++#endif
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++
++		/* Initialize the ring buffer's read and write pointers */
++		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
++
++		/* set the wb address whether it's enabled or not */
++		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
++		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
++		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
++		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
++
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
++
++		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
++		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
++
++		ring->wptr = 0;
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
++
++		/* enable DMA RB */
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++
++		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
++		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
++#ifdef __BIG_ENDIAN
++		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
++#endif
++		/* enable DMA IBs */
++		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
++
++		ring->ready = true;
++
++		r = amdgpu_ring_test_ring(ring);
++		if (r) {
++			ring->ready = false;
++			return r;
++		}
++
++		if (adev->mman.buffer_funcs_ring == ring)
++			amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
++	}
++
++	return 0;
++}
++
++/**
++ * sdma_v2_4_rlc_resume - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the compute DMA queues and enable them (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return 0;
++}
++
++/**
++ * sdma_v2_4_load_microcode - load the sDMA ME ucode
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Loads the sDMA0/1 ucode.
++ * Returns 0 for success, -EINVAL if the ucode is not available.
++ */
++static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
++{
++	const struct sdma_firmware_header_v1_0 *hdr;
++	const __le32 *fw_data;
++	u32 fw_size;
++	int i, j;
++	bool smc_loads_fw = false; /* XXX fix me */
++
++	if (!adev->sdma[0].fw || !adev->sdma[1].fw)
++		return -EINVAL;
++
++	/* halt the MEs */
++	sdma_v2_4_enable(adev, false);
++
++	if (smc_loads_fw) {
++		/* XXX query SMC for fw load complete */
++	} else {
++		for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++			hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
++			amdgpu_ucode_print_sdma_hdr(&hdr->header);
++			fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++			adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
++
++			fw_data = (const __le32 *)
++				(adev->sdma[i].fw->data +
++				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++			WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
++			for (j = 0; j < fw_size; j++)
++				WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
++			WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
++		}
++	}
++
++	return 0;
++}
++
++/**
++ * sdma_v2_4_start - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the DMA engines and enable them (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v2_4_start(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (!adev->firmware.smu_load) {
++		r = sdma_v2_4_load_microcode(adev);
++		if (r)
++			return r;
++	} else {
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_SDMA0);
++		if (r)
++			return -EINVAL;
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_SDMA1);
++		if (r)
++			return -EINVAL;
++	}
++
++	/* unhalt the MEs */
++	sdma_v2_4_enable(adev, true);
++
++	/* start the gfx rings and rlc compute queues */
++	r = sdma_v2_4_gfx_resume(adev);
++	if (r)
++		return r;
++	r = sdma_v2_4_rlc_resume(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++/**
++ * sdma_v2_4_ring_test_ring - simple async dma engine test
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Test the DMA engine by writing using it to write an
++ * value to memory. (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	unsigned i;
++	unsigned index;
++	int r;
++	u32 tmp;
++	u64 gpu_addr;
++
++	r = amdgpu_wb_get(adev, &index);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
++		return r;
++	}
++
++	gpu_addr = adev->wb.gpu_addr + (index * 4);
++	tmp = 0xCAFEDEAD;
++	adev->wb.wb[index] = cpu_to_le32(tmp);
++
++	r = amdgpu_ring_lock(ring, 5);
++	if (r) {
++		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
++		amdgpu_wb_free(adev, index);
++		return r;
++	}
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
++	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
++	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = le32_to_cpu(adev->wb.wb[index]);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
++			  ring->idx, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_wb_free(adev, index);
++
++	return r;
++}
++
++/**
++ * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Test a simple IB in the DMA ring (VI).
++ * Returns 0 on success, error on failure.
++ */
++static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_ib ib;
++	unsigned i;
++	unsigned index;
++	int r;
++	u32 tmp = 0;
++	u64 gpu_addr;
++
++	r = amdgpu_wb_get(adev, &index);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
++		return r;
++	}
++
++	gpu_addr = adev->wb.gpu_addr + (index * 4);
++	tmp = 0xCAFEDEAD;
++	adev->wb.wb[index] = cpu_to_le32(tmp);
++
++	r = amdgpu_ib_get(ring, NULL, 256, &ib);
++	if (r) {
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		return r;
++	}
++
++	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
++	ib.ptr[1] = lower_32_bits(gpu_addr);
++	ib.ptr[2] = upper_32_bits(gpu_addr);
++	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
++	ib.ptr[4] = 0xDEADBEEF;
++	ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
++	ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
++	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
++	ib.length_dw = 8;
++
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++		return r;
++	}
++	r = amdgpu_fence_wait(ib.fence, false);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		return r;
++	}
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = le32_to_cpu(adev->wb.wb[index]);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
++			 ib.fence->ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
++		r = -EINVAL;
++	}
++	amdgpu_ib_free(adev, &ib);
++	amdgpu_wb_free(adev, index);
++	return r;
++}
++
++/**
++ * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @src: src addr to copy from
++ * @count: number of page entries to update
++ *
++ * Update PTEs by copying them from the GART using sDMA (CIK).
++ */
++static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
++				  uint64_t pe, uint64_t src,
++				  unsigned count)
++{
++	while (count) {
++		unsigned bytes = count * 8;
++		if (bytes > 0x1FFFF8)
++			bytes = 0x1FFFF8;
++
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
++			SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++		ib->ptr[ib->length_dw++] = bytes;
++		ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
++		ib->ptr[ib->length_dw++] = lower_32_bits(src);
++		ib->ptr[ib->length_dw++] = upper_32_bits(src);
++		ib->ptr[ib->length_dw++] = lower_32_bits(pe);
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++
++		pe += bytes;
++		src += bytes;
++		count -= bytes / 8;
++	}
++}
++
++/**
++ * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: access flags
++ *
++ * Update PTEs by writing them manually using sDMA (CIK).
++ */
++static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
++				   uint64_t pe,
++				   uint64_t addr, unsigned count,
++				   uint32_t incr, uint32_t flags)
++{
++	uint64_t value;
++	unsigned ndw;
++
++	while (count) {
++		ndw = count * 2;
++		if (ndw > 0xFFFFE)
++			ndw = 0xFFFFE;
++
++		/* for non-physically contiguous pages (system) */
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++			SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++		ib->ptr[ib->length_dw++] = pe;
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++		ib->ptr[ib->length_dw++] = ndw;
++		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
++			if (flags & AMDGPU_PTE_SYSTEM) {
++				value = amdgpu_vm_map_gart(ib->ring->adev, addr);
++				value &= 0xFFFFFFFFFFFFF000ULL;
++			} else if (flags & AMDGPU_PTE_VALID) {
++				value = addr;
++			} else {
++				value = 0;
++			}
++			addr += incr;
++			value |= flags;
++			ib->ptr[ib->length_dw++] = value;
++			ib->ptr[ib->length_dw++] = upper_32_bits(value);
++		}
++	}
++}
++
++/**
++ * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: access flags
++ *
++ * Update the page tables using sDMA (CIK).
++ */
++static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
++				     uint64_t pe,
++				     uint64_t addr, unsigned count,
++				     uint32_t incr, uint32_t flags)
++{
++	uint64_t value;
++	unsigned ndw;
++
++	while (count) {
++		ndw = count;
++		if (ndw > 0x7FFFF)
++			ndw = 0x7FFFF;
++
++		if (flags & AMDGPU_PTE_VALID)
++			value = addr;
++		else
++			value = 0;
++
++		/* for physically contiguous pages (vram) */
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
++		ib->ptr[ib->length_dw++] = pe; /* dst addr */
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++		ib->ptr[ib->length_dw++] = flags; /* mask */
++		ib->ptr[ib->length_dw++] = 0;
++		ib->ptr[ib->length_dw++] = value; /* value */
++		ib->ptr[ib->length_dw++] = upper_32_bits(value);
++		ib->ptr[ib->length_dw++] = incr; /* increment size */
++		ib->ptr[ib->length_dw++] = 0;
++		ib->ptr[ib->length_dw++] = ndw; /* number of entries */
++
++		pe += ndw * 8;
++		addr += ndw * incr;
++		count -= ndw;
++	}
++}
++
++/**
++ * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
++ *
++ * @ib: indirect buffer to fill with padding
++ *
++ */
++static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
++{
++	while (ib->length_dw & 0x7)
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
++}
++
++/**
++ * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
++ *
++ * @ring: amdgpu_ring pointer
++ * @vm: amdgpu_vm pointer
++ *
++ * Update the page table base and flush the VM TLB
++ * using sDMA (VI).
++ */
++static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
++					 unsigned vm_id, uint64_t pd_addr)
++{
++	u32 srbm_gfx_cntl = 0;
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	if (vm_id < 8) {
++		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
++	} else {
++		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
++	}
++	amdgpu_ring_write(ring, pd_addr >> 12);
++
++	/* update SH_MEM_* regs */
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, srbm_gfx_cntl);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_BASES);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
++	amdgpu_ring_write(ring, 1);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
++	amdgpu_ring_write(ring, 0);
++
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, srbm_gfx_cntl);
++
++
++	/* flush TLB */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 1 << vm_id);
++
++	/* wait for flush */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0); /* reference */
++	amdgpu_ring_write(ring, 0); /* mask */
++	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
++			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
++}
++
++static int sdma_v2_4_early_init(struct amdgpu_device *adev)
++{
++	sdma_v2_4_set_ring_funcs(adev);
++	sdma_v2_4_set_buffer_funcs(adev);
++	sdma_v2_4_set_vm_pte_funcs(adev);
++	sdma_v2_4_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int sdma_v2_4_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* SDMA trap event */
++	r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
++	if (r)
++		return r;
++
++	/* SDMA Privileged inst */
++	r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
++	if (r)
++		return r;
++
++	/* SDMA Privileged inst */
++	r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
++	if (r)
++		return r;
++
++	r = sdma_v2_4_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load sdma firmware!\n");
++		return r;
++	}
++
++	ring = &adev->sdma[0].ring;
++	ring->ring_obj = NULL;
++	ring->use_doorbell = false;
++
++	ring = &adev->sdma[1].ring;
++	ring->ring_obj = NULL;
++	ring->use_doorbell = false;
++
++	ring = &adev->sdma[0].ring;
++	sprintf(ring->name, "sdma0");
++	r = amdgpu_ring_init(adev, ring, 256 * 1024,
++			     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
++			     &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
++			     AMDGPU_RING_TYPE_SDMA);
++	if (r)
++		return r;
++
++	ring = &adev->sdma[1].ring;
++	sprintf(ring->name, "sdma1");
++	r = amdgpu_ring_init(adev, ring, 256 * 1024,
++			     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
++			     &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
++			     AMDGPU_RING_TYPE_SDMA);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int sdma_v2_4_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_ring_fini(&adev->sdma[0].ring);
++	amdgpu_ring_fini(&adev->sdma[1].ring);
++
++	return 0;
++}
++
++static int sdma_v2_4_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	sdma_v2_4_init_golden_registers(adev);
++
++	r = sdma_v2_4_start(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int sdma_v2_4_hw_fini(struct amdgpu_device *adev)
++{
++	sdma_v2_4_enable(adev, false);
++
++	return 0;
++}
++
++static int sdma_v2_4_suspend(struct amdgpu_device *adev)
++{
++
++	return sdma_v2_4_hw_fini(adev);
++}
++
++static int sdma_v2_4_resume(struct amdgpu_device *adev)
++{
++
++	return sdma_v2_4_hw_init(adev);
++}
++
++static bool sdma_v2_4_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS2);
++
++	if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
++		   SRBM_STATUS2__SDMA1_BUSY_MASK))
++	    return false;
++
++	return true;
++}
++
++static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
++				SRBM_STATUS2__SDMA1_BUSY_MASK);
++
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void sdma_v2_4_print_status(struct amdgpu_device *adev)
++{
++	int i, j;
++
++	dev_info(adev->dev, "VI SDMA registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		 RREG32(mmSRBM_STATUS2));
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
++			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
++		mutex_lock(&adev->srbm_mutex);
++		for (j = 0; j < 16; j++) {
++			vi_srbm_select(adev, 0, 0, 0, j);
++			dev_info(adev->dev, "  VM %d:\n", j);
++			dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
++				 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
++			dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
++				 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
++		}
++		vi_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++	}
++}
++
++static int sdma_v2_4_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS2);
++
++	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
++		/* sdma0 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
++		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
++	}
++	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
++		/* sdma1 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
++		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
++	}
++
++	if (srbm_soft_reset) {
++		sdma_v2_4_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		sdma_v2_4_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *src,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	u32 sdma_cntl;
++
++	switch (type) {
++	case AMDGPU_SDMA_IRQ_TRAP0:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
++			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
++			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
++			break;
++		default:
++			break;
++		}
++		break;
++	case AMDGPU_SDMA_IRQ_TRAP1:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
++			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
++			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
++			break;
++		default:
++			break;
++		}
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	u8 instance_id, queue_id;
++
++	instance_id = (entry->ring_id & 0x3) >> 0;
++	queue_id = (entry->ring_id & 0xc) >> 2;
++	DRM_DEBUG("IH: SDMA trap\n");
++	switch (instance_id) {
++	case 0:
++		switch (queue_id) {
++		case 0:
++			amdgpu_fence_process(&adev->sdma[0].ring);
++			break;
++		case 1:
++			/* XXX compute */
++			break;
++		case 2:
++			/* XXX compute */
++			break;
++		}
++		break;
++	case 1:
++		switch (queue_id) {
++		case 0:
++			amdgpu_fence_process(&adev->sdma[1].ring);
++			break;
++		case 1:
++			/* XXX compute */
++			break;
++		case 2:
++			/* XXX compute */
++			break;
++		}
++		break;
++	}
++	return 0;
++}
++
++static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
++					      struct amdgpu_irq_src *source,
++					      struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal instruction in SDMA command stream\n");
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++static int sdma_v2_4_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	/* XXX handled via the smc on VI */
++
++	return 0;
++}
++
++static int sdma_v2_4_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs = {
++	.early_init = sdma_v2_4_early_init,
++	.late_init = NULL,
++	.sw_init = sdma_v2_4_sw_init,
++	.sw_fini = sdma_v2_4_sw_fini,
++	.hw_init = sdma_v2_4_hw_init,
++	.hw_fini = sdma_v2_4_hw_fini,
++	.suspend = sdma_v2_4_suspend,
++	.resume = sdma_v2_4_resume,
++	.is_idle = sdma_v2_4_is_idle,
++	.wait_for_idle = sdma_v2_4_wait_for_idle,
++	.soft_reset = sdma_v2_4_soft_reset,
++	.print_status = sdma_v2_4_print_status,
++	.set_clockgating_state = sdma_v2_4_set_clockgating_state,
++	.set_powergating_state = sdma_v2_4_set_powergating_state,
++};
++
++/**
++ * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Check if the async DMA engine is locked up (VI).
++ * Returns true if the engine appears to be locked up, false if not.
++ */
++static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
++{
++
++	if (sdma_v2_4_is_idle(ring->adev)) {
++		amdgpu_ring_lockup_update(ring);
++		return false;
++	}
++	return amdgpu_ring_test_lockup(ring);
++}
++
++static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
++	.get_rptr = sdma_v2_4_ring_get_rptr,
++	.get_wptr = sdma_v2_4_ring_get_wptr,
++	.set_wptr = sdma_v2_4_ring_set_wptr,
++	.parse_cs = NULL,
++	.emit_ib = sdma_v2_4_ring_emit_ib,
++	.emit_fence = sdma_v2_4_ring_emit_fence,
++	.emit_semaphore = sdma_v2_4_ring_emit_semaphore,
++	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
++	.test_ring = sdma_v2_4_ring_test_ring,
++	.test_ib = sdma_v2_4_ring_test_ib,
++	.is_lockup = sdma_v2_4_ring_is_lockup,
++};
++
++static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs;
++	adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
++	.set = sdma_v2_4_set_trap_irq_state,
++	.process = sdma_v2_4_process_trap_irq,
++};
++
++static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
++	.process = sdma_v2_4_process_illegal_inst_irq,
++};
++
++static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++	adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
++	adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
++}
++
++/**
++ * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @src_offset: src GPU address
++ * @dst_offset: dst GPU address
++ * @byte_count: number of bytes to xfer
++ *
++ * Copy GPU buffers using the DMA engine (VI).
++ * Used by the amdgpu ttm implementation to move pages if
++ * registered as the asic copy callback.
++ */
++static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ring *ring,
++				       uint64_t src_offset,
++				       uint64_t dst_offset,
++				       uint32_t byte_count)
++{
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
++			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
++	amdgpu_ring_write(ring, byte_count);
++	amdgpu_ring_write(ring, 0); /* src/dst endian swap */
++	amdgpu_ring_write(ring, lower_32_bits(src_offset));
++	amdgpu_ring_write(ring, upper_32_bits(src_offset));
++	amdgpu_ring_write(ring, lower_32_bits(dst_offset));
++	amdgpu_ring_write(ring, upper_32_bits(dst_offset));
++}
++
++/**
++ * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @src_data: value to write to buffer
++ * @dst_offset: dst GPU address
++ * @byte_count: number of bytes to xfer
++ *
++ * Fill GPU buffers using the DMA engine (VI).
++ */
++static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring,
++				       uint32_t src_data,
++				       uint64_t dst_offset,
++				       uint32_t byte_count)
++{
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
++	amdgpu_ring_write(ring, lower_32_bits(dst_offset));
++	amdgpu_ring_write(ring, upper_32_bits(dst_offset));
++	amdgpu_ring_write(ring, src_data);
++	amdgpu_ring_write(ring, byte_count);
++}
++
++static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
++	.copy_max_bytes = 0x1fffff,
++	.copy_num_dw = 7,
++	.emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
++
++	.fill_max_bytes = 0x1fffff,
++	.fill_num_dw = 7,
++	.emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
++};
++
++static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
++{
++	if (adev->mman.buffer_funcs == NULL) {
++		adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
++		adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
++	}
++}
++
++static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
++	.copy_pte = sdma_v2_4_vm_copy_pte,
++	.write_pte = sdma_v2_4_vm_write_pte,
++	.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
++	.pad_ib = sdma_v2_4_vm_pad_ib,
++};
++
++static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
++{
++	if (adev->vm_manager.vm_pte_funcs == NULL) {
++		adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
++		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
+new file mode 100644
+index 0000000..6cdf894
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __SDMA_V2_4_H__
++#define __SDMA_V2_4_H__
++
++extern const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+new file mode 100644
+index 0000000..dd547c7f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -0,0 +1,1514 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Alex Deucher
++ */
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_ucode.h"
++#include "amdgpu_trace.h"
++#include "vi.h"
++#include "vid.h"
++
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "gca/gfx_8_0_d.h"
++#include "gca/gfx_8_0_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "tonga_sdma_pkt_open.h"
++
++static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
++static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
++static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
++static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
++
++MODULE_FIRMWARE("radeon/tonga_sdma.bin");
++MODULE_FIRMWARE("radeon/tonga_sdma1.bin");
++MODULE_FIRMWARE("radeon/carrizo_sdma.bin");
++MODULE_FIRMWARE("radeon/carrizo_sdma1.bin");
++
++static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
++{
++	SDMA0_REGISTER_OFFSET,
++	SDMA1_REGISTER_OFFSET
++};
++
++static const u32 golden_settings_tonga_a11[] =
++{
++	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
++	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
++	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
++	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
++	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
++	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
++	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
++	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
++	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
++	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
++};
++
++static const u32 tonga_mgcg_cgcg_init[] =
++{
++	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
++	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
++};
++
++static const u32 cz_golden_settings_a11[] =
++{
++	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
++	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
++	mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
++	mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
++	mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
++	mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
++	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
++	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
++	mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
++	mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
++	mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
++	mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
++};
++
++static const u32 cz_mgcg_cgcg_init[] =
++{
++	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
++	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
++};
++
++/*
++ * sDMA - System DMA
++ * Starting with CIK, the GPU has new asynchronous
++ * DMA engines.  These engines are used for compute
++ * and gfx.  There are two DMA engines (SDMA0, SDMA1)
++ * and each one supports 1 ring buffer used for gfx
++ * and 2 queues used for compute.
++ *
++ * The programming model is very similar to the CP
++ * (ring buffer, IBs, etc.), but sDMA has it's own
++ * packet format that is different from the PM4 format
++ * used by the CP. sDMA supports copying data, writing
++ * embedded data, solid fills, and a number of other
++ * things.  It also has support for tiling/detiling of
++ * buffers.
++ */
++
++static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_TONGA:
++		amdgpu_program_register_sequence(adev,
++						 tonga_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 golden_settings_tonga_a11,
++						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
++		break;
++	case CHIP_CARRIZO:
++		amdgpu_program_register_sequence(adev,
++						 cz_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
++		amdgpu_program_register_sequence(adev,
++						 cz_golden_settings_a11,
++						 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
++		break;
++	default:
++		break;
++	}
++}
++
++/**
++ * sdma_v3_0_init_microcode - load ucode images from disk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Use the firmware interface to load the ucode images into
++ * the driver (not loaded into hw).
++ * Returns 0 on success, error on failure.
++ */
++static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
++{
++	const char *chip_name;
++	char fw_name[30];
++	int err, i;
++	struct amdgpu_firmware_info *info = NULL;
++	const struct common_firmware_header *header = NULL;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_TONGA:
++		chip_name = "tonga";
++		break;
++	case CHIP_CARRIZO:
++		chip_name = "carrizo";
++		break;
++	default: BUG();
++	}
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		if (i == 0)
++			snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
++		else
++			snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
++		err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
++		if (err)
++			goto out;
++		err = amdgpu_ucode_validate(adev->sdma[i].fw);
++		if (err)
++			goto out;
++
++		if (adev->firmware.smu_load) {
++			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
++			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
++			info->fw = adev->sdma[i].fw;
++			header = (const struct common_firmware_header *)info->fw->data;
++			adev->firmware.fw_size +=
++				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++		}
++	}
++out:
++	if (err) {
++		printk(KERN_ERR
++		       "sdma_v3_0: Failed to load firmware \"%s\"\n",
++		       fw_name);
++		for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++			release_firmware(adev->sdma[i].fw);
++			adev->sdma[i].fw = NULL;
++		}
++	}
++	return err;
++}
++
++/**
++ * sdma_v3_0_ring_get_rptr - get the current read pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Get the current rptr from the hardware (VI+).
++ */
++static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	u32 rptr;
++
++	/* XXX check if swapping is necessary on BE */
++	rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
++
++	return rptr;
++}
++
++/**
++ * sdma_v3_0_ring_get_wptr - get the current write pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Get the current wptr from the hardware (VI+).
++ */
++static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	u32 wptr;
++
++	if (ring->use_doorbell) {
++		/* XXX check if swapping is necessary on BE */
++		wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
++	} else {
++		int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
++
++		wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
++	}
++
++	return wptr;
++}
++
++/**
++ * sdma_v3_0_ring_set_wptr - commit the write pointer
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Write the wptr back to the hardware (VI+).
++ */
++static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring->use_doorbell) {
++		/* XXX check if swapping is necessary on BE */
++		adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
++		WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
++	} else {
++		int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
++
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
++	}
++}
++
++static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *);
++
++/**
++ * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
++ *
++ * @ring: amdgpu ring pointer
++ * @ib: IB object to schedule
++ *
++ * Schedule an IB in the DMA ring (VI).
++ */
++static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
++				   struct amdgpu_ib *ib)
++{
++	u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
++	u32 next_rptr = ring->wptr + 5;
++
++	if (ib->flush_hdp_writefifo)
++		next_rptr += 6;
++
++	while ((next_rptr & 7) != 2)
++		next_rptr++;
++	next_rptr += 6;
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
++	amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
++	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
++	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
++	amdgpu_ring_write(ring, next_rptr);
++
++	/* flush HDP */
++	if (ib->flush_hdp_writefifo) {
++		sdma_v3_0_hdp_flush_ring_emit(ring);
++	}
++
++	/* IB packet must end on a 8 DW boundary */
++	while ((ring->wptr & 7) != 2)
++		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
++			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
++	/* base must be 32 byte aligned */
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, ib->length_dw);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0);
++
++}
++
++/**
++ * sdma_v3_0_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
++ *
++ * @ring: amdgpu ring pointer
++ *
++ * Emit an hdp flush packet on the requested DMA ring.
++ */
++static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *ring)
++{
++	u32 ref_and_mask = 0;
++
++	if (ring == &ring->adev->sdma[0].ring)
++		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
++	else
++		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
++	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
++	amdgpu_ring_write(ring, ref_and_mask); /* reference */
++	amdgpu_ring_write(ring, ref_and_mask); /* mask */
++	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
++			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
++}
++
++/**
++ * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
++ *
++ * @ring: amdgpu ring pointer
++ * @fence: amdgpu fence object
++ *
++ * Add a DMA fence packet to the ring to write
++ * the fence seq number and DMA trap packet to generate
++ * an interrupt if needed (VI).
++ */
++static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				      bool write64bits)
++{
++	/* write the fence */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
++	amdgpu_ring_write(ring, lower_32_bits(addr));
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++	amdgpu_ring_write(ring, lower_32_bits(seq));
++
++	/* optionally write high bits as well */
++	if (write64bits) {
++		addr += 4;
++		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
++		amdgpu_ring_write(ring, lower_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(addr));
++		amdgpu_ring_write(ring, upper_32_bits(seq));
++	}
++
++	/* generate an interrupt */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
++	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
++}
++
++
++/**
++ * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @semaphore: amdgpu semaphore object
++ * @emit_wait: wait or signal semaphore
++ *
++ * Add a DMA semaphore packet to the ring wait on or signal
++ * other rings (VI).
++ */
++static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
++					  struct amdgpu_semaphore *semaphore,
++					  bool emit_wait)
++{
++	u64 addr = semaphore->gpu_addr;
++	u32 sig = emit_wait ? 0 : 1;
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
++			  SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
++	amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++
++	return true;
++}
++
++/**
++ * sdma_v3_0_gfx_stop - stop the gfx async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the gfx async dma ring buffers (VI).
++ */
++static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
++	struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
++	u32 rb_cntl, ib_cntl;
++	int i;
++
++	if ((adev->mman.buffer_funcs_ring == sdma0) ||
++	    (adev->mman.buffer_funcs_ring == sdma1))
++		amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
++		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
++		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
++	}
++	sdma0->ready = false;
++	sdma1->ready = false;
++}
++
++/**
++ * sdma_v3_0_rlc_stop - stop the compute async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the compute async dma queues (VI).
++ */
++static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++}
++
++/**
++ * sdma_v3_0_enable - stop the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ * @enable: enable/disable the DMA MEs.
++ *
++ * Halt or unhalt the async dma engines (VI).
++ */
++static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
++{
++	u32 f32_cntl;
++	int i;
++
++	if (enable == false) {
++		sdma_v3_0_gfx_stop(adev);
++		sdma_v3_0_rlc_stop(adev);
++	}
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
++		if (enable)
++			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
++		else
++			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
++		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
++	}
++}
++
++/**
++ * sdma_v3_0_gfx_resume - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the gfx DMA ring buffers and enable them (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	u32 rb_cntl, ib_cntl;
++	u32 rb_bufsz;
++	u32 wb_offset;
++	u32 doorbell;
++	int i, j, r;
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		ring = &adev->sdma[i].ring;
++		wb_offset = (ring->rptr_offs * 4);
++
++		mutex_lock(&adev->srbm_mutex);
++		for (j = 0; j < 16; j++) {
++			vi_srbm_select(adev, 0, 0, 0, j);
++			/* SDMA GFX */
++			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
++			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
++		}
++		vi_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++
++		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
++
++		/* Set ring buffer size in dwords */
++		rb_bufsz = order_base_2(ring->ring_size / 4);
++		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
++#ifdef __BIG_ENDIAN
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
++					RPTR_WRITEBACK_SWAP_ENABLE, 1);
++#endif
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++
++		/* Initialize the ring buffer's read and write pointers */
++		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
++
++		/* set the wb address whether it's enabled or not */
++		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
++		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
++		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
++		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
++
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
++
++		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
++		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
++
++		ring->wptr = 0;
++		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
++
++		doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
++
++		if (ring->use_doorbell) {
++			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
++						 OFFSET, ring->doorbell_index);
++			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
++		} else {
++			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
++		}
++		WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
++
++		/* enable DMA RB */
++		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
++		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
++
++		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
++		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
++#ifdef __BIG_ENDIAN
++		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
++#endif
++		/* enable DMA IBs */
++		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
++
++		ring->ready = true;
++
++		r = amdgpu_ring_test_ring(ring);
++		if (r) {
++			ring->ready = false;
++			return r;
++		}
++
++		if (adev->mman.buffer_funcs_ring == ring)
++			amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
++	}
++
++	return 0;
++}
++
++/**
++ * sdma_v3_0_rlc_resume - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the compute DMA queues and enable them (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
++{
++	/* XXX todo */
++	return 0;
++}
++
++/**
++ * sdma_v3_0_load_microcode - load the sDMA ME ucode
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Loads the sDMA0/1 ucode.
++ * Returns 0 for success, -EINVAL if the ucode is not available.
++ */
++static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
++{
++	const struct sdma_firmware_header_v1_0 *hdr;
++	const __le32 *fw_data;
++	u32 fw_size;
++	int i, j;
++
++	if (!adev->sdma[0].fw || !adev->sdma[1].fw)
++		return -EINVAL;
++
++	/* halt the MEs */
++	sdma_v3_0_enable(adev, false);
++
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
++		amdgpu_ucode_print_sdma_hdr(&hdr->header);
++		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
++		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
++
++		fw_data = (const __le32 *)
++			(adev->sdma[i].fw->data +
++				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
++		for (j = 0; j < fw_size; j++)
++			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
++		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
++	}
++
++	return 0;
++}
++
++/**
++ * sdma_v3_0_start - setup and start the async dma engines
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set up the DMA engines and enable them (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v3_0_start(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (!adev->firmware.smu_load) {
++		r = sdma_v3_0_load_microcode(adev);
++		if (r)
++			return r;
++	} else {
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_SDMA0);
++		if (r)
++			return -EINVAL;
++		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
++						AMDGPU_UCODE_ID_SDMA1);
++		if (r)
++			return -EINVAL;
++	}
++
++	/* unhalt the MEs */
++	sdma_v3_0_enable(adev, true);
++
++	/* start the gfx rings and rlc compute queues */
++	r = sdma_v3_0_gfx_resume(adev);
++	if (r)
++		return r;
++	r = sdma_v3_0_rlc_resume(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++/**
++ * sdma_v3_0_ring_test_ring - simple async dma engine test
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Test the DMA engine by writing using it to write an
++ * value to memory. (VI).
++ * Returns 0 for success, error for failure.
++ */
++static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	unsigned i;
++	unsigned index;
++	int r;
++	u32 tmp;
++	u64 gpu_addr;
++
++	r = amdgpu_wb_get(adev, &index);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
++		return r;
++	}
++
++	gpu_addr = adev->wb.gpu_addr + (index * 4);
++	tmp = 0xCAFEDEAD;
++	adev->wb.wb[index] = cpu_to_le32(tmp);
++
++	r = amdgpu_ring_lock(ring, 5);
++	if (r) {
++		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
++		amdgpu_wb_free(adev, index);
++		return r;
++	}
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
++	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
++	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
++	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = le32_to_cpu(adev->wb.wb[index]);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
++			  ring->idx, tmp);
++		r = -EINVAL;
++	}
++	amdgpu_wb_free(adev, index);
++
++	return r;
++}
++
++/**
++ * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Test a simple IB in the DMA ring (VI).
++ * Returns 0 on success, error on failure.
++ */
++static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_ib ib;
++	unsigned i;
++	unsigned index;
++	int r;
++	u32 tmp = 0;
++	u64 gpu_addr;
++
++	r = amdgpu_wb_get(adev, &index);
++	if (r) {
++		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
++		return r;
++	}
++
++	gpu_addr = adev->wb.gpu_addr + (index * 4);
++	tmp = 0xCAFEDEAD;
++	adev->wb.wb[index] = cpu_to_le32(tmp);
++
++	r = amdgpu_ib_get(ring, NULL, 256, &ib);
++	if (r) {
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
++		return r;
++	}
++
++	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
++	ib.ptr[1] = lower_32_bits(gpu_addr);
++	ib.ptr[2] = upper_32_bits(gpu_addr);
++	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
++	ib.ptr[4] = 0xDEADBEEF;
++	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
++	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
++	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
++	ib.length_dw = 8;
++
++	r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
++		return r;
++	}
++	r = amdgpu_fence_wait(ib.fence, false);
++	if (r) {
++		amdgpu_ib_free(adev, &ib);
++		amdgpu_wb_free(adev, index);
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		return r;
++	}
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = le32_to_cpu(adev->wb.wb[index]);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
++			 ib.fence->ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
++		r = -EINVAL;
++	}
++	amdgpu_ib_free(adev, &ib);
++	amdgpu_wb_free(adev, index);
++	return r;
++}
++
++/**
++ * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @src: src addr to copy from
++ * @count: number of page entries to update
++ *
++ * Update PTEs by copying them from the GART using sDMA (CIK).
++ */
++static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
++				  uint64_t pe, uint64_t src,
++				  unsigned count)
++{
++	while (count) {
++		unsigned bytes = count * 8;
++		if (bytes > 0x1FFFF8)
++			bytes = 0x1FFFF8;
++
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
++			SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++		ib->ptr[ib->length_dw++] = bytes;
++		ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
++		ib->ptr[ib->length_dw++] = lower_32_bits(src);
++		ib->ptr[ib->length_dw++] = upper_32_bits(src);
++		ib->ptr[ib->length_dw++] = lower_32_bits(pe);
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++
++		pe += bytes;
++		src += bytes;
++		count -= bytes / 8;
++	}
++}
++
++/**
++ * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: access flags
++ *
++ * Update PTEs by writing them manually using sDMA (CIK).
++ */
++static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
++				   uint64_t pe,
++				   uint64_t addr, unsigned count,
++				   uint32_t incr, uint32_t flags)
++{
++	uint64_t value;
++	unsigned ndw;
++
++	while (count) {
++		ndw = count * 2;
++		if (ndw > 0xFFFFE)
++			ndw = 0xFFFFE;
++
++		/* for non-physically contiguous pages (system) */
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
++			SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++		ib->ptr[ib->length_dw++] = pe;
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++		ib->ptr[ib->length_dw++] = ndw;
++		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
++			if (flags & AMDGPU_PTE_SYSTEM) {
++				value = amdgpu_vm_map_gart(ib->ring->adev, addr);
++				value &= 0xFFFFFFFFFFFFF000ULL;
++			} else if (flags & AMDGPU_PTE_VALID) {
++				value = addr;
++			} else {
++				value = 0;
++			}
++			addr += incr;
++			value |= flags;
++			ib->ptr[ib->length_dw++] = value;
++			ib->ptr[ib->length_dw++] = upper_32_bits(value);
++		}
++	}
++}
++
++/**
++ * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
++ *
++ * @ib: indirect buffer to fill with commands
++ * @pe: addr of the page entry
++ * @addr: dst addr to write into pe
++ * @count: number of page entries to update
++ * @incr: increase next addr by incr bytes
++ * @flags: access flags
++ *
++ * Update the page tables using sDMA (CIK).
++ */
++static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
++				     uint64_t pe,
++				     uint64_t addr, unsigned count,
++				     uint32_t incr, uint32_t flags)
++{
++	uint64_t value;
++	unsigned ndw;
++
++	while (count) {
++		ndw = count;
++		if (ndw > 0x7FFFF)
++			ndw = 0x7FFFF;
++
++		if (flags & AMDGPU_PTE_VALID)
++			value = addr;
++		else
++			value = 0;
++
++		/* for physically contiguous pages (vram) */
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
++		ib->ptr[ib->length_dw++] = pe; /* dst addr */
++		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
++		ib->ptr[ib->length_dw++] = flags; /* mask */
++		ib->ptr[ib->length_dw++] = 0;
++		ib->ptr[ib->length_dw++] = value; /* value */
++		ib->ptr[ib->length_dw++] = upper_32_bits(value);
++		ib->ptr[ib->length_dw++] = incr; /* increment size */
++		ib->ptr[ib->length_dw++] = 0;
++		ib->ptr[ib->length_dw++] = ndw; /* number of entries */
++
++		pe += ndw * 8;
++		addr += ndw * incr;
++		count -= ndw;
++	}
++}
++
++/**
++ * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
++ *
++ * @ib: indirect buffer to fill with padding
++ *
++ */
++static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
++{
++	while (ib->length_dw & 0x7)
++		ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
++}
++
++/**
++ * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
++ *
++ * @ring: amdgpu_ring pointer
++ * @vm: amdgpu_vm pointer
++ *
++ * Update the page table base and flush the VM TLB
++ * using sDMA (VI).
++ */
++static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
++					 unsigned vm_id, uint64_t pd_addr)
++{
++	u32 srbm_gfx_cntl = 0;
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	if (vm_id < 8) {
++		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
++	} else {
++		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
++	}
++	amdgpu_ring_write(ring, pd_addr >> 12);
++
++	/* update SH_MEM_* regs */
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, srbm_gfx_cntl);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_BASES);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
++	amdgpu_ring_write(ring, 1);
++
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
++	amdgpu_ring_write(ring, 0);
++
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
++	amdgpu_ring_write(ring, srbm_gfx_cntl);
++
++
++	/* flush TLB */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
++			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
++	amdgpu_ring_write(ring, 1 << vm_id);
++
++	/* wait for flush */
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
++			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
++	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, 0); /* reference */
++	amdgpu_ring_write(ring, 0); /* mask */
++	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
++			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
++}
++
++static int sdma_v3_0_early_init(struct amdgpu_device *adev)
++{
++	sdma_v3_0_set_ring_funcs(adev);
++	sdma_v3_0_set_buffer_funcs(adev);
++	sdma_v3_0_set_vm_pte_funcs(adev);
++	sdma_v3_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int sdma_v3_0_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* SDMA trap event */
++	r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
++	if (r)
++		return r;
++
++	/* SDMA Privileged inst */
++	r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
++	if (r)
++		return r;
++
++	/* SDMA Privileged inst */
++	r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
++	if (r)
++		return r;
++
++	r = sdma_v3_0_init_microcode(adev);
++	if (r) {
++		DRM_ERROR("Failed to load sdma firmware!\n");
++		return r;
++	}
++
++	ring = &adev->sdma[0].ring;
++	ring->ring_obj = NULL;
++	ring->use_doorbell = true;
++	ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
++
++	ring = &adev->sdma[1].ring;
++	ring->ring_obj = NULL;
++	ring->use_doorbell = true;
++	ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
++
++	ring = &adev->sdma[0].ring;
++	sprintf(ring->name, "sdma0");
++	r = amdgpu_ring_init(adev, ring, 256 * 1024,
++			     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
++			     &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
++			     AMDGPU_RING_TYPE_SDMA);
++	if (r)
++		return r;
++
++	ring = &adev->sdma[1].ring;
++	sprintf(ring->name, "sdma1");
++	r = amdgpu_ring_init(adev, ring, 256 * 1024,
++			     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
++			     &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
++			     AMDGPU_RING_TYPE_SDMA);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int sdma_v3_0_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_ring_fini(&adev->sdma[0].ring);
++	amdgpu_ring_fini(&adev->sdma[1].ring);
++
++	return 0;
++}
++
++static int sdma_v3_0_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	sdma_v3_0_init_golden_registers(adev);
++
++	r = sdma_v3_0_start(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int sdma_v3_0_hw_fini(struct amdgpu_device *adev)
++{
++	sdma_v3_0_enable(adev, false);
++
++	return 0;
++}
++
++static int sdma_v3_0_suspend(struct amdgpu_device *adev)
++{
++
++	return sdma_v3_0_hw_fini(adev);
++}
++
++static int sdma_v3_0_resume(struct amdgpu_device *adev)
++{
++
++	return sdma_v3_0_hw_init(adev);
++}
++
++static bool sdma_v3_0_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS2);
++
++	if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
++		   SRBM_STATUS2__SDMA1_BUSY_MASK))
++	    return false;
++
++	return true;
++}
++
++static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
++				SRBM_STATUS2__SDMA1_BUSY_MASK);
++
++		if (!tmp)
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void sdma_v3_0_print_status(struct amdgpu_device *adev)
++{
++	int i, j;
++
++	dev_info(adev->dev, "VI SDMA registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		 RREG32(mmSRBM_STATUS2));
++	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
++		dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
++			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
++		dev_info(adev->dev, "  SDMA%d_GFX_DOORBELL=0x%08X\n",
++			 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
++		mutex_lock(&adev->srbm_mutex);
++		for (j = 0; j < 16; j++) {
++			vi_srbm_select(adev, 0, 0, 0, j);
++			dev_info(adev->dev, "  VM %d:\n", j);
++			dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
++				 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
++			dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
++				 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
++		}
++		vi_srbm_select(adev, 0, 0, 0, 0);
++		mutex_unlock(&adev->srbm_mutex);
++	}
++}
++
++static int sdma_v3_0_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS2);
++
++	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
++		/* sdma0 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
++		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
++	}
++	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
++		/* sdma1 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
++		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
++	}
++
++	if (srbm_soft_reset) {
++		sdma_v3_0_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		sdma_v3_0_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	u32 sdma_cntl;
++
++	switch (type) {
++	case AMDGPU_SDMA_IRQ_TRAP0:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
++			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
++			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
++			break;
++		default:
++			break;
++		}
++		break;
++	case AMDGPU_SDMA_IRQ_TRAP1:
++		switch (state) {
++		case AMDGPU_IRQ_STATE_DISABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
++			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
++			break;
++		case AMDGPU_IRQ_STATE_ENABLE:
++			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
++			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
++			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
++			break;
++		default:
++			break;
++		}
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	u8 instance_id, queue_id;
++
++	instance_id = (entry->ring_id & 0x3) >> 0;
++	queue_id = (entry->ring_id & 0xc) >> 2;
++	DRM_DEBUG("IH: SDMA trap\n");
++	switch (instance_id) {
++	case 0:
++		switch (queue_id) {
++		case 0:
++			amdgpu_fence_process(&adev->sdma[0].ring);
++			break;
++		case 1:
++			/* XXX compute */
++			break;
++		case 2:
++			/* XXX compute */
++			break;
++		}
++		break;
++	case 1:
++		switch (queue_id) {
++		case 0:
++			amdgpu_fence_process(&adev->sdma[1].ring);
++			break;
++		case 1:
++			/* XXX compute */
++			break;
++		case 2:
++			/* XXX compute */
++			break;
++		}
++		break;
++	}
++	return 0;
++}
++
++static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
++					      struct amdgpu_irq_src *source,
++					      struct amdgpu_iv_entry *entry)
++{
++	DRM_ERROR("Illegal instruction in SDMA command stream\n");
++	schedule_work(&adev->reset_work);
++	return 0;
++}
++
++static int sdma_v3_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	/* XXX handled via the smc on VI */
++
++	return 0;
++}
++
++static int sdma_v3_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs = {
++	.early_init = sdma_v3_0_early_init,
++	.late_init = NULL,
++	.sw_init = sdma_v3_0_sw_init,
++	.sw_fini = sdma_v3_0_sw_fini,
++	.hw_init = sdma_v3_0_hw_init,
++	.hw_fini = sdma_v3_0_hw_fini,
++	.suspend = sdma_v3_0_suspend,
++	.resume = sdma_v3_0_resume,
++	.is_idle = sdma_v3_0_is_idle,
++	.wait_for_idle = sdma_v3_0_wait_for_idle,
++	.soft_reset = sdma_v3_0_soft_reset,
++	.print_status = sdma_v3_0_print_status,
++	.set_clockgating_state = sdma_v3_0_set_clockgating_state,
++	.set_powergating_state = sdma_v3_0_set_powergating_state,
++};
++
++/**
++ * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ *
++ * Check if the async DMA engine is locked up (VI).
++ * Returns true if the engine appears to be locked up, false if not.
++ */
++static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
++{
++
++	if (sdma_v3_0_is_idle(ring->adev)) {
++		amdgpu_ring_lockup_update(ring);
++		return false;
++	}
++	return amdgpu_ring_test_lockup(ring);
++}
++
++static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
++	.get_rptr = sdma_v3_0_ring_get_rptr,
++	.get_wptr = sdma_v3_0_ring_get_wptr,
++	.set_wptr = sdma_v3_0_ring_set_wptr,
++	.parse_cs = NULL,
++	.emit_ib = sdma_v3_0_ring_emit_ib,
++	.emit_fence = sdma_v3_0_ring_emit_fence,
++	.emit_semaphore = sdma_v3_0_ring_emit_semaphore,
++	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
++	.test_ring = sdma_v3_0_ring_test_ring,
++	.test_ib = sdma_v3_0_ring_test_ib,
++	.is_lockup = sdma_v3_0_ring_is_lockup,
++};
++
++static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
++	adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
++	.set = sdma_v3_0_set_trap_irq_state,
++	.process = sdma_v3_0_process_trap_irq,
++};
++
++static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
++	.process = sdma_v3_0_process_illegal_inst_irq,
++};
++
++static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++	adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
++	adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
++}
++
++/**
++ * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @src_offset: src GPU address
++ * @dst_offset: dst GPU address
++ * @byte_count: number of bytes to xfer
++ *
++ * Copy GPU buffers using the DMA engine (VI).
++ * Used by the amdgpu ttm implementation to move pages if
++ * registered as the asic copy callback.
++ */
++static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring,
++				       uint64_t src_offset,
++				       uint64_t dst_offset,
++				       uint32_t byte_count)
++{
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
++			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
++	amdgpu_ring_write(ring, byte_count);
++	amdgpu_ring_write(ring, 0); /* src/dst endian swap */
++	amdgpu_ring_write(ring, lower_32_bits(src_offset));
++	amdgpu_ring_write(ring, upper_32_bits(src_offset));
++	amdgpu_ring_write(ring, lower_32_bits(dst_offset));
++	amdgpu_ring_write(ring, upper_32_bits(dst_offset));
++}
++
++/**
++ * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
++ *
++ * @ring: amdgpu_ring structure holding ring information
++ * @src_data: value to write to buffer
++ * @dst_offset: dst GPU address
++ * @byte_count: number of bytes to xfer
++ *
++ * Fill GPU buffers using the DMA engine (VI).
++ */
++static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring,
++				       uint32_t src_data,
++				       uint64_t dst_offset,
++				       uint32_t byte_count)
++{
++	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
++	amdgpu_ring_write(ring, lower_32_bits(dst_offset));
++	amdgpu_ring_write(ring, upper_32_bits(dst_offset));
++	amdgpu_ring_write(ring, src_data);
++	amdgpu_ring_write(ring, byte_count);
++}
++
++static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
++	.copy_max_bytes = 0x1fffff,
++	.copy_num_dw = 7,
++	.emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
++
++	.fill_max_bytes = 0x1fffff,
++	.fill_num_dw = 5,
++	.emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
++};
++
++static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
++{
++	if (adev->mman.buffer_funcs == NULL) {
++		adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
++		adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
++	}
++}
++
++static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
++	.copy_pte = sdma_v3_0_vm_copy_pte,
++	.write_pte = sdma_v3_0_vm_write_pte,
++	.set_pte_pde = sdma_v3_0_vm_set_pte_pde,
++	.pad_ib = sdma_v3_0_vm_pad_ib,
++};
++
++static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
++{
++	if (adev->vm_manager.vm_pte_funcs == NULL) {
++		adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
++		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
+new file mode 100644
+index 0000000..85bf2ac
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __SDMA_V3_0_H__
++#define __SDMA_V3_0_H__
++
++extern const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu8.h b/drivers/gpu/drm/amd/amdgpu/smu8.h
+new file mode 100644
+index 0000000..d758d07
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu8.h
+@@ -0,0 +1,72 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU8_H
++#define SMU8_H
++
++#pragma pack(push, 1)
++
++#define ENABLE_DEBUG_FEATURES
++
++struct SMU8_Firmware_Header {
++	uint32_t Version;
++	uint32_t ImageSize;
++	uint32_t CodeSize;
++	uint32_t HeaderSize;
++	uint32_t EntryPoint;
++	uint32_t Rtos;
++	uint32_t UcodeLoadStatus;
++	uint32_t DpmTable;
++	uint32_t FanTable;
++	uint32_t PmFuseTable;
++	uint32_t Globals;
++	uint32_t Reserved[20];
++	uint32_t Signature;
++};
++
++struct SMU8_MultimediaPowerLogData {
++	uint32_t avgTotalPower;
++	uint32_t avgGpuPower;
++	uint32_t avgUvdPower;
++	uint32_t avgVcePower;
++
++	uint32_t avgSclk;
++	uint32_t avgDclk;
++	uint32_t avgVclk;
++	uint32_t avgEclk;
++
++	uint32_t startTimeHi;
++	uint32_t startTimeLo;
++
++	uint32_t endTimeHi;
++	uint32_t endTimeLo;
++};
++
++#define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
++#define SMU8_UNBCSR_START_ADDR 0xC0100000
++
++#define SMN_MP1_SRAM_START_ADDR 0x10000000
++
++#pragma pack(pop)
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h b/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h
+new file mode 100644
+index 0000000..5c9cc3c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h
+@@ -0,0 +1,127 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU8_FUSION_H
++#define SMU8_FUSION_H
++
++#include "smu8.h"
++
++#pragma pack(push, 1)
++
++#define SMU8_MAX_CUS 2
++#define SMU8_PSMS_PER_CU 4
++#define SMU8_CACS_PER_CU 4
++
++struct SMU8_GfxCuPgScoreboard {
++    uint8_t Enabled;
++    uint8_t spare[3];
++};
++
++struct SMU8_Port80MonitorTable {
++	uint32_t MmioAddress;
++	uint32_t MemoryBaseHi;
++	uint32_t MemoryBaseLo;
++	uint16_t MemoryBufferSize;
++	uint16_t MemoryPosition;
++	uint16_t PollingInterval;
++	uint8_t  EnableCsrShadow;
++	uint8_t  EnableDramShadow;
++};
++
++/* Clock Table Definitions */
++#define NUM_SCLK_LEVELS     8
++#define NUM_LCLK_LEVELS     8
++#define NUM_UVD_LEVELS      8
++#define NUM_ECLK_LEVELS     8
++#define NUM_ACLK_LEVELS     8
++
++struct SMU8_Fusion_ClkLevel {
++	uint8_t		GnbVid;
++	uint8_t		GfxVid;
++	uint8_t		DfsDid;
++	uint8_t		DeepSleepDid;
++	uint32_t	DfsBypass;
++	uint32_t	Frequency;
++};
++
++struct SMU8_Fusion_SclkBreakdownTable {
++	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
++	struct SMU8_Fusion_ClkLevel DpmOffLevel;
++	/* SMU8_Fusion_ClkLevel PwrOffLevel; */
++	uint32_t    SclkValidMask;
++	uint32_t    MaxSclkIndex;
++};
++
++struct SMU8_Fusion_LclkBreakdownTable {
++	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
++	struct SMU8_Fusion_ClkLevel DpmOffLevel;
++    /* SMU8_Fusion_ClkLevel PwrOffLevel; */
++	uint32_t    LclkValidMask;
++	uint32_t    MaxLclkIndex;
++};
++
++struct SMU8_Fusion_EclkBreakdownTable {
++	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
++	struct SMU8_Fusion_ClkLevel DpmOffLevel;
++	struct SMU8_Fusion_ClkLevel PwrOffLevel;
++	uint32_t    EclkValidMask;
++	uint32_t    MaxEclkIndex;
++};
++
++struct SMU8_Fusion_VclkBreakdownTable {
++	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
++	struct SMU8_Fusion_ClkLevel DpmOffLevel;
++	struct SMU8_Fusion_ClkLevel PwrOffLevel;
++	uint32_t    VclkValidMask;
++	uint32_t    MaxVclkIndex;
++};
++
++struct SMU8_Fusion_DclkBreakdownTable {
++	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
++	struct SMU8_Fusion_ClkLevel DpmOffLevel;
++	struct SMU8_Fusion_ClkLevel PwrOffLevel;
++	uint32_t    DclkValidMask;
++	uint32_t    MaxDclkIndex;
++};
++
++struct SMU8_Fusion_AclkBreakdownTable {
++	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
++	struct SMU8_Fusion_ClkLevel DpmOffLevel;
++	struct SMU8_Fusion_ClkLevel PwrOffLevel;
++	uint32_t    AclkValidMask;
++	uint32_t    MaxAclkIndex;
++};
++
++
++struct SMU8_Fusion_ClkTable {
++	struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
++	struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
++	struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
++	struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
++	struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
++	struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
++};
++
++#pragma pack(pop)
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h
+new file mode 100644
+index 0000000..f8ba071
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h
+@@ -0,0 +1,147 @@
++// CZ Ucode Loading Definitions
++#ifndef SMU_UCODE_XFER_CZ_H
++#define SMU_UCODE_XFER_CZ_H
++
++#define NUM_JOBLIST_ENTRIES      32
++
++#define TASK_TYPE_NO_ACTION      0
++#define TASK_TYPE_UCODE_LOAD     1
++#define TASK_TYPE_UCODE_SAVE     2
++#define TASK_TYPE_REG_LOAD       3
++#define TASK_TYPE_REG_SAVE       4
++#define TASK_TYPE_INITIALIZE     5
++
++#define TASK_ARG_REG_SMCIND      0
++#define TASK_ARG_REG_MMIO        1
++#define TASK_ARG_REG_FCH         2
++#define TASK_ARG_REG_UNB         3
++
++#define TASK_ARG_INIT_MM_PWR_LOG 0
++#define TASK_ARG_INIT_CLK_TABLE  1
++
++#define JOB_GFX_SAVE             0
++#define JOB_GFX_RESTORE          1
++#define JOB_FCH_SAVE             2
++#define JOB_FCH_RESTORE          3
++#define JOB_UNB_SAVE             4
++#define JOB_UNB_RESTORE          5
++#define JOB_GMC_SAVE             6
++#define JOB_GMC_RESTORE          7
++#define JOB_GNB_SAVE             8
++#define JOB_GNB_RESTORE          9
++
++#define IGNORE_JOB               0xff
++#define END_OF_TASK_LIST     (uint16_t)0xffff
++
++// Size of DRAM regions (in bytes) requested by SMU:
++#define SMU_DRAM_REQ_MM_PWR_LOG 48 
++
++#define UCODE_ID_SDMA0           0
++#define UCODE_ID_SDMA1           1
++#define UCODE_ID_CP_CE           2
++#define UCODE_ID_CP_PFP          3
++#define UCODE_ID_CP_ME           4
++#define UCODE_ID_CP_MEC_JT1      5
++#define UCODE_ID_CP_MEC_JT2      6
++#define UCODE_ID_GMCON_RENG      7
++#define UCODE_ID_RLC_G           8
++#define UCODE_ID_RLC_SCRATCH     9
++#define UCODE_ID_RLC_SRM_ARAM    10
++#define UCODE_ID_RLC_SRM_DRAM    11
++#define UCODE_ID_DMCU_ERAM       12
++#define UCODE_ID_DMCU_IRAM       13
++
++#define UCODE_ID_SDMA0_MASK           0x00000001       
++#define UCODE_ID_SDMA1_MASK           0x00000002        
++#define UCODE_ID_CP_CE_MASK           0x00000004      
++#define UCODE_ID_CP_PFP_MASK          0x00000008         
++#define UCODE_ID_CP_ME_MASK           0x00000010          
++#define UCODE_ID_CP_MEC_JT1_MASK      0x00000020             
++#define UCODE_ID_CP_MEC_JT2_MASK      0x00000040          
++#define UCODE_ID_GMCON_RENG_MASK      0x00000080            
++#define UCODE_ID_RLC_G_MASK           0x00000100           
++#define UCODE_ID_RLC_SCRATCH_MASK     0x00000200         
++#define UCODE_ID_RLC_SRM_ARAM_MASK    0x00000400                
++#define UCODE_ID_RLC_SRM_DRAM_MASK    0x00000800                 
++#define UCODE_ID_DMCU_ERAM_MASK       0x00001000             
++#define UCODE_ID_DMCU_IRAM_MASK       0x00002000              
++
++#define UCODE_ID_SDMA0_SIZE_BYTE           10368        
++#define UCODE_ID_SDMA1_SIZE_BYTE           10368          
++#define UCODE_ID_CP_CE_SIZE_BYTE           8576        
++#define UCODE_ID_CP_PFP_SIZE_BYTE          16768           
++#define UCODE_ID_CP_ME_SIZE_BYTE           16768            
++#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE      384               
++#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE      384            
++#define UCODE_ID_GMCON_RENG_SIZE_BYTE      4096              
++#define UCODE_ID_RLC_G_SIZE_BYTE           2048             
++#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE     132           
++#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE    8192                  
++#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE    4096                   
++#define UCODE_ID_DMCU_ERAM_SIZE_BYTE       24576               
++#define UCODE_ID_DMCU_IRAM_SIZE_BYTE       1024                 
++
++#define NUM_UCODES               14
++
++typedef struct {
++	uint32_t high;
++	uint32_t low;
++} data_64_t;
++
++struct SMU_Task {
++    uint8_t type;
++    uint8_t arg;
++    uint16_t next;
++    data_64_t addr;
++    uint32_t size_bytes;
++};
++typedef struct SMU_Task SMU_Task;
++
++struct TOC {
++    uint8_t JobList[NUM_JOBLIST_ENTRIES];
++    SMU_Task tasks[1];
++};
++
++// META DATA COMMAND Definitions
++#define METADATA_CMD_MODE0         0x00000103 
++#define METADATA_CMD_MODE1         0x00000113 
++#define METADATA_CMD_MODE2         0x00000123 
++#define METADATA_CMD_MODE3         0x00000133
++#define METADATA_CMD_DELAY         0x00000203
++#define METADATA_CMD_CHNG_REGSPACE 0x00000303
++#define METADATA_PERFORM_ON_SAVE   0x00001000
++#define METADATA_PERFORM_ON_LOAD   0x00002000
++#define METADATA_CMD_ARG_MASK      0xFFFF0000
++#define METADATA_CMD_ARG_SHIFT     16
++
++// Simple register addr/data fields
++struct SMU_MetaData_Mode0 {
++    uint32_t register_address;
++    uint32_t register_data;
++};
++typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0;
++
++// Register addr/data with mask
++struct SMU_MetaData_Mode1 {
++    uint32_t register_address;
++    uint32_t register_mask;
++    uint32_t register_data;
++};
++typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1;
++
++struct SMU_MetaData_Mode2 {
++    uint32_t register_address;
++    uint32_t register_mask;
++    uint32_t target_value;
++};
++typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2;
++
++// Always write data (even on a save operation)
++struct SMU_MetaData_Mode3 {
++    uint32_t register_address;
++    uint32_t register_mask;
++    uint32_t register_data;
++};
++typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
+new file mode 100644
+index 0000000..c24a81e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
+@@ -0,0 +1,100 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU_UCODE_XFER_VI_H
++#define SMU_UCODE_XFER_VI_H
++
++#define SMU_DRAMData_TOC_VERSION  1
++#define MAX_IH_REGISTER_COUNT     65535
++#define SMU_DIGEST_SIZE_BYTES     20
++#define SMU_FB_SIZE_BYTES         1048576
++#define SMU_MAX_ENTRIES           12
++
++#define UCODE_ID_SMU              0
++#define UCODE_ID_SDMA0            1
++#define UCODE_ID_SDMA1            2
++#define UCODE_ID_CP_CE            3
++#define UCODE_ID_CP_PFP           4
++#define UCODE_ID_CP_ME            5
++#define UCODE_ID_CP_MEC           6
++#define UCODE_ID_CP_MEC_JT1       7
++#define UCODE_ID_CP_MEC_JT2       8
++#define UCODE_ID_GMCON_RENG       9
++#define UCODE_ID_RLC_G            10
++#define UCODE_ID_IH_REG_RESTORE   11
++#define UCODE_ID_VBIOS            12
++#define UCODE_ID_MISC_METADATA    13
++#define UCODE_ID_RLC_SCRATCH      32
++#define UCODE_ID_RLC_SRM_ARAM     33
++#define UCODE_ID_RLC_SRM_DRAM     34
++#define UCODE_ID_MEC_STORAGE      35
++#define UCODE_ID_VBIOS_PARAMETERS 36
++#define UCODE_META_DATA           0xFF
++
++#define UCODE_ID_SMU_MASK             0x00000001
++#define UCODE_ID_SDMA0_MASK           0x00000002
++#define UCODE_ID_SDMA1_MASK           0x00000004
++#define UCODE_ID_CP_CE_MASK           0x00000008
++#define UCODE_ID_CP_PFP_MASK          0x00000010
++#define UCODE_ID_CP_ME_MASK           0x00000020
++#define UCODE_ID_CP_MEC_MASK          0x00000040
++#define UCODE_ID_CP_MEC_JT1_MASK      0x00000080
++#define UCODE_ID_CP_MEC_JT2_MASK      0x00000100
++#define UCODE_ID_GMCON_RENG_MASK      0x00000200
++#define UCODE_ID_RLC_G_MASK           0x00000400
++#define UCODE_ID_IH_REG_RESTORE_MASK  0x00000800
++#define UCODE_ID_VBIOS_MASK           0x00001000
++
++#define UCODE_FLAG_UNHALT_MASK   0x1
++
++struct SMU_Entry {
++#ifndef __BIG_ENDIAN
++	uint16_t id;
++	uint16_t version;
++	uint32_t image_addr_high;
++	uint32_t image_addr_low;
++	uint32_t meta_data_addr_high;
++	uint32_t meta_data_addr_low;
++	uint32_t data_size_byte;
++	uint16_t flags;
++	uint16_t num_register_entries;
++#else
++	uint16_t version;
++	uint16_t id;
++	uint32_t image_addr_high;
++	uint32_t image_addr_low;
++	uint32_t meta_data_addr_high;
++	uint32_t meta_data_addr_low;
++	uint32_t data_size_byte;
++	uint16_t num_register_entries;
++	uint16_t flags;
++#endif
++};
++
++struct SMU_DRAMData_TOC {
++	uint32_t structure_version;
++	uint32_t num_entries;
++	struct SMU_Entry entry[SMU_MAX_ENTRIES];
++};
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+new file mode 100644
+index 0000000..98bd707
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+@@ -0,0 +1,172 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "tonga_smumgr.h"
++
++MODULE_FIRMWARE("radeon/tonga_smc.bin");
++
++static void tonga_dpm_set_funcs(struct amdgpu_device *adev);
++
++static int tonga_dpm_early_init(struct amdgpu_device *adev)
++{
++	tonga_dpm_set_funcs(adev);
++
++	return 0;
++}
++
++static int tonga_dpm_init_microcode(struct amdgpu_device *adev)
++{
++	char fw_name[30] = "radeon/tonga_smc.bin";
++	int err;
++
++	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++	err = amdgpu_ucode_validate(adev->pm.fw);
++
++out:
++	if (err) {
++		DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
++		release_firmware(adev->pm.fw);
++		adev->pm.fw = NULL;
++	}
++	return err;
++}
++
++static int tonga_dpm_sw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	ret = tonga_dpm_init_microcode(adev);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int tonga_dpm_sw_fini(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int tonga_dpm_hw_init(struct amdgpu_device *adev)
++{
++	int ret;
++
++	mutex_lock(&adev->pm.mutex);
++
++	ret = tonga_smu_init(adev);
++	if (ret) {
++		DRM_ERROR("SMU initialization failed\n");
++		goto fail;
++	}
++
++	ret = tonga_smu_start(adev);
++	if (ret) {
++		DRM_ERROR("SMU start failed\n");
++		goto fail;
++	}
++
++	mutex_unlock(&adev->pm.mutex);
++	return 0;
++
++fail:
++	adev->firmware.smu_load = false;
++	mutex_unlock(&adev->pm.mutex);
++	return -EINVAL;
++}
++
++static int tonga_dpm_hw_fini(struct amdgpu_device *adev)
++{
++	mutex_lock(&adev->pm.mutex);
++	tonga_smu_fini(adev);
++	mutex_unlock(&adev->pm.mutex);
++	return 0;
++}
++
++static int tonga_dpm_suspend(struct amdgpu_device *adev)
++{
++	tonga_dpm_hw_fini(adev);
++
++	return 0;
++}
++
++static int tonga_dpm_resume(struct amdgpu_device *adev)
++{
++	tonga_dpm_hw_init(adev);
++
++	return 0;
++}
++
++static int tonga_dpm_set_clockgating_state(struct amdgpu_device *adev,
++			enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int tonga_dpm_set_powergating_state(struct amdgpu_device *adev,
++			enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs tonga_dpm_ip_funcs = {
++	.early_init = tonga_dpm_early_init,
++	.late_init = NULL,
++	.sw_init = tonga_dpm_sw_init,
++	.sw_fini = tonga_dpm_sw_fini,
++	.hw_init = tonga_dpm_hw_init,
++	.hw_fini = tonga_dpm_hw_fini,
++	.suspend = tonga_dpm_suspend,
++	.resume = tonga_dpm_resume,
++	.is_idle = NULL,
++	.wait_for_idle = NULL,
++	.soft_reset = NULL,
++	.print_status = NULL,
++	.set_clockgating_state = tonga_dpm_set_clockgating_state,
++	.set_powergating_state = tonga_dpm_set_powergating_state,
++};
++
++static const struct amdgpu_dpm_funcs tonga_dpm_funcs = {
++	.get_temperature = NULL,
++	.pre_set_power_state = NULL,
++	.set_power_state = NULL,
++	.post_set_power_state = NULL,
++	.display_configuration_changed = NULL,
++	.get_sclk = NULL,
++	.get_mclk = NULL,
++	.print_power_state = NULL,
++	.debugfs_print_current_performance_level = NULL,
++	.force_performance_level = NULL,
++	.vblank_too_short = NULL,
++	.powergate_uvd = NULL,
++};
++
++static void tonga_dpm_set_funcs(struct amdgpu_device *adev)
++{
++	if (NULL == adev->pm.funcs)
++		adev->pm.funcs = &tonga_dpm_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+new file mode 100644
+index 0000000..cff1b8b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+@@ -0,0 +1,458 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_ih.h"
++#include "vid.h"
++
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++
++#include "bif/bif_5_1_d.h"
++#include "bif/bif_5_1_sh_mask.h"
++
++/*
++ * Interrupts
++ * Starting with r6xx, interrupts are handled via a ring buffer.
++ * Ring buffers are areas of GPU accessible memory that the GPU
++ * writes interrupt vectors into and the host reads vectors out of.
++ * There is a rptr (read pointer) that determines where the
++ * host is currently reading, and a wptr (write pointer)
++ * which determines where the GPU has written.  When the
++ * pointers are equal, the ring is idle.  When the GPU
++ * writes vectors to the ring buffer, it increments the
++ * wptr.  When there is an interrupt, the host then starts
++ * fetching commands and processing them until the pointers are
++ * equal again at which point it updates the rptr.
++ */
++
++static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
++
++/**
++ * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Enable the interrupt ring buffer (VI).
++ */
++static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	adev->irq.ih.enabled = true;
++}
++
++/**
++ * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable the interrupt ring buffer (VI).
++ */
++static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
++{
++	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
++
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++	adev->irq.ih.enabled = false;
++	adev->irq.ih.rptr = 0;
++}
++
++/**
++ * tonga_ih_irq_init - init and enable the interrupt ring
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Allocate a ring buffer for the interrupt controller,
++ * enable the RLC, disable interrupts, enable the IH
++ * ring buffer and enable it (VI).
++ * Called at device load and reume.
++ * Returns 0 for success, errors for failure.
++ */
++static int tonga_ih_irq_init(struct amdgpu_device *adev)
++{
++	int ret = 0;
++	int rb_bufsz;
++	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
++	u64 wptr_off;
++
++	/* disable irqs */
++	tonga_ih_disable_interrupts(adev);
++
++	/* setup interrupt control */
++	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
++	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
++	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
++	 */
++	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
++	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
++	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
++	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
++
++	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
++	if (adev->irq.ih.use_bus_addr)
++		WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
++	else
++		WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
++
++	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
++	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
++	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
++	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
++
++	if (adev->irq.msi_enabled)
++		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
++
++	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
++
++	/* set the writeback address whether it's enabled or not */
++	if (adev->irq.ih.use_bus_addr)
++		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
++	else
++		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
++	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
++	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
++
++	/* set rptr, wptr to 0 */
++	WREG32(mmIH_RB_RPTR, 0);
++	WREG32(mmIH_RB_WPTR, 0);
++
++	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
++	if (adev->irq.ih.use_doorbell) {
++		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
++						 OFFSET, adev->irq.ih.doorbell_index);
++		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
++						 ENABLE, 1);
++	} else {
++		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
++						 ENABLE, 0);
++	}
++	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
++
++	pci_set_master(adev->pdev);
++
++	/* enable interrupts */
++	tonga_ih_enable_interrupts(adev);
++
++	return ret;
++}
++
++/**
++ * tonga_ih_irq_disable - disable interrupts
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Disable interrupts on the hw (VI).
++ */
++static void tonga_ih_irq_disable(struct amdgpu_device *adev)
++{
++	tonga_ih_disable_interrupts(adev);
++
++	/* Wait and acknowledge irq */
++	mdelay(1);
++}
++
++/**
++ * tonga_ih_get_wptr - get the IH ring buffer wptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Get the IH ring buffer wptr from either the register
++ * or the writeback memory buffer (VI).  Also check for
++ * ring buffer overflow and deal with it.
++ * Used by cz_irq_process(VI).
++ * Returns the value of the wptr.
++ */
++static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
++{
++	u32 wptr, tmp;
++
++	if (adev->irq.ih.use_bus_addr)
++		wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
++	else
++		wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
++
++	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
++		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
++		/* When a ring buffer overflow happen start parsing interrupt
++		 * from the last not overwritten vector (wptr + 16). Hopefully
++		 * this should allow us to catchup.
++		 */
++		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
++			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
++		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
++		tmp = RREG32(mmIH_RB_CNTL);
++		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
++		WREG32(mmIH_RB_CNTL, tmp);
++	}
++	return (wptr & adev->irq.ih.ptr_mask);
++}
++
++/**
++ * tonga_ih_decode_iv - decode an interrupt vector
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Decodes the interrupt vector at the current rptr
++ * position and also advance the position.
++ */
++static void tonga_ih_decode_iv(struct amdgpu_device *adev,
++				 struct amdgpu_iv_entry *entry)
++{
++	/* wptr/rptr are in bytes! */
++	u32 ring_index = adev->irq.ih.rptr >> 2;
++	uint32_t dw[4];
++
++	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
++	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
++	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
++	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
++
++	entry->src_id = dw[0] & 0xff;
++	entry->src_data = dw[1] & 0xfffffff;
++	entry->ring_id = dw[2] & 0xff;
++	entry->vm_id = (dw[2] >> 8) & 0xff;
++	entry->pas_id = (dw[2] >> 16) & 0xffff;
++
++	/* wptr/rptr are in bytes! */
++	adev->irq.ih.rptr += 16;
++}
++
++/**
++ * tonga_ih_set_rptr - set the IH ring buffer rptr
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Set the IH ring buffer rptr.
++ */
++static void tonga_ih_set_rptr(struct amdgpu_device *adev)
++{
++	if (adev->irq.ih.use_doorbell) {
++		/* XXX check if swapping is necessary on BE */
++		if (adev->irq.ih.use_bus_addr)
++			adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
++		else
++			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
++		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
++	} else {
++		WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
++	}
++}
++
++static int tonga_ih_early_init(struct amdgpu_device *adev)
++{
++	tonga_ih_set_interrupt_funcs(adev);
++	return 0;
++}
++
++static int tonga_ih_sw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_ih_ring_init(adev, 4 * 1024, true);
++	if (r)
++		return r;
++
++	adev->irq.ih.use_doorbell = true;
++	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;
++
++	r = amdgpu_irq_init(adev);
++
++	return r;
++}
++
++static int tonga_ih_sw_fini(struct amdgpu_device *adev)
++{
++	amdgpu_irq_fini(adev);
++	amdgpu_ih_ring_fini(adev);
++
++	return 0;
++}
++
++static int tonga_ih_hw_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = tonga_ih_irq_init(adev);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static int tonga_ih_hw_fini(struct amdgpu_device *adev)
++{
++	tonga_ih_irq_disable(adev);
++
++	return 0;
++}
++
++static int tonga_ih_suspend(struct amdgpu_device *adev)
++{
++	return tonga_ih_hw_fini(adev);
++}
++
++static int tonga_ih_resume(struct amdgpu_device *adev)
++{
++	return tonga_ih_hw_init(adev);
++}
++
++static bool tonga_ih_is_idle(struct amdgpu_device *adev)
++{
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
++		return false;
++
++	return true;
++}
++
++static int tonga_ih_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++	u32 tmp;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		/* read MC_STATUS */
++		tmp = RREG32(mmSRBM_STATUS);
++		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
++			return 0;
++		udelay(1);
++	}
++	return -ETIMEDOUT;
++}
++
++static void tonga_ih_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "TONGA IH registers\n");
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL));
++	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
++		 RREG32(mmINTERRUPT_CNTL2));
++	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
++		 RREG32(mmIH_CNTL));
++	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
++		 RREG32(mmIH_RB_CNTL));
++	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
++		 RREG32(mmIH_RB_BASE));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_LO));
++	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR_ADDR_HI));
++	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
++		 RREG32(mmIH_RB_RPTR));
++	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
++		 RREG32(mmIH_RB_WPTR));
++}
++
++static int tonga_ih_soft_reset(struct amdgpu_device *adev)
++{
++	u32 srbm_soft_reset = 0;
++	u32 tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
++						SOFT_RESET_IH, 1);
++
++	if (srbm_soft_reset) {
++		tonga_ih_print_status(adev);
++
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		/* Wait a little for things to settle down */
++		udelay(50);
++
++		tonga_ih_print_status(adev);
++	}
++
++	return 0;
++}
++
++static int tonga_ih_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	// TODO
++	return 0;
++}
++
++static int tonga_ih_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	// TODO
++	return 0;
++}
++
++const struct amdgpu_ip_funcs tonga_ih_ip_funcs = {
++	.early_init = tonga_ih_early_init,
++	.late_init = NULL,
++	.sw_init = tonga_ih_sw_init,
++	.sw_fini = tonga_ih_sw_fini,
++	.hw_init = tonga_ih_hw_init,
++	.hw_fini = tonga_ih_hw_fini,
++	.suspend = tonga_ih_suspend,
++	.resume = tonga_ih_resume,
++	.is_idle = tonga_ih_is_idle,
++	.wait_for_idle = tonga_ih_wait_for_idle,
++	.soft_reset = tonga_ih_soft_reset,
++	.print_status = tonga_ih_print_status,
++	.set_clockgating_state = tonga_ih_set_clockgating_state,
++	.set_powergating_state = tonga_ih_set_powergating_state,
++};
++
++static const struct amdgpu_ih_funcs tonga_ih_funcs = {
++	.get_wptr = tonga_ih_get_wptr,
++	.decode_iv = tonga_ih_decode_iv,
++	.set_rptr = tonga_ih_set_rptr
++};
++
++static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
++{
++	if (adev->irq.ih_funcs == NULL)
++		adev->irq.ih_funcs = &tonga_ih_funcs;
++}
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
+new file mode 100644
+index 0000000..7c9bae8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __TONGA_IH_H__
++#define __TONGA_IH_H__
++
++extern const struct amdgpu_ip_funcs tonga_ih_ip_funcs;
++
++#endif /* __CZ_IH_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
+new file mode 100644
+index 0000000..811781f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
+@@ -0,0 +1,198 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef TONGA_PP_SMC_H
++#define TONGA_PP_SMC_H
++
++#pragma pack(push, 1)
++
++#define PPSMC_SWSTATE_FLAG_DC                           0x01
++#define PPSMC_SWSTATE_FLAG_UVD                          0x02
++#define PPSMC_SWSTATE_FLAG_VCE                          0x04
++#define PPSMC_SWSTATE_FLAG_PCIE_X1                      0x08
++
++#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
++#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
++#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff 
++
++#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01 
++#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02 
++#define PPSMC_SYSTEMFLAG_GDDR5                          0x04 
++
++#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08 
++
++#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10 
++#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20 
++#define PPSMC_SYSTEMFLAG_12CHANNEL                      0x40
++
++#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
++#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
++
++#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
++#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
++
++#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH      0x10
++#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17               0x20
++#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17                  0x40
++
++#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01 
++#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02 
++#define PPSMC_DPM2FLAGS_OCP                             0x04 
++
++#define PPSMC_DISPLAY_WATERMARK_LOW                     0
++#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
++
++#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    		0x01
++#define PPSMC_STATEFLAG_POWERBOOST         		0x02
++#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 		0x04
++#define PPSMC_STATEFLAG_POWERSHIFT         		0x08
++#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   		0x10
++#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 		0x20
++#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   		0x40
++
++#define FDO_MODE_HARDWARE 0
++#define FDO_MODE_PIECE_WISE_LINEAR 1
++
++enum FAN_CONTROL {
++	FAN_CONTROL_FUZZY,
++	FAN_CONTROL_TABLE
++};
++
++#define PPSMC_Result_OK             			((uint16_t)0x01)
++#define PPSMC_Result_NoMore         			((uint16_t)0x02)
++#define PPSMC_Result_NotNow         			((uint16_t)0x03)
++#define PPSMC_Result_Failed         			((uint16_t)0xFF) 
++#define PPSMC_Result_UnknownCmd     			((uint16_t)0xFE) 
++#define PPSMC_Result_UnknownVT      			((uint16_t)0xFD) 
++
++typedef uint16_t PPSMC_Result;
++
++#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
++
++#define PPSMC_MSG_Halt                      		((uint16_t)0x10)
++#define PPSMC_MSG_Resume                    		((uint16_t)0x11)
++#define PPSMC_MSG_EnableDPMLevel            		((uint16_t)0x12)
++#define PPSMC_MSG_ZeroLevelsDisabled        		((uint16_t)0x13)
++#define PPSMC_MSG_OneLevelsDisabled         		((uint16_t)0x14)
++#define PPSMC_MSG_TwoLevelsDisabled         		((uint16_t)0x15)
++#define PPSMC_MSG_EnableThermalInterrupt    		((uint16_t)0x16)
++#define PPSMC_MSG_RunningOnAC               		((uint16_t)0x17)
++#define PPSMC_MSG_LevelUp                   		((uint16_t)0x18)
++#define PPSMC_MSG_LevelDown                 		((uint16_t)0x19)
++#define PPSMC_MSG_ResetDPMCounters          		((uint16_t)0x1a)
++#define PPSMC_MSG_SwitchToSwState           		((uint16_t)0x20)
++#define PPSMC_MSG_SwitchToSwStateLast       		((uint16_t)0x3f)
++#define PPSMC_MSG_SwitchToInitialState      		((uint16_t)0x40)
++#define PPSMC_MSG_NoForcedLevel             		((uint16_t)0x41)
++#define PPSMC_MSG_ForceHigh                 		((uint16_t)0x42)
++#define PPSMC_MSG_ForceMediumOrHigh         		((uint16_t)0x43)
++#define PPSMC_MSG_SwitchToMinimumPower      		((uint16_t)0x51)
++#define PPSMC_MSG_ResumeFromMinimumPower    		((uint16_t)0x52)
++#define PPSMC_MSG_EnableCac                 		((uint16_t)0x53)
++#define PPSMC_MSG_DisableCac                		((uint16_t)0x54)
++#define PPSMC_DPMStateHistoryStart          		((uint16_t)0x55)
++#define PPSMC_DPMStateHistoryStop           		((uint16_t)0x56)
++#define PPSMC_CACHistoryStart               		((uint16_t)0x57)
++#define PPSMC_CACHistoryStop                		((uint16_t)0x58)
++#define PPSMC_TDPClampingActive             		((uint16_t)0x59)
++#define PPSMC_TDPClampingInactive           		((uint16_t)0x5A)
++#define PPSMC_StartFanControl               		((uint16_t)0x5B)
++#define PPSMC_StopFanControl                		((uint16_t)0x5C)
++#define PPSMC_NoDisplay                     		((uint16_t)0x5D)
++#define PPSMC_HasDisplay                    		((uint16_t)0x5E)
++#define PPSMC_MSG_UVDPowerOFF               		((uint16_t)0x60)
++#define PPSMC_MSG_UVDPowerON                		((uint16_t)0x61)
++#define PPSMC_MSG_EnableULV                 		((uint16_t)0x62)
++#define PPSMC_MSG_DisableULV                		((uint16_t)0x63)
++#define PPSMC_MSG_EnterULV                  		((uint16_t)0x64)
++#define PPSMC_MSG_ExitULV                   		((uint16_t)0x65)
++#define PPSMC_PowerShiftActive              		((uint16_t)0x6A)
++#define PPSMC_PowerShiftInactive            		((uint16_t)0x6B)
++#define PPSMC_OCPActive                     		((uint16_t)0x6C)
++#define PPSMC_OCPInactive                   		((uint16_t)0x6D)
++#define PPSMC_CACLongTermAvgEnable          		((uint16_t)0x6E)
++#define PPSMC_CACLongTermAvgDisable         		((uint16_t)0x6F)
++#define PPSMC_MSG_InferredStateSweep_Start  		((uint16_t)0x70)
++#define PPSMC_MSG_InferredStateSweep_Stop   		((uint16_t)0x71)
++#define PPSMC_MSG_SwitchToLowestInfState    		((uint16_t)0x72)
++#define PPSMC_MSG_SwitchToNonInfState       		((uint16_t)0x73)
++#define PPSMC_MSG_AllStateSweep_Start       		((uint16_t)0x74)
++#define PPSMC_MSG_AllStateSweep_Stop        		((uint16_t)0x75)
++#define PPSMC_MSG_SwitchNextLowerInfState   		((uint16_t)0x76)
++#define PPSMC_MSG_SwitchNextHigherInfState  		((uint16_t)0x77)
++#define PPSMC_MSG_MclkRetrainingTest        		((uint16_t)0x78)
++#define PPSMC_MSG_ForceTDPClamping          		((uint16_t)0x79)
++#define PPSMC_MSG_CollectCAC_PowerCorreln   		((uint16_t)0x7A)
++#define PPSMC_MSG_CollectCAC_WeightCalib    		((uint16_t)0x7B)
++#define PPSMC_MSG_CollectCAC_SQonly         		((uint16_t)0x7C)
++#define PPSMC_MSG_CollectCAC_TemperaturePwr 		((uint16_t)0x7D)
++#define PPSMC_MSG_ExtremitiesTest_Start     		((uint16_t)0x7E)
++#define PPSMC_MSG_ExtremitiesTest_Stop      		((uint16_t)0x7F)
++#define PPSMC_FlushDataCache                		((uint16_t)0x80)
++#define PPSMC_FlushInstrCache               		((uint16_t)0x81)
++#define PPSMC_MSG_SetEnabledLevels          		((uint16_t)0x82)
++#define PPSMC_MSG_SetForcedLevels           		((uint16_t)0x83)
++#define PPSMC_MSG_ResetToDefaults           		((uint16_t)0x84)
++#define PPSMC_MSG_SetForcedLevelsAndJump    		((uint16_t)0x85)
++#define PPSMC_MSG_SetCACHistoryMode         		((uint16_t)0x86)
++#define PPSMC_MSG_EnableDTE                 		((uint16_t)0x87)
++#define PPSMC_MSG_DisableDTE                		((uint16_t)0x88)
++#define PPSMC_MSG_SmcSpaceSetAddress        		((uint16_t)0x89)
++#define PPSMC_MSG_SmcSpaceWriteDWordInc     		((uint16_t)0x8A)
++#define PPSMC_MSG_SmcSpaceWriteWordInc      		((uint16_t)0x8B)
++#define PPSMC_MSG_SmcSpaceWriteByteInc      		((uint16_t)0x8C)
++#define PPSMC_MSG_ChangeNearTDPLimit        		((uint16_t)0x90)
++#define PPSMC_MSG_ChangeSafePowerLimit      		((uint16_t)0x91)
++#define PPSMC_MSG_DPMStateSweepStart        		((uint16_t)0x92)
++#define PPSMC_MSG_DPMStateSweepStop         		((uint16_t)0x93)
++#define PPSMC_MSG_OVRDDisableSCLKDS         		((uint16_t)0x94)
++#define PPSMC_MSG_CancelDisableOVRDSCLKDS   		((uint16_t)0x95)
++#define PPSMC_MSG_ThrottleOVRDSCLKDS        		((uint16_t)0x96)
++#define PPSMC_MSG_CancelThrottleOVRDSCLKDS  		((uint16_t)0x97)
++#define PPSMC_MSG_GPIO17                    		((uint16_t)0x98)
++#define PPSMC_MSG_API_SetSvi2Volt_Vddc      		((uint16_t)0x99)
++#define PPSMC_MSG_API_SetSvi2Volt_Vddci     		((uint16_t)0x9A)
++#define PPSMC_MSG_API_SetSvi2Volt_Mvdd      		((uint16_t)0x9B)
++#define PPSMC_MSG_API_GetSvi2Volt_Vddc      		((uint16_t)0x9C)
++#define PPSMC_MSG_API_GetSvi2Volt_Vddci     		((uint16_t)0x9D)
++#define PPSMC_MSG_API_GetSvi2Volt_Mvdd      		((uint16_t)0x9E)
++
++#define PPSMC_MSG_BREAK                     		((uint16_t)0xF8)
++
++#define PPSMC_MSG_Test                      		((uint16_t)0x100)
++#define PPSMC_MSG_DRV_DRAM_ADDR_HI            		((uint16_t)0x250)
++#define PPSMC_MSG_DRV_DRAM_ADDR_LO            		((uint16_t)0x251)
++#define PPSMC_MSG_SMU_DRAM_ADDR_HI            		((uint16_t)0x252)
++#define PPSMC_MSG_SMU_DRAM_ADDR_LO            		((uint16_t)0x253)
++#define PPSMC_MSG_LoadUcodes                  		((uint16_t)0x254)
++
++typedef uint16_t PPSMC_Msg;
++
++#define PPSMC_EVENT_STATUS_THERMAL          		0x00000001
++#define PPSMC_EVENT_STATUS_REGULATORHOT     		0x00000002
++#define PPSMC_EVENT_STATUS_DC               		0x00000004
++#define PPSMC_EVENT_STATUS_GPIO17           		0x00000008
++
++#pragma pack(pop)
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h
+new file mode 100644
+index 0000000..099b7b5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h
+@@ -0,0 +1,2240 @@
++/*
++ * Copyright (C) 2014  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __TONGA_SDMA_PKT_OPEN_H_
++#define __TONGA_SDMA_PKT_OPEN_H_
++
++#define SDMA_OP_NOP  0
++#define SDMA_OP_COPY  1
++#define SDMA_OP_WRITE  2
++#define SDMA_OP_INDIRECT  4
++#define SDMA_OP_FENCE  5
++#define SDMA_OP_TRAP  6
++#define SDMA_OP_SEM  7
++#define SDMA_OP_POLL_REGMEM  8
++#define SDMA_OP_COND_EXE  9
++#define SDMA_OP_ATOMIC  10
++#define SDMA_OP_CONST_FILL  11
++#define SDMA_OP_GEN_PTEPDE  12
++#define SDMA_OP_TIMESTAMP  13
++#define SDMA_OP_SRBM_WRITE  14
++#define SDMA_OP_PRE_EXE  15
++#define SDMA_SUBOP_TIMESTAMP_SET  0
++#define SDMA_SUBOP_TIMESTAMP_GET  1
++#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL  2
++#define SDMA_SUBOP_COPY_LINEAR  0
++#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND  4
++#define SDMA_SUBOP_COPY_TILED  1
++#define SDMA_SUBOP_COPY_TILED_SUB_WIND  5
++#define SDMA_SUBOP_COPY_T2T_SUB_WIND  6
++#define SDMA_SUBOP_COPY_SOA  3
++#define SDMA_SUBOP_WRITE_LINEAR  0
++#define SDMA_SUBOP_WRITE_TILED  1
++
++/*define for op field*/
++#define SDMA_PKT_HEADER_op_offset 0
++#define SDMA_PKT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_HEADER_op_shift  0
++#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_HEADER_sub_op_offset 0
++#define SDMA_PKT_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_HEADER_sub_op_shift  8
++#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift)
++
++/*
++** Definitions for SDMA_PKT_COPY_LINEAR packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift  0
++#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift)
++
++/*define for broadcast field*/
++#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0
++#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift  27
++#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1
++#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift  0
++#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift)
++
++/*define for PARAMETER word*/
++/*define for dst_sw field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift  16
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)
++
++/*define for dst_ha field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift  22
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift  24
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)
++
++/*define for src_ha field*/
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift  30
++#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift)
++
++/*define for broadcast field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift  27
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift)
++
++/*define for PARAMETER word*/
++/*define for dst2_sw field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask   0x00000003
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift  8
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift)
++
++/*define for dst2_ha field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift  14
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift)
++
++/*define for dst1_sw field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask   0x00000003
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift  16
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift)
++
++/*define for dst1_ha field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift  22
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift  24
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift)
++
++/*define for src_ha field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask   0x00000001
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift  30
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DST1_ADDR_LO word*/
++/*define for dst1_addr_31_0 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift)
++
++/*define for DST1_ADDR_HI word*/
++/*define for dst1_addr_63_32 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift)
++
++/*define for DST2_ADDR_LO word*/
++/*define for dst2_addr_31_0 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift)
++
++/*define for DST2_ADDR_HI word*/
++/*define for dst2_addr_63_32 field*/
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift  0
++#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift)
++
++/*define for elementsize field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask   0x00000007
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift  29
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for src_x field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift)
++
++/*define for src_y field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift)
++
++/*define for DW_4 word*/
++/*define for src_z field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask   0x000007FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift)
++
++/*define for src_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift)
++
++/*define for DW_5 word*/
++/*define for src_slice_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask   0x0FFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_8 word*/
++/*define for dst_x field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift)
++
++/*define for dst_y field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift)
++
++/*define for DW_9 word*/
++/*define for dst_z field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask   0x000007FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift)
++
++/*define for dst_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift)
++
++/*define for DW_10 word*/
++/*define for dst_slice_pitch field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask   0x0FFFFFFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift)
++
++/*define for DW_11 word*/
++/*define for rect_x field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift)
++
++/*define for rect_y field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift)
++
++/*define for DW_12 word*/
++/*define for rect_z field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask   0x000007FF
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift  0
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift)
++
++/*define for dst_sw field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift  16
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift)
++
++/*define for dst_ha field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift  22
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift  24
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift)
++
++/*define for src_ha field*/
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask   0x00000001
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift  30
++#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_TILED packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0
++#define SDMA_PKT_COPY_TILED_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_HEADER_op_shift  0
++#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift)
++
++/*define for detile field*/
++#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0
++#define SDMA_PKT_COPY_TILED_HEADER_detile_mask   0x00000001
++#define SDMA_PKT_COPY_TILED_HEADER_detile_shift  31
++#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift)
++
++/*define for TILED_ADDR_LO word*/
++/*define for tiled_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift)
++
++/*define for TILED_ADDR_HI word*/
++/*define for tiled_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3
++#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift  0
++#define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift)
++
++/*define for height field*/
++#define SDMA_PKT_COPY_TILED_DW_3_height_offset 3
++#define SDMA_PKT_COPY_TILED_DW_3_height_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_DW_3_height_shift  16
++#define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift)
++
++/*define for DW_4 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4
++#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift)
++
++/*define for DW_5 word*/
++/*define for element_size field*/
++#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift  0
++#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift  3
++#define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift  8
++#define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift  15
++#define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift  18
++#define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift  21
++#define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift  24
++#define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5
++#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift  26
++#define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift)
++
++/*define for DW_6 word*/
++/*define for x field*/
++#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6
++#define SDMA_PKT_COPY_TILED_DW_6_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_DW_6_x_shift  0
++#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift)
++
++/*define for y field*/
++#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6
++#define SDMA_PKT_COPY_TILED_DW_6_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_DW_6_y_shift  16
++#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift)
++
++/*define for DW_7 word*/
++/*define for z field*/
++#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7
++#define SDMA_PKT_COPY_TILED_DW_7_z_mask   0x00000FFF
++#define SDMA_PKT_COPY_TILED_DW_7_z_shift  0
++#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7
++#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift  16
++#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift)
++
++/*define for tile_sw field*/
++#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7
++#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift  24
++#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++/*define for LINEAR_PITCH word*/
++/*define for linear_pitch field*/
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_TILED_COUNT_count_offset 11
++#define SDMA_PKT_COPY_TILED_COUNT_count_mask   0x000FFFFF
++#define SDMA_PKT_COPY_TILED_COUNT_count_shift  0
++#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift)
++
++/*define for videocopy field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask   0x00000001
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift  26
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift)
++
++/*define for broadcast field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask   0x00000001
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift  27
++#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift)
++
++/*define for TILED_ADDR_LO_0 word*/
++/*define for tiled_addr0_31_0 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift)
++
++/*define for TILED_ADDR_HI_0 word*/
++/*define for tiled_addr0_63_32 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift)
++
++/*define for TILED_ADDR_LO_1 word*/
++/*define for tiled_addr1_31_0 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift)
++
++/*define for TILED_ADDR_HI_1 word*/
++/*define for tiled_addr1_63_32 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift)
++
++/*define for DW_5 word*/
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask   0x000007FF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift)
++
++/*define for height field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask   0x00003FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift  16
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift)
++
++/*define for DW_6 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift)
++
++/*define for DW_7 word*/
++/*define for element_size field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift  3
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift  8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift  15
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift  18
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift  21
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift  24
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift  26
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift)
++
++/*define for DW_8 word*/
++/*define for x field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift)
++
++/*define for y field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift  16
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift)
++
++/*define for DW_9 word*/
++/*define for z field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask   0x00000FFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift)
++
++/*define for DW_10 word*/
++/*define for dst2_sw field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift  8
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift)
++
++/*define for dst2_ha field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask   0x00000001
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift  14
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift  16
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift)
++
++/*define for tile_sw field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask   0x00000003
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift  24
++#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++/*define for LINEAR_PITCH word*/
++/*define for linear_pitch field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask   0x0007FFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask   0x000FFFFF
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift  0
++#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_T2T packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0
++#define SDMA_PKT_COPY_T2T_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_T2T_HEADER_op_shift  0
++#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift)
++
++/*define for SRC_ADDR_LO word*/
++/*define for src_addr_31_0 field*/
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift  0
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift)
++
++/*define for SRC_ADDR_HI word*/
++/*define for src_addr_63_32 field*/
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift  0
++#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for src_x field*/
++#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3
++#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift  0
++#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift)
++
++/*define for src_y field*/
++#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3
++#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift  16
++#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift)
++
++/*define for DW_4 word*/
++/*define for src_z field*/
++#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4
++#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask   0x000007FF
++#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift  0
++#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift)
++
++/*define for src_pitch_in_tile field*/
++#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4
++#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask   0x00000FFF
++#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift  16
++#define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift)
++
++/*define for DW_5 word*/
++/*define for src_slice_pitch field*/
++#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5
++#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift  0
++#define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift)
++
++/*define for DW_6 word*/
++/*define for src_element_size field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift  0
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift)
++
++/*define for src_array_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift  3
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift)
++
++/*define for src_mit_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift  8
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift)
++
++/*define for src_tilesplit_size field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift)
++
++/*define for src_bank_w field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift  15
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift)
++
++/*define for src_bank_h field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift  18
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift)
++
++/*define for src_num_bank field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift  21
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift)
++
++/*define for src_mat_aspt field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift  24
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift)
++
++/*define for src_pipe_config field*/
++#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6
++#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift  26
++#define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_9 word*/
++/*define for dst_x field*/
++#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9
++#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift  0
++#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift)
++
++/*define for dst_y field*/
++#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9
++#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift  16
++#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift)
++
++/*define for DW_10 word*/
++/*define for dst_z field*/
++#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10
++#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask   0x000007FF
++#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift  0
++#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift)
++
++/*define for dst_pitch_in_tile field*/
++#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10
++#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask   0x00000FFF
++#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift  16
++#define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift)
++
++/*define for DW_11 word*/
++/*define for dst_slice_pitch field*/
++#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11
++#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift  0
++#define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift)
++
++/*define for DW_12 word*/
++/*define for dst_array_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift  3
++#define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift)
++
++/*define for dst_mit_mode field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift  8
++#define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift)
++
++/*define for dst_tilesplit_size field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift)
++
++/*define for dst_bank_w field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift  15
++#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift)
++
++/*define for dst_bank_h field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift  18
++#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift)
++
++/*define for dst_num_bank field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift  21
++#define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift)
++
++/*define for dst_mat_aspt field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift  24
++#define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift)
++
++/*define for dst_pipe_config field*/
++#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12
++#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift  26
++#define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift)
++
++/*define for DW_13 word*/
++/*define for rect_x field*/
++#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13
++#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift  0
++#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift)
++
++/*define for rect_y field*/
++#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13
++#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift  16
++#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift)
++
++/*define for DW_14 word*/
++/*define for rect_z field*/
++#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14
++#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask   0x000007FF
++#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift  0
++#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift)
++
++/*define for dst_sw field*/
++#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14
++#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift  16
++#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift)
++
++/*define for src_sw field*/
++#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14
++#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask   0x00000003
++#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift  24
++#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift)
++
++/*define for detile field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask   0x00000001
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift  31
++#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift)
++
++/*define for TILED_ADDR_LO word*/
++/*define for tiled_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift)
++
++/*define for TILED_ADDR_HI word*/
++/*define for tiled_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for tiled_x field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift)
++
++/*define for tiled_y field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift)
++
++/*define for DW_4 word*/
++/*define for tiled_z field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift)
++
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask   0x00000FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift)
++
++/*define for DW_5 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift)
++
++/*define for DW_6 word*/
++/*define for element_size field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask   0x0000000F
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift  3
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift  8
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift  11
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift  15
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift  18
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift  21
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift  24
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask   0x0000001F
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift  26
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++/*define for DW_9 word*/
++/*define for linear_x field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift)
++
++/*define for linear_y field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift)
++
++/*define for DW_10 word*/
++/*define for linear_z field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift)
++
++/*define for linear_pitch field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift)
++
++/*define for DW_11 word*/
++/*define for linear_slice_pitch field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask   0x0FFFFFFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift)
++
++/*define for DW_12 word*/
++/*define for rect_x field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift)
++
++/*define for rect_y field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask   0x00003FFF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift)
++
++/*define for DW_13 word*/
++/*define for rect_z field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask   0x000007FF
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift  0
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift  16
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift)
++
++/*define for tile_sw field*/
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask   0x00000003
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift  24
++#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COPY_STRUCT packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0
++#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift  0
++#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0
++#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift  8
++#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift)
++
++/*define for detile field*/
++#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0
++#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask   0x00000001
++#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift  31
++#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift)
++
++/*define for SB_ADDR_LO word*/
++/*define for sb_addr_31_0 field*/
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift  0
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift)
++
++/*define for SB_ADDR_HI word*/
++/*define for sb_addr_63_32 field*/
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift  0
++#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift)
++
++/*define for START_INDEX word*/
++/*define for start_index field*/
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift  0
++#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4
++#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift  0
++#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift)
++
++/*define for DW_5 word*/
++/*define for stride field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask   0x000007FF
++#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift  0
++#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift)
++
++/*define for struct_sw field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask   0x00000003
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift  16
++#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift)
++
++/*define for struct_ha field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask   0x00000001
++#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift  22
++#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift)
++
++/*define for linear_sw field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask   0x00000003
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift  24
++#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift)
++
++/*define for linear_ha field*/
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask   0x00000001
++#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift  30
++#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift)
++
++/*define for LINEAR_ADDR_LO word*/
++/*define for linear_addr_31_0 field*/
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift  0
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift)
++
++/*define for LINEAR_ADDR_HI word*/
++/*define for linear_addr_63_32 field*/
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift  0
++#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_WRITE_UNTILED packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0
++#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift  0
++#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0
++#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift  8
++#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for count field*/
++#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3
++#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask   0x003FFFFF
++#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift)
++
++/*define for sw field*/
++#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3
++#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask   0x00000003
++#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift  24
++#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift)
++
++/*define for DATA0 word*/
++/*define for data0 field*/
++#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4
++#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift  0
++#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift)
++
++
++/*
++** Definitions for SDMA_PKT_WRITE_TILED packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0
++#define SDMA_PKT_WRITE_TILED_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_TILED_HEADER_op_shift  0
++#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0
++#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift  8
++#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DW_3 word*/
++/*define for pitch_in_tile field*/
++#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3
++#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask   0x000007FF
++#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift)
++
++/*define for height field*/
++#define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3
++#define SDMA_PKT_WRITE_TILED_DW_3_height_mask   0x00003FFF
++#define SDMA_PKT_WRITE_TILED_DW_3_height_shift  16
++#define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift)
++
++/*define for DW_4 word*/
++/*define for slice_pitch field*/
++#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4
++#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask   0x003FFFFF
++#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift)
++
++/*define for DW_5 word*/
++/*define for element_size field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask   0x00000007
++#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift)
++
++/*define for array_mode field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask   0x0000000F
++#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift  3
++#define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift)
++
++/*define for mit_mode field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask   0x00000007
++#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift  8
++#define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift)
++
++/*define for tilesplit_size field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask   0x00000007
++#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift  11
++#define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift)
++
++/*define for bank_w field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift  15
++#define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift)
++
++/*define for bank_h field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift  18
++#define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift)
++
++/*define for num_bank field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift  21
++#define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift)
++
++/*define for mat_aspt field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift  24
++#define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift)
++
++/*define for pipe_config field*/
++#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5
++#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask   0x0000001F
++#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift  26
++#define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift)
++
++/*define for DW_6 word*/
++/*define for x field*/
++#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6
++#define SDMA_PKT_WRITE_TILED_DW_6_x_mask   0x00003FFF
++#define SDMA_PKT_WRITE_TILED_DW_6_x_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift)
++
++/*define for y field*/
++#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6
++#define SDMA_PKT_WRITE_TILED_DW_6_y_mask   0x00003FFF
++#define SDMA_PKT_WRITE_TILED_DW_6_y_shift  16
++#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift)
++
++/*define for DW_7 word*/
++/*define for z field*/
++#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7
++#define SDMA_PKT_WRITE_TILED_DW_7_z_mask   0x00000FFF
++#define SDMA_PKT_WRITE_TILED_DW_7_z_shift  0
++#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift)
++
++/*define for sw field*/
++#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7
++#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask   0x00000003
++#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift  24
++#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8
++#define SDMA_PKT_WRITE_TILED_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_WRITE_TILED_COUNT_count_shift  0
++#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift)
++
++/*define for DATA0 word*/
++/*define for data0 field*/
++#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9
++#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift  0
++#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift)
++
++
++/*
++** Definitions for SDMA_PKT_WRITE_INCR packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0
++#define SDMA_PKT_WRITE_INCR_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_INCR_HEADER_op_shift  0
++#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0
++#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift  8
++#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for MASK_DW0 word*/
++/*define for mask_dw0 field*/
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift  0
++#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift)
++
++/*define for MASK_DW1 word*/
++/*define for mask_dw1 field*/
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift  0
++#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift)
++
++/*define for INIT_DW0 word*/
++/*define for init_dw0 field*/
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift  0
++#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift)
++
++/*define for INIT_DW1 word*/
++/*define for init_dw1 field*/
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift  0
++#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift)
++
++/*define for INCR_DW0 word*/
++/*define for incr_dw0 field*/
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift  0
++#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift)
++
++/*define for INCR_DW1 word*/
++/*define for incr_dw1 field*/
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask   0xFFFFFFFF
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift  0
++#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9
++#define SDMA_PKT_WRITE_INCR_COUNT_count_mask   0x0007FFFF
++#define SDMA_PKT_WRITE_INCR_COUNT_count_shift  0
++#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_INDIRECT packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_INDIRECT_HEADER_op_offset 0
++#define SDMA_PKT_INDIRECT_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_INDIRECT_HEADER_op_shift  0
++#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0
++#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift  8
++#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift)
++
++/*define for vmid field*/
++#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0
++#define SDMA_PKT_INDIRECT_HEADER_vmid_mask   0x0000000F
++#define SDMA_PKT_INDIRECT_HEADER_vmid_shift  16
++#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift)
++
++/*define for BASE_LO word*/
++/*define for ib_base_31_0 field*/
++#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1
++#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift  0
++#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift)
++
++/*define for BASE_HI word*/
++/*define for ib_base_63_32 field*/
++#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2
++#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift  0
++#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift)
++
++/*define for IB_SIZE word*/
++/*define for ib_size field*/
++#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3
++#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask   0x000FFFFF
++#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift  0
++#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift)
++
++/*define for CSA_ADDR_LO word*/
++/*define for csa_addr_31_0 field*/
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift  0
++#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift)
++
++/*define for CSA_ADDR_HI word*/
++/*define for csa_addr_63_32 field*/
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift  0
++#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_SEMAPHORE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_SEMAPHORE_HEADER_op_shift  0
++#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift  8
++#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift)
++
++/*define for write_one field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask   0x00000001
++#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift  29
++#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift)
++
++/*define for signal field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask   0x00000001
++#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift  30
++#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift)
++
++/*define for mailbox field*/
++#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0
++#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask   0x00000001
++#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift  31
++#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_FENCE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_FENCE_HEADER_op_offset 0
++#define SDMA_PKT_FENCE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_FENCE_HEADER_op_shift  0
++#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0
++#define SDMA_PKT_FENCE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_FENCE_HEADER_sub_op_shift  8
++#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift)
++
++/*define for DATA word*/
++/*define for data field*/
++#define SDMA_PKT_FENCE_DATA_data_offset 3
++#define SDMA_PKT_FENCE_DATA_data_mask   0xFFFFFFFF
++#define SDMA_PKT_FENCE_DATA_data_shift  0
++#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift)
++
++
++/*
++** Definitions for SDMA_PKT_SRBM_WRITE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0
++#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift  0
++#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0
++#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift  8
++#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift)
++
++/*define for byte_en field*/
++#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0
++#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask   0x0000000F
++#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift  28
++#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift)
++
++/*define for ADDR word*/
++/*define for addr field*/
++#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1
++#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask   0x0000FFFF
++#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift  0
++#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift)
++
++/*define for DATA word*/
++/*define for data field*/
++#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2
++#define SDMA_PKT_SRBM_WRITE_DATA_data_mask   0xFFFFFFFF
++#define SDMA_PKT_SRBM_WRITE_DATA_data_shift  0
++#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift)
++
++
++/*
++** Definitions for SDMA_PKT_PRE_EXE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0
++#define SDMA_PKT_PRE_EXE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_PRE_EXE_HEADER_op_shift  0
++#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0
++#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift  8
++#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift)
++
++/*define for dev_sel field*/
++#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0
++#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask   0x000000FF
++#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift  16
++#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift)
++
++/*define for EXEC_COUNT word*/
++/*define for exec_count field*/
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift  0
++#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_COND_EXE packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_COND_EXE_HEADER_op_offset 0
++#define SDMA_PKT_COND_EXE_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_COND_EXE_HEADER_op_shift  0
++#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0
++#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift  8
++#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift)
++
++/*define for REFERENCE word*/
++/*define for reference field*/
++#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3
++#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask   0xFFFFFFFF
++#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift  0
++#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift)
++
++/*define for EXEC_COUNT word*/
++/*define for exec_count field*/
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask   0x00003FFF
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift  0
++#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_CONSTANT_FILL packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift  0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift  8
++#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift)
++
++/*define for sw field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask   0x00000003
++#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift  16
++#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift)
++
++/*define for fillsize field*/
++#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0
++#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask   0x00000003
++#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift  30
++#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift)
++
++/*define for DST_ADDR_LO word*/
++/*define for dst_addr_31_0 field*/
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift  0
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift)
++
++/*define for DST_ADDR_HI word*/
++/*define for dst_addr_63_32 field*/
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift  0
++#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift)
++
++/*define for DATA word*/
++/*define for src_data_31_0 field*/
++#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3
++#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift  0
++#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift)
++
++/*define for COUNT word*/
++/*define for count field*/
++#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4
++#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask   0x003FFFFF
++#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift  0
++#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_POLL_REGMEM packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift  0
++#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift  8
++#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift)
++
++/*define for hdp_flush field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask   0x00000001
++#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift  26
++#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift)
++
++/*define for func field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask   0x00000007
++#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift  28
++#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift)
++
++/*define for mem_poll field*/
++#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0
++#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask   0x00000001
++#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift  31
++#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift)
++
++/*define for VALUE word*/
++/*define for value field*/
++#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3
++#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift  0
++#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift)
++
++/*define for MASK word*/
++/*define for mask field*/
++#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4
++#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask   0xFFFFFFFF
++#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift  0
++#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift)
++
++/*define for DW5 word*/
++/*define for interval field*/
++#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5
++#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask   0x0000FFFF
++#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift  0
++#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift)
++
++/*define for retry_count field*/
++#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5
++#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask   0x00000FFF
++#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift  16
++#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift)
++
++
++/*
++** Definitions for SDMA_PKT_ATOMIC packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_ATOMIC_HEADER_op_offset 0
++#define SDMA_PKT_ATOMIC_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_ATOMIC_HEADER_op_shift  0
++#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift)
++
++/*define for loop field*/
++#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0
++#define SDMA_PKT_ATOMIC_HEADER_loop_mask   0x00000001
++#define SDMA_PKT_ATOMIC_HEADER_loop_shift  16
++#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift)
++
++/*define for atomic_op field*/
++#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0
++#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask   0x0000007F
++#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift  25
++#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift)
++
++/*define for ADDR_LO word*/
++/*define for addr_31_0 field*/
++#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1
++#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift  0
++#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift)
++
++/*define for ADDR_HI word*/
++/*define for addr_63_32 field*/
++#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2
++#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift  0
++#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift)
++
++/*define for SRC_DATA_LO word*/
++/*define for src_data_31_0 field*/
++#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3
++#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift  0
++#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift)
++
++/*define for SRC_DATA_HI word*/
++/*define for src_data_63_32 field*/
++#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4
++#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift  0
++#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift)
++
++/*define for CMP_DATA_LO word*/
++/*define for cmp_data_31_0 field*/
++#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5
++#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift  0
++#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift)
++
++/*define for CMP_DATA_HI word*/
++/*define for cmp_data_63_32 field*/
++#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6
++#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift  0
++#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift)
++
++/*define for LOOP_INTERVAL word*/
++/*define for loop_interval field*/
++#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7
++#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask   0x00001FFF
++#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift  0
++#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TIMESTAMP_SET packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift  0
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift  8
++#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift)
++
++/*define for INIT_DATA_LO word*/
++/*define for init_data_31_0 field*/
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift  0
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift)
++
++/*define for INIT_DATA_HI word*/
++/*define for init_data_63_32 field*/
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift  0
++#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TIMESTAMP_GET packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift  8
++#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift)
++
++/*define for WRITE_ADDR_LO word*/
++/*define for write_addr_31_3 field*/
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift  3
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift)
++
++/*define for WRITE_ADDR_HI word*/
++/*define for write_addr_63_32 field*/
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift  8
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift)
++
++/*define for WRITE_ADDR_LO word*/
++/*define for write_addr_31_3 field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask   0x1FFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift  3
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift)
++
++/*define for WRITE_ADDR_HI word*/
++/*define for write_addr_63_32 field*/
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask   0xFFFFFFFF
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift  0
++#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift)
++
++
++/*
++** Definitions for SDMA_PKT_TRAP packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_TRAP_HEADER_op_offset 0
++#define SDMA_PKT_TRAP_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_TRAP_HEADER_op_shift  0
++#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0
++#define SDMA_PKT_TRAP_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_TRAP_HEADER_sub_op_shift  8
++#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift)
++
++/*define for INT_CONTEXT word*/
++/*define for int_context field*/
++#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1
++#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask   0x0FFFFFFF
++#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift  0
++#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift)
++
++
++/*
++** Definitions for SDMA_PKT_NOP packet
++*/
++
++/*define for HEADER word*/
++/*define for op field*/
++#define SDMA_PKT_NOP_HEADER_op_offset 0
++#define SDMA_PKT_NOP_HEADER_op_mask   0x000000FF
++#define SDMA_PKT_NOP_HEADER_op_shift  0
++#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift)
++
++/*define for sub_op field*/
++#define SDMA_PKT_NOP_HEADER_sub_op_offset 0
++#define SDMA_PKT_NOP_HEADER_sub_op_mask   0x000000FF
++#define SDMA_PKT_NOP_HEADER_sub_op_shift  8
++#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift)
++
++
++#endif /* __TONGA_SDMA_PKT_OPEN_H_ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smc.c b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
+new file mode 100644
+index 0000000..5fc53a4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
+@@ -0,0 +1,852 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "tonga_ppsmc.h"
++#include "tonga_smumgr.h"
++#include "smu_ucode_xfer_vi.h"
++#include "amdgpu_ucode.h"
++
++#include "smu/smu_7_1_2_d.h"
++#include "smu/smu_7_1_2_sh_mask.h"
++
++#define TONGA_SMC_SIZE 0x20000
++
++static int tonga_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t limit)
++{
++	uint32_t val;
++
++	if (smc_address & 3)
++		return -EINVAL;
++
++	if ((smc_address + 3) > limit)
++		return -EINVAL;
++
++	WREG32(mmSMC_IND_INDEX_0, smc_address);
++
++	val = RREG32(mmSMC_IND_ACCESS_CNTL);
++	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
++	WREG32(mmSMC_IND_ACCESS_CNTL, val);
++
++	return 0;
++}
++
++static int tonga_copy_bytes_to_smc(struct amdgpu_device *adev, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit)
++{
++	uint32_t addr;
++	uint32_t data, orig_data;
++	int result = 0;
++	uint32_t extra_shift;
++	unsigned long flags;
++
++	if (smc_start_address & 3)
++		return -EINVAL;
++
++	if ((smc_start_address + byte_count) > limit)
++		return -EINVAL;
++
++	addr = smc_start_address;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	while (byte_count >= 4) {
++		/* Bytes are written into the SMC addres space with the MSB first */
++		data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
++
++		result = tonga_set_smc_sram_address(adev, addr, limit);
++
++		if (result)
++			goto out;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++
++		src += 4;
++		byte_count -= 4;
++		addr += 4;
++	}
++
++	if (0 != byte_count) {
++		/* Now write odd bytes left, do a read modify write cycle */
++		data = 0;
++
++		result = tonga_set_smc_sram_address(adev, addr, limit);
++		if (result)
++			goto out;
++
++		orig_data = RREG32(mmSMC_IND_DATA_0);
++		extra_shift = 8 * (4 - byte_count);
++
++		while (byte_count > 0) {
++			data = (data << 8) + *src++;
++			byte_count--;
++		}
++
++		data <<= extra_shift;
++		data |= (orig_data & ~((~0UL) << extra_shift));
++
++		result = tonga_set_smc_sram_address(adev, addr, limit);
++		if (result)
++			goto out;
++
++		WREG32(mmSMC_IND_DATA_0, data);
++	}
++
++out:
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return result;
++}
++
++static int tonga_program_jump_on_start(struct amdgpu_device *adev)
++{
++	static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40};
++	tonga_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
++
++	return 0;
++}
++
++static bool tonga_is_smc_ram_running(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++	val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable);
++
++	return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));
++}
++
++static int wait_smu_response(struct amdgpu_device *adev)
++{
++	int i;
++	uint32_t val;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32(mmSMC_RESP_0);
++		if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int tonga_send_msg_to_smc_offset(struct amdgpu_device *adev)
++{
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MSG_ARG_0, 0x20000);
++	WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_Test);
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send message\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int tonga_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
++{
++	if (!tonga_is_smc_ram_running(adev))
++	{
++		return -EINVAL;;
++	}
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MESSAGE_0, msg);
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send message\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int tonga_send_msg_to_smc_without_waiting(struct amdgpu_device *adev,
++						PPSMC_Msg msg)
++{
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MESSAGE_0, msg);
++
++	return 0;
++}
++
++static int tonga_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
++						PPSMC_Msg msg,
++						uint32_t parameter)
++{
++	if (!tonga_is_smc_ram_running(adev))
++		return -EINVAL;
++
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MSG_ARG_0, parameter);
++
++	return tonga_send_msg_to_smc(adev, msg);
++}
++
++static int tonga_send_msg_to_smc_with_parameter_without_waiting(
++					struct amdgpu_device *adev,
++					PPSMC_Msg msg, uint32_t parameter)
++{
++	if (wait_smu_response(adev)) {
++		DRM_ERROR("Failed to send previous message\n");
++		return -EINVAL;
++	}
++
++	WREG32(mmSMC_MSG_ARG_0, parameter);
++
++	return tonga_send_msg_to_smc_without_waiting(adev, msg);
++}
++
++#if 0 /* not used yet */
++static int tonga_wait_for_smc_inactive(struct amdgpu_device *adev)
++{
++	int i;
++	uint32_t val;
++
++	if (!tonga_is_smc_ram_running(adev))
++		return -EINVAL;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++		if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout)
++		return -EINVAL;
++
++	return 0;
++}
++#endif
++
++static int tonga_smu_upload_firmware_image(struct amdgpu_device *adev)
++{
++	const struct smc_firmware_header_v1_0 *hdr;
++	uint32_t ucode_size;
++	uint32_t ucode_start_address;
++	const uint8_t *src;
++	uint32_t val;
++	uint32_t byte_count;
++	uint32_t *data;
++	unsigned long flags;
++
++	if (!adev->pm.fw)
++		return -EINVAL;
++
++	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
++	amdgpu_ucode_print_smc_hdr(&hdr->header);
++
++	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
++	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
++	ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
++	src = (const uint8_t *)
++		(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
++
++	if (ucode_size & 3) {
++		DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
++		return -EINVAL;
++	}
++
++	if (ucode_size > TONGA_SMC_SIZE) {
++		DRM_ERROR("SMC address is beyond the SMC RAM area\n");
++		return -EINVAL;
++	}
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
++
++	val = RREG32(mmSMC_IND_ACCESS_CNTL);
++	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
++	WREG32(mmSMC_IND_ACCESS_CNTL, val);
++
++	byte_count = ucode_size;
++	data = (uint32_t *)src;
++	for (; byte_count >= 4; data++, byte_count -= 4)
++		WREG32(mmSMC_IND_DATA_0, data[0]);
++
++	val = RREG32(mmSMC_IND_ACCESS_CNTL);
++	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
++	WREG32(mmSMC_IND_ACCESS_CNTL, val);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++
++	return 0;
++}
++
++#if 0 /* not used yet */
++static int tonga_read_smc_sram_dword(struct amdgpu_device *adev,
++				uint32_t smc_address,
++				uint32_t *value,
++				uint32_t limit)
++{
++	int result;
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	result = tonga_set_smc_sram_address(adev, smc_address, limit);
++	if (result == 0)
++		*value = RREG32(mmSMC_IND_DATA_0);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return result;
++}
++
++static int tonga_write_smc_sram_dword(struct amdgpu_device *adev,
++				uint32_t smc_address,
++				uint32_t value,
++				uint32_t limit)
++{
++	int result;
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	result = tonga_set_smc_sram_address(adev, smc_address, limit);
++	if (result == 0)
++		WREG32(mmSMC_IND_DATA_0, value);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return result;
++}
++
++static int tonga_smu_stop_smc(struct amdgpu_device *adev)
++{
++	uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++
++	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
++
++	return 0;
++}
++#endif
++
++static enum AMDGPU_UCODE_ID tonga_convert_fw_type(uint32_t fw_type)
++{
++	switch (fw_type) {
++		case UCODE_ID_SDMA0:
++			return AMDGPU_UCODE_ID_SDMA0;
++		case UCODE_ID_SDMA1:
++			return AMDGPU_UCODE_ID_SDMA1;
++		case UCODE_ID_CP_CE:
++			return AMDGPU_UCODE_ID_CP_CE;
++		case UCODE_ID_CP_PFP:
++			return AMDGPU_UCODE_ID_CP_PFP;
++		case UCODE_ID_CP_ME:
++			return AMDGPU_UCODE_ID_CP_ME;
++		case UCODE_ID_CP_MEC:
++		case UCODE_ID_CP_MEC_JT1:
++			return AMDGPU_UCODE_ID_CP_MEC1;
++		case UCODE_ID_CP_MEC_JT2:
++			return AMDGPU_UCODE_ID_CP_MEC2;
++		case UCODE_ID_RLC_G:
++			return AMDGPU_UCODE_ID_RLC_G;
++		default:
++			DRM_ERROR("ucode type is out of range!\n");
++			return AMDGPU_UCODE_ID_MAXIMUM;
++	}
++}
++
++static int tonga_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
++						uint32_t fw_type,
++						struct SMU_Entry *entry)
++{
++	enum AMDGPU_UCODE_ID id = tonga_convert_fw_type(fw_type);
++	struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
++	const struct gfx_firmware_header_v1_0 *header = NULL;
++	uint64_t gpu_addr;
++	uint32_t data_size;
++
++	if (ucode->fw == NULL)
++		return -EINVAL;
++
++	gpu_addr  = ucode->mc_addr;
++	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
++	data_size = le32_to_cpu(header->header.ucode_size_bytes);
++
++	if ((fw_type == UCODE_ID_CP_MEC_JT1) ||
++		(fw_type == UCODE_ID_CP_MEC_JT2)) {
++		gpu_addr += le32_to_cpu(header->jt_offset) << 2;
++		data_size = le32_to_cpu(header->jt_size) << 2;
++	}
++
++	entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
++	entry->id = (uint16_t)fw_type;
++	entry->image_addr_high = upper_32_bits(gpu_addr);
++	entry->image_addr_low = lower_32_bits(gpu_addr);
++	entry->meta_data_addr_high = 0;
++	entry->meta_data_addr_low = 0;
++	entry->data_size_byte = data_size;
++	entry->num_register_entries = 0;
++
++	if (fw_type == UCODE_ID_RLC_G)
++		entry->flags = 1;
++	else
++		entry->flags = 0;
++
++	return 0;
++}
++
++static int tonga_smu_request_load_fw(struct amdgpu_device *adev)
++{
++	struct tonga_smu_private_data *private = (struct tonga_smu_private_data *)adev->smu.priv;
++	struct SMU_DRAMData_TOC *toc;
++	uint32_t fw_to_load;
++
++	WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0);
++
++	tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_HI, private->smu_buffer_addr_high);
++	tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_LO, private->smu_buffer_addr_low);
++
++	toc = (struct SMU_DRAMData_TOC *)private->header;
++	toc->num_entries = 0;
++	toc->structure_version = 1;
++
++	if (!adev->firmware.smu_load)
++		return 0;
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for RLC\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for CE\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for PFP\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for ME\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for MEC\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for SDMA0\n");
++		return -EINVAL;
++	}
++
++	if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1,
++			&toc->entry[toc->num_entries++])) {
++		DRM_ERROR("Failed to get firmware entry for SDMA1\n");
++		return -EINVAL;
++	}
++
++	tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high);
++	tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low);
++
++	fw_to_load = UCODE_ID_RLC_G_MASK |
++			UCODE_ID_SDMA0_MASK |
++			UCODE_ID_SDMA1_MASK |
++			UCODE_ID_CP_CE_MASK |
++			UCODE_ID_CP_ME_MASK |
++			UCODE_ID_CP_PFP_MASK |
++			UCODE_ID_CP_MEC_MASK;
++
++	if (tonga_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
++		DRM_ERROR("Fail to request SMU load ucode\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static uint32_t tonga_smu_get_mask_for_fw_type(uint32_t fw_type)
++{
++	switch (fw_type) {
++		case AMDGPU_UCODE_ID_SDMA0:
++			return UCODE_ID_SDMA0_MASK;
++		case AMDGPU_UCODE_ID_SDMA1:
++			return UCODE_ID_SDMA1_MASK;
++		case AMDGPU_UCODE_ID_CP_CE:
++			return UCODE_ID_CP_CE_MASK;
++		case AMDGPU_UCODE_ID_CP_PFP:
++			return UCODE_ID_CP_PFP_MASK;
++		case AMDGPU_UCODE_ID_CP_ME:
++			return UCODE_ID_CP_ME_MASK;
++		case AMDGPU_UCODE_ID_CP_MEC1:
++			return UCODE_ID_CP_MEC_MASK;
++		case AMDGPU_UCODE_ID_CP_MEC2:
++			return UCODE_ID_CP_MEC_MASK;
++		case AMDGPU_UCODE_ID_RLC_G:
++			return UCODE_ID_RLC_G_MASK;
++		default:
++			DRM_ERROR("ucode type is out of range!\n");
++			return 0;
++	}
++}
++
++static int tonga_smu_check_fw_load_finish(struct amdgpu_device *adev,
++					uint32_t fw_type)
++{
++	uint32_t fw_mask = tonga_smu_get_mask_for_fw_type(fw_type);
++	int i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("check firmware loading failed\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int tonga_smu_start_in_protection_mode(struct amdgpu_device *adev)
++{
++	int result;
++	uint32_t val;
++	int i;
++
++	/* Assert reset */
++	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++
++	result = tonga_smu_upload_firmware_image(adev);
++	if (result)
++		return result;
++
++	/* Clear status */
++	WREG32_SMC(ixSMU_STATUS, 0);
++
++	/* Enable clock */
++	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
++
++	/* De-assert reset */
++	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++
++	/* Set SMU Auto Start */
++	val = RREG32_SMC(ixSMU_INPUT_DATA);
++	val = REG_SET_FIELD(val, SMU_INPUT_DATA, AUTO_START, 1);
++	WREG32_SMC(ixSMU_INPUT_DATA, val);
++
++	/* Clear firmware interrupt enable flag */
++	WREG32_SMC(ixFIRMWARE_FLAGS, 0);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixRCU_UC_EVENTS);
++		if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("Interrupt is not enabled by firmware\n");
++		return -EINVAL;
++	}
++
++	/* Call Test SMU message with 0x20000 offset
++	 * to trigger SMU start
++	 */
++	tonga_send_msg_to_smc_offset(adev);
++
++	/* Wait for done bit to be set */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixSMU_STATUS);
++		if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("Timeout for SMU start\n");
++		return -EINVAL;
++	}
++
++	/* Check pass/failed indicator */
++	val = RREG32_SMC(ixSMU_STATUS);
++	if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) {
++		DRM_ERROR("SMU Firmware start failed\n");
++		return -EINVAL;
++	}
++
++	/* Wait for firmware to initialize */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixFIRMWARE_FLAGS);
++		if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("SMU firmware initialization failed\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int tonga_smu_start_in_non_protection_mode(struct amdgpu_device *adev)
++{
++	int i, result;
++	uint32_t val;
++
++	/* wait for smc boot up */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixRCU_UC_EVENTS);
++		val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done);
++		if (val)
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("SMC boot sequence is not completed\n");
++		return -EINVAL;
++	}
++
++	/* Clear firmware interrupt enable flag */
++	WREG32_SMC(ixFIRMWARE_FLAGS, 0);
++
++	/* Assert reset */
++	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++
++	result = tonga_smu_upload_firmware_image(adev);
++	if (result)
++		return result;
++
++	/* Set smc instruct start point at 0x0 */
++	tonga_program_jump_on_start(adev);
++
++	/* Enable clock */
++	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
++	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
++	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
++
++	/* De-assert reset */
++	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
++	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
++	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
++
++	/* Wait for firmware to initialize */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		val = RREG32_SMC(ixFIRMWARE_FLAGS);
++		if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
++			break;
++		udelay(1);
++	}
++
++	if (i == adev->usec_timeout) {
++		DRM_ERROR("Timeout for SMC firmware initialization\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++int tonga_smu_start(struct amdgpu_device *adev)
++{
++	int result;
++	uint32_t val;
++
++	if (!tonga_is_smc_ram_running(adev)) {
++		val = RREG32_SMC(ixSMU_FIRMWARE);
++		if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) {
++			result = tonga_smu_start_in_non_protection_mode(adev);
++			if (result)
++				return result;
++		} else {
++			result = tonga_smu_start_in_protection_mode(adev);
++			if (result)
++				return result;
++		}
++	}
++
++	return tonga_smu_request_load_fw(adev);
++}
++
++static const struct amdgpu_smumgr_funcs tonga_smumgr_funcs = {
++	.check_fw_load_finish = tonga_smu_check_fw_load_finish,
++	.request_smu_load_fw = NULL,
++	.request_smu_specific_fw = NULL,
++};
++
++int tonga_smu_init(struct amdgpu_device *adev)
++{
++	struct tonga_smu_private_data *private;
++	uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
++	uint32_t smu_internal_buffer_size = 200*4096;
++	struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
++	struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;
++	uint64_t mc_addr;
++	void *toc_buf_ptr;
++	void *smu_buf_ptr;
++	int ret;
++
++	private = kzalloc(sizeof(struct tonga_smu_private_data), GFP_KERNEL);
++	if (NULL == private)
++		return -ENOMEM;
++
++	/* allocate firmware buffers */
++	if (adev->firmware.smu_load)
++		amdgpu_ucode_init_bo(adev);
++
++	adev->smu.priv = private;
++	adev->smu.fw_flags = 0;
++
++	/* Allocate FW image data structure and header buffer */
++	ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE,
++				true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, toc_buf);
++	if (ret) {
++		DRM_ERROR("Failed to allocate memory for TOC buffer\n");
++		return -ENOMEM;
++	}
++
++	/* Allocate buffer for SMU internal buffer */
++	ret = amdgpu_bo_create(adev, smu_internal_buffer_size, PAGE_SIZE,
++				true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, smu_buf);
++	if (ret) {
++		DRM_ERROR("Failed to allocate memory for SMU internal buffer\n");
++		return -ENOMEM;
++	}
++
++	/* Retrieve GPU address for header buffer and internal buffer */
++	ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
++	if (ret) {
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to reserve the TOC buffer\n");
++		return -EINVAL;
++	}
++
++	ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.toc_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to pin the TOC buffer\n");
++		return -EINVAL;
++	}
++
++	ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.toc_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to map the TOC buffer\n");
++		return -EINVAL;
++	}
++
++	amdgpu_bo_unreserve(adev->smu.toc_buf);
++	private->header_addr_low = lower_32_bits(mc_addr);
++	private->header_addr_high = upper_32_bits(mc_addr);
++	private->header = toc_buf_ptr;
++
++	ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);
++	if (ret) {
++		amdgpu_bo_unref(&adev->smu.smu_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to reserve the SMU internal buffer\n");
++		return -EINVAL;
++	}
++
++	ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.smu_buf);
++		amdgpu_bo_unref(&adev->smu.smu_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to pin the SMU internal buffer\n");
++		return -EINVAL;
++	}
++
++	ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr);
++	if (ret) {
++		amdgpu_bo_unreserve(adev->smu.smu_buf);
++		amdgpu_bo_unref(&adev->smu.smu_buf);
++		amdgpu_bo_unref(&adev->smu.toc_buf);
++		DRM_ERROR("Failed to map the SMU internal buffer\n");
++		return -EINVAL;
++	}
++
++	amdgpu_bo_unreserve(adev->smu.smu_buf);
++	private->smu_buffer_addr_low = lower_32_bits(mc_addr);
++	private->smu_buffer_addr_high = upper_32_bits(mc_addr);
++
++	adev->smu.smumgr_funcs = &tonga_smumgr_funcs;
++
++	return 0;
++}
++
++int tonga_smu_fini(struct amdgpu_device *adev)
++{
++	amdgpu_bo_unref(&adev->smu.toc_buf);
++	amdgpu_bo_unref(&adev->smu.smu_buf);
++	kfree(adev->smu.priv);
++	adev->smu.priv = NULL;
++	if (adev->firmware.fw_buf)
++		amdgpu_ucode_fini_bo(adev);
++
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h b/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h
+new file mode 100644
+index 0000000..c031ff9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef TONGA_SMUMGR_H
++#define TONGA_SMUMGR_H
++
++#include "tonga_ppsmc.h"
++
++int tonga_smu_init(struct amdgpu_device *adev);
++int tonga_smu_fini(struct amdgpu_device *adev);
++int tonga_smu_start(struct amdgpu_device *adev);
++
++struct tonga_smu_private_data
++{
++	uint8_t *header;
++	uint32_t smu_buffer_addr_high;
++	uint32_t smu_buffer_addr_low;
++	uint32_t header_addr_high;
++	uint32_t header_addr_low;
++};
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+new file mode 100644
+index 0000000..f3b3026
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+@@ -0,0 +1,830 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_uvd.h"
++#include "vid.h"
++#include "uvd/uvd_5_0_d.h"
++#include "uvd/uvd_5_0_sh_mask.h"
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
++static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
++static int uvd_v5_0_start(struct amdgpu_device *adev);
++static void uvd_v5_0_stop(struct amdgpu_device *adev);
++
++/**
++ * uvd_v5_0_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32(mmUVD_RBC_RB_RPTR);
++}
++
++/**
++ * uvd_v5_0_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32(mmUVD_RBC_RB_WPTR);
++}
++
++/**
++ * uvd_v5_0_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
++}
++
++static int uvd_v5_0_early_init(struct amdgpu_device *adev)
++{
++	uvd_v5_0_set_ring_funcs(adev);
++	uvd_v5_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int uvd_v5_0_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* UVD TRAP */
++	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->uvd.ring;
++	sprintf(ring->name, "uvd");
++	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
++			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
++
++	return r;
++}
++
++static int uvd_v5_0_sw_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_uvd_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_sw_fini(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++/**
++ * uvd_v5_0_hw_init - start and test UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initialize the hardware, boot up the VCPU and do some testing
++ */
++static int uvd_v5_0_hw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	uint32_t tmp;
++	int r;
++
++	/* raise clocks while booting up the VCPU */
++	amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
++
++	r = uvd_v5_0_start(adev);
++	if (r)
++		goto done;
++
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		goto done;
++	}
++
++	r = amdgpu_ring_lock(ring, 10);
++	if (r) {
++		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
++		goto done;
++	}
++
++	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	/* Clear timeout status bits */
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
++	amdgpu_ring_write(ring, 0x8);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
++	amdgpu_ring_write(ring, 3);
++
++	amdgpu_ring_unlock_commit(ring);
++
++done:
++	/* lower clocks again */
++	amdgpu_asic_set_uvd_clocks(adev, 0, 0);
++
++	if (!r)
++		DRM_INFO("UVD initialized successfully.\n");
++
++	return r;
++}
++
++/**
++ * uvd_v5_0_hw_fini - stop the hardware block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the UVD block, mark ring as not ready any more
++ */
++static int uvd_v5_0_hw_fini(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++
++	uvd_v5_0_stop(adev);
++	ring->ready = false;
++
++	return 0;
++}
++
++static int uvd_v5_0_suspend(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = uvd_v5_0_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_suspend(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int uvd_v5_0_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_uvd_resume(adev);
++	if (r)
++		return r;
++
++	r = uvd_v5_0_hw_init(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++/**
++ * uvd_v5_0_mc_resume - memory controller programming
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Let the UVD memory controller know it's offsets
++ */
++static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
++{
++	uint64_t offset;
++	uint32_t size;
++
++	/* programm memory controller bits 0-27 */
++	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
++			lower_32_bits(adev->uvd.gpu_addr));
++	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
++			upper_32_bits(adev->uvd.gpu_addr));
++
++	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
++	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
++	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
++	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
++
++	offset += size;
++	size = AMDGPU_UVD_STACK_SIZE;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
++	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
++
++	offset += size;
++	size = AMDGPU_UVD_HEAP_SIZE;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
++	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
++}
++
++/**
++ * uvd_v5_0_start - start UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the UVD block
++ */
++static int uvd_v5_0_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	uint32_t rb_bufsz, tmp;
++	uint32_t lmi_swap_cntl;
++	uint32_t mp_swap_cntl;
++	int i, j, r;
++
++	/*disable DPG */
++	WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
++
++	/* disable byte swapping */
++	lmi_swap_cntl = 0;
++	mp_swap_cntl = 0;
++
++	uvd_v5_0_mc_resume(adev);
++
++	/* disable clock gating */
++	WREG32(mmUVD_CGC_GATE, 0);
++
++	/* disable interupt */
++	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
++
++	/* stall UMC and register bus before resetting VCPU */
++	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
++	mdelay(1);
++
++	/* put LMI, VCPU, RBC etc... into reset */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* take UVD block out of reset */
++	WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
++	mdelay(5);
++
++	/* initialize UVD memory controller */
++	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
++			     (1 << 21) | (1 << 9) | (1 << 20));
++
++#ifdef __BIG_ENDIAN
++	/* swap (8 in 32) RB and IB */
++	lmi_swap_cntl = 0xa;
++	mp_swap_cntl = 0;
++#endif
++	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
++	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
++
++	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
++	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
++	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
++	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
++	WREG32(mmUVD_MPC_SET_ALU, 0);
++	WREG32(mmUVD_MPC_SET_MUX, 0x88);
++
++	/* take all subblocks out of reset, except VCPU */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* enable VCPU clock */
++	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
++
++	/* enable UMC */
++	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
++
++	/* boot up the VCPU */
++	WREG32(mmUVD_SOFT_RESET, 0);
++	mdelay(10);
++
++	for (i = 0; i < 10; ++i) {
++		uint32_t status;
++		for (j = 0; j < 100; ++j) {
++			status = RREG32(mmUVD_STATUS);
++			if (status & 2)
++				break;
++			mdelay(10);
++		}
++		r = 0;
++		if (status & 2)
++			break;
++
++		DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
++		WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
++				~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++		mdelay(10);
++		WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++		mdelay(10);
++		r = -1;
++	}
++
++	if (r) {
++		DRM_ERROR("UVD not responding, giving up!!!\n");
++		return r;
++	}
++	/* enable master interrupt */
++	WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
++
++	/* clear the bit 4 of UVD_STATUS */
++	WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
++
++	rb_bufsz = order_base_2(ring->ring_size);
++	tmp = 0;
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
++	/* force RBC into idle state */
++	WREG32(mmUVD_RBC_RB_CNTL, tmp);
++
++	/* set the write pointer delay */
++	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
++
++	/* set the wb address */
++	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
++
++	/* programm the RB_BASE for ring buffer */
++	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
++			lower_32_bits(ring->gpu_addr));
++	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
++			upper_32_bits(ring->gpu_addr));
++
++	/* Initialize the ring buffer's read and write pointers */
++	WREG32(mmUVD_RBC_RB_RPTR, 0);
++
++	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
++	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
++
++	WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
++
++	return 0;
++}
++
++/**
++ * uvd_v5_0_stop - stop UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the UVD block
++ */
++static void uvd_v5_0_stop(struct amdgpu_device *adev)
++{
++	/* force RBC into idle state */
++	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
++
++	/* Stall UMC and register bus before resetting VCPU */
++	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
++	mdelay(1);
++
++	/* put VCPU into reset */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* disable VCPU clock */
++	WREG32(mmUVD_VCPU_CNTL, 0x0);
++
++	/* Unstall UMC and register bus */
++	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
++}
++
++/**
++ * uvd_v5_0_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				     bool write64bit)
++{
++	WARN_ON(write64bit);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
++	amdgpu_ring_write(ring, seq);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
++	amdgpu_ring_write(ring, addr & 0xffffffff);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
++	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
++	amdgpu_ring_write(ring, 2);
++}
++
++/**
++ * uvd_v5_0_ring_emit_semaphore - emit semaphore command
++ *
++ * @ring: amdgpu_ring pointer
++ * @semaphore: semaphore to emit commands for
++ * @emit_wait: true if we should emit a wait command
++ *
++ * Emit a semaphore command (either wait or signal) to the UVD ring.
++ */
++static bool uvd_v5_0_ring_emit_semaphore(struct amdgpu_ring *ring,
++					 struct amdgpu_semaphore *semaphore,
++					 bool emit_wait)
++{
++	uint64_t addr = semaphore->gpu_addr;
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
++	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
++	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
++	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
++
++	return true;
++}
++
++/**
++ * uvd_v5_0_ring_test_ring - register write test
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Test if we can successfully write to the context register
++ */
++static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
++	r = amdgpu_ring_lock(ring, 3);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
++			  ring->idx, r);
++		return r;
++	}
++	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmUVD_CONTEXT_ID);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n",
++			 ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
++			  ring->idx, tmp);
++		r = -EINVAL;
++	}
++	return r;
++}
++
++/**
++ * uvd_v5_0_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer
++ */
++static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
++				  struct amdgpu_ib *ib)
++{
++	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
++	amdgpu_ring_write(ring, ib->length_dw);
++}
++
++/**
++ * uvd_v5_0_ring_test_ib - test ib execution
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Test if we can successfully execute an IB
++ */
++static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_fence *fence = NULL;
++	int r;
++
++	r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
++		return r;
++	}
++
++	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_fence_wait(fence, false);
++	if (r) {
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		goto error;
++	}
++	DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
++error:
++	amdgpu_fence_unref(&fence);
++	amdgpu_asic_set_uvd_clocks(adev, 0, 0);
++	return r;
++}
++
++static bool uvd_v5_0_is_idle(struct amdgpu_device *adev)
++{
++	return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
++}
++
++static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
++			return 0;
++	}
++	return -ETIMEDOUT;
++}
++
++static int uvd_v5_0_soft_reset(struct amdgpu_device *adev)
++{
++	uvd_v5_0_stop(adev);
++
++	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
++			~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
++	mdelay(5);
++
++	return uvd_v5_0_start(adev);
++}
++
++static void uvd_v5_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "UVD 5.0 registers\n");
++	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
++		 RREG32(mmUVD_SEMA_ADDR_LOW));
++	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
++		 RREG32(mmUVD_SEMA_ADDR_HIGH));
++	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
++		 RREG32(mmUVD_SEMA_CMD));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_CMD));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_DATA0));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_DATA1));
++	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
++		 RREG32(mmUVD_ENGINE_CNTL));
++	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_CNTL));
++	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
++		 RREG32(mmUVD_LMI_EXT40_ADDR));
++	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
++		 RREG32(mmUVD_CTX_INDEX));
++	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
++		 RREG32(mmUVD_CTX_DATA));
++	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
++		 RREG32(mmUVD_CGC_GATE));
++	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
++		 RREG32(mmUVD_CGC_CTRL));
++	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
++		 RREG32(mmUVD_LMI_CTRL2));
++	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
++		 RREG32(mmUVD_MASTINT_EN));
++	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
++		 RREG32(mmUVD_LMI_ADDR_EXT));
++	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
++		 RREG32(mmUVD_LMI_CTRL));
++	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmUVD_LMI_SWAP_CNTL));
++	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmUVD_MP_SWAP_CNTL));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXA0));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXA1));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXB0));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXB1));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUX));
++	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_ALU));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE0));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE1));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE2));
++	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CNTL));
++	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
++		 RREG32(mmUVD_SOFT_RESET));
++	dev_info(adev->dev, "  UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n",
++		 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW));
++	dev_info(adev->dev, "  UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n",
++		 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH));
++	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
++		 RREG32(mmUVD_RBC_IB_SIZE));
++	dev_info(adev->dev, "  UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n",
++		 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW));
++	dev_info(adev->dev, "  UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n",
++		 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH));
++	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_RPTR));
++	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_WPTR));
++	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
++	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_CNTL));
++	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
++		 RREG32(mmUVD_STATUS));
++	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
++		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
++	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
++		 RREG32(mmUVD_CONTEXT_ID));
++}
++
++static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	// TODO
++	return 0;
++}
++
++static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: UVD TRAP\n");
++	amdgpu_fence_process(&adev->uvd.ring);
++	return 0;
++}
++
++static int uvd_v5_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	//TODO
++
++	return 0;
++}
++
++static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	/* This doesn't actually powergate the UVD block.
++	 * That's done in the dpm code via the SMC.  This
++	 * just re-inits the block as necessary.  The actual
++	 * gating still happens in the dpm code.  We should
++	 * revisit this when there is a cleaner line between
++	 * the smc and the hw blocks
++	 */
++	if (state == AMDGPU_PG_STATE_GATE) {
++		uvd_v5_0_stop(adev);
++		return 0;
++	} else {
++		return uvd_v5_0_start(adev);
++	}
++}
++
++const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs = {
++	.early_init = uvd_v5_0_early_init,
++	.late_init = NULL,
++	.sw_init = uvd_v5_0_sw_init,
++	.sw_fini = uvd_v5_0_sw_fini,
++	.hw_init = uvd_v5_0_hw_init,
++	.hw_fini = uvd_v5_0_hw_fini,
++	.suspend = uvd_v5_0_suspend,
++	.resume = uvd_v5_0_resume,
++	.is_idle = uvd_v5_0_is_idle,
++	.wait_for_idle = uvd_v5_0_wait_for_idle,
++	.soft_reset = uvd_v5_0_soft_reset,
++	.print_status = uvd_v5_0_print_status,
++	.set_clockgating_state = uvd_v5_0_set_clockgating_state,
++	.set_powergating_state = uvd_v5_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
++	.get_rptr = uvd_v5_0_ring_get_rptr,
++	.get_wptr = uvd_v5_0_ring_get_wptr,
++	.set_wptr = uvd_v5_0_ring_set_wptr,
++	.parse_cs = amdgpu_uvd_ring_parse_cs,
++	.emit_ib = uvd_v5_0_ring_emit_ib,
++	.emit_fence = uvd_v5_0_ring_emit_fence,
++	.emit_semaphore = uvd_v5_0_ring_emit_semaphore,
++	.test_ring = uvd_v5_0_ring_test_ring,
++	.test_ib = uvd_v5_0_ring_test_ib,
++	.is_lockup = amdgpu_ring_test_lockup,
++};
++
++static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
++	.set = uvd_v5_0_set_interrupt_state,
++	.process = uvd_v5_0_process_interrupt,
++};
++
++static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->uvd.irq.num_types = 1;
++	adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
+new file mode 100644
+index 0000000..7d7a152
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __UVD_V5_0_H__
++#define __UVD_V5_0_H__
++
++extern const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+new file mode 100644
+index 0000000..f59942d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -0,0 +1,810 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_uvd.h"
++#include "vid.h"
++#include "uvd/uvd_6_0_d.h"
++#include "uvd/uvd_6_0_sh_mask.h"
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
++static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
++static int uvd_v6_0_start(struct amdgpu_device *adev);
++static void uvd_v6_0_stop(struct amdgpu_device *adev);
++
++/**
++ * uvd_v6_0_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32(mmUVD_RBC_RB_RPTR);
++}
++
++/**
++ * uvd_v6_0_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32(mmUVD_RBC_RB_WPTR);
++}
++
++/**
++ * uvd_v6_0_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
++}
++
++static int uvd_v6_0_early_init(struct amdgpu_device *adev)
++{
++	uvd_v6_0_set_ring_funcs(adev);
++	uvd_v6_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int uvd_v6_0_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* UVD TRAP */
++	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->uvd.ring;
++	sprintf(ring->name, "uvd");
++	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
++			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
++
++	return r;
++}
++
++static int uvd_v6_0_sw_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_uvd_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_sw_fini(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++/**
++ * uvd_v6_0_hw_init - start and test UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Initialize the hardware, boot up the VCPU and do some testing
++ */
++static int uvd_v6_0_hw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	uint32_t tmp;
++	int r;
++
++	r = uvd_v6_0_start(adev);
++	if (r)
++		goto done;
++
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		goto done;
++	}
++
++	r = amdgpu_ring_lock(ring, 10);
++	if (r) {
++		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
++		goto done;
++	}
++
++	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
++	amdgpu_ring_write(ring, tmp);
++	amdgpu_ring_write(ring, 0xFFFFF);
++
++	/* Clear timeout status bits */
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
++	amdgpu_ring_write(ring, 0x8);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
++	amdgpu_ring_write(ring, 3);
++
++	amdgpu_ring_unlock_commit(ring);
++
++done:
++	if (!r)
++		DRM_INFO("UVD initialized successfully.\n");
++
++	return r;
++}
++
++/**
++ * uvd_v6_0_hw_fini - stop the hardware block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Stop the UVD block, mark ring as not ready any more
++ */
++static int uvd_v6_0_hw_fini(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++
++	uvd_v6_0_stop(adev);
++	ring->ready = false;
++
++	return 0;
++}
++
++static int uvd_v6_0_suspend(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = uvd_v6_0_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_uvd_suspend(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int uvd_v6_0_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_uvd_resume(adev);
++	if (r)
++		return r;
++
++	r = uvd_v6_0_hw_init(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++/**
++ * uvd_v6_0_mc_resume - memory controller programming
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Let the UVD memory controller know it's offsets
++ */
++static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
++{
++	uint64_t offset;
++	uint32_t size;
++
++	/* programm memory controller bits 0-27 */
++	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
++			lower_32_bits(adev->uvd.gpu_addr));
++	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
++			upper_32_bits(adev->uvd.gpu_addr));
++
++	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
++	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
++	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
++	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
++
++	offset += size;
++	size = AMDGPU_UVD_STACK_SIZE;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
++	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
++
++	offset += size;
++	size = AMDGPU_UVD_HEAP_SIZE;
++	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
++	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
++}
++
++/**
++ * uvd_v6_0_start - start UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the UVD block
++ */
++static int uvd_v6_0_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->uvd.ring;
++	uint32_t rb_bufsz, tmp;
++	uint32_t lmi_swap_cntl;
++	uint32_t mp_swap_cntl;
++	int i, j, r;
++
++	/*disable DPG */
++	WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
++
++	/* disable byte swapping */
++	lmi_swap_cntl = 0;
++	mp_swap_cntl = 0;
++
++	uvd_v6_0_mc_resume(adev);
++
++	/* disable clock gating */
++	WREG32(mmUVD_CGC_GATE, 0);
++
++	/* disable interupt */
++	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
++
++	/* stall UMC and register bus before resetting VCPU */
++	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
++	mdelay(1);
++
++	/* put LMI, VCPU, RBC etc... into reset */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
++		UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* take UVD block out of reset */
++	WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
++	mdelay(5);
++
++	/* initialize UVD memory controller */
++	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
++			     (1 << 21) | (1 << 9) | (1 << 20));
++
++#ifdef __BIG_ENDIAN
++	/* swap (8 in 32) RB and IB */
++	lmi_swap_cntl = 0xa;
++	mp_swap_cntl = 0;
++#endif
++	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
++	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
++
++	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
++	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
++	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
++	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
++	WREG32(mmUVD_MPC_SET_ALU, 0);
++	WREG32(mmUVD_MPC_SET_MUX, 0x88);
++
++	/* take all subblocks out of reset, except VCPU */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* enable VCPU clock */
++	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
++
++	/* enable UMC */
++	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
++
++	/* boot up the VCPU */
++	WREG32(mmUVD_SOFT_RESET, 0);
++	mdelay(10);
++
++	for (i = 0; i < 10; ++i) {
++		uint32_t status;
++
++		for (j = 0; j < 100; ++j) {
++			status = RREG32(mmUVD_STATUS);
++			if (status & 2)
++				break;
++			mdelay(10);
++		}
++		r = 0;
++		if (status & 2)
++			break;
++
++		DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
++		WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
++				~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++		mdelay(10);
++		WREG32_P(mmUVD_SOFT_RESET, 0,
++			 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++		mdelay(10);
++		r = -1;
++	}
++
++	if (r) {
++		DRM_ERROR("UVD not responding, giving up!!!\n");
++		return r;
++	}
++	/* enable master interrupt */
++	WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
++
++	/* clear the bit 4 of UVD_STATUS */
++	WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
++
++	rb_bufsz = order_base_2(ring->ring_size);
++	tmp = 0;
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
++	/* force RBC into idle state */
++	WREG32(mmUVD_RBC_RB_CNTL, tmp);
++
++	/* set the write pointer delay */
++	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
++
++	/* set the wb address */
++	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
++
++	/* programm the RB_BASE for ring buffer */
++	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
++			lower_32_bits(ring->gpu_addr));
++	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
++			upper_32_bits(ring->gpu_addr));
++
++	/* Initialize the ring buffer's read and write pointers */
++	WREG32(mmUVD_RBC_RB_RPTR, 0);
++
++	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
++	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
++
++	WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
++
++	return 0;
++}
++
++/**
++ * uvd_v6_0_stop - stop UVD block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the UVD block
++ */
++static void uvd_v6_0_stop(struct amdgpu_device *adev)
++{
++	/* force RBC into idle state */
++	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
++
++	/* Stall UMC and register bus before resetting VCPU */
++	WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
++	mdelay(1);
++
++	/* put VCPU into reset */
++	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
++	mdelay(5);
++
++	/* disable VCPU clock */
++	WREG32(mmUVD_VCPU_CNTL, 0x0);
++
++	/* Unstall UMC and register bus */
++	WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
++}
++
++/**
++ * uvd_v6_0_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				     bool write64bit)
++{
++	WARN_ON(write64bit);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
++	amdgpu_ring_write(ring, seq);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
++	amdgpu_ring_write(ring, addr & 0xffffffff);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
++	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
++	amdgpu_ring_write(ring, 0);
++	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
++	amdgpu_ring_write(ring, 2);
++}
++
++/**
++ * uvd_v6_0_ring_emit_semaphore - emit semaphore command
++ *
++ * @ring: amdgpu_ring pointer
++ * @semaphore: semaphore to emit commands for
++ * @emit_wait: true if we should emit a wait command
++ *
++ * Emit a semaphore command (either wait or signal) to the UVD ring.
++ */
++static bool uvd_v6_0_ring_emit_semaphore(struct amdgpu_ring *ring,
++					 struct amdgpu_semaphore *semaphore,
++					 bool emit_wait)
++{
++	uint64_t addr = semaphore->gpu_addr;
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
++	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
++	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
++
++	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
++	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
++
++	return true;
++}
++
++/**
++ * uvd_v6_0_ring_test_ring - register write test
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Test if we can successfully write to the context register
++ */
++static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
++	r = amdgpu_ring_lock(ring, 3);
++	if (r) {
++		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
++			  ring->idx, r);
++		return r;
++	}
++	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_unlock_commit(ring);
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(mmUVD_CONTEXT_ID);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i < adev->usec_timeout) {
++		DRM_INFO("ring test on %d succeeded in %d usecs\n",
++			 ring->idx, i);
++	} else {
++		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
++			  ring->idx, tmp);
++		r = -EINVAL;
++	}
++	return r;
++}
++
++/**
++ * uvd_v6_0_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer
++ */
++static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
++				  struct amdgpu_ib *ib)
++{
++	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
++	amdgpu_ring_write(ring, ib->length_dw);
++}
++
++/**
++ * uvd_v6_0_ring_test_ib - test ib execution
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Test if we can successfully execute an IB
++ */
++static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring)
++{
++	struct amdgpu_fence *fence = NULL;
++	int r;
++
++	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
++	if (r) {
++		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
++		goto error;
++	}
++
++	r = amdgpu_fence_wait(fence, false);
++	if (r) {
++		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
++		goto error;
++	}
++	DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
++error:
++	amdgpu_fence_unref(&fence);
++	return r;
++}
++
++static bool uvd_v6_0_is_idle(struct amdgpu_device *adev)
++{
++	return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
++}
++
++static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
++			return 0;
++	}
++	return -ETIMEDOUT;
++}
++
++static int uvd_v6_0_soft_reset(struct amdgpu_device *adev)
++{
++	uvd_v6_0_stop(adev);
++
++	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
++			~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
++	mdelay(5);
++
++	return uvd_v6_0_start(adev);
++}
++
++static void uvd_v6_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "UVD 6.0 registers\n");
++	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
++		 RREG32(mmUVD_SEMA_ADDR_LOW));
++	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
++		 RREG32(mmUVD_SEMA_ADDR_HIGH));
++	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
++		 RREG32(mmUVD_SEMA_CMD));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_CMD));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_DATA0));
++	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
++		 RREG32(mmUVD_GPCOM_VCPU_DATA1));
++	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
++		 RREG32(mmUVD_ENGINE_CNTL));
++	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
++		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
++	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_CNTL));
++	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
++		 RREG32(mmUVD_LMI_EXT40_ADDR));
++	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
++		 RREG32(mmUVD_CTX_INDEX));
++	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
++		 RREG32(mmUVD_CTX_DATA));
++	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
++		 RREG32(mmUVD_CGC_GATE));
++	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
++		 RREG32(mmUVD_CGC_CTRL));
++	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
++		 RREG32(mmUVD_LMI_CTRL2));
++	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
++		 RREG32(mmUVD_MASTINT_EN));
++	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
++		 RREG32(mmUVD_LMI_ADDR_EXT));
++	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
++		 RREG32(mmUVD_LMI_CTRL));
++	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmUVD_LMI_SWAP_CNTL));
++	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmUVD_MP_SWAP_CNTL));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXA0));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXA1));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXB0));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUXB1));
++	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_MUX));
++	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
++		 RREG32(mmUVD_MPC_SET_ALU));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE0));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE1));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
++	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CACHE_SIZE2));
++	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
++		 RREG32(mmUVD_VCPU_CNTL));
++	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
++		 RREG32(mmUVD_SOFT_RESET));
++	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
++		 RREG32(mmUVD_RBC_IB_SIZE));
++	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_RPTR));
++	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_WPTR));
++	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
++	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
++		 RREG32(mmUVD_RBC_RB_CNTL));
++	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
++		 RREG32(mmUVD_STATUS));
++	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
++		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
++	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
++		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
++	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
++		 RREG32(mmUVD_CONTEXT_ID));
++}
++
++static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	// TODO
++	return 0;
++}
++
++static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: UVD TRAP\n");
++	amdgpu_fence_process(&adev->uvd.ring);
++	return 0;
++}
++
++static int uvd_v6_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	//TODO
++
++	return 0;
++}
++
++static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	/* This doesn't actually powergate the UVD block.
++	 * That's done in the dpm code via the SMC.  This
++	 * just re-inits the block as necessary.  The actual
++	 * gating still happens in the dpm code.  We should
++	 * revisit this when there is a cleaner line between
++	 * the smc and the hw blocks
++	 */
++	if (state == AMDGPU_PG_STATE_GATE) {
++		uvd_v6_0_stop(adev);
++		return 0;
++	} else {
++		return uvd_v6_0_start(adev);
++	}
++}
++
++const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs = {
++	.early_init = uvd_v6_0_early_init,
++	.late_init = NULL,
++	.sw_init = uvd_v6_0_sw_init,
++	.sw_fini = uvd_v6_0_sw_fini,
++	.hw_init = uvd_v6_0_hw_init,
++	.hw_fini = uvd_v6_0_hw_fini,
++	.suspend = uvd_v6_0_suspend,
++	.resume = uvd_v6_0_resume,
++	.is_idle = uvd_v6_0_is_idle,
++	.wait_for_idle = uvd_v6_0_wait_for_idle,
++	.soft_reset = uvd_v6_0_soft_reset,
++	.print_status = uvd_v6_0_print_status,
++	.set_clockgating_state = uvd_v6_0_set_clockgating_state,
++	.set_powergating_state = uvd_v6_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
++	.get_rptr = uvd_v6_0_ring_get_rptr,
++	.get_wptr = uvd_v6_0_ring_get_wptr,
++	.set_wptr = uvd_v6_0_ring_set_wptr,
++	.parse_cs = amdgpu_uvd_ring_parse_cs,
++	.emit_ib = uvd_v6_0_ring_emit_ib,
++	.emit_fence = uvd_v6_0_ring_emit_fence,
++	.emit_semaphore = uvd_v6_0_ring_emit_semaphore,
++	.test_ring = uvd_v6_0_ring_test_ring,
++	.test_ib = uvd_v6_0_ring_test_ib,
++	.is_lockup = amdgpu_ring_test_lockup,
++};
++
++static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
++	.set = uvd_v6_0_set_interrupt_state,
++	.process = uvd_v6_0_process_interrupt,
++};
++
++static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->uvd.irq.num_types = 1;
++	adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
+new file mode 100644
+index 0000000..bc21afc
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __UVD_V6_0_H__
++#define __UVD_V6_0_H__
++
++extern const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+new file mode 100644
+index 0000000..384c45e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+@@ -0,0 +1,521 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * Authors: Christian König <christian.koenig@amd.com>
++ */
++
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_vce.h"
++#include "vid.h"
++#include "vce/vce_3_0_d.h"
++#include "vce/vce_3_0_sh_mask.h"
++#include "oss/oss_2_0_d.h"
++#include "oss/oss_2_0_sh_mask.h"
++
++static void vce_v3_0_mc_resume(struct amdgpu_device *adev);
++static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
++static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
++
++/**
++ * vce_v3_0_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vce.ring[0])
++		return RREG32(mmVCE_RB_RPTR);
++	else
++		return RREG32(mmVCE_RB_RPTR2);
++}
++
++/**
++ * vce_v3_0_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vce.ring[0])
++		return RREG32(mmVCE_RB_WPTR);
++	else
++		return RREG32(mmVCE_RB_WPTR2);
++}
++
++/**
++ * vce_v3_0_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vce.ring[0])
++		WREG32(mmVCE_RB_WPTR, ring->wptr);
++	else
++		WREG32(mmVCE_RB_WPTR2, ring->wptr);
++}
++
++/**
++ * vce_v3_0_start - start VCE block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the VCE block
++ */
++static int vce_v3_0_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int i, j, r;
++
++	vce_v3_0_mc_resume(adev);
++
++	/* set BUSY flag */
++	WREG32_P(mmVCE_STATUS, 1, ~1);
++
++	ring = &adev->vce.ring[0];
++	WREG32(mmVCE_RB_RPTR, ring->wptr);
++	WREG32(mmVCE_RB_WPTR, ring->wptr);
++	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
++	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
++	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
++
++	ring = &adev->vce.ring[1];
++	WREG32(mmVCE_RB_RPTR2, ring->wptr);
++	WREG32(mmVCE_RB_WPTR2, ring->wptr);
++	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
++	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
++	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
++
++	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
++
++	WREG32_P(mmVCE_SOFT_RESET,
++		 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
++		 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++
++	mdelay(100);
++
++	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++
++	for (i = 0; i < 10; ++i) {
++		uint32_t status;
++		for (j = 0; j < 100; ++j) {
++			status = RREG32(mmVCE_STATUS);
++			if (status & 2)
++				break;
++			mdelay(10);
++		}
++		r = 0;
++		if (status & 2)
++			break;
++
++		DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
++		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
++				~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++		mdelay(10);
++		WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
++		mdelay(10);
++		r = -1;
++	}
++
++	/* clear BUSY flag */
++	WREG32_P(mmVCE_STATUS, 0, ~1);
++
++	if (r) {
++		DRM_ERROR("VCE not responding, giving up!!!\n");
++		return r;
++	}
++
++	return 0;
++}
++
++static int vce_v3_0_early_init(struct amdgpu_device *adev)
++{
++	vce_v3_0_set_ring_funcs(adev);
++	vce_v3_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++static int vce_v3_0_sw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* VCE */
++	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->vce.ring[0];
++	sprintf(ring->name, "vce0");
++	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
++			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
++	if (r)
++		return r;
++
++	ring = &adev->vce.ring[1];
++	sprintf(ring->name, "vce1");
++	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
++			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int vce_v3_0_sw_fini(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_vce_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_sw_fini(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int vce_v3_0_hw_init(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int r;
++
++	r = vce_v3_0_start(adev);
++	if (r)
++		return r;
++
++	ring = &adev->vce.ring[0];
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		return r;
++	}
++
++	ring = &adev->vce.ring[1];
++	ring->ready = true;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->ready = false;
++		return r;
++	}
++
++	DRM_INFO("VCE initialized successfully.\n");
++
++	return 0;
++}
++
++static int vce_v3_0_hw_fini(struct amdgpu_device *adev)
++{
++	// TODO
++	return 0;
++}
++
++static int vce_v3_0_suspend(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = vce_v3_0_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_suspend(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static int vce_v3_0_resume(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_vce_resume(adev);
++	if (r)
++		return r;
++
++	r = vce_v3_0_hw_init(adev);
++	if (r)
++		return r;
++
++	return r;
++}
++
++static void vce_v3_0_mc_resume(struct amdgpu_device *adev)
++{
++	uint32_t offset, size;
++
++	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
++	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
++	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
++	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
++
++	WREG32(mmVCE_LMI_CTRL, 0x00398000);
++	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
++	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
++	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
++	WREG32(mmVCE_LMI_VM_CTRL, 0);
++
++	WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
++	offset = AMDGPU_VCE_FIRMWARE_OFFSET;
++	size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size);
++	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
++	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
++
++	offset += size;
++	size = AMDGPU_VCE_STACK_SIZE;
++	WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
++	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
++
++	offset += size;
++	size = AMDGPU_VCE_HEAP_SIZE;
++	WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
++	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
++
++	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
++
++	WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
++		 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
++}
++
++static bool vce_v3_0_is_idle(struct amdgpu_device *adev)
++{
++	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
++}
++
++static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev)
++{
++	unsigned i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
++			return 0;
++	}
++	return -ETIMEDOUT;
++}
++
++static int vce_v3_0_soft_reset(struct amdgpu_device *adev)
++{
++	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
++			~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
++	mdelay(5);
++
++	return vce_v3_0_start(adev);
++}
++
++static void vce_v3_0_print_status(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "VCE 3.0 registers\n");
++	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",
++		 RREG32(mmVCE_STATUS));
++	dev_info(adev->dev, "  VCE_VCPU_CNTL=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CNTL));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE0=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_SIZE0));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE1=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_SIZE1));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
++	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE2=0x%08X\n",
++		 RREG32(mmVCE_VCPU_CACHE_SIZE2));
++	dev_info(adev->dev, "  VCE_SOFT_RESET=0x%08X\n",
++		 RREG32(mmVCE_SOFT_RESET));
++	dev_info(adev->dev, "  VCE_RB_BASE_LO2=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_LO2));
++	dev_info(adev->dev, "  VCE_RB_BASE_HI2=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_HI2));
++	dev_info(adev->dev, "  VCE_RB_SIZE2=0x%08X\n",
++		 RREG32(mmVCE_RB_SIZE2));
++	dev_info(adev->dev, "  VCE_RB_RPTR2=0x%08X\n",
++		 RREG32(mmVCE_RB_RPTR2));
++	dev_info(adev->dev, "  VCE_RB_WPTR2=0x%08X\n",
++		 RREG32(mmVCE_RB_WPTR2));
++	dev_info(adev->dev, "  VCE_RB_BASE_LO=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_LO));
++	dev_info(adev->dev, "  VCE_RB_BASE_HI=0x%08X\n",
++		 RREG32(mmVCE_RB_BASE_HI));
++	dev_info(adev->dev, "  VCE_RB_SIZE=0x%08X\n",
++		 RREG32(mmVCE_RB_SIZE));
++	dev_info(adev->dev, "  VCE_RB_RPTR=0x%08X\n",
++		 RREG32(mmVCE_RB_RPTR));
++	dev_info(adev->dev, "  VCE_RB_WPTR=0x%08X\n",
++		 RREG32(mmVCE_RB_WPTR));
++	dev_info(adev->dev, "  VCE_CLOCK_GATING_A=0x%08X\n",
++		 RREG32(mmVCE_CLOCK_GATING_A));
++	dev_info(adev->dev, "  VCE_CLOCK_GATING_B=0x%08X\n",
++		 RREG32(mmVCE_CLOCK_GATING_B));
++	dev_info(adev->dev, "  VCE_UENC_CLOCK_GATING=0x%08X\n",
++		 RREG32(mmVCE_UENC_CLOCK_GATING));
++	dev_info(adev->dev, "  VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
++		 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
++	dev_info(adev->dev, "  VCE_SYS_INT_EN=0x%08X\n",
++		 RREG32(mmVCE_SYS_INT_EN));
++	dev_info(adev->dev, "  VCE_LMI_CTRL2=0x%08X\n",
++		 RREG32(mmVCE_LMI_CTRL2));
++	dev_info(adev->dev, "  VCE_LMI_CTRL=0x%08X\n",
++		 RREG32(mmVCE_LMI_CTRL));
++	dev_info(adev->dev, "  VCE_LMI_VM_CTRL=0x%08X\n",
++		 RREG32(mmVCE_LMI_VM_CTRL));
++	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL=0x%08X\n",
++		 RREG32(mmVCE_LMI_SWAP_CNTL));
++	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL1=0x%08X\n",
++		 RREG32(mmVCE_LMI_SWAP_CNTL1));
++	dev_info(adev->dev, "  VCE_LMI_CACHE_CTRL=0x%08X\n",
++		 RREG32(mmVCE_LMI_CACHE_CTRL));
++}
++
++static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	uint32_t val = 0;
++
++	if (state == AMDGPU_IRQ_STATE_ENABLE)
++		val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
++
++	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
++	return 0;
++}
++
++static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: VCE\n");
++	switch (entry->src_data) {
++	case 0:
++		amdgpu_fence_process(&adev->vce.ring[0]);
++		break;
++	case 1:
++		amdgpu_fence_process(&adev->vce.ring[1]);
++		break;
++	default:
++		DRM_ERROR("Unhandled interrupt: %d %d\n",
++			  entry->src_id, entry->src_data);
++		break;
++	}
++
++	return 0;
++}
++
++static int vce_v3_0_set_clockgating_state(struct amdgpu_device *adev,
++					  enum amdgpu_clockgating_state state)
++{
++	//TODO
++	return 0;
++}
++
++static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev,
++					  enum amdgpu_powergating_state state)
++{
++	/* This doesn't actually powergate the VCE block.
++	 * That's done in the dpm code via the SMC.  This
++	 * just re-inits the block as necessary.  The actual
++	 * gating still happens in the dpm code.  We should
++	 * revisit this when there is a cleaner line between
++	 * the smc and the hw blocks
++	 */
++	if (state == AMDGPU_PG_STATE_GATE)
++		/* XXX do we need a vce_v3_0_stop()? */
++		return 0;
++	else
++		return vce_v3_0_start(adev);
++}
++
++const struct amdgpu_ip_funcs vce_v3_0_ip_funcs = {
++	.early_init = vce_v3_0_early_init,
++	.late_init = NULL,
++	.sw_init = vce_v3_0_sw_init,
++	.sw_fini = vce_v3_0_sw_fini,
++	.hw_init = vce_v3_0_hw_init,
++	.hw_fini = vce_v3_0_hw_fini,
++	.suspend = vce_v3_0_suspend,
++	.resume = vce_v3_0_resume,
++	.is_idle = vce_v3_0_is_idle,
++	.wait_for_idle = vce_v3_0_wait_for_idle,
++	.soft_reset = vce_v3_0_soft_reset,
++	.print_status = vce_v3_0_print_status,
++	.set_clockgating_state = vce_v3_0_set_clockgating_state,
++	.set_powergating_state = vce_v3_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
++	.get_rptr = vce_v3_0_ring_get_rptr,
++	.get_wptr = vce_v3_0_ring_get_wptr,
++	.set_wptr = vce_v3_0_ring_set_wptr,
++	.parse_cs = amdgpu_vce_ring_parse_cs,
++	.emit_ib = amdgpu_vce_ring_emit_ib,
++	.emit_fence = amdgpu_vce_ring_emit_fence,
++	.emit_semaphore = amdgpu_vce_ring_emit_semaphore,
++	.test_ring = amdgpu_vce_ring_test_ring,
++	.test_ib = amdgpu_vce_ring_test_ib,
++	.is_lockup = amdgpu_ring_test_lockup,
++};
++
++static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs;
++	adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs;
++}
++
++static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
++	.set = vce_v3_0_set_interrupt_state,
++	.process = vce_v3_0_process_interrupt,
++};
++
++static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->vce.irq.num_types = 1;
++	adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
+new file mode 100644
+index 0000000..f3c2ba9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __VCE_V3_0_H__
++#define __VCE_V3_0_H__
++
++extern const struct amdgpu_ip_funcs vce_v3_0_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+new file mode 100644
+index 0000000..20a1598
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -0,0 +1,1373 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include "drmP.h"
++#include "amdgpu.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_ih.h"
++#include "amdgpu_uvd.h"
++#include "amdgpu_vce.h"
++#include "amdgpu_ucode.h"
++#include "atom.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "oss/oss_3_0_d.h"
++#include "oss/oss_3_0_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "gca/gfx_8_0_d.h"
++#include "gca/gfx_8_0_sh_mask.h"
++
++#include "smu/smu_7_1_1_d.h"
++#include "smu/smu_7_1_1_sh_mask.h"
++
++#include "uvd/uvd_5_0_d.h"
++#include "uvd/uvd_5_0_sh_mask.h"
++
++#include "vce/vce_3_0_d.h"
++#include "vce/vce_3_0_sh_mask.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++
++#include "vid.h"
++#include "vi.h"
++#include "vi_dpm.h"
++#include "gmc_v8_0.h"
++#include "gfx_v8_0.h"
++#include "sdma_v2_4.h"
++#include "sdma_v3_0.h"
++#include "dce_v10_0.h"
++#include "dce_v11_0.h"
++#include "iceland_ih.h"
++#include "tonga_ih.h"
++#include "cz_ih.h"
++#include "uvd_v5_0.h"
++#include "uvd_v6_0.h"
++#include "vce_v3_0.h"
++
++/*
++ * Indirect registers accessor
++ */
++static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(mmPCIE_INDEX, reg);
++	(void)RREG32(mmPCIE_INDEX);
++	r = RREG32(mmPCIE_DATA);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++	return r;
++}
++
++static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(mmPCIE_INDEX, reg);
++	(void)RREG32(mmPCIE_INDEX);
++	WREG32(mmPCIE_DATA, v);
++	(void)RREG32(mmPCIE_DATA);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
++static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, (reg));
++	r = RREG32(mmSMC_IND_DATA_0);
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++	return r;
++}
++
++static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->smc_idx_lock, flags);
++	WREG32(mmSMC_IND_INDEX_0, (reg));
++	WREG32(mmSMC_IND_DATA_0, (v));
++	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
++}
++
++static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
++	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
++	r = RREG32(mmUVD_CTX_DATA);
++	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
++	return r;
++}
++
++static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
++	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
++	WREG32(mmUVD_CTX_DATA, (v));
++	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
++}
++
++static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags;
++	u32 r;
++
++	spin_lock_irqsave(&adev->didt_idx_lock, flags);
++	WREG32(mmDIDT_IND_INDEX, (reg));
++	r = RREG32(mmDIDT_IND_DATA);
++	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
++	return r;
++}
++
++static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&adev->didt_idx_lock, flags);
++	WREG32(mmDIDT_IND_INDEX, (reg));
++	WREG32(mmDIDT_IND_DATA, (v));
++	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
++}
++
++static const u32 tonga_mgcg_cgcg_init[] =
++{
++	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
++	mmPCIE_INDEX, 0xffffffff, 0x0140001c,
++	mmPCIE_DATA, 0x000f0000, 0x00000000,
++	mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
++	mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
++	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
++	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
++	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
++	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
++};
++
++static const u32 iceland_mgcg_cgcg_init[] =
++{
++	mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
++	mmPCIE_DATA, 0x000f0000, 0x00000000,
++	mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
++	mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
++	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
++};
++
++static const u32 cz_mgcg_cgcg_init[] =
++{
++	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
++	mmPCIE_INDEX, 0xffffffff, 0x0140001c,
++	mmPCIE_DATA, 0x000f0000, 0x00000000,
++	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
++	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
++	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
++	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
++};
++
++static void vi_init_golden_registers(struct amdgpu_device *adev)
++{
++	/* Some of the registers might be dependent on GRBM_GFX_INDEX */
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		amdgpu_program_register_sequence(adev,
++						 iceland_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
++		break;
++	case CHIP_TONGA:
++		amdgpu_program_register_sequence(adev,
++						 tonga_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
++		break;
++	case CHIP_CARRIZO:
++		amdgpu_program_register_sequence(adev,
++						 cz_mgcg_cgcg_init,
++						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
++		break;
++	default:
++		break;
++	}
++	mutex_unlock(&adev->grbm_idx_mutex);
++}
++
++/**
++ * vi_get_xclk - get the xclk
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Returns the reference clock used by the gfx engine
++ * (VI).
++ */
++static u32 vi_get_xclk(struct amdgpu_device *adev)
++{
++	u32 reference_clock = adev->clock.spll.reference_freq;
++	u32 tmp;
++
++	if (adev->flags & AMDGPU_IS_APU)
++		return reference_clock;
++
++	tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
++	if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
++		return 1000;
++
++	tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
++	if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
++		return reference_clock / 4;
++
++	return reference_clock;
++}
++
++/**
++ * vi_srbm_select - select specific register instances
++ *
++ * @adev: amdgpu_device pointer
++ * @me: selected ME (micro engine)
++ * @pipe: pipe
++ * @queue: queue
++ * @vmid: VMID
++ *
++ * Switches the currently active registers instances.  Some
++ * registers are instanced per VMID, others are instanced per
++ * me/pipe/queue combination.
++ */
++void vi_srbm_select(struct amdgpu_device *adev,
++		     u32 me, u32 pipe, u32 queue, u32 vmid)
++{
++	u32 srbm_gfx_cntl = 0;
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
++	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
++	WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
++}
++
++static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
++{
++	/* todo */
++}
++
++static bool vi_read_disabled_bios(struct amdgpu_device *adev)
++{
++	u32 bus_cntl;
++	u32 d1vga_control = 0;
++	u32 d2vga_control = 0;
++	u32 vga_render_control = 0;
++	u32 rom_cntl;
++	bool r;
++
++	bus_cntl = RREG32(mmBUS_CNTL);
++	if (adev->mode_info.num_crtc) {
++		d1vga_control = RREG32(mmD1VGA_CONTROL);
++		d2vga_control = RREG32(mmD2VGA_CONTROL);
++		vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
++	}
++	rom_cntl = RREG32_SMC(ixROM_CNTL);
++
++	/* enable the rom */
++	WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
++	if (adev->mode_info.num_crtc) {
++		/* Disable VGA mode */
++		WREG32(mmD1VGA_CONTROL,
++		       (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
++					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
++		WREG32(mmD2VGA_CONTROL,
++		       (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
++					  D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
++		WREG32(mmVGA_RENDER_CONTROL,
++		       (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
++	}
++	WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
++
++	r = amdgpu_read_bios(adev);
++
++	/* restore regs */
++	WREG32(mmBUS_CNTL, bus_cntl);
++	if (adev->mode_info.num_crtc) {
++		WREG32(mmD1VGA_CONTROL, d1vga_control);
++		WREG32(mmD2VGA_CONTROL, d2vga_control);
++		WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
++	}
++	WREG32_SMC(ixROM_CNTL, rom_cntl);
++	return r;
++}
++static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
++	{mmGB_MACROTILE_MODE7, true},
++};
++
++static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
++	{mmGB_TILE_MODE7, true},
++	{mmGB_TILE_MODE12, true},
++	{mmGB_TILE_MODE17, true},
++	{mmGB_TILE_MODE23, true},
++	{mmGB_MACROTILE_MODE7, true},
++};
++
++static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
++	{mmGRBM_STATUS, false},
++	{mmGB_ADDR_CONFIG, false},
++	{mmMC_ARB_RAMCFG, false},
++	{mmGB_TILE_MODE0, false},
++	{mmGB_TILE_MODE1, false},
++	{mmGB_TILE_MODE2, false},
++	{mmGB_TILE_MODE3, false},
++	{mmGB_TILE_MODE4, false},
++	{mmGB_TILE_MODE5, false},
++	{mmGB_TILE_MODE6, false},
++	{mmGB_TILE_MODE7, false},
++	{mmGB_TILE_MODE8, false},
++	{mmGB_TILE_MODE9, false},
++	{mmGB_TILE_MODE10, false},
++	{mmGB_TILE_MODE11, false},
++	{mmGB_TILE_MODE12, false},
++	{mmGB_TILE_MODE13, false},
++	{mmGB_TILE_MODE14, false},
++	{mmGB_TILE_MODE15, false},
++	{mmGB_TILE_MODE16, false},
++	{mmGB_TILE_MODE17, false},
++	{mmGB_TILE_MODE18, false},
++	{mmGB_TILE_MODE19, false},
++	{mmGB_TILE_MODE20, false},
++	{mmGB_TILE_MODE21, false},
++	{mmGB_TILE_MODE22, false},
++	{mmGB_TILE_MODE23, false},
++	{mmGB_TILE_MODE24, false},
++	{mmGB_TILE_MODE25, false},
++	{mmGB_TILE_MODE26, false},
++	{mmGB_TILE_MODE27, false},
++	{mmGB_TILE_MODE28, false},
++	{mmGB_TILE_MODE29, false},
++	{mmGB_TILE_MODE30, false},
++	{mmGB_TILE_MODE31, false},
++	{mmGB_MACROTILE_MODE0, false},
++	{mmGB_MACROTILE_MODE1, false},
++	{mmGB_MACROTILE_MODE2, false},
++	{mmGB_MACROTILE_MODE3, false},
++	{mmGB_MACROTILE_MODE4, false},
++	{mmGB_MACROTILE_MODE5, false},
++	{mmGB_MACROTILE_MODE6, false},
++	{mmGB_MACROTILE_MODE7, false},
++	{mmGB_MACROTILE_MODE8, false},
++	{mmGB_MACROTILE_MODE9, false},
++	{mmGB_MACROTILE_MODE10, false},
++	{mmGB_MACROTILE_MODE11, false},
++	{mmGB_MACROTILE_MODE12, false},
++	{mmGB_MACROTILE_MODE13, false},
++	{mmGB_MACROTILE_MODE14, false},
++	{mmGB_MACROTILE_MODE15, false},
++	{mmCC_RB_BACKEND_DISABLE, false, true},
++	{mmGC_USER_RB_BACKEND_DISABLE, false, true},
++	{mmGB_BACKEND_MAP, false, false},
++	{mmPA_SC_RASTER_CONFIG, false, true},
++	{mmPA_SC_RASTER_CONFIG_1, false, true},
++};
++
++static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
++					 u32 sh_num, u32 reg_offset)
++{
++	uint32_t val;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	if (se_num != 0xffffffff || sh_num != 0xffffffff)
++		gfx_v8_0_select_se_sh(adev, se_num, sh_num);
++
++	val = RREG32(reg_offset);
++
++	if (se_num != 0xffffffff || sh_num != 0xffffffff)
++		gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++	return val;
++}
++
++static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
++			    u32 sh_num, u32 reg_offset, u32 *value)
++{
++	struct amdgpu_allowed_register_entry *asic_register_table = NULL;
++	struct amdgpu_allowed_register_entry *asic_register_entry;
++	uint32_t size, i;
++
++	*value = 0;
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		asic_register_table = tonga_allowed_read_registers;
++		size = ARRAY_SIZE(tonga_allowed_read_registers);
++		break;
++	case CHIP_TONGA:
++	case CHIP_CARRIZO:
++		asic_register_table = cz_allowed_read_registers;
++		size = ARRAY_SIZE(cz_allowed_read_registers);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	if (asic_register_table) {
++		for (i = 0; i < size; i++) {
++			asic_register_entry = asic_register_table + i;
++			if (reg_offset != asic_register_entry->reg_offset)
++				continue;
++			if (!asic_register_entry->untouched)
++				*value = asic_register_entry->grbm_indexed ?
++					vi_read_indexed_register(adev, se_num,
++								 sh_num, reg_offset) :
++					RREG32(reg_offset);
++			return 0;
++		}
++	}
++
++	for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
++		if (reg_offset != vi_allowed_read_registers[i].reg_offset)
++			continue;
++
++		if (!vi_allowed_read_registers[i].untouched)
++			*value = vi_allowed_read_registers[i].grbm_indexed ?
++				vi_read_indexed_register(adev, se_num,
++							 sh_num, reg_offset) :
++				RREG32(reg_offset);
++		return 0;
++	}
++	return -EINVAL;
++}
++
++static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
++{
++	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
++		RREG32(mmGRBM_STATUS));
++	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
++		RREG32(mmGRBM_STATUS2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE0));
++	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE1));
++	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE2));
++	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
++		RREG32(mmGRBM_STATUS_SE3));
++	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
++		RREG32(mmSRBM_STATUS));
++	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
++		RREG32(mmSRBM_STATUS2));
++	dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
++		RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
++	dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
++		 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
++	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
++	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT2));
++	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
++		 RREG32(mmCP_STALLED_STAT3));
++	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
++		 RREG32(mmCP_CPF_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPF_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
++	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
++	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
++		 RREG32(mmCP_CPC_STALLED_STAT1));
++	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
++}
++
++/**
++ * vi_gpu_check_soft_reset - check which blocks are busy
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Check which blocks are busy and return the relevant reset
++ * mask to be used by vi_gpu_soft_reset().
++ * Returns a mask of the blocks to be reset.
++ */
++u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
++{
++	u32 reset_mask = 0;
++	u32 tmp;
++
++	/* GRBM_STATUS */
++	tmp = RREG32(mmGRBM_STATUS);
++	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
++		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
++		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
++		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
++		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
++		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
++		reset_mask |= AMDGPU_RESET_GFX;
++
++	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
++		reset_mask |= AMDGPU_RESET_CP;
++
++	/* GRBM_STATUS2 */
++	tmp = RREG32(mmGRBM_STATUS2);
++	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_RLC;
++
++	if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
++		   GRBM_STATUS2__CPC_BUSY_MASK |
++		   GRBM_STATUS2__CPG_BUSY_MASK))
++		reset_mask |= AMDGPU_RESET_CP;
++
++	/* SRBM_STATUS2 */
++	tmp = RREG32(mmSRBM_STATUS2);
++	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_DMA;
++
++	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_DMA1;
++
++	/* SRBM_STATUS */
++	tmp = RREG32(mmSRBM_STATUS);
++
++	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_IH;
++
++	if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_SEM;
++
++	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
++		reset_mask |= AMDGPU_RESET_GRBM;
++
++	if (adev->asic_type != CHIP_TOPAZ) {
++		if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
++			   SRBM_STATUS__UVD_BUSY_MASK))
++			reset_mask |= AMDGPU_RESET_UVD;
++	}
++
++	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
++		reset_mask |= AMDGPU_RESET_VMC;
++
++	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
++		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
++		reset_mask |= AMDGPU_RESET_MC;
++
++	/* SDMA0_STATUS_REG */
++	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
++	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
++		reset_mask |= AMDGPU_RESET_DMA;
++
++	/* SDMA1_STATUS_REG */
++	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
++	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
++		reset_mask |= AMDGPU_RESET_DMA1;
++#if 0
++	/* VCE_STATUS */
++	if (adev->asic_type != CHIP_TOPAZ) {
++		tmp = RREG32(mmVCE_STATUS);
++		if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
++			reset_mask |= AMDGPU_RESET_VCE;
++		if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
++			reset_mask |= AMDGPU_RESET_VCE1;
++
++	}
++
++	if (adev->asic_type != CHIP_TOPAZ) {
++		if (amdgpu_display_is_display_hung(adev))
++			reset_mask |= AMDGPU_RESET_DISPLAY;
++	}
++#endif
++
++	/* Skip MC reset as it's mostly likely not hung, just busy */
++	if (reset_mask & AMDGPU_RESET_MC) {
++		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
++		reset_mask &= ~AMDGPU_RESET_MC;
++	}
++
++	return reset_mask;
++}
++
++/**
++ * vi_gpu_soft_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ * @reset_mask: mask of which blocks to reset
++ *
++ * Soft reset the blocks specified in @reset_mask.
++ */
++static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
++	u32 tmp;
++
++	if (reset_mask == 0)
++		return;
++
++	dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
++
++	vi_print_gpu_status_regs(adev);
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
++	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
++		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
++
++	/* disable CG/PG */
++
++	/* stop the rlc */
++	//XXX
++	//gfx_v8_0_rlc_stop(adev);
++
++	/* Disable GFX parsing/prefetching */
++	tmp = RREG32(mmCP_ME_CNTL);
++	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
++	WREG32(mmCP_ME_CNTL, tmp);
++
++	/* Disable MEC parsing/prefetching */
++	tmp = RREG32(mmCP_MEC_CNTL);
++	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
++	WREG32(mmCP_MEC_CNTL, tmp);
++
++	if (reset_mask & AMDGPU_RESET_DMA) {
++		/* sdma0 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
++		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++	}
++	if (reset_mask & AMDGPU_RESET_DMA1) {
++		/* sdma1 */
++		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
++		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++	}
++
++	gmc_v8_0_mc_stop(adev, &save);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
++	}
++
++	if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
++		grbm_soft_reset =
++			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
++		grbm_soft_reset =
++			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
++	}
++
++	if (reset_mask & AMDGPU_RESET_CP) {
++		grbm_soft_reset =
++			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
++	}
++
++	if (reset_mask & AMDGPU_RESET_DMA)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
++
++	if (reset_mask & AMDGPU_RESET_DMA1)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
++
++	if (reset_mask & AMDGPU_RESET_DISPLAY)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
++
++	if (reset_mask & AMDGPU_RESET_RLC)
++		grbm_soft_reset =
++			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
++
++	if (reset_mask & AMDGPU_RESET_SEM)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
++
++	if (reset_mask & AMDGPU_RESET_IH)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
++
++	if (reset_mask & AMDGPU_RESET_GRBM)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
++
++	if (reset_mask & AMDGPU_RESET_VMC)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
++
++	if (reset_mask & AMDGPU_RESET_UVD)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
++
++	if (reset_mask & AMDGPU_RESET_VCE)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
++
++	if (reset_mask & AMDGPU_RESET_VCE)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
++
++	if (!(adev->flags & AMDGPU_IS_APU)) {
++		if (reset_mask & AMDGPU_RESET_MC)
++		srbm_soft_reset =
++			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
++	}
++
++	if (grbm_soft_reset) {
++		tmp = RREG32(mmGRBM_SOFT_RESET);
++		tmp |= grbm_soft_reset;
++		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmGRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmGRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~grbm_soft_reset;
++		WREG32(mmGRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmGRBM_SOFT_RESET);
++	}
++
++	if (srbm_soft_reset) {
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++		tmp |= srbm_soft_reset;
++		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++
++		udelay(50);
++
++		tmp &= ~srbm_soft_reset;
++		WREG32(mmSRBM_SOFT_RESET, tmp);
++		tmp = RREG32(mmSRBM_SOFT_RESET);
++	}
++
++	/* Wait a little for things to settle down */
++	udelay(50);
++
++	gmc_v8_0_mc_resume(adev, &save);
++	udelay(50);
++
++	vi_print_gpu_status_regs(adev);
++}
++
++static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
++{
++	struct amdgpu_mode_mc_save save;
++	u32 tmp, i;
++
++	dev_info(adev->dev, "GPU pci config reset\n");
++
++	/* disable dpm? */
++
++	/* disable cg/pg */
++
++	/* Disable GFX parsing/prefetching */
++	tmp = RREG32(mmCP_ME_CNTL);
++	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
++	WREG32(mmCP_ME_CNTL, tmp);
++
++	/* Disable MEC parsing/prefetching */
++	tmp = RREG32(mmCP_MEC_CNTL);
++	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
++	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
++	WREG32(mmCP_MEC_CNTL, tmp);
++
++	/* Disable GFX parsing/prefetching */
++	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
++		CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
++
++	/* Disable MEC parsing/prefetching */
++	WREG32(mmCP_MEC_CNTL,
++			CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
++
++	/* sdma0 */
++	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
++	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
++	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
++
++	/* sdma1 */
++	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
++	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
++	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
++
++	/* XXX other engines? */
++
++	/* halt the rlc, disable cp internal ints */
++	//XXX
++	//gfx_v8_0_rlc_stop(adev);
++
++	udelay(50);
++
++	/* disable mem access */
++	gmc_v8_0_mc_stop(adev, &save);
++	if (amdgpu_asic_wait_for_mc_idle(adev)) {
++		dev_warn(adev->dev, "Wait for MC idle timed out !\n");
++	}
++
++	/* disable BM */
++	pci_clear_master(adev->pdev);
++	/* reset */
++	amdgpu_pci_config_reset(adev);
++
++	udelay(100);
++
++	/* wait for asic to come out of reset */
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
++			break;
++		udelay(1);
++	}
++
++}
++
++static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
++{
++	u32 tmp = RREG32(mmBIOS_SCRATCH_3);
++
++	if (hung)
++		tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
++	else
++		tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
++
++	WREG32(mmBIOS_SCRATCH_3, tmp);
++}
++
++/**
++ * vi_asic_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up which blocks are hung and attempt
++ * to reset them.
++ * Returns 0 for success.
++ */
++static int vi_asic_reset(struct amdgpu_device *adev)
++{
++	u32 reset_mask;
++
++	reset_mask = vi_gpu_check_soft_reset(adev);
++
++	if (reset_mask)
++		vi_set_bios_scratch_engine_hung(adev, true);
++
++	/* try soft reset */
++	vi_gpu_soft_reset(adev, reset_mask);
++
++	reset_mask = vi_gpu_check_soft_reset(adev);
++
++	/* try pci config reset */
++	if (reset_mask && amdgpu_hard_reset)
++		vi_gpu_pci_config_reset(adev);
++
++	reset_mask = vi_gpu_check_soft_reset(adev);
++
++	if (!reset_mask)
++		vi_set_bios_scratch_engine_hung(adev, false);
++
++	return 0;
++}
++
++static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
++			u32 cntl_reg, u32 status_reg)
++{
++	int r, i;
++	struct atom_clock_dividers dividers;
++	uint32_t tmp;
++
++	r = amdgpu_atombios_get_clock_dividers(adev,
++					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
++					       clock, false, &dividers);
++	if (r)
++		return r;
++
++	tmp = RREG32_SMC(cntl_reg);
++	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
++		CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
++	tmp |= dividers.post_divider;
++	WREG32_SMC(cntl_reg, tmp);
++
++	for (i = 0; i < 100; i++) {
++		if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
++			break;
++		mdelay(10);
++	}
++	if (i == 100)
++		return -ETIMEDOUT;
++
++	return 0;
++}
++
++static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
++{
++	int r;
++
++	r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
++	if (r)
++		return r;
++
++	r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
++
++	return 0;
++}
++
++static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
++{
++	/* todo */
++
++	return 0;
++}
++
++static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
++{
++	u32 mask;
++	int ret;
++
++	if (amdgpu_pcie_gen2 == 0)
++		return;
++
++	if (adev->flags & AMDGPU_IS_APU)
++		return;
++
++	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
++	if (ret != 0)
++		return;
++
++	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
++		return;
++
++	/* todo */
++}
++
++static void vi_program_aspm(struct amdgpu_device *adev)
++{
++
++	if (amdgpu_aspm == 0)
++		return;
++
++	/* todo */
++}
++
++static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
++					bool enable)
++{
++	u32 tmp;
++
++	/* not necessary on CZ */
++	if (adev->flags & AMDGPU_IS_APU)
++		return;
++
++	tmp = RREG32(mmBIF_DOORBELL_APER_EN);
++	if (enable)
++		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
++	else
++		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
++
++	WREG32(mmBIF_DOORBELL_APER_EN, tmp);
++}
++
++/* topaz has no DCE, UVD, VCE */
++static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vi_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 2,
++		.minor = 4,
++		.rev = 0,
++		.funcs = &iceland_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 1,
++		.rev = 0,
++		.funcs = &iceland_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gfx_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 2,
++		.minor = 4,
++		.rev = 0,
++		.funcs = &sdma_v2_4_ip_funcs,
++	},
++};
++
++static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vi_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 3,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &tonga_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 7,
++		.minor = 1,
++		.rev = 0,
++		.funcs = &tonga_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 10,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &dce_v10_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gfx_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 3,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &sdma_v3_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 5,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &uvd_v5_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 3,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v3_0_ip_funcs,
++	},
++};
++
++static const struct amdgpu_ip_block_version cz_ip_blocks[] =
++{
++	/* ORDER MATTERS! */
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_COMMON,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vi_common_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GMC,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gmc_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_IH,
++		.major = 3,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cz_ih_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SMC,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &cz_dpm_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_DCE,
++		.major = 11,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &dce_v11_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_GFX,
++		.major = 8,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &gfx_v8_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_SDMA,
++		.major = 3,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &sdma_v3_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_UVD,
++		.major = 6,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &uvd_v6_0_ip_funcs,
++	},
++	{
++		.type = AMDGPU_IP_BLOCK_TYPE_VCE,
++		.major = 3,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &vce_v3_0_ip_funcs,
++	},
++};
++
++int vi_set_ip_blocks(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		adev->ip_blocks = topaz_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
++		break;
++	case CHIP_TONGA:
++		adev->ip_blocks = tonga_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
++		break;
++	case CHIP_CARRIZO:
++		adev->ip_blocks = cz_ip_blocks;
++		adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL);
++	if (adev->ip_block_enabled == NULL)
++		return -ENOMEM;
++
++	return 0;
++}
++
++static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
++{
++	if (adev->asic_type == CHIP_TOPAZ)
++		return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
++			>> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
++	else
++		return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
++			>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
++}
++
++static const struct amdgpu_asic_funcs vi_asic_funcs =
++{
++	.read_disabled_bios = &vi_read_disabled_bios,
++	.read_register = &vi_read_register,
++	.reset = &vi_asic_reset,
++	.set_vga_state = &vi_vga_set_state,
++	.get_xclk = &vi_get_xclk,
++	.set_uvd_clocks = &vi_set_uvd_clocks,
++	.set_vce_clocks = &vi_set_vce_clocks,
++	.get_cu_info = &gfx_v8_0_get_cu_info,
++	/* these should be moved to their own ip modules */
++	.get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
++	.wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
++};
++
++static int vi_common_early_init(struct amdgpu_device *adev)
++{
++	bool smc_enabled = false;
++
++	adev->smc_rreg = &vi_smc_rreg;
++	adev->smc_wreg = &vi_smc_wreg;
++	adev->pcie_rreg = &vi_pcie_rreg;
++	adev->pcie_wreg = &vi_pcie_wreg;
++	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
++	adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
++	adev->didt_rreg = &vi_didt_rreg;
++	adev->didt_wreg = &vi_didt_wreg;
++
++	adev->asic_funcs = &vi_asic_funcs;
++
++	if (amdgpu_get_ip_block(adev, AMDGPU_IP_BLOCK_TYPE_SMC) &&
++		(amdgpu_ip_block_mask & (1 << AMDGPU_IP_BLOCK_TYPE_SMC)))
++		smc_enabled = true;
++
++	adev->rev_id = vi_get_rev_id(adev);
++	adev->external_rev_id = 0xFF;
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++		adev->has_uvd = false;
++		adev->cg_flags = 0;
++		adev->pg_flags = 0;
++		adev->external_rev_id = 0x1;
++		if (amdgpu_smc_load_fw && smc_enabled)
++			adev->firmware.smu_load = true;
++		break;
++	case CHIP_TONGA:
++		adev->has_uvd = true;
++		adev->cg_flags = 0;
++		adev->pg_flags = 0;
++		adev->external_rev_id = adev->rev_id + 0x14;
++		if (amdgpu_smc_load_fw && smc_enabled)
++			adev->firmware.smu_load = true;
++		break;
++	case CHIP_CARRIZO:
++		adev->has_uvd = true;
++		adev->cg_flags = 0;
++		adev->pg_flags = 0;
++		adev->external_rev_id = adev->rev_id + 0x1;
++		if (amdgpu_smc_load_fw && smc_enabled)
++			adev->firmware.smu_load = true;
++		break;
++	default:
++		/* FIXME: not supported yet */
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int vi_common_sw_init(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int vi_common_sw_fini(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static int vi_common_hw_init(struct amdgpu_device *adev)
++{
++	/* move the golden regs per IP block */
++	vi_init_golden_registers(adev);
++	/* enable pcie gen2/3 link */
++	vi_pcie_gen3_enable(adev);
++	/* enable aspm */
++	vi_program_aspm(adev);
++	/* enable the doorbell aperture */
++	vi_enable_doorbell_aperture(adev, true);
++
++	return 0;
++}
++
++static int vi_common_hw_fini(struct amdgpu_device *adev)
++{
++	/* enable the doorbell aperture */
++	vi_enable_doorbell_aperture(adev, false);
++
++	return 0;
++}
++
++static int vi_common_suspend(struct amdgpu_device *adev)
++{
++	return vi_common_hw_fini(adev);
++}
++
++static int vi_common_resume(struct amdgpu_device *adev)
++{
++	return vi_common_hw_init(adev);
++}
++
++static bool vi_common_is_idle(struct amdgpu_device *adev)
++{
++	return true;
++}
++
++static int vi_common_wait_for_idle(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static void vi_common_print_status(struct amdgpu_device *adev)
++{
++
++}
++
++static int vi_common_soft_reset(struct amdgpu_device *adev)
++{
++	/* XXX hard reset?? */
++	return 0;
++}
++
++static int vi_common_set_clockgating_state(struct amdgpu_device *adev,
++					    enum amdgpu_clockgating_state state)
++{
++	return 0;
++}
++
++static int vi_common_set_powergating_state(struct amdgpu_device *adev,
++					    enum amdgpu_powergating_state state)
++{
++	return 0;
++}
++
++const struct amdgpu_ip_funcs vi_common_ip_funcs = {
++	.early_init = vi_common_early_init,
++	.late_init = NULL,
++	.sw_init = vi_common_sw_init,
++	.sw_fini = vi_common_sw_fini,
++	.hw_init = vi_common_hw_init,
++	.hw_fini = vi_common_hw_fini,
++	.suspend = vi_common_suspend,
++	.resume = vi_common_resume,
++	.is_idle = vi_common_is_idle,
++	.wait_for_idle = vi_common_wait_for_idle,
++	.soft_reset = vi_common_soft_reset,
++	.print_status = vi_common_print_status,
++	.set_clockgating_state = vi_common_set_clockgating_state,
++	.set_powergating_state = vi_common_set_powergating_state,
++};
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
+new file mode 100644
+index 0000000..d16a5f7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vi.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __VI_H__
++#define __VI_H__
++
++extern const struct amdgpu_ip_funcs vi_common_ip_funcs;
++
++void vi_srbm_select(struct amdgpu_device *adev,
++		    u32 me, u32 pipe, u32 queue, u32 vmid);
++int vi_set_ip_blocks(struct amdgpu_device *adev);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h
+new file mode 100644
+index 0000000..11cb1f7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h
+@@ -0,0 +1,36 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __VI_DPM_H__
++#define __VI_DPM_H__
++
++extern const struct amdgpu_ip_funcs cz_dpm_ip_funcs;
++int cz_smu_init(struct amdgpu_device *adev);
++int cz_smu_start(struct amdgpu_device *adev);
++int cz_smu_fini(struct amdgpu_device *adev);
++
++extern const struct amdgpu_ip_funcs tonga_dpm_ip_funcs;
++
++extern const struct amdgpu_ip_funcs iceland_dpm_ip_funcs;
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
+new file mode 100644
+index 0000000..385267c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vid.h
+@@ -0,0 +1,363 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef VI_H
++#define VI_H
++
++#define SDMA0_REGISTER_OFFSET                             0x0 /* not a register */
++#define SDMA1_REGISTER_OFFSET                             0x200 /* not a register */
++#define SDMA_MAX_INSTANCE 2
++
++/* crtc instance offsets */
++#define CRTC0_REGISTER_OFFSET                 (0x1b9c - 0x1b9c)
++#define CRTC1_REGISTER_OFFSET                 (0x1d9c - 0x1b9c)
++#define CRTC2_REGISTER_OFFSET                 (0x1f9c - 0x1b9c)
++#define CRTC3_REGISTER_OFFSET                 (0x419c - 0x1b9c)
++#define CRTC4_REGISTER_OFFSET                 (0x439c - 0x1b9c)
++#define CRTC5_REGISTER_OFFSET                 (0x459c - 0x1b9c)
++#define CRTC6_REGISTER_OFFSET                 (0x479c - 0x1b9c)
++
++/* dig instance offsets */
++#define DIG0_REGISTER_OFFSET                 (0x4a00 - 0x4a00)
++#define DIG1_REGISTER_OFFSET                 (0x4b00 - 0x4a00)
++#define DIG2_REGISTER_OFFSET                 (0x4c00 - 0x4a00)
++#define DIG3_REGISTER_OFFSET                 (0x4d00 - 0x4a00)
++#define DIG4_REGISTER_OFFSET                 (0x4e00 - 0x4a00)
++#define DIG5_REGISTER_OFFSET                 (0x4f00 - 0x4a00)
++#define DIG6_REGISTER_OFFSET                 (0x5400 - 0x4a00)
++#define DIG7_REGISTER_OFFSET                 (0x5600 - 0x4a00)
++#define DIG8_REGISTER_OFFSET                 (0x5700 - 0x4a00)
++
++/* audio endpt instance offsets */
++#define AUD0_REGISTER_OFFSET                 (0x17a8 - 0x17a8)
++#define AUD1_REGISTER_OFFSET                 (0x17ac - 0x17a8)
++#define AUD2_REGISTER_OFFSET                 (0x17b0 - 0x17a8)
++#define AUD3_REGISTER_OFFSET                 (0x17b4 - 0x17a8)
++#define AUD4_REGISTER_OFFSET                 (0x17b8 - 0x17a8)
++#define AUD5_REGISTER_OFFSET                 (0x17bc - 0x17a8)
++#define AUD6_REGISTER_OFFSET                 (0x17c4 - 0x17a8)
++
++/* hpd instance offsets */
++#define HPD0_REGISTER_OFFSET                 (0x1898 - 0x1898)
++#define HPD1_REGISTER_OFFSET                 (0x18a0 - 0x1898)
++#define HPD2_REGISTER_OFFSET                 (0x18a8 - 0x1898)
++#define HPD3_REGISTER_OFFSET                 (0x18b0 - 0x1898)
++#define HPD4_REGISTER_OFFSET                 (0x18b8 - 0x1898)
++#define HPD5_REGISTER_OFFSET                 (0x18c0 - 0x1898)
++
++#define AMDGPU_NUM_OF_VMIDS			8
++
++#define RB_BITMAP_WIDTH_PER_SH     2
++
++#define MC_SEQ_MISC0__GDDR5__SHIFT	0x1c
++#define MC_SEQ_MISC0__GDDR5_MASK	0xf0000000
++#define MC_SEQ_MISC0__GDDR5_VALUE	5
++
++/*
++ * PM4
++ */
++#define	PACKET_TYPE0	0
++#define	PACKET_TYPE1	1
++#define	PACKET_TYPE2	2
++#define	PACKET_TYPE3	3
++
++#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
++#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
++#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
++#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
++#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
++			 ((reg) & 0xFFFF) |			\
++			 ((n) & 0x3FFF) << 16)
++#define CP_PACKET2			0x80000000
++#define		PACKET2_PAD_SHIFT		0
++#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
++
++#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
++
++#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
++			 (((op) & 0xFF) << 8) |				\
++			 ((n) & 0x3FFF) << 16)
++
++#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
++
++/* Packet 3 types */
++#define	PACKET3_NOP					0x10
++#define	PACKET3_SET_BASE				0x11
++#define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
++#define			CE_PARTITION_BASE		3
++#define	PACKET3_CLEAR_STATE				0x12
++#define	PACKET3_INDEX_BUFFER_SIZE			0x13
++#define	PACKET3_DISPATCH_DIRECT				0x15
++#define	PACKET3_DISPATCH_INDIRECT			0x16
++#define	PACKET3_ATOMIC_GDS				0x1D
++#define	PACKET3_ATOMIC_MEM				0x1E
++#define	PACKET3_OCCLUSION_QUERY				0x1F
++#define	PACKET3_SET_PREDICATION				0x20
++#define	PACKET3_REG_RMW					0x21
++#define	PACKET3_COND_EXEC				0x22
++#define	PACKET3_PRED_EXEC				0x23
++#define	PACKET3_DRAW_INDIRECT				0x24
++#define	PACKET3_DRAW_INDEX_INDIRECT			0x25
++#define	PACKET3_INDEX_BASE				0x26
++#define	PACKET3_DRAW_INDEX_2				0x27
++#define	PACKET3_CONTEXT_CONTROL				0x28
++#define	PACKET3_INDEX_TYPE				0x2A
++#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
++#define	PACKET3_DRAW_INDEX_AUTO				0x2D
++#define	PACKET3_NUM_INSTANCES				0x2F
++#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
++#define	PACKET3_INDIRECT_BUFFER_CONST			0x33
++#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
++#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
++#define	PACKET3_DRAW_PREAMBLE				0x36
++#define	PACKET3_WRITE_DATA				0x37
++#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
++		/* 0 - register
++		 * 1 - memory (sync - via GRBM)
++		 * 2 - gl2
++		 * 3 - gds
++		 * 4 - reserved
++		 * 5 - memory (async - direct)
++		 */
++#define		WR_ONE_ADDR                             (1 << 16)
++#define		WR_CONFIRM                              (1 << 20)
++#define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
++		/* 0 - LRU
++		 * 1 - Stream
++		 */
++#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
++		/* 0 - me
++		 * 1 - pfp
++		 * 2 - ce
++		 */
++#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
++#define	PACKET3_MEM_SEMAPHORE				0x39
++#              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
++#              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
++#              define PACKET3_SEM_CLIENT_CODE	    ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
++#              define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
++#              define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
++#define	PACKET3_WAIT_REG_MEM				0x3C
++#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
++		/* 0 - always
++		 * 1 - <
++		 * 2 - <=
++		 * 3 - ==
++		 * 4 - !=
++		 * 5 - >=
++		 * 6 - >
++		 */
++#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
++		/* 0 - reg
++		 * 1 - mem
++		 */
++#define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
++		/* 0 - wait_reg_mem
++		 * 1 - wr_wait_wr_reg
++		 */
++#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
++		/* 0 - me
++		 * 1 - pfp
++		 */
++#define	PACKET3_INDIRECT_BUFFER				0x3F
++#define		INDIRECT_BUFFER_TCL2_VOLATILE           (1 << 22)
++#define		INDIRECT_BUFFER_VALID                   (1 << 23)
++#define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#define	PACKET3_COPY_DATA				0x40
++#define	PACKET3_PFP_SYNC_ME				0x42
++#define	PACKET3_SURFACE_SYNC				0x43
++#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
++#              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
++#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
++#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
++#              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
++#              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
++#              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
++#              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
++#              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
++#              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
++#              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
++#              define PACKET3_TCL1_VOL_ACTION_ENA  (1 << 15)
++#              define PACKET3_TC_VOL_ACTION_ENA    (1 << 16) /* L2 */
++#              define PACKET3_TC_WB_ACTION_ENA     (1 << 18) /* L2 */
++#              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
++#              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
++#              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
++#              define PACKET3_TC_ACTION_ENA        (1 << 23) /* L2 */
++#              define PACKET3_CB_ACTION_ENA        (1 << 25)
++#              define PACKET3_DB_ACTION_ENA        (1 << 26)
++#              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
++#              define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
++#              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
++#define	PACKET3_COND_WRITE				0x45
++#define	PACKET3_EVENT_WRITE				0x46
++#define		EVENT_TYPE(x)                           ((x) << 0)
++#define		EVENT_INDEX(x)                          ((x) << 8)
++		/* 0 - any non-TS event
++		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
++		 * 2 - SAMPLE_PIPELINESTAT
++		 * 3 - SAMPLE_STREAMOUTSTAT*
++		 * 4 - *S_PARTIAL_FLUSH
++		 * 5 - EOP events
++		 * 6 - EOS events
++		 */
++#define	PACKET3_EVENT_WRITE_EOP				0x47
++#define		EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
++#define		EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
++#define		EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
++#define		EOP_TCL1_ACTION_EN                      (1 << 16)
++#define		EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
++#define		EOP_TCL2_VOLATILE                       (1 << 24)
++#define		EOP_CACHE_POLICY(x)                     ((x) << 25)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#define		DATA_SEL(x)                             ((x) << 29)
++		/* 0 - discard
++		 * 1 - send low 32bit data
++		 * 2 - send 64bit data
++		 * 3 - send 64bit GPU counter value
++		 * 4 - send 64bit sys counter value
++		 */
++#define		INT_SEL(x)                              ((x) << 24)
++		/* 0 - none
++		 * 1 - interrupt only (DATA_SEL = 0)
++		 * 2 - interrupt when data write is confirmed
++		 */
++#define		DST_SEL(x)                              ((x) << 16)
++		/* 0 - MC
++		 * 1 - TC/L2
++		 */
++#define	PACKET3_EVENT_WRITE_EOS				0x48
++#define	PACKET3_RELEASE_MEM				0x49
++#define	PACKET3_PREAMBLE_CNTL				0x4A
++#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
++#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
++#define	PACKET3_DMA_DATA				0x50
++/* 1. header
++ * 2. CONTROL
++ * 3. SRC_ADDR_LO or DATA [31:0]
++ * 4. SRC_ADDR_HI [31:0]
++ * 5. DST_ADDR_LO [31:0]
++ * 6. DST_ADDR_HI [7:0]
++ * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
++ */
++/* CONTROL */
++#              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
++		/* 0 - ME
++		 * 1 - PFP
++		 */
++#              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#              define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
++#              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
++		/* 0 - DST_ADDR using DAS
++		 * 1 - GDS
++		 * 3 - DST_ADDR using L2
++		 */
++#              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
++		/* 0 - LRU
++		 * 1 - Stream
++		 * 2 - Bypass
++		 */
++#              define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
++#              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
++		/* 0 - SRC_ADDR using SAS
++		 * 1 - GDS
++		 * 2 - DATA
++		 * 3 - SRC_ADDR using L2
++		 */
++#              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
++/* COMMAND */
++#              define PACKET3_DMA_DATA_DIS_WC      (1 << 21)
++#              define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
++		/* 0 - none
++		 * 1 - 8 in 16
++		 * 2 - 8 in 32
++		 * 3 - 8 in 64
++		 */
++#              define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
++		/* 0 - none
++		 * 1 - 8 in 16
++		 * 2 - 8 in 32
++		 * 3 - 8 in 64
++		 */
++#              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
++		/* 0 - memory
++		 * 1 - register
++		 */
++#              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
++		/* 0 - memory
++		 * 1 - register
++		 */
++#              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
++#              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
++#              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
++#define	PACKET3_AQUIRE_MEM				0x58
++#define	PACKET3_REWIND					0x59
++#define	PACKET3_LOAD_UCONFIG_REG			0x5E
++#define	PACKET3_LOAD_SH_REG				0x5F
++#define	PACKET3_LOAD_CONFIG_REG				0x60
++#define	PACKET3_LOAD_CONTEXT_REG			0x61
++#define	PACKET3_SET_CONFIG_REG				0x68
++#define		PACKET3_SET_CONFIG_REG_START			0x00002000
++#define		PACKET3_SET_CONFIG_REG_END			0x00002c00
++#define	PACKET3_SET_CONTEXT_REG				0x69
++#define		PACKET3_SET_CONTEXT_REG_START			0x0000a000
++#define		PACKET3_SET_CONTEXT_REG_END			0x0000a400
++#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
++#define	PACKET3_SET_SH_REG				0x76
++#define		PACKET3_SET_SH_REG_START			0x00002c00
++#define		PACKET3_SET_SH_REG_END				0x00003000
++#define	PACKET3_SET_SH_REG_OFFSET			0x77
++#define	PACKET3_SET_QUEUE_REG				0x78
++#define	PACKET3_SET_UCONFIG_REG				0x79
++#define		PACKET3_SET_UCONFIG_REG_START			0x0000c000
++#define		PACKET3_SET_UCONFIG_REG_END			0x0000c400
++#define	PACKET3_SCRATCH_RAM_WRITE			0x7D
++#define	PACKET3_SCRATCH_RAM_READ			0x7E
++#define	PACKET3_LOAD_CONST_RAM				0x80
++#define	PACKET3_WRITE_CONST_RAM				0x81
++#define	PACKET3_DUMP_CONST_RAM				0x83
++#define	PACKET3_INCREMENT_CE_COUNTER			0x84
++#define	PACKET3_INCREMENT_DE_COUNTER			0x85
++#define	PACKET3_WAIT_ON_CE_COUNTER			0x86
++#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
++#define	PACKET3_SWITCH_BUFFER				0x8B
++
++#define VCE_CMD_NO_OP		0x00000000
++#define VCE_CMD_END		0x00000001
++#define VCE_CMD_IB		0x00000002
++#define VCE_CMD_FENCE		0x00000003
++#define VCE_CMD_TRAP		0x00000004
++#define VCE_CMD_IB_AUTO 	0x00000005
++#define VCE_CMD_SEMAPHORE	0x00000006
++
++#endif
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0040-yocto-amd-drm-amdgpu-add-BIF-5-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0040-yocto-amd-drm-amdgpu-add-BIF-5-0-register-headers.patch
new file mode 100644
index 00000000..c6ea58a2
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0040-yocto-amd-drm-amdgpu-add-BIF-5-0-register-headers.patch
@@ -0,0 +1,109 @@
+From 381ac2a10e04a82ac1ab015e034623aa95e8c996 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 17:36:52 -0400
+Subject: drm/amdgpu: add CIK pci ids
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index d1af448..632a8d1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -138,6 +138,89 @@ MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disab
+ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
+ 
+ static struct pci_device_id pciidlist[] = {
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	/* Kaveri */
++	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU},
++	/* Bonaire */
++	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY},
++	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY},
++	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY},
++	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY},
++	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
++	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
++	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
++	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
++	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
++	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
++	/* Hawaii */
++	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
++	/* Kabini */
++	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU},
++	/* mullins */
++	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
++#endif
+ 
+ 	{0, 0, 0}
+ };
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0041-yocto-amd-drm-amdgpu-add-BIF-4-1-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0041-yocto-amd-drm-amdgpu-add-BIF-4-1-register-headers.patch
new file mode 100644
index 00000000..18299165
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0041-yocto-amd-drm-amdgpu-add-BIF-4-1-register-headers.patch
@@ -0,0 +1,42 @@
+From 1f38cda75103fb424c899bad7c30af2ecf530f75 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Apr 2015 17:37:54 -0400
+Subject: drm/amdgpu: add VI pci ids
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com>
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 632a8d1..dfd4261 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -221,6 +221,26 @@ static struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
+ 	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU},
+ #endif
++	/* topaz */
++	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
++	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
++	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
++	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
++	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
++	/* tonga */
++	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
++	/* carrizo */
++	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU},
++	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU},
++	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU},
++	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU},
++	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU},
+ 
+ 	{0, 0, 0}
+ };
+-- 
+cgit v0.10.2
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0042-yocto-amd-drm-amdgpu-fix-amdgpu.dpm-0-kernel-bug-482.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0042-yocto-amd-drm-amdgpu-fix-amdgpu.dpm-0-kernel-bug-482.patch
new file mode 100644
index 00000000..cff8364e
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0042-yocto-amd-drm-amdgpu-fix-amdgpu.dpm-0-kernel-bug-482.patch
@@ -0,0 +1,58 @@
+From 5ecb7c958d3c90b6b00536484526ecc538740914 Mon Sep 17 00:00:00 2001
+From: Sonny Jiang <sonny.jiang@amd.com>
+Date: Thu, 30 Apr 2015 17:12:14 -0400
+Subject: [PATCH] drm/amdgpu fix amdgpu.dpm=0 kernel bug#482
+
+Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
+Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 19 +++++++++++++++----
+ 1 file changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+index b5c8485..87e2a4f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+@@ -1206,10 +1206,7 @@ static int cz_dpm_enable(struct amdgpu_device *adev)
+ 
+ static int cz_dpm_hw_init(struct amdgpu_device *adev)
+ {
+-	int ret;
+-
+-	if (!amdgpu_dpm)
+-		return 0;
++	int ret = 0;
+ 
+ 	mutex_lock(&adev->pm.mutex);
+ 
+@@ -1229,6 +1226,13 @@ static int cz_dpm_hw_init(struct amdgpu_device *adev)
+ 		return ret;
+ 	}
+ 
++	if (!amdgpu_dpm)
++	{
++		adev->pm.dpm_enabled = false;
++		mutex_unlock(&adev->pm.mutex);
++		return ret;
++	}
++
+ 	/* cz dpm setup asic */
+ 	cz_dpm_setup_asic(adev);
+ 
+@@ -1330,6 +1334,13 @@ static int cz_dpm_resume(struct amdgpu_device *adev)
+ 		return ret;
+ 	}
+ 
++	if (!amdgpu_dpm)
++	{
++		adev->pm.dpm_enabled = false;
++		mutex_unlock(&adev->pm.mutex);
++		return ret;
++	}
++
+ 	/* cz dpm setup asic */
+ 	cz_dpm_setup_asic(adev);
+ 
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0043-yocto-amd-drm-amdgpu-set-the-gfx-config-properly-for-all-CZ-va.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0043-yocto-amd-drm-amdgpu-set-the-gfx-config-properly-for-all-CZ-va.patch
new file mode 100644
index 00000000..003d731c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0043-yocto-amd-drm-amdgpu-set-the-gfx-config-properly-for-all-CZ-va.patch
@@ -0,0 +1,70 @@
+From dbcbc331d82ded9315603197da3125cdfeabcb3d Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Thu, 11 Jun 2015 13:15:42 +0530
+Subject: [PATCH 1/1] drm/amdgpu: set the gfx config properly for all CZ
+ variants
+
+Need to adjust the number of CUs and RBs.
+
+v2: get proper values
+
+Reviewed-by: Samuel Li <samuel.li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 38 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 36 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index a8397dd..8fc2379 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1929,9 +1929,43 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
+ 	case CHIP_CARRIZO:
+ 		adev->gfx.config.max_shader_engines = 1;
+ 		adev->gfx.config.max_tile_pipes = 2;
+-		adev->gfx.config.max_cu_per_sh = 8;
+ 		adev->gfx.config.max_sh_per_se = 1;
+-		adev->gfx.config.max_backends_per_se = 2;
++
++		switch (adev->pdev->revision) {
++		case 0xc4:
++		case 0x84:
++		case 0xc8:
++		case 0xcc:
++			/* B10 */
++			adev->gfx.config.max_cu_per_sh = 8;
++			adev->gfx.config.max_backends_per_se = 2;
++			break;
++		case 0xc5:
++		case 0x81:
++		case 0x85:
++		case 0xc9:
++		case 0xcd:
++			/* B8 */
++			adev->gfx.config.max_cu_per_sh = 6;
++			adev->gfx.config.max_backends_per_se = 2;
++			break;
++		case 0xc6:
++		case 0xca:
++		case 0xce:
++			/* B6 */
++			adev->gfx.config.max_cu_per_sh = 6;
++			adev->gfx.config.max_backends_per_se = 2;
++			break;
++		case 0xc7:
++		case 0x87:
++		case 0xcb:
++		default:
++			/* B4 */
++			adev->gfx.config.max_cu_per_sh = 4;
++			adev->gfx.config.max_backends_per_se = 1;
++			break;
++		}
++
+ 		adev->gfx.config.max_texture_channel_caches = 2;
+ 		adev->gfx.config.max_gprs = 256;
+ 		adev->gfx.config.max_gs_threads = 32;
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0044-yocto-amd-sdhci-add-support-for-CZ-SD-host-controller.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0044-yocto-amd-sdhci-add-support-for-CZ-SD-host-controller.patch
new file mode 100644
index 00000000..fb3f37c0
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/0044-yocto-amd-sdhci-add-support-for-CZ-SD-host-controller.patch
@@ -0,0 +1,136 @@
+From 0ada1e55a85758964e24b07b1b80385a8bcbdc3a Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Tue, 16 Jun 2015 13:06:30 +0530
+Subject: [PATCH 1/1] sdhci: add support for CZ SD host controller
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ drivers/mmc/host/sdhci-pci.c | 54 ++++++++++++++++++++++++++++++++++++++++++++
+ drivers/mmc/host/sdhci.c     | 11 ++++++---
+ include/linux/mmc/sdhci.h    |  2 ++
+ include/linux/pci_ids.h      |  1 +
+ 4 files changed, 65 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
+index 19bfa0a..8eb70a9 100644
+--- a/drivers/mmc/host/sdhci-pci.c
++++ b/drivers/mmc/host/sdhci-pci.c
+@@ -614,6 +614,50 @@ static const struct sdhci_pci_fixes sdhci_via = {
+ 	.probe		= via_probe,
+ };
+ 
++/* AMD chipset generation */
++enum amd_chipset_gen {
++	AMD_CHIPSET_BEFORE_ML,
++	AMD_CHIPSET_CZ,
++	AMD_CHIPSET_NL,
++	AMD_CHIPSET_UNKNOWN,
++};
++
++static int amd_probe(struct sdhci_pci_chip *chip)
++{
++	struct pci_dev	*smbus_dev;
++	enum amd_chipset_gen gen;
++
++	smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
++			PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
++
++	if (smbus_dev) {
++		gen = AMD_CHIPSET_BEFORE_ML;
++	} else {
++		smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
++				PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
++
++		if (smbus_dev) {
++			if (smbus_dev->revision < 0x51)
++				gen = AMD_CHIPSET_CZ;
++			else
++				gen = AMD_CHIPSET_NL;
++		} else {
++			gen = AMD_CHIPSET_UNKNOWN;
++		}
++	}
++
++	if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
++		chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
++		chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
++	}
++
++	return 0;
++}
++
++static const struct sdhci_pci_fixes sdhci_amd = {
++	.probe		= amd_probe,
++};
++
+ static const struct pci_device_id pci_ids[] = {
+ 	{
+ 		.vendor		= PCI_VENDOR_ID_RICOH,
+@@ -983,6 +1027,16 @@ static const struct pci_device_id pci_ids[] = {
+ 		.driver_data	= (kernel_ulong_t)&sdhci_o2,
+ 	},
+ 
++	{
++		.vendor		= PCI_VENDOR_ID_AMD,
++		.device		= PCI_ANY_ID,
++		.class		= PCI_CLASS_SYSTEM_SDHCI << 8,
++		.class_mask	= 0xFFFF00,
++		.subvendor	= PCI_ANY_ID,
++		.subdevice	= PCI_ANY_ID,
++		.driver_data	= (kernel_ulong_t)&sdhci_amd,
++	},
++
+ 	{	/* Generic SD host controller */
+ 		PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
+ 	},
+diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
+index 135018e..ee72095 100644
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -899,10 +899,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
+ 	struct mmc_data *data = cmd->data;
+ 
+ 	if (data == NULL) {
+-		/* clear Auto CMD settings for no data CMDs */
+-		mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
+-		sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
++		if (host->quirks2 &
++			SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
++			sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
++		} else {
++			/* clear Auto CMD settings for no data CMDs */
++			mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
++			sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
+ 				SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
++		}
+ 		return;
+ 	}
+ 
+diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
+index 362927c4..4d828e1 100644
+--- a/include/linux/mmc/sdhci.h
++++ b/include/linux/mmc/sdhci.h
+@@ -100,6 +100,8 @@ struct sdhci_host {
+ #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL		(1<<5)
+ /* Controller does not support HS200 */
+ #define SDHCI_QUIRK2_BROKEN_HS200			(1<<6)
++/* need clear transfer mode register before send cmd */
++#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
+ 
+ 	int irq;		/* Device IRQ */
+ 	void __iomem *ioaddr;	/* Mapped address */
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 057c1d8..ccf55b3 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -572,6 +572,7 @@
+ #define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE	0x7800
+ #define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS		0x780b
+ #define PCI_DEVICE_ID_AMD_HUDSON2_IDE		0x780c
++#define PCI_DEVICE_ID_AMD_KERNCZ_SMBUS	0x790b
+ 
+ #define PCI_VENDOR_ID_TRIDENT		0x1023
+ #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-preempt-rt.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-preempt-rt.scc
new file mode 100644
index 00000000..6973e809
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-preempt-rt.scc
@@ -0,0 +1,14 @@
+define KMACHINE amdfalconx86
+define KTYPE preempt-rt
+define KARCH x86_64
+
+include ktypes/preempt-rt/preempt-rt.scc
+branch amdfalconx86
+
+include amdfalconx86.scc
+
+# default policy for preempt-rt kernels
+include cfg/usb-mass-storage.scc
+include cfg/boot-live.scc
+include features/latencytop/latencytop.scc
+include features/profiling/profiling.scc
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard.scc
new file mode 100644
index 00000000..4af7fc4f
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard.scc
@@ -0,0 +1,14 @@
+define KMACHINE amdfalconx86
+define KTYPE standard
+define KARCH x86_64
+
+include bsp/common-pc-64/common-pc-64-standard.scc
+branch amdfalconx86
+
+include amdfalconx86.scc
+
+# default policy for standard kernels
+include cfg/usb-mass-storage.scc
+include cfg/boot-live.scc
+include features/latencytop/latencytop.scc
+include features/profiling/profiling.scc
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-tiny.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-tiny.scc
new file mode 100644
index 00000000..7c6f6a51
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-tiny.scc
@@ -0,0 +1,8 @@
+define KMACHINE amdfalconx86
+define KTYPE tiny
+define KARCH x86_64
+
+include ktypes/tiny/tiny.scc
+branch amdfalconx86
+
+include amdfalconx86.scc
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg
new file mode 100644
index 00000000..cd334f51
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg
@@ -0,0 +1,231 @@
+CONFIG_STAGING=y
+CONFIG_AMD_IMC=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC=m
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_PIIX4=m
+CONFIG_IGB=m
+CONFIG_SENSORS_K10TEMP=m
+CONFIG_X86_MCE=y
+CONFIG_X86_MCE_AMD=y
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_PCSP=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_INPUT_JACK=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_HDA_CODEC_CIRRUS=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_CA0110=y
+CONFIG_SND_HDA_CODEC_CA0132=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_CS=m
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_RUNTIME_UARTS=32
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_X86_AMD_PLATFORM_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_GART_IOMMU=y
+CONFIG_CALGARY_IOMMU=y
+CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
+CONFIG_NR_CPUS=24
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_MCE_INJECT=m
+CONFIG_MICROCODE=m
+CONFIG_X86_MSR=m
+CONFIG_X86_CPUID=m
+CONFIG_NUMA=y
+CONFIG_AMD_NUMA=y
+CONFIG_X86_64_ACPI_NUMA=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
+CONFIG_NODES_SHIFT=6
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_HAVE_BOOTMEM_INFO_NODE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTPLUG_SPARSE=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_NEED_BOUNCE_POOL=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_COMPAT_VDSO=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_SBS=m
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=m
+CONFIG_ACPI_APEI_ERST_DEBUG=m
+CONFIG_SFI=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_X86_PCC_CPUFREQ=m
+CONFIG_X86_POWERNOW_K8=y
+CONFIG_X86_SPEEDSTEP_CENTRINO=y
+CONFIG_X86_P4_CLOCKMOD=m
+CONFIG_X86_SPEEDSTEP_LIB=m
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
+CONFIG_HOTPLUG_PCI_SHPC=m
+CONFIG_X86_SYSFB=y
+CONFIG_NET_SCH_FQ=m
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_HW_RANDOM_TPM=m
+CONFIG_NVRAM=m
+CONFIG_HANGCHECK_TIMER=m
+CONFIG_TCG_TPM=y
+CONFIG_I2C_ALGOBIT=m
+CONFIG_GPIO_GENERIC=m
+CONFIG_GPIO_GENERIC_PLATFORM=m
+CONFIG_SENSORS_K8TEMP=m
+CONFIG_SENSORS_FAM15H_POWER=m
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_AGP_AMD64=y
+CONFIG_VGA_SWITCHEROO=y
+CONFIG_DRM=m
+CONFIG_DRM_KMS_HELPER=m
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_TTM=m
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_VGASTATE=m
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD_PCI=m
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_MMC_SDHCI_PLTFM=m
+CONFIG_MMC_SPI=m
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_DECODE_MCE=y
+CONFIG_EDAC_MCE_INJ=m
+CONFIG_EDAC_MM_EDAC=m
+CONFIG_EDAC_AMD64=m
+CONFIG_AUXDISPLAY=y
+CONFIG_IOMMU_API=y
+CONFIG_AMD_IOMMU=y
+CONFIG_AMD_IOMMU_STATS=y
+CONFIG_AMD_IOMMU_V2=m
+CONFIG_DMAR_TABLE=y
+CONFIG_IRQ_REMAP=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_MEMORY=y
+CONFIG_EDD=y
+CONFIG_EDD_OFF=y
+CONFIG_DMI_SYSFS=m
+CONFIG_EFI_VARS=y
+CONFIG_EFI_VARS_PSTORE=y
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_UEFI_CPER=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+CONFIG_PROC_VMCORE=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_PSTORE=y
+CONFIG_SECURITYFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_FB_SIMPLE=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_R8169=n
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc
new file mode 100644
index 00000000..47bb35f0
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc
@@ -0,0 +1,51 @@
+patch 0001-yocto-amd-staging-add-support-to-enable-and-disable-IMC-to-fetch-BIOS-code.patch
+patch 0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IMC-from-fetching-BIOS-code.patch
+patch 0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch
+patch 0004-yocto-amd-temperature-monitoring-support-for-F15h-M60h-processor.patch
+patch 0005-yocto-amd-i2c-driver_support_ACPI2Platform-1.0.patch
+patch 0006-yocto-amd-tty-driver_enable_UART_support-1.0.patch
+patch 0007-yocto-amd-backport-kernel-dependencies-for-amdgpu-driver.patch
+patch 0001-yocto-amd-drm-amdgpu-add-VI-pci-idsamdgpu.patch
+patch 0002-yocto-amd-drm-amdgpu-add-CIK-pci-ids.patch
+patch 0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch
+patch 0004-yocto-amd-drm-amdgpu-Add-support-for-CIK-parts.patch
+patch 0005-yocto-amd-drm-amdgpu-Do-not-directly-dereference-pointers-to-BIOS-area.patch
+patch 0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch
+patch 0007-yocto-amd-drm-amdgpu-add-core-driver.patch
+patch 0008-yocto-amd-drm-amdgpu-add-amdgpu-h.patch
+patch 0009-yocto-amd-drm-amdgpu-add-amdgpu_family-h.patch
+patch 0010-yocto-amd-drm-amdgpu-add-ppsmc-hA.patch
+patch 0011-yocto-amd-drm-amdgpu-add-clearstate_defs-h.patch
+patch 0012-yocto-amd-drm-amdgpu-add-atombios-headers.patch
+patch 0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch
+patch 0014-yocto-amd-drm-amdgpu-add-VCE-3-0-register-headers.patch
+patch 0015-yocto-amd-drm-amdgpu-add-VCE-2-0-register-headers.patch
+patch 0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch
+patch 0017-yocto-amd-drm-amdgpu-add-UVD-5-0-register-headers.patch
+patch 0018-yocto-amd-drm-amdgpu-add-UVD-4-2-register-headers.patch
+patch 0019-yocto-amd-drm-amdgpu-add-SMU-8-0-register-headers.patch
+patch 0020-yocto-amd-drm-amdgpu-add-SMU-7-1-2-register-headers.patch
+patch 0021-yocto-amd-drm-amdgpu-add-SMU-7-1-1-register-headers.patch
+patch 0022-yocto-amd-drm-amdgpu-add-SMU-7-1-0-register-headers.patch
+patch 0023-yocto-amd-drm-amdgpu-add-SMU-7-0-1-register-headers.patch
+patch 0024-yocto-amd-drm-amdgpu-add-SMU-7-0-0-register-headers.patch
+patch 0025-yocto-amd-drm-amdgpu-add-OSS-3-0-1-register-headers.patch
+patch 0026-yocto-amd-drm-amdgpu-add-OSS-3-0-register-headers.patch
+patch 0027-yocto-amd-drm-amdgpu-add-OSS-2-4-register-headers.patch
+patch 0028-yocto-amd-drm-amdgpu-add-OSS-2-0-register-headers.patch
+patch 0029-yocto-amd-drm-amdgpu-add-GMC-8-2-register-headers.patch
+patch 0030-yocto-amd-drm-amdgpu-add-GMC-8-1-register-headers.patch
+patch 0031-yocto-amd-drm-amdgpu-add-GMC-7-1-register-headers.patch
+patch 0032-yocto-amd-drm-amdgpu-add-GMC-7-0-register-headers.patch
+patch 0033-yocto-amd-drm-amdgpu-add-GCA-8-0-register-headers.patch
+patch 0034-yocto-amd-drm-amdgpu-add-GCA-7-2-register-headers.patch
+patch 0035-yocto-amd-drm-amdgpu-add-GCA-7-0-register-headers.patch
+patch 0036-yocto-amd-drm-amdgpu-add-DCE-11-0-register-headers.patch
+patch 0037-yocto-amd-drm-amdgpu-add-DCE-10-0-register-headers.patch
+patch 0038-yocto-amd-drm-amdgpu-add-DCE-8-0-register-headers.patch
+patch 0039-yocto-amd-drm-amdgpu-add-BIF-5-1-register-headers.patch
+patch 0040-yocto-amd-drm-amdgpu-add-BIF-5-0-register-headers.patch
+patch 0041-yocto-amd-drm-amdgpu-add-BIF-4-1-register-headers.patch
+patch 0042-yocto-amd-drm-amdgpu-fix-amdgpu.dpm-0-kernel-bug-482.patch
+patch 0043-yocto-amd-drm-amdgpu-set-the-gfx-config-properly-for-all-CZ-va.patch
+patch 0044-yocto-amd-sdhci-add-support-for-CZ-SD-host-controller.patch
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg
new file mode 100644
index 00000000..3d62e2ea
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg
@@ -0,0 +1,70 @@
+CONFIG_PRINTK=y
+
+# Basic hardware support for the box - network, USB, PCI, sound
+CONFIG_NETDEVICES=y
+CONFIG_ATA=y
+CONFIG_ATA_GENERIC=y
+CONFIG_ATA_SFF=y
+CONFIG_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_R8169=y
+CONFIG_PATA_SCH=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_NET=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_HDA_INTEL=m
+
+# Make sure these are on, otherwise the bootup won't be fun
+CONFIG_EXT3_FS=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_MODULES=y
+CONFIG_SHMEM=y
+CONFIG_TMPFS=y
+CONFIG_PACKET=y
+
+CONFIG_I2C=y
+CONFIG_AGP=y
+CONFIG_PM=y
+CONFIG_ACPI=y
+CONFIG_INPUT=y
+
+# Needed for booting (and using) USB memory sticks
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+
+CONFIG_RD_GZIP=y
+
+# FB Console and Logo Support
+CONFIG_DRM_I915=n
+CONFIG_FB_VESA=y
+CONFIG_FB_EFI=y
+CONFIG_LOGO=y
+
+# Filesystems
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V4=y
+CONFIG_QFMT_V2
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QUOTA_TREE=m
+CONFIG_QUOTACTL=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.scc
new file mode 100644
index 00000000..6ba2f222
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.scc
@@ -0,0 +1,9 @@
+kconf hardware amdfalconx86.cfg
+
+include features/serial/8250.scc
+
+include cfg/usb-mass-storage.scc
+include features/power/intel.scc
+
+kconf hardware amdfalconx86-user-config.cfg
+include amdfalconx86-user-patches.scc
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/bluetooth.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/bluetooth.cfg
new file mode 100644
index 00000000..581830f0
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/bluetooth.cfg
@@ -0,0 +1,13 @@
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_ATH3K=m
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/disable-kgdb.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/disable-kgdb.cfg
new file mode 100644
index 00000000..d07c288b
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/disable-kgdb.cfg
@@ -0,0 +1 @@
+CONFIG_KGDB=n
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/usb-serial.cfg b/meta-amdfalconx86/recipes-kernel/linux/files/usb-serial.cfg
new file mode 100644
index 00000000..11402439
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/files/usb-serial.cfg
@@ -0,0 +1 @@
+CONFIG_USB_SERIAL_MOS7840=y
diff --git a/meta-amdfalconx86/recipes-kernel/linux/linux-yocto_3.14.bbappend b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto_3.14.bbappend
new file mode 100644
index 00000000..e07ad776
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/linux/linux-yocto_3.14.bbappend
@@ -0,0 +1,22 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+PR := "${INC_PR}.10"
+
+KBRANCH_amdfalconx86 ?= "standard/common-pc-64/base"
+SRCREV_machine_amdfalconx86 ?= "c100e8665052051487a17169748c457829d3f88c"
+SRCREV_meta_amdfalconx86 ?= "fb6271a942b57bdc40c6e49f0203be153699f81c"
+
+LINUX_VERSION_amdfalconx86 = "3.14.24"
+
+COMPATIBLE_MACHINE_amdfalconx86 = "amdfalconx86"
+
+KERNEL_FEATURES_append_amdfalconx86 += " cfg/smp.scc cfg/sound.scc"
+
+SRC_URI_append_amdfalconx86 += "file://amdfalconx86-standard.scc \
+				file://amdfalconx86-user-config.cfg \
+				file://amdfalconx86-user-features.scc \
+				file://amdfalconx86-user-patches.scc \
+				${@bb.utils.contains("DISTRO_FEATURES", "bluetooth", "file://bluetooth.cfg", "", d)} \
+				${@bb.utils.contains("DISTRO", "mel", "", "file://disable-kgdb.cfg", d)} \
+				file://usb-serial.cfg \
+			       "
diff --git a/meta-amdfalconx86/recipes-kernel/lttng/lttng-modules_2.5.0.bbappend b/meta-amdfalconx86/recipes-kernel/lttng/lttng-modules_2.5.0.bbappend
new file mode 100644
index 00000000..106d24b8
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/lttng/lttng-modules_2.5.0.bbappend
@@ -0,0 +1,5 @@
+# Not yet needed here.  The right fix may be to specify which platforms
+# explicitly get this patch but I need to do more due diligence first.
+SRC_URI_remove_amdfalconx86 = " \
+     file://Update-compaction-instrumentation-to-3.12-kernel.patch \
+"
diff --git a/meta-amdfalconx86/recipes-kernel/r8168/files/0001-r8168-adjust-Makefiles-for-Yocto-environment.patch b/meta-amdfalconx86/recipes-kernel/r8168/files/0001-r8168-adjust-Makefiles-for-Yocto-environment.patch
new file mode 100644
index 00000000..395257e5
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/r8168/files/0001-r8168-adjust-Makefiles-for-Yocto-environment.patch
@@ -0,0 +1,145 @@
+From 156a79c8aa451e3cf121d81ed3edae8054bc38fd Mon Sep 17 00:00:00 2001
+From: Awais Belal <awais_belal@mentor.com>
+Date: Mon, 8 Jun 2015 18:21:24 +0500
+Subject: [PATCH] r8168: adjust Makefiles for Yocto environment
+
+Signed-off-by: Awais Belal <awais_belal@mentor.com>
+---
+ Makefile     | 26 ++++----------------
+ src/Makefile | 77 +++++++++++++++++++++++++-----------------------------------
+ 2 files changed, 36 insertions(+), 67 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index a41f96e..e955097 100755
+--- a/Makefile
++++ b/Makefile
+@@ -29,30 +29,12 @@
+ #  US6,570,884, US6,115,776, and US6,327,625.
+ ################################################################################
+ 
+-KFLAG := 2$(shell uname -r | sed -ne 's/^2\.[4]\..*/4/p')x
+-
+-all: clean modules install
+-
+-modules:
+-ifeq ($(KFLAG),24x)
+-	$(MAKE) -C src/ -f Makefile_linux24x modules
+-else
+-	$(MAKE) -C src/ modules
+-endif
++all:
++	$(MAKE) -C src/
+ 
+ clean:
+-ifeq ($(KFLAG),24x)
+-	$(MAKE) -C src/ -f Makefile_linux24x clean
+-else
+ 	$(MAKE) -C src/ clean
+-endif
+-
+-install:
+-ifeq ($(KFLAG),24x)
+-	$(MAKE) -C src/ -f Makefile_linux24x install
+-else
+-	$(MAKE) -C src/ install
+-endif
+-
+ 
++modules_install:
++	$(MAKE) -C src/ modules_install
+ 
+diff --git a/src/Makefile b/src/Makefile
+index 641a369..fab0ca4 100755
+--- a/src/Makefile
++++ b/src/Makefile
+@@ -36,55 +36,42 @@ CONFIG_ASPM = y
+ ENABLE_S5WOL = y
+ ENABLE_EEE = n
+ 
+-ifneq ($(KERNELRELEASE),)
+-	obj-m := r8168.o
+-	r8168-objs := r8168_n.o r8168_asf.o rtl_eeprom.o rtltool.o
+-	ifeq ($(ENABLE_REALWOW_SUPPORT), y)
+-	    r8168-objs += r8168_realwow.o
+-		EXTRA_CFLAGS += -DENABLE_REALWOW_SUPPORT
+-	endif
+-	ifeq ($(ENABLE_DASH_SUPPORT), y)
+-	    r8168-objs += r8168_dash.o
+-		EXTRA_CFLAGS += -DENABLE_DASH_SUPPORT
+-	endif
+-	EXTRA_CFLAGS += -DCONFIG_R8168_NAPI
+-	EXTRA_CFLAGS += -DCONFIG_R8168_VLAN
+-	ifeq ($(CONFIG_DOWN_SPEED_100), y)
+-		EXTRA_CFLAGS += -DCONFIG_DOWN_SPEED_100
+-	endif
+-	ifeq ($(CONFIG_ASPM), y)
+-		EXTRA_CFLAGS += -DCONFIG_ASPM
+-	endif
+-	ifeq ($(ENABLE_S5WOL), y)
+-		EXTRA_CFLAGS += -DENABLE_S5WOL
+-	endif
+-	ifeq ($(ENABLE_EEE), y)
+-		EXTRA_CFLAGS += -DENABLE_EEE
+-	endif
+-else
+-	BASEDIR := /lib/modules/$(shell uname -r)
+-	KERNELDIR ?= $(BASEDIR)/build
+-	PWD :=$(shell pwd)
+-	DRIVERDIR := $(shell find $(BASEDIR)/kernel/drivers/net -name realtek -type d)
+-	ifeq ($(DRIVERDIR),)
+-		DRIVERDIR := $(BASEDIR)/kernel/drivers/net
+-	endif
+-	RTKDIR := $(subst $(BASEDIR)/,,$(DRIVERDIR))
++SRC := $(shell pwd)
+ 
+-.PHONY: all
+-all: clean modules install
++obj-m := r8168.o
++r8168-objs := r8168_n.o r8168_asf.o rtl_eeprom.o rtltool.o
++ifeq ($(ENABLE_REALWOW_SUPPORT), y)
++    r8168-objs += r8168_realwow.o
++	EXTRA_CFLAGS += -DENABLE_REALWOW_SUPPORT
++endif
++ifeq ($(ENABLE_DASH_SUPPORT), y)
++    r8168-objs += r8168_dash.o
++	EXTRA_CFLAGS += -DENABLE_DASH_SUPPORT
++endif
++EXTRA_CFLAGS += -DCONFIG_R8168_NAPI
++EXTRA_CFLAGS += -DCONFIG_R8168_VLAN
++ifeq ($(CONFIG_DOWN_SPEED_100), y)
++	EXTRA_CFLAGS += -DCONFIG_DOWN_SPEED_100
++endif
++ifeq ($(CONFIG_ASPM), y)
++	EXTRA_CFLAGS += -DCONFIG_ASPM
++endif
++ifeq ($(ENABLE_S5WOL), y)
++	EXTRA_CFLAGS += -DENABLE_S5WOL
++endif
++ifeq ($(ENABLE_EEE), y)
++	EXTRA_CFLAGS += -DENABLE_EEE
++endif
+ 
+-.PHONY:modules
+-modules:
+-	$(MAKE) -C $(KERNELDIR) SUBDIRS=$(PWD) modules
++.PHONY:all
++all:
++	$(MAKE) -C $(KERNEL_SRC) M=$(SRC)
+ 
+ .PHONY:clean
+ clean:
+-	$(MAKE) -C $(KERNELDIR) SUBDIRS=$(PWD) clean
++	$(MAKE) -C $(KERNEL_SRC) M=$(SRC) clean
+ 
+-.PHONY:install
+-install:
+-	$(MAKE) -C $(KERNELDIR) SUBDIRS=$(PWD) INSTALL_MOD_DIR=$(RTKDIR) modules_install
+-
+-endif
++.PHONY:modules_install
++modules_install:
++	$(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
+ 
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-kernel/r8168/files/0002-r8168-8.040.00.tar.bz2 b/meta-amdfalconx86/recipes-kernel/r8168/files/0002-r8168-8.040.00.tar.bz2
new file mode 100644
index 00000000..baa3380c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/r8168/files/0002-r8168-8.040.00.tar.bz2
diff --git a/meta-amdfalconx86/recipes-kernel/r8168/r8168_8.040.00.bb b/meta-amdfalconx86/recipes-kernel/r8168/r8168_8.040.00.bb
new file mode 100644
index 00000000..4e9e14f2
--- /dev/null
+++ b/meta-amdfalconx86/recipes-kernel/r8168/r8168_8.040.00.bb
@@ -0,0 +1,13 @@
+DESCRIPTION = "This kernel module provides support for RealTek R8168 driver"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
+
+inherit module
+
+PR = "r0"
+PV = "8.040.00"
+
+SRC_URI = "file://0002-${PN}-${PV}.tar.bz2 \
+	   file://0001-r8168-adjust-Makefiles-for-Yocto-environment.patch \
+"
+
diff --git a/meta-amdfalconx86/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-amdgpu.patch b/meta-amdfalconx86/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-amdgpu.patch
new file mode 100644
index 00000000..d8d718f8
--- /dev/null
+++ b/meta-amdfalconx86/recipes-multimedia/gstreamer/gstreamer1.0-omx/0001-adjust-gstomx.conf-for-amdgpu.patch
@@ -0,0 +1,50 @@
+From 1091020cfd26089583d3f83f21c26bba88d5e8d0 Mon Sep 17 00:00:00 2001
+From: Arindam Nath <arindam.nath@amd.com>
+Date: Fri, 17 Apr 2015 18:26:10 +0530
+Subject: [PATCH 1/1] adjust gstomx.conf for amdgpu
+
+Signed-off-by: Arindam Nath <arindam.nath@amd.com>
+---
+ config/bellagio/gstomx.conf | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/config/bellagio/gstomx.conf b/config/bellagio/gstomx.conf
+index 78f8e7d..bc26507 100644
+--- a/config/bellagio/gstomx.conf
++++ b/config/bellagio/gstomx.conf
+@@ -10,11 +10,10 @@ hacks=event-port-settings-changed-ndata-parameter-swap;event-port-settings-chang
+ [omxh264dec]
+ type-name=GstOMXH264Dec
+ core-name=/usr/local/lib/libomxil-bellagio.so.0
+-component-name=OMX.st.video_decoder.avc
++component-name=OMX.mesa.video_decoder.avc
+ rank=256
+ in-port-index=0
+ out-port-index=1
+-hacks=event-port-settings-changed-ndata-parameter-swap;event-port-settings-changed-port-0-to-1
+ 
+ [omxmpeg4videoenc]
+ type-name=GstOMXMPEG4VideoEnc
+@@ -33,3 +32,19 @@ rank=0
+ in-port-index=0
+ out-port-index=1
+ hacks=event-port-settings-changed-ndata-parameter-swap
++
++[omxmpeg2dec]
++type-name=GstOMXMPEG2VideoDec
++core-name=/usr/local/lib/libomxil-bellagio.so.0
++component-name=OMX.mesa.video_decoder.mpeg2
++rank=256
++in-port-index=0
++out-port-index=1
++
++[omxh264enc]
++type-name=GstOMXH264Enc
++core-name=/usr/local/lib/libomxil-bellagio.so.0
++component-name=OMX.mesa.video_encoder.avc
++rank=256
++in-port-index=0
++out-port-index=1
+-- 
+1.9.1
+
diff --git a/meta-amdfalconx86/recipes-multimedia/gstreamer/gstreamer1.0-omx_git.bbappend b/meta-amdfalconx86/recipes-multimedia/gstreamer/gstreamer1.0-omx_git.bbappend
new file mode 100644
index 00000000..008a140c
--- /dev/null
+++ b/meta-amdfalconx86/recipes-multimedia/gstreamer/gstreamer1.0-omx_git.bbappend
@@ -0,0 +1,5 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI_append_amdfalconx86 += " \
+	   file://0001-adjust-gstomx.conf-for-amdgpu.patch \
+	  "